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module iuq_ic_miss_table(
input new_miss,
input miss_ci_l2,
input reld_r1_val_l2,
input r2_crit_qw_l2,
input ecc_err,
input ecc_err_ue,
input addr_match,
input iu2_flush,
input release_sm,
input miss_flushed_l2,
input miss_inval_l2,
input [0:5] miss_tid_sm_l2,
input last_data,
output [0:5] miss_tid_sm_d,
output reset_state,
output request_tag,
output write_dir_inval,
output write_dir_val,
output hold_tid,
output data_write,
output dir_write,
output load_tag,
output release_sm_hold
);
wire [1:23] miss_sm_pt;
// Example State Ordering for cacheable reloads
// 64B Cacheline, No Gaps : (2)(3)(3)(3)(3)(5) - Wait, Data, Data, Data, Data, CheckECC
// 64B Cacheline, Always Gaps : (2)(3)(2)(3)(2)(3)(2)(3)(5) - Wait, Data, Wait, Data, Wait, Data, Wait, Data, CheckECC
// similar pattern for 128B
/*
//table_start
?TABLE miss_sm LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET);
*INPUTS*=========================================*OUTPUTS*========================================*
| | |
| new_miss | miss_tid_sm_d |
| | | | |
| | | | reset_state |
| | | | | |
| | miss_ci_l2 | | | request_tag |
| | | reld_r1_val_l2 | | | | write_dir_inval |
| | | | r2_crit_qw_l2 | | | | | write_dir_val |
| | | | | ecc_err | | | | | | |
| | | | | | ecc_err_ue | | | | | | |
| | | | | | | | | | | | | |
| | | | | | | | | | | | | |
| | | | | | | addr_match | | | | | | |
| | | | | | | | iu2_flush | | | | | | hold_tid | -- this holds 1 tid and gates iu2
| | | | | | | | | release_sm | | | | | | | |
| | | | | | | | | | miss_flushed_l2 | | | | | | | |
| | | | | | | | | | | miss_inval_l2 | | | | | | | |
| | | | | | | | | | | | miss_tid_sm_l2 | | | | | | | |
| | | | | | | | | | | | | last_data | | | | | | | |
| | | | | | | | | | | | | | | | | | | | | data_write |
| | | | | | | | | | | | | | | | | | | | | | dir_write |
| | | | | | | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | | | | | load_tag |
| | | | | | | | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | | | | | | release_sm_hold |
| | | | | | | | | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | 012345 | | 012345 | | | | | | | | | |
*TYPE*===========================================+================================================+
| P P P P P P P P P P P PPPPPP P | PPPPPP P P P P P P P P P |
*OPTIMIZE*-------------------------------------->| AAAAAA A A A A B A A A A |
*TERMS*==========================================+================================================+
| 0 - - - - - - 0 - - - 100000 - | 100000 0 0 0 0 0 0 0 0 0 | -- In idle and stay in idle
| 1 - - - - - 0 0 - - - 100000 - | 001000 0 1 0 0 0 0 0 0 0 | -- In idle and we got a miss for my tag not CI and no match
| 1 - - - - - 1 0 0 - - 100000 - | 010000 0 0 0 0 0 0 0 0 0 | -- In Idle miss that matches a current tag's outstanding address
| 1 - - - - - 1 0 1 - - 100000 - | 100000 0 0 0 0 0 0 0 0 0 | -- In Idle miss that matches a current tag's outstanding address, release_sm
| - - - - - - - 1 - - - 100000 - | 100000 0 0 0 0 0 0 0 0 0 | -- Flush while in idle
| | |
| - - - - - - - 0 0 - - 010000 - | 010000 0 0 0 0 1 0 0 0 0 | -- (1) In WaitMiss no valid stay in WaitMiss
| - - - - - - - 0 1 - - 010000 - | 100000 0 0 0 0 1 0 0 0 0 | -- (1) In WaitMiss got a valid to another tag, release hold
| - - - - - - - 1 - - - 010000 - | 100000 0 0 0 0 1 0 0 0 0 | -- (1) In WaitMiss and flushed, go to idle
| | |
| - - 0 - - - - - - - - 001000 - | 001000 0 0 0 0 1 0 0 0 0 | -- (2) In Wait0 no valid to tag, stay in wait0
| - 0 1 - - - - - - - - 001000 - | 000100 0 0 0 0 1 0 0 0 0 | -- (2) In Wait0 Got a valid command and not CI
| - 1 1 - - - - - - - - 001000 - | 000010 0 0 0 0 1 0 0 0 0 | -- (2) In Wait0 Got a valid command and CI
| | |
| - - 0 1 - - - - - 0 0 000100 0 | 001000 0 0 1 0 1 1 1 1 0 | -- (3) In Data0 no valid, goto Wait1 - Crit QW
| - - 1 1 - - - - - 0 0 000100 0 | 000100 0 0 1 0 1 1 1 1 0 | -- (3) In Data0 valid, goto Data1 - Crit QW
| - - 0 0 - - - - - 0 0 000100 0 | 001000 0 0 1 0 1 1 1 0 0 | -- (3) In Data0 no valid, goto Wait1
| - - 1 0 - - - - - 0 0 000100 0 | 000100 0 0 1 0 1 1 1 0 0 | -- (3) In Data0 valid, goto Data1
| - - 0 - - - - - - 1 - 000100 0 | 001000 0 0 0 0 1 0 0 0 0 | -- (3) In Data0 no valid, goto Wait1; Flushed
| - - 1 - - - - - - 1 - 000100 0 | 000100 0 0 0 0 1 0 0 0 0 | -- (3) In Data0 valid, goto Data1; Flushed
| - - 0 0 - - - - - 0 1 000100 0 | 001000 0 0 0 0 1 0 0 0 0 | -- (3) In Data0 no valid, goto Wait1; Invalidated - don't cache
| - - 1 0 - - - - - 0 1 000100 0 | 000100 0 0 0 0 1 0 0 0 0 | -- (3) In Data0 valid, goto Data1; Invalidated - don't cache
| - - 0 1 - - - - - 0 1 000100 0 | 001000 0 0 0 0 1 0 0 1 0 | -- (3) In Data0 no valid, goto Wait1; Invalidated - don't cache
| - - 1 1 - - - - - 0 1 000100 0 | 000100 0 0 0 0 1 0 0 1 0 | -- (3) In Data0 valid, goto Data1; Invalidated - don't cache
| | |
| - - 0 1 0 0 - - - 0 0 000100 1 | 000001 0 0 0 1 0 1 0 1 1 | -- (3) In Data3/7 goto CheckECC - Crit QW
| - - 0 0 0 0 - - - 0 0 000100 1 | 000001 0 0 0 1 0 1 0 0 1 | -- (3) In Data3/7 goto CheckECC
| - - 0 1 1 - - - - 0 0 000100 1 | 000001 0 0 0 0 0 1 0 1 1 | -- (3) In Data3/7 ECC don't write dir; goto CheckECC - Crit QW
| - - 0 0 1 - - - - 0 0 000100 1 | 000001 0 0 0 0 0 1 0 0 1 | -- (3) In Data3/7 ECC don't write dir; goto CheckECC
| - - 0 1 - 1 - - - 0 0 000100 1 | 000001 0 0 0 0 0 1 0 1 1 | -- (3) In Data3/7 UE don't write dir; goto CheckECC - Crit QW
| - - 0 0 - 1 - - - 0 0 000100 1 | 000001 0 0 0 0 0 1 0 0 1 | -- (3) In Data3/7 UE don't write dir; goto CheckECC
| - - 0 - - - - - - 1 - 000100 1 | 000001 0 0 0 0 0 0 0 0 1 | -- (3) In Data3/7 goto CheckECC; Flushed
| - - 0 0 - - - - - 0 1 000100 1 | 000001 0 0 0 0 0 0 0 0 1 | -- (3) In Data3/7 goto CheckECC; Invalidated
| - - 0 1 - - - - - 0 1 000100 1 | 000001 0 0 0 0 0 0 0 1 1 | -- (3) In Data3/7 goto CheckECC; Invalidated
| | |
| - - - - - - - - - 0 - 000010 - | 000001 0 0 0 0 0 0 0 1 1 | -- (4) In Load data to IU2
| - - - - - - - - - 1 - 000010 - | 000001 0 0 0 0 0 0 0 0 1 | -- (4) In Load data to IU2; Flushed
| | |
| - - - - 0 0 - - - - - 000001 - | 100000 1 0 0 0 0 0 0 0 1 | -- (5) In CheckECC, no error; go to idle
| - - - - 0 1 - - - - - 000001 - | 100000 1 0 0 0 0 0 0 0 1 | -- (5) In CheckECC, uncorrectable error; go to idle
| - - - - 1 - - - - - - 000001 - | 001000 0 0 0 0 0 0 0 0 0 | -- (5) In CheckECC, correctable error; go to wait state
*END*============================================+================================================+
?TABLE END miss_sm;
//table_end
*/
//assign_start
assign miss_sm_pt[1] =
(({ miss_flushed_l2 , miss_inval_l2 ,
miss_tid_sm_l2[3] , last_data
}) === 4'b0010);
assign miss_sm_pt[2] =
(({ reld_r1_val_l2 , miss_tid_sm_l2[3] ,
last_data }) === 3'b010);
assign miss_sm_pt[3] =
(({ miss_tid_sm_l2[3] , last_data
}) === 2'b10);
assign miss_sm_pt[4] =
(({ ecc_err , ecc_err_ue ,
miss_flushed_l2 , miss_inval_l2 ,
miss_tid_sm_l2[3] , last_data
}) === 6'b000011);
assign miss_sm_pt[5] =
(({ miss_tid_sm_l2[3] , last_data
}) === 2'b11);
assign miss_sm_pt[6] =
(({ iu2_flush , miss_tid_sm_l2[2] ,
miss_tid_sm_l2[3] , miss_tid_sm_l2[4] ,
miss_tid_sm_l2[5] }) === 5'b10000);
assign miss_sm_pt[7] =
(({ miss_tid_sm_l2[0] , miss_tid_sm_l2[3] ,
miss_tid_sm_l2[4] , miss_tid_sm_l2[5]
}) === 4'b0000);
assign miss_sm_pt[8] =
(({ ecc_err , miss_tid_sm_l2[5]
}) === 2'b01);
assign miss_sm_pt[9] =
(({ ecc_err , miss_tid_sm_l2[5]
}) === 2'b11);
assign miss_sm_pt[10] =
(({ miss_flushed_l2 , miss_tid_sm_l2[4]
}) === 2'b01);
assign miss_sm_pt[11] =
(({ miss_tid_sm_l2[4] }) === 1'b1);
assign miss_sm_pt[12] =
(({ miss_flushed_l2 , miss_inval_l2 ,
miss_tid_sm_l2[3] }) === 3'b001);
assign miss_sm_pt[13] =
(({ r2_crit_qw_l2 , miss_flushed_l2 ,
miss_tid_sm_l2[3] }) === 3'b101);
assign miss_sm_pt[14] =
(({ reld_r1_val_l2 , miss_tid_sm_l2[3]
}) === 2'b11);
assign miss_sm_pt[15] =
(({ reld_r1_val_l2 , miss_tid_sm_l2[2]
}) === 2'b01);
assign miss_sm_pt[16] =
(({ miss_ci_l2 , reld_r1_val_l2 ,
miss_tid_sm_l2[2] }) === 3'b011);
assign miss_sm_pt[17] =
(({ miss_ci_l2 , reld_r1_val_l2 ,
miss_tid_sm_l2[2] }) === 3'b111);
assign miss_sm_pt[18] =
(({ iu2_flush , release_sm ,
miss_tid_sm_l2[1] }) === 3'b001);
assign miss_sm_pt[19] =
(({ release_sm , miss_tid_sm_l2[1]
}) === 2'b11);
assign miss_sm_pt[20] =
(({ new_miss , addr_match ,
iu2_flush , release_sm ,
miss_tid_sm_l2[0] }) === 5'b11001);
assign miss_sm_pt[21] =
(({ addr_match , release_sm ,
miss_tid_sm_l2[0] }) === 3'b111);
assign miss_sm_pt[22] =
(({ new_miss , addr_match ,
iu2_flush , miss_tid_sm_l2[0]
}) === 4'b1001);
assign miss_sm_pt[23] =
(({ new_miss , miss_tid_sm_l2[0]
}) === 2'b01);
assign miss_tid_sm_d[0] =
(miss_sm_pt[6] | miss_sm_pt[8]
| miss_sm_pt[19] | miss_sm_pt[21]
| miss_sm_pt[23]);
assign miss_tid_sm_d[1] =
(miss_sm_pt[18] | miss_sm_pt[20]
);
assign miss_tid_sm_d[2] =
(miss_sm_pt[2] | miss_sm_pt[9]
| miss_sm_pt[15] | miss_sm_pt[22]
);
assign miss_tid_sm_d[3] =
(miss_sm_pt[14] | miss_sm_pt[16]
);
assign miss_tid_sm_d[4] =
(miss_sm_pt[17]);
assign miss_tid_sm_d[5] =
(miss_sm_pt[5] | miss_sm_pt[11]
);
assign reset_state =
(miss_sm_pt[8]);
assign request_tag =
(miss_sm_pt[22]);
assign write_dir_inval =
(miss_sm_pt[1]);
assign write_dir_val =
(miss_sm_pt[4]);
assign hold_tid =
(miss_sm_pt[3] | miss_sm_pt[7]
);
assign data_write =
(miss_sm_pt[12]);
assign dir_write =
(miss_sm_pt[1]);
assign load_tag =
(miss_sm_pt[10] | miss_sm_pt[13]
);
assign release_sm_hold =
(miss_sm_pt[5] | miss_sm_pt[8]
| miss_sm_pt[11]);
//assign_end
endmodule |
module rv_cmpitag(
vld,
itag,
vld_ary,
itag_ary,
abort,
hit_clear,
hit_abort
);
`include "tri_a2o.vh"
parameter q_itag_busses_g = 7;
input [0:`THREADS-1] vld;
input [0:`ITAG_SIZE_ENC-1] itag;
input [0:(q_itag_busses_g*`THREADS)-1] vld_ary;
input [0:(q_itag_busses_g*`ITAG_SIZE_ENC)-1] itag_ary;
input [0:q_itag_busses_g-1] abort;
output hit_clear;
output hit_abort;
wire [0:7] valid;
wire [0:7] itag_xor[0:7];
wire [0:3] itag_andl10_b;
wire [0:3] itag_andl11_b;
wire [0:3] itag_andl12_b;
wire [0:3] itag_andl13_b;
wire [0:3] itag_andl14_b;
wire [0:3] itag_andl15_b;
wire [0:3] itag_andl16_b;
wire [0:3] itag_andl17_b;
wire [0:1] itag_andl20;
wire [0:1] itag_andl21;
wire [0:1] itag_andl22;
wire [0:1] itag_andl23;
wire [0:1] itag_andl24;
wire [0:1] itag_andl25;
wire [0:1] itag_andl26;
wire [0:1] itag_andl27;
wire [0:7] itagc_andl3_b;
wire [0:3] itagc_orl4;
wire [0:1] itagc_orl5_b;
wire itagc_orl6;
wire [0:7] itaga_andl3_b;
wire [0:3] itaga_orl4;
wire [0:1] itaga_orl5_b;
wire itaga_orl6;
wire [0:7] itag_abort;
wire [0:7] itag_abort_b;
(* analysis_not_referenced="true" *)
wire unused;
//-------------------------------------------------------------------------------------------------------
// Total Logic: XOR + 6 levels
//-------------------------------------------------------------------------------------------------------
generate
begin : xhdl0
genvar n;
for (n = 0; n <= 5; n = n + 1)
begin : q_valid_gen
assign valid[n] = |(vld_ary[n*`THREADS:n*`THREADS+`THREADS-1] & vld);
assign itag_xor[n] = {~(itag ^ itag_ary[n*`ITAG_SIZE_ENC:n*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[n]};
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// XOR ITAG Compares
//-------------------------------------------------------------------------------------------------------
assign itag_abort[0:5] = abort[0:5];
generate
if (q_itag_busses_g == 6)
begin : l1xor_gen6
assign itag_xor[6] = {8{1'b0}};
assign itag_xor[7] = {8{1'b0}};
assign valid[6] = 1'b0;
assign valid[7] = 1'b0;
assign itag_abort[6] = 1'b0;
assign itag_abort[7] = 1'b0;
end
endgenerate
generate
if (q_itag_busses_g == 7)
begin : l1xor_gen7
assign itag_xor[6] = {~(itag ^ itag_ary[6*`ITAG_SIZE_ENC:6*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[6]};
assign itag_xor[7] = {8{1'b0}};
assign valid[6] = |(vld_ary[6*`THREADS:6*`THREADS+`THREADS-1] & vld);
assign valid[7] = 1'b0;
assign itag_abort[6] = abort[6];
assign itag_abort[7] = 1'b0;
assign unused = valid[7] ;
end
endgenerate
generate
if (q_itag_busses_g == 8)
begin : l1xor_gen8
assign itag_xor[6] = {~(itag ^ itag_ary[6*`ITAG_SIZE_ENC:6*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[6]};
assign itag_xor[7] = {~(itag ^ itag_ary[7*`ITAG_SIZE_ENC:7*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[7]};
assign valid[6] = |(vld_ary[6*`THREADS:6*`THREADS+`THREADS-1] & vld);
assign valid[7] = |(vld_ary[7*`THREADS:7*`THREADS+`THREADS-1] & vld);
assign itag_abort[6] = abort[6];
assign itag_abort[7] = abort[7];
end
endgenerate
assign itag_abort_b = ~itag_abort;
//-------------------------------------------------------------------------------------------------------
// AND Tree. 8 groups of 8, 3 levels each
//-------------------------------------------------------------------------------------------------------
// Level 1
assign itag_andl10_b[0] = ~(itag_xor[0][0] & itag_xor[0][1]);
assign itag_andl10_b[1] = ~(itag_xor[0][2] & itag_xor[0][3]);
assign itag_andl10_b[2] = ~(itag_xor[0][4] & itag_xor[0][5]);
assign itag_andl10_b[3] = ~(itag_xor[0][6] & itag_xor[0][7]);
assign itag_andl11_b[0] = ~(itag_xor[1][0] & itag_xor[1][1]);
assign itag_andl11_b[1] = ~(itag_xor[1][2] & itag_xor[1][3]);
assign itag_andl11_b[2] = ~(itag_xor[1][4] & itag_xor[1][5]);
assign itag_andl11_b[3] = ~(itag_xor[1][6] & itag_xor[1][7]);
assign itag_andl12_b[0] = ~(itag_xor[2][0] & itag_xor[2][1]);
assign itag_andl12_b[1] = ~(itag_xor[2][2] & itag_xor[2][3]);
assign itag_andl12_b[2] = ~(itag_xor[2][4] & itag_xor[2][5]);
assign itag_andl12_b[3] = ~(itag_xor[2][6] & itag_xor[2][7]);
assign itag_andl13_b[0] = ~(itag_xor[3][0] & itag_xor[3][1]);
assign itag_andl13_b[1] = ~(itag_xor[3][2] & itag_xor[3][3]);
assign itag_andl13_b[2] = ~(itag_xor[3][4] & itag_xor[3][5]);
assign itag_andl13_b[3] = ~(itag_xor[3][6] & itag_xor[3][7]);
assign itag_andl14_b[0] = ~(itag_xor[4][0] & itag_xor[4][1]);
assign itag_andl14_b[1] = ~(itag_xor[4][2] & itag_xor[4][3]);
assign itag_andl14_b[2] = ~(itag_xor[4][4] & itag_xor[4][5]);
assign itag_andl14_b[3] = ~(itag_xor[4][6] & itag_xor[4][7]);
assign itag_andl15_b[0] = ~(itag_xor[5][0] & itag_xor[5][1]);
assign itag_andl15_b[1] = ~(itag_xor[5][2] & itag_xor[5][3]);
assign itag_andl15_b[2] = ~(itag_xor[5][4] & itag_xor[5][5]);
assign itag_andl15_b[3] = ~(itag_xor[5][6] & itag_xor[5][7]);
assign itag_andl16_b[0] = ~(itag_xor[6][0] & itag_xor[6][1]);
assign itag_andl16_b[1] = ~(itag_xor[6][2] & itag_xor[6][3]);
assign itag_andl16_b[2] = ~(itag_xor[6][4] & itag_xor[6][5]);
assign itag_andl16_b[3] = ~(itag_xor[6][6] & itag_xor[6][7]);
assign itag_andl17_b[0] = ~(itag_xor[7][0] & itag_xor[7][1]);
assign itag_andl17_b[1] = ~(itag_xor[7][2] & itag_xor[7][3]);
assign itag_andl17_b[2] = ~(itag_xor[7][4] & itag_xor[7][5]);
assign itag_andl17_b[3] = ~(itag_xor[7][6] & itag_xor[7][7]);
// Level 2
assign itag_andl20[0] = ~(itag_andl10_b[0] | itag_andl10_b[1]);
assign itag_andl20[1] = ~(itag_andl10_b[2] | itag_andl10_b[3]);
assign itag_andl21[0] = ~(itag_andl11_b[0] | itag_andl11_b[1]);
assign itag_andl21[1] = ~(itag_andl11_b[2] | itag_andl11_b[3]);
assign itag_andl22[0] = ~(itag_andl12_b[0] | itag_andl12_b[1]);
assign itag_andl22[1] = ~(itag_andl12_b[2] | itag_andl12_b[3]);
assign itag_andl23[0] = ~(itag_andl13_b[0] | itag_andl13_b[1]);
assign itag_andl23[1] = ~(itag_andl13_b[2] | itag_andl13_b[3]);
assign itag_andl24[0] = ~(itag_andl14_b[0] | itag_andl14_b[1]);
assign itag_andl24[1] = ~(itag_andl14_b[2] | itag_andl14_b[3]);
assign itag_andl25[0] = ~(itag_andl15_b[0] | itag_andl15_b[1]);
assign itag_andl25[1] = ~(itag_andl15_b[2] | itag_andl15_b[3]);
assign itag_andl26[0] = ~(itag_andl16_b[0] | itag_andl16_b[1]);
assign itag_andl26[1] = ~(itag_andl16_b[2] | itag_andl16_b[3]);
assign itag_andl27[0] = ~(itag_andl17_b[0] | itag_andl17_b[1]);
assign itag_andl27[1] = ~(itag_andl17_b[2] | itag_andl17_b[3]);
// Level 3 - sneak in the abort here
assign itagc_andl3_b[0] = ~(itag_andl20[0] & itag_andl20[1] & itag_abort_b[0]);
assign itagc_andl3_b[1] = ~(itag_andl21[0] & itag_andl21[1] & itag_abort_b[1]);
assign itagc_andl3_b[2] = ~(itag_andl22[0] & itag_andl22[1] & itag_abort_b[2]);
assign itagc_andl3_b[3] = ~(itag_andl23[0] & itag_andl23[1] & itag_abort_b[3]);
assign itagc_andl3_b[4] = ~(itag_andl24[0] & itag_andl24[1] & itag_abort_b[4]);
assign itagc_andl3_b[5] = ~(itag_andl25[0] & itag_andl25[1] & itag_abort_b[5]);
assign itagc_andl3_b[6] = ~(itag_andl26[0] & itag_andl26[1] & itag_abort_b[6]);
assign itagc_andl3_b[7] = ~(itag_andl27[0] & itag_andl27[1] & itag_abort_b[7]);
// Level 3 - sneak in the abort here
assign itaga_andl3_b[0] = ~(itag_andl20[0] & itag_andl20[1] & itag_abort[0]);
assign itaga_andl3_b[1] = ~(itag_andl21[0] & itag_andl21[1] & itag_abort[1]);
assign itaga_andl3_b[2] = ~(itag_andl22[0] & itag_andl22[1] & itag_abort[2]);
assign itaga_andl3_b[3] = ~(itag_andl23[0] & itag_andl23[1] & itag_abort[3]);
assign itaga_andl3_b[4] = ~(itag_andl24[0] & itag_andl24[1] & itag_abort[4]);
assign itaga_andl3_b[5] = ~(itag_andl25[0] & itag_andl25[1] & itag_abort[5]);
assign itaga_andl3_b[6] = ~(itag_andl26[0] & itag_andl26[1] & itag_abort[6]);
assign itaga_andl3_b[7] = ~(itag_andl27[0] & itag_andl27[1] & itag_abort[7]);
//-------------------------------------------------------------------------------------------------------
// CLEAR OR Tree. 8 groups. Coming in inverted. 3 more levels
//-------------------------------------------------------------------------------------------------------
// Level 4
assign itagc_orl4[0] = ~(itagc_andl3_b[0] & itagc_andl3_b[1]);
assign itagc_orl4[1] = ~(itagc_andl3_b[2] & itagc_andl3_b[3]);
assign itagc_orl4[2] = ~(itagc_andl3_b[4] & itagc_andl3_b[5]);
assign itagc_orl4[3] = ~(itagc_andl3_b[6] & itagc_andl3_b[7]);
// Level 5
assign itagc_orl5_b[0] = ~(itagc_orl4[0] | itagc_orl4[1]);
assign itagc_orl5_b[1] = ~(itagc_orl4[2] | itagc_orl4[3]);
// Level 6
assign itagc_orl6 = ~(itagc_orl5_b[0] & itagc_orl5_b[1]);
assign hit_clear = itagc_orl6;
//-------------------------------------------------------------------------------------------------------
// ABORT OR Tree. 8 groups. Coming in inverted. 3 more levels
//-------------------------------------------------------------------------------------------------------
// Level 4
assign itaga_orl4[0] = ~(itaga_andl3_b[0] & itaga_andl3_b[1]);
assign itaga_orl4[1] = ~(itaga_andl3_b[2] & itaga_andl3_b[3]);
assign itaga_orl4[2] = ~(itaga_andl3_b[4] & itaga_andl3_b[5]);
assign itaga_orl4[3] = ~(itaga_andl3_b[6] & itaga_andl3_b[7]);
// Level 5
assign itaga_orl5_b[0] = ~(itaga_orl4[0] | itaga_orl4[1]);
assign itaga_orl5_b[1] = ~(itaga_orl4[2] | itaga_orl4[3]);
// Level 6
assign itaga_orl6 = ~(itaga_orl5_b[0] & itaga_orl5_b[1]);
assign hit_abort = itaga_orl6;
endmodule // rv_cmpitag |
module lq_agen_csmuxe(
sum_0,
sum_1,
ci_b,
sum
);
input [0:3] sum_0; // after xor
input [0:3] sum_1;
input ci_b;
output [0:3] sum;
wire [0:3] sum0_b;
wire [0:3] sum1_b;
wire int_ci;
wire int_ci_t;
wire int_ci_b;
//assign int_ci = (~ci_b);
tri_inv int_ci_0 (.y(int_ci), .a(ci_b));
//assign int_ci_t = (~ci_b);
tri_inv int_ci_t_0 (.y(int_ci_t), .a(ci_b));
//assign int_ci_b = (~int_ci_t);
tri_inv int_ci_b_0 (.y(int_ci_b), .a(int_ci_t));
//assign sum0_b[0] = (~(sum_0[0] & int_ci_b));
tri_nand2 #(.WIDTH(4)) sum0_b_0 (.y(sum0_b[0:3]), .a(sum_0[0:3]), .b({4{int_ci_b}}));
//assign sum1_b[0] = (~(sum_1[0] & int_ci));
tri_nand2 #(.WIDTH(4)) sum1_b_0 (.y(sum1_b[0:3]), .a(sum_1[0:3]), .b({4{int_ci}}));
//assign sum[0] = (~(sum0_b[0] & sum1_b[0]));
tri_nand2 #(.WIDTH(4)) sum0 (.y(sum[0:3]), .a(sum0_b[0:3]), .b(sum1_b[0:3]));
endmodule |
module pcq_clks_ctrl(
// Include model build parameters
`include "tri_a2o.vh"
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input rtim_sl_thold_6,
input func_sl_thold_6,
input func_nsl_thold_6,
input ary_nsl_thold_6,
input sg_6,
input fce_6,
input gsd_test_enable_dc,
input gsd_test_acmode_dc,
input ccflush_dc,
input ccenable_dc,
input lbist_en_dc,
input lbist_ip_dc,
input rg_ck_fast_xstop,
input ct_ck_pm_ccflush_disable,
input ct_ck_pm_raise_tholds,
input [0:8] scan_type_dc,
// --Thold + control outputs to the units
output ccflush_out_dc,
output gptr_sl_thold_5,
output time_sl_thold_5,
output repr_sl_thold_5,
output cfg_sl_thold_5,
output cfg_slp_sl_thold_5,
output abst_sl_thold_5,
output abst_slp_sl_thold_5,
output regf_sl_thold_5,
output regf_slp_sl_thold_5,
output func_sl_thold_5,
output func_slp_sl_thold_5,
output func_nsl_thold_5,
output func_slp_nsl_thold_5,
output ary_nsl_thold_5,
output ary_slp_nsl_thold_5,
output rtim_sl_thold_5,
output sg_5,
output fce_5
);
//=====================================================================
// Signal Declarations
//=====================================================================
// Scan ring select decodes for scan_type_dc vector
parameter SCANTYPE_SIZE = 9; // Use bits 0:8 of scan_type vector
parameter SCANTYPE_FUNC = 0;
parameter SCANTYPE_MODE = 1;
parameter SCANTYPE_CCFG = 2;
parameter SCANTYPE_GPTR = 2;
parameter SCANTYPE_REGF = 3;
parameter SCANTYPE_FUSE = 3;
parameter SCANTYPE_LBST = 4;
parameter SCANTYPE_ABST = 5;
parameter SCANTYPE_REPR = 6;
parameter SCANTYPE_TIME = 7;
parameter SCANTYPE_BNDY = 8;
parameter SCANTYPE_FARY = 9;
wire fast_xstop_gated_staged;
wire fce_in;
wire sg_in;
wire ary_nsl_thold;
wire func_nsl_thold;
wire rtim_sl_thold;
wire func_sl_thold;
wire gptr_sl_thold_in;
wire time_sl_thold_in;
wire repr_sl_thold_in;
wire rtim_sl_thold_in;
wire cfg_run_sl_thold_in;
wire cfg_slp_sl_thold_in;
wire abst_run_sl_thold_in;
wire abst_slp_sl_thold_in;
wire regf_run_sl_thold_in;
wire regf_slp_sl_thold_in;
wire func_run_sl_thold_in;
wire func_slp_sl_thold_in;
wire func_run_nsl_thold_in;
wire func_slp_nsl_thold_in;
wire ary_run_nsl_thold_in;
wire ary_slp_nsl_thold_in;
wire pm_ccflush_disable_dc;
wire ccflush_out_dc_int;
wire testdc;
wire thold_overide_ctrl;
wire [0:SCANTYPE_SIZE-1] scan_type_b;
// Get rid of sinkless net messages
// synopsys translate_off
(* analysis_not_referenced="true" *)
// synopsys translate_on
wire unused_signals;
assign unused_signals = (scan_type_b[2] | scan_type_b[4] | (|scan_type_b[6:8]) | lbist_ip_dc);
//!! Bugspray Include: pcq_clks_ctrl;
//=====================================================================
// Clock Control Logic
//=====================================================================
// detect test dc mode
assign testdc = gsd_test_enable_dc & (~gsd_test_acmode_dc);
// enable sg/fce before latching
assign sg_in = sg_6 & ccenable_dc;
assign fce_in = fce_6 & ccenable_dc;
// scan chain type
assign scan_type_b = ({SCANTYPE_SIZE {sg_in}} & (~scan_type_dc));
// setup for xx_thold_6 inputs
assign thold_overide_ctrl = fast_xstop_gated_staged & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc);
assign rtim_sl_thold = rtim_sl_thold_6;
assign func_sl_thold = func_sl_thold_6 | thold_overide_ctrl;
assign func_nsl_thold = func_nsl_thold_6 | thold_overide_ctrl;
assign ary_nsl_thold = ary_nsl_thold_6 | thold_overide_ctrl;
// setup for plat flush control signals
// Active when power_management enabled (PM_Sleep_enable or PM_RVW_enable active)
// If plats were in flush mode, forces plats to be clocked again for power-savings.
assign pm_ccflush_disable_dc = ct_ck_pm_ccflush_disable;
assign ccflush_out_dc_int = ccflush_dc & ((~pm_ccflush_disable_dc) | lbist_en_dc | testdc);
assign ccflush_out_dc = ccflush_out_dc_int;
// OR and MUX of thold signals
// scan only: stop if not scanning, not part of LBIST, hence no sg_in here
assign gptr_sl_thold_in = func_sl_thold | (~scan_type_dc[SCANTYPE_GPTR]) | (~ccenable_dc);
// scan only: stop if not scanning, not part of LBIST, hence no sg_in here
assign time_sl_thold_in = func_sl_thold | (~scan_type_dc[SCANTYPE_TIME]) | (~ccenable_dc);
// scan only: stop if not scanning, not part of LBIST, hence no sg_in here
assign repr_sl_thold_in = func_sl_thold | (~scan_type_dc[SCANTYPE_REPR]) | (~ccenable_dc);
assign cfg_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_MODE] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
assign cfg_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_MODE];
assign abst_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_ABST] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
assign abst_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_ABST];
assign regf_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_REGF] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
assign regf_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_REGF];
assign func_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_FUNC] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
assign func_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_FUNC];
assign func_run_nsl_thold_in = func_nsl_thold | (ct_ck_pm_raise_tholds & (~fce_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
assign func_slp_nsl_thold_in = func_nsl_thold;
assign ary_run_nsl_thold_in = ary_nsl_thold | (ct_ck_pm_raise_tholds & (~fce_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
assign ary_slp_nsl_thold_in = ary_nsl_thold;
assign rtim_sl_thold_in = rtim_sl_thold;
// PLAT staging/redrive
tri_plat #(.WIDTH(1)) fast_stop_staging(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc_int),
.din(rg_ck_fast_xstop),
.q(fast_xstop_gated_staged)
);
tri_plat #(.WIDTH(2)) sg_fce_plat(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc_int),
.din({sg_in, fce_in}),
.q ({sg_5, fce_5 })
);
tri_plat #(.WIDTH(16)) thold_plat(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc_int),
.din({gptr_sl_thold_in, time_sl_thold_in, repr_sl_thold_in, cfg_run_sl_thold_in,
cfg_slp_sl_thold_in, abst_run_sl_thold_in, abst_slp_sl_thold_in, regf_run_sl_thold_in,
regf_slp_sl_thold_in, func_run_sl_thold_in, func_slp_sl_thold_in, func_run_nsl_thold_in,
func_slp_nsl_thold_in, ary_run_nsl_thold_in, ary_slp_nsl_thold_in, rtim_sl_thold_in}),
.q ({gptr_sl_thold_5, time_sl_thold_5, repr_sl_thold_5, cfg_sl_thold_5,
cfg_slp_sl_thold_5, abst_sl_thold_5, abst_slp_sl_thold_5, regf_sl_thold_5,
regf_slp_sl_thold_5, func_sl_thold_5, func_slp_sl_thold_5, func_nsl_thold_5,
func_slp_nsl_thold_5, ary_nsl_thold_5, ary_slp_nsl_thold_5, rtim_sl_thold_5})
);
endmodule |
module fu_alg_add(
vdd,
gnd,
f_byp_alg_ex2_b_expo,
f_byp_alg_ex2_a_expo,
f_byp_alg_ex2_c_expo,
ex2_sel_special_b,
ex2_bsha_6_o,
ex2_bsha_7_o,
ex2_bsha_8_o,
ex2_bsha_9_o,
ex2_bsha_neg_o,
ex2_sh_ovf,
ex2_sh_unf_x,
ex2_lvl1_shdcd000_b,
ex2_lvl1_shdcd001_b,
ex2_lvl1_shdcd002_b,
ex2_lvl1_shdcd003_b,
ex2_lvl2_shdcd000,
ex2_lvl2_shdcd004,
ex2_lvl2_shdcd008,
ex2_lvl2_shdcd012,
ex2_lvl3_shdcd000,
ex2_lvl3_shdcd016,
ex2_lvl3_shdcd032,
ex2_lvl3_shdcd048,
ex2_lvl3_shdcd064,
ex2_lvl3_shdcd080,
ex2_lvl3_shdcd096,
ex2_lvl3_shdcd112,
ex2_lvl3_shdcd128,
ex2_lvl3_shdcd144,
ex2_lvl3_shdcd160,
ex2_lvl3_shdcd176,
ex2_lvl3_shdcd192,
ex2_lvl3_shdcd208,
ex2_lvl3_shdcd224,
ex2_lvl3_shdcd240
);
inout vdd;
inout gnd;
input [1:13] f_byp_alg_ex2_b_expo;
input [1:13] f_byp_alg_ex2_a_expo;
input [1:13] f_byp_alg_ex2_c_expo;
input ex2_sel_special_b;
output ex2_bsha_6_o;
output ex2_bsha_7_o;
output ex2_bsha_8_o;
output ex2_bsha_9_o;
output ex2_bsha_neg_o;
output ex2_sh_ovf;
output ex2_sh_unf_x;
output ex2_lvl1_shdcd000_b;
output ex2_lvl1_shdcd001_b;
output ex2_lvl1_shdcd002_b;
output ex2_lvl1_shdcd003_b;
output ex2_lvl2_shdcd000;
output ex2_lvl2_shdcd004;
output ex2_lvl2_shdcd008;
output ex2_lvl2_shdcd012;
output ex2_lvl3_shdcd000; // 0000 +000
output ex2_lvl3_shdcd016; // 0001 +016
output ex2_lvl3_shdcd032; // 0010 +032
output ex2_lvl3_shdcd048; // 0011 +048
output ex2_lvl3_shdcd064; // 0100 +064
output ex2_lvl3_shdcd080; // 0101 +080
output ex2_lvl3_shdcd096; // 0110 +096
output ex2_lvl3_shdcd112; // 0111 +112
output ex2_lvl3_shdcd128; // 1000 +128
output ex2_lvl3_shdcd144; // 1001 +144
output ex2_lvl3_shdcd160; // 1010 +160
output ex2_lvl3_shdcd176; // 1011
output ex2_lvl3_shdcd192; // 1100 -064
output ex2_lvl3_shdcd208; // 1101 -048
output ex2_lvl3_shdcd224; // 1110 -032
output ex2_lvl3_shdcd240; // 1111 -016
//-----------------------------------------------------------------
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [2:14] ex2_bsha_sim_c;
wire [1:13] ex2_bsha_sim_p;
wire [2:13] ex2_bsha_sim_g;
wire [1:13] ex2_bsha_sim;
wire [1:13] ex2_b_expo_b;
wire [2:13] ex2_a_expo_b;
wire [2:13] ex2_c_expo_b;
wire ex2_bsha_neg;
wire ex2_sh_ovf_b;
wire [1:13] ex2_alg_sx;
(* analysis_not_referenced="<0:0>TRUE" *)
wire [0:12] ex2_alg_cx;
wire [1:12] ex2_alg_add_p;
wire [2:12] ex2_alg_add_g_b;
wire [2:11] ex2_alg_add_t_b;
wire ex2_bsha_6_b;
wire ex2_bsha_7_b;
wire ex2_bsha_8_b;
wire ex2_bsha_9_b;
wire ex2_67_dcd00_b;
wire ex2_67_dcd01_b;
wire ex2_67_dcd10_b;
wire ex2_67_dcd11_b;
wire ex2_89_dcd00_b;
wire ex2_89_dcd01_b;
wire ex2_89_dcd10_b;
wire ex2_89_dcd11_b;
wire ex2_lv2_0pg0_b;
wire ex2_lv2_0pg1_b;
wire ex2_lv2_0pk0_b;
wire ex2_lv2_0pk1_b;
wire ex2_lv2_0pp0_b;
wire ex2_lv2_0pp1_b;
wire ex2_lv2_1pg0_b;
wire ex2_lv2_1pg1_b;
wire ex2_lv2_1pk0_b;
wire ex2_lv2_1pk1_b;
wire ex2_lv2_1pp0_b;
wire ex2_lv2_1pp1_b;
wire ex2_lv2_shdcd000;
wire ex2_lv2_shdcd004;
wire ex2_lv2_shdcd008;
wire ex2_lv2_shdcd012;
wire ex2_lvl2_shdcd000_b;
wire ex2_lvl2_shdcd004_b;
wire ex2_lvl2_shdcd008_b;
wire ex2_lvl2_shdcd012_b;
wire [7:10] ex2_alg_add_c_b;
wire ex2_g02_12;
wire ex2_g02_12_b;
wire ex2_bsha_13_b;
wire ex2_bsha_13;
wire ex2_bsha_12_b;
wire ex2_bsha_12;
wire ex2_lv2_ci11n_en_b;
wire ex2_lv2_ci11p_en_b;
wire ex2_lv2_ci11n_en;
wire ex2_lv2_ci11p_en;
wire ex2_g02_10;
wire ex2_t02_10;
wire ex2_g04_10_b;
wire ex2_lv2_g11_x;
wire ex2_lv2_g11_b;
wire ex2_lv2_g11;
wire ex2_lv2_k11_b;
wire ex2_lv2_k11;
wire ex2_lv2_p11_b;
wire ex2_lv2_p11;
wire ex2_lv2_p10_b;
wire ex2_lv2_p10;
wire ex2_g04_10;
wire ex2_g02_6;
wire ex2_g02_7;
wire ex2_g02_8;
wire ex2_g02_9;
wire ex2_t02_6;
wire ex2_t02_7;
wire ex2_t02_8;
wire ex2_t02_9;
wire ex2_g04_6_b;
wire ex2_g04_7_b;
wire ex2_g04_8_b;
wire ex2_g04_9_b;
wire ex2_t04_6_b;
wire ex2_t04_7_b;
wire ex2_t04_8_b;
wire ex2_t04_9_b;
wire ex2_g08_6;
wire ex2_g04_7;
wire ex2_g04_8;
wire ex2_g04_9;
wire ex2_t04_7;
wire ex2_t04_8;
wire ex2_t04_9;
wire ex2_bsha_6;
wire ex2_bsha_7;
wire ex2_bsha_8;
wire ex2_bsha_9;
wire ex2_g02_4;
wire ex2_g02_2;
wire ex2_t02_4;
wire ex2_t02_2;
wire ex2_g04_2_b;
wire ex2_t04_2_b;
wire ex2_ones_2t3_b;
wire ex2_ones_4t5_b;
wire ex2_ones_2t5;
wire ex2_ones_2t5_b;
wire ex2_zero_2_b;
wire ex2_zero_3_b;
wire ex2_zero_4_b;
wire ex2_zero_5;
wire ex2_zero_5_b;
wire ex2_zero_2t3;
wire ex2_zero_4t5;
wire ex2_zero_2t5_b;
wire pos_if_pco6;
wire pos_if_nco6;
wire pos_if_pco6_b;
wire pos_if_nco6_b;
wire unf_if_nco6_b;
wire unf_if_pco6_b;
wire ex2_g08_6_b;
wire ex2_bsha_pos;
wire ex2_bsha_6_i;
wire ex2_bsha_7_i;
wire ex2_bsha_8_i;
wire ex2_bsha_9_i;
wire [1:13] ex2_ack_s;
wire [1:12] ex2_ack_c;
//==##############################################################
//# map block attributes
//==##############################################################
//-----------------------------------------------------
// FOR simulation only : will not generate any logic
//-----------------------------------------------------
assign ex2_bsha_sim_p[1:12] = ex2_alg_sx[1:12] ^ ex2_alg_cx[1:12];
assign ex2_bsha_sim_p[13] = ex2_alg_sx[13];
assign ex2_bsha_sim_g[2:12] = ex2_alg_sx[2:12] & ex2_alg_cx[2:12];
assign ex2_bsha_sim_g[13] = tidn;
assign ex2_bsha_sim[1:13] = ex2_bsha_sim_p[1:13] ^ ex2_bsha_sim_c[2:14];
assign ex2_bsha_sim_c[14] = tidn;
assign ex2_bsha_sim_c[13] = ex2_bsha_sim_g[13] | (ex2_bsha_sim_p[13] & ex2_bsha_sim_c[14]);
assign ex2_bsha_sim_c[12] = ex2_bsha_sim_g[12] | (ex2_bsha_sim_p[12] & ex2_bsha_sim_c[13]);
assign ex2_bsha_sim_c[11] = ex2_bsha_sim_g[11] | (ex2_bsha_sim_p[11] & ex2_bsha_sim_c[12]);
assign ex2_bsha_sim_c[10] = ex2_bsha_sim_g[10] | (ex2_bsha_sim_p[10] & ex2_bsha_sim_c[11]);
assign ex2_bsha_sim_c[9] = ex2_bsha_sim_g[9] | (ex2_bsha_sim_p[9] & ex2_bsha_sim_c[10]);
assign ex2_bsha_sim_c[8] = ex2_bsha_sim_g[8] | (ex2_bsha_sim_p[8] & ex2_bsha_sim_c[9]);
assign ex2_bsha_sim_c[7] = ex2_bsha_sim_g[7] | (ex2_bsha_sim_p[7] & ex2_bsha_sim_c[8]);
assign ex2_bsha_sim_c[6] = ex2_bsha_sim_g[6] | (ex2_bsha_sim_p[6] & ex2_bsha_sim_c[7]);
assign ex2_bsha_sim_c[5] = ex2_bsha_sim_g[5] | (ex2_bsha_sim_p[5] & ex2_bsha_sim_c[6]);
assign ex2_bsha_sim_c[4] = ex2_bsha_sim_g[4] | (ex2_bsha_sim_p[4] & ex2_bsha_sim_c[5]);
assign ex2_bsha_sim_c[3] = ex2_bsha_sim_g[3] | (ex2_bsha_sim_p[3] & ex2_bsha_sim_c[4]);
assign ex2_bsha_sim_c[2] = ex2_bsha_sim_g[2] | (ex2_bsha_sim_p[2] & ex2_bsha_sim_c[3]);
//==##############################################################
//# ex2 logic
//==##############################################################
//==--------------------------------------
//== timing ? long-cut to make sha have correct meaning
//==--------------------------------------
// for MADD operations SHA = (Ea+Ec+!Eb) + 1 -bias + 56
// (Ea+Ec+!Eb) + 57 +!bias + 1
// (Ea+Ec+!Eb) + 58 +!bias
// 0_0011_1111_1111 bias = 1023
// 1_1100_0000_0000 !bias
// 11_1010 58
// -----------------------
// 1_1100_0011_1010 ( !bias + 58 )
//
// leading bit [1] is a sign bit, but the compressor creates bit 0.
// 13 bits should be enough to hold the entire result, therefore throw away bit 0.
assign ex2_a_expo_b[2:13] = (~f_byp_alg_ex2_a_expo[2:13]);
assign ex2_c_expo_b[2:13] = (~f_byp_alg_ex2_c_expo[2:13]);
assign ex2_b_expo_b[1:13] = (~f_byp_alg_ex2_b_expo[1:13]);
assign ex2_ack_s[1] = (~(f_byp_alg_ex2_a_expo[1] ^ f_byp_alg_ex2_c_expo[1])); //K[ 1]==1
assign ex2_ack_s[2] = (~(f_byp_alg_ex2_a_expo[2] ^ f_byp_alg_ex2_c_expo[2])); //K[ 2]==1
assign ex2_ack_s[3] = (~(f_byp_alg_ex2_a_expo[3] ^ f_byp_alg_ex2_c_expo[3])); //K[ 3]==1
assign ex2_ack_s[4] = (f_byp_alg_ex2_a_expo[4] ^ f_byp_alg_ex2_c_expo[4]); //K[ 4]==0
assign ex2_ack_s[5] = (f_byp_alg_ex2_a_expo[5] ^ f_byp_alg_ex2_c_expo[5]); //K[ 5]==0
assign ex2_ack_s[6] = (f_byp_alg_ex2_a_expo[6] ^ f_byp_alg_ex2_c_expo[6]); //K[ 6]==0
assign ex2_ack_s[7] = (f_byp_alg_ex2_a_expo[7] ^ f_byp_alg_ex2_c_expo[7]); //K[ 7]==0
assign ex2_ack_s[8] = (~(f_byp_alg_ex2_a_expo[8] ^ f_byp_alg_ex2_c_expo[8])); //K[ 8]==1
assign ex2_ack_s[9] = (~(f_byp_alg_ex2_a_expo[9] ^ f_byp_alg_ex2_c_expo[9])); //K[ 9]==1 1
assign ex2_ack_s[10] = (~(f_byp_alg_ex2_a_expo[10] ^ f_byp_alg_ex2_c_expo[10])); //K[10]==1 1
assign ex2_ack_s[11] = (f_byp_alg_ex2_a_expo[11] ^ f_byp_alg_ex2_c_expo[11]); //K[11]==0
assign ex2_ack_s[12] = (~(f_byp_alg_ex2_a_expo[12] ^ f_byp_alg_ex2_c_expo[12])); //K[12]==1
assign ex2_ack_s[13] = (f_byp_alg_ex2_a_expo[13] ^ f_byp_alg_ex2_c_expo[13]); //K[13]==0
// cx00: ex2_ack_c( 0) <= not( ex2_a_expo_b( 1) and ex2_c_expo_b( 1) ); --K[ 1]==1 +or
assign ex2_ack_c[1] = (~(ex2_a_expo_b[2] & ex2_c_expo_b[2])); //K[ 2]==1 +or
assign ex2_ack_c[2] = (~(ex2_a_expo_b[3] & ex2_c_expo_b[3])); //K[ 3]==1 +or
assign ex2_ack_c[3] = (~(ex2_a_expo_b[4] | ex2_c_expo_b[4])); //K[ 4]==0 +and
assign ex2_ack_c[4] = (~(ex2_a_expo_b[5] | ex2_c_expo_b[5])); //K[ 5]==0 +and
assign ex2_ack_c[5] = (~(ex2_a_expo_b[6] | ex2_c_expo_b[6])); //K[ 6]==0 +and
assign ex2_ack_c[6] = (~(ex2_a_expo_b[7] | ex2_c_expo_b[7])); //K[ 7]==0 +and
assign ex2_ack_c[7] = (~(ex2_a_expo_b[8] & ex2_c_expo_b[8])); //K[ 8]==1 +or
assign ex2_ack_c[8] = (~(ex2_a_expo_b[9] & ex2_c_expo_b[9])); //K[ 9]==1 +or
assign ex2_ack_c[9] = (~(ex2_a_expo_b[10] & ex2_c_expo_b[10])); //K[10]==1 +or
assign ex2_ack_c[10] = (~(ex2_a_expo_b[11] | ex2_c_expo_b[11])); //K[11]==0 +and
assign ex2_ack_c[11] = (~(ex2_a_expo_b[12] & ex2_c_expo_b[12])); //K[12]==1 +or
assign ex2_ack_c[12] = (~(ex2_a_expo_b[13] | ex2_c_expo_b[13])); //K[13]==0
// fu_csa32s_h2
tri_csa32 sha32_01( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[1]), //i--
.b(ex2_ack_s[1]), //i--
.c(ex2_ack_c[1]), //i--
.sum(ex2_alg_sx[1]), //o--
.car(ex2_alg_cx[0]) //o--
);
tri_csa32 sha32_02( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[2]), //i--
.b(ex2_ack_s[2]), //i--
.c(ex2_ack_c[2]), //i--
.sum(ex2_alg_sx[2]), //o--
.car(ex2_alg_cx[1]) //o--
);
tri_csa32 sha32_03( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[3]), //i--
.b(ex2_ack_s[3]), //i--
.c(ex2_ack_c[3]), //i--
.sum(ex2_alg_sx[3]), //o--
.car(ex2_alg_cx[2]) //o--
);
tri_csa32 sha32_04( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[4]), //i--
.b(ex2_ack_s[4]), //i--
.c(ex2_ack_c[4]), //i--
.sum(ex2_alg_sx[4]), //o--
.car(ex2_alg_cx[3]) //o--
);
tri_csa32 sha32_05( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[5]), //i--
.b(ex2_ack_s[5]), //i--
.c(ex2_ack_c[5]), //i--
.sum(ex2_alg_sx[5]), //o--
.car(ex2_alg_cx[4]) //o--
);
tri_csa32 sha32_06( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[6]), //i--
.b(ex2_ack_s[6]), //i--
.c(ex2_ack_c[6]), //i--
.sum(ex2_alg_sx[6]), //o--
.car(ex2_alg_cx[5]) //o--
);
tri_csa32 sha32_07( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[7]), //i--
.b(ex2_ack_s[7]), //i--
.c(ex2_ack_c[7]), //i--
.sum(ex2_alg_sx[7]), //o--
.car(ex2_alg_cx[6]) //o--
);
tri_csa32 sha32_08( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[8]), //i--
.b(ex2_ack_s[8]), //i--
.c(ex2_ack_c[8]), //i--
.sum(ex2_alg_sx[8]), //o--
.car(ex2_alg_cx[7]) //o--
);
tri_csa32 sha32_09( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[9]), //i--
.b(ex2_ack_s[9]), //i--
.c(ex2_ack_c[9]), //i--
.sum(ex2_alg_sx[9]), //o--
.car(ex2_alg_cx[8]) //o--
);
tri_csa32 sha32_10( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[10]), //i--
.b(ex2_ack_s[10]), //i--
.c(ex2_ack_c[10]), //i--
.sum(ex2_alg_sx[10]), //o--
.car(ex2_alg_cx[9]) //o--
);
tri_csa32 sha32_11( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[11]), //i--
.b(ex2_ack_s[11]), //i--
.c(ex2_ack_c[11]), //i--
.sum(ex2_alg_sx[11]), //o--
.car(ex2_alg_cx[10]) //o--
);
tri_csa32 sha32_12( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[12]), //i--
.b(ex2_ack_s[12]), //i--
.c(ex2_ack_c[12]), //i--
.sum(ex2_alg_sx[12]), //o--
.car(ex2_alg_cx[11]) //o--
);
tri_csa32 sha32_13( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32
.vd(vdd),
.gd(gnd),
.a(ex2_b_expo_b[13]), //i--
.b(ex2_ack_s[13]), //i--
.c(tidn), //i--
.sum(ex2_alg_sx[13]), //o--
.car(ex2_alg_cx[12]) //o--
);
// now finish the add (for sha==0 means shift 0)
assign ex2_alg_add_p[1] = ex2_alg_sx[1] ^ ex2_alg_cx[1];
assign ex2_alg_add_p[2] = ex2_alg_sx[2] ^ ex2_alg_cx[2];
assign ex2_alg_add_p[3] = ex2_alg_sx[3] ^ ex2_alg_cx[3];
assign ex2_alg_add_p[4] = ex2_alg_sx[4] ^ ex2_alg_cx[4];
assign ex2_alg_add_p[5] = ex2_alg_sx[5] ^ ex2_alg_cx[5];
assign ex2_alg_add_p[6] = ex2_alg_sx[6] ^ ex2_alg_cx[6];
assign ex2_alg_add_p[7] = ex2_alg_sx[7] ^ ex2_alg_cx[7];
assign ex2_alg_add_p[8] = ex2_alg_sx[8] ^ ex2_alg_cx[8];
assign ex2_alg_add_p[9] = ex2_alg_sx[9] ^ ex2_alg_cx[9];
assign ex2_alg_add_p[10] = ex2_alg_sx[10] ^ ex2_alg_cx[10];
assign ex2_alg_add_p[11] = ex2_alg_sx[11] ^ ex2_alg_cx[11];
assign ex2_alg_add_p[12] = ex2_alg_sx[12] ^ ex2_alg_cx[12];
// ex2_alg_add_p(13) <= ex2_alg_sx(13);
//g1_01: ex2_alg_add_g_b( 1) <= not( ex2_alg_sx( 1) and ex2_alg_cx( 1) );
assign ex2_alg_add_g_b[2] = (~(ex2_alg_sx[2] & ex2_alg_cx[2]));
assign ex2_alg_add_g_b[3] = (~(ex2_alg_sx[3] & ex2_alg_cx[3]));
assign ex2_alg_add_g_b[4] = (~(ex2_alg_sx[4] & ex2_alg_cx[4]));
assign ex2_alg_add_g_b[5] = (~(ex2_alg_sx[5] & ex2_alg_cx[5]));
assign ex2_alg_add_g_b[6] = (~(ex2_alg_sx[6] & ex2_alg_cx[6]));
assign ex2_alg_add_g_b[7] = (~(ex2_alg_sx[7] & ex2_alg_cx[7]));
assign ex2_alg_add_g_b[8] = (~(ex2_alg_sx[8] & ex2_alg_cx[8]));
assign ex2_alg_add_g_b[9] = (~(ex2_alg_sx[9] & ex2_alg_cx[9]));
assign ex2_alg_add_g_b[10] = (~(ex2_alg_sx[10] & ex2_alg_cx[10]));
assign ex2_alg_add_g_b[11] = (~(ex2_alg_sx[11] & ex2_alg_cx[11]));
assign ex2_alg_add_g_b[12] = (~(ex2_alg_sx[12] & ex2_alg_cx[12]));
//t1_01: ex2_alg_add_t_b( 1) <= not( ex2_alg_sx( 1) or ex2_alg_cx( 1) );
assign ex2_alg_add_t_b[2] = (~(ex2_alg_sx[2] | ex2_alg_cx[2]));
assign ex2_alg_add_t_b[3] = (~(ex2_alg_sx[3] | ex2_alg_cx[3]));
assign ex2_alg_add_t_b[4] = (~(ex2_alg_sx[4] | ex2_alg_cx[4]));
assign ex2_alg_add_t_b[5] = (~(ex2_alg_sx[5] | ex2_alg_cx[5]));
assign ex2_alg_add_t_b[6] = (~(ex2_alg_sx[6] | ex2_alg_cx[6]));
assign ex2_alg_add_t_b[7] = (~(ex2_alg_sx[7] | ex2_alg_cx[7]));
assign ex2_alg_add_t_b[8] = (~(ex2_alg_sx[8] | ex2_alg_cx[8]));
assign ex2_alg_add_t_b[9] = (~(ex2_alg_sx[9] | ex2_alg_cx[9]));
assign ex2_alg_add_t_b[10] = (~(ex2_alg_sx[10] | ex2_alg_cx[10]));
assign ex2_alg_add_t_b[11] = (~(ex2_alg_sx[11] | ex2_alg_cx[11]));
//---------------------------------------------------------------------
// 12:13 are a decode group (12,13) are known before adder starts )
//---------------------------------------------------------------------
assign ex2_g02_12 = (~ex2_alg_add_g_b[12]); // main carry chain
assign ex2_g02_12_b = (~ex2_g02_12); // main carry chain
assign ex2_bsha_13_b = (~ex2_alg_sx[13]); // direct from compressor
assign ex2_bsha_13 = (~ex2_bsha_13_b); // to decoder 0/1/2/3
assign ex2_bsha_12_b = (~ex2_alg_add_p[12]);
assign ex2_bsha_12 = (~ex2_bsha_12_b); // to decoder 0/1/2/3
assign ex2_lv2_ci11n_en_b = (~(ex2_sel_special_b & ex2_g02_12_b));
assign ex2_lv2_ci11p_en_b = (~(ex2_sel_special_b & ex2_g02_12));
assign ex2_lv2_ci11n_en = (~(ex2_lv2_ci11n_en_b)); // to decoder 0/4/8/12
assign ex2_lv2_ci11p_en = (~(ex2_lv2_ci11p_en_b)); // to decoder 0/4/8/12
//---------------------------------------------------------------------
// 10:11 are a decode group, do not compute adder result (send signal direct to decode)
//---------------------------------------------------------------------
assign ex2_g02_10 = (~(ex2_alg_add_g_b[10] & (ex2_alg_add_t_b[10] | ex2_alg_add_g_b[11]))); //main carry chain
assign ex2_t02_10 = (~(ex2_alg_add_t_b[10] | ex2_alg_add_t_b[11])); //main carry chain
assign ex2_g04_10_b = (~(ex2_g02_10 | (ex2_t02_10 & ex2_g02_12))); //main carry chain
assign ex2_lv2_g11_x = (~(ex2_alg_add_g_b[11]));
assign ex2_lv2_g11_b = (~(ex2_lv2_g11_x));
assign ex2_lv2_g11 = (~(ex2_lv2_g11_b)); // to decoder 0/4/8/12
assign ex2_lv2_k11_b = (~(ex2_alg_add_t_b[11]));
assign ex2_lv2_k11 = (~(ex2_lv2_k11_b)); // to decoder 0/4/8/12
assign ex2_lv2_p11_b = (~(ex2_alg_add_p[11]));
assign ex2_lv2_p11 = (~(ex2_lv2_p11_b)); // to decoder 0/4/8/12
assign ex2_lv2_p10_b = (~(ex2_alg_add_p[10])); // to decoder 0/4/8/12
assign ex2_lv2_p10 = (~(ex2_lv2_p10_b)); // to decoder 0/4/8/12
//---------------------------------------------------------------------
// 6:9 are a decode group, not used until next cycle: (get add result then decode)
//----------------------------------------------------------------------
assign ex2_g04_10 = (~ex2_g04_10_b); // use this buffered of version to finish the local carry chain
assign ex2_g02_6 = (~(ex2_alg_add_g_b[6] & (ex2_alg_add_t_b[6] | ex2_alg_add_g_b[7])));
assign ex2_g02_7 = (~(ex2_alg_add_g_b[7] & (ex2_alg_add_t_b[7] | ex2_alg_add_g_b[8])));
assign ex2_g02_8 = (~(ex2_alg_add_g_b[8] & (ex2_alg_add_t_b[8] | ex2_alg_add_g_b[9])));
assign ex2_g02_9 = (~(ex2_alg_add_g_b[9]));
assign ex2_t02_6 = (~(ex2_alg_add_t_b[6] | ex2_alg_add_t_b[7]));
assign ex2_t02_7 = (~(ex2_alg_add_t_b[7] | ex2_alg_add_t_b[8]));
assign ex2_t02_8 = (~(ex2_alg_add_t_b[8] | ex2_alg_add_t_b[9]));
assign ex2_t02_9 = (~(ex2_alg_add_t_b[9]));
assign ex2_g04_6_b = (~(ex2_g02_6 | (ex2_t02_6 & ex2_g02_8)));
assign ex2_g04_7_b = (~(ex2_g02_7 | (ex2_t02_7 & ex2_g02_9)));
assign ex2_g04_8_b = (~(ex2_g02_8));
assign ex2_g04_9_b = (~(ex2_g02_9));
assign ex2_t04_6_b = (~(ex2_t02_6 & ex2_t02_8));
assign ex2_t04_7_b = (~(ex2_t02_7 & ex2_t02_9));
assign ex2_t04_8_b = (~(ex2_t02_8));
assign ex2_t04_9_b = (~(ex2_t02_9));
assign ex2_g08_6 = (~(ex2_g04_6_b & (ex2_t04_6_b | ex2_g04_10_b))); //main carry chain
assign ex2_g04_7 = (~(ex2_g04_7_b));
assign ex2_g04_8 = (~(ex2_g04_8_b));
assign ex2_g04_9 = (~(ex2_g04_9_b));
assign ex2_t04_7 = (~(ex2_t04_7_b));
assign ex2_t04_8 = (~(ex2_t04_8_b));
assign ex2_t04_9 = (~(ex2_t04_9_b));
assign ex2_alg_add_c_b[7] = (~(ex2_g04_7 | (ex2_t04_7 & ex2_g04_10)));
assign ex2_alg_add_c_b[8] = (~(ex2_g04_8 | (ex2_t04_8 & ex2_g04_10)));
assign ex2_alg_add_c_b[9] = (~(ex2_g04_9 | (ex2_t04_9 & ex2_g04_10)));
assign ex2_alg_add_c_b[10] = (~(ex2_g04_10));
assign ex2_bsha_6 = (~(ex2_alg_add_p[6] ^ ex2_alg_add_c_b[7])); //to multiple of 16 decoder
assign ex2_bsha_7 = (~(ex2_alg_add_p[7] ^ ex2_alg_add_c_b[8])); //to multiple of 16 decoder
assign ex2_bsha_8 = (~(ex2_alg_add_p[8] ^ ex2_alg_add_c_b[9])); //to multiple of 16 decoder
assign ex2_bsha_9 = (~(ex2_alg_add_p[9] ^ ex2_alg_add_c_b[10])); //to multiple of 16 decoder
assign ex2_bsha_6_i = (~ex2_bsha_6);
assign ex2_bsha_7_i = (~ex2_bsha_7);
assign ex2_bsha_8_i = (~ex2_bsha_8);
assign ex2_bsha_9_i = (~ex2_bsha_9);
assign ex2_bsha_6_o = (~ex2_bsha_6_i);
assign ex2_bsha_7_o = (~ex2_bsha_7_i);
assign ex2_bsha_8_o = (~ex2_bsha_8_i);
assign ex2_bsha_9_o = (~ex2_bsha_9_i);
//-----------------------------------------------------------------------
// Just need to know if 2/3/4/5 != 0000 for unf, produce that signal directly
//-----------------------------------------------------------------------
assign ex2_g02_2 = (~(ex2_alg_add_g_b[2] & (ex2_alg_add_t_b[2] | ex2_alg_add_g_b[3]))); //for carry select
assign ex2_g02_4 = (~(ex2_alg_add_g_b[4] & (ex2_alg_add_t_b[4] | ex2_alg_add_g_b[5]))); //for carry select
assign ex2_t02_2 = (~((ex2_alg_add_t_b[2] | ex2_alg_add_t_b[3]))); //for carry select
assign ex2_t02_4 = (~(ex2_alg_add_g_b[4] & (ex2_alg_add_t_b[4] | ex2_alg_add_t_b[5]))); //for carry select
assign ex2_g04_2_b = (~(ex2_g02_2 | (ex2_t02_2 & ex2_g02_4))); //for carry select
assign ex2_t04_2_b = (~(ex2_g02_2 | (ex2_t02_2 & ex2_t02_4))); //for carry select
assign ex2_ones_2t3_b = (~(ex2_alg_add_p[2] & ex2_alg_add_p[3])); // for unf calculation
assign ex2_ones_4t5_b = (~(ex2_alg_add_p[4] & ex2_alg_add_p[5])); // for unf calculation
assign ex2_ones_2t5 = (~(ex2_ones_2t3_b | ex2_ones_4t5_b)); // for unf calculation
assign ex2_ones_2t5_b = (~(ex2_ones_2t5));
assign ex2_zero_2_b = (~(ex2_alg_add_p[2] ^ ex2_alg_add_t_b[3])); // for unf calc
assign ex2_zero_3_b = (~(ex2_alg_add_p[3] ^ ex2_alg_add_t_b[4])); // for unf calc
assign ex2_zero_4_b = (~(ex2_alg_add_p[4] ^ ex2_alg_add_t_b[5])); // for unf calc
assign ex2_zero_5 = (~(ex2_alg_add_p[5])); // for unf calc
assign ex2_zero_5_b = (~(ex2_zero_5)); // for unf calc
assign ex2_zero_2t3 = (~(ex2_zero_2_b | ex2_zero_3_b)); // for unf calc
assign ex2_zero_4t5 = (~(ex2_zero_4_b | ex2_zero_5_b)); // for unf calc
assign ex2_zero_2t5_b = (~(ex2_zero_2t3 & ex2_zero_4t5)); // for unf calc
//--------------------------------------------------------------------------
// [1] is really the sign bit .. needed to indicate ovf/underflow
//-----------------------------------------------
// finish shift underflow
// if sha > 162 all the bits should become sticky and the aligner output should be zero
// from 163:255 the shifter does this, so just need to detect the upper bits
assign pos_if_pco6 = (ex2_alg_add_p[1] ^ ex2_t04_2_b);
assign pos_if_nco6 = (ex2_alg_add_p[1] ^ ex2_g04_2_b);
assign pos_if_pco6_b = (~pos_if_pco6);
assign pos_if_nco6_b = (~pos_if_nco6);
assign unf_if_nco6_b = (~(pos_if_nco6 & ex2_zero_2t5_b));
assign unf_if_pco6_b = (~(pos_if_pco6 & ex2_ones_2t5_b));
assign ex2_g08_6_b = (~ex2_g08_6);
assign ex2_bsha_pos = (~((pos_if_pco6_b & ex2_g08_6) | (pos_if_nco6_b & ex2_g08_6_b))); // same as neg
assign ex2_sh_ovf_b = (~((pos_if_pco6_b & ex2_g08_6) | (pos_if_nco6_b & ex2_g08_6_b))); // same as neg
assign ex2_sh_unf_x = (~((unf_if_pco6_b & ex2_g08_6) | (unf_if_nco6_b & ex2_g08_6_b)));
assign ex2_bsha_neg = (~(ex2_bsha_pos));
assign ex2_bsha_neg_o = (~(ex2_bsha_pos));
assign ex2_sh_ovf = (~(ex2_sh_ovf_b));
//==-------------------------------------------------------------------------------
//== decode for first level shifter (0/1/2/3)
//==-------------------------------------------------------------------------------
assign ex2_lvl1_shdcd000_b = (~(ex2_bsha_12_b & ex2_bsha_13_b));
assign ex2_lvl1_shdcd001_b = (~(ex2_bsha_12_b & ex2_bsha_13));
assign ex2_lvl1_shdcd002_b = (~(ex2_bsha_12 & ex2_bsha_13_b));
assign ex2_lvl1_shdcd003_b = (~(ex2_bsha_12 & ex2_bsha_13));
//==-------------------------------------------------------------------------------
//== decode for second level shifter (0/4/8/12)
//==-------------------------------------------------------------------------------
// ex2_lvl2_shdcd000 <= not ex2_bsha(10) and not ex2_bsha(11) ;
// ex2_lvl2_shdcd004 <= not ex2_bsha(10) and ex2_bsha(11) ;
// ex2_lvl2_shdcd008 <= ex2_bsha(10) and not ex2_bsha(11) ;
// ex2_lvl2_shdcd012 <= ex2_bsha(10) and ex2_bsha(11) ;
//--------------------------------------------------------------------
// p10 (11) ci11 DCD p10 (11) ci11 DCD
// !p k 0 00 !p k 0 00
// !P p 0 01 p g 0 00
// !p g 0 10 P p 1 00
//
// p k 0 10 !P p 0 01
// P p 0 11 !p k 1 01
// p g 0 00 p g 1 01
//
// !p k 1 01 !p g 0 10
// !P p 1 10 p k 0 10
// !p g 1 11 !P p 1 10
//
// p k 1 11 P p 0 11
// P p 1 00 !p g 1 11
// p g 1 01 p k 1 11
assign ex2_lv2_0pg0_b = (~(ex2_lv2_p10_b & ex2_lv2_g11 & ex2_lv2_ci11n_en));
assign ex2_lv2_0pg1_b = (~(ex2_lv2_p10_b & ex2_lv2_g11 & ex2_lv2_ci11p_en));
assign ex2_lv2_0pk0_b = (~(ex2_lv2_p10_b & ex2_lv2_k11 & ex2_lv2_ci11n_en));
assign ex2_lv2_0pk1_b = (~(ex2_lv2_p10_b & ex2_lv2_k11 & ex2_lv2_ci11p_en));
assign ex2_lv2_0pp0_b = (~(ex2_lv2_p10_b & ex2_lv2_p11 & ex2_lv2_ci11n_en));
assign ex2_lv2_0pp1_b = (~(ex2_lv2_p10_b & ex2_lv2_p11 & ex2_lv2_ci11p_en));
assign ex2_lv2_1pg0_b = (~(ex2_lv2_p10 & ex2_lv2_g11 & ex2_lv2_ci11n_en));
assign ex2_lv2_1pg1_b = (~(ex2_lv2_p10 & ex2_lv2_g11 & ex2_lv2_ci11p_en));
assign ex2_lv2_1pk0_b = (~(ex2_lv2_p10 & ex2_lv2_k11 & ex2_lv2_ci11n_en));
assign ex2_lv2_1pk1_b = (~(ex2_lv2_p10 & ex2_lv2_k11 & ex2_lv2_ci11p_en));
assign ex2_lv2_1pp0_b = (~(ex2_lv2_p10 & ex2_lv2_p11 & ex2_lv2_ci11n_en));
assign ex2_lv2_1pp1_b = (~(ex2_lv2_p10 & ex2_lv2_p11 & ex2_lv2_ci11p_en));
assign ex2_lv2_shdcd000 = (~(ex2_lv2_0pk0_b & ex2_lv2_1pg0_b & ex2_lv2_1pp1_b));
assign ex2_lv2_shdcd004 = (~(ex2_lv2_0pp0_b & ex2_lv2_0pk1_b & ex2_lv2_1pg1_b));
assign ex2_lv2_shdcd008 = (~(ex2_lv2_0pg0_b & ex2_lv2_1pk0_b & ex2_lv2_0pp1_b));
assign ex2_lv2_shdcd012 = (~(ex2_lv2_1pp0_b & ex2_lv2_0pg1_b & ex2_lv2_1pk1_b));
assign ex2_lvl2_shdcd000_b = (~ex2_lv2_shdcd000);
assign ex2_lvl2_shdcd004_b = (~ex2_lv2_shdcd004);
assign ex2_lvl2_shdcd008_b = (~ex2_lv2_shdcd008);
assign ex2_lvl2_shdcd012_b = (~ex2_lv2_shdcd012);
assign ex2_lvl2_shdcd000 = (~ex2_lvl2_shdcd000_b);
assign ex2_lvl2_shdcd004 = (~ex2_lvl2_shdcd004_b);
assign ex2_lvl2_shdcd008 = (~ex2_lvl2_shdcd008_b);
assign ex2_lvl2_shdcd012 = (~ex2_lvl2_shdcd012_b);
//==--------------------------------------------
//== decode to control ex3 shifting
//==--------------------------------------------
assign ex2_bsha_6_b = (~ex2_bsha_6);
assign ex2_bsha_7_b = (~ex2_bsha_7);
assign ex2_bsha_8_b = (~ex2_bsha_8);
assign ex2_bsha_9_b = (~ex2_bsha_9);
assign ex2_67_dcd00_b = (~(ex2_bsha_6_b & ex2_bsha_7_b));
assign ex2_67_dcd01_b = (~(ex2_bsha_6_b & ex2_bsha_7));
assign ex2_67_dcd10_b = (~(ex2_bsha_6 & ex2_bsha_7_b));
assign ex2_67_dcd11_b = (~(ex2_bsha_6 & ex2_bsha_7 & ex2_bsha_neg));
assign ex2_89_dcd00_b = (~(ex2_bsha_8_b & ex2_bsha_9_b & ex2_sel_special_b));
assign ex2_89_dcd01_b = (~(ex2_bsha_8_b & ex2_bsha_9 & ex2_sel_special_b));
assign ex2_89_dcd10_b = (~(ex2_bsha_8 & ex2_bsha_9_b & ex2_sel_special_b));
assign ex2_89_dcd11_b = (~(ex2_bsha_8 & ex2_bsha_9 & ex2_sel_special_b));
assign ex2_lvl3_shdcd000 = (~(ex2_67_dcd00_b | ex2_89_dcd00_b)); // 0000 +000
assign ex2_lvl3_shdcd016 = (~(ex2_67_dcd00_b | ex2_89_dcd01_b)); // 0001 +016
assign ex2_lvl3_shdcd032 = (~(ex2_67_dcd00_b | ex2_89_dcd10_b)); // 0010 +032
assign ex2_lvl3_shdcd048 = (~(ex2_67_dcd00_b | ex2_89_dcd11_b)); // 0011 +048
assign ex2_lvl3_shdcd064 = (~(ex2_67_dcd01_b | ex2_89_dcd00_b)); // 0100 +064
assign ex2_lvl3_shdcd080 = (~(ex2_67_dcd01_b | ex2_89_dcd01_b)); // 0101 +080
assign ex2_lvl3_shdcd096 = (~(ex2_67_dcd01_b | ex2_89_dcd10_b)); // 0110 +096
assign ex2_lvl3_shdcd112 = (~(ex2_67_dcd01_b | ex2_89_dcd11_b)); // 0111 +112
assign ex2_lvl3_shdcd128 = (~(ex2_67_dcd10_b | ex2_89_dcd00_b)); // 1000 +128
assign ex2_lvl3_shdcd144 = (~(ex2_67_dcd10_b | ex2_89_dcd01_b)); // 1001 +144
assign ex2_lvl3_shdcd160 = (~(ex2_67_dcd10_b | ex2_89_dcd10_b)); // 1010 +160
assign ex2_lvl3_shdcd176 = (~(ex2_67_dcd10_b | ex2_89_dcd11_b)); // 1011
assign ex2_lvl3_shdcd192 = (~(ex2_67_dcd11_b | ex2_89_dcd00_b)); // 1100 -064
assign ex2_lvl3_shdcd208 = (~(ex2_67_dcd11_b | ex2_89_dcd01_b)); // 1101 -048
assign ex2_lvl3_shdcd224 = (~(ex2_67_dcd11_b | ex2_89_dcd10_b)); // 1110 -032
assign ex2_lvl3_shdcd240 = (~(ex2_67_dcd11_b | ex2_89_dcd11_b)); // 1111 -016
endmodule |
module pcq_dbg(
// Include model build parameters
`include "tri_a2o.vh"
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input scan_dis_dc_b,
input lcb_clkoff_dc_b,
input lcb_mpw1_dc_b,
input lcb_mpw2_dc_b,
input lcb_delay_lclkr_dc,
input lcb_act_dis_dc,
input pc_pc_func_slp_sl_thold_0,
input pc_pc_sg_0,
input func_scan_in,
output func_scan_out,
// Trace/Trigger Bus
output [0:31] debug_bus_out,
input [0:31] debug_bus_in,
input rg_db_trace_bus_enable,
input [0:10] rg_db_debug_mux_ctrls,
input [0:3] coretrace_ctrls_in,
output [0:3] coretrace_ctrls_out,
//PC Unit internal debug signals
input [0:11] rg_db_dbg_scom,
input [0:24] rg_db_dbg_thrctls,
input [0:15] rg_db_dbg_ram,
input [0:27] rg_db_dbg_fir0_err,
input [0:19] rg_db_dbg_fir1_err,
input [0:19] rg_db_dbg_fir2_err,
input [0:14] rg_db_dbg_fir_misc,
input [0:14] ct_db_dbg_ctrls,
input [0:7] rg_db_dbg_spr
);
//=====================================================================
// Signal Declarations
//=====================================================================
parameter RAMCTRL_SIZE = 2;
parameter SCMISC_SIZE = 7;
parameter FIRMISC_SIZE = 2;
parameter TRACEOUT_SIZE = 32;
parameter CORETRACE_SIZE = 4;
//---------------------------------------------------------------------
// Scan Ring Ordering:
// start of func scan chain ordering
parameter RAMCTRL_OFFSET = 0;
parameter SCMISC_OFFSET = RAMCTRL_OFFSET + RAMCTRL_SIZE;
parameter FIRMISC_OFFSET = SCMISC_OFFSET + SCMISC_SIZE;
parameter TRACEOUT_OFFSET = FIRMISC_OFFSET + FIRMISC_SIZE;
parameter CORETRACE_OFFSET = TRACEOUT_OFFSET + TRACEOUT_SIZE;
parameter FUNC_RIGHT = CORETRACE_OFFSET + CORETRACE_SIZE - 1;
// end of func scan chain ordering
//---------------------------------------------------------------------
// Basic/Misc signals
wire [0:FUNC_RIGHT] func_siv;
wire [0:FUNC_RIGHT] func_sov;
wire pc_pc_func_slp_sl_thold_0_b;
wire force_func;
// Trace/Trigger/Event Mux signals
wire [0:TRACEOUT_SIZE-1] debug_group_0;
wire [0:TRACEOUT_SIZE-1] debug_group_1;
wire [0:TRACEOUT_SIZE-1] debug_group_2;
wire [0:TRACEOUT_SIZE-1] debug_group_3;
wire [0:TRACEOUT_SIZE-1] debug_group_4;
wire [0:TRACEOUT_SIZE-1] debug_group_5;
wire [0:TRACEOUT_SIZE-1] debug_group_6;
wire [0:TRACEOUT_SIZE-1] debug_group_7;
// Trace/Trigger input signals
wire [0:31] fir0_errors_q;
wire [0:31] fir1_errors_q;
wire [0:31] fir2_errors_q;
wire [0:2] fir_xstop_err_q;
wire [0:2] fir_lxstop_err_q;
wire [0:2] fir_recov_err_q;
wire fir0_recov_err_pulse_q;
wire fir1_recov_err_pulse_q;
wire fir2_recov_err_pulse_q;
wire fir_block_ram_mode_q;
wire [0:1] fir_xstop_per_thread_d;
wire [0:1] fir_xstop_per_thread_q;
//
wire scmisc_sc_act_d;
wire scmisc_sc_act_q;
wire scmisc_sc_req_q;
wire scmisc_sc_wr_q;
wire [0:5] scmisc_scaddr_predecode_d;
wire [0:5] scmisc_scaddr_predecode_q;
wire scmisc_scaddr_nvld_q;
wire scmisc_sc_wr_nvld_q;
wire scmisc_sc_rd_nvld_q;
//
wire ram_mode_q;
wire [0:1] ram_active_q;
wire ram_execute_q;
wire ram_msrovren_q;
wire ram_msrovrpr_q;
wire ram_msrovrgs_q;
wire ram_msrovrde_q;
wire ram_unsupported_q;
wire ram_instr_overrun_d;
wire ram_instr_overrun_q;
wire ram_interrupt_q;
wire ram_mode_xstop_d;
wire ram_mode_xstop_q;
wire ram_done_q;
wire ram_xu_ram_data_val_q;
wire ram_fu_ram_data_val_q;
wire ram_lq_ram_data_val_q;
//
wire regs_xstop_report_ovrid;
wire regs_dis_pwr_savings;
wire regs_dis_overrun_chks;
wire regs_maxRecErrCntrValue;
wire regs_ext_debug_stop_q;
wire [0:1] regs_spattn_data_q;
wire [0:1] regs_power_managed_q;
wire [0:1] regs_pm_thread_stop_q;
wire [0:1] regs_stop_dbg_event_q;
wire [0:1] regs_stop_dbg_dnh_q;
wire [0:1] regs_tx_stop_q;
wire [0:1] regs_thread_running_q;
wire [0:1] regs_tx_step_q;
wire [0:1] regs_tx_step_done_q;
wire [0:1] regs_tx_step_req_q;
//
wire ctrls_pmstate_q_anded;
wire ctrls_pmstate_all_q;
wire ctrls_power_managed_q;
wire ctrls_pm_rvwinkled_q;
wire [0:7] ctrls_pmclkctrl_dly_q;
wire ctrls_dis_pwr_sav_q;
wire ctrls_ccflush_dis_q;
wire ctrls_raise_tholds_q;
//
wire spr_cesr1_wren;
wire spr_sramd_wren;
wire [0:1] spr_perfmon_alert_q;
wire [0:1] spr_cesr1_is0_l2;
wire [0:1] spr_cesr1_is1_l2;
// Latch definitions begin
wire [0:TRACEOUT_SIZE-1] trace_data_out_d;
wire [0:TRACEOUT_SIZE-1] trace_data_out_q;
wire [0:3] coretrace_ctrls_out_d;
wire [0:3] coretrace_ctrls_out_q;
//=====================================================================
// Trace/Trigger Bus - Sort out input debug signals
//=====================================================================
// FIR/Error related signals.
assign fir0_errors_q[0:31] = {rg_db_dbg_fir0_err, { 4 {1'b0}} };
assign fir1_errors_q[0:31] = {rg_db_dbg_fir1_err, {12 {1'b0}} };
assign fir2_errors_q[0:31] = {rg_db_dbg_fir2_err, {12 {1'b0}} };
assign fir_xstop_err_q = rg_db_dbg_fir_misc[0:2];
assign fir_lxstop_err_q = rg_db_dbg_fir_misc[3:5];
assign fir_recov_err_q = rg_db_dbg_fir_misc[6:8];
assign fir0_recov_err_pulse_q = rg_db_dbg_fir_misc[9];
assign fir1_recov_err_pulse_q = rg_db_dbg_fir_misc[10];
assign fir2_recov_err_pulse_q = rg_db_dbg_fir_misc[11];
assign fir_block_ram_mode_q = rg_db_dbg_fir_misc[12];
assign fir_xstop_per_thread_d = rg_db_dbg_fir_misc[13:14];
// SCOM error; control signals
assign scmisc_sc_act_d = rg_db_dbg_scom[0];
assign scmisc_sc_req_q = rg_db_dbg_scom[1];
assign scmisc_sc_wr_q = rg_db_dbg_scom[2];
assign scmisc_scaddr_predecode_d = rg_db_dbg_scom[3:8];
assign scmisc_scaddr_nvld_q = rg_db_dbg_scom[9];
assign scmisc_sc_wr_nvld_q = rg_db_dbg_scom[10];
assign scmisc_sc_rd_nvld_q = rg_db_dbg_scom[11];
// RAM control signals
assign ram_mode_q = rg_db_dbg_ram[0];
assign ram_active_q = rg_db_dbg_ram[1:2];
assign ram_execute_q = rg_db_dbg_ram[3];
assign ram_msrovren_q = rg_db_dbg_ram[4];
assign ram_msrovrpr_q = rg_db_dbg_ram[5];
assign ram_msrovrgs_q = rg_db_dbg_ram[6];
assign ram_msrovrde_q = rg_db_dbg_ram[7];
assign ram_unsupported_q = rg_db_dbg_ram[8];
assign ram_instr_overrun_d = rg_db_dbg_ram[9];
assign ram_interrupt_q = rg_db_dbg_ram[10];
assign ram_mode_xstop_d = rg_db_dbg_ram[11];
assign ram_done_q = rg_db_dbg_ram[12];
assign ram_xu_ram_data_val_q = rg_db_dbg_ram[13];
assign ram_fu_ram_data_val_q = rg_db_dbg_ram[14];
assign ram_lq_ram_data_val_q = rg_db_dbg_ram[15];
// THRCTL and misc control signals
assign regs_xstop_report_ovrid = rg_db_dbg_thrctls[0];
assign regs_dis_pwr_savings = rg_db_dbg_thrctls[1];
assign regs_dis_overrun_chks = rg_db_dbg_thrctls[2];
assign regs_maxRecErrCntrValue = rg_db_dbg_thrctls[3];
assign regs_ext_debug_stop_q = rg_db_dbg_thrctls[4];
assign regs_spattn_data_q = rg_db_dbg_thrctls[5:6];
assign regs_power_managed_q = rg_db_dbg_thrctls[7:8];
assign regs_pm_thread_stop_q = rg_db_dbg_thrctls[9:10];
assign regs_stop_dbg_event_q = rg_db_dbg_thrctls[11:12];
assign regs_stop_dbg_dnh_q = rg_db_dbg_thrctls[13:14];
assign regs_tx_stop_q = rg_db_dbg_thrctls[15:16];
assign regs_thread_running_q = rg_db_dbg_thrctls[17:18];
assign regs_tx_step_q = rg_db_dbg_thrctls[19:20];
assign regs_tx_step_done_q = rg_db_dbg_thrctls[21:22];
assign regs_tx_step_req_q = rg_db_dbg_thrctls[23:24];
// Power Management signals
assign ctrls_pmstate_q_anded = ct_db_dbg_ctrls[0];
assign ctrls_pmstate_all_q = ct_db_dbg_ctrls[1];
assign ctrls_power_managed_q = ct_db_dbg_ctrls[2];
assign ctrls_pm_rvwinkled_q = ct_db_dbg_ctrls[3];
assign ctrls_pmclkctrl_dly_q = ct_db_dbg_ctrls[4:11];
assign ctrls_dis_pwr_sav_q = ct_db_dbg_ctrls[12];
assign ctrls_ccflush_dis_q = ct_db_dbg_ctrls[13];
assign ctrls_raise_tholds_q = ct_db_dbg_ctrls[14];
// SPRs signals
assign spr_cesr1_wren = rg_db_dbg_spr[0];
assign spr_sramd_wren = rg_db_dbg_spr[1];
assign spr_perfmon_alert_q = rg_db_dbg_spr[2:3];
assign spr_cesr1_is0_l2 = rg_db_dbg_spr[4:5];
assign spr_cesr1_is1_l2 = rg_db_dbg_spr[6:7];
//=====================================================================
// Trace/Trigger Bus - Form trace bus groups from input debug signals
//=====================================================================
// FIR0[32:59] errors not connected: max_recov_err_cntr_value (32), spare (59)
// FIR1[32:51] errors not connected: wdt_reset (45), debug_event (46), spare (47:51)
// FIR2[32:51] errors not connected: wdt_reset (45), debug_event (46), spare (47:51)
assign debug_group_0[0:TRACEOUT_SIZE-1] = { fir0_errors_q[0:31] }; // 0:31
assign debug_group_1[0:TRACEOUT_SIZE-1] = { fir1_errors_q[0:31] }; // 0:31
assign debug_group_2[0:TRACEOUT_SIZE-1] = { fir2_errors_q[0:31] }; // 0:31
assign debug_group_3[0:TRACEOUT_SIZE-1] = {
fir_recov_err_q[0:2], fir_xstop_err_q[0:2], fir_lxstop_err_q[0:2], fir_xstop_per_thread_q[0:1], // 0:15
fir_block_ram_mode_q, fir0_recov_err_pulse_q, fir1_recov_err_pulse_q, fir2_recov_err_pulse_q,
scmisc_sc_act_q, scmisc_sc_req_q, scmisc_sc_wr_q, scmisc_scaddr_nvld_q, // 16:31
scmisc_sc_wr_nvld_q, scmisc_sc_rd_nvld_q, scmisc_scaddr_predecode_q[0:5], 5'b00000
};
assign debug_group_4[0:TRACEOUT_SIZE-1] = {
regs_maxRecErrCntrValue, regs_xstop_report_ovrid, regs_spattn_data_q[0:1], // 0:15
regs_ext_debug_stop_q, regs_stop_dbg_event_q[0:1], regs_stop_dbg_dnh_q[0:1],
regs_pm_thread_stop_q[0:1], regs_thread_running_q[0:1], regs_power_managed_q[0:1],
regs_dis_pwr_savings,
regs_tx_stop_q[0:1], regs_tx_step_q[0:1], regs_tx_step_done_q[0:1], regs_tx_step_req_q[0:1], // 16:31
spr_perfmon_alert_q[0:1], spr_cesr1_is0_l2[0:1], spr_cesr1_is1_l2[0:1],
spr_sramd_wren, spr_cesr1_wren
};
assign debug_group_5[0:TRACEOUT_SIZE-1] = {
ctrls_pmstate_q_anded, ctrls_pmstate_all_q, ctrls_power_managed_q, ctrls_pm_rvwinkled_q, // 0:15
ctrls_pmclkctrl_dly_q[0:7], ctrls_dis_pwr_sav_q, ctrls_ccflush_dis_q, ctrls_raise_tholds_q,
regs_dis_overrun_chks,
ram_mode_q, ram_active_q[0:1], ram_execute_q, ram_done_q, ram_xu_ram_data_val_q, // 16:31
ram_fu_ram_data_val_q, ram_lq_ram_data_val_q, ram_msrovren_q, ram_msrovrpr_q, ram_msrovrgs_q,
ram_msrovrde_q, ram_unsupported_q, ram_instr_overrun_q, ram_interrupt_q, ram_mode_xstop_q
};
assign debug_group_6[0:TRACEOUT_SIZE-1] = { {32 {1'b0}} };
assign debug_group_7[0:TRACEOUT_SIZE-1] = { {32 {1'b0}} };
//=====================================================================
// Trace Bus Mux
//=====================================================================
tri_debug_mux8 debug_mux(
.select_bits(rg_db_debug_mux_ctrls),
.dbg_group0(debug_group_0),
.dbg_group1(debug_group_1),
.dbg_group2(debug_group_2),
.dbg_group3(debug_group_3),
.dbg_group4(debug_group_4),
.dbg_group5(debug_group_5),
.dbg_group6(debug_group_6),
.dbg_group7(debug_group_7),
.trace_data_in(debug_bus_in),
.trace_data_out(trace_data_out_d),
.coretrace_ctrls_in(coretrace_ctrls_in),
.coretrace_ctrls_out(coretrace_ctrls_out_d)
);
//=====================================================================
// Outputs
//=====================================================================
assign debug_bus_out = trace_data_out_q;
assign coretrace_ctrls_out = coretrace_ctrls_out_q;
//=====================================================================
// Latches
//=====================================================================
// func ring registers start
tri_rlmreg_p #(.WIDTH(RAMCTRL_SIZE), .INIT(0)) ramctrl(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rg_db_trace_bus_enable),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[RAMCTRL_OFFSET:RAMCTRL_OFFSET + RAMCTRL_SIZE - 1]),
.scout(func_sov[RAMCTRL_OFFSET:RAMCTRL_OFFSET + RAMCTRL_SIZE - 1]),
.din( {ram_instr_overrun_d, ram_mode_xstop_d}),
.dout({ram_instr_overrun_q, ram_mode_xstop_q})
);
tri_rlmreg_p #(.WIDTH(SCMISC_SIZE), .INIT(0)) scmisc(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rg_db_trace_bus_enable),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[SCMISC_OFFSET:SCMISC_OFFSET + SCMISC_SIZE - 1]),
.scout(func_sov[SCMISC_OFFSET:SCMISC_OFFSET + SCMISC_SIZE - 1]),
.din( {scmisc_sc_act_d, scmisc_scaddr_predecode_d}),
.dout({scmisc_sc_act_q, scmisc_scaddr_predecode_q})
);
tri_rlmreg_p #(.WIDTH(FIRMISC_SIZE), .INIT(0)) firmisc(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rg_db_trace_bus_enable),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[FIRMISC_OFFSET:FIRMISC_OFFSET + FIRMISC_SIZE - 1]),
.scout(func_sov[FIRMISC_OFFSET:FIRMISC_OFFSET + FIRMISC_SIZE - 1]),
.din( fir_xstop_per_thread_d),
.dout(fir_xstop_per_thread_q)
);
tri_rlmreg_p #(.WIDTH(TRACEOUT_SIZE), .INIT(0)) traceout(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rg_db_trace_bus_enable),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[TRACEOUT_OFFSET:TRACEOUT_OFFSET + TRACEOUT_SIZE - 1]),
.scout(func_sov[TRACEOUT_OFFSET:TRACEOUT_OFFSET + TRACEOUT_SIZE - 1]),
.din( trace_data_out_d),
.dout(trace_data_out_q)
);
tri_rlmreg_p #(.WIDTH(CORETRACE_SIZE), .INIT(0)) coretrace(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rg_db_trace_bus_enable),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[CORETRACE_OFFSET:CORETRACE_OFFSET + CORETRACE_SIZE - 1]),
.scout(func_sov[CORETRACE_OFFSET:CORETRACE_OFFSET + CORETRACE_SIZE - 1]),
.din( coretrace_ctrls_out_d),
.dout(coretrace_ctrls_out_q)
);
// func ring registers end
//=====================================================================
// Thold/SG Staging
//=====================================================================
// func lcbor
tri_lcbor lcbor_func0(
.clkoff_b(lcb_clkoff_dc_b),
.thold(pc_pc_func_slp_sl_thold_0),
.sg(pc_pc_sg_0),
.act_dis(lcb_act_dis_dc),
.force_t(force_func),
.thold_b(pc_pc_func_slp_sl_thold_0_b)
);
//=====================================================================
// Scan Connections
//=====================================================================
// Func ring
assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]};
assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b;
endmodule |
module fu_divsqrt_nq_table(
x,
nq
);
`include "tri_a2o.vh"
input [0:3] x;
output nq;
wire not1111;
wire nq_b;
//// Implements this table:
// assign exx_nq_bit0 = (exx_sum4 == 4'b1000) ? 1'b1 :
// (exx_sum4 == 4'b1001) ? 1'b1 :
// (exx_sum4 == 4'b1010) ? 1'b1 :
// (exx_sum4 == 4'b1011) ? 1'b1 :
// (exx_sum4 == 4'b1100) ? 1'b1 :
// (exx_sum4 == 4'b1101) ? 1'b1 :
// (exx_sum4 == 4'b1110) ? 1'b1 :
// 1'b0;
tri_nand4 #(.WIDTH(1), .BTR("NAND4_X4M_A9TH")) DIVSQRT_NQ_TABLE_NAND4_00(not1111, x[0], x[1], x[2], x[3]);
tri_nand2 #(.WIDTH(1), .BTR("NAND2_X6A_A9TH")) DIVSQRT_NQ_TABLE_NAND2_00(nq_b, x[0], not1111);
tri_inv #(.WIDTH(1), .BTR("INV_X11M_A9TH")) DIVSQRT_NQ_TABLE_INV_00(nq, nq_b);
endmodule |
module lq_agen(
x,
y,
mode64,
dir_ig_57_b,
sum_non_erat,
sum,
sum_arr_dir01,
sum_arr_dir23,
sum_arr_dir45,
sum_arr_dir67,
way,
rel4_dir_wr_val,
ary_write_act_01,
ary_write_act_23,
ary_write_act_45,
ary_write_act_67
);
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter expand_type = 2; // 2 - ibm tech, 1 - other
input [0:63] x;
input [0:63] y;
input mode64; // 1 per byte [0:31]
input dir_ig_57_b; // when this is low , bit 57 becomes "1" .
output [0:63] sum_non_erat; // for compares and uses other than array address
output [0:51] sum; // 0:51 for erat
output [52:57] sum_arr_dir01;
output [52:57] sum_arr_dir23;
output [52:57] sum_arr_dir45;
output [52:57] sum_arr_dir67;
input [0:7] way; // 8 bit vector use to be in array model
input rel4_dir_wr_val;
output ary_write_act_01;
output ary_write_act_23;
output ary_write_act_45;
output ary_write_act_67;
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:51] sum_int;
wire [0:51] sum_non_erat_b;
wire [0:51] sum_erat;
wire [0:51] sum_erat_b;
wire [0:51] sum_0;
wire [0:51] sum_1;
wire [1:7] g08;
wire [1:6] t08;
wire [1:7] c64_b;
wire addr_sel_64;
wire [0:63] x_b;
wire [0:63] y_b;
wire [52:57] sum_arr;
wire [52:57] sum_arr_lv1_0_b;
wire [52:57] sum_arr_lv1_1_b;
assign addr_sel_64 = mode64;
// assume pins come in the top
// start global carry along the top .
// byte groups (0 near top) stretch out along the macro.
//assign x_b[0:63] = (~(x[0:63])); // receiving inverter near pin
tri_inv #(.WIDTH(64)) x_b_0 (.y(x_b[0:63]), .a(x[0:63]));
//assign y_b[0:63] = (~(y[0:63])); // receiving inverter near pin
tri_inv #(.WIDTH(64)) y_b_0 (.y(y_b[0:63]), .a(y[0:63]));
//##################################################
//## local part of byte group
//##################################################
lq_agen_loca loc_0(
.x_b(x_b[0:7]), //i--
.y_b(y_b[0:7]), //i--
.sum_0(sum_0[0:7]), //o--
.sum_1(sum_1[0:7]) //o--
);
lq_agen_loca loc_1(
.x_b(x_b[8:15]), //i--
.y_b(y_b[8:15]), //i--
.sum_0(sum_0[8:15]), //o--
.sum_1(sum_1[8:15]) //o--
);
lq_agen_loca loc_2(
.x_b(x_b[16:23]), //i--
.y_b(y_b[16:23]), //i--
.sum_0(sum_0[16:23]), //o--
.sum_1(sum_1[16:23]) //o--
);
lq_agen_loca loc_3(
.x_b(x_b[24:31]), //i--
.y_b(y_b[24:31]), //i--
.sum_0(sum_0[24:31]), //o--
.sum_1(sum_1[24:31]) //o--
);
lq_agen_loca loc_4(
.x_b(x_b[32:39]), //i--
.y_b(y_b[32:39]), //i--
.sum_0(sum_0[32:39]), //o--
.sum_1(sum_1[32:39]) //o--
);
lq_agen_loca loc_5(
.x_b(x_b[40:47]), //i--
.y_b(y_b[40:47]), //i--
.sum_0(sum_0[40:47]), //o--
.sum_1(sum_1[40:47]) //o--
);
lq_agen_locae loc_6(
.x_b(x_b[48:55]), //i--
.y_b(y_b[48:55]), //i--
.sum_0(sum_0[48:51]), //o--
.sum_1(sum_1[48:51]) //o--
);
//##################################################
//## local part of global carry
//##################################################
lq_agen_glbloc gclc_1(
.x_b(x_b[8:15]), //i--
.y_b(y_b[8:15]), //i--
.g08(g08[1]), //o--
.t08(t08[1]) //o--
);
lq_agen_glbloc gclc_2(
.x_b(x_b[16:23]), //i--
.y_b(y_b[16:23]), //i--
.g08(g08[2]), //o--
.t08(t08[2]) //o--
);
lq_agen_glbloc gclc_3(
.x_b(x_b[24:31]), //i--
.y_b(y_b[24:31]), //i--
.g08(g08[3]), //o--
.t08(t08[3]) //o--
);
lq_agen_glbloc gclc_4(
.x_b(x_b[32:39]), //i--
.y_b(y_b[32:39]), //i--
.g08(g08[4]), //o--
.t08(t08[4]) //o--
);
lq_agen_glbloc gclc_5(
.x_b(x_b[40:47]), //i--
.y_b(y_b[40:47]), //i--
.g08(g08[5]), //o--
.t08(t08[5]) //o--
);
lq_agen_glbloc gclc_6(
.x_b(x_b[48:55]), //i--
.y_b(y_b[48:55]), //i--
.g08(g08[6]), //o--
.t08(t08[6]) //o--
);
lq_agen_glbloc_lsb gclc_7(
.x_b(x_b[56:63]), //i--
.y_b(y_b[56:63]), //i--
.g08(g08[7]) //o--
);
//##################################################
//## global part of global carry {replicate ending of global carry vertical)
//##################################################
lq_agen_glbglb gc(
.g08(g08[1:7]), //i--
.t08(t08[1:6]), //i--
.c64_b(c64_b[1:7]) //o--
);
//##################################################
//## final mux (vertical)
//##################################################
lq_agen_csmux fm_0(
.ci_b(c64_b[1]), //i--
.sum_0(sum_0[0:7]), //i--
.sum_1(sum_1[0:7]), //i--
.sum(sum_int[0:7]) //o--
);
lq_agen_csmux fm_1(
.ci_b(c64_b[2]), //i--
.sum_0(sum_0[8:15]), //i--
.sum_1(sum_1[8:15]), //i--
.sum(sum_int[8:15]) //o--
);
lq_agen_csmux fm_2(
.ci_b(c64_b[3]), //i--
.sum_0(sum_0[16:23]), //i--
.sum_1(sum_1[16:23]), //i--
.sum(sum_int[16:23]) //o--
);
lq_agen_csmux fm_3(
.ci_b(c64_b[4]), //i--
.sum_0(sum_0[24:31]), //i--
.sum_1(sum_1[24:31]), //i--
.sum(sum_int[24:31]) //o--
);
lq_agen_csmux fm_4(
.ci_b(c64_b[5]), //i--
.sum_0(sum_0[32:39]), //i--
.sum_1(sum_1[32:39]), //i--
.sum(sum_int[32:39]) //o--
);
lq_agen_csmux fm_5(
.ci_b(c64_b[6]), //i--
.sum_0(sum_0[40:47]), //i--
.sum_1(sum_1[40:47]), //i--
.sum(sum_int[40:47]) //o--
);
// just the 4 msb of the byte go to erat
lq_agen_csmuxe fm_6(
.ci_b(c64_b[7]), //i--
.sum_0(sum_0[48:51]), //i--
.sum_1(sum_1[48:51]), //i--
.sum(sum_int[48:51]) //o--
);
// 12 lsbs are for the DIRECTORY
lq_agen_lo kog(
.dir_ig_57_b(dir_ig_57_b), //i--lq_agen_lo(kog) force dir addr 57 to "1"
.x_b(x_b[52:63]), //i--lq_agen_lo(kog)
.y_b(y_b[52:63]), //i--lq_agen_lo(kog)
.sum(sum_non_erat[52:63]), //o--lq_agen_lo(kog) for the compares etc
.sum_arr(sum_arr[52:57]) //o--lq_agen_lo(kog) for the array address
);
//assign sum_non_erat_b[0:51] = (~(sum_int[0:51]));
tri_inv #(.WIDTH(52)) sum_non_erat_b_0 (.y(sum_non_erat_b[0:51]), .a(sum_int[0:51]));
//assign sum_non_erat[0:51] = (~(sum_non_erat_b[0:51]));
tri_inv #(.WIDTH(52)) sum_non_erat_0 (.y(sum_non_erat[0:51]), .a(sum_non_erat_b[0:51]));
//assign sum_erat_b[0:31] = (~(sum_int[0:31] & {32{addr_sel_64}}));
tri_nand2 #(.WIDTH(32)) sum_erat_b_0 (.y(sum_erat_b[0:31]), .a(sum_int[0:31]), .b({32{addr_sel_64}}));
//assign sum_erat_b[32:51] = (~(sum_int[32:51]));
tri_inv #(.WIDTH(20)) sum_erat_b_32 (.y(sum_erat_b[32:51]), .a(sum_int[32:51]));
//assign sum_erat = (~(sum_erat_b));
tri_inv #(.WIDTH(52)) sum_erat_0 (.y(sum_erat[0:51]), .a(sum_erat_b[0:51]));
assign sum = sum_erat; //rename-- to ERAT only
// ###################################
// # repower network for directoru
// ###################################
//assign sum_arr_lv1_1_b[52:57] = (~(sum_arr[52:57])); // 4x
tri_inv #(.WIDTH(6)) sum_arr_lv1_1_b_52 (.y(sum_arr_lv1_1_b[52:57]), .a(sum_arr[52:57]));
//assign sum_arr_dir01[52:57] = (~(sum_arr_lv1_1_b[52:57])); // 4x --output--
tri_inv #(.WIDTH(6)) sum_arr_dir01_52 (.y(sum_arr_dir01[52:57]), .a(sum_arr_lv1_1_b[52:57]));
//assign sum_arr_dir45[52:57] = (~(sum_arr_lv1_1_b[52:57])); // 4x --output--
tri_inv #(.WIDTH(6)) sum_arr_dir45_52 (.y(sum_arr_dir45[52:57]), .a(sum_arr_lv1_1_b[52:57]));
//assign sum_arr_lv1_0_b[52:57] = (~(sum_arr[52:57])); // 6x
tri_inv #(.WIDTH(6)) sum_arr_lv1_0_b_52 (.y(sum_arr_lv1_0_b[52:57]), .a(sum_arr[52:57]));
//assign sum_arr_dir23[52:57] = (~(sum_arr_lv1_0_b[52:57])); // 4x --output--
tri_inv #(.WIDTH(6)) sum_arr_dir23_52 (.y(sum_arr_dir23[52:57]), .a(sum_arr_lv1_0_b[52:57]));
//assign sum_arr_dir67[52:57] = (~(sum_arr_lv1_0_b[52:57])); // 4x --output--
tri_inv #(.WIDTH(6)) sum_arr_dir67_52 (.y(sum_arr_dir67[52:57]), .a(sum_arr_lv1_0_b[52:57]));
// ######################################################################
// ## this experimental piece is for directory read/write collisions
// ######################################################################
assign ary_write_act_01 = rel4_dir_wr_val & (way[0] | way[1]);
assign ary_write_act_23 = rel4_dir_wr_val & (way[2] | way[3]);
assign ary_write_act_45 = rel4_dir_wr_val & (way[4] | way[5]);
assign ary_write_act_67 = rel4_dir_wr_val & (way[6] | way[7]);
endmodule |
module iuq_axu_fu_rn #(
parameter FPR_POOL = 64,
parameter FPR_UCODE_POOL = 4,
parameter FPSCR_POOL_ENC = 5)
(
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types
input pc_iu_sg_2,
input clkoff_b,
input act_dis,
input tc_ac_ccflush_dc,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input func_scan_in,
output func_scan_out,
//-----------------------------
// Inputs to rename from decode
//-----------------------------
input iu_au_iu5_i0_vld,
input [0:2] iu_au_iu5_i0_ucode,
input iu_au_iu5_i0_rte_lq,
input iu_au_iu5_i0_rte_sq,
input iu_au_iu5_i0_rte_fx0,
input iu_au_iu5_i0_rte_fx1,
input iu_au_iu5_i0_rte_axu0,
input iu_au_iu5_i0_rte_axu1,
input iu_au_iu5_i0_ord,
input iu_au_iu5_i0_cord,
input [0:31] iu_au_iu5_i0_instr,
input [62-`EFF_IFAR_WIDTH:61] iu_au_iu5_i0_ifar,
input [0:9] iu_au_iu5_i0_gshare,
input [0:3] iu_au_iu5_i0_ilat,
input iu_au_iu5_i0_isload,
input iu_au_iu5_i0_t1_v,
input [0:2] iu_au_iu5_i0_t1_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_t1_a,
input iu_au_iu5_i0_t2_v,
input [0:2] iu_au_iu5_i0_t2_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_t2_a,
input iu_au_iu5_i0_t3_v,
input [0:2] iu_au_iu5_i0_t3_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_t3_a,
input iu_au_iu5_i0_s1_v,
input [0:2] iu_au_iu5_i0_s1_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_s1_a,
input iu_au_iu5_i0_s2_v,
input [0:2] iu_au_iu5_i0_s2_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_s2_a,
input iu_au_iu5_i0_s3_v,
input [0:2] iu_au_iu5_i0_s3_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_s3_a,
input iu_au_iu5_i1_vld,
input [0:2] iu_au_iu5_i1_ucode,
input iu_au_iu5_i1_rte_lq,
input iu_au_iu5_i1_rte_sq,
input iu_au_iu5_i1_rte_fx0,
input iu_au_iu5_i1_rte_fx1,
input iu_au_iu5_i1_rte_axu0,
input iu_au_iu5_i1_rte_axu1,
input iu_au_iu5_i1_ord,
input iu_au_iu5_i1_cord,
input [0:31] iu_au_iu5_i1_instr,
input [62-`EFF_IFAR_WIDTH:61] iu_au_iu5_i1_ifar,
input [0:9] iu_au_iu5_i1_gshare,
input [0:3] iu_au_iu5_i1_ilat,
input iu_au_iu5_i1_isload,
input iu_au_iu5_i1_t1_v,
input [0:2] iu_au_iu5_i1_t1_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_t1_a,
input iu_au_iu5_i1_t2_v,
input [0:2] iu_au_iu5_i1_t2_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_t2_a,
input iu_au_iu5_i1_t3_v,
input [0:2] iu_au_iu5_i1_t3_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_t3_a,
input iu_au_iu5_i1_s1_v,
input [0:2] iu_au_iu5_i1_s1_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_s1_a,
input iu_au_iu5_i1_s2_v,
input [0:2] iu_au_iu5_i1_s2_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_s2_a,
input iu_au_iu5_i1_s3_v,
input [0:2] iu_au_iu5_i1_s3_t,
input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_s3_a,
//-----------------------------
// SPR values
//-----------------------------
input spr_single_issue,
//-----------------------------
// Stall to decode
//-----------------------------
output au_iu_iu5_stall,
//----------------------------
// Completion Interface
//----------------------------
input cp_rn_i0_axu_exception_val,
input [0:3] cp_rn_i0_axu_exception,
input [0:`ITAG_SIZE_ENC-1] cp_rn_i0_itag,
input cp_rn_i0_t1_v,
input [0:2] cp_rn_i0_t1_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_a,
input cp_rn_i0_t2_v,
input [0:2] cp_rn_i0_t2_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_a,
input cp_rn_i0_t3_v,
input [0:2] cp_rn_i0_t3_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_a,
input cp_rn_i1_axu_exception_val,
input [0:3] cp_rn_i1_axu_exception,
input [0:`ITAG_SIZE_ENC-1] cp_rn_i1_itag,
input cp_rn_i1_t1_v,
input [0:2] cp_rn_i1_t1_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_a,
input cp_rn_i1_t2_v,
input [0:2] cp_rn_i1_t2_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_a,
input cp_rn_i1_t3_v,
input [0:2] cp_rn_i1_t3_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_a,
input cp_flush,
input br_iu_redirect,
//----------------------------------------------------------------
// Interface to Rename
//----------------------------------------------------------------
input iu_au_iu5_send_ok,
input [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i0,
input [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i1,
output au_iu_iu5_axu0_send_ok,
output au_iu_iu5_axu1_send_ok,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t1_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t2_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t3_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s1_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s2_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s3_p,
output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s1_itag,
output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s2_itag,
output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s3_itag,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t1_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t2_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t3_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s1_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s2_p,
output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s3_p,
output au_iu_iu5_i1_s1_dep_hit,
output au_iu_iu5_i1_s2_dep_hit,
output au_iu_iu5_i1_s3_dep_hit,
output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s1_itag,
output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s2_itag,
output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s3_itag
);
parameter cp_flush_offset = 0;
parameter br_iu_hold_offset = cp_flush_offset + 1;
parameter scan_right = br_iu_hold_offset + 1 - 1;
// scan
wire [0:scan_right] siv;
wire [0:scan_right] sov;
wire [0:1] map_siv;
wire [0:1] map_sov;
wire tidn;
wire tiup;
// Latch to delay the flush signal
wire cp_flush_d;
wire cp_flush_l2;
wire br_iu_hold_d;
wire br_iu_hold_l2;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`GPR_POOL_ENC-1] fpr_iu5_i0_src1_p;
wire [0:`GPR_POOL_ENC-1] fpr_iu5_i0_src2_p;
wire [0:`GPR_POOL_ENC-1] fpr_iu5_i0_src3_p;
wire [0:`GPR_POOL_ENC-1] fpr_iu5_i1_src1_p;
wire [0:`GPR_POOL_ENC-1] fpr_iu5_i1_src2_p;
wire [0:`GPR_POOL_ENC-1] fpr_iu5_i1_src3_p;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i0_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i0_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i0_src3_itag;
wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i1_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i1_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i1_src3_itag;
// I1 dependency hit vs I0 for each source this is used by RV
wire fpr_s1_dep_hit;
wire fpr_s2_dep_hit;
wire fpr_s3_dep_hit;
// Free from completion to the fpr pool
wire fpr_cp_i0_wr_v;
wire [0:`GPR_POOL_ENC-1] fpr_cp_i0_wr_a;
wire [0:`GPR_POOL_ENC-1] fpr_cp_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] fpr_cp_i0_wr_itag;
wire fpr_cp_i1_wr_v;
wire [0:`GPR_POOL_ENC-1] fpr_cp_i1_wr_a;
wire [0:`GPR_POOL_ENC-1] fpr_cp_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] fpr_cp_i1_wr_itag;
wire fpr_spec_i0_wr_v;
wire fpr_spec_i0_wr_v_fast;
wire [0:`GPR_POOL_ENC-1] fpr_spec_i0_wr_a;
wire [0:`GPR_POOL_ENC-1] fpr_spec_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] fpr_spec_i0_wr_itag;
wire fpr_spec_i1_wr_v;
wire fpr_spec_i1_wr_v_fast;
wire [0:`GPR_POOL_ENC-1] fpr_spec_i1_wr_a;
wire [0:`GPR_POOL_ENC-1] fpr_spec_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] fpr_spec_i1_wr_itag;
wire next_fpr_0_v;
wire [0:`GPR_POOL_ENC-1] next_fpr_0;
wire next_fpr_1_v;
wire [0:`GPR_POOL_ENC-1] next_fpr_1;
wire fpscr_cp_i0_wr_v;
wire [0:FPSCR_POOL_ENC-1] fpscr_cp_i0_wr_a;
wire [0:FPSCR_POOL_ENC-1] fpscr_cp_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] fpscr_cp_i0_wr_itag;
wire fpscr_cp_i1_wr_v;
wire [0:FPSCR_POOL_ENC-1] fpscr_cp_i1_wr_a;
wire [0:FPSCR_POOL_ENC-1] fpscr_cp_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] fpscr_cp_i1_wr_itag;
wire fpscr_spec_i0_wr_v;
wire fpscr_spec_i0_wr_v_fast;
wire [0:FPSCR_POOL_ENC-1] fpscr_spec_i0_wr_a;
wire [0:FPSCR_POOL_ENC-1] fpscr_spec_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] fpscr_spec_i0_wr_itag;
wire fpscr_spec_i1_wr_v;
wire fpscr_spec_i1_wr_v_fast;
wire [0:FPSCR_POOL_ENC-1] fpscr_spec_i1_wr_a;
wire [0:FPSCR_POOL_ENC-1] fpscr_spec_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] fpscr_spec_i1_wr_itag;
wire next_fpscr_0_v;
wire [0:FPSCR_POOL_ENC-1] next_fpscr_0;
wire next_fpscr_1_v;
wire [0:FPSCR_POOL_ENC-1] next_fpscr_1;
wire [0:1] fpr_send_cnt;
wire [0:1] fpscr_send_cnt;
wire fpr_send_ok;
wire fpscr_send_ok;
wire send_instructions;
// Pervasive
wire pc_iu_func_sl_thold_1;
wire pc_iu_func_sl_thold_0;
wire pc_iu_func_sl_thold_0_b;
wire pc_iu_sg_1;
wire pc_iu_sg_0;
wire force_t;
// This signal compares credits left and issues LQ/FX instructions to FX when set
wire dual_issue_use_fx;
//--------------------------------------------------------------
assign tidn = 1'b0;
assign tiup = 1'b1;
assign cp_flush_d = cp_flush;
assign br_iu_hold_d = (br_iu_redirect | br_iu_hold_l2) & (~(cp_flush_l2));
assign fpr_send_cnt = ({(iu_au_iu5_i0_t2_v & (iu_au_iu5_i0_t2_t == `axu0_t)), (iu_au_iu5_i1_t2_v & (iu_au_iu5_i1_t2_t == `axu0_t))});
assign fpscr_send_cnt = ({(iu_au_iu5_i0_t1_v & (iu_au_iu5_i0_t1_t == `axu1_t)), (iu_au_iu5_i1_t1_v & (iu_au_iu5_i1_t1_t == `axu1_t))});
assign fpr_send_ok = (fpr_send_cnt == 2'b00) | ((fpr_send_cnt[0] ^ fpr_send_cnt[1]) & next_fpr_0_v) | (next_fpr_0_v & next_fpr_1_v);
assign fpscr_send_ok = (fpscr_send_cnt == 2'b00) | ((fpscr_send_cnt[0] ^ fpscr_send_cnt[1]) & next_fpscr_0_v) | (next_fpscr_0_v & next_fpscr_1_v);
assign au_iu_iu5_axu0_send_ok = fpr_send_ok & fpscr_send_ok;
assign au_iu_iu5_axu1_send_ok = 1'b1;
//todo... frn may not send instr due to other credits...
assign send_instructions = (fpr_send_ok & fpscr_send_ok & iu_au_iu5_send_ok & iu_au_iu5_i0_vld) & (~(br_iu_hold_l2));
assign dual_issue_use_fx = 1'b0;
//-----------------------------------------------------------------------
//-- Outputs
//-----------------------------------------------------------------------
assign au_iu_iu5_stall = (~(fpr_send_ok & fpscr_send_ok));
assign au_iu_iu5_i0_t1_p[0:`GPR_POOL_ENC - 1] = {2'b00,next_fpscr_0};
assign au_iu_iu5_i0_t2_p = next_fpr_0;
assign au_iu_iu5_i0_t3_p = 0;
assign au_iu_iu5_i0_s1_p = fpr_iu5_i0_src1_p;
assign au_iu_iu5_i0_s2_p = fpr_iu5_i0_src2_p;
assign au_iu_iu5_i0_s3_p = fpr_iu5_i0_src3_p;
assign au_iu_iu5_i0_s1_itag = fpr_iu5_i0_src1_itag;
assign au_iu_iu5_i0_s2_itag = fpr_iu5_i0_src2_itag;
assign au_iu_iu5_i0_s3_itag = fpr_iu5_i0_src3_itag;
assign au_iu_iu5_i1_t1_p[0:`GPR_POOL_ENC - 1] = {2'b00,next_fpscr_1};
assign au_iu_iu5_i1_t2_p = next_fpr_1;
assign au_iu_iu5_i1_t3_p = 0;
assign au_iu_iu5_i1_s1_p = fpr_iu5_i1_src1_p;
assign au_iu_iu5_i1_s2_p = fpr_iu5_i1_src2_p;
assign au_iu_iu5_i1_s3_p = fpr_iu5_i1_src3_p;
assign au_iu_iu5_i1_s1_itag = fpr_iu5_i1_src1_itag;
assign au_iu_iu5_i1_s2_itag = fpr_iu5_i1_src2_itag;
assign au_iu_iu5_i1_s3_itag = fpr_iu5_i1_src3_itag;
assign au_iu_iu5_i1_s1_dep_hit = fpr_s1_dep_hit & (iu_au_iu5_i1_s1_t == `axu0_t);
assign au_iu_iu5_i1_s2_dep_hit = fpr_s2_dep_hit & (iu_au_iu5_i1_s2_t == `axu0_t);
assign au_iu_iu5_i1_s3_dep_hit = fpr_s3_dep_hit & (iu_au_iu5_i1_s3_t == `axu0_t);
//-----------------------------------------------------------------------
//-- FPR Renamer
//-----------------------------------------------------------------------
// Gate the FPR write enable by killing its completion report to the rn mapper
assign fpr_cp_i0_wr_v = cp_rn_i0_t2_v & (cp_rn_i0_t2_t == `axu0_t) & (~(cp_rn_i0_axu_exception[0:3] == 4'b0101));
assign fpr_cp_i0_wr_a = cp_rn_i0_t2_a;
assign fpr_cp_i0_wr_p = cp_rn_i0_t2_p;
assign fpr_cp_i0_wr_itag = cp_rn_i0_itag;
assign fpr_cp_i1_wr_v = cp_rn_i1_t2_v & (cp_rn_i1_t2_t == `axu0_t) & (~(cp_rn_i1_axu_exception[0:3] == 4'b0101));
assign fpr_cp_i1_wr_a = cp_rn_i1_t2_a;
assign fpr_cp_i1_wr_p = cp_rn_i1_t2_p;
assign fpr_cp_i1_wr_itag = cp_rn_i1_itag;
assign fpr_spec_i0_wr_v = send_instructions & (~(fpr_send_cnt[0:1] == 2'b00));
assign fpr_spec_i0_wr_v_fast = (~(fpr_send_cnt[0:1] == 2'b00));
assign fpr_spec_i0_wr_a = (fpr_send_cnt[0] ? iu_au_iu5_i0_t2_a : 0) | (((~(fpr_send_cnt[0])) & fpr_send_cnt[1]) ? iu_au_iu5_i1_t2_a : 0);
assign fpr_spec_i0_wr_p = next_fpr_0;
assign fpr_spec_i0_wr_itag = (fpr_send_cnt[0] ? iu_au_iu5_next_itag_i0 : 0) | (((~(fpr_send_cnt[0])) & fpr_send_cnt[1]) ? iu_au_iu5_next_itag_i1 : 0);
assign fpr_spec_i1_wr_v = send_instructions & (fpr_send_cnt[0:1] == 2'b11);
assign fpr_spec_i1_wr_v_fast = (fpr_send_cnt[0:1] == 2'b11);
assign fpr_spec_i1_wr_a = iu_au_iu5_i1_t2_a;
assign fpr_spec_i1_wr_p = next_fpr_1;
assign fpr_spec_i1_wr_itag = iu_au_iu5_next_itag_i1;
assign fpr_s1_dep_hit = fpr_spec_i0_wr_v_fast & fpr_send_cnt[0] & (fpr_spec_i0_wr_a == iu_au_iu5_i1_s1_a);
assign fpr_s2_dep_hit = fpr_spec_i0_wr_v_fast & fpr_send_cnt[0] & (fpr_spec_i0_wr_a == iu_au_iu5_i1_s2_a);
assign fpr_s3_dep_hit = fpr_spec_i0_wr_v_fast & fpr_send_cnt[0] & (fpr_spec_i0_wr_a == iu_au_iu5_i1_s3_a);
iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((32 + FPR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(FPR_POOL), .STORAGE_WIDTH(`GPR_POOL_ENC)) fpr_rn_map(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.pc_iu_sg_0(pc_iu_sg_0),
.force_t(force_t),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.func_scan_in(map_siv[0]),
.func_scan_out(map_sov[0]),
.take_a(fpr_spec_i0_wr_v),
.take_b(fpr_spec_i1_wr_v),
.next_reg_a_val(next_fpr_0_v),
.next_reg_a(next_fpr_0),
.next_reg_b_val(next_fpr_1_v),
.next_reg_b(next_fpr_1),
.src1_a(iu_au_iu5_i0_s1_a), //fdec_frn_iu5_i0_s1_a,
.src1_p(fpr_iu5_i0_src1_p),
.src1_itag(fpr_iu5_i0_src1_itag),
.src2_a(iu_au_iu5_i0_s2_a), //fdec_frn_iu5_i0_s2_a,
.src2_p(fpr_iu5_i0_src2_p),
.src2_itag(fpr_iu5_i0_src2_itag),
.src3_a(iu_au_iu5_i0_s3_a), //fdec_frn_iu5_i0_s3_a,
.src3_p(fpr_iu5_i0_src3_p),
.src3_itag(fpr_iu5_i0_src3_itag),
.src4_a(iu_au_iu5_i1_s1_a), //fdec_frn_iu5_i1_s1_a,
.src4_p(fpr_iu5_i1_src1_p),
.src4_itag(fpr_iu5_i1_src1_itag),
.src5_a(iu_au_iu5_i1_s2_a), //fdec_frn_iu5_i1_s2_a,
.src5_p(fpr_iu5_i1_src2_p),
.src5_itag(fpr_iu5_i1_src2_itag),
.src6_a(iu_au_iu5_i1_s3_a), //fdec_frn_iu5_i1_s3_a,
.src6_p(fpr_iu5_i1_src3_p),
.src6_itag(fpr_iu5_i1_src3_itag),
.comp_0_wr_val(fpr_cp_i0_wr_v),
.comp_0_wr_arc(fpr_cp_i0_wr_a),
.comp_0_wr_rename(fpr_cp_i0_wr_p),
.comp_0_wr_itag(fpr_cp_i0_wr_itag),
.comp_1_wr_val(fpr_cp_i1_wr_v),
.comp_1_wr_arc(fpr_cp_i1_wr_a),
.comp_1_wr_rename(fpr_cp_i1_wr_p),
.comp_1_wr_itag(fpr_cp_i1_wr_itag),
.spec_0_wr_val(fpr_spec_i0_wr_v),
.spec_0_wr_val_fast(fpr_spec_i0_wr_v_fast),
.spec_0_wr_arc(fpr_spec_i0_wr_a),
.spec_0_wr_rename(fpr_spec_i0_wr_p),
.spec_0_wr_itag(fpr_spec_i0_wr_itag),
.spec_1_dep_hit_s1(fpr_s1_dep_hit),
.spec_1_dep_hit_s2(fpr_s2_dep_hit),
.spec_1_dep_hit_s3(fpr_s3_dep_hit),
.spec_1_wr_val(fpr_spec_i1_wr_v),
.spec_1_wr_val_fast(fpr_spec_i1_wr_v_fast),
.spec_1_wr_arc(fpr_spec_i1_wr_a),
.spec_1_wr_rename(fpr_spec_i1_wr_p),
.spec_1_wr_itag(fpr_spec_i1_wr_itag),
.flush_map(cp_flush_l2)
);
//-----------------------------------------------------------------------
//-- FPSCR Renamer
//-----------------------------------------------------------------------
assign fpscr_cp_i0_wr_v = cp_rn_i0_t1_v & (cp_rn_i0_t1_t == `axu1_t);
assign fpscr_cp_i0_wr_a = cp_rn_i0_t1_a[1:`GPR_POOL_ENC - 1];
assign fpscr_cp_i0_wr_p = cp_rn_i0_t1_p[1:`GPR_POOL_ENC - 1];
assign fpscr_cp_i0_wr_itag = cp_rn_i0_itag;
assign fpscr_cp_i1_wr_v = cp_rn_i1_t1_v & (cp_rn_i1_t1_t == `axu1_t);
assign fpscr_cp_i1_wr_a = cp_rn_i1_t1_a[1:`GPR_POOL_ENC - 1];
assign fpscr_cp_i1_wr_p = cp_rn_i1_t1_p[1:`GPR_POOL_ENC - 1];
assign fpscr_cp_i1_wr_itag = cp_rn_i1_itag;
assign fpscr_spec_i0_wr_v = send_instructions & (~(fpscr_send_cnt[0:1] == 2'b00));
assign fpscr_spec_i0_wr_v_fast = (~(fpscr_send_cnt[0:1] == 2'b00));
assign fpscr_spec_i0_wr_a = (fpscr_send_cnt[0] ? iu_au_iu5_i0_t1_a[1:`GPR_POOL_ENC - 1] : 0) | (((~(fpscr_send_cnt[0])) & fpscr_send_cnt[1]) ? iu_au_iu5_i1_t1_a[1:`GPR_POOL_ENC - 1] : 0);
assign fpscr_spec_i0_wr_p = next_fpscr_0;
assign fpscr_spec_i0_wr_itag = (fpscr_send_cnt[0] ? iu_au_iu5_next_itag_i0 : 0) | (((~(fpscr_send_cnt[0])) & fpscr_send_cnt[1]) ? iu_au_iu5_next_itag_i1 : 0);
assign fpscr_spec_i1_wr_v = send_instructions & (fpscr_send_cnt[0:1] == 2'b11);
assign fpscr_spec_i1_wr_v_fast = (fpscr_send_cnt[0:1] == 2'b11);
assign fpscr_spec_i1_wr_a = iu_au_iu5_i1_t1_a[1:`GPR_POOL_ENC - 1];
assign fpscr_spec_i1_wr_p = next_fpscr_1;
assign fpscr_spec_i1_wr_itag = iu_au_iu5_next_itag_i1;
`ifndef THREADS1
// 24 entries per thread for dual thread
iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(24), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC)
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.pc_iu_sg_0(pc_iu_sg_0),
.force_t(force_t),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.func_scan_in(map_siv[1]),
.func_scan_out(map_sov[1]),
.take_a(fpscr_spec_i0_wr_v),
.take_b(fpscr_spec_i1_wr_v),
.next_reg_a_val(next_fpscr_0_v),
.next_reg_a(next_fpscr_0),
.next_reg_b_val(next_fpscr_1_v),
.next_reg_b(next_fpscr_1),
.src1_a(iu_au_iu5_i0_s1_a[1:`GPR_POOL_ENC - 1]),
.src1_p(),
.src1_itag(),
.src2_a(iu_au_iu5_i0_s2_a[1:`GPR_POOL_ENC - 1]),
.src2_p(),
.src2_itag(),
.src3_a(iu_au_iu5_i0_s3_a[1:`GPR_POOL_ENC - 1]),
.src3_p(),
.src3_itag(),
.src4_a(iu_au_iu5_i1_s1_a[1:`GPR_POOL_ENC - 1]),
.src4_p(),
.src4_itag(),
.src5_a(iu_au_iu5_i1_s2_a[1:`GPR_POOL_ENC - 1]),
.src5_p(),
.src5_itag(),
.src6_a(iu_au_iu5_i1_s3_a[1:`GPR_POOL_ENC - 1]),
.src6_p(),
.src6_itag(),
.comp_0_wr_val(fpscr_cp_i0_wr_v),
.comp_0_wr_arc(fpscr_cp_i0_wr_a),
.comp_0_wr_rename(fpscr_cp_i0_wr_p),
.comp_0_wr_itag(fpscr_cp_i0_wr_itag),
.comp_1_wr_val(fpscr_cp_i1_wr_v),
.comp_1_wr_arc(fpscr_cp_i1_wr_a),
.comp_1_wr_rename(fpscr_cp_i1_wr_p),
.comp_1_wr_itag(fpscr_cp_i1_wr_itag),
.spec_0_wr_val(fpscr_spec_i0_wr_v),
.spec_0_wr_val_fast(fpscr_spec_i0_wr_v_fast),
.spec_0_wr_arc(fpscr_spec_i0_wr_a),
.spec_0_wr_rename(fpscr_spec_i0_wr_p),
.spec_0_wr_itag(fpscr_spec_i0_wr_itag),
.spec_1_dep_hit_s1(gnd),
.spec_1_dep_hit_s2(gnd),
.spec_1_dep_hit_s3(gnd),
.spec_1_wr_val(fpscr_spec_i1_wr_v),
.spec_1_wr_val_fast(fpscr_spec_i1_wr_v_fast),
.spec_1_wr_arc(fpscr_spec_i1_wr_a),
.spec_1_wr_rename(fpscr_spec_i1_wr_p),
.spec_1_wr_itag(fpscr_spec_i1_wr_itag),
.flush_map(cp_flush_l2)
);
`else
// 32 if single thread
iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(32), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC)
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.pc_iu_sg_0(pc_iu_sg_0),
.force_t(force_t),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.func_scan_in(map_siv[1]),
.func_scan_out(map_sov[1]),
.take_a(fpscr_spec_i0_wr_v),
.take_b(fpscr_spec_i1_wr_v),
.next_reg_a_val(next_fpscr_0_v),
.next_reg_a(next_fpscr_0),
.next_reg_b_val(next_fpscr_1_v),
.next_reg_b(next_fpscr_1),
.src1_a(iu_au_iu5_i0_s1_a[1:`GPR_POOL_ENC - 1]),
.src1_p(),
.src1_itag(),
.src2_a(iu_au_iu5_i0_s2_a[1:`GPR_POOL_ENC - 1]),
.src2_p(),
.src2_itag(),
.src3_a(iu_au_iu5_i0_s3_a[1:`GPR_POOL_ENC - 1]),
.src3_p(),
.src3_itag(),
.src4_a(iu_au_iu5_i1_s1_a[1:`GPR_POOL_ENC - 1]),
.src4_p(),
.src4_itag(),
.src5_a(iu_au_iu5_i1_s2_a[1:`GPR_POOL_ENC - 1]),
.src5_p(),
.src5_itag(),
.src6_a(iu_au_iu5_i1_s3_a[1:`GPR_POOL_ENC - 1]),
.src6_p(),
.src6_itag(),
.comp_0_wr_val(fpscr_cp_i0_wr_v),
.comp_0_wr_arc(fpscr_cp_i0_wr_a),
.comp_0_wr_rename(fpscr_cp_i0_wr_p),
.comp_0_wr_itag(fpscr_cp_i0_wr_itag),
.comp_1_wr_val(fpscr_cp_i1_wr_v),
.comp_1_wr_arc(fpscr_cp_i1_wr_a),
.comp_1_wr_rename(fpscr_cp_i1_wr_p),
.comp_1_wr_itag(fpscr_cp_i1_wr_itag),
.spec_0_wr_val(fpscr_spec_i0_wr_v),
.spec_0_wr_val_fast(fpscr_spec_i0_wr_v_fast),
.spec_0_wr_arc(fpscr_spec_i0_wr_a),
.spec_0_wr_rename(fpscr_spec_i0_wr_p),
.spec_0_wr_itag(fpscr_spec_i0_wr_itag),
.spec_1_dep_hit_s1(gnd),
.spec_1_dep_hit_s2(gnd),
.spec_1_dep_hit_s3(gnd),
.spec_1_wr_val(fpscr_spec_i1_wr_v),
.spec_1_wr_val_fast(fpscr_spec_i1_wr_v_fast),
.spec_1_wr_arc(fpscr_spec_i1_wr_a),
.spec_1_wr_rename(fpscr_spec_i1_wr_p),
.spec_1_wr_itag(fpscr_spec_i1_wr_itag),
.flush_map(cp_flush_l2)
);
`endif
tri_rlmlatch_p #(.INIT(0)) cp_flush_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[cp_flush_offset]),
.scout(sov[cp_flush_offset]),
.din(cp_flush_d),
.dout(cp_flush_l2)
);
tri_rlmlatch_p #(.INIT(0)) br_iu_hold_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[br_iu_hold_offset]),
.scout(sov[br_iu_hold_offset]),
.din(br_iu_hold_d),
.dout(br_iu_hold_l2)
);
//-----------------------------------------------
// pervasive
//-----------------------------------------------
tri_plat #(.WIDTH(2)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2,pc_iu_sg_2}),
.q({pc_iu_func_sl_thold_1,pc_iu_sg_1})
);
tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1,pc_iu_sg_1}),
.q({pc_iu_func_sl_thold_0,pc_iu_sg_0})
);
tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b),
.thold(pc_iu_func_sl_thold_0),
.sg(pc_iu_sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b)
);
assign map_siv = {func_scan_in, map_sov[0]};
assign siv = {sov[1:scan_right], map_sov[1]};
assign func_scan_out = sov[0];
endmodule |
module rv_fx1_rvs(
`include "tri_a2o.vh"
//------------------------------------------------------------------------------------------------------------
// Instructions from RV_DEP
//------------------------------------------------------------------------------------------------------------
input [0:`THREADS-1] rv0_instr_i0_vld,
input rv0_instr_i0_rte_fx1,
input [0:`THREADS-1] rv0_instr_i1_vld,
input rv0_instr_i1_rte_fx1,
input [0:31] rv0_instr_i0_instr,
input [0:2] rv0_instr_i0_ucode,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag,
input rv0_instr_i0_t1_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t1_p,
input rv0_instr_i0_t2_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t2_p,
input rv0_instr_i0_t3_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t3_p,
input rv0_instr_i0_s1_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s1_p,
input [0:2] rv0_instr_i0_s1_t,
input rv0_instr_i0_s2_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s2_p,
input [0:2] rv0_instr_i0_s2_t,
input rv0_instr_i0_s3_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s3_p,
input [0:2] rv0_instr_i0_s3_t,
input [0:3] rv0_instr_i0_ilat,
input rv0_instr_i0_isStore,
input [0:3] rv0_instr_i0_spare,
input rv0_instr_i0_is_brick,
input [0:2] rv0_instr_i0_brick,
input [0:31] rv0_instr_i1_instr,
input [0:2] rv0_instr_i1_ucode,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag,
input rv0_instr_i1_t1_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t1_p,
input rv0_instr_i1_t2_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t2_p,
input rv0_instr_i1_t3_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t3_p,
input rv0_instr_i1_s1_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s1_p,
input [0:2] rv0_instr_i1_s1_t,
input rv0_instr_i1_s2_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s2_p,
input [0:2] rv0_instr_i1_s2_t,
input rv0_instr_i1_s3_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s3_p,
input [0:2] rv0_instr_i1_s3_t,
input [0:3] rv0_instr_i1_ilat,
input rv0_instr_i1_isStore,
input [0:3] rv0_instr_i1_spare,
input rv0_instr_i1_is_brick,
input [0:2] rv0_instr_i1_brick,
input rv0_instr_i0_s1_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag,
input rv0_instr_i0_s2_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag,
input rv0_instr_i0_s3_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag,
input rv0_instr_i1_s1_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag,
input rv0_instr_i1_s2_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag,
input rv0_instr_i1_s3_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag,
//------------------------------------------------------------------------------------------------------------
// Credit Interface with IU
//------------------------------------------------------------------------------------------------------------
output [0:`THREADS-1] rv_iu_fx1_credit_free,
//------------------------------------------------------------------------------------------------------------
// Machine zap interface
//------------------------------------------------------------------------------------------------------------
input [0:`THREADS-1] cp_flush,
//------------------------------------------------------------------------------------------------------------
// Interface to fx1
//------------------------------------------------------------------------------------------------------------
output [0:`THREADS-1] rv_fx1_vld,
output rv_fx1_s1_v,
output [0:`GPR_POOL_ENC-1] rv_fx1_s1_p,
output rv_fx1_s2_v,
output [0:`GPR_POOL_ENC-1] rv_fx1_s2_p,
output rv_fx1_s3_v,
output [0:`GPR_POOL_ENC-1] rv_fx1_s3_p,
output [0:`THREADS-1] rv_byp_fx1_vld,
output [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_itag,
output rv_byp_fx1_t1_v,
output rv_byp_fx1_t2_v,
output rv_byp_fx1_t3_v,
output [0:2] rv_byp_fx1_s1_t,
output [0:2] rv_byp_fx1_s2_t,
output [0:2] rv_byp_fx1_s3_t,
output [0:3] rv_byp_fx1_ilat,
output rv_byp_fx1_ex0_isStore,
output [0:`ITAG_SIZE_ENC-1] rv_fx1_ex0_itag,
output [0:31] rv_fx1_ex0_instr,
output [0:2] rv_fx1_ex0_ucode,
output rv_fx1_ex0_t1_v,
output [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t1_p,
output rv_fx1_ex0_t2_v,
output [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t2_p,
output rv_fx1_ex0_t3_v,
output [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t3_p,
output rv_fx1_ex0_s1_v,
output [0:2] rv_fx1_ex0_s3_t,
output rv_fx1_ex0_isStore,
output [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_s1_itag,
output [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_s2_itag,
output [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_s3_itag,
//------------------------------------------------------------------------------------------------------------
// RV Release bus
//------------------------------------------------------------------------------------------------------------
input fx1_rv_ex2_s1_abort,
input fx1_rv_ex2_s2_abort,
input fx1_rv_ex2_s3_abort,
input fx0_rv_itag_abort,
input fx1_rv_itag_abort,
input lq_rv_ext_itag0_abort,
input lq_rv_ext_itag1_abort,
input axu1_rv_ext_itag_abort,
input axu0_rv_ext_itag_abort,
input [0:`THREADS-1] fx0_rv_itag_vld,
input [0:`ITAG_SIZE_ENC-1] fx0_rv_itag,
input [0:`THREADS-1] fx1_rv_itag_vld,
input [0:`ITAG_SIZE_ENC-1] fx1_rv_itag,
input [0:`THREADS-1] axu0_rv_ext_itag_vld,
input [0:`ITAG_SIZE_ENC-1] axu0_rv_ext_itag,
input [0:`THREADS-1] axu1_rv_ext_itag_vld,
input [0:`ITAG_SIZE_ENC-1] axu1_rv_ext_itag,
input [0:`THREADS-1] lq_rv_ext_itag0_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag0,
input [0:`THREADS-1] lq_rv_itag1_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1,
input lq_rv_itag1_restart,
input lq_rv_itag1_hold,
input [0:`THREADS-1] lq_rv_ext_itag1_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag1,
input [0:`THREADS-1] lq_rv_ext_itag2_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag2,
input [0:`THREADS-1] lq_rv_clr_hold,
input fx1_rv_hold_all,
output [0:`THREADS-1] rv_byp_fx1_ilat0_vld,
output [0:`THREADS-1] rv_byp_fx1_ilat1_vld,
input [0:`THREADS-1] rv1_fx0_ilat0_vld,
input [0:`ITAG_SIZE_ENC-1] rv1_fx0_ilat0_itag,
output [0:`THREADS-1] rv1_fx1_ilat0_vld,
output [0:`ITAG_SIZE_ENC-1] rv1_fx1_ilat0_itag,
//------------------------------------------------------------------------------------------------------------
// Pervasive
//------------------------------------------------------------------------------------------------------------
output [0:8*`THREADS-1] fx1_rvs_perf_bus,
output [0:31] fx1_rvs_dbg_bus,
inout vdd,
inout gnd,
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk
input [0:`NCLK_WIDTH-1] nclk,
input func_sl_thold_1,
input sg_1,
input clkoff_b,
input act_dis,
input ccflush_dc,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input scan_in,
output scan_out
);
parameter num_itag_busses_g = 7;
//------------------------------------------------------------------------------------------------------------
// RV FX1 RVS INSTR ISSUE
//------------------------------------------------------------------------------------------------------------
parameter rvfx1_ex0_start = 0;
parameter rvfx1_instr_start = rvfx1_ex0_start;
parameter rvfx1_instr_stop = (rvfx1_instr_start + (32)) - 1;
parameter rvfx1_ucode_start = rvfx1_instr_stop + 1;
parameter rvfx1_ucode_stop = (rvfx1_ucode_start + (3)) - 1;
parameter rvfx1_t1_p_start = rvfx1_ucode_stop + 1;
parameter rvfx1_t1_p_stop = (rvfx1_t1_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvfx1_t2_p_start = rvfx1_t1_p_stop + 1;
parameter rvfx1_t2_p_stop = (rvfx1_t2_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvfx1_t3_p_start = rvfx1_t2_p_stop + 1;
parameter rvfx1_t3_p_stop = (rvfx1_t3_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvfx1_isStore_start = rvfx1_t3_p_stop + 1;
parameter rvfx1_isStore_stop = (rvfx1_isStore_start + (1)) - 1;
parameter rvfx1_spare_start = rvfx1_isStore_stop + 1;
parameter rvfx1_spare_stop = (rvfx1_spare_start + (4)) - 1;
parameter rvfx1_ex0_end = rvfx1_spare_stop;
parameter rvfx1_ex0_size = rvfx1_ex0_end + 1;
parameter rvfx1_start = 0;
parameter rvfx1_t1_v_start = rvfx1_start;
parameter rvfx1_t1_v_stop = (rvfx1_t1_v_start + (1)) - 1;
parameter rvfx1_t2_v_start = rvfx1_t1_v_stop + 1;
parameter rvfx1_t2_v_stop = (rvfx1_t2_v_start + (1)) - 1;
parameter rvfx1_t3_v_start = rvfx1_t2_v_stop + 1;
parameter rvfx1_t3_v_stop = (rvfx1_t3_v_start + (1)) - 1;
parameter rvfx1_s1_v_start = rvfx1_t3_v_stop + 1;
parameter rvfx1_s1_v_stop = (rvfx1_s1_v_start + (1)) - 1;
parameter rvfx1_s1_p_start = rvfx1_s1_v_stop + 1;
parameter rvfx1_s1_p_stop = (rvfx1_s1_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvfx1_s1_t_start = rvfx1_s1_p_stop + 1;
parameter rvfx1_s1_t_stop = (rvfx1_s1_t_start + (3)) - 1;
parameter rvfx1_s2_v_start = rvfx1_s1_t_stop + 1;
parameter rvfx1_s2_v_stop = (rvfx1_s2_v_start + (1)) - 1;
parameter rvfx1_s2_p_start = rvfx1_s2_v_stop + 1;
parameter rvfx1_s2_p_stop = (rvfx1_s2_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvfx1_s2_t_start = rvfx1_s2_p_stop + 1;
parameter rvfx1_s2_t_stop = (rvfx1_s2_t_start + (3)) - 1;
parameter rvfx1_s3_v_start = rvfx1_s2_t_stop + 1;
parameter rvfx1_s3_v_stop = (rvfx1_s3_v_start + (1)) - 1;
parameter rvfx1_s3_p_start = rvfx1_s3_v_stop + 1;
parameter rvfx1_s3_p_stop = (rvfx1_s3_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvfx1_s3_t_start = rvfx1_s3_p_stop + 1;
parameter rvfx1_s3_t_stop = (rvfx1_s3_t_start + (3)) - 1;
parameter rvfx1_end = rvfx1_s3_t_stop;
parameter rvfx1_size = rvfx1_end + 1;
//------------------------------------------------------------------------------------------------------------
// Pervasive
//------------------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------------------
// RV1
//------------------------------------------------------------------------------------------------------------
wire [rvfx1_start:rvfx1_end] rv0_instr_i0_dat;
wire [rvfx1_start:rvfx1_end] rv0_instr_i1_dat;
wire [rvfx1_ex0_start:rvfx1_ex0_end] rv0_instr_i0_dat_ex0;
wire [rvfx1_ex0_start:rvfx1_ex0_end] rv0_instr_i1_dat_ex0;
wire rv0_instr_i0_ord;
wire rv0_instr_i0_cord;
wire rv0_instr_i0_spec;
wire rv0_instr_i1_ord;
wire rv0_instr_i1_cord;
wire rv0_instr_i1_spec;
wire rv0_i0_s1_v;
wire [0:`GPR_POOL_ENC-1] rv0_i0_s1_p;
wire [0:2] rv0_i0_s1_t;
wire rv0_i1_s1_v;
wire [0:`GPR_POOL_ENC-1] rv0_i1_s1_p;
wire [0:2] rv0_i1_s1_t;
wire rv0_i0_s1_dep_hit;
wire [0:`ITAG_SIZE_ENC-1] rv0_i0_s1_itag;
wire rv0_i1_s1_dep_hit;
wire [0:`ITAG_SIZE_ENC-1] rv0_i1_s1_itag;
wire [0:`THREADS-1] fx1_rv_ord_complete;
//------------------------------------------------------------------------------------------------------------
// RV2
//------------------------------------------------------------------------------------------------------------
wire [rvfx1_start:rvfx1_end] rv1_instr_dat;
wire [0:`THREADS-1] rv1_instr_v;
wire [0:`THREADS-1] rv1_instr_ilat0_vld;
wire [0:`THREADS-1] rv1_instr_ilat1_vld;
wire [0:3] rv1_instr_ilat;
wire [0:`ITAG_SIZE_ENC-1] rv1_instr_itag;
wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s1_itag;
wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s2_itag;
wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s3_itag;
wire [0:`THREADS-1] ex1_credit_free;
//------------------------------------------------------------------------------------------------------------
// EX0
//------------------------------------------------------------------------------------------------------------
wire rv_ex0_act;
(* analysis_not_referenced="<54:57>true" *)
wire [rvfx1_ex0_start:rvfx1_ex0_end] ex0_instr_dat;
wire [0:`ITAG_SIZE_ENC-1] ex0_itag_d;
wire ex0_t1_v_d;
wire ex0_t2_v_d;
wire ex0_t3_v_d;
wire ex0_s1_v_d;
wire [0:2] ex0_s3_t_d;
wire [0:`ITAG_SIZE_ENC-1] ex0_itag_q;
wire ex0_t1_v_q;
wire ex0_t2_v_q;
wire ex0_t3_v_q;
wire ex0_s1_v_q;
wire [0:2] ex0_s3_t_q;
//------------------------------------------------------------------------------------------------------------
// Itag busses and shadow
//------------------------------------------------------------------------------------------------------------
wire [0:`THREADS-1] lq_rv_itag1_rst_vld;
wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst;
wire [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag;
//------------------------------------------------------------------------------------------------------------
// Scan Chains
//------------------------------------------------------------------------------------------------------------
parameter rvs_offset = 0 + 0;
parameter ex0_itag_offset = rvs_offset + 1;
parameter ex0_t1_v_offset = ex0_itag_offset + `ITAG_SIZE_ENC;
parameter ex0_t2_v_offset = ex0_t1_v_offset + 1;
parameter ex0_t3_v_offset = ex0_t2_v_offset + 1;
parameter ex0_s1_v_offset = ex0_t3_v_offset + 1;
parameter ex0_s3_t_offset = ex0_s1_v_offset + 1;
parameter scan_right = ex0_s3_t_offset + 3;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
wire func_sl_thold_0;
wire func_sl_thold_0_b;
wire sg_0;
wire force_t;
// Unused Nets
(* analysis_not_referenced="true" *)
wire [0:`THREADS-1] q_ord_tid;
(* analysis_not_referenced="true" *)
wire rvs_empty;
(* analysis_not_referenced="true" *)
wire rv1_instr_is_brick;
(* analysis_not_referenced="true" *)
wire rv1_instr_ord;
(* analysis_not_referenced="true" *)
wire rv1_instr_spec;
//!! Bugspray Include: rv_fx1_rvs;
//------------------------------------------------------------------------------------------------------------
// Pervasive
//------------------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------------------
// Store Source Swizzle
//------------------------------------------------------------------------------------------------------------
assign rv0_i0_s1_v = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_v :
rv0_instr_i0_s1_v;
assign rv0_i0_s1_p = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_p :
rv0_instr_i0_s1_p;
assign rv0_i0_s1_t = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_t :
rv0_instr_i0_s1_t;
assign rv0_i0_s1_dep_hit = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_dep_hit :
rv0_instr_i0_s1_dep_hit;
assign rv0_i0_s1_itag = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_itag :
rv0_instr_i0_s1_itag;
assign rv0_i1_s1_v = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_v :
rv0_instr_i1_s1_v;
assign rv0_i1_s1_p = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_p :
rv0_instr_i1_s1_p;
assign rv0_i1_s1_t = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_t :
rv0_instr_i1_s1_t;
assign rv0_i1_s1_dep_hit = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_dep_hit :
rv0_instr_i1_s1_dep_hit;
assign rv0_i1_s1_itag = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_itag :
rv0_instr_i1_s1_itag;
//------------------------------------------------------------------------------------------------------------
// RV Entry
//------------------------------------------------------------------------------------------------------------
assign rv0_instr_i0_dat = {(rv0_instr_i0_t1_v & (~rv0_instr_i0_isStore)),
(rv0_instr_i0_t2_v & (~rv0_instr_i0_isStore)),
(rv0_instr_i0_t3_v & (~rv0_instr_i0_isStore)),
rv0_i0_s1_v,
rv0_i0_s1_p,
rv0_i0_s1_t,
rv0_instr_i0_s2_v,
rv0_instr_i0_s2_p,
rv0_instr_i0_s2_t,
rv0_instr_i0_s3_v,
rv0_instr_i0_s3_p,
rv0_instr_i0_s3_t};
assign rv0_instr_i0_dat_ex0 = {rv0_instr_i0_instr,
rv0_instr_i0_ucode,
rv0_instr_i0_t1_p,
rv0_instr_i0_t2_p,
rv0_instr_i0_t3_p,
rv0_instr_i0_isStore,
rv0_instr_i0_spare};
assign rv0_instr_i1_dat = {(rv0_instr_i1_t1_v & (~rv0_instr_i1_isStore)),
(rv0_instr_i1_t2_v & (~rv0_instr_i1_isStore)),
(rv0_instr_i1_t3_v & (~rv0_instr_i1_isStore)),
rv0_i1_s1_v,
rv0_i1_s1_p,
rv0_i1_s1_t,
rv0_instr_i1_s2_v,
rv0_instr_i1_s2_p,
rv0_instr_i1_s2_t,
rv0_instr_i1_s3_v,
rv0_instr_i1_s3_p,
rv0_instr_i1_s3_t};
assign rv0_instr_i1_dat_ex0 = {rv0_instr_i1_instr,
rv0_instr_i1_ucode,
rv0_instr_i1_t1_p,
rv0_instr_i1_t2_p,
rv0_instr_i1_t3_p,
rv0_instr_i1_isStore,
rv0_instr_i1_spare};
//------------------------------------------------------------------------------------------------------------
// fx1 Reservation Stations
//------------------------------------------------------------------------------------------------------------
assign rv0_instr_i0_ord = 1'b0;
assign rv0_instr_i0_cord = 1'b0;
assign rv0_instr_i0_spec = 1'b0;
assign rv0_instr_i1_ord = 1'b0;
assign rv0_instr_i1_cord = 1'b0;
assign rv0_instr_i1_spec = 1'b0;
assign lq_rv_itag1_cord = 1'b0;
assign fx1_rv_ord_complete = {`THREADS{1'b0}};
assign cp_next_itag = {`THREADS*`ITAG_SIZE_ENC{1'b0}};
rv_station #( .q_dat_width_g(rvfx1_size), .q_dat_ex0_width_g(rvfx1_ex0_size), .q_num_entries_g(`RV_FX1_ENTRIES), .q_itag_busses_g(num_itag_busses_g), .q_brick_g(1'b0))
rvs(
.cp_flush(cp_flush),
.cp_next_itag(cp_next_itag),
.rv0_instr_i0_vld(rv0_instr_i0_vld),
.rv0_instr_i0_rte(rv0_instr_i0_rte_fx1),
.rv0_instr_i1_vld(rv0_instr_i1_vld),
.rv0_instr_i1_rte(rv0_instr_i1_rte_fx1),
.rv0_instr_i0_dat(rv0_instr_i0_dat),
.rv0_instr_i0_dat_ex0(rv0_instr_i0_dat_ex0),
.rv0_instr_i0_itag(rv0_instr_i0_itag),
.rv0_instr_i0_ord(rv0_instr_i0_ord),
.rv0_instr_i0_cord(rv0_instr_i0_cord),
.rv0_instr_i0_spec(rv0_instr_i0_spec),
.rv0_instr_i0_s1_dep_hit(rv0_i0_s1_dep_hit),
.rv0_instr_i0_s1_itag(rv0_i0_s1_itag),
.rv0_instr_i0_s2_dep_hit(rv0_instr_i0_s2_dep_hit),
.rv0_instr_i0_s2_itag(rv0_instr_i0_s2_itag),
.rv0_instr_i0_s3_dep_hit(rv0_instr_i0_s3_dep_hit),
.rv0_instr_i0_s3_itag(rv0_instr_i0_s3_itag),
.rv0_instr_i0_is_brick(rv0_instr_i0_is_brick),
.rv0_instr_i0_brick(rv0_instr_i0_brick),
.rv0_instr_i0_ilat(rv0_instr_i0_ilat),
.rv0_instr_i0_s1_v(rv0_i0_s1_v), //swap
.rv0_instr_i0_s2_v(rv0_instr_i0_s2_v),
.rv0_instr_i0_s3_v(rv0_instr_i0_s3_v),
.rv0_instr_i1_dat(rv0_instr_i1_dat),
.rv0_instr_i1_dat_ex0(rv0_instr_i1_dat_ex0),
.rv0_instr_i1_itag(rv0_instr_i1_itag),
.rv0_instr_i1_ord(rv0_instr_i1_ord),
.rv0_instr_i1_cord(rv0_instr_i1_cord),
.rv0_instr_i1_spec(rv0_instr_i1_spec),
.rv0_instr_i1_s1_dep_hit(rv0_i1_s1_dep_hit),
.rv0_instr_i1_s1_itag(rv0_i1_s1_itag),
.rv0_instr_i1_s2_dep_hit(rv0_instr_i1_s2_dep_hit),
.rv0_instr_i1_s2_itag(rv0_instr_i1_s2_itag),
.rv0_instr_i1_s3_dep_hit(rv0_instr_i1_s3_dep_hit),
.rv0_instr_i1_s3_itag(rv0_instr_i1_s3_itag),
.rv0_instr_i1_is_brick(rv0_instr_i1_is_brick),
.rv0_instr_i1_brick(rv0_instr_i1_brick),
.rv0_instr_i1_ilat(rv0_instr_i1_ilat),
.rv0_instr_i1_s1_v(rv0_i1_s1_v), //swap
.rv0_instr_i1_s2_v(rv0_instr_i1_s2_v),
.rv0_instr_i1_s3_v(rv0_instr_i1_s3_v),
.rv1_instr_vld(rv1_instr_v),
.rv1_instr_dat(rv1_instr_dat),
.rv1_instr_ord(rv1_instr_ord),
.rv1_instr_spec(rv1_instr_spec),
.rv1_instr_itag(rv1_instr_itag),
.rv1_instr_ilat(rv1_instr_ilat),
.rv1_instr_ilat0_vld(rv1_instr_ilat0_vld),
.rv1_instr_ilat1_vld(rv1_instr_ilat1_vld),
.rv1_instr_s1_itag(rv1_instr_s1_itag),
.rv1_instr_s2_itag(rv1_instr_s2_itag),
.rv1_instr_s3_itag(rv1_instr_s3_itag),
.ex0_instr_dat(ex0_instr_dat),
.ex1_credit_free(ex1_credit_free),
.rv1_instr_is_brick(rv1_instr_is_brick),
.rv1_other_ilat0_vld(rv1_fx0_ilat0_vld),
.rv1_other_ilat0_itag(rv1_fx0_ilat0_itag),
.rv1_other_ilat0_vld_out(rv1_fx1_ilat0_vld),
.rv1_other_ilat0_itag_out(rv1_fx1_ilat0_itag),
.q_hold_all(fx1_rv_hold_all),
.q_ord_complete(fx1_rv_ord_complete),
.fx0_rv_itag (fx0_rv_itag),
.fx1_rv_itag (fx1_rv_itag),
.lq_rv_itag0 (lq_rv_ext_itag0),
.lq_rv_itag1 (lq_rv_ext_itag1),
.lq_rv_itag2 (lq_rv_ext_itag2),
.axu0_rv_itag (axu0_rv_ext_itag),
.axu1_rv_itag (axu1_rv_ext_itag),
.fx0_rv_itag_vld (fx0_rv_itag_vld),
.fx1_rv_itag_vld (fx1_rv_itag_vld),
.lq_rv_itag0_vld (lq_rv_ext_itag0_vld),
.lq_rv_itag1_vld (lq_rv_ext_itag1_vld),
.lq_rv_itag2_vld (lq_rv_ext_itag2_vld),
.axu0_rv_itag_vld (axu0_rv_ext_itag_vld),
.axu1_rv_itag_vld (axu1_rv_ext_itag_vld),
.fx0_rv_itag_abort (fx0_rv_itag_abort),
.fx1_rv_itag_abort (fx1_rv_itag_abort),
.lq_rv_itag0_abort (lq_rv_ext_itag0_abort),
.lq_rv_itag1_abort (lq_rv_ext_itag1_abort),
.axu0_rv_itag_abort (axu0_rv_ext_itag_abort),
.axu1_rv_itag_abort (axu1_rv_ext_itag_abort),
.xx_rv_ex2_s1_abort(fx1_rv_ex2_s1_abort),
.xx_rv_ex2_s2_abort(fx1_rv_ex2_s2_abort),
.xx_rv_ex2_s3_abort(fx1_rv_ex2_s3_abort),
.lq_rv_itag1_restart(lq_rv_itag1_restart),
.lq_rv_itag1_hold(lq_rv_itag1_hold),
.lq_rv_itag1_cord(lq_rv_itag1_cord),
.lq_rv_itag1_rst_vld(lq_rv_itag1_rst_vld),
.lq_rv_itag1_rst(lq_rv_itag1_rst),
.lq_rv_clr_hold(lq_rv_clr_hold),
.rvs_perf_bus(fx1_rvs_perf_bus),
.rvs_dbg_bus(fx1_rvs_dbg_bus),
.q_ord_tid(q_ord_tid),
.rvs_empty(rvs_empty),
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.sg_1(sg_1),
.func_sl_thold_1(func_sl_thold_1),
.ccflush_dc(ccflush_dc),
.act_dis(act_dis),
.clkoff_b(clkoff_b),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scan_in(siv[rvs_offset]),
.scan_out(sov[rvs_offset])
);
assign rv_iu_fx1_credit_free = ex1_credit_free;
assign rv_fx1_vld = rv1_instr_v;
assign rv_fx1_s1_v = rv1_instr_dat[rvfx1_s1_v_start];
assign rv_fx1_s1_p = rv1_instr_dat[rvfx1_s1_p_start:rvfx1_s1_p_stop];
assign rv_fx1_s2_v = rv1_instr_dat[rvfx1_s2_v_start];
assign rv_fx1_s2_p = rv1_instr_dat[rvfx1_s2_p_start:rvfx1_s2_p_stop];
assign rv_fx1_s3_v = rv1_instr_dat[rvfx1_s3_v_start];
assign rv_fx1_s3_p = rv1_instr_dat[rvfx1_s3_p_start:rvfx1_s3_p_stop];
assign rv_byp_fx1_vld = rv1_instr_v;
assign rv_byp_fx1_itag = rv1_instr_itag;
assign rv_byp_fx1_s1_itag = rv1_instr_s1_itag;
assign rv_byp_fx1_s2_itag = rv1_instr_s2_itag;
assign rv_byp_fx1_s3_itag = rv1_instr_s3_itag;
assign rv_byp_fx1_t1_v = rv1_instr_dat[rvfx1_t1_v_start];
assign rv_byp_fx1_t2_v = rv1_instr_dat[rvfx1_t2_v_start];
assign rv_byp_fx1_t3_v = rv1_instr_dat[rvfx1_t3_v_start];
assign rv_byp_fx1_s1_t = rv1_instr_dat[rvfx1_s1_t_start:rvfx1_s1_t_stop];
assign rv_byp_fx1_s2_t = rv1_instr_dat[rvfx1_s2_t_start:rvfx1_s2_t_stop];
assign rv_byp_fx1_s3_t = rv1_instr_dat[rvfx1_s3_t_start:rvfx1_s3_t_stop];
assign rv_byp_fx1_ilat = rv1_instr_ilat;
assign rv_byp_fx1_ilat0_vld = rv1_instr_ilat0_vld;
assign rv_byp_fx1_ilat1_vld = rv1_instr_ilat1_vld;
assign rv_ex0_act = |(rv1_instr_v);
assign rv_fx1_ex0_instr = ex0_instr_dat[rvfx1_instr_start:rvfx1_instr_stop];
assign rv_fx1_ex0_ucode = ex0_instr_dat[rvfx1_ucode_start:rvfx1_ucode_stop];
assign rv_fx1_ex0_t1_p = ex0_instr_dat[rvfx1_t1_p_start:rvfx1_t1_p_stop];
assign rv_fx1_ex0_t2_p = ex0_instr_dat[rvfx1_t2_p_start:rvfx1_t2_p_stop];
assign rv_fx1_ex0_t3_p = ex0_instr_dat[rvfx1_t3_p_start:rvfx1_t3_p_stop];
assign rv_byp_fx1_ex0_isStore = ex0_instr_dat[rvfx1_isStore_start];
assign rv_fx1_ex0_isStore = ex0_instr_dat[rvfx1_isStore_start];
assign ex0_itag_d = rv1_instr_itag;
assign ex0_t1_v_d = rv1_instr_dat[rvfx1_t1_v_start];
assign ex0_t2_v_d = rv1_instr_dat[rvfx1_t2_v_start];
assign ex0_t3_v_d = rv1_instr_dat[rvfx1_t3_v_start];
assign ex0_s1_v_d = rv1_instr_dat[rvfx1_s1_v_start];
assign ex0_s3_t_d = rv1_instr_dat[rvfx1_s3_t_start:rvfx1_s3_t_stop];
assign rv_fx1_ex0_itag = ex0_itag_q;
assign rv_fx1_ex0_t1_v = ex0_t1_v_q;
assign rv_fx1_ex0_t2_v = ex0_t2_v_q;
assign rv_fx1_ex0_t3_v = ex0_t3_v_q;
assign rv_fx1_ex0_s1_v = ex0_s1_v_q;
assign rv_fx1_ex0_s3_t = ex0_s3_t_q;
//------------------------------------------------------------------------------------------------------------
// Itag busses
//------------------------------------------------------------------------------------------------------------
// Restart Itag and Valid from LQ. This is separate because it could be early (not latched)
assign lq_rv_itag1_rst_vld = lq_rv_itag1_vld;
assign lq_rv_itag1_rst = lq_rv_itag1;
//------------------------------------------------------------------------------------------------------------
// Pipeline Latches
//------------------------------------------------------------------------------------------------------------
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0))
ex0_itag_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rv_ex0_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]),
.scout(sov[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]),
.din(ex0_itag_d),
.dout(ex0_itag_q)
);
tri_rlmlatch_p #(.INIT(0))
ex0_t1_v_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rv_ex0_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex0_t1_v_offset]),
.scout(sov[ex0_t1_v_offset]),
.din(ex0_t1_v_d),
.dout(ex0_t1_v_q)
);
tri_rlmlatch_p #(.INIT(0))
ex0_t2_v_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rv_ex0_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex0_t2_v_offset]),
.scout(sov[ex0_t2_v_offset]),
.din(ex0_t2_v_d),
.dout(ex0_t2_v_q)
);
tri_rlmlatch_p #(.INIT(0)) ex0_t3_v_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rv_ex0_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex0_t3_v_offset]),
.scout(sov[ex0_t3_v_offset]),
.din(ex0_t3_v_d),
.dout(ex0_t3_v_q)
);
tri_rlmlatch_p #(.INIT(0)) ex0_s1_v_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rv_ex0_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex0_s1_v_offset]),
.scout(sov[ex0_s1_v_offset]),
.din(ex0_s1_v_d),
.dout(ex0_s1_v_q)
);
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex0_s3_t_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rv_ex0_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex0_s3_t_offset:ex0_s3_t_offset + 3 - 1]),
.scout(sov[ex0_s3_t_offset:ex0_s3_t_offset + 3 - 1]),
.din(ex0_s3_t_d),
.dout(ex0_s3_t_q)
);
//------------------------------------------------------------------------------------------------------------
// Scan Connections
//------------------------------------------------------------------------------------------------------------
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
//-----------------------------------------------
// pervasive
//-----------------------------------------------
tri_plat #(.WIDTH(2))
perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_dc),
.din({func_sl_thold_1, sg_1}),
.q({func_sl_thold_0, sg_0})
);
tri_lcbor
perv_lcbor(
.clkoff_b(clkoff_b),
.thold(func_sl_thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(func_sl_thold_0_b)
);
endmodule |
module iuq_ram(
pc_iu_ram_instr,
pc_iu_ram_instr_ext,
pc_iu_ram_issue,
pc_iu_ram_active,
iu_pc_ram_done,
cp_flush,
ib_rm_rdy,
rm_ib_iu3_val,
rm_ib_iu3_instr,
vdd,
gnd,
nclk,
pc_iu_sg_2,
pc_iu_func_sl_thold_2,
clkoff_b,
act_dis,
tc_ac_ccflush_dc,
d_mode,
delay_lclkr,
mpw1_b,
mpw2_b,
scan_in,
scan_out
);
`include "tri_a2o.vh"
// parameter `EXPAND_TYPE = 2;
// parameter `THREADS = 2; // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
input [0:31] pc_iu_ram_instr;
input [0:3] pc_iu_ram_instr_ext;
input pc_iu_ram_issue;
input [0:`THREADS-1] pc_iu_ram_active;
input iu_pc_ram_done;
input [0:`THREADS-1] cp_flush;
input [0:`THREADS-1] ib_rm_rdy;
output [0:`THREADS-1] rm_ib_iu3_val;
output [0:35] rm_ib_iu3_instr;
//pervasive
inout vdd;
inout gnd;
(* pin_data="PIN_FUNCTION=/G_CLK/" *)
input [0:`NCLK_WIDTH-1] nclk;
input pc_iu_sg_2;
input pc_iu_func_sl_thold_2;
input clkoff_b;
input act_dis;
input tc_ac_ccflush_dc;
input d_mode;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input scan_in;
output scan_out;
//--------------------------
// components
//--------------------------
//--------------------------
// constants
//--------------------------
//scan chain
parameter cp_flush_offset = 0;
parameter ram_val_offset = cp_flush_offset + `THREADS;
parameter ram_act_offset = ram_val_offset + `THREADS;
parameter ram_instr_offset = ram_act_offset + `THREADS;
parameter ram_done_offset = ram_instr_offset + 36;
parameter scan_right = ram_done_offset + 1 - 1;
//--------------------------
// signals
//--------------------------
wire tiup;
wire ram_valid;
wire [0:`THREADS-1] ram_val_d;
wire [0:`THREADS-1] ram_val_q;
wire [0:`THREADS-1] ram_act_d;
wire [0:`THREADS-1] ram_act_q;
wire [0:35] ram_instr_d;
wire [0:35] ram_instr_q;
wire ram_done_d;
wire ram_done_q;
wire [0:`THREADS-1] cp_flush_d;
wire [0:`THREADS-1] cp_flush_q;
wire pc_iu_func_sl_thold_1;
wire pc_iu_func_sl_thold_0;
wire pc_iu_func_sl_thold_0_b;
wire pc_iu_sg_1;
wire pc_iu_sg_0;
wire force_t;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
assign tiup = 1'b1;
//assign tidn = 1'b0;
//-----------------------------------------------
// logic
//-----------------------------------------------
assign cp_flush_d = cp_flush;
assign ram_done_d = iu_pc_ram_done;
generate
begin : xhdl1
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : issue_gating
assign ram_val_d[i] = (pc_iu_ram_active[i] & pc_iu_ram_issue) | (ram_val_q[i] & (~ib_rm_rdy[i])) | (cp_flush_q[i] & ram_act_d[i]);
assign ram_act_d[i] = (ram_done_q == 1'b1) ? 1'b0 :
(ram_val_q[i] == 1'b1) ? 1'b1 :
ram_act_q[i];
end
end
endgenerate
assign ram_valid = pc_iu_ram_issue;
assign ram_instr_d = {pc_iu_ram_instr, pc_iu_ram_instr_ext};
//-----------------------------------------------
// outputs
//-----------------------------------------------
assign rm_ib_iu3_val = ram_val_q;
assign rm_ib_iu3_instr = ram_instr_q;
//-----------------------------------------------
// latches
//-----------------------------------------------
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]),
.scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]),
.din(cp_flush_d),
.dout(cp_flush_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ram_val_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ram_val_offset:ram_val_offset + `THREADS - 1]),
.scout(sov[ram_val_offset:ram_val_offset + `THREADS - 1]),
.din(ram_val_d),
.dout(ram_val_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ram_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ram_act_offset:ram_act_offset + `THREADS - 1]),
.scout(sov[ram_act_offset:ram_act_offset + `THREADS - 1]),
.din(ram_act_d),
.dout(ram_act_q)
);
tri_rlmreg_p #(.WIDTH(36), .INIT(0)) ram_instr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(ram_valid),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ram_instr_offset:ram_instr_offset + 35]),
.scout(sov[ram_instr_offset:ram_instr_offset + 35]),
.din(ram_instr_d[0:35]),
.dout(ram_instr_q[0:35])
);
tri_rlmlatch_p #(.INIT(0)) ram_done_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ram_done_offset]),
.scout(sov[ram_done_offset]),
.din(ram_done_d),
.dout(ram_done_q)
);
//-----------------------------------------------
// pervasive
//-----------------------------------------------
tri_plat #(.WIDTH(2)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2,pc_iu_sg_2}),
.q({pc_iu_func_sl_thold_1,pc_iu_sg_1})
);
tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1,pc_iu_sg_1}),
.q({pc_iu_func_sl_thold_0,pc_iu_sg_0})
);
tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b),
.thold(pc_iu_func_sl_thold_0),
.sg(pc_iu_sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b)
);
//-----------------------------------------------
// scan
//-----------------------------------------------
assign siv[0:scan_right] = {scan_in, sov[0:scan_right - 1]};
assign scan_out = sov[scan_right];
endmodule |
module pcq_clks(
// Include model build parameters
`include "tri_a2o.vh"
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input rtim_sl_thold_7,
input func_sl_thold_7,
input func_nsl_thold_7,
input ary_nsl_thold_7,
input sg_7,
input fce_7,
input gsd_test_enable_dc,
input gsd_test_acmode_dc,
input ccflush_dc,
input ccenable_dc,
input lbist_en_dc,
input lbist_ip_dc,
input rg_ck_fast_xstop,
input ct_ck_pm_ccflush_disable,
input ct_ck_pm_raise_tholds,
input [0:8] scan_type_dc,
// --Thold + control outputs to the units
output pc_pc_ccflush_out_dc,
output pc_pc_gptr_sl_thold_4,
output pc_pc_time_sl_thold_4,
output pc_pc_repr_sl_thold_4,
output pc_pc_abst_sl_thold_4,
output pc_pc_abst_slp_sl_thold_4,
output pc_pc_regf_sl_thold_4,
output pc_pc_regf_slp_sl_thold_4,
output pc_pc_func_sl_thold_4,
output pc_pc_func_slp_sl_thold_4,
output pc_pc_cfg_sl_thold_4,
output pc_pc_cfg_slp_sl_thold_4,
output pc_pc_func_nsl_thold_4,
output pc_pc_func_slp_nsl_thold_4,
output pc_pc_ary_nsl_thold_4,
output pc_pc_ary_slp_nsl_thold_4,
output pc_pc_rtim_sl_thold_4,
output pc_pc_sg_4,
output pc_pc_fce_4,
// Thold + control signals used by fu
output pc_fu_ccflush_dc,
output pc_fu_gptr_sl_thold_3,
output pc_fu_time_sl_thold_3,
output pc_fu_repr_sl_thold_3,
output pc_fu_abst_sl_thold_3,
output pc_fu_abst_slp_sl_thold_3,
output [0:1] pc_fu_func_sl_thold_3,
output [0:1] pc_fu_func_slp_sl_thold_3,
output pc_fu_cfg_sl_thold_3,
output pc_fu_cfg_slp_sl_thold_3,
output pc_fu_func_nsl_thold_3,
output pc_fu_func_slp_nsl_thold_3,
output pc_fu_ary_nsl_thold_3,
output pc_fu_ary_slp_nsl_thold_3,
output [0:1] pc_fu_sg_3,
output pc_fu_fce_3,
// Thold + control signals used in pcq
output pc_pc_ccflush_dc,
output pc_pc_gptr_sl_thold_0,
output pc_pc_func_sl_thold_0,
output pc_pc_func_slp_sl_thold_0,
output pc_pc_cfg_sl_thold_0,
output pc_pc_cfg_slp_sl_thold_0,
output pc_pc_sg_0
);
//=====================================================================
// Signal Declarations
//=====================================================================
wire rtim_sl_thold_6;
wire func_sl_thold_6;
wire func_nsl_thold_6;
wire ary_nsl_thold_6;
wire sg_6;
wire fce_6;
wire ccflush_out_dc;
wire gptr_sl_thold_5;
wire time_sl_thold_5;
wire repr_sl_thold_5;
wire abst_sl_thold_5;
wire abst_slp_sl_thold_5;
wire regf_sl_thold_5;
wire regf_slp_sl_thold_5;
wire func_sl_thold_5;
wire func_slp_sl_thold_5;
wire cfg_sl_thold_5;
wire cfg_slp_sl_thold_5;
wire func_nsl_thold_5;
wire func_slp_nsl_thold_5;
wire ary_nsl_thold_5;
wire ary_slp_nsl_thold_5;
wire rtim_sl_thold_5;
wire sg_5;
wire fce_5;
//=====================================================================
// Clock Control and Staging Logic
//=====================================================================
pcq_clks_ctrl clkctrl(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.rtim_sl_thold_6(rtim_sl_thold_6),
.func_sl_thold_6(func_sl_thold_6),
.func_nsl_thold_6(func_nsl_thold_6),
.ary_nsl_thold_6(ary_nsl_thold_6),
.sg_6(sg_6),
.fce_6(fce_6),
.gsd_test_enable_dc(gsd_test_enable_dc),
.gsd_test_acmode_dc(gsd_test_acmode_dc),
.ccflush_dc(ccflush_dc),
.ccenable_dc(ccenable_dc),
.scan_type_dc(scan_type_dc),
.lbist_en_dc(lbist_en_dc),
.lbist_ip_dc(lbist_ip_dc),
.rg_ck_fast_xstop(rg_ck_fast_xstop),
.ct_ck_pm_ccflush_disable(ct_ck_pm_ccflush_disable),
.ct_ck_pm_raise_tholds(ct_ck_pm_raise_tholds),
// --Thold + control outputs to the units
.ccflush_out_dc(ccflush_out_dc),
.gptr_sl_thold_5(gptr_sl_thold_5),
.time_sl_thold_5(time_sl_thold_5),
.repr_sl_thold_5(repr_sl_thold_5),
.cfg_sl_thold_5(cfg_sl_thold_5),
.cfg_slp_sl_thold_5(cfg_slp_sl_thold_5),
.abst_sl_thold_5(abst_sl_thold_5),
.abst_slp_sl_thold_5(abst_slp_sl_thold_5),
.regf_sl_thold_5(regf_sl_thold_5),
.regf_slp_sl_thold_5(regf_slp_sl_thold_5),
.func_sl_thold_5(func_sl_thold_5),
.func_slp_sl_thold_5(func_slp_sl_thold_5),
.func_nsl_thold_5(func_nsl_thold_5),
.func_slp_nsl_thold_5(func_slp_nsl_thold_5),
.ary_nsl_thold_5(ary_nsl_thold_5),
.ary_slp_nsl_thold_5(ary_slp_nsl_thold_5),
.rtim_sl_thold_5(rtim_sl_thold_5),
.sg_5(sg_5),
.fce_5(fce_5)
);
pcq_clks_stg clkstg(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.ccflush_out_dc(ccflush_out_dc),
.gptr_sl_thold_5(gptr_sl_thold_5),
.time_sl_thold_5(time_sl_thold_5),
.repr_sl_thold_5(repr_sl_thold_5),
.cfg_sl_thold_5(cfg_sl_thold_5),
.cfg_slp_sl_thold_5(cfg_slp_sl_thold_5),
.abst_sl_thold_5(abst_sl_thold_5),
.abst_slp_sl_thold_5(abst_slp_sl_thold_5),
.regf_sl_thold_5(regf_sl_thold_5),
.regf_slp_sl_thold_5(regf_slp_sl_thold_5),
.func_sl_thold_5(func_sl_thold_5),
.func_slp_sl_thold_5(func_slp_sl_thold_5),
.func_nsl_thold_5(func_nsl_thold_5),
.func_slp_nsl_thold_5(func_slp_nsl_thold_5),
.ary_nsl_thold_5(ary_nsl_thold_5),
.ary_slp_nsl_thold_5(ary_slp_nsl_thold_5),
.rtim_sl_thold_5(rtim_sl_thold_5),
.sg_5(sg_5),
.fce_5(fce_5),
// Thold + control outputs to the units
.pc_pc_ccflush_out_dc(pc_pc_ccflush_out_dc),
.pc_pc_gptr_sl_thold_4(pc_pc_gptr_sl_thold_4),
.pc_pc_time_sl_thold_4(pc_pc_time_sl_thold_4),
.pc_pc_repr_sl_thold_4(pc_pc_repr_sl_thold_4),
.pc_pc_abst_sl_thold_4(pc_pc_abst_sl_thold_4),
.pc_pc_abst_slp_sl_thold_4(pc_pc_abst_slp_sl_thold_4),
.pc_pc_regf_sl_thold_4(pc_pc_regf_sl_thold_4),
.pc_pc_regf_slp_sl_thold_4(pc_pc_regf_slp_sl_thold_4),
.pc_pc_func_sl_thold_4(pc_pc_func_sl_thold_4),
.pc_pc_func_slp_sl_thold_4(pc_pc_func_slp_sl_thold_4),
.pc_pc_cfg_sl_thold_4(pc_pc_cfg_sl_thold_4),
.pc_pc_cfg_slp_sl_thold_4(pc_pc_cfg_slp_sl_thold_4),
.pc_pc_func_nsl_thold_4(pc_pc_func_nsl_thold_4),
.pc_pc_func_slp_nsl_thold_4(pc_pc_func_slp_nsl_thold_4),
.pc_pc_ary_nsl_thold_4(pc_pc_ary_nsl_thold_4),
.pc_pc_ary_slp_nsl_thold_4(pc_pc_ary_slp_nsl_thold_4),
.pc_pc_rtim_sl_thold_4(pc_pc_rtim_sl_thold_4),
.pc_pc_sg_4(pc_pc_sg_4),
.pc_pc_fce_4(pc_pc_fce_4),
// Thold + control signals used by fu
.pc_fu_ccflush_dc(pc_fu_ccflush_dc),
.pc_fu_gptr_sl_thold_3(pc_fu_gptr_sl_thold_3),
.pc_fu_time_sl_thold_3(pc_fu_time_sl_thold_3),
.pc_fu_repr_sl_thold_3(pc_fu_repr_sl_thold_3),
.pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3),
.pc_fu_abst_slp_sl_thold_3(pc_fu_abst_slp_sl_thold_3),
.pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3),
.pc_fu_func_slp_sl_thold_3(pc_fu_func_slp_sl_thold_3),
.pc_fu_cfg_sl_thold_3(pc_fu_cfg_sl_thold_3),
.pc_fu_cfg_slp_sl_thold_3(pc_fu_cfg_slp_sl_thold_3),
.pc_fu_func_nsl_thold_3(pc_fu_func_nsl_thold_3),
.pc_fu_func_slp_nsl_thold_3(pc_fu_func_slp_nsl_thold_3),
.pc_fu_ary_nsl_thold_3(pc_fu_ary_nsl_thold_3),
.pc_fu_ary_slp_nsl_thold_3(pc_fu_ary_slp_nsl_thold_3),
.pc_fu_sg_3(pc_fu_sg_3),
.pc_fu_fce_3(pc_fu_fce_3),
// PC Unit thold + control signals
.pc_pc_ccflush_dc(pc_pc_ccflush_dc),
.pc_pc_gptr_sl_thold_0(pc_pc_gptr_sl_thold_0),
.pc_pc_func_sl_thold_0(pc_pc_func_sl_thold_0),
.pc_pc_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0),
.pc_pc_cfg_sl_thold_0(pc_pc_cfg_sl_thold_0),
.pc_pc_cfg_slp_sl_thold_0(pc_pc_cfg_slp_sl_thold_0),
.pc_pc_sg_0(pc_pc_sg_0)
);
tri_plat #(.WIDTH(6)) lvl7to6_plat(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_dc),
.din({rtim_sl_thold_7, func_sl_thold_7, func_nsl_thold_7,
ary_nsl_thold_7, sg_7, fce_7}),
.q( {rtim_sl_thold_6, func_sl_thold_6, func_nsl_thold_6,
ary_nsl_thold_6, sg_6, fce_6})
);
endmodule |
module fu_hc16pp_lsb(
x,
y,
s0,
s1,
g16,
t16
);
input [0:13] x;
input [0:12] y;
output [0:13] s0;
output [0:13] s1;
output g16;
output t16;
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:12] g01_b;
wire [0:13] t01_b;
wire [0:13] p01_b;
wire [0:13] p01;
wire [0:5] g01od;
wire [0:6] t01od;
wire [0:6] g02ev;
wire [0:6] t02ev;
wire [1:6] g02ev_b;
wire [1:6] t02ev_b;
wire [1:6] g04ev;
wire [1:6] t04ev;
wire [1:6] g08ev_b;
wire [1:6] t08ev_b;
wire [1:6] g16ev;
wire [1:6] t16ev;
wire [1:12] c0_b;
wire [1:13] c1_b;
wire glb_g04_e01_b; //new // rep glb
wire glb_g04_e23_b;
wire glb_g04_e45_b;
wire glb_g04_e67_b;
wire glb_t04_e01_b; //new // rep glb
wire glb_t04_e23_b;
wire glb_t04_e45_b;
wire glb_t04_e67_b;
wire glb_g08_e03; //new // rep glb
wire glb_g08_e47;
wire glb_t08_e03;
wire glb_t08_e47;
wire glb_g16_e07_b; //new // rep glb
wire glb_t16_e07_b;
////#####################################
////## group 1
////#####################################
assign g01_b[0] = (~(x[0] & y[0])); //critical
assign g01_b[1] = (~(x[1] & y[1])); //critical
assign g01_b[2] = (~(x[2] & y[2])); //critical
assign g01_b[3] = (~(x[3] & y[3])); //critical
assign g01_b[4] = (~(x[4] & y[4])); //critical
assign g01_b[5] = (~(x[5] & y[5])); //critical
assign g01_b[6] = (~(x[6] & y[6])); //critical
assign g01_b[7] = (~(x[7] & y[7])); //critical
assign g01_b[8] = (~(x[8] & y[8])); //critical
assign g01_b[9] = (~(x[9] & y[9])); //critical
assign g01_b[10] = (~(x[10] & y[10])); //critical
assign g01_b[11] = (~(x[11] & y[11])); //critical
assign g01_b[12] = (~(x[12] & y[12])); //critical
assign t01_b[0] = (~(x[0] | y[0])); //critical
assign t01_b[1] = (~(x[1] | y[1])); //critical
assign t01_b[2] = (~(x[2] | y[2])); //critical
assign t01_b[3] = (~(x[3] | y[3])); //critical
assign t01_b[4] = (~(x[4] | y[4])); //critical
assign t01_b[5] = (~(x[5] | y[5])); //critical
assign t01_b[6] = (~(x[6] | y[6])); //critical
assign t01_b[7] = (~(x[7] | y[7])); //critical
assign t01_b[8] = (~(x[8] | y[8])); //critical
assign t01_b[9] = (~(x[9] | y[9])); //critical
assign t01_b[10] = (~(x[10] | y[10])); //critical
assign t01_b[11] = (~(x[11] | y[11])); //critical
assign t01_b[12] = (~(x[12] | y[12])); //critical
assign t01_b[13] = (~(x[13])); //critical
assign p01[0] = (x[0] ^ y[0]); //not critical
assign p01[1] = (x[1] ^ y[1]); //not critical
assign p01[2] = (x[2] ^ y[2]); //not critical
assign p01[3] = (x[3] ^ y[3]); //not critical
assign p01[4] = (x[4] ^ y[4]); //not critical
assign p01[5] = (x[5] ^ y[5]); //not critical
assign p01[6] = (x[6] ^ y[6]); //not critical
assign p01[7] = (x[7] ^ y[7]); //not critical
assign p01[8] = (x[8] ^ y[8]); //not critical
assign p01[9] = (x[9] ^ y[9]); //not critical
assign p01[10] = (x[10] ^ y[10]); //not critical
assign p01[11] = (x[11] ^ y[11]); //not critical
assign p01[12] = (x[12] ^ y[12]); //not critical
assign p01[13] = (~p01_b[13]);
assign p01_b[0] = (~(p01[0])); //not critical
assign p01_b[1] = (~(p01[1])); //not critical
assign p01_b[2] = (~(p01[2])); //not critical
assign p01_b[3] = (~(p01[3])); //not critical
assign p01_b[4] = (~(p01[4])); //not critical
assign p01_b[5] = (~(p01[5])); //not critical
assign p01_b[6] = (~(p01[6])); //not critical
assign p01_b[7] = (~(p01[7])); //not critical
assign p01_b[8] = (~(p01[8])); //not critical
assign p01_b[9] = (~(p01[9])); //not critical
assign p01_b[10] = (~(p01[10])); //not critical
assign p01_b[11] = (~(p01[11])); //not critical
assign p01_b[12] = (~(p01[12])); //not critical
assign p01_b[13] = (~(x[13])); //not critical
assign g01od[0] = (~g01_b[1]);
assign g01od[1] = (~g01_b[3]);
assign g01od[2] = (~g01_b[5]);
assign g01od[3] = (~g01_b[7]);
assign g01od[4] = (~g01_b[9]);
assign g01od[5] = (~g01_b[11]);
assign t01od[0] = (~t01_b[1]);
assign t01od[1] = (~t01_b[3]);
assign t01od[2] = (~t01_b[5]);
assign t01od[3] = (~t01_b[7]);
assign t01od[4] = (~t01_b[9]);
assign t01od[5] = (~t01_b[11]);
assign t01od[6] = (~t01_b[13]);
////#####################################
////## group 2 // local and global shared
////#####################################
assign g02ev[6] = (~(g01_b[12])); //final
assign g02ev[5] = (~((t01_b[10] | g01_b[11]) & g01_b[10]));
assign g02ev[4] = (~((t01_b[8] | g01_b[9]) & g01_b[8]));
assign g02ev[3] = (~((t01_b[6] | g01_b[7]) & g01_b[6]));
assign g02ev[2] = (~((t01_b[4] | g01_b[5]) & g01_b[4]));
assign g02ev[1] = (~((t01_b[2] | g01_b[3]) & g01_b[2]));
assign g02ev[0] = (~((t01_b[0] | g01_b[1]) & g01_b[0]));
assign t02ev[6] = (~((t01_b[12] | t01_b[13]) & g01_b[12])); //final
assign t02ev[5] = (~((t01_b[10] | t01_b[11])));
assign t02ev[4] = (~((t01_b[8] | t01_b[9])));
assign t02ev[3] = (~((t01_b[6] | t01_b[7])));
assign t02ev[2] = (~((t01_b[4] | t01_b[5])));
assign t02ev[1] = (~((t01_b[2] | t01_b[3])));
assign t02ev[0] = (~((t01_b[0] | t01_b[1])));
assign g02ev_b[6] = (~(g02ev[6])); //new
assign g02ev_b[5] = (~(g02ev[5])); //new
assign g02ev_b[4] = (~(g02ev[4])); //new
assign g02ev_b[3] = (~(g02ev[3])); //new
assign g02ev_b[2] = (~(g02ev[2])); //new
assign g02ev_b[1] = (~(g02ev[1])); //new
assign t02ev_b[6] = (~(t02ev[6])); //new
assign t02ev_b[5] = (~(t02ev[5])); //new
assign t02ev_b[4] = (~(t02ev[4])); //new
assign t02ev_b[3] = (~(t02ev[3])); //new
assign t02ev_b[2] = (~(t02ev[2])); //new
assign t02ev_b[1] = (~(t02ev[1])); //new
////#####################################
////## replicating for global chain
////#####################################
assign glb_g04_e01_b = (~(g02ev[0] | (t02ev[0] & g02ev[1])));
assign glb_g04_e23_b = (~(g02ev[2] | (t02ev[2] & g02ev[3])));
assign glb_g04_e45_b = (~(g02ev[4] | (t02ev[4] & g02ev[5])));
assign glb_g04_e67_b = (~(g02ev[6]));
assign glb_t04_e01_b = (~(t02ev[0] & t02ev[1]));
assign glb_t04_e23_b = (~(t02ev[2] & t02ev[3]));
assign glb_t04_e45_b = (~(t02ev[4] & t02ev[5]));
assign glb_t04_e67_b = (~(t02ev[6]));
assign glb_g08_e03 = (~(glb_g04_e01_b & (glb_t04_e01_b | glb_g04_e23_b)));
assign glb_g08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_g04_e67_b)));
assign glb_t08_e03 = (~(glb_t04_e01_b | glb_t04_e23_b));
assign glb_t08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_t04_e67_b)));
assign glb_g16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_g08_e47)));
assign glb_t16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_t08_e47)));
assign g16 = (~(glb_g16_e07_b)); //output
assign t16 = (~(glb_t16_e07_b)); //output
////#####################################
////## group 4
////#####################################
assign g04ev[6] = (~(g02ev_b[6]));
assign g04ev[5] = (~((t02ev_b[5] | g02ev_b[6]) & g02ev_b[5])); //final
assign g04ev[4] = (~((t02ev_b[4] | g02ev_b[5]) & g02ev_b[4]));
assign g04ev[3] = (~((t02ev_b[3] | g02ev_b[4]) & g02ev_b[3]));
assign g04ev[2] = (~((t02ev_b[2] | g02ev_b[3]) & g02ev_b[2]));
assign g04ev[1] = (~((t02ev_b[1] | g02ev_b[2]) & g02ev_b[1]));
assign t04ev[6] = (~(t02ev_b[6]));
assign t04ev[5] = (~((t02ev_b[5] | t02ev_b[6]) & g02ev_b[5])); //final
assign t04ev[4] = (~(t02ev_b[4] | t02ev_b[5]));
assign t04ev[3] = (~(t02ev_b[3] | t02ev_b[4]));
assign t04ev[2] = (~(t02ev_b[2] | t02ev_b[3]));
assign t04ev[1] = (~(t02ev_b[1] | t02ev_b[2]));
////#####################################
////## group 8
////#####################################
assign g08ev_b[6] = (~(g04ev[6]));
assign g08ev_b[5] = (~(g04ev[5]));
assign g08ev_b[4] = (~(g04ev[4] | (t04ev[4] & g04ev[6]))); //final
assign g08ev_b[3] = (~(g04ev[3] | (t04ev[3] & g04ev[5]))); //final
assign g08ev_b[2] = (~(g04ev[2] | (t04ev[2] & g04ev[4])));
assign g08ev_b[1] = (~(g04ev[1] | (t04ev[1] & g04ev[3])));
assign t08ev_b[6] = (~(t04ev[6]));
assign t08ev_b[5] = (~(t04ev[5]));
assign t08ev_b[4] = (~(g04ev[4] | (t04ev[4] & t04ev[6]))); //final
assign t08ev_b[3] = (~(g04ev[3] | (t04ev[3] & t04ev[5]))); //final
assign t08ev_b[2] = (~(t04ev[2] & t04ev[4]));
assign t08ev_b[1] = (~(t04ev[1] & t04ev[3]));
////#####################################
////## group 16
////#####################################
assign g16ev[6] = (~(g08ev_b[6]));
assign g16ev[5] = (~(g08ev_b[5]));
assign g16ev[4] = (~(g08ev_b[4]));
assign g16ev[3] = (~(g08ev_b[3]));
assign g16ev[2] = (~((t08ev_b[2] | g08ev_b[6]) & g08ev_b[2])); //final
assign g16ev[1] = (~((t08ev_b[1] | g08ev_b[5]) & g08ev_b[1])); //final
assign t16ev[6] = (~(t08ev_b[6]));
assign t16ev[5] = (~(t08ev_b[5]));
assign t16ev[4] = (~(t08ev_b[4]));
assign t16ev[3] = (~(t08ev_b[3]));
assign t16ev[2] = (~((t08ev_b[2] | t08ev_b[6]) & g08ev_b[2])); //final
assign t16ev[1] = (~((t08ev_b[1] | t08ev_b[5]) & g08ev_b[1])); //final
////#####################################
////## group 16 delayed
////#####################################
assign c0_b[12] = (~(g16ev[6]));
assign c0_b[10] = (~(g16ev[5]));
assign c0_b[8] = (~(g16ev[4]));
assign c0_b[6] = (~(g16ev[3]));
assign c0_b[4] = (~(g16ev[2]));
assign c0_b[2] = (~(g16ev[1]));
assign c1_b[12] = (~(t16ev[6]));
assign c1_b[10] = (~(t16ev[5]));
assign c1_b[8] = (~(t16ev[4]));
assign c1_b[6] = (~(t16ev[3]));
assign c1_b[4] = (~(t16ev[2]));
assign c1_b[2] = (~(t16ev[1]));
assign c0_b[11] = (~((t01od[5] & g16ev[6]) | g01od[5]));
assign c0_b[9] = (~((t01od[4] & g16ev[5]) | g01od[4]));
assign c0_b[7] = (~((t01od[3] & g16ev[4]) | g01od[3]));
assign c0_b[5] = (~((t01od[2] & g16ev[3]) | g01od[2]));
assign c0_b[3] = (~((t01od[1] & g16ev[2]) | g01od[1]));
assign c0_b[1] = (~((t01od[0] & g16ev[1]) | g01od[0]));
assign c1_b[13] = (~(t01od[6]));
assign c1_b[11] = (~((t01od[5] & t16ev[6]) | g01od[5]));
assign c1_b[9] = (~((t01od[4] & t16ev[5]) | g01od[4]));
assign c1_b[7] = (~((t01od[3] & t16ev[4]) | g01od[3]));
assign c1_b[5] = (~((t01od[2] & t16ev[3]) | g01od[2]));
assign c1_b[3] = (~((t01od[1] & t16ev[2]) | g01od[1]));
assign c1_b[1] = (~((t01od[0] & t16ev[1]) | g01od[0]));
////#####################################
////## sum
////#####################################
assign s0[0] = (p01_b[0] ^ c0_b[1]);
assign s0[1] = (p01_b[1] ^ c0_b[2]);
assign s0[2] = (p01_b[2] ^ c0_b[3]);
assign s0[3] = (p01_b[3] ^ c0_b[4]);
assign s0[4] = (p01_b[4] ^ c0_b[5]);
assign s0[5] = (p01_b[5] ^ c0_b[6]);
assign s0[6] = (p01_b[6] ^ c0_b[7]);
assign s0[7] = (p01_b[7] ^ c0_b[8]);
assign s0[8] = (p01_b[8] ^ c0_b[9]);
assign s0[9] = (p01_b[9] ^ c0_b[10]);
assign s0[10] = (p01_b[10] ^ c0_b[11]);
assign s0[11] = (p01_b[11] ^ c0_b[12]);
assign s0[12] = (~(p01_b[12]));
assign s0[13] = (~(p01_b[13]));
assign s1[0] = (p01_b[0] ^ c1_b[1]);
assign s1[1] = (p01_b[1] ^ c1_b[2]);
assign s1[2] = (p01_b[2] ^ c1_b[3]);
assign s1[3] = (p01_b[3] ^ c1_b[4]);
assign s1[4] = (p01_b[4] ^ c1_b[5]);
assign s1[5] = (p01_b[5] ^ c1_b[6]);
assign s1[6] = (p01_b[6] ^ c1_b[7]);
assign s1[7] = (p01_b[7] ^ c1_b[8]);
assign s1[8] = (p01_b[8] ^ c1_b[9]);
assign s1[9] = (p01_b[9] ^ c1_b[10]);
assign s1[10] = (p01_b[10] ^ c1_b[11]);
assign s1[11] = (p01_b[11] ^ c1_b[12]);
assign s1[12] = (p01_b[12] ^ c1_b[13]);
assign s1[13] = (~(p01[13]));
endmodule |
module rv_dep_scard(
iu_xx_zap,
rv0_sc_act,
ta_v,
ta_itag,
tb_v,
tb_itag,
xx_rv_itag_v,
xx_rv_itag_abort,
xx_rv_itag_ary0,
xx_rv_itag_ary1,
xx_rv_itag_ary2,
xx_rv_itag_ary3,
xx_rv_itag_ary4,
xx_rv_itag_ary5,
xx_rv_itag_ary6,
i0_s1_itag,
i0_s1_itag_v,
i0_s2_itag,
i0_s2_itag_v,
i0_s3_itag,
i0_s3_itag_v,
i1_s1_itag,
i1_s1_itag_v,
i1_s2_itag,
i1_s2_itag_v,
i1_s3_itag,
i1_s3_itag_v,
vdd,
gnd,
nclk,
chip_b_sl_sg_0_t,
chip_b_sl_2_thold_0_b,
force_t,
d_mode,
delay_lclkr,
mpw1_b,
mpw2_b,
scan_in,
scan_out
);
`include "tri_a2o.vh"
parameter num_entries_g = 32;
parameter itag_width_enc_g = 6;
//------------------------------------------------------------------------------------------------------------
// IU Control
//------------------------------------------------------------------------------------------------------------
input iu_xx_zap;
input rv0_sc_act;
//------------------------------------------------------------------------------------------------------------
// Target interface
//------------------------------------------------------------------------------------------------------------
input ta_v;
input [0:itag_width_enc_g-1] ta_itag;
input tb_v;
input [0:itag_width_enc_g-1] tb_itag;
//------------------------------------------------------------------------------------------------------------
// Itag Compare and Reset Valid Interface
//------------------------------------------------------------------------------------------------------------
input [0:6] xx_rv_itag_v;
input [0:6] xx_rv_itag_abort;
input [0:itag_width_enc_g-1] xx_rv_itag_ary0;
input [0:itag_width_enc_g-1] xx_rv_itag_ary1;
input [0:itag_width_enc_g-1] xx_rv_itag_ary2;
input [0:itag_width_enc_g-1] xx_rv_itag_ary3;
input [0:itag_width_enc_g-1] xx_rv_itag_ary4;
input [0:itag_width_enc_g-1] xx_rv_itag_ary5;
input [0:itag_width_enc_g-1] xx_rv_itag_ary6;
//------------------------------------------------------------------------------------------------------------
// Itag Mux(s)
//------------------------------------------------------------------------------------------------------------
input [0:itag_width_enc_g-1] i0_s1_itag;
output i0_s1_itag_v;
input [0:itag_width_enc_g-1] i0_s2_itag;
output i0_s2_itag_v;
input [0:itag_width_enc_g-1] i0_s3_itag;
output i0_s3_itag_v;
input [0:itag_width_enc_g-1] i1_s1_itag;
output i1_s1_itag_v;
input [0:itag_width_enc_g-1] i1_s2_itag;
output i1_s2_itag_v;
input [0:itag_width_enc_g-1] i1_s3_itag;
output i1_s3_itag_v;
//------------------------------------------------------------------------------------------------------------
// Pervasive
//------------------------------------------------------------------------------------------------------------
inout vdd;
inout gnd;
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk
input [0:`NCLK_WIDTH-1] nclk;
input chip_b_sl_sg_0_t;
input chip_b_sl_2_thold_0_b;
input force_t;
input d_mode;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input scan_in;
output scan_out;
//!! Bugspray Include: rv_dep_scard ;
//------------------------------------------------------------------------------------------------------------
// typedefs and constants
//------------------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------------------
// Select and mux signals
//------------------------------------------------------------------------------------------------------------
wire [0:num_entries_g-1] i0_s1_itag_v_gated;
wire [0:num_entries_g-1] i0_s2_itag_v_gated;
wire [0:num_entries_g-1] i0_s3_itag_v_gated;
wire [0:num_entries_g-1] i1_s1_itag_v_gated;
wire [0:num_entries_g-1] i1_s2_itag_v_gated;
wire [0:num_entries_g-1] i1_s3_itag_v_gated;
//------------------------------------------------------------------------------------------------------------
// Storage
//------------------------------------------------------------------------------------------------------------
wire [0:num_entries_g-1] scorecard_d;
wire [0:num_entries_g-1] scorecard_q;
wire [0:num_entries_g-1] score_ta_match;
wire [0:num_entries_g-1] score_tb_match;
wire [0:num_entries_g-1] itag_ary0_match;
wire [0:num_entries_g-1] itag_ary1_match;
wire [0:num_entries_g-1] itag_ary2_match;
wire [0:num_entries_g-1] itag_ary3_match;
wire [0:num_entries_g-1] itag_ary4_match;
wire [0:num_entries_g-1] itag_ary5_match;
wire [0:num_entries_g-1] itag_ary6_match;
wire [0:num_entries_g-1] score_set;
wire [0:num_entries_g-1] score_reset;
//------------------------------------------------------------------------------------------------------------
// Scan
//------------------------------------------------------------------------------------------------------------
`define scorecard_offset 0
`define scan_right `scorecard_offset + num_entries_g
wire [0:`scan_right-1] siv;
wire [0:`scan_right-1] sov;
//------------------------------------------------------------------------------------------------------------
// Set the target if t_v is valid and clear the valid if any of the target busses match
//------------------------------------------------------------------------------------------------------------
generate
begin : xhdl1
genvar i;
for (i = 0; i <= num_entries_g - 1; i = i + 1)
begin : g0
wire [0:itag_width_enc_g-1] id = i;
assign score_ta_match[i] = (ta_v & (id == ta_itag));
assign score_tb_match[i] = (tb_v & (id == tb_itag));
assign itag_ary0_match[i] = (id == xx_rv_itag_ary0);
assign itag_ary1_match[i] = (id == xx_rv_itag_ary1);
assign itag_ary2_match[i] = (id == xx_rv_itag_ary2);
assign itag_ary3_match[i] = (id == xx_rv_itag_ary3);
assign itag_ary4_match[i] = (id == xx_rv_itag_ary4);
assign itag_ary5_match[i] = (id == xx_rv_itag_ary5);
assign itag_ary6_match[i] = (id == xx_rv_itag_ary6);
assign score_reset[i] = (xx_rv_itag_v[0] & ~xx_rv_itag_abort[0] & itag_ary0_match[i]) |
(xx_rv_itag_v[1] & ~xx_rv_itag_abort[1] & itag_ary1_match[i]) |
(xx_rv_itag_v[2] & ~xx_rv_itag_abort[2] & itag_ary2_match[i]) |
(xx_rv_itag_v[3] & ~xx_rv_itag_abort[3] & itag_ary3_match[i]) |
(xx_rv_itag_v[4] & ~xx_rv_itag_abort[4] & itag_ary4_match[i]) |
(xx_rv_itag_v[5] & ~xx_rv_itag_abort[5] & itag_ary5_match[i]) |
(xx_rv_itag_v[6] & ~xx_rv_itag_abort[6] & itag_ary6_match[i]) ;
assign score_set[i] = (xx_rv_itag_v[0] & xx_rv_itag_abort[0] & itag_ary0_match[i]) |
(xx_rv_itag_v[1] & xx_rv_itag_abort[1] & itag_ary1_match[i]) |
(xx_rv_itag_v[2] & xx_rv_itag_abort[2] & itag_ary2_match[i]) |
(xx_rv_itag_v[3] & xx_rv_itag_abort[3] & itag_ary3_match[i]) |
(xx_rv_itag_v[4] & xx_rv_itag_abort[4] & itag_ary4_match[i]) |
(xx_rv_itag_v[5] & xx_rv_itag_abort[5] & itag_ary5_match[i]) |
(xx_rv_itag_v[6] & xx_rv_itag_abort[6] & itag_ary6_match[i]) ;
assign scorecard_d[i] = (score_ta_match[i] | score_tb_match[i] | score_set[i] | scorecard_q[i]) & (~score_reset[i]) & (~iu_xx_zap);
end
end
endgenerate
//------------------------------------------------------------------------------------------------------------
// Mux out the itag
//------------------------------------------------------------------------------------------------------------
generate
begin : xhdl2
genvar i;
for (i = 0; i <= num_entries_g - 1; i = i + 1)
begin : g1
wire [0:itag_width_enc_g-1] id = i;
assign i0_s1_itag_v_gated[i] = (scorecard_q[i]) & (i0_s1_itag == id);
assign i0_s2_itag_v_gated[i] = (scorecard_q[i]) & (i0_s2_itag == id);
assign i0_s3_itag_v_gated[i] = (scorecard_q[i]) & (i0_s3_itag == id);
assign i1_s1_itag_v_gated[i] = (scorecard_q[i]) & (i1_s1_itag == id);
assign i1_s2_itag_v_gated[i] = (scorecard_q[i]) & (i1_s2_itag == id);
assign i1_s3_itag_v_gated[i] = (scorecard_q[i]) & (i1_s3_itag == id);
end
end
endgenerate
assign i0_s1_itag_v = |(i0_s1_itag_v_gated);
assign i0_s2_itag_v = |(i0_s2_itag_v_gated);
assign i0_s3_itag_v = |(i0_s3_itag_v_gated);
assign i1_s1_itag_v = |(i1_s1_itag_v_gated);
assign i1_s2_itag_v = |(i1_s2_itag_v_gated);
assign i1_s3_itag_v = |(i1_s3_itag_v_gated);
//------------------------------------------------------------------------------------------------------------
// Storage Elements
//------------------------------------------------------------------------------------------------------------
tri_rlmreg_p #(.WIDTH(num_entries_g), .INIT(0) ) scorecard_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rv0_sc_act),
.thold_b(chip_b_sl_2_thold_0_b),
.sg(chip_b_sl_sg_0_t),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[`scorecard_offset :`scorecard_offset + num_entries_g - 1]),
.scout(sov[`scorecard_offset :`scorecard_offset + num_entries_g - 1]),
.din(scorecard_d),
.dout(scorecard_q)
);
//---------------------------------------------------------------------
// Scan
//---------------------------------------------------------------------
assign siv[0:`scan_right-1] = {sov[1:`scan_right-1], scan_in};
assign scan_out = sov[0];
endmodule |
module xu_fctr
#(
parameter CLOCKGATE = 1,
parameter PASSTHRU = 1,
parameter DELAY_WIDTH = 4,
parameter WIDTH = 2
)
(
input [0:`NCLK_WIDTH-1] nclk,
input force_t,
input thold_b,
input sg,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input scin,
output scout,
input [0:WIDTH-1] din,
output [0:WIDTH-1] dout,
input [0:DELAY_WIDTH-1] delay,
inout vdd,
inout gnd
);
// Latches
wire [0:DELAY_WIDTH-1] delay_q[0:WIDTH-1];
wire [0:DELAY_WIDTH-1] delay_d[0:WIDTH-1];
// Scanchains
localparam delay_offset = 0;
localparam scan_right = delay_offset + DELAY_WIDTH*WIDTH;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
// Signals
wire [0:WIDTH-1] set;
wire [0:WIDTH-1] zero_b;
wire [0:WIDTH-1] act;
generate
genvar t;
for (t=0;t<=WIDTH-1;t=t+1)
begin : threads_gen
wire [0:DELAY_WIDTH-1] delay_m1;
assign set[t] = din[t];
assign zero_b[t] = |(delay_q[t]);
assign delay_m1 = delay_q[t] - {{DELAY_WIDTH-1{1'b0}},1'b1};
if (CLOCKGATE == 0) begin : clockgate_0
assign act[t] = set[t] | zero_b[t];
assign delay_d[t] = ({set[t], zero_b[t]} == 2'b11) ? delay :
({set[t], zero_b[t]} == 2'b10) ? delay :
({set[t], zero_b[t]} == 2'b01) ? delay_m1 :
delay_q[t];
end
if (CLOCKGATE == 1) begin : clockgate_1
assign act[t] = set[t] | zero_b[t];
assign delay_d[t] = (set[t] == 1'b1) ? delay :
delay_m1;
end
if (PASSTHRU == 1)begin : PASSTHRU_gen_1
assign dout[t] = zero_b[t] | din[t];
end
if (PASSTHRU == 0) begin : PASSTHRU_gen_0
assign dout[t] = zero_b[t];
end
tri_rlmreg_p #(.WIDTH(DELAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) delay_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(act[t]),
.force_t(force_t),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.thold_b(thold_b),
.sg(sg),
.scin(siv[delay_offset+DELAY_WIDTH*t:delay_offset+DELAY_WIDTH*(t+1)-1]),
.scout(sov[delay_offset+DELAY_WIDTH*t:delay_offset+DELAY_WIDTH*(t+1)-1]),
.din(delay_d[t]),
.dout(delay_q[t])
);
end
endgenerate
assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scin};
assign scout = sov[0];
endmodule |
module mmq_tlb_lrat_matchline(
inout vdd,
inout gnd,
input [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] addr_in,
input addr_enable,
input [0:3] entry_size,
input [0:`LRAT_CMPMASK_WIDTH-1] entry_cmpmask,
input entry_xbit,
input [0:`LRAT_CMPMASK_WIDTH-1] entry_xbitmask,
input [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] entry_lpn,
input [0:`LPID_WIDTH-1] entry_lpid,
input [0:`LPID_WIDTH-1] comp_lpid,
input lpid_enable,
input entry_v,
output match,
output dbg_addr_match,
output dbg_lpid_match
);
parameter HAVE_XBIT = 1;
parameter NUM_PGSIZES = 8;
parameter HAVE_CMPMASK = 1;
//----------------------------------------------------------------------
// Components
//----------------------------------------------------------------------
//----------------------------------------------------------------------
// Signals
//----------------------------------------------------------------------
wire [64-`LRAT_MAXSIZE_LOG2:64-`LRAT_MINSIZE_LOG2-1] entry_lpn_b;
wire function_24_43;
wire function_26_43;
wire function_30_43;
wire function_32_43;
wire function_34_43;
wire function_36_43;
wire function_40_43;
wire pgsize_eq_16M; // PS7
wire pgsize_eq_256M; // PS9
wire pgsize_eq_1G; // PS10
wire pgsize_eq_4G; // PS11
wire pgsize_eq_16G; // PS12
wire pgsize_eq_256G; // PS14
wire pgsize_eq_1T; // PS15
wire pgsize_gte_16M; // PS7
wire pgsize_gte_256M; // PS9
wire pgsize_gte_1G; // PS10
wire pgsize_gte_4G; // PS11
wire pgsize_gte_16G; // PS12
wire pgsize_gte_256G; // PS14
wire pgsize_gte_1T; // PS15
wire comp_or_24_25;
wire comp_or_26_29;
wire comp_or_30_31;
wire comp_or_32_33;
wire comp_or_34_35;
wire comp_or_36_39;
wire comp_or_40_43;
wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2+`LPID_WIDTH-1] match_line;
wire addr_match;
wire lpid_match;
(* analysis_not_referenced="true" *)
wire [0:2] unused_dc;
assign match_line[64-`REAL_ADDR_WIDTH : 64-`LRAT_MINSIZE_LOG2+`LPID_WIDTH-1] =
(~ (({entry_lpn[64-`REAL_ADDR_WIDTH : 64-`LRAT_MINSIZE_LOG2-1], entry_lpid[0:`LPID_WIDTH-1]}) ^
({ addr_in[64-`REAL_ADDR_WIDTH : 64-`LRAT_MINSIZE_LOG2-1], comp_lpid[0:`LPID_WIDTH-1]})) );
generate
if (NUM_PGSIZES == 8)
begin : numpgsz8
assign entry_lpn_b[64 - `LRAT_MAXSIZE_LOG2:64 - `LRAT_MINSIZE_LOG2 - 1] = (~(entry_lpn[64 - `LRAT_MAXSIZE_LOG2:64 - `LRAT_MINSIZE_LOG2 - 1]));
if (HAVE_CMPMASK == 0) // PS7
begin : gen_nocmpmask80
assign pgsize_eq_16M = ((entry_size == 4'b0111)) ? 1'b1 :
1'b0;
assign pgsize_eq_256M = ((entry_size == 4'b1001)) ? 1'b1 : // PS9
1'b0;
assign pgsize_eq_1G = ((entry_size == 4'b1010)) ? 1'b1 : // PS10
1'b0;
assign pgsize_eq_4G = ((entry_size == 4'b1011)) ? 1'b1 : // PS11
1'b0;
assign pgsize_eq_16G = ((entry_size == 4'b1100)) ? 1'b1 : // PS12
1'b0;
assign pgsize_eq_256G = ((entry_size == 4'b1110)) ? 1'b1 : // PS14
1'b0;
assign pgsize_eq_1T = ((entry_size == 4'b1111)) ? 1'b1 : // PS15
1'b0;
assign pgsize_gte_16M = ((entry_size == 4'b0111 | pgsize_gte_256M == 1'b1)) ? 1'b1 : // PS7 or larger
1'b0;
assign pgsize_gte_256M = ((entry_size == 4'b1001 | pgsize_gte_1G == 1'b1)) ? 1'b1 : // PS9 or larger
1'b0;
assign pgsize_gte_1G = ((entry_size == 4'b1010 | pgsize_gte_4G == 1'b1)) ? 1'b1 : // PS10 or larger
1'b0;
assign pgsize_gte_4G = ((entry_size == 4'b1011 | pgsize_gte_16G == 1'b1)) ? 1'b1 : // PS11 or larger
1'b0;
assign pgsize_gte_16G = ((entry_size == 4'b1100 | pgsize_gte_256G == 1'b1)) ? 1'b1 : // PS12 or larger
1'b0;
assign pgsize_gte_256G = ((entry_size == 4'b1110 | pgsize_gte_1T == 1'b1)) ? 1'b1 : // PS14 or larger
1'b0;
assign pgsize_gte_1T = ((entry_size == 4'b1111)) ? 1'b1 : // PS15
1'b0;
end
// size entry_cmpmask: 0123456
// 1TB 1111111
// 256GB 0111111
// 16GB 0011111
// 4GB 0001111
// 1GB 0000111
// 256MB 0000011
// 16MB 0000001
// 1MB 0000000
if (HAVE_CMPMASK == 1)
begin : gen_cmpmask80
assign pgsize_gte_1T = entry_cmpmask[0];
assign pgsize_gte_256G = entry_cmpmask[1];
assign pgsize_gte_16G = entry_cmpmask[2];
assign pgsize_gte_4G = entry_cmpmask[3];
assign pgsize_gte_1G = entry_cmpmask[4];
assign pgsize_gte_256M = entry_cmpmask[5];
assign pgsize_gte_16M = entry_cmpmask[6];
// size entry_xbitmask: 0123456
// 1TB 1000000
// 256GB 0100000
// 16GB 0010000
// 4GB 0001000
// 1GB 0000100
// 256MB 0000010
// 16MB 0000001
// 1MB 0000000
assign pgsize_eq_1T = entry_xbitmask[0];
assign pgsize_eq_256G = entry_xbitmask[1];
assign pgsize_eq_16G = entry_xbitmask[2];
assign pgsize_eq_4G = entry_xbitmask[3];
assign pgsize_eq_1G = entry_xbitmask[4];
assign pgsize_eq_256M = entry_xbitmask[5];
assign pgsize_eq_16M = entry_xbitmask[6];
end
if (HAVE_XBIT == 0)
begin : gen_noxbit80
assign function_24_43 = 1'b0;
assign function_26_43 = 1'b0;
assign function_30_43 = 1'b0;
assign function_32_43 = 1'b0;
assign function_34_43 = 1'b0;
assign function_36_43 = 1'b0;
assign function_40_43 = 1'b0;
end
if (HAVE_XBIT != 0 & `REAL_ADDR_WIDTH == 42)
begin : gen_xbit80
assign function_24_43 = (~(entry_xbit)) | (~(pgsize_eq_1T)) | |(entry_lpn_b[24:43] & addr_in[24:43]);
assign function_26_43 = (~(entry_xbit)) | (~(pgsize_eq_256G)) | |(entry_lpn_b[26:43] & addr_in[26:43]);
assign function_30_43 = (~(entry_xbit)) | (~(pgsize_eq_16G)) | |(entry_lpn_b[30:43] & addr_in[30:43]);
assign function_32_43 = (~(entry_xbit)) | (~(pgsize_eq_4G)) | |(entry_lpn_b[32:43] & addr_in[32:43]);
assign function_34_43 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | |(entry_lpn_b[34:43] & addr_in[34:43]);
assign function_36_43 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | |(entry_lpn_b[36:43] & addr_in[36:43]);
assign function_40_43 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | |(entry_lpn_b[40:43] & addr_in[40:43]);
end
if (HAVE_XBIT != 0 & `REAL_ADDR_WIDTH == 32)
begin : gen_xbit81
assign function_24_43 = 1'b1;
assign function_26_43 = 1'b1;
assign function_30_43 = 1'b1;
assign function_32_43 = 1'b1;
assign function_34_43 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | |(entry_lpn_b[34:43] & addr_in[34:43]);
assign function_36_43 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | |(entry_lpn_b[36:43] & addr_in[36:43]);
assign function_40_43 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | |(entry_lpn_b[40:43] & addr_in[40:43]);
end
if (`REAL_ADDR_WIDTH == 42)
begin : gen_comp80
assign comp_or_24_25 = &(match_line[24:25]) | pgsize_gte_1T;
assign comp_or_26_29 = &(match_line[26:29]) | pgsize_gte_256G;
assign comp_or_30_31 = &(match_line[30:31]) | pgsize_gte_16G;
assign comp_or_32_33 = &(match_line[32:33]) | pgsize_gte_4G;
assign comp_or_34_35 = &(match_line[34:35]) | pgsize_gte_1G;
assign comp_or_36_39 = &(match_line[36:39]) | pgsize_gte_256M;
assign comp_or_40_43 = &(match_line[40:43]) | pgsize_gte_16M;
end
if (`REAL_ADDR_WIDTH == 32)
begin : gen_comp81
assign comp_or_24_25 = 1'b1;
assign comp_or_26_29 = 1'b1;
assign comp_or_30_31 = 1'b1;
assign comp_or_32_33 = 1'b1;
assign comp_or_34_35 = &(match_line[34:35]) | pgsize_gte_1G;
assign comp_or_36_39 = &(match_line[36:39]) | pgsize_gte_256M;
assign comp_or_40_43 = &(match_line[40:43]) | pgsize_gte_16M;
end
if (HAVE_XBIT == 0 & `REAL_ADDR_WIDTH == 42)
begin : gen_noxbit81
// Regular compare largest page size
assign addr_match = ( &(match_line[22:23]) &
comp_or_24_25 &
comp_or_26_29 &
comp_or_30_31 &
comp_or_32_33 &
comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 ) | (~(addr_enable)); // Ignore functions based on page size
end
// Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
if (HAVE_XBIT == 0 & `REAL_ADDR_WIDTH == 32)
begin : gen_noxbit82
// Regular compare largest page size
assign addr_match = ( &(match_line[32:33]) &
comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 ) | (~(addr_enable)); // Ignore functions based on page size
end
// Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
if (HAVE_XBIT != 0 & `REAL_ADDR_WIDTH == 42)
begin : gen_xbit82
// Exclusion functions
// Regular compare largest page size
assign addr_match = ( &(match_line[22:23]) &
comp_or_24_25 &
comp_or_26_29 &
comp_or_30_31 &
comp_or_32_33 &
comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
function_24_43 &
function_26_43 &
function_30_43 &
function_32_43 &
function_34_43 &
function_36_43 &
function_40_43 ) | (~(addr_enable)); // Ignore functions based on page size
end
// Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
if (HAVE_XBIT != 0 & `REAL_ADDR_WIDTH == 32)
begin : gen_xbit83
// Exclusion functions
// Regular compare largest page size
assign addr_match = ( &(match_line[32:33]) &
comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
function_34_43 &
function_36_43 &
function_40_43 ) | (~(addr_enable)); // Ignore functions based on page size
end
end
endgenerate
// Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
// numpgsz8: NUM_PGSIZES = 8
//signal match_line : std_ulogic_vector(64-`REAL_ADDR_WIDTH to 64-`LRAT_MINSIZE_LOG2+`LPID_WIDTH-1);
// entry_lpid=0 ignores lpid match for translation, not invalidation
assign lpid_match = &(match_line[64 - `LRAT_MINSIZE_LOG2:64 - `LRAT_MINSIZE_LOG2 + `LPID_WIDTH - 1]) | (~(|(entry_lpid[0:7]))) | (~(lpid_enable));
// Address compare
assign match = addr_match & lpid_match & entry_v; // LPID compare
// Valid
// debug outputs
assign dbg_addr_match = addr_match; // out std_ulogic;
assign dbg_lpid_match = lpid_match; // out std_ulogic;
generate
if (HAVE_CMPMASK == 0)
begin : gen_unused0
assign unused_dc[0] = 1'b0;
assign unused_dc[1] = vdd;
assign unused_dc[2] = gnd;
end
endgenerate
generate
if (HAVE_CMPMASK == 1)
begin : gen_unused1
assign unused_dc[0] = |(entry_size);
assign unused_dc[1] = vdd;
assign unused_dc[2] = gnd;
end
endgenerate
endmodule |
module fu_tblsqo(
f,
est,
rng
);
input [1:6] f;
output [1:20] est;
output [6:20] rng;
// end ports
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire dcd_00x;
wire dcd_01x;
wire dcd_10x;
wire dcd_11x;
wire dcd_000;
wire dcd_001;
wire dcd_010;
wire dcd_011;
wire dcd_100;
wire dcd_101;
wire dcd_110;
wire dcd_111;
wire combo2_1000;
wire combo2_0100;
wire combo2_1100;
wire combo2_0010;
wire combo2_1010;
wire combo2_0110;
wire combo2_1110;
wire combo2_0001;
wire combo2_1001;
wire combo2_0101;
wire combo2_1101;
wire combo2_0011;
wire combo2_1011;
wire combo2_0111;
wire combo2_1000_xxxx_b;
wire combo2_0100_xxxx_b;
wire combo2_1100_xxxx_b;
wire combo2_0010_xxxx_b;
wire combo2_1010_xxxx_b;
wire combo2_0110_xxxx_b;
wire combo2_1110_xxxx_b;
wire combo2_0001_xxxx_b;
wire combo2_1001_xxxx_b;
wire combo2_0101_xxxx_b;
wire combo2_1101_xxxx_b;
wire combo2_0011_xxxx_b;
wire combo2_1011_xxxx_b;
wire combo2_0111_xxxx_b;
wire combo2_xxxx_1000_b;
wire combo2_xxxx_0100_b;
wire combo2_xxxx_1100_b;
wire combo2_xxxx_0010_b;
wire combo2_xxxx_1010_b;
wire combo2_xxxx_0110_b;
wire combo2_xxxx_1110_b;
wire combo2_xxxx_0001_b;
wire combo2_xxxx_1001_b;
wire combo2_xxxx_0101_b;
wire combo2_xxxx_1101_b;
wire combo2_xxxx_0011_b;
wire combo2_xxxx_1011_b;
wire combo2_xxxx_0111_b;
wire combo3_0000_0001;
wire combo3_0000_0011;
wire combo3_0000_0100;
wire combo3_0000_1011;
wire combo3_0000_1100;
wire combo3_0000_1101;
wire combo3_0000_1111;
wire combo3_0001_0001;
wire combo3_0001_0010;
wire combo3_0001_0100;
wire combo3_0001_0101;
wire combo3_0001_0111;
wire combo3_0001_1000;
wire combo3_0001_1110;
wire combo3_0001_1111;
wire combo3_0010_0001;
wire combo3_0010_0010;
wire combo3_0010_0011;
wire combo3_0010_0100;
wire combo3_0010_0110;
wire combo3_0010_1001;
wire combo3_0010_1101;
wire combo3_0010_1110;
wire combo3_0011_0000;
wire combo3_0011_0001;
wire combo3_0011_0011;
wire combo3_0011_0100;
wire combo3_0011_0101;
wire combo3_0011_1000;
wire combo3_0011_1001;
wire combo3_0011_1010;
wire combo3_0011_1100;
wire combo3_0011_1110;
wire combo3_0011_1111;
wire combo3_0100_0000;
wire combo3_0100_0101;
wire combo3_0100_0110;
wire combo3_0100_1000;
wire combo3_0100_1001;
wire combo3_0100_1010;
wire combo3_0100_1100;
wire combo3_0100_1101;
wire combo3_0101_0000;
wire combo3_0101_0001;
wire combo3_0101_0011;
wire combo3_0101_0101;
wire combo3_0101_0110;
wire combo3_0101_1001;
wire combo3_0101_1010;
wire combo3_0101_1110;
wire combo3_0101_1111;
wire combo3_0110_0011;
wire combo3_0110_0110;
wire combo3_0110_0111;
wire combo3_0110_1001;
wire combo3_0110_1010;
wire combo3_0110_1011;
wire combo3_0110_1100;
wire combo3_0110_1101;
wire combo3_0110_1110;
wire combo3_0110_1111;
wire combo3_0111_0000;
wire combo3_0111_0010;
wire combo3_0111_0011;
wire combo3_0111_0110;
wire combo3_0111_1000;
wire combo3_0111_1001;
wire combo3_0111_1100;
wire combo3_0111_1110;
wire combo3_0111_1111;
wire combo3_1000_0000;
wire combo3_1000_0001;
wire combo3_1000_0011;
wire combo3_1000_0110;
wire combo3_1000_1000;
wire combo3_1000_1010;
wire combo3_1000_1101;
wire combo3_1000_1110;
wire combo3_1000_1111;
wire combo3_1001_0000;
wire combo3_1001_0010;
wire combo3_1001_0011;
wire combo3_1001_0100;
wire combo3_1001_0111;
wire combo3_1001_1000;
wire combo3_1001_1001;
wire combo3_1001_1010;
wire combo3_1001_1100;
wire combo3_1001_1101;
wire combo3_1001_1110;
wire combo3_1001_1111;
wire combo3_1010_0010;
wire combo3_1010_0100;
wire combo3_1010_0101;
wire combo3_1010_0110;
wire combo3_1010_0111;
wire combo3_1010_1010;
wire combo3_1010_1100;
wire combo3_1010_1101;
wire combo3_1010_1110;
wire combo3_1011_0011;
wire combo3_1011_0110;
wire combo3_1011_0111;
wire combo3_1011_1000;
wire combo3_1011_1001;
wire combo3_1011_1010;
wire combo3_1011_1011;
wire combo3_1011_1110;
wire combo3_1100_0000;
wire combo3_1100_0001;
wire combo3_1100_0011;
wire combo3_1100_0110;
wire combo3_1100_0111;
wire combo3_1100_1010;
wire combo3_1100_1100;
wire combo3_1100_1110;
wire combo3_1101_0000;
wire combo3_1101_0011;
wire combo3_1101_0101;
wire combo3_1101_1000;
wire combo3_1101_1010;
wire combo3_1101_1011;
wire combo3_1101_1101;
wire combo3_1110_0000;
wire combo3_1110_0001;
wire combo3_1110_0010;
wire combo3_1110_0011;
wire combo3_1110_0100;
wire combo3_1110_0101;
wire combo3_1110_0110;
wire combo3_1110_1010;
wire combo3_1110_1011;
wire combo3_1111_0000;
wire combo3_1111_0011;
wire combo3_1111_0101;
wire combo3_1111_1000;
wire combo3_1111_1001;
wire combo3_1111_1011;
wire combo3_1111_1100;
wire combo3_1111_1110;
wire [0:7] e_00_b;
wire [0:7] e_01_b;
wire [0:7] e_02_b;
wire [0:7] e_03_b;
wire [0:7] e_04_b;
wire [0:7] e_05_b;
wire [0:7] e_06_b;
wire [0:7] e_07_b;
wire [0:7] e_08_b;
wire [0:7] e_09_b;
wire [0:7] e_10_b;
wire [0:7] e_11_b;
wire [0:7] e_12_b;
wire [0:7] e_13_b;
wire [0:7] e_14_b;
wire [0:7] e_15_b;
wire [0:7] e_16_b;
wire [0:7] e_17_b;
wire [0:7] e_18_b;
wire [0:7] e_19_b;
wire [0:19] e;
wire [0:7] r_00_b;
wire [0:7] r_01_b;
wire [0:7] r_02_b;
wire [0:7] r_03_b;
wire [0:7] r_04_b;
wire [0:7] r_05_b;
wire [0:7] r_06_b;
wire [0:7] r_07_b;
wire [0:7] r_08_b;
wire [0:7] r_09_b;
wire [0:7] r_10_b;
wire [0:7] r_11_b;
wire [0:7] r_12_b;
wire [0:7] r_13_b;
wire [0:7] r_14_b;
wire [0:14] r;
////#######################################
////## decode the upper 3 index bits
////#######################################
assign dcd_00x = (~f[1]) & (~f[2]);
assign dcd_01x = (~f[1]) & f[2];
assign dcd_10x = f[1] & (~f[2]);
assign dcd_11x = f[1] & f[2];
assign dcd_000 = (~f[3]) & dcd_00x;
assign dcd_001 = f[3] & dcd_00x;
assign dcd_010 = (~f[3]) & dcd_01x;
assign dcd_011 = f[3] & dcd_01x;
assign dcd_100 = (~f[3]) & dcd_10x;
assign dcd_101 = f[3] & dcd_10x;
assign dcd_110 = (~f[3]) & dcd_11x;
assign dcd_111 = f[3] & dcd_11x;
////#######################################
////## combos based on lower 2 index bits
////#######################################
assign combo2_1000 = (~f[5]) & (~f[6]); // [0]
assign combo2_0100 = (~f[5]) & f[6]; // [1]
assign combo2_1100 = (~f[5]); // [0,1]
assign combo2_0010 = f[5] & (~f[6]); // [2]
assign combo2_1010 = (~f[6]); // [0,2]
assign combo2_0110 = f[5] ^ f[6]; // [1,2]
assign combo2_1110 = (~(f[5] & f[6])); // [0,1,2]
assign combo2_0001 = f[5] & f[6]; // [3]
assign combo2_1001 = (~(f[5] ^ f[6])); // [0,3]
assign combo2_0101 = f[6]; // [1,3]
assign combo2_1101 = (~(f[5] & (~f[6]))); // [1,2,3]
assign combo2_0011 = f[5]; // [2,3]
assign combo2_1011 = (~((~f[5]) & f[6])); // [0,2,3]
assign combo2_0111 = (~((~f[5]) & (~f[6]))); // [1,2,3]
////#######################################
////## combos based on lower 3 index bits
////#######################################
assign combo2_1000_xxxx_b = (~((~f[4]) & combo2_1000));
assign combo2_0100_xxxx_b = (~((~f[4]) & combo2_0100));
assign combo2_1100_xxxx_b = (~((~f[4]) & combo2_1100));
assign combo2_0010_xxxx_b = (~((~f[4]) & combo2_0010));
assign combo2_1010_xxxx_b = (~((~f[4]) & combo2_1010));
assign combo2_0110_xxxx_b = (~((~f[4]) & combo2_0110));
assign combo2_1110_xxxx_b = (~((~f[4]) & combo2_1110));
assign combo2_0001_xxxx_b = (~((~f[4]) & combo2_0001));
assign combo2_1001_xxxx_b = (~((~f[4]) & combo2_1001));
assign combo2_0101_xxxx_b = (~((~f[4]) & combo2_0101));
assign combo2_1101_xxxx_b = (~((~f[4]) & combo2_1101));
assign combo2_0011_xxxx_b = (~((~f[4]) & combo2_0011));
assign combo2_1011_xxxx_b = (~((~f[4]) & combo2_1011));
assign combo2_0111_xxxx_b = (~((~f[4]) & combo2_0111));
assign combo2_xxxx_1000_b = (~(f[4] & combo2_1000));
assign combo2_xxxx_0100_b = (~(f[4] & combo2_0100));
assign combo2_xxxx_1100_b = (~(f[4] & combo2_1100));
assign combo2_xxxx_0010_b = (~(f[4] & combo2_0010));
assign combo2_xxxx_1010_b = (~(f[4] & combo2_1010));
assign combo2_xxxx_0110_b = (~(f[4] & combo2_0110));
assign combo2_xxxx_1110_b = (~(f[4] & combo2_1110));
assign combo2_xxxx_0001_b = (~(f[4] & combo2_0001));
assign combo2_xxxx_1001_b = (~(f[4] & combo2_1001));
assign combo2_xxxx_0101_b = (~(f[4] & combo2_0101));
assign combo2_xxxx_1101_b = (~(f[4] & combo2_1101));
assign combo2_xxxx_0011_b = (~(f[4] & combo2_0011));
assign combo2_xxxx_1011_b = (~(f[4] & combo2_1011));
assign combo2_xxxx_0111_b = (~(f[4] & combo2_0111));
assign combo3_0000_0001 = (~(combo2_xxxx_0001_b)); //i=1, 1 1
assign combo3_0000_0011 = (~(combo2_xxxx_0011_b)); //i=3, 4 2
assign combo3_0000_0100 = (~(combo2_xxxx_0100_b)); //i=4, 1 3
assign combo3_0000_1011 = (~(combo2_xxxx_1011_b)); //i=11, 1 4
assign combo3_0000_1100 = (~(combo2_xxxx_1100_b)); //i=12, 1 5
assign combo3_0000_1101 = (~(combo2_xxxx_1101_b)); //i=13, 1 6
assign combo3_0000_1111 = (~((~f[4]))); //i=15, 4 7
assign combo3_0001_0001 = (~((~combo2_0001))); //i=17, 1 8*
assign combo3_0001_0010 = (~(combo2_0001_xxxx_b & combo2_xxxx_0010_b)); //i=18, 1 9
assign combo3_0001_0100 = (~(combo2_0001_xxxx_b & combo2_xxxx_0100_b)); //i=20, 1 10
assign combo3_0001_0101 = (~(combo2_0001_xxxx_b & combo2_xxxx_0101_b)); //i=21, 2 11
assign combo3_0001_0111 = (~(combo2_0001_xxxx_b & combo2_xxxx_0111_b)); //i=23, 1 12
assign combo3_0001_1000 = (~(combo2_0001_xxxx_b & combo2_xxxx_1000_b)); //i=24, 1 13
assign combo3_0001_1110 = (~(combo2_0001_xxxx_b & combo2_xxxx_1110_b)); //i=30, 1 14
assign combo3_0001_1111 = (~(combo2_0001_xxxx_b & (~f[4]))); //i=31, 2 15
assign combo3_0010_0001 = (~(combo2_0010_xxxx_b & combo2_xxxx_0001_b)); //i=33, 1 16
assign combo3_0010_0010 = (~((~combo2_0010))); //i=34, 1 17*
assign combo3_0010_0011 = (~(combo2_0010_xxxx_b & combo2_xxxx_0011_b)); //i=35, 1 18
assign combo3_0010_0100 = (~(combo2_0010_xxxx_b & combo2_xxxx_0100_b)); //i=36, 1 19
assign combo3_0010_0110 = (~(combo2_0010_xxxx_b & combo2_xxxx_0110_b)); //i=38, 2 20
assign combo3_0010_1001 = (~(combo2_0010_xxxx_b & combo2_xxxx_1001_b)); //i=41, 2 21
assign combo3_0010_1101 = (~(combo2_0010_xxxx_b & combo2_xxxx_1101_b)); //i=45, 2 22
assign combo3_0010_1110 = (~(combo2_0010_xxxx_b & combo2_xxxx_1110_b)); //i=46, 1 23
assign combo3_0011_0000 = (~(combo2_0011_xxxx_b)); //i=48, 1 24
assign combo3_0011_0001 = (~(combo2_0011_xxxx_b & combo2_xxxx_0001_b)); //i=49, 3 25
assign combo3_0011_0011 = (~((~combo2_0011))); //i=51, 1 26*
assign combo3_0011_0100 = (~(combo2_0011_xxxx_b & combo2_xxxx_0100_b)); //i=52, 1 27
assign combo3_0011_0101 = (~(combo2_0011_xxxx_b & combo2_xxxx_0101_b)); //i=53, 1 28
assign combo3_0011_1000 = (~(combo2_0011_xxxx_b & combo2_xxxx_1000_b)); //i=56, 5 29
assign combo3_0011_1001 = (~(combo2_0011_xxxx_b & combo2_xxxx_1001_b)); //i=57, 4 30
assign combo3_0011_1010 = (~(combo2_0011_xxxx_b & combo2_xxxx_1010_b)); //i=58, 1 31
assign combo3_0011_1100 = (~(combo2_0011_xxxx_b & combo2_xxxx_1100_b)); //i=60, 2 32
assign combo3_0011_1110 = (~(combo2_0011_xxxx_b & combo2_xxxx_1110_b)); //i=62, 2 33
assign combo3_0011_1111 = (~(combo2_0011_xxxx_b & (~f[4]))); //i=63, 3 34
assign combo3_0100_0000 = (~(combo2_0100_xxxx_b)); //i=64, 1 35
assign combo3_0100_0101 = (~(combo2_0100_xxxx_b & combo2_xxxx_0101_b)); //i=69, 1 36
assign combo3_0100_0110 = (~(combo2_0100_xxxx_b & combo2_xxxx_0110_b)); //i=70, 1 37
assign combo3_0100_1000 = (~(combo2_0100_xxxx_b & combo2_xxxx_1000_b)); //i=72, 1 38
assign combo3_0100_1001 = (~(combo2_0100_xxxx_b & combo2_xxxx_1001_b)); //i=73, 1 39
assign combo3_0100_1010 = (~(combo2_0100_xxxx_b & combo2_xxxx_1010_b)); //i=74, 2 40
assign combo3_0100_1100 = (~(combo2_0100_xxxx_b & combo2_xxxx_1100_b)); //i=76, 1 41
assign combo3_0100_1101 = (~(combo2_0100_xxxx_b & combo2_xxxx_1101_b)); //i=77, 1 42
assign combo3_0101_0000 = (~(combo2_0101_xxxx_b)); //i=80, 1 43
assign combo3_0101_0001 = (~(combo2_0101_xxxx_b & combo2_xxxx_0001_b)); //i=81, 2 44
assign combo3_0101_0011 = (~(combo2_0101_xxxx_b & combo2_xxxx_0011_b)); //i=83, 1 45
assign combo3_0101_0101 = (~((~combo2_0101))); //i=85, 1 46*
assign combo3_0101_0110 = (~(combo2_0101_xxxx_b & combo2_xxxx_0110_b)); //i=86, 1 47
assign combo3_0101_1001 = (~(combo2_0101_xxxx_b & combo2_xxxx_1001_b)); //i=89, 1 48
assign combo3_0101_1010 = (~(combo2_0101_xxxx_b & combo2_xxxx_1010_b)); //i=90, 1 49
assign combo3_0101_1110 = (~(combo2_0101_xxxx_b & combo2_xxxx_1110_b)); //i=94, 1 50
assign combo3_0101_1111 = (~(combo2_0101_xxxx_b & (~f[4]))); //i=95, 1 51
assign combo3_0110_0011 = (~(combo2_0110_xxxx_b & combo2_xxxx_0011_b)); //i=99, 1 52
assign combo3_0110_0110 = (~((~combo2_0110))); //i=102, 2 53*
assign combo3_0110_0111 = (~(combo2_0110_xxxx_b & combo2_xxxx_0111_b)); //i=103, 1 54
assign combo3_0110_1001 = (~(combo2_0110_xxxx_b & combo2_xxxx_1001_b)); //i=105, 1 55
assign combo3_0110_1010 = (~(combo2_0110_xxxx_b & combo2_xxxx_1010_b)); //i=106, 1 56
assign combo3_0110_1011 = (~(combo2_0110_xxxx_b & combo2_xxxx_1011_b)); //i=107, 1 57
assign combo3_0110_1100 = (~(combo2_0110_xxxx_b & combo2_xxxx_1100_b)); //i=108, 1 58
assign combo3_0110_1101 = (~(combo2_0110_xxxx_b & combo2_xxxx_1101_b)); //i=109, 4 59
assign combo3_0110_1110 = (~(combo2_0110_xxxx_b & combo2_xxxx_1110_b)); //i=110, 1 60
assign combo3_0110_1111 = (~(combo2_0110_xxxx_b & (~f[4]))); //i=111, 1 61
assign combo3_0111_0000 = (~(combo2_0111_xxxx_b)); //i=112, 1 62
assign combo3_0111_0010 = (~(combo2_0111_xxxx_b & combo2_xxxx_0010_b)); //i=114, 3 63
assign combo3_0111_0011 = (~(combo2_0111_xxxx_b & combo2_xxxx_0011_b)); //i=115, 1 64
assign combo3_0111_0110 = (~(combo2_0111_xxxx_b & combo2_xxxx_0110_b)); //i=118, 1 65
assign combo3_0111_1000 = (~(combo2_0111_xxxx_b & combo2_xxxx_1000_b)); //i=120, 2 66
assign combo3_0111_1001 = (~(combo2_0111_xxxx_b & combo2_xxxx_1001_b)); //i=121, 1 67
assign combo3_0111_1100 = (~(combo2_0111_xxxx_b & combo2_xxxx_1100_b)); //i=124, 2 68
assign combo3_0111_1110 = (~(combo2_0111_xxxx_b & combo2_xxxx_1110_b)); //i=126, 1 69
assign combo3_0111_1111 = (~(combo2_0111_xxxx_b & (~f[4]))); //i=127, 3 70
assign combo3_1000_0000 = (~(combo2_1000_xxxx_b)); //i=128, 4 71
assign combo3_1000_0001 = (~(combo2_1000_xxxx_b & combo2_xxxx_0001_b)); //i=129, 1 72
assign combo3_1000_0011 = (~(combo2_1000_xxxx_b & combo2_xxxx_0011_b)); //i=131, 2 73
assign combo3_1000_0110 = (~(combo2_1000_xxxx_b & combo2_xxxx_0110_b)); //i=134, 1 74
assign combo3_1000_1000 = (~((~combo2_1000))); //i=136, 1 75*
assign combo3_1000_1010 = (~(combo2_1000_xxxx_b & combo2_xxxx_1010_b)); //i=138, 2 76
assign combo3_1000_1101 = (~(combo2_1000_xxxx_b & combo2_xxxx_1101_b)); //i=141, 1 77
assign combo3_1000_1110 = (~(combo2_1000_xxxx_b & combo2_xxxx_1110_b)); //i=142, 1 78
assign combo3_1000_1111 = (~(combo2_1000_xxxx_b & (~f[4]))); //i=143, 1 79
assign combo3_1001_0000 = (~(combo2_1001_xxxx_b)); //i=144, 1 80
assign combo3_1001_0010 = (~(combo2_1001_xxxx_b & combo2_xxxx_0010_b)); //i=146, 2 81
assign combo3_1001_0011 = (~(combo2_1001_xxxx_b & combo2_xxxx_0011_b)); //i=147, 2 82
assign combo3_1001_0100 = (~(combo2_1001_xxxx_b & combo2_xxxx_0100_b)); //i=148, 2 83
assign combo3_1001_0111 = (~(combo2_1001_xxxx_b & combo2_xxxx_0111_b)); //i=151, 1 84
assign combo3_1001_1000 = (~(combo2_1001_xxxx_b & combo2_xxxx_1000_b)); //i=152, 1 85
assign combo3_1001_1001 = (~((~combo2_1001))); //i=153, 3 86*
assign combo3_1001_1010 = (~(combo2_1001_xxxx_b & combo2_xxxx_1010_b)); //i=154, 2 87
assign combo3_1001_1100 = (~(combo2_1001_xxxx_b & combo2_xxxx_1100_b)); //i=156, 2 88
assign combo3_1001_1101 = (~(combo2_1001_xxxx_b & combo2_xxxx_1101_b)); //i=157, 1 89
assign combo3_1001_1110 = (~(combo2_1001_xxxx_b & combo2_xxxx_1110_b)); //i=158, 1 90
assign combo3_1001_1111 = (~(combo2_1001_xxxx_b & (~f[4]))); //i=159, 1 91
assign combo3_1010_0010 = (~(combo2_1010_xxxx_b & combo2_xxxx_0010_b)); //i=162, 1 92
assign combo3_1010_0100 = (~(combo2_1010_xxxx_b & combo2_xxxx_0100_b)); //i=164, 2 93
assign combo3_1010_0101 = (~(combo2_1010_xxxx_b & combo2_xxxx_0101_b)); //i=165, 1 94
assign combo3_1010_0110 = (~(combo2_1010_xxxx_b & combo2_xxxx_0110_b)); //i=166, 1 95
assign combo3_1010_0111 = (~(combo2_1010_xxxx_b & combo2_xxxx_0111_b)); //i=167, 2 96
assign combo3_1010_1010 = (~((~combo2_1010))); //i=170, 2 97*
assign combo3_1010_1100 = (~(combo2_1010_xxxx_b & combo2_xxxx_1100_b)); //i=172, 1 98
assign combo3_1010_1101 = (~(combo2_1010_xxxx_b & combo2_xxxx_1101_b)); //i=173, 1 99
assign combo3_1010_1110 = (~(combo2_1010_xxxx_b & combo2_xxxx_1110_b)); //i=174, 1 100
assign combo3_1011_0011 = (~(combo2_1011_xxxx_b & combo2_xxxx_0011_b)); //i=179, 1 101
assign combo3_1011_0110 = (~(combo2_1011_xxxx_b & combo2_xxxx_0110_b)); //i=182, 2 102
assign combo3_1011_0111 = (~(combo2_1011_xxxx_b & combo2_xxxx_0111_b)); //i=183, 1 103
assign combo3_1011_1000 = (~(combo2_1011_xxxx_b & combo2_xxxx_1000_b)); //i=184, 1 104
assign combo3_1011_1001 = (~(combo2_1011_xxxx_b & combo2_xxxx_1001_b)); //i=185, 1 105
assign combo3_1011_1010 = (~(combo2_1011_xxxx_b & combo2_xxxx_1010_b)); //i=186, 1 106
assign combo3_1011_1011 = (~((~combo2_1011))); //i=187, 2 107*
assign combo3_1011_1110 = (~(combo2_1011_xxxx_b & combo2_xxxx_1110_b)); //i=190, 2 108
assign combo3_1100_0000 = (~(combo2_1100_xxxx_b)); //i=192, 3 109
assign combo3_1100_0001 = (~(combo2_1100_xxxx_b & combo2_xxxx_0001_b)); //i=193, 1 110
assign combo3_1100_0011 = (~(combo2_1100_xxxx_b & combo2_xxxx_0011_b)); //i=195, 2 111
assign combo3_1100_0110 = (~(combo2_1100_xxxx_b & combo2_xxxx_0110_b)); //i=198, 1 112
assign combo3_1100_0111 = (~(combo2_1100_xxxx_b & combo2_xxxx_0111_b)); //i=199, 2 113
assign combo3_1100_1010 = (~(combo2_1100_xxxx_b & combo2_xxxx_1010_b)); //i=202, 2 114
assign combo3_1100_1100 = (~((~combo2_1100))); //i=204, 2 115*
assign combo3_1100_1110 = (~(combo2_1100_xxxx_b & combo2_xxxx_1110_b)); //i=206, 1 116
assign combo3_1101_0000 = (~(combo2_1101_xxxx_b)); //i=208, 1 117
assign combo3_1101_0011 = (~(combo2_1101_xxxx_b & combo2_xxxx_0011_b)); //i=211, 2 118
assign combo3_1101_0101 = (~(combo2_1101_xxxx_b & combo2_xxxx_0101_b)); //i=213, 3 119
assign combo3_1101_1000 = (~(combo2_1101_xxxx_b & combo2_xxxx_1000_b)); //i=216, 1 120
assign combo3_1101_1010 = (~(combo2_1101_xxxx_b & combo2_xxxx_1010_b)); //i=218, 2 121
assign combo3_1101_1011 = (~(combo2_1101_xxxx_b & combo2_xxxx_1011_b)); //i=219, 1 122
assign combo3_1101_1101 = (~((~combo2_1101))); //i=221, 1 123*
assign combo3_1110_0000 = (~(combo2_1110_xxxx_b)); //i=224, 1 124
assign combo3_1110_0001 = (~(combo2_1110_xxxx_b & combo2_xxxx_0001_b)); //i=225, 1 125
assign combo3_1110_0010 = (~(combo2_1110_xxxx_b & combo2_xxxx_0010_b)); //i=226, 1 126
assign combo3_1110_0011 = (~(combo2_1110_xxxx_b & combo2_xxxx_0011_b)); //i=227, 4 127
assign combo3_1110_0100 = (~(combo2_1110_xxxx_b & combo2_xxxx_0100_b)); //i=228, 1 128
assign combo3_1110_0101 = (~(combo2_1110_xxxx_b & combo2_xxxx_0101_b)); //i=229, 1 129
assign combo3_1110_0110 = (~(combo2_1110_xxxx_b & combo2_xxxx_0110_b)); //i=230, 2 130
assign combo3_1110_1010 = (~(combo2_1110_xxxx_b & combo2_xxxx_1010_b)); //i=234, 1 131
assign combo3_1110_1011 = (~(combo2_1110_xxxx_b & combo2_xxxx_1011_b)); //i=235, 1 132
assign combo3_1111_0000 = (~(f[4])); //i=240, 4 133
assign combo3_1111_0011 = (~(f[4] & combo2_xxxx_0011_b)); //i=243, 2 134
assign combo3_1111_0101 = (~(f[4] & combo2_xxxx_0101_b)); //i=245, 1 135
assign combo3_1111_1000 = (~(f[4] & combo2_xxxx_1000_b)); //i=248, 2 136
assign combo3_1111_1001 = (~(f[4] & combo2_xxxx_1001_b)); //i=249, 1 137
assign combo3_1111_1011 = (~(f[4] & combo2_xxxx_1011_b)); //i=251, 1 138
assign combo3_1111_1100 = (~(f[4] & combo2_xxxx_1100_b)); //i=252, 4 139
assign combo3_1111_1110 = (~(f[4] & combo2_xxxx_1110_b)); //i=254, 2 140
////#######################################
////## ESTIMATE VECTORs
////#######################################
assign e_00_b[0] = (~(dcd_000 & tiup));
assign e_00_b[1] = (~(dcd_001 & tiup));
assign e_00_b[2] = (~(dcd_010 & tiup));
assign e_00_b[3] = (~(dcd_011 & tiup));
assign e_00_b[4] = (~(dcd_100 & tiup));
assign e_00_b[5] = (~(dcd_101 & tiup));
assign e_00_b[6] = (~(dcd_110 & combo3_1100_0000));
assign e_00_b[7] = (~(dcd_111 & tidn));
assign e[0] = (~(e_00_b[0] & e_00_b[1] & e_00_b[2] & e_00_b[3] & e_00_b[4] & e_00_b[5] & e_00_b[6] & e_00_b[7]));
assign e_01_b[0] = (~(dcd_000 & tiup));
assign e_01_b[1] = (~(dcd_001 & tiup));
assign e_01_b[2] = (~(dcd_010 & combo3_1111_0000));
assign e_01_b[3] = (~(dcd_011 & tidn));
assign e_01_b[4] = (~(dcd_100 & tidn));
assign e_01_b[5] = (~(dcd_101 & tidn));
assign e_01_b[6] = (~(dcd_110 & combo3_0011_1111));
assign e_01_b[7] = (~(dcd_111 & tiup));
assign e[1] = (~(e_01_b[0] & e_01_b[1] & e_01_b[2] & e_01_b[3] & e_01_b[4] & e_01_b[5] & e_01_b[6] & e_01_b[7]));
assign e_02_b[0] = (~(dcd_000 & tiup));
assign e_02_b[1] = (~(dcd_001 & combo3_1000_0000));
assign e_02_b[2] = (~(dcd_010 & combo3_0000_1111));
assign e_02_b[3] = (~(dcd_011 & tiup));
assign e_02_b[4] = (~(dcd_100 & combo3_1000_0000));
assign e_02_b[5] = (~(dcd_101 & tidn));
assign e_02_b[6] = (~(dcd_110 & combo3_0011_1111));
assign e_02_b[7] = (~(dcd_111 & tiup));
assign e[2] = (~(e_02_b[0] & e_02_b[1] & e_02_b[2] & e_02_b[3] & e_02_b[4] & e_02_b[5] & e_02_b[6] & e_02_b[7]));
assign e_03_b[0] = (~(dcd_000 & combo3_1111_1000));
assign e_03_b[1] = (~(dcd_001 & combo3_0111_1100));
assign e_03_b[2] = (~(dcd_010 & combo3_0000_1111));
assign e_03_b[3] = (~(dcd_011 & combo3_1100_0000));
assign e_03_b[4] = (~(dcd_100 & combo3_0111_1111));
assign e_03_b[5] = (~(dcd_101 & combo3_1000_0000));
assign e_03_b[6] = (~(dcd_110 & combo3_0011_1111));
assign e_03_b[7] = (~(dcd_111 & combo3_1111_0000));
assign e[3] = (~(e_03_b[0] & e_03_b[1] & e_03_b[2] & e_03_b[3] & e_03_b[4] & e_03_b[5] & e_03_b[6] & e_03_b[7]));
assign e_04_b[0] = (~(dcd_000 & combo3_1110_0110));
assign e_04_b[1] = (~(dcd_001 & combo3_0111_0011));
assign e_04_b[2] = (~(dcd_010 & combo3_1000_1110));
assign e_04_b[3] = (~(dcd_011 & combo3_0011_1100));
assign e_04_b[4] = (~(dcd_100 & combo3_0111_1000));
assign e_04_b[5] = (~(dcd_101 & combo3_0111_1100));
assign e_04_b[6] = (~(dcd_110 & combo3_0011_1110));
assign e_04_b[7] = (~(dcd_111 & combo3_0000_1111));
assign e[4] = (~(e_04_b[0] & e_04_b[1] & e_04_b[2] & e_04_b[3] & e_04_b[4] & e_04_b[5] & e_04_b[6] & e_04_b[7]));
assign e_05_b[0] = (~(dcd_000 & combo3_1101_0101));
assign e_05_b[1] = (~(dcd_001 & combo3_0110_1011));
assign e_05_b[2] = (~(dcd_010 & combo3_0110_1101));
assign e_05_b[3] = (~(dcd_011 & combo3_1011_0011));
assign e_05_b[4] = (~(dcd_100 & combo3_0110_0110));
assign e_05_b[5] = (~(dcd_101 & combo3_0110_0011));
assign e_05_b[6] = (~(dcd_110 & combo3_0011_1001));
assign e_05_b[7] = (~(dcd_111 & combo3_1100_1110));
assign e[5] = (~(e_05_b[0] & e_05_b[1] & e_05_b[2] & e_05_b[3] & e_05_b[4] & e_05_b[5] & e_05_b[6] & e_05_b[7]));
assign e_06_b[0] = (~(dcd_000 & combo3_1000_0001));
assign e_06_b[1] = (~(dcd_001 & combo3_1100_0110));
assign e_06_b[2] = (~(dcd_010 & combo3_0100_1001));
assign e_06_b[3] = (~(dcd_011 & combo3_0110_1010));
assign e_06_b[4] = (~(dcd_100 & combo3_1101_0101));
assign e_06_b[5] = (~(dcd_101 & combo3_0101_1010));
assign e_06_b[6] = (~(dcd_110 & combo3_1010_0101));
assign e_06_b[7] = (~(dcd_111 & combo3_0010_1101));
assign e[6] = (~(e_06_b[0] & e_06_b[1] & e_06_b[2] & e_06_b[3] & e_06_b[4] & e_06_b[5] & e_06_b[6] & e_06_b[7]));
assign e_07_b[0] = (~(dcd_000 & combo3_1000_0110));
assign e_07_b[1] = (~(dcd_001 & combo3_0100_1010));
assign e_07_b[2] = (~(dcd_010 & combo3_1101_0011));
assign e_07_b[3] = (~(dcd_011 & combo3_0011_1000));
assign e_07_b[4] = (~(dcd_100 & combo3_0111_1111));
assign e_07_b[5] = (~(dcd_101 & combo3_1111_0000));
assign e_07_b[6] = (~(dcd_110 & combo3_1111_0011));
assign e_07_b[7] = (~(dcd_111 & combo3_1001_1001));
assign e[7] = (~(e_07_b[0] & e_07_b[1] & e_07_b[2] & e_07_b[3] & e_07_b[4] & e_07_b[5] & e_07_b[6] & e_07_b[7]));
assign e_08_b[0] = (~(dcd_000 & combo3_1000_1010));
assign e_08_b[1] = (~(dcd_001 & combo3_1001_1111));
assign e_08_b[2] = (~(dcd_010 & combo3_1001_1010));
assign e_08_b[3] = (~(dcd_011 & combo3_1010_0100));
assign e_08_b[4] = (~(dcd_100 & combo3_0111_1111));
assign e_08_b[5] = (~(dcd_101 & combo3_1111_0011));
assign e_08_b[6] = (~(dcd_110 & combo3_0011_0100));
assign e_08_b[7] = (~(dcd_111 & combo3_1010_1010));
assign e[8] = (~(e_08_b[0] & e_08_b[1] & e_08_b[2] & e_08_b[3] & e_08_b[4] & e_08_b[5] & e_08_b[6] & e_08_b[7]));
assign e_09_b[0] = (~(dcd_000 & combo3_1001_0000));
assign e_09_b[1] = (~(dcd_001 & combo3_0101_1111));
assign e_09_b[2] = (~(dcd_010 & combo3_1010_1100));
assign e_09_b[3] = (~(dcd_011 & combo3_0001_0010));
assign e_09_b[4] = (~(dcd_100 & combo3_0100_0000));
assign e_09_b[5] = (~(dcd_101 & combo3_0011_0101));
assign e_09_b[6] = (~(dcd_110 & combo3_0101_1001));
assign e_09_b[7] = (~(dcd_111 & tiup));
assign e[9] = (~(e_09_b[0] & e_09_b[1] & e_09_b[2] & e_09_b[3] & e_09_b[4] & e_09_b[5] & e_09_b[6] & e_09_b[7]));
assign e_10_b[0] = (~(dcd_000 & combo3_1011_1000));
assign e_10_b[1] = (~(dcd_001 & combo3_1111_0000));
assign e_10_b[2] = (~(dcd_010 & combo3_1000_1010));
assign e_10_b[3] = (~(dcd_011 & combo3_0110_0111));
assign e_10_b[4] = (~(dcd_100 & combo3_0011_0000));
assign e_10_b[5] = (~(dcd_101 & combo3_1101_0000));
assign e_10_b[6] = (~(dcd_110 & combo3_0001_0101));
assign e_10_b[7] = (~(dcd_111 & combo3_1000_0011));
assign e[10] = (~(e_10_b[0] & e_10_b[1] & e_10_b[2] & e_10_b[3] & e_10_b[4] & e_10_b[5] & e_10_b[6] & e_10_b[7]));
assign e_11_b[0] = (~(dcd_000 & combo3_1000_1101));
assign e_11_b[1] = (~(dcd_001 & combo3_1001_1001));
assign e_11_b[2] = (~(dcd_010 & combo3_0101_0001));
assign e_11_b[3] = (~(dcd_011 & combo3_1011_0111));
assign e_11_b[4] = (~(dcd_100 & combo3_0110_1001));
assign e_11_b[5] = (~(dcd_101 & combo3_0111_1000));
assign e_11_b[6] = (~(dcd_110 & combo3_0011_0001));
assign e_11_b[7] = (~(dcd_111 & combo3_0110_1101));
assign e[11] = (~(e_11_b[0] & e_11_b[1] & e_11_b[2] & e_11_b[3] & e_11_b[4] & e_11_b[5] & e_11_b[6] & e_11_b[7]));
assign e_12_b[0] = (~(dcd_000 & combo3_1010_0010));
assign e_12_b[1] = (~(dcd_001 & tidn));
assign e_12_b[2] = (~(dcd_010 & combo3_1110_0011));
assign e_12_b[3] = (~(dcd_011 & combo3_1111_0101));
assign e_12_b[4] = (~(dcd_100 & combo3_0110_0110));
assign e_12_b[5] = (~(dcd_101 & combo3_0000_1100));
assign e_12_b[6] = (~(dcd_110 & combo3_0110_1110));
assign e_12_b[7] = (~(dcd_111 & combo3_0101_0000));
assign e[12] = (~(e_12_b[0] & e_12_b[1] & e_12_b[2] & e_12_b[3] & e_12_b[4] & e_12_b[5] & e_12_b[6] & e_12_b[7]));
assign e_13_b[0] = (~(dcd_000 & combo3_1100_0111));
assign e_13_b[1] = (~(dcd_001 & combo3_0000_0100));
assign e_13_b[2] = (~(dcd_010 & combo3_1011_1001));
assign e_13_b[3] = (~(dcd_011 & combo3_1011_1010));
assign e_13_b[4] = (~(dcd_100 & combo3_1111_1110));
assign e_13_b[5] = (~(dcd_101 & combo3_0101_1110));
assign e_13_b[6] = (~(dcd_110 & combo3_1110_0011));
assign e_13_b[7] = (~(dcd_111 & combo3_1001_0100));
assign e[13] = (~(e_13_b[0] & e_13_b[1] & e_13_b[2] & e_13_b[3] & e_13_b[4] & e_13_b[5] & e_13_b[6] & e_13_b[7]));
assign e_14_b[0] = (~(dcd_000 & combo3_0111_1001));
assign e_14_b[1] = (~(dcd_001 & combo3_1111_1011));
assign e_14_b[2] = (~(dcd_010 & combo3_1010_0111));
assign e_14_b[3] = (~(dcd_011 & combo3_1000_0000));
assign e_14_b[4] = (~(dcd_100 & combo3_1110_0001));
assign e_14_b[5] = (~(dcd_101 & combo3_0110_1101));
assign e_14_b[6] = (~(dcd_110 & combo3_0000_0001));
assign e_14_b[7] = (~(dcd_111 & combo3_0001_0111));
assign e[14] = (~(e_14_b[0] & e_14_b[1] & e_14_b[2] & e_14_b[3] & e_14_b[4] & e_14_b[5] & e_14_b[6] & e_14_b[7]));
assign e_15_b[0] = (~(dcd_000 & combo3_0101_0101));
assign e_15_b[1] = (~(dcd_001 & combo3_1001_1010));
assign e_15_b[2] = (~(dcd_010 & combo3_0010_1001));
assign e_15_b[3] = (~(dcd_011 & combo3_0010_1001));
assign e_15_b[4] = (~(dcd_100 & combo3_1001_1101));
assign e_15_b[5] = (~(dcd_101 & combo3_1001_1110));
assign e_15_b[6] = (~(dcd_110 & combo3_1100_1010));
assign e_15_b[7] = (~(dcd_111 & combo3_1110_0100));
assign e[15] = (~(e_15_b[0] & e_15_b[1] & e_15_b[2] & e_15_b[3] & e_15_b[4] & e_15_b[5] & e_15_b[6] & e_15_b[7]));
assign e_16_b[0] = (~(dcd_000 & combo3_0111_1110));
assign e_16_b[1] = (~(dcd_001 & combo3_1100_1010));
assign e_16_b[2] = (~(dcd_010 & combo3_0010_0010));
assign e_16_b[3] = (~(dcd_011 & combo3_1111_1001));
assign e_16_b[4] = (~(dcd_100 & combo3_1101_1000));
assign e_16_b[5] = (~(dcd_101 & combo3_0111_0010));
assign e_16_b[6] = (~(dcd_110 & combo3_0100_1101));
assign e_16_b[7] = (~(dcd_111 & combo3_0011_1010));
assign e[16] = (~(e_16_b[0] & e_16_b[1] & e_16_b[2] & e_16_b[3] & e_16_b[4] & e_16_b[5] & e_16_b[6] & e_16_b[7]));
assign e_17_b[0] = (~(dcd_000 & combo3_0111_0010));
assign e_17_b[1] = (~(dcd_001 & combo3_1010_1110));
assign e_17_b[2] = (~(dcd_010 & combo3_1110_0010));
assign e_17_b[3] = (~(dcd_011 & combo3_0100_0110));
assign e_17_b[4] = (~(dcd_100 & combo3_1101_0011));
assign e_17_b[5] = (~(dcd_101 & combo3_1000_1111));
assign e_17_b[6] = (~(dcd_110 & combo3_0000_1101));
assign e_17_b[7] = (~(dcd_111 & combo3_1001_1100));
assign e[17] = (~(e_17_b[0] & e_17_b[1] & e_17_b[2] & e_17_b[3] & e_17_b[4] & e_17_b[5] & e_17_b[6] & e_17_b[7]));
assign e_18_b[0] = (~(dcd_000 & combo3_0001_0100));
assign e_18_b[1] = (~(dcd_001 & combo3_0011_1000));
assign e_18_b[2] = (~(dcd_010 & combo3_0101_0001));
assign e_18_b[3] = (~(dcd_011 & combo3_0001_0001));
assign e_18_b[4] = (~(dcd_100 & combo3_0010_0110));
assign e_18_b[5] = (~(dcd_101 & combo3_0011_0001));
assign e_18_b[6] = (~(dcd_110 & combo3_0111_0110));
assign e_18_b[7] = (~(dcd_111 & combo3_1001_1100));
assign e[18] = (~(e_18_b[0] & e_18_b[1] & e_18_b[2] & e_18_b[3] & e_18_b[4] & e_18_b[5] & e_18_b[6] & e_18_b[7]));
assign e_19_b[0] = (~(dcd_000 & tiup));
assign e_19_b[1] = (~(dcd_001 & tiup));
assign e_19_b[2] = (~(dcd_010 & tiup));
assign e_19_b[3] = (~(dcd_011 & tiup));
assign e_19_b[4] = (~(dcd_100 & tiup));
assign e_19_b[5] = (~(dcd_101 & tiup));
assign e_19_b[6] = (~(dcd_110 & tiup));
assign e_19_b[7] = (~(dcd_111 & tiup));
assign e[19] = (~(e_19_b[0] & e_19_b[1] & e_19_b[2] & e_19_b[3] & e_19_b[4] & e_19_b[5] & e_19_b[6] & e_19_b[7]));
////#######################################
////## RANGE VECTORs
////#######################################
assign r_00_b[0] = (~(dcd_000 & tidn));
assign r_00_b[1] = (~(dcd_001 & tidn));
assign r_00_b[2] = (~(dcd_010 & tidn));
assign r_00_b[3] = (~(dcd_011 & tidn));
assign r_00_b[4] = (~(dcd_100 & tidn));
assign r_00_b[5] = (~(dcd_101 & tidn));
assign r_00_b[6] = (~(dcd_110 & tidn));
assign r_00_b[7] = (~(dcd_111 & tidn));
assign r[0] = (~(r_00_b[0] & r_00_b[1] & r_00_b[2] & r_00_b[3] & r_00_b[4] & r_00_b[5] & r_00_b[6] & r_00_b[7]));
assign r_01_b[0] = (~(dcd_000 & tiup));
assign r_01_b[1] = (~(dcd_001 & tiup));
assign r_01_b[2] = (~(dcd_010 & tiup));
assign r_01_b[3] = (~(dcd_011 & tiup));
assign r_01_b[4] = (~(dcd_100 & combo3_1111_1100));
assign r_01_b[5] = (~(dcd_101 & tidn));
assign r_01_b[6] = (~(dcd_110 & tidn));
assign r_01_b[7] = (~(dcd_111 & tidn));
assign r[1] = (~(r_01_b[0] & r_01_b[1] & r_01_b[2] & r_01_b[3] & r_01_b[4] & r_01_b[5] & r_01_b[6] & r_01_b[7]));
assign r_02_b[0] = (~(dcd_000 & tiup));
assign r_02_b[1] = (~(dcd_001 & combo3_1111_1100));
assign r_02_b[2] = (~(dcd_010 & tidn));
assign r_02_b[3] = (~(dcd_011 & tidn));
assign r_02_b[4] = (~(dcd_100 & combo3_0000_0011));
assign r_02_b[5] = (~(dcd_101 & tiup));
assign r_02_b[6] = (~(dcd_110 & tiup));
assign r_02_b[7] = (~(dcd_111 & tiup));
assign r[2] = (~(r_02_b[0] & r_02_b[1] & r_02_b[2] & r_02_b[3] & r_02_b[4] & r_02_b[5] & r_02_b[6] & r_02_b[7]));
assign r_03_b[0] = (~(dcd_000 & combo3_1111_1100));
assign r_03_b[1] = (~(dcd_001 & combo3_0000_0011));
assign r_03_b[2] = (~(dcd_010 & tiup));
assign r_03_b[3] = (~(dcd_011 & tidn));
assign r_03_b[4] = (~(dcd_100 & combo3_0000_0011));
assign r_03_b[5] = (~(dcd_101 & tiup));
assign r_03_b[6] = (~(dcd_110 & tiup));
assign r_03_b[7] = (~(dcd_111 & combo3_1110_0000));
assign r[3] = (~(r_03_b[0] & r_03_b[1] & r_03_b[2] & r_03_b[3] & r_03_b[4] & r_03_b[5] & r_03_b[6] & r_03_b[7]));
assign r_04_b[0] = (~(dcd_000 & combo3_1110_0011));
assign r_04_b[1] = (~(dcd_001 & combo3_1100_0011));
assign r_04_b[2] = (~(dcd_010 & combo3_1100_0000));
assign r_04_b[3] = (~(dcd_011 & combo3_1111_1100));
assign r_04_b[4] = (~(dcd_100 & combo3_0000_0011));
assign r_04_b[5] = (~(dcd_101 & combo3_1111_1110));
assign r_04_b[6] = (~(dcd_110 & tidn));
assign r_04_b[7] = (~(dcd_111 & combo3_0001_1111));
assign r[4] = (~(r_04_b[0] & r_04_b[1] & r_04_b[2] & r_04_b[3] & r_04_b[4] & r_04_b[5] & r_04_b[6] & r_04_b[7]));
assign r_05_b[0] = (~(dcd_000 & combo3_1001_0011));
assign r_05_b[1] = (~(dcd_001 & combo3_0010_0011));
assign r_05_b[2] = (~(dcd_010 & combo3_0011_1000));
assign r_05_b[3] = (~(dcd_011 & combo3_1110_0011));
assign r_05_b[4] = (~(dcd_100 & combo3_1100_0011));
assign r_05_b[5] = (~(dcd_101 & combo3_1100_0001));
assign r_05_b[6] = (~(dcd_110 & combo3_1111_1000));
assign r_05_b[7] = (~(dcd_111 & combo3_0001_1111));
assign r[5] = (~(r_05_b[0] & r_05_b[1] & r_05_b[2] & r_05_b[3] & r_05_b[4] & r_05_b[5] & r_05_b[6] & r_05_b[7]));
assign r_06_b[0] = (~(dcd_000 & combo3_1101_1010));
assign r_06_b[1] = (~(dcd_001 & combo3_1001_0010));
assign r_06_b[2] = (~(dcd_010 & combo3_1010_0100));
assign r_06_b[3] = (~(dcd_011 & combo3_1001_0011));
assign r_06_b[4] = (~(dcd_100 & combo3_0011_0011));
assign r_06_b[5] = (~(dcd_101 & combo3_0011_0001));
assign r_06_b[6] = (~(dcd_110 & combo3_1100_0111));
assign r_06_b[7] = (~(dcd_111 & combo3_0001_1110));
assign r[6] = (~(r_06_b[0] & r_06_b[1] & r_06_b[2] & r_06_b[3] & r_06_b[4] & r_06_b[5] & r_06_b[6] & r_06_b[7]));
assign r_07_b[0] = (~(dcd_000 & combo3_0100_1100));
assign r_07_b[1] = (~(dcd_001 & combo3_0011_1000));
assign r_07_b[2] = (~(dcd_010 & combo3_0111_0010));
assign r_07_b[3] = (~(dcd_011 & combo3_0100_1010));
assign r_07_b[4] = (~(dcd_100 & combo3_1010_1010));
assign r_07_b[5] = (~(dcd_101 & combo3_1010_1101));
assign r_07_b[6] = (~(dcd_110 & combo3_0010_0100));
assign r_07_b[7] = (~(dcd_111 & combo3_1001_1001));
assign r[7] = (~(r_07_b[0] & r_07_b[1] & r_07_b[2] & r_07_b[3] & r_07_b[4] & r_07_b[5] & r_07_b[6] & r_07_b[7]));
assign r_08_b[0] = (~(dcd_000 & combo3_1110_1010));
assign r_08_b[1] = (~(dcd_001 & combo3_0011_1000));
assign r_08_b[2] = (~(dcd_010 & combo3_1001_0100));
assign r_08_b[3] = (~(dcd_011 & combo3_1001_1000));
assign r_08_b[4] = (~(dcd_100 & tidn));
assign r_08_b[5] = (~(dcd_101 & combo3_0011_1001));
assign r_08_b[6] = (~(dcd_110 & combo3_1001_0010));
assign r_08_b[7] = (~(dcd_111 & combo3_1101_0101));
assign r[8] = (~(r_08_b[0] & r_08_b[1] & r_08_b[2] & r_08_b[3] & r_08_b[4] & r_08_b[5] & r_08_b[6] & r_08_b[7]));
assign r_09_b[0] = (~(dcd_000 & combo3_0010_0001));
assign r_09_b[1] = (~(dcd_001 & combo3_0011_1001));
assign r_09_b[2] = (~(dcd_010 & combo3_0011_1110));
assign r_09_b[3] = (~(dcd_011 & combo3_0101_0110));
assign r_09_b[4] = (~(dcd_100 & tidn));
assign r_09_b[5] = (~(dcd_101 & combo3_1101_1010));
assign r_09_b[6] = (~(dcd_110 & combo3_1011_0110));
assign r_09_b[7] = (~(dcd_111 & combo3_0111_0000));
assign r[9] = (~(r_09_b[0] & r_09_b[1] & r_09_b[2] & r_09_b[3] & r_09_b[4] & r_09_b[5] & r_09_b[6] & r_09_b[7]));
assign r_10_b[0] = (~(dcd_000 & combo3_0101_0011));
assign r_10_b[1] = (~(dcd_001 & combo3_1011_1011));
assign r_10_b[2] = (~(dcd_010 & combo3_1011_0110));
assign r_10_b[3] = (~(dcd_011 & combo3_1101_1101));
assign r_10_b[4] = (~(dcd_100 & combo3_1000_0011));
assign r_10_b[5] = (~(dcd_101 & combo3_0110_1111));
assign r_10_b[6] = (~(dcd_110 & combo3_1110_0101));
assign r_10_b[7] = (~(dcd_111 & combo3_0100_1000));
assign r[10] = (~(r_10_b[0] & r_10_b[1] & r_10_b[2] & r_10_b[3] & r_10_b[4] & r_10_b[5] & r_10_b[6] & r_10_b[7]));
assign r_11_b[0] = (~(dcd_000 & combo3_0010_1110));
assign r_11_b[1] = (~(dcd_001 & combo3_0000_1011));
assign r_11_b[2] = (~(dcd_010 & combo3_1110_1011));
assign r_11_b[3] = (~(dcd_011 & combo3_1010_0111));
assign r_11_b[4] = (~(dcd_100 & combo3_0100_0101));
assign r_11_b[5] = (~(dcd_101 & combo3_1100_1100));
assign r_11_b[6] = (~(dcd_110 & combo3_0110_1100));
assign r_11_b[7] = (~(dcd_111 & combo3_0010_0110));
assign r[11] = (~(r_11_b[0] & r_11_b[1] & r_11_b[2] & r_11_b[3] & r_11_b[4] & r_11_b[5] & r_11_b[6] & r_11_b[7]));
assign r_12_b[0] = (~(dcd_000 & combo3_0011_1100));
assign r_12_b[1] = (~(dcd_001 & combo3_1010_0110));
assign r_12_b[2] = (~(dcd_010 & combo3_1000_1000));
assign r_12_b[3] = (~(dcd_011 & combo3_0010_1101));
assign r_12_b[4] = (~(dcd_100 & combo3_0011_1001));
assign r_12_b[5] = (~(dcd_101 & combo3_1101_1011));
assign r_12_b[6] = (~(dcd_110 & combo3_1011_1011));
assign r_12_b[7] = (~(dcd_111 & combo3_1100_1100));
assign r[12] = (~(r_12_b[0] & r_12_b[1] & r_12_b[2] & r_12_b[3] & r_12_b[4] & r_12_b[5] & r_12_b[6] & r_12_b[7]));
assign r_13_b[0] = (~(dcd_000 & combo3_1001_0111));
assign r_13_b[1] = (~(dcd_001 & combo3_0001_0101));
assign r_13_b[2] = (~(dcd_010 & combo3_1011_1110));
assign r_13_b[3] = (~(dcd_011 & combo3_1110_0110));
assign r_13_b[4] = (~(dcd_100 & combo3_0000_1111));
assign r_13_b[5] = (~(dcd_101 & combo3_0001_1000));
assign r_13_b[6] = (~(dcd_110 & combo3_1011_1110));
assign r_13_b[7] = (~(dcd_111 & combo3_0110_1101));
assign r[13] = (~(r_13_b[0] & r_13_b[1] & r_13_b[2] & r_13_b[3] & r_13_b[4] & r_13_b[5] & r_13_b[6] & r_13_b[7]));
assign r_14_b[0] = (~(dcd_000 & tidn));
assign r_14_b[1] = (~(dcd_001 & tidn));
assign r_14_b[2] = (~(dcd_010 & tidn));
assign r_14_b[3] = (~(dcd_011 & tidn));
assign r_14_b[4] = (~(dcd_100 & tidn));
assign r_14_b[5] = (~(dcd_101 & tidn));
assign r_14_b[6] = (~(dcd_110 & tidn));
assign r_14_b[7] = (~(dcd_111 & tidn));
assign r[14] = (~(r_14_b[0] & r_14_b[1] & r_14_b[2] & r_14_b[3] & r_14_b[4] & r_14_b[5] & r_14_b[6] & r_14_b[7]));
////#######################################
////## RENUMBERING OUTPUTS
////#######################################
assign est[1:20] = e[0:19]; // renumbering
assign rng[6:20] = r[0:14]; // renumbering
endmodule |
module xu_alu_add
(
//-------------------------------------------------------------------
// Clocks & Power
//-------------------------------------------------------------------
input [0:`NCLK_WIDTH-1] nclk,
inout vdd,
inout gnd,
//-------------------------------------------------------------------
// Pervasive
//-------------------------------------------------------------------
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input sg_0,
input scan_in,
output scan_out,
//-------------------------------------------------------------------
// Decode Interface
//-------------------------------------------------------------------
input ex1_act,
input ex2_msb_64b_sel,
input [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv,
input dec_alu_ex2_add_ci,
//-------------------------------------------------------------------
// Bypass Interface
//-------------------------------------------------------------------
input [64-`GPR_WIDTH:63] ex2_rs1,
input [64-`GPR_WIDTH:63] ex2_rs2,
//-------------------------------------------------------------------
// Target Data
//-------------------------------------------------------------------
(* NO_MODIFICATION="TRUE" *) // ex2_add_rt
// NET_DATA="PLANES=/C1 C2/" // ex2_add_rt
output [64-`GPR_WIDTH:63] ex2_add_rt, // Add result
(* NO_MODIFICATION="TRUE" *) // ex2_add_ovf
output ex2_add_ovf, // Add overflow
// Add carry
output ex2_add_ca
);
localparam msb = 64-`GPR_WIDTH;
// Latches
wire [64-`GPR_WIDTH:63] ex2_rs1_inv_b_q; //input=>ex1_rs1_inv, act=>ex1_act
wire [64-`GPR_WIDTH:63] ex1_rs1_inv;
// Scanchain
localparam ex2_rs1_inv_b_offset = 0;
localparam scan_right = ex2_rs1_inv_b_offset + `GPR_WIDTH;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
// Signals
wire [0:`NCLK_WIDTH-1] ex1_rs0_inv_lclk;
wire ex1_rs0_inv_d1clk;
wire ex1_rs0_inv_d2clk;
wire [64-`GPR_WIDTH:63] ex2_rs1_b;
wire [64-`GPR_WIDTH:63] ex2_rs2_b;
wire [64-`GPR_WIDTH:63] ex2_x_b;
wire [64-`GPR_WIDTH:63] ex2_y;
wire [64-`GPR_WIDTH:63] ex2_y_b;
wire ex2_aop_00;
wire ex2_aop_32;
wire ex2_bop_00;
wire ex2_bop_32;
// synopsys translate_off
(* NO_MODIFICATION="TRUE" *) // ex2_sgn00_32
// synopsys translate_on
wire ex2_sgn00_32;
wire ex2_sgn11_32;
// synopsys translate_off
(* NO_MODIFICATION="TRUE" *) // ex2_sgn00_64
// synopsys translate_on
wire ex2_sgn00_64;
wire ex2_sgn11_64;
wire ex2_cout_32;
wire ex2_cout_00;
// synopsys translate_off
(* NO_MODIFICATION="TRUE" *) // ex2_ovf32_00_b
// synopsys translate_on
wire ex2_ovf32_00_b;
wire ex2_ovf32_11_b;
// synopsys translate_off
(* NO_MODIFICATION="TRUE" *) // ex2_ovf64_00_b
// synopsys translate_on
wire ex2_ovf64_00_b;
wire ex2_ovf64_11_b;
wire [64-`GPR_WIDTH:63] ex2_add_rslt;
wire [64-`GPR_WIDTH:63] ex2_rs1_inv_q;
generate
genvar i;
for (i=0; i<`GPR_WIDTH; i=i+1) begin : ex1_rs1_inv_gen
assign ex1_rs1_inv[i] = dec_alu_ex1_add_rs1_inv[i % (`GPR_WIDTH/8)];
end
endgenerate
// synopsys translate_off
// synopsys translate_on
assign ex2_rs1_inv_q = (~ex2_rs1_inv_b_q);
assign ex2_rs1_b = (~ex2_rs1);
assign ex2_rs2_b = (~ex2_rs2);
// synopsys translate_off
// synopsys translate_on
assign ex2_x_b = ex2_rs1_b ^ ex2_rs1_inv_q; // xor2_x2m --w=12
// synopsys translate_off
// synopsys translate_on
assign ex2_y = (~ex2_rs2_b); // inv_x1m --w=4
// synopsys translate_off
// synopsys translate_on
assign ex2_y_b = (~ex2_y); // inv_x2m --w=4
// synopsys translate_off
// synopsys translate_on
assign ex2_aop_00 = (~ex2_x_b[msb]);
// synopsys translate_off
// synopsys translate_on
assign ex2_aop_32 = (~ex2_x_b[32]);
// synopsys translate_off
// synopsys translate_on
assign ex2_bop_00 = (~ex2_y_b[msb]);
// synopsys translate_off
// synopsys translate_on
assign ex2_bop_32 = (~ex2_y_b[32]);
tri_st_add csa(
.x_b(ex2_x_b),
.y_b(ex2_y_b),
.ci(dec_alu_ex2_add_ci),
.sum(ex2_add_rslt),
.cout_32(ex2_cout_32),
.cout_0(ex2_cout_00)
);
assign ex2_add_rt = ex2_add_rslt;
// Overflow occurs when the sign bit of the inputs differs from the sign of the result
assign ex2_sgn00_32 = (~ex2_msb_64b_sel) & (~ex2_aop_32) & (~ex2_bop_32);
assign ex2_sgn11_32 = (~ex2_msb_64b_sel) & ex2_aop_32 & ex2_bop_32;
assign ex2_sgn00_64 = ex2_msb_64b_sel & (~ex2_aop_00) & (~ex2_bop_00);
assign ex2_sgn11_64 = ex2_msb_64b_sel & ex2_aop_00 & ex2_bop_00;
assign ex2_ovf32_00_b = (~(ex2_add_rslt[32] & ex2_sgn00_32));
assign ex2_ovf32_11_b = (~((~ex2_add_rslt[32]) & ex2_sgn11_32));
assign ex2_ovf64_00_b = (~(ex2_add_rslt[msb] & ex2_sgn00_64));
assign ex2_ovf64_11_b = (~((~ex2_add_rslt[msb]) & ex2_sgn11_64));
assign ex2_add_ovf = (~(ex2_ovf64_00_b & ex2_ovf64_11_b & ex2_ovf32_00_b & ex2_ovf32_11_b));
//-------------------------------------------------------------------
// Latch instances
//-------------------------------------------------------------------
assign ex2_add_ca = (ex2_msb_64b_sel == 1'b1) ? ex2_cout_00 : ex2_cout_32;
tri_lcbnd ex1_rs0_inv_lcb(
.vd(vdd),
.gd(gnd),
.act(ex1_act),
.nclk(nclk),
.force_t(func_sl_force),
.thold_b(func_sl_thold_0_b),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.sg(sg_0),
.lclk(ex1_rs0_inv_lclk),
.d1clk(ex1_rs0_inv_d1clk),
.d2clk(ex1_rs0_inv_d2clk)
);
tri_inv_nlats #(.WIDTH(`GPR_WIDTH), .BTR("NLI0001_X1_A12TH"), .INIT(0)) ex1_rs0_inv_b_latch(
.vd(vdd),
.gd(gnd),
.lclk(ex1_rs0_inv_lclk),
.d1clk(ex1_rs0_inv_d1clk),
.d2clk(ex1_rs0_inv_d2clk),
.scanin(siv[ex2_rs1_inv_b_offset:ex2_rs1_inv_b_offset + `GPR_WIDTH - 1]),
.scanout(sov[ex2_rs1_inv_b_offset:ex2_rs1_inv_b_offset + `GPR_WIDTH - 1]),
.d(ex1_rs1_inv),
.qb(ex2_rs1_inv_b_q)
);
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
endmodule |
module fu_cr2(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
f_cr2_si,
f_cr2_so,
ex1_act,
ex2_act,
ex1_thread_b,
f_dcd_ex7_cancel,
f_fmt_ex2_bop_byt,
f_dcd_ex1_fpscr_bit_data_b,
f_dcd_ex1_fpscr_bit_mask_b,
f_dcd_ex1_fpscr_nib_mask_b,
f_dcd_ex1_mtfsbx_b,
f_dcd_ex1_mcrfs_b,
f_dcd_ex1_mtfsf_b,
f_dcd_ex1_mtfsfi_b,
f_cr2_ex4_thread_b,
f_cr2_ex4_fpscr_bit_data_b,
f_cr2_ex4_fpscr_bit_mask_b,
f_cr2_ex4_fpscr_nib_mask_b,
f_cr2_ex4_mtfsbx_b,
f_cr2_ex4_mcrfs_b,
f_cr2_ex4_mtfsf_b,
f_cr2_ex4_mtfsfi_b,
f_cr2_ex6_fpscr_rd_dat,
f_cr2_ex7_fpscr_rd_dat,
f_cr2_ex2_fpscr_shadow
);
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input [1:7] delay_lclkr; // tidn,
input [1:7] mpw1_b; // tidn,
input [0:1] mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input f_cr2_si; // perv
output f_cr2_so; // perv
input ex1_act; // act writes
input ex2_act; // act writes
input [0:3] ex1_thread_b; // thread write
input f_dcd_ex7_cancel;
input [45:52] f_fmt_ex2_bop_byt; //for mtfsf to shadow reg
input [0:3] f_dcd_ex1_fpscr_bit_data_b; //data to write to nibble (other than mtfsf)
input [0:3] f_dcd_ex1_fpscr_bit_mask_b; //enable update of bit within the nibble
input [0:8] f_dcd_ex1_fpscr_nib_mask_b; //enable update of this nibble
input f_dcd_ex1_mtfsbx_b; //fpscr set bit, reset bit
input f_dcd_ex1_mcrfs_b; //move fpscr field to cr and reset exceptions
input f_dcd_ex1_mtfsf_b; //move fpr data to fpscr
input f_dcd_ex1_mtfsfi_b; //move immediate data to fpscr
output [0:3] f_cr2_ex4_thread_b; //scr
output [0:3] f_cr2_ex4_fpscr_bit_data_b; //data to write to nibble (other than mtfsf)
output [0:3] f_cr2_ex4_fpscr_bit_mask_b; //enable update of bit within the nibble
output [0:8] f_cr2_ex4_fpscr_nib_mask_b; //enable update of this nibble
output f_cr2_ex4_mtfsbx_b; //fpscr set bit, reset bit
output f_cr2_ex4_mcrfs_b; //move fpscr field to cr and reset exceptions
output f_cr2_ex4_mtfsf_b; //move fpr data to fpscr
output f_cr2_ex4_mtfsfi_b; //move immediate data to fpscr
output [24:31] f_cr2_ex6_fpscr_rd_dat; //scr
output [24:31] f_cr2_ex7_fpscr_rd_dat; //scr
output [0:7] f_cr2_ex2_fpscr_shadow; //fpic
// end ports
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire sg_0;
wire thold_0_b;
wire thold_0;
wire force_t;
wire ex7_th0_act;
wire ex7_th1_act;
wire ex7_th2_act;
wire ex7_th3_act;
wire ex3_act;
wire ex4_act;
wire ex5_act;
wire ex6_act;
wire ex7_act;
wire ex5_mv_to_op;
wire ex6_mv_to_op;
wire ex7_mv_to_op;
wire [0:3] ex2_thread;
wire [0:3] ex3_thread;
wire [0:3] ex4_thread;
wire [0:3] ex5_thread;
wire [0:3] ex6_thread;
wire [0:3] ex7_thread;
(* analysis_not_referenced="TRUE" *)
wire [0:2] act_spare_unused;
//-----------------
wire [0:6] act_so; //SCAN
wire [0:6] act_si;
wire [0:33] ex2_ctl_so; //SCAN
wire [0:33] ex2_ctl_si;
wire [0:24] ex3_ctl_so; //SCAN
wire [0:24] ex3_ctl_si;
wire [0:24] ex4_ctl_so; //SCAN
wire [0:24] ex4_ctl_si;
wire [0:4] ex5_ctl_so; //SCAN
wire [0:4] ex5_ctl_si;
wire [0:4] ex6_ctl_so; //SCAN
wire [0:4] ex6_ctl_si;
wire [0:4] ex7_ctl_so; //SCAN
wire [0:4] ex7_ctl_si;
wire [0:7] shadow0_so; //SCAN
wire [0:7] shadow0_si;
wire [0:7] shadow1_so; //SCAN
wire [0:7] shadow1_si;
wire [0:7] shadow2_so; //SCAN
wire [0:7] shadow2_si;
wire [0:7] shadow3_so; //SCAN
wire [0:7] shadow3_si;
wire [0:7] shadow_byp2_so; //SCAN
wire [0:7] shadow_byp2_si;
wire [0:7] shadow_byp3_so; //SCAN
wire [0:7] shadow_byp3_si;
wire [0:7] shadow_byp4_so; //SCAN
wire [0:7] shadow_byp4_si;
wire [0:7] shadow_byp5_so; //SCAN
wire [0:7] shadow_byp5_si;
wire [0:7] shadow_byp6_so; //SCAN
wire [0:7] shadow_byp6_si;
//-----------------
wire [0:7] shadow0;
wire [0:7] shadow1;
wire [0:7] shadow2;
wire [0:7] shadow3;
wire [0:7] shadow_byp2;
wire [0:7] shadow_byp3;
wire [0:7] shadow_byp4;
wire [0:7] shadow_byp5;
wire [0:7] shadow_byp6;
wire [0:7] shadow_byp2_din;
wire [0:7] ex2_bit_sel;
wire [0:3] ex2_fpscr_bit_data;
wire [0:3] ex2_fpscr_bit_mask;
wire [0:8] ex2_fpscr_nib_mask;
wire ex2_mtfsbx;
wire ex2_mcrfs;
wire ex2_mtfsf;
wire ex2_mtfsfi;
wire [0:3] ex3_fpscr_bit_data;
wire [0:3] ex3_fpscr_bit_mask;
wire [0:8] ex3_fpscr_nib_mask;
wire ex3_mtfsbx;
wire ex3_mcrfs;
wire ex3_mtfsf;
wire ex3_mtfsfi;
wire [0:3] ex4_fpscr_bit_data;
wire [0:3] ex4_fpscr_bit_mask;
wire [0:8] ex4_fpscr_nib_mask;
wire ex4_mtfsbx;
wire ex4_mcrfs;
wire ex4_mtfsf;
wire ex4_mtfsfi;
wire ex2_mv_to_op;
wire ex3_mv_to_op;
wire ex4_mv_to_op;
wire [0:7] ex2_fpscr_data;
wire [0:3] ex1_thread;
wire ex1_rd_sel_0;
wire ex2_rd_sel_0;
wire ex1_rd_sel_1;
wire ex2_rd_sel_1;
wire ex1_rd_sel_2;
wire ex2_rd_sel_2;
wire ex1_rd_sel_3;
wire ex2_rd_sel_3;
wire ex1_rd_sel_byp2;
wire ex2_rd_sel_byp2;
wire ex1_rd_sel_byp3;
wire ex2_rd_sel_byp3;
wire ex1_rd_sel_byp4;
wire ex2_rd_sel_byp4;
wire ex1_rd_sel_byp5;
wire ex2_rd_sel_byp5;
wire ex1_rd_sel_byp6;
wire ex2_rd_sel_byp6;
wire ex1_rd_sel_byp2_pri;
wire ex1_rd_sel_byp3_pri;
wire ex1_rd_sel_byp4_pri;
wire ex1_rd_sel_byp5_pri;
wire ex1_rd_sel_byp6_pri;
wire [0:7] ex2_fpscr_shadow_mux;
wire ex1_thread_match_1;
wire ex1_thread_match_2;
wire ex1_thread_match_3;
wire ex1_thread_match_4;
wire ex1_thread_match_5;
wire [0:3] ex1_fpscr_bit_data;
wire [0:3] ex1_fpscr_bit_mask;
wire [0:8] ex1_fpscr_nib_mask;
wire ex1_mtfsbx;
wire ex1_mcrfs;
wire ex1_mtfsf;
wire ex1_mtfsfi;
wire ex7_cancel;
wire [24:31] ex7_fpscr_rd_dat_no_byp;
////############################################
////# pervasive
////############################################
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
////############################################
////# ACT LATCHES
////############################################
tri_rlmreg_p #(.WIDTH(7), .NEEDS_SRESET(0)) act_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[6]), // tidn,
.mpw1_b(mpw1_b[6]), // tidn,
.mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable),
.scout(act_so),
.scin(act_si),
//---------------
.din({ act_spare_unused[0],
act_spare_unused[1],
ex2_act,
ex3_act,
ex4_act,
ex5_act,
ex6_act}),
//-----------------
.dout({ act_spare_unused[0],
act_spare_unused[1],
ex3_act,
ex4_act,
ex5_act,
ex6_act,
ex7_act})
);
assign act_spare_unused[2] = ex1_act; // take this out?
////#############################################
////## ex2 latches
////#############################################
assign ex1_thread[0:3] = (~ex1_thread_b[0:3]);
assign ex1_fpscr_bit_data[0:3] = (~f_dcd_ex1_fpscr_bit_data_b[0:3]);
assign ex1_fpscr_bit_mask[0:3] = (~f_dcd_ex1_fpscr_bit_mask_b[0:3]);
assign ex1_fpscr_nib_mask[0:8] = (~f_dcd_ex1_fpscr_nib_mask_b[0:8]);
assign ex1_mtfsbx = (~f_dcd_ex1_mtfsbx_b);
assign ex1_mcrfs = (~f_dcd_ex1_mcrfs_b);
assign ex1_mtfsf = (~f_dcd_ex1_mtfsf_b);
assign ex1_mtfsfi = (~f_dcd_ex1_mtfsfi_b);
tri_rlmreg_p #(.WIDTH(34)) ex2_ctl_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[1]), // tidn,
.mpw1_b(mpw1_b[1]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable), //ex1_act
.scout(ex2_ctl_so),
.scin(ex2_ctl_si),
//-----------------
.din({ ex1_thread[0:3],
ex1_fpscr_bit_data[0:3],
ex1_fpscr_bit_mask[0:3],
ex1_fpscr_nib_mask[0:8],
ex1_mtfsbx,
ex1_mcrfs,
ex1_mtfsf,
ex1_mtfsfi,
ex1_rd_sel_0,
ex1_rd_sel_1,
ex1_rd_sel_2,
ex1_rd_sel_3,
ex1_rd_sel_byp2_pri,
ex1_rd_sel_byp3_pri,
ex1_rd_sel_byp4_pri,
ex1_rd_sel_byp5_pri,
ex1_rd_sel_byp6_pri}),
//-----------------
.dout({ ex2_thread[0:3],
ex2_fpscr_bit_data[0:3],
ex2_fpscr_bit_mask[0:3],
ex2_fpscr_nib_mask[0:8],
ex2_mtfsbx,
ex2_mcrfs,
ex2_mtfsf,
ex2_mtfsfi,
ex2_rd_sel_0,
ex2_rd_sel_1,
ex2_rd_sel_2,
ex2_rd_sel_3,
ex2_rd_sel_byp2,
ex2_rd_sel_byp3,
ex2_rd_sel_byp4,
ex2_rd_sel_byp5,
ex2_rd_sel_byp6})
);
////#############################################
////## ex3 latches
////#############################################
tri_rlmreg_p #(.WIDTH(25)) ex3_ctl_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[2]), // tidn,
.mpw1_b(mpw1_b[2]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable),//ex2_act
.scout(ex3_ctl_so),
.scin(ex3_ctl_si),
//-----------------
.din({ ex2_thread[0:3],
ex2_fpscr_bit_data[0:3],
ex2_fpscr_bit_mask[0:3],
ex2_fpscr_nib_mask[0:8],
ex2_mtfsbx,
ex2_mcrfs,
ex2_mtfsf,
ex2_mtfsfi}),
//-----------------
.dout({ ex3_thread[0:3],
ex3_fpscr_bit_data[0:3],
ex3_fpscr_bit_mask[0:3],
ex3_fpscr_nib_mask[0:8],
ex3_mtfsbx,
ex3_mcrfs,
ex3_mtfsf,
ex3_mtfsfi})
);
////#############################################
////## ex4 latches
////#############################################
tri_rlmreg_p #(.WIDTH(25)) ex4_ctl_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[3]), // tidn,
.mpw1_b(mpw1_b[3]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable),//ex3_act
.scout(ex4_ctl_so),
.scin(ex4_ctl_si),
//-----------------
.din({ ex3_thread[0:3],
ex3_fpscr_bit_data[0:3],
ex3_fpscr_bit_mask[0:3],
ex3_fpscr_nib_mask[0:8],
ex3_mtfsbx,
ex3_mcrfs,
ex3_mtfsf,
ex3_mtfsfi}),
//-----------------
.dout({ ex4_thread[0:3],
ex4_fpscr_bit_data[0:3],
ex4_fpscr_bit_mask[0:3],
ex4_fpscr_nib_mask[0:8],
ex4_mtfsbx,
ex4_mcrfs,
ex4_mtfsf,
ex4_mtfsfi})
);
assign f_cr2_ex4_thread_b[0:3] = (~ex4_thread[0:3]); //output--
assign f_cr2_ex4_fpscr_bit_data_b[0:3] = (~ex4_fpscr_bit_data[0:3]); //output--
assign f_cr2_ex4_fpscr_bit_mask_b[0:3] = (~ex4_fpscr_bit_mask[0:3]); //output--
assign f_cr2_ex4_fpscr_nib_mask_b[0:8] = (~ex4_fpscr_nib_mask[0:8]); //output--
assign f_cr2_ex4_mtfsbx_b = (~ex4_mtfsbx); //output--
assign f_cr2_ex4_mcrfs_b = (~ex4_mcrfs); //output--
assign f_cr2_ex4_mtfsf_b = (~ex4_mtfsf); //output--
assign f_cr2_ex4_mtfsfi_b = (~ex4_mtfsfi); //output--
tri_rlmreg_p #(.WIDTH(5)) ex5_ctl_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[4]), // tidn,
.mpw1_b(mpw1_b[4]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable),//ex4_act
.scout(ex5_ctl_so),
.scin(ex5_ctl_si),
//-----------------
.din({ ex4_thread[0:3],
ex4_mv_to_op}),
//-----------------
.dout({ ex5_thread[0:3],
ex5_mv_to_op})
);
tri_rlmreg_p #(.WIDTH(5)) ex6_ctl_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[5]), // tidn,
.mpw1_b(mpw1_b[5]), // tidn,
.mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable),//ex5_act
.scout(ex6_ctl_so),
.scin(ex6_ctl_si),
//-----------------
.din({ ex5_thread[0:3],
ex5_mv_to_op}),
//-----------------
.dout({ ex6_thread[0:3],
ex6_mv_to_op})
);
tri_rlmreg_p #(.WIDTH(5)) ex7_ctl_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[6]), // tidn,
.mpw1_b(mpw1_b[6]), // tidn,
.mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable),//ex6_act
.scout(ex7_ctl_so),
.scin(ex7_ctl_si),
//-----------------
.din({ ex6_thread[0:3],
ex6_mv_to_op}),
.dout({ ex7_thread[0:3],
ex7_mv_to_op})
);
assign ex7_cancel = f_dcd_ex7_cancel;
////##############################################
////# read mux for mffs instruction
////##############################################
assign f_cr2_ex6_fpscr_rd_dat[24:31] = ({8{ex6_thread[0]}} & shadow0[0:7]) |
({8{ex6_thread[1]}} & shadow1[0:7]) |
({8{ex6_thread[2]}} & shadow2[0:7]) |
({8{ex6_thread[3]}} & shadow3[0:7]); // output to rounder
assign ex7_fpscr_rd_dat_no_byp[24:31] = ({8{ex7_thread[0]}} & shadow0[0:7]) |
({8{ex7_thread[1]}} & shadow1[0:7]) |
({8{ex7_thread[2]}} & shadow2[0:7]) |
({8{ex7_thread[3]}} & shadow3[0:7]);
assign f_cr2_ex7_fpscr_rd_dat[24:31] = ({8{ex7_mv_to_op}} & shadow_byp6[0:7]) |
({8{(~ex7_mv_to_op)}} & ex7_fpscr_rd_dat_no_byp[24:31]);
////##############################################
////# fpscr write data / merge
////##############################################
assign ex2_bit_sel[0:3] = ex2_fpscr_bit_mask[0:3] & {4{ex2_mv_to_op & ex2_fpscr_nib_mask[6]}};
assign ex2_bit_sel[4:7] = ex2_fpscr_bit_mask[0:3] & {4{ex2_mv_to_op & ex2_fpscr_nib_mask[7]}};
assign ex2_fpscr_data[0:3] = (f_fmt_ex2_bop_byt[45:48] & {4{ex2_mtfsf}}) |
(ex2_fpscr_bit_data[0:3] & {4{(~ex2_mtfsf)}});
assign ex2_fpscr_data[4:7] = (f_fmt_ex2_bop_byt[49:52] & {4{ex2_mtfsf}}) |
(ex2_fpscr_bit_data[0:3] & {4{(~ex2_mtfsf)}});
assign shadow_byp2_din[0:7] = (ex2_fpscr_shadow_mux[0:7] & (~ex2_bit_sel[0:7])) |
(ex2_fpscr_data[0:7] & ex2_bit_sel[0:7]); // may not update all the bits
////##############################################
////# read mux select generation (for pipeline control bits)
////##############################################
assign ex2_mv_to_op = ex2_mtfsbx | ex2_mtfsf | ex2_mtfsfi;
assign ex3_mv_to_op = ex3_mtfsbx | ex3_mtfsf | ex3_mtfsfi;
assign ex4_mv_to_op = ex4_mtfsbx | ex4_mtfsf | ex4_mtfsfi;
assign ex1_thread_match_1 = (ex1_thread[0] & ex2_thread[0]) | (ex1_thread[1] & ex2_thread[1]) | (ex1_thread[2] & ex2_thread[2]) | (ex1_thread[3] & ex2_thread[3]);
assign ex1_thread_match_2 = (ex1_thread[0] & ex3_thread[0]) | (ex1_thread[1] & ex3_thread[1]) | (ex1_thread[2] & ex3_thread[2]) | (ex1_thread[3] & ex3_thread[3]);
assign ex1_thread_match_3 = (ex1_thread[0] & ex4_thread[0]) | (ex1_thread[1] & ex4_thread[1]) | (ex1_thread[2] & ex4_thread[2]) | (ex1_thread[3] & ex4_thread[3]);
assign ex1_thread_match_4 = (ex1_thread[0] & ex5_thread[0]) | (ex1_thread[1] & ex5_thread[1]) | (ex1_thread[2] & ex5_thread[2]) | (ex1_thread[3] & ex5_thread[3]);
assign ex1_thread_match_5 = (ex1_thread[0] & ex6_thread[0]) | (ex1_thread[1] & ex6_thread[1]) | (ex1_thread[2] & ex6_thread[2]) | (ex1_thread[3] & ex6_thread[3]);
assign ex1_rd_sel_byp2 = ex1_thread_match_1 & ex2_mv_to_op;
assign ex1_rd_sel_byp3 = ex1_thread_match_2 & ex3_mv_to_op;
assign ex1_rd_sel_byp4 = ex1_thread_match_3 & ex4_mv_to_op;
assign ex1_rd_sel_byp5 = ex1_thread_match_4 & ex5_mv_to_op;
assign ex1_rd_sel_byp6 = ex1_thread_match_5 & ex6_mv_to_op;
assign ex1_rd_sel_0 = ex1_thread[0] & (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & (~ex1_rd_sel_byp6);
assign ex1_rd_sel_1 = ex1_thread[1] & (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & (~ex1_rd_sel_byp6);
assign ex1_rd_sel_2 = ex1_thread[2] & (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & (~ex1_rd_sel_byp6);
assign ex1_rd_sel_3 = ex1_thread[3] & (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & (~ex1_rd_sel_byp6);
assign ex1_rd_sel_byp2_pri = ex1_rd_sel_byp2;
assign ex1_rd_sel_byp3_pri = (~ex1_rd_sel_byp2) & ex1_rd_sel_byp3;
assign ex1_rd_sel_byp4_pri = (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & ex1_rd_sel_byp4;
assign ex1_rd_sel_byp5_pri = (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & ex1_rd_sel_byp5;
assign ex1_rd_sel_byp6_pri = (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & ex1_rd_sel_byp6;
////##############################################
////# read mux for pipeline control bits
////##############################################
assign ex2_fpscr_shadow_mux[0:7] = ({8{ex2_rd_sel_0}} & shadow0[0:7]) |
({8{ex2_rd_sel_1}} & shadow1[0:7]) |
({8{ex2_rd_sel_2}} & shadow2[0:7]) |
({8{ex2_rd_sel_3}} & shadow3[0:7]) |
({8{ex2_rd_sel_byp2}} & shadow_byp2[0:7]) |
({8{ex2_rd_sel_byp3}} & shadow_byp3[0:7]) |
({8{ex2_rd_sel_byp4}} & shadow_byp4[0:7]) |
({8{ex2_rd_sel_byp5}} & shadow_byp5[0:7]) |
({8{ex2_rd_sel_byp6}} & shadow_byp6[0:7]);
assign f_cr2_ex2_fpscr_shadow[0:7] = ex2_fpscr_shadow_mux[0:7];
////##############################################
////# latches
////##############################################
tri_rlmreg_p #(.WIDTH(8)) shadow_byp2_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[2]), // tidn,
.mpw1_b(mpw1_b[2]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex2_act),
.scout(shadow_byp2_so),
.scin(shadow_byp2_si),
//----------------
.din(shadow_byp2_din[0:7]),
.dout(shadow_byp2[0:7]) //LAT--
);
tri_rlmreg_p #(.WIDTH(8)) shadow_byp3_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[3]), // tidn,
.mpw1_b(mpw1_b[3]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex3_act),
.scout(shadow_byp3_so),
.scin(shadow_byp3_si),
//-----------------
.din(shadow_byp2[0:7]),
.dout(shadow_byp3[0:7]) //LAT--
);
tri_rlmreg_p #(.WIDTH(8)) shadow_byp4_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[4]), // tidn,
.mpw1_b(mpw1_b[4]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex4_act),
.scout(shadow_byp4_so),
.scin(shadow_byp4_si),
//-----------------
.din(shadow_byp3[0:7]),
.dout(shadow_byp4[0:7]) //LAT--
);
tri_rlmreg_p #(.WIDTH(8)) shadow_byp5_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[5]), // tidn,
.mpw1_b(mpw1_b[5]), // tidn,
.mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex5_act),
.scout(shadow_byp5_so),
.scin(shadow_byp5_si),
//-----------------
.din(shadow_byp4[0:7]),
.dout(shadow_byp5[0:7]) //LAT--
);
tri_rlmreg_p #(.WIDTH(8)) shadow_byp6_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[6]), // tidn,
.mpw1_b(mpw1_b[6]), // tidn,
.mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex6_act),
.scout(shadow_byp6_so),
.scin(shadow_byp6_si),
//-----------------
.din(shadow_byp5[0:7]),
.dout(shadow_byp6[0:7]) //LAT--
);
assign ex7_th0_act = ex7_act & ex7_thread[0] & (~ex7_cancel) & ex7_mv_to_op;
assign ex7_th1_act = ex7_act & ex7_thread[1] & (~ex7_cancel) & ex7_mv_to_op;
assign ex7_th2_act = ex7_act & ex7_thread[2] & (~ex7_cancel) & ex7_mv_to_op;
assign ex7_th3_act = ex7_act & ex7_thread[3] & (~ex7_cancel) & ex7_mv_to_op;
tri_rlmreg_p #(.WIDTH(8)) shadow0_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[7]), // tidn,
.mpw1_b(mpw1_b[7]), // tidn,
.mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex7_th0_act),
.scout(shadow0_so),
.scin(shadow0_si),
//-----------------
.din(shadow_byp6[0:7]),
.dout(shadow0[0:7]) //LAT--
);
tri_rlmreg_p #(.WIDTH(8)) shadow1_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[7]), // tidn,
.mpw1_b(mpw1_b[7]), // tidn,
.mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex7_th1_act),
.scout(shadow1_so),
.scin(shadow1_si),
//-----------------
.din(shadow_byp6[0:7]),
.dout(shadow1[0:7]) //LAT--
);
tri_rlmreg_p #(.WIDTH(8)) shadow2_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[7]), // tidn,
.mpw1_b(mpw1_b[7]), // tidn,
.mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex7_th2_act),
.scout(shadow2_so),
.scin(shadow2_si),
//-----------------
.din(shadow_byp6[0:7]),
.dout(shadow2[0:7]) //LAT--
);
tri_rlmreg_p #(.WIDTH(8)) shadow3_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[7]), // tidn,
.mpw1_b(mpw1_b[7]), // tidn,
.mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex7_th3_act),
.scout(shadow3_so),
.scin(shadow3_si),
//-----------------
.din(shadow_byp6[0:7]),
.dout(shadow3[0:7]) //LAT--
);
////############################################
////# scan
////############################################
// initial value must be "11111" for _b latches --
assign ex2_ctl_si[0:33] = {ex2_ctl_so[1:33], f_cr2_si};
assign ex3_ctl_si[0:24] = {ex3_ctl_so[1:24], ex2_ctl_so[0]};
assign ex4_ctl_si[0:24] = {ex4_ctl_so[1:24], ex3_ctl_so[0]};
assign ex5_ctl_si[0:4] = {ex5_ctl_so[1:4], ex4_ctl_so[0]};
assign ex6_ctl_si[0:4] = {ex6_ctl_so[1:4], ex5_ctl_so[0]};
assign ex7_ctl_si[0:4] = {ex7_ctl_so[1:4], ex6_ctl_so[0]};
assign shadow0_si[0:7] = {shadow0_so[1:7], ex7_ctl_so[0]};
assign shadow1_si[0:7] = {shadow1_so[1:7], shadow0_so[0]};
assign shadow2_si[0:7] = {shadow2_so[1:7], shadow1_so[0]};
assign shadow3_si[0:7] = {shadow3_so[1:7], shadow2_so[0]};
assign shadow_byp2_si[0:7] = {shadow_byp2_so[1:7], shadow3_so[0]};
assign shadow_byp3_si[0:7] = {shadow_byp3_so[1:7], shadow_byp2_so[0]};
assign shadow_byp4_si[0:7] = {shadow_byp4_so[1:7], shadow_byp3_so[0]};
assign shadow_byp5_si[0:7] = {shadow_byp5_so[1:7], shadow_byp4_so[0]};
assign shadow_byp6_si[0:7] = {shadow_byp6_so[1:7], shadow_byp5_so[0]};
assign act_si[0:6] = {act_so[1:6], shadow_byp6_so[0]};
assign f_cr2_so = act_so[0];
endmodule |
module fu_perv(
vdd,
gnd,
nclk,
pc_fu_sg_3,
pc_fu_abst_sl_thold_3,
pc_fu_func_sl_thold_3,
pc_fu_func_slp_sl_thold_3,
pc_fu_gptr_sl_thold_3,
pc_fu_time_sl_thold_3,
pc_fu_ary_nsl_thold_3,
pc_fu_cfg_sl_thold_3,
pc_fu_repr_sl_thold_3,
pc_fu_fce_3,
tc_ac_ccflush_dc,
tc_ac_scan_diag_dc,
abst_sl_thold_1,
func_sl_thold_1,
time_sl_thold_1,
ary_nsl_thold_1,
cfg_sl_thold_1,
gptr_sl_thold_0,
func_slp_sl_thold_1,
fce_1,
sg_1,
clkoff_dc_b,
act_dis,
delay_lclkr_dc,
mpw1_dc_b,
mpw2_dc_b,
repr_scan_in,
repr_scan_out,
gptr_scan_in,
gptr_scan_out
);
inout vdd;
inout gnd;
input [0:`NCLK_WIDTH-1] nclk;
input [0:1] pc_fu_sg_3;
input pc_fu_abst_sl_thold_3;
input [0:1] pc_fu_func_sl_thold_3;
input [0:1] pc_fu_func_slp_sl_thold_3;
input pc_fu_gptr_sl_thold_3;
input pc_fu_time_sl_thold_3;
input pc_fu_ary_nsl_thold_3;
input pc_fu_cfg_sl_thold_3;
input pc_fu_repr_sl_thold_3;
input pc_fu_fce_3;
input tc_ac_ccflush_dc;
input tc_ac_scan_diag_dc;
output abst_sl_thold_1;
output [0:1] func_sl_thold_1;
output time_sl_thold_1;
output ary_nsl_thold_1;
output cfg_sl_thold_1;
output gptr_sl_thold_0;
output func_slp_sl_thold_1;
output fce_1;
output [0:1] sg_1;
output clkoff_dc_b;
output act_dis;
output [0:9] delay_lclkr_dc;
output [0:9] mpw1_dc_b;
output [0:1] mpw2_dc_b;
input repr_scan_in; //tc_ac_repr_scan_in(2)
output repr_scan_out; //tc_ac_repr_scan_in(2)
input gptr_scan_in;
output gptr_scan_out;
//--
wire abst_sl_thold_2;
wire time_sl_thold_2;
wire [0:1] func_sl_thold_2;
wire func_slp_sl_thold_2;
wire gptr_sl_thold_0_int;
wire gptr_sl_thold_2;
wire ary_nsl_thold_2;
wire cfg_sl_thold_2;
wire repr_sl_thold_2;
wire [0:1] sg_2;
wire fce_2;
wire gptr_sl_thold_1;
wire repr_sl_thold_1;
wire [0:1] sg_1_int;
wire repr_sl_thold_0;
wire repr_sl_force;
wire repr_sl_thold_0_b;
wire repr_in;
wire repr_UNUSED;
(* analysis_not_assigned="true" *)
(* analysis_not_referenced="true" *)
wire spare_unused;
wire sg_0;
wire gptr_sio;
wire [0:9] prv_delay_lclkr_dc;
wire [0:9] prv_mpw1_dc_b;
wire [0:1] prv_mpw2_dc_b;
wire prv_act_dis;
wire prv_clkoff_dc_b;
wire tihi;
wire tiup;
assign tihi = 1'b1;
assign tiup = 1'b1;
tri_plat #(.WIDTH(12)) perv_3to2_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({
pc_fu_func_sl_thold_3[0:1],
pc_fu_gptr_sl_thold_3,
pc_fu_abst_sl_thold_3,
pc_fu_sg_3[0:1],
pc_fu_time_sl_thold_3,
pc_fu_fce_3,
pc_fu_ary_nsl_thold_3,
pc_fu_cfg_sl_thold_3,
pc_fu_repr_sl_thold_3,
pc_fu_func_slp_sl_thold_3[0]}),
.q({
func_sl_thold_2[0:1],
gptr_sl_thold_2,
abst_sl_thold_2,
sg_2[0:1],
time_sl_thold_2,
fce_2,
ary_nsl_thold_2,
cfg_sl_thold_2,
repr_sl_thold_2,
func_slp_sl_thold_2})
);
tri_plat #(.WIDTH(12)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({
func_sl_thold_2[0:1],
gptr_sl_thold_2,
abst_sl_thold_2,
sg_2[0:1],
time_sl_thold_2,
fce_2,
ary_nsl_thold_2,
cfg_sl_thold_2,
repr_sl_thold_2,
func_slp_sl_thold_2}),
.q({
func_sl_thold_1[0:1],
gptr_sl_thold_1,
abst_sl_thold_1,
sg_1_int[0:1],
time_sl_thold_1,
fce_1,
ary_nsl_thold_1,
cfg_sl_thold_1,
repr_sl_thold_1,
func_slp_sl_thold_1})
);
assign sg_1[0:1] = sg_1_int[0:1];
tri_plat #(.WIDTH(3)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({ gptr_sl_thold_1,
sg_1_int[0],
repr_sl_thold_1}),
.q({ gptr_sl_thold_0_int,
sg_0,
repr_sl_thold_0})
);
assign gptr_sl_thold_0 = gptr_sl_thold_0_int;
// Pipeline mapping of mpw1_b and delay_lclkr, mpw2_b
// RF0 8 1
// RF1 0 0
// EX1 1 0
// EX2 2 0
// EX3 3 0
// EX4 4 0
// EX5 5 1
// EX6 6 1
// EX7 7 1
// Ctrl 9 1
tri_lcbcntl_mac perv_lcbctrl0(
.vdd(vdd),
.gnd(gnd),
.sg(sg_0),
.nclk(nclk),
.scan_in(gptr_scan_in),
.scan_diag_dc(tc_ac_scan_diag_dc),
.thold(gptr_sl_thold_0_int),
.clkoff_dc_b(prv_clkoff_dc_b),
.delay_lclkr_dc(prv_delay_lclkr_dc[0:4]),
.act_dis_dc(),
.mpw1_dc_b(prv_mpw1_dc_b[0:4]),
.mpw2_dc_b(prv_mpw2_dc_b[0]),
.scan_out(gptr_sio)
);
tri_lcbcntl_mac perv_lcbctrl1(
.vdd(vdd),
.gnd(gnd),
.sg(sg_0),
.nclk(nclk),
.scan_in(gptr_sio),
.scan_diag_dc(tc_ac_scan_diag_dc),
.thold(gptr_sl_thold_0_int),
.clkoff_dc_b(),
.delay_lclkr_dc(prv_delay_lclkr_dc[5:9]),
.act_dis_dc(),
.mpw1_dc_b(prv_mpw1_dc_b[5:9]),
.mpw2_dc_b(prv_mpw2_dc_b[1]),
.scan_out(gptr_scan_out)
);
//Outputs
assign delay_lclkr_dc[0:9] = prv_delay_lclkr_dc[0:9];
assign mpw1_dc_b[0:9] = prv_mpw1_dc_b[0:9];
assign mpw2_dc_b[0:1] = prv_mpw2_dc_b[0:1];
//never disable act pins, they are used functionally
assign prv_act_dis = 1'b0;
assign act_dis = prv_act_dis;
assign clkoff_dc_b = prv_clkoff_dc_b;
// Repower latch for repr scan ins/outs
tri_lcbor repr_sl_lcbor_0(
.clkoff_b(prv_clkoff_dc_b),
.thold(repr_sl_thold_0),
.sg(sg_0),
.act_dis(prv_act_dis),
.force_t(repr_sl_force),
.thold_b(repr_sl_thold_0_b)
);
assign repr_in = 1'b0;
tri_rlmreg_p #(.INIT(0), .WIDTH(1)) repr_rpwr_lat(
.nclk(nclk),
.act(tihi),
.force_t(repr_sl_force),
.d_mode(tiup),
.delay_lclkr(prv_delay_lclkr_dc[9]),
.mpw1_b(prv_mpw1_dc_b[9]),
.mpw2_b(prv_mpw2_dc_b[1]),
.thold_b(repr_sl_thold_0_b),
.sg(sg_0),
.vd(vdd),
.gd(gnd),
.scin(repr_scan_in),
.scout(repr_scan_out),
//-------------------------------------------
.din(repr_in),
//-------------------------------------------
.dout(repr_UNUSED)
);
// Unused logic
assign spare_unused = pc_fu_func_slp_sl_thold_3[1];
endmodule |
module fu_loc8inc_lsb(
x,
co_b,
s0,
s1
);
input [0:4] x; //48 to 52
output co_b;
output [0:4] s0;
output [0:4] s1;
wire [0:4] x_b;
wire [0:4] t2_b;
wire [0:4] t4;
// FOLDED layout
// i0_xb i2_xb i4_xb skip skip skip skip
// i1_xb i3_xb skip skip skip skip skip
// i0_t2 i2_t2 i4_t2 skip skip skip skip
// skip i1_t2 i3_t2 skip skip skip skip
// i0_t2 i2_t2 i4_t2 skip skip skip skip
// i0_t8 i1_t2 i3_t2 skip skip skip skip
// i0_s0 i2_s0 i4_s0 skip skip skip skip
// i1_s0 i3_s0 skip skip skip skip skip
// i0_s1 i2_s1 i4_s1 skip skip skip skip
// i1_s1 i3_s1 skip skip skip skip skip
//-------------------------------
// buffer off non critical path
//-------------------------------
assign x_b[0] = (~x[0]);
assign x_b[1] = (~x[1]);
assign x_b[2] = (~x[2]);
assign x_b[3] = (~x[3]);
assign x_b[4] = (~x[4]);
//--------------------------
// local carry chain
//--------------------------
assign t2_b[0] = (~(x[0]));
assign t2_b[1] = (~(x[1] & x[2]));
assign t2_b[2] = (~(x[2] & x[3]));
assign t2_b[3] = (~(x[3] & x[4]));
assign t2_b[4] = (~(x[4]));
assign t4[0] = (~(t2_b[0]));
assign t4[1] = (~(t2_b[1] | t2_b[3]));
assign t4[2] = (~(t2_b[2] | t2_b[4]));
assign t4[3] = (~(t2_b[3]));
assign t4[4] = (~(t2_b[4]));
assign co_b = (~(t4[0] & t4[1]));
//------------------------
// sum generation
//------------------------
assign s0[0] = (~(x_b[0]));
assign s0[1] = (~(x_b[1]));
assign s0[2] = (~(x_b[2]));
assign s0[3] = (~(x_b[3]));
assign s0[4] = (~(x_b[4]));
assign s1[0] = (~(x_b[0] ^ t4[1]));
assign s1[1] = (~(x_b[1] ^ t4[2]));
assign s1[2] = (~(x_b[2] ^ t4[3]));
assign s1[3] = (~(x_b[3] ^ t4[4]));
assign s1[4] = (~(t4[4]));
endmodule |
module lq_spr
#(
parameter hvmode = 1,
parameter a2mode = 1
)(
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
input [0:`NCLK_WIDTH-1] nclk,
input d_mode_dc,
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input ccfg_sl_force,
input ccfg_sl_thold_0_b,
input func_sl_force,
input func_sl_thold_0_b,
input func_nsl_force,
input func_nsl_thold_0_b,
input sg_0,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input ccfg_scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output ccfg_scan_out,
input [0:`THREADS-1] flush,
input [0:`THREADS-1] ex1_valid,
input ex3_data_val,
input [64-`GPR_WIDTH:63] ex3_eff_addr,
// SlowSPR Interface
input slowspr_val_in,
input slowspr_rw_in,
input [0:1] slowspr_etid_in,
input [0:9] slowspr_addr_in,
input [64-`GPR_WIDTH:63] slowspr_data_in,
input slowspr_done_in,
output slowspr_val_out,
output slowspr_rw_out,
output [0:1] slowspr_etid_out,
output [0:9] slowspr_addr_out,
output [64-`GPR_WIDTH:63] slowspr_data_out,
output slowspr_done_out,
// DAC
input ex2_is_any_load_dac,
input ex2_is_any_store_dac,
output spr_dcc_ex4_dvc1_en,
output spr_dcc_ex4_dvc2_en,
output spr_dcc_ex4_dacrw1_cmpr,
output spr_dcc_ex4_dacrw2_cmpr,
output spr_dcc_ex4_dacrw3_cmpr,
output spr_dcc_ex4_dacrw4_cmpr,
// SPRs
input [0:`THREADS-1] spr_msr_pr,
input [0:`THREADS-1] spr_msr_gs,
input [0:`THREADS-1] spr_msr_ds,
input [0:2*`THREADS-1] spr_dbcr0_dac1,
input [0:2*`THREADS-1] spr_dbcr0_dac2,
input [0:2*`THREADS-1] spr_dbcr0_dac3,
input [0:2*`THREADS-1] spr_dbcr0_dac4,
output spr_xudbg0_exec,
output [0:`THREADS-1] spr_xudbg0_tid,
input spr_xudbg0_done,
input spr_xudbg1_valid,
input [0:3] spr_xudbg1_watch,
input [0:3] spr_xudbg1_parity,
input [0:6] spr_xudbg1_lru,
input spr_xudbg1_lock,
input [33:63] spr_xudbg2_tag,
output [0:8*`THREADS-1] spr_dbcr2_dvc1be,
output [0:8*`THREADS-1] spr_dbcr2_dvc2be,
output [0:2*`THREADS-1] spr_dbcr2_dvc1m,
output [0:2*`THREADS-1] spr_dbcr2_dvc2m,
output [0:`THREADS-1] spr_epsc_wr,
output [0:`THREADS-1] spr_eplc_wr,
output [0:31] spr_pesr,
output [0:`GPR_WIDTH-1] spr_dvc1,
output [0:`GPR_WIDTH-1] spr_dvc2,
output [0:5] spr_lesr1_muxseleb0,
output [0:5] spr_lesr1_muxseleb1,
output [0:5] spr_lesr1_muxseleb2,
output [0:5] spr_lesr1_muxseleb3,
output [0:5] spr_lesr2_muxseleb4,
output [0:5] spr_lesr2_muxseleb5,
output [0:5] spr_lesr2_muxseleb6,
output [0:5] spr_lesr2_muxseleb7,
output [0:2] spr_lsucr0_lca,
output [0:2] spr_lsucr0_sca,
output spr_lsucr0_lge,
output spr_lsucr0_b2b,
output spr_lsucr0_dfwd,
output spr_lsucr0_clchk,
output spr_lsucr0_ford,
output [0:7] spr_xucr2_rmt3,
output [0:7] spr_xucr2_rmt2,
output [0:7] spr_xucr2_rmt1,
output [0:7] spr_xucr2_rmt0,
output [0:2] spr_xudbg0_way,
output [0:5] spr_xudbg0_row,
output [0:32*`THREADS-1] spr_acop_ct,
output [0:`THREADS-1] spr_dbcr3_ivc,
output [0:`THREADS-1] spr_dscr_lsd,
output [0:`THREADS-1] spr_dscr_snse,
output [0:`THREADS-1] spr_dscr_sse,
output [0:3*`THREADS-1] spr_dscr_dpfd,
output [0:`THREADS-1] spr_eplc_epr,
output [0:`THREADS-1] spr_eplc_eas,
output [0:`THREADS-1] spr_eplc_egs,
output [0:8*`THREADS-1] spr_eplc_elpid,
output [0:14*`THREADS-1] spr_eplc_epid,
output [0:`THREADS-1] spr_epsc_epr,
output [0:`THREADS-1] spr_epsc_eas,
output [0:`THREADS-1] spr_epsc_egs,
output [0:8*`THREADS-1] spr_epsc_elpid,
output [0:14*`THREADS-1] spr_epsc_epid,
output [0:32*`THREADS-1] spr_hacop_ct,
// Power
inout vdd,
inout gnd
);
localparam tiup = 1'b1;
wire slowspr_val_in_q; // input=>slowspr_val_in ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func
wire slowspr_rw_in_q; // input=>slowspr_rw_in ,act=>slowspr_act_in ,scan=>Y ,sleep=>N, ring=>func
wire [0:1] slowspr_etid_in_q; // input=>slowspr_etid_in ,act=>slowspr_act_in ,scan=>Y ,sleep=>N, ring=>func
wire [0:9] slowspr_addr_in_q; // input=>slowspr_addr_in ,act=>slowspr_act_in ,scan=>Y ,sleep=>N, ring=>func
wire [64-`GPR_WIDTH:63] slowspr_data_in_q; // input=>slowspr_data_in ,act=>slowspr_act_in ,scan=>Y ,sleep=>N, ring=>func
wire slowspr_done_in_q; // input=>slowspr_done_in ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func
wire slowspr_val_out_q; // input=>slowspr_val_in_q ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func
wire slowspr_rw_out_q; // input=>slowspr_rw_in_q ,act=>slowspr_val_in_q ,scan=>Y ,sleep=>N, ring=>func
wire [0:1] slowspr_etid_out_q; // input=>slowspr_etid_in_q ,act=>slowspr_val_in_q ,scan=>Y ,sleep=>N, ring=>func
wire [0:9] slowspr_addr_out_q; // input=>slowspr_addr_in_q ,act=>slowspr_val_in_q ,scan=>Y ,sleep=>N, ring=>func
wire [64-`GPR_WIDTH:63] slowspr_data_out_q; // input=>slowspr_data_out_d ,act=>slowspr_val_in_q ,scan=>Y ,sleep=>N, ring=>func
wire [64-`GPR_WIDTH:63] slowspr_data_out_d;
wire slowspr_done_out_q; // input=>slowspr_done_out_d ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func
wire slowspr_done_out_d;
wire [0:`THREADS-1] flush_q; // input=>flush ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func
// Scanchain
parameter slowspr_val_in_offset = `THREADS + 1;
parameter slowspr_rw_in_offset = slowspr_val_in_offset + 1;
parameter slowspr_etid_in_offset = slowspr_rw_in_offset + 1;
parameter slowspr_addr_in_offset = slowspr_etid_in_offset + 2;
parameter slowspr_data_in_offset = slowspr_addr_in_offset + 10;
parameter slowspr_done_in_offset = slowspr_data_in_offset + `GPR_WIDTH;
parameter slowspr_val_out_offset = slowspr_done_in_offset + 1;
parameter slowspr_rw_out_offset = slowspr_val_out_offset + 1;
parameter slowspr_etid_out_offset = slowspr_rw_out_offset + 1;
parameter slowspr_addr_out_offset = slowspr_etid_out_offset + 2;
parameter slowspr_data_out_offset = slowspr_addr_out_offset + 10;
parameter slowspr_done_out_offset = slowspr_data_out_offset + `GPR_WIDTH;
parameter flush_offset = slowspr_done_out_offset + 1;
parameter scan_right = flush_offset + `THREADS;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
// Signals
wire slowspr_act_in;
wire [0:`THREADS-1] slowspr_val_tid;
wire [0:3] slowspr_tid;
wire [0:3] slowspr_tid_in;
wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dac1us;
wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dac1er;
wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dac2us;
wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dac2er;
wire [0:2*`THREADS-1] tspr_cspr_dbcr3_dac3us;
wire [0:2*`THREADS-1] tspr_cspr_dbcr3_dac3er;
wire [0:2*`THREADS-1] tspr_cspr_dbcr3_dac4us;
wire [0:2*`THREADS-1] tspr_cspr_dbcr3_dac4er;
wire [0:`THREADS-1] tspr_cspr_dbcr2_dac12m;
wire [0:`THREADS-1] tspr_cspr_dbcr3_dac34m;
wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dvc1m;
wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dvc2m;
wire [0:8*`THREADS-1] tspr_cspr_dbcr2_dvc1be;
wire [0:8*`THREADS-1] tspr_cspr_dbcr2_dvc2be;
wire [0:`THREADS-1] tspr_done;
wire [0:`THREADS-1] tspr_sel;
wire [0:`GPR_WIDTH-1] tspr_rt[0:`THREADS-1];
wire cspr_done;
wire [64-`GPR_WIDTH:63] cspr_rt;
wire [0:`THREADS-1] cspr_tspr_msr_pr;
wire [0:`THREADS-1] cspr_tspr_msr_gs;
wire slowspr_val_in_gate;
wire slowspr_val_in_stg;
reg [0:`GPR_WIDTH-1] tspr_tid_mux;
assign slowspr_tid = (slowspr_etid_in_q == 2'b00) ? 4'b1000 :
(slowspr_etid_in_q == 2'b01) ? 4'b0100 :
(slowspr_etid_in_q == 2'b10) ? 4'b0010 :
(slowspr_etid_in_q == 2'b11) ? 4'b0001 :
4'b0000;
assign slowspr_tid_in = (slowspr_etid_in == 2'b00) ? 4'b1000 :
(slowspr_etid_in == 2'b01) ? 4'b0100 :
(slowspr_etid_in == 2'b10) ? 4'b0010 :
(slowspr_etid_in == 2'b11) ? 4'b0001 :
4'b0000;
assign slowspr_val_tid = slowspr_tid[0:`THREADS-1] & {`THREADS{slowspr_val_in_q}};
assign tspr_sel = tspr_done & slowspr_val_tid;
assign slowspr_val_in_gate = slowspr_val_in & ~(|(slowspr_tid_in[0:`THREADS - 1] & flush_q));
assign slowspr_val_in_stg = slowspr_val_in_q & ~(|(slowspr_tid[0:`THREADS - 1] & flush_q));
assign slowspr_act_in = slowspr_val_in;
assign slowspr_val_out = slowspr_val_out_q;
assign slowspr_rw_out = slowspr_rw_out_q;
assign slowspr_etid_out = slowspr_etid_out_q;
assign slowspr_addr_out = slowspr_addr_out_q;
assign slowspr_data_out = slowspr_data_out_q;
assign slowspr_done_out = slowspr_done_out_q;
assign spr_xudbg0_tid = slowspr_tid[0:`THREADS-1];
always @* begin : tsprMux
reg [0:`GPR_WIDTH-1] tspr;
integer tid;
tspr = {`GPR_WIDTH{1'b0}};
for (tid=0; tid<`THREADS; tid=tid+1) begin
tspr = (tspr_rt[tid] & {`GPR_WIDTH{tspr_sel[tid]}}) | tspr;
end
tspr_tid_mux <= tspr;
end
assign slowspr_done_out_d = slowspr_done_in_q | |(tspr_done) | cspr_done;
assign slowspr_data_out_d = slowspr_data_in_q | tspr_tid_mux | (cspr_rt & {`GPR_WIDTH{cspr_done}});
assign spr_dbcr2_dvc1be = tspr_cspr_dbcr2_dvc1be;
assign spr_dbcr2_dvc2be = tspr_cspr_dbcr2_dvc2be;
assign spr_dbcr2_dvc1m = tspr_cspr_dbcr2_dvc1m;
assign spr_dbcr2_dvc2m = tspr_cspr_dbcr2_dvc2m;
lq_spr_cspr #(.hvmode(hvmode), .a2mode(a2mode)) lq_spr_cspr(
.nclk(nclk),
.d_mode_dc(d_mode_dc),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.ccfg_sl_force(ccfg_sl_force),
.ccfg_sl_thold_0_b(ccfg_sl_thold_0_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.func_nsl_force(func_nsl_force),
.func_nsl_thold_0_b(func_nsl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[`THREADS]),
.scan_out(sov[`THREADS]),
.ccfg_scan_in(ccfg_scan_in),
.ccfg_scan_out(ccfg_scan_out),
.flush(flush_q),
.ex1_valid(ex1_valid),
.ex3_data_val(ex3_data_val),
.ex3_eff_addr(ex3_eff_addr),
// SlowSPR Interface
.slowspr_val_in(slowspr_val_in_q),
.slowspr_rw_in(slowspr_rw_in_q),
.slowspr_addr_in(slowspr_addr_in_q),
.slowspr_data_in(slowspr_data_in_q),
.cspr_done(cspr_done),
.cspr_rt(cspr_rt),
// DAC
.ex2_is_any_load_dac(ex2_is_any_load_dac),
.ex2_is_any_store_dac(ex2_is_any_store_dac),
.spr_dcc_ex4_dvc1_en(spr_dcc_ex4_dvc1_en),
.spr_dcc_ex4_dvc2_en(spr_dcc_ex4_dvc2_en),
.spr_dcc_ex4_dacrw1_cmpr(spr_dcc_ex4_dacrw1_cmpr),
.spr_dcc_ex4_dacrw2_cmpr(spr_dcc_ex4_dacrw2_cmpr),
.spr_dcc_ex4_dacrw3_cmpr(spr_dcc_ex4_dacrw3_cmpr),
.spr_dcc_ex4_dacrw4_cmpr(spr_dcc_ex4_dacrw4_cmpr),
// SPRs
.spr_msr_pr(spr_msr_pr),
.spr_msr_gs(spr_msr_gs),
.spr_msr_ds(spr_msr_ds),
.spr_dbcr0_dac1(spr_dbcr0_dac1),
.spr_dbcr0_dac2(spr_dbcr0_dac2),
.spr_dbcr0_dac3(spr_dbcr0_dac3),
.spr_dbcr0_dac4(spr_dbcr0_dac4),
.spr_xudbg0_exec(spr_xudbg0_exec),
.spr_xudbg0_done(spr_xudbg0_done),
.spr_xudbg1_valid(spr_xudbg1_valid),
.spr_xudbg1_watch(spr_xudbg1_watch),
.spr_xudbg1_parity(spr_xudbg1_parity),
.spr_xudbg1_lru(spr_xudbg1_lru),
.spr_xudbg1_lock(spr_xudbg1_lock),
.spr_xudbg2_tag(spr_xudbg2_tag),
.spr_pesr(spr_pesr),
.cspr_tspr_msr_pr(cspr_tspr_msr_pr),
.cspr_tspr_msr_gs(cspr_tspr_msr_gs),
.tspr_cspr_dbcr2_dac1us(tspr_cspr_dbcr2_dac1us),
.tspr_cspr_dbcr2_dac1er(tspr_cspr_dbcr2_dac1er),
.tspr_cspr_dbcr2_dac2us(tspr_cspr_dbcr2_dac2us),
.tspr_cspr_dbcr2_dac2er(tspr_cspr_dbcr2_dac2er),
.tspr_cspr_dbcr3_dac3us(tspr_cspr_dbcr3_dac3us),
.tspr_cspr_dbcr3_dac3er(tspr_cspr_dbcr3_dac3er),
.tspr_cspr_dbcr3_dac4us(tspr_cspr_dbcr3_dac4us),
.tspr_cspr_dbcr3_dac4er(tspr_cspr_dbcr3_dac4er),
.tspr_cspr_dbcr2_dac12m(tspr_cspr_dbcr2_dac12m),
.tspr_cspr_dbcr3_dac34m(tspr_cspr_dbcr3_dac34m),
.tspr_cspr_dbcr2_dvc1m(tspr_cspr_dbcr2_dvc1m),
.tspr_cspr_dbcr2_dvc2m(tspr_cspr_dbcr2_dvc2m),
.tspr_cspr_dbcr2_dvc1be(tspr_cspr_dbcr2_dvc1be),
.tspr_cspr_dbcr2_dvc2be(tspr_cspr_dbcr2_dvc2be),
.spr_dvc1(spr_dvc1),
.spr_dvc2(spr_dvc2),
.spr_lesr1_muxseleb0(spr_lesr1_muxseleb0),
.spr_lesr1_muxseleb1(spr_lesr1_muxseleb1),
.spr_lesr1_muxseleb2(spr_lesr1_muxseleb2),
.spr_lesr1_muxseleb3(spr_lesr1_muxseleb3),
.spr_lesr2_muxseleb4(spr_lesr2_muxseleb4),
.spr_lesr2_muxseleb5(spr_lesr2_muxseleb5),
.spr_lesr2_muxseleb6(spr_lesr2_muxseleb6),
.spr_lesr2_muxseleb7(spr_lesr2_muxseleb7),
.spr_lsucr0_lca(spr_lsucr0_lca),
.spr_lsucr0_sca(spr_lsucr0_sca),
.spr_lsucr0_lge(spr_lsucr0_lge),
.spr_lsucr0_b2b(spr_lsucr0_b2b),
.spr_lsucr0_dfwd(spr_lsucr0_dfwd),
.spr_lsucr0_clchk(spr_lsucr0_clchk),
.spr_lsucr0_ford(spr_lsucr0_ford),
.spr_xucr2_rmt3(spr_xucr2_rmt3),
.spr_xucr2_rmt2(spr_xucr2_rmt2),
.spr_xucr2_rmt1(spr_xucr2_rmt1),
.spr_xucr2_rmt0(spr_xucr2_rmt0),
.spr_xudbg0_way(spr_xudbg0_way),
.spr_xudbg0_row(spr_xudbg0_row),
// Power
.vdd(vdd),
.gnd(gnd)
);
generate begin : thread
genvar t;
for (t=0; t<`THREADS; t=t+1) begin : thread
lq_spr_tspr #(.hvmode(hvmode), .a2mode(a2mode)) lq_spr_tspr(
.nclk(nclk),
.d_mode_dc(d_mode_dc),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[t]),
.scan_out(sov[t]),
// SlowSPR Interface
.slowspr_val_in(slowspr_val_tid[t]),
.slowspr_rw_in(slowspr_rw_in_q),
.slowspr_addr_in(slowspr_addr_in_q),
.slowspr_data_in(slowspr_data_in_q),
.tspr_done(tspr_done[t]),
.tspr_rt(tspr_rt[t]),
// SPRs
.cspr_tspr_msr_pr(cspr_tspr_msr_pr[t]),
.cspr_tspr_msr_gs(cspr_tspr_msr_gs[t]),
.tspr_cspr_dbcr2_dac1us(tspr_cspr_dbcr2_dac1us[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr2_dac1er(tspr_cspr_dbcr2_dac1er[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr2_dac2us(tspr_cspr_dbcr2_dac2us[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr2_dac2er(tspr_cspr_dbcr2_dac2er[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr3_dac3us(tspr_cspr_dbcr3_dac3us[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr3_dac3er(tspr_cspr_dbcr3_dac3er[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr3_dac4us(tspr_cspr_dbcr3_dac4us[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr3_dac4er(tspr_cspr_dbcr3_dac4er[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr2_dac12m(tspr_cspr_dbcr2_dac12m[t]),
.tspr_cspr_dbcr3_dac34m(tspr_cspr_dbcr3_dac34m[t]),
.tspr_cspr_dbcr2_dvc1m(tspr_cspr_dbcr2_dvc1m[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr2_dvc2m(tspr_cspr_dbcr2_dvc2m[t*2:2*(t+1)-1]),
.tspr_cspr_dbcr2_dvc1be(tspr_cspr_dbcr2_dvc1be[t*8:8*(t+1)-1]),
.tspr_cspr_dbcr2_dvc2be(tspr_cspr_dbcr2_dvc2be[t*8:8*(t+1)-1]),
.spr_epsc_wr(spr_epsc_wr[t]),
.spr_eplc_wr(spr_eplc_wr[t]),
.spr_acop_ct(spr_acop_ct[32*t : 32*(t+1)-1]),
.spr_dbcr3_ivc(spr_dbcr3_ivc[t]),
.spr_dscr_lsd(spr_dscr_lsd[t]),
.spr_dscr_snse(spr_dscr_snse[t]),
.spr_dscr_sse(spr_dscr_sse[t]),
.spr_dscr_dpfd(spr_dscr_dpfd[3*t : 3*(t+1)-1]),
.spr_eplc_epr(spr_eplc_epr[t]),
.spr_eplc_eas(spr_eplc_eas[t]),
.spr_eplc_egs(spr_eplc_egs[t]),
.spr_eplc_elpid(spr_eplc_elpid[8*t : 8*(t+1)-1]),
.spr_eplc_epid(spr_eplc_epid[14*t : 14*(t+1)-1]),
.spr_epsc_epr(spr_epsc_epr[t]),
.spr_epsc_eas(spr_epsc_eas[t]),
.spr_epsc_egs(spr_epsc_egs[t]),
.spr_epsc_elpid(spr_epsc_elpid[8*t : 8*(t+1)-1]),
.spr_epsc_epid(spr_epsc_epid[14*t : 14*(t+1)-1]),
.spr_hacop_ct(spr_hacop_ct[32*t : 32*(t+1)-1]),
// Power
.vdd(vdd),
.gnd(gnd)
);
end
end
endgenerate
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_in_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_val_in_offset]),
.scout(sov[slowspr_val_in_offset]),
.din(slowspr_val_in_gate),
.dout(slowspr_val_in_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_in_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(slowspr_act_in),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_rw_in_offset]),
.scout(sov[slowspr_rw_in_offset]),
.din(slowspr_rw_in),
.dout(slowspr_rw_in_q)
);
tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_in_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(slowspr_act_in),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_etid_in_offset:slowspr_etid_in_offset + 2 - 1]),
.scout(sov[slowspr_etid_in_offset:slowspr_etid_in_offset + 2 - 1]),
.din(slowspr_etid_in),
.dout(slowspr_etid_in_q)
);
tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_in_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(slowspr_act_in),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_addr_in_offset:slowspr_addr_in_offset + 10 - 1]),
.scout(sov[slowspr_addr_in_offset:slowspr_addr_in_offset + 10 - 1]),
.din(slowspr_addr_in),
.dout(slowspr_addr_in_q)
);
tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_in_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(slowspr_act_in),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_data_in_offset:slowspr_data_in_offset + `GPR_WIDTH - 1]),
.scout(sov[slowspr_data_in_offset:slowspr_data_in_offset + `GPR_WIDTH - 1]),
.din(slowspr_data_in),
.dout(slowspr_data_in_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_in_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_done_in_offset]),
.scout(sov[slowspr_done_in_offset]),
.din(slowspr_done_in),
.dout(slowspr_done_in_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_out_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_val_out_offset]),
.scout(sov[slowspr_val_out_offset]),
.din(slowspr_val_in_stg),
.dout(slowspr_val_out_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_out_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(slowspr_val_in_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_rw_out_offset]),
.scout(sov[slowspr_rw_out_offset]),
.din(slowspr_rw_in_q),
.dout(slowspr_rw_out_q)
);
tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_out_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(slowspr_val_in_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_etid_out_offset:slowspr_etid_out_offset + 2 - 1]),
.scout(sov[slowspr_etid_out_offset:slowspr_etid_out_offset + 2 - 1]),
.din(slowspr_etid_in_q),
.dout(slowspr_etid_out_q)
);
tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_out_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(slowspr_val_in_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_addr_out_offset:slowspr_addr_out_offset + 10 - 1]),
.scout(sov[slowspr_addr_out_offset:slowspr_addr_out_offset + 10 - 1]),
.din(slowspr_addr_in_q),
.dout(slowspr_addr_out_q)
);
tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_out_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(slowspr_val_in_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_data_out_offset:slowspr_data_out_offset + `GPR_WIDTH - 1]),
.scout(sov[slowspr_data_out_offset:slowspr_data_out_offset + `GPR_WIDTH - 1]),
.din(slowspr_data_out_d),
.dout(slowspr_data_out_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_out_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[slowspr_done_out_offset]),
.scout(sov[slowspr_done_out_offset]),
.din(slowspr_done_out_d),
.dout(slowspr_done_out_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) flush_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[flush_offset:flush_offset + `THREADS - 1]),
.scout(sov[flush_offset:flush_offset + `THREADS - 1]),
.din(flush),
.dout(flush_q)
);
assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scan_in};
assign scan_out = sov[0];
endmodule |
module yuv2rgb(
input clk,
input [7:0] y_in,
input [7:0] u_in,
input [7:0] v_in,
input vs_in,
input hs_in,
input de_in,
output [7:0] r_out,
output [7:0] g_out,
output [7:0] b_out,
output vs_out,
output hs_out,
output de_out
);
reg[17: 0] mult_y_for_r_18b=0;
reg[17: 0] mult_y_for_g_18b=0;
reg[17: 0] mult_y_for_b_18b=0;
reg[17: 0] mult_u_for_r_18b=0;
reg[17: 0] mult_u_for_g_18b=0;
reg[17: 0] mult_u_for_b_18b=0;
reg[17: 0] mult_v_for_r_18b=0;
reg[17: 0] mult_v_for_g_18b=0;
reg[17: 0] mult_v_for_b_18b=0;
reg[17: 0] add_r_0_18b=0;
reg[17: 0] add_g_0_18b=0;
reg[17: 0] add_b_0_18b=0;
reg[17: 0] add_r_1_18b=0;
reg[17: 0] add_g_1_18b=0;
reg[17: 0] add_b_1_18b=0;
reg[17: 0] result_r_18b=0;
reg[17: 0] result_g_18b=0;
reg[17: 0] result_b_18b=0;
reg[9:0] r_tmp=0;
reg[9:0] g_tmp=0;
reg[9:0] b_tmp=0;
reg vs_r;
reg hs_r;
reg de_r;
reg vs_r2;
reg hs_r2;
reg de_r2;
reg vs_r3;
reg hs_r3;
reg de_r3;
reg vs_r4;
reg hs_r4;
reg de_r4;
/*----------------Ò»¼¶Á÷Ë®-³Ë·¨--------------*/
always @(posedge clk)begin
mult_y_for_r_18b <= ((y_in<<8));
mult_y_for_g_18b <= ((y_in<<8));
mult_y_for_b_18b <= ((y_in<<8));
end
always @(posedge clk)begin
mult_u_for_r_18b <= 18'b0;
mult_u_for_g_18b <= ((u_in<<6)+(u_in<<4)+(u_in<<3));
mult_u_for_b_18b <= ((u_in<<8)+(u_in<<7)+(u_in<<6)+(u_in<<2)+(u_in<<1));
end
always @(posedge clk)begin
mult_v_for_r_18b <= ((v_in<<8)+(v_in<<6)+(v_in<<5)+(v_in<<2)+(v_in<<1)+(v_in));
mult_v_for_g_18b <= ((v_in<<7)+(v_in<<5)+(v_in<<4)+(v_in<<2)+(v_in<<1)+(v_in));
mult_v_for_b_18b <= 0;
end
always @(posedge clk)begin
vs_r <= vs_in;
hs_r <= hs_in;
de_r <= de_in;
vs_r2 <= vs_r;
hs_r2 <= hs_r;
de_r2 <= de_r;
vs_r3 <= vs_r2;
hs_r3 <= hs_r2;
de_r3 <= de_r2;
vs_r4 <= vs_r3;
hs_r4 <= hs_r3;
de_r4 <= de_r3;
end
/*---------------¶þ¼¶Á÷Ë®-·ÖÕý¸ºÏî¼Ó--------------*/
always @(posedge clk)begin
add_r_0_18b <= mult_y_for_r_18b + mult_u_for_r_18b + mult_v_for_r_18b;//+
add_r_1_18b <= 45940;//-
end
always @(posedge clk)begin
add_g_0_18b <= mult_y_for_g_18b + 34678;//+
add_g_1_18b <= mult_u_for_g_18b + mult_v_for_g_18b;//-
end
always @(posedge clk)begin
add_b_0_18b <= mult_y_for_b_18b + mult_u_for_b_18b + mult_v_for_b_18b;//+
add_b_1_18b <= 58065;//-
end
/*---------------Èý¼¶Á÷Ë®-ÇóºÍ--------------*/
assign sign_r = (add_r_0_18b >= add_r_1_18b);
assign sign_g = (add_g_0_18b >= add_g_1_18b);
assign sign_b = (add_b_0_18b >= add_b_1_18b);
always @(posedge clk)begin
result_r_18b <= sign_r ? (add_r_0_18b - add_r_1_18b) : 18'd0;
result_g_18b <= sign_g ? (add_g_0_18b - add_g_1_18b) : 18'd0;
result_b_18b <= sign_b ? (add_b_0_18b - add_b_1_18b) : 18'd0;
end
/*---------------Ëļ¶Á÷Ë®-½øλ±íʾ--------------*/
always @(posedge clk)
begin
r_tmp <= result_r_18b[15:8] + {9'd0,result_r_18b[7]};
g_tmp <= result_g_18b[15:8] + {9'd0,result_g_18b[7]};
b_tmp <= result_b_18b[15:8] + {9'd0,result_b_18b[7]};
end
/*----Êä³ö----*/
assign r_out = (r_tmp[9:8] == 2'b00) ? r_tmp[7 : 0] : 8'hFF;
assign g_out = (g_tmp[9:8] == 2'b00) ? g_tmp[7 : 0] : 8'hFF;
assign b_out = (b_tmp[9:8] == 2'b00) ? b_tmp[7 : 0] : 8'hFF;
assign vs_out = vs_r4;
assign hs_out = hs_r4;
assign de_out = de_r4;
endmodule |
module eth_img_rec
#(
parameter integer PIXEL_WIDTH = 32 ,
parameter integer VIDEO_LENGTH = 16'd960 ,
parameter integer VIDEO_HIGTH = 16'd540
)
(
input wire eth_rx_clk ,
input wire rstn ,
input wire [PIXEL_WIDTH - 1 : 0] udp_date_rcev /* synthesis PAP_MARK_DEBUG="1" */,
input wire udp_date_en ,
output reg img_data_en /* synthesis PAP_MARK_DEBUG="1" */,
output reg img_data_vs /* synthesis PAP_MARK_DEBUG="1" */,
output reg [15 : 0] img_data /* synthesis PAP_MARK_DEBUG="1" */
);
//~~~~~~~~~~~~~~~~~~~~~~~parameter~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
parameter ETH_RX_WAIT_HEAD_0 = 2'd0 ;//µÈ´ýÖ¡Æðʼ±ê־λ
parameter ETH_RX_WAIT_HEAD_1 = 2'd1 ;//µÈ´ý·Ö±æÂÊ
parameter ETH_RX_RECV_DATA = 2'd2 ;//µÈ´ýÊý¾Ý´«Êä
//parameter ETH_RX_END = 2'b1000 ;
//~~~~~~~~~~~~~~~~~~~~~~~reg~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
reg [PIXEL_WIDTH - 1 : 0] udp_date_rcev_d0;
reg [3 : 0] eth_rx_state/* synthesis PAP_MARK_DEBUG="1" */;
reg [3 : 0] eth_rx_next_state/* synthesis PAP_MARK_DEBUG="1" */;
reg skip_en /* synthesis PAP_MARK_DEBUG="1" */;
reg error_en/* synthesis PAP_MARK_DEBUG="1" */;
reg img_recv_start/* synthesis PAP_MARK_DEBUG="1" */;
reg [20 : 0] img_data_recv_cnt/* synthesis PAP_MARK_DEBUG="1" */;
reg img_data_en_cnt/* synthesis PAP_MARK_DEBUG="1" */;
//~~~~~~~~~~~~~~~~~~~~~~~wire~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//~~~~~~~~~~~~~~~~~~~~~~~assign~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//~~~~~~~~~~~~~~~~~~~~~~~always~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//always @(posedge eth_rx_clk ) begin
// if(!rstn) begin
// udp_date_rcev_d0 <= 'd0;
// end
// else if(udp_date_rcev) begin
// udp_date_rcev_d0 <= udp_date_rcev;
// end
//end
always @(posedge eth_rx_clk ) begin
if(!rstn) begin
skip_en <= 'd0;
error_en <= 'd0;
img_data <= 'd0;
img_data_vs <= 'd0;
img_recv_start <= 'd0;
img_data_recv_cnt <= 'd0;
eth_rx_state <= ETH_RX_WAIT_HEAD_0;
img_data_en_cnt <= 'd0;
end
else begin
//skip_en <= 'd0;
//error_en <= 'd0;
img_data_en <= 'd0;
case(eth_rx_state)
ETH_RX_WAIT_HEAD_0: begin
img_data_recv_cnt <= 'd0;
img_data_en_cnt <= 'd0;
if(udp_date_en && udp_date_rcev == {32'hf0_5a_a5_0f}) begin//½ÓÊÕµ½Ö¡Í·£¬½øÈëµÈ´ý״̬2
eth_rx_state <= ETH_RX_WAIT_HEAD_1;
img_data_vs <= 'd1;//½ÓÊÕµ½Ö¡Í·Ê±£¬À¸ßvsÐźÅÒÔ¹©ÆäËûÄ£¿é¸´Î»
end
else begin
eth_rx_state <= ETH_RX_WAIT_HEAD_0;
end
end
ETH_RX_WAIT_HEAD_1: begin
if(udp_date_en && udp_date_rcev == {16'd960,16'd540}) begin//½ÓÊÕµ½·Ö±æÂÊÐÅÏ¢£¬½øÈë½ÓÊÕÊý¾Ý״̬
eth_rx_state <= ETH_RX_RECV_DATA;
img_data_vs <= 'd0;
end
else if(udp_date_en && udp_date_rcev != {16'd960,16'd540})begin//Èç¹ûµÚ¶þ¸öÊý¾Ý²»ÊÇ·Ö±æÂÊÔòÀ¸ßerror£¬ÖØеȴýÖ¡Í·
eth_rx_state <= ETH_RX_WAIT_HEAD_0;
img_data_vs <= 'd0;
end
else begin
eth_rx_state <= ETH_RX_WAIT_HEAD_1;
end
end
ETH_RX_RECV_DATA: begin
if(udp_date_en) begin
img_recv_start <= 'd1;
end
if(udp_date_en || img_recv_start) begin
img_data_recv_cnt <= img_data_recv_cnt + 'd1;
if(img_data_en_cnt == 'd0) begin//µÚһϽ«udpÊý¾Ý¸ß16λת»¯Îª32bits¸ñʽrgb565
//img_data[31 : 27] <= udp_date_rcev[31 : 27];
//img_data[21 : 16] <= udp_date_rcev[26 : 21];
//img_data[11 : 7] <= udp_date_rcev[20 : 16];
img_data[15 : 11] <= udp_date_rcev[31 : 27];
img_data[10 : 5] <= udp_date_rcev[26 : 21];
img_data[4 : 0] <= udp_date_rcev[20 : 16];
img_data_en <= 'd1;
img_data_en_cnt <= 'd1;
end
else if(img_data_en_cnt == 'd1) begin//µÚ¶þϽ«udpÊý¾ÝµÍ16λת»¯Îª32bits¸ñʽrgb565
//img_data[31 : 27] <= udp_date_rcev[15 : 11];
//img_data[21 : 16] <= udp_date_rcev[10 : 5];
//img_data[11 : 7] <= udp_date_rcev[4 : 0];
img_data[15 : 11] <= udp_date_rcev[15 : 11];
img_data[10 : 5] <= udp_date_rcev[10 : 5];
img_data[4 : 0] <= udp_date_rcev[4 : 0];
img_data_en <= 'd1;
img_recv_start <= 'd0;
img_data_en_cnt <= 'd0;
end
end
if(img_data_recv_cnt == 960*540) begin//½ÓÊÕµ½960*540¸öÏñËغó½áÊøÒ»Ö¡½ÓÊÕ
eth_rx_state <= ETH_RX_WAIT_HEAD_0;
end
end
endcase
end
end
//always @(posedge eth_rx_clk) begin
// if(!rstn) begin
// eth_rx_cur_state <= ETH_RX_WAIT_HEAD_0;
// end
// else begin
// eth_rx_cur_state <= eth_rx_next_state;
// end
//end
//always @(*) begin
// case(eth_rx_cur_state)
// ETH_RX_WAIT_HEAD_0: begin
// if(udp_date_en && udp_date_rcev == {32'hf0_5a_a5_0f}) begin
// eth_rx_next_state = ETH_RX_WAIT_HEAD_1;
// end
// else begin
// eth_rx_next_state = ETH_RX_WAIT_HEAD_0;
// end
// end
// ETH_RX_WAIT_HEAD_1: begin
// if(udp_date_en && udp_date_rcev == 32'h03c0_021c) begin
// eth_rx_next_state = ETH_RX_RECV_DATA;
// end
// else if(udp_date_en && udp_date_rcev != {16'd960,16'd540}) begin
// eth_rx_next_state = ETH_RX_WAIT_HEAD_0;
// end
// else begin
// eth_rx_next_state = ETH_RX_WAIT_HEAD_1;
// end
// end
// ETH_RX_RECV_DATA: begin
// if(img_data_recv_cnt == 'd518400) begin
// eth_rx_next_state = ETH_RX_WAIT_HEAD_0;
// end
// else begin
// eth_rx_next_state = ETH_RX_RECV_DATA;
// end
// end
// default: begin
// eth_rx_next_state = ETH_RX_WAIT_HEAD_0;
// end
// endcase
//end
endmodule |
module i2c_com(clock_i2c , //i2c控制接口传输所需时钟，0-400khz，此处为20khz
camera_rstn ,
ack , //应答信号
i2c_data , //sdin接口传输的32位数据
start , //开始传输标志
tr_end , //传输结束标志
i2c_sclk , //FPGA与camera iic时钟接口
i2c_sdat //FPGA与camera iic数据接口
);
input [31:0]i2c_data;
input camera_rstn;
input clock_i2c;
output ack;
input start;
output tr_end;
output i2c_sclk;
inout i2c_sdat;
reg [5:0] cyc_count;
reg reg_sdat;
reg sclk;
reg ack1,ack2,ack3;
reg tr_end;
wire i2c_sclk;
wire i2c_sdat;
wire ack;
assign ack=ack1|ack2|ack3;
assign i2c_sclk=sclk|(((cyc_count>=4)&(cyc_count<=39))?~clock_i2c:0);
assign i2c_sdat=reg_sdat?1'bz:0;
always@(posedge clock_i2c)
begin
if(!camera_rstn)
cyc_count<=6'b111111;
else
begin
if(start==0)
cyc_count<=0;
else if(cyc_count<6'b111111)
cyc_count<=cyc_count+1;
end
end
always@(posedge clock_i2c)
begin
if(!camera_rstn)
begin
tr_end<=0;
ack1<=1;
ack2<=1;
ack3<=1;
sclk<=1;
reg_sdat<=1;
end
else
case(cyc_count)
0:begin ack1<=1;ack2<=1;ack3<=1;tr_end<=0;sclk<=1;reg_sdat<=1;end
1:reg_sdat<=0; //开始传输
2:sclk<=0;
3:reg_sdat<=i2c_data[31];
4:reg_sdat<=i2c_data[30];
5:reg_sdat<=i2c_data[29];
6:reg_sdat<=i2c_data[28];
7:reg_sdat<=i2c_data[27];
8:reg_sdat<=i2c_data[26];
9:reg_sdat<=i2c_data[25];
10:reg_sdat<=i2c_data[24];
11:reg_sdat<=1; //应答信号
12:begin reg_sdat<=i2c_data[23];ack1<=i2c_sdat;end
13:reg_sdat<=i2c_data[22];
14:reg_sdat<=i2c_data[21];
15:reg_sdat<=i2c_data[20];
16:reg_sdat<=i2c_data[19];
17:reg_sdat<=i2c_data[18];
18:reg_sdat<=i2c_data[17];
19:reg_sdat<=i2c_data[16];
20:reg_sdat<=1; //应答信号
21:begin reg_sdat<=i2c_data[15];ack1<=i2c_sdat;end
22:reg_sdat<=i2c_data[14];
23:reg_sdat<=i2c_data[13];
24:reg_sdat<=i2c_data[12];
25:reg_sdat<=i2c_data[11];
26:reg_sdat<=i2c_data[10];
27:reg_sdat<=i2c_data[9];
28:reg_sdat<=i2c_data[8];
29:reg_sdat<=1; //应答信号
30:begin reg_sdat<=i2c_data[7];ack2<=i2c_sdat;end
31:reg_sdat<=i2c_data[6];
32:reg_sdat<=i2c_data[5];
33:reg_sdat<=i2c_data[4];
34:reg_sdat<=i2c_data[3];
35:reg_sdat<=i2c_data[2];
36:reg_sdat<=i2c_data[1];
37:reg_sdat<=i2c_data[0];
38:reg_sdat<=1; //应答信号
39:begin ack3<=i2c_sdat;sclk<=0;reg_sdat<=0;end
40:sclk<=1;
41:begin reg_sdat<=1;tr_end<=1;end
endcase
end
endmodule |
module rw_fifo_ctrl(
input wire rstn ,//ϵͳ¸´Î»
input wire ddr_clk ,//дÈëÄÚ´æµÄʱÖÓ£¨ÄÚ´æaxi4½Ó¿ÚʱÖÓ£©
//дfifo
input wire wfifo_wr_clk ,//wfifoдʱÖÓ
input wire wfifo_wr_en /* synthesis PAP_MARK_DEBUG="1" */,//wfifoÊäÈëʹÄÜ
input wire [31 : 0] wfifo_wr_data32_in /* synthesis PAP_MARK_DEBUG="1" */,//wfifoÊäÈëÊý¾Ý,16bits
input wire wfifo_rd_req /* synthesis PAP_MARK_DEBUG="1" */,//wfifo¶ÁÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
//input wire wfifo_pre_rd_req /* synthesis PAP_MARK_DEBUG="1" */,
output wire [8 : 0] wfifo_rd_water_level /* synthesis PAP_MARK_DEBUG="1" */,//wfifo¶Áˮ룬µ±ÊýÁ¿´óÓÚÍ»·¢³¤¶Èʱ¿ªÊ¼´«Êä
output wire [255 : 0] wfifo_rd_data256_out /* synthesis PAP_MARK_DEBUG="1" */,//wfifo¶ÁÊý¾Ý£¬256bits
//¶Áfifo
input wire rfifo_rd_clk ,//rfifo¶ÁʱÖÓ
input wire rfifo_rd_en /* synthesis PAP_MARK_DEBUG="1" */,//rfifoÊäÈëʹÄÜ
output wire [31 : 0] rfifo_rd_data32_out /* synthesis PAP_MARK_DEBUG="1" */,//rfifoÊäÈëÊý¾Ý,16bits
input wire rfifo_wr_req /* synthesis PAP_MARK_DEBUG="1" */,//rfifoдÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
output wire [8 : 0] rfifo_wr_water_level /* synthesis PAP_MARK_DEBUG="1" */,//rfifoдˮ룬µ±ÊýÁ¿Ð¡ÓÚÍ»·¢³¤¶Èʱ¿ªÊ¼´«Êä
input wire [255 : 0] rfifo_wr_data256_in /* synthesis PAP_MARK_DEBUG="1" */, //rfifoдÊý¾Ý£¬256bits
//¸´Î»ÐźÅ
input wire vs_in ,
input wire vs_out
);
//²ÎÊý********************************************************
//wire********************************************************
//reg********************************************************
//¸´Î»ÐźÅ
reg r_vs_in_d0;
reg [15 : 0] r_vs_in_d1;
reg r_vs_out_d0;
reg [15 : 0] r_vs_out_d1;
reg r_wr_rst/* synthesis PAP_MARK_DEBUG="1" */;
reg r_rd_rst/* synthesis PAP_MARK_DEBUG="1" */;
//×éºÏÂß¼********************************************************
//дfifo¸´Î»
always @(posedge wfifo_wr_clk ) begin
if(!rstn ) begin
r_vs_in_d0 <= 'd0;
end
else begin
r_vs_in_d0 <= vs_in;
end
end
//λÒƼĴæ
always @(posedge wfifo_wr_clk ) begin
if(!rstn ) begin
r_vs_in_d1 <= 'd0;
end
else begin
r_vs_in_d1 <= {r_vs_in_d1[14:0],r_vs_in_d0};
end
end
//²úÉúÒ»¶Î¶àÖÜÆÚ¸´Î»µçƽ£¬Âú×ãfifo¸´Î»Ê±Ðò
always @(posedge wfifo_wr_clk ) begin
if(!rstn)
r_wr_rst <= 1'b0;
else if(r_vs_in_d1[0] && !r_vs_in_d1[14])
r_wr_rst <= 1'b1;
else
r_wr_rst <= 1'b0;
end
//¶Áfifo¸´Î»
always @(posedge rfifo_rd_clk ) begin
if(!rstn ) begin
r_vs_out_d0 <= 'd0;
end
else begin
r_vs_out_d0 <= vs_out;
end
end
//λÒƼĴæ
always @(posedge rfifo_rd_clk ) begin
if(!rstn ) begin
r_vs_out_d1 <= 'd0;
end
else begin
r_vs_out_d1 <= {r_vs_out_d1[14:0],r_vs_out_d0};
end
end
//²úÉúÒ»¶Î¶àÖÜÆÚ¸´Î»µçƽ£¬Âú×ãfifo¸´Î»Ê±Ðò
always @(posedge rfifo_rd_clk ) begin
if(!rstn)
r_rd_rst <= 1'b0;
else if(r_vs_out_d1[0] && !r_vs_out_d1[14])
r_rd_rst <= 1'b1;
else
r_rd_rst <= 1'b0;
end
//״̬»ú********************************************************
//Àý»¯********************************************************
write_ddr_fifo user_write_ddr_fifo (
.wr_clk (wfifo_wr_clk ),// input
.wr_rst (~rstn | r_wr_rst ),// input
.wr_en (wfifo_wr_en ),// input
.wr_data (wfifo_wr_data32_in ),// input [31:0]
.wr_full ( ),// output
.wr_water_level ( ),// output [11:0]
.almost_full ( ),// output
.rd_clk (ddr_clk ),// input
.rd_rst (~rstn | r_wr_rst ),// input
.rd_en (wfifo_rd_req ),// input
.rd_data (wfifo_rd_data256_out),// output [255:0]
.rd_empty ( ),// output
.rd_water_level (wfifo_rd_water_level),// output [8:0]
.almost_empty ( ) // output
);
read_ddr_fifo user_read_ddr_fifo (
.wr_clk (ddr_clk ),// input
.wr_rst (~rstn | r_rd_rst ),// input
.wr_en (rfifo_wr_req ),// input
.wr_data (rfifo_wr_data256_in ),// input [255:0]
.wr_full ( ),// output
.wr_water_level (rfifo_wr_water_level),// output [8:0]
.almost_full ( ),// output
.rd_clk (rfifo_rd_clk ),// input
.rd_rst (~rstn | r_rd_rst ),// input
.rd_en (rfifo_rd_en ),// input
.rd_data (rfifo_rd_data32_out ),// output [31:0]
.rd_empty ( ),// output
.rd_water_level ( ),// output [11:0]
.almost_empty ( ) // output
);
endmodule |
module rgb2yuv(
input clk,
input [7:0] r_in,
input [7:0] g_in,
input [7:0] b_in,
input vs_in,
input hs_in,
input de_in,
output [7:0] y_out,
output [7:0] u_out,
output [7:0] v_out,
output vs_out,
output hs_out,
output de_out,
input wire [7 : 0] video_enhance_lightdown_num/* synthesis PAP_MARK_DEBUG="1" */,
input wire video_enhance_lightdown_sw /* synthesis PAP_MARK_DEBUG="1" */,
input wire [7 : 0] video_enhance_darkup_num /* synthesis PAP_MARK_DEBUG="1" */,
input wire video_enhance_darkup_sw /* synthesis PAP_MARK_DEBUG="1" */
);
reg[15: 0] mult_r_for_y_16b=0;
reg[15: 0] mult_r_for_u_16b=0;
reg[15: 0] mult_r_for_v_16b=0;
reg[15: 0] mult_g_for_y_16b=0;
reg[15: 0] mult_g_for_u_16b=0;
reg[15: 0] mult_g_for_v_16b=0;
reg[15: 0] mult_b_for_y_16b=0;
reg[15: 0] mult_b_for_u_16b=0;
reg[15: 0] mult_b_for_v_16b=0;
reg[15: 0] add_y_16b=0;
reg[15: 0] add_u_16b=0;
reg[15: 0] add_v_16b=0;
reg[15:0] y_tmp=0/* synthesis PAP_MARK_DEBUG="1" */;
reg[7:0] u_tmp=0;
reg[7:0] v_tmp=0;
reg vs_r/* synthesis PAP_MARK_DEBUG="1" */;
reg hs_r/* synthesis PAP_MARK_DEBUG="1" */;
reg de_r/* synthesis PAP_MARK_DEBUG="1" */;
reg vs_r2/* synthesis PAP_MARK_DEBUG="1" */;
reg hs_r2/* synthesis PAP_MARK_DEBUG="1" */;
reg de_r2/* synthesis PAP_MARK_DEBUG="1" */;
reg vs_r3/* synthesis PAP_MARK_DEBUG="1" */;
reg hs_r3/* synthesis PAP_MARK_DEBUG="1" */;
reg de_r3/* synthesis PAP_MARK_DEBUG="1" */;
wire y_big;
wire [4:0]add/* synthesis PAP_MARK_DEBUG="1" */;
wire [4:0]sub/* synthesis PAP_MARK_DEBUG="1" */;
/*----------------Ò»¼¶Á÷Ë®-³Ë·¨--------------*/
always @(posedge clk)begin
mult_r_for_y_16b <= ((r_in<<6)+(r_in<<3)+(r_in<<2)+(r_in));
mult_r_for_u_16b <= ((r_in<<5)+(r_in<<3)+(r_in<<1)+(r_in));
mult_r_for_v_16b <= ((r_in<<7));
end
always @(posedge clk)begin
mult_g_for_y_16b <= ((g_in<<7)+(g_in<<4)+(g_in<<2)+(g_in<<1));
mult_g_for_u_16b <= ((g_in<<6)+(g_in<<4)+(g_in<<2)+(g_in));
mult_g_for_v_16b <= ((g_in<<6)+(g_in<<5)+(g_in<<3)+(g_in<<1)+(g_in));
end
always @(posedge clk)begin
mult_b_for_y_16b <= ((b_in<<4)+(b_in<<3)+(b_in<<2)+(b_in));
mult_b_for_u_16b <= ((b_in<<7));
mult_b_for_v_16b <= ((b_in<<4)+(b_in<<2)+(b_in));
end
always @(posedge clk)begin
vs_r <= vs_in;
hs_r <= hs_in;
de_r <= de_in;
vs_r2 <= vs_r;
hs_r2 <= hs_r;
de_r2 <= de_r;
vs_r3 <= vs_r2;
hs_r3 <= hs_r2;
de_r3 <= de_r2;
end
/*---------------¶þ¼¶Á÷Ë®-·ÖÕý¸ºÏî¼Ó--------------*/
always @(posedge clk)begin
add_y_16b <= mult_r_for_y_16b + mult_g_for_y_16b + mult_b_for_y_16b;
end
always @(posedge clk)begin
add_u_16b <= - mult_r_for_u_16b - mult_g_for_u_16b + mult_b_for_u_16b + 32768;
end
always @(posedge clk)begin
add_v_16b <= mult_r_for_v_16b - mult_g_for_v_16b - mult_b_for_v_16b + 32768;
end
/*---------------Èý¼¶Á÷Ë®-½øλ±íʾ--------------*/
always @(posedge clk)
begin
y_tmp <= add_y_16b[15:8] + {7'd0,add_y_16b[7]};
//y_tmp <= add_y_16b[15:8] * add_y_16b[15:8];
u_tmp <= add_u_16b[15:8] + {7'd0,add_u_16b[7]};
v_tmp <= add_v_16b[15:8] + {7'd0,add_v_16b[7]};
end
/*----Êä³ö----*/
assign add = video_enhance_darkup_sw ? ((y_tmp[7:0] > video_enhance_darkup_num ) ? 0 : ((video_enhance_darkup_num - y_tmp[7:0])>>3)) : 0;
assign sub = video_enhance_lightdown_sw ? ((y_tmp[7:0] < video_enhance_lightdown_num) ? 0 : ((y_tmp[7:0] - video_enhance_lightdown_num)>>3)) : 0;
//assign y_out = (y_tmp <= 128) ? y_tmp[7:0]+8'b0001_0000 : y_tmp[7:0]-8'b0001_0000;
//assign y_out = (y_tmp[7:0] > 222) ? y_tmp[7:0] : y_tmp[7:0] + 32;
//assign y_out = y_tmp[7:0];
assign y_out = y_tmp[7:0] + add - sub;//;
assign u_out = u_tmp[7:0];
assign v_out = v_tmp[7:0];
assign vs_out = vs_r3;
assign hs_out = hs_r3;
assign de_out = de_r3;
endmodule |
module ov5640_power_on_delay(
input clk_50M ,
input reset_n ,
output camera1_rstn ,
output camera2_rstn ,
output camera_pwnd ,
output reg initial_en
);
reg [18:0]cnt1;
reg [15:0]cnt2;
reg [19:0]cnt3;
reg camera_rstn_reg;
reg camera_pwnd_reg;
assign camera1_rstn=camera_rstn_reg;
assign camera2_rstn=camera_rstn_reg;
assign camera_pwnd=camera_pwnd_reg;
//5ms, delay from sensor power up stable to Pwdn pull down
always@(posedge clk_50M)begin
if(reset_n==1'b0) begin
cnt1<=0;
camera_pwnd_reg<=1'b1;// 1'b1
end
else if(cnt1<19'h40000) begin
cnt1<=cnt1+1'b1;
camera_pwnd_reg<=1'b1;
end
else
camera_pwnd_reg<=1'b0;
end
//1.3ms, delay from pwdn low to resetb pull up
always@(posedge clk_50M)begin
if(camera_pwnd_reg==1) begin
cnt2<=0;
camera_rstn_reg<=1'b0;
end
else if(cnt2<16'hffff) begin
cnt2<=cnt2+1'b1;
camera_rstn_reg<=1'b0;
end
else
camera_rstn_reg<=1'b1;
end
//21ms, delay from resetb pul high to SCCB initialization
always@(posedge clk_50M)begin
if(camera_rstn_reg==0) begin
cnt3<=0;
initial_en<=1'b0;
end
else if(cnt3<20'hfffff) begin
cnt3<=cnt3+1'b1;
initial_en<=1'b0;
end
else
initial_en<=1'b1;
end
endmodule |
module ms7200_ctrl(
input clk,
input rstn,
output reg init_over,
output [7:0] device_id,
output reg iic_trig ,
output reg w_r ,
output reg [15:0] addr ,
output reg [ 7:0] data_in ,
input busy ,
input [ 7:0] data_out ,
input byte_over
);
assign device_id = 8'h56;
function [23:0] cmd_data;
input [9:0] index;
begin
case(index)
9'd0 : cmd_data = {16'h0204, 8'h02};
9'd1 : cmd_data = {16'h0205, 8'h40};
9'd2 : cmd_data = {16'h0004, 8'h01};
9'd3 : cmd_data = {16'h0009, 8'h26};
9'd4 : cmd_data = {16'h102E, 8'h01};
9'd5 : cmd_data = {16'h1025, 8'hB0};
9'd6 : cmd_data = {16'h102D, 8'h83};
9'd7 : cmd_data = {16'h1000, 8'h20};
9'd8 : cmd_data = {16'h100F, 8'h04};
9'd9 : cmd_data = {16'h0003, 8'hC3};
9'd10 : cmd_data = {16'h103B, 8'h02};
9'd11 : cmd_data = {16'h00E1, 8'h00};
9'd12 : cmd_data = {16'h00A8, 8'h08};
9'd13 : cmd_data = {16'h000A, 8'h00};
9'd14 : cmd_data = {16'h0016, 8'h02};
9'd15 : cmd_data = {16'h00E2, 8'h01};
9'd16 : cmd_data = {16'h00C2, 8'h14};
9'd17 : cmd_data = {16'h102D, 8'hC7};
9'd18 : cmd_data = {16'h1005, 8'h04};
9'd19 : cmd_data = {16'h1003, 8'h14};
9'd20 : cmd_data = {16'h1004, 8'h01};
9'd21 : cmd_data = {16'h1000, 8'h60};
9'd22 : cmd_data = {16'h1020, 8'h13};
9'd23 : cmd_data = {16'h1021, 8'h04};
9'd24 : cmd_data = {16'h1022, 8'h04};
9'd25 : cmd_data = {16'h1023, 8'h0C};
9'd26 : cmd_data = {16'h102B, 8'h33};
9'd27 : cmd_data = {16'h102C, 8'h33};
9'd28 : cmd_data = {16'h00F0, 8'h10};
9'd29 : cmd_data = {16'h000C, 8'h80};
9'd30 : cmd_data = {16'h0D00, 8'h00};
9'd31 : cmd_data = {16'h0D01, 8'hFF};
9'd32 : cmd_data = {16'h0D02, 8'hFF};
9'd33 : cmd_data = {16'h0D03, 8'hFF};
9'd34 : cmd_data = {16'h0D04, 8'hFF};
9'd35 : cmd_data = {16'h0D05, 8'hFF};
9'd36 : cmd_data = {16'h0D06, 8'hFF};
9'd37 : cmd_data = {16'h0D07, 8'h00};
9'd38 : cmd_data = {16'h0D00, 8'h00};
9'd39 : cmd_data = {16'h0D01, 8'hFF};
9'd40 : cmd_data = {16'h0D02, 8'hFF};
9'd41 : cmd_data = {16'h0D03, 8'hFF};
9'd42 : cmd_data = {16'h0D04, 8'hFF};
9'd43 : cmd_data = {16'h0D05, 8'hFF};
9'd44 : cmd_data = {16'h0D06, 8'hFF};
9'd45 : cmd_data = {16'h0D07, 8'h00};
9'd46 : cmd_data = {16'h0D08, 8'h4C};
9'd47 : cmd_data = {16'h0D09, 8'h2D};
9'd48 : cmd_data = {16'h0D0A, 8'hFF};
9'd49 : cmd_data = {16'h0D0B, 8'h0D};
9'd50 : cmd_data = {16'h0D0C, 8'h58};
9'd51 : cmd_data = {16'h0D0D, 8'h4D};
9'd52 : cmd_data = {16'h0D0E, 8'h51};
9'd53 : cmd_data = {16'h0D0F, 8'h30};
9'd54 : cmd_data = {16'h0D10, 8'h1C};
9'd55 : cmd_data = {16'h0D11, 8'h1C};
9'd56 : cmd_data = {16'h0D12, 8'h01};
9'd57 : cmd_data = {16'h0D13, 8'h03};
9'd58 : cmd_data = {16'h0D14, 8'h80};
9'd59 : cmd_data = {16'h0D15, 8'h3D};
9'd60 : cmd_data = {16'h0D16, 8'h23};
9'd61 : cmd_data = {16'h0D17, 8'h78};
9'd62 : cmd_data = {16'h0D18, 8'h2A};
9'd63 : cmd_data = {16'h0D19, 8'h5F};
9'd64 : cmd_data = {16'h0D1A, 8'hB1};
9'd65 : cmd_data = {16'h0D1B, 8'hA2};
9'd66 : cmd_data = {16'h0D1C, 8'h57};
9'd67 : cmd_data = {16'h0D1D, 8'h4F};
9'd68 : cmd_data = {16'h0D1E, 8'hA2};
9'd69 : cmd_data = {16'h0D1F, 8'h28};
9'd70 : cmd_data = {16'h0D20, 8'h0F};
9'd71 : cmd_data = {16'h0D21, 8'h50};
9'd72 : cmd_data = {16'h0D22, 8'h54};
9'd73 : cmd_data = {16'h0D23, 8'hBF};
9'd74 : cmd_data = {16'h0D24, 8'hEF};
9'd75 : cmd_data = {16'h0D25, 8'h80};
9'd76 : cmd_data = {16'h0D26, 8'h71};
9'd77 : cmd_data = {16'h0D27, 8'h4F};
9'd78 : cmd_data = {16'h0D28, 8'h81};
9'd79 : cmd_data = {16'h0D29, 8'h00};
9'd80 : cmd_data = {16'h0D2A, 8'h81};
9'd81 : cmd_data = {16'h0D2B, 8'hC0};
9'd82 : cmd_data = {16'h0D2C, 8'h81};
9'd83 : cmd_data = {16'h0D2D, 8'h80};
9'd84 : cmd_data = {16'h0D2E, 8'h95};
9'd85 : cmd_data = {16'h0D2F, 8'h00};
9'd86 : cmd_data = {16'h0D30, 8'hA9};
9'd87 : cmd_data = {16'h0D31, 8'hC0};
9'd88 : cmd_data = {16'h0D32, 8'hB3};
9'd89 : cmd_data = {16'h0D33, 8'h00};
9'd90 : cmd_data = {16'h0D34, 8'h01};
9'd91 : cmd_data = {16'h0D35, 8'h01};
9'd92 : cmd_data = {16'h0D36, 8'h04};
9'd93 : cmd_data = {16'h0D37, 8'h74};
9'd94 : cmd_data = {16'h0D38, 8'h00};
9'd95 : cmd_data = {16'h0D39, 8'h30};
9'd96 : cmd_data = {16'h0D3A, 8'hF2};
9'd97 : cmd_data = {16'h0D3B, 8'h70};
9'd98 : cmd_data = {16'h0D3C, 8'h5A};
9'd99 : cmd_data = {16'h0D3D, 8'h80};
9'd100 : cmd_data = {16'h0D3E, 8'hB0};
9'd101 : cmd_data = {16'h0D3F, 8'h58};
9'd102 : cmd_data = {16'h0D40, 8'h8A};
9'd103 : cmd_data = {16'h0D41, 8'h00};
9'd104 : cmd_data = {16'h0D42, 8'h60};
9'd105 : cmd_data = {16'h0D43, 8'h59};
9'd106 : cmd_data = {16'h0D44, 8'h21};
9'd107 : cmd_data = {16'h0D45, 8'h00};
9'd108 : cmd_data = {16'h0D46, 8'h00};
9'd109 : cmd_data = {16'h0D47, 8'h1E};
9'd110 : cmd_data = {16'h0D48, 8'h00};
9'd111 : cmd_data = {16'h0D49, 8'h00};
9'd112 : cmd_data = {16'h0D4A, 8'h00};
9'd113 : cmd_data = {16'h0D4B, 8'hFD};
9'd114 : cmd_data = {16'h0D4C, 8'h00};
9'd115 : cmd_data = {16'h0D4D, 8'h18};
9'd116 : cmd_data = {16'h0D4E, 8'h4B};
9'd117 : cmd_data = {16'h0D4F, 8'h1E};
9'd118 : cmd_data = {16'h0D50, 8'h5A};
9'd119 : cmd_data = {16'h0D51, 8'h1E};
9'd120 : cmd_data = {16'h0D52, 8'h00};
9'd121 : cmd_data = {16'h0D53, 8'h0A};
9'd122 : cmd_data = {16'h0D54, 8'h20};
9'd123 : cmd_data = {16'h0D55, 8'h20};
9'd124 : cmd_data = {16'h0D56, 8'h20};
9'd125 : cmd_data = {16'h0D57, 8'h20};
9'd126 : cmd_data = {16'h0D58, 8'h20};
9'd127 : cmd_data = {16'h0D59, 8'h20};
9'd128 : cmd_data = {16'h0D5A, 8'h00};
9'd129 : cmd_data = {16'h0D5B, 8'h00};
9'd130 : cmd_data = {16'h0D5C, 8'h00};
9'd131 : cmd_data = {16'h0D5D, 8'hFC};
9'd132 : cmd_data = {16'h0D5E, 8'h00};
9'd133 : cmd_data = {16'h0D5F, 8'h55};
9'd134 : cmd_data = {16'h0D60, 8'h32};
9'd135 : cmd_data = {16'h0D61, 8'h38};
9'd136 : cmd_data = {16'h0D62, 8'h48};
9'd137 : cmd_data = {16'h0D63, 8'h37};
9'd138 : cmd_data = {16'h0D64, 8'h35};
9'd139 : cmd_data = {16'h0D65, 8'h78};
9'd140 : cmd_data = {16'h0D66, 8'h0A};
9'd141 : cmd_data = {16'h0D67, 8'h20};
9'd142 : cmd_data = {16'h0D68, 8'h20};
9'd143 : cmd_data = {16'h0D69, 8'h20};
9'd144 : cmd_data = {16'h0D6A, 8'h20};
9'd145 : cmd_data = {16'h0D6B, 8'h20};
9'd146 : cmd_data = {16'h0D6C, 8'h00};
9'd147 : cmd_data = {16'h0D6D, 8'h00};
9'd148 : cmd_data = {16'h0D6E, 8'h00};
9'd149 : cmd_data = {16'h0D6F, 8'hFF};
9'd150 : cmd_data = {16'h0D70, 8'h00};
9'd151 : cmd_data = {16'h0D71, 8'h48};
9'd152 : cmd_data = {16'h0D72, 8'h54};
9'd153 : cmd_data = {16'h0D73, 8'h50};
9'd154 : cmd_data = {16'h0D74, 8'h4B};
9'd155 : cmd_data = {16'h0D75, 8'h37};
9'd156 : cmd_data = {16'h0D76, 8'h30};
9'd157 : cmd_data = {16'h0D77, 8'h30};
9'd158 : cmd_data = {16'h0D78, 8'h30};
9'd159 : cmd_data = {16'h0D79, 8'h35};
9'd160 : cmd_data = {16'h0D7A, 8'h31};
9'd161 : cmd_data = {16'h0D7B, 8'h0A};
9'd162 : cmd_data = {16'h0D7C, 8'h20};
9'd163 : cmd_data = {16'h0D7D, 8'h20};
9'd164 : cmd_data = {16'h0D7E, 8'h01};
9'd165 : cmd_data = {16'h0D7F, 8'hF7};
9'd166 : cmd_data = {16'h0D80, 8'h02};
9'd167 : cmd_data = {16'h0D81, 8'h03};
9'd168 : cmd_data = {16'h0D82, 8'h26};
9'd169 : cmd_data = {16'h0D83, 8'hF0};
9'd170 : cmd_data = {16'h0D84, 8'h4B};
9'd171 : cmd_data = {16'h0D85, 8'h5F};
9'd172 : cmd_data = {16'h0D86, 8'h10};
9'd173 : cmd_data = {16'h0D87, 8'h04};
9'd174 : cmd_data = {16'h0D88, 8'h1F};
9'd175 : cmd_data = {16'h0D89, 8'h13};
9'd176 : cmd_data = {16'h0D8A, 8'h03};
9'd177 : cmd_data = {16'h0D8B, 8'h12};
9'd178 : cmd_data = {16'h0D8C, 8'h20};
9'd179 : cmd_data = {16'h0D8D, 8'h22};
9'd180 : cmd_data = {16'h0D8E, 8'h5E};
9'd181 : cmd_data = {16'h0D8F, 8'h5D};
9'd182 : cmd_data = {16'h0D90, 8'h23};
9'd183 : cmd_data = {16'h0D91, 8'h09};
9'd184 : cmd_data = {16'h0D92, 8'h07};
9'd185 : cmd_data = {16'h0D93, 8'h07};
9'd186 : cmd_data = {16'h0D94, 8'h83};
9'd187 : cmd_data = {16'h0D95, 8'h01};
9'd188 : cmd_data = {16'h0D96, 8'h00};
9'd189 : cmd_data = {16'h0D97, 8'h00};
9'd190 : cmd_data = {16'h0D98, 8'h6D};
9'd191 : cmd_data = {16'h0D99, 8'h03};
9'd192 : cmd_data = {16'h0D9A, 8'h0C};
9'd193 : cmd_data = {16'h0D9B, 8'h00};
9'd194 : cmd_data = {16'h0D9C, 8'h10};
9'd195 : cmd_data = {16'h0D9D, 8'h00};
9'd196 : cmd_data = {16'h0D9E, 8'h80};
9'd197 : cmd_data = {16'h0D9F, 8'h3C};
9'd198 : cmd_data = {16'h0DA0, 8'h20};
9'd199 : cmd_data = {16'h0DA1, 8'h10};
9'd200 : cmd_data = {16'h0DA2, 8'h60};
9'd201 : cmd_data = {16'h0DA3, 8'h01};
9'd202 : cmd_data = {16'h0DA4, 8'h02};
9'd203 : cmd_data = {16'h0DA5, 8'h03};
9'd204 : cmd_data = {16'h0DA6, 8'h02};
9'd205 : cmd_data = {16'h0DA7, 8'h3A};
9'd206 : cmd_data = {16'h0DA8, 8'h80};
9'd207 : cmd_data = {16'h0DA9, 8'h18};
9'd208 : cmd_data = {16'h0DAA, 8'h71};
9'd209 : cmd_data = {16'h0DAB, 8'h38};
9'd210 : cmd_data = {16'h0DAC, 8'h2D};
9'd211 : cmd_data = {16'h0DAD, 8'h40};
9'd212 : cmd_data = {16'h0DAE, 8'h58};
9'd213 : cmd_data = {16'h0DAF, 8'h2C};
9'd214 : cmd_data = {16'h0DB0, 8'h45};
9'd215 : cmd_data = {16'h0DB1, 8'h00};
9'd216 : cmd_data = {16'h0DB2, 8'h60};
9'd217 : cmd_data = {16'h0DB3, 8'h59};
9'd218 : cmd_data = {16'h0DB4, 8'h21};
9'd219 : cmd_data = {16'h0DB5, 8'h00};
9'd220 : cmd_data = {16'h0DB6, 8'h00};
9'd221 : cmd_data = {16'h0DB7, 8'h1E};
9'd222 : cmd_data = {16'h0DB8, 8'h02};
9'd223 : cmd_data = {16'h0DB9, 8'h3A};
9'd224 : cmd_data = {16'h0DBA, 8'h80};
9'd225 : cmd_data = {16'h0DBB, 8'hD0};
9'd226 : cmd_data = {16'h0DBC, 8'h72};
9'd227 : cmd_data = {16'h0DBD, 8'h38};
9'd228 : cmd_data = {16'h0DBE, 8'h2D};
9'd229 : cmd_data = {16'h0DBF, 8'h40};
9'd230 : cmd_data = {16'h0DC0, 8'h10};
9'd231 : cmd_data = {16'h0DC1, 8'h2C};
9'd232 : cmd_data = {16'h0DC2, 8'h45};
9'd233 : cmd_data = {16'h0DC3, 8'h80};
9'd234 : cmd_data = {16'h0DC4, 8'h60};
9'd235 : cmd_data = {16'h0DC5, 8'h59};
9'd236 : cmd_data = {16'h0DC6, 8'h21};
9'd237 : cmd_data = {16'h0DC7, 8'h00};
9'd238 : cmd_data = {16'h0DC8, 8'h00};
9'd239 : cmd_data = {16'h0DC9, 8'h1E};
9'd240 : cmd_data = {16'h0DCA, 8'h01};
9'd241 : cmd_data = {16'h0DCB, 8'h1D};
9'd242 : cmd_data = {16'h0DCC, 8'h00};
9'd243 : cmd_data = {16'h0DCD, 8'h72};
9'd244 : cmd_data = {16'h0DCE, 8'h51};
9'd245 : cmd_data = {16'h0DCF, 8'hD0};
9'd246 : cmd_data = {16'h0DD0, 8'h1E};
9'd247 : cmd_data = {16'h0DD1, 8'h20};
9'd248 : cmd_data = {16'h0DD2, 8'h6E};
9'd249 : cmd_data = {16'h0DD3, 8'h28};
9'd250 : cmd_data = {16'h0DD4, 8'h55};
9'd251 : cmd_data = {16'h0DD5, 8'h00};
9'd252 : cmd_data = {16'h0DD6, 8'h60};
9'd253 : cmd_data = {16'h0DD7, 8'h59};
9'd254 : cmd_data = {16'h0DD8, 8'h21};
9'd255 : cmd_data = {16'h0DD9, 8'h00};
9'd256 : cmd_data = {16'h0DDA, 8'h00};
9'd257 : cmd_data = {16'h0DDB, 8'h1E};
9'd258 : cmd_data = {16'h0DDC, 8'h56};
9'd259 : cmd_data = {16'h0DDD, 8'h5E};
9'd260 : cmd_data = {16'h0DDE, 8'h00};
9'd261 : cmd_data = {16'h0DDF, 8'hA0};
9'd262 : cmd_data = {16'h0DE0, 8'hA0};
9'd263 : cmd_data = {16'h0DE1, 8'hA0};
9'd264 : cmd_data = {16'h0DE2, 8'h29};
9'd265 : cmd_data = {16'h0DE3, 8'h50};
9'd266 : cmd_data = {16'h0DE4, 8'h30};
9'd267 : cmd_data = {16'h0DE5, 8'h20};
9'd268 : cmd_data = {16'h0DE6, 8'h35};
9'd269 : cmd_data = {16'h0DE7, 8'h00};
9'd270 : cmd_data = {16'h0DE8, 8'h60};
9'd271 : cmd_data = {16'h0DE9, 8'h59};
9'd272 : cmd_data = {16'h0DEA, 8'h21};
9'd273 : cmd_data = {16'h0DEB, 8'h00};
9'd274 : cmd_data = {16'h0DEC, 8'h00};
9'd275 : cmd_data = {16'h0DED, 8'h1A};
9'd276 : cmd_data = {16'h0DEE, 8'h00};
9'd277 : cmd_data = {16'h0DEF, 8'h00};
9'd278 : cmd_data = {16'h0DF0, 8'h00};
9'd279 : cmd_data = {16'h0DF1, 8'h00};
9'd280 : cmd_data = {16'h0DF2, 8'h00};
9'd281 : cmd_data = {16'h0DF3, 8'h00};
9'd282 : cmd_data = {16'h0DF4, 8'h00};
9'd283 : cmd_data = {16'h0DF5, 8'h00};
9'd284 : cmd_data = {16'h0DF6, 8'h00};
9'd285 : cmd_data = {16'h0DF7, 8'h00};
9'd286 : cmd_data = {16'h0DF8, 8'h00};
9'd287 : cmd_data = {16'h0DF9, 8'h00};
9'd288 : cmd_data = {16'h0DFA, 8'h00};
9'd289 : cmd_data = {16'h0DFB, 8'h00};
9'd290 : cmd_data = {16'h0DFC, 8'h00};
9'd291 : cmd_data = {16'h0DFD, 8'h00};
9'd292 : cmd_data = {16'h0DFE, 8'h00};
9'd293 : cmd_data = {16'h0DFF, 8'hA8};
9'd294 : cmd_data = {16'h000C, 8'h00};
9'd295 : cmd_data = {16'h000A, 8'h04};
9'd296 : cmd_data = {16'h2000, 8'h0F};
9'd297 : cmd_data = {16'h2001, 8'h00};
9'd298 : cmd_data = {16'h2002, 8'h00};
9'd299 : cmd_data = {16'h2003, 8'h01};
9'd300 : cmd_data = {16'h209C, 8'h00};
9'd301 : cmd_data = {16'h209D, 8'h00};
9'd302 : cmd_data = {16'h209E, 8'h00};
9'd303 : cmd_data = {16'h209F, 8'h00};
9'd304 : cmd_data = {16'h1010, 8'h01};
9'd305 : cmd_data = {16'h1024, 8'h00};
9'd306 : cmd_data = {16'h0200, 8'h00};
9'd307 : cmd_data = {16'h1024, 8'h70};
9'd308 : cmd_data = {16'h0200, 8'h07};
9'd309 : cmd_data = {16'h0215, 8'h01};
9'd310 : cmd_data = {16'h0215, 8'h00};
endcase
end
endfunction
//===========================================================================
// MS7210 driver control FSM
//===========================================================================
parameter IDLE = 7'b000_0001;
parameter CONECT = 7'b000_0010;
parameter INIT = 7'b000_0100;
parameter WAIT = 7'b000_1000;
parameter STA_RD = 7'b001_0000;
parameter SETING = 7'b010_0000;
parameter RD_BAK = 7'b100_0000;
reg [ 6:0] state/*synthesis PAP_MARK_DEBUG="true"*/;
reg [ 6:0] state_n;
reg [ 8:0] dri_cnt;
reg [23:0] delay_cnt;
reg [ 8:0] cmd_index/*synthesis PAP_MARK_DEBUG="true"*/;
reg [31:0] freq_rec/*synthesis PAP_MARK_DEBUG="true"*/;
reg [31:0] freq_rec_1d/*synthesis PAP_MARK_DEBUG="true"*/;
reg [31:0] freq_rec_2d/*synthesis PAP_MARK_DEBUG="true"*/;
reg busy_1d;
wire busy_falling;
assign busy_falling = ((~busy) & busy_1d);
always @(posedge clk)
begin
busy_1d <= busy;
// if(state_n ==STA_RD && dri_cnt == 9'd3 && byte_over)
// begin
freq_rec_1d <= freq_rec;
// end
if(state_n ==STA_RD && dri_cnt == 9'd2 && busy_falling)
begin
freq_rec_2d <= freq_rec_1d;
end
end
reg freq_ensure/*synthesis PAP_MARK_DEBUG="true"*/;
// assign freq_ensure = (freq_rec_1d[17:16]==2'b00) && (freq_rec[17:16] == 2'b10);
always @(posedge clk)
begin
if(!rstn)
freq_ensure <= 1'b0;
else if(state_n == SETING)
freq_ensure <= 1'b0;
else if(state_n ==STA_RD && dri_cnt == 9'd2 && busy_falling && (freq_rec_2d[17:16]==2'b00) && (freq_rec_1d[17:16] == 2'b10))
freq_ensure <= 1'b1;
else
freq_ensure <= freq_ensure;
end
//===========================================================================
// MS7210 driver control FSM First Step
always @(posedge clk)
begin
if(!rstn)
state <= IDLE;
else
state <= state_n;
end
//===========================================================================
// MS7210 driver control FSM Second Step
always @(*)
begin
state_n = state;
case(state)
IDLE : begin //000_0001
state_n = CONECT;
end
CONECT : begin //000_0010
if(dri_cnt == 5'd1 && busy_falling && data_out == 8'h5A)//)//
state_n = INIT;
else
state_n = state;
end
INIT : begin //000_0100
if(dri_cnt == 9'd299 && busy_falling)
state_n = STA_RD;//WAIT;
else
state_n = state;
end
WAIT : begin //000_1000
if(delay_cnt == 24'h989680)//)//
state_n = STA_RD;//RD_BAK;//SETING;//
else
state_n = state;
end
STA_RD : begin //001_0000
if(dri_cnt == 9'd3 && busy_falling && freq_ensure)//freq_rec[15:0] > 16'h5000)
state_n = SETING;//WAIT;//
else
state_n = state;
end
SETING : begin //010_0000
if(dri_cnt == 5'd6 && busy_falling)
state_n = STA_RD;
else
state_n = state;
end
RD_BAK : begin //100_0000
if(dri_cnt == 9'd299 && busy_falling)
state_n = WAIT;
else
state_n = state;
end
default : begin
state_n = IDLE;
end
endcase
end
//===========================================================================
// MS7210 driver control FSM Third Step
always @(posedge clk)
begin
if(!rstn)
dri_cnt <= 5'd0;
else
begin
case(state)
IDLE ,
WAIT : dri_cnt <= 5'd0;
CONECT : begin
if(busy_falling)
begin
if(dri_cnt == 5'd1)
dri_cnt <= 5'd0;
else
dri_cnt <= dri_cnt + 5'd1;
end
else
dri_cnt <= dri_cnt;
end
INIT : begin
if(busy_falling)
begin
if(dri_cnt == 9'd299)
dri_cnt <= 5'd0;
else
dri_cnt <= dri_cnt + 5'd1;
end
else
dri_cnt <= dri_cnt;
end
STA_RD : begin
if(busy_falling)
begin
if(dri_cnt == 5'd3)
dri_cnt <= 5'd0;
else
dri_cnt <= dri_cnt + 5'd1;
end
else
dri_cnt <= dri_cnt;
end
SETING : begin
if(busy_falling)
begin
if(dri_cnt == 5'd6)
dri_cnt <= 5'd0;
else
dri_cnt <= dri_cnt + 5'd1;
end
else
dri_cnt <= dri_cnt;
end
RD_BAK : begin
if(busy_falling)
begin
if(dri_cnt == 9'd299)
dri_cnt <= 5'd0;
else
dri_cnt <= dri_cnt + 5'd1;
end
else
dri_cnt <= dri_cnt;
end
default : dri_cnt <= 5'd0;
endcase
end
end
always @(posedge clk)
begin
if(state == WAIT)
begin
if(delay_cnt == 24'h989680)//)//
delay_cnt <= 22'd0;
else
delay_cnt <= delay_cnt + 22'd1;
end
else
delay_cnt <= 22'd0;
end
always @(posedge clk)
begin
if(!rstn)
iic_trig <= 1'd0;
else
begin
case(state)
IDLE : iic_trig <= 1'b1;
WAIT : iic_trig <= (delay_cnt == 24'h989680);//);//
CONECT ,
INIT ,
SETING ,
RD_BAK ,
STA_RD : iic_trig <= busy_falling;
default : iic_trig <= 1'd0;
endcase
end
end
always @(posedge clk)
begin
if(!rstn)
w_r <= 1'd1;
else
begin
case(state)
IDLE : w_r <= 1'b1;
CONECT : begin
if(dri_cnt == 5'd0 && busy_falling)
w_r <= 1'b0;
else if(dri_cnt == 5'd1 && busy_falling)
w_r <= 1'b1;
else
w_r <= w_r;
end
INIT : begin
if(dri_cnt == 9'd299 && busy_falling)
w_r <= 1'b0;
else
w_r <= w_r;
end
STA_RD : begin
if(dri_cnt == 9'd3 && busy_falling && freq_ensure)//freq_rec[15:0] > 16'h5000)
w_r <= 1'b1;
else
w_r <= w_r;
end
RD_BAK ,
WAIT : w_r <= w_r;
SETING : begin
if(dri_cnt == 5'd6 && busy_falling)
w_r <= 1'b0;
else
w_r <= w_r;
end
default : w_r <= 1'b1;
endcase
end
end
always @(posedge clk)
begin
if(!rstn)
cmd_index <= 6'd0;
else
begin
case(state)
IDLE : cmd_index <= 6'd0;
CONECT : cmd_index <= 6'd0;
INIT : begin
if(byte_over)
begin
// if(dri_cnt == 9'd299)
// cmd_index <= cmd_index - 4'd6;
// else
cmd_index <= cmd_index + 1'b1;
end
else
cmd_index <= cmd_index;
end
WAIT : cmd_index <= cmd_index;
RD_BAK :begin
// if(byte_over)
// cmd_index <= cmd_index + 1'b1;
// else
cmd_index <= cmd_index;
end
SETING ,
STA_RD : begin
// if(byte_over)
// begin
// if(dri_cnt == 9'd3 && freq_rec[15:0] == 0)
// cmd_index <= cmd_index - 3'd3;
// else
// cmd_index <= cmd_index + 1'b1;
// end
// else
cmd_index <= cmd_index;
end
default : cmd_index <= 6'd0;
endcase
end
end
always @(posedge clk)
begin
if(!rstn)
freq_rec <= 31'd0;
else
begin
case(state)
IDLE ,
INIT ,
WAIT ,
RD_BAK ,
CONECT : freq_rec <= freq_rec;
STA_RD : begin
if(byte_over)
begin
case(dri_cnt)
9'd0 : freq_rec <= {freq_rec[31:8],data_out};
9'd1 : freq_rec <= {freq_rec[31:16],data_out,freq_rec[7:0]};
9'd2 : freq_rec <= {freq_rec[31:24],data_out,freq_rec[15:0]};
9'd3 : freq_rec <= {data_out,freq_rec[23:0]};
default : freq_rec <= freq_rec;
endcase
end
else
freq_rec <= freq_rec;
end
SETING : freq_rec <= freq_rec;
default : freq_rec <= 6'd0;
endcase
end
end
reg [23:0] cmd_iic;
always@(posedge clk)
begin
if(~rstn)
cmd_iic <= 0;
else if(state == IDLE)
cmd_iic <= 24'd0;
else //if(state == WAIT || state == SETING)
cmd_iic <= cmd_data(cmd_index);
end
always @(posedge clk)
begin
if(!rstn)
begin
addr <= 16'd0;
data_in <= 8'd0;
end
else
begin
case(state)
IDLE : begin
addr <= 16'h0003;
data_in <= 8'h5A;
end
CONECT : begin
if(dri_cnt == 5'd1 && busy_falling && data_out == 8'h5A)
begin
addr <= cmd_iic[23:8];
data_in <= cmd_iic[ 7:0];
end
else
begin
addr <= addr;
data_in <= data_in;
end
end
INIT ,
WAIT ,
RD_BAK :begin
addr <= cmd_iic[23:8];
data_in <= cmd_iic[ 7:0];
end
STA_RD :begin
case(dri_cnt)
9'd0 : begin
addr <= 16'h209C;
data_in <= 8'h00;
end
9'd1 : begin
addr <= 16'h209D;
data_in <= 8'h00;
end
9'd2 : begin
addr <= 16'h209E;
data_in <= 8'h00;
end
9'd3 : begin
addr <= 16'h209F;
data_in <= 8'h00;
end
default: begin
addr <= 0;
data_in <= 0;
end
endcase
end
SETING : begin
case(dri_cnt)
9'd0 : begin
addr <= 16'h1010;
data_in <= 8'h01;
end
9'd1 : begin
addr <= 16'h1024;
data_in <= 8'h00;
end
9'd2 : begin
addr <= 16'h0200;
data_in <= 8'h0;
end
9'd3 : begin
addr <= 16'h1024;
data_in <= 8'h70;
end
9'd4 : begin
addr <= 16'h0200;
data_in <= 8'h07;
end
9'd5 : begin
addr <= 16'h0215;
data_in <= 8'h01;
end
9'd6 : begin
addr <= 16'h0215;
data_in <= 8'h00;
end
default: begin
addr <= 16'h0215;
data_in <= 8'h00;
end
endcase
end
default : begin
addr <= 0;
data_in <= 0;
end
endcase
end
end
always @(posedge clk)
begin
if(!rstn)
init_over <= 1'b0;
else if(state == SETING && dri_cnt == 5'd6 && busy_falling)
init_over <= 1'b1;
else
init_over <= init_over;
end
endmodule |
module udp_rx(
input clk , //ʱÖÓÐźÅ
input rst_n , //¸´Î»Ðźţ¬µÍµçƽÓÐЧ
input gmii_rx_dv , //GMIIÊäÈëÊý¾ÝÓÐЧÐźÅ
input [7:0] gmii_rxd /* synthesis PAP_MARK_DEBUG="1" */, //GMIIÊäÈëÊý¾Ý
output reg rec_pkt_done, //ÒÔÌ«Íøµ¥°üÊý¾Ý½ÓÊÕÍê³ÉÐźÅ
output reg rec_en /* synthesis PAP_MARK_DEBUG="1" */, //ÒÔÌ«Íø½ÓÊÕµÄÊý¾ÝʹÄÜÐźÅ
output reg [31:0] rec_data /* synthesis PAP_MARK_DEBUG="1" */, //ÒÔÌ«Íø½ÓÊÕµÄÊý¾Ý
output reg [15:0] rec_byte_num //ÒÔÌ«Íø½ÓÊÕµÄÓÐЧ×ÖÊý µ¥Î»:byte
);
//parameter define
//¿ª·¢°åMACµØÖ· 00-11-22-33-44-55
parameter BOARD_MAC = 48'h00_11_22_33_44_55;
//¿ª·¢°åIPµØÖ· 192.168.1.10
parameter BOARD_IP = {8'd192,8'd168,8'd1,8'd10};
localparam st_idle = 7'b000_0001; //³õʼ״̬£¬µÈ´ý½ÓÊÕÇ°µ¼Âë
localparam st_preamble = 7'b000_0010; //½ÓÊÕÇ°µ¼Âë״̬
localparam st_eth_head = 7'b000_0100; //½ÓÊÕÒÔÌ«ÍøÖ¡Í·
localparam st_ip_head = 7'b000_1000; //½ÓÊÕIPÊײ¿
localparam st_udp_head = 7'b001_0000; //½ÓÊÕUDPÊײ¿
localparam st_rx_data = 7'b010_0000; //½ÓÊÕÓÐЧÊý¾Ý
localparam st_rx_end = 7'b100_0000; //½ÓÊÕ½áÊø
localparam ETH_TYPE = 16'h0800 ; //ÒÔÌ«ÍøÐÒéÀàÐÍ IPÐÒé
//reg define
reg [6:0] cur_state ;
reg [6:0] next_state /* synthesis PAP_MARK_DEBUG="1" */;
reg skip_en ; //¿ØÖÆ״̬ÌøתʹÄÜÐźÅ
reg error_en /* synthesis PAP_MARK_DEBUG="1" */; //½âÎö´íÎóʹÄÜÐźÅ
reg [4:0] cnt ; //½âÎöÊý¾Ý¼ÆÊýÆ÷
reg [47:0] des_mac ; //Ä¿µÄMACµØÖ·
reg [15:0] eth_type ; //ÒÔÌ«ÍøÀàÐÍ
reg [31:0] des_ip ; //Ä¿µÄIPµØÖ·
reg [5:0] ip_head_byte_num; //IPÊײ¿³¤¶È
reg [15:0] udp_byte_num ; //UDP³¤¶È
reg [15:0] data_byte_num ; //Êý¾Ý³¤¶È
reg [15:0] data_cnt ; //ÓÐЧÊý¾Ý¼ÆÊý
reg [1:0] rec_en_cnt ; //8bitת32bit¼ÆÊýÆ÷
//*****************************************************
//** main code
//*****************************************************
//(Èý¶Îʽ״̬»ú)ͬ²½Ê±ÐòÃèÊö״̬תÒÆ
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cur_state <= st_idle;
else
cur_state <= next_state;
end
//×éºÏÂß¼ÅжÏ״̬תÒÆÌõ¼þ
always @(*) begin
next_state = st_idle;
case(cur_state)
st_idle : begin //µÈ´ý½ÓÊÕÇ°µ¼Âë
if(skip_en)
next_state = st_preamble;
else
next_state = st_idle;
end
st_preamble : begin //½ÓÊÕÇ°µ¼Âë
if(skip_en)
next_state = st_eth_head;
else if(error_en)
next_state = st_rx_end;
else
next_state = st_preamble;
end
st_eth_head : begin //½ÓÊÕÒÔÌ«ÍøÖ¡Í·
if(skip_en)
next_state = st_ip_head;
else if(error_en)
next_state = st_rx_end;
else
next_state = st_eth_head;
end
st_ip_head : begin //½ÓÊÕIPÊײ¿
if(skip_en)
next_state = st_udp_head;
else if(error_en)
next_state = st_rx_end;
else
next_state = st_ip_head;
end
st_udp_head : begin //½ÓÊÕUDPÊײ¿
if(skip_en)
next_state = st_rx_data;
else
next_state = st_udp_head;
end
st_rx_data : begin //½ÓÊÕÓÐЧÊý¾Ý
if(skip_en)
next_state = st_rx_end;
else
next_state = st_rx_data;
end
st_rx_end : begin //½ÓÊÕ½áÊø
if(skip_en)
next_state = st_idle;
else
next_state = st_rx_end;
end
default : next_state = st_idle;
endcase
end
//ʱÐòµç·ÃèÊö״̬Êä³ö,½âÎöÒÔÌ«ÍøÊý¾Ý
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
skip_en <= 1'b0;
error_en <= 1'b0;
cnt <= 5'd0;
des_mac <= 48'd0;
eth_type <= 16'd0;
des_ip <= 32'd0;
ip_head_byte_num <= 6'd0;
udp_byte_num <= 16'd0;
data_byte_num <= 16'd0;
data_cnt <= 16'd0;
rec_en_cnt <= 2'd0;
rec_en <= 1'b0;
rec_data <= 32'd0;
rec_pkt_done <= 1'b0;
rec_byte_num <= 16'd0;
end
else begin
skip_en <= 1'b0;
error_en <= 1'b0;
rec_en <= 1'b0;
rec_pkt_done <= 1'b0;
case(next_state)
st_idle : begin
if((gmii_rx_dv == 1'b1) && (gmii_rxd == 8'h55))
skip_en <= 1'b1;
end
st_preamble : begin
if(gmii_rx_dv) begin //½âÎöÇ°µ¼Âë
cnt <= cnt + 5'd1;
if((cnt < 5'd6) && (gmii_rxd != 8'h55)) //7¸ö8'h55
error_en <= 1'b1;
else if(cnt==5'd6) begin
cnt <= 5'd0;
if(gmii_rxd==8'hd5) //1¸ö8'hd5
skip_en <= 1'b1;
else
error_en <= 1'b1;
end
end
end
st_eth_head : begin
if(gmii_rx_dv) begin
cnt <= cnt + 5'b1;
if(cnt < 5'd6)
des_mac <= {des_mac[39:0],gmii_rxd}; //Ä¿µÄMACµØÖ·
else if(cnt == 5'd12)
eth_type[15:8] <= gmii_rxd; //ÒÔÌ«ÍøÐÒéÀàÐÍ
else if(cnt == 5'd13) begin
eth_type[7:0] <= gmii_rxd;
cnt <= 5'd0;
//ÅжÏMACµØÖ·ÊÇ·ñΪ¿ª·¢°åMACµØÖ·»òÕß¹«¹²µØÖ· ÅжÏÀàÐÍÊÇ·ñΪIPÐÒ飨0800£©
if(((des_mac == BOARD_MAC) ||(des_mac == 48'hff_ff_ff_ff_ff_ff))
&& eth_type[15:8] == ETH_TYPE[15:8] && gmii_rxd == ETH_TYPE[7:0])
skip_en <= 1'b1;
else
error_en <= 1'b1;
end
end
end
st_ip_head : begin
if(gmii_rx_dv) begin
cnt <= cnt + 5'd1;
if(cnt == 5'd0)
ip_head_byte_num <= {gmii_rxd[3:0],2'd0}; //IP¼Ä´æÊײ¿³¤¶È£¬×óÒÆÁ½Î»=x4£¬¼´dwX4±ä³É×Ö½ÚÊý
//±È½ÏÊÓƵ´úÂ룬ÉÙÁ˶ÔUDPÐÒéµÄ½âÎö
else if((cnt >= 5'd16) && (cnt <= 5'd18))
des_ip <= {des_ip[23:0],gmii_rxd}; //Ä¿µÄIPµØÖ·
else if(cnt == 5'd19) begin
des_ip <= {des_ip[23:0],gmii_rxd};
//ÅжÏIPµØÖ·ÊÇ·ñΪ¿ª·¢°åIPµØÖ·
if((des_ip[23:0] == BOARD_IP[31:8])
&& (gmii_rxd == BOARD_IP[7:0])) begin
if(cnt == ip_head_byte_num - 1'b1) begin//¼ÆÊýÊÇ·ñµÈÓÚÊײ¿×Ö½ÚÊý£¿Èç¹û»¹°üº¬¿ÉÑ¡×ֶλá¼ÌÐø×ÔÔöµÈ´ýÌøת
skip_en <=1'b1;
cnt <= 5'd0;
end
end
else begin
//IP´íÎó£¬Í£Ö¹½âÎöÊý¾Ý
error_en <= 1'b1;
cnt <= 5'd0;
end
end
else if(cnt == ip_head_byte_num - 1'b1) begin
skip_en <=1'b1; //IPÊײ¿½âÎöÍê³É
cnt <= 5'd0;
end
end
end
st_udp_head : begin
if(gmii_rx_dv) begin
cnt <= cnt + 5'd1;
if(cnt == 5'd4)
udp_byte_num[15:8] <= gmii_rxd; //½âÎöUDP×Ö½Ú³¤¶È £¨Êײ¿+Êý¾Ý£©
else if(cnt == 5'd5)
udp_byte_num[7:0] <= gmii_rxd;
else if(cnt == 5'd7) begin
//ÓÐЧÊý¾Ý×Ö½Ú³¤¶È£¬£¨UDPÊײ¿8¸ö×Ö½Ú£¬ËùÒÔ¼õÈ¥8£©
data_byte_num <= udp_byte_num - 16'd8;
skip_en <= 1'b1;
cnt <= 5'd0;
end
end
end
st_rx_data : begin
//½ÓÊÕÊý¾Ý£¬×ª»»³É32bit »ýÀÛËÄ´ÎʱÖÓÖÜÆÚÈ»ºóת
if(gmii_rx_dv) begin
data_cnt <= data_cnt + 16'd1;
rec_en_cnt <= rec_en_cnt + 2'd1;
if(data_cnt == data_byte_num - 16'd1) begin
skip_en <= 1'b1; //ÓÐЧÊý¾Ý½ÓÊÕÍê³É
data_cnt <= 16'd0;
rec_en_cnt <= 2'd0;
rec_pkt_done <= 1'b1;
rec_en <= 1'b1;
rec_byte_num <= data_byte_num;
end
//ÏÈÊÕµ½µÄÊý¾Ý·ÅÔÚÁËrec_dataµÄ¸ßλ,ËùÒÔµ±Êý¾Ý²»ÊÇ4µÄ±¶Êýʱ,
//µÍλÊý¾ÝΪÎÞЧÊý¾Ý£¬¿É¸ù¾ÝÓÐЧ×Ö½ÚÊýÀ´ÅжÏ(rec_byte_num)
if(rec_en_cnt == 2'd0)
rec_data[31:24] <= gmii_rxd;
else if(rec_en_cnt == 2'd1)
rec_data[23:16] <= gmii_rxd;
else if(rec_en_cnt == 2'd2)
rec_data[15:8] <= gmii_rxd;
else if(rec_en_cnt==2'd3) begin
rec_en <= 1'b1;
rec_data[7:0] <= gmii_rxd;
end
end
end
st_rx_end : begin //µ¥°üÊý¾Ý½ÓÊÕÍê³É
if(gmii_rx_dv == 1'b0 && skip_en == 1'b0)
skip_en <= 1'b1;
end
default : ;
endcase
end
end
endmodule |
module ov5640_reg_config(
input clk_25M,
input camera_rstn,
input initial_en,
output reg_conf_done,
output i2c_sclk,
inout i2c_sdat,
output reg clock_20k,
output reg [8:0]reg_index
);
reg [15:0]clock_20k_cnt;
reg [1:0]config_step;
reg [31:0]i2c_data;
reg [23:0]reg_data;
reg start;
reg reg_conf_done_reg;
i2c_com u1(.clock_i2c(clock_20k),
.camera_rstn(camera_rstn),
.ack(ack),
.i2c_data(i2c_data),
.start(start),
.tr_end(tr_end),
.i2c_sclk(i2c_sclk),
.i2c_sdat(i2c_sdat));
assign reg_conf_done=reg_conf_done_reg;
//²úÉúi2c¿ØÖÆʱÖÓ-20khz
always@(posedge clk_25M)
begin
if(!camera_rstn) begin
clock_20k<=0;
clock_20k_cnt<=0;
end
else if(clock_20k_cnt<1249)
clock_20k_cnt<=clock_20k_cnt+1'b1;
else begin
clock_20k<=!clock_20k;
clock_20k_cnt<=0;
end
end
////iic¼Ä´æÆ÷ÅäÖùý³Ì¿ØÖÆ
always@(posedge clock_20k)
begin
if(!camera_rstn) begin
config_step<=0;
start<=0;
reg_index<=0;
reg_conf_done_reg<=0;
end
else begin
if(reg_conf_done_reg==1'b0) begin //Èç¹ûcamera³õʼ»¯Î´Íê³É
if(reg_index<360) begin //ÅäÖüĴæÆ÷
case(config_step)
0:begin
i2c_data<={8'h78,reg_data}; //OV5640 IIC Device address is 0x78
start<=1; //i2cд¿ªÊ¼
config_step<=1;
end
1:begin
if(tr_end) begin //i2cд½áÊø
start<=0;
config_step<=2;
end
end
2:begin
reg_index<=reg_index+1'b1; //ÅäÖÃÏÂÒ»¸ö¼Ä´æÆ÷
config_step<=0;
end
endcase
end
else
reg_conf_done_reg<=1'b1; //OV5640¼Ä´æÆ÷³õʼ»¯Íê³É
end
end
end
////iicÐèÒªÅäÖõļĴæÆ÷Öµ
always@(reg_index)
begin
case(reg_index)
0 :reg_data <=24'h310311 ;//
1 :reg_data <=24'h300882 ;//
102 :reg_data <=24'h300842 ;//
103 :reg_data <=24'h310303 ;//
104 :reg_data <=24'h3017ff ;//
105 :reg_data <=24'h3018ff ;//
106 :reg_data <=24'h30341A ;//
107 :reg_data <=24'h303713 ;//
108 :reg_data <=24'h310801 ;//
109 :reg_data <=24'h363036 ;//
110 :reg_data <=24'h36310e ;//
111 :reg_data <=24'h3632e2 ;//
112 :reg_data <=24'h363312 ;//
113 :reg_data <=24'h3621e0 ;//
114 :reg_data <=24'h3704a0 ;//
115 :reg_data <=24'h37035a ;//
116 :reg_data <=24'h371578 ;//
117 :reg_data <=24'h371701 ;//
118 :reg_data <=24'h370b60 ;//
119 :reg_data <=24'h37051a ;//
120 :reg_data <=24'h390502 ;//
121 :reg_data <=24'h390610 ;//
122 :reg_data <=24'h39010a ;//
123 :reg_data <=24'h373112 ;//
124 :reg_data <=24'h360008 ;//
125 :reg_data <=24'h360133 ;//
126 :reg_data <=24'h302d60 ;//
127 :reg_data <=24'h362052 ;//
128 :reg_data <=24'h371b20 ;//
129 :reg_data <=24'h471c50 ;//
130 :reg_data <=24'h3a1343 ;//
131 :reg_data <=24'h3a1800 ;//
132 :reg_data <=24'h3a19f8 ;//
133 :reg_data <=24'h363513 ;//
134 :reg_data <=24'h363603 ;//
135 :reg_data <=24'h363440 ;//
136 :reg_data <=24'h362201 ;///
137 :reg_data <=24'h3c0134 ;//
138 :reg_data <=24'h3c0428 ;//
139 :reg_data <=24'h3c0598 ;//
140 :reg_data <=24'h3c0600 ;//
141 :reg_data <=24'h3c0708 ;//
142 :reg_data <=24'h3c0800 ;//
143 :reg_data <=24'h3c091c ;//
144 :reg_data <=24'h3c0a9c ;//
145 :reg_data <=24'h3c0b40 ;//
146 :reg_data <=24'h381000 ;//
147 :reg_data <=24'h381110 ;//
148 :reg_data <=24'h381200 ;//
149 :reg_data <=24'h370864 ;//
150 :reg_data <=24'h400102 ;//
151 :reg_data <=24'h40051a ;//
152 :reg_data <=24'h300000 ;//
153 :reg_data <=24'h3004ff ;//
154 :reg_data <=24'h300e58 ;//
155 :reg_data <=24'h302e00 ;//
156 :reg_data <=24'h430060 ;//
157 :reg_data <=24'h501f01 ;//
158 :reg_data <=24'h440e00 ;//
159 :reg_data <=24'h5000a7 ;//
160 :;//reg_data <=24'h3a0f28 ;//reg_data <=24'h3a0f30 ;// -0.7ev
161 :;//reg_data <=24'h3a1020 ;//reg_data <=24'h3a1028 ;//
162 :;//reg_data <=24'h3a1b28 ;//reg_data <=24'h3a1b30 ;//
163 :;//reg_data <=24'h3a1e20 ;//reg_data <=24'h3a1e26 ;//
164 :;//reg_data <=24'h3a1151 ;//reg_data <=24'h3a1160 ;//
165 :;//reg_data <=24'h3a1f10 ;//reg_data <=24'h3a1f14 ;//
166 :reg_data <=24'h580023 ;//
167 :reg_data <=24'h580114 ;//
168 :reg_data <=24'h58020f ;//
169 :reg_data <=24'h58030f ;//
170 :reg_data <=24'h580412 ;//
171 :reg_data <=24'h580526 ;//
172 :reg_data <=24'h58060c ;//
173 :reg_data <=24'h580708 ;//
174 :reg_data <=24'h580805 ;//
175 :reg_data <=24'h580905 ;//
176 :reg_data <=24'h580a08 ;//
177 :reg_data <=24'h580b0d ;//
178 :reg_data <=24'h580c08 ;//
179 :reg_data <=24'h580d03 ;//
180 :reg_data <=24'h580e00 ;//
181 :reg_data <=24'h580f00 ;//
182 :reg_data <=24'h581003 ;//
183 :reg_data <=24'h581109 ;//
184 :reg_data <=24'h581207 ;//
185 :reg_data <=24'h581303 ;//
186 :reg_data <=24'h581400 ;//
187 :reg_data <=24'h581501 ;//
188 :reg_data <=24'h581603 ;//
189 :reg_data <=24'h581708 ;//
190 :reg_data <=24'h58180d ;//
191 :reg_data <=24'h581908 ;//
192 :reg_data <=24'h581a05 ;//
193 :reg_data <=24'h581b06 ;//
194 :reg_data <=24'h581c08 ;//
195 :reg_data <=24'h581d0e ;//
196 :reg_data <=24'h581e29 ;//
197 :reg_data <=24'h581f17 ;//
198 :reg_data <=24'h582011 ;//
199 :reg_data <=24'h582111 ;//
200 :reg_data <=24'h582215 ;//
201 :reg_data <=24'h582328 ;//
202 :reg_data <=24'h582446 ;//
203 :reg_data <=24'h582526 ;//
204 :reg_data <=24'h582608 ;//
205 :reg_data <=24'h582726 ;//
206 :reg_data <=24'h582864 ;//
207 :reg_data <=24'h582926 ;//
208 :reg_data <=24'h582a24 ;//
209 :reg_data <=24'h582b22 ;//
210 :reg_data <=24'h582c24 ;//
211 :reg_data <=24'h582d24 ;//
212 :reg_data <=24'h582e06 ;//
213 :reg_data <=24'h582f22 ;//
214 :reg_data <=24'h583040 ;//
215 :reg_data <=24'h583142 ;//
216 :reg_data <=24'h583224 ;//
217 :reg_data <=24'h583326 ;//
218 :reg_data <=24'h583424 ;//
219 :reg_data <=24'h583522 ;//
220 :reg_data <=24'h583622 ;//
221 :reg_data <=24'h583726 ;//
222 :reg_data <=24'h583844 ;//
223 :reg_data <=24'h583924 ;//
224 :reg_data <=24'h583a26 ;//
225 :reg_data <=24'h583b28 ;//
226 :reg_data <=24'h583c42 ;//
227 :reg_data <=24'h583dce ;//
228 :reg_data <=24'h5180ff ;//
229 :reg_data <=24'h5181f2 ;//
230 :reg_data <=24'h518200 ;//
231 :reg_data <=24'h518314 ;//
232 :reg_data <=24'h518425 ;//
233 :reg_data <=24'h518524 ;//
234 :reg_data <=24'h518609 ;//
235 :reg_data <=24'h518709 ;//
236 :reg_data <=24'h518809 ;//
237 :reg_data <=24'h518975 ;//
238 :reg_data <=24'h518a54 ;//
239 :reg_data <=24'h518be0 ;//
240 :reg_data <=24'h518cb2 ;//
241 :reg_data <=24'h518d42 ;//
242 :reg_data <=24'h518e3d ;//
243 :reg_data <=24'h518f56 ;//
244 :reg_data <=24'h519046 ;//
245 :reg_data <=24'h5191f8 ;//
246 :reg_data <=24'h519204 ;//
247 :reg_data <=24'h519370 ;//
248 :reg_data <=24'h5194f0 ;//
249 :reg_data <=24'h5195f0 ;//
250 :reg_data <=24'h519603 ;//
251 :reg_data <=24'h519701 ;//
252 :reg_data <=24'h519804 ;//
253 :reg_data <=24'h519912 ;//
254 :reg_data <=24'h519a04 ;//
255 :reg_data <=24'h519b00 ;//
256 :reg_data <=24'h519c06 ;//
257 :reg_data <=24'h519d82 ;//
258 :reg_data <=24'h519e38 ;//
259 :reg_data <=24'h548001 ;//
260 :reg_data <=24'h548108 ;//
261 :reg_data <=24'h548214 ;//
262 :reg_data <=24'h548328 ;//
263 :reg_data <=24'h548451 ;//
264 :reg_data <=24'h548565 ;//
265 :reg_data <=24'h548671 ;//
266 :reg_data <=24'h54877d ;//
267 :reg_data <=24'h548887 ;//
268 :reg_data <=24'h548991 ;//
269 :reg_data <=24'h548a9a ;//
270 :reg_data <=24'h548baa ;//
271 :reg_data <=24'h548cb8 ;//
272 :reg_data <=24'h548dcd ;//
273 :reg_data <=24'h548edd ;//
274 :reg_data <=24'h548fea ;//
275 :reg_data <=24'h54901d ;//
276 :reg_data <=24'h53811e ;//
277 :reg_data <=24'h53825b ;//
278 :reg_data <=24'h538308 ;//
279 :reg_data <=24'h53840a ;//
280 :reg_data <=24'h53857e ;//
281 :reg_data <=24'h538688 ;//
282 :reg_data <=24'h53877c ;//
283 :reg_data <=24'h53886c ;//
284 :reg_data <=24'h538910 ;//
285 :reg_data <=24'h538a01 ;//
286 :reg_data <=24'h538b98 ;//
287 :reg_data <=24'h558007 ;//
288 :reg_data <=24'h558340 ;//
289 :reg_data <=24'h558410 ;//
290 :reg_data <=24'h558910 ;//
291 :reg_data <=24'h558a00 ;//
292 :reg_data <=24'h558bf8 ;//
293 :reg_data <=24'h501d40 ;//
294 :reg_data <=24'h530008 ;//
295 :reg_data <=24'h530130 ;//
296 :reg_data <=24'h530210 ;//
297 :reg_data <=24'h530300 ;//
298 :reg_data <=24'h530408 ;//
299 :reg_data <=24'h530530 ;//
300 :reg_data <=24'h530608 ;//
301 :reg_data <=24'h530716 ;//
302 :reg_data <=24'h530908 ;//
303 :reg_data <=24'h530a30 ;//
304 :reg_data <=24'h530b04 ;//
305 :reg_data <=24'h530c06 ;//
306 :reg_data <=24'h502500 ;//
307 :reg_data <=24'h300802 ;//
//720 30Ö¡/Ãë, night mode 5fps ;//
//input clock=24Mhz,PCLK=84Mhz ;//
308 :reg_data <=24'h303521 ;//PLL
309 :reg_data <=24'h303669 ;//PLL
310 :reg_data <=24'h3c0708 ;//
311 :reg_data <=24'h382040 ;//
312 :reg_data <=24'h382106 ;//
313 :reg_data <=24'h381431 ;//
314 :reg_data <=24'h381531 ;//
315 :reg_data <=24'h380000 ;//
316 :reg_data <=24'h380100 ;//
317 :reg_data <=24'h380200 ;//
318 :reg_data <=24'h3803fa ;//
319 :reg_data <=24'h38040a ;//
320 :reg_data <=24'h38053f ;//
321 :reg_data <=24'h380606 ;//
322 :reg_data <=24'h3807a9 ;//
323 :reg_data <=24'h380803 ;//24'h380805 ;// ˮƽ·Ö±æÂʸß
324 :reg_data <=24'h3809c0 ;//24'h380900 ;//
325 :reg_data <=24'h380a02 ;//24'h380a02 ;// ÊúÖ±·Ö±æÂÊ
326 :reg_data <=24'h380b1c ;//24'h380bd0 ;//
327 :reg_data <=24'h380c07 ;//
328 :reg_data <=24'h380d64 ;//
329 :reg_data <=24'h380e02 ;//
330 :reg_data <=24'h380fe4 ;//
331 :reg_data <=24'h381304 ;//
332 :reg_data <=24'h361800 ;//
333 :reg_data <=24'h361229 ;//
334 :reg_data <=24'h370952 ;//
335 :reg_data <=24'h370c03 ;//
336 :reg_data <=24'h3a0202 ;//
337 :reg_data <=24'h3a03e0 ;//
338 :reg_data <=24'h3a0800 ;//
339 :reg_data <=24'h3a096f ;//
340 :reg_data <=24'h3a0a00 ;//
341 :reg_data <=24'h3a0b5c ;//
342 :reg_data <=24'h3a0e06 ;//
343 :reg_data <=24'h3a0d08 ;//
344 :reg_data <=24'h3a1402 ;//
345 :reg_data <=24'h3a15e0 ;//
346 :reg_data <=24'h400402 ;//
347 :reg_data <=24'h30021c ;//
348 :reg_data <=24'h3006c3 ;//
349 :reg_data <=24'h471303 ;//
350 :reg_data <=24'h440704 ;//
351 :reg_data <=24'h460b37 ;//
352 :reg_data <=24'h460c20 ;//
353 :reg_data <=24'h483716 ;//
354 :reg_data <=24'h382404 ;//
355 :reg_data <=24'h5001ff ;//
356 :reg_data <=24'h350300 ;//
357 :reg_data <=24'h558178 ;//sinÒò×Ó
358 :reg_data <=24'h558220 ;//cosÒò×Ó
359 :reg_data <=24'h558801 ;//Ó¦ÓòÎÊý
default:reg_data<=24'hffffff;//
endcase
end
endmodule |
module cmos_8_16bit(
input pclk ,
input rst_n ,
input de_i ,
input [7:0] pdata_i ,
input vs_i ,
output wire pixel_clk ,
output reg de_o ,
output reg [15:0] pdata_o
);
reg de_out1 ;
reg [15:0] pdata_out1 ;
reg de_out2 ;
reg [15:0] pdata_out2 ;
reg [1:0] cnt ;
wire pclk_IOCLKBUF ;
reg vs_i_reg ;
reg enble ;
reg [7:0] pdata_i_reg;
reg de_i_r,de_i_r1;
reg de_out3 ;
reg [15:0] pdata_out3 ;
always @(posedge pclk)begin
vs_i_reg <= vs_i ;
end
always@(posedge pclk)
begin
if(!rst_n)
enble <= 1'b0;
else if(!vs_i_reg&&vs_i)
enble <= 1'b1;
else
enble <= enble;
end
GTP_IOCLKBUF #(
.GATE_EN("FALSE")//
) u_GTP_IOCLKBUF (
.CLKOUT(pclk_IOCLKBUF),// OUTPUT
.CLKIN(pclk), // INPUT
.DI(1'b1) // INPUT
);
GTP_IOCLKDIV #(
.GRS_EN("TRUE"),
.DIV_FACTOR("2")
) u_GTP_IOCLKDIV (
.CLKDIVOUT(pixel_clk),// OUTPUT
.CLKIN(pclk_IOCLKBUF), // INPUT
.RST_N(rst_n) // INPUT
);
always@(posedge pclk)
begin
if(!rst_n)
cnt <= 2'b0;
else if(de_i == 1'b1 && cnt == 2'd1)
cnt <= 2'b0;
else if(de_i == 1'b1)
cnt <= cnt + 1'b1;
end
always@(posedge pclk)
begin
if(!rst_n)
pdata_i_reg <= 8'b0;
else if(de_i == 1'b1)
pdata_i_reg <= pdata_i;
end
always@(posedge pclk)
begin
if(!rst_n)
pdata_out1 <= 16'b0;
else if(de_i == 1'b1 && cnt == 2'd1)
pdata_out1 <= {pdata_i_reg,pdata_i};
end
always@(posedge pclk)begin
de_i_r <= de_i;
de_i_r1 <= de_i_r;
end
always@(posedge pclk)
begin
if(!rst_n)
de_out1 <= 1'b0;
else if(!de_i_r1 && de_i_r )//ÉÏÉýÑØ
de_out1 <= 1'b1;
else if(de_i_r1 && !de_i_r )//ϽµÑØ
de_out1 <= 1'b0;
else
de_out1 <= de_out1;
end
always@(posedge pixel_clk)begin
de_out2<=de_out1;
de_out3<=de_out2;
de_o <=de_out3;
end
always@(posedge pixel_clk)begin
pdata_out2<=pdata_out1;
pdata_out3<=pdata_out2;
pdata_o <=pdata_out3;
end
endmodule |
module axi_m_arbitration #(
parameter integer VIDEO_LENGTH = 1920 ,
parameter integer VIDEO_HIGTH = 1080 ,
parameter integer ZOOM_VIDEO_LENGTH = 960 ,
parameter integer ZOOM_VIDEO_HIGTH = 540 ,
parameter integer PIXEL_WIDTH = 32 ,
parameter integer CTRL_ADDR_WIDTH = 28 ,
parameter integer DQ_WIDTH = 32 ,
parameter integer M_AXI_BRUST_LEN = 8
)
(
input wire DDR_INIT_DONE /* synthesis PAP_MARK_DEBUG="1" */,
input wire M_AXI_ACLK /* synthesis PAP_MARK_DEBUG="1" */,
input wire M_AXI_ARESETN /* synthesis PAP_MARK_DEBUG="1" */,
input wire pix_clk_out ,
//дµØַͨµÀ¡ý
output wire [3 : 0] M_AXI_AWID ,
output wire [CTRL_ADDR_WIDTH-1 : 0] M_AXI_AWADDR ,
// output wire [3 : 0] M_AXI_AWLEN ,
output wire M_AXI_AWUSER ,
output wire M_AXI_AWVALID ,
input wire M_AXI_AWREADY ,
//дÊý¾ÝͨµÀ¡ý
output wire [DQ_WIDTH*8-1 : 0] M_AXI_WDATA ,
output wire [DQ_WIDTH-1 : 0] M_AXI_WSTRB ,
input wire M_AXI_WLAST ,
input wire [3 : 0] M_AXI_WUSER ,
input wire M_AXI_WREADY ,
//¶ÁµØַͨµÀ¡ý
output wire [3 : 0] M_AXI_ARID ,
output wire M_AXI_ARUSER ,
output wire [CTRL_ADDR_WIDTH-1 : 0] M_AXI_ARADDR ,
// output wire [3 : 0] M_AXI_ARLEN ,
output wire M_AXI_ARVALID ,
input wire M_AXI_ARREADY ,
//¶ÁÊý¾ÝͨµÀ¡ý
input wire [3 : 0] M_AXI_RID ,
input wire [DQ_WIDTH*8-1 : 0] M_AXI_RDATA ,
input wire M_AXI_RLAST ,
input wire M_AXI_RVALID ,
//video
input wire vs_in /* synthesis PAP_MARK_DEBUG="1" */,
input wire vs_out /* synthesis PAP_MARK_DEBUG="1" */,
//fifo0ÐźÅ
input wire video0_clk_in ,
input wire video0_de_in /* synthesis PAP_MARK_DEBUG="1" */,
input wire [31 : 0] video0_data_in /* synthesis PAP_MARK_DEBUG="1" */,
input wire video0_rd_en ,
output wire [31 : 0] video0_data_out /* synthesis PAP_MARK_DEBUG="1" */,
output wire fram0_done ,
input wire video0_vs_in ,
//fifo1ÐźÅ
input wire video1_clk_in ,
input wire video1_de_in /* synthesis PAP_MARK_DEBUG="1" */,
input wire [31 : 0] video1_data_in ,
input wire video1_rd_en ,
output wire [31 : 0] video1_data_out /* synthesis PAP_MARK_DEBUG="1" */,
output wire fram1_done ,
input wire video1_vs_in ,
//fifo2ÐźÅ
input wire video2_clk_in ,
input wire video2_de_in /* synthesis PAP_MARK_DEBUG="1" */,
input wire [31 : 0] video2_data_in ,
input wire video2_rd_en ,
output wire [31 : 0] video2_data_out /* synthesis PAP_MARK_DEBUG="1" */,
output wire fram2_done ,
input wire video2_vs_in ,
//fifo3ÐźÅ
input wire video3_clk_in ,
input wire video3_de_in /* synthesis PAP_MARK_DEBUG="1" */,
input wire [31 : 0] video3_data_in ,
input wire video3_rd_en ,
output wire [31 : 0] video3_data_out /* synthesis PAP_MARK_DEBUG="1" */,
output wire fram3_done ,
input wire video3_vs_in ,
//ÆäËû
input [19 : 0] wr_addr_min ,//дÊý¾Ýddr×îСµØÖ·0µØÖ·¿ªÊ¼Ë㣬1920*1080*16 = 33177600 bits
input [19 : 0] wr_addr_max ,//дÊý¾Ýddr×î´óµØÖ·£¬Ò»¸öµØÖ·´æ32λ 33177600/32 = 1036800 = 20'b1111_1101_0010_0000_0000
input wire [11 : 0] y_act ,
input wire [11 : 0] x_act
);
//********************************parameter**********************************//
parameter VIDEO0_BASE_ADDR = 2'd0;
parameter VIDEO1_BASE_ADDR = 2'd1;
parameter VIDEO2_BASE_ADDR = 2'd2;
parameter VIDEO3_BASE_ADDR = 2'd3;
//parameter WRITE_ARBITRATION = 3'd0;
//parameter M0_WRITE = 4'b0001;
//parameter M1_WRITE = 4'b0010;
//parameter M2_WRITE = 4'b0100;
//parameter M3_WRITE = 4'b1000;
parameter M0_WRITE = 2'd0;
parameter M1_WRITE = 2'd1;
parameter M2_WRITE = 2'd2;
parameter M3_WRITE = 2'd3;
parameter READ_ARBITRATION = 3'd0;
parameter M0_READ = 3'd1;
parameter M1_READ = 3'd2;
parameter M2_READ = 3'd3;
parameter M3_READ = 3'd4;
//********************************wire**********************************//
wire [255 : 0] M0_AXI_WDATA /* synthesis PAP_MARK_DEBUG="1" */;
wire M0_AXI_AWVALID /* synthesis PAP_MARK_DEBUG="1" */;
wire M0_AXI_AWREADY /* synthesis PAP_MARK_DEBUG="1" */;
wire [CTRL_ADDR_WIDTH-1 : 0] M0_AXI_AWADDR /* synthesis PAP_MARK_DEBUG="1" */;
wire M0_AXI_WLAST /* synthesis PAP_MARK_DEBUG="1" */;
wire M0_AXI_WREADY /* synthesis PAP_MARK_DEBUG="1" */;
wire M0_AXI_ARVALID /* synthesis PAP_MARK_DEBUG="1" */;
wire M0_AXI_ARREADY /* synthesis PAP_MARK_DEBUG="1" */;
wire [CTRL_ADDR_WIDTH-1 : 0] M0_AXI_ARADDR /* synthesis PAP_MARK_DEBUG="1" */;
wire [255 : 0] M0_AXI_RDATA /* synthesis PAP_MARK_DEBUG="1" */;
wire M0_AXI_RLAST /* synthesis PAP_MARK_DEBUG="1" */;
wire M0_AXI_RVALID /* synthesis PAP_MARK_DEBUG="1" */;
wire [255 : 0] M1_AXI_WDATA /* synthesis PAP_MARK_DEBUG="1" */;
wire M1_AXI_AWVALID /* synthesis PAP_MARK_DEBUG="1" */;
wire M1_AXI_AWREADY /* synthesis PAP_MARK_DEBUG="1" */;
wire [CTRL_ADDR_WIDTH-1 : 0] M1_AXI_AWADDR /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M1_AXI_WLAST /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M1_AXI_WREADY /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M1_AXI_ARVALID /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M1_AXI_ARREADY /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [CTRL_ADDR_WIDTH-1 : 0] M1_AXI_ARADDR /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [255 : 0] M1_AXI_RDATA /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M1_AXI_RLAST /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M1_AXI_RVALID /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [255 : 0] M2_AXI_WDATA /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M2_AXI_AWVALID /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M2_AXI_AWREADY /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [CTRL_ADDR_WIDTH-1 : 0] M2_AXI_AWADDR /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M2_AXI_WLAST /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M2_AXI_WREADY /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M2_AXI_ARVALID /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M2_AXI_ARREADY /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [CTRL_ADDR_WIDTH-1 : 0] M2_AXI_ARADDR /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [255 : 0] M2_AXI_RDATA /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M2_AXI_RLAST /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M2_AXI_RVALID /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [255 : 0] M3_AXI_WDATA /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M3_AXI_AWVALID /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M3_AXI_AWREADY /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [CTRL_ADDR_WIDTH-1 : 0] M3_AXI_AWADDR /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M3_AXI_WLAST /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M3_AXI_WREADY /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M3_AXI_ARVALID /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M3_AXI_ARREADY /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [CTRL_ADDR_WIDTH-1 : 0] M3_AXI_ARADDR /* synthesis PAP_MARK_DEBUG="1" */ ;
wire [255 : 0] M3_AXI_RDATA /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M3_AXI_RLAST /* synthesis PAP_MARK_DEBUG="1" */ ;
wire M3_AXI_RVALID /* synthesis PAP_MARK_DEBUG="1" */ ;
wire rfifo0_wr_req /* synthesis PAP_MARK_DEBUG="1" */;
wire [8 : 0] rfifo0_wr_water_level/* synthesis PAP_MARK_DEBUG="1" */;
wire rfifo1_wr_req /* synthesis PAP_MARK_DEBUG="1" */;
wire [8 : 0] rfifo1_wr_water_level/* synthesis PAP_MARK_DEBUG="1" */;
wire rfifo2_wr_req /* synthesis PAP_MARK_DEBUG="1" */;
wire [8 : 0] rfifo2_wr_water_level/* synthesis PAP_MARK_DEBUG="1" */;
wire rfifo3_wr_req /* synthesis PAP_MARK_DEBUG="1" */;
wire [8 : 0] rfifo3_wr_water_level/* synthesis PAP_MARK_DEBUG="1" */;
wire [8 : 0] wfifo0_rd_water_level/* synthesis PAP_MARK_DEBUG="1" */;
wire [8 : 0] wfifo1_rd_water_level/* synthesis PAP_MARK_DEBUG="1" */;
wire [8 : 0] wfifo2_rd_water_level/* synthesis PAP_MARK_DEBUG="1" */;
wire [8 : 0] wfifo3_rd_water_level/* synthesis PAP_MARK_DEBUG="1" */;
wire wfifo0_rd_req /* synthesis PAP_MARK_DEBUG="1" */;
wire wfifo0_pre_rd_req/* synthesis PAP_MARK_DEBUG="1" */;
wire wfifo1_rd_req /* synthesis PAP_MARK_DEBUG="1" */;
wire wfifo1_pre_rd_req/* synthesis PAP_MARK_DEBUG="1" */;
wire wfifo2_rd_req /* synthesis PAP_MARK_DEBUG="1" */;
wire wfifo2_pre_rd_req/* synthesis PAP_MARK_DEBUG="1" */;
wire wfifo3_rd_req /* synthesis PAP_MARK_DEBUG="1" */;
wire wfifo3_pre_rd_req/* synthesis PAP_MARK_DEBUG="1" */;
wire [1 : 0] wfifo0_state/* synthesis PAP_MARK_DEBUG="1" */;
wire [1 : 0] wfifo1_state/* synthesis PAP_MARK_DEBUG="1" */;
wire [1 : 0] wfifo2_state/* synthesis PAP_MARK_DEBUG="1" */;
wire [1 : 0] wfifo3_state/* synthesis PAP_MARK_DEBUG="1" */;
wire [1 : 0] rfifo0_state/* synthesis PAP_MARK_DEBUG="1" */;
wire [1 : 0] rfifo1_state/* synthesis PAP_MARK_DEBUG="1" */;
wire [1 : 0] rfifo2_state/* synthesis PAP_MARK_DEBUG="1" */;
wire [1 : 0] rfifo3_state/* synthesis PAP_MARK_DEBUG="1" */;
wire wr_rst /* synthesis PAP_MARK_DEBUG="1" */;
wire rd_rst /* synthesis PAP_MARK_DEBUG="1" */;
wire [19 : 0] wr_addr_cnt0 /* synthesis PAP_MARK_DEBUG="1" */;
wire [19 : 0] wr_addr_cnt1 /* synthesis PAP_MARK_DEBUG="1" */;
wire [19 : 0] wr_addr_cnt2 /* synthesis PAP_MARK_DEBUG="1" */;
wire [19 : 0] wr_addr_cnt3 /* synthesis PAP_MARK_DEBUG="1" */;
//********************************reg**********************************//
reg [4 : 0] arbitration_wr_state/* synthesis PAP_MARK_DEBUG="1" */;
reg [2 : 0] arbitration_rd_state/* synthesis PAP_MARK_DEBUG="1" */;
reg rfifo_pre_write_init/* synthesis PAP_MARK_DEBUG="1" */;
reg [11 : 0] r_y_act_d0/* synthesis PAP_MARK_DEBUG="1" */;
reg [11 : 0] r_x_act_d0/* synthesis PAP_MARK_DEBUG="1" */;
reg r_video0_rd_en_d0/* synthesis PAP_MARK_DEBUG="1" */;
reg r_video1_rd_en_d0/* synthesis PAP_MARK_DEBUG="1" */;
reg r_video2_rd_en_d0/* synthesis PAP_MARK_DEBUG="1" */;
reg r_video3_rd_en_d0/* synthesis PAP_MARK_DEBUG="1" */;
//********************************assign**********************************//
//¹Ì¶¨Êä³öµÄ½Ó¿Ú£¬¸÷Ö÷»ú²»ÐèÒªµ¥¶ÀÔÙÊä³ö
assign M_AXI_AWID = 4'b0;
assign M_AXI_AWUSER = 1'b0;
assign M_AXI_WSTRB = {(DQ_WIDTH){1'b1}};//ÉÁ¹âµÆÐźţ¬Êý¾Ýλ¿í/4 4λ¶¼Îª1
assign M_AXI_ARID = 4'b0;//ÓëдµØÖ·ÀàËÆ
assign M_AXI_ARUSER = 1'b0;
//ÖÙ²ÃÆ÷Êä³öÖ÷»úµÄ¿ØÖÆÐźÅ
assign M_AXI_AWVALID = (arbitration_wr_state == M0_WRITE)?M0_AXI_AWVALID:((arbitration_wr_state == M1_WRITE)?M1_AXI_AWVALID : ((arbitration_wr_state == M2_WRITE)?M2_AXI_AWVALID : (arbitration_wr_state == M3_WRITE)?M3_AXI_AWVALID : 'd0));//r_M_AXI_AWVALID; //ÖÙ²ÃÆ÷Êä³öawvalid
assign M_AXI_AWADDR = (arbitration_wr_state == M0_WRITE)?M0_AXI_AWADDR:((arbitration_wr_state == M1_WRITE)?M1_AXI_AWADDR : ((arbitration_wr_state == M2_WRITE)?M2_AXI_AWADDR : (arbitration_wr_state == M3_WRITE)?M3_AXI_AWADDR : 'd0)); //ÖÙ²ÃÆ÷Êä³öawaddr
assign M_AXI_ARVALID = (arbitration_rd_state == M0_READ)?M0_AXI_ARVALID:((arbitration_rd_state == M1_READ)?M1_AXI_ARVALID : ((arbitration_rd_state == M2_READ)?M2_AXI_ARVALID : (arbitration_rd_state == M3_READ)?M3_AXI_ARVALID : 'd0));
assign M_AXI_ARADDR = (arbitration_rd_state == M0_READ)?M0_AXI_ARADDR:((arbitration_rd_state == M1_READ)?M1_AXI_ARADDR : ((arbitration_rd_state == M2_READ)?M2_AXI_ARADDR : (arbitration_rd_state == M3_READ)?M3_AXI_ARADDR : 'd0));
//ÖÙ²ÃÆ÷½«´Ó»ú·¢³öµÄÐźÅת·¢¸øÖ÷»ú0
assign M0_AXI_AWREADY = (arbitration_wr_state == M0_WRITE)?M_AXI_AWREADY : 'd0 ; //r_M0_AXI_AWREADY;ÓÉÓÚ¶àÒ»¸öalways¿é»áµ¼ÖÂÐźÅÂýÒ»ÅÄ£¬¶ÔÓÚ´Ó»úÀ´²»ÐÐ
assign M0_AXI_WLAST = (arbitration_wr_state == M0_WRITE)?M_AXI_WLAST : 'd0 ; //r_M0_AXI_WLAST ;ÓÉÓÚ¶àÒ»¸öalways¿é»áµ¼ÖÂÐźÅÂýÒ»ÅÄ£¬¶ÔÓÚ´Ó»úÀ´²»ÐÐ
assign M0_AXI_WREADY = (arbitration_wr_state == M0_WRITE)?M_AXI_WREADY : 'd0 ; //r_M0_AXI_WREADY ;ÓÉÓÚ¶àÒ»¸öalways¿é»áµ¼ÖÂÐźÅÂýÒ»ÅÄ£¬¶ÔÓÚ´Ó»úÀ´²»ÐÐ
assign M0_AXI_ARREADY = (arbitration_rd_state == M0_READ )?M_AXI_ARREADY : 'd0;//r_M0_AXI_ARREADY;ÓÉÓÚ¶àÒ»¸öalways¿é»áµ¼ÖÂÐźÅÂýÒ»ÅÄ£¬¶ÔÓÚ´Ó»úÀ´²»ÐÐ
assign M0_AXI_RLAST = (arbitration_rd_state == M0_READ )?M_AXI_RLAST : 'd0;//r_M0_AXI_RLAST ;ÓÉÓÚ¶àÒ»¸öalways¿é»áµ¼ÖÂÐźÅÂýÒ»ÅÄ£¬¶ÔÓÚ´Ó»úÀ´²»ÐÐ
assign M0_AXI_RVALID = (arbitration_rd_state == M0_READ )?M_AXI_RVALID : 'd0;//r_M0_AXI_RVALID ;ÓÉÓÚ¶àÒ»¸öalways¿é»áµ¼ÖÂÐźÅÂýÒ»ÅÄ£¬¶ÔÓÚ´Ó»úÀ´²»ÐÐ
//ÖÙ²ÃÆ÷½«´Ó»ú·¢³öµÄÐźÅת·¢¸øÖ÷»ú1
assign M1_AXI_AWREADY = (arbitration_wr_state == M1_WRITE)?M_AXI_AWREADY : 'd0 ; //r_M1_AXI_AWREADY;
assign M1_AXI_WLAST = (arbitration_wr_state == M1_WRITE)?M_AXI_WLAST : 'd0 ; //r_M1_AXI_WLAST;
assign M1_AXI_WREADY = (arbitration_wr_state == M1_WRITE)?M_AXI_WREADY : 'd0 ; //r_M1_AXI_WREADY;
assign M1_AXI_ARREADY = (arbitration_rd_state == M1_READ )?M_AXI_ARREADY : 'd0;// r_M1_AXI_ARREADY;
assign M1_AXI_RLAST = (arbitration_rd_state == M1_READ )?M_AXI_RLAST : 'd0;// r_M1_AXI_RLAST ;
assign M1_AXI_RVALID = (arbitration_rd_state == M1_READ )?M_AXI_RVALID : 'd0;// r_M1_AXI_RVALID ;
//ÖÙ²ÃÆ÷½«´Ó»ú·¢³öµÄÐźÅת·¢¸øÖ÷»ú2
assign M2_AXI_AWREADY = (arbitration_wr_state == M2_WRITE)?M_AXI_AWREADY : 'd0 ; //r_M2_AXI_AWREADY;
assign M2_AXI_WLAST = (arbitration_wr_state == M2_WRITE)?M_AXI_WLAST : 'd0 ; //r_M2_AXI_WLAST;
assign M2_AXI_WREADY = (arbitration_wr_state == M2_WRITE)?M_AXI_WREADY : 'd0 ; //r_M2_AXI_WREADY;
assign M2_AXI_ARREADY = (arbitration_rd_state == M2_READ )?M_AXI_ARREADY : 'd0;// r_M2_AXI_ARREADY;
assign M2_AXI_RLAST = (arbitration_rd_state == M2_READ )?M_AXI_RLAST : 'd0;// r_M2_AXI_RLAST ;
assign M2_AXI_RVALID = (arbitration_rd_state == M2_READ )?M_AXI_RVALID : 'd0;// r_M2_AXI_RVALID ;
//ÖÙ²ÃÆ÷½«´Ó»ú·¢³öµÄÐźÅת·¢¸øÖ÷»ú3
assign M3_AXI_AWREADY = (arbitration_wr_state == M3_WRITE)?M_AXI_AWREADY : 'd0 ; //r_M3_AXI_AWREADY;
assign M3_AXI_WLAST = (arbitration_wr_state == M3_WRITE)?M_AXI_WLAST : 'd0 ; //r_M3_AXI_WLAST;
assign M3_AXI_WREADY = (arbitration_wr_state == M3_WRITE)?M_AXI_WREADY : 'd0 ; //r_M3_AXI_WREADY;
assign M3_AXI_ARREADY = (arbitration_rd_state == M3_READ )?M_AXI_ARREADY : 'd0;//r_M3_AXI_ARREADY;
assign M3_AXI_RLAST = (arbitration_rd_state == M3_READ )?M_AXI_RLAST : 'd0;//r_M3_AXI_RLAST ;
assign M3_AXI_RVALID = (arbitration_rd_state == M3_READ )?M_AXI_RVALID : 'd0;//r_M3_AXI_RVALID ;
//Êý¾ÝÊä³ö
assign M_AXI_WDATA = (arbitration_wr_state == M0_WRITE)?M0_AXI_WDATA:((arbitration_wr_state == M1_WRITE)?M1_AXI_WDATA : ((arbitration_wr_state == M2_WRITE)?M2_AXI_WDATA : (arbitration_wr_state == M3_WRITE)?M3_AXI_WDATA : 'd0));//дFIFOÊä³öÊý¾Ý¸øDDR
//Êý¾ÝÊäÈë
assign M0_AXI_RDATA = (arbitration_rd_state == M0_READ )?M_AXI_RDATA : 'd0;
assign M1_AXI_RDATA = (arbitration_rd_state == M1_READ )?M_AXI_RDATA : 'd0;
assign M2_AXI_RDATA = (arbitration_rd_state == M2_READ )?M_AXI_RDATA : 'd0;
assign M3_AXI_RDATA = (arbitration_rd_state == M3_READ )?M_AXI_RDATA : 'd0;
//********************************always**********************************//
//¶ÔAXIÖ÷»úºÍFIFO½øÐи´Î»
always @(posedge M_AXI_ACLK ) begin
if(!M_AXI_ARESETN) begin
r_video0_rd_en_d0 <= 'd0;
r_video1_rd_en_d0 <= 'd0;
r_video2_rd_en_d0 <= 'd0;
r_video3_rd_en_d0 <= 'd0;
r_y_act_d0 <= 'd0;
r_x_act_d0 <= 'd0;
end
else begin
r_video0_rd_en_d0 <= video0_rd_en;
r_video1_rd_en_d0 <= video1_rd_en;
r_video2_rd_en_d0 <= video2_rd_en;
r_video3_rd_en_d0 <= video3_rd_en;
r_y_act_d0 <= y_act;
r_x_act_d0 <= x_act;
end
end
//********************************״̬»ú**********************************//
//д״̬»ú£¬ÒÀ´ÎдÊý¾Ý
always @(posedge M_AXI_ACLK ) begin
if(!M_AXI_ARESETN ) begin
arbitration_wr_state <= 'd0;
end
else if(DDR_INIT_DONE)begin
case(arbitration_wr_state)
M0_WRITE:
begin
if(M0_AXI_WLAST) begin//µÚÒ»´Î´«ÊäÍê³É£¬¶ÔµÚ¶þ¸öÖ÷»ú½øÐд«Êä
arbitration_wr_state <= M1_WRITE;
end
else if( (!(wfifo0_state == 'd3)) && (wfifo0_rd_water_level < M_AXI_BRUST_LEN) && (wr_addr_cnt0 < wr_addr_max - M_AXI_BRUST_LEN * 8 )) begin
arbitration_wr_state <= M1_WRITE;
end
end
M1_WRITE:
begin
if(M1_AXI_WLAST) begin
arbitration_wr_state <= M2_WRITE;
end
else if( (!(wfifo1_state == 'd3)) && (wfifo1_rd_water_level < M_AXI_BRUST_LEN)&& (wr_addr_cnt1 < wr_addr_max - M_AXI_BRUST_LEN * 8 )) begin
arbitration_wr_state <= M2_WRITE;
end
end
M2_WRITE:
begin
if(M2_AXI_WLAST) begin
arbitration_wr_state <= M3_WRITE;
end
else if((!(wfifo2_state == 'd3)) && (wfifo2_rd_water_level < M_AXI_BRUST_LEN)&& (wr_addr_cnt2 < wr_addr_max - M_AXI_BRUST_LEN * 8 )) begin
arbitration_wr_state <= M3_WRITE;
end
end
M3_WRITE:
begin
if(M3_AXI_WLAST) begin
arbitration_wr_state <= M0_WRITE;
end
else if((!(wfifo3_state == 'd3)) && (wfifo3_rd_water_level < M_AXI_BRUST_LEN)&& (wr_addr_cnt3 < wr_addr_max - M_AXI_BRUST_LEN * 8 )) begin
arbitration_wr_state <= M0_WRITE;
end
end
endcase
end
else begin
arbitration_wr_state <= arbitration_wr_state;
end
end
//¶Á״̬»ú£¬ÒÀ´Î¶Á
always @(posedge M_AXI_ACLK ) begin
if(!M_AXI_ARESETN || rd_rst) begin
arbitration_rd_state <= READ_ARBITRATION;
rfifo_pre_write_init <= 3'd0;//rfifoԤдÈë±êÖ¾£¬Ò»Ö¡¿ªÊ¼Ê±ÏòËĸöÖ÷»úÂÖÁ÷ÏòrfifoԤдÈëÒ»ÐÐÊý¾Ý
end
else if(DDR_INIT_DONE)begin
case(arbitration_rd_state)
READ_ARBITRATION:
begin
if(!rfifo_pre_write_init) begin
if(rfifo0_wr_water_level < ZOOM_VIDEO_LENGTH*PIXEL_WIDTH/256*2 ) begin//rfifo0ԤдÍêÒ»ÐкóÇл»µ½ÏÂÒ»¸örfifo
arbitration_rd_state <= M0_READ;
end
else if(rfifo1_wr_water_level < ZOOM_VIDEO_LENGTH*PIXEL_WIDTH/256*2 ) begin
arbitration_rd_state <= M1_READ;
end
else if(rfifo2_wr_water_level < ZOOM_VIDEO_LENGTH*PIXEL_WIDTH/256*2 ) begin
arbitration_rd_state <= M2_READ;
end
else if(rfifo3_wr_water_level < ZOOM_VIDEO_LENGTH*PIXEL_WIDTH/256*2 ) begin
arbitration_rd_state <= M3_READ;
end
else begin
rfifo_pre_write_init <= 1'd1;//Ëĸörfifo¶¼Ð´Íêºó±êÖ¾ÖÃ1£¬ÔÚ²»Í¬ÇøÓò¶Ôrfifo½øÐÐдÈë
end
end
else if(r_video0_rd_en_d0 || r_video1_rd_en_d0) begin
arbitration_rd_state <= M0_READ;
end
//else if(r_video1_rd_en_d0) begin
// arbitration_rd_state <= M1_READ;
//end
else if(r_video2_rd_en_d0 || r_video3_rd_en_d0) begin
arbitration_rd_state <= M2_READ;
end
//else if(r_video3_rd_en_d0) begin
// arbitration_rd_state <= M3_READ;
//end
else begin
arbitration_rd_state <= arbitration_rd_state;
end
end
M0_READ:
begin
if(fram0_done) begin
//if(M0_AXI_RLAST) begin//µÚÒ»´Î´«ÊäÍê³É£¬¶ÔµÚ¶þ¸öÖ÷»ú½øÐд«Êä
// arbitration_rd_state <= READ_ARBITRATION;
//end
if((rfifo0_wr_water_level >= 'd120) && (rfifo0_state == 1)) begin
arbitration_rd_state <= M1_READ;
end
else begin
arbitration_rd_state <= arbitration_rd_state;
end
end
else begin
arbitration_rd_state <= READ_ARBITRATION;
end
end
M1_READ:
begin
if(fram1_done) begin
//if(M1_AXI_RLAST) begin//µÚÒ»´Î´«ÊäÍê³É£¬¶ÔµÚ¶þ¸öÖ÷»ú½øÐд«Êä
// arbitration_rd_state <= READ_ARBITRATION;
//end
if((rfifo1_wr_water_level >= 'd120)&& (rfifo1_state == 1)) begin
arbitration_rd_state <= READ_ARBITRATION;
end
else begin
arbitration_rd_state <= arbitration_rd_state;
end
end
else begin
arbitration_rd_state <= READ_ARBITRATION;
end
end
M2_READ:
begin
if(fram2_done) begin
//if(M2_AXI_RLAST) begin//µÚÒ»´Î´«ÊäÍê³É£¬¶ÔµÚ¶þ¸öÖ÷»ú½øÐд«Êä
// arbitration_rd_state <= READ_ARBITRATION;
//end
if((rfifo2_wr_water_level >= 'd120)&& (rfifo2_state == 1)) begin
arbitration_rd_state <= M3_READ;
end
else begin
arbitration_rd_state <= arbitration_rd_state;
end
end
else begin
arbitration_rd_state <= READ_ARBITRATION;
end
end
M3_READ:
begin
if(fram3_done) begin
//if(M3_AXI_RLAST) begin//µÚÒ»´Î´«ÊäÍê³É£¬¶ÔµÚ¶þ¸öÖ÷»ú½øÐд«Êä
// arbitration_rd_state <= READ_ARBITRATION;
//end
if( (rfifo3_wr_water_level >= 'd120 )&& (rfifo3_state == 1)) begin
arbitration_rd_state <= READ_ARBITRATION;
end
else begin
arbitration_rd_state <= arbitration_rd_state;
end
end
else begin
arbitration_rd_state <= READ_ARBITRATION;
end
end
default :
arbitration_rd_state <= READ_ARBITRATION;
endcase
end
else begin
arbitration_rd_state <= READ_ARBITRATION;
end
end
//********************************Àý»¯**********************************//
//Àý»¯AXI_FULL_M
//AXIÖ÷»ú0
AXI_FULL_M #(
.VIDEO_LENGTH (ZOOM_VIDEO_LENGTH) ,
.VIDEO_HIGTH (ZOOM_VIDEO_HIGTH ) ,
.PIXEL_WIDTH (PIXEL_WIDTH ) ,
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH ) ,
.DQ_WIDTH (DQ_WIDTH ) ,
.M_AXI_BRUST_LEN (M_AXI_BRUST_LEN ) ,
.VIDEO_BASE_ADDR (VIDEO0_BASE_ADDR )
)
u_axi_full_m0
(
.DDR_INIT_DONE (DDR_INIT_DONE ) ,//input wire
.M_AXI_ACLK (M_AXI_ACLK ) ,//input wire
.M_AXI_ARESETN (M_AXI_ARESETN) ,//input wire
//дµØַͨµÀ¡ý
.M_AXI_AWADDR (M0_AXI_AWADDR ) , //output wire
.M_AXI_AWVALID (M0_AXI_AWVALID ) , //output wire
.M_AXI_AWREADY (M0_AXI_AWREADY ) , //input wire
//дÊý¾ÝͨµÀ¡ý //дÊý¾ÝͨµÀ¡ý
.M_AXI_WLAST (M0_AXI_WLAST ) , //input wire
.M_AXI_WREADY (M0_AXI_WREADY ) , //input wire
//дÏìӦͨµÀ¡ý //дÏìӦͨµÀ¡ý
//¶ÁµØַͨµÀ¡ý //¶ÁµØַͨµÀ¡ý
.M_AXI_ARADDR (M0_AXI_ARADDR ) , //output wire
.M_AXI_ARVALID (M0_AXI_ARVALID ) , //output wire
.M_AXI_ARREADY (M0_AXI_ARREADY ) , //input wire
//¶ÁÊý¾ÝͨµÀ¡ý //¶ÁÊý¾ÝͨµÀ¡ý
.M_AXI_RLAST (M0_AXI_RLAST ) , //input wire
.M_AXI_RVALID (M0_AXI_RVALID ) , //input wire
//video ////video
.vs_in (video0_vs_in ) , //input wire
.vs_out (vs_out ) , //input wire
//fifo ////fifoÐźÅ
.wfifo_rd_water_level(wfifo0_rd_water_level) , //input wire
.wfifo_rd_req (wfifo0_rd_req ) , //output
.wfifo_pre_rd_req (wfifo0_pre_rd_req ) , //output
.rfifo_wr_water_level(rfifo0_wr_water_level) , //input wire
.rfifo_wr_req (rfifo0_wr_req ) , // output
.r_fram_done (fram0_done ) , // output reg
//ÆäËû
.wr_addr_min (wr_addr_min ) , // input
.wr_addr_max (wr_addr_max ) , // input
.r_wr_rst (wr_rst ) ,
.r_rd_rst (rd_rst ) ,
.w_fifo_state (wfifo0_state ) ,
.r_fifo_state (rfifo0_state ) ,
.wr_addr_cnt (wr_addr_cnt0 )
);
//AXIÖ÷»ú1
AXI_FULL_M #(
.VIDEO_LENGTH (ZOOM_VIDEO_LENGTH) ,
.VIDEO_HIGTH (ZOOM_VIDEO_HIGTH ) ,
.PIXEL_WIDTH (PIXEL_WIDTH ) ,
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH ) ,
.DQ_WIDTH (DQ_WIDTH ) ,
.M_AXI_BRUST_LEN (M_AXI_BRUST_LEN ) ,
.VIDEO_BASE_ADDR (VIDEO1_BASE_ADDR )
)
u_axi_full_m1
(
.DDR_INIT_DONE (DDR_INIT_DONE ) ,
.M_AXI_ACLK (M_AXI_ACLK ) ,
.M_AXI_ARESETN (M_AXI_ARESETN) ,
//дµØַͨµÀ¡ý
.M_AXI_AWADDR (M1_AXI_AWADDR ) ,
.M_AXI_AWVALID (M1_AXI_AWVALID ) ,
.M_AXI_AWREADY (M1_AXI_AWREADY ) ,
//дÊý¾ÝͨµÀ¡ý
.M_AXI_WLAST (M1_AXI_WLAST ) ,
.M_AXI_WREADY (M1_AXI_WREADY ) ,
//дÏìӦͨµÀ¡ý
//¶ÁµØַͨµÀ¡ý
.M_AXI_ARADDR (M1_AXI_ARADDR ) ,
.M_AXI_ARVALID (M1_AXI_ARVALID ) ,
.M_AXI_ARREADY (M1_AXI_ARREADY ) ,
//¶ÁÊý¾ÝͨµÀ¡ý
.M_AXI_RLAST (M1_AXI_RLAST ) ,
.M_AXI_RVALID (M1_AXI_RVALID ) ,
//video
.vs_in (video1_vs_in ) ,
.vs_out (vs_out ) ,
//fifo
.wfifo_rd_water_level(wfifo1_rd_water_level),
.wfifo_rd_req (wfifo1_rd_req ) ,
.wfifo_pre_rd_req (wfifo1_pre_rd_req ),
.rfifo_wr_water_level(rfifo1_wr_water_level),
.rfifo_wr_req (rfifo1_wr_req ) ,
.r_fram_done (fram1_done ) ,
.wr_addr_min (wr_addr_min ) ,
.wr_addr_max (wr_addr_max ) ,
.r_wr_rst ( ) ,
.r_rd_rst ( ) ,
.w_fifo_state (wfifo1_state) ,
.r_fifo_state (rfifo1_state) ,
.wr_addr_cnt (wr_addr_cnt1 )
);
//AXIÖ÷»ú2
AXI_FULL_M #(
.VIDEO_LENGTH (ZOOM_VIDEO_LENGTH) ,
.VIDEO_HIGTH (ZOOM_VIDEO_HIGTH ) ,
.PIXEL_WIDTH (PIXEL_WIDTH ) ,
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH ) ,
.DQ_WIDTH (DQ_WIDTH ) ,
.M_AXI_BRUST_LEN (M_AXI_BRUST_LEN ) ,
.VIDEO_BASE_ADDR (VIDEO2_BASE_ADDR )
)
u_axi_full_m2
(
.DDR_INIT_DONE (DDR_INIT_DONE ) ,
.M_AXI_ACLK (M_AXI_ACLK ) ,
.M_AXI_ARESETN (M_AXI_ARESETN) ,
//дµØַͨµÀ¡ý
.M_AXI_AWADDR (M2_AXI_AWADDR ) ,
.M_AXI_AWVALID (M2_AXI_AWVALID ) ,
.M_AXI_AWREADY (M2_AXI_AWREADY ) ,
//дÊý¾ÝͨµÀ¡ý
.M_AXI_WLAST (M2_AXI_WLAST ) ,
.M_AXI_WREADY (M2_AXI_WREADY ) ,
//дÏìӦͨµÀ¡ý
//¶ÁµØַͨµÀ¡ý
.M_AXI_ARADDR (M2_AXI_ARADDR ) ,
.M_AXI_ARVALID (M2_AXI_ARVALID ) ,
.M_AXI_ARREADY (M2_AXI_ARREADY ) ,
//¶ÁÊý¾ÝͨµÀ¡ý
.M_AXI_RLAST (M2_AXI_RLAST ) ,
.M_AXI_RVALID (M2_AXI_RVALID ) ,
//video
.vs_in (video2_vs_in ) ,
.vs_out (vs_out ) ,
//fifo
.wfifo_rd_water_level(wfifo2_rd_water_level),
.wfifo_rd_req (wfifo2_rd_req ) ,
.wfifo_pre_rd_req (wfifo2_pre_rd_req ),
.rfifo_wr_water_level(rfifo2_wr_water_level),
.rfifo_wr_req (rfifo2_wr_req ) ,
.r_fram_done (fram2_done ) ,
.wr_addr_min (wr_addr_min ) ,
.wr_addr_max (wr_addr_max ) ,
.r_wr_rst ( ) ,
.r_rd_rst ( ) ,
.w_fifo_state (wfifo2_state) ,
.r_fifo_state (rfifo2_state) ,
.wr_addr_cnt (wr_addr_cnt2 )
);
//AXIÖ÷»ú3
AXI_FULL_M #(
.VIDEO_LENGTH (ZOOM_VIDEO_LENGTH) ,
.VIDEO_HIGTH (ZOOM_VIDEO_HIGTH ) ,
.PIXEL_WIDTH (PIXEL_WIDTH ) ,
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH ) ,
.DQ_WIDTH (DQ_WIDTH ) ,
.M_AXI_BRUST_LEN (M_AXI_BRUST_LEN ) ,
.VIDEO_BASE_ADDR (VIDEO3_BASE_ADDR )
)
u_axi_full_m3
(
.DDR_INIT_DONE (DDR_INIT_DONE ) ,
.M_AXI_ACLK (M_AXI_ACLK ) ,
.M_AXI_ARESETN (M_AXI_ARESETN) ,
//дµØַͨµÀ¡ý
.M_AXI_AWADDR (M3_AXI_AWADDR ) ,
.M_AXI_AWVALID (M3_AXI_AWVALID ) ,
.M_AXI_AWREADY (M3_AXI_AWREADY ) ,
//дÊý¾ÝͨµÀ¡ý
.M_AXI_WLAST (M3_AXI_WLAST ) ,
.M_AXI_WREADY (M3_AXI_WREADY ) ,
//дÏìӦͨµÀ¡ý
//¶ÁµØַͨµÀ¡ý
.M_AXI_ARADDR (M3_AXI_ARADDR ) ,
.M_AXI_ARVALID (M3_AXI_ARVALID ) ,
.M_AXI_ARREADY (M3_AXI_ARREADY ) ,
//¶ÁÊý¾ÝͨµÀ¡ý
.M_AXI_RLAST (M3_AXI_RLAST ) ,
.M_AXI_RVALID (M3_AXI_RVALID ) ,
//video
.vs_in (video3_vs_in ) ,
.vs_out (vs_out ) ,
//fifo
.wfifo_rd_water_level(wfifo3_rd_water_level),
.wfifo_rd_req (wfifo3_rd_req ) ,
.wfifo_pre_rd_req (wfifo3_pre_rd_req ),
.rfifo_wr_water_level(rfifo3_wr_water_level),
.rfifo_wr_req (rfifo3_wr_req ) ,
.r_fram_done (fram3_done ) ,
.wr_addr_min (wr_addr_min ) ,
.wr_addr_max (wr_addr_max ) ,
.r_wr_rst ( ) ,
.r_rd_rst ( ) ,
.w_fifo_state (wfifo3_state) ,
.r_fifo_state (rfifo3_state) ,
.wr_addr_cnt (wr_addr_cnt3 )
);
//µÚ0×éFIFO
rw_fifo_ctrl user_rw_fifo_ctrl0(
.rstn (M_AXI_ARESETN),//ϵͳ¸´Î»,DDRδ³õʼ»¯Íê³Éʱ±£³Ö¸´Î»×´Ì¬
.ddr_clk (M_AXI_ACLK ),//дÈëÄÚ´æµÄʱÖÓ£¨ÄÚ´æaxi4½Ó¿ÚʱÖÓ£©
//hdmi_wfifo_ddr
.wfifo_wr_clk (video0_clk_in ),//wfifoдʱÖÓ
.wfifo_wr_en (video0_de_in ),//wfifoÊäÈëʹÄÜ
.wfifo_wr_data32_in (video0_data_in ),//wfifoÊäÈëÊý¾Ý,32bits
.wfifo_rd_req (wfifo0_rd_req || wfifo0_pre_rd_req),//wfifo¶ÁÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
.wfifo_rd_water_level (wfifo0_rd_water_level),//wfifo¶Áˮ룬µ±ÊýÁ¿´óÓÚÍ»·¢³¤¶Èʱ¿ªÊ¼´«Êä
.wfifo_rd_data256_out (M0_AXI_WDATA ),//wfifo¶ÁÊý¾Ý£¬256bits
//ddr_rfifo_hdmi
.rfifo_rd_clk (pix_clk_out) ,//rfifo¶ÁʱÖÓ
.rfifo_rd_en (video0_rd_en ) ,//rfifo¶Á³öʹÄÜ
.rfifo_rd_data32_out (video0_data_out) ,//rfifoÊäÈëÊý¾Ý,32bits
.rfifo_wr_req (rfifo0_wr_req) ,//rfifoдÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
.rfifo_wr_water_level (rfifo0_wr_water_level),//rfifoдˮ룬µ±ÊýÁ¿Ð¡ÓÚÒ»ÐÐÊý¾Ýʱ¿ªÊ¼´«Êä
.rfifo_wr_data256_in (M0_AXI_RDATA) ,//rfifoдÊý¾Ý£¬256bits
.vs_in (video0_vs_in ) ,
.vs_out (vs_out )
);
//µÚ1×éFIFO
rw_fifo_ctrl user_rw_fifo_ctrl1(
.rstn (M_AXI_ARESETN),//ϵͳ¸´Î»,DDRδ³õʼ»¯Íê³Éʱ±£³Ö¸´Î»×´Ì¬
.ddr_clk (M_AXI_ACLK ),//дÈëÄÚ´æµÄʱÖÓ£¨ÄÚ´æaxi4½Ó¿ÚʱÖÓ£©
//hdmi_wfifo_ddr
.wfifo_wr_clk (video1_clk_in ),//wfifoдʱÖÓ
.wfifo_wr_en (video1_de_in ),//wfifoÊäÈëʹÄÜ
.wfifo_wr_data32_in (video1_data_in ),//wfifoÊäÈëÊý¾Ý,32bits
.wfifo_rd_req (wfifo1_rd_req || wfifo1_pre_rd_req),//wfifo¶ÁÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
.wfifo_rd_water_level (wfifo1_rd_water_level),//wfifo¶Áˮ룬µ±ÊýÁ¿´óÓÚÍ»·¢³¤¶Èʱ¿ªÊ¼´«Êä
.wfifo_rd_data256_out (M1_AXI_WDATA ),//wfifo¶ÁÊý¾Ý£¬256bits
//ddr_rfifo_hdmi
.rfifo_rd_clk (pix_clk_out) ,//rfifo¶ÁʱÖÓ
.rfifo_rd_en (video1_rd_en) ,//rfifo¶Á³öʹÄÜ
.rfifo_rd_data32_out (video1_data_out) ,//rfifoÊäÈëÊý¾Ý,16bits
.rfifo_wr_req (rfifo1_wr_req) ,//rfifoдÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
.rfifo_wr_water_level (rfifo1_wr_water_level),//rfifoдˮ룬µ±ÊýÁ¿Ð¡ÓÚÍ»·¢³¤¶Èʱ¿ªÊ¼´«Êä
.rfifo_wr_data256_in (M1_AXI_RDATA) , //rfifoдÊý¾Ý£¬256bits
.vs_in (video1_vs_in ) ,
.vs_out (vs_out )
);
//µÚ2×éFIFO
rw_fifo_ctrl user_rw_fifo_ctrl2(
.rstn (M_AXI_ARESETN),//ϵͳ¸´Î»,DDRδ³õʼ»¯Íê³Éʱ±£³Ö¸´Î»×´Ì¬
.ddr_clk (M_AXI_ACLK ),//дÈëÄÚ´æµÄʱÖÓ£¨ÄÚ´æaxi4½Ó¿ÚʱÖÓ£©
//hdmi_wfifo_ddr
.wfifo_wr_clk (video2_clk_in ),//wfifoдʱÖÓ
.wfifo_wr_en (video2_de_in ),//wfifoÊäÈëʹÄÜ
.wfifo_wr_data32_in (video2_data_in ),//wfifoÊäÈëÊý¾Ý,32bits
.wfifo_rd_req (wfifo2_rd_req || wfifo2_pre_rd_req),//wfifo¶ÁÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
.wfifo_rd_water_level (wfifo2_rd_water_level),//wfifo¶Áˮ룬µ±ÊýÁ¿´óÓÚÍ»·¢³¤¶Èʱ¿ªÊ¼´«Êä
.wfifo_rd_data256_out (M2_AXI_WDATA ),//wfifo¶ÁÊý¾Ý£¬256bits
//ddr_rfifo_hdmi
.rfifo_rd_clk (pix_clk_out) ,//rfifo¶ÁʱÖÓ
.rfifo_rd_en (video2_rd_en) ,//rfifo¶Á³öʹÄÜ
.rfifo_rd_data32_out (video2_data_out) ,//rfifoÊäÈëÊý¾Ý,16bits
.rfifo_wr_req (rfifo2_wr_req) ,//rfifoдÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
.rfifo_wr_water_level (rfifo2_wr_water_level),//rfifoдˮ룬µ±ÊýÁ¿Ð¡ÓÚÍ»·¢³¤¶Èʱ¿ªÊ¼´«Êä
.rfifo_wr_data256_in (M2_AXI_RDATA) , //rfifoдÊý¾Ý£¬256bits
.vs_in (video2_vs_in ) ,
.vs_out (vs_out )
);
//µÚ3×éFIFO
rw_fifo_ctrl user_rw_fifo_ctrl3(
.rstn (M_AXI_ARESETN),//ϵͳ¸´Î»,DDRδ³õʼ»¯Íê³Éʱ±£³Ö¸´Î»×´Ì¬
.ddr_clk (M_AXI_ACLK ),//дÈëÄÚ´æµÄʱÖÓ£¨ÄÚ´æaxi4½Ó¿ÚʱÖÓ£©
//hdmi_wfifo_ddr
.wfifo_wr_clk (video3_clk_in ),//wfifoдʱÖÓ
.wfifo_wr_en (video3_de_in ),//wfifoÊäÈëʹÄÜ
.wfifo_wr_data32_in (video3_data_in ),//wfifoÊäÈëÊý¾Ý,32bits
.wfifo_rd_req (wfifo3_rd_req || wfifo3_pre_rd_req),//wfifo¶ÁÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
.wfifo_rd_water_level (wfifo3_rd_water_level),//wfifo¶Áˮ룬µ±ÊýÁ¿´óÓÚÍ»·¢³¤¶Èʱ¿ªÊ¼´«Êä
.wfifo_rd_data256_out (M3_AXI_WDATA ),//wfifo¶ÁÊý¾Ý£¬256bits
//ddr_rfifo_hdmi
.rfifo_rd_clk (pix_clk_out) ,//rfifo¶ÁʱÖÓ
.rfifo_rd_en (video3_rd_en) ,//rfifo¶Á³öʹÄÜ
.rfifo_rd_data32_out (video3_data_out) ,//rfifoÊäÈëÊý¾Ý,32bits
.rfifo_wr_req (rfifo3_wr_req ) ,//rfifoдÇëÇ󣬵±ÊýÁ¿´óÓÚÍ»·¢³¤¶ÈʱÀ¸ß
.rfifo_wr_water_level (rfifo3_wr_water_level),//rfifoдˮ룬µ±ÊýÁ¿Ð¡ÓÚÍ»·¢³¤¶Èʱ¿ªÊ¼´«Êä
.rfifo_wr_data256_in (M3_AXI_RDATA) , //rfifoдÊý¾Ý£¬256bits
.vs_in (video3_vs_in ) ,
.vs_out (vs_out )
);
endmodule |
module video_zoom #(
parameter PIXEL_WIDTH = 32 ,
parameter VIDEO_LENGTH = 12'd1920 ,
parameter VIDEO_HIGTH = 12'd1080
//·Ç±ê×¼VESAʱÐò£¬½ö×ö·ÂÕæʹÓ᣷ֱæÂÊΪ128*72£¨ÎªÁË·½±ã²âÊÔ£¬Ä¿±êËõ·Å·Ö±æÂÊΪ64*36
)(
input clk ,
input rstn ,
input vs_in /* synthesis PAP_MARK_DEBUG="1" */,
input hs_in ,
input de_in /* synthesis PAP_MARK_DEBUG="1" */,
input [PIXEL_WIDTH - 1 : 0] video_data_in ,
output reg de_out /* synthesis PAP_MARK_DEBUG="1" */,
output reg [PIXEL_WIDTH - 1 : 0] video_data_out /* synthesis PAP_MARK_DEBUG="1" */
);
parameter VIDEO_WAIT = 2'd0;
parameter VIDEO_ZOOM = 2'd1;
parameter VIDEO_END = 2'd2;
parameter FIRST_PIX = 2'd0;
parameter SECOND_PIX = 2'd1;
parameter THIRD_PIX = 2'd2;
parameter FOURTH_PIX = 2'd3;
parameter FIRST_LINE = 2'd0;
parameter SECOND_LINE = 2'd1;
parameter THIRD_LINE = 2'd2;
parameter FOURTH_LINE = 2'd3;
parameter DE_IN_WAIT = 1'd0;
parameter DE_IN_CNT = 1'd1;
parameter OFFSET_ADDR = 11'd0;
parameter DELAY_OUTPUT = 11'd2;
wire [PIXEL_WIDTH - 1 : 0] ram0_rd_data/* synthesis PAP_MARK_DEBUG="1" */;
wire [PIXEL_WIDTH - 1 : 0] ram1_rd_data/* synthesis PAP_MARK_DEBUG="1" */;
wire vs_rst/* synthesis PAP_MARK_DEBUG="1" */;
reg [PIXEL_WIDTH - 1 : 0] pix_data0/* synthesis PAP_MARK_DEBUG="1" */;//ÓÃÓÚ½ÓÊÕµ¥¸öÊý¾Ý
reg [PIXEL_WIDTH - 1 : 0] pix_data1/* synthesis PAP_MARK_DEBUG="1" */;//ÿ½ÓÊÕÁ½¸ö½øÐÐÒ»´ÎÏßÐÔ²å
reg [PIXEL_WIDTH - 1 : 0] pix_data2/* synthesis PAP_MARK_DEBUG="1" */;
reg [PIXEL_WIDTH - 1 : 0] pix_data3/* synthesis PAP_MARK_DEBUG="1" */;
reg [PIXEL_WIDTH - 1 : 0] r_ram0_wr_data;
reg [10 : 0] r_ram0_wr_addr/* synthesis PAP_MARK_DEBUG="1" */;
reg [PIXEL_WIDTH - 1 : 0] r_ram1_wr_data;
reg [10 : 0] r_ram1_wr_addr /* synthesis PAP_MARK_DEBUG="1" */;
reg [10 : 0] r_ram0_rd_addr /* synthesis PAP_MARK_DEBUG="1" */;
reg [10 : 0] r_ram1_rd_addr /* synthesis PAP_MARK_DEBUG="1" */;
reg r_ram0_wr_en /* synthesis PAP_MARK_DEBUG="1" */;
reg r_ram1_wr_en /* synthesis PAP_MARK_DEBUG="1" */;
reg [1 : 0] interpolation_cnt_state /* synthesis PAP_MARK_DEBUG="1" */; //µ¥ÏßÐÔ²åÖµ¼ÆÊý״̬
reg interpolation_data_save /* synthesis PAP_MARK_DEBUG="1" */; //µ¥ÏßÐÔ²åÖµÍê³É±êÖ¾
reg interpolation_data_save_flag /* synthesis PAP_MARK_DEBUG="1" */; //ÓÃÓÚÇл»pix_data´æÈëRAM
reg interpolation_done0 /* synthesis PAP_MARK_DEBUG="1" */;
reg interpolation_done1 /* synthesis PAP_MARK_DEBUG="1" */;
reg [9 : 0] interpolation_cnt /* synthesis PAP_MARK_DEBUG="1" */;
reg [1 : 0] interpolation_data_state /* synthesis PAP_MARK_DEBUG="1" */;
reg [9 : 0] bilinear_interpolation_cnt /* synthesis PAP_MARK_DEBUG="1" */;
reg bilinear_interpolation_flag /* synthesis PAP_MARK_DEBUG="1" */;
reg de_in_state;
reg [11 : 0] de_in_cnt /* synthesis PAP_MARK_DEBUG="1" */;
reg de_in_d0 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_in_d1 /* synthesis PAP_MARK_DEBUG="1" */;
reg vs_in_d0 /* synthesis PAP_MARK_DEBUG="1" */;
reg vs_in_d1 /* synthesis PAP_MARK_DEBUG="1" */;
reg [10 : 0] pix_cnt /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_state;
reg [11 : 0] de_out_cnt /* synthesis PAP_MARK_DEBUG="1" */;
wire w_de_out /* synthesis PAP_MARK_DEBUG="1" */;
reg [19 : 0] de_out_ff /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d0 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d1 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d2 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d3 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d4 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d5 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d6 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d7 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d8 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d9 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d10 /* synthesis PAP_MARK_DEBUG="1" */;
reg de_out_d11 /* synthesis PAP_MARK_DEBUG="1" */;
reg ram0_rd_oce /* synthesis PAP_MARK_DEBUG="1" */;
reg ram1_rd_oce /* synthesis PAP_MARK_DEBUG="1" */;
assign w_de_out = de_out;
assign vs_rst = !vs_in_d0 && vs_in_d1;
always @(posedge clk) begin//ץϽµÑØ
if(!rstn) begin
vs_in_d0 <= 'd0;
vs_in_d1 <= 'd0;
de_in_d0 <= 'd0;
de_in_d1 <= 'd0;
de_in_cnt <= 'd0;
de_in_state <= 'd0;
end
else begin
vs_in_d0 <= vs_in;
vs_in_d1 <= vs_in_d0;
de_in_d0 <= de_in;
de_in_d1 <= de_in_d0;
case(de_in_state)
DE_IN_WAIT:
begin
if(!vs_in_d0 && vs_in_d1) begin
de_in_state <= DE_IN_CNT;//ץȡvs_inϽµÑØ£¬µ±×¥µ½Ï½µÑØʱ¿ªÊ¼¼ÆÊý
end
end
DE_IN_CNT:
begin
if(de_in_d0 && !de_in_d1) begin
de_in_cnt <= de_in_cnt + 1'd1;//ץȡdeÉÏÉýÑØ£¬deÉÏÉýʱ¼ÆÊý
end
if(vs_in_d0 && !vs_in_d1) begin
de_in_cnt <= 'd0;
de_in_state <= DE_IN_WAIT;//ץȡvs_inÉÏÉýÑØ£¬µ±×¥µ½ÉÏÉýÑØʱ¼ÆÊý¹éÁã
end
end
endcase
end
end
always @(posedge clk) begin//ץϽµÑØ
if(!rstn) begin
de_out_ff <= 'd0;
de_out_cnt <= 'd0;
de_out_state <= 'd0;
end
else begin
de_out_ff <= {de_out_ff[18 : 0] , de_out};
case(de_out_state)
DE_IN_WAIT:
begin
if(!vs_in_d0 && vs_in_d1) begin
de_out_state <= DE_IN_CNT;//ץȡvs_inϽµÑØ£¬µ±×¥µ½Ï½µÑØʱ¿ªÊ¼¼ÆÊý
end
end
DE_IN_CNT:
begin
if(de_out_ff[0] && !de_out_ff[1]) begin
de_out_cnt <= de_out_cnt + 1'd1;//ץȡdeÉÏÉýÑØ£¬deÉÏÉýʱ¼ÆÊý
end
if(vs_in_d0 && !vs_in_d1) begin
de_out_cnt <= 'd0;
de_out_state <= DE_IN_WAIT;//ץȡvs_inÉÏÉýÑØ£¬µ±×¥µ½ÉÏÉýÑØʱ¼ÆÊý¹éÁã
end
end
endcase
end
end
//¶ÔÊäÈëµÄÊý¾Ý½øÐÐÔÝ´æ
always @(posedge clk) begin
if(!rstn || vs_rst) begin
interpolation_cnt_state <= 'd0;
interpolation_data_save <= 'd0;
interpolation_data_save_flag <= 'd0;
pix_data0 <= 'd0;
pix_data1 <= 'd0;
pix_data2 <= 'd0;
pix_data3 <= 'd0;
pix_cnt <= 'd0;
end
else if(de_in || de_in_d0) begin//deÀ¸ßºó¶ÔÊäÈëµÄÊý¾Ý½øÐÐÔÝ´æ
pix_cnt <= pix_cnt + 'd1;
case(interpolation_cnt_state)
FIRST_PIX: begin
pix_data0 <= video_data_in;
interpolation_data_save <= 1'b0;//ÔÝ´æµÚÒ»¸öÊý¾Ý
interpolation_cnt_state <= 2'd1;
end
SECOND_PIX: begin
pix_data1 <= video_data_in;//ÔÝ´æµÚ¶þ¸öÊý¾Ý£¬È»ºóÀ¸ßdone
interpolation_data_save_flag <= 'd0;
interpolation_data_save <= 1'b1;
interpolation_cnt_state <= 2'd2;
end
THIRD_PIX: begin
pix_data2 <= video_data_in;//ÔÝ´æµÚ3¸öÊý¾Ý
interpolation_cnt_state <= 2'd3;
interpolation_data_save <= 1'b0;
end
FOURTH_PIX: begin
pix_data3 <= video_data_in;//ÔÝ´æµÚ4¸öÊý¾Ý£¬È»ºóÀ¸ßsave
interpolation_data_save_flag <= 'd1;
interpolation_data_save <= 1'b1;
interpolation_cnt_state <= 2'd0;
end
endcase
end
else begin
pix_cnt <= 'd0;
pix_data0 <= 'd0;
pix_data1 <= 'd0;
pix_data2 <= 'd0;
pix_data3 <= 'd0;
interpolation_cnt_state <= 1'b0;
interpolation_data_save <= 1'b0;
interpolation_data_save_flag <= 'd0;
end
end
//¶ÔÊäÈëµÄÊý¾Ý½øÐеÚÒ»´ÎÏßÐÔ²åÖµ
always @(posedge clk) begin
if(!rstn || vs_rst) begin
interpolation_cnt <= 'd0 + OFFSET_ADDR;
interpolation_data_state <= 'd0;
r_ram0_wr_en <= 1'b0;
r_ram1_wr_en <= 1'b0;
r_ram0_wr_data <= 'd0;
r_ram1_wr_data <= 'd0;
r_ram0_wr_addr <= 'd0;
r_ram1_wr_addr <= 'd0;
interpolation_done0 <= 'd0;
interpolation_done1 <= 'd0;
end
else begin//doneÐźÅÀ¸ßºó£¬¶ÔÔÝ´æµÄÁ½¸öÊý¾Ý½øÐÐÒ»´ÎÏßÐÔ²åÖµ£¬Í¬Ê±¼ÆÊý£¬µ±²åÖµ´ïµ½ÊÓƵ×ÝÏò·Ö±æÂÊÒ»°ëʱ½áÊø²åÖµ
case(interpolation_data_state)
FIRST_LINE:
begin//µÚÒ»ÐÐÊý¾Ý²åÖµ£¬´æÈëram0µÄpage0ÖÐ
if(interpolation_data_save) begin
r_ram0_wr_addr <= {1'b0,interpolation_cnt};
r_ram0_wr_en <= 1'b1;
interpolation_cnt <= interpolation_cnt + 1'b1;
if(interpolation_data_save_flag == 0) begin//µ±save_flagΪ0ʱ£¬¼ÆËãpix0pix1 дÊý¾Ýµ½ram0//ÇмǽøÐзÖͨµÀ¼ÆËã
//test
//r_ram0_wr_data <= pix_data0 / 2 + pix_data1 / 2;
r_ram0_wr_data[31:22] <= (pix_data0[31:22] / 2) + (pix_data1[31:22] / 2);
r_ram0_wr_data[21:12] <= (pix_data0[21:12] / 2) + (pix_data1[21:12] / 2);
r_ram0_wr_data[11: 2] <= (pix_data0[11: 2] / 2) + (pix_data1[11: 2] / 2);
end
else if(interpolation_data_save_flag == 1) begin
//test
//r_ram0_wr_data <= pix_data2 / 2 + pix_data3 / 2;
r_ram0_wr_data[31:22] <= (pix_data2[31:22] / 2) + (pix_data3[31:22] / 2);
r_ram0_wr_data[21:12] <= (pix_data2[21:12] / 2) + (pix_data3[21:12] / 2);
r_ram0_wr_data[11: 2] <= (pix_data2[11: 2] / 2) + (pix_data3[11: 2] / 2);
end
end
else if(interpolation_cnt == VIDEO_LENGTH/2 + OFFSET_ADDR) begin
r_ram0_wr_en <= 1'b0;
interpolation_cnt <= 'd0 + OFFSET_ADDR;
interpolation_done0 <= 'd0;
interpolation_done1 <= 'd0;
interpolation_data_state <= 'd1;
end
else begin
r_ram0_wr_en <= 'd0;
r_ram1_wr_en <= 'd0;
interpolation_cnt <= interpolation_cnt;
interpolation_data_state <= interpolation_data_state;
end
end
SECOND_LINE:
begin//µÚ¶þÐÐÊý¾Ý²åÖµ,´æÈëram1µÄpage0ÖÐ
if(interpolation_data_save) begin
r_ram1_wr_addr <= {1'b0,interpolation_cnt};
r_ram1_wr_en <= 1'b1;
interpolation_cnt <= interpolation_cnt + 1'b1;
if(interpolation_data_save_flag == 0) begin//µ±save_flagΪ1ʱ£¬¼ÆËãpix2pix3
//test
//r_ram1_wr_data <= pix_data0 / 2 + pix_data1 / 2;
r_ram1_wr_data[31:22] <= (pix_data0[31:22] / 2) + (pix_data1[31:22] / 2);
r_ram1_wr_data[21:12] <= (pix_data0[21:12] / 2) + (pix_data1[21:12] / 2);
r_ram1_wr_data[11: 2] <= (pix_data0[11: 2] / 2) + (pix_data1[11: 2] / 2);
end
else if(interpolation_data_save_flag == 1) begin
//test
//r_ram1_wr_data <= pix_data2 / 2 + pix_data3 / 2;
r_ram1_wr_data[31:22] <= (pix_data2[31:22] / 2) + (pix_data3[31:22] / 2);
r_ram1_wr_data[21:12] <= (pix_data2[21:12] / 2) + (pix_data3[21:12] / 2);
r_ram1_wr_data[11: 2] <= (pix_data2[11: 2] / 2) + (pix_data3[11: 2] / 2);
end
end
else if(interpolation_cnt == VIDEO_LENGTH/2 + OFFSET_ADDR) begin
r_ram1_wr_en <= 1'b0;
interpolation_cnt <= 'd0 + OFFSET_ADDR;
interpolation_done0 <= 'd1;
interpolation_data_state <= 'd2;
end
else begin
r_ram0_wr_en <= 'd0;
r_ram1_wr_en <= 'd0;
interpolation_cnt <= interpolation_cnt;
interpolation_data_state <= interpolation_data_state;
end
end
THIRD_LINE:
begin//ÓÉÓÚÇ°Á½ÐвåÖµÍê³ÉºóÐèÒª½øÐмÆË㣬ËùÒÔ»¹ÐèÒªµÚÈýµÚËÄÐÐÀ´½øÐÐÔÝ´æ,µÚÈýÐÐÊý¾Ý²åÖµ£¬´æÈëram0µÄpage1ÖÐ
if(interpolation_data_save) begin
r_ram0_wr_addr <= {1'b1,interpolation_cnt};
r_ram0_wr_en <= 1'b1;
interpolation_cnt <= interpolation_cnt + 1'b1;
if(interpolation_data_save_flag == 0) begin
//test
//r_ram0_wr_data <= pix_data0 / 2 + pix_data1 / 2;
r_ram0_wr_data[31:22] <= (pix_data0[31:22] / 2) + (pix_data1[31:22] / 2);
r_ram0_wr_data[21:12] <= (pix_data0[21:12] / 2) + (pix_data1[21:12] / 2);
r_ram0_wr_data[11: 2] <= (pix_data0[11: 2] / 2) + (pix_data1[11: 2] / 2);
end
else if(interpolation_data_save_flag == 1) begin
//test
//r_ram0_wr_data <= pix_data2 / 2 + pix_data3 / 2;
r_ram0_wr_data[31:22] <= (pix_data2[31:22] / 2) + (pix_data3[31:22] / 2);
r_ram0_wr_data[21:12] <= (pix_data2[21:12] / 2) + (pix_data3[21:12] / 2);
r_ram0_wr_data[11: 2] <= (pix_data2[11: 2] / 2) + (pix_data3[11: 2] / 2);
end
end
else if(interpolation_cnt == VIDEO_LENGTH/2 + OFFSET_ADDR) begin
r_ram0_wr_en <= 1'b0;
interpolation_cnt <= 'd0 + OFFSET_ADDR;
interpolation_done0 <= 'd0;
interpolation_done1 <= 'd0;
interpolation_data_state <= 'd3;
end
else begin
r_ram0_wr_en <= 'd0;
r_ram1_wr_en <= 'd0;
interpolation_cnt <= interpolation_cnt;
interpolation_data_state <= interpolation_data_state;
end
end
FOURTH_LINE:
begin//µÚ4ÐÐÊý¾Ý²åÖµ£¬´æÈëram1µÄpage1ÖÐ
if(interpolation_data_save) begin
r_ram1_wr_addr <= {1'b1,interpolation_cnt};
r_ram1_wr_en <= 1'b1;
interpolation_cnt <= interpolation_cnt + 1'b1;
if(interpolation_data_save_flag == 0) begin
//test
//r_ram1_wr_data <= pix_data0 / 2 + pix_data1 / 2;
r_ram1_wr_data[31:22] <= (pix_data0[31:22] / 2) + (pix_data1[31:22] / 2);
r_ram1_wr_data[21:12] <= (pix_data0[21:12] / 2) + (pix_data1[21:12] / 2);
r_ram1_wr_data[11: 2] <= (pix_data0[11: 2] / 2) + (pix_data1[11: 2] / 2);
end
else if(interpolation_data_save_flag == 1) begin
//test
//r_ram1_wr_data <= pix_data2 / 2 + pix_data3 / 2;
r_ram1_wr_data[31:22] <= (pix_data2[31:22] / 2) + (pix_data3[31:22] / 2);
r_ram1_wr_data[21:12] <= (pix_data2[21:12] / 2) + (pix_data3[21:12] / 2);
r_ram1_wr_data[11: 2] <= (pix_data2[11: 2] / 2) + (pix_data3[11: 2] / 2);
end
end
else if(interpolation_cnt == VIDEO_LENGTH/2 + OFFSET_ADDR) begin
r_ram1_wr_en <= 1'b0;
interpolation_cnt <= 'd0 + OFFSET_ADDR;
interpolation_done1 <= 'd1;
interpolation_data_state <= 'd0;
end
else begin
r_ram0_wr_en <= 'd0;
r_ram1_wr_en <= 'd0;
interpolation_cnt <= interpolation_cnt;
interpolation_data_state <= interpolation_data_state;
end
end
endcase
end
end
//Íê³ÉÁ½ÐеÄÏßÐÔ²åÖµºó£¬¶Á³ö´æÈëramµÄµÚÒ»´Î²åÖµµÄÊýÖµ£¬½øÐеڶþ´ÎÏßÐÔ²åÖ¡
always @(posedge clk) begin
if(!rstn || vs_rst) begin
bilinear_interpolation_cnt <= 'd0 + OFFSET_ADDR;
r_ram0_rd_addr <= 'd0;
r_ram1_rd_addr <= 'd0;
video_data_out <= 'd0;
de_out <= 'd0;
bilinear_interpolation_flag <= 'd0;
end
else if(interpolation_done0 && !bilinear_interpolation_flag) begin
r_ram0_rd_addr <= {1'b0,bilinear_interpolation_cnt};
r_ram1_rd_addr <= {1'b0,bilinear_interpolation_cnt};
ram0_rd_oce <= 'd1;
ram1_rd_oce <= 'd1;
bilinear_interpolation_cnt <= bilinear_interpolation_cnt + 1'd1;
if(bilinear_interpolation_cnt >= VIDEO_LENGTH/2 + OFFSET_ADDR ) begin
ram0_rd_oce <= 'd0;
ram1_rd_oce <= 'd0;
end
if(bilinear_interpolation_cnt >= VIDEO_LENGTH/2 + OFFSET_ADDR + DELAY_OUTPUT) begin
bilinear_interpolation_cnt <= 'd0 + OFFSET_ADDR;
bilinear_interpolation_flag <= 'd1;
de_out <= 'd0;
end
else if(bilinear_interpolation_cnt >= OFFSET_ADDR + DELAY_OUTPUT) begin //¸øRAM¶ÁµØÖ·ºóÊý¾ÝÑÓ³ÙÈý¸öÖÜÆڲųöÀ´£¬ÕâʱºòÔÙÀ¸ßde_outÊä³öÊý¾Ý
de_out <= 'd1;
//test
//video_data_out <= ram0_rd_data / 2 + ram1_rd_data / 2;
video_data_out[31:22] <= ram0_rd_data[31:22]/2 + ram1_rd_data[31:22]/2;
video_data_out[21:12] <= ram0_rd_data[21:12]/2 + ram1_rd_data[21:12]/2;
video_data_out[11: 2] <= ram0_rd_data[11: 2]/2 + ram1_rd_data[11: 2]/2;
end
end
else if(interpolation_done1 && bilinear_interpolation_flag) begin
r_ram0_rd_addr <= {1'b1,bilinear_interpolation_cnt};
r_ram1_rd_addr <= {1'b1,bilinear_interpolation_cnt};
ram0_rd_oce <= 'd1;
ram1_rd_oce <= 'd1;
bilinear_interpolation_cnt <= bilinear_interpolation_cnt + 1'd1;
if(bilinear_interpolation_cnt >= VIDEO_LENGTH/2 + OFFSET_ADDR ) begin
ram0_rd_oce <= 'd0;
ram1_rd_oce <= 'd0;
end
if(bilinear_interpolation_cnt >= VIDEO_LENGTH/2 + OFFSET_ADDR + DELAY_OUTPUT) begin
bilinear_interpolation_cnt <= 'd0 + OFFSET_ADDR;
bilinear_interpolation_flag <= 'd0;
de_out <= 'd0;
end
else if(bilinear_interpolation_cnt >= OFFSET_ADDR + DELAY_OUTPUT) begin
de_out <= 'd1;
//test
//video_data_out <= ram0_rd_data / 2 + ram1_rd_data / 2;
video_data_out[31:22] <= ram0_rd_data[31:22]/2 + ram1_rd_data[31:22]/2;
video_data_out[21:12] <= ram0_rd_data[21:12]/2 + ram1_rd_data[21:12]/2;
video_data_out[11: 2] <= ram0_rd_data[11: 2]/2 + ram1_rd_data[11: 2]/2;
end
end
else begin
video_data_out <= 'd0;
de_out <= 'd0;
ram0_rd_oce <= 'd0;
ram1_rd_oce <= 'd0;
if(bilinear_interpolation_flag) begin//ÌáÇ°¸´Î»µØÖ·
r_ram0_rd_addr <= {1'b1,bilinear_interpolation_cnt};
r_ram1_rd_addr <= {1'b1,bilinear_interpolation_cnt};
end
else if(!bilinear_interpolation_flag)begin
r_ram0_rd_addr <= {1'b0,bilinear_interpolation_cnt};
r_ram1_rd_addr <= {1'b0,bilinear_interpolation_cnt};
end
end
end
//ramΪ¸ß¸´Î»
interpolation_ram user_interpolation_ram0 (
.wr_data(r_ram0_wr_data), // input [31:0]
.wr_addr(r_ram0_wr_addr), // input [10:0]
.wr_en (r_ram0_wr_en), // input
.wr_clk (clk), // input
.wr_rst (!rstn || vs_rst), // input
.rd_addr(r_ram0_rd_addr), // input [10:0]
.rd_data(ram0_rd_data), // output [31:0]
.rd_clk (clk), // input
//.rd_oce(ram0_rd_oce), // input
.rd_rst (!rstn) // input
);
interpolation_ram user_interpolation_ram1 (
.wr_data(r_ram1_wr_data), // input [31:0]
.wr_addr(r_ram1_wr_addr), // input [10:0]
.wr_en (r_ram1_wr_en), // input
.wr_clk (clk), // input
.wr_rst (!rstn || vs_rst), // input
.rd_addr(r_ram1_rd_addr), // input [10:0]
.rd_data(ram1_rd_data), // output [31:0]
.rd_clk (clk), // input
//.rd_oce(ram1_rd_oce), // input
.rd_rst (!rstn) // input
);
endmodule |
module AXI_FULL_M #
(
parameter integer VIDEO_LENGTH = 1920 ,
parameter integer VIDEO_HIGTH = 1080 ,
parameter integer PIXEL_WIDTH = 32 ,
parameter integer CTRL_ADDR_WIDTH = 28 ,
parameter integer DQ_WIDTH = 32 ,
parameter integer M_AXI_BRUST_LEN = 8 ,
parameter integer VIDEO_BASE_ADDR = 2'd0
)
(
input wire DDR_INIT_DONE ,
input wire M_AXI_ACLK ,
input wire M_AXI_ARESETN ,
//дµØַͨµÀ¡ý
output wire [CTRL_ADDR_WIDTH-1 : 0] M_AXI_AWADDR ,
output wire M_AXI_AWVALID ,
input wire M_AXI_AWREADY ,
//дÊý¾ÝͨµÀ¡ý
input wire M_AXI_WLAST ,
input wire M_AXI_WREADY ,
//дÏìӦͨµÀ¡ý
//¶ÁµØַͨµÀ¡ý
output wire [CTRL_ADDR_WIDTH-1 : 0] M_AXI_ARADDR ,
output wire M_AXI_ARVALID ,
input wire M_AXI_ARREADY ,
//¶ÁÊý¾ÝͨµÀ¡ý
input wire M_AXI_RLAST ,
input wire M_AXI_RVALID ,
//video
input wire vs_in ,
input wire vs_out ,
//fifoÐźÅ
input wire [8 : 0] wfifo_rd_water_level ,
output wfifo_rd_req /* synthesis PAP_MARK_DEBUG="1" */,
output wfifo_pre_rd_req /* synthesis PAP_MARK_DEBUG="1" */,
input wire [8 : 0] rfifo_wr_water_level ,
output rfifo_wr_req ,
output reg r_fram_done ,
//ÆäËû
input [19 : 0] wr_addr_min ,//дÊý¾Ýddr×îСµØÖ·0µØÖ·¿ªÊ¼Ë㣬1920*1080*16 = 33177600 bits
input [19 : 0] wr_addr_max ,//дÊý¾Ýddr×î´óµØÖ·£¬Ò»¸öµØÖ·´æ32λ 33177600/32 = 1036800 = 20'b1111_1101_0010_0000_0000
output reg r_wr_rst ,
output reg r_rd_rst ,
output reg [1 : 0] w_fifo_state/* synthesis PAP_MARK_DEBUG="1" */,
output reg [1 : 0] r_fifo_state/* synthesis PAP_MARK_DEBUG="1" */,
output wire [19 : 0] wr_addr_cnt/* synthesis PAP_MARK_DEBUG="1" */
);
/************************************************************************/
/*******************************²ÎÊý***************************************/
parameter IDLE = 'd0,
WRITE_START = 'd1,
WRITE_ADDR = 'd2,
WRITE_DATA = 'd3,
READ_START = 'd1,
READ_ADDR = 'd2,
READ_DATA = 'd3;
/*******************************¼Ä´æÆ÷***************************************/
reg [CTRL_ADDR_WIDTH - 1 : 0] r_m_axi_awaddr;//µØÖ·¼Ä´æÆ÷
reg r_m_axi_awvalid;
reg r_m_axi_wlast;
reg r_m_axi_wvalid;
reg [CTRL_ADDR_WIDTH*8 - 1 : 0] r_m_axi_araddr;
reg r_m_axi_arvalid/* synthesis PAP_MARK_DEBUG="1" */;
reg [7 : 0] r_wburst_cnt;
reg [7 : 0] r_rburst_cnt;
reg [DQ_WIDTH*8 - 1 : 0] r_m_axi_rdata;
reg [19 : 0] r_wr_addr_cnt/* synthesis PAP_MARK_DEBUG="1" */;
reg [19 : 0] r_rd_addr_cnt/* synthesis PAP_MARK_DEBUG="1" */;
reg [1 : 0] r_wr_addr_page/* synthesis PAP_MARK_DEBUG="1" */;
reg [1 : 0] r_rd_addr_page/* synthesis PAP_MARK_DEBUG="1" */;
reg [1 : 0] r_wr_last_page/* synthesis PAP_MARK_DEBUG="1" */;
reg [1 : 0] r_rd_last_page/* synthesis PAP_MARK_DEBUG="1" */;
reg r_wr_done;//һ֡ͼÏñ´«ÊäÍê³ÉÐźÅ
reg r_rd_done;
reg r_wfifo_rd_req;
reg r_wfifo_pre_rd_req;
reg r_wfifo_pre_rd_flag;
reg r_rfifo_wr_req;
//¸´Î»ÐźÅ
reg r_vs_in_d0;
reg r_vs_in_d1;
reg r_vs_out_d0;
reg r_vs_out_d1;
//reg r_wr_rst/* synthesis PAP_MARK_DEBUG="1" */;
//reg r_rd_rst/* synthesis PAP_MARK_DEBUG="1" */;
/*******************************Íø±íÐÍ***************************************/
/*******************************×éºÏÂß¼***************************************/
//һЩ³£ÓýӿÚÊdz£Á¿£¬¸ù¾Ý¶¥²ãÄ£¿éÖ±½Ó¸³Öµ¾ÍºÃ
//дµØÖ·
assign M_AXI_AWADDR = {4'b0 , VIDEO_BASE_ADDR , r_wr_addr_page , r_wr_addr_cnt};//27-22¸ßλ0£¬21-20 Ö¡»º´æÒ³Êý£¬ 19-0 дµØÖ·¼ÆÊý
assign M_AXI_AWVALID = r_m_axi_awvalid;
//дÊý¾Ý
assign wfifo_rd_req = M_AXI_WLAST ? 1'b0 : M_AXI_WREADY;//r_wfifo_rd_req;
assign wfifo_pre_rd_req = r_wfifo_pre_rd_req;//µ±µØÖ·ÓÐЧºó½øÐÐÔ¤¶Á³öÒ»´ÎÊý¾Ý
//¶ÁµØÖ·
assign M_AXI_ARADDR = {4'b0 , VIDEO_BASE_ADDR , r_rd_addr_page , r_rd_addr_cnt};//27-22¸ßλ0£¬21-20 Ö¡»º´æÒ³Êý£¬ 19-0 ¶ÁµØÖ·¼ÆÊý
assign M_AXI_ARVALID = r_m_axi_arvalid;
assign rfifo_wr_req = M_AXI_RLAST ? 1'b0 : M_AXI_RVALID;//r_rfifo_wr_req;
assign wr_addr_cnt = r_wr_addr_cnt;
//¶ÁÊý¾Ý
//ÄÚ´æÇл»
/*******************************½ø³Ì***************************************/
//ץȡ֡ͬ²½ÉÏÉýÑØ£¬·½±ãºóÐø¸´Î»²Ù×÷
always @(posedge M_AXI_ACLK ) begin
if(!M_AXI_ARESETN ) begin
r_vs_in_d0 <= 'd0;
r_vs_in_d1 <= 'd0;
r_vs_out_d0 <= 'd0;
r_vs_out_d1 <= 'd0;
end
else begin
r_vs_in_d0 <= vs_in;
r_vs_in_d1 <= r_vs_in_d0;
r_vs_out_d0 <= vs_out;
r_vs_out_d1 <= r_vs_out_d0;
end
end
//Âö³å¸´Î»
always @(posedge M_AXI_ACLK ) begin
if(!M_AXI_ARESETN ) begin
r_wr_rst <= 'd0;
end
else if(r_vs_in_d0 && (!r_vs_in_d1)) begin//ץȡÉÏÉýÑØ£¬d0Ϊ¸ß£¬d1Ϊ1ʱÀ¸ß¸´Î»
r_wr_rst <= 'd1;
end
else if(r_wr_addr_cnt == wr_addr_min) begin //µ±µØַλ¹éÁãʱ½áÊø¸´Î»
r_wr_rst <= 'd0;
end
else begin
r_wr_rst <= r_wr_rst;
end
end
always @(posedge M_AXI_ACLK ) begin
if(!M_AXI_ARESETN ) begin
r_rd_rst <= 'd0;
end
else if(r_vs_out_d0 && (!r_vs_out_d1)) begin//ץȡÉÏÉýÑØ£¬d0Ϊ¸ß£¬d1Ϊ1ʱÀ¸ß¸´Î»
r_rd_rst <= 'd1;
end
else if(r_rd_addr_cnt == wr_addr_min) begin //µ±µØַλ¹éÁãʱ½áÊø¸´Î»
r_rd_rst <= 'd0;
end
else begin
r_rd_rst <= r_rd_rst;
end
end
//µØÖ·Ò³¸Ä±ä
always @(posedge M_AXI_ACLK ) begin
if(!M_AXI_ARESETN ) begin//¸´Î»ºóΪ0ʱ
r_wr_addr_page <= 2'b0;
r_wr_last_page <= 2'b0;
end
else if(r_wr_done) begin
r_wr_last_page <= r_wr_addr_page ;
r_wr_addr_page <= r_wr_addr_page + 1; //×îºóÒ»´ÎÍ»·¢´«ÊäÍê³É£¬Ò»Ö¡Í¼Ïñ´«ÊäÍê³É
if(r_wr_addr_page == r_rd_addr_page) begin
r_wr_addr_page <= r_wr_addr_page + 1;
end
end
end
always @(posedge M_AXI_ACLK ) begin
if(!M_AXI_ARESETN ) begin//¸´Î»ºóΪ0ʱ
r_rd_addr_page <= 2'b0;
r_rd_last_page <= 2'b0;
end
else if(r_rd_done) begin//Ö¡»º´æ¶ÁÍêºó£¬¶ÔµØÖ·Ò³½øÐÐÇл»£¬¶ÔÉÏÒ»´ÎдµÄÖ¡»º´æ½øÐжÁ£¬Èç¹ûµ±Ç°Ð´ÈëµÄÖ¡»º´æºÍÉÏÒ»´ÎµÄÖ¡»º´æδ±ä£¨Ö¡»º´æûÓÐдÍ꣩£¬ÔòÖظ´¶ÁÉÏÒ»´ÎµÄ¶ÁÖ¡»º´æ
r_rd_last_page <= r_rd_addr_page;
r_rd_addr_page <= r_wr_last_page;
if(r_rd_addr_page == r_wr_addr_page) begin
r_rd_addr_page <= r_rd_last_page ;
end
end
end
//Ò»¸öalways¿é×îºÃ¿ØÖÆÒ»¸öreg
//дµØַͨµÀ
always @(posedge M_AXI_ACLK ) begin
if(!M_AXI_ARESETN ) begin//ÓÐЧÐźźÍ×¼±¸ÐźŶ¼Îª1ʱ£¬ÓÐЧÐźŹé0
r_m_axi_awvalid <= 1'b0;
r_wr_addr_cnt <= 20'b0;
r_wr_done <= 1'b0;
r_fram_done <= 1'b0;
end
else if (r_wr_rst) begin
r_wr_addr_cnt <= wr_addr_min;
r_m_axi_awvalid <= 1'b0;
end
else if (DDR_INIT_DONE) begin
if(r_wr_addr_cnt < wr_addr_max - M_AXI_BRUST_LEN * 8 ) begin //дÈëµÄµØַСÓÚ×î´óµØÖ·¼õÈ¥Ò»´ÎÍ»·¢´«ÊäµÄ×ÜÁ¿£¨len*axi_data_width(256)/32£©
r_wr_done<= 1'b0;
if(M_AXI_AWVALID && M_AXI_AWREADY) begin
r_m_axi_awvalid <= 1'b0;
r_wr_addr_cnt <= r_wr_addr_cnt + M_AXI_BRUST_LEN * 8;
end
else if(w_fifo_state == WRITE_ADDR) begin
r_m_axi_awvalid <= 1'b1;
end
end
else if(r_wr_addr_cnt >= wr_addr_max - M_AXI_BRUST_LEN * 8 ) begin//×îºóÒ»´ÎÍ»·¢´«Êäʱ£¬µØÖ·¼ÆÊý¹éÁã
if(M_AXI_AWVALID && M_AXI_AWREADY) begin
r_m_axi_awvalid <= 1'b0;
r_wr_addr_cnt <= wr_addr_min;
r_wr_done<= 1'b1;
r_fram_done <= 1'b1;
end
else if(w_fifo_state == WRITE_ADDR) begin
r_m_axi_awvalid <= 1'b1;
end
end
end
else begin
r_m_axi_awvalid <= r_m_axi_awvalid;//ÆäËû״̬±£³Ö²»¶¯
r_wr_done <= r_wr_done;
r_wr_addr_cnt <= 20'b0;
end
end
//дÊý¾ÝͨµÀ
always @(posedge M_AXI_ACLK )begin//дͻ·¢¼ÆÊý
if(!M_AXI_ARESETN || M_AXI_WLAST)begin
r_wburst_cnt <= 'd0;
r_wfifo_rd_req <= 1'b0;
end
else if (M_AXI_WREADY) begin
r_wburst_cnt <= r_wburst_cnt + 1 ;
r_wfifo_rd_req <= 1'b1;
if (r_wburst_cnt == M_AXI_BRUST_LEN - 1'b1) begin//µ±¼ÆÊýµ½7ʱ£¬²»ÔÙʹÄܶÁ³öwfifo
r_wfifo_rd_req <= 1'b0;
end
end
else begin
r_wburst_cnt <= r_wburst_cnt;
r_wfifo_rd_req <= 'd0;
end
end
//Ô¤¶ÁWFIFO£¬Çå³ýfifoÊä³ö½Ó¿ÚÉÏÒ»´ÎÊý¾Ý
always @(posedge M_AXI_ACLK )begin//дͻ·¢¼ÆÊý
if(!M_AXI_ARESETN ||(!(r_vs_in_d0) && r_vs_in_d1))begin//ÿ´ÎVSϽµÑضÔÆ临λ
r_wfifo_pre_rd_req <= 'd0;
r_wfifo_pre_rd_flag <= 'd0;
end
else if(M_AXI_AWVALID && M_AXI_AWREADY && (r_wfifo_pre_rd_flag == 'd0)) begin
r_wfifo_pre_rd_req <= 'd1;
r_wfifo_pre_rd_flag <= 'd1;
end
else begin
r_wfifo_pre_rd_req <= 'd0;
end
end
//¶ÁµØÖ·
always @(posedge M_AXI_ACLK ) begin//¶ÁµØÖ·ÓÐЧ
if(!M_AXI_ARESETN)begin
r_m_axi_arvalid <= 'd0;//¸´Î»¡¢À¸ßºó¹éÁã
r_rd_addr_cnt <= 20'b0;
r_rd_done <= 'd0;
end
else if(r_rd_rst)begin
r_rd_addr_cnt <= wr_addr_min;
r_m_axi_arvalid <= 'd0;
end
else if (DDR_INIT_DONE) begin//DDR³õʼ»¯½áÊøÇÒÓÐһ֡ͼÏñÒѾ´æ´¢ºÃºó,
if(r_rd_addr_cnt < wr_addr_max - M_AXI_BRUST_LEN * 8) begin
r_rd_done <= 'd0;
if(M_AXI_ARVALID && M_AXI_ARREADY) begin//´Ó»úÏàÓ¦ºóÀµÍ£¬Ð´µØÖ·ÓÐЧÀµÍ£¬Í¬Ê±µØÖ·×ÔÔö
r_m_axi_arvalid <= 1'b0;
r_rd_addr_cnt <= r_rd_addr_cnt + M_AXI_BRUST_LEN * 8;
end
else if(r_fifo_state == READ_ADDR) begin
r_m_axi_arvalid <= 1'b1;
end
end
else if(r_rd_addr_cnt == wr_addr_max - M_AXI_BRUST_LEN * 8) begin
if(M_AXI_ARVALID && M_AXI_ARREADY) begin//×îºó´«ÊäÍê³Éºó¹éÁã
r_m_axi_arvalid <= 1'b0;
r_rd_addr_cnt <= wr_addr_min;
r_rd_done <= 'd1;
end
else if(r_fifo_state == READ_ADDR) begin
r_m_axi_arvalid <= 1'b1;
end
end
end
else begin
r_m_axi_arvalid <= r_m_axi_arvalid;
r_rd_addr_cnt <= r_rd_addr_cnt;
end
end
//¶ÁÊý¾Ý
always @(posedge M_AXI_ACLK )begin//ÊÕµ½validºóʹÄÜfifo´«ÊäÊý¾Ý
if(!M_AXI_ARESETN || M_AXI_RLAST)begin
r_rfifo_wr_req <= 'd0;
r_rburst_cnt <= 'd0;
end
else if (M_AXI_RVALID) begin
r_rfifo_wr_req <= 1'b1;
r_rburst_cnt <= r_rburst_cnt + 1'b1;
if (r_rburst_cnt == M_AXI_BRUST_LEN - 1'b1) begin//µ±¼ÆÊýµ½7ʱ£¬²»ÔÙʹÄܶÁ³öwfifo
r_rfifo_wr_req <= 1'b0;
end
end
else begin
r_rfifo_wr_req <= 'd0;
r_rburst_cnt <= r_rburst_cnt;
end
end
/*******************************״̬»ú***************************************/
//ΪÁËʵÏÖË«Ïòͬʱ´«Ê以²»Ó°Ï죬ËùÒÔ¶Áд״̬µ¥¶À×ö״̬»úʹÓÃ
//DDR3д״̬»ú
always @(posedge M_AXI_ACLK ) begin
if(~M_AXI_ARESETN || r_wr_rst)
w_fifo_state <= IDLE;
else begin
case(w_fifo_state)
IDLE:
begin
if(DDR_INIT_DONE)
w_fifo_state <= WRITE_START ;
else
w_fifo_state <= IDLE;
end
WRITE_START:
begin
// if (r_wr_rst) begin
// w_fifo_state <= WRITE_START;
// end
if(wfifo_rd_water_level > M_AXI_BRUST_LEN) begin//µ±wfifoÖжÁˮλ¸ßÓÚÍ»·¢³¤¶È£¨4£©ÊÇ£¬¿ªÊ¼Í»·¢´«Êä
w_fifo_state <= WRITE_ADDR; //Ìøµ½Ð´²Ù×÷
end
else if((r_wr_addr_cnt >= wr_addr_max - M_AXI_BRUST_LEN * 8) && (wfifo_rd_water_level >= M_AXI_BRUST_LEN - 1'b1)) begin//ÓÉÓÚ֮ǰԤ¶ÁÁËÒ»´Î£¬ËùÒÔÕâÀïÐèÒª-1
w_fifo_state <= WRITE_ADDR;
end
else begin
w_fifo_state <= w_fifo_state;
end
end
WRITE_ADDR:
begin
if(M_AXI_AWVALID && M_AXI_AWREADY)
w_fifo_state <= WRITE_DATA; //Ìøµ½Ð´Êý¾Ý²Ù×÷
else
w_fifo_state <= w_fifo_state; //Ìõ¼þ²»Âú×㣬±£³Öµ±Ç°Öµ
end
WRITE_DATA:
begin
//дµ½É趨µÄ³¤¶ÈÌøµ½µÈ´ý״̬
if(M_AXI_WLAST)//M_AXI_WREADY && (r_wburst_cnt == M_AXI_BRUST_LEN - 1)
w_fifo_state <= WRITE_START; //дµ½É趨µÄ³¤¶ÈÌøµ½µÈ´ý״̬
else
w_fifo_state <= w_fifo_state; //дÌõ¼þ²»Âú×㣬±£³Öµ±Ç°Öµ
end
default:
begin
w_fifo_state <= IDLE;
end
endcase
end
end
//DDR¶Á״̬»ú
always @(posedge M_AXI_ACLK ) begin
if(~M_AXI_ARESETN || r_rd_rst)
r_fifo_state <= IDLE;
else begin
case(r_fifo_state)
IDLE:
begin
if(DDR_INIT_DONE && r_fram_done) begin
r_fifo_state <= READ_START ;
end
else begin
r_fifo_state <= IDLE;
end
end
READ_START:
begin
// if(r_rd_rst) begin
// r_fifo_state <= READ_START;
// end
if(rfifo_wr_water_level < VIDEO_LENGTH*PIXEL_WIDTH/128)//µ±wfifoÖжÁˮλСÓÚ240£¬¿ªÊ¼Í»·¢´«Ê䣬1920*32*2/256 = 240£¨120¸öÍ»·¢´«ÊäÊý¾Ý£©240/8 = 30´ÎÍ»·¢´«Êä
r_fifo_state <= READ_ADDR; //Ìøµ½Ð´²Ù×÷
else
r_fifo_state <= r_fifo_state;
end
READ_ADDR:
begin
if(M_AXI_ARVALID && M_AXI_ARREADY)
r_fifo_state <= READ_DATA; //Ìøµ½Ð´Êý¾Ý²Ù×÷
else
r_fifo_state <= r_fifo_state; //Ìõ¼þ²»Âú×㣬±£³Öµ±Ç°Öµ
end
READ_DATA:
begin
//дµ½É趨µÄ³¤¶ÈÌøµ½µÈ´ý״̬
if(M_AXI_RLAST ) //&& (r_rburst_cnt == M_AXI_BRUST_LEN - 1)
r_fifo_state <= READ_START; //дµ½É趨µÄ³¤¶ÈÌøµ½µÈ´ý״̬
else
r_fifo_state <= r_fifo_state; //дÌõ¼þ²»Âú×㣬±£³Öµ±Ç°Öµ
end
default:
begin
r_fifo_state <= IDLE;
end
endcase
end
end
endmodule |
module video_enhance(
input wire pix_clk,
input wire vs_in,
input wire hs_in,
input wire de_in,
input wire [7 : 0] r_in,
input wire [7 : 0] g_in,
input wire [7 : 0] b_in,
output wire vs_out,
output wire hs_out,
output wire de_out,
output wire [7 : 0] r_out,
output wire [7 : 0] g_out,
output wire [7 : 0] b_out,
input wire [7 : 0] video_enhance_lightdown_num,
input wire video_enhance_lightdown_sw ,
input wire [7 : 0] video_enhance_darkup_num ,
input wire video_enhance_darkup_sw
);
wire [7 : 0] y_out;
wire [7 : 0] u_out;
wire [7 : 0] v_out;
//wire [7 : 0] r_out;
//wire [7 : 0] g_out;
//wire [7 : 0] b_out;
wire yuv_vs_out;
wire yuv_hs_out;
wire yuv_de_out;
rgb2yuv video_enhance_rgb2yuv(
.clk (pix_clk),//input
.r_in (r_in),//input [7:0]
.g_in (g_in),//input [7:0]
.b_in (b_in),//input [7:0]
.vs_in (vs_in),//input
.hs_in (hs_in),//input
.de_in (de_in),//input
.y_out (y_out),//output [7:0]
.u_out (u_out),//output [7:0]
.v_out (v_out),//output [7:0]
.vs_out(yuv_vs_out),//output
.hs_out(yuv_hs_out),//output
.de_out(yuv_de_out), //output
.video_enhance_lightdown_num(video_enhance_lightdown_num),// input wire [7 : 0]
.video_enhance_lightdown_sw (video_enhance_lightdown_sw ),// input wire
.video_enhance_darkup_num (video_enhance_darkup_num ),// input wire [7 : 0]
.video_enhance_darkup_sw (video_enhance_darkup_sw ) // input wire
);
yuv2rgb video_enhance_yuv2rgb(
.clk (pix_clk),//input
.y_in (y_out),//input [7:0]
.u_in (u_out),//input [7:0]
.v_in (v_out),//input [7:0]
.vs_in (yuv_vs_out),//input
.hs_in (yuv_hs_out),//input
.de_in (yuv_de_out),//input
.r_out (r_out),//output [7:0]
.g_out (g_out),//output [7:0]
.b_out (b_out),//output [7:0]
.vs_out(vs_out),//output
.hs_out(hs_out),//output
.de_out(de_out) //output
);
endmodule |
module ms7210_ctrl(
input clk,
input rstn,
output reg init_over,
output [7:0] device_id,
output reg iic_trig ,
output reg w_r ,
output reg [15:0] addr ,
output reg [ 7:0] data_in ,
input busy ,
input [ 7:0] data_out ,
input byte_over
);
assign device_id = 8'hB2;
function [23:0] cmd_data;
input [5:0] index;
begin
case(index)
6'd0 : cmd_data = {16'h1281,8'h04};
6'd1 : cmd_data = {16'h0016,8'h04};//
6'd2 : cmd_data = {16'h0009,8'h01};//
6'd3 : cmd_data = {16'h0007,8'h09};//
6'd4 : cmd_data = {16'h0008,8'hF0};//
6'd5 : cmd_data = {16'h000A,8'hF0};//
6'd6 : cmd_data = {16'h0006,8'h11};//
6'd7 : cmd_data = {16'h0531,8'h84};//
6'd8 : cmd_data = {16'h0900,8'h20};//
6'd9 : cmd_data = {16'h0901,8'h47};//
6'd10 : cmd_data = {16'h0904,8'h09};
6'd11 : cmd_data = {16'h0923,8'h07};//
6'd12 : cmd_data = {16'h0924,8'h44};//
6'd13 : cmd_data = {16'h0925,8'h44};//
6'd14 : cmd_data = {16'h090F,8'h80};//
6'd15 : cmd_data = {16'h091F,8'h07};//
6'd16 : cmd_data = {16'h0920,8'h1E};// INT EN
6'd17 : cmd_data = {16'h0018,8'h20};//
6'd18 : cmd_data = {16'h05c0,8'hFE};//
6'd19 : cmd_data = {16'h000B,8'h00};// seting
6'd20 : cmd_data = {16'h0507,8'h06};
6'd21 : cmd_data = {16'h0906,8'h04};//
6'd22 : cmd_data = {16'h0920,8'h5E};//
6'd23 : cmd_data = {16'h0926,8'hDD};//
6'd24 : cmd_data = {16'h0927,8'h0D};//
6'd25 : cmd_data = {16'h0928,8'h88};//
6'd26 : cmd_data = {16'h0929,8'h08};//
6'd27 : cmd_data = {16'h0910,8'h01};//
6'd28 : cmd_data = {16'h000B,8'h11};//
6'd29 : cmd_data = {16'h050E,8'h00};//
6'd30 : cmd_data = {16'h050A,8'h82};
6'd31 : cmd_data = {16'h0509,8'h02};//
6'd32 : cmd_data = {16'h050B,8'h0D};//
6'd33 : cmd_data = {16'h050D,8'h06};//
6'd34 : cmd_data = {16'h050D,8'h11};//
6'd35 : cmd_data = {16'h050D,8'h58};//
6'd36 : cmd_data = {16'h050D,8'h00};//
6'd37 : cmd_data = {16'h050D,8'h00};//
6'd38 : cmd_data = {16'h050D,8'h00};//
6'd39 : cmd_data = {16'h050D,8'h00};//
6'd40 : cmd_data = {16'h050D,8'h00};
6'd41 : cmd_data = {16'h050D,8'h00};//
6'd42 : cmd_data = {16'h050D,8'h00};//
6'd43 : cmd_data = {16'h050D,8'h00};//
6'd44 : cmd_data = {16'h050D,8'h00};//
6'd45 : cmd_data = {16'h050D,8'h00};//
6'd46 : cmd_data = {16'h050D,8'h00};//
6'd47 : cmd_data = {16'h050E,8'h40};//
6'd48 : cmd_data = {16'h0507,8'h00};//
endcase
end
endfunction
//===========================================================================
// MS7210 driver control FSM
//===========================================================================
parameter IDLE = 6'b00_0001;
parameter CONECT = 6'b00_0010;
parameter INIT = 6'b00_0100;
parameter WAIT = 6'b00_1000;
parameter SETING = 6'b01_0000;
parameter STA_RD = 6'b10_0000;
reg [ 5:0] state;
reg [ 5:0] state_n;
reg [ 4:0] dri_cnt;
reg [21:0] delay_cnt;
reg [ 5:0] cmd_index;
reg busy_1d;
wire busy_falling;
assign busy_falling = ((~busy) & busy_1d);
always @(posedge clk)
begin
busy_1d <= busy;
end
//===========================================================================
// MS7210 driver control FSM First Step
always @(posedge clk)
begin
if(!rstn)
state <= IDLE;
else
state <= state_n;
end
//===========================================================================
// MS7210 driver control FSM Second Step
always @(*)
begin
state_n = state;
case(state)
IDLE : begin
state_n = CONECT;
end
CONECT : begin
if(dri_cnt == 5'd1 && busy_falling && data_out == 8'h5A)
state_n = INIT;
else
state_n = state;
end
INIT : begin
if(dri_cnt == 5'd18 && busy_falling)
state_n = WAIT;
else
state_n = state;
end
WAIT : begin
if(delay_cnt == 22'h30D399)//)//
state_n = SETING;
else
state_n = state;
end
SETING : begin
if(dri_cnt == 5'd29 && busy_falling)
state_n = STA_RD;
else
state_n = state;
end
STA_RD : begin
state_n = state;
end
default : begin
state_n = IDLE;
end
endcase
end
//===========================================================================
// MS7210 driver control FSM Third Step
always @(posedge clk)
begin
if(!rstn)
dri_cnt <= 5'd0;
else
begin
case(state)
IDLE ,
WAIT ,
STA_RD : dri_cnt <= 5'd0;
CONECT : begin
if(busy_falling)
begin
if(dri_cnt == 5'd1)
dri_cnt <= 5'd0;
else
dri_cnt <= dri_cnt + 5'd1;
end
else
dri_cnt <= dri_cnt;
end
INIT : begin
if(busy_falling)
begin
if(dri_cnt == 5'd18)
dri_cnt <= 5'd0;
else
dri_cnt <= dri_cnt + 5'd1;
end
else
dri_cnt <= dri_cnt;
end
SETING : begin
if(busy_falling)
begin
if(dri_cnt == 5'd29)
dri_cnt <= 5'd0;
else
dri_cnt <= dri_cnt + 5'd1;
end
else
dri_cnt <= dri_cnt;
end
default : dri_cnt <= 5'd0;
endcase
end
end
always @(posedge clk)
begin
if(state == WAIT)
begin
if(delay_cnt == 22'h30D399)
delay_cnt <= 22'd0;
else
delay_cnt <= delay_cnt + 22'd1;
end
else
delay_cnt <= 22'd0;
end
always @(posedge clk)
begin
if(!rstn)
iic_trig <= 1'd0;
else
begin
case(state)
IDLE : iic_trig <= 1'b1;
WAIT : iic_trig <= (delay_cnt == 22'h30D399);
CONECT ,
INIT ,
SETING ,
STA_RD : iic_trig <= busy_falling;
default : iic_trig <= 1'd0;
endcase
end
end
always @(posedge clk)
begin
if(!rstn)
w_r <= 1'd1;
else
begin
case(state)
IDLE : w_r <= 1'b1;
CONECT : begin
if(dri_cnt == 5'd0 && busy_falling)
w_r <= 1'b0;
else if(dri_cnt == 5'd1 && busy_falling)
w_r <= 1'b1;
else
w_r <= w_r;
end
INIT ,
STA_RD ,
WAIT : w_r <= w_r;
SETING : begin
if(dri_cnt == 5'd29 && busy_falling)
w_r <= 1'b0;
else
w_r <= w_r;
end
default : w_r <= 1'b1;
endcase
end
end
always @(posedge clk)
begin
if(!rstn)
cmd_index <= 6'd0;
else
begin
case(state)
IDLE : cmd_index <= 6'd0;
CONECT : cmd_index <= 6'd0;
INIT ,
SETING :begin
if(byte_over)
cmd_index <= cmd_index + 1'b1;
else
cmd_index <= cmd_index;
end
WAIT ,
STA_RD : cmd_index <= cmd_index;
default : cmd_index <= 6'd0;
endcase
end
end
reg [23:0] cmd_iic;
always@(posedge clk)
begin
if(~rstn)
cmd_iic <= 0;
else if(state == IDLE)
cmd_iic <= 24'd0;
else //if(state == WAIT || state == SETING)
cmd_iic <= cmd_data(cmd_index);
end
always @(posedge clk)
begin
if(!rstn)
begin
addr <= 16'd0;
data_in <= 8'd0;
end
else
begin
case(state)
IDLE : begin
addr <= 16'h0003;
data_in <= 8'h5A;
end
CONECT : begin
if(dri_cnt == 5'd1 && busy_falling && data_out == 8'h5A)
begin
addr <= cmd_iic[23:8];
data_in <= cmd_iic[ 7:0];
end
else
begin
addr <= addr;
data_in <= data_in;
end
end
INIT ,
WAIT ,
SETING :begin
addr <= cmd_iic[23:8];
data_in <= cmd_iic[ 7:0];
end
STA_RD :begin
addr <= 16'h0502;
data_in <= 8'd0;
end
default : begin
addr <= 0;
data_in <= 0;
end
endcase
end
end
always @(posedge clk)
begin
if(!rstn)
init_over <= 1'b0;
else if(state == STA_RD)// && busy_falling)
init_over <= 1'b1;
end
endmodule |
module pcie_dma_ctrl(
input wire clk ,
input wire pix_clk_out ,
input wire rstn ,
input wire axis_master_tvalid /* synthesis PAP_MARK_DEBUG="1" */,
output wire axis_master_tready /* synthesis PAP_MARK_DEBUG="1" */,
input wire [127:0] axis_master_tdata /* synthesis PAP_MARK_DEBUG="1" */,
input wire [3:0] axis_master_tkeep /* synthesis PAP_MARK_DEBUG="1" */,
input wire axis_master_tlast /* synthesis PAP_MARK_DEBUG="1" */,
input wire [7:0] axis_master_tuser /* synthesis PAP_MARK_DEBUG="1" */,
input [7 : 0] ep_bus_num ,
input [4 : 0] ep_dev_num ,
input AXIS_S_TREADY /* synthesis PAP_MARK_DEBUG="1" */,
output AXIS_S_TVALID /* synthesis PAP_MARK_DEBUG="1" */,
output [127:0] AXIS_S_TDATA /* synthesis PAP_MARK_DEBUG="1" */,
output AXIS_S_TLAST /* synthesis PAP_MARK_DEBUG="1" */,
output AXIS_S_TUSER /* synthesis PAP_MARK_DEBUG="1" */,
//HDMI FIFO DATA IN
input [15: 0] hdmi_data_in /* synthesis PAP_MARK_DEBUG="1" */,
//input [8 : 0] rd_water_level /* synthesis PAP_MARK_DEBUG="1" */,
//output reg pcie_rd_en /* synthesis PAP_MARK_DEBUG="1" */,
//output reg fram_start /* synthesis PAP_MARK_DEBUG="1" */,
input vs_in ,
input de_in ,
//PCIe ctrl
output reg [7 : 0] video_enhance_lightdown_num /* synthesis PAP_MARK_DEBUG="1" */,
output reg video_enhance_lightdown_sw /* synthesis PAP_MARK_DEBUG="1" */,
output reg [7 : 0] video_enhance_darkup_num /* synthesis PAP_MARK_DEBUG="1" */,
output reg video_enhance_darkup_sw /* synthesis PAP_MARK_DEBUG="1" */
);
/*****************************wire******************************/
wire [12 : 0] rd_water_level /* synthesis PAP_MARK_DEBUG="1" */;
wire [127:0] pcie_dma_data /* synthesis PAP_MARK_DEBUG="1" */;
/*****************************reg******************************/
localparam MWR_32 = 8'h40;
localparam DMA_CMD_L_ADDR = 12'h110;
localparam DMA_CMD_CLEAR_ADDR = 12'h130;
localparam DMA_CMD_VIDEO_HIGHTLIGHT_SUB = 12'h140;
localparam DMA_CMD_VIDEO_LOWLIGHT_ADD = 12'h150;
localparam DMA_CMD_VIDEO_ENHANCE_CLEAR = 12'h160;
parameter ALLOC_ADDR_1 = 4'd1;
parameter ALLOC_ADDR_2 = 4'd2;
parameter ALLOC_ADDR_3 = 4'd3;
parameter ALLOC_ADDR_4 = 4'd4;
parameter MWR_IDLE = 2'd0;
parameter MWR_TLP_HEADER = 2'd1;
parameter MWR_TLP_DATA = 2'd2;
parameter TLP_LENGTH = 10'd16;
parameter DMA_TRAN_TIMES = 'd64801;// 8100´Î´«Êä 8100*64*4=1920*1080//64;//129600;
reg [1:0] mwr_state /* synthesis PAP_MARK_DEBUG="1" */;
reg r_axis_s_tvalid/* synthesis PAP_MARK_DEBUG="1" */;
reg [127:0] r_axis_s_tdata;
reg r_axis_s_tlast;
reg [10 :0] r_tlp_length_cnt/* synthesis PAP_MARK_DEBUG="1" */;
reg [127:0] axis_master_tdata_d0 /* synthesis PAP_MARK_DEBUG="1" */;
reg axis_master_tvalid_d0 /* synthesis PAP_MARK_DEBUG="1" */;
reg axis_master_tvalid_d1 /* synthesis PAP_MARK_DEBUG="1" */;
reg [2 : 0] tlp_fmt /* synthesis PAP_MARK_DEBUG="1" */;
reg [4 : 0] tlp_type /* synthesis PAP_MARK_DEBUG="1" */;
reg mwr32 /* synthesis PAP_MARK_DEBUG="1" */;
reg [31: 0] mwr_addr /* synthesis PAP_MARK_DEBUG="1" */;
reg [11: 0] cmd_reg_addr /* synthesis PAP_MARK_DEBUG="1" */;
reg [9 : 0] tlp_lenght /* synthesis PAP_MARK_DEBUG="1" */;
reg rc_cfg_ep_flag /* synthesis PAP_MARK_DEBUG="1" */;
reg [31: 0] alloc_addrl /* synthesis PAP_MARK_DEBUG="1" */;
//·ÖÅäµÄÖ¡»º´æµØÖ·
reg [3 : 0] alloc_addr_state /* synthesis PAP_MARK_DEBUG="1" */;
reg [1 : 0] addr_page /* synthesis PAP_MARK_DEBUG="1" */;
reg [31: 0] dma_addr0 /* synthesis PAP_MARK_DEBUG="1" */;
reg [31: 0] dma_addr1 /* synthesis PAP_MARK_DEBUG="1" */;
reg [31: 0] dma_addr2 /* synthesis PAP_MARK_DEBUG="1" */;
reg [31: 0] dma_addr3 /* synthesis PAP_MARK_DEBUG="1" */;
reg dma_addr_cfg_flag /* synthesis PAP_MARK_DEBUG="1" */;
reg dma_stop_flag /* synthesis PAP_MARK_DEBUG="1" */;
reg [1 : 0] rc_cfg_cnt /* synthesis PAP_MARK_DEBUG="1" */;
reg [15: 0] dma_cnt /* synthesis PAP_MARK_DEBUG="1" */;
reg rc_cfg_ep_flag_d0 /* synthesis PAP_MARK_DEBUG="1" */;
reg vs_in_d0 /* synthesis PAP_MARK_DEBUG="1" */;
reg vs_in_d1 /* synthesis PAP_MARK_DEBUG="1" */;
reg r_pre_rd_flag /* synthesis PAP_MARK_DEBUG="1" */;
reg fram_start /* synthesis PAP_MARK_DEBUG="1" */;
reg dma_start /* synthesis PAP_MARK_DEBUG="1" */;
reg pcie_rd_en /* synthesis PAP_MARK_DEBUG="1" */;
reg [7 : 0] fram_cnt /* synthesis PAP_MARK_DEBUG="1" */;
/*****************************assign******************************/
assign axis_master_tready = 'd1;
assign AXIS_S_TVALID = r_axis_s_tvalid;
assign AXIS_S_TDATA = r_axis_s_tdata ;
assign AXIS_S_TLAST = r_axis_s_tlast ;
assign AXIS_S_TUSER = 'd0;
/************************always**********************************/
//¶ÔÊäÈëÊý¾Ý¶à´òÒ»ÅÄ
always @(posedge clk) begin
if(!rstn) begin
axis_master_tdata_d0 <= 'd0;
axis_master_tvalid_d0 <= 'd0;
rc_cfg_ep_flag_d0 <= 'd0;
vs_in_d0 <= 'd0;
vs_in_d1 <= 'd0;
end
else begin
axis_master_tdata_d0 <= axis_master_tdata;
axis_master_tvalid_d0 <= axis_master_tvalid;
axis_master_tvalid_d1 <= axis_master_tvalid_d0;
rc_cfg_ep_flag_d0 <= rc_cfg_ep_flag;
vs_in_d0 <= vs_in;
vs_in_d1 <= vs_in_d0;
end
end
//¸ù¾ÝÊäÈëÊý¾Ý·ÖÎö¸ñʽ
always @(posedge clk) begin
if(!rstn) begin
tlp_fmt <= 'd0;
tlp_type <= 'd0;
mwr32 <= 'd0;
mwr_addr <= 'd0;
cmd_reg_addr <= 'd0;
tlp_lenght <= 'd0;
end
else if(axis_master_tvalid_d0 && !(axis_master_tvalid_d1))begin
tlp_fmt <= axis_master_tdata_d0[31:29];
tlp_type <= axis_master_tdata_d0[28:24];
mwr_addr <= axis_master_tdata_d0[95:64];
cmd_reg_addr <= axis_master_tdata_d0[75:64];//cmdÆ«ÒƵØÖ·
tlp_lenght <= axis_master_tdata_d0[9:0];//TLPÊý¾Ý°ü³¤¶È
end
else begin
tlp_fmt <= 'd0;
tlp_type <= 'd0;
mwr_addr <= 'd0;
cmd_reg_addr <= 'd0;
tlp_lenght <= 'd0;
end
end
always @(posedge clk) begin//¶ÔRCÅäÖÃEPµÄMWRÐźŽøÐмÆÊý
if(!rstn || dma_stop_flag) begin
alloc_addr_state <= ALLOC_ADDR_1;
dma_addr0 <= 'd0;
dma_addr1 <= 'd0;
dma_addr2 <= 'd0;
dma_addr3 <= 'd0;
dma_stop_flag <= 'd0;
video_enhance_lightdown_num <= 'd0;
video_enhance_lightdown_sw <= 'd0;
video_enhance_darkup_num <= 'd0;
video_enhance_darkup_sw <= 'd0;
end
else if(({tlp_fmt,tlp_type} == MWR_32 )&& (tlp_lenght == 1) && (cmd_reg_addr == DMA_CMD_L_ADDR)) begin
case(alloc_addr_state)//Ñ»·²¶»ñµØÖ·
ALLOC_ADDR_1:
begin
dma_addr0 <= {axis_master_tdata_d0[7:0],axis_master_tdata_d0[15:8],axis_master_tdata_d0[23:16],axis_master_tdata_d0[31:24]};
alloc_addr_state <= ALLOC_ADDR_2;
end
ALLOC_ADDR_2:
begin
dma_addr1 <= {axis_master_tdata_d0[7:0],axis_master_tdata_d0[15:8],axis_master_tdata_d0[23:16],axis_master_tdata_d0[31:24]};
alloc_addr_state <= ALLOC_ADDR_3;
end
ALLOC_ADDR_3:
begin
dma_addr2 <= {axis_master_tdata_d0[7:0],axis_master_tdata_d0[15:8],axis_master_tdata_d0[23:16],axis_master_tdata_d0[31:24]};
alloc_addr_state <= ALLOC_ADDR_4;
end
ALLOC_ADDR_4:
begin
dma_addr3 <= {axis_master_tdata_d0[7:0],axis_master_tdata_d0[15:8],axis_master_tdata_d0[23:16],axis_master_tdata_d0[31:24]};
alloc_addr_state <= ALLOC_ADDR_1;
end
endcase
end
else if(({tlp_fmt,tlp_type} == MWR_32 )&& (tlp_lenght == 1) && (cmd_reg_addr == DMA_CMD_CLEAR_ADDR)) begin//½ÓÊÕµ½Çå¿ÕDMAµØÖ·ÃüÁî
dma_stop_flag <= 1'b1;
end
else if(({tlp_fmt,tlp_type} == MWR_32 )&& (tlp_lenght == 1) && (cmd_reg_addr == DMA_CMD_VIDEO_LOWLIGHT_ADD)) begin//°µ¹âÔöÇ¿ÃüÁî
video_enhance_darkup_num <= axis_master_tdata_d0[31:24];
video_enhance_darkup_sw <= 1'b1;
end
else if(({tlp_fmt,tlp_type} == MWR_32 )&& (tlp_lenght == 1) && (cmd_reg_addr == DMA_CMD_VIDEO_HIGHTLIGHT_SUB)) begin//¸ß¹âѹÖÆÃüÁî
video_enhance_lightdown_num <= axis_master_tdata_d0[31:24];
video_enhance_lightdown_sw <= 1'b1;
end
else if(({tlp_fmt,tlp_type} == MWR_32 )&& (tlp_lenght == 1) && (cmd_reg_addr == DMA_CMD_VIDEO_ENHANCE_CLEAR)) begin//Í£Ö¹ÊÓƵÔöÇ¿
video_enhance_lightdown_sw <= 1'b0;
video_enhance_darkup_sw <= 1'b0;
video_enhance_lightdown_num <= 'd0;
video_enhance_darkup_num <= 'd0;
end
else begin
alloc_addr_state <= alloc_addr_state ;
dma_addr0 <= dma_addr0 ;
dma_addr1 <= dma_addr1 ;
dma_addr2 <= dma_addr2 ;
dma_addr3 <= dma_addr3 ;
dma_addr_cfg_flag <= dma_addr_cfg_flag;
video_enhance_lightdown_num <= video_enhance_lightdown_num;
video_enhance_lightdown_sw <= video_enhance_lightdown_sw ;
video_enhance_darkup_num <= video_enhance_darkup_num ;
video_enhance_darkup_sw <= video_enhance_darkup_sw ;
end
end
always @(posedge clk) begin//ÓÃÓÚÅжϸ÷ÖÖ±ê־λ
if(!rstn || dma_stop_flag) begin
rc_cfg_ep_flag <= 'd0;
dma_cnt <= 'd0;
fram_start <= 'd0;
dma_start <= 'd0;
end
else begin
if((dma_addr0 != 32'b0) && (dma_addr1 != 32'b0) && (dma_addr2 != 32'b0) && (dma_addr3 != 32'b0)) begin//ÊÕµ½RCµÄÁ½¸öMWR_32ºó£¬rc_cfg_ep_flagÀ¸ß£¬¿ªÊ¼µÈ´ýÊÓƵ֡ͷµ½À´
rc_cfg_ep_flag <= 'd1;
end
if(!vs_in_d0 && vs_in_d1 && rc_cfg_ep_flag) begin//µ±rc_cfg_ep_flagÀ¸ß£¬Í¬Ê±×¥È¡VSϽµÑØ£¬Ï½µÑØÀ´µ½Ê±±íʾһ֡¿ªÊ¼£¬À¸ßfram_start
fram_start <= 'd1;
dma_start <= 'd0;
end
if(fram_start && (vs_in_d0 && !vs_in_d1)) begin//fram_startÀ¸ßºó£¬×¥È¡ÉÏÉýÑØ£¬ÉÏÉýÑص½À´Ê±±íʾһ֡½áÊø£¬fram_startÀµÍ
fram_start <= 'd0;
//rc_cfg_ep_flag <= 'd0;
end
if(AXIS_S_TLAST) begin//Ò»´ÎDMA½áÊøºó£¬Ïà¹Ø±ê־λÀµÍ
dma_start <= 'd0;
if(dma_cnt >= DMA_TRAN_TIMES - 1) begin
dma_cnt <= 'd0;
end
else begin
dma_cnt <= dma_cnt +'d1;
end
end
else if( ((dma_cnt == 0)&&(rd_water_level >= TLP_LENGTH/4 + 1))|| ((dma_cnt != 0)&&(rd_water_level >= TLP_LENGTH/4)) || ((rd_water_level >= TLP_LENGTH/4 - 1) &&( dma_cnt == DMA_TRAN_TIMES - 2)) || dma_cnt == DMA_TRAN_TIMES-1) begin//ˮλ¸ßÓÚ4£¨16dw£©£¬À¸ßdma_start±ê־λ
dma_start <= 'd1;
end
end
end
//¿ØÖÆAXIS·¢ËÍTLP°ü
always @(posedge clk) begin
if(!rstn || dma_stop_flag) begin
r_axis_s_tvalid <= 'd0;
r_axis_s_tdata <= 'd0;
r_axis_s_tlast <= 'd0;
r_tlp_length_cnt <= 'd0;
r_pre_rd_flag <= 'd0;
pcie_rd_en <= 'd0;
alloc_addrl <= 'd0;
addr_page <= 'd0;
fram_cnt <= 'd1;
end
else if (vs_in_d0 && !vs_in_d1) begin//vsÉÏÉýÑظ´Î»
r_axis_s_tvalid <= 'd0;
r_axis_s_tdata <= 'd0;
r_axis_s_tlast <= 'd0;
r_tlp_length_cnt <= 'd0;
r_pre_rd_flag <= 'd0;
pcie_rd_en <= 'd0;
addr_page <= addr_page + 'd1;
//Åжϵ±Ç°µØÖ·Ò³
if(addr_page == 0) begin
alloc_addrl <= dma_addr0;
end
else if(addr_page == 1) begin
alloc_addrl <= dma_addr1;
end
else if(addr_page == 2) begin
alloc_addrl <= dma_addr2;
end
else if(addr_page == 3) begin
alloc_addrl <= dma_addr3;
end
end
else if (fram_start && dma_start && rc_cfg_ep_flag) begin //(rc_cfg_ep_flag) begin //
case(mwr_state)
MWR_IDLE:
begin
r_axis_s_tvalid <= 'd0;
r_axis_s_tdata <= 'd0;
r_axis_s_tlast <= 'd0;
if(r_pre_rd_flag == 0) begin
pcie_rd_en <= 'd1;
r_pre_rd_flag <= 'd1;
end
else begin
pcie_rd_en <= 'd0;
end
end
MWR_TLP_HEADER:
begin
//Mwr
r_axis_s_tvalid <= 'd1;
r_axis_s_tlast <= 'd0;
//Byte 0+
r_axis_s_tdata[9 : 0] <= TLP_LENGTH; //°ü³¤ 2
r_axis_s_tdata[11 : 10] <= 'h0; //AT
r_axis_s_tdata[13 : 12] <= 'h0; //Attr
r_axis_s_tdata[14] <= 'h0; //EP
r_axis_s_tdata[15] <= 'h0; //TD
r_axis_s_tdata[16] <= 'h0; //TH
r_axis_s_tdata[17] <= 'h0; //±£Áô
r_axis_s_tdata[18] <= 'h0; //Attr2
r_axis_s_tdata[19] <= 'h0; //±£Áô
r_axis_s_tdata[22 : 20] <= 'h0; //TC
r_axis_s_tdata[23] <= 'h0; //±£Áô
r_axis_s_tdata[28 : 24] <= 'h0; //Type
r_axis_s_tdata[31 : 29] <= 3'b010; //Fmt 3DW Mwr
//Byte 4+
r_axis_s_tdata[35 : 32] <= 4'hf; //First DW BE ÓÃÓÚ˵Ã÷Êý¾ÝµÚÒ»¸öDWÄÄÒ»¸ö×Ö½ÚÓÐЧ
r_axis_s_tdata[39 : 36] <= 4'hf; //Last DW BE ÓÃÓÚ˵Ã÷Êý¾Ý×îºóÒ»¸öDWÄÄÒ»¸ö×Ö½ÚÓÐЧ
r_axis_s_tdata[47 : 40] <= 8'h01; //Tag
r_axis_s_tdata[63 : 48] <= {ep_bus_num,ep_dev_num,3'b0}; //Requester ID [63:56] Bus Num [55:51] Device Num [50:48] Function Num
//Byte 8+
r_axis_s_tdata[95 : 64] <= alloc_addrl;//r_dma_addr; //64λµÄ¸ß32λµØÖ· or 32λµÄµÍ30λµØÖ·£¨µÍÁ½Î»±£Áô£¬±£Ö¤Êý¾ÝDW¶ÔÆ䣩
//Byte 12+_
r_axis_s_tdata[127: 96] <= 32'd0; //64λµÄµÍ30λµØÖ·£¨µÍÁ½Î»±£Áô£©
pcie_rd_en <= 'd1;//ÌáÇ°Ò»¸öÖÜÆÚ°ÑÊý¾ÝÕû³öÀ´
end
MWR_TLP_DATA:
begin
if(AXIS_S_TREADY) begin
if(dma_cnt <= DMA_TRAN_TIMES - 2) begin
//µØÖ·×ö±ä»»
r_axis_s_tdata <= {
pcie_dma_data[103: 96],pcie_dma_data[111:104],pcie_dma_data[119:112],pcie_dma_data[127:120],
pcie_dma_data[71 : 64],pcie_dma_data[79 : 72],pcie_dma_data[87 : 80],pcie_dma_data[95 : 88],
pcie_dma_data[39 : 32],pcie_dma_data[47 : 40],pcie_dma_data[55 : 48],pcie_dma_data[63 : 56],
pcie_dma_data[7 : 0],pcie_dma_data[15 : 8],pcie_dma_data[23 : 16],pcie_dma_data[31 : 24] };//Ç°60´Î´«Ê䣬´«ÊäÊý¾Ý
end
else if(dma_cnt >= DMA_TRAN_TIMES - 1) begin
r_axis_s_tdata <= {16{fram_cnt}};//128'hdddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd;//×îºó4´Î´«Ê䣬´«Êä±ê־λ
if(fram_cnt == 8'hff) begin
fram_cnt <= 'd1;
end
else begin
fram_cnt <= fram_cnt + 'd1;
end
pcie_rd_en <= 'd0;
end
r_tlp_length_cnt <= r_tlp_length_cnt + 1'd1;
if(AXIS_S_TLAST) begin
r_tlp_length_cnt <= 'd0;
r_axis_s_tvalid <= 'd0;
r_axis_s_tdata <= 'd0;
r_axis_s_tlast <= 'd0;
alloc_addrl <= alloc_addrl + TLP_LENGTH*4;//½áÊø´«ÊäºóµØÖ·×ÔÔö °ü³¤*4
end
else if(((TLP_LENGTH <= 4) || ((TLP_LENGTH > 4) && (r_tlp_length_cnt >= TLP_LENGTH/4 - 1)) && AXIS_S_TREADY)) begin
r_axis_s_tlast <= 'd1;
pcie_rd_en <= 'd0;
end
end
else begin
pcie_rd_en <= 'd0;
end
end
default:
begin
r_axis_s_tvalid <= 'd0;
r_axis_s_tdata <= 'd0;
r_axis_s_tlast <= 'd0;
pcie_rd_en <='d0 ;
end
endcase
end
end
/************************state_machine**********************************/
//¿ØÖÆAXIS·¢ËÍTLP°ü
always @(posedge clk) begin
if(!rstn || (vs_in_d0 && !vs_in_d1) || dma_stop_flag) begin
mwr_state <= 'd0;
end
else if(fram_start && dma_start && rc_cfg_ep_flag) begin // (rc_cfg_ep_flag) begin //
case(mwr_state)
MWR_IDLE:
begin
if(AXIS_S_TREADY) begin
mwr_state <= MWR_TLP_HEADER;
end
else begin
mwr_state <= mwr_state;
end
end
MWR_TLP_HEADER:
begin
if(AXIS_S_TREADY) begin//µ±ValidºÍReadyͬʱÀ¸ßʱ£¬½øÈëÏÂÒ»¸ö״̬
mwr_state <= MWR_TLP_DATA;
end
else begin
mwr_state <= mwr_state;
end
end
MWR_TLP_DATA:
begin
if(AXIS_S_TLAST) begin //À¸ßºó»Ø¹éIDLE
mwr_state <= MWR_IDLE;
end
else begin
mwr_state <= mwr_state;
end
end
default:
begin
mwr_state <= mwr_state;
end
endcase
end
else begin
mwr_state <= mwr_state;
end
end
hdmi_pcie_fifo u_hdmi_pcie_fifo (
.wr_clk (pix_clk_out ), // input
.wr_rst (vs_in || ~rstn || dma_stop_flag ), // input
.wr_en (de_in && fram_start ), // input
.wr_data (hdmi_data_in ), // input [15:0]
.wr_full ( ), // output
.wr_water_level ( ), // output [10:0]
.almost_full ( ), // output
.rd_clk (clk ), // input
.rd_rst (vs_in || ~rstn || dma_stop_flag ), // input
.rd_en (pcie_rd_en ), // input
.rd_data (pcie_dma_data ), // output [127:0]
.rd_empty ( ), // output
.rd_water_level (rd_water_level ), // output [10:0]
.almost_empty ( ) // output
);
endmodule |
module udp_top(
input rst_n , //¸´Î»Ðźţ¬µÍµçƽÓÐЧ
//GMII½Ó¿Ú
input gmii_rx_clk , //GMII½ÓÊÕÊý¾ÝʱÖÓ
input gmii_rx_dv , //GMIIÊäÈëÊý¾ÝÓÐЧÐźÅ
input [7:0] gmii_rxd , //GMIIÊäÈëÊý¾Ý
input gmii_tx_clk , //GMII·¢ËÍÊý¾ÝʱÖÓ
output gmii_tx_en , //GMIIÊä³öÊý¾ÝÓÐЧÐźÅ
output [7:0] gmii_txd , //GMIIÊä³öÊý¾Ý
//Óû§½Ó¿Ú
output rec_pkt_done, //ÒÔÌ«Íøµ¥°üÊý¾Ý½ÓÊÕÍê³ÉÐźÅ
output rec_en , //ÒÔÌ«Íø½ÓÊÕµÄÊý¾ÝʹÄÜÐźÅ
output [31:0] rec_data , //ÒÔÌ«Íø½ÓÊÕµÄÊý¾Ý
output [15:0] rec_byte_num, //ÒÔÌ«Íø½ÓÊÕµÄÓÐЧ×Ö½ÚÊý µ¥Î»:byte
input tx_start_en , //ÒÔÌ«Íø¿ªÊ¼·¢ËÍÐźÅ
input [31:0] tx_data , //ÒÔÌ«Íø´ý·¢ËÍÊý¾Ý
input [15:0] tx_byte_num , //ÒÔÌ«Íø·¢Ë͵ÄÓÐЧ×Ö½ÚÊý µ¥Î»:byte
input [47:0] des_mac , //·¢Ë͵ÄÄ¿±êMACµØÖ·
input [31:0] des_ip , //·¢Ë͵ÄÄ¿±êIPµØÖ·
output tx_done , //ÒÔÌ«Íø·¢ËÍÍê³ÉÐźÅ
output tx_req //¶ÁÊý¾ÝÇëÇóÐźÅ
);
//parameter define
//¿ª·¢°åMACµØÖ· 00-11-22-33-44-55
parameter BOARD_MAC = 48'h00_11_22_33_44_55;
//¿ª·¢°åIPµØÖ· 192.168.1.10
parameter BOARD_IP = {8'd192,8'd168,8'd1,8'd10};
//Ä¿µÄMACµØÖ· ff_ff_ff_ff_ff_ff
parameter DES_MAC = 48'hff_ff_ff_ff_ff_ff;
//Ä¿µÄIPµØÖ· 192.168.1.102
parameter DES_IP = {8'd192,8'd168,8'd1,8'd102};
//wire define
wire crc_en ; //CRC¿ªÊ¼Ð£ÑéʹÄÜ
wire crc_clr ; //CRCÊý¾Ý¸´Î»ÐźÅ
wire [7:0] crc_d8 ; //ÊäÈë´ýУÑé8λÊý¾Ý
wire [31:0] crc_data; //CRCУÑéÊý¾Ý
wire [31:0] crc_next; //CRCÏ´ÎУÑéÍê³ÉÊý¾Ý
//*****************************************************
//** main code
//*****************************************************
assign crc_d8 = gmii_txd;
//ÒÔÌ«Íø½ÓÊÕÄ£¿é
udp_rx
#(
.BOARD_MAC (BOARD_MAC), //²ÎÊýÀý»¯
.BOARD_IP (BOARD_IP )
)
u_udp_rx(
.clk (gmii_rx_clk ),
.rst_n (rst_n ),
.gmii_rx_dv (gmii_rx_dv ),
.gmii_rxd (gmii_rxd ),
.rec_pkt_done (rec_pkt_done),
.rec_en (rec_en ),
.rec_data (rec_data ),
.rec_byte_num (rec_byte_num)
);
//ÒÔÌ«Íø·¢ËÍÄ£¿é
udp_tx
#(
.BOARD_MAC (BOARD_MAC), //²ÎÊýÀý»¯
.BOARD_IP (BOARD_IP ),
.DES_MAC (DES_MAC ),
.DES_IP (DES_IP )
)
u_udp_tx(
.clk (gmii_tx_clk),
.rst_n (rst_n ),
.tx_start_en (tx_start_en),
.tx_data (tx_data ),
.tx_byte_num (tx_byte_num),
.des_mac (des_mac ),
.des_ip (des_ip ),
.crc_data (crc_data ),
.crc_next (crc_next[31:24]),
.tx_done (tx_done ),
.tx_req (tx_req ),
.gmii_tx_en (gmii_tx_en ),
.gmii_txd (gmii_txd ),
.crc_en (crc_en ),
.crc_clr (crc_clr )
);
//ÒÔÌ«Íø·¢ËÍCRCУÑéÄ£¿é
crc32_d8 u_crc32_d8(
.clk (gmii_tx_clk),
.rst_n (rst_n ),
.data (crc_d8 ),
.crc_en (crc_en ),
.crc_clr (crc_clr ),
.crc_data (crc_data ),
.crc_next (crc_next )
);
endmodule |
module gmii_to_rgmii(
input rst,
output rgmii_clk,
//macÊäÈëµÄÊý¾ÝÓÉgmiiת»¯Îªrgmii£¬Ê±ÖÓΪrgmii_clk
input mac_tx_data_valid,
input [7:0] mac_tx_data,
//ethÊäÈëµÄÊý¾ÝÓÉrgmiiת»¯Îªgmii£¬Ê±ÖÓΪrgmii_clk
output reg mac_rx_error,
output reg mac_rx_data_valid,
output reg [7:0] mac_rx_data,
//eth½ÓÊÕ
input rgmii_rxc,
input rgmii_rx_ctl,
input [3:0] rgmii_rxd,
//eth·¢ËÍ
output rgmii_txc,
output rgmii_tx_ctl,
output [3:0] rgmii_txd
);
//=============================================================
// RGMII TX
//=============================================================
wire rgmii_txc_obuf;
wire rgmii_txc_tbuf;
wire rgmii_tx_ctl_obuf;
wire rgmii_tx_ctl_tbuf;
wire [3:0] rgmii_txd_obuf;
wire [3:0] rgmii_txd_tbuf;
generate
genvar i;
for (i=0; i<4; i=i+1)
begin : rgmii_tx_data
GTP_OSERDES #(
.OSERDES_MODE("ODDR"), //"ODDR","OMDDR","OGSER4","OMSER4","OGSER7","OGSER8",OMSER8"
.WL_EXTEND ("FALSE"), //"TRUE"; "FALSE"
.GRS_EN ("TRUE"), //"TRUE"; "FALSE"
.LRS_EN ("TRUE"), //"TRUE"; "FALSE"
.TSDDR_INIT (1'b0) //1'b0;1'b1
) tx_data_oddr(
.DO (rgmii_txd_obuf[i]), //Êý¾ÝÊä³ö output
.TQ (rgmii_txd_tbuf[i]), //ѡͨÊä³ö output
.DI ({6'd0,mac_tx_data[i+4],mac_tx_data[i]}), //Êý¾ÝÊäÈë input
.TI (4'd0), //ѡͨÊäÈë input
.RCLK (rgmii_clk), //Êä³öʱÖÓ input
.SERCLK(rgmii_clk), //´®ÐÐʱÖÓ input
.OCLK (1'd0), //Êä³öʱÖÓ input
.RST (1'b0) //¸´Î» input
);
GTP_OUTBUFT gtp_outbuft1(
.I(rgmii_txd_obuf[i]),
.T(rgmii_txd_tbuf[i]) ,
.O(rgmii_txd[i])
);
end
endgenerate
GTP_OSERDES #(
.OSERDES_MODE("ODDR"), //"ODDR","OMDDR","OGSER4","OMSER4","OGSER7","OGSER8",OMSER8"
.WL_EXTEND ("FALSE"), //"TRUE"; "FALSE"
.GRS_EN ("TRUE"), //"TRUE"; "FALSE"
.LRS_EN ("TRUE"), //"TRUE"; "FALSE"
.TSDDR_INIT (1'b0) //1'b0;1'b1
) tx_ctl_oddr(
.DO (rgmii_tx_ctl_obuf),
.TQ (rgmii_tx_ctl_tbuf),
.DI ({6'd0,mac_tx_data_valid ^ 1'b0,mac_tx_data_valid}),
.TI (4'd0),
.RCLK (rgmii_clk),
.SERCLK(rgmii_clk),
.OCLK (1'd0),
.RST (tx_reset_sync)
);
GTP_OUTBUFT gtp_outbuft1(
.I(rgmii_tx_ctl_obuf),
.T(rgmii_tx_ctl_tbuf) ,
.O(rgmii_tx_ctl)
);
//DDRÊý¾ÝÊä³öת»»Ä£¿é
GTP_OSERDES #(
.OSERDES_MODE("ODDR"), //"ODDR","OMDDR","OGSER4","OMSER4","OGSER7","OGSER8",OMSER8"
.WL_EXTEND ("FALSE"), //"TRUE"; "FALSE"
.GRS_EN ("TRUE"), //"TRUE"; "FALSE"
.LRS_EN ("TRUE"), //"TRUE"; "FALSE"
.TSDDR_INIT (1'b0) //1'b0;1'b1
) tx_clk_oddr(
.DO (rgmii_txc_obuf),
.TQ (rgmii_txc_tbuf),
.DI ({7'd0,1'b1}),
.TI (4'd0),
.RCLK (rgmii_clk),
.SERCLK(rgmii_clk),
.OCLK (1'd0),
.RST (tx_reset_sync)
);
GTP_OUTBUFT gtp_outbuft6
(
.I(rgmii_txc_obuf),
.T(rgmii_txc_tbuf) ,
.O(rgmii_txc)
);
//=============================================================
// RGMII RX
//=============================================================
wire rgmii_rxc_ibuf;
wire rgmii_rxc_bufio;
wire rgmii_rx_ctl_ibuf;
wire [3:0] rgmii_rxd_ibuf;
wire [7:0] delay_step_b ;
wire [7:0] delay_step_gray ;
assign delay_step_b = 8'hA0; // 0~247 , 10ps/step
wire lock;
GTP_DLL #(
.GRS_EN("TRUE"),
.FAST_LOCK("TRUE"),
.DELAY_STEP_OFFSET(0)
) clk_dll (
.DELAY_STEP(delay_step_gray),// OUTPUT[7:0]
.LOCK (lock), // OUTPUT
.CLKIN (rgmii_rxc), // INPUT
.PWD (1'b0), // INPUT
.RST (1'b0), // INPUT
.UPDATE_N (1'b1) // INPUT
);
GTP_IOCLKDELAY #(
.DELAY_STEP_VALUE ( 'd127 ),
.DELAY_STEP_SEL ( "PARAMETER" ),
.SIM_DEVICE ( "LOGOS" )
) rgmii_clk_delay (
.DELAY_STEP ( delay_step_gray ),// INPUT[7:0]
.CLKOUT ( rgmii_rxc_ibuf ),// OUTPUT
.DELAY_OB ( ),// OUTPUT
.CLKIN ( rgmii_rxc ),// INPUT
.DIRECTION ( 1'b0 ),// INPUT
.LOAD ( 1'b0 ),// INPUT
.MOVE ( 1'b0 ) // INPUT
);
GTP_CLKBUFG GTP_CLKBUFG_RXSHFT(
.CLKIN (rgmii_rxc_ibuf),
.CLKOUT (rgmii_clk)
);
GTP_INBUF #(
.IOSTANDARD("DEFAULT"),
.TERM_DDR("ON")
) u_rgmii_rx_ctl_ibuf (
.O(rgmii_rx_ctl_ibuf),// OUTPUT
.I(rgmii_rx_ctl) // INPUT
);
wire rgmii_rx_ctl_delay;
parameter DELAY_STEP = 8'h0F;
wire [5:0] rx_ctl_nc;
wire gmii_ctl;
wire rgmii_rx_valid_xor_error;
GTP_ISERDES #(
.ISERDES_MODE("IDDR"),
.GRS_EN("TRUE"),
.LRS_EN("TRUE")
) gmii_ctl_in (
.DO ({rgmii_rx_valid_xor_error,gmii_ctl,rx_ctl_nc[5: 0]}), // OUTPUT[7:0]
.RADDR(3'd0), // INPUT[2:0]
.WADDR(3'd0), // INPUT[2:0]
.DESCLK(rgmii_clk),// INPUT
.DI(rgmii_rx_ctl_ibuf), // INPUT
.ICLK(1'b0), // INPUT
.RCLK(rgmii_clk), // INPUT
.RST(1'b0) // INPUT
);
wire [3:0] rgmii_rxd_delay;
wire [23:0] rxd_nc;
wire [7:0] gmii_rxd;
always @(posedge rgmii_clk)
begin
mac_rx_data <= gmii_rxd;
mac_rx_data_valid <= gmii_ctl;
mac_rx_error <= gmii_ctl ^ rgmii_rx_valid_xor_error;
end
generate
genvar j;
for (j=0; j<4; j=j+1)
begin : rgmii_rx_data
GTP_INBUF #(
.IOSTANDARD("DEFAULT"),
.TERM_DDR("ON")
) u_rgmii_rxd_ibuf (
.O(rgmii_rxd_ibuf[j]),// OUTPUT
.I(rgmii_rxd[j]) // INPUT
);
GTP_ISERDES #(
.ISERDES_MODE("IDDR"),
.GRS_EN("TRUE"),
.LRS_EN("TRUE")
) gmii_rxd_in (
.DO ({gmii_rxd[j+4],gmii_rxd[j],rxd_nc[j*6 +: 6]}), // OUTPUT[7:0]
.RADDR(3'd0), // INPUT[2:0]
.WADDR(3'd0), // INPUT[2:0]
.DESCLK(rgmii_clk),// INPUT
.DI(rgmii_rxd_ibuf[j]), // INPUT
.ICLK(1'b0), // INPUT
.RCLK(rgmii_clk), // INPUT
.RST(1'b0) // INPUT
);
end
endgenerate
endmodule |
module vesa_debug#(
parameter PIX_WIGHT = 16
)
(
input wire pix_clk,
input wire rstn,
input wire vs,
input wire de,
output reg [15 : 0] vesa_data
);
reg de_d0;
reg de_d1;
wire de_pos;
wire de_neg;
assign de_pos_d0 = de && !de_d0;
assign de_neg = !de_d0 && de_d1;
always @(posedge pix_clk)begin
if(!rstn||vs) begin
vesa_data <= 16'hA500;
end
else if(de) begin
vesa_data <= vesa_data + 'd1;
end
else if(de_neg) begin
vesa_data <= 16'hA500;
end
end
always @(posedge pix_clk)begin
if(!rstn||vs) begin
de_d0 <= 'd0;
end
else begin
de_d0 <= de;
de_d1 <= de_d0;
end
end
endmodule |
module eth_img_pkt(
input rst_n , //¸´Î»Ðźţ¬µÍµçƽÓÐЧ
//ͼÏñÏà¹ØÐźÅ
input cam_pclk , //ÏñËØʱÖÓ
input img_vsync , //֡ͬ²½ÐźÅ
input img_data_en , //Êý¾ÝÓÐЧʹÄÜÐźÅ
input [15:0] img_data , //ÓÐЧÊý¾Ý
input transfer_flag , //ͼÏñ¿ªÊ¼´«Êä±êÖ¾,1:¿ªÊ¼´«Êä 0:Í£Ö¹´«Êä
//ÒÔÌ«ÍøÏà¹ØÐźÅ
input eth_tx_clk , //ÒÔÌ«Íø·¢ËÍʱÖÓ
input udp_tx_req , //udp·¢ËÍÊý¾ÝÇëÇóÐźÅ
input udp_tx_done /* synthesis PAP_MARK_DEBUG="1" */, //udp·¢ËÍÊý¾ÝÍê³ÉÐźÅ
output reg udp_tx_start_en, //udp¿ªÊ¼·¢ËÍÐźÅ
output [31:0] udp_tx_data /* synthesis PAP_MARK_DEBUG="1" */, //udp·¢Ë͵ÄÊý¾Ý
output reg [15:0] udp_tx_byte_num //udpµ¥°ü·¢Ë͵ÄÓÐЧ×Ö½ÚÊý
);
//parameter define
parameter CMOS_H_PIXEL = 16'd960; //ͼÏñˮƽ·½Ïò·Ö±æÂÊ
parameter CMOS_V_PIXEL = 16'd540; //ͼÏñ´¹Ö±·½Ïò·Ö±æÂÊ
parameter UDP_DATA_SIZE = 16'd960; //UDPÊý¾Ý³¤¶È£¨²»°üº¬Êײ¿£©
parameter ETH_TRAN_DELAY = 11'd800; //Ö¡¼ä¸ôÑÓ³Ù
//ͼÏñÖ¡Í·,ÓÃÓÚ±êÖ¾Ò»Ö¡Êý¾ÝµÄ¿ªÊ¼
parameter IMG_FRAME_HEAD = {32'hf0_5a_a5_0f};
reg img_vsync_d0 ; //Ö¡ÓÐЧÐźŴòÅÄ
reg img_vsync_d1 ; //Ö¡ÓÐЧÐźŴòÅÄ
reg neg_vsync_d0 ; //Ö¡ÓÐЧÐźÅϽµÑØ´òÅÄ
reg neg_vsync_d1 ;
reg img_de_d0 ; //DE±ê־λ´òÅÄ
reg img_de_d1 ; //DE±ê־λ ´òÅÄ
reg eth_delay_d0 ;
reg eth_delay_d1 ;
reg wr_sw ; //ÓÃÓÚλƴ½ÓµÄ±êÖ¾
reg [15:0] img_data_d0 ; //ÓÐЧͼÏñÊý¾Ý´òÅÄ
reg wr_fifo_en /* synthesis PAP_MARK_DEBUG="1" */; //дfifoʹÄÜ
reg [31:0] wr_fifo_data /* synthesis PAP_MARK_DEBUG="1" */; //дfifoÊý¾Ý
reg img_vsync_txc_d0; //ÒÔÌ«Íø·¢ËÍʱÖÓÓòÏÂ,Ö¡ÓÐЧÐźŴòÅÄ
reg img_vsync_txc_d1; //ÒÔÌ«Íø·¢ËÍʱÖÓÓòÏÂ,Ö¡ÓÐЧÐźŴòÅÄ
reg tx_busy_flag ; //·¢ËÍæÐźűêÖ¾
reg [15 : 0] img_de_cnt /* synthesis PAP_MARK_DEBUG="1" */;//deϽµÑؼÆÊý
reg [31 : 0] img_pkt_cnt /* synthesis PAP_MARK_DEBUG="1" */;
reg [15 : 0] eth_delay_cnt /* synthesis PAP_MARK_DEBUG="1" */; //delay¼ÆÊýÆ÷
reg eth_delay_start/* synthesis PAP_MARK_DEBUG="1" */;
reg eth_delay_done /* synthesis PAP_MARK_DEBUG="1" */;
//wire define
wire pos_vsync ; //Ö¡ÓÐЧÐźÅÉÏÉýÑØ
wire neg_vsync ; //Ö¡ÓÐЧÐźÅϽµÑØ
wire neg_vsynt_txc ; //ÒÔÌ«Íø·¢ËÍʱÖÓÓòÏÂ,Ö¡ÓÐЧÐźÅϽµÑØ
wire pos_de ; //Êý¾ÝÓÐЧÐźÅÉÏÉýÑØ
wire pos_eth_delay ; //udp
wire [10:0] fifo_rdusedw /* synthesis PAP_MARK_DEBUG="1" */; //µ±Ç°FIFO»º´æµÄ¸öÊý
//*****************************************************
//** main code
//*****************************************************
//ÐźŲÉÑØ
assign neg_vsync = img_vsync_d1 & (~img_vsync_d0);
assign pos_vsync = ~img_vsync_d1 & img_vsync_d0;
assign neg_vsynt_txc = ~img_vsync_txc_d1 & img_vsync_txc_d0;
assign neg_de = (~img_de_d0) & img_de_d1;
assign pos_eth_delay = eth_delay_d0 & (~eth_delay_d1);
//¶Ôimg_vsyncÐźÅÑÓʱÁ½¸öʱÖÓÖÜÆÚ,ÓÃÓÚ²ÉÑØ
always @(posedge cam_pclk or negedge rst_n) begin
if(!rst_n) begin
img_vsync_d0 <= 1'b0;
img_vsync_d1 <= 1'b0;
img_de_d0 <= 1'b0;
img_de_d1 <= 1'b0;
eth_delay_d0 <= 'd0;//ÔÚÊäÈëʱÖÓÓò϶Ôudp·¢ËÍÍê³ÉÐźŲÉÑù
eth_delay_d1 <= 'd0;
end
else begin
img_vsync_d0 <= img_vsync;
img_vsync_d1 <= img_vsync_d0;
img_de_d0 <= img_data_en;
img_de_d1 <= img_de_d0;
eth_delay_d0 <= eth_delay_start;//ÔÚÊäÈëʱÖÓÓò϶Ôudp·¢ËÍÍê³ÉÐźŲÉÑù
eth_delay_d1 <= eth_delay_d0;
end
end
//¼Ä´æneg_vsyncÐźÅ
always @(posedge cam_pclk or negedge rst_n) begin
if(!rst_n) begin
neg_vsync_d0 <= 1'b0;
neg_vsync_d1 <= 1'b0;
end
else begin
neg_vsync_d0 <= neg_vsync;
neg_vsync_d1 <= neg_vsync_d0;
end
end
//¶Ôwr_swºÍimg_data_d0ÐźŸ³Öµ,ÓÃÓÚλƴ½Ó
always @(posedge cam_pclk or negedge rst_n) begin
if(!rst_n) begin
wr_sw <= 1'b0;
img_data_d0 <= 1'b0;
end
else if(neg_vsync)
wr_sw <= 1'b0;
else if(img_data_en) begin
wr_sw <= ~wr_sw;
img_data_d0 <= img_data;
end
end
//½«Ö¡Í·ºÍͼÏñÊý¾ÝдÈëFIFO
always @(posedge cam_pclk or negedge rst_n) begin
if(!rst_n || pos_vsync) begin
wr_fifo_en <= 1'b0;
wr_fifo_data <= 32'b0;
img_de_cnt <= 32'd0;
img_pkt_cnt <= 'd1;
end
else begin
if(neg_vsync) begin
wr_fifo_en <= 1'b1;
wr_fifo_data <= img_pkt_cnt; //UDP°ü±ê־λ
img_pkt_cnt <= img_pkt_cnt + 'd1;
end
else if(neg_vsync_d0) begin
wr_fifo_en <= 1'b1;
wr_fifo_data <= IMG_FRAME_HEAD; //Ö¡Í·
end
else if(neg_vsync_d1) begin
wr_fifo_en <= 1'b1;
wr_fifo_data <= {CMOS_H_PIXEL,CMOS_V_PIXEL}; //ˮƽºÍ´¹Ö±·½Ïò·Ö±æÂÊ
end
else if(img_data_en && wr_sw) begin
wr_fifo_en <= 1'b1;
img_de_cnt <= img_de_cnt + 'd1;
wr_fifo_data <= {img_data_d0,img_data}; //ͼÏñÊý¾Ýλƴ½Ó,16λת32λ
end
else if(img_de_cnt == 240) begin
wr_fifo_en <= 1'b1;
wr_fifo_data <= img_pkt_cnt;
img_pkt_cnt <= img_pkt_cnt + 'd1;
end
else if(neg_de) begin
wr_fifo_en <= 1'b1;
wr_fifo_data <= img_pkt_cnt; //de½áÊøºóдÈë¼ÆÊý
img_pkt_cnt <= img_pkt_cnt + 'd1;
img_de_cnt <= 'd0;
end
else begin
wr_fifo_en <= 1'b0;
wr_fifo_data <= 32'b0;
end
end
end
//ÒÔÌ«Íø·¢ËÍʱÖÓÓòÏÂ,¶Ôimg_vsyncÐźÅÑÓʱÁ½¸öʱÖÓÖÜÆÚ,ÓÃÓÚ²ÉÑØ
always @(posedge eth_tx_clk or negedge rst_n) begin
if(!rst_n) begin
img_vsync_txc_d0 <= 1'b0;
img_vsync_txc_d1 <= 1'b0;
end
else begin
img_vsync_txc_d0 <= img_vsync;
img_vsync_txc_d1 <= img_vsync_txc_d0;
end
end
//¿ØÖÆÒÔÌ«Íø·¢Ë͵Ä×Ö½ÚÊý
always @(posedge eth_tx_clk or negedge rst_n) begin
if(!rst_n)
udp_tx_byte_num <= 1'b0;
else if(neg_vsynt_txc)//vsºóµÚÒ»¸öÊý¾Ý°ü·¢ËÍͼÏñÊý¾Ý³¤¶È+Æðʼ±ê־볤¶È8Byte
//udp_tx_byte_num <= {CMOS_H_PIXEL,1'b0} + 16'd8;
udp_tx_byte_num <= UDP_DATA_SIZE + 16'd12;//16'd960 + 16'd8;
else if(udp_tx_done)//ºóÐøÕý³£°ü³¤
//udp_tx_byte_num <= {CMOS_H_PIXEL,1'b0};
udp_tx_byte_num <= UDP_DATA_SIZE + 16'd4;//16'd960;
end
//¿ØÖÆÒÔÌ«Íø·¢ËÍ¿ªÊ¼ÐźÅ
always @(posedge eth_tx_clk or negedge rst_n) begin
if(!rst_n) begin
udp_tx_start_en <= 1'b0;
tx_busy_flag <= 1'b0;
end
//ÉÏλ»úδ·¢ËÍ"¿ªÊ¼"ÃüÁîʱ,ÒÔÌ«Íø²»·¢ËÍͼÏñÊý¾Ý
else if(transfer_flag == 1'b0) begin
udp_tx_start_en <= 1'b0;
tx_busy_flag <= 1'b0;
end
else begin
udp_tx_start_en <= 1'b0;
//µ±FIFOÖеĸöÊýÂú×ãÐèÒª·¢Ë͵Ä×Ö½ÚÊýʱ ˮλ/4(32bit->8bit)
if(tx_busy_flag == 1'b0 && fifo_rdusedw >= udp_tx_byte_num[15:2]) begin
udp_tx_start_en <= 1'b1; //¿ªÊ¼¿ØÖÆ·¢ËÍÒ»°üÊý¾Ý
tx_busy_flag <= 1'b1;
end
else if(eth_delay_done|| neg_vsynt_txc)
tx_busy_flag <= 1'b0;
end
end
//×îС֡¼ä¸ô£¬ÖÁÉÙÓÐ96bitsµÄ¼ä¸ô,ǧÕ×ÒÔÌ«ÍøÒªÇó96ns£¬125Mhz->8ns£¬¼´12¸öʱÖÓÖÜÆÚ£¬ÕâÀï¸ø500+°É
always @(posedge eth_tx_clk or negedge rst_n) begin
if(!rst_n) begin
eth_delay_cnt <= 'd0;
eth_delay_start <= 'd0;
eth_delay_done <= 'd0;
end
else begin
eth_delay_done <= 'd0;
if(udp_tx_done) begin
eth_delay_start <= 'd1;
end
if(eth_delay_start) begin
eth_delay_cnt <= eth_delay_cnt + 'd1;
end
if(eth_delay_cnt >= ETH_TRAN_DELAY) begin
eth_delay_done <= 'd1;
eth_delay_start <= 'd0;
eth_delay_cnt <= 'd0;
end
end
end
reg [10:0] udp_pkt_cnt /* synthesis PAP_MARK_DEBUG="1" */; //udp°ü¼ÆÊý
always @(posedge eth_tx_clk or negedge rst_n) begin
if(!rst_n || neg_vsynt_txc) begin
udp_pkt_cnt <= 'd0;
end
else if(udp_tx_done)begin
udp_pkt_cnt <= udp_pkt_cnt + 'd1;
end
else begin
udp_pkt_cnt <= udp_pkt_cnt;
end
end
//Òì²½FIFO
eth_pkt_fifo u_eth_pkt_fifo (
.wr_clk (cam_pclk ) , // input
.wr_rst (pos_vsync | (~transfer_flag)) , // input
.wr_en (wr_fifo_en ) , // input
.wr_data (wr_fifo_data ) , // input [31:0]
.wr_full ( ) , // output
.wr_water_level ( ) , // output [10:0]
.almost_full ( ) , // output
.rd_clk (eth_tx_clk ) , // input
.rd_rst (pos_vsync | (~transfer_flag)) , // input
.rd_en (udp_tx_req ) , // input
.rd_data (udp_tx_data ) , // output [31:0]
.rd_empty ( ) , // output
.rd_water_level (fifo_rdusedw ) , // output [10:0]
.almost_empty ( ) // output
);
//eth_pkt_fifo u_eth_pkt_fifo (
// .wr_clk(wr_clk), // input
// .wr_rst(wr_rst), // input
// .wr_en(wr_en), // input
// .wr_data(wr_data), // input [31:0]
// .wr_full(wr_full), // output
// .wr_water_level(wr_water_level), // output [9:0]
// .almost_full(almost_full), // output
// .rd_clk(rd_clk), // input
// .rd_rst(rd_rst), // input
// .rd_en(rd_en), // input
// .rd_data(rd_data), // output [31:0]
// .rd_empty(rd_empty), // output
// .rd_water_level(rd_water_level), // output [9:0]
// .almost_empty(almost_empty) // output
//);
endmodule |
module udp_tx(
input clk , //ʱÖÓÐźÅ
input rst_n , //¸´Î»Ðźţ¬µÍµçƽÓÐЧ
input tx_start_en, //ÒÔÌ«Íø¿ªÊ¼·¢ËÍÐźÅ
input [31:0] tx_data /* synthesis PAP_MARK_DEBUG="1" */, //ÒÔÌ«Íø´ý·¢ËÍÊý¾Ý
input [15:0] tx_byte_num, //ÒÔÌ«Íø·¢Ë͵ÄÓÐЧ×Ö½ÚÊý
input [47:0] des_mac /* synthesis PAP_MARK_DEBUG="1" */, //·¢Ë͵ÄÄ¿±êMACµØÖ·
input [31:0] des_ip /* synthesis PAP_MARK_DEBUG="1" */, //·¢Ë͵ÄÄ¿±êIPµØÖ·
input [31:0] crc_data , //CRCУÑéÊý¾Ý
input [7:0] crc_next , //CRCÏ´ÎУÑéÍê³ÉÊý¾Ý
output reg tx_done , //ÒÔÌ«Íø·¢ËÍÍê³ÉÐźÅ
output reg tx_req /* synthesis PAP_MARK_DEBUG="1" */, //¶ÁÊý¾ÝÇëÇóÐźÅ
output reg gmii_tx_en /* synthesis PAP_MARK_DEBUG="1" */, //GMIIÊä³öÊý¾ÝÓÐЧÐźÅ
output reg [7:0] gmii_txd /* synthesis PAP_MARK_DEBUG="1" */, //GMIIÊä³öÊý¾Ý
output reg crc_en , //CRC¿ªÊ¼Ð£ÑéʹÄÜ
output reg crc_clr //CRCÊý¾Ý¸´Î»ÐźÅ
);
//parameter define
//¿ª·¢°åMACµØÖ· 00-11-22-33-44-55
parameter BOARD_MAC = 48'h00_11_22_33_44_55;
//¿ª·¢°åIPµØÖ· 192.168.1.123
parameter BOARD_IP = {8'd192,8'd168,8'd1,8'd123};
//Ä¿µÄMACµØÖ· ff_ff_ff_ff_ff_ff
parameter DES_MAC = 48'hff_ff_ff_ff_ff_ff;
//Ä¿µÄIPµØÖ· 192.168.1.102
parameter DES_IP = {8'd192,8'd168,8'd1,8'd102};
localparam st_idle = 7'b000_0001; //³õʼ״̬£¬µÈ´ý¿ªÊ¼·¢ËÍÐźÅ
localparam st_check_sum = 7'b000_0010; //IPÊײ¿Ð£ÑéºÍ
localparam st_preamble = 7'b000_0100; //·¢ËÍÇ°µ¼Âë+Ö¡Æðʼ½ç¶¨·û
localparam st_eth_head = 7'b000_1000; //·¢ËÍÒÔÌ«ÍøÖ¡Í·
localparam st_ip_head = 7'b001_0000; //·¢ËÍIPÊײ¿+UDPÊײ¿
localparam st_tx_data = 7'b010_0000; //·¢ËÍÊý¾Ý
localparam st_crc = 7'b100_0000; //·¢ËÍCRCУÑéÖµ
localparam ETH_TYPE = 16'h0800 ; //ÒÔÌ«ÍøÐÒéÀàÐÍ IPÐÒé
//ÒÔÌ«ÍøÊý¾Ý×îС46¸ö×Ö½Ú£¬IPÊײ¿20¸ö×Ö½Ú+UDPÊײ¿8¸ö×Ö½Ú
//ËùÒÔÊý¾ÝÖÁÉÙ46-20-8=18¸ö×Ö½Ú
localparam MIN_DATA_NUM = 16'd18 ;
//reg define
reg [6:0] cur_state ;
reg [6:0] next_state /* synthesis PAP_MARK_DEBUG="1" */;
reg [7:0] preamble[7:0] ; //Ç°µ¼Âë
reg [7:0] eth_head[13:0] ; //ÒÔÌ«ÍøÊײ¿
reg [31:0] ip_head[6:0] ; //IPÊײ¿ + UDPÊײ¿
reg start_en_d0 ;
reg start_en_d1 ;
reg [15:0] tx_data_num ; //·¢Ë͵ÄÓÐЧÊý¾Ý×Ö½Ú¸öÊý
reg [15:0] total_num ; //×Ü×Ö½ÚÊý
reg trig_tx_en ;
reg [15:0] udp_num ; //UDP×Ö½ÚÊý
reg skip_en ; //¿ØÖÆ״̬ÌøתʹÄÜÐźÅ
reg [4:0] cnt ;
reg [31:0] check_buffer ; //Êײ¿Ð£ÑéºÍ
reg [1:0] tx_bit_sel /* synthesis PAP_MARK_DEBUG="1" */;
reg [15:0] data_cnt /* synthesis PAP_MARK_DEBUG="1" */; //·¢ËÍÊý¾Ý¸öÊý¼ÆÊýÆ÷
reg tx_done_t ;
reg [4:0] real_add_cnt ; //ÒÔÌ«ÍøÊý¾Ýʵ¼Ê¶à·¢µÄ×Ö½ÚÊý
//wire define
wire pos_start_en ;//¿ªÊ¼·¢ËÍÊý¾ÝÉÏÉýÑØ
wire [15:0] real_tx_data_num;//ʵ¼Ê·¢Ë͵Ä×Ö½ÚÊý(ÒÔÌ«Íø×îÉÙ×Ö½ÚÒªÇó)
//*****************************************************
//** main code
//*****************************************************
assign pos_start_en = (~start_en_d1) & start_en_d0;
assign real_tx_data_num = (tx_data_num >= MIN_DATA_NUM)
? tx_data_num : MIN_DATA_NUM;
//²Étx_start_enµÄÉÏÉýÑØ
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
start_en_d0 <= 1'b0;
start_en_d1 <= 1'b0;
end
else begin
start_en_d0 <= tx_start_en;
start_en_d1 <= start_en_d0;
end
end
//¼Ä´æÊý¾ÝÓÐЧ×Ö½Ú
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
tx_data_num <= 16'd0;
total_num <= 16'd0;
udp_num <= 16'd0;
end
else begin
if(pos_start_en && cur_state==st_idle) begin
//Êý¾Ý³¤¶È
tx_data_num <= tx_byte_num;
//IP³¤¶È£ºÓÐЧÊý¾Ý+IPÊײ¿³¤¶È
total_num <= tx_byte_num + 16'd28;
//UDP³¤¶È£ºÓÐЧÊý¾Ý+UDPÊײ¿³¤¶È
udp_num <= tx_byte_num + 16'd8;
end
end
end
//´¥·¢·¢ËÍÐźÅ
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
trig_tx_en <= 1'b0;
else
trig_tx_en <= pos_start_en;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cur_state <= st_idle;
else
cur_state <= next_state;
end
always @(*) begin
next_state = st_idle;
case(cur_state)
st_idle : begin //µÈ´ý·¢ËÍÊý¾Ý
if(skip_en)
next_state = st_check_sum;
else
next_state = st_idle;
end
st_check_sum: begin //IPÊײ¿Ð£Ñé
if(skip_en)
next_state = st_preamble;
else
next_state = st_check_sum;
end
st_preamble : begin //·¢ËÍÇ°µ¼Âë+Ö¡Æðʼ½ç¶¨·û
if(skip_en)
next_state = st_eth_head;
else
next_state = st_preamble;
end
st_eth_head : begin //·¢ËÍÒÔÌ«ÍøÊײ¿
if(skip_en)
next_state = st_ip_head;
else
next_state = st_eth_head;
end
st_ip_head : begin //·¢ËÍIPÊײ¿+UDPÊײ¿
if(skip_en)
next_state = st_tx_data;
else
next_state = st_ip_head;
end
st_tx_data : begin //·¢ËÍÊý¾Ý
if(skip_en)
next_state = st_crc;
else
next_state = st_tx_data;
end
st_crc: begin //·¢ËÍCRCУÑéÖµ
if(skip_en)
next_state = st_idle;
else
next_state = st_crc;
end
default : next_state = st_idle;
endcase
end
//·¢ËÍÊý¾Ý
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
skip_en <= 1'b0;
cnt <= 5'd0;
check_buffer <= 32'd0;
ip_head[1][31:16] <= 16'd0;
tx_bit_sel <= 2'b0;
crc_en <= 1'b0;
gmii_tx_en <= 1'b0;
gmii_txd <= 8'd0;
tx_req <= 1'b0;
tx_done_t <= 1'b0;
data_cnt <= 16'd0;
real_add_cnt <= 5'd0;
//³õʼ»¯Êý×é
//Ç°µ¼Âë 7¸ö8'h55 + 1¸ö8'hd5
preamble[0] <= 8'h55;
preamble[1] <= 8'h55;
preamble[2] <= 8'h55;
preamble[3] <= 8'h55;
preamble[4] <= 8'h55;
preamble[5] <= 8'h55;
preamble[6] <= 8'h55;
preamble[7] <= 8'hd5;
//Ä¿µÄMACµØÖ·
eth_head[0] <= DES_MAC[47:40];
eth_head[1] <= DES_MAC[39:32];
eth_head[2] <= DES_MAC[31:24];
eth_head[3] <= DES_MAC[23:16];
eth_head[4] <= DES_MAC[15:8];
eth_head[5] <= DES_MAC[7:0];
//Ô´MACµØÖ·
eth_head[6] <= BOARD_MAC[47:40];
eth_head[7] <= BOARD_MAC[39:32];
eth_head[8] <= BOARD_MAC[31:24];
eth_head[9] <= BOARD_MAC[23:16];
eth_head[10] <= BOARD_MAC[15:8];
eth_head[11] <= BOARD_MAC[7:0];
//ÒÔÌ«ÍøÀàÐÍ
eth_head[12] <= ETH_TYPE[15:8];
eth_head[13] <= ETH_TYPE[7:0];
end
else begin
skip_en <= 1'b0;
tx_req <= 1'b0;
crc_en <= 1'b0;
gmii_tx_en <= 1'b0;
tx_done_t <= 1'b0;
case(next_state)
st_idle : begin
if(trig_tx_en) begin
skip_en <= 1'b1;
//°æ±¾ºÅ£º4 Êײ¿³¤¶È£º5(µ¥Î»:32bit,20byte/4=5)
ip_head[0] <= {8'h45,8'h00,total_num};
//16λ±êʶ£¬Ã¿´Î·¢ËÍÀÛ¼Ó1
ip_head[1][31:16] <= ip_head[1][31:16] + 1'b1;
//bit[15:13]: 010±íʾ²»·ÖƬ
ip_head[1][15:0] <= 16'h4000;
//ÐÒ飺17(udp)
ip_head[2] <= {8'h40,8'd17,16'h0};
//Ô´IPµØÖ·
ip_head[3] <= BOARD_IP;
//Ä¿µÄIPµØÖ·
if(des_ip != 32'd0)
ip_head[4] <= des_ip;
else
ip_head[4] <= DES_IP;
//16λԴ¶Ë¿ÚºÅ£º1234 16λĿµÄ¶Ë¿ÚºÅ£º1234
ip_head[5] <= {16'd1234,16'd1234};
//16λudp³¤¶È£¬16λudpУÑéºÍ
ip_head[6] <= {udp_num,16'h0000};
//¸üÐÂMACµØÖ·
if(des_mac != 48'b0) begin
//Ä¿µÄMACµØÖ·
eth_head[0] <= des_mac[47:40];
eth_head[1] <= des_mac[39:32];
eth_head[2] <= des_mac[31:24];
eth_head[3] <= des_mac[23:16];
eth_head[4] <= des_mac[15:8];
eth_head[5] <= des_mac[7:0];
end
end
end
st_check_sum: begin //IPÊײ¿Ð£Ñé
cnt <= cnt + 5'd1;
if(cnt == 5'd0) begin
check_buffer <= ip_head[0][31:16] + ip_head[0][15:0]
+ ip_head[1][31:16] + ip_head[1][15:0]
+ ip_head[2][31:16] + ip_head[2][15:0]
+ ip_head[3][31:16] + ip_head[3][15:0]
+ ip_head[4][31:16] + ip_head[4][15:0];
end
else if(cnt == 5'd1) //¿ÉÄܳöÏÖ½øλ,ÀÛ¼ÓÒ»´Î
check_buffer <= check_buffer[31:16] + check_buffer[15:0];
else if(cnt == 5'd2) begin //¿ÉÄÜÔٴγöÏÖ½øλ,ÀÛ¼ÓÒ»´Î
check_buffer <= check_buffer[31:16] + check_buffer[15:0];
end
else if(cnt == 5'd3) begin //°´Î»È¡·´
skip_en <= 1'b1;
cnt <= 5'd0;
ip_head[2][15:0] <= ~check_buffer[15:0];
end
end
st_preamble : begin //·¢ËÍÇ°µ¼Âë+Ö¡Æðʼ½ç¶¨·û
gmii_tx_en <= 1'b1;
gmii_txd <= preamble[cnt];
if(cnt == 5'd7) begin
skip_en <= 1'b1;
cnt <= 5'd0;
end
else
cnt <= cnt + 5'd1;
end
st_eth_head : begin //·¢ËÍÒÔÌ«ÍøÊײ¿
gmii_tx_en <= 1'b1;
crc_en <= 1'b1;
gmii_txd <= eth_head[cnt];
if (cnt == 5'd13) begin
skip_en <= 1'b1;
cnt <= 5'd0;
end
else
cnt <= cnt + 5'd1;
end
st_ip_head : begin //·¢ËÍIPÊײ¿ + UDPÊײ¿
crc_en <= 1'b1;
gmii_tx_en <= 1'b1;
tx_bit_sel <= tx_bit_sel + 2'd1;
if(tx_bit_sel == 3'd0)
gmii_txd <= ip_head[cnt][31:24];
else if(tx_bit_sel == 3'd1)
gmii_txd <= ip_head[cnt][23:16];
else if(tx_bit_sel == 3'd2) begin
gmii_txd <= ip_head[cnt][15:8];
if(cnt == 5'd6) begin
//ÌáÇ°¶ÁÇëÇóÊý¾Ý£¬µÈ´ýÊý¾ÝÓÐЧʱ·¢ËÍ
tx_req <= 1'b1;
end
end
else if(tx_bit_sel == 3'd3) begin
gmii_txd <= ip_head[cnt][7:0];
if(cnt == 5'd6) begin
skip_en <= 1'b1;
cnt <= 5'd0;
end
else
cnt <= cnt + 5'd1;
end
end
st_tx_data : begin //·¢ËÍÊý¾Ý
crc_en <= 1'b1;
gmii_tx_en <= 1'b1;
tx_bit_sel <= tx_bit_sel + 3'd1;
if(data_cnt < tx_data_num - 16'd1)
data_cnt <= data_cnt + 16'd1;
else if(data_cnt == tx_data_num - 16'd1)begin
//Èç¹û·¢Ë͵ÄÓÐЧÊý¾ÝÉÙÓÚ18¸ö×Ö½Ú£¬ÔÚºóÃæÌî²¹³äλ
//²¹³äµÄֵΪ×îºóÒ»´Î·¢Ë͵ÄÓÐЧÊý¾Ý
gmii_txd <= 8'd0;
if(data_cnt + real_add_cnt < real_tx_data_num - 16'd1)
real_add_cnt <= real_add_cnt + 5'd1;
else begin
skip_en <= 1'b1;
data_cnt <= 16'd0;
real_add_cnt <= 5'd0;
tx_bit_sel <= 3'd0;
end
end
if(tx_bit_sel == 1'b0)
gmii_txd <= tx_data[23:16];
else if(tx_bit_sel == 3'd1)
gmii_txd <= tx_data[31:24];
else if(tx_bit_sel == 3'd2) begin
gmii_txd <= tx_data[7:0];
if(data_cnt != tx_data_num - 16'd2)
tx_req <= 1'b1;
end
else if(tx_bit_sel == 3'd3)
gmii_txd <= tx_data[15:8];
end
st_crc : begin //·¢ËÍCRCУÑéÖµ
gmii_tx_en <= 1'b1;
tx_bit_sel <= tx_bit_sel + 3'd1;
if(tx_bit_sel == 3'd0)
gmii_txd <= {~crc_next[0], ~crc_next[1], ~crc_next[2],~crc_next[3],
~crc_next[4], ~crc_next[5], ~crc_next[6],~crc_next[7]};
else if(tx_bit_sel == 3'd1)
gmii_txd <= {~crc_data[16], ~crc_data[17], ~crc_data[18],~crc_data[19],
~crc_data[20], ~crc_data[21], ~crc_data[22],~crc_data[23]};
else if(tx_bit_sel == 3'd2) begin
gmii_txd <= {~crc_data[8], ~crc_data[9], ~crc_data[10],~crc_data[11],
~crc_data[12], ~crc_data[13], ~crc_data[14],~crc_data[15]};
end
else if(tx_bit_sel == 3'd3) begin
gmii_txd <= {~crc_data[0], ~crc_data[1], ~crc_data[2],~crc_data[3],
~crc_data[4], ~crc_data[5], ~crc_data[6],~crc_data[7]};
tx_done_t <= 1'b1;
skip_en <= 1'b1;
end
end
default :;
endcase
end
end
//·¢ËÍÍê³ÉÐźż°crcÖµ¸´Î»ÐźÅ
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
tx_done <= 1'b0;
crc_clr <= 1'b0;
end
else begin
tx_done <= tx_done_t;
crc_clr <= tx_done_t;
end
end
endmodule |
module crc32_d8(
input clk , //ʱÖÓÐźÅ
input rst_n , //¸´Î»Ðźţ¬µÍµçƽÓÐЧ
input [7:0] data , //ÊäÈë´ýУÑé8λÊý¾Ý
input crc_en , //crcʹÄÜ£¬¿ªÊ¼Ð£Ñé±êÖ¾
input crc_clr , //crcÊý¾Ý¸´Î»ÐźÅ
output reg [31:0] crc_data, //CRCУÑéÊý¾Ý
output [31:0] crc_next //CRCÏ´ÎУÑéÍê³ÉÊý¾Ý
);
//*****************************************************
//** main code
//*****************************************************
//ÊäÈë´ýУÑé8λÊý¾Ý,ÐèÒªÏȽ«¸ßµÍ뻥»»
wire [7:0] data_t;
assign data_t = {data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7]};
//CRC32µÄÉú³É¶àÏîʽΪ£ºG(x)= x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11
//+ x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
assign crc_next[0] = crc_data[24] ^ crc_data[30] ^ data_t[0] ^ data_t[6];
assign crc_next[1] = crc_data[24] ^ crc_data[25] ^ crc_data[30] ^ crc_data[31]
^ data_t[0] ^ data_t[1] ^ data_t[6] ^ data_t[7];
assign crc_next[2] = crc_data[24] ^ crc_data[25] ^ crc_data[26] ^ crc_data[30]
^ crc_data[31] ^ data_t[0] ^ data_t[1] ^ data_t[2] ^ data_t[6]
^ data_t[7];
assign crc_next[3] = crc_data[25] ^ crc_data[26] ^ crc_data[27] ^ crc_data[31]
^ data_t[1] ^ data_t[2] ^ data_t[3] ^ data_t[7];
assign crc_next[4] = crc_data[24] ^ crc_data[26] ^ crc_data[27] ^ crc_data[28]
^ crc_data[30] ^ data_t[0] ^ data_t[2] ^ data_t[3] ^ data_t[4]
^ data_t[6];
assign crc_next[5] = crc_data[24] ^ crc_data[25] ^ crc_data[27] ^ crc_data[28]
^ crc_data[29] ^ crc_data[30] ^ crc_data[31] ^ data_t[0]
^ data_t[1] ^ data_t[3] ^ data_t[4] ^ data_t[5] ^ data_t[6]
^ data_t[7];
assign crc_next[6] = crc_data[25] ^ crc_data[26] ^ crc_data[28] ^ crc_data[29]
^ crc_data[30] ^ crc_data[31] ^ data_t[1] ^ data_t[2] ^ data_t[4]
^ data_t[5] ^ data_t[6] ^ data_t[7];
assign crc_next[7] = crc_data[24] ^ crc_data[26] ^ crc_data[27] ^ crc_data[29]
^ crc_data[31] ^ data_t[0] ^ data_t[2] ^ data_t[3] ^ data_t[5]
^ data_t[7];
assign crc_next[8] = crc_data[0] ^ crc_data[24] ^ crc_data[25] ^ crc_data[27]
^ crc_data[28] ^ data_t[0] ^ data_t[1] ^ data_t[3] ^ data_t[4];
assign crc_next[9] = crc_data[1] ^ crc_data[25] ^ crc_data[26] ^ crc_data[28]
^ crc_data[29] ^ data_t[1] ^ data_t[2] ^ data_t[4] ^ data_t[5];
assign crc_next[10] = crc_data[2] ^ crc_data[24] ^ crc_data[26] ^ crc_data[27]
^ crc_data[29] ^ data_t[0] ^ data_t[2] ^ data_t[3] ^ data_t[5];
assign crc_next[11] = crc_data[3] ^ crc_data[24] ^ crc_data[25] ^ crc_data[27]
^ crc_data[28] ^ data_t[0] ^ data_t[1] ^ data_t[3] ^ data_t[4];
assign crc_next[12] = crc_data[4] ^ crc_data[24] ^ crc_data[25] ^ crc_data[26]
^ crc_data[28] ^ crc_data[29] ^ crc_data[30] ^ data_t[0]
^ data_t[1] ^ data_t[2] ^ data_t[4] ^ data_t[5] ^ data_t[6];
assign crc_next[13] = crc_data[5] ^ crc_data[25] ^ crc_data[26] ^ crc_data[27]
^ crc_data[29] ^ crc_data[30] ^ crc_data[31] ^ data_t[1]
^ data_t[2] ^ data_t[3] ^ data_t[5] ^ data_t[6] ^ data_t[7];
assign crc_next[14] = crc_data[6] ^ crc_data[26] ^ crc_data[27] ^ crc_data[28]
^ crc_data[30] ^ crc_data[31] ^ data_t[2] ^ data_t[3] ^ data_t[4]
^ data_t[6] ^ data_t[7];
assign crc_next[15] = crc_data[7] ^ crc_data[27] ^ crc_data[28] ^ crc_data[29]
^ crc_data[31] ^ data_t[3] ^ data_t[4] ^ data_t[5] ^ data_t[7];
assign crc_next[16] = crc_data[8] ^ crc_data[24] ^ crc_data[28] ^ crc_data[29]
^ data_t[0] ^ data_t[4] ^ data_t[5];
assign crc_next[17] = crc_data[9] ^ crc_data[25] ^ crc_data[29] ^ crc_data[30]
^ data_t[1] ^ data_t[5] ^ data_t[6];
assign crc_next[18] = crc_data[10] ^ crc_data[26] ^ crc_data[30] ^ crc_data[31]
^ data_t[2] ^ data_t[6] ^ data_t[7];
assign crc_next[19] = crc_data[11] ^ crc_data[27] ^ crc_data[31] ^ data_t[3] ^ data_t[7];
assign crc_next[20] = crc_data[12] ^ crc_data[28] ^ data_t[4];
assign crc_next[21] = crc_data[13] ^ crc_data[29] ^ data_t[5];
assign crc_next[22] = crc_data[14] ^ crc_data[24] ^ data_t[0];
assign crc_next[23] = crc_data[15] ^ crc_data[24] ^ crc_data[25] ^ crc_data[30]
^ data_t[0] ^ data_t[1] ^ data_t[6];
assign crc_next[24] = crc_data[16] ^ crc_data[25] ^ crc_data[26] ^ crc_data[31]
^ data_t[1] ^ data_t[2] ^ data_t[7];
assign crc_next[25] = crc_data[17] ^ crc_data[26] ^ crc_data[27] ^ data_t[2] ^ data_t[3];
assign crc_next[26] = crc_data[18] ^ crc_data[24] ^ crc_data[27] ^ crc_data[28]
^ crc_data[30] ^ data_t[0] ^ data_t[3] ^ data_t[4] ^ data_t[6];
assign crc_next[27] = crc_data[19] ^ crc_data[25] ^ crc_data[28] ^ crc_data[29]
^ crc_data[31] ^ data_t[1] ^ data_t[4] ^ data_t[5] ^ data_t[7];
assign crc_next[28] = crc_data[20] ^ crc_data[26] ^ crc_data[29] ^ crc_data[30]
^ data_t[2] ^ data_t[5] ^ data_t[6];
assign crc_next[29] = crc_data[21] ^ crc_data[27] ^ crc_data[30] ^ crc_data[31]
^ data_t[3] ^ data_t[6] ^ data_t[7];
assign crc_next[30] = crc_data[22] ^ crc_data[28] ^ crc_data[31] ^ data_t[4] ^ data_t[7];
assign crc_next[31] = crc_data[23] ^ crc_data[29] ^ data_t[5];
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
crc_data <= 32'hff_ff_ff_ff;
else if(crc_clr) //CRCУÑéÖµ¸´Î»
crc_data <= 32'hff_ff_ff_ff;
else if(crc_en)
crc_data <= crc_next;
end
endmodule |
module hdmi_ctrl(
input clk,
input rst_n,
output init_over,
output iic_tx_scl,
inout iic_tx_sda,
output iic_scl,
inout iic_sda
);
reg rstn_temp1,rstn_temp2;
reg rstn;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
rstn_temp1 <= 1'b0;
else
rstn_temp1 <= rst_n;
end
always @(posedge clk)
begin
rstn_temp2 <= rstn_temp1;
rstn <= rstn_temp2;
end
wire init_over_rx;
wire [7:0] device_id_rx;
wire iic_trig_rx ;
wire w_r_rx ;
wire [15:0] addr_rx /*synthesis PAP_MARK_DEBUG="true"*/;
wire [ 7:0] data_in_rx ;
wire busy_rx ;
wire [ 7:0] data_out_rx ;
wire byte_over_rx;
wire [7:0] device_id_tx;
wire iic_trig_tx ;
wire w_r_tx ;
wire [15:0] addr_tx /*synthesis PAP_MARK_DEBUG="true"*/;
wire [ 7:0] data_in_tx ;
wire busy_tx ;
wire [ 7:0] data_out_tx ;
wire byte_over_tx;
// wire [7:0] device_id ;
// wire iic_trig ;
// wire w_r ;
// wire [15:0] addr /*synthesis PAP_MARK_DEBUG="true"*/;
// wire [ 7:0] data_in ;
// wire busy ;
// wire [ 7:0] data_out /*synthesis PAP_MARK_DEBUG="true"*/;
// wire byte_over /*synthesis PAP_MARK_DEBUG="true"*/;
ms7200_ctrl user_ms7200_ctrl(
.clk ( clk ),//input
.rstn ( rstn ),//input
.init_over ( init_over_rx ),//output reg
.device_id ( device_id_rx ),//output [7:0]
.iic_trig ( iic_trig_rx ),//output reg
.w_r ( w_r_rx ),//output reg
.addr ( addr_rx ),//output reg [15:0]
.data_in ( data_in_rx ),//output reg [ 7:0]
.busy ( busy_rx ),//input
.data_out ( data_out_rx ),//input [ 7:0]
.byte_over ( byte_over_rx ) //input
);
ms7210_ctrl user_ms7210_ctrl(
.clk ( clk ),//input
.rstn ( init_over_rx ),//input rstn),//
.init_over ( init_over ),//output reg
.device_id ( device_id_tx ),//output [7:0]
.iic_trig ( iic_trig_tx ),//output reg
.w_r ( w_r_tx ),//output reg
.addr ( addr_tx ),//output reg [15:0]
.data_in ( data_in_tx ),//output reg [ 7:0]
.busy ( busy_tx ),//input
.data_out ( data_out_tx ),//input [ 7:0]
.byte_over ( byte_over_tx ) //input
);
// assign device_id = (init_over_rx == 1'b1 && init_over == 1'b0) ? device_id_tx : device_id_rx;
// assign iic_trig = (init_over_rx == 1'b1 && init_over == 1'b0) ? iic_trig_tx : iic_trig_rx;
// assign w_r = (init_over_rx == 1'b1 && init_over == 1'b0) ? w_r_tx : w_r_rx;
// assign addr = (init_over_rx == 1'b1 && init_over == 1'b0) ? addr_tx : addr_rx;
// assign data_in = (init_over_rx == 1'b1 && init_over == 1'b0) ? data_in_tx : data_in_rx;
// assign busy_tx = (init_over_rx == 1'b1 && init_over == 1'b0) ? busy : 0;
// assign data_out_tx = (init_over_rx == 1'b1 && init_over == 1'b0) ? data_out : 0;
// assign byte_over_tx = (init_over_rx == 1'b1 && init_over == 1'b0) ? byte_over : 0;
//
// assign busy_rx = (init_over_rx == 1'b0 || init_over == 1'b1) ? busy : 0;
// assign data_out_rx = (init_over_rx == 1'b0 || init_over == 1'b1) ? data_out : 0;
// assign byte_over_rx = (init_over_rx == 1'b0 || init_over == 1'b1) ? byte_over : 0;
wire sda_in/*synthesis PAP_MARK_DEBUG="true"*/;
wire sda_out/*synthesis PAP_MARK_DEBUG="true"*/;
wire sda_out_en/*synthesis PAP_MARK_DEBUG="true"*/;
iic_rx_driver #(
.CLK_FRE ( 27'd10_000_000 ),//parameter CLK_FRE = 27'd50_000_000,//system clock frequency
.IIC_FREQ ( 20'd400_000 ),//parameter IIC_FREQ = 20'd400_000, //I2c clock frequency
.T_WR ( 10'd1 ),//parameter T_WR = 10'd5, //I2c transmit delay ms
.ADDR_BYTE ( 2'd2 ),//parameter ADDR_BYTE = 2'd1, //I2C addr byte number
.LEN_WIDTH ( 8'd3 ),//parameter LEN_WIDTH = 8'd3, //I2C transmit byte width
.DATA_BYTE ( 2'd1 ) //parameter DATA_BYTE = 2'd1 //I2C data byte number
)user_iic_rx_driver(
.clk ( clk ),//input clk,
.rstn ( rstn ),//input rstn,
.device_id ( device_id_rx ),//input device_id,
.pluse ( iic_trig_rx ),//input pluse, //I2C transmit trigger
.w_r ( w_r_rx ),//input w_r, //I2C transmit direction 1:send 0:receive
.byte_len ( 4'd1 ),//input [LEN_WIDTH:0] byte_len, //I2C transmit data byte length of once trigger
.addr ( addr_rx ),//input [7:0] addr, //I2C transmit addr
.data_in ( data_in_rx ),//input [7:0] data_in, //I2C send data
.busy ( busy_rx ),//output reg busy=0, //I2C bus status
.byte_over ( byte_over_rx ),//output reg byte_over=0, //I2C byte transmit over flag
.data_out ( data_out_rx ),//output reg[7:0] data_out, //I2C receive data
.scl ( iic_scl ),//output scl,
.sda_in ( sda_in ),//input sda_in,
.sda_out ( sda_out ),//output reg sda_out=1'b1,
.sda_out_en ( sda_out_en ) //output sda_out_en
);
assign iic_sda = sda_out_en ? sda_out : 1'bz;
assign sda_in = iic_sda;
wire sda_tx_in/*synthesis PAP_MARK_DEBUG="true"*/;
wire sda_tx_out/*synthesis PAP_MARK_DEBUG="true"*/;
wire sda_tx_out_en/*synthesis PAP_MARK_DEBUG="true"*/;
iic_tx_driver #(
.CLK_FRE ( 27'd10_000_000 ),//parameter CLK_FRE = 27'd50_000_000,//system clock frequency
.IIC_FREQ ( 20'd400_000 ),//parameter IIC_FREQ = 20'd400_000, //I2c clock frequency
.T_WR ( 10'd1 ),//parameter T_WR = 10'd5, //I2c transmit delay ms
.ADDR_BYTE ( 2'd2 ),//parameter ADDR_BYTE = 2'd1, //I2C addr byte number
.LEN_WIDTH ( 8'd3 ),//parameter LEN_WIDTH = 8'd3, //I2C transmit byte width
.DATA_BYTE ( 2'd1 ) //parameter DATA_BYTE = 2'd1 //I2C data byte number
)user_iic_tx_driver(
.clk ( clk ),//input clk,
.rstn ( rstn ),//input rstn,
.device_id ( device_id_tx ),//input device_id,
.pluse ( iic_trig_tx ),//input pluse, //I2C transmit trigger
.w_r ( w_r_tx ),//input w_r, //I2C transmit direction 1:send 0:receive
.byte_len ( 4'd1 ),//input [LEN_WIDTH:0] byte_len, //I2C transmit data byte length of once trigger
.addr ( addr_tx ),//input [7:0] addr, //I2C transmit addr
.data_in ( data_in_tx ),//input [7:0] data_in, //I2C send data
.busy ( busy_tx ),//output reg busy=0, //I2C bus status
.byte_over ( byte_over_tx ),//output reg byte_over=0, //I2C byte transmit over flag
.data_out ( data_out_tx ),//output reg[7:0] data_out, //I2C receive data
.scl ( iic_tx_scl ),//output scl,
.sda_in ( sda_tx_in ),//input sda_in,
.sda_out ( sda_tx_out ),//output reg sda_out=1'b1,
.sda_out_en ( sda_tx_out_en ) //output sda_out_en
);
assign iic_tx_sda = sda_tx_out_en ? sda_tx_out : 1'bz;
assign sda_tx_in = iic_tx_sda;
// GTP_IOBUF #(
// .IOSTANDARD ( "DEFAULT" ),
// .SLEW_RATE ( "SLOW" ),
// .DRIVE_STRENGTH ( "8" ),
// .TERM_DDR ( "ON" )
// ) GTP_IOBUF (
// .IO ( iic_sda ),// INOUT
// .O ( sda_in ), // OUTPUT
// .I ( sda_out ), // INPUT
// .T ( sda_out_en ) // INPUT
// );
endmodule |
module interpolation_ram0_tb;
localparam T_CLK_PERIOD = 10 ; //clock a half perid
localparam T_RST_TIME = 200 ; //reset time
localparam WR_ADDR_WIDTH = 11 ; // @IPC int 9,20
localparam WR_DATA_WIDTH = 16 ; // @IPC int 1,1152
localparam RD_ADDR_WIDTH = 11 ; // @IPC int 9,20
localparam RD_DATA_WIDTH = 16 ; // @IPC int 1,1152
localparam OUTPUT_REG = 0 ; // @IPC bool
localparam RD_OCE_EN = 0 ; // @IPC bool
localparam RD_CLK_OR_POL_INV = 0 ; // @IPC bool
localparam RESET_TYPE = "ASYNC" ; // @IPC enum Sync_Internally,SYNC,ASYNC
localparam POWER_OPT = 0 ; // @IPC bool
localparam INIT_FILE = "NONE" ; // @IPC string
localparam INIT_FORMAT = "BIN" ; // @IPC enum BIN,HEX
localparam WR_BYTE_EN = 0 ; // @IPC bool
localparam BE_WIDTH = 1 ; // @IPC int 2,128
localparam RD_BE_WIDTH = 1 ; // @IPC int 2,128
localparam BYTE_SIZE = 8 ; // @IPC enum 8,9
localparam INIT_EN = 0 ; // @IPC bool
localparam SAMEWIDTH_EN = 1 ; // @IPC bool
localparam WR_CLK_EN = 0 ; // @IPC bool
localparam RD_CLK_EN = 0 ; // @IPC bool
localparam WR_ADDR_STROBE_EN = 0 ; // @IPC bool
localparam RD_ADDR_STROBE_EN = 0 ; // @IPC bool
localparam RESET_TYPE_CTRL = (RESET_TYPE == "ASYNC") ? "ASYNC_RESET" :
(RESET_TYPE == "SYNC") ? "SYNC_RESET" : "ASYNC_RESET_SYNC_RELEASE";
localparam DEVICE_NAME = "PGL50H";
localparam WR_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? 10 : WR_DATA_WIDTH;
localparam RD_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? 10 : RD_DATA_WIDTH;
// variable declaration
reg wr_clk ;
reg rd_clk ;
reg tb_wr_rst ;
wire tb_wr_clk ;
reg tb_wr_clk_en ;
reg tb_wr_en ;
reg [WR_ADDR_WIDTH :0] tb_wr_addr ;
reg tb_wr_addr_strobe ;
reg [BE_WIDTH-1:0] tb_wr_byte_en ;
reg [WR_DATA_WIDTH-1:0] tb_wrdata_cnt ;
reg tb_rd_rst ;
wire tb_rd_clk ;
reg tb_rd_clk_en ;
reg [RD_ADDR_WIDTH :0] tb_rd_addr ;
reg tb_rd_addr_strobe ;
reg tb_rd_oce ;
wire [RD_DATA_WIDTH-1:0] tb_rddata ;
reg tb_rd_en ;
reg tb_rd_en_dly ;
reg tb_rd_en_2dly ;
reg [RD_DATA_WIDTH-1:0] tb_rddata_cnt ;
reg [RD_DATA_WIDTH-1:0] tb_rddata_cnt_dly ;
reg [RD_DATA_WIDTH-1:0] tb_expected_data ;
reg check_err ;
reg [2:0] results_cnt ;
//************************************************************ CGU ****************************************************************************
initial
begin
wr_clk = 1'b0 ;
tb_wr_en = 1'b0 ;
tb_wr_addr = {WR_ADDR_WIDTH+1{1'b0}} ;
tb_wrdata_cnt = {WR_DATA_WIDTH{1'b0}} ;
rd_clk = 1'b0 ;
tb_rd_addr = {RD_ADDR_WIDTH+1{1'b0}} ;
tb_rd_en = 1'b0 ;
tb_rddata_cnt = {RD_DATA_WIDTH{1'b0}} ;
tb_rddata_cnt_dly = {RD_DATA_WIDTH{1'b0}} ;
if (WR_CLK_EN == 1)
tb_wr_clk_en = 1'b1 ;
else
tb_wr_clk_en = 1'b0 ;
if (WR_BYTE_EN == 1)
tb_wr_byte_en = {BE_WIDTH{1'b1}} ;
else
tb_wr_byte_en = {BE_WIDTH{1'b0}} ;
if (WR_ADDR_STROBE_EN == 1)
tb_wr_addr_strobe = 1'b0 ;
else
tb_wr_addr_strobe = 1'b0 ;
if (RD_CLK_EN == 1)
tb_rd_clk_en = 1'b1 ;
else
tb_rd_clk_en = 1'b0 ;
if (RD_OCE_EN == 1)
tb_rd_oce = 1'b1 ;
else
tb_rd_oce = 1'b0 ;
if (RD_ADDR_STROBE_EN == 1)
tb_rd_addr_strobe = 1'b0 ;
else
tb_rd_addr_strobe = 1'b0 ;
end
initial
begin
forever #(T_CLK_PERIOD/2) wr_clk = ~wr_clk ;
end
initial
begin
forever #(T_CLK_PERIOD/2) rd_clk = ~rd_clk ;
end
assign tb_wr_clk = wr_clk;
assign tb_rd_clk = (RD_CLK_OR_POL_INV == 1) ? ~rd_clk : rd_clk;
task write_sdpram ;
input write_sdpram ;
begin
while ( tb_wr_addr < 2**WR_ADDR_WIDTH )
begin
@(posedge wr_clk) ;
tb_wr_en = 1'b1 ;
tb_wr_addr = tb_wr_addr + {{WR_ADDR_WIDTH{1'b0}},1'b1} ;
end
tb_wr_en = 1'b0 ;
end
endtask
task read_sdpram ;
input read_sdpram ;
begin
while (tb_rd_addr < 2**RD_ADDR_WIDTH )
begin
@(posedge rd_clk) ;
tb_rd_en = 1'b1 ;
tb_rd_addr = tb_rd_addr + {{RD_ADDR_WIDTH{1'b0}},1'b1} ;
end
tb_rd_en =1'b0 ;
end
endtask
initial begin
tb_wr_rst = 1'b1 ;
tb_rd_rst = 1'b1 ;
#T_RST_TIME ;
tb_wr_rst = 1'b0 ;
tb_rd_rst = 1'b0 ;
#10 ;
if(INIT_FILE == "NONE") begin
$display("Writing SDPRAM") ;
write_sdpram(1) ;
#10 ;
$display("Reading SDPRAM") ;
read_sdpram(1) ;
#10 ;
$display("SDPRAM Simulation is Done.") ;
end
else begin
$display("Reading Initial SDPRAM") ;
read_sdpram(1) ;
end
if (|results_cnt)
$display("Simulation Failed due to Error Found.") ;
else
$display("Simulation Success.") ;
#500 ;
$finish ;
end
always@(posedge wr_clk or posedge tb_wr_rst)
begin
if(tb_wr_rst)
tb_wrdata_cnt <= {WR_DATA_WIDTH{1'b1}} ;
else if (tb_wr_en)
tb_wrdata_cnt <= tb_wrdata_cnt - {{WR_DATA_WIDTH-1{1'b0}},1'b1} ;
end
always@(posedge rd_clk or posedge tb_rd_rst)
begin
if(tb_rd_rst)
tb_rddata_cnt <= {RD_DATA_WIDTH{1'b1}} ;
else if (!tb_rd_en)
tb_rddata_cnt <= {RD_DATA_WIDTH{1'b1}} ;
else if (((RD_OCE_EN == 1'b1) && (tb_rd_oce))
|| (RD_OCE_EN == 1'b0))
tb_rddata_cnt <= tb_rddata_cnt - {{RD_DATA_WIDTH-1{1'b0}},1'b1} ;
end
always@(posedge tb_rd_clk or posedge tb_rd_rst)
begin
if (tb_rd_rst)
tb_rddata_cnt_dly <= {RD_DATA_WIDTH{1'b0}} ;
else
tb_rddata_cnt_dly <= tb_rddata_cnt ;
end
always@(posedge tb_rd_clk or posedge tb_rd_rst)
begin
if (tb_rd_rst)
begin
tb_rd_en_dly <= 1'b0;
tb_rd_en_2dly <= 1'b0;
end
else
begin
tb_rd_en_dly <= tb_rd_en;
tb_rd_en_2dly <= tb_rd_en_dly;
end
end
always@(posedge tb_rd_clk or posedge tb_rd_rst)
begin
if (tb_rd_rst)
tb_expected_data <= {RD_DATA_WIDTH{1'b0}} ;
else if (RD_OCE_EN == 1'b1)
begin
if (tb_rd_oce)
tb_expected_data <= tb_rddata_cnt_dly ;
end
else if (OUTPUT_REG == 1'b1)
tb_expected_data <= tb_rddata_cnt_dly ;
else
tb_expected_data <= tb_rddata_cnt ;
end
always@(posedge tb_rd_clk or posedge tb_rd_rst)
begin
if(tb_rd_rst)
check_err <= 1'b0;
else if(INIT_FILE == "NONE")
begin
if (((RD_OCE_EN == 1'b1) && (tb_rd_en_2dly) && (tb_rd_oce))
|| ((OUTPUT_REG == 1'b0) && (tb_rd_en_dly))
|| ((OUTPUT_REG == 1'b1) && (tb_rd_en_2dly)))
check_err <= (tb_expected_data != tb_rddata) ;
else
check_err <= 1'b0;
end
else
check_err <= 1'b0;
end
always@(posedge tb_rd_clk or posedge tb_rd_rst)
begin
if (tb_rd_rst)
results_cnt <= 3'b000 ;
else if (&results_cnt)
results_cnt <= 3'b100 ;
else if (check_err)
results_cnt <= results_cnt + 3'd1 ;
end
//***************************************************************** DUT INST **************************************************************************************
GTP_GRS GRS_INST(
.GRS_N(1'b1)
) ;
interpolation_ram0 U_interpolation_ram0 (
.wr_data ( tb_wrdata_cnt ),
.wr_addr ( tb_wr_addr[WR_ADDR_WIDTH-1:0] ),
.wr_en ( tb_wr_en ),
.wr_clk ( wr_clk ),
.wr_rst ( tb_wr_rst ),
.rd_data ( tb_rddata ),
.rd_addr ( tb_rd_addr[RD_ADDR_WIDTH-1:0] ),
.rd_clk ( rd_clk ),
.rd_rst ( tb_rd_rst )
) ;
endmodule |
module ddr_test_ddrphy_top #(
parameter [15:0] T200US = 16'd20000 ,
parameter [15:0] T500US = 16'd50000 ,
parameter MEM_TYPE = "DDR3" ,
parameter [7:0] TMRD = 4/4 ,
parameter [7:0] TMOD = 12/4 ,
parameter [9:0] TZQINIT = 10'd128,
parameter [7:0] TXPR = 31 ,
parameter [7:0] TRP = 2 ,
parameter [7:0] TRFC = 30 ,
parameter [7:0] TRCD = 2 ,
parameter MEM_ADDR_WIDTH = 15 ,
parameter MEM_BANK_WIDTH = 3 ,
parameter MEM_DQ_WIDTH = 32 ,
parameter MEM_DM_WIDTH = 4 ,
parameter MEM_DQS_WIDTH = 4 ,
parameter REGION_NUM = 3 ,
parameter DM_GROUP_EN = 0
)(
//clk
input ref_clk ,
input ddr_rstn ,
input pll_lock ,
output ddrphy_ioclk_gate ,
output ddrphy_pll_rst ,
output ddrphy_dqs_rst ,
input ddrphy_clkin ,
input [8:0] ddrphy_ioclk ,
input ioclk_gate_clk ,
//rst
input ddrphy_gate_update_en,
output [MEM_DQS_WIDTH-1:0] update_com_val_err_flag,
input [1:0] init_read_clk_ctrl ,
input [3:0] init_slip_step ,
input [7:0] init_samp_position ,
input force_read_clk_ctrl ,
//dfi
input [4*MEM_ADDR_WIDTH-1:0] dfi_address ,
input [4*MEM_BANK_WIDTH-1:0] dfi_bank ,
input [3:0] dfi_cs_n ,
input [3:0] dfi_cas_n ,
input [3:0] dfi_ras_n ,
input [3:0] dfi_we_n ,
input [3:0] dfi_cke ,
input [3:0] dfi_odt ,
input [3:0] dfi_wrdata_en ,
input [8*MEM_DQ_WIDTH-1:0] dfi_wrdata ,
input [8*MEM_DM_WIDTH-1:0] dfi_wrdata_mask ,
output [8*MEM_DQ_WIDTH-1:0] dfi_rddata ,
output dfi_rddata_valid ,
input dfi_reset_n ,
output dfi_phyupd_req ,
input dfi_phyupd_ack ,
output dfi_init_complete ,
output dfi_error ,
input rd_fake_stop ,
output mem_rst_n ,
output mem_ck ,
output mem_ck_n ,
output mem_cke ,
output mem_cs_n ,
output mem_ras_n ,
output mem_cas_n ,
output mem_we_n ,
output mem_odt ,
output [MEM_ADDR_WIDTH-1:0] mem_a ,
output [MEM_BANK_WIDTH-1:0] mem_ba ,
inout [MEM_DQS_WIDTH-1:0] mem_dqs ,
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n ,
inout [MEM_DQ_WIDTH-1:0] mem_dq ,
output [MEM_DM_WIDTH-1:0] mem_dm ,
output [21:0] debug_calib_ctrl ,
output [34*MEM_DQS_WIDTH -1:0] debug_data ,
output [13*MEM_DQS_WIDTH -1:0] debug_slice_state ,
output [7:0] ck_dly_set_bin ,
input [7:0] force_ck_dly_set_bin ,
input force_ck_dly_en ,
output [7:0] dll_step ,
output dll_lock
);
localparam real CLKIN_FREQ = 50.0 ;
//MR0_DDR3
localparam [0:0] DDR3_PPD = 1'b1;
localparam [2:0] DDR3_WR = 3'd2;
localparam [0:0] DDR3_DLL = 1'b1;
localparam [0:0] DDR3_TM = 1'b0;
localparam [0:0] DDR3_RBT = 1'b0;
localparam [3:0] DDR3_CL = 4'd4;
localparam [1:0] DDR3_BL = 2'b00;
localparam [15:0] MR0_DDR3 = {3'b000, DDR3_PPD, DDR3_WR, DDR3_DLL, DDR3_TM, DDR3_CL[3:1], DDR3_RBT, DDR3_CL[0], DDR3_BL};
//MR1_DDR3
localparam [0:0] DDR3_QOFF = 1'b0;
localparam [0:0] DDR3_TDQS = 1'b0;
localparam [2:0] DDR3_RTT_NOM = 3'b001;
localparam [0:0] DDR3_LEVEL = 1'b0;
localparam [1:0] DDR3_DIC = 2'b00;
localparam [1:0] DDR3_AL = 2'd2;
localparam [0:0] DDR3_DLL_EN = 1'b0;
localparam [15:0] MR1_DDR3 = {1'b0, DDR3_QOFF, DDR3_TDQS, 1'b0, DDR3_RTT_NOM[2], 1'b0, DDR3_LEVEL, DDR3_RTT_NOM[1], DDR3_DIC[1], DDR3_AL, DDR3_RTT_NOM[0], DDR3_DIC[0], DDR3_DLL_EN};
//MR2_DDR3
localparam [1:0] DDR3_RTT_WR = 2'b00;
localparam [0:0] DDR3_SRT = 1'b0;
localparam [0:0] DDR3_ASR = 1'b0;
localparam [2:0] DDR3_CWL = 5 - 5;
localparam [2:0] DDR3_PASR = 3'b000;
localparam [15:0] MR2_DDR3 = {5'b00000, DDR3_RTT_WR, 1'b0, DDR3_SRT, DDR3_ASR, DDR3_CWL, DDR3_PASR};
//MR3_DDR3
localparam [0:0] DDR3_MPR = 1'b0;
localparam [1:0] DDR3_MPR_LOC = 2'b00;
localparam [15:0] MR3_DDR3 = {13'b0, DDR3_MPR, DDR3_MPR_LOC};
wire dll_update_n ;
wire dll_update_n_syn ;
wire ddrphy_dll_rst ;
wire dll_update_req_rst_ctrl ;
wire dll_update_ack_rst_ctrl ;
wire ddrphy_rst_n ;
wire dll_update_ack ;
wire dll_freeze ;
wire dll_freeze_syn ;
wire [4:0] mc_wl ;
wire [4:0] mc_rl ;
wire [15:0] mr0_ddr3 ;
wire [15:0] mr1_ddr3 ;
wire [15:0] mr2_ddr3 ;
wire [15:0] mr3_ddr3 ;
wire calib_done ;
wire ddrphy_update ;
wire ddrphy_update_done ;
wire update_cal_req ;
wire update_done ;
wire [31:0] read_wait_cnt ;
wire [2*MEM_DQS_WIDTH-1:0] dqs_drift ;
wire update_gate_read_flag ;
wire dqs_gate_update1 ;
wire dqs_gate_update2 ;
wire gate_update1_done ;
wire gate_update2_done ;
wire dqs_gate_check_falling ;
wire ddrphy_rst_req ;
wire ddrphy_rst_ack ;
wire wrlvl_dqs_req ;
wire wrlvl_dqs_resp ;
wire wrlvl_error ;
wire wrlvl_ck_dly_start_rst ;
wire gatecal_start ;
wire gate_check_pass ;
wire gate_adj_done ;
wire gate_cal_error ;
wire gate_move_en ;
wire rddata_cal ;
wire rddata_check_pass ;
wire init_adj_rdel ;
wire reinit_adj_rdel ;
wire adj_rdel_done ;
wire rdel_calibration ;
wire rdel_calib_done ;
wire rdel_calib_error ;
wire rdel_move_en ;
wire rdel_move_done ;
wire gate_check_error ;
wire calib_rst ;
wire [MEM_BANK_WIDTH-1:0] calib_ba ;
wire [MEM_ADDR_WIDTH-1:0] calib_address ;
wire calib_cs_n ;
wire calib_ras_n ;
wire calib_cas_n ;
wire calib_we_n ;
wire calib_cke ;
wire calib_odt ;
wire [3:0] calib_wrdata_en ;
wire [8*MEM_DQ_WIDTH-1:0] calib_wrdata ;
wire [8*MEM_DM_WIDTH-1:0] calib_wrdata_mask ;
wire ddrphy_dqs_training_rstn ;
wire [3:0] read_cmd ;
wire read_valid ;
wire [MEM_DQS_WIDTH-1:0] ddrphy_read_valid ;
wire [8*MEM_DQ_WIDTH-1:0] o_read_data ;
wire [3:0] phy_wrdata_en ;
wire [8*MEM_DM_WIDTH-1:0] phy_wrdata_mask ;
wire [8*MEM_DQ_WIDTH-1:0] phy_wrdata ;
wire [3:0] phy_cke ;
wire [3:0] phy_cs_n ;
wire [3:0] phy_ras_n ;
wire [3:0] phy_cas_n ;
wire [3:0] phy_we_n ;
wire [4*MEM_ADDR_WIDTH-1:0] phy_addr ;
wire [4*MEM_BANK_WIDTH-1:0] phy_ba ;
wire [3:0] phy_odt ;
wire [3:0] phy_ck ;
wire phy_rst ;
GTP_DLL #(
.GRS_EN ("FALSE"), //"true"; "false"
.FAST_LOCK ("TRUE" ), //"true"; "false"
.DELAY_STEP_OFFSET (0 ) //-4, -3,-2, -1, 0, 1, 2, 3, 4
) I_GTP_DLL(
.CLKIN (ddrphy_ioclk[4] ),
.UPDATE_N (dll_update_n ),
.RST (ddrphy_dll_rst ),
.PWD (dll_freeze_syn ),
.DELAY_STEP (dll_step ),
.LOCK (dll_lock )
);
ipsxb_ddrphy_reset_ctrl_v1_4 ddrphy_reset_ctrl(
.ddrphy_clkin (ddrphy_clkin ),
.ddr_rstn (ddr_rstn ),
.ref_clk (ref_clk ),
.ioclk_gate_clk (ioclk_gate_clk ),
.dll_lock (dll_lock ),
.pll_lock (pll_lock ),
.dll_update_req_rst_ctrl (dll_update_req_rst_ctrl ),
.dll_update_ack_rst_ctrl (dll_update_ack_rst_ctrl ),
.training_error (dfi_error ),
.ddrphy_calib_done (calib_done ),
.ddrphy_dll_rst (ddrphy_dll_rst ), //dll reset
.ddrphy_rst_n (ddrphy_rst_n ),
.ddrphy_pll_rst (ddrphy_pll_rst ),
.ddrphy_dqs_rst (ddrphy_dqs_rst ),
.logic_rstn (logic_rstn ),
.ddrphy_ioclk_gate (ddrphy_ioclk_gate ),
.gate_check_error (gate_check_error ),
.dll_tran_update_en (dll_tran_update_en ),
.wrlvl_ck_dly_start_rst (wrlvl_ck_dly_start_rst )
);
ipsxb_ddrphy_gate_update_ctrl_v1_3 #(
.MEM_DQS_WIDTH (MEM_DQS_WIDTH )
) ddrphy_gate_update_ctrl (
.ddrphy_clkin (ddrphy_clkin ),
.ddrphy_rst_n (ddrphy_rst_n ),
.ddrphy_gate_update_en (ddrphy_gate_update_en ),
.calib_done (calib_done ),
.dqs_drift (dqs_drift ),
.update_done (update_done ),
.ddrphy_update_done (ddrphy_update_done ),
.update_req_start (ddrphy_update ),
.ddrphy_read_valid (ddrphy_read_valid ),
.update_gate_read_flag (update_gate_read_flag ),
.update_com_val_err_flag (update_com_val_err_flag )
);
ipsxb_ddrphy_dll_update_ctrl_v1_0 ddrphy_dll_update_ctrl(
.ddr_clkin (ref_clk ),
.ddr_rstn (logic_rstn ),
.dll_update_req_rst_ctrl (dll_update_req_rst_ctrl ),
.dll_update_ack_rst_ctrl (dll_update_ack_rst_ctrl ),
.dll_update_req_training (1'b0 ),
.dll_update_ack_training (dll_update_ack ),
.dll_tran_update_en (dll_tran_update_en ),
.dll_update_n (dll_update_n ),
.dll_freeze (dll_freeze )
);
ipsxb_rst_sync_v1_1 #(
.DATA_WIDTH (1 ),
.DFT_VALUE (1'b0 )
) u_dll_freeze_sync(
.clk (ddrphy_clkin ),
.rst_n (ddrphy_dll_rst_n ),
.sig_async (dll_freeze ),
.sig_synced (dll_freeze_syn )
);
ipsxb_ddrphy_calib_top_v1_3 #(
.T200US (T200US ),
.T500US (T500US ),
.TMRD (TMRD ),
.TMOD (TMOD ),
.TXPR (TXPR ),
.TZQINIT (TZQINIT ),
.TRFC (TRFC ),
.TRCD (TRCD ),
.MEM_ADDR_WIDTH (MEM_ADDR_WIDTH ),
.MEM_BANKADDR_WIDTH (MEM_BANK_WIDTH ),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.MEM_DM_WIDTH (MEM_DM_WIDTH ),
.MEM_DQS_WIDTH (MEM_DQS_WIDTH )
) ddrphy_calib_top(
.mc_wl (mc_wl ),
.mr0_ddr3 (mr0_ddr3 ),
.mr1_ddr3 (mr1_ddr3 ),
.mr2_ddr3 (mr2_ddr3 ),
.mr3_ddr3 (mr3_ddr3 ),
.ddrphy_clkin (ddrphy_clkin ),
.ddrphy_rst_n (ddrphy_rst_n ),
.calib_done (calib_done ),
.update_done (update_done ),
.ddrphy_update_done (ddrphy_update_done ),
.ddrphy_rst_req (ddrphy_rst_req ),
.ddrphy_rst_ack (ddrphy_rst_ack ),
.wrlvl_dqs_req (wrlvl_dqs_req ),
.wrlvl_dqs_resp (wrlvl_dqs_resp ),
.wrlvl_error (wrlvl_error ),
.gatecal_start (gatecal_start ),
.gate_check_pass (gate_check_pass ),
.gate_adj_done (gate_adj_done ),
.gate_cal_error (gate_cal_error ),
.gate_move_en (gate_move_en ),
.rddata_cal (rddata_cal ),
.rddata_check_pass (rddata_check_pass ),
.stop_with_error (1'b0 ),
.init_adj_rdel (init_adj_rdel ),
.reinit_adj_rdel (reinit_adj_rdel ),
.adj_rdel_done (adj_rdel_done ),
.rdel_calibration (rdel_calibration ),
.rdel_calib_done (rdel_calib_done ),
.rdel_calib_error (rdel_calib_error ),
.rdel_move_en (rdel_move_en ),
.rdel_move_done (rdel_move_done ),
.write_debug (1'b0 ),
.dqgt_debug (1'b0 ),
.rdel_rd_cnt (19'd64 ),
.dfi_error (dfi_error ),
.debug_calib_ctrl (debug_calib_ctrl ),
.read_wait_cnt (read_wait_cnt ),
.read_data (o_read_data ),
.read_valid (read_valid ),
.dqs_gate_update1 (dqs_gate_update1 ),
.dqs_gate_update2 (dqs_gate_update2 ),
.gate_update1_done (gate_update1_done ),
.gate_update2_done (gate_update2_done ),
.dqs_gate_check_falling (dqs_gate_check_falling),
.update_cal_req (update_cal_req ),
.update_gate_read_flag (update_gate_read_flag ),
.calib_ba (calib_ba ),
.calib_address (calib_address ),
.calib_cs_n (calib_cs_n ),
.calib_ras_n (calib_ras_n ),
.calib_cas_n (calib_cas_n ),
.calib_we_n (calib_we_n ),
.calib_cke (calib_cke ),
.calib_odt (calib_odt ),
.calib_rst (calib_rst ),
.calib_wrdata_en (calib_wrdata_en ),
.calib_wrdata (calib_wrdata ),
.calib_wrdata_mask (calib_wrdata_mask )
);
ipsxb_ddrphy_training_ctrl_v1_0 ddrphy_training_ctrl
(
.ddrphy_clkin (ddrphy_clkin ),
.ddrphy_rst_n (ddrphy_rst_n ),
.ddrphy_rst_req (ddrphy_rst_req ),
.ddrphy_rst_ack (ddrphy_rst_ack ),
.ddrphy_dqs_training_rstn (ddrphy_dqs_training_rstn )
);
ipsxb_ddrphy_slice_top_v1_4 #(
.MEM_ADDR_WIDTH (MEM_ADDR_WIDTH ),
.MEM_BANKADDR_WIDTH (MEM_BANK_WIDTH ),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.MEM_DQS_WIDTH (MEM_DQS_WIDTH ),
.MEM_DM_WIDTH (MEM_DM_WIDTH ),
.WL_EXTEND ("FALSE" ),
.DM_GROUP_EN (DM_GROUP_EN )
) ddrphy_slice_top(
.mc_rl (mc_rl ),
.init_read_clk_ctrl (init_read_clk_ctrl ),
.init_slip_step (init_slip_step ),
.init_samp_position (init_samp_position ),
.ddrphy_clkin (ddrphy_clkin ),
.ddrphy_rst_n (ddrphy_rst_n ),
.logic_rstn (logic_rstn ),
.ddrphy_ioclk (ddrphy_ioclk ),
.ddrphy_dqs_rst (ddrphy_dqs_rst ),
.ddrphy_dqs_training_rstn (ddrphy_dqs_training_rstn ),
.ddrphy_iodly_ctrl (3'b000 ),
.ddrphy_wl_ctrl (3'b001 ),
.wrlvl_dqs_req (wrlvl_dqs_req ),
.wrlvl_dqs_resp (wrlvl_dqs_resp ),
.wrlvl_error (wrlvl_error ),
.man_wrlvl_dqs (1'b0 ),
.wrlvl_ck_dly_start_rst (wrlvl_ck_dly_start_rst ),
.force_ck_dly_en (force_ck_dly_en ),
.force_ck_dly_set_bin (force_ck_dly_set_bin ),
.force_read_clk_ctrl (force_read_clk_ctrl ),
.gatecal_start (gatecal_start ),
.gate_check_pass (gate_check_pass ),
.gate_check_error (gate_check_error ),
.gate_adj_done (gate_adj_done ),
.gate_cal_error (gate_cal_error ),
.gate_move_en (gate_move_en ),
.dqs_gate_update1 (dqs_gate_update1 ),
.dqs_gate_update2 (dqs_gate_update2 ),
.gate_update1_done (gate_update1_done ),
.gate_update2_done (gate_update2_done ),
.dqs_gate_check_falling (dqs_gate_check_falling ),
.rddata_cal (rddata_cal ),
.rddata_check_pass (rddata_check_pass ),
.read_cmd (read_cmd ),
.ddrphy_read_valid (ddrphy_read_valid ),
.force_samp_position (1'b0 ),
.dll_step (dll_step ),
.dqs_drift (dqs_drift ),
.init_adj_rdel (init_adj_rdel ),
.reinit_adj_rdel (reinit_adj_rdel ),
.adj_rdel_done (adj_rdel_done ),
.rdel_calibration (rdel_calibration ),
.rdel_calib_done (rdel_calib_done ),
.rdel_calib_error (rdel_calib_error ),
.rdel_move_en (rdel_move_en ),
.rdel_move_done (rdel_move_done ),
.read_valid (read_valid ),
.o_read_data (o_read_data ),
.phy_wrdata_en (phy_wrdata_en ),
.phy_wrdata_mask (phy_wrdata_mask ),
.phy_wrdata (phy_wrdata ),
.phy_cke (phy_cke ),
.phy_cs_n (phy_cs_n ),
.phy_ras_n (phy_ras_n ),
.phy_cas_n (phy_cas_n ),
.phy_we_n (phy_we_n ),
.phy_addr (phy_addr ),
.phy_ba (phy_ba ),
.phy_odt (phy_odt ),
.phy_ck (phy_ck ),
.phy_rst (phy_rst ),
.mem_cs_n (mem_cs_n ),
.mem_rst_n (mem_rst_n ),
.mem_ck (mem_ck ),
.mem_ck_n (mem_ck_n ),
.mem_cke (mem_cke ),
.mem_ras_n (mem_ras_n ),
.mem_cas_n (mem_cas_n ),
.mem_we_n (mem_we_n ),
.mem_odt (mem_odt ),
.mem_a (mem_a ),
.mem_ba (mem_ba ),
.mem_dqs (mem_dqs ),
.mem_dqs_n (mem_dqs_n ),
.mem_dq (mem_dq ),
.mem_dm (mem_dm ),
.debug_data (debug_data ),
.debug_slice_state (debug_slice_state ),
.ck_dly_set_bin (ck_dly_set_bin )
);
ipsxb_ddrphy_dfi_v1_4 #(
.MEM_ADDR_WIDTH (MEM_ADDR_WIDTH ),
.MEM_BANKADDR_WIDTH (MEM_BANK_WIDTH ),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.MEM_DQS_WIDTH (MEM_DQS_WIDTH ),
.MEM_DM_WIDTH (MEM_DM_WIDTH )
) ddrphy_dfi(
.ddrphy_clkin (ddrphy_clkin ),
.ddrphy_rst_n (ddrphy_rst_n ),
.calib_done (calib_done ),
.calib_rst (calib_rst ),
.calib_ba (calib_ba ),
.calib_address (calib_address ),
.calib_cs_n (calib_cs_n ),
.calib_ras_n (calib_ras_n ),
.calib_cas_n (calib_cas_n ),
.calib_we_n (calib_we_n ),
.calib_cke (calib_cke ),
.calib_odt (calib_odt ),
.calib_wrdata_en (calib_wrdata_en ),
.calib_wrdata (calib_wrdata ),
.calib_wrdata_mask (calib_wrdata_mask ),
.read_valid (read_valid ),
.o_read_data (o_read_data ),
.ddrphy_update (ddrphy_update ),
.update_cal_req (update_cal_req ),
.update_done (update_done ),
.ddrphy_update_done (ddrphy_update_done ),
.read_wait_cnt (read_wait_cnt ),
.rd_fake_stop (rd_fake_stop ),
.ddrphy_gate_update_en (ddrphy_gate_update_en),
.dfi_address (dfi_address ),
.dfi_bank (dfi_bank ),
.dfi_cs_n (dfi_cs_n ),
.dfi_cas_n (dfi_cas_n ),
.dfi_ras_n (dfi_ras_n ),
.dfi_we_n (dfi_we_n ),
.dfi_cke (dfi_cke ),
.dfi_odt (dfi_odt ),
.dfi_wrdata_en (dfi_wrdata_en ),
.dfi_wrdata (dfi_wrdata ),
.dfi_wrdata_mask (dfi_wrdata_mask ),
.dfi_rddata (dfi_rddata ),
.dfi_rddata_valid (dfi_rddata_valid ),
.dfi_reset_n (dfi_reset_n ),
.dfi_phyupd_req (dfi_phyupd_req ),
.dfi_phyupd_ack (dfi_phyupd_ack ),
.dfi_init_complete (dfi_init_complete ),
.read_cmd (read_cmd ),
.phy_ck (phy_ck ),
.phy_rst (phy_rst ),
.phy_addr (phy_addr ),
.phy_ba (phy_ba ),
.phy_cs_n (phy_cs_n ),
.phy_ras_n (phy_ras_n ),
.phy_cas_n (phy_cas_n ),
.phy_we_n (phy_we_n ),
.phy_cke (phy_cke ),
.phy_odt (phy_odt ),
.phy_wrdata_en (phy_wrdata_en ),
.phy_wrdata (phy_wrdata ),
.phy_wrdata_mask (phy_wrdata_mask )
);
ipsxb_ddrphy_info_v1_0 #(
.MEM_ADDR_WIDTH (MEM_ADDR_WIDTH ),
.MEM_BANKADDR_WIDTH (MEM_BANK_WIDTH ),
.MR0_DDR3 (MR0_DDR3 ),
.MR1_DDR3 (MR1_DDR3 ),
.MR2_DDR3 (MR2_DDR3 ),
.MR3_DDR3 (MR3_DDR3 )
) ddrphy_info (
.ddrphy_clkin (ddrphy_clkin ),
.ddrphy_rst_n (ddrphy_rst_n ),
.calib_done (calib_done ),
.phy_addr (phy_addr ),
.phy_ba (phy_ba ),
.phy_cs_n (phy_cs_n ),
.phy_cas_n (phy_cas_n ),
.phy_ras_n (phy_ras_n ),
.phy_we_n (phy_we_n ),
.phy_cke (phy_cke ),
.mc_rl (mc_rl ),
.mc_wl (mc_wl ),
.mr0_ddr3 (mr0_ddr3 ),
.mr1_ddr3 (mr1_ddr3 ),
.mr2_ddr3 (mr2_ddr3 ),
.mr3_ddr3 (mr3_ddr3 )
);
endmodule |
module ddr_test #(
parameter DFI_CLK_PERIOD = 10000 ,
parameter MEM_ROW_WIDTH = 15 ,
parameter MEM_COLUMN_WIDTH = 10 ,
parameter MEM_BANK_WIDTH = 3 ,
parameter MEM_DQ_WIDTH = 32 ,
parameter MEM_DM_WIDTH = 4 ,
parameter MEM_DQS_WIDTH = 4 ,
parameter REGION_NUM = 3 ,
parameter CTRL_ADDR_WIDTH = MEM_ROW_WIDTH + MEM_COLUMN_WIDTH + MEM_BANK_WIDTH
)(
input ref_clk ,
input resetn ,
output ddr_init_done ,
output ddrphy_clkin ,
output pll_lock ,
input [CTRL_ADDR_WIDTH-1:0] axi_awaddr ,
input axi_awuser_ap ,
input [3:0] axi_awuser_id ,
input [3:0] axi_awlen ,
output axi_awready ,
input axi_awvalid ,
input [MEM_DQ_WIDTH*8-1:0] axi_wdata ,
input [MEM_DQ_WIDTH-1:0] axi_wstrb ,
output axi_wready ,
output [3:0] axi_wusero_id ,
output axi_wusero_last,
input [CTRL_ADDR_WIDTH-1:0] axi_araddr ,
input axi_aruser_ap ,
input [3:0] axi_aruser_id ,
input [3:0] axi_arlen ,
output axi_arready ,
input axi_arvalid ,
output[8*MEM_DQ_WIDTH-1:0] axi_rdata ,
output[3:0] axi_rid ,
output axi_rlast ,
output axi_rvalid ,
input apb_clk ,
input apb_rst_n ,
input apb_sel ,
input apb_enable ,
input [7:0] apb_addr ,
input apb_write ,
output apb_ready ,
input [15:0] apb_wdata ,
output[15:0] apb_rdata ,
output apb_int ,
output [34*MEM_DQS_WIDTH -1:0] debug_data ,
output [13*MEM_DQS_WIDTH -1:0] debug_slice_state ,
output [21:0] debug_calib_ctrl ,
output [7:0] ck_dly_set_bin ,
input force_ck_dly_en ,
input [7:0] force_ck_dly_set_bin ,
output [7:0] dll_step ,
output dll_lock ,
input [1:0] init_read_clk_ctrl ,
input [3:0] init_slip_step ,
input force_read_clk_ctrl ,
input ddrphy_gate_update_en,
output [MEM_DQS_WIDTH-1:0] update_com_val_err_flag,
input rd_fake_stop ,
output mem_rst_n ,
output mem_ck ,
output mem_ck_n ,
output mem_cke ,
output mem_cs_n ,
output mem_ras_n ,
output mem_cas_n ,
output mem_we_n ,
output mem_odt ,
output [MEM_ROW_WIDTH-1:0] mem_a ,
output [MEM_BANK_WIDTH-1:0] mem_ba ,
inout [MEM_DQS_WIDTH-1:0] mem_dqs ,
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n ,
inout [MEM_DQ_WIDTH-1:0] mem_dq ,
output [MEM_DM_WIDTH-1:0] mem_dm
);
`ifdef SIMULATION
localparam T200US = (200*1000*1000 / DFI_CLK_PERIOD) / 100;
`else
localparam T200US = (200*1000*1000 / DFI_CLK_PERIOD);
`endif
`ifdef SIMULATION
localparam T500US = (500*1000*1000 / DFI_CLK_PERIOD) / 100;
`else
localparam T500US = (500*1000*1000 / DFI_CLK_PERIOD);
`endif
//MR0_DDR3
localparam [0:0] DDR3_PPD = 1'b1;
localparam [2:0] DDR3_WR = 3'd2;
localparam [0:0] DDR3_DLL = 1'b1;
localparam [0:0] DDR3_TM = 1'b0;
localparam [0:0] DDR3_RBT = 1'b0;
localparam [3:0] DDR3_CL = 4'd4;
localparam [1:0] DDR3_BL = 2'b00;
localparam [15:0] MR0_DDR3 = {3'b000, DDR3_PPD, DDR3_WR, DDR3_DLL, DDR3_TM, DDR3_CL[3:1], DDR3_RBT, DDR3_CL[0], DDR3_BL};
//MR1_DDR3
localparam [0:0] DDR3_QOFF = 1'b0;
localparam [0:0] DDR3_TDQS = 1'b0;
localparam [2:0] DDR3_RTT_NOM = 3'b001;
localparam [0:0] DDR3_LEVEL = 1'b0;
localparam [1:0] DDR3_DIC = 2'b00;
localparam [1:0] DDR3_AL = 2'd2;
localparam [0:0] DDR3_DLL_EN = 1'b0;
localparam [15:0] MR1_DDR3 = {1'b0, DDR3_QOFF, DDR3_TDQS, 1'b0, DDR3_RTT_NOM[2], 1'b0, DDR3_LEVEL, DDR3_RTT_NOM[1], DDR3_DIC[1], DDR3_AL, DDR3_RTT_NOM[0], DDR3_DIC[0], DDR3_DLL_EN};
//MR2_DDR3
localparam [1:0] DDR3_RTT_WR = 2'b00;
localparam [0:0] DDR3_SRT = 1'b0;
localparam [0:0] DDR3_ASR = 1'b0;
localparam [2:0] DDR3_CWL = 5 - 5;
localparam [2:0] DDR3_PASR = 3'b000;
localparam [15:0] MR2_DDR3 = {5'b00000, DDR3_RTT_WR, 1'b0, DDR3_SRT, DDR3_ASR, DDR3_CWL, DDR3_PASR};
//MR3_DDR3
localparam [0:0] DDR3_MPR = 1'b0;
localparam [1:0] DDR3_MPR_LOC = 2'b00;
localparam [15:0] MR3_DDR3 = {13'b0, DDR3_MPR, DDR3_MPR_LOC};
//****************************************************************************
//The following parameters are mode register settings
//*****************************************************************************
localparam INIT_MC_AL = 2'b10 ;
localparam INIT_MC_CL = 6 ;
localparam INIT_MC_CWL = 5 ;
localparam INIT_MC_WR = 6 ;
//******************************************************************************
//The following parameters are Memory Timing
//******************************************************************************
localparam MEM_TYPE = "DDR3" ;
localparam [7:0] PHY_TMRD = 4/4 ;
localparam [7:0] PHY_TRP = 2 ;
localparam [7:0] PHY_TRCD = 2 ;
localparam DDRC_TXSDLL = 512 ;
localparam DDRC_TXP = 3 ;
localparam DDRC_TFAW = 18 ;
localparam DDRC_TRAS = 15 ;
localparam DDRC_TRCD = 6 ;
localparam DDRC_TRFC = 120 ;
localparam DDRC_TREFI = 3120 ;
localparam DDRC_TRC = 20 ;
localparam DDRC_TRP = 6 ;
localparam DDRC_TRRD = 4 ;
localparam DDRC_TRTP = 4 ;
localparam DDRC_TWR = 6 ;
localparam DDRC_TWTR = 4 ;
localparam [7:0] PHY_TMOD = 12/4 ;
localparam [9:0] PHY_TZQINIT = 10'd128 ;
localparam [7:0] PHY_TRFC = 30 ;
localparam [7:0] PHY_TXPR = 31 ;
localparam real CLKIN_FREQ = 50.0 ;
localparam PLL_IDIV = 1 ;
localparam PLL_FDIV = 16 ;
localparam PLL_ODIV0 = 2 ;
localparam PLL_ODIV1 = 2*4 ;
localparam PLL_DUTY0 = 2 ;
localparam PLL_DUTY1 = 2*4 ;
wire dfi_phyupd_req ;
wire dfi_phyupd_ack ;
wire dfi_init_complete;
wire [4*MEM_ROW_WIDTH-1:0] dfi_address ;
wire [4*MEM_BANK_WIDTH-1:0] dfi_bank ;
wire [4-1:0] dfi_cs_n ;
wire [4-1:0] dfi_ras_n ;
wire [4-1:0] dfi_cas_n ;
wire [4-1:0] dfi_we_n ;
wire [4-1:0] dfi_cke ;
wire [4-1:0] dfi_odt ;
wire [2*4*MEM_DQ_WIDTH-1:0] dfi_wrdata ;
wire [4-1:0] dfi_wrdata_en ;
wire [2*4*MEM_DQ_WIDTH/8-1:0] dfi_wrdata_mask ;
wire [2*4*MEM_DQ_WIDTH-1:0] dfi_rddata ;
wire dfi_rddata_valid;
wire ddrphy_ioclk_gate;
wire ddrphy_dqs_rst ;
wire [1:0] ddrphy_ioclk_source;
wire [REGION_NUM-1:0] ioclk;
wire [8:0] ddrphy_ioclk;
wire pll_clkin;
wire [1:0] pll_ioclk_lock;
wire ddr_rstn;
wire ddrphy_pll_rst;
wire ioclk_gate_clk;
wire ioclk_gate_clk_pll;
ipsxb_rst_sync_v1_1 u_ddrp_rstn_sync(
.clk (pll_clkin ),
.rst_n (resetn ),
.sig_async (1'b1),
.sig_synced (ddr_rstn )
);
GTP_CLKBUFG u_clkbufg
(
.CLKOUT(pll_clkin ),
.CLKIN (ref_clk )
);
//pll_0
ipsxb_ddrphy_pll_v1_0 #(
.CLKIN_FREQ (CLKIN_FREQ ),
.STATIC_RATIOI (PLL_IDIV ),
.STATIC_RATIOF (PLL_FDIV ),
.STATIC_RATIO0 (PLL_ODIV0 ),
.STATIC_DUTY0 (PLL_DUTY0 ),
.STATIC_RATIO1 (PLL_ODIV1 ),
.STATIC_DUTY1 (PLL_DUTY1 )
) u_ipsxb_ddrphy_pll_0 (
.pll_rst (ddrphy_pll_rst ),
.pll_lock (pll_ioclk_lock[0] ),
.clkout0_gate (ddrphy_ioclk_gate ),
.clkout0 (ddrphy_ioclk_source[0] ), //io clock
.clkout1 (ioclk_gate_clk_pll ),
.clkin1 (pll_clkin )
);
//pll_1
ipsxb_ddrphy_pll_v1_0 #(
.CLKIN_FREQ (CLKIN_FREQ ),
.STATIC_RATIOI (PLL_IDIV ),
.STATIC_RATIOF (PLL_FDIV ),
.STATIC_RATIO0 (PLL_ODIV0 ),
.STATIC_DUTY0 (PLL_DUTY0 ),
.STATIC_RATIO1 (PLL_ODIV1 ),
.STATIC_DUTY1 (PLL_DUTY1 )
) u_ipsxb_ddrphy_pll_1 (
.pll_rst (ddrphy_pll_rst ),
.pll_lock (pll_ioclk_lock[1] ),
.clkout0_gate (ddrphy_ioclk_gate ),
.clkout0 (ddrphy_ioclk_source[1] ), //io clock
.clkin1 (pll_clkin )
);
GTP_IOCLKBUF #(
.GATE_EN ("TRUE" )
) I_GTP_IOCLKBUF_0 (
.CLKOUT (ioclk[0] ),
.CLKIN (ddrphy_ioclk_source[0]),
.DI (1'b1 )
);
GTP_IOCLKBUF #(
.GATE_EN("TRUE" )
) I_GTP_IOCLKBUF_1 (
.CLKOUT(ioclk[1] ),
.CLKIN(ddrphy_ioclk_source[0]),
.DI(1'b1 )
);
GTP_IOCLKBUF #(
.GATE_EN ("TRUE" )
) I_GTP_IOCLKBUF_2 (
.CLKOUT (ioclk[2] ),
.CLKIN (ddrphy_ioclk_source[1]),
.DI (1'b1 )
);
GTP_IOCLKDIV #(
.DIV_FACTOR ("4"), //"2"; "3.5"; "4"; "5";
.GRS_EN ("FALSE") //"true"; "false"
)I_GTP_CLKDIV(
.CLKIN (ddrphy_ioclk_source[0]),
.RST_N (~ddrphy_dqs_rst),
.CLKDIVOUT (ddrphy_clkin)
);
assign ddrphy_ioclk = {ioclk[2],ioclk[2],ioclk[2],ioclk[1],ioclk[1],ioclk[1],ioclk[0],ioclk[0],ioclk[0]};
GTP_CLKBUFG u_clkbufg_gate
(
.CLKOUT(ioclk_gate_clk ),
.CLKIN (ioclk_gate_clk_pll )
);
assign pll_lock = &pll_ioclk_lock;
ipsxb_mcdq_wrapper_v1_2a #(
.MEM_ROW_ADDR_WIDTH (MEM_ROW_WIDTH ),
.MEM_COL_ADDR_WIDTH (MEM_COLUMN_WIDTH ),
.MEM_BA_ADDR_WIDTH (MEM_BANK_WIDTH ),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH ),
.ADDR_MAPPING_SEL (1 ), //0: ROW + BANK + COLUMN 1:BANK + ROW +COLUMN
.MR0_DDR3 (MR0_DDR3 ),
.MR1_DDR3 (MR1_DDR3 ),
.MR2_DDR3 (MR2_DDR3 ),
.MR3_DDR3 (MR3_DDR3 ),
.TXSDLL (DDRC_TXSDLL ),
.TXP (DDRC_TXP ),
.TFAW (DDRC_TFAW ),
.TRAS (DDRC_TRAS ),
.TRCD (DDRC_TRCD ),
.TREFI (DDRC_TREFI ),
.TRFC (DDRC_TRFC ),
.TRC (DDRC_TRC ),
.TRP (DDRC_TRP ),
.TRRD (DDRC_TRRD ),
.TRTP (DDRC_TRTP ),
.TWR (DDRC_TWR ),
.TWTR (DDRC_TWTR )
)u_ipsxb_ddrc_top(
.clk (ddrphy_clkin ),
.rst_n (ddr_rstn ),
.phy_init_done (dfi_init_complete ),
.ddr_init_done (ddr_init_done ),
.axi_awaddr (axi_awaddr ),
.axi_awuser_ap (axi_awuser_ap ),
.axi_awuser_id (axi_awuser_id ),
.axi_awlen (axi_awlen ),
.axi_awready (axi_awready ),
.axi_awvalid (axi_awvalid ),
.axi_wdata (axi_wdata ),
.axi_wstrb (axi_wstrb ),
.axi_wready (axi_wready ),
.axi_wusero_id (axi_wusero_id ),
.axi_wusero_last (axi_wusero_last ),
.axi_araddr (axi_araddr ),
.axi_aruser_ap (axi_aruser_ap ),
.axi_aruser_id (axi_aruser_id ),
.axi_arlen (axi_arlen ),
.axi_arready (axi_arready ),
.axi_arvalid (axi_arvalid ),
.axi_rdata (axi_rdata ),
.axi_rid (axi_rid ),
.axi_rlast (axi_rlast ),
.axi_rvalid (axi_rvalid ),
.apb_clk (apb_clk ),
.apb_rst_n (apb_rst_n ),
.apb_sel (apb_sel ),
.apb_enable (apb_enable ),
.apb_addr (apb_addr ),
.apb_write (apb_write ),
.apb_ready (apb_ready ),
.apb_wdata (apb_wdata ),
.apb_rdata (apb_rdata ),
.dfi_phyupd_req (dfi_phyupd_req ),
.dfi_phyupd_ack (dfi_phyupd_ack ),
.dfi_address (dfi_address ),
.dfi_bank (dfi_bank ),
.dfi_cs_n (dfi_cs_n ),
.dfi_ras_n (dfi_ras_n ),
.dfi_cas_n (dfi_cas_n ),
.dfi_we_n (dfi_we_n ),
.dfi_cke (dfi_cke ),
.dfi_odt (dfi_odt ),
.dfi_wrdata (dfi_wrdata ),
.dfi_wrdata_en (dfi_wrdata_en ),
.dfi_wrdata_mask (dfi_wrdata_mask ),
.dfi_rddata (dfi_rddata ),
.dfi_rddata_valid (dfi_rddata_valid )
);
ddr_test_ddrphy_top #(
.T200US (T200US ),
.T500US (T500US ),
.MEM_TYPE (MEM_TYPE ),
.TMRD (PHY_TMRD ),
.TMOD (PHY_TMOD ),
.TZQINIT (PHY_TZQINIT ),
.TXPR (PHY_TXPR ),
.TRP (PHY_TRP ),
.TRFC (PHY_TRFC ),
.TRCD (PHY_TRCD ),
.MEM_ADDR_WIDTH (MEM_ROW_WIDTH ),
.MEM_BANK_WIDTH (MEM_BANK_WIDTH ),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.MEM_DM_WIDTH (MEM_DM_WIDTH ),
.MEM_DQS_WIDTH (MEM_DQS_WIDTH )
)u_ddrphy_top(
.ref_clk (pll_clkin ),
.ddr_rstn (ddr_rstn ),
.pll_lock (pll_lock ),
.ddrphy_ioclk_gate (ddrphy_ioclk_gate ),
.ddrphy_pll_rst (ddrphy_pll_rst ),
.ioclk_gate_clk (ioclk_gate_clk ),
.ddrphy_dqs_rst (ddrphy_dqs_rst ),
.ddrphy_clkin (ddrphy_clkin ),
.ddrphy_ioclk (ddrphy_ioclk ),
.dll_step (dll_step ),
.dll_lock (dll_lock ),
.ddrphy_gate_update_en (ddrphy_gate_update_en ),
.update_com_val_err_flag (update_com_val_err_flag ),
.init_read_clk_ctrl (init_read_clk_ctrl ),
.init_slip_step (init_slip_step ),
.force_read_clk_ctrl (force_read_clk_ctrl ),
.init_samp_position (8'h0 ),
.dfi_address (dfi_address ),
.dfi_bank (dfi_bank ),
.dfi_cs_n (dfi_cs_n ),
.dfi_cas_n (dfi_cas_n ),
.dfi_ras_n (dfi_ras_n ),
.dfi_we_n (dfi_we_n ),
.dfi_cke (dfi_cke ),
.dfi_odt (dfi_odt ),
.dfi_wrdata_en (dfi_wrdata_en ),
.dfi_wrdata (dfi_wrdata ),
.dfi_wrdata_mask (dfi_wrdata_mask ),
.dfi_rddata (dfi_rddata ),
.dfi_rddata_valid (dfi_rddata_valid ),
.dfi_reset_n (1'b1 ),
.dfi_phyupd_req (dfi_phyupd_req ),
.dfi_phyupd_ack (dfi_phyupd_ack ),
.dfi_init_complete (dfi_init_complete ),
.rd_fake_stop (rd_fake_stop ),
.debug_calib_ctrl (debug_calib_ctrl ),
.debug_data (debug_data ),
.debug_slice_state (debug_slice_state ),
.ck_dly_set_bin (ck_dly_set_bin ),
.force_ck_dly_set_bin (force_ck_dly_set_bin ),
.force_ck_dly_en (force_ck_dly_en ),
.mem_rst_n (mem_rst_n ),
.mem_ck (mem_ck ),
.mem_ck_n (mem_ck_n ),
.mem_cke (mem_cke ),
.mem_cs_n (mem_cs_n ),
.mem_ras_n (mem_ras_n ),
.mem_cas_n (mem_cas_n ),
.mem_we_n (mem_we_n ),
.mem_odt (mem_odt ),
.mem_a (mem_a ),
.mem_ba (mem_ba ),
.mem_dqs (mem_dqs ),
.mem_dqs_n (mem_dqs_n ),
.mem_dq (mem_dq ),
.mem_dm (mem_dm )
);
endmodule |
module ipsxb_rst_sync_v1_1 #
(
parameter DATA_WIDTH = 1'd1, //
parameter DFT_VALUE = {DATA_WIDTH{1'b0}}
)
(
input wire clk,
input wire rst_n,
input wire [DATA_WIDTH-1:0] sig_async,
output wire [DATA_WIDTH-1:0] sig_synced
);
reg [DATA_WIDTH-1:0] sig_async_r1;
reg [DATA_WIDTH-1:0] sig_async_r2;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
sig_async_r1 <= DFT_VALUE;
sig_async_r2 <= DFT_VALUE;
end
else
begin
sig_async_r1 <= sig_async;
sig_async_r2 <= sig_async_r1;
end
end
assign sig_synced = sig_async_r2;
endmodule |
module test_main_ctrl_v1_0 #(
parameter CTRL_ADDR_WIDTH = 28,
parameter MEM_DQ_WIDTH = 16,
parameter MEM_SPACE_AW = 18
)(
input clk,
input rst_n,
input [1:0] wr_mode,
input [1:0] data_mode,
input len_random_en,
input [3:0] fix_axi_len,
input bist_stop ,
output wire pattern_en ,
output wire random_data_en,
output wire read_repeat_en,
output wire stress_test ,
output wire write_to_read ,
output [CTRL_ADDR_WIDTH-1:0] random_rw_addr,
output [3:0] random_axi_id,
output [3:0] random_axi_len,
output random_axi_ap,
input ddrc_init_done,
output reg init_start,
input init_done,
output reg write_en,
input write_done_p,
output reg read_en,
input read_done_p,
output reg bist_run_led,
output reg [3:0] test_main_state
);
wire [127:0] prbs_dout;
wire random_write_en;
reg [1:0] wr_mode_d0;
reg [1:0] wr_mode_d1;
reg [1:0] data_mode_d0;
reg [1:0] data_mode_d1;
//wire write_to_read;
reg [17:0] run_led_cnt;
reg [3:0] fix_axi_len_d0;
reg [3:0] fix_axi_len_d1;
reg len_random_en_d0;
reg len_random_en_d1;
localparam E_IDLE = 4'd0;
localparam E_INIT = 4'd1;
localparam E_WR = 4'd2;
localparam E_RD = 4'd3;
localparam E_END = 4'd4;
reg ddrc_init_done_d0;
reg ddrc_init_done_d1;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
ddrc_init_done_d0 <= 0;
ddrc_init_done_d1 <= 0;
end
else begin
ddrc_init_done_d0 <= ddrc_init_done;
ddrc_init_done_d1 <= ddrc_init_done_d0;
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)begin
wr_mode_d0 <= 2'b00;
wr_mode_d1 <= 2'b00;
end
else begin
wr_mode_d0 <= wr_mode;
wr_mode_d1 <= wr_mode_d0;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)begin
data_mode_d0 <= 2'b00;
data_mode_d1 <= 2'b00;
end
else begin
data_mode_d0 <= data_mode;
data_mode_d1 <= data_mode_d0;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)begin
len_random_en_d0 <= 0;
len_random_en_d1 <= 0;
end
else begin
len_random_en_d0 <= len_random_en;
len_random_en_d1 <= len_random_en_d0;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)begin
fix_axi_len_d0 <= 4'b0;
fix_axi_len_d1 <= 4'b0;
end
else begin
fix_axi_len_d0 <= fix_axi_len;
fix_axi_len_d1 <= fix_axi_len_d0;
end
end
assign read_repeat_en = wr_mode_d1[0];
assign write_to_read = wr_mode_d1[1];
assign pattern_en = data_mode_d1 == 2'b11;
assign random_data_en = data_mode_d1 == 2'b00;
assign stress_test = data_mode_d1 == 2'b10;
//reg [3:0] test_main_state;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
test_main_state <= E_IDLE;
write_en <= 1'b0;
read_en <= 1'b0;
init_start <= 1'b0;
end
else begin
case (test_main_state)
E_IDLE: begin
if (ddrc_init_done_d1)
begin
if(write_to_read)
test_main_state <= E_WR;
else
test_main_state <= E_INIT;
end
else
test_main_state <= E_IDLE;
end
E_INIT : begin
init_start <= 1'b1;
if(init_done) begin
test_main_state <= E_WR;
init_start <= 1'b0;
end
end
E_WR: begin
if (write_done_p) begin
write_en <= 1'b0;
if(write_to_read)
test_main_state <= E_RD;
else
test_main_state <= E_END;
end
else if(bist_stop)
write_en <= 1'b0;
else
write_en <= 1'b1;
end
E_RD: begin
if (read_done_p) begin
read_en <= 1'b0;
if(write_to_read)
test_main_state <= E_WR;
else
test_main_state <= E_END;
end
else if(bist_stop)
read_en <= 1'b0;
else
read_en <= 1'b1;
end
E_END: begin
if (random_write_en)
test_main_state <= E_WR;
else
test_main_state <= E_RD;
end
default: begin
test_main_state <= E_IDLE;
end
endcase
end
assign prbs_clk_en = (~write_to_read & write_done_p) | read_done_p;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
run_led_cnt <= 18'd0;
else if(read_done_p|write_done_p)
run_led_cnt <= run_led_cnt + 18'd1;
else;
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
bist_run_led <= 1'b0;
else if((&run_led_cnt)&(read_done_p|write_done_p))
bist_run_led <= ~bist_run_led;
end
prbs31_128bit_v1_0 #(
.PRBS_INIT (128'h1234_5678_9abc_def0_8686_2016_0707_336a),
.PRBS_GEN_EN (1'b1)
)
I_prbs31_128bit(
.clk (clk),
.rstn (rst_n),
.clk_en (prbs_clk_en),
.cnt_mode (1'b0 ),
.din (128'd0),
.dout (prbs_dout),
.insert_er (1'b0),
.error ()
);
wire [CTRL_ADDR_WIDTH-1:0] random_rw_addr_mask = {CTRL_ADDR_WIDTH{1'b0}} + {(MEM_SPACE_AW-1){1'b1}};
assign random_rw_addr = {prbs_dout[96+CTRL_ADDR_WIDTH-4:96], 3'd0} & random_rw_addr_mask;
assign random_axi_id = prbs_dout[39:36];
assign random_axi_len = (len_random_en_d1==1) ? prbs_dout[35:32] : fix_axi_len_d1;
assign random_write_en = prbs_dout[0];
assign random_axi_ap = 0;
endmodule |
module prbs31_128bit_v1_0 #(
parameter PRBS_INIT = 128'b0,
parameter PRBS_GEN_EN = 1'b0
)(
input clk,
input rstn,
input clk_en,
input cnt_mode,
input [127:0] din,
output [127:0] dout,
input insert_er,
output reg error
);
wire [128:1] Y;
wire [128:1] X;
wire [128:1] y_comb;
reg [128:1] latch_y_all;
reg [128:1] latch_y;
reg [2:0] insert_er_d;
assign Y[128] = X[31] ^ X[28] ^ 1 ;
assign Y[127] = X[30] ^ X[27] ^ 1 ;
assign Y[126] = X[29] ^ X[26] ^ 1 ;
assign Y[125] = X[28] ^ X[25] ^ 1 ;
assign Y[124] = X[27] ^ X[24] ^ 1 ;
assign Y[123] = X[26] ^ X[23] ^ 1 ;
assign Y[122] = X[25] ^ X[22] ^ 1 ;
assign Y[121] = X[24] ^ X[21] ^ 1 ;
assign Y[120] = X[23] ^ X[20] ^ 1 ;
assign Y[119] = X[22] ^ X[19] ^ 1 ;
assign Y[118] = X[21] ^ X[18] ^ 1 ;
assign Y[117] = X[20] ^ X[17] ^ 1 ;
assign Y[116] = X[19] ^ X[16] ^ 1 ;
assign Y[115] = X[18] ^ X[15] ^ 1 ;
assign Y[114] = X[17] ^ X[14] ^ 1 ;
assign Y[113] = X[16] ^ X[13] ^ 1 ;
assign Y[112] = X[15] ^ X[12] ^ 1 ;
assign Y[111] = X[14] ^ X[11] ^ 1 ;
assign Y[110] = X[13] ^ X[10] ^ 1 ;
assign Y[109] = X[12] ^ X[9] ^ 1 ;
assign Y[108] = X[11] ^ X[8] ^ 1 ;
assign Y[107] = X[10] ^ X[7] ^ 1 ;
assign Y[106] = X[9] ^ X[6] ^ 1 ;
assign Y[105] = X[8] ^ X[5] ^ 1 ;
assign Y[104] = X[7] ^ X[4] ^ 1 ;
assign Y[103] = X[6] ^ X[3] ^ 1 ;
assign Y[102] = X[5] ^ X[2] ^ 1 ;
assign Y[101] = X[4] ^ X[1] ^ 1 ;
assign Y[100] = X[31] ^ X[28] ^ X[3] ^ 0 ;
assign Y[99] = X[30] ^ X[27] ^ X[2] ^ 0 ;
assign Y[98] = X[29] ^ X[26] ^ X[1] ^ 0 ;
assign Y[97] = X[31] ^ X[25] ^ 1 ;
assign Y[96] = X[30] ^ X[24] ^ 1 ;
assign Y[95] = X[29] ^ X[23] ^ 1 ;
assign Y[94] = X[28] ^ X[22] ^ 1 ;
assign Y[93] = X[27] ^ X[21] ^ 1 ;
assign Y[92] = X[26] ^ X[20] ^ 1 ;
assign Y[91] = X[25] ^ X[19] ^ 1 ;
assign Y[90] = X[24] ^ X[18] ^ 1 ;
assign Y[89] = X[23] ^ X[17] ^ 1 ;
assign Y[88] = X[22] ^ X[16] ^ 1 ;
assign Y[87] = X[21] ^ X[15] ^ 1 ;
assign Y[86] = X[20] ^ X[14] ^ 1 ;
assign Y[85] = X[19] ^ X[13] ^ 1 ;
assign Y[84] = X[18] ^ X[12] ^ 1 ;
assign Y[83] = X[17] ^ X[11] ^ 1 ;
assign Y[82] = X[16] ^ X[10] ^ 1 ;
assign Y[81] = X[15] ^ X[9] ^ 1 ;
assign Y[80] = X[14] ^ X[8] ^ 1 ;
assign Y[79] = X[13] ^ X[7] ^ 1 ;
assign Y[78] = X[12] ^ X[6] ^ 1 ;
assign Y[77] = X[11] ^ X[5] ^ 1 ;
assign Y[76] = X[10] ^ X[4] ^ 1 ;
assign Y[75] = X[9] ^ X[3] ^ 1 ;
assign Y[74] = X[8] ^ X[2] ^ 1 ;
assign Y[73] = X[7] ^ X[1] ^ 1 ;
assign Y[72] = X[31] ^ X[28] ^ X[6] ^ 0 ;
assign Y[71] = X[30] ^ X[27] ^ X[5] ^ 0 ;
assign Y[70] = X[29] ^ X[26] ^ X[4] ^ 0 ;
assign Y[69] = X[28] ^ X[25] ^ X[3] ^ 0 ;
assign Y[68] = X[27] ^ X[24] ^ X[2] ^ 0 ;
assign Y[67] = X[26] ^ X[23] ^ X[1] ^ 0 ;
assign Y[66] = X[31] ^ X[28] ^ X[25] ^ X[22] ^ 1 ;
assign Y[65] = X[30] ^ X[27] ^ X[24] ^ X[21] ^ 1 ;
assign Y[64] = X[29] ^ X[26] ^ X[23] ^ X[20] ^ 1 ;
assign Y[63] = X[28] ^ X[25] ^ X[22] ^ X[19] ^ 1 ;
assign Y[62] = X[27] ^ X[24] ^ X[21] ^ X[18] ^ 1 ;
assign Y[61] = X[26] ^ X[23] ^ X[20] ^ X[17] ^ 1 ;
assign Y[60] = X[25] ^ X[22] ^ X[19] ^ X[16] ^ 1 ;
assign Y[59] = X[24] ^ X[21] ^ X[18] ^ X[15] ^ 1 ;
assign Y[58] = X[23] ^ X[20] ^ X[17] ^ X[14] ^ 1 ;
assign Y[57] = X[22] ^ X[19] ^ X[16] ^ X[13] ^ 1 ;
assign Y[56] = X[21] ^ X[18] ^ X[15] ^ X[12] ^ 1 ;
assign Y[55] = X[20] ^ X[17] ^ X[14] ^ X[11] ^ 1 ;
assign Y[54] = X[19] ^ X[16] ^ X[13] ^ X[10] ^ 1 ;
assign Y[53] = X[18] ^ X[15] ^ X[12] ^ X[9] ^ 1 ;
assign Y[52] = X[17] ^ X[14] ^ X[11] ^ X[8] ^ 1 ;
assign Y[51] = X[16] ^ X[13] ^ X[10] ^ X[7] ^ 1 ;
assign Y[50] = X[15] ^ X[12] ^ X[9] ^ X[6] ^ 1 ;
assign Y[49] = X[14] ^ X[11] ^ X[8] ^ X[5] ^ 1 ;
assign Y[48] = X[13] ^ X[10] ^ X[7] ^ X[4] ^ 1 ;
assign Y[47] = X[12] ^ X[9] ^ X[6] ^ X[3] ^ 1 ;
assign Y[46] = X[11] ^ X[8] ^ X[5] ^ X[2] ^ 1 ;
assign Y[45] = X[10] ^ X[7] ^ X[4] ^ X[1] ^ 1 ;
assign Y[44] = X[31] ^ X[28] ^ X[9] ^ X[6] ^ X[3] ^ 0 ;
assign Y[43] = X[30] ^ X[27] ^ X[8] ^ X[5] ^ X[2] ^ 0 ;
assign Y[42] = X[29] ^ X[26] ^ X[7] ^ X[4] ^ X[1] ^ 0 ;
assign Y[41] = X[31] ^ X[25] ^ X[6] ^ X[3] ^ 1 ;
assign Y[40] = X[30] ^ X[24] ^ X[5] ^ X[2] ^ 1 ;
assign Y[39] = X[29] ^ X[23] ^ X[4] ^ X[1] ^ 1 ;
assign Y[38] = X[31] ^ X[22] ^ X[3] ^ 0 ;
assign Y[37] = X[30] ^ X[21] ^ X[2] ^ 0 ;
assign Y[36] = X[29] ^ X[20] ^ X[1] ^ 0 ;
assign Y[35] = X[31] ^ X[19] ^ 1 ;
assign Y[34] = X[30] ^ X[18] ^ 1 ;
assign Y[33] = X[29] ^ X[17] ^ 1 ;
assign Y[32] = X[28] ^ X[16] ^ 1 ;
assign Y[31] = X[27] ^ X[15] ^ 1 ;
assign Y[30] = X[26] ^ X[14] ^ 1 ;
assign Y[29] = X[25] ^ X[13] ^ 1 ;
assign Y[28] = X[24] ^ X[12] ^ 1 ;
assign Y[27] = X[23] ^ X[11] ^ 1 ;
assign Y[26] = X[22] ^ X[10] ^ 1 ;
assign Y[25] = X[21] ^ X[9] ^ 1 ;
assign Y[24] = X[20] ^ X[8] ^ 1 ;
assign Y[23] = X[19] ^ X[7] ^ 1 ;
assign Y[22] = X[18] ^ X[6] ^ 1 ;
assign Y[21] = X[17] ^ X[5] ^ 1 ;
assign Y[20] = X[16] ^ X[4] ^ 1 ;
assign Y[19] = X[15] ^ X[3] ^ 1 ;
assign Y[18] = X[14] ^ X[2] ^ 1 ;
assign Y[17] = X[13] ^ X[1] ^ 1 ;
assign Y[16] = X[31] ^ X[28] ^ X[12] ^ 0 ;
assign Y[15] = X[30] ^ X[27] ^ X[11] ^ 0 ;
assign Y[14] = X[29] ^ X[26] ^ X[10] ^ 0 ;
assign Y[13] = X[28] ^ X[25] ^ X[9] ^ 0 ;
assign Y[12] = X[27] ^ X[24] ^ X[8] ^ 0 ;
assign Y[11] = X[26] ^ X[23] ^ X[7] ^ 0 ;
assign Y[10] = X[25] ^ X[22] ^ X[6] ^ 0 ;
assign Y[9] = X[24] ^ X[21] ^ X[5] ^ 0 ;
assign Y[8] = X[23] ^ X[20] ^ X[4] ^ 0 ;
assign Y[7] = X[22] ^ X[19] ^ X[3] ^ 0 ;
assign Y[6] = X[21] ^ X[18] ^ X[2] ^ 0 ;
assign Y[5] = X[20] ^ X[17] ^ X[1] ^ 0 ;
assign Y[4] = X[31] ^ X[28] ^ X[19] ^ X[16] ^ 1 ;
assign Y[3] = X[30] ^ X[27] ^ X[18] ^ X[15] ^ 1 ;
assign Y[2] = X[29] ^ X[26] ^ X[17] ^ X[14] ^ 1 ;
assign Y[1] = X[28] ^ X[25] ^ X[16] ^ X[13] ^ 1 ;
assign y_comb[128:1] = cnt_mode ? (latch_y + 128'b1) : (PRBS_GEN_EN ? Y[128:1] : din[127:0]);
always @(posedge clk or negedge rstn)
if (!rstn) begin
latch_y <= PRBS_INIT;
latch_y_all <= PRBS_INIT;
end
else if (clk_en) begin
latch_y <= y_comb;
latch_y_all <= Y;
end
always @(posedge clk or negedge rstn)
if (!rstn) begin
insert_er_d <= 3'b0;
error <= 1'b0;
end
else if (clk_en) begin
insert_er_d <= {insert_er_d[1:0], insert_er};
error <= latch_y_all != latch_y; //for cfg_prbs_mode 1~6
end
assign X = latch_y;
assign dout[127:1] = X[128:2];
assign dout[0] = (insert_er_d[2] ^ insert_er_d[1]) ? (~X[1]) : X[1];
endmodule |
module test_rd_ctrl_v1_0 #(
parameter DATA_PATTERN0 = 8'h55,
parameter DATA_PATTERN1 = 8'haa,
parameter DATA_PATTERN2 = 8'h7f,
parameter DATA_PATTERN3 = 8'h80,
parameter DATA_PATTERN4 = 8'h55,
parameter DATA_PATTERN5 = 8'haa,
parameter DATA_PATTERN6 = 8'h7f,
parameter DATA_PATTERN7 = 8'h80,
parameter DATA_MASK_EN = 0,
parameter CTRL_ADDR_WIDTH = 28,
parameter MEM_DQ_WIDTH = 16,
parameter MEM_SPACE_AW = 18
)(
input clk ,
input rst_n ,
input pattern_en ,
input random_data_en,
input read_repeat_en,
input [3:0] read_repeat_num,
input stress_test ,
input write_to_read ,
input data_order ,
input [7:0] dq_inversion ,
input [CTRL_ADDR_WIDTH-1:0] random_rw_addr,
input [3:0] random_axi_id ,
input [3:0] random_axi_len,
input random_axi_ap ,
input read_en ,
output reg read_done_p ,
output reg [CTRL_ADDR_WIDTH-1:0] axi_araddr ,
output reg axi_aruser_ap ,
output reg [3:0] axi_aruser_id ,
output reg [3:0] axi_arlen ,
input axi_arready ,
output reg axi_arvalid ,
input [MEM_DQ_WIDTH*8-1:0] axi_rdata ,
//input [3:0] axi_rid ,
//input axi_rlast ,
input axi_rvalid ,
output reg [7:0] err_cnt,
output reg err_flag_led ,
output reg[MEM_DQ_WIDTH*8-1:0] err_data_out ,
output reg[MEM_DQ_WIDTH*8-1:0] err_flag_out ,
output reg[MEM_DQ_WIDTH*8-1:0] exp_data_out ,
input manu_clear ,
output reg next_err_flag,
output reg [15:0] result_bit_out,
output reg [2:0] test_rd_state,
output reg [MEM_DQ_WIDTH*8-1:0] next_err_data,
output reg [MEM_DQ_WIDTH*8-1:0] err_data_pre ,
output reg [MEM_DQ_WIDTH*8-1:0] err_data_aft
);
localparam E_IDLE = 3'd0;
localparam E_RD = 3'd1;
localparam E_END = 3'd2;
localparam DQ_NUM = MEM_DQ_WIDTH/8;
reg [15:0] req_rd_cnt;
reg [15:0] execute_rd_cnt;
wire read_finished;
wire [15:0] rd_data_addr;
wire [9:0] rd_data_addr0;
wire [9:0] rd_data_addr1;
wire [9:0] rd_data_addr2;
wire [9:0] rd_data_addr3;
wire [9:0] rd_data_addr4;
wire [9:0] rd_data_addr5;
wire [9:0] rd_data_addr6;
wire [9:0] rd_data_addr7;
wire [7:0] rd_data_random_0;
wire [7:0] rd_data_random_1;
wire [7:0] rd_data_random_2;
wire [7:0] rd_data_random_3;
wire [7:0] rd_data_random_4;
wire [7:0] rd_data_random_5;
wire [7:0] rd_data_random_6;
wire [7:0] rd_data_random_7;
wire [7:0] rd_data_r0;
wire [7:0] rd_data_r1;
wire [7:0] rd_data_r2;
wire [7:0] rd_data_r3;
wire [7:0] rd_data_r4;
wire [7:0] rd_data_r5;
wire [7:0] rd_data_r6;
wire [7:0] rd_data_r7;
wire [7:0] rd_data_0;
wire [7:0] rd_data_1;
wire [7:0] rd_data_2;
wire [7:0] rd_data_3;
wire [7:0] rd_data_4;
wire [7:0] rd_data_5;
wire [7:0] rd_data_6;
wire [7:0] rd_data_7;
wire [MEM_DQ_WIDTH*8-1:0] rddata_exp_pre;
wire [MEM_DQ_WIDTH*8-1:0] rddata_exp;
reg [MEM_DQ_WIDTH*8-1:0] rddata_exp_reorder;
reg [MEM_DQ_WIDTH*8-1:0] rddata_exp_d1;
reg [MEM_DQ_WIDTH*8-1:0] rddata_exp_d2;
reg [MEM_DQ_WIDTH*8-1:0] data_err ;
reg err;
reg [MEM_DQ_WIDTH*8-1:0] rddata_mask;
reg [MEM_DQ_WIDTH*8-1:0] rddata_mask_d1;
wire [15:0] prbs_din;
wire [63:0] prbs_dout;
wire prbs_en;
reg prbs_din_en;
reg axi_rvalid_d1;
reg axi_rvalid_d2;
reg [CTRL_ADDR_WIDTH-1:0] normal_rd_addr;
reg [3:0] cnt_len;
reg [3:0] rd_cnt;
reg [MEM_DQ_WIDTH*8-1:0] axi_rdata_d1 ;
reg [MEM_DQ_WIDTH*8-1:0] axi_rdata_d2 ;
reg [MEM_DQ_WIDTH*8-1:0] axi_rdata_d3 ;
reg manu_clear_d1,manu_clear_d2;
reg [3:0] read_repeat_num_d0;
reg [3:0] read_repeat_num_d1;
reg read_finished_d0;
reg read_finished_d1;
wire read_finished_pos;
reg [3:0] result_cnt;
reg result_bit_lock;
wire [7:0] rd_data_mask;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)begin
read_repeat_num_d0 <= 4'd0;
read_repeat_num_d1 <= 4'd0;
end
else begin
read_repeat_num_d0 <= read_repeat_num;
read_repeat_num_d1 <= read_repeat_num_d0;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
test_rd_state <= E_IDLE;
else begin
case (test_rd_state)
E_IDLE: begin
if (read_en & read_finished)
test_rd_state <= E_RD;
end
E_RD: begin
if (axi_arvalid&axi_arready)
test_rd_state <= E_END;
end
E_END: begin
if (read_finished)
test_rd_state <= E_IDLE;
end
default: begin
test_rd_state <= E_IDLE;
end
endcase
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
axi_araddr <= {CTRL_ADDR_WIDTH{1'b0}};
axi_aruser_id <= 4'b0;
axi_arlen <= 4'b0;
axi_aruser_ap <= 1'b0;
end
else if((test_rd_state == E_IDLE) & read_en & read_finished)
begin
axi_aruser_id <= random_axi_id;
axi_araddr <= random_rw_addr;
axi_arlen <= random_axi_len;
axi_aruser_ap <= random_axi_ap;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
axi_arvalid <= 1'b0;
read_done_p <= 1'b0;
rd_cnt <= 4'd0;
end
else begin
case (test_rd_state)
E_IDLE: begin
read_done_p <= 1'b0 ;
axi_arvalid <= 1'b0;
end
E_RD: begin
axi_arvalid <= 1'b1;
if (axi_arvalid&axi_arready) begin
axi_arvalid <= 1'b0;
if(read_repeat_en) begin
if(rd_cnt==read_repeat_num_d1)
rd_cnt <= 4'd0;
else
rd_cnt <= rd_cnt + 4'd1;
end
if(read_repeat_en) begin
if(rd_cnt==read_repeat_num_d1)
read_done_p <= 1'b1;
else
read_done_p <= 1'b0;
end
else
read_done_p <= 1'b1;
end
end
E_END: begin
axi_arvalid <= 1'b0;
read_done_p <= 1'b0;
end
default: begin
axi_arvalid <= 1'b0;
read_done_p <= 1'b0;
end
endcase
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
normal_rd_addr <= {CTRL_ADDR_WIDTH{1'b0}};
cnt_len <= 4'd0;
end
else begin
if(test_rd_state == E_RD) begin
normal_rd_addr <= axi_araddr;
cnt_len <= 4'd0;
end
else if(test_rd_state == E_END) begin
if(cnt_len <= axi_arlen) begin
if(axi_rvalid) begin
normal_rd_addr <= normal_rd_addr + 8;
cnt_len <= cnt_len + 4'd1;
end
end
end
end
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
req_rd_cnt <= 16'd0;
execute_rd_cnt <= 16'd0;
end
else begin
if (axi_arvalid & axi_arready) begin
req_rd_cnt <= req_rd_cnt + {8'd0,axi_arlen} + 1;
end
if (axi_rvalid) begin
execute_rd_cnt <= execute_rd_cnt + 1;
end
end
assign read_finished = (req_rd_cnt == execute_rd_cnt);
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
axi_rvalid_d1 <= 1'b0;
axi_rvalid_d2 <= 1'b0;
end
else
begin
axi_rvalid_d1 <= axi_rvalid;
axi_rvalid_d2 <= axi_rvalid_d1;
end
end
assign rd_data_addr = normal_rd_addr[15:0];
assign rd_data_random_0 = random_data_en ? prbs_dout[7:0] : prbs_dout[7:0] + 8'd0;
assign rd_data_random_1 = random_data_en ? prbs_dout[15:8] : prbs_dout[7:0] + 8'd1;
assign rd_data_random_2 = random_data_en ? prbs_dout[23:16] : prbs_dout[7:0] + 8'd2;
assign rd_data_random_3 = random_data_en ? prbs_dout[31:24] : prbs_dout[7:0] + 8'd3;
assign rd_data_random_4 = random_data_en ? prbs_dout[39:32] : prbs_dout[7:0] + 8'd4;
assign rd_data_random_5 = random_data_en ? prbs_dout[47:40] : prbs_dout[7:0] + 8'd5;
assign rd_data_random_6 = random_data_en ? prbs_dout[55:48] : prbs_dout[7:0] + 8'd6;
assign rd_data_random_7 = random_data_en ? prbs_dout[63:56] : prbs_dout[7:0] + 8'd7;
assign rd_data_r0 = pattern_en ? DATA_PATTERN0 : stress_test ? rd_data_random_0 : rd_data_random_0 ;
assign rd_data_r1 = pattern_en ? DATA_PATTERN1 : stress_test ? rd_data_random_0 : rd_data_random_1 ;
assign rd_data_r2 = pattern_en ? DATA_PATTERN2 : stress_test ? rd_data_random_0 : rd_data_random_2 ;
assign rd_data_r3 = pattern_en ? DATA_PATTERN3 : stress_test ? rd_data_random_0 : rd_data_random_3 ;
assign rd_data_r4 = pattern_en ? DATA_PATTERN4 : stress_test ? rd_data_random_0 : rd_data_random_4 ;
assign rd_data_r5 = pattern_en ? DATA_PATTERN5 : stress_test ? rd_data_random_0 : rd_data_random_5 ;
assign rd_data_r6 = pattern_en ? DATA_PATTERN6 : stress_test ? rd_data_random_0 : rd_data_random_6 ;
assign rd_data_r7 = pattern_en ? DATA_PATTERN7 : stress_test ? rd_data_random_0 : rd_data_random_7 ;
assign rd_data_0 = dq_inversion[0] ? (~rd_data_r0) : rd_data_r0;
assign rd_data_1 = dq_inversion[1] ? (~rd_data_r1) : rd_data_r1;
assign rd_data_2 = dq_inversion[2] ? (~rd_data_r2) : rd_data_r2;
assign rd_data_3 = dq_inversion[3] ? (~rd_data_r3) : rd_data_r3;
assign rd_data_4 = dq_inversion[4] ? (~rd_data_r4) : rd_data_r4;
assign rd_data_5 = dq_inversion[5] ? (~rd_data_r5) : rd_data_r5;
assign rd_data_6 = dq_inversion[6] ? (~rd_data_r6) : rd_data_r6;
assign rd_data_7 = dq_inversion[7] ? (~rd_data_r7) : rd_data_r7;
assign rddata_exp_pre = {{DQ_NUM{rd_data_7}},{DQ_NUM{rd_data_6}},{DQ_NUM{rd_data_5}},{DQ_NUM{rd_data_4}},{DQ_NUM{rd_data_3}},{DQ_NUM{rd_data_2}},{DQ_NUM{rd_data_1}},{DQ_NUM{rd_data_0}}};
assign rddata_exp = (stress_test | data_order) ? rddata_exp_reorder : rddata_exp_pre ;
integer i,j,k;
always @(*) begin
for (i=0; i<8; i=i+1)
for (j=0; j<DQ_NUM; j=j+1)
for (k=0; k<8; k=k+1)
rddata_exp_reorder[i*8*DQ_NUM+j*8+k] = rddata_exp_pre[k*8*DQ_NUM+j*8+i];
end
assign prbs_din = rd_data_addr;
assign prbs_en = (write_to_read == 0) ? 0 : axi_rvalid;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
prbs_din_en <= 0;
else if(write_to_read == 0)
prbs_din_en <= 1;
else begin
if(read_repeat_en==0)
prbs_din_en <= 0;
else if(axi_arvalid&axi_arready)
prbs_din_en <= 1;
else if(axi_rvalid)
prbs_din_en <= 0;
end
end
prbs15_64bit_v1_0 #(
.PRBS_INIT (16'h0)
)
u_prbs15_64bit
(
.clk (clk ),
.rst_n (rst_n ),
.prbs_en (prbs_en ),
.din_en (prbs_din_en),
.din (prbs_din),
.dout (prbs_dout)
);
assign rd_data_mask = (DATA_MASK_EN == 1) ? prbs_dout[7:0] : 8'hff;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
axi_rdata_d1 <= {MEM_DQ_WIDTH{8'h0}} ;
else if(axi_rvalid)
axi_rdata_d1 <= axi_rdata;
else
axi_rdata_d1 <= axi_rdata_d1 ;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
axi_rdata_d2 <= {MEM_DQ_WIDTH{8'h0}} ;
else
axi_rdata_d2 <= axi_rdata_d1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
axi_rdata_d3 <= {MEM_DQ_WIDTH{8'h0}} ;
else
axi_rdata_d3 <= axi_rdata_d2;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rddata_exp_d1 <= {MEM_DQ_WIDTH{8'h0}} ;
else if( axi_rvalid )
rddata_exp_d1 <= rddata_exp;
else
rddata_exp_d1 <= rddata_exp_d1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rddata_exp_d2 <= {MEM_DQ_WIDTH{8'h0}} ;
else
rddata_exp_d2 <= rddata_exp_d1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rddata_mask <= {MEM_DQ_WIDTH{8'h0}} ;
else if( axi_rvalid )
rddata_mask <= {{(DQ_NUM*8){rd_data_mask[7]}},{(DQ_NUM*8){rd_data_mask[6]}},{(DQ_NUM*8){rd_data_mask[5]}},{(DQ_NUM*8){rd_data_mask[4]}},
{(DQ_NUM*8){rd_data_mask[3]}},{(DQ_NUM*8){rd_data_mask[2]}},{(DQ_NUM*8){rd_data_mask[1]}},{(DQ_NUM*8){rd_data_mask[0]}}}; //0:mask
else
rddata_mask <= rddata_mask;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rddata_mask_d1 <= {MEM_DQ_WIDTH{8'h0}} ;
else
rddata_mask_d1 <= rddata_mask;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
data_err <= {MEM_DQ_WIDTH{8'h0}};
else
data_err <= (axi_rdata_d1 ^ rddata_exp_d1) & rddata_mask;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
err <= 0;
else
err <= |((axi_rdata_d1 ^ rddata_exp_d1) & rddata_mask);
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
err_cnt <= 8'b0;
err_flag_led <= 1'b0;
end
else if(manu_clear_d2)
begin
err_cnt <= 8'b0;
err_flag_led <= 1'b0;
end
else if(err && axi_rvalid_d2)
begin
if(err_cnt == 8'hff)
err_cnt <= err_cnt;
else
err_cnt <= err_cnt + 8'b1;
err_flag_led <= 1'b1;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
read_finished_d0 <= 0;
read_finished_d1 <= 0;
end
else begin
read_finished_d0 <= read_finished;
read_finished_d1 <= read_finished_d0;
end
end
assign read_finished_pos = read_finished_d0 & ~read_finished_d1;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
result_cnt <= 4'd0;
else if(read_repeat_en) begin
if(read_finished_pos)begin
if(result_cnt==read_repeat_num_d1)
result_cnt <= 4'd0;
else
result_cnt <= result_cnt + 4'd1;
end
end
else
result_cnt <= 4'd0;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
result_bit_lock <= 0;
else if(manu_clear_d2)
result_bit_lock <= 0;
else if(read_repeat_en) begin
if(read_finished_pos & (result_cnt==read_repeat_num_d1) & err_flag_led)
result_bit_lock <= 1;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
result_bit_out <= 16'h0;
else if(manu_clear_d2)
result_bit_out <= 16'h0;
else if(err & axi_rvalid_d2 & ~result_bit_lock)
begin
for(i=0;i<16;i=i+1)
if(i == result_cnt)
result_bit_out[i] <= 1;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
manu_clear_d2 <= 0;
manu_clear_d1 <= 0;
end
else begin
manu_clear_d2 <= manu_clear_d1;
manu_clear_d1 <= manu_clear;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
err_data_out <= {MEM_DQ_WIDTH{8'h0}} ;
err_flag_out <= {MEM_DQ_WIDTH{8'h0}} ;
exp_data_out <= {MEM_DQ_WIDTH{8'h0}} ;
end
else if(err & axi_rvalid_d2 & ~err_flag_led)begin
err_data_out <= axi_rdata_d2;
err_flag_out <= data_err;
exp_data_out <= rddata_exp_d2 & rddata_mask_d1;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
err_data_pre <= {MEM_DQ_WIDTH{8'h0}};
else if(err_flag_led == 0)
err_data_pre <= axi_rdata_d3;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
err_data_aft <= {MEM_DQ_WIDTH{8'h0}};
else if(err_flag_led == 0)
err_data_aft <= axi_rdata_d1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
next_err_flag <= 1'b0;
else if(manu_clear_d2)
next_err_flag <= 1'b0;
else if(err & axi_rvalid_d2 & err_flag_led)
next_err_flag <= 1'b1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
next_err_data <= {MEM_DQ_WIDTH{8'h0}} ;
end
else if(err & axi_rvalid_d2 & err_flag_led & ~next_err_flag)begin
next_err_data <= axi_rdata_d2;
end
end
endmodule |
module prbs15_64bit_v1_0 #(
parameter PRBS_INIT = 16'h00
)
(
input clk ,
input rst_n ,
input prbs_en ,
input din_en ,
input [15:0] din ,
output [63:0] dout
);
wire [63:0] Y;
reg [63:0] O;
wire [15:0] X;
assign Y[63] = X[11] ^ X[7] ^ 1 ; //Y[46] ^ Y[45] ^ 1 ;
assign Y[62] = X[10] ^ X[6] ^ 1 ; //Y[45] ^ Y[44] ^ 1 ;
assign Y[61] = X[9] ^ X[5] ^ 1 ; //Y[44] ^ Y[43] ^ 1 ;
assign Y[60] = X[8] ^ X[4] ^ 1 ; //Y[43] ^ Y[42] ^ 1 ;
assign Y[59] = X[7] ^ X[3] ^ 1 ; //Y[42] ^ Y[41] ^ 1 ;
assign Y[58] = X[6] ^ X[2] ^ 1 ; //Y[41] ^ Y[40] ^ 1 ;
assign Y[57] = X[5] ^ X[1] ^ 1 ; //Y[40] ^ Y[39] ^ 1 ;
assign Y[56] = X[4] ^ X[0] ^ 1 ; //Y[39] ^ Y[38] ^ 1 ;
assign Y[55] = X[3] ^ X[14] ^ X[13] ; //Y[38] ^ Y[37] ^ 1 ;
assign Y[54] = X[2] ^ X[13] ^ X[12] ^ 1; //Y[37] ^ Y[36] ^ 1 ;
assign Y[53] = X[1] ^ X[12] ^ X[11] ^ 1; //Y[36] ^ Y[35] ^ 1 ;
assign Y[52] = X[0] ^ X[11] ^ X[10] ; //Y[35] ^ Y[34] ^ 1 ;
assign Y[51] = X[14] ^ X[10] ^ X[13] ^ X[9] ; //Y[34] ^ Y[33] ^ 1 ;
assign Y[50] = X[13] ^ X[9] ^ X[12] ^ X[8] ^ 1 ; //Y[33] ^ Y[32] ^ 1 ;
assign Y[49] = X[12] ^ X[11] ^ X[8] ^ X[7] ; //Y[32] ^ Y[46] ^ Y[45] ;
assign Y[48] = X[11] ^ X[10] ^ X[7] ^ X[6] ; //Y[46] ^ Y[44] ;
assign Y[47] = X[12] ^ X[10] ^ X[11] ^ X[9] ^ 1 ; //Y[30] ^ Y[29] ^ 1 ;
assign Y[46] = X[11] ^ X[9] ^ X[10] ^ X[8] ^ 1 ; //Y[29] ^ Y[28] ^ 1 ;
assign Y[45] = X[10] ^ X[8] ^ X[9] ^ X[7] ^ 1 ; //Y[28] ^ Y[27] ^ 1 ;
assign Y[44] = X[9] ^ X[7] ^ X[8] ^ X[6] ^ 1 ; //Y[27] ^ Y[26] ^ 1 ;
assign Y[43] = X[8] ^ X[6] ^ X[7] ^ X[5] ^ 1 ; //Y[26] ^ Y[25] ^ 1 ;
assign Y[42] = X[7] ^ X[5] ^ X[6] ^ X[4] ^ 1 ; //Y[25] ^ Y[24] ^ 1 ;
assign Y[41] = X[6] ^ X[4] ^ X[5] ^ X[3] ^ 1 ; //Y[24] ^ Y[23] ^ 1 ;
assign Y[40] = X[5] ^ X[3] ^ X[4] ^ X[2] ^ 1 ; //Y[23] ^ Y[22] ^ 1 ;
assign Y[39] = X[4] ^ X[2] ^ X[3] ^ X[1] ^ 1 ; //Y[22] ^ Y[21] ^ 1 ;
assign Y[38] = X[3] ^ X[1] ^ X[2] ^ X[0] ^ 1 ; //Y[21] ^ Y[20] ^ 1 ;
assign Y[37] = X[2] ^ X[0] ^ X[1] ^ X[14] ^ X[13] ; //Y[20] ^ Y[19] ^ 1 ;
assign Y[36] = X[1] ^ X[14] ^ X[0] ^ X[12] ; //Y[19] ^ Y[18] ^ 1 ;
assign Y[35] = X[0] ^ X[14] ^ X[11] ; //Y[18] ^ Y[17] ^ 1 ;
assign Y[34] = X[14] ^ X[10] ^ 1 ; //Y[17] ^ Y[16] ^ 1 ;
assign Y[33] = X[13] ^ X[9] ^ 0 ; //Y[16] ^ Y[30] ^ Y[29] ;
assign Y[32] = X[12] ^ X[8] ^ 0 ; //Y[30] ^ Y[28] ;
assign Y[31] = X[13] ^ X[11] ^ 1 ; //Y[14] ^ Y[13] ^ 1 ;
assign Y[30] = X[12] ^ X[10] ^ 1 ; //Y[13] ^ Y[12] ^ 1 ;
assign Y[29] = X[11] ^ X[9] ^ 1 ; //Y[12] ^ Y[11] ^ 1 ;
assign Y[28] = X[10] ^ X[8] ^ 1 ; //Y[11] ^ Y[10] ^ 1 ;
assign Y[27] = X[9] ^ X[7] ^ 1 ; //Y[10] ^ Y[9] ^ 1 ;
assign Y[26] = X[8] ^ X[6] ^ 1 ; //Y[9] ^ Y[8] ^ 1 ;
assign Y[25] = X[7] ^ X[5] ^ 1 ; //Y[8] ^ Y[7] ^ 1 ;
assign Y[24] = X[6] ^ X[4] ^ 1 ; //Y[7] ^ Y[6] ^ 1 ;
assign Y[23] = X[5] ^ X[3] ^ 1 ; //Y[6] ^ Y[5] ^ 1 ;
assign Y[22] = X[4] ^ X[2] ^ 1 ; //Y[5] ^ Y[4] ^ 1 ;
assign Y[21] = X[3] ^ X[1] ^ 1 ; //Y[4] ^ Y[3] ^ 1 ;
assign Y[20] = X[2] ^ X[0] ^ 1 ; //Y[3] ^ Y[2] ^ 1 ;
assign Y[19] = X[1] ^ X[14] ^ X[13] ; //Y[2] ^ Y[1] ^ 1 ;
assign Y[18] = X[0] ^ X[13] ^ X[12] ^ 1 ; //Y[1] ^ Y[0] ^ 1;
assign Y[17] = X[14] ^ X[12] ^ X[13] ^ X[11] ; //Y[0] ^ Y[14] ^ Y[13] ;
assign Y[16] = X[13] ^ X[12] ^ X[11] ^ X[10] ; //Y[14] ^ Y[12] ;
//assign Y[15:2] = X[14:1] ^ X[13:0] ^ 14'h3fff ; // Y = X15 + X14 + 1
assign Y[15] = X[14] ^ X[13] ^ 1 ;
assign Y[14] = X[13] ^ X[12] ^ 1 ;
assign Y[13] = X[12] ^ X[11] ^ 1 ;
assign Y[12] = X[11] ^ X[10] ^ 1 ;
assign Y[11] = X[10] ^ X[9] ^ 1 ;
assign Y[10] = X[9] ^ X[8] ^ 1 ;
assign Y[9] = X[8] ^ X[7] ^ 1 ;
assign Y[8] = X[7] ^ X[6] ^ 1 ;
assign Y[7] = X[6] ^ X[5] ^ 1 ;
assign Y[6] = X[5] ^ X[4] ^ 1 ;
assign Y[5] = X[4] ^ X[3] ^ 1 ;
assign Y[4] = X[3] ^ X[2] ^ 1 ;
assign Y[3] = X[2] ^ X[1] ^ 1 ;
assign Y[2] = X[1] ^ X[0] ^ 1 ;
assign Y[1] = X[0] ^ X[14] ^ X[13] ^ 0 ; // X[0] ^ Y[15] ^ 1;
assign Y[0] = X[14] ^ X[12] ^ 0 ; // Y[14] ^ Y[15] ^ 1;
assign X = (din_en==1) ? din : O[63:48] ;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n) begin
O <= PRBS_INIT;
end
else if (prbs_en) begin
O <= Y;
end
else begin
O <= O;
end
end
assign dout = Y;
endmodule |
module test_wr_ctrl_v1_0 #(
parameter DATA_PATTERN0 = 8'h55,
parameter DATA_PATTERN1 = 8'haa,
parameter DATA_PATTERN2 = 8'h7f,
parameter DATA_PATTERN3 = 8'h80,
parameter DATA_PATTERN4 = 8'h55,
parameter DATA_PATTERN5 = 8'haa,
parameter DATA_PATTERN6 = 8'h7f,
parameter DATA_PATTERN7 = 8'h80,
parameter DATA_MASK_EN = 0,
parameter CTRL_ADDR_WIDTH = 28,
parameter MEM_DQ_WIDTH = 16,
parameter MEM_SPACE_AW = 18
)(
input clk ,
input rst_n ,
input init_start ,
input write_en ,
input insert_err ,
output reg write_done_p ,
output reg init_done ,
input pattern_en ,
input random_data_en ,
input stress_test ,
input write_to_read ,
input read_repeat_en ,
input data_order ,
input [7:0] dq_inversion ,
input [CTRL_ADDR_WIDTH-1:0] random_rw_addr ,
input [3:0] random_axi_id ,
input [3:0] random_axi_len ,
input random_axi_ap ,
output reg [CTRL_ADDR_WIDTH-1:0] axi_awaddr ,
output reg axi_awuser_ap ,
output reg [3:0] axi_awuser_id ,
output reg [3:0] axi_awlen ,
input axi_awready ,
output reg axi_awvalid ,
output [MEM_DQ_WIDTH*8-1:0] axi_wdata ,
output [MEM_DQ_WIDTH*8/8-1:0] axi_wstrb ,
input axi_wready ,
output reg [2:0] test_wr_state
);
localparam DQ_NUM = MEM_DQ_WIDTH/8;
localparam [CTRL_ADDR_WIDTH:0] AXI_ADDR_MAX = (1'b1<<MEM_SPACE_AW);
localparam E_IDLE = 3'd0;
localparam E_WR = 3'd1;
localparam E_END = 3'd2;
reg [CTRL_ADDR_WIDTH:0] init_addr;
reg [CTRL_ADDR_WIDTH-1:0] normal_wr_addr;
wire [15:0] wr_data_addr;
reg [15:0] req_wr_cnt ;
reg [15:0] execute_wr_cnt ;
wire write_finished ;
reg [7:0] cnt_len;
reg [8*MEM_DQ_WIDTH-1:0] wrdata_reorder;
wire[8*MEM_DQ_WIDTH-1:0] wrdata_pre;
wire[7:0] wr_data_random_0;
wire[7:0] wr_data_random_1;
wire[7:0] wr_data_random_2;
wire[7:0] wr_data_random_3;
wire[7:0] wr_data_random_4;
wire[7:0] wr_data_random_5;
wire[7:0] wr_data_random_6;
wire[7:0] wr_data_random_7;
wire [9:0] wr_data_addr0;
wire [9:0] wr_data_addr1;
wire [9:0] wr_data_addr2;
wire [9:0] wr_data_addr3;
wire [9:0] wr_data_addr4;
wire [9:0] wr_data_addr5;
wire [9:0] wr_data_addr6;
wire [9:0] wr_data_addr7;
wire [7:0] wr_data_r0;
wire [7:0] wr_data_r1;
wire [7:0] wr_data_r2;
wire [7:0] wr_data_r3;
wire [7:0] wr_data_r4;
wire [7:0] wr_data_r5;
wire [7:0] wr_data_r6;
wire [7:0] wr_data_r7;
wire [7:0] wr_data_0;
wire [7:0] wr_data_1;
wire [7:0] wr_data_2;
wire [7:0] wr_data_3;
wire [7:0] wr_data_4;
wire [7:0] wr_data_5;
wire [7:0] wr_data_6;
wire [7:0] wr_data_7;
wire [7:0] wr_data_mask;
wire [15:0] prbs_din;
wire [63:0] prbs_dout;
wire prbs_en;
reg prbs_din_en;
wire [8*MEM_DQ_WIDTH-1:0] wrdata_ch ;
reg insert_err_d1,insert_err_d2;
wire insert_err_pos;
reg insert_err_valid;
reg [7:0] delay_cnt;
assign axi_wstrb = {{DQ_NUM{wr_data_mask[7]}},{DQ_NUM{wr_data_mask[6]}},{DQ_NUM{wr_data_mask[5]}},{DQ_NUM{wr_data_mask[4]}},
{DQ_NUM{wr_data_mask[3]}},{DQ_NUM{wr_data_mask[2]}},{DQ_NUM{wr_data_mask[1]}},{DQ_NUM{wr_data_mask[0]}}};
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
axi_awaddr <= 'b0;
axi_awuser_ap <= 1'b0;
axi_awuser_id <= 4'b0;
axi_awlen <= 4'b0;
axi_awvalid <= 1'b0;
test_wr_state <= E_IDLE;
write_done_p <= 1'b0;
end
else begin
if(init_start) begin
axi_awlen <= 4'd15;
axi_awuser_ap <= 1'b0;
if (axi_awaddr < (AXI_ADDR_MAX - 8'd128)) begin
axi_awvalid <= 1;
if(axi_awvalid&axi_awready) begin
axi_awaddr <= axi_awaddr + 8'd128;
axi_awuser_id <= axi_awuser_id + 1;
end
end
else if(axi_awaddr == (AXI_ADDR_MAX - 8'd128)) begin
if(axi_awvalid&axi_awready)
axi_awvalid <= 0;
end
else
axi_awvalid <= 0;
end
else begin
if ((test_wr_state == E_IDLE) && write_en && write_finished) begin //add more condition for easy debug
axi_awuser_id <= random_axi_id;
axi_awaddr <= random_rw_addr;
axi_awlen <= random_axi_len;
axi_awuser_ap <= random_axi_ap;
end
case(test_wr_state)
E_IDLE: begin
if (write_en && write_finished)
test_wr_state <= E_WR;
end
E_WR: begin
axi_awvalid <= 1'b1;
if (axi_awvalid&axi_awready) begin
test_wr_state <= E_END;
write_done_p <= 1'b1;
axi_awvalid <= 1'b0;
end
end
E_END: begin
axi_awvalid <= 1'b0;
write_done_p <= 1'b0;
if (write_finished)
test_wr_state <= E_IDLE;
end
default: begin
test_wr_state <= E_IDLE;
end
endcase
end
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
init_done <= 0;
else if((init_start==1)&&(init_addr >= AXI_ADDR_MAX) && (delay_cnt[7]==1))
init_done <= 1;
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
delay_cnt <= 8'd0;
else if((init_start==1)&&(init_addr >= AXI_ADDR_MAX))
delay_cnt <= delay_cnt + 8'd1;
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
init_addr <= {(CTRL_ADDR_WIDTH+1){1'b0}};
normal_wr_addr <= {CTRL_ADDR_WIDTH{1'b0}};
end
else begin
if(init_start) begin
if(init_addr < AXI_ADDR_MAX)begin
if(axi_wready)
init_addr <= init_addr + 8;
end
end
else begin
if(test_wr_state == E_WR)begin
normal_wr_addr <= axi_awaddr;
end
else if(test_wr_state == E_END) begin
if(axi_wready) begin
normal_wr_addr <= normal_wr_addr + 8;
end
end
end
end
end
assign axi_wdata = wrdata_ch ;
assign wr_data_addr = (init_start==1) ? init_addr[15:0] : normal_wr_addr[15:0];
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
req_wr_cnt <= 16'd0;
execute_wr_cnt <= 16'd0;
end
else if (!init_start)
begin
if (axi_awvalid & axi_awready) begin
req_wr_cnt <= req_wr_cnt + axi_awlen + 1;
end
if (axi_wready) begin
execute_wr_cnt <= execute_wr_cnt + 1;
end
end
else begin
req_wr_cnt <= 16'd0;
execute_wr_cnt <= 16'd0;
end
assign write_finished = (req_wr_cnt == execute_wr_cnt);
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
insert_err_d1 <= 0;
insert_err_d2 <= 0;
end
else begin
insert_err_d1 <= insert_err;
insert_err_d2 <= insert_err_d1;
end
end
assign insert_err_pos = insert_err_d1 & ~insert_err_d2;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
insert_err_valid <= 0;
else if(insert_err_pos)
insert_err_valid <= 1;
else if(axi_wready)
insert_err_valid <= 0;
end
assign wr_data_random_0 = random_data_en ? prbs_dout[7:0] : prbs_dout[7:0] + 8'd0;
assign wr_data_random_1 = random_data_en ? prbs_dout[15:8] : prbs_dout[7:0] + 8'd1;
assign wr_data_random_2 = random_data_en ? prbs_dout[23:16] : prbs_dout[7:0] + 8'd2;
assign wr_data_random_3 = random_data_en ? prbs_dout[31:24] : prbs_dout[7:0] + 8'd3;
assign wr_data_random_4 = random_data_en ? prbs_dout[39:32] : prbs_dout[7:0] + 8'd4;
assign wr_data_random_5 = random_data_en ? prbs_dout[47:40] : prbs_dout[7:0] + 8'd5;
assign wr_data_random_6 = random_data_en ? prbs_dout[55:48] : prbs_dout[7:0] + 8'd6;
assign wr_data_random_7 = random_data_en ? prbs_dout[63:56] : prbs_dout[7:0] + 8'd7;
assign wr_data_r0 = pattern_en ? DATA_PATTERN0 : stress_test ? wr_data_random_0 : wr_data_random_0 ;
assign wr_data_r1 = pattern_en ? DATA_PATTERN1 : stress_test ? wr_data_random_0 : wr_data_random_1 ;
assign wr_data_r2 = pattern_en ? DATA_PATTERN2 : stress_test ? wr_data_random_0 : wr_data_random_2 ;
assign wr_data_r3 = pattern_en ? DATA_PATTERN3 : stress_test ? wr_data_random_0 : wr_data_random_3 ;
assign wr_data_r4 = pattern_en ? DATA_PATTERN4 : stress_test ? wr_data_random_0 : wr_data_random_4 ;
assign wr_data_r5 = pattern_en ? DATA_PATTERN5 : stress_test ? wr_data_random_0 : wr_data_random_5 ;
assign wr_data_r6 = pattern_en ? DATA_PATTERN6 : stress_test ? wr_data_random_0 : wr_data_random_6 ;
assign wr_data_r7 = pattern_en ? DATA_PATTERN7 : stress_test ? wr_data_random_0 : wr_data_random_7 ;
assign wr_data_0 = (dq_inversion[0] ^ insert_err_valid) ? (~wr_data_r0) : wr_data_r0;
assign wr_data_1 = dq_inversion[1] ? (~wr_data_r1) : wr_data_r1;
assign wr_data_2 = dq_inversion[2] ? (~wr_data_r2) : wr_data_r2;
assign wr_data_3 = dq_inversion[3] ? (~wr_data_r3) : wr_data_r3;
assign wr_data_4 = dq_inversion[4] ? (~wr_data_r4) : wr_data_r4;
assign wr_data_5 = dq_inversion[5] ? (~wr_data_r5) : wr_data_r5;
assign wr_data_6 = dq_inversion[6] ? (~wr_data_r6) : wr_data_r6;
assign wr_data_7 = dq_inversion[7] ? (~wr_data_r7) : wr_data_r7;
assign wrdata_pre = {{DQ_NUM{wr_data_7}},{DQ_NUM{wr_data_6}},{DQ_NUM{wr_data_5}},{DQ_NUM{wr_data_4}},{DQ_NUM{wr_data_3}},{DQ_NUM{wr_data_2}},{DQ_NUM{wr_data_1}},{DQ_NUM{wr_data_0}}};
assign wrdata_ch = (stress_test | data_order) ? wrdata_reorder : wrdata_pre ;
integer i,j,k;
always @(*) begin
for (i=0; i<8; i=i+1)
for (j=0; j<DQ_NUM; j=j+1)
for (k=0; k<8; k=k+1)
wrdata_reorder[i*8*DQ_NUM+j*8+k] = wrdata_pre[k*8*DQ_NUM+j*8+i];
end
assign prbs_din = wr_data_addr;
assign prbs_en = (write_to_read == 0) ? 0 : axi_wready;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
prbs_din_en <= 0;
else if(write_to_read == 0)
prbs_din_en <= 1;
else begin
if(read_repeat_en==0)
prbs_din_en <= 0;
else if(axi_awvalid&axi_awready)
prbs_din_en <= 1;
else if(axi_wready)
prbs_din_en <= 0;
end
end
prbs15_64bit_v1_0 #(
.PRBS_INIT (16'h0)
)
u_prbs15_64bit
(
.clk (clk ),
.rst_n (rst_n ),
.prbs_en (prbs_en ),
.din_en (prbs_din_en),
.din (prbs_din),
.dout (prbs_dout)
);
assign wr_data_mask = (DATA_MASK_EN == 1) ? prbs_dout[7:0] : 8'hff;
endmodule |
module uart_rd_lock
(
input core_clk ,
input core_rst_n ,
input uart_read_req ,
output reg uart_read_ack ,
input [8:0] uart_read_addr ,
input [31:0] status_bus_80 ,
input [31:0] status_bus_81 ,
input [31:0] status_bus_82 ,
input [31:0] status_bus_83 ,
input [31:0] status_bus_84 ,
input [31:0] status_bus_85 ,
input [31:0] status_bus_86 ,
input [31:0] status_bus_87 ,
input [31:0] status_bus_88 ,
input [31:0] status_bus_89 ,
input [31:0] status_bus_8a ,
input [31:0] status_bus_8b ,
input [31:0] status_bus_8c ,
input [31:0] status_bus_8d ,
input [31:0] status_bus_8e ,
input [31:0] status_bus_8f ,
input [31:0] status_bus_90 ,
input [31:0] status_bus_91 ,
input [31:0] status_bus_92 ,
input [31:0] status_bus_93 ,
input [31:0] status_bus_94 ,
input [31:0] status_bus_95 ,
input [31:0] status_bus_96 ,
input [31:0] status_bus_97 ,
input [31:0] status_bus_98 ,
input [31:0] status_bus_99 ,
input [31:0] status_bus_9a ,
input [31:0] status_bus_9b ,
input [31:0] status_bus_9c ,
input [31:0] status_bus_9d ,
input [31:0] status_bus_9e ,
input [31:0] status_bus_9f ,
input [31:0] status_bus_a0 ,
input [31:0] status_bus_a1 ,
input [31:0] status_bus_a2 ,
input [31:0] status_bus_a3 ,
input [31:0] status_bus_a4 ,
input [31:0] status_bus_a5 ,
input [31:0] status_bus_a6 ,
input [31:0] status_bus_a7 ,
input [31:0] status_bus_a8 ,
input [31:0] status_bus_a9 ,
input [31:0] status_bus_aa ,
input [31:0] status_bus_ab ,
input [31:0] status_bus_ac ,
input [31:0] status_bus_ad ,
input [31:0] status_bus_ae ,
input [31:0] status_bus_af ,
input [31:0] status_bus_b0 ,
input [31:0] status_bus_b1 ,
input [31:0] status_bus_b2 ,
input [31:0] status_bus_b3 ,
input [31:0] status_bus_b4 ,
input [31:0] status_bus_b5 ,
input [31:0] status_bus_b6 ,
input [31:0] status_bus_b7 ,
input [31:0] status_bus_b8 ,
input [31:0] status_bus_b9 ,
input [31:0] status_bus_ba ,
input [31:0] status_bus_bb ,
input [31:0] status_bus_bc ,
input [31:0] status_bus_bd ,
input [31:0] status_bus_be ,
input [31:0] status_bus_bf ,
input [31:0] status_bus_c0 ,
input [31:0] status_bus_c1 ,
input [31:0] status_bus_c2 ,
input [31:0] status_bus_c3 ,
input [31:0] status_bus_c4 ,
input [31:0] status_bus_c5 ,
input [31:0] status_bus_c6 ,
input [31:0] status_bus_c7 ,
input [31:0] status_bus_c8 ,
input [31:0] status_bus_c9 ,
input [31:0] status_bus_ca ,
input [31:0] status_bus_cb ,
input [31:0] status_bus_cc ,
input [31:0] status_bus_cd ,
input [31:0] status_bus_ce ,
input [31:0] status_bus_cf ,
input [31:0] status_bus_d0 ,
input [31:0] status_bus_d1 ,
input [31:0] status_bus_d2 ,
input [31:0] status_bus_d3 ,
input [31:0] status_bus_d4 ,
input [31:0] status_bus_d5 ,
input [31:0] status_bus_d6 ,
input [31:0] status_bus_d7 ,
input [31:0] status_bus_d8 ,
input [31:0] status_bus_d9 ,
input [31:0] status_bus_da ,
input [31:0] status_bus_db ,
input [31:0] status_bus_dc ,
input [31:0] status_bus_dd ,
input [31:0] status_bus_de ,
input [31:0] status_bus_df ,
input [31:0] status_bus_e0 ,
input [31:0] status_bus_e1 ,
input [31:0] status_bus_e2 ,
input [31:0] status_bus_e3 ,
input [31:0] status_bus_e4 ,
input [31:0] status_bus_e5 ,
input [31:0] status_bus_e6 ,
input [31:0] status_bus_e7 ,
input [31:0] status_bus_e8 ,
input [31:0] status_bus_e9 ,
input [31:0] status_bus_ea ,
input [31:0] status_bus_eb ,
input [31:0] status_bus_ec ,
input [31:0] status_bus_ed ,
input [31:0] status_bus_ee ,
input [31:0] status_bus_ef ,
input [31:0] status_bus_f0 ,
input [31:0] status_bus_f1 ,
input [31:0] status_bus_f2 ,
input [31:0] status_bus_f3 ,
input [31:0] status_bus_f4 ,
input [31:0] status_bus_f5 ,
input [31:0] status_bus_f6 ,
input [31:0] status_bus_f7 ,
input [31:0] status_bus_f8 ,
input [31:0] status_bus_f9 ,
input [31:0] status_bus_fa ,
input [31:0] status_bus_fb ,
input [31:0] status_bus_fc ,
input [31:0] status_bus_fd ,
input [31:0] status_bus_fe ,
input [31:0] status_bus_ff ,
output reg [31:0] status_bus_lock
);
reg uart_read_req_syn1;
reg uart_read_req_syn2;
reg uart_read_req_syn3;
wire uart_read_req_inv;
reg uart_read_req_inv_d1;
reg uart_read_req_inv_d2;
wire [32*8-1:0] status_bus_0;
wire [32*8-1:0] status_bus_1;
wire [32*8-1:0] status_bus_2;
wire [32*8-1:0] status_bus_3;
wire [32*8-1:0] status_bus_4;
wire [32*8-1:0] status_bus_5;
wire [32*8-1:0] status_bus_6;
wire [32*8-1:0] status_bus_7;
wire [32*8-1:0] status_bus_8;
wire [32*8-1:0] status_bus_9;
wire [32*8-1:0] status_bus_a;
wire [32*8-1:0] status_bus_b;
wire [32*8-1:0] status_bus_c;
wire [32*8-1:0] status_bus_d;
wire [32*8-1:0] status_bus_e;
wire [32*8-1:0] status_bus_f;
reg [32*8-1:0] status_bus_sel_0;
reg [32*8-1:0] status_bus_sel_1;
reg [32*8-1:0] status_bus_sel_2;
reg [32*8-1:0] status_bus_sel_3;
reg [32*8-1:0] status_bus_sel_4;
reg [32*8-1:0] status_bus_sel_5;
reg [32*8-1:0] status_bus_sel_6;
reg [32*8-1:0] status_bus_sel_7;
reg [32*8-1:0] status_bus_sel;
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
begin
uart_read_req_syn1 <= 1'b0;
uart_read_req_syn2 <= 1'b0;
uart_read_req_syn3 <= 1'b0;
end
else
begin
uart_read_req_syn1 <= uart_read_req;
uart_read_req_syn2 <= uart_read_req_syn1;
uart_read_req_syn3 <= uart_read_req_syn2;
end
end
assign uart_read_req_inv = uart_read_req_syn3 ^ uart_read_req_syn2;
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
uart_read_req_inv_d1 <= 1'b0;
else
uart_read_req_inv_d1 <= uart_read_req_inv;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
uart_read_req_inv_d2 <= 1'b0;
else
uart_read_req_inv_d2 <= uart_read_req_inv_d1;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
uart_read_ack <= 1'b0;
else if(uart_read_req_inv_d2)
uart_read_ack <= ~uart_read_ack;
else;
end
//******************************** status 8x ********************************//
assign status_bus_0 = {status_bus_f0,
status_bus_e0,
status_bus_d0,
status_bus_c0,
status_bus_b0,
status_bus_a0,
status_bus_90,
status_bus_80};
assign status_bus_1 = {status_bus_f1,
status_bus_e1,
status_bus_d1,
status_bus_c1,
status_bus_b1,
status_bus_a1,
status_bus_91,
status_bus_81};
assign status_bus_2 = {status_bus_f2,
status_bus_e2,
status_bus_d2,
status_bus_c2,
status_bus_b2,
status_bus_a2,
status_bus_92,
status_bus_82};
assign status_bus_3 = {status_bus_f3,
status_bus_e3,
status_bus_d3,
status_bus_c3,
status_bus_b3,
status_bus_a3,
status_bus_93,
status_bus_83};
assign status_bus_4 = {status_bus_f4,
status_bus_e4,
status_bus_d4,
status_bus_c4,
status_bus_b4,
status_bus_a4,
status_bus_94,
status_bus_84};
assign status_bus_5 = {status_bus_f5,
status_bus_e5,
status_bus_d5,
status_bus_c5,
status_bus_b5,
status_bus_a5,
status_bus_95,
status_bus_85};
assign status_bus_6 = {status_bus_f6,
status_bus_e6,
status_bus_d6,
status_bus_c6,
status_bus_b6,
status_bus_a6,
status_bus_96,
status_bus_86};
assign status_bus_7 = {status_bus_f7,
status_bus_e7,
status_bus_d7,
status_bus_c7,
status_bus_b7,
status_bus_a7,
status_bus_97,
status_bus_87};
assign status_bus_8 = {status_bus_f8,
status_bus_e8,
status_bus_d8,
status_bus_c8,
status_bus_b8,
status_bus_a8,
status_bus_98,
status_bus_88};
assign status_bus_9 = {status_bus_f9,
status_bus_e9,
status_bus_d9,
status_bus_c9,
status_bus_b9,
status_bus_a9,
status_bus_99,
status_bus_89};
assign status_bus_a = {status_bus_fa,
status_bus_ea,
status_bus_da,
status_bus_ca,
status_bus_ba,
status_bus_aa,
status_bus_9a,
status_bus_8a};
assign status_bus_b = {status_bus_fb,
status_bus_eb,
status_bus_db,
status_bus_cb,
status_bus_bb,
status_bus_ab,
status_bus_9b,
status_bus_8b};
assign status_bus_c = {status_bus_fc,
status_bus_ec,
status_bus_dc,
status_bus_cc,
status_bus_bc,
status_bus_ac,
status_bus_9c,
status_bus_8c};
assign status_bus_d = {status_bus_fd,
status_bus_ed,
status_bus_dd,
status_bus_cd,
status_bus_bd,
status_bus_ad,
status_bus_9d,
status_bus_8d};
assign status_bus_e = {status_bus_fe,
status_bus_ee,
status_bus_de,
status_bus_ce,
status_bus_be,
status_bus_ae,
status_bus_9e,
status_bus_8e};
assign status_bus_f = {status_bus_ff,
status_bus_ef,
status_bus_df,
status_bus_cf,
status_bus_bf,
status_bus_af,
status_bus_9f,
status_bus_8f};
genvar i;
generate
for(i=0;i<8;i=i+1) begin:status_gen
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_sel_0[i*32+31:i*32] <= 32'b0;
else if(uart_read_req_inv)
begin
case(uart_read_addr[0])
1'b0: status_bus_sel_0[i*32+31:i*32] <= status_bus_0[i*32+31:i*32];
1'b1: status_bus_sel_0[i*32+31:i*32] <= status_bus_1[i*32+31:i*32];
default : status_bus_sel_0[i*32+31:i*32] <= 32'b0;
endcase
end
else;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_sel_1[i*32+31:i*32] <= 32'b0;
else if(uart_read_req_inv)
begin
case(uart_read_addr[0])
1'b0: status_bus_sel_1[i*32+31:i*32] <= status_bus_2[i*32+31:i*32];
1'b1: status_bus_sel_1[i*32+31:i*32] <= status_bus_3[i*32+31:i*32];
default : status_bus_sel_1[i*32+31:i*32] <= 32'b0;
endcase
end
else;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_sel_2[i*32+31:i*32] <= 32'b0;
else if(uart_read_req_inv)
begin
case(uart_read_addr[0])
1'b0: status_bus_sel_2[i*32+31:i*32] <= status_bus_4[i*32+31:i*32];
1'b1: status_bus_sel_2[i*32+31:i*32] <= status_bus_5[i*32+31:i*32];
default : status_bus_sel_2[i*32+31:i*32] <= 32'b0;
endcase
end
else;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_sel_3[i*32+31:i*32] <= 32'b0;
else if(uart_read_req_inv)
begin
case(uart_read_addr[0])
1'b0: status_bus_sel_3[i*32+31:i*32] <= status_bus_6[i*32+31:i*32];
1'b1: status_bus_sel_3[i*32+31:i*32] <= status_bus_7[i*32+31:i*32];
default : status_bus_sel_3[i*32+31:i*32] <= 32'b0;
endcase
end
else;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_sel_4[i*32+31:i*32] <= 32'b0;
else if(uart_read_req_inv)
begin
case(uart_read_addr[0])
1'b0: status_bus_sel_4[i*32+31:i*32] <= status_bus_8[i*32+31:i*32];
1'b1: status_bus_sel_4[i*32+31:i*32] <= status_bus_9[i*32+31:i*32];
default : status_bus_sel_4[i*32+31:i*32] <= 32'b0;
endcase
end
else;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_sel_5[i*32+31:i*32] <= 32'b0;
else if(uart_read_req_inv)
begin
case(uart_read_addr[0])
1'b0: status_bus_sel_5[i*32+31:i*32] <= status_bus_a[i*32+31:i*32];
1'b1: status_bus_sel_5[i*32+31:i*32] <= status_bus_b[i*32+31:i*32];
default : status_bus_sel_5[i*32+31:i*32] <= 32'b0;
endcase
end
else;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_sel_6[i*32+31:i*32] <= 32'b0;
else if(uart_read_req_inv)
begin
case(uart_read_addr[0])
1'b0: status_bus_sel_6[i*32+31:i*32] <= status_bus_c[i*32+31:i*32];
1'b1: status_bus_sel_6[i*32+31:i*32] <= status_bus_d[i*32+31:i*32];
default : status_bus_sel_6[i*32+31:i*32] <= 32'b0;
endcase
end
else;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_sel_7[i*32+31:i*32] <= 32'b0;
else if(uart_read_req_inv)
begin
case(uart_read_addr[0])
1'b0: status_bus_sel_7[i*32+31:i*32] <= status_bus_e[i*32+31:i*32];
1'b1: status_bus_sel_7[i*32+31:i*32] <= status_bus_f[i*32+31:i*32];
default : status_bus_sel_7[i*32+31:i*32] <= 32'b0;
endcase
end
else;
end
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_sel[i*32+31:i*32] <= 32'b0;
else if(uart_read_req_inv_d1)
begin
case(uart_read_addr[3:1])
3'h0: status_bus_sel[i*32+31:i*32] <= status_bus_sel_0[i*32+31:i*32];
3'h1: status_bus_sel[i*32+31:i*32] <= status_bus_sel_1[i*32+31:i*32];
3'h2: status_bus_sel[i*32+31:i*32] <= status_bus_sel_2[i*32+31:i*32];
3'h3: status_bus_sel[i*32+31:i*32] <= status_bus_sel_3[i*32+31:i*32];
3'h4: status_bus_sel[i*32+31:i*32] <= status_bus_sel_4[i*32+31:i*32];
3'h5: status_bus_sel[i*32+31:i*32] <= status_bus_sel_5[i*32+31:i*32];
3'h6: status_bus_sel[i*32+31:i*32] <= status_bus_sel_6[i*32+31:i*32];
3'h7: status_bus_sel[i*32+31:i*32] <= status_bus_sel_7[i*32+31:i*32];
default : status_bus_sel[i*32+31:i*32] <= 32'b0;
endcase
end
else;
end
end
endgenerate
always @(posedge core_clk or negedge core_rst_n)
begin
if(!core_rst_n)
status_bus_lock <= 32'b0;
else if(uart_read_req_inv_d2)
begin
case(uart_read_addr[8:4])
5'h08: status_bus_lock <= status_bus_sel[32*0 +: 32];
5'h09: status_bus_lock <= status_bus_sel[32*1 +: 32];
5'h0a: status_bus_lock <= status_bus_sel[32*2 +: 32];
5'h0b: status_bus_lock <= status_bus_sel[32*3 +: 32];
5'h0c: status_bus_lock <= status_bus_sel[32*4 +: 32];
5'h0d: status_bus_lock <= status_bus_sel[32*5 +: 32];
5'h0e: status_bus_lock <= status_bus_sel[32*6 +: 32];
5'h0f: status_bus_lock <= status_bus_sel[32*7 +: 32];
default : status_bus_lock <= 32'b0;
endcase
end
else;
end
endmodule |
module test_ddr #(
parameter MEM_ROW_ADDR_WIDTH = 15 ,
parameter MEM_COL_ADDR_WIDTH = 10 ,
parameter MEM_BADDR_WIDTH = 3 ,
parameter MEM_DQ_WIDTH = 32 ,
parameter MEM_DM_WIDTH = MEM_DQ_WIDTH/8,
parameter MEM_DQS_WIDTH = MEM_DQ_WIDTH/8,
parameter CTRL_ADDR_WIDTH = MEM_ROW_ADDR_WIDTH + MEM_BADDR_WIDTH + MEM_COL_ADDR_WIDTH
)(
input ref_clk ,
input free_clk ,
input rst_board ,
output pll_lock ,
output ddr_init_done ,
//uart
input uart_rxd ,
output uart_txd ,
output mem_rst_n ,
output mem_ck ,
output mem_ck_n ,
output mem_cke ,
output mem_cs_n ,
output mem_ras_n ,
output mem_cas_n ,
output mem_we_n ,
output mem_odt ,
output [MEM_ROW_ADDR_WIDTH-1:0] mem_a ,
output [MEM_BADDR_WIDTH-1:0] mem_ba ,
inout [MEM_DQS_WIDTH-1:0] mem_dqs ,
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n ,
inout [MEM_DQ_WIDTH-1:0] mem_dq ,
output [MEM_DM_WIDTH-1:0] mem_dm ,
output reg heart_beat_led ,
output err_flag_led
);
parameter TH_1S = 27'd50_000_000;
parameter TH_4MS = 27'd200_000;
parameter REM_DQS_WIDTH = 4 - MEM_DQS_WIDTH;
wire core_clk_rst_n ;
wire free_clk_rst_n ;
wire core_clk ;
wire free_clk_g ;
wire [CTRL_ADDR_WIDTH-1:0] axi_awaddr ;
wire axi_awuser_ap ;
wire [3:0] axi_awuser_id ;
wire [3:0] axi_awlen ;
wire axi_awready ;
wire axi_awvalid ;
wire [MEM_DQ_WIDTH*8-1:0] axi_wdata ;
wire [MEM_DQ_WIDTH*8/8-1:0] axi_wstrb ;
wire axi_wready ;
wire [CTRL_ADDR_WIDTH-1:0] axi_araddr ;
wire axi_aruser_ap ;
wire [3:0] axi_aruser_id ;
wire [3:0] axi_arlen ;
wire axi_arready ;
wire axi_arvalid ;
wire [MEM_DQ_WIDTH*8-1:0] axi_rdata ;
wire axi_rvalid ;
wire resetn ;
reg [26:0] cnt ;
wire [7:0] ck_dly_set_bin ;
wire force_ck_dly_en ;
wire [7:0] force_ck_dly_set_bin ;
wire [7:0] dll_step ;
wire dll_lock ;
wire [1:0] init_read_clk_ctrl ;
wire [3:0] init_slip_step ;
wire force_read_clk_ctrl ;
wire ddrphy_gate_update_en ;
wire [34*MEM_DQS_WIDTH-1:0] debug_data ;
wire [13*MEM_DQS_WIDTH-1:0] debug_slice_state ;
wire [34*4-1:0] status_debug_data ;
wire [13*4-1:0 ] status_debug_slice_state ;
wire rd_fake_stop ;
wire bist_run_led ;
//***********************************************************************************
//uart ctrl
wire [31:0] ctrl_bus_0 ;
wire [31:0] ctrl_bus_1 ;
wire [31:0] ctrl_bus_2 ;
wire [31:0] ctrl_bus_3 ;
wire [31:0] ctrl_bus_4 ;
wire [31:0] ctrl_bus_5 ;
wire [31:0] ctrl_bus_6 ;
wire [31:0] ctrl_bus_7 ;
wire [31:0] ctrl_bus_8 ;
wire [31:0] ctrl_bus_9 ;
wire [31:0] ctrl_bus_10 ;
wire [31:0] ctrl_bus_11 ;
wire [31:0] ctrl_bus_12 ;
wire [31:0] ctrl_bus_13 ;
wire [31:0] ctrl_bus_14 ;
wire [31:0] ctrl_bus_15 ;
wire [31:0] status_bus_80 ;
wire [31:0] status_bus_81 ;
wire [31:0] status_bus_82 ;
wire [31:0] status_bus_83 ;
wire [31:0] status_bus_84 ;
wire [31:0] status_bus_85 ;
wire [31:0] status_bus_86 ;
wire [31:0] status_bus_87 ;
wire [31:0] status_bus_88 ;
wire [31:0] status_bus_89 ;
wire [31:0] status_bus_8a ;
wire [31:0] status_bus_8b ;
wire [31:0] status_bus_8c ;
wire [31:0] status_bus_8d ;
wire [31:0] status_bus_8e ;
wire [31:0] status_bus_8f ;
wire [31:0] status_bus_90 ;
wire [31:0] status_bus_91 ;
wire [31:0] status_bus_92 ;
wire [31:0] status_bus_93 ;
wire [31:0] status_bus_94 ;
wire [31:0] status_bus_95 ;
wire [31:0] status_bus_96 ;
wire [31:0] status_bus_97 ;
wire [31:0] status_bus_98 ;
wire [31:0] status_bus_99 ;
wire [31:0] status_bus_9a ;
wire [31:0] status_bus_9b ;
wire [31:0] status_bus_9c ;
wire [31:0] status_bus_9d ;
wire [31:0] status_bus_9e ;
wire [31:0] status_bus_9f ;
wire [31:0] status_bus_a0 ;
wire [31:0] status_bus_a1 ;
wire [31:0] status_bus_a2 ;
wire [31:0] status_bus_a3 ;
wire [31:0] status_bus_a4 ;
wire [31:0] status_bus_a5 ;
wire [31:0] status_bus_a6 ;
wire [31:0] status_bus_a7 ;
wire [31:0] status_bus_a8 ;
wire [31:0] status_bus_a9 ;
wire [31:0] status_bus_aa ;
wire [31:0] status_bus_ab ;
wire [31:0] status_bus_ac ;
wire [31:0] status_bus_ad ;
wire [31:0] status_bus_ae ;
wire [31:0] status_bus_af ;
wire [31:0] status_bus_b0 ;
wire [31:0] status_bus_b1 ;
wire [31:0] status_bus_b2 ;
wire [31:0] status_bus_b3 ;
wire [31:0] status_bus_b4 ;
wire [31:0] status_bus_b5 ;
wire [31:0] status_bus_b6 ;
wire [31:0] status_bus_b7 ;
wire [31:0] status_bus_b8 ;
wire [31:0] status_bus_b9 ;
wire [31:0] status_bus_ba ;
wire [31:0] status_bus_bb ;
wire [31:0] status_bus_bc ;
wire [31:0] status_bus_bd ;
wire [31:0] status_bus_be ;
wire [31:0] status_bus_bf ;
wire [31:0] status_bus_c0 ;
wire [31:0] status_bus_c1 ;
wire [31:0] status_bus_c2 ;
wire [31:0] status_bus_c3 ;
wire [31:0] status_bus_c4 ;
wire [31:0] status_bus_c5 ;
wire [31:0] status_bus_c6 ;
wire [31:0] status_bus_c7 ;
wire [31:0] status_bus_c8 ;
wire [31:0] status_bus_c9 ;
wire [31:0] status_bus_ca ;
wire [31:0] status_bus_cb ;
wire [31:0] status_bus_cc ;
wire [31:0] status_bus_cd ;
wire [31:0] status_bus_ce ;
wire [31:0] status_bus_cf ;
wire [31:0] status_bus_d0 ;
wire [31:0] status_bus_d1 ;
wire [31:0] status_bus_d2 ;
wire [31:0] status_bus_d3 ;
wire [31:0] status_bus_d4 ;
wire [31:0] status_bus_d5 ;
wire [31:0] status_bus_d6 ;
wire [31:0] status_bus_d7 ;
wire [31:0] status_bus_d8 ;
wire [31:0] status_bus_d9 ;
wire [31:0] status_bus_da ;
wire [31:0] status_bus_db ;
wire [31:0] status_bus_dc ;
wire [31:0] status_bus_dd ;
wire [31:0] status_bus_de ;
wire [31:0] status_bus_df ;
wire [31:0] status_bus_e0 ;
wire [31:0] status_bus_e1 ;
wire [31:0] status_bus_e2 ;
wire [31:0] status_bus_e3 ;
wire [31:0] status_bus_e4 ;
wire [31:0] status_bus_e5 ;
wire [31:0] status_bus_e6 ;
wire [31:0] status_bus_e7 ;
wire [31:0] status_bus_e8 ;
wire [31:0] status_bus_e9 ;
wire [31:0] status_bus_ea ;
wire [31:0] status_bus_eb ;
wire [31:0] status_bus_ec ;
wire [31:0] status_bus_ed ;
wire [31:0] status_bus_ee ;
wire [31:0] status_bus_ef ;
wire [31:0] status_bus_f0 ;
wire [31:0] status_bus_f1 ;
wire [31:0] status_bus_f2 ;
wire [31:0] status_bus_f3 ;
wire [31:0] status_bus_f4 ;
wire [31:0] status_bus_f5 ;
wire [31:0] status_bus_f6 ;
wire [31:0] status_bus_f7 ;
wire [31:0] status_bus_f8 ;
wire [31:0] status_bus_f9 ;
wire [31:0] status_bus_fa ;
wire [31:0] status_bus_fb ;
wire [31:0] status_bus_fc ;
wire [31:0] status_bus_fd ;
wire [31:0] status_bus_fe ;
wire [31:0] status_bus_ff ;
wire [31:0] status_bus_lock ;
wire uart_read_req ;
wire uart_read_ack ;
wire [8:0] uart_read_addr ;
wire debug_ddr_rst_n ;
wire [7:0] err_cnt ;
wire [3:0] test_main_state ;
wire [2:0] test_wr_state ;
wire [2:0] test_rd_state ;
wire [21:0] debug_calib_ctrl ;
wire manu_clear ;
wire [15:0] result_bit_out ;
wire [1:0] wr_mode ;
wire [1:0] data_mode ;
wire data_order ;
wire insert_err ;
wire [7:0] dq_inversion ;
wire bist_stop ;
wire len_random_en ;
wire [3:0] fix_axi_len ;
wire [3:0] read_repeat_num ;
wire [MEM_DQ_WIDTH*8-1:0] err_data_out ;
wire [MEM_DQ_WIDTH*8-1:0] err_flag_out ;
wire [MEM_DQ_WIDTH*8-1:0] exp_data_out ;
wire next_err_flag ;
wire [MEM_DQ_WIDTH*8-1:0] next_err_data ;
wire [MEM_DQ_WIDTH*8-1:0] err_data_pre ;
wire [MEM_DQ_WIDTH*8-1:0] err_data_aft ;
wire [32*8-1:0] status_err_data_out ;
wire [32*8-1:0] status_err_flag_out ;
wire [32*8-1:0] status_exp_data_out ;
wire [32*8-1:0] status_next_err_data ;
wire [32*8-1:0] status_err_data_pre ;
wire [32*8-1:0] status_err_data_aft ;
wire [MEM_DQS_WIDTH-1:0] update_com_val_err_flag ;
wire [3:0] status_com_val_err_flag ;
//control bus 0
parameter DFT_CTRL_BUS_0 = 32'h00_00_00_01;
assign debug_ddr_rst_n = ctrl_bus_0[0];
//control bus 1
parameter DFT_CTRL_BUS_1 = 32'h00_00_00_00;
assign manu_clear = ctrl_bus_1[1];
//control bus 2
parameter DFT_CTRL_BUS_2 = 32'h00_00_00_00;
assign wr_mode = ctrl_bus_2[1:0];
assign data_mode = ctrl_bus_2[5:4];
assign data_order = ctrl_bus_2[8];
assign insert_err = ctrl_bus_2[12];
assign dq_inversion = ctrl_bus_2[23:16];
assign bist_stop = ctrl_bus_2[24];
//control bus 3
parameter DFT_CTRL_BUS_3 = 32'h00_00_00_00;
assign force_read_clk_ctrl = ctrl_bus_3[0];
assign init_slip_step = ctrl_bus_3[7:4];
assign init_read_clk_ctrl = ctrl_bus_3[9:8];
//control bus 4
parameter DFT_CTRL_BUS_4 = 32'h00_00_03_01;
assign len_random_en = ctrl_bus_4[0];
assign fix_axi_len = ctrl_bus_4[7:4];
assign read_repeat_num = ctrl_bus_4[11:8];
//control bus 5
parameter DFT_CTRL_BUS_5 = 32'h00_00_00_01;
assign ddrphy_gate_update_en = ctrl_bus_5[0];
assign rd_fake_stop = ctrl_bus_5[4];
//control bus 6
parameter DFT_CTRL_BUS_6 = 32'h00_00_00_00;
//control bus 7
parameter DFT_CTRL_BUS_7 = 32'h00_00_00_00;
//control bus 8
parameter DFT_CTRL_BUS_8 = 32'h00_00_00_00;
//control bus 9
parameter DFT_CTRL_BUS_9 = 32'h00_00_00_00;
//control bus 10
parameter DFT_CTRL_BUS_10 = 32'h00_00_00_00;
//control bus 11
parameter DFT_CTRL_BUS_11 = 32'h00_00_00_00;
//control bus 12
parameter DFT_CTRL_BUS_12 = 32'h00_00_00_00;
//control bus 13
parameter DFT_CTRL_BUS_13 = 32'h00_00_00_00;
//control bus 14
parameter DFT_CTRL_BUS_14 = 32'h00_00_00_00;
//control bus 15
parameter DFT_CTRL_BUS_15 = 32'h00_00_01_40;
assign force_ck_dly_en = ctrl_bus_15[0];
assign force_ck_dly_set_bin = ctrl_bus_15[11:4];
assign status_debug_slice_state = {{13*REM_DQS_WIDTH{1'b0}},debug_slice_state };
assign status_debug_data = {{34*REM_DQS_WIDTH{1'b0}},debug_data };
assign status_err_flag_out = {{64*REM_DQS_WIDTH{1'b0}},err_flag_out };
assign status_err_data_out = {{64*REM_DQS_WIDTH{1'b0}},err_data_out };
assign status_exp_data_out = {{64*REM_DQS_WIDTH{1'b0}},exp_data_out };
assign status_next_err_data = {{64*REM_DQS_WIDTH{1'b0}},next_err_data };
assign status_err_data_pre = {{64*REM_DQS_WIDTH{1'b0}},err_data_pre };
assign status_err_data_aft = {{64*REM_DQS_WIDTH{1'b0}},err_data_aft };
assign status_com_val_err_flag = {{REM_DQS_WIDTH{1'b0}},update_com_val_err_flag};
//status
assign status_bus_80 = {15'b0,heart_beat_led,3'b0,ddr_init_done,3'b0,dll_lock,3'b0,pll_lock,3'b0,err_flag_led};
assign status_bus_81 = {10'b0,debug_calib_ctrl};
assign status_bus_82 = {15'b0,ck_dly_set_bin,next_err_flag,dll_step};
assign status_bus_83 = 32'b0;
assign status_bus_84 = 32'b0;
assign status_bus_85 = 32'b0;
assign status_bus_86 = 32'b0;
assign status_bus_87 = 32'b0;
assign status_bus_88 = 32'b0;
assign status_bus_89 = 32'b0;
assign status_bus_8a = 32'b0;
assign status_bus_8b = {14'b0,test_rd_state,test_wr_state,test_main_state,err_cnt};
assign status_bus_8c = 32'b0;
assign status_bus_8d = 32'b0;
assign status_bus_8e = 32'b0;
assign status_bus_8f = 32'b0;
assign status_bus_90 = status_debug_data[32*0 +: 32];
assign status_bus_91 = status_debug_data[32*1 +: 32];
assign status_bus_92 = status_debug_data[32*2 +: 32];
assign status_bus_93 = status_debug_data[32*3 +: 32];
assign status_bus_94 = {24'b0,status_debug_data[32*4 +: 8]};
assign status_bus_95 = 32'b0;
assign status_bus_96 = 32'b0;
assign status_bus_97 = 32'b0;
assign status_bus_98 = 32'b0;
assign status_bus_99 = status_debug_slice_state[32*0 +: 32];
assign status_bus_9a = {12'b0,status_debug_slice_state[32*1 +: 20]};
assign status_bus_9b = 32'b0;
assign status_bus_9c = 32'b0;
assign status_bus_9d = status_err_flag_out[32*0 +: 32];
assign status_bus_9e = status_err_flag_out[32*1 +: 32];
assign status_bus_9f = status_err_flag_out[32*2 +: 32];
assign status_bus_a0 = status_err_flag_out[32*3 +: 32];
assign status_bus_a1 = status_err_flag_out[32*4 +: 32];
assign status_bus_a2 = status_err_flag_out[32*5 +: 32];
assign status_bus_a3 = status_err_flag_out[32*6 +: 32];
assign status_bus_a4 = status_err_flag_out[32*7 +: 32];
assign status_bus_a5 = 32'b0;
assign status_bus_a6 = 32'b0;
assign status_bus_a7 = 32'b0;
assign status_bus_a8 = 32'b0;
assign status_bus_a9 = 32'b0;
assign status_bus_aa = 32'b0;
assign status_bus_ab = 32'b0;
assign status_bus_ac = 32'b0;
assign status_bus_ad = status_err_data_out[32*0 +: 32];
assign status_bus_ae = status_err_data_out[32*1 +: 32];
assign status_bus_af = status_err_data_out[32*2 +: 32];
assign status_bus_b0 = status_err_data_out[32*3 +: 32];
assign status_bus_b1 = status_err_data_out[32*4 +: 32];
assign status_bus_b2 = status_err_data_out[32*5 +: 32];
assign status_bus_b3 = status_err_data_out[32*6 +: 32];
assign status_bus_b4 = status_err_data_out[32*7 +: 32];
assign status_bus_b5 = 32'b0;
assign status_bus_b6 = 32'b0;
assign status_bus_b7 = 32'b0;
assign status_bus_b8 = 32'b0;
assign status_bus_b9 = 32'b0;
assign status_bus_ba = 32'b0;
assign status_bus_bb = 32'b0;
assign status_bus_bc = 32'b0;
assign status_bus_bd = status_exp_data_out[32*0 +: 32];
assign status_bus_be = status_exp_data_out[32*1 +: 32];
assign status_bus_bf = status_exp_data_out[32*2 +: 32];
assign status_bus_c0 = status_exp_data_out[32*3 +: 32];
assign status_bus_c1 = status_exp_data_out[32*4 +: 32];
assign status_bus_c2 = status_exp_data_out[32*5 +: 32];
assign status_bus_c3 = status_exp_data_out[32*6 +: 32];
assign status_bus_c4 = status_exp_data_out[32*7 +: 32];
assign status_bus_c5 = 32'b0;
assign status_bus_c6 = 32'b0;
assign status_bus_c7 = 32'b0;
assign status_bus_c8 = 32'b0;
assign status_bus_c9 = 32'b0;
assign status_bus_ca = 32'b0;
assign status_bus_cb = 32'b0;
assign status_bus_cc = 32'b0;
assign status_bus_cd = status_err_data_pre[32*0 +: 32];
assign status_bus_ce = status_err_data_pre[32*1 +: 32];
assign status_bus_cf = status_err_data_pre[32*2 +: 32];
assign status_bus_d0 = status_err_data_pre[32*3 +: 32];
assign status_bus_d1 = status_err_data_pre[32*4 +: 32];
assign status_bus_d2 = status_err_data_pre[32*5 +: 32];
assign status_bus_d3 = status_err_data_pre[32*6 +: 32];
assign status_bus_d4 = status_err_data_pre[32*7 +: 32];
assign status_bus_d5 = 32'b0;
assign status_bus_d6 = 32'b0;
assign status_bus_d7 = 32'b0;
assign status_bus_d8 = 32'b0;
assign status_bus_d9 = 32'b0;
assign status_bus_da = 32'b0;
assign status_bus_db = 32'b0;
assign status_bus_dc = 32'b0;
assign status_bus_dd = status_err_data_aft[32*0 +: 32];
assign status_bus_de = status_err_data_aft[32*1 +: 32];
assign status_bus_df = status_err_data_aft[32*2 +: 32];
assign status_bus_e0 = status_err_data_aft[32*3 +: 32];
assign status_bus_e1 = status_err_data_aft[32*4 +: 32];
assign status_bus_e2 = status_err_data_aft[32*5 +: 32];
assign status_bus_e3 = status_err_data_aft[32*6 +: 32];
assign status_bus_e4 = status_err_data_aft[32*7 +: 32];
assign status_bus_e5 = 32'b0;
assign status_bus_e6 = 32'b0;
assign status_bus_e7 = 32'b0;
assign status_bus_e8 = 32'b0;
assign status_bus_e9 = 32'b0;
assign status_bus_ea = 32'b0;
assign status_bus_eb = 32'b0;
assign status_bus_ec = 32'b0;
assign status_bus_ed = status_next_err_data[32*0 +: 32];
assign status_bus_ee = status_next_err_data[32*1 +: 32];
assign status_bus_ef = status_next_err_data[32*2 +: 32];
assign status_bus_f0 = status_next_err_data[32*3 +: 32];
assign status_bus_f1 = status_next_err_data[32*4 +: 32];
assign status_bus_f2 = status_next_err_data[32*5 +: 32];
assign status_bus_f3 = status_next_err_data[32*6 +: 32];
assign status_bus_f4 = status_next_err_data[32*7 +: 32];
assign status_bus_f5 = 32'b0;
assign status_bus_f6 = 32'b0;
assign status_bus_f7 = 32'b0;
assign status_bus_f8 = 32'b0;
assign status_bus_f9 = 32'b0;
assign status_bus_fa = 32'b0;
assign status_bus_fb = 32'b0;
assign status_bus_fc = 32'b0;
assign status_bus_fd = {28'b0,status_com_val_err_flag};
assign status_bus_fe = 32'b0;
assign status_bus_ff = 32'b0;
GTP_CLKBUFG free_clk_ibufg
(
.CLKOUT (free_clk_g ),
.CLKIN (free_clk )
);
ipsxb_rst_sync_v1_1 u_free_clk_rstn_sync(
.clk (free_clk_g ),
.rst_n (rst_board ),
.sig_async (1'b1),
.sig_synced (free_clk_rst_n )
);
ipsxb_uart_ctrl_top_32bit # (
`ifdef IPS_DDR_SPEEDUP_SIM
.CLK_DIV_P (16'd18 ),
`else
.CLK_DIV_P (16'd72 ), //115200bps for 50MHz clk.
`endif
.DFT_CTRL_BUS_0 (DFT_CTRL_BUS_0 ),
.DFT_CTRL_BUS_1 (DFT_CTRL_BUS_1 ),
.DFT_CTRL_BUS_2 (DFT_CTRL_BUS_2 ),
.DFT_CTRL_BUS_3 (DFT_CTRL_BUS_3 ),
.DFT_CTRL_BUS_4 (DFT_CTRL_BUS_4 ),
.DFT_CTRL_BUS_5 (DFT_CTRL_BUS_5 ),
.DFT_CTRL_BUS_6 (DFT_CTRL_BUS_6 ),
.DFT_CTRL_BUS_7 (DFT_CTRL_BUS_7 ),
.DFT_CTRL_BUS_8 (DFT_CTRL_BUS_8 ),
.DFT_CTRL_BUS_9 (DFT_CTRL_BUS_9 ),
.DFT_CTRL_BUS_10 (DFT_CTRL_BUS_10 ),
.DFT_CTRL_BUS_11 (DFT_CTRL_BUS_11 ),
.DFT_CTRL_BUS_12 (DFT_CTRL_BUS_12 ),
.DFT_CTRL_BUS_13 (DFT_CTRL_BUS_13 ),
.DFT_CTRL_BUS_14 (DFT_CTRL_BUS_14 ),
.DFT_CTRL_BUS_15 (DFT_CTRL_BUS_15 )
) u_ipsxb_uart_ctrl (
.rst_n (free_clk_rst_n ),
.clk (free_clk_g ),
.txd (uart_txd ),
.rxd (uart_rxd ),
.read_req (uart_read_req ),
.read_ack (uart_read_ack ),
.uart_rd_addr (uart_read_addr ),
.ctrl_bus_0 (ctrl_bus_0 ),
.ctrl_bus_1 (ctrl_bus_1 ),
.ctrl_bus_2 (ctrl_bus_2 ),
.ctrl_bus_3 (ctrl_bus_3 ),
.ctrl_bus_4 (ctrl_bus_4 ),
.ctrl_bus_5 (ctrl_bus_5 ),
.ctrl_bus_6 (ctrl_bus_6 ),
.ctrl_bus_7 (ctrl_bus_7 ),
.ctrl_bus_8 (ctrl_bus_8 ),
.ctrl_bus_9 (ctrl_bus_9 ),
.ctrl_bus_10 (ctrl_bus_10 ),
.ctrl_bus_11 (ctrl_bus_11 ),
.ctrl_bus_12 (ctrl_bus_12 ),
.ctrl_bus_13 (ctrl_bus_13 ),
.ctrl_bus_14 (ctrl_bus_14 ),
.ctrl_bus_15 (ctrl_bus_15 ),
.status_bus (status_bus_lock )
);
uart_rd_lock u_uart_rd_lock
(
.core_clk (free_clk_g ),
.core_rst_n (free_clk_rst_n ),
.uart_read_req (uart_read_req ),
.uart_read_ack (uart_read_ack ),
.uart_read_addr (uart_read_addr ),
.status_bus_80 (status_bus_80 ),
.status_bus_81 (status_bus_81 ),
.status_bus_82 (status_bus_82 ),
.status_bus_83 (status_bus_83 ),
.status_bus_84 (status_bus_84 ),
.status_bus_85 (status_bus_85 ),
.status_bus_86 (status_bus_86 ),
.status_bus_87 (status_bus_87 ),
.status_bus_88 (status_bus_88 ),
.status_bus_89 (status_bus_89 ),
.status_bus_8a (status_bus_8a ),
.status_bus_8b (status_bus_8b ),
.status_bus_8c (status_bus_8c ),
.status_bus_8d (status_bus_8d ),
.status_bus_8e (status_bus_8e ),
.status_bus_8f (status_bus_8f ),
.status_bus_90 (status_bus_90 ),
.status_bus_91 (status_bus_91 ),
.status_bus_92 (status_bus_92 ),
.status_bus_93 (status_bus_93 ),
.status_bus_94 (status_bus_94 ),
.status_bus_95 (status_bus_95 ),
.status_bus_96 (status_bus_96 ),
.status_bus_97 (status_bus_97 ),
.status_bus_98 (status_bus_98 ),
.status_bus_99 (status_bus_99 ),
.status_bus_9a (status_bus_9a ),
.status_bus_9b (status_bus_9b ),
.status_bus_9c (status_bus_9c ),
.status_bus_9d (status_bus_9d ),
.status_bus_9e (status_bus_9e ),
.status_bus_9f (status_bus_9f ),
.status_bus_a0 (status_bus_a0 ),
.status_bus_a1 (status_bus_a1 ),
.status_bus_a2 (status_bus_a2 ),
.status_bus_a3 (status_bus_a3 ),
.status_bus_a4 (status_bus_a4 ),
.status_bus_a5 (status_bus_a5 ),
.status_bus_a6 (status_bus_a6 ),
.status_bus_a7 (status_bus_a7 ),
.status_bus_a8 (status_bus_a8 ),
.status_bus_a9 (status_bus_a9 ),
.status_bus_aa (status_bus_aa ),
.status_bus_ab (status_bus_ab ),
.status_bus_ac (status_bus_ac ),
.status_bus_ad (status_bus_ad ),
.status_bus_ae (status_bus_ae ),
.status_bus_af (status_bus_af ),
.status_bus_b0 (status_bus_b0 ),
.status_bus_b1 (status_bus_b1 ),
.status_bus_b2 (status_bus_b2 ),
.status_bus_b3 (status_bus_b3 ),
.status_bus_b4 (status_bus_b4 ),
.status_bus_b5 (status_bus_b5 ),
.status_bus_b6 (status_bus_b6 ),
.status_bus_b7 (status_bus_b7 ),
.status_bus_b8 (status_bus_b8 ),
.status_bus_b9 (status_bus_b9 ),
.status_bus_ba (status_bus_ba ),
.status_bus_bb (status_bus_bb ),
.status_bus_bc (status_bus_bc ),
.status_bus_bd (status_bus_bd ),
.status_bus_be (status_bus_be ),
.status_bus_bf (status_bus_bf ),
.status_bus_c0 (status_bus_c0 ),
.status_bus_c1 (status_bus_c1 ),
.status_bus_c2 (status_bus_c2 ),
.status_bus_c3 (status_bus_c3 ),
.status_bus_c4 (status_bus_c4 ),
.status_bus_c5 (status_bus_c5 ),
.status_bus_c6 (status_bus_c6 ),
.status_bus_c7 (status_bus_c7 ),
.status_bus_c8 (status_bus_c8 ),
.status_bus_c9 (status_bus_c9 ),
.status_bus_ca (status_bus_ca ),
.status_bus_cb (status_bus_cb ),
.status_bus_cc (status_bus_cc ),
.status_bus_cd (status_bus_cd ),
.status_bus_ce (status_bus_ce ),
.status_bus_cf (status_bus_cf ),
.status_bus_d0 (status_bus_d0 ),
.status_bus_d1 (status_bus_d1 ),
.status_bus_d2 (status_bus_d2 ),
.status_bus_d3 (status_bus_d3 ),
.status_bus_d4 (status_bus_d4 ),
.status_bus_d5 (status_bus_d5 ),
.status_bus_d6 (status_bus_d6 ),
.status_bus_d7 (status_bus_d7 ),
.status_bus_d8 (status_bus_d8 ),
.status_bus_d9 (status_bus_d9 ),
.status_bus_da (status_bus_da ),
.status_bus_db (status_bus_db ),
.status_bus_dc (status_bus_dc ),
.status_bus_dd (status_bus_dd ),
.status_bus_de (status_bus_de ),
.status_bus_df (status_bus_df ),
.status_bus_e0 (status_bus_e0 ),
.status_bus_e1 (status_bus_e1 ),
.status_bus_e2 (status_bus_e2 ),
.status_bus_e3 (status_bus_e3 ),
.status_bus_e4 (status_bus_e4 ),
.status_bus_e5 (status_bus_e5 ),
.status_bus_e6 (status_bus_e6 ),
.status_bus_e7 (status_bus_e7 ),
.status_bus_e8 (status_bus_e8 ),
.status_bus_e9 (status_bus_e9 ),
.status_bus_ea (status_bus_ea ),
.status_bus_eb (status_bus_eb ),
.status_bus_ec (status_bus_ec ),
.status_bus_ed (status_bus_ed ),
.status_bus_ee (status_bus_ee ),
.status_bus_ef (status_bus_ef ),
.status_bus_f0 (status_bus_f0 ),
.status_bus_f1 (status_bus_f1 ),
.status_bus_f2 (status_bus_f2 ),
.status_bus_f3 (status_bus_f3 ),
.status_bus_f4 (status_bus_f4 ),
.status_bus_f5 (status_bus_f5 ),
.status_bus_f6 (status_bus_f6 ),
.status_bus_f7 (status_bus_f7 ),
.status_bus_f8 (status_bus_f8 ),
.status_bus_f9 (status_bus_f9 ),
.status_bus_fa (status_bus_fa ),
.status_bus_fb (status_bus_fb ),
.status_bus_fc (status_bus_fc ),
.status_bus_fd (status_bus_fd ),
.status_bus_fe (status_bus_fe ),
.status_bus_ff (status_bus_ff ),
.status_bus_lock (status_bus_lock )
);
//***********************************************************************************
assign resetn = debug_ddr_rst_n & rst_board ;
//***********************************************************************************
`ifdef SIMULATION
parameter MEM_SPACE_AW = 13; //to reduce simulation time
`else
parameter MEM_SPACE_AW = CTRL_ADDR_WIDTH;
`endif
//***********************************************************************************
reg [2:0] rst_board_dly;
reg [26:0] cnt_rst ;
reg rst_board_rg = 1'b1;
always @(posedge ref_clk)
begin
rst_board_dly <= {rst_board_dly[1:0],rst_board};
end
always @(posedge ref_clk)
begin
if (!rst_board_dly[2] && rst_board_dly[1]) begin
cnt_rst <= 0;
rst_board_rg <= 1'b1;
end
else begin
if(!rst_board_dly[2])begin
if(cnt_rst == TH_4MS) begin
rst_board_rg <= 1'b0;
end
else begin
cnt_rst <= cnt_rst + 1'b1;
end
end
end
end
always@(posedge core_clk or negedge resetn)
begin
if (!resetn)
cnt <= 27'd0;
else if ( cnt >= TH_1S )
cnt <= 27'd0;
else
cnt <= cnt + 27'd1;
end
always @(posedge core_clk or negedge resetn)
begin
if (!resetn)
heart_beat_led <= 1'd1;
else if ( cnt >= TH_1S )
heart_beat_led <= ~heart_beat_led;
end
ipsxb_rst_sync_v1_1 u_core_clk_rst_sync(
.clk (core_clk ),
.rst_n (resetn ),
.sig_async (1'b1),
.sig_synced (core_clk_rst_n )
);
ddr_test #
(
//***************************************************************************
// The following parameters are Memory Feature
//***************************************************************************
.MEM_ROW_WIDTH (MEM_ROW_ADDR_WIDTH),
.MEM_COLUMN_WIDTH (MEM_COL_ADDR_WIDTH),
.MEM_BANK_WIDTH (MEM_BADDR_WIDTH ),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.MEM_DM_WIDTH (MEM_DM_WIDTH ),
.MEM_DQS_WIDTH (MEM_DQS_WIDTH ),
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH )
)
I_ipsxb_ddr_top(
.ref_clk (ref_clk ),
.resetn (resetn ),
.ddr_init_done (ddr_init_done ),
.ddrphy_clkin (core_clk ),
.pll_lock (pll_lock ),
.axi_awaddr (axi_awaddr ),
.axi_awuser_ap (axi_awuser_ap ),
.axi_awuser_id (axi_awuser_id ),
.axi_awlen (axi_awlen ),
.axi_awready (axi_awready ),
.axi_awvalid (axi_awvalid ),
.axi_wdata (axi_wdata ),
.axi_wstrb (axi_wstrb ),
.axi_wready (axi_wready ),
.axi_wusero_id ( ),
.axi_wusero_last ( ),
.axi_araddr (axi_araddr ),
.axi_aruser_ap (axi_aruser_ap ),
.axi_aruser_id (axi_aruser_id ),
.axi_arlen (axi_arlen ),
.axi_arready (axi_arready ),
.axi_arvalid (axi_arvalid ),
.axi_rdata (axi_rdata ),
.axi_rid ( ),
.axi_rlast ( ),
.axi_rvalid (axi_rvalid ),
.apb_clk (1'b0 ),
.apb_rst_n (1'b0 ),
.apb_sel (1'b0 ),
.apb_enable (1'b0 ),
.apb_addr (8'd0 ),
.apb_write (1'b0 ),
.apb_ready ( ),
.apb_wdata (16'd0 ),
.apb_rdata ( ),
.apb_int ( ),
.debug_data (debug_data ),
.debug_slice_state (debug_slice_state ),
.debug_calib_ctrl (debug_calib_ctrl ),
.ck_dly_set_bin (ck_dly_set_bin ),
.force_ck_dly_en (force_ck_dly_en ),
.force_ck_dly_set_bin (force_ck_dly_set_bin ),
.dll_step (dll_step ),
.dll_lock (dll_lock ),
.init_read_clk_ctrl (init_read_clk_ctrl ),
.init_slip_step (init_slip_step ),
.force_read_clk_ctrl (force_read_clk_ctrl ),
.ddrphy_gate_update_en (ddrphy_gate_update_en ),
.update_com_val_err_flag (update_com_val_err_flag),
.rd_fake_stop (rd_fake_stop ),
.mem_rst_n (mem_rst_n ),
.mem_ck (mem_ck ),
.mem_ck_n (mem_ck_n ),
.mem_cke (mem_cke ),
.mem_cs_n (mem_cs_n ),
.mem_ras_n (mem_ras_n ),
.mem_cas_n (mem_cas_n ),
.mem_we_n (mem_we_n ),
.mem_odt (mem_odt ),
.mem_a (mem_a ),
.mem_ba (mem_ba ),
.mem_dqs (mem_dqs ),
.mem_dqs_n (mem_dqs_n ),
.mem_dq (mem_dq ),
.mem_dm (mem_dm )
);
//***********************************************************************************
axi_bist_top_v1_0 #(
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.MEM_SPACE_AW (MEM_SPACE_AW )
) u_bist_top (
.core_clk (core_clk ),
.core_clk_rst_n (core_clk_rst_n ),
.wr_mode (wr_mode ),
.data_mode (data_mode ),
.len_random_en (len_random_en ),
.fix_axi_len (fix_axi_len ),
.ddrc_init_done (ddr_init_done ),
.read_repeat_num (read_repeat_num ),
.bist_stop (bist_stop ),
.data_order (data_order ),
.dq_inversion (dq_inversion ),
.insert_err (insert_err ),
.manu_clear (manu_clear ),
.bist_run_led (bist_run_led ),
.test_main_state (test_main_state ),
.axi_awaddr (axi_awaddr ),
.axi_awuser_ap (axi_awuser_ap ),
.axi_awuser_id (axi_awuser_id ),
.axi_awlen (axi_awlen ),
.axi_awready (axi_awready ),
.axi_awvalid (axi_awvalid ),
.axi_wdata (axi_wdata ),
.axi_wstrb (axi_wstrb ),
.axi_wready (axi_wready ),
.test_wr_state (test_wr_state ),
.axi_araddr (axi_araddr ),
.axi_aruser_ap (axi_aruser_ap ),
.axi_aruser_id (axi_aruser_id ),
.axi_arlen (axi_arlen ),
.axi_arready (axi_arready ),
.axi_arvalid (axi_arvalid ),
.axi_rdata (axi_rdata ),
.axi_rvalid (axi_rvalid ),
.err_cnt (err_cnt ),
.err_flag_led (err_flag_led ),
.err_data_out (err_data_out ),
.err_flag_out (err_flag_out ),
.exp_data_out (exp_data_out ),
.next_err_flag (next_err_flag ),
.next_err_data (next_err_data ),
.err_data_pre (err_data_pre ),
.err_data_aft (err_data_aft ),
.result_bit_out (result_bit_out ),
.test_rd_state (test_rd_state )
);
endmodule |
module axi_bist_top_v1_0 #(
parameter DATA_MASK_EN = 0,
parameter CTRL_ADDR_WIDTH = 28,
parameter MEM_DQ_WIDTH = 16,
parameter MEM_SPACE_AW = 18,
parameter DATA_PATTERN0 = 8'h55,
parameter DATA_PATTERN1 = 8'haa,
parameter DATA_PATTERN2 = 8'h7f,
parameter DATA_PATTERN3 = 8'h80,
parameter DATA_PATTERN4 = 8'h55,
parameter DATA_PATTERN5 = 8'haa,
parameter DATA_PATTERN6 = 8'h7f,
parameter DATA_PATTERN7 = 8'h80
)(
input core_clk ,
input core_clk_rst_n ,
input [1:0] wr_mode ,
input [1:0] data_mode ,
input len_random_en ,
input [3:0] fix_axi_len ,
input bist_stop ,
input ddrc_init_done ,
input [3:0] read_repeat_num ,
input data_order ,
input [7:0] dq_inversion ,
input insert_err ,
input manu_clear ,
output bist_run_led ,
output [3:0] test_main_state ,
output [CTRL_ADDR_WIDTH-1:0] axi_awaddr ,
output axi_awuser_ap ,
output [3:0] axi_awuser_id ,
output [3:0] axi_awlen ,
input axi_awready ,
output axi_awvalid ,
output [MEM_DQ_WIDTH*8-1:0] axi_wdata ,
output [MEM_DQ_WIDTH*8/8-1:0] axi_wstrb ,
input axi_wready ,
output [2:0] test_wr_state ,
output [CTRL_ADDR_WIDTH-1:0] axi_araddr ,
output axi_aruser_ap ,
output [3:0] axi_aruser_id ,
output [3:0] axi_arlen ,
input axi_arready ,
output axi_arvalid ,
input [MEM_DQ_WIDTH*8-1:0] axi_rdata ,
input axi_rvalid ,
output [7:0] err_cnt ,
output err_flag_led ,
output [MEM_DQ_WIDTH*8-1:0] err_data_out ,
output [MEM_DQ_WIDTH*8-1:0] err_flag_out ,
output [MEM_DQ_WIDTH*8-1:0] exp_data_out ,
output next_err_flag,
output [15:0] result_bit_out,
output [2:0] test_rd_state,
output [MEM_DQ_WIDTH*8-1:0] next_err_data,
output [MEM_DQ_WIDTH*8-1:0] err_data_pre ,
output [MEM_DQ_WIDTH*8-1:0] err_data_aft
);
wire pattern_en ;
wire random_data_en;
wire read_repeat_en;
wire stress_test ;
wire write_to_read ;
wire [CTRL_ADDR_WIDTH-1:0] random_rw_addr;
wire [3:0] random_axi_id;
wire [3:0] random_axi_len;
wire random_axi_ap;
wire init_start ;
wire init_done ;
wire write_en ;
wire write_done_p ;
wire read_en ;
wire read_done_p ;
reg data_order_d0;
reg data_order_d1;
reg [7:0] dq_inversion_d0;
reg [7:0] dq_inversion_d1;
reg bist_stop_d0;
reg bist_stop_d1;
always @(posedge core_clk or negedge core_clk_rst_n)
begin
if (!core_clk_rst_n)begin
data_order_d0 <= 0;
data_order_d1 <= 0;
end
else begin
data_order_d0 <= data_order;
data_order_d1 <= data_order_d0;
end
end
always @(posedge core_clk or negedge core_clk_rst_n)
begin
if (!core_clk_rst_n)begin
dq_inversion_d0 <= 8'd0;
dq_inversion_d1 <= 8'd0;
end
else begin
dq_inversion_d0 <= dq_inversion;
dq_inversion_d1 <= dq_inversion_d0;
end
end
always @(posedge core_clk or negedge core_clk_rst_n)
begin
if (!core_clk_rst_n)begin
bist_stop_d0 <= 0;
bist_stop_d1 <= 0;
end
else begin
bist_stop_d0 <= bist_stop;
bist_stop_d1 <= bist_stop_d0;
end
end
test_main_ctrl_v1_0 #(
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH ),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.MEM_SPACE_AW (MEM_SPACE_AW )
) u_test_main_ctrl (
.clk (core_clk ),
.rst_n (core_clk_rst_n ),
.wr_mode (wr_mode ),
.data_mode (data_mode ),
.len_random_en (len_random_en ),
.fix_axi_len (fix_axi_len ),
.bist_stop (bist_stop_d1 ),
.random_rw_addr (random_rw_addr ),
.random_axi_id (random_axi_id ),
.random_axi_len (random_axi_len ),
.random_axi_ap (random_axi_ap ),
.pattern_en (pattern_en ),
.random_data_en (random_data_en ),
.read_repeat_en (read_repeat_en ),
.stress_test (stress_test ),
.write_to_read (write_to_read ),
.ddrc_init_done (ddrc_init_done ),
.init_start (init_start ),
.init_done (init_done ),
.write_en (write_en ),
.write_done_p (write_done_p ),
.read_en (read_en ),
.read_done_p (read_done_p ),
.bist_run_led (bist_run_led ),
.test_main_state (test_main_state )
);
test_wr_ctrl_v1_0 #(
.DATA_PATTERN0 (DATA_PATTERN0 ),
.DATA_PATTERN1 (DATA_PATTERN1 ),
.DATA_PATTERN2 (DATA_PATTERN2 ),
.DATA_PATTERN3 (DATA_PATTERN3 ),
.DATA_PATTERN4 (DATA_PATTERN4 ),
.DATA_PATTERN5 (DATA_PATTERN5 ),
.DATA_PATTERN6 (DATA_PATTERN6 ),
.DATA_PATTERN7 (DATA_PATTERN7 ),
.DATA_MASK_EN (DATA_MASK_EN ),
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH ),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.MEM_SPACE_AW (MEM_SPACE_AW )
) u_test_wr_ctrl (
.clk (core_clk ),
.rst_n (core_clk_rst_n ),
.init_start (init_start ),
.write_en (write_en ),
.write_done_p (write_done_p ),
.init_done (init_done ),
.insert_err (insert_err ),
.pattern_en (pattern_en ),
.random_data_en (random_data_en ),
.read_repeat_en (read_repeat_en ),
.stress_test (stress_test ),
.write_to_read (write_to_read ),
.data_order (data_order_d1 ),
.dq_inversion (dq_inversion_d1 ),
.random_rw_addr (random_rw_addr ),
.random_axi_id (random_axi_id ),
.random_axi_len (random_axi_len ),
.random_axi_ap (random_axi_ap ),
.axi_awaddr (axi_awaddr ),
.axi_awuser_ap (axi_awuser_ap ),
.axi_awuser_id (axi_awuser_id ),
.axi_awlen (axi_awlen ),
.axi_awready (axi_awready ),
.axi_awvalid (axi_awvalid ),
.axi_wdata (axi_wdata ),
.axi_wstrb (axi_wstrb ),
.axi_wready (axi_wready ),
.test_wr_state (test_wr_state )
);
test_rd_ctrl_v1_0 #(
.DATA_PATTERN0 (DATA_PATTERN0 ),
.DATA_PATTERN1 (DATA_PATTERN1 ),
.DATA_PATTERN2 (DATA_PATTERN2 ),
.DATA_PATTERN3 (DATA_PATTERN3 ),
.DATA_PATTERN4 (DATA_PATTERN4 ),
.DATA_PATTERN5 (DATA_PATTERN5 ),
.DATA_PATTERN6 (DATA_PATTERN6 ),
.DATA_PATTERN7 (DATA_PATTERN7 ),
.DATA_MASK_EN (DATA_MASK_EN ),
.CTRL_ADDR_WIDTH (CTRL_ADDR_WIDTH ),
.MEM_DQ_WIDTH (MEM_DQ_WIDTH ),
.MEM_SPACE_AW (MEM_SPACE_AW )
)u_test_rd_ctrl(
.clk (core_clk ),
.rst_n (core_clk_rst_n ),
.pattern_en (pattern_en ),
.random_data_en (random_data_en ),
.read_repeat_en (read_repeat_en ),
.read_repeat_num (read_repeat_num ),
.stress_test (stress_test ),
.write_to_read (write_to_read ),
.data_order (data_order_d1 ),
.dq_inversion (dq_inversion_d1 ),
.random_rw_addr (random_rw_addr ),
.random_axi_id (random_axi_id ),
.random_axi_len (random_axi_len ),
.random_axi_ap (random_axi_ap ),
.read_en (read_en ),
.read_done_p (read_done_p ),
.axi_araddr (axi_araddr ),
.axi_aruser_ap (axi_aruser_ap ),
.axi_aruser_id (axi_aruser_id ),
.axi_arlen (axi_arlen ),
.axi_arready (axi_arready ),
.axi_arvalid (axi_arvalid ),
.axi_rdata (axi_rdata ),
.axi_rvalid (axi_rvalid ),
.err_cnt (err_cnt ),
.err_flag_led (err_flag_led ),
.err_data_out (err_data_out ),
.err_flag_out (err_flag_out ),
.exp_data_out (exp_data_out ),
.manu_clear (manu_clear ),
.next_err_flag (next_err_flag ),
.result_bit_out (result_bit_out ),
.test_rd_state (test_rd_state ),
.next_err_data (next_err_data ),
.err_data_pre (err_data_pre ),
.err_data_aft (err_data_aft )
);
endmodule |
module ipsxb_seu_uart_tx(
input wire clk ,
input wire clk_en ,
input wire rst_n ,
input wire [31:0] tx_fifo_rd_data ,
input wire tx_fifo_rd_data_valid , // Transfer the data until tx_fifo is empty
output reg tx_fifo_rd_data_req ,
output reg txd
);
localparam IDLE = 2'b00;
localparam START = 2'b01;
localparam DATA = 2'b10;
localparam END = 2'b11;
reg [1:0] tx_cs ;
reg [1:0] tx_ns ;
reg [5:0] tx_data_cnt ;
wire data_end ;
reg [2:0] cnt ;
wire bit_en ; //5 div from clk_en
reg transmitting ;
wire [37:0] tx_frame_data ;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt <= 3'd0;
else if(~transmitting)
cnt <= 3'd0;
else if(clk_en)
begin
if(cnt == 3'd5)
cnt <= 3'd0;
else
cnt <= cnt + 3'd1;
end
else;
end
assign bit_en = (cnt == 3'd5) && clk_en;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
tx_cs <= IDLE;
else if(bit_en)
tx_cs <= tx_ns;
else;
end
always@(*)
begin
case(tx_cs)
IDLE: begin
if(transmitting)
tx_ns = START;
else
tx_ns = IDLE;
end
START: begin
tx_ns = DATA;
end
DATA: begin
if(data_end)
tx_ns = END;
else
tx_ns = DATA;
end
END: begin
if(transmitting && tx_fifo_rd_data_valid)
tx_ns = START;
else
tx_ns = IDLE;
end
default: begin
tx_ns = IDLE;
end
endcase
end
//read data from fifo ,once a time
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
transmitting <= 0;
else if(tx_fifo_rd_data_valid)
transmitting <= 1;
else if(~tx_fifo_rd_data_valid && (tx_cs == END) && bit_en)
transmitting <= 0;
else;
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
tx_fifo_rd_data_req <= 0;
else if(tx_fifo_rd_data_valid && transmitting && data_end && bit_en)
tx_fifo_rd_data_req <= 1;
else
tx_fifo_rd_data_req <= 0;
end
//tx data cnt
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
tx_data_cnt <= 6'd0;
else if(tx_cs == DATA)
if(bit_en)
tx_data_cnt <= tx_data_cnt + 6'd1;
else;
else
tx_data_cnt <= 6'd0;
end
assign data_end = tx_data_cnt == 6'd37;
assign tx_frame_data = {tx_fifo_rd_data[31:24],2'b01,tx_fifo_rd_data[23:16],2'b01,tx_fifo_rd_data[15:8],2'b01,tx_fifo_rd_data[7:0]};
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
txd <= 1'b1;
else if(tx_cs == START)
txd <= 1'b0;
else if(tx_cs == DATA)
txd <= tx_frame_data[tx_data_cnt];
else
txd <= 1'b1;
end
endmodule |
module ipsxb_ver_ctrl_32bit #(
parameter DFT_CTRL_BUS_0 = 32'h0000_0000,
parameter DFT_CTRL_BUS_1 = 32'h0000_0000,
parameter DFT_CTRL_BUS_2 = 32'h0000_0000,
parameter DFT_CTRL_BUS_3 = 32'h0000_0000,
parameter DFT_CTRL_BUS_4 = 32'h0000_0000,
parameter DFT_CTRL_BUS_5 = 32'h0000_0000,
parameter DFT_CTRL_BUS_6 = 32'h0000_0000,
parameter DFT_CTRL_BUS_7 = 32'h0000_0000,
parameter DFT_CTRL_BUS_8 = 32'h0000_0000,
parameter DFT_CTRL_BUS_9 = 32'h0000_0000,
parameter DFT_CTRL_BUS_10 = 32'h0000_0000,
parameter DFT_CTRL_BUS_11 = 32'h0000_0000,
parameter DFT_CTRL_BUS_12 = 32'h0000_0000,
parameter DFT_CTRL_BUS_13 = 32'h0000_0000,
parameter DFT_CTRL_BUS_14 = 32'h0000_0000,
parameter DFT_CTRL_BUS_15 = 32'h0000_0000
)(
input clk ,
input rst_n ,
input [8:0] addr ,
input [31:0] data ,
input we ,
input cmd_en ,
output reg cmd_done ,
output wire [31:0] fifo_data ,
input fifo_data_valid ,
output reg fifo_data_req ,
output reg read_req ,
input read_ack ,
output reg [31:0] ctrl_bus_0 ,
output reg [31:0] ctrl_bus_1 ,
output reg [31:0] ctrl_bus_2 ,
output reg [31:0] ctrl_bus_3 ,
output reg [31:0] ctrl_bus_4 ,
output reg [31:0] ctrl_bus_5 ,
output reg [31:0] ctrl_bus_6 ,
output reg [31:0] ctrl_bus_7 ,
output reg [31:0] ctrl_bus_8 ,
output reg [31:0] ctrl_bus_9 ,
output reg [31:0] ctrl_bus_10 ,
output reg [31:0] ctrl_bus_11 ,
output reg [31:0] ctrl_bus_12 ,
output reg [31:0] ctrl_bus_13 ,
output reg [31:0] ctrl_bus_14 ,
output reg [31:0] ctrl_bus_15 ,
input [31:0] status_bus
);
reg [31:0] rd_data ;
reg [1:0] clk_cnt ;
reg we_rg ;
wire clk_pos ;
wire [31:0] version_id;
reg read_ack_syn1;
reg read_ack_syn2;
reg read_ack_syn3;
reg read_ack_inv;
assign version_id = 32'h20200729;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
clk_cnt <= 2'd0;
else
clk_cnt <= clk_cnt + 2'd1;
end
assign clk_pos = clk_cnt == 2'd3;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
we_rg <= 1'b0;
else if(cmd_en && we)
we_rg <= 1'b1;
else if(clk_pos)
we_rg <= 1'b0;
else;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
ctrl_bus_0 <= DFT_CTRL_BUS_0;
ctrl_bus_1 <= DFT_CTRL_BUS_1;
ctrl_bus_2 <= DFT_CTRL_BUS_2;
ctrl_bus_3 <= DFT_CTRL_BUS_3;
ctrl_bus_4 <= DFT_CTRL_BUS_4;
ctrl_bus_5 <= DFT_CTRL_BUS_5;
ctrl_bus_6 <= DFT_CTRL_BUS_6;
ctrl_bus_7 <= DFT_CTRL_BUS_7;
ctrl_bus_8 <= DFT_CTRL_BUS_8;
ctrl_bus_9 <= DFT_CTRL_BUS_9;
ctrl_bus_10 <= DFT_CTRL_BUS_10;
ctrl_bus_11 <= DFT_CTRL_BUS_11;
ctrl_bus_12 <= DFT_CTRL_BUS_12;
ctrl_bus_13 <= DFT_CTRL_BUS_13;
ctrl_bus_14 <= DFT_CTRL_BUS_14;
ctrl_bus_15 <= DFT_CTRL_BUS_15;
end
else if(we_rg && clk_pos)
begin
case(addr)
9'h000: ctrl_bus_0 <= data;
9'h001: ctrl_bus_1 <= data;
9'h002: ctrl_bus_2 <= data;
9'h003: ctrl_bus_3 <= data;
9'h004: ctrl_bus_4 <= data;
9'h005: ctrl_bus_5 <= data;
9'h006: ctrl_bus_6 <= data;
9'h007: ctrl_bus_7 <= data;
9'h008: ctrl_bus_8 <= data;
9'h009: ctrl_bus_9 <= data;
9'h00a: ctrl_bus_10 <= data;
9'h00b: ctrl_bus_11 <= data;
9'h00c: ctrl_bus_12 <= data;
9'h00d: ctrl_bus_13 <= data;
9'h00e: ctrl_bus_14 <= data;
9'h00f: ctrl_bus_15 <= data;
default:;
endcase
end
else;
//else if(clk_pos)
//begin
// ctrl_bus_2[0] <= 1'b0;
//end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
read_req <= 1'b0;
else if(cmd_en && ~we)
read_req <= ~read_req;
else;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
read_ack_syn1 <= 1'b0;
read_ack_syn2 <= 1'b0;
read_ack_syn3 <= 1'b0;
read_ack_inv <= 1'b0;
end
else
begin
read_ack_syn1 <= read_ack;
read_ack_syn2 <= read_ack_syn1;
read_ack_syn3 <= read_ack_syn2;
read_ack_inv <= read_ack_syn3 ^ read_ack_syn2;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
rd_data <= 32'd0;
end
else if(read_ack_inv)
begin
case(addr)
9'h000: rd_data <= ctrl_bus_0;
9'h001: rd_data <= ctrl_bus_1;
9'h002: rd_data <= ctrl_bus_2;
9'h003: rd_data <= ctrl_bus_3;
9'h004: rd_data <= ctrl_bus_4;
9'h005: rd_data <= ctrl_bus_5;
9'h006: rd_data <= ctrl_bus_6;
9'h007: rd_data <= ctrl_bus_7;
9'h008: rd_data <= ctrl_bus_8;
9'h009: rd_data <= ctrl_bus_9;
9'h00a: rd_data <= ctrl_bus_10;
9'h00b: rd_data <= ctrl_bus_11;
9'h00c: rd_data <= ctrl_bus_12;
9'h00d: rd_data <= ctrl_bus_13;
9'h00e: rd_data <= ctrl_bus_14;
9'h00f: rd_data <= ctrl_bus_15;
9'h0ff: rd_data <= version_id;
default: rd_data <= status_bus;
endcase
end
else;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cmd_done <= 1'b0;
else if(read_ack_inv || (we_rg & clk_pos))
cmd_done <= 1'b1;
else
cmd_done <= 1'b0;
end
assign fifo_data = rd_data;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
fifo_data_req <= 1'b0;
else if(read_ack_inv & fifo_data_valid)
fifo_data_req <= 1'b1;
else
fifo_data_req <= 1'b0;
end
endmodule |
module ipsxb_cmd_parser_32bit(
input clk,
input rst_n,
input [7:0] fifo_data,
input fifo_data_valid,
output reg fifo_data_req,
output [23:0] addr,
output [31:0] data,
output we,
output cmd_en,
input cmd_done
);
localparam ST_IDLE = 4'd0;
localparam ST_W_ADDRL = 4'd1;
localparam ST_W_ADDRM = 4'd2;
localparam ST_W_ADDRH = 4'd3;
localparam ST_W_DATA_B0 = 4'd4;
localparam ST_W_DATA_B1 = 4'd5;
localparam ST_W_DATA_B2 = 4'd6;
localparam ST_W_DATA_B3 = 4'd7;
localparam ST_W_CMD = 4'd8;
localparam ST_WAIT = 4'd9;
localparam ST_R_ADDRL = 4'd10;
localparam ST_R_ADDRM = 4'd11;
localparam ST_R_ADDRH = 4'd12;
localparam ST_R_CMD = 4'd13;
localparam ASC_w = 8'h77;
localparam ASC_r = 8'h72;
reg [3:0] crt_st;
reg [3:0] nxt_st;
reg [7:0] addrl;
reg [7:0] addrm;
reg [7:0] addrh;
reg [7:0] data_b0;
reg [7:0] data_b1;
reg [7:0] data_b2;
reg [7:0] data_b3;
assign addr = {addrh,addrm,addrl};
assign data = {data_b3,data_b2,data_b1,data_b0};
assign we = crt_st == ST_W_CMD;
assign cmd_en = (crt_st == ST_W_CMD) | (crt_st == ST_R_CMD);
wire in_st_idle = crt_st == ST_IDLE;
wire in_st_w_addrl = crt_st == ST_W_ADDRL;
wire in_st_w_addrm = crt_st == ST_W_ADDRM;
wire in_st_w_addrh = crt_st == ST_W_ADDRH;
wire in_st_w_data_b0 = crt_st == ST_W_DATA_B0;
wire in_st_w_data_b1 = crt_st == ST_W_DATA_B1;
wire in_st_w_data_b2 = crt_st == ST_W_DATA_B2;
wire in_st_w_data_b3 = crt_st == ST_W_DATA_B3;
wire in_st_r_addrl = crt_st == ST_R_ADDRL;
wire in_st_r_addrm = crt_st == ST_R_ADDRM;
wire in_st_r_addrh = crt_st == ST_R_ADDRH;
wire wait_fifo_data = in_st_idle | in_st_w_addrl | in_st_w_addrm | in_st_w_addrh | in_st_w_data_b0 | in_st_w_data_b1 |
in_st_w_data_b2 | in_st_w_data_b3 | in_st_r_addrl | in_st_r_addrm | in_st_r_addrh;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
crt_st <= ST_IDLE;
else
crt_st <= nxt_st;
end
always @(*)
begin
nxt_st = crt_st;
case(crt_st)
ST_IDLE :
begin
if(fifo_data_valid)
begin
if(fifo_data == ASC_w)
nxt_st = ST_W_ADDRL;
else if(fifo_data == ASC_r)
nxt_st = ST_R_ADDRL;
else
nxt_st = crt_st;
end
else
nxt_st = crt_st;
end
ST_W_ADDRL :
begin
if(fifo_data_valid)
nxt_st = ST_W_ADDRM;
else
nxt_st = ST_W_ADDRL;
end
ST_W_ADDRM :
begin
if(fifo_data_valid)
nxt_st = ST_W_ADDRH;
else
nxt_st = ST_W_ADDRM;
end
ST_W_ADDRH :
begin
if(fifo_data_valid)
nxt_st = ST_W_DATA_B0;
else
nxt_st = crt_st;
end
ST_W_DATA_B0 :
begin
if(fifo_data_valid)
nxt_st = ST_W_DATA_B1;
else
nxt_st = crt_st;
end
ST_W_DATA_B1 :
begin
if(fifo_data_valid)
nxt_st = ST_W_DATA_B2;
else
nxt_st = crt_st;
end
ST_W_DATA_B2 :
begin
if(fifo_data_valid)
nxt_st = ST_W_DATA_B3;
else
nxt_st = crt_st;
end
ST_W_DATA_B3 :
begin
if(fifo_data_valid)
nxt_st = ST_W_CMD;
else
nxt_st = crt_st;
end
ST_W_CMD :
begin
nxt_st = ST_WAIT;
end
ST_WAIT :
begin
if(cmd_done)
nxt_st = ST_IDLE;
else
nxt_st = crt_st;
end
ST_R_ADDRL :
begin
if(fifo_data_valid)
nxt_st = ST_R_ADDRM;
else
nxt_st = crt_st;
end
ST_R_ADDRM :
begin
if(fifo_data_valid)
nxt_st = ST_R_ADDRH;
else
nxt_st = crt_st;
end
ST_R_ADDRH :
begin
if(fifo_data_valid)
nxt_st = ST_R_CMD;
else
nxt_st = crt_st;
end
ST_R_CMD :
begin
nxt_st = ST_WAIT;
end
default :
begin
nxt_st = ST_IDLE;
end
endcase
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
addrl <= 8'b0;
else if((in_st_w_addrl | in_st_r_addrl) && fifo_data_valid)
addrl <= fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
addrm <= 8'b0;
else if((in_st_w_addrm | in_st_r_addrm) && fifo_data_valid)
addrm <= fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
addrh <= 8'b0;
else if((in_st_w_addrh | in_st_r_addrh) && fifo_data_valid)
addrh <= fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
data_b0 <= 8'b0;
else if(in_st_w_data_b0 && fifo_data_valid)
data_b0 <= fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
data_b1 <= 8'b0;
else if(in_st_w_data_b1 && fifo_data_valid)
data_b1 <= fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
data_b2 <= 8'b0;
else if(in_st_w_data_b2 && fifo_data_valid)
data_b2 <= fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
data_b3 <= 8'b0;
else if(in_st_w_data_b3 && fifo_data_valid)
data_b3 <= fifo_data;
end
always @(*)
begin
if(wait_fifo_data && fifo_data_valid)
fifo_data_req = 1'b1;
else
fifo_data_req = 1'b0;
end
endmodule //pgr_cmd_parser |
module ipsxb_uart_ctrl_top_32bit
#(
parameter CLK_DIV_P = 16'd145 ,
parameter FIFO_D = 16 ,
parameter WORD_LEN = 2'b11 ,
parameter PARITY_EN = 1'b0 ,
parameter PARITY_TYPE = 1'b0 ,
parameter STOP_LEN = 1'b0 ,
parameter MODE = 1'b0 ,
parameter DFT_CTRL_BUS_0 = 32'h0000_0000,
parameter DFT_CTRL_BUS_1 = 32'h0000_0000,
parameter DFT_CTRL_BUS_2 = 32'h0000_0000,
parameter DFT_CTRL_BUS_3 = 32'h0000_0000,
parameter DFT_CTRL_BUS_4 = 32'h0000_0000,
parameter DFT_CTRL_BUS_5 = 32'h0000_0000,
parameter DFT_CTRL_BUS_6 = 32'h0000_0000,
parameter DFT_CTRL_BUS_7 = 32'h0000_0000,
parameter DFT_CTRL_BUS_8 = 32'h0000_0000,
parameter DFT_CTRL_BUS_9 = 32'h0000_0000,
parameter DFT_CTRL_BUS_10 = 32'h0000_0000,
parameter DFT_CTRL_BUS_11 = 32'h0000_0000,
parameter DFT_CTRL_BUS_12 = 32'h0000_0000,
parameter DFT_CTRL_BUS_13 = 32'h0000_0000,
parameter DFT_CTRL_BUS_14 = 32'h0000_0000,
parameter DFT_CTRL_BUS_15 = 32'h0000_0000
)
(
input clk ,
input rst_n ,
output txd ,
input rxd ,
output read_req ,
input read_ack ,
output [8:0] uart_rd_addr ,
output [31:0] ctrl_bus_0 ,
output [31:0] ctrl_bus_1 ,
output [31:0] ctrl_bus_2 ,
output [31:0] ctrl_bus_3 ,
output [31:0] ctrl_bus_4 ,
output [31:0] ctrl_bus_5 ,
output [31:0] ctrl_bus_6 ,
output [31:0] ctrl_bus_7 ,
output [31:0] ctrl_bus_8 ,
output [31:0] ctrl_bus_9 ,
output [31:0] ctrl_bus_10 ,
output [31:0] ctrl_bus_11 ,
output [31:0] ctrl_bus_12 ,
output [31:0] ctrl_bus_13 ,
output [31:0] ctrl_bus_14 ,
output [31:0] ctrl_bus_15 ,
input [31:0] status_bus
);
wire [31:0] tx_fifo_wr_data;
wire tx_fifo_wr_data_valid;
wire tx_fifo_wr_data_req;
wire [7:0] rx_fifo_rd_data;
wire rx_fifo_rd_data_valid;
wire rx_fifo_rd_data_req;
//ipsxb_uart_top_32bit
//#(
// .CLK_DIV_P (CLK_DIV_P ),
// .FIFO_D (FIFO_D ),
// .WORD_LEN (WORD_LEN ),
// .PARITY_EN (PARITY_EN ),
// .PARITY_TYPE (PARITY_TYPE ),
// .STOP_LEN (STOP_LEN ),
// .MODE (MODE )
//)
//u_uart_top(
// .clk (clk ),
// .rst_n (rst_n ),
//
// .tx_fifo_wr_data (tx_fifo_wr_data ),
// .tx_fifo_wr_data_valid (tx_fifo_wr_data_valid ),
// .tx_fifo_wr_data_req (tx_fifo_wr_data_req ),
//
// .rx_fifo_rd_data (rx_fifo_rd_data ),
// .rx_fifo_rd_data_valid (rx_fifo_rd_data_valid ),
// .rx_fifo_rd_data_req (rx_fifo_rd_data_req ),
//
// .txd (txd ),
// .rxd (rxd )
//);
ipsxb_seu_rs232_intf
#(
.CLK_DIV_P (CLK_DIV_P ),
.FIFO_D (FIFO_D )
)
u_uart_top
(
.clk (clk ),
.rst_n (rst_n ),
.tx_fifo_wr_data (tx_fifo_wr_data ),
.tx_fifo_wr_data_valid (tx_fifo_wr_data_valid ),
.tx_fifo_wr_data_req (tx_fifo_wr_data_req ),
.rx_fifo_rd_data (rx_fifo_rd_data ),
.rx_fifo_rd_data_valid (rx_fifo_rd_data_valid ),
.rx_fifo_rd_data_req (rx_fifo_rd_data_req ),
.txd (txd ),
.rxd (rxd )
);
ipsxb_uart_ctrl_32bit #(
.CLK_DIV_P (CLK_DIV_P ),
.DFT_CTRL_BUS_0 (DFT_CTRL_BUS_0 ),
.DFT_CTRL_BUS_1 (DFT_CTRL_BUS_1 ),
.DFT_CTRL_BUS_2 (DFT_CTRL_BUS_2 ),
.DFT_CTRL_BUS_3 (DFT_CTRL_BUS_3 ),
.DFT_CTRL_BUS_4 (DFT_CTRL_BUS_4 ),
.DFT_CTRL_BUS_5 (DFT_CTRL_BUS_5 ),
.DFT_CTRL_BUS_6 (DFT_CTRL_BUS_6 ),
.DFT_CTRL_BUS_7 (DFT_CTRL_BUS_7 ),
.DFT_CTRL_BUS_8 (DFT_CTRL_BUS_8 ),
.DFT_CTRL_BUS_9 (DFT_CTRL_BUS_9 ),
.DFT_CTRL_BUS_10 (DFT_CTRL_BUS_10 ),
.DFT_CTRL_BUS_11 (DFT_CTRL_BUS_11 ),
.DFT_CTRL_BUS_12 (DFT_CTRL_BUS_12 ),
.DFT_CTRL_BUS_13 (DFT_CTRL_BUS_13 ),
.DFT_CTRL_BUS_14 (DFT_CTRL_BUS_14 ),
.DFT_CTRL_BUS_15 (DFT_CTRL_BUS_15 )
) u_uart_ctrl(
.clk (clk ),
.rst_n (rst_n ),
.tx_fifo_wr_data (tx_fifo_wr_data ),
.tx_fifo_wr_data_valid (tx_fifo_wr_data_valid ),
.tx_fifo_wr_data_req (tx_fifo_wr_data_req ),
.rx_fifo_rd_data (rx_fifo_rd_data ),
.rx_fifo_rd_data_valid (rx_fifo_rd_data_valid ),
.rx_fifo_rd_data_req (rx_fifo_rd_data_req ),
.read_req (read_req ),
.read_ack (read_ack ),
.uart_rd_addr (uart_rd_addr ),
.ctrl_bus_0 (ctrl_bus_0 ),
.ctrl_bus_1 (ctrl_bus_1 ),
.ctrl_bus_2 (ctrl_bus_2 ),
.ctrl_bus_3 (ctrl_bus_3 ),
.ctrl_bus_4 (ctrl_bus_4 ),
.ctrl_bus_5 (ctrl_bus_5 ),
.ctrl_bus_6 (ctrl_bus_6 ),
.ctrl_bus_7 (ctrl_bus_7 ),
.ctrl_bus_8 (ctrl_bus_8 ),
.ctrl_bus_9 (ctrl_bus_9 ),
.ctrl_bus_10 (ctrl_bus_10 ),
.ctrl_bus_11 (ctrl_bus_11 ),
.ctrl_bus_12 (ctrl_bus_12 ),
.ctrl_bus_13 (ctrl_bus_13 ),
.ctrl_bus_14 (ctrl_bus_14 ),
.ctrl_bus_15 (ctrl_bus_15 ),
.status_bus (status_bus )
);
endmodule |
module ipsxb_seu_rs232_intf
#(
parameter CLK_DIV_P = 16'd145 ,
parameter FIFO_D = 1024
)
(
input clk ,
input rst_n ,
input [31:0] tx_fifo_wr_data,
output reg tx_fifo_wr_data_valid,
input tx_fifo_wr_data_req,
output [7:0] rx_fifo_rd_data ,
output rx_fifo_rd_data_valid ,
input rx_fifo_rd_data_req ,
output txd ,
input rxd
);
wire clk_en;
wire tx_fifo_rd_data_req;
wire [31:0] tx_fifo_rd_data;
wire tx_fifo_rd_data_valid;
wire rx_fifo_wr_data_req;
wire [7:0] rx_fifo_wr_data;
reg rx_fifo_wr_data_valid;
assign rx_fifo_rd_data = rx_fifo_wr_data;
assign rx_fifo_rd_data_valid = ~rx_fifo_wr_data_valid;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rx_fifo_wr_data_valid <= 1'b1;
else if(rx_fifo_wr_data_req)
rx_fifo_wr_data_valid <= 1'b0;
else if(rx_fifo_rd_data_req)
rx_fifo_wr_data_valid <= 1'b1;
else;
end
assign tx_fifo_rd_data = tx_fifo_wr_data;
assign tx_fifo_rd_data_valid = ~tx_fifo_wr_data_valid;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
tx_fifo_wr_data_valid <= 1'b1;
else if(tx_fifo_wr_data_req)
tx_fifo_wr_data_valid <= 1'b0;
else if(tx_fifo_rd_data_req)
tx_fifo_wr_data_valid <= 1'b1;
else;
end
ipsxb_clk_gen_32bit u_ipsxb_clk_gen(
.clk (clk ),
.rst_n (rst_n ),
.clk_div (CLK_DIV_P ),
.clk_en (clk_en )
);
ipsxb_seu_uart_tx u_ipsxb_seu_uart_tx(
.clk (clk ),
.clk_en (clk_en ),
.rst_n (rst_n ),
.tx_fifo_rd_data (tx_fifo_rd_data ),
.tx_fifo_rd_data_valid (tx_fifo_rd_data_valid ),
.tx_fifo_rd_data_req (tx_fifo_rd_data_req ),
.txd (txd )
);
ipsxb_seu_uart_rx u_ipsxb_seu_uart_rx(
.clk (clk ),
.rst_n (rst_n ),
.clk_en (clk_en ),
.rx_fifo_wr_data (rx_fifo_wr_data ),
.rx_fifo_wr_data_valid (rx_fifo_wr_data_valid ),
.rx_fifo_wr_data_req (rx_fifo_wr_data_req ),
.rxd_in (rxd )
);
endmodule |
module ipsxb_clk_gen_32bit(
input clk,
input rst_n,
input [15:0] clk_div,
output reg clk_en // divided from baud
);
reg [15:0] cnt;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt <= 16'b0;
else if(cnt == (clk_div - 16'd1))
cnt <= 16'b0;
else
cnt <= cnt + 16'b1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
clk_en <= 1'b0;
else
clk_en <= cnt == (clk_div - 16'd1);
end
endmodule //pgr_clk_gen |
module ipsxb_seu_uart_rx(
input clk ,
input rst_n ,
input clk_en ,
output reg [7:0] rx_fifo_wr_data ,
input rx_fifo_wr_data_valid ,
output wire rx_fifo_wr_data_req ,
input rxd_in
);
reg [1:0] rxd_d ;
reg [2:0] rxd_tmp ;
reg rxd_r1 ;
reg rxd_r2 ;
wire rxd ;
wire rxd_neg ;
reg in_cyc ;
reg [3:0] rx_cnt ;
reg [2:0] cnt ;
wire rx_over ;
wire rx_sample ;
reg rx_req ;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rxd_d <= 2'b11;
else
rxd_d <= {rxd_d[0],rxd_in};
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rxd_tmp <= 3'b111;
else if(clk_en)
rxd_tmp <= {rxd_tmp[1:0],rxd_d[1]};
else;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rxd_r1 <= 1'b1;
else if(clk_en)
begin
if(rxd_tmp == 3'b111)
rxd_r1 <= 1'b1;
else if(rxd_tmp == 3'b000)
rxd_r1 <= 1'b0;
else;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rxd_r2 <= 1'b1;
else if(clk_en)
rxd_r2 <= rxd_r1;
end
assign rxd = rxd_r2;
assign rxd_neg = rxd_r2 & ~rxd_r1;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
in_cyc <= 1'b0;
else if(clk_en)
begin
if(rxd_neg)
in_cyc <= 1'b1;
else if(rx_over && rx_sample)
in_cyc <= 1'b0;
end
end
assign cnt_down = cnt == 3'd5;
assign rx_sample = cnt == 3'd2;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt <= 3'b0;
else if(clk_en)
begin
if(cnt_down)
cnt <= 3'b0;
else if(~in_cyc)
cnt <= 3'b0;
else
cnt <= cnt + 3'b1;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
rx_fifo_wr_data <= 8'b0;
rx_cnt <= 4'd9;
end
else if(clk_en)
begin
if(~in_cyc)
begin
rx_fifo_wr_data <= 8'b0;
rx_cnt <= 4'd9;
end
else if(rx_sample)
begin
rx_fifo_wr_data <= {rxd,rx_fifo_wr_data[7:1]};
rx_cnt <= rx_cnt + 4'hf; // rx_cnt = rx_cnt - 1;
end
end
end
assign rx_over = rx_cnt == 4'd1;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rx_req <= 1'b0;
else if(clk_en)
begin
if(rx_sample && rx_over)
rx_req <= 1'b1;
end
else
rx_req <= 1'b0;
end
assign rx_fifo_wr_data_req = rx_req && rx_fifo_wr_data_valid;
endmodule |
module ipsxb_uart_ctrl_32bit #(
parameter CLK_DIV_P = 'd72 ,
parameter DFT_CTRL_BUS_0 = 32'h0000_0000,
parameter DFT_CTRL_BUS_1 = 32'h0000_0000,
parameter DFT_CTRL_BUS_2 = 32'h0000_0000,
parameter DFT_CTRL_BUS_3 = 32'h0000_0000,
parameter DFT_CTRL_BUS_4 = 32'h0000_0000,
parameter DFT_CTRL_BUS_5 = 32'h0000_0000,
parameter DFT_CTRL_BUS_6 = 32'h0000_0000,
parameter DFT_CTRL_BUS_7 = 32'h0000_0000,
parameter DFT_CTRL_BUS_8 = 32'h0000_0000,
parameter DFT_CTRL_BUS_9 = 32'h0000_0000,
parameter DFT_CTRL_BUS_10 = 32'h0000_0000,
parameter DFT_CTRL_BUS_11 = 32'h0000_0000,
parameter DFT_CTRL_BUS_12 = 32'h0000_0000,
parameter DFT_CTRL_BUS_13 = 32'h0000_0000,
parameter DFT_CTRL_BUS_14 = 32'h0000_0000,
parameter DFT_CTRL_BUS_15 = 32'h0000_0000
)(
input clk ,
input rst_n ,
output [31:0] tx_fifo_wr_data ,
input tx_fifo_wr_data_valid ,
output tx_fifo_wr_data_req ,
input [7:0] rx_fifo_rd_data ,
input rx_fifo_rd_data_valid ,
output rx_fifo_rd_data_req ,
output read_req ,
input read_ack ,
output [8:0] uart_rd_addr ,
output [31:0] ctrl_bus_0 ,
output [31:0] ctrl_bus_1 ,
output [31:0] ctrl_bus_2 ,
output [31:0] ctrl_bus_3 ,
output [31:0] ctrl_bus_4 ,
output [31:0] ctrl_bus_5 ,
output [31:0] ctrl_bus_6 ,
output [31:0] ctrl_bus_7 ,
output [31:0] ctrl_bus_8 ,
output [31:0] ctrl_bus_9 ,
output [31:0] ctrl_bus_10 ,
output [31:0] ctrl_bus_11 ,
output [31:0] ctrl_bus_12 ,
output [31:0] ctrl_bus_13 ,
output [31:0] ctrl_bus_14 ,
output [31:0] ctrl_bus_15 ,
input [31:0] status_bus
);
wire [23:0] addr ;
wire [31:0] data ;
wire we ;
wire cmd_en ;
wire ver_cmd_en ;
wire cmd_done ;
wire ver_cmd_done ;
wire [31:0] ver_tx_fifo_wr_data ;
wire ver_tx_fifo_wr_data_req ;
assign cmd_done = ver_cmd_done;
assign tx_fifo_wr_data = ver_tx_fifo_wr_data;
assign tx_fifo_wr_data_req = ver_tx_fifo_wr_data_req;
assign ver_cmd_en = cmd_en;
assign uart_rd_addr = addr[8:0];
ipsxb_cmd_parser_32bit u_cmd_parser(
.clk (clk ),
.rst_n (rst_n ),
.fifo_data (rx_fifo_rd_data ),
.fifo_data_valid (rx_fifo_rd_data_valid ),
.fifo_data_req (rx_fifo_rd_data_req ),
.addr (addr ),
.data (data ),
.we (we ),
.cmd_en (cmd_en ),
.cmd_done (cmd_done )
);
ipsxb_ver_ctrl_32bit #(
.DFT_CTRL_BUS_0 (DFT_CTRL_BUS_0 ),
.DFT_CTRL_BUS_1 (DFT_CTRL_BUS_1 ),
.DFT_CTRL_BUS_2 (DFT_CTRL_BUS_2 ),
.DFT_CTRL_BUS_3 (DFT_CTRL_BUS_3 ),
.DFT_CTRL_BUS_4 (DFT_CTRL_BUS_4 ),
.DFT_CTRL_BUS_5 (DFT_CTRL_BUS_5 ),
.DFT_CTRL_BUS_6 (DFT_CTRL_BUS_6 ),
.DFT_CTRL_BUS_7 (DFT_CTRL_BUS_7 ),
.DFT_CTRL_BUS_8 (DFT_CTRL_BUS_8 ),
.DFT_CTRL_BUS_9 (DFT_CTRL_BUS_9 ),
.DFT_CTRL_BUS_10 (DFT_CTRL_BUS_10 ),
.DFT_CTRL_BUS_11 (DFT_CTRL_BUS_11 ),
.DFT_CTRL_BUS_12 (DFT_CTRL_BUS_12 ),
.DFT_CTRL_BUS_13 (DFT_CTRL_BUS_13 ),
.DFT_CTRL_BUS_14 (DFT_CTRL_BUS_14 ),
.DFT_CTRL_BUS_15 (DFT_CTRL_BUS_15 )
)u_ver_ctrl(
.clk (clk ),
.rst_n (rst_n ),
.addr (addr[8:0] ),
.data (data ),
.we (we ),
.cmd_en (ver_cmd_en ),
.cmd_done (ver_cmd_done ),
.fifo_data (ver_tx_fifo_wr_data ),
.fifo_data_valid (tx_fifo_wr_data_valid ),
.fifo_data_req (ver_tx_fifo_wr_data_req),
.read_req (read_req ),
.read_ack (read_ack ),
.ctrl_bus_0 (ctrl_bus_0 ),
.ctrl_bus_1 (ctrl_bus_1 ),
.ctrl_bus_2 (ctrl_bus_2 ),
.ctrl_bus_3 (ctrl_bus_3 ),
.ctrl_bus_4 (ctrl_bus_4 ),
.ctrl_bus_5 (ctrl_bus_5 ),
.ctrl_bus_6 (ctrl_bus_6 ),
.ctrl_bus_7 (ctrl_bus_7 ),
.ctrl_bus_8 (ctrl_bus_8 ),
.ctrl_bus_9 (ctrl_bus_9 ),
.ctrl_bus_10 (ctrl_bus_10 ),
.ctrl_bus_11 (ctrl_bus_11 ),
.ctrl_bus_12 (ctrl_bus_12 ),
.ctrl_bus_13 (ctrl_bus_13 ),
.ctrl_bus_14 (ctrl_bus_14 ),
.ctrl_bus_15 (ctrl_bus_15 ),
.status_bus (status_bus )
);
endmodule |
module ipsxb_ddrphy_pll_v1_0 #(
parameter real CLKIN_FREQ = 50.0,
parameter integer STATIC_RATIOI = 2,
parameter integer STATIC_RATIOF = 32,
parameter integer STATIC_RATIO0 = 2,
parameter integer STATIC_RATIO1 = 8,
parameter integer STATIC_DUTY0 = 2,
parameter integer STATIC_DUTY1 = 8
) (
clkin1,
clkout0_gate,
pll_rst,
clkout0,
clkout1,
pll_lock
);
localparam integer STATIC_RATIO2 = 16;
localparam integer STATIC_RATIO3 = 16;
localparam integer STATIC_RATIO4 = 4;
localparam integer STATIC_DUTY2 = 16;
localparam integer STATIC_DUTY3 = 16;
localparam integer STATIC_DUTY4 = 4;
localparam integer STATIC_DUTYF = 32;
localparam integer STATIC_PHASE0 = 16;
localparam integer STATIC_PHASE1 = 16;
localparam integer STATIC_PHASE2 = 16;
localparam integer STATIC_PHASE3 = 16;
localparam integer STATIC_PHASE4 = 16;
localparam CLK_CAS1_EN = "FALSE";
localparam CLK_CAS2_EN = "FALSE";
localparam CLK_CAS3_EN = "FALSE";
localparam CLK_CAS4_EN = "FALSE";
localparam CLKIN_BYPASS_EN = "FALSE";
localparam CLKOUT0_GATE_EN = "TRUE";
localparam CLKOUT0_EXT_GATE_EN = "FALSE";
localparam CLKOUT1_GATE_EN = "FALSE";
localparam CLKOUT2_GATE_EN = "FALSE";
localparam CLKOUT3_GATE_EN = "FALSE";
localparam CLKOUT4_GATE_EN = "FALSE";
localparam FBMODE = "FALSE";
localparam integer FBDIV_SEL = 0;
localparam BANDWIDTH = "OPTIMIZED";
localparam PFDEN_EN = "FALSE";
localparam VCOCLK_DIV2 = 1'b0;
localparam DYNAMIC_RATIOI_EN = "FALSE";
localparam DYNAMIC_RATIO0_EN = "FALSE";
localparam DYNAMIC_RATIO1_EN = "FALSE";
localparam DYNAMIC_RATIO2_EN = "FALSE";
localparam DYNAMIC_RATIO3_EN = "FALSE";
localparam DYNAMIC_RATIO4_EN = "FALSE";
localparam DYNAMIC_RATIOF_EN = "FALSE";
localparam DYNAMIC_DUTY0_EN = "FALSE";
localparam DYNAMIC_DUTY1_EN = "FALSE";
localparam DYNAMIC_DUTY2_EN = "FALSE";
localparam DYNAMIC_DUTY3_EN = "FALSE";
localparam DYNAMIC_DUTY4_EN = "FALSE";
localparam DYNAMIC_DUTYF_EN = "FALSE";
localparam PHASE_ADJUST0_EN = "TRUE";
localparam PHASE_ADJUST1_EN = (CLK_CAS1_EN == "TRUE") ? "FALSE" : "TRUE";
localparam PHASE_ADJUST2_EN = (CLK_CAS2_EN == "TRUE") ? "FALSE" : "TRUE";
localparam PHASE_ADJUST3_EN = (CLK_CAS3_EN == "TRUE") ? "FALSE" : "TRUE";
localparam PHASE_ADJUST4_EN = (CLK_CAS4_EN == "TRUE") ? "FALSE" : "TRUE";
localparam DYNAMIC_PHASE0_EN = "FALSE";
localparam DYNAMIC_PHASE1_EN = "FALSE";
localparam DYNAMIC_PHASE2_EN = "FALSE";
localparam DYNAMIC_PHASE3_EN = "FALSE";
localparam DYNAMIC_PHASE4_EN = "FALSE";
localparam DYNAMIC_PHASEF_EN = "FALSE";
localparam integer STATIC_PHASEF = 16;
localparam CLK_CAS0_EN = "FALSE";
localparam integer CLKOUT5_SEL = 0;
localparam CLKOUT5_GATE_EN = "FALSE";
localparam INTERNAL_FB = (FBMODE == "FALSE") ? "ENABLE":"DISABLE";
localparam EXTERNAL_FB = (FBMODE == "FALSE") ? "DISABLE":
(FBDIV_SEL == 0) ? "CLKOUT0":
(FBDIV_SEL == 1) ? "CLKOUT1":
(FBDIV_SEL == 2) ? "CLKOUT2":
(FBDIV_SEL == 3) ? "CLKOUT3":
(FBDIV_SEL == 4) ? "CLKOUT4":"DISABLE";
localparam RSTODIV_ENABLE = "FALSE";
localparam integer STATIC_RATIOM = 1;
input clkin1;
input clkout0_gate;
input pll_rst;
output clkout0;
output clkout1;
output pll_lock;
wire clkout0;
wire clkout0_2pad;
// wire clkout1;
wire clkout2;
wire clkout3;
wire clkout4;
wire clkout5;
wire clkswitch_flag;
wire pll_lock;
wire clkin1;
wire clkin2;
wire clkfb;
wire clkin_sel;
wire clkin_sel_en;
wire pfden;
wire clkout0_gate;
wire clkout0_2pad_gate;
wire clkout1_gate;
wire clkout2_gate;
wire clkout3_gate;
wire clkout4_gate;
wire clkout5_gate;
wire [9:0] dyn_idiv;
wire [9:0] dyn_odiv0;
wire [9:0] dyn_odiv1;
wire [9:0] dyn_odiv2;
wire [9:0] dyn_odiv3;
wire [9:0] dyn_odiv4;
wire [9:0] dyn_fdiv;
wire [9:0] dyn_duty0;
wire [9:0] dyn_duty1;
wire [9:0] dyn_duty2;
wire [9:0] dyn_duty3;
wire [9:0] dyn_duty4;
wire [12:0] dyn_phase0;
wire [12:0] dyn_phase1;
wire [12:0] dyn_phase2;
wire [12:0] dyn_phase3;
wire [12:0] dyn_phase4;
wire pll_pwd;
wire pll_rst;
wire rstodiv;
wire icp_base;
wire [3:0] icp_sel;
wire [2:0] lpfres_sel;
wire cripple_sel;
wire [2:0] phase_sel;
wire phase_dir;
wire phase_step_n;
wire load_phase;
wire [6:0] dyn_mdiv;
assign clkin2 = 1'b0;
assign clkin_sel = 1'b0;
assign clkin_sel_en = 1'b0;
assign pll_pwd = 1'b0;
assign rstodiv = 1'b0;
GTP_PLL_E3 #(
.CLKIN_FREQ(CLKIN_FREQ),
.PFDEN_EN(PFDEN_EN),
.VCOCLK_DIV2(VCOCLK_DIV2),
.DYNAMIC_RATIOI_EN(DYNAMIC_RATIOI_EN),
.DYNAMIC_RATIOM_EN("FALSE"),
.DYNAMIC_RATIO0_EN(DYNAMIC_RATIO0_EN),
.DYNAMIC_RATIO1_EN(DYNAMIC_RATIO1_EN),
.DYNAMIC_RATIO2_EN(DYNAMIC_RATIO2_EN),
.DYNAMIC_RATIO3_EN(DYNAMIC_RATIO3_EN),
.DYNAMIC_RATIO4_EN(DYNAMIC_RATIO4_EN),
.DYNAMIC_RATIOF_EN(DYNAMIC_RATIOF_EN),
.STATIC_RATIOI(STATIC_RATIOI),
.STATIC_RATIOM(STATIC_RATIOM),
.STATIC_RATIO0(STATIC_RATIO0),
.STATIC_RATIO1(STATIC_RATIO1),
.STATIC_RATIO2(STATIC_RATIO2),
.STATIC_RATIO3(STATIC_RATIO3),
.STATIC_RATIO4(STATIC_RATIO4),
.STATIC_RATIOF(STATIC_RATIOF),
.DYNAMIC_DUTY0_EN(DYNAMIC_DUTY0_EN),
.DYNAMIC_DUTY1_EN(DYNAMIC_DUTY1_EN),
.DYNAMIC_DUTY2_EN(DYNAMIC_DUTY2_EN),
.DYNAMIC_DUTY3_EN(DYNAMIC_DUTY3_EN),
.DYNAMIC_DUTY4_EN(DYNAMIC_DUTY4_EN),
.STATIC_DUTY0(STATIC_DUTY0),
.STATIC_DUTY1(STATIC_DUTY1),
.STATIC_DUTY2(STATIC_DUTY2),
.STATIC_DUTY3(STATIC_DUTY3),
.STATIC_DUTY4(STATIC_DUTY4),
.STATIC_PHASE0(STATIC_PHASE0[2:0]),
.STATIC_PHASE1(STATIC_PHASE1[2:0]),
.STATIC_PHASE2(STATIC_PHASE2[2:0]),
.STATIC_PHASE3(STATIC_PHASE3[2:0]),
.STATIC_PHASE4(STATIC_PHASE4[2:0]),
.STATIC_PHASEF(STATIC_PHASEF[2:0]),
.STATIC_CPHASE0(STATIC_PHASE0[12:3]-2),
.STATIC_CPHASE1(STATIC_PHASE1[12:3]-2),
.STATIC_CPHASE2(STATIC_PHASE2[12:3]-2),
.STATIC_CPHASE3(STATIC_PHASE3[12:3]-2),
.STATIC_CPHASE4(STATIC_PHASE4[12:3]-2),
.STATIC_CPHASEF(STATIC_PHASEF[12:3]-2),
.CLK_CAS1_EN(CLK_CAS1_EN),
.CLK_CAS2_EN(CLK_CAS2_EN),
.CLK_CAS3_EN(CLK_CAS3_EN),
.CLK_CAS4_EN(CLK_CAS4_EN),
.CLKOUT5_SEL(CLKOUT5_SEL),
.CLKIN_BYPASS_EN(CLKIN_BYPASS_EN),
.CLKOUT0_SYN_EN(CLKOUT0_GATE_EN),
.CLKOUT0_EXT_SYN_EN(CLKOUT0_EXT_GATE_EN),
.CLKOUT1_SYN_EN(CLKOUT1_GATE_EN),
.CLKOUT2_SYN_EN(CLKOUT2_GATE_EN),
.CLKOUT3_SYN_EN(CLKOUT3_GATE_EN),
.CLKOUT4_SYN_EN(CLKOUT4_GATE_EN),
.CLKOUT5_SYN_EN(CLKOUT5_GATE_EN),
.INTERNAL_FB(INTERNAL_FB),
.EXTERNAL_FB(EXTERNAL_FB),
.DYNAMIC_LOOP_EN("FALSE"),
.LOOP_MAPPING_EN("FALSE"),
.BANDWIDTH(BANDWIDTH)
) u_pll_e3 (
.CLKOUT0(clkout0),
.CLKOUT0_EXT(clkout0_2pad),
.CLKOUT1(clkout1),
.CLKOUT2(clkout2),
.CLKOUT3(clkout3),
.CLKOUT4(clkout4),
.CLKOUT5(clkout5),
.CLKSWITCH_FLAG(clkswitch_flag),
.LOCK(pll_lock),
.CLKIN1(clkin1),
.CLKIN2(clkin2),
.CLKFB(clkfb),
.CLKIN_SEL(clkin_sel),
.CLKIN_SEL_EN(clkin_sel_en),
.PFDEN(pfden),
.ICP_BASE(1'b0),
.ICP_SEL(4'b0),
.LPFRES_SEL(3'b0),
.CRIPPLE_SEL(1'b0),
.PHASE_SEL(3'b0),
.PHASE_DIR(1'b0),
.PHASE_STEP_N(1'b0),
.LOAD_PHASE(1'b0),
.RATIOM(7'b0),
.RATIOI(dyn_idiv),
.RATIO0(dyn_odiv0),
.RATIO1(dyn_odiv1),
.RATIO2(dyn_odiv2),
.RATIO3(dyn_odiv3),
.RATIO4(dyn_odiv4),
.RATIOF(dyn_fdiv),
.DUTY0(dyn_duty0),
.DUTY1(dyn_duty1),
.DUTY2(dyn_duty2),
.DUTY3(dyn_duty3),
.DUTY4(dyn_duty4),
.CLKOUT0_SYN(clkout0_gate),
.CLKOUT0_EXT_SYN(clkout0_2pad_gate),
.CLKOUT1_SYN(clkout1_gate),
.CLKOUT2_SYN(clkout2_gate),
.CLKOUT3_SYN(clkout3_gate),
.CLKOUT4_SYN(clkout4_gate),
.CLKOUT5_SYN(clkout5_gate),
.PLL_PWD(pll_pwd),
.RST(pll_rst),
.RSTODIV(rstodiv)
);
endmodule |
module pcie_test
(
//clk and rst
input free_clk ,
output wire pclk ,
output wire pclk_div2 ,
output wire ref_clk ,
input ref_clk_n ,
input ref_clk_p ,
input button_rst_n ,
input power_up_rst_n ,
input perst_n ,
output wire core_rst_n ,
//APB interface to DBI cfg
// input p_clk ,
input p_sel ,
input [ 3:0] p_strb ,
input [15:0] p_addr ,
input [31:0] p_wdata ,
input p_ce ,
input p_we ,
output wire p_rdy ,
output wire [31:0] p_rdata ,
//PHY diff signals
input [1:0] rxn ,
input [1:0] rxp ,
output wire [1:0] txn ,
output wire [1:0] txp ,
input [1:0] pcs_nearend_loop ,
input [1:0] pma_nearend_ploop ,
input [1:0] pma_nearend_sloop ,
//AXIS master interface
output wire axis_master_tvalid ,
input axis_master_tready ,
output wire [127:0] axis_master_tdata ,
output wire [3:0] axis_master_tkeep ,
output wire axis_master_tlast ,
output wire [7:0] axis_master_tuser ,
//axis slave 0 interface
output wire axis_slave0_tready ,
input axis_slave0_tvalid ,
input [127:0] axis_slave0_tdata ,
input axis_slave0_tlast ,
input axis_slave0_tuser ,
//axis slave 1 interface
output wire axis_slave1_tready ,
input axis_slave1_tvalid ,
input [127:0] axis_slave1_tdata ,
input axis_slave1_tlast ,
input axis_slave1_tuser ,
//axis slave 2 interface
output wire axis_slave2_tready ,
input axis_slave2_tvalid ,
input [127:0] axis_slave2_tdata ,
input axis_slave2_tlast ,
input axis_slave2_tuser ,
output wire pm_xtlh_block_tlp , //ask about the processing latency
output wire cfg_send_cor_err_mux ,
output wire cfg_send_nf_err_mux ,
output wire cfg_send_f_err_mux ,
output wire cfg_sys_err_rc ,
output wire cfg_aer_rc_err_mux ,
//radm timeout
output wire radm_cpl_timeout ,
output wire [7:0] cfg_pbus_num ,
output wire [4:0] cfg_pbus_dev_num ,
//configuration signals
output wire [2:0] cfg_max_rd_req_size ,
output wire cfg_bus_master_en ,
output wire [2:0] cfg_max_payload_size ,
output wire cfg_ext_tag_en ,
output wire cfg_rcb ,
output wire cfg_mem_space_en ,
output wire cfg_pm_no_soft_rst ,
output wire cfg_crs_sw_vis_en ,
output wire cfg_no_snoop_en ,
output wire cfg_relax_order_en ,
output wire [2-1:0] cfg_tph_req_en ,
output wire [3-1:0] cfg_pf_tph_st_mode ,
output wire rbar_ctrl_update ,
output wire cfg_atomic_req_en ,
//debug signals
output wire radm_idle ,
output wire radm_q_not_empty ,
output wire radm_qoverflow ,
input [1:0] diag_ctrl_bus ,
output wire cfg_link_auto_bw_mux , //merge cfg_link_auto_bw_msi and cfg_link_auto_bw_int
output wire cfg_bw_mgt_mux , //merge cfg_bw_mgt_int and cfg_bw_mgt_msi
output wire cfg_pme_mux , //merge cfg_pme_int and cfg_pme_msi
input app_ras_des_sd_hold_ltssm ,
input [1:0] app_ras_des_tba_ctrl ,
input [3:0] dyn_debug_info_sel ,
output wire [132:0] debug_info_mux ,
//system signal
output wire smlh_link_up ,
output wire rdlh_link_up ,
output wire [4:0] smlh_ltssm_state
);
localparam DEVICE_TYPE = 3'b000;//@IPC enum 3'b000,3'b001,3'b100
`ifdef IPSL_PCIE_SPEEDUP_SIM
localparam DIAG_CTRL_BUS_B2 = "FAST_LINK_MODE";
`else
localparam DIAG_CTRL_BUS_B2 = "NORMAL";
`endif
localparam MSI_CAP_DISABLE = "TRUE";
localparam MSIX_CAP_DISABLE = "TRUE";
localparam MSI_PVM_DISABLE = "TRUE";
localparam ATOMIC_DISABLE = "TRUE";
localparam TPH_DISABLE = "TRUE";
// cfg space reg
localparam MAX_LINK_WIDTH = 6'd2 ; //@IPC enum 6'd1,6'd2,6'd4
localparam MAX_LINK_SPEED = 4'd2 ; //@IPC enum 4'd1,4'd2
localparam LINK_CAPABLE = 6'd3 ; //@IPC enum 6'd1,6'd3,6'd7
localparam SCRAMBLE_DISABLE = 1'b0; //@IPC bool
localparam AUTO_LANE_FLIP_CTRL_EN = 1'b0; //@IPC bool
localparam NUM_OF_LANES = 5'b1 ; //@IPC bool
localparam MAX_PAYLOAD_SIZE = 3'd0 ; //@IPC enum 3'd0,3'd1,3'd2,3'd3
localparam INT_DISABLE = 1'b1; //@IPC bool
localparam MSI_ENABLE = 1'b0; //@IPC bool
localparam MSI_64_BIT_ADDR_CAP = 1'b0; //@IPC bool
localparam MSI_MULTIPLE_MSG_CAP = 3'd0 ; //@IPC enum 3'd0,3'd1,3'd2,3'd3,3'd4,3'd5
localparam PVM_SUPPORT = 1'b0 ; //@IPC bool
localparam CAP_POINTER = 8'h70 ;
localparam PCIE_CAP_NEXT_PTR = 8'h00 ;
localparam VENDOR_ID = 16'h0755 ; //@IPC string
localparam DEVICE_ID = 16'h0755 ; //@IPC string
localparam BASE_CLASS_CODE = 8'h05 ; //@IPC string
localparam SUBCLASS_CODE = 8'h80 ; //@IPC string
localparam PROGRAM_INTERFACE = 8'h00 ; //@IPC string
localparam REVISION_ID = 8'h00 ; //@IPC string
localparam SUBSYS_VENDOR_ID = 16'h0000 ; //@IPC string
localparam SUBSYS_DEV_ID = 16'h0000 ; //@IPC string
localparam BAR0_PREFETCH = 1'b0 ; //@IPC enum 1'b0,1'b1
localparam BAR0_TYPE = 2'd0 ; //@IPC enum 2'd0,2'd2
localparam BAR0_MEM_IO = 1'b0 ; //@IPC enum 1'b0,1'b1
localparam BAR0_ENABLED = 1'b1 ; //@IPC bool
localparam BAR0_MASK = 31'hfff ; //@IPC string
localparam BAR1_MEM_IO = 1'b0 ; //@IPC enum 1'b0,1'b1
localparam BAR1_ENABLED = 1'b1 ; //@IPC bool
localparam BAR1_MASK = 31'h7ff ; //@IPC string
localparam BAR2_PREFETCH = 1'b0 ; //@IPC enum 1'b0,1'b1
localparam BAR2_TYPE = 2'd2 ; //@IPC enum 2'd0,2'd2
localparam BAR2_MEM_IO = 1'b0 ; //@IPC enum 1'b0,1'b1
localparam BAR2_ENABLED = 1'b1 ; //@IPC bool
localparam BAR2_MASK = 31'hfff ; //@IPC string
localparam BAR3_MEM_IO = 1'b0 ; //@IPC enum 1'b0,1'b1
localparam BAR3_ENABLED = 1'b0 ; //@IPC bool
localparam BAR3_MASK = 31'h0 ; //@IPC string
localparam BAR4_PREFETCH = 1'b0 ; //@IPC enum 1'b0,1'b1
localparam BAR4_TYPE = 2'd0 ; //@IPC enum 2'd0,2'd2
localparam BAR4_MEM_IO = 1'b0 ; //@IPC enum 1'b0,1'b1
localparam BAR4_ENABLED = 1'b0 ; //@IPC bool
localparam BAR4_MASK = 31'h0 ; //@IPC string
localparam BAR5_MEM_IO = 1'b0 ; //@IPC enum 1'b0,1'b1
localparam BAR5_ENABLED = 1'b0 ; //@IPC bool
localparam BAR5_MASK = 31'h0 ; //@IPC string
localparam ROM_BAR_ENABLE = 1'b0 ; //@IPC bool
localparam ROM_BAR_ENABLED = 1'b0 ; //@IPC bool
localparam ROM_MASK = 31'h0 ; //@IPC string
localparam DO_DESKEW_FOR_SRIS = 1'b1 ;
localparam PCIE_CAP_HW_AUTO_SPEED_DISABLE = 1'b0 ; //@IPC bool
localparam TARGET_LINK_SPEED = 4'h2 ; //@IPC enum 4'h1,4'h2
localparam ECRC_CHECK_EN = 1'b1 ; //@IPC bool
localparam ECRC_GEN_EN = 1'b0 ; //@IPC bool
localparam EXT_TAG_EN = 1'b1 ; //@IPC bool
localparam EXT_TAG_SUPP = 1'b1 ; //@IPC bool
localparam PCIE_CAP_RCB = 1'b1 ; //@IPC enum 1'b0,1'b1
localparam PCIE_CAP_CRS = 1'b0 ; //@IPC bool
localparam PCIE_CAP_ATOMIC_EN = 1'b0 ; //@IPC bool
localparam PCI_MSIX_ENABLE = 1'b0 ; //@IPC bool
localparam PCI_FUNCTION_MASK = 1'b0 ;
localparam PCI_MSIX_TABLE_SIZE = 11'h1 ; //@IPC string
localparam PCI_MSIX_CPA_NEXT_OFFSET = 8'h0 ;
localparam PCI_MSIX_TABLE_OFFSET = 29'h0 ; //@IPC string
localparam PCI_MSIX_BIR = 3'd0 ; //@IPC enum 1'b0,1'b1
localparam PCI_MSIX_PBA_OFFSET = 29'h0 ; //@IPC string
localparam PCI_MSIX_PBA_BIR = 3'd0 ; //@IPC enum 1'b0,1'b1
localparam AER_CAP_NEXT_OFFSET = 12'h0 ;
localparam TPH_REQ_NEXT_PTR = 12'h0 ;
localparam integer BAR_RESIZABLE = 6'b000000 ;
localparam integer NUM_OF_RBARS = 3 ;
localparam integer BAR_INDEX_0 = 0 ;
localparam integer BAR_INDEX_1 = 1 ;
localparam integer BAR_INDEX_2 = 2 ;
localparam integer BAR_MASK_WRITABLE = 6'b111111 ;
localparam RESBAR_BAR0_MAX_SUPP_SIZE = 20'hf_ffff ;
localparam RESBAR_BAR0_INIT_SIZE = 5'h0 ;
localparam RESBAR_BAR1_MAX_SUPP_SIZE = 20'hf_ffff ;
localparam RESBAR_BAR1_INIT_SIZE = 5'h0 ;
localparam RESBAR_BAR2_MAX_SUPP_SIZE = 20'hf_ffff ;
localparam RESBAR_BAR2_INIT_SIZE = 5'h0 ;
localparam UPCONFIGURE_SUPPORT = 1'b1 ; //@IPC bool
localparam integer HSST_LANE_NUM = 2 ;
`ifdef IPSL_PCIE_SPEEDUP_SIM
initial
$display("HSST_X2_LANE MODE!");
`endif
//hot rst
wire app_init_rst;
wire training_rst_n;
assign app_init_rst = 1'b0;
//system ctrl
wire rx_lane_flip_en ;
wire tx_lane_flip_en ;
wire app_req_retry_en ;
assign rx_lane_flip_en = 1'b0;
assign tx_lane_flip_en = 1'b0;
assign app_req_retry_en = 1'b0;
//Rcv_Queue_Manage
wire [2:0] trgt1_radm_pkt_halt ;
wire [5:0] radm_grant_tlp_type ;
assign trgt1_radm_pkt_halt = 3'b0;
//legacy interrupt
wire cfg_int_disable ;
wire sys_int ;
wire inta_grt_mux ;
wire intb_grt_mux ;
wire intc_grt_mux ;
wire intd_grt_mux ;
assign sys_int = 1'b0;
//msi
wire [4:0] ven_msi_vector ;
wire [(32*1)-1:0] cfg_msi_pending ;
wire cfg_msi_en ;
assign ven_msi_vector = 5'b0;
assign cfg_msi_pending = 32'b0;
//msi
wire ven_msi_req ;
wire [2:0] ven_msi_tc ;
wire ven_msi_grant ;
assign ven_msi_req = 1'b0;
assign ven_msi_tc = 3'b0;
// MSI-X interface
wire [63:0] msix_addr ;
wire [31:0] msix_data ;
wire cfg_msix_en ;
wire cfg_msix_func_mask ;
assign msix_addr = 64'b0;
assign msix_data = 32'b0;
//unlock message
wire radm_msg_unlock ;
wire app_unlock_msg ;
assign app_unlock_msg = 1'b0;
//power management
wire radm_pm_turnoff ;
wire outband_pwrup_cmd ;
wire pm_status ;
wire [2:0] pm_dstate ;
wire aux_pm_en ;
wire pm_pme_en ;
wire pm_linkst_in_l0s ;
wire pm_linkst_in_l1 ;
wire pm_linkst_in_l2 ;
wire pm_linkst_l2_exit ;
wire app_req_entr_l1 ;
wire app_ready_entr_l23 ;
wire app_req_exit_l1 ;
wire app_xfer_pending ;
wire wake ;
wire radm_pm_pme ;
wire radm_pm_to_ack ;
wire apps_pm_xmt_turnoff ;
wire apps_pm_xmt_pme ;
wire [4:0] pm_master_state ;
wire [4:0] pm_slave_state ;
assign outband_pwrup_cmd = 1'b0;
assign app_req_entr_l1 = 1'b0;
assign app_ready_entr_l23 = 1'b0;
assign app_req_exit_l1 = 1'b0;
assign app_xfer_pending = 1'b0;
assign apps_pm_xmt_turnoff = 1'b0;
assign apps_pm_xmt_pme = 1'b0;
//error handling
wire app_hdr_valid ;
wire [127:0] app_hdr_log ;
wire [12:0] app_err_bus ;
wire app_err_advisory ;
assign app_hdr_valid = 1'b0;
assign app_hdr_log = 128'b0;
assign app_err_bus = 13'b0;
assign app_err_advisory = 1'b0;
//radm timeout
wire [2:0] radm_timeout_cpl_tc ;
wire [7:0] radm_timeout_cpl_tag ;
wire [1:0] radm_timeout_cpl_attr;
wire [10:0] radm_timeout_cpl_len ;
//misc
wire cfg_ido_req_en ;
wire cfg_ido_cpl_en ;
wire [7:0] xadm_ph_cdts ;
wire [11:0] xadm_pd_cdts ;
wire [7:0] xadm_nph_cdts ;
wire [11:0] xadm_npd_cdts ;
wire [7:0] xadm_cplh_cdts ;
wire [11:0] xadm_cpld_cdts ;
//-------------------------------PCIE IP WRAP include PHY
ipsl_pcie_top_v1_3 #(
.DEVICE_TYPE (DEVICE_TYPE ),
.DIAG_CTRL_BUS_B2 (DIAG_CTRL_BUS_B2 ), // "NORMAL" "FAST_LINK_MODE"
.BAR_RESIZABLE (BAR_RESIZABLE ), // 0: no resizable bar, 1: bar0 resizable, 2: bar1 resizable, 3: bar0-1 resizable, ... 56: bar3-bar5 resizable; Please do not set more than 3 resizable bars at the same time Default value is 21 which is 6'b010101
.NUM_OF_RBARS (NUM_OF_RBARS ), // 0: no resizable bar, 1: one resizable bar, 2: two resizable bars, 3: three resizable bars Default value is 3
.BAR_INDEX_0 (BAR_INDEX_0 ), // set bar index0 in resizable bar control register, 0: bar0 resizable 1: bar1 resizable 2: bar2 resizable ... 5: bar5 resizable Default value is 0
.BAR_INDEX_1 (BAR_INDEX_1 ), // set bar index1 in resizable bar control register, 0: bar0 resizable 1: bar1 resizable 2: bar2 resizable ... 5: bar5 resizable Default value is 2
.BAR_INDEX_2 (BAR_INDEX_2 ), // set bar index2 in resizable bar control register, 0: bar0 resizable 1: bar1 resizable 2: bar2 resizable ... 5: bar5 resizable Default value is 4
.BAR_MASK_WRITABLE (BAR_MASK_WRITABLE ), // 0: no writable bar, 1: bar0 writable, 2: bar1 writable, 3: bar3 writable, ... 63: bar0-5 writable
.TPH_DISABLE (TPH_DISABLE ), // FALSE, TRUE
.MSI_CAP_DISABLE (MSI_CAP_DISABLE ), // FALSE, TRUE
.MSI_PVM_DISABLE (MSI_PVM_DISABLE ), // FALSE, TRUE
.ATOMIC_DISABLE (ATOMIC_DISABLE ), // FALSE, TRUE
.MSIX_CAP_DISABLE (MSIX_CAP_DISABLE ), // FALSE, TRUE
.HSST_LANE_NUM (HSST_LANE_NUM ),
// cfg space reg
.MAX_LINK_WIDTH (MAX_LINK_WIDTH ),
.MAX_LINK_SPEED (MAX_LINK_SPEED ),
.LINK_CAPABLE (LINK_CAPABLE ),
.SCRAMBLE_DISABLE (SCRAMBLE_DISABLE ),
.AUTO_LANE_FLIP_CTRL_EN (AUTO_LANE_FLIP_CTRL_EN ),
.NUM_OF_LANES (NUM_OF_LANES ),
.MAX_PAYLOAD_SIZE (MAX_PAYLOAD_SIZE ),
.INT_DISABLE (INT_DISABLE ),
.PVM_SUPPORT (PVM_SUPPORT ),
.MSI_64_BIT_ADDR_CAP (MSI_64_BIT_ADDR_CAP ),
.MSI_MULTIPLE_MSG_CAP (MSI_MULTIPLE_MSG_CAP ),
.MSI_ENABLE (MSI_ENABLE ),
.CAP_POINTER (CAP_POINTER ),
.PCIE_CAP_NEXT_PTR (PCIE_CAP_NEXT_PTR ),
.VENDOR_ID (VENDOR_ID ),
.DEVICE_ID (DEVICE_ID ),
.BASE_CLASS_CODE (BASE_CLASS_CODE ),
.SUBCLASS_CODE (SUBCLASS_CODE ),
.PROGRAM_INTERFACE (PROGRAM_INTERFACE ),
.REVISION_ID (REVISION_ID ),
.SUBSYS_DEV_ID (SUBSYS_DEV_ID ),
.SUBSYS_VENDOR_ID (SUBSYS_VENDOR_ID ),
.BAR0_PREFETCH (BAR0_PREFETCH ),
.BAR0_TYPE (BAR0_TYPE ),
.BAR0_MEM_IO (BAR0_MEM_IO ),
.BAR0_ENABLED (BAR0_ENABLED ),
.BAR0_MASK (BAR0_MASK ),
.BAR1_MEM_IO (BAR1_MEM_IO ),
.BAR1_ENABLED (BAR1_ENABLED ),
.BAR1_MASK (BAR1_MASK ),
.BAR2_PREFETCH (BAR2_PREFETCH ),
.BAR2_TYPE (BAR2_TYPE ),
.BAR2_MEM_IO (BAR2_MEM_IO ),
.BAR2_ENABLED (BAR2_ENABLED ),
.BAR2_MASK (BAR2_MASK ),
.BAR3_MEM_IO (BAR3_MEM_IO ),
.BAR3_ENABLED (BAR3_ENABLED ),
.BAR3_MASK (BAR3_MASK ),
.BAR4_PREFETCH (BAR4_PREFETCH ),
.BAR4_TYPE (BAR4_TYPE ),
.BAR4_MEM_IO (BAR4_MEM_IO ),
.BAR4_ENABLED (BAR4_ENABLED ),
.BAR4_MASK (BAR4_MASK ),
.BAR5_MEM_IO (BAR5_MEM_IO ),
.BAR5_ENABLED (BAR5_ENABLED ),
.BAR5_MASK (BAR5_MASK ),
.ROM_BAR_ENABLE (ROM_BAR_ENABLE ),
.ROM_BAR_ENABLED (ROM_BAR_ENABLED ),
.ROM_MASK (ROM_MASK ),
.DO_DESKEW_FOR_SRIS (DO_DESKEW_FOR_SRIS ),
.PCIE_CAP_HW_AUTO_SPEED_DISABLE (PCIE_CAP_HW_AUTO_SPEED_DISABLE ),
.TARGET_LINK_SPEED (TARGET_LINK_SPEED ),
.ECRC_CHECK_EN (ECRC_CHECK_EN ),
.ECRC_GEN_EN (ECRC_GEN_EN ),
.EXT_TAG_EN (EXT_TAG_EN ),
.EXT_TAG_SUPP (EXT_TAG_SUPP ),
.PCIE_CAP_RCB (PCIE_CAP_RCB ),
.PCIE_CAP_CRS (PCIE_CAP_CRS ),
.PCIE_CAP_ATOMIC_EN (PCIE_CAP_ATOMIC_EN ),
.PCI_MSIX_ENABLE (PCI_MSIX_ENABLE ),
.PCI_FUNCTION_MASK (PCI_FUNCTION_MASK ),
.PCI_MSIX_TABLE_SIZE (PCI_MSIX_TABLE_SIZE ),
.PCI_MSIX_CPA_NEXT_OFFSET (PCI_MSIX_CPA_NEXT_OFFSET ),
.PCI_MSIX_TABLE_OFFSET (PCI_MSIX_TABLE_OFFSET ),
.PCI_MSIX_BIR (PCI_MSIX_BIR ),
.PCI_MSIX_PBA_OFFSET (PCI_MSIX_PBA_OFFSET ),
.PCI_MSIX_PBA_BIR (PCI_MSIX_PBA_BIR ),
.AER_CAP_NEXT_OFFSET (AER_CAP_NEXT_OFFSET ),
.TPH_REQ_NEXT_PTR (TPH_REQ_NEXT_PTR ),
.RESBAR_BAR0_MAX_SUPP_SIZE (RESBAR_BAR0_MAX_SUPP_SIZE ),
.RESBAR_BAR0_INIT_SIZE (RESBAR_BAR0_INIT_SIZE ),
.RESBAR_BAR1_MAX_SUPP_SIZE (RESBAR_BAR1_MAX_SUPP_SIZE ),
.RESBAR_BAR1_INIT_SIZE (RESBAR_BAR1_INIT_SIZE ),
.RESBAR_BAR2_MAX_SUPP_SIZE (RESBAR_BAR2_MAX_SUPP_SIZE ),
.RESBAR_BAR2_INIT_SIZE (RESBAR_BAR2_INIT_SIZE ),
.UPCONFIGURE_SUPPORT (UPCONFIGURE_SUPPORT )
) u_pcie_top (
.i_button_rstn (button_rst_n ),
.i_power_up_rstn (power_up_rst_n ),
.i_perstn (perst_n ),
.o_core_rst_n (core_rst_n ),
.o_training_rst_n (training_rst_n ),
.i_app_init_rst (app_init_rst ),
.free_clk (free_clk ),
.pclk (pclk ),
.pclk_div2 (pclk_div2 ),
//APB
// .i_apb_clk (p_clk ),
.i_apb_sel (p_sel ),
.i_apb_strb (p_strb ),
.i_apb_addr (p_addr ),
.i_apb_wdata (p_wdata ),
.i_apb_ce (p_ce ),
.i_apb_we (p_we ),
.o_apb_rdy (p_rdy ),
.o_apb_rdata (p_rdata ),
//diff signals
.o_txn_lane (txn ),
.o_txp_lane (txp ),
.i_rxn_lane (rxn ),
.i_rxp_lane (rxp ),
.i_refckn (ref_clk_n ),
.i_refckp (ref_clk_p ),
.i_pcs_nearend_loop (pcs_nearend_loop ),
.i_pma_nearend_ploop (pma_nearend_ploop ),
.i_pma_nearend_sloop (pma_nearend_sloop ),
//AXIS master interface
.o_axis_master_tvalid (axis_master_tvalid ),
.i_axis_master_tready (axis_master_tready ),
.o_axis_master_tdata (axis_master_tdata ),
.o_axis_master_tkeep (axis_master_tkeep ),
.o_axis_master_tlast (axis_master_tlast ),
.o_axis_master_tuser (axis_master_tuser ),
.i_trgt1_radm_pkt_halt (trgt1_radm_pkt_halt ),
.o_radm_grant_tlp_type (radm_grant_tlp_type ),
//axis slave 0 interface
.o_axis_slave0_tready (axis_slave0_tready ),
.i_axis_slave0_tvalid (axis_slave0_tvalid ),
.i_axis_slave0_tdata (axis_slave0_tdata ),
.i_axis_slave0_tlast (axis_slave0_tlast ),
.i_axis_slave0_tuser (axis_slave0_tuser ),
//axis slave 1 interface
.o_axis_slave1_tready (axis_slave1_tready ),
.i_axis_slave1_tvalid (axis_slave1_tvalid ),
.i_axis_slave1_tdata (axis_slave1_tdata ),
.i_axis_slave1_tlast (axis_slave1_tlast ),
.i_axis_slave1_tuser (axis_slave1_tuser ),
//axis slave 2 interface
.o_axis_slave2_tready (axis_slave2_tready ),
.i_axis_slave2_tvalid (axis_slave2_tvalid ),
.i_axis_slave2_tdata (axis_slave2_tdata ),
.i_axis_slave2_tlast (axis_slave2_tlast ),
.i_axis_slave2_tuser (axis_slave2_tuser ),
.o_pm_xtlh_block_tlp (pm_xtlh_block_tlp ),
//INT
.o_cfg_int_disable (cfg_int_disable ),
.i_sys_int (sys_int ),
.o_inta_grt_mux (inta_grt_mux ),
.o_intb_grt_mux (intb_grt_mux ),
.o_intc_grt_mux (intc_grt_mux ),
.o_intd_grt_mux (intd_grt_mux ),
//MSI
.i_ven_msi_req (ven_msi_req ),
.i_ven_msi_tc (ven_msi_tc ),
.i_ven_msi_vector (ven_msi_vector ),
.o_ven_msi_grant (ven_msi_grant ),
.i_cfg_msi_pending (cfg_msi_pending ),
.o_cfg_msi_en (cfg_msi_en ),
//MSI-X
.i_msix_addr (msix_addr ),
.i_msix_data (msix_data ),
.o_cfg_msix_en (cfg_msix_en ),
.o_cfg_msix_func_mask (cfg_msix_func_mask ),
//unlock message
.o_radm_msg_unlock (radm_msg_unlock ),
.i_app_unlock_msg (app_unlock_msg ),
//power management
.o_radm_pm_turnoff (radm_pm_turnoff ),
.i_outband_pwrup_cmd (outband_pwrup_cmd ),
.o_pm_status (pm_status ),
.o_pm_dstate (pm_dstate ),
.o_aux_pm_en (aux_pm_en ),
.o_pm_pme_en (pm_pme_en ),
.o_pm_linkst_in_l0s (pm_linkst_in_l0s ),
.o_pm_linkst_in_l1 (pm_linkst_in_l1 ),
.o_pm_linkst_in_l2 (pm_linkst_in_l2 ),
.o_pm_linkst_l2_exit (pm_linkst_l2_exit ),
.i_app_req_entr_l1 (app_req_entr_l1 ),
.i_app_ready_entr_l23 (app_ready_entr_l23 ),
.i_app_req_exit_l1 (app_req_exit_l1 ),
.i_app_xfer_pending (app_xfer_pending ),
.o_wake (wake ),
.o_radm_pm_pme (radm_pm_pme ),
.o_radm_pm_to_ack (radm_pm_to_ack ),
.i_apps_pm_xmt_turnoff (apps_pm_xmt_turnoff ),
.i_apps_pm_xmt_pme (apps_pm_xmt_pme ),
.i_app_clk_pm_en (1'b0 ),
.o_pm_master_state (pm_master_state ),
.o_pm_slave_state (pm_slave_state ),
.i_sys_aux_pwr_det (1'b1 ),
//error handling
.i_app_hdr_valid (app_hdr_valid ),
.i_app_hdr_log (app_hdr_log ),
.i_app_err_bus (app_err_bus ),
.i_app_err_advisory (app_err_advisory ),
.o_cfg_send_cor_err_mux (cfg_send_cor_err_mux ),
.o_cfg_send_nf_err_mux (cfg_send_nf_err_mux ),
.o_cfg_send_f_err_mux (cfg_send_f_err_mux ),
.o_cfg_sys_err_rc (cfg_sys_err_rc ),
.o_cfg_aer_rc_err_mux (cfg_aer_rc_err_mux ),
//radm timeout
.o_radm_cpl_timeout (radm_cpl_timeout ),
.o_radm_timeout_cpl_tc (radm_timeout_cpl_tc ),
.o_radm_timeout_cpl_tag (radm_timeout_cpl_tag ),
.o_radm_timeout_cpl_attr (radm_timeout_cpl_attr ),
.o_radm_timeout_cpl_len (radm_timeout_cpl_len ),
//configuration signals
.o_cfg_max_rd_req_size (cfg_max_rd_req_size ),
.o_cfg_bus_master_en (cfg_bus_master_en ),
.o_cfg_max_payload_size (cfg_max_payload_size ),
.o_cfg_ext_tag_en (cfg_ext_tag_en ),
.o_cfg_rcb (cfg_rcb ),
.o_cfg_mem_space_en (cfg_mem_space_en ),
.o_cfg_pm_no_soft_rst (cfg_pm_no_soft_rst ),
.o_cfg_crs_sw_vis_en (cfg_crs_sw_vis_en ),
.o_cfg_no_snoop_en (cfg_no_snoop_en ),
.o_cfg_relax_order_en (cfg_relax_order_en ),
.o_cfg_tph_req_en (cfg_tph_req_en ),
.o_cfg_pf_tph_st_mode (cfg_pf_tph_st_mode ),
.o_cfg_pbus_num (cfg_pbus_num ),
.o_cfg_pbus_dev_num (cfg_pbus_dev_num ),
.o_rbar_ctrl_update (rbar_ctrl_update ),
.o_cfg_atomic_req_en (cfg_atomic_req_en ),
.o_cfg_atomic_egress_block ( ),
//debug signals
.o_radm_idle (radm_idle ),
.o_radm_q_not_empty (radm_q_not_empty ),
.o_radm_qoverflow (radm_qoverflow ),
.i_diag_ctrl_bus (diag_ctrl_bus ),
.i_dyn_debug_info_sel (dyn_debug_info_sel ),
.o_cfg_link_auto_bw_mux (cfg_link_auto_bw_mux ),
.o_cfg_bw_mgt_mux (cfg_bw_mgt_mux ),
.o_cfg_pme_mux (cfg_pme_mux ),
.o_debug_info_mux (debug_info_mux ),
.i_app_ras_des_sd_hold_ltssm (app_ras_des_sd_hold_ltssm ),
.i_app_ras_des_tba_ctrl (app_ras_des_tba_ctrl ),
//misc
.o_cfg_ido_req_en (cfg_ido_req_en ),
.o_cfg_ido_cpl_en (cfg_ido_cpl_en ),
.o_xadm_ph_cdts (xadm_ph_cdts ),
.o_xadm_pd_cdts (xadm_pd_cdts ),
.o_xadm_nph_cdts (xadm_nph_cdts ),
.o_xadm_npd_cdts (xadm_npd_cdts ),
.o_xadm_cplh_cdts (xadm_cplh_cdts ),
.o_xadm_cpld_cdts (xadm_cpld_cdts ),
//system signal
.i_rx_lane_flip_en (rx_lane_flip_en ),
.i_tx_lane_flip_en (tx_lane_flip_en ),
.o_smlh_link_up (smlh_link_up ),
.o_rdlh_link_up (rdlh_link_up ),
.i_app_req_retry_en (app_req_retry_en ),
.o_smlh_ltssm_state (smlh_ltssm_state ),
.o_refck2core_0 (ref_clk )
);
endmodule |
module interpolation_ram
(
wr_data , //input write data
wr_addr , //input write address
wr_en , //input write enable
wr_clk , //input write clock
wr_rst , //input write reset
rd_data , //output read data
rd_addr , //input read address
rd_clk , //input read clock
rd_rst //input read reset
);
localparam WR_ADDR_WIDTH = 11 ; // @IPC int 9,20
localparam WR_DATA_WIDTH = 32 ; // @IPC int 1,1152
localparam RD_ADDR_WIDTH = 11 ; // @IPC int 9,20
localparam RD_DATA_WIDTH = 32 ; // @IPC int 1,1152
localparam OUTPUT_REG = 0 ; // @IPC bool
localparam RD_OCE_EN = 0 ; // @IPC bool
localparam RD_CLK_OR_POL_INV = 0 ; // @IPC bool
localparam RESET_TYPE = "ASYNC" ; // @IPC enum Sync_Internally,SYNC,ASYNC
localparam POWER_OPT = 0 ; // @IPC bool
localparam INIT_FILE = "NONE" ; // @IPC string
localparam INIT_FORMAT = "BIN" ; // @IPC enum BIN,HEX
localparam WR_BYTE_EN = 0 ; // @IPC bool
localparam BE_WIDTH = 1 ; // @IPC int 2,128
localparam RD_BE_WIDTH = 1 ; // @IPC int 2,128
localparam BYTE_SIZE = 8 ; // @IPC enum 8,9
localparam INIT_EN = 0 ; // @IPC bool
localparam SAMEWIDTH_EN = 1 ; // @IPC bool
localparam WR_CLK_EN = 0 ; // @IPC bool
localparam RD_CLK_EN = 0 ; // @IPC bool
localparam WR_ADDR_STROBE_EN = 0 ; // @IPC bool
localparam RD_ADDR_STROBE_EN = 0 ; // @IPC bool
localparam RESET_TYPE_CTRL = (RESET_TYPE == "ASYNC") ? "ASYNC_RESET" :
(RESET_TYPE == "SYNC") ? "SYNC_RESET" : "ASYNC_RESET_SYNC_RELEASE";
localparam DEVICE_NAME = "PGL50H";
localparam WR_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? 10 : WR_DATA_WIDTH;
localparam RD_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? 10 : RD_DATA_WIDTH;
localparam SIM_DEVICE = ((DEVICE_NAME == "PGL22G") || (DEVICE_NAME == "PGL22GS")) ? "PGL22G" : "LOGOS";
input [WR_DATA_WIDTH-1:0] wr_data ; //input write data [WR_DATA_WIDTH-1:0]
input [WR_ADDR_WIDTH-1:0] wr_addr ; //input write address [WR_ADDR_WIDTH-1:0]
input wr_en ; //input write enable
input wr_clk ; //input write clock
input wr_rst ; //input write reset
output [RD_DATA_WIDTH-1:0] rd_data ; //output read data [C_RD_DATA_WIDTH-1:0]
input [RD_ADDR_WIDTH-1:0] rd_addr ; //input read address [RD_ADDR_WIDTH-1:0]
input rd_clk ; //input read clock
input rd_rst ; //input read reset
wire [WR_DATA_WIDTH-1:0] wr_data ; //input write data [WR_DATA_WIDTH-1:0]
wire [WR_ADDR_WIDTH-1:0] wr_addr ; //input write address [WR_ADDR_WIDTH-1:0]
wire wr_en ; //input write enable
wire wr_clk ; //input write clock
wire wr_clk_en ; //input write clock enable
wire wr_rst ; //input write reset
wire [BE_WIDTH-1:0] wr_byte_en ; //input write reset
wire wr_addr_strobe ; //input write address string
wire [RD_DATA_WIDTH-1:0] rd_data ; //output read data [C_RD_DATA_WIDTH-1:0]
wire [RD_ADDR_WIDTH-1:0] rd_addr ; //input read address [RD_ADDR_WIDTH-1:0]
wire rd_clk ; //input read clock
wire rd_clk_en ; //input read clock enable
wire rd_rst ; //input read reset
wire rd_oce ; //input read output register enable
wire rd_addr_strobe ; //input read address string
wire [BE_WIDTH-1:0] wr_byte_en_mux ;
wire rd_oce_mux ;
wire wr_clk_en_mux ;
wire rd_clk_en_mux ;
wire wr_addr_strobe_mux ;
wire rd_addr_strobe_mux ;
wire [WR_DATA_WIDTH_WRAP-1 : 0] wr_data_wrap;
wire [RD_DATA_WIDTH_WRAP-1 : 0] rd_data_wrap;
assign wr_byte_en_mux = (WR_BYTE_EN == 1) ? wr_byte_en : -1 ;
assign rd_oce_mux = (RD_OCE_EN == 1) ? rd_oce :
(OUTPUT_REG == 1) ? 1'b1 : 1'b0 ;
assign wr_clk_en_mux = (WR_CLK_EN == 1) ? wr_clk_en : 1'b1 ;
assign rd_clk_en_mux = (RD_CLK_EN == 1) ? rd_clk_en : 1'b1 ;
assign wr_addr_strobe_mux = (WR_ADDR_STROBE_EN ==1) ? wr_addr_strobe : 1'b0 ;
assign rd_addr_strobe_mux = (RD_ADDR_STROBE_EN ==1) ? rd_addr_strobe : 1'b0 ;
assign wr_data_wrap = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? {{(WR_DATA_WIDTH_WRAP - WR_DATA_WIDTH){1'b0}},wr_data} : wr_data;
assign rd_data = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? rd_data_wrap[RD_DATA_WIDTH-1 : 0] : rd_data_wrap;
//ipml_sdpram IP instance
ipml_sdpram_v1_6_interpolation_ram
#(
.c_SIM_DEVICE (SIM_DEVICE ),
.c_WR_ADDR_WIDTH (WR_ADDR_WIDTH ),
.c_WR_DATA_WIDTH (WR_DATA_WIDTH_WRAP ),
.c_RD_ADDR_WIDTH (RD_ADDR_WIDTH ),
.c_RD_DATA_WIDTH (RD_DATA_WIDTH_WRAP ),
.c_OUTPUT_REG (OUTPUT_REG ),
.c_RD_OCE_EN (RD_OCE_EN ),
.c_WR_ADDR_STROBE_EN (WR_ADDR_STROBE_EN ),
.c_RD_ADDR_STROBE_EN (RD_ADDR_STROBE_EN ),
.c_WR_CLK_EN (WR_CLK_EN ),
.c_RD_CLK_EN (RD_CLK_EN ),
.c_RD_CLK_OR_POL_INV (RD_CLK_OR_POL_INV ),
.c_RESET_TYPE (RESET_TYPE_CTRL ),
.c_POWER_OPT (POWER_OPT ),
.c_INIT_FILE ("NONE" ),
.c_INIT_FORMAT (INIT_FORMAT ),
.c_WR_BYTE_EN (WR_BYTE_EN ),
.c_BE_WIDTH (BE_WIDTH )
) U_ipml_sdpram_interpolation_ram
(
.wr_data (wr_data_wrap ),//input write data
.wr_addr (wr_addr ),//input write address
.wr_en (wr_en ),//input write enable
.wr_clk (wr_clk ),//input write clock
.wr_clk_en (wr_clk_en_mux ),//input write clock enable
.wr_rst (wr_rst ),//input write reset
.wr_byte_en (wr_byte_en_mux ),//input write byte enable
.wr_addr_strobe (wr_addr_strobe_mux ),//input write address strobe
.rd_data (rd_data_wrap ),//output read data
.rd_addr (rd_addr ),//input read address
.rd_clk (rd_clk ),//input read clock
.rd_clk_en (rd_clk_en_mux ),//input read clock enable
.rd_rst (rd_rst ),//input read reset
.rd_oce (rd_oce_mux ),//input read output register enable
.rd_addr_strobe (rd_addr_strobe_mux ) //input read address strobe
);
endmodule |
module hdmi_pcie_fifo_prefetch
(
wr_clk , // input write clock
wr_rst , // input write reset
rd_clk , // input read clock
rd_rst , // input read reset
wr_en , // input write enable 1 active
wr_vld ,
wr_data , // input write data
rd_en , // input read enable
rd_vld ,
rd_data // output read data
);
localparam WR_DEPTH_WIDTH = 15 ; // @IPC int 9,20
localparam WR_DATA_WIDTH = 16 ; // @IPC int 1,1152
localparam RD_DEPTH_WIDTH = 12 ; // @IPC int 9,20
localparam RD_DATA_WIDTH = 128 ; // @IPC int 1,1152
localparam RESET_TYPE = "ASYNC" ; // @IPC enum Sync_Internally,SYNC,ASYNC
localparam POWER_OPT = 0 ; // @IPC bool
localparam FIFO_TYPE = "ASYN_FIFO" ; // @IPC enum SYN_FIFO,ASYN_FIFO
localparam ASYN_FIFO_EN = "1" ; // @IPC bool
localparam RESET_TYPE_SEL = (RESET_TYPE == "ASYNC") ? "ASYNC_RESET" :
(RESET_TYPE == "SYNC") ? "SYNC_RESET": "ASYNC_RESET_SYNC_RELEASE";
localparam FIFO_TYPE_SEL = (FIFO_TYPE=="SYN_FIFO") ? "SYN" : "ASYN" ; // @IPC enum SYN,ASYN
localparam DEVICE_NAME = "PGL50H";
localparam WR_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? 10 : WR_DATA_WIDTH;
localparam RD_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? 10 : RD_DATA_WIDTH;
input wr_clk ; // input write clock
input wr_rst ; // input write reset
input rd_clk ; // input read clock
input rd_rst ; // input read reset
input [WR_DATA_WIDTH-1 : 0] wr_data ; // input write data
input wr_en ; // input write enable 1 active
output wr_vld ;
output [RD_DATA_WIDTH-1 : 0] rd_data ; // output read data
input rd_en ; // input read enable
output rd_vld ;
wire [WR_DATA_WIDTH-1 : 0] wr_data ; // input write data
wire wr_en ; // input write enable 1 active
wire wr_clk ; // input write clock
wire wr_rst ; // input write reset
wire [RD_DATA_WIDTH-1 : 0] rd_data ; // output read data
wire rd_en ; // input read enable
wire rd_clk ; // input read clock
wire rd_rst ; // input read reset
wire wr_vld;
wire rd_vld;
wire [WR_DATA_WIDTH_WRAP-1 : 0] wr_data_wrap;
wire [RD_DATA_WIDTH_WRAP-1 : 0] rd_data_wrap;
assign wr_data_wrap = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? {{(WR_DATA_WIDTH_WRAP - WR_DATA_WIDTH){1'b0}},wr_data} : wr_data;
assign rd_data = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? rd_data_wrap[RD_DATA_WIDTH-1 : 0] : rd_data_wrap;
//ipml_prefetch_fifo IP instance
ipml_prefetch_fifo_v1_6_hdmi_pcie_fifo
#(
.c_WR_DEPTH_WIDTH (WR_DEPTH_WIDTH ), // fifo depth width 9 -- 20 legal value:9~20
.c_WR_DATA_WIDTH (WR_DATA_WIDTH_WRAP ), // write data width 1 -- 1152 1)WR_BYTE_EN =0 legal value:1~1152 2)WR_BYTE_EN=1 legal value:2^N or 9*2^N
.c_RD_DEPTH_WIDTH (RD_DEPTH_WIDTH ), // read address width 9 -- 20 legal value:1~20
.c_RD_DATA_WIDTH (RD_DATA_WIDTH_WRAP ), // read data width 1 -- 1152 1)WR_BYTE_EN =0 legal value:1~1152 2)WR_BYTE_EN=1 legal value:2^N or 9*2^N
.c_RESET_TYPE (RESET_TYPE_SEL ), // reset type legal valve "ASYNC_RESET_SYNC_RELEASE" "SYNC_RESET" "ASYNC_RESET"
.c_POWER_OPT (POWER_OPT ), // 0 :normal mode 1:low power mode legal value:0 or 1
.c_FIFO_TYPE (FIFO_TYPE_SEL ) // fifo type legal value "SYN" or "ASYN"
) U_ipml_fifo_hdmi_pcie_fifo
(
.wr_clk ( wr_clk ) , // input write clock
.wr_rst ( wr_rst ) , // input write reset
.rd_clk ( rd_clk ) , // input read clock
.rd_rst ( rd_rst ) , // input read reset
.wr_en ( wr_en ) , // input write enable 1 active
.wr_vld ( wr_vld ) ,
.wr_data ( wr_data_wrap ) , // input write data
.rd_en ( rd_en ) , // input read enable
.rd_vld ( rd_vld ) ,
.rd_data ( rd_data_wrap ) // output read data
);
endmodule |
module hdmi_pcie_fifo_tb;
localparam T_CLK_PERIOD = 10 ; //clock a half perid
localparam T_RST_TIME = 200 ; //reset time
localparam WR_DEPTH_WIDTH = 15 ; // @IPC int 9,20
localparam WR_DATA_WIDTH = 16 ; // @IPC int 1,1152
localparam RD_DEPTH_WIDTH = 12 ; // @IPC int 9,20
localparam RD_DATA_WIDTH = 128 ; // @IPC int 1,1152
localparam OUTPUT_REG = 0 ; // @IPC bool
localparam RD_OCE_EN = 0 ; // @IPC bool
localparam RD_CLK_OR_POL_INV = 0 ; // @IPC bool
localparam RESET_TYPE = "ASYNC" ; // @IPC enum Sync_Internally,SYNC,ASYNC
localparam POWER_OPT = 0 ; // @IPC bool
localparam WR_BYTE_EN = 0 ; // @IPC bool
localparam BE_WIDTH = 1 ; // @IPC int 2,128
localparam FIFO_TYPE = "ASYN_FIFO" ; // @IPC enum SYN_FIFO,ASYN_FIFO
localparam ASYN_FIFO_EN = "1" ; // @IPC bool
localparam ALMOST_FULL_NUM = 1020 ; // @IPC int
localparam ALMOST_EMPTY_NUM = 4 ; // @IPC int
localparam FULL_WL_EN = 1 ; // @IPC bool
localparam EMPTY_WL_EN = 1 ; // @IPC bool
localparam BYTE_SIZE = 8 ; // @IPC enum 8,9
localparam RESET_TYPE_SEL = (RESET_TYPE == "ASYNC" ) ? "ASYNC_RESET" :
(RESET_TYPE == "SYNC" ) ? "SYNC_RESET" : "ASYNC_RESET_SYNC_RELEASE" ;
localparam FIFO_TYPE_SEL = (FIFO_TYPE == "SYN_FIFO") ? "SYNC" : "ASYNC" ;
localparam DEVICE_NAME = "PGL50H";
localparam WR_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? 10 : WR_DATA_WIDTH;
localparam RD_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? 10 : RD_DATA_WIDTH;
// variable declaration
reg clk ;
wire tb_clk ;
reg tb_rst ;
wire [WR_DATA_WIDTH-1 : 0] tb_wrdata ;
reg tb_wr_en ;
wire tb_wr_full ;
reg [BE_WIDTH-1 : 0] tb_wr_byte_en ;
wire [WR_DEPTH_WIDTH : 0] tb_wr_water_level ;
wire tb_almost_full ;
wire [RD_DATA_WIDTH-1 : 0] tb_rddata ;
reg [RD_DATA_WIDTH-1 : 0] tb_rddata_dly ;
reg tb_rd_en ;
reg tb_rd_en_dly ;
reg tb_rd_en_2dly ;
wire tb_rd_empty ;
reg tb_rd_oce ;
wire [RD_DEPTH_WIDTH : 0] tb_rd_water_level ;
wire tb_almost_empty ;
reg [RD_DEPTH_WIDTH : 0] tb_rd_addr ;
reg [WR_DEPTH_WIDTH : 0] tb_wr_addr ;
reg [WR_DATA_WIDTH-1 : 0] tb_wrdata_cnt ;
reg [RD_DATA_WIDTH-1 : 0] tb_rddata_cnt ;
reg [RD_DATA_WIDTH-1 : 0] tb_rddata_cnt_dly ;
reg [RD_DATA_WIDTH-1 : 0] tb_expected_data ;
reg check_err ;
reg [2:0] results_cnt ;
//********************************************************* CGU ********************************************************************************
initial
begin
tb_wr_en = 1'b0 ;
tb_wr_addr = {WR_DEPTH_WIDTH+1{1'b0}} ;
tb_wrdata_cnt = {WR_DATA_WIDTH{1'b0}} ;
tb_rd_en = 1'b0;
tb_rd_addr = {RD_DEPTH_WIDTH+1{1'b0}} ;
tb_rddata_cnt = {RD_DATA_WIDTH{1'b0}} ;
tb_rst = 1'b1 ;
#T_RST_TIME;
tb_rst = 1'b0 ;
clk = 1'b0;
if(RD_OCE_EN == 1)
tb_rd_oce = 1'b1 ;
else
tb_rd_oce = 1'b0 ;
if(WR_BYTE_EN == 1)
tb_wr_byte_en = {BE_WIDTH{1'b1}} ;
else
tb_wr_byte_en = {BE_WIDTH{1'b0}} ;
end
initial
begin
forever #(T_CLK_PERIOD/2) clk = ~clk ;
end
assign tb_clk = (RD_CLK_OR_POL_INV == 1) ? ~clk : clk;
task write_fifo ;
input wr_fifo ;
begin
tb_wr_addr = {WR_DEPTH_WIDTH+1{1'b0}} ;
while (tb_wr_addr <= (2**WR_DEPTH_WIDTH))
begin
@(posedge clk) ;
tb_wr_en = 1'b1 ;
tb_wr_addr = tb_wr_addr + {{WR_DEPTH_WIDTH{1'b0}},1'b1} ;
end
tb_wr_en = 1'b0 ;
end
endtask
task read_fifo ;
input rd_fifo ;
begin
tb_rd_addr = {RD_DEPTH_WIDTH+1{1'b0}} ;
while (tb_rd_addr <= (2**RD_DEPTH_WIDTH))
begin
@(posedge clk) ;
tb_rd_en = 1'b1 ;
tb_rd_addr = tb_rd_addr + {{RD_DEPTH_WIDTH{1'b0}},1'b1} ;
end
tb_rd_en =1'b0 ;
end
endtask
initial
begin
$display("Writing FIFO") ;
write_fifo(1) ;
#10;
$display("Reading FIFO") ;
read_fifo(1) ;
$display("FIFO simulation is done.") ;
if (|results_cnt)
$display("Simulation Failed due to Error Found.") ;
else
$display("Simulation Success.") ;
#500 ;
$finish ;
end
always@(posedge clk or posedge tb_rst)
begin
if(tb_rst)
tb_wrdata_cnt <= {WR_DATA_WIDTH{1'b1}} ;
else if (tb_wr_en)
tb_wrdata_cnt <= tb_wrdata_cnt - {{WR_DATA_WIDTH-1{1'b0}},1'b1} ;
end
assign tb_wrdata = tb_wrdata_cnt ;
always@(posedge clk or posedge tb_rst)
begin
if(tb_rst)
tb_rddata_cnt <= {RD_DATA_WIDTH{1'b1}} ;
else if (!tb_rd_en)
tb_rddata_cnt <= {RD_DATA_WIDTH{1'b1}} ;
else
tb_rddata_cnt <= tb_rddata_cnt - {{RD_DATA_WIDTH-1{1'b0}},1'b1} ;
end
always@(posedge tb_clk or posedge tb_rst)
begin
if (tb_rst)
tb_rddata_cnt_dly <= {RD_DATA_WIDTH{1'b0}} ;
else
tb_rddata_cnt_dly <= tb_rddata_cnt ;
end
always@(posedge tb_clk or posedge tb_rst)
begin
if (tb_rst)
begin
tb_rd_en_dly <= 1'b0;
tb_rd_en_2dly <= 1'b0;
tb_rddata_dly <= 0;
end
else
begin
tb_rd_en_dly <= tb_rd_en;
tb_rd_en_2dly <= tb_rd_en_dly;
tb_rddata_dly <= tb_rddata;
end
end
always@(posedge tb_clk or posedge tb_rst)
begin
if (tb_rst)
tb_expected_data <= {RD_DATA_WIDTH{1'b1}} ;
else if (RD_OCE_EN == 1'b1)
begin
if (tb_rd_oce)
tb_expected_data <= tb_rddata_cnt_dly ;
end
else if (OUTPUT_REG == 1'b1)
tb_expected_data <= tb_rddata_cnt_dly ;
else
tb_expected_data <= tb_rddata_cnt ;
end
always@(posedge tb_clk or posedge tb_rst)
begin
if(tb_rst)
check_err <= 1'b0;
else if (((RD_OCE_EN == 1'b1) && (tb_rd_en_2dly) && (tb_rd_oce))
|| ((OUTPUT_REG == 1'b0) && (tb_rd_en_dly))
|| ((OUTPUT_REG == 1'b1) && (tb_rd_en_2dly)))
check_err <= (tb_expected_data != tb_rddata) ;
else
check_err <= 1'b0;
end
always @(posedge tb_clk or posedge tb_rst)
begin
if (tb_rst)
results_cnt <= 3'b000 ;
else if (&results_cnt)
results_cnt <= 3'b100 ;
else if (check_err)
results_cnt <= results_cnt + 3'd1 ;
end
//***************************************************************** DUT INST **************************************************************************************
GTP_GRS GRS_INST(
.GRS_N(1'b1)
) ;
hdmi_pcie_fifo U_hdmi_pcie_fifo (
.wr_data ( tb_wrdata ) ,
.wr_en ( tb_wr_en ) ,
.wr_clk ( clk ) ,
.wr_rst ( tb_rst ) ,
.wr_full ( tb_wr_full ) ,
.wr_water_level ( tb_wr_water_level ) ,
.almost_full ( tb_almost_full ) ,
.rd_data ( tb_rddata ) ,
.rd_en ( tb_rd_en ) ,
.rd_clk ( clk ) ,
.rd_rst ( tb_rst ) ,
.rd_empty ( tb_rd_empty ) ,
.rd_water_level ( tb_rd_water_level ) ,
.almost_empty ( tb_almost_empty )
) ;
endmodule |
module hdmi_pcie_fifo
(
wr_clk , // input write clock
wr_rst , // input write reset
wr_en , // input write enable 1 active
wr_data , // input write data
wr_full , // output write full flag 1 active
wr_water_level , // output write water level
rd_clk , // input read clock
rd_rst , // input read reset
rd_en , // input read enable
rd_data , // output read data
almost_full , // output write almost full
rd_empty , // output read empty
rd_water_level , // output read water level
almost_empty // output write almost empty
);
localparam WR_DEPTH_WIDTH = 15 ; // @IPC int 9,20
localparam WR_DATA_WIDTH = 16 ; // @IPC int 1,1152
localparam RD_DEPTH_WIDTH = 12 ; // @IPC int 9,20
localparam RD_DATA_WIDTH = 128 ; // @IPC int 1,1152
localparam OUTPUT_REG = 0 ; // @IPC bool
localparam RD_OCE_EN = 0 ; // @IPC bool
localparam RD_CLK_OR_POL_INV = 0 ; // @IPC bool
localparam RESET_TYPE = "ASYNC" ; // @IPC enum Sync_Internally,SYNC,ASYNC
localparam POWER_OPT = 0 ; // @IPC bool
localparam WR_BYTE_EN = 0 ; // @IPC bool
localparam BE_WIDTH = 1 ; // @IPC int 2,128
localparam FIFO_TYPE = "ASYN_FIFO" ; // @IPC enum SYN_FIFO,ASYN_FIFO
localparam ASYN_FIFO_EN = "1" ; // @IPC bool
localparam ALMOST_FULL_NUM = 1020 ; // @IPC int
localparam ALMOST_EMPTY_NUM = 4 ; // @IPC int
localparam FULL_WL_EN = 1 ; // @IPC bool
localparam EMPTY_WL_EN = 1 ; // @IPC bool
localparam BYTE_SIZE = 8 ; // @IPC enum 8,9
localparam RESET_TYPE_SEL = (RESET_TYPE == "ASYNC") ? "ASYNC_RESET" :
(RESET_TYPE == "SYNC") ? "SYNC_RESET": "ASYNC_RESET_SYNC_RELEASE";
localparam FIFO_TYPE_SEL = (FIFO_TYPE=="SYN_FIFO") ? "SYN" : "ASYN" ; // @IPC enum SYN,ASYN
localparam DEVICE_NAME = "PGL50H";
localparam WR_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? 10 : WR_DATA_WIDTH;
localparam RD_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? 10 : RD_DATA_WIDTH;
localparam SIM_DEVICE = ((DEVICE_NAME == "PGL22G") || (DEVICE_NAME == "PGL22GS")) ? "PGL22G" : "LOGOS";
input [WR_DATA_WIDTH-1 : 0] wr_data ; // input write data
input wr_en ; // input write enable 1 active
input wr_clk ; // input write clock
input wr_rst ; // input write reset
output wr_full ; // output write full flag 1 active
output almost_full ; // output write almost full
output [WR_DEPTH_WIDTH : 0] wr_water_level ; // output write water level
output [RD_DATA_WIDTH-1 : 0] rd_data ; // output read data
input rd_en ; // input read enable
input rd_clk ; // input read clock
input rd_rst ; // input read reset
output rd_empty ; // output read empty
output almost_empty ; // output read water level
output [RD_DEPTH_WIDTH : 0] rd_water_level ;
wire [WR_DATA_WIDTH-1 : 0] wr_data ; // input write data
wire wr_en ; // input write enable 1 active
wire wr_clk ; // input write clock
wire wr_full ; // input write full flag 1 active
wire wr_rst ; // input write reset
wire [BE_WIDTH-1 : 0] wr_byte_en ; // input write byte enable
wire almost_full ; // output write almost full
wire [WR_DEPTH_WIDTH : 0] wr_water_level ; // output write water level
wire [RD_DATA_WIDTH-1 : 0] rd_data ; // output read data
wire rd_en ; // input read enable
wire rd_clk ; // input read clock
wire rd_empty ; // output read empty
wire rd_rst ; // input read reset
wire rd_oce ; // output read output register enable
wire almost_empty ; // output read water level
wire [RD_DEPTH_WIDTH : 0] rd_water_level ;
wire [BE_WIDTH-1:0] wr_byte_en_mux ;
wire rd_oce_mux ;
wire [WR_DATA_WIDTH_WRAP-1 : 0] wr_data_wrap;
wire [RD_DATA_WIDTH_WRAP-1 : 0] rd_data_wrap;
assign wr_byte_en_mux = (WR_BYTE_EN == 1) ? wr_byte_en : -1 ;
assign rd_oce_mux = (RD_OCE_EN == 1) ? rd_oce :
(OUTPUT_REG == 1) ? 1'b1 : 1'b0 ;
assign wr_data_wrap = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? {{(WR_DATA_WIDTH_WRAP - WR_DATA_WIDTH){1'b0}},wr_data} : wr_data;
assign rd_data = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? rd_data_wrap[RD_DATA_WIDTH-1 : 0] : rd_data_wrap;
//ipml_sdpram IP instance
ipml_fifo_v1_6_hdmi_pcie_fifo
#(
.c_SIM_DEVICE (SIM_DEVICE ),
.c_WR_DEPTH_WIDTH (WR_DEPTH_WIDTH ), // fifo depth width 9 -- 20 legal value:9~20
.c_WR_DATA_WIDTH (WR_DATA_WIDTH_WRAP ), // write data width 1 -- 1152 1)WR_BYTE_EN =0 legal value:1~1152 2)WR_BYTE_EN=1 legal value:2^N or 9*2^N
.c_RD_DEPTH_WIDTH (RD_DEPTH_WIDTH ), // read address width 9 -- 20 legal value:1~20
.c_RD_DATA_WIDTH (RD_DATA_WIDTH_WRAP ), // read data width 1 -- 1152 1)WR_BYTE_EN =0 legal value:1~1152 2)WR_BYTE_EN=1 legal value:2^N or 9*2^N
.c_OUTPUT_REG (OUTPUT_REG ), // output register legal value:0 or 1
.c_RD_OCE_EN (RD_OCE_EN ),
.c_RESET_TYPE (RESET_TYPE_SEL ), // reset type legal valve "ASYNC_RESET_SYNC_RELEASE" "SYNC_RESET" "ASYNC_RESET"
.c_POWER_OPT (POWER_OPT ), // 0 :normal mode 1:low power mode legal value:0 or 1
.c_RD_CLK_OR_POL_INV (RD_CLK_OR_POL_INV ), // clk polarity invert for output register legal value: 0 or 1
.c_WR_BYTE_EN (WR_BYTE_EN ), // byte write enable legal value: 0 or 1
.c_BE_WIDTH (BE_WIDTH ), // byte width legal value: 1~128
.c_FIFO_TYPE (FIFO_TYPE_SEL ), // fifo type legal value "SYN" or "ASYN"
.c_ALMOST_FULL_NUM (ALMOST_FULL_NUM ), // almost full number
.c_ALMOST_EMPTY_NUM (ALMOST_EMPTY_NUM ) // almost full number
) U_ipml_fifo_hdmi_pcie_fifo
(
.wr_clk ( wr_clk ) , // input write clock
.wr_rst ( wr_rst ) , // input write reset
.wr_en ( wr_en ) , // input write enable 1 active
.wr_data ( wr_data_wrap ) , // input write data
.wr_full ( wr_full ) , // input write full flag 1 active
.wr_byte_en ( wr_byte_en_mux ) , // input write byte enable
.almost_full ( almost_full ) , // output write almost full
.wr_water_level ( wr_water_level ) , // output write water level
.rd_clk ( rd_clk ) , // input read clock
.rd_rst ( rd_rst ) , // input read reset
.rd_en ( rd_en ) , // input read enable
.rd_data ( rd_data_wrap ) , // output read data
.rd_oce ( rd_oce_mux ) , // output read output register enable
.rd_empty ( rd_empty ) , // output read empty
.almost_empty ( almost_empty ) , // output read water level
.rd_water_level ( rd_water_level )
);
endmodule |
module pll_cfg_tb ();
localparam CLKIN_FREQ = 50.0;
localparam integer FBDIV_SEL = 0;
localparam FBMODE = "FALSE";
// Generate testbench reset and clock
reg pll_rst;
reg rstodiv;
reg pll_pwd;
reg clkin1;
reg clkin2;
reg clkin_dsel;
reg clkin_dsel_en;
reg pfden;
reg clkout0_gate;
reg clkout0_2pad_gate;
reg clkout1_gate;
reg clkout2_gate;
reg clkout3_gate;
reg clkout4_gate;
reg clkout5_gate;
reg [9:0] dyn_idiv;
reg [9:0] dyn_odiv0;
reg [9:0] dyn_odiv1;
reg [9:0] dyn_odiv2;
reg [9:0] dyn_odiv3;
reg [9:0] dyn_odiv4;
reg [9:0] dyn_fdiv;
reg [9:0] dyn_duty0;
reg [9:0] dyn_duty1;
reg [9:0] dyn_duty2;
reg [9:0] dyn_duty3;
reg [9:0] dyn_duty4;
reg [12:0] dyn_phase0;
reg [12:0] dyn_phase1;
reg [12:0] dyn_phase2;
reg [12:0] dyn_phase3;
reg [12:0] dyn_phase4;
reg err_chk;
reg [2:0] results_cnt;
reg rst_n;
reg clk_tb;
wire clkout0;
wire clkout1;
wire clkout2;
wire clkout3;
wire clkout4;
wire clkfb = (FBMODE == "FALSE") ? clkin1 :
(FBDIV_SEL == 0 ) ? clkout0 :
(FBDIV_SEL == 1 ) ? clkout1 :
(FBDIV_SEL == 2 ) ? clkout2 :
(FBDIV_SEL == 3 ) ? clkout3 :
(FBDIV_SEL == 4 ) ? clkout4 : clkin1;
initial
begin
rst_n = 0;
#20
rst_n = 1;
end
initial
begin
clk_tb = 0;
forever #1 clk_tb = ~clk_tb;
end
parameter CLOCK_PERIOD1 = (500.0/CLKIN_FREQ);
//parameter CLOCK_PERIOD2 = (500.0/CLKIN_FREQ);
initial
begin
clkin1 = 0;
forever #(CLOCK_PERIOD1) clkin1 = ~clkin1;
end
initial
begin
pll_pwd = 0;
pll_rst = 0;
rstodiv = 0;
clkin_dsel = 0;
clkin_dsel_en = 0;
pfden = 0;
clkout0_gate = 0;
clkout0_2pad_gate = 0;
clkout1_gate = 0;
clkout2_gate = 0;
clkout3_gate = 0;
clkout4_gate = 0;
clkout5_gate = 0;
dyn_idiv = 10'd2;
dyn_fdiv = 10'd32;
dyn_odiv0 = 10'd100;
dyn_odiv1 = 10'd100;
dyn_odiv2 = 10'd100;
dyn_odiv3 = 10'd100;
dyn_odiv4 = 10'd100;
dyn_duty0 = 10'd100;
dyn_duty1 = 10'd100;
dyn_duty2 = 10'd100;
dyn_duty3 = 10'd100;
dyn_duty4 = 10'd100;
dyn_phase0 = 13'd16;
dyn_phase1 = 13'd16;
dyn_phase2 = 13'd16;
dyn_phase3 = 13'd16;
dyn_phase4 = 13'd16;
#10
pll_pwd = 1;
#20
pll_pwd = 0;
pll_rst = 0;
#10
pll_rst = 1;
#20
pll_rst = 0;
#1000000
dyn_odiv0 = 10'd200;
dyn_odiv1 = 10'd200;
dyn_odiv2 = 10'd200;
dyn_odiv3 = 10'd200;
dyn_odiv4 = 10'd200;
dyn_duty0 = 10'd200;
dyn_duty1 = 10'd200;
dyn_duty2 = 10'd200;
dyn_duty3 = 10'd200;
dyn_duty4 = 10'd200;
#3000000
$finish;
end
initial
begin
$display("Simulation Starts.") ;
$display("Simulation is done.") ;
if (|results_cnt)
$display("Simulation Failed due to Error Found.") ;
else
$display("Simulation Success.") ;
end
GTP_GRS GRS_INST(
.GRS_N(1'b1)
);
pll_cfg U_pll_cfg (
.clkout0(clkout0),
.clkout1(clkout1),
.clkin1(clkin1),
.pll_lock(pll_lock)
);
//******************Results Cheching************************
reg [2:0] pll_lock_shift;
wire pll_lock_pulse = ~pll_lock_shift[2] & pll_lock_shift[1];
always @( posedge clk_tb or negedge rst_n )
begin
if (!rst_n)
begin
pll_lock_shift <= 3'd0;
end
else
begin
pll_lock_shift[0] <= pll_lock;
pll_lock_shift[2:1] <= pll_lock_shift[1:0];
end
end
reg [1:0] pll_lock_pulse_cnt;
always @( posedge clk_tb or negedge rst_n )
begin
if (!rst_n)
begin
pll_lock_pulse_cnt <= 2'd0;
end
else
begin
if (pll_lock_pulse)
pll_lock_pulse_cnt <= pll_lock_pulse_cnt + 1;
else ;
end
end
always @( posedge clk_tb or negedge rst_n )
begin
if (!rst_n)
begin
err_chk <= 1'b0;
end
else
begin
if ((!pll_lock) && (^pll_lock_pulse_cnt))
err_chk <= 1'b1;
else if (pll_lock_pulse_cnt[1])
err_chk <= 1'b1;
else
err_chk <= 1'b0;
end
end
always @(posedge clk_tb or negedge rst_n)
begin
if (!rst_n)
results_cnt <= 3'b000 ;
else if (&results_cnt)
results_cnt <= 3'b100 ;
else if (err_chk)
results_cnt <= results_cnt + 3'd1 ;
end
integer result_fid;
initial begin
result_fid = $fopen ("sim_results.log","a");
$fmonitor(result_fid,"err_chk=%b", err_chk);
end
endmodule |
module ipsl_pcie_hard_ctrl_v1_3 #(
parameter DEVICE_TYPE = 3'b000 ,
parameter DEBUG_INFO_DW = 133 ,
parameter TP = 2 ,
parameter GRS_EN = "TRUE" ,
parameter PIN_MUX_INT_FORCE_EN = "FALSE" ,
parameter PIN_MUX_INT_DISABLE = "FALSE" ,
parameter DIAG_CTRL_BUS_B2 = "NORMAL" ,
parameter DYN_DEBUG_SEL_EN = "FALSE" ,
parameter integer DEBUG_INFO_SEL = 0 ,
parameter integer BAR_RESIZABLE = 21 ,
parameter integer NUM_OF_RBARS = 3 ,
parameter integer BAR_INDEX_0 = 0 ,
parameter integer BAR_INDEX_1 = 2 ,
parameter integer BAR_INDEX_2 = 4 ,
parameter TPH_DISABLE = "FALSE" ,
parameter MSIX_CAP_DISABLE = "FALSE" ,
parameter MSI_CAP_DISABLE = "FALSE" ,
parameter MSI_PVM_DISABLE = "FALSE" ,
parameter integer BAR_MASK_WRITABLE = 32 ,
parameter integer APP_DEV_NUM = 0 ,
parameter integer APP_BUS_NUM = 0 ,
parameter RAM_MUX_EN = "FALSE" ,
parameter ATOMIC_DISABLE = "FALSE" ,
// cfg space reg
parameter MAX_LINK_WIDTH = 6'b00_0100 ,
parameter MAX_LINK_SPEED = 4'b0010 ,
parameter LINK_CAPABLE = 6'b00_0111 ,
parameter SCRAMBLE_DISABLE = 1'b0 ,
parameter AUTO_LANE_FLIP_CTRL_EN = 1'b1 ,
parameter NUM_OF_LANES = 5'b0_0001 ,
parameter MAX_PAYLOAD_SIZE = 3'b011 ,
parameter INT_DISABLE = 1'b0 ,
parameter PVM_SUPPORT = 1'b1 ,
parameter MSI_64_BIT_ADDR_CAP = 1'b1 ,
parameter MSI_MULTIPLE_MSG_CAP = 3'b101 ,
parameter MSI_ENABLE = 1'b0 ,
parameter MSI_CAP_NEXT_OFFSET = 8'h70 ,
parameter CAP_POINTER = 8'h50 ,
parameter PCIE_CAP_NEXT_PTR = 8'h00 ,
parameter VENDOR_ID = 16'h0755 ,
parameter DEVICE_ID = 16'h0755 ,
parameter BASE_CLASS_CODE = 8'h05 ,
parameter SUBCLASS_CODE = 8'h80 ,
parameter PROGRAM_INTERFACE = 8'h00 ,
parameter REVISION_ID = 8'h00 ,
parameter SUBSYS_DEV_ID = 16'h0000 ,
parameter SUBSYS_VENDOR_ID = 16'h0000 ,
parameter BAR0_PREFETCH = 1'b0 ,
parameter BAR0_TYPE = 2'b0 ,
parameter BAR0_MEM_IO = 1'b0 ,
parameter BAR0_ENABLED = 1'b1 ,
parameter BAR0_MASK = 31'h0000_0fff ,
parameter BAR1_PREFETCH = 1'b0 ,
parameter BAR1_TYPE = 2'b0 ,
parameter BAR1_MEM_IO = 1'b0 ,
parameter BAR1_ENABLED = 1'b1 ,
parameter BAR1_MASK = 31'h0000_07ff ,
parameter BAR2_PREFETCH = 1'b0 ,
parameter BAR2_TYPE = 2'b10 ,
parameter BAR2_MEM_IO = 1'b0 ,
parameter BAR2_ENABLED = 1'b1 ,
parameter BAR2_MASK = 31'h0000_0fff ,
parameter BAR3_PREFETCH = 1'b0 ,
parameter BAR3_TYPE = 2'b0 ,
parameter BAR3_MEM_IO = 1'b0 ,
parameter BAR3_ENABLED = 1'b0 ,
parameter BAR3_MASK = 31'd0 ,
parameter BAR4_PREFETCH = 1'b0 ,
parameter BAR4_TYPE = 2'b0 ,
parameter BAR4_MEM_IO = 1'b0 ,
parameter BAR4_ENABLED = 1'b0 ,
parameter BAR4_MASK = 31'd0 ,
parameter BAR5_PREFETCH = 1'b0 ,
parameter BAR5_TYPE = 2'b0 ,
parameter BAR5_MEM_IO = 1'b0 ,
parameter BAR5_ENABLED = 1'b0 ,
parameter BAR5_MASK = 31'd0 ,
parameter ROM_BAR_ENABLE = 1'b0 ,
parameter ROM_BAR_ENABLED = 1'd0 ,
parameter ROM_MASK = 31'd0 ,
parameter DO_DESKEW_FOR_SRIS = 1'b1 ,
parameter PCIE_CAP_HW_AUTO_SPEED_DISABLE = 1'b0 ,
parameter TARGET_LINK_SPEED = 4'h1 ,
parameter ECRC_CHECK_EN = 1'b1 ,
parameter ECRC_GEN_EN = 1'b1 ,
parameter EXT_TAG_EN = 1'b1 ,
parameter EXT_TAG_SUPP = 1'b1 ,
parameter PCIE_CAP_RCB = 1'b1 ,
parameter PCIE_CAP_CRS = 1'b0 ,
parameter PCIE_CAP_ATOMIC_EN = 1'b0 ,
parameter PCI_MSIX_ENABLE = 1'b0 ,
parameter PCI_FUNCTION_MASK = 1'b0 ,
parameter PCI_MSIX_TABLE_SIZE = 11'h0 ,
parameter PCI_MSIX_CPA_NEXT_OFFSET = 8'h0 ,
parameter PCI_MSIX_TABLE_OFFSET = 29'h0 ,
parameter PCI_MSIX_BIR = 3'h0 ,
parameter PCI_MSIX_PBA_OFFSET = 29'h0 ,
parameter PCI_MSIX_PBA_BIR = 3'h0 ,
parameter AER_CAP_NEXT_OFFSET = 12'h0 ,
parameter TPH_REQ_NEXT_PTR = 12'h0 ,
parameter RESBAR_BAR0_MAX_SUPP_SIZE = 20'hf_ffff ,
parameter RESBAR_BAR0_INIT_SIZE = 5'h13 ,
parameter RESBAR_BAR1_MAX_SUPP_SIZE = 20'hf_ffff ,
parameter RESBAR_BAR1_INIT_SIZE = 5'h13 ,
parameter RESBAR_BAR2_MAX_SUPP_SIZE = 20'hf_ffff ,
parameter RESBAR_BAR2_INIT_SIZE = 5'hb ,
parameter UPCONFIGURE_SUPPORT = 1'b1
)(
//clk & rst
input mem_clk ,
input pclk ,
input pclk_div2 ,
input button_rst ,
input power_up_rst ,
input perst ,
output wire core_rst_n ,
output wire training_rst_n ,
input app_init_rst ,
output wire phy_rst_n ,
//system control
input rx_lane_flip_en ,
input tx_lane_flip_en ,
output wire smlh_link_up ,
output wire rdlh_link_up ,
input app_req_retry_en ,
output wire [4:0] smlh_ltssm_state ,
//AXIS master interface
output wire axis_master_tvalid ,
input axis_master_tready ,
output wire [127:0] axis_master_tdata ,
output wire [3:0] axis_master_tkeep ,
output wire axis_master_tlast ,
output wire [7:0] axis_master_tuser ,
input [2:0] trgt1_radm_pkt_halt ,
output wire [5:0] radm_grant_tlp_type ,
//AXIS slave 0 interface
output wire axis_slave0_tready ,
input axis_slave0_tvalid ,
input [127:0] axis_slave0_tdata ,
input axis_slave0_tlast ,
input axis_slave0_tuser ,
//AXIS slave 1 interface
output wire axis_slave1_tready ,
input axis_slave1_tvalid ,
input [127:0] axis_slave1_tdata ,
input axis_slave1_tlast ,
input axis_slave1_tuser ,
//AXIS slave 2 interface
output wire axis_slave2_tready ,
input axis_slave2_tvalid ,
input [127:0] axis_slave2_tdata ,
input axis_slave2_tlast ,
input axis_slave2_tuser ,
output wire pm_xtlh_block_tlp ,
//apb interface
input apb_sel ,
input [ 3:0] apb_strb ,
input [15:0] apb_addr ,
input [31:0] apb_wdata ,
input apb_ce ,
input apb_we ,
output wire apb_rdy ,
output wire [31:0] apb_rdata ,
input tx_rst_done ,
//Legacy Interrupt
output wire cfg_int_disable ,
input sys_int ,
output wire inta_grt_mux ,
output wire intb_grt_mux ,
output wire intc_grt_mux ,
output wire intd_grt_mux ,
//MSI Interface
input ven_msi_req ,
input [2:0] ven_msi_tc ,
input [4:0] ven_msi_vector ,
output wire ven_msi_grant ,
input [(32*1)-1:0] cfg_msi_pending ,
output wire cfg_msi_en ,
// MSI-X Interface
input [63:0] msix_addr ,
input [31:0] msix_data ,
output wire cfg_msix_en ,
output wire cfg_msix_func_mask ,
//Power Management
output wire radm_pm_turnoff ,
output wire radm_msg_unlock ,
input outband_pwrup_cmd ,
output wire pm_status ,
output wire [2:0] pm_dstate ,
output wire aux_pm_en ,
output wire pm_pme_en ,
output wire pm_linkst_in_l0s ,
output wire pm_linkst_in_l1 ,
output wire pm_linkst_in_l2 ,
output wire pm_linkst_l2_exit ,
input app_req_entr_l1 ,
input app_ready_entr_l23 ,
input app_req_exit_l1 ,
input app_xfer_pending ,
output wire wake ,
output wire radm_pm_pme ,
output wire radm_pm_to_ack ,
input apps_pm_xmt_turnoff ,
input app_unlock_msg ,
input apps_pm_xmt_pme ,
input app_clk_pm_en ,
output wire [4:0] pm_master_state ,
output wire [4:0] pm_slave_state ,
input sys_aux_pwr_det ,
//Error Handling
input app_hdr_valid ,
input [127:0] app_hdr_log ,
input [12:0] app_err_bus ,
input app_err_advisory ,
output wire cfg_send_cor_err_mux ,
output wire cfg_send_nf_err_mux ,
output wire cfg_send_f_err_mux ,
output wire cfg_sys_err_rc ,
output wire cfg_aer_rc_err_mux ,
//radm timeout
output wire radm_cpl_timeout ,
output wire [2:0] radm_timeout_cpl_tc ,
output wire [7:0] radm_timeout_cpl_tag ,
output wire [1:0] radm_timeout_cpl_attr ,
output wire [10:0] radm_timeout_cpl_len ,
//Configuration Information Signals
output wire [2:0] cfg_max_rd_req_size ,
output wire cfg_bus_master_en ,
output wire [2:0] cfg_max_payload_size ,
output wire cfg_ext_tag_en ,
output wire cfg_rcb ,
output wire cfg_mem_space_en ,
output wire cfg_pm_no_soft_rst ,
output wire cfg_crs_sw_vis_en ,
output wire cfg_no_snoop_en ,
output wire cfg_relax_order_en ,
output wire [2-1:0] cfg_tph_req_en ,
output wire [3-1:0] cfg_pf_tph_st_mode ,
output wire [7:0] cfg_pbus_num ,
output wire [4:0] cfg_pbus_dev_num ,
output wire rbar_ctrl_update ,
output wire cfg_atomic_req_en ,
output wire cfg_atomic_egress_block ,
//Debug Signals
output wire radm_idle ,
output wire radm_q_not_empty ,
output wire radm_qoverflow ,
input [1:0] diag_ctrl_bus ,
input [3:0] dyn_debug_info_sel ,
output wire cfg_link_auto_bw_mux ,
output wire cfg_bw_mgt_mux ,
output wire cfg_pme_mux ,
output wire [DEBUG_INFO_DW-1:0] debug_info_mux ,
input app_ras_des_sd_hold_ltssm ,
input [1:0] app_ras_des_tba_ctrl ,
//MISC
output wire cfg_ido_req_en ,
output wire cfg_ido_cpl_en ,
output wire [7:0] xadm_ph_cdts ,
output wire [11:0] xadm_pd_cdts ,
output wire [7:0] xadm_nph_cdts ,
output wire [11:0] xadm_npd_cdts ,
output wire [7:0] xadm_cplh_cdts ,
output wire [11:0] xadm_cpld_cdts ,
// PIPE interface
input phy_rate_chng_halt ,
output wire [1 : 0] mac_phy_powerdown ,
input [3:0] phy_mac_rxelecidle ,
input [3:0] phy_mac_phystatus ,
input [127:0] phy_mac_rxdata ,
input [15:0] phy_mac_rxdatak ,
input [3:0] phy_mac_rxvalid ,
input [(4*3)-1:0] phy_mac_rxstatus ,
output wire [127:0] mac_phy_txdata ,
output wire [15:0] mac_phy_txdatak ,
output wire [3:0] mac_phy_txdetectrx_loopback ,
output wire [3:0] mac_phy_txelecidle_l ,
output wire [3:0] mac_phy_txelecidle_h ,
output wire [3:0] mac_phy_txcompliance ,
output wire [3:0] mac_phy_rxpolarity ,
output wire mac_phy_rate ,
output wire [1:0] mac_phy_txdeemph ,
output wire [2:0] mac_phy_txmargin ,
output wire mac_phy_txswing ,
output wire cfg_hw_auto_sp_dis
);
//external ram interface : rcv data ram , retry buff data ram.
wire [10-1:0] p_dataq_addra ;
wire [66-1:0] p_dataq_datain ;
wire [1-1:0] p_dataq_ena ;
wire [1-1:0] p_dataq_wea ;
wire [66-1:0] p_dataq_dataout ;
wire [10-1:0] p_dataq_addrb ;
wire [1-1:0] p_dataq_enb ;
wire [11 -1:0] xdlh_retryram_addr ;
wire [68-1:0] xdlh_retryram_data ;
wire xdlh_retryram_we ;
wire xdlh_retryram_en ;
wire [68-1:0] retryram_xdlh_data ;
wire [8:0] p_hdrq_addra ;
wire [137:0] p_hdrq_datain ;
wire [1-1:0] p_hdrq_ena ;
wire [1-1:0] p_hdrq_wea ;
wire [8:0] p_hdrq_addrb ;
wire [1-1:0] p_hdrq_enb ;
wire [137:0] p_hdrq_dataout ;
reg [137:0] p_hdrq_data_in_r ;
wire [137:0] p_hdrq_data_in_ram ;
wire [ 65:0] p_dataq_data_in_ram ;
wire [ 8:0] p_hdrq_addra_in_ram ;
wire [ 9:0] p_dataq_addra_in_ram ;
wire [71:0] retryram_xdlh_data_i ;
wire [71:0] p_dataq_dataout_i ;
wire [143:0] p_hdrq_dataout_i ;
reg core_rst_n_mem ;
reg core_rst_n_mem_r1 ;
wire mem_rst_n ;
wire s_mem_rst_n ;
//seio
wire sedo ;
wire sedo_en ;
wire sedi ;
wire sedi_ack ;
// APB2DBI
reg [31:0] dbi_addr ;
reg [31:0] dbi_din ;
reg dbi_cs ;
reg dbi_cs2 ;
reg [3:0] dbi_wr ;
reg app_dbi_ro_wr_disable ;
wire app_ltssm_enable ;
wire dbi_halt ;
wire lbc_dbi_ack ;
wire [31:0] lbc_dbi_dout ;
wire init_finish ;
wire [31:0] init_dbi_addr ;
wire [31:0] init_dbi_din ;
wire init_dbi_cs ;
wire init_dbi_cs2 ;
wire [3:0] init_dbi_wr ;
wire init_app_dbi_ro_wr_disable ;
wire [31:0] if_dbi_addr ;
wire [31:0] if_dbi_din ;
wire if_dbi_cs ;
wire if_dbi_cs2 ;
wire [3:0] if_dbi_wr ;
wire if_app_dbi_ro_wr_disable ;
wire s_tx_rst_done ;
// External RAMs begin
always @ (posedge mem_clk or negedge core_rst_n)
begin
if(~core_rst_n)
begin
core_rst_n_mem_r1 <= 1'b0;
core_rst_n_mem <= 1'b0;
end
else
begin
core_rst_n_mem_r1 <= 1'b1;
core_rst_n_mem <= core_rst_n_mem_r1;
end
end
`ifndef RAM_OUTPUT_MUX_DISABLE
always @ (posedge mem_clk or negedge core_rst_n_mem )
if(~core_rst_n_mem)
p_hdrq_data_in_r <= 138'h0;
else
p_hdrq_data_in_r <= p_hdrq_datain;
assign p_hdrq_data_in_ram = {p_hdrq_datain[68:0],p_hdrq_data_in_r[68:0]};
assign p_hdrq_addra_in_ram = p_dataq_addra[8:0];
assign p_dataq_data_in_ram = p_hdrq_datain[65:0];
assign p_dataq_addra_in_ram = p_dataq_addra;
`else
assign p_hdrq_data_in_ram = p_hdrq_datain;
assign p_hdrq_addra_in_ram = p_hdrq_addra;
assign p_dataq_data_in_ram = p_dataq_datain;
assign p_dataq_addra_in_ram = p_dataq_addra;
`endif
assign #TP retryram_xdlh_data = retryram_xdlh_data_i[67:0];
assign #TP p_dataq_dataout = p_dataq_dataout_i[65 :0];
assign #TP p_hdrq_dataout = p_hdrq_dataout_i[137:0];
assign mem_rst_n = ~button_rst && ~perst;
ipsl_pcie_sync_v1_0 mem_button_rstn_sync (.clk(mem_clk), .rst_n(mem_rst_n), .sig_async(1'b1), .sig_synced(s_mem_rst_n));
ipsl_pcie_ext_rcvd_ram u_pcie_iip_exrcvdata_rams(
.wr_addr (p_dataq_addra_in_ram ),
.rd_addr (p_dataq_addrb ),
.wr_data ({6'b0,p_dataq_data_in_ram} ),
.wr_en (p_dataq_ena ),
.rd_data (p_dataq_dataout_i ),
.wr_clk (mem_clk ),
.rd_clk (mem_clk ),
.rd_rst (~s_mem_rst_n ),
.wr_rst (~s_mem_rst_n )
);
ipsl_pcie_ext_rcvh_ram u_pcie_iip_exrcvhdr_rams(
.wr_addr (p_hdrq_addra_in_ram ),
.rd_addr (p_hdrq_addrb ),
.wr_data ({6'b0,p_hdrq_data_in_ram} ),
.wr_en (p_hdrq_ena ),
.rd_data (p_hdrq_dataout_i ),
.wr_clk (mem_clk ),
.rd_clk (mem_clk ),
.rd_rst (~s_mem_rst_n ),
.wr_rst (~s_mem_rst_n )
);
ipsl_pcie_retryd_ram u_pcie_iip_exretry_rams(
.addr (xdlh_retryram_addr ),
.wr_data ({4'b0,xdlh_retryram_data} ),
.wr_en (xdlh_retryram_we ),
.rd_data (retryram_xdlh_data_i ),
.clk (mem_clk ),
.rst (~s_mem_rst_n )
);
// External RAMs end
// SEIO begin
ipsl_pcie_seio_intf_v1_0 u_pcie_seio(
.pclk_div2 (pclk_div2 ),
.user_rst_n (core_rst_n ),
.sedo_in (sedo ),
.sedo_en_in (sedo_en ),
.sedi (sedi ),
.sedi_ack (sedi_ack )
);
// SEIO end
// Configuration Initial begin
ipsl_pcie_sync_v1_0 tx_rst_done_sync (.clk(pclk_div2), .rst_n(core_rst_n), .sig_async(tx_rst_done), .sig_synced(s_tx_rst_done));
ipsl_pcie_cfg_init_v1_3 #(
.DEVICE_TYPE (DEVICE_TYPE ),
.MAX_LINK_WIDTH (MAX_LINK_WIDTH ),
.MAX_LINK_SPEED (MAX_LINK_SPEED ),
.LINK_CAPABLE (LINK_CAPABLE ),
.SCRAMBLE_DISABLE (SCRAMBLE_DISABLE ),
.AUTO_LANE_FLIP_CTRL_EN (AUTO_LANE_FLIP_CTRL_EN ),
.NUM_OF_LANES (NUM_OF_LANES ),
.MAX_PAYLOAD_SIZE (MAX_PAYLOAD_SIZE ),
.INT_DISABLE (INT_DISABLE ),
.PVM_SUPPORT (PVM_SUPPORT ),
.MSI_64_BIT_ADDR_CAP (MSI_64_BIT_ADDR_CAP ),
.MSI_MULTIPLE_MSG_CAP (MSI_MULTIPLE_MSG_CAP ),
.MSI_ENABLE (MSI_ENABLE ),
.MSI_CAP_NEXT_OFFSET (MSI_CAP_NEXT_OFFSET ),
.CAP_POINTER (CAP_POINTER ),
.PCIE_CAP_NEXT_PTR (PCIE_CAP_NEXT_PTR ),
.VENDOR_ID (VENDOR_ID ),
.DEVICE_ID (DEVICE_ID ),
.BASE_CLASS_CODE (BASE_CLASS_CODE ),
.SUBCLASS_CODE (SUBCLASS_CODE ),
.PROGRAM_INTERFACE (PROGRAM_INTERFACE ),
.REVISION_ID (REVISION_ID ),
.SUBSYS_DEV_ID (SUBSYS_DEV_ID ),
.SUBSYS_VENDOR_ID (SUBSYS_VENDOR_ID ),
.BAR0_PREFETCH (BAR0_PREFETCH ),
.BAR0_TYPE (BAR0_TYPE ),
.BAR0_MEM_IO (BAR0_MEM_IO ),
.BAR0_ENABLED (BAR0_ENABLED ),
.BAR0_MASK (BAR0_MASK ),
.BAR1_PREFETCH (BAR1_PREFETCH ),
.BAR1_TYPE (BAR1_TYPE ),
.BAR1_MEM_IO (BAR1_MEM_IO ),
.BAR1_ENABLED (BAR1_ENABLED ),
.BAR1_MASK (BAR1_MASK ),
.BAR2_PREFETCH (BAR2_PREFETCH ),
.BAR2_TYPE (BAR2_TYPE ),
.BAR2_MEM_IO (BAR2_MEM_IO ),
.BAR2_ENABLED (BAR2_ENABLED ),
.BAR2_MASK (BAR2_MASK ),
.BAR3_PREFETCH (BAR3_PREFETCH ),
.BAR3_TYPE (BAR3_TYPE ),
.BAR3_MEM_IO (BAR3_MEM_IO ),
.BAR3_ENABLED (BAR3_ENABLED ),
.BAR3_MASK (BAR3_MASK ),
.BAR4_PREFETCH (BAR4_PREFETCH ),
.BAR4_TYPE (BAR4_TYPE ),
.BAR4_MEM_IO (BAR4_MEM_IO ),
.BAR4_ENABLED (BAR4_ENABLED ),
.BAR4_MASK (BAR4_MASK ),
.BAR5_PREFETCH (BAR5_PREFETCH ),
.BAR5_TYPE (BAR5_TYPE ),
.BAR5_MEM_IO (BAR5_MEM_IO ),
.BAR5_ENABLED (BAR5_ENABLED ),
.BAR5_MASK (BAR5_MASK ),
.ROM_BAR_ENABLE (ROM_BAR_ENABLE ),
.ROM_BAR_ENABLED (ROM_BAR_ENABLED ),
.ROM_MASK (ROM_MASK ),
.DO_DESKEW_FOR_SRIS (DO_DESKEW_FOR_SRIS ),
.PCIE_CAP_HW_AUTO_SPEED_DISABLE (PCIE_CAP_HW_AUTO_SPEED_DISABLE ),
.TARGET_LINK_SPEED (TARGET_LINK_SPEED ),
.ECRC_CHECK_EN (ECRC_CHECK_EN ),
.ECRC_GEN_EN (ECRC_GEN_EN ),
.EXT_TAG_EN (EXT_TAG_EN ),
.EXT_TAG_SUPP (EXT_TAG_SUPP ),
.PCIE_CAP_RCB (PCIE_CAP_RCB ),
.PCIE_CAP_CRS (PCIE_CAP_CRS ),
.PCIE_CAP_ATOMIC_EN (PCIE_CAP_ATOMIC_EN ),
.PCI_MSIX_ENABLE (PCI_MSIX_ENABLE ),
.PCI_FUNCTION_MASK (PCI_FUNCTION_MASK ),
.PCI_MSIX_TABLE_SIZE (PCI_MSIX_TABLE_SIZE ),
.PCI_MSIX_CPA_NEXT_OFFSET (PCI_MSIX_CPA_NEXT_OFFSET ),
.PCI_MSIX_TABLE_OFFSET (PCI_MSIX_TABLE_OFFSET ),
.PCI_MSIX_BIR (PCI_MSIX_BIR ),
.PCI_MSIX_PBA_OFFSET (PCI_MSIX_PBA_OFFSET ),
.PCI_MSIX_PBA_BIR (PCI_MSIX_PBA_BIR ),
.AER_CAP_NEXT_OFFSET (AER_CAP_NEXT_OFFSET ),
.TPH_REQ_NEXT_PTR (TPH_REQ_NEXT_PTR ),
.RESBAR_BAR0_MAX_SUPP_SIZE (RESBAR_BAR0_MAX_SUPP_SIZE ),
.RESBAR_BAR0_INIT_SIZE (RESBAR_BAR0_INIT_SIZE ),
.RESBAR_BAR1_MAX_SUPP_SIZE (RESBAR_BAR1_MAX_SUPP_SIZE ),
.RESBAR_BAR1_INIT_SIZE (RESBAR_BAR1_INIT_SIZE ),
.RESBAR_BAR2_MAX_SUPP_SIZE (RESBAR_BAR2_MAX_SUPP_SIZE ),
.RESBAR_BAR2_INIT_SIZE (RESBAR_BAR2_INIT_SIZE ),
.UPCONFIGURE_SUPPORT (UPCONFIGURE_SUPPORT )
) u_pcie_cfg_init(
.clk (pclk_div2 ), //input
.rst_n (core_rst_n ), //input
.start (s_tx_rst_done ), //input
.dbi_ack (lbc_dbi_ack ), //input
.dbi_cs (init_dbi_cs ), //output reg
.dbi_cs2 (init_dbi_cs2 ), //output reg
.dbi_addr (init_dbi_addr ), //output reg [31:0]
.dbi_din (init_dbi_din ), //output reg [31:0]
.dbi_wr (init_dbi_wr ), //output reg [3:0]
.dbi_ro_wr_disable (init_app_dbi_ro_wr_disable ), //output reg
.init_finish (init_finish ) //output reg
);
assign app_ltssm_enable = init_finish;
// Configuration Initial end
// APB2DBI begin
assign dbi_halt = phy_rate_chng_halt;
ipsl_pcie_apb2dbi_v1_0 u_pcie_apb2dbi(
.pclk_div2 (pclk_div2 ),
.apb_rst_n (core_rst_n ),
.p_sel (apb_sel ),
.p_strb (apb_strb ),
.p_addr (apb_addr ),
.p_wdata (apb_wdata ),
.p_ce (apb_ce ),
.p_we (apb_we ),
.p_rdy (apb_rdy ),
.p_rdata (apb_rdata ),
.dbi_addr (if_dbi_addr ),
.dbi_din (if_dbi_din ),
.dbi_cs (if_dbi_cs ),
.dbi_cs2 (if_dbi_cs2 ),
.dbi_wr (if_dbi_wr ),
.app_dbi_ro_wr_disable (if_app_dbi_ro_wr_disable ),
.lbc_dbi_ack (lbc_dbi_ack ),
.lbc_dbi_dout (lbc_dbi_dout ),
.dbi_halt (dbi_halt )
);
always @(*) begin
if (!init_finish) begin
dbi_addr = init_dbi_addr ;
dbi_din = init_dbi_din ;
dbi_cs = init_dbi_cs ;
dbi_cs2 = init_dbi_cs2 ;
dbi_wr = init_dbi_wr ;
app_dbi_ro_wr_disable = init_app_dbi_ro_wr_disable ;
end else begin
dbi_addr = if_dbi_addr ;
dbi_din = if_dbi_din ;
dbi_cs = if_dbi_cs ;
dbi_cs2 = if_dbi_cs2 ;
dbi_wr = if_dbi_wr ;
app_dbi_ro_wr_disable = if_app_dbi_ro_wr_disable ;
end
end
// APB2DBI end
// GTP_PCIEGEN2 instance begin
GTP_PCIEGEN2#(
.GRS_EN (GRS_EN ),
.PIN_MUX_INT_FORCE_EN (PIN_MUX_INT_FORCE_EN ),
.PIN_MUX_INT_DISABLE (PIN_MUX_INT_DISABLE ),
.DIAG_CTRL_BUS_B2 (DIAG_CTRL_BUS_B2 ),
.DYN_DEBUG_SEL_EN (DYN_DEBUG_SEL_EN ),
.DEBUG_INFO_SEL (DEBUG_INFO_SEL ),
.BAR_RESIZABLE (BAR_RESIZABLE ),
.NUM_OF_RBARS (NUM_OF_RBARS ),
.BAR_INDEX_0 (BAR_INDEX_0 ),
.BAR_INDEX_1 (BAR_INDEX_1 ),
.BAR_INDEX_2 (BAR_INDEX_2 ),
.TPH_DISABLE (TPH_DISABLE ),
.MSIX_CAP_DISABLE (MSIX_CAP_DISABLE ),
.MSI_CAP_DISABLE (MSI_CAP_DISABLE ),
.MSI_PVM_DISABLE (MSI_PVM_DISABLE ),
.BAR_MASK_WRITABLE (BAR_MASK_WRITABLE ),
.APP_DEV_NUM (APP_DEV_NUM ),
.APP_BUS_NUM (APP_BUS_NUM ),
.RAM_MUX_EN (RAM_MUX_EN ),
.ATOMIC_DISABLE (ATOMIC_DISABLE )
)u_pcie(
.MEM_CLK (mem_clk ),
.PCLK (pclk ),
.PCLK_DIV2 (pclk_div2 ),
.BUTTON_RST (button_rst ),
.POWER_UP_RST (power_up_rst ),
.PERST (perst ),
.CORE_RST_N (core_rst_n ),
.TRAINING_RST_N (training_rst_n ),
.APP_INIT_RST (app_init_rst ),
.PHY_RST_N (phy_rst_n ),
.DEVICE_TYPE (DEVICE_TYPE ),
.RX_LANE_FLIP_EN (rx_lane_flip_en ),
.TX_LANE_FLIP_EN (tx_lane_flip_en ),
.APP_LTSSM_EN (app_ltssm_enable ),
.SMLH_LINK_UP (smlh_link_up ),
.RDLH_LINK_UP (rdlh_link_up ),
.APP_REQ_RETRY_EN (app_req_retry_en ),
.SMLH_LTSSM_STATE (smlh_ltssm_state ),
//*********************************************************************
//AXIS master interface
.AXIS_MASTER_TVALID (axis_master_tvalid ),
.AXIS_MASTER_TREADY (axis_master_tready ),
.AXIS_MASTER_TDATA (axis_master_tdata ),
.AXIS_MASTER_TKEEP (axis_master_tkeep ),
.AXIS_MASTER_TLAST (axis_master_tlast ),
.AXIS_MASTER_TUSER (axis_master_tuser ),
.TRGT1_RADM_PKT_HALT (trgt1_radm_pkt_halt ),
.RADM_GRANT_TLP_TYPE (radm_grant_tlp_type ),
//*********************************************************************
//axis slave 0 interface
.AXIS_SLAVE0_TREADY (axis_slave0_tready ),
.AXIS_SLAVE0_TVALID (axis_slave0_tvalid ),
.AXIS_SLAVE0_TDATA (axis_slave0_tdata ),
.AXIS_SLAVE0_TLAST (axis_slave0_tlast ),
.AXIS_SLAVE0_TUSER (axis_slave0_tuser ),
//axis slave 1 interface
.AXIS_SLAVE1_TREADY (axis_slave1_tready ),
.AXIS_SLAVE1_TVALID (axis_slave1_tvalid ),
.AXIS_SLAVE1_TDATA (axis_slave1_tdata ),
.AXIS_SLAVE1_TLAST (axis_slave1_tlast ),
.AXIS_SLAVE1_TUSER (axis_slave1_tuser ),
//axis slave 2 interface
.AXIS_SLAVE2_TREADY (axis_slave2_tready ),
.AXIS_SLAVE2_TVALID (axis_slave2_tvalid ),
.AXIS_SLAVE2_TDATA (axis_slave2_tdata ),
.AXIS_SLAVE2_TLAST (axis_slave2_tlast ),
.AXIS_SLAVE2_TUSER (axis_slave2_tuser ),
.PM_XTLH_BLOCK_TLP (pm_xtlh_block_tlp ),
//*********************************************************************
// DBI interface
.DBI_ADDR (dbi_addr ),
.DBI_DIN (dbi_din ),
.DBI_CS (dbi_cs ),
.DBI_CS2 (dbi_cs2 ),
.DBI_WR (dbi_wr ),
.APP_DBI_RO_WR_DISABLE (app_dbi_ro_wr_disable ),
.LBC_DBI_ACK (lbc_dbi_ack ),
.LBC_DBI_DOUT (lbc_dbi_dout ),
// ELBI to SEIO interface
.SEDO (sedo ),
.SEDO_EN (sedo_en ),
.SEDI (sedi ),
.SEDI_ACK (sedi_ack ),
//**********************************************************************
//legacy interrupt
.CFG_INT_DISABLE (cfg_int_disable ),
.SYS_INT (sys_int ),
.INTA_GRT_MUX (inta_grt_mux ),
.INTB_GRT_MUX (intb_grt_mux ),
.INTC_GRT_MUX (intc_grt_mux ),
.INTD_GRT_MUX (intd_grt_mux ),
//msi
.VEN_MSI_REQ (ven_msi_req ),
.VEN_MSI_TC (ven_msi_tc ),
.VEN_MSI_VECTOR (ven_msi_vector ),
.VEN_MSI_GRANT (ven_msi_grant ),
.CFG_MSI_PENDING (cfg_msi_pending ),
.CFG_MSI_EN (cfg_msi_en ),
// MSI-X interface
.MSIX_ADDR (msix_addr ),
.MSIX_DATA (msix_data ),
.CFG_MSIX_EN (cfg_msix_en ),
.CFG_MSIX_FUNC_MASK (cfg_msix_func_mask ),
//**********************************************************************
//power management
.RADM_PM_TURNOFF (radm_pm_turnoff ),
.RADM_MSG_UNLOCK (radm_msg_unlock ),
.OUTBAND_PWRUP_CMD (outband_pwrup_cmd ),
.PM_STATUS (pm_status ),
.PM_DSTATE (pm_dstate ),
.AUX_PM_EN (aux_pm_en ),
.PM_PME_EN (pm_pme_en ),
.PM_LINKST_IN_L0S (pm_linkst_in_l0s ),
.PM_LINKST_IN_L1 (pm_linkst_in_l1 ),
.PM_LINKST_IN_L2 (pm_linkst_in_l2 ),
.PM_LINKST_L2_EXIT (pm_linkst_l2_exit ),
.APP_REQ_ENTR_L1 (app_req_entr_l1 ),
.APP_READY_ENTR_L23 (app_ready_entr_l23 ),
.APP_REQ_EXIT_L1 (app_req_exit_l1 ),
.APP_XFER_PENDING (app_xfer_pending ),
.WAKE (wake ),
.RADM_PM_PME (radm_pm_pme ),
.RADM_PM_TO_ACK (radm_pm_to_ack ),
.APPS_PM_XMT_TURNOFF (apps_pm_xmt_turnoff ),
.APP_UNLOCK_MSG (app_unlock_msg ),
.APPS_PM_XMT_PME (apps_pm_xmt_pme ),
.APP_CLK_PM_EN (app_clk_pm_en ),
.PM_MASTER_STATE (pm_master_state ),
.PM_SLAVE_STATE (pm_slave_state ),
.SYS_AUX_PWR_DET (sys_aux_pwr_det ),
//**********************************************************************
//error handling
.APP_HDR_VALID (app_hdr_valid ),
.APP_HDR_LOG (app_hdr_log ),
.APP_ERR_BUS (app_err_bus ),
.APP_ERR_ADVISORY (app_err_advisory ),
.CFG_SEND_COR_ERR_MUX (cfg_send_cor_err_mux ),
.CFG_SEND_NF_ERR_MUX (cfg_send_nf_err_mux ),
.CFG_SEND_F_ERR_MUX (cfg_send_f_err_mux ),
.CFG_SYS_ERR_RC (cfg_sys_err_rc ),
.CFG_AER_RC_ERR_MUX (cfg_aer_rc_err_mux ),
//radm timeout
.RADM_CPL_TIMEOUT (radm_cpl_timeout ),
.RADM_TIMEOUT_CPL_TC (radm_timeout_cpl_tc ),
.RADM_TIMEOUT_CPL_TAG (radm_timeout_cpl_tag ),
.RADM_TIMEOUT_CPL_ATTR (radm_timeout_cpl_attr ),
.RADM_TIMEOUT_CPL_LEN (radm_timeout_cpl_len ),
//**********************************************************************
//configuration signals
.CFG_MAX_RD_REQ_SIZE (cfg_max_rd_req_size ),
.CFG_BUS_MASTER_EN (cfg_bus_master_en ),
.CFG_MAX_PAYLOAD_SIZE (cfg_max_payload_size ),
.CFG_RCB (cfg_rcb ),
.CFG_MEM_SPACE_EN (cfg_mem_space_en ),
.CFG_PM_NO_SOFT_RST (cfg_pm_no_soft_rst ),
.CFG_CRS_SW_VIS_EN (cfg_crs_sw_vis_en ),
.CFG_NO_SNOOP_EN (cfg_no_snoop_en ),
.CFG_RELAX_ORDER_EN (cfg_relax_order_en ),
.CFG_TPH_REQ_EN (cfg_tph_req_en ),
.CFG_PF_TPH_ST_MODE (cfg_pf_tph_st_mode ),
.CFG_PBUS_NUM (cfg_pbus_num ),
.CFG_PBUS_DEV_NUM (cfg_pbus_dev_num ),
.RBAR_CTRL_UPDATE (rbar_ctrl_update ),
.CFG_ATOMIC_REQ_EN (cfg_atomic_req_en ),
.CFG_ATOMIC_EGRESS_BLOCK (cfg_atomic_egress_block ),
.CFG_EXT_TAG_EN (cfg_ext_tag_en ),
//**********************************************************************
//debug signals
.RADM_IDLE (radm_idle ),
.RADM_Q_NOT_EMPTY (radm_q_not_empty ),
.RADM_QOVERFLOW (radm_qoverflow ),
.DIAG_CTRL_BUS (diag_ctrl_bus ),
.DYN_DEBUG_INFO_SEL (dyn_debug_info_sel ),
.CFG_LINK_AUTO_BW_MUX (cfg_link_auto_bw_mux ),
.CFG_BW_MGT_MUX (cfg_bw_mgt_mux ),
.CFG_PME_MUX (cfg_pme_mux ),
.DEBUG_INFO_MUX (debug_info_mux ),
.APP_RAS_DES_SD_HOLD_LTSSM (app_ras_des_sd_hold_ltssm ),
.APP_RAS_DES_TBA_CTRL (app_ras_des_tba_ctrl ),
//misc
.CFG_IDO_REQ_EN (cfg_ido_req_en ),
.CFG_IDO_CPL_EN (cfg_ido_cpl_en ),
.XADM_PH_CDTS (xadm_ph_cdts ),
.XADM_PD_CDTS (xadm_pd_cdts ),
.XADM_NPH_CDTS (xadm_nph_cdts ),
.XADM_NPD_CDTS (xadm_npd_cdts ),
.XADM_CPLH_CDTS (xadm_cplh_cdts ),
.XADM_CPLD_CDTS (xadm_cpld_cdts ),
//**********************************************************************
// PIPE interface
.MAC_PHY_POWERDOWN (mac_phy_powerdown ),
.PHY_MAC_RXELECIDLE (phy_mac_rxelecidle ),
.PHY_MAC_PHYSTATUS (phy_mac_phystatus ),
.PHY_MAC_RXDATA (phy_mac_rxdata ),
.PHY_MAC_RXDATAK (phy_mac_rxdatak ),
.PHY_MAC_RXVALID (phy_mac_rxvalid ),
.PHY_MAC_RXSTATUS (phy_mac_rxstatus ),
.MAC_PHY_TXDATA (mac_phy_txdata ),
.MAC_PHY_TXDATAK (mac_phy_txdatak ),
.MAC_PHY_TXDETECTRX_LOOPBACK(mac_phy_txdetectrx_loopback),
.MAC_PHY_TXELECIDLE_L (mac_phy_txelecidle_l ),
.MAC_PHY_TXELECIDLE_H (mac_phy_txelecidle_h ),
.MAC_PHY_TXCOMPLIANCE (mac_phy_txcompliance ),
.MAC_PHY_RXPOLARITY (mac_phy_rxpolarity ),
.MAC_PHY_RATE (mac_phy_rate ),
.MAC_PHY_TXDEEMPH (mac_phy_txdeemph ),
.MAC_PHY_TXMARGIN (mac_phy_txmargin ),
.MAC_PHY_TXSWING (mac_phy_txswing ),
.CFG_HW_AUTO_SP_DIS (cfg_hw_auto_sp_dis ),
.P_DATAQ_DATAOUT (p_dataq_dataout ),
.P_DATAQ_ADDRA (p_dataq_addra ),
.P_DATAQ_ADDRB (p_dataq_addrb ),
.P_DATAQ_DATAIN (p_dataq_datain ),
.P_DATAQ_ENA (p_dataq_ena ),
.P_DATAQ_ENB (p_dataq_enb ),
.P_DATAQ_WEA (p_dataq_wea ),
.XDLH_RETRYRAM_ADDR (xdlh_retryram_addr ),
.XDLH_RETRYRAM_DATA (xdlh_retryram_data ),
.XDLH_RETRYRAM_WE (xdlh_retryram_we ),
.XDLH_RETRYRAM_EN (xdlh_retryram_en ),
.RETRYRAM_XDLH_DATA (retryram_xdlh_data ),
.P_HDRQ_ADDRA (p_hdrq_addra ),
.P_HDRQ_ADDRB (p_hdrq_addrb ),
.P_HDRQ_DATAIN (p_hdrq_datain ),
.P_HDRQ_ENA (p_hdrq_ena ),
.P_HDRQ_ENB (p_hdrq_enb ),
.P_HDRQ_WEA (p_hdrq_wea ),
.P_HDRQ_DATAOUT (p_hdrq_dataout ),
.RAM_TEST_EN (1'b0 ),
.RAM_TEST_ADDRH (1'b0 ),
.RETRY_TEST_DATA_EN (1'b0 ),
.RAM_TEST_MODE_N (1'b1 )
);
// GTP_PCIEGEN2 instance end
endmodule |
module ipsl_pcie_apb_cross_v1_0 (
//from src domain
input i_src_clk ,
input i_src_rst_n ,
input i_src_p_sel ,
input [3:0] i_src_p_strb ,
input [15:0] i_src_p_addr ,
input [31:0] i_src_p_wdata ,
input i_src_p_ce ,
input i_src_p_we ,
output reg o_src_p_rdy ,
output reg [31:0] o_src_p_rdata ,
//to target domain
input i_des_clk ,
input i_des_rst_n ,
output reg o_des_p_sel ,
output reg [3:0] o_des_p_strb ,
output reg [15:0] o_des_p_addr ,
output reg [31:0] o_des_p_wdata ,
output reg o_des_p_ce ,
output reg o_des_p_we ,
input i_des_p_rdy ,
input [31:0] i_des_p_rdata
);
reg src_p_sel;
reg [3:0] src_p_strb;
reg [15:0] src_p_addr;
reg [31:0] src_p_wdata;
reg src_p_ce;
reg src_p_we;
reg [2:0] src_dly;
reg [1:0] des_dly;
reg [1:0] sync_src_p_sel;
reg [1:0] sync_src_dly;
wire des_apb_start;
wire des_apb_end;
reg des_p_rdy_hold;
reg [31:0] des_p_rdata_hold;
//---------------------------------------------src domain-----------------------------------------------
always@(posedge i_src_clk or negedge i_src_rst_n)
begin
if(!i_src_rst_n)
src_p_sel <= 1'b0;
else
src_p_sel <= i_src_p_sel;
end
always@(posedge i_src_clk or negedge i_src_rst_n)
begin
if(!i_src_rst_n)
src_p_strb <= 4'b0;
else
src_p_strb <= i_src_p_strb;
end
always@(posedge i_src_clk or negedge i_src_rst_n)
begin
if(!i_src_rst_n)
src_p_addr <= 16'b0;
else
src_p_addr <= i_src_p_addr;
end
always@(posedge i_src_clk or negedge i_src_rst_n)
begin
if(!i_src_rst_n)
src_p_wdata <= 32'b0;
else
src_p_wdata <= i_src_p_wdata;
end
always@(posedge i_src_clk or negedge i_src_rst_n)
begin
if(!i_src_rst_n)
src_p_ce <= 1'b0;
else
src_p_ce <= i_src_p_ce;
end
always@(posedge i_src_clk or negedge i_src_rst_n)
begin
if(!i_src_rst_n)
src_p_we <= 1'b0;
else
src_p_we <= i_src_p_we;
end
always@(posedge i_src_clk or negedge i_src_rst_n)
begin
if(!i_src_rst_n)
src_dly <= 3'b0;
else
src_dly <= {src_dly[1:0],des_p_rdy_hold};
end
always@(posedge i_src_clk or negedge i_src_rst_n)
begin
if(!i_src_rst_n)
o_src_p_rdy <= 1'b0;
else if(o_src_p_rdy)
o_src_p_rdy <= 1'b0;
else if(src_p_sel & src_p_ce & ~o_src_p_rdy)
o_src_p_rdy <= ~src_dly[2] & src_dly[1];
end
always@(posedge i_src_clk or negedge i_src_rst_n)
begin
if(!i_src_rst_n)
o_src_p_rdata <= 32'b0;
else if(o_src_p_rdy)
o_src_p_rdata <= 32'b0;
else if(src_p_sel & src_p_ce & ~src_dly[2] & src_dly[1] & ~src_p_we)
o_src_p_rdata <= des_p_rdata_hold;
end
//---------------------------------------------des domain-----------------------------------------------
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
sync_src_p_sel <= 2'b0;
else
sync_src_p_sel <= {sync_src_p_sel[0],src_p_sel};
end
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
sync_src_dly <= 2'b0;
else
sync_src_dly <= {sync_src_dly[0],src_dly[2]};
end
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
des_dly <= 2'b0;
else if(sync_src_dly[1])
des_dly <= {des_dly[0],1'b0};
else
des_dly <= {des_dly[0],sync_src_p_sel[1]};
end
assign des_apb_start = ~des_dly[1] & des_dly[0];
assign des_apb_end = des_dly[1] & ~des_dly[0];
//get apb information
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
o_des_p_addr <= 16'b0;
else if(des_apb_start)
o_des_p_addr <= src_p_addr;
end
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
o_des_p_strb <= 4'b0;
else if(des_apb_start)
o_des_p_strb <= src_p_strb;
end
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
o_des_p_wdata <= 32'b0;
else if(des_apb_start)
o_des_p_wdata <= src_p_wdata;
end
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
o_des_p_we <= 1'b0;
else if(des_apb_start)
o_des_p_we <= src_p_we;
end
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
o_des_p_sel <= 1'b0;
else if(i_des_p_rdy)
o_des_p_sel <= 1'b0;
else if(des_apb_start)
o_des_p_sel <= 1'b1;
end
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
o_des_p_ce <= 1'b0;
else if(i_des_p_rdy)
o_des_p_ce <= 1'b0;
else if(o_des_p_sel)
o_des_p_ce <= 1'b1;
end
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
des_p_rdy_hold <= 1'b0;
else if(des_apb_end)
des_p_rdy_hold <= 1'b0;
else if(o_des_p_sel & o_des_p_ce & i_des_p_rdy )
des_p_rdy_hold <= 1'b1;
end
always@(posedge i_des_clk or negedge i_des_rst_n)
begin
if(!i_des_rst_n)
des_p_rdata_hold <= 32'b0;
else if(des_apb_end)
des_p_rdata_hold <= 32'b0;
else if(o_des_p_sel & o_des_p_ce & i_des_p_rdy & ~o_des_p_we)
des_p_rdata_hold <= i_des_p_rdata;
end
endmodule |
module ipsl_pcie_sync_v1_0 (
input clk,
input rst_n,
input sig_async,
output reg sig_synced
);
reg sig_async_ff;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
sig_async_ff <= 1'b0;
else
sig_async_ff <= sig_async;
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
sig_synced <= 1'b0;
else
sig_synced <= sig_async_ff;
end
endmodule |
module ipsl_pcie_apb_mux_v1_1 (
//from uart domain
input i_uart_clk ,
input i_uart_rst_n ,
input i_uart_p_sel ,
input [3:0] i_uart_p_strb ,
input [15:0] i_uart_p_addr ,
input [31:0] i_uart_p_wdata ,
input i_uart_p_ce ,
input i_uart_p_we ,
output wire o_uart_p_rdy ,
output wire [31:0] o_uart_p_rdata ,
//to pcie domain
input i_pcie_clk ,
input i_pcie_rst_n ,
output wire o_pcie_p_sel ,
output wire [3:0] o_pcie_p_strb ,
output wire [15:0] o_pcie_p_addr ,
output wire [31:0] o_pcie_p_wdata ,
output wire o_pcie_p_ce ,
output wire o_pcie_p_we ,
input i_pcie_p_rdy ,
input [31:0] i_pcie_p_rdata ,
//to hsstlp domain
input i_hsst_clk ,
input i_hsst_rst_n ,
output wire o_hsst_p_sel ,
output wire [3:0] o_hsst_p_strb ,
output wire [15:0] o_hsst_p_addr ,
output wire [31:0] o_hsst_p_wdata ,
output wire o_hsst_p_ce ,
output wire o_hsst_p_we ,
input i_hsst_p_rdy ,
input [31:0] i_hsst_p_rdata
);
wire pcie_p_sel ;
wire [3:0] pcie_p_strb ;
wire [15:0] pcie_p_addr ;
wire [31:0] pcie_p_wdata;
wire pcie_p_ce ;
wire pcie_p_we ;
wire pcie_p_rdy ;
wire [31:0] pcie_p_rdata;
//apb mux
assign o_hsst_p_sel = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >7)) ? i_uart_p_sel : 1'b0 ;
assign pcie_p_sel = (i_uart_p_addr[15:12] == 4'h7) ? i_uart_p_sel : 1'b0 ;
assign o_uart_p_rdy = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >7)) ? i_hsst_p_rdy :
(i_uart_p_addr[15:12] == 4'h7) ? pcie_p_rdy : 1'b0 ;
assign o_uart_p_rdata = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >7)) ? i_hsst_p_rdata :
(i_uart_p_addr[15:12] == 4'h7) ? pcie_p_rdata : 32'b0;
//apb2hsst
assign o_hsst_p_strb = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >7)) ? i_uart_p_strb : 4'b0 ;
assign o_hsst_p_addr = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >7)) ? i_uart_p_addr : 16'b0 ;
assign o_hsst_p_wdata = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >7)) ? i_uart_p_wdata : 32'b0 ;
assign o_hsst_p_ce = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >7)) ? i_uart_p_ce : 1'b0 ;
assign o_hsst_p_we = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >7)) ? i_uart_p_we : 1'b0 ;
//apb2pcie
assign pcie_p_strb = (i_uart_p_addr[15:12] == 4'h7) ? i_uart_p_strb : 4'b0 ;
assign pcie_p_addr = (i_uart_p_addr[15:12] == 4'h7) ? i_uart_p_addr : 16'b0 ;
assign pcie_p_wdata = (i_uart_p_addr[15:12] == 4'h7) ? i_uart_p_wdata : 32'b0 ;
assign pcie_p_ce = (i_uart_p_addr[15:12] == 4'h7) ? i_uart_p_ce : 1'b0 ;
assign pcie_p_we = (i_uart_p_addr[15:12] == 4'h7) ? i_uart_p_we : 1'b0 ;
ipsl_pcie_apb_cross_v1_0 u_pcie_apb_cross(
//from src domain
.i_src_clk (i_uart_clk ),
.i_src_rst_n (i_uart_rst_n ),
.i_src_p_sel (pcie_p_sel ),
.i_src_p_strb (pcie_p_strb ),
.i_src_p_addr (pcie_p_addr ),
.i_src_p_wdata (pcie_p_wdata ),
.i_src_p_ce (pcie_p_ce ),
.i_src_p_we (pcie_p_we ),
.o_src_p_rdy (pcie_p_rdy ),
.o_src_p_rdata (pcie_p_rdata ),
//to target domain
.i_des_clk (i_pcie_clk ),
.i_des_rst_n (i_pcie_rst_n ),
.o_des_p_sel (o_pcie_p_sel ),
.o_des_p_strb (o_pcie_p_strb ),
.o_des_p_addr (o_pcie_p_addr ),
.o_des_p_wdata (o_pcie_p_wdata),
.o_des_p_ce (o_pcie_p_ce ),
.o_des_p_we (o_pcie_p_we ),
.i_des_p_rdy (i_pcie_p_rdy ),
.i_des_p_rdata (i_pcie_p_rdata)
);
endmodule |
module ipsl_pcie_cfg_init_v1_3 #(
parameter DEVICE_TYPE = 3'b000 , // EP-> 3'b000; RC->3'b100;
parameter MAX_LINK_WIDTH = 6'b00_0100 , // x4
parameter MAX_LINK_SPEED = 4'b0010 , // gen2
parameter LINK_CAPABLE = 6'b00_0111 , // 4-lanes
parameter SCRAMBLE_DISABLE = 1'b0 ,
parameter AUTO_LANE_FLIP_CTRL_EN = 1'b1 ,
parameter NUM_OF_LANES = 5'b0_0001 ,
parameter MAX_PAYLOAD_SIZE = 3'b011 , // 1024-bytes
parameter INT_DISABLE = 1'b0 ,
parameter PVM_SUPPORT = 1'b1 ,
parameter MSI_64_BIT_ADDR_CAP = 1'b1 ,
parameter MSI_MULTIPLE_MSG_CAP = 3'b101 ,
parameter MSI_ENABLE = 1'b0 ,
parameter MSI_CAP_NEXT_OFFSET = 8'h70 ,
parameter CAP_POINTER = 8'h50 ,
parameter PCIE_CAP_NEXT_PTR = 8'hB0 ,
parameter VENDOR_ID = 16'h0755 ,
parameter DEVICE_ID = 16'h0755 ,
parameter BASE_CLASS_CODE = 8'h05 ,
parameter SUBCLASS_CODE = 8'h80 ,
parameter PROGRAM_INTERFACE = 8'h00 ,
parameter REVISION_ID = 8'h00 ,
parameter SUBSYS_DEV_ID = 16'h0000 ,
parameter SUBSYS_VENDOR_ID = 16'h0000 ,
parameter BAR0_PREFETCH = 1'b0 ,
parameter BAR0_TYPE = 2'b0 ,
parameter BAR0_MEM_IO = 1'b0 ,
parameter BAR0_ENABLED = 1'b1 ,
parameter BAR0_MASK = 31'h0000_0fff ,
parameter BAR1_PREFETCH = 1'b0 ,
parameter BAR1_TYPE = 2'b0 ,
parameter BAR1_MEM_IO = 1'b0 ,
parameter BAR1_ENABLED = 1'b1 ,
parameter BAR1_MASK = 31'h0000_07ff ,
parameter BAR2_PREFETCH = 1'b0 ,
parameter BAR2_TYPE = 2'b10 ,
parameter BAR2_MEM_IO = 1'b0 ,
parameter BAR2_ENABLED = 1'b1 ,
parameter BAR2_MASK = 31'h0000_0fff ,
parameter BAR3_PREFETCH = 1'b0 ,
parameter BAR3_TYPE = 2'b0 ,
parameter BAR3_MEM_IO = 1'b0 ,
parameter BAR3_ENABLED = 1'b0 ,
parameter BAR3_MASK = 31'd0 ,
parameter BAR4_PREFETCH = 1'b0 ,
parameter BAR4_TYPE = 2'b0 ,
parameter BAR4_MEM_IO = 1'b0 ,
parameter BAR4_ENABLED = 1'b0 ,
parameter BAR4_MASK = 31'd0 ,
parameter BAR5_PREFETCH = 1'b0 ,
parameter BAR5_TYPE = 2'b0 ,
parameter BAR5_MEM_IO = 1'b0 ,
parameter BAR5_ENABLED = 1'b0 ,
parameter BAR5_MASK = 31'd0 ,
parameter ROM_BAR_ENABLE = 1'b0 ,
parameter ROM_BAR_ENABLED = 1'd0 ,
parameter ROM_MASK = 31'd0 ,
parameter DO_DESKEW_FOR_SRIS = 1'b1 ,
parameter PCIE_CAP_HW_AUTO_SPEED_DISABLE = 1'b0 ,
parameter TARGET_LINK_SPEED = 4'h1 ,
parameter ECRC_CHECK_EN = 1'b1 ,
parameter ECRC_GEN_EN = 1'b1 ,
parameter EXT_TAG_EN = 1'b1 ,
parameter EXT_TAG_SUPP = 1'b1 ,
parameter PCIE_CAP_RCB = 1'b1 ,
parameter PCIE_CAP_CRS = 1'b0 ,
parameter PCIE_CAP_ATOMIC_EN = 1'b0 ,
//msix
parameter PCI_MSIX_ENABLE = 1'b0 ,
parameter PCI_FUNCTION_MASK = 1'b0 ,
parameter PCI_MSIX_TABLE_SIZE = 11'h0 ,
parameter PCI_MSIX_CPA_NEXT_OFFSET = 8'h0 ,
parameter PCI_MSIX_TABLE_OFFSET = 29'h0 ,
parameter PCI_MSIX_BIR = 3'h0 ,
parameter PCI_MSIX_PBA_OFFSET = 29'h0 ,
parameter PCI_MSIX_PBA_BIR = 3'h0 ,
parameter AER_CAP_NEXT_OFFSET = 12'h0 ,
//TPH
parameter TPH_REQ_NEXT_PTR = 12'h0 ,
//Resizable BAR
parameter RESBAR_BAR0_MAX_SUPP_SIZE = 20'hf_ffff ,
parameter RESBAR_BAR0_INIT_SIZE = 5'h13 ,
parameter RESBAR_BAR1_MAX_SUPP_SIZE = 20'hf_ffff ,
parameter RESBAR_BAR1_INIT_SIZE = 5'h13 ,
parameter RESBAR_BAR2_MAX_SUPP_SIZE = 20'hf_ffff ,
parameter RESBAR_BAR2_INIT_SIZE = 5'hb ,
//MULTI_LANE_CONTROL_OFF
parameter UPCONFIGURE_SUPPORT = 1'b1
)(
input clk ,
input rst_n ,
input start ,
input dbi_ack ,
output reg dbi_cs ,
output reg dbi_cs2 ,
output reg [31:0] dbi_addr ,
output reg [31:0] dbi_din ,
output reg [3:0] dbi_wr ,
output reg dbi_ro_wr_disable ,
output reg init_finish
);
// ROM Define
localparam ROM_CNT = 10'd46;
wire [47:0] init_rom [ROM_CNT-1:0] /* synthesis syn_romstyle = "select_rom" */;
wire dbi_standby;
reg [9:0] rom_raddr;
//================================================
// init parameter
//================================================
//------------------------------------------------
// rom width = 48-bits
// |--> [47:44] = 4-bits = dbi_wr
// |--> [43:32] = 12-bits = dbi_addr
// |--> [31:0] = 32-bits = dbi_data
//------------------------------------------------
//
//----------------------
// B=0x70, offset=B+0xc, = 0x7c
//----------------------
// max_link_width @[9:4]
// max_link_speed @[3:0]
localparam [47:0] INI_0 = {4'b0011, 12'h07c, 16'd0, 4'hf, 2'b10, MAX_LINK_WIDTH, MAX_LINK_SPEED};
//----------------------
// offset=0x710
//----------------------
// link_capable @[21:16]
// scramble_disable @[1]
localparam [47:0] INI_1 = {4'b0101, 12'h710, 10'h00, LINK_CAPABLE, 8'h0, 6'b0010_00, SCRAMBLE_DISABLE, 1'b0};
//----------------------
// offset=0x80c
//----------------------
// auto_lane_flip_ctrl_en @[16]
// num_of_lanes @[12:8]
localparam [47:0] INI_2 = {4'b0110, 12'h80c, 15'h01, AUTO_LANE_FLIP_CTRL_EN, 3'h0, NUM_OF_LANES, 8'h00};
//----------------------
// B=0x70, offset=B+0x24, = 0x94
//----------------------
// cpl_timeout_disable_support @[4]
// cpl_timeout_range @[3:0]
localparam [47:0] INI_3 = 48'd0;//{4'b0001, 12'h094, 24'd0, 3'b100, CPL_TIMEOUT_DISABLE_SUPPORT, CPL_TIMEOUT_RANGE};
//----------------------
// B=0x70, offset=B+0x4, = 0x74
//----------------------
// EXT_TAG_SUPP @[5]
// max_payload_size[2:0]
localparam [47:0] INI_4 = {4'b0001, 12'h074, 26'b0, EXT_TAG_SUPP, 2'b0, MAX_PAYLOAD_SIZE};
//----------------------
// B=0x00, offset=B+0x4, = 0x4
//----------------------
// INT_DISABLE[10]
localparam [47:0] INI_5 = {4'b0010, 12'h004, 16'd0, 5'd0, INT_DISABLE, 10'd0};
//----------------------
// B=0x50, offset=B+0x0, = 0x50
//----------------------
// pvm_support @[24]
// msi_64_bit_addr_cap @[23]
// msi_multiple_msg_cap @[19:17]
// msi_enable @[16]
// msi_cap_next_offset @[15:8]
localparam [47:0] INI_6 = {4'b1110, 12'h050, 7'd0, PVM_SUPPORT, MSI_64_BIT_ADDR_CAP, 3'd0, MSI_MULTIPLE_MSG_CAP, MSI_ENABLE, MSI_CAP_NEXT_OFFSET, 8'd0};
//----------------------
// B=0x00, offset=B+0x34, = 0x34
//----------------------
// cap_pointer @[7:0]
localparam [47:0] INI_7 = {4'b0001, 12'h034, 24'd0, CAP_POINTER};
//----------------------
// B=0x70, offset=B+0x0, = 0x70
//----------------------
// pcie_cap_next_ptr @[15:8]
localparam [47:0] INI_8 = {4'b0010, 12'h070, 16'd0, PCIE_CAP_NEXT_PTR, 8'd0};
//----------------------
// B=0x00, offset=B+0x0, = 0x00
//----------------------
// vendor_id [15:0]
// device_id [31:16]
localparam [47:0] INI_9 = {4'b1111, 12'h000, DEVICE_ID, VENDOR_ID};
//----------------------
// B=0x00, offset=B+0x8, = 0x8
//----------------------
// base_class_code @[31:24]
// subclass_code @[23:16]
// program_interface@[15:8]
// revision_id @[7:0]
localparam [47:0] INI_10 = {4'b1111, 12'h008, BASE_CLASS_CODE, SUBCLASS_CODE, PROGRAM_INTERFACE, REVISION_ID};
//----------------------
// B=0x00, offset=B+0x2c, = 0x2c
//----------------------
// subsys_dev_id @[31:16]
// subsys_vendor_id @[15:0]
localparam [47:0] INI_11 = (DEVICE_TYPE==3'b100) ? 48'd0 : {4'b1111, 12'h02c, SUBSYS_DEV_ID, SUBSYS_VENDOR_ID};
//----------------------
// B=0x00, offset=B+0x11, = 0x11
//----------------------
// bar0_enabled @[0]
// bar0_mask @[31:1]
localparam [47:0] INI_12 = {4'b1111, 12'h011, BAR0_MASK, BAR0_ENABLED};
//----------------------
// B=0x00, offset=B+0x10, = 0x10
//----------------------
// bar0_prefetch @[3]
// bar0_type @[2:1]
// bar0_mem_io @[0]
localparam [47:0] INI_13 = {4'b0001, 12'h010, 28'd0, BAR0_PREFETCH, BAR0_TYPE, BAR0_MEM_IO};
//----------------------
// B=0x00, offset=B+0x11, = 0x11
//----------------------
// bar1_enabled @[0]
// bar1_mask @[31:1]
localparam [47:0] INI_14 = {4'b1111, 12'h015, BAR1_MASK, BAR1_ENABLED};
//----------------------
// B=0x00, offset=B+0x10, = 0x10
//----------------------
// bar1_prefetch @[3]
// bar1_type @[2:1]
// bar1_mem_io @[0]
localparam [47:0] INI_15 = {4'b0001, 12'h014, 28'd0, BAR1_PREFETCH, BAR1_TYPE, BAR1_MEM_IO};
//----------------------
// B=0x00, offset=B+0x11, = 0x11
//----------------------
// BAR2_enabled @[0]
// BAR2_mask @[31:1]
localparam [47:0] INI_16 = (DEVICE_TYPE==3'b100) ? 48'd0 : {4'b1111, 12'h019, BAR2_MASK, BAR2_ENABLED};
//----------------------
// B=0x00, offset=B+0x10, = 0x10
//----------------------
// BAR2_prefetch @[3]
// BAR2_type @[2:1]
// BAR2_mem_io @[0]
localparam [47:0] INI_17 = (DEVICE_TYPE==3'b100) ? 48'd0 : {4'b0001, 12'h018, 28'd0, BAR2_PREFETCH, BAR2_TYPE, BAR2_MEM_IO};
//----------------------
// B=0x00, offset=B+0x11, = 0x11
//----------------------
// BAR3_enabled @[0]
// BAR3_mask @[31:1]
localparam [47:0] INI_18 = (DEVICE_TYPE==3'b100) ? 48'd0 : {4'b1111, 12'h01d, BAR3_MASK, BAR3_ENABLED};
//----------------------
// B=0x00, offset=B+0x10, = 0x10
//----------------------
// BAR3_prefetch @[3]
// BAR3_type @[2:1]
// BAR3_mem_io @[0]
localparam [47:0] INI_19 = (DEVICE_TYPE==3'b100) ? 48'd0 : {4'b0001, 12'h01c, 28'd0, BAR3_PREFETCH, BAR3_TYPE, BAR3_MEM_IO};
//----------------------
// B=0x00, offset=B+0x11, = 0x11
//----------------------
// BAR4_enabled @[0]
// BAR4_mask @[31:1]
localparam [47:0] INI_20 = (DEVICE_TYPE==3'b100) ? 48'd0 : {4'b1111, 12'h021, BAR4_MASK, BAR4_ENABLED};
//----------------------
// B=0x00, offset=B+0x10, = 0x10
//----------------------
// BAR4_prefetch @[3]
// BAR4_type @[2:1]
// BAR4_mem_io @[0]
localparam [47:0] INI_21 = (DEVICE_TYPE==3'b100) ? 48'd0 : {4'b0001, 12'h020, 28'd0, BAR4_PREFETCH, BAR4_TYPE, BAR4_MEM_IO};
//----------------------
// B=0x00, offset=B+0x11, = 0x11
//----------------------
// BAR5_enabled @[0]
// BAR5_mask @[31:1]
localparam [47:0] INI_22 = (DEVICE_TYPE==3'b100) ? 48'd0 : {4'b1111, 12'h025, BAR5_MASK, BAR5_ENABLED};
//----------------------
// B=0x00, offset=B+0x10, = 0x10
//----------------------
// BAR5_prefetch @[3]
// BAR5_type @[2:1]
// BAR5_mem_io @[0]
localparam [47:0] INI_23 = (DEVICE_TYPE==3'b100) ? 48'd0 : {4'b0001, 12'h024, 28'd0, BAR5_PREFETCH, BAR5_TYPE, BAR5_MEM_IO};
//----------------------
// B=0x00,
// ep-> offset=B+0x30, = 0x30
// rc-> offset=B+0x38, = 0x38
//----------------------
// rom_bar_enable @[0]
localparam [47:0] INI_24 = (DEVICE_TYPE==3'b100) ? {4'b0001, 12'h038, 31'd0, ROM_BAR_ENABLE} : {4'b0001, 12'h030, 31'd0, ROM_BAR_ENABLE};
//----------------------
// B=0x00,
// ep-> offset=B+0x31, = 0x31
// rc-> offset=B+0x39, = 0x39
//----------------------
// rom_bar_enabled @[0]
// rom_mask @[31:1]
localparam [47:0] INI_25 = (DEVICE_TYPE==3'b100) ? {4'b1111, 12'h039, ROM_MASK, ROM_BAR_ENABLED} : {4'b1111, 12'h031, ROM_MASK, ROM_BAR_ENABLED};
//----------------------
// offset 0x708
//----------------------
// DO_DESKEW_FOR_SRIS @[23]
localparam [47:0] INI_26 = {4'b0100, 12'h708, 8'd0, DO_DESKEW_FOR_SRIS, 23'd0};
//----------------------
// offset 0xa0
//----------------------
//PCIE_CAP_HW_AUTO_SPEED_DISABLE @[5]
// TARGET_LINK_SPEED @[3:0]
localparam [47:0] INI_27 = {4'b0001, 12'h0a0, 26'd0, PCIE_CAP_HW_AUTO_SPEED_DISABLE, 1'b0, TARGET_LINK_SPEED};
//----------------------
// offset 0xB+0x18
//----------------------
// ECRC_CHECK_EN @[8]
// ECRC_GEN_EN @[6]
localparam [47:0] INI_28 = {4'b0011, 12'h118, 16'd0, 7'd0, ECRC_CHECK_EN, 1'd1, ECRC_GEN_EN, 1'd1, 5'd0};
//----------------------
// offset 0xB(70)+0x8
//----------------------
// EXT_TAG_EN @[8]
localparam [47:0] INI_29 = {4'b0010, 12'h078, 8'h0, 4'h1, 4'h0, 4'h2, 3'h0, EXT_TAG_EN, 4'h1, 4'h0};
//----------------------
// offset 0xB(70)+0x10
//----------------------
localparam [47:0] INI_30 = (DEVICE_TYPE==3'b100) ? {4'b0001, 12'h080, 28'h0, PCIE_CAP_RCB , 3'h0} : {4'b0001, 12'h080, 28'h0, 1'b1 , 3'h0};
//----------------------
// offset 0xB(70)+0x1c
//----------------------
//rc
localparam [47:0] INI_31 = (DEVICE_TYPE==3'b100) ? {4'b0001, 12'h08c, 28'h0, PCIE_CAP_CRS, 3'h0} : {32'd0};
//----------------------
// offset 0xB(70)+0x28
//----------------------
// PCIE_CAP_ATOMIC_EN[6]
localparam [47:0] INI_32 = {4'b0001, 12'h098, 24'h0, 1'b0, PCIE_CAP_ATOMIC_EN, 2'b0 , 4'h0};
//----------------------
// offset 0xB(b0)+0x00
//----------------------
//PCI_MSIX_ENABLE [31]
//PCI_FUNCTION_MASK [30]
//PCI_MSIX_TABLE_SIZE [26:16]
//PCI_MSIX_CPA_NEXT_OFFSET [15:8]
localparam [47:0] INI_33 = {4'b1110, 12'h0b0, PCI_MSIX_ENABLE, PCI_FUNCTION_MASK, 3'h0, PCI_MSIX_TABLE_SIZE, PCI_MSIX_CPA_NEXT_OFFSET, 8'h0};
//----------------------
// offset 0xB(b0)+0x04
//----------------------
//PCI_MSIX_TABLE_OFFSET [31:3]
//PCI_MSIX_BIR [2:0]
localparam [47:0] INI_34 = {4'b1111, 12'h0b4, PCI_MSIX_TABLE_OFFSET, PCI_MSIX_BIR};
//----------------------
// offset 0xB(b0)+0x08
//----------------------
// PCI_MSIX_PBA_OFFSET [31:3]
// PCI_MSIX_PBA_BIR [2:0]
localparam [47:0] INI_35 = {4'b1111, 12'h0b8, PCI_MSIX_PBA_OFFSET, PCI_MSIX_PBA_BIR};
//----------------------
// offset 0x(100)+0x00
//----------------------
// AER_CAP_NEXT_OFFSET [31:20]
localparam [47:0] INI_36 = {4'b1100, 12'h100, AER_CAP_NEXT_OFFSET, 4'h2, 16'h0};
//----------------------
// offset 0x(158)+0x00
//----------------------
// TPH_REQ_NEXT_PTR [31:20]
localparam [47:0] INI_37 = {4'b1100, 12'h158, TPH_REQ_NEXT_PTR, 4'h1, 16'h0};
//----------------------
// offset 0x8c0
//----------------------
// UPCONFIGURE_SUPPORT [7]
localparam [47:0] INI_38 = {4'b0001, 12'h8c0, 24'h0, UPCONFIGURE_SUPPORT, 7'h0};
//----------------------
// offset 0x(2E4)+0x04
//----------------------
// RESBAR_BAR0_MAX_SUPP_SIZE [23:4]
localparam [47:0] INI_39 = {4'b0111, 12'h2E8, 8'h0,RESBAR_BAR0_MAX_SUPP_SIZE, 4'h0};
//----------------------
// offset 0x(2E4)+0x08
//----------------------
// RESBAR_BAR0_INIT_SIZE [12:8]
localparam [47:0] INI_40 = {4'b0010, 12'h2EC, 19'h0,RESBAR_BAR0_INIT_SIZE, 8'h0};
//----------------------
// offset 0x(2E4)+0x0C
//----------------------
// RESBAR_BAR1_MAX_SUPP_SIZE [23:4]
localparam [47:0] INI_41 = {4'b0111, 12'h2F0, 8'h0,RESBAR_BAR1_MAX_SUPP_SIZE, 4'h0};
//----------------------
// offset 0x(2E4)+0x10
//----------------------
// RESBAR_BAR1_INIT_SIZE [12:8]
localparam [47:0] INI_42 = {4'b0010, 12'h2F4, 19'h0,RESBAR_BAR1_INIT_SIZE, 8'h0};
//----------------------
// offset 0x(2E4)+0x14
//----------------------
// RESBAR_BAR2_MAX_SUPP_SIZE [23:4]
localparam [47:0] INI_43 = {4'b0111, 12'h2F8, 8'h0,RESBAR_BAR2_MAX_SUPP_SIZE, 4'h0};
//----------------------
// offset 0x(2E4)+0x18
//----------------------
// RESBAR_BAR2_INIT_SIZE [12:8]
localparam [47:0] INI_44 = {4'b0010, 12'h2FC, 19'h0,RESBAR_BAR2_INIT_SIZE, 8'h0};
// ROM Initial
assign init_rom[0] = INI_0;
assign init_rom[1] = INI_1;
assign init_rom[2] = INI_2;
assign init_rom[3] = INI_3;
assign init_rom[4] = INI_4;
assign init_rom[5] = INI_5;
assign init_rom[6] = INI_6;
assign init_rom[7] = INI_7;
assign init_rom[8] = INI_8;
assign init_rom[9] = INI_9;
assign init_rom[10] = INI_10;
assign init_rom[11] = INI_11;
assign init_rom[12] = INI_12;
assign init_rom[13] = INI_13;
assign init_rom[14] = INI_14;
assign init_rom[15] = INI_15;
assign init_rom[16] = INI_16;
assign init_rom[17] = INI_17;
assign init_rom[18] = INI_18;
assign init_rom[19] = INI_19;
assign init_rom[20] = INI_20;
assign init_rom[21] = INI_21;
assign init_rom[22] = INI_22;
assign init_rom[23] = INI_23;
assign init_rom[24] = INI_24;
assign init_rom[25] = INI_25;
assign init_rom[26] = INI_26;
assign init_rom[27] = INI_27;
assign init_rom[28] = INI_28;
assign init_rom[29] = INI_29;
assign init_rom[30] = INI_30;
assign init_rom[31] = INI_31;
assign init_rom[32] = INI_32;
assign init_rom[33] = INI_33;
assign init_rom[34] = INI_34;
assign init_rom[35] = INI_35;
assign init_rom[36] = INI_36;
assign init_rom[37] = INI_37;
assign init_rom[38] = INI_38;
assign init_rom[39] = INI_39;
assign init_rom[40] = INI_40;
assign init_rom[41] = INI_41;
assign init_rom[42] = INI_42;
assign init_rom[43] = INI_43;
assign init_rom[44] = INI_44;
assign init_rom[45] = 48'b0;
assign dbi_standby = !(dbi_cs || dbi_ack);
reg cnt_done;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt_done <= 1'd0;
else if (rom_raddr==(ROM_CNT-1) && dbi_ack && !dbi_cs)
//else if (rom_raddr==(ROM_CNT) && dbi_ack && !dbi_cs)
cnt_done <= 1'd1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
init_finish <= 1'b0;
else
init_finish <= cnt_done;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
dbi_ro_wr_disable <= 1'b1;
else if (cnt_done)
dbi_ro_wr_disable <= 1'b1;
else if (start && dbi_standby && !cnt_done)
dbi_ro_wr_disable <= 1'b0;
end
// Read Rom Adderess
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
rom_raddr <= 10'd0;
else if (rom_raddr == ROM_CNT-10'd1)
rom_raddr <= rom_raddr;
else if (dbi_ack && dbi_cs)
rom_raddr <= rom_raddr + 10'd1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dbi_cs <= 1'b0;
dbi_din <= 32'd0;
dbi_addr <= 32'd0;
dbi_wr <= 4'd0;
dbi_cs2 <= 1'd0;
end
else if (dbi_ack) begin
dbi_cs <= 1'b0;
dbi_cs2 <= 1'd0;
dbi_wr <= 4'd0;
end
else if (start && dbi_standby && !cnt_done) begin
dbi_cs <= 1'b1;
dbi_din <= init_rom[rom_raddr][31:0];
dbi_addr <= {20'd0, init_rom[rom_raddr][43:32]};
dbi_wr <= init_rom[rom_raddr][47:44];
if (init_rom[rom_raddr][32]==1'b1)
dbi_cs2 <= 1'b1;
else
dbi_cs2 <= 1'b0;
end
end
// debug logic
`ifdef IPSL_PCIE_SPEEDUP_SIM
reg [47:44] test_wr ;
reg [43:32] test_addr ;
reg [31:0] test_data ;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
test_wr <= 'd0;
test_addr <= 'd0;
test_data <= 'd0;
end
else begin
test_wr <= init_rom[rom_raddr][47:44];
test_addr <= init_rom[rom_raddr][43:32];
test_data <= init_rom[rom_raddr][31:0];
end
end
`else
`endif
endmodule |
module ipsl_pcie_top_v1_3 #(
parameter DEVICE_TYPE = 3'b000 ,
parameter DIAG_CTRL_BUS_B2 = "NORMAL" ,
parameter integer BAR_RESIZABLE = 6'b0 ,
parameter integer NUM_OF_RBARS = 0 ,
parameter integer BAR_INDEX_0 = 0 ,
parameter integer BAR_INDEX_1 = 2 ,
parameter integer BAR_INDEX_2 = 4 ,
parameter TPH_DISABLE = "FALSE" ,
parameter MSIX_CAP_DISABLE = "TRUE" ,
parameter MSI_CAP_DISABLE = "FALSE" ,
parameter MSI_PVM_DISABLE = "FALSE" ,
parameter integer BAR_MASK_WRITABLE = 6'b111111 ,
parameter integer APP_DEV_NUM = 0 ,
parameter integer APP_BUS_NUM = 0 ,
parameter ATOMIC_DISABLE = "TRUE" ,
parameter HSST_LANE_NUM = 4 ,
// cfg space reg
parameter MAX_LINK_WIDTH = 6'b00_0100 , // x4
parameter MAX_LINK_SPEED = 4'b0010 , // gen2
parameter LINK_CAPABLE = 6'b00_0111 , // 4-lanes
parameter SCRAMBLE_DISABLE = 1'b0 ,
parameter AUTO_LANE_FLIP_CTRL_EN = 1'b1 ,
parameter NUM_OF_LANES = 5'b0_0001 ,
parameter MAX_PAYLOAD_SIZE = 3'b011 , // 1024-bytes
parameter INT_DISABLE = 1'b0 ,
parameter PVM_SUPPORT = 1'b1 ,
parameter MSI_64_BIT_ADDR_CAP = 1'b1 ,
parameter MSI_MULTIPLE_MSG_CAP = 3'b101 ,
parameter MSI_ENABLE = 1'b0 ,
parameter MSI_CAP_NEXT_OFFSET = 8'h70 ,
parameter CAP_POINTER = 8'h50 ,
parameter PCIE_CAP_NEXT_PTR = 8'h00 ,
parameter VENDOR_ID = 16'h0755 ,
parameter DEVICE_ID = 16'h0755 ,
parameter BASE_CLASS_CODE = 8'h05 ,
parameter SUBCLASS_CODE = 8'h80 ,
parameter PROGRAM_INTERFACE = 8'h00 ,
parameter REVISION_ID = 8'h00 ,
parameter SUBSYS_DEV_ID = 16'h0000 ,
parameter SUBSYS_VENDOR_ID = 16'h0000 ,
parameter BAR0_PREFETCH = 1'b0 ,
parameter BAR0_TYPE = 2'b0 ,
parameter BAR0_MEM_IO = 1'b0 ,
parameter BAR0_ENABLED = 1'b1 ,
parameter BAR0_MASK = 31'h0000_0fff ,
parameter BAR1_PREFETCH = 1'b0 ,
parameter BAR1_TYPE = 2'b0 ,
parameter BAR1_MEM_IO = 1'b0 ,
parameter BAR1_ENABLED = 1'b1 ,
parameter BAR1_MASK = 31'h0000_07ff ,
parameter BAR2_PREFETCH = 1'b0 ,
parameter BAR2_TYPE = 2'b10 ,
parameter BAR2_MEM_IO = 1'b0 ,
parameter BAR2_ENABLED = 1'b1 ,
parameter BAR2_MASK = 31'h0000_0fff ,
parameter BAR3_PREFETCH = 1'b0 ,
parameter BAR3_TYPE = 2'b0 ,
parameter BAR3_MEM_IO = 1'b0 ,
parameter BAR3_ENABLED = 1'b0 ,
parameter BAR3_MASK = 31'd0 ,
parameter BAR4_PREFETCH = 1'b0 ,
parameter BAR4_TYPE = 2'b0 ,
parameter BAR4_MEM_IO = 1'b0 ,
parameter BAR4_ENABLED = 1'b0 ,
parameter BAR4_MASK = 31'd0 ,
parameter BAR5_PREFETCH = 1'b0 ,
parameter BAR5_TYPE = 2'b0 ,
parameter BAR5_MEM_IO = 1'b0 ,
parameter BAR5_ENABLED = 1'b0 ,
parameter BAR5_MASK = 31'd0 ,
parameter ROM_BAR_ENABLE = 1'b0 ,
parameter ROM_BAR_ENABLED = 1'd0 ,
parameter ROM_MASK = 31'd0 ,
parameter DO_DESKEW_FOR_SRIS = 1'b1 ,
parameter PCIE_CAP_HW_AUTO_SPEED_DISABLE = 1'b0 ,
parameter TARGET_LINK_SPEED = 4'h1 ,
parameter ECRC_CHECK_EN = 1'b1 ,
parameter ECRC_GEN_EN = 1'b1 ,
parameter EXT_TAG_EN = 1'b1 ,
parameter EXT_TAG_SUPP = 1'b1 ,
parameter PCIE_CAP_RCB = 1'b1 ,
parameter PCIE_CAP_CRS = 1'b0 ,
parameter PCIE_CAP_ATOMIC_EN = 1'b0 ,
parameter PCI_MSIX_ENABLE = 1'b0 ,
parameter PCI_FUNCTION_MASK = 1'b0 ,
parameter PCI_MSIX_TABLE_SIZE = 11'h0 ,
parameter PCI_MSIX_CPA_NEXT_OFFSET = 8'h0 ,
parameter PCI_MSIX_TABLE_OFFSET = 29'h0 ,
parameter PCI_MSIX_BIR = 3'h0 ,
parameter PCI_MSIX_PBA_OFFSET = 29'h0 ,
parameter PCI_MSIX_PBA_BIR = 3'h0 ,
parameter AER_CAP_NEXT_OFFSET = 12'h0 ,
parameter TPH_REQ_NEXT_PTR = 12'h0 ,
parameter RESBAR_BAR0_MAX_SUPP_SIZE = 20'hf_ffff ,
parameter RESBAR_BAR0_INIT_SIZE = 5'h13 ,
parameter RESBAR_BAR1_MAX_SUPP_SIZE = 20'hf_ffff ,
parameter RESBAR_BAR1_INIT_SIZE = 5'h13 ,
parameter RESBAR_BAR2_MAX_SUPP_SIZE = 20'hf_ffff ,
parameter RESBAR_BAR2_INIT_SIZE = 5'hb ,
parameter UPCONFIGURE_SUPPORT = 1'b1
)(
input free_clk ,
output wire pclk ,
output wire pclk_div2 ,
input i_button_rstn ,
input i_power_up_rstn ,
input i_perstn ,
output wire o_core_rst_n ,
//hot rst
output wire o_training_rst_n ,
input i_app_init_rst ,
// input i_apb_clk ,
input i_apb_sel ,
input [ 3:0] i_apb_strb ,
input [15:0] i_apb_addr ,
input [31:0] i_apb_wdata ,
input i_apb_ce ,
input i_apb_we ,
output wire o_apb_rdy ,
output wire [31:0] o_apb_rdata ,
output wire[HSST_LANE_NUM-1:0] o_txn_lane ,
output wire[HSST_LANE_NUM-1:0] o_txp_lane ,
input [HSST_LANE_NUM-1:0] i_rxn_lane ,
input [HSST_LANE_NUM-1:0] i_rxp_lane ,
input i_refckn ,
input i_refckp ,
input [HSST_LANE_NUM-1:0] i_pcs_nearend_loop ,
input [HSST_LANE_NUM-1:0] i_pma_nearend_ploop ,
input [HSST_LANE_NUM-1:0] i_pma_nearend_sloop ,
output wire o_axis_master_tvalid ,
input i_axis_master_tready ,
output wire [127:0] o_axis_master_tdata ,
output wire [3:0] o_axis_master_tkeep ,
output wire o_axis_master_tlast ,
output wire [7:0] o_axis_master_tuser ,
input [2:0] i_trgt1_radm_pkt_halt ,
output wire [5:0] o_radm_grant_tlp_type ,
output wire o_axis_slave0_tready ,
input i_axis_slave0_tvalid ,
input [127:0] i_axis_slave0_tdata ,
input i_axis_slave0_tlast ,
input i_axis_slave0_tuser ,
output wire o_axis_slave1_tready ,
input i_axis_slave1_tvalid ,
input [127:0] i_axis_slave1_tdata ,
input i_axis_slave1_tlast ,
input i_axis_slave1_tuser ,
output wire o_axis_slave2_tready ,
input i_axis_slave2_tvalid ,
input [127:0] i_axis_slave2_tdata ,
input i_axis_slave2_tlast ,
input i_axis_slave2_tuser ,
output wire o_pm_xtlh_block_tlp ,
output wire o_cfg_int_disable ,
input i_sys_int ,
output wire o_inta_grt_mux ,
output wire o_intb_grt_mux ,
output wire o_intc_grt_mux ,
output wire o_intd_grt_mux ,
input i_ven_msi_req ,
input [2:0] i_ven_msi_tc ,
input [4:0] i_ven_msi_vector ,
output wire o_ven_msi_grant ,
input [(32*1)-1:0] i_cfg_msi_pending ,
output wire o_cfg_msi_en ,
input [63:0] i_msix_addr ,
input [31:0] i_msix_data ,
output wire o_cfg_msix_en ,
output wire o_cfg_msix_func_mask ,
output wire o_radm_pm_turnoff ,
output wire o_radm_msg_unlock ,
input i_outband_pwrup_cmd ,
output wire o_pm_status ,
output wire [2:0] o_pm_dstate ,
output wire o_aux_pm_en ,
output wire o_pm_pme_en ,
output wire o_pm_linkst_in_l0s ,
output wire o_pm_linkst_in_l1 ,
output wire o_pm_linkst_in_l2 ,
output wire o_pm_linkst_l2_exit ,
input i_app_req_entr_l1 ,
input i_app_ready_entr_l23 ,
input i_app_req_exit_l1 ,
input i_app_xfer_pending ,
output wire o_wake ,
output wire o_radm_pm_pme ,
output wire o_radm_pm_to_ack ,
input i_apps_pm_xmt_turnoff ,
input i_app_unlock_msg ,
input i_apps_pm_xmt_pme ,
input i_app_clk_pm_en ,
output wire [4:0] o_pm_master_state ,
output wire [4:0] o_pm_slave_state ,
input i_sys_aux_pwr_det ,
input i_app_hdr_valid ,
input [127:0] i_app_hdr_log ,
input [12:0] i_app_err_bus ,
input i_app_err_advisory ,
output wire o_cfg_send_cor_err_mux ,
output wire o_cfg_send_nf_err_mux ,
output wire o_cfg_send_f_err_mux ,
output wire o_cfg_sys_err_rc ,
output wire o_cfg_aer_rc_err_mux ,
output wire o_radm_cpl_timeout ,
output wire [2:0] o_radm_timeout_cpl_tc ,
output wire [7:0] o_radm_timeout_cpl_tag ,
output wire [1:0] o_radm_timeout_cpl_attr ,
output wire [10:0] o_radm_timeout_cpl_len ,
output wire [2:0] o_cfg_max_rd_req_size ,
output wire o_cfg_bus_master_en ,
output wire [2:0] o_cfg_max_payload_size ,
output wire o_cfg_ext_tag_en ,
output wire o_cfg_rcb ,
output wire o_cfg_mem_space_en ,
output wire o_cfg_pm_no_soft_rst ,
output wire o_cfg_crs_sw_vis_en ,
output wire o_cfg_no_snoop_en ,
output wire o_cfg_relax_order_en ,
output wire [2-1:0] o_cfg_tph_req_en ,
output wire [3-1:0] o_cfg_pf_tph_st_mode ,
output wire [7:0] o_cfg_pbus_num ,
output wire [4:0] o_cfg_pbus_dev_num ,
output wire o_rbar_ctrl_update ,
output wire o_cfg_atomic_req_en ,
output wire o_cfg_atomic_egress_block ,
output wire o_radm_idle ,
output wire o_radm_q_not_empty ,
output wire o_radm_qoverflow ,
input [1:0] i_diag_ctrl_bus ,
input [3:0] i_dyn_debug_info_sel ,
output wire o_cfg_link_auto_bw_mux ,
output wire o_cfg_bw_mgt_mux ,
output wire o_cfg_pme_mux ,
output wire [132:0] o_debug_info_mux ,
input i_app_ras_des_sd_hold_ltssm ,
input [1:0] i_app_ras_des_tba_ctrl ,
output wire o_cfg_ido_req_en ,
output wire o_cfg_ido_cpl_en ,
output wire [7:0] o_xadm_ph_cdts ,
output wire [11:0] o_xadm_pd_cdts ,
output wire [7:0] o_xadm_nph_cdts ,
output wire [11:0] o_xadm_npd_cdts ,
output wire [7:0] o_xadm_cplh_cdts ,
output wire [11:0] o_xadm_cpld_cdts ,
input i_rx_lane_flip_en ,
input i_tx_lane_flip_en ,
output wire o_smlh_link_up ,
output wire o_rdlh_link_up ,
input i_app_req_retry_en ,
output wire [4:0] o_smlh_ltssm_state ,
output wire o_refck2core_0
);
wire [HSST_LANE_NUM*32-1:0] phy_mac_rxdata ;
wire [HSST_LANE_NUM*4-1:0] phy_mac_rxdatak ;
wire i_phy_rate_chng_halt ;
wire [1:0] mac_phy_powerdown ;
wire [HSST_LANE_NUM-1:0] phy_mac_rxelecidle ;
wire [3:0] phy_mac_phystatus ;
wire [HSST_LANE_NUM-1:0] phy_mac_rxvalid ;
wire [HSST_LANE_NUM*3-1:0] phy_mac_rxstatus ;
wire [127:0] mac_phy_txdata ;
wire [15:0] mac_phy_txdatak ;
wire [3:0] mac_phy_txdetectrx_loopback ;
wire [3:0] mac_phy_txelecidle_h ;
wire [3:0] mac_phy_txelecidle_l ;
wire [3:0] mac_phy_txcompliance ;
wire [3:0] mac_phy_rxpolarity ;
wire mac_phy_rate ;
wire [1:0] mac_phy_txdeemph ;
wire [2:0] mac_phy_txmargin ;
wire mac_phy_txswing ;
wire phy_rst_n ;
wire ref_clk ;
wire tx_rst_done ;
wire apb_core_rst_n ;
wire hsst_p_sel ;
wire hsst_p_ce ;
wire hsst_p_we ;
wire [15:0] hsst_p_addr ;
wire [31:0] hsst_p_wdata ;
wire [7:0] hsst_p_rdata ;
wire hsst_p_rdy ;
wire pcie_p_sel ;
wire [3:0] pcie_p_strb ;
wire [15:0] pcie_p_addr ;
wire [31:0] pcie_p_wdata ;
wire pcie_p_ce ;
wire pcie_p_we ;
wire pcie_p_rdy ;
wire [31:0] pcie_p_rdata ;
assign ref_clk = o_refck2core_0;
//=============================================================================
// RST SYNC
//=============================================================================
ipsl_pcie_sync_v1_0 u_core_rstn_sync (
//.clk (i_apb_clk ),
.clk (ref_clk ),
.rst_n (o_core_rst_n ),
.sig_async (1'b1 ),
.sig_synced (apb_core_rst_n )
);
//=============================================================================
// APB MUX
//=============================================================================
ipsl_pcie_apb_mux_v1_1 u_pcie_apb_mux (
//from uart domain
//.i_uart_clk (i_apb_clk ),
.i_uart_clk (ref_clk ),
.i_uart_rst_n (apb_core_rst_n ),
.i_uart_p_sel (i_apb_sel ),
.i_uart_p_strb (i_apb_strb ),
.i_uart_p_addr (i_apb_addr ),
.i_uart_p_wdata (i_apb_wdata ),
.i_uart_p_ce (i_apb_ce ),
.i_uart_p_we (i_apb_we ),
.o_uart_p_rdy (o_apb_rdy ),
.o_uart_p_rdata (o_apb_rdata ),
//to pcie domain
.i_pcie_clk (pclk_div2 ),
.i_pcie_rst_n (o_core_rst_n ),
.o_pcie_p_sel (pcie_p_sel ),
.o_pcie_p_strb (pcie_p_strb ),
.o_pcie_p_addr (pcie_p_addr ),
.o_pcie_p_wdata (pcie_p_wdata ),
.o_pcie_p_ce (pcie_p_ce ),
.o_pcie_p_we (pcie_p_we ),
.i_pcie_p_rdy (pcie_p_rdy ),
.i_pcie_p_rdata (pcie_p_rdata ),
//to hsstlp domain
.i_hsst_clk (ref_clk ),
.i_hsst_rst_n (apb_core_rst_n ),
.o_hsst_p_sel (hsst_p_sel ),
.o_hsst_p_strb ( ),
.o_hsst_p_addr (hsst_p_addr ),
.o_hsst_p_wdata (hsst_p_wdata ),
.o_hsst_p_ce (hsst_p_ce ),
.o_hsst_p_we (hsst_p_we ),
.i_hsst_p_rdy (hsst_p_rdy ),
.i_hsst_p_rdata ({24'b0,hsst_p_rdata} )
);
//=============================================================================
// PCIE_HARD_CTRL
//=============================================================================
ipsl_pcie_hard_ctrl_v1_3 #(
.DEVICE_TYPE (DEVICE_TYPE ),
.DEBUG_INFO_DW (133 ),
.TP (2 ),
.GRS_EN ("FALSE" ), // FALSE, TRUE
.PIN_MUX_INT_FORCE_EN ("FALSE" ), // FALSE, TRUE
.PIN_MUX_INT_DISABLE ("FALSE" ), // FALSE, TURE
.DIAG_CTRL_BUS_B2 (DIAG_CTRL_BUS_B2 ), // "NORMAL" "FAST_LINK_MODE"
.DYN_DEBUG_SEL_EN ("TRUE" ), // FALSE, TRUE
.DEBUG_INFO_SEL (0 ), // set debug_info_mux, 0-15
.BAR_RESIZABLE (BAR_RESIZABLE ), // 0: no resizable bar, 1: bar0 resizable, 2: bar1 resizable, 3: bar0-1 resizable, ... 56: bar3-bar5 resizable; Please do not set more than 3 resizable bars at the same time Default value is 21 which is 6'b010101
.NUM_OF_RBARS (NUM_OF_RBARS ), // 0: no resizable bar, 1: one resizable bar, 2: two resizable bars, 3: three resizable bars Default value is 3
.BAR_INDEX_0 (BAR_INDEX_0 ), // set bar index0 in resizable bar control register, 0: bar0 resizable 1: bar1 resizable 2: bar2 resizable ... 5: bar5 resizable Default value is 0
.BAR_INDEX_1 (BAR_INDEX_1 ), // set bar index1 in resizable bar control register, 0: bar0 resizable 1: bar1 resizable 2: bar2 resizable ... 5: bar5 resizable Default value is 2
.BAR_INDEX_2 (BAR_INDEX_2 ), // set bar index2 in resizable bar control register, 0: bar0 resizable 1: bar1 resizable 2: bar2 resizable ... 5: bar5 resizable Default value is 4
.TPH_DISABLE (TPH_DISABLE ), // FALSE, TRUE
.MSIX_CAP_DISABLE (MSIX_CAP_DISABLE ), // FALSE, TRUE
.MSI_CAP_DISABLE (MSI_CAP_DISABLE ), // FALSE, TRUE
.MSI_PVM_DISABLE (MSI_PVM_DISABLE ), // FALSE, TRUE
.BAR_MASK_WRITABLE (BAR_MASK_WRITABLE ), // 0: no writable bar, 1: bar0 writable, 2: bar1 writable, 3: bar3 writable, ... 63: bar0-5 writable
.APP_DEV_NUM (APP_DEV_NUM ), // set device_number
.APP_BUS_NUM (APP_BUS_NUM ), // set bus_number
.RAM_MUX_EN ("TRUE" ), // FALSE, TRUE
.ATOMIC_DISABLE (ATOMIC_DISABLE ), // FALSE, TRUE
// cfg space reg
.MAX_LINK_WIDTH (MAX_LINK_WIDTH ),
.MAX_LINK_SPEED (MAX_LINK_SPEED ),
.LINK_CAPABLE (LINK_CAPABLE ),
.SCRAMBLE_DISABLE (SCRAMBLE_DISABLE ),
.AUTO_LANE_FLIP_CTRL_EN (AUTO_LANE_FLIP_CTRL_EN ),
.NUM_OF_LANES (NUM_OF_LANES ),
.MAX_PAYLOAD_SIZE (MAX_PAYLOAD_SIZE ),
.INT_DISABLE (INT_DISABLE ),
.PVM_SUPPORT (PVM_SUPPORT ),
.MSI_64_BIT_ADDR_CAP (MSI_64_BIT_ADDR_CAP ),
.MSI_MULTIPLE_MSG_CAP (MSI_MULTIPLE_MSG_CAP ),
.MSI_ENABLE (MSI_ENABLE ),
.CAP_POINTER (CAP_POINTER ),
.PCIE_CAP_NEXT_PTR (PCIE_CAP_NEXT_PTR ),
.VENDOR_ID (VENDOR_ID ),
.DEVICE_ID (DEVICE_ID ),
.BASE_CLASS_CODE (BASE_CLASS_CODE ),
.SUBCLASS_CODE (SUBCLASS_CODE ),
.PROGRAM_INTERFACE (PROGRAM_INTERFACE ),
.REVISION_ID (REVISION_ID ),
.SUBSYS_DEV_ID (SUBSYS_DEV_ID ),
.SUBSYS_VENDOR_ID (SUBSYS_VENDOR_ID ),
.BAR0_PREFETCH (BAR0_PREFETCH ),
.BAR0_TYPE (BAR0_TYPE ),
.BAR0_MEM_IO (BAR0_MEM_IO ),
.BAR0_ENABLED (BAR0_ENABLED ),
.BAR0_MASK (BAR0_MASK ),
.BAR1_MEM_IO (BAR1_MEM_IO ),
.BAR1_ENABLED (BAR1_ENABLED ),
.BAR1_MASK (BAR1_MASK ),
.BAR2_PREFETCH (BAR2_PREFETCH ),
.BAR2_TYPE (BAR2_TYPE ),
.BAR2_MEM_IO (BAR2_MEM_IO ),
.BAR2_ENABLED (BAR2_ENABLED ),
.BAR2_MASK (BAR2_MASK ),
.BAR3_MEM_IO (BAR3_MEM_IO ),
.BAR3_ENABLED (BAR3_ENABLED ),
.BAR3_MASK (BAR3_MASK ),
.BAR4_PREFETCH (BAR4_PREFETCH ),
.BAR4_TYPE (BAR4_TYPE ),
.BAR4_MEM_IO (BAR4_MEM_IO ),
.BAR4_ENABLED (BAR4_ENABLED ),
.BAR4_MASK (BAR4_MASK ),
.BAR5_MEM_IO (BAR5_MEM_IO ),
.BAR5_ENABLED (BAR5_ENABLED ),
.BAR5_MASK (BAR5_MASK ),
.ROM_BAR_ENABLE (ROM_BAR_ENABLE ),
.ROM_BAR_ENABLED (ROM_BAR_ENABLED ),
.ROM_MASK (ROM_MASK ),
.DO_DESKEW_FOR_SRIS (DO_DESKEW_FOR_SRIS ),
.PCIE_CAP_HW_AUTO_SPEED_DISABLE (PCIE_CAP_HW_AUTO_SPEED_DISABLE ),
.TARGET_LINK_SPEED (TARGET_LINK_SPEED ),
.ECRC_CHECK_EN (ECRC_CHECK_EN ),
.ECRC_GEN_EN (ECRC_GEN_EN ),
.EXT_TAG_EN (EXT_TAG_EN ),
.EXT_TAG_SUPP (EXT_TAG_SUPP ),
.PCIE_CAP_RCB (PCIE_CAP_RCB ),
.PCIE_CAP_CRS (PCIE_CAP_CRS ),
.PCIE_CAP_ATOMIC_EN (PCIE_CAP_ATOMIC_EN ),
.PCI_MSIX_ENABLE (PCI_MSIX_ENABLE ),
.PCI_FUNCTION_MASK (PCI_FUNCTION_MASK ),
.PCI_MSIX_TABLE_SIZE (PCI_MSIX_TABLE_SIZE ),
.PCI_MSIX_CPA_NEXT_OFFSET (PCI_MSIX_CPA_NEXT_OFFSET ),
.PCI_MSIX_TABLE_OFFSET (PCI_MSIX_TABLE_OFFSET ),
.PCI_MSIX_BIR (PCI_MSIX_BIR ),
.PCI_MSIX_PBA_OFFSET (PCI_MSIX_PBA_OFFSET ),
.PCI_MSIX_PBA_BIR (PCI_MSIX_PBA_BIR ),
.AER_CAP_NEXT_OFFSET (AER_CAP_NEXT_OFFSET ),
.TPH_REQ_NEXT_PTR (TPH_REQ_NEXT_PTR ),
.RESBAR_BAR0_MAX_SUPP_SIZE (RESBAR_BAR0_MAX_SUPP_SIZE ),
.RESBAR_BAR0_INIT_SIZE (RESBAR_BAR0_INIT_SIZE ),
.RESBAR_BAR1_MAX_SUPP_SIZE (RESBAR_BAR1_MAX_SUPP_SIZE ),
.RESBAR_BAR1_INIT_SIZE (RESBAR_BAR1_INIT_SIZE ),
.RESBAR_BAR2_MAX_SUPP_SIZE (RESBAR_BAR2_MAX_SUPP_SIZE ),
.RESBAR_BAR2_INIT_SIZE (RESBAR_BAR2_INIT_SIZE ),
.UPCONFIGURE_SUPPORT (UPCONFIGURE_SUPPORT )
) u_pcie_hard_ctrl (
.mem_clk (pclk ), // input
.pclk (pclk ), // input
.pclk_div2 (pclk_div2 ), // input
.button_rst (!i_button_rstn ), // input
.power_up_rst (!i_power_up_rstn ), // input
.perst (!i_perstn ), // input
.core_rst_n (o_core_rst_n ), // output
.training_rst_n (o_training_rst_n ), // output
.app_init_rst (i_app_init_rst ), // input
.phy_rst_n (phy_rst_n ), // output
.rx_lane_flip_en (i_rx_lane_flip_en ), // input
.tx_lane_flip_en (i_tx_lane_flip_en ), // input
.smlh_link_up (o_smlh_link_up ), // output
.rdlh_link_up (o_rdlh_link_up ), // output
.app_req_retry_en (i_app_req_retry_en ), // input
.smlh_ltssm_state (o_smlh_ltssm_state ), // output [4:0]
.axis_master_tvalid (o_axis_master_tvalid ), // output
.axis_master_tready (i_axis_master_tready ), // input
.axis_master_tdata (o_axis_master_tdata ), // output [127:0]
.axis_master_tkeep (o_axis_master_tkeep ), // output [3:0]
.axis_master_tlast (o_axis_master_tlast ), // output
.axis_master_tuser (o_axis_master_tuser ), // output [7:0]
.trgt1_radm_pkt_halt (i_trgt1_radm_pkt_halt ), // input [2:0]
.radm_grant_tlp_type (o_radm_grant_tlp_type ), // output [5:0]
.axis_slave0_tready (o_axis_slave0_tready ), // output
.axis_slave0_tvalid (i_axis_slave0_tvalid ), // input
.axis_slave0_tdata (i_axis_slave0_tdata ), // input [127:0]
.axis_slave0_tlast (i_axis_slave0_tlast ), // input
.axis_slave0_tuser (i_axis_slave0_tuser ), // input
.axis_slave1_tready (o_axis_slave1_tready ), // output
.axis_slave1_tvalid (i_axis_slave1_tvalid ), // input
.axis_slave1_tdata (i_axis_slave1_tdata ), // input [127:0]
.axis_slave1_tlast (i_axis_slave1_tlast ), // input
.axis_slave1_tuser (i_axis_slave1_tuser ), // input
.axis_slave2_tready (o_axis_slave2_tready ), // output
.axis_slave2_tvalid (i_axis_slave2_tvalid ), // input
.axis_slave2_tdata (i_axis_slave2_tdata ), // input [127:0]
.axis_slave2_tlast (i_axis_slave2_tlast ), // input
.axis_slave2_tuser (i_axis_slave2_tuser ), // input
.pm_xtlh_block_tlp (o_pm_xtlh_block_tlp ), // output
//APB
.apb_sel (pcie_p_sel ), // input
.apb_strb (pcie_p_strb ), // input
.apb_addr (pcie_p_addr ), // input
.apb_wdata (pcie_p_wdata ), // input
.apb_ce (pcie_p_ce ), // input
.apb_we (pcie_p_we ), // input
.apb_rdy (pcie_p_rdy ), // output
.apb_rdata (pcie_p_rdata ), // output
.cfg_int_disable (o_cfg_int_disable ), // output
.tx_rst_done (tx_rst_done ), // input
.sys_int (i_sys_int ), // input
.inta_grt_mux (o_inta_grt_mux ), // output
.intb_grt_mux (o_intb_grt_mux ), // output
.intc_grt_mux (o_intc_grt_mux ), // output
.intd_grt_mux (o_intd_grt_mux ), // output
.ven_msi_req (i_ven_msi_req ), // input
.ven_msi_tc (i_ven_msi_tc ), // input [2:0]
.ven_msi_vector (i_ven_msi_vector ), // input [4:0]
.ven_msi_grant (o_ven_msi_grant ), // output
.cfg_msi_pending (i_cfg_msi_pending ), // input [(32*1)-1:0]
.cfg_msi_en (o_cfg_msi_en ), // output
.msix_addr (i_msix_addr ), // input [63:0]
.msix_data (i_msix_data ), // input [31:0]
.cfg_msix_en (o_cfg_msix_en ), // output
.cfg_msix_func_mask (o_cfg_msix_func_mask ), // output
.radm_pm_turnoff (o_radm_pm_turnoff ), // output
.radm_msg_unlock (o_radm_msg_unlock ), // output
.outband_pwrup_cmd (i_outband_pwrup_cmd ), // input
.pm_status (o_pm_status ), // output
.pm_dstate (o_pm_dstate ), // output [2:0]
.aux_pm_en (o_aux_pm_en ), // output
.pm_pme_en (o_pm_pme_en ), // output
.pm_linkst_in_l0s (o_pm_linkst_in_l0s ), // output
.pm_linkst_in_l1 (o_pm_linkst_in_l1 ), // output
.pm_linkst_in_l2 (o_pm_linkst_in_l2 ), // output
.pm_linkst_l2_exit (o_pm_linkst_l2_exit ), // output
.app_req_entr_l1 (i_app_req_entr_l1 ), // input
.app_ready_entr_l23 (i_app_ready_entr_l23 ), // input
.app_req_exit_l1 (i_app_req_exit_l1 ), // input
.app_xfer_pending (i_app_xfer_pending ), // input
.wake (o_wake ), // output
.radm_pm_pme (o_radm_pm_pme ), // output
.radm_pm_to_ack (o_radm_pm_to_ack ), // output
.apps_pm_xmt_turnoff (i_apps_pm_xmt_turnoff ), // input
.app_unlock_msg (i_app_unlock_msg ), // input
.apps_pm_xmt_pme (i_apps_pm_xmt_pme ), // input
.app_clk_pm_en (i_app_clk_pm_en ), // input
.pm_master_state (o_pm_master_state ), // output [4:0]
.pm_slave_state (o_pm_slave_state ), // output [4:0]
.sys_aux_pwr_det (i_sys_aux_pwr_det ), // input
.app_hdr_valid (i_app_hdr_valid ), // input
.app_hdr_log (i_app_hdr_log ), // input [127:0]
.app_err_bus (i_app_err_bus ), // input [12:0]
.app_err_advisory (i_app_err_advisory ), // input
.cfg_send_cor_err_mux (o_cfg_send_cor_err_mux ), // output
.cfg_send_nf_err_mux (o_cfg_send_nf_err_mux ), // output
.cfg_send_f_err_mux (o_cfg_send_f_err_mux ), // output
.cfg_sys_err_rc (o_cfg_sys_err_rc ), // output
.cfg_aer_rc_err_mux (o_cfg_aer_rc_err_mux ), // output
.radm_cpl_timeout (o_radm_cpl_timeout ), // output
.radm_timeout_cpl_tc (o_radm_timeout_cpl_tc ), // output [2:0]
.radm_timeout_cpl_tag (o_radm_timeout_cpl_tag ), // output [7:0]
.radm_timeout_cpl_attr (o_radm_timeout_cpl_attr ), // output [1:0]
.radm_timeout_cpl_len (o_radm_timeout_cpl_len ), // output [10:0]
.cfg_max_rd_req_size (o_cfg_max_rd_req_size ), // output [2:0]
.cfg_bus_master_en (o_cfg_bus_master_en ), // output
.cfg_max_payload_size (o_cfg_max_payload_size ), // output [2:0]
.cfg_ext_tag_en (o_cfg_ext_tag_en ), // output
.cfg_rcb (o_cfg_rcb ), // output
.cfg_mem_space_en (o_cfg_mem_space_en ), // output
.cfg_pm_no_soft_rst (o_cfg_pm_no_soft_rst ), // output
.cfg_crs_sw_vis_en (o_cfg_crs_sw_vis_en ), // output
.cfg_no_snoop_en (o_cfg_no_snoop_en ), // output
.cfg_relax_order_en (o_cfg_relax_order_en ), // output
.cfg_tph_req_en (o_cfg_tph_req_en ), // output [2-1:0]
.cfg_pf_tph_st_mode (o_cfg_pf_tph_st_mode ), // output [3-1:0]
.cfg_pbus_num (o_cfg_pbus_num ), // output [7:0]
.cfg_pbus_dev_num (o_cfg_pbus_dev_num ), // output [4:0]
.rbar_ctrl_update (o_rbar_ctrl_update ), // output
.cfg_atomic_req_en (o_cfg_atomic_req_en ), // output
.cfg_atomic_egress_block (o_cfg_atomic_egress_block ), // output
.radm_idle (o_radm_idle ), // output
.radm_q_not_empty (o_radm_q_not_empty ), // output
.radm_qoverflow (o_radm_qoverflow ), // output
.diag_ctrl_bus (i_diag_ctrl_bus ), // input [1:0]
.dyn_debug_info_sel (i_dyn_debug_info_sel ), // input [3:0]
.cfg_link_auto_bw_mux (o_cfg_link_auto_bw_mux ), // output
.cfg_bw_mgt_mux (o_cfg_bw_mgt_mux ), // output
.cfg_pme_mux (o_cfg_pme_mux ), // output
.debug_info_mux (o_debug_info_mux ), // output [132:0]
.app_ras_des_sd_hold_ltssm (i_app_ras_des_sd_hold_ltssm ), // input
.app_ras_des_tba_ctrl (i_app_ras_des_tba_ctrl ), // input [1:0]
.cfg_ido_req_en (o_cfg_ido_req_en ), // output
.cfg_ido_cpl_en (o_cfg_ido_cpl_en ), // output
.xadm_ph_cdts (o_xadm_ph_cdts ), // output [7:0]
.xadm_pd_cdts (o_xadm_pd_cdts ), // output [11:0]
.xadm_nph_cdts (o_xadm_nph_cdts ), // output [7:0]
.xadm_npd_cdts (o_xadm_npd_cdts ), // output [11:0]
.xadm_cplh_cdts (o_xadm_cplh_cdts ), // output [7:0]
.xadm_cpld_cdts (o_xadm_cpld_cdts ), // output [11:0]
.phy_rate_chng_halt (i_phy_rate_chng_halt ), // input
.mac_phy_powerdown (mac_phy_powerdown ), // output [1 : 0]
.phy_mac_rxelecidle ({{(4-HSST_LANE_NUM){1'b1}},phy_mac_rxelecidle} ), // input max[3:0]
.phy_mac_phystatus (phy_mac_phystatus ), // input [3:0]
.phy_mac_rxdata ({{(128-HSST_LANE_NUM*32){1'b0}},phy_mac_rxdata}), // input max[127:0]
.phy_mac_rxdatak ({{(16-HSST_LANE_NUM*4){1'b0}},phy_mac_rxdatak} ), // input max[15:0]
.phy_mac_rxvalid ({{(4-HSST_LANE_NUM){1'b0}},phy_mac_rxvalid} ), // input max[3:0]
.phy_mac_rxstatus ({{(12-HSST_LANE_NUM*3){1'b0}},phy_mac_rxstatus}), // input max[(4*3)-1:0]
.mac_phy_txdata (mac_phy_txdata ), // output [127:0]
.mac_phy_txdatak (mac_phy_txdatak ), // output [15:0]
.mac_phy_txdetectrx_loopback (mac_phy_txdetectrx_loopback ), // output [3:0]
.mac_phy_txelecidle_l (mac_phy_txelecidle_l ), // output [3:0]
.mac_phy_txelecidle_h (mac_phy_txelecidle_h ), // output [3:0]
.mac_phy_txcompliance (mac_phy_txcompliance ), // output [3:0]
.mac_phy_rxpolarity (mac_phy_rxpolarity ), // output [3:0]
.mac_phy_rate (mac_phy_rate ), // output
.mac_phy_txdeemph (mac_phy_txdeemph ), // output [1:0]
.mac_phy_txmargin (mac_phy_txmargin ), // output [2:0]
.mac_phy_txswing (mac_phy_txswing ) // output
//.cfg_hw_auto_sp_dis (cfg_hw_auto_sp_dis ) // output
);
ipsl_pcie_soft_phy_v1_2a #(
.HSST_LANE_NUM (HSST_LANE_NUM )
) u_pcie_soft_phy (
.button_rst_n (i_button_rstn ), // input
.external_rstn (i_power_up_rstn ), // input
.phy_rst_n (phy_rst_n ), // input
.P_TXN (o_txn_lane ), // output
.P_TXP (o_txp_lane ), // output
.P_RXN (i_rxn_lane ), // input
.P_RXP (i_rxp_lane ), // input
.P_REFCKN (i_refckn ), // input
.P_REFCKP (i_refckp ), // input
.P_REFCK2CORE_0 (o_refck2core_0 ), // output
.free_clk (free_clk ),
.pclk (pclk ), // output
.pclk_div2 (pclk_div2 ), // output
.i_p_cfg_psel (hsst_p_sel ), // input
.i_p_cfg_enable (hsst_p_ce ), // input
.i_p_cfg_write (hsst_p_we ), // input
.i_p_cfg_addr (hsst_p_addr ), // input [15:0]
.i_p_cfg_wdata (hsst_p_wdata[7:0] ), // input [7:0]
.o_p_cfg_rdata (hsst_p_rdata ), // output [7:0]
.o_p_cfg_int ( ), // output
.o_p_cfg_ready (hsst_p_rdy ), // output
.tx_rst_done (tx_rst_done ), // output
.mac_phy_powerdown (mac_phy_powerdown ), // input [1:0]
.phy_mac_rxelecidle (phy_mac_rxelecidle ), // output [3:0]
.phy_mac_phystatus (phy_mac_phystatus ), // output [3:0]
.phy_mac_rxdata (phy_mac_rxdata ), // output [127:0]
.phy_mac_rxdatak (phy_mac_rxdatak ), // output [15:0]
.phy_mac_rxvalid (phy_mac_rxvalid ), // output [3:0]
.phy_mac_rxstatus (phy_mac_rxstatus ), // output [(4*3)-1:0]
.mac_phy_txdata (mac_phy_txdata[0+:HSST_LANE_NUM*32]), // input max[127:0]
.mac_phy_txdatak (mac_phy_txdatak[0+:HSST_LANE_NUM*4]), // input max[15:0]
.mac_phy_txdetectrx_loopback (mac_phy_txdetectrx_loopback[0+:HSST_LANE_NUM]), // input max[3:0]
.mac_phy_txelecidle_h (mac_phy_txelecidle_h[0+:HSST_LANE_NUM]), // input max[3:0]
.mac_phy_txelecidle_l (mac_phy_txelecidle_l[0+:HSST_LANE_NUM]), // input max[3:0]
.mac_phy_txcompliance (mac_phy_txcompliance[0+:HSST_LANE_NUM]), // input max[3:0]
.mac_phy_rxpolarity (mac_phy_rxpolarity[0+:HSST_LANE_NUM]), // input [3:0]
.mac_phy_rate (mac_phy_rate ), // input
.mac_phy_txdeemph (mac_phy_txdeemph ), // input [1:0]
.mac_phy_txmargin (mac_phy_txmargin ), // input [2:0]
.mac_phy_txswing (mac_phy_txswing ), // input
.pcs_nearend_loop (i_pcs_nearend_loop[0+:HSST_LANE_NUM] ), // input max[3:0]
.pma_nearend_ploop (i_pma_nearend_ploop[0+:HSST_LANE_NUM]), // input max[3:0]
.pma_nearend_sloop (i_pma_nearend_sloop[0+:HSST_LANE_NUM]), // input max[3:0]
.phy_rate_chng_halt (i_phy_rate_chng_halt ) // output reg
);
endmodule |
module ipsl_pcie_apb2dbi_v1_0 (
input pclk_div2 ,
input apb_rst_n ,
input p_sel ,
input [ 3:0] p_strb ,
input [15:0] p_addr , // dbi use [11:2]
input [31:0] p_wdata ,
input p_ce ,
input p_we ,
output reg p_rdy ,
output reg [31:0] p_rdata ,
output reg [31:0] dbi_addr ,
output reg [31:0] dbi_din ,
output reg dbi_cs ,
output reg dbi_cs2 ,
output reg [ 3:0] dbi_wr ,
output reg app_dbi_ro_wr_disable ,
input lbc_dbi_ack ,
input [31:0] lbc_dbi_dout ,
input dbi_halt
);
wire apb_access ;
wire dbi_standby ;
assign dbi_standby = !(dbi_cs || lbc_dbi_ack);
assign apb_access = (p_sel && p_ce && !p_rdy);
always @(posedge pclk_div2 or negedge apb_rst_n) begin
if (!apb_rst_n)
begin
app_dbi_ro_wr_disable <= 1'd0;
dbi_cs2 <= 1'b0;
dbi_cs <= 1'b0;
dbi_addr <= 32'd0;
dbi_din <= 32'd0;
end
else if (apb_access && dbi_standby)
begin
if (p_addr[1])
app_dbi_ro_wr_disable <= 1'b1;
if (p_addr[0])
dbi_cs2 <= 1'b1;
else
dbi_cs2 <= 1'b0;
dbi_cs <= 1'b1;
dbi_addr <= {20'd0,p_addr[11:2],2'd0};
dbi_din <= p_wdata;
end
else if (lbc_dbi_ack)
begin
dbi_cs <= 1'b0;
dbi_cs2 <= 1'b0;
end
else
app_dbi_ro_wr_disable <= 1'b0;
end
always @(posedge pclk_div2 or negedge apb_rst_n) begin
if (!apb_rst_n)
dbi_wr <= 4'd0;
else if (dbi_standby && apb_access && p_we)
dbi_wr <= p_strb;
else
dbi_wr <= 4'd0;
end
always @(posedge pclk_div2 or negedge apb_rst_n) begin
if (!apb_rst_n)
begin
p_rdy <= 1'b0;
p_rdata <= 32'd0;
end
else if (!dbi_cs && lbc_dbi_ack && p_sel && p_ce)
begin
if (!dbi_halt)
p_rdy <= 1'b1;
else
p_rdy <= 1'b0;
if (!p_we)
p_rdata <= lbc_dbi_dout;
end
else
p_rdy <= 1'b0;
end
endmodule |
module ipsl_pcie_seio_intf_v1_0(
input pclk_div2 ,
input user_rst_n ,
input sedo_in ,
input sedo_en_in ,
output wire sedi ,
output reg sedi_ack
);
reg [1:0] seio_state ;
reg [1:0] seio_nxt_state ;
reg sedo_in_r ;
reg sedo_in_2r ;
reg sedo_en_r ;
reg sedo_en_2r ;
localparam SEIO_IDLE = 2'b00;
localparam SEIO_BUSY = 2'b01;
localparam SEIO_NACK = 2'b10;
assign sedi = 1'b0;
//----------------PHASE1
always @(posedge pclk_div2 or negedge user_rst_n)
if(!user_rst_n)
seio_state <= SEIO_IDLE;
else
seio_state <= seio_nxt_state;
//----------------PHASE2
always@(*)
case(seio_state)
SEIO_IDLE:begin
if(sedo_en_2r & sedo_in_r & ~sedo_in_2r) //WR OP
seio_nxt_state = SEIO_BUSY;
else if(sedo_en_2r & ~sedo_in_r & sedo_in_2r) //RD OP
seio_nxt_state = SEIO_BUSY;
else
seio_nxt_state = SEIO_IDLE;
end
SEIO_BUSY:begin
if(sedo_en_2r & ~sedo_en_r) //falling edge of sedo_en
seio_nxt_state = SEIO_NACK;
else
seio_nxt_state = SEIO_BUSY;
end
SEIO_NACK:begin
if(sedi_ack)
seio_nxt_state = SEIO_IDLE;
else
seio_nxt_state = SEIO_NACK;
end
default:seio_nxt_state = SEIO_IDLE;
endcase
//------------------------------SEIO Logic
always @(posedge pclk_div2 or negedge user_rst_n)
if(!user_rst_n)begin
sedo_in_r <= 1'b0;
sedo_in_2r <= 1'b0;
sedo_en_r <= 1'b0;
sedo_en_2r <= 1'b0;
end
else begin
sedo_in_r <= sedo_in;
sedo_in_2r <= sedo_in_r;
sedo_en_r <= sedo_en_in;
sedo_en_2r <= sedo_en_r;
end
always @(posedge pclk_div2 or negedge user_rst_n)
if(!user_rst_n)
sedi_ack <= 1'b0;
else if(seio_state == SEIO_NACK)
sedi_ack <= ~sedi_ack; //1 cycle pulse
else
sedi_ack <= 1'b0;
endmodule |
module ipsl_expd_apb_mux (
//from uart domain
input i_uart_clk ,
input i_uart_rst_n ,
input i_uart_p_sel ,
input [3:0] i_uart_p_strb ,
input [15:0] i_uart_p_addr ,
input [31:0] i_uart_p_wdata ,
input i_uart_p_ce ,
input i_uart_p_we ,
output wire o_uart_p_rdy ,
output wire [31:0] o_uart_p_rdata ,
//to dma domain
input i_pclk_div2_clk ,
input i_pclk_div2_rst_n ,
//
output wire [3:0] o_pclk_div2_p_strb ,
output wire [15:0] o_pclk_div2_p_addr ,
output wire [31:0] o_pclk_div2_p_wdata ,
output wire o_pclk_div2_p_ce ,
output wire o_pclk_div2_p_we ,
output wire o_pcie_p_sel ,
input i_pcie_p_rdy ,
input [31:0] i_pcie_p_rdata ,
output wire o_dma_p_sel ,
input i_dma_p_rdy ,
input [31:0] i_dma_p_rdata ,
//to cfg domain
output wire o_cfg_p_sel ,
input i_cfg_p_rdy ,
input [31:0] i_cfg_p_rdata
);
wire expd_sel ;
wire expd_rdy ;
wire [31:0] expd_rdata ;
wire pclk_div2_p_sel ;
wire pclk_div2_p_rdy ;
wire [31:0] pclk_div2_p_rdata ;
//apb mux
assign o_pcie_p_sel = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >=7)) ? i_uart_p_sel : 1'b0 ;
assign expd_sel = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >=7)) ? 1'b0 : i_uart_p_sel ;
assign o_uart_p_rdy = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >=7)) ? i_pcie_p_rdy : expd_rdy;
assign o_uart_p_rdata = ((i_uart_p_addr[15:12] < 4'h2) || (i_uart_p_addr[15:12] >=7)) ? i_pcie_p_rdata : expd_rdata ;
ipsl_pcie_apb_cross_v1_0 u_pcie_expd_apb_cross(
//from src domain
.i_src_clk (i_uart_clk ),
.i_src_rst_n (i_uart_rst_n ),
.i_src_p_sel (expd_sel ),
.i_src_p_strb (i_uart_p_strb ),
.i_src_p_addr (i_uart_p_addr ),
.i_src_p_wdata (i_uart_p_wdata ),
.i_src_p_ce (i_uart_p_ce ),
.i_src_p_we (i_uart_p_we ),
.o_src_p_rdy (expd_rdy ),
.o_src_p_rdata (expd_rdata ),
//to target domain
.i_des_clk (i_pclk_div2_clk ),
.i_des_rst_n (i_pclk_div2_rst_n ),
.o_des_p_sel (pclk_div2_p_sel ),
.o_des_p_strb (o_pclk_div2_p_strb ),
.o_des_p_addr (o_pclk_div2_p_addr ),
.o_des_p_wdata (o_pclk_div2_p_wdata ),
.o_des_p_ce (o_pclk_div2_p_ce ),
.o_des_p_we (o_pclk_div2_p_we ),
.i_des_p_rdy (pclk_div2_p_rdy ),
.i_des_p_rdata (pclk_div2_p_rdata )
);
assign o_dma_p_sel = (o_pclk_div2_p_addr[15:12] == 4'h3) ? pclk_div2_p_sel : 1'b0 ;
assign o_cfg_p_sel = (o_pclk_div2_p_addr[15:12] == 4'h4) ? pclk_div2_p_sel : 1'b0 ;
assign pclk_div2_p_rdy = (o_pclk_div2_p_addr[15:12] == 4'h3) ? i_dma_p_rdy :
(o_pclk_div2_p_addr[15:12] == 4'h4) ? i_cfg_p_rdy : 1'b0 ;
assign pclk_div2_p_rdata = (o_pclk_div2_p_addr[15:12] == 4'h3) ? i_dma_p_rdata :
(o_pclk_div2_p_addr[15:12] == 4'h4) ? i_cfg_p_rdata : 32'b0 ;
endmodule |
module pango_pcie_top_sim
#(
parameter integer APP_DEV_NUM = 0 , // set device_number,RC only
parameter integer APP_BUS_NUM = 0 // set bus_number,RC only
)
(
input button_rst_n ,
input perst_n ,
input free_clk ,
//UART interface
output wire txd ,
input rxd ,
//clk and rst
input ref_clk_n ,
input ref_clk_p ,
//diff signals
input [1:0] rxn ,
input [1:0] rxp ,
output wire [1:0] txn ,
output wire [1:0] txp ,
//LED signals
output reg ref_led ,
output reg pclk_led ,
output reg pclk_div2_led ,
output wire smlh_link_up ,
output wire rdlh_link_up
);
localparam DEVICE_TYPE = 3'b100;
localparam AXIS_SLAVE_NUM = 3 ; //@IPC enum 1 2 3
//TEST UNIT MODE SIGNALS
wire pcie_cfg_ctrl_en ;
wire axis_master_tready_cfg ;
wire cfg_axis_slave0_tvalid ;
wire [127:0] cfg_axis_slave0_tdata ;
wire cfg_axis_slave0_tlast ;
wire cfg_axis_slave0_tuser ;
//for mux
wire axis_master_tready_mem ;
wire axis_master_tvalid_mem ;
wire [127:0] axis_master_tdata_mem ;
wire [3:0] axis_master_tkeep_mem ;
wire axis_master_tlast_mem ;
wire [7:0] axis_master_tuser_mem ;
wire cross_4kb_boundary ;
wire dma_axis_slave0_tvalid ;
wire [127:0] dma_axis_slave0_tdata ;
wire dma_axis_slave0_tlast ;
wire dma_axis_slave0_tuser ;
//RESET DEBOUNCE and SYNC
wire sync_button_rst_n ;
wire s_pclk_rstn ;
wire s_pclk_div2_rstn ;
//********************** internal signal
//clk and rst
wire pclk_div2 ;
wire pclk ;
wire ref_clk ;
wire core_rst_n ;
//AXIS master interface
wire axis_master_tvalid ;
wire axis_master_tready ;
wire [127:0] axis_master_tdata ;
wire [3:0] axis_master_tkeep ;
wire axis_master_tlast ;
wire [7:0] axis_master_tuser ;
//axis slave 0 interface
wire axis_slave0_tready ;
wire axis_slave0_tvalid ;
wire [127:0] axis_slave0_tdata ;
wire axis_slave0_tlast ;
wire axis_slave0_tuser ;
//axis slave 1 interface
wire axis_slave1_tready ;
wire axis_slave1_tvalid ;
wire [127:0] axis_slave1_tdata ;
wire axis_slave1_tlast ;
wire axis_slave1_tuser ;
//axis slave 2 interface
wire axis_slave2_tready ;
wire axis_slave2_tvalid ;
wire [127:0] axis_slave2_tdata ;
wire axis_slave2_tlast ;
wire axis_slave2_tuser ;
wire [7:0] cfg_pbus_num ;
wire [4:0] cfg_pbus_dev_num ;
wire [2:0] cfg_max_rd_req_size ;
wire [2:0] cfg_max_payload_size ;
wire cfg_rcb ;
wire cfg_ido_req_en ;
wire cfg_ido_cpl_en ;
wire [7:0] xadm_ph_cdts ;
wire [11:0] xadm_pd_cdts ;
wire [7:0] xadm_nph_cdts ;
wire [11:0] xadm_npd_cdts ;
wire [7:0] xadm_cplh_cdts ;
wire [11:0] xadm_cpld_cdts ;
//system signal
wire [4:0] smlh_ltssm_state ;
// led lights up
reg [23:0] ref_led_cnt ;
reg [26:0] pclk_led_cnt ;
reg [26:0] pclk_div2_led_cnt ;
//uart2apb 32bits
wire uart_p_sel ;
wire [3:0] uart_p_strb ;
wire [15:0] uart_p_addr ;
wire [31:0] uart_p_wdata ;
wire uart_p_ce ;
wire uart_p_we ;
wire uart_p_rdy ;
wire [31:0] uart_p_rdata ;
//APB
wire [3:0] p_strb ;
wire [15:0] p_addr ;
wire [31:0] p_wdata ;
wire p_ce ;
wire p_we ;
//apb mux
wire p_sel_pcie ; //0~1,8~f:hsst 2,5,6:Reserved 7:pcie
wire p_sel_cfg ; //4: cfg
wire p_sel_dma ; //3: dma
wire [31:0] p_rdata_pcie ; //0~1,8~f:hsst 2,5,6:Reserved 7:pcie
wire [31:0] p_rdata_cfg ; //4: cfg
wire [31:0] p_rdata_dma ; //3: dma
wire p_rdy_pcie ; //0~1,8~f:hsst 2,5,6:Reserved 7:pcie
wire p_rdy_cfg ; //4: cfg
wire p_rdy_dma ; //3: dma
assign cfg_ido_req_en = 1'b0;
assign cfg_ido_cpl_en = 1'b0;
assign xadm_ph_cdts = 8'b0;
assign xadm_pd_cdts = 12'b0;
assign xadm_nph_cdts = 8'b0;
assign xadm_npd_cdts = 12'b0;
assign xadm_cplh_cdts = 8'b0;
assign xadm_cpld_cdts = 12'b0;
//----------------------------------------------------------rst debounce ----------------------------------------------------------
//ASYNC RST define IPSL_PCIE_SPEEDUP_SIM when simulation
hsst_rst_cross_sync_v1_0 #(
`ifdef IPSL_PCIE_SPEEDUP_SIM
.RST_CNTR_VALUE (16'h10 )
`else
.RST_CNTR_VALUE (16'hC000 )
`endif
)
u_refclk_buttonrstn_debounce(
.clk (ref_clk ),
.rstn_in (button_rst_n ),
.rstn_out (sync_button_rst_n )
);
hsst_rst_cross_sync_v1_0 #(
`ifdef IPSL_PCIE_SPEEDUP_SIM
.RST_CNTR_VALUE (16'h10 )
`else
.RST_CNTR_VALUE (16'hC000 )
`endif
)
u_refclk_perstn_debounce(
.clk (ref_clk ),
.rstn_in (perst_n ),
.rstn_out (sync_perst_n )
);
ipsl_pcie_sync_v1_0 u_ref_core_rstn_sync (
.clk (ref_clk ),
.rst_n (core_rst_n ),
.sig_async (1'b1 ),
.sig_synced (ref_core_rst_n )
);
ipsl_pcie_sync_v1_0 u_pclk_core_rstn_sync (
.clk (pclk ),
.rst_n (core_rst_n ),
.sig_async (1'b1 ),
.sig_synced (s_pclk_rstn )
);
ipsl_pcie_sync_v1_0 u_pclk_div2_core_rstn_sync (
.clk (pclk_div2 ),
.rst_n (core_rst_n ),
.sig_async (1'b1 ),
.sig_synced (s_pclk_div2_rstn )
);
//----------------------------------------------------------clk led ----------------------------------------------------------
always @(posedge ref_clk or negedge sync_perst_n)
begin
if (!sync_perst_n)
ref_led_cnt <= 24'd0;
else
ref_led_cnt <= ref_led_cnt + 24'd1;
end
always @(posedge ref_clk or negedge sync_perst_n)
begin
if (!sync_perst_n)
ref_led <= 1'b1;
else if(&ref_led_cnt)
ref_led <= ~ref_led;
end
always @(posedge pclk or negedge s_pclk_rstn)
begin
if (!s_pclk_rstn)
pclk_led_cnt <= 27'd0;
else
pclk_led_cnt <= pclk_led_cnt + 27'd1;
end
always @(posedge pclk or negedge s_pclk_rstn)
begin
if (!s_pclk_rstn)
pclk_led <= 1'b1;
else if(&pclk_led_cnt)
pclk_led <= ~pclk_led;
end
always @(posedge pclk_div2 or negedge s_pclk_div2_rstn)
begin
if (!s_pclk_div2_rstn)
pclk_div2_led_cnt <= 27'd0;
else
pclk_div2_led_cnt <= pclk_div2_led_cnt + 27'd1;
end
always @(posedge pclk_div2 or negedge s_pclk_div2_rstn)
begin
if (!s_pclk_div2_rstn)
pclk_div2_led <= 1'b1;
else if(&pclk_div2_led_cnt)
pclk_div2_led <= ~pclk_div2_led;
end
//----------------------------------------------------------uart2apb ----------------------------------------------------------
pgr_uart2apb_top_32bit u_uart2apb_top
(
.i_clk (ref_clk ), // input
.i_rst_n (ref_core_rst_n ), // input
//apb enable
.o_p_sel (uart_p_sel ), // output
.o_p_strb (uart_p_strb ), // output [SW-1:0]
.o_p_addr (uart_p_addr ), // output [AW-1:0]
.o_p_wdata (uart_p_wdata ), // output [DW-1:0]
.o_p_enable (uart_p_ce ), // output
.o_p_we (uart_p_we ), // output
.i_p_ready (uart_p_rdy ), // input
.i_p_rdata (uart_p_rdata ), // input [DW-1:0]
.i_apb_en (1'b1 ), // input
.i_strb_en (1'b1 ), // input
//uart
.o_uart_txd (txd ), // output
.i_uart_rxd (rxd ), // input
//just for debug
.rx_overrun ( ), // output
.rx_chk_err ( ), // output
//apb bypass
.o_uart_txvld ( ), // output
.i_uart_txreq (1'd0 ), // input
.i_uart_txdata(8'd0 ), // input [7:0]
.i_uart_rxreq (1'd0 ), // input
.o_uart_rxdata( ), // output [7:0]
.o_uart_rxvld ( ) // output
);
//----------------------------------------------------------apb mux----------------------------------------------------------
ipsl_expd_apb_mux u_ipsl_pcie_expd_apb_mux(
//from ref_clk domain
.i_uart_clk (ref_clk ),
.i_uart_rst_n (ref_core_rst_n ),
.i_uart_p_sel (uart_p_sel ),
.i_uart_p_strb (uart_p_strb ),
.i_uart_p_addr (uart_p_addr ),
.i_uart_p_wdata (uart_p_wdata ),
.i_uart_p_ce (uart_p_ce ),
.i_uart_p_we (uart_p_we ),
.o_uart_p_rdy (uart_p_rdy ),
.o_uart_p_rdata (uart_p_rdata ),
//to pclk_div2 domain
.i_pclk_div2_clk (pclk_div2 ),
.i_pclk_div2_rst_n (core_rst_n ),
.o_pclk_div2_p_strb (p_strb ),
.o_pclk_div2_p_addr (p_addr ),
.o_pclk_div2_p_wdata (p_wdata ),
.o_pclk_div2_p_ce (p_ce ),
.o_pclk_div2_p_we (p_we ),
//to pcie
.o_pcie_p_sel (p_sel_pcie ),
.i_pcie_p_rdy (p_rdy_pcie ),
.i_pcie_p_rdata (p_rdata_pcie ),
//to dma
.o_dma_p_sel (p_sel_dma ),
.i_dma_p_rdy (p_rdy_dma ),
.i_dma_p_rdata (p_rdata_dma ),
//to cfg
.o_cfg_p_sel (p_sel_cfg ),
.i_cfg_p_rdy (p_rdy_cfg ),
.i_cfg_p_rdata (p_rdata_cfg )
);
//---------------------------------------------------------- dma ----------------------------------------------------------
// DMA CTRL BASE ADDR = 0x8000
ipsl_pcie_dma #(
.DEVICE_TYPE (DEVICE_TYPE ),
.AXIS_SLAVE_NUM (AXIS_SLAVE_NUM )
)
u_ipsl_pcie_dma
(
.clk (pclk_div2 ), //gen1:62.5MHz,gen2:125MHz
.rst_n (core_rst_n ),
//num
.i_cfg_pbus_num (cfg_pbus_num ), //input [7:0]
.i_cfg_pbus_dev_num (cfg_pbus_dev_num ), //input [4:0]
.i_cfg_max_rd_req_size (cfg_max_rd_req_size ), //input [2:0]
.i_cfg_max_payload_size (cfg_max_payload_size ), //input [2:0]
//**********************************************************************
//axis master interface
.i_axis_master_tvld (axis_master_tvalid_mem ),
.o_axis_master_trdy (axis_master_tready_mem ),
.i_axis_master_tdata (axis_master_tdata_mem ),
.i_axis_master_tkeep (axis_master_tkeep_mem ),
.i_axis_master_tlast (axis_master_tlast_mem ),
.i_axis_master_tuser (axis_master_tuser_mem ),
//**********************************************************************
//axis_slave0 interface
.i_axis_slave0_trdy (axis_slave0_tready ),
.o_axis_slave0_tvld (dma_axis_slave0_tvalid ),
.o_axis_slave0_tdata (dma_axis_slave0_tdata ),
.o_axis_slave0_tlast (dma_axis_slave0_tlast ),
.o_axis_slave0_tuser (dma_axis_slave0_tuser ),
//axis_slave1 interface
.i_axis_slave1_trdy (axis_slave1_tready ),
.o_axis_slave1_tvld (axis_slave1_tvalid ),
.o_axis_slave1_tdata (axis_slave1_tdata ),
.o_axis_slave1_tlast (axis_slave1_tlast ),
.o_axis_slave1_tuser (axis_slave1_tuser ),
//axis_slave2 interface
.i_axis_slave2_trdy (axis_slave2_tready ),
.o_axis_slave2_tvld (axis_slave2_tvalid ),
.o_axis_slave2_tdata (axis_slave2_tdata ),
.o_axis_slave2_tlast (axis_slave2_tlast ),
.o_axis_slave2_tuser (axis_slave2_tuser ),
//from pcie
.i_cfg_ido_req_en (cfg_ido_req_en ),
.i_cfg_ido_cpl_en (cfg_ido_cpl_en ),
.i_xadm_ph_cdts (xadm_ph_cdts ),
.i_xadm_pd_cdts (xadm_pd_cdts ),
.i_xadm_nph_cdts (xadm_nph_cdts ),
.i_xadm_npd_cdts (xadm_npd_cdts ),
.i_xadm_cplh_cdts (xadm_cplh_cdts ),
.i_xadm_cpld_cdts (xadm_cpld_cdts ),
//**********************************************************************
//apb interface
.i_apb_psel (p_sel_dma ),
.i_apb_paddr (p_addr[8:0] ),
.i_apb_pwdata (p_wdata ),
.i_apb_pstrb (p_strb ),
.i_apb_pwrite (p_we ),
.i_apb_penable (p_ce ),
.o_apb_prdy (p_rdy_dma ),
.o_apb_prdata (p_rdata_dma ),
.o_cross_4kb_boundary (cross_4kb_boundary )
);
generate
if (DEVICE_TYPE == 3'd4)
begin:rc
//---------------------------------------------------------- cfg ctrl ----------------------------------------------------------
//CFG TLP TX RX BASE ADDR = 0x9000
ipsl_pcie_cfg_ctrl u_pcie_cfg_ctrl(
//from APB
.pclk_div2 (pclk_div2 ),
.apb_rst_n (core_rst_n ),
.p_sel (p_sel_cfg ),
.p_strb (p_strb ),
.p_addr (p_addr[7:0] ),
.p_wdata (p_wdata ),
.p_ce (p_ce ),
.p_we (p_we ),
.p_rdy (p_rdy_cfg ),
.p_rdata (p_rdata_cfg ),
.pcie_cfg_ctrl_en (pcie_cfg_ctrl_en ),
//to PCIE ctrl
.axis_slave_tready (axis_slave0_tready ),
.axis_slave_tvalid (cfg_axis_slave0_tvalid ),
.axis_slave_tlast (cfg_axis_slave0_tlast ),
.axis_slave_tuser (cfg_axis_slave0_tuser ),
.axis_slave_tdata (cfg_axis_slave0_tdata ),
.axis_master_tready (axis_master_tready_cfg ),
.axis_master_tvalid (axis_master_tvalid ),
.axis_master_tlast (axis_master_tlast ),
// .axis_master_tuser (axis_master_tuser ),
.axis_master_tkeep (axis_master_tkeep ),
.axis_master_tdata (axis_master_tdata )
);
//---------------------------------------------------------- logic mux ----------------------------------------------------------
assign axis_slave0_tvalid = pcie_cfg_ctrl_en ? cfg_axis_slave0_tvalid : dma_axis_slave0_tvalid;
assign axis_slave0_tlast = pcie_cfg_ctrl_en ? cfg_axis_slave0_tlast : dma_axis_slave0_tlast;
assign axis_slave0_tuser = pcie_cfg_ctrl_en ? cfg_axis_slave0_tuser : dma_axis_slave0_tuser;
assign axis_slave0_tdata = pcie_cfg_ctrl_en ? cfg_axis_slave0_tdata : dma_axis_slave0_tdata;
assign axis_master_tvalid_mem = pcie_cfg_ctrl_en ? 1'b0 : axis_master_tvalid;
assign axis_master_tdata_mem = pcie_cfg_ctrl_en ? 128'b0 : axis_master_tdata;
assign axis_master_tkeep_mem = pcie_cfg_ctrl_en ? 4'b0 : axis_master_tkeep;
assign axis_master_tlast_mem = pcie_cfg_ctrl_en ? 1'b0 : axis_master_tlast;
assign axis_master_tuser_mem = pcie_cfg_ctrl_en ? 8'b0 : axis_master_tuser;
assign axis_master_tready = pcie_cfg_ctrl_en ? axis_master_tready_cfg : axis_master_tready_mem;
end
else
begin:ep
assign p_rdy_cfg = 1'b0;
assign p_rdata_cfg = 32'b0;
assign axis_slave0_tvalid = dma_axis_slave0_tvalid;
assign axis_slave0_tlast = dma_axis_slave0_tlast;
assign axis_slave0_tuser = dma_axis_slave0_tuser;
assign axis_slave0_tdata = dma_axis_slave0_tdata;
assign axis_master_tvalid_mem = axis_master_tvalid;
assign axis_master_tdata_mem = axis_master_tdata;
assign axis_master_tkeep_mem = axis_master_tkeep;
assign axis_master_tlast_mem = axis_master_tlast;
assign axis_master_tuser_mem = axis_master_tuser;
assign axis_master_tready = axis_master_tready_mem;
end
endgenerate
//---------------------------------------------------------- pcie wrap ----------------------------------------------------------
//pcie wrap : HSSTLP : 0x0000~6000 PCIe BASE ADDR : 0x7000
ipsl_pcie_wrap_v1_3_sim
#(
.APP_DEV_NUM (APP_DEV_NUM ), // set device_number
.APP_BUS_NUM (APP_BUS_NUM ) // set bus_number
)
u_ipsl_pcie_wrap
(
.button_rst_n (sync_button_rst_n ),
.power_up_rst_n (sync_perst_n ),
.perst_n (sync_perst_n ),
//clk and rst
.free_clk (free_clk ),
.pclk (pclk ), //output
.pclk_div2 (pclk_div2 ), //output
.ref_clk (ref_clk ), //output
.ref_clk_n (ref_clk_n ), //input
.ref_clk_p (ref_clk_p ), //input
.core_rst_n (core_rst_n ), //output
//APB interface to DBI cfg
// .p_clk (ref_clk ), //input
.p_sel (p_sel_pcie ), //input
.p_strb (uart_p_strb ), //input [ 3:0]
.p_addr (uart_p_addr ), //input [15:0]
.p_wdata (uart_p_wdata ), //input [31:0]
.p_ce (uart_p_ce ), //input
.p_we (uart_p_we ), //input
.p_rdy (p_rdy_pcie ), //output
.p_rdata (p_rdata_pcie ), //output [31:0]
//PHY diff signals
.rxn (rxn ), //input max[3:0]
.rxp (rxp ), //input max[3:0]
.txn (txn ), //output max[3:0]
.txp (txp ), //output max[3:0]
.pcs_nearend_loop ({2{1'b0}} ), //input
.pma_nearend_ploop ({2{1'b0}} ), //input
.pma_nearend_sloop ({2{1'b0}} ), //input
//AXIS master interface
.axis_master_tvalid (axis_master_tvalid ), //output
.axis_master_tready (axis_master_tready ), //input
.axis_master_tdata (axis_master_tdata ), //output [127:0]
.axis_master_tkeep (axis_master_tkeep ), //output [3:0]
.axis_master_tlast (axis_master_tlast ), //output
.axis_master_tuser (axis_master_tuser ), //output [7:0]
//axis slave 0 interface
.axis_slave0_tready (axis_slave0_tready ), //output
.axis_slave0_tvalid (axis_slave0_tvalid ), //input
.axis_slave0_tdata (axis_slave0_tdata ), //input [127:0]
.axis_slave0_tlast (axis_slave0_tlast ), //input
.axis_slave0_tuser (axis_slave0_tuser ), //input
//axis slave 1 interface
.axis_slave1_tready (axis_slave1_tready ), //output
.axis_slave1_tvalid (axis_slave1_tvalid ), //input
.axis_slave1_tdata (axis_slave1_tdata ), //input [127:0]
.axis_slave1_tlast (axis_slave1_tlast ), //input
.axis_slave1_tuser (axis_slave1_tuser ), //input
//axis slave 2 interface
.axis_slave2_tready (axis_slave2_tready ), //output
.axis_slave2_tvalid (axis_slave2_tvalid ), //input
.axis_slave2_tdata (axis_slave2_tdata ), //input [127:0]
.axis_slave2_tlast (axis_slave2_tlast ), //input
.axis_slave2_tuser (axis_slave2_tuser ), //input
.pm_xtlh_block_tlp ( ), //output
.cfg_send_cor_err_mux ( ), //output
.cfg_send_nf_err_mux ( ), //output
.cfg_send_f_err_mux ( ), //output
.cfg_sys_err_rc ( ), //output
.cfg_aer_rc_err_mux ( ), //output
//radm timeout
.radm_cpl_timeout ( ), //output
//configuration signals
.cfg_max_rd_req_size (cfg_max_rd_req_size ), //output [2:0]
.cfg_bus_master_en ( ), //output
.cfg_max_payload_size (cfg_max_payload_size ), //output [2:0]
.cfg_ext_tag_en ( ), //output
.cfg_rcb (cfg_rcb ), //output
.cfg_mem_space_en ( ), //output
.cfg_pm_no_soft_rst ( ), //output
.cfg_crs_sw_vis_en ( ), //output
.cfg_no_snoop_en ( ), //output
.cfg_relax_order_en ( ), //output
.cfg_tph_req_en ( ), //output [2-1:0]
.cfg_pf_tph_st_mode ( ), //output [3-1:0]
.rbar_ctrl_update ( ), //output
.cfg_atomic_req_en ( ), //output
.cfg_pbus_num (cfg_pbus_num ), //output [7:0]
.cfg_pbus_dev_num (cfg_pbus_dev_num ), //output [4:0]
//debug signals
.radm_idle ( ), //output
.radm_q_not_empty ( ), //output
.radm_qoverflow ( ), //output
.diag_ctrl_bus (2'b0 ), //input [1:0]
.cfg_link_auto_bw_mux ( ), //output merge cfg_link_auto_bw_msi and cfg_link_auto_bw_int
.cfg_bw_mgt_mux ( ), //output merge cfg_bw_mgt_int and cfg_bw_mgt_msi
.cfg_pme_mux ( ), //output merge cfg_pme_int and cfg_pme_msi
.app_ras_des_sd_hold_ltssm (1'b0 ), //input
.app_ras_des_tba_ctrl (2'b0 ), //input [1:0]
.dyn_debug_info_sel (4'b0 ), //input [3:0]
.debug_info_mux ( ), //output [132:0]
//system signal
.smlh_link_up (smlh_link_up ), //output
.rdlh_link_up (rdlh_link_up ), //output
.smlh_ltssm_state (smlh_ltssm_state ) //output [4:0]
);
endmodule |
module pgr_cmd_parser_32bit#(
parameter AW = 8'd16,
parameter DW = 8'd32,
parameter SW = 8'd4,
parameter CLK_FREQ = 8'd50
)
(
input clk,
input rst_n,
input apb_en,
input strb_en,
input [7:0] fifo_data,
input fifo_data_valid,
output fifo_data_req,
output reg [SW-1:0] strb,
output [AW-1:0] addr,
output [DW-1:0] wdata,
output we,
output cmd_en,
input cmd_done,
input uart_rxreq,
output [7:0] uart_rxdata,
output uart_rxvld
);
localparam ST_IDLE = 5'd0;
localparam ST_W_ADDR_B0 = 5'd1;
localparam ST_W_ADDR_B1 = 5'd2;
localparam ST_W_ADDR_B2 = 5'd3;
localparam ST_W_ADDR_B3 = 5'd4;
localparam ST_W_DATA_B0 = 5'd5;
localparam ST_W_DATA_B1 = 5'd6;
localparam ST_W_DATA_B2 = 5'd7;
localparam ST_W_DATA_B3 = 5'd8;
localparam ST_W_STRB = 5'd9;
localparam ST_W_CMD = 5'd10;
localparam ST_WAIT = 5'd11;
localparam ST_R_ADDR_B0 = 5'd12;
localparam ST_R_ADDR_B1 = 5'd13;
localparam ST_R_ADDR_B2 = 5'd14;
localparam ST_R_ADDR_B3 = 5'd15;
localparam ST_R_CMD = 5'd16;
localparam ASC_w = 8'h77;
localparam ASC_r = 8'h72;
reg [4:0] crt_st;
reg [4:0] nxt_st;
reg [7:0] addr_b0;
reg [7:0] addr_b1;
reg [7:0] addr_b2;
reg [7:0] addr_b3;
reg [7:0] data_b0;
reg [7:0] data_b1;
reg [7:0] data_b2;
reg [7:0] data_b3;
assign addr = {addr_b3,addr_b2,addr_b1,addr_b0};
//assign strb = addrh[3:0];
assign wdata = {data_b3,data_b2,data_b1,data_b0};
assign we = crt_st == ST_W_CMD;
assign cmd_en = (crt_st == ST_W_CMD) | (crt_st == ST_R_CMD);
//wire in_st_idle = crt_st == ST_IDLE;
wire in_st_w_addr_b0 = crt_st == ST_W_ADDR_B0;
wire in_st_w_addr_b1 = crt_st == ST_W_ADDR_B1;
wire in_st_w_addr_b2 = crt_st == ST_W_ADDR_B2;
wire in_st_w_addr_b3 = crt_st == ST_W_ADDR_B3;
wire in_st_w_data_b0 = crt_st == ST_W_DATA_B0;
wire in_st_w_data_b1 = crt_st == ST_W_DATA_B1;
wire in_st_w_data_b2 = crt_st == ST_W_DATA_B2;
wire in_st_w_data_b3 = crt_st == ST_W_DATA_B3;
wire in_st_r_addr_b0 = crt_st == ST_R_ADDR_B0;
wire in_st_r_addr_b1 = crt_st == ST_R_ADDR_B1;
wire in_st_r_addr_b2 = crt_st == ST_R_ADDR_B2;
wire in_st_r_addr_b3 = crt_st == ST_R_ADDR_B3;
wire in_st_w_strb = crt_st == ST_W_STRB;
wire st_idle = nxt_st == ST_IDLE;
wire st_w_addr_b0 = nxt_st == ST_W_ADDR_B0;
wire st_w_addr_b1 = nxt_st == ST_W_ADDR_B1;
wire st_w_addr_b2 = nxt_st == ST_W_ADDR_B2;
wire st_w_addr_b3 = nxt_st == ST_W_ADDR_B3;
wire st_w_data_b0 = nxt_st == ST_W_DATA_B0;
wire st_w_data_b1 = nxt_st == ST_W_DATA_B1;
wire st_w_data_b2 = nxt_st == ST_W_DATA_B2;
wire st_w_data_b3 = nxt_st == ST_W_DATA_B3;
wire st_r_addr_b0 = nxt_st == ST_R_ADDR_B0;
wire st_r_addr_b1 = nxt_st == ST_R_ADDR_B1;
wire st_r_addr_b2 = nxt_st == ST_R_ADDR_B2;
wire st_r_addr_b3 = nxt_st == ST_R_ADDR_B3;
wire st_w_strb = nxt_st == ST_W_STRB;
//wire wait_fifo_data = in_st_idle | in_st_w_addr_b0 | in_st_w_addr_b1 | in_st_w_addr_b2 | in_st_w_addr_b3 | in_st_w_data_b0 | in_st_w_data_b1 |
// in_st_w_data_b2 | in_st_w_data_b3 | in_st_w_strb | in_st_r_addr_b0 | in_st_r_addr_b1 | in_st_r_addr_b2 | in_st_r_addr_b3;
wire wait_fifo_data = st_idle | st_w_addr_b0 | st_w_addr_b1 | st_w_addr_b2 | st_w_addr_b3 | st_w_data_b0 | st_w_data_b1 |
st_w_data_b2 | st_w_data_b3 | st_w_strb | st_r_addr_b0 | st_r_addr_b1 | st_r_addr_b2 | st_r_addr_b3;
localparam DATA_NUM = DW / 8 - 1;
localparam ADDR_NUM = AW / 8 - 1;
wire [7:0] apb_fifo_data;
wire apb_fifo_data_valid;
reg apb_fifo_data_req;
reg [15:0] cnt;
wire timeout;
assign fifo_data_req = apb_en ? apb_fifo_data_req : uart_rxreq;
assign uart_rxvld = (~apb_en) & fifo_data_valid;
assign uart_rxdata = {8{~apb_en}} & fifo_data;
assign apb_fifo_data_valid = apb_en & fifo_data_valid;
assign apb_fifo_data = {8{apb_en}} & fifo_data;
assign timeout = cnt == 100 * CLK_FREQ;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt <= 16'b0;
else if(crt_st != 5'd0)
begin
if(apb_fifo_data_valid)
cnt <= 16'b0;
else if(timeout)
cnt <= 16'b0;
else
cnt <= cnt + 16'b1;
end
else
cnt <= 16'b0;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
crt_st <= ST_IDLE;
else
crt_st <= nxt_st;
end
always @(*)
begin
nxt_st = crt_st;
case(crt_st)
ST_IDLE :
begin
if(apb_fifo_data_valid)
begin
if(apb_fifo_data == ASC_w)
nxt_st = ST_W_ADDR_B0;
else if(apb_fifo_data == ASC_r)
nxt_st = ST_R_ADDR_B0;
else
nxt_st = crt_st;
end
else
nxt_st = crt_st;
end
ST_W_ADDR_B0 :
begin
if(apb_fifo_data_valid)
begin
if(ADDR_NUM == 2'd0)
nxt_st = ST_W_DATA_B0;
else
nxt_st = ST_W_ADDR_B1;
end
else
begin
if(timeout)
nxt_st = ST_W_CMD;
else
nxt_st = ST_W_ADDR_B0;
end
end
ST_W_ADDR_B1 :
begin
if(apb_fifo_data_valid)
begin
if(ADDR_NUM == 2'd1)
nxt_st = ST_W_DATA_B0;
else
nxt_st = ST_W_ADDR_B2;
end
else
begin
if(timeout)
nxt_st = ST_W_CMD;
else
nxt_st = ST_W_ADDR_B1;
end
end
ST_W_ADDR_B2 :
begin
if(apb_fifo_data_valid)
begin
if(ADDR_NUM == 2'd2)
nxt_st = ST_W_DATA_B0;
else
nxt_st = ST_W_ADDR_B3;
end
else
begin
if(timeout)
nxt_st = ST_W_CMD;
else
nxt_st = ST_W_ADDR_B2;
end
end
ST_W_ADDR_B3 :
begin
if(apb_fifo_data_valid)
nxt_st = ST_W_DATA_B0;
else
begin
if(timeout)
nxt_st = ST_W_CMD;
else
nxt_st = ST_W_ADDR_B3;
end
end
ST_W_DATA_B0 :
begin
if(apb_fifo_data_valid)
begin
if(DATA_NUM == 2'd0)
begin
if(strb_en)
nxt_st = ST_W_STRB;
else
nxt_st = ST_W_CMD;
end
else
nxt_st = ST_W_DATA_B1;
end
else
begin
if(timeout)
nxt_st = ST_W_CMD;
else
nxt_st = ST_W_DATA_B0;
end
end
ST_W_DATA_B1 :
begin
if(apb_fifo_data_valid)
begin
if(DATA_NUM == 2'd1)
begin
if(strb_en)
nxt_st = ST_W_STRB;
else
nxt_st = ST_W_CMD;
end
else
nxt_st = ST_W_DATA_B2;
end
else
begin
if(timeout)
nxt_st = ST_W_CMD;
else
nxt_st = ST_W_DATA_B1;
end
end
ST_W_DATA_B2 :
begin
if(apb_fifo_data_valid)
begin
if(DATA_NUM == 2'd2)
begin
if(strb_en)
nxt_st = ST_W_STRB;
else
nxt_st = ST_W_CMD;
end
else
nxt_st = ST_W_DATA_B3;
end
else
begin
if(timeout)
nxt_st = ST_W_CMD;
else
nxt_st = ST_W_DATA_B2;
end
end
ST_W_DATA_B3 :
begin
if(apb_fifo_data_valid)
begin
if(strb_en)
nxt_st = ST_W_STRB;
else
nxt_st = ST_W_CMD;
end
else
begin
if(timeout)
nxt_st = ST_W_CMD;
else
nxt_st = ST_W_DATA_B3;
end
end
ST_W_STRB :
begin
if(apb_fifo_data_valid)
nxt_st = ST_W_CMD;
else
begin
if(timeout)
nxt_st = ST_W_CMD;
else
nxt_st = ST_W_STRB;
end
end
ST_W_CMD :
begin
nxt_st = ST_WAIT;
end
ST_WAIT :
begin
if(cmd_done)
nxt_st = ST_IDLE;
else
nxt_st = ST_WAIT;
end
ST_R_ADDR_B0 :
begin
if(apb_fifo_data_valid)
begin
if(ADDR_NUM == 2'd0)
nxt_st = ST_R_CMD;
else
nxt_st = ST_R_ADDR_B1;
end
else
begin
if(timeout)
nxt_st = ST_R_CMD;
else
nxt_st = ST_R_ADDR_B0;
end
end
ST_R_ADDR_B1 :
begin
if(apb_fifo_data_valid)
begin
if(ADDR_NUM == 2'd1)
nxt_st = ST_R_CMD;
else
nxt_st = ST_R_ADDR_B2;
end
else
begin
if(timeout)
nxt_st = ST_R_CMD;
else
nxt_st = ST_R_ADDR_B1;
end
end
ST_R_ADDR_B2 :
begin
if(apb_fifo_data_valid)
begin
if(ADDR_NUM == 2'd2)
nxt_st = ST_R_CMD;
else
nxt_st = ST_R_ADDR_B3;
end
else
begin
if(timeout)
nxt_st = ST_R_CMD;
else
nxt_st = ST_R_ADDR_B2;
end
end
ST_R_ADDR_B3 :
begin
if(apb_fifo_data_valid)
nxt_st = ST_R_CMD;
else
begin
if(timeout)
nxt_st = ST_R_CMD;
else
nxt_st = ST_R_ADDR_B3;
end
end
ST_R_CMD :
begin
nxt_st = ST_WAIT;
end
default :
begin
nxt_st = ST_IDLE;
end
endcase
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
addr_b0 <= 8'b0;
else if((in_st_w_addr_b0 || in_st_r_addr_b0) && apb_fifo_data_valid)
addr_b0 <= apb_fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
addr_b1 <= 8'b0;
else if((in_st_w_addr_b1 || in_st_r_addr_b1) && apb_fifo_data_valid)
addr_b1 <= apb_fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
addr_b2 <= 8'b0;
else if((in_st_w_addr_b2 || in_st_r_addr_b2) && apb_fifo_data_valid)
addr_b2 <= apb_fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
addr_b3 <= 8'b0;
else if((in_st_w_addr_b3 || in_st_r_addr_b3) && apb_fifo_data_valid)
addr_b3 <= apb_fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
data_b0 <= 8'b0;
else if(in_st_w_data_b0 && apb_fifo_data_valid)
data_b0 <= apb_fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
data_b1 <= 8'b0;
else if(in_st_w_data_b1 && apb_fifo_data_valid)
data_b1 <= apb_fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
data_b2 <= 8'b0;
else if(in_st_w_data_b2 && apb_fifo_data_valid)
data_b2 <= apb_fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
data_b3 <= 8'b0;
else if(in_st_w_data_b3 && apb_fifo_data_valid)
data_b3 <= apb_fifo_data;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
strb <= 'b0;
else if(in_st_w_strb && apb_fifo_data_valid)
strb <= apb_fifo_data[SW-1:0];
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
apb_fifo_data_req <= 1'b0;
else if(wait_fifo_data)
apb_fifo_data_req <= 1'b1;
else
apb_fifo_data_req <= 1'b0;
end
endmodule //pgr_cmd_parser |
module pgr_uart_rx_32bit(
input clk,
input rst_n,
input clk_en,
output wire[7:0] rx_fifo_wr_data,
input rx_fifo_wr_data_valid,
output wire rx_fifo_wr_data_req,
input [1:0] uart_word_len,
input uart_parity_en,
input uart_parity_type,
input uart_mode, //0:LSBF 1:MSBF
output reg rx_chk_err,
output reg rx_overrun,
input rxd_in
);
reg [1:0] rxd_d;
reg [2:0] rxd_tmp;
reg rxd_r1;
reg rxd_r2;
reg rxd;
wire rxd_neg;
reg [3:0] rx_cnt;
reg [2:0] cnt;
reg [8:0] rx_data;
reg [3:0] rx_len_left;
wire [7:0] rx_word_temp;
wire [7:0] rx_word_revise;
wire rx_over;
wire rx_chk;
wire rx_err;
reg rx_req;
reg [2:0] cnt_judge;
wire cnt_down;
reg in_cyc;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt_judge <= 3'b0;
else if(clk_en)
begin
if(cnt_down)
cnt_judge <= 3'b0;
else
begin
if(in_cyc)
cnt_judge <= cnt_judge + rxd_r2;
else
cnt_judge <= 3'b0;
end
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rxd_d <= 2'b11;
else
rxd_d <= {rxd_d[0],rxd_in};
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rxd_tmp <= 3'b111;
else if(clk_en)
rxd_tmp <= {rxd_tmp[1:0],rxd_d[1]};
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rxd_r1 <= 1'b1;
else if(clk_en)
begin
if(rxd_tmp == 3'b111)
rxd_r1 <= 1'b1;
else if(rxd_tmp == 3'b000)
rxd_r1 <= 1'b0;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rxd_r2 <= 1'b1;
else if(clk_en)
rxd_r2 <= rxd_r1;
end
//assign rxd = rxd_r2;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rxd <= 1'b0;
else if(cnt_down)
begin
if(cnt_judge < 3'd3)
rxd <= 1'b0;
else
rxd <= 1'b1;
end
end
assign rxd_neg = rxd_r2 & (~rxd_r1);
reg rx_sample;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
in_cyc <= 1'b0;
else if(clk_en)
begin
if(rxd_neg)
in_cyc <= 1'b1;
else if(rx_over && rx_sample)
in_cyc <= 1'b0;
end
end
assign rx_over = rx_cnt == rx_len_left;
assign cnt_down = cnt == 3'd5;
//assign rx_sample = cnt == 3'd2;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt <= 3'b0;
else if(clk_en)
begin
if(cnt_down)
cnt <= 3'b0;
else if(~in_cyc)
cnt <= 3'b0;
else
cnt <= cnt + 3'b1;
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rx_sample <= 1'b0;
else
begin
if(cnt_down)
rx_sample <= 1'b1;
else
rx_sample <=1'b0;
end
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
rx_data <= 9'b0;
rx_cnt <= 4'd9;
end
else if(clk_en)
begin
if(~in_cyc)
begin
rx_data <= 9'b0;
rx_cnt <= 4'd9;
end
else if(rx_sample)
begin
rx_data <= {rxd,rx_data[8:1]};
rx_cnt <= rx_cnt + 4'hf; // rx_cnt = rx_cnt - 1;
end
end
end
always @(*)
begin
case({uart_word_len,uart_parity_en})
3'b000 : rx_len_left = 3'd4;
3'b001 : rx_len_left = 3'd3;
3'b010 : rx_len_left = 3'd3;
3'b011 : rx_len_left = 3'd2;
3'b100 : rx_len_left = 3'd2;
3'b101 : rx_len_left = 3'd1;
3'b110 : rx_len_left = 3'd1;
3'b111 : rx_len_left = 3'd0;
endcase
end
assign rx_word_temp = uart_parity_en ? rx_data[7:0] : rx_data[8:1];
genvar i;
generate
for(i = 0; i <= 7; i = i + 1)
begin:REV_TX
assign rx_word_revise[i] = rx_word_temp[7 - i];
end
endgenerate //MSBF 2 LSBF
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rx_req <= 1'b0;
else if(clk_en)
begin
if(rx_sample && rx_over)
rx_req <= 1'b1;
end
else
rx_req <= 1'b0;
end
assign rx_fifo_wr_data_req = rx_req && rx_fifo_wr_data_valid && (~rx_err);
assign rx_fifo_wr_data = uart_mode ? rx_word_revise : (rx_word_temp >> (rx_len_left - {2'b00,(~uart_parity_en)}));
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rx_overrun <= 1'b0;
else if(rx_req && (~rx_fifo_wr_data_valid))
rx_overrun <= 1'b1;
else
rx_overrun <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
rx_chk_err <= 1'b0;
else if(rx_req)
rx_chk_err <= rx_err;
end
assign rx_err = uart_parity_en ? (rx_chk ^ uart_parity_type) : 1'b0;
assign rx_chk = ^rx_data;
endmodule //pgr_uart_rx |
module rstn_sync_32bit(
input clk,
input rst_n,
output wire sync_rst_n
);
reg rst_n_ff1;
reg rst_n_ff2;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
rst_n_ff1 <= 1'b0;
rst_n_ff2 <= 1'b0;
end
else
begin
rst_n_ff1 <= 1;
rst_n_ff2 <= rst_n_ff1;
end
end
assign sync_rst_n = rst_n_ff2;
endmodule |
module pgr_apb_mif_32bit
#(
parameter CLK_FREQ = 8'd50,
parameter AW = 8'd16,
parameter DW = 8'd32,
parameter SW = 8'd4
)(
input clk,
input rst_n,
input [SW-1:0] strb,
input [AW-1:0] addr,
input [DW-1:0] wdata,
input we,
input cmd_en,
output cmd_done,
output [7:0] fifo_data,
input fifo_data_valid,
output fifo_data_req,
output reg p_sel,
output reg [SW-1:0] p_strb,
output reg [AW-1:0] p_addr,
output reg [DW-1:0] p_wdata,
output reg p_ce,
output reg p_we,
input p_rdy,
input [DW-1:0] p_rdata,
input apb_en,
output uart_txvld,
input uart_txreq,
input [7:0] uart_txdata
);
reg [7:0] cnt;
reg time_out;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
time_out <= 1'b0;
else if(cnt == 8'hff)
time_out <= 1'b1;
else
time_out <= 1'b0;
end
//assign time_out = cnt == 8'hff;
reg [7:0] apb_fifo_data;
wire apb_fifo_data_valid;
reg apb_fifo_data_req;
assign fifo_data = apb_en ? apb_fifo_data : uart_txdata;
assign apb_fifo_data_valid = apb_en & fifo_data_valid;
assign uart_txvld = (~apb_en) & fifo_data_valid;
assign fifo_data_req = apb_en ? apb_fifo_data_req : uart_txreq;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt <= 8'b0;
else if(~p_ce)
cnt <= 8'b0;
else
cnt <= cnt + 8'b1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
p_addr <= 'b0;
else if(cmd_en)
p_addr <= addr;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
p_strb <= 'b0;
else if(cmd_en)
p_strb <= strb;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
p_wdata <= 'b0;
else if(cmd_en)
p_wdata <= wdata;
end
//modify for gen psel signal by wenbin at @2019.8.23
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
p_sel <= 1'b0;
else if(p_rdy)
p_sel <= 1'b0;
else if(time_out)
p_sel <= 1'b0;
else if(cmd_en)
p_sel <= 1'b1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
p_ce <= 1'b0;
else if(p_rdy)
p_ce <= 1'b0;
else if(time_out)
p_ce <= 1'b0;
else if(p_sel)
p_ce <= 1'b1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
p_we <= 1'b0;
else if(p_rdy)
p_we <= 1'b0;
else if(time_out)
p_we <= 1'b0;
else if(cmd_en)
p_we <= we;
end
assign cmd_done = p_ce & (p_rdy | time_out);
reg [DW-1:0] rdata;
reg rdata_valid;
//always@(posedge clk or negedge rst_n)
//begin
// if(~rst_n)
// rdata <= 'b0;
// else if(cmd_done)
// rdata <= p_rdata;
//end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rdata_valid <= 1'b0;
else if(cmd_done && (~p_we))
rdata_valid <= 1'b1;
else
rdata_valid <=1'b0;
end
localparam TX_INTERVAL = 6 * (((CLK_FREQ * 1000000 + 3 * 115200) / (6 * 115200)) - 2);
localparam BYTE_NUM = DW / 8;
//assign fifo_data = time_out ? 32'b0 : p_rdata;
//assign fifo_data_req = cmd_done & fifo_data_valid & ~p_we;
assign trans_start = rdata_valid & apb_fifo_data_valid;
// get APB read data,and write it into tx_fifo
reg clk_cnt_start1;
reg [15:0] clk_cnt;
reg [1:0] trans_cnt;
reg tx_enable;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
tx_enable <= 1'b0;
else if(clk_cnt == (TX_INTERVAL-1))
tx_enable <= 1'b1;
else
tx_enable <= 1'b0;
end
//wire tx_enable = clk_cnt == TX_INTERVAL;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n) begin
apb_fifo_data_req <= 1'b0;
apb_fifo_data <= 8'b0;
rdata <= 'b0;
end
else if(cmd_done & (~p_we))
rdata <= p_rdata;
else if(trans_start) begin
apb_fifo_data <= rdata[7:0];
apb_fifo_data_req <= 1'b1;
rdata <= (rdata >> 8);
end
else if(tx_enable && (trans_cnt == 2'd1) && (BYTE_NUM > 1)) begin
apb_fifo_data <= rdata[7:0];
apb_fifo_data_req <= 1'b1;
rdata <= (rdata >> 8);
end
else if(tx_enable && (trans_cnt == 2'd2) && (BYTE_NUM > 2)) begin
apb_fifo_data <= rdata[7:0];
apb_fifo_data_req <= 1'b1;
rdata <= (rdata >> 8);
end
else if(tx_enable && (trans_cnt == 2'd3) && (BYTE_NUM > 3)) begin
apb_fifo_data <= rdata[7:0];
apb_fifo_data_req <= 1'b1;
rdata <= (rdata >> 8);
end
else
apb_fifo_data_req <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
clk_cnt_start1 <= 1'b0;
else if(trans_start)
clk_cnt_start1 <= 1'b1;
else if(trans_cnt == (BYTE_NUM-1))
clk_cnt_start1 <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n) begin
clk_cnt <= 16'b0;
end
else if(trans_start) begin
clk_cnt <= 16'b0;
end
else if(tx_enable) begin
clk_cnt <= 16'b0;
end
else if(clk_cnt_start1) begin
clk_cnt <= clk_cnt + 16'b1;
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
trans_cnt <= 2'd0;
end
else
begin
if(clk_cnt == (TX_INTERVAL-1))
trans_cnt <= trans_cnt + 2'd1;
else if(trans_cnt == (BYTE_NUM-1))
trans_cnt <= 2'b0;
end
end
endmodule //pgr_apb_mif |
module pgr_uart2apb_top_32bit
#(
parameter CLK_FREQ = 8'd50 , //frequency, for 50MHz
parameter FIFO_D = 8'd16 , //fifo depth
parameter WORD_LEN = 2'b11 , //the bit width of valid data(00:5 01:6 10:7 11:8)
parameter PARITY_EN = 1'b0 , //0:no parity bit 1:1 parity bit
parameter PARITY_TYPE = 1'b0 , //the type of parity(0:even 1:odd)
parameter STOP_LEN = 1'b0 , //1:2 stop bit 0:1 stop bit
parameter MODE = 1'b0 , //0:LSBF 1:MSBF
parameter AW = 8'd16 , //the bit width of addr
parameter DW = 8'd32 , //the bit width of data
parameter SW = 8'd4 //the bit width of strb
)
(
input i_clk,
input i_rst_n,
//apb enable
output o_p_sel,
output [SW-1:0] o_p_strb,
output [AW-1:0] o_p_addr,
output [DW-1:0] o_p_wdata,
output o_p_enable,
output o_p_we,
input i_p_ready,
input [DW-1:0] i_p_rdata,
input i_apb_en,
input i_strb_en,
//uart
output o_uart_txd,
input i_uart_rxd,
//just for debug
output rx_overrun,
output rx_chk_err,
//apb bypass
output o_uart_txvld,
input i_uart_txreq,
input [7:0] i_uart_txdata,
input i_uart_rxreq,
output [7:0] o_uart_rxdata,
output o_uart_rxvld
);
wire [7:0] tx_fifo_wr_data;
wire tx_fifo_wr_data_valid;
wire tx_fifo_wr_data_req;
wire [7:0] rx_fifo_rd_data;
wire rx_fifo_rd_data_valid;
wire rx_fifo_rd_data_req;
wire sync_rst_n;
pgr_uart_top_32bit
#(
.CLK_FREQ (CLK_FREQ ),
.FIFO_D (FIFO_D ),
.WORD_LEN (WORD_LEN ),
.PARITY_EN (PARITY_EN ),
.PARITY_TYPE (PARITY_TYPE ),
.STOP_LEN (STOP_LEN ),
.MODE (MODE )
)
u_uart_top(
.clk (i_clk ),
.rst_n (sync_rst_n ),
.tx_fifo_wr_data (tx_fifo_wr_data ),
.tx_fifo_wr_data_valid (tx_fifo_wr_data_valid ),
.tx_fifo_wr_data_req (tx_fifo_wr_data_req ),
.rx_fifo_rd_data (rx_fifo_rd_data ),
.rx_fifo_rd_data_valid (rx_fifo_rd_data_valid ),
.rx_fifo_rd_data_req (rx_fifo_rd_data_req ),
.txd (o_uart_txd ),
.rxd (i_uart_rxd ),
.rx_overrun (rx_overrun ),
.rx_chk_err (rx_chk_err )
);
pgr_apb_ctr_32bit #(
.CLK_FREQ ( CLK_FREQ ),
.AW ( AW ),
.DW ( DW ),
.SW ( SW )
) u_apb_ctr(
.clk (i_clk ),
.rst_n (sync_rst_n ),
.tx_fifo_wr_data (tx_fifo_wr_data ),
.tx_fifo_wr_data_valid (tx_fifo_wr_data_valid ),
.tx_fifo_wr_data_req (tx_fifo_wr_data_req ),
.rx_fifo_rd_data (rx_fifo_rd_data ),
.rx_fifo_rd_data_valid (rx_fifo_rd_data_valid ),
.rx_fifo_rd_data_req (rx_fifo_rd_data_req ),
.p_sel (o_p_sel ),
.p_strb (o_p_strb ),
.p_addr (o_p_addr ),
.p_wdata (o_p_wdata ),
.p_ce (o_p_enable ),
.p_we (o_p_we ),
.p_rdy (i_p_ready ),
.p_rdata (i_p_rdata ),
.apb_en (i_apb_en ),
.strb_en (i_strb_en ),
.uart_rxvld (o_uart_rxvld ),
.uart_rxdata (o_uart_rxdata ),
.uart_rxreq (i_uart_rxreq ),
.uart_txvld (o_uart_txvld ),
.uart_txdata (i_uart_txdata ),
.uart_txreq (i_uart_txreq )
);
rstn_sync_32bit u_rstn_sync(
.clk (i_clk ),
.rst_n (i_rst_n ),
.sync_rst_n (sync_rst_n )
);
endmodule //pgr_uart2apb_top |
module pgr_fifo_top_32bit
#(
parameter D = 16'd1024
)
(
input clk,
input rst_n,
input [7:0] wr_data,
input wr_req,
output wr_ready,
input rd_req,
output [7:0] rd_data,
output rd_valid
);
pgr_prefetch_fifo
#(
.D (D ), //should be 2^N
.W (8 ),
.TYPE ("Distributed" ) // "Distributed" or "DRM"
)
u_prefetch_fifo(
.clk (clk ),
.rst_n (rst_n ),
.data_in_valid (wr_req ),
.data_in (wr_data ),
.data_in_ready (wr_ready ),
.data_out_ready (rd_req ),
.data_out (rd_data ),
.data_out_valid (rd_valid )
);
endmodule //fifo |
module pgr_uart_top_32bit
#(
parameter CLK_FREQ = 8'd50 ,
parameter FIFO_D = 16'd1024 ,
parameter WORD_LEN = 2'b11 ,
parameter PARITY_EN = 1'b0 ,
parameter PARITY_TYPE = 1'b0 ,
parameter STOP_LEN = 1'b0 ,
parameter MODE = 1'b0
)
(
input clk,
input rst_n,
input [7:0] tx_fifo_wr_data,
output tx_fifo_wr_data_valid,
input tx_fifo_wr_data_req,
output [7:0] rx_fifo_rd_data,
output rx_fifo_rd_data_valid,
input rx_fifo_rd_data_req,
output txd,
input rxd,
output rx_chk_err,
output rx_overrun
);
wire clk_en;
wire tx_fifo_rd_data_req;
wire [7:0] tx_fifo_rd_data;
wire tx_fifo_rd_data_valid;
wire rx_fifo_wr_data_req;
wire [7:0] rx_fifo_wr_data;
wire rx_fifo_wr_data_valid;
pgr_clk_gen_32bit
#(
.CLK_FREQ (CLK_FREQ )
)
u_pgr_clk_gen(
.clk (clk ),
.rst_n (rst_n ),
.clk_en (clk_en )
);
pgr_fifo_top_32bit
#(
.D (FIFO_D )
)
u_tx_fifo(
.clk (clk ),
.rst_n (rst_n ),
.wr_data (tx_fifo_wr_data ),
.wr_req (tx_fifo_wr_data_req ),
.wr_ready (tx_fifo_wr_data_valid ),
.rd_req (tx_fifo_rd_data_req ),
.rd_data (tx_fifo_rd_data ),
.rd_valid (tx_fifo_rd_data_valid )
);
pgr_fifo_top_32bit
#(
.D (FIFO_D )
)
u_rx_fifo(
.clk (clk ),
.rst_n (rst_n ),
.wr_data (rx_fifo_wr_data ),
.wr_req (rx_fifo_wr_data_req ),
.wr_ready (rx_fifo_wr_data_valid ),
.rd_req (rx_fifo_rd_data_req ),
.rd_data (rx_fifo_rd_data ),
.rd_valid (rx_fifo_rd_data_valid )
);
pgr_uart_tx_32bit u_pgr_uart_tx(
.clk (clk ),
.clk_en (clk_en ),
.rst_n (rst_n ),
.tx_fifo_rd_data (tx_fifo_rd_data ),
.tx_fifo_rd_data_valid (tx_fifo_rd_data_valid ),
.tx_fifo_rd_data_req (tx_fifo_rd_data_req ),
.uart_word_len (WORD_LEN ),
.uart_parity_en (PARITY_EN ),
.uart_parity_type (PARITY_TYPE ),
.uart_stop_len (STOP_LEN ),
.uart_mode (MODE ),
.txd (txd )
);
pgr_uart_rx_32bit u_pgr_uart_rx(
.clk (clk ),
.rst_n (rst_n ),
.clk_en (clk_en ),
.rx_fifo_wr_data (rx_fifo_wr_data ),
.rx_fifo_wr_data_valid (rx_fifo_wr_data_valid ),
.rx_fifo_wr_data_req (rx_fifo_wr_data_req ),
.uart_word_len (WORD_LEN ),
.uart_parity_en (PARITY_EN ),
.uart_parity_type (PARITY_TYPE ),
.uart_mode (MODE ),
.rx_overrun (rx_overrun ),
.rx_chk_err (rx_chk_err ),
.rxd_in (rxd )
);
endmodule //pgr_uart_top |
module pgr_uart_tx_32bit(
input clk,
input clk_en,
input rst_n,
input [7:0] tx_fifo_rd_data,
input tx_fifo_rd_data_valid, // Transfer the data until tx_fifo is empty
output wire tx_fifo_rd_data_req,
input [1:0] uart_word_len,
input uart_parity_en,
input uart_parity_type,
input uart_stop_len,
input uart_mode, //0:LSBF 1:MSBF
output wire txd
);
reg [2:0] cnt;
wire cnt_down;
reg clken; //5 div from clk_en
//reg in_cyc;
//reg tx_begin;
reg tx_req;
wire tx_over;
wire [7:0] tx_data;
wire [7:0] tx_data_temp;
wire [7:0] tx_data_revise;
reg [11:0] tx_frame;
reg [3:0] tx_len;
reg [3:0] tx_cnt;
reg [11:0] shift_reg;
reg [7:0] tx_data_purn;
assign cnt_down = cnt == 3'd5; // oversample, 6 times
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
clken <= 1'b0;
else
clken <= cnt_down && clk_en;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt <= 3'b0;
else if(clk_en)
begin
if(cnt_down)
cnt <= 3'b0;
else
cnt <= cnt + 3'b1;
end
end
//
//always @(posedge clk or negedge rst_n)
//begin
// if(~rst_n)
// begin
// tx_data <= 8'hff;
// tx_begin <= 1'b0;
// end
// else if(clken)
// begin
// if(~in_cyc && tx_fifo_rd_data_valid && ~tx_begin)
// begin
// tx_begin <= 1'b1;
// tx_data <= tx_fifo_rd_data;
// end
// else
// tx_begin <= 1'b0;
// end
//end
assign tx_data = tx_fifo_rd_data;
assign tx_fifo_rd_data_req = tx_req & clken;
//always @(posedge clk or negedge rst_n)
//begin
// if(~rst_n)
// in_cyc <= 1'b0;
// else if(clken)
// begin
// if(tx_begin)
// in_cyc <= 1'b1;
// else if(tx_over)
// in_cyc <= 1'b0;
// end
//end
genvar i;
generate
for(i = 0; i <= 7; i = i + 1)
begin:REV_TX
assign tx_data_revise[i] = tx_data[7 - i];
end
endgenerate //MSBF 2 LSBF
assign tx_data_temp = uart_mode ? (tx_data_revise >> (3 - uart_word_len)) : tx_data;
assign tx_parity = uart_parity_en ? (uart_parity_type ? (~(^tx_data_purn)) : (^tx_data_purn)) : 1'b1;
always @(*)
begin
case({uart_word_len,uart_parity_en,uart_stop_len})
4'b0000 : tx_len = 4'd6;
4'b0001 : tx_len = 4'd7;
4'b0010 : tx_len = 4'd7;
4'b0011 : tx_len = 4'd8;
4'b0100 : tx_len = 4'd7;
4'b0101 : tx_len = 4'd8;
4'b0110 : tx_len = 4'd8;
4'b0111 : tx_len = 4'd9;
4'b1000 : tx_len = 4'd8;
4'b1001 : tx_len = 4'd9;
4'b1010 : tx_len = 4'd9;
4'b1011 : tx_len = 4'd10;
4'b1100 : tx_len = 4'd9;
4'b1101 : tx_len = 4'd10;
4'b1110 : tx_len = 4'd10;
4'b1111 : tx_len = 4'd11;
endcase
end
always @(*)
begin
case(uart_word_len)
2'b00 : tx_data_purn = {3'b0,tx_data_temp[4:0]};
2'b01 : tx_data_purn = {2'b0,tx_data_temp[5:0]};
2'b10 : tx_data_purn = {1'b0,tx_data_temp[6:0]};
2'b11 : tx_data_purn = {tx_data_temp};
endcase
end
always @(*)
begin
case(uart_word_len)
2'b00 : tx_frame = {6'h3f,tx_parity,tx_data_temp[4:0],1'b0};
2'b01 : tx_frame = {5'h1f,tx_parity,tx_data_temp[5:0],1'b0};
2'b10 : tx_frame = {4'hf,tx_parity,tx_data_temp[6:0],1'b0};
2'b11 : tx_frame = {2'h3,tx_parity,tx_data_temp,1'b0};
endcase
end
reg valid_temp;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
valid_temp <= 1'b0;
else if(tx_fifo_rd_data_valid)
valid_temp <= 1'b1;
else if(tx_over && clken)
valid_temp <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
shift_reg <= 12'hfff;
tx_cnt <= 4'b0;
tx_req <= 1'b0;
end
else if(clken)
begin
if(tx_over)
begin
shift_reg <= valid_temp ? tx_frame : 12'hfff;
tx_cnt <= 4'b0;
tx_req <= 1;
end
else //if(in_cyc)
begin
shift_reg <= {1'b1,shift_reg[11:1]};
tx_cnt <= tx_cnt + 4'b1;
tx_req <= 1'b0;
end
end
end
assign txd = shift_reg[0];
assign tx_over = tx_cnt == tx_len;
endmodule //pgr_uart_tx |
module pgr_apb_ctr_32bit #(
parameter CLK_FREQ = 16'd50,
parameter AW = 16'd16,
parameter DW = 16'd32,
parameter SW = 16'd4
)(
input clk,
input rst_n,
output [7:0] tx_fifo_wr_data,
input tx_fifo_wr_data_valid,
output tx_fifo_wr_data_req,
input [7:0] rx_fifo_rd_data,
input rx_fifo_rd_data_valid,
output rx_fifo_rd_data_req,
output p_sel,
output [SW-1:0] p_strb,
output [AW-1:0] p_addr,
output [DW-1:0] p_wdata,
output p_ce,
output p_we,
input p_rdy,
input [DW-1:0] p_rdata,
output uart_txvld,
input uart_txreq,
input [7:0] uart_txdata,
input uart_rxreq,
output [7:0] uart_rxdata,
output uart_rxvld,
input apb_en,
input strb_en
);
wire [AW-1:0] addr;
wire [SW-1:0] strb;
wire [DW-1:0] wdata;
wire we;
wire cmd_en;
wire cmd_done;
pgr_apb_mif_32bit #(
.CLK_FREQ ( CLK_FREQ ),
.AW ( AW ),
.DW ( DW ),
.SW ( SW )
) u_apb_mif(
.clk (clk ),
.rst_n (rst_n ),
.strb (strb ),
.addr (addr ),
.wdata (wdata ),
.we (we ),
.cmd_en (cmd_en ),
.cmd_done (cmd_done ),
.fifo_data (tx_fifo_wr_data ),
.fifo_data_valid (tx_fifo_wr_data_valid ),
.fifo_data_req (tx_fifo_wr_data_req ),
.apb_en (apb_en ),
.p_sel (p_sel ),
.p_strb (p_strb ),
.p_addr (p_addr ),
.p_wdata (p_wdata ),
.p_ce (p_ce ),
.p_we (p_we ),
.p_rdy (p_rdy ),
.p_rdata (p_rdata ),
.uart_txvld (uart_txvld ),
.uart_txreq (uart_txreq ),
.uart_txdata (uart_txdata )
);
pgr_cmd_parser_32bit #(
.AW ( AW ),
.DW ( DW ),
.SW ( SW ),
.CLK_FREQ (CLK_FREQ )
)u_cmd_parser(
.clk (clk ),
.rst_n (rst_n ),
.fifo_data (rx_fifo_rd_data ),
.fifo_data_valid (rx_fifo_rd_data_valid ),
.fifo_data_req (rx_fifo_rd_data_req ),
.strb (strb ),
.addr (addr ),
.wdata (wdata ),
.we (we ),
.cmd_en (cmd_en ),
.cmd_done (cmd_done ),
.uart_rxvld (uart_rxvld ),
.uart_rxreq (uart_rxreq ),
.uart_rxdata (uart_rxdata ),
.apb_en (apb_en ),
.strb_en (strb_en )
);
endmodule //pgr_apb_ctr |
module pgr_clk_gen_32bit
#(
parameter CLK_FREQ = 8'd50
)
(
input clk,
input rst_n,
output reg clk_en // divided from baud
);
reg [15:0] cnt;
localparam CLK_DIV = (CLK_FREQ * 1000000 + 3 * 115200) / (6 * 115200) - 2;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt <= 16'b0;
else if(clk_en)
cnt <= 16'b0;
else
cnt <= cnt + 16'b1;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
clk_en <= 1'b0;
else
clk_en <= (cnt == CLK_DIV);
end
endmodule //pgr_clk_gen |
module ipsl_pcie_dma_mwr_tx_ctrl #(
parameter DEVICE_TYPE = 3'd0 //3'd0:EP,3'd1:Legacy EP,3'd4:RC
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
input [7:0] i_cfg_pbus_num ,
input [4:0] i_cfg_pbus_dev_num ,
input [2:0] i_cfg_max_payload_size ,
//**********************************************************************
//from dma controller
input i_user_define_data_flag ,
input i_mwr32_req ,
output reg o_mwr32_req_ack ,
input i_mwr64_req ,
output reg o_mwr64_req_ack ,
input [9:0] i_req_length ,
input [63:0] i_req_addr ,
input [31:0] i_req_data ,
//**********************************************************************
//ram interface
output reg o_rd_en ,
output wire [9:0] o_rd_length ,
input i_gen_tlp_start ,
input [127:0] i_rd_data ,
input i_last_data ,
//axis_slave interface
input i_axis_slave2_trdy ,
output reg o_axis_slave2_tvld ,
output reg [127:0] o_axis_slave2_tdata ,
output reg o_axis_slave2_tlast ,
output reg o_axis_slave2_tuser ,
output reg o_mwr_tx_busy ,
output wire o_mwr_tx_hold ,
output wire o_mwr_tlp_tx ,
//debug
input i_tx_restart
//output wire [13:0] o_dbg_bus
);
localparam IDLE = 2'd0;
localparam HEADER_TX = 2'd1;
localparam DATA_TX = 2'd2;
reg [63:0] mwr_addr;
reg [31:0] mwr_data;
wire [9:0] mwr_length_tx;
wire mwr_req_start;
reg mwr_req_start_ff;
reg [9:0] mwr_length;
reg mwr32_req_tx;
reg mwr64_req_tx;
reg [1:0] state;
reg [1:0] next_state;
wire mwr_req_rcv;
//tlp_tx
wire [15:0] requester_id;
reg [7:0] tag;
wire [2:0] fmt;
wire [4:0] tlp_type;
wire [2:0] tc;
wire [2:0] attr;
wire th;
wire td;
wire ep;
wire [1:0] at;
wire [31:0] mwr_header_tx;
wire [3:0] first_dwbe;
wire [3:0] last_dwbe;
wire [7:0] dwbe;
wire data_vlad;
wire mwr_req_ack;
wire tx_done;
wire [9:0] max_payload_size;
//when i_axis_slave2_trdy down,hold all tx logic
assign o_mwr_tx_hold = ~i_axis_slave2_trdy && o_axis_slave2_tvld;
assign mwr_req_rcv = i_mwr32_req || i_mwr64_req;
assign mwr_req_ack = o_mwr32_req_ack || o_mwr64_req_ack;
assign data_vlad = i_gen_tlp_start;
assign tx_done = o_axis_slave2_tlast && i_axis_slave2_trdy && o_axis_slave2_tvld;
assign mwr_req_start = mwr_req_rcv && mwr_req_ack;
assign max_payload_size = (i_cfg_max_payload_size == 3'd0) ? 10'h20 :
(i_cfg_max_payload_size == 3'd1) ? 10'h40 :
(i_cfg_max_payload_size == 3'd2) ? 10'h80 :
(i_cfg_max_payload_size == 3'd3) ? 10'h100 : 10'd20;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr_req_start_ff <= 1'b0;
else
mwr_req_start_ff <= mwr_req_start;
end
//get tlp information
//length > 128byte
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr_length <= 10'd0;
else if(mwr_req_start && !o_mwr_tx_busy)
mwr_length <= i_req_length;
else if(mwr_length > max_payload_size && state == HEADER_TX && !o_mwr_tx_hold) //header tx
mwr_length <= mwr_length - max_payload_size;
else if(mwr_length <= max_payload_size && state == HEADER_TX && !o_mwr_tx_hold)
mwr_length <= 10'd0;
end
//the true length to be transmitted
assign mwr_length_tx = (mwr_length > max_payload_size) ? max_payload_size : mwr_length ;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr_addr <= 64'd0;
else if(mwr_req_start && !o_mwr_tx_busy)
mwr_addr <= i_req_addr;
else if(|mwr_length && tx_done)
mwr_addr <= mwr_addr + {52'b0,max_payload_size,2'b0};
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr_data <= 32'd0;
else if(mwr_req_start && !o_mwr_tx_busy)
mwr_data <= i_req_data;
end
//rd ram ctrl
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_rd_en <= 1'b0;
else if(tx_done)
o_rd_en <= 1'b0;
else if(|mwr_length && ~i_user_define_data_flag)
o_rd_en <= 1'b1;
end
assign o_rd_length = mwr_length_tx;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr32_req_tx <= 1'b0;
else if(tx_done && ~(|mwr_length))
mwr32_req_tx <= 1'b0;
else if(mwr_req_start)
mwr32_req_tx <= i_mwr32_req;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr64_req_tx <= 1'b0;
else if(tx_done && ~(|mwr_length))
mwr64_req_tx <= 1'b0;
else if(mwr_req_start)
mwr64_req_tx <= i_mwr64_req;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tag <= 8'b0;
else if(tx_done)
tag <= tag + 8'b1;
end
//tlp header
assign requester_id = {i_cfg_pbus_num,i_cfg_pbus_dev_num,3'b0};
assign {fmt,tlp_type} = mwr32_req_tx ? 8'h40
: mwr64_req_tx ? 8'h60 : 8'h40;
assign tc = 3'b0;
assign attr = 3'b0;
assign {th,td,ep,at} = 5'b0;
assign mwr_header_tx = {fmt,tlp_type,1'b0,tc,1'b0,attr[2],1'b0,th,td,ep,attr[1:0],at,mwr_length_tx};
assign first_dwbe = 4'hf;
assign last_dwbe = mwr_length_tx == 10'h1 ? 4'h0 : 4'hf;
assign dwbe = {last_dwbe,first_dwbe};
//mwr_tx
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
state <= IDLE;
else
state <= next_state;
end
always @(*)
begin
case(state)
IDLE:
begin
if(((mwr_req_start_ff && i_user_define_data_flag) || i_gen_tlp_start) && i_axis_slave2_trdy) //start transmit
next_state = HEADER_TX;
else
next_state = IDLE;
end
HEADER_TX:
begin
if(i_axis_slave2_trdy)
next_state = DATA_TX;
else
next_state = state;
end
DATA_TX:
begin
if((i_user_define_data_flag || i_last_data) && !o_mwr_tx_hold)//transmit end
next_state = IDLE;
else
next_state = state;
end
default:
begin
next_state = IDLE;
end
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
o_axis_slave2_tdata <= 128'b0;
o_axis_slave2_tvld <= 1'b0;
o_axis_slave2_tuser <= 1'b0;
o_axis_slave2_tlast <= 1'b0;
end
else if(!o_mwr_tx_hold)
begin
case(state)
IDLE:
begin
o_axis_slave2_tdata <= 128'b0;
o_axis_slave2_tvld <= 1'b0;
o_axis_slave2_tuser <= 1'b0;
o_axis_slave2_tlast <= 1'b0;
end
HEADER_TX:
begin
o_axis_slave2_tvld <= 1'b1;
o_axis_slave2_tlast <= 1'b0;
if(mwr32_req_tx)
o_axis_slave2_tdata <= {{mwr_addr[31:2],2'b0},requester_id,tag,dwbe,mwr_header_tx};
else if(mwr64_req_tx)
o_axis_slave2_tdata <= {{mwr_addr[31:2],2'b0},mwr_addr[63:32],requester_id,tag,dwbe,mwr_header_tx};
end
DATA_TX:
begin
if(i_user_define_data_flag)
begin
o_axis_slave2_tvld <= 1'b1;
o_axis_slave2_tdata <= endian_convert({96'b0,mwr_data});
o_axis_slave2_tlast <= 1'b1;
end
else
begin
o_axis_slave2_tvld <= data_vlad;
o_axis_slave2_tdata <= endian_convert(i_rd_data);
if(i_last_data)
o_axis_slave2_tlast <= 1'b1;
end
end
default:
begin
o_axis_slave2_tdata <= 128'b0;
o_axis_slave2_tvld <= 1'b0;
o_axis_slave2_tuser <= 1'b0;
o_axis_slave2_tlast <= 1'b0;
end
endcase
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_mwr_tx_busy <= 1'b0;
else if(~(|mwr_length) && tx_done)
o_mwr_tx_busy <= 1'b0;
else if(mwr_req_start)
o_mwr_tx_busy <= 1'b1;
end
//ack
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_mwr32_req_ack <= 1'b0;
else if(!i_mwr32_req)
o_mwr32_req_ack <= 1'b0;
else if(i_mwr32_req && !o_mwr_tx_busy)
o_mwr32_req_ack <= 1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_mwr64_req_ack <= 1'b0;
else if(!i_mwr64_req)
o_mwr64_req_ack <= 1'b0;
else if(i_mwr64_req && !o_mwr_tx_busy)
o_mwr64_req_ack <= 1'b1;
end
assign o_mwr_tlp_tx = state == DATA_TX;
//******************************************************************debug*************************************************************************
//check for 128byte only
wire tlp_tx_vld;
reg tlp_data_tx;
reg [2:0] tlp_data_cnt;
reg [13:0] tlp_tx_sum;
assign tlp_tx_vld = i_axis_slave2_trdy && o_axis_slave2_tvld;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tlp_data_tx <= 1'b0;
else if(state == DATA_TX)
tlp_data_tx <= 1'b1;
else if(tlp_tx_vld)
tlp_data_tx <= 1'b0;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tlp_data_cnt <= 3'b0;
else if(tx_done)
tlp_data_cnt <= 3'b0;
else if(tlp_data_tx && tlp_tx_vld)
tlp_data_cnt <= tlp_data_cnt + 3'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tlp_tx_sum <= 14'b0;
else if(i_tx_restart)
tlp_tx_sum <= 14'b0;
else if(tx_done)
tlp_tx_sum <= tlp_tx_sum + 14'b1;
end
//debug_bus
//assign o_dbg_bus = {
// tlp_tx_sum //13:0
// };
//convert from little endian into big endian
function [127:0] endian_convert;
input [127:0] data_in;
begin
endian_convert[32*0+31:32*0+0] = {data_in[32*0+7:32*0+0], data_in[32*0+15:32*0+8], data_in[32*0+23:32*0+16], data_in[32*0+31:32*0+24]};
endian_convert[32*1+31:32*1+0] = {data_in[32*1+7:32*1+0], data_in[32*1+15:32*1+8], data_in[32*1+23:32*1+16], data_in[32*1+31:32*1+24]};
endian_convert[32*2+31:32*2+0] = {data_in[32*2+7:32*2+0], data_in[32*2+15:32*2+8], data_in[32*2+23:32*2+16], data_in[32*2+31:32*2+24]};
endian_convert[32*3+31:32*3+0] = {data_in[32*3+7:32*3+0], data_in[32*3+15:32*3+8], data_in[32*3+23:32*3+16], data_in[32*3+31:32*3+24]};
end
endfunction
endmodule |
module ipsl_pcie_dma_tx_mwr_rd_ctrl #(
parameter ADDR_WIDTH = 4'd9
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
//**********************************************************************
//ram interface
input i_rd_en ,
input [9:0] i_rd_length ,
input i_mwr_tx_busy ,
input i_mwr_tx_hold ,
input i_mwr_tlp_tx ,
output wire o_gen_tlp_start ,
output wire [127:0] o_rd_data ,
output wire o_last_data ,
//ram_rd
output wire o_bar_rd_clk_en ,
output wire [ADDR_WIDTH-1:0] o_bar_rd_addr ,
input [127:0] i_bar_rd_data
);
reg rd_en_ff;
wire rd_start;
reg [10:0] rd_addr;
reg [9:0] data_remain_cnt;
reg [9:0] data_remain_cnt_ff;
wire rd_ram_hold;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
rd_en_ff <= 1'b0;
else
rd_en_ff <= i_rd_en;
end
assign rd_start = ~rd_en_ff && i_rd_en;
//calculating rd addr from rd length
//data need to read
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_remain_cnt <= 10'b0;
else if(rd_start)
data_remain_cnt <= i_rd_length;
else if(!rd_ram_hold)
begin
if(data_remain_cnt >= 10'd4)
data_remain_cnt <= data_remain_cnt - 10'd4;
else if(data_remain_cnt < 10'd4)
data_remain_cnt <= 10'b0;
end
end
//data_shift
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_remain_cnt_ff <= 10'b0;
else if(!rd_ram_hold)
data_remain_cnt_ff <= data_remain_cnt;
end
//rd_dw_addr
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
rd_addr <= 11'b0;
else if(!i_mwr_tx_busy)
rd_addr <= 11'b0;
else if(o_bar_rd_clk_en && !rd_ram_hold)
begin
if(data_remain_cnt_ff >= 10'd4 )
rd_addr <= rd_addr +11'd4;
else
rd_addr <= rd_addr + {9'b0+data_remain_cnt_ff[1:0]};
end
end
ipsl_pcie_dma_rd_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH )
)
u_ipsl_pcie_dma_mwr_rd_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
//ram interface
.i_rd_en (rd_en_ff ),
.i_rd_length (i_rd_length ),
.i_rd_addr ({51'b0,rd_addr,2'b0} ),
.i_tx_hold (i_mwr_tx_hold ),
.i_tlp_tx (i_mwr_tlp_tx ),
.o_rd_ram_hold (rd_ram_hold ),
.o_gen_tlp_start (o_gen_tlp_start ),
.o_rd_data (o_rd_data ),
.o_last_data (o_last_data ),
//ram_rd
.o_bar_rd_clk_en (o_bar_rd_clk_en ),
.o_bar_rd_addr (o_bar_rd_addr ),
.i_bar_rd_data (i_bar_rd_data )
);
endmodule |
module ipsl_pcie_dma_rx_mwr_wr_ctrl #(
parameter ADDR_WIDTH = 4'd9
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
//**********************************************************************
input i_mwr_wr_start ,
input [9:0] i_mwr_length ,
input [7:0] i_mwr_dwbe ,
input [127:0] i_mwr_data ,
input [3:0] i_mwr_dw_vld ,
input [63:0] i_mwr_addr ,
input [1:0] i_bar_hit ,
//**********************************************************************
//ram write control
output wire o_mwr_wr_en ,
output wire [ADDR_WIDTH-1:0] o_mwr_wr_addr ,
output wire [127:0] o_mwr_wr_data ,
output wire [15:0] o_mwr_wr_be ,
output wire [1:0] o_mwr_wr_bar_hit
);
ipsl_pcie_dma_wr_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH )
)
ipsl_pcie_dma_mwr_wr_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
.i_wr_start (i_mwr_wr_start ),
.i_length (i_mwr_length ),
.i_dwbe (i_mwr_dwbe ),
.i_data (i_mwr_data ),
.i_dw_vld (i_mwr_dw_vld ),
.i_addr (i_mwr_addr ),
.i_bar_hit (i_bar_hit ),
//**********************************************************************
//ram write control
.o_wr_en (o_mwr_wr_en ),
.o_wr_addr (o_mwr_wr_addr ),
.o_wr_data (o_mwr_wr_data ),
.o_wr_be (o_mwr_wr_be ),
.o_wr_bar_hit (o_mwr_wr_bar_hit )
);
endmodule |
module ipsl_pcie_dma_tx_cpld_rd_ctrl #(
parameter ADDR_WIDTH = 4'd9
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
//**********************************************************************
//ram interface
input i_rd_en ,
input [9:0] i_rd_length ,
input [63:0] i_rd_addr ,
input i_cpld_tx_hold ,
input i_cpld_tlp_tx ,
output wire o_gen_tlp_start ,
output wire [127:0] o_rd_data ,
output wire o_last_data ,
//ram_rd
output wire o_bar_rd_clk_en ,
output wire [ADDR_WIDTH-1:0] o_bar_rd_addr ,
input [127:0] i_bar_rd_data
);
ipsl_pcie_dma_rd_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH )
)
u_ipsl_pcie_dma_cpld_rd_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
//ram interface
.i_rd_en (i_rd_en ),
.i_rd_length (i_rd_length ),
.i_rd_addr (i_rd_addr ),
.i_tx_hold (i_cpld_tx_hold ),
.i_tlp_tx (i_cpld_tlp_tx ),
.o_rd_ram_hold ( ),//no use
.o_gen_tlp_start (o_gen_tlp_start ),
.o_rd_data (o_rd_data ),
.o_last_data (o_last_data ),
//ram_rd
.o_bar_rd_clk_en (o_bar_rd_clk_en ),
.o_bar_rd_addr (o_bar_rd_addr ),
.i_bar_rd_data (i_bar_rd_data )
);
endmodule |
module ipsl_pcie_dma_tlp_tx_mux #(
parameter integer AXIS_SLAVE_NUM = 3
)
(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
//**********************************************************************
//from dma
//axis_slave0 interface
output wire o_dma_axis_slave0_trdy ,
input i_dma_axis_slave0_tvld ,
input [127:0] i_dma_axis_slave0_tdata ,
input i_dma_axis_slave0_tlast ,
input i_dma_axis_slave0_tuser ,
//axis_slave1 interface
output wire o_dma_axis_slave1_trdy ,
input i_dma_axis_slave1_tvld ,
input [127:0] i_dma_axis_slave1_tdata ,
input i_dma_axis_slave1_tlast ,
input i_dma_axis_slave1_tuser ,
//axis_slave2 interface
output wire o_dma_axis_slave2_trdy ,
input i_dma_axis_slave2_tvld ,
input [127:0] i_dma_axis_slave2_tdata ,
input i_dma_axis_slave2_tlast ,
input i_dma_axis_slave2_tuser ,
//credit interface
//from pcie
input i_cfg_ido_req_en ,
input i_cfg_ido_cpl_en ,
input [7:0] i_xadm_ph_cdts ,
input [11:0] i_xadm_pd_cdts ,
input [7:0] i_xadm_nph_cdts ,
input [11:0] i_xadm_npd_cdts ,
input [7:0] i_xadm_cplh_cdts ,
input [11:0] i_xadm_cpld_cdts ,
//pcie_axis_slave0
input i_pcie_axis_slave_trdy ,
output wire o_pcie_axis_slave_tvld ,
output wire [127:0] o_pcie_axis_slave_tdata ,
output wire o_pcie_axis_slave_tlast ,
output wire o_pcie_axis_slave_tuser
);
localparam SLAVE0_FIFO_DEEP = 8'd128; //should be 2^N real_deep = deep < 16 ? 16 : deep;
localparam SLAVE1_FIFO_DEEP = 8'd128; //should be 2^N real_deep = deep < 16 ? 16 : deep;
localparam SLAVE2_FIFO_DEEP = 8'd128; //should be 2^N real_deep = deep < 16 ? 16 : deep;
localparam DATA_WIDTH = 8'd131;
localparam IDLE = 2'd0;
localparam CPLD_TX = 2'd1;
localparam MWR_TX = 2'd2;
localparam MRD_TX = 2'd3;
wire [130:0] slave0_fifo_data_in;
wire [130:0] slave1_fifo_data_in;
wire [130:0] slave2_fifo_data_in;
reg [1:0] state;
reg [1:0] next_state;
wire cpld_tx_rdy;
wire mrd_tx_rdy;
wire mwr_tx_rdy;
wire cpld_fifo_out_rdy;
wire mrd_fifo_out_rdy;
wire mwr_fifo_out_rdy;
wire [130:0] cpld_fifo_out;
wire [130:0] mrd_fifo_out;
wire [130:0] mwr_fifo_out;
wire axis_slave0_vld;
wire axis_slave1_vld;
wire axis_slave2_vld;
wire cpld_tx_vld;
reg mwr_tx_vld;
wire mrd_tx_vld;
reg mwr_fifo_out_rdy_ff;
reg axis_slave2_vld_ff;
reg mwr_last_ff;
reg [9:0] mwr_length;
reg [130:0] axis_slave;
reg [7:0] xadm_nph_cdts;
reg [11:0] xadm_pd_cdts;
reg [7:0] xadm_ph_cdts;
//axis_slave
generate
if (AXIS_SLAVE_NUM == 1)
begin
assign slave0_fifo_data_in = {i_dma_axis_slave0_tvld,i_dma_axis_slave0_tuser,i_dma_axis_slave0_tlast,i_dma_axis_slave0_tdata};
pgs_pciex4_prefetch_fifo_v1_2
#(
.D (SLAVE0_FIFO_DEEP ), //should be 2^N
.W (DATA_WIDTH )
)
u_axis_slave0_fifo
(
.clk (clk ),
.rst_n (rst_n ),
.data_in_valid (i_dma_axis_slave0_tvld ),
.data_in (slave0_fifo_data_in ),
.data_in_ready (o_dma_axis_slave0_trdy ),
.data_out_ready (cpld_fifo_out_rdy ),
.data_out (cpld_fifo_out ),
.data_out_valid (axis_slave0_vld )
);
//cpld :infinite credit
assign cpld_tx_vld = axis_slave0_vld;
assign cpld_fifo_out_rdy = cpld_tx_rdy & i_pcie_axis_slave_trdy;
end
else
begin
assign cpld_tx_vld = 1'b0;
assign cpld_fifo_out = 131'b0;
end
endgenerate
//axis_slave1 mrd
assign slave1_fifo_data_in = {i_dma_axis_slave1_tvld,i_dma_axis_slave1_tuser,i_dma_axis_slave1_tlast,i_dma_axis_slave1_tdata};
pgs_pciex4_prefetch_fifo_v1_2
#(
.D (SLAVE1_FIFO_DEEP ), //should be 2^N
.W (DATA_WIDTH )
)
u_axis_slave1_fifo
(
.clk (clk ),
.rst_n (rst_n ),
.data_in_valid (i_dma_axis_slave1_tvld ),
.data_in (slave1_fifo_data_in ),
.data_in_ready (o_dma_axis_slave1_trdy ),
.data_out_ready (mrd_fifo_out_rdy ),
.data_out (mrd_fifo_out ),
.data_out_valid (axis_slave1_vld )
);
//Calculating mrd credit
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
xadm_nph_cdts <= 8'b0;
else
xadm_nph_cdts <= i_xadm_nph_cdts;
end
assign mrd_tx_vld = (|xadm_nph_cdts) ? axis_slave1_vld : 1'b0 ;
assign mrd_fifo_out_rdy = mrd_tx_rdy & i_pcie_axis_slave_trdy;
//axis_slave2 mwr
assign slave2_fifo_data_in = {i_dma_axis_slave2_tvld,i_dma_axis_slave2_tuser,i_dma_axis_slave2_tlast,i_dma_axis_slave2_tdata};
pgs_pciex4_prefetch_fifo_v1_2
#(
.D (SLAVE2_FIFO_DEEP ), //should be 2^N
.W (DATA_WIDTH )
)
u_axis_slave2_fifo
(
.clk (clk ),
.rst_n (rst_n ),
.data_in_valid (i_dma_axis_slave2_tvld ),
.data_in (slave2_fifo_data_in ),
.data_in_ready (o_dma_axis_slave2_trdy ),
.data_out_ready (mwr_fifo_out_rdy ),
.data_out (mwr_fifo_out ),
.data_out_valid (axis_slave2_vld )
);
assign mwr_fifo_out_rdy = mwr_tx_rdy & i_pcie_axis_slave_trdy & mwr_tx_vld;
//Calculating mwr credit
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
xadm_pd_cdts <= 12'b0;
else
xadm_pd_cdts <= i_xadm_pd_cdts;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
xadm_ph_cdts <= 8'b0;
else
xadm_ph_cdts <= i_xadm_ph_cdts;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
axis_slave2_vld_ff <= 1'b0;
else
axis_slave2_vld_ff <= axis_slave2_vld;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr_last_ff <= 1'b0;
else
mwr_last_ff <= mwr_fifo_out[128];
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr_fifo_out_rdy_ff <= 1'b0;
else
mwr_fifo_out_rdy_ff <= mwr_fifo_out_rdy;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr_length <= 10'b0;
else if((axis_slave2_vld & ~axis_slave2_vld_ff) || (mwr_last_ff & axis_slave2_vld & mwr_fifo_out_rdy_ff))
mwr_length <= mwr_fifo_out[9:0];
end
//assign mwr_tx_vld = ({i_xadm_pd_cdts,2'b0} >= {4'b0,mwr_length}) ? (|i_xadm_ph_cdts & axis_slave1_vld): 1'b0 ;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr_tx_vld <= 1'b0;
else if(mwr_fifo_out[128] & mwr_fifo_out_rdy)
mwr_tx_vld <= 1'b0;
else
mwr_tx_vld <= ({i_xadm_pd_cdts,2'b0} >= {4'b0,mwr_length}) && (|i_xadm_ph_cdts & axis_slave2_vld);
end
//tx fsm
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
state <= IDLE;
else
state <= next_state;
end
always @(*)
begin
case(state)
IDLE:
begin
if(cpld_tx_vld)
next_state = CPLD_TX;
else if(mwr_tx_vld)
next_state = MWR_TX;
else if(mrd_tx_vld)
next_state = MRD_TX;
else
next_state = IDLE;
end
CPLD_TX:
begin
if(cpld_tx_vld)
next_state = state;
else if(mwr_tx_vld)
next_state = MWR_TX;
else if(mrd_tx_vld)
next_state = MRD_TX;
else
next_state = IDLE;
end
MWR_TX:
begin
if(mwr_tx_vld)
next_state = state;
else if(cpld_tx_vld)
next_state = CPLD_TX;
else if(mrd_tx_vld)
next_state = MRD_TX;
else
next_state = IDLE;
end
MRD_TX:
begin
if(mrd_tx_vld)
next_state = state;
else if(cpld_tx_vld)
next_state = CPLD_TX;
else if(mwr_tx_vld)
next_state = MWR_TX;
else
next_state = IDLE;
end
default:
begin
next_state = IDLE;
end
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
//cpld_tx_rdy <= 1'b0;
//mwr_tx_rdy <= 1'b0;
//mrd_tx_rdy <= 1'b0;
axis_slave <= 131'b0;
end
else if(i_pcie_axis_slave_trdy)
begin
case(state)
IDLE:
begin
//cpld_tx_rdy <= 1'b0;
//mwr_tx_rdy <= 1'b0;
//mrd_tx_rdy <= 1'b0;
axis_slave <= 131'b0;
end
CPLD_TX:
begin
//cpld_tx_rdy <= 1'b1;
//mwr_tx_rdy <= 1'b0;
//mrd_tx_rdy <= 1'b0;
axis_slave <= (cpld_fifo_out_rdy & axis_slave0_vld) ? cpld_fifo_out : 131'b0;
end
MWR_TX:
begin
//cpld_tx_rdy <= 1'b0;
//mwr_tx_rdy <= 1'b1;
//mrd_tx_rdy <= 1'b0;
axis_slave <= (mwr_fifo_out_rdy & axis_slave2_vld) ? mwr_fifo_out : 131'b0;
end
MRD_TX:
begin
//cpld_tx_rdy <= 1'b0;
//mwr_tx_rdy <= 1'b0;
//mrd_tx_rdy <= 1'b1;
axis_slave <= (mrd_fifo_out_rdy & axis_slave1_vld) ? mrd_fifo_out : 131'b0;
end
default:
begin
//cpld_tx_rdy <= 1'b0;
//mwr_tx_rdy <= 1'b0;
//mrd_tx_rdy <= 1'b0;
axis_slave <= 131'b0;
end
endcase
end
end
assign cpld_tx_rdy = state == CPLD_TX ;
assign mwr_tx_rdy = state == MWR_TX ;
assign mrd_tx_rdy = state == MRD_TX ;
assign o_pcie_axis_slave_tdata = axis_slave[127:0];
assign o_pcie_axis_slave_tlast = axis_slave[128];
assign o_pcie_axis_slave_tuser = axis_slave[129];
assign o_pcie_axis_slave_tvld = axis_slave[130];
endmodule |
module ipsl_pcie_dma_rx_top #(
parameter DEVICE_TYPE = 3'd0 , //3'd0:EP,3'd1:Legacy EP,3'd4:RC
parameter ADDR_WIDTH = 4'd9
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
input [2:0] i_cfg_max_rd_req_size ,
//**********************************************************************
//AXIS master interface
input i_axis_master_tvld ,
output wire o_axis_master_trdy ,
input [127:0] i_axis_master_tdata ,
input [3:0] i_axis_master_tkeep ,
input i_axis_master_tlast ,
input [7:0] i_axis_master_tuser ,
output wire [2:0] o_trgt1_radm_pkt_halt ,
// input [5:0] i_radm_grant_tlp_type ,
//**********************************************************************
//bar0 rd interface
input i_bar0_rd_clk_en ,
input [ADDR_WIDTH-1:0] i_bar0_rd_addr ,
output wire [127:0] o_bar0_rd_data ,
//bar2 rd interface
input i_bar2_rd_clk_en ,
input [ADDR_WIDTH-1:0] i_bar2_rd_addr ,
output wire [127:0] o_bar2_rd_data ,
//bar1 wr interface
output reg o_bar1_wr_en ,
output reg [ADDR_WIDTH-1:0] o_bar1_wr_addr ,
output reg [127:0] o_bar1_wr_data ,
output reg [15:0] o_bar1_wr_byte_en ,
//**********************************************************************
//to tx top
//req rcv
output wire [2:0] o_mrd_tc ,
output wire [2:0] o_mrd_attr ,
output wire [9:0] o_mrd_length ,
output wire [15:0] o_mrd_id ,
output wire [7:0] o_mrd_tag ,
output wire [63:0] o_mrd_addr ,
output wire o_cpld_req_vld ,
input i_cpld_req_rdy ,
input i_cpld_tx_rdy ,
//cpld rcv
output wire o_cpld_rcv ,
output wire [7:0] o_cpld_tag ,
input i_tag_full ,
//rst tlp cnt
output wire [63:0] o_dma_check_result ,
input i_tx_restart
//output wire [42:0] o_dbg_bus_rx_ctrl ,
//output wire [69:0] o_dbg_tlp_rcv_cnt
);
wire mwr_wr_start;
wire [9:0] mwr_length;
wire [7:0] mwr_dwbe;
wire [127:0] mwr_data;
wire [3:0] mwr_dw_vld;
wire [63:0] mwr_addr;
wire cpld_wr_start;
wire [9:0] cpld_length;
wire [6:0] cpld_low_addr;
wire [11:0] cpld_byte_cnt;
wire [127:0] cpld_data;
wire [3:0] cpld_dw_vld;
wire multicpld_flag;
wire [1:0] bar_hit;
//mwr wr
wire mwr_wr_en;
wire [ADDR_WIDTH-1:0] mwr_wr_addr;
wire [127:0] mwr_wr_data;
wire [15:0] mwr_wr_be;
wire [1:0] mwr_wr_bar_hit;
//cpld wr
wire cpld_wr_en;
wire [ADDR_WIDTH-1:0] cpld_wr_addr;
wire [127:0] cpld_wr_data;
wire [15:0] cpld_wr_be;
wire [1:0] cpld_wr_bar_hit;
//bar0 wr interface
reg bar0_wr_en;
reg [ADDR_WIDTH-1:0] bar0_wr_addr;
reg [127:0] bar0_wr_data;
reg [15:0] bar0_wr_byte_en;
//bar2 wr interface
wire bar2_wr_en;
wire [ADDR_WIDTH-1:0] bar2_wr_addr;
wire [127:0] bar2_wr_data;
wire [15:0] bar2_wr_byte_en;
ipsl_pcie_dma_tlp_rcv #(
.DEVICE_TYPE (DEVICE_TYPE )
)
u_ipsl_pcie_dma_tlp_rcv
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
//AXIS master interface
.i_axis_master_tvld (i_axis_master_tvld ),
.o_axis_master_trdy (o_axis_master_trdy ),
.i_axis_master_tdata (i_axis_master_tdata ),
.i_axis_master_tkeep (i_axis_master_tkeep ),
.i_axis_master_tlast (i_axis_master_tlast ),
.i_axis_master_tuser (i_axis_master_tuser ),
.o_trgt1_radm_pkt_halt (o_trgt1_radm_pkt_halt ),
// .i_radm_grant_tlp_type (i_radm_grant_tlp_type ),
//**********************************************************************
//to mwr write control
.o_mwr_wr_start (mwr_wr_start ),
.o_mwr_length (mwr_length ),
.o_mwr_dwbe (mwr_dwbe ),
.o_mwr_data (mwr_data ),
.o_mwr_dw_vld (mwr_dw_vld ),
.o_mwr_addr (mwr_addr ),
//to cpld write control
.o_cpld_wr_start (cpld_wr_start ),
.o_cpld_length (cpld_length ),
.o_cpld_low_addr (cpld_low_addr ),
.o_cpld_byte_cnt (cpld_byte_cnt ),
.o_cpld_data (cpld_data ),
.o_cpld_dw_vld (cpld_dw_vld ),
.o_multicpld_flag (multicpld_flag ),
//write bar hit
.o_bar_hit (bar_hit ),
//**********************************************************************
//to tx top
//req rcv
.o_mrd_tc (o_mrd_tc ),
.o_mrd_attr (o_mrd_attr ),
.o_mrd_length (o_mrd_length ),
.o_mrd_id (o_mrd_id ),
.o_mrd_tag (o_mrd_tag ),
.o_mrd_addr (o_mrd_addr ),
.o_cpld_req_vld (o_cpld_req_vld ),
.i_cpld_req_rdy (i_cpld_req_rdy ),
.i_cpld_tx_rdy (i_cpld_tx_rdy ),
//cpld rcv
.o_cpld_rcv (o_cpld_rcv ),
.o_cpld_tag (o_cpld_tag ),
.i_tag_full (i_tag_full ),
//rst tlp cnt
.o_dma_check_result (o_dma_check_result ),
.i_tx_restart (i_tx_restart )
//.o_dbg_bus (o_dbg_bus_rx_ctrl ),
//.o_dbg_tlp_rcv_cnt (o_dbg_tlp_rcv_cnt )
);
ipsl_pcie_dma_rx_cpld_wr_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH )
)
u_cpld_wr_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
.i_cfg_max_rd_req_size (i_cfg_max_rd_req_size ), //input [2:0]
//****************************************
.i_cpld_wr_start (cpld_wr_start ),
.i_cpld_length (cpld_length ),
.i_cpld_low_addr (cpld_low_addr ),
.i_cpld_byte_cnt (cpld_byte_cnt ),
.i_cpld_data (cpld_data ),
.i_cpld_dw_vld (cpld_dw_vld ),
.i_cpld_tag (o_cpld_tag ),
.i_bar_hit (bar_hit ),
.i_multicpld_flag (multicpld_flag ),
//****************************************
.o_cpld_wr_en (cpld_wr_en ),
.o_cpld_wr_addr (cpld_wr_addr ),
.o_cpld_wr_data (cpld_wr_data ),
.o_cpld_wr_be (cpld_wr_be ),
.o_cpld_wr_bar_hit (cpld_wr_bar_hit )
);
ipsl_pcie_dma_rx_mwr_wr_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH )
)
u_mwr_wr_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//****************************************
.i_mwr_wr_start (mwr_wr_start ),
.i_mwr_length (mwr_length ),
.i_mwr_dwbe (mwr_dwbe ),
.i_mwr_data (mwr_data ),
.i_mwr_dw_vld (mwr_dw_vld ),
.i_mwr_addr (mwr_addr ),
.i_bar_hit (bar_hit ),
//****************************************
.o_mwr_wr_en (mwr_wr_en ),
.o_mwr_wr_addr (mwr_wr_addr ),
.o_mwr_wr_data (mwr_wr_data ),
.o_mwr_wr_be (mwr_wr_be ),
.o_mwr_wr_bar_hit (mwr_wr_bar_hit )
);
//bar0 interface
always@(*)
begin
if(mwr_wr_bar_hit == 2'b0)
begin
bar0_wr_en = mwr_wr_en;
bar0_wr_addr = mwr_wr_addr;
bar0_wr_data = mwr_wr_data;
bar0_wr_byte_en = mwr_wr_be;
end
else
begin
bar0_wr_en = 1'b0;
bar0_wr_addr = {ADDR_WIDTH{1'b0}};
bar0_wr_data = 128'b0;
bar0_wr_byte_en = 16'b0;
end
end
//bar1 interface
always@(*)
begin
if(bar_hit == 2'b1 && (DEVICE_TYPE == 3'b000 || DEVICE_TYPE == 3'b001))
begin
o_bar1_wr_en = 1'b1;
o_bar1_wr_addr = mwr_addr[ADDR_WIDTH-1:0];
o_bar1_wr_data = mwr_data;
o_bar1_wr_byte_en = {{4{mwr_dwbe[3]}},{4{mwr_dwbe[2]}},{4{mwr_dwbe[1]}},{4{mwr_dwbe[0]}}};
end
else
begin
o_bar1_wr_en = 1'b0;
o_bar1_wr_addr = {ADDR_WIDTH{1'b0}};
o_bar1_wr_data = 128'b0;
o_bar1_wr_byte_en = 16'b0;
end
end
assign bar2_wr_en = cpld_wr_en;
assign bar2_wr_addr = cpld_wr_addr;
assign bar2_wr_data = cpld_wr_data;
assign bar2_wr_byte_en = cpld_wr_be;
ipsl_pcie_dma_ram ipsl_pcie_dma_bar0 (
.wr_data (bar0_wr_data ), // input [127:0]
.wr_addr (bar0_wr_addr ), // input [8:0]
.wr_en (bar0_wr_en ), // input
.wr_byte_en (bar0_wr_byte_en ), // input [15:0]
.wr_clk (clk ), // input
.wr_rst (~rst_n ), // input
.rd_addr (i_bar0_rd_addr ), // input [8:0]
.rd_data (o_bar0_rd_data ), // output [127:0]
.rd_clk (clk ), // input
.rd_clk_en (i_bar0_rd_clk_en ), // input
.rd_rst (~rst_n ) // input
);
ipsl_pcie_dma_ram ipsl_pcie_dma_bar2 (
.wr_data (bar2_wr_data ), // input [127:0]
.wr_addr (bar2_wr_addr ), // input [8:0]
.wr_en (bar2_wr_en ), // input
.wr_byte_en (bar2_wr_byte_en ), // input [15:0]
.wr_clk (clk ), // input
.wr_rst (~rst_n ), // input
.rd_addr (i_bar2_rd_addr ), // input [8:0]
.rd_data (o_bar2_rd_data ), // output [127:0]
.rd_clk (clk ), // input
.rd_clk_en (i_bar2_rd_clk_en ), // input
.rd_rst (~rst_n ) // input
);
endmodule |
module ipsl_pcie_dma_tx_top #(
parameter DEVICE_TYPE = 3'd0 , //3'd0:EP,3'd1:Legacy EP,3'd4:RC
parameter ADDR_WIDTH = 4'd9
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
input [7:0] i_cfg_pbus_num ,
input [4:0] i_cfg_pbus_dev_num ,
input [2:0] i_cfg_max_rd_req_size ,
input [2:0] i_cfg_max_payload_size ,
//**********************************************************************
//axis_slave0 interface
input i_axis_slave0_trdy ,
output wire o_axis_slave0_tvld ,
output wire [127:0] o_axis_slave0_tdata ,
output wire o_axis_slave0_tlast ,
output wire o_axis_slave0_tuser ,
//axis_slave1 interface
input i_axis_slave1_trdy ,
output wire o_axis_slave1_tvld ,
output wire [127:0] o_axis_slave1_tdata ,
output wire o_axis_slave1_tlast ,
output wire o_axis_slave1_tuser ,
//axis_slave2 interface
input i_axis_slave2_trdy ,
output wire o_axis_slave2_tvld ,
output wire [127:0] o_axis_slave2_tdata ,
output wire o_axis_slave2_tlast ,
output wire o_axis_slave2_tuser ,
//**********************************************************************
//from dma_controller
input i_user_define_data_flag ,
//mwr
input i_mwr32_req ,
output wire o_mwr32_req_ack ,
input i_mwr64_req ,
output wire o_mwr64_req_ack ,
input i_mrd32_req ,
output wire o_mrd32_req_ack ,
input i_mrd64_req ,
output wire o_mrd64_req_ack ,
input [9:0] i_req_length ,
input [63:0] i_req_addr ,
input [31:0] i_req_data ,
//mrd
//**********************************************************************
//bar0 rd interface
output wire o_bar0_rd_clk_en ,
output wire [ADDR_WIDTH-1:0] o_bar0_rd_addr ,
input [127:0] i_bar0_rd_data ,
//bar2 rd interface
output wire o_bar2_rd_clk_en ,
output wire [ADDR_WIDTH-1:0] o_bar2_rd_addr ,
input [127:0] i_bar2_rd_data ,
//**********************************************************************
//from rx top
//req rcv
input [2:0] i_mrd_tc ,
input [2:0] i_mrd_attr ,
input [9:0] i_mrd_length ,
input [15:0] i_mrd_id ,
input [7:0] i_mrd_tag ,
input [63:0] i_mrd_addr ,
input i_cpld_req_vld ,
output wire o_cpld_req_rdy ,
output wire o_cpld_tx_rdy ,
//cpld rcv
input i_cpld_rcv ,
input [7:0] i_cpld_tag ,
output wire o_tag_full ,
//debug
//rst tlp cnt
input i_tx_restart
//output wire [13:0] o_dbg_bus_mrd_tx ,
//output wire [72:0] o_dbg_bus_mwr_tx
);
//mwr
wire mwr_rd_en;
wire [9:0] mwr_rd_length;
wire mwr_tx_busy;
wire mwr_tx_hold;
wire mwr_tlp_tx;
wire mwr_gen_tlp_start;
wire [127:0] mwr_rd_data;
wire mwr_last_data;
//cpld
wire cpld_rd_en;
wire [9:0] cpld_rd_length;
wire [63:0] cpld_rd_addr;
wire cpld_tx_hold;
wire cpld_tlp_tx;
wire cpld_gen_tlp_start;
wire [127:0] cpld_rd_data;
wire cpld_last_data;
ipsl_pcie_dma_tx_cpld_rd_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH )
)
u_ipsl_pcie_dma_tx_cpld_rd_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
//ram interface
.i_rd_en (cpld_rd_en ),
.i_rd_length (cpld_rd_length ),
.i_rd_addr (cpld_rd_addr ),
.i_cpld_tx_hold (cpld_tx_hold ),
.i_cpld_tlp_tx (cpld_tlp_tx ),
.o_gen_tlp_start (cpld_gen_tlp_start ),
.o_rd_data (cpld_rd_data ),
.o_last_data (cpld_last_data ),
//ram_rd
.o_bar_rd_clk_en (o_bar0_rd_clk_en ),
.o_bar_rd_addr (o_bar0_rd_addr ),
.i_bar_rd_data (i_bar0_rd_data )
);
ipsl_pcie_dma_tx_mwr_rd_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH )
)
u_ipsl_pcie_dma_tx_mwr_rd_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
//ram interface
.i_rd_en (mwr_rd_en ),
.i_rd_length (mwr_rd_length ),
.i_mwr_tx_busy (mwr_tx_busy ),
.i_mwr_tx_hold (mwr_tx_hold ),
.i_mwr_tlp_tx (mwr_tlp_tx ),
.o_gen_tlp_start (mwr_gen_tlp_start ),
.o_rd_data (mwr_rd_data ),
.o_last_data (mwr_last_data ),
//ram_rd
.o_bar_rd_clk_en (o_bar2_rd_clk_en ),
.o_bar_rd_addr (o_bar2_rd_addr ),
.i_bar_rd_data (i_bar2_rd_data )
);
ipsl_pcie_dma_cpld_tx_ctrl u_ipsl_pcie_dma_cpld_tx_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
.i_cfg_pbus_num (i_cfg_pbus_num ), //input [7:0]
.i_cfg_pbus_dev_num (i_cfg_pbus_dev_num ), //input [4:0]
.i_cfg_max_payload_size (i_cfg_max_payload_size ), //input [2:0]
//**********************************************************************
//from rx
.i_mrd_tc (i_mrd_tc ),
.i_mrd_attr (i_mrd_attr ),
.i_mrd_length (i_mrd_length ),
.i_mrd_id (i_mrd_id ),
.i_mrd_tag (i_mrd_tag ),
.i_mrd_addr (i_mrd_addr ),
.i_cpld_req_vld (i_cpld_req_vld ),
.o_cpld_req_rdy (o_cpld_req_rdy ),
.o_cpld_tx_rdy (o_cpld_tx_rdy ),
//**********************************************************************
//ram interface
.o_rd_en (cpld_rd_en ),
.o_rd_length (cpld_rd_length ),
.o_rd_addr (cpld_rd_addr ),
.o_cpld_tx_hold (cpld_tx_hold ),
.o_cpld_tlp_tx (cpld_tlp_tx ),
.i_gen_tlp_start (cpld_gen_tlp_start ),
.i_rd_data (cpld_rd_data ),
.i_last_data (cpld_last_data ),
//axis_slave interface
.i_axis_slave0_trdy (i_axis_slave0_trdy ),
.o_axis_slave0_tvld (o_axis_slave0_tvld ),
.o_axis_slave0_tdata (o_axis_slave0_tdata ),
.o_axis_slave0_tlast (o_axis_slave0_tlast ),
.o_axis_slave0_tuser (o_axis_slave0_tuser )
);
ipsl_pcie_dma_mrd_tx_ctrl u_ipsl_pcie_dma_mrd_tx_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
.i_cfg_pbus_num (i_cfg_pbus_num ), //input [7:0]
.i_cfg_pbus_dev_num (i_cfg_pbus_dev_num ), //input [4:0]
.i_cfg_max_rd_req_size (i_cfg_max_rd_req_size ), //input [2:0]
//**********************************************************************
//from dma controller
.i_mrd32_req (i_mrd32_req ),
.o_mrd32_req_ack (o_mrd32_req_ack ),
.i_mrd64_req (i_mrd64_req ),
.o_mrd64_req_ack (o_mrd64_req_ack ),
.i_req_length (i_req_length ),
.i_req_addr (i_req_addr ),
//**********************************************************************
.i_cpld_rcv (i_cpld_rcv ),
.i_cpld_tag (i_cpld_tag ),
.o_tag_full (o_tag_full ),
//axis_slave interface
.i_axis_slave1_trdy (i_axis_slave1_trdy ),
.o_axis_slave1_tvld (o_axis_slave1_tvld ),
.o_axis_slave1_tdata (o_axis_slave1_tdata ),
.o_axis_slave1_tlast (o_axis_slave1_tlast ),
.o_axis_slave1_tuser (o_axis_slave1_tuser ),
//debug
.i_tx_restart (i_tx_restart )
//.o_dbg_bus (o_dbg_bus_mrd_tx )
);
ipsl_pcie_dma_mwr_tx_ctrl #(
.DEVICE_TYPE (DEVICE_TYPE )
)
u_ipsl_pcie_dma_mwr_tx_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
.i_cfg_pbus_num (i_cfg_pbus_num ), //input [7:0]
.i_cfg_pbus_dev_num (i_cfg_pbus_dev_num ), //input [4:0]
.i_cfg_max_payload_size (i_cfg_max_payload_size ), //input [2:0]
//**********************************************************************
//from dma controller
.i_user_define_data_flag (i_user_define_data_flag ),
.i_mwr32_req (i_mwr32_req ),
.o_mwr32_req_ack (o_mwr32_req_ack ),
.i_mwr64_req (i_mwr64_req ),
.o_mwr64_req_ack (o_mwr64_req_ack ),
.i_req_length (i_req_length ),
.i_req_addr (i_req_addr ),
.i_req_data (i_req_data ),
//**********************************************************************
//ram interface
.o_rd_en (mwr_rd_en ),
.o_rd_length (mwr_rd_length ),
.i_gen_tlp_start (mwr_gen_tlp_start ),
.i_rd_data (mwr_rd_data ),
.i_last_data (mwr_last_data ),
//axis_slave interface
.i_axis_slave2_trdy (i_axis_slave2_trdy ),
.o_axis_slave2_tvld (o_axis_slave2_tvld ),
.o_axis_slave2_tdata (o_axis_slave2_tdata ),
.o_axis_slave2_tlast (o_axis_slave2_tlast ),
.o_axis_slave2_tuser (o_axis_slave2_tuser ),
.o_mwr_tx_busy (mwr_tx_busy ),
.o_mwr_tx_hold (mwr_tx_hold ),
.o_mwr_tlp_tx (mwr_tlp_tx ),
.i_tx_restart (i_tx_restart )
//debug
//.o_dbg_bus (o_dbg_bus_mwr_tx )
);
endmodule |
module ipsl_pcie_dma_controller #(
parameter DEVICE_TYPE = 3'd0 , //3'd0:EP,3'd1:Legacy EP,3'd4:RC
parameter ADDR_WIDTH = 4'd9
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
//**********************************************************************
//bar1 wr interface
input i_bar1_wr_en ,
input [ADDR_WIDTH-1:0] i_bar1_wr_addr ,
input [127:0] i_bar1_wr_data ,
input [15:0] i_bar1_wr_byte_en ,
//**********************************************************************
//apb interface
input i_apb_psel ,
input [8:0] i_apb_paddr ,
input [31:0] i_apb_pwdata ,
input [3:0] i_apb_pstrb ,
input i_apb_pwrite ,
input i_apb_penable ,
output reg o_apb_prdy ,
output reg [31:0] o_apb_prdata ,
//**********************************************************************
output reg o_user_define_data_flag ,
//**********************************************************************
//to tx
output reg o_mwr32_req ,
input i_mwr32_req_ack ,
output reg o_mwr64_req ,
input i_mwr64_req_ack ,
output reg o_mrd32_req ,
input i_mrd32_req_ack ,
output reg o_mrd64_req ,
input i_mrd64_req_ack ,
output reg [9:0] o_req_length ,
output reg [63:0] o_req_addr ,
output reg [31:0] o_req_data ,
input [63:0] i_dma_check_result ,
output wire o_tx_restart ,
output reg o_cross_4kb_boundary
);
//apb register for rc
reg [31:0] apb_cmd_reg;
reg [31:0] apb_cmd_length;
reg [31:0] apb_cmd_l_addr;
reg [31:0] apb_cmd_h_addr;
reg [31:0] apb_cmd_data;
reg [31:0] apb_pwdata;
reg apb_cmd_reg_vld;
reg apb_cmd_length_vld;
reg apb_cmd_l_addr_vld;
reg apb_cmd_h_addr_vld;
reg apb_cmd_data_vld;
reg apb_ctrl_cfg_done;
reg apb_length_cfg_done;
reg apb_l_addr_cfg_done;
reg apb_h_addr_cfg_done;
reg apb_data_cfg_done;
//mwr register for ep
reg [31:0] dma_cmd_reg;
reg [31:0] dma_cmd_l_addr;
reg [31:0] dma_cmd_h_addr;
reg [31:0] dma_wr_data;
reg dma_cmd_reg_vld;
reg dma_cmd_l_addr_vld;
reg dma_cmd_h_addr_vld;
reg dma_ctrl_cfg_done;
reg dma_l_addr_cfg_done;
reg dma_h_addr_cfg_done;
wire user_define_data_flag;
wire dma_32_64_addr_cmd_flag;
wire dma_wr_rd_cmd_flag;
wire ack_rcv;
wire device_rc;
wire device_ep;
wire apb_write;
wire apb_read;
wire cmd_reg_cfg_done;
wire l_addr_cfg_done;
wire h_addr_cfg_done;
wire mwr32_req_vld;
wire mwr64_req_vld;
wire mrd32_req_vld;
wire mrd64_req_vld;
//4KB boundary
wire [12:0] req_l_addr;
wire [12:0] total_data;
wire [12:0] target_addr;
wire cross_4kb_boundary;
//dma check
wire dma_check_success;
assign device_rc = (DEVICE_TYPE == 3'b100 ) ? 1'b1 : 1'b0;
assign device_ep = (DEVICE_TYPE == 3'b000 || DEVICE_TYPE == 3'b001) ? 1'b1 : 1'b0;
//req_ack
assign ack_rcv = i_mwr32_req_ack | i_mwr64_req_ack | i_mrd32_req_ack | i_mrd64_req_ack;
//********************************************************************dma controller register*********************************************************************
//dma_wr_data
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_wr_data <= 32'b0;
else
dma_wr_data <= i_bar1_wr_data[31:0];
end
//dma_cmd_reg_vld
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_cmd_reg_vld <= 1'b0;
else if(dma_cmd_reg_vld)
dma_cmd_reg_vld <= 1'b0;
else
dma_cmd_reg_vld <= &i_bar1_wr_byte_en && i_bar1_wr_en && (i_bar1_wr_addr[8:0] == 9'h100);
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_cmd_reg <= 32'd0;
else if(dma_cmd_reg_vld)
dma_cmd_reg <= dma_wr_data;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_ctrl_cfg_done <= 1'b0;
else if (ack_rcv || cross_4kb_boundary)
dma_ctrl_cfg_done <= 1'b0;
else if(dma_cmd_reg_vld)
dma_ctrl_cfg_done <= 1'b1;
end
//dma_cmd_l_addr
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_cmd_l_addr_vld <= 1'b0;
else if(dma_cmd_l_addr_vld)
dma_cmd_l_addr_vld <= 1'b0;
else
dma_cmd_l_addr_vld <= &i_bar1_wr_byte_en && i_bar1_wr_en && (i_bar1_wr_addr[8:0] == 9'h110);
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_cmd_l_addr <= 32'd0;
else if(dma_cmd_l_addr_vld)
dma_cmd_l_addr <= dma_wr_data;
end
//l_addr_cfg_done
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_l_addr_cfg_done <= 1'b0;
else if (ack_rcv || cross_4kb_boundary)
dma_l_addr_cfg_done <= 1'b0;
else if(dma_cmd_l_addr_vld)
dma_l_addr_cfg_done <= 1'b1;
end
//dma_cmd_h_addr
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_cmd_h_addr_vld <= 1'b0;
else if(dma_cmd_l_addr_vld)
dma_cmd_h_addr_vld <= 1'b0;
else
dma_cmd_h_addr_vld <= &i_bar1_wr_byte_en && i_bar1_wr_en && (i_bar1_wr_addr[8:0] == 9'h120);
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_cmd_h_addr <= 32'd0;
else if(dma_cmd_h_addr_vld)
dma_cmd_h_addr <= dma_wr_data;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_h_addr_cfg_done <= 1'b0;
else if (ack_rcv || cross_4kb_boundary)
dma_h_addr_cfg_done <= 1'b0;
else if(dma_cmd_h_addr_vld)
dma_h_addr_cfg_done <= 1'b1;
end
//********************************************************************apb controller register*********************************************************************
assign apb_write = i_apb_psel && i_apb_penable && i_apb_pwrite;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_pwdata <= 32'b0;
else
apb_pwdata <= i_apb_pwdata;
end
//apb_cmd_reg for rc
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_reg_vld <= 1'b0;
else if(apb_cmd_reg_vld)
apb_cmd_reg_vld <= 1'b0;
else
apb_cmd_reg_vld <= &i_apb_pstrb && apb_write && (i_apb_paddr == 9'h140);
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_reg <= 32'd0;
else if(apb_cmd_reg_vld)
apb_cmd_reg <= apb_pwdata;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_ctrl_cfg_done <= 1'b0;
else if (ack_rcv || cross_4kb_boundary)
apb_ctrl_cfg_done <= 1'b0;
else if(apb_cmd_reg_vld)
apb_ctrl_cfg_done <= 1'b1;
end
//apb_cmd_length
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_length_vld <= 1'b0;
else if(apb_cmd_length_vld)
apb_cmd_length_vld <= 1'b0;
else
apb_cmd_length_vld <= &i_apb_pstrb && apb_write && (i_apb_paddr == 9'h150);
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_length <= 32'd0;
else if(apb_cmd_length_vld)
apb_cmd_length <= apb_pwdata;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_length_cfg_done <= 1'b0;
else if (ack_rcv || cross_4kb_boundary)
apb_length_cfg_done <= 1'b0;
else if(apb_cmd_length_vld)
apb_length_cfg_done <= 1'b1;
end
//apb_cmd_l_addr
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_l_addr_vld <= 1'b0;
else if(apb_cmd_l_addr_vld)
apb_cmd_l_addr_vld <= 1'b0;
else
apb_cmd_l_addr_vld <= &i_apb_pstrb && apb_write && (i_apb_paddr == 9'h160);
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_l_addr <= 32'd0;
else if(apb_cmd_l_addr_vld)
apb_cmd_l_addr <= apb_pwdata;
end
//apb_l_addr_cfg_done
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_l_addr_cfg_done <= 1'b0;
else if (ack_rcv || cross_4kb_boundary)
apb_l_addr_cfg_done <= 1'b0;
else if(apb_cmd_l_addr_vld)
apb_l_addr_cfg_done <= 1'b1;
end
//apb_cmd_h_addr
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_h_addr_vld <= 1'b0;
else if(apb_cmd_h_addr_vld)
apb_cmd_h_addr_vld <= 1'b0;
else
apb_cmd_h_addr_vld <= &i_apb_pstrb && apb_write && (i_apb_paddr == 9'h170);
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_h_addr <= 32'd0;
else if(apb_cmd_h_addr_vld)
apb_cmd_h_addr <= apb_pwdata;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_h_addr_cfg_done <= 1'b0;
else if (ack_rcv || cross_4kb_boundary)
apb_h_addr_cfg_done <= 1'b0;
else if(apb_cmd_h_addr_vld)
apb_h_addr_cfg_done <= 1'b1;
end
//apb_cmd_data
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_data_vld <= 1'b0;
else if(apb_cmd_data_vld)
apb_cmd_data_vld <= 1'b0;
else
apb_cmd_data_vld <= &i_apb_pstrb && apb_write && (i_apb_paddr == 9'h180);
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_cmd_data <= 32'd0;
else if(apb_cmd_data_vld)
apb_cmd_data <= apb_pwdata;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
apb_data_cfg_done <= 1'b0;
else if (ack_rcv || cross_4kb_boundary)
apb_data_cfg_done <= 1'b0;
else if(apb_cmd_data_vld)
apb_data_cfg_done <= 1'b1;
end
assign cmd_reg_cfg_done = (device_ep && dma_ctrl_cfg_done) || (device_rc && apb_ctrl_cfg_done);
assign l_addr_cfg_done = (device_ep && dma_l_addr_cfg_done) || (device_rc && apb_l_addr_cfg_done);
assign h_addr_cfg_done = (device_ep && dma_h_addr_cfg_done) || (device_rc && apb_h_addr_cfg_done);
//********************************************************************req information*********************************************************************
//o_req_length
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_req_length <= 10'd0;
else if(cmd_reg_cfg_done)
begin
if(device_ep)
o_req_length <= dma_cmd_reg[9:0] + 10'h1;
else if(device_rc && apb_length_cfg_done)
o_req_length <= apb_cmd_length[9:0] + 10'h1;
end
end
//o_req_addr
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_req_addr[31:0] <= 32'd0;
else if(l_addr_cfg_done)
if(device_ep)
o_req_addr[31:0] <= dma_cmd_l_addr;
else if(device_rc)
o_req_addr[31:0] <= apb_cmd_l_addr;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_req_addr[63:32] <= 32'd0;
else if(h_addr_cfg_done)
if(device_ep)
o_req_addr[63:32] <= dma_cmd_h_addr;
else if(device_rc)
o_req_addr[63:32] <= apb_cmd_h_addr;
end
//o_req_data
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_req_data <= 32'd0;
else if(apb_data_cfg_done)
o_req_data[31:0] <= apb_cmd_data;
end
//******************************************************************tx request*************************************************************************
assign user_define_data_flag = device_rc ? apb_cmd_reg[8] : 1'b0; //0:use ram data; 1:use user define data
assign dma_32_64_addr_cmd_flag = device_rc ? apb_cmd_reg[16] : (device_ep ? dma_cmd_reg[16] : 1'b0); //0:32; 1:64;
assign dma_wr_rd_cmd_flag = device_rc ? apb_cmd_reg[24] : (device_ep ? dma_cmd_reg[24] : 1'b0); //0:read; 1:write;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_user_define_data_flag <= 1'd0;
else
o_user_define_data_flag <= user_define_data_flag;
end
//gen req valid
assign mwr32_req_vld = !dma_32_64_addr_cmd_flag && dma_wr_rd_cmd_flag && cmd_reg_cfg_done && l_addr_cfg_done && !cross_4kb_boundary;
assign mwr64_req_vld = dma_32_64_addr_cmd_flag && dma_wr_rd_cmd_flag && cmd_reg_cfg_done && l_addr_cfg_done && h_addr_cfg_done && !cross_4kb_boundary;
assign mrd32_req_vld = !dma_32_64_addr_cmd_flag && !dma_wr_rd_cmd_flag && cmd_reg_cfg_done && l_addr_cfg_done && !cross_4kb_boundary;
assign mrd64_req_vld = dma_32_64_addr_cmd_flag && !dma_wr_rd_cmd_flag && cmd_reg_cfg_done && l_addr_cfg_done && h_addr_cfg_done && !cross_4kb_boundary;
//mwr_32_req
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_mwr32_req <= 1'b0;
else if(i_mwr32_req_ack)
o_mwr32_req <= 1'b0;
else if(mwr32_req_vld)
begin
if(!user_define_data_flag)
o_mwr32_req <= 1'b1;
else if(apb_data_cfg_done)
o_mwr32_req <= 1'b1;
else
o_mwr32_req <= 1'b0;
end
end
//mwr_64_req
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_mwr64_req <= 1'b0;
else if(i_mwr64_req_ack)
o_mwr64_req <= 1'b0;
else if(mwr64_req_vld)
begin
if(!user_define_data_flag)
o_mwr64_req <= 1'b1;
else if(apb_data_cfg_done)
o_mwr64_req <= 1'b1;
else
o_mwr64_req <= 1'b0;
end
end
//mrd_32_req
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_mrd32_req <= 1'b0;
else if(i_mrd32_req_ack)
o_mrd32_req <= 1'b0;
else if(mrd32_req_vld)
o_mrd32_req <= 1'b1;
end
//mrd_64_req
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_mrd64_req <= 1'b0;
else if(i_mrd64_req_ack)
o_mrd64_req <= 1'b0;
else if(mrd64_req_vld)
o_mrd64_req <= 1'b1;
end
//**********************************************************************apb_read***************************************************************************
assign apb_read = i_apb_psel && i_apb_penable && ~i_apb_pwrite ;
assign dma_check_success = ~(|i_dma_check_result);
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_apb_prdata <= 32'd0;
else if(apb_read)
case(i_apb_paddr)
9'h100: o_apb_prdata <= dma_cmd_reg;
9'h110: o_apb_prdata <= dma_cmd_l_addr;
9'h120: o_apb_prdata <= dma_cmd_h_addr;
9'h140: o_apb_prdata <= apb_cmd_reg;
9'h150: o_apb_prdata <= {22'b0,apb_cmd_length};
9'h160: o_apb_prdata <= apb_cmd_l_addr;
9'h170: o_apb_prdata <= apb_cmd_h_addr;
9'h180: o_apb_prdata <= apb_cmd_data;
9'h190: o_apb_prdata <= i_dma_check_result[31:0];
9'h1A0: o_apb_prdata <= i_dma_check_result[63:32];
9'h1B0: o_apb_prdata <= {31'b0,dma_check_success};
default: o_apb_prdata <= 32'd0;
endcase
end
//apb_rdy
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_apb_prdy <= 1'b0;
else if(i_apb_psel && i_apb_penable && !o_apb_prdy)
o_apb_prdy <= 1'b1;
else
o_apb_prdy <= 1'b0;
end
assign o_tx_restart = i_bar1_wr_en && (i_bar1_wr_addr[8:0] == 9'h110);
//detect 4-KB boundary
assign req_l_addr = device_rc ? apb_cmd_l_addr[12:0] : dma_cmd_l_addr[12:0];
assign total_data = ~((device_rc && apb_length_cfg_done) || (device_ep && dma_ctrl_cfg_done)) ? 13'd0 :
(o_req_length[9:0] == 10'b0) ? 13'h1000 : {1'b0,o_req_length[9:0],2'b0}; //total byte data
assign target_addr = ~l_addr_cfg_done ? 13'd0 : (req_l_addr[12:0] + total_data);
assign cross_4kb_boundary = ~l_addr_cfg_done ? 1'b0 :
(target_addr[12] == req_l_addr[12]) ? 1'b0 : |target_addr[11:0];
//4-KB boundary flag
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_cross_4kb_boundary <= 1'b0;
else if(cross_4kb_boundary)
o_cross_4kb_boundary <= 1'b1;
else if(cmd_reg_cfg_done)
o_cross_4kb_boundary <= 1'b0;
end
endmodule |
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