module
stringlengths 21
82.9k
|
|---|
module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, force_t, thold_0_b, sg_0, scan_in, scan_out, re0, ra0, do0, re1, ra1, do1, we0, wa0, di0, we1, wa1, di1, perr);
parameter ADDRESSABLE_PORTS = 64; // number of addressable register in this array
parameter ADDRESSBUS_WIDTH = 6; // width of the bus to address all ports (2^ADDRESSBUS_WIDTH >= addressable_ports)
parameter PORT_BITWIDTH = 64; // bitwidth of ports
parameter LATCHED_READ = 1'b1;
parameter LATCHED_READ_DATA = 1'b1;
parameter LATCHED_WRITE = 1'b1;
// POWER PINS
(* ground_pin=1 *)
inout gnd;
(* power_pin=1 *)
inout vdd;
input [0:`NCLK_WIDTH-1] nclk;
//-------------------------------------------------------------------
// Pervasive
//-------------------------------------------------------------------
input delay_lclkr_dc;
input mpw1_dc_b;
input mpw2_dc_b;
input force_t;
input thold_0_b;
input sg_0;
input scan_in;
output scan_out;
//-------------------------------------------------------------------
// Functional
//-------------------------------------------------------------------
input re0;
input [0:ADDRESSBUS_WIDTH-1] ra0;
output [0:PORT_BITWIDTH-1] do0;
input re1;
input [0:ADDRESSBUS_WIDTH-1] ra1;
output [0:PORT_BITWIDTH-1] do1;
input we0;
input [0:ADDRESSBUS_WIDTH-1] wa0;
input [0:PORT_BITWIDTH-1] di0;
input we1;
input [0:ADDRESSBUS_WIDTH-1] wa1;
input [0:PORT_BITWIDTH-1] di1;
output perr;
reg re0_q;
reg we0_q;
reg [0:ADDRESSBUS_WIDTH-1] ra0_q;
reg [0:ADDRESSBUS_WIDTH-1] wa0_q;
reg [0:PORT_BITWIDTH-1] do0_q;
wire [0:PORT_BITWIDTH-1] do0_d;
reg [0:PORT_BITWIDTH-1] di0_q;
reg re1_q;
reg we1_q;
reg [0:ADDRESSBUS_WIDTH-1] ra1_q;
reg [0:ADDRESSBUS_WIDTH-1] wa1_q;
reg [0:PORT_BITWIDTH-1] do1_q;
wire [0:PORT_BITWIDTH-1] do1_d;
reg [0:PORT_BITWIDTH-1] di1_q;
wire correct_clk;
wire reset;
wire reset_hi;
reg reset_q;
wire [0:PORT_BITWIDTH-1] dout0; //std
wire wen0; //std
wire [0:ADDRESSBUS_WIDTH-1] addr_w0; //std
wire [0:ADDRESSBUS_WIDTH-1] addr_r0; //std
wire [0:PORT_BITWIDTH-1] din0; //std
wire [0:PORT_BITWIDTH-1] dout1; //std
wire wen1; //std
wire [0:ADDRESSBUS_WIDTH-1] addr_w1; //std
wire [0:ADDRESSBUS_WIDTH-1] addr_r1; //std
wire [0:PORT_BITWIDTH-1] din1; //std
reg we1_latch_q;
reg [0:ADDRESSBUS_WIDTH-1] wa1_latch_q;
reg [0:PORT_BITWIDTH-1] di1_latch_q;
(* analysis_not_referenced="true" *)
wire unused_SPO_0;
(* analysis_not_referenced="true" *)
wire unused_SPO_1;
generate
assign reset = nclk[1];
assign correct_clk = nclk[0];
assign reset_hi = reset;
// Slow Latches (nclk)
always @(posedge correct_clk or posedge reset)
begin: slatch
begin
if (reset == 1'b1)
we1_latch_q <= 1'b0;
else
begin
we1_latch_q <= we1_q;
wa1_latch_q <= wa1_q;
di1_latch_q <= di1_q;
end
end
end
// repower latches for resets
always @(posedge correct_clk)
begin: rlatch
reset_q <= reset_hi;
end
// need to select which array to write based on the lowest order bit of the address which will indicate odd or even itag
// when both we0 and we1 are both asserted it is assumed that the low order bit of wa0 will not be equal to the low order
// bit of wa1
assign addr_w0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
assign wen0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? we1_q : we0_q;
assign din0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? di1_q : di0_q;
assign addr_r0 = (ra0_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
assign addr_w1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
assign wen1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? we1_q : we0_q;
assign din1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? di1_q : di0_q;
assign addr_r1 = (ra1_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
assign perr = 1'b0;
begin : xhdl0
genvar i;
for (i = 0; i <= PORT_BITWIDTH - 1; i = i + 1)
begin : array_gen0
RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D0(
.DPO(dout0[i]),
.SPO(unused_SPO_0),
.A0(addr_w0[0]),
.A1(addr_w0[1]),
.A2(addr_w0[2]),
.A3(addr_w0[3]),
.A4(addr_w0[4]),
.A5(addr_w0[5]),
.D(din0[i]),
.DPRA0(addr_r0[0]),
.DPRA1(addr_r0[1]),
.DPRA2(addr_r0[2]),
.DPRA3(addr_r0[3]),
.DPRA4(addr_r0[4]),
.DPRA5(addr_r0[5]),
.WCLK(correct_clk),
.WE(wen0)
);
RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D1(
.DPO(dout1[i]),
.SPO(unused_SPO_1),
.A0(addr_w1[0]),
.A1(addr_w1[1]),
.A2(addr_w1[2]),
.A3(addr_w1[3]),
.A4(addr_w1[4]),
.A5(addr_w1[5]),
.D(din1[i]),
.DPRA0(addr_r1[0]),
.DPRA1(addr_r1[1]),
.DPRA2(addr_r1[2]),
.DPRA3(addr_r1[3]),
.DPRA4(addr_r1[4]),
.DPRA5(addr_r1[5]),
.WCLK(correct_clk),
.WE(wen1)
);
end
end
assign do0_d = (ra0_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0;
assign do1_d = (ra1_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0;
assign do0 = do0_q;
assign do1 = do1_q;
if (LATCHED_READ == 1'b0)
begin : read_latched_false
always @(*)
begin
re0_q <= re0;
ra0_q <= ra0;
re1_q <= re1;
ra1_q <= ra1;
end
end
if (LATCHED_READ == 1'b1)
begin : read_latched_true
always @(posedge correct_clk)
begin: read_latches
if (correct_clk == 1'b1)
begin
if (reset_q == 1'b1)
begin
re0_q <= 1'b0;
ra0_q <= {ADDRESSBUS_WIDTH{1'b0}};
re1_q <= 1'b0;
ra1_q <= {ADDRESSBUS_WIDTH{1'b0}};
end
else
begin
re0_q <= re0;
ra0_q <= ra0;
re1_q <= re1;
ra1_q <= ra1;
end
end
end
end
if (LATCHED_WRITE == 1'b0)
begin : write_latched_false
always @(*)
begin
we0_q <= we0;
wa0_q <= wa0;
di0_q <= di0;
we1_q <= we1;
wa1_q <= wa1;
di1_q <= di1;
end
end
if (LATCHED_WRITE == 1'b1)
begin : write_latched_true
always @(posedge correct_clk)
begin: write_latches
if (correct_clk == 1'b1)
begin
if (reset_q == 1'b1)
begin
we0_q <= 1'b0;
wa0_q <= {ADDRESSBUS_WIDTH{1'b0}};
di0_q <= {PORT_BITWIDTH{1'b0}};
we1_q <= 1'b0;
wa1_q <= {ADDRESSBUS_WIDTH{1'b0}};
di1_q <= {PORT_BITWIDTH{1'b0}};
end
else
begin
we0_q <= we0;
wa0_q <= wa0;
di0_q <= di0;
we1_q <= we1;
wa1_q <= wa1;
di1_q <= di1;
end
end
end
end
if (LATCHED_READ_DATA == 1'b0)
begin : read_data_latched_false
always @(*)
begin
do0_q <= do0_d;
do1_q <= do1_d;
end
end
if (LATCHED_READ_DATA == 1'b1)
begin : read_data_latched_true
always @(posedge correct_clk)
begin: read_data_latches
if (correct_clk == 1'b1)
begin
if (reset_q == 1'b1)
begin
do0_q <= {PORT_BITWIDTH{1'b0}};
do1_q <= {PORT_BITWIDTH{1'b0}};
end
else
begin
do0_q <= do0_d;
do1_q <= do1_d;
end
end
end
end
endgenerate
endmodule |
module tri_pri(
cond,
pri,
or_cond
);
parameter SIZE = 32; // Size of "cond", range 3 - 32
parameter REV = 0; // 0 = 0 is highest, 1 = 0 is lowest
parameter CMP_ZERO = 0; // 1 = include comparing cond to zero in pri vector, 0 = don't
input [0:SIZE-1] cond;
output [0:SIZE-1+CMP_ZERO] pri;
output or_cond;
// tri_pri
parameter s = SIZE - 1;
wire [0:s] l0;
wire [0:s] or_l1;
wire [0:s] or_l2;
wire [0:s] or_l3;
wire [0:s] or_l4;
wire [0:s] or_l5;
generate
begin
if (REV == 0)
begin
assign l0[0:s] = cond[0:s];
end
if (REV == 1)
begin
assign l0[0:s] = cond[s:0];
end
// Odd Numbered Levels are inverted
assign or_l1[0] = ~l0[0];
assign or_l1[1:s] = ~(l0[0:s - 1] | l0[1:s]);
if (s >= 2)
begin
assign or_l2[0:1] = ~or_l1[0:1];
assign or_l2[2:s] = ~(or_l1[2:s] & or_l1[0:s - 2]);
end
if (s < 2)
begin
assign or_l2 = ~or_l1;
end
if (s >= 4)
begin
assign or_l3[0:3] = ~or_l2[0:3];
assign or_l3[4:s] = ~(or_l2[4:s] | or_l2[0:s - 4]);
end
if (s < 4)
begin
assign or_l3 = ~or_l2;
end
if (s >= 8)
begin
assign or_l4[0:7] = ~or_l3[0:7];
assign or_l4[8:s] = ~(or_l3[8:s] & or_l3[0:s - 8]);
end
if (s < 8)
begin
assign or_l4 = ~or_l3;
end
if (s >= 16)
begin
assign or_l5[0:15] = ~or_l4[0:15];
assign or_l5[16:s] = ~(or_l4[16:s] | or_l4[0:s - 16]);
end
if (s < 16)
begin
assign or_l5 = ~or_l4;
end
//assert SIZE > 32 report "Maximum Size of 32 Exceeded!" severity error;
assign pri[0] = cond[0];
assign pri[1:s] = cond[1:s] & or_l5[0:s - 1];
if (CMP_ZERO == 1)
begin
assign pri[s + 1] = or_l5[s];
end
assign or_cond = ~or_l5[s];
end
endgenerate
//!! [fail; tri_pri; "Priority not zero or one hot!!"] : (pri1 ) <= not zero_or_one_hot(pri);
endmodule |
module tri_scom_addr_decode(
sc_addr,
scaddr_dec,
sc_req,
sc_r_nw,
scaddr_nvld,
sc_wr_nvld,
sc_rd_nvld,
vd,
gd
);
//=====================================================================
// I/O and Signal Declarations
//=====================================================================
parameter ADDR_SIZE = 64;
parameter SATID_NOBITS = 5; // should not be set by user
// Set the USE_ADDR, ADDR_IS_RDABLE, ADDR_IS_WRABLE vectors to generate a SCOM address
// HEX >>>>> "0000000000000000111111111111111122222222222222223333333333333333"
// ADDR >>>>> "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF"
//
// DEC >>>>> "0000000000111111111122222222223333333333444444444455555555556666"
// ADDR >>>>> "0123456789012345678901234567890123456789012345678901234567890123"
parameter [0:ADDR_SIZE-1] USE_ADDR = 64'b1000000000000000000000000000000000000000000000000000000000000000;
parameter [0:ADDR_SIZE-1] ADDR_IS_RDABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000;
parameter [0:ADDR_SIZE-1] ADDR_IS_WRABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000;
input [0:11-SATID_NOBITS-1] sc_addr; // binary coded scom address
output [0:ADDR_SIZE-1] scaddr_dec; // one hot coded scom address; not latched
input sc_req; // scom request
input sc_r_nw; // read / not write bit
output scaddr_nvld; // scom address not valid; not latched
output sc_wr_nvld; // scom write not allowed; not latched
output sc_rd_nvld; // scom read not allowed; not latched
inout vd;
inout gd;
//=====================================================================
wire [0:ADDR_SIZE-1] address;
// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
wire unused;
assign unused = vd | gd;
//=====================================================================
generate
begin : decode_it
genvar i;
for (i=0; i<ADDR_SIZE; i=i+1)
begin : decode_it
assign address[i] = ({{32-SATID_NOBITS{1'b0}},sc_addr} == i) & USE_ADDR[i];
end
end
endgenerate
assign scaddr_dec = address;
assign scaddr_nvld = sc_req & (~|address);
assign sc_wr_nvld = (~(|(address & ADDR_IS_WRABLE)) & sc_req & (~sc_r_nw));
assign sc_rd_nvld = (~(|(address & ADDR_IS_RDABLE)) & sc_req & sc_r_nw );
endmodule |
module tri_st_add_glbloc(
g01,
t01,
g08,
t08
);
input [0:7] g01; // after xor
input [0:7] t01;
output g08;
output t08;
wire [0:3] g02_b;
wire [0:3] t02_b;
wire [0:1] g04;
wire [0:1] t04;
wire g08_b;
wire t08_b;
assign g02_b[0] = (~(g01[0] | (t01[0] & g01[1])));
assign g02_b[1] = (~(g01[2] | (t01[2] & g01[3])));
assign g02_b[2] = (~(g01[4] | (t01[4] & g01[5])));
assign g02_b[3] = (~(g01[6] | (t01[6] & g01[7])));
assign t02_b[0] = (~(t01[0] & t01[1]));
assign t02_b[1] = (~(t01[2] & t01[3]));
assign t02_b[2] = (~(t01[4] & t01[5]));
assign t02_b[3] = (~(t01[6] & t01[7]));
assign g04[0] = (~(g02_b[0] & (t02_b[0] | g02_b[1])));
assign g04[1] = (~(g02_b[2] & (t02_b[2] | g02_b[3])));
assign t04[0] = (~(t02_b[0] | t02_b[1]));
assign t04[1] = (~(t02_b[2] | t02_b[3]));
assign g08_b = (~(g04[0] | (t04[0] & g04[1])));
assign t08_b = (~((t04[0] & t04[1])));
assign g08 = (~(g08_b)); // output
assign t08 = (~(t08_b)); // output
endmodule |
module tri_st_mult_boothrow(
s_neg,
s_x,
s_x2,
sign_bit_adj,
x,
q,
hot_one
);
input s_neg; // negate the row
input s_x; // shift by 0
input s_x2; // shift by 1
input sign_bit_adj;
input [0:31] x; // input (multiplicand)
output [0:32] q; // final output
// lsb term for row below
output hot_one;
wire [1:32] left;
//-------------------------------------------------------------------
// Build the booth mux row bit by bit
//-------------------------------------------------------------------
tri_bthmx u00(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(sign_bit_adj),
.right(left[1]),
.left(),
.q(q[0])
);
tri_bthmx u01(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[0]),
.right(left[2]),
.left(left[1]),
.q(q[1])
);
tri_bthmx u02(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[1]),
.right(left[3]),
.left(left[2]),
.q(q[2])
);
tri_bthmx u03(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[2]),
.right(left[4]),
.left(left[3]),
.q(q[3])
);
tri_bthmx u04(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[3]),
.right(left[5]),
.left(left[4]),
.q(q[4])
);
tri_bthmx u05(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[4]),
.right(left[6]),
.left(left[5]),
.q(q[5])
);
tri_bthmx u06(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[5]),
.right(left[7]),
.left(left[6]),
.q(q[6])
);
tri_bthmx u07(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[6]),
.right(left[8]),
.left(left[7]),
.q(q[7])
);
tri_bthmx u08(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[7]),
.right(left[9]),
.left(left[8]),
.q(q[8])
);
tri_bthmx u09(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[8]),
.right(left[10]),
.left(left[9]),
.q(q[9])
);
tri_bthmx u10(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[9]),
.right(left[11]),
.left(left[10]),
.q(q[10])
);
tri_bthmx u11(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[10]),
.right(left[12]),
.left(left[11]),
.q(q[11])
);
tri_bthmx u12(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[11]),
.right(left[13]),
.left(left[12]),
.q(q[12])
);
tri_bthmx u13(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[12]),
.right(left[14]),
.left(left[13]),
.q(q[13])
);
tri_bthmx u14(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[13]),
.right(left[15]),
.left(left[14]),
.q(q[14])
);
tri_bthmx u15(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[14]),
.right(left[16]),
.left(left[15]),
.q(q[15])
);
tri_bthmx u16(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[15]),
.right(left[17]),
.left(left[16]),
.q(q[16])
);
tri_bthmx u17(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[16]),
.right(left[18]),
.left(left[17]),
.q(q[17])
);
tri_bthmx u18(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[17]),
.right(left[19]),
.left(left[18]),
.q(q[18])
);
tri_bthmx u19(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[18]),
.right(left[20]),
.left(left[19]),
.q(q[19])
);
tri_bthmx u20(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[19]),
.right(left[21]),
.left(left[20]),
.q(q[20])
);
tri_bthmx u21(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[20]),
.right(left[22]),
.left(left[21]),
.q(q[21])
);
tri_bthmx u22(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[21]),
.right(left[23]),
.left(left[22]),
.q(q[22])
);
tri_bthmx u23(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[22]),
.right(left[24]),
.left(left[23]),
.q(q[23])
);
tri_bthmx u24(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[23]),
.right(left[25]),
.left(left[24]),
.q(q[24])
);
tri_bthmx u25(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[24]),
.right(left[26]),
.left(left[25]),
.q(q[25])
);
tri_bthmx u26(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[25]),
.right(left[27]),
.left(left[26]),
.q(q[26])
);
tri_bthmx u27(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[26]),
.right(left[28]),
.left(left[27]),
.q(q[27])
);
tri_bthmx u28(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[27]),
.right(left[29]),
.left(left[28]),
.q(q[28])
);
tri_bthmx u29(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[28]),
.right(left[30]),
.left(left[29]),
.q(q[29])
);
tri_bthmx u30(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[29]),
.right(left[31]),
.left(left[30]),
.q(q[30])
);
tri_bthmx u31(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[30]),
.right(left[32]),
.left(left[31]),
.q(q[31])
);
tri_bthmx u32(
.sneg(s_neg),
.sx(s_x),
.sx2(s_x2),
.x(x[31]),
.right(s_neg),
.left(left[32]),
.q(q[32])
);
assign hot_one = s_neg & (s_x | s_x2);
endmodule |
module tri_st_rot_ins(
ins_log_fcn,
ins_cmp_byt,
ins_sra_wd,
ins_sra_dw,
ins_xtd_byte,
ins_xtd_half,
ins_xtd_wd,
ins_prtyw,
ins_prtyd,
data0_i,
data1_i,
mrg_byp_log,
res_ins
);
input [0:3] ins_log_fcn; // use pass ra for rlwimi
// rs, ra/rb
// 0000 => "0"
// 0001 => rs AND rb
// 0010 => rs AND !rb
// 0011 => rs
// 0100 => !rs and RB
// 0101 => RB
// 0110 => rs xor RB
// 0111 => rs or RB
// 1000 => rs nor RB
// 1001 => rs xnor RB (use for cmp-byt)
// 1010 => !RB
// 1011 => rs or !rb
// 1100 => !rs
// 1101 => rs nand !rb, !rs or rb
// 1110 => rs nand rb ...
// 1111 => "1"
input ins_cmp_byt;
input ins_sra_wd;
input ins_sra_dw;
input ins_xtd_byte; // use with xtd
input ins_xtd_half; // use with xtd
input ins_xtd_wd; // use with xtd, sra
input ins_prtyw;
input ins_prtyd;
input [0:63] data0_i; //data input (rs)
input [0:63] data1_i; //data input (ra|rb)
output [0:63] mrg_byp_log;
output [0:63] res_ins; //insert data (also result of logicals)
wire [0:63] mrg_byp_log_b;
wire [0:63] res_log;
wire [0:7] byt_cmp;
wire [0:7] byt_cmp_b;
wire [0:63] byt_cmp_bus;
wire [0:63] sign_xtd_bus;
wire [0:63] xtd_byte_bus;
wire [0:63] xtd_half_bus;
wire [0:63] xtd_wd_bus;
wire [0:63] sra_dw_bus;
wire [0:63] sra_wd_bus;
wire [0:63] res_ins0_b;
wire [0:63] res_ins1_b;
wire [0:63] res_ins2_b;
wire [0:63] res_log0_b;
wire [0:63] res_log1_b;
wire [0:63] res_log2_b;
wire [0:63] res_log3_b;
wire [0:63] res_log_o0;
wire [0:63] res_log_o1;
wire [0:63] res_log_b;
wire [0:63] res_log2;
wire [0:3] byt0_cmp2_b;
wire [0:3] byt1_cmp2_b;
wire [0:3] byt2_cmp2_b;
wire [0:3] byt3_cmp2_b;
wire [0:3] byt4_cmp2_b;
wire [0:3] byt5_cmp2_b;
wire [0:3] byt6_cmp2_b;
wire [0:3] byt7_cmp2_b;
wire [0:1] byt0_cmp4;
wire [0:1] byt1_cmp4;
wire [0:1] byt2_cmp4;
wire [0:1] byt3_cmp4;
wire [0:1] byt4_cmp4;
wire [0:1] byt5_cmp4;
wire [0:1] byt6_cmp4;
wire [0:1] byt7_cmp4;
wire [0:63] sel_cmp_byt;
wire [0:63] sel_cmp_byt_b;
wire [0:63] data0_b;
wire [0:63] data1_b;
wire [0:63] data0;
wire [0:63] data1;
wire prtyhw0;
wire prtyhw1;
wire prtyhw2;
wire prtyhw3;
wire prtyw0;
wire prtyw1;
wire prtyd;
wire prty0;
wire prty1;
assign data0_b = (~data0_i);
assign data1_b = (~data1_i);
assign data0 = (~data0_b);
assign data1 = (~data1_b);
assign prtyhw0 = data0_i[7] ^ data0_i[15];
assign prtyhw1 = data0_i[23] ^ data0_i[31];
assign prtyhw2 = data0_i[39] ^ data0_i[47];
assign prtyhw3 = data0_i[55] ^ data0_i[63];
assign prtyw0 = prtyhw0 ^ prtyhw1;
assign prtyw1 = prtyhw2 ^ prtyhw3;
assign prtyd = prtyw0 ^ prtyw1;
assign prty1 = (prtyw1 & ins_prtyw) | (prtyd & ins_prtyd);
assign prty0 = (prtyw0 & ins_prtyw);
assign res_log2[31] = res_log[31] | prty0;
assign res_log2[63] = res_log[63] | prty1;
assign res_log2[0:30] = res_log[0:30];
assign res_log2[32:62] = res_log[32:62];
assign res_log0_b[0:63] = (~({64{ins_log_fcn[0]}} & data0_b[0:63] & data1_b[0:63]));
assign res_log1_b[0:63] = (~({64{ins_log_fcn[1]}} & data0_b[0:63] & data1[0:63]));
assign res_log2_b[0:63] = (~({64{ins_log_fcn[2]}} & data0[0:63] & data1_b[0:63]));
assign res_log3_b[0:63] = (~({64{ins_log_fcn[3]}} & data0[0:63] & data1[0:63]));
assign res_log_o0[0:63] = (~(res_log0_b[0:63] & res_log1_b[0:63]));
assign res_log_o1[0:63] = (~(res_log2_b[0:63] & res_log3_b[0:63]));
assign res_log_b[0:63] = (~(res_log_o0[0:63] | res_log_o1[0:63]));
assign res_log[0:63] = (~(res_log_b[0:63]));
assign mrg_byp_log_b[0:63] = (~(res_log[0:63]));
assign mrg_byp_log[0:63] = (~(mrg_byp_log_b[0:63]));
assign byt0_cmp2_b[0] = (~(res_log[0] & res_log[1]));
assign byt0_cmp2_b[1] = (~(res_log[2] & res_log[3]));
assign byt0_cmp2_b[2] = (~(res_log[4] & res_log[5]));
assign byt0_cmp2_b[3] = (~(res_log[6] & res_log[7]));
assign byt1_cmp2_b[0] = (~(res_log[8] & res_log[9]));
assign byt1_cmp2_b[1] = (~(res_log[10] & res_log[11]));
assign byt1_cmp2_b[2] = (~(res_log[12] & res_log[13]));
assign byt1_cmp2_b[3] = (~(res_log[14] & res_log[15]));
assign byt2_cmp2_b[0] = (~(res_log[16] & res_log[17]));
assign byt2_cmp2_b[1] = (~(res_log[18] & res_log[19]));
assign byt2_cmp2_b[2] = (~(res_log[20] & res_log[21]));
assign byt2_cmp2_b[3] = (~(res_log[22] & res_log[23]));
assign byt3_cmp2_b[0] = (~(res_log[24] & res_log[25]));
assign byt3_cmp2_b[1] = (~(res_log[26] & res_log[27]));
assign byt3_cmp2_b[2] = (~(res_log[28] & res_log[29]));
assign byt3_cmp2_b[3] = (~(res_log[30] & res_log[31]));
assign byt4_cmp2_b[0] = (~(res_log[32] & res_log[33]));
assign byt4_cmp2_b[1] = (~(res_log[34] & res_log[35]));
assign byt4_cmp2_b[2] = (~(res_log[36] & res_log[37]));
assign byt4_cmp2_b[3] = (~(res_log[38] & res_log[39]));
assign byt5_cmp2_b[0] = (~(res_log[40] & res_log[41]));
assign byt5_cmp2_b[1] = (~(res_log[42] & res_log[43]));
assign byt5_cmp2_b[2] = (~(res_log[44] & res_log[45]));
assign byt5_cmp2_b[3] = (~(res_log[46] & res_log[47]));
assign byt6_cmp2_b[0] = (~(res_log[48] & res_log[49]));
assign byt6_cmp2_b[1] = (~(res_log[50] & res_log[51]));
assign byt6_cmp2_b[2] = (~(res_log[52] & res_log[53]));
assign byt6_cmp2_b[3] = (~(res_log[54] & res_log[55]));
assign byt7_cmp2_b[0] = (~(res_log[56] & res_log[57]));
assign byt7_cmp2_b[1] = (~(res_log[58] & res_log[59]));
assign byt7_cmp2_b[2] = (~(res_log[60] & res_log[61]));
assign byt7_cmp2_b[3] = (~(res_log[62] & res_log[63]));
assign byt0_cmp4[0] = (~(byt0_cmp2_b[0] | byt0_cmp2_b[1]));
assign byt0_cmp4[1] = (~(byt0_cmp2_b[2] | byt0_cmp2_b[3]));
assign byt1_cmp4[0] = (~(byt1_cmp2_b[0] | byt1_cmp2_b[1]));
assign byt1_cmp4[1] = (~(byt1_cmp2_b[2] | byt1_cmp2_b[3]));
assign byt2_cmp4[0] = (~(byt2_cmp2_b[0] | byt2_cmp2_b[1]));
assign byt2_cmp4[1] = (~(byt2_cmp2_b[2] | byt2_cmp2_b[3]));
assign byt3_cmp4[0] = (~(byt3_cmp2_b[0] | byt3_cmp2_b[1]));
assign byt3_cmp4[1] = (~(byt3_cmp2_b[2] | byt3_cmp2_b[3]));
assign byt4_cmp4[0] = (~(byt4_cmp2_b[0] | byt4_cmp2_b[1]));
assign byt4_cmp4[1] = (~(byt4_cmp2_b[2] | byt4_cmp2_b[3]));
assign byt5_cmp4[0] = (~(byt5_cmp2_b[0] | byt5_cmp2_b[1]));
assign byt5_cmp4[1] = (~(byt5_cmp2_b[2] | byt5_cmp2_b[3]));
assign byt6_cmp4[0] = (~(byt6_cmp2_b[0] | byt6_cmp2_b[1]));
assign byt6_cmp4[1] = (~(byt6_cmp2_b[2] | byt6_cmp2_b[3]));
assign byt7_cmp4[0] = (~(byt7_cmp2_b[0] | byt7_cmp2_b[1]));
assign byt7_cmp4[1] = (~(byt7_cmp2_b[2] | byt7_cmp2_b[3]));
assign byt_cmp_b[0] = (~(byt0_cmp4[0] & byt0_cmp4[1]));
assign byt_cmp_b[1] = (~(byt1_cmp4[0] & byt1_cmp4[1]));
assign byt_cmp_b[2] = (~(byt2_cmp4[0] & byt2_cmp4[1]));
assign byt_cmp_b[3] = (~(byt3_cmp4[0] & byt3_cmp4[1]));
assign byt_cmp_b[4] = (~(byt4_cmp4[0] & byt4_cmp4[1]));
assign byt_cmp_b[5] = (~(byt5_cmp4[0] & byt5_cmp4[1]));
assign byt_cmp_b[6] = (~(byt6_cmp4[0] & byt6_cmp4[1]));
assign byt_cmp_b[7] = (~(byt7_cmp4[0] & byt7_cmp4[1]));
assign byt_cmp[0] = (~(byt_cmp_b[0]));
assign byt_cmp[1] = (~(byt_cmp_b[1]));
assign byt_cmp[2] = (~(byt_cmp_b[2]));
assign byt_cmp[3] = (~(byt_cmp_b[3]));
assign byt_cmp[4] = (~(byt_cmp_b[4]));
assign byt_cmp[5] = (~(byt_cmp_b[5]));
assign byt_cmp[6] = (~(byt_cmp_b[6]));
assign byt_cmp[7] = (~(byt_cmp_b[7]));
assign byt_cmp_bus[0:7] = {8{byt_cmp[0]}};
assign byt_cmp_bus[8:15] = {8{byt_cmp[1]}};
assign byt_cmp_bus[16:23] = {8{byt_cmp[2]}};
assign byt_cmp_bus[24:31] = {8{byt_cmp[3]}};
assign byt_cmp_bus[32:39] = {8{byt_cmp[4]}};
assign byt_cmp_bus[40:47] = {8{byt_cmp[5]}};
assign byt_cmp_bus[48:55] = {8{byt_cmp[6]}};
assign byt_cmp_bus[56:63] = {8{byt_cmp[7]}};
assign xtd_byte_bus[0:63] = {{57{data0[56]}}, data0[57:63]};
assign xtd_half_bus[0:63] = {{49{data0[48]}}, data0[49:63]};
assign xtd_wd_bus[0:63] = {{33{data0[32]}}, data0[33:63]};
assign sra_wd_bus[0:63] = {64{data0[32]}}; // all the bits for sra
assign sra_dw_bus[0:63] = {64{data0[0]}}; // all the bits for sra
assign sign_xtd_bus[0:63] = ({64{ins_xtd_byte}} & xtd_byte_bus[0:63]) |
({64{ins_xtd_half}} & xtd_half_bus[0:63]) |
({64{ins_xtd_wd}} & xtd_wd_bus[0:63]) |
({64{ins_sra_wd}} & sra_wd_bus[0:63]) |
({64{ins_sra_dw}} & sra_dw_bus[0:63]);
assign sel_cmp_byt = {64{ins_cmp_byt}};
assign sel_cmp_byt_b = ~{64{ins_cmp_byt}};
assign res_ins0_b[0:63] = (~(sel_cmp_byt & byt_cmp_bus[0:63]));
assign res_ins1_b[0:63] = (~(sel_cmp_byt_b & res_log2[0:63]));
assign res_ins2_b[0:63] = (~(sign_xtd_bus[0:63]));
assign res_ins[0:63] = (~(res_ins0_b[0:63] & res_ins1_b[0:63] & res_ins2_b[0:63])); //output--
endmodule |
module tri_st_popcnt_word(
b0,
b1,
b2,
b3,
y,
vdd,
gnd
);
input [0:3] b0;
input [0:3] b1;
input [0:3] b2;
input [0:3] b3;
output [0:5] y;
inout vdd;
inout gnd;
wire [0:0] s0;
wire [0:1] c1;
wire [0:1] s1;
wire [0:2] c2;
wire [0:1] s2;
wire [0:2] c3;
wire [0:1] s3;
wire [0:2] c4;
// Level 0
tri_csa32 csa_l0_0(
.vd(vdd),
.gd(gnd),
.a(b0[0]),
.b(b0[1]),
.c(b0[2]),
.sum(s0[0]),
.car(c1[0])
);
tri_csa22 csa_l0_1(
.a(b0[3]),
.b(s0[0]),
.sum(y[5]),
.car(c1[1])
);
// Level 1
tri_csa32 csa_l1_0(
.vd(vdd),
.gd(gnd),
.a(b1[0]),
.b(b1[1]),
.c(b1[2]),
.sum(s1[0]),
.car(c2[0])
);
tri_csa32 csa_l1_1(
.vd(vdd),
.gd(gnd),
.a(b1[3]),
.b(c1[0]),
.c(c1[1]),
.sum(s1[1]),
.car(c2[1])
);
tri_csa22 csa_l1_2(
.a(s1[0]),
.b(s1[1]),
.sum(y[4]),
.car(c2[2])
);
// Level 2
tri_csa32 csa_l2_0(
.vd(vdd),
.gd(gnd),
.a(b2[0]),
.b(b2[1]),
.c(b2[2]),
.sum(s2[0]),
.car(c3[0])
);
tri_csa32 csa_l2_1(
.vd(vdd),
.gd(gnd),
.a(b2[3]),
.b(c2[0]),
.c(c2[1]),
.sum(s2[1]),
.car(c3[1])
);
tri_csa32 csa_l2_2(
.vd(vdd),
.gd(gnd),
.a(c2[2]),
.b(s2[0]),
.c(s2[1]),
.sum(y[3]),
.car(c3[2])
);
// Level 3
tri_csa32 csa_l3_0(
.vd(vdd),
.gd(gnd),
.a(b3[0]),
.b(b3[1]),
.c(b3[2]),
.sum(s3[0]),
.car(c4[0])
);
tri_csa32 csa_l3_1(
.vd(vdd),
.gd(gnd),
.a(b3[3]),
.b(c3[0]),
.c(c3[1]),
.sum(s3[1]),
.car(c4[1])
);
tri_csa32 csa_l3_2(
.vd(vdd),
.gd(gnd),
.a(c3[2]),
.b(s3[0]),
.c(s3[1]),
.sum(y[2]),
.car(c4[2])
);
// Level 4
tri_csa32 csa_l4_0(
.vd(vdd),
.gd(gnd),
.a(c4[0]),
.b(c4[1]),
.c(c4[2]),
.sum(y[1]),
.car(y[0])
);
endmodule |
module tri_lcbs(
vd,
gd,
delay_lclkr,
nclk,
force_t,
thold_b,
dclk,
lclk
);
inout vd;
inout gd;
input delay_lclkr;
input[0:`NCLK_WIDTH-1] nclk;
input force_t;
input thold_b;
output dclk;
output[0:`NCLK_WIDTH-1] lclk;
// tri_lcbs
(* analysis_not_referenced="true" *)
wire unused;
assign unused = vd | gd | delay_lclkr | force_t;
// No scan chain in this methodology
assign dclk = thold_b;
assign lclk = nclk;
endmodule |
module tri_128x34_4w_1r1w(
gnd,
vdd,
vcs,
nclk,
rd_act,
wr_act,
sg_0,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
func_sl_thold_0_b,
func_force,
clkoff_dc_b,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
delay_lclkr_dc,
wr_abst_act,
rd0_abst_act,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
abist_rd0_adr,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
abst_scan_in,
time_scan_in,
repr_scan_in,
func_scan_in,
abst_scan_out,
time_scan_out,
repr_scan_out,
func_scan_out,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
wr_way,
wr_addr,
data_in,
rd_addr,
data_out
);
parameter addressable_ports = 128; // number of addressable register in this array
parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 34; // bitwidth of ports
parameter ways = 4; // number of ways
// POWER PINS
inout gnd;
inout vdd;
(* analysis_not_referenced="true" *)
inout vcs;
// CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk;
input rd_act;
input wr_act;
input sg_0;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;
input func_sl_thold_0_b;
input func_force;
input clkoff_dc_b;
input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input d_mode_dc;
input [0:4] mpw1_dc_b;
input mpw2_dc_b;
input [0:4] delay_lclkr_dc;
// ABIST
input wr_abst_act;
input rd0_abst_act;
input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:addressbus_width-1] abist_wr_adr;
input [0:addressbus_width-1] abist_rd0_adr;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;
// Scan
input [0:1] abst_scan_in;
input time_scan_in;
input repr_scan_in;
input func_scan_in;
output [0:1] abst_scan_out;
output time_scan_out;
output repr_scan_out;
output func_scan_out;
// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input [0:1] pc_bo_select; // select for mask and hier writes
output [0:1] bo_pc_failout; // fail/no-fix reg
output [0:1] bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;
// Write Ports
input [0:ways-1] wr_way;
input [0:addressbus_width-1] wr_addr;
input [0:port_bitwidth*ways-1] data_in;
// Read Ports
input [0:addressbus_width-1] rd_addr;
output [0:port_bitwidth*ways-1] data_out;
// tri_128x34_4w_1r1w
parameter ramb_base_width = 36;
parameter ramb_base_addr = 9;
parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way
// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
localparam rd_act_offset = 0;
localparam data_out_offset = rd_act_offset + 1;
localparam scan_right = data_out_offset + port_bitwidth*ways - 1;
wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in[0:ways-1];
wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1];
wire [0:ramb_base_addr-1] ramb_rd_addr;
wire [0:ramb_base_addr-1] ramb_wr_addr;
wire rd_act_l2;
wire [0:port_bitwidth*ways-1] data_out_d;
wire [0:port_bitwidth*ways-1] data_out_l2;
wire tidn;
(* analysis_not_referenced="true" *)
wire unused;
wire [31:0] dob;
wire [3:0] dopb;
wire [0:scan_right] func_sov;
generate
begin
assign tidn = 1'b0;
if (addressbus_width < ramb_base_addr)
begin
assign ramb_rd_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
assign ramb_rd_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = rd_addr;
assign ramb_wr_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
assign ramb_wr_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = wr_addr;
end
if (addressbus_width >= ramb_base_addr)
begin
assign ramb_rd_addr = rd_addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
assign ramb_wr_addr = wr_addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
end
genvar w;
for (w = 0; w < ways; w = w + 1)
begin : dw
genvar i;
for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1)
begin : din
if (i < port_bitwidth)
begin
assign ramb_data_in[w][i] = data_in[w * port_bitwidth + i];
end
if (i >= port_bitwidth)
begin
assign ramb_data_in[w][i] = 1'b0;
end
end
end
//genvar w;
for (w = 0; w < ways; w = w + 1)
begin : aw
genvar x;
for (x = 0; x < ramb_width_mult; x = x + 1)
begin : ax
RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
arr(
.DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DOB(dob),
.DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DOPB(dopb),
.ADDRA(ramb_rd_addr),
.ADDRB(ramb_wr_addr),
.CLKA(nclk[0]),
.CLKB(nclk[0]),
.DIA(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DIB(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DIPA(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DIPB(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ENA(rd_act),
.ENB(wr_act),
.SSRA(nclk[1]),
.SSRB(nclk[1]),
.WEA(tidn),
.WEB(wr_way[w])
);
end //ax
assign data_out_d[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
end //aw
end
endgenerate
assign data_out = data_out_l2;
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(1'b1),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(func_force),
.delay_lclkr(delay_lclkr_dc[0]),
.mpw1_b(mpw1_dc_b[0]),
.mpw2_b(mpw2_dc_b),
.d_mode(d_mode_dc),
.scin(1'b0),
.scout(func_sov[rd_act_offset]),
.din(rd_act),
.dout(rd_act_l2)
);
tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rd_act_l2),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(func_force),
.delay_lclkr(delay_lclkr_dc[0]),
.mpw1_b(mpw1_dc_b[0]),
.mpw2_b(mpw2_dc_b),
.d_mode(d_mode_dc),
.scin({port_bitwidth*ways{1'b0}}),
.scout(func_sov[data_out_offset:data_out_offset + (port_bitwidth*ways) - 1]),
.din(data_out_d),
.dout(data_out_l2)
);
assign abst_scan_out = {tidn, tidn};
assign time_scan_out = tidn;
assign repr_scan_out = tidn;
assign func_scan_out = tidn;
assign bo_pc_failout = {tidn, tidn};
assign bo_pc_diagloop = {tidn, tidn};
assign unused = | ({nclk[2:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, dob, dopb, func_sov, ramb_data_out[0][34:35], ramb_data_out[1][34:35], ramb_data_out[2][34:35], ramb_data_out[3][34:35]});
endmodule |
module tri_direct_err_rpt(
vd,
gd,
err_in,
err_out
);
parameter WIDTH = 1; // use to bundle error reporting checkers of the same exact type
inout vd;
inout gd;
input [0:WIDTH-1] err_in;
output [0:WIDTH-1] err_out;
// tri_direct_err_rpt
(* analysis_not_referenced="true" *)
wire unused;
assign unused = vd | gd;
assign err_out = err_in;
endmodule |
module tri_fu_mul(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
f_mul_si,
f_mul_so,
ex2_act,
f_fmt_ex2_a_frac,
f_fmt_ex2_a_frac_17,
f_fmt_ex2_a_frac_35,
f_fmt_ex2_c_frac,
f_mul_ex3_sum,
f_mul_ex3_car
);
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input delay_lclkr; // tidn,
input mpw1_b; // tidn,
input mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input f_mul_si; //perv
output f_mul_so; //perv
input ex2_act; //act
input [0:52] f_fmt_ex2_a_frac; // implicit bit already generated
input f_fmt_ex2_a_frac_17; // new port for replicated bit
input f_fmt_ex2_a_frac_35; // new port for replicated bit
input [0:53] f_fmt_ex2_c_frac; // implicit bit already generated
output [1:108] f_mul_ex3_sum;
output [1:108] f_mul_ex3_car;
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire thold_0_b;
wire thold_0;
wire force_t;
wire sg_0;
wire [0:3] spare_unused;
//--------------------------------------
wire [0:3] act_so; //SCAN
wire [0:3] act_si;
wire m92_0_so;
wire m92_1_so;
wire m92_2_so;
//--------------------------------------
wire [36:108] pp3_05;
wire [35:108] pp3_04;
wire [18:90] pp3_03;
wire [17:90] pp3_02;
wire [0:72] pp3_01;
wire [0:72] pp3_00;
wire hot_one_msb_unused;
wire hot_one_74;
wire hot_one_92;
wire xtd_unused;
wire [1:108] pp5_00;
wire [1:108] pp5_01;
////################################################################
////# pervasive
////################################################################
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
////################################################################
////# act
////################################################################
tri_rlmreg_p #(.WIDTH(4), .NEEDS_SRESET(0)) act_lat(
.force_t(force_t), //i-- tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr), //i-- tidn,
.mpw1_b(mpw1_b), //i-- tidn,
.mpw2_b(mpw2_b), //i-- tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(fpu_enable),
.thold_b(thold_0_b),
.sg(sg_0),
.scout(act_so),
.scin(act_si),
//-----------------
.din({ spare_unused[0],
spare_unused[1],
spare_unused[2],
spare_unused[3]}),
//-----------------
.dout({spare_unused[0],
spare_unused[1],
spare_unused[2],
spare_unused[3]})
);
assign act_si[0:3] = {act_so[1:3], m92_2_so};
assign f_mul_so = act_so[0];
////################################################################
////# ex2 logic
////################################################################
////# NUMBERING SYSTEM RELATIVE TO COMPRESSOR TREE
////#
////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111
////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000
////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
////# 0 ..DdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................................................
////# 1 ..1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................................
////# 2 ....1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............................................
////# 3 ......1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................................
////# 4 ........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........................................
////# 5 ..........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................................
////# 6 ............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......................................
////# 7 ..............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....................................
////# 8 ................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................................
////# 9 ..................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................
////# 10 ....................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............................
////# 11 ......................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................
////# 12 ........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........................
////# 13 ..........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................
////# 14 ............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......................
////# 15 ..............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....................
////# 16 ................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................
////# 17 ..................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................
////# 18 ....................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............
////# 19 ......................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............
////# 20 ........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........
////# 21 ..........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........
////# 22 ............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......
////# 23 ..............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....
////# 24 ................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..
////# 25 ..................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s
////# 26 ...................................................assDdddddddddddddddddddddddddddddddddddddddddddddddddddddD
tri_fu_mul_92 #(.inst(2)) m92_2(
.vdd(vdd), //i--
.gnd(gnd), //i--
.nclk(nclk), //i--
.force_t(force_t), //i--
.lcb_delay_lclkr(delay_lclkr), //i-- tidn
.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
.lcb_mpw2_b(mpw2_b), //i-- mpw2_b others=0
.thold_b(thold_0_b), //i--
.lcb_sg(sg_0), //i--
.si(f_mul_si), //i--
.so(m92_0_so), //o--
.ex2_act(ex2_act), //i--
//--------------------
.c_frac(f_fmt_ex2_c_frac[0:53]), //i-- Multiplicand (shift me)
.a_frac({f_fmt_ex2_a_frac[35:52], //i-- Multiplier (recode me)
tidn}), //i-- Multiplier (recode me)
.hot_one_out(hot_one_92), //o--
.sum92(pp3_05[36:108]), //o--
.car92(pp3_04[35:108]) //o--
);
tri_fu_mul_92 #(.inst(1)) m92_1(
.vdd(vdd), //i--
.gnd(gnd), //i--
.nclk(nclk), //i--
.force_t(force_t), //i--
.lcb_delay_lclkr(delay_lclkr), //i-- tidn
.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
.lcb_mpw2_b(mpw2_b), //i-- mpw2_b others=0
.thold_b(thold_0_b), //i--
.lcb_sg(sg_0), //i--
.si(m92_0_so), //i--
.so(m92_1_so), //o-- v
.ex2_act(ex2_act), //i--
//-------------------
.c_frac(f_fmt_ex2_c_frac[0:53]), //i-- Multiplicand (shift me)
.a_frac({f_fmt_ex2_a_frac[17:34], //i-- Multiplier (recode me)
f_fmt_ex2_a_frac_35}), //i-- Multiplier (recode me)
.hot_one_out(hot_one_74), //o--
.sum92(pp3_03[18:90]), //o--
.car92(pp3_02[17:90]) //o--
);
tri_fu_mul_92 #(.inst(0)) m92_0(
.vdd(vdd), //i--
.gnd(gnd), //i--
.nclk(nclk), //i--
.force_t(force_t), //i--
.lcb_delay_lclkr(delay_lclkr), //i-- tidn
.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
.lcb_mpw2_b(mpw2_b), //i-- mpw2_b others=0
.thold_b(thold_0_b), //i--
.lcb_sg(sg_0), //i--
.si(m92_1_so), //i--
.so(m92_2_so), //o--
.ex2_act(ex2_act), //i--
//-------------------
.c_frac(f_fmt_ex2_c_frac[0:53]), //i-- Multiplicand (shift me)
.a_frac({tidn, //i-- Multiplier (recode me)
f_fmt_ex2_a_frac[0:16], //i-- Multiplier (recode me)
f_fmt_ex2_a_frac_17}), //i-- Multiplier (recode me)
.hot_one_out(hot_one_msb_unused), //o--
.sum92(pp3_01[0:72]), //o--
.car92({xtd_unused, //o--
pp3_00[0:72]}) //o--
);
////##################################################
////# Compressor Level 4 , 5
////##################################################
tri_fu_mul_62 m62(
.vdd(vdd),
.gnd(gnd),
.hot_one_92(hot_one_92), //i--
.hot_one_74(hot_one_74), //i--
.pp3_05(pp3_05[36:108]), //i--
.pp3_04(pp3_04[35:108]), //i--
.pp3_03(pp3_03[18:90]), //i--
.pp3_02(pp3_02[17:90]), //i--
.pp3_01(pp3_01[0:72]), //i--
.pp3_00(pp3_00[0:72]), //i--
.sum62(pp5_01[1:108]), //o--
.car62(pp5_00[1:108]) //o--
);
////################################################################
////# ex3 logic
////################################################################
assign f_mul_ex3_sum[1:108] = pp5_01[1:108]; //output
assign f_mul_ex3_car[1:108] = pp5_00[1:108]; //output
endmodule |
module tri_err_rpt(
vd,
gd,
err_d1clk,
err_d2clk,
err_lclk,
err_scan_in,
err_scan_out,
mode_dclk,
mode_lclk,
mode_scan_in,
mode_scan_out,
err_in,
err_out,
hold_out,
mask_out
);
parameter WIDTH = 1; // number of errors of the same type
parameter MASK_RESET_VALUE = 1'b0; // use to set default/flush value for mask bits
parameter INLINE = 1'b0; // make hold latch be inline; err_out is sticky -- default to shadow
parameter SHARE_MASK = 1'b0; // PERMISSION NEEDED for true
// used for WIDTH >1 to reduce area of mask (common error disable)
parameter USE_NLATS = 1'b0; // only necessary in standby area to be able to reset to init value
parameter NEEDS_SRESET = 1; // for inferred latches
inout vd;
inout gd;
input err_d1clk; // caution1: if lcb uses powersavings, errors must always get reported
input err_d2clk; // caution2: if use_nlats is used these are also the clocks for the mask latches
input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks
// caution2: and all bits in the "func" chain have to be connected to the mode chain
// error scan chain (func or mode)
input [0:WIDTH-1] err_scan_in; // NOTE: connected to mode or func ring
output [0:WIDTH-1] err_scan_out;
// clock gateable mode clocks
input mode_dclk;
input [0:`NCLK_WIDTH-1] mode_lclk;
// mode scan chain
input [0:WIDTH-1] mode_scan_in;
output [0:WIDTH-1] mode_scan_out;
input [0:WIDTH-1] err_in;
output [0:WIDTH-1] err_out;
output [0:WIDTH-1] hold_out; // sticky error hold latch for trap usage
output [0:WIDTH-1] mask_out;
// tri_err_rpt
parameter [0:WIDTH-1] mask_initv = MASK_RESET_VALUE;
wire [0:WIDTH-1] hold_in;
wire [0:WIDTH-1] hold_lt;
wire [0:WIDTH-1] mask_lt;
(* analysis_not_referenced="true" *)
wire unused;
wire [0:WIDTH-1] unused_q_b;
// hold latches
assign hold_in = err_in | hold_lt;
tri_nlat_scan #(.WIDTH(WIDTH), .NEEDS_SRESET(NEEDS_SRESET))
hold(
.vd(vd),
.gd(gd),
.d1clk(err_d1clk),
.d2clk(err_d2clk),
.lclk(err_lclk),
.scan_in(err_scan_in[0:WIDTH - 1]),
.scan_out(err_scan_out[0:WIDTH - 1]),
.din(hold_in),
.q(hold_lt),
.q_b(unused_q_b)
);
generate
begin
// mask
if (SHARE_MASK == 1'b0)
begin : m
assign mask_lt = mask_initv;
end
if (SHARE_MASK == 1'b1)
begin : sm
assign mask_lt = {WIDTH{MASK_RESET_VALUE[0]}};
end
assign mode_scan_out = {WIDTH{1'b0}};
// assign outputs
assign hold_out = hold_lt;
assign mask_out = mask_lt;
if (INLINE == 1'b1)
begin : inline_hold
assign err_out = hold_lt & (~mask_lt);
end
if (INLINE == 1'b0)
begin : side_hold
assign err_out = err_in & (~mask_lt);
end
assign unused = | {mode_dclk, mode_lclk, mode_scan_in, unused_q_b};
end
endgenerate
endmodule |
module tri_nor2(
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "NOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
// tri_nor2
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
nor I0(y[i], a[i], b[i]);
end // block: w
end
endgenerate
endmodule |
module tri_addrcmp(
enable_lsb,
d0,
d1,
eq
);
input enable_lsb; // when "0" the LSB is disabled
input [0:35] d0;
input [0:35] d1;
output eq;
// tri_addrcmp
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:35] eq01_b;
wire [0:18] eq02;
wire [0:9] eq04_b;
wire [0:4] eq08;
wire [0:1] eq24_b;
assign eq01_b[0:35] = (d0[0:35] ^ d1[0:35]);
assign eq02[0] = (~(eq01_b[0] | eq01_b[1]));
assign eq02[1] = (~(eq01_b[2] | eq01_b[3]));
assign eq02[2] = (~(eq01_b[4] | eq01_b[5]));
assign eq02[3] = (~(eq01_b[6] | eq01_b[7]));
assign eq02[4] = (~(eq01_b[8] | eq01_b[9]));
assign eq02[5] = (~(eq01_b[10] | eq01_b[11]));
assign eq02[6] = (~(eq01_b[12] | eq01_b[13]));
assign eq02[7] = (~(eq01_b[14] | eq01_b[15]));
assign eq02[8] = (~(eq01_b[16] | eq01_b[17]));
assign eq02[9] = (~(eq01_b[18] | eq01_b[19]));
assign eq02[10] = (~(eq01_b[20] | eq01_b[21]));
assign eq02[11] = (~(eq01_b[22] | eq01_b[23]));
assign eq02[12] = (~(eq01_b[24] | eq01_b[25]));
assign eq02[13] = (~(eq01_b[26] | eq01_b[27]));
assign eq02[14] = (~(eq01_b[28] | eq01_b[29]));
assign eq02[15] = (~(eq01_b[30] | eq01_b[31]));
assign eq02[16] = (~(eq01_b[32] | eq01_b[33]));
assign eq02[17] = (~(eq01_b[34]));
assign eq02[18] = (~(eq01_b[35] & enable_lsb));
assign eq04_b[0] = (~(eq02[0] & eq02[1]));
assign eq04_b[1] = (~(eq02[2] & eq02[3]));
assign eq04_b[2] = (~(eq02[4] & eq02[5]));
assign eq04_b[3] = (~(eq02[6] & eq02[7]));
assign eq04_b[4] = (~(eq02[8] & eq02[9]));
assign eq04_b[5] = (~(eq02[10] & eq02[11]));
assign eq04_b[6] = (~(eq02[12] & eq02[13]));
assign eq04_b[7] = (~(eq02[14] & eq02[15]));
assign eq04_b[8] = (~(eq02[16] & eq02[17]));
assign eq04_b[9] = (~(eq02[18]));
assign eq08[0] = (~(eq04_b[0] | eq04_b[1]));
assign eq08[1] = (~(eq04_b[2] | eq04_b[3]));
assign eq08[2] = (~(eq04_b[4] | eq04_b[5]));
assign eq08[3] = (~(eq04_b[6] | eq04_b[7]));
assign eq08[4] = (~(eq04_b[8] | eq04_b[9]));
assign eq24_b[0] = (~(eq08[0] & eq08[1] & eq08[2]));
assign eq24_b[1] = (~(eq08[3] & eq08[4]));
assign eq = (~(eq24_b[0] | eq24_b[1])); // output
endmodule |
module tri_128x168_1w_0(
gnd,
vdd,
vcs,
nclk,
act,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
abst_scan_in,
repr_scan_in,
time_scan_in,
abst_scan_out,
repr_scan_out,
time_scan_out,
lcb_d_mode_dc,
lcb_clkoff_dc_b,
lcb_act_dis_dc,
lcb_mpw1_dc_b,
lcb_mpw2_dc_b,
lcb_delay_lclkr_dc,
lcb_sg_1,
lcb_time_sg_0,
lcb_repr_sg_0,
lcb_abst_sl_thold_0,
lcb_repr_sl_thold_0,
lcb_time_sl_thold_0,
lcb_ary_nsl_thold_0,
lcb_bolt_sl_thold_0,
tc_lbist_ary_wrt_thru_dc,
abist_en_1,
din_abist,
abist_cmp_en,
abist_raw_b_dc,
data_cmp_abist,
addr_abist,
r_wb_abist,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
write_enable,
addr,
data_in,
data_out
);
parameter addressable_ports = 128; // number of addressable register in this array
parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 168; // bitwidth of ports
parameter ways = 1; // number of ways
// POWER PINS
inout gnd;
inout vdd;
inout vcs;
// CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk;
input act;
input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input abst_scan_in;
input repr_scan_in;
input time_scan_in;
output abst_scan_out;
output repr_scan_out;
output time_scan_out;
input lcb_d_mode_dc;
input lcb_clkoff_dc_b;
input lcb_act_dis_dc;
input [0:4] lcb_mpw1_dc_b;
input lcb_mpw2_dc_b;
input [0:4] lcb_delay_lclkr_dc;
input lcb_sg_1;
input lcb_time_sg_0;
input lcb_repr_sg_0;
input lcb_abst_sl_thold_0;
input lcb_repr_sl_thold_0;
input lcb_time_sl_thold_0;
input lcb_ary_nsl_thold_0;
input lcb_bolt_sl_thold_0; // thold for any regs inside backend
input tc_lbist_ary_wrt_thru_dc;
input abist_en_1;
input [0:3] din_abist;
input abist_cmp_en;
input abist_raw_b_dc;
input [0:3] data_cmp_abist;
input [0:6] addr_abist;
input r_wb_abist;
// BOLT-ON
input pc_bo_enable_2; // general bolt-on enable, probably DC
input pc_bo_reset; // execute sticky bit decode
input pc_bo_unload;
input pc_bo_repair; // load repair reg
input pc_bo_shdata; // shift data for timing write
input pc_bo_select; // select for mask and hier writes
output bo_pc_failout; // fail/no-fix reg
output bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;
// PORTS
input write_enable;
input [0:addressbus_width-1] addr;
input [0:port_bitwidth-1] data_in;
output [0:port_bitwidth-1] data_out;
// tri_128x168_1w_0
parameter ramb_base_width = 36;
parameter ramb_base_addr = 9;
parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way
// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in;
wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1];
wire [0:ramb_base_addr-1] ramb_addr;
wire [0:ways-1] write;
wire tidn;
(* analysis_not_referenced="true" *)
wire unused;
wire [0:(ramb_base_width*ramb_width_mult-1)] unused_dob;
generate
begin
assign tidn = 1'b0;
if (addressbus_width < ramb_base_addr)
begin
assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr;
end
if (addressbus_width >= ramb_base_addr)
begin
assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
end
genvar i;
for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1)
begin : din
if (i < port_bitwidth)
begin
assign ramb_data_in[i] = data_in[i];
end
if (i >= port_bitwidth)
begin
assign ramb_data_in[i] = 1'b0;
end
end
genvar w;
for (w = 0; w < ways; w = w + 1)
begin : aw
assign write[w] = write_enable;
genvar x;
for (x = 0; x < ramb_width_mult; x = x + 1)
begin : ax
RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
ram(
.DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DOB(unused_dob[x * ramb_base_width:x * ramb_base_width + 31]),
.DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ADDRA(ramb_addr),
.ADDRB(ramb_addr),
.CLKA(nclk[0]),
.CLKB(tidn),
.DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
.DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
.DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ENA(act),
.ENB(tidn),
.SSRA(nclk[1]),
.SSRB(tidn),
.WEA(write[w]),
.WEB(tidn)
);
end //ax
assign data_out[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
end //aw
end
endgenerate
assign abst_scan_out = abst_scan_in;
assign repr_scan_out = repr_scan_in;
assign time_scan_out = time_scan_in;
assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0;
assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, nclk, unused_dob});
endmodule |
module tri_inv_nlats(
vd,
gd,
lclk,
d1clk,
d2clk,
scanin,
scanout,
d,
qb
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "NLI0001_X1_A12TH";
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] lclk;
input d1clk;
input d2clk;
input [OFFSET:OFFSET+WIDTH-1] scanin;
output [OFFSET:OFFSET+WIDTH-1] scanout;
input [OFFSET:OFFSET+WIDTH-1] d;
output [OFFSET:OFFSET+WIDTH-1] qb;
// tri_inv_nlats
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
wire [0:WIDTH-1] din;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign din = d; // Output is inverted, so don't invert here
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{d1clk}};
assign vact_b = {WIDTH{~d1clk}};
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};
always @(posedge lclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign qb = (~int_dout);
assign scanout = ZEROS;
assign unused = | {vd, gd, lclk, scanin};
end
endgenerate
endmodule |
module tri_bthmx(x, sneg, sx, sx2, right, left, q, vd, gd);
input x;
input sneg;
input sx;
input sx2;
input right;
output left;
output q;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout gd;
wire center, xn, spos;
assign xn = ~x;
assign spos = ~sneg;
assign center = ~(( xn & spos ) |
( x & sneg ));
assign left = center; // output
assign q = ( center & sx ) |
( right & sx2 ) ;
endmodule |
module tri_64x72_1r1w(
vdd,
vcs,
gnd,
nclk,
sg_0,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
rd0_act,
rd0_adr,
do0,
wr_act,
wr_adr,
di,
abst_scan_in,
abst_scan_out,
time_scan_in,
time_scan_out,
repr_scan_in,
repr_scan_out,
scan_dis_dc_b,
scan_diag_dc,
ccflush_dc,
clkoff_dc_b,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
delay_lclkr_dc,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
wr_abst_act,
abist_rd0_adr,
rd0_abst_act,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp
);
// Power
(* analysis_not_referenced="true" *)
inout vdd;
(* analysis_not_referenced="true" *)
inout vcs;
(* analysis_not_referenced="true" *)
inout gnd;
// Clock Pervasive
input [0:`NCLK_WIDTH-1] nclk;
input sg_0;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;
// Reads
input rd0_act;
input [0:5] rd0_adr;
output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0;
// Writes
input wr_act;
input [0:5] wr_adr;
input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] di;
// Scan
input abst_scan_in;
output abst_scan_out;
input time_scan_in;
output time_scan_out;
input repr_scan_in;
output repr_scan_out;
// Misc Pervasive
input scan_dis_dc_b;
input scan_diag_dc;
input ccflush_dc;
input clkoff_dc_b;
input d_mode_dc;
input [0:4] mpw1_dc_b;
input mpw2_dc_b;
input [0:4] delay_lclkr_dc;
// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input pc_bo_select; // select for mask and hier writes
output bo_pc_failout; // fail/no-fix reg
output bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;
// ABIST
input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:5] abist_wr_adr;
input wr_abst_act;
input [0:5] abist_rd0_adr;
input rd0_abst_act;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;
// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
wire clk;
wire clk2x;
reg [0:8] addra;
reg [0:8] addrb;
reg wea;
reg web;
wire [0:71] bdo;
wire [0:71] bdi;
wire sreset;
wire [0:71] tidn;
// Latches
reg reset_q;
reg gate_fq;
wire gate_d;
wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] bdo_d;
reg [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] bdo_fq;
wire toggle_d;
reg toggle_q;
wire toggle2x_d;
reg toggle2x_q;
(* analysis_not_referenced="true" *)
wire unused;
generate
begin
assign tidn = 72'b0;
assign clk = nclk[0];
assign clk2x = nclk[2];
assign sreset = nclk[1];
always @(posedge clk)
begin: rlatch
reset_q <= #10 sreset;
end
//
// NEW clk2x gate logic start
//
always @(posedge clk)
begin: tlatch
if (reset_q == 1'b1)
toggle_q <= 1'b1;
else
toggle_q <= toggle_d;
end
always @(posedge clk2x)
begin: flatch
toggle2x_q <= toggle2x_d;
gate_fq <= gate_d;
bdo_fq <= bdo_d;
end
assign toggle_d = (~toggle_q);
assign toggle2x_d = toggle_q;
// should force gate_fq to be on during odd 2x clock (second half of 1x clock).
//gate_d <= toggle_q xor toggle2x_q;
// if you want the first half do the following
assign gate_d = (~(toggle_q ^ toggle2x_q));
//
// NEW clk2x gate logic end
//
if (`GPR_WIDTH == 32)
begin
assign bdi = {tidn[0:31], di[32:63], di[64:70], tidn[71]};
end
if (`GPR_WIDTH == 64)
begin
assign bdi = di[0:71];
end
assign bdo_d = bdo[64 - `GPR_WIDTH:72 - (64/`GPR_WIDTH)];
assign do0 = bdo_fq;
always @ ( * )
begin
wea <= #10 (wr_act & gate_fq);
web <= #10 (wr_act & gate_fq);
addra <= #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} :
{2'b00, rd0_adr, 1'b0});
addrb <= #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} :
{2'b00, rd0_adr, 1'b1});
end
RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
bram0a(
.CLKA(clk2x),
.CLKB(clk2x),
.SSRA(sreset),
.SSRB(sreset),
.ADDRA(addra),
.ADDRB(addrb),
.DIA(bdi[00:31]),
.DIB(bdi[32:63]),
.DIPA(bdi[64:67]),
.DIPB(bdi[68:71]),
.DOA(bdo[00:31]),
.DOB(bdo[32:63]),
.DOPA(bdo[64:67]),
.DOPB(bdo[68:71]),
.ENA(1'b1),
.ENB(1'b1),
.WEA(wea),
.WEB(web)
);
assign abst_scan_out = abst_scan_in;
assign time_scan_out = time_scan_in;
assign repr_scan_out = repr_scan_in;
assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0;
assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});
end
endgenerate
endmodule |
module tri_st_add(
x_b,
y_b,
ci,
sum,
cout_32,
cout_0
);
input [0:63] x_b; // after xor
input [0:63] y_b;
input ci;
output [0:63] sum;
output cout_32;
output cout_0;
wire [0:63] g01;
wire [0:63] g01_b;
wire [0:63] t01;
wire [0:63] t01_b;
wire [0:63] sum_0;
wire [0:63] sum_1;
wire [0:7] g08;
wire [0:7] t08;
wire [0:7] c64_b;
wire cout_32x;
wire cout_32y_b;
wire ci_cp1_lv1_b;
wire ci_cp1_lv2;
wire ci_cp1_lv3_b;
wire ci_cp1_lv4;
wire ci_cp2_lv2;
wire ci_cp2_lv3_b;
assign ci_cp1_lv1_b = (~ci); // x2
assign ci_cp1_lv2 = (~ci_cp1_lv1_b); // x2
assign ci_cp1_lv3_b = (~ci_cp1_lv2); // x3
assign ci_cp1_lv4 = (~ci_cp1_lv3_b); // x4
assign ci_cp2_lv2 = (~ci_cp1_lv1_b); // x2
assign ci_cp2_lv3_b = (~ci_cp2_lv2); // x3
////##################################################
////## pgt
////##################################################
// extra logic on [63] is performance penalty to agen (dont need ci ).
// ci*x + ci*y + xy
// x(ci + y) + (ci * y )
assign g01[0:63] = (~(x_b[0:63] | y_b[0:63]));
assign t01[0:63] = (~(x_b[0:63] & y_b[0:63]));
assign g01_b[0:63] = (~g01[0:63]); // small, buffer off
assign t01_b[0:63] = (~t01[0:63]); // small, buffer off
////##################################################
////## local part of byte group
////##################################################
tri_st_add_loc loc_0(
.g01_b(g01_b[0:7]), //i--
.t01_b(t01_b[0:7]), //i--
.sum_0(sum_0[0:7]), //o--
.sum_1(sum_1[0:7]) //o--
);
tri_st_add_loc loc_1(
.g01_b(g01_b[8:15]), //i--
.t01_b(t01_b[8:15]), //i--
.sum_0(sum_0[8:15]), //o--
.sum_1(sum_1[8:15]) //o--
);
tri_st_add_loc loc_2(
.g01_b(g01_b[16:23]), //i--
.t01_b(t01_b[16:23]), //i--
.sum_0(sum_0[16:23]), //o--
.sum_1(sum_1[16:23]) //o--
);
tri_st_add_loc loc_3(
.g01_b(g01_b[24:31]), //i--
.t01_b(t01_b[24:31]), //i--
.sum_0(sum_0[24:31]), //o--
.sum_1(sum_1[24:31]) //o--
);
tri_st_add_loc loc_4(
.g01_b(g01_b[32:39]), //i--
.t01_b(t01_b[32:39]), //i--
.sum_0(sum_0[32:39]), //o--
.sum_1(sum_1[32:39]) //o--
);
tri_st_add_loc loc_5(
.g01_b(g01_b[40:47]), //i--
.t01_b(t01_b[40:47]), //i--
.sum_0(sum_0[40:47]), //o--
.sum_1(sum_1[40:47]) //o--
);
tri_st_add_loc loc_6(
.g01_b(g01_b[48:55]), //i--
.t01_b(t01_b[48:55]), //i--
.sum_0(sum_0[48:55]), //o--
.sum_1(sum_1[48:55]) //o--
);
tri_st_add_loc loc_7(
.g01_b(g01_b[56:63]), //i--
.t01_b(t01_b[56:63]), //i--
.sum_0(sum_0[56:63]), //o--
.sum_1(sum_1[56:63]) //o--
);
////##################################################
////## local part of global carry
////##################################################
tri_st_add_glbloc gclc_0(
.g01(g01[0:7]), //i--
.t01(t01[0:7]), //i--
.g08(g08[0]), //o--
.t08(t08[0]) //o--
);
tri_st_add_glbloc gclc_1(
.g01(g01[8:15]), //i--
.t01(t01[8:15]), //i--
.g08(g08[1]), //o--
.t08(t08[1]) //o--
);
tri_st_add_glbloc gclc_2(
.g01(g01[16:23]), //i--
.t01(t01[16:23]), //i--
.g08(g08[2]), //o--
.t08(t08[2]) //o--
);
tri_st_add_glbloc gclc_3(
.g01(g01[24:31]), //i--
.t01(t01[24:31]), //i--
.g08(g08[3]), //o--
.t08(t08[3]) //o--
);
tri_st_add_glbloc gclc_4(
.g01(g01[32:39]), //i--
.t01(t01[32:39]), //i--
.g08(g08[4]), //o--
.t08(t08[4]) //o--
);
tri_st_add_glbloc gclc_5(
.g01(g01[40:47]), //i--
.t01(t01[40:47]), //i--
.g08(g08[5]), //o--
.t08(t08[5]) //o--
);
tri_st_add_glbloc gclc_6(
.g01(g01[48:55]), //i--
.t01(t01[48:55]), //i--
.g08(g08[6]), //o--
.t08(t08[6]) //o--
);
tri_st_add_glbloc gclc_7(
.g01(g01[56:63]), //i--
.t01(t01[56:63]), //i--
.g08(g08[7]), //o--
.t08(t08[7]) //o--
);
////##################################################
////## global part of global carry
////##################################################
tri_st_add_glbglbci gc(
.g08(g08[0:7]), //i--
.t08(t08[0:7]), //i--
.ci(ci_cp1_lv4), //i--
.c64_b(c64_b[0:7]) //o--
);
assign cout_32x = (~c64_b[4]); //(small)
assign cout_32y_b = (~cout_32x);
assign cout_32 = (~cout_32y_b); //output--
assign cout_0 = (~c64_b[0]); //output-- --rename--
////##################################################
////## final mux
////##################################################
tri_st_add_csmux fm_0(
.ci_b(c64_b[1]), //i--
.sum_0(sum_0[0:7]), //i--
.sum_1(sum_1[0:7]), //i--
.sum(sum[0:7]) //o--
);
tri_st_add_csmux fm_1(
.ci_b(c64_b[2]), //i--
.sum_0(sum_0[8:15]), //i--
.sum_1(sum_1[8:15]), //i--
.sum(sum[8:15]) //o--
);
tri_st_add_csmux fm_2(
.ci_b(c64_b[3]), //i--
.sum_0(sum_0[16:23]), //i--
.sum_1(sum_1[16:23]), //i--
.sum(sum[16:23]) //o--
);
tri_st_add_csmux fm_3(
.ci_b(c64_b[4]), //i--
.sum_0(sum_0[24:31]), //i--
.sum_1(sum_1[24:31]), //i--
.sum(sum[24:31]) //o--
);
tri_st_add_csmux fm_4(
.ci_b(c64_b[5]), //i--
.sum_0(sum_0[32:39]), //i--
.sum_1(sum_1[32:39]), //i--
.sum(sum[32:39]) //o--
);
tri_st_add_csmux fm_5(
.ci_b(c64_b[6]), //i--
.sum_0(sum_0[40:47]), //i--
.sum_1(sum_1[40:47]), //i--
.sum(sum[40:47]) //o--
);
tri_st_add_csmux fm_6(
.ci_b(c64_b[7]), //i--
.sum_0(sum_0[48:55]), //i--
.sum_1(sum_1[48:55]), //i--
.sum(sum[48:55]) //o--
);
tri_st_add_csmux fm_7(
.ci_b(ci_cp2_lv3_b), //i--
.sum_0(sum_0[56:63]), //i--
.sum_1(sum_1[56:63]), //i--
.sum(sum[56:63]) //o--
);
endmodule |
module tri_ser_rlmreg_p(
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter WIDTH = 1;
parameter OFFSET = 0;
parameter INIT = 0;
parameter IBUF = 1'b0;
parameter DUALSCAN = "";
parameter NEEDS_SRESET = 1;
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input act;
input force_t;
input thold_b;
input d_mode;
input sg;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input [OFFSET:OFFSET+WIDTH-1] scin;
input [OFFSET:OFFSET+WIDTH-1] din;
output [OFFSET:OFFSET+WIDTH-1] scout;
output [OFFSET:OFFSET+WIDTH-1] dout;
// tri_ser_rlmreg_p
wire [OFFSET:OFFSET+WIDTH-1] dout_b;
wire [OFFSET:OFFSET+WIDTH-1] act_buf;
wire [OFFSET:OFFSET+WIDTH-1] act_buf_b;
wire [OFFSET:OFFSET+WIDTH-1] dout_buf;
assign act_buf = {WIDTH{act}};
assign act_buf_b = {WIDTH{~(act)}};
assign dout_buf = (~dout_b);
assign dout = dout_buf;
tri_aoi22_nlats_wlcb #(.WIDTH(WIDTH), .OFFSET(OFFSET), .INIT(INIT), .IBUF(IBUF), .DUALSCAN(DUALSCAN), .NEEDS_SRESET(NEEDS_SRESET)) tri_ser_rlmreg_p(
.nclk(nclk),
.vd(vd),
.gd(gd),
.act(act),
.force_t(force_t),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.thold_b(thold_b),
.sg(sg),
.scin(scin),
.scout(scout),
.a1(din),
.a2(act_buf),
.b1(dout_buf),
.b2(act_buf_b),
.qb(dout_b)
);
endmodule |
module tri_fu_mul_bthrow(
x,
s_neg,
s_x,
s_x2,
hot_one,
q
);
input [0:53] x;
input s_neg; // negate the row
input s_x; // shift by 1
input s_x2; // shift by 2
output hot_one; // lsb term for row below
output [0:54] q; // final output
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:54] left;
wire unused;
assign unused = left[0]; // dangling pin from edge bit
////###############################################################
//# A row of the repeated part of the booth_mux row
////###############################################################
tri_fu_mul_bthmux u00(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(tidn), //i-- ********
.right(left[1]), //i-- [n+1]
.left(left[0]), //o-- [n]
.q(q[0]) //o--
);
tri_fu_mul_bthmux u01(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[0]), //i-- [n-1]
.right(left[2]), //i-- [n+1]
.left(left[1]), //o-- [n]
.q(q[1]) //o--
);
tri_fu_mul_bthmux u02(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[1]), //i--
.right(left[3]), //i--
.left(left[2]), //o--
.q(q[2]) //o--
);
tri_fu_mul_bthmux u03(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[2]), //i--
.right(left[4]), //i--
.left(left[3]), //o--
.q(q[3]) //o--
);
tri_fu_mul_bthmux u04(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[3]), //i--
.right(left[5]), //i--
.left(left[4]), //o--
.q(q[4]) //o--
);
tri_fu_mul_bthmux u05(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[4]), //i--
.right(left[6]), //i--
.left(left[5]), //o--
.q(q[5]) //o--
);
tri_fu_mul_bthmux u06(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[5]), //i--
.right(left[7]), //i--
.left(left[6]), //o--
.q(q[6]) //o--
);
tri_fu_mul_bthmux u07(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[6]), //i--
.right(left[8]), //i--
.left(left[7]), //o--
.q(q[7]) //o--
);
tri_fu_mul_bthmux u08(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[7]), //i--
.right(left[9]), //i--
.left(left[8]), //o--
.q(q[8]) //o--
);
tri_fu_mul_bthmux u09(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[8]), //i--
.right(left[10]), //i--
.left(left[9]), //o--
.q(q[9]) //o--
);
tri_fu_mul_bthmux u10(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[9]), //i--
.right(left[11]), //i--
.left(left[10]), //o--
.q(q[10]) //o--
);
tri_fu_mul_bthmux u11(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[10]), //i--
.right(left[12]), //i--
.left(left[11]), //o--
.q(q[11]) //o--
);
tri_fu_mul_bthmux u12(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[11]), //i--
.right(left[13]), //i--
.left(left[12]), //o--
.q(q[12]) //o--
);
tri_fu_mul_bthmux u13(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[12]), //i--
.right(left[14]), //i--
.left(left[13]), //o--
.q(q[13]) //o--
);
tri_fu_mul_bthmux u14(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[13]), //i--
.right(left[15]), //i--
.left(left[14]), //o--
.q(q[14]) //o--
);
tri_fu_mul_bthmux u15(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[14]), //i--
.right(left[16]), //i--
.left(left[15]), //o--
.q(q[15]) //o--
);
tri_fu_mul_bthmux u16(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[15]), //i--
.right(left[17]), //i--
.left(left[16]), //o--
.q(q[16]) //o--
);
tri_fu_mul_bthmux u17(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[16]), //i--
.right(left[18]), //i--
.left(left[17]), //o--
.q(q[17]) //o--
);
tri_fu_mul_bthmux u18(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[17]), //i--
.right(left[19]), //i--
.left(left[18]), //o--
.q(q[18]) //o--
);
tri_fu_mul_bthmux u19(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[18]), //i--
.right(left[20]), //i--
.left(left[19]), //o--
.q(q[19]) //o--
);
tri_fu_mul_bthmux u20(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[19]), //i--
.right(left[21]), //i--
.left(left[20]), //o--
.q(q[20]) //o--
);
tri_fu_mul_bthmux u21(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[20]), //i--
.right(left[22]), //i--
.left(left[21]), //o--
.q(q[21]) //o--
);
tri_fu_mul_bthmux u22(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[21]), //i--
.right(left[23]), //i--
.left(left[22]), //o--
.q(q[22]) //o--
);
tri_fu_mul_bthmux u23(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[22]), //i--
.right(left[24]), //i--
.left(left[23]), //o--
.q(q[23]) //o--
);
tri_fu_mul_bthmux u24(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[23]), //i--
.right(left[25]), //i--
.left(left[24]), //o--
.q(q[24]) //o--
);
tri_fu_mul_bthmux u25(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[24]), //i--
.right(left[26]), //i--
.left(left[25]), //o--
.q(q[25]) //o--
);
tri_fu_mul_bthmux u26(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[25]), //i--
.right(left[27]), //i--
.left(left[26]), //o--
.q(q[26]) //o--
);
tri_fu_mul_bthmux u27(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[26]), //i--
.right(left[28]), //i--
.left(left[27]), //o--
.q(q[27]) //o--
);
tri_fu_mul_bthmux u28(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[27]), //i--
.right(left[29]), //i--
.left(left[28]), //o--
.q(q[28]) //o--
);
tri_fu_mul_bthmux u29(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[28]), //i--
.right(left[30]), //i--
.left(left[29]), //o--
.q(q[29]) //o--
);
tri_fu_mul_bthmux u30(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[29]), //i--
.right(left[31]), //i--
.left(left[30]), //o--
.q(q[30]) //o--
);
tri_fu_mul_bthmux u31(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[30]), //i--
.right(left[32]), //i--
.left(left[31]), //o--
.q(q[31]) //o--
);
tri_fu_mul_bthmux u32(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[31]), //i--
.right(left[33]), //i--
.left(left[32]), //o--
.q(q[32]) //o--
);
tri_fu_mul_bthmux u33(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[32]), //i--
.right(left[34]), //i--
.left(left[33]), //o--
.q(q[33]) //o--
);
tri_fu_mul_bthmux u34(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[33]), //i--
.right(left[35]), //i--
.left(left[34]), //o--
.q(q[34]) //o--
);
tri_fu_mul_bthmux u35(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[34]), //i--
.right(left[36]), //i--
.left(left[35]), //o--
.q(q[35]) //o--
);
tri_fu_mul_bthmux u36(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[35]), //i--
.right(left[37]), //i--
.left(left[36]), //o--
.q(q[36]) //o--
);
tri_fu_mul_bthmux u37(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[36]), //i--
.right(left[38]), //i--
.left(left[37]), //o--
.q(q[37]) //o--
);
tri_fu_mul_bthmux u38(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[37]), //i--
.right(left[39]), //i--
.left(left[38]), //o--
.q(q[38]) //o--
);
tri_fu_mul_bthmux u39(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[38]), //i--
.right(left[40]), //i--
.left(left[39]), //o--
.q(q[39]) //o--
);
tri_fu_mul_bthmux u40(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[39]), //i--
.right(left[41]), //i--
.left(left[40]), //o--
.q(q[40]) //o--
);
tri_fu_mul_bthmux u41(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[40]), //i--
.right(left[42]), //i--
.left(left[41]), //o--
.q(q[41]) //o--
);
tri_fu_mul_bthmux u42(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[41]), //i--
.right(left[43]), //i--
.left(left[42]), //o--
.q(q[42]) //o--
);
tri_fu_mul_bthmux u43(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[42]), //i--
.right(left[44]), //i--
.left(left[43]), //o--
.q(q[43]) //o--
);
tri_fu_mul_bthmux u44(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[43]), //i--
.right(left[45]), //i--
.left(left[44]), //o--
.q(q[44]) //o--
);
tri_fu_mul_bthmux u45(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[44]), //i--
.right(left[46]), //i--
.left(left[45]), //o--
.q(q[45]) //o--
);
tri_fu_mul_bthmux u46(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[45]), //i--
.right(left[47]), //i--
.left(left[46]), //o--
.q(q[46]) //o--
);
tri_fu_mul_bthmux u47(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[46]), //i--
.right(left[48]), //i--
.left(left[47]), //o--
.q(q[47]) //o--
);
tri_fu_mul_bthmux u48(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[47]), //i--
.right(left[49]), //i--
.left(left[48]), //o--
.q(q[48]) //o--
);
tri_fu_mul_bthmux u49(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[48]), //i--
.right(left[50]), //i--
.left(left[49]), //o--
.q(q[49]) //o--
);
tri_fu_mul_bthmux u50(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[49]), //i--
.right(left[51]), //i--
.left(left[50]), //o--
.q(q[50]) //o--
);
tri_fu_mul_bthmux u51(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[50]), //i--
.right(left[52]), //i--
.left(left[51]), //o--
.q(q[51]) //o--
);
tri_fu_mul_bthmux u52(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[51]), //i--
.right(left[53]), //i--
.left(left[52]), //o--
.q(q[52]) //o--
);
tri_fu_mul_bthmux u53(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[52]), //i--
.right(left[54]), //i--
.left(left[53]), //o--
.q(q[53]) //o--
);
tri_fu_mul_bthmux u54(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[53]), //i--
.right(s_neg), //i--
.left(left[54]), //o--
.q(q[54]) //o--
);
// For negate -A = !A + 1 ... this term is the plus 1.
// this has same bit weight as LSB, so it jumps down a row to free spot in compressor tree.
assign hot_one = (s_neg & (s_x | s_x2));
endmodule |
module tri_st_cntlz(
dword,
a,
y
);
input dword;
input [0:63] a;
output [0:6] y;
wire [0:23] ys;
wire [0:7] z;
wire [0:7] zh;
wire [0:2] yh;
wire [0:2] yh_sel;
wire zero_b;
assign y[0] = (dword == 1'b1) ? (~zero_b) :
1'b0;
assign y[1] = (dword == 1'b1) ? yh[0] :
(~zero_b);
assign y[2:3] = yh[1:2];
// Force the select to the lower half for word ops
assign yh_sel[0] = yh[0] | (~dword);
assign yh_sel[1:2] = yh[1:2];
// Force the select to be in the lower half for word
assign y[4:6] = (yh_sel[0:2] == 3'b000) ? ys[0:2] :
(yh_sel[0:2] == 3'b001) ? ys[3:5] :
(yh_sel[0:2] == 3'b010) ? ys[6:8] :
(yh_sel[0:2] == 3'b011) ? ys[9:11] :
(yh_sel[0:2] == 3'b100) ? ys[12:14] :
(yh_sel[0:2] == 3'b101) ? ys[15:17] :
(yh_sel[0:2] == 3'b110) ? ys[18:20] :
ys[21:23];
assign zh[0:3] = z[0:3] & {4{dword}};
assign zh[4:7] = z[4:7];
tri_st_cntlz_8b clz_h(
.a(zh[0:7]),
.y(yh[0:2]),
.z_b(zero_b)
);
tri_st_cntlz_8b clz_l0(
.a(a[0:7]),
.y(ys[0:2]),
.z_b(z[0])
);
tri_st_cntlz_8b clz_l1(
.a(a[8:15]),
.y(ys[3:5]),
.z_b(z[1])
);
tri_st_cntlz_8b clz_l2(
.a(a[16:23]),
.y(ys[6:8]),
.z_b(z[2])
);
tri_st_cntlz_8b clz_l3(
.a(a[24:31]),
.y(ys[9:11]),
.z_b(z[3])
);
tri_st_cntlz_8b clz_l4(
.a(a[32:39]),
.y(ys[12:14]),
.z_b(z[4])
);
tri_st_cntlz_8b clz_l5(
.a(a[40:47]),
.y(ys[15:17]),
.z_b(z[5])
);
tri_st_cntlz_8b clz_l6(
.a(a[48:55]),
.y(ys[18:20]),
.z_b(z[6])
);
tri_st_cntlz_8b clz_l7(
.a(a[56:63]),
.y(ys[21:23]),
.z_b(z[7])
);
endmodule |
module tri_slat_scan(
vd,
gd,
dclk,
lclk,
scan_in,
scan_out,
q,
q_b
);
parameter WIDTH = 1;
parameter OFFSET = 0;
parameter INIT = 0;
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "c_slat_scan";
parameter RESET_INVERTS_SCAN = 1'b1;
inout vd;
inout gd;
input dclk;
input [0:`NCLK_WIDTH-1] lclk;
input [OFFSET:OFFSET+WIDTH-1] scan_in;
output [OFFSET:OFFSET+WIDTH-1] scan_out;
output [OFFSET:OFFSET+WIDTH-1] q;
output [OFFSET:OFFSET+WIDTH-1] q_b;
// tri_slat_scan
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
parameter [0:WIDTH-1] initv = INIT;
(* analysis_not_referenced="true" *)
wire unused;
assign unused = | {vd, gd, dclk, lclk, scan_in};
assign scan_out = ZEROS;
assign q = initv;
assign q_b = (~initv);
endmodule |
module tri_agecmp(
a,
b,
a_newer_b
);
parameter SIZE = 8;
input [0:SIZE-1] a;
input [0:SIZE-1] b;
output a_newer_b;
// tri_agecmp
wire a_lt_b;
wire a_gte_b;
wire cmp_sel;
assign a_lt_b = (a[1:SIZE - 1] < b[1:SIZE - 1]) ? 1'b1 :
1'b0;
assign a_gte_b = (~a_lt_b);
assign cmp_sel = a[0] ~^ b[0];
assign a_newer_b = (a_lt_b & (~cmp_sel)) | (a_gte_b & cmp_sel);
endmodule |
module tri_regs(
vd,
gd,
nclk,
force_t,
thold_b,
delay_lclkr,
scin,
scout,
dout
);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter IBUF = 1'b0; //inverted latch IOs, if set to true.
parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock
input delay_lclkr; // 0: functional
input [OFFSET:OFFSET+WIDTH-1] scin; // scan in
output [OFFSET:OFFSET+WIDTH-1] scout;
output [OFFSET:OFFSET+WIDTH-1] dout;
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
// tri_regs
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1)
begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign int_din = (vsreset_b & int_dout) | (vsreset & init_v);
assign vact = {WIDTH{force_t}};
assign vact_b = {WIDTH{~force_t}};
assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}};
always @(posedge nclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
if (IBUF == 1'b1)
begin : cob
assign dout = (~int_dout);
end
if (IBUF == 1'b0)
begin : cnob
assign dout = int_dout;
end
assign scout = ZEROS;
assign unused = | {vd, gd, nclk, delay_lclkr, scin};
end
endgenerate
endmodule |
module fu_add_all1(
ex4_inc_byt_c_b,
ex4_inc_byt_c_glb,
ex4_inc_byt_c_glb_b,
ex4_inc_all1
);
input [0:6] ex4_inc_byt_c_b; // from each byte section
output [1:6] ex4_inc_byt_c_glb;
output [1:6] ex4_inc_byt_c_glb_b;
output ex4_inc_all1;
// ATTRIBUTE BTR_NAME OF fu_add_all1 : ENTITY IS "fu_add_all1";
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:6] ex4_inc_byt_g1;
wire [0:6] ex4_inc_byt_g2_b;
wire [0:6] ex4_inc_byt_g4;
wire [0:6] ex4_inc_byt_g8_b;
wire [1:6] ex4_inc_byt_g_glb_int;
assign ex4_inc_byt_g1[0:6] = (~ex4_inc_byt_c_b[0:6]); //expect some wire distance between latches
// drive to a common location
assign ex4_inc_byt_g2_b[6] = (~(ex4_inc_byt_g1[6]));
assign ex4_inc_byt_g2_b[5] = (~(ex4_inc_byt_g1[5] & ex4_inc_byt_g1[6]));
assign ex4_inc_byt_g2_b[4] = (~(ex4_inc_byt_g1[4] & ex4_inc_byt_g1[5]));
assign ex4_inc_byt_g2_b[3] = (~(ex4_inc_byt_g1[3] & ex4_inc_byt_g1[4]));
assign ex4_inc_byt_g2_b[2] = (~(ex4_inc_byt_g1[2] & ex4_inc_byt_g1[3]));
assign ex4_inc_byt_g2_b[1] = (~(ex4_inc_byt_g1[1] & ex4_inc_byt_g1[2]));
assign ex4_inc_byt_g2_b[0] = (~(ex4_inc_byt_g1[0] & ex4_inc_byt_g1[1]));
assign ex4_inc_byt_g4[6] = (~(ex4_inc_byt_g2_b[6]));
assign ex4_inc_byt_g4[5] = (~(ex4_inc_byt_g2_b[5]));
assign ex4_inc_byt_g4[4] = (~(ex4_inc_byt_g2_b[4] | ex4_inc_byt_g2_b[6]));
assign ex4_inc_byt_g4[3] = (~(ex4_inc_byt_g2_b[3] | ex4_inc_byt_g2_b[5]));
assign ex4_inc_byt_g4[2] = (~(ex4_inc_byt_g2_b[2] | ex4_inc_byt_g2_b[4]));
assign ex4_inc_byt_g4[1] = (~(ex4_inc_byt_g2_b[1] | ex4_inc_byt_g2_b[3]));
assign ex4_inc_byt_g4[0] = (~(ex4_inc_byt_g2_b[0] | ex4_inc_byt_g2_b[2]));
assign ex4_inc_byt_g8_b[6] = (~(ex4_inc_byt_g4[6]));
assign ex4_inc_byt_g8_b[5] = (~(ex4_inc_byt_g4[5]));
assign ex4_inc_byt_g8_b[4] = (~(ex4_inc_byt_g4[4]));
assign ex4_inc_byt_g8_b[3] = (~(ex4_inc_byt_g4[3]));
assign ex4_inc_byt_g8_b[2] = (~(ex4_inc_byt_g4[2] & ex4_inc_byt_g4[6]));
assign ex4_inc_byt_g8_b[1] = (~(ex4_inc_byt_g4[1] & ex4_inc_byt_g4[5]));
assign ex4_inc_byt_g8_b[0] = (~(ex4_inc_byt_g4[0] & ex4_inc_byt_g4[4]));
assign ex4_inc_all1 = (~ex4_inc_byt_g8_b[0]);
assign ex4_inc_byt_c_glb[1] = (~ex4_inc_byt_g8_b[1]); // drive back from common
assign ex4_inc_byt_c_glb[2] = (~ex4_inc_byt_g8_b[2]); // drive back from common
assign ex4_inc_byt_c_glb[3] = (~ex4_inc_byt_g8_b[3]); // drive back from common
assign ex4_inc_byt_c_glb[4] = (~ex4_inc_byt_g8_b[4]); // drive back from common
assign ex4_inc_byt_c_glb[5] = (~ex4_inc_byt_g8_b[5]); // drive back from common
assign ex4_inc_byt_c_glb[6] = (~ex4_inc_byt_g8_b[6]); // drive back from common
assign ex4_inc_byt_g_glb_int[1] = (~ex4_inc_byt_g8_b[1]);
assign ex4_inc_byt_g_glb_int[2] = (~ex4_inc_byt_g8_b[2]);
assign ex4_inc_byt_g_glb_int[3] = (~ex4_inc_byt_g8_b[3]);
assign ex4_inc_byt_g_glb_int[4] = (~ex4_inc_byt_g8_b[4]);
assign ex4_inc_byt_g_glb_int[5] = (~ex4_inc_byt_g8_b[5]);
assign ex4_inc_byt_g_glb_int[6] = (~ex4_inc_byt_g8_b[6]);
assign ex4_inc_byt_c_glb_b[1] = (~ex4_inc_byt_g_glb_int[1]); // drive back from common
assign ex4_inc_byt_c_glb_b[2] = (~ex4_inc_byt_g_glb_int[2]); // drive back from common
assign ex4_inc_byt_c_glb_b[3] = (~ex4_inc_byt_g_glb_int[3]); // drive back from common
assign ex4_inc_byt_c_glb_b[4] = (~ex4_inc_byt_g_glb_int[4]); // drive back from common
assign ex4_inc_byt_c_glb_b[5] = (~ex4_inc_byt_g_glb_int[5]); // drive back from common
assign ex4_inc_byt_c_glb_b[6] = (~ex4_inc_byt_g_glb_int[6]); // drive back from common
endmodule |
module c_wrapper(
// vcs,
// vdd,
// gnd,
clk,
clk2x,
clk4x,
reset,
an_ac_coreid,
an_ac_pm_thread_stop,
an_ac_ext_interrupt,
an_ac_crit_interrupt,
an_ac_perf_interrupt,
an_ac_external_mchk,
an_ac_flh2l2_gate,
an_ac_reservation_vld,
ac_an_debug_trigger,
an_ac_debug_stop,
an_ac_tb_update_enable,
an_ac_tb_update_pulse,
an_ac_hang_pulse,
ac_an_pm_thread_running,
ac_an_machine_check,
ac_an_recov_err,
ac_an_checkstop,
ac_an_local_checkstop,
an_ac_stcx_complete,
an_ac_stcx_pass,
an_ac_reld_data_vld,
an_ac_reld_core_tag,
an_ac_reld_data,
an_ac_reld_qw,
an_ac_reld_ecc_err,
an_ac_reld_ecc_err_ue,
an_ac_reld_data_coming,
an_ac_reld_crit_qw,
an_ac_reld_l1_dump,
an_ac_req_ld_pop,
an_ac_req_st_pop,
an_ac_req_st_gather,
an_ac_sync_ack,
ac_an_req_pwr_token,
ac_an_req,
ac_an_req_ra,
ac_an_req_ttype,
ac_an_req_thread,
ac_an_req_wimg_w,
ac_an_req_wimg_i,
ac_an_req_wimg_m,
ac_an_req_wimg_g,
ac_an_req_user_defined,
ac_an_req_ld_core_tag,
ac_an_req_ld_xfr_len,
ac_an_st_byte_enbl,
ac_an_st_data,
ac_an_req_endian,
ac_an_st_data_pwr_token
);
input clk;
input clk2x;
input clk4x;
input reset;
input [0:7] an_ac_coreid;
input [0:3] an_ac_pm_thread_stop;
input [0:3] an_ac_ext_interrupt;
input [0:3] an_ac_crit_interrupt;
input [0:3] an_ac_perf_interrupt;
input [0:3] an_ac_external_mchk;
input an_ac_flh2l2_gate; // Gate L1 Hit forwarding SPR config bit
input [0:3] an_ac_reservation_vld;
output [0:3] ac_an_debug_trigger;
input an_ac_debug_stop;
input an_ac_tb_update_enable;
input an_ac_tb_update_pulse;
input [0:3] an_ac_hang_pulse;
output [0:3] ac_an_pm_thread_running;
output [0:3] ac_an_machine_check;
output [0:2] ac_an_recov_err;
output [0:2] ac_an_checkstop;
output [0:2] ac_an_local_checkstop;
wire scan_in;
wire scan_out;
// Pervasive clock control
wire an_ac_rtim_sl_thold_8;
wire an_ac_func_sl_thold_8;
wire an_ac_func_nsl_thold_8;
wire an_ac_ary_nsl_thold_8;
wire an_ac_sg_8;
wire an_ac_fce_8;
wire [0:7] an_ac_abst_scan_in;
// L2 STCX complete
input [0:3] an_ac_stcx_complete;
input [0:3] an_ac_stcx_pass;
// ICBI ACK Interface
wire an_ac_icbi_ack;
wire [0:1] an_ac_icbi_ack_thread;
// Back invalidate interface
wire an_ac_back_inv;
wire [22:63] an_ac_back_inv_addr;
wire [0:4] an_ac_back_inv_target; // connect to bit(0)
wire an_ac_back_inv_local;
wire an_ac_back_inv_lbit;
wire an_ac_back_inv_gs;
wire an_ac_back_inv_ind;
wire [0:7] an_ac_back_inv_lpar_id;
wire ac_an_back_inv_reject;
wire [0:7] ac_an_lpar_id;
// L2 Reload Inputs
input an_ac_reld_data_vld; // reload data is coming next cycle
input [0:4] an_ac_reld_core_tag; // reload data destinatoin tag (which load queue)
input [0:127] an_ac_reld_data; // Reload Data
input [57:59] an_ac_reld_qw; // quadword address of reload data beat
input an_ac_reld_ecc_err; // Reload Data contains a Correctable ECC error
input an_ac_reld_ecc_err_ue; // Reload Data contains an Uncorrectable ECC error
input an_ac_reld_data_coming;
wire an_ac_reld_ditc;
input an_ac_reld_crit_qw;
input an_ac_reld_l1_dump;
wire [0:3] an_ac_req_spare_ctrl_a1; // spare control bits from L2
// load/store credit control
input an_ac_req_ld_pop; // credit for a load (L2 can take a load command)
input an_ac_req_st_pop; // credit for a store (L2 can take a store command)
input an_ac_req_st_gather; // credit for a store due to L2 gathering of store commands
input [0:3] an_ac_sync_ack;
//SCOM Satellite
wire [0:3] an_ac_scom_sat_id;
wire an_ac_scom_dch;
wire an_ac_scom_cch;
wire ac_an_scom_dch;
wire ac_an_scom_cch;
// FIR and Error Signals
wire [0:0] ac_an_special_attn;
wire ac_an_trace_error;
wire ac_an_livelock_active;
wire an_ac_checkstop;
// Perfmon Event Bus
wire [0:3] ac_an_event_bus0;
wire [0:3] ac_an_event_bus1;
// Reset related
wire an_ac_reset_1_complete;
wire an_ac_reset_2_complete;
wire an_ac_reset_3_complete;
wire an_ac_reset_wd_complete;
// Power Management
wire [0:0] an_ac_pm_fetch_halt;
wire ac_an_power_managed;
wire ac_an_rvwinkle_mode;
// Clock, Test, and LCB Controls
wire an_ac_gsd_test_enable_dc;
wire an_ac_gsd_test_acmode_dc;
wire an_ac_ccflush_dc;
wire an_ac_ccenable_dc;
wire an_ac_lbist_en_dc;
wire an_ac_lbist_ip_dc;
wire an_ac_lbist_ac_mode_dc;
wire an_ac_scan_diag_dc;
wire an_ac_scan_dis_dc_b;
//Thold input to clock control macro
wire [0:8] an_ac_scan_type_dc;
// Pervasive
wire ac_an_reset_1_request;
wire ac_an_reset_2_request;
wire ac_an_reset_3_request;
wire ac_an_reset_wd_request;
wire an_ac_lbist_ary_wrt_thru_dc;
wire [0:0] an_ac_sleep_en;
wire [0:3] an_ac_chipid_dc;
wire [0:0] an_ac_uncond_dbg_event;
wire [0:31] ac_an_debug_bus;
wire ac_an_coretrace_first_valid; // coretrace_ctrls[0]
wire ac_an_coretrace_valid; // coretrace_ctrls[1]
wire [0:1] ac_an_coretrace_type; // coretrace_ctrls[2:3]
// L2 Outputs
output ac_an_req_pwr_token; // power token for command coming next cycle
output ac_an_req; // command request valid
output [22:63] ac_an_req_ra; // real address for request
output [0:5] ac_an_req_ttype; // command (transaction) type
output [0:2] ac_an_req_thread; // encoded thread ID
output ac_an_req_wimg_w; // write-through
output ac_an_req_wimg_i; // cache-inhibited
output ac_an_req_wimg_m; // memory coherence required
output ac_an_req_wimg_g; // guarded memory
output [0:3] ac_an_req_user_defined; // User Defined Bits
wire [0:3] ac_an_req_spare_ctrl_a0; // Spare bits
output [0:4] ac_an_req_ld_core_tag; // load command tag (which load Q)
output [0:2] ac_an_req_ld_xfr_len; // transfer length for non-cacheable load
output [0:31] ac_an_st_byte_enbl; // byte enables for store data
output [0:255] ac_an_st_data; // store data
output ac_an_req_endian; // endian mode (0=big endian, 1=little endian)
output ac_an_st_data_pwr_token; // store data power token
// constant EXPAND_TYPE : integer $ 1;
wire clk_reset;
wire [0:15] rate;
wire [0:3] div2;
wire [0:3] div3;
wire [0:`NCLK_WIDTH-1] nclk;
wire [1:3] osc;
// component variable_osc
// Pervasive clock control
// L2 STCX complete
// ICBI ACK Interface
// Back invalidate interface
// connect to bit(0)
// L2 Reload Inputs
// reload data is coming next cycle
// reload data destinatoin tag (which load queue)
// Reload Data
// quadword address of reload data beat
// Reload Data contains a Correctable ECC error
// Reload Data contains an Uncorrectable ECC error
// spare control bits from L2
// load/store credit control
// Gate L1 Hit forwarding SPR config bit
// credit for a load (L2 can take a load command)
// credit for a store (L2 can take a store command)
// credit for a store due to L2 gathering of store commands
//SCOM Satellite
// FIR and Error Signals
// Perfmon Event Bus
// Reset related
// Power Management
// Clock, Test, and LCB Controls
//Thold input to clock control macro
// PSRO Sensors
// ABIST Engine
// Bolt-On ABIST system interface
// Pervasive
// L2 Outputs
// power token for command coming next cycle
// command request valid
// real address for request
// command (transaction) type
// encoded thread ID
// write-through
// cache-inhibited
// memory coherence required
// guarded memory
// User Defined Bits
// Spare bits
// load command tag (which load Q)
// transfer length for non-cacheable load
// byte enables for store data
// store data
// endian mode (0=big endian, 1=little endian)
// store data power token
assign rate = 16'b0000000100000000;
assign div2 = 4'b0010;
assign div3 = 4'b0100;
assign clk_reset = 1'b1;
assign an_ac_ccflush_dc = 1'b0;
assign an_ac_rtim_sl_thold_8= 1'b0;
assign an_ac_func_sl_thold_8= 1'b0;
assign an_ac_func_nsl_thold_8= 1'b0;
assign an_ac_ary_nsl_thold_8= 1'b0;
assign an_ac_sg_8= 1'b0;
assign an_ac_fce_8= 1'b0;
assign scan_in = 'b0;
assign an_ac_abst_scan_in = 'b0;
assign an_ac_icbi_ack = 'b0;
assign an_ac_icbi_ack_thread = 'b0;
assign an_ac_back_inv = 'b0;
assign an_ac_back_inv_addr = 'b0;
assign an_ac_back_inv_target = 'b0;
assign an_ac_back_inv_local = 'b0;
assign an_ac_back_inv_lbit = 'b0;
assign an_ac_back_inv_gs = 'b0;
assign an_ac_back_inv_ind = 'b0;
assign an_ac_back_inv_lpar_id = 'b0;
assign an_ac_reld_ditc = 'b0;
assign an_ac_req_spare_ctrl_a1 = 'b0;
assign an_ac_scom_sat_id = 'b0;
assign an_ac_scom_dch = 'b0;
assign an_ac_scom_cch = 'b0;
assign an_ac_checkstop = 'b0;
assign an_ac_reset_1_complete = 'b0;
assign an_ac_reset_2_complete = 'b0;
assign an_ac_reset_3_complete = 'b0;
assign an_ac_reset_wd_complete = 'b0;
assign an_ac_pm_fetch_halt = 'b0;
assign an_ac_gsd_test_enable_dc = 'b0;
assign an_ac_gsd_test_acmode_dc = 'b0;
assign an_ac_ccflush_dc = 'b0;
assign an_ac_ccenable_dc = 'b0;
assign an_ac_lbist_en_dc = 'b0;
assign an_ac_lbist_ip_dc = 'b0;
assign an_ac_lbist_ac_mode_dc = 'b0;
assign an_ac_scan_diag_dc = 'b0;
assign an_ac_scan_dis_dc_b = 'b0;
assign an_ac_scan_type_dc = 'b0;
assign an_ac_lbist_ary_wrt_thru_dc = 'b0;
assign an_ac_sleep_en = 'b0;
assign an_ac_chipid_dc = 'b0;
assign an_ac_uncond_dbg_event = 'b0;
assign nclk[0] = clk;
assign nclk[1] = reset;
assign nclk[2] = clk2x;
assign nclk[3] = clk4x;
assign nclk[4] = 'b0;
assign nclk[5] = 'b0;
(*dont_touch = "true" *) c c0(
// .vcs(vcs),
// .vdd(vdd),
// .gnd(gnd),
.nclk(nclk),
.scan_in(scan_in),
.scan_out(scan_out),
// Pervasive clock control
.an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8),
.an_ac_func_sl_thold_8(an_ac_func_sl_thold_8),
.an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8),
.an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8),
.an_ac_sg_8(an_ac_sg_8),
.an_ac_fce_8(an_ac_fce_8),
.an_ac_abst_scan_in(an_ac_abst_scan_in),
// L2 STCX complete
.an_ac_stcx_complete(an_ac_stcx_complete[0:`THREADS-1]),
.an_ac_stcx_pass(an_ac_stcx_pass[0:`THREADS-1]),
// ICBI ACK Interface
.an_ac_icbi_ack(an_ac_icbi_ack),
.an_ac_icbi_ack_thread(an_ac_icbi_ack_thread),
// Back invalidate interface
.an_ac_back_inv(an_ac_back_inv),
.an_ac_back_inv_addr(an_ac_back_inv_addr),
.an_ac_back_inv_target(an_ac_back_inv_target),
.an_ac_back_inv_local(an_ac_back_inv_local),
.an_ac_back_inv_lbit(an_ac_back_inv_lbit),
.an_ac_back_inv_gs(an_ac_back_inv_gs),
.an_ac_back_inv_ind(an_ac_back_inv_ind),
.an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id),
.ac_an_back_inv_reject(ac_an_back_inv_reject),
.ac_an_lpar_id(ac_an_lpar_id),
// L2 Reload Inputs
.an_ac_reld_data_vld(an_ac_reld_data_vld),
.an_ac_reld_core_tag(an_ac_reld_core_tag),
.an_ac_reld_data(an_ac_reld_data),
.an_ac_reld_qw(an_ac_reld_qw[58:59]),
.an_ac_reld_ecc_err(an_ac_reld_ecc_err),
.an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue),
.an_ac_reld_data_coming(an_ac_reld_data_coming),
.an_ac_reld_ditc(an_ac_reld_ditc),
.an_ac_reld_crit_qw(an_ac_reld_crit_qw),
.an_ac_reld_l1_dump(an_ac_reld_l1_dump),
.an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1),
// load/store credit control
.an_ac_flh2l2_gate(an_ac_flh2l2_gate),
.an_ac_req_ld_pop(an_ac_req_ld_pop),
.an_ac_req_st_pop(an_ac_req_st_pop),
.an_ac_req_st_gather(an_ac_req_st_gather),
.an_ac_sync_ack(an_ac_sync_ack[0:`THREADS-1]),
//SCOM Satellite
.an_ac_scom_sat_id(an_ac_scom_sat_id),
.an_ac_scom_dch(an_ac_scom_dch),
.an_ac_scom_cch(an_ac_scom_cch),
.ac_an_scom_dch(ac_an_scom_dch),
.ac_an_scom_cch(ac_an_scom_cch),
// FIR and Error Signals
.ac_an_special_attn(ac_an_special_attn),
.ac_an_checkstop(ac_an_checkstop),
.ac_an_local_checkstop(ac_an_local_checkstop),
.ac_an_recov_err(ac_an_recov_err),
.ac_an_trace_error(ac_an_trace_error),
.ac_an_livelock_active(ac_an_livelock_active),
.an_ac_checkstop(an_ac_checkstop),
.an_ac_external_mchk(an_ac_external_mchk[0:`THREADS-1]),
// Perfmon Event Bus
.ac_an_event_bus0(ac_an_event_bus0),
.ac_an_event_bus1(ac_an_event_bus1),
// Reset related
.an_ac_reset_1_complete(an_ac_reset_1_complete),
.an_ac_reset_2_complete(an_ac_reset_2_complete),
.an_ac_reset_3_complete(an_ac_reset_3_complete),
.an_ac_reset_wd_complete(an_ac_reset_wd_complete),
// Power Management
.ac_an_pm_thread_running(ac_an_pm_thread_running[0:`THREADS-1]),
.an_ac_pm_thread_stop(an_ac_pm_thread_stop[0:`THREADS-1]),
.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
.ac_an_power_managed(ac_an_power_managed),
.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),
// Clock, Test, and LCB Controls
.an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
.an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
.an_ac_ccflush_dc(an_ac_ccflush_dc),
.an_ac_ccenable_dc(an_ac_ccenable_dc),
.an_ac_lbist_en_dc(an_ac_lbist_en_dc),
.an_ac_lbist_ip_dc(an_ac_lbist_ip_dc),
.an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc),
.an_ac_scan_diag_dc(an_ac_scan_diag_dc),
.an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),
//Thold input to clock control macro
.an_ac_scan_type_dc(an_ac_scan_type_dc),
// Pervasive
.ac_an_reset_1_request(ac_an_reset_1_request),
.ac_an_reset_2_request(ac_an_reset_2_request),
.ac_an_reset_3_request(ac_an_reset_3_request),
.ac_an_reset_wd_request(ac_an_reset_wd_request),
.an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
.an_ac_reservation_vld(an_ac_reservation_vld[0:`THREADS-1]),
.an_ac_sleep_en(an_ac_sleep_en),
.an_ac_ext_interrupt(an_ac_ext_interrupt[0:`THREADS-1]),
.an_ac_crit_interrupt(an_ac_crit_interrupt[0:`THREADS-1]),
.an_ac_perf_interrupt(an_ac_perf_interrupt[0:`THREADS-1]),
.an_ac_hang_pulse(an_ac_hang_pulse[0:`THREADS-1]),
.an_ac_tb_update_enable(an_ac_tb_update_enable),
.an_ac_tb_update_pulse(an_ac_tb_update_pulse),
.an_ac_chipid_dc(an_ac_chipid_dc),
.an_ac_coreid(an_ac_coreid),
.ac_an_machine_check(ac_an_machine_check[0:`THREADS-1]),
.an_ac_debug_stop(an_ac_debug_stop),
.ac_an_debug_trigger(ac_an_debug_trigger[0:`THREADS-1]),
.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
.ac_an_debug_bus(ac_an_debug_bus),
.ac_an_coretrace_first_valid(ac_an_coretrace_first_valid),
.ac_an_coretrace_valid(ac_an_coretrace_valid),
.ac_an_coretrace_type(ac_an_coretrace_type),
// L2 Outputs
.ac_an_req_pwr_token(ac_an_req_pwr_token),
.ac_an_req(ac_an_req),
.ac_an_req_ra(ac_an_req_ra),
.ac_an_req_ttype(ac_an_req_ttype),
.ac_an_req_thread(ac_an_req_thread),
.ac_an_req_wimg_w(ac_an_req_wimg_w),
.ac_an_req_wimg_i(ac_an_req_wimg_i),
.ac_an_req_wimg_m(ac_an_req_wimg_m),
.ac_an_req_wimg_g(ac_an_req_wimg_g),
.ac_an_req_user_defined(ac_an_req_user_defined),
.ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0),
.ac_an_req_ld_core_tag(ac_an_req_ld_core_tag),
.ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len),
.ac_an_st_byte_enbl(ac_an_st_byte_enbl),
.ac_an_st_data(ac_an_st_data),
.ac_an_req_endian(ac_an_req_endian),
.ac_an_st_data_pwr_token(ac_an_st_data_pwr_token)
);
endmodule |
module iuq_dbg(
inout vdd,
inout gnd,
(* pin_data ="PIN_FUNCTION=/G_CLK/" *)
input [0:`NCLK_WIDTH-1] nclk,
input thold_2, // Connect to slp if unit uses slp
input pc_iu_sg_2,
input clkoff_b,
input act_dis,
input tc_ac_ccflush_dc,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
(* pin_data ="PIN_FUNCTION=/SCAN_IN/" *)
input func_scan_in,
(* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *)
output func_scan_out,
input [0:31] unit_dbg_data0,
input [0:31] unit_dbg_data1,
input [0:31] unit_dbg_data2,
input [0:31] unit_dbg_data3,
input [0:31] unit_dbg_data4,
input [0:31] unit_dbg_data5,
input [0:31] unit_dbg_data6,
input [0:31] unit_dbg_data7,
input [0:31] unit_dbg_data8,
input [0:31] unit_dbg_data9,
input [0:31] unit_dbg_data10,
input [0:31] unit_dbg_data11,
input [0:31] unit_dbg_data12,
input [0:31] unit_dbg_data13,
input [0:31] unit_dbg_data14,
input [0:31] unit_dbg_data15,
input pc_iu_trace_bus_enable,
input [0:10] pc_iu_debug_mux_ctrls,
input [0:31] debug_bus_in,
output [0:31] debug_bus_out,
input [0:3] coretrace_ctrls_in,
output [0:3] coretrace_ctrls_out
);
localparam trace_bus_enable_offset = 0;
localparam debug_mux_ctrls_offset = trace_bus_enable_offset + 1;
localparam trace_data_out_offset = debug_mux_ctrls_offset + 11;
localparam coretrace_ctrls_out_offset = trace_data_out_offset + 32;
localparam scan_right = coretrace_ctrls_out_offset + 4 - 1;
wire trace_bus_enable_d;
wire trace_bus_enable_q;
wire [0:10] debug_mux_ctrls_d;
wire [0:10] debug_mux_ctrls_q;
wire [0:31] trace_data_out_d;
wire [0:31] trace_data_out_q;
wire [0:3] coretrace_ctrls_out_d;
wire [0:3] coretrace_ctrls_out_q;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
wire thold_1;
wire thold_0;
wire thold_0_b;
wire pc_iu_sg_1;
wire pc_iu_sg_0;
wire force_t;
wire tiup;
//BEGIN
assign tiup = 1'b1;
tri_debug_mux16 dbg_mux0(
//.vd(vdd),
//.gd(gnd),
.select_bits(debug_mux_ctrls_q),
.trace_data_in(debug_bus_in),
.dbg_group0(unit_dbg_data0),
.dbg_group1(unit_dbg_data1),
.dbg_group2(unit_dbg_data2),
.dbg_group3(unit_dbg_data3),
.dbg_group4(unit_dbg_data4),
.dbg_group5(unit_dbg_data5),
.dbg_group6(unit_dbg_data6),
.dbg_group7(unit_dbg_data7),
.dbg_group8(unit_dbg_data8),
.dbg_group9(unit_dbg_data9),
.dbg_group10(unit_dbg_data10),
.dbg_group11(unit_dbg_data11),
.dbg_group12(unit_dbg_data12),
.dbg_group13(unit_dbg_data13),
.dbg_group14(unit_dbg_data14),
.dbg_group15(unit_dbg_data15),
.trace_data_out(trace_data_out_d),
.coretrace_ctrls_in(coretrace_ctrls_in),
.coretrace_ctrls_out(coretrace_ctrls_out_d)
);
assign debug_bus_out = trace_data_out_q;
assign coretrace_ctrls_out = coretrace_ctrls_out_q;
//---------------------------------------------------------------------
// Latches
//---------------------------------------------------------------------
assign trace_bus_enable_d = pc_iu_trace_bus_enable;
assign debug_mux_ctrls_d = pc_iu_debug_mux_ctrls;
tri_rlmlatch_p #(.INIT(0)) trace_bus_enable_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[trace_bus_enable_offset]),
.scout(sov[trace_bus_enable_offset]),
.din(trace_bus_enable_d),
.dout(trace_bus_enable_q)
);
tri_rlmreg_p #(.WIDTH(11), .INIT(0)) debug_mux_ctrls_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(trace_bus_enable_q),
.thold_b(thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[debug_mux_ctrls_offset:debug_mux_ctrls_offset + 10]),
.scout(sov[debug_mux_ctrls_offset:debug_mux_ctrls_offset + 10]),
.din(debug_mux_ctrls_d),
.dout(debug_mux_ctrls_q)
);
tri_rlmreg_p #(.WIDTH(32), .INIT(0)) trace_data_out_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(trace_bus_enable_q),
.thold_b(thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[trace_data_out_offset:trace_data_out_offset + 31]),
.scout(sov[trace_data_out_offset:trace_data_out_offset + 31]),
.din(trace_data_out_d),
.dout(trace_data_out_q)
);
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) coretrace_ctrls_out_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(trace_bus_enable_q),
.thold_b(thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[coretrace_ctrls_out_offset:coretrace_ctrls_out_offset + 3]),
.scout(sov[coretrace_ctrls_out_offset:coretrace_ctrls_out_offset + 3]),
.din(coretrace_ctrls_out_d),
.dout(coretrace_ctrls_out_q)
);
//---------------------------------------------------------------------
// pervasive thold/sg latches
//---------------------------------------------------------------------
tri_plat #(.WIDTH(2)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({thold_2, pc_iu_sg_2}),
.q( {thold_1, pc_iu_sg_1})
);
tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({thold_1, pc_iu_sg_1}),
.q( {thold_0, pc_iu_sg_0})
);
tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(pc_iu_sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
//---------------------------------------------------------------------
// Scan
//---------------------------------------------------------------------
assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
assign func_scan_out = sov[0];
endmodule |
module xu0_bcd(
// Clocks
input [0:`NCLK_WIDTH-1] nclk,
// Power
inout vdd,
inout gnd,
// Pervasive
input d_mode_dc,
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input sg_0,
input scan_in,
output scan_out,
// Decode Inputs
input dec_bcd_ex1_val,
input dec_bcd_ex1_is_addg6s,
input dec_bcd_ex1_is_cdtbcd,
// Source Data
input [64-`GPR_WIDTH:63] byp_bcd_ex2_rs1,
input [64-`GPR_WIDTH:63] byp_bcd_ex2_rs2,
// Target Data
output [64-`GPR_WIDTH:63] bcd_byp_ex3_rt,
output bcd_byp_ex3_done
);
// Latches
wire ex2_val_q; // input=>dec_bcd_ex1_val ,act=>1'b1
wire ex2_is_addg6s_q; // input=>dec_bcd_ex1_is_addg6s ,act=>dec_bcd_ex1_val
wire ex2_is_cdtbcd_q; // input=>dec_bcd_ex1_is_cdtbcd ,act=>dec_bcd_ex1_val
wire [64-`GPR_WIDTH:63] ex3_bcd_rt_q; // input=>ex2_bcd_rt ,act=>ex2_val_q
wire [64-`GPR_WIDTH:63] ex2_bcd_rt;
wire ex3_val_q; // input=>ex2_val_q ,act=>1'b1
// Scanchains
localparam ex2_val_offset = 0;
localparam ex2_is_addg6s_offset = ex2_val_offset + 1;
localparam ex2_is_cdtbcd_offset = ex2_is_addg6s_offset + 1;
localparam ex3_bcd_rt_offset = ex2_is_cdtbcd_offset + 1;
localparam ex3_val_offset = ex3_bcd_rt_offset + `GPR_WIDTH;
localparam scan_right = ex3_val_offset + 1;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
wire [0:63] g0;
wire [0:63] g1;
wire [0:63] g2;
wire [0:63] g3;
wire [0:63] g4;
wire [0:63] g5;
wire [0:63] g6;
wire [0:62] p0;
wire [0:61] p1;
wire [0:59] p2;
wire [0:55] p3;
wire [0:47] p4;
wire [0:31] p5;
wire [0:63] ex2_bcdtd_rt;
wire [0:63] ex2_dtbcd_rt;
wire [0:63] ex2_sixes_rt;
// synopsys translate_off
(* analysis_not_referenced="true" *)
// synopsys translate_on
wire unused;
// BCD to DPD
xu0_bcd_bcdtd bcdtd00(
.a(byp_bcd_ex2_rs1[8:19]),
.y(ex2_bcdtd_rt[12:21])
);
xu0_bcd_bcdtd bcdtd01(
.a(byp_bcd_ex2_rs1[20:31]),
.y(ex2_bcdtd_rt[22:31])
);
xu0_bcd_bcdtd bcdtd10(
.a(byp_bcd_ex2_rs1[40:51]),
.y(ex2_bcdtd_rt[44:53])
);
xu0_bcd_bcdtd bcdtd11(
.a(byp_bcd_ex2_rs1[52:63]),
.y(ex2_bcdtd_rt[54:63])
);
assign ex2_bcdtd_rt[0:11] = {12{1'b0}};
assign ex2_bcdtd_rt[32:43] = {12{1'b0}};
// DPD to BCD
xu0_bcd_dtbcd dtbcd00(
.a(byp_bcd_ex2_rs1[12:21]),
.y(ex2_dtbcd_rt[8:19])
);
xu0_bcd_dtbcd dtbcd01(
.a(byp_bcd_ex2_rs1[22:31]),
.y(ex2_dtbcd_rt[20:31])
);
xu0_bcd_dtbcd dtbcd10(
.a(byp_bcd_ex2_rs1[44:53]),
.y(ex2_dtbcd_rt[40:51])
);
xu0_bcd_dtbcd dtbcd11(
.a(byp_bcd_ex2_rs1[54:63]),
.y(ex2_dtbcd_rt[52:63])
);
assign ex2_dtbcd_rt[0:7] = {8{1'b0}};
assign ex2_dtbcd_rt[32:39] = {8{1'b0}};
// ADDG6S
assign p0[00:62] = byp_bcd_ex2_rs1[00:62] ^ byp_bcd_ex2_rs2[00:62];
assign g0[00:63] = byp_bcd_ex2_rs1[00:63] & byp_bcd_ex2_rs2[00:63];
// L1 (1)
assign g1[00:62] = (p0[00:62] & g0[01:63]) | g0[00:62];
assign g1[63:63] = g0[63:63];
assign p1[00:61] = p0[00:61] & p0[01:62];
// L2 (2)
assign g2[00:61] = (p1[00:61] & g1[02:63]) | g1[00:61];
assign g2[62:63] = g1[62:63];
assign p2[00:59] = p1[00:59] & p1[02:61];
// L3 (4)
assign g3[00:59] = (p2[00:59] & g2[04:63]) | g2[00:59];
assign g3[60:63] = g2[60:63];
assign p3[00:55] = p2[00:55] & p2[04:59];
// L4 (8)
assign g4[00:55] = (p3[00:55] & g3[08:63]) | g3[00:55];
assign g4[56:63] = g3[56:63];
assign p4[00:47] = p3[00:47] & p3[08:55];
// L5 (16)
assign g5[00:47] = (p4[00:47] & g4[16:63]) | g4[00:47];
assign g5[48:63] = g4[48:63];
assign p5[00:31] = p4[00:31] & p4[16:47];
// L6 (32)
assign g6[00:31] = (p5[00:31] & g5[32:63]) | g5[00:31];
assign g6[32:63] = g5[32:63];
generate
genvar b;
for (b = 0; b <= 15; b = b + 1)
begin : nibble
assign ex2_sixes_rt[4 * b:4 * b + 3] = (g6[b * 4] == 1'b0) ? 4'b0110 :
4'b0000;
end
endgenerate
//!! bugspray include: tri_a2o.bil
//!! %for(i=0;i<16;++i)
//!! [count; scenarios.addg6s_n%(i)_0 ; bugclk] : (pri2) <= ex2_val_q and ex2_is_addg6s_q and not g6(%(i*4));
//!! [count; scenarios.addg6s_n%(i)_1 ; bugclk] : (pri2) <= ex2_val_q and ex2_is_addg6s_q and g6(%(i*4));
//!! %end
assign ex2_bcd_rt = ({ex2_is_addg6s_q, ex2_is_cdtbcd_q} == 2'b10) ? ex2_sixes_rt :
({ex2_is_addg6s_q, ex2_is_cdtbcd_q} == 2'b01) ? ex2_dtbcd_rt :
ex2_bcdtd_rt;
assign bcd_byp_ex3_rt = ex3_bcd_rt_q;
assign bcd_byp_ex3_done = ex3_val_q;
// Latches
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(1'b1),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_val_offset]),
.scout(sov[ex2_val_offset]),
.din(dec_bcd_ex1_val),
.dout(ex2_val_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_addg6s_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_bcd_ex1_val),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_is_addg6s_offset]),
.scout(sov[ex2_is_addg6s_offset]),
.din(dec_bcd_ex1_is_addg6s),
.dout(ex2_is_addg6s_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_cdtbcd_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_bcd_ex1_val),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_is_cdtbcd_offset]),
.scout(sov[ex2_is_cdtbcd_offset]),
.din(dec_bcd_ex1_is_cdtbcd),
.dout(ex2_is_cdtbcd_q)
);
tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_bcd_rt_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_val_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_bcd_rt_offset:ex3_bcd_rt_offset + `GPR_WIDTH - 1]),
.scout(sov[ex3_bcd_rt_offset:ex3_bcd_rt_offset + `GPR_WIDTH - 1]),
.din(ex2_bcd_rt),
.dout(ex3_bcd_rt_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(1'b1),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_val_offset]),
.scout(sov[ex3_val_offset]),
.din(ex2_val_q),
.dout(ex3_val_q)
);
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
assign unused = (|g6[1:3]) | (|g6[5:7]) | (|g6[9:11]) | (|g6[13:15]) | (|g6[17:19]) | (|g6[21:23]) | (|g6[25:27]) |
(|g6[29:31]) | (|g6[33:35]) | (|g6[37:39]) | (|g6[41:43]) | (|g6[45:47]) | (|g6[49:51]) | (|g6[53:55]) |
(|g6[57:59]) | (|g6[61:63]);
endmodule |
module fu_lza_clz(
lv0_or,
lv6_or_0,
lv6_or_1,
lza_any_b,
lza_amt_b
);
input [0:162] lv0_or;
output lv6_or_0;
output lv6_or_1;
output lza_any_b;
output [0:7] lza_amt_b;
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:81] lv1_or_b; // group_002
wire [0:81] lv1_inv_b;
wire [0:81] lv1_enc7_b;
wire [0:40] lv2_or; // group_004
wire [0:40] lv2_inv;
wire [0:40] lv2_enc6;
wire [0:40] lv2_enc7;
wire [0:20] lv3_or_b; // group_008
wire [0:20] lv3_inv_b; // group_008
wire [0:20] lv3_enc5_b;
wire [0:20] lv3_enc6_b;
wire [0:20] lv3_enc7_b;
wire [0:10] lv4_or; // group_016
wire [0:10] lv4_inv; // group_016
wire [0:10] lv4_enc4;
wire [0:10] lv4_enc5;
wire [0:10] lv4_enc6;
wire [0:10] lv4_enc7;
wire [0:10] lv4_or_b; // group_016
wire [0:10] lv4_enc4_b;
wire [0:10] lv4_enc5_b;
wire [0:10] lv4_enc6_b;
wire [0:10] lv4_enc7_b;
//-----------------------------------------------------------
wire [0:5] lv5_or; // group_032
wire [0:5] lv5_inv;
wire [0:5] lv5_enc3;
wire [0:5] lv5_enc4;
wire [0:5] lv5_enc5;
wire [0:5] lv5_enc6;
wire [0:5] lv5_enc7;
wire [0:2] lv6_or_b; // group_064
wire [0:2] lv6_inv_b;
wire [0:2] lv6_enc2_b;
wire [0:2] lv6_enc3_b;
wire [0:2] lv6_enc4_b;
wire [0:2] lv6_enc5_b;
wire [0:2] lv6_enc6_b;
wire [0:2] lv6_enc7_b;
wire [0:1] lv7_or; // group_128
wire [0:1] lv7_inv;
wire [0:1] lv7_enc1;
wire [0:1] lv7_enc2;
wire [0:1] lv7_enc3;
wire [0:1] lv7_enc4;
wire [0:1] lv7_enc5;
wire [0:1] lv7_enc6;
wire [0:1] lv7_enc7;
wire [0:0] lv8_or_b; // group_256
wire [0:0] lv8_inv_b;
wire [0:0] lv8_enc0_b;
wire [0:0] lv8_enc1_b;
wire [0:0] lv8_enc2_b;
wire [0:0] lv8_enc3_b;
wire [0:0] lv8_enc4_b;
wire [0:0] lv8_enc5_b;
wire [0:0] lv8_enc6_b;
wire [0:0] lv8_enc7_b;
//=#------------------------------------------------
//=#-- ENCODING TREE (CLZ) count leading zeroes
//=#------------------------------------------------
//--------------------------------------------------------------------------------
// 002 bit group (phase_in=P, phase_out=N, level_in=lv0, level_out=lv1)
//--------------------------------------------------------------------------------
assign lv1_or_b[0] = (~(lv0_or[0] | lv0_or[1]));
assign lv1_or_b[1] = (~(lv0_or[2] | lv0_or[3]));
assign lv1_or_b[2] = (~(lv0_or[4] | lv0_or[5]));
assign lv1_or_b[3] = (~(lv0_or[6] | lv0_or[7]));
assign lv1_or_b[4] = (~(lv0_or[8] | lv0_or[9]));
assign lv1_or_b[5] = (~(lv0_or[10] | lv0_or[11]));
assign lv1_or_b[6] = (~(lv0_or[12] | lv0_or[13]));
assign lv1_or_b[7] = (~(lv0_or[14] | lv0_or[15]));
assign lv1_or_b[8] = (~(lv0_or[16] | lv0_or[17]));
assign lv1_or_b[9] = (~(lv0_or[18] | lv0_or[19]));
assign lv1_or_b[10] = (~(lv0_or[20] | lv0_or[21]));
assign lv1_or_b[11] = (~(lv0_or[22] | lv0_or[23]));
assign lv1_or_b[12] = (~(lv0_or[24] | lv0_or[25]));
assign lv1_or_b[13] = (~(lv0_or[26] | lv0_or[27]));
assign lv1_or_b[14] = (~(lv0_or[28] | lv0_or[29]));
assign lv1_or_b[15] = (~(lv0_or[30] | lv0_or[31]));
assign lv1_or_b[16] = (~(lv0_or[32] | lv0_or[33]));
assign lv1_or_b[17] = (~(lv0_or[34] | lv0_or[35]));
assign lv1_or_b[18] = (~(lv0_or[36] | lv0_or[37]));
assign lv1_or_b[19] = (~(lv0_or[38] | lv0_or[39]));
assign lv1_or_b[20] = (~(lv0_or[40] | lv0_or[41]));
assign lv1_or_b[21] = (~(lv0_or[42] | lv0_or[43]));
assign lv1_or_b[22] = (~(lv0_or[44] | lv0_or[45]));
assign lv1_or_b[23] = (~(lv0_or[46] | lv0_or[47]));
assign lv1_or_b[24] = (~(lv0_or[48] | lv0_or[49]));
assign lv1_or_b[25] = (~(lv0_or[50] | lv0_or[51]));
assign lv1_or_b[26] = (~(lv0_or[52] | lv0_or[53]));
assign lv1_or_b[27] = (~(lv0_or[54] | lv0_or[55]));
assign lv1_or_b[28] = (~(lv0_or[56] | lv0_or[57]));
assign lv1_or_b[29] = (~(lv0_or[58] | lv0_or[59]));
assign lv1_or_b[30] = (~(lv0_or[60] | lv0_or[61]));
assign lv1_or_b[31] = (~(lv0_or[62] | lv0_or[63]));
assign lv1_or_b[32] = (~(lv0_or[64] | lv0_or[65]));
assign lv1_or_b[33] = (~(lv0_or[66] | lv0_or[67]));
assign lv1_or_b[34] = (~(lv0_or[68] | lv0_or[69]));
assign lv1_or_b[35] = (~(lv0_or[70] | lv0_or[71]));
assign lv1_or_b[36] = (~(lv0_or[72] | lv0_or[73]));
assign lv1_or_b[37] = (~(lv0_or[74] | lv0_or[75]));
assign lv1_or_b[38] = (~(lv0_or[76] | lv0_or[77]));
assign lv1_or_b[39] = (~(lv0_or[78] | lv0_or[79]));
assign lv1_or_b[40] = (~(lv0_or[80] | lv0_or[81]));
assign lv1_or_b[41] = (~(lv0_or[82] | lv0_or[83]));
assign lv1_or_b[42] = (~(lv0_or[84] | lv0_or[85]));
assign lv1_or_b[43] = (~(lv0_or[86] | lv0_or[87]));
assign lv1_or_b[44] = (~(lv0_or[88] | lv0_or[89]));
assign lv1_or_b[45] = (~(lv0_or[90] | lv0_or[91]));
assign lv1_or_b[46] = (~(lv0_or[92] | lv0_or[93]));
assign lv1_or_b[47] = (~(lv0_or[94] | lv0_or[95]));
assign lv1_or_b[48] = (~(lv0_or[96] | lv0_or[97]));
assign lv1_or_b[49] = (~(lv0_or[98] | lv0_or[99]));
assign lv1_or_b[50] = (~(lv0_or[100] | lv0_or[101]));
assign lv1_or_b[51] = (~(lv0_or[102] | lv0_or[103]));
assign lv1_or_b[52] = (~(lv0_or[104] | lv0_or[105]));
assign lv1_or_b[53] = (~(lv0_or[106] | lv0_or[107]));
assign lv1_or_b[54] = (~(lv0_or[108] | lv0_or[109]));
assign lv1_or_b[55] = (~(lv0_or[110] | lv0_or[111]));
assign lv1_or_b[56] = (~(lv0_or[112] | lv0_or[113]));
assign lv1_or_b[57] = (~(lv0_or[114] | lv0_or[115]));
assign lv1_or_b[58] = (~(lv0_or[116] | lv0_or[117]));
assign lv1_or_b[59] = (~(lv0_or[118] | lv0_or[119]));
assign lv1_or_b[60] = (~(lv0_or[120] | lv0_or[121]));
assign lv1_or_b[61] = (~(lv0_or[122] | lv0_or[123]));
assign lv1_or_b[62] = (~(lv0_or[124] | lv0_or[125]));
assign lv1_or_b[63] = (~(lv0_or[126] | lv0_or[127]));
assign lv1_or_b[64] = (~(lv0_or[128] | lv0_or[129]));
assign lv1_or_b[65] = (~(lv0_or[130] | lv0_or[131]));
assign lv1_or_b[66] = (~(lv0_or[132] | lv0_or[133]));
assign lv1_or_b[67] = (~(lv0_or[134] | lv0_or[135]));
assign lv1_or_b[68] = (~(lv0_or[136] | lv0_or[137]));
assign lv1_or_b[69] = (~(lv0_or[138] | lv0_or[139]));
assign lv1_or_b[70] = (~(lv0_or[140] | lv0_or[141]));
assign lv1_or_b[71] = (~(lv0_or[142] | lv0_or[143]));
assign lv1_or_b[72] = (~(lv0_or[144] | lv0_or[145]));
assign lv1_or_b[73] = (~(lv0_or[146] | lv0_or[147]));
assign lv1_or_b[74] = (~(lv0_or[148] | lv0_or[149]));
assign lv1_or_b[75] = (~(lv0_or[150] | lv0_or[151]));
assign lv1_or_b[76] = (~(lv0_or[152] | lv0_or[153]));
assign lv1_or_b[77] = (~(lv0_or[154] | lv0_or[155]));
assign lv1_or_b[78] = (~(lv0_or[156] | lv0_or[157]));
assign lv1_or_b[79] = (~(lv0_or[158] | lv0_or[159]));
assign lv1_or_b[80] = (~(lv0_or[160] | lv0_or[161]));
assign lv1_or_b[81] = (~(lv0_or[162]));
assign lv1_inv_b[0] = (~(lv0_or[0]));
assign lv1_inv_b[1] = (~(lv0_or[2]));
assign lv1_inv_b[2] = (~(lv0_or[4]));
assign lv1_inv_b[3] = (~(lv0_or[6]));
assign lv1_inv_b[4] = (~(lv0_or[8]));
assign lv1_inv_b[5] = (~(lv0_or[10]));
assign lv1_inv_b[6] = (~(lv0_or[12]));
assign lv1_inv_b[7] = (~(lv0_or[14]));
assign lv1_inv_b[8] = (~(lv0_or[16]));
assign lv1_inv_b[9] = (~(lv0_or[18]));
assign lv1_inv_b[10] = (~(lv0_or[20]));
assign lv1_inv_b[11] = (~(lv0_or[22]));
assign lv1_inv_b[12] = (~(lv0_or[24]));
assign lv1_inv_b[13] = (~(lv0_or[26]));
assign lv1_inv_b[14] = (~(lv0_or[28]));
assign lv1_inv_b[15] = (~(lv0_or[30]));
assign lv1_inv_b[16] = (~(lv0_or[32]));
assign lv1_inv_b[17] = (~(lv0_or[34]));
assign lv1_inv_b[18] = (~(lv0_or[36]));
assign lv1_inv_b[19] = (~(lv0_or[38]));
assign lv1_inv_b[20] = (~(lv0_or[40]));
assign lv1_inv_b[21] = (~(lv0_or[42]));
assign lv1_inv_b[22] = (~(lv0_or[44]));
assign lv1_inv_b[23] = (~(lv0_or[46]));
assign lv1_inv_b[24] = (~(lv0_or[48]));
assign lv1_inv_b[25] = (~(lv0_or[50]));
assign lv1_inv_b[26] = (~(lv0_or[52]));
assign lv1_inv_b[27] = (~(lv0_or[54]));
assign lv1_inv_b[28] = (~(lv0_or[56]));
assign lv1_inv_b[29] = (~(lv0_or[58]));
assign lv1_inv_b[30] = (~(lv0_or[60]));
assign lv1_inv_b[31] = (~(lv0_or[62]));
assign lv1_inv_b[32] = (~(lv0_or[64]));
assign lv1_inv_b[33] = (~(lv0_or[66]));
assign lv1_inv_b[34] = (~(lv0_or[68]));
assign lv1_inv_b[35] = (~(lv0_or[70]));
assign lv1_inv_b[36] = (~(lv0_or[72]));
assign lv1_inv_b[37] = (~(lv0_or[74]));
assign lv1_inv_b[38] = (~(lv0_or[76]));
assign lv1_inv_b[39] = (~(lv0_or[78]));
assign lv1_inv_b[40] = (~(lv0_or[80]));
assign lv1_inv_b[41] = (~(lv0_or[82]));
assign lv1_inv_b[42] = (~(lv0_or[84]));
assign lv1_inv_b[43] = (~(lv0_or[86]));
assign lv1_inv_b[44] = (~(lv0_or[88]));
assign lv1_inv_b[45] = (~(lv0_or[90]));
assign lv1_inv_b[46] = (~(lv0_or[92]));
assign lv1_inv_b[47] = (~(lv0_or[94]));
assign lv1_inv_b[48] = (~(lv0_or[96]));
assign lv1_inv_b[49] = (~(lv0_or[98]));
assign lv1_inv_b[50] = (~(lv0_or[100]));
assign lv1_inv_b[51] = (~(lv0_or[102]));
assign lv1_inv_b[52] = (~(lv0_or[104]));
assign lv1_inv_b[53] = (~(lv0_or[106]));
assign lv1_inv_b[54] = (~(lv0_or[108]));
assign lv1_inv_b[55] = (~(lv0_or[110]));
assign lv1_inv_b[56] = (~(lv0_or[112]));
assign lv1_inv_b[57] = (~(lv0_or[114]));
assign lv1_inv_b[58] = (~(lv0_or[116]));
assign lv1_inv_b[59] = (~(lv0_or[118]));
assign lv1_inv_b[60] = (~(lv0_or[120]));
assign lv1_inv_b[61] = (~(lv0_or[122]));
assign lv1_inv_b[62] = (~(lv0_or[124]));
assign lv1_inv_b[63] = (~(lv0_or[126]));
assign lv1_inv_b[64] = (~(lv0_or[128]));
assign lv1_inv_b[65] = (~(lv0_or[130]));
assign lv1_inv_b[66] = (~(lv0_or[132]));
assign lv1_inv_b[67] = (~(lv0_or[134]));
assign lv1_inv_b[68] = (~(lv0_or[136]));
assign lv1_inv_b[69] = (~(lv0_or[138]));
assign lv1_inv_b[70] = (~(lv0_or[140]));
assign lv1_inv_b[71] = (~(lv0_or[142]));
assign lv1_inv_b[72] = (~(lv0_or[144]));
assign lv1_inv_b[73] = (~(lv0_or[146]));
assign lv1_inv_b[74] = (~(lv0_or[148]));
assign lv1_inv_b[75] = (~(lv0_or[150]));
assign lv1_inv_b[76] = (~(lv0_or[152]));
assign lv1_inv_b[77] = (~(lv0_or[154]));
assign lv1_inv_b[78] = (~(lv0_or[156]));
assign lv1_inv_b[79] = (~(lv0_or[158]));
assign lv1_inv_b[80] = (~(lv0_or[160]));
assign lv1_inv_b[81] = (~(lv0_or[162]));
assign lv1_enc7_b[0] = (~(lv1_inv_b[0] & lv0_or[1]));
assign lv1_enc7_b[1] = (~(lv1_inv_b[1] & lv0_or[3]));
assign lv1_enc7_b[2] = (~(lv1_inv_b[2] & lv0_or[5]));
assign lv1_enc7_b[3] = (~(lv1_inv_b[3] & lv0_or[7]));
assign lv1_enc7_b[4] = (~(lv1_inv_b[4] & lv0_or[9]));
assign lv1_enc7_b[5] = (~(lv1_inv_b[5] & lv0_or[11]));
assign lv1_enc7_b[6] = (~(lv1_inv_b[6] & lv0_or[13]));
assign lv1_enc7_b[7] = (~(lv1_inv_b[7] & lv0_or[15]));
assign lv1_enc7_b[8] = (~(lv1_inv_b[8] & lv0_or[17]));
assign lv1_enc7_b[9] = (~(lv1_inv_b[9] & lv0_or[19]));
assign lv1_enc7_b[10] = (~(lv1_inv_b[10] & lv0_or[21]));
assign lv1_enc7_b[11] = (~(lv1_inv_b[11] & lv0_or[23]));
assign lv1_enc7_b[12] = (~(lv1_inv_b[12] & lv0_or[25]));
assign lv1_enc7_b[13] = (~(lv1_inv_b[13] & lv0_or[27]));
assign lv1_enc7_b[14] = (~(lv1_inv_b[14] & lv0_or[29]));
assign lv1_enc7_b[15] = (~(lv1_inv_b[15] & lv0_or[31]));
assign lv1_enc7_b[16] = (~(lv1_inv_b[16] & lv0_or[33]));
assign lv1_enc7_b[17] = (~(lv1_inv_b[17] & lv0_or[35]));
assign lv1_enc7_b[18] = (~(lv1_inv_b[18] & lv0_or[37]));
assign lv1_enc7_b[19] = (~(lv1_inv_b[19] & lv0_or[39]));
assign lv1_enc7_b[20] = (~(lv1_inv_b[20] & lv0_or[41]));
assign lv1_enc7_b[21] = (~(lv1_inv_b[21] & lv0_or[43]));
assign lv1_enc7_b[22] = (~(lv1_inv_b[22] & lv0_or[45]));
assign lv1_enc7_b[23] = (~(lv1_inv_b[23] & lv0_or[47]));
assign lv1_enc7_b[24] = (~(lv1_inv_b[24] & lv0_or[49]));
assign lv1_enc7_b[25] = (~(lv1_inv_b[25] & lv0_or[51]));
assign lv1_enc7_b[26] = (~(lv1_inv_b[26] & lv0_or[53]));
assign lv1_enc7_b[27] = (~(lv1_inv_b[27] & lv0_or[55]));
assign lv1_enc7_b[28] = (~(lv1_inv_b[28] & lv0_or[57]));
assign lv1_enc7_b[29] = (~(lv1_inv_b[29] & lv0_or[59]));
assign lv1_enc7_b[30] = (~(lv1_inv_b[30] & lv0_or[61]));
assign lv1_enc7_b[31] = (~(lv1_inv_b[31] & lv0_or[63]));
assign lv1_enc7_b[32] = (~(lv1_inv_b[32] & lv0_or[65]));
assign lv1_enc7_b[33] = (~(lv1_inv_b[33] & lv0_or[67]));
assign lv1_enc7_b[34] = (~(lv1_inv_b[34] & lv0_or[69]));
assign lv1_enc7_b[35] = (~(lv1_inv_b[35] & lv0_or[71]));
assign lv1_enc7_b[36] = (~(lv1_inv_b[36] & lv0_or[73]));
assign lv1_enc7_b[37] = (~(lv1_inv_b[37] & lv0_or[75]));
assign lv1_enc7_b[38] = (~(lv1_inv_b[38] & lv0_or[77]));
assign lv1_enc7_b[39] = (~(lv1_inv_b[39] & lv0_or[79]));
assign lv1_enc7_b[40] = (~(lv1_inv_b[40] & lv0_or[81]));
assign lv1_enc7_b[41] = (~(lv1_inv_b[41] & lv0_or[83]));
assign lv1_enc7_b[42] = (~(lv1_inv_b[42] & lv0_or[85]));
assign lv1_enc7_b[43] = (~(lv1_inv_b[43] & lv0_or[87]));
assign lv1_enc7_b[44] = (~(lv1_inv_b[44] & lv0_or[89]));
assign lv1_enc7_b[45] = (~(lv1_inv_b[45] & lv0_or[91]));
assign lv1_enc7_b[46] = (~(lv1_inv_b[46] & lv0_or[93]));
assign lv1_enc7_b[47] = (~(lv1_inv_b[47] & lv0_or[95]));
assign lv1_enc7_b[48] = (~(lv1_inv_b[48] & lv0_or[97]));
assign lv1_enc7_b[49] = (~(lv1_inv_b[49] & lv0_or[99]));
assign lv1_enc7_b[50] = (~(lv1_inv_b[50] & lv0_or[101]));
assign lv1_enc7_b[51] = (~(lv1_inv_b[51] & lv0_or[103]));
assign lv1_enc7_b[52] = (~(lv1_inv_b[52] & lv0_or[105]));
assign lv1_enc7_b[53] = (~(lv1_inv_b[53] & lv0_or[107]));
assign lv1_enc7_b[54] = (~(lv1_inv_b[54] & lv0_or[109]));
assign lv1_enc7_b[55] = (~(lv1_inv_b[55] & lv0_or[111]));
assign lv1_enc7_b[56] = (~(lv1_inv_b[56] & lv0_or[113]));
assign lv1_enc7_b[57] = (~(lv1_inv_b[57] & lv0_or[115]));
assign lv1_enc7_b[58] = (~(lv1_inv_b[58] & lv0_or[117]));
assign lv1_enc7_b[59] = (~(lv1_inv_b[59] & lv0_or[119]));
assign lv1_enc7_b[60] = (~(lv1_inv_b[60] & lv0_or[121]));
assign lv1_enc7_b[61] = (~(lv1_inv_b[61] & lv0_or[123]));
assign lv1_enc7_b[62] = (~(lv1_inv_b[62] & lv0_or[125]));
assign lv1_enc7_b[63] = (~(lv1_inv_b[63] & lv0_or[127]));
assign lv1_enc7_b[64] = (~(lv1_inv_b[64] & lv0_or[129]));
assign lv1_enc7_b[65] = (~(lv1_inv_b[65] & lv0_or[131]));
assign lv1_enc7_b[66] = (~(lv1_inv_b[66] & lv0_or[133]));
assign lv1_enc7_b[67] = (~(lv1_inv_b[67] & lv0_or[135]));
assign lv1_enc7_b[68] = (~(lv1_inv_b[68] & lv0_or[137]));
assign lv1_enc7_b[69] = (~(lv1_inv_b[69] & lv0_or[139]));
assign lv1_enc7_b[70] = (~(lv1_inv_b[70] & lv0_or[141]));
assign lv1_enc7_b[71] = (~(lv1_inv_b[71] & lv0_or[143]));
assign lv1_enc7_b[72] = (~(lv1_inv_b[72] & lv0_or[145]));
assign lv1_enc7_b[73] = (~(lv1_inv_b[73] & lv0_or[147]));
assign lv1_enc7_b[74] = (~(lv1_inv_b[74] & lv0_or[149]));
assign lv1_enc7_b[75] = (~(lv1_inv_b[75] & lv0_or[151]));
assign lv1_enc7_b[76] = (~(lv1_inv_b[76] & lv0_or[153]));
assign lv1_enc7_b[77] = (~(lv1_inv_b[77] & lv0_or[155]));
assign lv1_enc7_b[78] = (~(lv1_inv_b[78] & lv0_or[157]));
assign lv1_enc7_b[79] = (~(lv1_inv_b[79] & lv0_or[159]));
assign lv1_enc7_b[80] = (~(lv1_inv_b[80] & lv0_or[161]));
assign lv1_enc7_b[81] = (~(lv1_inv_b[81])); //dflt1
//--------------------------------------------------------------------------------
// 004 bit group (phase_in=N, phase_out=P, level_in=lv1, level_out=lv2)
//--------------------------------------------------------------------------------
assign lv2_or[0] = (~(lv1_or_b[0] & lv1_or_b[1]));
assign lv2_or[1] = (~(lv1_or_b[2] & lv1_or_b[3]));
assign lv2_or[2] = (~(lv1_or_b[4] & lv1_or_b[5]));
assign lv2_or[3] = (~(lv1_or_b[6] & lv1_or_b[7]));
assign lv2_or[4] = (~(lv1_or_b[8] & lv1_or_b[9]));
assign lv2_or[5] = (~(lv1_or_b[10] & lv1_or_b[11]));
assign lv2_or[6] = (~(lv1_or_b[12] & lv1_or_b[13]));
assign lv2_or[7] = (~(lv1_or_b[14] & lv1_or_b[15]));
assign lv2_or[8] = (~(lv1_or_b[16] & lv1_or_b[17]));
assign lv2_or[9] = (~(lv1_or_b[18] & lv1_or_b[19]));
assign lv2_or[10] = (~(lv1_or_b[20] & lv1_or_b[21]));
assign lv2_or[11] = (~(lv1_or_b[22] & lv1_or_b[23]));
assign lv2_or[12] = (~(lv1_or_b[24] & lv1_or_b[25]));
assign lv2_or[13] = (~(lv1_or_b[26] & lv1_or_b[27]));
assign lv2_or[14] = (~(lv1_or_b[28] & lv1_or_b[29]));
assign lv2_or[15] = (~(lv1_or_b[30] & lv1_or_b[31]));
assign lv2_or[16] = (~(lv1_or_b[32] & lv1_or_b[33]));
assign lv2_or[17] = (~(lv1_or_b[34] & lv1_or_b[35]));
assign lv2_or[18] = (~(lv1_or_b[36] & lv1_or_b[37]));
assign lv2_or[19] = (~(lv1_or_b[38] & lv1_or_b[39]));
assign lv2_or[20] = (~(lv1_or_b[40] & lv1_or_b[41]));
assign lv2_or[21] = (~(lv1_or_b[42] & lv1_or_b[43]));
assign lv2_or[22] = (~(lv1_or_b[44] & lv1_or_b[45]));
assign lv2_or[23] = (~(lv1_or_b[46] & lv1_or_b[47]));
assign lv2_or[24] = (~(lv1_or_b[48] & lv1_or_b[49]));
assign lv2_or[25] = (~(lv1_or_b[50] & lv1_or_b[51]));
assign lv2_or[26] = (~(lv1_or_b[52] & lv1_or_b[53]));
assign lv2_or[27] = (~(lv1_or_b[54] & lv1_or_b[55]));
assign lv2_or[28] = (~(lv1_or_b[56] & lv1_or_b[57]));
assign lv2_or[29] = (~(lv1_or_b[58] & lv1_or_b[59]));
assign lv2_or[30] = (~(lv1_or_b[60] & lv1_or_b[61]));
assign lv2_or[31] = (~(lv1_or_b[62] & lv1_or_b[63]));
assign lv2_or[32] = (~(lv1_or_b[64] & lv1_or_b[65]));
assign lv2_or[33] = (~(lv1_or_b[66] & lv1_or_b[67]));
assign lv2_or[34] = (~(lv1_or_b[68] & lv1_or_b[69]));
assign lv2_or[35] = (~(lv1_or_b[70] & lv1_or_b[71]));
assign lv2_or[36] = (~(lv1_or_b[72] & lv1_or_b[73]));
assign lv2_or[37] = (~(lv1_or_b[74] & lv1_or_b[75]));
assign lv2_or[38] = (~(lv1_or_b[76] & lv1_or_b[77]));
assign lv2_or[39] = (~(lv1_or_b[78] & lv1_or_b[79]));
assign lv2_or[40] = (~(lv1_or_b[80] & lv1_or_b[81]));
assign lv2_inv[0] = (~(lv1_or_b[0]));
assign lv2_inv[1] = (~(lv1_or_b[2]));
assign lv2_inv[2] = (~(lv1_or_b[4]));
assign lv2_inv[3] = (~(lv1_or_b[6]));
assign lv2_inv[4] = (~(lv1_or_b[8]));
assign lv2_inv[5] = (~(lv1_or_b[10]));
assign lv2_inv[6] = (~(lv1_or_b[12]));
assign lv2_inv[7] = (~(lv1_or_b[14]));
assign lv2_inv[8] = (~(lv1_or_b[16]));
assign lv2_inv[9] = (~(lv1_or_b[18]));
assign lv2_inv[10] = (~(lv1_or_b[20]));
assign lv2_inv[11] = (~(lv1_or_b[22]));
assign lv2_inv[12] = (~(lv1_or_b[24]));
assign lv2_inv[13] = (~(lv1_or_b[26]));
assign lv2_inv[14] = (~(lv1_or_b[28]));
assign lv2_inv[15] = (~(lv1_or_b[30]));
assign lv2_inv[16] = (~(lv1_or_b[32]));
assign lv2_inv[17] = (~(lv1_or_b[34]));
assign lv2_inv[18] = (~(lv1_or_b[36]));
assign lv2_inv[19] = (~(lv1_or_b[38]));
assign lv2_inv[20] = (~(lv1_or_b[40]));
assign lv2_inv[21] = (~(lv1_or_b[42]));
assign lv2_inv[22] = (~(lv1_or_b[44]));
assign lv2_inv[23] = (~(lv1_or_b[46]));
assign lv2_inv[24] = (~(lv1_or_b[48]));
assign lv2_inv[25] = (~(lv1_or_b[50]));
assign lv2_inv[26] = (~(lv1_or_b[52]));
assign lv2_inv[27] = (~(lv1_or_b[54]));
assign lv2_inv[28] = (~(lv1_or_b[56]));
assign lv2_inv[29] = (~(lv1_or_b[58]));
assign lv2_inv[30] = (~(lv1_or_b[60]));
assign lv2_inv[31] = (~(lv1_or_b[62]));
assign lv2_inv[32] = (~(lv1_or_b[64]));
assign lv2_inv[33] = (~(lv1_or_b[66]));
assign lv2_inv[34] = (~(lv1_or_b[68]));
assign lv2_inv[35] = (~(lv1_or_b[70]));
assign lv2_inv[36] = (~(lv1_or_b[72]));
assign lv2_inv[37] = (~(lv1_or_b[74]));
assign lv2_inv[38] = (~(lv1_or_b[76]));
assign lv2_inv[39] = (~(lv1_or_b[78]));
assign lv2_inv[40] = (~(lv1_or_b[80]));
assign lv2_enc6[0] = (~(lv2_inv[0] | lv1_or_b[1]));
assign lv2_enc6[1] = (~(lv2_inv[1] | lv1_or_b[3]));
assign lv2_enc6[2] = (~(lv2_inv[2] | lv1_or_b[5]));
assign lv2_enc6[3] = (~(lv2_inv[3] | lv1_or_b[7]));
assign lv2_enc6[4] = (~(lv2_inv[4] | lv1_or_b[9]));
assign lv2_enc6[5] = (~(lv2_inv[5] | lv1_or_b[11]));
assign lv2_enc6[6] = (~(lv2_inv[6] | lv1_or_b[13]));
assign lv2_enc6[7] = (~(lv2_inv[7] | lv1_or_b[15]));
assign lv2_enc6[8] = (~(lv2_inv[8] | lv1_or_b[17]));
assign lv2_enc6[9] = (~(lv2_inv[9] | lv1_or_b[19]));
assign lv2_enc6[10] = (~(lv2_inv[10] | lv1_or_b[21]));
assign lv2_enc6[11] = (~(lv2_inv[11] | lv1_or_b[23]));
assign lv2_enc6[12] = (~(lv2_inv[12] | lv1_or_b[25]));
assign lv2_enc6[13] = (~(lv2_inv[13] | lv1_or_b[27]));
assign lv2_enc6[14] = (~(lv2_inv[14] | lv1_or_b[29]));
assign lv2_enc6[15] = (~(lv2_inv[15] | lv1_or_b[31]));
assign lv2_enc6[16] = (~(lv2_inv[16] | lv1_or_b[33]));
assign lv2_enc6[17] = (~(lv2_inv[17] | lv1_or_b[35]));
assign lv2_enc6[18] = (~(lv2_inv[18] | lv1_or_b[37]));
assign lv2_enc6[19] = (~(lv2_inv[19] | lv1_or_b[39]));
assign lv2_enc6[20] = (~(lv2_inv[20] | lv1_or_b[41]));
assign lv2_enc6[21] = (~(lv2_inv[21] | lv1_or_b[43]));
assign lv2_enc6[22] = (~(lv2_inv[22] | lv1_or_b[45]));
assign lv2_enc6[23] = (~(lv2_inv[23] | lv1_or_b[47]));
assign lv2_enc6[24] = (~(lv2_inv[24] | lv1_or_b[49]));
assign lv2_enc6[25] = (~(lv2_inv[25] | lv1_or_b[51]));
assign lv2_enc6[26] = (~(lv2_inv[26] | lv1_or_b[53]));
assign lv2_enc6[27] = (~(lv2_inv[27] | lv1_or_b[55]));
assign lv2_enc6[28] = (~(lv2_inv[28] | lv1_or_b[57]));
assign lv2_enc6[29] = (~(lv2_inv[29] | lv1_or_b[59]));
assign lv2_enc6[30] = (~(lv2_inv[30] | lv1_or_b[61]));
assign lv2_enc6[31] = (~(lv2_inv[31] | lv1_or_b[63]));
assign lv2_enc6[32] = (~(lv2_inv[32] | lv1_or_b[65]));
assign lv2_enc6[33] = (~(lv2_inv[33] | lv1_or_b[67]));
assign lv2_enc6[34] = (~(lv2_inv[34] | lv1_or_b[69]));
assign lv2_enc6[35] = (~(lv2_inv[35] | lv1_or_b[71]));
assign lv2_enc6[36] = (~(lv2_inv[36] | lv1_or_b[73]));
assign lv2_enc6[37] = (~(lv2_inv[37] | lv1_or_b[75]));
assign lv2_enc6[38] = (~(lv2_inv[38] | lv1_or_b[77]));
assign lv2_enc6[39] = (~(lv2_inv[39] | lv1_or_b[79]));
assign lv2_enc6[40] = (~(lv2_inv[40])); //dflt1
assign lv2_enc7[0] = (~(lv1_enc7_b[0] & (lv1_enc7_b[1] | lv2_inv[0])));
assign lv2_enc7[1] = (~(lv1_enc7_b[2] & (lv1_enc7_b[3] | lv2_inv[1])));
assign lv2_enc7[2] = (~(lv1_enc7_b[4] & (lv1_enc7_b[5] | lv2_inv[2])));
assign lv2_enc7[3] = (~(lv1_enc7_b[6] & (lv1_enc7_b[7] | lv2_inv[3])));
assign lv2_enc7[4] = (~(lv1_enc7_b[8] & (lv1_enc7_b[9] | lv2_inv[4])));
assign lv2_enc7[5] = (~(lv1_enc7_b[10] & (lv1_enc7_b[11] | lv2_inv[5])));
assign lv2_enc7[6] = (~(lv1_enc7_b[12] & (lv1_enc7_b[13] | lv2_inv[6])));
assign lv2_enc7[7] = (~(lv1_enc7_b[14] & (lv1_enc7_b[15] | lv2_inv[7])));
assign lv2_enc7[8] = (~(lv1_enc7_b[16] & (lv1_enc7_b[17] | lv2_inv[8])));
assign lv2_enc7[9] = (~(lv1_enc7_b[18] & (lv1_enc7_b[19] | lv2_inv[9])));
assign lv2_enc7[10] = (~(lv1_enc7_b[20] & (lv1_enc7_b[21] | lv2_inv[10])));
assign lv2_enc7[11] = (~(lv1_enc7_b[22] & (lv1_enc7_b[23] | lv2_inv[11])));
assign lv2_enc7[12] = (~(lv1_enc7_b[24] & (lv1_enc7_b[25] | lv2_inv[12])));
assign lv2_enc7[13] = (~(lv1_enc7_b[26] & (lv1_enc7_b[27] | lv2_inv[13])));
assign lv2_enc7[14] = (~(lv1_enc7_b[28] & (lv1_enc7_b[29] | lv2_inv[14])));
assign lv2_enc7[15] = (~(lv1_enc7_b[30] & (lv1_enc7_b[31] | lv2_inv[15])));
assign lv2_enc7[16] = (~(lv1_enc7_b[32] & (lv1_enc7_b[33] | lv2_inv[16])));
assign lv2_enc7[17] = (~(lv1_enc7_b[34] & (lv1_enc7_b[35] | lv2_inv[17])));
assign lv2_enc7[18] = (~(lv1_enc7_b[36] & (lv1_enc7_b[37] | lv2_inv[18])));
assign lv2_enc7[19] = (~(lv1_enc7_b[38] & (lv1_enc7_b[39] | lv2_inv[19])));
assign lv2_enc7[20] = (~(lv1_enc7_b[40] & (lv1_enc7_b[41] | lv2_inv[20])));
assign lv2_enc7[21] = (~(lv1_enc7_b[42] & (lv1_enc7_b[43] | lv2_inv[21])));
assign lv2_enc7[22] = (~(lv1_enc7_b[44] & (lv1_enc7_b[45] | lv2_inv[22])));
assign lv2_enc7[23] = (~(lv1_enc7_b[46] & (lv1_enc7_b[47] | lv2_inv[23])));
assign lv2_enc7[24] = (~(lv1_enc7_b[48] & (lv1_enc7_b[49] | lv2_inv[24])));
assign lv2_enc7[25] = (~(lv1_enc7_b[50] & (lv1_enc7_b[51] | lv2_inv[25])));
assign lv2_enc7[26] = (~(lv1_enc7_b[52] & (lv1_enc7_b[53] | lv2_inv[26])));
assign lv2_enc7[27] = (~(lv1_enc7_b[54] & (lv1_enc7_b[55] | lv2_inv[27])));
assign lv2_enc7[28] = (~(lv1_enc7_b[56] & (lv1_enc7_b[57] | lv2_inv[28])));
assign lv2_enc7[29] = (~(lv1_enc7_b[58] & (lv1_enc7_b[59] | lv2_inv[29])));
assign lv2_enc7[30] = (~(lv1_enc7_b[60] & (lv1_enc7_b[61] | lv2_inv[30])));
assign lv2_enc7[31] = (~(lv1_enc7_b[62] & (lv1_enc7_b[63] | lv2_inv[31])));
assign lv2_enc7[32] = (~(lv1_enc7_b[64] & (lv1_enc7_b[65] | lv2_inv[32])));
assign lv2_enc7[33] = (~(lv1_enc7_b[66] & (lv1_enc7_b[67] | lv2_inv[33])));
assign lv2_enc7[34] = (~(lv1_enc7_b[68] & (lv1_enc7_b[69] | lv2_inv[34])));
assign lv2_enc7[35] = (~(lv1_enc7_b[70] & (lv1_enc7_b[71] | lv2_inv[35])));
assign lv2_enc7[36] = (~(lv1_enc7_b[72] & (lv1_enc7_b[73] | lv2_inv[36])));
assign lv2_enc7[37] = (~(lv1_enc7_b[74] & (lv1_enc7_b[75] | lv2_inv[37])));
assign lv2_enc7[38] = (~(lv1_enc7_b[76] & (lv1_enc7_b[77] | lv2_inv[38])));
assign lv2_enc7[39] = (~(lv1_enc7_b[78] & (lv1_enc7_b[79] | lv2_inv[39])));
assign lv2_enc7[40] = (~(lv1_enc7_b[80] & (lv1_enc7_b[81] | lv2_inv[40])));
//--------------------------------------------------------------------------------
// 008 bit group (phase_in=P, phase_out=N, level_in=lv2, level_out=lv3)
//--------------------------------------------------------------------------------
assign lv3_or_b[0] = (~(lv2_or[0] | lv2_or[1]));
assign lv3_or_b[1] = (~(lv2_or[2] | lv2_or[3]));
assign lv3_or_b[2] = (~(lv2_or[4] | lv2_or[5]));
assign lv3_or_b[3] = (~(lv2_or[6] | lv2_or[7]));
assign lv3_or_b[4] = (~(lv2_or[8] | lv2_or[9]));
assign lv3_or_b[5] = (~(lv2_or[10] | lv2_or[11]));
assign lv3_or_b[6] = (~(lv2_or[12] | lv2_or[13]));
assign lv3_or_b[7] = (~(lv2_or[14] | lv2_or[15]));
assign lv3_or_b[8] = (~(lv2_or[16] | lv2_or[17]));
assign lv3_or_b[9] = (~(lv2_or[18] | lv2_or[19]));
assign lv3_or_b[10] = (~(lv2_or[20] | lv2_or[21]));
assign lv3_or_b[11] = (~(lv2_or[22] | lv2_or[23]));
assign lv3_or_b[12] = (~(lv2_or[24] | lv2_or[25]));
assign lv3_or_b[13] = (~(lv2_or[26] | lv2_or[27]));
assign lv3_or_b[14] = (~(lv2_or[28] | lv2_or[29]));
assign lv3_or_b[15] = (~(lv2_or[30] | lv2_or[31]));
assign lv3_or_b[16] = (~(lv2_or[32] | lv2_or[33]));
assign lv3_or_b[17] = (~(lv2_or[34] | lv2_or[35]));
assign lv3_or_b[18] = (~(lv2_or[36] | lv2_or[37]));
assign lv3_or_b[19] = (~(lv2_or[38] | lv2_or[39]));
assign lv3_or_b[20] = (~(lv2_or[40]));
assign lv3_inv_b[0] = (~(lv2_or[0]));
assign lv3_inv_b[1] = (~(lv2_or[2]));
assign lv3_inv_b[2] = (~(lv2_or[4]));
assign lv3_inv_b[3] = (~(lv2_or[6]));
assign lv3_inv_b[4] = (~(lv2_or[8]));
assign lv3_inv_b[5] = (~(lv2_or[10]));
assign lv3_inv_b[6] = (~(lv2_or[12]));
assign lv3_inv_b[7] = (~(lv2_or[14]));
assign lv3_inv_b[8] = (~(lv2_or[16]));
assign lv3_inv_b[9] = (~(lv2_or[18]));
assign lv3_inv_b[10] = (~(lv2_or[20]));
assign lv3_inv_b[11] = (~(lv2_or[22]));
assign lv3_inv_b[12] = (~(lv2_or[24]));
assign lv3_inv_b[13] = (~(lv2_or[26]));
assign lv3_inv_b[14] = (~(lv2_or[28]));
assign lv3_inv_b[15] = (~(lv2_or[30]));
assign lv3_inv_b[16] = (~(lv2_or[32]));
assign lv3_inv_b[17] = (~(lv2_or[34]));
assign lv3_inv_b[18] = (~(lv2_or[36]));
assign lv3_inv_b[19] = (~(lv2_or[38]));
assign lv3_inv_b[20] = (~(lv2_or[40]));
assign lv3_enc5_b[0] = (~(lv3_inv_b[0] & lv2_or[1]));
assign lv3_enc5_b[1] = (~(lv3_inv_b[1] & lv2_or[3]));
assign lv3_enc5_b[2] = (~(lv3_inv_b[2] & lv2_or[5]));
assign lv3_enc5_b[3] = (~(lv3_inv_b[3] & lv2_or[7]));
assign lv3_enc5_b[4] = (~(lv3_inv_b[4] & lv2_or[9]));
assign lv3_enc5_b[5] = (~(lv3_inv_b[5] & lv2_or[11]));
assign lv3_enc5_b[6] = (~(lv3_inv_b[6] & lv2_or[13]));
assign lv3_enc5_b[7] = (~(lv3_inv_b[7] & lv2_or[15]));
assign lv3_enc5_b[8] = (~(lv3_inv_b[8] & lv2_or[17]));
assign lv3_enc5_b[9] = (~(lv3_inv_b[9] & lv2_or[19]));
assign lv3_enc5_b[10] = (~(lv3_inv_b[10] & lv2_or[21]));
assign lv3_enc5_b[11] = (~(lv3_inv_b[11] & lv2_or[23]));
assign lv3_enc5_b[12] = (~(lv3_inv_b[12] & lv2_or[25]));
assign lv3_enc5_b[13] = (~(lv3_inv_b[13] & lv2_or[27]));
assign lv3_enc5_b[14] = (~(lv3_inv_b[14] & lv2_or[29]));
assign lv3_enc5_b[15] = (~(lv3_inv_b[15] & lv2_or[31]));
assign lv3_enc5_b[16] = (~(lv3_inv_b[16] & lv2_or[33]));
assign lv3_enc5_b[17] = (~(lv3_inv_b[17] & lv2_or[35]));
assign lv3_enc5_b[18] = (~(lv3_inv_b[18] & lv2_or[37]));
assign lv3_enc5_b[19] = (~(lv3_inv_b[19] & lv2_or[39]));
assign lv3_enc5_b[20] = tiup; //dflt0
assign lv3_enc6_b[0] = (~(lv2_enc6[0] | (lv2_enc6[1] & lv3_inv_b[0])));
assign lv3_enc6_b[1] = (~(lv2_enc6[2] | (lv2_enc6[3] & lv3_inv_b[1])));
assign lv3_enc6_b[2] = (~(lv2_enc6[4] | (lv2_enc6[5] & lv3_inv_b[2])));
assign lv3_enc6_b[3] = (~(lv2_enc6[6] | (lv2_enc6[7] & lv3_inv_b[3])));
assign lv3_enc6_b[4] = (~(lv2_enc6[8] | (lv2_enc6[9] & lv3_inv_b[4])));
assign lv3_enc6_b[5] = (~(lv2_enc6[10] | (lv2_enc6[11] & lv3_inv_b[5])));
assign lv3_enc6_b[6] = (~(lv2_enc6[12] | (lv2_enc6[13] & lv3_inv_b[6])));
assign lv3_enc6_b[7] = (~(lv2_enc6[14] | (lv2_enc6[15] & lv3_inv_b[7])));
assign lv3_enc6_b[8] = (~(lv2_enc6[16] | (lv2_enc6[17] & lv3_inv_b[8])));
assign lv3_enc6_b[9] = (~(lv2_enc6[18] | (lv2_enc6[19] & lv3_inv_b[9])));
assign lv3_enc6_b[10] = (~(lv2_enc6[20] | (lv2_enc6[21] & lv3_inv_b[10])));
assign lv3_enc6_b[11] = (~(lv2_enc6[22] | (lv2_enc6[23] & lv3_inv_b[11])));
assign lv3_enc6_b[12] = (~(lv2_enc6[24] | (lv2_enc6[25] & lv3_inv_b[12])));
assign lv3_enc6_b[13] = (~(lv2_enc6[26] | (lv2_enc6[27] & lv3_inv_b[13])));
assign lv3_enc6_b[14] = (~(lv2_enc6[28] | (lv2_enc6[29] & lv3_inv_b[14])));
assign lv3_enc6_b[15] = (~(lv2_enc6[30] | (lv2_enc6[31] & lv3_inv_b[15])));
assign lv3_enc6_b[16] = (~(lv2_enc6[32] | (lv2_enc6[33] & lv3_inv_b[16])));
assign lv3_enc6_b[17] = (~(lv2_enc6[34] | (lv2_enc6[35] & lv3_inv_b[17])));
assign lv3_enc6_b[18] = (~(lv2_enc6[36] | (lv2_enc6[37] & lv3_inv_b[18])));
assign lv3_enc6_b[19] = (~(lv2_enc6[38] | (lv2_enc6[39] & lv3_inv_b[19])));
assign lv3_enc6_b[20] = (~(lv2_enc6[40] | lv3_inv_b[20])); //dflt1
assign lv3_enc7_b[0] = (~(lv2_enc7[0] | (lv2_enc7[1] & lv3_inv_b[0])));
assign lv3_enc7_b[1] = (~(lv2_enc7[2] | (lv2_enc7[3] & lv3_inv_b[1])));
assign lv3_enc7_b[2] = (~(lv2_enc7[4] | (lv2_enc7[5] & lv3_inv_b[2])));
assign lv3_enc7_b[3] = (~(lv2_enc7[6] | (lv2_enc7[7] & lv3_inv_b[3])));
assign lv3_enc7_b[4] = (~(lv2_enc7[8] | (lv2_enc7[9] & lv3_inv_b[4])));
assign lv3_enc7_b[5] = (~(lv2_enc7[10] | (lv2_enc7[11] & lv3_inv_b[5])));
assign lv3_enc7_b[6] = (~(lv2_enc7[12] | (lv2_enc7[13] & lv3_inv_b[6])));
assign lv3_enc7_b[7] = (~(lv2_enc7[14] | (lv2_enc7[15] & lv3_inv_b[7])));
assign lv3_enc7_b[8] = (~(lv2_enc7[16] | (lv2_enc7[17] & lv3_inv_b[8])));
assign lv3_enc7_b[9] = (~(lv2_enc7[18] | (lv2_enc7[19] & lv3_inv_b[9])));
assign lv3_enc7_b[10] = (~(lv2_enc7[20] | (lv2_enc7[21] & lv3_inv_b[10])));
assign lv3_enc7_b[11] = (~(lv2_enc7[22] | (lv2_enc7[23] & lv3_inv_b[11])));
assign lv3_enc7_b[12] = (~(lv2_enc7[24] | (lv2_enc7[25] & lv3_inv_b[12])));
assign lv3_enc7_b[13] = (~(lv2_enc7[26] | (lv2_enc7[27] & lv3_inv_b[13])));
assign lv3_enc7_b[14] = (~(lv2_enc7[28] | (lv2_enc7[29] & lv3_inv_b[14])));
assign lv3_enc7_b[15] = (~(lv2_enc7[30] | (lv2_enc7[31] & lv3_inv_b[15])));
assign lv3_enc7_b[16] = (~(lv2_enc7[32] | (lv2_enc7[33] & lv3_inv_b[16])));
assign lv3_enc7_b[17] = (~(lv2_enc7[34] | (lv2_enc7[35] & lv3_inv_b[17])));
assign lv3_enc7_b[18] = (~(lv2_enc7[36] | (lv2_enc7[37] & lv3_inv_b[18])));
assign lv3_enc7_b[19] = (~(lv2_enc7[38] | (lv2_enc7[39] & lv3_inv_b[19])));
assign lv3_enc7_b[20] = (~(lv2_enc7[40] | lv3_inv_b[20])); //dflt1
//--------------------------------------------------------------------------------
// 016 bit group (phase_in=N, phase_out=P, level_in=lv3, level_out=lv4)
//--------------------------------------------------------------------------------
assign lv4_or[0] = (~(lv3_or_b[0] & lv3_or_b[1]));
assign lv4_or[1] = (~(lv3_or_b[2] & lv3_or_b[3]));
assign lv4_or[2] = (~(lv3_or_b[4] & lv3_or_b[5]));
assign lv4_or[3] = (~(lv3_or_b[6] & lv3_or_b[7]));
assign lv4_or[4] = (~(lv3_or_b[8] & lv3_or_b[9]));
assign lv4_or[5] = (~(lv3_or_b[10] & lv3_or_b[11]));
assign lv4_or[6] = (~(lv3_or_b[12] & lv3_or_b[13]));
assign lv4_or[7] = (~(lv3_or_b[14] & lv3_or_b[15]));
assign lv4_or[8] = (~(lv3_or_b[16] & lv3_or_b[17]));
assign lv4_or[9] = (~(lv3_or_b[18] & lv3_or_b[19]));
assign lv4_or[10] = (~(lv3_or_b[20]));
assign lv4_inv[0] = (~(lv3_or_b[0]));
assign lv4_inv[1] = (~(lv3_or_b[2]));
assign lv4_inv[2] = (~(lv3_or_b[4]));
assign lv4_inv[3] = (~(lv3_or_b[6]));
assign lv4_inv[4] = (~(lv3_or_b[8]));
assign lv4_inv[5] = (~(lv3_or_b[10]));
assign lv4_inv[6] = (~(lv3_or_b[12]));
assign lv4_inv[7] = (~(lv3_or_b[14]));
assign lv4_inv[8] = (~(lv3_or_b[16]));
assign lv4_inv[9] = (~(lv3_or_b[18]));
assign lv4_inv[10] = (~(lv3_or_b[20]));
assign lv4_enc4[0] = (~(lv4_inv[0] | lv3_or_b[1]));
assign lv4_enc4[1] = (~(lv4_inv[1] | lv3_or_b[3]));
assign lv4_enc4[2] = (~(lv4_inv[2] | lv3_or_b[5]));
assign lv4_enc4[3] = (~(lv4_inv[3] | lv3_or_b[7]));
assign lv4_enc4[4] = (~(lv4_inv[4] | lv3_or_b[9]));
assign lv4_enc4[5] = (~(lv4_inv[5] | lv3_or_b[11]));
assign lv4_enc4[6] = (~(lv4_inv[6] | lv3_or_b[13]));
assign lv4_enc4[7] = (~(lv4_inv[7] | lv3_or_b[15]));
assign lv4_enc4[8] = (~(lv4_inv[8] | lv3_or_b[17]));
assign lv4_enc4[9] = (~(lv4_inv[9] | lv3_or_b[19]));
assign lv4_enc4[10] = tidn; //dflt0
assign lv4_enc5[0] = (~(lv3_enc5_b[0] & (lv3_enc5_b[1] | lv4_inv[0])));
assign lv4_enc5[1] = (~(lv3_enc5_b[2] & (lv3_enc5_b[3] | lv4_inv[1])));
assign lv4_enc5[2] = (~(lv3_enc5_b[4] & (lv3_enc5_b[5] | lv4_inv[2])));
assign lv4_enc5[3] = (~(lv3_enc5_b[6] & (lv3_enc5_b[7] | lv4_inv[3])));
assign lv4_enc5[4] = (~(lv3_enc5_b[8] & (lv3_enc5_b[9] | lv4_inv[4])));
assign lv4_enc5[5] = (~(lv3_enc5_b[10] & (lv3_enc5_b[11] | lv4_inv[5])));
assign lv4_enc5[6] = (~(lv3_enc5_b[12] & (lv3_enc5_b[13] | lv4_inv[6])));
assign lv4_enc5[7] = (~(lv3_enc5_b[14] & (lv3_enc5_b[15] | lv4_inv[7])));
assign lv4_enc5[8] = (~(lv3_enc5_b[16] & (lv3_enc5_b[17] | lv4_inv[8])));
assign lv4_enc5[9] = (~(lv3_enc5_b[18] & (lv3_enc5_b[19] | lv4_inv[9])));
assign lv4_enc5[10] = (~(lv3_enc5_b[20])); //dflt0 pass
assign lv4_enc6[0] = (~(lv3_enc6_b[0] & (lv3_enc6_b[1] | lv4_inv[0])));
assign lv4_enc6[1] = (~(lv3_enc6_b[2] & (lv3_enc6_b[3] | lv4_inv[1])));
assign lv4_enc6[2] = (~(lv3_enc6_b[4] & (lv3_enc6_b[5] | lv4_inv[2])));
assign lv4_enc6[3] = (~(lv3_enc6_b[6] & (lv3_enc6_b[7] | lv4_inv[3])));
assign lv4_enc6[4] = (~(lv3_enc6_b[8] & (lv3_enc6_b[9] | lv4_inv[4])));
assign lv4_enc6[5] = (~(lv3_enc6_b[10] & (lv3_enc6_b[11] | lv4_inv[5])));
assign lv4_enc6[6] = (~(lv3_enc6_b[12] & (lv3_enc6_b[13] | lv4_inv[6])));
assign lv4_enc6[7] = (~(lv3_enc6_b[14] & (lv3_enc6_b[15] | lv4_inv[7])));
assign lv4_enc6[8] = (~(lv3_enc6_b[16] & (lv3_enc6_b[17] | lv4_inv[8])));
assign lv4_enc6[9] = (~(lv3_enc6_b[18] & (lv3_enc6_b[19] | lv4_inv[9])));
assign lv4_enc6[10] = (~(lv3_enc6_b[20] & lv4_inv[10])); //dflt1
assign lv4_enc7[0] = (~(lv3_enc7_b[0] & (lv3_enc7_b[1] | lv4_inv[0])));
assign lv4_enc7[1] = (~(lv3_enc7_b[2] & (lv3_enc7_b[3] | lv4_inv[1])));
assign lv4_enc7[2] = (~(lv3_enc7_b[4] & (lv3_enc7_b[5] | lv4_inv[2])));
assign lv4_enc7[3] = (~(lv3_enc7_b[6] & (lv3_enc7_b[7] | lv4_inv[3])));
assign lv4_enc7[4] = (~(lv3_enc7_b[8] & (lv3_enc7_b[9] | lv4_inv[4])));
assign lv4_enc7[5] = (~(lv3_enc7_b[10] & (lv3_enc7_b[11] | lv4_inv[5])));
assign lv4_enc7[6] = (~(lv3_enc7_b[12] & (lv3_enc7_b[13] | lv4_inv[6])));
assign lv4_enc7[7] = (~(lv3_enc7_b[14] & (lv3_enc7_b[15] | lv4_inv[7])));
assign lv4_enc7[8] = (~(lv3_enc7_b[16] & (lv3_enc7_b[17] | lv4_inv[8])));
assign lv4_enc7[9] = (~(lv3_enc7_b[18] & (lv3_enc7_b[19] | lv4_inv[9])));
assign lv4_enc7[10] = (~(lv3_enc7_b[20] & lv4_inv[10])); //dflt1
assign lv4_or_b[0] = (~(lv4_or[0])); //repower,long wire
assign lv4_or_b[1] = (~(lv4_or[1])); //repower,long wire
assign lv4_or_b[2] = (~(lv4_or[2])); //repower,long wire
assign lv4_or_b[3] = (~(lv4_or[3])); //repower,long wire
assign lv4_or_b[4] = (~(lv4_or[4])); //repower,long wire
assign lv4_or_b[5] = (~(lv4_or[5])); //repower,long wire
assign lv4_or_b[6] = (~(lv4_or[6])); //repower,long wire
assign lv4_or_b[7] = (~(lv4_or[7])); //repower,long wire
assign lv4_or_b[8] = (~(lv4_or[8])); //repower,long wire
assign lv4_or_b[9] = (~(lv4_or[9])); //repower,long wire
assign lv4_or_b[10] = (~(lv4_or[10])); //repower,long wire
assign lv4_enc4_b[0] = (~(lv4_enc4[0])); //repower,long wire
assign lv4_enc4_b[1] = (~(lv4_enc4[1])); //repower,long wire
assign lv4_enc4_b[2] = (~(lv4_enc4[2])); //repower,long wire
assign lv4_enc4_b[3] = (~(lv4_enc4[3])); //repower,long wire
assign lv4_enc4_b[4] = (~(lv4_enc4[4])); //repower,long wire
assign lv4_enc4_b[5] = (~(lv4_enc4[5])); //repower,long wire
assign lv4_enc4_b[6] = (~(lv4_enc4[6])); //repower,long wire
assign lv4_enc4_b[7] = (~(lv4_enc4[7])); //repower,long wire
assign lv4_enc4_b[8] = (~(lv4_enc4[8])); //repower,long wire
assign lv4_enc4_b[9] = (~(lv4_enc4[9])); //repower,long wire
assign lv4_enc4_b[10] = (~(lv4_enc4[10])); //repower,long wire
assign lv4_enc5_b[0] = (~(lv4_enc5[0])); //repower,long wire
assign lv4_enc5_b[1] = (~(lv4_enc5[1])); //repower,long wire
assign lv4_enc5_b[2] = (~(lv4_enc5[2])); //repower,long wire
assign lv4_enc5_b[3] = (~(lv4_enc5[3])); //repower,long wire
assign lv4_enc5_b[4] = (~(lv4_enc5[4])); //repower,long wire
assign lv4_enc5_b[5] = (~(lv4_enc5[5])); //repower,long wire
assign lv4_enc5_b[6] = (~(lv4_enc5[6])); //repower,long wire
assign lv4_enc5_b[7] = (~(lv4_enc5[7])); //repower,long wire
assign lv4_enc5_b[8] = (~(lv4_enc5[8])); //repower,long wire
assign lv4_enc5_b[9] = (~(lv4_enc5[9])); //repower,long wire
assign lv4_enc5_b[10] = (~(lv4_enc5[10])); //repower,long wire
assign lv4_enc6_b[0] = (~(lv4_enc6[0])); //repower,long wire
assign lv4_enc6_b[1] = (~(lv4_enc6[1])); //repower,long wire
assign lv4_enc6_b[2] = (~(lv4_enc6[2])); //repower,long wire
assign lv4_enc6_b[3] = (~(lv4_enc6[3])); //repower,long wire
assign lv4_enc6_b[4] = (~(lv4_enc6[4])); //repower,long wire
assign lv4_enc6_b[5] = (~(lv4_enc6[5])); //repower,long wire
assign lv4_enc6_b[6] = (~(lv4_enc6[6])); //repower,long wire
assign lv4_enc6_b[7] = (~(lv4_enc6[7])); //repower,long wire
assign lv4_enc6_b[8] = (~(lv4_enc6[8])); //repower,long wire
assign lv4_enc6_b[9] = (~(lv4_enc6[9])); //repower,long wire
assign lv4_enc6_b[10] = (~(lv4_enc6[10])); //repower,long wire
assign lv4_enc7_b[0] = (~(lv4_enc7[0])); //repower,long wire
assign lv4_enc7_b[1] = (~(lv4_enc7[1])); //repower,long wire
assign lv4_enc7_b[2] = (~(lv4_enc7[2])); //repower,long wire
assign lv4_enc7_b[3] = (~(lv4_enc7[3])); //repower,long wire
assign lv4_enc7_b[4] = (~(lv4_enc7[4])); //repower,long wire
assign lv4_enc7_b[5] = (~(lv4_enc7[5])); //repower,long wire
assign lv4_enc7_b[6] = (~(lv4_enc7[6])); //repower,long wire
assign lv4_enc7_b[7] = (~(lv4_enc7[7])); //repower,long wire
assign lv4_enc7_b[8] = (~(lv4_enc7[8])); //repower,long wire
assign lv4_enc7_b[9] = (~(lv4_enc7[9])); //repower,long wire
assign lv4_enc7_b[10] = (~(lv4_enc7[10])); //repower,long wire
//--------------------------------------------------------------------------------
// 032 bit group (phase_in=N, phase_out=P, level_in=lv4, level_out=lv5)
//--------------------------------------------------------------------------------
assign lv5_or[0] = (~(lv4_or_b[0] & lv4_or_b[1]));
assign lv5_or[1] = (~(lv4_or_b[2] & lv4_or_b[3]));
assign lv5_or[2] = (~(lv4_or_b[4] & lv4_or_b[5]));
assign lv5_or[3] = (~(lv4_or_b[6] & lv4_or_b[7]));
assign lv5_or[4] = (~(lv4_or_b[8] & lv4_or_b[9]));
assign lv5_or[5] = (~(lv4_or_b[10]));
assign lv5_inv[0] = (~(lv4_or_b[0]));
assign lv5_inv[1] = (~(lv4_or_b[2]));
assign lv5_inv[2] = (~(lv4_or_b[4]));
assign lv5_inv[3] = (~(lv4_or_b[6]));
assign lv5_inv[4] = (~(lv4_or_b[8]));
assign lv5_inv[5] = (~(lv4_or_b[10]));
assign lv5_enc3[0] = (~(lv5_inv[0] | lv4_or_b[1]));
assign lv5_enc3[1] = (~(lv5_inv[1] | lv4_or_b[3]));
assign lv5_enc3[2] = (~(lv5_inv[2] | lv4_or_b[5]));
assign lv5_enc3[3] = (~(lv5_inv[3] | lv4_or_b[7]));
assign lv5_enc3[4] = (~(lv5_inv[4] | lv4_or_b[9]));
assign lv5_enc3[5] = tidn; //dflt0
assign lv5_enc4[0] = (~(lv4_enc4_b[0] & (lv4_enc4_b[1] | lv5_inv[0])));
assign lv5_enc4[1] = (~(lv4_enc4_b[2] & (lv4_enc4_b[3] | lv5_inv[1])));
assign lv5_enc4[2] = (~(lv4_enc4_b[4] & (lv4_enc4_b[5] | lv5_inv[2])));
assign lv5_enc4[3] = (~(lv4_enc4_b[6] & (lv4_enc4_b[7] | lv5_inv[3])));
assign lv5_enc4[4] = (~(lv4_enc4_b[8] & (lv4_enc4_b[9] | lv5_inv[4])));
assign lv5_enc4[5] = (~(lv4_enc4_b[10])); //dflt0 pass
assign lv5_enc5[0] = (~(lv4_enc5_b[0] & (lv4_enc5_b[1] | lv5_inv[0])));
assign lv5_enc5[1] = (~(lv4_enc5_b[2] & (lv4_enc5_b[3] | lv5_inv[1])));
assign lv5_enc5[2] = (~(lv4_enc5_b[4] & (lv4_enc5_b[5] | lv5_inv[2])));
assign lv5_enc5[3] = (~(lv4_enc5_b[6] & (lv4_enc5_b[7] | lv5_inv[3])));
assign lv5_enc5[4] = (~(lv4_enc5_b[8] & (lv4_enc5_b[9] | lv5_inv[4])));
assign lv5_enc5[5] = (~(lv4_enc5_b[10])); //dflt0 pass
assign lv5_enc6[0] = (~(lv4_enc6_b[0] & (lv4_enc6_b[1] | lv5_inv[0])));
assign lv5_enc6[1] = (~(lv4_enc6_b[2] & (lv4_enc6_b[3] | lv5_inv[1])));
assign lv5_enc6[2] = (~(lv4_enc6_b[4] & (lv4_enc6_b[5] | lv5_inv[2])));
assign lv5_enc6[3] = (~(lv4_enc6_b[6] & (lv4_enc6_b[7] | lv5_inv[3])));
assign lv5_enc6[4] = (~(lv4_enc6_b[8] & (lv4_enc6_b[9] | lv5_inv[4])));
assign lv5_enc6[5] = (~(lv4_enc6_b[10] & lv5_inv[5])); //dflt1
assign lv5_enc7[0] = (~(lv4_enc7_b[0] & (lv4_enc7_b[1] | lv5_inv[0])));
assign lv5_enc7[1] = (~(lv4_enc7_b[2] & (lv4_enc7_b[3] | lv5_inv[1])));
assign lv5_enc7[2] = (~(lv4_enc7_b[4] & (lv4_enc7_b[5] | lv5_inv[2])));
assign lv5_enc7[3] = (~(lv4_enc7_b[6] & (lv4_enc7_b[7] | lv5_inv[3])));
assign lv5_enc7[4] = (~(lv4_enc7_b[8] & (lv4_enc7_b[9] | lv5_inv[4])));
assign lv5_enc7[5] = (~(lv4_enc7_b[10] & lv5_inv[5])); //dflt1
//--------------------------------------------------------------------------------
// 064 bit group (phase_in=P, phase_out=N, level_in=lv5, level_out=lv6)
//--------------------------------------------------------------------------------
assign lv6_or_0 = (~lv6_or_b[0]);
assign lv6_or_1 = (~lv6_or_b[1]);
assign lv6_or_b[0] = (~(lv5_or[0] | lv5_or[1]));
assign lv6_or_b[1] = (~(lv5_or[2] | lv5_or[3]));
assign lv6_or_b[2] = (~(lv5_or[4] | lv5_or[5]));
assign lv6_inv_b[0] = (~(lv5_or[0]));
assign lv6_inv_b[1] = (~(lv5_or[2]));
assign lv6_inv_b[2] = (~(lv5_or[4]));
assign lv6_enc2_b[0] = (~(lv6_inv_b[0] & lv5_or[1]));
assign lv6_enc2_b[1] = (~(lv6_inv_b[1] & lv5_or[3]));
assign lv6_enc2_b[2] = (~(lv6_inv_b[2])); //dflt1
assign lv6_enc3_b[0] = (~(lv5_enc3[0] | (lv5_enc3[1] & lv6_inv_b[0])));
assign lv6_enc3_b[1] = (~(lv5_enc3[2] | (lv5_enc3[3] & lv6_inv_b[1])));
assign lv6_enc3_b[2] = (~(lv5_enc3[4] | (lv5_enc3[5] & lv6_inv_b[2])));
assign lv6_enc4_b[0] = (~(lv5_enc4[0] | (lv5_enc4[1] & lv6_inv_b[0])));
assign lv6_enc4_b[1] = (~(lv5_enc4[2] | (lv5_enc4[3] & lv6_inv_b[1])));
assign lv6_enc4_b[2] = (~(lv5_enc4[4] | (lv5_enc4[5] & lv6_inv_b[2])));
assign lv6_enc5_b[0] = (~(lv5_enc5[0] | (lv5_enc5[1] & lv6_inv_b[0])));
assign lv6_enc5_b[1] = (~(lv5_enc5[2] | (lv5_enc5[3] & lv6_inv_b[1])));
assign lv6_enc5_b[2] = (~(lv5_enc5[4] | (lv5_enc5[5] & lv6_inv_b[2])));
assign lv6_enc6_b[0] = (~(lv5_enc6[0] | (lv5_enc6[1] & lv6_inv_b[0])));
assign lv6_enc6_b[1] = (~(lv5_enc6[2] | (lv5_enc6[3] & lv6_inv_b[1])));
assign lv6_enc6_b[2] = (~(lv5_enc6[4] | (lv5_enc6[5] & lv6_inv_b[2])));
assign lv6_enc7_b[0] = (~(lv5_enc7[0] | (lv5_enc7[1] & lv6_inv_b[0])));
assign lv6_enc7_b[1] = (~(lv5_enc7[2] | (lv5_enc7[3] & lv6_inv_b[1])));
assign lv6_enc7_b[2] = (~(lv5_enc7[4] | (lv5_enc7[5] & lv6_inv_b[2])));
//--------------------------------------------------------------------------------
// 128 bit group (phase_in=N, phase_out=P, level_in=lv6, level_out=lv7)
//--------------------------------------------------------------------------------
assign lv7_or[0] = (~(lv6_or_b[0] & lv6_or_b[1]));
assign lv7_or[1] = (~(lv6_or_b[2]));
assign lv7_inv[0] = (~(lv6_or_b[0]));
assign lv7_inv[1] = (~(lv6_or_b[2]));
assign lv7_enc1[0] = (~(lv7_inv[0] | lv6_or_b[1]));
assign lv7_enc1[1] = tidn; //dflt0
assign lv7_enc2[0] = (~(lv6_enc2_b[0] & (lv6_enc2_b[1] | lv7_inv[0])));
assign lv7_enc2[1] = (~(lv6_enc2_b[2] & lv7_inv[1])); //dflt1
assign lv7_enc3[0] = (~(lv6_enc3_b[0] & (lv6_enc3_b[1] | lv7_inv[0])));
assign lv7_enc3[1] = (~(lv6_enc3_b[2])); //dflt0 pass
assign lv7_enc4[0] = (~(lv6_enc4_b[0] & (lv6_enc4_b[1] | lv7_inv[0])));
assign lv7_enc4[1] = (~(lv6_enc4_b[2])); //dflt0 pass
assign lv7_enc5[0] = (~(lv6_enc5_b[0] & (lv6_enc5_b[1] | lv7_inv[0])));
assign lv7_enc5[1] = (~(lv6_enc5_b[2])); //dflt0 pass
assign lv7_enc6[0] = (~(lv6_enc6_b[0] & (lv6_enc6_b[1] | lv7_inv[0])));
assign lv7_enc6[1] = (~(lv6_enc6_b[2] & lv7_inv[1])); //dflt1
assign lv7_enc7[0] = (~(lv6_enc7_b[0] & (lv6_enc7_b[1] | lv7_inv[0])));
assign lv7_enc7[1] = (~(lv6_enc7_b[2] & lv7_inv[1])); //dflt1
//--------------------------------------------------------------------------------
// 256 bit group (phase_in=P, phase_out=N, level_in=lv7, level_out=lv8)
//--------------------------------------------------------------------------------
assign lv8_or_b[0] = (~(lv7_or[0] | lv7_or[1]));
assign lv8_inv_b[0] = (~(lv7_or[0]));
assign lv8_enc0_b[0] = (~(lv8_inv_b[0])); //dflt1
assign lv8_enc1_b[0] = (~(lv7_enc1[0] | (lv7_enc1[1] & lv8_inv_b[0])));
assign lv8_enc2_b[0] = (~(lv7_enc2[0] | (lv7_enc2[1] & lv8_inv_b[0])));
assign lv8_enc3_b[0] = (~(lv7_enc3[0] | (lv7_enc3[1] & lv8_inv_b[0])));
assign lv8_enc4_b[0] = (~(lv7_enc4[0] | (lv7_enc4[1] & lv8_inv_b[0])));
assign lv8_enc5_b[0] = (~(lv7_enc5[0] | (lv7_enc5[1] & lv8_inv_b[0])));
assign lv8_enc6_b[0] = (~(lv7_enc6[0] | (lv7_enc6[1] & lv8_inv_b[0])));
assign lv8_enc7_b[0] = (~(lv7_enc7[0] | (lv7_enc7[1] & lv8_inv_b[0])));
assign lza_any_b = (lv8_or_b[0]); //repower,long wire
assign lza_amt_b[0] = (lv8_enc0_b[0]); //repower,long wire
assign lza_amt_b[1] = (lv8_enc1_b[0]); //repower,long wire
assign lza_amt_b[2] = (lv8_enc2_b[0]); //repower,long wire
assign lza_amt_b[3] = (lv8_enc3_b[0]); //repower,long wire
assign lza_amt_b[4] = (lv8_enc4_b[0]); //repower,long wire
assign lza_amt_b[5] = (lv8_enc5_b[0]); //repower,long wire
assign lza_amt_b[6] = (lv8_enc6_b[0]); //repower,long wire
assign lza_amt_b[7] = (lv8_enc7_b[0]); //repower,long wire
endmodule |
module fu_divsqrt_add4(
x,
y,
s
);
`include "tri_a2o.vh"
input [0:3] x;
input [0:3] y;
output [0:3] s;
wire [0:3] h;
wire [1:3] g_b;
wire [1:2] t_b;
wire g2_3t3;
wire g2_2t3;
wire g2_1t2;
wire t2_1t2;
wire g4_1t3_b;
wire g8_1t3;
//VHDL is below in comments to preserve the labels
//sum4_l1xor: h(0 to 3) <= ( x(0 to 3) xor y(0 to 3) ) ;--Lvl 1/2 P
//sum4_l1nor: t_b(1 to 2) <= not( x(1 to 2) or y(1 to 2) ) ;--Lvl 1 P or G ... -KILL
//sum4_l1nand: g_b(1 to 3) <= not( x(1 to 3) and y(1 to 3) ) ;--Lvl 1 G
//sum4_l2not: g2_3t3 <= not( g_b(3) );--kogge-stone carry tree
//sum4_l2oai1: g2_2t3 <= not(g_b(2) and (t_b(2) or g_b(3)) );
//sum4_l2oai2: g2_1t2 <= not(g_b(1) and (t_b(1) or g_b(2)) );
//sum4_l2nor: t2_1t2 <= not( (t_b(1) or t_b(2)) );
//sum4_l3aoi: g4_1t3_b <= not(g2_1t2 or (t2_1t2 and g2_3t3) );
//sum4_l4not3: g8_1t3 <= not( g4_1t3_b );
//sum4_l5xor0: s(0) <= ( g8_1t3 xor h(0) );--output
//sum4_l5xor1: s(1) <= ( g2_2t3 xor h(1) );--output
//sum4_l5xor2: s(2) <= ( g2_3t3 xor h(2) );--output
// s(3) <= ( h(3) );--output
// EXAMPLE
// tri_xor2 #(.WIDTH(1), .BTR("XOR2_X2M_A9TH")) DIVSQRT_XOR2_0(s[0], g8_1t3, h[0]);
////////////////////////////////////////////////////////////////////////////////////////////////
//assign h[0:3] = (x[0:3] ^ y[0:3]); //Lvl 1/2 P
tri_xor2 #(.WIDTH(4), .BTR("XOR2_X4M_A9TH")) DIVSQRT_XOR2_00(h[0:3], x[0:3], y[0:3]);
//assign t_b[1:2] = (~(x[1:2] | y[1:2])); //Lvl 1 P or G ... -KILL
tri_nor2 #(.WIDTH(1), .BTR("NOR2_X4M_A9TH")) DIVSQRT_NOR2_t_b_1(t_b[1], x[1], y[1]);
tri_nor2 #(.WIDTH(1), .BTR("NOR2_X2M_A9TH")) DIVSQRT_NOR2_t_b_2(t_b[2], x[2], y[2]);
//assign g_b[1:3] = (~(x[1:3] & y[1:3])); //Lvl 1 G
tri_nand2 #(.WIDTH(1), .BTR("NAND2_X1M_A9TH")) DIVSQRT_NAND2_g_b_1(g_b[1], x[1], y[1]);
tri_nand2 #(.WIDTH(1), .BTR("NAND2_X2M_A9TH")) DIVSQRT_NAND2_g_b_2(g_b[2], x[2], y[2]);
tri_nand2 #(.WIDTH(1), .BTR("NAND2_X4M_A9TH")) DIVSQRT_NAND2_g_b_3(g_b[3], x[3], y[3]);
//assign g2_3t3 = (~(g_b[3])); //kogge-stone carry tree
tri_inv #(.WIDTH(1), .BTR("INV_X6M_A9TH")) DIVSQRT_INV_g2_3t3(g2_3t3, g_b[3]);
//assign g2_2t3 = (~(g_b[2] & (t_b[2] | g_b[3])));
tri_oai21 #(.WIDTH(1), .BTR("OAI21_X3M_A9TH")) DIVSQRT_OAI21_g2_2t3(g2_2t3, t_b[2], g_b[3], g_b[2]);
//assign g2_1t2 = (~(g_b[1] & (t_b[1] | g_b[2])));
tri_oai21 #(.WIDTH(1), .BTR("OAI21_X4M_A9TH")) DIVSQRT_OAI21_g2_1t2(g2_1t2, t_b[1], g_b[2], g_b[1]);
//assign t2_1t2 = (~((t_b[1] | t_b[2])));
tri_nor2 #(.WIDTH(1), .BTR("NOR2_X2M_A9TH")) DIVSQRT_NOR2_t2_1t2(t2_1t2, t_b[1], t_b[2]);
//assign g4_1t3_b = (~(g2_1t2 | (t2_1t2 & g2_3t3)));
tri_aoi21 #(.WIDTH(1), .BTR("AOI21_X4M_A9TH")) DIVSQRT_AOI21_g4_1t3_b(g4_1t3_b, t2_1t2, g2_3t3, g2_1t2);
//assign g8_1t3 = (~(g4_1t3_b));
tri_inv #(.WIDTH(1), .BTR("INV_X6M_A9TH")) DIVSQRT_INV_g8_1t3(g8_1t3, g4_1t3_b);
//assign s[0] = (g8_1t3 ^ h[0]); //output
tri_xor2 #(.WIDTH(1), .BTR("XOR2_X4M_A9TH")) DIVSQRT_XOR2_10(s[0], g8_1t3, h[0]);
//assign s[1] = (g2_2t3 ^ h[1]); //output
tri_xor2 #(.WIDTH(1), .BTR("XOR2_X4M_A9TH")) DIVSQRT_XOR2_11(s[1], g2_2t3, h[1]);
//assign s[2] = (g2_3t3 ^ h[2]); //output
tri_xor2 #(.WIDTH(1), .BTR("XOR2_X4M_A9TH")) DIVSQRT_XOR2_12(s[2], g2_3t3, h[2]);
assign s[3] = (h[3]); //output
endmodule |
module mmq_perv(
inout vdd,
inout gnd,
(* pin_data ="PIN_FUNCTION=/G_CLK/" *)
input [0:`NCLK_WIDTH-1] nclk,
input [0:1] pc_mm_sg_3,
input [0:1] pc_mm_func_sl_thold_3,
input [0:1] pc_mm_func_slp_sl_thold_3,
input pc_mm_gptr_sl_thold_3,
input pc_mm_fce_3,
input pc_mm_time_sl_thold_3,
input pc_mm_repr_sl_thold_3,
input pc_mm_abst_sl_thold_3,
input pc_mm_abst_slp_sl_thold_3,
input pc_mm_cfg_sl_thold_3,
input pc_mm_cfg_slp_sl_thold_3,
input pc_mm_func_nsl_thold_3,
input pc_mm_func_slp_nsl_thold_3,
input pc_mm_ary_nsl_thold_3,
input pc_mm_ary_slp_nsl_thold_3,
input tc_ac_ccflush_dc,
input tc_scan_diag_dc,
input tc_ac_scan_dis_dc_b,
output [0:1] pc_sg_0,
output [0:1] pc_sg_1,
output [0:1] pc_sg_2,
output [0:1] pc_func_sl_thold_2,
output [0:1] pc_func_slp_sl_thold_2,
output pc_func_slp_nsl_thold_2,
output pc_cfg_sl_thold_2,
output pc_cfg_slp_sl_thold_2,
output pc_fce_2,
output pc_time_sl_thold_0,
output pc_repr_sl_thold_0,
output pc_abst_sl_thold_0,
output pc_abst_slp_sl_thold_0,
output pc_ary_nsl_thold_0,
output pc_ary_slp_nsl_thold_0,
output [0:1] pc_func_sl_thold_0,
output [0:1] pc_func_sl_thold_0_b,
output [0:1] pc_func_slp_sl_thold_0,
output [0:1] pc_func_slp_sl_thold_0_b,
output lcb_clkoff_dc_b,
output lcb_act_dis_dc,
output lcb_d_mode_dc,
output [0:4] lcb_delay_lclkr_dc,
output [0:4] lcb_mpw1_dc_b,
output lcb_mpw2_dc_b,
output g6t_gptr_lcb_clkoff_dc_b,
output g6t_gptr_lcb_act_dis_dc,
output g6t_gptr_lcb_d_mode_dc,
output [0:4] g6t_gptr_lcb_delay_lclkr_dc,
output [0:4] g6t_gptr_lcb_mpw1_dc_b,
output g6t_gptr_lcb_mpw2_dc_b,
output g8t_gptr_lcb_clkoff_dc_b,
output g8t_gptr_lcb_act_dis_dc,
output g8t_gptr_lcb_d_mode_dc,
output [0:4] g8t_gptr_lcb_delay_lclkr_dc,
output [0:4] g8t_gptr_lcb_mpw1_dc_b,
output g8t_gptr_lcb_mpw2_dc_b,
// abist engine controls for arrays from pervasive
input [0:3] pc_mm_abist_dcomp_g6t_2r,
input [0:3] pc_mm_abist_di_0,
input [0:3] pc_mm_abist_di_g6t_2r,
input pc_mm_abist_ena_dc,
input pc_mm_abist_g6t_r_wb,
input pc_mm_abist_g8t1p_renb_0,
input pc_mm_abist_g8t_bw_0,
input pc_mm_abist_g8t_bw_1,
input [0:3] pc_mm_abist_g8t_dcomp,
input pc_mm_abist_g8t_wenb,
input [0:9] pc_mm_abist_raddr_0,
input [0:9] pc_mm_abist_waddr_0,
input pc_mm_abist_wl128_comp_ena,
output pc_mm_abist_g8t_wenb_q,
output pc_mm_abist_g8t1p_renb_0_q,
output [0:3] pc_mm_abist_di_0_q,
output pc_mm_abist_g8t_bw_1_q,
output pc_mm_abist_g8t_bw_0_q,
output [0:9] pc_mm_abist_waddr_0_q,
output [0:9] pc_mm_abist_raddr_0_q,
output pc_mm_abist_wl128_comp_ena_q,
output [0:3] pc_mm_abist_g8t_dcomp_q,
output [0:3] pc_mm_abist_dcomp_g6t_2r_q,
output [0:3] pc_mm_abist_di_g6t_2r_q,
output pc_mm_abist_g6t_r_wb_q,
// BOLT-ON pervasive stuff for asic
input pc_mm_bolt_sl_thold_3,
input pc_mm_bo_enable_3, // general bolt-on enable
output pc_mm_bolt_sl_thold_0,
output pc_mm_bo_enable_2,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input gptr_scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output gptr_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input time_scan_in,
output time_scan_in_int,
input time_scan_out_int,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output time_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input [0:9] func_scan_in,
output [0:9] func_scan_in_int,
input [0:9] func_scan_out_int,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output [0:9] func_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input repr_scan_in,
output repr_scan_in_int,
input repr_scan_out_int,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output repr_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input [0:1] abst_scan_in,
output [0:1] abst_scan_in_int,
input [0:1] abst_scan_out_int,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output [0:1] abst_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input bcfg_scan_in, // config latches that are setup same on all cores
output bcfg_scan_in_int,
input bcfg_scan_out_int,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output bcfg_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input ccfg_scan_in, // config latches that could be setup differently on multiple cores
output ccfg_scan_in_int,
input ccfg_scan_out_int,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output ccfg_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input dcfg_scan_in,
output dcfg_scan_in_int,
input dcfg_scan_out_int,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output dcfg_scan_out
);
wire tidn;
wire tiup;
wire [0:1] pc_func_sl_thold_2_int;
wire [0:1] pc_func_slp_sl_thold_2_int;
wire [0:1] pc_sg_2_int;
wire pc_gptr_sl_thold_2_int;
wire pc_fce_2_int;
wire pc_time_sl_thold_2_int;
wire pc_repr_sl_thold_2_int;
wire pc_abst_sl_thold_2_int;
wire pc_abst_slp_sl_thold_2_int;
wire pc_cfg_sl_thold_2_int;
wire pc_cfg_slp_sl_thold_2_int;
wire pc_func_nsl_thold_2_int;
wire pc_func_slp_nsl_thold_2_int;
wire pc_ary_nsl_thold_2_int;
wire pc_ary_slp_nsl_thold_2_int;
wire pc_mm_bolt_sl_thold_2_int;
wire [0:1] pc_func_sl_thold_1_int;
wire [0:1] pc_func_slp_sl_thold_1_int;
wire [0:1] pc_sg_1_int;
wire pc_gptr_sl_thold_1_int;
wire pc_fce_1_int;
wire pc_time_sl_thold_1_int;
wire pc_repr_sl_thold_1_int;
wire pc_abst_sl_thold_1_int;
wire pc_abst_slp_sl_thold_1_int;
wire pc_cfg_sl_thold_1_int;
wire pc_cfg_slp_sl_thold_1_int;
wire pc_func_nsl_thold_1_int;
wire pc_func_slp_nsl_thold_1_int;
wire pc_ary_nsl_thold_1_int;
wire pc_ary_slp_nsl_thold_1_int;
wire pc_mm_bolt_sl_thold_1_int;
wire [0:1] pc_func_sl_thold_0_int;
wire [0:1] pc_func_slp_sl_thold_0_int;
wire [0:1] pc_sg_0_int;
wire pc_gptr_sl_thold_0_int;
wire pc_fce_0_int;
wire pc_time_sl_thold_0_int;
wire pc_repr_sl_thold_0_int;
wire pc_abst_sl_thold_0_int;
wire pc_abst_slp_sl_thold_0_int;
wire pc_cfg_sl_thold_0_int;
wire pc_cfg_slp_sl_thold_0_int;
wire pc_func_nsl_thold_0_int;
wire pc_func_slp_nsl_thold_0_int;
wire pc_ary_nsl_thold_0_int;
wire pc_ary_slp_nsl_thold_0_int;
wire [0:1] pc_func_sl_thold_0_b_int;
wire [0:1] pc_func_slp_sl_thold_0_b_int;
wire [0:1] pc_func_slp_sl_force_int;
wire [0:1] pc_func_sl_force_int;
wire [0:1] abst_scan_in_q;
wire [0:1] abst_scan_out_q;
wire time_scan_in_q;
wire time_scan_out_q;
wire repr_scan_in_q;
wire repr_scan_out_q;
wire gptr_scan_in_q;
wire gptr_scan_out_int;
wire gptr_scan_out_q;
wire [0:1] gptr_scan_lcbctrl;
wire bcfg_scan_in_q;
wire bcfg_scan_out_q;
wire ccfg_scan_in_q;
wire ccfg_scan_out_q;
wire dcfg_scan_in_q;
wire dcfg_scan_out_q;
wire [0:9] func_scan_in_q;
wire [0:9] func_scan_out_q;
wire [0:1] slat_force;
wire abst_slat_thold_b;
wire abst_slat_d2clk;
wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
wire time_slat_thold_b;
wire time_slat_d2clk;
wire [0:`NCLK_WIDTH-1] time_slat_lclk;
wire repr_slat_thold_b;
wire repr_slat_d2clk;
wire [0:`NCLK_WIDTH-1] repr_slat_lclk;
wire gptr_slat_thold_b;
wire gptr_slat_d2clk;
wire [0:`NCLK_WIDTH-1] gptr_slat_lclk;
wire bcfg_slat_thold_b;
wire bcfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] bcfg_slat_lclk;
wire ccfg_slat_thold_b;
wire ccfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] ccfg_slat_lclk;
wire dcfg_slat_thold_b;
wire dcfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] dcfg_slat_lclk;
wire func_slat_thold_b;
wire func_slat_d2clk;
wire [0:`NCLK_WIDTH-1] func_slat_lclk;
wire pc_abst_sl_thold_0_b;
wire pc_abst_sl_force;
wire [0:4] lcb_delay_lclkr_dc_int;
wire lcb_d_mode_dc_int;
wire [0:4] lcb_mpw1_dc_b_int;
wire lcb_mpw2_dc_b_int;
wire lcb_clkoff_dc_b_int;
wire [0:41] abist_siv;
wire [0:41] abist_sov;
(* analysis_not_referenced="true" *)
wire [0:8] unused_dc;
(* analysis_not_referenced="true" *)
wire [0:3] perv_abst_stg_q, perv_abst_stg_q_b;
(* analysis_not_referenced="true" *)
wire [0:1] perv_time_stg_q, perv_time_stg_q_b, perv_repr_stg_q, perv_repr_stg_q_b,
perv_gptr_stg_q, perv_gptr_stg_q_b, perv_bcfg_stg_q, perv_bcfg_stg_q_b,
perv_ccfg_stg_q, perv_ccfg_stg_q_b, perv_dcfg_stg_q, perv_dcfg_stg_q_b;
(* analysis_not_referenced="true" *)
wire [0:19] perv_func_stg_q, perv_func_stg_q_b;
assign tidn = 1'b0;
assign tiup = 1'b1;
tri_plat #(.WIDTH(20)) perv_3to2_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din( {pc_mm_sg_3[0:1],
pc_mm_func_slp_sl_thold_3[0:1],
pc_mm_func_sl_thold_3[0:1],
pc_mm_gptr_sl_thold_3,
pc_mm_fce_3,
pc_mm_time_sl_thold_3,
pc_mm_repr_sl_thold_3,
pc_mm_abst_sl_thold_3,
pc_mm_abst_slp_sl_thold_3,
pc_mm_cfg_sl_thold_3,
pc_mm_cfg_slp_sl_thold_3,
pc_mm_func_nsl_thold_3,
pc_mm_func_slp_nsl_thold_3,
pc_mm_ary_nsl_thold_3,
pc_mm_ary_slp_nsl_thold_3,
pc_mm_bolt_sl_thold_3,
pc_mm_bo_enable_3} ),
.q( {pc_sg_2_int[0:1],
pc_func_slp_sl_thold_2_int[0:1],
pc_func_sl_thold_2_int[0:1],
pc_gptr_sl_thold_2_int,
pc_fce_2_int,
pc_time_sl_thold_2_int,
pc_repr_sl_thold_2_int,
pc_abst_sl_thold_2_int,
pc_abst_slp_sl_thold_2_int,
pc_cfg_sl_thold_2_int,
pc_cfg_slp_sl_thold_2_int,
pc_func_nsl_thold_2_int,
pc_func_slp_nsl_thold_2_int,
pc_ary_nsl_thold_2_int,
pc_ary_slp_nsl_thold_2_int,
pc_mm_bolt_sl_thold_2_int,
pc_mm_bo_enable_2} )
);
tri_plat #(.WIDTH(19)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din( {pc_sg_2_int[0:1],
pc_func_slp_sl_thold_2_int[0:1],
pc_func_sl_thold_2_int[0:1],
pc_gptr_sl_thold_2_int,
pc_fce_2_int,
pc_time_sl_thold_2_int,
pc_repr_sl_thold_2_int,
pc_abst_sl_thold_2_int,
pc_abst_slp_sl_thold_2_int,
pc_cfg_sl_thold_2_int,
pc_cfg_slp_sl_thold_2_int,
pc_func_nsl_thold_2_int,
pc_func_slp_nsl_thold_2_int,
pc_ary_nsl_thold_2_int,
pc_ary_slp_nsl_thold_2_int,
pc_mm_bolt_sl_thold_2_int} ),
.q( {pc_sg_1_int[0:1],
pc_func_slp_sl_thold_1_int[0:1],
pc_func_sl_thold_1_int[0:1],
pc_gptr_sl_thold_1_int,
pc_fce_1_int,
pc_time_sl_thold_1_int,
pc_repr_sl_thold_1_int,
pc_abst_sl_thold_1_int,
pc_abst_slp_sl_thold_1_int,
pc_cfg_sl_thold_1_int,
pc_cfg_slp_sl_thold_1_int,
pc_func_nsl_thold_1_int,
pc_func_slp_nsl_thold_1_int,
pc_ary_nsl_thold_1_int,
pc_ary_slp_nsl_thold_1_int,
pc_mm_bolt_sl_thold_1_int} )
);
tri_plat #(.WIDTH(19)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din( {pc_sg_1_int[0:1],
pc_func_slp_sl_thold_1_int[0:1],
pc_func_sl_thold_1_int[0:1],
pc_gptr_sl_thold_1_int,
pc_fce_1_int,
pc_time_sl_thold_1_int,
pc_repr_sl_thold_1_int,
pc_abst_sl_thold_1_int,
pc_abst_slp_sl_thold_1_int,
pc_cfg_sl_thold_1_int,
pc_cfg_slp_sl_thold_1_int,
pc_func_nsl_thold_1_int,
pc_func_slp_nsl_thold_1_int,
pc_ary_nsl_thold_1_int,
pc_ary_slp_nsl_thold_1_int,
pc_mm_bolt_sl_thold_1_int} ),
.q( {pc_sg_0_int[0:1],
pc_func_slp_sl_thold_0_int[0:1],
pc_func_sl_thold_0_int[0:1],
pc_gptr_sl_thold_0_int,
pc_fce_0_int,
pc_time_sl_thold_0_int,
pc_repr_sl_thold_0_int,
pc_abst_sl_thold_0_int,
pc_abst_slp_sl_thold_0_int,
pc_cfg_sl_thold_0_int,
pc_cfg_slp_sl_thold_0_int,
pc_func_nsl_thold_0_int,
pc_func_slp_nsl_thold_0_int,
pc_ary_nsl_thold_0_int,
pc_ary_slp_nsl_thold_0_int,
pc_mm_bolt_sl_thold_0} )
);
assign pc_time_sl_thold_0 = pc_time_sl_thold_0_int;
assign pc_abst_sl_thold_0 = pc_abst_sl_thold_0_int;
assign pc_abst_slp_sl_thold_0 = pc_abst_slp_sl_thold_0_int;
assign pc_repr_sl_thold_0 = pc_repr_sl_thold_0_int;
assign pc_ary_nsl_thold_0 = pc_ary_nsl_thold_0_int;
assign pc_ary_slp_nsl_thold_0 = pc_ary_slp_nsl_thold_0_int;
assign pc_func_sl_thold_0 = pc_func_sl_thold_0_int;
assign pc_func_sl_thold_0_b = pc_func_sl_thold_0_b_int;
assign pc_func_slp_sl_thold_0 = pc_func_slp_sl_thold_0_int;
assign pc_func_slp_sl_thold_0_b = pc_func_slp_sl_thold_0_b_int;
assign pc_sg_0 = pc_sg_0_int;
assign pc_sg_1 = pc_sg_1_int;
assign pc_sg_2 = pc_sg_2_int;
assign pc_func_sl_thold_2 = pc_func_sl_thold_2_int;
assign pc_func_slp_sl_thold_2 = pc_func_slp_sl_thold_2_int;
assign pc_func_slp_nsl_thold_2 = pc_func_slp_nsl_thold_2_int;
assign pc_cfg_sl_thold_2 = pc_cfg_sl_thold_2_int;
assign pc_cfg_slp_sl_thold_2 = pc_cfg_slp_sl_thold_2_int;
assign pc_fce_2 = pc_fce_2_int;
assign lcb_clkoff_dc_b = lcb_clkoff_dc_b_int;
assign lcb_d_mode_dc = lcb_d_mode_dc_int;
assign lcb_delay_lclkr_dc = lcb_delay_lclkr_dc_int;
assign lcb_mpw1_dc_b = lcb_mpw1_dc_b_int;
assign lcb_mpw2_dc_b = lcb_mpw2_dc_b_int;
tri_lcbcntl_mac perv_lcbctrl(
.vdd(vdd),
.gnd(gnd),
.sg(pc_sg_0_int[0]),
.nclk(nclk),
.scan_in(gptr_scan_in_q),
.scan_diag_dc(tc_scan_diag_dc),
.thold(pc_gptr_sl_thold_0_int),
.clkoff_dc_b(lcb_clkoff_dc_b_int),
.delay_lclkr_dc(lcb_delay_lclkr_dc_int[0:4]),
.act_dis_dc(unused_dc[6]),
.d_mode_dc(lcb_d_mode_dc_int),
.mpw1_dc_b(lcb_mpw1_dc_b_int[0:4]),
.mpw2_dc_b(lcb_mpw2_dc_b_int),
.scan_out(gptr_scan_lcbctrl[0])
);
tri_lcbcntl_array_mac perv_g6t_gptr_lcbctrl(
.vdd(vdd),
.gnd(gnd),
.sg(pc_sg_0_int[1]),
.nclk(nclk),
.scan_in(gptr_scan_lcbctrl[0]),
.scan_diag_dc(tc_scan_diag_dc),
.thold(pc_gptr_sl_thold_0_int),
.clkoff_dc_b(g6t_gptr_lcb_clkoff_dc_b),
.delay_lclkr_dc(g6t_gptr_lcb_delay_lclkr_dc[0:4]),
.act_dis_dc(unused_dc[7]),
.d_mode_dc(g6t_gptr_lcb_d_mode_dc),
.mpw1_dc_b(g6t_gptr_lcb_mpw1_dc_b[0:4]),
.mpw2_dc_b(g6t_gptr_lcb_mpw2_dc_b),
.scan_out(gptr_scan_lcbctrl[1])
);
tri_lcbcntl_array_mac perv_g8t_gptr_lcbctrl(
.vdd(vdd),
.gnd(gnd),
.sg(pc_sg_0_int[1]),
.nclk(nclk),
.scan_in(gptr_scan_lcbctrl[1]),
.scan_diag_dc(tc_scan_diag_dc),
.thold(pc_gptr_sl_thold_0_int),
.clkoff_dc_b(g8t_gptr_lcb_clkoff_dc_b),
.delay_lclkr_dc(g8t_gptr_lcb_delay_lclkr_dc[0:4]),
.act_dis_dc(unused_dc[8]),
.d_mode_dc(g8t_gptr_lcb_d_mode_dc),
.mpw1_dc_b(g8t_gptr_lcb_mpw1_dc_b[0:4]),
.mpw2_dc_b(g8t_gptr_lcb_mpw2_dc_b),
.scan_out(gptr_scan_out_int)
);
//never disable act pins, they are used functionally
assign lcb_act_dis_dc = 1'b0;
assign g8t_gptr_lcb_act_dis_dc = 1'b0;
assign g6t_gptr_lcb_act_dis_dc = 1'b0;
assign time_scan_in_int = time_scan_in_q;
assign repr_scan_in_int = repr_scan_in_q;
assign func_scan_in_int = func_scan_in_q;
assign bcfg_scan_in_int = bcfg_scan_in_q;
assign ccfg_scan_in_int = ccfg_scan_in_q;
assign dcfg_scan_in_int = dcfg_scan_in_q;
assign time_scan_out = time_scan_out_q & tc_ac_scan_dis_dc_b;
assign gptr_scan_out = gptr_scan_out_q & tc_ac_scan_dis_dc_b;
assign repr_scan_out = repr_scan_out_q & tc_ac_scan_dis_dc_b;
assign func_scan_out = func_scan_out_q & {10{tc_ac_scan_dis_dc_b}};
assign abst_scan_out = abst_scan_out_q & {2{tc_ac_scan_dis_dc_b}};
assign bcfg_scan_out = bcfg_scan_out_q & tc_ac_scan_dis_dc_b;
assign ccfg_scan_out = ccfg_scan_out_q & tc_ac_scan_dis_dc_b;
assign dcfg_scan_out = dcfg_scan_out_q & tc_ac_scan_dis_dc_b;
// LCBs for scan only staging latches
assign slat_force = pc_sg_0_int;
assign abst_slat_thold_b = (~pc_abst_sl_thold_0_int);
assign time_slat_thold_b = (~pc_time_sl_thold_0_int);
assign repr_slat_thold_b = (~pc_repr_sl_thold_0_int);
assign gptr_slat_thold_b = (~pc_gptr_sl_thold_0_int);
assign bcfg_slat_thold_b = (~pc_cfg_sl_thold_0_int);
assign ccfg_slat_thold_b = (~pc_cfg_sl_thold_0_int);
assign dcfg_slat_thold_b = (~pc_cfg_sl_thold_0_int);
assign func_slat_thold_b = (~pc_func_sl_thold_0_int[0]);
tri_lcbs perv_lcbs_abst(
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc_int[0]),
.nclk(nclk),
.force_t(slat_force[1]),
.thold_b(abst_slat_thold_b),
.dclk(abst_slat_d2clk),
.lclk(abst_slat_lclk)
);
tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_abst_stg(
.vd(vdd),
.gd(gnd),
.dclk(abst_slat_d2clk),
.lclk(abst_slat_lclk),
.scan_in( {abst_scan_out_int, abst_scan_in} ),
.scan_out( {abst_scan_out_q, abst_scan_in_q} ),
.q( perv_abst_stg_q),
.q_b( perv_abst_stg_q_b)
);
tri_lcbs perv_lcbs_time(
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc_int[0]),
.nclk(nclk),
.force_t(slat_force[1]),
.thold_b(time_slat_thold_b),
.dclk(time_slat_d2clk),
.lclk(time_slat_lclk)
);
tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_time_stg(
.vd(vdd),
.gd(gnd),
.dclk(time_slat_d2clk),
.lclk(time_slat_lclk),
.scan_in( {time_scan_in, time_scan_out_int} ),
.scan_out( {time_scan_in_q, time_scan_out_q} ),
.q( perv_time_stg_q),
.q_b( perv_time_stg_q_b)
);
tri_lcbs perv_lcbs_repr(
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc_int[0]),
.nclk(nclk),
.force_t(slat_force[1]),
.thold_b(repr_slat_thold_b),
.dclk(repr_slat_d2clk),
.lclk(repr_slat_lclk)
);
tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_repr_stg(
.vd(vdd),
.gd(gnd),
.dclk(repr_slat_d2clk),
.lclk(repr_slat_lclk),
.scan_in( {repr_scan_in, repr_scan_out_int} ),
.scan_out( {repr_scan_in_q, repr_scan_out_q} ),
.q( perv_repr_stg_q),
.q_b( perv_repr_stg_q_b)
);
tri_lcbs perv_lcbs_gptr(
.vd(vdd),
.gd(gnd),
.delay_lclkr(tiup),
.nclk(nclk),
.force_t(slat_force[0]),
.thold_b(gptr_slat_thold_b),
.dclk(gptr_slat_d2clk),
.lclk(gptr_slat_lclk)
);
tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_gptr_stg(
.vd(vdd),
.gd(gnd),
.dclk(gptr_slat_d2clk),
.lclk(gptr_slat_lclk),
.scan_in( {gptr_scan_in, gptr_scan_out_int} ),
.scan_out( {gptr_scan_in_q, gptr_scan_out_q} ),
.q( perv_gptr_stg_q),
.q_b( perv_gptr_stg_q_b)
);
tri_lcbs perv_lcbs_bcfg(
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc_int[0]),
.nclk(nclk),
.force_t(slat_force[0]),
.thold_b(bcfg_slat_thold_b),
.dclk(bcfg_slat_d2clk),
.lclk(bcfg_slat_lclk)
);
tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_bcfg_stg(
.vd(vdd),
.gd(gnd),
.dclk(bcfg_slat_d2clk),
.lclk(bcfg_slat_lclk),
.scan_in( {bcfg_scan_in, bcfg_scan_out_int} ),
.scan_out( {bcfg_scan_in_q, bcfg_scan_out_q} ),
.q( perv_bcfg_stg_q),
.q_b( perv_bcfg_stg_q_b)
);
tri_lcbs perv_lcbs_ccfg(
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc_int[0]),
.nclk(nclk),
.force_t(slat_force[0]),
.thold_b(ccfg_slat_thold_b),
.dclk(ccfg_slat_d2clk),
.lclk(ccfg_slat_lclk)
);
tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_ccfg_stg(
.vd(vdd),
.gd(gnd),
.dclk(ccfg_slat_d2clk),
.lclk(ccfg_slat_lclk),
.scan_in( {ccfg_scan_in, ccfg_scan_out_int} ),
.scan_out( {ccfg_scan_in_q, ccfg_scan_out_q} ),
.q( perv_ccfg_stg_q),
.q_b( perv_ccfg_stg_q_b)
);
tri_lcbs perv_lcbs_dcfg(
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc_int[0]),
.nclk(nclk),
.force_t(slat_force[0]),
.thold_b(dcfg_slat_thold_b),
.dclk(dcfg_slat_d2clk),
.lclk(dcfg_slat_lclk)
);
tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_dcfg_stg(
.vd(vdd),
.gd(gnd),
.dclk(dcfg_slat_d2clk),
.lclk(dcfg_slat_lclk),
.scan_in( {dcfg_scan_in, dcfg_scan_out_int} ),
.scan_out( {dcfg_scan_in_q, dcfg_scan_out_q} ),
.q( perv_dcfg_stg_q),
.q_b( perv_dcfg_stg_q_b)
);
tri_lcbs perv_lcbs_func(
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc_int[0]),
.nclk(nclk),
.force_t(slat_force[0]),
.thold_b(func_slat_thold_b),
.dclk(func_slat_d2clk),
.lclk(func_slat_lclk)
);
tri_slat_scan #(.WIDTH(20), .INIT(20'b00000000000000000000)) perv_func_stg(
.vd(vdd),
.gd(gnd),
.dclk(func_slat_d2clk),
.lclk(func_slat_lclk),
.scan_in( {func_scan_out_int, func_scan_in} ),
.scan_out( {func_scan_out_q, func_scan_in_q} ),
.q( perv_func_stg_q),
.q_b( perv_func_stg_q_b)
);
tri_lcbor perv_lcbor_func_sl_0(
.clkoff_b(lcb_clkoff_dc_b_int),
.thold(pc_func_sl_thold_0_int[0]),
.sg(pc_sg_0_int[0]),
.act_dis(tidn),
.force_t(pc_func_sl_force_int[0]),
.thold_b(pc_func_sl_thold_0_b_int[0])
);
tri_lcbor perv_lcbor_func_sl_1(
.clkoff_b(lcb_clkoff_dc_b_int),
.thold(pc_func_sl_thold_0_int[1]),
.sg(pc_sg_0_int[1]),
.act_dis(tidn),
.force_t(pc_func_sl_force_int[1]),
.thold_b(pc_func_sl_thold_0_b_int[1])
);
tri_lcbor perv_lcbor_func_slp_sl_0(
.clkoff_b(lcb_clkoff_dc_b_int),
.thold(pc_func_slp_sl_thold_0_int[0]),
.sg(pc_sg_0_int[0]),
.act_dis(tidn),
.force_t(pc_func_slp_sl_force_int[0]),
.thold_b(pc_func_slp_sl_thold_0_b_int[0])
);
tri_lcbor perv_lcbor_func_slp_sl_1(
.clkoff_b(lcb_clkoff_dc_b_int),
.thold(pc_func_slp_sl_thold_0_int[1]),
.sg(pc_sg_0_int[1]),
.act_dis(tidn),
.force_t(pc_func_slp_sl_force_int[1]),
.thold_b(pc_func_slp_sl_thold_0_b_int[1])
);
tri_lcbor perv_lcbor_abst_sl(
.clkoff_b(lcb_clkoff_dc_b_int),
.thold(pc_abst_sl_thold_0_int),
.sg(pc_sg_0_int[1]),
.act_dis(tidn),
.force_t(pc_abst_sl_force),
.thold_b(pc_abst_sl_thold_0_b)
);
//---------------------------------------------------------------------
// abist latches
//---------------------------------------------------------------------
tri_rlmreg_p #(.INIT(0), .WIDTH(42), .NEEDS_SRESET(0)) abist_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(pc_mm_abist_ena_dc),
.thold_b(pc_abst_sl_thold_0_b),
.sg(pc_sg_0_int[1]),
.force_t(pc_abst_sl_force),
.delay_lclkr(lcb_delay_lclkr_dc_int[0]),
.mpw1_b(lcb_mpw1_dc_b_int[0]),
.mpw2_b(lcb_mpw2_dc_b_int),
.d_mode(lcb_d_mode_dc_int),
.scin(abist_siv[0:41]),
.scout(abist_sov[0:41]),
.din( {pc_mm_abist_g8t_wenb,
pc_mm_abist_g8t1p_renb_0,
pc_mm_abist_di_0,
pc_mm_abist_g8t_bw_1,
pc_mm_abist_g8t_bw_0,
pc_mm_abist_waddr_0,
pc_mm_abist_raddr_0,
pc_mm_abist_wl128_comp_ena,
pc_mm_abist_g8t_dcomp,
pc_mm_abist_dcomp_g6t_2r,
pc_mm_abist_di_g6t_2r,
pc_mm_abist_g6t_r_wb} ),
.dout( {pc_mm_abist_g8t_wenb_q,
pc_mm_abist_g8t1p_renb_0_q,
pc_mm_abist_di_0_q,
pc_mm_abist_g8t_bw_1_q,
pc_mm_abist_g8t_bw_0_q,
pc_mm_abist_waddr_0_q,
pc_mm_abist_raddr_0_q,
pc_mm_abist_wl128_comp_ena_q,
pc_mm_abist_g8t_dcomp_q,
pc_mm_abist_dcomp_g6t_2r_q,
pc_mm_abist_di_g6t_2r_q,
pc_mm_abist_g6t_r_wb_q} )
);
assign abist_siv = {abist_sov[1:41], abst_scan_in_q[0]};
assign abst_scan_in_int[0] = abist_sov[0];
assign abst_scan_in_int[1] = abst_scan_in_q[1];
// unused spare signal assignments
assign unused_dc[0] = pc_fce_0_int;
assign unused_dc[1] = pc_cfg_slp_sl_thold_0_int;
assign unused_dc[2] = pc_func_nsl_thold_0_int;
assign unused_dc[3] = pc_func_slp_nsl_thold_0_int;
assign unused_dc[4] = |(pc_func_sl_force_int);
assign unused_dc[5] = |(pc_func_slp_sl_force_int);
endmodule |
module pcq_local_fir2(
// Include model build parameters
`include "tri_a2o.vh"
nclk,
vdd,
gnd,
lcb_clkoff_dc_b,
lcb_mpw1_dc_b,
lcb_mpw2_dc_b,
lcb_delay_lclkr_dc,
lcb_act_dis_dc,
lcb_sg_0,
lcb_func_slp_sl_thold_0,
lcb_cfg_slp_sl_thold_0,
mode_scan_siv,
mode_scan_sov,
func_scan_siv,
func_scan_sov,
sys_xstop_in,
error_in,
xstop_err,
recov_err,
lxstop_mchk,
trace_error,
recov_reset,
fir_out,
act0_out,
act1_out,
mask_out,
sc_parity_error_inject,
sc_active,
sc_wr_q,
sc_addr_v,
sc_wdata,
sc_rdata,
fir_parity_check
);
parameter WIDTH = 1; // this must be >=1 and <=64
parameter IMPL_LXSTOP_MCHK = 1'b1; // generate local checkstop /machine check output
parameter USE_RECOV_RESET = 1'b0; // this adds a reset feature without the second wof register.
parameter [0:WIDTH-1] FIR_INIT = 1'b0; // init value for fir register; length = width !
parameter [0:WIDTH-1] FIR_MASK_INIT = 1'b0; // init value for fir mask register; length = width !
parameter FIR_MASK_PAR_INIT = 1'b0; // init value for fir mask register even parity
parameter [0:WIDTH-1] FIR_ACTION0_INIT = 1'b0; // init value for fir action0 register; length = width !
parameter FIR_ACTION0_PAR_INIT = 1'b0; // init value for fir action0 register even parity
parameter [0:WIDTH-1] FIR_ACTION1_INIT = 1'b0; // init value for fir action1 register; length = width !
parameter FIR_ACTION1_PAR_INIT = 1'b0; // init value for fir action1 register even parity
//=====================================================================
// Port Definitions
//=====================================================================
// Global lines for clocking and scan control
input [0:`NCLK_WIDTH-1] nclk;
inout vdd;
inout gnd;
input lcb_clkoff_dc_b; //from lcb_cntl external to component
input lcb_mpw1_dc_b; //from lcb_cntl external to component
input lcb_mpw2_dc_b; //from lcb_cntl external to component
input lcb_delay_lclkr_dc; //from lcb_cntl external to component
input lcb_act_dis_dc; //from lcb_cntl external to component
input lcb_sg_0;
input lcb_func_slp_sl_thold_0;
input lcb_cfg_slp_sl_thold_0;
input [0:3*(WIDTH+1)+WIDTH-1] mode_scan_siv; // scan vector in
output [0:3*(WIDTH+1)+WIDTH-1] mode_scan_sov; // scan vector out
input [0:4] func_scan_siv; // scan vector in
output [0:4] func_scan_sov; // scan vector out
// External interface
input sys_xstop_in; // freeze FIR on system checkstop from chip GEM
input [0:WIDTH-1] error_in; // needs to be directly off a latch for timing
output xstop_err; // checkstop output to Global FIR
output recov_err; // recoverable output to Global FIR
output lxstop_mchk; // use ONLY if IMPL_LXSTOP_MCHK = true
output trace_error; // connect to error_input of closest trdata macro
input recov_reset; // only needed if USE_RECOV_RESET = true
output [0:WIDTH-1] fir_out; // output of current FIR state if needed
output [0:WIDTH-1] act0_out; // output of current FIR Act0 state if needed
output [0:WIDTH-1] act1_out; // output of current FIR Act1 state if needed
output [0:WIDTH-1] mask_out; // output of current FIR Mask state if needed
// SCOM register connections
input sc_parity_error_inject; // Force parity error
input sc_active;
input sc_wr_q;
input [0:8] sc_addr_v;
input [0:WIDTH-1] sc_wdata;
output [0:WIDTH-1] sc_rdata;
output [0:2] fir_parity_check; // Action0, Action1, Mask reg parity checks
//=====================================================================
// Signal Declarations
//=====================================================================
// Clocks
wire func_d1clk;
wire func_d2clk;
wire [0:`NCLK_WIDTH-1] func_lclk;
wire mode_d1clk;
wire mode_d2clk;
wire [0:`NCLK_WIDTH-1] mode_lclk;
wire scom_mode_d1clk;
wire scom_mode_d2clk;
wire [0:`NCLK_WIDTH-1] scom_mode_lclk;
wire func_thold_b;
wire func_force;
wire mode_thold_b;
wire mode_force;
// FIR regs
wire [0:WIDTH-1] data_ones;
wire [0:WIDTH-1] or_fir;
wire [0:WIDTH-1] and_fir;
wire [0:WIDTH-1] or_mask;
wire [0:WIDTH-1] and_mask;
wire [0:WIDTH-1] fir_mask_in;
wire [0:WIDTH-1] fir_mask_lt;
wire [0:WIDTH-1] masked;
wire fir_mask_par_in;
wire fir_mask_par_lt;
wire fir_mask_par_err;
wire [0:WIDTH-1] fir_action0_in;
wire [0:WIDTH-1] fir_action0_lt;
wire fir_action0_par_in;
wire fir_action0_par_lt;
wire fir_action0_par_err;
wire [0:WIDTH-1] fir_action1_in;
wire [0:WIDTH-1] fir_action1_lt;
wire fir_action1_par_in;
wire fir_action1_par_lt;
wire fir_action1_par_err;
wire [0:WIDTH-1] fir_reset;
wire [0:WIDTH-1] error_input;
wire [0:WIDTH-1] fir_error_in_reef;
wire [0:WIDTH-1] fir_in;
wire [0:WIDTH-1] fir_lt;
wire fir_act;
wire block_fir;
wire or_fir_load;
wire and_fir_ones;
wire and_fir_load;
wire or_mask_load;
wire and_mask_ones;
wire and_mask_load;
// Error report
wire sys_xstop_lt;
wire recov_in;
wire recov_lt;
wire xstop_in;
wire xstop_lt;
wire trace_error_in;
wire trace_error_lt;
// Other
wire tieup;
// Scan chain hookups
wire [0:3*(WIDTH+1)+WIDTH-1] mode_si;
wire [0:3*(WIDTH+1)+WIDTH-1] mode_so;
wire [0:4] func_si;
wire [0:4] func_so;
// Get rid of sinkless net messages
// synopsys translate_off
(* analysis_not_referenced="true" *)
// synopsys translate_on
wire unused_signals;
assign unused_signals = recov_reset | sc_addr_v[5];
assign tieup = 1'b1;
assign data_ones = {WIDTH {1'b1}};
//******************************************************
//* LCB driver, LCB and Register Instantiations
//******************************************************
// functional ring regs; NOT power managed
tri_lcbor func_lcbor(
.clkoff_b(lcb_clkoff_dc_b),
.thold(lcb_func_slp_sl_thold_0),
.sg(lcb_sg_0),
.act_dis(lcb_act_dis_dc),
.force_t(func_force),
.thold_b(func_thold_b)
);
tri_lcbnd func_lcb(
.act(tieup), // not power managed
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.nclk(nclk),
.force_t(func_force),
.sg(lcb_sg_0),
.thold_b(func_thold_b),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk)
);
// config ring regs; NOT power managed
tri_lcbor mode_lcbor(
.clkoff_b(lcb_clkoff_dc_b),
.thold(lcb_cfg_slp_sl_thold_0),
.sg(lcb_sg_0),
.act_dis(lcb_act_dis_dc),
.force_t(mode_force),
.thold_b(mode_thold_b)
);
assign fir_act = sc_active | (|error_in);
tri_lcbnd mode_lcb(
.act(fir_act), // active during scom access or FIR error input
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.nclk(nclk),
.force_t(mode_force),
.sg(lcb_sg_0),
.thold_b(mode_thold_b),
.d1clk(mode_d1clk),
.d2clk(mode_d2clk),
.lclk(mode_lclk)
);
tri_lcbnd scom_mode_lcb(
.act(sc_active), // active during scom access
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.nclk(nclk),
.force_t(mode_force),
.sg(lcb_sg_0),
.thold_b(mode_thold_b),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk)
);
//--------------------------------------------------------------------
// Mode Registers
//--------------------------------------------------------------------
tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_ACTION0_INIT)) fir_action0(
.vd(vdd),
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.scan_in( mode_si[0:WIDTH - 1]),
.scan_out(mode_so[0:WIDTH - 1]),
.din(fir_action0_in),
.q(fir_action0_lt)
);
tri_nlat_scan #(.WIDTH(1), .INIT(FIR_ACTION0_PAR_INIT)) fir_action0_par(
.vd(vdd),
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.scan_in( mode_si[WIDTH:WIDTH]),
.scan_out(mode_so[WIDTH:WIDTH]),
.din(fir_action0_par_in),
.q(fir_action0_par_lt)
);
tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_ACTION1_INIT)) fir_action1(
.vd(vdd),
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.scan_in( mode_si[(WIDTH + 1):(2*WIDTH)]),
.scan_out(mode_so[(WIDTH + 1):(2*WIDTH)]),
.din(fir_action1_in),
.q(fir_action1_lt)
);
tri_nlat_scan #(.WIDTH(1), .INIT(FIR_ACTION1_PAR_INIT)) fir_action1_par(
.vd(vdd),
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.scan_in( mode_si[(2*WIDTH + 1):(2*WIDTH + 1)]),
.scan_out(mode_so[(2*WIDTH + 1):(2*WIDTH + 1)]),
.din(fir_action1_par_in),
.q(fir_action1_par_lt)
);
tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_MASK_INIT)) fir_mask(
.vd(vdd),
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.scan_in( mode_si[(2*WIDTH + 2):(3*WIDTH + 1)]),
.scan_out(mode_so[(2*WIDTH + 2):(3*WIDTH + 1)]),
.din(fir_mask_in),
.q(fir_mask_lt)
);
tri_nlat_scan #(.WIDTH(1), .INIT(FIR_MASK_PAR_INIT)) fir_mask_par(
.vd(vdd),
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.scan_in( mode_si[(3*WIDTH + 2):(3*WIDTH + 2)]),
.scan_out(mode_so[(3*WIDTH + 2):(3*WIDTH + 2)]),
.din(fir_mask_par_in),
.q(fir_mask_par_lt)
);
tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_INIT)) fir(
.vd(vdd),
.gd(gnd),
.d1clk(mode_d1clk),
.d2clk(mode_d2clk),
.lclk(mode_lclk),
.scan_in( mode_si[(3*WIDTH + 3):(4*WIDTH + 2)]),
.scan_out(mode_so[(3*WIDTH + 3):(4*WIDTH + 2)]),
.din(fir_in),
.q(fir_lt)
);
//--------------------------------------------------------------------
// Func Registers with no power savings
//--------------------------------------------------------------------
tri_nlat #(.WIDTH(1), .INIT(1'b0)) sys_xstop(
.vd(vdd),
.gd(gnd),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk),
.scan_in(func_si[1]),
.scan_out(func_so[1]),
.din(sys_xstop_in),
.q(sys_xstop_lt)
);
tri_nlat #(.WIDTH(1), .INIT(1'b0)) recov(
.vd(vdd),
.gd(gnd),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk),
.scan_in(func_si[2]),
.scan_out(func_so[2]),
.din(recov_in),
.q(recov_lt)
);
tri_nlat #(.WIDTH(1), .INIT(1'b0)) xstop(
.vd(vdd),
.gd(gnd),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk),
.scan_in(func_si[3]),
.scan_out(func_so[3]),
.din(xstop_in),
.q(xstop_lt)
);
tri_nlat #(.WIDTH(1), .INIT(1'b0)) trace_err(
.vd(vdd),
.gd(gnd),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk),
.scan_in(func_si[4]),
.scan_out(func_so[4]),
.din(trace_error_in),
.q(trace_error_lt)
);
//******************************************************
//* Optional Recovery Reset
//******************************************************
generate
if (USE_RECOV_RESET == 1'b1)
begin : use_recov_reset_yes
assign fir_reset = (~({WIDTH {recov_reset}} & (~fir_action0_lt) & fir_action1_lt));
end
endgenerate
generate
if (USE_RECOV_RESET == 1'b0)
begin : use_recov_reset_no
assign fir_reset = {WIDTH {1'b1}};
end
endgenerate
//******************************************************
//* FIR
//******************************************************
// write to x'0' to write FIR directly
// write to x'1' to And-Mask FIR
// write to x'2' to Or-Mask FIR
assign or_fir_load = (sc_addr_v[0] | sc_addr_v[2]) & sc_wr_q;
assign and_fir_ones = (~((sc_addr_v[0] | sc_addr_v[1]) & sc_wr_q));
assign and_fir_load = sc_addr_v[1] & sc_wr_q;
assign or_fir = ({WIDTH {or_fir_load}} & sc_wdata);
assign and_fir = ({WIDTH {and_fir_load}} & sc_wdata) | ({WIDTH {and_fir_ones}} & data_ones);
assign fir_in = ({WIDTH {~block_fir}} & error_input) | or_fir | (fir_lt & and_fir & fir_reset);
assign fir_error_in_reef = error_in; // does a signal rename for the reef tool
assign error_input = fir_error_in_reef;
//******************************************************
//* FIR Mask
//******************************************************
// write to x'6' to write FIR-MASK directly
// write to x'7' to And-Mask FIR-MASK
// write to x'8' to Or-Mask FIR-MASK
assign or_mask_load = (sc_addr_v[6] | sc_addr_v[8]) & sc_wr_q;
assign and_mask_ones = (~((sc_addr_v[6] | sc_addr_v[7]) & sc_wr_q));
assign and_mask_load = sc_addr_v[7] & sc_wr_q;
assign or_mask = ({WIDTH {or_mask_load}} & sc_wdata);
assign and_mask = ({WIDTH {and_mask_load}} & sc_wdata) | ({WIDTH {and_mask_ones}} & data_ones);
assign fir_mask_in = or_mask | (fir_mask_lt & and_mask);
assign fir_mask_par_in = ((sc_wr_q & (|sc_addr_v[6:8])) == 1'b1) ? (^fir_mask_in) : fir_mask_par_lt;
assign fir_mask_par_err = ((^fir_mask_lt) ^ fir_mask_par_lt) | (sc_wr_q & (|sc_addr_v[6:8]) & sc_parity_error_inject);
assign masked = fir_mask_lt;
//******************************************************
//* Action Registers
//******************************************************
// write to x'3' to write FIR-Action0 directly
assign fir_action0_in = ((sc_wr_q & sc_addr_v[3]) == 1'b1) ? sc_wdata : fir_action0_lt;
assign fir_action0_par_in = ((sc_wr_q & sc_addr_v[3]) == 1'b1) ? (^fir_action0_in) : fir_action0_par_lt;
assign fir_action0_par_err = ((^fir_action0_lt) ^ fir_action0_par_lt) | (sc_wr_q & sc_addr_v[3] & sc_parity_error_inject);
// write to x'4' to write FIR-Action1 directly
assign fir_action1_in = ((sc_wr_q & sc_addr_v[4]) == 1'b1) ? sc_wdata : fir_action1_lt;
assign fir_action1_par_in = ((sc_wr_q & sc_addr_v[4]) == 1'b1) ? (^fir_action1_in) : fir_action1_par_lt;
assign fir_action1_par_err = ((^fir_action1_lt) ^ fir_action1_par_lt) | (sc_wr_q & sc_addr_v[4] & sc_parity_error_inject);
//******************************************************
//* Summary
//******************************************************
assign xstop_in = (|(fir_lt & fir_action0_lt & (~fir_action1_lt) & (~masked))); // fir_action = 10
assign recov_in = (|(fir_lt & (~fir_action0_lt) & fir_action1_lt & (~masked))); // fir_action = 01
assign block_fir = xstop_lt | sys_xstop_lt;
assign xstop_err = xstop_lt;
assign recov_err = recov_lt;
assign trace_error = trace_error_lt;
assign fir_out = fir_lt;
assign act0_out = fir_action0_lt;
assign act1_out = fir_action1_lt;
assign mask_out = fir_mask_lt;
assign fir_parity_check = {fir_action0_par_err, fir_action1_par_err, fir_mask_par_err};
//******************************************************
//* SCOM read logic
//******************************************************
assign sc_rdata = ({WIDTH {sc_addr_v[0]}} & fir_lt) |
({WIDTH {sc_addr_v[3]}} & fir_action0_lt) |
({WIDTH {sc_addr_v[4]}} & fir_action1_lt) |
({WIDTH {sc_addr_v[6]}} & fir_mask_lt) ;
//******************************************************
//* Optional MCHK Enable Register and Output
//******************************************************
generate
if (IMPL_LXSTOP_MCHK == 1'b1)
begin : mchkgen
wire lxstop_mchk_in;
wire lxstop_mchk_lt;
assign lxstop_mchk_in = (|(fir_lt & fir_action0_lt & fir_action1_lt & (~masked))); // fir_action = 11
assign lxstop_mchk = lxstop_mchk_lt;
assign trace_error_in = xstop_in | recov_in | lxstop_mchk_in;
tri_nlat #(.WIDTH(1), .INIT(1'b0)) mchk(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.d2clk(func_d2clk),
.scan_in(func_si[0]),
.scan_out(func_so[0]),
.din(lxstop_mchk_in),
.q(lxstop_mchk_lt)
);
end
endgenerate
generate
if (IMPL_LXSTOP_MCHK == 1'b0)
begin : nomchk
assign trace_error_in = xstop_in | recov_in;
assign lxstop_mchk = 1'b0;
assign func_so[0] = func_si[0];
end
endgenerate
//******************************************************
// Scan Chain Connections
//******************************************************
assign mode_si = mode_scan_siv;
assign mode_scan_sov = mode_so;
assign func_si = func_scan_siv;
assign func_scan_sov = func_so;
endmodule |
module xu0_bprm(
a,
s,
y
);
// IOs
input [0:63] a;
input [0:7] s;
output y;
// Signals
wire [0:7] mh;
wire [0:7] ml;
wire [0:63] a1;
wire [0:63] a2;
assign mh[0:7] = (s[0:4] == 5'b00000) ? 8'b10000000 :
(s[0:4] == 5'b00001) ? 8'b01000000 :
(s[0:4] == 5'b00010) ? 8'b00100000 :
(s[0:4] == 5'b00011) ? 8'b00010000 :
(s[0:4] == 5'b00100) ? 8'b00001000 :
(s[0:4] == 5'b00101) ? 8'b00000100 :
(s[0:4] == 5'b00110) ? 8'b00000010 :
(s[0:4] == 5'b00111) ? 8'b00000001 :
8'b00000000 ;
assign ml[0:7] = (s[5:7] == 3'b000) ? 8'b10000000 :
(s[5:7] == 3'b001) ? 8'b01000000 :
(s[5:7] == 3'b010) ? 8'b00100000 :
(s[5:7] == 3'b011) ? 8'b00010000 :
(s[5:7] == 3'b100) ? 8'b00001000 :
(s[5:7] == 3'b101) ? 8'b00000100 :
(s[5:7] == 3'b110) ? 8'b00000010 :
8'b00000001;
genvar i;
generate for (i=0; i<=7; i=i+1)
begin : msk
assign a1[8*i:8*i+7] = a[8*i:8*i+7] & ml[0:7];
assign a2[8*i:8*i+7] = a1[8*i:8*i+7] & {8{mh[i]}};
end
endgenerate
assign y = |a2;
endmodule |
module pcq_clks_stg(
// Include model build parameters
`include "tri_a2o.vh"
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input ccflush_out_dc,
input gptr_sl_thold_5,
input time_sl_thold_5,
input repr_sl_thold_5,
input cfg_sl_thold_5,
input cfg_slp_sl_thold_5,
input abst_sl_thold_5,
input abst_slp_sl_thold_5,
input regf_sl_thold_5,
input regf_slp_sl_thold_5,
input func_sl_thold_5,
input func_slp_sl_thold_5,
input func_nsl_thold_5,
input func_slp_nsl_thold_5,
input ary_nsl_thold_5,
input ary_slp_nsl_thold_5,
input rtim_sl_thold_5,
input sg_5,
input fce_5,
// Thold + control outputs to the units
output pc_pc_ccflush_out_dc,
output pc_pc_gptr_sl_thold_4,
output pc_pc_time_sl_thold_4,
output pc_pc_repr_sl_thold_4,
output pc_pc_abst_sl_thold_4,
output pc_pc_abst_slp_sl_thold_4,
output pc_pc_regf_sl_thold_4,
output pc_pc_regf_slp_sl_thold_4,
output pc_pc_func_sl_thold_4,
output pc_pc_func_slp_sl_thold_4,
output pc_pc_cfg_sl_thold_4,
output pc_pc_cfg_slp_sl_thold_4,
output pc_pc_func_nsl_thold_4,
output pc_pc_func_slp_nsl_thold_4,
output pc_pc_ary_nsl_thold_4,
output pc_pc_ary_slp_nsl_thold_4,
output pc_pc_rtim_sl_thold_4,
output pc_pc_sg_4,
output pc_pc_fce_4,
// Thold + control signals used by fu
output pc_fu_ccflush_dc,
output pc_fu_gptr_sl_thold_3,
output pc_fu_time_sl_thold_3,
output pc_fu_repr_sl_thold_3,
output pc_fu_abst_sl_thold_3,
output pc_fu_abst_slp_sl_thold_3,
output [0:1] pc_fu_func_sl_thold_3,
output [0:1] pc_fu_func_slp_sl_thold_3,
output pc_fu_cfg_sl_thold_3,
output pc_fu_cfg_slp_sl_thold_3,
output pc_fu_func_nsl_thold_3,
output pc_fu_func_slp_nsl_thold_3,
output pc_fu_ary_nsl_thold_3,
output pc_fu_ary_slp_nsl_thold_3,
output [0:1] pc_fu_sg_3,
output pc_fu_fce_3,
// Thold + control signals used in pcq
output pc_pc_ccflush_dc,
output pc_pc_gptr_sl_thold_0,
output pc_pc_func_sl_thold_0,
output pc_pc_func_slp_sl_thold_0,
output pc_pc_cfg_sl_thold_0,
output pc_pc_cfg_slp_sl_thold_0,
output pc_pc_sg_0
);
//=====================================================================
// Signal Declarations
//=====================================================================
wire pc_pc_gptr_sl_thold_4_int;
wire pc_pc_time_sl_thold_4_int;
wire pc_pc_repr_sl_thold_4_int;
wire pc_pc_abst_sl_thold_4_int;
wire pc_pc_abst_slp_sl_thold_4_int;
wire pc_pc_regf_sl_thold_4_int;
wire pc_pc_regf_slp_sl_thold_4_int;
wire pc_pc_func_sl_thold_4_int;
wire pc_pc_func_slp_sl_thold_4_int;
wire pc_pc_cfg_sl_thold_4_int;
wire pc_pc_cfg_slp_sl_thold_4_int;
wire pc_pc_func_nsl_thold_4_int;
wire pc_pc_func_slp_nsl_thold_4_int;
wire pc_pc_ary_nsl_thold_4_int;
wire pc_pc_ary_slp_nsl_thold_4_int;
wire pc_pc_rtim_sl_thold_4_int;
wire pc_pc_sg_4_int;
wire pc_pc_fce_4_int;
wire pc_pc_gptr_sl_thold_3;
wire pc_pc_abst_sl_thold_3;
wire pc_pc_func_sl_thold_3;
wire pc_pc_func_slp_sl_thold_3;
wire pc_pc_cfg_slp_sl_thold_3;
wire pc_pc_cfg_sl_thold_3;
wire pc_pc_sg_3;
wire pc_pc_gptr_sl_thold_2;
wire pc_pc_abst_sl_thold_2;
wire pc_pc_func_sl_thold_2;
wire pc_pc_func_slp_sl_thold_2;
wire pc_pc_cfg_slp_sl_thold_2;
wire pc_pc_cfg_sl_thold_2;
wire pc_pc_sg_2;
wire pc_pc_gptr_sl_thold_1;
wire pc_pc_abst_sl_thold_1;
wire pc_pc_func_sl_thold_1;
wire pc_pc_func_slp_sl_thold_1;
wire pc_pc_cfg_slp_sl_thold_1;
wire pc_pc_cfg_sl_thold_1;
wire pc_pc_sg_1;
//=====================================================================
// LCB control signals staged/redriven to other units
//=====================================================================
assign pc_pc_ccflush_out_dc = ccflush_out_dc;
assign pc_pc_ccflush_dc = ccflush_out_dc;
assign pc_fu_ccflush_dc = ccflush_out_dc;
// Start of thold/SG/FCE staging (level 5 to level 3)
tri_plat #(.WIDTH(18)) lvl5to4_plat(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din({gptr_sl_thold_5, time_sl_thold_5, repr_sl_thold_5,
rtim_sl_thold_5, abst_sl_thold_5, abst_slp_sl_thold_5,
regf_sl_thold_5, regf_slp_sl_thold_5, func_sl_thold_5,
func_slp_sl_thold_5, cfg_sl_thold_5, cfg_slp_sl_thold_5,
func_nsl_thold_5, func_slp_nsl_thold_5, ary_nsl_thold_5,
ary_slp_nsl_thold_5, sg_5, fce_5}),
.q( {pc_pc_gptr_sl_thold_4_int, pc_pc_time_sl_thold_4_int, pc_pc_repr_sl_thold_4_int,
pc_pc_rtim_sl_thold_4_int, pc_pc_abst_sl_thold_4_int, pc_pc_abst_slp_sl_thold_4_int,
pc_pc_regf_sl_thold_4_int, pc_pc_regf_slp_sl_thold_4_int, pc_pc_func_sl_thold_4_int,
pc_pc_func_slp_sl_thold_4_int, pc_pc_cfg_sl_thold_4_int, pc_pc_cfg_slp_sl_thold_4_int,
pc_pc_func_nsl_thold_4_int, pc_pc_func_slp_nsl_thold_4_int, pc_pc_ary_nsl_thold_4_int,
pc_pc_ary_slp_nsl_thold_4_int, pc_pc_sg_4_int, pc_pc_fce_4_int})
);
// Level 4 staging goes to the pervasive repower logic
assign pc_pc_gptr_sl_thold_4 = pc_pc_gptr_sl_thold_4_int;
assign pc_pc_time_sl_thold_4 = pc_pc_time_sl_thold_4_int;
assign pc_pc_repr_sl_thold_4 = pc_pc_repr_sl_thold_4_int;
assign pc_pc_abst_sl_thold_4 = pc_pc_abst_sl_thold_4_int;
assign pc_pc_abst_slp_sl_thold_4 = pc_pc_abst_slp_sl_thold_4_int;
assign pc_pc_regf_sl_thold_4 = pc_pc_regf_sl_thold_4_int;
assign pc_pc_regf_slp_sl_thold_4 = pc_pc_regf_slp_sl_thold_4_int;
assign pc_pc_func_sl_thold_4 = pc_pc_func_sl_thold_4_int;
assign pc_pc_func_slp_sl_thold_4 = pc_pc_func_slp_sl_thold_4_int;
assign pc_pc_cfg_sl_thold_4 = pc_pc_cfg_sl_thold_4_int;
assign pc_pc_cfg_slp_sl_thold_4 = pc_pc_cfg_slp_sl_thold_4_int;
assign pc_pc_func_nsl_thold_4 = pc_pc_func_nsl_thold_4_int;
assign pc_pc_func_slp_nsl_thold_4 = pc_pc_func_slp_nsl_thold_4_int;
assign pc_pc_ary_nsl_thold_4 = pc_pc_ary_nsl_thold_4_int;
assign pc_pc_ary_slp_nsl_thold_4 = pc_pc_ary_slp_nsl_thold_4_int;
assign pc_pc_rtim_sl_thold_4 = pc_pc_rtim_sl_thold_4_int;
assign pc_pc_sg_4 = pc_pc_sg_4_int;
assign pc_pc_fce_4 = pc_pc_fce_4_int;
// FU clock control staging: level 4 to 3
tri_plat #(.WIDTH(18)) fu_clkstg_4to3(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din({pc_pc_gptr_sl_thold_4_int, pc_pc_time_sl_thold_4_int, pc_pc_repr_sl_thold_4_int,
pc_pc_abst_sl_thold_4_int, pc_pc_abst_slp_sl_thold_4_int, pc_pc_func_sl_thold_4_int,
pc_pc_func_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int,
pc_pc_cfg_sl_thold_4_int, pc_pc_cfg_slp_sl_thold_4_int, pc_pc_func_nsl_thold_4_int,
pc_pc_func_slp_nsl_thold_4_int, pc_pc_ary_nsl_thold_4_int, pc_pc_ary_slp_nsl_thold_4_int,
pc_pc_sg_4_int, pc_pc_sg_4_int, pc_pc_fce_4_int }),
.q( {pc_fu_gptr_sl_thold_3, pc_fu_time_sl_thold_3, pc_fu_repr_sl_thold_3,
pc_fu_abst_sl_thold_3, pc_fu_abst_slp_sl_thold_3, pc_fu_func_sl_thold_3[0],
pc_fu_func_sl_thold_3[1], pc_fu_func_slp_sl_thold_3[0], pc_fu_func_slp_sl_thold_3[1],
pc_fu_cfg_sl_thold_3, pc_fu_cfg_slp_sl_thold_3, pc_fu_func_nsl_thold_3,
pc_fu_func_slp_nsl_thold_3, pc_fu_ary_nsl_thold_3, pc_fu_ary_slp_nsl_thold_3,
pc_fu_sg_3[0], pc_fu_sg_3[1], pc_fu_fce_3 })
);
// PC clock control staging: level 4 to 3
tri_plat #(.WIDTH(6)) pc_lvl4to3(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din({pc_pc_func_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int, pc_pc_cfg_sl_thold_4_int,
pc_pc_cfg_slp_sl_thold_4_int, pc_pc_gptr_sl_thold_4_int, pc_pc_sg_4_int}),
.q( {pc_pc_func_sl_thold_3, pc_pc_func_slp_sl_thold_3, pc_pc_cfg_sl_thold_3,
pc_pc_cfg_slp_sl_thold_3, pc_pc_gptr_sl_thold_3, pc_pc_sg_3})
);
// End of thold/SG/FCE staging (level 5 to level 3)
//=====================================================================
// thold/SG staging (level 3 to level 0) for PC units
//=====================================================================
//----------------------------------------------------
// FUNC (RUN)
//----------------------------------------------------
tri_plat #(.WIDTH(1)) func_3_2(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_func_sl_thold_3),
.q(pc_pc_func_sl_thold_2)
);
tri_plat #(.WIDTH(1)) func_2_1(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_func_sl_thold_2),
.q(pc_pc_func_sl_thold_1)
);
tri_plat #(.WIDTH(1)) func_1_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_func_sl_thold_1),
.q(pc_pc_func_sl_thold_0)
);
//----------------------------------------------------
// FUNC (SLEEP)
//----------------------------------------------------
tri_plat #(.WIDTH(1)) func_slp_3_2(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_func_slp_sl_thold_3),
.q(pc_pc_func_slp_sl_thold_2)
);
tri_plat #(.WIDTH(1)) func_slp_2_1(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_func_slp_sl_thold_2),
.q(pc_pc_func_slp_sl_thold_1)
);
tri_plat #(.WIDTH(1)) func_slp_1_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_func_slp_sl_thold_1),
.q(pc_pc_func_slp_sl_thold_0)
);
//----------------------------------------------------
// CFG (RUN)
//----------------------------------------------------
tri_plat #(.WIDTH(1)) cfg_3_2(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_cfg_sl_thold_3),
.q(pc_pc_cfg_sl_thold_2)
);
tri_plat #(.WIDTH(1)) cfg_2_1(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_cfg_sl_thold_2),
.q(pc_pc_cfg_sl_thold_1)
);
tri_plat #(.WIDTH(1)) cfg_1_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_cfg_sl_thold_1),
.q(pc_pc_cfg_sl_thold_0)
);
//----------------------------------------------------
// CFG (SLEEP)
//----------------------------------------------------
tri_plat #(.WIDTH(1)) cfg_slp_3_2(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_cfg_slp_sl_thold_3),
.q(pc_pc_cfg_slp_sl_thold_2)
);
tri_plat #(.WIDTH(1)) cfg_slp_2_1(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_cfg_slp_sl_thold_2),
.q(pc_pc_cfg_slp_sl_thold_1)
);
tri_plat #(.WIDTH(1)) cfg_slp_1_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_cfg_slp_sl_thold_1),
.q(pc_pc_cfg_slp_sl_thold_0)
);
//----------------------------------------------------
// GPTR
//----------------------------------------------------
tri_plat #(.WIDTH(1)) gptr_3_2(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_gptr_sl_thold_3),
.q(pc_pc_gptr_sl_thold_2)
);
tri_plat #(.WIDTH(1)) gptr_2_1(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_gptr_sl_thold_2),
.q(pc_pc_gptr_sl_thold_1)
);
tri_plat #(.WIDTH(1)) gptr_1_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_gptr_sl_thold_1),
.q(pc_pc_gptr_sl_thold_0)
);
//----------------------------------------------------
// SG
//----------------------------------------------------
tri_plat #(.WIDTH(1)) sg_3_2(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_sg_3),
.q(pc_pc_sg_2)
);
tri_plat #(.WIDTH(1)) sg_2_1(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_sg_2),
.q(pc_pc_sg_1)
);
tri_plat #(.WIDTH(1)) sg_1_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_out_dc),
.din(pc_pc_sg_1),
.q(pc_pc_sg_0)
);
endmodule |
module lq_agen_lo(
x_b,
y_b,
sum,
sum_arr,
dir_ig_57_b
);
input [0:11] x_b; // after xor
input [0:11] y_b;
input dir_ig_57_b; // when this is low , bit 57 becomes "1" .
output [0:11] sum;
output [0:5] sum_arr;
wire [0:11] p01_b;
wire [0:11] p01;
wire [1:11] g01;
wire [1:10] t01;
wire [0:11] sum_x;
wire [0:11] sum_b;
wire sum_x_11_b;
wire [1:11] g12_x_b;
wire [1:11] g02_b;
wire [1:11] g04;
wire [1:11] c;
wire [1:7] g12_y_b;
wire [1:3] g12_z_b;
wire [1:9] t02_b;
wire [1:7] t04;
//####################################################################
//# propagate, generate, transmit
//####################################################################
//assign g01[1:11] = (~(x_b[1:11] | y_b[1:11]));
tri_nor2 #(.WIDTH(11)) g01_1 (.y(g01[1:11]), .a(x_b[1:11]), .b(y_b[1:11]));
//assign t01[1:10] = (~(x_b[1:10] & y_b[1:10]));
tri_nand2 #(.WIDTH(10)) t01_1 (.y(t01[1:10]), .a(x_b[1:10]), .b(y_b[1:10]));
//assign p01_b[0:11] = (~(x_b[0:11] ^ y_b[0:11]));
tri_xnor2 #(.WIDTH(12)) p01_b_1 (.y(p01_b[0:11]), .a(x_b[0:11]), .b(y_b[0:11]));
//assign p01[0:11] = (~(p01_b[0:11]));
tri_inv #(.WIDTH(12)) p01_0 (.y(p01[0:11]), .a(p01_b[0:11]));
//####################################################################
//# final sum and drive
//####################################################################
//assign sum_x[0:10] = p01[0:10] ^ c[1:11];
tri_xor2 #(.WIDTH(11)) sum_x_0 (.y(sum_x[0:10]), .a(p01[0:10]), .b(c[1:11]));
//assign sum_x_11_b = (~(p01[11]));
tri_inv sum_x_11_b_11 (.y(sum_x_11_b), .a(p01[11]));
//assign sum_x[11] = (~(sum_x_11_b));
tri_inv sum_x_11 (.y(sum_x[11]), .a(sum_x_11_b));
// 00 01 02 03 04 05 06 07 08 09 10 11
// 52 53 54 55 56 57 58 59 60 61 62 63
//assign sum_b[0:11] = (~(sum_x[0:11]));
tri_inv #(.WIDTH(12)) sum_b_0 (.y(sum_b[0:11]), .a(sum_x[0:11]));
//assign sum[0:11] = (~(sum_b[0:11]));
tri_inv #(.WIDTH(12)) sum_0 (.y(sum[0:11]), .a(sum_b[0:11]));
//assign sum_arr[0] = (~(sum_b[0]));
tri_inv #(.WIDTH(5)) sum_arr_0 (.y(sum_arr[0:4]), .a(sum_b[0:4]));
//assign sum_arr[5] = (~(sum_b[5] & dir_ig_57_b)); // OR with negative inputs
tri_nand2 sum_arr_5 (.y(sum_arr[5]), .a(sum_b[5]), .b(dir_ig_57_b));
//####################################################################
//# carry path is cogge-stone
//####################################################################
//assign g02_b[1] = (~(g01[1] | (t01[1] & g01[2])));
tri_aoi21 #(.WIDTH(10)) g02_b_1 (.y(g02_b[1:10]), .a0(t01[1:10]), .a1(g01[2:11]), .b0(g01[1:10]));
//assign g02_b[11] = (~(g01[11]));
tri_inv g02_b_11 (.y(g02_b[11]), .a(g01[11]));
//assign t02_b[1] = (~(t01[1] & t01[2]));
tri_nand2 #(.WIDTH(9)) t02_b_1 (.y(t02_b[1:9]), .a(t01[1:9]), .b(t01[2:10]));
//assign g04[1] = (~(g02_b[1] & (t02_b[1] | g02_b[3])));
tri_oai21 #(.WIDTH(9)) g04_1 (.y(g04[1:9]), .a0(t02_b[1:9]), .a1(g02_b[3:11]), .b0(g02_b[1:9]));
//assign g04[10] = (~(g02_b[10]));
tri_inv #(.WIDTH(2)) g04_10 (.y(g04[10:11]), .a(g02_b[10:11]));
//assign t04[1] = (~(t02_b[1] | t02_b[3]));
tri_nor2 #(.WIDTH(7)) t04_1 (.y(t04[1:7]), .a(t02_b[1:7]), .b(t02_b[3:9]));
//assign g12_x_b[1] = (~(g04[1]));
tri_inv g12_x_b_1 (.y(g12_x_b[1]), .a(g04[1]));
//assign g12_y_b[1] = (~(t04[1] & g04[5]));
tri_nand2 g12_y_b_1 (.y(g12_y_b[1]), .a(t04[1]), .b(g04[5]));
//assign g12_z_b[1] = (~(t04[1] & t04[5] & g04[9]));
tri_nand3 g12_z_b_1 (.y(g12_z_b[1]), .a(t04[1]), .b(t04[5]), .c(g04[9]));
//assign c[1] = (~(g12_x_b[1] & g12_y_b[1] & g12_z_b[1]));
tri_nand3 c_1 (.y(c[1]), .a(g12_x_b[1]), .b(g12_y_b[1]), .c(g12_z_b[1]));
//assign g12_x_b[2] = (~(g04[2]));
tri_inv g12_x_b_2 (.y(g12_x_b[2]), .a(g04[2]));
//assign g12_y_b[2] = (~(t04[2] & g04[6]));
tri_nand2 g12_y_b_2 (.y(g12_y_b[2]), .a(t04[2]), .b(g04[6]));
//assign g12_z_b[2] = (~(t04[2] & t04[6] & g04[10]));
tri_nand3 g12_z_b_2 (.y(g12_z_b[2]), .a(t04[2]), .b(t04[6]), .c(g04[10]));
//assign c[2] = (~(g12_x_b[2] & g12_y_b[2] & g12_z_b[2]));
tri_nand3 c_2 (.y(c[2]), .a(g12_x_b[2]), .b(g12_y_b[2]), .c(g12_z_b[2]));
//assign g12_x_b[3] = (~(g04[3]));
tri_inv g12_x_b_3 (.y(g12_x_b[3]), .a(g04[3]));
//assign g12_y_b[3] = (~(t04[3] & g04[7]));
tri_nand2 g12_y_b_3 (.y(g12_y_b[3]), .a(t04[3]), .b(g04[7]));
//assign g12_z_b[3] = (~(t04[3] & t04[7] & g04[11]));
tri_nand3 g12_z_b_3 (.y(g12_z_b[3]), .a(t04[3]), .b(t04[7]), .c(g04[11]));
//assign c[3] = (~(g12_x_b[3] & g12_y_b[3] & g12_z_b[3]));
tri_nand3 c_3 (.y(c[3]), .a(g12_x_b[3]), .b(g12_y_b[3]), .c(g12_z_b[3]));
//assign g12_x_b[4] = (~(g04[4]));
tri_inv g12_x_b_4 (.y(g12_x_b[4]), .a(g04[4]));
//assign g12_y_b[4] = (~(t04[4] & g04[8]));
tri_nand2 g12_y_b_4 (.y(g12_y_b[4]), .a(t04[4]), .b(g04[8]));
//assign c[4] = (~(g12_x_b[4] & g12_y_b[4]));
tri_nand2 c_4 (.y(c[4]), .a(g12_x_b[4]), .b(g12_y_b[4]));
//assign g12_x_b[5] = (~(g04[5]));
tri_inv g12_x_b_5 (.y(g12_x_b[5]), .a(g04[5]));
//assign g12_y_b[5] = (~(t04[5] & g04[9]));
tri_nand2 g12_y_b_5 (.y(g12_y_b[5]), .a(t04[5]), .b(g04[9]));
//assign c[5] = (~(g12_x_b[5] & g12_y_b[5]));
tri_nand2 c_5 (.y(c[5]), .a(g12_x_b[5]), .b(g12_y_b[5]));
//assign g12_x_b[6] = (~(g04[6]));
tri_inv g12_x_b_6 (.y(g12_x_b[6]), .a(g04[6]));
//assign g12_y_b[6] = (~(t04[6] & g04[10]));
tri_nand2 g12_y_b_6 (.y(g12_y_b[6]), .a(t04[6]), .b(g04[10]));
//assign c[6] = (~(g12_x_b[6] & g12_y_b[6]));
tri_nand2 c_6 (.y(c[6]), .a(g12_x_b[6]), .b(g12_y_b[6]));
//assign g12_x_b[7] = (~(g04[7]));
tri_inv g12_x_b_7 (.y(g12_x_b[7]), .a(g04[7]));
//assign g12_y_b[7] = (~(t04[7] & g04[11]));
tri_nand2 g12_y_b_7 (.y(g12_y_b[7]), .a(t04[7]), .b(g04[11]));
//assign c[7] = (~(g12_x_b[7] & g12_y_b[7]));
tri_nand2 c_7 (.y(c[7]), .a(g12_x_b[7]), .b(g12_y_b[7]));
//assign g12_x_b[8] = (~(g04[8]));
tri_inv g12_x_b_8 (.y(g12_x_b[8]), .a(g04[8]));
//assign c[8] = (~(g12_x_b[8]));
tri_inv c_8 (.y(c[8]), .a(g12_x_b[8]));
//assign g12_x_b[9] = (~(g04[9]));
tri_inv g12_x_b_9 (.y(g12_x_b[9]), .a(g04[9]));
//assign c[9] = (~(g12_x_b[9]));
tri_inv c_9 (.y(c[9]), .a(g12_x_b[9]));
//assign g12_x_b[10] = (~(g04[10]));
tri_inv g12_x_b_10 (.y(g12_x_b[10]), .a(g04[10]));
//assign c[10] = (~(g12_x_b[10]));
tri_inv c_10 (.y(c[10]), .a(g12_x_b[10]));
//assign g12_x_b[11] = (~(g04[11]));
tri_inv g12_x_b_11 (.y(g12_x_b[11]), .a(g04[11]));
//assign c[11] = (~(g12_x_b[11]));
tri_inv c_11 (.y(c[11]), .a(g12_x_b[11]));
endmodule |
module xu1(
//-------------------------------------------------------------------
// Clocks & Power
//-------------------------------------------------------------------
input [0:`NCLK_WIDTH-1] nclk,
inout vdd,
inout gnd,
//-------------------------------------------------------------------
// Pervasive
//-------------------------------------------------------------------
input d_mode_dc,
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input sg_0,
input scan_in,
output scan_out,
output xu1_pc_ram_done,
output [64-`GPR_WIDTH:63] xu1_pc_ram_data,
input xu0_xu1_ex3_act,
input lq_xu_ex5_act,
//-------------------------------------------------------------------
// Interface with SPR
//-------------------------------------------------------------------
input [0:`THREADS-1] spr_msr_cm, // 0: 32 bit mode, 1: 64 bit mode
//-------------------------------------------------------------------
// Interface with CP
//-------------------------------------------------------------------
input [0:`THREADS-1] cp_flush,
//-------------------------------------------------------------------
// Interface with RV
//-------------------------------------------------------------------
input [0:`THREADS-1] rv_xu1_vld,
input rv_xu1_s1_v,
input rv_xu1_s2_v,
input rv_xu1_s3_v,
input [0:31] rv_xu1_ex0_instr,
input [0:`ITAG_SIZE_ENC-1] rv_xu1_ex0_itag,
input rv_xu1_ex0_isstore,
input [1:1] rv_xu1_ex0_ucode,
input rv_xu1_ex0_t1_v,
input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t1_p,
input rv_xu1_ex0_t2_v,
input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t2_p,
input rv_xu1_ex0_t3_v,
input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t3_p,
input rv_xu1_ex0_s1_v,
input [0:2] rv_xu1_ex0_s3_t,
input [0:`THREADS-1] rv_xu1_ex0_spec_flush,
input [0:`THREADS-1] rv_xu1_ex1_spec_flush,
input [0:`THREADS-1] rv_xu1_ex2_spec_flush,
//-------------------------------------------------------------------
// Interface with Bypass Controller
//-------------------------------------------------------------------
input [1:11] rv_xu1_s1_fxu0_sel,
input [1:11] rv_xu1_s2_fxu0_sel,
input [2:11] rv_xu1_s3_fxu0_sel,
input [1:6] rv_xu1_s1_fxu1_sel,
input [1:6] rv_xu1_s2_fxu1_sel,
input [2:6] rv_xu1_s3_fxu1_sel,
input [4:8] rv_xu1_s1_lq_sel,
input [4:8] rv_xu1_s2_lq_sel,
input [4:8] rv_xu1_s3_lq_sel,
input [2:3] rv_xu1_s1_rel_sel,
input [2:3] rv_xu1_s2_rel_sel,
//-------------------------------------------------------------------
// Interface with LQ
//-------------------------------------------------------------------
output [0:`THREADS-1] xu1_lq_ex2_stq_val,
output [0:`ITAG_SIZE_ENC-1] xu1_lq_ex2_stq_itag,
output [1:4] xu1_lq_ex2_stq_size,
output xu1_lq_ex3_illeg_lswx,
output xu1_lq_ex3_strg_noop,
output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc1_cmp,
output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc2_cmp,
//-------------------------------------------------------------------
// Interface with IU
//-------------------------------------------------------------------
output [0:`THREADS-1] xu1_iu_execute_vld,
output [0:`ITAG_SIZE_ENC-1] xu1_iu_itag,
output [0:`THREADS-1] xu_iu_ucode_xer_val,
output [3:9] xu_iu_ucode_xer,
output xu1_rv_ex2_s1_abort,
output xu1_rv_ex2_s2_abort,
output xu1_rv_ex2_s3_abort,
//-------------------------------------------------------------------
// Bypass Inputs
//-------------------------------------------------------------------
// Regfile Data
input [64-`GPR_WIDTH:63] gpr_xu1_ex1_r1d,
input [64-`GPR_WIDTH:63] gpr_xu1_ex1_r2d,
input [0:9] xer_xu1_ex1_r3d,
input [0:3] cr_xu1_ex1_r3d,
// External Bypass
input xu0_xu1_ex2_abort,
input xu0_xu1_ex6_abort,
input lq_xu_ex5_abort,
input [64-`GPR_WIDTH:63] xu0_xu1_ex2_rt,
input [64-`GPR_WIDTH:63] xu0_xu1_ex3_rt,
input [64-`GPR_WIDTH:63] xu0_xu1_ex4_rt,
input [64-`GPR_WIDTH:63] xu0_xu1_ex5_rt,
input [64-`GPR_WIDTH:63] xu0_xu1_ex6_rt,
input [64-`GPR_WIDTH:63] xu0_xu1_ex7_rt,
input [64-`GPR_WIDTH:63] xu0_xu1_ex8_rt,
input [64-`GPR_WIDTH:63] xu0_xu1_ex6_lq_rt,
input [64-`GPR_WIDTH:63] xu0_xu1_ex7_lq_rt,
input [64-`GPR_WIDTH:63] xu0_xu1_ex8_lq_rt,
input [64-`GPR_WIDTH:63] lq_xu_ex5_rt,
input [64-`GPR_WIDTH:63] lq_xu_rel_rt,
input lq_xu_rel_act,
// CR
input [0:3] lq_xu_ex5_cr,
input [0:3] xu0_xu1_ex3_cr,
input [0:3] xu0_xu1_ex4_cr,
input [0:3] xu0_xu1_ex6_cr,
// XER
input [0:9] xu0_xu1_ex3_xer,
input [0:9] xu0_xu1_ex4_xer,
input [0:9] xu0_xu1_ex6_xer,
//-------------------------------------------------------------------
// Bypass Outputs
//-------------------------------------------------------------------
output xu1_xu0_ex3_act,
output xu1_xu0_ex2_abort,
output xu1_lq_ex3_abort,
output [64-`GPR_WIDTH:63] xu1_xu0_ex2_rt,
output [64-`GPR_WIDTH:63] xu1_xu0_ex3_rt,
output [64-`GPR_WIDTH:63] xu1_xu0_ex4_rt,
output [64-`GPR_WIDTH:63] xu1_xu0_ex5_rt,
output [64-`GPR_WIDTH:63] xu1_lq_ex3_rt,
// CR
output [0:3] xu1_xu0_ex3_cr,
// XER
output [0:9] xu1_xu0_ex3_xer,
//-------------------------------------------------------------------
// Interface with Regfiles
//-------------------------------------------------------------------
output xu1_gpr_ex3_we,
output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_gpr_ex3_wa,
output [64-`GPR_WIDTH:65+`GPR_WIDTH/8] xu1_gpr_ex3_wd,
output xu1_xer_ex3_we,
output [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] xu1_xer_ex3_wa,
output [0:9] xu1_xer_ex3_w0d,
output xu1_cr_ex3_we,
output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_cr_ex3_wa,
output [0:3] xu1_cr_ex3_w0d,
input [0:`THREADS-1] pc_xu_ram_active,
`ifndef THREADS1
input [64-`GPR_WIDTH:63] spr_dvc1_t1,
input [64-`GPR_WIDTH:63] spr_dvc2_t1,
`endif
input [64-`GPR_WIDTH:63] spr_dvc1_t0,
input [64-`GPR_WIDTH:63] spr_dvc2_t0,
// Debug
input [0:10] pc_xu_debug_mux_ctrls,
input [0:31] xu1_debug_bus_in,
output [0:31] xu1_debug_bus_out,
input [0:3] xu1_coretrace_ctrls_in,
output [0:3] xu1_coretrace_ctrls_out
);
//!! Bugspray Include: xu1_byp;
localparam scan_right = 3;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
// Signals
wire byp_dec_ex2_abort;
wire dec_byp_ex0_act;
wire [64-`GPR_WIDTH:63] dec_byp_ex1_imm;
wire [24:25] dec_byp_ex1_instr;
wire dec_byp_ex0_rs2_sel_imm;
wire dec_byp_ex0_rs1_sel_zero;
wire [0:`THREADS-1] dec_byp_ex2_tid;
wire [(64-`GPR_WIDTH)/8:7] dec_byp_ex2_dvc_mask;
wire dec_alu_ex1_act;
wire [0:31] dec_alu_ex1_instr;
wire dec_alu_ex1_sel_isel;
wire [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv;
wire [0:1] dec_alu_ex2_add_ci_sel;
wire dec_alu_ex1_sel_trap;
wire dec_alu_ex1_sel_cmpl;
wire dec_alu_ex1_sel_cmp;
wire dec_alu_ex1_msb_64b_sel;
wire dec_alu_ex1_xer_ov_en;
wire dec_alu_ex1_xer_ca_en;
wire [64-`GPR_WIDTH:63] alu_byp_ex2_add_rt;
wire [64-`GPR_WIDTH:63] alu_byp_ex3_rt;
wire [0:3] alu_byp_ex3_cr;
wire [0:9] alu_byp_ex3_xer;
wire [64-`GPR_WIDTH:63] byp_alu_ex2_rs1;
wire [64-`GPR_WIDTH:63] byp_alu_ex2_rs2;
wire byp_alu_ex2_cr_bit;
wire [0:9] byp_alu_ex2_xer;
wire [3:9] byp_dec_ex2_xer;
assign xu1_debug_bus_out = xu1_debug_bus_in;
assign xu1_coretrace_ctrls_out = xu1_coretrace_ctrls_in;
xu_alu alu(
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.d_mode_dc(d_mode_dc),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[0]),
.scan_out(sov[0]),
.dec_alu_ex1_act(dec_alu_ex1_act),
.dec_alu_ex1_instr(dec_alu_ex1_instr),
.dec_alu_ex1_sel_isel(dec_alu_ex1_sel_isel),
.dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv),
.dec_alu_ex2_add_ci_sel(dec_alu_ex2_add_ci_sel),
.dec_alu_ex1_sel_trap(dec_alu_ex1_sel_trap),
.dec_alu_ex1_sel_cmpl(dec_alu_ex1_sel_cmpl),
.dec_alu_ex1_sel_cmp(dec_alu_ex1_sel_cmp),
.dec_alu_ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel),
.dec_alu_ex1_xer_ov_en(dec_alu_ex1_xer_ov_en),
.dec_alu_ex1_xer_ca_en(dec_alu_ex1_xer_ca_en),
.byp_alu_ex2_rs1(byp_alu_ex2_rs1),
.byp_alu_ex2_rs2(byp_alu_ex2_rs2),
.byp_alu_ex2_cr_bit(byp_alu_ex2_cr_bit),
.byp_alu_ex2_xer(byp_alu_ex2_xer),
.alu_byp_ex2_add_rt(alu_byp_ex2_add_rt),
.alu_byp_ex3_rt(alu_byp_ex3_rt),
.alu_byp_ex3_cr(alu_byp_ex3_cr),
.alu_byp_ex3_xer(alu_byp_ex3_xer),
.alu_dec_ex3_trap_val()
);
xu1_byp byp(
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.d_mode_dc(d_mode_dc),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[1]),
.scan_out(sov[1]),
.dec_byp_ex0_act(dec_byp_ex0_act),
.byp_dec_ex2_abort(byp_dec_ex2_abort),
.xu0_xu1_ex3_act(xu0_xu1_ex3_act),
.lq_xu_ex5_act(lq_xu_ex5_act),
.dec_byp_ex1_imm(dec_byp_ex1_imm),
.dec_byp_ex1_instr(dec_byp_ex1_instr),
.dec_byp_ex0_rs2_sel_imm(dec_byp_ex0_rs2_sel_imm),
.dec_byp_ex0_rs1_sel_zero(dec_byp_ex0_rs1_sel_zero),
.dec_byp_ex2_tid(dec_byp_ex2_tid),
.dec_byp_ex2_dvc_mask(dec_byp_ex2_dvc_mask),
.rv_xu1_s1_v(rv_xu1_s1_v),
.rv_xu1_s2_v(rv_xu1_s2_v),
.rv_xu1_s3_v(rv_xu1_s3_v),
.rv_xu1_s1_fxu0_sel(rv_xu1_s1_fxu0_sel),
.rv_xu1_s2_fxu0_sel(rv_xu1_s2_fxu0_sel),
.rv_xu1_s3_fxu0_sel(rv_xu1_s3_fxu0_sel),
.rv_xu1_s1_fxu1_sel(rv_xu1_s1_fxu1_sel),
.rv_xu1_s2_fxu1_sel(rv_xu1_s2_fxu1_sel),
.rv_xu1_s3_fxu1_sel(rv_xu1_s3_fxu1_sel),
.rv_xu1_s1_lq_sel(rv_xu1_s1_lq_sel),
.rv_xu1_s2_lq_sel(rv_xu1_s2_lq_sel),
.rv_xu1_s3_lq_sel(rv_xu1_s3_lq_sel),
.rv_xu1_s1_rel_sel(rv_xu1_s1_rel_sel),
.rv_xu1_s2_rel_sel(rv_xu1_s2_rel_sel),
.gpr_xu1_ex1_r1d(gpr_xu1_ex1_r1d),
.gpr_xu1_ex1_r2d(gpr_xu1_ex1_r2d),
.xer_xu1_ex1_r3d(xer_xu1_ex1_r3d),
.cr_xu1_ex1_r3d(cr_xu1_ex1_r3d),
.xu0_xu1_ex2_abort(xu0_xu1_ex2_abort),
.xu0_xu1_ex6_abort(xu0_xu1_ex6_abort),
.xu0_xu1_ex2_rt(xu0_xu1_ex2_rt),
.xu0_xu1_ex3_rt(xu0_xu1_ex3_rt),
.xu0_xu1_ex4_rt(xu0_xu1_ex4_rt),
.xu0_xu1_ex5_rt(xu0_xu1_ex5_rt),
.xu0_xu1_ex6_rt(xu0_xu1_ex6_rt),
.xu0_xu1_ex7_rt(xu0_xu1_ex7_rt),
.xu0_xu1_ex8_rt(xu0_xu1_ex8_rt),
.xu0_xu1_ex6_lq_rt(xu0_xu1_ex6_lq_rt),
.xu0_xu1_ex7_lq_rt(xu0_xu1_ex7_lq_rt),
.xu0_xu1_ex8_lq_rt(xu0_xu1_ex8_lq_rt),
.lq_xu_ex5_abort(lq_xu_ex5_abort),
.lq_xu_ex5_rt(lq_xu_ex5_rt),
.lq_xu_rel_act(lq_xu_rel_act),
.lq_xu_rel_rt(lq_xu_rel_rt),
.lq_xu_ex5_cr(lq_xu_ex5_cr),
.xu0_xu1_ex3_cr(xu0_xu1_ex3_cr),
.xu0_xu1_ex4_cr(xu0_xu1_ex4_cr),
.xu0_xu1_ex6_cr(xu0_xu1_ex6_cr),
.xu0_xu1_ex3_xer(xu0_xu1_ex3_xer),
.xu0_xu1_ex4_xer(xu0_xu1_ex4_xer),
.xu0_xu1_ex6_xer(xu0_xu1_ex6_xer),
.alu_byp_ex2_add_rt(alu_byp_ex2_add_rt),
.alu_byp_ex3_rt(alu_byp_ex3_rt),
.alu_byp_ex3_cr(alu_byp_ex3_cr),
.alu_byp_ex3_xer(alu_byp_ex3_xer),
.xu1_xu0_ex2_abort(xu1_xu0_ex2_abort),
.xu1_lq_ex3_abort(xu1_lq_ex3_abort),
.xu1_xu0_ex2_rt(xu1_xu0_ex2_rt),
.xu1_xu0_ex3_rt(xu1_xu0_ex3_rt),
.xu1_xu0_ex4_rt(xu1_xu0_ex4_rt),
.xu1_xu0_ex5_rt(xu1_xu0_ex5_rt),
.xu1_lq_ex3_rt(xu1_lq_ex3_rt),
.xu1_pc_ram_data(xu1_pc_ram_data),
.xu1_xu0_ex3_cr(xu1_xu0_ex3_cr),
.xu1_xu0_ex3_xer(xu1_xu0_ex3_xer),
.byp_alu_ex2_rs1(byp_alu_ex2_rs1),
.byp_alu_ex2_rs2(byp_alu_ex2_rs2),
.byp_alu_ex2_cr_bit(byp_alu_ex2_cr_bit),
.byp_alu_ex2_xer(byp_alu_ex2_xer),
.byp_dec_ex2_xer(byp_dec_ex2_xer),
.xu_iu_ucode_xer(xu_iu_ucode_xer),
.xu1_rv_ex2_s1_abort(xu1_rv_ex2_s1_abort),
.xu1_rv_ex2_s2_abort(xu1_rv_ex2_s2_abort),
.xu1_rv_ex2_s3_abort(xu1_rv_ex2_s3_abort),
.xu1_gpr_ex3_wd(xu1_gpr_ex3_wd),
.xu1_xer_ex3_w0d(xu1_xer_ex3_w0d),
.xu1_cr_ex3_w0d(xu1_cr_ex3_w0d),
.xu1_lq_ex2_stq_dvc1_cmp(xu1_lq_ex2_stq_dvc1_cmp),
.xu1_lq_ex2_stq_dvc2_cmp(xu1_lq_ex2_stq_dvc2_cmp),
`ifndef THREADS1
.spr_dvc1_t1(spr_dvc1_t1),
.spr_dvc2_t1(spr_dvc2_t1),
`endif
.spr_dvc1_t0(spr_dvc1_t0),
.spr_dvc2_t0(spr_dvc2_t0)
);
xu1_dec dec(
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.d_mode_dc(d_mode_dc),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[2]),
.scan_out(sov[2]),
.spr_msr_cm(spr_msr_cm), // 0=> 0,
.cp_flush(cp_flush),
.rv_xu1_vld(rv_xu1_vld),
.rv_xu1_ex0_instr(rv_xu1_ex0_instr),
.rv_xu1_ex0_itag(rv_xu1_ex0_itag),
.rv_xu1_ex0_isstore(rv_xu1_ex0_isstore),
.rv_xu1_ex0_ucode(rv_xu1_ex0_ucode),
.rv_xu1_ex0_t1_v(rv_xu1_ex0_t1_v),
.rv_xu1_ex0_t1_p(rv_xu1_ex0_t1_p),
.rv_xu1_ex0_t2_v(rv_xu1_ex0_t2_v),
.rv_xu1_ex0_t2_p(rv_xu1_ex0_t2_p),
.rv_xu1_ex0_t3_v(rv_xu1_ex0_t3_v),
.rv_xu1_ex0_t3_p(rv_xu1_ex0_t3_p),
.rv_xu1_ex0_s1_v(rv_xu1_ex0_s1_v),
.rv_xu1_ex0_s3_t(rv_xu1_ex0_s3_t),
.rv_xu1_ex0_spec_flush(rv_xu1_ex0_spec_flush),
.rv_xu1_ex1_spec_flush(rv_xu1_ex1_spec_flush),
.rv_xu1_ex2_spec_flush(rv_xu1_ex2_spec_flush),
.xu1_lq_ex2_stq_val(xu1_lq_ex2_stq_val),
.xu1_lq_ex2_stq_itag(xu1_lq_ex2_stq_itag),
.xu1_lq_ex2_stq_size(xu1_lq_ex2_stq_size),
.xu1_lq_ex3_illeg_lswx(xu1_lq_ex3_illeg_lswx),
.xu1_lq_ex3_strg_noop(xu1_lq_ex3_strg_noop),
.xu1_iu_execute_vld(xu1_iu_execute_vld),
.xu1_iu_itag(xu1_iu_itag),
.xu_iu_ucode_xer_val(xu_iu_ucode_xer_val),
.xu1_pc_ram_done(xu1_pc_ram_done),
.dec_alu_ex1_act(dec_alu_ex1_act),
.dec_alu_ex1_instr(dec_alu_ex1_instr),
.dec_alu_ex1_sel_isel(dec_alu_ex1_sel_isel),
.dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv),
.dec_alu_ex2_add_ci_sel(dec_alu_ex2_add_ci_sel),
.dec_alu_ex1_sel_trap(dec_alu_ex1_sel_trap),
.dec_alu_ex1_sel_cmpl(dec_alu_ex1_sel_cmpl),
.dec_alu_ex1_sel_cmp(dec_alu_ex1_sel_cmp),
.dec_alu_ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel),
.dec_alu_ex1_xer_ov_en(dec_alu_ex1_xer_ov_en),
.dec_alu_ex1_xer_ca_en(dec_alu_ex1_xer_ca_en),
.xu1_xu0_ex3_act(xu1_xu0_ex3_act),
.dec_byp_ex0_act(dec_byp_ex0_act),
.byp_dec_ex2_abort(byp_dec_ex2_abort),
.dec_byp_ex1_imm(dec_byp_ex1_imm),
.dec_byp_ex1_instr(dec_byp_ex1_instr),
.dec_byp_ex0_rs2_sel_imm(dec_byp_ex0_rs2_sel_imm),
.dec_byp_ex0_rs1_sel_zero(dec_byp_ex0_rs1_sel_zero),
.dec_byp_ex2_tid(dec_byp_ex2_tid),
.dec_byp_ex2_dvc_mask(dec_byp_ex2_dvc_mask),
.byp_dec_ex2_xer(byp_dec_ex2_xer),
.xu1_gpr_ex3_we(xu1_gpr_ex3_we),
.xu1_gpr_ex3_wa(xu1_gpr_ex3_wa),
.xu1_xer_ex3_we(xu1_xer_ex3_we),
.xu1_xer_ex3_wa(xu1_xer_ex3_wa),
.xu1_cr_ex3_we(xu1_cr_ex3_we),
.xu1_cr_ex3_wa(xu1_cr_ex3_wa),
.pc_xu_ram_active(pc_xu_ram_active)
);
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
endmodule |
module fu_hc16pp_msb(
x,
y,
ci0,
ci0_b,
ci1,
ci1_b,
s0,
s1,
g16,
t16
);
input [0:15] x;
input [0:15] y;
input ci0;
input ci0_b;
input ci1;
input ci1_b;
output [0:15] s0;
output [0:15] s1;
output g16;
output t16;
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [1:15] g01_b;
wire [0:15] t01_b;
wire [0:15] p01_b;
wire [0:15] p01;
wire [0:7] g01od;
wire [0:7] t01od;
wire [0:7] g02ev;
wire [0:7] t02ev;
wire [1:7] g02ev_b;
wire [1:7] t02ev_b;
wire [1:7] g04ev;
wire [1:7] t04ev;
wire [1:7] g08ev_b;
wire [1:7] t08ev_b;
wire [1:7] g16ev;
wire [1:7] t16ev;
wire [1:15] c0_b;
wire [1:15] c1_b;
wire [0:15] s0_raw;
wire [0:15] s1_raw;
wire [0:15] s0_x_b;
wire [0:15] s0_y_b;
wire [0:15] s1_x_b;
wire [0:15] s1_y_b;
wire glb_g04_e01_b; //new // rep glb
wire glb_g04_e23_b;
wire glb_g04_e45_b;
wire glb_g04_e67_b;
wire glb_t04_e01_b; //new // rep glb
wire glb_t04_e23_b;
wire glb_t04_e45_b;
wire glb_t04_e67_b;
wire glb_g08_e03; //new // rep glb
wire glb_g08_e47;
wire glb_t08_e03;
wire glb_t08_e47;
wire glb_g16_e07_b; //new // rep glb
wire glb_t16_e07_b;
////#####################################
////## group 1
////#####################################
//hc00_g01: g01_b( 0) <= tiup ; --critical <=== different then MID
assign g01_b[1] = (~(x[1] & y[1])); //critical
assign g01_b[2] = (~(x[2] & y[2])); //critical
assign g01_b[3] = (~(x[3] & y[3])); //critical
assign g01_b[4] = (~(x[4] & y[4])); //critical
assign g01_b[5] = (~(x[5] & y[5])); //critical
assign g01_b[6] = (~(x[6] & y[6])); //critical
assign g01_b[7] = (~(x[7] & y[7])); //critical
assign g01_b[8] = (~(x[8] & y[8])); //critical
assign g01_b[9] = (~(x[9] & y[9])); //critical
assign g01_b[10] = (~(x[10] & y[10])); //critical
assign g01_b[11] = (~(x[11] & y[11])); //critical
assign g01_b[12] = (~(x[12] & y[12])); //critical
assign g01_b[13] = (~(x[13] & y[13])); //critical
assign g01_b[14] = (~(x[14] & y[14])); //critical
assign g01_b[15] = (~(x[15] & y[15])); //critical
assign t01_b[0] = (~(x[0] & y[0])); //critical <==== different then MID
assign t01_b[1] = (~(x[1] | y[1])); //critical
assign t01_b[2] = (~(x[2] | y[2])); //critical
assign t01_b[3] = (~(x[3] | y[3])); //critical
assign t01_b[4] = (~(x[4] | y[4])); //critical
assign t01_b[5] = (~(x[5] | y[5])); //critical
assign t01_b[6] = (~(x[6] | y[6])); //critical
assign t01_b[7] = (~(x[7] | y[7])); //critical
assign t01_b[8] = (~(x[8] | y[8])); //critical
assign t01_b[9] = (~(x[9] | y[9])); //critical
assign t01_b[10] = (~(x[10] | y[10])); //critical
assign t01_b[11] = (~(x[11] | y[11])); //critical
assign t01_b[12] = (~(x[12] | y[12])); //critical
assign t01_b[13] = (~(x[13] | y[13])); //critical
assign t01_b[14] = (~(x[14] | y[14])); //critical
assign t01_b[15] = (~(x[15] | y[15])); //critical
assign p01[0] = (~(x[0] ^ y[0])); //not critical <==== different than MID
assign p01[1] = (x[1] ^ y[1]); //not critical
assign p01[2] = (x[2] ^ y[2]); //not critical
assign p01[3] = (x[3] ^ y[3]); //not critical
assign p01[4] = (x[4] ^ y[4]); //not critical
assign p01[5] = (x[5] ^ y[5]); //not critical
assign p01[6] = (x[6] ^ y[6]); //not critical
assign p01[7] = (x[7] ^ y[7]); //not critical
assign p01[8] = (x[8] ^ y[8]); //not critical
assign p01[9] = (x[9] ^ y[9]); //not critical
assign p01[10] = (x[10] ^ y[10]); //not critical
assign p01[11] = (x[11] ^ y[11]); //not critical
assign p01[12] = (x[12] ^ y[12]); //not critical
assign p01[13] = (x[13] ^ y[13]); //not critical
assign p01[14] = (x[14] ^ y[14]); //not critical
assign p01[15] = (x[15] ^ y[15]); //not critical
assign p01_b[0] = (~(p01[0])); //not critical
assign p01_b[1] = (~(p01[1])); //not critical
assign p01_b[2] = (~(p01[2])); //not critical
assign p01_b[3] = (~(p01[3])); //not critical
assign p01_b[4] = (~(p01[4])); //not critical
assign p01_b[5] = (~(p01[5])); //not critical
assign p01_b[6] = (~(p01[6])); //not critical
assign p01_b[7] = (~(p01[7])); //not critical
assign p01_b[8] = (~(p01[8])); //not critical
assign p01_b[9] = (~(p01[9])); //not critical
assign p01_b[10] = (~(p01[10])); //not critical
assign p01_b[11] = (~(p01[11])); //not critical
assign p01_b[12] = (~(p01[12])); //not critical
assign p01_b[13] = (~(p01[13])); //not critical
assign p01_b[14] = (~(p01[14])); //not critical
assign p01_b[15] = (~(p01[15])); //not critical
assign g01od[0] = (~g01_b[1]);
assign g01od[1] = (~g01_b[3]);
assign g01od[2] = (~g01_b[5]);
assign g01od[3] = (~g01_b[7]);
assign g01od[4] = (~g01_b[9]);
assign g01od[5] = (~g01_b[11]);
assign g01od[6] = (~g01_b[13]);
assign g01od[7] = (~g01_b[15]);
assign t01od[0] = (~t01_b[1]);
assign t01od[1] = (~t01_b[3]);
assign t01od[2] = (~t01_b[5]);
assign t01od[3] = (~t01_b[7]);
assign t01od[4] = (~t01_b[9]);
assign t01od[5] = (~t01_b[11]);
assign t01od[6] = (~t01_b[13]);
assign t01od[7] = (~t01_b[15]);
////#####################################
////## group 2
////#####################################
assign g02ev[7] = (~((t01_b[14] | g01_b[15]) & g01_b[14])); //final
assign g02ev[6] = (~((t01_b[12] | g01_b[13]) & g01_b[12]));
assign g02ev[5] = (~((t01_b[10] | g01_b[11]) & g01_b[10]));
assign g02ev[4] = (~((t01_b[8] | g01_b[9]) & g01_b[8]));
assign g02ev[3] = (~((t01_b[6] | g01_b[7]) & g01_b[6]));
assign g02ev[2] = (~((t01_b[4] | g01_b[5]) & g01_b[4]));
assign g02ev[1] = (~((t01_b[2] | g01_b[3]) & g01_b[2]));
assign g02ev[0] = (~(t01_b[0] | g01_b[1])); // <==== different than MID
assign t02ev[7] = (~((t01_b[14] | t01_b[15]) & g01_b[14])); //final
assign t02ev[6] = (~(t01_b[12] | t01_b[13]));
assign t02ev[5] = (~(t01_b[10] | t01_b[11]));
assign t02ev[4] = (~(t01_b[8] | t01_b[9]));
assign t02ev[3] = (~(t01_b[6] | t01_b[7]));
assign t02ev[2] = (~(t01_b[4] | t01_b[5]));
assign t02ev[1] = (~(t01_b[2] | t01_b[3]));
assign t02ev[0] = (~(t01_b[0] | t01_b[1]));
assign g02ev_b[7] = (~(g02ev[7])); //new
assign g02ev_b[6] = (~(g02ev[6])); //new
assign g02ev_b[5] = (~(g02ev[5])); //new
assign g02ev_b[4] = (~(g02ev[4])); //new
assign g02ev_b[3] = (~(g02ev[3])); //new
assign g02ev_b[2] = (~(g02ev[2])); //new
assign g02ev_b[1] = (~(g02ev[1])); //new
assign t02ev_b[7] = (~(t02ev[7])); //new
assign t02ev_b[6] = (~(t02ev[6])); //new
assign t02ev_b[5] = (~(t02ev[5])); //new
assign t02ev_b[4] = (~(t02ev[4])); //new
assign t02ev_b[3] = (~(t02ev[3])); //new
assign t02ev_b[2] = (~(t02ev[2])); //new
assign t02ev_b[1] = (~(t02ev[1])); //new
////#####################################
////## replicating for global chain
////#####################################
assign glb_g04_e01_b = (~(g02ev[0] | (t02ev[0] & g02ev[1])));
assign glb_g04_e23_b = (~(g02ev[2] | (t02ev[2] & g02ev[3])));
assign glb_g04_e45_b = (~(g02ev[4] | (t02ev[4] & g02ev[5])));
assign glb_g04_e67_b = (~(g02ev[6] | (t02ev[6] & g02ev[7])));
assign glb_t04_e01_b = (~(t02ev[0] & t02ev[1]));
assign glb_t04_e23_b = (~(t02ev[2] & t02ev[3]));
assign glb_t04_e45_b = (~(t02ev[4] & t02ev[5]));
assign glb_t04_e67_b = (~(g02ev[6] | (t02ev[6] & t02ev[7])));
assign glb_g08_e03 = (~(glb_g04_e01_b & (glb_t04_e01_b | glb_g04_e23_b)));
assign glb_g08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_g04_e67_b)));
assign glb_t08_e03 = (~(glb_t04_e01_b | glb_t04_e23_b));
assign glb_t08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_t04_e67_b)));
assign glb_g16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_g08_e47)));
assign glb_t16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_t08_e47)));
assign g16 = (~(glb_g16_e07_b)); //output
assign t16 = (~(glb_t16_e07_b)); //output
////#####################################
////## group 4 // delayed for local chain ... reverse phase
////#####################################
assign g04ev[7] = (~(g02ev_b[7]));
assign g04ev[6] = (~(g02ev_b[6] & (t02ev_b[6] | g02ev_b[7]))); //final
assign g04ev[5] = (~(g02ev_b[5] & (t02ev_b[5] | g02ev_b[6])));
assign g04ev[4] = (~(g02ev_b[4] & (t02ev_b[4] | g02ev_b[5])));
assign g04ev[3] = (~(g02ev_b[3] & (t02ev_b[3] | g02ev_b[4])));
assign g04ev[2] = (~(g02ev_b[2] & (t02ev_b[2] | g02ev_b[3])));
assign g04ev[1] = (~(g02ev_b[1] & (t02ev_b[1] | g02ev_b[2])));
assign t04ev[7] = (~(t02ev_b[7]));
assign t04ev[6] = (~(g02ev_b[6] & (t02ev_b[6] | t02ev_b[7]))); //final
assign t04ev[5] = (~(t02ev_b[5] | t02ev_b[6]));
assign t04ev[4] = (~(t02ev_b[4] | t02ev_b[5]));
assign t04ev[3] = (~(t02ev_b[3] | t02ev_b[4]));
assign t04ev[2] = (~(t02ev_b[2] | t02ev_b[3]));
assign t04ev[1] = (~(t02ev_b[1] | t02ev_b[2]));
////#####################################
////## group 8
////#####################################
assign g08ev_b[7] = (~(g04ev[7]));
assign g08ev_b[6] = (~(g04ev[6]));
assign g08ev_b[5] = (~(g04ev[5] | (t04ev[5] & g04ev[7]))); //final
assign g08ev_b[4] = (~(g04ev[4] | (t04ev[4] & g04ev[6]))); //final
assign g08ev_b[3] = (~(g04ev[3] | (t04ev[3] & g04ev[5])));
assign g08ev_b[2] = (~(g04ev[2] | (t04ev[2] & g04ev[4])));
assign g08ev_b[1] = (~(g04ev[1] | (t04ev[1] & g04ev[3])));
assign t08ev_b[7] = (~(t04ev[7]));
assign t08ev_b[6] = (~(t04ev[6]));
assign t08ev_b[5] = (~(g04ev[5] | (t04ev[5] & t04ev[7]))); //final
assign t08ev_b[4] = (~(g04ev[4] | (t04ev[4] & t04ev[6]))); //final
assign t08ev_b[3] = (~(t04ev[3] & t04ev[5]));
assign t08ev_b[2] = (~(t04ev[2] & t04ev[4]));
assign t08ev_b[1] = (~(t04ev[1] & t04ev[3]));
////#####################################
////## group 16
////#####################################
assign g16ev[7] = (~(g08ev_b[7]));
assign g16ev[6] = (~(g08ev_b[6]));
assign g16ev[5] = (~(g08ev_b[5]));
assign g16ev[4] = (~(g08ev_b[4]));
assign g16ev[3] = (~(g08ev_b[3] & (t08ev_b[3] | g08ev_b[7]))); //final
assign g16ev[2] = (~(g08ev_b[2] & (t08ev_b[2] | g08ev_b[6]))); //final
assign g16ev[1] = (~(g08ev_b[1] & (t08ev_b[1] | g08ev_b[5]))); //final
assign t16ev[7] = (~(t08ev_b[7]));
assign t16ev[6] = (~(t08ev_b[6]));
assign t16ev[5] = (~(t08ev_b[5]));
assign t16ev[4] = (~(t08ev_b[4]));
assign t16ev[3] = (~(g08ev_b[3] & (t08ev_b[3] | t08ev_b[7]))); //final
assign t16ev[2] = (~(g08ev_b[2] & (t08ev_b[2] | t08ev_b[6]))); //final
assign t16ev[1] = (~(g08ev_b[1] & (t08ev_b[1] | t08ev_b[5]))); //final
////#####################################
////## group 16 delayed
////#####################################
assign c0_b[14] = (~(g16ev[7]));
assign c0_b[12] = (~(g16ev[6]));
assign c0_b[10] = (~(g16ev[5]));
assign c0_b[8] = (~(g16ev[4]));
assign c0_b[6] = (~(g16ev[3]));
assign c0_b[4] = (~(g16ev[2]));
assign c0_b[2] = (~(g16ev[1]));
assign c1_b[14] = (~(t16ev[7]));
assign c1_b[12] = (~(t16ev[6]));
assign c1_b[10] = (~(t16ev[5]));
assign c1_b[8] = (~(t16ev[4]));
assign c1_b[6] = (~(t16ev[3]));
assign c1_b[4] = (~(t16ev[2]));
assign c1_b[2] = (~(t16ev[1]));
assign c0_b[15] = (~(g01od[7]));
assign c0_b[13] = (~((t01od[6] & g16ev[7]) | g01od[6]));
assign c0_b[11] = (~((t01od[5] & g16ev[6]) | g01od[5]));
assign c0_b[9] = (~((t01od[4] & g16ev[5]) | g01od[4]));
assign c0_b[7] = (~((t01od[3] & g16ev[4]) | g01od[3]));
assign c0_b[5] = (~((t01od[2] & g16ev[3]) | g01od[2]));
assign c0_b[3] = (~((t01od[1] & g16ev[2]) | g01od[1]));
assign c0_b[1] = (~((t01od[0] & g16ev[1]) | g01od[0]));
assign c1_b[15] = (~(t01od[7]));
assign c1_b[13] = (~((t01od[6] & t16ev[7]) | g01od[6]));
assign c1_b[11] = (~((t01od[5] & t16ev[6]) | g01od[5]));
assign c1_b[9] = (~((t01od[4] & t16ev[5]) | g01od[4]));
assign c1_b[7] = (~((t01od[3] & t16ev[4]) | g01od[3]));
assign c1_b[5] = (~((t01od[2] & t16ev[3]) | g01od[2]));
assign c1_b[3] = (~((t01od[1] & t16ev[2]) | g01od[1]));
assign c1_b[1] = (~((t01od[0] & t16ev[1]) | g01od[0]));
////#####################################
////## sum before select
////#####################################
assign s0_raw[0] = (p01_b[0] ^ c0_b[1]);
assign s0_raw[1] = (p01_b[1] ^ c0_b[2]);
assign s0_raw[2] = (p01_b[2] ^ c0_b[3]);
assign s0_raw[3] = (p01_b[3] ^ c0_b[4]);
assign s0_raw[4] = (p01_b[4] ^ c0_b[5]);
assign s0_raw[5] = (p01_b[5] ^ c0_b[6]);
assign s0_raw[6] = (p01_b[6] ^ c0_b[7]);
assign s0_raw[7] = (p01_b[7] ^ c0_b[8]);
assign s0_raw[8] = (p01_b[8] ^ c0_b[9]);
assign s0_raw[9] = (p01_b[9] ^ c0_b[10]);
assign s0_raw[10] = (p01_b[10] ^ c0_b[11]);
assign s0_raw[11] = (p01_b[11] ^ c0_b[12]);
assign s0_raw[12] = (p01_b[12] ^ c0_b[13]);
assign s0_raw[13] = (p01_b[13] ^ c0_b[14]);
assign s0_raw[14] = (p01_b[14] ^ c0_b[15]);
assign s0_raw[15] = (~p01_b[15]);
assign s1_raw[0] = (p01_b[0] ^ c1_b[1]);
assign s1_raw[1] = (p01_b[1] ^ c1_b[2]);
assign s1_raw[2] = (p01_b[2] ^ c1_b[3]);
assign s1_raw[3] = (p01_b[3] ^ c1_b[4]);
assign s1_raw[4] = (p01_b[4] ^ c1_b[5]);
assign s1_raw[5] = (p01_b[5] ^ c1_b[6]);
assign s1_raw[6] = (p01_b[6] ^ c1_b[7]);
assign s1_raw[7] = (p01_b[7] ^ c1_b[8]);
assign s1_raw[8] = (p01_b[8] ^ c1_b[9]);
assign s1_raw[9] = (p01_b[9] ^ c1_b[10]);
assign s1_raw[10] = (p01_b[10] ^ c1_b[11]);
assign s1_raw[11] = (p01_b[11] ^ c1_b[12]);
assign s1_raw[12] = (p01_b[12] ^ c1_b[13]);
assign s1_raw[13] = (p01_b[13] ^ c1_b[14]);
assign s1_raw[14] = (p01_b[14] ^ c1_b[15]);
assign s1_raw[15] = (~s0_raw[15]);
////#####################################
////## sum after select
////#####################################
assign s0_x_b[0] = (~(s0_raw[0] & ci0_b));
assign s0_y_b[0] = (~(s1_raw[0] & ci0));
assign s1_x_b[0] = (~(s0_raw[0] & ci1_b));
assign s1_y_b[0] = (~(s1_raw[0] & ci1));
assign s0[0] = (~(s0_x_b[0] & s0_y_b[0]));
assign s1[0] = (~(s1_x_b[0] & s1_y_b[0]));
assign s0_x_b[1] = (~(s0_raw[1] & ci0_b));
assign s0_y_b[1] = (~(s1_raw[1] & ci0));
assign s1_x_b[1] = (~(s0_raw[1] & ci1_b));
assign s1_y_b[1] = (~(s1_raw[1] & ci1));
assign s0[1] = (~(s0_x_b[1] & s0_y_b[1]));
assign s1[1] = (~(s1_x_b[1] & s1_y_b[1]));
assign s0_x_b[2] = (~(s0_raw[2] & ci0_b));
assign s0_y_b[2] = (~(s1_raw[2] & ci0));
assign s1_x_b[2] = (~(s0_raw[2] & ci1_b));
assign s1_y_b[2] = (~(s1_raw[2] & ci1));
assign s0[2] = (~(s0_x_b[2] & s0_y_b[2]));
assign s1[2] = (~(s1_x_b[2] & s1_y_b[2]));
assign s0_x_b[3] = (~(s0_raw[3] & ci0_b));
assign s0_y_b[3] = (~(s1_raw[3] & ci0));
assign s1_x_b[3] = (~(s0_raw[3] & ci1_b));
assign s1_y_b[3] = (~(s1_raw[3] & ci1));
assign s0[3] = (~(s0_x_b[3] & s0_y_b[3]));
assign s1[3] = (~(s1_x_b[3] & s1_y_b[3]));
assign s0_x_b[4] = (~(s0_raw[4] & ci0_b));
assign s0_y_b[4] = (~(s1_raw[4] & ci0));
assign s1_x_b[4] = (~(s0_raw[4] & ci1_b));
assign s1_y_b[4] = (~(s1_raw[4] & ci1));
assign s0[4] = (~(s0_x_b[4] & s0_y_b[4]));
assign s1[4] = (~(s1_x_b[4] & s1_y_b[4]));
assign s0_x_b[5] = (~(s0_raw[5] & ci0_b));
assign s0_y_b[5] = (~(s1_raw[5] & ci0));
assign s1_x_b[5] = (~(s0_raw[5] & ci1_b));
assign s1_y_b[5] = (~(s1_raw[5] & ci1));
assign s0[5] = (~(s0_x_b[5] & s0_y_b[5]));
assign s1[5] = (~(s1_x_b[5] & s1_y_b[5]));
assign s0_x_b[6] = (~(s0_raw[6] & ci0_b));
assign s0_y_b[6] = (~(s1_raw[6] & ci0));
assign s1_x_b[6] = (~(s0_raw[6] & ci1_b));
assign s1_y_b[6] = (~(s1_raw[6] & ci1));
assign s0[6] = (~(s0_x_b[6] & s0_y_b[6]));
assign s1[6] = (~(s1_x_b[6] & s1_y_b[6]));
assign s0_x_b[7] = (~(s0_raw[7] & ci0_b));
assign s0_y_b[7] = (~(s1_raw[7] & ci0));
assign s1_x_b[7] = (~(s0_raw[7] & ci1_b));
assign s1_y_b[7] = (~(s1_raw[7] & ci1));
assign s0[7] = (~(s0_x_b[7] & s0_y_b[7]));
assign s1[7] = (~(s1_x_b[7] & s1_y_b[7]));
assign s0_x_b[8] = (~(s0_raw[8] & ci0_b));
assign s0_y_b[8] = (~(s1_raw[8] & ci0));
assign s1_x_b[8] = (~(s0_raw[8] & ci1_b));
assign s1_y_b[8] = (~(s1_raw[8] & ci1));
assign s0[8] = (~(s0_x_b[8] & s0_y_b[8]));
assign s1[8] = (~(s1_x_b[8] & s1_y_b[8]));
assign s0_x_b[9] = (~(s0_raw[9] & ci0_b));
assign s0_y_b[9] = (~(s1_raw[9] & ci0));
assign s1_x_b[9] = (~(s0_raw[9] & ci1_b));
assign s1_y_b[9] = (~(s1_raw[9] & ci1));
assign s0[9] = (~(s0_x_b[9] & s0_y_b[9]));
assign s1[9] = (~(s1_x_b[9] & s1_y_b[9]));
assign s0_x_b[10] = (~(s0_raw[10] & ci0_b));
assign s0_y_b[10] = (~(s1_raw[10] & ci0));
assign s1_x_b[10] = (~(s0_raw[10] & ci1_b));
assign s1_y_b[10] = (~(s1_raw[10] & ci1));
assign s0[10] = (~(s0_x_b[10] & s0_y_b[10]));
assign s1[10] = (~(s1_x_b[10] & s1_y_b[10]));
assign s0_x_b[11] = (~(s0_raw[11] & ci0_b));
assign s0_y_b[11] = (~(s1_raw[11] & ci0));
assign s1_x_b[11] = (~(s0_raw[11] & ci1_b));
assign s1_y_b[11] = (~(s1_raw[11] & ci1));
assign s0[11] = (~(s0_x_b[11] & s0_y_b[11]));
assign s1[11] = (~(s1_x_b[11] & s1_y_b[11]));
assign s0_x_b[12] = (~(s0_raw[12] & ci0_b));
assign s0_y_b[12] = (~(s1_raw[12] & ci0));
assign s1_x_b[12] = (~(s0_raw[12] & ci1_b));
assign s1_y_b[12] = (~(s1_raw[12] & ci1));
assign s0[12] = (~(s0_x_b[12] & s0_y_b[12]));
assign s1[12] = (~(s1_x_b[12] & s1_y_b[12]));
assign s0_x_b[13] = (~(s0_raw[13] & ci0_b));
assign s0_y_b[13] = (~(s1_raw[13] & ci0));
assign s1_x_b[13] = (~(s0_raw[13] & ci1_b));
assign s1_y_b[13] = (~(s1_raw[13] & ci1));
assign s0[13] = (~(s0_x_b[13] & s0_y_b[13]));
assign s1[13] = (~(s1_x_b[13] & s1_y_b[13]));
assign s0_x_b[14] = (~(s0_raw[14] & ci0_b));
assign s0_y_b[14] = (~(s1_raw[14] & ci0));
assign s1_x_b[14] = (~(s0_raw[14] & ci1_b));
assign s1_y_b[14] = (~(s1_raw[14] & ci1));
assign s0[14] = (~(s0_x_b[14] & s0_y_b[14]));
assign s1[14] = (~(s1_x_b[14] & s1_y_b[14]));
assign s0_x_b[15] = (~(s0_raw[15] & ci0_b));
assign s0_y_b[15] = (~(s1_raw[15] & ci0));
assign s1_x_b[15] = (~(s0_raw[15] & ci1_b));
assign s1_y_b[15] = (~(s1_raw[15] & ci1));
assign s0[15] = (~(s0_x_b[15] & s0_y_b[15]));
assign s1[15] = (~(s1_x_b[15] & s1_y_b[15]));
endmodule |
module fu_gst_add11(
a_b,
b_b,
s0
);
`include "tri_a2o.vh"
input [0:10] a_b; // inverted adder input
input [0:10] b_b; // inverted adder input
output [0:10] s0;
(* NO_MODIFICATION="TRUE" *)
wire [0:10] p1;
(* NO_MODIFICATION="TRUE" *)
wire [1:10] g1;
(* NO_MODIFICATION="TRUE" *)
wire [1:9] t1;
(* NO_MODIFICATION="TRUE" *)
wire [1:10] g2_b;
(* NO_MODIFICATION="TRUE" *)
wire [1:10] g4;
(* NO_MODIFICATION="TRUE" *)
wire [1:10] g8_b;
(* NO_MODIFICATION="TRUE" *)
wire [1:10] c16;
(* NO_MODIFICATION="TRUE" *)
wire [1:8] t2_b;
(* NO_MODIFICATION="TRUE" *)
wire [1:6] t4;
(* NO_MODIFICATION="TRUE" *)
wire [1:2] t8_b;
assign p1[0:10] = (a_b[0:10] ^ b_b[0:10]);
assign g1[1:10] = (~(a_b[1:10] | b_b[1:10]));
assign t1[1:9] = (~(a_b[1:9] & b_b[1:9]));
//---------------------------------------------
// carry chain ---
//---------------------------------------------
assign g2_b[1] = (~(g1[1] | (t1[1] & g1[2])));
assign g2_b[2] = (~(g1[2] | (t1[2] & g1[3])));
assign g2_b[3] = (~(g1[3] | (t1[3] & g1[4])));
assign g2_b[4] = (~(g1[4] | (t1[4] & g1[5])));
assign g2_b[5] = (~(g1[5] | (t1[5] & g1[6])));
assign g2_b[6] = (~(g1[6] | (t1[6] & g1[7])));
assign g2_b[7] = (~(g1[7] | (t1[7] & g1[8])));
assign g2_b[8] = (~(g1[8] | (t1[8] & g1[9])));
assign g2_b[9] = (~(g1[9] | (t1[9] & g1[10]))); //done
assign g2_b[10] = (~(g1[10]));
assign t2_b[1] = (~(t1[1] & t1[2]));
assign t2_b[2] = (~(t1[2] & t1[3]));
assign t2_b[3] = (~(t1[3] & t1[4]));
assign t2_b[4] = (~(t1[4] & t1[5]));
assign t2_b[5] = (~(t1[5] & t1[6]));
assign t2_b[6] = (~(t1[6] & t1[7]));
assign t2_b[7] = (~(t1[7] & t1[8]));
assign t2_b[8] = (~(t1[8] & t1[9]));
assign g4[1] = (~(g2_b[1] & (t2_b[1] | g2_b[3])));
assign g4[2] = (~(g2_b[2] & (t2_b[2] | g2_b[4])));
assign g4[3] = (~(g2_b[3] & (t2_b[3] | g2_b[5])));
assign g4[4] = (~(g2_b[4] & (t2_b[4] | g2_b[6])));
assign g4[5] = (~(g2_b[5] & (t2_b[5] | g2_b[7])));
assign g4[6] = (~(g2_b[6] & (t2_b[6] | g2_b[8])));
assign g4[7] = (~(g2_b[7] & (t2_b[7] | g2_b[9]))); //done
assign g4[8] = (~(g2_b[8] & (t2_b[8] | g2_b[10]))); //done
assign g4[9] = (~(g2_b[9]));
assign g4[10] = (~(g2_b[10]));
assign t4[1] = (~(t2_b[1] | t2_b[3]));
assign t4[2] = (~(t2_b[2] | t2_b[4]));
assign t4[3] = (~(t2_b[3] | t2_b[5]));
assign t4[4] = (~(t2_b[4] | t2_b[6]));
assign t4[5] = (~(t2_b[5] | t2_b[7]));
assign t4[6] = (~(t2_b[6] | t2_b[8]));
assign g8_b[1] = (~(g4[1] | (t4[1] & g4[5])));
assign g8_b[2] = (~(g4[2] | (t4[2] & g4[6])));
assign g8_b[3] = (~(g4[3] | (t4[3] & g4[7]))); //done
assign g8_b[4] = (~(g4[4] | (t4[4] & g4[8]))); //done
assign g8_b[5] = (~(g4[5] | (t4[5] & g4[9]))); //done
assign g8_b[6] = (~(g4[6] | (t4[6] & g4[10]))); //done
assign g8_b[7] = (~(g4[7]));
assign g8_b[8] = (~(g4[8]));
assign g8_b[9] = (~(g4[9]));
assign g8_b[10] = (~(g4[10]));
assign t8_b[1] = (~(t4[1] & t4[5]));
assign t8_b[2] = (~(t4[2] & t4[6]));
assign c16[1] = (~(g8_b[1] & (t8_b[1] | g8_b[9]))); //done
assign c16[2] = (~(g8_b[2] & (t8_b[2] | g8_b[10]))); //done
assign c16[3] = (~(g8_b[3]));
assign c16[4] = (~(g8_b[4]));
assign c16[5] = (~(g8_b[5]));
assign c16[6] = (~(g8_b[6]));
assign c16[7] = (~(g8_b[7]));
assign c16[8] = (~(g8_b[8]));
assign c16[9] = (~(g8_b[9]));
assign c16[10] = (~(g8_b[10]));
//---------------------------------------------
// final result ---
//---------------------------------------------
assign s0[0:9] = p1[0:9] ^ c16[1:10];
assign s0[10] = p1[10];
endmodule |
module mmq_perf(
inout vdd,
inout gnd,
(* pin_data ="PIN_FUNCTION=/G_CLK/" *)
input [0:`NCLK_WIDTH-1] nclk,
input pc_func_sl_thold_2,
input pc_func_slp_nsl_thold_2,
input pc_sg_2,
input pc_fce_2,
input tc_ac_ccflush_dc,
input lcb_clkoff_dc_b,
input lcb_act_dis_dc,
input lcb_d_mode_dc,
input lcb_delay_lclkr_dc,
input lcb_mpw1_dc_b,
input lcb_mpw2_dc_b,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out,
input [0:`MM_THREADS-1] cp_flush_p1,
input [0:`THDID_WIDTH-1] xu_mm_msr_gs,
input [0:`THDID_WIDTH-1] xu_mm_msr_pr,
input xu_mm_ccr2_notlb_b,
// count event inputs
input [0:`THDID_WIDTH-1] lq_mm_perf_dtlb,
input [0:`THDID_WIDTH-1] iu_mm_perf_itlb,
input lq_mm_derat_req_nonspec,
input iu_mm_ierat_req_nonspec,
input [0:9] tlb_cmp_perf_event_t0,
input [0:9] tlb_cmp_perf_event_t1,
input [0:1] tlb_cmp_perf_state, // gs & pr
input tlb_cmp_perf_miss_direct,
input tlb_cmp_perf_hit_direct,
input tlb_cmp_perf_hit_indirect,
input tlb_cmp_perf_hit_first_page,
input tlb_cmp_perf_ptereload,
input tlb_cmp_perf_ptereload_noexcep,
input tlb_cmp_perf_lrat_request,
input tlb_cmp_perf_lrat_miss,
input tlb_cmp_perf_pt_fault,
input tlb_cmp_perf_pt_inelig,
input tlb_ctl_perf_tlbwec_resv,
input tlb_ctl_perf_tlbwec_noresv,
input [0:`THDID_WIDTH-1] derat_req0_thdid,
input derat_req0_valid,
input derat_req0_nonspec,
input [0:`THDID_WIDTH-1] derat_req1_thdid,
input derat_req1_valid,
input derat_req1_nonspec,
input [0:`THDID_WIDTH-1] derat_req2_thdid,
input derat_req2_valid,
input derat_req2_nonspec,
input [0:`THDID_WIDTH-1] derat_req3_thdid,
input derat_req3_valid,
input derat_req3_nonspec,
input [0:`THDID_WIDTH-1] ierat_req0_thdid,
input ierat_req0_valid,
input ierat_req0_nonspec,
input [0:`THDID_WIDTH-1] ierat_req1_thdid,
input ierat_req1_valid,
input ierat_req1_nonspec,
input [0:`THDID_WIDTH-1] ierat_req2_thdid,
input ierat_req2_valid,
input ierat_req2_nonspec,
input [0:`THDID_WIDTH-1] ierat_req3_thdid,
input ierat_req3_valid,
input ierat_req3_nonspec,
input ierat_req_taken,
input derat_req_taken,
input [0:`THDID_WIDTH-1] tlb_tag0_thdid,
input [0:1] tlb_tag0_type, // derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
input tlb_tag0_nonspec,
input tlb_tag4_nonspec,
input tlb_seq_idle,
input inval_perf_tlbilx,
input inval_perf_tlbivax,
input inval_perf_tlbivax_snoop,
input inval_perf_tlb_flush,
input htw_req0_valid,
input [0:`THDID_WIDTH-1] htw_req0_thdid,
input [0:1] htw_req0_type,
input htw_req1_valid,
input [0:`THDID_WIDTH-1] htw_req1_thdid,
input [0:1] htw_req1_type,
input htw_req2_valid,
input [0:`THDID_WIDTH-1] htw_req2_thdid,
input [0:1] htw_req2_type,
input htw_req3_valid,
input [0:`THDID_WIDTH-1] htw_req3_thdid,
input [0:1] htw_req3_type,
`ifdef WAIT_UPDATES
input [0:`MM_THREADS+5-1] cp_mm_perf_except_taken_q,
// 0:1 - thdid/val
// 2 - I=0/D=1
// 3 - TLB miss
// 4 - Storage int (TLBI/PTfault)
// 5 - LRAT miss
// 6 - Mcheck
`endif
// control inputs
input [0:`MESR1_WIDTH*`THREADS-1] mmq_spr_event_mux_ctrls,
input [0:2] pc_mm_event_count_mode, // 0=count events in problem state,1=sup,2=hypv
input rp_mm_event_bus_enable_q, // act for perf related latches from repower
input [0:`PERF_EVENT_WIDTH*`THREADS-1] mm_event_bus_in,
output [0:`PERF_EVENT_WIDTH*`THREADS-1] mm_event_bus_out
);
parameter rp_mm_event_bus_enable_offset = 0;
parameter mmq_spr_event_mux_ctrls_offset = rp_mm_event_bus_enable_offset + 1;
parameter pc_mm_event_count_mode_offset = mmq_spr_event_mux_ctrls_offset + `MESR1_WIDTH*`THREADS;
parameter xu_mm_msr_gs_offset = pc_mm_event_count_mode_offset + 3;
parameter xu_mm_msr_pr_offset = xu_mm_msr_gs_offset + `THDID_WIDTH;
parameter event_bus_out_offset = xu_mm_msr_pr_offset + `THDID_WIDTH;
parameter scan_right = event_bus_out_offset + `PERF_EVENT_WIDTH*`THREADS - 1;
wire [0:`PERF_EVENT_WIDTH*`THREADS-1] event_bus_out_d, event_bus_out_q;
wire rp_mm_event_bus_enable_int_q;
wire [0:`MESR1_WIDTH*`THREADS-1] mmq_spr_event_mux_ctrls_q;
wire [0:2] pc_mm_event_count_mode_q; // 0=count events in problem state,1=sup,2=hypv
wire [0:23] mm_perf_event_t0_d, mm_perf_event_t0_q; // t0 threadwise events
wire [0:23] mm_perf_event_t1_d, mm_perf_event_t1_q; // t1 threadwise events
wire [0:31] mm_perf_event_core_level_d, mm_perf_event_core_level_q; // thread independent events
wire [0:`THDID_WIDTH-1] xu_mm_msr_gs_q;
wire [0:`THDID_WIDTH-1] xu_mm_msr_pr_q;
wire [0:`THDID_WIDTH] event_en;
wire [0:`PERF_MUX_WIDTH-1] unit_t0_events_in;
`ifndef THREADS1
wire [0:`PERF_MUX_WIDTH-1] unit_t1_events_in;
`endif
wire [0:scan_right] siv;
wire [0:scan_right] sov;
wire tidn;
wire tiup;
wire pc_func_sl_thold_1;
wire pc_func_sl_thold_0;
wire pc_func_sl_thold_0_b;
wire pc_func_slp_nsl_thold_1;
wire pc_func_slp_nsl_thold_0;
wire pc_func_slp_nsl_thold_0_b;
wire pc_func_slp_nsl_force;
wire pc_sg_1;
wire pc_sg_0;
wire pc_fce_1;
wire pc_fce_0;
wire force_t;
wire [0:79] tri_regk_unused_scan;
//---------------------------------------------------------------------
// Logic
//---------------------------------------------------------------------
assign tidn = 1'b0;
assign tiup = 1'b1;
assign event_en[0:3] = (xu_mm_msr_pr_q[0:3] & {4{pc_mm_event_count_mode_q[0]}}) |
// User problem state
((~xu_mm_msr_pr_q[0:3]) & xu_mm_msr_gs_q[0:3] & {4{pc_mm_event_count_mode_q[1]}}) |
// Guest Supervisor
((~xu_mm_msr_pr_q[0:3]) & (~xu_mm_msr_gs_q[0:3]) & {4{pc_mm_event_count_mode_q[2]}});
// Hypervisor
//tlb_cmp_perf_state: 0 =gs, 1=pr
assign event_en[4] = (tlb_cmp_perf_state[1] & pc_mm_event_count_mode_q[0]) |
// User problem state
(tlb_cmp_perf_state[0] & (~tlb_cmp_perf_state[1]) & pc_mm_event_count_mode_q[1]) |
// Guest Supervisor
((~tlb_cmp_perf_state[0]) & (~tlb_cmp_perf_state[1]) & pc_mm_event_count_mode_q[2]);
// Hypervisor
//--------------------------------------------------
// t* threadwise event list
//--------------------------------------------------
// 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch)
// 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch)
// 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception)
// 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch)
// 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi)
// 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op)
// 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op)
// 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception)
// 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op)
// 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi)
// 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency)
// 11 DERAT miss (or latency), edge (or level) (total derat misses or latency)
// 12 TLB hit direct entry (instr.) (ind=0 entry hit for NONSPECULATIVE fetch)
// 13 TLB miss direct entry (instr.) (ind=0 entry missed for NONSPECULATIVE fetch)
// 14 TLB hit direct entry (data) (ind=0 entry hit for NONSPECULATIVE load/store/cache op)
// 15 TLB miss direct entry (data) (ind=0 entry miss for NONSPECULATIVE load/store/cache op)
// 16 IERAT miss (or latency), edge (or level) (total NONSPECULATIVE ierat misses or latency)
// 17 DERAT miss (or latency), edge (or level) (total NONSPECULATIVE derat misses or latency)
// 18 TLB hit direct entry (instr.) (ind=0 entry hit for SPECULATIVE fetch)
// 19 TLB miss direct entry (instr.) (ind=0 entry missed for SPECULATIVE fetch)
// 20 TLB hit direct entry (data) (ind=0 entry hit for SPECULATIVE load/store/cache op)
// 21 TLB miss direct entry (data) (ind=0 entry miss for SPECULATIVE load/store/cache op)
// 22 IERAT miss (or latency), edge (or level) (total SPECULATIVE ierat misses or latency)
// 23 DERAT miss (or latency), edge (or level) (total SPECULATIVE derat misses or latency)
//--------------------------------------------------
// core single event list
//--------------------------------------------------
// 0 IERAT miss total (part of direct entry search total)
// 1 DERAT miss total (part of direct entry search total)
// 2 TLB miss direct entry total (total TLB ind=0 misses)
// 3 TLB hit direct entry first page size
//--------------------------------------------------
// 4 TLB indirect entry hits total (=page table searches)
// 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss)
// 6 LRAT translation request total (for GS=1 tlbwe and ptereload)
// 7 LRAT misses total (for GS=1 tlbwe and ptereload)
//--------------------------------------------------
// 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi)
// 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi)
// 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match)
// 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match)
//--------------------------------------------------
// 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total)
// 13 tlbivax invalidations sourced total (sourced tlbivax on this core total)
// 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care)
// 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards)
//--------------------------------------------------
// 16 IERAT NONSPECULATIVE miss total (part of direct entry search total)
// 17 DERAT NONSPECULATIVE miss total (part of direct entry search total)
// 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses)
// 19 TLB NONSPECULATIVE hit direct entry first page size
//--------------------------------------------------
// 20 IERAT SPECULATIVE miss total (part of direct entry search total)
// 21 DERAT SPECULATIVE miss total (part of direct entry search total)
// 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses)
// 23 TLB SPECULATIVE hit direct entry first page size
//--------------------------------------------------
// 24 ERAT miss total (TLB direct entry search total for both I and D sides)
// 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides)
// 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides)
// 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides)
// 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides)
// 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides)
// 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1)
// 31 Raw Total ERAT misses, either mode
//--------------------------------------------------
// t* threadwise event list
//--------------------------------------------------
// 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch)
// 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch)
// 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception)
// 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch)
// 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi)
// 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op)
// 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op)
// 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception)
// 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op)
// 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi)
assign mm_perf_event_t0_d[0:9] = tlb_cmp_perf_event_t0[0:9] & {10{event_en[0]}};
// 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
assign mm_perf_event_t0_d[10] = (((ierat_req0_valid & ierat_req0_thdid[0]) |
(ierat_req1_valid & ierat_req1_thdid[0]) |
(ierat_req2_valid & ierat_req2_thdid[0]) |
(ierat_req3_valid & ierat_req3_thdid[0]) |
// ierat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[0]) |
// searching tlb for direct entry, or ptereload of instr
(htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[0]) |
(htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[0]) |
(htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[0]) |
(htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) |
// htw servicing miss of instr
(iu_mm_perf_itlb[0] & (~xu_mm_ccr2_notlb_b));
// 11 DERAT miss (or latency), edge (or level) (total derat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
assign mm_perf_event_t0_d[11] = (((derat_req0_valid & derat_req0_thdid[0]) |
(derat_req1_valid & derat_req1_thdid[0]) |
(derat_req2_valid & derat_req2_thdid[0]) |
(derat_req3_valid & derat_req3_thdid[0]) |
// derat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[0]) |
// searching tlb for direct entry, or ptereload of data
(htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[0]) |
(htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[0]) |
(htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[0]) |
(htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) |
// htw servicing miss of data
(lq_mm_perf_dtlb[0] & (~xu_mm_ccr2_notlb_b));
// 12 TLB hit direct entry (instr.) (ind=0 entry hit for NONSPECULATIVE fetch)
assign mm_perf_event_t0_d[12] = tlb_cmp_perf_event_t0[0] & event_en[0] & tlb_tag4_nonspec;
// 13 TLB miss direct entry (instr.) (ind=0 entry missed for NONSPECULATIVE fetch)
assign mm_perf_event_t0_d[13] = tlb_cmp_perf_event_t0[1] & event_en[0] & tlb_tag4_nonspec;
// 14 TLB hit direct entry (data) (ind=0 entry hit for NONSPECULATIVE load/store/cache op)
assign mm_perf_event_t0_d[14] = tlb_cmp_perf_event_t0[5] & event_en[0] & tlb_tag4_nonspec;
// 15 TLB miss direct entry (data) (ind=0 entry miss for NONSPECULATIVE load/store/cache op)
assign mm_perf_event_t0_d[15] = tlb_cmp_perf_event_t0[6] & event_en[0] & tlb_tag4_nonspec;
// 16 IERAT miss (or latency), edge (or level) (total NONSPECULATIVE ierat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
assign mm_perf_event_t0_d[16] = (((ierat_req0_valid & ierat_req0_nonspec & ierat_req0_thdid[0]) |
(ierat_req1_valid & ierat_req1_nonspec & ierat_req1_thdid[0]) |
(ierat_req2_valid & ierat_req2_nonspec & ierat_req2_thdid[0]) |
(ierat_req3_valid & ierat_req3_nonspec & ierat_req3_thdid[0]) |
// ierat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[0] & tlb_tag0_nonspec) |
// searching tlb for direct entry, or ptereload of instr
(htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[0]) |
(htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[0]) |
(htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[0]) |
(htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) |
// htw servicing miss of instr
(iu_mm_perf_itlb[0] & iu_mm_ierat_req_nonspec & (~xu_mm_ccr2_notlb_b));
// 17 DERAT miss (or latency), edge (or level) (total NONSPECULATIVE derat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
assign mm_perf_event_t0_d[17] = (((derat_req0_valid & derat_req0_nonspec & derat_req0_thdid[0]) |
(derat_req1_valid & derat_req1_nonspec & derat_req1_thdid[0]) |
(derat_req2_valid & derat_req2_nonspec & derat_req2_thdid[0]) |
(derat_req3_valid & derat_req3_nonspec & derat_req3_thdid[0]) |
// derat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[0] & tlb_tag0_nonspec) |
// searching tlb for direct entry, or ptereload of data
(htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[0]) |
(htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[0]) |
(htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[0]) |
(htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) |
// htw servicing miss of data
(lq_mm_perf_dtlb[0] & lq_mm_derat_req_nonspec & (~xu_mm_ccr2_notlb_b));
// 18 TLB hit direct entry (instr.) (ind=0 entry hit for SPECULATIVE fetch)
assign mm_perf_event_t0_d[18] = tlb_cmp_perf_event_t0[0] & event_en[0] & ~tlb_tag4_nonspec;
// 19 TLB miss direct entry (instr.) (ind=0 entry missed for SPECULATIVE fetch)
assign mm_perf_event_t0_d[19] = tlb_cmp_perf_event_t0[1] & event_en[0] & ~tlb_tag4_nonspec;
// 20 TLB hit direct entry (data) (ind=0 entry hit for SPECULATIVE load/store/cache op)
assign mm_perf_event_t0_d[20] = tlb_cmp_perf_event_t0[5] & event_en[0] & ~tlb_tag4_nonspec;
// 21 TLB miss direct entry (data) (ind=0 entry miss for SPECULATIVE load/store/cache op)
assign mm_perf_event_t0_d[21] = tlb_cmp_perf_event_t0[6] & event_en[0] & ~tlb_tag4_nonspec;
// 22 IERAT miss (or latency), edge (or level) (total SPECULATIVE ierat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
// NOTE - speculative requests do not envoke h/w tablewalker actions..
// ..tablewalker handles only non-speculative requests
assign mm_perf_event_t0_d[22] = (((ierat_req0_valid & ~ierat_req0_nonspec & ierat_req0_thdid[0]) |
(ierat_req1_valid & ~ierat_req1_nonspec & ierat_req1_thdid[0]) |
(ierat_req2_valid & ~ierat_req2_nonspec & ierat_req2_thdid[0]) |
(ierat_req3_valid & ~ierat_req3_nonspec & ierat_req3_thdid[0]) |
// ierat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[0] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) |
// searching tlb for direct entry, or ptereload of instr
(iu_mm_perf_itlb[0] & (~iu_mm_ierat_req_nonspec) & (~xu_mm_ccr2_notlb_b));
// 23 DERAT miss (or latency), edge (or level) (total SPECULATIVE derat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
// NOTE - speculative requests do not envoke h/w tablewalker actions..
// ..tablewalker handles only non-speculative requests
assign mm_perf_event_t0_d[23] = (((derat_req0_valid & ~derat_req0_nonspec & derat_req0_thdid[0]) |
(derat_req1_valid & ~derat_req1_nonspec & derat_req1_thdid[0]) |
(derat_req2_valid & ~derat_req2_nonspec & derat_req2_thdid[0]) |
(derat_req3_valid & ~derat_req3_nonspec & derat_req3_thdid[0]) |
// derat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[0] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) |
// searching tlb for direct entry, or ptereload of data
(lq_mm_perf_dtlb[0] & (~lq_mm_derat_req_nonspec) & (~xu_mm_ccr2_notlb_b));
//--------------------------------------------------
// t* threadwise event list
//--------------------------------------------------
// 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch)
// 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch)
// 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception)
// 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch)
// 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi)
// 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op)
// 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op)
// 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception)
// 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op)
// 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi)
assign mm_perf_event_t1_d[0:9] = tlb_cmp_perf_event_t1[0:9] & {10{event_en[1]}};
// 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
assign mm_perf_event_t1_d[10] = (((ierat_req0_valid & ierat_req0_thdid[1]) |
(ierat_req1_valid & ierat_req1_thdid[1]) |
(ierat_req2_valid & ierat_req2_thdid[1]) |
(ierat_req3_valid & ierat_req3_thdid[1]) |
// ierat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[1]) |
// searching tlb for direct entry, or ptereload of instr
(htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[1]) |
(htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[1]) |
(htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[1]) |
(htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) |
// htw servicing miss of instr
(iu_mm_perf_itlb[1] & (~xu_mm_ccr2_notlb_b));
// 11 DERAT miss (or latency), edge (or level) (total derat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
assign mm_perf_event_t1_d[11] = (((derat_req0_valid & derat_req0_thdid[1]) |
(derat_req1_valid & derat_req1_thdid[1]) |
(derat_req2_valid & derat_req2_thdid[1]) |
(derat_req3_valid & derat_req3_thdid[1]) |
// derat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[1]) |
// searching tlb for direct entry, or ptereload of data
(htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[1]) |
(htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[1]) |
(htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[1]) |
(htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) |
// htw servicing miss of data
(lq_mm_perf_dtlb[1] & (~xu_mm_ccr2_notlb_b));
// 12 TLB hit direct entry (instr.) (ind=0 entry hit for NONSPECULATIVE fetch)
assign mm_perf_event_t1_d[12] = tlb_cmp_perf_event_t1[0] & event_en[1] & tlb_tag4_nonspec;
// 13 TLB miss direct entry (instr.) (ind=0 entry missed for NONSPECULATIVE fetch)
assign mm_perf_event_t1_d[13] = tlb_cmp_perf_event_t1[1] & event_en[1] & tlb_tag4_nonspec;
// 14 TLB hit direct entry (data) (ind=0 entry hit for NONSPECULATIVE load/store/cache op)
assign mm_perf_event_t1_d[14] = tlb_cmp_perf_event_t1[5] & event_en[1] & tlb_tag4_nonspec;
// 15 TLB miss direct entry (data) (ind=0 entry miss for NONSPECULATIVE load/store/cache op)
assign mm_perf_event_t1_d[15] = tlb_cmp_perf_event_t1[6] & event_en[1] & tlb_tag4_nonspec;
// 16 IERAT miss (or latency), edge (or level) (total NONSPECULATIVE ierat misses or latency)
assign mm_perf_event_t1_d[16] = (((ierat_req0_valid & ierat_req0_nonspec & ierat_req0_thdid[1]) |
(ierat_req1_valid & ierat_req1_nonspec & ierat_req1_thdid[1]) |
(ierat_req2_valid & ierat_req2_nonspec & ierat_req2_thdid[1]) |
(ierat_req3_valid & ierat_req3_nonspec & ierat_req3_thdid[1]) |
// ierat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[1] & tlb_tag0_nonspec) |
// searching tlb for direct entry, or ptereload of instr
(htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[1]) |
(htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[1]) |
(htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[1]) |
(htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) |
// htw servicing miss of instr
(iu_mm_perf_itlb[1] & iu_mm_ierat_req_nonspec & (~xu_mm_ccr2_notlb_b));
// 17 DERAT miss (or latency), edge (or level) (total NONSPECULATIVE derat misses or latency)
assign mm_perf_event_t1_d[17] = (((derat_req0_valid & derat_req0_nonspec & derat_req0_thdid[1]) |
(derat_req1_valid & derat_req1_nonspec & derat_req1_thdid[1]) |
(derat_req2_valid & derat_req2_nonspec & derat_req2_thdid[1]) |
(derat_req3_valid & derat_req3_nonspec & derat_req3_thdid[1]) |
// derat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[1] & tlb_tag0_nonspec) |
// searching tlb for direct entry, or ptereload of data
(htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[1]) |
(htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[1]) |
(htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[1]) |
(htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) |
// htw servicing miss of data
(lq_mm_perf_dtlb[1] & lq_mm_derat_req_nonspec & (~xu_mm_ccr2_notlb_b));
// 18 TLB hit direct entry (instr.) (ind=0 entry hit for SPECULATIVE fetch)
assign mm_perf_event_t1_d[18] = tlb_cmp_perf_event_t1[0] & event_en[1] & ~tlb_tag4_nonspec;
// 19 TLB miss direct entry (instr.) (ind=0 entry missed for SPECULATIVE fetch)
assign mm_perf_event_t1_d[19] = tlb_cmp_perf_event_t1[1] & event_en[1] & ~tlb_tag4_nonspec;
// 20 TLB hit direct entry (data) (ind=0 entry hit for SPECULATIVE load/store/cache op)
assign mm_perf_event_t1_d[20] = tlb_cmp_perf_event_t1[5] & event_en[1] & ~tlb_tag4_nonspec;
// 21 TLB miss direct entry (data) (ind=0 entry miss for SPECULATIVE load/store/cache op)
assign mm_perf_event_t1_d[21] = tlb_cmp_perf_event_t1[6] & event_en[1] & ~tlb_tag4_nonspec;
// 22 IERAT miss (or latency), edge (or level) (total SPECULATIVE ierat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
// NOTE - speculative requests do not envoke h/w tablewalker actions..
// ..tablewalker handles only non-speculative requests
assign mm_perf_event_t1_d[22] = (((ierat_req0_valid & ~ierat_req0_nonspec & ierat_req0_thdid[1]) |
(ierat_req1_valid & ~ierat_req1_nonspec & ierat_req1_thdid[1]) |
(ierat_req2_valid & ~ierat_req2_nonspec & ierat_req2_thdid[1]) |
(ierat_req3_valid & ~ierat_req3_nonspec & ierat_req3_thdid[1]) |
// ierat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[1] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) |
// searching tlb for direct entry, or ptereload of instr
(iu_mm_perf_itlb[1] & (~iu_mm_ierat_req_nonspec) & (~xu_mm_ccr2_notlb_b));
// 23 DERAT miss (or latency), edge (or level) (total SPECULATIVE derat misses or latency)
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
// NOTE - speculative requests do not envoke h/w tablewalker actions..
// ..tablewalker handles only non-speculative requests
assign mm_perf_event_t1_d[23] = (((derat_req0_valid & ~derat_req0_nonspec & derat_req0_thdid[1]) |
(derat_req1_valid & ~derat_req1_nonspec & derat_req1_thdid[1]) |
(derat_req2_valid & ~derat_req2_nonspec & derat_req2_thdid[1]) |
(derat_req3_valid & ~derat_req3_nonspec & derat_req3_thdid[1]) |
// derat nonspec miss request
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[1] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) |
// searching tlb for direct entry, or ptereload of data
(lq_mm_perf_dtlb[1] & (~lq_mm_derat_req_nonspec) & (~xu_mm_ccr2_notlb_b));
//--------------------------------------------------
// core single event list
//--------------------------------------------------
// 0 IERAT miss total (part of direct entry search total)
// 1 DERAT miss total (part of direct entry search total)
// 2 TLB miss direct entry total (total TLB ind=0 misses)
// 3 TLB hit direct entry first page size
//--------------------------------------------------
// 4 TLB indirect entry hits total (=page table searches)
// 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss)
// 6 LRAT translation request total (for GS=1 tlbwe and ptereload)
// 7 LRAT misses total (for GS=1 tlbwe and ptereload)
//--------------------------------------------------
// 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi)
// 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi)
// 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match)
// 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match)
//--------------------------------------------------
// 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total)
// 13 tlbivax invalidations sourced total (sourced tlbivax on this core total)
// 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care)
// 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards)
//--------------------------------------------------
// 16 IERAT NONSPECULATIVE miss total (part of direct entry search total)
// 17 DERAT NONSPECULATIVE miss total (part of direct entry search total)
// 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses)
// 19 TLB NONSPECULATIVE hit direct entry first page size
//--------------------------------------------------
// 20 IERAT SPECULATIVE miss total (part of direct entry search total)
// 21 DERAT SPECULATIVE miss total (part of direct entry search total)
// 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses)
// 23 TLB SPECULATIVE hit direct entry first page size
//--------------------------------------------------
// 24 ERAT miss total (TLB direct entry search total for both I and D sides)
// 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides)
// 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides)
// 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides)
// 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides)
// 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides)
// 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1)
// 31 Raw Total ERAT misses, either mode
// 0 IERAT miss total (part of direct entry search total)
assign mm_perf_event_core_level_d[0] = (ierat_req_taken & xu_mm_ccr2_notlb_b) |
( |(iu_mm_perf_itlb) & (~xu_mm_ccr2_notlb_b) );
// 1 DERAT miss total (part of direct entry search total)
assign mm_perf_event_core_level_d[1] = (derat_req_taken & xu_mm_ccr2_notlb_b) |
( |(lq_mm_perf_dtlb) & (~xu_mm_ccr2_notlb_b) );
// 2 TLB miss direct entry total (total TLB ind=0 misses)
assign mm_perf_event_core_level_d[2] = tlb_cmp_perf_miss_direct & event_en[4];
// 3 TLB hit direct entry first page size
assign mm_perf_event_core_level_d[3] = tlb_cmp_perf_hit_first_page & event_en[4];
// 4 TLB indirect entry hits total (=page table searches)
assign mm_perf_event_core_level_d[4] = tlb_cmp_perf_hit_indirect & event_en[4];
// 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss)
assign mm_perf_event_core_level_d[5] = tlb_cmp_perf_ptereload_noexcep & event_en[4];
// 6 LRAT translation request total (for GS=1 tlbwe and ptereload)
assign mm_perf_event_core_level_d[6] = tlb_cmp_perf_lrat_request & event_en[4];
// 7 LRAT misses total (for GS=1 tlbwe and ptereload)
assign mm_perf_event_core_level_d[7] = tlb_cmp_perf_lrat_miss & event_en[4];
// 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi)
assign mm_perf_event_core_level_d[8] = tlb_cmp_perf_pt_fault & event_en[4];
// 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi)
assign mm_perf_event_core_level_d[9] = tlb_cmp_perf_pt_inelig & event_en[4];
// 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match)
assign mm_perf_event_core_level_d[10] = tlb_ctl_perf_tlbwec_noresv & event_en[4];
// 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match)
assign mm_perf_event_core_level_d[11] = tlb_ctl_perf_tlbwec_resv & event_en[4];
// 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total)
assign mm_perf_event_core_level_d[12] = inval_perf_tlbilx;
// 13 tlbivax invalidations sourced total (sourced tlbivax on this core total)
assign mm_perf_event_core_level_d[13] = inval_perf_tlbivax;
// 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care)
assign mm_perf_event_core_level_d[14] = inval_perf_tlbivax_snoop;
// 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards)
assign mm_perf_event_core_level_d[15] = inval_perf_tlb_flush;
//--------------------------------------------------
// 16 IERAT NONSPECULATIVE miss total (part of direct entry search total)
assign mm_perf_event_core_level_d[16] = (mm_perf_event_core_level_q[0] & tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // ierat_req_taken, nonspec
( |(iu_mm_perf_itlb) & iu_mm_ierat_req_nonspec & (~xu_mm_ccr2_notlb_b) );
// 17 DERAT NONSPECULATIVE miss total (part of direct entry search total)
assign mm_perf_event_core_level_d[17] = (mm_perf_event_core_level_q[1] & tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // derat_req_taken, nonspec
( |(lq_mm_perf_dtlb) & lq_mm_derat_req_nonspec & (~xu_mm_ccr2_notlb_b) );
// 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses)
assign mm_perf_event_core_level_d[18] = tlb_cmp_perf_miss_direct & event_en[4] & tlb_tag4_nonspec;
// 19 TLB NONSPECULATIVE hit direct entry first page size
assign mm_perf_event_core_level_d[19] = tlb_cmp_perf_hit_first_page & event_en[4] & tlb_tag4_nonspec;
//--------------------------------------------------
// 20 IERAT SPECULATIVE miss total (part of direct entry search total)
assign mm_perf_event_core_level_d[20] = (mm_perf_event_core_level_q[0] & ~tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // ierat_req_taken, spec
( |(iu_mm_perf_itlb) & (~iu_mm_ierat_req_nonspec) & (~xu_mm_ccr2_notlb_b) );
// 21 DERAT SPECULATIVE miss total (part of direct entry search total)
assign mm_perf_event_core_level_d[21] = (mm_perf_event_core_level_q[1] & ~tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // derat_req_taken, spec
( |(lq_mm_perf_dtlb) & (~lq_mm_derat_req_nonspec) & (~xu_mm_ccr2_notlb_b) );
// 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses)
assign mm_perf_event_core_level_d[22] = tlb_cmp_perf_miss_direct & event_en[4] & ~tlb_tag4_nonspec;
// 23 TLB SPECULATIVE hit direct entry first page size
assign mm_perf_event_core_level_d[23] = tlb_cmp_perf_hit_first_page & event_en[4] & ~tlb_tag4_nonspec;
//--------------------------------------------------
// 24 ERAT miss total (TLB direct entry search total for both I and D sides)
assign mm_perf_event_core_level_d[24] = (mm_perf_event_core_level_q[0] | mm_perf_event_core_level_q[1]); // i/derat_req_taken (tlb mode),
// or raw i/derat misses (erat-only mode)
// 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides)
assign mm_perf_event_core_level_d[25] = ( (mm_perf_event_core_level_q[0] | mm_perf_event_core_level_q[1]) & tlb_tag0_nonspec & xu_mm_ccr2_notlb_b ) | // nonspec i/derat_req_taken (tlb mode)
( (mm_perf_event_core_level_q[16] | mm_perf_event_core_level_q[17]) & (~xu_mm_ccr2_notlb_b) ); // raw nonspec i/derat misses (erat-only mode)
// 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides)
assign mm_perf_event_core_level_d[26] = ( (mm_perf_event_core_level_q[0] | mm_perf_event_core_level_q[1]) & ~tlb_tag0_nonspec & xu_mm_ccr2_notlb_b ) | // spec i/derat_req_taken (tlb mode)
( (mm_perf_event_core_level_q[20] | mm_perf_event_core_level_q[21]) & (~xu_mm_ccr2_notlb_b) ); // raw spec i/derat misses (erat-only mode)
// 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides)
assign mm_perf_event_core_level_d[27] = tlb_cmp_perf_hit_direct & event_en[4];
// 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides)
assign mm_perf_event_core_level_d[28] = tlb_cmp_perf_hit_direct & event_en[4] & tlb_tag4_nonspec;
// 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides)
assign mm_perf_event_core_level_d[29] = tlb_cmp_perf_hit_direct & event_en[4] & ~tlb_tag4_nonspec;
// 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1)
assign mm_perf_event_core_level_d[30] = tlb_cmp_perf_ptereload & event_en[4];
// 31 Raw Total ERAT misses, either mode
assign mm_perf_event_core_level_d[31] = ( |(iu_mm_perf_itlb) | |(lq_mm_perf_dtlb) );
//--------------------------------------------------
// end of core single event list
//--------------------------------------------------
assign unit_t0_events_in = {1'b0, mm_perf_event_t0_q[0:23],
7'b0,
mm_perf_event_core_level_q[0:31]};
tri_event_mux1t #(.EVENTS_IN(`PERF_MUX_WIDTH), .EVENTS_OUT(4)) event_mux0(
.vd(vdd),
.gd(gnd),
.select_bits(mmq_spr_event_mux_ctrls_q[0:`MESR1_WIDTH - 1]),
.unit_events_in(unit_t0_events_in[1:63]),
.event_bus_in(mm_event_bus_in[0:3]),
.event_bus_out(event_bus_out_d[0:3])
);
`ifndef THREADS1
assign unit_t1_events_in = {1'b0, mm_perf_event_t1_q[0:23],
7'b0,
mm_perf_event_core_level_q[0:31]};
tri_event_mux1t #(.EVENTS_IN(`PERF_MUX_WIDTH), .EVENTS_OUT(4)) event_mux1(
.vd(vdd),
.gd(gnd),
.select_bits(mmq_spr_event_mux_ctrls_q[`MESR1_WIDTH:`MESR1_WIDTH+`MESR2_WIDTH - 1]),
.unit_events_in(unit_t1_events_in),
.event_bus_in(mm_event_bus_in[4:7]),
.event_bus_out(event_bus_out_d[4:7])
);
`endif
assign mm_event_bus_out = event_bus_out_q;
//---------------------------------------------------------------------
// Latches
//---------------------------------------------------------------------
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rp_mm_event_bus_enable_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_func_sl_thold_0_b),
.sg(pc_sg_0),
.force_t(force_t),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.d_mode(lcb_d_mode_dc),
.scin(siv[rp_mm_event_bus_enable_offset]),
.scout(sov[rp_mm_event_bus_enable_offset]),
.din(rp_mm_event_bus_enable_q), // yes, this in the input name
.dout(rp_mm_event_bus_enable_int_q) // this is local internal version
);
tri_rlmreg_p #(.WIDTH(`MESR1_WIDTH*`THREADS), .INIT(0)) mmq_spr_event_mux_ctrls_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_func_sl_thold_0_b),
.sg(pc_sg_0),
.force_t(force_t),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.d_mode(lcb_d_mode_dc),
.scin(siv[mmq_spr_event_mux_ctrls_offset:mmq_spr_event_mux_ctrls_offset + `MESR1_WIDTH*`THREADS - 1]),
.scout(sov[mmq_spr_event_mux_ctrls_offset:mmq_spr_event_mux_ctrls_offset + `MESR1_WIDTH*`THREADS - 1]),
.din(mmq_spr_event_mux_ctrls),
.dout(mmq_spr_event_mux_ctrls_q)
);
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) pc_mm_event_count_mode_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_func_sl_thold_0_b),
.sg(pc_sg_0),
.force_t(force_t),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.d_mode(lcb_d_mode_dc),
.scin(siv[pc_mm_event_count_mode_offset:pc_mm_event_count_mode_offset + 3 - 1]),
.scout(sov[pc_mm_event_count_mode_offset:pc_mm_event_count_mode_offset + 3 - 1]),
.din(pc_mm_event_count_mode),
.dout(pc_mm_event_count_mode_q)
);
tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0)) xu_mm_msr_gs_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rp_mm_event_bus_enable_int_q),
.thold_b(pc_func_sl_thold_0_b),
.sg(pc_sg_0),
.force_t(force_t),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.d_mode(lcb_d_mode_dc),
.scin(siv[xu_mm_msr_gs_offset:xu_mm_msr_gs_offset + `THDID_WIDTH - 1]),
.scout(sov[xu_mm_msr_gs_offset:xu_mm_msr_gs_offset + `THDID_WIDTH - 1]),
.din(xu_mm_msr_gs),
.dout(xu_mm_msr_gs_q)
);
tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0)) xu_mm_msr_pr_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rp_mm_event_bus_enable_int_q),
.thold_b(pc_func_sl_thold_0_b),
.sg(pc_sg_0),
.force_t(force_t),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.d_mode(lcb_d_mode_dc),
.scin(siv[xu_mm_msr_pr_offset:xu_mm_msr_pr_offset + `THDID_WIDTH - 1]),
.scout(sov[xu_mm_msr_pr_offset:xu_mm_msr_pr_offset + `THDID_WIDTH - 1]),
.din(xu_mm_msr_pr),
.dout(xu_mm_msr_pr_q)
);
tri_rlmreg_p #(.WIDTH(`PERF_EVENT_WIDTH*`THREADS), .INIT(0)) event_bus_out_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rp_mm_event_bus_enable_int_q),
.thold_b(pc_func_sl_thold_0_b),
.sg(pc_sg_0),
.force_t(force_t),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.d_mode(lcb_d_mode_dc),
.scin(siv[event_bus_out_offset:event_bus_out_offset + `PERF_EVENT_WIDTH*`THREADS - 1]),
.scout(sov[event_bus_out_offset:event_bus_out_offset + `PERF_EVENT_WIDTH*`THREADS - 1]),
.din(event_bus_out_d),
.dout(event_bus_out_q)
);
tri_regk #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_t0_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(rp_mm_event_bus_enable_int_q),
.sg(pc_sg_0),
.force_t(pc_func_slp_nsl_force),
.d_mode(lcb_d_mode_dc),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.thold_b(pc_func_slp_nsl_thold_0_b),
.scin(tri_regk_unused_scan[0:23]),
.scout(tri_regk_unused_scan[0:23]),
.din(mm_perf_event_t0_d),
.dout(mm_perf_event_t0_q)
);
tri_regk #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_t1_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(rp_mm_event_bus_enable_int_q),
.sg(pc_sg_0),
.force_t(pc_func_slp_nsl_force),
.d_mode(lcb_d_mode_dc),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.thold_b(pc_func_slp_nsl_thold_0_b),
.scin(tri_regk_unused_scan[24:47]),
.scout(tri_regk_unused_scan[24:47]),
.din(mm_perf_event_t1_d),
.dout(mm_perf_event_t1_q)
);
tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_core_level_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(rp_mm_event_bus_enable_int_q),
.sg(pc_sg_0),
.force_t(pc_func_slp_nsl_force),
.d_mode(lcb_d_mode_dc),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.thold_b(pc_func_slp_nsl_thold_0_b),
.scin(tri_regk_unused_scan[48:79]),
.scout(tri_regk_unused_scan[48:79]),
.din(mm_perf_event_core_level_d),
.dout(mm_perf_event_core_level_q)
);
//-----------------------------------------------
// pervasive
//-----------------------------------------------
tri_plat #(.WIDTH(4)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din( {pc_func_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ),
.q( {pc_func_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} )
);
tri_plat #(.WIDTH(4)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din( {pc_func_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ),
.q( {pc_func_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} )
);
tri_lcbor perv_lcbor(
.clkoff_b(lcb_clkoff_dc_b),
.thold(pc_func_sl_thold_0),
.sg(pc_sg_0),
.act_dis(lcb_act_dis_dc),
.force_t(force_t),
.thold_b(pc_func_sl_thold_0_b)
);
tri_lcbor perv_nsl_lcbor(
.clkoff_b(lcb_clkoff_dc_b),
.thold(pc_func_slp_nsl_thold_0),
.sg(pc_fce_0),
.act_dis(tidn),
.force_t(pc_func_slp_nsl_force),
.thold_b(pc_func_slp_nsl_thold_0_b)
);
//---------------------------------------------------------------------
// Scan
//---------------------------------------------------------------------
assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
assign scan_out = sov[0];
endmodule |
module rv_dep(
`include "tri_a2o.vh"
//------------------------------------------------------------------------------------------------------------
// IU Control
//------------------------------------------------------------------------------------------------------------
input iu_xx_zap,
input rv0_i0_act,
input rv0_i1_act,
//------------------------------------------------------------------------------------------------------------
// Instruction Sources
//------------------------------------------------------------------------------------------------------------
input rv0_instr_i0_vld,
input rv0_instr_i0_t1_v,
input rv0_instr_i0_t2_v,
input rv0_instr_i0_t3_v,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag,
input rv0_instr_i0_s1_v,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag,
input rv0_instr_i0_s2_v,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag,
input rv0_instr_i0_s3_v,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag,
input rv0_instr_i1_vld,
input rv0_instr_i1_t1_v,
input rv0_instr_i1_t2_v,
input rv0_instr_i1_t3_v,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag,
input rv0_instr_i1_s1_v,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag,
input rv0_instr_i1_s2_v,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag,
input rv0_instr_i1_s3_v,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag,
//------------------------------------------------------------------------------------------------------------
// ITAG Busses
//------------------------------------------------------------------------------------------------------------
input fx0_rv_itag_vld,
input [0:`ITAG_SIZE_ENC-1] fx0_rv_itag,
input fx1_rv_itag_vld,
input [0:`ITAG_SIZE_ENC-1] fx1_rv_itag,
input lq_rv_itag0_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0,
input lq_rv_itag1_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1,
input lq_rv_itag2_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_itag2,
input axu0_rv_itag_vld,
input [0:`ITAG_SIZE_ENC-1] axu0_rv_itag,
input axu1_rv_itag_vld,
input [0:`ITAG_SIZE_ENC-1] axu1_rv_itag,
input fx0_rv_itag_abort,
input fx1_rv_itag_abort,
input lq_rv_itag0_abort,
input lq_rv_itag1_abort,
input axu0_rv_itag_abort,
input axu1_rv_itag_abort,
//------------------------------------------------------------------------------------------------------------
// Source Hit Information
//------------------------------------------------------------------------------------------------------------
output rv0_instr_i0_s1_dep_hit,
output rv0_instr_i0_s2_dep_hit,
output rv0_instr_i0_s3_dep_hit,
output rv0_instr_i1_s1_dep_hit,
output rv0_instr_i1_s2_dep_hit,
output rv0_instr_i1_s3_dep_hit,
//------------------------------------------------------------------------------------------------------------
// Pervasive
//------------------------------------------------------------------------------------------------------------
inout vdd,
inout gnd,
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk
input [0:`NCLK_WIDTH-1] nclk,
input func_sl_thold_1,
input sg_1,
input clkoff_b,
input act_dis,
input ccflush_dc,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input scan_in,
output scan_out
);
//------------------------------------------------------------------------------------------------------------
// Misc
//------------------------------------------------------------------------------------------------------------
wire tiup;
parameter zero = 0;
//------------------------------------------------------------------------------------------------------------
// Input Latches
//------------------------------------------------------------------------------------------------------------
wire rv0_sc_act;
wire [0:6] xx_rv_itag_v_d;
wire [0:6] xx_rv_itag_v_q;
wire [0:6] xx_rv_itag_abort_d;
wire [0:6] xx_rv_itag_abort_q;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary0_d;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary1_d;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary2_d;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary3_d;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary4_d;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary5_d;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary6_d;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary0_q;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary1_q;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary2_q;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary3_q;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary4_q;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary5_q;
wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary6_q;
//------------------------------------------------------------------------------------------------------------
// GPR PRF Scorecard Signals
//------------------------------------------------------------------------------------------------------------
wire i0_target_v;
wire i1_target_v;
wire rv0_instr_i0_s1_dep_hit_v;
wire rv0_instr_i0_s2_dep_hit_v;
wire rv0_instr_i0_s3_dep_hit_v;
wire rv0_instr_i1_s1_dep_hit_v;
wire rv0_instr_i1_s2_dep_hit_v;
wire rv0_instr_i1_s3_dep_hit_v;
//------------------------------------------------------------------------------------------------------------
// Scan
//------------------------------------------------------------------------------------------------------------
parameter scorecard_offset = 0;
parameter xx_rv_itag_v_offset = scorecard_offset + 1;
parameter xx_rv_itag_abort_offset = xx_rv_itag_v_offset + 7;
parameter xx_rv_itag_ary0_offset = xx_rv_itag_abort_offset + 7;
parameter xx_rv_itag_ary1_offset = xx_rv_itag_ary0_offset + `ITAG_SIZE_ENC-2;
parameter xx_rv_itag_ary2_offset = xx_rv_itag_ary1_offset + `ITAG_SIZE_ENC-2;
parameter xx_rv_itag_ary3_offset = xx_rv_itag_ary2_offset + `ITAG_SIZE_ENC-2;
parameter xx_rv_itag_ary4_offset = xx_rv_itag_ary3_offset + `ITAG_SIZE_ENC-2;
parameter xx_rv_itag_ary5_offset = xx_rv_itag_ary4_offset + `ITAG_SIZE_ENC-2;
parameter xx_rv_itag_ary6_offset = xx_rv_itag_ary5_offset + `ITAG_SIZE_ENC-2;
parameter scan_right = xx_rv_itag_ary6_offset + `ITAG_SIZE_ENC-2;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
wire func_sl_thold_0;
wire func_sl_thold_0_b;
wire sg_0;
wire force_t;
(* analysis_not_referenced="true" *)
wire unused;
assign rv0_sc_act = rv0_i0_act | rv0_i1_act | (|xx_rv_itag_v_q) | (|iu_xx_zap);
//------------------------------------------------------------------------------------------------------------
// GPR PRF Scorecard
//------------------------------------------------------------------------------------------------------------
assign i0_target_v = rv0_instr_i0_vld & (rv0_instr_i0_t1_v | rv0_instr_i0_t2_v | rv0_instr_i0_t3_v);
assign i1_target_v = rv0_instr_i1_vld & (rv0_instr_i1_t1_v | rv0_instr_i1_t2_v | rv0_instr_i1_t3_v);
//num_entries_enc_g => ``GPR_POOL_ENC,
rv_dep_scard #(.num_entries_g(2 ** (`ITAG_SIZE_ENC - 2)), .itag_width_enc_g(`ITAG_SIZE_ENC - 2) ) sc(
.iu_xx_zap(iu_xx_zap),
.rv0_sc_act(rv0_sc_act),
.ta_v(i0_target_v),
.ta_itag(rv0_instr_i0_itag[2:`ITAG_SIZE_ENC - 1]),
.tb_v(i1_target_v),
.tb_itag(rv0_instr_i1_itag[2:`ITAG_SIZE_ENC - 1]),
.xx_rv_itag_v(xx_rv_itag_v_q),
.xx_rv_itag_abort(xx_rv_itag_abort_q),
.xx_rv_itag_ary0(xx_rv_itag_ary0_q),
.xx_rv_itag_ary1(xx_rv_itag_ary1_q),
.xx_rv_itag_ary2(xx_rv_itag_ary2_q),
.xx_rv_itag_ary3(xx_rv_itag_ary3_q),
.xx_rv_itag_ary4(xx_rv_itag_ary4_q),
.xx_rv_itag_ary5(xx_rv_itag_ary5_q),
.xx_rv_itag_ary6(xx_rv_itag_ary6_q),
.i0_s1_itag(rv0_instr_i0_s1_itag[2:`ITAG_SIZE_ENC - 1]),
.i0_s2_itag(rv0_instr_i0_s2_itag[2:`ITAG_SIZE_ENC - 1]),
.i0_s3_itag(rv0_instr_i0_s3_itag[2:`ITAG_SIZE_ENC - 1]),
.i1_s1_itag(rv0_instr_i1_s1_itag[2:`ITAG_SIZE_ENC - 1]),
.i1_s2_itag(rv0_instr_i1_s2_itag[2:`ITAG_SIZE_ENC - 1]),
.i1_s3_itag(rv0_instr_i1_s3_itag[2:`ITAG_SIZE_ENC - 1]),
.i0_s1_itag_v(rv0_instr_i0_s1_dep_hit_v),
.i0_s2_itag_v(rv0_instr_i0_s2_dep_hit_v),
.i0_s3_itag_v(rv0_instr_i0_s3_dep_hit_v),
.i1_s1_itag_v(rv0_instr_i1_s1_dep_hit_v),
.i1_s2_itag_v(rv0_instr_i1_s2_dep_hit_v),
.i1_s3_itag_v(rv0_instr_i1_s3_dep_hit_v),
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.chip_b_sl_sg_0_t(sg_0),
.chip_b_sl_2_thold_0_b(func_sl_thold_0_b),
.force_t(force_t),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scan_in(siv[scorecard_offset]),
.scan_out(sov[scorecard_offset])
);
assign rv0_instr_i0_s1_dep_hit = rv0_instr_i0_s1_dep_hit_v & (rv0_instr_i0_s1_v & ~rv0_instr_i0_s1_itag[1]);
assign rv0_instr_i0_s2_dep_hit = rv0_instr_i0_s2_dep_hit_v & (rv0_instr_i0_s2_v & ~rv0_instr_i0_s2_itag[1]);
assign rv0_instr_i0_s3_dep_hit = rv0_instr_i0_s3_dep_hit_v & (rv0_instr_i0_s3_v & ~rv0_instr_i0_s3_itag[1]);
assign rv0_instr_i1_s1_dep_hit = rv0_instr_i1_s1_dep_hit_v & (rv0_instr_i1_s1_v & ~rv0_instr_i1_s1_itag[1]);
assign rv0_instr_i1_s2_dep_hit = rv0_instr_i1_s2_dep_hit_v & (rv0_instr_i1_s2_v & ~rv0_instr_i1_s2_itag[1]);
assign rv0_instr_i1_s3_dep_hit = rv0_instr_i1_s3_dep_hit_v & (rv0_instr_i1_s3_v & ~rv0_instr_i1_s3_itag[1]);
//------------------------------------------------------------------------------------------------------------
// Misc
//------------------------------------------------------------------------------------------------------------
assign tiup = 1'b1;
//------------------------------------------------------------------------------------------------------------
// Release/Abort Busses
//------------------------------------------------------------------------------------------------------------
assign xx_rv_itag_v_d[0] = fx0_rv_itag_vld & ~(iu_xx_zap);
assign xx_rv_itag_v_d[1] = fx1_rv_itag_vld & ~(iu_xx_zap);
assign xx_rv_itag_v_d[2] = lq_rv_itag0_vld & ~(iu_xx_zap);
assign xx_rv_itag_v_d[3] = lq_rv_itag1_vld & ~(iu_xx_zap);
assign xx_rv_itag_v_d[4] = lq_rv_itag2_vld & ~(iu_xx_zap);
assign xx_rv_itag_v_d[5] = axu0_rv_itag_vld & ~(iu_xx_zap);
assign xx_rv_itag_v_d[6] = axu1_rv_itag_vld & ~(iu_xx_zap);
assign xx_rv_itag_ary0_d = fx0_rv_itag[2:`ITAG_SIZE_ENC - 1];
assign xx_rv_itag_ary1_d = fx1_rv_itag[2:`ITAG_SIZE_ENC - 1];
assign xx_rv_itag_ary2_d = lq_rv_itag0[2:`ITAG_SIZE_ENC - 1];
assign xx_rv_itag_ary3_d = lq_rv_itag1[2:`ITAG_SIZE_ENC - 1];
assign xx_rv_itag_ary4_d = lq_rv_itag2[2:`ITAG_SIZE_ENC - 1];
assign xx_rv_itag_ary5_d = axu0_rv_itag[2:`ITAG_SIZE_ENC - 1];
assign xx_rv_itag_ary6_d = axu1_rv_itag[2:`ITAG_SIZE_ENC - 1];
assign xx_rv_itag_abort_d[0] = fx0_rv_itag_abort;
assign xx_rv_itag_abort_d[1] = fx1_rv_itag_abort;
assign xx_rv_itag_abort_d[2] = lq_rv_itag0_abort;
assign xx_rv_itag_abort_d[3] = lq_rv_itag1_abort;
assign xx_rv_itag_abort_d[4] = 1'b0;
assign xx_rv_itag_abort_d[5] = axu0_rv_itag_abort;
assign xx_rv_itag_abort_d[6] = axu1_rv_itag_abort;
//------------------------------------------------------------------------------------------------------------
// Latches
//------------------------------------------------------------------------------------------------------------
tri_rlmreg_p #(.WIDTH(7), .INIT(0) ) xx_rv_itag_v_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[xx_rv_itag_v_offset:xx_rv_itag_v_offset + 7 - 1]),
.scout(sov[xx_rv_itag_v_offset:xx_rv_itag_v_offset + 7 - 1]),
.din(xx_rv_itag_v_d),
.dout(xx_rv_itag_v_q)
);
tri_rlmreg_p #(.WIDTH(7), .INIT(0) ) xx_rv_itag_abort_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[xx_rv_itag_abort_offset:xx_rv_itag_abort_offset + 7 - 1]),
.scout(sov[xx_rv_itag_abort_offset:xx_rv_itag_abort_offset + 7 - 1]),
.din(xx_rv_itag_abort_d),
.dout(xx_rv_itag_abort_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary0_q_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin( siv[xx_rv_itag_ary0_offset :xx_rv_itag_ary0_offset + `ITAG_SIZE_ENC-2 - 1]),
.scout(sov[xx_rv_itag_ary0_offset :xx_rv_itag_ary0_offset + `ITAG_SIZE_ENC-2 - 1]),
.din(xx_rv_itag_ary0_d),
.dout(xx_rv_itag_ary0_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary1_q_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin( siv[xx_rv_itag_ary1_offset :xx_rv_itag_ary1_offset + `ITAG_SIZE_ENC-2 - 1]),
.scout(sov[xx_rv_itag_ary1_offset :xx_rv_itag_ary1_offset + `ITAG_SIZE_ENC-2 - 1]),
.din(xx_rv_itag_ary1_d),
.dout(xx_rv_itag_ary1_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary2_q_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin( siv[xx_rv_itag_ary2_offset :xx_rv_itag_ary2_offset + `ITAG_SIZE_ENC-2 - 1]),
.scout(sov[xx_rv_itag_ary2_offset :xx_rv_itag_ary2_offset + `ITAG_SIZE_ENC-2 - 1]),
.din(xx_rv_itag_ary2_d),
.dout(xx_rv_itag_ary2_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary3_q_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin( siv[xx_rv_itag_ary3_offset :xx_rv_itag_ary3_offset + `ITAG_SIZE_ENC-2 - 1]),
.scout(sov[xx_rv_itag_ary3_offset :xx_rv_itag_ary3_offset + `ITAG_SIZE_ENC-2 - 1]),
.din(xx_rv_itag_ary3_d),
.dout(xx_rv_itag_ary3_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary4_q_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin( siv[xx_rv_itag_ary4_offset :xx_rv_itag_ary4_offset + `ITAG_SIZE_ENC-2 - 1]),
.scout(sov[xx_rv_itag_ary4_offset :xx_rv_itag_ary4_offset + `ITAG_SIZE_ENC-2 - 1]),
.din(xx_rv_itag_ary4_d),
.dout(xx_rv_itag_ary4_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary5_q_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin( siv[xx_rv_itag_ary5_offset :xx_rv_itag_ary5_offset + `ITAG_SIZE_ENC-2 - 1]),
.scout(sov[xx_rv_itag_ary5_offset :xx_rv_itag_ary5_offset + `ITAG_SIZE_ENC-2 - 1]),
.din(xx_rv_itag_ary5_d),
.dout(xx_rv_itag_ary5_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary6_q_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin( siv[xx_rv_itag_ary6_offset :xx_rv_itag_ary6_offset + `ITAG_SIZE_ENC-2 - 1]),
.scout(sov[xx_rv_itag_ary6_offset :xx_rv_itag_ary6_offset + `ITAG_SIZE_ENC-2 - 1]),
.din(xx_rv_itag_ary6_d),
.dout(xx_rv_itag_ary6_q)
);
//---------------------------------------------------------------------
// Scan
//---------------------------------------------------------------------
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
//-----------------------------------------------
// pervasive
//-----------------------------------------------
tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_dc),
.din({func_sl_thold_1,sg_1}),
.q({func_sl_thold_0,sg_0})
);
tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b),
.thold(func_sl_thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(func_sl_thold_0_b)
);
//-----------------------------------------------
// unused signals
//-----------------------------------------------
assign unused = rv0_instr_i0_s1_itag[0] | rv0_instr_i0_s2_itag[0] | rv0_instr_i0_s3_itag[0] |
rv0_instr_i1_s1_itag[0] | rv0_instr_i1_s2_itag[0] | rv0_instr_i1_s3_itag[0] |
|rv0_instr_i0_itag[0:1] | |rv0_instr_i1_itag[0:1] |
|fx0_rv_itag[0:1] | |fx1_rv_itag[0:1] | |lq_rv_itag0[0:1] | |lq_rv_itag1[0:1] | |lq_rv_itag2[0:1] | |axu0_rv_itag[0:1] | |axu1_rv_itag[0:1] ;
endmodule |
module fu_tblsqe(
f,
est,
rng
);
input [1:6] f;
output [1:20] est;
output [6:20] rng;
// end ports
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire dcd_00x;
wire dcd_01x;
wire dcd_10x;
wire dcd_11x;
wire dcd_000;
wire dcd_001;
wire dcd_010;
wire dcd_011;
wire dcd_100;
wire dcd_101;
wire dcd_110;
wire dcd_111;
wire combo2_1000;
wire combo2_0100;
wire combo2_1100;
wire combo2_0010;
wire combo2_1010;
wire combo2_0110;
wire combo2_1110;
wire combo2_0001;
wire combo2_1001;
wire combo2_0101;
wire combo2_1101;
wire combo2_0011;
wire combo2_1011;
wire combo2_0111;
wire combo2_1000_xxxx_b;
wire combo2_0100_xxxx_b;
wire combo2_1100_xxxx_b;
wire combo2_0010_xxxx_b;
wire combo2_1010_xxxx_b;
wire combo2_0110_xxxx_b;
wire combo2_1110_xxxx_b;
wire combo2_0001_xxxx_b;
wire combo2_1001_xxxx_b;
wire combo2_0101_xxxx_b;
wire combo2_1101_xxxx_b;
wire combo2_0011_xxxx_b;
wire combo2_1011_xxxx_b;
wire combo2_0111_xxxx_b;
wire combo2_xxxx_1000_b;
wire combo2_xxxx_0100_b;
wire combo2_xxxx_1100_b;
wire combo2_xxxx_0010_b;
wire combo2_xxxx_1010_b;
wire combo2_xxxx_0110_b;
wire combo2_xxxx_1110_b;
wire combo2_xxxx_0001_b;
wire combo2_xxxx_1001_b;
wire combo2_xxxx_0101_b;
wire combo2_xxxx_1101_b;
wire combo2_xxxx_0011_b;
wire combo2_xxxx_1011_b;
wire combo2_xxxx_0111_b;
wire combo3_0000_0001;
wire combo3_0000_0011;
wire combo3_0000_0100;
wire combo3_0000_0111;
wire combo3_0000_1001;
wire combo3_0000_1010;
wire combo3_0000_1011;
wire combo3_0000_1101;
wire combo3_0000_1111;
wire combo3_0001_0001;
wire combo3_0001_0010;
wire combo3_0001_0100;
wire combo3_0001_0101;
wire combo3_0001_0111;
wire combo3_0001_1000;
wire combo3_0001_1100;
wire combo3_0001_1101;
wire combo3_0001_1110;
wire combo3_0001_1111;
wire combo3_0010_0001;
wire combo3_0010_0011;
wire combo3_0010_0100;
wire combo3_0010_0101;
wire combo3_0010_1000;
wire combo3_0010_1001;
wire combo3_0010_1010;
wire combo3_0010_1100;
wire combo3_0010_1101;
wire combo3_0010_1110;
wire combo3_0010_1111;
wire combo3_0011_0000;
wire combo3_0011_0001;
wire combo3_0011_0011;
wire combo3_0011_0101;
wire combo3_0011_0110;
wire combo3_0011_1000;
wire combo3_0011_1001;
wire combo3_0011_1110;
wire combo3_0011_1111;
wire combo3_0100_0000;
wire combo3_0100_0010;
wire combo3_0100_0100;
wire combo3_0100_0101;
wire combo3_0100_1001;
wire combo3_0100_1100;
wire combo3_0100_1110;
wire combo3_0100_1111;
wire combo3_0101_0010;
wire combo3_0101_0100;
wire combo3_0101_0110;
wire combo3_0101_1001;
wire combo3_0101_1100;
wire combo3_0101_1111;
wire combo3_0110_0000;
wire combo3_0110_0011;
wire combo3_0110_0110;
wire combo3_0110_0111;
wire combo3_0110_1100;
wire combo3_0110_1101;
wire combo3_0110_1111;
wire combo3_0111_0000;
wire combo3_0111_0101;
wire combo3_0111_0111;
wire combo3_0111_1000;
wire combo3_0111_1001;
wire combo3_0111_1010;
wire combo3_0111_1111;
wire combo3_1000_0000;
wire combo3_1000_0011;
wire combo3_1000_0110;
wire combo3_1000_0111;
wire combo3_1000_1010;
wire combo3_1000_1110;
wire combo3_1001_0000;
wire combo3_1001_0001;
wire combo3_1001_0010;
wire combo3_1001_0100;
wire combo3_1001_0110;
wire combo3_1001_0111;
wire combo3_1001_1000;
wire combo3_1001_1001;
wire combo3_1001_1010;
wire combo3_1001_1011;
wire combo3_1001_1100;
wire combo3_1010_0000;
wire combo3_1010_0001;
wire combo3_1010_0010;
wire combo3_1010_0100;
wire combo3_1010_0101;
wire combo3_1010_0110;
wire combo3_1010_0111;
wire combo3_1010_1001;
wire combo3_1010_1010;
wire combo3_1010_1100;
wire combo3_1010_1101;
wire combo3_1010_1111;
wire combo3_1011_0001;
wire combo3_1011_0010;
wire combo3_1011_0100;
wire combo3_1011_0101;
wire combo3_1011_1000;
wire combo3_1011_1010;
wire combo3_1011_1100;
wire combo3_1100_0000;
wire combo3_1100_0001;
wire combo3_1100_0011;
wire combo3_1100_0101;
wire combo3_1100_0110;
wire combo3_1100_0111;
wire combo3_1100_1001;
wire combo3_1100_1010;
wire combo3_1100_1011;
wire combo3_1100_1101;
wire combo3_1100_1111;
wire combo3_1101_0010;
wire combo3_1101_0011;
wire combo3_1101_1000;
wire combo3_1101_1001;
wire combo3_1101_1010;
wire combo3_1101_1100;
wire combo3_1101_1110;
wire combo3_1101_1111;
wire combo3_1110_0000;
wire combo3_1110_0001;
wire combo3_1110_0011;
wire combo3_1110_0110;
wire combo3_1110_1000;
wire combo3_1110_1010;
wire combo3_1110_1101;
wire combo3_1111_0000;
wire combo3_1111_0001;
wire combo3_1111_0010;
wire combo3_1111_1000;
wire combo3_1111_1001;
wire combo3_1111_1010;
wire combo3_1111_1100;
wire [0:7] e_00_b;
wire [0:7] e_01_b;
wire [0:7] e_02_b;
wire [0:7] e_03_b;
wire [0:7] e_04_b;
wire [0:7] e_05_b;
wire [0:7] e_06_b;
wire [0:7] e_07_b;
wire [0:7] e_08_b;
wire [0:7] e_09_b;
wire [0:7] e_10_b;
wire [0:7] e_11_b;
wire [0:7] e_12_b;
wire [0:7] e_13_b;
wire [0:7] e_14_b;
wire [0:7] e_15_b;
wire [0:7] e_16_b;
wire [0:7] e_17_b;
wire [0:7] e_18_b;
wire [0:7] e_19_b;
wire [0:19] e;
wire [0:7] r_00_b;
wire [0:7] r_01_b;
wire [0:7] r_02_b;
wire [0:7] r_03_b;
wire [0:7] r_04_b;
wire [0:7] r_05_b;
wire [0:7] r_06_b;
wire [0:7] r_07_b;
wire [0:7] r_08_b;
wire [0:7] r_09_b;
wire [0:7] r_10_b;
wire [0:7] r_11_b;
wire [0:7] r_12_b;
wire [0:7] r_13_b;
wire [0:7] r_14_b;
wire [0:14] r;
////#######################################
////## decode the upper 3 index bits
////#######################################
assign dcd_00x = (~f[1]) & (~f[2]);
assign dcd_01x = (~f[1]) & f[2];
assign dcd_10x = f[1] & (~f[2]);
assign dcd_11x = f[1] & f[2];
assign dcd_000 = (~f[3]) & dcd_00x;
assign dcd_001 = f[3] & dcd_00x;
assign dcd_010 = (~f[3]) & dcd_01x;
assign dcd_011 = f[3] & dcd_01x;
assign dcd_100 = (~f[3]) & dcd_10x;
assign dcd_101 = f[3] & dcd_10x;
assign dcd_110 = (~f[3]) & dcd_11x;
assign dcd_111 = f[3] & dcd_11x;
////#######################################
////## combos based on lower 2 index bits
////#######################################
assign combo2_1000 = (~f[5]) & (~f[6]); // [0]
assign combo2_0100 = (~f[5]) & f[6]; // [1]
assign combo2_1100 = (~f[5]); // [0,1]
assign combo2_0010 = f[5] & (~f[6]); // [2]
assign combo2_1010 = (~f[6]); // [0,2]
assign combo2_0110 = f[5] ^ f[6]; // [1,2]
assign combo2_1110 = (~(f[5] & f[6])); // [0,1,2]
assign combo2_0001 = f[5] & f[6]; // [3]
assign combo2_1001 = (~(f[5] ^ f[6])); // [0,3]
assign combo2_0101 = f[6]; // [1,3]
assign combo2_1101 = (~(f[5] & (~f[6]))); // [1,2,3]
assign combo2_0011 = f[5]; // [2,3]
assign combo2_1011 = (~((~f[5]) & f[6])); // [0,2,3]
assign combo2_0111 = (~((~f[5]) & (~f[6]))); // [1,2,3]
////#######################################
////## combos based on lower 3 index bits
////#######################################
assign combo2_1000_xxxx_b = (~((~f[4]) & combo2_1000));
assign combo2_0100_xxxx_b = (~((~f[4]) & combo2_0100));
assign combo2_1100_xxxx_b = (~((~f[4]) & combo2_1100));
assign combo2_0010_xxxx_b = (~((~f[4]) & combo2_0010));
assign combo2_1010_xxxx_b = (~((~f[4]) & combo2_1010));
assign combo2_0110_xxxx_b = (~((~f[4]) & combo2_0110));
assign combo2_1110_xxxx_b = (~((~f[4]) & combo2_1110));
assign combo2_0001_xxxx_b = (~((~f[4]) & combo2_0001));
assign combo2_1001_xxxx_b = (~((~f[4]) & combo2_1001));
assign combo2_0101_xxxx_b = (~((~f[4]) & combo2_0101));
assign combo2_1101_xxxx_b = (~((~f[4]) & combo2_1101));
assign combo2_0011_xxxx_b = (~((~f[4]) & combo2_0011));
assign combo2_1011_xxxx_b = (~((~f[4]) & combo2_1011));
assign combo2_0111_xxxx_b = (~((~f[4]) & combo2_0111));
assign combo2_xxxx_1000_b = (~(f[4] & combo2_1000));
assign combo2_xxxx_0100_b = (~(f[4] & combo2_0100));
assign combo2_xxxx_1100_b = (~(f[4] & combo2_1100));
assign combo2_xxxx_0010_b = (~(f[4] & combo2_0010));
assign combo2_xxxx_1010_b = (~(f[4] & combo2_1010));
assign combo2_xxxx_0110_b = (~(f[4] & combo2_0110));
assign combo2_xxxx_1110_b = (~(f[4] & combo2_1110));
assign combo2_xxxx_0001_b = (~(f[4] & combo2_0001));
assign combo2_xxxx_1001_b = (~(f[4] & combo2_1001));
assign combo2_xxxx_0101_b = (~(f[4] & combo2_0101));
assign combo2_xxxx_1101_b = (~(f[4] & combo2_1101));
assign combo2_xxxx_0011_b = (~(f[4] & combo2_0011));
assign combo2_xxxx_1011_b = (~(f[4] & combo2_1011));
assign combo2_xxxx_0111_b = (~(f[4] & combo2_0111));
assign combo3_0000_0001 = (~(combo2_xxxx_0001_b)); //i=1, 1 1
assign combo3_0000_0011 = (~(combo2_xxxx_0011_b)); //i=3, 5 2
assign combo3_0000_0100 = (~(combo2_xxxx_0100_b)); //i=4, 1 3
assign combo3_0000_0111 = (~(combo2_xxxx_0111_b)); //i=7, 1 4
assign combo3_0000_1001 = (~(combo2_xxxx_1001_b)); //i=9, 1 5
assign combo3_0000_1010 = (~(combo2_xxxx_1010_b)); //i=10, 1 6
assign combo3_0000_1011 = (~(combo2_xxxx_1011_b)); //i=11, 1 7
assign combo3_0000_1101 = (~(combo2_xxxx_1101_b)); //i=13, 2 8
assign combo3_0000_1111 = (~((~f[4]))); //i=15, 1 9
assign combo3_0001_0001 = (~((~combo2_0001))); //i=17, 1 10*
assign combo3_0001_0010 = (~(combo2_0001_xxxx_b & combo2_xxxx_0010_b)); //i=18, 1 11
assign combo3_0001_0100 = (~(combo2_0001_xxxx_b & combo2_xxxx_0100_b)); //i=20, 1 12
assign combo3_0001_0101 = (~(combo2_0001_xxxx_b & combo2_xxxx_0101_b)); //i=21, 2 13
assign combo3_0001_0111 = (~(combo2_0001_xxxx_b & combo2_xxxx_0111_b)); //i=23, 1 14
assign combo3_0001_1000 = (~(combo2_0001_xxxx_b & combo2_xxxx_1000_b)); //i=24, 2 15
assign combo3_0001_1100 = (~(combo2_0001_xxxx_b & combo2_xxxx_1100_b)); //i=28, 4 16
assign combo3_0001_1101 = (~(combo2_0001_xxxx_b & combo2_xxxx_1101_b)); //i=29, 2 17
assign combo3_0001_1110 = (~(combo2_0001_xxxx_b & combo2_xxxx_1110_b)); //i=30, 1 18
assign combo3_0001_1111 = (~(combo2_0001_xxxx_b & (~f[4]))); //i=31, 1 19
assign combo3_0010_0001 = (~(combo2_0010_xxxx_b & combo2_xxxx_0001_b)); //i=33, 1 20
assign combo3_0010_0011 = (~(combo2_0010_xxxx_b & combo2_xxxx_0011_b)); //i=35, 1 21
assign combo3_0010_0100 = (~(combo2_0010_xxxx_b & combo2_xxxx_0100_b)); //i=36, 1 22
assign combo3_0010_0101 = (~(combo2_0010_xxxx_b & combo2_xxxx_0101_b)); //i=37, 1 23
assign combo3_0010_1000 = (~(combo2_0010_xxxx_b & combo2_xxxx_1000_b)); //i=40, 3 24
assign combo3_0010_1001 = (~(combo2_0010_xxxx_b & combo2_xxxx_1001_b)); //i=41, 2 25
assign combo3_0010_1010 = (~(combo2_0010_xxxx_b & combo2_xxxx_1010_b)); //i=42, 1 26
assign combo3_0010_1100 = (~(combo2_0010_xxxx_b & combo2_xxxx_1100_b)); //i=44, 1 27
assign combo3_0010_1101 = (~(combo2_0010_xxxx_b & combo2_xxxx_1101_b)); //i=45, 1 28
assign combo3_0010_1110 = (~(combo2_0010_xxxx_b & combo2_xxxx_1110_b)); //i=46, 1 29
assign combo3_0010_1111 = (~(combo2_0010_xxxx_b & (~f[4]))); //i=47, 1 30
assign combo3_0011_0000 = (~(combo2_0011_xxxx_b)); //i=48, 2 31
assign combo3_0011_0001 = (~(combo2_0011_xxxx_b & combo2_xxxx_0001_b)); //i=49, 1 32
assign combo3_0011_0011 = (~((~combo2_0011))); //i=51, 1 33*
assign combo3_0011_0101 = (~(combo2_0011_xxxx_b & combo2_xxxx_0101_b)); //i=53, 1 34
assign combo3_0011_0110 = (~(combo2_0011_xxxx_b & combo2_xxxx_0110_b)); //i=54, 2 35
assign combo3_0011_1000 = (~(combo2_0011_xxxx_b & combo2_xxxx_1000_b)); //i=56, 1 36
assign combo3_0011_1001 = (~(combo2_0011_xxxx_b & combo2_xxxx_1001_b)); //i=57, 1 37
assign combo3_0011_1110 = (~(combo2_0011_xxxx_b & combo2_xxxx_1110_b)); //i=62, 1 38
assign combo3_0011_1111 = (~(combo2_0011_xxxx_b & (~f[4]))); //i=63, 5 39
assign combo3_0100_0000 = (~(combo2_0100_xxxx_b)); //i=64, 1 40
assign combo3_0100_0010 = (~(combo2_0100_xxxx_b & combo2_xxxx_0010_b)); //i=66, 1 41
assign combo3_0100_0100 = (~((~combo2_0100))); //i=68, 1 42*
assign combo3_0100_0101 = (~(combo2_0100_xxxx_b & combo2_xxxx_0101_b)); //i=69, 1 43
assign combo3_0100_1001 = (~(combo2_0100_xxxx_b & combo2_xxxx_1001_b)); //i=73, 1 44
assign combo3_0100_1100 = (~(combo2_0100_xxxx_b & combo2_xxxx_1100_b)); //i=76, 2 45
assign combo3_0100_1110 = (~(combo2_0100_xxxx_b & combo2_xxxx_1110_b)); //i=78, 1 46
assign combo3_0100_1111 = (~(combo2_0100_xxxx_b & (~f[4]))); //i=79, 1 47
assign combo3_0101_0010 = (~(combo2_0101_xxxx_b & combo2_xxxx_0010_b)); //i=82, 2 48
assign combo3_0101_0100 = (~(combo2_0101_xxxx_b & combo2_xxxx_0100_b)); //i=84, 1 49
assign combo3_0101_0110 = (~(combo2_0101_xxxx_b & combo2_xxxx_0110_b)); //i=86, 4 50
assign combo3_0101_1001 = (~(combo2_0101_xxxx_b & combo2_xxxx_1001_b)); //i=89, 2 51
assign combo3_0101_1100 = (~(combo2_0101_xxxx_b & combo2_xxxx_1100_b)); //i=92, 1 52
assign combo3_0101_1111 = (~(combo2_0101_xxxx_b & (~f[4]))); //i=95, 2 53
assign combo3_0110_0000 = (~(combo2_0110_xxxx_b)); //i=96, 1 54
assign combo3_0110_0011 = (~(combo2_0110_xxxx_b & combo2_xxxx_0011_b)); //i=99, 1 55
assign combo3_0110_0110 = (~((~combo2_0110))); //i=102, 2 56*
assign combo3_0110_0111 = (~(combo2_0110_xxxx_b & combo2_xxxx_0111_b)); //i=103, 1 57
assign combo3_0110_1100 = (~(combo2_0110_xxxx_b & combo2_xxxx_1100_b)); //i=108, 2 58
assign combo3_0110_1101 = (~(combo2_0110_xxxx_b & combo2_xxxx_1101_b)); //i=109, 2 59
assign combo3_0110_1111 = (~(combo2_0110_xxxx_b & (~f[4]))); //i=111, 1 60
assign combo3_0111_0000 = (~(combo2_0111_xxxx_b)); //i=112, 1 61
assign combo3_0111_0101 = (~(combo2_0111_xxxx_b & combo2_xxxx_0101_b)); //i=117, 1 62
assign combo3_0111_0111 = (~((~combo2_0111))); //i=119, 3 63*
assign combo3_0111_1000 = (~(combo2_0111_xxxx_b & combo2_xxxx_1000_b)); //i=120, 1 64
assign combo3_0111_1001 = (~(combo2_0111_xxxx_b & combo2_xxxx_1001_b)); //i=121, 2 65
assign combo3_0111_1010 = (~(combo2_0111_xxxx_b & combo2_xxxx_1010_b)); //i=122, 2 66
assign combo3_0111_1111 = (~(combo2_0111_xxxx_b & (~f[4]))); //i=127, 4 67
assign combo3_1000_0000 = (~(combo2_1000_xxxx_b)); //i=128, 3 68
assign combo3_1000_0011 = (~(combo2_1000_xxxx_b & combo2_xxxx_0011_b)); //i=131, 1 69
assign combo3_1000_0110 = (~(combo2_1000_xxxx_b & combo2_xxxx_0110_b)); //i=134, 1 70
assign combo3_1000_0111 = (~(combo2_1000_xxxx_b & combo2_xxxx_0111_b)); //i=135, 1 71
assign combo3_1000_1010 = (~(combo2_1000_xxxx_b & combo2_xxxx_1010_b)); //i=138, 1 72
assign combo3_1000_1110 = (~(combo2_1000_xxxx_b & combo2_xxxx_1110_b)); //i=142, 2 73
assign combo3_1001_0000 = (~(combo2_1001_xxxx_b)); //i=144, 2 74
assign combo3_1001_0001 = (~(combo2_1001_xxxx_b & combo2_xxxx_0001_b)); //i=145, 1 75
assign combo3_1001_0010 = (~(combo2_1001_xxxx_b & combo2_xxxx_0010_b)); //i=146, 2 76
assign combo3_1001_0100 = (~(combo2_1001_xxxx_b & combo2_xxxx_0100_b)); //i=148, 1 77
assign combo3_1001_0110 = (~(combo2_1001_xxxx_b & combo2_xxxx_0110_b)); //i=150, 1 78
assign combo3_1001_0111 = (~(combo2_1001_xxxx_b & combo2_xxxx_0111_b)); //i=151, 1 79
assign combo3_1001_1000 = (~(combo2_1001_xxxx_b & combo2_xxxx_1000_b)); //i=152, 1 80
assign combo3_1001_1001 = (~((~combo2_1001))); //i=153, 2 81*
assign combo3_1001_1010 = (~(combo2_1001_xxxx_b & combo2_xxxx_1010_b)); //i=154, 1 82
assign combo3_1001_1011 = (~(combo2_1001_xxxx_b & combo2_xxxx_1011_b)); //i=155, 2 83
assign combo3_1001_1100 = (~(combo2_1001_xxxx_b & combo2_xxxx_1100_b)); //i=156, 1 84
assign combo3_1010_0000 = (~(combo2_1010_xxxx_b)); //i=160, 1 85
assign combo3_1010_0001 = (~(combo2_1010_xxxx_b & combo2_xxxx_0001_b)); //i=161, 1 86
assign combo3_1010_0010 = (~(combo2_1010_xxxx_b & combo2_xxxx_0010_b)); //i=162, 1 87
assign combo3_1010_0100 = (~(combo2_1010_xxxx_b & combo2_xxxx_0100_b)); //i=164, 1 88
assign combo3_1010_0101 = (~(combo2_1010_xxxx_b & combo2_xxxx_0101_b)); //i=165, 2 89
assign combo3_1010_0110 = (~(combo2_1010_xxxx_b & combo2_xxxx_0110_b)); //i=166, 1 90
assign combo3_1010_0111 = (~(combo2_1010_xxxx_b & combo2_xxxx_0111_b)); //i=167, 1 91
assign combo3_1010_1001 = (~(combo2_1010_xxxx_b & combo2_xxxx_1001_b)); //i=169, 2 92
assign combo3_1010_1010 = (~((~combo2_1010))); //i=170, 2 93*
assign combo3_1010_1100 = (~(combo2_1010_xxxx_b & combo2_xxxx_1100_b)); //i=172, 2 94
assign combo3_1010_1101 = (~(combo2_1010_xxxx_b & combo2_xxxx_1101_b)); //i=173, 1 95
assign combo3_1010_1111 = (~(combo2_1010_xxxx_b & (~f[4]))); //i=175, 1 96
assign combo3_1011_0001 = (~(combo2_1011_xxxx_b & combo2_xxxx_0001_b)); //i=177, 1 97
assign combo3_1011_0010 = (~(combo2_1011_xxxx_b & combo2_xxxx_0010_b)); //i=178, 1 98
assign combo3_1011_0100 = (~(combo2_1011_xxxx_b & combo2_xxxx_0100_b)); //i=180, 1 99
assign combo3_1011_0101 = (~(combo2_1011_xxxx_b & combo2_xxxx_0101_b)); //i=181, 1 100
assign combo3_1011_1000 = (~(combo2_1011_xxxx_b & combo2_xxxx_1000_b)); //i=184, 1 101
assign combo3_1011_1010 = (~(combo2_1011_xxxx_b & combo2_xxxx_1010_b)); //i=186, 1 102
assign combo3_1011_1100 = (~(combo2_1011_xxxx_b & combo2_xxxx_1100_b)); //i=188, 1 103
assign combo3_1100_0000 = (~(combo2_1100_xxxx_b)); //i=192, 4 104
assign combo3_1100_0001 = (~(combo2_1100_xxxx_b & combo2_xxxx_0001_b)); //i=193, 1 105
assign combo3_1100_0011 = (~(combo2_1100_xxxx_b & combo2_xxxx_0011_b)); //i=195, 1 106
assign combo3_1100_0101 = (~(combo2_1100_xxxx_b & combo2_xxxx_0101_b)); //i=197, 1 107
assign combo3_1100_0110 = (~(combo2_1100_xxxx_b & combo2_xxxx_0110_b)); //i=198, 1 108
assign combo3_1100_0111 = (~(combo2_1100_xxxx_b & combo2_xxxx_0111_b)); //i=199, 1 109
assign combo3_1100_1001 = (~(combo2_1100_xxxx_b & combo2_xxxx_1001_b)); //i=201, 1 110
assign combo3_1100_1010 = (~(combo2_1100_xxxx_b & combo2_xxxx_1010_b)); //i=202, 2 111
assign combo3_1100_1011 = (~(combo2_1100_xxxx_b & combo2_xxxx_1011_b)); //i=203, 3 112
assign combo3_1100_1101 = (~(combo2_1100_xxxx_b & combo2_xxxx_1101_b)); //i=205, 1 113
assign combo3_1100_1111 = (~(combo2_1100_xxxx_b & (~f[4]))); //i=207, 1 114
assign combo3_1101_0010 = (~(combo2_1101_xxxx_b & combo2_xxxx_0010_b)); //i=210, 1 115
assign combo3_1101_0011 = (~(combo2_1101_xxxx_b & combo2_xxxx_0011_b)); //i=211, 2 116
assign combo3_1101_1000 = (~(combo2_1101_xxxx_b & combo2_xxxx_1000_b)); //i=216, 1 117
assign combo3_1101_1001 = (~(combo2_1101_xxxx_b & combo2_xxxx_1001_b)); //i=217, 2 118
assign combo3_1101_1010 = (~(combo2_1101_xxxx_b & combo2_xxxx_1010_b)); //i=218, 2 119
assign combo3_1101_1100 = (~(combo2_1101_xxxx_b & combo2_xxxx_1100_b)); //i=220, 1 120
assign combo3_1101_1110 = (~(combo2_1101_xxxx_b & combo2_xxxx_1110_b)); //i=222, 1 121
assign combo3_1101_1111 = (~(combo2_1101_xxxx_b & (~f[4]))); //i=223, 2 122
assign combo3_1110_0000 = (~(combo2_1110_xxxx_b)); //i=224, 5 123
assign combo3_1110_0001 = (~(combo2_1110_xxxx_b & combo2_xxxx_0001_b)); //i=225, 1 124
assign combo3_1110_0011 = (~(combo2_1110_xxxx_b & combo2_xxxx_0011_b)); //i=227, 2 125
assign combo3_1110_0110 = (~(combo2_1110_xxxx_b & combo2_xxxx_0110_b)); //i=230, 1 126
assign combo3_1110_1000 = (~(combo2_1110_xxxx_b & combo2_xxxx_1000_b)); //i=232, 1 127
assign combo3_1110_1010 = (~(combo2_1110_xxxx_b & combo2_xxxx_1010_b)); //i=234, 1 128
assign combo3_1110_1101 = (~(combo2_1110_xxxx_b & combo2_xxxx_1101_b)); //i=237, 3 129
assign combo3_1111_0000 = (~(f[4])); //i=240, 2 130
assign combo3_1111_0001 = (~(f[4] & combo2_xxxx_0001_b)); //i=241, 1 131
assign combo3_1111_0010 = (~(f[4] & combo2_xxxx_0010_b)); //i=242, 2 132
assign combo3_1111_1000 = (~(f[4] & combo2_xxxx_1000_b)); //i=248, 3 133
assign combo3_1111_1001 = (~(f[4] & combo2_xxxx_1001_b)); //i=249, 2 134
assign combo3_1111_1010 = (~(f[4] & combo2_xxxx_1010_b)); //i=250, 2 135
assign combo3_1111_1100 = (~(f[4] & combo2_xxxx_1100_b)); //i=252, 4 136
////#######################################
////## ESTIMATE VECTORs
////#######################################
assign e_00_b[0] = (~(dcd_000 & tidn));
assign e_00_b[1] = (~(dcd_001 & tidn));
assign e_00_b[2] = (~(dcd_010 & tidn));
assign e_00_b[3] = (~(dcd_011 & tidn));
assign e_00_b[4] = (~(dcd_100 & tidn));
assign e_00_b[5] = (~(dcd_101 & tidn));
assign e_00_b[6] = (~(dcd_110 & tidn));
assign e_00_b[7] = (~(dcd_111 & tidn));
assign e[0] = (~(e_00_b[0] & e_00_b[1] & e_00_b[2] & e_00_b[3] & e_00_b[4] & e_00_b[5] & e_00_b[6] & e_00_b[7]));
assign e_01_b[0] = (~(dcd_000 & tiup));
assign e_01_b[1] = (~(dcd_001 & tiup));
assign e_01_b[2] = (~(dcd_010 & combo3_1100_0000));
assign e_01_b[3] = (~(dcd_011 & tidn));
assign e_01_b[4] = (~(dcd_100 & tidn));
assign e_01_b[5] = (~(dcd_101 & tidn));
assign e_01_b[6] = (~(dcd_110 & tidn));
assign e_01_b[7] = (~(dcd_111 & tidn));
assign e[1] = (~(e_01_b[0] & e_01_b[1] & e_01_b[2] & e_01_b[3] & e_01_b[4] & e_01_b[5] & e_01_b[6] & e_01_b[7]));
assign e_02_b[0] = (~(dcd_000 & combo3_1111_0000));
assign e_02_b[1] = (~(dcd_001 & tidn));
assign e_02_b[2] = (~(dcd_010 & combo3_0011_1111));
assign e_02_b[3] = (~(dcd_011 & tiup));
assign e_02_b[4] = (~(dcd_100 & combo3_1111_1100));
assign e_02_b[5] = (~(dcd_101 & tidn));
assign e_02_b[6] = (~(dcd_110 & tidn));
assign e_02_b[7] = (~(dcd_111 & tidn));
assign e[2] = (~(e_02_b[0] & e_02_b[1] & e_02_b[2] & e_02_b[3] & e_02_b[4] & e_02_b[5] & e_02_b[6] & e_02_b[7]));
assign e_03_b[0] = (~(dcd_000 & combo3_0000_1111));
assign e_03_b[1] = (~(dcd_001 & combo3_1110_0000));
assign e_03_b[2] = (~(dcd_010 & combo3_0011_1111));
assign e_03_b[3] = (~(dcd_011 & combo3_1110_0000));
assign e_03_b[4] = (~(dcd_100 & combo3_0000_0011));
assign e_03_b[5] = (~(dcd_101 & tiup));
assign e_03_b[6] = (~(dcd_110 & combo3_1100_0000));
assign e_03_b[7] = (~(dcd_111 & tidn));
assign e[3] = (~(e_03_b[0] & e_03_b[1] & e_03_b[2] & e_03_b[3] & e_03_b[4] & e_03_b[5] & e_03_b[6] & e_03_b[7]));
assign e_04_b[0] = (~(dcd_000 & combo3_1000_1110));
assign e_04_b[1] = (~(dcd_001 & combo3_0001_1100));
assign e_04_b[2] = (~(dcd_010 & combo3_0011_1110));
assign e_04_b[3] = (~(dcd_011 & combo3_0001_1111));
assign e_04_b[4] = (~(dcd_100 & combo3_0000_0011));
assign e_04_b[5] = (~(dcd_101 & combo3_1110_0000));
assign e_04_b[6] = (~(dcd_110 & combo3_0011_1111));
assign e_04_b[7] = (~(dcd_111 & combo3_1000_0000));
assign e[4] = (~(e_04_b[0] & e_04_b[1] & e_04_b[2] & e_04_b[3] & e_04_b[4] & e_04_b[5] & e_04_b[6] & e_04_b[7]));
assign e_05_b[0] = (~(dcd_000 & combo3_0110_1101));
assign e_05_b[1] = (~(dcd_001 & combo3_1001_1011));
assign e_05_b[2] = (~(dcd_010 & combo3_0011_0001));
assign e_05_b[3] = (~(dcd_011 & combo3_1001_1100));
assign e_05_b[4] = (~(dcd_100 & combo3_1110_0011));
assign e_05_b[5] = (~(dcd_101 & combo3_0001_1110));
assign e_05_b[6] = (~(dcd_110 & combo3_0011_1000));
assign e_05_b[7] = (~(dcd_111 & combo3_0111_1000));
assign e[5] = (~(e_05_b[0] & e_05_b[1] & e_05_b[2] & e_05_b[3] & e_05_b[4] & e_05_b[5] & e_05_b[6] & e_05_b[7]));
assign e_06_b[0] = (~(dcd_000 & combo3_1100_1011));
assign e_06_b[1] = (~(dcd_001 & combo3_0101_0110));
assign e_06_b[2] = (~(dcd_010 & combo3_1010_1101));
assign e_06_b[3] = (~(dcd_011 & combo3_0101_0010));
assign e_06_b[4] = (~(dcd_100 & combo3_1101_0010));
assign e_06_b[5] = (~(dcd_101 & combo3_1101_1001));
assign e_06_b[6] = (~(dcd_110 & combo3_0011_0110));
assign e_06_b[7] = (~(dcd_111 & combo3_0110_0110));
assign e[6] = (~(e_06_b[0] & e_06_b[1] & e_06_b[2] & e_06_b[3] & e_06_b[4] & e_06_b[5] & e_06_b[6] & e_06_b[7]));
assign e_07_b[0] = (~(dcd_000 & combo3_0101_1001));
assign e_07_b[1] = (~(dcd_001 & combo3_1000_0011));
assign e_07_b[2] = (~(dcd_010 & combo3_1111_1000));
assign e_07_b[3] = (~(dcd_011 & combo3_0011_1001));
assign e_07_b[4] = (~(dcd_100 & combo3_1001_1001));
assign e_07_b[5] = (~(dcd_101 & combo3_1011_0100));
assign e_07_b[6] = (~(dcd_110 & combo3_1010_0101));
assign e_07_b[7] = (~(dcd_111 & combo3_0101_0100));
assign e[7] = (~(e_07_b[0] & e_07_b[1] & e_07_b[2] & e_07_b[3] & e_07_b[4] & e_07_b[5] & e_07_b[6] & e_07_b[7]));
assign e_08_b[0] = (~(dcd_000 & combo3_0001_0101));
assign e_08_b[1] = (~(dcd_001 & combo3_0110_0011));
assign e_08_b[2] = (~(dcd_010 & combo3_1111_1001));
assign e_08_b[3] = (~(dcd_011 & combo3_1101_1010));
assign e_08_b[4] = (~(dcd_100 & combo3_1010_1010));
assign e_08_b[5] = (~(dcd_101 & combo3_1101_1001));
assign e_08_b[6] = (~(dcd_110 & combo3_1000_1110));
assign e_08_b[7] = (~(dcd_111 & combo3_0000_0001));
assign e[8] = (~(e_08_b[0] & e_08_b[1] & e_08_b[2] & e_08_b[3] & e_08_b[4] & e_08_b[5] & e_08_b[6] & e_08_b[7]));
assign e_09_b[0] = (~(dcd_000 & combo3_0011_0000));
assign e_09_b[1] = (~(dcd_001 & combo3_1101_0011));
assign e_09_b[2] = (~(dcd_010 & combo3_1111_1010));
assign e_09_b[3] = (~(dcd_011 & combo3_0110_1100));
assign e_09_b[4] = (~(dcd_100 & combo3_0000_0011));
assign e_09_b[5] = (~(dcd_101 & combo3_1011_0101));
assign e_09_b[6] = (~(dcd_110 & combo3_0100_1001));
assign e_09_b[7] = (~(dcd_111 & combo3_1100_0001));
assign e[9] = (~(e_09_b[0] & e_09_b[1] & e_09_b[2] & e_09_b[3] & e_09_b[4] & e_09_b[5] & e_09_b[6] & e_09_b[7]));
assign e_10_b[0] = (~(dcd_000 & combo3_0110_1111));
assign e_10_b[1] = (~(dcd_001 & combo3_0111_1010));
assign e_10_b[2] = (~(dcd_010 & combo3_0001_1100));
assign e_10_b[3] = (~(dcd_011 & combo3_1100_1011));
assign e_10_b[4] = (~(dcd_100 & combo3_0000_0100));
assign e_10_b[5] = (~(dcd_101 & combo3_1101_1111));
assign e_10_b[6] = (~(dcd_110 & combo3_1110_1101));
assign e_10_b[7] = (~(dcd_111 & combo3_1011_0001));
assign e[10] = (~(e_10_b[0] & e_10_b[1] & e_10_b[2] & e_10_b[3] & e_10_b[4] & e_10_b[5] & e_10_b[6] & e_10_b[7]));
assign e_11_b[0] = (~(dcd_000 & combo3_0111_1001));
assign e_11_b[1] = (~(dcd_001 & combo3_1100_1001));
assign e_11_b[2] = (~(dcd_010 & combo3_0010_1000));
assign e_11_b[3] = (~(dcd_011 & combo3_1101_1110));
assign e_11_b[4] = (~(dcd_100 & combo3_1001_1001));
assign e_11_b[5] = (~(dcd_101 & combo3_1001_0000));
assign e_11_b[6] = (~(dcd_110 & combo3_0111_0111));
assign e_11_b[7] = (~(dcd_111 & combo3_0010_1001));
assign e[11] = (~(e_11_b[0] & e_11_b[1] & e_11_b[2] & e_11_b[3] & e_11_b[4] & e_11_b[5] & e_11_b[6] & e_11_b[7]));
assign e_12_b[0] = (~(dcd_000 & combo3_0110_0110));
assign e_12_b[1] = (~(dcd_001 & combo3_0111_0111));
assign e_12_b[2] = (~(dcd_010 & combo3_1100_1010));
assign e_12_b[3] = (~(dcd_011 & combo3_1111_0000));
assign e_12_b[4] = (~(dcd_100 & combo3_0110_1101));
assign e_12_b[5] = (~(dcd_101 & combo3_1011_1000));
assign e_12_b[6] = (~(dcd_110 & combo3_1010_0111));
assign e_12_b[7] = (~(dcd_111 & combo3_0100_0101));
assign e[12] = (~(e_12_b[0] & e_12_b[1] & e_12_b[2] & e_12_b[3] & e_12_b[4] & e_12_b[5] & e_12_b[6] & e_12_b[7]));
assign e_13_b[0] = (~(dcd_000 & combo3_1010_1001));
assign e_13_b[1] = (~(dcd_001 & combo3_0010_1110));
assign e_13_b[2] = (~(dcd_010 & combo3_1011_1010));
assign e_13_b[3] = (~(dcd_011 & combo3_0100_0010));
assign e_13_b[4] = (~(dcd_100 & combo3_1110_1101));
assign e_13_b[5] = (~(dcd_101 & combo3_1010_1100));
assign e_13_b[6] = (~(dcd_110 & combo3_0010_1111));
assign e_13_b[7] = (~(dcd_111 & combo3_0010_1001));
assign e[13] = (~(e_13_b[0] & e_13_b[1] & e_13_b[2] & e_13_b[3] & e_13_b[4] & e_13_b[5] & e_13_b[6] & e_13_b[7]));
assign e_14_b[0] = (~(dcd_000 & combo3_0111_1001));
assign e_14_b[1] = (~(dcd_001 & combo3_0001_1000));
assign e_14_b[2] = (~(dcd_010 & combo3_0100_1100));
assign e_14_b[3] = (~(dcd_011 & combo3_1100_1011));
assign e_14_b[4] = (~(dcd_100 & combo3_1111_0010));
assign e_14_b[5] = (~(dcd_101 & combo3_0101_1111));
assign e_14_b[6] = (~(dcd_110 & combo3_0110_1100));
assign e_14_b[7] = (~(dcd_111 & combo3_0001_0010));
assign e[14] = (~(e_14_b[0] & e_14_b[1] & e_14_b[2] & e_14_b[3] & e_14_b[4] & e_14_b[5] & e_14_b[6] & e_14_b[7]));
assign e_15_b[0] = (~(dcd_000 & combo3_1001_0000));
assign e_15_b[1] = (~(dcd_001 & combo3_1001_0010));
assign e_15_b[2] = (~(dcd_010 & combo3_1101_1010));
assign e_15_b[3] = (~(dcd_011 & combo3_1001_0111));
assign e_15_b[4] = (~(dcd_100 & combo3_0101_1111));
assign e_15_b[5] = (~(dcd_101 & combo3_1001_0001));
assign e_15_b[6] = (~(dcd_110 & combo3_0011_0101));
assign e_15_b[7] = (~(dcd_111 & combo3_1100_0101));
assign e[15] = (~(e_15_b[0] & e_15_b[1] & e_15_b[2] & e_15_b[3] & e_15_b[4] & e_15_b[5] & e_15_b[6] & e_15_b[7]));
assign e_16_b[0] = (~(dcd_000 & combo3_1010_1111));
assign e_16_b[1] = (~(dcd_001 & combo3_0101_1100));
assign e_16_b[2] = (~(dcd_010 & combo3_0100_0000));
assign e_16_b[3] = (~(dcd_011 & combo3_0001_0001));
assign e_16_b[4] = (~(dcd_100 & combo3_0000_1101));
assign e_16_b[5] = (~(dcd_101 & combo3_1100_1111));
assign e_16_b[6] = (~(dcd_110 & combo3_1010_0100));
assign e_16_b[7] = (~(dcd_111 & combo3_0001_1101));
assign e[16] = (~(e_16_b[0] & e_16_b[1] & e_16_b[2] & e_16_b[3] & e_16_b[4] & e_16_b[5] & e_16_b[6] & e_16_b[7]));
assign e_17_b[0] = (~(dcd_000 & combo3_1010_0010));
assign e_17_b[1] = (~(dcd_001 & combo3_1111_0010));
assign e_17_b[2] = (~(dcd_010 & combo3_0101_1001));
assign e_17_b[3] = (~(dcd_011 & combo3_1000_0110));
assign e_17_b[4] = (~(dcd_100 & combo3_1110_0001));
assign e_17_b[5] = (~(dcd_101 & combo3_0010_0011));
assign e_17_b[6] = (~(dcd_110 & combo3_1000_1010));
assign e_17_b[7] = (~(dcd_111 & combo3_1001_0100));
assign e[17] = (~(e_17_b[0] & e_17_b[1] & e_17_b[2] & e_17_b[3] & e_17_b[4] & e_17_b[5] & e_17_b[6] & e_17_b[7]));
assign e_18_b[0] = (~(dcd_000 & combo3_1101_1100));
assign e_18_b[1] = (~(dcd_001 & combo3_0010_1101));
assign e_18_b[2] = (~(dcd_010 & combo3_1100_1010));
assign e_18_b[3] = (~(dcd_011 & combo3_1010_0001));
assign e_18_b[4] = (~(dcd_100 & combo3_1000_0000));
assign e_18_b[5] = (~(dcd_101 & combo3_1011_0010));
assign e_18_b[6] = (~(dcd_110 & combo3_1110_1010));
assign e_18_b[7] = (~(dcd_111 & combo3_0010_1000));
assign e[18] = (~(e_18_b[0] & e_18_b[1] & e_18_b[2] & e_18_b[3] & e_18_b[4] & e_18_b[5] & e_18_b[6] & e_18_b[7]));
assign e_19_b[0] = (~(dcd_000 & tiup));
assign e_19_b[1] = (~(dcd_001 & tiup));
assign e_19_b[2] = (~(dcd_010 & tiup));
assign e_19_b[3] = (~(dcd_011 & tiup));
assign e_19_b[4] = (~(dcd_100 & tiup));
assign e_19_b[5] = (~(dcd_101 & tiup));
assign e_19_b[6] = (~(dcd_110 & tiup));
assign e_19_b[7] = (~(dcd_111 & tiup));
assign e[19] = (~(e_19_b[0] & e_19_b[1] & e_19_b[2] & e_19_b[3] & e_19_b[4] & e_19_b[5] & e_19_b[6] & e_19_b[7]));
////#######################################
////## RANGE VECTORs
////#######################################
assign r_00_b[0] = (~(dcd_000 & tidn));
assign r_00_b[1] = (~(dcd_001 & tidn));
assign r_00_b[2] = (~(dcd_010 & tidn));
assign r_00_b[3] = (~(dcd_011 & tidn));
assign r_00_b[4] = (~(dcd_100 & tidn));
assign r_00_b[5] = (~(dcd_101 & tidn));
assign r_00_b[6] = (~(dcd_110 & tidn));
assign r_00_b[7] = (~(dcd_111 & tidn));
assign r[0] = (~(r_00_b[0] & r_00_b[1] & r_00_b[2] & r_00_b[3] & r_00_b[4] & r_00_b[5] & r_00_b[6] & r_00_b[7]));
assign r_01_b[0] = (~(dcd_000 & tiup));
assign r_01_b[1] = (~(dcd_001 & tiup));
assign r_01_b[2] = (~(dcd_010 & combo3_1000_0000));
assign r_01_b[3] = (~(dcd_011 & tidn));
assign r_01_b[4] = (~(dcd_100 & tidn));
assign r_01_b[5] = (~(dcd_101 & tidn));
assign r_01_b[6] = (~(dcd_110 & tidn));
assign r_01_b[7] = (~(dcd_111 & tidn));
assign r[1] = (~(r_01_b[0] & r_01_b[1] & r_01_b[2] & r_01_b[3] & r_01_b[4] & r_01_b[5] & r_01_b[6] & r_01_b[7]));
assign r_02_b[0] = (~(dcd_000 & tidn));
assign r_02_b[1] = (~(dcd_001 & tidn));
assign r_02_b[2] = (~(dcd_010 & combo3_0111_1111));
assign r_02_b[3] = (~(dcd_011 & tiup));
assign r_02_b[4] = (~(dcd_100 & tiup));
assign r_02_b[5] = (~(dcd_101 & tiup));
assign r_02_b[6] = (~(dcd_110 & tiup));
assign r_02_b[7] = (~(dcd_111 & tiup));
assign r[2] = (~(r_02_b[0] & r_02_b[1] & r_02_b[2] & r_02_b[3] & r_02_b[4] & r_02_b[5] & r_02_b[6] & r_02_b[7]));
assign r_03_b[0] = (~(dcd_000 & combo3_1111_1000));
assign r_03_b[1] = (~(dcd_001 & tidn));
assign r_03_b[2] = (~(dcd_010 & combo3_0111_1111));
assign r_03_b[3] = (~(dcd_011 & tiup));
assign r_03_b[4] = (~(dcd_100 & combo3_1100_0000));
assign r_03_b[5] = (~(dcd_101 & tidn));
assign r_03_b[6] = (~(dcd_110 & tidn));
assign r_03_b[7] = (~(dcd_111 & tidn));
assign r[3] = (~(r_03_b[0] & r_03_b[1] & r_03_b[2] & r_03_b[3] & r_03_b[4] & r_03_b[5] & r_03_b[6] & r_03_b[7]));
assign r_04_b[0] = (~(dcd_000 & combo3_1000_0111));
assign r_04_b[1] = (~(dcd_001 & combo3_1110_0000));
assign r_04_b[2] = (~(dcd_010 & combo3_0111_1111));
assign r_04_b[3] = (~(dcd_011 & tidn));
assign r_04_b[4] = (~(dcd_100 & combo3_0011_1111));
assign r_04_b[5] = (~(dcd_101 & combo3_1111_1100));
assign r_04_b[6] = (~(dcd_110 & tidn));
assign r_04_b[7] = (~(dcd_111 & tidn));
assign r[4] = (~(r_04_b[0] & r_04_b[1] & r_04_b[2] & r_04_b[3] & r_04_b[4] & r_04_b[5] & r_04_b[6] & r_04_b[7]));
assign r_05_b[0] = (~(dcd_000 & combo3_0110_0111));
assign r_05_b[1] = (~(dcd_001 & combo3_0001_1000));
assign r_05_b[2] = (~(dcd_010 & combo3_0111_0000));
assign r_05_b[3] = (~(dcd_011 & combo3_1111_1000));
assign r_05_b[4] = (~(dcd_100 & combo3_0011_1111));
assign r_05_b[5] = (~(dcd_101 & combo3_0000_0011));
assign r_05_b[6] = (~(dcd_110 & combo3_1111_1100));
assign r_05_b[7] = (~(dcd_111 & tidn));
assign r[5] = (~(r_05_b[0] & r_05_b[1] & r_05_b[2] & r_05_b[3] & r_05_b[4] & r_05_b[5] & r_05_b[6] & r_05_b[7]));
assign r_06_b[0] = (~(dcd_000 & combo3_0101_0110));
assign r_06_b[1] = (~(dcd_001 & combo3_1001_0110));
assign r_06_b[2] = (~(dcd_010 & combo3_0100_1100));
assign r_06_b[3] = (~(dcd_011 & combo3_1100_0110));
assign r_06_b[4] = (~(dcd_100 & combo3_0011_0000));
assign r_06_b[5] = (~(dcd_101 & combo3_1110_0011));
assign r_06_b[6] = (~(dcd_110 & combo3_1100_0011));
assign r_06_b[7] = (~(dcd_111 & combo3_1110_0000));
assign r[6] = (~(r_06_b[0] & r_06_b[1] & r_06_b[2] & r_06_b[3] & r_06_b[4] & r_06_b[5] & r_06_b[6] & r_06_b[7]));
assign r_07_b[0] = (~(dcd_000 & combo3_1111_1100));
assign r_07_b[1] = (~(dcd_001 & combo3_1100_1101));
assign r_07_b[2] = (~(dcd_010 & combo3_0010_1010));
assign r_07_b[3] = (~(dcd_011 & combo3_1010_0101));
assign r_07_b[4] = (~(dcd_100 & combo3_0010_1100));
assign r_07_b[5] = (~(dcd_101 & combo3_1001_1011));
assign r_07_b[6] = (~(dcd_110 & combo3_0011_0011));
assign r_07_b[7] = (~(dcd_111 & combo3_1001_1000));
assign r[7] = (~(r_07_b[0] & r_07_b[1] & r_07_b[2] & r_07_b[3] & r_07_b[4] & r_07_b[5] & r_07_b[6] & r_07_b[7]));
assign r_08_b[0] = (~(dcd_000 & combo3_0001_1101));
assign r_08_b[1] = (~(dcd_001 & combo3_0101_0110));
assign r_08_b[2] = (~(dcd_010 & combo3_0111_1111));
assign r_08_b[3] = (~(dcd_011 & combo3_1111_0001));
assign r_08_b[4] = (~(dcd_100 & combo3_1001_1010));
assign r_08_b[5] = (~(dcd_101 & combo3_0101_0010));
assign r_08_b[6] = (~(dcd_110 & combo3_1010_1010));
assign r_08_b[7] = (~(dcd_111 & combo3_0101_0110));
assign r[8] = (~(r_08_b[0] & r_08_b[1] & r_08_b[2] & r_08_b[3] & r_08_b[4] & r_08_b[5] & r_08_b[6] & r_08_b[7]));
assign r_09_b[0] = (~(dcd_000 & combo3_1110_0110));
assign r_09_b[1] = (~(dcd_001 & combo3_0000_1101));
assign r_09_b[2] = (~(dcd_010 & combo3_0110_0000));
assign r_09_b[3] = (~(dcd_011 & combo3_0011_0110));
assign r_09_b[4] = (~(dcd_100 & combo3_1010_1100));
assign r_09_b[5] = (~(dcd_101 & combo3_1100_0111));
assign r_09_b[6] = (~(dcd_110 & tiup));
assign r_09_b[7] = (~(dcd_111 & combo3_0001_1100));
assign r[9] = (~(r_09_b[0] & r_09_b[1] & r_09_b[2] & r_09_b[3] & r_09_b[4] & r_09_b[5] & r_09_b[6] & r_09_b[7]));
assign r_10_b[0] = (~(dcd_000 & combo3_1110_1101));
assign r_10_b[1] = (~(dcd_001 & combo3_0001_0111));
assign r_10_b[2] = (~(dcd_010 & combo3_1101_1000));
assign r_10_b[3] = (~(dcd_011 & combo3_1101_0011));
assign r_10_b[4] = (~(dcd_100 & combo3_1111_1010));
assign r_10_b[5] = (~(dcd_101 & combo3_1010_0110));
assign r_10_b[6] = (~(dcd_110 & combo3_0000_0111));
assign r_10_b[7] = (~(dcd_111 & combo3_0010_0101));
assign r[10] = (~(r_10_b[0] & r_10_b[1] & r_10_b[2] & r_10_b[3] & r_10_b[4] & r_10_b[5] & r_10_b[6] & r_10_b[7]));
assign r_11_b[0] = (~(dcd_000 & combo3_1011_1100));
assign r_11_b[1] = (~(dcd_001 & combo3_1010_0000));
assign r_11_b[2] = (~(dcd_010 & combo3_0111_0111));
assign r_11_b[3] = (~(dcd_011 & combo3_0111_1010));
assign r_11_b[4] = (~(dcd_100 & combo3_0001_1100));
assign r_11_b[5] = (~(dcd_101 & combo3_0001_0101));
assign r_11_b[6] = (~(dcd_110 & combo3_1111_1001));
assign r_11_b[7] = (~(dcd_111 & combo3_0100_1111));
assign r[11] = (~(r_11_b[0] & r_11_b[1] & r_11_b[2] & r_11_b[3] & r_11_b[4] & r_11_b[5] & r_11_b[6] & r_11_b[7]));
assign r_12_b[0] = (~(dcd_000 & combo3_0100_1110));
assign r_12_b[1] = (~(dcd_001 & combo3_0100_0100));
assign r_12_b[2] = (~(dcd_010 & combo3_1101_1111));
assign r_12_b[3] = (~(dcd_011 & combo3_1100_0000));
assign r_12_b[4] = (~(dcd_100 & combo3_0000_1010));
assign r_12_b[5] = (~(dcd_101 & combo3_0010_0001));
assign r_12_b[6] = (~(dcd_110 & combo3_0000_1011));
assign r_12_b[7] = (~(dcd_111 & combo3_1110_1000));
assign r[12] = (~(r_12_b[0] & r_12_b[1] & r_12_b[2] & r_12_b[3] & r_12_b[4] & r_12_b[5] & r_12_b[6] & r_12_b[7]));
assign r_13_b[0] = (~(dcd_000 & combo3_1010_1001));
assign r_13_b[1] = (~(dcd_001 & combo3_0001_0100));
assign r_13_b[2] = (~(dcd_010 & combo3_0111_0101));
assign r_13_b[3] = (~(dcd_011 & combo3_0000_1001));
assign r_13_b[4] = (~(dcd_100 & combo3_0010_1000));
assign r_13_b[5] = (~(dcd_101 & combo3_0000_0011));
assign r_13_b[6] = (~(dcd_110 & combo3_1001_0010));
assign r_13_b[7] = (~(dcd_111 & combo3_0010_0100));
assign r[13] = (~(r_13_b[0] & r_13_b[1] & r_13_b[2] & r_13_b[3] & r_13_b[4] & r_13_b[5] & r_13_b[6] & r_13_b[7]));
assign r_14_b[0] = (~(dcd_000 & tidn));
assign r_14_b[1] = (~(dcd_001 & tidn));
assign r_14_b[2] = (~(dcd_010 & tidn));
assign r_14_b[3] = (~(dcd_011 & tidn));
assign r_14_b[4] = (~(dcd_100 & tidn));
assign r_14_b[5] = (~(dcd_101 & tidn));
assign r_14_b[6] = (~(dcd_110 & tidn));
assign r_14_b[7] = (~(dcd_111 & tidn));
assign r[14] = (~(r_14_b[0] & r_14_b[1] & r_14_b[2] & r_14_b[3] & r_14_b[4] & r_14_b[5] & r_14_b[6] & r_14_b[7]));
////#######################################
////## RENUMBERING OUTPUTS
////#######################################
assign est[1:20] = e[0:19]; // renumbering
assign rng[6:20] = r[0:14]; // renumbering
endmodule |
module fu_nrm(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
f_nrm_si,
f_nrm_so,
ex4_act_b,
f_lza_ex5_lza_amt_cp1,
f_lza_ex5_lza_dcd64_cp1,
f_lza_ex5_lza_dcd64_cp2,
f_lza_ex5_lza_dcd64_cp3,
f_lza_ex5_sh_rgt_en,
f_add_ex5_res,
f_add_ex5_sticky,
f_pic_ex5_byp_prod_nz,
f_nrm_ex6_res,
f_nrm_ex6_int_sign,
f_nrm_ex6_int_lsbs,
f_nrm_ex6_nrm_sticky_dp,
f_nrm_ex6_nrm_guard_dp,
f_nrm_ex6_nrm_lsb_dp,
f_nrm_ex6_nrm_sticky_sp,
f_nrm_ex6_nrm_guard_sp,
f_nrm_ex6_nrm_lsb_sp,
f_nrm_ex6_exact_zero,
f_nrm_ex5_extra_shift,
f_nrm_ex6_fpscr_wr_dat_dfp,
f_nrm_ex6_fpscr_wr_dat
);
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input [4:5] delay_lclkr; // tidn,
input [4:5] mpw1_b; // tidn,
input [0:1] mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input f_nrm_si; // perv
output f_nrm_so; // perv
input ex4_act_b; // act
input [0:7] f_lza_ex5_lza_amt_cp1; // shift amount
input [0:2] f_lza_ex5_lza_dcd64_cp1; //fnrm
input [0:1] f_lza_ex5_lza_dcd64_cp2; //fnrm
input [0:0] f_lza_ex5_lza_dcd64_cp3; //fnrm
input f_lza_ex5_sh_rgt_en;
input [0:162] f_add_ex5_res; // data to shift
input f_add_ex5_sticky; // or into sticky
input f_pic_ex5_byp_prod_nz;
output [0:52] f_nrm_ex6_res; //rnd,
output f_nrm_ex6_int_sign; //rnd, (151:162)
output [1:12] f_nrm_ex6_int_lsbs; //rnd, (151:162)
output f_nrm_ex6_nrm_sticky_dp; //rnd,
output f_nrm_ex6_nrm_guard_dp; //rnd,
output f_nrm_ex6_nrm_lsb_dp; //rnd,
output f_nrm_ex6_nrm_sticky_sp; //rnd,
output f_nrm_ex6_nrm_guard_sp; //rnd,
output f_nrm_ex6_nrm_lsb_sp; //rnd,
output f_nrm_ex6_exact_zero; //rnd,
output f_nrm_ex5_extra_shift; //expo_ov,
output [0:3] f_nrm_ex6_fpscr_wr_dat_dfp; //fpscr, (17:20)
output [0:31] f_nrm_ex6_fpscr_wr_dat; //fpscr, (21:52)
// end ports
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire sg_0;
wire thold_0_b;
wire thold_0;
wire force_t;
wire ex4_act;
wire ex5_act;
wire [0:2] act_spare_unused;
//-----------------
wire [0:3] act_so; //SCAN
wire [0:3] act_si; //SCAN
wire [0:52] ex6_res_so; //SCAN
wire [0:52] ex6_res_si; //SCAN
wire [0:3] ex6_nrm_lg_so; //SCAN
wire [0:3] ex6_nrm_lg_si; //SCAN
wire [0:2] ex6_nrm_x_so; //SCAN
wire [0:2] ex6_nrm_x_si; //SCAN
wire [0:12] ex6_nrm_pass_so; //SCAN
wire [0:12] ex6_nrm_pass_si; //SCAN
wire [0:35] ex6_fmv_so; //SCAN
wire [0:35] ex6_fmv_si; //SCAN
//-----------------
wire [26:72] ex5_sh2;
wire ex5_sh4_25; //shifting
wire ex5_sh4_54; //shifting
wire [0:53] ex5_nrm_res; //shifting
wire [0:53] ex5_sh5_x_b;
wire [0:53] ex5_sh5_y_b;
wire ex5_lt064_x; //sticky
wire ex5_lt128_x; //sticky
wire ex5_lt016_x; //sticky
wire ex5_lt032_x; //sticky
wire ex5_lt048_x; //sticky
wire ex5_lt016; //sticky
wire ex5_lt032; //sticky
wire ex5_lt048; //sticky
wire ex5_lt064; //sticky
wire ex5_lt080; //sticky
wire ex5_lt096; //sticky
wire ex5_lt112; //sticky
wire ex5_lt128; //sticky
wire ex5_lt04_x; //sticky
wire ex5_lt08_x; //sticky
wire ex5_lt12_x; //sticky
wire ex5_lt01_x; //sticky
wire ex5_lt02_x; //sticky
wire ex5_lt03_x; //sticky
wire ex5_sticky_sp; //sticky
wire ex5_sticky_dp; //sticky
wire ex5_sticky16_dp; //sticky
wire ex5_sticky16_sp; //sticky
wire [0:10] ex5_or_grp16; //sticky
wire [0:14] ex5_lt; //sticky
wire ex5_exact_zero; //sticky
wire ex5_exact_zero_b; //sticky
//------------------
wire [0:52] ex6_res; // LATCH OUTPUTS
wire ex6_nrm_sticky_dp;
wire ex6_nrm_guard_dp;
wire ex6_nrm_lsb_dp;
wire ex6_nrm_sticky_sp;
wire ex6_nrm_guard_sp;
wire ex6_nrm_lsb_sp;
wire ex6_exact_zero;
wire ex6_int_sign;
wire [1:12] ex6_int_lsbs;
wire [0:31] ex6_fpscr_wr_dat;
wire [0:3] ex6_fpscr_wr_dat_dfp;
wire ex5_rgt_4more;
wire ex5_rgt_3more;
wire ex5_rgt_2more;
wire ex5_shift_extra_cp2;
wire unused;
wire ex5_sticky_dp_x2_b;
wire ex5_sticky_dp_x1_b;
wire ex5_sticky_dp_x1;
wire ex5_sticky_sp_x2_b;
wire ex5_sticky_sp_x1_b;
wire ex5_sticky_sp_x1;
wire ex6_d1clk;
wire ex6_d2clk;
wire [0:`NCLK_WIDTH-1] ex6_lclk;
wire ex5_sticky_stuff;
// sticky bit sp/dp does not look at all the bits
assign unused = |(ex5_sh2[41:54]) | |(ex5_nrm_res[0:53]) | ex5_sticky_sp | ex5_sticky_dp | ex5_exact_zero;
////############################################
//# pervasive
////############################################
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
tri_lcbnd ex6_lcb(
.delay_lclkr(delay_lclkr[5]), // tidn
.mpw1_b(mpw1_b[5]), // tidn
.mpw2_b(mpw2_b[1]), // tidn
.force_t(force_t), // tidn
.nclk(nclk), //in
.vd(vdd), //inout
.gd(gnd), //inout
.act(ex5_act), //in
.sg(sg_0), //in
.thold_b(thold_0_b), //in
.d1clk(ex6_d1clk), //out
.d2clk(ex6_d2clk), //out
.lclk(ex6_lclk) //out
);
////############################################
//# ACT LATCHES
////############################################
assign ex4_act = (~ex4_act_b);
tri_rlmreg_p #(.WIDTH(4), .NEEDS_SRESET(0)) act_lat(
.force_t(force_t), //i-- tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[4]), //i-- tidn,
.mpw1_b(mpw1_b[4]), //i-- tidn,
.mpw2_b(mpw2_b[0]), //i-- tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable),
.scout(act_so[0:3]),
.scin(act_si[0:3]),
//-----------------
.din({ act_spare_unused[0],
act_spare_unused[1],
ex4_act,
act_spare_unused[2]}),
//-----------------
.dout({ act_spare_unused[0],
act_spare_unused[1],
ex5_act,
act_spare_unused[2]})
);
////##############################################
//# EX5 logic: shifting
////##############################################
fu_nrm_sh sh(
.f_lza_ex5_sh_rgt_en(f_lza_ex5_sh_rgt_en), //i--
.f_lza_ex5_lza_amt_cp1(f_lza_ex5_lza_amt_cp1[2:7]), //i--
.f_lza_ex5_lza_dcd64_cp1(f_lza_ex5_lza_dcd64_cp1[0:2]), //i--
.f_lza_ex5_lza_dcd64_cp2(f_lza_ex5_lza_dcd64_cp2[0:1]), //i--
.f_lza_ex5_lza_dcd64_cp3(f_lza_ex5_lza_dcd64_cp3[0:0]), //i--
.f_add_ex5_res(f_add_ex5_res[0:162]), //i--
.ex5_shift_extra_cp1(f_nrm_ex5_extra_shift), //o-- <30ish> loads feov
.ex5_shift_extra_cp2(ex5_shift_extra_cp2), //o-- <2> loads sticky sp/dp
.ex5_sh4_25(ex5_sh4_25), //o--
.ex5_sh4_54(ex5_sh4_54), //o--
.ex5_sh2_o(ex5_sh2[26:72]), //o--
.ex5_sh5_x_b(ex5_sh5_x_b[0:53]), //o--
.ex5_sh5_y_b(ex5_sh5_y_b[0:53]) //o--
);
assign ex5_nrm_res[0:53] = (~(ex5_sh5_x_b[0:53] & ex5_sh5_y_b[0:53]));
////##############################################
//# EX5 logic: stciky bit
////##############################################
//# thermometer decode 1 ---------------
//#
//# the smaller the shift the more sticky bits.
//# the multiple of 16 shifter is 0:68 ... bits after 68 are known sticky DP.
//# 53-24=29 extra sp bits 68-29 = 39
//# bits after 39 are known sticky SP.
assign ex5_lt064_x = (~(f_lza_ex5_lza_amt_cp1[0] | f_lza_ex5_lza_amt_cp1[1])); // 00
assign ex5_lt128_x = (~(f_lza_ex5_lza_amt_cp1[0])); // 00 01
assign ex5_lt016_x = (~(f_lza_ex5_lza_amt_cp1[2] | f_lza_ex5_lza_amt_cp1[3])); // 00
assign ex5_lt032_x = (~(f_lza_ex5_lza_amt_cp1[2])); // 00 01
assign ex5_lt048_x = (~(f_lza_ex5_lza_amt_cp1[2] & f_lza_ex5_lza_amt_cp1[3])); // 00 01 10
assign ex5_lt016 = ex5_lt064_x & ex5_lt016_x; //tail=067 sticky_dp=069:162 sticky_sp=039:162
assign ex5_lt032 = ex5_lt064_x & ex5_lt032_x; //tail=083 sticky_dp=085:162 sticky_sp=055:162
assign ex5_lt048 = ex5_lt064_x & ex5_lt048_x; //tail=099 sticky_dp=101:162 sticky_sp=071:162
assign ex5_lt064 = ex5_lt064_x; //tail=115 sticky_dp=117:162 sticky_sp=087:162
assign ex5_lt080 = ex5_lt064_x | (ex5_lt128_x & ex5_lt016_x); //tail=131 sticky_dp=133:162 sticky_sp=103:162
assign ex5_lt096 = ex5_lt064_x | (ex5_lt128_x & ex5_lt032_x); //tail=147 sticky_dp=149:162 sticky_sp=119:162
assign ex5_lt112 = ex5_lt064_x | (ex5_lt128_x & ex5_lt048_x); //tail=163 sticky_dp=xxxxxxx sticky_sp=135:162
assign ex5_lt128 = ex5_lt128_x; //tail=179 sticky_dp=xxxxxxx sticky_sp=151:162
// 1111xxxx shift right 1 -> 16 (shift right sticky groups of 16 may be off by one from shift left sticky groups)
// 1110xxxx shift right 17 -> 32
// 1101xxxx shift right 33 -> 48
// 1100xxxx shift right 49 -> 64
// x0xxxxxx shift > 64
// 0xxxxxxx shift > 64
// for shift right Amt[0]==Amt[1]==shRgtEn
// xx00_dddd Right64, then Left00 4 more sticky16 group than 0000_dddd
// xx01_dddd Right64, then Left16 3 more sticky16 group than 0000_dddd
// xx10_dddd Right64, then Left32 2 more sticky16 group than 0000_dddd
// xx11_dddd Right64, then Left48 1 more sticky16 group than 0000_dddd
assign ex5_rgt_2more = f_lza_ex5_sh_rgt_en & ((~f_lza_ex5_lza_amt_cp1[2]) | (~f_lza_ex5_lza_amt_cp1[3])); // 234
assign ex5_rgt_3more = f_lza_ex5_sh_rgt_en & ((~f_lza_ex5_lza_amt_cp1[2])); // 23
assign ex5_rgt_4more = f_lza_ex5_sh_rgt_en & ((~f_lza_ex5_lza_amt_cp1[2]) & (~f_lza_ex5_lza_amt_cp1[3])); // 2
//#------------------------
//# sticky group 16 ors
//#------------------------
fu_nrm_or16 or16(
.f_add_ex5_res(f_add_ex5_res[0:162]), //i--
.ex5_or_grp16(ex5_or_grp16[0:10]) //o--
);
//#------------------------
//# enable the 16 bit ors
//#------------------------
assign ex5_sticky_stuff = (f_pic_ex5_byp_prod_nz) | (f_add_ex5_sticky);
// 71: 86
// 87:102
//103:118
//119:134
//135:150
//151:162
// so group16s match for sp/dp
assign ex5_sticky16_dp = (ex5_or_grp16[1] & ex5_rgt_4more) | (ex5_or_grp16[2] & ex5_rgt_3more) | (ex5_or_grp16[3] & ex5_rgt_2more) | (ex5_or_grp16[4] & f_lza_ex5_sh_rgt_en) | (ex5_or_grp16[5] & (ex5_lt016 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[6] & (ex5_lt032 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[7] & (ex5_lt048 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[8] & (ex5_lt064 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[9] & (ex5_lt080 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[10] & (ex5_lt096 | f_lza_ex5_sh_rgt_en)) | (ex5_sh2[70]) | (ex5_sh2[71]) | (ex5_sh2[72]) | (ex5_sticky_stuff); // so group16s match for sp/dp
// 39: 54
// 55: 70
// 71: 86
// 87:102
//103:118
//119:134
//135:150
assign ex5_sticky16_sp = (ex5_or_grp16[0] & ex5_rgt_3more) | (ex5_or_grp16[1] & ex5_rgt_2more) | (ex5_or_grp16[2] & f_lza_ex5_sh_rgt_en) | (ex5_or_grp16[3] & (ex5_lt016 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[4] & (ex5_lt032 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[5] & (ex5_lt048 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[6] & (ex5_lt064 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[7] & (ex5_lt080 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[8] & (ex5_lt096 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[9] & (ex5_lt112 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[10] & (ex5_lt128 | f_lza_ex5_sh_rgt_en)) | (ex5_sticky_stuff); //151:162
assign ex5_exact_zero_b = ex5_or_grp16[0] | ex5_or_grp16[1] | ex5_or_grp16[2] | ex5_or_grp16[3] | ex5_or_grp16[4] | ex5_or_grp16[5] | ex5_or_grp16[6] | ex5_or_grp16[7] | ex5_or_grp16[8] | ex5_or_grp16[9] | ex5_or_grp16[10] | (ex5_sticky_stuff);
assign ex5_exact_zero = (~ex5_exact_zero_b);
//#------------------------
//# thermometer decode 2
//#------------------------
assign ex5_lt04_x = (~(f_lza_ex5_lza_amt_cp1[4] | f_lza_ex5_lza_amt_cp1[5])); // 00
assign ex5_lt08_x = (~(f_lza_ex5_lza_amt_cp1[4])); // 00 01
assign ex5_lt12_x = (~(f_lza_ex5_lza_amt_cp1[4] & f_lza_ex5_lza_amt_cp1[5])); // 00 01 10
assign ex5_lt01_x = (~(f_lza_ex5_lza_amt_cp1[6] | f_lza_ex5_lza_amt_cp1[7])); // 00
assign ex5_lt02_x = (~(f_lza_ex5_lza_amt_cp1[6])); // 00 01
assign ex5_lt03_x = (~(f_lza_ex5_lza_amt_cp1[6] & f_lza_ex5_lza_amt_cp1[7])); // 00 01 10
assign ex5_lt[0] = ex5_lt04_x & ex5_lt01_x; // 1
assign ex5_lt[1] = ex5_lt04_x & ex5_lt02_x; // 2
assign ex5_lt[2] = ex5_lt04_x & ex5_lt03_x; // 3
assign ex5_lt[3] = ex5_lt04_x; // 4
assign ex5_lt[4] = ex5_lt04_x | (ex5_lt08_x & ex5_lt01_x); // 5
assign ex5_lt[5] = ex5_lt04_x | (ex5_lt08_x & ex5_lt02_x); // 6
assign ex5_lt[6] = ex5_lt04_x | (ex5_lt08_x & ex5_lt03_x); // 7
assign ex5_lt[7] = (ex5_lt08_x); // 8
assign ex5_lt[8] = ex5_lt08_x | (ex5_lt12_x & ex5_lt01_x); // 9
assign ex5_lt[9] = ex5_lt08_x | (ex5_lt12_x & ex5_lt02_x); //10
assign ex5_lt[10] = ex5_lt08_x | (ex5_lt12_x & ex5_lt03_x); //11
assign ex5_lt[11] = (ex5_lt12_x); //12
assign ex5_lt[12] = ex5_lt12_x | ex5_lt01_x; //13
assign ex5_lt[13] = ex5_lt12_x | ex5_lt02_x; //14
assign ex5_lt[14] = ex5_lt12_x | ex5_lt03_x; //15
//#------------------------
//# final sticky bits
//#------------------------
// lt 01
// lt 02
// lt 03
// lt 04
// lt 05
// lt 06
// lt 07
// lt 08
// lt 09
// lt 10
// lt 11
// lt 12
// lt 13
// lt 14
assign ex5_sticky_sp_x1 = (ex5_lt[14] & ex5_sh2[40]) | (ex5_lt[13] & ex5_sh2[39]) | (ex5_lt[12] & ex5_sh2[38]) | (ex5_lt[11] & ex5_sh2[37]) | (ex5_lt[10] & ex5_sh2[36]) | (ex5_lt[9] & ex5_sh2[35]) | (ex5_lt[8] & ex5_sh2[34]) | (ex5_lt[7] & ex5_sh2[33]) | (ex5_lt[6] & ex5_sh2[32]) | (ex5_lt[5] & ex5_sh2[31]) | (ex5_lt[4] & ex5_sh2[30]) | (ex5_lt[3] & ex5_sh2[29]) | (ex5_lt[2] & ex5_sh2[28]) | (ex5_lt[1] & ex5_sh2[27]) | (ex5_lt[0] & ex5_sh2[26]) | (ex5_sticky16_sp); // lt 15
assign ex5_sticky_sp_x2_b = (~((~ex5_shift_extra_cp2) & ex5_sh4_25));
assign ex5_sticky_sp_x1_b = (~ex5_sticky_sp_x1);
assign ex5_sticky_sp = (~(ex5_sticky_sp_x1_b & ex5_sticky_sp_x2_b));
// lt 01
// lt 02
// lt 03
// lt 04
// lt 05
// lt 06
// lt 07
// lt 08
// lt 09
// lt 10
// lt 11
// lt 12
// lt 13
// lt 14
assign ex5_sticky_dp_x1 = (ex5_lt[14] & ex5_sh2[69]) | (ex5_lt[13] & ex5_sh2[68]) | (ex5_lt[12] & ex5_sh2[67]) | (ex5_lt[11] & ex5_sh2[66]) | (ex5_lt[10] & ex5_sh2[65]) | (ex5_lt[9] & ex5_sh2[64]) | (ex5_lt[8] & ex5_sh2[63]) | (ex5_lt[7] & ex5_sh2[62]) | (ex5_lt[6] & ex5_sh2[61]) | (ex5_lt[5] & ex5_sh2[60]) | (ex5_lt[4] & ex5_sh2[59]) | (ex5_lt[3] & ex5_sh2[58]) | (ex5_lt[2] & ex5_sh2[57]) | (ex5_lt[1] & ex5_sh2[56]) | (ex5_lt[0] & ex5_sh2[55]) | (ex5_sticky16_dp); // lt 15
assign ex5_sticky_dp_x2_b = (~((~ex5_shift_extra_cp2) & ex5_sh4_54));
assign ex5_sticky_dp_x1_b = (~ex5_sticky_dp_x1);
assign ex5_sticky_dp = (~(ex5_sticky_dp_x1_b & ex5_sticky_dp_x2_b));
////##############################################
//# EX6 latches
////##############################################
// , ibuf => true,
tri_nand2_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex6_res_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_res_si),
.scanout(ex6_res_so),
.a1(ex5_sh5_x_b[0:52]),
.a2(ex5_sh5_y_b[0:52]),
.qb(ex6_res[0:52]) //LAT--
);
// , ibuf => true,
tri_nand2_nlats #(.WIDTH(4), .NEEDS_SRESET(0)) ex6_nrm_lg_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_nrm_lg_si),
.scanout(ex6_nrm_lg_so),
//-----------------
.a1({ex5_sh5_x_b[23],
ex5_sh5_x_b[24],
ex5_sh5_x_b[52],
ex5_sh5_x_b[53]}),
//-----------------
.a2({ex5_sh5_y_b[23],
ex5_sh5_y_b[24],
ex5_sh5_y_b[52],
ex5_sh5_y_b[53]}),
//-----------------
.qb({ex6_nrm_lsb_sp, //LAT-- --sp lsb
ex6_nrm_guard_sp, //LAT-- --sp guard
ex6_nrm_lsb_dp, //LAT-- --dp lsb
ex6_nrm_guard_dp}) //LAT-- --dp guard
);
// , ibuf => true,
tri_nand2_nlats #(.WIDTH(3), .NEEDS_SRESET(0)) ex6_nrm_x_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_nrm_x_si),
.scanout(ex6_nrm_x_so),
//-----------------
.a1({ ex5_sticky_sp_x2_b,
ex5_sticky_dp_x2_b,
ex5_exact_zero_b}),
//-----------------
.a2({ ex5_sticky_sp_x1_b,
ex5_sticky_dp_x1_b,
tiup}),
//-----------------
.qb({ ex6_nrm_sticky_sp, //LAT--
ex6_nrm_sticky_dp, //LAT--
ex6_exact_zero}) //LAT--
);
tri_rlmreg_p #(.WIDTH(13), .IBUF(1'B1), .NEEDS_SRESET(0)) ex6_nrm_pass_lat(
.force_t(force_t), //i-- tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[5]), //i-- tidn,
.mpw1_b(mpw1_b[5]), //i-- tidn,
.mpw2_b(mpw2_b[1]), //i-- tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex5_act),
.scout(ex6_nrm_pass_so),
.scin(ex6_nrm_pass_si),
//-----------------
.din({f_add_ex5_res[99],
f_add_ex5_res[151:162]}), // (151:162)
//-----------------
.dout({ex6_int_sign, //LAT--
ex6_int_lsbs[1:12]}) //LAT-- --(151:162)
);
tri_rlmreg_p #(.WIDTH(36), .IBUF(1'B1), .NEEDS_SRESET(1)) ex6_fmv_lat(
.force_t(force_t), //i-- tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[5]), //i-- tidn,
.mpw1_b(mpw1_b[5]), //i-- tidn,
.mpw2_b(mpw2_b[1]), //i-- tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex5_act),
.scout(ex6_fmv_so),
.scin(ex6_fmv_si),
//-----------------
.din(f_add_ex5_res[17:52]), //LAT
//-----------------
.dout({ex6_fpscr_wr_dat_dfp[0:3],
ex6_fpscr_wr_dat[0:31]}) //LAT
);
assign f_nrm_ex6_res = ex6_res[0:52]; //output--rnd
assign f_nrm_ex6_nrm_lsb_sp = ex6_nrm_lsb_sp; //output--rnd
assign f_nrm_ex6_nrm_guard_sp = ex6_nrm_guard_sp; //output--rnd
assign f_nrm_ex6_nrm_sticky_sp = ex6_nrm_sticky_sp; //output--rnd
assign f_nrm_ex6_nrm_lsb_dp = ex6_nrm_lsb_dp; //output--rnd
assign f_nrm_ex6_nrm_guard_dp = ex6_nrm_guard_dp; //output--rnd
assign f_nrm_ex6_nrm_sticky_dp = ex6_nrm_sticky_dp; //output--rnd
assign f_nrm_ex6_exact_zero = ex6_exact_zero; //output--rnd
assign f_nrm_ex6_int_lsbs = ex6_int_lsbs[1:12]; //output--rnd (151:162)
assign f_nrm_ex6_fpscr_wr_dat = ex6_fpscr_wr_dat[0:31]; //output--fpscr, (21:52)
assign f_nrm_ex6_fpscr_wr_dat_dfp = ex6_fpscr_wr_dat_dfp[0:3]; //output--fpscr (17:20)
assign f_nrm_ex6_int_sign = ex6_int_sign; //output--rnd (151:162)
////############################################
//# scan
////############################################
assign act_si[0:3] = {act_so[1:3], f_nrm_si};
assign ex6_res_si[0:52] = {ex6_res_so[1:52], act_so[0]};
assign ex6_nrm_lg_si[0:3] = {ex6_nrm_lg_so[1:3], ex6_res_so[0]};
assign ex6_nrm_x_si[0:2] = {ex6_nrm_x_so[1:2], ex6_nrm_lg_so[0]};
assign ex6_nrm_pass_si[0:12] = {ex6_nrm_pass_so[1:12], ex6_nrm_x_so[0]};
assign ex6_fmv_si[0:35] = {ex6_fmv_so[1:35], ex6_nrm_pass_so[0]};
assign f_nrm_so = ex6_fmv_so[0];
endmodule |
module fu_lze(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
f_lze_si,
f_lze_so,
ex2_act_b,
f_eie_ex3_lzo_expo,
f_eie_ex3_b_expo,
f_eie_ex3_use_bexp,
f_pic_ex3_lzo_dis_prod,
f_pic_ex3_sp_lzo,
f_pic_ex3_est_recip,
f_pic_ex3_est_rsqrt,
f_fmt_ex3_pass_msb_dp,
f_pic_ex3_frsp_ue1,
f_alg_ex3_byp_nonflip,
f_pic_ex3_b_valid,
f_alg_ex3_sel_byp,
f_pic_ex3_to_integer,
f_pic_ex3_prenorm,
f_lze_ex3_lzo_din,
f_lze_ex4_sh_rgt_amt,
f_lze_ex4_sh_rgt_en
);
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input [2:3] delay_lclkr; // tidn,
input [2:3] mpw1_b; // tidn,
input [0:0] mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input f_lze_si; //perv
output f_lze_so; //perv
input ex2_act_b; //act
input [1:13] f_eie_ex3_lzo_expo;
input [1:13] f_eie_ex3_b_expo;
input f_eie_ex3_use_bexp;
input f_pic_ex3_lzo_dis_prod;
input f_pic_ex3_sp_lzo;
input f_pic_ex3_est_recip;
input f_pic_ex3_est_rsqrt;
input f_fmt_ex3_pass_msb_dp;
input f_pic_ex3_frsp_ue1;
input f_alg_ex3_byp_nonflip;
input f_pic_ex3_b_valid;
input f_alg_ex3_sel_byp;
input f_pic_ex3_to_integer;
input f_pic_ex3_prenorm;
output [0:162] f_lze_ex3_lzo_din;
output [0:7] f_lze_ex4_sh_rgt_amt;
output f_lze_ex4_sh_rgt_en;
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire thold_0_b;
wire thold_0;
wire force_t;
wire sg_0;
wire ex2_act;
wire ex3_act;
(* analysis_not_referenced="TRUE" *) // spare_unused
wire [0:3] spare_unused;
wire ex3_dp_001_by;
wire ex3_sp_001_by;
wire ex3_addr_dp_by;
wire ex3_addr_sp_by;
wire ex3_en_addr_dp_by;
wire ex3_en_addr_sp_by;
wire ex3_lzo_en;
wire ex3_lzo_en_rapsp;
wire ex3_lzo_en_by;
wire ex3_expo_neg_dp_by;
wire ex3_expo_neg_sp_by;
wire ex3_expo_6_adj_by;
wire ex3_addr_dp;
wire ex3_addr_sp;
wire ex3_addr_sp_rap;
wire ex3_en_addr_dp;
wire ex3_en_addr_sp;
wire ex3_en_addr_sp_rap;
wire ex3_lzo_cont;
wire ex3_lzo_cont_dp;
wire ex3_lzo_cont_sp;
wire ex3_expo_neg_dp;
wire ex3_expo_neg_sp;
wire ex3_expo_6_adj;
wire ex3_ins_est;
wire ex3_sh_rgt_en_by;
wire ex3_sh_rgt_en_p;
wire ex3_sh_rgt_en;
wire ex3_lzo_forbyp_0;
wire ex3_lzo_nonbyp_0;
wire ex4_sh_rgt_en;
wire [1:13] ex3_expo_by;
wire [0:0] ex3_lzo_dcd_hi_by;
wire [0:0] ex3_lzo_dcd_lo_by;
wire [1:13] ex3_expo;
wire [0:10] ex3_lzo_dcd_hi;
wire [0:15] ex3_lzo_dcd_lo;
wire [8:13] ex3_expo_p_sim_p;
wire [9:13] ex3_expo_p_sim_g;
wire [8:13] ex3_expo_p_sim;
wire [8:13] ex3_expo_sim_p;
wire [9:13] ex3_expo_sim_g;
wire [8:13] ex3_expo_sim;
wire [0:7] ex3_sh_rgt_amt;
wire [0:8] ex4_shr_so;
wire [0:8] ex4_shr_si;
wire [0:4] act_so;
wire [0:4] act_si;
wire [0:7] ex4_sh_rgt_amt;
wire ex3_lzo_dcd_0;
wire [0:162] ex3_lzo_dcd_b;
(* analysis_not_referenced="TRUE" *) // unused
wire unused;
wire f_alg_ex3_sel_byp_b;
wire ex3_lzo_nonbyp_0_b;
wire ex3_lzo_forbyp_0_b;
//-=###############################################################
//-= map block attributes
//-=###############################################################
assign unused = ex3_lzo_dcd_b[0];
//-=###############################################################
//-= pervasive
//-=###############################################################
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
//-=###############################################################
//-= act
//-=###############################################################
assign ex2_act = (~ex2_act_b);
tri_rlmreg_p #(.WIDTH(5), .NEEDS_SRESET(0)) act_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[2]), // tidn,
.mpw1_b(mpw1_b[2]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(fpu_enable),
.thold_b(thold_0_b),
.sg(sg_0),
.scout(act_so),
.scin(act_si),
//-----------------
.din({ spare_unused[0],
spare_unused[1],
ex2_act,
spare_unused[2],
spare_unused[3]}),
//-----------------
.dout({ spare_unused[0],
spare_unused[1],
ex3_act,
spare_unused[2],
spare_unused[3]})
);
//-=###############################################################
//-= ex3 logic
//-=###############################################################
assign ex3_dp_001_by = (~ex3_expo_by[1]) & (~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[4]) & (~ex3_expo_by[5]) & (~ex3_expo_by[6]) & (~ex3_expo_by[7]) & (~ex3_expo_by[8]) & (~ex3_expo_by[9]) & (~ex3_expo_by[10]) & (~ex3_expo_by[11]) & (~ex3_expo_by[12]) & ex3_expo_by[13]; //x001
assign ex3_sp_001_by = (~ex3_expo_by[1]) & (~ex3_expo_by[2]) & (~ex3_expo_by[3]) & ex3_expo_by[4] & ex3_expo_by[5] & ex3_expo_by[6] & (~ex3_expo_by[7]) & (~ex3_expo_by[8]) & (~ex3_expo_by[9]) & (~ex3_expo_by[10]) & (~ex3_expo_by[11]) & (~ex3_expo_by[12]) & ex3_expo_by[13]; //x381
//----------------------------------------------------------------
// lzo dcd when B = denorm.
// sp denorm in dp_format may need to denormalize.
// sp is bypassed at [26] so there is room to do this on the left
//----------------------------------------------------------------
// if B is normalized when bypassed, then no need for denorm because it will not shift left ?
// for EffSub, b MSB can move right 1 position ... only if BFrac = 0000111111,can't if bypass norm
// If B==0 then should NOT bypass ... except for Move instructions.
assign ex3_expo_by[1:13] = f_eie_ex3_b_expo[1:13];
//=#------------------------------------------------
//=#-- LZO Decode
//=#------------------------------------------------
// the product exponent points at [0] in the dataflow.
// the lzo puts a marker (false edge) at the point where shifting must stop
// so the lza will not create a denormal exponent. (001/897) dp/sp.
// if p_expo==1 then maker @ 0
// if p_expo==2 then maker @ 1
// if p_expo==3 then maker @ 2
//
// false edges are also used to control shifting for to-integer, aligner-bypass
assign ex3_addr_dp_by = (~ex3_expo_by[1]) & (~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[4]) & (~ex3_expo_by[5]); // x001 (1) in bits above decode 256
assign ex3_addr_sp_by = (~ex3_expo_by[1]) & (~ex3_expo_by[2]) & (~ex3_expo_by[3]) & ex3_expo_by[4] & ex3_expo_by[5]; // x381 (897) in bits above decode 256
assign ex3_en_addr_dp_by = ex3_addr_dp_by & ex3_lzo_cont_dp;
assign ex3_en_addr_sp_by = ex3_addr_sp_by & ex3_lzo_cont_sp;
// want to avoid shift right for sp op with shOv of sp_den in dp format
// sp is bypassed 26 positions to the left , mark with LZO to create the denorm.
assign ex3_lzo_en_by = (ex3_en_addr_dp_by | ex3_en_addr_sp_by) & ex3_lzo_cont;
//decode 0
assign ex3_expo_neg_dp_by = (ex3_lzo_en_by & ex3_lzo_dcd_hi_by[0] & ex3_lzo_dcd_lo_by[0]) | (ex3_expo_by[1]); //negative exponent
// dp denorm starts at 0, but sp denorm starts at 896 (x380)
// sp addr 0_0011_xxxx_xxxx covers 0768-1023 <and with decode bits>
// 0_000x_xxxx_xxxx covers 0000,0001
// 0_00x0_xxxx_xxxx covers 0000,0010
assign ex3_expo_neg_sp_by = (ex3_expo_by[1]) | ((~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[4])) | ((~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[5])) | ((~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[6])) | ((~ex3_expo_by[2]) & (~ex3_expo_by[3]) & ex3_expo_by[4] & ex3_expo_by[5] & ex3_expo_by[6] & (~(ex3_expo_by[7] | ex3_expo_by[8] | ex3_expo_by[9] | ex3_expo_by[10] | ex3_expo_by[11] | ex3_expo_by[12] | ex3_expo_by[13]))); // negative
assign ex3_expo_6_adj_by = ((~ex3_expo_by[6]) & f_pic_ex3_sp_lzo) | (ex3_expo_by[6] & (~f_pic_ex3_sp_lzo));
assign ex3_lzo_dcd_0 = ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[1];
assign ex3_lzo_dcd_hi_by[0] = (~ex3_expo_6_adj_by) & (~ex3_expo_by[7]) & (~ex3_expo_by[8]) & (~ex3_expo_by[9]) & ex3_lzo_en_by;
assign ex3_lzo_dcd_lo_by[0] = (~ex3_expo_by[10]) & (~ex3_expo_by[11]) & (~ex3_expo_by[12]) & (~ex3_expo_by[13]);
//=#------------------------------------------------
//=#-- LZO Decode
//=#------------------------------------------------
// the product exponent points at [0] in the dataflow.
// the lzo puts a marker (false edge) at the point where shifting must stop
// so the lza will not create a denormal exponent. (001/897) dp/sp.
// if p_expo==1 then maker @ 0
// if p_expo==2 then maker @ 1
// if p_expo==3 then maker @ 2
//
// false edges are also used to control shifting for to-integer, aligner-bypass
assign ex3_expo[1:13] = f_eie_ex3_lzo_expo[1:13];
assign ex3_addr_dp = (~ex3_expo[1]) & (~ex3_expo[2]) & (~ex3_expo[3]) & (~ex3_expo[4]) & (~ex3_expo[5]); // x001 (1) in bits above decode 256
assign ex3_addr_sp = (~ex3_expo[1]) & (~ex3_expo[2]) & (~ex3_expo[3]) & ex3_expo[4] & ex3_expo[5]; // x381 (897) in bits above decode 256
assign ex3_addr_sp_rap = (~ex3_expo[1]) & (~ex3_expo[2]) & ex3_expo[3] & (~ex3_expo[4]) & (~ex3_expo[5]); // x381 (897) in bits above decode 256
assign ex3_en_addr_dp = ex3_addr_dp & ex3_lzo_cont_dp;
assign ex3_en_addr_sp = ex3_addr_sp & ex3_lzo_cont_sp;
assign ex3_en_addr_sp_rap = ex3_addr_sp_rap & ex3_lzo_cont_sp;
assign ex3_lzo_cont = (~f_pic_ex3_lzo_dis_prod);
assign ex3_lzo_cont_dp = (~f_pic_ex3_lzo_dis_prod) & (~f_pic_ex3_sp_lzo);
assign ex3_lzo_cont_sp = (~f_pic_ex3_lzo_dis_prod) & f_pic_ex3_sp_lzo;
// want to avoid shift right for sp op with shOv of sp_den in dp format
// sp is bypassed 26 positions to the left , mark with LZO to create the denorm.
assign ex3_lzo_en = (ex3_en_addr_dp | ex3_en_addr_sp) & ex3_lzo_cont;
assign ex3_lzo_en_rapsp = (ex3_en_addr_dp | ex3_en_addr_sp_rap) & ex3_lzo_cont;
//decode 0
assign ex3_expo_neg_dp = (ex3_lzo_en & ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[0]) | (ex3_expo[1]); //negative exponent
// dp denorm starts at 0, but sp denorm starts at 896 (x380)
// sp addr 0_0011_xxxx_xxxx covers 0768-1023 <and with decode bits>
// 0_000x_xxxx_xxxx covers 0000,0001
// 0_00x0_xxxx_xxxx covers 0000,0010
assign ex3_expo_neg_sp = (ex3_expo[1]) | ((~ex3_expo[2]) & (~ex3_expo[3]) & (~ex3_expo[4])) | ((~ex3_expo[2]) & (~ex3_expo[3]) & (~ex3_expo[5])) | ((~ex3_expo[2]) & (~ex3_expo[3]) & (~ex3_expo[6])) | ((~ex3_expo[2]) & (~ex3_expo[3]) & ex3_expo[4] & ex3_expo[5] & ex3_expo[6] & (~(ex3_expo[7] | ex3_expo[8] | ex3_expo[9] | ex3_expo[10] | ex3_expo[11] | ex3_expo[12] | ex3_expo[13]))); // negative
assign ex3_expo_6_adj = ((~ex3_expo[6]) & f_pic_ex3_sp_lzo) | (ex3_expo[6] & (~f_pic_ex3_sp_lzo));
assign ex3_lzo_dcd_hi[0] = (~ex3_expo_6_adj) & (~ex3_expo[7]) & (~ex3_expo[8]) & (~ex3_expo[9]) & ex3_lzo_en;
assign ex3_lzo_dcd_hi[1] = (~ex3_expo_6_adj) & (~ex3_expo[7]) & (~ex3_expo[8]) & ex3_expo[9] & ex3_lzo_en;
assign ex3_lzo_dcd_hi[2] = (~ex3_expo_6_adj) & (~ex3_expo[7]) & ex3_expo[8] & (~ex3_expo[9]) & ex3_lzo_en;
assign ex3_lzo_dcd_hi[3] = (~ex3_expo_6_adj) & (~ex3_expo[7]) & ex3_expo[8] & ex3_expo[9] & ex3_lzo_en;
assign ex3_lzo_dcd_hi[4] = (~ex3_expo_6_adj) & ex3_expo[7] & (~ex3_expo[8]) & (~ex3_expo[9]) & ex3_lzo_en;
assign ex3_lzo_dcd_hi[5] = (~ex3_expo_6_adj) & ex3_expo[7] & (~ex3_expo[8]) & ex3_expo[9] & ex3_lzo_en;
assign ex3_lzo_dcd_hi[6] = (~ex3_expo_6_adj) & ex3_expo[7] & ex3_expo[8] & (~ex3_expo[9]) & ex3_lzo_en;
assign ex3_lzo_dcd_hi[7] = (~ex3_expo_6_adj) & ex3_expo[7] & ex3_expo[8] & ex3_expo[9] & ex3_lzo_en;
assign ex3_lzo_dcd_hi[8] = ex3_expo_6_adj & (~ex3_expo[7]) & (~ex3_expo[8]) & (~ex3_expo[9]) & ex3_lzo_en_rapsp;
assign ex3_lzo_dcd_hi[9] = ex3_expo_6_adj & (~ex3_expo[7]) & (~ex3_expo[8]) & ex3_expo[9] & ex3_lzo_en_rapsp;
assign ex3_lzo_dcd_hi[10] = ex3_expo_6_adj & (~ex3_expo[7]) & ex3_expo[8] & (~ex3_expo[9]) & ex3_lzo_en_rapsp;
assign ex3_lzo_dcd_lo[0] = (~ex3_expo[10]) & (~ex3_expo[11]) & (~ex3_expo[12]) & (~ex3_expo[13]);
assign ex3_lzo_dcd_lo[1] = (~ex3_expo[10]) & (~ex3_expo[11]) & (~ex3_expo[12]) & ex3_expo[13];
assign ex3_lzo_dcd_lo[2] = (~ex3_expo[10]) & (~ex3_expo[11]) & ex3_expo[12] & (~ex3_expo[13]);
assign ex3_lzo_dcd_lo[3] = (~ex3_expo[10]) & (~ex3_expo[11]) & ex3_expo[12] & ex3_expo[13];
assign ex3_lzo_dcd_lo[4] = (~ex3_expo[10]) & ex3_expo[11] & (~ex3_expo[12]) & (~ex3_expo[13]);
assign ex3_lzo_dcd_lo[5] = (~ex3_expo[10]) & ex3_expo[11] & (~ex3_expo[12]) & ex3_expo[13];
assign ex3_lzo_dcd_lo[6] = (~ex3_expo[10]) & ex3_expo[11] & ex3_expo[12] & (~ex3_expo[13]);
assign ex3_lzo_dcd_lo[7] = (~ex3_expo[10]) & ex3_expo[11] & ex3_expo[12] & ex3_expo[13];
assign ex3_lzo_dcd_lo[8] = ex3_expo[10] & (~ex3_expo[11]) & (~ex3_expo[12]) & (~ex3_expo[13]);
assign ex3_lzo_dcd_lo[9] = ex3_expo[10] & (~ex3_expo[11]) & (~ex3_expo[12]) & ex3_expo[13];
assign ex3_lzo_dcd_lo[10] = ex3_expo[10] & (~ex3_expo[11]) & ex3_expo[12] & (~ex3_expo[13]);
assign ex3_lzo_dcd_lo[11] = ex3_expo[10] & (~ex3_expo[11]) & ex3_expo[12] & ex3_expo[13];
assign ex3_lzo_dcd_lo[12] = ex3_expo[10] & ex3_expo[11] & (~ex3_expo[12]) & (~ex3_expo[13]);
assign ex3_lzo_dcd_lo[13] = ex3_expo[10] & ex3_expo[11] & (~ex3_expo[12]) & ex3_expo[13];
assign ex3_lzo_dcd_lo[14] = ex3_expo[10] & ex3_expo[11] & ex3_expo[12] & (~ex3_expo[13]);
assign ex3_lzo_dcd_lo[15] = ex3_expo[10] & ex3_expo[11] & ex3_expo[12] & ex3_expo[13];
assign ex3_lzo_dcd_b[0] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[1] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[2] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[3] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[4] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[5] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[6] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[7] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[8] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[9] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[10] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[11] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[12] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[13] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[14] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[15] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[16] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[17] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[18] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[19] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[20] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[21] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[22] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[23] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[24] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[25] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[26] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[27] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[28] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[29] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[30] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[31] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[32] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[33] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[34] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[35] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[36] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[37] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[38] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[39] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[40] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[41] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[42] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[43] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[44] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[45] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[46] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[47] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[48] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[49] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[50] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[51] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[52] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[53] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[54] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[55] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[56] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[57] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[58] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[59] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[60] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[61] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[62] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[63] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[64] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[65] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[66] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[67] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[68] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[69] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[70] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[71] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[72] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[73] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[74] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[75] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[76] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[77] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[78] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[79] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[80] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[81] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[82] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[83] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[84] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[85] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[86] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[87] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[88] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[89] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[90] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[91] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[92] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[93] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[94] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[95] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[96] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[97] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[98] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[99] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[100] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[101] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[102] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[103] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[104] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[105] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[106] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[107] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[108] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[109] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[110] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[111] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[112] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[113] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[114] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[115] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[116] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[117] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[118] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[119] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[120] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[121] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[122] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[123] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[124] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[125] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[126] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[127] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[128] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[129] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[130] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[131] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[132] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[133] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[134] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[135] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[136] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[137] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[138] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[139] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[140] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[141] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[142] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[143] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[144] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[145] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[146] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[3]));
assign ex3_lzo_dcd_b[147] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[4]));
assign ex3_lzo_dcd_b[148] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[5]));
assign ex3_lzo_dcd_b[149] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[6]));
assign ex3_lzo_dcd_b[150] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[7]));
assign ex3_lzo_dcd_b[151] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[8]));
assign ex3_lzo_dcd_b[152] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[9]));
assign ex3_lzo_dcd_b[153] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[10]));
assign ex3_lzo_dcd_b[154] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[11]));
assign ex3_lzo_dcd_b[155] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[12]));
assign ex3_lzo_dcd_b[156] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[13]));
assign ex3_lzo_dcd_b[157] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[14]));
assign ex3_lzo_dcd_b[158] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[15]));
assign ex3_lzo_dcd_b[159] = (~(ex3_lzo_dcd_hi[10] & ex3_lzo_dcd_lo[0]));
assign ex3_lzo_dcd_b[160] = (~(ex3_lzo_dcd_hi[10] & ex3_lzo_dcd_lo[1]));
assign ex3_lzo_dcd_b[161] = (~(ex3_lzo_dcd_hi[10] & ex3_lzo_dcd_lo[2]));
assign ex3_lzo_dcd_b[162] = (~(ex3_lzo_dcd_hi[10] & ex3_lzo_dcd_lo[3]));
//-----------------------------------------
assign f_alg_ex3_sel_byp_b = (~(f_alg_ex3_sel_byp));
assign ex3_lzo_nonbyp_0_b = (~(ex3_lzo_nonbyp_0));
assign ex3_lzo_forbyp_0_b = (~(ex3_lzo_forbyp_0));
assign f_lze_ex3_lzo_din[0] = (~((f_alg_ex3_sel_byp | ex3_lzo_nonbyp_0_b) & (f_alg_ex3_sel_byp_b | ex3_lzo_forbyp_0_b))); // neg input and/or
assign f_lze_ex3_lzo_din[1] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[1])); // neg input and --
assign f_lze_ex3_lzo_din[2] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[2])); // neg input and --
assign f_lze_ex3_lzo_din[3] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[3])); // neg input and --
assign f_lze_ex3_lzo_din[4] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[4])); // neg input and --
assign f_lze_ex3_lzo_din[5] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[5])); // neg input and --
assign f_lze_ex3_lzo_din[6] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[6])); // neg input and --
assign f_lze_ex3_lzo_din[7] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[7])); // neg input and --
assign f_lze_ex3_lzo_din[8] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[8])); // neg input and --
assign f_lze_ex3_lzo_din[9] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[9])); // neg input and --
assign f_lze_ex3_lzo_din[10] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[10])); // neg input and --
assign f_lze_ex3_lzo_din[11] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[11])); // neg input and --
assign f_lze_ex3_lzo_din[12] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[12])); // neg input and --
assign f_lze_ex3_lzo_din[13] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[13])); // neg input and --
assign f_lze_ex3_lzo_din[14] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[14])); // neg input and --
assign f_lze_ex3_lzo_din[15] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[15])); // neg input and --
assign f_lze_ex3_lzo_din[16] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[16])); // neg input and --
assign f_lze_ex3_lzo_din[17] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[17])); // neg input and --
assign f_lze_ex3_lzo_din[18] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[18])); // neg input and --
assign f_lze_ex3_lzo_din[19] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[19])); // neg input and --
assign f_lze_ex3_lzo_din[20] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[20])); // neg input and --
assign f_lze_ex3_lzo_din[21] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[21])); // neg input and --
assign f_lze_ex3_lzo_din[22] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[22])); // neg input and --
assign f_lze_ex3_lzo_din[23] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[23])); // neg input and --
assign f_lze_ex3_lzo_din[24] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[24])); // neg input and --
assign f_lze_ex3_lzo_din[25] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[25])); // neg input and --
assign f_lze_ex3_lzo_din[26] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[26])); // neg input and --
assign f_lze_ex3_lzo_din[27] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[27])); // neg input and --
assign f_lze_ex3_lzo_din[28] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[28])); // neg input and --
assign f_lze_ex3_lzo_din[29] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[29])); // neg input and --
assign f_lze_ex3_lzo_din[30] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[30])); // neg input and --
assign f_lze_ex3_lzo_din[31] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[31])); // neg input and --
assign f_lze_ex3_lzo_din[32] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[32])); // neg input and --
assign f_lze_ex3_lzo_din[33] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[33])); // neg input and --
assign f_lze_ex3_lzo_din[34] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[34])); // neg input and --
assign f_lze_ex3_lzo_din[35] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[35])); // neg input and --
assign f_lze_ex3_lzo_din[36] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[36])); // neg input and --
assign f_lze_ex3_lzo_din[37] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[37])); // neg input and --
assign f_lze_ex3_lzo_din[38] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[38])); // neg input and --
assign f_lze_ex3_lzo_din[39] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[39])); // neg input and --
assign f_lze_ex3_lzo_din[40] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[40])); // neg input and --
assign f_lze_ex3_lzo_din[41] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[41])); // neg input and --
assign f_lze_ex3_lzo_din[42] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[42])); // neg input and --
assign f_lze_ex3_lzo_din[43] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[43])); // neg input and --
assign f_lze_ex3_lzo_din[44] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[44])); // neg input and --
assign f_lze_ex3_lzo_din[45] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[45])); // neg input and --
assign f_lze_ex3_lzo_din[46] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[46])); // neg input and --
assign f_lze_ex3_lzo_din[47] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[47])); // neg input and --
assign f_lze_ex3_lzo_din[48] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[48])); // neg input and --
assign f_lze_ex3_lzo_din[49] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[49])); // neg input and --
assign f_lze_ex3_lzo_din[50] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[50])); // neg input and --
assign f_lze_ex3_lzo_din[51] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[51])); // neg input and --
assign f_lze_ex3_lzo_din[52] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[52])); // neg input and --
assign f_lze_ex3_lzo_din[53] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[53])); // neg input and --
assign f_lze_ex3_lzo_din[54] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[54])); // neg input and --
assign f_lze_ex3_lzo_din[55] = (~ex3_lzo_dcd_b[55]);
assign f_lze_ex3_lzo_din[56] = (~ex3_lzo_dcd_b[56]);
assign f_lze_ex3_lzo_din[57] = (~ex3_lzo_dcd_b[57]);
assign f_lze_ex3_lzo_din[58] = (~ex3_lzo_dcd_b[58]);
assign f_lze_ex3_lzo_din[59] = (~ex3_lzo_dcd_b[59]);
assign f_lze_ex3_lzo_din[60] = (~ex3_lzo_dcd_b[60]);
assign f_lze_ex3_lzo_din[61] = (~ex3_lzo_dcd_b[61]);
assign f_lze_ex3_lzo_din[62] = (~ex3_lzo_dcd_b[62]);
assign f_lze_ex3_lzo_din[63] = (~ex3_lzo_dcd_b[63]);
assign f_lze_ex3_lzo_din[64] = (~ex3_lzo_dcd_b[64]);
assign f_lze_ex3_lzo_din[65] = (~ex3_lzo_dcd_b[65]);
assign f_lze_ex3_lzo_din[66] = (~ex3_lzo_dcd_b[66]);
assign f_lze_ex3_lzo_din[67] = (~ex3_lzo_dcd_b[67]);
assign f_lze_ex3_lzo_din[68] = (~ex3_lzo_dcd_b[68]);
assign f_lze_ex3_lzo_din[69] = (~ex3_lzo_dcd_b[69]);
assign f_lze_ex3_lzo_din[70] = (~ex3_lzo_dcd_b[70]);
assign f_lze_ex3_lzo_din[71] = (~ex3_lzo_dcd_b[71]);
assign f_lze_ex3_lzo_din[72] = (~ex3_lzo_dcd_b[72]);
assign f_lze_ex3_lzo_din[73] = (~ex3_lzo_dcd_b[73]);
assign f_lze_ex3_lzo_din[74] = (~ex3_lzo_dcd_b[74]);
assign f_lze_ex3_lzo_din[75] = (~ex3_lzo_dcd_b[75]);
assign f_lze_ex3_lzo_din[76] = (~ex3_lzo_dcd_b[76]);
assign f_lze_ex3_lzo_din[77] = (~ex3_lzo_dcd_b[77]);
assign f_lze_ex3_lzo_din[78] = (~ex3_lzo_dcd_b[78]);
assign f_lze_ex3_lzo_din[79] = (~ex3_lzo_dcd_b[79]);
assign f_lze_ex3_lzo_din[80] = (~ex3_lzo_dcd_b[80]);
assign f_lze_ex3_lzo_din[81] = (~ex3_lzo_dcd_b[81]);
assign f_lze_ex3_lzo_din[82] = (~ex3_lzo_dcd_b[82]);
assign f_lze_ex3_lzo_din[83] = (~ex3_lzo_dcd_b[83]);
assign f_lze_ex3_lzo_din[84] = (~ex3_lzo_dcd_b[84]);
assign f_lze_ex3_lzo_din[85] = (~ex3_lzo_dcd_b[85]);
assign f_lze_ex3_lzo_din[86] = (~ex3_lzo_dcd_b[86]);
assign f_lze_ex3_lzo_din[87] = (~ex3_lzo_dcd_b[87]);
assign f_lze_ex3_lzo_din[88] = (~ex3_lzo_dcd_b[88]);
assign f_lze_ex3_lzo_din[89] = (~ex3_lzo_dcd_b[89]);
assign f_lze_ex3_lzo_din[90] = (~ex3_lzo_dcd_b[90]);
assign f_lze_ex3_lzo_din[91] = (~ex3_lzo_dcd_b[91]);
assign f_lze_ex3_lzo_din[92] = (~ex3_lzo_dcd_b[92]);
assign f_lze_ex3_lzo_din[93] = (~ex3_lzo_dcd_b[93]);
assign f_lze_ex3_lzo_din[94] = (~ex3_lzo_dcd_b[94]);
assign f_lze_ex3_lzo_din[95] = (~ex3_lzo_dcd_b[95]);
assign f_lze_ex3_lzo_din[96] = (~ex3_lzo_dcd_b[96]);
assign f_lze_ex3_lzo_din[97] = (~ex3_lzo_dcd_b[97]);
assign f_lze_ex3_lzo_din[98] = (~ex3_lzo_dcd_b[98]);
assign f_lze_ex3_lzo_din[99] = (~(ex3_lzo_dcd_b[99] & (~f_pic_ex3_to_integer)));
assign f_lze_ex3_lzo_din[100] = (~ex3_lzo_dcd_b[100]);
assign f_lze_ex3_lzo_din[101] = (~ex3_lzo_dcd_b[101]);
assign f_lze_ex3_lzo_din[102] = (~ex3_lzo_dcd_b[102]);
assign f_lze_ex3_lzo_din[103] = (~ex3_lzo_dcd_b[103]);
assign f_lze_ex3_lzo_din[104] = (~ex3_lzo_dcd_b[104]);
assign f_lze_ex3_lzo_din[105] = (~ex3_lzo_dcd_b[105]);
assign f_lze_ex3_lzo_din[106] = (~ex3_lzo_dcd_b[106]);
assign f_lze_ex3_lzo_din[107] = (~ex3_lzo_dcd_b[107]);
assign f_lze_ex3_lzo_din[108] = (~ex3_lzo_dcd_b[108]);
assign f_lze_ex3_lzo_din[109] = (~ex3_lzo_dcd_b[109]);
assign f_lze_ex3_lzo_din[110] = (~ex3_lzo_dcd_b[110]);
assign f_lze_ex3_lzo_din[111] = (~ex3_lzo_dcd_b[111]);
assign f_lze_ex3_lzo_din[112] = (~ex3_lzo_dcd_b[112]);
assign f_lze_ex3_lzo_din[113] = (~ex3_lzo_dcd_b[113]);
assign f_lze_ex3_lzo_din[114] = (~ex3_lzo_dcd_b[114]);
assign f_lze_ex3_lzo_din[115] = (~ex3_lzo_dcd_b[115]);
assign f_lze_ex3_lzo_din[116] = (~ex3_lzo_dcd_b[116]);
assign f_lze_ex3_lzo_din[117] = (~ex3_lzo_dcd_b[117]);
assign f_lze_ex3_lzo_din[118] = (~ex3_lzo_dcd_b[118]);
assign f_lze_ex3_lzo_din[119] = (~ex3_lzo_dcd_b[119]);
assign f_lze_ex3_lzo_din[120] = (~ex3_lzo_dcd_b[120]);
assign f_lze_ex3_lzo_din[121] = (~ex3_lzo_dcd_b[121]);
assign f_lze_ex3_lzo_din[122] = (~ex3_lzo_dcd_b[122]);
assign f_lze_ex3_lzo_din[123] = (~ex3_lzo_dcd_b[123]);
assign f_lze_ex3_lzo_din[124] = (~ex3_lzo_dcd_b[124]);
assign f_lze_ex3_lzo_din[125] = (~ex3_lzo_dcd_b[125]);
assign f_lze_ex3_lzo_din[126] = (~ex3_lzo_dcd_b[126]);
assign f_lze_ex3_lzo_din[127] = (~ex3_lzo_dcd_b[127]);
assign f_lze_ex3_lzo_din[128] = (~ex3_lzo_dcd_b[128]);
assign f_lze_ex3_lzo_din[129] = (~ex3_lzo_dcd_b[129]);
assign f_lze_ex3_lzo_din[130] = (~ex3_lzo_dcd_b[130]);
assign f_lze_ex3_lzo_din[131] = (~ex3_lzo_dcd_b[131]);
assign f_lze_ex3_lzo_din[132] = (~ex3_lzo_dcd_b[132]);
assign f_lze_ex3_lzo_din[133] = (~ex3_lzo_dcd_b[133]);
assign f_lze_ex3_lzo_din[134] = (~ex3_lzo_dcd_b[134]);
assign f_lze_ex3_lzo_din[135] = (~ex3_lzo_dcd_b[135]);
assign f_lze_ex3_lzo_din[136] = (~ex3_lzo_dcd_b[136]);
assign f_lze_ex3_lzo_din[137] = (~ex3_lzo_dcd_b[137]);
assign f_lze_ex3_lzo_din[138] = (~ex3_lzo_dcd_b[138]);
assign f_lze_ex3_lzo_din[139] = (~ex3_lzo_dcd_b[139]);
assign f_lze_ex3_lzo_din[140] = (~ex3_lzo_dcd_b[140]);
assign f_lze_ex3_lzo_din[141] = (~ex3_lzo_dcd_b[141]);
assign f_lze_ex3_lzo_din[142] = (~ex3_lzo_dcd_b[142]);
assign f_lze_ex3_lzo_din[143] = (~ex3_lzo_dcd_b[143]);
assign f_lze_ex3_lzo_din[144] = (~ex3_lzo_dcd_b[144]);
assign f_lze_ex3_lzo_din[145] = (~ex3_lzo_dcd_b[145]);
assign f_lze_ex3_lzo_din[146] = (~ex3_lzo_dcd_b[146]);
assign f_lze_ex3_lzo_din[147] = (~ex3_lzo_dcd_b[147]);
assign f_lze_ex3_lzo_din[148] = (~ex3_lzo_dcd_b[148]);
assign f_lze_ex3_lzo_din[149] = (~ex3_lzo_dcd_b[149]);
assign f_lze_ex3_lzo_din[150] = (~ex3_lzo_dcd_b[150]);
assign f_lze_ex3_lzo_din[151] = (~ex3_lzo_dcd_b[151]);
assign f_lze_ex3_lzo_din[152] = (~ex3_lzo_dcd_b[152]);
assign f_lze_ex3_lzo_din[153] = (~ex3_lzo_dcd_b[153]);
assign f_lze_ex3_lzo_din[154] = (~ex3_lzo_dcd_b[154]);
assign f_lze_ex3_lzo_din[155] = (~ex3_lzo_dcd_b[155]);
assign f_lze_ex3_lzo_din[156] = (~ex3_lzo_dcd_b[156]);
assign f_lze_ex3_lzo_din[157] = (~ex3_lzo_dcd_b[157]);
assign f_lze_ex3_lzo_din[158] = (~ex3_lzo_dcd_b[158]);
assign f_lze_ex3_lzo_din[159] = (~ex3_lzo_dcd_b[159]);
assign f_lze_ex3_lzo_din[160] = (~ex3_lzo_dcd_b[160]);
assign f_lze_ex3_lzo_din[161] = (~ex3_lzo_dcd_b[161]);
assign f_lze_ex3_lzo_din[162] = (~ex3_lzo_dcd_b[162]);
////##------------------------------------------
////## shift right stuff ... some could be in cycle 3
////##------------------------------------------
// enable shift right when bypassing a denormal B operand (and NOT ue=1 or PRRENORM)
assign ex3_ins_est = f_pic_ex3_est_recip | f_pic_ex3_est_rsqrt;
assign ex3_sh_rgt_en_by = (f_eie_ex3_use_bexp & ex3_expo_neg_sp_by & ex3_lzo_cont_sp & (~f_alg_ex3_byp_nonflip) & (~ex3_ins_est)) | (f_eie_ex3_use_bexp & ex3_expo_neg_dp_by & ex3_lzo_cont_dp & (~f_alg_ex3_byp_nonflip) & (~ex3_ins_est)); // set LZO[0] so can just OR into result
assign ex3_sh_rgt_en_p = ((~f_eie_ex3_use_bexp) & ex3_expo_neg_sp & ex3_lzo_cont_sp & (~f_alg_ex3_byp_nonflip)) | ((~f_eie_ex3_use_bexp) & ex3_expo_neg_dp & ex3_lzo_cont_dp & (~f_alg_ex3_byp_nonflip)); // set LZO[0] so can just OR into result
assign ex3_sh_rgt_en = ex3_sh_rgt_en_by | ex3_sh_rgt_en_p;
////----------------------------------------------------------------------------------------------
//// you might be thinking that the shift right amount needs a limiter (so that amounts > 64
//// do not wrap a round and leave bits in the result when the result should be zero).
//// (1) if the shift amount belongs to the "B" operand, (bypass) and since we only shift right
//// when B is a denorm (it has a bit on) then the maximum shift right is (52) because
//// the smallest b exponent (expo min) after prenorm is -52.
//// there is the possibility that a divide could create an artificially small Bexpo.
//// if that is true the shift right amount should be zero (right 64 followed by left 0).
//// (2) otherwise the right shift amount comes from the product exponent.
//// the product exponent could be very small, however for a multiply add if it becomes
//// too small then the exponent will come from the addend, so no problem.
//// a multiply instruction does not have an addend, and it could have a very small exponent.
//// BUT, the lead bit is at [55] and even if the shift right goes right 64 followed by left 64,
//// it will not but a bit into the result or guard fields.
////-----------------------------------------------------------------------------------------------
// calculate shift right amount (DP) ... expo must be correct value to subtract in expo logic
// decode = 0 shift right 1 -(-1) for expo 0_0000_0000_0000 -> 1_1111_1111_1111 -x = !x + 1, !x = -x - 1
// decode = -1 shift right 2 -(-2) for expo 0_0000_0000_0001 -> 1_1111_1111_1110
// decode = -2 shift right 3 -(-3) for expo 0_0000_0000_0010 -> 1_1111_1111_1101
//
// max = -53 0_0000_0011_0101 -> 1_1111_1100_1010
// * **** **dd_dddd
// calculate shift right amount (SP)
// decode = x380 shift right 1 -(-1) for expo 0_0011_1000_0000 -> 1_1100_0111_1111 -x = !x + 1, !x = -x - 1
// decode = x37F shift right 2 -(-2) for expo 0_0011_1000_0001 -> 1_1100_0111_1110
// decode = x37E shift right 3 -(-3) for expo 0_0011_1000_0010 -> 1_1100_0111_1101
// * **** **dd_dddd
// expo = Bexpo - lza
// Bexpo + (!lza) ... lza is usually sign extended and inverted to make a negative number,
// Bexpo must be added to in denorm cases
// Make lza a negative number, so that when it is flipped it becomes a positive number.
//
// expo_adj
// expo = x380 896 0_0011_1000_0000 1 -( 1) 1111_1111
// expo = x37f 895 0_0011_0111_1111 2 -( 2) 1111_1110
// expo = x37e 894 0_0011_0111_1110 3 1111_1101
// expo = x37d 893 0_0011_0111_1101 4 1111_1100
// expo = x37c 892 0_0011_0111_1100 5
// expo = x37b 891 0_0011_0111_1011 6
// expo = x37a 890 0_0011_0111_1010 7
// expo = x379 889 0_0011_0111_1001 8
// expo = x378 888 0_0011_0111_1000 9
// expo = x377 887 0_0011_0111_0111 10
// expo = x376 886 0_0011_0111_0110 11
// expo = x375 885 0_0011_0111_0101 12
// expo = x374 884 0_0011_0111_0100 13
// expo = x373 883 0_0011_0111_0011 14
// expo = x372 882 0_0011_0111_0010 15
// expo = x371 881 0_0011_0111_0001 16
// expo = x370 880 0_0011_0111_0000 17
// expo = x36f 879 0_0011_0110_1111 18
// expo = x36e 878 0_0011_0110_1110 19
// expo = x36d 877 0_0011_0110_1101 20
// expo = x36c 876 0_0011_0110_1100 21
// expo = x36b 875 0_0011_0110_1011 22
// expo = x36a 874 0_0011_0110_1010 23 -(23) 1110_1001
//-----------------------------
// expo = x369 873 0_0011_0110_1001 24 -(24) 1110_1000
// if p_exp an be more neg then -63 , then this needs to be detected and shAmt forced to a const.
assign ex3_expo_p_sim_p[8:13] = (~ex3_expo[8:13]);
assign ex3_expo_p_sim_g[13] = ex3_expo[13];
assign ex3_expo_p_sim_g[12] = ex3_expo[13] | ex3_expo[12];
assign ex3_expo_p_sim_g[11] = ex3_expo[13] | ex3_expo[12] | ex3_expo[11];
assign ex3_expo_p_sim_g[10] = ex3_expo[13] | ex3_expo[12] | ex3_expo[11] | ex3_expo[10];
assign ex3_expo_p_sim_g[9] = ex3_expo[13] | ex3_expo[12] | ex3_expo[11] | ex3_expo[10] | ex3_expo[9];
assign ex3_expo_p_sim[13] = ex3_expo_p_sim_p[13];
assign ex3_expo_p_sim[12] = ex3_expo_p_sim_p[12] ^ (ex3_expo_p_sim_g[13]);
assign ex3_expo_p_sim[11] = ex3_expo_p_sim_p[11] ^ (ex3_expo_p_sim_g[12]);
assign ex3_expo_p_sim[10] = ex3_expo_p_sim_p[10] ^ (ex3_expo_p_sim_g[11]);
assign ex3_expo_p_sim[9] = ex3_expo_p_sim_p[9] ^ (ex3_expo_p_sim_g[10]);
assign ex3_expo_p_sim[8] = ex3_expo_p_sim_p[8] ^ (ex3_expo_p_sim_g[9]);
assign ex3_expo_sim_p[8:13] = (~ex3_expo_by[8:13]);
assign ex3_expo_sim_g[13] = ex3_expo_by[13];
assign ex3_expo_sim_g[12] = ex3_expo_by[13] | ex3_expo_by[12];
assign ex3_expo_sim_g[11] = ex3_expo_by[13] | ex3_expo_by[12] | ex3_expo_by[11];
assign ex3_expo_sim_g[10] = ex3_expo_by[13] | ex3_expo_by[12] | ex3_expo_by[11] | ex3_expo_by[10];
assign ex3_expo_sim_g[9] = ex3_expo_by[13] | ex3_expo_by[12] | ex3_expo_by[11] | ex3_expo_by[10] | ex3_expo_by[9];
assign ex3_expo_sim[13] = ex3_expo_sim_p[13];
assign ex3_expo_sim[12] = ex3_expo_sim_p[12] ^ (ex3_expo_sim_g[13]);
assign ex3_expo_sim[11] = ex3_expo_sim_p[11] ^ (ex3_expo_sim_g[12]);
assign ex3_expo_sim[10] = ex3_expo_sim_p[10] ^ (ex3_expo_sim_g[11]);
assign ex3_expo_sim[9] = ex3_expo_sim_p[9] ^ (ex3_expo_sim_g[10]);
assign ex3_expo_sim[8] = ex3_expo_sim_p[8] ^ (ex3_expo_sim_g[9]);
// testing a new (simpler) version -------------
// could include these in lzo dis
// could include these in lzo_dis
assign ex3_lzo_forbyp_0 = (f_pic_ex3_est_recip) | (f_pic_ex3_est_rsqrt) | (f_alg_ex3_byp_nonflip & (~f_pic_ex3_prenorm)) | ((~f_fmt_ex3_pass_msb_dp) & (~f_pic_ex3_lzo_dis_prod)) | ((ex3_expo_neg_dp_by | ex3_dp_001_by) & ex3_lzo_cont_dp) | ((ex3_expo_neg_sp_by | ex3_sp_001_by) & ex3_lzo_cont_sp); // allow norm to decr MSB then renormalize
assign ex3_lzo_nonbyp_0 = (ex3_lzo_dcd_0) | (ex3_expo_neg_dp & ex3_lzo_cont_dp) | (ex3_expo_neg_sp & ex3_lzo_cont_sp) | (f_pic_ex3_est_recip) | (f_pic_ex3_est_rsqrt);
assign ex3_sh_rgt_amt[0] = ex3_sh_rgt_en; // huge shift right should give "0"
assign ex3_sh_rgt_amt[1] = ex3_sh_rgt_en; // huge shift right should give "0"
assign ex3_sh_rgt_amt[2] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[8]) | (ex3_sh_rgt_en_by & ex3_expo_sim[8]);
assign ex3_sh_rgt_amt[3] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[9]) | (ex3_sh_rgt_en_by & ex3_expo_sim[9]);
assign ex3_sh_rgt_amt[4] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[10]) | (ex3_sh_rgt_en_by & ex3_expo_sim[10]);
assign ex3_sh_rgt_amt[5] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[11]) | (ex3_sh_rgt_en_by & ex3_expo_sim[11]);
assign ex3_sh_rgt_amt[6] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[12]) | (ex3_sh_rgt_en_by & ex3_expo_sim[12]);
assign ex3_sh_rgt_amt[7] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[13]) | (ex3_sh_rgt_en_by & ex3_expo_sim[13]);
// bit_to_set |------ b_expo ----------|
// 0 897 x381 0_0011_1000_0001 <== all normal SP numbers go here
// 1 896 x380 0_0011_1000_0000
// 2 895 x37f 0_0011_0111_1111
// 3 894 x37e 0_0011_0111_1110
// 4 893 x37d 0_0011_0111_1101
// 5 892 x37c 0_0011_0111_1100
// 6 891 x37b 0_0011_0111_1011
// 7 890 x37a 0_0011_0111_1010
// 8 889 x379 0_0011_0111_1001
// 9 888 x378 0_0011_0111_1000
// 10 887 x377 0_0011_0111_0111
// 11 886 x376 0_0011_0111_0110
// 12 885 x375 0_0011_0111_0101
// 13 884 x374 0_0011_0111_0100 expo = (884 +26 -13) = 884 + 13 = 897
// 14 883 x373 0_0011_0111_0011
// 15 882 x372 0_0011_0111_0010
// 16 881 x371 0_0011_0111_0001
// 17 880 x370 0_0011_0111_0000
// 18 879 x36f 0_0011_0011_1111
// 19 878 x36e 0_0011_0011_1110
// 20 877 x36d 0_0011_0011_1101
// 21 876 x36c 0_0011_0011_1100
// 22 875 x36b 0_0011_0011_1011
// 23 874 x36a 0_0011_0011_1010
// -----------------------------------------
// 24 873 x369 0_0011_0011_1001 <=== if this or smaller do nothing (special case sp invalid)
//
//-=###############################################################
//-=## ex4 latches
//-=###############################################################
tri_rlmreg_p #(.WIDTH(9), .NEEDS_SRESET(0)) ex4_shr_lat(
.force_t(force_t), // tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[3]), // tidn,
.mpw1_b(mpw1_b[3]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(ex3_act),
.thold_b(thold_0_b),
.sg(sg_0),
.scout(ex4_shr_so),
.scin(ex4_shr_si),
//-----------------
.din({ex3_sh_rgt_amt[0:7],
ex3_sh_rgt_en}),
//-----------------
.dout({ex4_sh_rgt_amt[0:7],
ex4_sh_rgt_en})
);
assign f_lze_ex4_sh_rgt_amt[0:7] = ex4_sh_rgt_amt[0:7]; //OUTPUT--
assign f_lze_ex4_sh_rgt_en = ex4_sh_rgt_en; //OUTPUT--
//-=###############################################################
//-= scan string
//-=###############################################################
assign ex4_shr_si[0:8] = {ex4_shr_so[1:8], f_lze_si};
assign act_si[0:4] = {act_so[1:4], ex4_shr_so[0]};
assign f_lze_so = act_so[0];
endmodule |
module fu_nrm_or16(
f_add_ex5_res,
ex5_or_grp16
);
input [0:162] f_add_ex5_res;
output [0:10] ex5_or_grp16;
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:162] ex5_res_b;
wire [0:3] g00_or02;
wire [0:7] g01_or02;
wire [0:7] g02_or02;
wire [0:7] g03_or02;
wire [0:7] g04_or02;
wire [0:7] g05_or02;
wire [0:7] g06_or02;
wire [0:7] g07_or02;
wire [0:7] g08_or02;
wire [0:7] g09_or02;
wire [0:5] g10_or02;
wire [0:1] g00_or04_b;
wire [0:3] g01_or04_b;
wire [0:3] g02_or04_b;
wire [0:3] g03_or04_b;
wire [0:3] g04_or04_b;
wire [0:3] g05_or04_b;
wire [0:3] g06_or04_b;
wire [0:3] g07_or04_b;
wire [0:3] g08_or04_b;
wire [0:3] g09_or04_b;
wire [0:2] g10_or04_b;
wire [0:0] g00_or08;
wire [0:1] g01_or08;
wire [0:1] g02_or08;
wire [0:1] g03_or08;
wire [0:1] g04_or08;
wire [0:1] g05_or08;
wire [0:1] g06_or08;
wire [0:1] g07_or08;
wire [0:1] g08_or08;
wire [0:1] g09_or08;
wire [0:1] g10_or08;
wire g00_or16_b;
wire g01_or16_b;
wire g02_or16_b;
wire g03_or16_b;
wire g04_or16_b;
wire g05_or16_b;
wire g06_or16_b;
wire g07_or16_b;
wire g08_or16_b;
wire g09_or16_b;
wire g10_or16_b;
// ex5_or_grp16(0) <= 0: 7
// ex5_or_grp16(1) <= 8: 23
// ex5_or_grp16(2) <= 24: 39
// ex5_or_grp16(3) <= 40: 55
// ex5_or_grp16(4) <= 56: 71
// ex5_or_grp16(5) <= 72: 87
// ex5_or_grp16(6) <= 88:103
// ex5_or_grp16(7) <= 104:119
// ex5_or_grp16(8) <= 120:135
// ex5_or_grp16(9) <= 136:151
// ex5_or_grp16(10) <= 152:162
//===============================================================--
assign ex5_res_b[0:162] = (~f_add_ex5_res[0:162]); // small
//===============================================================--
assign g00_or02[0] = (~(ex5_res_b[0] & ex5_res_b[1]));
assign g00_or02[1] = (~(ex5_res_b[2] & ex5_res_b[3]));
assign g00_or02[2] = (~(ex5_res_b[4] & ex5_res_b[5]));
assign g00_or02[3] = (~(ex5_res_b[6] & ex5_res_b[7]));
assign g01_or02[0] = (~(ex5_res_b[8] & ex5_res_b[9]));
assign g01_or02[1] = (~(ex5_res_b[10] & ex5_res_b[11]));
assign g01_or02[2] = (~(ex5_res_b[12] & ex5_res_b[13]));
assign g01_or02[3] = (~(ex5_res_b[14] & ex5_res_b[15]));
assign g01_or02[4] = (~(ex5_res_b[16] & ex5_res_b[17]));
assign g01_or02[5] = (~(ex5_res_b[18] & ex5_res_b[19]));
assign g01_or02[6] = (~(ex5_res_b[20] & ex5_res_b[21]));
assign g01_or02[7] = (~(ex5_res_b[22] & ex5_res_b[23]));
assign g02_or02[0] = (~(ex5_res_b[24] & ex5_res_b[25]));
assign g02_or02[1] = (~(ex5_res_b[26] & ex5_res_b[27]));
assign g02_or02[2] = (~(ex5_res_b[28] & ex5_res_b[29]));
assign g02_or02[3] = (~(ex5_res_b[30] & ex5_res_b[31]));
assign g02_or02[4] = (~(ex5_res_b[32] & ex5_res_b[33]));
assign g02_or02[5] = (~(ex5_res_b[34] & ex5_res_b[35]));
assign g02_or02[6] = (~(ex5_res_b[36] & ex5_res_b[37]));
assign g02_or02[7] = (~(ex5_res_b[38] & ex5_res_b[39]));
assign g03_or02[0] = (~(ex5_res_b[40] & ex5_res_b[41]));
assign g03_or02[1] = (~(ex5_res_b[42] & ex5_res_b[43]));
assign g03_or02[2] = (~(ex5_res_b[44] & ex5_res_b[45]));
assign g03_or02[3] = (~(ex5_res_b[46] & ex5_res_b[47]));
assign g03_or02[4] = (~(ex5_res_b[48] & ex5_res_b[49]));
assign g03_or02[5] = (~(ex5_res_b[50] & ex5_res_b[51]));
assign g03_or02[6] = (~(ex5_res_b[52] & ex5_res_b[53]));
assign g03_or02[7] = (~(ex5_res_b[54] & ex5_res_b[55]));
assign g04_or02[0] = (~(ex5_res_b[56] & ex5_res_b[57]));
assign g04_or02[1] = (~(ex5_res_b[58] & ex5_res_b[59]));
assign g04_or02[2] = (~(ex5_res_b[60] & ex5_res_b[61]));
assign g04_or02[3] = (~(ex5_res_b[62] & ex5_res_b[63]));
assign g04_or02[4] = (~(ex5_res_b[64] & ex5_res_b[65]));
assign g04_or02[5] = (~(ex5_res_b[66] & ex5_res_b[67]));
assign g04_or02[6] = (~(ex5_res_b[68] & ex5_res_b[69]));
assign g04_or02[7] = (~(ex5_res_b[70] & ex5_res_b[71]));
assign g05_or02[0] = (~(ex5_res_b[72] & ex5_res_b[73]));
assign g05_or02[1] = (~(ex5_res_b[74] & ex5_res_b[75]));
assign g05_or02[2] = (~(ex5_res_b[76] & ex5_res_b[77]));
assign g05_or02[3] = (~(ex5_res_b[78] & ex5_res_b[79]));
assign g05_or02[4] = (~(ex5_res_b[80] & ex5_res_b[81]));
assign g05_or02[5] = (~(ex5_res_b[82] & ex5_res_b[83]));
assign g05_or02[6] = (~(ex5_res_b[84] & ex5_res_b[85]));
assign g05_or02[7] = (~(ex5_res_b[86] & ex5_res_b[87]));
assign g06_or02[0] = (~(ex5_res_b[88] & ex5_res_b[89]));
assign g06_or02[1] = (~(ex5_res_b[90] & ex5_res_b[91]));
assign g06_or02[2] = (~(ex5_res_b[92] & ex5_res_b[93]));
assign g06_or02[3] = (~(ex5_res_b[94] & ex5_res_b[95]));
assign g06_or02[4] = (~(ex5_res_b[96] & ex5_res_b[97]));
assign g06_or02[5] = (~(ex5_res_b[98] & ex5_res_b[99]));
assign g06_or02[6] = (~(ex5_res_b[100] & ex5_res_b[101]));
assign g06_or02[7] = (~(ex5_res_b[102] & ex5_res_b[103]));
assign g07_or02[0] = (~(ex5_res_b[104] & ex5_res_b[105]));
assign g07_or02[1] = (~(ex5_res_b[106] & ex5_res_b[107]));
assign g07_or02[2] = (~(ex5_res_b[108] & ex5_res_b[109]));
assign g07_or02[3] = (~(ex5_res_b[110] & ex5_res_b[111]));
assign g07_or02[4] = (~(ex5_res_b[112] & ex5_res_b[113]));
assign g07_or02[5] = (~(ex5_res_b[114] & ex5_res_b[115]));
assign g07_or02[6] = (~(ex5_res_b[116] & ex5_res_b[117]));
assign g07_or02[7] = (~(ex5_res_b[118] & ex5_res_b[119]));
assign g08_or02[0] = (~(ex5_res_b[120] & ex5_res_b[121]));
assign g08_or02[1] = (~(ex5_res_b[122] & ex5_res_b[123]));
assign g08_or02[2] = (~(ex5_res_b[124] & ex5_res_b[125]));
assign g08_or02[3] = (~(ex5_res_b[126] & ex5_res_b[127]));
assign g08_or02[4] = (~(ex5_res_b[128] & ex5_res_b[129]));
assign g08_or02[5] = (~(ex5_res_b[130] & ex5_res_b[131]));
assign g08_or02[6] = (~(ex5_res_b[132] & ex5_res_b[133]));
assign g08_or02[7] = (~(ex5_res_b[134] & ex5_res_b[135]));
assign g09_or02[0] = (~(ex5_res_b[136] & ex5_res_b[137]));
assign g09_or02[1] = (~(ex5_res_b[138] & ex5_res_b[139]));
assign g09_or02[2] = (~(ex5_res_b[140] & ex5_res_b[141]));
assign g09_or02[3] = (~(ex5_res_b[142] & ex5_res_b[143]));
assign g09_or02[4] = (~(ex5_res_b[144] & ex5_res_b[145]));
assign g09_or02[5] = (~(ex5_res_b[146] & ex5_res_b[147]));
assign g09_or02[6] = (~(ex5_res_b[148] & ex5_res_b[149]));
assign g09_or02[7] = (~(ex5_res_b[150] & ex5_res_b[151]));
assign g10_or02[0] = (~(ex5_res_b[152] & ex5_res_b[153]));
assign g10_or02[1] = (~(ex5_res_b[154] & ex5_res_b[155]));
assign g10_or02[2] = (~(ex5_res_b[156] & ex5_res_b[157]));
assign g10_or02[3] = (~(ex5_res_b[158] & ex5_res_b[159]));
assign g10_or02[4] = (~(ex5_res_b[160] & ex5_res_b[161]));
assign g10_or02[5] = (~(ex5_res_b[162]));
//===============================================================--
assign g00_or04_b[0] = (~(g00_or02[0] | g00_or02[1]));
assign g00_or04_b[1] = (~(g00_or02[2] | g00_or02[3]));
assign g01_or04_b[0] = (~(g01_or02[0] | g01_or02[1]));
assign g01_or04_b[1] = (~(g01_or02[2] | g01_or02[3]));
assign g01_or04_b[2] = (~(g01_or02[4] | g01_or02[5]));
assign g01_or04_b[3] = (~(g01_or02[6] | g01_or02[7]));
assign g02_or04_b[0] = (~(g02_or02[0] | g02_or02[1]));
assign g02_or04_b[1] = (~(g02_or02[2] | g02_or02[3]));
assign g02_or04_b[2] = (~(g02_or02[4] | g02_or02[5]));
assign g02_or04_b[3] = (~(g02_or02[6] | g02_or02[7]));
assign g03_or04_b[0] = (~(g03_or02[0] | g03_or02[1]));
assign g03_or04_b[1] = (~(g03_or02[2] | g03_or02[3]));
assign g03_or04_b[2] = (~(g03_or02[4] | g03_or02[5]));
assign g03_or04_b[3] = (~(g03_or02[6] | g03_or02[7]));
assign g04_or04_b[0] = (~(g04_or02[0] | g04_or02[1]));
assign g04_or04_b[1] = (~(g04_or02[2] | g04_or02[3]));
assign g04_or04_b[2] = (~(g04_or02[4] | g04_or02[5]));
assign g04_or04_b[3] = (~(g04_or02[6] | g04_or02[7]));
assign g05_or04_b[0] = (~(g05_or02[0] | g05_or02[1]));
assign g05_or04_b[1] = (~(g05_or02[2] | g05_or02[3]));
assign g05_or04_b[2] = (~(g05_or02[4] | g05_or02[5]));
assign g05_or04_b[3] = (~(g05_or02[6] | g05_or02[7]));
assign g06_or04_b[0] = (~(g06_or02[0] | g06_or02[1]));
assign g06_or04_b[1] = (~(g06_or02[2] | g06_or02[3]));
assign g06_or04_b[2] = (~(g06_or02[4] | g06_or02[5]));
assign g06_or04_b[3] = (~(g06_or02[6] | g06_or02[7]));
assign g07_or04_b[0] = (~(g07_or02[0] | g07_or02[1]));
assign g07_or04_b[1] = (~(g07_or02[2] | g07_or02[3]));
assign g07_or04_b[2] = (~(g07_or02[4] | g07_or02[5]));
assign g07_or04_b[3] = (~(g07_or02[6] | g07_or02[7]));
assign g08_or04_b[0] = (~(g08_or02[0] | g08_or02[1]));
assign g08_or04_b[1] = (~(g08_or02[2] | g08_or02[3]));
assign g08_or04_b[2] = (~(g08_or02[4] | g08_or02[5]));
assign g08_or04_b[3] = (~(g08_or02[6] | g08_or02[7]));
assign g09_or04_b[0] = (~(g09_or02[0] | g09_or02[1]));
assign g09_or04_b[1] = (~(g09_or02[2] | g09_or02[3]));
assign g09_or04_b[2] = (~(g09_or02[4] | g09_or02[5]));
assign g09_or04_b[3] = (~(g09_or02[6] | g09_or02[7]));
assign g10_or04_b[0] = (~(g10_or02[0] | g10_or02[1]));
assign g10_or04_b[1] = (~(g10_or02[2] | g10_or02[3]));
assign g10_or04_b[2] = (~(g10_or02[4] | g10_or02[5]));
//===============================================================--
assign g00_or08[0] = (~(g00_or04_b[0] & g00_or04_b[1]));
assign g01_or08[0] = (~(g01_or04_b[0] & g01_or04_b[1]));
assign g01_or08[1] = (~(g01_or04_b[2] & g01_or04_b[3]));
assign g02_or08[0] = (~(g02_or04_b[0] & g02_or04_b[1]));
assign g02_or08[1] = (~(g02_or04_b[2] & g02_or04_b[3]));
assign g03_or08[0] = (~(g03_or04_b[0] & g03_or04_b[1]));
assign g03_or08[1] = (~(g03_or04_b[2] & g03_or04_b[3]));
assign g04_or08[0] = (~(g04_or04_b[0] & g04_or04_b[1]));
assign g04_or08[1] = (~(g04_or04_b[2] & g04_or04_b[3]));
assign g05_or08[0] = (~(g05_or04_b[0] & g05_or04_b[1]));
assign g05_or08[1] = (~(g05_or04_b[2] & g05_or04_b[3]));
assign g06_or08[0] = (~(g06_or04_b[0] & g06_or04_b[1]));
assign g06_or08[1] = (~(g06_or04_b[2] & g06_or04_b[3]));
assign g07_or08[0] = (~(g07_or04_b[0] & g07_or04_b[1]));
assign g07_or08[1] = (~(g07_or04_b[2] & g07_or04_b[3]));
assign g08_or08[0] = (~(g08_or04_b[0] & g08_or04_b[1]));
assign g08_or08[1] = (~(g08_or04_b[2] & g08_or04_b[3]));
assign g09_or08[0] = (~(g09_or04_b[0] & g09_or04_b[1]));
assign g09_or08[1] = (~(g09_or04_b[2] & g09_or04_b[3]));
assign g10_or08[0] = (~(g10_or04_b[0] & g10_or04_b[1]));
assign g10_or08[1] = (~(g10_or04_b[2]));
//===============================================================--
assign g00_or16_b = (~(g00_or08[0]));
assign g01_or16_b = (~(g01_or08[0] | g01_or08[1]));
assign g02_or16_b = (~(g02_or08[0] | g02_or08[1]));
assign g03_or16_b = (~(g03_or08[0] | g03_or08[1]));
assign g04_or16_b = (~(g04_or08[0] | g04_or08[1]));
assign g05_or16_b = (~(g05_or08[0] | g05_or08[1]));
assign g06_or16_b = (~(g06_or08[0] | g06_or08[1]));
assign g07_or16_b = (~(g07_or08[0] | g07_or08[1]));
assign g08_or16_b = (~(g08_or08[0] | g08_or08[1]));
assign g09_or16_b = (~(g09_or08[0] | g09_or08[1]));
assign g10_or16_b = (~(g10_or08[0] | g10_or08[1]));
//===============================================================--
///////////////////////////////////////////////////////////--
assign ex5_or_grp16[0] = (~(g00_or16_b)); //output--
assign ex5_or_grp16[1] = (~(g01_or16_b)); //output--
assign ex5_or_grp16[2] = (~(g02_or16_b)); //output--
assign ex5_or_grp16[3] = (~(g03_or16_b)); //output--
assign ex5_or_grp16[4] = (~(g04_or16_b)); //output--
assign ex5_or_grp16[5] = (~(g05_or16_b)); //output--
assign ex5_or_grp16[6] = (~(g06_or16_b)); //output--
assign ex5_or_grp16[7] = (~(g07_or16_b)); //output--
assign ex5_or_grp16[8] = (~(g08_or16_b)); //output--
assign ex5_or_grp16[9] = (~(g09_or16_b)); //output--
assign ex5_or_grp16[10] = (~(g10_or16_b)); //output--
endmodule |
module fu_loc8inc(
x,
ci,
ci_b,
co_b,
s0,
s1
);
input [0:7] x;
input ci;
input ci_b;
output co_b;
output [0:7] s0;
output [0:7] s1;
wire [0:7] x_if_ci;
wire [0:7] x_b;
wire [0:7] x_p;
wire g2_6t7_b;
wire g2_4t5_b;
wire g2_2t3_b;
wire g2_0t1_b;
wire g4_4t7;
wire g4_0t3;
wire t2_6t7;
wire t2_4t5;
wire t2_2t3;
wire t4_6t7_b;
wire t4_4t7_b;
wire t4_2t5_b;
wire t8_6t7;
wire t8_4t7;
wire t8_2t7;
wire t8_7t7_b;
wire t8_6t7_b;
wire t8_5t7_b;
wire t8_4t7_b;
wire t8_3t7_b;
wire t8_2t7_b;
wire t8_1t7_b;
wire [0:7] s1x_b;
wire [0:7] s1y_b;
wire [0:7] s0_b;
// i0_b0 i1_b0 i2_b0 i3_b0 i4_b0 i5_b0 i6_b0 i7_b0 <=== buffer inputs
// i0_b1 i1_b1 i2_b1 i3_b1 i4_b1 i5_b1 i6_b1 i7_b1 <=== buffer inputs
// i0_g2 i0_g4 i2_g2 i0_g8 i4_g2 i4_g4 i6_g2 skip <=== global chain
// skip skip i2_t4 i2_t2 i4_t4 i4_t2 i6_t4 i6_t2 <=== local carry
// skip skip i2_t8x skip i4_t8x skip i6_t8x skip <=== local carry
// skip i1_t8 i2_t8 i3_t8 i4_t8 i5_t8 i6_t8 i7_t8 <=== local carry
// i0_if i1_if i2_if i3_if i4_if i5_if i6_if i7_if <=== local carry
// i0_s1x i1_s1x i2_s1x i3_s1x i4_s1x i5_s1x i6_s1x i7_s1x <=== carry select
// i0_s1y i1_s1y i2_s1y i3_s1y i4_s1y i5_s1y i6_s1y i7_s1y <=== carry select
// i0_s1 i1_s1 i2_s1 i3_s1 i4_s1 i5_s1 i6_s1 i7_s1 <=== carry select
// i0_s0b i1_s0b i2_s0b i3_s0b i4_s0b i5_s0b i6_s0b i7_s0b <=== carry select
// i0_s0 i1_s0 i2_s0 i3_s0 i4_s0 i5_s0 i6_s0 i7_s0 <=== carry select
//FOLDED
// i0_b0 i2_b0 i4_b0 i6_b0 skip skip skip skip <=== buffer inputs
// i1_b0 i3_b0 i5_b0 i7_b0 skip skip skip skip <=== buffer inputs
// i0_b1 i2_b1 i4_b1 i6_b1 skip skip skip skip <=== buffer inputs
// i1_b1 i3_b1 i5_b1 i7_b1 skip skip skip skip <=== buffer inputs
// i0_g2 i2_g2 i4_g2 i6_g2 skip skip skip skip <=== global chain
// i0_g4 i0_g8 i4_g4 skip skip skip skip skip <=== global chain
// skip i2_t2 i4_t2 i6_t2 skip skip skip skip <=== local carry
// skip i2_t4 i4_t4 i6_t4 skip skip skip skip <=== local carry
// skip i2_t8x i4_t8x i6_t8x skip skip skip skip <=== local carry
// skip i2_t8 i4_t8 i6_t8 skip skip skip skip <=== local carry
// i1_t8 i3_t8 i5_t8 i7_t8 skip skip skip skip <=== local carry
// i0_if i2_if i4_if i6_if skip skip skip skip <=== local carry
// i1_if i3_if i5_if i7_if skip skip skip skip <=== local carry
// i0_s1x i2_s1x i4_s1x i6_s1x skip skip skip skip <=== carry select
// i1_s1x i3_s1x i5_s1x i7_s1x skip skip skip skip <=== carry select
// i0_s1y i2_s1y i4_s1y i6_s1y skip skip skip skip <=== carry select
// i1_s1y i3_s1y i5_s1y i7_s1y skip skip skip skip <=== carry select
// i0_s1 i2_s1 i4_s1 i6_s1 skip skip skip skip <=== carry select
// i1_s1 i3_s1 i5_s1 i7_s1 skip skip skip skip <=== carry select
// i0_s0b i2_s0b i4_s0b i6_s0b skip skip skip skip <=== carry select
// i1_s0b i3_s0b i5_s0b i7_s0b skip skip skip skip <=== carry select
// i0_s0 i2_s0 i4_s0 i6_s0 skip skip skip skip <=== carry select
// i1_s0 i3_s0 i5_s0 i7_s0 skip skip skip skip <=== carry select
assign x_b[0] = (~x[0]);
assign x_b[1] = (~x[1]);
assign x_b[2] = (~x[2]);
assign x_b[3] = (~x[3]);
assign x_b[4] = (~x[4]);
assign x_b[5] = (~x[5]);
assign x_b[6] = (~x[6]);
assign x_b[7] = (~x[7]);
assign x_p[0] = (~x_b[0]);
assign x_p[1] = (~x_b[1]);
assign x_p[2] = (~x_b[2]);
assign x_p[3] = (~x_b[3]);
assign x_p[4] = (~x_b[4]);
assign x_p[5] = (~x_b[5]);
assign x_p[6] = (~x_b[6]);
assign x_p[7] = (~x_b[7]);
//--------------------------------------------
assign g2_0t1_b = (~(x[0] & x[1])); //0--
assign g2_2t3_b = (~(x[2] & x[3])); //2--
assign g2_4t5_b = (~(x[4] & x[5])); //4--
assign g2_6t7_b = (~(x[6] & x[7])); //6--
assign g4_0t3 = (~(g2_0t1_b | g2_2t3_b)); //1--
assign g4_4t7 = (~(g2_4t5_b | g2_6t7_b)); //5--
assign co_b = (~(g4_0t3 & g4_4t7)); //3-- ; --output
//-------------------------------------------
assign t2_2t3 = (~(x_b[2] | x_b[3])); //2--
assign t2_4t5 = (~(x_b[4] | x_b[5])); //4--
assign t2_6t7 = (~(x_b[6] | x_b[7])); //6--
assign t4_2t5_b = (~(t2_2t3 & t2_4t5)); //3--
assign t4_4t7_b = (~(t2_4t5 & t2_6t7)); //5--
assign t4_6t7_b = (~(t2_6t7)); //7--
assign t8_2t7 = (~(t4_2t5_b | t4_6t7_b)); //3--
assign t8_4t7 = (~(t4_4t7_b)); //5--
assign t8_6t7 = (~(t4_6t7_b)); //7--
assign t8_1t7_b = (~(t8_2t7 & x_p[1])); //1--
assign t8_2t7_b = (~(t8_2t7)); //2--
assign t8_3t7_b = (~(t8_4t7 & x_p[3])); //3--
assign t8_4t7_b = (~(t8_4t7)); //4--
assign t8_5t7_b = (~(t8_6t7 & x_p[5])); //5--
assign t8_6t7_b = (~(t8_6t7)); //6--
assign t8_7t7_b = (~(x_p[7])); //7--
//------------------------------------
assign x_if_ci[0] = (~(x_p[0] ^ t8_1t7_b));
assign x_if_ci[1] = (~(x_p[1] ^ t8_2t7_b));
assign x_if_ci[2] = (~(x_p[2] ^ t8_3t7_b));
assign x_if_ci[3] = (~(x_p[3] ^ t8_4t7_b));
assign x_if_ci[4] = (~(x_p[4] ^ t8_5t7_b));
assign x_if_ci[5] = (~(x_p[5] ^ t8_6t7_b));
assign x_if_ci[6] = (~(x_p[6] ^ t8_7t7_b));
assign x_if_ci[7] = (~(x_p[7]));
assign s1x_b[0] = (~(x_p[0] & ci_b));
assign s1x_b[1] = (~(x_p[1] & ci_b));
assign s1x_b[2] = (~(x_p[2] & ci_b));
assign s1x_b[3] = (~(x_p[3] & ci_b));
assign s1x_b[4] = (~(x_p[4] & ci_b));
assign s1x_b[5] = (~(x_p[5] & ci_b));
assign s1x_b[6] = (~(x_p[6] & ci_b));
assign s1x_b[7] = (~(x_p[7] & ci_b));
assign s1y_b[0] = (~(x_if_ci[0] & ci));
assign s1y_b[1] = (~(x_if_ci[1] & ci));
assign s1y_b[2] = (~(x_if_ci[2] & ci));
assign s1y_b[3] = (~(x_if_ci[3] & ci));
assign s1y_b[4] = (~(x_if_ci[4] & ci));
assign s1y_b[5] = (~(x_if_ci[5] & ci));
assign s1y_b[6] = (~(x_if_ci[6] & ci));
assign s1y_b[7] = (~(x_if_ci[7] & ci));
assign s1[0] = (~(s1x_b[0] & s1y_b[0])); //output
assign s1[1] = (~(s1x_b[1] & s1y_b[1])); //output
assign s1[2] = (~(s1x_b[2] & s1y_b[2])); //output
assign s1[3] = (~(s1x_b[3] & s1y_b[3])); //output
assign s1[4] = (~(s1x_b[4] & s1y_b[4])); //output
assign s1[5] = (~(s1x_b[5] & s1y_b[5])); //output
assign s1[6] = (~(s1x_b[6] & s1y_b[6])); //output
assign s1[7] = (~(s1x_b[7] & s1y_b[7])); //output
assign s0_b[0] = (~x_p[0]);
assign s0_b[1] = (~x_p[1]);
assign s0_b[2] = (~x_p[2]);
assign s0_b[3] = (~x_p[3]);
assign s0_b[4] = (~x_p[4]);
assign s0_b[5] = (~x_p[5]);
assign s0_b[6] = (~x_p[6]);
assign s0_b[7] = (~x_p[7]);
assign s0[0] = (~s0_b[0]); // output
assign s0[1] = (~s0_b[1]); // output
assign s0[2] = (~s0_b[2]); // output
assign s0[3] = (~s0_b[3]); // output
assign s0[4] = (~s0_b[4]); // output
assign s0[5] = (~s0_b[5]); // output
assign s0[6] = (~s0_b[6]); // output
assign s0[7] = (~s0_b[7]); // output
endmodule |
module fu_gst_loa(
a,
shamt
);
`include "tri_a2o.vh"
input [1:19] a;
output [0:4] shamt;
wire unused;
assign unused = a[19];
//@@ ESPRESSO TABLE START @@
// ##################################################################################################
// ##################################################################################################
// .i 19
// .o 5
// .ilb a(01) a(02) a(03) a(04) a(05) a(06) a(07) a(08) a(09) a(10) a(11) a(12) a(13) a(14) a(15) a(16) a(17) a(18) a(19)
// .ob shamt(0) shamt(1) shamt(2) shamt(3) shamt(4)
// .type fr
////#######################
//
// 0000000000000000001 10011
// 000000000000000001- 10010
// 00000000000000001-- 10001
// 0000000000000001--- 10000
// 000000000000001---- 01111
// 00000000000001----- 01110
// 0000000000001------ 01101
// 000000000001------- 01100
// 00000000001-------- 01011
// 0000000001--------- 01010
// 000000001---------- 01001
// 00000001----------- 01000
// 0000001------------ 00111
// 000001------------- 00110
// 00001-------------- 00101
// 0001--------------- 00100
// 001---------------- 00011
// 01----------------- 00010
// 1------------------ 00001
// 0000000000000000000 00000
// ###############################################################################
// .e
//@@ ESPRESSO TABLE END @@
//@@ ESPRESSO LOGIC START @@
// logic generated on: Tue Dec 4 13:14:17 2007
assign shamt[0] = ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & (~a[12]) & (~a[13]) & (~a[14]) & (~a[15]) & a[19]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & (~a[12]) & (~a[13]) & (~a[14]) & (~a[15]) & a[18]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & (~a[12]) & (~a[13]) & (~a[14]) & (~a[15]) & a[17]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & (~a[12]) & (~a[13]) & (~a[14]) & (~a[15]) & a[16]);
assign shamt[1] = ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[15]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[14]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[13]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[12]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[11]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[10]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[09]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[08]);
assign shamt[2] = ((~a[01]) & (~a[02]) & (~a[03]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & a[15]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & a[14]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & a[13]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & a[12]) | ((~a[01]) & (~a[02]) & (~a[03]) & a[07]) | ((~a[01]) & (~a[02]) & (~a[03]) & a[06]) | ((~a[01]) & (~a[02]) & (~a[03]) & a[05]) | ((~a[01]) & (~a[02]) & (~a[03]) & a[04]);
assign shamt[3] = ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & (~a[12]) & (~a[13]) & (~a[16]) & (~a[17]) & a[19]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & (~a[12]) & (~a[13]) & (~a[16]) & (~a[17]) & a[18]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & (~a[12]) & (~a[13]) & a[15]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & (~a[12]) & (~a[13]) & a[14]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & a[11]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & a[10]) | ((~a[01]) & (~a[04]) & (~a[05]) & a[07]) | ((~a[01]) & (~a[04]) & (~a[05]) & a[06]) | ((~a[01]) & a[03]) | ((~a[01]) & a[02]);
assign shamt[4] = ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & (~a[12]) & (~a[14]) & (~a[16]) & (~a[18]) & a[19]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & (~a[12]) & (~a[14]) & (~a[16]) & a[17]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & (~a[12]) & (~a[14]) & a[15]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & (~a[12]) & a[13]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & a[11]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & a[09]) | ((~a[02]) & (~a[04]) & (~a[06]) & a[07]) | ((~a[02]) & (~a[04]) & a[05]) | ((~a[02]) & a[03]) | (a[01]);
endmodule |
module pcq_regs_fir(
// Include model build parameters
`include "tri_a2o.vh"
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input lcb_clkoff_dc_b,
input lcb_mpw1_dc_b,
input lcb_mpw2_dc_b,
input lcb_delay_lclkr_dc,
input lcb_act_dis_dc,
input lcb_sg_0,
input lcb_func_slp_sl_thold_0,
input lcb_cfg_slp_sl_thold_0,
input cfgslp_d1clk,
input cfgslp_d2clk,
input [0:`NCLK_WIDTH-1] cfgslp_lclk,
input cfg_slat_d2clk,
input [0:`NCLK_WIDTH-1] cfg_slat_lclk,
input bcfg_scan_in,
output bcfg_scan_out,
input func_scan_in,
output func_scan_out,
// SCOM Satellite Interface
input sc_active,
input sc_wr_q,
input [0:63] sc_addr_v,
input [0:63] sc_wdata,
output [0:63] sc_rdata,
// FIR and Error Signals
output [0:2] ac_an_checkstop,
output [0:2] ac_an_local_checkstop,
output [0:2] ac_an_recov_err,
output ac_an_trace_error,
output rg_rg_any_fir_xstop,
output ac_an_livelock_active,
input an_ac_checkstop,
input iu_pc_err_icache_parity,
input iu_pc_err_icachedir_parity,
input iu_pc_err_icachedir_multihit,
input lq_pc_err_dcache_parity,
input lq_pc_err_dcachedir_ldp_parity,
input lq_pc_err_dcachedir_stp_parity,
input lq_pc_err_dcachedir_ldp_multihit,
input lq_pc_err_dcachedir_stp_multihit,
input iu_pc_err_ierat_parity,
input iu_pc_err_ierat_multihit,
input iu_pc_err_btb_parity,
input lq_pc_err_derat_parity,
input lq_pc_err_derat_multihit,
input mm_pc_err_tlb_parity,
input mm_pc_err_tlb_multihit,
input mm_pc_err_tlb_lru_parity,
input mm_pc_err_local_snoop_reject,
input lq_pc_err_l2intrf_ecc,
input lq_pc_err_l2intrf_ue,
input lq_pc_err_invld_reld,
input lq_pc_err_l2credit_overrun,
input [0:1] scom_reg_par_checks,
input scom_sat_fsm_error,
input scom_ack_error,
input lq_pc_err_prefetcher_parity,
input lq_pc_err_relq_parity,
input [0:`THREADS-1] xu_pc_err_sprg_ecc,
input [0:`THREADS-1] xu_pc_err_sprg_ue,
input [0:`THREADS-1] xu_pc_err_regfile_parity,
input [0:`THREADS-1] xu_pc_err_regfile_ue,
input [0:`THREADS-1] lq_pc_err_regfile_parity,
input [0:`THREADS-1] lq_pc_err_regfile_ue,
input [0:`THREADS-1] fu_pc_err_regfile_parity,
input [0:`THREADS-1] fu_pc_err_regfile_ue,
input [0:`THREADS-1] iu_pc_err_cpArray_parity,
input [0:`THREADS-1] iu_pc_err_ucode_illegal,
input [0:`THREADS-1] iu_pc_err_mchk_disabled,
input [0:`THREADS-1] xu_pc_err_llbust_attempt,
input [0:`THREADS-1] xu_pc_err_llbust_failed,
input [0:`THREADS-1] xu_pc_err_wdt_reset,
input [0:`THREADS-1] iu_pc_err_debug_event,
input rg_rg_ram_mode,
output rg_rg_ram_mode_xstop,
input rg_rg_xstop_report_ovride,
output [0:`THREADS-1] rg_rg_xstop_err,
input sc_parity_error_inject,
output [0:22+9*(`THREADS-1)] rg_rg_errinj_shutoff,
input rg_rg_maxRecErrCntrValue,
output rg_rg_gateRecErrCntr,
input [0:31] errDbg_out,
// Trace/Trigger Signals
output [0:27] dbg_fir0_err,
output [0:19] dbg_fir1_err,
output [0:19] dbg_fir2_err,
output [0:14] dbg_fir_misc
);
//=====================================================================
// Signal Declarations
//=====================================================================
// FIR0 Init Values
parameter FIR0_WIDTH = 28;
parameter FIR0_INIT = 28'h0000000;
parameter FIR0MASK_INIT = 28'hFFFFFFF;
parameter FIR0MASK_PAR_INIT = 1'b0;
parameter FIR0ACT0_INIT = 28'h0000390;
parameter FIR0ACT0_PAR_INIT = 1'b0;
parameter FIR0ACT1_INIT = 28'hFFFFFFE;
parameter FIR0ACT1_PAR_INIT = 1'b1;
// FIR1 Init Values
parameter FIR1_WIDTH = 20;
parameter FIR1_INIT = 20'h00000;
parameter FIR1MASK_INIT = 20'hFFFFF;
parameter FIR1MASK_PAR_INIT = 1'b0;
parameter FIR1ACT0_INIT = 20'h55660;
parameter FIR1ACT0_PAR_INIT = 1'b0;
parameter FIR1ACT1_INIT = 20'hFFFE0;
parameter FIR1ACT1_PAR_INIT = 1'b1;
// FIR2 Init Values
`ifdef THREADS1
parameter FIR2_WIDTH = 1;
parameter FIR2_INIT = 1'b0;
parameter FIR2MASK_INIT = 1'b1;
parameter FIR2MASK_PAR_INIT = 1'b1;
parameter FIR2ACT0_INIT = 1'b0;
parameter FIR2ACT0_PAR_INIT = 1'b0;
parameter FIR2ACT1_INIT = 1'b0;
parameter FIR2ACT1_PAR_INIT = 1'b0;
`else
parameter FIR2_WIDTH = 20;
parameter FIR2_INIT = 20'h00000;
parameter FIR2MASK_INIT = 20'hFFFFF;
parameter FIR2MASK_PAR_INIT = 1'b0;
parameter FIR2ACT0_INIT = 20'h55660;
parameter FIR2ACT0_PAR_INIT = 1'b0;
parameter FIR2ACT1_INIT = 20'hFFFE0;
parameter FIR2ACT1_PAR_INIT = 1'b1;
`endif
// Common Init Values
parameter SCPAR_ERR_RPT_WIDTH = 11;
parameter SCPAR_RPT_RESET_VALUE = 11'b00000000000;
parameter SCACK_ERR_RPT_WIDTH = 2;
parameter SCACK_RPT_RESET_VALUE = 2'b00;
parameter SCRDATA_SIZE = 64;
// Scan Ring Ordering:
parameter FIR0_BCFG_SIZE = 3 * (FIR0_WIDTH + 1) + FIR0_WIDTH;
parameter FIR1_BCFG_SIZE = 3 * (FIR1_WIDTH + 1) + FIR1_WIDTH;
parameter FIR2_BCFG_SIZE = 3 * (FIR2_WIDTH + 1) + FIR2_WIDTH;
parameter FIR0_FUNC_SIZE = 5;
parameter FIR1_FUNC_SIZE = 5;
parameter FIR2_FUNC_SIZE = 5;
parameter ERROUT_FUNC_SIZE = 30;
// START OF BCFG SCAN CHAIN ORDERING
parameter BCFG_FIR0_OFFSET = 0;
parameter BCFG_FIR1_OFFSET = BCFG_FIR0_OFFSET + FIR0_BCFG_SIZE;
parameter BCFG_FIR2_OFFSET = BCFG_FIR1_OFFSET + FIR1_BCFG_SIZE;
parameter BCFG_ERPT1_HLD_OFFSET = BCFG_FIR2_OFFSET + FIR2_BCFG_SIZE;
parameter BCFG_ERPT1_MSK_OFFSET = BCFG_ERPT1_HLD_OFFSET + SCPAR_ERR_RPT_WIDTH;
parameter BCFG_ERPT2_HLD_OFFSET = BCFG_ERPT1_MSK_OFFSET + SCPAR_ERR_RPT_WIDTH;
parameter BCFG_ERPT2_MSK_OFFSET = BCFG_ERPT2_HLD_OFFSET + SCACK_ERR_RPT_WIDTH;
parameter BCFG_RIGHT = BCFG_ERPT2_MSK_OFFSET + SCACK_ERR_RPT_WIDTH - 1;
// END OF BCFG SCAN CHAIN ORDERING
// START OF FUNC SCAN CHAIN ORDERING
parameter FUNC_FIR0_OFFSET = 0;
parameter FUNC_FIR1_OFFSET = FUNC_FIR0_OFFSET + FIR0_FUNC_SIZE;
parameter FUNC_FIR2_OFFSET = FUNC_FIR1_OFFSET + FIR1_FUNC_SIZE;
parameter FUNC_ERROUT_OFFSET = FUNC_FIR2_OFFSET + FIR2_FUNC_SIZE;
parameter FUNC_F0ERR_OFFSET = FUNC_ERROUT_OFFSET + ERROUT_FUNC_SIZE;
parameter FUNC_F1ERR_OFFSET = FUNC_F0ERR_OFFSET + FIR0_WIDTH;
parameter FUNC_F2ERR_OFFSET = FUNC_F1ERR_OFFSET + FIR1_WIDTH;
parameter FUNC_RIGHT = FUNC_F2ERR_OFFSET + FIR2_WIDTH - 1;
// end of func scan chain ordering
//---------------------------------------------------------------------
// Basic/Misc signals
wire tidn;
wire tiup;
wire [0:31] tidn_32;
// Clocks
wire func_d1clk;
wire func_d2clk;
wire [0:`NCLK_WIDTH-1] func_lclk;
wire func_thold_b;
wire func_force;
// SCOM
wire [0:63] scomErr_errDbg_status;
wire [0:SCPAR_ERR_RPT_WIDTH-1] sc_reg_par_err_in;
wire [0:SCPAR_ERR_RPT_WIDTH-1] sc_reg_par_err_out;
wire [0:SCPAR_ERR_RPT_WIDTH-1] sc_reg_par_err_out_q;
wire [0:SCPAR_ERR_RPT_WIDTH-1] sc_reg_par_err_hold;
wire scom_reg_parity_err;
wire fir_regs_parity_err;
wire [0:SCACK_ERR_RPT_WIDTH-1] sc_reg_ack_err_in;
wire [0:SCACK_ERR_RPT_WIDTH-1] sc_reg_ack_err_out;
wire [0:SCACK_ERR_RPT_WIDTH-1] sc_reg_ack_err_out_q;
wire [0:SCACK_ERR_RPT_WIDTH-1] sc_reg_ack_err_hold;
wire scom_reg_ack_err;
// FIR0
wire [0:FIR0_WIDTH-1] fir0_errors;
wire [0:FIR0_WIDTH-1] fir0_errors_q;
wire [0:FIR0_WIDTH-1] fir0_fir_out;
wire [0:FIR0_WIDTH-1] fir0_act0_out;
wire [0:FIR0_WIDTH-1] fir0_act1_out;
wire [0:FIR0_WIDTH-1] fir0_mask_out;
wire [0:FIR0_WIDTH-1] fir0_scrdata;
wire [0:31] fir0_fir_scom_out;
wire [0:31] fir0_act0_scom_out;
wire [0:31] fir0_act1_scom_out;
wire [0:31] fir0_mask_scom_out;
wire fir0_xstop_err;
wire fir0_recov_err;
wire fir0_lxstop_mchk;
wire fir0_trace_error;
wire fir0_block_on_checkstop;
wire [0:2] fir0_fir_parity_check;
wire [0:FIR0_WIDTH-1] fir0_recoverable_errors;
wire [0:1] fir0_recov_err_in;
wire [0:1] fir0_recov_err_q;
wire fir0_recov_err_pulse;
wire [32:32+FIR0_WIDTH-1] fir0_enabled_checkstops;
// FIR1
wire [0:FIR1_WIDTH-1] fir1_errors;
wire [0:FIR1_WIDTH-1] fir1_errors_q;
wire [0:FIR1_WIDTH-1] fir1_fir_out;
wire [0:FIR1_WIDTH-1] fir1_act0_out;
wire [0:FIR1_WIDTH-1] fir1_act1_out;
wire [0:FIR1_WIDTH-1] fir1_mask_out;
wire [0:FIR1_WIDTH-1] fir1_scrdata;
wire [0:31] fir1_fir_scom_out;
wire [0:31] fir1_act0_scom_out;
wire [0:31] fir1_act1_scom_out;
wire [0:31] fir1_mask_scom_out;
wire fir1_xstop_err;
wire fir1_recov_err;
wire fir1_lxstop_mchk;
wire fir1_trace_error;
wire fir1_block_on_checkstop;
wire [0:2] fir1_fir_parity_check;
wire [0:FIR1_WIDTH-1] fir1_recoverable_errors;
wire [0:1] fir1_recov_err_in;
wire [0:1] fir1_recov_err_q;
wire fir1_recov_err_pulse;
wire [32:32+FIR1_WIDTH-1] fir1_enabled_checkstops;
// FIR2
wire [0:FIR2_WIDTH-1] fir2_errors;
wire [0:FIR2_WIDTH-1] fir2_errors_q;
wire [0:FIR2_WIDTH-1] fir2_fir_out;
wire [0:FIR2_WIDTH-1] fir2_act0_out;
wire [0:FIR2_WIDTH-1] fir2_act1_out;
wire [0:FIR2_WIDTH-1] fir2_mask_out;
wire [0:FIR2_WIDTH-1] fir2_scrdata;
wire [0:31] fir2_fir_scom_out;
wire [0:31] fir2_act0_scom_out;
wire [0:31] fir2_act1_scom_out;
wire [0:31] fir2_mask_scom_out;
wire fir2_xstop_err;
wire fir2_recov_err;
wire fir2_lxstop_mchk;
wire fir2_trace_error;
wire fir2_block_on_checkstop;
wire [0:2] fir2_fir_parity_check;
wire [0:FIR2_WIDTH-1] fir2_recoverable_errors;
wire [0:1] fir2_recov_err_in;
wire [0:1] fir2_recov_err_q;
wire fir2_recov_err_pulse;
wire [32:32+FIR2_WIDTH-1] fir2_enabled_checkstops;
// Error Inject Shutoff
wire injoff_icache_parity;
wire injoff_icachedir_parity;
wire injoff_icachedir_multihit;
wire injoff_dcache_parity;
wire injoff_dcachedir_ldp_parity;
wire injoff_dcachedir_stp_parity;
wire injoff_dcachedir_ldp_multihit;
wire injoff_dcachedir_stp_multihit;
wire injoff_scomreg_parity;
wire injoff_prefetcher_parity;
wire injoff_relq_parity;
wire injoff_sprg_ecc_t0;
wire injoff_fx0regfile_par_t0;
wire injoff_fx1regfile_par_t0;
wire injoff_lqregfile_par_t0;
wire injoff_furegfile_par_t0;
wire injoff_cpArray_par_t0;
wire injoff_llbust_attempt_t0;
wire injoff_llbust_failed_t0;
wire injoff_sprg_ecc_t1;
wire injoff_fx0regfile_par_t1;
wire injoff_fx1regfile_par_t1;
wire injoff_lqregfile_par_t1;
wire injoff_furegfile_par_t1;
wire injoff_cpArray_par_t1;
wire injoff_llbust_attempt_t1;
wire injoff_llbust_failed_t1;
wire [0:22+9*(`THREADS-1)] error_inject_shutoff;
// MISC
wire [0:2] recov_err_int;
wire [0:2] xstop_err_int;
wire [0:2] xstop_err_q;
wire [0:2] xstop_out_d;
wire [0:2] xstop_out_q;
wire [0:2] lxstop_err_int;
wire [0:2] lxstop_out_d;
wire [0:2] lxstop_out_q;
wire xstop_err_common;
wire [0:`THREADS-1] xstop_err_per_thread;
wire [0:1] dbg_thread_xstop_err;
wire any_fir_xstop_int;
wire an_ac_checkstop_q;
wire maxRecErrCntrValue_errrpt;
wire block_xstop_in_ram_mode;
wire livelock_active_d;
wire livelock_active_q;
wire [0:BCFG_RIGHT] bcfg_siv;
wire [0:BCFG_RIGHT] bcfg_sov;
wire [0:FUNC_RIGHT] func_siv;
wire [0:FUNC_RIGHT] func_sov;
// Get rid of sinkless net messages
// synopsys translate_off
(* analysis_not_referenced="true" *)
// synopsys translate_on
wire unused_signals;
assign unused_signals = ((|fir0_scrdata) | (|fir1_scrdata) | (|fir2_scrdata ) | fir0_recoverable_errors[0] |
sc_addr_v[9] | sc_addr_v[19] | (|sc_addr_v[29:63]) | (|sc_wdata[0:31]));
//---------------------------------------------------------------------
//!! Bugspray Include: pcq_regs_fir;
assign tiup = 1'b1;
assign tidn = 1'b0;
assign tidn_32 = {32{1'b0}};
//=====================================================================
// FIR0 Instantiation
//=====================================================================
pcq_local_fir2 #(
.WIDTH(FIR0_WIDTH),
.IMPL_LXSTOP_MCHK(1'b1),
.USE_RECOV_RESET(1'b0),
.FIR_INIT(FIR0_INIT),
.FIR_MASK_INIT(FIR0MASK_INIT),
.FIR_MASK_PAR_INIT(FIR0MASK_PAR_INIT),
.FIR_ACTION0_INIT(FIR0ACT0_INIT),
.FIR_ACTION0_PAR_INIT(FIR0ACT0_PAR_INIT),
.FIR_ACTION1_INIT(FIR0ACT1_INIT),
.FIR_ACTION1_PAR_INIT(FIR0ACT1_PAR_INIT)
) FIR0(
// Global lines for clocking and scan control
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.lcb_clkoff_dc_b(lcb_clkoff_dc_b),
.lcb_mpw1_dc_b(lcb_mpw1_dc_b),
.lcb_mpw2_dc_b(lcb_mpw2_dc_b),
.lcb_delay_lclkr_dc(lcb_delay_lclkr_dc),
.lcb_act_dis_dc(lcb_act_dis_dc),
.lcb_sg_0(lcb_sg_0),
.lcb_func_slp_sl_thold_0(lcb_func_slp_sl_thold_0), // not power-managed
.lcb_cfg_slp_sl_thold_0(lcb_cfg_slp_sl_thold_0), // not power-managed
.mode_scan_siv(bcfg_siv[BCFG_FIR0_OFFSET:BCFG_FIR0_OFFSET + FIR0_BCFG_SIZE - 1]),
.mode_scan_sov(bcfg_sov[BCFG_FIR0_OFFSET:BCFG_FIR0_OFFSET + FIR0_BCFG_SIZE - 1]),
.func_scan_siv(func_siv[FUNC_FIR0_OFFSET:FUNC_FIR0_OFFSET + FIR0_FUNC_SIZE - 1]),
.func_scan_sov(func_sov[FUNC_FIR0_OFFSET:FUNC_FIR0_OFFSET + FIR0_FUNC_SIZE - 1]),
// external interface
.error_in(fir0_errors_q), // needs to be directly off a latch for timing
.xstop_err(fir0_xstop_err), // checkstop output to Global FIR
.recov_err(fir0_recov_err), // recoverable output to Global FIR
.lxstop_mchk(fir0_lxstop_mchk), // use ONLY if impl_lxstop_mchk = true
.trace_error(fir0_trace_error), // connect to error_input of closest trdata macro
.sys_xstop_in(fir0_block_on_checkstop), // freeze FIR on other checkstop errors
.recov_reset(tidn), // only needed if use_recov_reset = true
.fir_out(fir0_fir_out), // output of current FIR state if needed
.act0_out(fir0_act0_out), // output of current FIR ACT0 if needed
.act1_out(fir0_act1_out), // output of current FIR ACT1 if needed
.mask_out(fir0_mask_out), // output of current FIR MASK if needed
// scom register connections
.sc_parity_error_inject(sc_parity_error_inject), // Force parity error
.sc_active(sc_active),
.sc_wr_q(sc_wr_q),
.sc_addr_v(sc_addr_v[0:8]),
.sc_wdata(sc_wdata[32:32 + FIR0_WIDTH - 1]),
.sc_rdata(fir0_scrdata),
.fir_parity_check(fir0_fir_parity_check)
);
//---------------------------------------------------------------------
// Error Input Facility
assign fir0_errors = {
maxRecErrCntrValue_errrpt, iu_pc_err_icache_parity, // 0:1
iu_pc_err_icachedir_parity, iu_pc_err_icachedir_multihit, // 2:3
lq_pc_err_dcache_parity, lq_pc_err_dcachedir_ldp_parity, // 4:5
lq_pc_err_dcachedir_stp_parity, lq_pc_err_dcachedir_ldp_multihit, // 6:7
lq_pc_err_dcachedir_stp_multihit, iu_pc_err_ierat_parity, // 8:9
iu_pc_err_ierat_multihit, lq_pc_err_derat_parity, // 10:11
lq_pc_err_derat_multihit, mm_pc_err_tlb_parity, // 12:13
mm_pc_err_tlb_multihit, mm_pc_err_tlb_lru_parity, // 14:15
mm_pc_err_local_snoop_reject, lq_pc_err_l2intrf_ecc, // 16:17
lq_pc_err_l2intrf_ue, lq_pc_err_invld_reld, // 18:19
lq_pc_err_l2credit_overrun, scom_reg_parity_err, // 20:21
scom_reg_ack_err, fir_regs_parity_err, // 22:23
lq_pc_err_prefetcher_parity, lq_pc_err_relq_parity, // 24:25
iu_pc_err_btb_parity, fir0_errors_q[27] // 26:27 (spares: wrapback dout=>din)
};
//---------------------------------------------------------------------
// Block FIR on checkstop (external input or from other FIRs)
assign fir0_block_on_checkstop = an_ac_checkstop_q | xstop_err_q[1] | xstop_err_q[2];
//=====================================================================
// FIR1 Instantiation
//=====================================================================
pcq_local_fir2 #(
.WIDTH(FIR1_WIDTH),
.IMPL_LXSTOP_MCHK(1'b1),
.USE_RECOV_RESET(1'b0),
.FIR_INIT(FIR1_INIT),
.FIR_MASK_INIT(FIR1MASK_INIT),
.FIR_MASK_PAR_INIT(FIR1MASK_PAR_INIT),
.FIR_ACTION0_INIT(FIR1ACT0_INIT),
.FIR_ACTION0_PAR_INIT(FIR1ACT0_PAR_INIT),
.FIR_ACTION1_INIT(FIR1ACT1_INIT),
.FIR_ACTION1_PAR_INIT(FIR1ACT1_PAR_INIT)
) FIR1(
// Global lines for clocking and scan control
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.lcb_clkoff_dc_b(lcb_clkoff_dc_b),
.lcb_mpw1_dc_b(lcb_mpw1_dc_b),
.lcb_mpw2_dc_b(lcb_mpw2_dc_b),
.lcb_delay_lclkr_dc(lcb_delay_lclkr_dc),
.lcb_act_dis_dc(lcb_act_dis_dc),
.lcb_sg_0(lcb_sg_0),
.lcb_func_slp_sl_thold_0(lcb_func_slp_sl_thold_0), // not power-managed
.lcb_cfg_slp_sl_thold_0(lcb_cfg_slp_sl_thold_0), // not power-managed
.mode_scan_siv(bcfg_siv[BCFG_FIR1_OFFSET:BCFG_FIR1_OFFSET + FIR1_BCFG_SIZE - 1]),
.mode_scan_sov(bcfg_sov[BCFG_FIR1_OFFSET:BCFG_FIR1_OFFSET + FIR1_BCFG_SIZE - 1]),
.func_scan_siv(func_siv[FUNC_FIR1_OFFSET:FUNC_FIR1_OFFSET + FIR1_FUNC_SIZE - 1]),
.func_scan_sov(func_sov[FUNC_FIR1_OFFSET:FUNC_FIR1_OFFSET + FIR1_FUNC_SIZE - 1]),
// external interface
.error_in(fir1_errors_q), // needs to be directly off a latch for timing
.xstop_err(fir1_xstop_err), // checkstop output to Global FIR
.recov_err(fir1_recov_err), // recoverable output to Global FIR
.lxstop_mchk(fir1_lxstop_mchk), // use ONLY if impl_lxstop_mchk = true
.trace_error(fir1_trace_error), // connect to error_input of closest trdata macro
.sys_xstop_in(fir1_block_on_checkstop), // freeze FIR on other checkstop errors
.recov_reset(tidn), // only needed if use_recov_reset = true
.fir_out(fir1_fir_out), // output of current FIR state if needed
.act0_out(fir1_act0_out), // output of current FIR ACT0 if needed
.act1_out(fir1_act1_out), // output of current FIR ACT1 if needed
.mask_out(fir1_mask_out), // output of current FIR MASK if needed
// scom register connections
.sc_parity_error_inject(sc_parity_error_inject), // Force parity error
.sc_active(sc_active),
.sc_wr_q(sc_wr_q),
.sc_addr_v(sc_addr_v[10:18]),
.sc_wdata(sc_wdata[32:32 + FIR1_WIDTH - 1]),
.sc_rdata(fir1_scrdata),
.fir_parity_check(fir1_fir_parity_check)
);
//---------------------------------------------------------------------
// Error Input Facility
assign fir1_errors = {
xu_pc_err_sprg_ecc[0], xu_pc_err_sprg_ue[0], // 0:1
xu_pc_err_regfile_parity[0], xu_pc_err_regfile_ue[0], // 2:3
lq_pc_err_regfile_parity[0], lq_pc_err_regfile_ue[0], // 4:5
fu_pc_err_regfile_parity[0], fu_pc_err_regfile_ue[0], // 6:7
iu_pc_err_cpArray_parity[0], iu_pc_err_ucode_illegal[0], // 8:9
iu_pc_err_mchk_disabled[0], xu_pc_err_llbust_attempt[0], // 10:11
xu_pc_err_llbust_failed[0], xu_pc_err_wdt_reset[0], // 12:13
iu_pc_err_debug_event[0], fir1_errors_q[15:19] // 14:19 (spares: wrapback dout=>din)
};
//---------------------------------------------------------------------
// Block FIR on checkstop (external input or from other FIRs)
assign fir1_block_on_checkstop = an_ac_checkstop_q | xstop_err_q[0] | xstop_err_q[2];
//=====================================================================
// FIR2 Instantiation
//=====================================================================
pcq_local_fir2 #(
.WIDTH(FIR2_WIDTH),
.IMPL_LXSTOP_MCHK(1'b1),
.USE_RECOV_RESET(1'b0),
.FIR_INIT(FIR2_INIT),
.FIR_MASK_INIT(FIR2MASK_INIT),
.FIR_MASK_PAR_INIT(FIR2MASK_PAR_INIT),
.FIR_ACTION0_INIT(FIR2ACT0_INIT),
.FIR_ACTION0_PAR_INIT(FIR2ACT0_PAR_INIT),
.FIR_ACTION1_INIT(FIR2ACT1_INIT),
.FIR_ACTION1_PAR_INIT(FIR2ACT1_PAR_INIT)
) FIR2(
// Global lines for clocking and scan control
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.lcb_clkoff_dc_b(lcb_clkoff_dc_b),
.lcb_mpw1_dc_b(lcb_mpw1_dc_b),
.lcb_mpw2_dc_b(lcb_mpw2_dc_b),
.lcb_delay_lclkr_dc(lcb_delay_lclkr_dc),
.lcb_act_dis_dc(lcb_act_dis_dc),
.lcb_sg_0(lcb_sg_0),
.lcb_func_slp_sl_thold_0(lcb_func_slp_sl_thold_0), // not power-managed
.lcb_cfg_slp_sl_thold_0(lcb_cfg_slp_sl_thold_0), // not power-managed
.mode_scan_siv(bcfg_siv[BCFG_FIR2_OFFSET:BCFG_FIR2_OFFSET + FIR2_BCFG_SIZE - 1]),
.mode_scan_sov(bcfg_sov[BCFG_FIR2_OFFSET:BCFG_FIR2_OFFSET + FIR2_BCFG_SIZE - 1]),
.func_scan_siv(func_siv[FUNC_FIR2_OFFSET:FUNC_FIR2_OFFSET + FIR2_FUNC_SIZE - 1]),
.func_scan_sov(func_sov[FUNC_FIR2_OFFSET:FUNC_FIR2_OFFSET + FIR2_FUNC_SIZE - 1]),
// external interface
.error_in(fir2_errors_q), // needs to be directly off a latch for timing
.xstop_err(fir2_xstop_err), // checkstop output to Global FIR
.recov_err(fir2_recov_err), // recoverable output to Global FIR
.lxstop_mchk(fir2_lxstop_mchk), // use ONLY if impl_lxstop_mchk = true
.trace_error(fir2_trace_error), // connect to error_input of closest trdata macro
.sys_xstop_in(fir2_block_on_checkstop), // freeze FIR on other checkstop errors
.recov_reset(tidn), // only needed if use_recov_reset = true
.fir_out(fir2_fir_out), // output of current FIR state if needed
.act0_out(fir2_act0_out), // output of current FIR ACT0 if needed
.act1_out(fir2_act1_out), // output of current FIR ACT1 if needed
.mask_out(fir2_mask_out), // output of current FIR MASK if needed
// scom register connections
.sc_parity_error_inject(sc_parity_error_inject), // Force parity error
.sc_active(sc_active),
.sc_wr_q(sc_wr_q),
.sc_addr_v(sc_addr_v[20:28]),
.sc_wdata(sc_wdata[32:32 + FIR2_WIDTH - 1]),
.sc_rdata(fir2_scrdata),
.fir_parity_check(fir2_fir_parity_check)
);
//---------------------------------------------------------------------
// Error Input Facility
generate
if (`THREADS == 1)
begin : FIR2ERR_1T
assign fir2_errors = 1'b0;
end
endgenerate
generate
if (`THREADS == 2)
begin : FIR2ERR_2T
assign fir2_errors = {
xu_pc_err_sprg_ecc[1], xu_pc_err_sprg_ue[1], // 0:1
xu_pc_err_regfile_parity[1], xu_pc_err_regfile_ue[1], // 2:3
lq_pc_err_regfile_parity[1], lq_pc_err_regfile_ue[1], // 4:5
fu_pc_err_regfile_parity[1], fu_pc_err_regfile_ue[1], // 6:7
iu_pc_err_cpArray_parity[1], iu_pc_err_ucode_illegal[1], // 8:9
iu_pc_err_mchk_disabled[1], xu_pc_err_llbust_attempt[1], // 10:11
xu_pc_err_llbust_failed[1], xu_pc_err_wdt_reset[1], // 12:13
iu_pc_err_debug_event[1], fir2_errors_q[15:19] // 14:19 (spares: wrapback dout=>din)
};
end
endgenerate
//---------------------------------------------------------------------
// Block FIR on checkstop (external input or from other FIRs)
assign fir2_block_on_checkstop = an_ac_checkstop_q | xstop_err_q[0] | xstop_err_q[1];
//=====================================================================
// SCOM Register Read
//=====================================================================
assign scomErr_errDbg_status = { sc_reg_par_err_hold[0:SCPAR_ERR_RPT_WIDTH - 1],
sc_reg_ack_err_hold[0:SCACK_ERR_RPT_WIDTH - 1],
{32-(SCPAR_ERR_RPT_WIDTH+SCACK_ERR_RPT_WIDTH) {1'b0}},
errDbg_out
};
assign fir0_fir_scom_out = {fir0_fir_out, {32-FIR0_WIDTH {1'b0}}};
assign fir0_act0_scom_out = {fir0_act0_out, {32-FIR0_WIDTH {1'b0}}};
assign fir0_act1_scom_out = {fir0_act1_out, {32-FIR0_WIDTH {1'b0}}};
assign fir0_mask_scom_out = {fir0_mask_out, {32-FIR0_WIDTH {1'b0}}};
assign fir1_fir_scom_out = {fir1_fir_out, {32-FIR1_WIDTH {1'b0}}};
assign fir1_act0_scom_out = {fir1_act0_out, {32-FIR1_WIDTH {1'b0}}};
assign fir1_act1_scom_out = {fir1_act1_out, {32-FIR1_WIDTH {1'b0}}};
assign fir1_mask_scom_out = {fir1_mask_out, {32-FIR1_WIDTH {1'b0}}};
assign fir2_fir_scom_out = {fir2_fir_out, {32-FIR2_WIDTH {1'b0}}};
assign fir2_act0_scom_out = {fir2_act0_out, {32-FIR2_WIDTH {1'b0}}};
assign fir2_act1_scom_out = {fir2_act1_out, {32-FIR2_WIDTH {1'b0}}};
assign fir2_mask_scom_out = {fir2_mask_out, {32-FIR2_WIDTH {1'b0}}};
assign sc_rdata[0:SCRDATA_SIZE-1] =
({SCRDATA_SIZE {sc_addr_v[0] }} & {tidn_32, fir0_fir_scom_out }) |
({SCRDATA_SIZE {sc_addr_v[3] }} & {tidn_32, fir0_act0_scom_out}) |
({SCRDATA_SIZE {sc_addr_v[4] }} & {tidn_32, fir0_act1_scom_out}) |
({SCRDATA_SIZE {sc_addr_v[6] }} & {tidn_32, fir0_mask_scom_out}) |
({SCRDATA_SIZE {sc_addr_v[10]}} & {tidn_32, fir1_fir_scom_out }) |
({SCRDATA_SIZE {sc_addr_v[13]}} & {tidn_32, fir1_act0_scom_out}) |
({SCRDATA_SIZE {sc_addr_v[14]}} & {tidn_32, fir1_act1_scom_out}) |
({SCRDATA_SIZE {sc_addr_v[16]}} & {tidn_32, fir1_mask_scom_out}) |
({SCRDATA_SIZE {sc_addr_v[20]}} & {tidn_32, fir2_fir_scom_out }) |
({SCRDATA_SIZE {sc_addr_v[23]}} & {tidn_32, fir2_act0_scom_out}) |
({SCRDATA_SIZE {sc_addr_v[24]}} & {tidn_32, fir2_act1_scom_out}) |
({SCRDATA_SIZE {sc_addr_v[26]}} & {tidn_32, fir2_mask_scom_out}) |
({SCRDATA_SIZE {sc_addr_v[5] }} & scomErr_errDbg_status) |
({SCRDATA_SIZE {sc_addr_v[19]}} & {fir0_fir_scom_out, fir1_fir_scom_out}) ;
//=====================================================================
// Error Related Signals
//=====================================================================
// SCOM parity error reporting macro
assign sc_reg_par_err_in = {scom_reg_par_checks, fir0_fir_parity_check, fir1_fir_parity_check, fir2_fir_parity_check};
assign scom_reg_parity_err = (|sc_reg_par_err_out[0:1]);
assign fir_regs_parity_err = (|sc_reg_par_err_out[2:10]);
tri_err_rpt #(.WIDTH(SCPAR_ERR_RPT_WIDTH), .MASK_RESET_VALUE(SCPAR_RPT_RESET_VALUE), .INLINE(1'b0)) scom_err(
// use to bundle error reporting checkers of the same exact type
.vd(vdd),
.gd(gnd),
.err_d1clk(cfgslp_d1clk), // CAUTION: if LCB uses powersavings,
.err_d2clk(cfgslp_d2clk), // errors must always get reported
.err_lclk(cfgslp_lclk),
.err_scan_in(bcfg_siv[ BCFG_ERPT1_HLD_OFFSET:BCFG_ERPT1_HLD_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]),
.err_scan_out(bcfg_sov[BCFG_ERPT1_HLD_OFFSET:BCFG_ERPT1_HLD_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]),
.mode_dclk(cfg_slat_d2clk),
.mode_lclk(cfg_slat_lclk),
.mode_scan_in(bcfg_siv[ BCFG_ERPT1_MSK_OFFSET:BCFG_ERPT1_MSK_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]),
.mode_scan_out(bcfg_sov[BCFG_ERPT1_MSK_OFFSET:BCFG_ERPT1_MSK_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]),
.err_in(sc_reg_par_err_in),
.err_out(sc_reg_par_err_out),
.hold_out(sc_reg_par_err_hold)
);
//---------------------------------------------------------------------
// SCOM control error reporting macro
assign sc_reg_ack_err_in = {scom_ack_error, scom_sat_fsm_error};
assign scom_reg_ack_err = (|sc_reg_ack_err_out);
tri_err_rpt #(.WIDTH(SCACK_ERR_RPT_WIDTH), .MASK_RESET_VALUE(SCACK_RPT_RESET_VALUE), .INLINE(1'b0)) sc_ack_err(
// use to bundle error reporting checkers of the same exact type
.vd(vdd),
.gd(gnd),
.err_d1clk(cfgslp_d1clk), // CAUTION: if LCB uses powersavings,
.err_d2clk(cfgslp_d2clk), // errors must always get reported
.err_lclk(cfgslp_lclk),
.err_scan_in(bcfg_siv[ BCFG_ERPT2_HLD_OFFSET:BCFG_ERPT2_HLD_OFFSET + SCACK_ERR_RPT_WIDTH - 1]),
.err_scan_out(bcfg_sov[BCFG_ERPT2_HLD_OFFSET:BCFG_ERPT2_HLD_OFFSET + SCACK_ERR_RPT_WIDTH - 1]),
.mode_dclk(cfg_slat_d2clk),
.mode_lclk(cfg_slat_lclk),
.mode_scan_in(bcfg_siv[ BCFG_ERPT2_MSK_OFFSET:BCFG_ERPT2_MSK_OFFSET + SCACK_ERR_RPT_WIDTH - 1]),
.mode_scan_out(bcfg_sov[BCFG_ERPT2_MSK_OFFSET:BCFG_ERPT2_MSK_OFFSET + SCACK_ERR_RPT_WIDTH - 1]),
.err_in(sc_reg_ack_err_in),
.err_out(sc_reg_ack_err_out),
.hold_out(sc_reg_ack_err_hold)
);
//---------------------------------------------------------------------
// Other error reporting macros
tri_direct_err_rpt #(.WIDTH(1)) misc_dir_err(
.vd(vdd),
.gd(gnd),
.err_in(rg_rg_maxRecErrCntrValue),
.err_out(maxRecErrCntrValue_errrpt)
);
//---------------------------------------------------------------------
// Error related facilities used in other functions
// FIR0 Errors that increment the recoverable error counter (Act0=0; Act1=1)
assign fir0_recoverable_errors = fir0_errors_q & (~fir0_act0_out) & fir0_act1_out & (~fir0_mask_out);
// Leaving maxRecErrCntrValue (FIR0(0)) out of input that gates recoverable error counter.
assign fir0_recov_err_in[0] = (|fir0_recoverable_errors[1:FIR0_WIDTH - 1]);
assign fir0_recov_err_in[1] = fir0_recov_err_q[0];
// Only indicates 1 recoverable error pulse if error input active multiple cycles
assign fir0_recov_err_pulse = fir0_recov_err_q[0] & (~fir0_recov_err_q[1]);
// FIR1 Errors that increment the recoverable error counter (Act0=0; Act1=1)
assign fir1_recoverable_errors = fir1_errors_q & (~fir1_act0_out) & fir1_act1_out & (~fir1_mask_out);
assign fir1_recov_err_in[0] = (|fir1_recoverable_errors);
assign fir1_recov_err_in[1] = fir1_recov_err_q[0];
// Only indicates 1 recoverable error pulse if error input active multiple cycles
assign fir1_recov_err_pulse = fir1_recov_err_q[0] & (~fir1_recov_err_q[1]);
// FIR2 Errors that increment the recoverable error counter (Act0=0; Act1=1)
assign fir2_recoverable_errors = fir2_errors_q & (~fir2_act0_out) & fir2_act1_out & (~fir2_mask_out);
assign fir2_recov_err_in[0] = (|fir2_recoverable_errors);
assign fir2_recov_err_in[1] = fir2_recov_err_q[0];
// Only indicates 1 recoverable error pulse if error input active multiple cycles
assign fir2_recov_err_pulse = fir2_recov_err_q[0] & (~fir2_recov_err_q[1]);
// Combined recoverable error signal from all the FIRs
assign recov_err_int = {fir0_recov_err, fir1_recov_err, fir2_recov_err};
// Enabled checkstop (system and local) errors used to stop failing thread (Act0=1; Act1=X)
assign fir0_enabled_checkstops = fir0_fir_out & fir0_act0_out & (~fir0_mask_out);
assign fir1_enabled_checkstops = fir1_fir_out & fir1_act0_out & (~fir1_mask_out);
assign fir2_enabled_checkstops = fir2_fir_out & fir2_act0_out & (~fir2_mask_out);
//---------------------------------------------------------------------
// Determines how errors will force failing thread(s) to stop if configured as checkstop:
// This is based on the error bit definition in each FIR (thread specific or per core).
//
// Per core FIR0
// T0 FIR1
// T1 FIR2
//
assign xstop_err_common = (|fir0_enabled_checkstops);
assign xstop_err_per_thread[0] = xstop_err_common | (|fir1_enabled_checkstops);
generate
if (`THREADS == 2)
begin : THRDXSTOP_2T
assign xstop_err_per_thread[1] = xstop_err_common | (|fir2_enabled_checkstops);
end
endgenerate
//---------------------------------------------------------------------
// Report xstop + lxstop errors to Chiplet FIR. Can bypass in Ram mode if override signal active.
assign xstop_err_int[0:2] = {fir0_xstop_err, fir1_xstop_err, fir2_xstop_err};
assign lxstop_err_int[0:2] = {fir0_lxstop_mchk, fir1_lxstop_mchk, fir2_lxstop_mchk};
assign any_fir_xstop_int = (|xstop_err_int[0:2]) | (|lxstop_err_int[0:2]);
assign block_xstop_in_ram_mode = rg_rg_xstop_report_ovride & rg_rg_ram_mode;
assign xstop_out_d[0:2] = (block_xstop_in_ram_mode == 1'b0) ? xstop_err_int[0:2] : 3'b000 ;
assign lxstop_out_d[0:2] = (block_xstop_in_ram_mode == 1'b0) ? lxstop_err_int[0:2] : 3'b000 ;
//---------------------------------------------------------------------
// Error injection shutoff control signals
assign injoff_icache_parity = fir0_errors_q[1];
assign injoff_icachedir_parity = fir0_errors_q[2];
assign injoff_icachedir_multihit = fir0_errors_q[3];
assign injoff_dcache_parity = fir0_errors_q[4];
assign injoff_dcachedir_ldp_parity = fir0_errors_q[5];
assign injoff_dcachedir_stp_parity = fir0_errors_q[6];
assign injoff_dcachedir_ldp_multihit = fir0_errors_q[7];
assign injoff_dcachedir_stp_multihit = fir0_errors_q[8];
assign injoff_scomreg_parity = fir0_errors_q[21];
assign injoff_prefetcher_parity = fir0_errors_q[24];
assign injoff_relq_parity = fir0_errors_q[25];
assign injoff_sprg_ecc_t0 = fir1_errors_q[0];
assign injoff_fx0regfile_par_t0 = fir1_errors_q[2];
assign injoff_fx1regfile_par_t0 = fir1_errors_q[2];
assign injoff_lqregfile_par_t0 = fir1_errors_q[4];
assign injoff_furegfile_par_t0 = fir1_errors_q[6];
assign injoff_cpArray_par_t0 = fir1_errors_q[8];
assign injoff_llbust_attempt_t0 = fir1_errors_q[11];
assign injoff_llbust_failed_t0 = fir1_errors_q[12];
assign error_inject_shutoff[0:22] = {
injoff_icache_parity, injoff_icachedir_parity, injoff_icachedir_multihit, // 0:2
injoff_dcache_parity, injoff_dcachedir_ldp_parity, injoff_dcachedir_stp_parity, // 3:5
injoff_dcachedir_ldp_multihit, injoff_dcachedir_stp_multihit, injoff_scomreg_parity, // 6:8
injoff_prefetcher_parity, injoff_relq_parity, 2'b00, // 9:12
injoff_sprg_ecc_t0, injoff_fx0regfile_par_t0, injoff_fx1regfile_par_t0, // 13:15
injoff_lqregfile_par_t0, injoff_furegfile_par_t0, injoff_llbust_attempt_t0, // 16:18
injoff_llbust_failed_t0, injoff_cpArray_par_t0, 2'b00 }; // 19:22
generate
if (`THREADS == 1)
begin : ERRINJOFF_2T_BYP
assign injoff_sprg_ecc_t1 = 1'b0;
assign injoff_fx0regfile_par_t1 = 1'b0;
assign injoff_fx1regfile_par_t1 = 1'b0;
assign injoff_lqregfile_par_t1 = 1'b0;
assign injoff_furegfile_par_t1 = 1'b0;
assign injoff_llbust_attempt_t1 = 1'b0;
assign injoff_llbust_failed_t1 = 1'b0;
end
endgenerate
generate
if (`THREADS > 1)
begin : ERRINJOFF_2T
assign injoff_sprg_ecc_t1 = fir2_errors_q[0];
assign injoff_fx0regfile_par_t1 = fir2_errors_q[2];
assign injoff_fx1regfile_par_t1 = fir2_errors_q[2];
assign injoff_lqregfile_par_t1 = fir2_errors_q[4];
assign injoff_furegfile_par_t1 = fir2_errors_q[6];
assign injoff_cpArray_par_t1 = fir2_errors_q[8];
assign injoff_llbust_attempt_t1 = fir2_errors_q[11];
assign injoff_llbust_failed_t1 = fir2_errors_q[12];
assign error_inject_shutoff[23:31] = {
injoff_sprg_ecc_t1, injoff_fx0regfile_par_t1, injoff_fx1regfile_par_t1, // 23:25
injoff_lqregfile_par_t1, injoff_furegfile_par_t1, injoff_llbust_attempt_t1, // 26:28
injoff_llbust_failed_t1, injoff_cpArray_par_t1, 1'b0 }; // 29:31
end
endgenerate
//---------------------------------------------------------------------
// Livelock error pulses; ORed together and sent to L2 hang detect logic.
assign livelock_active_d = (|xu_pc_err_llbust_attempt) | (|xu_pc_err_llbust_failed);
//=====================================================================
// Output Assignments
//=====================================================================
assign ac_an_checkstop = xstop_out_q[0:2];
assign ac_an_local_checkstop = lxstop_out_q[0:2];
assign ac_an_recov_err = recov_err_int[0:2];
assign ac_an_trace_error = fir0_trace_error | fir1_trace_error | fir2_trace_error;
assign rg_rg_xstop_err = xstop_err_per_thread[0:`THREADS - 1];
assign rg_rg_any_fir_xstop = any_fir_xstop_int;
assign rg_rg_ram_mode_xstop = rg_rg_ram_mode & any_fir_xstop_int;
assign rg_rg_errinj_shutoff = error_inject_shutoff;
assign rg_rg_gateRecErrCntr = fir0_recov_err_pulse | fir1_recov_err_pulse | fir2_recov_err_pulse;
assign ac_an_livelock_active = livelock_active_q;
//=====================================================================
// Trace/Trigger Signals
//=====================================================================
assign dbg_fir0_err = fir0_errors_q;
assign dbg_fir1_err = fir1_errors_q;
assign dbg_fir_misc =
{
xstop_err_int[0:2], // 0:2
lxstop_err_int[0:2], // 3:5
recov_err_int[0:2], // 6:8
fir0_recov_err_pulse, // 9
fir1_recov_err_pulse, // 10
fir2_recov_err_pulse, // 11
block_xstop_in_ram_mode, // 12
dbg_thread_xstop_err[0:1] // 13:14
};
generate
if (`THREADS == 1)
begin : DBG_1T
assign dbg_fir2_err = {FIR1_WIDTH {1'b0}};
assign dbg_thread_xstop_err = {xstop_err_per_thread[0], 1'b0};
end
else
begin : DBG_2T
assign dbg_fir2_err = fir2_errors_q;
assign dbg_thread_xstop_err = xstop_err_per_thread[0:1];
end
endgenerate
//=====================================================================
// Latches
//=====================================================================
tri_nlat_scan #(.WIDTH(ERROUT_FUNC_SIZE), .INIT({ERROUT_FUNC_SIZE {1'b0}})) error_out(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.d2clk(func_d2clk),
.scan_in(func_siv[ FUNC_ERROUT_OFFSET:FUNC_ERROUT_OFFSET + ERROUT_FUNC_SIZE - 1]),
.scan_out(func_sov[FUNC_ERROUT_OFFSET:FUNC_ERROUT_OFFSET + ERROUT_FUNC_SIZE - 1]),
.din({xstop_err_int, xstop_out_d, lxstop_out_d,
fir0_recov_err_in, fir1_recov_err_in, fir2_recov_err_in,
an_ac_checkstop, sc_reg_par_err_out, sc_reg_ack_err_out,
livelock_active_d }),
.q( {xstop_err_q, xstop_out_q, lxstop_out_q,
fir0_recov_err_q, fir1_recov_err_q, fir2_recov_err_q,
an_ac_checkstop_q, sc_reg_par_err_out_q, sc_reg_ack_err_out_q,
livelock_active_q })
);
tri_nlat_scan #(.WIDTH(FIR0_WIDTH), .INIT(FIR0_INIT)) f0err_out(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.d2clk(func_d2clk),
.scan_in(func_siv[ FUNC_F0ERR_OFFSET:FUNC_F0ERR_OFFSET + FIR0_WIDTH - 1]),
.scan_out(func_sov[FUNC_F0ERR_OFFSET:FUNC_F0ERR_OFFSET + FIR0_WIDTH - 1]),
.din(fir0_errors),
.q(fir0_errors_q)
);
tri_nlat_scan #(.WIDTH(FIR1_WIDTH), .INIT(FIR1_INIT)) f1err_out(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.d2clk(func_d2clk),
.scan_in(func_siv[ FUNC_F1ERR_OFFSET:FUNC_F1ERR_OFFSET + FIR1_WIDTH - 1]),
.scan_out(func_sov[FUNC_F1ERR_OFFSET:FUNC_F1ERR_OFFSET + FIR1_WIDTH - 1]),
.din(fir1_errors),
.q(fir1_errors_q)
);
tri_nlat_scan #(.WIDTH(FIR2_WIDTH), .INIT(FIR2_INIT)) f2err_out(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.d2clk(func_d2clk),
.scan_in(func_siv[ FUNC_F2ERR_OFFSET:FUNC_F2ERR_OFFSET + FIR2_WIDTH - 1]),
.scan_out(func_sov[FUNC_F2ERR_OFFSET:FUNC_F2ERR_OFFSET + FIR2_WIDTH - 1]),
.din(fir2_errors),
.q(fir2_errors_q)
);
//=====================================================================
// LCBs
//=====================================================================
// functional ring regs; NOT power managed
tri_lcbor func_lcbor(
.clkoff_b(lcb_clkoff_dc_b),
.thold(lcb_func_slp_sl_thold_0),
.sg(lcb_sg_0),
.act_dis(lcb_act_dis_dc),
.force_t(func_force),
.thold_b(func_thold_b)
);
tri_lcbnd func_lcb(
.act(tiup), // not power saved
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.nclk(nclk),
.force_t(func_force),
.sg(lcb_sg_0),
.thold_b(func_thold_b),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk)
);
//=====================================================================
// Scan Connections
//=====================================================================
assign bcfg_siv[0:BCFG_RIGHT] = {bcfg_scan_in, bcfg_sov[0:BCFG_RIGHT - 1]};
assign bcfg_scan_out = bcfg_sov[BCFG_RIGHT];
assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]};
assign func_scan_out = func_sov[FUNC_RIGHT];
endmodule |
module lq_spr_tspr
#(
parameter hvmode = 1,
parameter a2mode = 1
)(
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
input [0:`NCLK_WIDTH-1] nclk,
input d_mode_dc,
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input sg_0,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out,
// SlowSPR Interface
input slowspr_val_in,
input slowspr_rw_in,
input [0:9] slowspr_addr_in,
input [64-`GPR_WIDTH:63] slowspr_data_in,
output tspr_done,
output [64-`GPR_WIDTH:63] tspr_rt,
// SPRs
input cspr_tspr_msr_pr,
input cspr_tspr_msr_gs,
output [0:1] tspr_cspr_dbcr2_dac1us,
output [0:1] tspr_cspr_dbcr2_dac1er,
output [0:1] tspr_cspr_dbcr2_dac2us,
output [0:1] tspr_cspr_dbcr2_dac2er,
output [0:1] tspr_cspr_dbcr3_dac3us,
output [0:1] tspr_cspr_dbcr3_dac3er,
output [0:1] tspr_cspr_dbcr3_dac4us,
output [0:1] tspr_cspr_dbcr3_dac4er,
output tspr_cspr_dbcr2_dac12m,
output tspr_cspr_dbcr3_dac34m,
output [0:1] tspr_cspr_dbcr2_dvc1m,
output [0:1] tspr_cspr_dbcr2_dvc2m,
output [0:7] tspr_cspr_dbcr2_dvc1be,
output [0:7] tspr_cspr_dbcr2_dvc2be,
output spr_epsc_wr,
output spr_eplc_wr,
output [0:31] spr_acop_ct,
output spr_dbcr3_ivc,
output spr_dscr_lsd,
output spr_dscr_snse,
output spr_dscr_sse,
output [0:2] spr_dscr_dpfd,
output spr_eplc_epr,
output spr_eplc_eas,
output spr_eplc_egs,
output [0:7] spr_eplc_elpid,
output [0:13] spr_eplc_epid,
output spr_epsc_epr,
output spr_epsc_eas,
output spr_epsc_egs,
output [0:7] spr_epsc_elpid,
output [0:13] spr_epsc_epid,
output [0:31] spr_hacop_ct,
// Power
inout vdd,
inout gnd
);
// Types
wire eplc_we_d;
wire eplc_we_q;
wire epsc_we_d;
wire epsc_we_q;
// SPR Registers
wire [32:63] acop_d, acop_q;
wire [35:63] dbcr2_d, dbcr2_q;
wire [54:63] dbcr3_d, dbcr3_q;
wire [58:63] dscr_d, dscr_q;
wire [39:63] eplc_d, eplc_q;
wire [39:63] epsc_d, epsc_q;
wire [32:63] hacop_d, hacop_q;
// FUNC Scanchain
localparam acop_offset = 0;
localparam dbcr2_offset = acop_offset + 32*a2mode;
localparam dbcr3_offset = dbcr2_offset + 29*a2mode;
localparam dscr_offset = dbcr3_offset + 10;
localparam eplc_offset = dscr_offset + 6;
localparam epsc_offset = eplc_offset + 25*hvmode;
localparam hacop_offset = epsc_offset + 25*hvmode;
localparam last_reg_offset = hacop_offset + 32*hvmode;
parameter eplc_we_offset = last_reg_offset;
parameter epsc_we_offset = eplc_we_offset + 1;
parameter scan_right = epsc_we_offset + 1;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
// Signals
wire tiup;
wire [00:63] tidn;
wire sspr_spr_we;
wire [11:20] sspr_instr;
wire sspr_is_mtspr;
wire [64-`GPR_WIDTH:63] sspr_spr_wd;
wire hyp_state;
// Data
wire [0:1] spr_dbcr2_dac1us;
wire [0:1] spr_dbcr2_dac1er;
wire [0:1] spr_dbcr2_dac2us;
wire [0:1] spr_dbcr2_dac2er;
wire spr_dbcr2_dac12m;
wire [0:1] spr_dbcr2_dvc1m;
wire [0:1] spr_dbcr2_dvc2m;
wire [0:7] spr_dbcr2_dvc1be;
wire [0:7] spr_dbcr2_dvc2be;
wire [0:1] spr_dbcr3_dac3us;
wire [0:1] spr_dbcr3_dac3er;
wire [0:1] spr_dbcr3_dac4us;
wire [0:1] spr_dbcr3_dac4er;
wire spr_dbcr3_dac34m;
wire [32:63] sspr_acop_di;
wire [35:63] sspr_dbcr2_di;
wire [54:63] sspr_dbcr3_di;
wire [58:63] sspr_dscr_di;
wire [39:63] sspr_eplc_di;
wire [39:63] sspr_epsc_di;
wire [32:63] sspr_hacop_di;
wire
sspr_acop_rdec , sspr_dbcr2_rdec, sspr_dbcr3_rdec, sspr_dscr_rdec
, sspr_eplc_rdec , sspr_epsc_rdec , sspr_hacop_rdec;
wire
sspr_acop_re , sspr_dbcr2_re , sspr_dbcr3_re , sspr_dscr_re
, sspr_eplc_re , sspr_epsc_re , sspr_hacop_re ;
wire
sspr_acop_wdec , sspr_dbcr2_wdec, sspr_dbcr3_wdec, sspr_dscr_wdec
, sspr_eplc_wdec , sspr_epsc_wdec , sspr_hacop_wdec;
wire
sspr_acop_we , sspr_dbcr2_we , sspr_dbcr3_we , sspr_dscr_we
, sspr_eplc_we , sspr_epsc_we , sspr_hacop_we ;
wire
acop_act , dbcr2_act , dbcr3_act , dscr_act
, eplc_act , epsc_act , hacop_act ;
wire [0:64]
acop_do , dbcr2_do , dbcr3_do , dscr_do
, eplc_do , epsc_do , hacop_do ;
//!! Bugspray Include: lq_spr_tspr;
//## figtree_source: lq_spr_tspr.fig;
assign tiup = 1'b1;
assign tidn = {64{1'b0}};
assign sspr_is_mtspr = (~slowspr_rw_in);
assign sspr_instr = {slowspr_addr_in[5:9], slowspr_addr_in[0:4]};
assign sspr_spr_we = slowspr_val_in;
assign sspr_spr_wd = slowspr_data_in;
assign hyp_state = ~(cspr_tspr_msr_pr | cspr_tspr_msr_gs);
// SPR Input Control
// ACOP
assign acop_act = sspr_acop_we;
assign acop_d = sspr_acop_di;
// HACOP
assign hacop_act = sspr_hacop_we;
assign hacop_d = sspr_hacop_di;
// DBCR2
assign dbcr2_act = sspr_dbcr2_we;
assign dbcr2_d = sspr_dbcr2_di;
// DBCR3
assign dbcr3_act = sspr_dbcr3_we;
assign dbcr3_d = sspr_dbcr3_di;
// DSCR
assign dscr_act = sspr_dscr_we;
assign dscr_d = sspr_dscr_di;
// EPLC
assign eplc_act = sspr_eplc_we;
assign eplc_we_d = sspr_eplc_we;
assign eplc_d[39:1 + 39] = sspr_eplc_di[39:1 + 39];
assign eplc_d[(2 + 39) + 9:63] = sspr_eplc_di[(2 + 39) + 9:63];
assign eplc_d[2 + 39:(2 + 39) + 8] = (hyp_state == 1'b1) ? sspr_eplc_di[2 + 39:(2 + 39) + 8] :
eplc_q[2 + 39:(2 + 39) + 8];
// EPSC
assign epsc_act = sspr_epsc_we;
assign epsc_we_d = sspr_epsc_we;
assign epsc_d[39:1 + 39] = sspr_epsc_di[39:1 + 39];
assign epsc_d[(2 + 39) + 9:63] = sspr_epsc_di[(2 + 39) + 9:63];
assign epsc_d[2 + 39:(2 + 39) + 8] = (hyp_state == 1'b1) ? sspr_epsc_di[2 + 39:(2 + 39) + 8] :
epsc_q[2 + 39:(2 + 39) + 8];
generate
if (a2mode == 0 & hvmode == 0) begin : readmux_00
assign tspr_rt =
(dbcr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr3_re }}) |
(dscr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dscr_re }});
end
endgenerate
generate
if (a2mode == 0 & hvmode == 1) begin : readmux_01
assign tspr_rt =
(dbcr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr3_re }}) |
(dscr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dscr_re }}) |
(eplc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_eplc_re }}) |
(epsc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_epsc_re }}) |
(hacop_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_hacop_re }});
end
endgenerate
generate
if (a2mode == 1 & hvmode == 0) begin : readmux_10
assign tspr_rt =
(acop_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_acop_re }}) |
(dbcr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr2_re }}) |
(dbcr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr3_re }}) |
(dscr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dscr_re }});
end
endgenerate
generate
if (a2mode == 1 & hvmode == 1) begin : readmux_11
assign tspr_rt =
(acop_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_acop_re }}) |
(dbcr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr2_re }}) |
(dbcr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr3_re }}) |
(dscr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dscr_re }}) |
(eplc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_eplc_re }}) |
(epsc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_epsc_re }}) |
(hacop_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_hacop_re }});
end
endgenerate
assign sspr_acop_rdec = (sspr_instr[11:20] == 10'b1111100000); // 31
assign sspr_dbcr2_rdec = (sspr_instr[11:20] == 10'b1011001001); // 310
assign sspr_dbcr3_rdec = (sspr_instr[11:20] == 10'b1000011010); // 848
assign sspr_dscr_rdec = (sspr_instr[11:20] == 10'b1000100000); // 17
assign sspr_eplc_rdec = (sspr_instr[11:20] == 10'b1001111101); // 947
assign sspr_epsc_rdec = (sspr_instr[11:20] == 10'b1010011101); // 948
assign sspr_hacop_rdec = (sspr_instr[11:20] == 10'b1111101010); // 351
assign sspr_acop_re = sspr_acop_rdec;
assign sspr_dbcr2_re = sspr_dbcr2_rdec;
assign sspr_dbcr3_re = sspr_dbcr3_rdec;
assign sspr_dscr_re = sspr_dscr_rdec;
assign sspr_eplc_re = sspr_eplc_rdec;
assign sspr_epsc_re = sspr_epsc_rdec;
assign sspr_hacop_re = sspr_hacop_rdec;
assign sspr_acop_wdec = sspr_acop_rdec;
assign sspr_dbcr2_wdec = sspr_dbcr2_rdec;
assign sspr_dbcr3_wdec = sspr_dbcr3_rdec;
assign sspr_dscr_wdec = sspr_dscr_rdec;
assign sspr_eplc_wdec = sspr_eplc_rdec;
assign sspr_epsc_wdec = sspr_epsc_rdec;
assign sspr_hacop_wdec = (sspr_instr[11:20] == 10'b1111101010); // 351
assign sspr_acop_we = sspr_spr_we & sspr_is_mtspr & sspr_acop_wdec;
assign sspr_dbcr2_we = sspr_spr_we & sspr_is_mtspr & sspr_dbcr2_wdec;
assign sspr_dbcr3_we = sspr_spr_we & sspr_is_mtspr & sspr_dbcr3_wdec;
assign sspr_dscr_we = sspr_spr_we & sspr_is_mtspr & sspr_dscr_wdec;
assign sspr_eplc_we = sspr_spr_we & sspr_is_mtspr & sspr_eplc_wdec;
assign sspr_epsc_we = sspr_spr_we & sspr_is_mtspr & sspr_epsc_wdec;
assign sspr_hacop_we = sspr_spr_we & sspr_is_mtspr & sspr_hacop_wdec;
assign tspr_done = slowspr_val_in & (
sspr_acop_rdec | sspr_dbcr2_rdec | sspr_dbcr3_rdec
| sspr_dscr_rdec | sspr_eplc_rdec | sspr_epsc_rdec
| sspr_hacop_rdec );
assign spr_acop_ct = acop_q[32:63];
assign spr_dbcr2_dac1us = dbcr2_q[35:36];
assign spr_dbcr2_dac1er = dbcr2_q[37:38];
assign spr_dbcr2_dac2us = dbcr2_q[39:40];
assign spr_dbcr2_dac2er = dbcr2_q[41:42];
assign spr_dbcr2_dac12m = dbcr2_q[43];
assign spr_dbcr2_dvc1m = dbcr2_q[44:45];
assign spr_dbcr2_dvc2m = dbcr2_q[46:47];
assign spr_dbcr2_dvc1be = dbcr2_q[48:55];
assign spr_dbcr2_dvc2be = dbcr2_q[56:63];
assign spr_dbcr3_dac3us = dbcr3_q[54:55];
assign spr_dbcr3_dac3er = dbcr3_q[56:57];
assign spr_dbcr3_dac4us = dbcr3_q[58:59];
assign spr_dbcr3_dac4er = dbcr3_q[60:61];
assign spr_dbcr3_dac34m = dbcr3_q[62];
assign spr_dbcr3_ivc = dbcr3_q[63];
assign spr_dscr_lsd = dscr_q[58];
assign spr_dscr_snse = dscr_q[59];
assign spr_dscr_sse = dscr_q[60];
assign spr_dscr_dpfd = dscr_q[61:63];
assign spr_eplc_epr = eplc_q[39];
assign spr_eplc_eas = eplc_q[40];
assign spr_eplc_egs = eplc_q[41];
assign spr_eplc_elpid = eplc_q[42:49];
assign spr_eplc_epid = eplc_q[50:63];
assign spr_epsc_epr = epsc_q[39];
assign spr_epsc_eas = epsc_q[40];
assign spr_epsc_egs = epsc_q[41];
assign spr_epsc_elpid = epsc_q[42:49];
assign spr_epsc_epid = epsc_q[50:63];
assign spr_hacop_ct = hacop_q[32:63];
assign tspr_cspr_dbcr2_dac1us = spr_dbcr2_dac1us;
assign tspr_cspr_dbcr2_dac1er = spr_dbcr2_dac1er;
assign tspr_cspr_dbcr2_dac2us = spr_dbcr2_dac2us;
assign tspr_cspr_dbcr2_dac2er = spr_dbcr2_dac2er;
assign tspr_cspr_dbcr3_dac3us = spr_dbcr3_dac3us;
assign tspr_cspr_dbcr3_dac3er = spr_dbcr3_dac3er;
assign tspr_cspr_dbcr3_dac4us = spr_dbcr3_dac4us;
assign tspr_cspr_dbcr3_dac4er = spr_dbcr3_dac4er;
assign tspr_cspr_dbcr2_dac12m = spr_dbcr2_dac12m;
assign tspr_cspr_dbcr3_dac34m = spr_dbcr3_dac34m;
assign tspr_cspr_dbcr2_dvc1m = spr_dbcr2_dvc1m;
assign tspr_cspr_dbcr2_dvc2m = spr_dbcr2_dvc2m;
assign tspr_cspr_dbcr2_dvc1be = spr_dbcr2_dvc1be;
assign tspr_cspr_dbcr2_dvc2be = spr_dbcr2_dvc2be;
assign spr_epsc_wr = epsc_we_q;
assign spr_eplc_wr = eplc_we_q;
// ACOP
assign sspr_acop_di = { sspr_spr_wd[32:63] }; //CT
assign acop_do = { tidn[0:0] ,
tidn[0:31] , /////
acop_q[32:63] }; //CT
// DBCR2
assign sspr_dbcr2_di = { sspr_spr_wd[32:33] , //DAC1US
sspr_spr_wd[34:35] , //DAC1ER
sspr_spr_wd[36:37] , //DAC2US
sspr_spr_wd[38:39] , //DAC2ER
sspr_spr_wd[41:41] , //DAC12M
sspr_spr_wd[44:45] , //DVC1M
sspr_spr_wd[46:47] , //DVC2M
sspr_spr_wd[48:55] , //DVC1BE
sspr_spr_wd[56:63] }; //DVC2BE
assign dbcr2_do = { tidn[0:0] ,
tidn[0:31] , /////
dbcr2_q[35:36] , //DAC1US
dbcr2_q[37:38] , //DAC1ER
dbcr2_q[39:40] , //DAC2US
dbcr2_q[41:42] , //DAC2ER
tidn[40:40] , /////
dbcr2_q[43:43] , //DAC12M
tidn[42:43] , /////
dbcr2_q[44:45] , //DVC1M
dbcr2_q[46:47] , //DVC2M
dbcr2_q[48:55] , //DVC1BE
dbcr2_q[56:63] }; //DVC2BE
// DBCR3
assign sspr_dbcr3_di = { sspr_spr_wd[32:33] , //DAC3US
sspr_spr_wd[34:35] , //DAC3ER
sspr_spr_wd[36:37] , //DAC4US
sspr_spr_wd[38:39] , //DAC4ER
sspr_spr_wd[41:41] , //DAC34M
sspr_spr_wd[63:63] }; //IVC
assign dbcr3_do = { tidn[0:0] ,
tidn[0:31] , /////
dbcr3_q[54:55] , //DAC3US
dbcr3_q[56:57] , //DAC3ER
dbcr3_q[58:59] , //DAC4US
dbcr3_q[60:61] , //DAC4ER
tidn[40:40] , /////
dbcr3_q[62:62] , //DAC34M
tidn[42:62] , /////
dbcr3_q[63:63] }; //IVC
// DSCR
assign sspr_dscr_di = { sspr_spr_wd[58:58] , //LSD
sspr_spr_wd[59:59] , //SNSE
sspr_spr_wd[60:60] , //SSE
sspr_spr_wd[61:63] }; //DPFD
assign dscr_do = { tidn[0:0] ,
tidn[0:31] , /////
tidn[32:57] , /////
dscr_q[58:58] , //LSD
dscr_q[59:59] , //SNSE
dscr_q[60:60] , //SSE
dscr_q[61:63] }; //DPFD
// EPLC
assign sspr_eplc_di = { sspr_spr_wd[32:32] , //EPR
sspr_spr_wd[33:33] , //EAS
sspr_spr_wd[34:34] , //EGS
sspr_spr_wd[40:47] , //ELPID
sspr_spr_wd[50:63] }; //EPID
assign eplc_do = { tidn[0:0] ,
tidn[0:31] , /////
eplc_q[39:39] , //EPR
eplc_q[40:40] , //EAS
eplc_q[41:41] , //EGS
tidn[35:39] , /////
eplc_q[42:49] , //ELPID
tidn[48:49] , /////
eplc_q[50:63] }; //EPID
// EPSC
assign sspr_epsc_di = { sspr_spr_wd[32:32] , //EPR
sspr_spr_wd[33:33] , //EAS
sspr_spr_wd[34:34] , //EGS
sspr_spr_wd[40:47] , //ELPID
sspr_spr_wd[50:63] }; //EPID
assign epsc_do = { tidn[0:0] ,
tidn[0:31] , /////
epsc_q[39:39] , //EPR
epsc_q[40:40] , //EAS
epsc_q[41:41] , //EGS
tidn[35:39] , /////
epsc_q[42:49] , //ELPID
tidn[48:49] , /////
epsc_q[50:63] }; //EPID
// HACOP
assign sspr_hacop_di = { sspr_spr_wd[32:63] }; //CT
assign hacop_do = { tidn[0:0] ,
tidn[0:31] , /////
hacop_q[32:63] }; //CT
// Unused Signals
assign unused_do_bits = |{
acop_do[0:64-`GPR_WIDTH]
,dbcr2_do[0:64-`GPR_WIDTH]
,dbcr3_do[0:64-`GPR_WIDTH]
,dscr_do[0:64-`GPR_WIDTH]
,eplc_do[0:64-`GPR_WIDTH]
,epsc_do[0:64-`GPR_WIDTH]
,hacop_do[0:64-`GPR_WIDTH]
};
generate
if (a2mode == 1) begin : acop_latch_gen
tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) acop_latch(
.nclk(nclk),.vd(vdd),.gd(gnd),
.act(acop_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[acop_offset:acop_offset + 32 - 1]),
.scout(sov[acop_offset:acop_offset + 32 - 1]),
.din(acop_d),
.dout(acop_q)
);
end
if (a2mode == 0) begin : acop_latch_tie
assign acop_q = {32{1'b0}};
end
endgenerate
generate
if (a2mode == 1) begin : dbcr2_latch_gen
tri_ser_rlmreg_p #(.WIDTH(29), .INIT(0), .NEEDS_SRESET(1)) dbcr2_latch(
.nclk(nclk),.vd(vdd),.gd(gnd),
.act(dbcr2_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[dbcr2_offset:dbcr2_offset + 29 - 1]),
.scout(sov[dbcr2_offset:dbcr2_offset + 29 - 1]),
.din(dbcr2_d),
.dout(dbcr2_q)
);
end
if (a2mode == 0) begin : dbcr2_latch_tie
assign dbcr2_q = {29{1'b0}};
end
endgenerate
tri_ser_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) dbcr3_latch(
.nclk(nclk),.vd(vdd),.gd(gnd),
.act(dbcr3_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[dbcr3_offset:dbcr3_offset + 10 - 1]),
.scout(sov[dbcr3_offset:dbcr3_offset + 10 - 1]),
.din(dbcr3_d),
.dout(dbcr3_q)
);
tri_ser_rlmreg_p #(.WIDTH(6), .INIT(32), .NEEDS_SRESET(1)) dscr_latch(
.nclk(nclk),.vd(vdd),.gd(gnd),
.act(dscr_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[dscr_offset:dscr_offset + 6 - 1]),
.scout(sov[dscr_offset:dscr_offset + 6 - 1]),
.din(dscr_d),
.dout(dscr_q)
);
generate
if (hvmode == 1) begin : eplc_latch_gen
tri_ser_rlmreg_p #(.WIDTH(25), .INIT(0), .NEEDS_SRESET(1)) eplc_latch(
.nclk(nclk),.vd(vdd),.gd(gnd),
.act(eplc_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[eplc_offset:eplc_offset + 25 - 1]),
.scout(sov[eplc_offset:eplc_offset + 25 - 1]),
.din(eplc_d),
.dout(eplc_q)
);
end
if (hvmode == 0) begin : eplc_latch_tie
assign eplc_q = {25{1'b0}};
end
endgenerate
generate
if (hvmode == 1) begin : epsc_latch_gen
tri_ser_rlmreg_p #(.WIDTH(25), .INIT(0), .NEEDS_SRESET(1)) epsc_latch(
.nclk(nclk),.vd(vdd),.gd(gnd),
.act(epsc_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[epsc_offset:epsc_offset + 25 - 1]),
.scout(sov[epsc_offset:epsc_offset + 25 - 1]),
.din(epsc_d),
.dout(epsc_q)
);
end
if (hvmode == 0) begin : epsc_latch_tie
assign epsc_q = {25{1'b0}};
end
endgenerate
generate
if (hvmode == 1) begin : hacop_latch_gen
tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) hacop_latch(
.nclk(nclk),.vd(vdd),.gd(gnd),
.act(hacop_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[hacop_offset:hacop_offset + 32 - 1]),
.scout(sov[hacop_offset:hacop_offset + 32 - 1]),
.din(hacop_d),
.dout(hacop_q)
);
end
if (hvmode == 0) begin : hacop_latch_tie
assign hacop_q = {32{1'b0}};
end
endgenerate
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) eplc_we_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[eplc_we_offset]),
.scout(sov[eplc_we_offset]),
.din(eplc_we_d),
.dout(eplc_we_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epsc_we_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[epsc_we_offset]),
.scout(sov[epsc_we_offset]),
.din(epsc_we_d),
.dout(epsc_we_q)
);
assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scan_in};
assign scan_out = sov[0];
endmodule |
module fu_lza(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
f_lza_si,
f_lza_so,
ex2_act_b,
f_sa3_ex4_s,
f_sa3_ex4_c,
f_alg_ex3_effsub_eac_b,
f_lze_ex3_lzo_din,
f_lze_ex4_sh_rgt_amt,
f_lze_ex4_sh_rgt_en,
f_lza_ex5_no_lza_edge,
f_lza_ex5_lza_amt,
f_lza_ex5_lza_dcd64_cp1,
f_lza_ex5_lza_dcd64_cp2,
f_lza_ex5_lza_dcd64_cp3,
f_lza_ex5_sh_rgt_en,
f_lza_ex5_sh_rgt_en_eov,
f_lza_ex5_lza_amt_eov
);
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input [3:4] delay_lclkr; // tidn,
input [3:4] mpw1_b; // tidn,
input [0:0] mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input f_lza_si; //perv
output f_lza_so; //perv
input ex2_act_b; //act
input [0:162] f_sa3_ex4_s; // data
input [53:161] f_sa3_ex4_c; // data
input f_alg_ex3_effsub_eac_b;
input [0:162] f_lze_ex3_lzo_din;
input [0:7] f_lze_ex4_sh_rgt_amt;
input f_lze_ex4_sh_rgt_en;
output f_lza_ex5_no_lza_edge; //fpic
output [0:7] f_lza_ex5_lza_amt; //fnrm
output [0:2] f_lza_ex5_lza_dcd64_cp1; //fnrm
output [0:1] f_lza_ex5_lza_dcd64_cp2; //fnrm
output [0:0] f_lza_ex5_lza_dcd64_cp3; //fnrm
output f_lza_ex5_sh_rgt_en;
output f_lza_ex5_sh_rgt_en_eov;
output [0:7] f_lza_ex5_lza_amt_eov; //feov
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire thold_0_b;
wire thold_0;
wire force_t;
wire sg_0;
wire ex3_act;
wire ex4_act;
wire ex2_act;
(* analysis_not_referenced="TRUE" *)
wire [0:3] act_spare_unused;
//--------------------------------------
wire [0:5] act_so; //SCAN
wire [0:5] act_si; //SCAN
wire [0:162] ex4_lzo_so; //SCAN
wire [0:162] ex4_lzo_si; //SCAN
wire [0:0] ex4_sub_so; //SCAN
wire [0:0] ex4_sub_si; //SCAN
wire [0:15] ex5_amt_so; //SCAN
wire [0:15] ex5_amt_si; //SCAN
wire [0:8] ex5_dcd_so; //SCAN
wire [0:8] ex5_dcd_si; //SCAN
//--------------------------------------
wire ex4_lza_any_b;
wire ex4_effsub;
wire ex5_no_edge;
wire ex4_no_edge_b;
wire [0:162] ex4_lzo;
wire [0:7] ex4_lza_amt_b;
wire [0:7] ex5_amt_eov;
wire [0:7] ex5_amt;
wire [0:162] ex4_sum;
wire [53:162] ex4_car;
wire [0:162] ex4_lv0_or;
wire ex4_sh_rgt_en_b;
wire ex4_lv6_or_0_b;
wire ex4_lv6_or_1_b;
wire ex4_lv6_or_0_t;
wire ex4_lv6_or_1_t;
wire ex4_lza_dcd64_0_b;
wire ex4_lza_dcd64_1_b;
wire ex4_lza_dcd64_2_b;
wire [0:2] ex5_lza_dcd64_cp1;
wire [0:1] ex5_lza_dcd64_cp2;
wire [0:0] ex5_lza_dcd64_cp3;
wire ex5_sh_rgt_en;
wire ex5_sh_rgt_en_eov;
wire ex3_effsub_eac;
wire ex3_effsub_eac_b;
wire [0:162] ex4_lzo_b;
wire [0:162] ex4_lzo_l2_b;
wire ex4_lv6_or_0;
wire ex4_lv6_or_1;
wire [0:7] ex4_rgt_amt_b;
wire lza_ex5_d1clk;
wire lza_ex5_d2clk;
wire lza_ex4_d1clk;
wire lza_ex4_d2clk;
wire [0:`NCLK_WIDTH-1] lza_ex5_lclk;
wire [0:`NCLK_WIDTH-1] lza_ex4_lclk;
//=###############################################################
//= map block attributes
//=###############################################################
//=###############################################################
//= pervasive
//=###############################################################
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
//=###############################################################
//= act
//=###############################################################
assign ex2_act = (~ex2_act_b);
tri_rlmreg_p #(.WIDTH(6), .NEEDS_SRESET(0)) act_lat(
.force_t(force_t), //i-- tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[3]), //i-- tidn,
.mpw1_b(mpw1_b[3]), //i-- tidn,
.mpw2_b(mpw2_b[0]), //i-- tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(fpu_enable),
.thold_b(thold_0_b),
.sg(sg_0),
.scout(act_so),
.scin(act_si),
//-----------------
.din({ act_spare_unused[0],
act_spare_unused[1],
ex2_act,
ex3_act,
act_spare_unused[2],
act_spare_unused[3]}),
//-----------------
.dout({ act_spare_unused[0],
act_spare_unused[1],
ex3_act,
ex4_act,
act_spare_unused[2],
act_spare_unused[3]})
);
tri_lcbnd lza_ex4_lcb(
.delay_lclkr(delay_lclkr[3]), // tidn ,--in
.mpw1_b(mpw1_b[3]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in
.nclk(nclk), //in
.vd(vdd), //inout
.gd(gnd), //inout
.act(ex3_act), //in
.sg(sg_0), //in
.thold_b(thold_0_b), //in
.d1clk(lza_ex4_d1clk), //out
.d2clk(lza_ex4_d2clk), //out
.lclk(lza_ex4_lclk) //out
);
tri_lcbnd lza_ex5_lcb(
.delay_lclkr(delay_lclkr[4]), // tidn ,--in
.mpw1_b(mpw1_b[4]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in
.nclk(nclk), //in
.vd(vdd), //inout
.gd(gnd), //inout
.act(ex4_act), //in
.sg(sg_0), //in
.thold_b(thold_0_b), //in
.d1clk(lza_ex5_d1clk), //out
.d2clk(lza_ex5_d2clk), //out
.lclk(lza_ex5_lclk) //out
);
//=###############################################################
//= ex4 latches
//=###############################################################
tri_inv_nlats #(.WIDTH(163), .NEEDS_SRESET(0)) ex4_lzo_lat(
.vd(vdd),
.gd(gnd),
.lclk(lza_ex4_lclk), // lclk.clk
.d1clk(lza_ex4_d1clk),
.d2clk(lza_ex4_d2clk),
.scanin(ex4_lzo_si),
.scanout(ex4_lzo_so),
.d(f_lze_ex3_lzo_din[0:162]),
.qb(ex4_lzo_l2_b[0:162])
);
assign ex4_lzo[0:162] = (~ex4_lzo_l2_b[0:162]);
assign ex4_lzo_b[0:162] = (~ex4_lzo[0:162]);
assign ex3_effsub_eac = (~f_alg_ex3_effsub_eac_b);
assign ex3_effsub_eac_b = (~ex3_effsub_eac);
tri_inv_nlats #(.WIDTH(1), .NEEDS_SRESET(0)) ex4_sub_lat(
.vd(vdd),
.gd(gnd),
.lclk(lza_ex4_lclk), // lclk.clk
.d1clk(lza_ex4_d1clk),
.d2clk(lza_ex4_d2clk),
.scanin(ex4_sub_si[0]),
.scanout(ex4_sub_so[0]),
.d(ex3_effsub_eac_b),
.qb(ex4_effsub)
);
assign ex4_sum[0:52] = f_sa3_ex4_s[0:52];
//=###############################################################
//= ex4 logic
//=###############################################################
assign ex4_sum[53:162] = f_sa3_ex4_s[53:162];
assign ex4_car[53:162] = {f_sa3_ex4_c[53:161], tidn};
//=#------------------------------------------------
//=#-- EDGE DETECTION
//=#------------------------------------------------
fu_lza_ej lzaej(
.effsub(ex4_effsub), //i--
.sum(ex4_sum[0:162]), //i--
.car(ex4_car[53:162]), //i--
.lzo_b(ex4_lzo_b[0:162]), //i--
.edge_t(ex4_lv0_or[0:162]) //o--
);
//=#------------------------------------------------
//=#-- ENCODING TREE (CLZ) count leading zeroes
//=#------------------------------------------------
fu_lza_clz lzaclz(
.lv0_or(ex4_lv0_or[0:162]), //i--
.lv6_or_0(ex4_lv6_or_0), //o--
.lv6_or_1(ex4_lv6_or_1), //o--
.lza_any_b(ex4_lza_any_b), //i--
.lza_amt_b(ex4_lza_amt_b[0:7]) //o--
);
assign ex4_no_edge_b = (~ex4_lza_any_b);
//=###############################################################
//= ex5 latches
//=###############################################################
assign ex4_rgt_amt_b[0:7] = (~f_lze_ex4_sh_rgt_amt[0:7]);
assign ex4_sh_rgt_en_b = (~f_lze_ex4_sh_rgt_en);
assign ex4_lv6_or_0_b = (~ex4_lv6_or_0);
assign ex4_lv6_or_1_b = (~ex4_lv6_or_1);
assign ex4_lv6_or_0_t = (~ex4_lv6_or_0_b);
assign ex4_lv6_or_1_t = (~ex4_lv6_or_1_b);
assign ex4_lza_dcd64_0_b = (~(ex4_lv6_or_0_t & ex4_sh_rgt_en_b));
assign ex4_lza_dcd64_1_b = (~(ex4_lv6_or_0_b & ex4_lv6_or_1_t & ex4_sh_rgt_en_b));
assign ex4_lza_dcd64_2_b = (~(ex4_lv6_or_0_b & ex4_lv6_or_1_b & ex4_sh_rgt_en_b));
tri_inv_nlats #(.WIDTH(9), .NEEDS_SRESET(0)) ex5_dcd_lat(
.vd(vdd),
.gd(gnd),
.lclk(lza_ex5_lclk), // lclk.clk
.d1clk(lza_ex5_d1clk),
.d2clk(lza_ex5_d2clk),
.scanin(ex5_dcd_si[0:8]),
.scanout(ex5_dcd_so[0:8]),
.d({ex4_lza_dcd64_0_b, //( 0)
ex4_lza_dcd64_0_b, //( 1)
ex4_lza_dcd64_0_b, //( 2)
ex4_lza_dcd64_1_b, //( 3)
ex4_lza_dcd64_1_b, //( 4)
ex4_lza_dcd64_2_b, //( 5)
ex4_sh_rgt_en_b, //( 6)
ex4_sh_rgt_en_b, //( 7)
ex4_no_edge_b}), //(24)
//-----------------
.qb({ex5_lza_dcd64_cp1[0], //( 6)
ex5_lza_dcd64_cp2[0], //( 9)
ex5_lza_dcd64_cp3[0], //( 1)
ex5_lza_dcd64_cp1[1], //( 7)
ex5_lza_dcd64_cp2[1], //( 0)
ex5_lza_dcd64_cp1[2], //( 8)
ex5_sh_rgt_en, //( 2)
ex5_sh_rgt_en_eov, //( 3)
ex5_no_edge}) //(24)
);
tri_nand2_nlats #(.WIDTH(16), .NEEDS_SRESET(0)) ex5_amt_lat(
.vd(vdd),
.gd(gnd),
.lclk(lza_ex5_lclk), //in --lclk.clk
.d1clk(lza_ex5_d1clk), //in
.d2clk(lza_ex5_d2clk), //in
.scanin(ex5_amt_si[0:15]),
.scanout(ex5_amt_so[0:15]),
.a1({ ex4_lza_amt_b[0], //( 8)
ex4_lza_amt_b[0], //( 9)
ex4_lza_amt_b[1], //(10)
ex4_lza_amt_b[1], //(11)
ex4_lza_amt_b[2], //(12)
ex4_lza_amt_b[2], //(13)
ex4_lza_amt_b[3], //(14)
ex4_lza_amt_b[3], //(15)
ex4_lza_amt_b[4], //(16)
ex4_lza_amt_b[4], //(17)
ex4_lza_amt_b[5], //(18)
ex4_lza_amt_b[5], //(19)
ex4_lza_amt_b[6], //(20)
ex4_lza_amt_b[6], //(21)
ex4_lza_amt_b[7], //(22)
ex4_lza_amt_b[7]}), //(23)
.a2({ ex4_rgt_amt_b[0], //( 8)
ex4_rgt_amt_b[0], //( 9)
ex4_rgt_amt_b[1], //(10)
ex4_rgt_amt_b[1], //(11)
ex4_rgt_amt_b[2], //(12)
ex4_rgt_amt_b[2], //(13)
ex4_rgt_amt_b[3], //(14)
ex4_rgt_amt_b[3], //(15)
ex4_rgt_amt_b[4], //(16)
ex4_rgt_amt_b[4], //(17)
ex4_rgt_amt_b[5], //(18)
ex4_rgt_amt_b[5], //(19)
ex4_rgt_amt_b[6], //(20)
ex4_rgt_amt_b[6], //(21)
ex4_rgt_amt_b[7], //(22)
ex4_rgt_amt_b[7] }), //(23)
//-----------------
.qb({ ex5_amt[0], //( 0)
ex5_amt_eov[0], //( 8)
ex5_amt[1], //(11)
ex5_amt_eov[1], //(19)
ex5_amt[2], //(12)
ex5_amt_eov[2], //(10)
ex5_amt[3], //(13)
ex5_amt_eov[3], //(11)
ex5_amt[4], //(14)
ex5_amt_eov[4], //(12)
ex5_amt[5], //(15)
ex5_amt_eov[5], //(13)
ex5_amt[6], //(26)
ex5_amt_eov[6], //(24)
ex5_amt[7], //(27)
ex5_amt_eov[7]}) //(24)
);
assign f_lza_ex5_sh_rgt_en = ex5_sh_rgt_en;
assign f_lza_ex5_sh_rgt_en_eov = ex5_sh_rgt_en_eov;
assign f_lza_ex5_lza_amt = ex5_amt[0:7]; //output-- --fnrm--
assign f_lza_ex5_lza_dcd64_cp1[0:2] = ex5_lza_dcd64_cp1[0:2]; //ouptut-- --fnrm
assign f_lza_ex5_lza_dcd64_cp2[0:1] = ex5_lza_dcd64_cp2[0:1]; //ouptut-- --fnrm
assign f_lza_ex5_lza_dcd64_cp3[0] = ex5_lza_dcd64_cp3[0]; //ouptut-- --fnrm
assign f_lza_ex5_lza_amt_eov = ex5_amt_eov[0:7]; //output-- --feov--
assign f_lza_ex5_no_lza_edge = ex5_no_edge; //output-- --fpic--
//=###############################################################
//= scan string
//=###############################################################
assign ex4_lzo_si[0:162] = {ex4_lzo_so[1:162], f_lza_si};
assign ex4_sub_si[0] = ex4_lzo_so[0];
assign ex5_amt_si[0:15] = {ex5_amt_so[1:15], ex4_sub_so[0]};
assign ex5_dcd_si[0:8] = {ex5_dcd_so[1:8], ex5_amt_so[0]};
assign act_si[0:5] = {act_so[1:5], ex5_dcd_so[0]};
assign f_lza_so = act_so[0];
endmodule |
module fu_add(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
f_add_si,
f_add_so,
ex2_act_b,
f_sa3_ex4_s,
f_sa3_ex4_c,
f_alg_ex4_frc_sel_p1,
f_alg_ex4_sticky,
f_alg_ex3_effsub_eac_b,
f_alg_ex3_prod_z,
f_pic_ex4_is_gt,
f_pic_ex4_is_lt,
f_pic_ex4_is_eq,
f_pic_ex4_is_nan,
f_pic_ex4_cmp_sgnpos,
f_pic_ex4_cmp_sgnneg,
f_add_ex5_res,
f_add_ex5_flag_nan,
f_add_ex5_flag_gt,
f_add_ex5_flag_lt,
f_add_ex5_flag_eq,
f_add_ex5_fpcc_iu,
f_add_ex5_sign_carry,
f_add_ex5_to_int_ovf_wd,
f_add_ex5_to_int_ovf_dw,
f_add_ex5_sticky
);
// parameter expand_type = 2; // 0 - ibm tech, 1 - other );
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input [3:4] delay_lclkr; // tidn,
input [3:4] mpw1_b; // tidn,
input [0:0] mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input f_add_si; //perv
output f_add_so; //perv
input ex2_act_b; //act
input [0:162] f_sa3_ex4_s; // data
input [53:161] f_sa3_ex4_c; // data
input f_alg_ex4_frc_sel_p1; // rounding converts
input f_alg_ex4_sticky; // part of eac control
input f_alg_ex3_effsub_eac_b; // already shut off for algByp
input f_alg_ex3_prod_z;
input f_pic_ex4_is_gt; // compare
input f_pic_ex4_is_lt; // compare
input f_pic_ex4_is_eq; // compare
input f_pic_ex4_is_nan; // compare
input f_pic_ex4_cmp_sgnpos; // compare
input f_pic_ex4_cmp_sgnneg; // compare
output [0:162] f_add_ex5_res; // RESULT
output f_add_ex5_flag_nan; // compare for fpscr
output f_add_ex5_flag_gt; // compare for fpscr
output f_add_ex5_flag_lt; // compare for fpscr
output f_add_ex5_flag_eq; // compare for fpscr
output [0:3] f_add_ex5_fpcc_iu; // compare for iu
output f_add_ex5_sign_carry; // select sign from product/addend
output [0:1] f_add_ex5_to_int_ovf_wd; // raw data
output [0:1] f_add_ex5_to_int_ovf_dw; // raw data
output f_add_ex5_sticky; // for nrm
parameter tiup = 1'b1;
parameter tidn = 1'b0;
////#################################
////# sigdef : non-functional
////#################################
wire thold_0_b;
wire thold_0;
wire sg_0;
wire force_t;
wire ex2_act;
wire ex3_act;
wire ex4_act;
wire [0:8] act_si;
wire [0:8] act_so;
wire [0:162] ex5_res_so;
wire [0:162] ex5_res_si;
wire [0:9] ex5_cmp_so;
wire [0:9] ex5_cmp_si;
wire [0:3] spare_unused;
////#################################
////# sigdef : functional
////#################################
wire [0:162] ex4_s;
wire [53:161] ex4_c;
wire ex4_flag_nan;
wire ex4_flag_gt;
wire ex4_flag_lt;
wire ex4_flag_eq;
wire ex4_sign_carry;
wire ex4_inc_all1;
wire [1:6] ex4_inc_byt_c_glb;
wire [1:6] ex4_inc_byt_c_glb_b;
wire [0:52] ex4_inc_p1;
wire [0:52] ex4_inc_p0;
wire [53:162] ex4_s_p0;
wire [53:162] ex4_s_p1;
wire [0:162] ex4_res;
wire ex3_effsub;
wire ex4_effsub;
wire ex3_effadd_npz;
wire ex3_effsub_npz;
wire ex4_effsub_npz;
wire ex4_effadd_npz;
wire ex4_flip_inc_p0;
wire ex4_flip_inc_p1;
wire ex4_inc_sel_p0;
wire ex4_inc_sel_p1;
wire [0:162] ex5_res;
wire [0:162] ex5_res_b;
wire [0:162] ex5_res_l2_b;
wire ex5_flag_nan_b;
wire ex5_flag_gt_b;
wire ex5_flag_lt_b;
wire ex5_flag_eq_b;
wire [0:3] ex5_fpcc_iu_b;
wire ex5_sign_carry_b;
wire ex5_sticky_b;
wire [0:6] ex4_g16;
wire [0:6] ex4_t16;
wire [1:6] ex4_g128;
wire [1:6] ex4_t128;
wire [1:6] ex4_g128_b;
wire [1:6] ex4_t128_b;
wire [0:6] ex4_inc_byt_c_b;
wire [0:6] ex4_eac_sel_p0n;
wire [0:6] ex4_eac_sel_p0;
wire [0:6] ex4_eac_sel_p1;
wire ex4_flag_nan_cp1;
wire ex4_flag_gt_cp1;
wire ex4_flag_lt_cp1;
wire ex4_flag_eq_cp1;
wire add_ex5_d1clk;
wire add_ex5_d2clk;
wire [0:`NCLK_WIDTH-1] add_ex5_lclk;
wire [53:162] ex4_s_p0n;
wire [53:162] ex4_res_p0n_b;
wire [53:162] ex4_res_p0_b;
wire [53:162] ex4_res_p1_b;
wire [0:52] ex4_inc_p0_x;
wire [0:52] ex4_inc_p1_x;
wire [0:52] ex4_incx_p0_b;
wire [0:52] ex4_incx_p1_b;
wire [53:162] ex4_sel_a1;
wire [53:162] ex4_sel_a2;
wire [53:162] ex4_sel_a3;
////################################################################
////# pervasive
////################################################################
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
////################################################################
////# act
////################################################################
assign ex2_act = (~ex2_act_b);
assign ex3_effsub = (~f_alg_ex3_effsub_eac_b);
assign ex3_effsub_npz = (~f_alg_ex3_effsub_eac_b) & (~f_alg_ex3_prod_z);
assign ex3_effadd_npz = f_alg_ex3_effsub_eac_b & (~f_alg_ex3_prod_z);
tri_rlmreg_p #(.WIDTH(9), .NEEDS_SRESET(0)) act_lat(
.force_t(force_t), //i-- tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[3]), //i-- tidn,
.mpw1_b(mpw1_b[3]), //i-- tidn,
.mpw2_b(mpw2_b[0]), //i-- tidn,
.nclk(nclk),
.act(fpu_enable),
.thold_b(thold_0_b),
.sg(sg_0),
.vd(vdd),
.gd(gnd),
.scout(act_so),
.scin(act_si),
//-----------------
.din({ spare_unused[0],
spare_unused[1],
ex2_act,
ex3_act,
ex3_effsub,
ex3_effsub_npz,
ex3_effadd_npz,
spare_unused[2],
spare_unused[3]}),
//-----------------
.dout({ spare_unused[0],
spare_unused[1],
ex3_act,
ex4_act,
ex4_effsub,
ex4_effsub_npz,
ex4_effadd_npz,
spare_unused[2],
spare_unused[3]})
);
tri_lcbnd add_ex5_lcb(
.delay_lclkr(delay_lclkr[4]), // tidn ,--in
.mpw1_b(mpw1_b[4]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in
.nclk(nclk), //in
.vd(vdd), //inout
.gd(gnd), //inout
.act(ex4_act), //in
.sg(sg_0), //in
.thold_b(thold_0_b), //in
.d1clk(add_ex5_d1clk), //out
.d2clk(add_ex5_d2clk), //out
.lclk(add_ex5_lclk) //out
);
////################################################################
////# ex4 logic
////################################################################
assign ex4_s[0:162] = f_sa3_ex4_s[0:162];
assign ex4_c[53:161] = f_sa3_ex4_c[53:161];
//ex4 incrementer-----------------------------------------
//ex4 incr (global carry)---------------------------------
fu_add_all1 all1(
.ex4_inc_byt_c_b(ex4_inc_byt_c_b[0:6]), //i--
.ex4_inc_byt_c_glb(ex4_inc_byt_c_glb[1:6]), //o--
.ex4_inc_byt_c_glb_b(ex4_inc_byt_c_glb_b[1:6]), //o--
.ex4_inc_all1(ex4_inc_all1) //o--
);
//ex4 incr (byte sections) -------------------------------------------------
fu_loc8inc_lsb inc8_6(
.co_b(ex4_inc_byt_c_b[6]), //o--
.x(ex4_s[48:52]), //i--
.s0(ex4_inc_p0[48:52]), //o--
.s1(ex4_inc_p1[48:52]) //o--
);
fu_loc8inc inc8_5(
.ci(ex4_inc_byt_c_glb[6]), //i--
.ci_b(ex4_inc_byt_c_glb_b[6]), //i--
.co_b(ex4_inc_byt_c_b[5]), //o--
.x(ex4_s[40:47]), //i--
.s0(ex4_inc_p0[40:47]), //o--
.s1(ex4_inc_p1[40:47]) //o--
);
fu_loc8inc inc8_4(
.ci(ex4_inc_byt_c_glb[5]), //i--
.ci_b(ex4_inc_byt_c_glb_b[5]), //i--
.co_b(ex4_inc_byt_c_b[4]), //o--
.x(ex4_s[32:39]), //i--
.s0(ex4_inc_p0[32:39]), //o--
.s1(ex4_inc_p1[32:39]) //o--
);
fu_loc8inc inc8_3(
.ci(ex4_inc_byt_c_glb[4]), //i--
.ci_b(ex4_inc_byt_c_glb_b[4]), //i--
.co_b(ex4_inc_byt_c_b[3]), //o--
.x(ex4_s[24:31]), //i--
.s0(ex4_inc_p0[24:31]), //o--
.s1(ex4_inc_p1[24:31]) //o--
);
fu_loc8inc inc8_2(
.ci(ex4_inc_byt_c_glb[3]), //i--
.ci_b(ex4_inc_byt_c_glb_b[3]), //i--
.co_b(ex4_inc_byt_c_b[2]), //o--
.x(ex4_s[16:23]), //i--
.s0(ex4_inc_p0[16:23]), //o--
.s1(ex4_inc_p1[16:23]) //o--
);
fu_loc8inc inc8_1(
.ci(ex4_inc_byt_c_glb[2]), //i--
.ci_b(ex4_inc_byt_c_glb_b[2]), //i--
.co_b(ex4_inc_byt_c_b[1]), //o--
.x(ex4_s[8:15]), //i--
.s0(ex4_inc_p0[8:15]), //o--
.s1(ex4_inc_p1[8:15]) //o--
);
fu_loc8inc inc8_0(
.ci(ex4_inc_byt_c_glb[1]), //i--
.ci_b(ex4_inc_byt_c_glb_b[1]), //i--
.co_b(ex4_inc_byt_c_b[0]), //o--
.x(ex4_s[0:7]), //i--
.s0(ex4_inc_p0[0:7]), //o--
.s1(ex4_inc_p1[0:7]) //o--
);
//ex4 adder-----------------------------------------------
// sum[53] is the raw aligner bit
// car[53] includes the bogus bit
// position 53 also includes a "1" to push out the bogus bit
//
// [0:52] needs "111...111" to push out the bogus bit
// but the first co of [53] is suppressed instead
//
// ex4_53 => s53, c53, "1", ci : 2nd co : s53 * c53 * ci
// sums
// [0] 053:068
// [1] 069:084
// [2] 085:100
// [3] 101:116
// [4] 117:132
// [5] 133:148
// [6] 149:164 <162,"1","1">
fu_hc16pp_msb hc16_0(
.x(ex4_s[53:68]), //i--
.y(ex4_c[53:68]), //i--
.ci0(ex4_g128[1]), //i--
.ci0_b(ex4_g128_b[1]), //i--
.ci1(ex4_t128[1]), //i--
.ci1_b(ex4_t128_b[1]), //i--
.s0(ex4_s_p0[53:68]), //o--
.s1(ex4_s_p1[53:68]), //o--
.g16(ex4_g16[0]), //o--
.t16(ex4_t16[0]) //o--
);
fu_hc16pp hc16_1(
.x(ex4_s[69:84]), //i--
.y(ex4_c[69:84]), //i--
.ci0(ex4_g128[2]), //i--
.ci0_b(ex4_g128_b[2]), //i--
.ci1(ex4_t128[2]), //i--
.ci1_b(ex4_t128_b[2]), //i--
.s0(ex4_s_p0[69:84]), //o--
.s1(ex4_s_p1[69:84]), //o--
.g16(ex4_g16[1]), //o--
.t16(ex4_t16[1]) //o--
);
fu_hc16pp hc16_2(
.x(ex4_s[85:100]), //i--
.y(ex4_c[85:100]), //i--
.ci0(ex4_g128[3]), //i--
.ci0_b(ex4_g128_b[3]), //i--
.ci1(ex4_t128[3]), //i--
.ci1_b(ex4_t128_b[3]), //i--
.s0(ex4_s_p0[85:100]), //o--
.s1(ex4_s_p1[85:100]), //o--
.g16(ex4_g16[2]), //o--
.t16(ex4_t16[2]) //o--
);
fu_hc16pp hc16_3(
.x(ex4_s[101:116]), //i--
.y(ex4_c[101:116]), //i--
.ci0(ex4_g128[4]), //i--
.ci0_b(ex4_g128_b[4]), //i--
.ci1(ex4_t128[4]), //i--
.ci1_b(ex4_t128_b[4]), //i--
.s0(ex4_s_p0[101:116]), //o--
.s1(ex4_s_p1[101:116]), //o--
.g16(ex4_g16[3]), //o--
.t16(ex4_t16[3]) //o--
);
fu_hc16pp hc16_4(
.x(ex4_s[117:132]), //i--
.y(ex4_c[117:132]), //i--
.ci0(ex4_g128[5]), //i--
.ci0_b(ex4_g128_b[5]), //i--
.ci1(ex4_t128[5]), //i--
.ci1_b(ex4_t128_b[5]), //i--
.s0(ex4_s_p0[117:132]), //o--
.s1(ex4_s_p1[117:132]), //o--
.g16(ex4_g16[4]), //o--
.t16(ex4_t16[4]) //o--
);
fu_hc16pp hc16_5(
.x(ex4_s[133:148]), //i--
.y(ex4_c[133:148]), //i--
.ci0(ex4_g128[6]), //i--
.ci0_b(ex4_g128_b[6]), //i--
.ci1(ex4_t128[6]), //i--
.ci1_b(ex4_t128_b[6]), //i--
.s0(ex4_s_p0[133:148]), //o--
.s1(ex4_s_p1[133:148]), //o--
.g16(ex4_g16[5]), //o--
.t16(ex4_t16[5]) //o--
);
fu_hc16pp_lsb hc16_6(
.x(ex4_s[149:162]), //i--
.y(ex4_c[149:161]), //i--
.s0(ex4_s_p0[149:162]), //o--
.s1(ex4_s_p1[149:162]), //o--
.g16(ex4_g16[6]), //o--
.t16(ex4_t16[6]) //o--
);
//=#########################################################################################
//=## EACMUX (move the nand3 into technology dependent latch ... latch not yet available)
//=#########################################################################################
//------------------------------------------------
// EACMUX: incrementer bits
//------------------------------------------------
assign ex4_inc_p0_x[0:52] = ex4_inc_p0[0:52] ^ {53{ex4_flip_inc_p0}};
assign ex4_inc_p1_x[0:52] = ex4_inc_p1[0:52] ^ {53{ex4_flip_inc_p1}};
assign ex4_incx_p0_b[0:52] = (~({53{ex4_inc_sel_p0}} & ex4_inc_p0_x[0:52]));
assign ex4_incx_p1_b[0:52] = (~({53{ex4_inc_sel_p1}} & ex4_inc_p1_x[0:52]));
assign ex4_res[0:52] = (~(ex4_incx_p0_b[0:52] & ex4_incx_p1_b[0:52]));
//------------------------------------------------
// EACMUX: adder bits
//------------------------------------------------
assign ex4_sel_a1[53:68] = {16{ex4_eac_sel_p0n[0]}}; //rename
assign ex4_sel_a1[69:84] = {16{ex4_eac_sel_p0n[1]}}; //rename
assign ex4_sel_a1[85:100] = {16{ex4_eac_sel_p0n[2]}}; //rename
assign ex4_sel_a1[101:116] = {16{ex4_eac_sel_p0n[3]}}; //rename
assign ex4_sel_a1[117:132] = {16{ex4_eac_sel_p0n[4]}}; //rename
assign ex4_sel_a1[133:148] = {16{ex4_eac_sel_p0n[5]}}; //rename
assign ex4_sel_a1[149:162] = {14{ex4_eac_sel_p0n[6]}}; //rename
assign ex4_sel_a2[53:68] = {16{ex4_eac_sel_p0[0]}}; //rename
assign ex4_sel_a2[69:84] = {16{ex4_eac_sel_p0[1]}}; //rename
assign ex4_sel_a2[85:100] = {16{ex4_eac_sel_p0[2]}}; //rename
assign ex4_sel_a2[101:116] = {16{ex4_eac_sel_p0[3]}}; //rename
assign ex4_sel_a2[117:132] = {16{ex4_eac_sel_p0[4]}}; //rename
assign ex4_sel_a2[133:148] = {16{ex4_eac_sel_p0[5]}}; //rename
assign ex4_sel_a2[149:162] = {14{ex4_eac_sel_p0[6]}}; //rename
assign ex4_sel_a3[53:68] = {16{ex4_eac_sel_p1[0]}}; //rename
assign ex4_sel_a3[69:84] = {16{ex4_eac_sel_p1[1]}}; //rename
assign ex4_sel_a3[85:100] = {16{ex4_eac_sel_p1[2]}}; //rename
assign ex4_sel_a3[101:116] = {16{ex4_eac_sel_p1[3]}}; //rename
assign ex4_sel_a3[117:132] = {16{ex4_eac_sel_p1[4]}}; //rename
assign ex4_sel_a3[133:148] = {16{ex4_eac_sel_p1[5]}}; //rename
assign ex4_sel_a3[149:162] = {14{ex4_eac_sel_p1[6]}}; //rename
assign ex4_s_p0n[53:162] = (~(ex4_s_p0[53:162]));
assign ex4_res_p0n_b[53:162] = (~(ex4_sel_a1[53:162] & ex4_s_p0n[53:162]));
assign ex4_res_p0_b[53:162] = (~(ex4_sel_a2[53:162] & ex4_s_p0[53:162]));
assign ex4_res_p1_b[53:162] = (~(ex4_sel_a3[53:162] & ex4_s_p1[53:162]));
assign ex4_res[53:162] = (~(ex4_res_p0n_b[53:162] & ex4_res_p0_b[53:162] & ex4_res_p1_b[53:162]));
//=##################################################################################
//=# global carry chain, eac_selects, compare, sign_carry
//=##################################################################################
fu_add_glbc glbc(
.ex4_g16(ex4_g16[0:6]), //i--
.ex4_t16(ex4_t16[0:6]), //i--
.ex4_inc_all1(ex4_inc_all1), //i--
.ex4_effsub(ex4_effsub), //i--
.ex4_effsub_npz(ex4_effsub_npz), //i--
.ex4_effadd_npz(ex4_effadd_npz), //i--
.f_alg_ex4_frc_sel_p1(f_alg_ex4_frc_sel_p1), //i--
.f_alg_ex4_sticky(f_alg_ex4_sticky), //i--
.f_pic_ex4_is_nan(f_pic_ex4_is_nan), //i--
.f_pic_ex4_is_gt(f_pic_ex4_is_gt), //i--
.f_pic_ex4_is_lt(f_pic_ex4_is_lt), //i--
.f_pic_ex4_is_eq(f_pic_ex4_is_eq), //i--
.f_pic_ex4_cmp_sgnpos(f_pic_ex4_cmp_sgnpos), //i--
.f_pic_ex4_cmp_sgnneg(f_pic_ex4_cmp_sgnneg), //i--
.ex4_g128(ex4_g128[1:6]), //o--
.ex4_g128_b(ex4_g128_b[1:6]), //o--
.ex4_t128(ex4_t128[1:6]), //o--
.ex4_t128_b(ex4_t128_b[1:6]), //o--
.ex4_flip_inc_p0(ex4_flip_inc_p0), //o--
.ex4_flip_inc_p1(ex4_flip_inc_p1), //o--
.ex4_inc_sel_p0(ex4_inc_sel_p0), //o--
.ex4_inc_sel_p1(ex4_inc_sel_p1), //o--
.ex4_eac_sel_p0n(ex4_eac_sel_p0n), //o--
.ex4_eac_sel_p0(ex4_eac_sel_p0), //o--
.ex4_eac_sel_p1(ex4_eac_sel_p1), //o--
.ex4_sign_carry(ex4_sign_carry), //o--
.ex4_flag_nan_cp1(ex4_flag_nan_cp1), //o-- duplicate lat driven by unique gate
.ex4_flag_gt_cp1(ex4_flag_gt_cp1), //o-- duplicate lat driven by unique gate
.ex4_flag_lt_cp1(ex4_flag_lt_cp1), //o-- duplicate lat driven by unique gate
.ex4_flag_eq_cp1(ex4_flag_eq_cp1), //o-- duplicate lat driven by unique gate
.ex4_flag_nan(ex4_flag_nan), //o--
.ex4_flag_gt(ex4_flag_gt), //o--
.ex4_flag_lt(ex4_flag_lt), //o--
.ex4_flag_eq(ex4_flag_eq) //o--
);
////################################################################
////# ex5 latches
////################################################################
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex5_res_hi_lat(
.vd(vdd),
.gd(gnd),
.lclk(add_ex5_lclk), // lclk.clk
.d1clk(add_ex5_d1clk),
.d2clk(add_ex5_d2clk),
.scanin(ex5_res_si[0:52]),
.scanout(ex5_res_so[0:52]),
.d(ex4_res[0:52]),
.qb(ex5_res_l2_b[0:52]) //LAT
);
tri_inv_nlats #(.WIDTH(110), .NEEDS_SRESET(0)) ex5_res_lo_lat(
.vd(vdd),
.gd(gnd),
.lclk(add_ex5_lclk), // lclk.clk
.d1clk(add_ex5_d1clk),
.d2clk(add_ex5_d2clk),
.scanin(ex5_res_si[53:162]),
.scanout(ex5_res_so[53:162]),
.d(ex4_res[53:162]),
.qb(ex5_res_l2_b[53:162]) //LAT
);
assign ex5_res[0:162] = (~ex5_res_l2_b[0:162]);
assign ex5_res_b[0:162] = (~ex5_res[0:162]);
assign f_add_ex5_res[0:162] = (~ex5_res_b[0:162]); // output
tri_inv_nlats #(.WIDTH(10), .NEEDS_SRESET(0)) ex5_cmp_lat(
.vd(vdd),
.gd(gnd),
.lclk(add_ex5_lclk), // lclk.clk
.d1clk(add_ex5_d1clk),
.d2clk(add_ex5_d2clk),
.scanin(ex5_cmp_si),
.scanout(ex5_cmp_so),
//-----------------
.d({ ex4_flag_lt,
ex4_flag_lt_cp1,
ex4_flag_gt,
ex4_flag_gt_cp1,
ex4_flag_eq,
ex4_flag_eq_cp1,
ex4_flag_nan,
ex4_flag_nan_cp1,
ex4_sign_carry,
f_alg_ex4_sticky}),
//-----------------
.qb({ ex5_flag_lt_b, //LAT
ex5_fpcc_iu_b[0], //LAT
ex5_flag_gt_b, //LAT
ex5_fpcc_iu_b[1], //LAT
ex5_flag_eq_b, //LAT
ex5_fpcc_iu_b[2], //LAT
ex5_flag_nan_b, //LAT
ex5_fpcc_iu_b[3], //LAT
ex5_sign_carry_b, //LAT
ex5_sticky_b}) //LAT
);
assign f_add_ex5_flag_nan = (~ex5_flag_nan_b); //output
assign f_add_ex5_flag_gt = (~ex5_flag_gt_b); //output
assign f_add_ex5_flag_lt = (~ex5_flag_lt_b); //output
assign f_add_ex5_flag_eq = (~ex5_flag_eq_b); //output
assign f_add_ex5_fpcc_iu[0:3] = (~ex5_fpcc_iu_b[0:3]); //output
assign f_add_ex5_sign_carry = (~ex5_sign_carry_b); //output
assign f_add_ex5_sticky = (~ex5_sticky_b); //output
assign f_add_ex5_to_int_ovf_wd[0] = ex5_res[130]; //output
assign f_add_ex5_to_int_ovf_wd[1] = ex5_res[131]; //output
assign f_add_ex5_to_int_ovf_dw[0] = ex5_res[98]; //output
assign f_add_ex5_to_int_ovf_dw[1] = ex5_res[99]; //output
////################################################################
////# ex5 logic
////################################################################
////################################################################
////# scan string
////################################################################
assign act_si[0:8] = {act_so[1:8], f_add_si};
assign ex5_res_si[0:162] = {ex5_res_so[1:162], act_so[0]};
assign ex5_cmp_si[0:9] = {ex5_cmp_so[1:9], ex5_res_so[0]};
assign f_add_so = ex5_cmp_so[0];
endmodule |
module pcq(
// Include model build parameters
`include "tri_a2o.vh"
// inout vdd,
// inout gnd,
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk
input [0:`NCLK_WIDTH-1] nclk,
//SCOM and Register Interfaces
// SCOM Satellite
input [0:3] an_ac_scom_sat_id,
input an_ac_scom_dch,
input an_ac_scom_cch,
output ac_an_scom_dch,
output ac_an_scom_cch,
// Slow SPR
input slowspr_val_in,
input slowspr_rw_in,
input [0:1] slowspr_etid_in,
input [0:9] slowspr_addr_in,
input [64-`GPR_WIDTH:63] slowspr_data_in,
input slowspr_done_in,
input [0:`THREADS-1] cp_flush,
output slowspr_val_out,
output slowspr_rw_out,
output [0:1] slowspr_etid_out,
output [0:9] slowspr_addr_out,
output [64-`GPR_WIDTH:63] slowspr_data_out,
output slowspr_done_out,
//FIR and Error Signals
output [0:`THREADS-1] ac_an_special_attn,
output [0:2] ac_an_checkstop,
output [0:2] ac_an_local_checkstop,
output [0:2] ac_an_recov_err,
output ac_an_trace_error,
output ac_an_livelock_active,
input an_ac_checkstop,
input [0:`THREADS-1] fu_pc_err_regfile_parity,
input [0:`THREADS-1] fu_pc_err_regfile_ue,
input iu_pc_err_icache_parity,
input iu_pc_err_icachedir_parity,
input iu_pc_err_icachedir_multihit,
input iu_pc_err_ierat_parity,
input iu_pc_err_ierat_multihit,
input iu_pc_err_btb_parity,
input [0:`THREADS-1] iu_pc_err_cpArray_parity,
input [0:`THREADS-1] iu_pc_err_ucode_illegal,
input [0:`THREADS-1] iu_pc_err_mchk_disabled,
input [0:`THREADS-1] iu_pc_err_debug_event,
input lq_pc_err_dcache_parity,
input lq_pc_err_dcachedir_ldp_parity,
input lq_pc_err_dcachedir_stp_parity,
input lq_pc_err_dcachedir_ldp_multihit,
input lq_pc_err_dcachedir_stp_multihit,
input lq_pc_err_derat_parity,
input lq_pc_err_derat_multihit,
input lq_pc_err_l2intrf_ecc,
input lq_pc_err_l2intrf_ue,
input lq_pc_err_invld_reld,
input lq_pc_err_l2credit_overrun,
input [0:`THREADS-1] lq_pc_err_regfile_parity,
input [0:`THREADS-1] lq_pc_err_regfile_ue,
input lq_pc_err_prefetcher_parity,
input lq_pc_err_relq_parity,
input mm_pc_err_tlb_parity,
input mm_pc_err_tlb_multihit,
input mm_pc_err_tlb_lru_parity,
input mm_pc_err_local_snoop_reject,
input [0:`THREADS-1] xu_pc_err_sprg_ecc,
input [0:`THREADS-1] xu_pc_err_sprg_ue,
input [0:`THREADS-1] xu_pc_err_regfile_parity,
input [0:`THREADS-1] xu_pc_err_regfile_ue,
input [0:`THREADS-1] xu_pc_err_llbust_attempt,
input [0:`THREADS-1] xu_pc_err_llbust_failed,
input [0:`THREADS-1] xu_pc_err_wdt_reset,
input [0:`THREADS-1] iu_pc_err_attention_instr,
output pc_iu_inj_icache_parity,
output pc_iu_inj_icachedir_parity,
output pc_iu_inj_icachedir_multihit,
output pc_lq_inj_dcache_parity,
output pc_lq_inj_dcachedir_ldp_parity,
output pc_lq_inj_dcachedir_stp_parity,
output pc_lq_inj_dcachedir_ldp_multihit,
output pc_lq_inj_dcachedir_stp_multihit,
output pc_lq_inj_prefetcher_parity,
output pc_lq_inj_relq_parity,
output [0:`THREADS-1] pc_xu_inj_sprg_ecc,
output [0:`THREADS-1] pc_fx0_inj_regfile_parity,
output [0:`THREADS-1] pc_fx1_inj_regfile_parity,
output [0:`THREADS-1] pc_lq_inj_regfile_parity,
output [0:`THREADS-1] pc_fu_inj_regfile_parity,
output [0:`THREADS-1] pc_xu_inj_llbust_attempt,
output [0:`THREADS-1] pc_xu_inj_llbust_failed,
output [0:`THREADS-1] pc_iu_inj_cpArray_parity,
// Unit quiesce and credit status bits
input [0:`THREADS-1] iu_pc_quiesce,
input [0:`THREADS-1] iu_pc_icache_quiesce,
input [0:`THREADS-1] lq_pc_ldq_quiesce,
input [0:`THREADS-1] lq_pc_stq_quiesce,
input [0:`THREADS-1] lq_pc_pfetch_quiesce,
input [0:`THREADS-1] mm_pc_tlb_req_quiesce,
input [0:`THREADS-1] mm_pc_tlb_ctl_quiesce,
input [0:`THREADS-1] mm_pc_htw_quiesce,
input [0:`THREADS-1] mm_pc_inval_quiesce,
input [0:`THREADS-1] iu_pc_fx0_credit_ok,
input [0:`THREADS-1] iu_pc_fx1_credit_ok,
input [0:`THREADS-1] iu_pc_axu0_credit_ok,
input [0:`THREADS-1] iu_pc_axu1_credit_ok,
input [0:`THREADS-1] iu_pc_lq_credit_ok,
input [0:`THREADS-1] iu_pc_sq_credit_ok,
//Debug Functions
// RAM Command/Data
output [0:31] pc_iu_ram_instr,
output [0:3] pc_iu_ram_instr_ext,
output [0:`THREADS-1] pc_iu_ram_active,
output pc_iu_ram_execute,
input iu_pc_ram_done,
input iu_pc_ram_interrupt,
input iu_pc_ram_unsupported,
output [0:`THREADS-1] pc_xu_ram_active,
input xu_pc_ram_data_val,
input [64-`GPR_WIDTH:63] xu_pc_ram_data,
output [0:`THREADS-1] pc_fu_ram_active,
input fu_pc_ram_data_val,
input [0:63] fu_pc_ram_data,
output [0:`THREADS-1] pc_lq_ram_active,
input lq_pc_ram_data_val,
input [64-`GPR_WIDTH:63] lq_pc_ram_data,
output pc_xu_msrovride_enab,
output pc_xu_msrovride_pr,
output pc_xu_msrovride_gs,
output pc_xu_msrovride_de,
output pc_iu_ram_force_cmplt,
output [0:`THREADS-1] pc_iu_ram_flush_thread,
// THRCTL + PCCR0 Registers
input [0:`THREADS-1] xu_pc_running,
input [0:`THREADS-1] iu_pc_stop_dbg_event,
input [0:`THREADS-1] xu_pc_stop_dnh_instr,
input [0:`THREADS-1] iu_pc_step_done,
output [0:`THREADS-1] pc_iu_stop,
output [0:`THREADS-1] pc_iu_step,
output pc_xu_extirpts_dis_on_stop,
output pc_xu_timebase_dis_on_stop,
output pc_xu_decrem_dis_on_stop,
input an_ac_debug_stop,
output [0:3*`THREADS-1] pc_iu_dbg_action,
output [0:`THREADS-1] pc_iu_spr_dbcr0_edm,
output [0:`THREADS-1] pc_xu_spr_dbcr0_edm,
//Trace/Debug Bus
output [0:31] debug_bus_out,
input [0:31] debug_bus_in,
input [0:3] coretrace_ctrls_in,
output [0:3] coretrace_ctrls_out,
// Debug Select Register outputs to units for debug grouping
output pc_iu_trace_bus_enable,
output pc_fu_trace_bus_enable,
output pc_rv_trace_bus_enable,
output pc_mm_trace_bus_enable,
output pc_xu_trace_bus_enable,
output pc_lq_trace_bus_enable,
output [0:10] pc_iu_debug_mux1_ctrls,
output [0:10] pc_iu_debug_mux2_ctrls,
output [0:10] pc_fu_debug_mux_ctrls,
output [0:10] pc_rv_debug_mux_ctrls,
output [0:10] pc_mm_debug_mux_ctrls,
output [0:10] pc_xu_debug_mux_ctrls,
output [0:10] pc_lq_debug_mux1_ctrls,
output [0:10] pc_lq_debug_mux2_ctrls,
//Performance event mux controls
output [0:39] pc_rv_event_mux_ctrls,
output pc_iu_event_bus_enable,
output pc_fu_event_bus_enable,
output pc_rv_event_bus_enable,
output pc_mm_event_bus_enable,
output pc_xu_event_bus_enable,
output pc_lq_event_bus_enable,
output [0:2] pc_iu_event_count_mode,
output [0:2] pc_fu_event_count_mode,
output [0:2] pc_rv_event_count_mode,
output [0:2] pc_mm_event_count_mode,
output [0:2] pc_xu_event_count_mode,
output [0:2] pc_lq_event_count_mode,
output pc_lq_event_bus_seldbghi,
output pc_lq_event_bus_seldbglo,
output pc_iu_instr_trace_mode,
output pc_iu_instr_trace_tid,
output pc_lq_instr_trace_mode,
output pc_lq_instr_trace_tid,
output pc_xu_instr_trace_mode,
output pc_xu_instr_trace_tid,
input [0:`THREADS-1] xu_pc_perfmon_alert,
output [0:`THREADS-1] pc_xu_spr_cesr1_pmae,
//Reset related
output pc_lq_init_reset,
output pc_iu_init_reset,
//Power Management
output [0:`THREADS-1] ac_an_pm_thread_running,
input [0:`THREADS-1] an_ac_pm_thread_stop,
input [0:`THREADS-1] an_ac_pm_fetch_halt,
output [0:`THREADS-1] pc_iu_pm_fetch_halt,
output ac_an_power_managed,
output ac_an_rvwinkle_mode,
output pc_xu_pm_hold_thread,
input [0:1] xu_pc_spr_ccr0_pme,
input [0:`THREADS-1] xu_pc_spr_ccr0_we,
//Clock, Test, and LCB Controls
input an_ac_gsd_test_enable_dc,
input an_ac_gsd_test_acmode_dc,
input an_ac_ccflush_dc,
input an_ac_ccenable_dc,
input an_ac_lbist_en_dc,
input an_ac_lbist_ip_dc,
input an_ac_lbist_ac_mode_dc,
input an_ac_scan_diag_dc,
input an_ac_scan_dis_dc_b,
// Thold input to clock control macro
input an_ac_rtim_sl_thold_7,
input an_ac_func_sl_thold_7,
input an_ac_func_nsl_thold_7,
input an_ac_ary_nsl_thold_7,
input an_ac_sg_7,
input an_ac_fce_7,
input [0:8] an_ac_scan_type_dc,
// Thold outputs to clock staging
output pc_rp_ccflush_out_dc,
output pc_rp_gptr_sl_thold_4,
output pc_rp_time_sl_thold_4,
output pc_rp_repr_sl_thold_4,
output pc_rp_abst_sl_thold_4,
output pc_rp_abst_slp_sl_thold_4,
output pc_rp_regf_sl_thold_4,
output pc_rp_regf_slp_sl_thold_4,
output pc_rp_func_sl_thold_4,
output pc_rp_func_slp_sl_thold_4,
output pc_rp_cfg_sl_thold_4,
output pc_rp_cfg_slp_sl_thold_4,
output pc_rp_func_nsl_thold_4,
output pc_rp_func_slp_nsl_thold_4,
output pc_rp_ary_nsl_thold_4,
output pc_rp_ary_slp_nsl_thold_4,
output pc_rp_rtim_sl_thold_4,
output pc_rp_sg_4,
output pc_rp_fce_4,
//
output pc_fu_ccflush_dc,
output pc_fu_gptr_sl_thold_3,
output pc_fu_time_sl_thold_3,
output pc_fu_repr_sl_thold_3,
output pc_fu_abst_sl_thold_3,
output pc_fu_abst_slp_sl_thold_3,
output [0:1] pc_fu_func_sl_thold_3,
output [0:1] pc_fu_func_slp_sl_thold_3,
output pc_fu_cfg_sl_thold_3,
output pc_fu_cfg_slp_sl_thold_3,
output pc_fu_func_nsl_thold_3,
output pc_fu_func_slp_nsl_thold_3,
output pc_fu_ary_nsl_thold_3,
output pc_fu_ary_slp_nsl_thold_3,
output [0:1] pc_fu_sg_3,
output pc_fu_fce_3,
//Scanning
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in
input gptr_scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in
input ccfg_scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in
input bcfg_scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in
input dcfg_scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in
input [0:1] func_scan_in,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out
output gptr_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out
output ccfg_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out
output bcfg_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out
output dcfg_scan_out,
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out
output [0:1] func_scan_out
);
//=====================================================================
// Signal Declarations
//=====================================================================
//---------------------------------------------------------------------
// Basic/Misc Signals
wire ct_db_func_scan_out;
wire db_ss_func_scan_out;
wire lcbctrl_gptr_scan_out;
// Misc Controls
wire [0:`THREADS-1] ct_rg_power_managed;
wire ct_ck_pm_raise_tholds;
wire ct_ck_pm_ccflush_disable;
wire rg_ct_dis_pwr_savings;
wire rg_ck_fast_xstop;
wire ct_rg_hold_during_init;
// SRAMD data and load pulse
wire rg_rg_load_sramd;
wire [0:63] rg_rg_sramd_din;
// Clock Controls
wire d_mode_dc;
wire clkoff_dc_b;
wire act_dis_dc;
wire [0:4] delay_lclkr_dc;
wire [0:4] mpw1_dc_b;
wire mpw2_dc_b;
wire pc_pc_ccflush_dc;
wire pc_pc_gptr_sl_thold_0;
wire pc_pc_func_sl_thold_0;
wire pc_pc_func_slp_sl_thold_0;
wire pc_pc_cfg_sl_thold_0;
wire pc_pc_cfg_slp_sl_thold_0;
wire pc_pc_sg_0;
// Trace bus signals
wire sp_rg_trace_bus_enable;
wire rg_db_trace_bus_enable;
wire [0:10] rg_db_debug_mux_ctrls;
wire [0:11] rg_db_dbg_scom;
wire [0:24] rg_db_dbg_thrctls;
wire [0:15] rg_db_dbg_ram;
wire [0:27] rg_db_dbg_fir0_err;
wire [0:19] rg_db_dbg_fir1_err;
wire [0:19] rg_db_dbg_fir2_err;
wire [0:14] rg_db_dbg_fir_misc;
wire [0:14] ct_db_dbg_ctrls;
wire [0:7] rg_db_dbg_spr;
wire vdd;
wire gnd;
// Get rid of sinkless net messages
// synopsys translate_off
(* analysis_not_referenced="true" *)
// synopsys translate_on
wire unused_signals;
assign unused_signals = (|{1'b0, 1'b0});
assign vdd = 1'b1;
assign gnd = 1'b0;
//!! Bugspray Include: pcq;
//=====================================================================
// Start of PCQ Module Instantiations
//=====================================================================
pcq_regs pcq_regs(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.scan_dis_dc_b(an_ac_scan_dis_dc_b),
.lcb_clkoff_dc_b(clkoff_dc_b),
.lcb_d_mode_dc(d_mode_dc),
.lcb_mpw1_dc_b(mpw1_dc_b[0]),
.lcb_mpw2_dc_b(mpw2_dc_b),
.lcb_delay_lclkr_dc(delay_lclkr_dc[0]),
.lcb_act_dis_dc(act_dis_dc),
.lcb_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0),
.lcb_cfg_sl_thold_0(pc_pc_cfg_sl_thold_0),
.lcb_cfg_slp_sl_thold_0(pc_pc_cfg_slp_sl_thold_0),
.lcb_sg_0(pc_pc_sg_0),
.ccfg_scan_in(ccfg_scan_in),
.bcfg_scan_in(bcfg_scan_in),
.dcfg_scan_in(dcfg_scan_in),
.func_scan_in(func_scan_in[0]),
.ccfg_scan_out(ccfg_scan_out),
.bcfg_scan_out(bcfg_scan_out),
.dcfg_scan_out(dcfg_scan_out),
.func_scan_out(func_scan_out[0]),
//SCOM Satellite interface
.an_ac_scom_sat_id(an_ac_scom_sat_id),
.an_ac_scom_dch(an_ac_scom_dch),
.an_ac_scom_cch(an_ac_scom_cch),
.ac_an_scom_dch(ac_an_scom_dch),
.ac_an_scom_cch(ac_an_scom_cch),
//Error Related
.ac_an_special_attn(ac_an_special_attn),
.ac_an_checkstop(ac_an_checkstop),
.ac_an_local_checkstop(ac_an_local_checkstop),
.ac_an_recov_err(ac_an_recov_err),
.ac_an_trace_error(ac_an_trace_error),
.ac_an_livelock_active(ac_an_livelock_active),
.an_ac_checkstop(an_ac_checkstop),
.rg_ck_fast_xstop(rg_ck_fast_xstop),
.fu_pc_err_regfile_parity(fu_pc_err_regfile_parity),
.fu_pc_err_regfile_ue(fu_pc_err_regfile_ue),
.iu_pc_err_icache_parity(iu_pc_err_icache_parity),
.iu_pc_err_icachedir_parity(iu_pc_err_icachedir_parity),
.iu_pc_err_icachedir_multihit(iu_pc_err_icachedir_multihit),
.iu_pc_err_ierat_parity(iu_pc_err_ierat_parity),
.iu_pc_err_ierat_multihit(iu_pc_err_ierat_multihit),
.iu_pc_err_btb_parity(iu_pc_err_btb_parity),
.iu_pc_err_cpArray_parity(iu_pc_err_cpArray_parity),
.iu_pc_err_ucode_illegal(iu_pc_err_ucode_illegal),
.iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled),
.iu_pc_err_debug_event(iu_pc_err_debug_event),
.lq_pc_err_dcache_parity(lq_pc_err_dcache_parity),
.lq_pc_err_dcachedir_ldp_parity(lq_pc_err_dcachedir_ldp_parity),
.lq_pc_err_dcachedir_stp_parity(lq_pc_err_dcachedir_stp_parity),
.lq_pc_err_dcachedir_ldp_multihit(lq_pc_err_dcachedir_ldp_multihit),
.lq_pc_err_dcachedir_stp_multihit(lq_pc_err_dcachedir_stp_multihit),
.lq_pc_err_derat_parity(lq_pc_err_derat_parity),
.lq_pc_err_derat_multihit(lq_pc_err_derat_multihit),
.lq_pc_err_l2intrf_ecc(lq_pc_err_l2intrf_ecc),
.lq_pc_err_l2intrf_ue(lq_pc_err_l2intrf_ue),
.lq_pc_err_invld_reld(lq_pc_err_invld_reld),
.lq_pc_err_l2credit_overrun(lq_pc_err_l2credit_overrun),
.lq_pc_err_regfile_parity(lq_pc_err_regfile_parity),
.lq_pc_err_regfile_ue(lq_pc_err_regfile_ue),
.lq_pc_err_prefetcher_parity(lq_pc_err_prefetcher_parity),
.lq_pc_err_relq_parity(lq_pc_err_relq_parity),
.mm_pc_err_tlb_parity(mm_pc_err_tlb_parity),
.mm_pc_err_tlb_multihit(mm_pc_err_tlb_multihit),
.mm_pc_err_tlb_lru_parity(mm_pc_err_tlb_lru_parity),
.mm_pc_err_local_snoop_reject(mm_pc_err_local_snoop_reject),
.xu_pc_err_sprg_ecc(xu_pc_err_sprg_ecc),
.xu_pc_err_sprg_ue(xu_pc_err_sprg_ue),
.xu_pc_err_regfile_parity(xu_pc_err_regfile_parity),
.xu_pc_err_regfile_ue(xu_pc_err_regfile_ue),
.xu_pc_err_llbust_attempt(xu_pc_err_llbust_attempt),
.xu_pc_err_llbust_failed(xu_pc_err_llbust_failed),
.xu_pc_err_wdt_reset(xu_pc_err_wdt_reset),
.iu_pc_err_attention_instr(iu_pc_err_attention_instr),
.pc_iu_inj_icache_parity(pc_iu_inj_icache_parity),
.pc_iu_inj_icachedir_parity(pc_iu_inj_icachedir_parity),
.pc_iu_inj_icachedir_multihit(pc_iu_inj_icachedir_multihit),
.pc_lq_inj_dcache_parity(pc_lq_inj_dcache_parity),
.pc_lq_inj_dcachedir_ldp_parity(pc_lq_inj_dcachedir_ldp_parity),
.pc_lq_inj_dcachedir_stp_parity(pc_lq_inj_dcachedir_stp_parity),
.pc_lq_inj_dcachedir_ldp_multihit(pc_lq_inj_dcachedir_ldp_multihit),
.pc_lq_inj_dcachedir_stp_multihit(pc_lq_inj_dcachedir_stp_multihit),
.pc_lq_inj_prefetcher_parity(pc_lq_inj_prefetcher_parity),
.pc_lq_inj_relq_parity(pc_lq_inj_relq_parity),
.pc_xu_inj_sprg_ecc(pc_xu_inj_sprg_ecc),
.pc_fx0_inj_regfile_parity(pc_fx0_inj_regfile_parity),
.pc_fx1_inj_regfile_parity(pc_fx1_inj_regfile_parity),
.pc_lq_inj_regfile_parity(pc_lq_inj_regfile_parity),
.pc_fu_inj_regfile_parity(pc_fu_inj_regfile_parity),
.pc_xu_inj_llbust_attempt(pc_xu_inj_llbust_attempt),
.pc_xu_inj_llbust_failed(pc_xu_inj_llbust_failed),
.pc_iu_inj_cpArray_parity(pc_iu_inj_cpArray_parity),
// Unit quiesce and credit status bits
.iu_pc_quiesce(iu_pc_quiesce),
.iu_pc_icache_quiesce(iu_pc_icache_quiesce),
.lq_pc_ldq_quiesce(lq_pc_ldq_quiesce),
.lq_pc_stq_quiesce(lq_pc_stq_quiesce),
.lq_pc_pfetch_quiesce(lq_pc_pfetch_quiesce),
.mm_pc_tlb_req_quiesce(mm_pc_tlb_req_quiesce),
.mm_pc_tlb_ctl_quiesce(mm_pc_tlb_ctl_quiesce),
.mm_pc_htw_quiesce(mm_pc_htw_quiesce),
.mm_pc_inval_quiesce(mm_pc_inval_quiesce),
.iu_pc_fx0_credit_ok(iu_pc_fx0_credit_ok),
.iu_pc_fx1_credit_ok(iu_pc_fx1_credit_ok),
.iu_pc_axu0_credit_ok(iu_pc_axu0_credit_ok),
.iu_pc_axu1_credit_ok(iu_pc_axu1_credit_ok),
.iu_pc_lq_credit_ok(iu_pc_lq_credit_ok),
.iu_pc_sq_credit_ok(iu_pc_sq_credit_ok),
//RAMC+RAMD
.pc_iu_ram_instr(pc_iu_ram_instr),
.pc_iu_ram_instr_ext(pc_iu_ram_instr_ext),
.pc_iu_ram_active(pc_iu_ram_active),
.pc_iu_ram_execute(pc_iu_ram_execute),
.iu_pc_ram_done(iu_pc_ram_done),
.iu_pc_ram_interrupt(iu_pc_ram_interrupt),
.iu_pc_ram_unsupported(iu_pc_ram_unsupported),
.pc_xu_ram_active(pc_xu_ram_active),
.xu_pc_ram_data_val(xu_pc_ram_data_val),
.xu_pc_ram_data(xu_pc_ram_data),
.pc_fu_ram_active(pc_fu_ram_active),
.fu_pc_ram_data_val(fu_pc_ram_data_val),
.fu_pc_ram_data(fu_pc_ram_data),
.pc_lq_ram_active(pc_lq_ram_active),
.lq_pc_ram_data_val(lq_pc_ram_data_val),
.lq_pc_ram_data(lq_pc_ram_data),
.pc_xu_msrovride_enab(pc_xu_msrovride_enab),
.pc_xu_msrovride_pr(pc_xu_msrovride_pr),
.pc_xu_msrovride_gs(pc_xu_msrovride_gs),
.pc_xu_msrovride_de(pc_xu_msrovride_de),
.pc_iu_ram_force_cmplt(pc_iu_ram_force_cmplt),
.pc_iu_ram_flush_thread(pc_iu_ram_flush_thread),
.rg_rg_load_sramd(rg_rg_load_sramd),
.rg_rg_sramd_din(rg_rg_sramd_din),
//THRCTL + PCCR0 Registers
.ac_an_pm_thread_running(ac_an_pm_thread_running),
.pc_iu_stop(pc_iu_stop),
.pc_iu_step(pc_iu_step),
.pc_iu_dbg_action(pc_iu_dbg_action),
.pc_iu_spr_dbcr0_edm(pc_iu_spr_dbcr0_edm),
.pc_xu_spr_dbcr0_edm(pc_xu_spr_dbcr0_edm),
.xu_pc_running(xu_pc_running),
.iu_pc_stop_dbg_event(iu_pc_stop_dbg_event),
.xu_pc_stop_dnh_instr(xu_pc_stop_dnh_instr),
.iu_pc_step_done(iu_pc_step_done),
.an_ac_pm_thread_stop(an_ac_pm_thread_stop),
.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
.pc_iu_pm_fetch_halt(pc_iu_pm_fetch_halt),
.ct_rg_power_managed(ct_rg_power_managed),
.ct_rg_hold_during_init(ct_rg_hold_during_init),
.an_ac_debug_stop(an_ac_debug_stop),
.pc_xu_extirpts_dis_on_stop(pc_xu_extirpts_dis_on_stop),
.pc_xu_timebase_dis_on_stop(pc_xu_timebase_dis_on_stop),
.pc_xu_decrem_dis_on_stop(pc_xu_decrem_dis_on_stop),
.rg_ct_dis_pwr_savings(rg_ct_dis_pwr_savings),
//Debug Registers
.sp_rg_trace_bus_enable(sp_rg_trace_bus_enable),
.rg_db_trace_bus_enable(rg_db_trace_bus_enable),
.pc_iu_trace_bus_enable(pc_iu_trace_bus_enable),
.pc_fu_trace_bus_enable(pc_fu_trace_bus_enable),
.pc_rv_trace_bus_enable(pc_rv_trace_bus_enable),
.pc_mm_trace_bus_enable(pc_mm_trace_bus_enable),
.pc_xu_trace_bus_enable(pc_xu_trace_bus_enable),
.pc_lq_trace_bus_enable(pc_lq_trace_bus_enable),
.rg_db_debug_mux_ctrls(rg_db_debug_mux_ctrls),
.pc_iu_debug_mux1_ctrls(pc_iu_debug_mux1_ctrls),
.pc_iu_debug_mux2_ctrls(pc_iu_debug_mux2_ctrls),
.pc_fu_debug_mux_ctrls(pc_fu_debug_mux_ctrls),
.pc_rv_debug_mux_ctrls(pc_rv_debug_mux_ctrls),
.pc_mm_debug_mux_ctrls(pc_mm_debug_mux_ctrls),
.pc_xu_debug_mux_ctrls(pc_xu_debug_mux_ctrls),
.pc_lq_debug_mux1_ctrls(pc_lq_debug_mux1_ctrls),
.pc_lq_debug_mux2_ctrls(pc_lq_debug_mux2_ctrls),
//Trace Signals
.dbg_scom(rg_db_dbg_scom),
.dbg_thrctls(rg_db_dbg_thrctls),
.dbg_ram(rg_db_dbg_ram),
.dbg_fir0_err(rg_db_dbg_fir0_err),
.dbg_fir1_err(rg_db_dbg_fir1_err),
.dbg_fir2_err(rg_db_dbg_fir2_err),
.dbg_fir_misc(rg_db_dbg_fir_misc)
);
pcq_ctrl pcq_ctrl(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.scan_dis_dc_b(an_ac_scan_dis_dc_b),
.lcb_clkoff_dc_b(clkoff_dc_b),
.lcb_mpw1_dc_b(mpw1_dc_b[1]),
.lcb_mpw2_dc_b(mpw2_dc_b),
.lcb_delay_lclkr_dc(delay_lclkr_dc[1]),
.lcb_act_dis_dc(act_dis_dc),
.pc_pc_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0),
.pc_pc_sg_0(pc_pc_sg_0),
.func_scan_in(func_scan_in[1]),
.func_scan_out(ct_db_func_scan_out),
//Stop/Start/Reset
.pc_lq_init_reset(pc_lq_init_reset),
.pc_iu_init_reset(pc_iu_init_reset),
.ct_rg_hold_during_init(ct_rg_hold_during_init),
//Power Management
.ct_rg_power_managed(ct_rg_power_managed),
.ac_an_power_managed(ac_an_power_managed),
.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),
.pc_xu_pm_hold_thread(pc_xu_pm_hold_thread),
.ct_ck_pm_ccflush_disable(ct_ck_pm_ccflush_disable),
.ct_ck_pm_raise_tholds(ct_ck_pm_raise_tholds),
.rg_ct_dis_pwr_savings(rg_ct_dis_pwr_savings),
.xu_pc_spr_ccr0_pme(xu_pc_spr_ccr0_pme),
.xu_pc_spr_ccr0_we(xu_pc_spr_ccr0_we),
//Trace/Trigger Signals
.dbg_ctrls(ct_db_dbg_ctrls)
);
pcq_dbg pcq_dbg(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.scan_dis_dc_b(an_ac_scan_dis_dc_b),
.lcb_clkoff_dc_b(clkoff_dc_b),
.lcb_mpw1_dc_b(mpw1_dc_b[2]),
.lcb_mpw2_dc_b(mpw2_dc_b),
.lcb_delay_lclkr_dc(delay_lclkr_dc[2]),
.lcb_act_dis_dc(act_dis_dc),
.pc_pc_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0),
.pc_pc_sg_0(pc_pc_sg_0),
.func_scan_in(ct_db_func_scan_out),
.func_scan_out(db_ss_func_scan_out),
//Trace/Trigger Bus
.debug_bus_out(debug_bus_out),
.debug_bus_in(debug_bus_in),
.rg_db_trace_bus_enable(rg_db_trace_bus_enable),
.rg_db_debug_mux_ctrls(rg_db_debug_mux_ctrls),
.coretrace_ctrls_in(coretrace_ctrls_in),
.coretrace_ctrls_out(coretrace_ctrls_out),
//PC Unit internal debug signals
.rg_db_dbg_scom(rg_db_dbg_scom),
.rg_db_dbg_thrctls(rg_db_dbg_thrctls),
.rg_db_dbg_ram(rg_db_dbg_ram),
.rg_db_dbg_fir0_err(rg_db_dbg_fir0_err),
.rg_db_dbg_fir1_err(rg_db_dbg_fir1_err),
.rg_db_dbg_fir2_err(rg_db_dbg_fir2_err),
.rg_db_dbg_fir_misc(rg_db_dbg_fir_misc),
.ct_db_dbg_ctrls(ct_db_dbg_ctrls),
.rg_db_dbg_spr(rg_db_dbg_spr)
);
pcq_spr pcq_spr(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.scan_dis_dc_b(an_ac_scan_dis_dc_b),
.lcb_clkoff_dc_b(clkoff_dc_b),
.lcb_mpw1_dc_b(mpw1_dc_b[0]),
.lcb_mpw2_dc_b(mpw2_dc_b),
.lcb_delay_lclkr_dc(delay_lclkr_dc[0]),
.lcb_act_dis_dc(act_dis_dc),
.pc_pc_func_sl_thold_0(pc_pc_func_sl_thold_0),
.pc_pc_sg_0(pc_pc_sg_0),
.func_scan_in(db_ss_func_scan_out),
.func_scan_out(func_scan_out[1]),
// slowSPR Interface
.slowspr_val_in(slowspr_val_in),
.slowspr_rw_in(slowspr_rw_in),
.slowspr_etid_in(slowspr_etid_in),
.slowspr_addr_in(slowspr_addr_in),
.slowspr_data_in(slowspr_data_in[64 - `GPR_WIDTH:63]),
.slowspr_done_in(slowspr_done_in),
.cp_flush(cp_flush),
.slowspr_val_out(slowspr_val_out),
.slowspr_rw_out(slowspr_rw_out),
.slowspr_etid_out(slowspr_etid_out),
.slowspr_addr_out(slowspr_addr_out),
.slowspr_data_out(slowspr_data_out[64 - `GPR_WIDTH:63]),
.slowspr_done_out(slowspr_done_out),
// Event Mux Controls
.pc_rv_event_mux_ctrls(pc_rv_event_mux_ctrls),
// CESR1 Controls
.pc_iu_event_bus_enable(pc_iu_event_bus_enable),
.pc_fu_event_bus_enable(pc_fu_event_bus_enable),
.pc_rv_event_bus_enable(pc_rv_event_bus_enable),
.pc_mm_event_bus_enable(pc_mm_event_bus_enable),
.pc_xu_event_bus_enable(pc_xu_event_bus_enable),
.pc_lq_event_bus_enable(pc_lq_event_bus_enable),
.pc_iu_event_count_mode(pc_iu_event_count_mode),
.pc_fu_event_count_mode(pc_fu_event_count_mode),
.pc_rv_event_count_mode(pc_rv_event_count_mode),
.pc_mm_event_count_mode(pc_mm_event_count_mode),
.pc_xu_event_count_mode(pc_xu_event_count_mode),
.pc_lq_event_count_mode(pc_lq_event_count_mode),
.sp_rg_trace_bus_enable(sp_rg_trace_bus_enable),
.pc_iu_instr_trace_mode(pc_iu_instr_trace_mode),
.pc_iu_instr_trace_tid(pc_iu_instr_trace_tid),
.pc_lq_instr_trace_mode(pc_lq_instr_trace_mode),
.pc_lq_instr_trace_tid(pc_lq_instr_trace_tid),
.pc_xu_instr_trace_mode(pc_xu_instr_trace_mode),
.pc_xu_instr_trace_tid(pc_xu_instr_trace_tid),
.pc_lq_event_bus_seldbghi(pc_lq_event_bus_seldbghi),
.pc_lq_event_bus_seldbglo(pc_lq_event_bus_seldbglo),
.xu_pc_perfmon_alert(xu_pc_perfmon_alert),
.pc_xu_spr_cesr1_pmae(pc_xu_spr_cesr1_pmae),
// SRAMD data and load pulse
.rg_rg_load_sramd(rg_rg_load_sramd),
.rg_rg_sramd_din(rg_rg_sramd_din),
// Debug
.dbg_spr(rg_db_dbg_spr)
);
pcq_clks pcq_clks(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.rtim_sl_thold_7(an_ac_rtim_sl_thold_7),
.func_sl_thold_7(an_ac_func_sl_thold_7),
.func_nsl_thold_7(an_ac_func_nsl_thold_7),
.ary_nsl_thold_7(an_ac_ary_nsl_thold_7),
.sg_7(an_ac_sg_7),
.fce_7(an_ac_fce_7),
.gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
.gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
.ccflush_dc(an_ac_ccflush_dc),
.ccenable_dc(an_ac_ccenable_dc),
.scan_type_dc(an_ac_scan_type_dc),
.lbist_en_dc(an_ac_lbist_en_dc),
.lbist_ip_dc(an_ac_lbist_ip_dc),
.rg_ck_fast_xstop(rg_ck_fast_xstop),
.ct_ck_pm_ccflush_disable(ct_ck_pm_ccflush_disable),
.ct_ck_pm_raise_tholds(ct_ck_pm_raise_tholds),
// --Thold outputs to the units
.pc_pc_ccflush_out_dc(pc_rp_ccflush_out_dc),
.pc_pc_gptr_sl_thold_4(pc_rp_gptr_sl_thold_4),
.pc_pc_time_sl_thold_4(pc_rp_time_sl_thold_4),
.pc_pc_repr_sl_thold_4(pc_rp_repr_sl_thold_4),
.pc_pc_abst_sl_thold_4(pc_rp_abst_sl_thold_4),
.pc_pc_abst_slp_sl_thold_4(pc_rp_abst_slp_sl_thold_4),
.pc_pc_regf_sl_thold_4(pc_rp_regf_sl_thold_4),
.pc_pc_regf_slp_sl_thold_4(pc_rp_regf_slp_sl_thold_4),
.pc_pc_func_sl_thold_4(pc_rp_func_sl_thold_4),
.pc_pc_func_slp_sl_thold_4(pc_rp_func_slp_sl_thold_4),
.pc_pc_cfg_sl_thold_4(pc_rp_cfg_sl_thold_4),
.pc_pc_cfg_slp_sl_thold_4(pc_rp_cfg_slp_sl_thold_4),
.pc_pc_func_nsl_thold_4(pc_rp_func_nsl_thold_4),
.pc_pc_func_slp_nsl_thold_4(pc_rp_func_slp_nsl_thold_4),
.pc_pc_ary_nsl_thold_4(pc_rp_ary_nsl_thold_4),
.pc_pc_ary_slp_nsl_thold_4(pc_rp_ary_slp_nsl_thold_4),
.pc_pc_rtim_sl_thold_4(pc_rp_rtim_sl_thold_4),
.pc_pc_sg_4(pc_rp_sg_4),
.pc_pc_fce_4(pc_rp_fce_4),
.pc_fu_ccflush_dc(pc_fu_ccflush_dc),
.pc_fu_gptr_sl_thold_3(pc_fu_gptr_sl_thold_3),
.pc_fu_time_sl_thold_3(pc_fu_time_sl_thold_3),
.pc_fu_repr_sl_thold_3(pc_fu_repr_sl_thold_3),
.pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3),
.pc_fu_abst_slp_sl_thold_3(pc_fu_abst_slp_sl_thold_3),
.pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3),
.pc_fu_func_slp_sl_thold_3(pc_fu_func_slp_sl_thold_3),
.pc_fu_cfg_sl_thold_3(pc_fu_cfg_sl_thold_3),
.pc_fu_cfg_slp_sl_thold_3(pc_fu_cfg_slp_sl_thold_3),
.pc_fu_func_nsl_thold_3(pc_fu_func_nsl_thold_3),
.pc_fu_func_slp_nsl_thold_3(pc_fu_func_slp_nsl_thold_3),
.pc_fu_ary_nsl_thold_3(pc_fu_ary_nsl_thold_3),
.pc_fu_ary_slp_nsl_thold_3(pc_fu_ary_slp_nsl_thold_3),
.pc_fu_sg_3(pc_fu_sg_3),
.pc_fu_fce_3(pc_fu_fce_3),
.pc_pc_ccflush_dc(pc_pc_ccflush_dc),
.pc_pc_gptr_sl_thold_0(pc_pc_gptr_sl_thold_0),
.pc_pc_func_sl_thold_0(pc_pc_func_sl_thold_0),
.pc_pc_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0),
.pc_pc_cfg_sl_thold_0(pc_pc_cfg_sl_thold_0),
.pc_pc_cfg_slp_sl_thold_0(pc_pc_cfg_slp_sl_thold_0),
.pc_pc_sg_0(pc_pc_sg_0)
);
//=====================================================================
// LCBCNTL Macro
//=====================================================================
tri_lcbcntl_mac lcbctrl(
.vdd(vdd),
.gnd(gnd),
.sg(pc_pc_sg_0),
.nclk(nclk),
.scan_in(gptr_scan_in),
.scan_diag_dc(an_ac_scan_diag_dc),
.thold(pc_pc_gptr_sl_thold_0),
.clkoff_dc_b(clkoff_dc_b),
.delay_lclkr_dc(delay_lclkr_dc[0:4]),
.act_dis_dc(),
.d_mode_dc(d_mode_dc),
.mpw1_dc_b(mpw1_dc_b[0:4]),
.mpw2_dc_b(mpw2_dc_b),
.scan_out(lcbctrl_gptr_scan_out)
);
// Forcing act_dis pin on all tri_lcbor components to 0.
// Using logic signal connected to LCB ACT pin to control if latch held or updated.
assign act_dis_dc = 1'b0;
endmodule |
module fu_hc16pp(
x,
y,
ci0,
ci0_b,
ci1,
ci1_b,
s0,
s1,
g16,
t16
);
input [0:15] x;
input [0:15] y;
input ci0;
input ci0_b;
input ci1;
input ci1_b;
output [0:15] s0;
output [0:15] s1;
output g16;
output t16;
wire [0:15] g01_b;
wire [0:15] t01_b;
wire [0:15] p01_b;
wire [0:15] p01;
wire [0:7] g01od;
wire [0:7] t01od;
wire [0:7] g02ev;
wire [0:7] t02ev;
wire [1:7] g02ev_b;
wire [1:7] t02ev_b;
wire [1:7] g04ev;
wire [1:7] t04ev;
wire [1:7] g08ev_b;
wire [1:7] t08ev_b;
wire [1:7] g16ev;
wire [1:7] t16ev;
wire [1:15] c0_b;
wire [1:15] c1_b;
wire [0:15] s0_raw;
wire [0:15] s1_raw;
wire [0:15] s0_x_b;
wire [0:15] s0_y_b;
wire [0:15] s1_x_b;
wire [0:15] s1_y_b;
wire glb_g04_e01_b; //new // rep glb
wire glb_g04_e23_b;
wire glb_g04_e45_b;
wire glb_g04_e67_b;
wire glb_t04_e01_b; //new // rep glb
wire glb_t04_e23_b;
wire glb_t04_e45_b;
wire glb_t04_e67_b;
wire glb_g08_e03; //new // rep glb
wire glb_g08_e47;
wire glb_t08_e03;
wire glb_t08_e47;
wire glb_g16_e07_b; //new // rep glb
wire glb_t16_e07_b;
////#####################################
////## group 1
////#####################################
// g01_b(0 to 15) <= not( x(0 to 15) and y(0 to 15) ); -- critical
// t01_b(0 to 15) <= not( x(0 to 15) or y(0 to 15) ); -- critical
// p01_b(0 to 15) <= not( x(0 to 15) xor y(0 to 15) ); -- not critical
assign g01_b[0] = (~(x[0] & y[0])); //critical
assign g01_b[1] = (~(x[1] & y[1])); //critical
assign g01_b[2] = (~(x[2] & y[2])); //critical
assign g01_b[3] = (~(x[3] & y[3])); //critical
assign g01_b[4] = (~(x[4] & y[4])); //critical
assign g01_b[5] = (~(x[5] & y[5])); //critical
assign g01_b[6] = (~(x[6] & y[6])); //critical
assign g01_b[7] = (~(x[7] & y[7])); //critical
assign g01_b[8] = (~(x[8] & y[8])); //critical
assign g01_b[9] = (~(x[9] & y[9])); //critical
assign g01_b[10] = (~(x[10] & y[10])); //critical
assign g01_b[11] = (~(x[11] & y[11])); //critical
assign g01_b[12] = (~(x[12] & y[12])); //critical
assign g01_b[13] = (~(x[13] & y[13])); //critical
assign g01_b[14] = (~(x[14] & y[14])); //critical
assign g01_b[15] = (~(x[15] & y[15])); //critical
assign t01_b[0] = (~(x[0] | y[0])); //critical
assign t01_b[1] = (~(x[1] | y[1])); //critical
assign t01_b[2] = (~(x[2] | y[2])); //critical
assign t01_b[3] = (~(x[3] | y[3])); //critical
assign t01_b[4] = (~(x[4] | y[4])); //critical
assign t01_b[5] = (~(x[5] | y[5])); //critical
assign t01_b[6] = (~(x[6] | y[6])); //critical
assign t01_b[7] = (~(x[7] | y[7])); //critical
assign t01_b[8] = (~(x[8] | y[8])); //critical
assign t01_b[9] = (~(x[9] | y[9])); //critical
assign t01_b[10] = (~(x[10] | y[10])); //critical
assign t01_b[11] = (~(x[11] | y[11])); //critical
assign t01_b[12] = (~(x[12] | y[12])); //critical
assign t01_b[13] = (~(x[13] | y[13])); //critical
assign t01_b[14] = (~(x[14] | y[14])); //critical
assign t01_b[15] = (~(x[15] | y[15])); //critical
assign p01[0] = (x[0] ^ y[0]); //not critical
assign p01[1] = (x[1] ^ y[1]); //not critical
assign p01[2] = (x[2] ^ y[2]); //not critical
assign p01[3] = (x[3] ^ y[3]); //not critical
assign p01[4] = (x[4] ^ y[4]); //not critical
assign p01[5] = (x[5] ^ y[5]); //not critical
assign p01[6] = (x[6] ^ y[6]); //not critical
assign p01[7] = (x[7] ^ y[7]); //not critical
assign p01[8] = (x[8] ^ y[8]); //not critical
assign p01[9] = (x[9] ^ y[9]); //not critical
assign p01[10] = (x[10] ^ y[10]); //not critical
assign p01[11] = (x[11] ^ y[11]); //not critical
assign p01[12] = (x[12] ^ y[12]); //not critical
assign p01[13] = (x[13] ^ y[13]); //not critical
assign p01[14] = (x[14] ^ y[14]); //not critical
assign p01[15] = (x[15] ^ y[15]); //not critical
assign p01_b[0] = (~(p01[0])); //not critical
assign p01_b[1] = (~(p01[1])); //not critical
assign p01_b[2] = (~(p01[2])); //not critical
assign p01_b[3] = (~(p01[3])); //not critical
assign p01_b[4] = (~(p01[4])); //not critical
assign p01_b[5] = (~(p01[5])); //not critical
assign p01_b[6] = (~(p01[6])); //not critical
assign p01_b[7] = (~(p01[7])); //not critical
assign p01_b[8] = (~(p01[8])); //not critical
assign p01_b[9] = (~(p01[9])); //not critical
assign p01_b[10] = (~(p01[10])); //not critical
assign p01_b[11] = (~(p01[11])); //not critical
assign p01_b[12] = (~(p01[12])); //not critical
assign p01_b[13] = (~(p01[13])); //not critical
assign p01_b[14] = (~(p01[14])); //not critical
assign p01_b[15] = (~(p01[15])); //not critical
assign g01od[0] = (~g01_b[1]);
assign g01od[1] = (~g01_b[3]);
assign g01od[2] = (~g01_b[5]);
assign g01od[3] = (~g01_b[7]);
assign g01od[4] = (~g01_b[9]);
assign g01od[5] = (~g01_b[11]);
assign g01od[6] = (~g01_b[13]);
assign g01od[7] = (~g01_b[15]);
assign t01od[0] = (~t01_b[1]);
assign t01od[1] = (~t01_b[3]);
assign t01od[2] = (~t01_b[5]);
assign t01od[3] = (~t01_b[7]);
assign t01od[4] = (~t01_b[9]);
assign t01od[5] = (~t01_b[11]);
assign t01od[6] = (~t01_b[13]);
assign t01od[7] = (~t01_b[15]);
////#####################################
////## group 2 // local and global (shared)
////#####################################
assign g02ev[7] = (~((t01_b[14] | g01_b[15]) & g01_b[14])); //final
assign g02ev[6] = (~((t01_b[12] | g01_b[13]) & g01_b[12]));
assign g02ev[5] = (~((t01_b[10] | g01_b[11]) & g01_b[10]));
assign g02ev[4] = (~((t01_b[8] | g01_b[9]) & g01_b[8]));
assign g02ev[3] = (~((t01_b[6] | g01_b[7]) & g01_b[6]));
assign g02ev[2] = (~((t01_b[4] | g01_b[5]) & g01_b[4]));
assign g02ev[1] = (~((t01_b[2] | g01_b[3]) & g01_b[2]));
assign g02ev[0] = (~((t01_b[0] | g01_b[1]) & g01_b[0]));
assign t02ev[7] = (~((t01_b[14] | t01_b[15]) & g01_b[14])); //final
assign t02ev[6] = (~(t01_b[12] | t01_b[13]));
assign t02ev[5] = (~(t01_b[10] | t01_b[11]));
assign t02ev[4] = (~(t01_b[8] | t01_b[9]));
assign t02ev[3] = (~(t01_b[6] | t01_b[7]));
assign t02ev[2] = (~(t01_b[4] | t01_b[5]));
assign t02ev[1] = (~(t01_b[2] | t01_b[3]));
assign t02ev[0] = (~(t01_b[0] | t01_b[1]));
assign g02ev_b[7] = (~(g02ev[7])); //new
assign g02ev_b[6] = (~(g02ev[6])); //new
assign g02ev_b[5] = (~(g02ev[5])); //new
assign g02ev_b[4] = (~(g02ev[4])); //new
assign g02ev_b[3] = (~(g02ev[3])); //new
assign g02ev_b[2] = (~(g02ev[2])); //new
assign g02ev_b[1] = (~(g02ev[1])); //new
assign t02ev_b[7] = (~(t02ev[7])); //new
assign t02ev_b[6] = (~(t02ev[6])); //new
assign t02ev_b[5] = (~(t02ev[5])); //new
assign t02ev_b[4] = (~(t02ev[4])); //new
assign t02ev_b[3] = (~(t02ev[3])); //new
assign t02ev_b[2] = (~(t02ev[2])); //new
assign t02ev_b[1] = (~(t02ev[1])); //new
////#####################################
////## replicating for global chain
////#####################################
assign glb_g04_e01_b = (~(g02ev[0] | (t02ev[0] & g02ev[1])));
assign glb_g04_e23_b = (~(g02ev[2] | (t02ev[2] & g02ev[3])));
assign glb_g04_e45_b = (~(g02ev[4] | (t02ev[4] & g02ev[5])));
assign glb_g04_e67_b = (~(g02ev[6] | (t02ev[6] & g02ev[7])));
assign glb_t04_e01_b = (~(t02ev[0] & t02ev[1]));
assign glb_t04_e23_b = (~(t02ev[2] & t02ev[3]));
assign glb_t04_e45_b = (~(t02ev[4] & t02ev[5]));
assign glb_t04_e67_b = (~(g02ev[6] | (t02ev[6] & t02ev[7])));
assign glb_g08_e03 = (~(glb_g04_e01_b & (glb_t04_e01_b | glb_g04_e23_b)));
assign glb_g08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_g04_e67_b)));
assign glb_t08_e03 = (~(glb_t04_e01_b | glb_t04_e23_b));
assign glb_t08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_t04_e67_b)));
assign glb_g16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_g08_e47)));
assign glb_t16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_t08_e47)));
assign g16 = (~(glb_g16_e07_b)); //output
assign t16 = (~(glb_t16_e07_b)); //output
////#####################################
////## group 4 // delayed for local chain ... reverse phase
////#####################################
assign g04ev[7] = (~(g02ev_b[7]));
assign g04ev[6] = (~(g02ev_b[6] & (t02ev_b[6] | g02ev_b[7]))); //final
assign g04ev[5] = (~(g02ev_b[5] & (t02ev_b[5] | g02ev_b[6])));
assign g04ev[4] = (~(g02ev_b[4] & (t02ev_b[4] | g02ev_b[5])));
assign g04ev[3] = (~(g02ev_b[3] & (t02ev_b[3] | g02ev_b[4])));
assign g04ev[2] = (~(g02ev_b[2] & (t02ev_b[2] | g02ev_b[3])));
assign g04ev[1] = (~(g02ev_b[1] & (t02ev_b[1] | g02ev_b[2])));
assign t04ev[7] = (~(t02ev_b[7]));
assign t04ev[6] = (~(g02ev_b[6] & (t02ev_b[6] | t02ev_b[7]))); //final
assign t04ev[5] = (~(t02ev_b[5] | t02ev_b[6]));
assign t04ev[4] = (~(t02ev_b[4] | t02ev_b[5]));
assign t04ev[3] = (~(t02ev_b[3] | t02ev_b[4]));
assign t04ev[2] = (~(t02ev_b[2] | t02ev_b[3]));
assign t04ev[1] = (~(t02ev_b[1] | t02ev_b[2]));
////#####################################
////## group 8
////#####################################
assign g08ev_b[7] = (~(g04ev[7]));
assign g08ev_b[6] = (~(g04ev[6]));
assign g08ev_b[5] = (~(g04ev[5] | (t04ev[5] & g04ev[7]))); //final
assign g08ev_b[4] = (~(g04ev[4] | (t04ev[4] & g04ev[6]))); //final
assign g08ev_b[3] = (~(g04ev[3] | (t04ev[3] & g04ev[5])));
assign g08ev_b[2] = (~(g04ev[2] | (t04ev[2] & g04ev[4])));
assign g08ev_b[1] = (~(g04ev[1] | (t04ev[1] & g04ev[3])));
assign t08ev_b[7] = (~(t04ev[7]));
assign t08ev_b[6] = (~(t04ev[6]));
assign t08ev_b[5] = (~(g04ev[5] | (t04ev[5] & t04ev[7]))); //final
assign t08ev_b[4] = (~(g04ev[4] | (t04ev[4] & t04ev[6]))); //final
assign t08ev_b[3] = (~(t04ev[3] & t04ev[5]));
assign t08ev_b[2] = (~(t04ev[2] & t04ev[4]));
assign t08ev_b[1] = (~(t04ev[1] & t04ev[3]));
////#####################################
////## group 16
////#####################################
assign g16ev[7] = (~(g08ev_b[7]));
assign g16ev[6] = (~(g08ev_b[6]));
assign g16ev[5] = (~(g08ev_b[5]));
assign g16ev[4] = (~(g08ev_b[4]));
assign g16ev[3] = (~(g08ev_b[3] & (t08ev_b[3] | g08ev_b[7]))); //final
assign g16ev[2] = (~(g08ev_b[2] & (t08ev_b[2] | g08ev_b[6]))); //final
assign g16ev[1] = (~(g08ev_b[1] & (t08ev_b[1] | g08ev_b[5]))); //final
assign t16ev[7] = (~(t08ev_b[7]));
assign t16ev[6] = (~(t08ev_b[6]));
assign t16ev[5] = (~(t08ev_b[5]));
assign t16ev[4] = (~(t08ev_b[4]));
assign t16ev[3] = (~(g08ev_b[3] & (t08ev_b[3] | t08ev_b[7]))); //final
assign t16ev[2] = (~(g08ev_b[2] & (t08ev_b[2] | t08ev_b[6]))); //final
assign t16ev[1] = (~(g08ev_b[1] & (t08ev_b[1] | t08ev_b[5]))); //final
////#####################################
////## group 16 delayed
////#####################################
assign c0_b[14] = (~(g16ev[7]));
assign c0_b[12] = (~(g16ev[6]));
assign c0_b[10] = (~(g16ev[5]));
assign c0_b[8] = (~(g16ev[4]));
assign c0_b[6] = (~(g16ev[3]));
assign c0_b[4] = (~(g16ev[2]));
assign c0_b[2] = (~(g16ev[1]));
assign c1_b[14] = (~(t16ev[7]));
assign c1_b[12] = (~(t16ev[6]));
assign c1_b[10] = (~(t16ev[5]));
assign c1_b[8] = (~(t16ev[4]));
assign c1_b[6] = (~(t16ev[3]));
assign c1_b[4] = (~(t16ev[2]));
assign c1_b[2] = (~(t16ev[1]));
assign c0_b[15] = (~(g01od[7]));
assign c0_b[13] = (~((t01od[6] & g16ev[7]) | g01od[6]));
assign c0_b[11] = (~((t01od[5] & g16ev[6]) | g01od[5]));
assign c0_b[9] = (~((t01od[4] & g16ev[5]) | g01od[4]));
assign c0_b[7] = (~((t01od[3] & g16ev[4]) | g01od[3]));
assign c0_b[5] = (~((t01od[2] & g16ev[3]) | g01od[2]));
assign c0_b[3] = (~((t01od[1] & g16ev[2]) | g01od[1]));
assign c0_b[1] = (~((t01od[0] & g16ev[1]) | g01od[0]));
assign c1_b[15] = (~(t01od[7]));
assign c1_b[13] = (~((t01od[6] & t16ev[7]) | g01od[6]));
assign c1_b[11] = (~((t01od[5] & t16ev[6]) | g01od[5]));
assign c1_b[9] = (~((t01od[4] & t16ev[5]) | g01od[4]));
assign c1_b[7] = (~((t01od[3] & t16ev[4]) | g01od[3]));
assign c1_b[5] = (~((t01od[2] & t16ev[3]) | g01od[2]));
assign c1_b[3] = (~((t01od[1] & t16ev[2]) | g01od[1]));
assign c1_b[1] = (~((t01od[0] & t16ev[1]) | g01od[0]));
////#####################################
////## sum before select
////#####################################
assign s0_raw[0] = (p01_b[0] ^ c0_b[1]);
assign s0_raw[1] = (p01_b[1] ^ c0_b[2]);
assign s0_raw[2] = (p01_b[2] ^ c0_b[3]);
assign s0_raw[3] = (p01_b[3] ^ c0_b[4]);
assign s0_raw[4] = (p01_b[4] ^ c0_b[5]);
assign s0_raw[5] = (p01_b[5] ^ c0_b[6]);
assign s0_raw[6] = (p01_b[6] ^ c0_b[7]);
assign s0_raw[7] = (p01_b[7] ^ c0_b[8]);
assign s0_raw[8] = (p01_b[8] ^ c0_b[9]);
assign s0_raw[9] = (p01_b[9] ^ c0_b[10]);
assign s0_raw[10] = (p01_b[10] ^ c0_b[11]);
assign s0_raw[11] = (p01_b[11] ^ c0_b[12]);
assign s0_raw[12] = (p01_b[12] ^ c0_b[13]);
assign s0_raw[13] = (p01_b[13] ^ c0_b[14]);
assign s0_raw[14] = (p01_b[14] ^ c0_b[15]);
assign s0_raw[15] = (~p01_b[15]);
assign s1_raw[0] = (p01_b[0] ^ c1_b[1]);
assign s1_raw[1] = (p01_b[1] ^ c1_b[2]);
assign s1_raw[2] = (p01_b[2] ^ c1_b[3]);
assign s1_raw[3] = (p01_b[3] ^ c1_b[4]);
assign s1_raw[4] = (p01_b[4] ^ c1_b[5]);
assign s1_raw[5] = (p01_b[5] ^ c1_b[6]);
assign s1_raw[6] = (p01_b[6] ^ c1_b[7]);
assign s1_raw[7] = (p01_b[7] ^ c1_b[8]);
assign s1_raw[8] = (p01_b[8] ^ c1_b[9]);
assign s1_raw[9] = (p01_b[9] ^ c1_b[10]);
assign s1_raw[10] = (p01_b[10] ^ c1_b[11]);
assign s1_raw[11] = (p01_b[11] ^ c1_b[12]);
assign s1_raw[12] = (p01_b[12] ^ c1_b[13]);
assign s1_raw[13] = (p01_b[13] ^ c1_b[14]);
assign s1_raw[14] = (p01_b[14] ^ c1_b[15]);
assign s1_raw[15] = (~s0_raw[15]);
////#####################################
////## sum after select
////#####################################
assign s0_x_b[0] = (~(s0_raw[0] & ci0_b));
assign s0_y_b[0] = (~(s1_raw[0] & ci0));
assign s1_x_b[0] = (~(s0_raw[0] & ci1_b));
assign s1_y_b[0] = (~(s1_raw[0] & ci1));
assign s0[0] = (~(s0_x_b[0] & s0_y_b[0]));
assign s1[0] = (~(s1_x_b[0] & s1_y_b[0]));
assign s0_x_b[1] = (~(s0_raw[1] & ci0_b));
assign s0_y_b[1] = (~(s1_raw[1] & ci0));
assign s1_x_b[1] = (~(s0_raw[1] & ci1_b));
assign s1_y_b[1] = (~(s1_raw[1] & ci1));
assign s0[1] = (~(s0_x_b[1] & s0_y_b[1]));
assign s1[1] = (~(s1_x_b[1] & s1_y_b[1]));
assign s0_x_b[2] = (~(s0_raw[2] & ci0_b));
assign s0_y_b[2] = (~(s1_raw[2] & ci0));
assign s1_x_b[2] = (~(s0_raw[2] & ci1_b));
assign s1_y_b[2] = (~(s1_raw[2] & ci1));
assign s0[2] = (~(s0_x_b[2] & s0_y_b[2]));
assign s1[2] = (~(s1_x_b[2] & s1_y_b[2]));
assign s0_x_b[3] = (~(s0_raw[3] & ci0_b));
assign s0_y_b[3] = (~(s1_raw[3] & ci0));
assign s1_x_b[3] = (~(s0_raw[3] & ci1_b));
assign s1_y_b[3] = (~(s1_raw[3] & ci1));
assign s0[3] = (~(s0_x_b[3] & s0_y_b[3]));
assign s1[3] = (~(s1_x_b[3] & s1_y_b[3]));
assign s0_x_b[4] = (~(s0_raw[4] & ci0_b));
assign s0_y_b[4] = (~(s1_raw[4] & ci0));
assign s1_x_b[4] = (~(s0_raw[4] & ci1_b));
assign s1_y_b[4] = (~(s1_raw[4] & ci1));
assign s0[4] = (~(s0_x_b[4] & s0_y_b[4]));
assign s1[4] = (~(s1_x_b[4] & s1_y_b[4]));
assign s0_x_b[5] = (~(s0_raw[5] & ci0_b));
assign s0_y_b[5] = (~(s1_raw[5] & ci0));
assign s1_x_b[5] = (~(s0_raw[5] & ci1_b));
assign s1_y_b[5] = (~(s1_raw[5] & ci1));
assign s0[5] = (~(s0_x_b[5] & s0_y_b[5]));
assign s1[5] = (~(s1_x_b[5] & s1_y_b[5]));
assign s0_x_b[6] = (~(s0_raw[6] & ci0_b));
assign s0_y_b[6] = (~(s1_raw[6] & ci0));
assign s1_x_b[6] = (~(s0_raw[6] & ci1_b));
assign s1_y_b[6] = (~(s1_raw[6] & ci1));
assign s0[6] = (~(s0_x_b[6] & s0_y_b[6]));
assign s1[6] = (~(s1_x_b[6] & s1_y_b[6]));
assign s0_x_b[7] = (~(s0_raw[7] & ci0_b));
assign s0_y_b[7] = (~(s1_raw[7] & ci0));
assign s1_x_b[7] = (~(s0_raw[7] & ci1_b));
assign s1_y_b[7] = (~(s1_raw[7] & ci1));
assign s0[7] = (~(s0_x_b[7] & s0_y_b[7]));
assign s1[7] = (~(s1_x_b[7] & s1_y_b[7]));
assign s0_x_b[8] = (~(s0_raw[8] & ci0_b));
assign s0_y_b[8] = (~(s1_raw[8] & ci0));
assign s1_x_b[8] = (~(s0_raw[8] & ci1_b));
assign s1_y_b[8] = (~(s1_raw[8] & ci1));
assign s0[8] = (~(s0_x_b[8] & s0_y_b[8]));
assign s1[8] = (~(s1_x_b[8] & s1_y_b[8]));
assign s0_x_b[9] = (~(s0_raw[9] & ci0_b));
assign s0_y_b[9] = (~(s1_raw[9] & ci0));
assign s1_x_b[9] = (~(s0_raw[9] & ci1_b));
assign s1_y_b[9] = (~(s1_raw[9] & ci1));
assign s0[9] = (~(s0_x_b[9] & s0_y_b[9]));
assign s1[9] = (~(s1_x_b[9] & s1_y_b[9]));
assign s0_x_b[10] = (~(s0_raw[10] & ci0_b));
assign s0_y_b[10] = (~(s1_raw[10] & ci0));
assign s1_x_b[10] = (~(s0_raw[10] & ci1_b));
assign s1_y_b[10] = (~(s1_raw[10] & ci1));
assign s0[10] = (~(s0_x_b[10] & s0_y_b[10]));
assign s1[10] = (~(s1_x_b[10] & s1_y_b[10]));
assign s0_x_b[11] = (~(s0_raw[11] & ci0_b));
assign s0_y_b[11] = (~(s1_raw[11] & ci0));
assign s1_x_b[11] = (~(s0_raw[11] & ci1_b));
assign s1_y_b[11] = (~(s1_raw[11] & ci1));
assign s0[11] = (~(s0_x_b[11] & s0_y_b[11]));
assign s1[11] = (~(s1_x_b[11] & s1_y_b[11]));
assign s0_x_b[12] = (~(s0_raw[12] & ci0_b));
assign s0_y_b[12] = (~(s1_raw[12] & ci0));
assign s1_x_b[12] = (~(s0_raw[12] & ci1_b));
assign s1_y_b[12] = (~(s1_raw[12] & ci1));
assign s0[12] = (~(s0_x_b[12] & s0_y_b[12]));
assign s1[12] = (~(s1_x_b[12] & s1_y_b[12]));
assign s0_x_b[13] = (~(s0_raw[13] & ci0_b));
assign s0_y_b[13] = (~(s1_raw[13] & ci0));
assign s1_x_b[13] = (~(s0_raw[13] & ci1_b));
assign s1_y_b[13] = (~(s1_raw[13] & ci1));
assign s0[13] = (~(s0_x_b[13] & s0_y_b[13]));
assign s1[13] = (~(s1_x_b[13] & s1_y_b[13]));
assign s0_x_b[14] = (~(s0_raw[14] & ci0_b));
assign s0_y_b[14] = (~(s1_raw[14] & ci0));
assign s1_x_b[14] = (~(s0_raw[14] & ci1_b));
assign s1_y_b[14] = (~(s1_raw[14] & ci1));
assign s0[14] = (~(s0_x_b[14] & s0_y_b[14]));
assign s1[14] = (~(s1_x_b[14] & s1_y_b[14]));
assign s0_x_b[15] = (~(s0_raw[15] & ci0_b));
assign s0_y_b[15] = (~(s1_raw[15] & ci0));
assign s1_x_b[15] = (~(s0_raw[15] & ci1_b));
assign s1_y_b[15] = (~(s1_raw[15] & ci1));
assign s0[15] = (~(s0_x_b[15] & s0_y_b[15]));
assign s1[15] = (~(s1_x_b[15] & s1_y_b[15]));
endmodule |
module fu_tblres(
f,
est,
rng
);
input [1:6] f;
output [1:20] est;
output [6:20] rng;
// end ports
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire dcd_00x;
wire dcd_01x;
wire dcd_10x;
wire dcd_11x;
wire dcd_000;
wire dcd_001;
wire dcd_010;
wire dcd_011;
wire dcd_100;
wire dcd_101;
wire dcd_110;
wire dcd_111;
wire combo2_1000;
wire combo2_0100;
wire combo2_1100;
wire combo2_0010;
wire combo2_1010;
wire combo2_0110;
wire combo2_1110;
wire combo2_0001;
wire combo2_1001;
wire combo2_0101;
wire combo2_1101;
wire combo2_0011;
wire combo2_1011;
wire combo2_0111;
wire combo2_1000_xxxx_b;
wire combo2_0100_xxxx_b;
wire combo2_1100_xxxx_b;
wire combo2_0010_xxxx_b;
wire combo2_1010_xxxx_b;
wire combo2_0110_xxxx_b;
wire combo2_1110_xxxx_b;
wire combo2_0001_xxxx_b;
wire combo2_1001_xxxx_b;
wire combo2_0101_xxxx_b;
wire combo2_1101_xxxx_b;
wire combo2_0011_xxxx_b;
wire combo2_1011_xxxx_b;
wire combo2_0111_xxxx_b;
wire combo2_xxxx_1000_b;
wire combo2_xxxx_0100_b;
wire combo2_xxxx_1100_b;
wire combo2_xxxx_0010_b;
wire combo2_xxxx_1010_b;
wire combo2_xxxx_0110_b;
wire combo2_xxxx_1110_b;
wire combo2_xxxx_0001_b;
wire combo2_xxxx_1001_b;
wire combo2_xxxx_0101_b;
wire combo2_xxxx_1101_b;
wire combo2_xxxx_0011_b;
wire combo2_xxxx_1011_b;
wire combo2_xxxx_0111_b;
wire combo3_0000_0001;
wire combo3_0000_0010;
wire combo3_0000_0011;
wire combo3_0000_0100;
wire combo3_0000_0101;
wire combo3_0000_0110;
wire combo3_0000_1001;
wire combo3_0000_1010;
wire combo3_0000_1011;
wire combo3_0000_1110;
wire combo3_0000_1111;
wire combo3_0001_0001;
wire combo3_0001_0010;
wire combo3_0001_0100;
wire combo3_0001_0101;
wire combo3_0001_0111;
wire combo3_0001_1000;
wire combo3_0001_1010;
wire combo3_0001_1011;
wire combo3_0001_1100;
wire combo3_0001_1110;
wire combo3_0001_1111;
wire combo3_0010_0000;
wire combo3_0010_0100;
wire combo3_0010_0101;
wire combo3_0010_0110;
wire combo3_0010_0111;
wire combo3_0010_1000;
wire combo3_0010_1001;
wire combo3_0010_1101;
wire combo3_0011_0000;
wire combo3_0011_0001;
wire combo3_0011_0011;
wire combo3_0011_0101;
wire combo3_0011_1000;
wire combo3_0011_1001;
wire combo3_0011_1010;
wire combo3_0011_1011;
wire combo3_0011_1100;
wire combo3_0011_1110;
wire combo3_0011_1111;
wire combo3_0100_0000;
wire combo3_0100_0011;
wire combo3_0100_0110;
wire combo3_0100_1000;
wire combo3_0100_1001;
wire combo3_0100_1010;
wire combo3_0100_1100;
wire combo3_0100_1101;
wire combo3_0100_1110;
wire combo3_0101_0000;
wire combo3_0101_0001;
wire combo3_0101_0010;
wire combo3_0101_0100;
wire combo3_0101_0101;
wire combo3_0101_0110;
wire combo3_0101_1000;
wire combo3_0101_1011;
wire combo3_0101_1111;
wire combo3_0110_0000;
wire combo3_0110_0010;
wire combo3_0110_0011;
wire combo3_0110_0110;
wire combo3_0110_0111;
wire combo3_0110_1000;
wire combo3_0110_1010;
wire combo3_0110_1011;
wire combo3_0110_1100;
wire combo3_0110_1101;
wire combo3_0111_0000;
wire combo3_0111_0001;
wire combo3_0111_0101;
wire combo3_0111_0110;
wire combo3_0111_1000;
wire combo3_0111_1001;
wire combo3_0111_1010;
wire combo3_0111_1011;
wire combo3_0111_1101;
wire combo3_0111_1111;
wire combo3_1000_0000;
wire combo3_1000_0001;
wire combo3_1000_0011;
wire combo3_1000_0100;
wire combo3_1000_0101;
wire combo3_1000_1010;
wire combo3_1000_1100;
wire combo3_1000_1101;
wire combo3_1001_0100;
wire combo3_1001_0110;
wire combo3_1001_0111;
wire combo3_1001_1000;
wire combo3_1001_1001;
wire combo3_1001_1010;
wire combo3_1001_1011;
wire combo3_1001_1111;
wire combo3_1010_0100;
wire combo3_1010_0110;
wire combo3_1010_1000;
wire combo3_1010_1001;
wire combo3_1010_1010;
wire combo3_1010_1011;
wire combo3_1010_1100;
wire combo3_1010_1101;
wire combo3_1011_0010;
wire combo3_1011_0011;
wire combo3_1011_0100;
wire combo3_1011_0101;
wire combo3_1011_0110;
wire combo3_1011_0111;
wire combo3_1100_0000;
wire combo3_1100_0001;
wire combo3_1100_0010;
wire combo3_1100_0011;
wire combo3_1100_0100;
wire combo3_1100_0111;
wire combo3_1100_1000;
wire combo3_1100_1001;
wire combo3_1100_1010;
wire combo3_1100_1101;
wire combo3_1100_1110;
wire combo3_1100_1111;
wire combo3_1101_0010;
wire combo3_1101_0011;
wire combo3_1101_0100;
wire combo3_1101_0101;
wire combo3_1101_0110;
wire combo3_1101_0111;
wire combo3_1101_1100;
wire combo3_1101_1101;
wire combo3_1101_1110;
wire combo3_1110_0000;
wire combo3_1110_0100;
wire combo3_1110_0101;
wire combo3_1110_0110;
wire combo3_1110_1000;
wire combo3_1110_1010;
wire combo3_1110_1101;
wire combo3_1111_0000;
wire combo3_1111_0001;
wire combo3_1111_0010;
wire combo3_1111_0100;
wire combo3_1111_1000;
wire combo3_1111_1001;
wire combo3_1111_1010;
wire combo3_1111_1100;
wire combo3_1111_1110;
wire [0:7] e_00_b;
wire [0:7] e_01_b;
wire [0:7] e_02_b;
wire [0:7] e_03_b;
wire [0:7] e_04_b;
wire [0:7] e_05_b;
wire [0:7] e_06_b;
wire [0:7] e_07_b;
wire [0:7] e_08_b;
wire [0:7] e_09_b;
wire [0:7] e_10_b;
wire [0:7] e_11_b;
wire [0:7] e_12_b;
wire [0:7] e_13_b;
wire [0:7] e_14_b;
wire [0:7] e_15_b;
wire [0:7] e_16_b;
wire [0:7] e_17_b;
wire [0:7] e_18_b;
wire [0:7] e_19_b;
wire [0:19] e;
wire [0:7] r_00_b;
wire [0:7] r_01_b;
wire [0:7] r_02_b;
wire [0:7] r_03_b;
wire [0:7] r_04_b;
wire [0:7] r_05_b;
wire [0:7] r_06_b;
wire [0:7] r_07_b;
wire [0:7] r_08_b;
wire [0:7] r_09_b;
wire [0:7] r_10_b;
wire [0:7] r_11_b;
wire [0:7] r_12_b;
wire [0:7] r_13_b;
wire [0:7] r_14_b;
wire [0:14] r;
////#######################################
////## decode the upper 3 index bits
////#######################################
assign dcd_00x = (~f[1]) & (~f[2]);
assign dcd_01x = (~f[1]) & f[2];
assign dcd_10x = f[1] & (~f[2]);
assign dcd_11x = f[1] & f[2];
assign dcd_000 = (~f[3]) & dcd_00x;
assign dcd_001 = f[3] & dcd_00x;
assign dcd_010 = (~f[3]) & dcd_01x;
assign dcd_011 = f[3] & dcd_01x;
assign dcd_100 = (~f[3]) & dcd_10x;
assign dcd_101 = f[3] & dcd_10x;
assign dcd_110 = (~f[3]) & dcd_11x;
assign dcd_111 = f[3] & dcd_11x;
////#######################################
////## combos based on lower 2 index bits
////#######################################
assign combo2_1000 = (~f[5]) & (~f[6]); // [0]
assign combo2_0100 = (~f[5]) & f[6]; // [1]
assign combo2_1100 = (~f[5]); // [0,1]
assign combo2_0010 = f[5] & (~f[6]); // [2]
assign combo2_1010 = (~f[6]); // [0,2]
assign combo2_0110 = f[5] ^ f[6]; // [1,2]
assign combo2_1110 = (~(f[5] & f[6])); // [0,1,2]
assign combo2_0001 = f[5] & f[6]; // [3]
assign combo2_1001 = (~(f[5] ^ f[6])); // [0,3]
assign combo2_0101 = f[6]; // [1,3]
assign combo2_1101 = (~(f[5] & (~f[6]))); // [1,2,3]
assign combo2_0011 = f[5]; // [2,3]
assign combo2_1011 = (~((~f[5]) & f[6])); // [0,2,3]
assign combo2_0111 = (~((~f[5]) & (~f[6]))); // [1,2,3]
////#######################################
////## combos based on lower 3 index bits
////#######################################
assign combo2_1000_xxxx_b = (~((~f[4]) & combo2_1000));
assign combo2_0100_xxxx_b = (~((~f[4]) & combo2_0100));
assign combo2_1100_xxxx_b = (~((~f[4]) & combo2_1100));
assign combo2_0010_xxxx_b = (~((~f[4]) & combo2_0010));
assign combo2_1010_xxxx_b = (~((~f[4]) & combo2_1010));
assign combo2_0110_xxxx_b = (~((~f[4]) & combo2_0110));
assign combo2_1110_xxxx_b = (~((~f[4]) & combo2_1110));
assign combo2_0001_xxxx_b = (~((~f[4]) & combo2_0001));
assign combo2_1001_xxxx_b = (~((~f[4]) & combo2_1001));
assign combo2_0101_xxxx_b = (~((~f[4]) & combo2_0101));
assign combo2_1101_xxxx_b = (~((~f[4]) & combo2_1101));
assign combo2_0011_xxxx_b = (~((~f[4]) & combo2_0011));
assign combo2_1011_xxxx_b = (~((~f[4]) & combo2_1011));
assign combo2_0111_xxxx_b = (~((~f[4]) & combo2_0111));
assign combo2_xxxx_1000_b = (~(f[4] & combo2_1000));
assign combo2_xxxx_0100_b = (~(f[4] & combo2_0100));
assign combo2_xxxx_1100_b = (~(f[4] & combo2_1100));
assign combo2_xxxx_0010_b = (~(f[4] & combo2_0010));
assign combo2_xxxx_1010_b = (~(f[4] & combo2_1010));
assign combo2_xxxx_0110_b = (~(f[4] & combo2_0110));
assign combo2_xxxx_1110_b = (~(f[4] & combo2_1110));
assign combo2_xxxx_0001_b = (~(f[4] & combo2_0001));
assign combo2_xxxx_1001_b = (~(f[4] & combo2_1001));
assign combo2_xxxx_0101_b = (~(f[4] & combo2_0101));
assign combo2_xxxx_1101_b = (~(f[4] & combo2_1101));
assign combo2_xxxx_0011_b = (~(f[4] & combo2_0011));
assign combo2_xxxx_1011_b = (~(f[4] & combo2_1011));
assign combo2_xxxx_0111_b = (~(f[4] & combo2_0111));
assign combo3_0000_0001 = (~(combo2_xxxx_0001_b)); //i=1, 2 1
assign combo3_0000_0010 = (~(combo2_xxxx_0010_b)); //i=2, 1 2
assign combo3_0000_0011 = (~(combo2_xxxx_0011_b)); //i=3, 3 3
assign combo3_0000_0100 = (~(combo2_xxxx_0100_b)); //i=4, 1 4
assign combo3_0000_0101 = (~(combo2_xxxx_0101_b)); //i=5, 2 5
assign combo3_0000_0110 = (~(combo2_xxxx_0110_b)); //i=6, 2 6
assign combo3_0000_1001 = (~(combo2_xxxx_1001_b)); //i=9, 1 7
assign combo3_0000_1010 = (~(combo2_xxxx_1010_b)); //i=10, 2 8
assign combo3_0000_1011 = (~(combo2_xxxx_1011_b)); //i=11, 2 9
assign combo3_0000_1110 = (~(combo2_xxxx_1110_b)); //i=14, 1 10
assign combo3_0000_1111 = (~((~f[4]))); //i=15, 2 11
assign combo3_0001_0001 = (~((~combo2_0001))); //i=17, 2 12*
assign combo3_0001_0010 = (~(combo2_0001_xxxx_b & combo2_xxxx_0010_b)); //i=18, 1 13
assign combo3_0001_0100 = (~(combo2_0001_xxxx_b & combo2_xxxx_0100_b)); //i=20, 1 14
assign combo3_0001_0101 = (~(combo2_0001_xxxx_b & combo2_xxxx_0101_b)); //i=21, 1 15
assign combo3_0001_0111 = (~(combo2_0001_xxxx_b & combo2_xxxx_0111_b)); //i=23, 1 16
assign combo3_0001_1000 = (~(combo2_0001_xxxx_b & combo2_xxxx_1000_b)); //i=24, 3 17
assign combo3_0001_1010 = (~(combo2_0001_xxxx_b & combo2_xxxx_1010_b)); //i=26, 1 18
assign combo3_0001_1011 = (~(combo2_0001_xxxx_b & combo2_xxxx_1011_b)); //i=27, 1 19
assign combo3_0001_1100 = (~(combo2_0001_xxxx_b & combo2_xxxx_1100_b)); //i=28, 1 20
assign combo3_0001_1110 = (~(combo2_0001_xxxx_b & combo2_xxxx_1110_b)); //i=30, 1 21
assign combo3_0001_1111 = (~(combo2_0001_xxxx_b & (~f[4]))); //i=31, 4 22
assign combo3_0010_0000 = (~(combo2_0010_xxxx_b)); //i=32, 2 23
assign combo3_0010_0100 = (~(combo2_0010_xxxx_b & combo2_xxxx_0100_b)); //i=36, 1 24
assign combo3_0010_0101 = (~(combo2_0010_xxxx_b & combo2_xxxx_0101_b)); //i=37, 1 25
assign combo3_0010_0110 = (~(combo2_0010_xxxx_b & combo2_xxxx_0110_b)); //i=38, 2 26
assign combo3_0010_0111 = (~(combo2_0010_xxxx_b & combo2_xxxx_0111_b)); //i=39, 1 27
assign combo3_0010_1000 = (~(combo2_0010_xxxx_b & combo2_xxxx_1000_b)); //i=40, 2 28
assign combo3_0010_1001 = (~(combo2_0010_xxxx_b & combo2_xxxx_1001_b)); //i=41, 1 29
assign combo3_0010_1101 = (~(combo2_0010_xxxx_b & combo2_xxxx_1101_b)); //i=45, 4 30
assign combo3_0011_0000 = (~(combo2_0011_xxxx_b)); //i=48, 1 31
assign combo3_0011_0001 = (~(combo2_0011_xxxx_b & combo2_xxxx_0001_b)); //i=49, 3 32
assign combo3_0011_0011 = (~((~combo2_0011))); //i=51, 1 33*
assign combo3_0011_0101 = (~(combo2_0011_xxxx_b & combo2_xxxx_0101_b)); //i=53, 1 34
assign combo3_0011_1000 = (~(combo2_0011_xxxx_b & combo2_xxxx_1000_b)); //i=56, 3 35
assign combo3_0011_1001 = (~(combo2_0011_xxxx_b & combo2_xxxx_1001_b)); //i=57, 1 36
assign combo3_0011_1010 = (~(combo2_0011_xxxx_b & combo2_xxxx_1010_b)); //i=58, 1 37
assign combo3_0011_1011 = (~(combo2_0011_xxxx_b & combo2_xxxx_1011_b)); //i=59, 1 38
assign combo3_0011_1100 = (~(combo2_0011_xxxx_b & combo2_xxxx_1100_b)); //i=60, 3 39
assign combo3_0011_1110 = (~(combo2_0011_xxxx_b & combo2_xxxx_1110_b)); //i=62, 1 40
assign combo3_0011_1111 = (~(combo2_0011_xxxx_b & (~f[4]))); //i=63, 4 41
assign combo3_0100_0000 = (~(combo2_0100_xxxx_b)); //i=64, 1 42
assign combo3_0100_0011 = (~(combo2_0100_xxxx_b & combo2_xxxx_0011_b)); //i=67, 2 43
assign combo3_0100_0110 = (~(combo2_0100_xxxx_b & combo2_xxxx_0110_b)); //i=70, 1 44
assign combo3_0100_1000 = (~(combo2_0100_xxxx_b & combo2_xxxx_1000_b)); //i=72, 2 45
assign combo3_0100_1001 = (~(combo2_0100_xxxx_b & combo2_xxxx_1001_b)); //i=73, 2 46
assign combo3_0100_1010 = (~(combo2_0100_xxxx_b & combo2_xxxx_1010_b)); //i=74, 2 47
assign combo3_0100_1100 = (~(combo2_0100_xxxx_b & combo2_xxxx_1100_b)); //i=76, 1 48
assign combo3_0100_1101 = (~(combo2_0100_xxxx_b & combo2_xxxx_1101_b)); //i=77, 1 49
assign combo3_0100_1110 = (~(combo2_0100_xxxx_b & combo2_xxxx_1110_b)); //i=78, 1 50
assign combo3_0101_0000 = (~(combo2_0101_xxxx_b)); //i=80, 3 51
assign combo3_0101_0001 = (~(combo2_0101_xxxx_b & combo2_xxxx_0001_b)); //i=81, 1 52
assign combo3_0101_0010 = (~(combo2_0101_xxxx_b & combo2_xxxx_0010_b)); //i=82, 1 53
assign combo3_0101_0100 = (~(combo2_0101_xxxx_b & combo2_xxxx_0100_b)); //i=84, 3 54
assign combo3_0101_0101 = (~((~combo2_0101))); //i=85, 1 55*
assign combo3_0101_0110 = (~(combo2_0101_xxxx_b & combo2_xxxx_0110_b)); //i=86, 1 56
assign combo3_0101_1000 = (~(combo2_0101_xxxx_b & combo2_xxxx_1000_b)); //i=88, 1 57
assign combo3_0101_1011 = (~(combo2_0101_xxxx_b & combo2_xxxx_1011_b)); //i=91, 3 58
assign combo3_0101_1111 = (~(combo2_0101_xxxx_b & (~f[4]))); //i=95, 1 59
assign combo3_0110_0000 = (~(combo2_0110_xxxx_b)); //i=96, 1 60
assign combo3_0110_0010 = (~(combo2_0110_xxxx_b & combo2_xxxx_0010_b)); //i=98, 1 61
assign combo3_0110_0011 = (~(combo2_0110_xxxx_b & combo2_xxxx_0011_b)); //i=99, 1 62
assign combo3_0110_0110 = (~((~combo2_0110))); //i=102, 1 63*
assign combo3_0110_0111 = (~(combo2_0110_xxxx_b & combo2_xxxx_0111_b)); //i=103, 3 64
assign combo3_0110_1000 = (~(combo2_0110_xxxx_b & combo2_xxxx_1000_b)); //i=104, 1 65
assign combo3_0110_1010 = (~(combo2_0110_xxxx_b & combo2_xxxx_1010_b)); //i=106, 2 66
assign combo3_0110_1011 = (~(combo2_0110_xxxx_b & combo2_xxxx_1011_b)); //i=107, 1 67
assign combo3_0110_1100 = (~(combo2_0110_xxxx_b & combo2_xxxx_1100_b)); //i=108, 1 68
assign combo3_0110_1101 = (~(combo2_0110_xxxx_b & combo2_xxxx_1101_b)); //i=109, 1 69
assign combo3_0111_0000 = (~(combo2_0111_xxxx_b)); //i=112, 3 70
assign combo3_0111_0001 = (~(combo2_0111_xxxx_b & combo2_xxxx_0001_b)); //i=113, 1 71
assign combo3_0111_0101 = (~(combo2_0111_xxxx_b & combo2_xxxx_0101_b)); //i=117, 1 72
assign combo3_0111_0110 = (~(combo2_0111_xxxx_b & combo2_xxxx_0110_b)); //i=118, 1 73
assign combo3_0111_1000 = (~(combo2_0111_xxxx_b & combo2_xxxx_1000_b)); //i=120, 3 74
assign combo3_0111_1001 = (~(combo2_0111_xxxx_b & combo2_xxxx_1001_b)); //i=121, 1 75
assign combo3_0111_1010 = (~(combo2_0111_xxxx_b & combo2_xxxx_1010_b)); //i=122, 2 76
assign combo3_0111_1011 = (~(combo2_0111_xxxx_b & combo2_xxxx_1011_b)); //i=123, 1 77
assign combo3_0111_1101 = (~(combo2_0111_xxxx_b & combo2_xxxx_1101_b)); //i=125, 1 78
assign combo3_0111_1111 = (~(combo2_0111_xxxx_b & (~f[4]))); //i=127, 3 79
assign combo3_1000_0000 = (~(combo2_1000_xxxx_b)); //i=128, 7 80
assign combo3_1000_0001 = (~(combo2_1000_xxxx_b & combo2_xxxx_0001_b)); //i=129, 1 81
assign combo3_1000_0011 = (~(combo2_1000_xxxx_b & combo2_xxxx_0011_b)); //i=131, 1 82
assign combo3_1000_0100 = (~(combo2_1000_xxxx_b & combo2_xxxx_0100_b)); //i=132, 2 83
assign combo3_1000_0101 = (~(combo2_1000_xxxx_b & combo2_xxxx_0101_b)); //i=133, 1 84
assign combo3_1000_1010 = (~(combo2_1000_xxxx_b & combo2_xxxx_1010_b)); //i=138, 1 85
assign combo3_1000_1100 = (~(combo2_1000_xxxx_b & combo2_xxxx_1100_b)); //i=140, 1 86
assign combo3_1000_1101 = (~(combo2_1000_xxxx_b & combo2_xxxx_1101_b)); //i=141, 1 87
assign combo3_1001_0100 = (~(combo2_1001_xxxx_b & combo2_xxxx_0100_b)); //i=148, 1 88
assign combo3_1001_0110 = (~(combo2_1001_xxxx_b & combo2_xxxx_0110_b)); //i=150, 3 89
assign combo3_1001_0111 = (~(combo2_1001_xxxx_b & combo2_xxxx_0111_b)); //i=151, 1 90
assign combo3_1001_1000 = (~(combo2_1001_xxxx_b & combo2_xxxx_1000_b)); //i=152, 1 91
assign combo3_1001_1001 = (~((~combo2_1001))); //i=153, 3 92*
assign combo3_1001_1010 = (~(combo2_1001_xxxx_b & combo2_xxxx_1010_b)); //i=154, 1 93
assign combo3_1001_1011 = (~(combo2_1001_xxxx_b & combo2_xxxx_1011_b)); //i=155, 1 94
assign combo3_1001_1111 = (~(combo2_1001_xxxx_b & (~f[4]))); //i=159, 1 95
assign combo3_1010_0100 = (~(combo2_1010_xxxx_b & combo2_xxxx_0100_b)); //i=164, 1 96
assign combo3_1010_0110 = (~(combo2_1010_xxxx_b & combo2_xxxx_0110_b)); //i=166, 1 97
assign combo3_1010_1000 = (~(combo2_1010_xxxx_b & combo2_xxxx_1000_b)); //i=168, 2 98
assign combo3_1010_1001 = (~(combo2_1010_xxxx_b & combo2_xxxx_1001_b)); //i=169, 1 99
assign combo3_1010_1010 = (~((~combo2_1010))); //i=170, 1 100*
assign combo3_1010_1011 = (~(combo2_1010_xxxx_b & combo2_xxxx_1011_b)); //i=171, 1 101
assign combo3_1010_1100 = (~(combo2_1010_xxxx_b & combo2_xxxx_1100_b)); //i=172, 2 102
assign combo3_1010_1101 = (~(combo2_1010_xxxx_b & combo2_xxxx_1101_b)); //i=173, 2 103
assign combo3_1011_0010 = (~(combo2_1011_xxxx_b & combo2_xxxx_0010_b)); //i=178, 1 104
assign combo3_1011_0011 = (~(combo2_1011_xxxx_b & combo2_xxxx_0011_b)); //i=179, 3 105
assign combo3_1011_0100 = (~(combo2_1011_xxxx_b & combo2_xxxx_0100_b)); //i=180, 1 106
assign combo3_1011_0101 = (~(combo2_1011_xxxx_b & combo2_xxxx_0101_b)); //i=181, 2 107
assign combo3_1011_0110 = (~(combo2_1011_xxxx_b & combo2_xxxx_0110_b)); //i=182, 3 108
assign combo3_1011_0111 = (~(combo2_1011_xxxx_b & combo2_xxxx_0111_b)); //i=183, 1 109
assign combo3_1100_0000 = (~(combo2_1100_xxxx_b)); //i=192, 4 110
assign combo3_1100_0001 = (~(combo2_1100_xxxx_b & combo2_xxxx_0001_b)); //i=193, 1 111
assign combo3_1100_0010 = (~(combo2_1100_xxxx_b & combo2_xxxx_0010_b)); //i=194, 1 112
assign combo3_1100_0011 = (~(combo2_1100_xxxx_b & combo2_xxxx_0011_b)); //i=195, 2 113
assign combo3_1100_0100 = (~(combo2_1100_xxxx_b & combo2_xxxx_0100_b)); //i=196, 1 114
assign combo3_1100_0111 = (~(combo2_1100_xxxx_b & combo2_xxxx_0111_b)); //i=199, 1 115
assign combo3_1100_1000 = (~(combo2_1100_xxxx_b & combo2_xxxx_1000_b)); //i=200, 1 116
assign combo3_1100_1001 = (~(combo2_1100_xxxx_b & combo2_xxxx_1001_b)); //i=201, 2 117
assign combo3_1100_1010 = (~(combo2_1100_xxxx_b & combo2_xxxx_1010_b)); //i=202, 2 118
assign combo3_1100_1101 = (~(combo2_1100_xxxx_b & combo2_xxxx_1101_b)); //i=205, 2 119
assign combo3_1100_1110 = (~(combo2_1100_xxxx_b & combo2_xxxx_1110_b)); //i=206, 2 120
assign combo3_1100_1111 = (~(combo2_1100_xxxx_b & (~f[4]))); //i=207, 2 121
assign combo3_1101_0010 = (~(combo2_1101_xxxx_b & combo2_xxxx_0010_b)); //i=210, 1 122
assign combo3_1101_0011 = (~(combo2_1101_xxxx_b & combo2_xxxx_0011_b)); //i=211, 1 123
assign combo3_1101_0100 = (~(combo2_1101_xxxx_b & combo2_xxxx_0100_b)); //i=212, 2 124
assign combo3_1101_0101 = (~(combo2_1101_xxxx_b & combo2_xxxx_0101_b)); //i=213, 1 125
assign combo3_1101_0110 = (~(combo2_1101_xxxx_b & combo2_xxxx_0110_b)); //i=214, 2 126
assign combo3_1101_0111 = (~(combo2_1101_xxxx_b & combo2_xxxx_0111_b)); //i=215, 1 127
assign combo3_1101_1100 = (~(combo2_1101_xxxx_b & combo2_xxxx_1100_b)); //i=220, 1 128
assign combo3_1101_1101 = (~((~combo2_1101))); //i=221, 1 129*
assign combo3_1101_1110 = (~(combo2_1101_xxxx_b & combo2_xxxx_1110_b)); //i=222, 1 130
assign combo3_1110_0000 = (~(combo2_1110_xxxx_b)); //i=224, 2 131
assign combo3_1110_0100 = (~(combo2_1110_xxxx_b & combo2_xxxx_0100_b)); //i=228, 2 132
assign combo3_1110_0101 = (~(combo2_1110_xxxx_b & combo2_xxxx_0101_b)); //i=229, 1 133
assign combo3_1110_0110 = (~(combo2_1110_xxxx_b & combo2_xxxx_0110_b)); //i=230, 1 134
assign combo3_1110_1000 = (~(combo2_1110_xxxx_b & combo2_xxxx_1000_b)); //i=232, 1 135
assign combo3_1110_1010 = (~(combo2_1110_xxxx_b & combo2_xxxx_1010_b)); //i=234, 1 136
assign combo3_1110_1101 = (~(combo2_1110_xxxx_b & combo2_xxxx_1101_b)); //i=237, 2 137
assign combo3_1111_0000 = (~(f[4])); //i=240, 2 138
assign combo3_1111_0001 = (~(f[4] & combo2_xxxx_0001_b)); //i=241, 1 139
assign combo3_1111_0010 = (~(f[4] & combo2_xxxx_0010_b)); //i=242, 1 140
assign combo3_1111_0100 = (~(f[4] & combo2_xxxx_0100_b)); //i=244, 2 141
assign combo3_1111_1000 = (~(f[4] & combo2_xxxx_1000_b)); //i=248, 1 142
assign combo3_1111_1001 = (~(f[4] & combo2_xxxx_1001_b)); //i=249, 1 143
assign combo3_1111_1010 = (~(f[4] & combo2_xxxx_1010_b)); //i=250, 1 144
assign combo3_1111_1100 = (~(f[4] & combo2_xxxx_1100_b)); //i=252, 2 145
assign combo3_1111_1110 = (~(f[4] & combo2_xxxx_1110_b)); //i=254, 2 146
////#######################################
////## ESTIMATE VECTORs
////#######################################
assign e_00_b[0] = (~(dcd_000 & tiup));
assign e_00_b[1] = (~(dcd_001 & tiup));
assign e_00_b[2] = (~(dcd_010 & combo3_1111_1100));
assign e_00_b[3] = (~(dcd_011 & tidn));
assign e_00_b[4] = (~(dcd_100 & tidn));
assign e_00_b[5] = (~(dcd_101 & tidn));
assign e_00_b[6] = (~(dcd_110 & tidn));
assign e_00_b[7] = (~(dcd_111 & tidn));
assign e[0] = (~(e_00_b[0] & e_00_b[1] & e_00_b[2] & e_00_b[3] & e_00_b[4] & e_00_b[5] & e_00_b[6] & e_00_b[7]));
assign e_01_b[0] = (~(dcd_000 & tiup));
assign e_01_b[1] = (~(dcd_001 & combo3_1100_0000));
assign e_01_b[2] = (~(dcd_010 & combo3_0000_0011));
assign e_01_b[3] = (~(dcd_011 & tiup));
assign e_01_b[4] = (~(dcd_100 & combo3_1111_1110));
assign e_01_b[5] = (~(dcd_101 & tidn));
assign e_01_b[6] = (~(dcd_110 & tidn));
assign e_01_b[7] = (~(dcd_111 & tidn));
assign e[1] = (~(e_01_b[0] & e_01_b[1] & e_01_b[2] & e_01_b[3] & e_01_b[4] & e_01_b[5] & e_01_b[6] & e_01_b[7]));
assign e_02_b[0] = (~(dcd_000 & combo3_1111_1000));
assign e_02_b[1] = (~(dcd_001 & combo3_0011_1110));
assign e_02_b[2] = (~(dcd_010 & combo3_0000_0011));
assign e_02_b[3] = (~(dcd_011 & combo3_1111_1100));
assign e_02_b[4] = (~(dcd_100 & combo3_0000_0001));
assign e_02_b[5] = (~(dcd_101 & tiup));
assign e_02_b[6] = (~(dcd_110 & combo3_1100_0000));
assign e_02_b[7] = (~(dcd_111 & tidn));
assign e[2] = (~(e_02_b[0] & e_02_b[1] & e_02_b[2] & e_02_b[3] & e_02_b[4] & e_02_b[5] & e_02_b[6] & e_02_b[7]));
assign e_03_b[0] = (~(dcd_000 & combo3_1110_0110));
assign e_03_b[1] = (~(dcd_001 & combo3_0011_0001));
assign e_03_b[2] = (~(dcd_010 & combo3_1100_0011));
assign e_03_b[3] = (~(dcd_011 & combo3_1100_0011));
assign e_03_b[4] = (~(dcd_100 & combo3_1100_0001));
assign e_03_b[5] = (~(dcd_101 & combo3_1111_0000));
assign e_03_b[6] = (~(dcd_110 & combo3_0011_1111));
assign e_03_b[7] = (~(dcd_111 & combo3_1000_0000));
assign e[3] = (~(e_03_b[0] & e_03_b[1] & e_03_b[2] & e_03_b[3] & e_03_b[4] & e_03_b[5] & e_03_b[6] & e_03_b[7]));
assign e_04_b[0] = (~(dcd_000 & combo3_1101_0101));
assign e_04_b[1] = (~(dcd_001 & combo3_0010_1101));
assign e_04_b[2] = (~(dcd_010 & combo3_1011_0011));
assign e_04_b[3] = (~(dcd_011 & combo3_0011_0011));
assign e_04_b[4] = (~(dcd_100 & combo3_0011_0001));
assign e_04_b[5] = (~(dcd_101 & combo3_1100_1110));
assign e_04_b[6] = (~(dcd_110 & combo3_0011_1100));
assign e_04_b[7] = (~(dcd_111 & combo3_0111_1000));
assign e[4] = (~(e_04_b[0] & e_04_b[1] & e_04_b[2] & e_04_b[3] & e_04_b[4] & e_04_b[5] & e_04_b[6] & e_04_b[7]));
assign e_05_b[0] = (~(dcd_000 & combo3_1000_0011));
assign e_05_b[1] = (~(dcd_001 & combo3_1001_1011));
assign e_05_b[2] = (~(dcd_010 & combo3_0110_1010));
assign e_05_b[3] = (~(dcd_011 & combo3_1010_1010));
assign e_05_b[4] = (~(dcd_100 & combo3_1010_1101));
assign e_05_b[5] = (~(dcd_101 & combo3_0010_1101));
assign e_05_b[6] = (~(dcd_110 & combo3_1011_0010));
assign e_05_b[7] = (~(dcd_111 & combo3_0110_0110));
assign e[5] = (~(e_05_b[0] & e_05_b[1] & e_05_b[2] & e_05_b[3] & e_05_b[4] & e_05_b[5] & e_05_b[6] & e_05_b[7]));
assign e_06_b[0] = (~(dcd_000 & combo3_1000_0100));
assign e_06_b[1] = (~(dcd_001 & combo3_1010_1001));
assign e_06_b[2] = (~(dcd_010 & combo3_0011_1000));
assign e_06_b[3] = (~(dcd_011 & tidn));
assign e_06_b[4] = (~(dcd_100 & combo3_0011_1001));
assign e_06_b[5] = (~(dcd_101 & combo3_1001_1001));
assign e_06_b[6] = (~(dcd_110 & combo3_0010_1001));
assign e_06_b[7] = (~(dcd_111 & combo3_0101_0101));
assign e[6] = (~(e_06_b[0] & e_06_b[1] & e_06_b[2] & e_06_b[3] & e_06_b[4] & e_06_b[5] & e_06_b[6] & e_06_b[7]));
assign e_07_b[0] = (~(dcd_000 & combo3_1001_1001));
assign e_07_b[1] = (~(dcd_001 & combo3_1000_1100));
assign e_07_b[2] = (~(dcd_010 & combo3_1010_0110));
assign e_07_b[3] = (~(dcd_011 & tidn));
assign e_07_b[4] = (~(dcd_100 & combo3_1100_1010));
assign e_07_b[5] = (~(dcd_101 & combo3_1010_1011));
assign e_07_b[6] = (~(dcd_110 & combo3_0110_0011));
assign e_07_b[7] = (~(dcd_111 & combo3_1000_0000));
assign e[7] = (~(e_07_b[0] & e_07_b[1] & e_07_b[2] & e_07_b[3] & e_07_b[4] & e_07_b[5] & e_07_b[6] & e_07_b[7]));
assign e_08_b[0] = (~(dcd_000 & combo3_1000_1101));
assign e_08_b[1] = (~(dcd_001 & combo3_0111_0101));
assign e_08_b[2] = (~(dcd_010 & combo3_1111_0001));
assign e_08_b[3] = (~(dcd_011 & combo3_0000_0011));
assign e_08_b[4] = (~(dcd_100 & combo3_0101_1000));
assign e_08_b[5] = (~(dcd_101 & combo3_0000_0110));
assign e_08_b[6] = (~(dcd_110 & combo3_1101_0010));
assign e_08_b[7] = (~(dcd_111 & combo3_0110_0000));
assign e[8] = (~(e_08_b[0] & e_08_b[1] & e_08_b[2] & e_08_b[3] & e_08_b[4] & e_08_b[5] & e_08_b[6] & e_08_b[7]));
assign e_09_b[0] = (~(dcd_000 & combo3_1010_1100));
assign e_09_b[1] = (~(dcd_001 & combo3_0111_0001));
assign e_09_b[2] = (~(dcd_010 & combo3_0001_0100));
assign e_09_b[3] = (~(dcd_011 & combo3_1000_0101));
assign e_09_b[4] = (~(dcd_100 & combo3_1111_0100));
assign e_09_b[5] = (~(dcd_101 & combo3_0000_1010));
assign e_09_b[6] = (~(dcd_110 & combo3_0111_1001));
assign e_09_b[7] = (~(dcd_111 & combo3_0101_0000));
assign e[9] = (~(e_09_b[0] & e_09_b[1] & e_09_b[2] & e_09_b[3] & e_09_b[4] & e_09_b[5] & e_09_b[6] & e_09_b[7]));
assign e_10_b[0] = (~(dcd_000 & combo3_1010_0100));
assign e_10_b[1] = (~(dcd_001 & combo3_0001_1000));
assign e_10_b[2] = (~(dcd_010 & combo3_0000_0101));
assign e_10_b[3] = (~(dcd_011 & combo3_0100_1001));
assign e_10_b[4] = (~(dcd_100 & combo3_0001_1110));
assign e_10_b[5] = (~(dcd_101 & combo3_0001_1011));
assign e_10_b[6] = (~(dcd_110 & combo3_0111_1010));
assign e_10_b[7] = (~(dcd_111 & combo3_0001_1100));
assign e[10] = (~(e_10_b[0] & e_10_b[1] & e_10_b[2] & e_10_b[3] & e_10_b[4] & e_10_b[5] & e_10_b[6] & e_10_b[7]));
assign e_11_b[0] = (~(dcd_000 & combo3_1110_1010));
assign e_11_b[1] = (~(dcd_001 & combo3_1100_0010));
assign e_11_b[2] = (~(dcd_010 & combo3_1010_1100));
assign e_11_b[3] = (~(dcd_011 & combo3_1011_0110));
assign e_11_b[4] = (~(dcd_100 & combo3_1011_0011));
assign e_11_b[5] = (~(dcd_101 & combo3_0011_0101));
assign e_11_b[6] = (~(dcd_110 & combo3_0100_1001));
assign e_11_b[7] = (~(dcd_111 & combo3_0010_1000));
assign e[11] = (~(e_11_b[0] & e_11_b[1] & e_11_b[2] & e_11_b[3] & e_11_b[4] & e_11_b[5] & e_11_b[6] & e_11_b[7]));
assign e_12_b[0] = (~(dcd_000 & combo3_1111_1010));
assign e_12_b[1] = (~(dcd_001 & combo3_1110_0100));
assign e_12_b[2] = (~(dcd_010 & combo3_0010_0100));
assign e_12_b[3] = (~(dcd_011 & combo3_1100_1001));
assign e_12_b[4] = (~(dcd_100 & combo3_0111_1111));
assign e_12_b[5] = (~(dcd_101 & combo3_1111_0100));
assign e_12_b[6] = (~(dcd_110 & combo3_1011_0111));
assign e_12_b[7] = (~(dcd_111 & combo3_1100_1010));
assign e[12] = (~(e_12_b[0] & e_12_b[1] & e_12_b[2] & e_12_b[3] & e_12_b[4] & e_12_b[5] & e_12_b[6] & e_12_b[7]));
assign e_13_b[0] = (~(dcd_000 & combo3_1001_1000));
assign e_13_b[1] = (~(dcd_001 & combo3_0101_1011));
assign e_13_b[2] = (~(dcd_010 & combo3_1101_1100));
assign e_13_b[3] = (~(dcd_011 & combo3_0000_0110));
assign e_13_b[4] = (~(dcd_100 & combo3_0100_0011));
assign e_13_b[5] = (~(dcd_101 & combo3_1110_1000));
assign e_13_b[6] = (~(dcd_110 & combo3_1111_1110));
assign e_13_b[7] = (~(dcd_111 & combo3_1001_1010));
assign e[13] = (~(e_13_b[0] & e_13_b[1] & e_13_b[2] & e_13_b[3] & e_13_b[4] & e_13_b[5] & e_13_b[6] & e_13_b[7]));
assign e_14_b[0] = (~(dcd_000 & combo3_0101_0100));
assign e_14_b[1] = (~(dcd_001 & combo3_0010_0110));
assign e_14_b[2] = (~(dcd_010 & combo3_0101_0000));
assign e_14_b[3] = (~(dcd_011 & combo3_0111_0000));
assign e_14_b[4] = (~(dcd_100 & combo3_0010_1101));
assign e_14_b[5] = (~(dcd_101 & combo3_1101_0100));
assign e_14_b[6] = (~(dcd_110 & combo3_1100_1000));
assign e_14_b[7] = (~(dcd_111 & combo3_0110_1000));
assign e[14] = (~(e_14_b[0] & e_14_b[1] & e_14_b[2] & e_14_b[3] & e_14_b[4] & e_14_b[5] & e_14_b[6] & e_14_b[7]));
assign e_15_b[0] = (~(dcd_000 & combo3_0101_1011));
assign e_15_b[1] = (~(dcd_001 & combo3_0010_0000));
assign e_15_b[2] = (~(dcd_010 & combo3_1101_0110));
assign e_15_b[3] = (~(dcd_011 & combo3_1000_0001));
assign e_15_b[4] = (~(dcd_100 & combo3_1001_0110));
assign e_15_b[5] = (~(dcd_101 & combo3_1110_0101));
assign e_15_b[6] = (~(dcd_110 & combo3_0100_1110));
assign e_15_b[7] = (~(dcd_111 & combo3_1110_0000));
assign e[15] = (~(e_15_b[0] & e_15_b[1] & e_15_b[2] & e_15_b[3] & e_15_b[4] & e_15_b[5] & e_15_b[6] & e_15_b[7]));
assign e_16_b[0] = (~(dcd_000 & combo3_0100_1000));
assign e_16_b[1] = (~(dcd_001 & combo3_0010_0101));
assign e_16_b[2] = (~(dcd_010 & combo3_1001_0111));
assign e_16_b[3] = (~(dcd_011 & combo3_0011_1010));
assign e_16_b[4] = (~(dcd_100 & combo3_0000_0101));
assign e_16_b[5] = (~(dcd_101 & combo3_1110_0100));
assign e_16_b[6] = (~(dcd_110 & combo3_0000_1111));
assign e_16_b[7] = (~(dcd_111 & combo3_0000_0100));
assign e[16] = (~(e_16_b[0] & e_16_b[1] & e_16_b[2] & e_16_b[3] & e_16_b[4] & e_16_b[5] & e_16_b[6] & e_16_b[7]));
assign e_17_b[0] = (~(dcd_000 & combo3_0000_1011));
assign e_17_b[1] = (~(dcd_001 & combo3_1100_1111));
assign e_17_b[2] = (~(dcd_010 & combo3_0000_1011));
assign e_17_b[3] = (~(dcd_011 & combo3_0010_0000));
assign e_17_b[4] = (~(dcd_100 & combo3_1101_0011));
assign e_17_b[5] = (~(dcd_101 & combo3_0010_1000));
assign e_17_b[6] = (~(dcd_110 & combo3_1111_0010));
assign e_17_b[7] = (~(dcd_111 & combo3_0100_0110));
assign e[17] = (~(e_17_b[0] & e_17_b[1] & e_17_b[2] & e_17_b[3] & e_17_b[4] & e_17_b[5] & e_17_b[6] & e_17_b[7]));
assign e_18_b[0] = (~(dcd_000 & combo3_0000_1001));
assign e_18_b[1] = (~(dcd_001 & combo3_1100_1101));
assign e_18_b[2] = (~(dcd_010 & combo3_0000_1010));
assign e_18_b[3] = (~(dcd_011 & combo3_0000_0001));
assign e_18_b[4] = (~(dcd_100 & combo3_0101_0000));
assign e_18_b[5] = (~(dcd_101 & combo3_1001_0100));
assign e_18_b[6] = (~(dcd_110 & combo3_0101_0010));
assign e_18_b[7] = (~(dcd_111 & tidn));
assign e[18] = (~(e_18_b[0] & e_18_b[1] & e_18_b[2] & e_18_b[3] & e_18_b[4] & e_18_b[5] & e_18_b[6] & e_18_b[7]));
assign e_19_b[0] = (~(dcd_000 & combo3_0111_1111));
assign e_19_b[1] = (~(dcd_001 & tiup));
assign e_19_b[2] = (~(dcd_010 & tiup));
assign e_19_b[3] = (~(dcd_011 & tiup));
assign e_19_b[4] = (~(dcd_100 & tiup));
assign e_19_b[5] = (~(dcd_101 & tiup));
assign e_19_b[6] = (~(dcd_110 & tiup));
assign e_19_b[7] = (~(dcd_111 & tiup));
assign e[19] = (~(e_19_b[0] & e_19_b[1] & e_19_b[2] & e_19_b[3] & e_19_b[4] & e_19_b[5] & e_19_b[6] & e_19_b[7]));
////#######################################
////## RANGE VECTORs
////#######################################
assign r_00_b[0] = (~(dcd_000 & tiup));
assign r_00_b[1] = (~(dcd_001 & tiup));
assign r_00_b[2] = (~(dcd_010 & tiup));
assign r_00_b[3] = (~(dcd_011 & combo3_1110_0000));
assign r_00_b[4] = (~(dcd_100 & tidn));
assign r_00_b[5] = (~(dcd_101 & tidn));
assign r_00_b[6] = (~(dcd_110 & tidn));
assign r_00_b[7] = (~(dcd_111 & tidn));
assign r[0] = (~(r_00_b[0] & r_00_b[1] & r_00_b[2] & r_00_b[3] & r_00_b[4] & r_00_b[5] & r_00_b[6] & r_00_b[7]));
assign r_01_b[0] = (~(dcd_000 & tiup));
assign r_01_b[1] = (~(dcd_001 & combo3_1100_0000));
assign r_01_b[2] = (~(dcd_010 & tidn));
assign r_01_b[3] = (~(dcd_011 & combo3_0001_1111));
assign r_01_b[4] = (~(dcd_100 & tiup));
assign r_01_b[5] = (~(dcd_101 & tiup));
assign r_01_b[6] = (~(dcd_110 & tiup));
assign r_01_b[7] = (~(dcd_111 & tiup));
assign r[1] = (~(r_01_b[0] & r_01_b[1] & r_01_b[2] & r_01_b[3] & r_01_b[4] & r_01_b[5] & r_01_b[6] & r_01_b[7]));
assign r_02_b[0] = (~(dcd_000 & combo3_1111_0000));
assign r_02_b[1] = (~(dcd_001 & combo3_0011_1111));
assign r_02_b[2] = (~(dcd_010 & combo3_1000_0000));
assign r_02_b[3] = (~(dcd_011 & combo3_0001_1111));
assign r_02_b[4] = (~(dcd_100 & tiup));
assign r_02_b[5] = (~(dcd_101 & combo3_1000_0000));
assign r_02_b[6] = (~(dcd_110 & tidn));
assign r_02_b[7] = (~(dcd_111 & tidn));
assign r[2] = (~(r_02_b[0] & r_02_b[1] & r_02_b[2] & r_02_b[3] & r_02_b[4] & r_02_b[5] & r_02_b[6] & r_02_b[7]));
assign r_03_b[0] = (~(dcd_000 & combo3_1100_1110));
assign r_03_b[1] = (~(dcd_001 & combo3_0011_1000));
assign r_03_b[2] = (~(dcd_010 & combo3_0111_1000));
assign r_03_b[3] = (~(dcd_011 & combo3_0001_1111));
assign r_03_b[4] = (~(dcd_100 & combo3_1000_0000));
assign r_03_b[5] = (~(dcd_101 & combo3_0111_1111));
assign r_03_b[6] = (~(dcd_110 & combo3_1100_0000));
assign r_03_b[7] = (~(dcd_111 & tidn));
assign r[3] = (~(r_03_b[0] & r_03_b[1] & r_03_b[2] & r_03_b[3] & r_03_b[4] & r_03_b[5] & r_03_b[6] & r_03_b[7]));
assign r_04_b[0] = (~(dcd_000 & combo3_1010_1101));
assign r_04_b[1] = (~(dcd_001 & combo3_0010_0110));
assign r_04_b[2] = (~(dcd_010 & combo3_0110_0111));
assign r_04_b[3] = (~(dcd_011 & combo3_0001_1000));
assign r_04_b[4] = (~(dcd_100 & combo3_0111_0000));
assign r_04_b[5] = (~(dcd_101 & combo3_0111_1000));
assign r_04_b[6] = (~(dcd_110 & combo3_0011_1111));
assign r_04_b[7] = (~(dcd_111 & combo3_1000_0000));
assign r[4] = (~(r_04_b[0] & r_04_b[1] & r_04_b[2] & r_04_b[3] & r_04_b[4] & r_04_b[5] & r_04_b[6] & r_04_b[7]));
assign r_05_b[0] = (~(dcd_000 & combo3_1111_1001));
assign r_05_b[1] = (~(dcd_001 & combo3_1011_0101));
assign r_05_b[2] = (~(dcd_010 & combo3_0101_0110));
assign r_05_b[3] = (~(dcd_011 & combo3_1001_0110));
assign r_05_b[4] = (~(dcd_100 & combo3_0110_1100));
assign r_05_b[5] = (~(dcd_101 & combo3_0110_0111));
assign r_05_b[6] = (~(dcd_110 & combo3_0011_1000));
assign r_05_b[7] = (~(dcd_111 & combo3_0111_0000));
assign r[5] = (~(r_05_b[0] & r_05_b[1] & r_05_b[2] & r_05_b[3] & r_05_b[4] & r_05_b[5] & r_05_b[6] & r_05_b[7]));
assign r_06_b[0] = (~(dcd_000 & combo3_0001_1010));
assign r_06_b[1] = (~(dcd_001 & combo3_1101_1110));
assign r_06_b[2] = (~(dcd_010 & combo3_0011_1100));
assign r_06_b[3] = (~(dcd_011 & combo3_0100_1101));
assign r_06_b[4] = (~(dcd_100 & combo3_0100_1010));
assign r_06_b[5] = (~(dcd_101 & combo3_0101_0100));
assign r_06_b[6] = (~(dcd_110 & combo3_1011_0110));
assign r_06_b[7] = (~(dcd_111 & combo3_0100_1100));
assign r[6] = (~(r_06_b[0] & r_06_b[1] & r_06_b[2] & r_06_b[3] & r_06_b[4] & r_06_b[5] & r_06_b[6] & r_06_b[7]));
assign r_07_b[0] = (~(dcd_000 & combo3_0010_1101));
assign r_07_b[1] = (~(dcd_001 & combo3_1001_1001));
assign r_07_b[2] = (~(dcd_010 & combo3_1100_0100));
assign r_07_b[3] = (~(dcd_011 & combo3_1001_0110));
assign r_07_b[4] = (~(dcd_100 & combo3_0001_1111));
assign r_07_b[5] = (~(dcd_101 & combo3_0000_1110));
assign r_07_b[6] = (~(dcd_110 & combo3_0110_1101));
assign r_07_b[7] = (~(dcd_111 & combo3_0110_1010));
assign r[7] = (~(r_07_b[0] & r_07_b[1] & r_07_b[2] & r_07_b[3] & r_07_b[4] & r_07_b[5] & r_07_b[6] & r_07_b[7]));
assign r_08_b[0] = (~(dcd_000 & combo3_0000_0010));
assign r_08_b[1] = (~(dcd_001 & combo3_1011_0101));
assign r_08_b[2] = (~(dcd_010 & combo3_1100_1001));
assign r_08_b[3] = (~(dcd_011 & combo3_1100_1101));
assign r_08_b[4] = (~(dcd_100 & combo3_1001_1111));
assign r_08_b[5] = (~(dcd_101 & combo3_0001_0010));
assign r_08_b[6] = (~(dcd_110 & combo3_1011_0110));
assign r_08_b[7] = (~(dcd_111 & combo3_0011_1111));
assign r[8] = (~(r_08_b[0] & r_08_b[1] & r_08_b[2] & r_08_b[3] & r_08_b[4] & r_08_b[5] & r_08_b[6] & r_08_b[7]));
assign r_09_b[0] = (~(dcd_000 & combo3_0100_1010));
assign r_09_b[1] = (~(dcd_001 & combo3_0011_0001));
assign r_09_b[2] = (~(dcd_010 & combo3_1101_1101));
assign r_09_b[3] = (~(dcd_011 & combo3_1100_0111));
assign r_09_b[4] = (~(dcd_100 & combo3_0101_1111));
assign r_09_b[5] = (~(dcd_101 & combo3_0010_0111));
assign r_09_b[6] = (~(dcd_110 & combo3_1110_1101));
assign r_09_b[7] = (~(dcd_111 & combo3_0011_0000));
assign r[9] = (~(r_09_b[0] & r_09_b[1] & r_09_b[2] & r_09_b[3] & r_09_b[4] & r_09_b[5] & r_09_b[6] & r_09_b[7]));
assign r_10_b[0] = (~(dcd_000 & combo3_0111_1010));
assign r_10_b[1] = (~(dcd_001 & combo3_0011_1011));
assign r_10_b[2] = (~(dcd_010 & combo3_0001_0111));
assign r_10_b[3] = (~(dcd_011 & combo3_1101_0111));
assign r_10_b[4] = (~(dcd_100 & combo3_0001_0001));
assign r_10_b[5] = (~(dcd_101 & combo3_0111_0110));
assign r_10_b[6] = (~(dcd_110 & combo3_0110_0111));
assign r_10_b[7] = (~(dcd_111 & combo3_1010_1000));
assign r[10] = (~(r_10_b[0] & r_10_b[1] & r_10_b[2] & r_10_b[3] & r_10_b[4] & r_10_b[5] & r_10_b[6] & r_10_b[7]));
assign r_11_b[0] = (~(dcd_000 & combo3_0000_1111));
assign r_11_b[1] = (~(dcd_001 & combo3_0101_0100));
assign r_11_b[2] = (~(dcd_010 & combo3_1110_1101));
assign r_11_b[3] = (~(dcd_011 & combo3_0001_0101));
assign r_11_b[4] = (~(dcd_100 & combo3_1010_1000));
assign r_11_b[5] = (~(dcd_101 & combo3_0111_1101));
assign r_11_b[6] = (~(dcd_110 & combo3_1011_0100));
assign r_11_b[7] = (~(dcd_111 & combo3_1000_0100));
assign r[11] = (~(r_11_b[0] & r_11_b[1] & r_11_b[2] & r_11_b[3] & r_11_b[4] & r_11_b[5] & r_11_b[6] & r_11_b[7]));
assign r_12_b[0] = (~(dcd_000 & combo3_1100_1111));
assign r_12_b[1] = (~(dcd_001 & combo3_0110_1011));
assign r_12_b[2] = (~(dcd_010 & combo3_0100_1000));
assign r_12_b[3] = (~(dcd_011 & combo3_0111_1011));
assign r_12_b[4] = (~(dcd_100 & combo3_1101_0110));
assign r_12_b[5] = (~(dcd_101 & combo3_0001_0001));
assign r_12_b[6] = (~(dcd_110 & combo3_1011_0011));
assign r_12_b[7] = (~(dcd_111 & combo3_0100_0000));
assign r[12] = (~(r_12_b[0] & r_12_b[1] & r_12_b[2] & r_12_b[3] & r_12_b[4] & r_12_b[5] & r_12_b[6] & r_12_b[7]));
assign r_13_b[0] = (~(dcd_000 & combo3_0101_0001));
assign r_13_b[1] = (~(dcd_001 & combo3_0011_1100));
assign r_13_b[2] = (~(dcd_010 & combo3_0101_1011));
assign r_13_b[3] = (~(dcd_011 & combo3_0001_1000));
assign r_13_b[4] = (~(dcd_100 & combo3_0110_0010));
assign r_13_b[5] = (~(dcd_101 & combo3_1101_0100));
assign r_13_b[6] = (~(dcd_110 & combo3_0100_0011));
assign r_13_b[7] = (~(dcd_111 & combo3_1000_1010));
assign r[13] = (~(r_13_b[0] & r_13_b[1] & r_13_b[2] & r_13_b[3] & r_13_b[4] & r_13_b[5] & r_13_b[6] & r_13_b[7]));
assign r_14_b[0] = (~(dcd_000 & combo3_1000_0000));
assign r_14_b[1] = (~(dcd_001 & tidn));
assign r_14_b[2] = (~(dcd_010 & tidn));
assign r_14_b[3] = (~(dcd_011 & tidn));
assign r_14_b[4] = (~(dcd_100 & tidn));
assign r_14_b[5] = (~(dcd_101 & tidn));
assign r_14_b[6] = (~(dcd_110 & tidn));
assign r_14_b[7] = (~(dcd_111 & tidn));
assign r[14] = (~(r_14_b[0] & r_14_b[1] & r_14_b[2] & r_14_b[3] & r_14_b[4] & r_14_b[5] & r_14_b[6] & r_14_b[7]));
////#######################################
////## RENUMBERING OUTPUTS
////#######################################
assign est[1:20] = e[0:19]; // renumbering
assign rng[6:20] = r[0:14]; // renumbering
endmodule |
module iuq_bd(
instruction,
instruction_next,
branch_decode,
bp_bc_en,
bp_bclr_en,
bp_bcctr_en,
bp_sw_en
);
//parameter `GPR_WIDTH = 64;
`include "tri_a2o.vh"
(* analysis_not_referenced="<12:20>true" *)
input [0:31] instruction;
(* analysis_not_referenced="<6:7>,<9:10>,<14:20>,<31>true" *)
input [0:31] instruction_next;
output [0:3] branch_decode;
input bp_bc_en;
input bp_bclr_en;
input bp_bcctr_en;
input bp_sw_en;
wire [1:12] MICROCODE_PT;
wire core64;
wire to_uc;
//architecture iuq_bd of iuq_bd is
wire b;
wire bc;
wire bclr;
wire bcctr;
wire bctar;
wire br_val;
wire [0:4] bo;
wire hint;
wire hint_val;
wire cmpi;
wire cmpli;
wire cmp;
wire cmpl;
wire [0:2] bf;
wire next_bc;
wire next_bclr;
wire next_bcctr;
wire next_bctar;
wire [0:2] next_bi;
wire next_ctr;
wire fuse_val;
//@@ START OF EXECUTABLE CODE FOR IUQ_BD
//begin
assign b = instruction[0:5] == 6'b010010;
assign bc = bp_bc_en & instruction[0:5] == 6'b010000;
assign bclr = bp_bclr_en & instruction[0:5] == 6'b010011 & instruction[21:30] == 10'b0000010000;
assign bcctr = bp_bcctr_en & instruction[0:5] == 6'b010011 & instruction[21:30] == 10'b1000010000;
assign bctar = bp_bcctr_en & instruction[0:5] == 6'b010011 & instruction[21:30] == 10'b1000110000;
assign br_val = b | bc | bclr | bcctr | bctar;
assign bo[0:4] = instruction[6:10];
assign hint_val = (bo[0] & bo[2]) | (bp_sw_en & ((bo[0] == 1'b0 & bo[2] == 1'b1 & bo[3] == 1'b1) | (bo[0] == 1'b1 & bo[2] == 1'b0 & bo[1] == 1'b1)));
assign hint = (bo[0] & bo[2]) | bo[4];
assign branch_decode[0:3] = {br_val, (b | to_uc), ((br_val & hint_val) | fuse_val), hint};
//------------------
// fusion predecode
//------------------
assign cmpi = instruction[0:5] == 6'b001011;
assign cmpli = instruction[0:5] == 6'b001010;
assign cmp = instruction[0:5] == 6'b011111 & instruction[21:30] == 10'b0000000000;
assign cmpl = instruction[0:5] == 6'b011111 & instruction[21:30] == 10'b0000100000;
assign bf[0:2] = instruction[6:8];
assign next_bc = instruction_next[0:5] == 6'b010000;
assign next_bclr = instruction_next[0:5] == 6'b010011 & instruction_next[21:30] == 10'b0000010000;
assign next_bcctr = instruction_next[0:5] == 6'b010011 & instruction_next[21:30] == 10'b1000010000;
assign next_bctar = instruction_next[0:5] == 6'b010011 & instruction_next[21:30] == 10'b1000110000;
assign next_bi[0:2] = instruction_next[11:13];
assign next_ctr = instruction_next[8] == 1'b0;
//remove update LR cases for now
assign fuse_val = (bf[0:2] == next_bi[0:2]) & (((cmpi | cmpli) & (next_bc | next_bcctr | ((next_bclr | next_bctar) & (~next_ctr)))) | ((cmp | cmpl) & (((next_bc) & (~next_ctr)))));
//------------------
// ucode predecode
//------------------
//64-bit core
generate
if (`GPR_WIDTH == 64)
begin : c64
assign core64 = 1'b1;
end
endgenerate
//32-bit core
generate
if (`GPR_WIDTH == 32)
begin : c32
assign core64 = 1'b0;
end
endgenerate
/*
//table_start
?TABLE microcode LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET);
*INPUTS*=====================*OUTPUTS*==*
| | |
| core64 | |
| | | |
| | instruction | to_uc |
| | | instruction | | |
| | | | instruction | | |
| | | | | | | |
| | | 1 22222222233 | | |
| | 012345 1 12345678901 | | |
*TYPE*=======================+==========+
| S PPPPPP P PPPPPPPPPPP | S |
*TERMS*======================+==========+
| . 100011 . ........... | 1 | lbzu
| . 011111 . 0001110111. | 1 | lbzux
| 1 111010 . .........01 | 1 | ldu
| 1 011111 . 0000110101. | 1 | ldux
| . 101011 . ........... | 1 | lhau
| . 011111 . 0101110111. | 1 | lhaux
| . 101001 . ........... | 1 | lhzu
| . 011111 . 0100110111. | 1 | lhzux
| . 101110 . ........... | 1 | lmw
| . 011111 . 1001010101. | 1 | lswi
| . 011111 . 1000010101. | 1 | lswx
| 1 011111 . 0101110101. | 1 | lwaux
| . 100001 . ........... | 1 | lwzu
| . 011111 . 0000110111. | 1 | lwzux
| . 110001 . ........... | 1 | lfsu
| . 011111 . 1000110111. | 1 | lfsux
| . 110011 . ........... | 1 | lfdu
| . 011111 . 1001110111. | 1 | lfdux
| . 011111 . 1000000000. | 1 | mcrxr
| . 011111 0 0000010011. | 1 | mfcr
| . 011111 0 0010010000. | 1 | mtcrf
| . 101111 . ........... | 1 | stmw
| . 011111 . 1011010101. | 1 | stswi
| . 011111 . 1010010101. | 1 | stswx
*END*========================+==========+
?TABLE END microcode ;
//table_end
*/
//assign_start
//
// Final Table Listing
// *INPUTS*=====================*OUTPUTS*==*
// | | |
// | core64 | |
// | | | |
// | | instruction | to_uc |
// | | | instruction | | |
// | | | | instruction | | |
// | | | | | | | |
// | | | 1 22222222233 | | |
// | | 012345 1 12345678901 | | |
// *TYPE*=======================+==========+
// | S PPPPPP P PPPPPPPPPPP | S |
// *POLARITY*------------------>| + |
// *PHASE*--------------------->| T |
// *TERMS*======================+==========+
// 1 | - 011111 0 0010010000- | 1 |
// 2 | - 011111 - 1000000000- | 1 |
// 3 | 1 011111 - 01011101-1- | 1 |
// 4 | - 011111 0 0000010011- | 1 |
// 5 | 1 011111 - 00001101-1- | 1 |
// 6 | - 011111 - 10--010101- | 1 |
// 7 | - 011111 - 0-0-110111- | 1 |
// 8 | - 011111 - -00-110111- | 1 |
// 9 | 1 111010 - ---------01 | 1 |
// 10 | - 1-00-1 - ----------- | 1 |
// 11 | - 10-0-1 - ----------- | 1 |
// 12 | - 10111- - ----------- | 1 |
// *=======================================*
//
// Table MICROCODE Signal Assignments for Product Terms
assign MICROCODE_PT[1] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[11], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 17'b01111100010010000);
assign MICROCODE_PT[2] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 16'b0111111000000000);
assign MICROCODE_PT[3] = (({core64, instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[30]}) === 16'b1011111010111011);
assign MICROCODE_PT[4] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[11], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 17'b01111100000010011);
assign MICROCODE_PT[5] = (({core64, instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[30]}) === 16'b1011111000011011);
assign MICROCODE_PT[6] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 14'b01111110010101);
assign MICROCODE_PT[7] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[23], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 14'b01111100110111);
assign MICROCODE_PT[8] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[22], instruction[23], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 14'b01111100110111);
assign MICROCODE_PT[9] = (({core64, instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[30], instruction[31]}) === 9'b111101001);
assign MICROCODE_PT[10] = (({instruction[0], instruction[2], instruction[3], instruction[5]}) === 4'b1001);
assign MICROCODE_PT[11] = (({instruction[0], instruction[1], instruction[3], instruction[5]}) === 4'b1001);
assign MICROCODE_PT[12] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4]}) === 5'b10111);
// Table MICROCODE Signal Assignments for Outputs
assign to_uc = (MICROCODE_PT[1] | MICROCODE_PT[2] | MICROCODE_PT[3] | MICROCODE_PT[4] | MICROCODE_PT[5] | MICROCODE_PT[6] | MICROCODE_PT[7] | MICROCODE_PT[8] | MICROCODE_PT[9] | MICROCODE_PT[10] | MICROCODE_PT[11] | MICROCODE_PT[12]);
//assign_end
endmodule |
module iuq_uc_buffer(
vdd,
gnd,
nclk,
pc_iu_func_sl_thold_0_b,
pc_iu_sg_0,
force_t,
d_mode,
delay_lclkr,
mpw1_b,
mpw2_b,
scan_in,
scan_out,
iu3_val_l2,
iu3_ifar_l2,
iu3_2ucode_l2,
iu3_0_instr_l2,
iu3_1_instr_l2,
iu3_2_instr_l2,
iu3_3_instr_l2,
ic_bp_iu2_flush,
ic_bp_iu3_flush,
ic_bp_iu3_ecc_err,
bp_ib_iu3_val,
uc_ib_iu3_invalid,
uc_ib_iu3_flush_all,
uc_ic_hold,
uc_iu4_flush,
uc_iu4_flush_ifar,
xu_iu_flush,
uc_val,
advance_buffers,
br_hold_l2,
cplbuffer_full,
clear_ill_flush_2ucode,
next_valid,
next_instr,
iu2_flush,
flush_next,
flush_current
);
inout vdd;
inout gnd;
(* pin_data ="PIN_FUNCTION=/G_CLK/" *)
input [0:`NCLK_WIDTH-1] nclk;
input pc_iu_func_sl_thold_0_b;
input pc_iu_sg_0;
input force_t;
input d_mode;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
(* pin_data ="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in;
(* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out;
input [0:3] iu3_val_l2;
input [62-`EFF_IFAR_WIDTH:61] iu3_ifar_l2;
input iu3_2ucode_l2; // Only iu3_0_instr0 can ever be 2ucode because xu_iu_flush clears everything before it.
input [0:33] iu3_0_instr_l2;
input [0:33] iu3_1_instr_l2;
input [0:33] iu3_2_instr_l2;
input [0:33] iu3_3_instr_l2;
input ic_bp_iu2_flush;
input ic_bp_iu3_flush;
input ic_bp_iu3_ecc_err;
input [0:3] bp_ib_iu3_val;
output [0:3] uc_ib_iu3_invalid; // IB uses this to mask off the valids
output uc_ib_iu3_flush_all; // IB uses this to clear buffer (because not enough time to get into iu3_invalid)
output uc_ic_hold;
output uc_iu4_flush;
output [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar;
input xu_iu_flush;
// Internal to microcode
input uc_val;
input advance_buffers;
input br_hold_l2;
input cplbuffer_full;
input clear_ill_flush_2ucode;
output next_valid; // Does not include flush
output [0:31] next_instr;
output iu2_flush; // Does not include XU flush
output flush_next; // Includes XU flush
output flush_current; // Includes XU flush
parameter uc_ic_hold_offset = 0;
parameter uc_iu4_flush_offset = uc_ic_hold_offset + 1;
parameter uc_iu4_flush_ifar_offset = uc_iu4_flush_offset + 1;
parameter buffer_valid_offset = uc_iu4_flush_ifar_offset + `EFF_IFAR_WIDTH;
parameter buffer1_offset = buffer_valid_offset + 4; //buffer0_offset + 2;
parameter buffer2_offset = buffer1_offset + 32;
parameter buffer3_offset = buffer2_offset + 32;
parameter buffer4_offset = buffer3_offset + 32;
parameter scan_right = buffer4_offset + 32 - 1; //buffer_stg_iu4_offset + 5 - 1;
// Latches
wire uc_ic_hold_d;
wire uc_iu4_flush_d;
wire [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar_d;
wire [1:4] buffer_valid_d;
wire [0:31] buffer1_d;
wire [0:31] buffer2_d;
wire [0:31] buffer3_d;
wire [0:31] buffer4_d;
wire uc_ic_hold_l2;
wire uc_iu4_flush_l2;
wire [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar_l2;
wire [1:4] buffer_valid_l2;
wire [0:31] buffer1_l2;
wire [0:31] buffer2_l2;
wire [0:31] buffer3_l2;
wire [0:31] buffer4_l2;
wire [0:3] new_ucode_in;
wire uc_buffer_act;
wire uc_stall;
// Left shift incoming microcode instructions
wire [0:3] ucode_and_bp_in;
wire [0:3] valid_in;
wire [0:3] early_val_in;
wire [0:31] instr0_in;
wire [0:31] instr1_in;
wire [0:31] instr2_in;
wire [0:31] instr3_in;
wire [60:61] ic_ifar0;
wire [60:61] ic_ifar1;
wire [60:61] ic_ifar2;
wire [60:61] ic_ifar3;
wire [60:61] ifar0_in;
wire [60:61] ifar1_in;
wire [60:61] ifar2_in;
wire [60:61] ifar3_in;
// Flushes
wire iu3_flush;
wire [0:3] early_need_flush_instr_in;
wire [0:3] need_flush_instr_in;
wire [60:61] overflow_flush_ifar;
wire [0:3] imask0_in;
wire [0:3] imask1_in;
wire [0:3] imask2_in;
wire [0:3] imask3_in;
wire [0:3] uc_iu3_flush_imask;
// Buffer
wire bp_flush_next;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
//tidn <= '0';
//tiup <= '1';
assign new_ucode_in[0] = iu3_val_l2[0] & ((iu3_0_instr_l2[32:33] == 2'b01) | iu3_2ucode_l2);
assign new_ucode_in[1] = iu3_val_l2[1] & (iu3_1_instr_l2[32:33] == 2'b01);
assign new_ucode_in[2] = iu3_val_l2[2] & (iu3_2_instr_l2[32:33] == 2'b01);
assign new_ucode_in[3] = iu3_val_l2[3] & (iu3_3_instr_l2[32:33] == 2'b01);
// default act signal
assign uc_buffer_act = uc_val | buffer_valid_l2[1] | (|(new_ucode_in)) | uc_iu4_flush_l2;
// stall if processing command in buffer0 or commands are being held off. When current command finishes,
// buffer0 takes next command when uc_end, but Buffers need to latch info
// and advance next cycle because we cannot make timing (ib_uc_rdy comes late)
// This means buffer0 can have same command as buffer1 for a cycle
assign uc_stall = (uc_val | br_hold_l2 | cplbuffer_full) & (~advance_buffers);
//---------------------------------------------------------------------
// left shift incoming microcode instructions
//---------------------------------------------------------------------
//Detect if redirected by BP
assign ucode_and_bp_in = new_ucode_in & bp_ib_iu3_val;
assign valid_in[0] = |(ucode_and_bp_in);
assign valid_in[1] = (~(( ucode_and_bp_in[0:2] == 3'b000) |
(({ucode_and_bp_in[0:1], ucode_and_bp_in[3]}) == 3'b000) |
(({ucode_and_bp_in[0], ucode_and_bp_in[2:3]}) == 3'b000) |
( ucode_and_bp_in[1:3] == 3'b000))); // not 0000,0001,0010,0100,1000
assign valid_in[2] = ( ucode_and_bp_in[0:2] == 3'b111) |
({ucode_and_bp_in[0:1], ucode_and_bp_in[3]} == 3'b111) |
({ucode_and_bp_in[0], ucode_and_bp_in[2:3]} == 3'b111) |
( ucode_and_bp_in[1:3] == 3'b111); // 1111,1110,1101,1011,0111
assign valid_in[3] = ucode_and_bp_in == 4'b1111;
// This early signal does not include BP val, and is used for IB invalidate
assign early_val_in[0] = |(new_ucode_in);
assign early_val_in[1] = (~(( new_ucode_in[0:2] == 3'b000) |
({new_ucode_in[0:1], new_ucode_in[3]} == 3'b000) |
({new_ucode_in[0], new_ucode_in[2:3]} == 3'b000) |
( new_ucode_in[1:3] == 3'b000))); // not 0000,0001,0010,0100,1000
assign early_val_in[2] = ( new_ucode_in[0:2] == 3'b111) |
({new_ucode_in[0:1], new_ucode_in[3]} == 3'b111) |
({new_ucode_in[0], new_ucode_in[2:3]} == 3'b111) |
( new_ucode_in[1:3] == 3'b111); // 1111,1110,1101,1011,0111
assign early_val_in[3] = new_ucode_in == 4'b1111;
assign instr0_in = (new_ucode_in[0] == 1'b1) ? iu3_0_instr_l2[0:31] : // 1---
(new_ucode_in[1] == 1'b1) ? iu3_1_instr_l2[0:31] : // 01--
(new_ucode_in[2] == 1'b1) ? iu3_2_instr_l2[0:31] : // 001-
iu3_3_instr_l2[0:31];
assign instr1_in = (new_ucode_in[0:1] == 2'b11) ? iu3_1_instr_l2[0:31] : // 11--
(((new_ucode_in[0:2] == 3'b011) | // 011-
(new_ucode_in[0:2] == 3'b101))) ? iu3_2_instr_l2[0:31] : // 101-
iu3_3_instr_l2[0:31];
assign instr2_in = (new_ucode_in[0:2] == 3'b111) ? iu3_2_instr_l2[0:31] : // 111-
iu3_3_instr_l2[0:31];
assign instr3_in = iu3_3_instr_l2[0:31];
assign ic_ifar0 = iu3_ifar_l2[60:61];
assign ic_ifar1 = (iu3_ifar_l2[60:61] == 2'b00) ? 2'b01 :
(iu3_ifar_l2[60:61] == 2'b01) ? 2'b10 :
2'b11;
assign ic_ifar2 = {(~iu3_ifar_l2[60]), iu3_ifar_l2[61]};
assign ic_ifar3 = 2'b11;
assign ifar0_in = (new_ucode_in[0] == 1'b1) ? ic_ifar0 : // 1---
(new_ucode_in[1] == 1'b1) ? ic_ifar1 : // 01--
(new_ucode_in[2] == 1'b1) ? ic_ifar2 : // 001-
ic_ifar3;
assign ifar1_in = (new_ucode_in[0:1] == 2'b11) ? ic_ifar1 : // 11--
(((new_ucode_in[0:2] == 3'b011) | // 011-
(new_ucode_in[0:2] == 3'b101))) ? ic_ifar2 : // 101-
ic_ifar3;
assign ifar2_in = (new_ucode_in[0:2] == 3'b111) ? ic_ifar2 : // 111-
ic_ifar3;
assign ifar3_in = ic_ifar3;
//---------------------------------------------------------------------
// Flushes
//---------------------------------------------------------------------
// Does not include xu_iu_flush (for timing)
assign iu3_flush = ic_bp_iu3_flush | uc_iu4_flush_l2 | ic_bp_iu3_ecc_err;
assign iu2_flush = ic_bp_iu3_flush | uc_iu4_flush_l2 | (|(need_flush_instr_in)) | ic_bp_iu2_flush;
// Need UC flush if overflowing buffer
// early signal does not check BP val
assign early_need_flush_instr_in = ((early_val_in[0] & buffer_valid_l2[4] & uc_stall) == 1'b1) ? 4'b1000 :
((early_val_in[1] & ((buffer_valid_l2[3] & uc_stall) | (buffer_valid_l2[4] & (~uc_stall)))) == 1'b1) ? 4'b0100 :
((early_val_in[2] & ((buffer_valid_l2[2] & uc_stall) | (buffer_valid_l2[3] & (~uc_stall)))) == 1'b1) ? 4'b0010 :
((early_val_in[3] & ((buffer_valid_l2[1] & uc_stall) | (buffer_valid_l2[2] & (~uc_stall)))) == 1'b1) ? 4'b0001 :
4'b0000;
assign need_flush_instr_in = early_need_flush_instr_in & valid_in;
assign overflow_flush_ifar[60:61] = (ifar0_in & {2{need_flush_instr_in[0]}}) |
(ifar1_in & {2{need_flush_instr_in[1]}}) |
(ifar2_in & {2{need_flush_instr_in[2]}}) |
(ifar3_in & {2{need_flush_instr_in[3]}});
assign uc_iu4_flush_ifar_d[62 - `EFF_IFAR_WIDTH:59] = iu3_ifar_l2[62 - `EFF_IFAR_WIDTH:59];
assign uc_iu4_flush_ifar_d[60:61] = clear_ill_flush_2ucode ? ifar0_in :
overflow_flush_ifar;
// Which of the 4 instructions was flushed
assign imask0_in = (new_ucode_in[0] == 1'b1) ? 4'b1111 : // 1---
(new_ucode_in[1] == 1'b1) ? 4'b0111 : // 01--
(new_ucode_in[2] == 1'b1) ? 4'b0011 : // 001-
4'b0001;
assign imask1_in = (new_ucode_in[0:1] == 2'b11) ? 4'b0111 : // 11--
(((new_ucode_in[0:2] == 3'b011) | // 011-
(new_ucode_in[0:2] == 3'b101))) ? 4'b0011 : // 101-
4'b0001;
assign imask2_in = (new_ucode_in[0:2] == 3'b111) ? 4'b0011 : // 111-
4'b0001;
assign imask3_in = 4'b0001;
assign uc_iu3_flush_imask = (imask0_in & {4{early_need_flush_instr_in[0]}}) |
(imask1_in & {4{early_need_flush_instr_in[1]}}) |
(imask2_in & {4{early_need_flush_instr_in[2]}}) |
(imask3_in & {4{early_need_flush_instr_in[3]}});
assign uc_ib_iu3_invalid = uc_iu3_flush_imask | {4{uc_iu4_flush_l2}};
assign uc_iu4_flush_d = (|(need_flush_instr_in) | clear_ill_flush_2ucode) & (~iu3_flush) & (~xu_iu_flush);
assign uc_ib_iu3_flush_all = clear_ill_flush_2ucode & (~iu3_flush);
// Detect IB flush
// Simpler to wait until IU4 because BP flush is IU3 & IU4
// (old)IB flush should take precedence over UC flush in IC because we invalidated UC flushes in IU3
// UC flush should take precedence over BP flush in IC because we checked BP valids in IU3
assign uc_iu4_flush = uc_iu4_flush_l2;
assign uc_iu4_flush_ifar = uc_iu4_flush_ifar_l2;
assign uc_ic_hold_d = (buffer_valid_d[4] == 1'b0) ? 1'b0 :
(uc_iu4_flush_l2 == 1'b1) ? 1'b1 :
uc_ic_hold_l2;
assign uc_ic_hold = uc_ic_hold_l2;
//---------------------------------------------------------------------
// Buffers
//---------------------------------------------------------------------
// Buffer0 is the instruction that UC is currently working on
assign next_instr = (buffer_valid_l2[2] == 1'b1 & advance_buffers == 1'b1) ? buffer2_l2[0:31] :
(buffer_valid_l2[1] == 1'b1 & advance_buffers == 1'b0) ? buffer1_l2[0:31] :
instr0_in;
// Note: buffer0 could be taking buffer2 info next cycle, but we never can get an ib_flush on buffer0
// in that scenario
// ??? Do I want to switch ordering so bufferX_l2 is default case? (save power/toggling)
assign buffer1_d = (uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b1) ? buffer1_l2 :
(uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b1) ? buffer2_l2 :
(uc_stall == 1'b0 & buffer_valid_l2[1] == 1'b0) ? instr1_in :
instr0_in;
assign buffer2_d = (uc_stall == 1'b1 & buffer_valid_l2[2] == 1'b1) ? buffer2_l2 :
(uc_stall == 1'b0 & buffer_valid_l2[3] == 1'b1) ? buffer3_l2 :
(uc_stall == 1'b0 & buffer_valid_l2[1] == 1'b0) ? instr2_in :
(uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b0) ? instr1_in :
(uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b0) ? instr1_in :
instr0_in;
assign buffer3_d = (uc_stall == 1'b1 & buffer_valid_l2[3] == 1'b1) ? buffer3_l2 :
(uc_stall == 1'b0 & buffer_valid_l2[4] == 1'b1) ? buffer4_l2 :
(uc_stall == 1'b0 & buffer_valid_l2[1] == 1'b0) ? instr3_in :
(uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b0) ? instr2_in :
(uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b0) ? instr2_in :
(uc_stall == 1'b1 & buffer_valid_l2[2] == 1'b0) ? instr1_in :
(uc_stall == 1'b0 & buffer_valid_l2[3] == 1'b0) ? instr1_in :
instr0_in;
assign buffer4_d = (uc_stall == 1'b1 & buffer_valid_l2[4] == 1'b1) ? buffer4_l2 :
(uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b0) ? instr3_in :
(uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b0) ? instr3_in :
(uc_stall == 1'b1 & buffer_valid_l2[2] == 1'b0) ? instr2_in :
(uc_stall == 1'b0 & buffer_valid_l2[3] == 1'b0) ? instr2_in :
(uc_stall == 1'b1 & buffer_valid_l2[3] == 1'b0) ? instr1_in :
(uc_stall == 1'b0 & buffer_valid_l2[4] == 1'b0) ? instr1_in :
instr0_in;
// Output is never in IU4 now that we latch incoming IU2 signals
assign bp_flush_next = (|(new_ucode_in)) & (~valid_in[0]);
assign flush_current = xu_iu_flush; // Current instruction flushed
assign flush_next = ((~((buffer_valid_l2[2] & advance_buffers) | (buffer_valid_l2[1] & (~advance_buffers)))) & (iu3_flush | bp_flush_next)) | xu_iu_flush;
assign next_valid = (buffer_valid_l2[2] & advance_buffers) |
(buffer_valid_l2[1] & (~advance_buffers)) |
(|(new_ucode_in)); // Does not include flush
assign buffer_valid_d[1] = ((buffer_valid_l2[1] & uc_stall) |
buffer_valid_l2[2] |
(((valid_in[1]) |
(valid_in[0] & buffer_valid_l2[1]) |
(uc_stall & valid_in[0])) & (~iu3_flush)))
& (~xu_iu_flush);
assign buffer_valid_d[2] = ((buffer_valid_l2[2] & uc_stall) |
buffer_valid_l2[3] |
(((valid_in[2]) |
(valid_in[1] & buffer_valid_l2[1]) |
(valid_in[0] & buffer_valid_l2[2]) |
(uc_stall & (valid_in[1] |
(valid_in[0] & buffer_valid_l2[1])))) & (~iu3_flush)))
& (~xu_iu_flush);
assign buffer_valid_d[3] = ((buffer_valid_l2[3] & uc_stall) |
buffer_valid_l2[4] |
(((valid_in[3]) |
(valid_in[2] & buffer_valid_l2[1]) |
(valid_in[1] & buffer_valid_l2[2]) |
(valid_in[0] & buffer_valid_l2[3]) |
(uc_stall & (valid_in[2] |
(valid_in[1] & buffer_valid_l2[1]) |
(valid_in[0] & buffer_valid_l2[2])))) & (~iu3_flush)))
& (~xu_iu_flush);
assign buffer_valid_d[4] = ((buffer_valid_l2[4] & uc_stall) |
(((valid_in[3] & buffer_valid_l2[1]) |
(valid_in[2] & buffer_valid_l2[2]) |
(valid_in[1] & buffer_valid_l2[3]) |
(valid_in[0] & buffer_valid_l2[4]) |
(uc_stall & (valid_in[3] |
(valid_in[2] & buffer_valid_l2[1]) |
(valid_in[1] & buffer_valid_l2[2]) |
(valid_in[0] & buffer_valid_l2[3])))) & (~iu3_flush)))
& (~xu_iu_flush);
//---------------------------------------------------------------------
// Latches
//---------------------------------------------------------------------
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uc_ic_hold_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(uc_buffer_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[uc_ic_hold_offset]),
.scout(sov[uc_ic_hold_offset]),
.din(uc_ic_hold_d),
.dout(uc_ic_hold_l2)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uc_iu4_flush_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(uc_buffer_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[uc_iu4_flush_offset]),
.scout(sov[uc_iu4_flush_offset]),
.din(uc_iu4_flush_d),
.dout(uc_iu4_flush_l2)
);
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) uc_iu4_flush_ifar_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(uc_iu4_flush_d),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[uc_iu4_flush_ifar_offset:uc_iu4_flush_ifar_offset + `EFF_IFAR_WIDTH - 1]),
.scout(sov[uc_iu4_flush_ifar_offset:uc_iu4_flush_ifar_offset + `EFF_IFAR_WIDTH - 1]),
.din(uc_iu4_flush_ifar_d),
.dout(uc_iu4_flush_ifar_l2)
);
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) buffer_valid_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(uc_buffer_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[buffer_valid_offset:buffer_valid_offset + 4 - 1]),
.scout(sov[buffer_valid_offset:buffer_valid_offset + 4 - 1]),
.din(buffer_valid_d),
.dout(buffer_valid_l2)
);
tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer1_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(uc_buffer_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[buffer1_offset:buffer1_offset + 32 - 1]),
.scout(sov[buffer1_offset:buffer1_offset + 32 - 1]),
.din(buffer1_d),
.dout(buffer1_l2)
);
tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer2_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(uc_buffer_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[buffer2_offset:buffer2_offset + 32 - 1]),
.scout(sov[buffer2_offset:buffer2_offset + 32 - 1]),
.din(buffer2_d),
.dout(buffer2_l2)
);
tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer3_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(uc_buffer_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[buffer3_offset:buffer3_offset + 32 - 1]),
.scout(sov[buffer3_offset:buffer3_offset + 32 - 1]),
.din(buffer3_d),
.dout(buffer3_l2)
);
tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer4_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(uc_buffer_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[buffer4_offset:buffer4_offset + 32 - 1]),
.scout(sov[buffer4_offset:buffer4_offset + 32 - 1]),
.din(buffer4_d),
.dout(buffer4_l2)
);
//---------------------------------------------------------------------
// Scan
//---------------------------------------------------------------------
assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
assign scan_out = sov[0];
endmodule |
module fu_lza_ej(
effsub,
sum,
car,
lzo_b,
edge_t
);
input effsub;
input [0:162] sum;
input [53:162] car;
input [0:162] lzo_b;
output [0:162] edge_t;
// generic 3 bit edge ::
// P G !Z
// P Z !G
// !P G !G
// !P Z !Z
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:52] x0;
wire [0:52] x1;
wire [0:52] x2;
wire [0:52] x1_b;
wire [0:52] ej_b;
wire [53:162] g_b;
wire [53:162] z;
wire [53:162] p;
wire [53:162] g;
wire [53:162] z_b;
wire [53:162] p_b;
wire sum_52_b;
wire lzo_54;
wire [55:162] gz;
wire [55:162] zg;
wire [55:162] gg;
wire [55:162] zz;
wire [53:162] e0_b;
wire [53:162] e1_b;
wire [54:54] e2_b;
wire unused;
// these are different heights for different bits ... place them as seperate columns
// for 0 :52
// for 53
// for 54
// for 55
// for 56:162
assign unused = g[54] | z_b[53] | z_b[162] | p_b[161] | p_b[162];
//-------------------------------------------
// (0:52) only one data input
//-------------------------------------------
assign x0[0:52] = {tidn, effsub, sum[0:50]}; // just a rename
assign x1[0:52] = {effsub, sum[0:51]}; // just a rename
assign x2[0:52] = sum[0:52]; // just a rename
assign x1_b[0:52] = (~x1[0:52]);
assign ej_b[0:52] = (~(x1_b[0:52] & (x0[0:52] | x2[0:52])));
assign edge_t[0:52] = (~(ej_b[0:52] & lzo_b[0:52]));
//-----------------------------------------------------------------
// (53) psuedo bit
//-----------------------------------------------------------------
assign g_b[53] = (~(sum[53] & car[53]));
assign z[53] = (~(sum[53] | car[53]));
assign p[53] = (sum[53] ^ car[53]);
assign g[53] = (~(g_b[53]));
assign z_b[53] = (~(z[53])); //UNUSED
assign p_b[53] = (~(p[53]));
assign sum_52_b = (~(sum[52]));
assign e0_b[53] = (~(sum[51] & sum_52_b));
assign e1_b[53] = (~(sum_52_b & g[53]));
assign edge_t[53] = (~(lzo_b[53] & e0_b[53] & e1_b[53])); //output
//-----------------------------------------------------------------
// (54) pseudo bit + 1
//-----------------------------------------------------------------
assign g_b[54] = (~(sum[54] & car[54]));
assign z[54] = (~(sum[54] | car[54]));
assign p[54] = (sum[54] ^ car[54]);
assign g[54] = (~(g_b[54])); //UNUSED
assign z_b[54] = (~(z[54]));
assign p_b[54] = (~(p[54]));
assign lzo_54 = (~lzo_b[54]);
assign e0_b[54] = (~(sum_52_b & p[53] & z_b[54])); //really is p54 (demotes to z54)
assign e1_b[54] = (~(sum[52] & p[53] & g_b[54])); //really is p54 (demotes to z54)
assign e2_b[54] = (~((sum[52] & z[53]) | lzo_54));
assign edge_t[54] = (~(e0_b[54] & e1_b[54] & e2_b[54])); //output
//-----------------------------------------------------------------
// (55) pseudo bit + 2
//-----------------------------------------------------------------
assign g_b[55] = (~(sum[55] & car[55]));
assign z[55] = (~(sum[55] | car[55]));
assign p[55] = (sum[55] ^ car[55]);
assign g[55] = (~(g_b[55]));
assign z_b[55] = (~(z[55]));
assign p_b[55] = (~(p[55]));
assign gz[55] = (~(g_b[54] | z[55]));
assign zg[55] = (~(z_b[54] | g[55]));
assign gg[55] = (~(g_b[54] | g[55]));
assign zz[55] = (~(z_b[54] | z[55]));
assign e1_b[55] = (~(p_b[53] & (gz[55] | zg[55]))); // P is flipped for psuedo bit
assign e0_b[55] = (~(p[53] & (gg[55] | zz[55]))); // P is flipped for psuedo bit
assign edge_t[55] = (~(e0_b[55] & e1_b[55] & lzo_b[55])); //output
//-----------------------------------------------------------------
// (56:162) normal 2 input edge_t
//-----------------------------------------------------------------
assign g_b[56:162] = (~(sum[56:162] & car[56:162]));
assign z[56:162] = (~(sum[56:162] | car[56:162]));
assign p[56:162] = (sum[56:162] ^ car[56:162]);
assign g[56:162] = (~(g_b[56:162]));
assign z_b[56:162] = (~(z[56:162])); //162 unused
assign p_b[56:162] = (~(p[56:162])); //161,162 unused
assign gz[56:162] = (~(g_b[55:161] | z[56:162]));
assign zg[56:162] = (~(z_b[55:161] | g[56:162]));
assign gg[56:162] = (~(g_b[55:161] | g[56:162]));
assign zz[56:162] = (~(z_b[55:161] | z[56:162]));
assign e1_b[56:162] = (~(p[54:160] & (gz[56:162] | zg[56:162])));
assign e0_b[56:162] = (~(p_b[54:160] & (gg[56:162] | zz[56:162])));
assign edge_t[56:162] = (~(e0_b[56:162] & e1_b[56:162] & lzo_b[56:162])); //output
endmodule |
module rv_decode(
instr,
is_brick,
brick_cycles
);
input [0:31] instr;
output is_brick;
output [0:2] brick_cycles;
//@@ Signal Declarations
wire [1:8] RV_INSTRUCTION_DECODER_PT;
wire [0:5] instr_0_5;
wire [0:10] instr_21_31;
(* analysis_not_referenced="true" *)
wire unused;
assign unused = |instr[6:20] | instr_21_31[10];
//@@ START OF EXECUTABLE CODE FOR RTL
assign instr_0_5 = instr[0:5];
assign instr_21_31 = instr[21:31];
//table_start
//?TABLE rv_instruction_decoder LISTING(final) OPTIMIZE PARMS(ON-SET);
//*INPUTS*===============*OUTPUTS*==========*
//| | |
//| instr_0_5 | is_brick |
//| | instr_21_31 | | brick_cycles |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | | | | |
//| | | 1 | | | |
//| 012345 01234567890 | | 012 |
//*TYPE*=================+==================+
//| SSSSSS SSSSSSSSSSS | P PPP | INSTR
//*TERMS*=*=*============+==================+
//| 000111 ........... | 1 000 | mulli 2
//| 011111 0011101001. | 1 001 | mulld 3
//| 011111 1011101001. | 1 010 | mulldo 4
//| 011111 .001001001. | 1 010 | mulhd 4
//| 011111 .000001001. | 1 010 | mulhdu 4
//| 011111 1100110011. | 1 000 | erativax 2
//| 011111 0011010100. | 1 000 | ldawx
//| 011111 0010100110. | 1 000 | dcbtls
//| 011111 0010000110. | 1 000 | dcbtstls
//| 011111 0000110100. | 1 000 | lbarx
//| 011111 0001010100. | 1 000 | ldarx
//| 011111 0001110100. | 1 000 | lharx
//| 011111 0000010100. | 1 000 | lwarx
//*END*==================+==================+
//?TABLE END rv_instruction_decoder ;
//table_end
//assign_start
assign RV_INSTRUCTION_DECODER_PT[1] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 16'b0111111100110011);
assign RV_INSTRUCTION_DECODER_PT[2] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 15'b011111001000110);
assign RV_INSTRUCTION_DECODER_PT[3] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 16'b0111111011101001);
assign RV_INSTRUCTION_DECODER_PT[4] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 16'b0111110011101001);
assign RV_INSTRUCTION_DECODER_PT[5] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 14'b01111100010100);
assign RV_INSTRUCTION_DECODER_PT[6] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 15'b011111001010100);
assign RV_INSTRUCTION_DECODER_PT[7] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[1], instr_21_31[2], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 14'b01111100001001);
assign RV_INSTRUCTION_DECODER_PT[8] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5]}) == 6'b000111);
// Table RV_INSTRUCTION_DECODER Signal Assignments for Outputs
assign is_brick = (RV_INSTRUCTION_DECODER_PT[1] | RV_INSTRUCTION_DECODER_PT[2] | RV_INSTRUCTION_DECODER_PT[3] | RV_INSTRUCTION_DECODER_PT[4] | RV_INSTRUCTION_DECODER_PT[5] | RV_INSTRUCTION_DECODER_PT[6] | RV_INSTRUCTION_DECODER_PT[7] | RV_INSTRUCTION_DECODER_PT[8]);
assign brick_cycles[0] = (1'b0);
assign brick_cycles[1] = (RV_INSTRUCTION_DECODER_PT[3] | RV_INSTRUCTION_DECODER_PT[7]);
assign brick_cycles[2] = (RV_INSTRUCTION_DECODER_PT[4]);
//assign_end
endmodule |
module fu_add_glbc(
ex4_g16,
ex4_t16,
ex4_inc_all1,
ex4_effsub,
ex4_effsub_npz,
ex4_effadd_npz,
f_alg_ex4_frc_sel_p1,
f_alg_ex4_sticky,
f_pic_ex4_is_nan,
f_pic_ex4_is_gt,
f_pic_ex4_is_lt,
f_pic_ex4_is_eq,
f_pic_ex4_cmp_sgnpos,
f_pic_ex4_cmp_sgnneg,
ex4_g128,
ex4_g128_b,
ex4_t128,
ex4_t128_b,
ex4_flip_inc_p0,
ex4_flip_inc_p1,
ex4_inc_sel_p0,
ex4_inc_sel_p1,
ex4_eac_sel_p0n,
ex4_eac_sel_p0,
ex4_eac_sel_p1,
ex4_sign_carry,
ex4_flag_nan_cp1,
ex4_flag_gt_cp1,
ex4_flag_lt_cp1,
ex4_flag_eq_cp1,
ex4_flag_nan,
ex4_flag_gt,
ex4_flag_lt,
ex4_flag_eq
);
input [0:6] ex4_g16; // from each byte section
input [0:6] ex4_t16; // from each byte section
input ex4_inc_all1;
input ex4_effsub;
input ex4_effsub_npz;
input ex4_effadd_npz;
input f_alg_ex4_frc_sel_p1;
input f_alg_ex4_sticky;
input f_pic_ex4_is_nan;
input f_pic_ex4_is_gt;
input f_pic_ex4_is_lt;
input f_pic_ex4_is_eq;
input f_pic_ex4_cmp_sgnpos;
input f_pic_ex4_cmp_sgnneg;
//------------------
output [1:6] ex4_g128; // to each byte section
output [1:6] ex4_g128_b; // to each byte section
output [1:6] ex4_t128; // to each byte section
output [1:6] ex4_t128_b; // to each byte section
//------------------
output ex4_flip_inc_p0;
output ex4_flip_inc_p1;
output ex4_inc_sel_p0;
output ex4_inc_sel_p1;
output [0:6] ex4_eac_sel_p0n;
output [0:6] ex4_eac_sel_p0;
output [0:6] ex4_eac_sel_p1;
output ex4_sign_carry;
output ex4_flag_nan_cp1;
output ex4_flag_gt_cp1;
output ex4_flag_lt_cp1;
output ex4_flag_eq_cp1;
output ex4_flag_nan;
output ex4_flag_gt;
output ex4_flag_lt;
output ex4_flag_eq;
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire cp0_g32_01_b;
wire cp0_g32_23_b;
wire cp0_g32_45_b;
wire cp0_g32_66_b;
wire cp0_t32_01_b;
wire cp0_t32_23_b;
wire cp0_t32_45_b;
wire cp0_t32_66_b;
wire cp0_g64_03;
wire cp0_g64_46;
wire cp0_t64_03;
wire cp0_t64_46;
wire cp0_g128_06_b;
wire cp0_t128_06_b;
wire cp0_all1_b;
wire cp0_all1_p;
wire cp0_co_p0;
wire cp0_co_p1;
wire cp0_flip_inc_p1_b;
wire ex4_inc_sel_p0_b;
wire ex4_sign_carry_b;
wire ex4_my_gt_b;
wire ex4_my_lt;
wire ex4_my_eq_b;
wire ex4_my_gt;
wire ex4_my_eq;
wire ex4_gt_pos_b;
wire ex4_gt_neg_b;
wire ex4_lt_pos_b;
wire ex4_lt_neg_b;
wire ex4_eq_eq_b;
wire ex4_is_gt_b;
wire ex4_is_lt_b;
wire ex4_is_eq_b;
wire ex4_sgn_eq;
wire cp7_g32_00_b;
wire cp7_g32_12_b;
wire cp7_g32_34_b;
wire cp7_g32_56_b;
wire cp7_t32_00_b;
wire cp7_t32_12_b;
wire cp7_t32_34_b;
wire cp7_g64_02;
wire cp7_g64_36;
wire cp7_t64_02;
wire cp7_g128_06_b;
wire cp7_all1_b;
wire cp7_all1_p;
wire cp7_co_p0;
wire cp7_sel_p0n_x_b;
wire cp7_sel_p0n_y_b;
wire cp7_sel_p0_b;
wire cp7_sel_p1_b;
wire cp7_sub_sticky;
wire cp7_sub_stickyn;
wire cp7_add_frcp1_b;
wire cp7_add_frcp0_b;
wire cp6_g32_00_b;
wire cp6_g32_12_b;
wire cp6_g32_34_b;
wire cp6_g32_56_b;
wire cp6_t32_00_b;
wire cp6_t32_12_b;
wire cp6_t32_34_b;
wire cp6_g64_02;
wire cp6_g64_36;
wire cp6_t64_02;
wire cp6_g128_06_b;
wire cp6_all1_b;
wire cp6_all1_p;
wire cp6_co_p0;
wire cp6_sel_p0n_x_b;
wire cp6_sel_p0n_y_b;
wire cp6_sel_p0_b;
wire cp6_sel_p1_b;
wire cp6_sub_sticky;
wire cp6_sub_stickyn;
wire cp6_add_frcp1_b;
wire cp6_add_frcp0_b;
wire cp5_g32_00_b;
wire cp5_g32_12_b;
wire cp5_g32_34_b;
wire cp5_g32_56_b;
wire cp5_t32_00_b;
wire cp5_t32_12_b;
wire cp5_t32_34_b;
wire cp5_t32_56_b;
wire cp5_g64_02;
wire cp5_g64_36;
wire cp5_t64_02;
wire cp5_g128_06_b;
wire cp5_all1_b;
wire cp5_all1_p;
wire cp5_co_p0;
wire cp5_sel_p0n_x_b;
wire cp5_sel_p0n_y_b;
wire cp5_sel_p0_b;
wire cp5_sel_p1_b;
wire cp5_sub_sticky;
wire cp5_sub_stickyn;
wire cp5_add_frcp1_b;
wire cp5_add_frcp0_b;
wire cp4_g32_01_b;
wire cp4_g32_23_b;
wire cp4_g32_45_b;
wire cp4_g32_66_b;
wire cp4_t32_01_b;
wire cp4_t32_23_b;
wire cp4_t32_45_b;
wire cp4_t32_66_b;
wire cp4_g64_03;
wire cp4_g64_46;
wire cp4_t64_03;
wire cp4_t64_46;
wire cp4_g128_06_b;
wire cp4_all1_b;
wire cp4_all1_p;
wire cp4_co_p0;
wire cp4_sel_p0n_x_b;
wire cp4_sel_p0n_y_b;
wire cp4_sel_p0_b;
wire cp4_sel_p1_b;
wire cp4_sub_sticky;
wire cp4_sub_stickyn;
wire cp4_add_frcp1_b;
wire cp4_add_frcp0_b;
wire cp3_g32_00_b;
wire cp3_g32_12_b;
wire cp3_g32_34_b;
wire cp3_g32_56_b;
wire cp3_t32_00_b;
wire cp3_t32_12_b;
wire cp3_t32_34_b;
wire cp3_t32_56_b;
wire cp3_g64_02;
wire cp3_g64_36;
wire cp3_t64_02;
wire cp3_t64_36;
wire cp3_g128_06_b;
wire cp3_all1_b;
wire cp3_all1_p;
wire cp3_co_p0;
wire cp3_sel_p0n_x_b;
wire cp3_sel_p0n_y_b;
wire cp3_sel_p0_b;
wire cp3_sel_p1_b;
wire cp3_sub_sticky;
wire cp3_sub_stickyn;
wire cp3_add_frcp1_b;
wire cp3_add_frcp0_b;
wire cp2_g32_01_b;
wire cp2_g32_23_b;
wire cp2_g32_45_b;
wire cp2_g32_66_b;
wire cp2_t32_01_b;
wire cp2_t32_23_b;
wire cp2_t32_45_b;
wire cp2_t32_66_b;
wire cp2_g64_03;
wire cp2_g64_46;
wire cp2_t64_03;
wire cp2_t64_46;
wire cp2_g128_06_b;
wire cp2_all1_b;
wire cp2_all1_p;
wire cp2_co_p0;
wire cp2_sel_p0n_x_b;
wire cp2_sel_p0n_y_b;
wire cp2_sel_p0_b;
wire cp2_sel_p1_b;
wire cp2_sub_sticky;
wire cp2_sub_stickyn;
wire cp2_add_frcp1_b;
wire cp2_add_frcp0_b;
wire cp1_g32_01_b;
wire cp1_g32_23_b;
wire cp1_g32_45_b;
wire cp1_g32_66_b;
wire cp1_t32_01_b;
wire cp1_t32_23_b;
wire cp1_t32_45_b;
wire cp1_t32_66_b;
wire cp1_g64_03;
wire cp1_g64_46;
wire cp1_t64_03;
wire cp1_t64_46;
wire cp1_g128_06_b;
wire cp1_all1_b;
wire cp1_all1_p;
wire cp1_co_p0;
wire cp1_sel_p0n_x_b;
wire cp1_sel_p0n_y_b;
wire cp1_sel_p0_b;
wire cp1_sel_p1_b;
wire cp1_sub_sticky;
wire cp1_sub_stickyn;
wire cp1_add_frcp1_b;
wire cp1_add_frcp0_b;
wire cp1_g32_11_b; //EXTRA
wire cp1_t32_11_b;
wire cp1_g64_13;
wire cp1_t64_13;
wire cp1_g128_16_b;
wire cp1_t128_16_b;
wire cp2_g64_23;
wire cp2_t64_23;
wire cp2_g128_26_b;
wire cp2_t128_26_b;
wire cp3_g128_36_b;
wire cp3_t128_36_b;
wire cp4_g128_46_b;
wire cp4_t128_46_b;
wire cp5_g64_56;
wire cp5_t64_56;
wire cp5_g128_56_b;
wire cp5_t128_56_b;
wire cp6_g32_66_b;
wire cp6_t32_66_b;
wire cp1_g128_16; //DRIVER
wire cp1_t128_16;
wire cp2_g128_26;
wire cp2_t128_26;
wire cp3_g128_36;
wire cp3_t128_36;
wire cp4_g128_46;
wire cp4_t128_46;
wire cp5_g128_56;
wire cp5_t128_56;
wire cp6_g128_66;
wire cp6_t128_66;
//=#########################################
//= global carry chain <PARALLEL VERSIONS>
//=#########################################
// try to put all long wire from BYT to global
// parallel copies should allow for smaller aoi/oai blocks
//=#########################################
//= CMP COPY
//=#########################################
// --compare stuff----
// -- c0 : gt
// -- c1 : ge
//
// ex4_my_eq <= (ex4_add_co_p1 and ex4_inc_all1 ) and not ex4_add_co_p0; -- ge * !gt
// ex4_my_gt <= (ex4_add_co_p0 and ex4_inc_all1 ) ; -- gt
// ex4_my_lt <= not(ex4_add_co_p1 and ex4_inc_all1 ) ; -- !ge
//
// ex4_flag_nan <= f_pic_ex4_is_nan;
// ex4_flag_gt <= f_pic_ex4_is_gt or (f_pic_ex4_cmp_sgnpos and ex4_my_gt) or (f_pic_ex4_cmp_sgnneg and ex4_my_lt) ;
// ex4_flag_lt <= f_pic_ex4_is_lt or (f_pic_ex4_cmp_sgnpos and ex4_my_lt) or (f_pic_ex4_cmp_sgnneg and ex4_my_gt) ;
// ex4_flag_eq <= f_pic_ex4_is_eq or (f_pic_ex4_cmp_sgnpos and ex4_my_eq) or (f_pic_ex4_cmp_sgnneg and ex4_my_eq) ;
assign cp0_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21
assign cp0_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21
assign cp0_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21
assign cp0_g32_66_b = (~(ex4_g16[6])); //cw_invert --done
assign cp0_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2
assign cp0_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2
assign cp0_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2
assign cp0_t32_66_b = (~(ex4_t16[6])); //cw_invert
assign cp0_g64_03 = (~(cp0_g32_01_b & (cp0_t32_01_b | cp0_g32_23_b))); //cw_oai21
assign cp0_g64_46 = (~(cp0_g32_45_b & (cp0_t32_45_b | cp0_g32_66_b))); //cw_oai21
assign cp0_t64_03 = (~(cp0_t32_01_b | cp0_t32_23_b)); //cw_nor2
assign cp0_t64_46 = (~(cp0_g32_45_b & (cp0_t32_45_b | cp0_t32_66_b))); //cw_oai21
assign cp0_g128_06_b = (~(cp0_g64_03 | (cp0_t64_03 & cp0_g64_46))); //cw_aoi21
assign cp0_t128_06_b = (~(cp0_g64_03 | (cp0_t64_03 & cp0_t64_46))); //cw_aoi21
assign cp0_all1_b = (~ex4_inc_all1); //cw_invert
assign cp0_all1_p = (~cp0_all1_b); //cw_invert
assign cp0_co_p0 = (~(cp0_g128_06_b)); //cw_invert
assign cp0_co_p1 = (~(cp0_t128_06_b)); //cw_invert
//-------------- incr eac selects --------------------
assign ex4_flip_inc_p0 = ex4_effsub; //NOT MAPPED --output--
assign cp0_flip_inc_p1_b = (~(ex4_effsub & cp0_all1_b)); //cw_nand2
assign ex4_flip_inc_p1 = (~(cp0_flip_inc_p1_b)); //cw_invert --output--
assign ex4_inc_sel_p1 = (~cp0_g128_06_b); //cw_invert --OUTPUT--
assign ex4_inc_sel_p0_b = (~cp0_g128_06_b); //cw_invert
assign ex4_inc_sel_p0 = (~ex4_inc_sel_p0_b); //cw_invert --OUTPUT--
//-------------- sign selects --------------------
assign ex4_sign_carry_b = (~(ex4_effsub & cp0_all1_p & cp0_co_p0)); //cw_nand3
assign ex4_sign_carry = (~(ex4_sign_carry_b)); //cw_invert --OUTPUT--
//--------------- compares ---------------------------
assign ex4_my_gt_b = (~(cp0_co_p0 & cp0_all1_p)); //cw_nand2
assign ex4_my_lt = (~(cp0_co_p1 & cp0_all1_p)); //cw_nand2
assign ex4_my_eq_b = (~(cp0_co_p1 & cp0_all1_p & cp0_g128_06_b)); //cw_nand3
assign ex4_my_gt = (~ex4_my_gt_b); //cw_invert
assign ex4_my_eq = (~ex4_my_eq_b); //cw_invert
assign ex4_gt_pos_b = (~(ex4_my_gt & f_pic_ex4_cmp_sgnpos)); //cw_nand2
assign ex4_gt_neg_b = (~(ex4_my_lt & f_pic_ex4_cmp_sgnneg)); //cw_nand2
assign ex4_lt_pos_b = (~(ex4_my_lt & f_pic_ex4_cmp_sgnpos)); //cw_nand2
assign ex4_lt_neg_b = (~(ex4_my_gt & f_pic_ex4_cmp_sgnneg)); //cw_nand2
assign ex4_eq_eq_b = (~(ex4_my_eq & ex4_sgn_eq)); //cw_nand3
assign ex4_flag_gt = (~(ex4_gt_pos_b & ex4_gt_neg_b & ex4_is_gt_b)); //cw_nand3 --output--
assign ex4_flag_gt_cp1 = (~(ex4_gt_pos_b & ex4_gt_neg_b & ex4_is_gt_b)); //cw_nand3 --output--
assign ex4_flag_lt = (~(ex4_lt_pos_b & ex4_lt_neg_b & ex4_is_lt_b)); //cw_nand3 --output--
assign ex4_flag_lt_cp1 = (~(ex4_lt_pos_b & ex4_lt_neg_b & ex4_is_lt_b)); //cw_nand3 --output--
assign ex4_flag_eq = (~(ex4_eq_eq_b & ex4_is_eq_b)); //cw_nand2 --output--
assign ex4_flag_eq_cp1 = (~(ex4_eq_eq_b & ex4_is_eq_b)); //cw_nand2 --output--
assign ex4_flag_nan = f_pic_ex4_is_nan; //NOT MAPPED --output--
assign ex4_flag_nan_cp1 = f_pic_ex4_is_nan; //NOT MAPPED --output--
assign ex4_is_gt_b = (~(f_pic_ex4_is_gt)); //NOT MAPPED
assign ex4_is_lt_b = (~(f_pic_ex4_is_lt)); //NOT MAPPED
assign ex4_is_eq_b = (~(f_pic_ex4_is_eq)); //NOT MAPPED
assign ex4_sgn_eq = f_pic_ex4_cmp_sgnpos | f_pic_ex4_cmp_sgnneg; //NOT MAPPED
//=#########################################
//= BYT_0 MSB COPY
//=#########################################
assign cp1_g32_11_b = (~(ex4_g16[1])); //cw_aoi21 --EXTRA
assign cp1_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21
assign cp1_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21
assign cp1_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21
assign cp1_g32_66_b = (~(ex4_g16[6])); //cw_invert --done
assign cp1_t32_11_b = (~(ex4_t16[1])); //cw_invert --EXTRA
assign cp1_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2
assign cp1_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2
assign cp1_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2
assign cp1_t32_66_b = (~(ex4_t16[6])); //cw_invert
assign cp1_g64_03 = (~(cp1_g32_01_b & (cp1_t32_01_b | cp1_g32_23_b))); //cw_oai21
assign cp1_g64_13 = (~(cp1_g32_11_b & (cp1_t32_11_b | cp1_g32_23_b))); //cw_oai21 --EXTRA
assign cp1_g64_46 = (~(cp1_g32_45_b & (cp1_t32_45_b | cp1_g32_66_b))); //cw_oai21
assign cp1_t64_03 = (~(cp1_t32_01_b | cp1_t32_23_b)); //cw_nor2
assign cp1_t64_13 = (~(cp1_t32_11_b | cp1_t32_23_b)); //cw_nor2 --EXTRA
assign cp1_t64_46 = (~(cp1_g32_45_b & (cp1_t32_45_b | cp1_t32_66_b))); //cw_oai21
assign cp1_g128_06_b = (~(cp1_g64_03 | (cp1_t64_03 & cp1_g64_46))); //cw_aoi21
assign cp1_g128_16_b = (~(cp1_g64_13 | (cp1_t64_13 & cp1_g64_46))); //cw_aoi21 --EXTRA
assign cp1_t128_16_b = (~(cp1_g64_13 | (cp1_t64_13 & cp1_t64_46))); //cw_aoi21 --EXTRA
assign ex4_g128[1] = (~(cp1_g128_16_b)); //cw_invert --OUTPUT--
assign cp1_g128_16 = (~(cp1_g128_16_b)); //cw_invert
assign ex4_g128_b[1] = (~(cp1_g128_16)); //cw_invert --OUTPUT--
assign ex4_t128[1] = (~(cp1_t128_16_b)); //cw_invert --OUTPUT--
assign cp1_t128_16 = (~(cp1_t128_16_b)); //cw_invert
assign ex4_t128_b[1] = (~(cp1_t128_16)); //cw_invert --OUTPUT--
assign cp1_all1_b = (~ex4_inc_all1); //cw_invert
assign cp1_all1_p = (~cp1_all1_b); //cw_invert
assign cp1_co_p0 = (~(cp1_g128_06_b)); //cw_invert
assign cp1_sel_p0n_x_b = (~(cp1_all1_b & ex4_effsub_npz)); //cw_nand2
assign cp1_sel_p0n_y_b = (~(cp1_g128_06_b & ex4_effsub_npz)); //cw_nand2
assign cp1_sel_p0_b = (~(cp1_co_p0 & cp1_all1_p & cp1_sub_sticky)); //cw_nand3
assign cp1_sel_p1_b = (~(cp1_co_p0 & cp1_all1_p & cp1_sub_stickyn)); //cw_nand3
assign ex4_eac_sel_p0n[0] = (~(cp1_sel_p0n_x_b & cp1_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p0[0] = (~(cp1_sel_p0_b & cp1_add_frcp0_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p1[0] = (~(cp1_sel_p1_b & cp1_add_frcp1_b)); //cw_nand2 --OUTPUT--
assign cp1_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
assign cp1_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
assign cp1_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
assign cp1_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
//=#########################################
//= BYT_1 MSB COPY
//=#########################################
assign cp2_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21
assign cp2_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21
assign cp2_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21
assign cp2_g32_66_b = (~(ex4_g16[6])); //cw_invert --done
assign cp2_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2
assign cp2_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2
assign cp2_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2
assign cp2_t32_66_b = (~(ex4_t16[6])); //cw_invert
assign cp2_g64_23 = (~(cp2_g32_23_b)); //cw_invert --EXTRA
assign cp2_g64_03 = (~(cp2_g32_01_b & (cp2_t32_01_b | cp2_g32_23_b))); //cw_oai21
assign cp2_g64_46 = (~(cp2_g32_45_b & (cp2_t32_45_b | cp2_g32_66_b))); //cw_oai21
assign cp2_t64_23 = (~(cp2_t32_23_b)); //cw_invert --EXTRA
assign cp2_t64_03 = (~(cp2_t32_01_b | cp2_t32_23_b)); //cw_nor2
assign cp2_t64_46 = (~(cp2_g32_45_b & (cp2_t32_45_b | cp2_t32_66_b))); //cw_oai21
assign cp2_g128_06_b = (~(cp2_g64_03 | (cp2_t64_03 & cp2_g64_46))); //cw_aoi21
assign cp2_g128_26_b = (~(cp2_g64_23 | (cp2_t64_23 & cp2_g64_46))); //cw_aoi21 --EXTRA
assign cp2_t128_26_b = (~(cp2_g64_23 | (cp2_t64_23 & cp2_t64_46))); //cw_aoi21 --EXTRA
assign ex4_g128[2] = (~(cp2_g128_26_b)); //cw_invert --OUTPUT--
assign cp2_g128_26 = (~(cp2_g128_26_b)); //cw_invert
assign ex4_g128_b[2] = (~(cp2_g128_26)); //cw_invert --OUTPUT--
assign ex4_t128[2] = (~(cp2_t128_26_b)); //cw_invert --OUTPUT--
assign cp2_t128_26 = (~(cp2_t128_26_b)); //cw_invert
assign ex4_t128_b[2] = (~(cp2_t128_26)); //cw_invert --OUTPUT--
assign cp2_all1_b = (~ex4_inc_all1); //cw_invert
assign cp2_all1_p = (~cp2_all1_b); //cw_invert
assign cp2_co_p0 = (~(cp2_g128_06_b)); //cw_invert
assign cp2_sel_p0n_x_b = (~(cp2_all1_b & ex4_effsub_npz)); //cw_nand2
assign cp2_sel_p0n_y_b = (~(cp2_g128_06_b & ex4_effsub_npz)); //cw_nand2
assign cp2_sel_p0_b = (~(cp2_co_p0 & cp2_all1_p & cp2_sub_sticky)); //cw_nand3
assign cp2_sel_p1_b = (~(cp2_co_p0 & cp2_all1_p & cp2_sub_stickyn)); //cw_nand3
assign ex4_eac_sel_p0n[1] = (~(cp2_sel_p0n_x_b & cp2_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p0[1] = (~(cp2_sel_p0_b & cp2_add_frcp0_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p1[1] = (~(cp2_sel_p1_b & cp2_add_frcp1_b)); //cw_nand2 --OUTPUT--
assign cp2_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
assign cp2_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
assign cp2_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
assign cp2_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
//=#########################################
//= BYT_2 MSB COPY
//=#########################################
assign cp3_g32_00_b = (~(ex4_g16[0])); //cw_invert
assign cp3_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21
assign cp3_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21
assign cp3_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21
assign cp3_t32_00_b = (~(ex4_t16[0])); //cw_invert
assign cp3_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2
assign cp3_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2
assign cp3_t32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_t16[6]))); //cw_aoi21
assign cp3_g64_02 = (~(cp3_g32_00_b & (cp3_t32_00_b | cp3_g32_12_b))); //cw_oai21
assign cp3_g64_36 = (~(cp3_g32_34_b & (cp3_t32_34_b | cp3_g32_56_b))); //cw_oai21
assign cp3_t64_02 = (~(cp3_t32_00_b | cp3_t32_12_b)); //cw_nor2
assign cp3_t64_36 = (~(cp3_g32_34_b & (cp3_t32_34_b | cp3_t32_56_b))); //cw_oai21
assign cp3_g128_06_b = (~(cp3_g64_02 | (cp3_t64_02 & cp3_g64_36))); //cw_aoi21
assign cp3_g128_36_b = (~(cp3_g64_36)); //cw_invert --EXTRA
assign cp3_t128_36_b = (~(cp3_t64_36)); //cw_invert --EXTRA
assign ex4_g128[3] = (~(cp3_g128_36_b)); //cw_invert --OUTPUT--
assign cp3_g128_36 = (~(cp3_g128_36_b)); //cw_invert
assign ex4_g128_b[3] = (~(cp3_g128_36)); //cw_invert --OUTPUT--
assign ex4_t128[3] = (~(cp3_t128_36_b)); //cw_invert --OUTPUT--
assign cp3_t128_36 = (~(cp3_t128_36_b)); //cw_invert
assign ex4_t128_b[3] = (~(cp3_t128_36)); //cw_invert --OUTPUT--
assign cp3_all1_b = (~ex4_inc_all1); //cw_invert
assign cp3_all1_p = (~cp3_all1_b); //cw_invert
assign cp3_co_p0 = (~(cp3_g128_06_b)); //cw_invert
assign cp3_sel_p0n_x_b = (~(cp3_all1_b & ex4_effsub_npz)); //cw_nand2
assign cp3_sel_p0n_y_b = (~(cp3_g128_06_b & ex4_effsub_npz)); //cw_nand2
assign cp3_sel_p0_b = (~(cp3_co_p0 & cp3_all1_p & cp3_sub_sticky)); //cw_nand3
assign cp3_sel_p1_b = (~(cp3_co_p0 & cp3_all1_p & cp3_sub_stickyn)); //cw_nand3
assign ex4_eac_sel_p0n[2] = (~(cp3_sel_p0n_x_b & cp3_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p0[2] = (~(cp3_sel_p0_b & cp3_add_frcp0_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p1[2] = (~(cp3_sel_p1_b & cp3_add_frcp1_b)); //cw_nand2 --OUTPUT--
assign cp3_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
assign cp3_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
assign cp3_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
assign cp3_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
//=#########################################
//= BYT_3 MSB COPY
//=#########################################
assign cp4_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21
assign cp4_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21
assign cp4_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21
assign cp4_g32_66_b = (~(ex4_g16[6])); //cw_invert --done
assign cp4_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2
assign cp4_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2
assign cp4_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2
assign cp4_t32_66_b = (~(ex4_t16[6])); //cw_invert
assign cp4_g64_03 = (~(cp4_g32_01_b & (cp4_t32_01_b | cp4_g32_23_b))); //cw_oai21
assign cp4_g64_46 = (~(cp4_g32_45_b & (cp4_t32_45_b | cp4_g32_66_b))); //cw_oai21
assign cp4_t64_03 = (~(cp4_t32_01_b | cp4_t32_23_b)); //cw_nor2
assign cp4_t64_46 = (~(cp4_g32_45_b & (cp4_t32_45_b | cp4_t32_66_b))); //cw_oai21
assign cp4_g128_06_b = (~(cp4_g64_03 | (cp4_t64_03 & cp4_g64_46))); //cw_aoi21
assign cp4_g128_46_b = (~(cp4_g64_46)); //cw_invert --EXTRA
assign cp4_t128_46_b = (~(cp4_t64_46)); //cw_invert --EXTRA
assign ex4_g128[4] = (~(cp4_g128_46_b)); //cw_invert --OUTPUT--
assign cp4_g128_46 = (~(cp4_g128_46_b)); //cw_invert
assign ex4_g128_b[4] = (~(cp4_g128_46)); //cw_invert --OUTPUT--
assign ex4_t128[4] = (~(cp4_t128_46_b)); //cw_invert --OUTPUT--
assign cp4_t128_46 = (~(cp4_t128_46_b)); //cw_invert
assign ex4_t128_b[4] = (~(cp4_t128_46)); //cw_invert --OUTPUT--
assign cp4_all1_b = (~ex4_inc_all1); //cw_invert
assign cp4_all1_p = (~cp4_all1_b); //cw_invert
assign cp4_co_p0 = (~(cp4_g128_06_b)); //cw_invert
assign cp4_sel_p0n_x_b = (~(cp4_all1_b & ex4_effsub_npz)); //cw_nand2
assign cp4_sel_p0n_y_b = (~(cp4_g128_06_b & ex4_effsub_npz)); //cw_nand2
assign cp4_sel_p0_b = (~(cp4_co_p0 & cp4_all1_p & cp4_sub_sticky)); //cw_nand3
assign cp4_sel_p1_b = (~(cp4_co_p0 & cp4_all1_p & cp4_sub_stickyn)); //cw_nand3
assign ex4_eac_sel_p0n[3] = (~(cp4_sel_p0n_x_b & cp4_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p0[3] = (~(cp4_sel_p0_b & cp4_add_frcp0_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p1[3] = (~(cp4_sel_p1_b & cp4_add_frcp1_b)); //cw_nand2 --OUTPUT--
assign cp4_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
assign cp4_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
assign cp4_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
assign cp4_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
//=#########################################
//= BYT_4
//=#########################################
assign cp5_g32_00_b = (~(ex4_g16[0])); //cw_invert
assign cp5_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21
assign cp5_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21
assign cp5_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21
assign cp5_t32_00_b = (~(ex4_t16[0])); //cw_invert
assign cp5_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2
assign cp5_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2
assign cp5_t32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_t16[6]))); //cw_aoi21
assign cp5_g64_02 = (~(cp5_g32_00_b & (cp5_t32_00_b | cp5_g32_12_b))); //cw_oai21
assign cp5_g64_36 = (~(cp5_g32_34_b & (cp5_t32_34_b | cp5_g32_56_b))); //cw_oai21
assign cp5_g64_56 = (~(cp5_g32_56_b)); //cw_invert --EXTRA
assign cp5_t64_02 = (~(cp5_t32_00_b | cp5_t32_12_b)); //cw_nor2
assign cp5_t64_56 = (~(cp5_t32_56_b)); //cw_invert --EXTRA
assign cp5_g128_06_b = (~(cp5_g64_02 | (cp5_t64_02 & cp5_g64_36))); //cw_aoi21
assign cp5_g128_56_b = (~(cp5_g64_56)); //cw_invert --EXTRA
assign cp5_t128_56_b = (~(cp5_t64_56)); //cw_invert --EXTRA
assign ex4_g128[5] = (~(cp5_g128_56_b)); //cw_invert --OUTPUT--
assign cp5_g128_56 = (~(cp5_g128_56_b)); //cw_invert
assign ex4_g128_b[5] = (~(cp5_g128_56)); //cw_invert --OUTPUT--
assign ex4_t128[5] = (~(cp5_t128_56_b)); //cw_invert --OUTPUT--
assign cp5_t128_56 = (~(cp5_t128_56_b)); //cw_invert
assign ex4_t128_b[5] = (~(cp5_t128_56)); //cw_invert --OUTPUT--
assign cp5_all1_b = (~ex4_inc_all1); //cw_invert
assign cp5_all1_p = (~cp5_all1_b); //cw_invert
assign cp5_co_p0 = (~(cp5_g128_06_b)); //cw_invert
assign cp5_sel_p0n_x_b = (~(cp5_all1_b & ex4_effsub_npz)); //cw_nand2
assign cp5_sel_p0n_y_b = (~(cp5_g128_06_b & ex4_effsub_npz)); //cw_nand2
assign cp5_sel_p0_b = (~(cp5_co_p0 & cp5_all1_p & cp5_sub_sticky)); //cw_nand3
assign cp5_sel_p1_b = (~(cp5_co_p0 & cp5_all1_p & cp5_sub_stickyn)); //cw_nand3
assign ex4_eac_sel_p0n[4] = (~(cp5_sel_p0n_x_b & cp5_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p0[4] = (~(cp5_sel_p0_b & cp5_add_frcp0_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p1[4] = (~(cp5_sel_p1_b & cp5_add_frcp1_b)); //cw_nand2 --OUTPUT--
assign cp5_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
assign cp5_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
assign cp5_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
assign cp5_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
//=#########################################
//= BYT_5
//=#########################################
assign cp6_g32_00_b = (~(ex4_g16[0])); //cw_invert
assign cp6_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21
assign cp6_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21
assign cp6_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21
assign cp6_g32_66_b = (~(ex4_g16[6])); //cw_invert EXTRA
assign cp6_t32_00_b = (~(ex4_t16[0])); //cw_invert
assign cp6_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2
assign cp6_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2
assign cp6_t32_66_b = (~(ex4_t16[6])); //cw_invert EXTRA
assign cp6_g64_02 = (~(cp6_g32_00_b & (cp6_t32_00_b | cp6_g32_12_b))); //cw_oai21
assign cp6_g64_36 = (~(cp6_g32_34_b & (cp6_t32_34_b | cp6_g32_56_b))); //cw_oai21
assign cp6_t64_02 = (~(cp6_t32_00_b | cp6_t32_12_b)); //cw_nor2
assign cp6_g128_06_b = (~(cp6_g64_02 | (cp6_t64_02 & cp6_g64_36))); //cw_aoi21
assign ex4_g128[6] = (~(cp6_g32_66_b)); //cw_invert --OUTPUT--
assign cp6_g128_66 = (~(cp6_g32_66_b)); //cw_invert
assign ex4_g128_b[6] = (~(cp6_g128_66)); //cw_invert --OUTPUT--
assign ex4_t128[6] = (~(cp6_t32_66_b)); //cw_invert --OUTPUT--
assign cp6_t128_66 = (~(cp6_t32_66_b)); //cw_invert
assign ex4_t128_b[6] = (~(cp6_t128_66)); //cw_invert --OUTPUT--
assign cp6_all1_b = (~ex4_inc_all1); //cw_invert
assign cp6_all1_p = (~cp6_all1_b); //cw_invert
assign cp6_co_p0 = (~(cp6_g128_06_b)); //cw_invert
assign cp6_sel_p0n_x_b = (~(cp6_all1_b & ex4_effsub_npz)); //cw_nand2
assign cp6_sel_p0n_y_b = (~(cp6_g128_06_b & ex4_effsub_npz)); //cw_nand2
assign cp6_sel_p0_b = (~(cp6_co_p0 & cp6_all1_p & cp6_sub_sticky)); //cw_nand3
assign cp6_sel_p1_b = (~(cp6_co_p0 & cp6_all1_p & cp6_sub_stickyn)); //cw_nand3
assign ex4_eac_sel_p0n[5] = (~(cp6_sel_p0n_x_b & cp6_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p0[5] = (~(cp6_sel_p0_b & cp6_add_frcp0_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p1[5] = (~(cp6_sel_p1_b & cp6_add_frcp1_b)); //cw_nand2 --OUTPUT--
assign cp6_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
assign cp6_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
assign cp6_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
assign cp6_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
//=#########################################
//= BYT_6 LSB COPY
//=#########################################
assign cp7_g32_00_b = (~(ex4_g16[0])); //cw_invert
assign cp7_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21
assign cp7_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21
assign cp7_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21
assign cp7_t32_00_b = (~(ex4_t16[0])); //cw_invert
assign cp7_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2
assign cp7_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2
assign cp7_g64_02 = (~(cp7_g32_00_b & (cp7_t32_00_b | cp7_g32_12_b))); //cw_oai21
assign cp7_g64_36 = (~(cp7_g32_34_b & (cp7_t32_34_b | cp7_g32_56_b))); //cw_oai21
assign cp7_t64_02 = (~(cp7_t32_00_b | cp7_t32_12_b)); //cw_nor2
assign cp7_g128_06_b = (~(cp7_g64_02 | (cp7_t64_02 & cp7_g64_36))); //cw_aoi21
assign cp7_all1_b = (~ex4_inc_all1); //cw_invert
assign cp7_all1_p = (~cp7_all1_b); //cw_invert
assign cp7_co_p0 = (~(cp7_g128_06_b)); //cw_invert
assign cp7_sel_p0n_x_b = (~(cp7_all1_b & ex4_effsub_npz)); //cw_nand2
assign cp7_sel_p0n_y_b = (~(cp7_g128_06_b & ex4_effsub_npz)); //cw_nand2
assign cp7_sel_p0_b = (~(cp7_co_p0 & cp7_all1_p & cp7_sub_sticky)); //cw_nand3
assign cp7_sel_p1_b = (~(cp7_co_p0 & cp7_all1_p & cp7_sub_stickyn)); //cw_nand3
assign ex4_eac_sel_p0n[6] = (~(cp7_sel_p0n_x_b & cp7_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p0[6] = (~(cp7_sel_p0_b & cp7_add_frcp0_b)); //cw_nand2 --OUTPUT--
assign ex4_eac_sel_p1[6] = (~(cp7_sel_p1_b & cp7_add_frcp1_b)); //cw_nand2 --OUTPUT--
assign cp7_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
assign cp7_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
assign cp7_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
assign cp7_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
endmodule |
module iuq_cpl_itag( inc, i, o);
parameter SIZE = 7;
parameter WRAP = 40;
input [0:1] inc;
input [0:SIZE-1] i;
output [0:SIZE-1] o;
wire [1:SIZE] a;
wire [1:SIZE] b;
wire [1:SIZE] rslt;
wire rollover;
wire rollover_m1;
wire inc_1;
wire inc_2;
wire [0:1] wrap_sel;
(* analysis_not_referenced="true" *)
wire unused;
// Increment by 1 or 2.
// Go back to zero at WRAP
// Flip bit zero when a rollover occurs
// eg 0...39, 64..103
assign unused = rslt[SIZE];
assign a = {i[1:SIZE - 1], inc[1]};
assign b = {{SIZE-2{1'b0}},{inc[0], inc[1]}};
assign rslt = a + b;
assign rollover = {{32-SIZE+1{1'b0}},i[1:SIZE - 1]} == WRAP;
assign rollover_m1 = {{32-SIZE+1{1'b0}},i[1:SIZE - 1]} == WRAP - 1;
assign inc_1 = inc[0] ^ inc[1];
assign inc_2 = inc[0] & inc[1];
assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2);
assign wrap_sel[1] = rollover & inc_2;
assign o[0] = i[0] ^ |(wrap_sel);
assign o[1:SIZE-1] = (wrap_sel[0:1] == 2'b10) ? {SIZE-1{1'b0}} :
(wrap_sel[0:1] == 2'b01) ? {{SIZE-2{1'b0}},{1'b1}} :
rslt[1:SIZE-1];
endmodule |
module fu_alg_or16(
ex3_sh_lvl2,
ex3_sticky_or16
);
input [0:67] ex3_sh_lvl2;
output [0:4] ex3_sticky_or16;
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:7] ex3_g1o2_b;
wire [0:7] ex3_g2o2_b;
wire [0:7] ex3_g3o2_b;
wire [0:7] ex3_g4o2_b;
wire [0:3] ex3_g1o4;
wire [0:3] ex3_g2o4;
wire [0:3] ex3_g3o4;
wire [0:3] ex3_g4o4;
wire [0:1] ex3_g0o8_b;
wire [0:1] ex3_g1o8_b;
wire [0:1] ex3_g2o8_b;
wire [0:1] ex3_g3o8_b;
wire [0:1] ex3_g4o8_b;
wire [0:4] ex3_o16;
wire [0:4] ex3_o16_b;
//----------------------------------------------------------
// UnMapped original equations
//----------------------------------------------------------
// ex3_sticky_or16(4) <= OR( ex3_sh_lvl2[52:67] );
// ex3_sticky_or16(3) <= OR( ex3_sh_lvl2[36:51] );
// ex3_sticky_or16(2) <= OR( ex3_sh_lvl2[20:35] );
// ex3_sticky_or16(1) <= OR( ex3_sh_lvl2[ 4:19] );
// ex3_sticky_or16(0) <= OR( ex3_sh_lvl2[ 0: 3] );
//---------------------------------------------------------
assign ex3_g1o2_b[0] = (~(ex3_sh_lvl2[4] | ex3_sh_lvl2[5]));
assign ex3_g1o2_b[1] = (~(ex3_sh_lvl2[6] | ex3_sh_lvl2[7]));
assign ex3_g1o2_b[2] = (~(ex3_sh_lvl2[8] | ex3_sh_lvl2[9]));
assign ex3_g1o2_b[3] = (~(ex3_sh_lvl2[10] | ex3_sh_lvl2[11]));
assign ex3_g1o2_b[4] = (~(ex3_sh_lvl2[12] | ex3_sh_lvl2[13]));
assign ex3_g1o2_b[5] = (~(ex3_sh_lvl2[14] | ex3_sh_lvl2[15]));
assign ex3_g1o2_b[6] = (~(ex3_sh_lvl2[16] | ex3_sh_lvl2[17]));
assign ex3_g1o2_b[7] = (~(ex3_sh_lvl2[18] | ex3_sh_lvl2[19]));
assign ex3_g2o2_b[0] = (~(ex3_sh_lvl2[20] | ex3_sh_lvl2[21]));
assign ex3_g2o2_b[1] = (~(ex3_sh_lvl2[22] | ex3_sh_lvl2[23]));
assign ex3_g2o2_b[2] = (~(ex3_sh_lvl2[24] | ex3_sh_lvl2[25]));
assign ex3_g2o2_b[3] = (~(ex3_sh_lvl2[26] | ex3_sh_lvl2[27]));
assign ex3_g2o2_b[4] = (~(ex3_sh_lvl2[28] | ex3_sh_lvl2[29]));
assign ex3_g2o2_b[5] = (~(ex3_sh_lvl2[30] | ex3_sh_lvl2[31]));
assign ex3_g2o2_b[6] = (~(ex3_sh_lvl2[32] | ex3_sh_lvl2[33]));
assign ex3_g2o2_b[7] = (~(ex3_sh_lvl2[34] | ex3_sh_lvl2[35]));
assign ex3_g3o2_b[0] = (~(ex3_sh_lvl2[36] | ex3_sh_lvl2[37]));
assign ex3_g3o2_b[1] = (~(ex3_sh_lvl2[38] | ex3_sh_lvl2[39]));
assign ex3_g3o2_b[2] = (~(ex3_sh_lvl2[40] | ex3_sh_lvl2[41]));
assign ex3_g3o2_b[3] = (~(ex3_sh_lvl2[42] | ex3_sh_lvl2[43]));
assign ex3_g3o2_b[4] = (~(ex3_sh_lvl2[44] | ex3_sh_lvl2[45]));
assign ex3_g3o2_b[5] = (~(ex3_sh_lvl2[46] | ex3_sh_lvl2[47]));
assign ex3_g3o2_b[6] = (~(ex3_sh_lvl2[48] | ex3_sh_lvl2[49]));
assign ex3_g3o2_b[7] = (~(ex3_sh_lvl2[50] | ex3_sh_lvl2[51]));
assign ex3_g4o2_b[0] = (~(ex3_sh_lvl2[52] | ex3_sh_lvl2[53]));
assign ex3_g4o2_b[1] = (~(ex3_sh_lvl2[54] | ex3_sh_lvl2[55]));
assign ex3_g4o2_b[2] = (~(ex3_sh_lvl2[56] | ex3_sh_lvl2[57]));
assign ex3_g4o2_b[3] = (~(ex3_sh_lvl2[58] | ex3_sh_lvl2[59]));
assign ex3_g4o2_b[4] = (~(ex3_sh_lvl2[60] | ex3_sh_lvl2[61]));
assign ex3_g4o2_b[5] = (~(ex3_sh_lvl2[62] | ex3_sh_lvl2[63]));
assign ex3_g4o2_b[6] = (~(ex3_sh_lvl2[64] | ex3_sh_lvl2[65]));
assign ex3_g4o2_b[7] = (~(ex3_sh_lvl2[66] | ex3_sh_lvl2[67]));
//------------------------------------------
assign ex3_g1o4[0] = (~(ex3_g1o2_b[0] & ex3_g1o2_b[1]));
assign ex3_g1o4[1] = (~(ex3_g1o2_b[2] & ex3_g1o2_b[3]));
assign ex3_g1o4[2] = (~(ex3_g1o2_b[4] & ex3_g1o2_b[5]));
assign ex3_g1o4[3] = (~(ex3_g1o2_b[6] & ex3_g1o2_b[7]));
assign ex3_g2o4[0] = (~(ex3_g2o2_b[0] & ex3_g2o2_b[1]));
assign ex3_g2o4[1] = (~(ex3_g2o2_b[2] & ex3_g2o2_b[3]));
assign ex3_g2o4[2] = (~(ex3_g2o2_b[4] & ex3_g2o2_b[5]));
assign ex3_g2o4[3] = (~(ex3_g2o2_b[6] & ex3_g2o2_b[7]));
assign ex3_g3o4[0] = (~(ex3_g3o2_b[0] & ex3_g3o2_b[1]));
assign ex3_g3o4[1] = (~(ex3_g3o2_b[2] & ex3_g3o2_b[3]));
assign ex3_g3o4[2] = (~(ex3_g3o2_b[4] & ex3_g3o2_b[5]));
assign ex3_g3o4[3] = (~(ex3_g3o2_b[6] & ex3_g3o2_b[7]));
assign ex3_g4o4[0] = (~(ex3_g4o2_b[0] & ex3_g4o2_b[1]));
assign ex3_g4o4[1] = (~(ex3_g4o2_b[2] & ex3_g4o2_b[3]));
assign ex3_g4o4[2] = (~(ex3_g4o2_b[4] & ex3_g4o2_b[5]));
assign ex3_g4o4[3] = (~(ex3_g4o2_b[6] & ex3_g4o2_b[7]));
//---------------------------------------------
assign ex3_g0o8_b[0] = (~(ex3_sh_lvl2[0] | ex3_sh_lvl2[1]));
assign ex3_g0o8_b[1] = (~(ex3_sh_lvl2[2] | ex3_sh_lvl2[3]));
assign ex3_g1o8_b[0] = (~(ex3_g1o4[0] | ex3_g1o4[1]));
assign ex3_g1o8_b[1] = (~(ex3_g1o4[2] | ex3_g1o4[3]));
assign ex3_g2o8_b[0] = (~(ex3_g2o4[0] | ex3_g2o4[1]));
assign ex3_g2o8_b[1] = (~(ex3_g2o4[2] | ex3_g2o4[3]));
assign ex3_g3o8_b[0] = (~(ex3_g3o4[0] | ex3_g3o4[1]));
assign ex3_g3o8_b[1] = (~(ex3_g3o4[2] | ex3_g3o4[3]));
assign ex3_g4o8_b[0] = (~(ex3_g4o4[0] | ex3_g4o4[1]));
assign ex3_g4o8_b[1] = (~(ex3_g4o4[2] | ex3_g4o4[3]));
//------------------------------------------------
assign ex3_o16[0] = (~(ex3_g0o8_b[0] & ex3_g0o8_b[1]));
assign ex3_o16[1] = (~(ex3_g1o8_b[0] & ex3_g1o8_b[1]));
assign ex3_o16[2] = (~(ex3_g2o8_b[0] & ex3_g2o8_b[1]));
assign ex3_o16[3] = (~(ex3_g3o8_b[0] & ex3_g3o8_b[1]));
assign ex3_o16[4] = (~(ex3_g4o8_b[0] & ex3_g4o8_b[1]));
//------------------------------------------------
assign ex3_o16_b[0] = (~(ex3_o16[0]));
assign ex3_o16_b[1] = (~(ex3_o16[1]));
assign ex3_o16_b[2] = (~(ex3_o16[2]));
assign ex3_o16_b[3] = (~(ex3_o16[3]));
assign ex3_o16_b[4] = (~(ex3_o16[4]));
//------------------------------------------------
assign ex3_sticky_or16[0] = (~(ex3_o16_b[0]));
assign ex3_sticky_or16[1] = (~(ex3_o16_b[1]));
assign ex3_sticky_or16[2] = (~(ex3_o16_b[2]));
assign ex3_sticky_or16[3] = (~(ex3_o16_b[3]));
assign ex3_sticky_or16[4] = (~(ex3_o16_b[4]));
endmodule |
module rv_prisel(
cond,
din,
dout
);
parameter q_num_entries_g = 16;
parameter q_dat_width_g = 7;
input [0:q_num_entries_g-1] cond;
input [0:q_dat_width_g*q_num_entries_g-1] din;
output [0:q_dat_width_g-1] dout;
wire [0:q_dat_width_g-1] q_dat_l1[0:7];
wire [0:q_dat_width_g-1] q_dat_l1a[0:7];
wire [0:q_dat_width_g-1] q_dat_l1b[0:7];
wire [0:q_dat_width_g-1] q_dat_l2[0:3];
wire [0:q_dat_width_g-1] q_dat_l2a[0:3];
wire [0:q_dat_width_g-1] q_dat_l2b[0:3];
wire [0:q_dat_width_g-1] q_dat_l4[0:1];
wire [0:q_dat_width_g-1] q_dat_l4a[0:1];
wire [0:q_dat_width_g-1] q_dat_l4b[0:1];
wire [0:q_dat_width_g-1] q_dat_l8a;
wire [0:q_dat_width_g-1] q_dat_l8b;
wire [0:q_dat_width_g-1] q_dat_l8;
wire [0:7] selval1_b;
wire [0:7] selpri1;
wire [0:7] selpri1_b;
wire [0:3] selval2;
wire [0:3] selpri2;
wire [0:3] selpri2_b;
wire [0:1] selval4_b;
wire [0:1] selpri4;
wire [0:1] selpri4_b;
wire selval8;
wire selpri8;
wire selpri8_b;
(* analysis_not_referenced="true" *)
wire selpri1_unused;
(* analysis_not_referenced="true" *)
wire selpri1_b_unused;
(* analysis_not_referenced="true" *)
wire q_dat_l1_unused;
parameter aryoff = q_dat_width_g;
assign selval1_b[0] = ~(cond[0] | cond[1]);
assign selval1_b[1] = ~(cond[2] | cond[3]);
assign selval1_b[2] = ~(cond[4] | cond[5]);
assign selval1_b[3] = ~(cond[6] | cond[7]);
generate
if (q_num_entries_g == 8)
begin : selval1_gen08
assign selval1_b[4] = 1'b1;
assign selval1_b[5] = 1'b1;
assign selval1_b[6] = 1'b1;
assign selval1_b[7] = 1'b1;
end
endgenerate
generate
if (q_num_entries_g == 12)
begin : selval1_gen0
assign selval1_b[4] = ~(cond[8] | cond[9]);
assign selval1_b[5] = ~(cond[10] | cond[11]);
assign selval1_b[6] = 1'b1;
assign selval1_b[7] = 1'b1;
end
endgenerate
generate
if (q_num_entries_g == 16)
begin : selval1_gen1
assign selval1_b[4] = ~(cond[8] | cond[9]);
assign selval1_b[5] = ~(cond[10] | cond[11]);
assign selval1_b[6] = ~(cond[12] | cond[13]);
assign selval1_b[7] = ~(cond[14] | cond[15]);
end
endgenerate
assign selpri1_b[0] = (~cond[1]);
assign selpri1_b[1] = (~cond[3]);
assign selpri1_b[2] = (~cond[5]);
assign selpri1_b[3] = (~cond[7]);
generate
if (q_num_entries_g == 8)
begin : selpri1_gen08
assign selpri1_b[4] = 1'b1;
assign selpri1_b[5] = 1'b1;
assign selpri1_b[6] = 1'b1;
assign selpri1_b[7] = 1'b1;
assign selpri1_b_unused = selpri1_b[4] | selpri1_b[5] | selpri1_b[6] | selpri1_b[7] ;
end
endgenerate
generate
if (q_num_entries_g == 12)
begin : selpri1_gen0
assign selpri1_b[4] = (~cond[9]);
assign selpri1_b[5] = (~cond[11]);
assign selpri1_b[6] = 1'b1;
assign selpri1_b[7] = 1'b1;
assign selpri1_b_unused = selpri1_b[6] | selpri1_b[7] ;
end
endgenerate
generate
if (q_num_entries_g == 16)
begin : selpri1_gen1
assign selpri1_b[4] = (~cond[9]);
assign selpri1_b[5] = (~cond[11]);
assign selpri1_b[6] = (~cond[13]);
assign selpri1_b[7] = (~cond[15]);
assign selpri1_b_unused =1'b0;
end
endgenerate
assign selpri1[0] = cond[1];
assign selpri1[1] = cond[3];
assign selpri1[2] = cond[5];
assign selpri1[3] = cond[7];
generate
if (q_num_entries_g == 8)
begin : selpri1_gen0b8
assign selpri1[4] = 1'b0;
assign selpri1[5] = 1'b0;
assign selpri1[6] = 1'b0;
assign selpri1[7] = 1'b0;
assign selpri1_unused = selpri1[4] | selpri1[5] | selpri1[6] | selpri1[7] ;
end
endgenerate
generate
if (q_num_entries_g == 12)
begin : selpri1_gen0b
assign selpri1[4] = cond[9];
assign selpri1[5] = cond[11];
assign selpri1[6] = 1'b0;
assign selpri1[7] = 1'b0;
assign selpri1_unused = selpri1[6] | selpri1[7];
end
endgenerate
generate
if (q_num_entries_g == 16)
begin : selpri1_gen1b
assign selpri1[4] = cond[9];
assign selpri1[5] = cond[11];
assign selpri1[6] = cond[13];
assign selpri1[7] = cond[15];
assign selpri1_unused=1'b0;
end
endgenerate
assign selval2[0] = ~(selval1_b[0] & selval1_b[1]);
assign selval2[1] = ~(selval1_b[2] & selval1_b[3]);
assign selval2[2] = ~(selval1_b[4] & selval1_b[5]);
assign selval2[3] = ~(selval1_b[6] & selval1_b[7]);
assign selpri2[0] = (~selval1_b[1]);
assign selpri2[1] = (~selval1_b[3]);
assign selpri2[2] = (~selval1_b[5]);
assign selpri2[3] = (~selval1_b[7]);
assign selpri2_b[0] = selval1_b[1];
assign selpri2_b[1] = selval1_b[3];
assign selpri2_b[2] = selval1_b[5];
assign selpri2_b[3] = selval1_b[7];
assign selval4_b[0] = ~(selval2[0] | selval2[1]);
assign selval4_b[1] = ~(selval2[2] | selval2[3]);
assign selpri4_b[0] = (~selval2[1]);
assign selpri4_b[1] = (~selval2[3]);
assign selpri4[0] = selval2[1];
assign selpri4[1] = selval2[3];
assign selval8 = ~(selval4_b[0] & selval4_b[1]);
assign selpri8 = (~selval4_b[1]);
assign selpri8_b = selval4_b[1];
//-------------------------------------------------------------------------------------------------------
// Instruction Muxing
//-------------------------------------------------------------------------------------------------------
// Level 1
// 01 23 45 67 89 1011 1213 1415
assign q_dat_l1a[0] = ~(din[0*aryoff:0*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[0]}});
assign q_dat_l1b[0] = ~(din[1*aryoff:1*aryoff+aryoff-1] & {q_dat_width_g{selpri1[0]}});
assign q_dat_l1[0] = ~(q_dat_l1a[0] & q_dat_l1b[0]);
assign q_dat_l1a[1] = ~(din[2*aryoff:2*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[1]}});
assign q_dat_l1b[1] = ~(din[3*aryoff:3*aryoff+aryoff-1] & {q_dat_width_g{selpri1[1]}});
assign q_dat_l1[1] = ~(q_dat_l1a[1] & q_dat_l1b[1]);
assign q_dat_l1a[2] = ~(din[4*aryoff:4*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[2]}});
assign q_dat_l1b[2] = ~(din[5*aryoff:5*aryoff+aryoff-1] & {q_dat_width_g{selpri1[2]}});
assign q_dat_l1[2] = ~(q_dat_l1a[2] & q_dat_l1b[2]);
assign q_dat_l1a[3] = ~(din[6*aryoff:6*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[3]}});
assign q_dat_l1b[3] = ~(din[7*aryoff:7*aryoff+aryoff-1] & {q_dat_width_g{selpri1[3]}});
assign q_dat_l1[3] = ~(q_dat_l1a[3] & q_dat_l1b[3]);
generate
if (q_num_entries_g == 8)
begin : l1_gen8
assign q_dat_l1a[4] = {q_dat_width_g{1'b0}};
assign q_dat_l1b[4] = {q_dat_width_g{1'b0}};
assign q_dat_l1[4] = {q_dat_width_g{1'b0}};
assign q_dat_l1a[5] = {q_dat_width_g{1'b0}};
assign q_dat_l1b[5] = {q_dat_width_g{1'b0}};
assign q_dat_l1[5] = {q_dat_width_g{1'b0}};
assign q_dat_l1a[6] = {q_dat_width_g{1'b0}};
assign q_dat_l1b[6] = {q_dat_width_g{1'b0}};
assign q_dat_l1[6] = {q_dat_width_g{1'b0}};
assign q_dat_l1a[7] = {q_dat_width_g{1'b0}};
assign q_dat_l1b[7] = {q_dat_width_g{1'b0}};
assign q_dat_l1[7] = {q_dat_width_g{1'b0}};
assign q_dat_l1_unused = (|q_dat_l1a[4]) | (|q_dat_l1a[5]) | (|q_dat_l1a[6]) | (|q_dat_l1a[7]) |
(|q_dat_l1b[4]) | (|q_dat_l1b[5]) | (|q_dat_l1b[6]) | (|q_dat_l1b[7]) |
(|q_dat_l1[4]) | (|q_dat_l1[5]) | (|q_dat_l1[6]) | (|q_dat_l1[7]) ;
end
endgenerate
generate
if (q_num_entries_g == 12)
begin : l1_gen12
assign q_dat_l1a[4] = ~(din[8*aryoff:8*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[4]}});
assign q_dat_l1b[4] = ~(din[9*aryoff:9*aryoff+aryoff-1] & {q_dat_width_g{selpri1[4]}});
assign q_dat_l1[4] = ~(q_dat_l1a[4] & q_dat_l1b[4]);
assign q_dat_l1a[5] = ~(din[10*aryoff:10*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[5]}});
assign q_dat_l1b[5] = ~(din[11*aryoff:11*aryoff+aryoff-1] & {q_dat_width_g{selpri1[5]}});
assign q_dat_l1[5] = ~(q_dat_l1a[5] & q_dat_l1b[5]);
assign q_dat_l1a[6] = {q_dat_width_g{1'b0}};
assign q_dat_l1b[6] = {q_dat_width_g{1'b0}};
assign q_dat_l1[6] = {q_dat_width_g{1'b0}};
assign q_dat_l1a[7] = {q_dat_width_g{1'b0}};
assign q_dat_l1b[7] = {q_dat_width_g{1'b0}};
assign q_dat_l1[7] = {q_dat_width_g{1'b0}};
assign q_dat_l1_unused = (|q_dat_l1a[6]) | (|q_dat_l1a[7]) |
(|q_dat_l1b[6]) | (|q_dat_l1b[7]) |
(|q_dat_l1[6]) | (|q_dat_l1[7]) ;
end
endgenerate
generate
if (q_num_entries_g == 16)
begin : l1_gen16
assign q_dat_l1a[4] = ~(din[8*aryoff:8*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[4]}});
assign q_dat_l1b[4] = ~(din[9*aryoff:9*aryoff+aryoff-1] & {q_dat_width_g{selpri1[4]}});
assign q_dat_l1[4] = ~(q_dat_l1a[4] & q_dat_l1b[4]);
assign q_dat_l1a[5] = ~(din[10*aryoff:10*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[5]}});
assign q_dat_l1b[5] = ~(din[11*aryoff:11*aryoff+aryoff-1] & {q_dat_width_g{selpri1[5]}});
assign q_dat_l1[5] = ~(q_dat_l1a[5] & q_dat_l1b[5]);
assign q_dat_l1a[6] = ~(din[12*aryoff:12*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[6]}});
assign q_dat_l1b[6] = ~(din[13*aryoff:13*aryoff+aryoff-1] & {q_dat_width_g{selpri1[6]}});
assign q_dat_l1[6] = ~(q_dat_l1a[6] & q_dat_l1b[6]);
assign q_dat_l1a[7] = ~(din[14*aryoff:14*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[7]}});
assign q_dat_l1b[7] = ~(din[15*aryoff:15*aryoff+aryoff-1] & {q_dat_width_g{selpri1[7]}});
assign q_dat_l1[7] = ~(q_dat_l1a[7] & q_dat_l1b[7]);
assign q_dat_l1_unused = 1'b0;
end
endgenerate
// Level 2
// 0123 4567 891011 12131415
assign q_dat_l2a[0] = ~(q_dat_l1[0] & {q_dat_width_g{selpri2_b[0]}});
assign q_dat_l2b[0] = ~(q_dat_l1[1] & {q_dat_width_g{selpri2[0]}});
assign q_dat_l2[0] = ~(q_dat_l2a[0] & q_dat_l2b[0]);
assign q_dat_l2a[1] = ~(q_dat_l1[2] & {q_dat_width_g{selpri2_b[1]}});
assign q_dat_l2b[1] = ~(q_dat_l1[3] & {q_dat_width_g{selpri2[1]}});
assign q_dat_l2[1] = ~(q_dat_l2a[1] & q_dat_l2b[1]);
assign q_dat_l2a[2] = ~(q_dat_l1[4] & {q_dat_width_g{selpri2_b[2]}});
assign q_dat_l2b[2] = ~(q_dat_l1[5] & {q_dat_width_g{selpri2[2]}});
assign q_dat_l2[2] = ~(q_dat_l2a[2] & q_dat_l2b[2]);
assign q_dat_l2a[3] = ~(q_dat_l1[6] & {q_dat_width_g{selpri2_b[3]}});
assign q_dat_l2b[3] = ~(q_dat_l1[7] & {q_dat_width_g{selpri2[3]}});
assign q_dat_l2[3] = ~(q_dat_l2a[3] & q_dat_l2b[3]);
// Level 4
// 01234567 89101112131415
assign q_dat_l4a[0] = ~(q_dat_l2[0] & {q_dat_width_g{selpri4_b[0]}});
assign q_dat_l4b[0] = ~(q_dat_l2[1] & {q_dat_width_g{selpri4[0]}});
assign q_dat_l4[0] = ~(q_dat_l4a[0] & q_dat_l4b[0]);
assign q_dat_l4a[1] = ~(q_dat_l2[2] & {q_dat_width_g{selpri4_b[1]}});
assign q_dat_l4b[1] = ~(q_dat_l2[3] & {q_dat_width_g{selpri4[1]}});
assign q_dat_l4[1] = ~(q_dat_l4a[1] & q_dat_l4b[1]);
// Level 8
// 0123456789101112131415
assign q_dat_l8a = ~(q_dat_l4[0] & {q_dat_width_g{selpri8_b}});
assign q_dat_l8b = ~(q_dat_l4[1] & {q_dat_width_g{selpri8}});
assign q_dat_l8 = ~(q_dat_l8a & q_dat_l8b);
assign dout = q_dat_l8 & {q_dat_width_g{selval8}};
endmodule // rv_prisel |
module iuq_rn_map_inc #(
parameter SIZE = 7,
parameter WRAP = 40)
(
inc,
i,
o
);
input [0:1] inc;
input [0:SIZE-1] i;
output [0:SIZE-1] o;
localparam [0:31] value_1 = 32'h00000001;
wire [0:SIZE] a;
wire [0:SIZE] b;
wire [0:SIZE] rslt;
wire rollover;
wire rollover_m1;
wire inc_1;
wire inc_2;
wire [0:1] wrap_sel;
// Increment by 1 or 2.
// Go back to zero at WRAP
// Flip bit zero when a rollover occurs
// eg 0...39, 64..103
assign a = {i[0:SIZE - 1], inc[1]};
assign b = {{SIZE-1{1'b0}}, inc[0], inc[1]};
assign rslt = a + b;
assign rollover = i[0:SIZE - 1] == WRAP;
assign rollover_m1 = i[0:SIZE - 1] == WRAP - 1;
assign inc_1 = inc[0] ^ inc[1];
assign inc_2 = inc[0] & inc[1];
assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2);
assign wrap_sel[1] = rollover & inc_2;
assign o[0:SIZE - 1] = (wrap_sel[0:1] == 2'b10) ? {SIZE{1'b0}} :
(wrap_sel[0:1] == 2'b01) ? value_1[32-SIZE:31] :
rslt[0:SIZE - 1];
endmodule |
module fu_eie(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
f_eie_si,
f_eie_so,
ex2_act,
f_byp_eie_ex2_a_expo,
f_byp_eie_ex2_c_expo,
f_byp_eie_ex2_b_expo,
f_pic_ex2_from_integer,
f_pic_ex2_fsel,
f_pic_ex3_frsp_ue1,
f_alg_ex3_sel_byp,
f_fmt_ex3_fsel_bsel,
f_pic_ex3_force_sel_bexp,
f_pic_ex3_sp_b,
f_pic_ex3_math_bzer_b,
f_eie_ex3_tbl_expo,
f_eie_ex3_lt_bias,
f_eie_ex3_eq_bias_m1,
f_eie_ex3_wd_ov,
f_eie_ex3_dw_ov,
f_eie_ex3_wd_ov_if,
f_eie_ex3_dw_ov_if,
f_eie_ex3_lzo_expo,
f_eie_ex3_b_expo,
f_eie_ex3_use_bexp,
f_eie_ex4_iexp
);
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input [2:3] delay_lclkr; // tidn,
input [2:3] mpw1_b; // tidn,
input [0:0] mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input f_eie_si; // perv
output f_eie_so; // perv
input ex2_act; // act
input [1:13] f_byp_eie_ex2_a_expo;
input [1:13] f_byp_eie_ex2_c_expo;
input [1:13] f_byp_eie_ex2_b_expo;
input f_pic_ex2_from_integer;
input f_pic_ex2_fsel;
input f_pic_ex3_frsp_ue1;
input f_alg_ex3_sel_byp;
input f_fmt_ex3_fsel_bsel;
input f_pic_ex3_force_sel_bexp;
input f_pic_ex3_sp_b;
input f_pic_ex3_math_bzer_b;
output [1:13] f_eie_ex3_tbl_expo;
output f_eie_ex3_lt_bias; //f_pic
output f_eie_ex3_eq_bias_m1; //f_pic
output f_eie_ex3_wd_ov; //f_pic
output f_eie_ex3_dw_ov; //f_pic
output f_eie_ex3_wd_ov_if; //f_pic
output f_eie_ex3_dw_ov_if; //f_pic
output [1:13] f_eie_ex3_lzo_expo; //dlza to lzo
output [1:13] f_eie_ex3_b_expo; //dlza to lzo
output f_eie_ex3_use_bexp;
output [1:13] f_eie_ex4_iexp; //deov to lzasub
// end ports
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire sg_0;
wire thold_0_b;
wire thold_0;
wire force_t;
wire ex3_act;
wire [0:3] act_spare_unused;
//-----------------
wire [0:4] act_so; //SCAN
wire [0:4] act_si; //SCAN
wire [0:12] ex3_bop_so; //SCAN
wire [0:12] ex3_bop_si; //SCAN
wire [0:12] ex3_pop_so; //SCAN
wire [0:12] ex3_pop_si; //SCAN
wire [0:6] ex3_ctl_so; //SCAN
wire [0:6] ex3_ctl_si; //SCAN
wire [0:13] ex4_iexp_so; //SCAN
wire [0:13] ex4_iexp_si; //SCAN
//-----------------
wire [1:13] ex2_a_expo;
wire [1:13] ex2_c_expo;
wire [1:13] ex2_b_expo;
wire [1:13] ex2_ep56_sum;
wire [1:12] ex2_ep56_car;
wire [1:13] ex2_ep56_p;
wire [2:12] ex2_ep56_g;
wire [2:11] ex2_ep56_t;
wire [1:13] ex2_ep56_s;
wire [2:12] ex2_ep56_c;
wire [1:13] ex2_p_expo_adj;
wire [1:13] ex2_from_k;
wire [1:13] ex2_b_expo_adj;
wire [1:13] ex3_p_expo;
wire [1:13] ex3_b_expo;
wire [1:13] ex3_iexp;
wire [1:13] ex3_b_expo_adj;
wire [1:13] ex3_p_expo_adj;
wire [1:13] ex4_iexp;
wire ex2_wd_ge_bot;
wire ex2_dw_ge_bot;
wire ex2_ge_2048;
wire ex2_ge_1024;
wire ex2_dw_ge_mid;
wire ex2_wd_ge_mid;
wire ex2_dw_ge;
wire ex2_wd_ge;
wire ex2_dw_eq_top;
wire ex2_wd_eq_bot;
wire ex2_wd_eq;
wire ex2_dw_eq;
wire ex3_iexp_b_sel;
wire ex3_dw_ge;
wire ex3_wd_ge;
wire ex3_wd_eq;
wire ex3_dw_eq;
wire ex3_fsel;
wire ex4_sp_b;
wire [1:13] ex3_b_expo_fixed; //experiment sp_den/dp_fmt
wire ex2_ge_bias;
wire ex2_lt_bias;
wire ex2_eq_bias_m1;
wire ex3_lt_bias;
wire ex3_eq_bias_m1;
wire [2:12] ex2_ep56_g2;
wire [2:10] ex2_ep56_t2;
wire [2:12] ex2_ep56_g4;
wire [2:8] ex2_ep56_t4;
wire [2:12] ex2_ep56_g8;
wire [2:4] ex2_ep56_t8;
////############################################
////# pervasive
////############################################
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
////############################################
////# ACT LATCHES
////############################################
tri_rlmreg_p #(.WIDTH(5), .NEEDS_SRESET(0)) act_lat(
.force_t(force_t), //tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[2]), //tidn,
.mpw1_b(mpw1_b[2]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable),
.scout(act_so),
.scin(act_si),
//-----------------
.din({ act_spare_unused[0],
act_spare_unused[1],
ex2_act,
act_spare_unused[2],
act_spare_unused[3]}),
//-----------------
.dout({ act_spare_unused[0],
act_spare_unused[1],
ex3_act,
act_spare_unused[2],
act_spare_unused[3]})
);
////##############################################
////# EX2 latch inputs from rf1
////##############################################
assign ex2_a_expo[1:13] = f_byp_eie_ex2_a_expo[1:13];
assign ex2_c_expo[1:13] = f_byp_eie_ex2_c_expo[1:13];
assign ex2_b_expo[1:13] = f_byp_eie_ex2_b_expo[1:13];
////##############################################
////# EX2 logic
////##############################################
////##-------------------------------------------------------------------------
////## Product Exponent adder (+56 scouta subtract gives final resutl)
////##-------------------------------------------------------------------------
// rebiased from 1023 to 4095 ... (append 2 ones)
// ep56 : Ec + Ea -bias
// ep0 : Ec + Ea -bias + 56 = Ec + Ea -4095 + 56
//
// 0_0011_1111_1111
// 1_1100_0000_0001 !1023 + 1 = -1023
// 11_1000 56
//------------------
// 1_1100_0011_1001 + Ea + Ec
//
// ex2_ep56_sum( 0) <= tiup; -- 1
assign ex2_ep56_sum[1] = (~(ex2_a_expo[1] ^ ex2_c_expo[1])); // 1
assign ex2_ep56_sum[2] = (~(ex2_a_expo[2] ^ ex2_c_expo[2])); // 1
assign ex2_ep56_sum[3] = (~(ex2_a_expo[3] ^ ex2_c_expo[3])); // 1
assign ex2_ep56_sum[4] = (ex2_a_expo[4] ^ ex2_c_expo[4]); // 0
assign ex2_ep56_sum[5] = (ex2_a_expo[5] ^ ex2_c_expo[5]); // 0
assign ex2_ep56_sum[6] = (ex2_a_expo[6] ^ ex2_c_expo[6]); // 0
assign ex2_ep56_sum[7] = (ex2_a_expo[7] ^ ex2_c_expo[7]); // 0
assign ex2_ep56_sum[8] = (~(ex2_a_expo[8] ^ ex2_c_expo[8])); // 1
assign ex2_ep56_sum[9] = (~(ex2_a_expo[9] ^ ex2_c_expo[9])); // 1
assign ex2_ep56_sum[10] = (~(ex2_a_expo[10] ^ ex2_c_expo[10])); // 1
assign ex2_ep56_sum[11] = (ex2_a_expo[11] ^ ex2_c_expo[11]); // 0
assign ex2_ep56_sum[12] = (ex2_a_expo[12] ^ ex2_c_expo[12]); // 0
assign ex2_ep56_sum[13] = (~(ex2_a_expo[13] ^ ex2_c_expo[13])); // 1
// ex2_ep56_car( 0) <= ( ex2_a_expo( 1) or ex2_c_expo( 1) ); -- 1
assign ex2_ep56_car[1] = (ex2_a_expo[2] | ex2_c_expo[2]); // 1
assign ex2_ep56_car[2] = (ex2_a_expo[3] | ex2_c_expo[3]); // 1
assign ex2_ep56_car[3] = (ex2_a_expo[4] & ex2_c_expo[4]); // 0
assign ex2_ep56_car[4] = (ex2_a_expo[5] & ex2_c_expo[5]); // 0
assign ex2_ep56_car[5] = (ex2_a_expo[6] & ex2_c_expo[6]); // 0
assign ex2_ep56_car[6] = (ex2_a_expo[7] & ex2_c_expo[7]); // 0
assign ex2_ep56_car[7] = (ex2_a_expo[8] | ex2_c_expo[8]); // 1
assign ex2_ep56_car[8] = (ex2_a_expo[9] | ex2_c_expo[9]); // 1
assign ex2_ep56_car[9] = (ex2_a_expo[10] | ex2_c_expo[10]); // 1
assign ex2_ep56_car[10] = (ex2_a_expo[11] & ex2_c_expo[11]); // 0
assign ex2_ep56_car[11] = (ex2_a_expo[12] & ex2_c_expo[12]); // 0
assign ex2_ep56_car[12] = (ex2_a_expo[13] | ex2_c_expo[13]); // 1
assign ex2_ep56_p[1:12] = ex2_ep56_sum[1:12] ^ ex2_ep56_car[1:12];
assign ex2_ep56_p[13] = ex2_ep56_sum[13];
assign ex2_ep56_g[2:12] = ex2_ep56_sum[2:12] & ex2_ep56_car[2:12];
assign ex2_ep56_t[2:11] = ex2_ep56_sum[2:11] | ex2_ep56_car[2:11];
assign ex2_ep56_s[1:11] = ex2_ep56_p[1:11] ^ ex2_ep56_c[2:12];
assign ex2_ep56_s[12] = ex2_ep56_p[12];
assign ex2_ep56_s[13] = ex2_ep56_p[13];
assign ex2_ep56_g2[12] = ex2_ep56_g[12];
assign ex2_ep56_g2[11] = ex2_ep56_g[11] | (ex2_ep56_t[11] & ex2_ep56_g[12]);
assign ex2_ep56_g2[10] = ex2_ep56_g[10] | (ex2_ep56_t[10] & ex2_ep56_g[11]);
assign ex2_ep56_g2[9] = ex2_ep56_g[9] | (ex2_ep56_t[9] & ex2_ep56_g[10]);
assign ex2_ep56_g2[8] = ex2_ep56_g[8] | (ex2_ep56_t[8] & ex2_ep56_g[9]);
assign ex2_ep56_g2[7] = ex2_ep56_g[7] | (ex2_ep56_t[7] & ex2_ep56_g[8]);
assign ex2_ep56_g2[6] = ex2_ep56_g[6] | (ex2_ep56_t[6] & ex2_ep56_g[7]);
assign ex2_ep56_g2[5] = ex2_ep56_g[5] | (ex2_ep56_t[5] & ex2_ep56_g[6]);
assign ex2_ep56_g2[4] = ex2_ep56_g[4] | (ex2_ep56_t[4] & ex2_ep56_g[5]);
assign ex2_ep56_g2[3] = ex2_ep56_g[3] | (ex2_ep56_t[3] & ex2_ep56_g[4]);
assign ex2_ep56_g2[2] = ex2_ep56_g[2] | (ex2_ep56_t[2] & ex2_ep56_g[3]);
// ex2_ep56_g2( 1) <= ex2_ep56_g( 1) or (ex2_ep56_t( 1) and ex2_ep56_g( 2)) ;
assign ex2_ep56_t2[10] = (ex2_ep56_t[10] & ex2_ep56_t[11]);
assign ex2_ep56_t2[9] = (ex2_ep56_t[9] & ex2_ep56_t[10]);
assign ex2_ep56_t2[8] = (ex2_ep56_t[8] & ex2_ep56_t[9]);
assign ex2_ep56_t2[7] = (ex2_ep56_t[7] & ex2_ep56_t[8]);
assign ex2_ep56_t2[6] = (ex2_ep56_t[6] & ex2_ep56_t[7]);
assign ex2_ep56_t2[5] = (ex2_ep56_t[5] & ex2_ep56_t[6]);
assign ex2_ep56_t2[4] = (ex2_ep56_t[4] & ex2_ep56_t[5]);
assign ex2_ep56_t2[3] = (ex2_ep56_t[3] & ex2_ep56_t[4]);
assign ex2_ep56_t2[2] = (ex2_ep56_t[2] & ex2_ep56_t[3]);
// ex2_ep56_t2( 1) <= (ex2_ep56_t( 1) and ex2_ep56_t( 2)) ;
assign ex2_ep56_g4[12] = ex2_ep56_g2[12];
assign ex2_ep56_g4[11] = ex2_ep56_g2[11];
assign ex2_ep56_g4[10] = ex2_ep56_g2[10] | (ex2_ep56_t2[10] & ex2_ep56_g2[12]);
assign ex2_ep56_g4[9] = ex2_ep56_g2[9] | (ex2_ep56_t2[9] & ex2_ep56_g2[11]);
assign ex2_ep56_g4[8] = ex2_ep56_g2[8] | (ex2_ep56_t2[8] & ex2_ep56_g2[10]);
assign ex2_ep56_g4[7] = ex2_ep56_g2[7] | (ex2_ep56_t2[7] & ex2_ep56_g2[9]);
assign ex2_ep56_g4[6] = ex2_ep56_g2[6] | (ex2_ep56_t2[6] & ex2_ep56_g2[8]);
assign ex2_ep56_g4[5] = ex2_ep56_g2[5] | (ex2_ep56_t2[5] & ex2_ep56_g2[7]);
assign ex2_ep56_g4[4] = ex2_ep56_g2[4] | (ex2_ep56_t2[4] & ex2_ep56_g2[6]);
assign ex2_ep56_g4[3] = ex2_ep56_g2[3] | (ex2_ep56_t2[3] & ex2_ep56_g2[5]);
assign ex2_ep56_g4[2] = ex2_ep56_g2[2] | (ex2_ep56_t2[2] & ex2_ep56_g2[4]);
// ex2_ep56_g4( 1) <= ex2_ep56_g2( 1) or (ex2_ep56_t2( 1) and ex2_ep56_g2( 3)) ;
assign ex2_ep56_t4[8] = (ex2_ep56_t2[8] & ex2_ep56_t2[10]);
assign ex2_ep56_t4[7] = (ex2_ep56_t2[7] & ex2_ep56_t2[9]);
assign ex2_ep56_t4[6] = (ex2_ep56_t2[6] & ex2_ep56_t2[8]);
assign ex2_ep56_t4[5] = (ex2_ep56_t2[5] & ex2_ep56_t2[7]);
assign ex2_ep56_t4[4] = (ex2_ep56_t2[4] & ex2_ep56_t2[6]);
assign ex2_ep56_t4[3] = (ex2_ep56_t2[3] & ex2_ep56_t2[5]);
assign ex2_ep56_t4[2] = (ex2_ep56_t2[2] & ex2_ep56_t2[4]);
// ex2_ep56_t4( 1) <= (ex2_ep56_t2( 1) and ex2_ep56_t2( 3)) ;
assign ex2_ep56_g8[12] = ex2_ep56_g4[12];
assign ex2_ep56_g8[11] = ex2_ep56_g4[11];
assign ex2_ep56_g8[10] = ex2_ep56_g4[10];
assign ex2_ep56_g8[9] = ex2_ep56_g4[9];
assign ex2_ep56_g8[8] = ex2_ep56_g4[8] | (ex2_ep56_t4[8] & ex2_ep56_g4[12]);
assign ex2_ep56_g8[7] = ex2_ep56_g4[7] | (ex2_ep56_t4[7] & ex2_ep56_g4[11]);
assign ex2_ep56_g8[6] = ex2_ep56_g4[6] | (ex2_ep56_t4[6] & ex2_ep56_g4[10]);
assign ex2_ep56_g8[5] = ex2_ep56_g4[5] | (ex2_ep56_t4[5] & ex2_ep56_g4[9]);
assign ex2_ep56_g8[4] = ex2_ep56_g4[4] | (ex2_ep56_t4[4] & ex2_ep56_g4[8]);
assign ex2_ep56_g8[3] = ex2_ep56_g4[3] | (ex2_ep56_t4[3] & ex2_ep56_g4[7]);
assign ex2_ep56_g8[2] = ex2_ep56_g4[2] | (ex2_ep56_t4[2] & ex2_ep56_g4[6]);
// ex2_ep56_g8( 1) <= ex2_ep56_g4( 1) or (ex2_ep56_t4( 1) and ex2_ep56_g4( 5)) ;
assign ex2_ep56_t8[4] = (ex2_ep56_t4[4] & ex2_ep56_t4[8]);
assign ex2_ep56_t8[3] = (ex2_ep56_t4[3] & ex2_ep56_t4[7]);
assign ex2_ep56_t8[2] = (ex2_ep56_t4[2] & ex2_ep56_t4[6]);
// ex2_ep56_t8( 1) <= (ex2_ep56_t4( 1) and ex2_ep56_t4( 5)) ;
assign ex2_ep56_c[12] = ex2_ep56_g8[12];
assign ex2_ep56_c[11] = ex2_ep56_g8[11];
assign ex2_ep56_c[10] = ex2_ep56_g8[10];
assign ex2_ep56_c[9] = ex2_ep56_g8[9];
assign ex2_ep56_c[8] = ex2_ep56_g8[8];
assign ex2_ep56_c[7] = ex2_ep56_g8[7];
assign ex2_ep56_c[6] = ex2_ep56_g8[6];
assign ex2_ep56_c[5] = ex2_ep56_g8[5];
assign ex2_ep56_c[4] = ex2_ep56_g8[4] | (ex2_ep56_t8[4] & ex2_ep56_g8[12]);
assign ex2_ep56_c[3] = ex2_ep56_g8[3] | (ex2_ep56_t8[3] & ex2_ep56_g8[11]);
assign ex2_ep56_c[2] = ex2_ep56_g8[2] | (ex2_ep56_t8[2] & ex2_ep56_g8[10]);
// ex2_ep56_c( 1) <= ex2_ep56_g8( 1) or (ex2_ep56_t8( 1) and ex2_ep56_g8( 9)) ;
////##---------------------------------------
////## hold onto c_exponent for fsel
////##---------------------------------------
assign ex2_p_expo_adj[1:13] = (ex2_ep56_s[1:13] & {13{(~f_pic_ex2_fsel)}}) |
(ex2_c_expo[1:13] & {13{f_pic_ex2_fsel}});
////##---------------------------------------
////## select b exponent
////##---------------------------------------
// From integer exponent
// lsb is at position 162, and value = bias
// therefore set b_expo to (bias+162)
// 0_1111_1111_1111 1023 = bias
// 101_0010 162
// ---------------- ----
// 1_0000_0101_0001 4096+57
// 1 2345 6789 0123
assign ex2_from_k[1] = tidn; // 4096
assign ex2_from_k[2] = tidn; // 2048
assign ex2_from_k[3] = tiup; // 1024
assign ex2_from_k[4] = tidn; // 512
assign ex2_from_k[5] = tidn; // 256
assign ex2_from_k[6] = tiup; // 128
assign ex2_from_k[7] = tidn; // 64
assign ex2_from_k[8] = tiup; // 32
assign ex2_from_k[9] = tidn; // 16
assign ex2_from_k[10] = tidn; // 8
assign ex2_from_k[11] = tidn; // 4
assign ex2_from_k[12] = tidn; // 2
assign ex2_from_k[13] = tiup; // 1
assign ex2_b_expo_adj[1:13] = (ex2_from_k[1:13] & {13{f_pic_ex2_from_integer}}) |
(ex2_b_expo[1:13] & {13{(~f_pic_ex2_from_integer)}});
////##---------------------------------------
////## to integer overflow boundaries
////##---------------------------------------
// convert to signed_word:
// pos int ov ge 2**31 1023+31
// ov eq 2**30 * rnd_up 1023+30 <= just look at final MSB position
// neg int ov gt 2**31 1023+31
// neg int ov eq 2**31 1023+31 & frac[1:*] != 0
// convert to signed_doubleword:
// pos int ov ge 2**63 1023+63 1086
// ov eq 2**62 * rnd_up 1023+62 1085 <=== just look at final msb position
// neg int ov gt 2**63 1023+63 1086
// neg int ov eq 2**63 1023+63 1086 & frac[1:*] != 0;
//
// 0_0011_1111_1111 bias 1023
// 10_0000 32
// 0_0100 0001 1111 <=== ge
//
// 0_0011_1111_1111 bias 1023
// 1_1111 31
// 0_0100 0001 1110 <=== eq
//
// 0_0011_1111_1111 bias 1023
// 100_0000 64
// 0_0100 0011 1111 <==== ge 1087
//
// 0_0011_1111_1111 bias 1023
// 11_1111 63
// 0_0100 0011 1110 <==== eq 1086
//
// 1111
// 1 2345 6789 0123
//
// if exponent less than bias (1023)
// positive input if +rnd_up result = +ulp (ok) int 1
// positive input if -rnd_up result = +0 (ok) int 0
// negative input if +rnd_up result = -ulp (ok) int -1 (no increment)
// negative input if -rnd_up result = +0 <== ??force sign??
// normalizer shifts wrong (98)=1
assign ex2_wd_ge_bot = ex2_b_expo[9] & ex2_b_expo[10] & ex2_b_expo[11] & ex2_b_expo[12] & ex2_b_expo[13];
assign ex2_dw_ge_bot = ex2_b_expo[8] & ex2_wd_ge_bot;
assign ex2_ge_2048 = (~ex2_b_expo[1]) & ex2_b_expo[2];
assign ex2_ge_1024 = (~ex2_b_expo[1]) & ex2_b_expo[3];
assign ex2_dw_ge_mid = ex2_b_expo[4] | ex2_b_expo[5] | ex2_b_expo[6] | ex2_b_expo[7];
assign ex2_wd_ge_mid = ex2_b_expo[8] | ex2_dw_ge_mid;
assign ex2_dw_ge = (ex2_ge_2048) | (ex2_ge_1024 & ex2_dw_ge_mid) | (ex2_ge_1024 & ex2_dw_ge_bot);
assign ex2_wd_ge = (ex2_ge_2048) | (ex2_ge_1024 & ex2_wd_ge_mid) | (ex2_ge_1024 & ex2_wd_ge_bot);
assign ex2_dw_eq_top = (~ex2_b_expo[1]) & (~ex2_b_expo[2]) & ex2_b_expo[3] & (~ex2_b_expo[4]) & (~ex2_b_expo[5]) & (~ex2_b_expo[6]) & (~ex2_b_expo[7]);
assign ex2_wd_eq_bot = ex2_b_expo[9] & ex2_b_expo[10] & ex2_b_expo[11] & ex2_b_expo[12] & (~ex2_b_expo[13]);
assign ex2_wd_eq = ex2_dw_eq_top & (~ex2_b_expo[8]) & ex2_wd_eq_bot;
assign ex2_dw_eq = ex2_dw_eq_top & ex2_b_expo[8] & ex2_wd_eq_bot;
assign ex2_ge_bias = ((~ex2_b_expo[1]) & ex2_b_expo[2]) | ((~ex2_b_expo[1]) & ex2_b_expo[3]) | ((~ex2_b_expo[1]) & ex2_b_expo[4] & ex2_b_expo[5] & ex2_b_expo[6] & ex2_b_expo[7] & ex2_b_expo[8] & ex2_b_expo[9] & ex2_b_expo[10] & ex2_b_expo[11] & ex2_b_expo[12] & ex2_b_expo[13]); // for rnd_to_int
assign ex2_lt_bias = (~ex2_ge_bias);
// rnd-to-int nearest rounds up
// sign
// 2048
// 1024
// 512
// 256
// 128
// 64
// 32
// 16
// 8
// 4
assign ex2_eq_bias_m1 = (~ex2_b_expo[1]) & (~ex2_b_expo[2]) & (~ex2_b_expo[3]) & ex2_b_expo[4] & ex2_b_expo[5] & ex2_b_expo[6] & ex2_b_expo[7] & ex2_b_expo[8] & ex2_b_expo[9] & ex2_b_expo[10] & ex2_b_expo[11] & ex2_b_expo[12] & (~ex2_b_expo[13]); // 2
// 1
////##############################################
////# EX3 latches
////##############################################
tri_rlmreg_p #(.WIDTH(13), .NEEDS_SRESET(0)) ex3_bop_lat(
.force_t(force_t), //tidn,
.d_mode(tiup), //
.delay_lclkr(delay_lclkr[2]), //tidn,
.mpw1_b(mpw1_b[2]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex2_act),
.scout(ex3_bop_so),
.scin(ex3_bop_si),
//-----------------
.din(ex2_b_expo_adj[1:13]),
.dout(ex3_b_expo_adj[1:13]) //LAT--
);
tri_rlmreg_p #(.WIDTH(13), .NEEDS_SRESET(0)) ex3_pop_lat(
.force_t(force_t), //tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[2]), //tidn,
.mpw1_b(mpw1_b[2]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex2_act),
.scout(ex3_pop_so),
.scin(ex3_pop_si),
//-----------------
.din(ex2_p_expo_adj[1:13]),
.dout(ex3_p_expo_adj[1:13]) //LAT--
);
tri_rlmreg_p #(.WIDTH(7), .NEEDS_SRESET(0)) ex3_ctl_lat(
.force_t(force_t), //tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[2]), //tidn,
.mpw1_b(mpw1_b[2]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex2_act),
.scout(ex3_ctl_so),
.scin(ex3_ctl_si),
//-----------------
.din({ ex2_dw_ge,
ex2_wd_ge,
ex2_wd_eq,
ex2_dw_eq,
f_pic_ex2_fsel,
ex2_lt_bias,
ex2_eq_bias_m1}),
//-----------------
.dout({ex3_dw_ge, //LAT--
ex3_wd_ge, //LAT--
ex3_wd_eq, //LAT--
ex3_dw_eq, //LAT--
ex3_fsel, //LAT--
ex3_lt_bias, //LAT--
ex3_eq_bias_m1}) //LAT--
);
assign f_eie_ex3_lt_bias = ex3_lt_bias; //output --f_pic
assign f_eie_ex3_eq_bias_m1 = ex3_eq_bias_m1; //output --f_pic
assign ex3_p_expo[1:13] = ex3_p_expo_adj[1:13];
assign ex3_b_expo[1:13] = ex3_b_expo_adj[1:13];
assign f_eie_ex3_wd_ov = ex3_wd_ge; //output --f_pic
assign f_eie_ex3_dw_ov = ex3_dw_ge; //output --f_pic
assign f_eie_ex3_wd_ov_if = ex3_wd_eq; //output --f_pic
assign f_eie_ex3_dw_ov_if = ex3_dw_eq; //output --f_pic
assign f_eie_ex3_lzo_expo[1:13] = ex3_p_expo_adj[1:13]; //output --dlza for lzo
assign f_eie_ex3_b_expo[1:13] = ex3_b_expo[1:13];
assign f_eie_ex3_tbl_expo[1:13] = ex3_b_expo[1:13];
////##############################################
////# EX3 logic
////##############################################
// --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// --experiment sp_den/dp_fmt
// -- experimental -- (add 24 for bypass B cases) shift 24 positions to avoid shift right
// -- SP_den in DP format is normalized, but SP op must give denorm result.
// -- do not want to shift right in normalizer, scoutdent in aligner.
// -- ?? problem: LZO positions for bypass case :
// -- UE=0: set LZO 24 instead of LZO 0 .... ??? can [0:23] be an alias ???
// -- UE=1: always normalize, LZO does not matter
// --
// -- (changed from 24 to 26) for the offset
//
//
// ex3_bexp26(13) <= ex3_b_expo(13); -- 0001
// ex3_bexp26(12) <= not ex3_b_expo(12); -- 0002
// ex3_bexp26(11) <= ex3_b_expo(11) xor ex3_bexp26_c(12); -- 0004
// ex3_bexp26(10) <= not ex3_b_expo(10) xor ex3_bexp26_c(11) ; -- 0008
// ex3_bexp26(9) <= not ex3_b_expo(9) xor ex3_bexp26_c(10); -- 0016
// ex3_bexp26(1 to 8) <= ex3_b_expo(1 to 8) xor ex3_bexp26_c(2 to 9) ; -- 0032 ...
//
// ex3_bexpo26_9_o_10 <= ex3_b_expo(9) or ex3_b_expo(10) ;
//
// ex3_bexp26_c(12) <= ex3_b_expo(12);
// ex3_bexp26_c(11) <= ex3_b_expo(11) and ex3_b_expo(12);
// ex3_bexp26_c(10) <= ex3_b_expo(10) or (ex3_b_expo(11) and ex3_b_expo(12) );
// ex3_bexp26_c(9) <= ex3_bexpo26_9_o_10 or (ex3_b_expo(11) and ex3_b_expo(12) );
// ex3_bexp26_c(8) <= ex3_bexp26_gg(8) and ex3_bexp26_c(9);
// ex3_bexp26_c(7) <= ex3_bexp26_gg(7) and ex3_bexp26_c(9);
// ex3_bexp26_c(6) <= ex3_bexp26_gg(6) and ex3_bexp26_c(9);
// ex3_bexp26_c(5) <= ex3_bexp26_gg(5) and ex3_bexp26_c(9);
// ex3_bexp26_c(4) <= ex3_bexp26_gg(4) and ex3_bexp26_c(9);
// ex3_bexp26_c(3) <= ex3_bexp26_gg(3) and ex3_bexp26_c(9);
// ex3_bexp26_c(2) <= ex3_bexp26_gg(2) and ex3_bexp26_c(9);
//
// ex3_bexp26_gg2(8) <= ex3_b_expo(8) ;
// ex3_bexp26_gg2(7) <= ex3_b_expo(7) and ex3_b_expo(8) ;
// ex3_bexp26_gg2(6) <= ex3_b_expo(6) and ex3_b_expo(7) ;
// ex3_bexp26_gg2(5) <= ex3_b_expo(5) and ex3_b_expo(6) ;
// ex3_bexp26_gg2(4) <= ex3_b_expo(4) and ex3_b_expo(5) ;
// ex3_bexp26_gg2(3) <= ex3_b_expo(3) and ex3_b_expo(4) ;
// ex3_bexp26_gg2(2) <= ex3_b_expo(2) and ex3_b_expo(3) ;
//
// ex3_bexp26_gg4(8) <= ex3_bexp26_gg2(8) ;
// ex3_bexp26_gg4(7) <= ex3_bexp26_gg2(7) ;
// ex3_bexp26_gg4(6) <= ex3_bexp26_gg2(6) and ex3_bexp26_gg2(8) ;
// ex3_bexp26_gg4(5) <= ex3_bexp26_gg2(5) and ex3_bexp26_gg2(7) ;
// ex3_bexp26_gg4(4) <= ex3_bexp26_gg2(4) and ex3_bexp26_gg2(6) ;
// ex3_bexp26_gg4(3) <= ex3_bexp26_gg2(3) and ex3_bexp26_gg2(5) ;
// ex3_bexp26_gg4(2) <= ex3_bexp26_gg2(2) and ex3_bexp26_gg2(4) ;
//
// ex3_bexp26_gg(8) <= ex3_bexp26_gg4(8) ;
// ex3_bexp26_gg(7) <= ex3_bexp26_gg4(7) ;
// ex3_bexp26_gg(6) <= ex3_bexp26_gg4(6) ;
// ex3_bexp26_gg(5) <= ex3_bexp26_gg4(5) ;
// ex3_bexp26_gg(4) <= ex3_bexp26_gg4(4) and ex3_bexp26_gg4(8) ;
// ex3_bexp26_gg(3) <= ex3_bexp26_gg4(3) and ex3_bexp26_gg4(7) ;
// ex3_bexp26_gg(2) <= ex3_bexp26_gg4(2) and ex3_bexp26_gg4(6) ;
//
//
//
// ex3_b_expo_fixed(1 to 13) <= --experiment sp_den/dp_fmt
// ( ex3_b_expo(1 to 13) and (1 to 13 => f_pic_ex3_sp_b) ) or -- DP --experiment sp_den/dp_fmt
// ( ex3_bexp26(1 to 13) and (1 to 13 => not f_pic_ex3_sp_b) ) ; -- SP --experiment sp_den/dp_fmt
// --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
assign ex3_b_expo_fixed[1:13] = ex3_b_expo[1:13];
assign f_eie_ex3_use_bexp = ex3_iexp_b_sel;
//NAN/shOv
// fsel
assign ex3_iexp_b_sel = (f_alg_ex3_sel_byp & (~ex3_fsel) & f_pic_ex3_math_bzer_b) | f_fmt_ex3_fsel_bsel | f_pic_ex3_force_sel_bexp | f_pic_ex3_frsp_ue1; // by opcode
// frsp with ue=1 always does bypass because must normalize anyway
// if frsp(ue=1) has a shift unf, then loose bits and canot normalize)
assign ex3_iexp[1:13] = (ex3_b_expo_fixed[1:13] & {13{ex3_iexp_b_sel}}) |
(ex3_p_expo[1:13] & {13{(~ex3_iexp_b_sel)}}); //experiment sp_den/dp_fmt
////##############################################
////# EX4 latches
////##############################################
tri_rlmreg_p #(.WIDTH(14), .NEEDS_SRESET(0)) ex4_iexp_lat(
.force_t(force_t), //tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[3]), //tidn,
.mpw1_b(mpw1_b[3]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex3_act),
.scout(ex4_iexp_so),
.scin(ex4_iexp_si),
//-----------------
.din({f_pic_ex3_sp_b,
ex3_iexp[1:13]}),
//-----------------
.dout({ex4_sp_b, //LAT--
ex4_iexp[1:13]}) //LAT--
);
assign f_eie_ex4_iexp[1:13] = ex4_iexp[1:13]; //output--feov
////##############################################
////# EX4 logic
////##############################################
////############################################
////# scan
////############################################
assign ex3_bop_si[0:12] = {ex3_bop_so[1:12], f_eie_si};
assign ex3_pop_si[0:12] = {ex3_pop_so[1:12], ex3_bop_so[0]};
assign ex3_ctl_si[0:6] = {ex3_ctl_so[1:6], ex3_pop_so[0]};
assign ex4_iexp_si[0:13] = {ex4_iexp_so[1:13], ex3_ctl_so[0]};
assign act_si[0:4] = {act_so[1:4], ex4_iexp_so[0]};
assign f_eie_so = act_so[0];
endmodule |
module xu_alu(
//-------------------------------------------------------------------
// Clocks & Power
//-------------------------------------------------------------------
input [0:`NCLK_WIDTH-1] nclk,
inout vdd,
inout gnd,
//-------------------------------------------------------------------
// Pervasive
//-------------------------------------------------------------------
input d_mode_dc,
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input sg_0,
input scan_in,
output scan_out,
//-------------------------------------------------------------------
// Decode Interface
//-------------------------------------------------------------------
input dec_alu_ex1_act,
input [0:31] dec_alu_ex1_instr,
input dec_alu_ex1_sel_isel, // Critical!
input [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv,
input [0:1] dec_alu_ex2_add_ci_sel,
input dec_alu_ex1_sel_trap,
input dec_alu_ex1_sel_cmpl,
input dec_alu_ex1_sel_cmp,
input dec_alu_ex1_msb_64b_sel,
input dec_alu_ex1_xer_ov_en,
input dec_alu_ex1_xer_ca_en,
//-------------------------------------------------------------------
// Bypass Inputs
//-------------------------------------------------------------------
input [64-`GPR_WIDTH:63] byp_alu_ex2_rs1, // Source Data
input [64-`GPR_WIDTH:63] byp_alu_ex2_rs2,
input byp_alu_ex2_cr_bit, // CR bit for isel
input [0:9] byp_alu_ex2_xer,
//-------------------------------------------------------------------
// Bypass Outputs
//-------------------------------------------------------------------
output [64-`GPR_WIDTH:63] alu_byp_ex2_add_rt,
output [64-`GPR_WIDTH:63] alu_byp_ex3_rt,
output [0:3] alu_byp_ex3_cr,
output [0:9] alu_byp_ex3_xer,
output alu_dec_ex3_trap_val
);
localparam msb = 64 - `GPR_WIDTH;
// Latches
wire ex2_act_q; // input=>dec_alu_ex1_act ,act=>1'b1
wire ex2_sel_isel_q; // input=>dec_alu_ex1_sel_isel ,act=>dec_alu_ex1_act
wire ex2_msb_64b_sel_q; // input=>dec_alu_ex1_msb_64b_sel ,act=>dec_alu_ex1_act
wire ex2_sel_trap_q; // input=>dec_alu_ex1_sel_trap ,act=>dec_alu_ex1_act
wire ex2_sel_cmpl_q; // input=>dec_alu_ex1_sel_cmpl ,act=>dec_alu_ex1_act
wire ex2_sel_cmp_q; // input=>dec_alu_ex1_sel_cmp ,act=>dec_alu_ex1_act
wire [6:10] ex2_instr_6to10_q; // input=>dec_alu_ex1_instr(6 to 10) ,act=>dec_alu_ex1_act
wire ex2_xer_ov_en_q; // input=>dec_alu_ex1_xer_ov_en ,act=>dec_alu_ex1_act
wire ex2_xer_ca_en_q; // input=>dec_alu_ex1_xer_ca_en ,act=>dec_alu_ex1_act
wire ex3_add_ca_q; // input=>ex2_add_ca ,act=>ex2_act_q
wire ex2_add_ca;
wire ex3_add_ovf_q; // input=>ex2_add_ovf ,act=>ex2_act_q
wire ex2_add_ovf;
wire ex3_sel_rot_log_q; // input=>ex2_sel_rot_log ,act=>ex2_act_q
wire ex2_sel_rot_log;
wire [0:9] ex3_xer_q; // input=>byp_alu_ex2_xer(0 to 9) ,act=>ex2_act_q
wire ex3_xer_ov_en_q; // input=>ex2_xer_ov_en_q ,act=>ex2_act_q
wire ex3_xer_ca_en_q; // input=>ex2_xer_ca_en_q ,act=>ex2_act_q
// Scanchains
localparam ex2_act_offset = 3;
localparam ex2_sel_isel_offset = ex2_act_offset + 1;
localparam ex2_msb_64b_sel_offset = ex2_sel_isel_offset + 1;
localparam ex2_sel_trap_offset = ex2_msb_64b_sel_offset + 1;
localparam ex2_sel_cmpl_offset = ex2_sel_trap_offset + 1;
localparam ex2_sel_cmp_offset = ex2_sel_cmpl_offset + 1;
localparam ex2_instr_6to10_offset = ex2_sel_cmp_offset + 1;
localparam ex2_xer_ov_en_offset = ex2_instr_6to10_offset + 5;
localparam ex2_xer_ca_en_offset = ex2_xer_ov_en_offset + 1;
localparam ex3_add_ca_offset = ex2_xer_ca_en_offset + 1;
localparam ex3_add_ovf_offset = ex3_add_ca_offset + 1;
localparam ex3_sel_rot_log_offset = ex3_add_ovf_offset + 1;
localparam ex3_xer_offset = ex3_sel_rot_log_offset + 1;
localparam ex3_xer_ov_en_offset = ex3_xer_offset + 10;
localparam ex3_xer_ca_en_offset = ex3_xer_ov_en_offset + 1;
localparam scan_right = ex3_xer_ca_en_offset + 1;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
//!! bugspray include: xu_alu.bil;
// Signals
wire [msb:63] ex2_add_rs1;
wire [msb:63] ex2_add_rs2;
wire [msb:63] ex2_rot_rs0_b;
wire [msb:63] ex2_rot_rs1_b;
wire [msb:63] ex2_add_rt;
wire [msb:63] ex3_alu_rt;
wire ex3_rot_ca;
wire ex3_alu_ca;
wire ex2_add_ci;
wire [0:3] ex2_isel_fcn;
wire [0:3] ex2_isel_type;
wire ex3_alu_so;
//---------------------------------------------------------------
// Source Buffering
//---------------------------------------------------------------
assign ex2_add_rs1 = byp_alu_ex2_rs1;
assign ex2_add_rs2 = byp_alu_ex2_rs2;
assign ex2_rot_rs0_b = (~byp_alu_ex2_rs1);
assign ex2_rot_rs1_b = (~byp_alu_ex2_rs2);
//---------------------------------------------------------------
// Target Muxing/Buffering
//---------------------------------------------------------------
assign alu_byp_ex3_rt = ex3_alu_rt;
assign ex3_alu_ca = (ex3_sel_rot_log_q == 1'b1) ? ex3_rot_ca :
ex3_add_ca_q;
assign alu_byp_ex3_cr[3] = ex3_alu_so;
assign alu_byp_ex3_xer[0] = ex3_alu_so;
assign ex3_alu_so = (ex3_xer_ov_en_q == 1'b1) ? ex3_add_ovf_q | ex3_xer_q[0] :
ex3_xer_q[0];
assign alu_byp_ex3_xer[1] = (ex3_xer_ov_en_q == 1'b1) ? ex3_add_ovf_q :
ex3_xer_q[1];
assign alu_byp_ex3_xer[2] = (ex3_xer_ca_en_q == 1'b1) ? ex3_alu_ca :
ex3_xer_q[2];
assign alu_byp_ex3_xer[3:9] = ex3_xer_q[3:9];
assign alu_byp_ex2_add_rt = ex2_add_rt;
//---------------------------------------------------------------
// Add
//---------------------------------------------------------------
xu_alu_add add(
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[0]),
.scan_out(sov[0]),
.ex1_act(dec_alu_ex1_act),
.ex2_msb_64b_sel(ex2_msb_64b_sel_q),
.dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv),
.dec_alu_ex2_add_ci(ex2_add_ci),
.ex2_rs1(ex2_add_rs1),
.ex2_rs2(ex2_add_rs2),
.ex2_add_rt(ex2_add_rt),
.ex2_add_ovf(ex2_add_ovf),
.ex2_add_ca(ex2_add_ca)
);
//---------------------------------------------------------------
// Rotate / Logical
//---------------------------------------------------------------
assign ex2_add_ci = (dec_alu_ex2_add_ci_sel == 2'b10) ? byp_alu_ex2_xer[2] :
(dec_alu_ex2_add_ci_sel == 2'b01) ? 1'b1 :
1'b0;
tri_st_rot rot(
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.d_mode_dc(d_mode_dc),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[1]),
.scan_out(sov[1]),
.ex1_act(dec_alu_ex1_act),
.ex1_instr(dec_alu_ex1_instr),
.ex2_isel_fcn(ex2_isel_fcn),
.ex2_sel_rot_log(ex2_sel_rot_log),
// Source Inputs
.ex2_rs0_b(ex2_rot_rs0_b),
.ex2_rs1_b(ex2_rot_rs1_b),
// Other ALU Inputs for muxing
.ex2_alu_rt(ex2_add_rt),
// EX3 Bypass Tap
.ex3_rt(ex3_alu_rt),
.ex2_log_rt(),
// EX2 Bypass Tap (logicals only)
.ex3_xer_ca(ex3_rot_ca),
.ex3_cr_eq()
);
assign ex2_isel_type = {1'b0, (~(byp_alu_ex2_cr_bit)), byp_alu_ex2_cr_bit, 1'b1};
assign ex2_isel_fcn = ex2_sel_isel_q==1'b1 ? ex2_isel_type : 4'b0;
//---------------------------------------------------------------
// Compare / Trap
//---------------------------------------------------------------
xu_alu_cmp cmp(
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.d_mode_dc(d_mode_dc),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[2]),
.scan_out(sov[2]),
.ex2_act(ex2_act_q),
.ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel),
.ex2_instr(ex2_instr_6to10_q),
.ex2_sel_trap(ex2_sel_trap_q),
.ex2_sel_cmpl(ex2_sel_cmpl_q),
.ex2_sel_cmp(ex2_sel_cmp_q),
.ex2_rs1_00(ex2_add_rs1[msb]),
.ex2_rs1_32(ex2_add_rs1[32]),
.ex2_rs2_00(ex2_add_rs2[msb]),
.ex2_rs2_32(ex2_add_rs2[32]),
.ex3_alu_rt(ex3_alu_rt),
.ex3_add_ca(ex3_add_ca_q),
.ex3_alu_cr(alu_byp_ex3_cr[0:2]),
.ex3_trap_val(alu_dec_ex3_trap_val)
);
//---------------------------------------------------------------
// Latches
//---------------------------------------------------------------
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_act_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(1'b1),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_act_offset]),
.scout(sov[ex2_act_offset]),
.din(dec_alu_ex1_act),
.dout(ex2_act_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_isel_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_alu_ex1_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_sel_isel_offset]),
.scout(sov[ex2_sel_isel_offset]),
.din(dec_alu_ex1_sel_isel),
.dout(ex2_sel_isel_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msb_64b_sel_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_alu_ex1_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_msb_64b_sel_offset]),
.scout(sov[ex2_msb_64b_sel_offset]),
.din(dec_alu_ex1_msb_64b_sel),
.dout(ex2_msb_64b_sel_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_trap_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_alu_ex1_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_sel_trap_offset]),
.scout(sov[ex2_sel_trap_offset]),
.din(dec_alu_ex1_sel_trap),
.dout(ex2_sel_trap_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_cmpl_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_alu_ex1_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_sel_cmpl_offset]),
.scout(sov[ex2_sel_cmpl_offset]),
.din(dec_alu_ex1_sel_cmpl),
.dout(ex2_sel_cmpl_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_cmp_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_alu_ex1_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_sel_cmp_offset]),
.scout(sov[ex2_sel_cmp_offset]),
.din(dec_alu_ex1_sel_cmp),
.dout(ex2_sel_cmp_q)
);
tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_6to10_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_alu_ex1_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_instr_6to10_offset:ex2_instr_6to10_offset + 5 - 1]),
.scout(sov[ex2_instr_6to10_offset:ex2_instr_6to10_offset + 5 - 1]),
.din(dec_alu_ex1_instr[6:10]),
.dout(ex2_instr_6to10_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_en_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_alu_ex1_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_xer_ov_en_offset]),
.scout(sov[ex2_xer_ov_en_offset]),
.din(dec_alu_ex1_xer_ov_en),
.dout(ex2_xer_ov_en_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ca_en_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(dec_alu_ex1_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_xer_ca_en_offset]),
.scout(sov[ex2_xer_ca_en_offset]),
.din(dec_alu_ex1_xer_ca_en),
.dout(ex2_xer_ca_en_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_ca_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_add_ca_offset]),
.scout(sov[ex3_add_ca_offset]),
.din(ex2_add_ca),
.dout(ex3_add_ca_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_ovf_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_add_ovf_offset]),
.scout(sov[ex3_add_ovf_offset]),
.din(ex2_add_ovf),
.dout(ex3_add_ovf_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_rot_log_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_sel_rot_log_offset]),
.scout(sov[ex3_sel_rot_log_offset]),
.din(ex2_sel_rot_log),
.dout(ex3_sel_rot_log_q)
);
tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex3_xer_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_xer_offset:ex3_xer_offset + 10 - 1]),
.scout(sov[ex3_xer_offset:ex3_xer_offset + 10 - 1]),
.din(byp_alu_ex2_xer[0:9]),
.dout(ex3_xer_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_en_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_xer_ov_en_offset]),
.scout(sov[ex3_xer_ov_en_offset]),
.din(ex2_xer_ov_en_q),
.dout(ex3_xer_ov_en_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ca_en_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_xer_ca_en_offset]),
.scout(sov[ex3_xer_ca_en_offset]),
.din(ex2_xer_ca_en_q),
.dout(ex3_xer_ca_en_q)
);
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
endmodule |
module fu_sto(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
f_sto_si,
f_sto_so,
f_dcd_ex1_sto_act,
f_dcd_ex1_sto_v,
f_fpr_ex2_s_expo_extra,
f_fpr_ex2_s_par,
f_sto_ex3_s_parity_check,
f_dcd_ex1_sto_dp,
f_dcd_ex1_sto_sp,
f_dcd_ex1_sto_wd,
f_byp_ex1_s_sign,
f_byp_ex1_s_expo,
f_byp_ex1_s_frac,
f_sto_ex3_sto_data
);
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input [1:2] delay_lclkr; // tidn,
input [1:2] mpw1_b; // tidn,
input [0:0] mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input f_sto_si;
output f_sto_so;
input f_dcd_ex1_sto_act;
input f_dcd_ex1_sto_v;
input [0:1] f_fpr_ex2_s_expo_extra;
input [0:7] f_fpr_ex2_s_par;
output f_sto_ex3_s_parity_check; // raw calculation
input f_dcd_ex1_sto_dp;
input f_dcd_ex1_sto_sp;
input f_dcd_ex1_sto_wd;
input f_byp_ex1_s_sign;
input [1:11] f_byp_ex1_s_expo;
input [0:52] f_byp_ex1_s_frac;
output [0:63] f_sto_ex3_sto_data;
// end ports
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire sg_0;
wire thold_0_b;
wire thold_0;
wire ex1_act;
wire ex2_act;
(* analysis_not_referenced="TRUE" *)
wire [0:1] spare_unused;
//-----------------
wire [0:3] act_so; //SCAN
wire [0:3] act_si; //SCAN
wire [0:2] ex2_sins_so;
wire [0:2] ex2_sins_si;
wire [0:64] ex2_sop_so;
wire [0:64] ex2_sop_si;
wire [0:72] ex3_sto_so;
wire [0:72] ex3_sto_si;
//-----------------
wire ex2_s_sign;
wire [1:11] ex2_s_expo;
wire [0:52] ex2_s_frac;
wire [0:63] ex2_sto_data;
wire [0:63] ex3_sto_data;
wire ex2_sto_dp;
wire ex2_sto_sp;
wire ex2_sto_wd;
wire ex2_den_ramt8_02;
wire ex2_den_ramt8_18;
wire ex2_den_ramt4_12;
wire ex2_den_ramt4_08;
wire ex2_den_ramt4_04;
wire ex2_den_ramt4_00;
wire ex2_den_ramt1_03;
wire ex2_den_ramt1_02;
wire ex2_den_ramt1_01;
wire ex2_den_ramt1_00;
wire ex2_expo_eq896;
wire ex2_expo_ge896;
wire ex2_expo_lt896;
wire ex2_sts_lt896;
wire ex2_sts_ge896;
wire ex2_sts_expo_nz;
wire ex2_fixden;
wire ex2_fixden_small;
wire ex2_fixden_big;
wire ex2_std_nonden;
wire ex2_std_fixden_big;
wire ex2_std_fixden_small;
wire ex2_std_nonbig;
wire ex2_std_nonden_wd;
wire ex2_std_lamt8_02;
wire ex2_std_lamt8_10;
wire ex2_std_lamt8_18;
wire ex2_std_lamt2_0;
wire ex2_std_lamt2_2;
wire ex2_std_lamt2_4;
wire ex2_std_lamt2_6;
wire ex2_std_lamt1_0;
wire ex2_std_lamt1_1;
wire [0:23] ex2_sts_sh8;
wire [0:23] ex2_sts_sh4;
wire [0:23] ex2_sts_sh1;
wire [0:23] ex2_sts_nrm;
wire [1:23] ex2_sts_frac;
wire [1:8] ex2_sts_expo;
wire [0:10] ex2_clz02_or;
wire [0:10] ex2_clz02_enc4;
wire [0:5] ex2_clz04_or;
wire [0:5] ex2_clz04_enc3;
wire [0:5] ex2_clz04_enc4;
wire [0:2] ex2_clz08_or;
wire [0:2] ex2_clz08_enc2;
wire [0:2] ex2_clz08_enc3;
wire [0:2] ex2_clz08_enc4;
wire [0:1] ex2_clz16_or;
wire [0:1] ex2_clz16_enc1;
wire [0:1] ex2_clz16_enc2;
wire [0:1] ex2_clz16_enc3;
wire [0:1] ex2_clz16_enc4;
wire [0:4] ex2_sto_clz;
wire [1:11] ex2_expo_nonden;
wire [1:11] ex2_expo_fixden;
wire [1:11] ex2_std_expo;
wire [1:52] ex2_std_frac_nrm;
wire [0:23] ex2_std_sh8;
wire [0:23] ex2_std_sh2;
wire [1:23] ex2_std_frac_den;
wire ex2_ge874;
wire ex2_any_edge;
wire [0:63] ex3_sto_data_rot0_b;
wire [0:63] ex3_sto_data_rot1_b;
wire [0:3] ex3_sto_wd;
wire [0:3] ex3_sto_sp;
wire force_t;
wire ex2_s_party_chick;
wire ex3_s_party_chick;
wire [0:7] ex2_s_party;
wire ex2_sto_v;
(* analysis_not_referenced="TRUE" *) // unused
wire [0:1] unused;
////############################################
////# pervasive
////############################################
assign unused[0] = ex2_sts_sh1[0] | ex2_sts_nrm[0] | ex2_std_sh2[0];
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
////############################################
////# ACT LATCHES
////############################################
assign ex1_act = f_dcd_ex1_sto_act;
tri_rlmreg_p #(.WIDTH(4)) act_lat(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.force_t(force_t), // tidn
.d_mode(tiup),
.delay_lclkr(delay_lclkr[1]), // tidn,
.mpw1_b(mpw1_b[1]), // tidn,
.mpw2_b(mpw2_b[0]), // tidn,
.act(tiup),
.thold_b(thold_0_b),
.sg(sg_0),
.scout(act_so),
.scin(act_si),
//-----------------
.din({ ex1_act,
spare_unused[0],
spare_unused[1],
f_dcd_ex1_sto_v}),
//-----------------
.dout({ ex2_act,
spare_unused[0],
spare_unused[1],
ex2_sto_v})
);
assign unused[1] = ex2_sto_v;
////##############################################
////# EX2 latch inputs from ex1
////##############################################
tri_rlmreg_p #(.WIDTH(3), .IBUF(1'B1)) ex2_sins_lat(
.force_t(force_t), //tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[1]), //tidn,
.mpw1_b(mpw1_b[1]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex1_act),
.vd(vdd),
.gd(gnd),
.scout(ex2_sins_so),
.scin(ex2_sins_si),
//-----------------
.din({ f_dcd_ex1_sto_dp,
f_dcd_ex1_sto_sp,
f_dcd_ex1_sto_wd}),
//-----------------
.dout({ ex2_sto_dp,
ex2_sto_sp,
ex2_sto_wd})
);
tri_rlmreg_p #(.WIDTH(65), .NEEDS_SRESET(0), .IBUF(1'B1)) ex2_sop_lat(
.force_t(force_t), //tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[1]), //tidn,
.mpw1_b(mpw1_b[1]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex1_act),
.vd(vdd),
.gd(gnd),
.scout(ex2_sop_so),
.scin(ex2_sop_si),
//-----------------
.din({ f_byp_ex1_s_sign,
f_byp_ex1_s_expo[1:11],
f_byp_ex1_s_frac[0:52]}),
//-----------------
.dout({ ex2_s_sign,
ex2_s_expo[1:11],
ex2_s_frac[0:52]})
);
////##############################################
////# EX2 logic
////##############################################
////###################################################
////# shifting for store sp
////###################################################
// output of dp instr with expo below x381 needs to denormalize to sp format.
// x380 d896 011_1000_0000 => right 1 11 11 11 <== treat as special case
// x37F d895 011_0111_1111 => right 2 00 00 00
// x37E d894 011_0111_1110 => right 3 00 00 01
// x37D d893 011_0111_1101 => right 4 00 00 10
// x37C d892 011_0111_1100 => right 5 00 00 11
// x37B d891 011_0111_1011 => right 6 00 01 00
// x37A d890 011_0111_1010 => right 7 00 01 01
// x379 d889 011_0111_1001 => right 8 00 01 10
// x378 d888 011_0111_1000 => right 9 00 01 11
// x377 d887 011_0111_0111 => right 10 00 10 00
// x376 d886 011_0111_0110 => right 11 00 10 01
// x375 d885 011_0111_0101 => right 12 00 10 10
// x374 d884 011_0111_0100 => right 13 00 10 11
// x373 d883 011_0111_0011 => right 14 00 11 00
// x372 d882 011_0111_0010 => right 15 00 11 01
// x371 d881 011_0111_0001 => right 16 00 11 10
// x370 d880 011_0111_0000 => right 17 00 11 11
// x36F d879 011_0110_1111 => right 18 01 00 00
// x36E d878 011_0110_1110 => right 19 01 00 01
// x36B d877 011_0110_1101 => right 20 01 00 10
// x36C d876 011_0110_1100 => right 21 01 00 11
// x36B d875 011_0110_1011 => right 22 01 01 00
// x36A d874 011_0110_1010 => right 23 01 01 01
// x369 d873 011_0110_1001 => right 24 01 01 10 ===> result is zero after here
//------------------------
// 000 0000 0011
// 123 4567 8901
assign ex2_den_ramt8_02 = ex2_s_expo[6] & ex2_s_expo[7];
assign ex2_den_ramt8_18 = ex2_s_expo[6] & (~ex2_s_expo[7]);
assign ex2_den_ramt4_12 = (~ex2_s_expo[8]) & (~ex2_s_expo[9]);
assign ex2_den_ramt4_08 = (~ex2_s_expo[8]) & ex2_s_expo[9];
assign ex2_den_ramt4_04 = ex2_s_expo[8] & (~ex2_s_expo[9]);
assign ex2_den_ramt4_00 = ex2_s_expo[8] & ex2_s_expo[9];
assign ex2_den_ramt1_03 = (~ex2_s_expo[10]) & (~ex2_s_expo[11]);
assign ex2_den_ramt1_02 = (~ex2_s_expo[10]) & ex2_s_expo[11];
assign ex2_den_ramt1_01 = ex2_s_expo[10] & (~ex2_s_expo[11]);
assign ex2_den_ramt1_00 = ex2_s_expo[10] & ex2_s_expo[11];
assign ex2_expo_eq896 = (~ex2_s_expo[1]) & ex2_s_expo[2] & ex2_s_expo[3] & ex2_s_expo[4] & (~ex2_s_expo[5]) & (~ex2_s_expo[6]) & (~ex2_s_expo[7]) & (~ex2_s_expo[8]) & (~ex2_s_expo[9]) & (~ex2_s_expo[10]) & (~ex2_s_expo[11]); // 011_1000_0000
assign ex2_expo_ge896 = (ex2_s_expo[1]) | (ex2_s_expo[2] & ex2_s_expo[3] & ex2_s_expo[4]);
assign ex2_ge874 = (ex2_s_expo[1]) | (ex2_s_expo[2] & ex2_s_expo[3] & ex2_s_expo[4]) | (ex2_s_expo[2] & ex2_s_expo[3] & ex2_s_expo[5] & ex2_s_expo[6]); // 011_0110_1010 -- enough so shifter does not wrap 011_0110_xxxx
assign ex2_expo_lt896 = (~ex2_expo_ge896);
assign ex2_sts_lt896 = ex2_sto_sp & ex2_expo_lt896 & ex2_ge874; // result = zero when lt 874
assign ex2_sts_ge896 = ex2_sto_sp & ex2_expo_ge896;
assign ex2_sts_sh8[0:23] = ({24{ex2_den_ramt8_02}} & ({{2{tidn}}, ex2_s_frac[0:21]})) |
({24{ex2_den_ramt8_18}} & ({{18{tidn}}, ex2_s_frac[0:5]}));
assign ex2_sts_sh4[0:23] = ({24{ex2_den_ramt4_12}} & ({{12{tidn}}, ex2_sts_sh8[0:11]})) |
({24{ex2_den_ramt4_08}} & ({{8{tidn}}, ex2_sts_sh8[0:15]})) |
({24{ex2_den_ramt4_04}} & ({{4{tidn}}, ex2_sts_sh8[0:19]})) |
({24{ex2_den_ramt4_00}} & (ex2_sts_sh8[0:23]));
assign ex2_sts_sh1[0:23] = ({24{ex2_den_ramt1_03}} & ({{3{tidn}}, ex2_sts_sh4[0:20]})) |
({24{ex2_den_ramt1_02}} & ({{2{tidn}}, ex2_sts_sh4[0:21]})) |
({24{ex2_den_ramt1_01}} & ({tidn, ex2_sts_sh4[0:22]})) |
({24{ex2_den_ramt1_00}} & (ex2_sts_sh4[0:23]));
assign ex2_sts_nrm[0:23] = ({24{ex2_expo_eq896}} & ({tidn, ex2_s_frac[0:22]})) |
({24{(~ex2_expo_eq896)}} & (ex2_s_frac[0:23]));
assign ex2_sts_frac[1:23] = ({23{ex2_sts_lt896}} & ex2_sts_sh1[1:23]) |
({23{ex2_sts_ge896}} & ex2_sts_nrm[1:23]);
////###################################################
////# store_sp : calc shift amount :
////###################################################
assign ex2_sts_expo_nz = ex2_sto_sp & ex2_expo_ge896;
assign ex2_sts_expo[1] = ex2_s_expo[1] & ex2_sts_expo_nz;
assign ex2_sts_expo[2:7] = ex2_s_expo[5:10] & {6{ex2_sts_expo_nz}};
assign ex2_sts_expo[8] = ex2_s_expo[11] & ex2_s_frac[0] & ex2_sts_expo_nz;
////###################################################
////# normalization shift left amount for store_dp
////###################################################
// count leading zeroes to get the shift amount
//bit pos dp_expo bin_expo inv clz lsb shift left to norm
//
// 00 x381 011_1000_0001 1_1110 00 0_0000 <== normal
// 01 x380 011_1000_0000 1_1111 01 0_0001
// 02 x37F 011_0111_1111 0_0000 02 0_0010 <=== start clz on bit 2;
// 03 x37E 011_0111_1110 0_0001 03 0_0010
// 04 x37D 011_0111_1101 0_0010 04 0_0010
// 05 x37C 011_0111_1100 0_0011 05 0_0010
// 06 x37B 011_0111_1011 0_0100 06 0_0010
// 07 x37A 011_0111_1010 0_0101 07 0_0010
// 08 x379 011_0111_1001 0_0110 08 0_0010
// 09 x378 011_0111_1000 0_0111 09 0_0010
// 10 x377 011_0111_0111 0_1000 10 0_0010
// 11 x376 011_0111_0110 0_1001 11 0_0010
// 12 x375 011_0111_0101 0_1010 12 0_0010
// 13 x374 011_0111_0100 0_1011 13 0_0010
// 14 x373 011_0111_0011 0_1100 14 0_0010
// 15 x372 011_0111_0010 0_1101 15 0_0010
// 16 x371 011_0111_0001 0_1110 16 0_0010
// 17 x370 011_0111_0000 0_1111 17 0_0010
// 18 x36F 011_0110_1111 1_0000 18 0_0010
// 19 x36E 011_0110_1110 1_0001 19 0_0010
// 20 x36D 011_0110_1101 1_0010 20 0_0010
// 21 x36C 011_0110_1100 1_0011 21 0_0010
// 22 x36B 011_0110_1011 1_0100 22 0_0010
// 23 x36A 011_0110_1010 1_0101 23 0_0010
// if clz does not find leading bit (shift of 0 is ok)
assign ex2_clz02_or[0] = ex2_s_frac[2] | ex2_s_frac[3];
assign ex2_clz02_enc4[0] = (~ex2_s_frac[2]) & ex2_s_frac[3];
assign ex2_clz02_or[1] = ex2_s_frac[4] | ex2_s_frac[5];
assign ex2_clz02_enc4[1] = (~ex2_s_frac[4]) & ex2_s_frac[5];
assign ex2_clz02_or[2] = ex2_s_frac[6] | ex2_s_frac[7];
assign ex2_clz02_enc4[2] = (~ex2_s_frac[6]) & ex2_s_frac[7];
assign ex2_clz02_or[3] = ex2_s_frac[8] | ex2_s_frac[9];
assign ex2_clz02_enc4[3] = (~ex2_s_frac[8]) & ex2_s_frac[9];
assign ex2_clz02_or[4] = ex2_s_frac[10] | ex2_s_frac[11];
assign ex2_clz02_enc4[4] = (~ex2_s_frac[10]) & ex2_s_frac[11];
assign ex2_clz02_or[5] = ex2_s_frac[12] | ex2_s_frac[13];
assign ex2_clz02_enc4[5] = (~ex2_s_frac[12]) & ex2_s_frac[13];
assign ex2_clz02_or[6] = ex2_s_frac[14] | ex2_s_frac[15];
assign ex2_clz02_enc4[6] = (~ex2_s_frac[14]) & ex2_s_frac[15];
assign ex2_clz02_or[7] = ex2_s_frac[16] | ex2_s_frac[17];
assign ex2_clz02_enc4[7] = (~ex2_s_frac[16]) & ex2_s_frac[17];
assign ex2_clz02_or[8] = ex2_s_frac[18] | ex2_s_frac[19];
assign ex2_clz02_enc4[8] = (~ex2_s_frac[18]) & ex2_s_frac[19];
assign ex2_clz02_or[9] = ex2_s_frac[20] | ex2_s_frac[21];
assign ex2_clz02_enc4[9] = (~ex2_s_frac[20]) & ex2_s_frac[21];
assign ex2_clz02_or[10] = ex2_s_frac[22] | ex2_s_frac[23];
assign ex2_clz02_enc4[10] = (~ex2_s_frac[22]) & ex2_s_frac[23];
assign ex2_clz04_or[0] = ex2_clz02_or[0] | ex2_clz02_or[1];
assign ex2_clz04_enc3[0] = (~ex2_clz02_or[0]) & ex2_clz02_or[1];
assign ex2_clz04_enc4[0] = ex2_clz02_enc4[0] | ((~ex2_clz02_or[0]) & ex2_clz02_enc4[1]);
assign ex2_clz04_or[1] = ex2_clz02_or[2] | ex2_clz02_or[3];
assign ex2_clz04_enc3[1] = (~ex2_clz02_or[2]) & ex2_clz02_or[3];
assign ex2_clz04_enc4[1] = ex2_clz02_enc4[2] | ((~ex2_clz02_or[2]) & ex2_clz02_enc4[3]);
assign ex2_clz04_or[2] = ex2_clz02_or[4] | ex2_clz02_or[5];
assign ex2_clz04_enc3[2] = (~ex2_clz02_or[4]) & ex2_clz02_or[5];
assign ex2_clz04_enc4[2] = ex2_clz02_enc4[4] | ((~ex2_clz02_or[4]) & ex2_clz02_enc4[5]);
assign ex2_clz04_or[3] = ex2_clz02_or[6] | ex2_clz02_or[7];
assign ex2_clz04_enc3[3] = (~ex2_clz02_or[6]) & ex2_clz02_or[7];
assign ex2_clz04_enc4[3] = ex2_clz02_enc4[6] | ((~ex2_clz02_or[6]) & ex2_clz02_enc4[7]);
assign ex2_clz04_or[4] = ex2_clz02_or[8] | ex2_clz02_or[9];
assign ex2_clz04_enc3[4] = (~ex2_clz02_or[8]) & ex2_clz02_or[9];
assign ex2_clz04_enc4[4] = ex2_clz02_enc4[8] | ((~ex2_clz02_or[8]) & ex2_clz02_enc4[9]);
assign ex2_clz04_or[5] = ex2_clz02_or[10];
assign ex2_clz04_enc3[5] = tidn;
assign ex2_clz04_enc4[5] = ex2_clz02_enc4[10];
assign ex2_clz08_or[0] = ex2_clz04_or[0] | ex2_clz04_or[1];
assign ex2_clz08_enc2[0] = (~ex2_clz04_or[0]) & ex2_clz04_or[1];
assign ex2_clz08_enc3[0] = ex2_clz04_enc3[0] | ((~ex2_clz04_or[0]) & ex2_clz04_enc3[1]);
assign ex2_clz08_enc4[0] = ex2_clz04_enc4[0] | ((~ex2_clz04_or[0]) & ex2_clz04_enc4[1]);
assign ex2_clz08_or[1] = ex2_clz04_or[2] | ex2_clz04_or[3];
assign ex2_clz08_enc2[1] = (~ex2_clz04_or[2]) & ex2_clz04_or[3];
assign ex2_clz08_enc3[1] = ex2_clz04_enc3[2] | ((~ex2_clz04_or[2]) & ex2_clz04_enc3[3]);
assign ex2_clz08_enc4[1] = ex2_clz04_enc4[2] | ((~ex2_clz04_or[2]) & ex2_clz04_enc4[3]);
assign ex2_clz08_or[2] = ex2_clz04_or[4] | ex2_clz04_or[5];
assign ex2_clz08_enc2[2] = (~ex2_clz04_or[4]) & ex2_clz04_or[5];
assign ex2_clz08_enc3[2] = ex2_clz04_enc3[4] | ((~ex2_clz04_or[4]) & ex2_clz04_enc3[5]);
assign ex2_clz08_enc4[2] = ex2_clz04_enc4[4] | ((~ex2_clz04_or[4]) & ex2_clz04_enc4[5]);
assign ex2_clz16_or[0] = ex2_clz08_or[0] | ex2_clz08_or[1];
assign ex2_clz16_enc1[0] = (~ex2_clz08_or[0]) & ex2_clz08_or[1];
assign ex2_clz16_enc2[0] = ex2_clz08_enc2[0] | ((~ex2_clz08_or[0]) & ex2_clz08_enc2[1]);
assign ex2_clz16_enc3[0] = ex2_clz08_enc3[0] | ((~ex2_clz08_or[0]) & ex2_clz08_enc3[1]);
assign ex2_clz16_enc4[0] = ex2_clz08_enc4[0] | ((~ex2_clz08_or[0]) & ex2_clz08_enc4[1]);
assign ex2_clz16_or[1] = ex2_clz08_or[2];
assign ex2_clz16_enc1[1] = tidn;
assign ex2_clz16_enc2[1] = ex2_clz08_enc2[2];
assign ex2_clz16_enc3[1] = ex2_clz08_enc3[2];
assign ex2_clz16_enc4[1] = ex2_clz08_enc4[2];
assign ex2_sto_clz[0] = (~ex2_clz16_or[0]) & ex2_clz16_or[1];
assign ex2_sto_clz[1] = ex2_clz16_enc1[0] | ((~ex2_clz16_or[0]) & ex2_clz16_enc1[1]);
assign ex2_sto_clz[2] = ex2_clz16_enc2[0] | ((~ex2_clz16_or[0]) & ex2_clz16_enc2[1]);
assign ex2_sto_clz[3] = ex2_clz16_enc3[0] | ((~ex2_clz16_or[0]) & ex2_clz16_enc3[1]);
assign ex2_sto_clz[4] = ex2_clz16_enc4[0] | ((~ex2_clz16_or[0]) & ex2_clz16_enc4[1]);
assign ex2_any_edge = (ex2_clz16_or[0] | ex2_clz16_or[1]);
////###################################################
////# exponent for store dp
////###################################################
// exponent must be zero when input is zero x001 * !imp
assign ex2_fixden = ex2_s_expo[2] & (~ex2_s_frac[0]); // sp denorm or zero
assign ex2_fixden_small = ex2_s_expo[2] & (~ex2_s_frac[0]) & ex2_s_frac[1];
assign ex2_fixden_big = ex2_s_expo[2] & (~ex2_s_frac[0]) & (~ex2_s_frac[1]);
assign ex2_std_nonden = ex2_sto_dp & (~ex2_fixden);
assign ex2_std_fixden_big = ex2_sto_dp & ex2_fixden_big; // denorm more than 1
assign ex2_std_fixden_small = ex2_sto_dp & ex2_fixden_small; // denorm by 1
assign ex2_std_nonbig = ex2_sto_dp & (~ex2_fixden_big);
// dp denorm/zero turn of expo lsb
// sp denorm(1) goes to x380 (turn off lsb)
assign ex2_expo_nonden[1:10] = ex2_s_expo[1:10] & {10{ex2_std_nonbig}};
assign ex2_expo_nonden[11] = ex2_s_expo[11] & ex2_s_frac[0] & ex2_std_nonden;
assign ex2_expo_fixden[1] = tidn; // 011_011x_xxx
assign ex2_expo_fixden[2] = ex2_any_edge; // 011_011x_xxx
assign ex2_expo_fixden[3] = ex2_any_edge; // 011_011x_xxx
assign ex2_expo_fixden[4] = tidn; // 011_011x_xxx
assign ex2_expo_fixden[5] = ex2_any_edge; // 011_011x_xxx
assign ex2_expo_fixden[6] = ex2_any_edge; // 011_011x_xxx
assign ex2_expo_fixden[7:11] = (~ex2_sto_clz[0:4]) & {5{ex2_any_edge}};
assign ex2_std_expo[1:11] = (ex2_expo_nonden[1:11]) |
(ex2_expo_fixden[1:11] & {11{ex2_std_fixden_big}});
////#########################################################################
////# shifting for store dp
////#########################################################################
assign ex2_std_nonden_wd = ex2_std_nonden | ex2_sto_wd;
assign ex2_std_frac_nrm[1:20] = (ex2_s_frac[2:21] & {20{ex2_std_fixden_small}}) |
(ex2_s_frac[1:20] & {20{ex2_std_nonden}});
assign ex2_std_frac_nrm[21:52] = (({ex2_s_frac[22:52], tidn}) & {32{ex2_std_fixden_small}}) |
(ex2_s_frac[21:52] & {32{ex2_std_nonden_wd}}); // stfiwx has a 32 bit result f[21:52]
assign ex2_std_lamt8_02 = (~ex2_sto_clz[0]) & (~ex2_sto_clz[1]); // 0 + 2
assign ex2_std_lamt8_10 = (~ex2_sto_clz[0]) & ex2_sto_clz[1]; // 8 + 2
assign ex2_std_lamt8_18 = ex2_sto_clz[0] & (~ex2_sto_clz[1]); //16 + 2
assign ex2_std_lamt2_0 = (~ex2_sto_clz[2]) & (~ex2_sto_clz[3]);
assign ex2_std_lamt2_2 = (~ex2_sto_clz[2]) & ex2_sto_clz[3];
assign ex2_std_lamt2_4 = ex2_sto_clz[2] & (~ex2_sto_clz[3]);
assign ex2_std_lamt2_6 = ex2_sto_clz[2] & ex2_sto_clz[3];
assign ex2_std_lamt1_0 = ex2_std_fixden_big & (~ex2_sto_clz[4]);
assign ex2_std_lamt1_1 = ex2_std_fixden_big & ex2_sto_clz[4];
//@-- -- if the input was an sp denorm (sp format) then there are only 24 input bits [0:23]
assign ex2_std_sh8[0:23] = (({ex2_s_frac[2:23], {2{tidn}}}) & {24{ex2_std_lamt8_02}}) |
(({ex2_s_frac[10:23], {10{tidn}}}) & {24{ex2_std_lamt8_10}}) |
(({ex2_s_frac[18:23], {18{tidn}}}) & {24{ex2_std_lamt8_18}});
assign ex2_std_sh2[0:23] = (ex2_std_sh8[0:23] & {24{ex2_std_lamt2_0}}) |
(({ex2_std_sh8[2:23], {2{tidn}}}) & {24{ex2_std_lamt2_2}}) |
(({ex2_std_sh8[4:23], {4{tidn}}}) & {24{ex2_std_lamt2_4}}) |
(({ex2_std_sh8[6:23], {6{tidn}}}) & {24{ex2_std_lamt2_6}});
assign ex2_std_frac_den[1:23] = (ex2_std_sh2[1:23] & {23{ex2_std_lamt1_0}}) |
(({ex2_std_sh2[2:23], tidn}) & {23{ex2_std_lamt1_1}});
////###################################################
////# final combinations
////###################################################
assign ex2_sto_data[0] = ex2_s_sign & (~ex2_sto_wd); // sign bit
assign ex2_sto_data[1:8] = ex2_sts_expo[1:8] | ex2_std_expo[1:8];
assign ex2_sto_data[9:11] = ex2_sts_frac[1:3] | ex2_std_expo[9:11];
assign ex2_sto_data[12:31] = ex2_sts_frac[4:23] | ex2_std_frac_nrm[1:20] | ex2_std_frac_den[1:20];
assign ex2_sto_data[32:34] = ex2_std_frac_nrm[21:23] | ex2_std_frac_den[21:23]; //03 bits (includes stfwix)
assign ex2_sto_data[35:63] = ex2_std_frac_nrm[24:52]; //29 bits (includes stfwix)
////##############################################
////# EX3 latches
////##############################################
tri_rlmreg_p #(.WIDTH(73), .NEEDS_SRESET(0), .IBUF(1'B1)) ex3_sto_lat(
.force_t(force_t), //tidn,
.d_mode(tiup),
.delay_lclkr(delay_lclkr[2]), //tidn,
.mpw1_b(mpw1_b[2]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex2_act),
.vd(vdd),
.gd(gnd),
.scout(ex3_sto_so),
.scin(ex3_sto_si),
//-----------------
.din({ ex2_sto_data[0:63],
ex2_sto_sp,
ex2_sto_sp,
ex2_sto_sp,
ex2_sto_sp,
ex2_sto_wd,
ex2_sto_wd,
ex2_sto_wd,
ex2_sto_wd,
ex2_s_party_chick}),
.dout({ ex3_sto_data[0:63], //LAT--
ex3_sto_sp[0], //LAT--
ex3_sto_sp[1], //LAT--
ex3_sto_sp[2], //LAT--
ex3_sto_sp[3], //LAT--
ex3_sto_wd[0], //LAT--
ex3_sto_wd[1], //LAT--
ex3_sto_wd[2], //LAT--
ex3_sto_wd[3], //LAT--
ex3_s_party_chick}) //LAT--
);
assign f_sto_ex3_s_parity_check = ex3_s_party_chick;
// 1 unused
// 2 xx
// 3 1
// 4 2
// 5 3
// 6 4
// 7 5
// 8 6
// 9 7
// 10 8
// 11 9
// 12 10
// 13 11
assign ex2_s_party[0] = ex2_s_sign ^ f_fpr_ex2_s_expo_extra[0] ^ f_fpr_ex2_s_expo_extra[1] ^ ex2_s_expo[1] ^ ex2_s_expo[2] ^ ex2_s_expo[3] ^ ex2_s_expo[4] ^ ex2_s_expo[5] ^ ex2_s_expo[6] ^ ex2_s_expo[7];
assign ex2_s_party[1] = ex2_s_expo[8] ^ ex2_s_expo[9] ^ ex2_s_expo[10] ^ ex2_s_expo[11] ^ ex2_s_frac[0] ^ ex2_s_frac[1] ^ ex2_s_frac[2] ^ ex2_s_frac[3] ^ ex2_s_frac[4];
assign ex2_s_party[2] = ex2_s_frac[5] ^ ex2_s_frac[6] ^ ex2_s_frac[7] ^ ex2_s_frac[8] ^ ex2_s_frac[9] ^ ex2_s_frac[10] ^ ex2_s_frac[11] ^ ex2_s_frac[12];
assign ex2_s_party[3] = ex2_s_frac[13] ^ ex2_s_frac[14] ^ ex2_s_frac[15] ^ ex2_s_frac[16] ^ ex2_s_frac[17] ^ ex2_s_frac[18] ^ ex2_s_frac[19] ^ ex2_s_frac[20];
assign ex2_s_party[4] = ex2_s_frac[21] ^ ex2_s_frac[22] ^ ex2_s_frac[23] ^ ex2_s_frac[24] ^ ex2_s_frac[25] ^ ex2_s_frac[26] ^ ex2_s_frac[27] ^ ex2_s_frac[28];
assign ex2_s_party[5] = ex2_s_frac[29] ^ ex2_s_frac[30] ^ ex2_s_frac[31] ^ ex2_s_frac[32] ^ ex2_s_frac[33] ^ ex2_s_frac[34] ^ ex2_s_frac[35] ^ ex2_s_frac[36];
assign ex2_s_party[6] = ex2_s_frac[37] ^ ex2_s_frac[38] ^ ex2_s_frac[39] ^ ex2_s_frac[40] ^ ex2_s_frac[41] ^ ex2_s_frac[42] ^ ex2_s_frac[43] ^ ex2_s_frac[44];
assign ex2_s_party[7] = ex2_s_frac[45] ^ ex2_s_frac[46] ^ ex2_s_frac[47] ^ ex2_s_frac[48] ^ ex2_s_frac[49] ^ ex2_s_frac[50] ^ ex2_s_frac[51] ^ ex2_s_frac[52];
assign ex2_s_party_chick = (ex2_s_party[0] ^ f_fpr_ex2_s_par[0]) | (ex2_s_party[1] ^ f_fpr_ex2_s_par[1]) | (ex2_s_party[2] ^ f_fpr_ex2_s_par[2]) | (ex2_s_party[3] ^ f_fpr_ex2_s_par[3]) | (ex2_s_party[4] ^ f_fpr_ex2_s_par[4]) | (ex2_s_party[5] ^ f_fpr_ex2_s_par[5]) | (ex2_s_party[6] ^ f_fpr_ex2_s_par[6]) | (ex2_s_party[7] ^ f_fpr_ex2_s_par[7]);
////##############################################
////# EX3 logic
////##############################################
//@@ ex3_sto_data_rot(0 to 31) <=
//@@ ( ex3_sto_data( 0 to 31) and ( 0 to 31=> not ex3_sto_wd) ) or
//@@ ( ex3_sto_data(32 to 63) and ( 0 to 31=> ex3_sto_wd) );
//@@
//@@ ex3_sto_data_rot(32 to 63) <=
//@@ ( ex3_sto_data( 0 to 31) and (32 to 63=> ex3_sto_sp) ) or
//@@ ( ex3_sto_data(32 to 63) and (32 to 63=> not ex3_sto_sp) );
//@@
//@@
//@@ f_sto_ex3_sto_data( 0 to 63) <= ex3_sto_data_rot(0 to 63);
//@@
assign ex3_sto_data_rot0_b[0] = (~(ex3_sto_data[0] & (~ex3_sto_wd[0])));
assign ex3_sto_data_rot0_b[1] = (~(ex3_sto_data[1] & (~ex3_sto_wd[0])));
assign ex3_sto_data_rot0_b[2] = (~(ex3_sto_data[2] & (~ex3_sto_wd[0])));
assign ex3_sto_data_rot0_b[3] = (~(ex3_sto_data[3] & (~ex3_sto_wd[0])));
assign ex3_sto_data_rot0_b[4] = (~(ex3_sto_data[4] & (~ex3_sto_wd[0])));
assign ex3_sto_data_rot0_b[5] = (~(ex3_sto_data[5] & (~ex3_sto_wd[0])));
assign ex3_sto_data_rot0_b[6] = (~(ex3_sto_data[6] & (~ex3_sto_wd[0])));
assign ex3_sto_data_rot0_b[7] = (~(ex3_sto_data[7] & (~ex3_sto_wd[0])));
assign ex3_sto_data_rot0_b[8] = (~(ex3_sto_data[8] & (~ex3_sto_wd[1])));
assign ex3_sto_data_rot0_b[9] = (~(ex3_sto_data[9] & (~ex3_sto_wd[1])));
assign ex3_sto_data_rot0_b[10] = (~(ex3_sto_data[10] & (~ex3_sto_wd[1])));
assign ex3_sto_data_rot0_b[11] = (~(ex3_sto_data[11] & (~ex3_sto_wd[1])));
assign ex3_sto_data_rot0_b[12] = (~(ex3_sto_data[12] & (~ex3_sto_wd[1])));
assign ex3_sto_data_rot0_b[13] = (~(ex3_sto_data[13] & (~ex3_sto_wd[1])));
assign ex3_sto_data_rot0_b[14] = (~(ex3_sto_data[14] & (~ex3_sto_wd[1])));
assign ex3_sto_data_rot0_b[15] = (~(ex3_sto_data[15] & (~ex3_sto_wd[1])));
assign ex3_sto_data_rot0_b[16] = (~(ex3_sto_data[16] & (~ex3_sto_wd[2])));
assign ex3_sto_data_rot0_b[17] = (~(ex3_sto_data[17] & (~ex3_sto_wd[2])));
assign ex3_sto_data_rot0_b[18] = (~(ex3_sto_data[18] & (~ex3_sto_wd[2])));
assign ex3_sto_data_rot0_b[19] = (~(ex3_sto_data[19] & (~ex3_sto_wd[2])));
assign ex3_sto_data_rot0_b[20] = (~(ex3_sto_data[20] & (~ex3_sto_wd[2])));
assign ex3_sto_data_rot0_b[21] = (~(ex3_sto_data[21] & (~ex3_sto_wd[2])));
assign ex3_sto_data_rot0_b[22] = (~(ex3_sto_data[22] & (~ex3_sto_wd[2])));
assign ex3_sto_data_rot0_b[23] = (~(ex3_sto_data[23] & (~ex3_sto_wd[2])));
assign ex3_sto_data_rot0_b[24] = (~(ex3_sto_data[24] & (~ex3_sto_wd[3])));
assign ex3_sto_data_rot0_b[25] = (~(ex3_sto_data[25] & (~ex3_sto_wd[3])));
assign ex3_sto_data_rot0_b[26] = (~(ex3_sto_data[26] & (~ex3_sto_wd[3])));
assign ex3_sto_data_rot0_b[27] = (~(ex3_sto_data[27] & (~ex3_sto_wd[3])));
assign ex3_sto_data_rot0_b[28] = (~(ex3_sto_data[28] & (~ex3_sto_wd[3])));
assign ex3_sto_data_rot0_b[29] = (~(ex3_sto_data[29] & (~ex3_sto_wd[3])));
assign ex3_sto_data_rot0_b[30] = (~(ex3_sto_data[30] & (~ex3_sto_wd[3])));
assign ex3_sto_data_rot0_b[31] = (~(ex3_sto_data[31] & (~ex3_sto_wd[3])));
assign ex3_sto_data_rot0_b[32] = (~(ex3_sto_data[0] & ex3_sto_sp[0]));
assign ex3_sto_data_rot0_b[33] = (~(ex3_sto_data[1] & ex3_sto_sp[0]));
assign ex3_sto_data_rot0_b[34] = (~(ex3_sto_data[2] & ex3_sto_sp[0]));
assign ex3_sto_data_rot0_b[35] = (~(ex3_sto_data[3] & ex3_sto_sp[0]));
assign ex3_sto_data_rot0_b[36] = (~(ex3_sto_data[4] & ex3_sto_sp[0]));
assign ex3_sto_data_rot0_b[37] = (~(ex3_sto_data[5] & ex3_sto_sp[0]));
assign ex3_sto_data_rot0_b[38] = (~(ex3_sto_data[6] & ex3_sto_sp[0]));
assign ex3_sto_data_rot0_b[39] = (~(ex3_sto_data[7] & ex3_sto_sp[0]));
assign ex3_sto_data_rot0_b[40] = (~(ex3_sto_data[8] & ex3_sto_sp[1]));
assign ex3_sto_data_rot0_b[41] = (~(ex3_sto_data[9] & ex3_sto_sp[1]));
assign ex3_sto_data_rot0_b[42] = (~(ex3_sto_data[10] & ex3_sto_sp[1]));
assign ex3_sto_data_rot0_b[43] = (~(ex3_sto_data[11] & ex3_sto_sp[1]));
assign ex3_sto_data_rot0_b[44] = (~(ex3_sto_data[12] & ex3_sto_sp[1]));
assign ex3_sto_data_rot0_b[45] = (~(ex3_sto_data[13] & ex3_sto_sp[1]));
assign ex3_sto_data_rot0_b[46] = (~(ex3_sto_data[14] & ex3_sto_sp[1]));
assign ex3_sto_data_rot0_b[47] = (~(ex3_sto_data[15] & ex3_sto_sp[1]));
assign ex3_sto_data_rot0_b[48] = (~(ex3_sto_data[16] & ex3_sto_sp[2]));
assign ex3_sto_data_rot0_b[49] = (~(ex3_sto_data[17] & ex3_sto_sp[2]));
assign ex3_sto_data_rot0_b[50] = (~(ex3_sto_data[18] & ex3_sto_sp[2]));
assign ex3_sto_data_rot0_b[51] = (~(ex3_sto_data[19] & ex3_sto_sp[2]));
assign ex3_sto_data_rot0_b[52] = (~(ex3_sto_data[20] & ex3_sto_sp[2]));
assign ex3_sto_data_rot0_b[53] = (~(ex3_sto_data[21] & ex3_sto_sp[2]));
assign ex3_sto_data_rot0_b[54] = (~(ex3_sto_data[22] & ex3_sto_sp[2]));
assign ex3_sto_data_rot0_b[55] = (~(ex3_sto_data[23] & ex3_sto_sp[2]));
assign ex3_sto_data_rot0_b[56] = (~(ex3_sto_data[24] & ex3_sto_sp[3]));
assign ex3_sto_data_rot0_b[57] = (~(ex3_sto_data[25] & ex3_sto_sp[3]));
assign ex3_sto_data_rot0_b[58] = (~(ex3_sto_data[26] & ex3_sto_sp[3]));
assign ex3_sto_data_rot0_b[59] = (~(ex3_sto_data[27] & ex3_sto_sp[3]));
assign ex3_sto_data_rot0_b[60] = (~(ex3_sto_data[28] & ex3_sto_sp[3]));
assign ex3_sto_data_rot0_b[61] = (~(ex3_sto_data[29] & ex3_sto_sp[3]));
assign ex3_sto_data_rot0_b[62] = (~(ex3_sto_data[30] & ex3_sto_sp[3]));
assign ex3_sto_data_rot0_b[63] = (~(ex3_sto_data[31] & ex3_sto_sp[3]));
assign ex3_sto_data_rot1_b[0] = (~(ex3_sto_data[32] & ex3_sto_wd[0]));
assign ex3_sto_data_rot1_b[1] = (~(ex3_sto_data[33] & ex3_sto_wd[0]));
assign ex3_sto_data_rot1_b[2] = (~(ex3_sto_data[34] & ex3_sto_wd[0]));
assign ex3_sto_data_rot1_b[3] = (~(ex3_sto_data[35] & ex3_sto_wd[0]));
assign ex3_sto_data_rot1_b[4] = (~(ex3_sto_data[36] & ex3_sto_wd[0]));
assign ex3_sto_data_rot1_b[5] = (~(ex3_sto_data[37] & ex3_sto_wd[0]));
assign ex3_sto_data_rot1_b[6] = (~(ex3_sto_data[38] & ex3_sto_wd[0]));
assign ex3_sto_data_rot1_b[7] = (~(ex3_sto_data[39] & ex3_sto_wd[0]));
assign ex3_sto_data_rot1_b[8] = (~(ex3_sto_data[40] & ex3_sto_wd[1]));
assign ex3_sto_data_rot1_b[9] = (~(ex3_sto_data[41] & ex3_sto_wd[1]));
assign ex3_sto_data_rot1_b[10] = (~(ex3_sto_data[42] & ex3_sto_wd[1]));
assign ex3_sto_data_rot1_b[11] = (~(ex3_sto_data[43] & ex3_sto_wd[1]));
assign ex3_sto_data_rot1_b[12] = (~(ex3_sto_data[44] & ex3_sto_wd[1]));
assign ex3_sto_data_rot1_b[13] = (~(ex3_sto_data[45] & ex3_sto_wd[1]));
assign ex3_sto_data_rot1_b[14] = (~(ex3_sto_data[46] & ex3_sto_wd[1]));
assign ex3_sto_data_rot1_b[15] = (~(ex3_sto_data[47] & ex3_sto_wd[1]));
assign ex3_sto_data_rot1_b[16] = (~(ex3_sto_data[48] & ex3_sto_wd[2]));
assign ex3_sto_data_rot1_b[17] = (~(ex3_sto_data[49] & ex3_sto_wd[2]));
assign ex3_sto_data_rot1_b[18] = (~(ex3_sto_data[50] & ex3_sto_wd[2]));
assign ex3_sto_data_rot1_b[19] = (~(ex3_sto_data[51] & ex3_sto_wd[2]));
assign ex3_sto_data_rot1_b[20] = (~(ex3_sto_data[52] & ex3_sto_wd[2]));
assign ex3_sto_data_rot1_b[21] = (~(ex3_sto_data[53] & ex3_sto_wd[2]));
assign ex3_sto_data_rot1_b[22] = (~(ex3_sto_data[54] & ex3_sto_wd[2]));
assign ex3_sto_data_rot1_b[23] = (~(ex3_sto_data[55] & ex3_sto_wd[2]));
assign ex3_sto_data_rot1_b[24] = (~(ex3_sto_data[56] & ex3_sto_wd[3]));
assign ex3_sto_data_rot1_b[25] = (~(ex3_sto_data[57] & ex3_sto_wd[3]));
assign ex3_sto_data_rot1_b[26] = (~(ex3_sto_data[58] & ex3_sto_wd[3]));
assign ex3_sto_data_rot1_b[27] = (~(ex3_sto_data[59] & ex3_sto_wd[3]));
assign ex3_sto_data_rot1_b[28] = (~(ex3_sto_data[60] & ex3_sto_wd[3]));
assign ex3_sto_data_rot1_b[29] = (~(ex3_sto_data[61] & ex3_sto_wd[3]));
assign ex3_sto_data_rot1_b[30] = (~(ex3_sto_data[62] & ex3_sto_wd[3]));
assign ex3_sto_data_rot1_b[31] = (~(ex3_sto_data[63] & ex3_sto_wd[3]));
assign ex3_sto_data_rot1_b[32] = (~(ex3_sto_data[32] & (~ex3_sto_sp[0])));
assign ex3_sto_data_rot1_b[33] = (~(ex3_sto_data[33] & (~ex3_sto_sp[0])));
assign ex3_sto_data_rot1_b[34] = (~(ex3_sto_data[34] & (~ex3_sto_sp[0])));
assign ex3_sto_data_rot1_b[35] = (~(ex3_sto_data[35] & (~ex3_sto_sp[0])));
assign ex3_sto_data_rot1_b[36] = (~(ex3_sto_data[36] & (~ex3_sto_sp[0])));
assign ex3_sto_data_rot1_b[37] = (~(ex3_sto_data[37] & (~ex3_sto_sp[0])));
assign ex3_sto_data_rot1_b[38] = (~(ex3_sto_data[38] & (~ex3_sto_sp[0])));
assign ex3_sto_data_rot1_b[39] = (~(ex3_sto_data[39] & (~ex3_sto_sp[0])));
assign ex3_sto_data_rot1_b[40] = (~(ex3_sto_data[40] & (~ex3_sto_sp[1])));
assign ex3_sto_data_rot1_b[41] = (~(ex3_sto_data[41] & (~ex3_sto_sp[1])));
assign ex3_sto_data_rot1_b[42] = (~(ex3_sto_data[42] & (~ex3_sto_sp[1])));
assign ex3_sto_data_rot1_b[43] = (~(ex3_sto_data[43] & (~ex3_sto_sp[1])));
assign ex3_sto_data_rot1_b[44] = (~(ex3_sto_data[44] & (~ex3_sto_sp[1])));
assign ex3_sto_data_rot1_b[45] = (~(ex3_sto_data[45] & (~ex3_sto_sp[1])));
assign ex3_sto_data_rot1_b[46] = (~(ex3_sto_data[46] & (~ex3_sto_sp[1])));
assign ex3_sto_data_rot1_b[47] = (~(ex3_sto_data[47] & (~ex3_sto_sp[1])));
assign ex3_sto_data_rot1_b[48] = (~(ex3_sto_data[48] & (~ex3_sto_sp[2])));
assign ex3_sto_data_rot1_b[49] = (~(ex3_sto_data[49] & (~ex3_sto_sp[2])));
assign ex3_sto_data_rot1_b[50] = (~(ex3_sto_data[50] & (~ex3_sto_sp[2])));
assign ex3_sto_data_rot1_b[51] = (~(ex3_sto_data[51] & (~ex3_sto_sp[2])));
assign ex3_sto_data_rot1_b[52] = (~(ex3_sto_data[52] & (~ex3_sto_sp[2])));
assign ex3_sto_data_rot1_b[53] = (~(ex3_sto_data[53] & (~ex3_sto_sp[2])));
assign ex3_sto_data_rot1_b[54] = (~(ex3_sto_data[54] & (~ex3_sto_sp[2])));
assign ex3_sto_data_rot1_b[55] = (~(ex3_sto_data[55] & (~ex3_sto_sp[2])));
assign ex3_sto_data_rot1_b[56] = (~(ex3_sto_data[56] & (~ex3_sto_sp[3])));
assign ex3_sto_data_rot1_b[57] = (~(ex3_sto_data[57] & (~ex3_sto_sp[3])));
assign ex3_sto_data_rot1_b[58] = (~(ex3_sto_data[58] & (~ex3_sto_sp[3])));
assign ex3_sto_data_rot1_b[59] = (~(ex3_sto_data[59] & (~ex3_sto_sp[3])));
assign ex3_sto_data_rot1_b[60] = (~(ex3_sto_data[60] & (~ex3_sto_sp[3])));
assign ex3_sto_data_rot1_b[61] = (~(ex3_sto_data[61] & (~ex3_sto_sp[3])));
assign ex3_sto_data_rot1_b[62] = (~(ex3_sto_data[62] & (~ex3_sto_sp[3])));
assign ex3_sto_data_rot1_b[63] = (~(ex3_sto_data[63] & (~ex3_sto_sp[3])));
assign f_sto_ex3_sto_data[0:63] = (~(ex3_sto_data_rot0_b[0:63] & ex3_sto_data_rot1_b[0:63]));
////############################################
////# scan
////############################################
assign ex2_sins_si[0:2] = {ex2_sins_so[1:2], f_sto_si};
assign ex2_sop_si[0:64] = {ex2_sop_so[1:64], ex2_sins_so[0]};
assign ex3_sto_si[0:72] = {ex3_sto_so[1:72], ex2_sop_so[0]};
assign act_si[0:3] = {act_so[1:3], ex3_sto_so[0]};
assign f_sto_so = act_so[0];
endmodule |
module iuq_rn_top(
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types
input pc_iu_sg_2,
input clkoff_b,
input act_dis,
input tc_ac_ccflush_dc,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input [0:1] func_scan_in,
output [0:1] func_scan_out,
//-------------------------------
// Performance interface with I$
//-------------------------------
input pc_iu_event_bus_enable,
output perf_iu5_stall,
output perf_iu5_cpl_credit_stall,
output perf_iu5_gpr_credit_stall,
output perf_iu5_cr_credit_stall,
output perf_iu5_lr_credit_stall,
output perf_iu5_ctr_credit_stall,
output perf_iu5_xer_credit_stall,
output perf_iu5_br_hold_stall,
output perf_iu5_axu_hold_stall,
//-----------------------------
// Inputs to rename from decode
//-----------------------------
input fdec_frn_iu5_i0_vld,
input [0:2] fdec_frn_iu5_i0_ucode,
input fdec_frn_iu5_i0_2ucode,
input fdec_frn_iu5_i0_fuse_nop,
input fdec_frn_iu5_i0_rte_lq,
input fdec_frn_iu5_i0_rte_sq,
input fdec_frn_iu5_i0_rte_fx0,
input fdec_frn_iu5_i0_rte_fx1,
input fdec_frn_iu5_i0_rte_axu0,
input fdec_frn_iu5_i0_rte_axu1,
input fdec_frn_iu5_i0_valop,
input fdec_frn_iu5_i0_ord,
input fdec_frn_iu5_i0_cord,
input [0:2] fdec_frn_iu5_i0_error,
input fdec_frn_iu5_i0_btb_entry,
input [0:1] fdec_frn_iu5_i0_btb_hist,
input fdec_frn_iu5_i0_bta_val,
input [0:19] fdec_frn_iu5_i0_fusion,
input fdec_frn_iu5_i0_spec,
input fdec_frn_iu5_i0_type_fp,
input fdec_frn_iu5_i0_type_ap,
input fdec_frn_iu5_i0_type_spv,
input fdec_frn_iu5_i0_type_st,
input fdec_frn_iu5_i0_async_block,
input fdec_frn_iu5_i0_np1_flush,
input fdec_frn_iu5_i0_core_block,
input fdec_frn_iu5_i0_isram,
input fdec_frn_iu5_i0_isload,
input fdec_frn_iu5_i0_isstore,
input [0:31] fdec_frn_iu5_i0_instr,
input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_ifar,
input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_bta,
input fdec_frn_iu5_i0_br_pred,
input fdec_frn_iu5_i0_bh_update,
input [0:1] fdec_frn_iu5_i0_bh0_hist,
input [0:1] fdec_frn_iu5_i0_bh1_hist,
input [0:1] fdec_frn_iu5_i0_bh2_hist,
input [0:17] fdec_frn_iu5_i0_gshare,
input [0:2] fdec_frn_iu5_i0_ls_ptr,
input fdec_frn_iu5_i0_match,
input [0:3] fdec_frn_iu5_i0_ilat,
input fdec_frn_iu5_i0_t1_v,
input [0:2] fdec_frn_iu5_i0_t1_t,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t1_a,
input fdec_frn_iu5_i0_t2_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t2_a,
input [0:2] fdec_frn_iu5_i0_t2_t,
input fdec_frn_iu5_i0_t3_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t3_a,
input [0:2] fdec_frn_iu5_i0_t3_t,
input fdec_frn_iu5_i0_s1_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s1_a,
input [0:2] fdec_frn_iu5_i0_s1_t,
input fdec_frn_iu5_i0_s2_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s2_a,
input [0:2] fdec_frn_iu5_i0_s2_t,
input fdec_frn_iu5_i0_s3_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s3_a,
input [0:2] fdec_frn_iu5_i0_s3_t,
input fdec_frn_iu5_i1_vld,
input [0:2] fdec_frn_iu5_i1_ucode,
input fdec_frn_iu5_i1_fuse_nop,
input fdec_frn_iu5_i1_rte_lq,
input fdec_frn_iu5_i1_rte_sq,
input fdec_frn_iu5_i1_rte_fx0,
input fdec_frn_iu5_i1_rte_fx1,
input fdec_frn_iu5_i1_rte_axu0,
input fdec_frn_iu5_i1_rte_axu1,
input fdec_frn_iu5_i1_valop,
input fdec_frn_iu5_i1_ord,
input fdec_frn_iu5_i1_cord,
input [0:2] fdec_frn_iu5_i1_error,
input fdec_frn_iu5_i1_btb_entry,
input [0:1] fdec_frn_iu5_i1_btb_hist,
input fdec_frn_iu5_i1_bta_val,
input [0:19] fdec_frn_iu5_i1_fusion,
input fdec_frn_iu5_i1_spec,
input fdec_frn_iu5_i1_type_fp,
input fdec_frn_iu5_i1_type_ap,
input fdec_frn_iu5_i1_type_spv,
input fdec_frn_iu5_i1_type_st,
input fdec_frn_iu5_i1_async_block,
input fdec_frn_iu5_i1_np1_flush,
input fdec_frn_iu5_i1_core_block,
input fdec_frn_iu5_i1_isram,
input fdec_frn_iu5_i1_isload,
input fdec_frn_iu5_i1_isstore,
input [0:31] fdec_frn_iu5_i1_instr,
input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_ifar,
input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_bta,
input fdec_frn_iu5_i1_br_pred,
input fdec_frn_iu5_i1_bh_update,
input [0:1] fdec_frn_iu5_i1_bh0_hist,
input [0:1] fdec_frn_iu5_i1_bh1_hist,
input [0:1] fdec_frn_iu5_i1_bh2_hist,
input [0:17] fdec_frn_iu5_i1_gshare,
input [0:2] fdec_frn_iu5_i1_ls_ptr,
input fdec_frn_iu5_i1_match,
input [0:3] fdec_frn_iu5_i1_ilat,
input fdec_frn_iu5_i1_t1_v,
input [0:2] fdec_frn_iu5_i1_t1_t,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t1_a,
input fdec_frn_iu5_i1_t2_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t2_a,
input [0:2] fdec_frn_iu5_i1_t2_t,
input fdec_frn_iu5_i1_t3_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t3_a,
input [0:2] fdec_frn_iu5_i1_t3_t,
input fdec_frn_iu5_i1_s1_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s1_a,
input [0:2] fdec_frn_iu5_i1_s1_t,
input fdec_frn_iu5_i1_s2_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s2_a,
input [0:2] fdec_frn_iu5_i1_s2_t,
input fdec_frn_iu5_i1_s3_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s3_a,
input [0:2] fdec_frn_iu5_i1_s3_t,
//-----------------------------
// SPR values
//-----------------------------
input spr_high_pri_mask,
input spr_cpcr_we,
input [0:6] spr_cpcr3_cp_cnt,
input [0:6] spr_cpcr5_cp_cnt,
input spr_single_issue,
//-----------------------------
// Stall to decode
//-----------------------------
output frn_fdec_iu5_stall,
//-----------------------------
// Stall from dispatch
//-----------------------------
input fdis_frn_iu6_stall,
//----------------------------
// Completion Interface
//----------------------------
input cp_rn_i0_axu_exception_val,
input [0:3] cp_rn_i0_axu_exception,
input cp_rn_i1_axu_exception_val,
input [0:3] cp_rn_i1_axu_exception,
input cp_rn_empty,
input cp_rn_i0_v,
input [0:`ITAG_SIZE_ENC-1] cp_rn_i0_itag,
input cp_rn_i0_t1_v,
input [0:2] cp_rn_i0_t1_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_a,
input cp_rn_i0_t2_v,
input [0:2] cp_rn_i0_t2_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_a,
input cp_rn_i0_t3_v,
input [0:2] cp_rn_i0_t3_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_a,
input cp_rn_i1_v,
input [0:`ITAG_SIZE_ENC-1] cp_rn_i1_itag,
input cp_rn_i1_t1_v,
input [0:2] cp_rn_i1_t1_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_a,
input cp_rn_i1_t2_v,
input [0:2] cp_rn_i1_t2_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_a,
input cp_rn_i1_t3_v,
input [0:2] cp_rn_i1_t3_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_a,
input cp_flush,
input cp_flush_into_uc,
input br_iu_redirect,
input cp_rn_uc_credit_free,
//----------------------------------------------------------------
// Interface to reservation station - Completion is snooping also
//----------------------------------------------------------------
output frn_fdis_iu6_i0_vld,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag,
output [0:2] frn_fdis_iu6_i0_ucode,
output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt,
output frn_fdis_iu6_i0_2ucode,
output frn_fdis_iu6_i0_fuse_nop,
output frn_fdis_iu6_i0_rte_lq,
output frn_fdis_iu6_i0_rte_sq,
output frn_fdis_iu6_i0_rte_fx0,
output frn_fdis_iu6_i0_rte_fx1,
output frn_fdis_iu6_i0_rte_axu0,
output frn_fdis_iu6_i0_rte_axu1,
output frn_fdis_iu6_i0_valop,
output frn_fdis_iu6_i0_ord,
output frn_fdis_iu6_i0_cord,
output [0:2] frn_fdis_iu6_i0_error,
output frn_fdis_iu6_i0_btb_entry,
output [0:1] frn_fdis_iu6_i0_btb_hist,
output frn_fdis_iu6_i0_bta_val,
output [0:19] frn_fdis_iu6_i0_fusion,
output frn_fdis_iu6_i0_spec,
output frn_fdis_iu6_i0_type_fp,
output frn_fdis_iu6_i0_type_ap,
output frn_fdis_iu6_i0_type_spv,
output frn_fdis_iu6_i0_type_st,
output frn_fdis_iu6_i0_async_block,
output frn_fdis_iu6_i0_np1_flush,
output frn_fdis_iu6_i0_core_block,
output frn_fdis_iu6_i0_isram,
output frn_fdis_iu6_i0_isload,
output frn_fdis_iu6_i0_isstore,
output [0:31] frn_fdis_iu6_i0_instr,
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar,
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta,
output frn_fdis_iu6_i0_br_pred,
output frn_fdis_iu6_i0_bh_update,
output [0:1] frn_fdis_iu6_i0_bh0_hist,
output [0:1] frn_fdis_iu6_i0_bh1_hist,
output [0:1] frn_fdis_iu6_i0_bh2_hist,
output [0:17] frn_fdis_iu6_i0_gshare,
output [0:2] frn_fdis_iu6_i0_ls_ptr,
output frn_fdis_iu6_i0_match,
output [0:3] frn_fdis_iu6_i0_ilat,
output frn_fdis_iu6_i0_t1_v,
output [0:2] frn_fdis_iu6_i0_t1_t,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p,
output frn_fdis_iu6_i0_t2_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p,
output [0:2] frn_fdis_iu6_i0_t2_t,
output frn_fdis_iu6_i0_t3_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p,
output [0:2] frn_fdis_iu6_i0_t3_t,
output frn_fdis_iu6_i0_s1_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag,
output [0:2] frn_fdis_iu6_i0_s1_t,
output frn_fdis_iu6_i0_s2_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag,
output [0:2] frn_fdis_iu6_i0_s2_t,
output frn_fdis_iu6_i0_s3_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag,
output [0:2] frn_fdis_iu6_i0_s3_t,
output frn_fdis_iu6_i1_vld,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag,
output [0:2] frn_fdis_iu6_i1_ucode,
output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt,
output frn_fdis_iu6_i1_fuse_nop,
output frn_fdis_iu6_i1_rte_lq,
output frn_fdis_iu6_i1_rte_sq,
output frn_fdis_iu6_i1_rte_fx0,
output frn_fdis_iu6_i1_rte_fx1,
output frn_fdis_iu6_i1_rte_axu0,
output frn_fdis_iu6_i1_rte_axu1,
output frn_fdis_iu6_i1_valop,
output frn_fdis_iu6_i1_ord,
output frn_fdis_iu6_i1_cord,
output [0:2] frn_fdis_iu6_i1_error,
output frn_fdis_iu6_i1_btb_entry,
output [0:1] frn_fdis_iu6_i1_btb_hist,
output frn_fdis_iu6_i1_bta_val,
output [0:19] frn_fdis_iu6_i1_fusion,
output frn_fdis_iu6_i1_spec,
output frn_fdis_iu6_i1_type_fp,
output frn_fdis_iu6_i1_type_ap,
output frn_fdis_iu6_i1_type_spv,
output frn_fdis_iu6_i1_type_st,
output frn_fdis_iu6_i1_async_block,
output frn_fdis_iu6_i1_np1_flush,
output frn_fdis_iu6_i1_core_block,
output frn_fdis_iu6_i1_isram,
output frn_fdis_iu6_i1_isload,
output frn_fdis_iu6_i1_isstore,
output [0:31] frn_fdis_iu6_i1_instr,
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar,
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta,
output frn_fdis_iu6_i1_br_pred,
output frn_fdis_iu6_i1_bh_update,
output [0:1] frn_fdis_iu6_i1_bh0_hist,
output [0:1] frn_fdis_iu6_i1_bh1_hist,
output [0:1] frn_fdis_iu6_i1_bh2_hist,
output [0:17] frn_fdis_iu6_i1_gshare,
output [0:2] frn_fdis_iu6_i1_ls_ptr,
output frn_fdis_iu6_i1_match,
output [0:3] frn_fdis_iu6_i1_ilat,
output frn_fdis_iu6_i1_t1_v,
output [0:2] frn_fdis_iu6_i1_t1_t,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p,
output frn_fdis_iu6_i1_t2_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p,
output [0:2] frn_fdis_iu6_i1_t2_t,
output frn_fdis_iu6_i1_t3_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p,
output [0:2] frn_fdis_iu6_i1_t3_t,
output frn_fdis_iu6_i1_s1_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag,
output [0:2] frn_fdis_iu6_i1_s1_t,
output frn_fdis_iu6_i1_s1_dep_hit,
output frn_fdis_iu6_i1_s2_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag,
output [0:2] frn_fdis_iu6_i1_s2_t,
output frn_fdis_iu6_i1_s2_dep_hit,
output frn_fdis_iu6_i1_s3_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag,
output [0:2] frn_fdis_iu6_i1_s3_t,
output frn_fdis_iu6_i1_s3_dep_hit
);
wire au_iu_iu5_stall;
wire iu_au_iu5_send_ok;
wire [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i0;
wire [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i1;
wire au_iu_iu5_axu0_send_ok;
wire au_iu_iu5_axu1_send_ok;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t1_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t2_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t3_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s1_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s2_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s3_p;
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s1_itag;
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s2_itag;
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s3_itag;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t1_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t2_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t3_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s1_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s2_p;
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s3_p;
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s1_itag;
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s2_itag;
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s3_itag;
wire au_iu_iu5_i1_s1_dep_hit;
wire au_iu_iu5_i1_s2_dep_hit;
wire au_iu_iu5_i1_s3_dep_hit;
iuq_rn fx_rn0(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.pc_iu_sg_2(pc_iu_sg_2),
.clkoff_b(clkoff_b),
.act_dis(act_dis),
.tc_ac_ccflush_dc(tc_ac_ccflush_dc),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.func_scan_in(func_scan_in[0]),
.func_scan_out(func_scan_out[0]),
//-------------------------------
// Performance interface with I$
//-------------------------------
.pc_iu_event_bus_enable(pc_iu_event_bus_enable),
.perf_iu5_stall(perf_iu5_stall),
.perf_iu5_cpl_credit_stall(perf_iu5_cpl_credit_stall),
.perf_iu5_gpr_credit_stall(perf_iu5_gpr_credit_stall),
.perf_iu5_cr_credit_stall(perf_iu5_cr_credit_stall),
.perf_iu5_lr_credit_stall(perf_iu5_lr_credit_stall),
.perf_iu5_ctr_credit_stall(perf_iu5_ctr_credit_stall),
.perf_iu5_xer_credit_stall(perf_iu5_xer_credit_stall),
.perf_iu5_br_hold_stall(perf_iu5_br_hold_stall),
.perf_iu5_axu_hold_stall(perf_iu5_axu_hold_stall),
//-----------------------------
// Inputs to rename from decode
//-----------------------------
.fdec_frn_iu5_i0_vld(fdec_frn_iu5_i0_vld),
.fdec_frn_iu5_i0_ucode(fdec_frn_iu5_i0_ucode),
.fdec_frn_iu5_i0_2ucode(fdec_frn_iu5_i0_2ucode),
.fdec_frn_iu5_i0_fuse_nop(fdec_frn_iu5_i0_fuse_nop),
.fdec_frn_iu5_i0_rte_lq(fdec_frn_iu5_i0_rte_lq),
.fdec_frn_iu5_i0_rte_sq(fdec_frn_iu5_i0_rte_sq),
.fdec_frn_iu5_i0_rte_fx0(fdec_frn_iu5_i0_rte_fx0),
.fdec_frn_iu5_i0_rte_fx1(fdec_frn_iu5_i0_rte_fx1),
.fdec_frn_iu5_i0_rte_axu0(fdec_frn_iu5_i0_rte_axu0),
.fdec_frn_iu5_i0_rte_axu1(fdec_frn_iu5_i0_rte_axu1),
.fdec_frn_iu5_i0_valop(fdec_frn_iu5_i0_valop),
.fdec_frn_iu5_i0_ord(fdec_frn_iu5_i0_ord),
.fdec_frn_iu5_i0_cord(fdec_frn_iu5_i0_cord),
.fdec_frn_iu5_i0_error(fdec_frn_iu5_i0_error),
.fdec_frn_iu5_i0_btb_entry(fdec_frn_iu5_i0_btb_entry),
.fdec_frn_iu5_i0_btb_hist(fdec_frn_iu5_i0_btb_hist),
.fdec_frn_iu5_i0_bta_val(fdec_frn_iu5_i0_bta_val),
.fdec_frn_iu5_i0_fusion(fdec_frn_iu5_i0_fusion),
.fdec_frn_iu5_i0_spec(fdec_frn_iu5_i0_spec),
.fdec_frn_iu5_i0_type_fp(fdec_frn_iu5_i0_type_fp),
.fdec_frn_iu5_i0_type_ap(fdec_frn_iu5_i0_type_ap),
.fdec_frn_iu5_i0_type_spv(fdec_frn_iu5_i0_type_spv),
.fdec_frn_iu5_i0_type_st(fdec_frn_iu5_i0_type_st),
.fdec_frn_iu5_i0_async_block(fdec_frn_iu5_i0_async_block),
.fdec_frn_iu5_i0_np1_flush(fdec_frn_iu5_i0_np1_flush),
.fdec_frn_iu5_i0_core_block(fdec_frn_iu5_i0_core_block),
.fdec_frn_iu5_i0_isram(fdec_frn_iu5_i0_isram),
.fdec_frn_iu5_i0_isload(fdec_frn_iu5_i0_isload),
.fdec_frn_iu5_i0_isstore(fdec_frn_iu5_i0_isstore),
.fdec_frn_iu5_i0_instr(fdec_frn_iu5_i0_instr),
.fdec_frn_iu5_i0_ifar(fdec_frn_iu5_i0_ifar),
.fdec_frn_iu5_i0_bta(fdec_frn_iu5_i0_bta),
.fdec_frn_iu5_i0_br_pred(fdec_frn_iu5_i0_br_pred),
.fdec_frn_iu5_i0_bh_update(fdec_frn_iu5_i0_bh_update),
.fdec_frn_iu5_i0_bh0_hist(fdec_frn_iu5_i0_bh0_hist),
.fdec_frn_iu5_i0_bh1_hist(fdec_frn_iu5_i0_bh1_hist),
.fdec_frn_iu5_i0_bh2_hist(fdec_frn_iu5_i0_bh2_hist),
.fdec_frn_iu5_i0_gshare(fdec_frn_iu5_i0_gshare),
.fdec_frn_iu5_i0_ls_ptr(fdec_frn_iu5_i0_ls_ptr),
.fdec_frn_iu5_i0_match(fdec_frn_iu5_i0_match),
.fdec_frn_iu5_i0_ilat(fdec_frn_iu5_i0_ilat),
.fdec_frn_iu5_i0_t1_v(fdec_frn_iu5_i0_t1_v),
.fdec_frn_iu5_i0_t1_t(fdec_frn_iu5_i0_t1_t),
.fdec_frn_iu5_i0_t1_a(fdec_frn_iu5_i0_t1_a),
.fdec_frn_iu5_i0_t2_v(fdec_frn_iu5_i0_t2_v),
.fdec_frn_iu5_i0_t2_a(fdec_frn_iu5_i0_t2_a),
.fdec_frn_iu5_i0_t2_t(fdec_frn_iu5_i0_t2_t),
.fdec_frn_iu5_i0_t3_v(fdec_frn_iu5_i0_t3_v),
.fdec_frn_iu5_i0_t3_a(fdec_frn_iu5_i0_t3_a),
.fdec_frn_iu5_i0_t3_t(fdec_frn_iu5_i0_t3_t),
.fdec_frn_iu5_i0_s1_v(fdec_frn_iu5_i0_s1_v),
.fdec_frn_iu5_i0_s1_a(fdec_frn_iu5_i0_s1_a),
.fdec_frn_iu5_i0_s1_t(fdec_frn_iu5_i0_s1_t),
.fdec_frn_iu5_i0_s2_v(fdec_frn_iu5_i0_s2_v),
.fdec_frn_iu5_i0_s2_a(fdec_frn_iu5_i0_s2_a),
.fdec_frn_iu5_i0_s2_t(fdec_frn_iu5_i0_s2_t),
.fdec_frn_iu5_i0_s3_v(fdec_frn_iu5_i0_s3_v),
.fdec_frn_iu5_i0_s3_a(fdec_frn_iu5_i0_s3_a),
.fdec_frn_iu5_i0_s3_t(fdec_frn_iu5_i0_s3_t),
.fdec_frn_iu5_i1_vld(fdec_frn_iu5_i1_vld),
.fdec_frn_iu5_i1_ucode(fdec_frn_iu5_i1_ucode),
.fdec_frn_iu5_i1_fuse_nop(fdec_frn_iu5_i1_fuse_nop),
.fdec_frn_iu5_i1_rte_lq(fdec_frn_iu5_i1_rte_lq),
.fdec_frn_iu5_i1_rte_sq(fdec_frn_iu5_i1_rte_sq),
.fdec_frn_iu5_i1_rte_fx0(fdec_frn_iu5_i1_rte_fx0),
.fdec_frn_iu5_i1_rte_fx1(fdec_frn_iu5_i1_rte_fx1),
.fdec_frn_iu5_i1_rte_axu0(fdec_frn_iu5_i1_rte_axu0),
.fdec_frn_iu5_i1_rte_axu1(fdec_frn_iu5_i1_rte_axu1),
.fdec_frn_iu5_i1_valop(fdec_frn_iu5_i1_valop),
.fdec_frn_iu5_i1_ord(fdec_frn_iu5_i1_ord),
.fdec_frn_iu5_i1_cord(fdec_frn_iu5_i1_cord),
.fdec_frn_iu5_i1_error(fdec_frn_iu5_i1_error),
.fdec_frn_iu5_i1_btb_entry(fdec_frn_iu5_i1_btb_entry),
.fdec_frn_iu5_i1_btb_hist(fdec_frn_iu5_i1_btb_hist),
.fdec_frn_iu5_i1_bta_val(fdec_frn_iu5_i1_bta_val),
.fdec_frn_iu5_i1_fusion(fdec_frn_iu5_i1_fusion),
.fdec_frn_iu5_i1_spec(fdec_frn_iu5_i1_spec),
.fdec_frn_iu5_i1_type_fp(fdec_frn_iu5_i1_type_fp),
.fdec_frn_iu5_i1_type_ap(fdec_frn_iu5_i1_type_ap),
.fdec_frn_iu5_i1_type_spv(fdec_frn_iu5_i1_type_spv),
.fdec_frn_iu5_i1_type_st(fdec_frn_iu5_i1_type_st),
.fdec_frn_iu5_i1_async_block(fdec_frn_iu5_i1_async_block),
.fdec_frn_iu5_i1_np1_flush(fdec_frn_iu5_i1_np1_flush),
.fdec_frn_iu5_i1_core_block(fdec_frn_iu5_i1_core_block),
.fdec_frn_iu5_i1_isram(fdec_frn_iu5_i1_isram),
.fdec_frn_iu5_i1_isload(fdec_frn_iu5_i1_isload),
.fdec_frn_iu5_i1_isstore(fdec_frn_iu5_i1_isstore),
.fdec_frn_iu5_i1_instr(fdec_frn_iu5_i1_instr),
.fdec_frn_iu5_i1_ifar(fdec_frn_iu5_i1_ifar),
.fdec_frn_iu5_i1_bta(fdec_frn_iu5_i1_bta),
.fdec_frn_iu5_i1_br_pred(fdec_frn_iu5_i1_br_pred),
.fdec_frn_iu5_i1_bh_update(fdec_frn_iu5_i1_bh_update),
.fdec_frn_iu5_i1_bh0_hist(fdec_frn_iu5_i1_bh0_hist),
.fdec_frn_iu5_i1_bh1_hist(fdec_frn_iu5_i1_bh1_hist),
.fdec_frn_iu5_i1_bh2_hist(fdec_frn_iu5_i1_bh2_hist),
.fdec_frn_iu5_i1_gshare(fdec_frn_iu5_i1_gshare),
.fdec_frn_iu5_i1_ls_ptr(fdec_frn_iu5_i1_ls_ptr),
.fdec_frn_iu5_i1_match(fdec_frn_iu5_i1_match),
.fdec_frn_iu5_i1_ilat(fdec_frn_iu5_i1_ilat),
.fdec_frn_iu5_i1_t1_v(fdec_frn_iu5_i1_t1_v),
.fdec_frn_iu5_i1_t1_t(fdec_frn_iu5_i1_t1_t),
.fdec_frn_iu5_i1_t1_a(fdec_frn_iu5_i1_t1_a),
.fdec_frn_iu5_i1_t2_v(fdec_frn_iu5_i1_t2_v),
.fdec_frn_iu5_i1_t2_a(fdec_frn_iu5_i1_t2_a),
.fdec_frn_iu5_i1_t2_t(fdec_frn_iu5_i1_t2_t),
.fdec_frn_iu5_i1_t3_v(fdec_frn_iu5_i1_t3_v),
.fdec_frn_iu5_i1_t3_a(fdec_frn_iu5_i1_t3_a),
.fdec_frn_iu5_i1_t3_t(fdec_frn_iu5_i1_t3_t),
.fdec_frn_iu5_i1_s1_v(fdec_frn_iu5_i1_s1_v),
.fdec_frn_iu5_i1_s1_a(fdec_frn_iu5_i1_s1_a),
.fdec_frn_iu5_i1_s1_t(fdec_frn_iu5_i1_s1_t),
.fdec_frn_iu5_i1_s2_v(fdec_frn_iu5_i1_s2_v),
.fdec_frn_iu5_i1_s2_a(fdec_frn_iu5_i1_s2_a),
.fdec_frn_iu5_i1_s2_t(fdec_frn_iu5_i1_s2_t),
.fdec_frn_iu5_i1_s3_v(fdec_frn_iu5_i1_s3_v),
.fdec_frn_iu5_i1_s3_a(fdec_frn_iu5_i1_s3_a),
.fdec_frn_iu5_i1_s3_t(fdec_frn_iu5_i1_s3_t),
//-----------------------------
// SPR values
//-----------------------------
.spr_high_pri_mask(spr_high_pri_mask),
.spr_cpcr_we(spr_cpcr_we),
.spr_cpcr3_cp_cnt(spr_cpcr3_cp_cnt),
.spr_cpcr5_cp_cnt(spr_cpcr5_cp_cnt),
.spr_single_issue(spr_single_issue),
//-----------------------------
// Stall to decode
//-----------------------------
.frn_fdec_iu5_stall(frn_fdec_iu5_stall),
.au_iu_iu5_stall(au_iu_iu5_stall),
//-----------------------------
// Stall from dispatch
//-----------------------------
.fdis_frn_iu6_stall(fdis_frn_iu6_stall),
//----------------------------
// Completion Interface
//----------------------------
.cp_rn_empty(cp_rn_empty),
.cp_rn_i0_v(cp_rn_i0_v),
.cp_rn_i0_itag(cp_rn_i0_itag),
.cp_rn_i0_t1_v(cp_rn_i0_t1_v),
.cp_rn_i0_t1_t(cp_rn_i0_t1_t),
.cp_rn_i0_t1_p(cp_rn_i0_t1_p),
.cp_rn_i0_t1_a(cp_rn_i0_t1_a),
.cp_rn_i0_t2_v(cp_rn_i0_t2_v),
.cp_rn_i0_t2_t(cp_rn_i0_t2_t),
.cp_rn_i0_t2_p(cp_rn_i0_t2_p),
.cp_rn_i0_t2_a(cp_rn_i0_t2_a),
.cp_rn_i0_t3_v(cp_rn_i0_t3_v),
.cp_rn_i0_t3_t(cp_rn_i0_t3_t),
.cp_rn_i0_t3_p(cp_rn_i0_t3_p),
.cp_rn_i0_t3_a(cp_rn_i0_t3_a),
.cp_rn_i1_v(cp_rn_i1_v),
.cp_rn_i1_itag(cp_rn_i1_itag),
.cp_rn_i1_t1_v(cp_rn_i1_t1_v),
.cp_rn_i1_t1_t(cp_rn_i1_t1_t),
.cp_rn_i1_t1_p(cp_rn_i1_t1_p),
.cp_rn_i1_t1_a(cp_rn_i1_t1_a),
.cp_rn_i1_t2_v(cp_rn_i1_t2_v),
.cp_rn_i1_t2_t(cp_rn_i1_t2_t),
.cp_rn_i1_t2_p(cp_rn_i1_t2_p),
.cp_rn_i1_t2_a(cp_rn_i1_t2_a),
.cp_rn_i1_t3_v(cp_rn_i1_t3_v),
.cp_rn_i1_t3_t(cp_rn_i1_t3_t),
.cp_rn_i1_t3_p(cp_rn_i1_t3_p),
.cp_rn_i1_t3_a(cp_rn_i1_t3_a),
.cp_flush(cp_flush),
.cp_flush_into_uc(cp_flush_into_uc),
.br_iu_redirect(br_iu_redirect),
.cp_rn_uc_credit_free(cp_rn_uc_credit_free),
//----------------------------------------------------------------
// AXU Interface
//----------------------------------------------------------------
.iu_au_iu5_send_ok(iu_au_iu5_send_ok),
.iu_au_iu5_next_itag_i0(iu_au_iu5_next_itag_i0),
.iu_au_iu5_next_itag_i1(iu_au_iu5_next_itag_i1),
.au_iu_iu5_axu0_send_ok(au_iu_iu5_axu0_send_ok),
.au_iu_iu5_axu1_send_ok(au_iu_iu5_axu1_send_ok),
.au_iu_iu5_i0_t1_p(au_iu_iu5_i0_t1_p),
.au_iu_iu5_i0_t2_p(au_iu_iu5_i0_t2_p),
.au_iu_iu5_i0_t3_p(au_iu_iu5_i0_t3_p),
.au_iu_iu5_i0_s1_p(au_iu_iu5_i0_s1_p),
.au_iu_iu5_i0_s2_p(au_iu_iu5_i0_s2_p),
.au_iu_iu5_i0_s3_p(au_iu_iu5_i0_s3_p),
.au_iu_iu5_i0_s1_itag(au_iu_iu5_i0_s1_itag),
.au_iu_iu5_i0_s2_itag(au_iu_iu5_i0_s2_itag),
.au_iu_iu5_i0_s3_itag(au_iu_iu5_i0_s3_itag),
.au_iu_iu5_i1_t1_p(au_iu_iu5_i1_t1_p),
.au_iu_iu5_i1_t2_p(au_iu_iu5_i1_t2_p),
.au_iu_iu5_i1_t3_p(au_iu_iu5_i1_t3_p),
.au_iu_iu5_i1_s1_p(au_iu_iu5_i1_s1_p),
.au_iu_iu5_i1_s2_p(au_iu_iu5_i1_s2_p),
.au_iu_iu5_i1_s3_p(au_iu_iu5_i1_s3_p),
.au_iu_iu5_i1_s1_dep_hit(au_iu_iu5_i1_s1_dep_hit),
.au_iu_iu5_i1_s2_dep_hit(au_iu_iu5_i1_s2_dep_hit),
.au_iu_iu5_i1_s3_dep_hit(au_iu_iu5_i1_s3_dep_hit),
.au_iu_iu5_i1_s1_itag(au_iu_iu5_i1_s1_itag),
.au_iu_iu5_i1_s2_itag(au_iu_iu5_i1_s2_itag),
.au_iu_iu5_i1_s3_itag(au_iu_iu5_i1_s3_itag),
//----------------------------------------------------------------
// Interface to reservation station - Completion is snooping also
//----------------------------------------------------------------
.frn_fdis_iu6_i0_vld(frn_fdis_iu6_i0_vld),
.frn_fdis_iu6_i0_itag(frn_fdis_iu6_i0_itag),
.frn_fdis_iu6_i0_ucode(frn_fdis_iu6_i0_ucode),
.frn_fdis_iu6_i0_ucode_cnt(frn_fdis_iu6_i0_ucode_cnt),
.frn_fdis_iu6_i0_2ucode(frn_fdis_iu6_i0_2ucode),
.frn_fdis_iu6_i0_fuse_nop(frn_fdis_iu6_i0_fuse_nop),
.frn_fdis_iu6_i0_rte_lq(frn_fdis_iu6_i0_rte_lq),
.frn_fdis_iu6_i0_rte_sq(frn_fdis_iu6_i0_rte_sq),
.frn_fdis_iu6_i0_rte_fx0(frn_fdis_iu6_i0_rte_fx0),
.frn_fdis_iu6_i0_rte_fx1(frn_fdis_iu6_i0_rte_fx1),
.frn_fdis_iu6_i0_rte_axu0(frn_fdis_iu6_i0_rte_axu0),
.frn_fdis_iu6_i0_rte_axu1(frn_fdis_iu6_i0_rte_axu1),
.frn_fdis_iu6_i0_valop(frn_fdis_iu6_i0_valop),
.frn_fdis_iu6_i0_ord(frn_fdis_iu6_i0_ord),
.frn_fdis_iu6_i0_cord(frn_fdis_iu6_i0_cord),
.frn_fdis_iu6_i0_error(frn_fdis_iu6_i0_error),
.frn_fdis_iu6_i0_btb_entry(frn_fdis_iu6_i0_btb_entry),
.frn_fdis_iu6_i0_btb_hist(frn_fdis_iu6_i0_btb_hist),
.frn_fdis_iu6_i0_bta_val(frn_fdis_iu6_i0_bta_val),
.frn_fdis_iu6_i0_fusion(frn_fdis_iu6_i0_fusion),
.frn_fdis_iu6_i0_spec(frn_fdis_iu6_i0_spec),
.frn_fdis_iu6_i0_type_fp(frn_fdis_iu6_i0_type_fp),
.frn_fdis_iu6_i0_type_ap(frn_fdis_iu6_i0_type_ap),
.frn_fdis_iu6_i0_type_spv(frn_fdis_iu6_i0_type_spv),
.frn_fdis_iu6_i0_type_st(frn_fdis_iu6_i0_type_st),
.frn_fdis_iu6_i0_async_block(frn_fdis_iu6_i0_async_block),
.frn_fdis_iu6_i0_np1_flush(frn_fdis_iu6_i0_np1_flush),
.frn_fdis_iu6_i0_core_block(frn_fdis_iu6_i0_core_block),
.frn_fdis_iu6_i0_isram(frn_fdis_iu6_i0_isram),
.frn_fdis_iu6_i0_isload(frn_fdis_iu6_i0_isload),
.frn_fdis_iu6_i0_isstore(frn_fdis_iu6_i0_isstore),
.frn_fdis_iu6_i0_instr(frn_fdis_iu6_i0_instr),
.frn_fdis_iu6_i0_ifar(frn_fdis_iu6_i0_ifar),
.frn_fdis_iu6_i0_bta(frn_fdis_iu6_i0_bta),
.frn_fdis_iu6_i0_br_pred(frn_fdis_iu6_i0_br_pred),
.frn_fdis_iu6_i0_bh_update(frn_fdis_iu6_i0_bh_update),
.frn_fdis_iu6_i0_bh0_hist(frn_fdis_iu6_i0_bh0_hist),
.frn_fdis_iu6_i0_bh1_hist(frn_fdis_iu6_i0_bh1_hist),
.frn_fdis_iu6_i0_bh2_hist(frn_fdis_iu6_i0_bh2_hist),
.frn_fdis_iu6_i0_gshare(frn_fdis_iu6_i0_gshare),
.frn_fdis_iu6_i0_ls_ptr(frn_fdis_iu6_i0_ls_ptr),
.frn_fdis_iu6_i0_match(frn_fdis_iu6_i0_match),
.frn_fdis_iu6_i0_ilat(frn_fdis_iu6_i0_ilat),
.frn_fdis_iu6_i0_t1_v(frn_fdis_iu6_i0_t1_v),
.frn_fdis_iu6_i0_t1_t(frn_fdis_iu6_i0_t1_t),
.frn_fdis_iu6_i0_t1_a(frn_fdis_iu6_i0_t1_a),
.frn_fdis_iu6_i0_t1_p(frn_fdis_iu6_i0_t1_p),
.frn_fdis_iu6_i0_t2_v(frn_fdis_iu6_i0_t2_v),
.frn_fdis_iu6_i0_t2_a(frn_fdis_iu6_i0_t2_a),
.frn_fdis_iu6_i0_t2_p(frn_fdis_iu6_i0_t2_p),
.frn_fdis_iu6_i0_t2_t(frn_fdis_iu6_i0_t2_t),
.frn_fdis_iu6_i0_t3_v(frn_fdis_iu6_i0_t3_v),
.frn_fdis_iu6_i0_t3_a(frn_fdis_iu6_i0_t3_a),
.frn_fdis_iu6_i0_t3_p(frn_fdis_iu6_i0_t3_p),
.frn_fdis_iu6_i0_t3_t(frn_fdis_iu6_i0_t3_t),
.frn_fdis_iu6_i0_s1_v(frn_fdis_iu6_i0_s1_v),
.frn_fdis_iu6_i0_s1_a(frn_fdis_iu6_i0_s1_a),
.frn_fdis_iu6_i0_s1_p(frn_fdis_iu6_i0_s1_p),
.frn_fdis_iu6_i0_s1_itag(frn_fdis_iu6_i0_s1_itag),
.frn_fdis_iu6_i0_s1_t(frn_fdis_iu6_i0_s1_t),
.frn_fdis_iu6_i0_s2_v(frn_fdis_iu6_i0_s2_v),
.frn_fdis_iu6_i0_s2_a(frn_fdis_iu6_i0_s2_a),
.frn_fdis_iu6_i0_s2_p(frn_fdis_iu6_i0_s2_p),
.frn_fdis_iu6_i0_s2_itag(frn_fdis_iu6_i0_s2_itag),
.frn_fdis_iu6_i0_s2_t(frn_fdis_iu6_i0_s2_t),
.frn_fdis_iu6_i0_s3_v(frn_fdis_iu6_i0_s3_v),
.frn_fdis_iu6_i0_s3_a(frn_fdis_iu6_i0_s3_a),
.frn_fdis_iu6_i0_s3_p(frn_fdis_iu6_i0_s3_p),
.frn_fdis_iu6_i0_s3_itag(frn_fdis_iu6_i0_s3_itag),
.frn_fdis_iu6_i0_s3_t(frn_fdis_iu6_i0_s3_t),
.frn_fdis_iu6_i1_vld(frn_fdis_iu6_i1_vld),
.frn_fdis_iu6_i1_itag(frn_fdis_iu6_i1_itag),
.frn_fdis_iu6_i1_ucode(frn_fdis_iu6_i1_ucode),
.frn_fdis_iu6_i1_ucode_cnt(frn_fdis_iu6_i1_ucode_cnt),
.frn_fdis_iu6_i1_fuse_nop(frn_fdis_iu6_i1_fuse_nop),
.frn_fdis_iu6_i1_rte_lq(frn_fdis_iu6_i1_rte_lq),
.frn_fdis_iu6_i1_rte_sq(frn_fdis_iu6_i1_rte_sq),
.frn_fdis_iu6_i1_rte_fx0(frn_fdis_iu6_i1_rte_fx0),
.frn_fdis_iu6_i1_rte_fx1(frn_fdis_iu6_i1_rte_fx1),
.frn_fdis_iu6_i1_rte_axu0(frn_fdis_iu6_i1_rte_axu0),
.frn_fdis_iu6_i1_rte_axu1(frn_fdis_iu6_i1_rte_axu1),
.frn_fdis_iu6_i1_valop(frn_fdis_iu6_i1_valop),
.frn_fdis_iu6_i1_ord(frn_fdis_iu6_i1_ord),
.frn_fdis_iu6_i1_cord(frn_fdis_iu6_i1_cord),
.frn_fdis_iu6_i1_error(frn_fdis_iu6_i1_error),
.frn_fdis_iu6_i1_btb_entry(frn_fdis_iu6_i1_btb_entry),
.frn_fdis_iu6_i1_btb_hist(frn_fdis_iu6_i1_btb_hist),
.frn_fdis_iu6_i1_bta_val(frn_fdis_iu6_i1_bta_val),
.frn_fdis_iu6_i1_fusion(frn_fdis_iu6_i1_fusion),
.frn_fdis_iu6_i1_spec(frn_fdis_iu6_i1_spec),
.frn_fdis_iu6_i1_type_fp(frn_fdis_iu6_i1_type_fp),
.frn_fdis_iu6_i1_type_ap(frn_fdis_iu6_i1_type_ap),
.frn_fdis_iu6_i1_type_spv(frn_fdis_iu6_i1_type_spv),
.frn_fdis_iu6_i1_type_st(frn_fdis_iu6_i1_type_st),
.frn_fdis_iu6_i1_async_block(frn_fdis_iu6_i1_async_block),
.frn_fdis_iu6_i1_np1_flush(frn_fdis_iu6_i1_np1_flush),
.frn_fdis_iu6_i1_core_block(frn_fdis_iu6_i1_core_block),
.frn_fdis_iu6_i1_isram(frn_fdis_iu6_i1_isram),
.frn_fdis_iu6_i1_isload(frn_fdis_iu6_i1_isload),
.frn_fdis_iu6_i1_isstore(frn_fdis_iu6_i1_isstore),
.frn_fdis_iu6_i1_instr(frn_fdis_iu6_i1_instr),
.frn_fdis_iu6_i1_ifar(frn_fdis_iu6_i1_ifar),
.frn_fdis_iu6_i1_bta(frn_fdis_iu6_i1_bta),
.frn_fdis_iu6_i1_br_pred(frn_fdis_iu6_i1_br_pred),
.frn_fdis_iu6_i1_bh_update(frn_fdis_iu6_i1_bh_update),
.frn_fdis_iu6_i1_bh0_hist(frn_fdis_iu6_i1_bh0_hist),
.frn_fdis_iu6_i1_bh1_hist(frn_fdis_iu6_i1_bh1_hist),
.frn_fdis_iu6_i1_bh2_hist(frn_fdis_iu6_i1_bh2_hist),
.frn_fdis_iu6_i1_gshare(frn_fdis_iu6_i1_gshare),
.frn_fdis_iu6_i1_ls_ptr(frn_fdis_iu6_i1_ls_ptr),
.frn_fdis_iu6_i1_match(frn_fdis_iu6_i1_match),
.frn_fdis_iu6_i1_ilat(frn_fdis_iu6_i1_ilat),
.frn_fdis_iu6_i1_t1_v(frn_fdis_iu6_i1_t1_v),
.frn_fdis_iu6_i1_t1_t(frn_fdis_iu6_i1_t1_t),
.frn_fdis_iu6_i1_t1_a(frn_fdis_iu6_i1_t1_a),
.frn_fdis_iu6_i1_t1_p(frn_fdis_iu6_i1_t1_p),
.frn_fdis_iu6_i1_t2_v(frn_fdis_iu6_i1_t2_v),
.frn_fdis_iu6_i1_t2_a(frn_fdis_iu6_i1_t2_a),
.frn_fdis_iu6_i1_t2_p(frn_fdis_iu6_i1_t2_p),
.frn_fdis_iu6_i1_t2_t(frn_fdis_iu6_i1_t2_t),
.frn_fdis_iu6_i1_t3_v(frn_fdis_iu6_i1_t3_v),
.frn_fdis_iu6_i1_t3_a(frn_fdis_iu6_i1_t3_a),
.frn_fdis_iu6_i1_t3_p(frn_fdis_iu6_i1_t3_p),
.frn_fdis_iu6_i1_t3_t(frn_fdis_iu6_i1_t3_t),
.frn_fdis_iu6_i1_s1_v(frn_fdis_iu6_i1_s1_v),
.frn_fdis_iu6_i1_s1_a(frn_fdis_iu6_i1_s1_a),
.frn_fdis_iu6_i1_s1_p(frn_fdis_iu6_i1_s1_p),
.frn_fdis_iu6_i1_s1_itag(frn_fdis_iu6_i1_s1_itag),
.frn_fdis_iu6_i1_s1_t(frn_fdis_iu6_i1_s1_t),
.frn_fdis_iu6_i1_s1_dep_hit(frn_fdis_iu6_i1_s1_dep_hit),
.frn_fdis_iu6_i1_s2_v(frn_fdis_iu6_i1_s2_v),
.frn_fdis_iu6_i1_s2_a(frn_fdis_iu6_i1_s2_a),
.frn_fdis_iu6_i1_s2_p(frn_fdis_iu6_i1_s2_p),
.frn_fdis_iu6_i1_s2_itag(frn_fdis_iu6_i1_s2_itag),
.frn_fdis_iu6_i1_s2_t(frn_fdis_iu6_i1_s2_t),
.frn_fdis_iu6_i1_s2_dep_hit(frn_fdis_iu6_i1_s2_dep_hit),
.frn_fdis_iu6_i1_s3_v(frn_fdis_iu6_i1_s3_v),
.frn_fdis_iu6_i1_s3_a(frn_fdis_iu6_i1_s3_a),
.frn_fdis_iu6_i1_s3_p(frn_fdis_iu6_i1_s3_p),
.frn_fdis_iu6_i1_s3_itag(frn_fdis_iu6_i1_s3_itag),
.frn_fdis_iu6_i1_s3_t(frn_fdis_iu6_i1_s3_t),
.frn_fdis_iu6_i1_s3_dep_hit(frn_fdis_iu6_i1_s3_dep_hit)
);
iuq_axu_fu_rn #(.FPR_POOL(`GPR_POOL), .FPR_UCODE_POOL(4), .FPSCR_POOL_ENC(5)) axu_rn0(
.vdd(vdd), // inout power_logic;
.gnd(gnd), // inout power_logic;
.nclk(nclk), // in clk_logic;
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), // in std_ulogic; acts as reset for non-ibm types
.pc_iu_sg_2(pc_iu_sg_2), // in std_ulogic;
.clkoff_b(clkoff_b), // in std_ulogic; todo
.act_dis(act_dis), // in std_ulogic; todo
.tc_ac_ccflush_dc(tc_ac_ccflush_dc), // in std_ulogic; todo
.d_mode(d_mode), // in std_ulogic;
.delay_lclkr(delay_lclkr), // in std_ulogic;
.mpw1_b(mpw1_b), // in std_ulogic;
.mpw2_b(mpw2_b), // in std_ulogic;
.func_scan_in(func_scan_in[1]), // in std_ulogic; todo: hookup
.func_scan_out(func_scan_out[1]), // out std_ulogic;
.iu_au_iu5_i0_vld(fdec_frn_iu5_i0_vld),
.iu_au_iu5_i0_ucode(fdec_frn_iu5_i0_ucode),
.iu_au_iu5_i0_rte_lq(fdec_frn_iu5_i0_rte_lq),
.iu_au_iu5_i0_rte_sq(fdec_frn_iu5_i0_rte_sq),
.iu_au_iu5_i0_rte_fx0(fdec_frn_iu5_i0_rte_fx0),
.iu_au_iu5_i0_rte_fx1(fdec_frn_iu5_i0_rte_fx1),
.iu_au_iu5_i0_rte_axu0(fdec_frn_iu5_i0_rte_axu0),
.iu_au_iu5_i0_rte_axu1(fdec_frn_iu5_i0_rte_axu1),
.iu_au_iu5_i0_ord(fdec_frn_iu5_i0_ord),
.iu_au_iu5_i0_cord(fdec_frn_iu5_i0_cord),
.iu_au_iu5_i0_instr(fdec_frn_iu5_i0_instr),
.iu_au_iu5_i0_ifar(fdec_frn_iu5_i0_ifar),
.iu_au_iu5_i0_gshare(fdec_frn_iu5_i0_gshare[0:9]),
.iu_au_iu5_i0_ilat(fdec_frn_iu5_i0_ilat),
.iu_au_iu5_i0_isload(fdec_frn_iu5_i0_isload),
.iu_au_iu5_i0_t1_v(fdec_frn_iu5_i0_t1_v),
.iu_au_iu5_i0_t1_t(fdec_frn_iu5_i0_t1_t),
.iu_au_iu5_i0_t1_a(fdec_frn_iu5_i0_t1_a),
.iu_au_iu5_i0_t2_v(fdec_frn_iu5_i0_t2_v),
.iu_au_iu5_i0_t2_t(fdec_frn_iu5_i0_t2_t),
.iu_au_iu5_i0_t2_a(fdec_frn_iu5_i0_t2_a),
.iu_au_iu5_i0_t3_v(fdec_frn_iu5_i0_t3_v),
.iu_au_iu5_i0_t3_t(fdec_frn_iu5_i0_t3_t),
.iu_au_iu5_i0_t3_a(fdec_frn_iu5_i0_t3_a),
.iu_au_iu5_i0_s1_v(fdec_frn_iu5_i0_s1_v),
.iu_au_iu5_i0_s1_t(fdec_frn_iu5_i0_s1_t),
.iu_au_iu5_i0_s1_a(fdec_frn_iu5_i0_s1_a),
.iu_au_iu5_i0_s2_v(fdec_frn_iu5_i0_s2_v),
.iu_au_iu5_i0_s2_t(fdec_frn_iu5_i0_s2_t),
.iu_au_iu5_i0_s2_a(fdec_frn_iu5_i0_s2_a),
.iu_au_iu5_i0_s3_v(fdec_frn_iu5_i0_s3_v),
.iu_au_iu5_i0_s3_t(fdec_frn_iu5_i0_s3_t),
.iu_au_iu5_i0_s3_a(fdec_frn_iu5_i0_s3_a),
.iu_au_iu5_i1_vld(fdec_frn_iu5_i1_vld),
.iu_au_iu5_i1_ucode(fdec_frn_iu5_i1_ucode),
.iu_au_iu5_i1_rte_lq(fdec_frn_iu5_i1_rte_lq),
.iu_au_iu5_i1_rte_sq(fdec_frn_iu5_i1_rte_sq),
.iu_au_iu5_i1_rte_fx0(fdec_frn_iu5_i1_rte_fx0),
.iu_au_iu5_i1_rte_fx1(fdec_frn_iu5_i1_rte_fx1),
.iu_au_iu5_i1_rte_axu0(fdec_frn_iu5_i1_rte_axu0),
.iu_au_iu5_i1_rte_axu1(fdec_frn_iu5_i1_rte_axu1),
.iu_au_iu5_i1_ord(fdec_frn_iu5_i1_ord),
.iu_au_iu5_i1_cord(fdec_frn_iu5_i1_cord),
.iu_au_iu5_i1_instr(fdec_frn_iu5_i1_instr),
.iu_au_iu5_i1_ifar(fdec_frn_iu5_i1_ifar),
.iu_au_iu5_i1_gshare(fdec_frn_iu5_i1_gshare[0:9]),
.iu_au_iu5_i1_ilat(fdec_frn_iu5_i1_ilat),
.iu_au_iu5_i1_isload(fdec_frn_iu5_i1_isload),
.iu_au_iu5_i1_t1_v(fdec_frn_iu5_i1_t1_v),
.iu_au_iu5_i1_t1_t(fdec_frn_iu5_i1_t1_t),
.iu_au_iu5_i1_t1_a(fdec_frn_iu5_i1_t1_a),
.iu_au_iu5_i1_t2_v(fdec_frn_iu5_i1_t2_v),
.iu_au_iu5_i1_t2_t(fdec_frn_iu5_i1_t2_t),
.iu_au_iu5_i1_t2_a(fdec_frn_iu5_i1_t2_a),
.iu_au_iu5_i1_t3_v(fdec_frn_iu5_i1_t3_v),
.iu_au_iu5_i1_t3_t(fdec_frn_iu5_i1_t3_t),
.iu_au_iu5_i1_t3_a(fdec_frn_iu5_i1_t3_a),
.iu_au_iu5_i1_s1_v(fdec_frn_iu5_i1_s1_v),
.iu_au_iu5_i1_s1_t(fdec_frn_iu5_i1_s1_t),
.iu_au_iu5_i1_s1_a(fdec_frn_iu5_i1_s1_a),
.iu_au_iu5_i1_s2_v(fdec_frn_iu5_i1_s2_v),
.iu_au_iu5_i1_s2_t(fdec_frn_iu5_i1_s2_t),
.iu_au_iu5_i1_s2_a(fdec_frn_iu5_i1_s2_a),
.iu_au_iu5_i1_s3_v(fdec_frn_iu5_i1_s3_v),
.iu_au_iu5_i1_s3_t(fdec_frn_iu5_i1_s3_t),
.iu_au_iu5_i1_s3_a(fdec_frn_iu5_i1_s3_a),
.spr_single_issue(1'b0), // in std_ulogic;
.au_iu_iu5_stall(au_iu_iu5_stall), // out std_ulogic;
.cp_rn_i0_axu_exception_val(cp_rn_i0_axu_exception_val),
.cp_rn_i0_axu_exception(cp_rn_i0_axu_exception),
.cp_rn_i0_itag(cp_rn_i0_itag),
.cp_rn_i0_t1_v(cp_rn_i0_t1_v), // in std_ulogic;
.cp_rn_i0_t1_t(cp_rn_i0_t1_t), // in std_ulogic;
.cp_rn_i0_t1_p(cp_rn_i0_t1_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i0_t1_a(cp_rn_i0_t1_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i0_t2_v(cp_rn_i0_t2_v), // in std_ulogic;
.cp_rn_i0_t2_t(cp_rn_i0_t2_t), // in std_ulogic_vector(0 to 2);
.cp_rn_i0_t2_p(cp_rn_i0_t2_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i0_t2_a(cp_rn_i0_t2_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i0_t3_v(cp_rn_i0_t3_v), // in std_ulogic;
.cp_rn_i0_t3_t(cp_rn_i0_t3_t), // in std_ulogic_vector(0 to 2);
.cp_rn_i0_t3_p(cp_rn_i0_t3_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i0_t3_a(cp_rn_i0_t3_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i1_axu_exception_val(cp_rn_i1_axu_exception_val),
.cp_rn_i1_axu_exception(cp_rn_i1_axu_exception),
.cp_rn_i1_itag(cp_rn_i1_itag),
.cp_rn_i1_t1_v(cp_rn_i1_t1_v), // in std_ulogic;
.cp_rn_i1_t1_t(cp_rn_i1_t1_t), // in std_ulogic;
.cp_rn_i1_t1_p(cp_rn_i1_t1_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i1_t1_a(cp_rn_i1_t1_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i1_t2_v(cp_rn_i1_t2_v), // in std_ulogic;
.cp_rn_i1_t2_t(cp_rn_i1_t2_t), // in std_ulogic_vector(0 to 2);
.cp_rn_i1_t2_p(cp_rn_i1_t2_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i1_t2_a(cp_rn_i1_t2_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i1_t3_v(cp_rn_i1_t3_v), // in std_ulogic;
.cp_rn_i1_t3_t(cp_rn_i1_t3_t), // in std_ulogic_vector(0 to 2);
.cp_rn_i1_t3_p(cp_rn_i1_t3_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_rn_i1_t3_a(cp_rn_i1_t3_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
.cp_flush(cp_flush), // in std_ulogic;
.br_iu_redirect(br_iu_redirect),
.iu_au_iu5_send_ok(iu_au_iu5_send_ok),
.iu_au_iu5_next_itag_i0(iu_au_iu5_next_itag_i0),
.iu_au_iu5_next_itag_i1(iu_au_iu5_next_itag_i1),
.au_iu_iu5_axu0_send_ok(au_iu_iu5_axu0_send_ok),
.au_iu_iu5_axu1_send_ok(au_iu_iu5_axu1_send_ok),
.au_iu_iu5_i0_t1_p(au_iu_iu5_i0_t1_p),
.au_iu_iu5_i0_t2_p(au_iu_iu5_i0_t2_p),
.au_iu_iu5_i0_t3_p(au_iu_iu5_i0_t3_p),
.au_iu_iu5_i0_s1_p(au_iu_iu5_i0_s1_p),
.au_iu_iu5_i0_s2_p(au_iu_iu5_i0_s2_p),
.au_iu_iu5_i0_s3_p(au_iu_iu5_i0_s3_p),
.au_iu_iu5_i0_s1_itag(au_iu_iu5_i0_s1_itag),
.au_iu_iu5_i0_s2_itag(au_iu_iu5_i0_s2_itag),
.au_iu_iu5_i0_s3_itag(au_iu_iu5_i0_s3_itag),
.au_iu_iu5_i1_t1_p(au_iu_iu5_i1_t1_p),
.au_iu_iu5_i1_t2_p(au_iu_iu5_i1_t2_p),
.au_iu_iu5_i1_t3_p(au_iu_iu5_i1_t3_p),
.au_iu_iu5_i1_s1_p(au_iu_iu5_i1_s1_p),
.au_iu_iu5_i1_s2_p(au_iu_iu5_i1_s2_p),
.au_iu_iu5_i1_s3_p(au_iu_iu5_i1_s3_p),
.au_iu_iu5_i1_s1_dep_hit(au_iu_iu5_i1_s1_dep_hit),
.au_iu_iu5_i1_s2_dep_hit(au_iu_iu5_i1_s2_dep_hit),
.au_iu_iu5_i1_s3_dep_hit(au_iu_iu5_i1_s3_dep_hit),
.au_iu_iu5_i1_s1_itag(au_iu_iu5_i1_s1_itag),
.au_iu_iu5_i1_s2_itag(au_iu_iu5_i1_s2_itag),
.au_iu_iu5_i1_s3_itag(au_iu_iu5_i1_s3_itag)
);
endmodule |
module xu_alu_cmp(
// Clocks
input [0:`NCLK_WIDTH-1] nclk,
// Power
inout vdd,
inout gnd,
// Pervasive
input d_mode_dc,
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input sg_0,
input scan_in,
output scan_out,
input ex2_act,
input ex1_msb_64b_sel,
input [6:10] ex2_instr,
input ex2_sel_trap,
input ex2_sel_cmpl,
input ex2_sel_cmp,
input ex2_rs1_00,
input ex2_rs1_32,
input ex2_rs2_00,
input ex2_rs2_32,
input [64-`GPR_WIDTH:63] ex3_alu_rt,
input ex3_add_ca,
output [0:2] ex3_alu_cr,
output ex3_trap_val
);
localparam msb = 64 - `GPR_WIDTH;
// Latches
wire ex2_msb_64b_sel_q; // input=>ex1_msb_64b_sel ,act=>1'b1
wire ex3_msb_64b_sel_q; // input=>ex2_msb_64b_sel_q ,act=>ex2_act
wire ex3_diff_sign_q; // input=>ex2_diff_sign ,act=>ex2_act
wire ex2_diff_sign;
wire ex3_rs1_trm1_q; // input=>ex2_rs1_trm1 ,act=>ex2_act
wire ex2_rs1_trm1;
wire ex3_rs2_trm1_q; // input=>ex2_rs2_trm1 ,act=>ex2_act
wire ex2_rs2_trm1;
wire [6:10] ex3_instr_q; // input=>ex2_instr ,act=>ex2_act
wire ex3_sel_trap_q; // input=>ex2_sel_trap ,act=>ex2_act
wire ex3_sel_cmpl_q; // input=>ex2_sel_cmpl ,act=>ex2_act
wire ex3_sel_cmp_q; // input=>ex2_sel_cmp ,act=>ex2_act
// Scanchains
localparam ex2_msb_64b_sel_offset = 0;
localparam ex3_msb_64b_sel_offset = ex2_msb_64b_sel_offset + 1;
localparam ex3_diff_sign_offset = ex3_msb_64b_sel_offset + 1;
localparam ex3_rs1_trm1_offset = ex3_diff_sign_offset + 1;
localparam ex3_rs2_trm1_offset = ex3_rs1_trm1_offset + 1;
localparam ex3_instr_offset = ex3_rs2_trm1_offset + 1;
localparam ex3_sel_trap_offset = ex3_instr_offset + 5;
localparam ex3_sel_cmpl_offset = ex3_sel_trap_offset + 1;
localparam ex3_sel_cmp_offset = ex3_sel_cmpl_offset + 1;
localparam scan_right = ex3_sel_cmp_offset + 1;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
// Signals
wire ex3_cmp0_hi;
wire ex3_cmp0_lo;
wire ex3_cmp0_eq;
wire ex2_rs1_msb;
wire ex2_rs2_msb;
wire ex3_rt_msb;
wire ex3_rslt_gt_s;
wire ex3_rslt_lt_s;
wire ex3_rslt_gt_u;
wire ex3_rslt_lt_u;
wire ex3_cmp_eq;
wire ex3_cmp_gt;
wire ex3_cmp_lt;
wire ex3_sign_cmp;
tri_st_or3232 or3232(
.d(ex3_alu_rt),
.or_hi_b(ex3_cmp0_hi),
.or_lo_b(ex3_cmp0_lo)
);
assign ex2_rs1_msb = (ex2_msb_64b_sel_q == 1'b1) ? ex2_rs1_00 : ex2_rs1_32;
assign ex2_rs2_msb = (ex2_msb_64b_sel_q == 1'b1) ? ex2_rs2_00 : ex2_rs2_32;
assign ex3_rt_msb = (ex3_msb_64b_sel_q == 1'b1) ? ex3_alu_rt[msb] : ex3_alu_rt[32];
// If the signs are different, then we immediately know if one is bigger than the other.
// but only look at this in case of compare instructions
assign ex3_cmp0_eq = (ex3_msb_64b_sel_q == 1'b1) ? (ex3_cmp0_lo & ex3_cmp0_hi) : ex3_cmp0_lo;
assign ex2_diff_sign = (ex2_rs1_msb ^ ex2_rs2_msb) & (ex2_sel_cmpl | ex2_sel_cmp | ex2_sel_trap);
// In case the sigs are not different, we need some more logic
// Look at adder carry out for compares (need to be able to check over flow case)
// Look at sign bit for record forms (overflow is ignored, ie two positives equal a negative.)
assign ex3_sign_cmp = ((ex3_sel_cmpl_q | ex3_sel_cmp_q | ex3_sel_trap_q) == 1'b1) ? ex3_add_ca : ex3_rt_msb;
assign ex2_rs1_trm1 = ex2_rs1_msb & ex2_diff_sign;
assign ex2_rs2_trm1 = ex2_rs2_msb & ex2_diff_sign;
// Signed compare
assign ex3_rslt_gt_s = (ex3_rs2_trm1_q | (~ex3_sign_cmp & ~ex3_diff_sign_q)); // RS2 < RS1
assign ex3_rslt_lt_s = (ex3_rs1_trm1_q | ( ex3_sign_cmp & ~ex3_diff_sign_q)); // RS2 > RS1
// Unsigned compare
assign ex3_rslt_gt_u = (ex3_rs1_trm1_q | (~ex3_sign_cmp & ~ex3_diff_sign_q)); // RS2 < RS1
assign ex3_rslt_lt_u = (ex3_rs2_trm1_q | ( ex3_sign_cmp & ~ex3_diff_sign_q)); // RS2 > RS1
assign ex3_cmp_eq = ex3_cmp0_eq;
assign ex3_cmp_gt = ((~ex3_sel_cmpl_q & ex3_rslt_gt_s) | (ex3_sel_cmpl_q & ex3_rslt_gt_u)) & (~ex3_cmp0_eq);
assign ex3_cmp_lt = ((~ex3_sel_cmpl_q & ex3_rslt_lt_s) | (ex3_sel_cmpl_q & ex3_rslt_lt_u)) & (~ex3_cmp0_eq);
// CR Field for Add, Logical, Rotate
assign ex3_alu_cr = {ex3_cmp_lt, ex3_cmp_gt, ex3_cmp_eq};
// Trap logic
assign ex3_trap_val = ex3_sel_trap_q &
((ex3_instr_q[6] & (~ex3_cmp_eq) & ex3_rslt_lt_s) |
(ex3_instr_q[7] & (~ex3_cmp_eq) & ex3_rslt_gt_s) |
(ex3_instr_q[8] & ex3_cmp_eq) |
(ex3_instr_q[9] & (~ex3_cmp_eq) & ex3_rslt_lt_u) |
(ex3_instr_q[10] & (~ex3_cmp_eq) & ex3_rslt_gt_u));
// Latch Instances
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msb_64b_sel_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(1'b1),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex2_msb_64b_sel_offset]),
.scout(sov[ex2_msb_64b_sel_offset]),
.din(ex1_msb_64b_sel),
.dout(ex2_msb_64b_sel_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_msb_64b_sel_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_msb_64b_sel_offset]),
.scout(sov[ex3_msb_64b_sel_offset]),
.din(ex2_msb_64b_sel_q),
.dout(ex3_msb_64b_sel_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_diff_sign_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_diff_sign_offset]),
.scout(sov[ex3_diff_sign_offset]),
.din(ex2_diff_sign),
.dout(ex3_diff_sign_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_rs1_trm1_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_rs1_trm1_offset]),
.scout(sov[ex3_rs1_trm1_offset]),
.din(ex2_rs1_trm1),
.dout(ex3_rs1_trm1_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_rs2_trm1_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_rs2_trm1_offset]),
.scout(sov[ex3_rs2_trm1_offset]),
.din(ex2_rs2_trm1),
.dout(ex3_rs2_trm1_q)
);
tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_instr_offset:ex3_instr_offset + 5 - 1]),
.scout(sov[ex3_instr_offset:ex3_instr_offset + 5 - 1]),
.din(ex2_instr),
.dout(ex3_instr_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_trap_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_sel_trap_offset]),
.scout(sov[ex3_sel_trap_offset]),
.din(ex2_sel_trap),
.dout(ex3_sel_trap_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_cmpl_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_sel_cmpl_offset]),
.scout(sov[ex3_sel_cmpl_offset]),
.din(ex2_sel_cmpl),
.dout(ex3_sel_cmpl_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_cmp_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(ex2_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_sel_cmp_offset]),
.scout(sov[ex3_sel_cmp_offset]),
.din(ex2_sel_cmp),
.dout(ex3_sel_cmp_q)
);
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
endmodule |
module iuq_rn_map #(
parameter ARCHITECTED_REGISTER_DEPTH = 36,
parameter REGISTER_RENAME_DEPTH = 64,
parameter STORAGE_WIDTH = 6)
(
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input pc_iu_func_sl_thold_0_b, // acts as reset for non-ibm types
input pc_iu_sg_0,
input force_t,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input func_scan_in,
output func_scan_out,
input take_a,
input take_b,
output next_reg_a_val,
output reg [0:STORAGE_WIDTH-1] next_reg_a,
output next_reg_b_val,
output reg [0:STORAGE_WIDTH-1] next_reg_b,
input [0:STORAGE_WIDTH-1] src1_a,
output reg [0:STORAGE_WIDTH-1] src1_p,
output reg [0:`ITAG_SIZE_ENC-1] src1_itag,
input [0:STORAGE_WIDTH-1] src2_a,
output reg [0:STORAGE_WIDTH-1] src2_p,
output reg [0:`ITAG_SIZE_ENC-1] src2_itag,
input [0:STORAGE_WIDTH-1] src3_a,
output reg [0:STORAGE_WIDTH-1] src3_p,
output reg [0:`ITAG_SIZE_ENC-1] src3_itag,
input [0:STORAGE_WIDTH-1] src4_a,
output [0:STORAGE_WIDTH-1] src4_p,
output [0:`ITAG_SIZE_ENC-1] src4_itag,
input [0:STORAGE_WIDTH-1] src5_a,
output [0:STORAGE_WIDTH-1] src5_p,
output [0:`ITAG_SIZE_ENC-1] src5_itag,
input [0:STORAGE_WIDTH-1] src6_a,
output [0:STORAGE_WIDTH-1] src6_p,
output [0:`ITAG_SIZE_ENC-1] src6_itag,
input comp_0_wr_val,
input [0:STORAGE_WIDTH-1] comp_0_wr_arc,
input [0:STORAGE_WIDTH-1] comp_0_wr_rename,
input [0:`ITAG_SIZE_ENC-1] comp_0_wr_itag,
input comp_1_wr_val,
input [0:STORAGE_WIDTH-1] comp_1_wr_arc,
input [0:STORAGE_WIDTH-1] comp_1_wr_rename,
input [0:`ITAG_SIZE_ENC-1] comp_1_wr_itag,
input spec_0_wr_val,
input spec_0_wr_val_fast,
input [0:STORAGE_WIDTH-1] spec_0_wr_arc,
input [0:STORAGE_WIDTH-1] spec_0_wr_rename,
input [0:`ITAG_SIZE_ENC-1] spec_0_wr_itag,
input spec_1_dep_hit_s1,
input spec_1_dep_hit_s2,
input spec_1_dep_hit_s3,
input spec_1_wr_val,
input spec_1_wr_val_fast,
input [0:STORAGE_WIDTH-1] spec_1_wr_arc,
input [0:STORAGE_WIDTH-1] spec_1_wr_rename,
input [0:`ITAG_SIZE_ENC-1] spec_1_wr_itag,
input flush_map
);
localparam [0:31] value_1 = 32'h00000001;
localparam [0:31] value_2 = 32'h00000002;
parameter comp_map_offset = 0;
parameter spec_map_arc_offset = comp_map_offset + STORAGE_WIDTH * ARCHITECTED_REGISTER_DEPTH;
parameter spec_map_itag_offset = spec_map_arc_offset + STORAGE_WIDTH * ARCHITECTED_REGISTER_DEPTH;
parameter buffer_pool_offset = spec_map_itag_offset + `ITAG_SIZE_ENC * ARCHITECTED_REGISTER_DEPTH;
parameter read_ptr_offset = buffer_pool_offset + (REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH) * STORAGE_WIDTH;
parameter write_ptr_offset = read_ptr_offset + STORAGE_WIDTH;
parameter free_cnt_offset = write_ptr_offset + STORAGE_WIDTH;
parameter pool_free_0_v_offset = free_cnt_offset + STORAGE_WIDTH;
parameter pool_free_0_offset = pool_free_0_v_offset + 1;
parameter pool_free_1_v_offset = pool_free_0_offset + STORAGE_WIDTH;
parameter pool_free_1_offset = pool_free_1_v_offset + 1;
parameter scan_right = pool_free_1_offset + STORAGE_WIDTH - 1;
// scan
wire [0:scan_right] siv;
wire [0:scan_right] sov;
wire tidn;
wire tiup;
wire comp_map_act;
reg [0:STORAGE_WIDTH-1] comp_map_d[0:ARCHITECTED_REGISTER_DEPTH-1];
wire [0:STORAGE_WIDTH-1] comp_map_l2[0:ARCHITECTED_REGISTER_DEPTH-1];
wire spec_map_arc_act;
reg [0:STORAGE_WIDTH-1] spec_map_arc_d[0:ARCHITECTED_REGISTER_DEPTH-1];
wire [0:STORAGE_WIDTH-1] spec_map_arc_l2[0:ARCHITECTED_REGISTER_DEPTH-1];
wire spec_map_itag_act;
reg [0:`ITAG_SIZE_ENC-1] spec_map_itag_d[0:ARCHITECTED_REGISTER_DEPTH-1];
wire [0:`ITAG_SIZE_ENC-1] spec_map_itag_l2[0:ARCHITECTED_REGISTER_DEPTH-1];
reg [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] buffer_pool_act;
reg [0:STORAGE_WIDTH-1] buffer_pool_d[0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1];
wire [0:STORAGE_WIDTH-1] buffer_pool_l2[0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1];
wire read_ptr_act;
wire [0:STORAGE_WIDTH-1] read_ptr_d;
wire [0:STORAGE_WIDTH-1] read_ptr_l2;
wire [0:STORAGE_WIDTH-1] read_ptr_inc;
reg [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] read_ptr;
wire [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] read_ptr_p1;
wire write_ptr_act;
wire [0:STORAGE_WIDTH-1] write_ptr_d;
wire [0:STORAGE_WIDTH-1] write_ptr_l2;
reg [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] write_ptr;
wire [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] write_ptr_p1;
wire [0:STORAGE_WIDTH-1] write_ptr_value;
wire free_cnt_act;
reg [0:STORAGE_WIDTH-1] free_cnt_d;
wire [0:STORAGE_WIDTH-1] free_cnt_l2;
reg pool_free_0_v_d;
wire pool_free_0_v_l2;
reg [0:STORAGE_WIDTH-1] pool_free_0_d;
wire [0:STORAGE_WIDTH-1] pool_free_0_l2;
reg pool_free_1_v_d;
wire pool_free_1_v_l2;
reg [0:STORAGE_WIDTH-1] pool_free_1_d;
wire [0:STORAGE_WIDTH-1] pool_free_1_l2;
// temporary signal prior to mux select for i0->i1 bypass
reg [0:STORAGE_WIDTH-1] src4_temp_p;
reg [0:STORAGE_WIDTH-1] src5_temp_p;
reg [0:STORAGE_WIDTH-1] src6_temp_p;
reg [0:`ITAG_SIZE_ENC-1] src4_temp_itag;
reg [0:`ITAG_SIZE_ENC-1] src5_temp_itag;
reg [0:`ITAG_SIZE_ENC-1] src6_temp_itag;
assign tidn = 1'b0;
assign tiup = 1'b1;
always @( * )
begin: read_spec_map_arc_proc
integer i;
src1_p <= 0;
src2_p <= 0;
src3_p <= 0;
src4_temp_p <= 0;
src5_temp_p <= 0;
src6_temp_p <= 0;
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin
if (src1_a == i)
src1_p <= spec_map_arc_l2[i];
if (src2_a == i)
src2_p <= spec_map_arc_l2[i];
if (src3_a == i)
src3_p <= spec_map_arc_l2[i];
if (src4_a == i)
src4_temp_p <= spec_map_arc_l2[i];
if (src5_a == i)
src5_temp_p <= spec_map_arc_l2[i];
if (src6_a == i)
src6_temp_p <= spec_map_arc_l2[i];
end
end
assign src4_p = spec_1_dep_hit_s1 ? spec_0_wr_rename :
src4_temp_p;
assign src5_p = spec_1_dep_hit_s2 ? spec_0_wr_rename :
src5_temp_p;
assign src6_p = spec_1_dep_hit_s3 ? spec_0_wr_rename :
src6_temp_p;
always @( * )
begin: read_spec_map_itag_proc
integer i;
src1_itag <= 0;
src2_itag <= 0;
src3_itag <= 0;
src4_temp_itag <= 0;
src5_temp_itag <= 0;
src6_temp_itag <= 0;
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin
if (src1_a == i)
src1_itag <= spec_map_itag_l2[i];
if (src2_a == i)
src2_itag <= spec_map_itag_l2[i];
if (src3_a == i)
src3_itag <= spec_map_itag_l2[i];
if (src4_a == i)
src4_temp_itag <= spec_map_itag_l2[i];
if (src5_a == i)
src5_temp_itag <= spec_map_itag_l2[i];
if (src6_a == i)
src6_temp_itag <= spec_map_itag_l2[i];
end
end
assign src4_itag = spec_1_dep_hit_s1 ? spec_0_wr_itag :
src4_temp_itag;
assign src5_itag = spec_1_dep_hit_s2 ? spec_0_wr_itag :
src5_temp_itag;
assign src6_itag = spec_1_dep_hit_s3 ? spec_0_wr_itag :
src6_temp_itag;
assign comp_map_act = comp_0_wr_val | comp_1_wr_val;
always @( * )
begin: set_comp_map_proc
integer i;
pool_free_0_v_d <= 0;
pool_free_0_d <= 0;
pool_free_1_v_d <= 0;
pool_free_1_d <= 0;
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin
comp_map_d[i] <= comp_map_l2[i];
if ((comp_0_wr_val == 1'b1) & (comp_1_wr_val == 1'b1) & (comp_0_wr_arc == comp_1_wr_arc) & comp_0_wr_arc == i)
begin
comp_map_d[i] <= comp_1_wr_rename;
pool_free_0_v_d <= 1'b1;
pool_free_0_d <= comp_map_l2[i];
pool_free_1_v_d <= 1'b1;
pool_free_1_d <= comp_0_wr_rename;
end
else
begin
if ((comp_0_wr_val == 1'b1) & comp_0_wr_arc == i)
begin
comp_map_d[i] <= comp_0_wr_rename;
pool_free_0_v_d <= 1'b1;
pool_free_0_d <= comp_map_l2[i];
end
if ((comp_1_wr_val == 1'b1) & comp_1_wr_arc == i)
begin
comp_map_d[i] <= comp_1_wr_rename;
pool_free_1_v_d <= 1'b1;
pool_free_1_d <= comp_map_l2[i];
end
end
end
end
assign spec_map_arc_act = flush_map | spec_0_wr_val_fast | spec_1_wr_val_fast;
assign spec_map_itag_act = 1'b1;
generate
begin : xhdl1
genvar i;
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : map_set0
always @(flush_map or spec_0_wr_val or spec_0_wr_arc or spec_0_wr_rename or spec_1_wr_val or spec_1_wr_arc or spec_1_wr_rename or spec_map_arc_l2[i] or comp_map_l2[i])
begin: set_spec_map_arc_proc
spec_map_arc_d[i] <= spec_map_arc_l2[i];
if (flush_map == 1'b1)
spec_map_arc_d[i] <= comp_map_l2[i];
else if ((spec_1_wr_val == 1'b1) & spec_1_wr_arc == i)
spec_map_arc_d[i] <= spec_1_wr_rename;
else if ((spec_0_wr_val == 1'b1) & spec_0_wr_arc == i)
spec_map_arc_d[i] <= spec_0_wr_rename;
end
always @(flush_map or spec_0_wr_val or spec_0_wr_arc or spec_0_wr_itag or spec_1_wr_val or spec_1_wr_arc or spec_1_wr_itag or spec_map_itag_l2[i] or comp_0_wr_val or comp_0_wr_itag or comp_1_wr_val or comp_1_wr_itag)
begin: set_spec_map_itag_proc
spec_map_itag_d[i] <= spec_map_itag_l2[i];
if (flush_map == 1'b1)
spec_map_itag_d[i] <= {`ITAG_SIZE_ENC{1'b1}};
else if ((spec_1_wr_val == 1'b1) & spec_1_wr_arc == i)
spec_map_itag_d[i] <= spec_1_wr_itag;
else if ((spec_0_wr_val == 1'b1) & spec_0_wr_arc == i)
spec_map_itag_d[i] <= spec_0_wr_itag;
else
begin
if ((comp_0_wr_val == 1'b1) & comp_0_wr_itag == spec_map_itag_l2[i])
spec_map_itag_d[i] <= {`ITAG_SIZE_ENC{1'b1}};
if ((comp_1_wr_val == 1'b1) & comp_1_wr_itag == spec_map_itag_l2[i])
spec_map_itag_d[i] <= {`ITAG_SIZE_ENC{1'b1}};
end
end
end
end
endgenerate
generate
begin : write_ptr_calc
genvar i;
for(i = 0; i <= (REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1); i = i + 1)
begin : write_ptr_set
always @( * )
if (write_ptr_l2 == i)
write_ptr[i] <= (pool_free_0_v_l2 | pool_free_1_v_l2);
else
write_ptr[i] <= 1'b0;
end
end
endgenerate
assign write_ptr_p1 = {REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH{pool_free_0_v_l2 & pool_free_1_v_l2}} &
({write_ptr[REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1], write_ptr[0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-2]});
assign write_ptr_value = ({pool_free_0_v_l2, pool_free_1_v_l2} == 2'b01) ? pool_free_1_l2 :
pool_free_0_l2;
generate
begin : xhdl2
genvar i;
for (i = 0; i <= REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : buffer_pool_gen
always @( * )
begin
buffer_pool_act[i] <= write_ptr[i] | write_ptr_p1[i];
buffer_pool_d[i] <= ({STORAGE_WIDTH{write_ptr[i]}} & write_ptr_value) |
({STORAGE_WIDTH{write_ptr_p1[i]}} & pool_free_1_l2);
end
end
end
endgenerate
iuq_rn_map_inc #(.SIZE(STORAGE_WIDTH), .WRAP(REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1)) read_ptr_inc0(
.inc({take_a, take_b}),
.i(read_ptr_l2),
.o(read_ptr_inc)
);
assign read_ptr_act = take_a | take_b | flush_map;
assign read_ptr_d = (flush_map == 1'b0) ? read_ptr_inc :
write_ptr_l2;
assign write_ptr_act = pool_free_0_v_l2 | pool_free_1_v_l2;
iuq_rn_map_inc #(.SIZE(STORAGE_WIDTH), .WRAP(REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1)) write_ptr_inc0(
.inc({pool_free_0_v_l2, pool_free_1_v_l2}),
.i(write_ptr_l2),
.o(write_ptr_d)
);
assign free_cnt_act = flush_map | take_a | take_b | pool_free_0_v_l2 | pool_free_1_v_l2;
always @(flush_map or take_a or take_b or pool_free_0_v_l2 or pool_free_1_v_l2 or free_cnt_l2)
begin: free_cnt_proc
free_cnt_d <= free_cnt_l2;
if (flush_map == 1'b1)
free_cnt_d <= REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH;
else
begin
if ((take_a == 1'b0 & (pool_free_0_v_l2 == 1'b1 ^ pool_free_1_v_l2 == 1'b1)) |
(take_a == 1'b1 & take_b == 1'b0 & pool_free_0_v_l2 == 1'b1 & pool_free_1_v_l2 == 1'b1))
free_cnt_d <= free_cnt_l2 + value_1[32-STORAGE_WIDTH:31];
if (take_a == 1'b0 & pool_free_0_v_l2 == 1'b1 & pool_free_1_v_l2 == 1'b1)
free_cnt_d <= free_cnt_l2 + value_2[32-STORAGE_WIDTH:31];
if ((take_a == 1'b1 & take_b == 1'b0 & pool_free_0_v_l2 == 1'b0 & pool_free_1_v_l2 == 1'b0) |
(take_a == 1'b1 & take_b == 1'b1 & (pool_free_0_v_l2 == 1'b1 ^ pool_free_1_v_l2 == 1'b1)))
free_cnt_d <= free_cnt_l2 - value_1[32-STORAGE_WIDTH:31];
if (take_a == 1'b1 & take_b == 1'b1 & pool_free_0_v_l2 == 1'b0 & pool_free_1_v_l2 == 1'b0)
free_cnt_d <= free_cnt_l2 - value_2[32-STORAGE_WIDTH:31];
end
end
// Creating 1 hot muxing from pointers
generate
begin : read_ptr_calc
genvar i;
for(i = 0; i <= (REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1); i = i + 1)
begin : read_ptr_set
always @( * )
if (read_ptr_l2 == i)
read_ptr[i] <= 1'b1;
else
read_ptr[i] <= 1'b0;
end
end
endgenerate
assign read_ptr_p1 = {read_ptr[REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1], read_ptr[0:REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 2]};
// OUTPUTS
assign next_reg_a_val = (~(free_cnt_l2 == 0));
assign next_reg_b_val = (~(free_cnt_l2 == 1));
always @( * )
begin: next_reg_proc
integer e;
next_reg_a <= 0;
next_reg_b <= 0;
for (e = 0; e <= (REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1+1) - 1; e = e + 1)
begin
if (read_ptr[e] == 1'b1)
next_reg_a <= buffer_pool_l2[e];
if (read_ptr_p1[e] == 1'b1)
next_reg_b <= buffer_pool_l2[e];
end
end
generate
begin : xhdl3
genvar i;
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : comp_map0
tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(i)) comp_map_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(comp_map_act),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b),
.d_mode(d_mode),
.sg(pc_iu_sg_0),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scin(siv[comp_map_offset + (STORAGE_WIDTH) * i:comp_map_offset + (STORAGE_WIDTH) * (i + 1) - 1]),
.scout(sov[comp_map_offset + (STORAGE_WIDTH) * i:comp_map_offset + (STORAGE_WIDTH) * (i + 1) - 1]),
.din(comp_map_d[i]),
.dout(comp_map_l2[i])
);
end
end
endgenerate
generate
begin : xhdl4
genvar i;
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : spec_map0
tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(i)) spec_map_arc_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(spec_map_arc_act),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b),
.d_mode(d_mode),
.sg(pc_iu_sg_0),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scin(siv[spec_map_arc_offset + (STORAGE_WIDTH) * i:(spec_map_arc_offset + (STORAGE_WIDTH) * (i + 1)) - 1]),
.scout(sov[spec_map_arc_offset + (STORAGE_WIDTH) * i:(spec_map_arc_offset + (STORAGE_WIDTH) * (i + 1)) - 1]),
.din(spec_map_arc_d[i]),
.dout(spec_map_arc_l2[i])
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(i)) spec_map_itag_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(spec_map_itag_act),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b),
.d_mode(d_mode),
.sg(pc_iu_sg_0),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scin(siv[spec_map_itag_offset + (`ITAG_SIZE_ENC) * i:(spec_map_itag_offset + (`ITAG_SIZE_ENC) * (i + 1)) - 1]),
.scout(sov[spec_map_itag_offset + (`ITAG_SIZE_ENC) * i:(spec_map_itag_offset + (`ITAG_SIZE_ENC) * (i + 1)) - 1]),
.din(spec_map_itag_d[i]),
.dout(spec_map_itag_l2[i])
);
end
end
endgenerate
generate
begin : xhdl5
genvar i;
for (i = 0; i <= REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : buffer_pool_lat
tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT((i + ARCHITECTED_REGISTER_DEPTH))) buffer_pool_latch0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(buffer_pool_act[i]),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b),
.d_mode(d_mode),
.sg(pc_iu_sg_0),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scin(siv[buffer_pool_offset + (STORAGE_WIDTH) * i:(buffer_pool_offset + (STORAGE_WIDTH) * (i + 1)) - 1]),
.scout(sov[buffer_pool_offset + (STORAGE_WIDTH) * i:(buffer_pool_offset + (STORAGE_WIDTH) * (i + 1)) - 1]),
.din(buffer_pool_d[i]),
.dout(buffer_pool_l2[i])
);
end
end
endgenerate
tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) read_ptr_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(read_ptr_act),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b),
.d_mode(d_mode),
.sg(pc_iu_sg_0),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scin(siv[read_ptr_offset:read_ptr_offset + STORAGE_WIDTH - 1]),
.scout(sov[read_ptr_offset:read_ptr_offset + STORAGE_WIDTH - 1]),
.din(read_ptr_d),
.dout(read_ptr_l2)
);
tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) write_ptr_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(write_ptr_act),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b),
.d_mode(d_mode),
.sg(pc_iu_sg_0),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scin(siv[write_ptr_offset:write_ptr_offset + STORAGE_WIDTH - 1]),
.scout(sov[write_ptr_offset:write_ptr_offset + STORAGE_WIDTH - 1]),
.din(write_ptr_d),
.dout(write_ptr_l2)
);
tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH)) free_cnt_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(free_cnt_act),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b),
.d_mode(d_mode),
.sg(pc_iu_sg_0),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scin(siv[free_cnt_offset:free_cnt_offset + STORAGE_WIDTH - 1]),
.scout(sov[free_cnt_offset:free_cnt_offset + STORAGE_WIDTH - 1]),
.din(free_cnt_d),
.dout(free_cnt_l2)
);
tri_rlmlatch_p #(.INIT(0)) pool_free_0_v_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[pool_free_0_v_offset]),
.scout(sov[pool_free_0_v_offset]),
.din(pool_free_0_v_d),
.dout(pool_free_0_v_l2)
);
tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) pool_free_0_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b),
.d_mode(d_mode),
.sg(pc_iu_sg_0),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scin(siv[pool_free_0_offset:pool_free_0_offset + STORAGE_WIDTH - 1]),
.scout(sov[pool_free_0_offset:pool_free_0_offset + STORAGE_WIDTH - 1]),
.din(pool_free_0_d),
.dout(pool_free_0_l2)
);
tri_rlmlatch_p #(.INIT(0)) pool_free_1_v_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[pool_free_1_v_offset]),
.scout(sov[pool_free_1_v_offset]),
.din(pool_free_1_v_d),
.dout(pool_free_1_v_l2)
);
tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) pool_free_1_latch(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b),
.d_mode(d_mode),
.sg(pc_iu_sg_0),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scin(siv[pool_free_1_offset:pool_free_1_offset + STORAGE_WIDTH - 1]),
.scout(sov[pool_free_1_offset:pool_free_1_offset + STORAGE_WIDTH - 1]),
.din(pool_free_1_d),
.dout(pool_free_1_l2)
);
//---------------------------------------------------------------------
// Scan
//---------------------------------------------------------------------
assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
assign func_scan_out = sov[0];
endmodule |
module xu_gpr(
//-------------------------------------------------------------------
// Clocks & Power
//-------------------------------------------------------------------
input [0:`NCLK_WIDTH-1] nclk,
inout vdd,
inout gnd,
//-------------------------------------------------------------------
// Pervasive
//-------------------------------------------------------------------
input pc_xu_ccflush_dc,
input d_mode_dc,
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input sg_0,
input scan_in,
output scan_out,
//-------------------------------------------------------------------
// Read Ports
//-------------------------------------------------------------------
input r0e,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r0a,
output [64-`GPR_WIDTH:63] r0d,
input r1e,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a,
output [64-`GPR_WIDTH:63] r1d,
input r2e,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a,
output [64-`GPR_WIDTH:63] r2d,
input r3e,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r3a,
output [64-`GPR_WIDTH:63] r3d,
// Special Port for 3src instructions- erativax
input r4e,
input [0:2] r4t_q,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r4a,
output r0_pe,
output r1_pe,
output r2_pe,
output r3_pe,
//-------------------------------------------------------------------
// Write ports
//-------------------------------------------------------------------
input w0e,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w0a,
input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w0d,
input w1e,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w1a,
input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w1d,
input w2e,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w2a,
input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w2d,
input w3e,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w3a,
input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w3d
);
// Latches
wire r4e_q; // input=>r4e ,act=>1'b1
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r4a_q; // input=>r4a ,act=>1'b1
// Scanchain
localparam r4e_offset = 2;
localparam r4a_offset = r4e_offset + 1;
localparam scan_right = r4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
// Signals
wire [64-`GPR_WIDTH:77] w0d_int;
wire [64-`GPR_WIDTH:77] w1d_int;
wire [64-`GPR_WIDTH:77] w2d_int;
wire [64-`GPR_WIDTH:77] w3d_int;
wire [64-`GPR_WIDTH:77] r0d_int;
wire [64-`GPR_WIDTH:77] r1d_int;
wire [64-`GPR_WIDTH:77] r2d_int;
wire [64-`GPR_WIDTH:77] r3d_int;
wire [0:`GPR_WIDTH/8-1] r0d_par;
wire [0:`GPR_WIDTH/8-1] r1d_par;
wire [0:`GPR_WIDTH/8-1] r2d_par;
wire [0:`GPR_WIDTH/8-1] r3d_par;
wire r0e_int;
wire r4e_sel;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r0a_int;
assign r4e_sel = r4e_q & ~|r4t_q;
assign r0e_int = r4e_sel | r0e;
assign r0a_int = (r4e_sel == 1'b1) ? r4a_q : r0a;
assign r0d = r0d_int[64 - `GPR_WIDTH:63];
assign r1d = r1d_int[64 - `GPR_WIDTH:63];
assign r2d = r2d_int[64 - `GPR_WIDTH:63];
assign r3d = r3d_int[64 - `GPR_WIDTH:63];
assign w0d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w0d;
assign w0d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}};
assign w1d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w1d;
assign w1d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}};
assign w2d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w2d;
assign w2d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}};
assign w3d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w3d;
assign w3d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}};
generate
genvar i;
for (i = 0; i <= `GPR_WIDTH/8 - 1; i = i + 1)
begin : parity
assign r0d_par[i] = ^(r0d_int[8 * i:8 * i + 7]);
assign r1d_par[i] = ^(r1d_int[8 * i:8 * i + 7]);
assign r2d_par[i] = ^(r2d_int[8 * i:8 * i + 7]);
assign r3d_par[i] = ^(r3d_int[8 * i:8 * i + 7]);
end
endgenerate
assign r0_pe = r0e & (r0d_par != r0d_int[64:63 + `GPR_WIDTH/8]);
assign r1_pe = r1e & (r1d_par != r1d_int[64:63 + `GPR_WIDTH/8]);
assign r2_pe = r2e & (r2d_par != r2d_int[64:63 + `GPR_WIDTH/8]);
assign r3_pe = r3e & (r3d_par != r3d_int[64:63 + `GPR_WIDTH/8]);
tri_144x78_2r4w gpr0(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.func_slp_sl_force(func_sl_force),
.func_slp_sl_thold_0_b(func_sl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[0]),
.scan_out(sov[0]),
.r_late_en_1(r0e_int),
.r_addr_in_1(r0a_int),
.r_data_out_1(r0d_int),
.r_late_en_2(r1e),
.r_addr_in_2(r1a),
.r_data_out_2(r1d_int),
.w_late_en_1(w0e),
.w_addr_in_1(w0a),
.w_data_in_1(w0d_int),
.w_late_en_2(w1e),
.w_addr_in_2(w1a),
.w_data_in_2(w1d_int),
.w_late_en_3(w2e),
.w_addr_in_3(w2a),
.w_data_in_3(w2d_int),
.w_late_en_4(w3e),
.w_addr_in_4(w3a),
.w_data_in_4(w3d_int)
);
tri_144x78_2r4w gpr1(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b),
.func_sl_force(func_sl_force),
.func_sl_thold_0_b(func_sl_thold_0_b),
.func_slp_sl_force(func_sl_force),
.func_slp_sl_thold_0_b(func_sl_thold_0_b),
.sg_0(sg_0),
.scan_in(siv[1]),
.scan_out(sov[1]),
.r_late_en_1(r2e),
.r_addr_in_1(r2a),
.r_data_out_1(r2d_int),
.r_late_en_2(r3e),
.r_addr_in_2(r3a),
.r_data_out_2(r3d_int),
.w_late_en_1(w0e),
.w_addr_in_1(w0a),
.w_data_in_1(w0d_int),
.w_late_en_2(w1e),
.w_addr_in_2(w1a),
.w_data_in_2(w1d_int),
.w_late_en_3(w2e),
.w_addr_in_3(w2a),
.w_data_in_3(w2d_int),
.w_late_en_4(w3e),
.w_addr_in_4(w3a),
.w_data_in_4(w3d_int)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r4e_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(1'b1),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[r4e_offset]),
.scout(sov[r4e_offset]),
.din(r4e),
.dout(r4e_q)
);
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r4a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(1'b1),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[r4a_offset:r4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[r4a_offset:r4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(r4a),
.dout(r4a_q)
);
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
endmodule |
module iuq_cpl_ctrl_inc(
inc,
i,
o
);
`include "tri_a2o.vh"
parameter SIZE = 7;
parameter WRAP = 40;
input [0:1] inc;
input [0:SIZE-1] i;
output [0:SIZE-1] o;
wire [1:SIZE] a;
wire [1:SIZE] b;
wire [1:SIZE] rslt;
wire rollover;
wire rollover_m1;
wire inc_1;
wire inc_2;
wire [0:1] wrap_sel;
// Increment by 1 or 2.
// Go back to zero at WRAP
// Flip bit zero when a rollover occurs
// eg 0...39, 64..103
assign a = {i[1:SIZE - 1], inc[1]};
assign b = {1'b0, inc[0], inc[1]};
assign rslt = a + b;
assign rollover = i[1:SIZE - 1] == WRAP;
assign rollover_m1 = i[1:SIZE - 1] == WRAP - 1;
assign inc_1 = inc[0] ^ inc[1];
assign inc_2 = inc[0] & inc[1];
assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2);
assign wrap_sel[1] = rollover & inc_2;
assign o[0] = i[0] ^ |(wrap_sel);
assign o[1:SIZE - 1] = (wrap_sel[0:1] == 2'b10) ? 0 :
(wrap_sel[0:1] == 2'b01) ? 1 :
rslt[1:SIZE - 1];
endmodule |
module mmq_tlb_matchline(
inout vdd,
inout gnd,
input [0:51] addr_in,
input [0:8] addr_enable,
input [0:3] comp_pgsize,
input pgsize_enable,
input [0:3] entry_size,
input [0:`TLB_CMPMASK_WIDTH-1] entry_cmpmask,
input entry_xbit,
input [0:`TLB_CMPMASK_WIDTH-1] entry_xbitmask,
input [0:51] entry_epn,
input [0:1] comp_class,
input [0:1] entry_class,
input class_enable,
input [0:1] comp_extclass,
input [0:1] entry_extclass,
input [0:1] extclass_enable,
input [0:1] comp_state,
input entry_gs,
input entry_ts,
input [0:1] state_enable,
input [0:3] entry_thdid,
input [0:3] comp_thdid,
input thdid_enable,
input [0:13] entry_pid,
input [0:13] comp_pid,
input pid_enable,
input [0:7] entry_lpid,
input [0:7] comp_lpid,
input lpid_enable,
input entry_ind,
input comp_ind,
input ind_enable,
input entry_iprot,
input comp_iprot,
input iprot_enable,
input entry_v,
input comp_invalidate,
output match,
output dbg_addr_match,
output dbg_pgsize_match,
output dbg_class_match,
output dbg_extclass_match,
output dbg_state_match,
output dbg_thdid_match,
output dbg_pid_match,
output dbg_lpid_match,
output dbg_ind_match,
output dbg_iprot_match
);
parameter HAVE_XBIT = 1;
parameter NUM_PGSIZES = 5;
parameter HAVE_CMPMASK = 1;
//----------------------------------------------------------------------
// Components
//----------------------------------------------------------------------
//----------------------------------------------------------------------
// Signals
//----------------------------------------------------------------------
wire [30:51] entry_epn_b;
wire function_50_51;
wire function_48_51;
wire function_46_51;
wire function_44_51;
wire function_40_51;
wire function_36_51;
wire function_34_51;
wire pgsize_gte_16K;
wire pgsize_gte_64K;
wire pgsize_gte_256K;
wire pgsize_gte_1M;
wire pgsize_gte_16M;
wire pgsize_gte_256M;
wire pgsize_gte_1G;
wire pgsize_eq_16K;
wire pgsize_eq_64K;
wire pgsize_eq_256K;
wire pgsize_eq_1M;
wire pgsize_eq_16M;
wire pgsize_eq_256M;
wire pgsize_eq_1G;
wire comp_or_34_35;
wire comp_or_36_39;
wire comp_or_40_43;
wire comp_or_44_45;
wire comp_or_44_47;
wire comp_or_46_47;
wire comp_or_48_49;
wire comp_or_48_51;
wire comp_or_50_51;
wire [0:85] match_line;
wire pgsize_match;
wire addr_match;
wire class_match;
wire extclass_match;
wire state_match;
wire thdid_match;
wire pid_match;
wire lpid_match;
wire ind_match;
wire iprot_match;
wire addr_match_xbit_contrib;
wire addr_match_lsb_contrib;
wire addr_match_msb_contrib;
(* analysis_not_referenced="true" *)
wire [0:6] unused_dc;
assign match_line[0:85] = ( ~(({entry_epn[0:51], entry_size[0:3], entry_class[0:1], entry_extclass[0:1], entry_gs, entry_ts, entry_pid[0:13],
entry_lpid[0:7], entry_ind, entry_iprot}) ^ ({addr_in[0:51], comp_pgsize[0:3], comp_class[0:1],
comp_extclass[0:1], comp_state[0:1], comp_pid[0:13], comp_lpid[0:7], comp_ind, comp_iprot})) );
generate
if (NUM_PGSIZES == 8)
begin : numpgsz8
assign entry_epn_b[30:51] = (~(entry_epn[30:51]));
assign unused_dc[0:4] = {5{1'b0}};
assign unused_dc[5] = vdd;
assign unused_dc[6] = gnd;
if (HAVE_CMPMASK == 0)
begin : gen_nocmpmask80
assign pgsize_gte_1G = (entry_size[0] & (~(entry_size[1])) & entry_size[2] & (~(entry_size[3])));
assign pgsize_gte_256M = (entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])) & entry_size[3]) | pgsize_gte_1G;
assign pgsize_gte_16M = ((~(entry_size[0])) & entry_size[1] & entry_size[2] & entry_size[3]) | pgsize_gte_256M;
assign pgsize_gte_1M = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])) & entry_size[3]) | pgsize_gte_16M;
assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])) & (~(entry_size[3]))) | pgsize_gte_1M;
assign pgsize_gte_64K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2] & entry_size[3]) | pgsize_gte_256K;
assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2] & (~(entry_size[3]))) | pgsize_gte_64K;
end
// size entry_cmpmask: 0123456
// 1GB 1111111
// 256MB 0111111
// 16MB 0011111
// 1MB 0001111
// 256KB 0000111
// 64KB 0000011
// 16KB 0000001
// 4KB 0000000
if (HAVE_CMPMASK == 1)
begin : gen_cmpmask80
assign pgsize_gte_1G = entry_cmpmask[0];
assign pgsize_gte_256M = entry_cmpmask[1];
assign pgsize_gte_16M = entry_cmpmask[2];
assign pgsize_gte_1M = entry_cmpmask[3];
assign pgsize_gte_256K = entry_cmpmask[4];
assign pgsize_gte_64K = entry_cmpmask[5];
assign pgsize_gte_16K = entry_cmpmask[6];
// size entry_xbitmask: 0123456
// 1GB 1000000
// 256MB 0100000
// 16MB 0010000
// 1MB 0001000
// 256KB 0000100
// 64KB 0000010
// 16KB 0000001
// 4KB 0000000
assign pgsize_eq_1G = entry_xbitmask[0];
assign pgsize_eq_256M = entry_xbitmask[1];
assign pgsize_eq_16M = entry_xbitmask[2];
assign pgsize_eq_1M = entry_xbitmask[3];
assign pgsize_eq_256K = entry_xbitmask[4];
assign pgsize_eq_64K = entry_xbitmask[5];
assign pgsize_eq_16K = entry_xbitmask[6];
end
//function_30_51 <= '0';
if (HAVE_XBIT == 0)
begin : gen_noxbit80
assign function_34_51 = 1'b0;
assign function_36_51 = 1'b0;
assign function_40_51 = 1'b0;
assign function_44_51 = 1'b0;
assign function_46_51 = 1'b0;
assign function_48_51 = 1'b0;
assign function_50_51 = 1'b0;
end
// 1G
if (HAVE_XBIT != 0)
begin : gen_xbit80
assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | |(entry_epn_b[34:51] & addr_in[34:51]);
assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | |(entry_epn_b[36:51] & addr_in[36:51]);
assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | |(entry_epn_b[40:51] & addr_in[40:51]);
assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | |(entry_epn_b[44:51] & addr_in[44:51]);
assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | |(entry_epn_b[46:51] & addr_in[46:51]);
assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | |(entry_epn_b[48:51] & addr_in[48:51]);
assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | |(entry_epn_b[50:51] & addr_in[50:51]);
end
assign comp_or_50_51 = &(match_line[50:51]) | pgsize_gte_16K;
assign comp_or_48_49 = &(match_line[48:49]) | pgsize_gte_64K;
assign comp_or_46_47 = &(match_line[46:47]) | pgsize_gte_256K;
assign comp_or_44_45 = &(match_line[44:45]) | pgsize_gte_1M;
assign comp_or_40_43 = &(match_line[40:43]) | pgsize_gte_16M;
assign comp_or_36_39 = &(match_line[36:39]) | pgsize_gte_256M;
assign comp_or_34_35 = &(match_line[34:35]) | pgsize_gte_1G;
if (HAVE_XBIT == 0) // Ignore functions based on page size
begin : gen_noxbit81
assign addr_match = ( comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
(&(match_line[0:12]) | (~(addr_enable[0]))) &
(&(match_line[13:14]) | (~(addr_enable[1]))) &
(&(match_line[15:16]) | (~(addr_enable[2]))) &
(&(match_line[17:18]) | (~(addr_enable[3]))) &
(&(match_line[19:22]) | (~(addr_enable[4]))) &
(&(match_line[23:26]) | (~(addr_enable[5]))) &
(&(match_line[27:30]) | (~(addr_enable[6]))) &
(&(match_line[31:33]) | (~(addr_enable[7]))) ) // Regular compare largest page size
| (~(addr_enable[8])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
assign addr_match_xbit_contrib = 1'b0;
assign addr_match_lsb_contrib = (comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
comp_or_50_51); // Ignore functions based on page size
assign addr_match_msb_contrib = (&(match_line[0:12]) | (~(addr_enable[0]))) &
(&(match_line[13:14]) | (~(addr_enable[1]))) &
(&(match_line[15:16]) | (~(addr_enable[2]))) &
(&(match_line[17:18]) | (~(addr_enable[3]))) &
(&(match_line[19:22]) | (~(addr_enable[4]))) &
(&(match_line[23:26]) | (~(addr_enable[5]))) &
(&(match_line[27:30]) | (~(addr_enable[6]))) &
(&(match_line[31:33]) | (~(addr_enable[7])));
end
if (HAVE_XBIT != 0) // Exclusion functions
begin : gen_xbit81
// Regular compare largest page size
assign addr_match = ( function_50_51 &
function_48_51 &
function_46_51 &
function_44_51 &
function_40_51 &
function_36_51 &
function_34_51 &
comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
comp_or_50_51 &
(&(match_line[0:12]) | (~(addr_enable[0]))) &
(&(match_line[13:14]) | (~(addr_enable[1]))) &
(&(match_line[15:16]) | (~(addr_enable[2]))) &
(&(match_line[17:18]) | (~(addr_enable[3]))) &
(&(match_line[19:22]) | (~(addr_enable[4]))) &
(&(match_line[23:26]) | (~(addr_enable[5]))) &
(&(match_line[27:30]) | (~(addr_enable[6]))) &
(&(match_line[31:33]) | (~(addr_enable[7]))) ) // Ignore functions based on page size
| (~(addr_enable[8])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
assign addr_match_xbit_contrib = (function_50_51 &
function_48_51 &
function_46_51 &
function_44_51 &
function_40_51 &
function_36_51 &
function_34_51); // Exclusion functions
assign addr_match_lsb_contrib = (comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
comp_or_50_51); // Ignore functions based on page size
assign addr_match_msb_contrib = (&(match_line[0:12]) | (~(addr_enable[0]))) &
(&(match_line[13:14]) | (~(addr_enable[1]))) &
(&(match_line[15:16]) | (~(addr_enable[2]))) &
(&(match_line[17:18]) | (~(addr_enable[3]))) &
(&(match_line[19:22]) | (~(addr_enable[4]))) &
(&(match_line[23:26]) | (~(addr_enable[5]))) &
(&(match_line[27:30]) | (~(addr_enable[6]))) &
(&(match_line[31:33]) | (~(addr_enable[7])));
end
end
endgenerate
// numpgsz8: NUM_PGSIZES = 8
// tie off unused signals
generate
if (NUM_PGSIZES == 5)
begin : numpgsz5
assign function_50_51 = 1'b0;
assign function_46_51 = 1'b0;
assign pgsize_gte_16K = 1'b0;
assign pgsize_gte_256K = 1'b0;
assign pgsize_eq_16K = 1'b0;
assign pgsize_eq_256K = 1'b0;
assign comp_or_44_45 = 1'b0;
assign comp_or_46_47 = 1'b0;
assign comp_or_48_49 = 1'b0;
assign comp_or_50_51 = 1'b0;
assign entry_epn_b[30:51] = (~(entry_epn[30:51]));
assign unused_dc[0] = (pgsize_gte_16K & pgsize_gte_256K & pgsize_eq_16K & pgsize_eq_256K);
assign unused_dc[1] = (function_50_51 & function_46_51);
assign unused_dc[2] = (comp_or_44_45 & comp_or_46_47 & comp_or_48_49 & comp_or_50_51);
assign unused_dc[3] = |(entry_epn_b[30:33]);
assign unused_dc[4] = addr_match_xbit_contrib & addr_match_lsb_contrib & addr_match_msb_contrib;
assign unused_dc[5] = vdd;
assign unused_dc[6] = gnd;
// 1010
if (HAVE_CMPMASK == 0)
begin : gen_nocmpmask50
assign pgsize_gte_1G = (entry_size[0] & (~(entry_size[1])) & entry_size[2] & (~(entry_size[3])));
// 1001, large indirect entry size
assign pgsize_gte_256M = (entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])) & entry_size[3]) | pgsize_gte_1G;
// 0111
assign pgsize_gte_16M = ((~(entry_size[0])) & entry_size[1] & entry_size[2] & entry_size[3]) | pgsize_gte_256M;
// 0101
assign pgsize_gte_1M = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])) & entry_size[3]) | pgsize_gte_16M;
// 0011
assign pgsize_gte_64K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2] & entry_size[3]) | pgsize_gte_1M;
// 1010
assign pgsize_eq_1G = (entry_size[0] & (~(entry_size[1])) & entry_size[2] & (~(entry_size[3])));
// 1001, large indirect entry size
assign pgsize_eq_256M = (entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])) & entry_size[3]);
// 0111
assign pgsize_eq_16M = ((~(entry_size[0])) & entry_size[1] & entry_size[2] & entry_size[3]);
// 0101
assign pgsize_eq_1M = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])) & entry_size[3]);
// 0011
assign pgsize_eq_64K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2] & entry_size[3]);
end
// size entry_cmpmask: 01234
// 1GB 11111
// 256MB 01111
// 16MB 00111
// 1MB 00011
// 64KB 00001
// 4KB 00000
if (HAVE_CMPMASK == 1)
begin : gen_cmpmask50
assign pgsize_gte_1G = entry_cmpmask[0];
assign pgsize_gte_256M = entry_cmpmask[1];
assign pgsize_gte_16M = entry_cmpmask[2];
assign pgsize_gte_1M = entry_cmpmask[3];
assign pgsize_gte_64K = entry_cmpmask[4];
// size entry_xbitmask: 01234
// 1GB 10000
// 256MB 01000
// 16MB 00100
// 1MB 00010
// 64KB 00001
// 4KB 00000
assign pgsize_eq_1G = entry_xbitmask[0];
assign pgsize_eq_256M = entry_xbitmask[1];
assign pgsize_eq_16M = entry_xbitmask[2];
assign pgsize_eq_1M = entry_xbitmask[3];
assign pgsize_eq_64K = entry_xbitmask[4];
end
if (HAVE_XBIT == 0)
begin : gen_noxbit50
assign function_34_51 = 1'b0;
assign function_36_51 = 1'b0;
assign function_40_51 = 1'b0;
assign function_44_51 = 1'b0;
assign function_48_51 = 1'b0;
end
// 1G
if (HAVE_XBIT != 0)
begin : gen_xbit50
assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | |(entry_epn_b[34:51] & addr_in[34:51]);
// 256M
assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | |(entry_epn_b[36:51] & addr_in[36:51]);
// 16M
assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | |(entry_epn_b[40:51] & addr_in[40:51]);
// 1M
assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | |(entry_epn_b[44:51] & addr_in[44:51]);
// 64K
assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | |(entry_epn_b[48:51] & addr_in[48:51]);
end
assign comp_or_48_51 = &(match_line[48:51]) | pgsize_gte_64K;
assign comp_or_44_47 = &(match_line[44:47]) | pgsize_gte_1M;
assign comp_or_40_43 = &(match_line[40:43]) | pgsize_gte_16M;
assign comp_or_36_39 = &(match_line[36:39]) | pgsize_gte_256M;
assign comp_or_34_35 = &(match_line[34:35]) | pgsize_gte_1G; // glorp
if (HAVE_XBIT == 0) // Ignore functions based on page size
begin : gen_noxbit51
assign addr_match = (comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51 &
(&(match_line[0:12]) | (~(addr_enable[0]))) &
(&(match_line[13:14]) | (~(addr_enable[1]))) &
(&(match_line[15:16]) | (~(addr_enable[2]))) &
(&(match_line[17:18]) | (~(addr_enable[3]))) &
(&(match_line[19:22]) | (~(addr_enable[4]))) &
(&(match_line[23:26]) | (~(addr_enable[5]))) &
(&(match_line[27:30]) | (~(addr_enable[6]))) &
(&(match_line[31:33]) | (~(addr_enable[7])))) // Regular compare largest page size
| (~(addr_enable[8])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
assign addr_match_xbit_contrib = 1'b0;
assign addr_match_lsb_contrib = (comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51); // Ignore functions based on page size
assign addr_match_msb_contrib = (&(match_line[0:12]) | (~(addr_enable[0]))) &
(&(match_line[13:14]) | (~(addr_enable[1]))) &
(&(match_line[15:16]) | (~(addr_enable[2]))) &
(&(match_line[17:18]) | (~(addr_enable[3]))) &
(&(match_line[19:22]) | (~(addr_enable[4]))) &
(&(match_line[23:26]) | (~(addr_enable[5]))) &
(&(match_line[27:30]) | (~(addr_enable[6]))) &
(&(match_line[31:33]) | (~(addr_enable[7])));
end
if (HAVE_XBIT != 0)
begin : gen_xbit51
// Regular compare largest page size
assign addr_match = (function_48_51 &
function_44_51 &
function_40_51 &
function_36_51 &
function_34_51 &
comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51 &
(&(match_line[0:12]) | (~(addr_enable[0]))) &
(&(match_line[13:14]) | (~(addr_enable[1]))) &
(&(match_line[15:16]) | (~(addr_enable[2]))) &
(&(match_line[17:18]) | (~(addr_enable[3]))) &
(&(match_line[19:22]) | (~(addr_enable[4]))) &
(&(match_line[23:26]) | (~(addr_enable[5]))) &
(&(match_line[27:30]) | (~(addr_enable[6]))) &
(&(match_line[31:33]) | (~(addr_enable[7])))) // Ignore functions based on page size
| (~(addr_enable[8])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
assign addr_match_xbit_contrib = (function_48_51 &
function_44_51 &
function_40_51 &
function_36_51 &
function_34_51); // Exclusion functions
assign addr_match_lsb_contrib = (comp_or_34_35 &
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51); // Ignore functions based on page size
assign addr_match_msb_contrib = (&(match_line[0:12]) | (~(addr_enable[0]))) &
(&(match_line[13:14]) | (~(addr_enable[1]))) &
(&(match_line[15:16]) | (~(addr_enable[2]))) &
(&(match_line[17:18]) | (~(addr_enable[3]))) &
(&(match_line[19:22]) | (~(addr_enable[4]))) &
(&(match_line[23:26]) | (~(addr_enable[5]))) &
(&(match_line[27:30]) | (~(addr_enable[6]))) &
(&(match_line[31:33]) | (~(addr_enable[7])));
end
end
endgenerate
// numpgsz5: NUM_PGSIZES = 5
assign pgsize_match = &(match_line[52:55]) | (~(pgsize_enable));
assign class_match = &(match_line[56:57]) | (~(class_enable));
assign extclass_match = (match_line[58] | (~(extclass_enable[0]))) & (match_line[59] | (~(extclass_enable[1])));
assign state_match = (match_line[60] | (~(state_enable[0]))) & (match_line[61] | (~(state_enable[1])));
assign thdid_match = |(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable));
// entry_pid=0 ignores pid match for translation, not invalidation
assign pid_match = &(match_line[62:75]) | ((~(|(entry_pid[0:13]))) & (~comp_invalidate)) | (~(pid_enable));
// entry_lpid=0 ignores lpid match for translation, not invalidation
assign lpid_match = &(match_line[76:83]) | ((~(|(entry_lpid[0:7]))) & (~comp_invalidate)) | (~(lpid_enable));
assign ind_match = match_line[84] | (~(ind_enable));
assign iprot_match = match_line[85] | (~(iprot_enable));
// Address compare
// PgSize compare
// Class compare
// ExtClass compare
// State compare
// ThdID compare
// PID compare
// LPID compare
// indirect compare
// inval prot compare
// Valid
assign match = addr_match &
pgsize_match &
class_match &
extclass_match &
state_match &
thdid_match &
pid_match &
lpid_match &
ind_match &
iprot_match &
entry_v;
// debug outputs
assign dbg_addr_match = addr_match;
assign dbg_pgsize_match = pgsize_match;
assign dbg_class_match = class_match;
assign dbg_extclass_match = extclass_match;
assign dbg_state_match = state_match;
assign dbg_thdid_match = thdid_match;
assign dbg_pid_match = pid_match;
assign dbg_lpid_match = lpid_match;
assign dbg_ind_match = ind_match;
assign dbg_iprot_match = iprot_match;
endmodule |
module xu0_bcd_dtbcd(
input [0:9] a,
output [0:11] y
);
assign y[0] = ((~a[3]) & a[6] & a[7]) | (a[4] & a[6] & a[7] & a[3]) | (a[6] & a[7] & (~a[8]));
assign y[1] = (a[0] & a[3] & a[8] & (~a[4])) | (a[0] & (~a[7])) | (a[0] & (~a[6]));
assign y[2] = (a[1] & a[3] & a[8] & (~a[4])) | (a[1] & (~a[7])) | (a[1] & (~a[6]));
assign y[3] = a[2];
assign y[4] = (a[6] & (~a[7]) & a[8]) | (a[3] & a[6] & a[7] & a[8]) | ((~a[4]) & a[6] & a[8] & a[7]);
assign y[5] = (a[0] & a[4] & a[6] & a[7] & a[8] & (~a[3])) | (a[3] & (~a[8]) & a[6]) | (a[3] & (~a[6]));
assign y[6] = (a[1] & a[4] & a[7] & a[6] & a[8] & (~a[3])) | (a[4] & (~a[8]) & a[6]) | (a[4] & (~a[6]));
assign y[7] = a[5];
assign y[8] = (a[4] & a[6] & a[7] & a[8]) | (a[3] & a[6] & a[7] & a[8]) | (a[6] & (~a[7]) & (~a[8]));
assign y[9] = (a[0] & (~a[3]) & (~a[4]) & a[7] & a[6]) | (a[3] & a[6] & (~a[7]) & a[8]) | (a[0] & a[7] & (~a[8]) & a[6]) | (a[7] & (~a[6]));
assign y[10] = (a[1] & (~a[3]) & (~a[4]) & a[6] & a[7]) | (a[4] & a[6] & (~a[7]) & a[8]) | (a[1] & a[6] & a[7] & (~a[8])) | (a[8] & (~a[6]));
assign y[11] = a[9];
endmodule |
module rv_rpri(
cond,
pri
);
parameter size = 32;
input [0:size-1] cond;
output [0:size-1] pri;
parameter s = size - 1;
wire [0:s] or_l1;
wire [0:s] or_l2;
wire [0:s] or_l3;
wire [0:s] or_l4;
(* analysis_not_referenced="<0>true" *)
wire [0:s] or_l5;
// Odd Numbered Levels are inverted
assign or_l1[s] = (~cond[s]);
assign or_l1[0:s - 1] = ~(cond[0:s - 1] | cond[1:s]);
generate
if (s >= 2)
begin : or_l2_gen0
assign or_l2[s - 1:s] = (~or_l1[s - 1:s]);
assign or_l2[0:s - 2] = ~(or_l1[2:s] & or_l1[0:s - 2]);
end
endgenerate
generate
if (s < 2)
begin : or_l2_gen1
assign or_l2 = (~or_l1);
end
endgenerate
generate
if (s >= 4)
begin : or_l3_gen0
assign or_l3[s - 3:s] = (~or_l2[s - 3:s]);
assign or_l3[0:s - 4] = ~(or_l2[4:s] | or_l2[0:s - 4]);
end
endgenerate
generate
if (s < 4)
begin : or_l3_gen1
assign or_l3 = (~or_l2);
end
endgenerate
generate
if (s >= 8)
begin : or_l4_gen0
assign or_l4[s - 7:s] = (~or_l3[s - 7:s]);
assign or_l4[0:s - 8] = ~(or_l3[8:s] & or_l3[0:s - 8]);
end
endgenerate
generate
if (s < 8)
begin : or_l4_gen1
assign or_l4 = (~or_l3);
end
endgenerate
generate
if (s >= 16)
begin : or_l5_gen0
assign or_l5[s - 15:s] = (~or_l4[s - 15:s]);
assign or_l5[0:s - 16] = ~{or_l4[16:s] | or_l4[0:s - 16]};
end
endgenerate
generate
if (s < 16)
begin : or_l5_gen1
assign or_l5 = (~or_l4);
end
endgenerate
//assert size > 32 report "Maximum Size of 32 Exceeded!" severity error;
assign pri[s] = cond[s];
assign pri[0:s - 1] = cond[0:s - 1] & or_l5[1:s];
endmodule |
module lq_spr_dacen(
spr_msr_pr,
spr_msr_ds,
spr_dbcr0_dac,
spr_dbcr_dac_us,
spr_dbcr_dac_er,
val,
load,
store,
dacr_en,
dacw_en
);
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter `THREADS = 4;
input [0:`THREADS-1] spr_msr_pr;
input [0:`THREADS-1] spr_msr_ds;
input [0:2*`THREADS-1] spr_dbcr0_dac;
input [0:2*`THREADS-1] spr_dbcr_dac_us;
input [0:2*`THREADS-1] spr_dbcr_dac_er;
input [0:`THREADS-1] val;
input load;
input store;
output [0:`THREADS-1] dacr_en;
output [0:`THREADS-1] dacw_en;
// Signals
wire [0:1] spr_dbcr0_dac_tid[0:`THREADS-1];
wire [0:1] spr_dbcr_dac_us_tid[0:`THREADS-1];
wire [0:1] spr_dbcr_dac_er_tid[0:`THREADS-1];
wire [0:`THREADS-1] dac_ld_en;
wire [0:`THREADS-1] dac_st_en;
wire [0:`THREADS-1] dac_us_en;
wire [0:`THREADS-1] dac_er_en;
generate begin : sprTid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid
assign spr_dbcr0_dac_tid[tid] = spr_dbcr0_dac[tid*2:tid*2+1];
assign spr_dbcr_dac_us_tid[tid] = spr_dbcr_dac_us[tid*2:tid*2+1];
assign spr_dbcr_dac_er_tid[tid] = spr_dbcr_dac_er[tid*2:tid*2+1];
end
end
endgenerate
generate begin : dacen_gen
genvar t;
for (t = 0; t <= `THREADS - 1; t = t + 1) begin : dacen_gen
assign dac_ld_en[t] = spr_dbcr0_dac_tid[t][0] & load;
assign dac_st_en[t] = spr_dbcr0_dac_tid[t][1] & store;
assign dac_us_en[t] = ((~spr_dbcr_dac_us_tid[t][0]) & (~spr_dbcr_dac_us_tid[t][1])) | (spr_dbcr_dac_us_tid[t][0] & (spr_dbcr_dac_us_tid[t][1] ~^ spr_msr_pr[t]));
assign dac_er_en[t] = ((~spr_dbcr_dac_er_tid[t][0]) & (~spr_dbcr_dac_er_tid[t][1])) | (spr_dbcr_dac_er_tid[t][0] & (spr_dbcr_dac_er_tid[t][1] ~^ spr_msr_ds[t]));
assign dacr_en[t] = val[t] & dac_ld_en[t] & dac_us_en[t] & dac_er_en[t];
assign dacw_en[t] = val[t] & dac_st_en[t] & dac_us_en[t] & dac_er_en[t];
end
end
endgenerate
endmodule |
module rv_primux(
cond,
din,
dout
);
parameter q_num_entries_g = 16;
parameter q_dat_width_g = 7;
input [0:q_num_entries_g-1] cond;
input [0:q_dat_width_g*q_num_entries_g-1] din;
output [0:q_dat_width_g-1] dout;
wire [0:q_dat_width_g-1] q_dat_l1[0:7];
wire [0:q_dat_width_g-1] q_dat_l1a[0:7];
wire [0:q_dat_width_g-1] q_dat_l1b[0:7];
wire [0:q_dat_width_g-1] q_dat_l2[0:3];
wire [0:q_dat_width_g-1] q_dat_l2a[0:3];
wire [0:q_dat_width_g-1] q_dat_l2b[0:3];
wire [0:q_dat_width_g-1] q_dat_l4[0:1];
wire [0:q_dat_width_g-1] q_dat_l4a[0:1];
wire [0:q_dat_width_g-1] q_dat_l4b[0:1];
wire [0:q_dat_width_g-1] q_dat_l8a;
wire [0:q_dat_width_g-1] q_dat_l8b;
wire [0:q_dat_width_g-1] q_dat_l8;
wire [1:7] selval1_b;
wire [0:7] selpri1;
wire [0:7] selpri1_b;
wire [1:3] selval2;
wire [0:3] selpri2;
wire [0:3] selpri2_b;
wire [1:1] selval4_b;
wire [0:1] selpri4;
wire [0:1] selpri4_b;
wire selpri8;
wire selpri8_b;
(* analysis_not_referenced="true" *)
wire selpri1_unused;
(* analysis_not_referenced="true" *)
wire selpri1_b_unused;
(* analysis_not_referenced="true" *)
wire [0:q_dat_width_g-1] q_dat_l1_unused;
(* analysis_not_referenced="true" *)
wire cond_unused;
genvar n;
parameter aryoff = q_dat_width_g;
assign cond_unused = cond[0];
tri_nor2 selval1_b1(selval1_b[1], cond[2], cond[3]);
tri_nor2 selval1_b2(selval1_b[2], cond[4], cond[5]);
tri_nor2 selval1_b3(selval1_b[3], cond[6], cond[7]);
generate
if (q_num_entries_g == 8)
begin : selval1_gen08
assign selval1_b[4] = 1'b1;
assign selval1_b[5] = 1'b1;
assign selval1_b[6] = 1'b1;
assign selval1_b[7] = 1'b1;
end
endgenerate
generate
if (q_num_entries_g == 12)
begin : selval1_gen0
tri_nor2 selval1_b4(selval1_b[4], cond[8], cond[9]);
tri_nor2 selval1_b5(selval1_b[5], cond[10], cond[11]);
assign selval1_b[6] = 1'b1;
assign selval1_b[7] = 1'b1;
end
endgenerate
generate
if (q_num_entries_g == 16)
begin : selval1_gen1
tri_nor2 selval1_b4(selval1_b[4], cond[8], cond[9]);
tri_nor2 selval1_b5(selval1_b[5], cond[10], cond[11]);
tri_nor2 selval1_b6(selval1_b[6], cond[12], cond[13]);
tri_nor2 selval1_b7(selval1_b[7], cond[14], cond[15]);
end
endgenerate
tri_inv selpri1_b0( selpri1_b[0], cond[1]);
tri_inv selpri1_b1( selpri1_b[1], cond[3]);
tri_inv selpri1_b2( selpri1_b[2], cond[5]);
tri_inv selpri1_b3( selpri1_b[3], cond[7]);
generate
if (q_num_entries_g == 8)
begin : selpri1_gen08
assign selpri1_b[4] = 1'b1;
assign selpri1_b[5] = 1'b1;
assign selpri1_b[6] = 1'b1;
assign selpri1_b[7] = 1'b1;
assign selpri1_b_unused = selpri1_b[4] | selpri1_b[5] | selpri1_b[6] | selpri1_b[7] ;
end
endgenerate
generate
if (q_num_entries_g == 12)
begin : selpri1_gen0
tri_inv selpri1_b4( selpri1_b[4], cond[9]);
tri_inv selpri1_b5( selpri1_b[5], cond[11]);
assign selpri1_b[6] = 1'b1;
assign selpri1_b[7] = 1'b1;
assign selpri1_b_unused = selpri1_b[6] | selpri1_b[7] ;
end
endgenerate
generate
if (q_num_entries_g == 16)
begin : selpri1_gen1
tri_inv selpri1_b4( selpri1_b[4], cond[9]);
tri_inv selpri1_b5( selpri1_b[5], cond[11]);
tri_inv selpri1_b6( selpri1_b[6], cond[13]);
tri_inv selpri1_b7( selpri1_b[7], cond[15]);
assign selpri1_b_unused =1'b0;
end
endgenerate
tri_inv selpri1_0( selpri1[0], selpri1_b[0]);
tri_inv selpri1_1( selpri1[1], selpri1_b[1]);
tri_inv selpri1_2( selpri1[2], selpri1_b[2]);
tri_inv selpri1_3( selpri1[3], selpri1_b[3]);
generate
if (q_num_entries_g == 8)
begin : selpri1_gen0b8
assign selpri1[4] = 1'b0;
assign selpri1[5] = 1'b0;
assign selpri1[6] = 1'b0;
assign selpri1[7] = 1'b0;
assign selpri1_unused = selpri1[4] | selpri1[5] | selpri1[6] | selpri1[7] ;
end
endgenerate
generate
if (q_num_entries_g == 12)
begin : selpri1_gen0b
tri_inv selpri1_4( selpri1[4], selpri1_b[4]);
tri_inv selpri1_5( selpri1[5], selpri1_b[5]);
assign selpri1[6] = 1'b0;
assign selpri1[7] = 1'b0;
assign selpri1_unused = selpri1[6] | selpri1[7];
end
endgenerate
generate
if (q_num_entries_g == 16)
begin : selpri1_gen1b
tri_inv selpri1_4( selpri1[4], selpri1_b[4]);
tri_inv selpri1_5( selpri1[5], selpri1_b[5]);
tri_inv selpri1_6( selpri1[6], selpri1_b[6]);
tri_inv selpri1_7( selpri1[7], selpri1_b[7]);
assign selpri1_unused=1'b0;
end
endgenerate
tri_nand2 selval21(selval2[1], selval1_b[2], selval1_b[3]);
tri_nand2 selval22(selval2[2], selval1_b[4], selval1_b[5]);
tri_nand2 selval23(selval2[3], selval1_b[6], selval1_b[7]);
assign selpri2[0] = (~selval1_b[1]);
assign selpri2[1] = (~selval1_b[3]);
assign selpri2[2] = (~selval1_b[5]);
assign selpri2[3] = (~selval1_b[7]);
assign selpri2_b[0] = selval1_b[1];
assign selpri2_b[1] = selval1_b[3];
assign selpri2_b[2] = selval1_b[5];
assign selpri2_b[3] = selval1_b[7];
tri_nor2 selval4_b1(selval4_b[1], selval2[2], selval2[3]);
assign selpri4_b[0] = (~selval2[1]);
assign selpri4_b[1] = (~selval2[3]);
assign selpri4[0] = selval2[1];
assign selpri4[1] = selval2[3];
assign selpri8 = (~selval4_b[1]);
assign selpri8_b = selval4_b[1];
//-------------------------------------------------------------------------------------------------------
// Instruction Muxing
//-------------------------------------------------------------------------------------------------------
generate
begin : xhdl
for (n = 0; n <= (q_dat_width_g - 1); n = n + 1)
begin : gendat
// Level 1
// 01 23 45 67 89 1011 1213 1415
tri_nand2 q_dat_l1a0(q_dat_l1a[0][n], din[0*aryoff+n], selpri1_b[0]);
tri_nand2 q_dat_l1b0(q_dat_l1b[0][n], din[1*aryoff+n], selpri1[0]);
tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l10(q_dat_l1[0][n], q_dat_l1a[0][n], q_dat_l1b[0][n]);
tri_nand2 q_dat_l1a1(q_dat_l1a[1][n], din[2*aryoff+n], selpri1_b[1]);
tri_nand2 q_dat_l1b1(q_dat_l1b[1][n], din[3*aryoff+n], selpri1[1]);
tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l11(q_dat_l1[1][n], q_dat_l1a[1][n], q_dat_l1b[1][n]);
tri_nand2 q_dat_l1a2(q_dat_l1a[2][n], din[4*aryoff+n], selpri1_b[2]);
tri_nand2 q_dat_l1b2(q_dat_l1b[2][n], din[5*aryoff+n], selpri1[2]);
tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l12(q_dat_l1[2][n], q_dat_l1a[2][n], q_dat_l1b[2][n]);
tri_nand2 q_dat_l1a3(q_dat_l1a[3][n], din[6*aryoff+n], selpri1_b[3]);
tri_nand2 q_dat_l1b3(q_dat_l1b[3][n], din[7*aryoff+n], selpri1[3]);
tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l13(q_dat_l1[3][n], q_dat_l1a[3][n], q_dat_l1b[3][n]);
//generate
if (q_num_entries_g == 8)
begin : l1_gen8
assign q_dat_l1a[4][n] = 1'b0;
assign q_dat_l1b[4][n] = 1'b0;
assign q_dat_l1[4][n] = 1'b0;
assign q_dat_l1a[5][n] = 1'b0;
assign q_dat_l1b[5][n] = 1'b0;
assign q_dat_l1[5][n] = 1'b0;
assign q_dat_l1a[6][n] = 1'b0;
assign q_dat_l1b[6][n] = 1'b0;
assign q_dat_l1[6][n] = 1'b0;
assign q_dat_l1a[7][n] = 1'b0;
assign q_dat_l1b[7][n] = 1'b0;
assign q_dat_l1[7][n] = 1'b0;
assign q_dat_l1_unused[n] = (|q_dat_l1a[4][n]) | (|q_dat_l1a[5][n]) | (|q_dat_l1a[6][n]) | (|q_dat_l1a[7][n]) |
(|q_dat_l1b[4][n]) | (|q_dat_l1b[5][n]) | (|q_dat_l1b[6][n]) | (|q_dat_l1b[7][n]) |
(|q_dat_l1[4][n]) | (|q_dat_l1[5][n]) | (|q_dat_l1[6][n]) | (|q_dat_l1[7][n]) ;
end
//endgenerate
//generate
if (q_num_entries_g == 12)
begin : l1_gen12
tri_nand2 q_dat_l1a4(q_dat_l1a[4][n], din[8*aryoff+n], selpri1_b[4]);
tri_nand2 q_dat_l1b4(q_dat_l1b[4][n], din[9*aryoff+n], selpri1[4]);
tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l14(q_dat_l1[4][n], q_dat_l1a[4][n], q_dat_l1b[4][n]);
tri_nand2 q_dat_l1a5(q_dat_l1a[5][n], din[10*aryoff+n], selpri1_b[5]);
tri_nand2 q_dat_l1b5(q_dat_l1b[5][n], din[11*aryoff+n], selpri1[5]);
tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l15(q_dat_l1[5][n], q_dat_l1a[5][n], q_dat_l1b[5][n]);
assign q_dat_l1a[6][n] = 1'b0;
assign q_dat_l1b[6][n] = 1'b0;
assign q_dat_l1[6][n] = 1'b0;
assign q_dat_l1a[7][n] = 1'b0;
assign q_dat_l1b[7][n] = 1'b0;
assign q_dat_l1[7][n] = 1'b0;
assign q_dat_l1_unused[n] = (|q_dat_l1a[6][n]) | (|q_dat_l1a[7][n]) |
(|q_dat_l1b[6][n]) | (|q_dat_l1b[7][n]) |
(|q_dat_l1[6][n]) | (|q_dat_l1[7][n]) ;
end
//endgenerate
//generate
if (q_num_entries_g == 16)
begin : l1_gen16
tri_nand2 q_dat_l1a4(q_dat_l1a[4][n], din[8*aryoff+n], selpri1_b[4]);
tri_nand2 q_dat_l1b4(q_dat_l1b[4][n], din[9*aryoff+n], selpri1[4]);
tri_nand2 q_dat_l14(q_dat_l1[4][n], q_dat_l1a[4][n], q_dat_l1b[4][n]);
tri_nand2 q_dat_l1a5(q_dat_l1a[5][n], din[10*aryoff+n], selpri1_b[5]);
tri_nand2 q_dat_l1b5(q_dat_l1b[5][n], din[11*aryoff+n], selpri1[5]);
tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l15(q_dat_l1[5][n], q_dat_l1a[5][n], q_dat_l1b[5][n]);
tri_nand2 q_dat_l1a6(q_dat_l1a[6][n], din[12*aryoff+n], selpri1_b[6]);
tri_nand2 q_dat_l1b6(q_dat_l1b[6][n], din[13*aryoff+n], selpri1[6]);
tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l16(q_dat_l1[6][n], q_dat_l1a[6][n], q_dat_l1b[6][n]);
tri_nand2 q_dat_l1a7(q_dat_l1a[7][n], din[14*aryoff+n], selpri1_b[7]);
tri_nand2 q_dat_l1b7(q_dat_l1b[7][n], din[15*aryoff+n], selpri1[7]);
tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l17(q_dat_l1[7][n], q_dat_l1a[7][n], q_dat_l1b[7][n]);
assign q_dat_l1_unused[n]=1'b0;
end
//endgenerate
end
end
endgenerate
// Level 2
// 0123 4567 891011 12131415
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2a0(q_dat_l2a[0], q_dat_l1[0], {q_dat_width_g{selpri2_b[0]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2b0(q_dat_l2b[0], q_dat_l1[1], {q_dat_width_g{selpri2[0]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l20(q_dat_l2[0], q_dat_l2a[0], q_dat_l2b[0]);
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2a1(q_dat_l2a[1], q_dat_l1[2], {q_dat_width_g{selpri2_b[1]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2b1(q_dat_l2b[1], q_dat_l1[3], {q_dat_width_g{selpri2[1]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l21(q_dat_l2[1], q_dat_l2a[1], q_dat_l2b[1]);
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2a2(q_dat_l2a[2], q_dat_l1[4], {q_dat_width_g{selpri2_b[2]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2b2(q_dat_l2b[2], q_dat_l1[5], {q_dat_width_g{selpri2[2]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l22(q_dat_l2[2], q_dat_l2a[2], q_dat_l2b[2]);
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2a3(q_dat_l2a[3], q_dat_l1[6], {q_dat_width_g{selpri2_b[3]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2b3(q_dat_l2b[3], q_dat_l1[7], {q_dat_width_g{selpri2[3]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l23(q_dat_l2[3], q_dat_l2a[3], q_dat_l2b[3]);
// Level 4
// 01234567 89101112131415
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l4a0(q_dat_l4a[0], q_dat_l2[0], {q_dat_width_g{selpri4_b[0]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l4b0(q_dat_l4b[0], q_dat_l2[1], {q_dat_width_g{selpri4[0]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X4M_A9TH")) q_dat_l40(q_dat_l4[0], q_dat_l4a[0], q_dat_l4b[0]);
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l4a1(q_dat_l4a[1], q_dat_l2[2], {q_dat_width_g{selpri4_b[1]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l4b1(q_dat_l4b[1], q_dat_l2[3], {q_dat_width_g{selpri4[1]}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X4M_A9TH")) q_dat_l41(q_dat_l4[1], q_dat_l4a[1], q_dat_l4b[1]);
// Level 8
// 0123456789101112131415
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X6M_A9TH")) q_dat_l8a0(q_dat_l8a, q_dat_l4[0], {q_dat_width_g{selpri8_b}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X6M_A9TH")) q_dat_l8b0(q_dat_l8b, q_dat_l4[1], {q_dat_width_g{selpri8}});
tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X8M_A9TH")) q_dat_180( q_dat_l8, q_dat_l8a, q_dat_l8b);
assign dout = q_dat_l8;
endmodule // rv_primux |
module pcq_ctrl(
// Include model build parameters
`include "tri_a2o.vh"
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input scan_dis_dc_b,
input lcb_clkoff_dc_b,
input lcb_mpw1_dc_b,
input lcb_mpw2_dc_b,
input lcb_delay_lclkr_dc,
input lcb_act_dis_dc,
input pc_pc_func_slp_sl_thold_0,
input pc_pc_sg_0,
input func_scan_in,
output func_scan_out,
// Reset Related
output pc_lq_init_reset,
output pc_iu_init_reset,
output ct_rg_hold_during_init,
// Power Management
output [0:`THREADS-1] ct_rg_power_managed,
output ac_an_power_managed,
output ac_an_rvwinkle_mode,
output pc_xu_pm_hold_thread,
output ct_ck_pm_ccflush_disable,
output ct_ck_pm_raise_tholds,
input rg_ct_dis_pwr_savings,
input [0:1] xu_pc_spr_ccr0_pme,
input [0:`THREADS-1] xu_pc_spr_ccr0_we,
// Trace/Trigger Signals
output [0:14] dbg_ctrls
);
//=====================================================================
// Signal Declarations
//=====================================================================
parameter INITACTIVE_SIZE = 1;
parameter HOLDCNTR_SIZE = 3;
parameter INITCNTR_SIZE = 9;
parameter INITERAT_SIZE = 1;
parameter PMCTRLS_T0_SIZE = 15;
parameter PMCTRLS_T1_SIZE = 2 * (`THREADS - 1);
parameter SPARECTRL_SIZE = 6;
//---------------------------------------------------------------------
// Scan Ring Ordering:
// start of func scan chain ordering
parameter INITACTIVE_OFFSET = 0;
parameter HOLDCNTR_OFFSET = INITACTIVE_OFFSET + INITACTIVE_SIZE;
parameter INITCNTR_OFFSET = HOLDCNTR_OFFSET + HOLDCNTR_SIZE;
parameter INITERAT_OFFSET = INITCNTR_OFFSET + INITCNTR_SIZE;
parameter PMCTRLS_T0_OFFSET = INITERAT_OFFSET + INITERAT_SIZE;
parameter PMCTRLS_T1_OFFSET = PMCTRLS_T0_OFFSET + PMCTRLS_T0_SIZE;
parameter SPARECTRL_OFFSET = PMCTRLS_T1_OFFSET + PMCTRLS_T1_SIZE;
parameter FUNC_RIGHT = SPARECTRL_OFFSET + SPARECTRL_SIZE - 1;
// end of func scan chain ordering
//---------------------------------------------------------------------
// Array Initialization Controls:
parameter HOLDCNT_IDLE = 0;
parameter HOLDCNT_DONE = 7;
parameter INITCNT_START = 15+(`INIT_BHT*496); // sets INITCNTR to 15 or 511
parameter INITCNT_DONE = 0;
//---------------------------------------------------------------------
// Basic/Misc signals
wire tiup;
wire [0:FUNC_RIGHT] func_siv;
wire [0:FUNC_RIGHT] func_sov;
wire pc_pc_func_slp_sl_thold_0_b;
wire force_funcslp;
// Reset Signals
wire initcntr_enabled;
// Power management Signals
wire [0:1] spr_ccr0_pme_q;
wire [0:`THREADS-1] spr_ccr0_we_q;
wire pm_sleep_enable;
wire pm_rvw_enable;
wire [0:`THREADS-1] thread_stopped;
wire pmstate_q_anded;
// Latch definitions begin
wire [0:HOLDCNTR_SIZE-1] holdcntr_d;
wire [0:HOLDCNTR_SIZE-1] holdcntr_q;
wire [0:INITCNTR_SIZE-1] initcntr_d;
wire [0:INITCNTR_SIZE-1] initcntr_q;
wire init_active_d;
wire init_active_q;
wire initerat_d;
wire initerat_q;
wire pmstate_enab;
wire [0:`THREADS-1] pmstate_d;
wire [0:`THREADS-1] pmstate_q;
wire pmstate_all_d;
wire pmstate_all_q;
wire [0:7] pmclkctrl_dly_d;
wire [0:7] pmclkctrl_dly_q;
wire power_managed_d;
wire power_managed_q;
wire rvwinkled_d;
wire rvwinkled_q;
wire pm_ccflush_disable_int;
wire pm_raise_tholds_int;
wire [0:SPARECTRL_SIZE-1] spare_ctrl_wrapped_q;
//!! Bugspray Include: pcq_ctrl;
assign tiup = 1'b1;
//=====================================================================
// Reset State Machine
//=====================================================================
// HOLDCNTR: Delays start of array initialization for 7 cycles. Provides some time
// after clock start to ensure clock controls have propagated to LCBs. .
assign holdcntr_d = init_active_q == 1'b0 ? HOLDCNT_IDLE :
holdcntr_q == HOLDCNT_DONE ? HOLDCNT_DONE :
holdcntr_q + 3'b001;
// Latch ACT control: Goes inactive once array initialization is over.
assign initcntr_enabled = init_active_q | (|holdcntr_q);
// INITCNTR: Initialized to a value; counts down while array init signal held active.
// Default time is 16 cycles, which is long enough for the ERATs to initialize.
// To initialize the BHT, the array init signal is kept active for 512 cycles.
// Controlled by `INIT_BHT (0=16 cycles; 1=512 cycles)
assign initcntr_d = holdcntr_q != HOLDCNT_DONE ? initcntr_q :
initcntr_q == INITCNT_DONE ? INITCNT_DONE :
initcntr_q - 9'b000000001;
// INITERAT: The initerat latch controls the init_reset signals to IU and XU.
// Goes active when HOLDCNTR=7, and shuts off when INITCNTR counts down to 0.
assign initerat_d = ( holdcntr_q < HOLDCNT_DONE-1) ? 1'b0 :
(|initcntr_q);
// INIT_ACTIVE: init_active_q initializes to '1'; cleared after INITCNTR counts down to 0.
assign init_active_d = (initcntr_q == INITCNT_DONE) ? 1'b0 :
init_active_q;
//=====================================================================
// Power Management Latches
//=====================================================================
// XU signals indicate when power-savings is enabled (sleep or rvw modes), and which
// THREADS are stopped.
// The pmstate latch tracks which THREADS are stopped when either power-savings mode
// is enabled. The rvwinkled latch only when pm_rvw_enable is set.
// If all THREADS are stopped when power-savings is enabled, then signals to the
// clock control macro will initiate power savings actions. These controls force
// ccflush_dc inactive to ensure all PLATs are clocking. After a delay period, the
// run tholds will be raised to stop clocks.
// When coming out of power-savings, the tholds will be disabled prior to deactivating
// ccflush_dc.
assign pm_sleep_enable = (~spr_ccr0_pme_q[0]) & spr_ccr0_pme_q[1];
assign pm_rvw_enable = spr_ccr0_pme_q[0] & (~spr_ccr0_pme_q[1]);
assign thread_stopped = spr_ccr0_we_q;
assign pmstate_enab = (pm_sleep_enable | pm_rvw_enable) & (~initcntr_enabled);
assign pmstate_d = {`THREADS{pmstate_enab}} & thread_stopped[0:`THREADS - 1];
// Once all CCR0[WE] bits are set, pmstate_all_q is held active until pmclkctrl_dly_q(7).
// Forces an orderly sequence through PM controls, even if one thread wakes-up right away.
assign pmstate_q_anded = (&pmstate_q);
assign pmstate_all_d = ((~pmclkctrl_dly_q[7]) & (pmstate_q_anded | pmstate_all_q)) |
(pmstate_q_anded & pmstate_all_q);
assign power_managed_d = pmstate_all_d | pmclkctrl_dly_q[6];
assign rvwinkled_d = (pmstate_all_d | pmclkctrl_dly_q[6]) & pm_rvw_enable;
assign pmclkctrl_dly_d[0:7] = {pmstate_all_q, pmclkctrl_dly_q[0:6]};
//=====================================================================
// Outputs
//=====================================================================
// Used as part of thread stop signal to XU.
// Keeps THREADS stopped until after the Reset SM completes count.
assign ct_rg_hold_during_init = init_active_q;
// Init pulse to IU and XU to force initialization of IERAT, DERAT and BHT.
// IU also holds instruction fetch until init signal released.
assign pc_iu_init_reset = initerat_q;
assign pc_lq_init_reset = initerat_q;
// To THRCTL[Tx_PM]; indicates core power-managed via software actions.
assign ct_rg_power_managed = pmstate_q[0:`THREADS - 1];
// Core in rvwinkle power-savings state. L2 can prepare for Chiplet power-down.
assign ac_an_rvwinkle_mode = rvwinkled_q;
// Core in power-savings state due to any combination of power-savings instructions
assign ac_an_power_managed = power_managed_q;
assign pc_xu_pm_hold_thread = power_managed_q;
// Goes to clock controls to disable plat flush controls
assign pm_ccflush_disable_int = pmstate_all_q | pmclkctrl_dly_q[7];
assign ct_ck_pm_ccflush_disable = pm_ccflush_disable_int & (~rg_ct_dis_pwr_savings);
// Goes to clock controls to activate run tholds
assign pm_raise_tholds_int = pmstate_all_q & pmclkctrl_dly_q[7];
assign ct_ck_pm_raise_tholds = pm_raise_tholds_int & (~rg_ct_dis_pwr_savings);
//=====================================================================
// Trace/Trigger Signals
//=====================================================================
assign dbg_ctrls = { pmstate_q_anded, // 0
pmstate_all_q, // 1
power_managed_q, // 2
rvwinkled_q, // 3
pmclkctrl_dly_q[0:7], // 4:11
rg_ct_dis_pwr_savings, // 12
pm_ccflush_disable_int, // 13
pm_raise_tholds_int // 14
};
//=====================================================================
// Latches
//=====================================================================
// func ring registers start
tri_rlmlatch_p #(.INIT(1)) initactive(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_funcslp),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[ INITACTIVE_OFFSET]),
.scout(func_sov[INITACTIVE_OFFSET]),
.din(init_active_d),
.dout(init_active_q)
);
tri_rlmreg_p #(.WIDTH(HOLDCNTR_SIZE), .INIT(0)) holdcntr(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(initcntr_enabled),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_funcslp),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[ HOLDCNTR_OFFSET:HOLDCNTR_OFFSET + HOLDCNTR_SIZE - 1]),
.scout(func_sov[HOLDCNTR_OFFSET:HOLDCNTR_OFFSET + HOLDCNTR_SIZE - 1]),
.din(holdcntr_d),
.dout(holdcntr_q)
);
tri_rlmreg_p #(.WIDTH(INITCNTR_SIZE), .INIT(INITCNT_START)) initcntr(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(initcntr_enabled),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_funcslp),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[ INITCNTR_OFFSET:INITCNTR_OFFSET + INITCNTR_SIZE - 1]),
.scout(func_sov[INITCNTR_OFFSET:INITCNTR_OFFSET + INITCNTR_SIZE - 1]),
.din(initcntr_d),
.dout(initcntr_q)
);
tri_rlmlatch_p #(.INIT(0)) initerat(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(initcntr_enabled),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_funcslp),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[ INITERAT_OFFSET]),
.scout(func_sov[INITERAT_OFFSET]),
.din(initerat_d),
.dout(initerat_q)
);
tri_rlmreg_p #(.WIDTH(PMCTRLS_T0_SIZE), .INIT(0)) pmctrls_t0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_funcslp),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[ PMCTRLS_T0_OFFSET:PMCTRLS_T0_OFFSET + PMCTRLS_T0_SIZE - 1]),
.scout(func_sov[PMCTRLS_T0_OFFSET:PMCTRLS_T0_OFFSET + PMCTRLS_T0_SIZE - 1]),
.din( {pmclkctrl_dly_d, xu_pc_spr_ccr0_pme, xu_pc_spr_ccr0_we[0], pmstate_d[0],
pmstate_all_d, rvwinkled_d, power_managed_d}),
.dout({pmclkctrl_dly_q, spr_ccr0_pme_q, spr_ccr0_we_q[0], pmstate_q[0],
pmstate_all_q, rvwinkled_q, power_managed_q})
);
generate
if (`THREADS > 1)
begin : T1_pmctrls
tri_rlmreg_p #(.WIDTH(PMCTRLS_T1_SIZE), .INIT(0)) pmctrls_t1(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_funcslp),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[ PMCTRLS_T1_OFFSET:PMCTRLS_T1_OFFSET + PMCTRLS_T1_SIZE - 1]),
.scout(func_sov[PMCTRLS_T1_OFFSET:PMCTRLS_T1_OFFSET + PMCTRLS_T1_SIZE - 1]),
.din({xu_pc_spr_ccr0_we[1], pmstate_d[1]}),
.dout({spr_ccr0_we_q[1], pmstate_q[1]})
);
end
endgenerate
tri_rlmreg_p #(.WIDTH(SPARECTRL_SIZE), .INIT(0)) sparectrl(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_pc_func_slp_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_funcslp),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[ SPARECTRL_OFFSET:SPARECTRL_OFFSET + SPARECTRL_SIZE - 1]),
.scout(func_sov[SPARECTRL_OFFSET:SPARECTRL_OFFSET + SPARECTRL_SIZE - 1]),
.din(spare_ctrl_wrapped_q),
.dout(spare_ctrl_wrapped_q)
);
// func ring registers end
//=====================================================================
// Thold/SG Staging
//=====================================================================
// func_slp lcbor
tri_lcbor lcbor_funcslp(
.clkoff_b(lcb_clkoff_dc_b),
.thold(pc_pc_func_slp_sl_thold_0),
.sg(pc_pc_sg_0),
.act_dis(lcb_act_dis_dc),
.force_t(force_funcslp),
.thold_b(pc_pc_func_slp_sl_thold_0_b)
);
//=====================================================================
// Scan Connections
//=====================================================================
// Func ring
assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]};
assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b;
endmodule |
module lq_agen_glbloc(
x_b,
y_b,
g08,
t08
);
input [0:7] x_b;
input [0:7] y_b;
output g08;
output t08;
wire [0:7] g01;
wire [0:7] t01;
wire [0:3] g02_b;
wire [0:3] t02_b;
wire [0:1] g04;
wire [0:1] t04;
wire g08_b;
wire t08_b;
//assign g01[0] = (~(x_b[0] | y_b[0]));
tri_nor2 #(.WIDTH(8)) g01_0 (.y(g01[0:7]), .a(x_b[0:7]), .b(y_b[0:7]));
//assign t01[0] = (~(x_b[0] & y_b[0]));
tri_nand2 #(.WIDTH(8)) t01_0 (.y(t01[0:7]), .a(x_b[0:7]), .b(y_b[0:7]));
//assign g02_b[0] = (~(g01[0] | (t01[0] & g01[1])));
tri_aoi21 g02_b_0 (.y(g02_b[0]), .a0(t01[0]), .a1(g01[1]), .b0(g01[0]));
//assign g02_b[1] = (~(g01[2] | (t01[2] & g01[3])));
tri_aoi21 g02_b_1 (.y(g02_b[1]), .a0(t01[2]), .a1(g01[3]), .b0(g01[2]));
//assign g02_b[2] = (~(g01[4] | (t01[4] & g01[5])));
tri_aoi21 g02_b_2 (.y(g02_b[2]), .a0(t01[4]), .a1(g01[5]), .b0(g01[4]));
//assign g02_b[3] = (~(g01[6] | (t01[6] & g01[7])));
tri_aoi21 g02_b_3 (.y(g02_b[3]), .a0(t01[6]), .a1(g01[7]), .b0(g01[6]));
//assign t02_b[0] = (~(t01[0] & t01[1]));
tri_nand2 t02_b_0 (.y(t02_b[0]), .a(t01[0]), .b(t01[1]));
//assign t02_b[1] = (~(t01[2] & t01[3]));
tri_nand2 t02_b_1 (.y(t02_b[1]), .a(t01[2]), .b(t01[3]));
//assign t02_b[2] = (~(t01[4] & t01[5]));
tri_nand2 t02_b_2 (.y(t02_b[2]), .a(t01[4]), .b(t01[5]));
//assign t02_b[3] = (~(t01[6] & t01[7]));
tri_nand2 t02_b_3 (.y(t02_b[3]), .a(t01[6]), .b(t01[7]));
//assign g04[0] = (~(g02_b[0] & (t02_b[0] | g02_b[1])));
tri_oai21 g04_0 (.y(g04[0]), .a0(t02_b[0]), .a1(g02_b[1]), .b0(g02_b[0]));
//assign g04[1] = (~(g02_b[2] & (t02_b[2] | g02_b[3])));
tri_oai21 g04_1 (.y(g04[1]), .a0(t02_b[2]), .a1(g02_b[3]), .b0(g02_b[2]));
//assign t04[0] = (~(t02_b[0] | t02_b[1]));
tri_nor2 t04_0 (.y(t04[0]), .a(t02_b[0]), .b(t02_b[1]));
//assign t04[1] = (~(t02_b[2] | t02_b[3]));
tri_nor2 t04_1 (.y(t04[1]), .a(t02_b[2]), .b(t02_b[3]));
//assign g08_b = (~(g04[0] | (t04[0] & g04[1])));
tri_aoi21 g08_b_0 (.y(g08_b), .a0(t04[0]), .a1(g04[1]), .b0(g04[0]));
//assign t08_b = (~((t04[0] & t04[1])));
tri_nand2 t08_b_0 (.y(t08_b), .a(t04[0]), .b(t04[1]));
//assign g08 = (~(g08_b)); // output
tri_inv g08_0 (.y(g08), .a(g08_b));
//assign t08 = (~(t08_b)); // output
tri_inv t08_0 (.y(t08), .a(t08_b));
endmodule |
module lq_agen_csmux(
sum_0,
sum_1,
ci_b,
sum
);
input [0:7] sum_0; // after xor
input [0:7] sum_1;
input ci_b;
output [0:7] sum;
wire [0:7] sum0_b;
wire [0:7] sum1_b;
wire int_ci;
wire int_ci_t;
wire int_ci_b;
//assign int_ci = (~ci_b);
tri_inv int_ci_0 (.y(int_ci), .a(ci_b));
//assign int_ci_t = (~ci_b);
tri_inv int_ci_t_0 (.y(int_ci_t), .a(ci_b));
//assign int_ci_b = (~int_ci_t);
tri_inv int_ci_b_0 (.y(int_ci_b), .a(int_ci_t));
//assign sum0_b[0] = (~(sum_0[0] & int_ci_b));
tri_nand2 #(.WIDTH(8)) sum0_b_0 (.y(sum0_b[0:7]), .a(sum_0[0:7]), .b({8{int_ci_b}}));
//assign sum[0] = (~(sum0_b[0] & sum1_b[0]));
tri_nand2 #(.WIDTH(8)) sum0 (.y(sum[0:7]), .a(sum0_b[0:7]), .b(sum1_b[0:7]));
endmodule |
module lq_agen_glbglb(
g08,
t08,
c64_b
);
input [1:7] g08;
input [1:6] t08;
output [1:7] c64_b;
wire [0:3] b1_g16_b;
wire [0:2] b1_t16_b;
wire [0:1] b1_g32;
wire [0:0] b1_t32;
wire [0:3] b2_g16_b;
wire [0:2] b2_t16_b;
wire [0:1] b2_g32;
wire [0:0] b2_t32;
wire [0:3] b3_g16_b;
wire [0:2] b3_t16_b;
wire [0:1] b3_g32;
wire [0:0] b3_t32;
wire [0:3] b4_g16_b;
wire [0:2] b4_t16_b;
wire [0:1] b4_g32;
wire [0:0] b4_t32;
wire [0:2] b5_g16_b;
wire [0:1] b5_t16_b;
wire [0:1] b5_g32;
wire [0:0] b5_t32;
wire [0:1] b6_g16_b;
wire [0:0] b6_t16_b;
wire [0:0] b6_g32;
wire [0:0] b7_g16_b;
wire [0:0] b7_g32;
////#############################
////## byte 1
////#############################
//assign b1_g16_b[0] = (~(g08[1] | (t08[1] & g08[2])));
tri_aoi21 b1_g16_b_0 (.y(b1_g16_b[0]), .a0(t08[1]), .a1(g08[2]), .b0(g08[1]));
//assign b1_g16_b[1] = (~(g08[3] | (t08[3] & g08[4])));
tri_aoi21 b1_g16_b_1 (.y(b1_g16_b[1]), .a0(t08[3]), .a1(g08[4]), .b0(g08[3]));
//assign b1_g16_b[2] = (~(g08[5] | (t08[5] & g08[6])));
tri_aoi21 b1_g16_b_2 (.y(b1_g16_b[2]), .a0(t08[5]), .a1(g08[6]), .b0(g08[5]));
//assign b1_g16_b[3] = (~(g08[7]));
tri_inv b1_g16_b_3 (.y(b1_g16_b[3]), .a(g08[7]));
//assign b1_t16_b[0] = (~(t08[1] & t08[2]));
tri_nand2 b1_t16_b_0 (.y(b1_t16_b[0]), .a(t08[1]), .b(t08[2]));
//assign b1_t16_b[1] = (~(t08[3] & t08[4]));
tri_nand2 b1_t16_b_1 (.y(b1_t16_b[1]), .a(t08[3]), .b(t08[4]));
//assign b1_t16_b[2] = (~(t08[5] & t08[6]));
tri_nand2 b1_t16_b_2 (.y(b1_t16_b[2]), .a(t08[5]), .b(t08[6]));
//assign b1_g32[0] = (~(b1_g16_b[0] & (b1_t16_b[0] | b1_g16_b[1])));
tri_oai21 b1_g32_0 (.y(b1_g32[0]), .a0(b1_t16_b[0]), .a1(b1_g16_b[1]), .b0(b1_g16_b[0]));
//assign b1_g32[1] = (~(b1_g16_b[2] & (b1_t16_b[2] | b1_g16_b[3])));
tri_oai21 b1_g32_1 (.y(b1_g32[1]), .a0(b1_t16_b[2]), .a1(b1_g16_b[3]), .b0(b1_g16_b[2]));
//assign b1_t32[0] = (~(b1_t16_b[0] | b1_t16_b[1]));
tri_nor2 b1_t32_0 (.y(b1_t32[0]), .a(b1_t16_b[0]), .b(b1_t16_b[1]));
//assign c64_b[1] = (~(b1_g32[0] | (b1_t32[0] & b1_g32[1]))); //output--
tri_aoi21 c64_b_1 (.y(c64_b[1]), .a0(b1_t32[0]), .a1(b1_g32[1]), .b0(b1_g32[0]));
////#############################
////## byte 2
////#############################
//assign b2_g16_b[0] = (~(g08[2] | (t08[2] & g08[3])));
tri_aoi21 b2_g16_b_0 (.y(b2_g16_b[0]), .a0(t08[2]), .a1(g08[3]), .b0(g08[2]));
//assign b2_g16_b[1] = (~(g08[4] | (t08[4] & g08[5])));
tri_aoi21 b2_g16_b_1 (.y(b2_g16_b[1]), .a0(t08[4]), .a1(g08[5]), .b0(g08[4]));
//assign b2_g16_b[2] = (~(g08[6]));
tri_inv #(.WIDTH(2)) b2_g16_b_2 (.y(b2_g16_b[2:3]), .a(g08[6:7]));
//assign b2_t16_b[0] = (~(t08[2] & t08[3]));
tri_nand2 b2_t16_b_0 (.y(b2_t16_b[0]), .a(t08[2]), .b(t08[3]));
//assign b2_t16_b[1] = (~(t08[4] & t08[5]));
tri_nand2 b2_t16_b_1 (.y(b2_t16_b[1]), .a(t08[4]), .b(t08[5]));
//assign b2_t16_b[2] = (~(t08[6]));
tri_inv b2_t16_b_2 (.y(b2_t16_b[2]), .a(t08[6]));
//assign b2_g32[0] = (~(b2_g16_b[0] & (b2_t16_b[0] | b2_g16_b[1])));
tri_oai21 b2_g32_0 (.y(b2_g32[0]), .a0(b2_t16_b[0]), .a1(b2_g16_b[1]), .b0(b2_g16_b[0]));
//assign b2_g32[1] = (~(b2_g16_b[2] & (b2_t16_b[2] | b2_g16_b[3])));
tri_oai21 b2_g32_1 (.y(b2_g32[1]), .a0(b2_t16_b[2]), .a1(b2_g16_b[3]), .b0(b2_g16_b[2]));
//assign b2_t32[0] = (~(b2_t16_b[0] | b2_t16_b[1]));
tri_nor2 b2_t32_0 (.y(b2_t32[0]), .a(b2_t16_b[0]), .b(b2_t16_b[1]));
//assign c64_b[2] = (~(b2_g32[0] | (b2_t32[0] & b2_g32[1]))); //output--
tri_aoi21 c64_b_2 (.y(c64_b[2]), .a0(b2_t32[0]), .a1(b2_g32[1]), .b0(b2_g32[0]));
////#############################
////## byte 3
////#############################
//assign b3_g16_b[0] = (~(g08[3] | (t08[3] & g08[4])));
tri_aoi21 b3_g16_b_0 (.y(b3_g16_b[0]), .a0(t08[3]), .a1(g08[4]), .b0(g08[3]));
//assign b3_g16_b[1] = (~(g08[5]));
tri_inv #(.WIDTH(3)) b3_g16_b_3 (.y(b3_g16_b[1:3]), .a(g08[5:7]));
//assign b3_t16_b[0] = (~(t08[3] & t08[4]));
tri_nand2 b3_t16_b_0 (.y(b3_t16_b[0]), .a(t08[3]), .b(t08[4]));
//assign b3_t16_b[1] = (~(t08[5]));
tri_inv #(.WIDTH(2)) b3_t16_b_1 (.y(b3_t16_b[1:2]), .a(t08[5:6]));
//assign b3_g32[0] = (~(b3_g16_b[0] & (b3_t16_b[0] | b3_g16_b[1])));
tri_oai21 b3_g32_0 (.y(b3_g32[0]), .a0(b3_t16_b[0]), .a1(b3_g16_b[1]), .b0(b3_g16_b[0]));
//assign b3_g32[1] = (~(b3_g16_b[2] & (b3_t16_b[2] | b3_g16_b[3])));
tri_oai21 b3_g32_1 (.y(b3_g32[1]), .a0(b3_t16_b[2]), .a1(b3_g16_b[3]), .b0(b3_g16_b[2]));
//assign b3_t32[0] = (~(b3_t16_b[0] | b3_t16_b[1]));
tri_nor2 b3_t32_0 (.y(b3_t32[0]), .a(b3_t16_b[0]), .b(b3_t16_b[1]));
//assign c64_b[3] = (~(b3_g32[0] | (b3_t32[0] & b3_g32[1]))); //output--
tri_aoi21 c64_b_3 (.y(c64_b[3]), .a0(b3_t32[0]), .a1(b3_g32[1]), .b0(b3_g32[0]));
////#############################
////## byte 4
////#############################
//assign b4_g16_b[0] = (~(g08[4]));
tri_inv #(.WIDTH(4)) b4_g16_b_0 (.y(b4_g16_b[0:3]), .a(g08[4:7]));
//assign b4_t16_b[0] = (~(t08[4]));
tri_inv #(.WIDTH(3)) b4_t16_b_0 (.y(b4_t16_b[0:2]), .a(t08[4:6]));
//assign b4_g32[0] = (~(b4_g16_b[0] & (b4_t16_b[0] | b4_g16_b[1])));
tri_oai21 b4_g32_0 (.y(b4_g32[0]), .a0(b4_t16_b[0]), .a1(b4_g16_b[1]), .b0(b4_g16_b[0]));
//assign b4_g32[1] = (~(b4_g16_b[2] & (b4_t16_b[2] | b4_g16_b[3])));
tri_oai21 b4_g32_1 (.y(b4_g32[1]), .a0(b4_t16_b[2]), .a1(b4_g16_b[3]), .b0(b4_g16_b[2]));
//assign b4_t32[0] = (~(b4_t16_b[0] | b4_t16_b[1]));
tri_nor2 b4_t32_0 (.y(b4_t32[0]), .a(b4_t16_b[0]), .b(b4_t16_b[1]));
//assign c64_b[4] = (~(b4_g32[0] | (b4_t32[0] & b4_g32[1]))); //output--
tri_aoi21 c64_b_4 (.y(c64_b[4]), .a0(b4_t32[0]), .a1(b4_g32[1]), .b0(b4_g32[0]));
////#############################
////## byte 5
////#############################
//assign b5_g16_b[0] = (~(g08[5]));
tri_inv #(.WIDTH(3)) b5_g16_b_0 (.y(b5_g16_b[0:2]), .a(g08[5:7]));
//assign b5_t16_b[0] = (~(t08[5]));
tri_inv #(.WIDTH(2)) b5_t16_b_0 (.y(b5_t16_b[0:1]), .a(t08[5:6]));
//assign b5_g32[0] = (~(b5_g16_b[0] & (b5_t16_b[0] | b5_g16_b[1])));
tri_oai21 b5_g32_0 (.y(b5_g32[0]), .a0(b5_t16_b[0]), .a1(b5_g16_b[1]), .b0(b5_g16_b[0]));
//assign b5_g32[1] = (~(b5_g16_b[2]));
tri_inv b5_g32_1 (.y(b5_g32[1]), .a(b5_g16_b[2]));
//assign b5_t32[0] = (~(b5_t16_b[0] | b5_t16_b[1]));
tri_nor2 b5_t32_0 (.y(b5_t32[0]), .a(b5_t16_b[0]), .b(b5_t16_b[1]));
//assign c64_b[5] = (~(b5_g32[0] | (b5_t32[0] & b5_g32[1]))); //output--
tri_aoi21 c64_b_5 (.y(c64_b[5]), .a0(b5_t32[0]), .a1(b5_g32[1]), .b0(b5_g32[0]));
////#############################
////## byte 6
////#############################
//assign b6_g16_b[0] = (~(g08[6]));
tri_inv #(.WIDTH(2)) b6_g16_b_0 (.y(b6_g16_b[0:1]), .a(g08[6:7]));
//assign b6_t16_b[0] = (~(t08[6]));
tri_inv b6_t16_b_0 (.y(b6_t16_b[0]), .a(t08[6]));
//assign b6_g32[0] = (~(b6_g16_b[0] & (b6_t16_b[0] | b6_g16_b[1])));
tri_oai21 b6_g32_0 (.y(b6_g32[0]), .a0(b6_t16_b[0]), .a1(b6_g16_b[1]), .b0(b6_g16_b[0]));
//assign c64_b[6] = (~(b6_g32[0])); //output--
tri_inv c64_b_6 (.y(c64_b[6]), .a(b6_g32[0]));
////#############################
////## byte 7
////#############################
//assign b7_g16_b[0] = (~(g08[7]));
tri_inv b7_g16_b_0 (.y(b7_g16_b[0]), .a(g08[7]));
//assign b7_g32[0] = (~(b7_g16_b[0]));
tri_inv b7_g32_0 (.y(b7_g32[0]), .a(b7_g16_b[0]));
//assign c64_b[7] = (~(b7_g32[0])); //output--
tri_inv c64_b_7 (.y(c64_b[7]), .a(b7_g32[0]));
endmodule |
module pcq_spr(
// Include model build parameters
`include "tri_a2o.vh"
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
// pervasive signals
input scan_dis_dc_b,
input lcb_clkoff_dc_b,
input lcb_mpw1_dc_b,
input lcb_mpw2_dc_b,
input lcb_delay_lclkr_dc,
input lcb_act_dis_dc,
input pc_pc_func_sl_thold_0,
input pc_pc_sg_0,
input func_scan_in,
output func_scan_out,
// slowSPR Interface
input slowspr_val_in,
input slowspr_rw_in,
input [0:1] slowspr_etid_in,
input [0:9] slowspr_addr_in,
input [64-`GPR_WIDTH:63] slowspr_data_in,
input slowspr_done_in,
input [0:`THREADS-1] cp_flush,
output slowspr_val_out,
output slowspr_rw_out,
output [0:1] slowspr_etid_out,
output [0:9] slowspr_addr_out,
output [64-`GPR_WIDTH:63] slowspr_data_out,
output slowspr_done_out,
// Event Mux Controls
output [0:39] pc_rv_event_mux_ctrls,
// CESR1 Controls
output pc_iu_event_bus_enable,
output pc_fu_event_bus_enable,
output pc_rv_event_bus_enable,
output pc_mm_event_bus_enable,
output pc_xu_event_bus_enable,
output pc_lq_event_bus_enable,
output [0:2] pc_iu_event_count_mode,
output [0:2] pc_fu_event_count_mode,
output [0:2] pc_rv_event_count_mode,
output [0:2] pc_mm_event_count_mode,
output [0:2] pc_xu_event_count_mode,
output [0:2] pc_lq_event_count_mode,
output sp_rg_trace_bus_enable,
output pc_iu_instr_trace_mode,
output pc_iu_instr_trace_tid,
output pc_lq_instr_trace_mode,
output pc_lq_instr_trace_tid,
output pc_xu_instr_trace_mode,
output pc_xu_instr_trace_tid,
output pc_lq_event_bus_seldbghi,
output pc_lq_event_bus_seldbglo,
input [0:`THREADS-1] xu_pc_perfmon_alert,
output [0:`THREADS-1] pc_xu_spr_cesr1_pmae,
// SRAMD data and load pulse
input rg_rg_load_sramd,
input [0:63] rg_rg_sramd_din,
// Trace/Trigger Signals
output [0:7] dbg_spr
);
//=====================================================================
// Signal Declarations
//=====================================================================
// Scan Ring Constants:
// Register sizes
parameter CESR1_SIZE = 12;
parameter CESR1_IS0_SIZE = 2;
parameter CESR1_IS1_SIZE = 2;
parameter RESR1_SIZE = 20;
parameter RESR2_SIZE = 20;
parameter SRAMD_SIZE = 64;
parameter MISC_SIZE = 2;
// start of func scan chain ordering
parameter CP_FLUSH_OFFSET = 0;
parameter SLOWSPR_VAL_OFFSET = CP_FLUSH_OFFSET + `THREADS;
parameter SLOWSPR_RW_OFFSET = SLOWSPR_VAL_OFFSET + 1;
parameter SLOWSPR_ETID_OFFSET = SLOWSPR_RW_OFFSET + 1;
parameter SLOWSPR_ADDR_OFFSET = SLOWSPR_ETID_OFFSET + 2;
parameter SLOWSPR_DATA_OFFSET = SLOWSPR_ADDR_OFFSET + 10;
parameter SLOWSPR_DONE_OFFSET = SLOWSPR_DATA_OFFSET + `GPR_WIDTH;
parameter CESR1_OFFSET = SLOWSPR_DONE_OFFSET + 1;
parameter CESR1_IS0_OFFSET = CESR1_OFFSET + CESR1_SIZE;
parameter CESR1_IS1_OFFSET = CESR1_IS0_OFFSET + CESR1_IS0_SIZE;
parameter RESR1_OFFSET = CESR1_IS1_OFFSET + CESR1_IS1_SIZE;
parameter RESR2_OFFSET = RESR1_OFFSET + RESR1_SIZE;
parameter SRAMD_OFFSET = RESR2_OFFSET + RESR2_SIZE;
parameter MISC_OFFSET = SRAMD_OFFSET + SRAMD_SIZE;
parameter FUNC_RIGHT = MISC_OFFSET + MISC_SIZE - 1;
// end of func scan chain ordering
parameter [32:63] CESR1_MASK = 32'b11111011110011110000000000000000;
parameter [32:63] EVENTMUX_32_MASK = 32'b11111111111111111111111111111111;
parameter [32:63] EVENTMUX_64_MASK = 32'b11111111111111111111000000000000;
parameter [32:63] EVENTMUX_128_MASK = 32'b11111111111111111111111100000000;
//--------------------------
// signals
//--------------------------
wire [0:`THREADS-1] cp_flush_l2;
wire slowspr_val_d;
wire slowspr_val_l2;
wire slowspr_rw_d;
wire slowspr_rw_l2;
wire [0:1] slowspr_etid_d;
wire [0:1] slowspr_etid_l2;
wire [0:9] slowspr_addr_d;
wire [0:9] slowspr_addr_l2;
wire [64-`GPR_WIDTH:63] slowspr_data_d;
wire [64-`GPR_WIDTH:63] slowspr_data_l2;
wire slowspr_done_d;
wire slowspr_done_l2;
wire pc_done_int;
wire [64-`GPR_WIDTH:63] pc_data_int;
wire [32:63] pc_reg_data;
wire cesr1_sel;
wire cesr1_wren;
wire cesr1_rden;
wire [32:32+CESR1_SIZE-1] cesr1_d;
wire [32:32+CESR1_SIZE-1] cesr1_l2;
wire [32:63] cesr1_out;
// Instruction Sampling PMAE/PMAO latches
wire [0:1] cesr1_is_wren;
wire [0:1] cesr1_is0_d;
wire [0:1] cesr1_is0_l2;
wire [0:1] cesr1_is1_d;
wire [0:1] cesr1_is1_l2;
wire [0:1] perfmon_alert_din;
wire [0:1] perfmon_alert_q;
wire [0:1] update_is_ctrls;
wire resr1_sel;
wire resr1_wren;
wire resr1_rden;
wire [32:32+RESR1_SIZE-1] resr1_d;
wire [32:32+RESR1_SIZE-1] resr1_l2;
wire [32:63] resr1_out;
wire resr2_sel;
wire resr2_wren;
wire resr2_rden;
wire [32:32+RESR2_SIZE-1] resr2_d;
wire [32:32+RESR2_SIZE-1] resr2_l2;
wire [32:63] resr2_out;
wire sramd_sel;
wire sramd_wren;
wire sramd_rden;
wire [0:SRAMD_SIZE-1] sramd_d;
wire [0:SRAMD_SIZE-1] sramd_l2;
wire [0:63] sramd_out;
wire [0:3] slowspr_tid;
// misc, pervasive signals
wire tiup;
wire pc_pc_func_sl_thold_0_b;
wire force_func;
wire [0:FUNC_RIGHT] func_siv;
wire [0:FUNC_RIGHT] func_sov;
// Get rid of sinkless net messages
// synopsys translate_off
(* analysis_not_referenced="true" *)
// synopsys translate_on
wire unused_signals;
assign unused_signals = (|slowspr_tid[2:3]);
//!! Bugspray Include: pcq_spr;
assign tiup = 1'b1;
//=====================================================================
// Latches
//=====================================================================
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[CP_FLUSH_OFFSET:CP_FLUSH_OFFSET + `THREADS - 1]),
.scout(func_sov[CP_FLUSH_OFFSET:CP_FLUSH_OFFSET + `THREADS - 1]),
.din(cp_flush),
.dout(cp_flush_l2)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[SLOWSPR_VAL_OFFSET]),
.scout(func_sov[SLOWSPR_VAL_OFFSET]),
.din(slowspr_val_d),
.dout(slowspr_val_l2)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(slowspr_val_d),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[SLOWSPR_RW_OFFSET]),
.scout(func_sov[SLOWSPR_RW_OFFSET]),
.din(slowspr_rw_d),
.dout(slowspr_rw_l2)
);
tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(slowspr_val_d),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[SLOWSPR_ETID_OFFSET:SLOWSPR_ETID_OFFSET + 2 - 1]),
.scout(func_sov[SLOWSPR_ETID_OFFSET:SLOWSPR_ETID_OFFSET + 2 - 1]),
.din(slowspr_etid_d),
.dout(slowspr_etid_l2)
);
tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(slowspr_val_d),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[SLOWSPR_ADDR_OFFSET:SLOWSPR_ADDR_OFFSET + 10 - 1]),
.scout(func_sov[SLOWSPR_ADDR_OFFSET:SLOWSPR_ADDR_OFFSET + 10 - 1]),
.din(slowspr_addr_d),
.dout(slowspr_addr_l2)
);
tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(slowspr_val_d),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[SLOWSPR_DATA_OFFSET:SLOWSPR_DATA_OFFSET + `GPR_WIDTH - 1]),
.scout(func_sov[SLOWSPR_DATA_OFFSET:SLOWSPR_DATA_OFFSET + `GPR_WIDTH - 1]),
.din(slowspr_data_d),
.dout(slowspr_data_l2)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[SLOWSPR_DONE_OFFSET]),
.scout(func_sov[SLOWSPR_DONE_OFFSET]),
.din(slowspr_done_d),
.dout(slowspr_done_l2)
);
tri_ser_rlmreg_p #(.WIDTH(CESR1_SIZE), .INIT(0)) cesr1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(cesr1_wren),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[CESR1_OFFSET:CESR1_OFFSET + CESR1_SIZE - 1]),
.scout(func_sov[CESR1_OFFSET:CESR1_OFFSET + CESR1_SIZE - 1]),
.din(cesr1_d),
.dout(cesr1_l2)
);
tri_ser_rlmreg_p #(.WIDTH(CESR1_IS0_SIZE), .INIT(0)) cesr1_is0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(cesr1_is_wren[0]),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[CESR1_IS0_OFFSET:CESR1_IS0_OFFSET + CESR1_IS0_SIZE - 1]),
.scout(func_sov[CESR1_IS0_OFFSET:CESR1_IS0_OFFSET + CESR1_IS0_SIZE - 1]),
.din(cesr1_is0_d),
.dout(cesr1_is0_l2)
);
tri_ser_rlmreg_p #(.WIDTH(CESR1_IS1_SIZE), .INIT(0)) cesr1_is1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(cesr1_is_wren[1]),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[CESR1_IS1_OFFSET:CESR1_IS1_OFFSET + CESR1_IS1_SIZE - 1]),
.scout(func_sov[CESR1_IS1_OFFSET:CESR1_IS1_OFFSET + CESR1_IS1_SIZE - 1]),
.din(cesr1_is1_d),
.dout(cesr1_is1_l2)
);
tri_ser_rlmreg_p #(.WIDTH(RESR1_SIZE), .INIT(0)) resr1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(resr1_wren),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[RESR1_OFFSET:RESR1_OFFSET + RESR1_SIZE - 1]),
.scout(func_sov[RESR1_OFFSET:RESR1_OFFSET + RESR1_SIZE - 1]),
.din(resr1_d),
.dout(resr1_l2)
);
tri_ser_rlmreg_p #(.WIDTH(RESR2_SIZE), .INIT(0)) resr2_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(resr2_wren),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[RESR2_OFFSET:RESR2_OFFSET + RESR2_SIZE - 1]),
.scout(func_sov[RESR2_OFFSET:RESR2_OFFSET + RESR2_SIZE - 1]),
.din(resr2_d),
.dout(resr2_l2)
);
tri_ser_rlmreg_p #(.WIDTH(SRAMD_SIZE), .INIT(0)) sramd_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(sramd_wren),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[SRAMD_OFFSET:SRAMD_OFFSET + SRAMD_SIZE - 1]),
.scout(func_sov[SRAMD_OFFSET:SRAMD_OFFSET + SRAMD_SIZE - 1]),
.din(sramd_d),
.dout(sramd_l2)
);
tri_rlmreg_p #(.WIDTH(MISC_SIZE), .INIT(0)) misc_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_pc_func_sl_thold_0_b),
.sg(pc_pc_sg_0),
.force_t(force_func),
.delay_lclkr(lcb_delay_lclkr_dc),
.mpw1_b(lcb_mpw1_dc_b),
.mpw2_b(lcb_mpw2_dc_b),
.scin(func_siv[MISC_OFFSET:MISC_OFFSET + MISC_SIZE - 1]),
.scout(func_sov[MISC_OFFSET:MISC_OFFSET + MISC_SIZE - 1]),
.din(perfmon_alert_din),
.dout(perfmon_alert_q)
);
//=====================================================================
// inputs + staging
//=====================================================================
assign slowspr_val_d = slowspr_val_in & !(|(slowspr_tid[0:`THREADS-1] & cp_flush_l2));
assign slowspr_rw_d = slowspr_rw_in;
assign slowspr_etid_d = slowspr_etid_in;
assign slowspr_addr_d = slowspr_addr_in;
assign slowspr_data_d = slowspr_data_in;
assign slowspr_done_d = slowspr_done_in;
//=====================================================================
// Outputs
//=====================================================================
assign slowspr_tid = (slowspr_etid_in == 2'b00) ? 4'b1000 :
(slowspr_etid_in == 2'b01) ? 4'b0100 :
(slowspr_etid_in == 2'b10) ? 4'b0010 :
(slowspr_etid_in == 2'b11) ? 4'b0001 :
4'b0000;
assign slowspr_val_out = slowspr_val_l2;
assign slowspr_rw_out = slowspr_rw_l2;
assign slowspr_etid_out = slowspr_etid_l2;
assign slowspr_addr_out = slowspr_addr_l2;
assign slowspr_data_out = slowspr_data_l2 | pc_data_int;
assign slowspr_done_out = slowspr_done_l2 | pc_done_int;
assign pc_rv_event_mux_ctrls = {resr1_out[32:51], resr2_out[32:51]};
// CESR1 controls miscellaneous performance related functions:
// Event bus enable to all units.
assign pc_iu_event_bus_enable = cesr1_out[32];
assign pc_fu_event_bus_enable = cesr1_out[32];
assign pc_rv_event_bus_enable = cesr1_out[32];
assign pc_mm_event_bus_enable = cesr1_out[32];
assign pc_xu_event_bus_enable = cesr1_out[32];
assign pc_lq_event_bus_enable = cesr1_out[32];
// Count modes function to all units.
assign pc_iu_event_count_mode = cesr1_out[33:35];
assign pc_fu_event_count_mode = cesr1_out[33:35];
assign pc_rv_event_count_mode = cesr1_out[33:35];
assign pc_mm_event_count_mode = cesr1_out[33:35];
assign pc_xu_event_count_mode = cesr1_out[33:35];
assign pc_lq_event_count_mode = cesr1_out[33:35];
// Trace bus enable to all units (from pcq_regs).
assign sp_rg_trace_bus_enable = cesr1_out[36];
// Select trace bits for event counting.
assign pc_lq_event_bus_seldbghi = cesr1_out[38];
assign pc_lq_event_bus_seldbglo = cesr1_out[39];
// Instruction tracing.
assign pc_iu_instr_trace_mode = cesr1_out[40];
assign pc_iu_instr_trace_tid = cesr1_out[41];
assign pc_lq_instr_trace_mode = cesr1_out[40];
assign pc_lq_instr_trace_tid = cesr1_out[41];
assign pc_xu_instr_trace_mode = cesr1_out[40];
assign pc_xu_instr_trace_tid = cesr1_out[41];
//=====================================================================
// Instruction sampling
//=====================================================================
generate
if (`THREADS == 1)
begin : T1_INSTRSAMP
assign pc_xu_spr_cesr1_pmae = cesr1_is0_l2[0];
assign perfmon_alert_din = {xu_pc_perfmon_alert[0], 1'b0};
end
endgenerate
generate
if (`THREADS == 2)
begin : T2_INSTRSAMP
assign pc_xu_spr_cesr1_pmae = {cesr1_is0_l2[0], cesr1_is1_l2[0]};
assign perfmon_alert_din = xu_pc_perfmon_alert[0:1];
end
endgenerate
//=====================================================================
// register select
//=====================================================================
assign cesr1_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1110010000; // 912
assign resr1_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1110011010; // 922
assign resr2_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1110011011; // 923
assign sramd_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1101111110; // 894
assign pc_done_int = cesr1_sel | resr1_sel | resr2_sel | sramd_sel;
//=====================================================================
// register write
//=====================================================================
assign cesr1_wren = cesr1_sel & slowspr_rw_l2 == 1'b0;
assign resr1_wren = resr1_sel & slowspr_rw_l2 == 1'b0;
assign resr2_wren = resr2_sel & slowspr_rw_l2 == 1'b0;
assign sramd_wren = rg_rg_load_sramd;
assign cesr1_d = CESR1_MASK[32:32 + CESR1_SIZE - 1] & slowspr_data_l2[32:32 + CESR1_SIZE - 1];
assign resr1_d = EVENTMUX_64_MASK[32:32 + RESR1_SIZE - 1] & slowspr_data_l2[32:32 + RESR1_SIZE - 1];
assign resr2_d = EVENTMUX_64_MASK[32:32 + RESR2_SIZE - 1] & slowspr_data_l2[32:32 + RESR2_SIZE - 1];
assign sramd_d = rg_rg_sramd_din;
// Instruction Sampling
assign update_is_ctrls = {(perfmon_alert_q[0] & cesr1_is0_l2[0]), (perfmon_alert_q[1] & cesr1_is1_l2[0])};
assign cesr1_is_wren = {(cesr1_wren | update_is_ctrls[0]), (cesr1_wren | update_is_ctrls[1])};
assign cesr1_is0_d[0] = CESR1_MASK[44] & slowspr_data_l2[44] & (~update_is_ctrls[0]); // PMAE_T0 cleared on perfmon alert.
assign cesr1_is0_d[1] = (CESR1_MASK[45] & slowspr_data_l2[45] & (~update_is_ctrls[0])) | update_is_ctrls[0]; // PMAO_T0 set on perfmon alert.
assign cesr1_is1_d[0] = CESR1_MASK[46] & slowspr_data_l2[46] & (~update_is_ctrls[1]); // PMAE_T1 cleared on perfmon alert.
assign cesr1_is1_d[1] = (CESR1_MASK[47] & slowspr_data_l2[47] & (~update_is_ctrls[1])) | update_is_ctrls[1]; // PMAO_T1 set on perfmon alert.
//=====================================================================
// register read
//=====================================================================
assign cesr1_rden = cesr1_sel & slowspr_rw_l2 == 1'b1;
assign resr1_rden = resr1_sel & slowspr_rw_l2 == 1'b1;
assign resr2_rden = resr2_sel & slowspr_rw_l2 == 1'b1;
assign sramd_rden = sramd_sel & slowspr_rw_l2 == 1'b1;
assign cesr1_out[32:63] = {cesr1_l2, cesr1_is0_l2, cesr1_is1_l2, {64-(32+CESR1_SIZE+CESR1_IS0_SIZE+CESR1_IS1_SIZE){1'b0}} };
assign resr1_out[32:63] = {resr1_l2, {64-(32+RESR1_SIZE){1'b0}} };
assign resr2_out[32:63] = {resr2_l2, {64-(32+RESR2_SIZE){1'b0}} };
assign sramd_out[0:63] = sramd_l2;
assign pc_reg_data[32:63] = (cesr1_rden == 1'b1) ? cesr1_out :
(resr1_rden == 1'b1) ? resr1_out :
(resr2_rden == 1'b1) ? resr2_out :
(sramd_rden == 1'b1) ? sramd_out[32:63] :
{32{1'b0}};
generate
if (`GPR_WIDTH > 32)
begin : r64
assign pc_data_int[0:31] = (sramd_rden == 1'b1) ? sramd_out[0:31] :
{32{1'b0}};
end
endgenerate
assign pc_data_int[32:63] = pc_reg_data[32:63];
//=====================================================================
// Trace/Trigger Signals
//=====================================================================
assign dbg_spr = { cesr1_wren, // 0
sramd_wren, // 1
perfmon_alert_q[0:1], // 2:3
cesr1_is0_l2[0:1], // 4:5
cesr1_is1_l2[0:1] // 6:7
};
//=====================================================================
// Thold/SG Staging
//=====================================================================
// func_slp lcbor
tri_lcbor lcbor_funcslp(
.clkoff_b(lcb_clkoff_dc_b),
.thold(pc_pc_func_sl_thold_0),
.sg(pc_pc_sg_0),
.act_dis(lcb_act_dis_dc),
.force_t(force_func),
.thold_b(pc_pc_func_sl_thold_0_b)
);
//=====================================================================
// Scan Connections
//=====================================================================
// Func ring
assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]};
assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b;
endmodule |
module lq_spr_dvccmp(
en,
en00,
cmp,
dvcm,
dvcbe,
dvc_cmpr
);
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
parameter REGSIZE = 64;
input en;
input en00;
input [8-(REGSIZE/8):7] cmp;
input [0:1] dvcm;
input [8-(REGSIZE/8):7] dvcbe;
output dvc_cmpr;
// Signals
wire [8-(REGSIZE/8):7] cmp_mask_or;
wire [8-(REGSIZE/8):7] cmp_mask_and;
wire cmp_and;
wire cmp_or;
wire cmp_andor;
assign cmp_mask_or = (cmp | (~dvcbe)) & {(REGSIZE/8){|(dvcbe)}};
assign cmp_mask_and = (cmp & dvcbe);
assign cmp_and = &(cmp_mask_or);
assign cmp_or = |(cmp_mask_and);
generate
if (REGSIZE == 32) begin : cmp_andor_gen32
assign cmp_andor = (&(cmp_mask_or[4:5]) & |(dvcbe[4:5])) |
(&(cmp_mask_or[6:7]) & |(dvcbe[6:7]));
end
endgenerate
generate
if (REGSIZE == 64) begin : cmp_andor_gen64
assign cmp_andor = (&(cmp_mask_or[0:1]) & |(dvcbe[0:1])) |
(&(cmp_mask_or[2:3]) & |(dvcbe[2:3])) |
(&(cmp_mask_or[4:5]) & |(dvcbe[4:5])) |
(&(cmp_mask_or[6:7]) & |(dvcbe[6:7]));
end
endgenerate
assign dvc_cmpr = (dvcm[0:1] == 2'b00) ? en00 :
(dvcm[0:1] == 2'b01) ? (en & cmp_and) :
(dvcm[0:1] == 2'b10) ? (en & cmp_or) :
(en & cmp_andor);
endmodule |
module fu_tbllut(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
si,
so,
ex2_act,
f_fmt_ex2_b_frac,
f_fmt_ex3_b_frac,
f_tbe_ex3_expo_lsb,
f_tbe_ex3_est_recip,
f_tbe_ex3_est_rsqrt,
f_tbe_ex4_recip_ue1,
f_tbe_ex4_lu_sh,
f_tbe_ex4_match_en_sp,
f_tbe_ex4_match_en_dp,
f_tbe_ex4_recip_2046,
f_tbe_ex4_recip_2045,
f_tbe_ex4_recip_2044,
f_tbl_ex6_est_frac,
f_tbl_ex5_unf_expo,
f_tbl_ex6_recip_den
);
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input [2:5] delay_lclkr; // tidn,
input [2:5] mpw1_b; // tidn,
input [0:1] mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input si; //perv
output so; //perv
input ex2_act; //act
//----------------------------
input [1:6] f_fmt_ex2_b_frac;
input [7:22] f_fmt_ex3_b_frac;
input f_tbe_ex3_expo_lsb;
input f_tbe_ex3_est_recip;
input f_tbe_ex3_est_rsqrt;
input f_tbe_ex4_recip_ue1;
input f_tbe_ex4_lu_sh;
input f_tbe_ex4_match_en_sp;
input f_tbe_ex4_match_en_dp;
input f_tbe_ex4_recip_2046;
input f_tbe_ex4_recip_2045;
input f_tbe_ex4_recip_2044;
//----------------------------
output [0:26] f_tbl_ex6_est_frac;
output f_tbl_ex5_unf_expo;
output f_tbl_ex6_recip_den; //generates den flag
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire ex5_unf_expo;
wire [1:6] ex3_f;
wire ex3_sel_recip;
wire ex3_sel_rsqte;
wire ex3_sel_rsqto;
wire [1:20] ex3_est;
wire [1:20] ex3_est_recip;
wire [1:20] ex3_est_rsqte;
wire [1:20] ex3_est_rsqto;
wire [6:20] ex3_rng;
wire [6:20] ex3_rng_recip;
wire [6:20] ex3_rng_rsqte;
wire [6:20] ex3_rng_rsqto;
wire thold_0_b;
wire thold_0;
wire force_t;
wire sg_0;
wire ex3_act;
wire ex4_act;
wire ex5_act;
wire [0:3] spare_unused;
wire [0:5] ex3_lut_so;
wire [0:5] ex3_lut_si;
wire [0:6] act_so;
wire [0:6] act_si;
wire [0:19] ex4_lut_e_so;
wire [0:19] ex4_lut_e_si;
wire [0:14] ex4_lut_r_so;
wire [0:14] ex4_lut_r_si;
wire [0:15] ex4_lut_b_so;
wire [0:15] ex4_lut_b_si;
wire [6:20] ex4_rng;
wire [6:20] ex4_rng_b;
wire [1:20] ex4_est;
wire [1:20] ex4_est_b;
wire [7:22] ex4_bop;
wire [7:22] ex4_bop_b;
wire [0:36] ex4_tbl_sum;
wire [0:35] ex4_tbl_car;
wire [0:38] ex5_tbl_sum;
wire [0:38] ex5_tbl_car;
wire [0:79] ex5_lut_so;
wire [0:79] ex5_lut_si;
wire [0:27] ex6_lut_so;
wire [0:27] ex6_lut_si;
wire [0:27] ex5_lu;
wire [0:27] ex5_lux;
wire [0:26] ex5_lu_nrm;
wire [0:26] ex6_lu;
wire [0:27] lua_p;
wire [1:37] lua_t;
wire [1:38] lua_g;
wire [1:38] lua_g2;
wire [1:36] lua_g4;
wire [1:32] lua_g8;
wire [1:36] lua_t2;
wire [1:32] lua_t4;
wire [1:28] lua_t8;
wire [1:28] lua_gt8;
wire [0:27] lua_s0_b;
wire [0:27] lua_s1_b;
wire [0:3] lua_g16;
wire [0:1] lua_t16;
wire lua_c32;
wire lua_c24;
wire lua_c16;
wire lua_c08;
wire ex5_recip_den;
wire ex6_recip_den;
wire ex5_lu_sh;
wire ex5_recip_ue1;
wire ex5_recip_2044;
wire ex5_recip_2046;
wire ex5_recip_2045;
wire ex5_recip_2044_dp;
wire ex5_recip_2046_dp;
wire ex5_recip_2045_dp;
wire ex5_recip_2044_sp;
wire ex5_recip_2046_sp;
wire ex5_recip_2045_sp;
wire ex5_shlft_1;
wire ex5_shlft_0;
wire ex5_shrgt_1;
wire ex5_shrgt_2;
wire ex5_match_en_sp;
wire ex5_match_en_dp;
wire tbl_ex4_d1clk;
wire tbl_ex4_d2clk;
wire tbl_ex5_d1clk;
wire tbl_ex5_d2clk;
wire [0:`NCLK_WIDTH-1] tbl_ex4_lclk;
wire [0:`NCLK_WIDTH-1] tbl_ex5_lclk;
wire unused;
wire [0:36] ex5_tbl_sum_b;
wire [0:35] ex5_tbl_car_b;
wire ex5_match_en_sp_b;
wire ex5_match_en_dp_b;
wire ex5_recip_2046_b;
wire ex5_recip_2045_b;
wire ex5_recip_2044_b;
wire ex5_lu_sh_b;
wire ex5_recip_ue1_b;
wire ex5_sp_chop_24;
wire ex5_sp_chop_23;
wire ex5_sp_chop_22;
wire ex5_sp_chop_21;
//==##############################################################
//= map block attributes
//==##############################################################
assign unused = |(lua_g8[29:31]) | |(lua_g4[33:35]);
//==##############################################################
//= ex3 logic
//==##############################################################
tri_rlmreg_p #(.WIDTH(6)) ex3_lut_lat(
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[2]),
.mpw1_b(mpw1_b[2]),
.mpw2_b(mpw2_b[0]),
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(ex2_act),
.thold_b(thold_0_b),
.sg(sg_0),
.scout(ex3_lut_so),
.scin(ex3_lut_si),
//-----------------
.din(f_fmt_ex2_b_frac[1:6]),
.dout(ex3_f[1:6])
);
//==##############################################################
//= ex3 logic
//==##############################################################
//==###########################################
//= rsqrt ev lookup table
//==###########################################
fu_tblsqe ftbe(
.f(ex3_f[1:6]), //i--
.est(ex3_est_rsqte[1:20]), //o--
.rng(ex3_rng_rsqte[6:20]) //o--
);
//==###########################################
//= rsqrt od lookup table
//==###########################################
fu_tblsqo ftbo(
.f(ex3_f[1:6]), //i--
.est(ex3_est_rsqto[1:20]), //o--
.rng(ex3_rng_rsqto[6:20]) //o--
);
//==###########################################
//= recip lookup table
//==###########################################
fu_tblres ftbr(
.f(ex3_f[1:6]), //i--
.est(ex3_est_recip[1:20]), //o--
.rng(ex3_rng_recip[6:20]) //o--
);
//==###########################################
//= muxing
//==###########################################
assign ex3_sel_recip = f_tbe_ex3_est_recip;
assign ex3_sel_rsqte = f_tbe_ex3_est_rsqrt & (~f_tbe_ex3_expo_lsb);
assign ex3_sel_rsqto = f_tbe_ex3_est_rsqrt & f_tbe_ex3_expo_lsb;
assign ex3_est[1:20] = ({20{ex3_sel_recip}} & ex3_est_recip[1:20]) |
({20{ex3_sel_rsqte}} & ex3_est_rsqte[1:20]) |
({20{ex3_sel_rsqto}} & ex3_est_rsqto[1:20]); // nand2 / nand3
assign ex3_rng[6:20] = ({15{ex3_sel_recip}} & (ex3_rng_recip[6:20])) |
({15{ex3_sel_rsqte}} & (ex3_rng_rsqte[6:20])) |
({15{ex3_sel_rsqto}} & (ex3_rng_rsqto[6:20])); // nand2 / nand3
//==##############################################################
//= ex4 latches
//==##############################################################
tri_inv_nlats #(.WIDTH(20), .NEEDS_SRESET(0)) ex4_lut_e_lat(
.vd(vdd),
.gd(gnd),
.lclk(tbl_ex4_lclk), // lclk.clk
.d1clk(tbl_ex4_d1clk),
.d2clk(tbl_ex4_d2clk),
.scanin(ex4_lut_e_si),
.scanout(ex4_lut_e_so),
.d(ex3_est[1:20]), //0:19
.qb(ex4_est_b[1:20]) //0:19
);
tri_inv_nlats #(.WIDTH(15), .NEEDS_SRESET(0)) ex4_lut_r_lat(
.vd(vdd),
.gd(gnd),
.lclk(tbl_ex4_lclk), // lclk.clk
.d1clk(tbl_ex4_d1clk),
.d2clk(tbl_ex4_d2clk),
.scanin(ex4_lut_r_si),
.scanout(ex4_lut_r_so),
.d(ex3_rng[6:20]), //20:34
.qb(ex4_rng_b[6:20]) //20:34
);
tri_inv_nlats #(.WIDTH(16), .NEEDS_SRESET(0)) ex4_lut_b_lat(
.vd(vdd),
.gd(gnd),
.lclk(tbl_ex4_lclk), // lclk.clk
.d1clk(tbl_ex4_d1clk),
.d2clk(tbl_ex4_d2clk),
.scanin(ex4_lut_b_si),
.scanout(ex4_lut_b_so),
.d(f_fmt_ex3_b_frac[7:22]), //35:50
.qb(ex4_bop_b[7:22]) //35:50
);
assign ex4_est[1:20] = (~ex4_est_b[1:20]);
assign ex4_rng[6:20] = (~ex4_rng_b[6:20]);
assign ex4_bop[7:22] = (~ex4_bop_b[7:22]);
//==##############################################################
//= ex4 logic : multiply
//==##############################################################
tri_fu_tblmul ftbm(
.vdd(vdd),
.gnd(gnd),
.x(ex4_rng[6:20]), //i-- RECODED
.y(ex4_bop[7:22]), //i-- SHIFTED
.z({tiup,ex4_est[1:20]}), //i--
.tbl_sum(ex4_tbl_sum[0:36]), //o--
.tbl_car(ex4_tbl_car[0:35]) //o--
);
//==##############################################################
//= ex5 latches
//==##############################################################
tri_inv_nlats #(.WIDTH(80), .NEEDS_SRESET(0)) ex5_lut_lat(
.vd(vdd),
.gd(gnd),
.lclk(tbl_ex5_lclk), // lclk.clk
.d1clk(tbl_ex5_d1clk),
.d2clk(tbl_ex5_d2clk),
.scanin(ex5_lut_si),
.scanout(ex5_lut_so),
.d({ex4_tbl_sum[0:36],
ex4_tbl_car[0:35],
f_tbe_ex4_match_en_sp,
f_tbe_ex4_match_en_dp,
f_tbe_ex4_recip_2046,
f_tbe_ex4_recip_2045,
f_tbe_ex4_recip_2044,
f_tbe_ex4_lu_sh,
f_tbe_ex4_recip_ue1}),
//----
.qb({
ex5_tbl_sum_b[0:36],
ex5_tbl_car_b[0:35],
ex5_match_en_sp_b,
ex5_match_en_dp_b,
ex5_recip_2046_b,
ex5_recip_2045_b,
ex5_recip_2044_b,
ex5_lu_sh_b,
ex5_recip_ue1_b})
);
assign ex5_tbl_sum[0:36] = (~ex5_tbl_sum_b[0:36]);
assign ex5_tbl_car[0:35] = (~ex5_tbl_car_b[0:35]);
assign ex5_match_en_sp = (~ex5_match_en_sp_b);
assign ex5_match_en_dp = (~ex5_match_en_dp_b);
assign ex5_recip_2046 = (~ex5_recip_2046_b);
assign ex5_recip_2045 = (~ex5_recip_2045_b);
assign ex5_recip_2044 = (~ex5_recip_2044_b);
assign ex5_lu_sh = (~ex5_lu_sh_b);
assign ex5_recip_ue1 = (~ex5_recip_ue1_b);
assign ex5_tbl_sum[37] = tidn;
assign ex5_tbl_sum[38] = tidn;
assign ex5_tbl_car[36] = tidn; //tiup; -- the +1 in -mul = !mul + 1
assign ex5_tbl_car[37] = tidn; //tiup; -- the +1 in -mul = !mul + 1
assign ex5_tbl_car[38] = tidn; //tiup; -- the +1 in -mul = !mul + 1
//==##############################################################
//= ex5 logic : add
//==##############################################################
// all bits paricipate in the carry, but only upper bits of sum are returned
// P/G/T ------------------------------------------------------
assign lua_p[0:27] = ex5_tbl_sum[0:27] ^ ex5_tbl_car[0:27];
assign lua_t[1:37] = ex5_tbl_sum[1:37] | ex5_tbl_car[1:37];
assign lua_g[1:38] = ex5_tbl_sum[1:38] & ex5_tbl_car[1:38];
// LOCAL BYTE CARRY --------------------------------------------------
assign lua_g2[38] = lua_g[38];
assign lua_g2[37] = lua_g[37] | (lua_t[37] & lua_g[38]);
assign lua_g2[36] = lua_g[36] | (lua_t[36] & lua_g[37]);
assign lua_g2[35] = lua_g[35] | (lua_t[35] & lua_g[36]);
assign lua_g2[34] = lua_g[34] | (lua_t[34] & lua_g[35]);
assign lua_g2[33] = lua_g[33] | (lua_t[33] & lua_g[34]);
assign lua_g2[32] = lua_g[32] | (lua_t[32] & lua_g[33]);
// lua_t2(38) <= lua_t(38) ;
// lua_t2(37) <= lua_t(37) and lua_t(38) ;
assign lua_t2[36] = lua_t[36] & lua_t[37];
assign lua_t2[35] = lua_t[35] & lua_t[36];
assign lua_t2[34] = lua_t[34] & lua_t[35];
assign lua_t2[33] = lua_t[33] & lua_t[34];
assign lua_t2[32] = lua_t[32] & lua_t[33];
// lua_g4(38) <= lua_g2(38) ;
// lua_g4(37) <= lua_g2(37) ;
assign lua_g4[36] = lua_g2[36] | (lua_t2[36] & lua_g2[38]);
assign lua_g4[35] = lua_g2[35] | (lua_t2[35] & lua_g2[37]);
assign lua_g4[34] = lua_g2[34] | (lua_t2[34] & lua_g2[36]);
assign lua_g4[33] = lua_g2[33] | (lua_t2[33] & lua_g2[35]);
assign lua_g4[32] = lua_g2[32] | (lua_t2[32] & lua_g2[34]);
// lua_t4(38) <= lua_t2(38) ;
// lua_t4(37) <= lua_t2(37) ;
// lua_t4(36) <= lua_t2(36) and lua_t2(38) ;
// lua_t4(35) <= lua_t2(35) and lua_t2(37) ;
// lua_t4(34) <= lua_t2(34) and lua_t2(36) ;
// lua_t4(33) <= lua_t2(33) and lua_t2(35) ;
assign lua_t4[32] = lua_t2[32] & lua_t2[34];
//lua_g8(38) <= lua_g4(38) ;
//lua_g8(37) <= lua_g4(37) ;
//lua_g8(36) <= lua_g4(36) ;
//lua_g8(35) <= lua_g4(35) ;
//lua_g8(34) <= lua_g4(34) or (lua_t4(34) and lua_g4(38) );
//lua_g8(33) <= lua_g4(33) or (lua_t4(33) and lua_g4(37) );
assign lua_g8[32] = lua_g4[32] | (lua_t4[32] & lua_g4[36]);
//lua_t8(38) <= lua_t4(38) ;
//lua_t8(37) <= lua_t4(37) ;
//lua_t8(36) <= lua_t4(36) ;
//lua_t8(35) <= lua_t4(35) ;
//lua_t8(34) <= lua_t4(34) and lua_t4(38) ;
//lua_t8(33) <= lua_t4(33) and lua_t4(37) ;
//lua_t8(32) <= lua_t4(32) and lua_t4(36) ;
assign lua_g2[31] = lua_g[31];
assign lua_g2[30] = lua_g[30] | (lua_t[30] & lua_g[31]);
assign lua_g2[29] = lua_g[29] | (lua_t[29] & lua_g[30]);
assign lua_g2[28] = lua_g[28] | (lua_t[28] & lua_g[29]);
assign lua_g2[27] = lua_g[27] | (lua_t[27] & lua_g[28]);
assign lua_g2[26] = lua_g[26] | (lua_t[26] & lua_g[27]);
assign lua_g2[25] = lua_g[25] | (lua_t[25] & lua_g[26]);
assign lua_g2[24] = lua_g[24] | (lua_t[24] & lua_g[25]);
assign lua_t2[31] = lua_t[31];
assign lua_t2[30] = lua_t[30] & lua_t[31];
assign lua_t2[29] = lua_t[29] & lua_t[30];
assign lua_t2[28] = lua_t[28] & lua_t[29];
assign lua_t2[27] = lua_t[27] & lua_t[28];
assign lua_t2[26] = lua_t[26] & lua_t[27];
assign lua_t2[25] = lua_t[25] & lua_t[26];
assign lua_t2[24] = lua_t[24] & lua_t[25];
assign lua_g4[31] = lua_g2[31];
assign lua_g4[30] = lua_g2[30];
assign lua_g4[29] = lua_g2[29] | (lua_t2[29] & lua_g2[31]);
assign lua_g4[28] = lua_g2[28] | (lua_t2[28] & lua_g2[30]);
assign lua_g4[27] = lua_g2[27] | (lua_t2[27] & lua_g2[29]);
assign lua_g4[26] = lua_g2[26] | (lua_t2[26] & lua_g2[28]);
assign lua_g4[25] = lua_g2[25] | (lua_t2[25] & lua_g2[27]);
assign lua_g4[24] = lua_g2[24] | (lua_t2[24] & lua_g2[26]);
assign lua_t4[31] = lua_t2[31];
assign lua_t4[30] = lua_t2[30];
assign lua_t4[29] = lua_t2[29] & lua_t2[31];
assign lua_t4[28] = lua_t2[28] & lua_t2[30];
assign lua_t4[27] = lua_t2[27] & lua_t2[29];
assign lua_t4[26] = lua_t2[26] & lua_t2[28];
assign lua_t4[25] = lua_t2[25] & lua_t2[27];
assign lua_t4[24] = lua_t2[24] & lua_t2[26];
assign lua_g8[31] = lua_g4[31];
assign lua_g8[30] = lua_g4[30];
assign lua_g8[29] = lua_g4[29];
assign lua_g8[28] = lua_g4[28];
assign lua_g8[27] = lua_g4[27] | (lua_t4[27] & lua_g4[31]);
assign lua_g8[26] = lua_g4[26] | (lua_t4[26] & lua_g4[30]);
assign lua_g8[25] = lua_g4[25] | (lua_t4[25] & lua_g4[29]);
assign lua_g8[24] = lua_g4[24] | (lua_t4[24] & lua_g4[28]);
// lua_t8(31) <= lua_t4(31) ;
// lua_t8(30) <= lua_t4(30) ;
// lua_t8(29) <= lua_t4(29) ;
assign lua_t8[28] = lua_t4[28];
assign lua_t8[27] = lua_t4[27] & lua_t4[31];
assign lua_t8[26] = lua_t4[26] & lua_t4[30];
assign lua_t8[25] = lua_t4[25] & lua_t4[29];
assign lua_t8[24] = lua_t4[24] & lua_t4[28];
assign lua_g2[23] = lua_g[23];
assign lua_g2[22] = lua_g[22] | (lua_t[22] & lua_g[23]);
assign lua_g2[21] = lua_g[21] | (lua_t[21] & lua_g[22]);
assign lua_g2[20] = lua_g[20] | (lua_t[20] & lua_g[21]);
assign lua_g2[19] = lua_g[19] | (lua_t[19] & lua_g[20]);
assign lua_g2[18] = lua_g[18] | (lua_t[18] & lua_g[19]);
assign lua_g2[17] = lua_g[17] | (lua_t[17] & lua_g[18]);
assign lua_g2[16] = lua_g[16] | (lua_t[16] & lua_g[17]);
assign lua_t2[23] = lua_t[23];
assign lua_t2[22] = lua_t[22] & lua_t[23];
assign lua_t2[21] = lua_t[21] & lua_t[22];
assign lua_t2[20] = lua_t[20] & lua_t[21];
assign lua_t2[19] = lua_t[19] & lua_t[20];
assign lua_t2[18] = lua_t[18] & lua_t[19];
assign lua_t2[17] = lua_t[17] & lua_t[18];
assign lua_t2[16] = lua_t[16] & lua_t[17];
assign lua_g4[23] = lua_g2[23];
assign lua_g4[22] = lua_g2[22];
assign lua_g4[21] = lua_g2[21] | (lua_t2[21] & lua_g2[23]);
assign lua_g4[20] = lua_g2[20] | (lua_t2[20] & lua_g2[22]);
assign lua_g4[19] = lua_g2[19] | (lua_t2[19] & lua_g2[21]);
assign lua_g4[18] = lua_g2[18] | (lua_t2[18] & lua_g2[20]);
assign lua_g4[17] = lua_g2[17] | (lua_t2[17] & lua_g2[19]);
assign lua_g4[16] = lua_g2[16] | (lua_t2[16] & lua_g2[18]);
assign lua_t4[23] = lua_t2[23];
assign lua_t4[22] = lua_t2[22];
assign lua_t4[21] = lua_t2[21] & lua_t2[23];
assign lua_t4[20] = lua_t2[20] & lua_t2[22];
assign lua_t4[19] = lua_t2[19] & lua_t2[21];
assign lua_t4[18] = lua_t2[18] & lua_t2[20];
assign lua_t4[17] = lua_t2[17] & lua_t2[19];
assign lua_t4[16] = lua_t2[16] & lua_t2[18];
assign lua_g8[23] = lua_g4[23];
assign lua_g8[22] = lua_g4[22];
assign lua_g8[21] = lua_g4[21];
assign lua_g8[20] = lua_g4[20];
assign lua_g8[19] = lua_g4[19] | (lua_t4[19] & lua_g4[23]);
assign lua_g8[18] = lua_g4[18] | (lua_t4[18] & lua_g4[22]);
assign lua_g8[17] = lua_g4[17] | (lua_t4[17] & lua_g4[21]);
assign lua_g8[16] = lua_g4[16] | (lua_t4[16] & lua_g4[20]);
assign lua_t8[23] = lua_t4[23];
assign lua_t8[22] = lua_t4[22];
assign lua_t8[21] = lua_t4[21];
assign lua_t8[20] = lua_t4[20];
assign lua_t8[19] = lua_t4[19] & lua_t4[23];
assign lua_t8[18] = lua_t4[18] & lua_t4[22];
assign lua_t8[17] = lua_t4[17] & lua_t4[21];
assign lua_t8[16] = lua_t4[16] & lua_t4[20];
assign lua_g2[15] = lua_g[15];
assign lua_g2[14] = lua_g[14] | (lua_t[14] & lua_g[15]);
assign lua_g2[13] = lua_g[13] | (lua_t[13] & lua_g[14]);
assign lua_g2[12] = lua_g[12] | (lua_t[12] & lua_g[13]);
assign lua_g2[11] = lua_g[11] | (lua_t[11] & lua_g[12]);
assign lua_g2[10] = lua_g[10] | (lua_t[10] & lua_g[11]);
assign lua_g2[9] = lua_g[9] | (lua_t[9] & lua_g[10]);
assign lua_g2[8] = lua_g[8] | (lua_t[8] & lua_g[9]);
assign lua_t2[15] = lua_t[15];
assign lua_t2[14] = lua_t[14] & lua_t[15];
assign lua_t2[13] = lua_t[13] & lua_t[14];
assign lua_t2[12] = lua_t[12] & lua_t[13];
assign lua_t2[11] = lua_t[11] & lua_t[12];
assign lua_t2[10] = lua_t[10] & lua_t[11];
assign lua_t2[9] = lua_t[9] & lua_t[10];
assign lua_t2[8] = lua_t[8] & lua_t[9];
assign lua_g4[15] = lua_g2[15];
assign lua_g4[14] = lua_g2[14];
assign lua_g4[13] = lua_g2[13] | (lua_t2[13] & lua_g2[15]);
assign lua_g4[12] = lua_g2[12] | (lua_t2[12] & lua_g2[14]);
assign lua_g4[11] = lua_g2[11] | (lua_t2[11] & lua_g2[13]);
assign lua_g4[10] = lua_g2[10] | (lua_t2[10] & lua_g2[12]);
assign lua_g4[9] = lua_g2[9] | (lua_t2[9] & lua_g2[11]);
assign lua_g4[8] = lua_g2[8] | (lua_t2[8] & lua_g2[10]);
assign lua_t4[15] = lua_t2[15];
assign lua_t4[14] = lua_t2[14];
assign lua_t4[13] = lua_t2[13] & lua_t2[15];
assign lua_t4[12] = lua_t2[12] & lua_t2[14];
assign lua_t4[11] = lua_t2[11] & lua_t2[13];
assign lua_t4[10] = lua_t2[10] & lua_t2[12];
assign lua_t4[9] = lua_t2[9] & lua_t2[11];
assign lua_t4[8] = lua_t2[8] & lua_t2[10];
assign lua_g8[15] = lua_g4[15];
assign lua_g8[14] = lua_g4[14];
assign lua_g8[13] = lua_g4[13];
assign lua_g8[12] = lua_g4[12];
assign lua_g8[11] = lua_g4[11] | (lua_t4[11] & lua_g4[15]);
assign lua_g8[10] = lua_g4[10] | (lua_t4[10] & lua_g4[14]);
assign lua_g8[9] = lua_g4[9] | (lua_t4[9] & lua_g4[13]);
assign lua_g8[8] = lua_g4[8] | (lua_t4[8] & lua_g4[12]);
assign lua_t8[15] = lua_t4[15];
assign lua_t8[14] = lua_t4[14];
assign lua_t8[13] = lua_t4[13];
assign lua_t8[12] = lua_t4[12];
assign lua_t8[11] = lua_t4[11] & lua_t4[15];
assign lua_t8[10] = lua_t4[10] & lua_t4[14];
assign lua_t8[9] = lua_t4[9] & lua_t4[13];
assign lua_t8[8] = lua_t4[8] & lua_t4[12];
assign lua_g2[7] = lua_g[7];
assign lua_g2[6] = lua_g[6] | (lua_t[6] & lua_g[7]);
assign lua_g2[5] = lua_g[5] | (lua_t[5] & lua_g[6]);
assign lua_g2[4] = lua_g[4] | (lua_t[4] & lua_g[5]);
assign lua_g2[3] = lua_g[3] | (lua_t[3] & lua_g[4]);
assign lua_g2[2] = lua_g[2] | (lua_t[2] & lua_g[3]);
assign lua_g2[1] = lua_g[1] | (lua_t[1] & lua_g[2]);
// lua_g2(0) <= lua_g(0) or (lua_t(0) and lua_g(1) );
assign lua_t2[7] = lua_t[7];
assign lua_t2[6] = lua_t[6] & lua_t[7];
assign lua_t2[5] = lua_t[5] & lua_t[6];
assign lua_t2[4] = lua_t[4] & lua_t[5];
assign lua_t2[3] = lua_t[3] & lua_t[4];
assign lua_t2[2] = lua_t[2] & lua_t[3];
assign lua_t2[1] = lua_t[1] & lua_t[2];
// lua_t2(0) <= lua_t(0) and lua_t(1) ;
assign lua_g4[7] = lua_g2[7];
assign lua_g4[6] = lua_g2[6];
assign lua_g4[5] = lua_g2[5] | (lua_t2[5] & lua_g2[7]);
assign lua_g4[4] = lua_g2[4] | (lua_t2[4] & lua_g2[6]);
assign lua_g4[3] = lua_g2[3] | (lua_t2[3] & lua_g2[5]);
assign lua_g4[2] = lua_g2[2] | (lua_t2[2] & lua_g2[4]);
assign lua_g4[1] = lua_g2[1] | (lua_t2[1] & lua_g2[3]);
// lua_g4(0) <= lua_g2(0) or (lua_t2(0) and lua_g2(2) );
assign lua_t4[7] = lua_t2[7];
assign lua_t4[6] = lua_t2[6];
assign lua_t4[5] = lua_t2[5] & lua_t2[7];
assign lua_t4[4] = lua_t2[4] & lua_t2[6];
assign lua_t4[3] = lua_t2[3] & lua_t2[5];
assign lua_t4[2] = lua_t2[2] & lua_t2[4];
assign lua_t4[1] = lua_t2[1] & lua_t2[3];
// lua_t4(0) <= lua_t2(0) and lua_t2(2) ;
assign lua_g8[7] = lua_g4[7];
assign lua_g8[6] = lua_g4[6];
assign lua_g8[5] = lua_g4[5];
assign lua_g8[4] = lua_g4[4];
assign lua_g8[3] = lua_g4[3] | (lua_t4[3] & lua_g4[7]);
assign lua_g8[2] = lua_g4[2] | (lua_t4[2] & lua_g4[6]);
assign lua_g8[1] = lua_g4[1] | (lua_t4[1] & lua_g4[5]);
//lua_g8(0) <= lua_g4(0) or (lua_t4(0) and lua_g4(4) );
assign lua_t8[7] = lua_t4[7];
assign lua_t8[6] = lua_t4[6];
assign lua_t8[5] = lua_t4[5];
assign lua_t8[4] = lua_t4[4];
assign lua_t8[3] = lua_t4[3] & lua_t4[7];
assign lua_t8[2] = lua_t4[2] & lua_t4[6];
assign lua_t8[1] = lua_t4[1] & lua_t4[5];
//lua_t8(0) <= lua_t4(0) and lua_t4(4) ;
// CONDITIONL SUM ---------------------------------------------
assign lua_gt8[1:28] = lua_g8[1:28] | lua_t8[1:28];
assign lua_s1_b[0:27] = (~(lua_p[0:27] ^ lua_gt8[1:28]));
assign lua_s0_b[0:27] = (~(lua_p[0:27] ^ lua_g8[1:28]));
// BYTE SELECT ------------------------------
// ex5_lu(0 to 27) <= not( ex5_lu_p(0 to 27) xor ex5_lu_c(1 to 28) ); -- invert
assign ex5_lu[0] = (lua_s0_b[0] & (~lua_c08)) | (lua_s1_b[0] & lua_c08);
assign ex5_lu[1] = (lua_s0_b[1] & (~lua_c08)) | (lua_s1_b[1] & lua_c08);
assign ex5_lu[2] = (lua_s0_b[2] & (~lua_c08)) | (lua_s1_b[2] & lua_c08);
assign ex5_lu[3] = (lua_s0_b[3] & (~lua_c08)) | (lua_s1_b[3] & lua_c08);
assign ex5_lu[4] = (lua_s0_b[4] & (~lua_c08)) | (lua_s1_b[4] & lua_c08);
assign ex5_lu[5] = (lua_s0_b[5] & (~lua_c08)) | (lua_s1_b[5] & lua_c08);
assign ex5_lu[6] = (lua_s0_b[6] & (~lua_c08)) | (lua_s1_b[6] & lua_c08);
assign ex5_lu[7] = (lua_s0_b[7] & (~lua_c08)) | (lua_s1_b[7] & lua_c08);
assign ex5_lu[8] = (lua_s0_b[8] & (~lua_c16)) | (lua_s1_b[8] & lua_c16);
assign ex5_lu[9] = (lua_s0_b[9] & (~lua_c16)) | (lua_s1_b[9] & lua_c16);
assign ex5_lu[10] = (lua_s0_b[10] & (~lua_c16)) | (lua_s1_b[10] & lua_c16);
assign ex5_lu[11] = (lua_s0_b[11] & (~lua_c16)) | (lua_s1_b[11] & lua_c16);
assign ex5_lu[12] = (lua_s0_b[12] & (~lua_c16)) | (lua_s1_b[12] & lua_c16);
assign ex5_lu[13] = (lua_s0_b[13] & (~lua_c16)) | (lua_s1_b[13] & lua_c16);
assign ex5_lu[14] = (lua_s0_b[14] & (~lua_c16)) | (lua_s1_b[14] & lua_c16);
assign ex5_lu[15] = (lua_s0_b[15] & (~lua_c16)) | (lua_s1_b[15] & lua_c16);
assign ex5_lu[16] = (lua_s0_b[16] & (~lua_c24)) | (lua_s1_b[16] & lua_c24);
assign ex5_lu[17] = (lua_s0_b[17] & (~lua_c24)) | (lua_s1_b[17] & lua_c24);
assign ex5_lu[18] = (lua_s0_b[18] & (~lua_c24)) | (lua_s1_b[18] & lua_c24);
assign ex5_lu[19] = (lua_s0_b[19] & (~lua_c24)) | (lua_s1_b[19] & lua_c24);
assign ex5_lu[20] = (lua_s0_b[20] & (~lua_c24)) | (lua_s1_b[20] & lua_c24);
assign ex5_lu[21] = (lua_s0_b[21] & (~lua_c24)) | (lua_s1_b[21] & lua_c24);
assign ex5_lu[22] = (lua_s0_b[22] & (~lua_c24)) | (lua_s1_b[22] & lua_c24);
assign ex5_lu[23] = (lua_s0_b[23] & (~lua_c24)) | (lua_s1_b[23] & lua_c24);
assign ex5_lu[24] = (lua_s0_b[24] & (~lua_c32)) | (lua_s1_b[24] & lua_c32);
assign ex5_lu[25] = (lua_s0_b[25] & (~lua_c32)) | (lua_s1_b[25] & lua_c32);
assign ex5_lu[26] = (lua_s0_b[26] & (~lua_c32)) | (lua_s1_b[26] & lua_c32);
assign ex5_lu[27] = (lua_s0_b[27] & (~lua_c32)) | (lua_s1_b[27] & lua_c32);
// GLOBAL BYTE CARRY ------------------------------
assign lua_g16[3] = lua_g8[32];
assign lua_g16[2] = lua_g8[24] | (lua_t8[24] & lua_g8[32]);
assign lua_g16[1] = lua_g8[16] | (lua_t8[16] & lua_g8[24]);
assign lua_g16[0] = lua_g8[8] | (lua_t8[8] & lua_g8[16]);
//lua_t16(3) <= lua_t8(32);
//lua_t16(2) <= lua_t8(24) and lua_t8(32) ;
assign lua_t16[1] = lua_t8[16] & lua_t8[24];
assign lua_t16[0] = lua_t8[8] & lua_t8[16];
assign lua_c32 = lua_g16[3];
assign lua_c24 = lua_g16[2];
assign lua_c16 = lua_g16[1] | (lua_t16[1] & lua_g16[3]);
assign lua_c08 = lua_g16[0] | (lua_t16[0] & lua_g16[2]);
//---------------------------------------------------------------
// normalize
//---------------------------------------------------------------
// expo=2046 ==> imp=0 shift right 1
// expo=2045 ==> imp=0 shift right 0
// expo=other => imp=1 shift right 0 <normal reslts>
assign ex5_recip_2044_dp = ex5_recip_2044 & ex5_match_en_dp & (~ex5_recip_ue1);
assign ex5_recip_2045_dp = ex5_recip_2045 & ex5_match_en_dp & (~ex5_recip_ue1);
assign ex5_recip_2046_dp = ex5_recip_2046 & ex5_match_en_dp & (~ex5_recip_ue1);
assign ex5_recip_2044_sp = ex5_recip_2044 & ex5_match_en_sp & (~ex5_recip_ue1);
assign ex5_recip_2045_sp = ex5_recip_2045 & ex5_match_en_sp & (~ex5_recip_ue1);
assign ex5_recip_2046_sp = ex5_recip_2046 & ex5_match_en_sp & (~ex5_recip_ue1);
// lu_sh means : shift left one, and decr exponent (unless it will create a denorm exponent)
// result in norm dp fmt, but set fpscr flag for sp unf
// result in norm dp fmt, but set fpscr flag for sp unf
// result in norm dp fmt, but set fpscr flag for sp unf
assign ex5_recip_den = ex5_recip_2046_sp | ex5_recip_2045_sp | (ex5_lu_sh & ex5_recip_2044_sp) | ex5_recip_2046_dp | ex5_recip_2045_dp | (ex5_lu_sh & ex5_recip_2044_dp); // use in round to set implicit bit
// cannot shift left , denorm result
// by not denormalizing sp the fpscr(ux) is set even though the implicit bit is set
// divide does not want the denormed result
// for setting UX (same for ue=0, ue=1
// ( ex5_match_en_dp) and -- leave SP normalized
assign ex5_unf_expo = (ex5_match_en_sp | ex5_match_en_dp) & (ex5_recip_2046 | ex5_recip_2045 | (ex5_recip_2044 & ex5_lu_sh)); // leave SP normalized
assign f_tbl_ex5_unf_expo = ex5_unf_expo; //output--
assign ex5_shlft_1 = (~ex5_recip_2046_dp) & (~ex5_recip_2045_dp) & (ex5_lu_sh & (~ex5_recip_2044_dp));
assign ex5_shlft_0 = (~ex5_recip_2046_dp) & (~ex5_recip_2045_dp) & (~(ex5_lu_sh & (~ex5_recip_2044_dp)));
assign ex5_shrgt_1 = ex5_recip_2045_dp;
assign ex5_shrgt_2 = ex5_recip_2046_dp;
// the final sp result will be in dp_norm format for an sp_denorm.
// emulate the dropping of bits when an sp is shifted right then fitted into 23 frac bits.
assign ex5_sp_chop_24 = ex5_recip_2046_sp | ex5_recip_2045_sp | ex5_recip_2044_sp;
assign ex5_sp_chop_23 = ex5_recip_2046_sp | ex5_recip_2045_sp;
assign ex5_sp_chop_22 = ex5_recip_2046_sp;
assign ex5_sp_chop_21 = tidn;
assign ex5_lux[0:20] = ex5_lu[0:20];
assign ex5_lux[21] = ex5_lu[21] & (~ex5_sp_chop_21);
assign ex5_lux[22] = ex5_lu[22] & (~ex5_sp_chop_22);
assign ex5_lux[23] = ex5_lu[23] & (~ex5_sp_chop_23);
assign ex5_lux[24] = ex5_lu[24] & (~ex5_sp_chop_24);
assign ex5_lux[25:27] = ex5_lu[25:27];
assign ex5_lu_nrm[0:26] = ({27{ex5_shlft_1}} & (ex5_lux[1:27])) |
({27{ex5_shlft_0}} & (ex5_lux[0:26])) |
({27{ex5_shrgt_1}} & ({tidn, ex5_lux[0:25]})) |
({27{ex5_shrgt_2}} & ({tidn, tidn, ex5_lux[0:24]}));
//==##############################################################
//= ex6 latches
//==##############################################################
tri_rlmreg_p #(.WIDTH(28)) ex6_lut_lat(
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[5]),
.mpw1_b(mpw1_b[5]),
.mpw2_b(mpw2_b[1]),
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(ex5_act),
.thold_b(thold_0_b),
.sg(sg_0),
.scout(ex6_lut_so),
.scin(ex6_lut_si),
//-----------------
.din({ex5_lu_nrm[0:26],
ex5_recip_den}),
.dout({ex6_lu[0:26],
ex6_recip_den})
);
assign f_tbl_ex6_est_frac[0:26] = ex6_lu[0:26];
assign f_tbl_ex6_recip_den = ex6_recip_den;
//==##############################################################
//= pervasive
//==##############################################################
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
//==##############################################################
//= act
//==##############################################################
tri_rlmreg_p #(.WIDTH(7)) act_lat(
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[4]),
.mpw1_b(mpw1_b[4]),
.mpw2_b(mpw2_b[0]),
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(fpu_enable),
.thold_b(thold_0_b),
.sg(sg_0),
.scout(act_so),
.scin(act_si),
//-----------------
.din({spare_unused[0],
spare_unused[1],
ex2_act,
ex3_act,
ex4_act,
spare_unused[2],
spare_unused[3]}),
//-----------------
.dout({ spare_unused[0],
spare_unused[1],
ex3_act,
ex4_act,
ex5_act,
spare_unused[2],
spare_unused[3]})
);
tri_lcbnd tbl_ex4_lcb(
.delay_lclkr(delay_lclkr[3]), // tidn ,--in
.mpw1_b(mpw1_b[3]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in
.nclk(nclk), //in
.vd(vdd), //inout
.gd(gnd), //inout
.act(ex3_act), //in
.sg(sg_0), //in
.thold_b(thold_0_b), //in
.d1clk(tbl_ex4_d1clk), //out
.d2clk(tbl_ex4_d2clk), //out
.lclk(tbl_ex4_lclk) //out
);
tri_lcbnd tbl_ex5_lcb(
.delay_lclkr(delay_lclkr[4]), // tidn ,--in
.mpw1_b(mpw1_b[4]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in
.nclk(nclk), //in
.vd(vdd), //inout
.gd(gnd), //inout
.act(ex4_act), //in
.sg(sg_0), //in
.thold_b(thold_0_b), //in
.d1clk(tbl_ex5_d1clk), //out
.d2clk(tbl_ex5_d2clk), //out
.lclk(tbl_ex5_lclk) //out
);
//==##############################################################
//= scan string
//==##############################################################
assign ex3_lut_si[0:5] = {ex3_lut_so[1:5], si};
assign ex4_lut_e_si[0:19] = {ex4_lut_e_so[1:19], ex3_lut_so[0]};
assign ex4_lut_r_si[0:14] = {ex4_lut_r_so[1:14], ex4_lut_e_so[0]};
assign ex4_lut_b_si[0:15] = {ex4_lut_b_so[1:15], ex4_lut_r_so[0]};
assign ex5_lut_si[0:79] = {ex5_lut_so[1:79], ex4_lut_b_so[0]};
assign ex6_lut_si[0:27] = {ex6_lut_so[1:27], ex5_lut_so[0]};
assign act_si[0:6] = {act_so[1:6], ex6_lut_so[0]};
assign so = act_so[0]; //SCAN
endmodule |
module lq_agen_loca(
x_b,
y_b,
sum_0,
sum_1
);
input [0:7] x_b; // after xor
input [0:7] y_b;
output [0:7] sum_0;
output [0:7] sum_1;
wire [0:7] h01;
wire [0:7] h01_b;
wire [0:7] x;
wire [0:7] y;
wire [1:7] g01_b;
wire [1:7] t01_b;
wire [0:7] p01;
wire [0:7] p01_b;
wire [1:7] g08_b;
wire [1:7] g08;
wire [1:7] g04_b;
wire [1:7] g02;
wire [1:7] t02;
wire [1:7] t04_b;
wire [1:7] t08;
wire [1:7] t08_b;
//####################################################################
//# inverter at top to drive to bit location
//####################################################################
//assign x[0:7] = (~x_b[0:7]); // maybe should be fat wire
tri_inv #(.WIDTH(8)) x_0 (.y(x[0:7]), .a(x_b[0:7]));
//assign y[0:7] = (~y_b[0:7]); // maybe should be fat wire
tri_inv #(.WIDTH(8)) y_0 (.y(y[0:7]), .a(y_b[0:7]));
//####################################################################
//# funny way to make xor
//####################################################################
//assign g01_b[1:7] = (~(x[1:7] & y[1:7]));
tri_nand2 #(.WIDTH(7)) g01_b_1 (.y(g01_b[1:7]), .a(x[1:7]), .b(y[1:7]));
//assign t01_b[1:7] = (~(x[1:7] | y[1:7]));
tri_nor2 #(.WIDTH(7)) t01_b_1 (.y(t01_b[1:7]), .a(x[1:7]), .b(y[1:7]));
//assign p01_b[0:7] = (~(x[0:7] ^ y[0:7]));
tri_xnor2 #(.WIDTH(8)) p01_b_0 (.y(p01_b[0:7]), .a(x[0:7]), .b(y[0:7]));
//assign p01[0:7] = (~(p01_b[0:7]));
tri_inv #(.WIDTH(8)) p01_0 (.y(p01[0:7]), .a(p01_b[0:7]));
//assign h01[0:7] = (~p01_b[0:7]);
tri_inv #(.WIDTH(8)) h01_0 (.y(h01[0:7]), .a(p01_b[0:7]));
//assign h01_b[0:7] = (~p01[0:7]);
tri_inv #(.WIDTH(8)) h01_b_0 (.y(h01_b[0:7]), .a(p01[0:7]));
//####################################################################
//# local carry
//####################################################################
//assign g02[1] = (~(g01_b[1] & (t01_b[1] | g01_b[2])));
tri_oai21 #(.WIDTH(6)) g02_1 (.y(g02[1:6]), .a0(t01_b[1:6]), .a1(g01_b[2:7]), .b0(g01_b[1:6]));
//assign g02[7] = (~(g01_b[7]));
tri_inv g02_7 (.y(g02[7]), .a(g01_b[7]));
//assign t02[1] = (~(t01_b[1] | t01_b[2]));
tri_nor2 #(.WIDTH(5)) t02_1 (.y(t02[1:5]), .a(t01_b[1:5]), .b(t01_b[2:6]));
//assign t02[6] = (~(g01_b[6] & (t01_b[6] | t01_b[7]))); //final--
tri_oai21 t02_6 (.y(t02[6]), .a0(t01_b[6]), .a1(t01_b[7]), .b0(g01_b[6]));
//assign t02[7] = (~(t01_b[7]));
tri_inv t02_7 (.y(t02[7]), .a(t01_b[7]));
//assign g04_b[1] = (~(g02[1] | (t02[1] & g02[3])));
tri_aoi21 #(.WIDTH(5)) g04_b_1 (.y(g04_b[1:5]), .a0(t02[1:5]), .a1(g02[3:7]), .b0(g02[1:5]));
//assign g04_b[6] = (~(g02[6]));
tri_inv #(.WIDTH(2)) g04_b_6 (.y(g04_b[6:7]), .a(g02[6:7]));
//assign t04_b[1] = (~(t02[1] & t02[3]));
tri_nand2 #(.WIDTH(3)) t04_b_1 (.y(t04_b[1:3]), .a(t02[1:3]), .b(t02[3:5]));
//assign t04_b[4] = (~(g02[4] | (t02[4] & t02[6]))); //final--
tri_aoi21 #(.WIDTH(2)) t04_b_4 (.y(t04_b[4:5]), .a0(t02[4:5]), .a1(t02[6:7]), .b0(g02[4:5]));
//assign t04_b[6] = (~(t02[6]));
tri_inv #(.WIDTH(2)) t04_b_6 (.y(t04_b[6:7]), .a(t02[6:7]));
//assign g08[1] = (~(g04_b[1] & (t04_b[1] | g04_b[5]))); //final--
tri_oai21 #(.WIDTH(3)) g08_1 (.y(g08[1:3]), .a0(t04_b[1:3]), .a1(g04_b[5:7]), .b0(g04_b[1:3]));
//assign g08[4] = (~(g04_b[4]));
tri_inv #(.WIDTH(4)) g08_4 (.y(g08[4:7]), .a(g04_b[4:7]));
//assign t08[1] = (~(g04_b[1] & (t04_b[1] | t04_b[5]))); //final--
tri_oai21 #(.WIDTH(3)) t08_1 (.y(t08[1:3]), .a0(t04_b[1:3]), .a1(t04_b[5:7]), .b0(g04_b[1:3]));
//assign t08[4] = (~(t04_b[4]));
tri_inv #(.WIDTH(4)) t08_4 (.y(t08[4:7]), .a(t04_b[4:7]));
//####################################################################
//# conditional sums // may need to make NON-xor implementation
//####################################################################
//assign g08_b[1] = (~g08[1]);
tri_inv #(.WIDTH(7)) g08_b_1 (.y(g08_b[1:7]), .a(g08[1:7]));
//assign t08_b[1] = (~t08[1]);
tri_inv #(.WIDTH(7)) t08_b_1 (.y(t08_b[1:7]), .a(t08[1:7]));
//assign sum_0[0] = (~((h01[0] & g08[1]) | (h01_b[0] & g08_b[1]))); //output--
tri_aoi22 #(.WIDTH(7)) sum_0_0 (.y(sum_0[0:6]), .a0(h01[0:6]), .a1(g08[1:7]), .b0(h01_b[0:6]), .b1(g08_b[1:7]));
//assign sum_0[7] = (~(h01_b[7])); //output--
tri_inv sum_0_7 (.y(sum_0[7]), .a(h01_b[7]));
//assign sum_1[0] = (~((h01[0] & t08[1]) | (h01_b[0] & t08_b[1]))); //output--
tri_aoi22 #(.WIDTH(7)) sum_1_0 (.y(sum_1[0:6]), .a0(h01[0:6]), .a1(t08[1:7]), .b0(h01_b[0:6]), .b1(t08_b[1:7]));
//assign sum_1[7] = (~(h01[7])); //output--
tri_inv sum_1_7 (.y(sum_1[7]), .a(h01[7]));
endmodule |
module rv_axu0_rvs(
`include "tri_a2o.vh"
//------------------------------------------------------------------------------------------------------------
// Instructions from RV_DEP
//------------------------------------------------------------------------------------------------------------
input [0:`THREADS-1] rv0_instr_i0_vld,
input rv0_instr_i0_rte_axu0,
input [0:`THREADS-1] rv0_instr_i1_vld,
input rv0_instr_i1_rte_axu0,
input [0:31] rv0_instr_i0_instr,
input [0:2] rv0_instr_i0_ucode,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag,
input rv0_instr_i0_ord,
input rv0_instr_i0_cord,
input rv0_instr_i0_t1_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t1_p,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t2_p,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t3_p,
input rv0_instr_i0_s1_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s1_p,
input rv0_instr_i0_s2_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s2_p,
input rv0_instr_i0_s3_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s3_p,
input rv0_instr_i0_isStore,
input [0:3] rv0_instr_i0_spare,
input [0:31] rv0_instr_i1_instr,
input [0:2] rv0_instr_i1_ucode,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag,
input rv0_instr_i1_ord,
input rv0_instr_i1_cord,
input rv0_instr_i1_t1_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t1_p,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t2_p,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t3_p,
input rv0_instr_i1_s1_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s1_p,
input rv0_instr_i1_s2_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s2_p,
input rv0_instr_i1_s3_v,
input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s3_p,
input rv0_instr_i1_isStore,
input [0:3] rv0_instr_i1_spare,
input rv0_instr_i0_s1_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag,
input rv0_instr_i0_s2_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag,
input rv0_instr_i0_s3_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag,
input rv0_instr_i1_s1_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag,
input rv0_instr_i1_s2_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag,
input rv0_instr_i1_s3_dep_hit,
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag,
//------------------------------------------------------------------------------------------------------------
// Credit Interface with IU
//------------------------------------------------------------------------------------------------------------
output [0:`THREADS-1] rv_iu_axu0_credit_free,
//------------------------------------------------------------------------------------------------------------
// Machine zap interface
//------------------------------------------------------------------------------------------------------------
input [0:`THREADS-1] cp_flush,
input [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag,
//------------------------------------------------------------------------------------------------------------
// Interface to axu0
//------------------------------------------------------------------------------------------------------------
output [0:`THREADS-1] rv_axu0_vld,
output rv_axu0_s1_v,
output [0:`GPR_POOL_ENC-1] rv_axu0_s1_p,
output rv_axu0_s2_v,
output [0:`GPR_POOL_ENC-1] rv_axu0_s2_p,
output rv_axu0_s3_v,
output [0:`GPR_POOL_ENC-1] rv_axu0_s3_p,
output [0:`ITAG_SIZE_ENC-1] rv_axu0_ex0_itag,
output [0:31] rv_axu0_ex0_instr,
output [0:2] rv_axu0_ex0_ucode,
output rv_axu0_ex0_t1_v,
output [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t1_p,
output [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t2_p,
output [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t3_p,
input axu0_rv_ord_complete,
input axu0_rv_hold_all,
//------------------------------------------------------------------------------------------------------------
// RV Release bus
//------------------------------------------------------------------------------------------------------------
input axu0_rv_ex2_s1_abort,
input axu0_rv_ex2_s2_abort,
input axu0_rv_ex2_s3_abort,
input fx0_rv_ext_itag_abort,
input fx1_rv_ext_itag_abort,
input lq_rv_ext_itag0_abort,
input lq_rv_ext_itag1_abort,
input axu0_rv_itag_abort,
input axu1_rv_itag_abort,
input [0:`THREADS-1] fx0_rv_ext_itag_vld,
input [0:`ITAG_SIZE_ENC-1] fx0_rv_ext_itag,
input [0:`THREADS-1] fx1_rv_ext_itag_vld,
input [0:`ITAG_SIZE_ENC-1] fx1_rv_ext_itag,
input [0:`THREADS-1] axu0_rv_itag_vld,
input [0:`ITAG_SIZE_ENC-1] axu0_rv_itag,
input [0:`THREADS-1] axu1_rv_itag_vld,
input [0:`ITAG_SIZE_ENC-1] axu1_rv_itag,
input [0:`THREADS-1] lq_rv_ext_itag0_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag0,
input [0:`THREADS-1] lq_rv_itag1_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1,
input lq_rv_itag1_restart,
input lq_rv_itag1_hold,
input [0:`THREADS-1] lq_rv_ext_itag1_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag1,
input [0:`THREADS-1] lq_rv_ext_itag2_vld,
input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag2,
input [0:`THREADS-1] lq_rv_clr_hold,
output [0:`THREADS-1] axu0_rv_ext_itag_vld,
output axu0_rv_ext_itag_abort,
output [0:`ITAG_SIZE_ENC-1] axu0_rv_ext_itag,
//------------------------------------------------------------------------------------------------------------
// Pervasive
//------------------------------------------------------------------------------------------------------------
output [0:8*`THREADS-1] axu0_rvs_perf_bus,
output [0:31] axu0_rvs_dbg_bus,
inout vdd,
inout gnd,
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk
input [0:`NCLK_WIDTH-1] nclk,
input func_sl_thold_1,
input sg_1,
input clkoff_b,
input act_dis,
input ccflush_dc,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input scan_in,
output scan_out
);
parameter num_itag_busses_g = 7;
//------------------------------------------------------------------------------------------------------------
// RV AXU0 RVS INSTR ISSUE
//------------------------------------------------------------------------------------------------------------
parameter rvaxu0_ex0_start = 0;
parameter rvaxu0_instr_start = rvaxu0_ex0_start;
parameter rvaxu0_instr_stop = (rvaxu0_instr_start + (32)) - 1;
parameter rvaxu0_ucode_start = rvaxu0_instr_stop + 1;
parameter rvaxu0_ucode_stop = (rvaxu0_ucode_start + (3)) - 1;
parameter rvaxu0_t1_v_start = rvaxu0_ucode_stop + 1;
parameter rvaxu0_t1_v_stop = (rvaxu0_t1_v_start + (1)) - 1;
parameter rvaxu0_t1_p_start = rvaxu0_t1_v_stop + 1;
parameter rvaxu0_t1_p_stop = (rvaxu0_t1_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvaxu0_t2_p_start = rvaxu0_t1_p_stop + 1;
parameter rvaxu0_t2_p_stop = (rvaxu0_t2_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvaxu0_t3_p_start = rvaxu0_t2_p_stop + 1;
parameter rvaxu0_t3_p_stop = (rvaxu0_t3_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvaxu0_spare_start = rvaxu0_t3_p_stop + 1;
parameter rvaxu0_spare_stop = (rvaxu0_spare_start + (4)) - 1;
parameter rvaxu0_ex0_end = rvaxu0_spare_stop;
parameter rvaxu0_ex0_size = rvaxu0_ex0_end + 1;
parameter rvaxu0_start = 0;
parameter rvaxu0_s1_v_start = rvaxu0_start;
parameter rvaxu0_s1_v_stop = (rvaxu0_s1_v_start + (1)) - 1;
parameter rvaxu0_s1_p_start = rvaxu0_s1_v_stop + 1;
parameter rvaxu0_s1_p_stop = (rvaxu0_s1_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvaxu0_s2_v_start = rvaxu0_s1_p_stop + 1;
parameter rvaxu0_s2_v_stop = (rvaxu0_s2_v_start + (1)) - 1;
parameter rvaxu0_s2_p_start = rvaxu0_s2_v_stop + 1;
parameter rvaxu0_s2_p_stop = (rvaxu0_s2_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvaxu0_s3_v_start = rvaxu0_s2_p_stop + 1;
parameter rvaxu0_s3_v_stop = (rvaxu0_s3_v_start + (1)) - 1;
parameter rvaxu0_s3_p_start = rvaxu0_s3_v_stop + 1;
parameter rvaxu0_s3_p_stop = (rvaxu0_s3_p_start + (`GPR_POOL_ENC)) - 1;
parameter rvaxu0_end = rvaxu0_s3_p_stop;
parameter rvaxu0_size = rvaxu0_end + 1;
//------------------------------------------------------------------------------------------------------------
// Pervasive
//------------------------------------------------------------------------------------------------------------
wire tiup;
wire [0:`THREADS-1] cp_flush_q;
//------------------------------------------------------------------------------------------------------------
// RV0
//------------------------------------------------------------------------------------------------------------
wire rv0_instr_i0_rte;
wire rv0_instr_i1_rte;
//------------------------------------------------------------------------------------------------------------
// RV1
//------------------------------------------------------------------------------------------------------------
wire [rvaxu0_start:rvaxu0_end] rv0_instr_i0_dat;
wire [rvaxu0_start:rvaxu0_end] rv0_instr_i1_dat;
wire [rvaxu0_ex0_start:rvaxu0_ex0_end] rv0_instr_i0_dat_ex0;
wire [rvaxu0_ex0_start:rvaxu0_ex0_end] rv0_instr_i1_dat_ex0;
wire rv0_instr_i0_spec;
wire rv0_instr_i1_spec;
wire rv0_instr_i0_is_brick;
wire [0:2] rv0_instr_i0_brick;
wire [0:3] rv0_instr_i0_ilat;
wire rv0_instr_i1_is_brick;
wire [0:2] rv0_instr_i1_brick;
wire [0:3] rv0_instr_i1_ilat;
wire rv0_i0_s1_v;
wire rv0_i0_s2_v;
wire rv0_i1_s1_v;
wire rv0_i1_s2_v;
wire rv0_i0_s1_dep_hit;
wire rv0_i0_s2_dep_hit;
wire rv0_i1_s1_dep_hit;
wire rv0_i1_s2_dep_hit;
//------------------------------------------------------------------------------------------------------------
// RV2
//------------------------------------------------------------------------------------------------------------
wire [0:`THREADS-1] rv1_other_ilat0_vld;
wire [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag;
wire [rvaxu0_start:rvaxu0_end] rv1_instr_dat;
wire [0:`THREADS-1] rv1_instr_v;
wire rv1_instr_ord;
(* analysis_not_referenced="true" *)
wire rv1_instr_spec;
wire [0:`ITAG_SIZE_ENC-1] rv1_instr_itag;
(* analysis_not_referenced="true" *)
wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s1_itag;
(* analysis_not_referenced="true" *)
wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s2_itag;
(* analysis_not_referenced="true" *)
wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s3_itag;
(* analysis_not_referenced="<54:57>true" *)
wire [rvaxu0_ex0_start:rvaxu0_ex0_end] ex0_instr_dat;
wire [0:`THREADS-1] ex1_credit_free;
wire ex0_ord_d;
wire ex0_ord_q;
wire [0:`THREADS-1] ex1_ord_vld_d;
wire [0:`THREADS-1] ex1_ord_vld_q;
wire [0:`THREADS-1] ex2_ord_vld_d;
wire [0:`THREADS-1] ex2_ord_vld_q;
wire [0:`THREADS-1] ex3_ord_flush_d;
wire [0:`THREADS-1] ex3_ord_flush_q;
//------------------------------------------------------------------------------------------------------------
// EX0
//------------------------------------------------------------------------------------------------------------
wire rv_ex0_act;
wire [0:`THREADS-1] ex0_vld_d;
wire [0:`ITAG_SIZE_ENC-1] ex0_itag_d;
wire [0:`THREADS-1] ex0_vld_q;
wire [0:`ITAG_SIZE_ENC-1] ex0_itag_q;
//------------------------------------------------------------------------------------------------------------
// Itag busses and shadow
//------------------------------------------------------------------------------------------------------------
wire [0:`THREADS-1] lq_rv_itag1_rst_vld;
wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst;
wire [0:`THREADS-1] q_ord_complete;
wire [0:`THREADS-1] ex3_ord_flush;
wire lq_rv_itag1_cord;
wire [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag_q;
//------------------------------------------------------------------------------------------------------------
// Scan Chains
//------------------------------------------------------------------------------------------------------------
parameter rvs_offset = 0 + 0;
parameter cp_flush_offset = rvs_offset + 1;
parameter ex0_ord_offset = cp_flush_offset + `THREADS;
parameter ex1_ord_vld_offset = ex0_ord_offset + 1;
parameter ex2_ord_vld_offset = ex1_ord_vld_offset + `THREADS;
parameter ex3_ord_flush_offset = ex2_ord_vld_offset + `THREADS;
parameter ex0_vld_offset = ex3_ord_flush_offset + `THREADS;
parameter ex0_itag_offset = ex0_vld_offset + `THREADS;
parameter axu0_rv_itag_vld_offset = ex0_itag_offset + `ITAG_SIZE_ENC;
parameter axu0_rv_itag_abort_offset = axu0_rv_itag_vld_offset + `THREADS;
parameter axu0_rv_itag_offset = axu0_rv_itag_abort_offset + 1;
parameter cp_next_itag_offset = axu0_rv_itag_offset + `ITAG_SIZE_ENC;
parameter scan_right = cp_next_itag_offset + `THREADS * `ITAG_SIZE_ENC;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
wire func_sl_thold_0;
wire func_sl_thold_0_b;
wire sg_0;
wire force_t;
//unused
(* analysis_not_referenced="true" *)
wire [0:`THREADS-1] q_ord_tid;
(* analysis_not_referenced="true" *)
wire [0:`THREADS-1] rv1_other_ilat0_vld_out;
(* analysis_not_referenced="true" *)
wire [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag_out;
(* analysis_not_referenced="true" *)
wire [0:3] rv1_instr_ilat;
(* analysis_not_referenced="true" *)
wire [0:`THREADS-1] rv1_instr_ilat0_vld;
(* analysis_not_referenced="true" *)
wire [0:`THREADS-1] rv1_instr_ilat1_vld;
(* analysis_not_referenced="true" *)
wire rvs_empty;
(* analysis_not_referenced="true" *)
wire rv1_instr_is_brick;
//------------------------------------------------------------------------------------------------------------
// Pervasive
//------------------------------------------------------------------------------------------------------------
assign tiup = 1'b1;
//------------------------------------------------------------------------------------------------------------
// RV Entry
//------------------------------------------------------------------------------------------------------------
//Don't hit on cracked store GPR valids
assign rv0_i0_s1_v = rv0_instr_i0_s1_v & ~rv0_instr_i0_isStore;
assign rv0_i0_s2_v = rv0_instr_i0_s2_v & ~rv0_instr_i0_isStore;
assign rv0_i0_s1_dep_hit = rv0_instr_i0_s1_dep_hit & ~rv0_instr_i0_isStore;
assign rv0_i0_s2_dep_hit = rv0_instr_i0_s2_dep_hit & ~rv0_instr_i0_isStore;
assign rv0_i1_s1_v = rv0_instr_i1_s1_v & ~rv0_instr_i1_isStore;
assign rv0_i1_s2_v = rv0_instr_i1_s2_v & ~rv0_instr_i1_isStore;
assign rv0_i1_s1_dep_hit = rv0_instr_i1_s1_dep_hit & ~rv0_instr_i1_isStore;
assign rv0_i1_s2_dep_hit = rv0_instr_i1_s2_dep_hit & ~rv0_instr_i1_isStore;
assign rv0_instr_i0_dat = {
rv0_i0_s1_v,
rv0_instr_i0_s1_p,
rv0_i0_s2_v,
rv0_instr_i0_s2_p,
rv0_instr_i0_s3_v,
rv0_instr_i0_s3_p};
assign rv0_instr_i0_dat_ex0 = {rv0_instr_i0_instr,
rv0_instr_i0_ucode,
rv0_instr_i0_t1_v,
rv0_instr_i0_t1_p,
rv0_instr_i0_t2_p,
rv0_instr_i0_t3_p,
rv0_instr_i0_spare};
assign rv0_instr_i1_dat = {
rv0_i1_s1_v,
rv0_instr_i1_s1_p,
rv0_i1_s2_v,
rv0_instr_i1_s2_p,
rv0_instr_i1_s3_v,
rv0_instr_i1_s3_p};
assign rv0_instr_i1_dat_ex0 = {rv0_instr_i1_instr,
rv0_instr_i1_ucode,
rv0_instr_i1_t1_v,
rv0_instr_i1_t1_p,
rv0_instr_i1_t2_p,
rv0_instr_i1_t3_p,
rv0_instr_i1_spare};
//------------------------------------------------------------------------------------------------------------
// axu0 Reservation Stations
//------------------------------------------------------------------------------------------------------------
assign rv0_instr_i0_spec = 1'b0;
assign rv0_instr_i0_is_brick = 1'b0;
assign rv0_instr_i0_brick = {3{1'b0}};
assign rv0_instr_i0_ilat = {4{1'b1}};
assign rv0_instr_i1_spec = 1'b0;
assign rv0_instr_i1_is_brick = 1'b0;
assign rv0_instr_i1_brick = {3{1'b0}};
assign rv0_instr_i1_ilat = {4{1'b1}};
assign lq_rv_itag1_cord = 1'b0;
assign rv1_other_ilat0_vld = {`THREADS{1'b0}};
assign rv1_other_ilat0_itag = {`ITAG_SIZE_ENC{1'b0}};
assign q_ord_complete = {`THREADS{axu0_rv_ord_complete}} | ex3_ord_flush;
assign rv0_instr_i0_rte = rv0_instr_i0_rte_axu0;
assign rv0_instr_i1_rte = rv0_instr_i1_rte_axu0;
rv_station #(.q_dat_width_g(rvaxu0_size), .q_dat_ex0_width_g(rvaxu0_ex0_size), .q_num_entries_g(`RV_AXU0_ENTRIES), .q_itag_busses_g(num_itag_busses_g), .q_noilat0_g(1'b1), .q_brick_g(1'b0))
rvs(
.cp_flush(cp_flush),
.cp_next_itag(cp_next_itag_q),
.rv0_instr_i0_vld(rv0_instr_i0_vld),
.rv0_instr_i0_rte(rv0_instr_i0_rte),
.rv0_instr_i1_vld(rv0_instr_i1_vld),
.rv0_instr_i1_rte(rv0_instr_i1_rte),
.rv0_instr_i0_dat(rv0_instr_i0_dat),
.rv0_instr_i0_dat_ex0(rv0_instr_i0_dat_ex0),
.rv0_instr_i0_itag(rv0_instr_i0_itag),
.rv0_instr_i0_ord(rv0_instr_i0_ord),
.rv0_instr_i0_cord(rv0_instr_i0_cord),
.rv0_instr_i0_spec(rv0_instr_i0_spec),
.rv0_instr_i0_s1_dep_hit(rv0_i0_s1_dep_hit),
.rv0_instr_i0_s1_itag(rv0_instr_i0_s1_itag),
.rv0_instr_i0_s2_dep_hit(rv0_i0_s2_dep_hit),
.rv0_instr_i0_s2_itag(rv0_instr_i0_s2_itag),
.rv0_instr_i0_s3_dep_hit(rv0_instr_i0_s3_dep_hit),
.rv0_instr_i0_s3_itag(rv0_instr_i0_s3_itag),
.rv0_instr_i0_is_brick(rv0_instr_i0_is_brick),
.rv0_instr_i0_brick(rv0_instr_i0_brick),
.rv0_instr_i0_ilat(rv0_instr_i0_ilat),
.rv0_instr_i0_s1_v(rv0_i0_s1_v),
.rv0_instr_i0_s2_v(rv0_i0_s2_v),
.rv0_instr_i0_s3_v(rv0_instr_i0_s3_v),
.rv0_instr_i1_dat(rv0_instr_i1_dat),
.rv0_instr_i1_dat_ex0(rv0_instr_i1_dat_ex0),
.rv0_instr_i1_itag(rv0_instr_i1_itag),
.rv0_instr_i1_ord(rv0_instr_i1_ord),
.rv0_instr_i1_cord(rv0_instr_i1_cord),
.rv0_instr_i1_spec(rv0_instr_i1_spec),
.rv0_instr_i1_s1_dep_hit(rv0_i1_s1_dep_hit),
.rv0_instr_i1_s1_itag(rv0_instr_i1_s1_itag),
.rv0_instr_i1_s2_dep_hit(rv0_i1_s2_dep_hit),
.rv0_instr_i1_s2_itag(rv0_instr_i1_s2_itag),
.rv0_instr_i1_s3_dep_hit(rv0_instr_i1_s3_dep_hit),
.rv0_instr_i1_s3_itag(rv0_instr_i1_s3_itag),
.rv0_instr_i1_is_brick(rv0_instr_i1_is_brick),
.rv0_instr_i1_brick(rv0_instr_i1_brick),
.rv0_instr_i1_ilat(rv0_instr_i1_ilat),
.rv0_instr_i1_s1_v(rv0_i1_s1_v),
.rv0_instr_i1_s2_v(rv0_i1_s2_v),
.rv0_instr_i1_s3_v(rv0_instr_i1_s3_v),
.rv1_instr_vld(rv1_instr_v),
.rv1_instr_dat(rv1_instr_dat),
.rv1_instr_ord(rv1_instr_ord),
.rv1_instr_spec(rv1_instr_spec),
.rv1_instr_itag(rv1_instr_itag),
.rv1_instr_s1_itag(rv1_instr_s1_itag),
.rv1_instr_s2_itag(rv1_instr_s2_itag),
.rv1_instr_s3_itag(rv1_instr_s3_itag),
.rv1_instr_is_brick(rv1_instr_is_brick),
.ex0_instr_dat(ex0_instr_dat),
.ex1_credit_free(ex1_credit_free),
.rv1_other_ilat0_vld(rv1_other_ilat0_vld),
.rv1_other_ilat0_itag(rv1_other_ilat0_itag),
.q_ord_tid(q_ord_tid),
.rv1_other_ilat0_vld_out(rv1_other_ilat0_vld_out),
.rv1_other_ilat0_itag_out(rv1_other_ilat0_itag_out),
.rv1_instr_ilat(rv1_instr_ilat),
.rv1_instr_ilat0_vld(rv1_instr_ilat0_vld),
.rv1_instr_ilat1_vld(rv1_instr_ilat1_vld),
.rvs_empty(rvs_empty),
.rvs_perf_bus(axu0_rvs_perf_bus),
.rvs_dbg_bus(axu0_rvs_dbg_bus),
.q_hold_all(axu0_rv_hold_all),
.q_ord_complete(q_ord_complete),
.fx0_rv_itag (fx0_rv_ext_itag),
.fx1_rv_itag (fx1_rv_ext_itag),
.lq_rv_itag0 (lq_rv_ext_itag0),
.lq_rv_itag1 (lq_rv_ext_itag1),
.lq_rv_itag2 (lq_rv_ext_itag2),
.axu0_rv_itag (axu0_rv_itag),
.axu1_rv_itag (axu1_rv_itag),
.fx0_rv_itag_vld (fx0_rv_ext_itag_vld),
.fx1_rv_itag_vld (fx1_rv_ext_itag_vld),
.lq_rv_itag0_vld (lq_rv_ext_itag0_vld),
.lq_rv_itag1_vld (lq_rv_ext_itag1_vld),
.lq_rv_itag2_vld (lq_rv_ext_itag2_vld),
.axu0_rv_itag_vld (axu0_rv_itag_vld),
.axu1_rv_itag_vld (axu1_rv_itag_vld),
.fx0_rv_itag_abort (fx0_rv_ext_itag_abort),
.fx1_rv_itag_abort (fx1_rv_ext_itag_abort),
.lq_rv_itag0_abort (lq_rv_ext_itag0_abort),
.lq_rv_itag1_abort (lq_rv_ext_itag1_abort),
.axu0_rv_itag_abort (axu0_rv_itag_abort),
.axu1_rv_itag_abort (axu1_rv_itag_abort),
.xx_rv_ex2_s1_abort(axu0_rv_ex2_s1_abort),
.xx_rv_ex2_s2_abort(axu0_rv_ex2_s2_abort),
.xx_rv_ex2_s3_abort(axu0_rv_ex2_s3_abort),
.lq_rv_itag1_restart(lq_rv_itag1_restart),
.lq_rv_itag1_hold(lq_rv_itag1_hold),
.lq_rv_itag1_cord(lq_rv_itag1_cord),
.lq_rv_itag1_rst_vld(lq_rv_itag1_rst_vld),
.lq_rv_itag1_rst(lq_rv_itag1_rst),
.lq_rv_clr_hold(lq_rv_clr_hold),
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.sg_1(sg_1),
.func_sl_thold_1(func_sl_thold_1),
.ccflush_dc(ccflush_dc),
.act_dis(act_dis),
.clkoff_b(clkoff_b),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scan_in(siv[rvs_offset]),
.scan_out(sov[rvs_offset])
);
assign rv_iu_axu0_credit_free = ex1_credit_free;
assign rv_axu0_vld = rv1_instr_v;
assign rv_axu0_s1_v = rv1_instr_dat[rvaxu0_s1_v_start];
assign rv_axu0_s1_p = rv1_instr_dat[rvaxu0_s1_p_start:rvaxu0_s1_p_stop];
assign rv_axu0_s2_v = rv1_instr_dat[rvaxu0_s2_v_start];
assign rv_axu0_s2_p = rv1_instr_dat[rvaxu0_s2_p_start:rvaxu0_s2_p_stop];
assign rv_axu0_s3_v = rv1_instr_dat[rvaxu0_s3_v_start];
assign rv_axu0_s3_p = rv1_instr_dat[rvaxu0_s3_p_start:rvaxu0_s3_p_stop];
assign ex0_vld_d = rv1_instr_v & (~cp_flush_q);
assign ex0_itag_d = rv1_instr_itag;
assign rv_axu0_ex0_instr = ex0_instr_dat[rvaxu0_instr_start:rvaxu0_instr_stop];
assign rv_axu0_ex0_ucode = ex0_instr_dat[rvaxu0_ucode_start:rvaxu0_ucode_stop];
assign rv_axu0_ex0_t1_v = ex0_instr_dat[rvaxu0_t1_v_start];
assign rv_axu0_ex0_t1_p = ex0_instr_dat[rvaxu0_t1_p_start:rvaxu0_t1_p_stop];
assign rv_axu0_ex0_t2_p = ex0_instr_dat[rvaxu0_t2_p_start:rvaxu0_t2_p_stop];
assign rv_axu0_ex0_t3_p = ex0_instr_dat[rvaxu0_t3_p_start:rvaxu0_t3_p_stop];
assign rv_ex0_act = |(rv1_instr_v);
assign rv_axu0_ex0_itag = ex0_itag_q;
//------------------------------------------------------------------------------------------------------------
// Itag busses
//------------------------------------------------------------------------------------------------------------
// Restart Itag and Valid from LQ. This is separate because it could be early (not latched)
assign lq_rv_itag1_rst_vld = lq_rv_itag1_vld;
assign lq_rv_itag1_rst = lq_rv_itag1;
assign ex0_ord_d = rv1_instr_ord;
assign ex1_ord_vld_d = {`THREADS{ex0_ord_q}} & ex0_vld_q & (~cp_flush_q);
assign ex2_ord_vld_d = ex1_ord_vld_q & (~cp_flush_q);
assign ex3_ord_flush_d = ex2_ord_vld_q & {`THREADS{(axu0_rv_ex2_s1_abort | axu0_rv_ex2_s2_abort | axu0_rv_ex2_s3_abort )}} ;
assign ex3_ord_flush = ex3_ord_flush_q & (~cp_flush_q);
//------------------------------------------------------------------------------------------------------------
// Pipeline Latches
//------------------------------------------------------------------------------------------------------------
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]),
.scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]),
.din(cp_flush),
.dout(cp_flush_q)
);
tri_rlmlatch_p #(.INIT(0)) ex0_ord_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rv_ex0_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex0_ord_offset]),
.scout(sov[ex0_ord_offset]),
.din(ex0_ord_d),
.dout(ex0_ord_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex1_ord_vld_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex1_ord_vld_offset:ex1_ord_vld_offset + `THREADS - 1]),
.scout(sov[ex1_ord_vld_offset:ex1_ord_vld_offset + `THREADS - 1]),
.din(ex1_ord_vld_d),
.dout(ex1_ord_vld_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex2_ord_vld_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex2_ord_vld_offset:ex2_ord_vld_offset + `THREADS - 1]),
.scout(sov[ex2_ord_vld_offset:ex2_ord_vld_offset + `THREADS - 1]),
.din(ex2_ord_vld_d),
.dout(ex2_ord_vld_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex3_ord_flush_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex3_ord_flush_offset:ex3_ord_flush_offset + `THREADS - 1]),
.scout(sov[ex3_ord_flush_offset:ex3_ord_flush_offset + `THREADS - 1]),
.din(ex3_ord_flush_d),
.dout(ex3_ord_flush_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex0_vld_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex0_vld_offset:ex0_vld_offset + `THREADS - 1]),
.scout(sov[ex0_vld_offset:ex0_vld_offset + `THREADS - 1]),
.din(ex0_vld_d),
.dout(ex0_vld_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex0_itag_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(rv_ex0_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]),
.scout(sov[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]),
.din(ex0_itag_d),
.dout(ex0_itag_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) axu0_rv_itag_vld_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[axu0_rv_itag_vld_offset:axu0_rv_itag_vld_offset + `THREADS - 1]),
.scout(sov[axu0_rv_itag_vld_offset:axu0_rv_itag_vld_offset + `THREADS - 1]),
.din(axu0_rv_itag_vld),
.dout(axu0_rv_ext_itag_vld)
);
tri_rlmlatch_p #( .INIT(0)) axu0_rv_itag_abort_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[axu0_rv_itag_abort_offset]),
.scout(sov[axu0_rv_itag_abort_offset]),
.din(axu0_rv_itag_abort),
.dout(axu0_rv_ext_itag_abort)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) axu0_rv_itag_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[axu0_rv_itag_offset:axu0_rv_itag_offset + `ITAG_SIZE_ENC - 1]),
.scout(sov[axu0_rv_itag_offset:axu0_rv_itag_offset + `ITAG_SIZE_ENC - 1]),
.din(axu0_rv_itag),
.dout(axu0_rv_ext_itag)
);
/*
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_itag0_vld_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[lq_rv_itag0_vld_offset:lq_rv_itag0_vld_offset + `THREADS - 1]),
.scout(sov[lq_rv_itag0_vld_offset:lq_rv_itag0_vld_offset + `THREADS - 1]),
.din(lq_rv_itag0_vld_d),
.dout(lq_rv_itag0_vld_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_itag0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[lq_rv_itag0_offset:lq_rv_itag0_offset + `ITAG_SIZE_ENC - 1]),
.scout(sov[lq_rv_itag0_offset:lq_rv_itag0_offset + `ITAG_SIZE_ENC - 1]),
.din(lq_rv_itag0),
.dout(lq_rv_itag0_q)
);
tri_rlmlatch_p #(.INIT(0)) lq_rv_itag0_spec_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[lq_rv_itag0_spec_offset]),
.scout(sov[lq_rv_itag0_spec_offset]),
.din(lq_rv_itag0_spec),
.dout(lq_rv_itag0_spec_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_itag1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[lq_rv_itag1_offset:lq_rv_itag1_offset + `ITAG_SIZE_ENC - 1]),
.scout(sov[lq_rv_itag1_offset:lq_rv_itag1_offset + `ITAG_SIZE_ENC - 1]),
.din(lq_rv_itag1),
.dout(lq_rv_itag1_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_itag2_vld_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[lq_rv_itag2_vld_offset:lq_rv_itag2_vld_offset + `THREADS - 1]),
.scout(sov[lq_rv_itag2_vld_offset:lq_rv_itag2_vld_offset + `THREADS - 1]),
.din(lq_rv_itag2_vld_d),
.dout(lq_rv_itag2_vld_q)
);
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_itag2_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[lq_rv_itag2_offset:lq_rv_itag2_offset + `ITAG_SIZE_ENC - 1]),
.scout(sov[lq_rv_itag2_offset:lq_rv_itag2_offset + `ITAG_SIZE_ENC - 1]),
.din(lq_rv_itag2),
.dout(lq_rv_itag2_q)
);
*/
tri_rlmreg_p #(.WIDTH(`THREADS*`ITAG_SIZE_ENC), .INIT(0))
cp_next_itag_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[cp_next_itag_offset :cp_next_itag_offset + `THREADS*`ITAG_SIZE_ENC-1]),
.scout(sov[cp_next_itag_offset:cp_next_itag_offset + `THREADS*`ITAG_SIZE_ENC-1]),
.din(cp_next_itag),
.dout(cp_next_itag_q)
);
//------------------------------------------------------------------------------------------------------------
// Scan Connections
//------------------------------------------------------------------------------------------------------------
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
//-----------------------------------------------
// pervasive
//-----------------------------------------------
tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_dc),
.din({func_sl_thold_1, sg_1}),
.q({func_sl_thold_0, sg_0})
);
tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b),
.thold(func_sl_thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(func_sl_thold_0_b)
);
endmodule // rv_axu0_rvs |
module xu0_dlmzb(
// Inputs
input [32:63] byp_dlm_ex2_rs1,
input [32:63] byp_dlm_ex2_rs2,
input [0:2] byp_dlm_ex2_xer,
// Outputs
output [0:9] dlm_byp_ex2_xer,
output [0:3] dlm_byp_ex2_cr,
output [60:63] dlm_byp_ex2_rt
);
wire [0:7] a;
wire [0:7] a0;
wire [0:7] a1;
wire [0:7] a2;
wire [0:3] y;
// Null == 0
assign a[0] = |(byp_dlm_ex2_rs1[32:39]);
assign a[1] = |(byp_dlm_ex2_rs1[40:47]);
assign a[2] = |(byp_dlm_ex2_rs1[48:55]);
assign a[3] = |(byp_dlm_ex2_rs1[56:63]);
assign a[4] = |(byp_dlm_ex2_rs2[32:39]);
assign a[5] = |(byp_dlm_ex2_rs2[40:47]);
assign a[6] = |(byp_dlm_ex2_rs2[48:55]);
assign a[7] = |(byp_dlm_ex2_rs2[56:63]);
assign a0[1:7] = a[0:6] & a[1:7];
assign a1[2:7] = a0[0:5] & a0[2:7];
assign a2[4:7] = a1[0:3] & a1[4:7];
assign a0[0:0] = a[0:0];
assign a1[0:1] = a0[0:1];
assign a2[0:3] = a1[0:3];
assign y = (a2[0:7] == 8'b00000000) ? 4'b0001 : // Null in last 4B
(a2[0:7] == 8'b10000000) ? 4'b0010 :
(a2[0:7] == 8'b11000000) ? 4'b0011 :
(a2[0:7] == 8'b11100000) ? 4'b0100 :
(a2[0:7] == 8'b11110000) ? 4'b0101 :
(a2[0:7] == 8'b11111000) ? 4'b0110 :
(a2[0:7] == 8'b11111100) ? 4'b0111 :
4'b1000;
assign dlm_byp_ex2_cr[0] = (~a2[7]) & a2[3];
assign dlm_byp_ex2_cr[1] = (~a2[7]) & (~a2[3]); // Null in first 4B
assign dlm_byp_ex2_cr[2] = a2[7]; // Null not found
assign dlm_byp_ex2_cr[3] = byp_dlm_ex2_xer[0]; // SO Copy
assign dlm_byp_ex2_xer = {byp_dlm_ex2_xer[0:2], 3'b000, y[0:3]};
assign dlm_byp_ex2_rt = y;
endmodule |
module fu_alg_bypmux(
ex3_byp_sel_byp_neg,
ex3_byp_sel_byp_pos,
ex3_byp_sel_neg,
ex3_byp_sel_pos,
ex3_prd_sel_neg_hi,
ex3_prd_sel_neg_lo,
ex3_prd_sel_neg_lohi,
ex3_prd_sel_pos_hi,
ex3_prd_sel_pos_lo,
ex3_prd_sel_pos_lohi,
ex3_sh_lvl3,
f_fmt_ex3_pass_frac,
f_alg_ex3_res
);
//--------- BYPASS CONTROLS -----------------
input ex3_byp_sel_byp_neg;
input ex3_byp_sel_byp_pos;
input ex3_byp_sel_neg;
input ex3_byp_sel_pos;
input ex3_prd_sel_neg_hi;
input ex3_prd_sel_neg_lo;
input ex3_prd_sel_neg_lohi;
input ex3_prd_sel_pos_hi;
input ex3_prd_sel_pos_lo;
input ex3_prd_sel_pos_lohi;
//--------- BYPASS DATA -----------------
input [0:162] ex3_sh_lvl3;
input [0:52] f_fmt_ex3_pass_frac;
//-------- BYPASS OUTPUT ---------------
output [0:162] f_alg_ex3_res;
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:162] m0_b;
wire [0:162] m1_b;
wire [0:162] ex3_sh_lvl3_b;
wire [0:52] f_fmt_ex3_pass_frac_b;
//#-------------------------------------------------
//# bypass mux & operand flip
//#-------------------------------------------------
//# integer operation positions
//# 32 32
//# 99:130 131:162
assign ex3_sh_lvl3_b[0:162] = (~(ex3_sh_lvl3[0:162]));
assign f_fmt_ex3_pass_frac_b[0:52] = (~(f_fmt_ex3_pass_frac[0:52]));
//--------------------------------------------------------------
assign m0_b[0:52] = (~(({53{ex3_byp_sel_pos}} & ex3_sh_lvl3[0:52]) |
({53{ex3_byp_sel_neg}} & ex3_sh_lvl3_b[0:52])));
assign m1_b[0:52] = (~(({53{ex3_byp_sel_byp_pos}} & f_fmt_ex3_pass_frac[0:52]) |
({53{ex3_byp_sel_byp_neg}} & f_fmt_ex3_pass_frac_b[0:52])));
//---------------------------------------------------------------
//---------------------------------------------------------------
assign m0_b[53:98] = (~({46{ex3_prd_sel_pos_hi}} & ex3_sh_lvl3[53:98]));
assign m1_b[53:98] = (~({46{ex3_prd_sel_neg_hi}} & ex3_sh_lvl3_b[53:98]));
//---------------------------------------------------------------
assign m0_b[99:130] = (~({32{ex3_prd_sel_pos_lohi}} & ex3_sh_lvl3[99:130]));
assign m1_b[99:130] = (~({32{ex3_prd_sel_neg_lohi}} & ex3_sh_lvl3_b[99:130]));
//---------------------------------------------------------------
assign m0_b[131:162] = (~({32{ex3_prd_sel_pos_lo}} & ex3_sh_lvl3[131:162]));
assign m1_b[131:162] = (~({32{ex3_prd_sel_neg_lo}} & ex3_sh_lvl3_b[131:162]));
//---------------------------------------------------------------
assign f_alg_ex3_res[0:162] = (~(m0_b[0:162] & m1_b[0:162]));
endmodule |
module iuq_btb(
// power pins
inout gnd,
inout vdd,
inout vcs,
// clock and clockcontrol ports
input [0:`NCLK_WIDTH-1] nclk,
input pc_iu_func_sl_thold_2,
input pc_iu_sg_2,
input pc_iu_fce_2,
input tc_ac_ccflush_dc,
input clkoff_b,
input act_dis,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input scan_in,
output scan_out,
// ports
input r_act,
input w_act,
input [0:5] r_addr,
input [0:5] w_addr,
input [0:2*`EFF_IFAR_WIDTH+2] data_in,
output [0:2*`EFF_IFAR_WIDTH+2] data_out,
input pc_iu_init_reset
);
//--------------------------
// constants
//--------------------------
parameter data_in_offset = 0;
parameter w_act_offset = data_in_offset + 2 * `EFF_IFAR_WIDTH + 3;
parameter r_act_offset = w_act_offset + 1;
parameter w_addr_offset = r_act_offset + 1;
parameter r_addr_offset = w_addr_offset + 6;
parameter reset_w_addr_offset = r_addr_offset + 6;
parameter data_out_offset = reset_w_addr_offset + 6;
parameter scan_right = data_out_offset + 2 * `EFF_IFAR_WIDTH + 3 - 1;
//--------------------------
// signals
//--------------------------
wire [0:71] w_data_in;
wire [0:71] r_data_out;
wire [0:5] zeros;
wire pc_iu_func_sl_thold_1;
wire pc_iu_func_sl_thold_0;
wire pc_iu_func_sl_thold_0_b;
wire pc_iu_sg_1;
wire pc_iu_sg_0;
wire pc_iu_fce_1;
(* analysis_not_referenced="true" *)
wire pc_iu_fce_0;
wire force_t;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
wire tiup;
wire tidn;
wire write_thru;
wire [0:2*`EFF_IFAR_WIDTH+2] data_in_d;
wire [0:2*`EFF_IFAR_WIDTH+2] data_in_q;
wire w_act_d;
wire w_act_q;
wire r_act_d;
wire r_act_q;
wire [0:5] w_addr_d;
wire [0:5] w_addr_q;
wire [0:5] r_addr_d;
wire [0:5] r_addr_q;
wire [0:2*`EFF_IFAR_WIDTH+2] data_out_d;
wire [0:2*`EFF_IFAR_WIDTH+2] data_out_q;
wire lat_wi_act;
wire lat_ri_act;
wire lat_ro_act;
wire reset_act;
wire [0:5] reset_w_addr_d;
wire [0:5] reset_w_addr_q;
wire w_act_in;
wire [0:5] w_addr_in;
//unused
(* analysis_not_referenced="true" *)
wire abst_scan_out;
(* analysis_not_referenced="true" *)
wire time_scan_out;
(* analysis_not_referenced="true" *)
wire repr_scan_out;
(* analysis_not_referenced="true" *)
wire bo_pc_failout;
(* analysis_not_referenced="true" *)
wire bo_pc_diagloop;
assign tiup = 1'b1;
assign tidn = 1'b0;
assign reset_act = pc_iu_init_reset;
assign reset_w_addr_d[0:5] = reset_w_addr_q[0:5] + 6'b000001;
//-- data in
//
assign zeros[0:5] = {6{1'b0}};
//
//-- arrays
//
// tri array
assign w_act_in = reset_act | w_act;
assign w_addr_in[0:5] = reset_act ? reset_w_addr_q[0:5] : w_addr[0:5];
assign w_data_in[0:71] = reset_act ? 0 : {data_in[0:2 * `EFF_IFAR_WIDTH + 2], {(71 - (2 * `EFF_IFAR_WIDTH + 2)){1'b0}} };
tri_64x72_1r1w btb0(
.vdd(vdd),
.vcs(vcs),
.gnd(gnd),
.nclk(nclk),
.sg_0(pc_iu_sg_0),
.abst_sl_thold_0(tidn),
.ary_nsl_thold_0(tidn),
.time_sl_thold_0(tiup),
.repr_sl_thold_0(tiup),
// Reads
.rd0_act(r_act),
.rd0_adr(r_addr),
.do0(r_data_out),
// Writes
.wr_act(w_act_in),
.wr_adr(w_addr_in),
.di(w_data_in),
// Scan
.abst_scan_in(tidn),
.abst_scan_out(abst_scan_out),
.time_scan_in(tidn),
.time_scan_out(time_scan_out),
.repr_scan_in(tidn),
.repr_scan_out(repr_scan_out),
// Misc Pervasive
.scan_dis_dc_b(tidn), //an_ac_scan_dis_dc_b,
.scan_diag_dc(tidn), //an_ac_scan_diag_dc,
.ccflush_dc(tc_ac_ccflush_dc),
.clkoff_dc_b(clkoff_b), //g8t_clkoff_dc_b,
.d_mode_dc(d_mode), //g8t_d_mode_dc,
.mpw1_dc_b({5{mpw1_b}}), //g8t_mpw1_dc_b,
.mpw2_dc_b(mpw2_b), //g8t_mpw2_dc_b,
.delay_lclkr_dc({5{delay_lclkr}}), //g8t_delay_lclkr_dc,
// BOLT-ON
.lcb_bolt_sl_thold_0(tidn), //bolt_sl_thold_0,
.pc_bo_enable_2(tidn), //bo_enable_2, -- general bolt-on enable
.pc_bo_reset(tidn), //pc_xu_bo_reset, -- reset
.pc_bo_unload(tidn), //pc_xu_bo_unload, -- unload sticky bits
.pc_bo_repair(tidn), //pc_xu_bo_repair, -- execute sticky bit decode
.pc_bo_shdata(tidn), //pc_xu_bo_shdata, -- shift data for timing write and diag loop
.pc_bo_select(tidn), //pc_xu_bo_select, -- select for mask and hier writes
.bo_pc_failout(bo_pc_failout),
.bo_pc_diagloop(bo_pc_diagloop),
.tri_lcb_mpw1_dc_b(mpw1_b), //mpw1_dc_b,
.tri_lcb_mpw2_dc_b(mpw2_b), //mpw2_dc_b,
.tri_lcb_delay_lclkr_dc(delay_lclkr), //delay_lclkr_dc,
.tri_lcb_clkoff_dc_b(clkoff_b), //clkoff_dc_b,
.tri_lcb_act_dis_dc(act_dis),
// ABIST
.abist_bw_odd(tidn), //abist_g8t_bw_1_q,
.abist_bw_even(tidn), //abist_g8t_bw_0_q,
.tc_lbist_ary_wrt_thru_dc(tidn), //an_ac_lbist_ary_wrt_thru_dc,
.abist_ena_1(tidn), //pc_xu_abist_ena_dc,
.wr_abst_act(tidn), //abist_g8t_wenb_q,
.abist_wr_adr(zeros[0:5]), //abist_waddr_0_q,
.abist_di(zeros[0:3]), //abist_di_0_q,
.rd0_abst_act(tidn), //abist_g8t1p_renb_0_q,
.abist_rd0_adr(zeros[0:5]), //abist_raddr_0_q,
.abist_g8t_rd0_comp_ena(tidn), //abist_wl32_comp_ena_q,
.abist_raw_dc_b(tidn), //pc_xu_abist_raw_dc_b,
.obs0_abist_cmp(zeros[0:3]) //abist_g8t_dcomp_q
);
// write through support
assign data_in_d[0:2 * `EFF_IFAR_WIDTH + 2] = data_in[0:2 * `EFF_IFAR_WIDTH + 2];
assign w_act_d = w_act;
assign r_act_d = r_act;
assign w_addr_d[0:5] = w_addr[0:5];
assign r_addr_d[0:5] = r_addr[0:5];
assign write_thru = w_act_q & (w_addr_q[0:5] == r_addr_q[0:5]) & r_act_q;
// data out
assign data_out_d[0:2 * `EFF_IFAR_WIDTH + 2] = (write_thru == 1'b1) ? data_in_q[0:2 * `EFF_IFAR_WIDTH + 2] :
r_data_out[0:2 * `EFF_IFAR_WIDTH + 2];
assign data_out[0:2 * `EFF_IFAR_WIDTH + 2] = data_out_q[0:2 * `EFF_IFAR_WIDTH + 2];
//latch acts
assign lat_wi_act = w_act;
assign lat_ri_act = r_act;
assign lat_ro_act = r_act_q;
// latches
tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_in_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[data_in_offset:data_in_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]),
.scout(sov[data_in_offset:data_in_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]),
.din(data_in_d),
.dout(data_in_q)
);
tri_rlmlatch_p #(.INIT(0)) w_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[w_act_offset]),
.scout(sov[w_act_offset]),
.din(w_act_d),
.dout(w_act_q)
);
tri_rlmlatch_p #(.INIT(0)) r_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[r_act_offset]),
.scout(sov[r_act_offset]),
.din(r_act_d),
.dout(r_act_q)
);
tri_rlmreg_p #(.WIDTH(6), .INIT(0)) w_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[w_addr_offset:w_addr_offset + 6 - 1]),
.scout(sov[w_addr_offset:w_addr_offset + 6 - 1]),
.din(w_addr_d),
.dout(w_addr_q)
);
tri_rlmreg_p #(.WIDTH(6), .INIT(0)) r_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_ri_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[r_addr_offset:r_addr_offset + 6 - 1]),
.scout(sov[r_addr_offset:r_addr_offset + 6 - 1]),
.din(r_addr_d),
.dout(r_addr_q)
);
tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_out_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_ro_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[data_out_offset:data_out_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]),
.scout(sov[data_out_offset:data_out_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]),
.din(data_out_d),
.dout(data_out_q)
);
tri_rlmreg_p #(.WIDTH(6), .INIT(0)) reset_w_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(reset_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[reset_w_addr_offset:reset_w_addr_offset + 6 - 1]),
.scout(sov[reset_w_addr_offset:reset_w_addr_offset + 6 - 1]),
.din(reset_w_addr_d),
.dout(reset_w_addr_q)
);
//-----------------------------------------------
// pervasive
//-----------------------------------------------
tri_plat #(.WIDTH(3)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_fce_2}),
.q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1})
);
tri_plat #(.WIDTH(3)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1}),
.q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_fce_0})
);
tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b),
.thold(pc_iu_func_sl_thold_0),
.sg(pc_iu_sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b)
);
//-----------------------------------------------
// scan
//-----------------------------------------------
assign siv[0:scan_right] = {scan_in, sov[0:scan_right - 1]};
assign scan_out = sov[scan_right];
endmodule |
module fu_gst_inc19(
a,
o
);
`include "tri_a2o.vh"
input [1:19] a;
output [1:19] o; // sum if ci=1
wire [01:19] a_sum;
wire [02:19] a_cout_b;
(* NO_MODIFICATION="TRUE" *)
wire [02:19] g2_b;
(* NO_MODIFICATION="TRUE" *)
wire [02:19] g4;
(* NO_MODIFICATION="TRUE" *)
wire [02:19] g8_b;
(* NO_MODIFICATION="TRUE" *)
wire [02:19] g16;
assign g2_b[19] = (~(a[19]));
assign g2_b[18] = (~(a[18] & a[19]));
assign g2_b[17] = (~(a[17] & a[18]));
assign g2_b[16] = (~(a[16] & a[17]));
assign g2_b[15] = (~(a[15] & a[16]));
assign g2_b[14] = (~(a[14] & a[15]));
assign g2_b[13] = (~(a[13] & a[14]));
assign g2_b[12] = (~(a[12] & a[13]));
assign g2_b[11] = (~(a[11] & a[12]));
assign g2_b[10] = (~(a[10] & a[11]));
assign g2_b[9] = (~(a[9] & a[10]));
assign g2_b[8] = (~(a[8] & a[9]));
assign g2_b[7] = (~(a[7] & a[8]));
assign g2_b[6] = (~(a[6] & a[7]));
assign g2_b[5] = (~(a[5] & a[6]));
assign g2_b[4] = (~(a[4] & a[5]));
assign g2_b[3] = (~(a[3] & a[4]));
assign g2_b[2] = (~(a[2] & a[3]));
assign g4[19] = (~(g2_b[19]));
assign g4[18] = (~(g2_b[18]));
assign g4[17] = (~(g2_b[17] | g2_b[19]));
assign g4[16] = (~(g2_b[16] | g2_b[18]));
assign g4[15] = (~(g2_b[15] | g2_b[17]));
assign g4[14] = (~(g2_b[14] | g2_b[16]));
assign g4[13] = (~(g2_b[13] | g2_b[15]));
assign g4[12] = (~(g2_b[12] | g2_b[14]));
assign g4[11] = (~(g2_b[11] | g2_b[13]));
assign g4[10] = (~(g2_b[10] | g2_b[12]));
assign g4[9] = (~(g2_b[9] | g2_b[11]));
assign g4[8] = (~(g2_b[8] | g2_b[10]));
assign g4[7] = (~(g2_b[7] | g2_b[9]));
assign g4[6] = (~(g2_b[6] | g2_b[8]));
assign g4[5] = (~(g2_b[5] | g2_b[7]));
assign g4[4] = (~(g2_b[4] | g2_b[6]));
assign g4[3] = (~(g2_b[3] | g2_b[5]));
assign g4[2] = (~(g2_b[2] | g2_b[4]));
assign g8_b[19] = (~(g4[19]));
assign g8_b[18] = (~(g4[18]));
assign g8_b[17] = (~(g4[17]));
assign g8_b[16] = (~(g4[16]));
assign g8_b[15] = (~(g4[15] & g4[19]));
assign g8_b[14] = (~(g4[14] & g4[18]));
assign g8_b[13] = (~(g4[13] & g4[17]));
assign g8_b[12] = (~(g4[12] & g4[16]));
assign g8_b[11] = (~(g4[11] & g4[15]));
assign g8_b[10] = (~(g4[10] & g4[14]));
assign g8_b[9] = (~(g4[9] & g4[13]));
assign g8_b[8] = (~(g4[8] & g4[12]));
assign g8_b[7] = (~(g4[7] & g4[11]));
assign g8_b[6] = (~(g4[6] & g4[10]));
assign g8_b[5] = (~(g4[5] & g4[9]));
assign g8_b[4] = (~(g4[4] & g4[8]));
assign g8_b[3] = (~(g4[3] & g4[7]));
assign g8_b[2] = (~(g4[2] & g4[6]));
assign g16[19] = (~(g8_b[19]));
assign g16[18] = (~(g8_b[18]));
assign g16[17] = (~(g8_b[17]));
assign g16[16] = (~(g8_b[16]));
assign g16[15] = (~(g8_b[15]));
assign g16[14] = (~(g8_b[14]));
assign g16[13] = (~(g8_b[13]));
assign g16[12] = (~(g8_b[12]));
assign g16[11] = (~(g8_b[11] | g8_b[19]));
assign g16[10] = (~(g8_b[10] | g8_b[18]));
assign g16[9] = (~(g8_b[9] | g8_b[17]));
assign g16[8] = (~(g8_b[8] | g8_b[16]));
assign g16[7] = (~(g8_b[7] | g8_b[15]));
assign g16[6] = (~(g8_b[6] | g8_b[14]));
assign g16[5] = (~(g8_b[5] | g8_b[13]));
assign g16[4] = (~(g8_b[4] | g8_b[12]));
assign g16[3] = (~(g8_b[3] | g8_b[11]));
assign g16[2] = (~(g8_b[2] | g8_b[10]));
assign a_cout_b[19] = (~(g16[19]));
assign a_cout_b[18] = (~(g16[18]));
assign a_cout_b[17] = (~(g16[17]));
assign a_cout_b[16] = (~(g16[16]));
assign a_cout_b[15] = (~(g16[15]));
assign a_cout_b[14] = (~(g16[14]));
assign a_cout_b[13] = (~(g16[13]));
assign a_cout_b[12] = (~(g16[12]));
assign a_cout_b[11] = (~(g16[11]));
assign a_cout_b[10] = (~(g16[10]));
assign a_cout_b[9] = (~(g16[9]));
assign a_cout_b[8] = (~(g16[8]));
assign a_cout_b[7] = (~(g16[7]));
assign a_cout_b[6] = (~(g16[6]));
assign a_cout_b[5] = (~(g16[5]));
assign a_cout_b[4] = (~(g16[4]));
assign a_cout_b[3] = (~(g16[3] & g16[19]));
assign a_cout_b[2] = (~(g16[2] & g16[18]));
//---------------------------------------------------------
assign a_sum[1:18] = a[1:18];
assign a_sum[19] = (~a[19]);
assign o[01:18] = (~(a_sum[01:18] ^ a_cout_b[02:19])); //output
assign o[19] = a_sum[19]; //output
endmodule |
module fu_alg_sh4(
ex2_lvl1_shdcd000_b,
ex2_lvl1_shdcd001_b,
ex2_lvl1_shdcd002_b,
ex2_lvl1_shdcd003_b,
ex2_lvl2_shdcd000,
ex2_lvl2_shdcd004,
ex2_lvl2_shdcd008,
ex2_lvl2_shdcd012,
ex2_sel_special,
ex2_b_sign,
ex2_b_expo,
ex2_b_frac,
ex2_sh_lvl2
);
//--------- SHIFT CONTROLS -----------------
input ex2_lvl1_shdcd000_b;
input ex2_lvl1_shdcd001_b;
input ex2_lvl1_shdcd002_b;
input ex2_lvl1_shdcd003_b;
input ex2_lvl2_shdcd000;
input ex2_lvl2_shdcd004;
input ex2_lvl2_shdcd008;
input ex2_lvl2_shdcd012;
input ex2_sel_special;
//--------- SHIFT DATA -----------------
input ex2_b_sign;
input [3:13] ex2_b_expo;
input [0:52] ex2_b_frac;
//-------- SHIFT OUTPUT ---------------
output [0:67] ex2_sh_lvl2;
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:63] ex2_special_fcfid;
wire [0:55] ex2_sh_lv1;
wire [0:53] ex2_sh_lv1x_b;
wire [2:55] ex2_sh_lv1y_b;
wire [0:59] ex2_sh_lv2x_b;
wire [8:67] ex2_sh_lv2y_b;
wire [0:63] ex2_sh_lv2z_b;
// signal sh1v1dcd0_cp1_b :std_ulogic;--decode signals
wire sh1v2dcd0_cp1;
wire sh1v3dcd0_cp1_b;
wire sh1v3dcd0_cp2_b;
wire sh1v4dcd0_cp1;
wire sh1v4dcd0_cp2;
wire sh1v4dcd0_cp3;
wire sh1v4dcd0_cp4;
// signal sh1v1dcd1_cp1_b :std_ulogic;
wire sh1v2dcd1_cp1;
wire sh1v3dcd1_cp1_b;
wire sh1v3dcd1_cp2_b;
wire sh1v4dcd1_cp1;
wire sh1v4dcd1_cp2;
wire sh1v4dcd1_cp3;
wire sh1v4dcd1_cp4;
// signal sh1v1dcd2_cp1_b :std_ulogic;
wire sh1v2dcd2_cp1;
wire sh1v3dcd2_cp1_b;
wire sh1v3dcd2_cp2_b;
wire sh1v4dcd2_cp1;
wire sh1v4dcd2_cp2;
wire sh1v4dcd2_cp3;
wire sh1v4dcd2_cp4;
// signal sh1v1dcd3_cp1_b :std_ulogic;
wire sh1v2dcd3_cp1;
wire sh1v3dcd3_cp1_b;
wire sh1v3dcd3_cp2_b;
wire sh1v4dcd3_cp1;
wire sh1v4dcd3_cp2;
wire sh1v4dcd3_cp3;
wire sh1v4dcd3_cp4;
wire sh2v1dcd00_cp1_b;
wire sh2v2dcd00_cp1;
wire sh2v3dcd00_cp1_b;
wire sh2v3dcd00_cp2_b;
wire sh2v4dcd00_cp1;
wire sh2v4dcd00_cp2;
wire sh2v4dcd00_cp3;
wire sh2v4dcd00_cp4;
wire sh2v1dcd04_cp1_b;
wire sh2v2dcd04_cp1;
wire sh2v3dcd04_cp1_b;
wire sh2v3dcd04_cp2_b;
wire sh2v4dcd04_cp1;
wire sh2v4dcd04_cp2;
wire sh2v4dcd04_cp3;
wire sh2v4dcd04_cp4;
wire sh2v1dcd08_cp1_b;
wire sh2v2dcd08_cp1;
wire sh2v3dcd08_cp1_b;
wire sh2v3dcd08_cp2_b;
wire sh2v4dcd08_cp1;
wire sh2v4dcd08_cp2;
wire sh2v4dcd08_cp3;
wire sh2v4dcd08_cp4;
wire sh2v1dcd12_cp1_b;
wire sh2v2dcd12_cp1;
wire sh2v3dcd12_cp1_b;
wire sh2v3dcd12_cp2_b;
wire sh2v4dcd12_cp1;
wire sh2v4dcd12_cp2;
wire sh2v4dcd12_cp3;
wire sh2v4dcd12_cp4;
wire sh2v1dcdpp_cp1_b;
wire sh2v2dcdpp_cp1;
wire sh2v3dcdpp_cp1_b;
wire sh2v3dcdpp_cp2_b;
wire sh2v4dcdpp_cp1;
wire sh2v4dcdpp_cp2;
wire sh2v4dcdpp_cp3;
wire sh2v4dcdpp_cp4;
//#-------------------------------------------------
//# adjust B for fcfid specials
//#-------------------------------------------------
// if implicit bit is off: exponent should be 0 instead of x001, x381 (1/897)
// frac(0) is the implicit bit.
// 0_0000_0000_0001 1
// 0_0011_1000_0001 897
assign ex2_special_fcfid[0] = ex2_b_sign; // fcfid integer
assign ex2_special_fcfid[1] = ex2_b_expo[3];
assign ex2_special_fcfid[2] = ex2_b_expo[4] & ex2_b_frac[0];
assign ex2_special_fcfid[3] = ex2_b_expo[5] & ex2_b_frac[0];
assign ex2_special_fcfid[4] = ex2_b_expo[6] & ex2_b_frac[0];
assign ex2_special_fcfid[5] = ex2_b_expo[7];
assign ex2_special_fcfid[6] = ex2_b_expo[8];
assign ex2_special_fcfid[7] = ex2_b_expo[9];
assign ex2_special_fcfid[8] = ex2_b_expo[10];
assign ex2_special_fcfid[9] = ex2_b_expo[11];
assign ex2_special_fcfid[10] = ex2_b_expo[12];
assign ex2_special_fcfid[11] = ex2_b_expo[13] & ex2_b_frac[0];
assign ex2_special_fcfid[12:63] = ex2_b_frac[1:52]; // fcfid integer
//#---------------------------------------
//# repower the selects for sh 0/1/2/3
//#---------------------------------------
assign sh1v2dcd0_cp1 = (~ex2_lvl1_shdcd000_b);
assign sh1v3dcd0_cp1_b = (~sh1v2dcd0_cp1);
assign sh1v3dcd0_cp2_b = (~sh1v2dcd0_cp1);
assign sh1v4dcd0_cp1 = (~sh1v3dcd0_cp1_b); //drive 0:13
assign sh1v4dcd0_cp2 = (~sh1v3dcd0_cp1_b); //drive 14:27
assign sh1v4dcd0_cp3 = (~sh1v3dcd0_cp2_b); //drive 28:41
assign sh1v4dcd0_cp4 = (~sh1v3dcd0_cp2_b); //drive 42:55
assign sh1v2dcd1_cp1 = (~ex2_lvl1_shdcd001_b);
assign sh1v3dcd1_cp1_b = (~sh1v2dcd1_cp1);
assign sh1v3dcd1_cp2_b = (~sh1v2dcd1_cp1);
assign sh1v4dcd1_cp1 = (~sh1v3dcd1_cp1_b); //drive 0:13
assign sh1v4dcd1_cp2 = (~sh1v3dcd1_cp1_b); //drive 14:27
assign sh1v4dcd1_cp3 = (~sh1v3dcd1_cp2_b); //drive 28:41
assign sh1v4dcd1_cp4 = (~sh1v3dcd1_cp2_b); //drive 42:55
assign sh1v2dcd2_cp1 = (~ex2_lvl1_shdcd002_b);
assign sh1v3dcd2_cp1_b = (~sh1v2dcd2_cp1);
assign sh1v3dcd2_cp2_b = (~sh1v2dcd2_cp1);
assign sh1v4dcd2_cp1 = (~sh1v3dcd2_cp1_b); //drive 0:13
assign sh1v4dcd2_cp2 = (~sh1v3dcd2_cp1_b); //drive 14:27
assign sh1v4dcd2_cp3 = (~sh1v3dcd2_cp2_b); //drive 28:41
assign sh1v4dcd2_cp4 = (~sh1v3dcd2_cp2_b); //drive 42:55
assign sh1v2dcd3_cp1 = (~ex2_lvl1_shdcd003_b);
assign sh1v3dcd3_cp1_b = (~sh1v2dcd3_cp1);
assign sh1v3dcd3_cp2_b = (~sh1v2dcd3_cp1);
assign sh1v4dcd3_cp1 = (~sh1v3dcd3_cp1_b); //drive 0:13
assign sh1v4dcd3_cp2 = (~sh1v3dcd3_cp1_b); //drive 14:27
assign sh1v4dcd3_cp3 = (~sh1v3dcd3_cp2_b); //drive 28:41
assign sh1v4dcd3_cp4 = (~sh1v3dcd3_cp2_b); //drive 42:55
//#---------------------------------------
//# repower the selects for sh 0/4/8/12
//#---------------------------------------
assign sh2v1dcd00_cp1_b = (~ex2_lvl2_shdcd000);
assign sh2v2dcd00_cp1 = (~sh2v1dcd00_cp1_b);
assign sh2v3dcd00_cp1_b = (~sh2v2dcd00_cp1);
assign sh2v3dcd00_cp2_b = (~sh2v2dcd00_cp1);
assign sh2v4dcd00_cp1 = (~sh2v3dcd00_cp1_b); //drive 0:16
assign sh2v4dcd00_cp2 = (~sh2v3dcd00_cp1_b); //drive 17:33
assign sh2v4dcd00_cp3 = (~sh2v3dcd00_cp2_b); //drive 34:50
assign sh2v4dcd00_cp4 = (~sh2v3dcd00_cp2_b); //drive 57:67
assign sh2v1dcd04_cp1_b = (~ex2_lvl2_shdcd004);
assign sh2v2dcd04_cp1 = (~sh2v1dcd04_cp1_b);
assign sh2v3dcd04_cp1_b = (~sh2v2dcd04_cp1);
assign sh2v3dcd04_cp2_b = (~sh2v2dcd04_cp1);
assign sh2v4dcd04_cp1 = (~sh2v3dcd04_cp1_b); //drive 0:16
assign sh2v4dcd04_cp2 = (~sh2v3dcd04_cp1_b); //drive 17:33
assign sh2v4dcd04_cp3 = (~sh2v3dcd04_cp2_b); //drive 34:50
assign sh2v4dcd04_cp4 = (~sh2v3dcd04_cp2_b); //drive 57:67
assign sh2v1dcd08_cp1_b = (~ex2_lvl2_shdcd008);
assign sh2v2dcd08_cp1 = (~sh2v1dcd08_cp1_b);
assign sh2v3dcd08_cp1_b = (~sh2v2dcd08_cp1);
assign sh2v3dcd08_cp2_b = (~sh2v2dcd08_cp1);
assign sh2v4dcd08_cp1 = (~sh2v3dcd08_cp1_b); //drive 0:16
assign sh2v4dcd08_cp2 = (~sh2v3dcd08_cp1_b); //drive 17:33
assign sh2v4dcd08_cp3 = (~sh2v3dcd08_cp2_b); //drive 34:50
assign sh2v4dcd08_cp4 = (~sh2v3dcd08_cp2_b); //drive 57:67
assign sh2v1dcd12_cp1_b = (~ex2_lvl2_shdcd012);
assign sh2v2dcd12_cp1 = (~sh2v1dcd12_cp1_b);
assign sh2v3dcd12_cp1_b = (~sh2v2dcd12_cp1);
assign sh2v3dcd12_cp2_b = (~sh2v2dcd12_cp1);
assign sh2v4dcd12_cp1 = (~sh2v3dcd12_cp1_b); //drive 0:16
assign sh2v4dcd12_cp2 = (~sh2v3dcd12_cp1_b); //drive 17:33
assign sh2v4dcd12_cp3 = (~sh2v3dcd12_cp2_b); //drive 34:50
assign sh2v4dcd12_cp4 = (~sh2v3dcd12_cp2_b); //drive 57:67
assign sh2v1dcdpp_cp1_b = (~ex2_sel_special);
assign sh2v2dcdpp_cp1 = (~sh2v1dcdpp_cp1_b);
assign sh2v3dcdpp_cp1_b = (~sh2v2dcdpp_cp1);
assign sh2v3dcdpp_cp2_b = (~sh2v2dcdpp_cp1);
assign sh2v4dcdpp_cp1 = (~sh2v3dcdpp_cp1_b); //drive 0:16
assign sh2v4dcdpp_cp2 = (~sh2v3dcdpp_cp1_b); //drive 17:33
assign sh2v4dcdpp_cp3 = (~sh2v3dcdpp_cp2_b); //drive 34:50
assign sh2v4dcdpp_cp4 = (~sh2v3dcdpp_cp2_b); //drive 57:67
//-------------------------------------
assign ex2_sh_lv1x_b[0] = (~(sh1v4dcd0_cp1 & ex2_b_frac[0]));
assign ex2_sh_lv1x_b[1] = (~((sh1v4dcd0_cp1 & ex2_b_frac[1]) | (sh1v4dcd1_cp1 & ex2_b_frac[0])));
assign ex2_sh_lv1x_b[2] = (~((sh1v4dcd0_cp1 & ex2_b_frac[2]) | (sh1v4dcd1_cp1 & ex2_b_frac[1])));
assign ex2_sh_lv1x_b[3] = (~((sh1v4dcd0_cp1 & ex2_b_frac[3]) | (sh1v4dcd1_cp1 & ex2_b_frac[2])));
assign ex2_sh_lv1x_b[4] = (~((sh1v4dcd0_cp1 & ex2_b_frac[4]) | (sh1v4dcd1_cp1 & ex2_b_frac[3])));
assign ex2_sh_lv1x_b[5] = (~((sh1v4dcd0_cp1 & ex2_b_frac[5]) | (sh1v4dcd1_cp1 & ex2_b_frac[4])));
assign ex2_sh_lv1x_b[6] = (~((sh1v4dcd0_cp1 & ex2_b_frac[6]) | (sh1v4dcd1_cp1 & ex2_b_frac[5])));
assign ex2_sh_lv1x_b[7] = (~((sh1v4dcd0_cp1 & ex2_b_frac[7]) | (sh1v4dcd1_cp1 & ex2_b_frac[6])));
assign ex2_sh_lv1x_b[8] = (~((sh1v4dcd0_cp1 & ex2_b_frac[8]) | (sh1v4dcd1_cp1 & ex2_b_frac[7])));
assign ex2_sh_lv1x_b[9] = (~((sh1v4dcd0_cp1 & ex2_b_frac[9]) | (sh1v4dcd1_cp1 & ex2_b_frac[8])));
assign ex2_sh_lv1x_b[10] = (~((sh1v4dcd0_cp1 & ex2_b_frac[10]) | (sh1v4dcd1_cp1 & ex2_b_frac[9])));
assign ex2_sh_lv1x_b[11] = (~((sh1v4dcd0_cp1 & ex2_b_frac[11]) | (sh1v4dcd1_cp1 & ex2_b_frac[10])));
assign ex2_sh_lv1x_b[12] = (~((sh1v4dcd0_cp1 & ex2_b_frac[12]) | (sh1v4dcd1_cp1 & ex2_b_frac[11])));
assign ex2_sh_lv1x_b[13] = (~((sh1v4dcd0_cp1 & ex2_b_frac[13]) | (sh1v4dcd1_cp1 & ex2_b_frac[12])));
assign ex2_sh_lv1x_b[14] = (~((sh1v4dcd0_cp2 & ex2_b_frac[14]) | (sh1v4dcd1_cp2 & ex2_b_frac[13])));
assign ex2_sh_lv1x_b[15] = (~((sh1v4dcd0_cp2 & ex2_b_frac[15]) | (sh1v4dcd1_cp2 & ex2_b_frac[14])));
assign ex2_sh_lv1x_b[16] = (~((sh1v4dcd0_cp2 & ex2_b_frac[16]) | (sh1v4dcd1_cp2 & ex2_b_frac[15])));
assign ex2_sh_lv1x_b[17] = (~((sh1v4dcd0_cp2 & ex2_b_frac[17]) | (sh1v4dcd1_cp2 & ex2_b_frac[16])));
assign ex2_sh_lv1x_b[18] = (~((sh1v4dcd0_cp2 & ex2_b_frac[18]) | (sh1v4dcd1_cp2 & ex2_b_frac[17])));
assign ex2_sh_lv1x_b[19] = (~((sh1v4dcd0_cp2 & ex2_b_frac[19]) | (sh1v4dcd1_cp2 & ex2_b_frac[18])));
assign ex2_sh_lv1x_b[20] = (~((sh1v4dcd0_cp2 & ex2_b_frac[20]) | (sh1v4dcd1_cp2 & ex2_b_frac[19])));
assign ex2_sh_lv1x_b[21] = (~((sh1v4dcd0_cp2 & ex2_b_frac[21]) | (sh1v4dcd1_cp2 & ex2_b_frac[20])));
assign ex2_sh_lv1x_b[22] = (~((sh1v4dcd0_cp2 & ex2_b_frac[22]) | (sh1v4dcd1_cp2 & ex2_b_frac[21])));
assign ex2_sh_lv1x_b[23] = (~((sh1v4dcd0_cp2 & ex2_b_frac[23]) | (sh1v4dcd1_cp2 & ex2_b_frac[22])));
assign ex2_sh_lv1x_b[24] = (~((sh1v4dcd0_cp2 & ex2_b_frac[24]) | (sh1v4dcd1_cp2 & ex2_b_frac[23])));
assign ex2_sh_lv1x_b[25] = (~((sh1v4dcd0_cp2 & ex2_b_frac[25]) | (sh1v4dcd1_cp2 & ex2_b_frac[24])));
assign ex2_sh_lv1x_b[26] = (~((sh1v4dcd0_cp2 & ex2_b_frac[26]) | (sh1v4dcd1_cp2 & ex2_b_frac[25])));
assign ex2_sh_lv1x_b[27] = (~((sh1v4dcd0_cp2 & ex2_b_frac[27]) | (sh1v4dcd1_cp2 & ex2_b_frac[26])));
assign ex2_sh_lv1x_b[28] = (~((sh1v4dcd0_cp3 & ex2_b_frac[28]) | (sh1v4dcd1_cp3 & ex2_b_frac[27])));
assign ex2_sh_lv1x_b[29] = (~((sh1v4dcd0_cp3 & ex2_b_frac[29]) | (sh1v4dcd1_cp3 & ex2_b_frac[28])));
assign ex2_sh_lv1x_b[30] = (~((sh1v4dcd0_cp3 & ex2_b_frac[30]) | (sh1v4dcd1_cp3 & ex2_b_frac[29])));
assign ex2_sh_lv1x_b[31] = (~((sh1v4dcd0_cp3 & ex2_b_frac[31]) | (sh1v4dcd1_cp3 & ex2_b_frac[30])));
assign ex2_sh_lv1x_b[32] = (~((sh1v4dcd0_cp3 & ex2_b_frac[32]) | (sh1v4dcd1_cp3 & ex2_b_frac[31])));
assign ex2_sh_lv1x_b[33] = (~((sh1v4dcd0_cp3 & ex2_b_frac[33]) | (sh1v4dcd1_cp3 & ex2_b_frac[32])));
assign ex2_sh_lv1x_b[34] = (~((sh1v4dcd0_cp3 & ex2_b_frac[34]) | (sh1v4dcd1_cp3 & ex2_b_frac[33])));
assign ex2_sh_lv1x_b[35] = (~((sh1v4dcd0_cp3 & ex2_b_frac[35]) | (sh1v4dcd1_cp3 & ex2_b_frac[34])));
assign ex2_sh_lv1x_b[36] = (~((sh1v4dcd0_cp3 & ex2_b_frac[36]) | (sh1v4dcd1_cp3 & ex2_b_frac[35])));
assign ex2_sh_lv1x_b[37] = (~((sh1v4dcd0_cp3 & ex2_b_frac[37]) | (sh1v4dcd1_cp3 & ex2_b_frac[36])));
assign ex2_sh_lv1x_b[38] = (~((sh1v4dcd0_cp3 & ex2_b_frac[38]) | (sh1v4dcd1_cp3 & ex2_b_frac[37])));
assign ex2_sh_lv1x_b[39] = (~((sh1v4dcd0_cp3 & ex2_b_frac[39]) | (sh1v4dcd1_cp3 & ex2_b_frac[38])));
assign ex2_sh_lv1x_b[40] = (~((sh1v4dcd0_cp3 & ex2_b_frac[40]) | (sh1v4dcd1_cp3 & ex2_b_frac[39])));
assign ex2_sh_lv1x_b[41] = (~((sh1v4dcd0_cp3 & ex2_b_frac[41]) | (sh1v4dcd1_cp3 & ex2_b_frac[40])));
assign ex2_sh_lv1x_b[42] = (~((sh1v4dcd0_cp4 & ex2_b_frac[42]) | (sh1v4dcd1_cp4 & ex2_b_frac[41])));
assign ex2_sh_lv1x_b[43] = (~((sh1v4dcd0_cp4 & ex2_b_frac[43]) | (sh1v4dcd1_cp4 & ex2_b_frac[42])));
assign ex2_sh_lv1x_b[44] = (~((sh1v4dcd0_cp4 & ex2_b_frac[44]) | (sh1v4dcd1_cp4 & ex2_b_frac[43])));
assign ex2_sh_lv1x_b[45] = (~((sh1v4dcd0_cp4 & ex2_b_frac[45]) | (sh1v4dcd1_cp4 & ex2_b_frac[44])));
assign ex2_sh_lv1x_b[46] = (~((sh1v4dcd0_cp4 & ex2_b_frac[46]) | (sh1v4dcd1_cp4 & ex2_b_frac[45])));
assign ex2_sh_lv1x_b[47] = (~((sh1v4dcd0_cp4 & ex2_b_frac[47]) | (sh1v4dcd1_cp4 & ex2_b_frac[46])));
assign ex2_sh_lv1x_b[48] = (~((sh1v4dcd0_cp4 & ex2_b_frac[48]) | (sh1v4dcd1_cp4 & ex2_b_frac[47])));
assign ex2_sh_lv1x_b[49] = (~((sh1v4dcd0_cp4 & ex2_b_frac[49]) | (sh1v4dcd1_cp4 & ex2_b_frac[48])));
assign ex2_sh_lv1x_b[50] = (~((sh1v4dcd0_cp4 & ex2_b_frac[50]) | (sh1v4dcd1_cp4 & ex2_b_frac[49])));
assign ex2_sh_lv1x_b[51] = (~((sh1v4dcd0_cp4 & ex2_b_frac[51]) | (sh1v4dcd1_cp4 & ex2_b_frac[50])));
assign ex2_sh_lv1x_b[52] = (~((sh1v4dcd0_cp4 & ex2_b_frac[52]) | (sh1v4dcd1_cp4 & ex2_b_frac[51])));
assign ex2_sh_lv1x_b[53] = (~(sh1v4dcd1_cp4 & ex2_b_frac[52]));
assign ex2_sh_lv1y_b[2] = (~(sh1v4dcd2_cp1 & ex2_b_frac[0]));
assign ex2_sh_lv1y_b[3] = (~((sh1v4dcd2_cp1 & ex2_b_frac[1]) | (sh1v4dcd3_cp1 & ex2_b_frac[0])));
assign ex2_sh_lv1y_b[4] = (~((sh1v4dcd2_cp1 & ex2_b_frac[2]) | (sh1v4dcd3_cp1 & ex2_b_frac[1])));
assign ex2_sh_lv1y_b[5] = (~((sh1v4dcd2_cp1 & ex2_b_frac[3]) | (sh1v4dcd3_cp1 & ex2_b_frac[2])));
assign ex2_sh_lv1y_b[6] = (~((sh1v4dcd2_cp1 & ex2_b_frac[4]) | (sh1v4dcd3_cp1 & ex2_b_frac[3])));
assign ex2_sh_lv1y_b[7] = (~((sh1v4dcd2_cp1 & ex2_b_frac[5]) | (sh1v4dcd3_cp1 & ex2_b_frac[4])));
assign ex2_sh_lv1y_b[8] = (~((sh1v4dcd2_cp1 & ex2_b_frac[6]) | (sh1v4dcd3_cp1 & ex2_b_frac[5])));
assign ex2_sh_lv1y_b[9] = (~((sh1v4dcd2_cp1 & ex2_b_frac[7]) | (sh1v4dcd3_cp1 & ex2_b_frac[6])));
assign ex2_sh_lv1y_b[10] = (~((sh1v4dcd2_cp1 & ex2_b_frac[8]) | (sh1v4dcd3_cp1 & ex2_b_frac[7])));
assign ex2_sh_lv1y_b[11] = (~((sh1v4dcd2_cp1 & ex2_b_frac[9]) | (sh1v4dcd3_cp1 & ex2_b_frac[8])));
assign ex2_sh_lv1y_b[12] = (~((sh1v4dcd2_cp1 & ex2_b_frac[10]) | (sh1v4dcd3_cp1 & ex2_b_frac[9])));
assign ex2_sh_lv1y_b[13] = (~((sh1v4dcd2_cp1 & ex2_b_frac[11]) | (sh1v4dcd3_cp1 & ex2_b_frac[10])));
assign ex2_sh_lv1y_b[14] = (~((sh1v4dcd2_cp2 & ex2_b_frac[12]) | (sh1v4dcd3_cp2 & ex2_b_frac[11])));
assign ex2_sh_lv1y_b[15] = (~((sh1v4dcd2_cp2 & ex2_b_frac[13]) | (sh1v4dcd3_cp2 & ex2_b_frac[12])));
assign ex2_sh_lv1y_b[16] = (~((sh1v4dcd2_cp2 & ex2_b_frac[14]) | (sh1v4dcd3_cp2 & ex2_b_frac[13])));
assign ex2_sh_lv1y_b[17] = (~((sh1v4dcd2_cp2 & ex2_b_frac[15]) | (sh1v4dcd3_cp2 & ex2_b_frac[14])));
assign ex2_sh_lv1y_b[18] = (~((sh1v4dcd2_cp2 & ex2_b_frac[16]) | (sh1v4dcd3_cp2 & ex2_b_frac[15])));
assign ex2_sh_lv1y_b[19] = (~((sh1v4dcd2_cp2 & ex2_b_frac[17]) | (sh1v4dcd3_cp2 & ex2_b_frac[16])));
assign ex2_sh_lv1y_b[20] = (~((sh1v4dcd2_cp2 & ex2_b_frac[18]) | (sh1v4dcd3_cp2 & ex2_b_frac[17])));
assign ex2_sh_lv1y_b[21] = (~((sh1v4dcd2_cp2 & ex2_b_frac[19]) | (sh1v4dcd3_cp2 & ex2_b_frac[18])));
assign ex2_sh_lv1y_b[22] = (~((sh1v4dcd2_cp2 & ex2_b_frac[20]) | (sh1v4dcd3_cp2 & ex2_b_frac[19])));
assign ex2_sh_lv1y_b[23] = (~((sh1v4dcd2_cp2 & ex2_b_frac[21]) | (sh1v4dcd3_cp2 & ex2_b_frac[20])));
assign ex2_sh_lv1y_b[24] = (~((sh1v4dcd2_cp2 & ex2_b_frac[22]) | (sh1v4dcd3_cp2 & ex2_b_frac[21])));
assign ex2_sh_lv1y_b[25] = (~((sh1v4dcd2_cp2 & ex2_b_frac[23]) | (sh1v4dcd3_cp2 & ex2_b_frac[22])));
assign ex2_sh_lv1y_b[26] = (~((sh1v4dcd2_cp2 & ex2_b_frac[24]) | (sh1v4dcd3_cp2 & ex2_b_frac[23])));
assign ex2_sh_lv1y_b[27] = (~((sh1v4dcd2_cp2 & ex2_b_frac[25]) | (sh1v4dcd3_cp2 & ex2_b_frac[24])));
assign ex2_sh_lv1y_b[28] = (~((sh1v4dcd2_cp3 & ex2_b_frac[26]) | (sh1v4dcd3_cp3 & ex2_b_frac[25])));
assign ex2_sh_lv1y_b[29] = (~((sh1v4dcd2_cp3 & ex2_b_frac[27]) | (sh1v4dcd3_cp3 & ex2_b_frac[26])));
assign ex2_sh_lv1y_b[30] = (~((sh1v4dcd2_cp3 & ex2_b_frac[28]) | (sh1v4dcd3_cp3 & ex2_b_frac[27])));
assign ex2_sh_lv1y_b[31] = (~((sh1v4dcd2_cp3 & ex2_b_frac[29]) | (sh1v4dcd3_cp3 & ex2_b_frac[28])));
assign ex2_sh_lv1y_b[32] = (~((sh1v4dcd2_cp3 & ex2_b_frac[30]) | (sh1v4dcd3_cp3 & ex2_b_frac[29])));
assign ex2_sh_lv1y_b[33] = (~((sh1v4dcd2_cp3 & ex2_b_frac[31]) | (sh1v4dcd3_cp3 & ex2_b_frac[30])));
assign ex2_sh_lv1y_b[34] = (~((sh1v4dcd2_cp3 & ex2_b_frac[32]) | (sh1v4dcd3_cp3 & ex2_b_frac[31])));
assign ex2_sh_lv1y_b[35] = (~((sh1v4dcd2_cp3 & ex2_b_frac[33]) | (sh1v4dcd3_cp3 & ex2_b_frac[32])));
assign ex2_sh_lv1y_b[36] = (~((sh1v4dcd2_cp3 & ex2_b_frac[34]) | (sh1v4dcd3_cp3 & ex2_b_frac[33])));
assign ex2_sh_lv1y_b[37] = (~((sh1v4dcd2_cp3 & ex2_b_frac[35]) | (sh1v4dcd3_cp3 & ex2_b_frac[34])));
assign ex2_sh_lv1y_b[38] = (~((sh1v4dcd2_cp3 & ex2_b_frac[36]) | (sh1v4dcd3_cp3 & ex2_b_frac[35])));
assign ex2_sh_lv1y_b[39] = (~((sh1v4dcd2_cp3 & ex2_b_frac[37]) | (sh1v4dcd3_cp3 & ex2_b_frac[36])));
assign ex2_sh_lv1y_b[40] = (~((sh1v4dcd2_cp3 & ex2_b_frac[38]) | (sh1v4dcd3_cp3 & ex2_b_frac[37])));
assign ex2_sh_lv1y_b[41] = (~((sh1v4dcd2_cp4 & ex2_b_frac[39]) | (sh1v4dcd3_cp4 & ex2_b_frac[38])));
assign ex2_sh_lv1y_b[42] = (~((sh1v4dcd2_cp4 & ex2_b_frac[40]) | (sh1v4dcd3_cp4 & ex2_b_frac[39])));
assign ex2_sh_lv1y_b[43] = (~((sh1v4dcd2_cp4 & ex2_b_frac[41]) | (sh1v4dcd3_cp4 & ex2_b_frac[40])));
assign ex2_sh_lv1y_b[44] = (~((sh1v4dcd2_cp4 & ex2_b_frac[42]) | (sh1v4dcd3_cp4 & ex2_b_frac[41])));
assign ex2_sh_lv1y_b[45] = (~((sh1v4dcd2_cp4 & ex2_b_frac[43]) | (sh1v4dcd3_cp4 & ex2_b_frac[42])));
assign ex2_sh_lv1y_b[46] = (~((sh1v4dcd2_cp4 & ex2_b_frac[44]) | (sh1v4dcd3_cp4 & ex2_b_frac[43])));
assign ex2_sh_lv1y_b[47] = (~((sh1v4dcd2_cp4 & ex2_b_frac[45]) | (sh1v4dcd3_cp4 & ex2_b_frac[44])));
assign ex2_sh_lv1y_b[48] = (~((sh1v4dcd2_cp4 & ex2_b_frac[46]) | (sh1v4dcd3_cp4 & ex2_b_frac[45])));
assign ex2_sh_lv1y_b[49] = (~((sh1v4dcd2_cp4 & ex2_b_frac[47]) | (sh1v4dcd3_cp4 & ex2_b_frac[46])));
assign ex2_sh_lv1y_b[50] = (~((sh1v4dcd2_cp4 & ex2_b_frac[48]) | (sh1v4dcd3_cp4 & ex2_b_frac[47])));
assign ex2_sh_lv1y_b[51] = (~((sh1v4dcd2_cp4 & ex2_b_frac[49]) | (sh1v4dcd3_cp4 & ex2_b_frac[48])));
assign ex2_sh_lv1y_b[52] = (~((sh1v4dcd2_cp4 & ex2_b_frac[50]) | (sh1v4dcd3_cp4 & ex2_b_frac[49])));
assign ex2_sh_lv1y_b[53] = (~((sh1v4dcd2_cp4 & ex2_b_frac[51]) | (sh1v4dcd3_cp4 & ex2_b_frac[50])));
assign ex2_sh_lv1y_b[54] = (~((sh1v4dcd2_cp4 & ex2_b_frac[52]) | (sh1v4dcd3_cp4 & ex2_b_frac[51])));
assign ex2_sh_lv1y_b[55] = (~(sh1v4dcd3_cp4 & ex2_b_frac[52]));
assign ex2_sh_lv1[0] = (~(ex2_sh_lv1x_b[0]));
assign ex2_sh_lv1[1] = (~(ex2_sh_lv1x_b[1]));
assign ex2_sh_lv1[2] = (~(ex2_sh_lv1x_b[2] & ex2_sh_lv1y_b[2]));
assign ex2_sh_lv1[3] = (~(ex2_sh_lv1x_b[3] & ex2_sh_lv1y_b[3]));
assign ex2_sh_lv1[4] = (~(ex2_sh_lv1x_b[4] & ex2_sh_lv1y_b[4]));
assign ex2_sh_lv1[5] = (~(ex2_sh_lv1x_b[5] & ex2_sh_lv1y_b[5]));
assign ex2_sh_lv1[6] = (~(ex2_sh_lv1x_b[6] & ex2_sh_lv1y_b[6]));
assign ex2_sh_lv1[7] = (~(ex2_sh_lv1x_b[7] & ex2_sh_lv1y_b[7]));
assign ex2_sh_lv1[8] = (~(ex2_sh_lv1x_b[8] & ex2_sh_lv1y_b[8]));
assign ex2_sh_lv1[9] = (~(ex2_sh_lv1x_b[9] & ex2_sh_lv1y_b[9]));
assign ex2_sh_lv1[10] = (~(ex2_sh_lv1x_b[10] & ex2_sh_lv1y_b[10]));
assign ex2_sh_lv1[11] = (~(ex2_sh_lv1x_b[11] & ex2_sh_lv1y_b[11]));
assign ex2_sh_lv1[12] = (~(ex2_sh_lv1x_b[12] & ex2_sh_lv1y_b[12]));
assign ex2_sh_lv1[13] = (~(ex2_sh_lv1x_b[13] & ex2_sh_lv1y_b[13]));
assign ex2_sh_lv1[14] = (~(ex2_sh_lv1x_b[14] & ex2_sh_lv1y_b[14]));
assign ex2_sh_lv1[15] = (~(ex2_sh_lv1x_b[15] & ex2_sh_lv1y_b[15]));
assign ex2_sh_lv1[16] = (~(ex2_sh_lv1x_b[16] & ex2_sh_lv1y_b[16]));
assign ex2_sh_lv1[17] = (~(ex2_sh_lv1x_b[17] & ex2_sh_lv1y_b[17]));
assign ex2_sh_lv1[18] = (~(ex2_sh_lv1x_b[18] & ex2_sh_lv1y_b[18]));
assign ex2_sh_lv1[19] = (~(ex2_sh_lv1x_b[19] & ex2_sh_lv1y_b[19]));
assign ex2_sh_lv1[20] = (~(ex2_sh_lv1x_b[20] & ex2_sh_lv1y_b[20]));
assign ex2_sh_lv1[21] = (~(ex2_sh_lv1x_b[21] & ex2_sh_lv1y_b[21]));
assign ex2_sh_lv1[22] = (~(ex2_sh_lv1x_b[22] & ex2_sh_lv1y_b[22]));
assign ex2_sh_lv1[23] = (~(ex2_sh_lv1x_b[23] & ex2_sh_lv1y_b[23]));
assign ex2_sh_lv1[24] = (~(ex2_sh_lv1x_b[24] & ex2_sh_lv1y_b[24]));
assign ex2_sh_lv1[25] = (~(ex2_sh_lv1x_b[25] & ex2_sh_lv1y_b[25]));
assign ex2_sh_lv1[26] = (~(ex2_sh_lv1x_b[26] & ex2_sh_lv1y_b[26]));
assign ex2_sh_lv1[27] = (~(ex2_sh_lv1x_b[27] & ex2_sh_lv1y_b[27]));
assign ex2_sh_lv1[28] = (~(ex2_sh_lv1x_b[28] & ex2_sh_lv1y_b[28]));
assign ex2_sh_lv1[29] = (~(ex2_sh_lv1x_b[29] & ex2_sh_lv1y_b[29]));
assign ex2_sh_lv1[30] = (~(ex2_sh_lv1x_b[30] & ex2_sh_lv1y_b[30]));
assign ex2_sh_lv1[31] = (~(ex2_sh_lv1x_b[31] & ex2_sh_lv1y_b[31]));
assign ex2_sh_lv1[32] = (~(ex2_sh_lv1x_b[32] & ex2_sh_lv1y_b[32]));
assign ex2_sh_lv1[33] = (~(ex2_sh_lv1x_b[33] & ex2_sh_lv1y_b[33]));
assign ex2_sh_lv1[34] = (~(ex2_sh_lv1x_b[34] & ex2_sh_lv1y_b[34]));
assign ex2_sh_lv1[35] = (~(ex2_sh_lv1x_b[35] & ex2_sh_lv1y_b[35]));
assign ex2_sh_lv1[36] = (~(ex2_sh_lv1x_b[36] & ex2_sh_lv1y_b[36]));
assign ex2_sh_lv1[37] = (~(ex2_sh_lv1x_b[37] & ex2_sh_lv1y_b[37]));
assign ex2_sh_lv1[38] = (~(ex2_sh_lv1x_b[38] & ex2_sh_lv1y_b[38]));
assign ex2_sh_lv1[39] = (~(ex2_sh_lv1x_b[39] & ex2_sh_lv1y_b[39]));
assign ex2_sh_lv1[40] = (~(ex2_sh_lv1x_b[40] & ex2_sh_lv1y_b[40]));
assign ex2_sh_lv1[41] = (~(ex2_sh_lv1x_b[41] & ex2_sh_lv1y_b[41]));
assign ex2_sh_lv1[42] = (~(ex2_sh_lv1x_b[42] & ex2_sh_lv1y_b[42]));
assign ex2_sh_lv1[43] = (~(ex2_sh_lv1x_b[43] & ex2_sh_lv1y_b[43]));
assign ex2_sh_lv1[44] = (~(ex2_sh_lv1x_b[44] & ex2_sh_lv1y_b[44]));
assign ex2_sh_lv1[45] = (~(ex2_sh_lv1x_b[45] & ex2_sh_lv1y_b[45]));
assign ex2_sh_lv1[46] = (~(ex2_sh_lv1x_b[46] & ex2_sh_lv1y_b[46]));
assign ex2_sh_lv1[47] = (~(ex2_sh_lv1x_b[47] & ex2_sh_lv1y_b[47]));
assign ex2_sh_lv1[48] = (~(ex2_sh_lv1x_b[48] & ex2_sh_lv1y_b[48]));
assign ex2_sh_lv1[49] = (~(ex2_sh_lv1x_b[49] & ex2_sh_lv1y_b[49]));
assign ex2_sh_lv1[50] = (~(ex2_sh_lv1x_b[50] & ex2_sh_lv1y_b[50]));
assign ex2_sh_lv1[51] = (~(ex2_sh_lv1x_b[51] & ex2_sh_lv1y_b[51]));
assign ex2_sh_lv1[52] = (~(ex2_sh_lv1x_b[52] & ex2_sh_lv1y_b[52]));
assign ex2_sh_lv1[53] = (~(ex2_sh_lv1x_b[53] & ex2_sh_lv1y_b[53]));
assign ex2_sh_lv1[54] = (~(ex2_sh_lv1y_b[54]));
assign ex2_sh_lv1[55] = (~(ex2_sh_lv1y_b[55]));
//--------------------------------------------------------------------------------------------
assign ex2_sh_lv2x_b[0] = (~(sh2v4dcd00_cp1 & ex2_sh_lv1[0]));
assign ex2_sh_lv2x_b[1] = (~(sh2v4dcd00_cp1 & ex2_sh_lv1[1]));
assign ex2_sh_lv2x_b[2] = (~(sh2v4dcd00_cp1 & ex2_sh_lv1[2]));
assign ex2_sh_lv2x_b[3] = (~(sh2v4dcd00_cp1 & ex2_sh_lv1[3]));
assign ex2_sh_lv2x_b[4] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[4]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[0])));
assign ex2_sh_lv2x_b[5] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[5]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[1])));
assign ex2_sh_lv2x_b[6] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[6]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[2])));
assign ex2_sh_lv2x_b[7] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[7]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[3])));
assign ex2_sh_lv2x_b[8] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[8]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[4])));
assign ex2_sh_lv2x_b[9] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[9]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[5])));
assign ex2_sh_lv2x_b[10] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[10]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[6])));
assign ex2_sh_lv2x_b[11] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[11]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[7])));
assign ex2_sh_lv2x_b[12] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[12]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[8])));
assign ex2_sh_lv2x_b[13] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[13]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[9])));
assign ex2_sh_lv2x_b[14] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[14]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[10])));
assign ex2_sh_lv2x_b[15] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[15]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[11])));
assign ex2_sh_lv2x_b[16] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[16]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[12])));
assign ex2_sh_lv2x_b[17] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[17]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[13])));
assign ex2_sh_lv2x_b[18] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[18]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[14])));
assign ex2_sh_lv2x_b[19] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[19]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[15])));
assign ex2_sh_lv2x_b[20] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[20]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[16]))); //
assign ex2_sh_lv2x_b[21] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[21]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[17])));
assign ex2_sh_lv2x_b[22] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[22]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[18])));
assign ex2_sh_lv2x_b[23] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[23]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[19])));
assign ex2_sh_lv2x_b[24] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[24]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[20])));
assign ex2_sh_lv2x_b[25] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[25]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[21])));
assign ex2_sh_lv2x_b[26] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[26]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[22])));
assign ex2_sh_lv2x_b[27] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[27]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[23])));
assign ex2_sh_lv2x_b[28] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[28]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[24])));
assign ex2_sh_lv2x_b[29] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[29]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[25])));
assign ex2_sh_lv2x_b[30] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[30]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[26])));
assign ex2_sh_lv2x_b[31] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[31]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[27])));
assign ex2_sh_lv2x_b[32] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[32]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[28])));
assign ex2_sh_lv2x_b[33] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[33]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[29])));
assign ex2_sh_lv2x_b[34] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[34]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[30])));
assign ex2_sh_lv2x_b[35] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[35]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[31])));
assign ex2_sh_lv2x_b[36] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[36]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[32])));
assign ex2_sh_lv2x_b[37] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[37]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[33])));
assign ex2_sh_lv2x_b[38] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[38]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[34])));
assign ex2_sh_lv2x_b[39] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[39]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[35])));
assign ex2_sh_lv2x_b[40] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[40]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[36])));
assign ex2_sh_lv2x_b[41] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[41]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[37])));
assign ex2_sh_lv2x_b[42] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[42]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[38])));
assign ex2_sh_lv2x_b[43] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[43]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[39])));
assign ex2_sh_lv2x_b[44] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[44]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[40])));
assign ex2_sh_lv2x_b[45] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[45]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[41])));
assign ex2_sh_lv2x_b[46] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[46]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[42])));
assign ex2_sh_lv2x_b[47] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[47]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[43])));
assign ex2_sh_lv2x_b[48] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[48]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[44])));
assign ex2_sh_lv2x_b[49] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[49]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[45])));
assign ex2_sh_lv2x_b[50] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[50]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[46])));
assign ex2_sh_lv2x_b[51] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[51]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[47])));
assign ex2_sh_lv2x_b[52] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[52]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[48])));
assign ex2_sh_lv2x_b[53] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[53]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[49])));
assign ex2_sh_lv2x_b[54] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[54]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[50])));
assign ex2_sh_lv2x_b[55] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[55]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[51])));
assign ex2_sh_lv2x_b[56] = (~(sh2v4dcd04_cp4 & ex2_sh_lv1[52]));
assign ex2_sh_lv2x_b[57] = (~(sh2v4dcd04_cp4 & ex2_sh_lv1[53]));
assign ex2_sh_lv2x_b[58] = (~(sh2v4dcd04_cp4 & ex2_sh_lv1[54]));
assign ex2_sh_lv2x_b[59] = (~(sh2v4dcd04_cp4 & ex2_sh_lv1[55]));
assign ex2_sh_lv2y_b[8] = (~(sh2v4dcd08_cp1 & ex2_sh_lv1[0]));
assign ex2_sh_lv2y_b[9] = (~(sh2v4dcd08_cp1 & ex2_sh_lv1[1]));
assign ex2_sh_lv2y_b[10] = (~(sh2v4dcd08_cp1 & ex2_sh_lv1[2]));
assign ex2_sh_lv2y_b[11] = (~(sh2v4dcd08_cp1 & ex2_sh_lv1[3]));
assign ex2_sh_lv2y_b[12] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[4]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[0])));
assign ex2_sh_lv2y_b[13] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[5]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[1])));
assign ex2_sh_lv2y_b[14] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[6]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[2])));
assign ex2_sh_lv2y_b[15] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[7]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[3])));
assign ex2_sh_lv2y_b[16] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[8]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[4])));
assign ex2_sh_lv2y_b[17] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[9]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[5])));
assign ex2_sh_lv2y_b[18] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[10]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[6])));
assign ex2_sh_lv2y_b[19] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[11]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[7])));
assign ex2_sh_lv2y_b[20] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[12]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[8])));
assign ex2_sh_lv2y_b[21] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[13]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[9])));
assign ex2_sh_lv2y_b[22] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[14]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[10])));
assign ex2_sh_lv2y_b[23] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[15]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[11])));
assign ex2_sh_lv2y_b[24] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[16]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[12])));
assign ex2_sh_lv2y_b[25] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[17]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[13])));
assign ex2_sh_lv2y_b[26] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[18]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[14])));
assign ex2_sh_lv2y_b[27] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[19]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[15])));
assign ex2_sh_lv2y_b[28] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[20]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[16])));
assign ex2_sh_lv2y_b[29] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[21]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[17])));
assign ex2_sh_lv2y_b[30] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[22]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[18])));
assign ex2_sh_lv2y_b[31] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[23]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[19])));
assign ex2_sh_lv2y_b[32] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[24]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[20])));
assign ex2_sh_lv2y_b[33] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[25]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[21])));
assign ex2_sh_lv2y_b[34] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[26]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[22])));
assign ex2_sh_lv2y_b[35] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[27]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[23])));
assign ex2_sh_lv2y_b[36] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[28]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[24])));
assign ex2_sh_lv2y_b[37] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[29]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[25])));
assign ex2_sh_lv2y_b[38] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[30]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[26])));
assign ex2_sh_lv2y_b[39] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[31]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[27])));
assign ex2_sh_lv2y_b[40] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[32]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[28])));
assign ex2_sh_lv2y_b[41] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[33]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[29])));
assign ex2_sh_lv2y_b[42] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[34]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[30])));
assign ex2_sh_lv2y_b[43] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[35]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[31])));
assign ex2_sh_lv2y_b[44] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[36]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[32])));
assign ex2_sh_lv2y_b[45] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[37]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[33])));
assign ex2_sh_lv2y_b[46] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[38]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[34])));
assign ex2_sh_lv2y_b[47] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[39]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[35])));
assign ex2_sh_lv2y_b[48] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[40]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[36])));
assign ex2_sh_lv2y_b[49] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[41]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[37])));
assign ex2_sh_lv2y_b[50] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[42]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[38])));
assign ex2_sh_lv2y_b[51] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[43]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[39])));
assign ex2_sh_lv2y_b[52] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[44]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[40])));
assign ex2_sh_lv2y_b[53] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[45]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[41])));
assign ex2_sh_lv2y_b[54] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[46]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[42])));
assign ex2_sh_lv2y_b[55] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[47]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[43])));
assign ex2_sh_lv2y_b[56] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[48]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[44])));
assign ex2_sh_lv2y_b[57] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[49]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[45])));
assign ex2_sh_lv2y_b[58] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[50]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[46])));
assign ex2_sh_lv2y_b[59] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[51]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[47])));
assign ex2_sh_lv2y_b[60] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[52]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[48])));
assign ex2_sh_lv2y_b[61] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[53]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[49])));
assign ex2_sh_lv2y_b[62] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[54]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[50])));
assign ex2_sh_lv2y_b[63] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[55]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[51])));
assign ex2_sh_lv2y_b[64] = (~(sh2v4dcd12_cp4 & ex2_sh_lv1[52]));
assign ex2_sh_lv2y_b[65] = (~(sh2v4dcd12_cp4 & ex2_sh_lv1[53]));
assign ex2_sh_lv2y_b[66] = (~(sh2v4dcd12_cp4 & ex2_sh_lv1[54]));
assign ex2_sh_lv2y_b[67] = (~(sh2v4dcd12_cp4 & ex2_sh_lv1[55]));
assign ex2_sh_lv2z_b[0] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[0]));
assign ex2_sh_lv2z_b[1] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[1]));
assign ex2_sh_lv2z_b[2] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[2]));
assign ex2_sh_lv2z_b[3] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[3]));
assign ex2_sh_lv2z_b[4] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[4]));
assign ex2_sh_lv2z_b[5] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[5]));
assign ex2_sh_lv2z_b[6] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[6]));
assign ex2_sh_lv2z_b[7] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[7]));
assign ex2_sh_lv2z_b[8] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[8]));
assign ex2_sh_lv2z_b[9] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[9]));
assign ex2_sh_lv2z_b[10] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[10]));
assign ex2_sh_lv2z_b[11] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[11]));
assign ex2_sh_lv2z_b[12] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[12]));
assign ex2_sh_lv2z_b[13] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[13]));
assign ex2_sh_lv2z_b[14] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[14]));
assign ex2_sh_lv2z_b[15] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[15]));
assign ex2_sh_lv2z_b[16] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[16]));
assign ex2_sh_lv2z_b[17] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[17]));
assign ex2_sh_lv2z_b[18] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[18]));
assign ex2_sh_lv2z_b[19] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[19]));
assign ex2_sh_lv2z_b[20] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[20]));
assign ex2_sh_lv2z_b[21] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[21]));
assign ex2_sh_lv2z_b[22] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[22]));
assign ex2_sh_lv2z_b[23] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[23]));
assign ex2_sh_lv2z_b[24] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[24]));
assign ex2_sh_lv2z_b[25] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[25]));
assign ex2_sh_lv2z_b[26] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[26]));
assign ex2_sh_lv2z_b[27] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[27]));
assign ex2_sh_lv2z_b[28] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[28]));
assign ex2_sh_lv2z_b[29] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[29]));
assign ex2_sh_lv2z_b[30] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[30]));
assign ex2_sh_lv2z_b[31] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[31]));
assign ex2_sh_lv2z_b[32] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[32]));
assign ex2_sh_lv2z_b[33] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[33]));
assign ex2_sh_lv2z_b[34] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[34]));
assign ex2_sh_lv2z_b[35] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[35]));
assign ex2_sh_lv2z_b[36] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[36]));
assign ex2_sh_lv2z_b[37] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[37]));
assign ex2_sh_lv2z_b[38] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[38]));
assign ex2_sh_lv2z_b[39] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[39]));
assign ex2_sh_lv2z_b[40] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[40]));
assign ex2_sh_lv2z_b[41] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[41]));
assign ex2_sh_lv2z_b[42] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[42]));
assign ex2_sh_lv2z_b[43] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[43]));
assign ex2_sh_lv2z_b[44] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[44]));
assign ex2_sh_lv2z_b[45] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[45]));
assign ex2_sh_lv2z_b[46] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[46]));
assign ex2_sh_lv2z_b[47] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[47]));
assign ex2_sh_lv2z_b[48] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[48]));
assign ex2_sh_lv2z_b[49] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[49]));
assign ex2_sh_lv2z_b[50] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[50]));
assign ex2_sh_lv2z_b[51] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[51]));
assign ex2_sh_lv2z_b[52] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[52]));
assign ex2_sh_lv2z_b[53] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[53]));
assign ex2_sh_lv2z_b[54] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[54]));
assign ex2_sh_lv2z_b[55] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[55]));
assign ex2_sh_lv2z_b[56] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[56]));
assign ex2_sh_lv2z_b[57] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[57]));
assign ex2_sh_lv2z_b[58] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[58]));
assign ex2_sh_lv2z_b[59] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[59]));
assign ex2_sh_lv2z_b[60] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[60]));
assign ex2_sh_lv2z_b[61] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[61]));
assign ex2_sh_lv2z_b[62] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[62]));
assign ex2_sh_lv2z_b[63] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[63]));
assign ex2_sh_lvl2[00] = (~(ex2_sh_lv2x_b[00] & ex2_sh_lv2z_b[00]));
assign ex2_sh_lvl2[01] = (~(ex2_sh_lv2x_b[01] & ex2_sh_lv2z_b[01]));
assign ex2_sh_lvl2[02] = (~(ex2_sh_lv2x_b[02] & ex2_sh_lv2z_b[02]));
assign ex2_sh_lvl2[03] = (~(ex2_sh_lv2x_b[03] & ex2_sh_lv2z_b[03]));
assign ex2_sh_lvl2[04] = (~(ex2_sh_lv2x_b[04] & ex2_sh_lv2z_b[04]));
assign ex2_sh_lvl2[05] = (~(ex2_sh_lv2x_b[05] & ex2_sh_lv2z_b[05]));
assign ex2_sh_lvl2[06] = (~(ex2_sh_lv2x_b[06] & ex2_sh_lv2z_b[06]));
assign ex2_sh_lvl2[07] = (~(ex2_sh_lv2x_b[07] & ex2_sh_lv2z_b[07]));
assign ex2_sh_lvl2[08] = (~(ex2_sh_lv2x_b[08] & ex2_sh_lv2y_b[08] & ex2_sh_lv2z_b[08]));
assign ex2_sh_lvl2[09] = (~(ex2_sh_lv2x_b[09] & ex2_sh_lv2y_b[09] & ex2_sh_lv2z_b[09]));
assign ex2_sh_lvl2[10] = (~(ex2_sh_lv2x_b[10] & ex2_sh_lv2y_b[10] & ex2_sh_lv2z_b[10]));
assign ex2_sh_lvl2[11] = (~(ex2_sh_lv2x_b[11] & ex2_sh_lv2y_b[11] & ex2_sh_lv2z_b[11]));
assign ex2_sh_lvl2[12] = (~(ex2_sh_lv2x_b[12] & ex2_sh_lv2y_b[12] & ex2_sh_lv2z_b[12]));
assign ex2_sh_lvl2[13] = (~(ex2_sh_lv2x_b[13] & ex2_sh_lv2y_b[13] & ex2_sh_lv2z_b[13]));
assign ex2_sh_lvl2[14] = (~(ex2_sh_lv2x_b[14] & ex2_sh_lv2y_b[14] & ex2_sh_lv2z_b[14]));
assign ex2_sh_lvl2[15] = (~(ex2_sh_lv2x_b[15] & ex2_sh_lv2y_b[15] & ex2_sh_lv2z_b[15]));
assign ex2_sh_lvl2[16] = (~(ex2_sh_lv2x_b[16] & ex2_sh_lv2y_b[16] & ex2_sh_lv2z_b[16]));
assign ex2_sh_lvl2[17] = (~(ex2_sh_lv2x_b[17] & ex2_sh_lv2y_b[17] & ex2_sh_lv2z_b[17]));
assign ex2_sh_lvl2[18] = (~(ex2_sh_lv2x_b[18] & ex2_sh_lv2y_b[18] & ex2_sh_lv2z_b[18]));
assign ex2_sh_lvl2[19] = (~(ex2_sh_lv2x_b[19] & ex2_sh_lv2y_b[19] & ex2_sh_lv2z_b[19]));
assign ex2_sh_lvl2[20] = (~(ex2_sh_lv2x_b[20] & ex2_sh_lv2y_b[20] & ex2_sh_lv2z_b[20]));
assign ex2_sh_lvl2[21] = (~(ex2_sh_lv2x_b[21] & ex2_sh_lv2y_b[21] & ex2_sh_lv2z_b[21]));
assign ex2_sh_lvl2[22] = (~(ex2_sh_lv2x_b[22] & ex2_sh_lv2y_b[22] & ex2_sh_lv2z_b[22]));
assign ex2_sh_lvl2[23] = (~(ex2_sh_lv2x_b[23] & ex2_sh_lv2y_b[23] & ex2_sh_lv2z_b[23]));
assign ex2_sh_lvl2[24] = (~(ex2_sh_lv2x_b[24] & ex2_sh_lv2y_b[24] & ex2_sh_lv2z_b[24]));
assign ex2_sh_lvl2[25] = (~(ex2_sh_lv2x_b[25] & ex2_sh_lv2y_b[25] & ex2_sh_lv2z_b[25]));
assign ex2_sh_lvl2[26] = (~(ex2_sh_lv2x_b[26] & ex2_sh_lv2y_b[26] & ex2_sh_lv2z_b[26]));
assign ex2_sh_lvl2[27] = (~(ex2_sh_lv2x_b[27] & ex2_sh_lv2y_b[27] & ex2_sh_lv2z_b[27]));
assign ex2_sh_lvl2[28] = (~(ex2_sh_lv2x_b[28] & ex2_sh_lv2y_b[28] & ex2_sh_lv2z_b[28]));
assign ex2_sh_lvl2[29] = (~(ex2_sh_lv2x_b[29] & ex2_sh_lv2y_b[29] & ex2_sh_lv2z_b[29]));
assign ex2_sh_lvl2[30] = (~(ex2_sh_lv2x_b[30] & ex2_sh_lv2y_b[30] & ex2_sh_lv2z_b[30]));
assign ex2_sh_lvl2[31] = (~(ex2_sh_lv2x_b[31] & ex2_sh_lv2y_b[31] & ex2_sh_lv2z_b[31]));
assign ex2_sh_lvl2[32] = (~(ex2_sh_lv2x_b[32] & ex2_sh_lv2y_b[32] & ex2_sh_lv2z_b[32]));
assign ex2_sh_lvl2[33] = (~(ex2_sh_lv2x_b[33] & ex2_sh_lv2y_b[33] & ex2_sh_lv2z_b[33]));
assign ex2_sh_lvl2[34] = (~(ex2_sh_lv2x_b[34] & ex2_sh_lv2y_b[34] & ex2_sh_lv2z_b[34]));
assign ex2_sh_lvl2[35] = (~(ex2_sh_lv2x_b[35] & ex2_sh_lv2y_b[35] & ex2_sh_lv2z_b[35]));
assign ex2_sh_lvl2[36] = (~(ex2_sh_lv2x_b[36] & ex2_sh_lv2y_b[36] & ex2_sh_lv2z_b[36]));
assign ex2_sh_lvl2[37] = (~(ex2_sh_lv2x_b[37] & ex2_sh_lv2y_b[37] & ex2_sh_lv2z_b[37]));
assign ex2_sh_lvl2[38] = (~(ex2_sh_lv2x_b[38] & ex2_sh_lv2y_b[38] & ex2_sh_lv2z_b[38]));
assign ex2_sh_lvl2[39] = (~(ex2_sh_lv2x_b[39] & ex2_sh_lv2y_b[39] & ex2_sh_lv2z_b[39]));
assign ex2_sh_lvl2[40] = (~(ex2_sh_lv2x_b[40] & ex2_sh_lv2y_b[40] & ex2_sh_lv2z_b[40]));
assign ex2_sh_lvl2[41] = (~(ex2_sh_lv2x_b[41] & ex2_sh_lv2y_b[41] & ex2_sh_lv2z_b[41]));
assign ex2_sh_lvl2[42] = (~(ex2_sh_lv2x_b[42] & ex2_sh_lv2y_b[42] & ex2_sh_lv2z_b[42]));
assign ex2_sh_lvl2[43] = (~(ex2_sh_lv2x_b[43] & ex2_sh_lv2y_b[43] & ex2_sh_lv2z_b[43]));
assign ex2_sh_lvl2[44] = (~(ex2_sh_lv2x_b[44] & ex2_sh_lv2y_b[44] & ex2_sh_lv2z_b[44]));
assign ex2_sh_lvl2[45] = (~(ex2_sh_lv2x_b[45] & ex2_sh_lv2y_b[45] & ex2_sh_lv2z_b[45]));
assign ex2_sh_lvl2[46] = (~(ex2_sh_lv2x_b[46] & ex2_sh_lv2y_b[46] & ex2_sh_lv2z_b[46]));
assign ex2_sh_lvl2[47] = (~(ex2_sh_lv2x_b[47] & ex2_sh_lv2y_b[47] & ex2_sh_lv2z_b[47]));
assign ex2_sh_lvl2[48] = (~(ex2_sh_lv2x_b[48] & ex2_sh_lv2y_b[48] & ex2_sh_lv2z_b[48]));
assign ex2_sh_lvl2[49] = (~(ex2_sh_lv2x_b[49] & ex2_sh_lv2y_b[49] & ex2_sh_lv2z_b[49]));
assign ex2_sh_lvl2[50] = (~(ex2_sh_lv2x_b[50] & ex2_sh_lv2y_b[50] & ex2_sh_lv2z_b[50]));
assign ex2_sh_lvl2[51] = (~(ex2_sh_lv2x_b[51] & ex2_sh_lv2y_b[51] & ex2_sh_lv2z_b[51]));
assign ex2_sh_lvl2[52] = (~(ex2_sh_lv2x_b[52] & ex2_sh_lv2y_b[52] & ex2_sh_lv2z_b[52]));
assign ex2_sh_lvl2[53] = (~(ex2_sh_lv2x_b[53] & ex2_sh_lv2y_b[53] & ex2_sh_lv2z_b[53]));
assign ex2_sh_lvl2[54] = (~(ex2_sh_lv2x_b[54] & ex2_sh_lv2y_b[54] & ex2_sh_lv2z_b[54]));
assign ex2_sh_lvl2[55] = (~(ex2_sh_lv2x_b[55] & ex2_sh_lv2y_b[55] & ex2_sh_lv2z_b[55]));
assign ex2_sh_lvl2[56] = (~(ex2_sh_lv2x_b[56] & ex2_sh_lv2y_b[56] & ex2_sh_lv2z_b[56]));
assign ex2_sh_lvl2[57] = (~(ex2_sh_lv2x_b[57] & ex2_sh_lv2y_b[57] & ex2_sh_lv2z_b[57]));
assign ex2_sh_lvl2[58] = (~(ex2_sh_lv2x_b[58] & ex2_sh_lv2y_b[58] & ex2_sh_lv2z_b[58]));
assign ex2_sh_lvl2[59] = (~(ex2_sh_lv2x_b[59] & ex2_sh_lv2y_b[59] & ex2_sh_lv2z_b[59]));
assign ex2_sh_lvl2[60] = (~(ex2_sh_lv2y_b[60] & ex2_sh_lv2z_b[60]));
assign ex2_sh_lvl2[61] = (~(ex2_sh_lv2y_b[61] & ex2_sh_lv2z_b[61]));
assign ex2_sh_lvl2[62] = (~(ex2_sh_lv2y_b[62] & ex2_sh_lv2z_b[62]));
assign ex2_sh_lvl2[63] = (~(ex2_sh_lv2y_b[63] & ex2_sh_lv2z_b[63]));
assign ex2_sh_lvl2[64] = (~(ex2_sh_lv2y_b[64]));
assign ex2_sh_lvl2[65] = (~(ex2_sh_lv2y_b[65]));
assign ex2_sh_lvl2[66] = (~(ex2_sh_lv2y_b[66]));
assign ex2_sh_lvl2[67] = (~(ex2_sh_lv2y_b[67]));
endmodule |
module rv_barf(
w0_dat,
w0_addr,
w0_en,
w1_dat,
w1_addr,
w1_en,
w_act,
r0_addr,
r0_dat,
vdd,
gnd,
nclk,
sg_1,
func_sl_thold_1,
ccflush_dc,
act_dis,
clkoff_b,
d_mode,
delay_lclkr,
mpw1_b,
mpw2_b,
scan_in,
scan_out
);
`include "tri_a2o.vh"
parameter q_dat_width_g = 137;
parameter q_num_entries_g = 16;
parameter q_barf_enc_g=4;
input [0:q_dat_width_g-1] w0_dat;
input [0:q_barf_enc_g-1] w0_addr;
input w0_en;
input [0:q_dat_width_g-1] w1_dat;
input [0:q_barf_enc_g-1] w1_addr;
input w1_en;
input [0:q_num_entries_g-1] w_act;
input [0:q_barf_enc_g-1] r0_addr;
output [0:q_dat_width_g-1] r0_dat;
// pervasive
inout vdd;
inout gnd;
input [0:`NCLK_WIDTH-1] nclk;
input sg_1;
input func_sl_thold_1;
input ccflush_dc;
input act_dis;
input clkoff_b;
input d_mode;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input scan_in;
output scan_out;
//-------------------------------------------------------------------------------------------------------
// Type definitions
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
// Functions
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------
// Signals
//-------------------------------------------------------------------
wire [0:q_num_entries_g-1] sg_0;
wire [0:q_num_entries_g-1] func_sl_thold_0;
wire [0:q_num_entries_g-1] func_sl_thold_0_b;
wire [0:q_num_entries_g-1] force_t;
wire [0:q_num_entries_g-1] q_entry_load0;
wire [0:q_num_entries_g-1] q_entry_load1;
wire [0:q_num_entries_g-1] q_entry_hold;
wire [0:q_num_entries_g-1] q_entry_read;
wire [0:q_num_entries_g-1] q_read_dat[0:q_dat_width_g-1];
wire [0:q_num_entries_g-1] q_dat_act;
wire [0:q_dat_width_g-1] q_dat_d[0:q_num_entries_g-1];
wire [0:q_dat_width_g-1] q_dat_q[0:q_num_entries_g-1];
//-------------------------------------------------------------------
// Scanchain
//-------------------------------------------------------------------
parameter q_dat_offset = 0;
parameter scan_right = q_dat_offset + q_num_entries_g * q_dat_width_g;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
//-------------------------------------------------------------------------------------------------------
// Notes
//-------------------------------------------------------------------------------------------------------
//
//-------------------------------------------------------------------------------------------------------
// misc
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
// Latch write data
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
// Write aoi
//-------------------------------------------------------------------------------------------------------
generate
begin : xhdl1
genvar n;
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_dat_gen
wire [0:q_barf_enc_g-1] id= n;
assign q_entry_load0[n] = (w0_addr == id) & w0_en;
assign q_entry_load1[n] = (w1_addr == id) & w1_en;
assign q_entry_hold[n] = (~q_entry_load0[n]) & (~q_entry_load1[n]);
assign q_dat_d[n] = (w0_dat & {q_dat_width_g{q_entry_load0[n]}}) |
(w1_dat & {q_dat_width_g{q_entry_load1[n]}}) |
(q_dat_q[n] & {q_dat_width_g{q_entry_hold[n]}}); //feedback
assign q_dat_act[n] = w_act[n];
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// Read Mux
//-------------------------------------------------------------------------------------------------------
generate
begin : xhdl1r
genvar n, b;
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : rgene
wire [0:q_barf_enc_g-1] idd= n;
//onehot addr
assign q_entry_read[n] = (r0_addr == idd);
for (b = 0; b <= (q_dat_width_g - 1); b = b + 1)
begin : rgenb
//AND
assign q_read_dat[b][n] = q_dat_q[n][b] & q_entry_read[n];
end
end
end
endgenerate
generate
begin : xhdl1o
genvar b;
for (b = 0; b <= (q_dat_width_g - 1); b = b + 1)
begin : rgeneo
//OR
assign r0_dat[b] = |(q_read_dat[b]);
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// storage elements
//-------------------------------------------------------------------------------------------------------
generate
begin : xhdl2
genvar n;
for (n = 0; n <= q_num_entries_g - 1; n = n + 1)
begin : q_x_q_gen
tri_plat #(.WIDTH(2))
perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(ccflush_dc),
.din({func_sl_thold_1, sg_1}),
.q({func_sl_thold_0[n], sg_0[n]})
);
tri_lcbor
perv_lcbor(
.clkoff_b(clkoff_b),
.thold(func_sl_thold_0[n]),
.sg(sg_0[n]),
.act_dis(act_dis),
.force_t(force_t[n]),
.thold_b(func_sl_thold_0_b[n])
);
tri_rlmreg_p #(.WIDTH(q_dat_width_g), .INIT(0))
q_dat_q_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(q_dat_act[n]),
.thold_b(func_sl_thold_0_b[n]),
.sg(sg_0[n]),
.force_t(force_t[n]),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[q_dat_offset + q_dat_width_g * n:q_dat_offset + q_dat_width_g * (n + 1) - 1]),
.scout(sov[q_dat_offset + q_dat_width_g * n:q_dat_offset + q_dat_width_g * (n + 1) - 1]),
.din(q_dat_d[n]),
.dout(q_dat_q[n])
);
end
end
endgenerate
//---------------------------------------------------------------------
// Scan
//---------------------------------------------------------------------
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
endmodule |
module c_perv_rp(
// Include model build parameters
`include "tri_a2o.vh"
// inout vdd,
// inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
//CLOCK CONTROLS
//Top level clock controls
input an_ac_ccflush_dc,
input rtim_sl_thold_8,
input func_sl_thold_8,
input func_nsl_thold_8,
input ary_nsl_thold_8,
input sg_8,
input fce_8,
output rtim_sl_thold_7,
output func_sl_thold_7,
output func_nsl_thold_7,
output ary_nsl_thold_7,
output sg_7,
output fce_7,
//Thold inputs from pcq clock controls
input pc_rp_ccflush_out_dc,
input pc_rp_gptr_sl_thold_4,
input pc_rp_time_sl_thold_4,
input pc_rp_repr_sl_thold_4,
input pc_rp_abst_sl_thold_4,
input pc_rp_abst_slp_sl_thold_4,
input pc_rp_regf_sl_thold_4,
input pc_rp_regf_slp_sl_thold_4,
input pc_rp_func_sl_thold_4,
input pc_rp_func_slp_sl_thold_4,
input pc_rp_cfg_sl_thold_4,
input pc_rp_cfg_slp_sl_thold_4,
input pc_rp_func_nsl_thold_4,
input pc_rp_func_slp_nsl_thold_4,
input pc_rp_ary_nsl_thold_4,
input pc_rp_ary_slp_nsl_thold_4,
input pc_rp_rtim_sl_thold_4,
input pc_rp_sg_4,
input pc_rp_fce_4,
//Thold outputs to the units
output rp_iu_ccflush_dc,
output rp_iu_gptr_sl_thold_3,
output rp_iu_time_sl_thold_3,
output rp_iu_repr_sl_thold_3,
output rp_iu_abst_sl_thold_3,
output rp_iu_abst_slp_sl_thold_3,
output rp_iu_regf_slp_sl_thold_3,
output rp_iu_func_sl_thold_3,
output rp_iu_func_slp_sl_thold_3,
output rp_iu_cfg_sl_thold_3,
output rp_iu_cfg_slp_sl_thold_3,
output rp_iu_func_nsl_thold_3,
output rp_iu_func_slp_nsl_thold_3,
output rp_iu_ary_nsl_thold_3,
output rp_iu_ary_slp_nsl_thold_3,
output rp_iu_sg_3,
output rp_iu_fce_3,
//
output rp_rv_ccflush_dc,
output rp_rv_gptr_sl_thold_3,
output rp_rv_time_sl_thold_3,
output rp_rv_repr_sl_thold_3,
output rp_rv_abst_sl_thold_3,
output rp_rv_abst_slp_sl_thold_3,
output rp_rv_func_sl_thold_3,
output rp_rv_func_slp_sl_thold_3,
output rp_rv_cfg_sl_thold_3,
output rp_rv_cfg_slp_sl_thold_3,
output rp_rv_func_nsl_thold_3,
output rp_rv_func_slp_nsl_thold_3,
output rp_rv_ary_nsl_thold_3,
output rp_rv_ary_slp_nsl_thold_3,
output rp_rv_sg_3,
output rp_rv_fce_3,
//
output rp_xu_ccflush_dc,
output rp_xu_gptr_sl_thold_3,
output rp_xu_time_sl_thold_3,
output rp_xu_repr_sl_thold_3,
output rp_xu_abst_sl_thold_3,
output rp_xu_abst_slp_sl_thold_3,
output rp_xu_regf_slp_sl_thold_3,
output rp_xu_func_sl_thold_3,
output rp_xu_func_slp_sl_thold_3,
output rp_xu_cfg_sl_thold_3,
output rp_xu_cfg_slp_sl_thold_3,
output rp_xu_func_nsl_thold_3,
output rp_xu_func_slp_nsl_thold_3,
output rp_xu_ary_nsl_thold_3,
output rp_xu_ary_slp_nsl_thold_3,
output rp_xu_sg_3,
output rp_xu_fce_3,
//
output rp_lq_ccflush_dc,
output rp_lq_gptr_sl_thold_3,
output rp_lq_time_sl_thold_3,
output rp_lq_repr_sl_thold_3,
output rp_lq_abst_sl_thold_3,
output rp_lq_abst_slp_sl_thold_3,
output rp_lq_regf_slp_sl_thold_3,
output rp_lq_func_sl_thold_3,
output rp_lq_func_slp_sl_thold_3,
output rp_lq_cfg_sl_thold_3,
output rp_lq_cfg_slp_sl_thold_3,
output rp_lq_func_nsl_thold_3,
output rp_lq_func_slp_nsl_thold_3,
output rp_lq_ary_nsl_thold_3,
output rp_lq_ary_slp_nsl_thold_3,
output rp_lq_sg_3,
output rp_lq_fce_3,
//
output rp_mm_ccflush_dc,
output rp_mm_gptr_sl_thold_3,
output rp_mm_time_sl_thold_3,
output rp_mm_repr_sl_thold_3,
output rp_mm_abst_sl_thold_3,
output rp_mm_abst_slp_sl_thold_3,
output rp_mm_func_sl_thold_3,
output rp_mm_func_slp_sl_thold_3,
output rp_mm_cfg_sl_thold_3,
output rp_mm_cfg_slp_sl_thold_3,
output rp_mm_func_nsl_thold_3,
output rp_mm_func_slp_nsl_thold_3,
output rp_mm_ary_nsl_thold_3,
output rp_mm_ary_slp_nsl_thold_3,
output rp_mm_sg_3,
output rp_mm_fce_3,
//SCANRING REPOWERING
input pc_bcfg_scan_in,
output pc_bcfg_scan_in_q,
input pc_dcfg_scan_in,
output pc_dcfg_scan_in_q,
input pc_bcfg_scan_out,
output pc_bcfg_scan_out_q,
input pc_ccfg_scan_out,
output pc_ccfg_scan_out_q,
input pc_dcfg_scan_out,
output pc_dcfg_scan_out_q,
input [0:1] pc_func_scan_in,
output [0:1] pc_func_scan_in_q,
input [0:1] pc_func_scan_out,
output [0:1] pc_func_scan_out_q,
//
input fu_abst_scan_in,
output fu_abst_scan_in_q,
input fu_abst_scan_out,
output fu_abst_scan_out_q,
input fu_ccfg_scan_out,
output fu_ccfg_scan_out_q,
input fu_bcfg_scan_out,
output fu_bcfg_scan_out_q,
input fu_dcfg_scan_out,
output fu_dcfg_scan_out_q,
input [0:3] fu_func_scan_in,
output [0:3] fu_func_scan_in_q,
input [0:3] fu_func_scan_out,
output [0:3] fu_func_scan_out_q,
//MISCELLANEOUS FUNCTIONAL SIGNALS
// node inputs going to pcq
input an_ac_scom_dch,
input an_ac_scom_cch,
input an_ac_checkstop,
input an_ac_debug_stop,
input [0:`THREADS-1] an_ac_pm_thread_stop,
input [0:`THREADS-1] an_ac_pm_fetch_halt,
//
output rp_pc_scom_dch_q,
output rp_pc_scom_cch_q,
output rp_pc_checkstop_q,
output rp_pc_debug_stop_q,
output [0:`THREADS-1] rp_pc_pm_thread_stop_q,
output [0:`THREADS-1] rp_pc_pm_fetch_halt_q,
// pcq outputs going to node
input pc_rp_scom_dch,
input pc_rp_scom_cch,
input [0:`THREADS-1] pc_rp_special_attn,
input [0:2] pc_rp_checkstop,
input [0:2] pc_rp_local_checkstop,
input [0:2] pc_rp_recov_err,
input pc_rp_trace_error,
input [0:`THREADS-1] pc_rp_pm_thread_running,
input pc_rp_power_managed,
input pc_rp_rvwinkle_mode,
input pc_rp_livelock_active,
//
output ac_an_scom_dch_q,
output ac_an_scom_cch_q,
output [0:`THREADS-1] ac_an_special_attn_q,
output [0:2] ac_an_checkstop_q,
output [0:2] ac_an_local_checkstop_q,
output [0:2] ac_an_recov_err_q,
output ac_an_trace_error_q,
output [0:`THREADS-1] ac_an_pm_thread_running_q,
output ac_an_power_managed_q,
output ac_an_rvwinkle_mode_q,
output ac_an_livelock_active_q,
// SCAN CHAINS
input scan_diag_dc,
input scan_dis_dc_b,
input func_scan_in,
input gptr_scan_in,
output func_scan_out,
output gptr_scan_out
);
//=====================================================================
// Signal Declarations
//=====================================================================
// FUNC Scan Ring
parameter FUNC2_T0_SIZE = 23;
parameter FUNC2_T1_SIZE = 4 * (`THREADS - 1);
// start of func scan chain ordering
parameter FUNC2_T0_OFFSET = 0;
parameter FUNC2_T1_OFFSET = FUNC2_T0_OFFSET + FUNC2_T0_SIZE;
parameter FUNC_RIGHT = FUNC2_T1_OFFSET + FUNC2_T1_SIZE - 1;
// end of func scan chain ordering
// Power signals
wire vdd;
wire gnd;
assign vdd = 1'b1;
assign gnd = 1'b0;
// Clock and Scan Signals
wire [0:FUNC_RIGHT] func_siv;
wire [0:FUNC_RIGHT] func_sov;
//
wire slat_force;
wire func_slat_thold_b;
wire func_slat_d2clk;
wire [0:`NCLK_WIDTH-1] func_slat_lclk;
wire abst_slat_thold_b;
wire abst_slat_d2clk;
wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
wire cfg_slat_thold_b;
wire cfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
//
wire sg_3_int;
wire func_sl_thold_3_int;
wire func_slp_sl_thold_3_int;
wire abst_sl_thold_3_int;
wire gptr_sl_thold_3_int;
wire cfg_sl_thold_3_int;
wire sg_2;
wire func_sl_thold_2;
wire func_slp_sl_thold_2;
wire abst_sl_thold_2;
wire gptr_sl_thold_2;
wire cfg_sl_thold_2;
wire sg_1;
wire func_sl_thold_1;
wire func_slp_sl_thold_1;
wire gptr_sl_thold_1;
wire abst_sl_thold_1;
wire cfg_sl_thold_1;
wire sg_0;
wire func_sl_thold_0;
wire func_sl_thold_0_b;
wire force_func;
wire func_slp_sl_thold_0;
wire func_slp_sl_thold_0_b;
wire force_func_slp;
wire gptr_sl_thold_0;
wire abst_sl_thold_0;
wire abst_sl_thold_0_b;
wire force_abst;
wire cfg_sl_thold_0;
//
wire clkoff_b;
wire act_dis;
wire d_mode;
wire [0:4] delay_lclkr;
wire [0:4] mpw1_b;
wire mpw2_b;
// Get rid of sinkless net messages
(* analysis_not_referenced="true" *)
wire unused;
assign unused = pc_rp_regf_sl_thold_4 | pc_rp_rtim_sl_thold_4 | d_mode | (|delay_lclkr[1:4]) | (|mpw1_b[1:4]);
// *****************************************************************************
// INTERNALLY USED CLOCK CONTROLS
// *****************************************************************************
// Thold/Sg Staging latches
tri_plat #(.WIDTH(6)) perv_4to3_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(pc_rp_ccflush_out_dc),
.din({pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_gptr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_sg_4 }),
.q( {func_sl_thold_3_int, func_slp_sl_thold_3_int, gptr_sl_thold_3_int,
abst_sl_thold_3_int, cfg_sl_thold_3_int, sg_3_int })
);
tri_plat #(.WIDTH(6)) perv_3to2_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(pc_rp_ccflush_out_dc),
.din({func_sl_thold_3_int, func_slp_sl_thold_3_int, gptr_sl_thold_3_int,
abst_sl_thold_3_int, cfg_sl_thold_3_int, sg_3_int }),
.q( {func_sl_thold_2, func_slp_sl_thold_2, gptr_sl_thold_2,
abst_sl_thold_2, cfg_sl_thold_2, sg_2 })
);
tri_plat #(.WIDTH(6)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(pc_rp_ccflush_out_dc),
.din({func_sl_thold_2, func_slp_sl_thold_2, gptr_sl_thold_2,
abst_sl_thold_2, cfg_sl_thold_2, sg_2 }),
.q( {func_sl_thold_1, func_slp_sl_thold_1, gptr_sl_thold_1,
abst_sl_thold_1, cfg_sl_thold_1, sg_1 })
);
tri_plat #(.WIDTH(6)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(pc_rp_ccflush_out_dc),
.din({func_sl_thold_1, func_slp_sl_thold_1, gptr_sl_thold_1,
abst_sl_thold_1, cfg_sl_thold_1, sg_1 }),
.q( {func_sl_thold_0, func_slp_sl_thold_0, gptr_sl_thold_0,
abst_sl_thold_0, cfg_sl_thold_0, sg_0 })
);
// LCBCNTRL Macro
tri_lcbcntl_mac perv_lcbcntl(
.vdd(vdd),
.gnd(gnd),
.sg(sg_0),
.nclk(nclk),
.scan_in(gptr_scan_in),
.scan_diag_dc(scan_diag_dc),
.thold(gptr_sl_thold_0),
.clkoff_dc_b(clkoff_b),
.delay_lclkr_dc(delay_lclkr[0:4]),
.act_dis_dc(act_dis),
.d_mode_dc(d_mode),
.mpw1_dc_b(mpw1_b[0:4]),
.mpw2_dc_b(mpw2_b),
.scan_out(gptr_scan_out)
);
// LCBORs
tri_lcbor abst_lcbor(
.clkoff_b(clkoff_b),
.thold(abst_sl_thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_abst),
.thold_b(abst_sl_thold_0_b)
);
tri_lcbor func_lcbor(
.clkoff_b(clkoff_b),
.thold(func_sl_thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_func),
.thold_b(func_sl_thold_0_b)
);
tri_lcbor func_slp_lcbor(
.clkoff_b(clkoff_b),
.thold(func_slp_sl_thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_func_slp),
.thold_b(func_slp_sl_thold_0_b)
);
// LCBs for scan only staging latches
assign slat_force = sg_0;
assign func_slat_thold_b = (~func_sl_thold_0);
assign abst_slat_thold_b = (~abst_sl_thold_0);
assign cfg_slat_thold_b = (~cfg_sl_thold_0);
tri_lcbs lcbs_func(
.vd(vdd),
.gd(gnd),
.delay_lclkr(delay_lclkr[0]),
.nclk(nclk),
.force_t(slat_force),
.thold_b(func_slat_thold_b),
.dclk(func_slat_d2clk),
.lclk(func_slat_lclk)
);
tri_lcbs lcbs_abst(
.vd(vdd),
.gd(gnd),
.delay_lclkr(delay_lclkr[0]),
.nclk(nclk),
.force_t(slat_force),
.thold_b(abst_slat_thold_b),
.dclk(abst_slat_d2clk),
.lclk(abst_slat_lclk)
);
tri_lcbs lcbs_cfg(
.vd(vdd),
.gd(gnd),
.delay_lclkr(delay_lclkr[0]),
.nclk(nclk),
.force_t(slat_force),
.thold_b(cfg_slat_thold_b),
.dclk(cfg_slat_d2clk),
.lclk(cfg_slat_lclk)
);
// *****************************************************************************
// CLOCK REPOWERING LOGIC
// *****************************************************************************
// Stages pcq clock control inputs
tri_plat #(.WIDTH(6)) pcq_lvl8to7(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(an_ac_ccflush_dc),
.din({rtim_sl_thold_8, func_sl_thold_8, func_nsl_thold_8,
ary_nsl_thold_8, sg_8, fce_8 }),
.q( {rtim_sl_thold_7, func_sl_thold_7, func_nsl_thold_7,
ary_nsl_thold_7, sg_7, fce_7 })
);
// Other units use the ccflush signal after being gated for power-savings operation
assign rp_iu_ccflush_dc = pc_rp_ccflush_out_dc;
assign rp_rv_ccflush_dc = pc_rp_ccflush_out_dc;
assign rp_xu_ccflush_dc = pc_rp_ccflush_out_dc;
assign rp_lq_ccflush_dc = pc_rp_ccflush_out_dc;
assign rp_mm_ccflush_dc = pc_rp_ccflush_out_dc;
// Clock control 4to3 output staging
tri_plat #(.WIDTH(16)) iu_clkstg_4to3(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(pc_rp_ccflush_out_dc),
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4,
pc_rp_ary_nsl_thold_4, pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
.q( {rp_iu_gptr_sl_thold_3, rp_iu_time_sl_thold_3, rp_iu_repr_sl_thold_3,
rp_iu_abst_sl_thold_3, rp_iu_abst_slp_sl_thold_3, rp_iu_regf_slp_sl_thold_3,
rp_iu_func_sl_thold_3, rp_iu_func_slp_sl_thold_3, rp_iu_cfg_sl_thold_3,
rp_iu_cfg_slp_sl_thold_3, rp_iu_func_nsl_thold_3, rp_iu_func_slp_nsl_thold_3,
rp_iu_ary_nsl_thold_3, rp_iu_ary_slp_nsl_thold_3, rp_iu_sg_3, rp_iu_fce_3 })
);
tri_plat #(.WIDTH(15)) rv_clkstg_4to3(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(pc_rp_ccflush_out_dc),
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4,
pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4,
pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4, pc_rp_ary_nsl_thold_4,
pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
.q( {rp_rv_gptr_sl_thold_3, rp_rv_time_sl_thold_3, rp_rv_repr_sl_thold_3,
rp_rv_abst_sl_thold_3, rp_rv_abst_slp_sl_thold_3, rp_rv_func_sl_thold_3,
rp_rv_func_slp_sl_thold_3, rp_rv_cfg_sl_thold_3, rp_rv_cfg_slp_sl_thold_3,
rp_rv_func_nsl_thold_3, rp_rv_func_slp_nsl_thold_3, rp_rv_ary_nsl_thold_3,
rp_rv_ary_slp_nsl_thold_3, rp_rv_sg_3, rp_rv_fce_3 })
);
tri_plat #(.WIDTH(16)) xu_clkstg_4to3(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(pc_rp_ccflush_out_dc),
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4,
pc_rp_ary_nsl_thold_4, pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
.q( {rp_xu_gptr_sl_thold_3, rp_xu_time_sl_thold_3, rp_xu_repr_sl_thold_3,
rp_xu_abst_sl_thold_3, rp_xu_abst_slp_sl_thold_3, rp_xu_regf_slp_sl_thold_3,
rp_xu_func_sl_thold_3, rp_xu_func_slp_sl_thold_3, rp_xu_cfg_sl_thold_3,
rp_xu_cfg_slp_sl_thold_3, rp_xu_func_nsl_thold_3, rp_xu_func_slp_nsl_thold_3,
rp_xu_ary_nsl_thold_3, rp_xu_ary_slp_nsl_thold_3, rp_xu_sg_3, rp_xu_fce_3 })
);
tri_plat #(.WIDTH(16)) lq_clkstg_4to3(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(pc_rp_ccflush_out_dc),
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4,
pc_rp_ary_nsl_thold_4, pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
.q( {rp_lq_gptr_sl_thold_3, rp_lq_time_sl_thold_3, rp_lq_repr_sl_thold_3,
rp_lq_abst_sl_thold_3, rp_lq_abst_slp_sl_thold_3, rp_lq_regf_slp_sl_thold_3,
rp_lq_func_sl_thold_3, rp_lq_func_slp_sl_thold_3, rp_lq_cfg_sl_thold_3,
rp_lq_cfg_slp_sl_thold_3, rp_lq_func_nsl_thold_3, rp_lq_func_slp_nsl_thold_3,
rp_lq_ary_nsl_thold_3, rp_lq_ary_slp_nsl_thold_3, rp_lq_sg_3, rp_lq_fce_3 })
);
tri_plat #(.WIDTH(15)) mm_clkstg_4to3(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(pc_rp_ccflush_out_dc),
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4,
pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4,
pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4, pc_rp_ary_nsl_thold_4,
pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
.q( {rp_mm_gptr_sl_thold_3, rp_mm_time_sl_thold_3, rp_mm_repr_sl_thold_3,
rp_mm_abst_sl_thold_3, rp_mm_abst_slp_sl_thold_3, rp_mm_func_sl_thold_3,
rp_mm_func_slp_sl_thold_3, rp_mm_cfg_sl_thold_3, rp_mm_cfg_slp_sl_thold_3,
rp_mm_func_nsl_thold_3, rp_mm_func_slp_nsl_thold_3, rp_mm_ary_nsl_thold_3,
rp_mm_ary_slp_nsl_thold_3, rp_mm_sg_3, rp_mm_fce_3 })
);
// *****************************************************************************
// SCANRING REPOWERING
// *****************************************************************************
// Staging latches for scan_in/out signals on abist rings
tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) fu_abst_stg(
.vd(vdd),
.gd(gnd),
.dclk(abst_slat_d2clk),
.lclk(abst_slat_lclk),
.scan_in( {fu_abst_scan_in, fu_abst_scan_out }),
.scan_out({fu_abst_scan_in_q, fu_abst_scan_out_q })
);
// Staging latches for scan_in/out signals on func rings
tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) pc_func_stg(
.vd(vdd),
.gd(gnd),
.dclk(func_slat_d2clk),
.lclk(func_slat_lclk),
.scan_in( {pc_func_scan_in[0:1], pc_func_scan_out[0:1] }),
.scan_out({pc_func_scan_in_q[0:1], pc_func_scan_out_q[0:1] })
);
tri_slat_scan #(.WIDTH(8), .INIT(8'b00000000)) fu_func_stg(
.vd(vdd),
.gd(gnd),
.dclk(func_slat_d2clk),
.lclk(func_slat_lclk),
.scan_in( {fu_func_scan_in[0:3], fu_func_scan_out[0:3] }),
.scan_out({fu_func_scan_in_q[0:3], fu_func_scan_out_q[0:3] })
);
// Staging latches for scan_in/out signals on config rings
tri_slat_scan #(.WIDTH(5), .INIT(5'b00000)) pc_cfg_stg(
.vd(vdd),
.gd(gnd),
.dclk(cfg_slat_d2clk),
.lclk(cfg_slat_lclk),
.scan_in( {pc_bcfg_scan_in, pc_dcfg_scan_in, pc_bcfg_scan_out,
pc_ccfg_scan_out, pc_dcfg_scan_out }),
.scan_out({pc_bcfg_scan_in_q, pc_dcfg_scan_in_q, pc_bcfg_scan_out_q,
pc_ccfg_scan_out_q, pc_dcfg_scan_out_q })
);
tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) fu_cfg_stg(
.vd(vdd),
.gd(gnd),
.dclk(cfg_slat_d2clk),
.lclk(cfg_slat_lclk),
.scan_in( {fu_bcfg_scan_out, fu_ccfg_scan_out, fu_dcfg_scan_out }),
.scan_out({fu_bcfg_scan_out_q, fu_ccfg_scan_out_q, fu_dcfg_scan_out_q })
);
// *****************************************************************************
// MISCELLANEOUS FUNCTIONAL SIGNALS
// *****************************************************************************
tri_rlmreg_p #(.WIDTH(FUNC2_T0_SIZE), .INIT(0)) func2_t0_rp(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(1'b1),
.thold_b(func_slp_sl_thold_0_b),
.sg(sg_0),
.force_t(force_func_slp),
.delay_lclkr(delay_lclkr[0]),
.mpw1_b(mpw1_b[0]),
.mpw2_b(mpw2_b),
.scin(func_siv[ FUNC2_T0_OFFSET:FUNC2_T0_OFFSET + FUNC2_T0_SIZE - 1]),
.scout(func_sov[FUNC2_T0_OFFSET:FUNC2_T0_OFFSET + FUNC2_T0_SIZE - 1]),
.din( {an_ac_scom_dch, an_ac_scom_cch, an_ac_checkstop,
an_ac_debug_stop, pc_rp_scom_dch, pc_rp_scom_cch,
pc_rp_checkstop, pc_rp_local_checkstop, pc_rp_recov_err,
pc_rp_power_managed, pc_rp_rvwinkle_mode, pc_rp_trace_error,
pc_rp_livelock_active, an_ac_pm_thread_stop[0], pc_rp_pm_thread_running[0],
pc_rp_special_attn[0], an_ac_pm_fetch_halt[0] }),
.dout({rp_pc_scom_dch_q, rp_pc_scom_cch_q, rp_pc_checkstop_q,
rp_pc_debug_stop_q, ac_an_scom_dch_q, ac_an_scom_cch_q,
ac_an_checkstop_q, ac_an_local_checkstop_q, ac_an_recov_err_q,
ac_an_power_managed_q, ac_an_rvwinkle_mode_q, ac_an_trace_error_q,
ac_an_livelock_active_q, rp_pc_pm_thread_stop_q[0], ac_an_pm_thread_running_q[0],
ac_an_special_attn_q[0], rp_pc_pm_fetch_halt_q[0] })
);
generate
if (`THREADS == 2)
begin : t1_rp
tri_rlmreg_p #(.WIDTH(FUNC2_T1_SIZE), .INIT(0)) func2_t1_rp(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(1'b1),
.thold_b(func_slp_sl_thold_0_b),
.sg(sg_0),
.force_t(force_func_slp),
.delay_lclkr(delay_lclkr[0]),
.mpw1_b(mpw1_b[0]),
.mpw2_b(mpw2_b),
.scin(func_siv[ FUNC2_T1_OFFSET:FUNC2_T1_OFFSET + FUNC2_T1_SIZE - 1]),
.scout(func_sov[FUNC2_T1_OFFSET:FUNC2_T1_OFFSET + FUNC2_T1_SIZE - 1]),
.din( {an_ac_pm_thread_stop[1], pc_rp_pm_thread_running[1], pc_rp_special_attn[1],
an_ac_pm_fetch_halt[1] }),
.dout({rp_pc_pm_thread_stop_q[1], ac_an_pm_thread_running_q[1], ac_an_special_attn_q[1],
rp_pc_pm_fetch_halt_q[1] })
);
end
endgenerate
// *****************************************************************************
// SCAN RING CONNECTIONS
// *****************************************************************************
//func ring
assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]};
assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b;
endmodule |
module fu_alg_sh16(
ex3_lvl3_shdcd000,
ex3_lvl3_shdcd016,
ex3_lvl3_shdcd032,
ex3_lvl3_shdcd048,
ex3_lvl3_shdcd064,
ex3_lvl3_shdcd080,
ex3_lvl3_shdcd096,
ex3_lvl3_shdcd112,
ex3_lvl3_shdcd128,
ex3_lvl3_shdcd144,
ex3_lvl3_shdcd160,
ex3_lvl3_shdcd192,
ex3_lvl3_shdcd208,
ex3_lvl3_shdcd224,
ex3_lvl3_shdcd240,
ex3_sel_special,
ex3_sh_lvl2,
ex3_sh16_162,
ex3_sh16_163,
ex3_sh_lvl3
);
//--------- SHIFT CONTROLS -----------------
input ex3_lvl3_shdcd000;
input ex3_lvl3_shdcd016;
input ex3_lvl3_shdcd032;
input ex3_lvl3_shdcd048;
input ex3_lvl3_shdcd064;
input ex3_lvl3_shdcd080;
input ex3_lvl3_shdcd096;
input ex3_lvl3_shdcd112;
input ex3_lvl3_shdcd128;
input ex3_lvl3_shdcd144;
input ex3_lvl3_shdcd160;
input ex3_lvl3_shdcd192;
input ex3_lvl3_shdcd208;
input ex3_lvl3_shdcd224;
input ex3_lvl3_shdcd240;
input ex3_sel_special;
//--------- SHIFT DATA -----------------
input [0:67] ex3_sh_lvl2;
//-------- SHIFT OUTPUT ---------------
output ex3_sh16_162;
output ex3_sh16_163;
output [0:162] ex3_sh_lvl3;
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:162] ex3_sh16_r1_b;
wire [0:162] ex3_sh16_r2_b;
wire [0:162] ex3_sh16_r3_b;
wire [99:162] ex3_special;
wire cpx_spc_b;
wire cpx_000_b;
wire cpx_016_b;
wire cpx_032_b;
wire cpx_048_b;
wire cpx_064_b;
wire cpx_080_b;
wire cpx_096_b;
wire cpx_112_b;
wire cpx_128_b;
wire cpx_144_b;
wire cpx_160_b;
wire cpx_192_b;
wire cpx_208_b;
wire cpx_224_b;
wire cpx_240_b;
wire cp1_spc;
wire cp1_000;
wire cp1_016;
wire cp1_032;
wire cp1_048;
wire cp1_064;
wire cp1_080;
wire cp1_096;
wire cp1_112;
wire cp1_128;
wire cp1_144;
wire cp1_160;
wire cp1_192;
wire cp1_208;
wire cp1_224;
wire cp1_240;
wire cp2_spc;
wire cp2_000;
wire cp2_016;
wire cp2_032;
wire cp2_048;
wire cp2_064;
wire cp2_080;
wire cp2_096;
wire cp2_112;
wire cp2_128;
wire cp2_144;
wire cp2_208;
wire cp2_224;
wire cp2_240;
wire cp3_spc;
wire cp3_000;
wire cp3_016;
wire cp3_032;
wire cp3_048;
wire cp3_064;
wire cp3_080;
wire cp3_096;
wire cp3_112;
wire cp3_128;
wire cp3_224;
wire cp3_240;
wire cp4_spc;
wire cp4_000;
wire cp4_016;
wire cp4_032;
wire cp4_048;
wire cp4_064;
wire cp4_080;
wire cp4_096;
wire cp4_112;
wire cp4_240;
wire cp5_spc;
wire cp5_000;
wire cp5_016;
wire cp5_032;
wire cp5_048;
wire cp5_064;
wire cp5_080;
wire cp5_096;
wire ex3_sh16_r1_162_b;
wire ex3_sh16_r2_162_b;
wire ex3_sh16_r3_162_b;
wire ex3_sh16_r1_163_b;
wire ex3_sh16_r2_163_b;
wire ex3_sh16_r3_163_b;
////################################################################
////# map block attributes
////################################################################
////#-------------------------------------------------
////# finish shifting
////#-------------------------------------------------
// this looks more like a 53:1 mux than a shifter to shrink it, and lower load on selects
// real implementation should be nand/nand/nor ... ?? integrate nor into latch ??
assign ex3_special[99:162] = ex3_sh_lvl2[0:63]; // just a rename
////#-----------------------------------------------------------------
////# repower select signal
////#-----------------------------------------------------------------
assign cpx_spc_b = (~ex3_sel_special);
assign cpx_000_b = (~ex3_lvl3_shdcd000);
assign cpx_016_b = (~ex3_lvl3_shdcd016);
assign cpx_032_b = (~ex3_lvl3_shdcd032);
assign cpx_048_b = (~ex3_lvl3_shdcd048);
assign cpx_064_b = (~ex3_lvl3_shdcd064);
assign cpx_080_b = (~ex3_lvl3_shdcd080);
assign cpx_096_b = (~ex3_lvl3_shdcd096);
assign cpx_112_b = (~ex3_lvl3_shdcd112);
assign cpx_128_b = (~ex3_lvl3_shdcd128);
assign cpx_144_b = (~ex3_lvl3_shdcd144);
assign cpx_160_b = (~ex3_lvl3_shdcd160);
assign cpx_192_b = (~ex3_lvl3_shdcd192);
assign cpx_208_b = (~ex3_lvl3_shdcd208);
assign cpx_224_b = (~ex3_lvl3_shdcd224);
assign cpx_240_b = (~ex3_lvl3_shdcd240);
assign cp1_spc = (~cpx_spc_b);
assign cp1_000 = (~cpx_000_b);
assign cp1_016 = (~cpx_016_b);
assign cp1_032 = (~cpx_032_b);
assign cp1_048 = (~cpx_048_b);
assign cp1_064 = (~cpx_064_b);
assign cp1_080 = (~cpx_080_b);
assign cp1_096 = (~cpx_096_b);
assign cp1_112 = (~cpx_112_b);
assign cp1_128 = (~cpx_128_b);
assign cp1_144 = (~cpx_144_b);
assign cp1_160 = (~cpx_160_b);
assign cp1_192 = (~cpx_192_b);
assign cp1_208 = (~cpx_208_b);
assign cp1_224 = (~cpx_224_b);
assign cp1_240 = (~cpx_240_b);
assign cp2_spc = (~cpx_spc_b);
assign cp2_000 = (~cpx_000_b);
assign cp2_016 = (~cpx_016_b);
assign cp2_032 = (~cpx_032_b);
assign cp2_048 = (~cpx_048_b);
assign cp2_064 = (~cpx_064_b);
assign cp2_080 = (~cpx_080_b);
assign cp2_096 = (~cpx_096_b);
assign cp2_112 = (~cpx_112_b);
assign cp2_128 = (~cpx_128_b);
assign cp2_144 = (~cpx_144_b);
assign cp2_208 = (~cpx_208_b);
assign cp2_224 = (~cpx_224_b);
assign cp2_240 = (~cpx_240_b);
assign cp3_spc = (~cpx_spc_b);
assign cp3_000 = (~cpx_000_b);
assign cp3_016 = (~cpx_016_b);
assign cp3_032 = (~cpx_032_b);
assign cp3_048 = (~cpx_048_b);
assign cp3_064 = (~cpx_064_b);
assign cp3_080 = (~cpx_080_b);
assign cp3_096 = (~cpx_096_b);
assign cp3_112 = (~cpx_112_b);
assign cp3_128 = (~cpx_128_b);
assign cp3_224 = (~cpx_224_b);
assign cp3_240 = (~cpx_240_b);
assign cp4_spc = (~cpx_spc_b);
assign cp4_000 = (~cpx_000_b);
assign cp4_016 = (~cpx_016_b);
assign cp4_032 = (~cpx_032_b);
assign cp4_048 = (~cpx_048_b);
assign cp4_064 = (~cpx_064_b);
assign cp4_080 = (~cpx_080_b);
assign cp4_096 = (~cpx_096_b);
assign cp4_112 = (~cpx_112_b);
assign cp4_240 = (~cpx_240_b);
assign cp5_spc = (~cpx_spc_b);
assign cp5_000 = (~cpx_000_b);
assign cp5_016 = (~cpx_016_b);
assign cp5_032 = (~cpx_032_b);
assign cp5_048 = (~cpx_048_b);
assign cp5_064 = (~cpx_064_b);
assign cp5_080 = (~cpx_080_b);
assign cp5_096 = (~cpx_096_b);
//-------------------------------------------------------------------
assign ex3_sh16_r1_b[0] = (~((cp1_192 & ex3_sh_lvl2[64]) | (cp1_208 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[1] = (~((cp1_192 & ex3_sh_lvl2[65]) | (cp1_208 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[2] = (~((cp1_192 & ex3_sh_lvl2[66]) | (cp1_208 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[3] = (~((cp1_192 & ex3_sh_lvl2[67]) | (cp1_208 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[4] = (~(cp1_208 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[5] = (~(cp1_208 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[6] = (~(cp1_208 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[7] = (~(cp1_208 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[8] = (~(cp1_208 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[9] = (~(cp1_208 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[10] = (~(cp1_208 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[11] = (~(cp1_208 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[12] = (~(cp1_208 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[13] = (~(cp1_208 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[14] = (~(cp1_208 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[15] = (~(cp1_208 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[16] = (~((cp2_208 & ex3_sh_lvl2[64]) | (cp2_224 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[17] = (~((cp2_208 & ex3_sh_lvl2[65]) | (cp2_224 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[18] = (~((cp2_208 & ex3_sh_lvl2[66]) | (cp2_224 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[19] = (~((cp2_208 & ex3_sh_lvl2[67]) | (cp2_224 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[20] = (~(cp2_224 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[21] = (~(cp2_224 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[22] = (~(cp2_224 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[23] = (~(cp2_224 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[24] = (~(cp2_224 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[25] = (~(cp2_224 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[26] = (~(cp2_224 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[27] = (~(cp2_224 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[28] = (~(cp2_224 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[29] = (~(cp2_224 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[30] = (~(cp2_224 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[31] = (~(cp2_224 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[32] = (~((cp3_224 & ex3_sh_lvl2[64]) | (cp3_240 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[33] = (~((cp3_224 & ex3_sh_lvl2[65]) | (cp3_240 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[34] = (~((cp3_224 & ex3_sh_lvl2[66]) | (cp3_240 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[35] = (~((cp3_224 & ex3_sh_lvl2[67]) | (cp3_240 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[36] = (~(cp3_240 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[37] = (~(cp3_240 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[38] = (~(cp3_240 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[39] = (~(cp3_240 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[40] = (~(cp3_240 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[41] = (~(cp3_240 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[42] = (~(cp3_240 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[43] = (~(cp3_240 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[44] = (~(cp3_240 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[45] = (~(cp3_240 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[46] = (~(cp3_240 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[47] = (~(cp3_240 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[48] = (~((cp4_240 & ex3_sh_lvl2[64]) | (cp4_000 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[49] = (~((cp4_240 & ex3_sh_lvl2[65]) | (cp4_000 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[50] = (~((cp4_240 & ex3_sh_lvl2[66]) | (cp4_000 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[51] = (~((cp4_240 & ex3_sh_lvl2[67]) | (cp4_000 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[52] = (~(cp4_000 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[53] = (~(cp4_000 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[54] = (~(cp4_000 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[55] = (~(cp4_000 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[56] = (~(cp4_000 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[57] = (~(cp4_000 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[58] = (~(cp4_000 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[59] = (~(cp4_000 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[60] = (~(cp4_000 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[61] = (~(cp4_000 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[62] = (~(cp4_000 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[63] = (~(cp4_000 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[64] = (~((cp5_000 & ex3_sh_lvl2[64]) | (cp4_016 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[65] = (~((cp5_000 & ex3_sh_lvl2[65]) | (cp4_016 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[66] = (~((cp5_000 & ex3_sh_lvl2[66]) | (cp4_016 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[67] = (~((cp5_000 & ex3_sh_lvl2[67]) | (cp4_016 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[68] = (~(cp4_016 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[69] = (~(cp4_016 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[70] = (~(cp4_016 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[71] = (~(cp4_016 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[72] = (~(cp4_016 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[73] = (~(cp4_016 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[74] = (~(cp4_016 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[75] = (~(cp4_016 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[76] = (~(cp4_016 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[77] = (~(cp4_016 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[78] = (~(cp4_016 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[79] = (~(cp4_016 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[80] = (~((cp5_016 & ex3_sh_lvl2[64]) | (cp4_032 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[81] = (~((cp5_016 & ex3_sh_lvl2[65]) | (cp4_032 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[82] = (~((cp5_016 & ex3_sh_lvl2[66]) | (cp4_032 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[83] = (~((cp5_016 & ex3_sh_lvl2[67]) | (cp4_032 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[84] = (~(cp4_032 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[85] = (~(cp4_032 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[86] = (~(cp4_032 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[87] = (~(cp4_032 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[88] = (~(cp4_032 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[89] = (~(cp4_032 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[90] = (~(cp4_032 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[91] = (~(cp4_032 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[92] = (~(cp4_032 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[93] = (~(cp4_032 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[94] = (~(cp4_032 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[95] = (~(cp4_032 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[96] = (~((cp5_032 & ex3_sh_lvl2[64]) | (cp4_048 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[97] = (~((cp5_032 & ex3_sh_lvl2[65]) | (cp4_048 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[98] = (~((cp5_032 & ex3_sh_lvl2[66]) | (cp4_048 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[99] = (~((cp5_032 & ex3_sh_lvl2[67]) | (cp4_048 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[100] = (~(cp4_048 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[101] = (~(cp4_048 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[102] = (~(cp4_048 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[103] = (~(cp4_048 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[104] = (~(cp4_048 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[105] = (~(cp4_048 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[106] = (~(cp4_048 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[107] = (~(cp4_048 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[108] = (~(cp4_048 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[109] = (~(cp4_048 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[110] = (~(cp4_048 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[111] = (~(cp4_048 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[112] = (~((cp5_048 & ex3_sh_lvl2[64]) | (cp4_064 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[113] = (~((cp5_048 & ex3_sh_lvl2[65]) | (cp4_064 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[114] = (~((cp5_048 & ex3_sh_lvl2[66]) | (cp4_064 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[115] = (~((cp5_048 & ex3_sh_lvl2[67]) | (cp4_064 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[116] = (~(cp4_064 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[117] = (~(cp4_064 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[118] = (~(cp4_064 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[119] = (~(cp4_064 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[120] = (~(cp4_064 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[121] = (~(cp4_064 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[122] = (~(cp4_064 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[123] = (~(cp4_064 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[124] = (~(cp4_064 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[125] = (~(cp4_064 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[126] = (~(cp4_064 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[127] = (~(cp4_064 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[128] = (~((cp5_064 & ex3_sh_lvl2[64]) | (cp4_080 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[129] = (~((cp5_064 & ex3_sh_lvl2[65]) | (cp4_080 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[130] = (~((cp5_064 & ex3_sh_lvl2[66]) | (cp4_080 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[131] = (~((cp5_064 & ex3_sh_lvl2[67]) | (cp4_080 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[132] = (~(cp4_080 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[133] = (~(cp4_080 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[134] = (~(cp4_080 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[135] = (~(cp4_080 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[136] = (~(cp4_080 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[137] = (~(cp4_080 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[138] = (~(cp4_080 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[139] = (~(cp4_080 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[140] = (~(cp4_080 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[141] = (~(cp4_080 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[142] = (~(cp4_080 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[143] = (~(cp4_080 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[144] = (~((cp5_080 & ex3_sh_lvl2[64]) | (cp4_096 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[145] = (~((cp5_080 & ex3_sh_lvl2[65]) | (cp4_096 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[146] = (~((cp5_080 & ex3_sh_lvl2[66]) | (cp4_096 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_b[147] = (~((cp5_080 & ex3_sh_lvl2[67]) | (cp4_096 & ex3_sh_lvl2[51])));
assign ex3_sh16_r1_b[148] = (~(cp4_096 & ex3_sh_lvl2[52]));
assign ex3_sh16_r1_b[149] = (~(cp4_096 & ex3_sh_lvl2[53]));
assign ex3_sh16_r1_b[150] = (~(cp4_096 & ex3_sh_lvl2[54]));
assign ex3_sh16_r1_b[151] = (~(cp4_096 & ex3_sh_lvl2[55]));
assign ex3_sh16_r1_b[152] = (~(cp4_096 & ex3_sh_lvl2[56]));
assign ex3_sh16_r1_b[153] = (~(cp4_096 & ex3_sh_lvl2[57]));
assign ex3_sh16_r1_b[154] = (~(cp4_096 & ex3_sh_lvl2[58]));
assign ex3_sh16_r1_b[155] = (~(cp4_096 & ex3_sh_lvl2[59]));
assign ex3_sh16_r1_b[156] = (~(cp4_096 & ex3_sh_lvl2[60]));
assign ex3_sh16_r1_b[157] = (~(cp4_096 & ex3_sh_lvl2[61]));
assign ex3_sh16_r1_b[158] = (~(cp4_096 & ex3_sh_lvl2[62]));
assign ex3_sh16_r1_b[159] = (~(cp4_096 & ex3_sh_lvl2[63]));
assign ex3_sh16_r1_b[160] = (~((cp5_096 & ex3_sh_lvl2[64]) | (cp4_112 & ex3_sh_lvl2[48])));
assign ex3_sh16_r1_b[161] = (~((cp5_096 & ex3_sh_lvl2[65]) | (cp4_112 & ex3_sh_lvl2[49])));
assign ex3_sh16_r1_b[162] = (~((cp5_096 & ex3_sh_lvl2[66]) | (cp4_112 & ex3_sh_lvl2[50])));
assign ex3_sh16_r2_b[0] = (~((cp1_224 & ex3_sh_lvl2[32]) | (cp1_240 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[1] = (~((cp1_224 & ex3_sh_lvl2[33]) | (cp1_240 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[2] = (~((cp1_224 & ex3_sh_lvl2[34]) | (cp1_240 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[3] = (~((cp1_224 & ex3_sh_lvl2[35]) | (cp1_240 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[4] = (~((cp1_224 & ex3_sh_lvl2[36]) | (cp1_240 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[5] = (~((cp1_224 & ex3_sh_lvl2[37]) | (cp1_240 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[6] = (~((cp1_224 & ex3_sh_lvl2[38]) | (cp1_240 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[7] = (~((cp1_224 & ex3_sh_lvl2[39]) | (cp1_240 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[8] = (~((cp1_224 & ex3_sh_lvl2[40]) | (cp1_240 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[9] = (~((cp1_224 & ex3_sh_lvl2[41]) | (cp1_240 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[10] = (~((cp1_224 & ex3_sh_lvl2[42]) | (cp1_240 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[11] = (~((cp1_224 & ex3_sh_lvl2[43]) | (cp1_240 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[12] = (~((cp1_224 & ex3_sh_lvl2[44]) | (cp1_240 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[13] = (~((cp1_224 & ex3_sh_lvl2[45]) | (cp1_240 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[14] = (~((cp1_224 & ex3_sh_lvl2[46]) | (cp1_240 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[15] = (~((cp1_224 & ex3_sh_lvl2[47]) | (cp1_240 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[16] = (~((cp2_240 & ex3_sh_lvl2[32]) | (cp2_000 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[17] = (~((cp2_240 & ex3_sh_lvl2[33]) | (cp2_000 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[18] = (~((cp2_240 & ex3_sh_lvl2[34]) | (cp2_000 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[19] = (~((cp2_240 & ex3_sh_lvl2[35]) | (cp2_000 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[20] = (~((cp2_240 & ex3_sh_lvl2[36]) | (cp2_000 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[21] = (~((cp2_240 & ex3_sh_lvl2[37]) | (cp2_000 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[22] = (~((cp2_240 & ex3_sh_lvl2[38]) | (cp2_000 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[23] = (~((cp2_240 & ex3_sh_lvl2[39]) | (cp2_000 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[24] = (~((cp2_240 & ex3_sh_lvl2[40]) | (cp2_000 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[25] = (~((cp2_240 & ex3_sh_lvl2[41]) | (cp2_000 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[26] = (~((cp2_240 & ex3_sh_lvl2[42]) | (cp2_000 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[27] = (~((cp2_240 & ex3_sh_lvl2[43]) | (cp2_000 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[28] = (~((cp2_240 & ex3_sh_lvl2[44]) | (cp2_000 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[29] = (~((cp2_240 & ex3_sh_lvl2[45]) | (cp2_000 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[30] = (~((cp2_240 & ex3_sh_lvl2[46]) | (cp2_000 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[31] = (~((cp2_240 & ex3_sh_lvl2[47]) | (cp2_000 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[32] = (~((cp3_000 & ex3_sh_lvl2[32]) | (cp2_016 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[33] = (~((cp3_000 & ex3_sh_lvl2[33]) | (cp2_016 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[34] = (~((cp3_000 & ex3_sh_lvl2[34]) | (cp2_016 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[35] = (~((cp3_000 & ex3_sh_lvl2[35]) | (cp2_016 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[36] = (~((cp3_000 & ex3_sh_lvl2[36]) | (cp2_016 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[37] = (~((cp3_000 & ex3_sh_lvl2[37]) | (cp2_016 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[38] = (~((cp3_000 & ex3_sh_lvl2[38]) | (cp2_016 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[39] = (~((cp3_000 & ex3_sh_lvl2[39]) | (cp2_016 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[40] = (~((cp3_000 & ex3_sh_lvl2[40]) | (cp2_016 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[41] = (~((cp3_000 & ex3_sh_lvl2[41]) | (cp2_016 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[42] = (~((cp3_000 & ex3_sh_lvl2[42]) | (cp2_016 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[43] = (~((cp3_000 & ex3_sh_lvl2[43]) | (cp2_016 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[44] = (~((cp3_000 & ex3_sh_lvl2[44]) | (cp2_016 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[45] = (~((cp3_000 & ex3_sh_lvl2[45]) | (cp2_016 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[46] = (~((cp3_000 & ex3_sh_lvl2[46]) | (cp2_016 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[47] = (~((cp3_000 & ex3_sh_lvl2[47]) | (cp2_016 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[48] = (~((cp3_016 & ex3_sh_lvl2[32]) | (cp2_032 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[49] = (~((cp3_016 & ex3_sh_lvl2[33]) | (cp2_032 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[50] = (~((cp3_016 & ex3_sh_lvl2[34]) | (cp2_032 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[51] = (~((cp3_016 & ex3_sh_lvl2[35]) | (cp2_032 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[52] = (~((cp3_016 & ex3_sh_lvl2[36]) | (cp2_032 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[53] = (~((cp3_016 & ex3_sh_lvl2[37]) | (cp2_032 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[54] = (~((cp3_016 & ex3_sh_lvl2[38]) | (cp2_032 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[55] = (~((cp3_016 & ex3_sh_lvl2[39]) | (cp2_032 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[56] = (~((cp3_016 & ex3_sh_lvl2[40]) | (cp2_032 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[57] = (~((cp3_016 & ex3_sh_lvl2[41]) | (cp2_032 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[58] = (~((cp3_016 & ex3_sh_lvl2[42]) | (cp2_032 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[59] = (~((cp3_016 & ex3_sh_lvl2[43]) | (cp2_032 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[60] = (~((cp3_016 & ex3_sh_lvl2[44]) | (cp2_032 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[61] = (~((cp3_016 & ex3_sh_lvl2[45]) | (cp2_032 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[62] = (~((cp3_016 & ex3_sh_lvl2[46]) | (cp2_032 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[63] = (~((cp3_016 & ex3_sh_lvl2[47]) | (cp2_032 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[64] = (~((cp3_032 & ex3_sh_lvl2[32]) | (cp2_048 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[65] = (~((cp3_032 & ex3_sh_lvl2[33]) | (cp2_048 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[66] = (~((cp3_032 & ex3_sh_lvl2[34]) | (cp2_048 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[67] = (~((cp3_032 & ex3_sh_lvl2[35]) | (cp2_048 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[68] = (~((cp3_032 & ex3_sh_lvl2[36]) | (cp2_048 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[69] = (~((cp3_032 & ex3_sh_lvl2[37]) | (cp2_048 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[70] = (~((cp3_032 & ex3_sh_lvl2[38]) | (cp2_048 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[71] = (~((cp3_032 & ex3_sh_lvl2[39]) | (cp2_048 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[72] = (~((cp3_032 & ex3_sh_lvl2[40]) | (cp2_048 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[73] = (~((cp3_032 & ex3_sh_lvl2[41]) | (cp2_048 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[74] = (~((cp3_032 & ex3_sh_lvl2[42]) | (cp2_048 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[75] = (~((cp3_032 & ex3_sh_lvl2[43]) | (cp2_048 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[76] = (~((cp3_032 & ex3_sh_lvl2[44]) | (cp2_048 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[77] = (~((cp3_032 & ex3_sh_lvl2[45]) | (cp2_048 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[78] = (~((cp3_032 & ex3_sh_lvl2[46]) | (cp2_048 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[79] = (~((cp3_032 & ex3_sh_lvl2[47]) | (cp2_048 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[80] = (~((cp3_048 & ex3_sh_lvl2[32]) | (cp2_064 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[81] = (~((cp3_048 & ex3_sh_lvl2[33]) | (cp2_064 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[82] = (~((cp3_048 & ex3_sh_lvl2[34]) | (cp2_064 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[83] = (~((cp3_048 & ex3_sh_lvl2[35]) | (cp2_064 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[84] = (~((cp3_048 & ex3_sh_lvl2[36]) | (cp2_064 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[85] = (~((cp3_048 & ex3_sh_lvl2[37]) | (cp2_064 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[86] = (~((cp3_048 & ex3_sh_lvl2[38]) | (cp2_064 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[87] = (~((cp3_048 & ex3_sh_lvl2[39]) | (cp2_064 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[88] = (~((cp3_048 & ex3_sh_lvl2[40]) | (cp2_064 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[89] = (~((cp3_048 & ex3_sh_lvl2[41]) | (cp2_064 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[90] = (~((cp3_048 & ex3_sh_lvl2[42]) | (cp2_064 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[91] = (~((cp3_048 & ex3_sh_lvl2[43]) | (cp2_064 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[92] = (~((cp3_048 & ex3_sh_lvl2[44]) | (cp2_064 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[93] = (~((cp3_048 & ex3_sh_lvl2[45]) | (cp2_064 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[94] = (~((cp3_048 & ex3_sh_lvl2[46]) | (cp2_064 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[95] = (~((cp3_048 & ex3_sh_lvl2[47]) | (cp2_064 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[96] = (~((cp3_064 & ex3_sh_lvl2[32]) | (cp2_080 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[97] = (~((cp3_064 & ex3_sh_lvl2[33]) | (cp2_080 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[98] = (~((cp3_064 & ex3_sh_lvl2[34]) | (cp2_080 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[99] = (~((cp3_064 & ex3_sh_lvl2[35]) | (cp2_080 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[100] = (~((cp3_064 & ex3_sh_lvl2[36]) | (cp2_080 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[101] = (~((cp3_064 & ex3_sh_lvl2[37]) | (cp2_080 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[102] = (~((cp3_064 & ex3_sh_lvl2[38]) | (cp2_080 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[103] = (~((cp3_064 & ex3_sh_lvl2[39]) | (cp2_080 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[104] = (~((cp3_064 & ex3_sh_lvl2[40]) | (cp2_080 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[105] = (~((cp3_064 & ex3_sh_lvl2[41]) | (cp2_080 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[106] = (~((cp3_064 & ex3_sh_lvl2[42]) | (cp2_080 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[107] = (~((cp3_064 & ex3_sh_lvl2[43]) | (cp2_080 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[108] = (~((cp3_064 & ex3_sh_lvl2[44]) | (cp2_080 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[109] = (~((cp3_064 & ex3_sh_lvl2[45]) | (cp2_080 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[110] = (~((cp3_064 & ex3_sh_lvl2[46]) | (cp2_080 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[111] = (~((cp3_064 & ex3_sh_lvl2[47]) | (cp2_080 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[112] = (~((cp3_080 & ex3_sh_lvl2[32]) | (cp2_096 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[113] = (~((cp3_080 & ex3_sh_lvl2[33]) | (cp2_096 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[114] = (~((cp3_080 & ex3_sh_lvl2[34]) | (cp2_096 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[115] = (~((cp3_080 & ex3_sh_lvl2[35]) | (cp2_096 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[116] = (~((cp3_080 & ex3_sh_lvl2[36]) | (cp2_096 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[117] = (~((cp3_080 & ex3_sh_lvl2[37]) | (cp2_096 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[118] = (~((cp3_080 & ex3_sh_lvl2[38]) | (cp2_096 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[119] = (~((cp3_080 & ex3_sh_lvl2[39]) | (cp2_096 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[120] = (~((cp3_080 & ex3_sh_lvl2[40]) | (cp2_096 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[121] = (~((cp3_080 & ex3_sh_lvl2[41]) | (cp2_096 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[122] = (~((cp3_080 & ex3_sh_lvl2[42]) | (cp2_096 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[123] = (~((cp3_080 & ex3_sh_lvl2[43]) | (cp2_096 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[124] = (~((cp3_080 & ex3_sh_lvl2[44]) | (cp2_096 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[125] = (~((cp3_080 & ex3_sh_lvl2[45]) | (cp2_096 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[126] = (~((cp3_080 & ex3_sh_lvl2[46]) | (cp2_096 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[127] = (~((cp3_080 & ex3_sh_lvl2[47]) | (cp2_096 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[128] = (~((cp3_096 & ex3_sh_lvl2[32]) | (cp2_112 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[129] = (~((cp3_096 & ex3_sh_lvl2[33]) | (cp2_112 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[130] = (~((cp3_096 & ex3_sh_lvl2[34]) | (cp2_112 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[131] = (~((cp3_096 & ex3_sh_lvl2[35]) | (cp2_112 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[132] = (~((cp3_096 & ex3_sh_lvl2[36]) | (cp2_112 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[133] = (~((cp3_096 & ex3_sh_lvl2[37]) | (cp2_112 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[134] = (~((cp3_096 & ex3_sh_lvl2[38]) | (cp2_112 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[135] = (~((cp3_096 & ex3_sh_lvl2[39]) | (cp2_112 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[136] = (~((cp3_096 & ex3_sh_lvl2[40]) | (cp2_112 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[137] = (~((cp3_096 & ex3_sh_lvl2[41]) | (cp2_112 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[138] = (~((cp3_096 & ex3_sh_lvl2[42]) | (cp2_112 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[139] = (~((cp3_096 & ex3_sh_lvl2[43]) | (cp2_112 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[140] = (~((cp3_096 & ex3_sh_lvl2[44]) | (cp2_112 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[141] = (~((cp3_096 & ex3_sh_lvl2[45]) | (cp2_112 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[142] = (~((cp3_096 & ex3_sh_lvl2[46]) | (cp2_112 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[143] = (~((cp3_096 & ex3_sh_lvl2[47]) | (cp2_112 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[144] = (~((cp3_112 & ex3_sh_lvl2[32]) | (cp2_128 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[145] = (~((cp3_112 & ex3_sh_lvl2[33]) | (cp2_128 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[146] = (~((cp3_112 & ex3_sh_lvl2[34]) | (cp2_128 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_b[147] = (~((cp3_112 & ex3_sh_lvl2[35]) | (cp2_128 & ex3_sh_lvl2[19])));
assign ex3_sh16_r2_b[148] = (~((cp3_112 & ex3_sh_lvl2[36]) | (cp2_128 & ex3_sh_lvl2[20])));
assign ex3_sh16_r2_b[149] = (~((cp3_112 & ex3_sh_lvl2[37]) | (cp2_128 & ex3_sh_lvl2[21])));
assign ex3_sh16_r2_b[150] = (~((cp3_112 & ex3_sh_lvl2[38]) | (cp2_128 & ex3_sh_lvl2[22])));
assign ex3_sh16_r2_b[151] = (~((cp3_112 & ex3_sh_lvl2[39]) | (cp2_128 & ex3_sh_lvl2[23])));
assign ex3_sh16_r2_b[152] = (~((cp3_112 & ex3_sh_lvl2[40]) | (cp2_128 & ex3_sh_lvl2[24])));
assign ex3_sh16_r2_b[153] = (~((cp3_112 & ex3_sh_lvl2[41]) | (cp2_128 & ex3_sh_lvl2[25])));
assign ex3_sh16_r2_b[154] = (~((cp3_112 & ex3_sh_lvl2[42]) | (cp2_128 & ex3_sh_lvl2[26])));
assign ex3_sh16_r2_b[155] = (~((cp3_112 & ex3_sh_lvl2[43]) | (cp2_128 & ex3_sh_lvl2[27])));
assign ex3_sh16_r2_b[156] = (~((cp3_112 & ex3_sh_lvl2[44]) | (cp2_128 & ex3_sh_lvl2[28])));
assign ex3_sh16_r2_b[157] = (~((cp3_112 & ex3_sh_lvl2[45]) | (cp2_128 & ex3_sh_lvl2[29])));
assign ex3_sh16_r2_b[158] = (~((cp3_112 & ex3_sh_lvl2[46]) | (cp2_128 & ex3_sh_lvl2[30])));
assign ex3_sh16_r2_b[159] = (~((cp3_112 & ex3_sh_lvl2[47]) | (cp2_128 & ex3_sh_lvl2[31])));
assign ex3_sh16_r2_b[160] = (~((cp3_128 & ex3_sh_lvl2[32]) | (cp2_144 & ex3_sh_lvl2[16])));
assign ex3_sh16_r2_b[161] = (~((cp3_128 & ex3_sh_lvl2[33]) | (cp2_144 & ex3_sh_lvl2[17])));
assign ex3_sh16_r2_b[162] = (~((cp3_128 & ex3_sh_lvl2[34]) | (cp2_144 & ex3_sh_lvl2[18])));
assign ex3_sh16_r3_b[0] = (~(cp1_000 & ex3_sh_lvl2[0]));
assign ex3_sh16_r3_b[1] = (~(cp1_000 & ex3_sh_lvl2[1]));
assign ex3_sh16_r3_b[2] = (~(cp1_000 & ex3_sh_lvl2[2]));
assign ex3_sh16_r3_b[3] = (~(cp1_000 & ex3_sh_lvl2[3]));
assign ex3_sh16_r3_b[4] = (~(cp1_000 & ex3_sh_lvl2[4]));
assign ex3_sh16_r3_b[5] = (~(cp1_000 & ex3_sh_lvl2[5]));
assign ex3_sh16_r3_b[6] = (~(cp1_000 & ex3_sh_lvl2[6]));
assign ex3_sh16_r3_b[7] = (~(cp1_000 & ex3_sh_lvl2[7]));
assign ex3_sh16_r3_b[8] = (~(cp1_000 & ex3_sh_lvl2[8]));
assign ex3_sh16_r3_b[9] = (~(cp1_000 & ex3_sh_lvl2[9]));
assign ex3_sh16_r3_b[10] = (~(cp1_000 & ex3_sh_lvl2[10]));
assign ex3_sh16_r3_b[11] = (~(cp1_000 & ex3_sh_lvl2[11]));
assign ex3_sh16_r3_b[12] = (~(cp1_000 & ex3_sh_lvl2[12]));
assign ex3_sh16_r3_b[13] = (~(cp1_000 & ex3_sh_lvl2[13]));
assign ex3_sh16_r3_b[14] = (~(cp1_000 & ex3_sh_lvl2[14]));
assign ex3_sh16_r3_b[15] = (~(cp1_000 & ex3_sh_lvl2[15]));
assign ex3_sh16_r3_b[16] = (~(cp1_016 & ex3_sh_lvl2[0]));
assign ex3_sh16_r3_b[17] = (~(cp1_016 & ex3_sh_lvl2[1]));
assign ex3_sh16_r3_b[18] = (~(cp1_016 & ex3_sh_lvl2[2]));
assign ex3_sh16_r3_b[19] = (~(cp1_016 & ex3_sh_lvl2[3]));
assign ex3_sh16_r3_b[20] = (~(cp1_016 & ex3_sh_lvl2[4]));
assign ex3_sh16_r3_b[21] = (~(cp1_016 & ex3_sh_lvl2[5]));
assign ex3_sh16_r3_b[22] = (~(cp1_016 & ex3_sh_lvl2[6]));
assign ex3_sh16_r3_b[23] = (~(cp1_016 & ex3_sh_lvl2[7]));
assign ex3_sh16_r3_b[24] = (~(cp1_016 & ex3_sh_lvl2[8]));
assign ex3_sh16_r3_b[25] = (~(cp1_016 & ex3_sh_lvl2[9]));
assign ex3_sh16_r3_b[26] = (~(cp1_016 & ex3_sh_lvl2[10]));
assign ex3_sh16_r3_b[27] = (~(cp1_016 & ex3_sh_lvl2[11]));
assign ex3_sh16_r3_b[28] = (~(cp1_016 & ex3_sh_lvl2[12]));
assign ex3_sh16_r3_b[29] = (~(cp1_016 & ex3_sh_lvl2[13]));
assign ex3_sh16_r3_b[30] = (~(cp1_016 & ex3_sh_lvl2[14]));
assign ex3_sh16_r3_b[31] = (~(cp1_016 & ex3_sh_lvl2[15]));
assign ex3_sh16_r3_b[32] = (~(cp1_032 & ex3_sh_lvl2[0]));
assign ex3_sh16_r3_b[33] = (~(cp1_032 & ex3_sh_lvl2[1]));
assign ex3_sh16_r3_b[34] = (~(cp1_032 & ex3_sh_lvl2[2]));
assign ex3_sh16_r3_b[35] = (~(cp1_032 & ex3_sh_lvl2[3]));
assign ex3_sh16_r3_b[36] = (~(cp1_032 & ex3_sh_lvl2[4]));
assign ex3_sh16_r3_b[37] = (~(cp1_032 & ex3_sh_lvl2[5]));
assign ex3_sh16_r3_b[38] = (~(cp1_032 & ex3_sh_lvl2[6]));
assign ex3_sh16_r3_b[39] = (~(cp1_032 & ex3_sh_lvl2[7]));
assign ex3_sh16_r3_b[40] = (~(cp1_032 & ex3_sh_lvl2[8]));
assign ex3_sh16_r3_b[41] = (~(cp1_032 & ex3_sh_lvl2[9]));
assign ex3_sh16_r3_b[42] = (~(cp1_032 & ex3_sh_lvl2[10]));
assign ex3_sh16_r3_b[43] = (~(cp1_032 & ex3_sh_lvl2[11]));
assign ex3_sh16_r3_b[44] = (~(cp1_032 & ex3_sh_lvl2[12]));
assign ex3_sh16_r3_b[45] = (~(cp1_032 & ex3_sh_lvl2[13]));
assign ex3_sh16_r3_b[46] = (~(cp1_032 & ex3_sh_lvl2[14]));
assign ex3_sh16_r3_b[47] = (~(cp1_032 & ex3_sh_lvl2[15]));
assign ex3_sh16_r3_b[48] = (~(cp1_048 & ex3_sh_lvl2[0]));
assign ex3_sh16_r3_b[49] = (~(cp1_048 & ex3_sh_lvl2[1]));
assign ex3_sh16_r3_b[50] = (~(cp1_048 & ex3_sh_lvl2[2]));
assign ex3_sh16_r3_b[51] = (~(cp1_048 & ex3_sh_lvl2[3]));
assign ex3_sh16_r3_b[52] = (~(cp1_048 & ex3_sh_lvl2[4]));
assign ex3_sh16_r3_b[53] = (~(cp1_048 & ex3_sh_lvl2[5]));
assign ex3_sh16_r3_b[54] = (~(cp1_048 & ex3_sh_lvl2[6]));
assign ex3_sh16_r3_b[55] = (~(cp1_048 & ex3_sh_lvl2[7]));
assign ex3_sh16_r3_b[56] = (~(cp1_048 & ex3_sh_lvl2[8]));
assign ex3_sh16_r3_b[57] = (~(cp1_048 & ex3_sh_lvl2[9]));
assign ex3_sh16_r3_b[58] = (~(cp1_048 & ex3_sh_lvl2[10]));
assign ex3_sh16_r3_b[59] = (~(cp1_048 & ex3_sh_lvl2[11]));
assign ex3_sh16_r3_b[60] = (~(cp1_048 & ex3_sh_lvl2[12]));
assign ex3_sh16_r3_b[61] = (~(cp1_048 & ex3_sh_lvl2[13]));
assign ex3_sh16_r3_b[62] = (~(cp1_048 & ex3_sh_lvl2[14]));
assign ex3_sh16_r3_b[63] = (~(cp1_048 & ex3_sh_lvl2[15]));
assign ex3_sh16_r3_b[64] = (~(cp1_064 & ex3_sh_lvl2[0]));
assign ex3_sh16_r3_b[65] = (~(cp1_064 & ex3_sh_lvl2[1]));
assign ex3_sh16_r3_b[66] = (~(cp1_064 & ex3_sh_lvl2[2]));
assign ex3_sh16_r3_b[67] = (~(cp1_064 & ex3_sh_lvl2[3]));
assign ex3_sh16_r3_b[68] = (~(cp1_064 & ex3_sh_lvl2[4]));
assign ex3_sh16_r3_b[69] = (~(cp1_064 & ex3_sh_lvl2[5]));
assign ex3_sh16_r3_b[70] = (~(cp1_064 & ex3_sh_lvl2[6]));
assign ex3_sh16_r3_b[71] = (~(cp1_064 & ex3_sh_lvl2[7]));
assign ex3_sh16_r3_b[72] = (~(cp1_064 & ex3_sh_lvl2[8]));
assign ex3_sh16_r3_b[73] = (~(cp1_064 & ex3_sh_lvl2[9]));
assign ex3_sh16_r3_b[74] = (~(cp1_064 & ex3_sh_lvl2[10]));
assign ex3_sh16_r3_b[75] = (~(cp1_064 & ex3_sh_lvl2[11]));
assign ex3_sh16_r3_b[76] = (~(cp1_064 & ex3_sh_lvl2[12]));
assign ex3_sh16_r3_b[77] = (~(cp1_064 & ex3_sh_lvl2[13]));
assign ex3_sh16_r3_b[78] = (~(cp1_064 & ex3_sh_lvl2[14]));
assign ex3_sh16_r3_b[79] = (~(cp1_064 & ex3_sh_lvl2[15]));
assign ex3_sh16_r3_b[80] = (~(cp1_080 & ex3_sh_lvl2[0]));
assign ex3_sh16_r3_b[81] = (~(cp1_080 & ex3_sh_lvl2[1]));
assign ex3_sh16_r3_b[82] = (~(cp1_080 & ex3_sh_lvl2[2]));
assign ex3_sh16_r3_b[83] = (~(cp1_080 & ex3_sh_lvl2[3]));
assign ex3_sh16_r3_b[84] = (~(cp1_080 & ex3_sh_lvl2[4]));
assign ex3_sh16_r3_b[85] = (~(cp1_080 & ex3_sh_lvl2[5]));
assign ex3_sh16_r3_b[86] = (~(cp1_080 & ex3_sh_lvl2[6]));
assign ex3_sh16_r3_b[87] = (~(cp1_080 & ex3_sh_lvl2[7]));
assign ex3_sh16_r3_b[88] = (~(cp1_080 & ex3_sh_lvl2[8]));
assign ex3_sh16_r3_b[89] = (~(cp1_080 & ex3_sh_lvl2[9]));
assign ex3_sh16_r3_b[90] = (~(cp1_080 & ex3_sh_lvl2[10]));
assign ex3_sh16_r3_b[91] = (~(cp1_080 & ex3_sh_lvl2[11]));
assign ex3_sh16_r3_b[92] = (~(cp1_080 & ex3_sh_lvl2[12]));
assign ex3_sh16_r3_b[93] = (~(cp1_080 & ex3_sh_lvl2[13]));
assign ex3_sh16_r3_b[94] = (~(cp1_080 & ex3_sh_lvl2[14]));
assign ex3_sh16_r3_b[95] = (~(cp1_080 & ex3_sh_lvl2[15]));
assign ex3_sh16_r3_b[96] = (~(cp1_096 & ex3_sh_lvl2[0]));
assign ex3_sh16_r3_b[97] = (~(cp1_096 & ex3_sh_lvl2[1]));
assign ex3_sh16_r3_b[98] = (~(cp1_096 & ex3_sh_lvl2[2]));
assign ex3_sh16_r3_b[99] = (~((cp1_096 & ex3_sh_lvl2[3]) | (cp1_spc & ex3_special[99])));
assign ex3_sh16_r3_b[100] = (~((cp1_096 & ex3_sh_lvl2[4]) | (cp1_spc & ex3_special[100])));
assign ex3_sh16_r3_b[101] = (~((cp1_096 & ex3_sh_lvl2[5]) | (cp1_spc & ex3_special[101])));
assign ex3_sh16_r3_b[102] = (~((cp1_096 & ex3_sh_lvl2[6]) | (cp1_spc & ex3_special[102])));
assign ex3_sh16_r3_b[103] = (~((cp1_096 & ex3_sh_lvl2[7]) | (cp1_spc & ex3_special[103])));
assign ex3_sh16_r3_b[104] = (~((cp1_096 & ex3_sh_lvl2[8]) | (cp1_spc & ex3_special[104])));
assign ex3_sh16_r3_b[105] = (~((cp1_096 & ex3_sh_lvl2[9]) | (cp1_spc & ex3_special[105])));
assign ex3_sh16_r3_b[106] = (~((cp1_096 & ex3_sh_lvl2[10]) | (cp1_spc & ex3_special[106])));
assign ex3_sh16_r3_b[107] = (~((cp1_096 & ex3_sh_lvl2[11]) | (cp1_spc & ex3_special[107])));
assign ex3_sh16_r3_b[108] = (~((cp1_096 & ex3_sh_lvl2[12]) | (cp1_spc & ex3_special[108])));
assign ex3_sh16_r3_b[109] = (~((cp1_096 & ex3_sh_lvl2[13]) | (cp1_spc & ex3_special[109])));
assign ex3_sh16_r3_b[110] = (~((cp1_096 & ex3_sh_lvl2[14]) | (cp1_spc & ex3_special[110])));
assign ex3_sh16_r3_b[111] = (~((cp1_096 & ex3_sh_lvl2[15]) | (cp1_spc & ex3_special[111])));
assign ex3_sh16_r3_b[112] = (~((cp1_112 & ex3_sh_lvl2[0]) | (cp2_spc & ex3_special[112])));
assign ex3_sh16_r3_b[113] = (~((cp1_112 & ex3_sh_lvl2[1]) | (cp2_spc & ex3_special[113])));
assign ex3_sh16_r3_b[114] = (~((cp1_112 & ex3_sh_lvl2[2]) | (cp2_spc & ex3_special[114])));
assign ex3_sh16_r3_b[115] = (~((cp1_112 & ex3_sh_lvl2[3]) | (cp2_spc & ex3_special[115])));
assign ex3_sh16_r3_b[116] = (~((cp1_112 & ex3_sh_lvl2[4]) | (cp2_spc & ex3_special[116])));
assign ex3_sh16_r3_b[117] = (~((cp1_112 & ex3_sh_lvl2[5]) | (cp2_spc & ex3_special[117])));
assign ex3_sh16_r3_b[118] = (~((cp1_112 & ex3_sh_lvl2[6]) | (cp2_spc & ex3_special[118])));
assign ex3_sh16_r3_b[119] = (~((cp1_112 & ex3_sh_lvl2[7]) | (cp2_spc & ex3_special[119])));
assign ex3_sh16_r3_b[120] = (~((cp1_112 & ex3_sh_lvl2[8]) | (cp2_spc & ex3_special[120])));
assign ex3_sh16_r3_b[121] = (~((cp1_112 & ex3_sh_lvl2[9]) | (cp2_spc & ex3_special[121])));
assign ex3_sh16_r3_b[122] = (~((cp1_112 & ex3_sh_lvl2[10]) | (cp2_spc & ex3_special[122])));
assign ex3_sh16_r3_b[123] = (~((cp1_112 & ex3_sh_lvl2[11]) | (cp2_spc & ex3_special[123])));
assign ex3_sh16_r3_b[124] = (~((cp1_112 & ex3_sh_lvl2[12]) | (cp2_spc & ex3_special[124])));
assign ex3_sh16_r3_b[125] = (~((cp1_112 & ex3_sh_lvl2[13]) | (cp2_spc & ex3_special[125])));
assign ex3_sh16_r3_b[126] = (~((cp1_112 & ex3_sh_lvl2[14]) | (cp2_spc & ex3_special[126])));
assign ex3_sh16_r3_b[127] = (~((cp1_112 & ex3_sh_lvl2[15]) | (cp2_spc & ex3_special[127])));
assign ex3_sh16_r3_b[128] = (~((cp1_128 & ex3_sh_lvl2[0]) | (cp3_spc & ex3_special[128])));
assign ex3_sh16_r3_b[129] = (~((cp1_128 & ex3_sh_lvl2[1]) | (cp3_spc & ex3_special[129])));
assign ex3_sh16_r3_b[130] = (~((cp1_128 & ex3_sh_lvl2[2]) | (cp3_spc & ex3_special[130])));
assign ex3_sh16_r3_b[131] = (~((cp1_128 & ex3_sh_lvl2[3]) | (cp3_spc & ex3_special[131])));
assign ex3_sh16_r3_b[132] = (~((cp1_128 & ex3_sh_lvl2[4]) | (cp3_spc & ex3_special[132])));
assign ex3_sh16_r3_b[133] = (~((cp1_128 & ex3_sh_lvl2[5]) | (cp3_spc & ex3_special[133])));
assign ex3_sh16_r3_b[134] = (~((cp1_128 & ex3_sh_lvl2[6]) | (cp3_spc & ex3_special[134])));
assign ex3_sh16_r3_b[135] = (~((cp1_128 & ex3_sh_lvl2[7]) | (cp3_spc & ex3_special[135])));
assign ex3_sh16_r3_b[136] = (~((cp1_128 & ex3_sh_lvl2[8]) | (cp3_spc & ex3_special[136])));
assign ex3_sh16_r3_b[137] = (~((cp1_128 & ex3_sh_lvl2[9]) | (cp3_spc & ex3_special[137])));
assign ex3_sh16_r3_b[138] = (~((cp1_128 & ex3_sh_lvl2[10]) | (cp3_spc & ex3_special[138])));
assign ex3_sh16_r3_b[139] = (~((cp1_128 & ex3_sh_lvl2[11]) | (cp3_spc & ex3_special[139])));
assign ex3_sh16_r3_b[140] = (~((cp1_128 & ex3_sh_lvl2[12]) | (cp3_spc & ex3_special[140])));
assign ex3_sh16_r3_b[141] = (~((cp1_128 & ex3_sh_lvl2[13]) | (cp3_spc & ex3_special[141])));
assign ex3_sh16_r3_b[142] = (~((cp1_128 & ex3_sh_lvl2[14]) | (cp3_spc & ex3_special[142])));
assign ex3_sh16_r3_b[143] = (~((cp1_128 & ex3_sh_lvl2[15]) | (cp3_spc & ex3_special[143])));
assign ex3_sh16_r3_b[144] = (~((cp1_144 & ex3_sh_lvl2[0]) | (cp4_spc & ex3_special[144])));
assign ex3_sh16_r3_b[145] = (~((cp1_144 & ex3_sh_lvl2[1]) | (cp4_spc & ex3_special[145])));
assign ex3_sh16_r3_b[146] = (~((cp1_144 & ex3_sh_lvl2[2]) | (cp4_spc & ex3_special[146])));
assign ex3_sh16_r3_b[147] = (~((cp1_144 & ex3_sh_lvl2[3]) | (cp4_spc & ex3_special[147])));
assign ex3_sh16_r3_b[148] = (~((cp1_144 & ex3_sh_lvl2[4]) | (cp4_spc & ex3_special[148])));
assign ex3_sh16_r3_b[149] = (~((cp1_144 & ex3_sh_lvl2[5]) | (cp4_spc & ex3_special[149])));
assign ex3_sh16_r3_b[150] = (~((cp1_144 & ex3_sh_lvl2[6]) | (cp4_spc & ex3_special[150])));
assign ex3_sh16_r3_b[151] = (~((cp1_144 & ex3_sh_lvl2[7]) | (cp4_spc & ex3_special[151])));
assign ex3_sh16_r3_b[152] = (~((cp1_144 & ex3_sh_lvl2[8]) | (cp4_spc & ex3_special[152])));
assign ex3_sh16_r3_b[153] = (~((cp1_144 & ex3_sh_lvl2[9]) | (cp4_spc & ex3_special[153])));
assign ex3_sh16_r3_b[154] = (~((cp1_144 & ex3_sh_lvl2[10]) | (cp4_spc & ex3_special[154])));
assign ex3_sh16_r3_b[155] = (~((cp1_144 & ex3_sh_lvl2[11]) | (cp4_spc & ex3_special[155])));
assign ex3_sh16_r3_b[156] = (~((cp1_144 & ex3_sh_lvl2[12]) | (cp4_spc & ex3_special[156])));
assign ex3_sh16_r3_b[157] = (~((cp1_144 & ex3_sh_lvl2[13]) | (cp4_spc & ex3_special[157])));
assign ex3_sh16_r3_b[158] = (~((cp1_144 & ex3_sh_lvl2[14]) | (cp4_spc & ex3_special[158])));
assign ex3_sh16_r3_b[159] = (~((cp1_144 & ex3_sh_lvl2[15]) | (cp4_spc & ex3_special[159])));
assign ex3_sh16_r3_b[160] = (~((cp1_160 & ex3_sh_lvl2[0]) | (cp5_spc & ex3_special[160])));
assign ex3_sh16_r3_b[161] = (~((cp1_160 & ex3_sh_lvl2[1]) | (cp5_spc & ex3_special[161])));
assign ex3_sh16_r3_b[162] = (~((cp1_160 & ex3_sh_lvl2[2]) | (cp5_spc & ex3_special[162])));
assign ex3_sh_lvl3[0] = (~(ex3_sh16_r1_b[0] & ex3_sh16_r2_b[0] & ex3_sh16_r3_b[0]));
assign ex3_sh_lvl3[1] = (~(ex3_sh16_r1_b[1] & ex3_sh16_r2_b[1] & ex3_sh16_r3_b[1]));
assign ex3_sh_lvl3[2] = (~(ex3_sh16_r1_b[2] & ex3_sh16_r2_b[2] & ex3_sh16_r3_b[2]));
assign ex3_sh_lvl3[3] = (~(ex3_sh16_r1_b[3] & ex3_sh16_r2_b[3] & ex3_sh16_r3_b[3]));
assign ex3_sh_lvl3[4] = (~(ex3_sh16_r1_b[4] & ex3_sh16_r2_b[4] & ex3_sh16_r3_b[4]));
assign ex3_sh_lvl3[5] = (~(ex3_sh16_r1_b[5] & ex3_sh16_r2_b[5] & ex3_sh16_r3_b[5]));
assign ex3_sh_lvl3[6] = (~(ex3_sh16_r1_b[6] & ex3_sh16_r2_b[6] & ex3_sh16_r3_b[6]));
assign ex3_sh_lvl3[7] = (~(ex3_sh16_r1_b[7] & ex3_sh16_r2_b[7] & ex3_sh16_r3_b[7]));
assign ex3_sh_lvl3[8] = (~(ex3_sh16_r1_b[8] & ex3_sh16_r2_b[8] & ex3_sh16_r3_b[8]));
assign ex3_sh_lvl3[9] = (~(ex3_sh16_r1_b[9] & ex3_sh16_r2_b[9] & ex3_sh16_r3_b[9]));
assign ex3_sh_lvl3[10] = (~(ex3_sh16_r1_b[10] & ex3_sh16_r2_b[10] & ex3_sh16_r3_b[10]));
assign ex3_sh_lvl3[11] = (~(ex3_sh16_r1_b[11] & ex3_sh16_r2_b[11] & ex3_sh16_r3_b[11]));
assign ex3_sh_lvl3[12] = (~(ex3_sh16_r1_b[12] & ex3_sh16_r2_b[12] & ex3_sh16_r3_b[12]));
assign ex3_sh_lvl3[13] = (~(ex3_sh16_r1_b[13] & ex3_sh16_r2_b[13] & ex3_sh16_r3_b[13]));
assign ex3_sh_lvl3[14] = (~(ex3_sh16_r1_b[14] & ex3_sh16_r2_b[14] & ex3_sh16_r3_b[14]));
assign ex3_sh_lvl3[15] = (~(ex3_sh16_r1_b[15] & ex3_sh16_r2_b[15] & ex3_sh16_r3_b[15]));
assign ex3_sh_lvl3[16] = (~(ex3_sh16_r1_b[16] & ex3_sh16_r2_b[16] & ex3_sh16_r3_b[16]));
assign ex3_sh_lvl3[17] = (~(ex3_sh16_r1_b[17] & ex3_sh16_r2_b[17] & ex3_sh16_r3_b[17]));
assign ex3_sh_lvl3[18] = (~(ex3_sh16_r1_b[18] & ex3_sh16_r2_b[18] & ex3_sh16_r3_b[18]));
assign ex3_sh_lvl3[19] = (~(ex3_sh16_r1_b[19] & ex3_sh16_r2_b[19] & ex3_sh16_r3_b[19]));
assign ex3_sh_lvl3[20] = (~(ex3_sh16_r1_b[20] & ex3_sh16_r2_b[20] & ex3_sh16_r3_b[20]));
assign ex3_sh_lvl3[21] = (~(ex3_sh16_r1_b[21] & ex3_sh16_r2_b[21] & ex3_sh16_r3_b[21]));
assign ex3_sh_lvl3[22] = (~(ex3_sh16_r1_b[22] & ex3_sh16_r2_b[22] & ex3_sh16_r3_b[22]));
assign ex3_sh_lvl3[23] = (~(ex3_sh16_r1_b[23] & ex3_sh16_r2_b[23] & ex3_sh16_r3_b[23]));
assign ex3_sh_lvl3[24] = (~(ex3_sh16_r1_b[24] & ex3_sh16_r2_b[24] & ex3_sh16_r3_b[24]));
assign ex3_sh_lvl3[25] = (~(ex3_sh16_r1_b[25] & ex3_sh16_r2_b[25] & ex3_sh16_r3_b[25]));
assign ex3_sh_lvl3[26] = (~(ex3_sh16_r1_b[26] & ex3_sh16_r2_b[26] & ex3_sh16_r3_b[26]));
assign ex3_sh_lvl3[27] = (~(ex3_sh16_r1_b[27] & ex3_sh16_r2_b[27] & ex3_sh16_r3_b[27]));
assign ex3_sh_lvl3[28] = (~(ex3_sh16_r1_b[28] & ex3_sh16_r2_b[28] & ex3_sh16_r3_b[28]));
assign ex3_sh_lvl3[29] = (~(ex3_sh16_r1_b[29] & ex3_sh16_r2_b[29] & ex3_sh16_r3_b[29]));
assign ex3_sh_lvl3[30] = (~(ex3_sh16_r1_b[30] & ex3_sh16_r2_b[30] & ex3_sh16_r3_b[30]));
assign ex3_sh_lvl3[31] = (~(ex3_sh16_r1_b[31] & ex3_sh16_r2_b[31] & ex3_sh16_r3_b[31]));
assign ex3_sh_lvl3[32] = (~(ex3_sh16_r1_b[32] & ex3_sh16_r2_b[32] & ex3_sh16_r3_b[32]));
assign ex3_sh_lvl3[33] = (~(ex3_sh16_r1_b[33] & ex3_sh16_r2_b[33] & ex3_sh16_r3_b[33]));
assign ex3_sh_lvl3[34] = (~(ex3_sh16_r1_b[34] & ex3_sh16_r2_b[34] & ex3_sh16_r3_b[34]));
assign ex3_sh_lvl3[35] = (~(ex3_sh16_r1_b[35] & ex3_sh16_r2_b[35] & ex3_sh16_r3_b[35]));
assign ex3_sh_lvl3[36] = (~(ex3_sh16_r1_b[36] & ex3_sh16_r2_b[36] & ex3_sh16_r3_b[36]));
assign ex3_sh_lvl3[37] = (~(ex3_sh16_r1_b[37] & ex3_sh16_r2_b[37] & ex3_sh16_r3_b[37]));
assign ex3_sh_lvl3[38] = (~(ex3_sh16_r1_b[38] & ex3_sh16_r2_b[38] & ex3_sh16_r3_b[38]));
assign ex3_sh_lvl3[39] = (~(ex3_sh16_r1_b[39] & ex3_sh16_r2_b[39] & ex3_sh16_r3_b[39]));
assign ex3_sh_lvl3[40] = (~(ex3_sh16_r1_b[40] & ex3_sh16_r2_b[40] & ex3_sh16_r3_b[40]));
assign ex3_sh_lvl3[41] = (~(ex3_sh16_r1_b[41] & ex3_sh16_r2_b[41] & ex3_sh16_r3_b[41]));
assign ex3_sh_lvl3[42] = (~(ex3_sh16_r1_b[42] & ex3_sh16_r2_b[42] & ex3_sh16_r3_b[42]));
assign ex3_sh_lvl3[43] = (~(ex3_sh16_r1_b[43] & ex3_sh16_r2_b[43] & ex3_sh16_r3_b[43]));
assign ex3_sh_lvl3[44] = (~(ex3_sh16_r1_b[44] & ex3_sh16_r2_b[44] & ex3_sh16_r3_b[44]));
assign ex3_sh_lvl3[45] = (~(ex3_sh16_r1_b[45] & ex3_sh16_r2_b[45] & ex3_sh16_r3_b[45]));
assign ex3_sh_lvl3[46] = (~(ex3_sh16_r1_b[46] & ex3_sh16_r2_b[46] & ex3_sh16_r3_b[46]));
assign ex3_sh_lvl3[47] = (~(ex3_sh16_r1_b[47] & ex3_sh16_r2_b[47] & ex3_sh16_r3_b[47]));
assign ex3_sh_lvl3[48] = (~(ex3_sh16_r1_b[48] & ex3_sh16_r2_b[48] & ex3_sh16_r3_b[48]));
assign ex3_sh_lvl3[49] = (~(ex3_sh16_r1_b[49] & ex3_sh16_r2_b[49] & ex3_sh16_r3_b[49]));
assign ex3_sh_lvl3[50] = (~(ex3_sh16_r1_b[50] & ex3_sh16_r2_b[50] & ex3_sh16_r3_b[50]));
assign ex3_sh_lvl3[51] = (~(ex3_sh16_r1_b[51] & ex3_sh16_r2_b[51] & ex3_sh16_r3_b[51]));
assign ex3_sh_lvl3[52] = (~(ex3_sh16_r1_b[52] & ex3_sh16_r2_b[52] & ex3_sh16_r3_b[52]));
assign ex3_sh_lvl3[53] = (~(ex3_sh16_r1_b[53] & ex3_sh16_r2_b[53] & ex3_sh16_r3_b[53]));
assign ex3_sh_lvl3[54] = (~(ex3_sh16_r1_b[54] & ex3_sh16_r2_b[54] & ex3_sh16_r3_b[54]));
assign ex3_sh_lvl3[55] = (~(ex3_sh16_r1_b[55] & ex3_sh16_r2_b[55] & ex3_sh16_r3_b[55]));
assign ex3_sh_lvl3[56] = (~(ex3_sh16_r1_b[56] & ex3_sh16_r2_b[56] & ex3_sh16_r3_b[56]));
assign ex3_sh_lvl3[57] = (~(ex3_sh16_r1_b[57] & ex3_sh16_r2_b[57] & ex3_sh16_r3_b[57]));
assign ex3_sh_lvl3[58] = (~(ex3_sh16_r1_b[58] & ex3_sh16_r2_b[58] & ex3_sh16_r3_b[58]));
assign ex3_sh_lvl3[59] = (~(ex3_sh16_r1_b[59] & ex3_sh16_r2_b[59] & ex3_sh16_r3_b[59]));
assign ex3_sh_lvl3[60] = (~(ex3_sh16_r1_b[60] & ex3_sh16_r2_b[60] & ex3_sh16_r3_b[60]));
assign ex3_sh_lvl3[61] = (~(ex3_sh16_r1_b[61] & ex3_sh16_r2_b[61] & ex3_sh16_r3_b[61]));
assign ex3_sh_lvl3[62] = (~(ex3_sh16_r1_b[62] & ex3_sh16_r2_b[62] & ex3_sh16_r3_b[62]));
assign ex3_sh_lvl3[63] = (~(ex3_sh16_r1_b[63] & ex3_sh16_r2_b[63] & ex3_sh16_r3_b[63]));
assign ex3_sh_lvl3[64] = (~(ex3_sh16_r1_b[64] & ex3_sh16_r2_b[64] & ex3_sh16_r3_b[64]));
assign ex3_sh_lvl3[65] = (~(ex3_sh16_r1_b[65] & ex3_sh16_r2_b[65] & ex3_sh16_r3_b[65]));
assign ex3_sh_lvl3[66] = (~(ex3_sh16_r1_b[66] & ex3_sh16_r2_b[66] & ex3_sh16_r3_b[66]));
assign ex3_sh_lvl3[67] = (~(ex3_sh16_r1_b[67] & ex3_sh16_r2_b[67] & ex3_sh16_r3_b[67]));
assign ex3_sh_lvl3[68] = (~(ex3_sh16_r1_b[68] & ex3_sh16_r2_b[68] & ex3_sh16_r3_b[68]));
assign ex3_sh_lvl3[69] = (~(ex3_sh16_r1_b[69] & ex3_sh16_r2_b[69] & ex3_sh16_r3_b[69]));
assign ex3_sh_lvl3[70] = (~(ex3_sh16_r1_b[70] & ex3_sh16_r2_b[70] & ex3_sh16_r3_b[70]));
assign ex3_sh_lvl3[71] = (~(ex3_sh16_r1_b[71] & ex3_sh16_r2_b[71] & ex3_sh16_r3_b[71]));
assign ex3_sh_lvl3[72] = (~(ex3_sh16_r1_b[72] & ex3_sh16_r2_b[72] & ex3_sh16_r3_b[72]));
assign ex3_sh_lvl3[73] = (~(ex3_sh16_r1_b[73] & ex3_sh16_r2_b[73] & ex3_sh16_r3_b[73]));
assign ex3_sh_lvl3[74] = (~(ex3_sh16_r1_b[74] & ex3_sh16_r2_b[74] & ex3_sh16_r3_b[74]));
assign ex3_sh_lvl3[75] = (~(ex3_sh16_r1_b[75] & ex3_sh16_r2_b[75] & ex3_sh16_r3_b[75]));
assign ex3_sh_lvl3[76] = (~(ex3_sh16_r1_b[76] & ex3_sh16_r2_b[76] & ex3_sh16_r3_b[76]));
assign ex3_sh_lvl3[77] = (~(ex3_sh16_r1_b[77] & ex3_sh16_r2_b[77] & ex3_sh16_r3_b[77]));
assign ex3_sh_lvl3[78] = (~(ex3_sh16_r1_b[78] & ex3_sh16_r2_b[78] & ex3_sh16_r3_b[78]));
assign ex3_sh_lvl3[79] = (~(ex3_sh16_r1_b[79] & ex3_sh16_r2_b[79] & ex3_sh16_r3_b[79]));
assign ex3_sh_lvl3[80] = (~(ex3_sh16_r1_b[80] & ex3_sh16_r2_b[80] & ex3_sh16_r3_b[80]));
assign ex3_sh_lvl3[81] = (~(ex3_sh16_r1_b[81] & ex3_sh16_r2_b[81] & ex3_sh16_r3_b[81]));
assign ex3_sh_lvl3[82] = (~(ex3_sh16_r1_b[82] & ex3_sh16_r2_b[82] & ex3_sh16_r3_b[82]));
assign ex3_sh_lvl3[83] = (~(ex3_sh16_r1_b[83] & ex3_sh16_r2_b[83] & ex3_sh16_r3_b[83]));
assign ex3_sh_lvl3[84] = (~(ex3_sh16_r1_b[84] & ex3_sh16_r2_b[84] & ex3_sh16_r3_b[84]));
assign ex3_sh_lvl3[85] = (~(ex3_sh16_r1_b[85] & ex3_sh16_r2_b[85] & ex3_sh16_r3_b[85]));
assign ex3_sh_lvl3[86] = (~(ex3_sh16_r1_b[86] & ex3_sh16_r2_b[86] & ex3_sh16_r3_b[86]));
assign ex3_sh_lvl3[87] = (~(ex3_sh16_r1_b[87] & ex3_sh16_r2_b[87] & ex3_sh16_r3_b[87]));
assign ex3_sh_lvl3[88] = (~(ex3_sh16_r1_b[88] & ex3_sh16_r2_b[88] & ex3_sh16_r3_b[88]));
assign ex3_sh_lvl3[89] = (~(ex3_sh16_r1_b[89] & ex3_sh16_r2_b[89] & ex3_sh16_r3_b[89]));
assign ex3_sh_lvl3[90] = (~(ex3_sh16_r1_b[90] & ex3_sh16_r2_b[90] & ex3_sh16_r3_b[90]));
assign ex3_sh_lvl3[91] = (~(ex3_sh16_r1_b[91] & ex3_sh16_r2_b[91] & ex3_sh16_r3_b[91]));
assign ex3_sh_lvl3[92] = (~(ex3_sh16_r1_b[92] & ex3_sh16_r2_b[92] & ex3_sh16_r3_b[92]));
assign ex3_sh_lvl3[93] = (~(ex3_sh16_r1_b[93] & ex3_sh16_r2_b[93] & ex3_sh16_r3_b[93]));
assign ex3_sh_lvl3[94] = (~(ex3_sh16_r1_b[94] & ex3_sh16_r2_b[94] & ex3_sh16_r3_b[94]));
assign ex3_sh_lvl3[95] = (~(ex3_sh16_r1_b[95] & ex3_sh16_r2_b[95] & ex3_sh16_r3_b[95]));
assign ex3_sh_lvl3[96] = (~(ex3_sh16_r1_b[96] & ex3_sh16_r2_b[96] & ex3_sh16_r3_b[96]));
assign ex3_sh_lvl3[97] = (~(ex3_sh16_r1_b[97] & ex3_sh16_r2_b[97] & ex3_sh16_r3_b[97]));
assign ex3_sh_lvl3[98] = (~(ex3_sh16_r1_b[98] & ex3_sh16_r2_b[98] & ex3_sh16_r3_b[98]));
assign ex3_sh_lvl3[99] = (~(ex3_sh16_r1_b[99] & ex3_sh16_r2_b[99] & ex3_sh16_r3_b[99]));
assign ex3_sh_lvl3[100] = (~(ex3_sh16_r1_b[100] & ex3_sh16_r2_b[100] & ex3_sh16_r3_b[100]));
assign ex3_sh_lvl3[101] = (~(ex3_sh16_r1_b[101] & ex3_sh16_r2_b[101] & ex3_sh16_r3_b[101]));
assign ex3_sh_lvl3[102] = (~(ex3_sh16_r1_b[102] & ex3_sh16_r2_b[102] & ex3_sh16_r3_b[102]));
assign ex3_sh_lvl3[103] = (~(ex3_sh16_r1_b[103] & ex3_sh16_r2_b[103] & ex3_sh16_r3_b[103]));
assign ex3_sh_lvl3[104] = (~(ex3_sh16_r1_b[104] & ex3_sh16_r2_b[104] & ex3_sh16_r3_b[104]));
assign ex3_sh_lvl3[105] = (~(ex3_sh16_r1_b[105] & ex3_sh16_r2_b[105] & ex3_sh16_r3_b[105]));
assign ex3_sh_lvl3[106] = (~(ex3_sh16_r1_b[106] & ex3_sh16_r2_b[106] & ex3_sh16_r3_b[106]));
assign ex3_sh_lvl3[107] = (~(ex3_sh16_r1_b[107] & ex3_sh16_r2_b[107] & ex3_sh16_r3_b[107]));
assign ex3_sh_lvl3[108] = (~(ex3_sh16_r1_b[108] & ex3_sh16_r2_b[108] & ex3_sh16_r3_b[108]));
assign ex3_sh_lvl3[109] = (~(ex3_sh16_r1_b[109] & ex3_sh16_r2_b[109] & ex3_sh16_r3_b[109]));
assign ex3_sh_lvl3[110] = (~(ex3_sh16_r1_b[110] & ex3_sh16_r2_b[110] & ex3_sh16_r3_b[110]));
assign ex3_sh_lvl3[111] = (~(ex3_sh16_r1_b[111] & ex3_sh16_r2_b[111] & ex3_sh16_r3_b[111]));
assign ex3_sh_lvl3[112] = (~(ex3_sh16_r1_b[112] & ex3_sh16_r2_b[112] & ex3_sh16_r3_b[112]));
assign ex3_sh_lvl3[113] = (~(ex3_sh16_r1_b[113] & ex3_sh16_r2_b[113] & ex3_sh16_r3_b[113]));
assign ex3_sh_lvl3[114] = (~(ex3_sh16_r1_b[114] & ex3_sh16_r2_b[114] & ex3_sh16_r3_b[114]));
assign ex3_sh_lvl3[115] = (~(ex3_sh16_r1_b[115] & ex3_sh16_r2_b[115] & ex3_sh16_r3_b[115]));
assign ex3_sh_lvl3[116] = (~(ex3_sh16_r1_b[116] & ex3_sh16_r2_b[116] & ex3_sh16_r3_b[116]));
assign ex3_sh_lvl3[117] = (~(ex3_sh16_r1_b[117] & ex3_sh16_r2_b[117] & ex3_sh16_r3_b[117]));
assign ex3_sh_lvl3[118] = (~(ex3_sh16_r1_b[118] & ex3_sh16_r2_b[118] & ex3_sh16_r3_b[118]));
assign ex3_sh_lvl3[119] = (~(ex3_sh16_r1_b[119] & ex3_sh16_r2_b[119] & ex3_sh16_r3_b[119]));
assign ex3_sh_lvl3[120] = (~(ex3_sh16_r1_b[120] & ex3_sh16_r2_b[120] & ex3_sh16_r3_b[120]));
assign ex3_sh_lvl3[121] = (~(ex3_sh16_r1_b[121] & ex3_sh16_r2_b[121] & ex3_sh16_r3_b[121]));
assign ex3_sh_lvl3[122] = (~(ex3_sh16_r1_b[122] & ex3_sh16_r2_b[122] & ex3_sh16_r3_b[122]));
assign ex3_sh_lvl3[123] = (~(ex3_sh16_r1_b[123] & ex3_sh16_r2_b[123] & ex3_sh16_r3_b[123]));
assign ex3_sh_lvl3[124] = (~(ex3_sh16_r1_b[124] & ex3_sh16_r2_b[124] & ex3_sh16_r3_b[124]));
assign ex3_sh_lvl3[125] = (~(ex3_sh16_r1_b[125] & ex3_sh16_r2_b[125] & ex3_sh16_r3_b[125]));
assign ex3_sh_lvl3[126] = (~(ex3_sh16_r1_b[126] & ex3_sh16_r2_b[126] & ex3_sh16_r3_b[126]));
assign ex3_sh_lvl3[127] = (~(ex3_sh16_r1_b[127] & ex3_sh16_r2_b[127] & ex3_sh16_r3_b[127]));
assign ex3_sh_lvl3[128] = (~(ex3_sh16_r1_b[128] & ex3_sh16_r2_b[128] & ex3_sh16_r3_b[128]));
assign ex3_sh_lvl3[129] = (~(ex3_sh16_r1_b[129] & ex3_sh16_r2_b[129] & ex3_sh16_r3_b[129]));
assign ex3_sh_lvl3[130] = (~(ex3_sh16_r1_b[130] & ex3_sh16_r2_b[130] & ex3_sh16_r3_b[130]));
assign ex3_sh_lvl3[131] = (~(ex3_sh16_r1_b[131] & ex3_sh16_r2_b[131] & ex3_sh16_r3_b[131]));
assign ex3_sh_lvl3[132] = (~(ex3_sh16_r1_b[132] & ex3_sh16_r2_b[132] & ex3_sh16_r3_b[132]));
assign ex3_sh_lvl3[133] = (~(ex3_sh16_r1_b[133] & ex3_sh16_r2_b[133] & ex3_sh16_r3_b[133]));
assign ex3_sh_lvl3[134] = (~(ex3_sh16_r1_b[134] & ex3_sh16_r2_b[134] & ex3_sh16_r3_b[134]));
assign ex3_sh_lvl3[135] = (~(ex3_sh16_r1_b[135] & ex3_sh16_r2_b[135] & ex3_sh16_r3_b[135]));
assign ex3_sh_lvl3[136] = (~(ex3_sh16_r1_b[136] & ex3_sh16_r2_b[136] & ex3_sh16_r3_b[136]));
assign ex3_sh_lvl3[137] = (~(ex3_sh16_r1_b[137] & ex3_sh16_r2_b[137] & ex3_sh16_r3_b[137]));
assign ex3_sh_lvl3[138] = (~(ex3_sh16_r1_b[138] & ex3_sh16_r2_b[138] & ex3_sh16_r3_b[138]));
assign ex3_sh_lvl3[139] = (~(ex3_sh16_r1_b[139] & ex3_sh16_r2_b[139] & ex3_sh16_r3_b[139]));
assign ex3_sh_lvl3[140] = (~(ex3_sh16_r1_b[140] & ex3_sh16_r2_b[140] & ex3_sh16_r3_b[140]));
assign ex3_sh_lvl3[141] = (~(ex3_sh16_r1_b[141] & ex3_sh16_r2_b[141] & ex3_sh16_r3_b[141]));
assign ex3_sh_lvl3[142] = (~(ex3_sh16_r1_b[142] & ex3_sh16_r2_b[142] & ex3_sh16_r3_b[142]));
assign ex3_sh_lvl3[143] = (~(ex3_sh16_r1_b[143] & ex3_sh16_r2_b[143] & ex3_sh16_r3_b[143]));
assign ex3_sh_lvl3[144] = (~(ex3_sh16_r1_b[144] & ex3_sh16_r2_b[144] & ex3_sh16_r3_b[144]));
assign ex3_sh_lvl3[145] = (~(ex3_sh16_r1_b[145] & ex3_sh16_r2_b[145] & ex3_sh16_r3_b[145]));
assign ex3_sh_lvl3[146] = (~(ex3_sh16_r1_b[146] & ex3_sh16_r2_b[146] & ex3_sh16_r3_b[146]));
assign ex3_sh_lvl3[147] = (~(ex3_sh16_r1_b[147] & ex3_sh16_r2_b[147] & ex3_sh16_r3_b[147]));
assign ex3_sh_lvl3[148] = (~(ex3_sh16_r1_b[148] & ex3_sh16_r2_b[148] & ex3_sh16_r3_b[148]));
assign ex3_sh_lvl3[149] = (~(ex3_sh16_r1_b[149] & ex3_sh16_r2_b[149] & ex3_sh16_r3_b[149]));
assign ex3_sh_lvl3[150] = (~(ex3_sh16_r1_b[150] & ex3_sh16_r2_b[150] & ex3_sh16_r3_b[150]));
assign ex3_sh_lvl3[151] = (~(ex3_sh16_r1_b[151] & ex3_sh16_r2_b[151] & ex3_sh16_r3_b[151]));
assign ex3_sh_lvl3[152] = (~(ex3_sh16_r1_b[152] & ex3_sh16_r2_b[152] & ex3_sh16_r3_b[152]));
assign ex3_sh_lvl3[153] = (~(ex3_sh16_r1_b[153] & ex3_sh16_r2_b[153] & ex3_sh16_r3_b[153]));
assign ex3_sh_lvl3[154] = (~(ex3_sh16_r1_b[154] & ex3_sh16_r2_b[154] & ex3_sh16_r3_b[154]));
assign ex3_sh_lvl3[155] = (~(ex3_sh16_r1_b[155] & ex3_sh16_r2_b[155] & ex3_sh16_r3_b[155]));
assign ex3_sh_lvl3[156] = (~(ex3_sh16_r1_b[156] & ex3_sh16_r2_b[156] & ex3_sh16_r3_b[156]));
assign ex3_sh_lvl3[157] = (~(ex3_sh16_r1_b[157] & ex3_sh16_r2_b[157] & ex3_sh16_r3_b[157]));
assign ex3_sh_lvl3[158] = (~(ex3_sh16_r1_b[158] & ex3_sh16_r2_b[158] & ex3_sh16_r3_b[158]));
assign ex3_sh_lvl3[159] = (~(ex3_sh16_r1_b[159] & ex3_sh16_r2_b[159] & ex3_sh16_r3_b[159]));
assign ex3_sh_lvl3[160] = (~(ex3_sh16_r1_b[160] & ex3_sh16_r2_b[160] & ex3_sh16_r3_b[160]));
assign ex3_sh_lvl3[161] = (~(ex3_sh16_r1_b[161] & ex3_sh16_r2_b[161] & ex3_sh16_r3_b[161]));
assign ex3_sh_lvl3[162] = (~(ex3_sh16_r1_b[162] & ex3_sh16_r2_b[162] & ex3_sh16_r3_b[162]));
//--------------------------------------
// replicated logic for sticky bit
//--------------------------------------
assign ex3_sh16_r3_162_b = (~((ex3_lvl3_shdcd160 & ex3_sh_lvl2[2]) | (ex3_sel_special & ex3_special[162])));
assign ex3_sh16_r3_163_b = (~(ex3_lvl3_shdcd160 & ex3_sh_lvl2[3]));
assign ex3_sh16_r2_162_b = (~((ex3_lvl3_shdcd128 & ex3_sh_lvl2[34]) | (ex3_lvl3_shdcd144 & ex3_sh_lvl2[18])));
assign ex3_sh16_r2_163_b = (~((ex3_lvl3_shdcd128 & ex3_sh_lvl2[35]) | (ex3_lvl3_shdcd144 & ex3_sh_lvl2[19])));
assign ex3_sh16_r1_162_b = (~((ex3_lvl3_shdcd096 & ex3_sh_lvl2[66]) | (ex3_lvl3_shdcd112 & ex3_sh_lvl2[50])));
assign ex3_sh16_r1_163_b = (~((ex3_lvl3_shdcd096 & ex3_sh_lvl2[67]) | (ex3_lvl3_shdcd112 & ex3_sh_lvl2[51])));
assign ex3_sh16_162 = (~(ex3_sh16_r1_162_b & ex3_sh16_r2_162_b & ex3_sh16_r3_162_b));
assign ex3_sh16_163 = (~(ex3_sh16_r1_163_b & ex3_sh16_r2_163_b & ex3_sh16_r3_163_b));
endmodule |
module lq_stq_rot(
rot_sel,
mask,
se_b,
rot_data,
data_rot
);
input [0:3] rot_sel;
input [0:3] mask;
input se_b;
input [0:7] rot_data;
output [0:7] data_rot;
wire [0:5] se1;
wire [0:7] mx1_d0;
wire [0:7] mx1_d1;
wire [0:7] mx1_d2;
wire [0:7] mx1_d3;
wire [0:7] mx1_s0;
wire [0:7] mx1_s1;
wire [0:7] mx1_s2;
wire [0:7] mx1_s3;
wire [0:7] mx1_0_b;
wire [0:7] mx1_1_b;
wire [0:7] mx1;
wire [0:7] mask_exp;
//--------------------------------------------------------------------------------------
// Muxing <0,2,4,6 bytes>
//--------------------------------------------------------------------------------------
assign mx1_s0[0:7] = {8{rot_sel[0]}};
assign mx1_s1[0:7] = {8{rot_sel[1]}};
assign mx1_s2[0:7] = {8{rot_sel[2]}};
assign mx1_s3[0:7] = {8{rot_sel[3]}};
// Generate a Mask that is dependent on the size of the operation
assign mask_exp[0] = mask[0]; // 8B
assign mask_exp[1] = mask[0]; // 8B
assign mask_exp[2] = mask[0]; // 8B
assign mask_exp[3] = mask[0]; // 8B
assign mask_exp[4] = mask[0] | mask[1]; // 8B/4B
assign mask_exp[5] = mask[0] | mask[1]; // 8B/4B
assign mask_exp[6] = mask[0] | mask[1] | mask[2]; // 8B/4B/2B
assign mask_exp[7] = mask[0] | mask[1] | mask[2] | mask[3]; // 8B/4B/2B/1B
assign se1[0:3] = {4{((~se_b))}};
assign se1[4:5] = {2{(((~se_b)) & mask[2])}};
assign mx1_d0 = (rot_data[0:7]) & mask_exp;
assign mx1_d1 = ({2'b0, rot_data[0:5]}) & mask_exp;
assign mx1_d2 = ({4'b0, rot_data[0:3]}) & mask_exp;
assign mx1_d3 = ({6'b0, rot_data[0:1]}) & mask_exp;
//assign mx1_0_b[0:7] = (~((mx1_s0[0:7] & mx1_d0[0:7]) | (mx1_s1[0:7] & mx1_d1[0:7])));
tri_aoi22 #(.WIDTH(8)) mx1_0_b_0 (.y(mx1_0_b[0:7]), .a0(mx1_s0[0:7]), .a1(mx1_d0[0:7]), .b0(mx1_s1[0:7]), .b1(mx1_d1[0:7]));
//assign mx1_1_b[0:7] = (~((mx1_s2[0:7] & mx1_d2[0:7]) | (mx1_s3[0:7] & mx1_d3[0:7])));
tri_aoi22 #(.WIDTH(8)) mx1_1_b_0 (.y(mx1_1_b[0:7]), .a0(mx1_s2[0:7]), .a1(mx1_d2[0:7]), .b0(mx1_s3[0:7]), .b1(mx1_d3[0:7]));
//assign mx1[0:7] = (~(mx1_0_b[0:7] & mx1_1_b[0:7]));
tri_nand2 #(.WIDTH(8)) mx1_0 (.y(mx1[0:7]), .a(mx1_0_b[0:7]), .b(mx1_1_b[0:7]));
assign data_rot = {(mx1[0:5] | se1[0:5]), mx1[6:7]};
endmodule |
module lq_dir_tag(
dcc_dir_binv3_ex3_stg_act,
dcc_dir_stq1_stg_act,
dcc_dir_stq2_stg_act,
dcc_dir_stq3_stg_act,
rel_way_upd_a,
rel_way_upd_b,
rel_way_upd_c,
rel_way_upd_d,
rel_way_upd_e,
rel_way_upd_f,
rel_way_upd_g,
rel_way_upd_h,
dcc_dir_ex2_binv_val,
spr_xucr0_dcdis,
dcc_dir_ex4_p_addr,
dcc_dir_ex3_ddir_acc,
lsq_ctl_stq1_addr,
stq2_ddir_acc,
pc_lq_inj_dcachedir_ldp_parity,
pc_lq_inj_dcachedir_stp_parity,
dir_arr_rd_data0,
dir_arr_rd_data1,
dir_arr_wr_way,
dir_arr_wr_addr,
dir_arr_wr_data,
ex4_way_cmp_a,
ex4_way_cmp_b,
ex4_way_cmp_c,
ex4_way_cmp_d,
ex4_way_cmp_e,
ex4_way_cmp_f,
ex4_way_cmp_g,
ex4_way_cmp_h,
ex4_tag_perr_way,
dir_dcc_ex4_way_tag_a,
dir_dcc_ex4_way_tag_b,
dir_dcc_ex4_way_tag_c,
dir_dcc_ex4_way_tag_d,
dir_dcc_ex4_way_tag_e,
dir_dcc_ex4_way_tag_f,
dir_dcc_ex4_way_tag_g,
dir_dcc_ex4_way_tag_h,
dir_dcc_ex4_way_par_a,
dir_dcc_ex4_way_par_b,
dir_dcc_ex4_way_par_c,
dir_dcc_ex4_way_par_d,
dir_dcc_ex4_way_par_e,
dir_dcc_ex4_way_par_f,
dir_dcc_ex4_way_par_g,
dir_dcc_ex4_way_par_h,
stq3_way_cmp_a,
stq3_way_cmp_b,
stq3_way_cmp_c,
stq3_way_cmp_d,
stq3_way_cmp_e,
stq3_way_cmp_f,
stq3_way_cmp_g,
stq3_way_cmp_h,
stq3_tag_way_perr,
vdd,
gnd,
nclk,
sg_0,
func_sl_thold_0_b,
func_sl_force,
func_slp_sl_thold_0_b,
func_slp_sl_force,
d_mode_dc,
delay_lclkr_dc,
mpw1_dc_b,
mpw2_dc_b,
scan_in,
scan_out
);
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2;
//parameter `DC_SIZE = 15;
//parameter `CL_SIZE = 6;
//parameter `REAL_IFAR_WIDTH = 42;
parameter WAYDATASIZE = 34; // TagSize + Parity Bits
parameter PARBITS = 4;
// Stage ACT Signals
input dcc_dir_binv3_ex3_stg_act;
input dcc_dir_stq1_stg_act;
input dcc_dir_stq2_stg_act;
input dcc_dir_stq3_stg_act;
// Reload Update Directory
input rel_way_upd_a;
input rel_way_upd_b;
input rel_way_upd_c;
input rel_way_upd_d;
input rel_way_upd_e;
input rel_way_upd_f;
input rel_way_upd_g;
input rel_way_upd_h;
// Back-Invalidate
input dcc_dir_ex2_binv_val;
// SPR Bits
input spr_xucr0_dcdis;
// LQ Pipe
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dcc_dir_ex4_p_addr;
input dcc_dir_ex3_ddir_acc;
// Commit Pipe
input [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_stq1_addr;
input stq2_ddir_acc;
// Error Inject
input pc_lq_inj_dcachedir_ldp_parity;
input pc_lq_inj_dcachedir_stp_parity;
// L1 Directory Read Interface
input [0:(8*WAYDATASIZE)-1] dir_arr_rd_data0;
input [0:(8*WAYDATASIZE)-1] dir_arr_rd_data1;
// L1 Directory Write Interface
output [0:7] dir_arr_wr_way;
output [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_wr_addr;
output [64-`REAL_IFAR_WIDTH:64-`REAL_IFAR_WIDTH+WAYDATASIZE-1] dir_arr_wr_data;
// LQ Pipe
output ex4_way_cmp_a;
output ex4_way_cmp_b;
output ex4_way_cmp_c;
output ex4_way_cmp_d;
output ex4_way_cmp_e;
output ex4_way_cmp_f;
output ex4_way_cmp_g;
output ex4_way_cmp_h;
output [0:7] ex4_tag_perr_way;
// L1 Directory Contents
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_a;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_b;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_c;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_d;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_e;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_f;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_g;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_h;
output [0:PARBITS-1] dir_dcc_ex4_way_par_a;
output [0:PARBITS-1] dir_dcc_ex4_way_par_b;
output [0:PARBITS-1] dir_dcc_ex4_way_par_c;
output [0:PARBITS-1] dir_dcc_ex4_way_par_d;
output [0:PARBITS-1] dir_dcc_ex4_way_par_e;
output [0:PARBITS-1] dir_dcc_ex4_way_par_f;
output [0:PARBITS-1] dir_dcc_ex4_way_par_g;
output [0:PARBITS-1] dir_dcc_ex4_way_par_h;
// Commit Pipe
output stq3_way_cmp_a;
output stq3_way_cmp_b;
output stq3_way_cmp_c;
output stq3_way_cmp_d;
output stq3_way_cmp_e;
output stq3_way_cmp_f;
output stq3_way_cmp_g;
output stq3_way_cmp_h;
output [0:7] stq3_tag_way_perr;
inout vdd;
inout gnd;
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
input [0:`NCLK_WIDTH-1] nclk;
input sg_0;
input func_sl_thold_0_b;
input func_sl_force;
input func_slp_sl_thold_0_b;
input func_slp_sl_force;
input d_mode_dc;
input delay_lclkr_dc;
input mpw1_dc_b;
input mpw2_dc_b;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out;
//--------------------------
// components
//--------------------------
//--------------------------
// signals
//--------------------------
parameter uprTagBit = 64 - `REAL_IFAR_WIDTH;
parameter lwrTagBit = 63 - (`DC_SIZE - 3);
parameter tagSize = lwrTagBit - uprTagBit + 1;
parameter parExtCalc = 8 - (tagSize % 8);
parameter uprCClassBit = 64 - (`DC_SIZE - 3);
parameter lwrCClassBit = 63 - `CL_SIZE;
wire [uprCClassBit:lwrCClassBit] arr_wr_addr;
wire [uprTagBit:lwrTagBit] arr_wr_data;
wire p0_way_cmp_a;
wire p0_way_cmp_b;
wire p0_way_cmp_c;
wire p0_way_cmp_d;
wire p0_way_cmp_e;
wire p0_way_cmp_f;
wire p0_way_cmp_g;
wire p0_way_cmp_h;
wire p1_way_cmp_a;
wire p1_way_cmp_b;
wire p1_way_cmp_c;
wire p1_way_cmp_d;
wire p1_way_cmp_e;
wire p1_way_cmp_f;
wire p1_way_cmp_g;
wire p1_way_cmp_h;
wire ex3_binv_val_d;
wire ex3_binv_val_q;
wire [uprTagBit:lwrTagBit] p0_way_tag_a;
wire [uprTagBit:lwrTagBit] p0_way_tag_b;
wire [uprTagBit:lwrTagBit] p0_way_tag_c;
wire [uprTagBit:lwrTagBit] p0_way_tag_d;
wire [uprTagBit:lwrTagBit] p0_way_tag_e;
wire [uprTagBit:lwrTagBit] p0_way_tag_f;
wire [uprTagBit:lwrTagBit] p0_way_tag_g;
wire [uprTagBit:lwrTagBit] p0_way_tag_h;
wire [uprTagBit:lwrTagBit] p1_way_tag_a;
wire [uprTagBit:lwrTagBit] p1_way_tag_b;
wire [uprTagBit:lwrTagBit] p1_way_tag_c;
wire [uprTagBit:lwrTagBit] p1_way_tag_d;
wire [uprTagBit:lwrTagBit] p1_way_tag_e;
wire [uprTagBit:lwrTagBit] p1_way_tag_f;
wire [uprTagBit:lwrTagBit] p1_way_tag_g;
wire [uprTagBit:lwrTagBit] p1_way_tag_h;
wire inj_ddir_ldp_parity_d;
wire inj_ddir_ldp_parity_q;
wire inj_ddir_stp_parity_d;
wire inj_ddir_stp_parity_q;
wire [uprTagBit:lwrCClassBit] stq2_addr_d;
wire [uprTagBit:lwrCClassBit] stq2_addr_q;
wire [uprTagBit:lwrCClassBit] stq3_addr_d;
wire [uprTagBit:lwrCClassBit] stq3_addr_q;
wire [uprTagBit:lwrCClassBit] stq4_addr_d;
wire [uprTagBit:lwrCClassBit] stq4_addr_q;
wire p0_par_err_det_a;
wire p0_par_err_det_b;
wire p0_par_err_det_c;
wire p0_par_err_det_d;
wire p0_par_err_det_e;
wire p0_par_err_det_f;
wire p0_par_err_det_g;
wire p0_par_err_det_h;
wire p1_par_err_det_a;
wire p1_par_err_det_b;
wire p1_par_err_det_c;
wire p1_par_err_det_d;
wire p1_par_err_det_e;
wire p1_par_err_det_f;
wire p1_par_err_det_g;
wire p1_par_err_det_h;
wire [0:PARBITS-1] p0_way_par_a;
wire [0:PARBITS-1] p0_way_par_b;
wire [0:PARBITS-1] p0_way_par_c;
wire [0:PARBITS-1] p0_way_par_d;
wire [0:PARBITS-1] p0_way_par_e;
wire [0:PARBITS-1] p0_way_par_f;
wire [0:PARBITS-1] p0_way_par_g;
wire [0:PARBITS-1] p0_way_par_h;
wire [0:7] ex4_en_par_chk_d;
wire [0:7] ex4_en_par_chk_q;
wire ex4_perr_det_a;
wire ex4_perr_det_b;
wire ex4_perr_det_c;
wire ex4_perr_det_d;
wire ex4_perr_det_e;
wire ex4_perr_det_f;
wire ex4_perr_det_g;
wire ex4_perr_det_h;
wire [0:7] stq3_en_par_chk_d;
wire [0:7] stq3_en_par_chk_q;
wire stq3_perr_det_a;
wire stq3_perr_det_b;
wire stq3_perr_det_c;
wire stq3_perr_det_d;
wire stq3_perr_det_e;
wire stq3_perr_det_f;
wire stq3_perr_det_g;
wire stq3_perr_det_h;
//--------------------------
// constants
//--------------------------
parameter ex3_binv_val_offset = 0;
parameter inj_ddir_ldp_parity_offset = ex3_binv_val_offset + 1;
parameter inj_ddir_stp_parity_offset = inj_ddir_ldp_parity_offset + 1;
parameter stq2_addr_offset = inj_ddir_stp_parity_offset + 1;
parameter stq3_addr_offset = stq2_addr_offset + (lwrCClassBit - uprTagBit) + 1;
parameter stq4_addr_offset = stq3_addr_offset + (lwrCClassBit - uprTagBit) + 1;
parameter ex4_en_par_chk_offset = stq4_addr_offset + (lwrCClassBit - uprTagBit) + 1;
parameter stq3_en_par_chk_offset = ex4_en_par_chk_offset + 8;
parameter scan_right = stq3_en_par_chk_offset + 8 - 1;
wire tiup;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
// ####################################################
// Inputs
// ####################################################
assign tiup = 1'b1;
assign stq2_addr_d = lsq_ctl_stq1_addr;
assign stq3_addr_d = stq2_addr_q;
assign stq4_addr_d = stq3_addr_q;
assign ex3_binv_val_d = dcc_dir_ex2_binv_val;
assign inj_ddir_ldp_parity_d = pc_lq_inj_dcachedir_ldp_parity;
assign inj_ddir_stp_parity_d = pc_lq_inj_dcachedir_stp_parity;
// ####################################################
// Dcache Number of Cachelines Configurations
// ####################################################
assign arr_wr_addr = stq4_addr_q[uprCClassBit:lwrCClassBit];
// ####################################################
// LQ Pipe
// ####################################################
// ####################################################
// Directory Update
// ####################################################
// Directory Congruence Class Write Address
assign arr_wr_data[uprTagBit:lwrTagBit] = stq4_addr_q[uprTagBit:lwrTagBit];
// ####################################################
// Tag Array Access
// 1) Contains the Array of Tags
// ####################################################
lq_dir_tag_arr #(.WAYDATASIZE(WAYDATASIZE), .PARBITS(PARBITS)) l1dcta(
.wdata(arr_wr_data),
.dir_arr_rd_data0(dir_arr_rd_data0),
.dir_arr_rd_data1(dir_arr_rd_data1),
.inj_ddir_p0_parity(inj_ddir_ldp_parity_q),
.inj_ddir_p1_parity(inj_ddir_stp_parity_q),
.dir_arr_wr_data(dir_arr_wr_data),
.p0_way_tag_a(p0_way_tag_a),
.p0_way_tag_b(p0_way_tag_b),
.p0_way_tag_c(p0_way_tag_c),
.p0_way_tag_d(p0_way_tag_d),
.p0_way_tag_e(p0_way_tag_e),
.p0_way_tag_f(p0_way_tag_f),
.p0_way_tag_g(p0_way_tag_g),
.p0_way_tag_h(p0_way_tag_h),
.p1_way_tag_a(p1_way_tag_a),
.p1_way_tag_b(p1_way_tag_b),
.p1_way_tag_c(p1_way_tag_c),
.p1_way_tag_d(p1_way_tag_d),
.p1_way_tag_e(p1_way_tag_e),
.p1_way_tag_f(p1_way_tag_f),
.p1_way_tag_g(p1_way_tag_g),
.p1_way_tag_h(p1_way_tag_h),
.p0_way_par_a(p0_way_par_a),
.p0_way_par_b(p0_way_par_b),
.p0_way_par_c(p0_way_par_c),
.p0_way_par_d(p0_way_par_d),
.p0_way_par_e(p0_way_par_e),
.p0_way_par_f(p0_way_par_f),
.p0_way_par_g(p0_way_par_g),
.p0_way_par_h(p0_way_par_h),
.p0_par_err_det_a(p0_par_err_det_a),
.p0_par_err_det_b(p0_par_err_det_b),
.p0_par_err_det_c(p0_par_err_det_c),
.p0_par_err_det_d(p0_par_err_det_d),
.p0_par_err_det_e(p0_par_err_det_e),
.p0_par_err_det_f(p0_par_err_det_f),
.p0_par_err_det_g(p0_par_err_det_g),
.p0_par_err_det_h(p0_par_err_det_h),
.p1_par_err_det_a(p1_par_err_det_a),
.p1_par_err_det_b(p1_par_err_det_b),
.p1_par_err_det_c(p1_par_err_det_c),
.p1_par_err_det_d(p1_par_err_det_d),
.p1_par_err_det_e(p1_par_err_det_e),
.p1_par_err_det_f(p1_par_err_det_f),
.p1_par_err_det_g(p1_par_err_det_g),
.p1_par_err_det_h(p1_par_err_det_h)
);
// ####################################################
// Parity Reporting for Load Pipe and Back-Invalidate Pipe
// ####################################################
// Parity Check Enable
assign ex4_en_par_chk_d[0] = (dcc_dir_ex3_ddir_acc | ex3_binv_val_q) & (~spr_xucr0_dcdis);
assign ex4_en_par_chk_d[1] = (dcc_dir_ex3_ddir_acc | ex3_binv_val_q) & (~spr_xucr0_dcdis);
assign ex4_en_par_chk_d[2] = (dcc_dir_ex3_ddir_acc | ex3_binv_val_q) & (~spr_xucr0_dcdis);
assign ex4_en_par_chk_d[3] = (dcc_dir_ex3_ddir_acc | ex3_binv_val_q) & (~spr_xucr0_dcdis);
assign ex4_en_par_chk_d[4] = (dcc_dir_ex3_ddir_acc | ex3_binv_val_q) & (~spr_xucr0_dcdis);
assign ex4_en_par_chk_d[5] = (dcc_dir_ex3_ddir_acc | ex3_binv_val_q) & (~spr_xucr0_dcdis);
assign ex4_en_par_chk_d[6] = (dcc_dir_ex3_ddir_acc | ex3_binv_val_q) & (~spr_xucr0_dcdis);
assign ex4_en_par_chk_d[7] = (dcc_dir_ex3_ddir_acc | ex3_binv_val_q) & (~spr_xucr0_dcdis);
// Parity Error Detected
assign ex4_perr_det_a = p0_par_err_det_a & ex4_en_par_chk_q[0];
assign ex4_perr_det_b = p0_par_err_det_b & ex4_en_par_chk_q[1];
assign ex4_perr_det_c = p0_par_err_det_c & ex4_en_par_chk_q[2];
assign ex4_perr_det_d = p0_par_err_det_d & ex4_en_par_chk_q[3];
assign ex4_perr_det_e = p0_par_err_det_e & ex4_en_par_chk_q[4];
assign ex4_perr_det_f = p0_par_err_det_f & ex4_en_par_chk_q[5];
assign ex4_perr_det_g = p0_par_err_det_g & ex4_en_par_chk_q[6];
assign ex4_perr_det_h = p0_par_err_det_h & ex4_en_par_chk_q[7];
// ####################################################
// Parity Reporting for Store Commit Pipe
// ####################################################
// Parity Check Enable for Store Commit Pipe
assign stq3_en_par_chk_d[0] = stq2_ddir_acc & (~spr_xucr0_dcdis);
assign stq3_en_par_chk_d[1] = stq2_ddir_acc & (~spr_xucr0_dcdis);
assign stq3_en_par_chk_d[2] = stq2_ddir_acc & (~spr_xucr0_dcdis);
assign stq3_en_par_chk_d[3] = stq2_ddir_acc & (~spr_xucr0_dcdis);
assign stq3_en_par_chk_d[4] = stq2_ddir_acc & (~spr_xucr0_dcdis);
assign stq3_en_par_chk_d[5] = stq2_ddir_acc & (~spr_xucr0_dcdis);
assign stq3_en_par_chk_d[6] = stq2_ddir_acc & (~spr_xucr0_dcdis);
assign stq3_en_par_chk_d[7] = stq2_ddir_acc & (~spr_xucr0_dcdis);
// Parity Error Detected
assign stq3_perr_det_a = p1_par_err_det_a & stq3_en_par_chk_q[0];
assign stq3_perr_det_b = p1_par_err_det_b & stq3_en_par_chk_q[1];
assign stq3_perr_det_c = p1_par_err_det_c & stq3_en_par_chk_q[2];
assign stq3_perr_det_d = p1_par_err_det_d & stq3_en_par_chk_q[3];
assign stq3_perr_det_e = p1_par_err_det_e & stq3_en_par_chk_q[4];
assign stq3_perr_det_f = p1_par_err_det_f & stq3_en_par_chk_q[5];
assign stq3_perr_det_g = p1_par_err_det_g & stq3_en_par_chk_q[6];
assign stq3_perr_det_h = p1_par_err_det_h & stq3_en_par_chk_q[7];
// ####################################################
// Hit Logic
// ####################################################
assign p0_way_cmp_a = (p0_way_tag_a[uprTagBit:lwrTagBit] == dcc_dir_ex4_p_addr[uprTagBit:lwrTagBit]);
assign p0_way_cmp_b = (p0_way_tag_b[uprTagBit:lwrTagBit] == dcc_dir_ex4_p_addr[uprTagBit:lwrTagBit]);
assign p0_way_cmp_c = (p0_way_tag_c[uprTagBit:lwrTagBit] == dcc_dir_ex4_p_addr[uprTagBit:lwrTagBit]);
assign p0_way_cmp_d = (p0_way_tag_d[uprTagBit:lwrTagBit] == dcc_dir_ex4_p_addr[uprTagBit:lwrTagBit]);
assign p0_way_cmp_e = (p0_way_tag_e[uprTagBit:lwrTagBit] == dcc_dir_ex4_p_addr[uprTagBit:lwrTagBit]);
assign p0_way_cmp_f = (p0_way_tag_f[uprTagBit:lwrTagBit] == dcc_dir_ex4_p_addr[uprTagBit:lwrTagBit]);
assign p0_way_cmp_g = (p0_way_tag_g[uprTagBit:lwrTagBit] == dcc_dir_ex4_p_addr[uprTagBit:lwrTagBit]);
assign p0_way_cmp_h = (p0_way_tag_h[uprTagBit:lwrTagBit] == dcc_dir_ex4_p_addr[uprTagBit:lwrTagBit]);
assign p1_way_cmp_a = (p1_way_tag_a[uprTagBit:lwrTagBit] == stq3_addr_q[uprTagBit:lwrTagBit]);
assign p1_way_cmp_b = (p1_way_tag_b[uprTagBit:lwrTagBit] == stq3_addr_q[uprTagBit:lwrTagBit]);
assign p1_way_cmp_c = (p1_way_tag_c[uprTagBit:lwrTagBit] == stq3_addr_q[uprTagBit:lwrTagBit]);
assign p1_way_cmp_d = (p1_way_tag_d[uprTagBit:lwrTagBit] == stq3_addr_q[uprTagBit:lwrTagBit]);
assign p1_way_cmp_e = (p1_way_tag_e[uprTagBit:lwrTagBit] == stq3_addr_q[uprTagBit:lwrTagBit]);
assign p1_way_cmp_f = (p1_way_tag_f[uprTagBit:lwrTagBit] == stq3_addr_q[uprTagBit:lwrTagBit]);
assign p1_way_cmp_g = (p1_way_tag_g[uprTagBit:lwrTagBit] == stq3_addr_q[uprTagBit:lwrTagBit]);
assign p1_way_cmp_h = (p1_way_tag_h[uprTagBit:lwrTagBit] == stq3_addr_q[uprTagBit:lwrTagBit]);
// ####################################################
// Outputs
// ####################################################
// Directory Way Write Enables
assign dir_arr_wr_way = {rel_way_upd_a, rel_way_upd_b, rel_way_upd_c, rel_way_upd_d,
rel_way_upd_e, rel_way_upd_f, rel_way_upd_g, rel_way_upd_h};
assign dir_arr_wr_addr = arr_wr_addr;
assign ex4_way_cmp_a = p0_way_cmp_a;
assign ex4_way_cmp_b = p0_way_cmp_b;
assign ex4_way_cmp_c = p0_way_cmp_c;
assign ex4_way_cmp_d = p0_way_cmp_d;
assign ex4_way_cmp_e = p0_way_cmp_e;
assign ex4_way_cmp_f = p0_way_cmp_f;
assign ex4_way_cmp_g = p0_way_cmp_g;
assign ex4_way_cmp_h = p0_way_cmp_h;
assign ex4_tag_perr_way = {ex4_perr_det_a, ex4_perr_det_b, ex4_perr_det_c, ex4_perr_det_d,
ex4_perr_det_e, ex4_perr_det_f, ex4_perr_det_g, ex4_perr_det_h};
assign dir_dcc_ex4_way_tag_a = p0_way_tag_a;
assign dir_dcc_ex4_way_tag_b = p0_way_tag_b;
assign dir_dcc_ex4_way_tag_c = p0_way_tag_c;
assign dir_dcc_ex4_way_tag_d = p0_way_tag_d;
assign dir_dcc_ex4_way_tag_e = p0_way_tag_e;
assign dir_dcc_ex4_way_tag_f = p0_way_tag_f;
assign dir_dcc_ex4_way_tag_g = p0_way_tag_g;
assign dir_dcc_ex4_way_tag_h = p0_way_tag_h;
assign dir_dcc_ex4_way_par_a = p0_way_par_a;
assign dir_dcc_ex4_way_par_b = p0_way_par_b;
assign dir_dcc_ex4_way_par_c = p0_way_par_c;
assign dir_dcc_ex4_way_par_d = p0_way_par_d;
assign dir_dcc_ex4_way_par_e = p0_way_par_e;
assign dir_dcc_ex4_way_par_f = p0_way_par_f;
assign dir_dcc_ex4_way_par_g = p0_way_par_g;
assign dir_dcc_ex4_way_par_h = p0_way_par_h;
assign stq3_way_cmp_a = p1_way_cmp_a;
assign stq3_way_cmp_b = p1_way_cmp_b;
assign stq3_way_cmp_c = p1_way_cmp_c;
assign stq3_way_cmp_d = p1_way_cmp_d;
assign stq3_way_cmp_e = p1_way_cmp_e;
assign stq3_way_cmp_f = p1_way_cmp_f;
assign stq3_way_cmp_g = p1_way_cmp_g;
assign stq3_way_cmp_h = p1_way_cmp_h;
assign stq3_tag_way_perr = {stq3_perr_det_a, stq3_perr_det_b, stq3_perr_det_c, stq3_perr_det_d,
stq3_perr_det_e, stq3_perr_det_f, stq3_perr_det_g, stq3_perr_det_h};
// ####################################################
// Back Invalidate Registers
// ####################################################
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_slp_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_slp_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_binv_val_offset]),
.scout(sov[ex3_binv_val_offset]),
.din(ex3_binv_val_d),
.dout(ex3_binv_val_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_ddir_ldp_parity_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[inj_ddir_ldp_parity_offset]),
.scout(sov[inj_ddir_ldp_parity_offset]),
.din(inj_ddir_ldp_parity_d),
.dout(inj_ddir_ldp_parity_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_ddir_stp_parity_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[inj_ddir_stp_parity_offset]),
.scout(sov[inj_ddir_stp_parity_offset]),
.din(inj_ddir_stp_parity_d),
.dout(inj_ddir_stp_parity_q)
);
tri_rlmreg_p #(.WIDTH((lwrCClassBit - uprTagBit) + 1), .INIT(0), .NEEDS_SRESET(1)) stq2_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(dcc_dir_stq1_stg_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq2_addr_offset:stq2_addr_offset + (lwrCClassBit-uprTagBit+1) - 1]),
.scout(sov[stq2_addr_offset:stq2_addr_offset + (lwrCClassBit-uprTagBit+1) - 1]),
.din(stq2_addr_d),
.dout(stq2_addr_q)
);
tri_rlmreg_p #(.WIDTH((lwrCClassBit - uprTagBit) + 1), .INIT(0), .NEEDS_SRESET(1)) stq3_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(dcc_dir_stq2_stg_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq3_addr_offset:stq3_addr_offset + (lwrCClassBit-uprTagBit+1) - 1]),
.scout(sov[stq3_addr_offset:stq3_addr_offset + (lwrCClassBit-uprTagBit+1) - 1]),
.din(stq3_addr_d),
.dout(stq3_addr_q)
);
tri_rlmreg_p #(.WIDTH((lwrCClassBit - uprTagBit) + 1), .INIT(0), .NEEDS_SRESET(1)) stq4_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(dcc_dir_stq3_stg_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq4_addr_offset:stq4_addr_offset + (lwrCClassBit-uprTagBit+1) - 1]),
.scout(sov[stq4_addr_offset:stq4_addr_offset + (lwrCClassBit-uprTagBit+1) - 1]),
.din(stq4_addr_d),
.dout(stq4_addr_q)
);
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_en_par_chk_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_slp_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_slp_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex4_en_par_chk_offset:ex4_en_par_chk_offset + 8 - 1]),
.scout(sov[ex4_en_par_chk_offset:ex4_en_par_chk_offset + 8 - 1]),
.din(ex4_en_par_chk_d),
.dout(ex4_en_par_chk_q)
);
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq3_en_par_chk_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq3_en_par_chk_offset:stq3_en_par_chk_offset + 8 - 1]),
.scout(sov[stq3_en_par_chk_offset:stq3_en_par_chk_offset + 8 - 1]),
.din(stq3_en_par_chk_d),
.dout(stq3_en_par_chk_q)
);
assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
assign scan_out = sov[0];
endmodule |
module lq_dir_tag_arr(
wdata,
dir_arr_rd_data0,
dir_arr_rd_data1,
inj_ddir_p0_parity,
inj_ddir_p1_parity,
dir_arr_wr_data,
p0_way_tag_a,
p0_way_tag_b,
p0_way_tag_c,
p0_way_tag_d,
p0_way_tag_e,
p0_way_tag_f,
p0_way_tag_g,
p0_way_tag_h,
p1_way_tag_a,
p1_way_tag_b,
p1_way_tag_c,
p1_way_tag_d,
p1_way_tag_e,
p1_way_tag_f,
p1_way_tag_g,
p1_way_tag_h,
p0_way_par_a,
p0_way_par_b,
p0_way_par_c,
p0_way_par_d,
p0_way_par_e,
p0_way_par_f,
p0_way_par_g,
p0_way_par_h,
p0_par_err_det_a,
p0_par_err_det_b,
p0_par_err_det_c,
p0_par_err_det_d,
p0_par_err_det_e,
p0_par_err_det_f,
p0_par_err_det_g,
p0_par_err_det_h,
p1_par_err_det_a,
p1_par_err_det_b,
p1_par_err_det_c,
p1_par_err_det_d,
p1_par_err_det_e,
p1_par_err_det_f,
p1_par_err_det_g,
p1_par_err_det_h
);
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//parameter `DC_SIZE = 15; // 2^14 = 16384, 2^15 = 32768 Bytes L1 D$
//parameter `CL_SIZE = 6; // 2^6 = 64 Bytes CacheLines
//parameter `REAL_IFAR_WIDTH = 42; // 42 bit real address
parameter WAYDATASIZE = 34; // TagSize + Parity Bits
parameter PARBITS = 4; // Parity Bits
// Write Path
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] wdata;
// Directory Array Read Data
input [0:(8*WAYDATASIZE)-1] dir_arr_rd_data0;
input [0:(8*WAYDATASIZE)-1] dir_arr_rd_data1;
// Parity Error Injection
input inj_ddir_p0_parity;
input inj_ddir_p1_parity;
// Directory Array Write Controls
output [64-`REAL_IFAR_WIDTH:64-`REAL_IFAR_WIDTH+WAYDATASIZE-1] dir_arr_wr_data;
// Way Tag Data
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_a;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_b;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_c;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_d;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_e;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_f;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_g;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_h;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_a;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_b;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_c;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_d;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_e;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_f;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_g;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_h;
// Way Tag Parity
output [0:PARBITS-1] p0_way_par_a;
output [0:PARBITS-1] p0_way_par_b;
output [0:PARBITS-1] p0_way_par_c;
output [0:PARBITS-1] p0_way_par_d;
output [0:PARBITS-1] p0_way_par_e;
output [0:PARBITS-1] p0_way_par_f;
output [0:PARBITS-1] p0_way_par_g;
output [0:PARBITS-1] p0_way_par_h;
// Parity Error Detected
output p0_par_err_det_a;
output p0_par_err_det_b;
output p0_par_err_det_c;
output p0_par_err_det_d;
output p0_par_err_det_e;
output p0_par_err_det_f;
output p0_par_err_det_g;
output p0_par_err_det_h;
output p1_par_err_det_a;
output p1_par_err_det_b;
output p1_par_err_det_c;
output p1_par_err_det_d;
output p1_par_err_det_e;
output p1_par_err_det_f;
output p1_par_err_det_g;
output p1_par_err_det_h;
//--------------------------
// components
//--------------------------
//--------------------------
// constants
//--------------------------
parameter uprTagBit = 64 - `REAL_IFAR_WIDTH;
parameter lwrTagBit = 63 - (`DC_SIZE - 3);
parameter tagSize = lwrTagBit - uprTagBit + 1;
parameter numWays = 8;
//--------------------------
// signals
//--------------------------
wire [uprTagBit:lwrTagBit] wr_data;
wire [uprTagBit:lwrTagBit] p0_rd_way[0:numWays-1];
wire [uprTagBit:lwrTagBit] p1_rd_way[0:numWays-1];
wire [0:(8*WAYDATASIZE)-1] arr_rd_data0;
wire [0:(8*WAYDATASIZE)-1] arr_rd_data1;
wire [0:PARBITS-1] arr_parity;
wire [0:7] extra_byte_par;
wire [uprTagBit:lwrTagBit+PARBITS] arr_wr_data;
wire [0:PARBITS-1] p0_rd_par_arr;
wire [0:PARBITS-1] p1_rd_par_arr;
wire [0:PARBITS-1] p0_rd_par[0:numWays-1];
wire [0:PARBITS-1] p1_rd_par[0:numWays-1];
wire [0:7] p0_extra_tag_par[0:numWays-1];
wire [0:7] p1_extra_tag_par[0:numWays-1];
wire [0:PARBITS-1] p0_par_err_det[0:numWays-1];
wire [0:PARBITS-1] p1_par_err_det[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p0_par_gen_1stlvla[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p0_par_gen_1stlvlb[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p0_par_gen_1stlvlc[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p0_par_gen_1stlvld[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p0_parity_gen_1b[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p0_parity_gen_2b[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p1_par_gen_1stlvla[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p1_par_gen_1stlvlb[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p1_par_gen_1stlvlc[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p1_par_gen_1stlvld[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p1_parity_gen_1b[0:numWays-1];
(* NO_MODIFICATION="TRUE" *)
wire [0:PARBITS-1] p1_parity_gen_2b[0:numWays-1];
// ####################################################
// Inputs
// ####################################################
assign arr_rd_data0 = dir_arr_rd_data0;
assign arr_rd_data1 = dir_arr_rd_data1;
assign wr_data = wdata;
// ####################################################
// Array Parity Generation
// ####################################################
generate begin : extra_byte
genvar t;
for (t = 0; t <= 7; t = t + 1) begin : extra_byte
if (t < (tagSize % 8)) begin : R0
assign extra_byte_par[t] = wr_data[uprTagBit+(8*(tagSize/8)) + t];
end
if (t >= (tagSize % 8)) begin : R1
assign extra_byte_par[t] = 1'b0;
end
end
end
endgenerate
generate begin : par_gen
genvar i;
for (i = 0; i <= (tagSize/8) - 1; i = i + 1) begin : par_gen
assign arr_parity[i] = ^(wr_data[8*i+uprTagBit:8*i+uprTagBit+7]);
end
end
endgenerate
generate
if ((tagSize % 8) != 0) begin : par_gen_x
assign arr_parity[tagSize/8] = ^(extra_byte_par);
end
endgenerate
assign arr_wr_data = {wr_data, arr_parity};
// ####################################################
// Tag Array Read
// ####################################################
generate begin : tagRead
genvar way;
for (way=0; way<numWays; way=way+1) begin : tagRead
assign p0_rd_way[way] = arr_rd_data0[(way*WAYDATASIZE):(way*WAYDATASIZE) + tagSize - 1];
assign p1_rd_way[way] = arr_rd_data1[(way*WAYDATASIZE):(way*WAYDATASIZE) + tagSize - 1];
if (way == 0) begin :injErr
assign p0_rd_par_arr = arr_rd_data0[(way*WAYDATASIZE) + tagSize:(way*WAYDATASIZE) + tagSize + PARBITS - 1];
assign p0_rd_par[way] = {(p0_rd_par_arr[0] ^ inj_ddir_p0_parity), p0_rd_par_arr[1:PARBITS - 1]};
assign p1_rd_par_arr = arr_rd_data1[(way*WAYDATASIZE) + tagSize:(way*WAYDATASIZE) + tagSize + PARBITS - 1];
assign p1_rd_par[way] = {(p1_rd_par_arr[0] ^ inj_ddir_p1_parity), p1_rd_par_arr[1:PARBITS - 1]};
end
if (way != 0) begin :noErr
assign p0_rd_par[way] = arr_rd_data0[(way*WAYDATASIZE) + tagSize:(way*WAYDATASIZE) + tagSize + PARBITS - 1];
assign p1_rd_par[way] = arr_rd_data1[(way*WAYDATASIZE) + tagSize:(way*WAYDATASIZE) + tagSize + PARBITS - 1];
end
end
end
endgenerate
// ####################################################
// Tag Parity Generation
// ####################################################
generate begin : rdExtraByte
genvar way;
for (way=0; way<numWays; way=way+1) begin : rdExtraByte
genvar t;
for (t=0; t<8; t=t+1) begin : rdExtraByte
if (t < (tagSize % 8)) begin : R0
assign p0_extra_tag_par[way][t] = p0_rd_way[way][uprTagBit + (8 * (tagSize/8)) + t];
assign p1_extra_tag_par[way][t] = p1_rd_way[way][uprTagBit + (8 * (tagSize/8)) + t];
end
if (t >= (tagSize % 8)) begin : R1
assign p0_extra_tag_par[way][t] = 1'b0;
assign p1_extra_tag_par[way][t] = 1'b0;
end
end
end
end
endgenerate
generate begin : rdParGen
genvar way;
for (way=0; way<numWays; way=way+1) begin : rdParGen
genvar i;
for (i = 0; i <= (tagSize/8) - 1; i = i + 1) begin : rdParGen
// Port 0
//assign p0_par_gen_1stlvla[way][i] = (~(p0_rd_way[way][8 * i + uprTagBit + 0] ^ p0_rd_way[way][8 * i + uprTagBit + 1]));
tri_xnor2 p0_par_gen_1stlvla_0 (.y(p0_par_gen_1stlvla[way][i]), .a(p0_rd_way[way][8*i + uprTagBit+0]), .b(p0_rd_way[way][8*i + uprTagBit+1]));
//assign p0_par_gen_1stlvlb[way][i] = (~(p0_rd_way[way][8 * i + uprTagBit + 2] ^ p0_rd_way[way][8 * i + uprTagBit + 3]));
tri_xnor2 p0_par_gen_1stlvlb_0 (.y(p0_par_gen_1stlvlb[way][i]), .a(p0_rd_way[way][8*i + uprTagBit+2]), .b(p0_rd_way[way][8*i + uprTagBit+3]));
//assign p0_par_gen_1stlvlc[way][i] = (~(p0_rd_way[way][8 * i + uprTagBit + 4] ^ p0_rd_way[way][8 * i + uprTagBit + 5]));
tri_xnor2 p0_par_gen_1stlvlc_0 (.y(p0_par_gen_1stlvlc[way][i]), .a(p0_rd_way[way][8*i + uprTagBit+4]), .b(p0_rd_way[way][8*i + uprTagBit+5]));
//assign p0_par_gen_1stlvld[way][i] = (~(p0_rd_way[way][8 * i + uprTagBit + 6] ^ p0_rd_way[way][8 * i + uprTagBit + 7]));
tri_xnor2 p0_par_gen_1stlvld_0 (.y(p0_par_gen_1stlvld[way][i]), .a(p0_rd_way[way][8*i + uprTagBit+6]), .b(p0_rd_way[way][8*i + uprTagBit+7]));
//assign p0_parity_gen_1b[way][i] = (~(p0_par_gen_1stlvla[way][i] ^ p0_par_gen_1stlvlb[way][i]));
tri_xnor2 p0_parity_gen_1b_0 (.y(p0_parity_gen_1b[way][i]), .a(p0_par_gen_1stlvla[way][i]), .b(p0_par_gen_1stlvlb[way][i]));
//assign p0_parity_gen_2b[way][i] = (~(p0_par_gen_1stlvlc[way][i] ^ p0_par_gen_1stlvld[way][i]));
tri_xnor2 p0_parity_gen_2b_0 (.y(p0_parity_gen_2b[way][i]), .a(p0_par_gen_1stlvlc[way][i]), .b(p0_par_gen_1stlvld[way][i]));
// Port 1
//assign p1_par_gen_1stlvla[way][i] = (~(p1_rd_way[way][8 * i + uprTagBit + 0] ^ p1_rd_way[way][8 * i + uprTagBit + 1]));
tri_xnor2 p1_par_gen_1stlvla_0 (.y(p1_par_gen_1stlvla[way][i]), .a(p1_rd_way[way][8*i + uprTagBit+0]), .b(p1_rd_way[way][8*i + uprTagBit+1]));
//assign p1_par_gen_1stlvlb[way][i] = (~(p1_rd_way[way][8 * i + uprTagBit + 2] ^ p1_rd_way[way][8 * i + uprTagBit + 3]));
tri_xnor2 p1_par_gen_1stlvlb_0 (.y(p1_par_gen_1stlvlb[way][i]), .a(p1_rd_way[way][8*i + uprTagBit+2]), .b(p1_rd_way[way][8*i + uprTagBit+3]));
//assign p1_par_gen_1stlvlc[way][i] = (~(p1_rd_way[way][8 * i + uprTagBit + 4] ^ p1_rd_way[way][8 * i + uprTagBit + 5]));
tri_xnor2 p1_par_gen_1stlvlc_0 (.y(p1_par_gen_1stlvlc[way][i]), .a(p1_rd_way[way][8*i + uprTagBit+4]), .b(p1_rd_way[way][8*i + uprTagBit+5]));
//assign p1_par_gen_1stlvld[way][i] = (~(p1_rd_way[way][8 * i + uprTagBit + 6] ^ p1_rd_way[way][8 * i + uprTagBit + 7]));
tri_xnor2 p1_par_gen_1stlvld_0 (.y(p1_par_gen_1stlvld[way][i]), .a(p1_rd_way[way][8*i + uprTagBit+6]), .b(p1_rd_way[way][8*i + uprTagBit+7]));
//assign p1_parity_gen_1b[way][i] = (~(p1_par_gen_1stlvla[way][i] ^ p1_par_gen_1stlvlb[way][i]));
tri_xnor2 p1_parity_gen_1b_0 (.y(p1_parity_gen_1b[way][i]), .a(p1_par_gen_1stlvla[way][i]), .b(p1_par_gen_1stlvlb[way][i]));
//assign p1_parity_gen_2b[way][i] = (~(p1_par_gen_1stlvlc[way][i] ^ p1_par_gen_1stlvld[way][i]));
tri_xnor2 p1_parity_gen_2b_0 (.y(p1_parity_gen_2b[way][i]), .a(p1_par_gen_1stlvlc[way][i]), .b(p1_par_gen_1stlvld[way][i]));
end
end
end
endgenerate
generate
if ((tagSize % 8) != 0) begin : rdParGenx
genvar way;
for (way=0; way<numWays; way=way+1) begin : rdParGenx
// Port 0
assign p0_par_gen_1stlvla[way][PARBITS - 1] = (~(p0_extra_tag_par[way][0] ^ p0_extra_tag_par[way][1]));
assign p0_par_gen_1stlvlb[way][PARBITS - 1] = (~(p0_extra_tag_par[way][2] ^ p0_extra_tag_par[way][3]));
assign p0_par_gen_1stlvlc[way][PARBITS - 1] = (~(p0_extra_tag_par[way][4] ^ p0_extra_tag_par[way][5]));
assign p0_par_gen_1stlvld[way][PARBITS - 1] = (~(p0_extra_tag_par[way][6] ^ p0_extra_tag_par[way][7]));
assign p0_parity_gen_1b[way][PARBITS - 1] = (~(p0_par_gen_1stlvla[way][PARBITS - 1] ^ p0_par_gen_1stlvlb[way][PARBITS - 1]));
assign p0_parity_gen_2b[way][PARBITS - 1] = (~(p0_par_gen_1stlvlc[way][PARBITS - 1] ^ p0_par_gen_1stlvld[way][PARBITS - 1]));
// Port 1
assign p1_par_gen_1stlvla[way][PARBITS - 1] = (~(p1_extra_tag_par[way][0] ^ p1_extra_tag_par[way][1]));
assign p1_par_gen_1stlvlb[way][PARBITS - 1] = (~(p1_extra_tag_par[way][2] ^ p1_extra_tag_par[way][3]));
assign p1_par_gen_1stlvlc[way][PARBITS - 1] = (~(p1_extra_tag_par[way][4] ^ p1_extra_tag_par[way][5]));
assign p1_par_gen_1stlvld[way][PARBITS - 1] = (~(p1_extra_tag_par[way][6] ^ p1_extra_tag_par[way][7]));
assign p1_parity_gen_1b[way][PARBITS - 1] = (~(p1_par_gen_1stlvla[way][PARBITS - 1] ^ p1_par_gen_1stlvlb[way][PARBITS - 1]));
assign p1_parity_gen_2b[way][PARBITS - 1] = (~(p1_par_gen_1stlvlc[way][PARBITS - 1] ^ p1_par_gen_1stlvld[way][PARBITS - 1]));
end
end
endgenerate
// ####################################################
// Parity Error Detect
// ####################################################
generate begin : parDet
genvar way;
for (way=0; way<numWays; way=way+1) begin : parDet
assign p0_par_err_det[way] = p0_parity_gen_1b[way] ^ p0_parity_gen_2b[way] ^ p0_rd_par[way];
assign p1_par_err_det[way] = p1_parity_gen_1b[way] ^ p1_parity_gen_2b[way] ^ p1_rd_par[way];
end
end
endgenerate
// ####################################################
// Outputs
// ####################################################
// Directory Array Write Data
assign dir_arr_wr_data = arr_wr_data;
// Directory Array Read Tags
assign p0_way_tag_a = p0_rd_way[0];
assign p0_way_tag_b = p0_rd_way[1];
assign p0_way_tag_c = p0_rd_way[2];
assign p0_way_tag_d = p0_rd_way[3];
assign p0_way_tag_e = p0_rd_way[4];
assign p0_way_tag_f = p0_rd_way[5];
assign p0_way_tag_g = p0_rd_way[6];
assign p0_way_tag_h = p0_rd_way[7];
assign p1_way_tag_a = p1_rd_way[0];
assign p1_way_tag_b = p1_rd_way[1];
assign p1_way_tag_c = p1_rd_way[2];
assign p1_way_tag_d = p1_rd_way[3];
assign p1_way_tag_e = p1_rd_way[4];
assign p1_way_tag_f = p1_rd_way[5];
assign p1_way_tag_g = p1_rd_way[6];
assign p1_way_tag_h = p1_rd_way[7];
// Directory Array Read Parity
assign p0_way_par_a = p0_rd_par[0];
assign p0_way_par_b = p0_rd_par[1];
assign p0_way_par_c = p0_rd_par[2];
assign p0_way_par_d = p0_rd_par[3];
assign p0_way_par_e = p0_rd_par[4];
assign p0_way_par_f = p0_rd_par[5];
assign p0_way_par_g = p0_rd_par[6];
assign p0_way_par_h = p0_rd_par[7];
// Directory Parity Error Detected
assign p0_par_err_det_a = |(p0_par_err_det[0]);
assign p0_par_err_det_b = |(p0_par_err_det[1]);
assign p0_par_err_det_c = |(p0_par_err_det[2]);
assign p0_par_err_det_d = |(p0_par_err_det[3]);
assign p0_par_err_det_e = |(p0_par_err_det[4]);
assign p0_par_err_det_f = |(p0_par_err_det[5]);
assign p0_par_err_det_g = |(p0_par_err_det[6]);
assign p0_par_err_det_h = |(p0_par_err_det[7]);
assign p1_par_err_det_a = |(p1_par_err_det[0]);
assign p1_par_err_det_b = |(p1_par_err_det[1]);
assign p1_par_err_det_c = |(p1_par_err_det[2]);
assign p1_par_err_det_d = |(p1_par_err_det[3]);
assign p1_par_err_det_e = |(p1_par_err_det[4]);
assign p1_par_err_det_f = |(p1_par_err_det[5]);
assign p1_par_err_det_g = |(p1_par_err_det[6]);
assign p1_par_err_det_h = |(p1_par_err_det[7]);
endmodule |
module fu_divsqrt_q_table(
x,
cin,
q
);
`include "tri_a2o.vh"
input [0:3] x;
input cin;
output q;
wire nor123;
wire nor123_b;
wire x0_b;
wire not0and1or2or3_b;
wire nor01;
wire nor23;
wire not0or1or2or3_and_cin_b;
//// Implements this table:
// assign exx_q_bit0_prebuf = (exx_sum4 == 4'b0000) ? exx_q_bit0_cin :
// (exx_sum4 == 4'b0001) ? 1'b1 :
// (exx_sum4 == 4'b0010) ? 1'b1 :
// (exx_sum4 == 4'b0011) ? 1'b1 :
// (exx_sum4 == 4'b0100) ? 1'b1 :
// (exx_sum4 == 4'b0101) ? 1'b1 :
// (exx_sum4 == 4'b0110) ? 1'b1 :
// (exx_sum4 == 4'b0111) ? 1'b1 :
// 1'b0;
tri_nor3 #(.WIDTH(1), .BTR("NOR3_X4M_A9TH")) DIVSQRT_N_TABLE_NOR3_01(nor123, x[1], x[2], x[3]);
tri_inv #(.WIDTH(1), .BTR("INV_X3M_A9TH")) DIVSQRT_N_TABLE_INV_02a(nor123_b, nor123);
tri_inv #(.WIDTH(1), .BTR("INV_X5B_A9TH")) DIVSQRT_N_TABLE_INV_02b(x0_b, x[0]);
tri_nand2 #(.WIDTH(1), .BTR("NAND2_X4A_A9TH")) DIVSQRT_N_TABLE_NAND2_03(not0and1or2or3_b, x0_b, nor123_b);
//
tri_nor2 #(.WIDTH(1), .BTR("NOR2_X8B_A9TH")) DIVSQRT_N_TABLE_NOR2_01a(nor01, x[0], x[1]);
tri_nor2 #(.WIDTH(1), .BTR("NOR2_X4B_A9TH")) DIVSQRT_N_TABLE_NOR2_01b(nor23, x[2], x[3]);
tri_nand3 #(.WIDTH(1), .BTR("NAND3_X6M_A9TH")) DIVSQRT_N_TABLE_NAND3_02(not0or1or2or3_and_cin_b, nor01, nor23, cin);
//
tri_nand2 #(.WIDTH(1), .BTR("NAND2_X8A_A9TH")) DIVSQRT_N_TABLE_NAND2_04(q, not0or1or2or3_and_cin_b, not0and1or2or3_b);
endmodule |
module fu_tblexp(
vdd,
gnd,
clkoff_b,
act_dis,
flush,
delay_lclkr,
mpw1_b,
mpw2_b,
sg_1,
thold_1,
fpu_enable,
nclk,
si,
so,
ex2_act_b,
f_pic_ex3_ue1,
f_pic_ex3_sp_b,
f_pic_ex3_est_recip,
f_pic_ex3_est_rsqrt,
f_eie_ex3_tbl_expo,
f_fmt_ex3_lu_den_recip,
f_fmt_ex3_lu_den_rsqrto,
f_tbe_ex4_recip_ue1,
f_tbe_ex4_lu_sh,
f_tbe_ex4_match_en_sp,
f_tbe_ex4_match_en_dp,
f_tbe_ex4_recip_2046,
f_tbe_ex4_recip_2045,
f_tbe_ex4_recip_2044,
f_tbe_ex4_may_ov,
f_tbe_ex4_res_expo
);
`include "tri_a2o.vh"
inout vdd;
inout gnd;
input clkoff_b; // tiup
input act_dis; // ??tidn??
input flush; // ??tidn??
input [2:3] delay_lclkr; // tidn,
input [2:3] mpw1_b; // tidn,
input [0:0] mpw2_b; // tidn,
input sg_1;
input thold_1;
input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
input si; // perv
output so; // perv
input ex2_act_b; // act
input f_pic_ex3_ue1;
input f_pic_ex3_sp_b;
input f_pic_ex3_est_recip;
input f_pic_ex3_est_rsqrt;
input [1:13] f_eie_ex3_tbl_expo;
input f_fmt_ex3_lu_den_recip;
input f_fmt_ex3_lu_den_rsqrto;
output f_tbe_ex4_recip_ue1;
output f_tbe_ex4_lu_sh;
output f_tbe_ex4_match_en_sp;
output f_tbe_ex4_match_en_dp;
output f_tbe_ex4_recip_2046;
output f_tbe_ex4_recip_2045;
output f_tbe_ex4_recip_2044;
output f_tbe_ex4_may_ov;
output [1:13] f_tbe_ex4_res_expo; // to rounder
// end ports
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire thold_0_b;
wire thold_0;
wire force_t;
wire sg_0;
wire [0:3] act_spare_unused;
wire ex3_act;
wire [0:4] act_so;
wire [0:4] act_si;
wire [0:19] ex4_expo_so;
wire [0:19] ex4_expo_si;
wire [1:13] ex3_res_expo;
wire [1:13] ex4_res_expo;
wire ex4_recip_2044;
wire ex3_recip_2044;
wire ex3_recip_ue1;
wire ex4_recip_2045;
wire ex3_recip_2045;
wire ex4_recip_ue1;
wire ex4_recip_2046;
wire ex3_recip_2046;
wire ex4_force_expo_den;
wire [1:13] ex3_b_expo_adj_b;
wire [1:13] ex3_b_expo_adj;
wire [1:13] ex3_recip_k;
wire [1:13] ex3_recip_p;
wire [2:13] ex3_recip_g;
wire [2:12] ex3_recip_t;
wire [2:13] ex3_recip_c;
wire [1:13] ex3_recip_expo;
wire [1:13] ex3_rsqrt_k;
wire [1:13] ex3_rsqrt_p;
wire [2:13] ex3_rsqrt_g;
wire [2:12] ex3_rsqrt_t;
wire [2:13] ex3_rsqrt_c;
wire [1:13] ex3_rsqrt_expo;
wire [1:13] ex3_rsqrt_bsh_b;
wire [2:13] ex3_recip_g2;
wire [2:11] ex3_recip_t2;
wire [2:13] ex3_recip_g4;
wire [2:9] ex3_recip_t4;
wire [2:13] ex3_recip_g8;
wire [2:5] ex3_recip_t8;
wire [2:13] ex3_rsqrt_g2;
wire [2:11] ex3_rsqrt_t2;
wire [2:13] ex3_rsqrt_g4;
wire [2:9] ex3_rsqrt_t4;
wire [2:13] ex3_rsqrt_g8;
wire [2:5] ex3_rsqrt_t8;
wire ex2_act;
wire ex3_lu_sh;
wire ex4_lu_sh;
wire [2:13] ex4_res_expo_c;
wire [2:13] ex4_res_expo_g8_b;
wire [2:13] ex4_res_expo_g4;
wire [2:13] ex4_res_expo_g2_b;
wire [1:13] ex4_res_decr;
wire [1:13] ex4_res_expo_b;
wire ex4_decr_expo;
wire ex3_mid_match_ifsp;
wire ex3_mid_match_ifdp;
wire ex3_match_en_dp;
wire ex3_match_en_sp;
wire ex4_match_en_dp;
wire ex4_match_en_sp;
wire ex3_com_match;
wire ex4_recip_2044_dp;
wire ex4_recip_2045_dp;
wire ex4_recip_2046_dp;
////############################################
////# pervasive
////############################################
tri_plat thold_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(thold_1),
.q(thold_0)
);
tri_plat sg_reg_0(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(flush),
.din(sg_1),
.q(sg_0)
);
tri_lcbor lcbor_0(
.clkoff_b(clkoff_b),
.thold(thold_0),
.sg(sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(thold_0_b)
);
////############################################
////# ACT LATCHES
////############################################
assign ex2_act = (~ex2_act_b);
tri_rlmreg_p #(.WIDTH(5)) act_lat(
.force_t(force_t), //tidn,
.d_mode(tiup), // => d_mode ,--tiup,
.delay_lclkr(delay_lclkr[2]), //tidn,
.mpw1_b(mpw1_b[2]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(fpu_enable),
.scout(act_so),
.scin(act_si),
//-----------------
.din({ act_spare_unused[0],
act_spare_unused[1],
ex2_act,
act_spare_unused[2],
act_spare_unused[3]}),
//-----------------
.dout({ act_spare_unused[0],
act_spare_unused[1],
ex3_act,
act_spare_unused[2],
act_spare_unused[3]})
);
////##############################################
////# EX3 logic
////##############################################
// 1* 2 3 4 5* 6 7 8 9* 10 11 12 13*
// * * * *
// 0 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 sqrt_q0
// 0 0 1 1 1 1 1 1 1 1 1 1 0
// * * * *
// !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 !B13 fres
// 0 0 1 1 1 1 1 1 1 1 1 1 0
// * * * *
// 1 !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 rsqrte
// 0 0 1 0 1 1 1 1 1 1 1 1 !B13
// * * * *
//-----------------------------------------------------------------------------
// 1 !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 rsqrte
// 0 0 1 0 1 1 1 1 1 1 1 1 (!c5 +!B13 +<1>)
// 1 1 1 1 1 1 1 1 !c0 !c1 !c2 !c3 !c4
//
// !c5 + !b13 + <1> | or xnor | or+xnor => put into LSB position
//------------------+-----------+--------
// 0 0 | 0 1 | 1+0
// 0 1 | 1 0 | 1+0
// 1 0 | 1 0 | 1+0
// 1 1 | 1 1 | 1+1
////#--------------------------------------------
////# first generate B - clz (upper half should be carry select)
////#----------------------------------------------
////# upper half should be carry select decrementer
assign ex3_b_expo_adj[1:13] = f_eie_ex3_tbl_expo[1:13];
assign ex3_b_expo_adj_b[1:13] = (~ex3_b_expo_adj[1:13]);
////#--------------------------------------------
////# adder for !(B-clz) + K_res
////#--------------------------------------------
// 1 2 3 4 5 6 7 8 9 10 11 12 13
// !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 !B13 fres
// 0 0 1 1 1 1 1 1 1 1 1 1 0
assign ex3_recip_k[1:13] = {{2{tidn}}, {10{tiup}}, tidn};
assign ex3_recip_p[1:13] = ex3_recip_k[1:13] ^ ex3_b_expo_adj_b[1:13];
assign ex3_recip_g[2:13] = ex3_recip_k[2:13] & ex3_b_expo_adj_b[2:13];
assign ex3_recip_t[2:12] = ex3_recip_k[2:12] | ex3_b_expo_adj_b[2:12];
assign ex3_recip_g2[13] = ex3_recip_g[13];
assign ex3_recip_g2[12] = ex3_recip_g[12] | (ex3_recip_t[12] & ex3_recip_g[13]);
assign ex3_recip_g2[11] = ex3_recip_g[11] | (ex3_recip_t[11] & ex3_recip_g[12]);
assign ex3_recip_g2[10] = ex3_recip_g[10] | (ex3_recip_t[10] & ex3_recip_g[11]);
assign ex3_recip_g2[9] = ex3_recip_g[9] | (ex3_recip_t[9] & ex3_recip_g[10]);
assign ex3_recip_g2[8] = ex3_recip_g[8] | (ex3_recip_t[8] & ex3_recip_g[9]);
assign ex3_recip_g2[7] = ex3_recip_g[7] | (ex3_recip_t[7] & ex3_recip_g[8]);
assign ex3_recip_g2[6] = ex3_recip_g[6] | (ex3_recip_t[6] & ex3_recip_g[7]);
assign ex3_recip_g2[5] = ex3_recip_g[5] | (ex3_recip_t[5] & ex3_recip_g[6]);
assign ex3_recip_g2[4] = ex3_recip_g[4] | (ex3_recip_t[4] & ex3_recip_g[5]);
assign ex3_recip_g2[3] = ex3_recip_g[3] | (ex3_recip_t[3] & ex3_recip_g[4]);
assign ex3_recip_g2[2] = ex3_recip_g[2] | (ex3_recip_t[2] & ex3_recip_g[3]);
assign ex3_recip_t2[11] = (ex3_recip_t[11] & ex3_recip_t[12]);
assign ex3_recip_t2[10] = (ex3_recip_t[10] & ex3_recip_t[11]);
assign ex3_recip_t2[9] = (ex3_recip_t[9] & ex3_recip_t[10]);
assign ex3_recip_t2[8] = (ex3_recip_t[8] & ex3_recip_t[9]);
assign ex3_recip_t2[7] = (ex3_recip_t[7] & ex3_recip_t[8]);
assign ex3_recip_t2[6] = (ex3_recip_t[6] & ex3_recip_t[7]);
assign ex3_recip_t2[5] = (ex3_recip_t[5] & ex3_recip_t[6]);
assign ex3_recip_t2[4] = (ex3_recip_t[4] & ex3_recip_t[5]);
assign ex3_recip_t2[3] = (ex3_recip_t[3] & ex3_recip_t[4]);
assign ex3_recip_t2[2] = (ex3_recip_t[2] & ex3_recip_t[3]);
assign ex3_recip_g4[13] = ex3_recip_g2[13];
assign ex3_recip_g4[12] = ex3_recip_g2[12];
assign ex3_recip_g4[11] = ex3_recip_g2[11] | (ex3_recip_t2[11] & ex3_recip_g2[13]);
assign ex3_recip_g4[10] = ex3_recip_g2[10] | (ex3_recip_t2[10] & ex3_recip_g2[12]);
assign ex3_recip_g4[9] = ex3_recip_g2[9] | (ex3_recip_t2[9] & ex3_recip_g2[11]);
assign ex3_recip_g4[8] = ex3_recip_g2[8] | (ex3_recip_t2[8] & ex3_recip_g2[10]);
assign ex3_recip_g4[7] = ex3_recip_g2[7] | (ex3_recip_t2[7] & ex3_recip_g2[9]);
assign ex3_recip_g4[6] = ex3_recip_g2[6] | (ex3_recip_t2[6] & ex3_recip_g2[8]);
assign ex3_recip_g4[5] = ex3_recip_g2[5] | (ex3_recip_t2[5] & ex3_recip_g2[7]);
assign ex3_recip_g4[4] = ex3_recip_g2[4] | (ex3_recip_t2[4] & ex3_recip_g2[6]);
assign ex3_recip_g4[3] = ex3_recip_g2[3] | (ex3_recip_t2[3] & ex3_recip_g2[5]);
assign ex3_recip_g4[2] = ex3_recip_g2[2] | (ex3_recip_t2[2] & ex3_recip_g2[4]);
assign ex3_recip_t4[9] = (ex3_recip_t2[9] & ex3_recip_t2[11]);
assign ex3_recip_t4[8] = (ex3_recip_t2[8] & ex3_recip_t2[10]);
assign ex3_recip_t4[7] = (ex3_recip_t2[7] & ex3_recip_t2[9]);
assign ex3_recip_t4[6] = (ex3_recip_t2[6] & ex3_recip_t2[8]);
assign ex3_recip_t4[5] = (ex3_recip_t2[5] & ex3_recip_t2[7]);
assign ex3_recip_t4[4] = (ex3_recip_t2[4] & ex3_recip_t2[6]);
assign ex3_recip_t4[3] = (ex3_recip_t2[3] & ex3_recip_t2[5]);
assign ex3_recip_t4[2] = (ex3_recip_t2[2] & ex3_recip_t2[4]);
assign ex3_recip_g8[13] = ex3_recip_g4[13];
assign ex3_recip_g8[12] = ex3_recip_g4[12];
assign ex3_recip_g8[11] = ex3_recip_g4[11];
assign ex3_recip_g8[10] = ex3_recip_g4[10];
assign ex3_recip_g8[9] = ex3_recip_g4[9] | (ex3_recip_t4[9] & ex3_recip_g4[13]);
assign ex3_recip_g8[8] = ex3_recip_g4[8] | (ex3_recip_t4[8] & ex3_recip_g4[12]);
assign ex3_recip_g8[7] = ex3_recip_g4[7] | (ex3_recip_t4[7] & ex3_recip_g4[11]);
assign ex3_recip_g8[6] = ex3_recip_g4[6] | (ex3_recip_t4[6] & ex3_recip_g4[10]);
assign ex3_recip_g8[5] = ex3_recip_g4[5] | (ex3_recip_t4[5] & ex3_recip_g4[9]);
assign ex3_recip_g8[4] = ex3_recip_g4[4] | (ex3_recip_t4[4] & ex3_recip_g4[8]);
assign ex3_recip_g8[3] = ex3_recip_g4[3] | (ex3_recip_t4[3] & ex3_recip_g4[7]);
assign ex3_recip_g8[2] = ex3_recip_g4[2] | (ex3_recip_t4[2] & ex3_recip_g4[6]);
assign ex3_recip_t8[5] = (ex3_recip_t4[5] & ex3_recip_t4[9]);
assign ex3_recip_t8[4] = (ex3_recip_t4[4] & ex3_recip_t4[8]);
assign ex3_recip_t8[3] = (ex3_recip_t4[3] & ex3_recip_t4[7]);
assign ex3_recip_t8[2] = (ex3_recip_t4[2] & ex3_recip_t4[6]);
assign ex3_recip_c[13] = ex3_recip_g8[13];
assign ex3_recip_c[12] = ex3_recip_g8[12];
assign ex3_recip_c[11] = ex3_recip_g8[11];
assign ex3_recip_c[10] = ex3_recip_g8[10];
assign ex3_recip_c[9] = ex3_recip_g8[9];
assign ex3_recip_c[8] = ex3_recip_g8[8];
assign ex3_recip_c[7] = ex3_recip_g8[7];
assign ex3_recip_c[6] = ex3_recip_g8[6];
assign ex3_recip_c[5] = ex3_recip_g8[5] | (ex3_recip_t8[5] & ex3_recip_g8[13]);
assign ex3_recip_c[4] = ex3_recip_g8[4] | (ex3_recip_t8[4] & ex3_recip_g8[12]);
assign ex3_recip_c[3] = ex3_recip_g8[3] | (ex3_recip_t8[3] & ex3_recip_g8[11]);
assign ex3_recip_c[2] = ex3_recip_g8[2] | (ex3_recip_t8[2] & ex3_recip_g8[10]);
assign ex3_recip_expo[1:12] = ex3_recip_p[1:12] ^ ex3_recip_c[2:13];
assign ex3_recip_expo[13] = ex3_recip_p[13];
////#--------------------------------------------
////# adder for !(B-clz) + K_rsqrt
////#--------------------------------------------
// 1 2 3 4 5 6 7 8 9 10 11 12 13
// 1 !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 rsqrte
// 0 0 1 0 1 1 1 1 1 1 1 1 !B13
assign ex3_rsqrt_k[1:13] = {tidn, tidn, tiup, tidn, {8{tiup}}, ex3_b_expo_adj_b[13]};
assign ex3_rsqrt_bsh_b[1:13] = {ex3_b_expo_adj_b[1], ex3_b_expo_adj_b[1:12]}; //negative expo in -> positive
assign ex3_rsqrt_p[1:13] = ex3_rsqrt_k[1:13] ^ ex3_rsqrt_bsh_b[1:13];
assign ex3_rsqrt_g[2:13] = ex3_rsqrt_k[2:13] & ex3_rsqrt_bsh_b[2:13];
assign ex3_rsqrt_t[2:12] = ex3_rsqrt_k[2:12] | ex3_rsqrt_bsh_b[2:12];
assign ex3_rsqrt_g2[13] = ex3_rsqrt_g[13];
assign ex3_rsqrt_g2[12] = ex3_rsqrt_g[12] | (ex3_rsqrt_t[12] & ex3_rsqrt_g[13]);
assign ex3_rsqrt_g2[11] = ex3_rsqrt_g[11] | (ex3_rsqrt_t[11] & ex3_rsqrt_g[12]);
assign ex3_rsqrt_g2[10] = ex3_rsqrt_g[10] | (ex3_rsqrt_t[10] & ex3_rsqrt_g[11]);
assign ex3_rsqrt_g2[9] = ex3_rsqrt_g[9] | (ex3_rsqrt_t[9] & ex3_rsqrt_g[10]);
assign ex3_rsqrt_g2[8] = ex3_rsqrt_g[8] | (ex3_rsqrt_t[8] & ex3_rsqrt_g[9]);
assign ex3_rsqrt_g2[7] = ex3_rsqrt_g[7] | (ex3_rsqrt_t[7] & ex3_rsqrt_g[8]);
assign ex3_rsqrt_g2[6] = ex3_rsqrt_g[6] | (ex3_rsqrt_t[6] & ex3_rsqrt_g[7]);
assign ex3_rsqrt_g2[5] = ex3_rsqrt_g[5] | (ex3_rsqrt_t[5] & ex3_rsqrt_g[6]);
assign ex3_rsqrt_g2[4] = ex3_rsqrt_g[4] | (ex3_rsqrt_t[4] & ex3_rsqrt_g[5]);
assign ex3_rsqrt_g2[3] = ex3_rsqrt_g[3] | (ex3_rsqrt_t[3] & ex3_rsqrt_g[4]);
assign ex3_rsqrt_g2[2] = ex3_rsqrt_g[2] | (ex3_rsqrt_t[2] & ex3_rsqrt_g[3]);
assign ex3_rsqrt_t2[11] = (ex3_rsqrt_t[11] & ex3_rsqrt_t[12]);
assign ex3_rsqrt_t2[10] = (ex3_rsqrt_t[10] & ex3_rsqrt_t[11]);
assign ex3_rsqrt_t2[9] = (ex3_rsqrt_t[9] & ex3_rsqrt_t[10]);
assign ex3_rsqrt_t2[8] = (ex3_rsqrt_t[8] & ex3_rsqrt_t[9]);
assign ex3_rsqrt_t2[7] = (ex3_rsqrt_t[7] & ex3_rsqrt_t[8]);
assign ex3_rsqrt_t2[6] = (ex3_rsqrt_t[6] & ex3_rsqrt_t[7]);
assign ex3_rsqrt_t2[5] = (ex3_rsqrt_t[5] & ex3_rsqrt_t[6]);
assign ex3_rsqrt_t2[4] = (ex3_rsqrt_t[4] & ex3_rsqrt_t[5]);
assign ex3_rsqrt_t2[3] = (ex3_rsqrt_t[3] & ex3_rsqrt_t[4]);
assign ex3_rsqrt_t2[2] = (ex3_rsqrt_t[2] & ex3_rsqrt_t[3]);
assign ex3_rsqrt_g4[13] = ex3_rsqrt_g2[13];
assign ex3_rsqrt_g4[12] = ex3_rsqrt_g2[12];
assign ex3_rsqrt_g4[11] = ex3_rsqrt_g2[11] | (ex3_rsqrt_t2[11] & ex3_rsqrt_g2[13]);
assign ex3_rsqrt_g4[10] = ex3_rsqrt_g2[10] | (ex3_rsqrt_t2[10] & ex3_rsqrt_g2[12]);
assign ex3_rsqrt_g4[9] = ex3_rsqrt_g2[9] | (ex3_rsqrt_t2[9] & ex3_rsqrt_g2[11]);
assign ex3_rsqrt_g4[8] = ex3_rsqrt_g2[8] | (ex3_rsqrt_t2[8] & ex3_rsqrt_g2[10]);
assign ex3_rsqrt_g4[7] = ex3_rsqrt_g2[7] | (ex3_rsqrt_t2[7] & ex3_rsqrt_g2[9]);
assign ex3_rsqrt_g4[6] = ex3_rsqrt_g2[6] | (ex3_rsqrt_t2[6] & ex3_rsqrt_g2[8]);
assign ex3_rsqrt_g4[5] = ex3_rsqrt_g2[5] | (ex3_rsqrt_t2[5] & ex3_rsqrt_g2[7]);
assign ex3_rsqrt_g4[4] = ex3_rsqrt_g2[4] | (ex3_rsqrt_t2[4] & ex3_rsqrt_g2[6]);
assign ex3_rsqrt_g4[3] = ex3_rsqrt_g2[3] | (ex3_rsqrt_t2[3] & ex3_rsqrt_g2[5]);
assign ex3_rsqrt_g4[2] = ex3_rsqrt_g2[2] | (ex3_rsqrt_t2[2] & ex3_rsqrt_g2[4]);
assign ex3_rsqrt_t4[9] = (ex3_rsqrt_t2[9] & ex3_rsqrt_t2[11]);
assign ex3_rsqrt_t4[8] = (ex3_rsqrt_t2[8] & ex3_rsqrt_t2[10]);
assign ex3_rsqrt_t4[7] = (ex3_rsqrt_t2[7] & ex3_rsqrt_t2[9]);
assign ex3_rsqrt_t4[6] = (ex3_rsqrt_t2[6] & ex3_rsqrt_t2[8]);
assign ex3_rsqrt_t4[5] = (ex3_rsqrt_t2[5] & ex3_rsqrt_t2[7]);
assign ex3_rsqrt_t4[4] = (ex3_rsqrt_t2[4] & ex3_rsqrt_t2[6]);
assign ex3_rsqrt_t4[3] = (ex3_rsqrt_t2[3] & ex3_rsqrt_t2[5]);
assign ex3_rsqrt_t4[2] = (ex3_rsqrt_t2[2] & ex3_rsqrt_t2[4]);
assign ex3_rsqrt_g8[13] = ex3_rsqrt_g4[13];
assign ex3_rsqrt_g8[12] = ex3_rsqrt_g4[12];
assign ex3_rsqrt_g8[11] = ex3_rsqrt_g4[11];
assign ex3_rsqrt_g8[10] = ex3_rsqrt_g4[10];
assign ex3_rsqrt_g8[9] = ex3_rsqrt_g4[9] | (ex3_rsqrt_t4[9] & ex3_rsqrt_g4[13]);
assign ex3_rsqrt_g8[8] = ex3_rsqrt_g4[8] | (ex3_rsqrt_t4[8] & ex3_rsqrt_g4[12]);
assign ex3_rsqrt_g8[7] = ex3_rsqrt_g4[7] | (ex3_rsqrt_t4[7] & ex3_rsqrt_g4[11]);
assign ex3_rsqrt_g8[6] = ex3_rsqrt_g4[6] | (ex3_rsqrt_t4[6] & ex3_rsqrt_g4[10]);
assign ex3_rsqrt_g8[5] = ex3_rsqrt_g4[5] | (ex3_rsqrt_t4[5] & ex3_rsqrt_g4[9]);
assign ex3_rsqrt_g8[4] = ex3_rsqrt_g4[4] | (ex3_rsqrt_t4[4] & ex3_rsqrt_g4[8]);
assign ex3_rsqrt_g8[3] = ex3_rsqrt_g4[3] | (ex3_rsqrt_t4[3] & ex3_rsqrt_g4[7]);
assign ex3_rsqrt_g8[2] = ex3_rsqrt_g4[2] | (ex3_rsqrt_t4[2] & ex3_rsqrt_g4[6]);
assign ex3_rsqrt_t8[5] = (ex3_rsqrt_t4[5] & ex3_rsqrt_t4[9]);
assign ex3_rsqrt_t8[4] = (ex3_rsqrt_t4[4] & ex3_rsqrt_t4[8]);
assign ex3_rsqrt_t8[3] = (ex3_rsqrt_t4[3] & ex3_rsqrt_t4[7]);
assign ex3_rsqrt_t8[2] = (ex3_rsqrt_t4[2] & ex3_rsqrt_t4[6]);
assign ex3_rsqrt_c[13] = ex3_rsqrt_g8[13];
assign ex3_rsqrt_c[12] = ex3_rsqrt_g8[12];
assign ex3_rsqrt_c[11] = ex3_rsqrt_g8[11];
assign ex3_rsqrt_c[10] = ex3_rsqrt_g8[10];
assign ex3_rsqrt_c[9] = ex3_rsqrt_g8[9];
assign ex3_rsqrt_c[8] = ex3_rsqrt_g8[8];
assign ex3_rsqrt_c[7] = ex3_rsqrt_g8[7];
assign ex3_rsqrt_c[6] = ex3_rsqrt_g8[6];
assign ex3_rsqrt_c[5] = ex3_rsqrt_g8[5] | (ex3_rsqrt_t8[5] & ex3_rsqrt_g8[13]);
assign ex3_rsqrt_c[4] = ex3_rsqrt_g8[4] | (ex3_rsqrt_t8[4] & ex3_rsqrt_g8[12]);
assign ex3_rsqrt_c[3] = ex3_rsqrt_g8[3] | (ex3_rsqrt_t8[3] & ex3_rsqrt_g8[11]);
assign ex3_rsqrt_c[2] = ex3_rsqrt_g8[2] | (ex3_rsqrt_t8[2] & ex3_rsqrt_g8[10]);
assign ex3_rsqrt_expo[1:12] = ex3_rsqrt_p[1:12] ^ ex3_rsqrt_c[2:13];
assign ex3_rsqrt_expo[13] = ex3_rsqrt_p[13];
////#--------------------------------------------
////# select the result
////#--------------------------------------------
assign ex3_res_expo[1:13] = ({13{f_pic_ex3_est_rsqrt}} & ex3_rsqrt_expo[1:13]) |
({13{f_pic_ex3_est_recip}} & ex3_recip_expo[1:13]);
////#--------------------------------------------
////## --------------------------------------------------
////## DETECT: exponents that require denormalization
//
// rsqrte: -( (e - bias)/2 ) + bias = -e/2 + 3/2 bias
// expo = 7ff inf/nan (2047) <=== special case logic gives result
// expo = 7fe (2046) -(2046 - 1023)/2 + 1023 = -1023/2 + 1023 = -512 + 1023 = 611 : norm
//
//
// recip : 2bias -expo = -(e - bias) + bias
// expo = 7ff inf/nan (2047) <=== special case logic gives result
// expo = 7fe (2046) 2bias -expo = 2046 - 2046 = x000 denorm
// expo = 7fd (2045) 2046 - 2045 = x001 denorm ?
// expo = 7fc (2044) 2046 - 2044 = x002 norm (denorm if adjust)
////## --------------------------------------------------
// for sp underflow, no need to denormalize, but must set the UX flag
// 2046 -1151 = 895 - 1 = 894 <=== INF/NAN in sp range
// 2046 -1150 = 896 - 1 = 895 x380
// 2046 -1149 = 897 - 1 = 896 x380
// 2046 -1148 = 898 - 1 = 897 (denorm if adjust)
//
// 2046 111_1111_11110
// 2045 111_1111_11101
// 2044 111_1111_11100
//
// 1150 100_0111_11110
// 1149 100_0111_11101
// 1148 100_0111_11100
//
// 0512
assign ex3_mid_match_ifsp = (~f_eie_ex3_tbl_expo[4]) & (~f_eie_ex3_tbl_expo[5]) & (~f_eie_ex3_tbl_expo[6]); // 0256
// 0128
// 0512 total = 896
assign ex3_mid_match_ifdp = f_eie_ex3_tbl_expo[4] & f_eie_ex3_tbl_expo[5] & f_eie_ex3_tbl_expo[6]; // 0256
// 0128
// sign
// 2048
// 1024
// 0064
// 0032
// 0016
assign ex3_com_match = (~f_eie_ex3_tbl_expo[1]) & (~f_eie_ex3_tbl_expo[2]) & f_eie_ex3_tbl_expo[3] & f_eie_ex3_tbl_expo[7] & f_eie_ex3_tbl_expo[8] & f_eie_ex3_tbl_expo[9] & f_eie_ex3_tbl_expo[10] & f_eie_ex3_tbl_expo[11]; // 0008
// 0004
assign ex3_match_en_dp = ex3_com_match & f_pic_ex3_sp_b & ex3_mid_match_ifdp;
assign ex3_match_en_sp = ex3_com_match & (~f_pic_ex3_sp_b) & ex3_mid_match_ifsp;
// not f_pic_ex3_ue1 and
assign ex3_recip_2046 = f_pic_ex3_est_recip & f_eie_ex3_tbl_expo[12] & (~f_eie_ex3_tbl_expo[13]); // 0002
// 0001
// not f_pic_ex3_ue1 and
assign ex3_recip_2045 = f_pic_ex3_est_recip & (~f_eie_ex3_tbl_expo[12]) & f_eie_ex3_tbl_expo[13]; // 0002
// 0001
// not f_pic_ex3_ue1 and
assign ex3_recip_2044 = f_pic_ex3_est_recip & (~f_eie_ex3_tbl_expo[12]) & (~f_eie_ex3_tbl_expo[13]); // 0002
// 0001
assign ex3_recip_ue1 = f_pic_ex3_est_recip & f_pic_ex3_ue1;
////##############################################
////# EX4 latches
////##############################################
// name says odd(unbiased) but it is really for even biased.
assign ex3_lu_sh = (f_fmt_ex3_lu_den_recip & f_pic_ex3_est_recip) | (f_fmt_ex3_lu_den_rsqrto & f_pic_ex3_est_rsqrt & (~f_eie_ex3_tbl_expo[13]));
tri_rlmreg_p #(.WIDTH(20)) ex4_expo_lat(
.force_t(force_t), //tidn,
.d_mode(tiup), //d_mode => d_mode ,--tiup,
.delay_lclkr(delay_lclkr[3]), //tidn,
.mpw1_b(mpw1_b[3]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.thold_b(thold_0_b),
.sg(sg_0),
.act(ex3_act),
.scout(ex4_expo_so),
.scin(ex4_expo_si),
.din({ ex3_res_expo[1:13],
ex3_match_en_dp,
ex3_match_en_sp,
ex3_recip_2046,
ex3_recip_2045,
ex3_recip_2044,
ex3_lu_sh,
ex3_recip_ue1}),
//-----------------
.dout({ ex4_res_expo[1:13], //LAT--
ex4_match_en_dp, //LAT--
ex4_match_en_sp, //LAT--
ex4_recip_2046, //LAT--
ex4_recip_2045, //LAT--
ex4_recip_2044, //LAT--
ex4_lu_sh, //LAT--
ex4_recip_ue1}) //LAT--
);
////##############################################
////# EX4 logic
////##############################################
assign f_tbe_ex4_match_en_sp = ex4_match_en_sp; //output
assign f_tbe_ex4_match_en_dp = ex4_match_en_dp; //output
assign f_tbe_ex4_recip_2046 = ex4_recip_2046; //output
assign f_tbe_ex4_recip_2045 = ex4_recip_2045; //output
assign f_tbe_ex4_recip_2044 = ex4_recip_2044; //output
assign f_tbe_ex4_lu_sh = ex4_lu_sh; //output--
assign f_tbe_ex4_recip_ue1 = ex4_recip_ue1; //output--
assign ex4_recip_2046_dp = ex4_recip_2046 & ex4_match_en_dp & (~ex4_recip_ue1); // for shifting
assign ex4_recip_2045_dp = ex4_recip_2045 & ex4_match_en_dp & (~ex4_recip_ue1); // for shifting
assign ex4_recip_2044_dp = ex4_recip_2044 & ex4_match_en_dp & (~ex4_recip_ue1); // for shifting
assign ex4_force_expo_den = ex4_recip_2046_dp | ex4_recip_2045_dp; // do not force DEN for ue1 mode
// 2044 conditionally backs into denorm depending on lu_sh ... decrement
assign ex4_decr_expo = (ex4_lu_sh & ex4_recip_ue1) | (ex4_lu_sh & (~ex4_recip_ue1) & (~ex4_recip_2046_dp) & (~ex4_recip_2045_dp) & (~ex4_recip_2044_dp)); // for denormalization / normalization
// decrement is like add 11111....11111 (lsb does not change
// t = 1
// g = d
assign ex4_res_expo_b[1:13] = (~ex4_res_expo[1:13]);
assign ex4_res_expo_g2_b[13] = (~(ex4_res_expo[13]));
assign ex4_res_expo_g2_b[12] = (~(ex4_res_expo[12] | ex4_res_expo[13]));
assign ex4_res_expo_g2_b[11] = (~(ex4_res_expo[11] | ex4_res_expo[12]));
assign ex4_res_expo_g2_b[10] = (~(ex4_res_expo[10] | ex4_res_expo[11]));
assign ex4_res_expo_g2_b[9] = (~(ex4_res_expo[9] | ex4_res_expo[10]));
assign ex4_res_expo_g2_b[8] = (~(ex4_res_expo[8] | ex4_res_expo[9]));
assign ex4_res_expo_g2_b[7] = (~(ex4_res_expo[7] | ex4_res_expo[8]));
assign ex4_res_expo_g2_b[6] = (~(ex4_res_expo[6] | ex4_res_expo[7]));
assign ex4_res_expo_g2_b[5] = (~(ex4_res_expo[5] | ex4_res_expo[6]));
assign ex4_res_expo_g2_b[4] = (~(ex4_res_expo[4] | ex4_res_expo[5]));
assign ex4_res_expo_g2_b[3] = (~(ex4_res_expo[3] | ex4_res_expo[4]));
assign ex4_res_expo_g2_b[2] = (~(ex4_res_expo[2] | ex4_res_expo[3]));
assign ex4_res_expo_g4[13] = (~(ex4_res_expo_g2_b[13]));
assign ex4_res_expo_g4[12] = (~(ex4_res_expo_g2_b[12]));
assign ex4_res_expo_g4[11] = (~(ex4_res_expo_g2_b[11] & ex4_res_expo_g2_b[13]));
assign ex4_res_expo_g4[10] = (~(ex4_res_expo_g2_b[10] & ex4_res_expo_g2_b[12]));
assign ex4_res_expo_g4[9] = (~(ex4_res_expo_g2_b[9] & ex4_res_expo_g2_b[11]));
assign ex4_res_expo_g4[8] = (~(ex4_res_expo_g2_b[8] & ex4_res_expo_g2_b[10]));
assign ex4_res_expo_g4[7] = (~(ex4_res_expo_g2_b[7] & ex4_res_expo_g2_b[9]));
assign ex4_res_expo_g4[6] = (~(ex4_res_expo_g2_b[6] & ex4_res_expo_g2_b[8]));
assign ex4_res_expo_g4[5] = (~(ex4_res_expo_g2_b[5] & ex4_res_expo_g2_b[7]));
assign ex4_res_expo_g4[4] = (~(ex4_res_expo_g2_b[4] & ex4_res_expo_g2_b[6]));
assign ex4_res_expo_g4[3] = (~(ex4_res_expo_g2_b[3] & ex4_res_expo_g2_b[5]));
assign ex4_res_expo_g4[2] = (~(ex4_res_expo_g2_b[2] & ex4_res_expo_g2_b[4]));
assign ex4_res_expo_g8_b[13] = (~(ex4_res_expo_g4[13]));
assign ex4_res_expo_g8_b[12] = (~(ex4_res_expo_g4[12]));
assign ex4_res_expo_g8_b[11] = (~(ex4_res_expo_g4[11]));
assign ex4_res_expo_g8_b[10] = (~(ex4_res_expo_g4[10]));
assign ex4_res_expo_g8_b[9] = (~(ex4_res_expo_g4[9] | ex4_res_expo_g4[13]));
assign ex4_res_expo_g8_b[8] = (~(ex4_res_expo_g4[8] | ex4_res_expo_g4[12]));
assign ex4_res_expo_g8_b[7] = (~(ex4_res_expo_g4[7] | ex4_res_expo_g4[11]));
assign ex4_res_expo_g8_b[6] = (~(ex4_res_expo_g4[6] | ex4_res_expo_g4[10]));
assign ex4_res_expo_g8_b[5] = (~(ex4_res_expo_g4[5] | ex4_res_expo_g4[9]));
assign ex4_res_expo_g8_b[4] = (~(ex4_res_expo_g4[4] | ex4_res_expo_g4[8]));
assign ex4_res_expo_g8_b[3] = (~(ex4_res_expo_g4[3] | ex4_res_expo_g4[7]));
assign ex4_res_expo_g8_b[2] = (~(ex4_res_expo_g4[2] | ex4_res_expo_g4[6]));
assign ex4_res_expo_c[13] = (~(ex4_res_expo_g8_b[13]));
assign ex4_res_expo_c[12] = (~(ex4_res_expo_g8_b[12]));
assign ex4_res_expo_c[11] = (~(ex4_res_expo_g8_b[11]));
assign ex4_res_expo_c[10] = (~(ex4_res_expo_g8_b[10]));
assign ex4_res_expo_c[9] = (~(ex4_res_expo_g8_b[9]));
assign ex4_res_expo_c[8] = (~(ex4_res_expo_g8_b[8]));
assign ex4_res_expo_c[7] = (~(ex4_res_expo_g8_b[7]));
assign ex4_res_expo_c[6] = (~(ex4_res_expo_g8_b[6]));
assign ex4_res_expo_c[5] = (~(ex4_res_expo_g8_b[5] & ex4_res_expo_g8_b[13]));
assign ex4_res_expo_c[4] = (~(ex4_res_expo_g8_b[4] & ex4_res_expo_g8_b[12]));
assign ex4_res_expo_c[3] = (~(ex4_res_expo_g8_b[3] & ex4_res_expo_g8_b[11]));
assign ex4_res_expo_c[2] = (~(ex4_res_expo_g8_b[2] & ex4_res_expo_g8_b[10]));
assign ex4_res_decr[1:12] = ex4_res_expo_b[1:12] ^ ex4_res_expo_c[2:13];
assign ex4_res_decr[13] = ex4_res_expo_b[13];
assign f_tbe_ex4_res_expo[1] = (ex4_res_expo[1] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[1] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[2] = (ex4_res_expo[2] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[2] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[3] = (ex4_res_expo[3] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[3] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[4] = (ex4_res_expo[4] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[4] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[5] = (ex4_res_expo[5] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[5] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[6] = (ex4_res_expo[6] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[6] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[7] = (ex4_res_expo[7] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[7] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[8] = (ex4_res_expo[8] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[8] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[9] = (ex4_res_expo[9] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[9] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[10] = (ex4_res_expo[10] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[10] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[11] = (ex4_res_expo[11] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[11] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[12] = (ex4_res_expo[12] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[12] & ex4_decr_expo); //output
assign f_tbe_ex4_res_expo[13] = (ex4_res_expo[13] & (~ex4_decr_expo)) | (ex4_res_decr[13] & ex4_decr_expo) | (ex4_force_expo_den); //output
// (not ex4_res_expo(1) and ex4_res_expo(3) ) or
assign f_tbe_ex4_may_ov = ((~ex4_res_expo[1]) & ex4_res_expo[2]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[4]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[5]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[6]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[7]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[8] & ex4_res_expo[9]); // before the den adjustments on purpose
////############################################
////# scan
////############################################
assign ex4_expo_si[0:19] = {ex4_expo_so[1:19], si};
assign act_si[0:4] = {act_so[1:4], ex4_expo_so[0]};
assign so = act_so[0];
endmodule |
module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
`include "tri_a2o.vh"
inout vdd,
inout gnd,
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk
input [0:`NCLK_WIDTH-1] nclk,
input rp_rv_ccflush_dc,
input rp_rv_func_sl_thold_3,
input rp_rv_gptr_sl_thold_3,
input rp_rv_sg_3,
input rp_rv_fce_3,
input an_ac_scan_diag_dc,
input an_ac_scan_dis_dc_b,
input d_mode,
output func_sl_thold_1,
output fce_1,
output sg_1,
output clkoff_dc_b,
output act_dis,
output [0:9] delay_lclkr_dc,
output [0:9] mpw1_dc_b,
output mpw2_dc_b,
input gptr_scan_in,
output gptr_scan_out,
input scan_in,
output scan_out,
//------------------------------------------------------------------------------------------------------------
// Debug and Perf
//------------------------------------------------------------------------------------------------------------
input [0:8*`THREADS-1] fx0_rvs_perf_bus,
input [0:31] fx0_rvs_dbg_bus,
input [0:8*`THREADS-1] fx1_rvs_perf_bus,
input [0:31] fx1_rvs_dbg_bus,
input [0:8*`THREADS-1] lq_rvs_perf_bus,
input [0:31] lq_rvs_dbg_bus,
input [0:8*`THREADS-1] axu0_rvs_perf_bus,
input [0:31] axu0_rvs_dbg_bus,
input [0:`THREADS-1] spr_msr_gs,
input [0:`THREADS-1] spr_msr_pr,
input pc_rv_trace_bus_enable,
input [0:10] pc_rv_debug_mux_ctrls,
input pc_rv_event_bus_enable,
input [0:2] pc_rv_event_count_mode,
input [0:39] pc_rv_event_mux_ctrls,
input [0:4*`THREADS-1] rv_event_bus_in,
output [0:4*`THREADS-1] rv_event_bus_out,
output [0:31] debug_bus_out,
input [0:31] debug_bus_in,
input [0:3] coretrace_ctrls_in,
output [0:3] coretrace_ctrls_out
);
wire func_sl_thold_2;
wire gptr_sl_thold_2;
wire sg_2;
wire fce_2;
wire gptr_sl_thold_1;
wire func_sl_thold_1_int;
wire sg_1_int;
wire gptr_sl_thold_0;
wire func_sl_thold_0;
wire force_t;
wire sg_0;
wire gptr_sio;
wire [0:9] prv_delay_lclkr_dc;
wire [0:9] prv_mpw1_dc_b;
wire prv_mpw2_dc_b;
wire prv_act_dis;
wire prv_clkoff_dc_b;
// Debug and Perf
wire trc_act;
wire evt_act;
wire delay_lclkr;
wire mpw1_b;
wire mpw2_b;
wire [0:31] debug_bus_mux;
wire [0:3] coretrace_ctrls_mux;
wire [0:10] debug_mux_ctrls;
wire [0:39] event_mux_ctrls;
wire [0:2] event_count_mode;
wire [0:`THREADS-1] spr_msr_gs_q;
wire [0:`THREADS-1] spr_msr_pr_q;
wire [0:`THREADS-1] event_en;
wire [0:32*`THREADS-1] event_bus_in;
wire [0:4*`THREADS-1] event_bus_d;
wire [0:4*`THREADS-1] event_bus_q;
wire [0:31] dbg_group0;
wire [0:31] dbg_group1;
wire [0:31] dbg_group2;
wire [0:31] dbg_group3;
// Unused Signals
(* analysis_not_referenced="TRUE" *)
wire act0_dis_dc;
(* analysis_not_referenced="TRUE" *)
wire d0_mode_dc;
(* analysis_not_referenced="TRUE" *)
wire clkoff1_dc_b;
(* analysis_not_referenced="TRUE" *)
wire act1_dis_dc;
(* analysis_not_referenced="TRUE" *)
wire d1_mode_dc;
(* analysis_not_referenced="TRUE" *)
wire nc_mpw2_dc_b;
(* analysis_not_referenced="TRUE" *)
wire unused;
//------------------------------------------------------------------------------------------------------------
// Scan Chains
//------------------------------------------------------------------------------------------------------------
parameter debug_bus_offset = 0 + 0;
parameter debug_mux_offset = debug_bus_offset + 32;
parameter event_bus_offset = debug_mux_offset + 11;
parameter event_count_offset = event_bus_offset + 4*`THREADS;
parameter spr_msr_gs_offset = event_count_offset + 3;
parameter spr_msr_pr_offset = spr_msr_gs_offset + `THREADS;
parameter event_mux_ctrls_offset = spr_msr_pr_offset + `THREADS;
parameter coretrace_ctrls_offset = event_mux_ctrls_offset + 40;
parameter scan_right = coretrace_ctrls_offset + 4;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
assign unused = an_ac_scan_dis_dc_b ;
tri_plat #(.WIDTH(4))
perv_3to2_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(rp_rv_ccflush_dc),
.din({rp_rv_func_sl_thold_3, rp_rv_gptr_sl_thold_3, rp_rv_sg_3, rp_rv_fce_3}),
.q({func_sl_thold_2, gptr_sl_thold_2, sg_2, fce_2})
);
tri_plat #(.WIDTH(4))
perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(rp_rv_ccflush_dc),
.din({func_sl_thold_2, gptr_sl_thold_2, sg_2, fce_2}),
.q({func_sl_thold_1_int, gptr_sl_thold_1, sg_1_int, fce_1})
);
assign func_sl_thold_1 = func_sl_thold_1_int;
assign sg_1 = sg_1_int;
tri_plat #(.WIDTH(3))
perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(rp_rv_ccflush_dc),
.din({gptr_sl_thold_1 , func_sl_thold_1_int, sg_1_int}),
.q({gptr_sl_thold_0, func_sl_thold_0, sg_0})
);
tri_lcbor
perv_lcbor(
.clkoff_b(prv_clkoff_dc_b),
.thold(func_sl_thold_0),
.sg(sg_0),
.act_dis(prv_act_dis),
.force_t(force_t),
.thold_b(func_sl_thold_0_b)
);
// Pipeline mapping of mpw1_b and delay_lclkr
// RF0
// RF1 0
// EX1 1
// EX2 2
// EX3 3
// EX4 4
// EX5 5
// EX6 6
// EX7 7
tri_lcbcntl_mac
perv_lcbctrl0(
.vdd(vdd),
.gnd(gnd),
.sg(sg_0),
.nclk(nclk),
.scan_in(gptr_scan_in),
.scan_diag_dc(an_ac_scan_diag_dc),
.thold(gptr_sl_thold_0),
.clkoff_dc_b(prv_clkoff_dc_b),
.delay_lclkr_dc(prv_delay_lclkr_dc[0:4]),
.act_dis_dc(act0_dis_dc),
.d_mode_dc(d0_mode_dc),
.mpw1_dc_b(prv_mpw1_dc_b[0:4]),
.mpw2_dc_b(prv_mpw2_dc_b),
.scan_out(gptr_sio)
);
tri_lcbcntl_mac
perv_lcbctrl1(
.vdd(vdd),
.gnd(gnd),
.sg(sg_0),
.nclk(nclk),
.scan_in(gptr_sio),
.scan_diag_dc(an_ac_scan_diag_dc),
.thold(gptr_sl_thold_0),
.clkoff_dc_b(clkoff1_dc_b),
.delay_lclkr_dc(prv_delay_lclkr_dc[5:9]),
.act_dis_dc(act1_dis_dc),
.d_mode_dc(d1_mode_dc),
.mpw1_dc_b(prv_mpw1_dc_b[5:9]),
.mpw2_dc_b(nc_mpw2_dc_b),
.scan_out(gptr_scan_out)
);
//Outputs
assign delay_lclkr_dc[0:9] = prv_delay_lclkr_dc[0:9];
assign mpw1_dc_b[0:9] = prv_mpw1_dc_b[0:9];
assign mpw2_dc_b = prv_mpw2_dc_b;
//never disable act pins, they are used functionally
assign prv_act_dis = 1'b0;
assign act_dis = prv_act_dis;
assign clkoff_dc_b = prv_clkoff_dc_b;
//------------------------------------------------------------------------------------------------------------
// Perf bus
//------------------------------------------------------------------------------------------------------------
assign event_en = ( spr_msr_pr_q & {`THREADS{event_count_mode[0]}}) | //-- User
((~spr_msr_pr_q) & spr_msr_gs_q & {`THREADS{event_count_mode[1]}}) | //-- Guest Supervisor
((~spr_msr_pr_q) & (~spr_msr_gs_q) & {`THREADS{event_count_mode[2]}}); //-- Hypervisor
assign event_bus_in[ 0: 7] = fx0_rvs_perf_bus[0:7] & {8{event_en[0]}};
assign event_bus_in[ 8:15] = fx1_rvs_perf_bus[0:7] & {8{event_en[0]}};
assign event_bus_in[16:23] = lq_rvs_perf_bus[0:7] & {8{event_en[0]}};
assign event_bus_in[24:31] = axu0_rvs_perf_bus[0:7] & {8{event_en[0]}};
tri_event_mux1t #(.EVENTS_IN(32), .EVENTS_OUT(4))
event_mux0(
.vd(vdd),
.gd(gnd),
.event_bus_in(rv_event_bus_in[0:3]),
.event_bus_out(event_bus_d[0:3]),
.unit_events_in(event_bus_in[1:31]),
.select_bits(event_mux_ctrls[0:19])
);
`ifndef THREADS1
assign event_bus_in[32:39] = fx0_rvs_perf_bus[8:15] & {8{event_en[1]}};
assign event_bus_in[40:47] = fx1_rvs_perf_bus[8:15] & {8{event_en[1]}};
assign event_bus_in[48:55] = lq_rvs_perf_bus[8:15] & {8{event_en[1]}};
assign event_bus_in[56:63] = axu0_rvs_perf_bus[8:15] & {8{event_en[1]}};
tri_event_mux1t #(.EVENTS_IN(32), .EVENTS_OUT(4))
event_mux1(
.vd(vdd),
.gd(gnd),
.event_bus_in(rv_event_bus_in[4:7]),
.event_bus_out(event_bus_d[4:7]),
.unit_events_in(event_bus_in[32:63]),
.select_bits(event_mux_ctrls[20:39])
);
`endif
assign rv_event_bus_out = event_bus_q;
//------------------------------------------------------------------------------------------------------------
// Debug bus
//------------------------------------------------------------------------------------------------------------
assign dbg_group0 = fx0_rvs_dbg_bus[0:31] ;
assign dbg_group1 = fx1_rvs_dbg_bus[0:31] ;
assign dbg_group2 = lq_rvs_dbg_bus[0:31] ;
assign dbg_group3 = axu0_rvs_dbg_bus[0:31] ;
tri_debug_mux4 #(.DBG_WIDTH(32))
dbg_mux(
.select_bits(debug_mux_ctrls),
.trace_data_in(debug_bus_in),
.dbg_group0(dbg_group0),
.dbg_group1(dbg_group1),
.dbg_group2(dbg_group2),
.dbg_group3(dbg_group3),
.trace_data_out(debug_bus_mux),
.coretrace_ctrls_in(coretrace_ctrls_in),
.coretrace_ctrls_out(coretrace_ctrls_mux)
);
//------------------------------------------------------------------------------------------------------------
// Latches
//------------------------------------------------------------------------------------------------------------
assign trc_act = pc_rv_trace_bus_enable;
assign evt_act = pc_rv_event_bus_enable;
assign delay_lclkr = prv_delay_lclkr_dc[0];
assign mpw1_b = prv_mpw1_dc_b[0];
assign mpw2_b = prv_mpw2_dc_b;
tri_rlmreg_p #(.WIDTH(32), .INIT(0))
debug_bus_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(trc_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[debug_bus_offset:debug_bus_offset + 32 - 1]),
.scout(sov[debug_bus_offset:debug_bus_offset + 32 - 1]),
.din(debug_bus_mux),
.dout(debug_bus_out)
);
tri_rlmreg_p #(.WIDTH(11), .INIT(0))
debug_mux_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(trc_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[debug_mux_offset:debug_mux_offset + 11 - 1]),
.scout(sov[debug_mux_offset:debug_mux_offset + 11 - 1]),
.din(pc_rv_debug_mux_ctrls),
.dout(debug_mux_ctrls)
);
tri_rlmreg_p #(.WIDTH(4*`THREADS), .INIT(0))
event_bus_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(evt_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[event_bus_offset:event_bus_offset + 4*`THREADS - 1]),
.scout(sov[event_bus_offset:event_bus_offset + 4*`THREADS - 1]),
.din(event_bus_d),
.dout(event_bus_q)
);
tri_rlmreg_p #(.WIDTH(3), .INIT(0))
event_count_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(evt_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[event_count_offset:event_count_offset + 3 - 1]),
.scout(sov[event_count_offset:event_count_offset + 3 - 1]),
.din(pc_rv_event_count_mode),
.dout(event_count_mode)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0))
spr_msr_gs_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(evt_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]),
.scout(sov[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]),
.din(spr_msr_gs),
.dout(spr_msr_gs_q)
);
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0))
spr_msr_pr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(evt_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]),
.scout(sov[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]),
.din(spr_msr_pr),
.dout(spr_msr_pr_q)
);
tri_rlmreg_p #(.WIDTH(40), .INIT(0))
event_mux_ctrls_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(evt_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[event_mux_ctrls_offset:event_mux_ctrls_offset + 40 - 1]),
.scout(sov[event_mux_ctrls_offset:event_mux_ctrls_offset + 40 - 1]),
.din(pc_rv_event_mux_ctrls),
.dout(event_mux_ctrls)
);
tri_rlmreg_p #(.WIDTH(4), .INIT(0))
core_trace_ctrls_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(trc_act),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[coretrace_ctrls_offset:coretrace_ctrls_offset + 4 - 1]),
.scout(sov[coretrace_ctrls_offset:coretrace_ctrls_offset + 4 - 1]),
.din(coretrace_ctrls_mux),
.dout(coretrace_ctrls_out)
);
//------------------------------------------------------------------------------------------------------------
// Scan Connections
//------------------------------------------------------------------------------------------------------------
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
assign scan_out = sov[0];
endmodule |
module iuq_dec_top(
inout vdd,
inout gnd,
input [0:`NCLK_WIDTH-1] nclk,
input pc_iu_sg_2,
input pc_iu_func_sl_thold_2,
input clkoff_b,
input act_dis,
input tc_ac_ccflush_dc,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input [0:3] scan_in,
output [0:3] scan_out,
input xu_iu_epcr_dgtmi,
input xu_iu_msrp_uclep,
input xu_iu_msr_pr,
input xu_iu_msr_gs,
input xu_iu_msr_ucle,
input xu_iu_ccr2_ucode_dis,
input [0:31] spr_dec_mask,
input [0:31] spr_dec_match,
input [0:7] iu_au_config_iucr,
input mm_iu_tlbwe_binv,
input cp_iu_iu4_flush,
input uc_ib_iu3_flush_all,
input br_iu_redirect,
input ib_id_iu4_0_valid,
input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_0_ifar,
input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_0_bta,
input [0:69] ib_id_iu4_0_instr,
input [0:2] ib_id_iu4_0_ucode,
input [0:3] ib_id_iu4_0_ucode_ext,
input ib_id_iu4_0_isram,
input [0:31] ib_id_iu4_0_fuse_data,
input ib_id_iu4_0_fuse_val,
input ib_id_iu4_1_valid,
input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_1_ifar,
input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_1_bta,
input [0:69] ib_id_iu4_1_instr,
input [0:2] ib_id_iu4_1_ucode,
input [0:3] ib_id_iu4_1_ucode_ext,
input ib_id_iu4_1_isram,
input [0:31] ib_id_iu4_1_fuse_data,
input ib_id_iu4_1_fuse_val,
output id_ib_iu4_stall,
// Decoded instruction to send to rename
output fdec_frn_iu5_i0_vld,
output [0:2] fdec_frn_iu5_i0_ucode,
output fdec_frn_iu5_i0_2ucode,
output fdec_frn_iu5_i0_fuse_nop,
output fdec_frn_iu5_i0_rte_lq,
output fdec_frn_iu5_i0_rte_sq,
output fdec_frn_iu5_i0_rte_fx0,
output fdec_frn_iu5_i0_rte_fx1,
output fdec_frn_iu5_i0_rte_axu0,
output fdec_frn_iu5_i0_rte_axu1,
output fdec_frn_iu5_i0_valop,
output fdec_frn_iu5_i0_ord,
output fdec_frn_iu5_i0_cord,
output [0:2] fdec_frn_iu5_i0_error,
output [0:19] fdec_frn_iu5_i0_fusion,
output fdec_frn_iu5_i0_spec,
output fdec_frn_iu5_i0_type_fp,
output fdec_frn_iu5_i0_type_ap,
output fdec_frn_iu5_i0_type_spv,
output fdec_frn_iu5_i0_type_st,
output fdec_frn_iu5_i0_async_block,
output fdec_frn_iu5_i0_np1_flush,
output fdec_frn_iu5_i0_core_block,
output fdec_frn_iu5_i0_isram,
output fdec_frn_iu5_i0_isload,
output fdec_frn_iu5_i0_isstore,
output [0:31] fdec_frn_iu5_i0_instr,
output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_ifar,
output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_bta,
output [0:3] fdec_frn_iu5_i0_ilat,
output fdec_frn_iu5_i0_t1_v,
output [0:2] fdec_frn_iu5_i0_t1_t,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t1_a,
output fdec_frn_iu5_i0_t2_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t2_a,
output [0:2] fdec_frn_iu5_i0_t2_t,
output fdec_frn_iu5_i0_t3_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t3_a,
output [0:2] fdec_frn_iu5_i0_t3_t,
output fdec_frn_iu5_i0_s1_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s1_a,
output [0:2] fdec_frn_iu5_i0_s1_t,
output fdec_frn_iu5_i0_s2_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s2_a,
output [0:2] fdec_frn_iu5_i0_s2_t,
output fdec_frn_iu5_i0_s3_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s3_a,
output [0:2] fdec_frn_iu5_i0_s3_t,
output fdec_frn_iu5_i0_br_pred,
output fdec_frn_iu5_i0_bh_update,
output [0:1] fdec_frn_iu5_i0_bh0_hist,
output [0:1] fdec_frn_iu5_i0_bh1_hist,
output [0:1] fdec_frn_iu5_i0_bh2_hist,
output [0:17] fdec_frn_iu5_i0_gshare,
output [0:2] fdec_frn_iu5_i0_ls_ptr,
output fdec_frn_iu5_i0_match,
output fdec_frn_iu5_i0_btb_entry,
output [0:1] fdec_frn_iu5_i0_btb_hist,
output fdec_frn_iu5_i0_bta_val,
output fdec_frn_iu5_i1_vld,
output [0:2] fdec_frn_iu5_i1_ucode,
output fdec_frn_iu5_i1_fuse_nop,
output fdec_frn_iu5_i1_rte_lq,
output fdec_frn_iu5_i1_rte_sq,
output fdec_frn_iu5_i1_rte_fx0,
output fdec_frn_iu5_i1_rte_fx1,
output fdec_frn_iu5_i1_rte_axu0,
output fdec_frn_iu5_i1_rte_axu1,
output fdec_frn_iu5_i1_valop,
output fdec_frn_iu5_i1_ord,
output fdec_frn_iu5_i1_cord,
output [0:2] fdec_frn_iu5_i1_error,
output [0:19] fdec_frn_iu5_i1_fusion,
output fdec_frn_iu5_i1_spec,
output fdec_frn_iu5_i1_type_fp,
output fdec_frn_iu5_i1_type_ap,
output fdec_frn_iu5_i1_type_spv,
output fdec_frn_iu5_i1_type_st,
output fdec_frn_iu5_i1_async_block,
output fdec_frn_iu5_i1_np1_flush,
output fdec_frn_iu5_i1_core_block,
output fdec_frn_iu5_i1_isram,
output fdec_frn_iu5_i1_isload,
output fdec_frn_iu5_i1_isstore,
output [0:31] fdec_frn_iu5_i1_instr,
output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_ifar,
output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_bta,
output [0:3] fdec_frn_iu5_i1_ilat,
output fdec_frn_iu5_i1_t1_v,
output [0:2] fdec_frn_iu5_i1_t1_t,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t1_a,
output fdec_frn_iu5_i1_t2_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t2_a,
output [0:2] fdec_frn_iu5_i1_t2_t,
output fdec_frn_iu5_i1_t3_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t3_a,
output [0:2] fdec_frn_iu5_i1_t3_t,
output fdec_frn_iu5_i1_s1_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s1_a,
output [0:2] fdec_frn_iu5_i1_s1_t,
output fdec_frn_iu5_i1_s2_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s2_a,
output [0:2] fdec_frn_iu5_i1_s2_t,
output fdec_frn_iu5_i1_s3_v,
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s3_a,
output [0:2] fdec_frn_iu5_i1_s3_t,
output fdec_frn_iu5_i1_br_pred,
output fdec_frn_iu5_i1_bh_update,
output [0:1] fdec_frn_iu5_i1_bh0_hist,
output [0:1] fdec_frn_iu5_i1_bh1_hist,
output [0:1] fdec_frn_iu5_i1_bh2_hist,
output [0:17] fdec_frn_iu5_i1_gshare,
output [0:2] fdec_frn_iu5_i1_ls_ptr,
output fdec_frn_iu5_i1_match,
output fdec_frn_iu5_i1_btb_entry,
output [0:1] fdec_frn_iu5_i1_btb_hist,
output fdec_frn_iu5_i1_bta_val,
input frn_fdec_iu5_stall
);
//AXU Interface
wire au_iu_iu4_i0_i_dec_b;
wire [0:2] au_iu_iu4_i0_ucode;
wire au_iu_iu4_i0_t1_v;
wire [0:2] au_iu_iu4_i0_t1_t;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_t1_a;
wire au_iu_iu4_i0_t2_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_t2_a;
wire [0:2] au_iu_iu4_i0_t2_t;
wire au_iu_iu4_i0_t3_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_t3_a;
wire [0:2] au_iu_iu4_i0_t3_t;
wire au_iu_iu4_i0_s1_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_s1_a;
wire [0:2] au_iu_iu4_i0_s1_t;
wire au_iu_iu4_i0_s2_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_s2_a;
wire [0:2] au_iu_iu4_i0_s2_t;
wire au_iu_iu4_i0_s3_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_s3_a;
wire [0:2] au_iu_iu4_i0_s3_t;
wire [0:2] au_iu_iu4_i0_ilat;
wire au_iu_iu4_i0_ord;
wire au_iu_iu4_i0_cord;
wire au_iu_iu4_i0_spec;
wire au_iu_iu4_i0_type_fp;
wire au_iu_iu4_i0_type_ap;
wire au_iu_iu4_i0_type_spv;
wire au_iu_iu4_i0_type_st;
wire au_iu_iu4_i0_async_block;
wire au_iu_iu4_i0_isload;
wire au_iu_iu4_i0_isstore;
wire au_iu_iu4_i0_rte_lq;
wire au_iu_iu4_i0_rte_sq;
wire au_iu_iu4_i0_rte_axu0;
wire au_iu_iu4_i0_rte_axu1;
wire au_iu_iu4_i0_no_ram;
wire au_iu_iu4_i1_i_dec_b; // decoded a valid FU instruction (inverted) 0509
wire [0:2] au_iu_iu4_i1_ucode;
wire au_iu_iu4_i1_t1_v;
wire [0:2] au_iu_iu4_i1_t1_t;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_t1_a;
wire au_iu_iu4_i1_t2_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_t2_a;
wire [0:2] au_iu_iu4_i1_t2_t;
wire au_iu_iu4_i1_t3_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_t3_a;
wire [0:2] au_iu_iu4_i1_t3_t;
wire au_iu_iu4_i1_s1_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_s1_a;
wire [0:2] au_iu_iu4_i1_s1_t;
wire au_iu_iu4_i1_s2_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_s2_a;
wire [0:2] au_iu_iu4_i1_s2_t;
wire au_iu_iu4_i1_s3_v;
wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_s3_a;
wire [0:2] au_iu_iu4_i1_s3_t;
wire [0:2] au_iu_iu4_i1_ilat;
wire au_iu_iu4_i1_ord;
wire au_iu_iu4_i1_cord;
wire au_iu_iu4_i1_spec;
wire au_iu_iu4_i1_type_fp;
wire au_iu_iu4_i1_type_ap;
wire au_iu_iu4_i1_type_spv;
wire au_iu_iu4_i1_type_st;
wire au_iu_iu4_i1_async_block;
wire au_iu_iu4_i1_isload;
wire au_iu_iu4_i1_isstore;
wire au_iu_iu4_i1_rte_lq;
wire au_iu_iu4_i1_rte_sq;
wire au_iu_iu4_i1_rte_axu0;
wire au_iu_iu4_i1_rte_axu1;
wire au_iu_iu4_i1_no_ram;
wire fdec_frn_iu5_i0_vld_int;
wire iu5_stall;
assign iu5_stall = frn_fdec_iu5_stall & fdec_frn_iu5_i0_vld_int;
assign id_ib_iu4_stall = iu5_stall;
assign fdec_frn_iu5_i0_vld = fdec_frn_iu5_i0_vld_int;
iuq_idec fx_dec0(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.clkoff_b(clkoff_b),
.act_dis(act_dis),
.tc_ac_ccflush_dc(tc_ac_ccflush_dc),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scan_in(scan_in[0]),
.scan_out(scan_out[0]),
.xu_iu_epcr_dgtmi(xu_iu_epcr_dgtmi),
.xu_iu_msrp_uclep(xu_iu_msrp_uclep),
.xu_iu_msr_pr(xu_iu_msr_pr),
.xu_iu_msr_gs(xu_iu_msr_gs),
.xu_iu_msr_ucle(xu_iu_msr_ucle),
.xu_iu_ccr2_ucode_dis(xu_iu_ccr2_ucode_dis),
.mm_iu_tlbwe_binv(mm_iu_tlbwe_binv),
.spr_dec_mask(spr_dec_mask),
.spr_dec_match(spr_dec_match),
.cp_iu_iu4_flush(cp_iu_iu4_flush),
.uc_ib_iu3_flush_all(uc_ib_iu3_flush_all),
.br_iu_redirect(br_iu_redirect),
.ib_id_iu4_valid(ib_id_iu4_0_valid),
.ib_id_iu4_ifar(ib_id_iu4_0_ifar),
.ib_id_iu4_bta(ib_id_iu4_0_bta),
.ib_id_iu4_instr(ib_id_iu4_0_instr),
.ib_id_iu4_ucode(ib_id_iu4_0_ucode),
.ib_id_iu4_ucode_ext(ib_id_iu4_0_ucode_ext),
.ib_id_iu4_isram(ib_id_iu4_0_isram),
.ib_id_iu4_fuse_data(ib_id_iu4_0_fuse_data),
.ib_id_iu4_fuse_val(ib_id_iu4_0_fuse_val),
//AXU Interface
.au_iu_iu4_i_dec_b(au_iu_iu4_i0_i_dec_b),
.au_iu_iu4_ucode(au_iu_iu4_i0_ucode),
.au_iu_iu4_t1_v(au_iu_iu4_i0_t1_v),
.au_iu_iu4_t1_t(au_iu_iu4_i0_t1_t),
.au_iu_iu4_t1_a(au_iu_iu4_i0_t1_a),
.au_iu_iu4_t2_v(au_iu_iu4_i0_t2_v),
.au_iu_iu4_t2_a(au_iu_iu4_i0_t2_a),
.au_iu_iu4_t2_t(au_iu_iu4_i0_t2_t),
.au_iu_iu4_t3_v(au_iu_iu4_i0_t3_v),
.au_iu_iu4_t3_a(au_iu_iu4_i0_t3_a),
.au_iu_iu4_t3_t(au_iu_iu4_i0_t3_t),
.au_iu_iu4_s1_v(au_iu_iu4_i0_s1_v),
.au_iu_iu4_s1_a(au_iu_iu4_i0_s1_a),
.au_iu_iu4_s1_t(au_iu_iu4_i0_s1_t),
.au_iu_iu4_s2_v(au_iu_iu4_i0_s2_v),
.au_iu_iu4_s2_a(au_iu_iu4_i0_s2_a),
.au_iu_iu4_s2_t(au_iu_iu4_i0_s2_t),
.au_iu_iu4_s3_v(au_iu_iu4_i0_s3_v),
.au_iu_iu4_s3_a(au_iu_iu4_i0_s3_a),
.au_iu_iu4_s3_t(au_iu_iu4_i0_s3_t),
.au_iu_iu4_ilat(au_iu_iu4_i0_ilat),
.au_iu_iu4_ord(au_iu_iu4_i0_ord),
.au_iu_iu4_cord(au_iu_iu4_i0_cord),
.au_iu_iu4_spec(au_iu_iu4_i0_spec),
.au_iu_iu4_type_fp(au_iu_iu4_i0_type_fp),
.au_iu_iu4_type_ap(au_iu_iu4_i0_type_ap),
.au_iu_iu4_type_spv(au_iu_iu4_i0_type_spv),
.au_iu_iu4_type_st(au_iu_iu4_i0_type_st),
.au_iu_iu4_async_block(au_iu_iu4_i0_async_block),
.au_iu_iu4_isload(au_iu_iu4_i0_isload),
.au_iu_iu4_isstore(au_iu_iu4_i0_isstore),
.au_iu_iu4_rte_lq(au_iu_iu4_i0_rte_lq),
.au_iu_iu4_rte_sq(au_iu_iu4_i0_rte_sq),
.au_iu_iu4_rte_axu0(au_iu_iu4_i0_rte_axu0),
.au_iu_iu4_rte_axu1(au_iu_iu4_i0_rte_axu1),
.au_iu_iu4_no_ram(au_iu_iu4_i0_no_ram),
// Decoded instruction to send to rename
.fdec_frn_iu5_ix_vld(fdec_frn_iu5_i0_vld_int),
.fdec_frn_iu5_ix_ucode(fdec_frn_iu5_i0_ucode),
.fdec_frn_iu5_ix_2ucode(fdec_frn_iu5_i0_2ucode),
.fdec_frn_iu5_ix_fuse_nop(fdec_frn_iu5_i0_fuse_nop),
.fdec_frn_iu5_ix_rte_lq(fdec_frn_iu5_i0_rte_lq),
.fdec_frn_iu5_ix_rte_sq(fdec_frn_iu5_i0_rte_sq),
.fdec_frn_iu5_ix_rte_fx0(fdec_frn_iu5_i0_rte_fx0),
.fdec_frn_iu5_ix_rte_fx1(fdec_frn_iu5_i0_rte_fx1),
.fdec_frn_iu5_ix_rte_axu0(fdec_frn_iu5_i0_rte_axu0),
.fdec_frn_iu5_ix_rte_axu1(fdec_frn_iu5_i0_rte_axu1),
.fdec_frn_iu5_ix_valop(fdec_frn_iu5_i0_valop),
.fdec_frn_iu5_ix_ord(fdec_frn_iu5_i0_ord),
.fdec_frn_iu5_ix_cord(fdec_frn_iu5_i0_cord),
.fdec_frn_iu5_ix_error(fdec_frn_iu5_i0_error),
.fdec_frn_iu5_ix_fusion(fdec_frn_iu5_i0_fusion),
.fdec_frn_iu5_ix_spec(fdec_frn_iu5_i0_spec),
.fdec_frn_iu5_ix_type_fp(fdec_frn_iu5_i0_type_fp),
.fdec_frn_iu5_ix_type_ap(fdec_frn_iu5_i0_type_ap),
.fdec_frn_iu5_ix_type_spv(fdec_frn_iu5_i0_type_spv),
.fdec_frn_iu5_ix_type_st(fdec_frn_iu5_i0_type_st),
.fdec_frn_iu5_ix_async_block(fdec_frn_iu5_i0_async_block),
.fdec_frn_iu5_ix_np1_flush(fdec_frn_iu5_i0_np1_flush),
.fdec_frn_iu5_ix_core_block(fdec_frn_iu5_i0_core_block),
.fdec_frn_iu5_ix_isram(fdec_frn_iu5_i0_isram),
.fdec_frn_iu5_ix_isload(fdec_frn_iu5_i0_isload),
.fdec_frn_iu5_ix_isstore(fdec_frn_iu5_i0_isstore),
.fdec_frn_iu5_ix_instr(fdec_frn_iu5_i0_instr),
.fdec_frn_iu5_ix_ifar(fdec_frn_iu5_i0_ifar),
.fdec_frn_iu5_ix_bta(fdec_frn_iu5_i0_bta),
.fdec_frn_iu5_ix_ilat(fdec_frn_iu5_i0_ilat),
.fdec_frn_iu5_ix_t1_v(fdec_frn_iu5_i0_t1_v),
.fdec_frn_iu5_ix_t1_t(fdec_frn_iu5_i0_t1_t),
.fdec_frn_iu5_ix_t1_a(fdec_frn_iu5_i0_t1_a),
.fdec_frn_iu5_ix_t2_v(fdec_frn_iu5_i0_t2_v),
.fdec_frn_iu5_ix_t2_a(fdec_frn_iu5_i0_t2_a),
.fdec_frn_iu5_ix_t2_t(fdec_frn_iu5_i0_t2_t),
.fdec_frn_iu5_ix_t3_v(fdec_frn_iu5_i0_t3_v),
.fdec_frn_iu5_ix_t3_a(fdec_frn_iu5_i0_t3_a),
.fdec_frn_iu5_ix_t3_t(fdec_frn_iu5_i0_t3_t),
.fdec_frn_iu5_ix_s1_v(fdec_frn_iu5_i0_s1_v),
.fdec_frn_iu5_ix_s1_a(fdec_frn_iu5_i0_s1_a),
.fdec_frn_iu5_ix_s1_t(fdec_frn_iu5_i0_s1_t),
.fdec_frn_iu5_ix_s2_v(fdec_frn_iu5_i0_s2_v),
.fdec_frn_iu5_ix_s2_a(fdec_frn_iu5_i0_s2_a),
.fdec_frn_iu5_ix_s2_t(fdec_frn_iu5_i0_s2_t),
.fdec_frn_iu5_ix_s3_v(fdec_frn_iu5_i0_s3_v),
.fdec_frn_iu5_ix_s3_a(fdec_frn_iu5_i0_s3_a),
.fdec_frn_iu5_ix_s3_t(fdec_frn_iu5_i0_s3_t),
.fdec_frn_iu5_ix_br_pred(fdec_frn_iu5_i0_br_pred),
.fdec_frn_iu5_ix_bh_update(fdec_frn_iu5_i0_bh_update),
.fdec_frn_iu5_ix_bh0_hist(fdec_frn_iu5_i0_bh0_hist),
.fdec_frn_iu5_ix_bh1_hist(fdec_frn_iu5_i0_bh1_hist),
.fdec_frn_iu5_ix_bh2_hist(fdec_frn_iu5_i0_bh2_hist),
.fdec_frn_iu5_ix_gshare(fdec_frn_iu5_i0_gshare),
.fdec_frn_iu5_ix_ls_ptr(fdec_frn_iu5_i0_ls_ptr),
.fdec_frn_iu5_ix_match(fdec_frn_iu5_i0_match),
.fdec_frn_iu5_ix_btb_entry(fdec_frn_iu5_i0_btb_entry),
.fdec_frn_iu5_ix_btb_hist(fdec_frn_iu5_i0_btb_hist),
.fdec_frn_iu5_ix_bta_val(fdec_frn_iu5_i0_bta_val),
.frn_fdec_iu5_stall(iu5_stall)
);
iuq_idec fx_dec1(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.clkoff_b(clkoff_b),
.act_dis(act_dis),
.tc_ac_ccflush_dc(tc_ac_ccflush_dc),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scan_in(scan_in[1]),
.scan_out(scan_out[1]),
.xu_iu_epcr_dgtmi(xu_iu_epcr_dgtmi),
.xu_iu_msrp_uclep(xu_iu_msrp_uclep),
.xu_iu_msr_pr(xu_iu_msr_pr),
.xu_iu_msr_gs(xu_iu_msr_gs),
.xu_iu_msr_ucle(xu_iu_msr_ucle),
.xu_iu_ccr2_ucode_dis(xu_iu_ccr2_ucode_dis),
.mm_iu_tlbwe_binv(mm_iu_tlbwe_binv),
.spr_dec_mask(spr_dec_mask),
.spr_dec_match(spr_dec_match),
.cp_iu_iu4_flush(cp_iu_iu4_flush),
.uc_ib_iu3_flush_all(uc_ib_iu3_flush_all),
.br_iu_redirect(br_iu_redirect),
.ib_id_iu4_valid(ib_id_iu4_1_valid),
.ib_id_iu4_ifar(ib_id_iu4_1_ifar),
.ib_id_iu4_bta(ib_id_iu4_1_bta),
.ib_id_iu4_instr(ib_id_iu4_1_instr),
.ib_id_iu4_ucode(ib_id_iu4_1_ucode),
.ib_id_iu4_ucode_ext(ib_id_iu4_1_ucode_ext),
.ib_id_iu4_isram(ib_id_iu4_1_isram),
.ib_id_iu4_fuse_data(ib_id_iu4_1_fuse_data),
.ib_id_iu4_fuse_val(ib_id_iu4_1_fuse_val),
//AXU Interface
.au_iu_iu4_i_dec_b(au_iu_iu4_i1_i_dec_b),
.au_iu_iu4_ucode(au_iu_iu4_i1_ucode),
.au_iu_iu4_t1_v(au_iu_iu4_i1_t1_v),
.au_iu_iu4_t1_t(au_iu_iu4_i1_t1_t),
.au_iu_iu4_t1_a(au_iu_iu4_i1_t1_a),
.au_iu_iu4_t2_v(au_iu_iu4_i1_t2_v),
.au_iu_iu4_t2_a(au_iu_iu4_i1_t2_a),
.au_iu_iu4_t2_t(au_iu_iu4_i1_t2_t),
.au_iu_iu4_t3_v(au_iu_iu4_i1_t3_v),
.au_iu_iu4_t3_a(au_iu_iu4_i1_t3_a),
.au_iu_iu4_t3_t(au_iu_iu4_i1_t3_t),
.au_iu_iu4_s1_v(au_iu_iu4_i1_s1_v),
.au_iu_iu4_s1_a(au_iu_iu4_i1_s1_a),
.au_iu_iu4_s1_t(au_iu_iu4_i1_s1_t),
.au_iu_iu4_s2_v(au_iu_iu4_i1_s2_v),
.au_iu_iu4_s2_a(au_iu_iu4_i1_s2_a),
.au_iu_iu4_s2_t(au_iu_iu4_i1_s2_t),
.au_iu_iu4_s3_v(au_iu_iu4_i1_s3_v),
.au_iu_iu4_s3_a(au_iu_iu4_i1_s3_a),
.au_iu_iu4_s3_t(au_iu_iu4_i1_s3_t),
.au_iu_iu4_ilat(au_iu_iu4_i1_ilat),
.au_iu_iu4_ord(au_iu_iu4_i1_ord),
.au_iu_iu4_cord(au_iu_iu4_i1_cord),
.au_iu_iu4_spec(au_iu_iu4_i1_spec),
.au_iu_iu4_type_fp(au_iu_iu4_i1_type_fp),
.au_iu_iu4_type_ap(au_iu_iu4_i1_type_ap),
.au_iu_iu4_type_spv(au_iu_iu4_i1_type_spv),
.au_iu_iu4_type_st(au_iu_iu4_i1_type_st),
.au_iu_iu4_async_block(au_iu_iu4_i1_async_block),
.au_iu_iu4_isload(au_iu_iu4_i1_isload),
.au_iu_iu4_isstore(au_iu_iu4_i1_isstore),
.au_iu_iu4_rte_lq(au_iu_iu4_i1_rte_lq),
.au_iu_iu4_rte_sq(au_iu_iu4_i1_rte_sq),
.au_iu_iu4_rte_axu0(au_iu_iu4_i1_rte_axu0),
.au_iu_iu4_rte_axu1(au_iu_iu4_i1_rte_axu1),
.au_iu_iu4_no_ram(au_iu_iu4_i1_no_ram),
// Decoded instruction to send to rename
.fdec_frn_iu5_ix_vld(fdec_frn_iu5_i1_vld),
.fdec_frn_iu5_ix_ucode(fdec_frn_iu5_i1_ucode),
.fdec_frn_iu5_ix_2ucode(),
.fdec_frn_iu5_ix_fuse_nop(fdec_frn_iu5_i1_fuse_nop),
.fdec_frn_iu5_ix_rte_lq(fdec_frn_iu5_i1_rte_lq),
.fdec_frn_iu5_ix_rte_sq(fdec_frn_iu5_i1_rte_sq),
.fdec_frn_iu5_ix_rte_fx0(fdec_frn_iu5_i1_rte_fx0),
.fdec_frn_iu5_ix_rte_fx1(fdec_frn_iu5_i1_rte_fx1),
.fdec_frn_iu5_ix_rte_axu0(fdec_frn_iu5_i1_rte_axu0),
.fdec_frn_iu5_ix_rte_axu1(fdec_frn_iu5_i1_rte_axu1),
.fdec_frn_iu5_ix_valop(fdec_frn_iu5_i1_valop),
.fdec_frn_iu5_ix_ord(fdec_frn_iu5_i1_ord),
.fdec_frn_iu5_ix_cord(fdec_frn_iu5_i1_cord),
.fdec_frn_iu5_ix_error(fdec_frn_iu5_i1_error),
.fdec_frn_iu5_ix_fusion(fdec_frn_iu5_i1_fusion),
.fdec_frn_iu5_ix_spec(fdec_frn_iu5_i1_spec),
.fdec_frn_iu5_ix_type_fp(fdec_frn_iu5_i1_type_fp),
.fdec_frn_iu5_ix_type_ap(fdec_frn_iu5_i1_type_ap),
.fdec_frn_iu5_ix_type_spv(fdec_frn_iu5_i1_type_spv),
.fdec_frn_iu5_ix_type_st(fdec_frn_iu5_i1_type_st),
.fdec_frn_iu5_ix_async_block(fdec_frn_iu5_i1_async_block),
.fdec_frn_iu5_ix_np1_flush(fdec_frn_iu5_i1_np1_flush),
.fdec_frn_iu5_ix_core_block(fdec_frn_iu5_i1_core_block),
.fdec_frn_iu5_ix_isram(fdec_frn_iu5_i1_isram),
.fdec_frn_iu5_ix_isload(fdec_frn_iu5_i1_isload),
.fdec_frn_iu5_ix_isstore(fdec_frn_iu5_i1_isstore),
.fdec_frn_iu5_ix_instr(fdec_frn_iu5_i1_instr),
.fdec_frn_iu5_ix_ifar(fdec_frn_iu5_i1_ifar),
.fdec_frn_iu5_ix_bta(fdec_frn_iu5_i1_bta),
.fdec_frn_iu5_ix_ilat(fdec_frn_iu5_i1_ilat),
.fdec_frn_iu5_ix_t1_v(fdec_frn_iu5_i1_t1_v),
.fdec_frn_iu5_ix_t1_t(fdec_frn_iu5_i1_t1_t),
.fdec_frn_iu5_ix_t1_a(fdec_frn_iu5_i1_t1_a),
.fdec_frn_iu5_ix_t2_v(fdec_frn_iu5_i1_t2_v),
.fdec_frn_iu5_ix_t2_a(fdec_frn_iu5_i1_t2_a),
.fdec_frn_iu5_ix_t2_t(fdec_frn_iu5_i1_t2_t),
.fdec_frn_iu5_ix_t3_v(fdec_frn_iu5_i1_t3_v),
.fdec_frn_iu5_ix_t3_a(fdec_frn_iu5_i1_t3_a),
.fdec_frn_iu5_ix_t3_t(fdec_frn_iu5_i1_t3_t),
.fdec_frn_iu5_ix_s1_v(fdec_frn_iu5_i1_s1_v),
.fdec_frn_iu5_ix_s1_a(fdec_frn_iu5_i1_s1_a),
.fdec_frn_iu5_ix_s1_t(fdec_frn_iu5_i1_s1_t),
.fdec_frn_iu5_ix_s2_v(fdec_frn_iu5_i1_s2_v),
.fdec_frn_iu5_ix_s2_a(fdec_frn_iu5_i1_s2_a),
.fdec_frn_iu5_ix_s2_t(fdec_frn_iu5_i1_s2_t),
.fdec_frn_iu5_ix_s3_v(fdec_frn_iu5_i1_s3_v),
.fdec_frn_iu5_ix_s3_a(fdec_frn_iu5_i1_s3_a),
.fdec_frn_iu5_ix_s3_t(fdec_frn_iu5_i1_s3_t),
.fdec_frn_iu5_ix_br_pred(fdec_frn_iu5_i1_br_pred),
.fdec_frn_iu5_ix_bh_update(fdec_frn_iu5_i1_bh_update),
.fdec_frn_iu5_ix_bh0_hist(fdec_frn_iu5_i1_bh0_hist),
.fdec_frn_iu5_ix_bh1_hist(fdec_frn_iu5_i1_bh1_hist),
.fdec_frn_iu5_ix_bh2_hist(fdec_frn_iu5_i1_bh2_hist),
.fdec_frn_iu5_ix_gshare(fdec_frn_iu5_i1_gshare),
.fdec_frn_iu5_ix_ls_ptr(fdec_frn_iu5_i1_ls_ptr),
.fdec_frn_iu5_ix_match(fdec_frn_iu5_i1_match),
.fdec_frn_iu5_ix_btb_entry(fdec_frn_iu5_i1_btb_entry),
.fdec_frn_iu5_ix_btb_hist(fdec_frn_iu5_i1_btb_hist),
.fdec_frn_iu5_ix_bta_val(fdec_frn_iu5_i1_bta_val),
.frn_fdec_iu5_stall(iu5_stall)
);
iuq_axu_fu_dec axu_dec0(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.i_dec_si(scan_in[2]),
.i_dec_so(scan_out[2]),
.pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.clkoff_b(clkoff_b),
.act_dis(act_dis),
.tc_ac_ccflush_dc(tc_ac_ccflush_dc),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.iu_au_iu4_isram(ib_id_iu4_0_isram),
.iu_au_ucode_restart(1'b0),
.iu_au_config_iucr(iu_au_config_iucr),
.iu_au_iu4_instr_v(ib_id_iu4_0_valid),
.iu_au_iu4_instr(ib_id_iu4_0_instr[0:31]),
.iu_au_iu4_ucode_ext(ib_id_iu4_0_ucode_ext),
.iu_au_iu4_ucode(ib_id_iu4_0_ucode),
.iu_au_iu4_2ucode(1'b0),
.au_iu_iu4_i_dec_b(au_iu_iu4_i0_i_dec_b),
.au_iu_iu4_ucode(au_iu_iu4_i0_ucode),
.au_iu_iu4_t1_v(au_iu_iu4_i0_t1_v),
.au_iu_iu4_t1_t(au_iu_iu4_i0_t1_t),
.au_iu_iu4_t1_a(au_iu_iu4_i0_t1_a),
.au_iu_iu4_t2_v(au_iu_iu4_i0_t2_v),
.au_iu_iu4_t2_a(au_iu_iu4_i0_t2_a),
.au_iu_iu4_t2_t(au_iu_iu4_i0_t2_t),
.au_iu_iu4_t3_v(au_iu_iu4_i0_t3_v),
.au_iu_iu4_t3_a(au_iu_iu4_i0_t3_a),
.au_iu_iu4_t3_t(au_iu_iu4_i0_t3_t),
.au_iu_iu4_s1_v(au_iu_iu4_i0_s1_v),
.au_iu_iu4_s1_a(au_iu_iu4_i0_s1_a),
.au_iu_iu4_s1_t(au_iu_iu4_i0_s1_t),
.au_iu_iu4_s2_v(au_iu_iu4_i0_s2_v),
.au_iu_iu4_s2_a(au_iu_iu4_i0_s2_a),
.au_iu_iu4_s2_t(au_iu_iu4_i0_s2_t),
.au_iu_iu4_s3_v(au_iu_iu4_i0_s3_v),
.au_iu_iu4_s3_a(au_iu_iu4_i0_s3_a),
.au_iu_iu4_s3_t(au_iu_iu4_i0_s3_t),
.au_iu_iu4_ilat(au_iu_iu4_i0_ilat),
.au_iu_iu4_ord(au_iu_iu4_i0_ord),
.au_iu_iu4_cord(au_iu_iu4_i0_cord),
.au_iu_iu4_spec(au_iu_iu4_i0_spec),
.au_iu_iu4_type_fp(au_iu_iu4_i0_type_fp),
.au_iu_iu4_type_ap(au_iu_iu4_i0_type_ap),
.au_iu_iu4_type_spv(au_iu_iu4_i0_type_spv),
.au_iu_iu4_type_st(au_iu_iu4_i0_type_st),
.au_iu_iu4_async_block(au_iu_iu4_i0_async_block),
.au_iu_iu4_isload(au_iu_iu4_i0_isload),
.au_iu_iu4_isstore(au_iu_iu4_i0_isstore),
.au_iu_iu4_rte_lq(au_iu_iu4_i0_rte_lq),
.au_iu_iu4_rte_sq(au_iu_iu4_i0_rte_sq),
.au_iu_iu4_rte_axu0(au_iu_iu4_i0_rte_axu0),
.au_iu_iu4_rte_axu1(au_iu_iu4_i0_rte_axu1),
.au_iu_iu4_no_ram(au_iu_iu4_i0_no_ram)
);
iuq_axu_fu_dec axu_dec1(
.vdd(vdd),
.gnd(gnd),
.nclk(nclk),
.i_dec_si(scan_in[3]),
.i_dec_so(scan_out[3]),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.pc_iu_sg_2(pc_iu_sg_2),
.clkoff_b(clkoff_b),
.act_dis(act_dis),
.tc_ac_ccflush_dc(tc_ac_ccflush_dc),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.iu_au_iu4_isram(ib_id_iu4_1_isram),
.iu_au_ucode_restart(1'b0),
.iu_au_config_iucr(iu_au_config_iucr),
.iu_au_iu4_instr_v(ib_id_iu4_1_valid),
.iu_au_iu4_instr(ib_id_iu4_1_instr[0:31]),
.iu_au_iu4_ucode_ext(ib_id_iu4_1_ucode_ext),
.iu_au_iu4_ucode(ib_id_iu4_1_ucode),
.iu_au_iu4_2ucode(1'b0),
.au_iu_iu4_i_dec_b(au_iu_iu4_i1_i_dec_b),
.au_iu_iu4_ucode(au_iu_iu4_i1_ucode),
.au_iu_iu4_t1_v(au_iu_iu4_i1_t1_v),
.au_iu_iu4_t1_t(au_iu_iu4_i1_t1_t),
.au_iu_iu4_t1_a(au_iu_iu4_i1_t1_a),
.au_iu_iu4_t2_v(au_iu_iu4_i1_t2_v),
.au_iu_iu4_t2_a(au_iu_iu4_i1_t2_a),
.au_iu_iu4_t2_t(au_iu_iu4_i1_t2_t),
.au_iu_iu4_t3_v(au_iu_iu4_i1_t3_v),
.au_iu_iu4_t3_a(au_iu_iu4_i1_t3_a),
.au_iu_iu4_t3_t(au_iu_iu4_i1_t3_t),
.au_iu_iu4_s1_v(au_iu_iu4_i1_s1_v),
.au_iu_iu4_s1_a(au_iu_iu4_i1_s1_a),
.au_iu_iu4_s1_t(au_iu_iu4_i1_s1_t),
.au_iu_iu4_s2_v(au_iu_iu4_i1_s2_v),
.au_iu_iu4_s2_a(au_iu_iu4_i1_s2_a),
.au_iu_iu4_s2_t(au_iu_iu4_i1_s2_t),
.au_iu_iu4_s3_v(au_iu_iu4_i1_s3_v),
.au_iu_iu4_s3_a(au_iu_iu4_i1_s3_a),
.au_iu_iu4_s3_t(au_iu_iu4_i1_s3_t),
.au_iu_iu4_ilat(au_iu_iu4_i1_ilat),
.au_iu_iu4_ord(au_iu_iu4_i1_ord),
.au_iu_iu4_cord(au_iu_iu4_i1_cord),
.au_iu_iu4_spec(au_iu_iu4_i1_spec),
.au_iu_iu4_type_fp(au_iu_iu4_i1_type_fp),
.au_iu_iu4_type_ap(au_iu_iu4_i1_type_ap),
.au_iu_iu4_type_spv(au_iu_iu4_i1_type_spv),
.au_iu_iu4_type_st(au_iu_iu4_i1_type_st),
.au_iu_iu4_async_block(au_iu_iu4_i1_async_block),
.au_iu_iu4_isload(au_iu_iu4_i1_isload),
.au_iu_iu4_isstore(au_iu_iu4_i1_isstore),
.au_iu_iu4_rte_lq(au_iu_iu4_i1_rte_lq),
.au_iu_iu4_rte_sq(au_iu_iu4_i1_rte_sq),
.au_iu_iu4_rte_axu0(au_iu_iu4_i1_rte_axu0),
.au_iu_iu4_rte_axu1(au_iu_iu4_i1_rte_axu1),
.au_iu_iu4_no_ram(au_iu_iu4_i1_no_ram)
);
endmodule |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.