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module jglim_7seg(
input [7:0] io_in,
output [7:0] io_out
);
hex7seg seg7(
.counter(io_in[3:0]),
.dot(io_in[4]),
.inv(io_in[5]),
.segments(io_out[7:0])
);
endmodule |
module tt2_tholin_multiplier(
input [7:0] io_in,
output [7:0] io_out
);
wire s_A0 = io_in[0];
wire s_A1 = io_in[1];
wire s_A2 = io_in[2];
wire s_A3 = io_in[3];
wire s_B0 = io_in[4];
wire s_B1 = io_in[5];
wire s_B2 = io_in[6];
wire s_B3 = io_in[7];
wire s_R0;
wire s_R1;
wire s_R2;
wire s_R3;
wire s_R4;
wire s_R5;
wire s_R6;
wire s_R7;
assign io_out[0] = s_R0;
assign io_out[1] = s_R1;
assign io_out[2] = s_R2;
assign io_out[3] = s_R3;
assign io_out[4] = s_R4;
assign io_out[5] = s_R5;
assign io_out[6] = s_R6;
assign io_out[7] = s_R7;
main CIRCUIT_0 (.A0(s_A0),
.A1(s_A1),
.A2(s_A2),
.A3(s_A3),
.B0(s_B0),
.B1(s_B1),
.B2(s_B2),
.B3(s_B3),
.R0(s_R0),
.R1(s_R1),
.R2(s_R2),
.R3(s_R3),
.R4(s_R4),
.R5(s_R5),
.R6(s_R6),
.R7(s_R7));
endmodule |
module asic_multiplier_wrapper (
input [7:0] io_in ,
output [7:0] io_out
);
// Instantiate the multiplier
asic_multiplier asic_multiplier_top (
.clk (io_in[0] ),
.reset (io_in[1] ),
.i_factor_a (io_in[4:2] ),
.i_factor_b (io_in[7:5] ),
.o_segments (io_out[6:0]),
.o_lsb_digit(io_out[7] )
);
endmodule |
module user_module_347688030570545747(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5;
wire net6;
wire net7;
wire net8;
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59;
wire net60;
wire net61;
wire net62;
wire net63;
wire net64;
wire net65;
wire net66;
wire net67;
wire net68;
wire net69;
wire net70;
wire net71;
wire net72;
wire net73;
wire net74;
wire net75;
wire net76;
wire net77;
wire net78;
wire net79;
wire net80;
wire net81;
wire net82;
wire net83;
wire net84;
wire net85;
wire net86;
wire net87;
wire net88;
wire net89;
wire net90;
wire net91;
wire net92;
wire net93;
wire net94;
wire net95;
wire net96;
wire net97;
wire net98;
wire net99;
wire net100;
wire net101;
wire net102;
wire net103;
wire net104;
wire net105;
wire net106;
wire net107 = 1'b1;
wire net108 = 1'b1;
wire net109 = 1'b0;
assign io_out[0] = net5;
assign io_out[1] = net6;
assign io_out[2] = net7;
assign io_out[3] = net8;
assign io_out[4] = net9;
assign io_out[5] = net10;
assign io_out[6] = net11;
buffer_cell input_w (
.in (net1),
.out (net12)
);
not_cell input_not_w (
.in (net1),
.out (net13)
);
buffer_cell input_x (
.in (net2),
.out (net14)
);
not_cell input_not_x (
.in (net2),
.out (net15)
);
buffer_cell input_y (
.in (net3),
.out (net16)
);
not_cell input_not_y (
.in (net3),
.out (net17)
);
buffer_cell input_z (
.in (net4),
.out (net18)
);
not_cell input_not_z (
.in (net4),
.out (net19)
);
and_cell gate_and_0 (
.a (net13),
.b (net15),
.out (net20)
);
and_cell gate_and_1 (
.a (net16),
.b (net16),
.out (net21)
);
and_cell gate_and_2 (
.a (net12),
.b (net15),
.out (net22)
);
and_cell gate_and_3 (
.a (net17),
.b (net17),
.out (net23)
);
and_cell gate_and_4 (
.a (net13),
.b (net14),
.out (net24)
);
and_cell gate_and_5 (
.a (net18),
.b (net18),
.out (net25)
);
and_cell gate_and_6 (
.a (net15),
.b (net17),
.out (net26)
);
and_cell gate_and_7 (
.a (net19),
.b (net19),
.out (net27)
);
and_cell gate_and_8 (
.a (net13),
.b (net17),
.out (net28)
);
and_cell gate_and_9 (
.a (net19),
.b (net19),
.out (net29)
);
and_cell gate_and_10 (
.a (net15),
.b (net17),
.out (net30)
);
and_cell gate_and_11 (
.a (net13),
.b (net15),
.out (net31)
);
and_cell gate_and_12 (
.a (net13),
.b (net16),
.out (net32)
);
and_cell gate_and_13 (
.a (net18),
.b (net18),
.out (net33)
);
and_cell gate_and_14 (
.a (net13),
.b (net14),
.out (net34)
);
and_cell gate_and_15 (
.a (net13),
.b (net17),
.out (net35)
);
and_cell gate_and_16 (
.a (net15),
.b (net17),
.out (net36)
);
and_cell gate_and_17 (
.a (net18),
.b (net18),
.out (net37)
);
and_cell gate_and_18 (
.a (net13),
.b (net18),
.out (net38)
);
and_cell gate_and_19 (
.a (net13),
.b (net15),
.out (net39)
);
and_cell gate_and_20 (
.a (net16),
.b (net16),
.out (net40)
);
and_cell gate_and_21 (
.a (net15),
.b (net17),
.out (net41)
);
and_cell gate_and_22 (
.a (net19),
.b (net19),
.out (net42)
);
and_cell gate_and_23 (
.a (net13),
.b (net14),
.out (net43)
);
and_cell gate_and_24 (
.a (net17),
.b (net18),
.out (net44)
);
and_cell gate_and_25 (
.a (net13),
.b (net16),
.out (net45)
);
and_cell gate_and_26 (
.a (net19),
.b (net19),
.out (net46)
);
and_cell gate_and_27 (
.a (net15),
.b (net17),
.out (net47)
);
and_cell gate_and_28 (
.a (net19),
.b (net19),
.out (net48)
);
and_cell gate_and_29 (
.a (net13),
.b (net16),
.out (net49)
);
and_cell gate_and_30 (
.a (net19),
.b (net19),
.out (net50)
);
and_cell gate_and_31 (
.a (net15),
.b (net17),
.out (net51)
);
and_cell gate_and_32 (
.a (net19),
.b (net19),
.out (net52)
);
and_cell gate_and_33 (
.a (net12),
.b (net15),
.out (net53)
);
and_cell gate_and_34 (
.a (net17),
.b (net17),
.out (net54)
);
and_cell gate_and_35 (
.a (net13),
.b (net14),
.out (net55)
);
and_cell gate_and_36 (
.a (net17),
.b (net17),
.out (net56)
);
and_cell gate_and_37 (
.a (net13),
.b (net14),
.out (net57)
);
and_cell gate_and_38 (
.a (net19),
.b (net19),
.out (net58)
);
and_cell gate_and_39 (
.a (net13),
.b (net15),
.out (net59)
);
and_cell gate_and_40 (
.a (net16),
.b (net16),
.out (net60)
);
and_cell gate_and_41 (
.a (net12),
.b (net15),
.out (net61)
);
and_cell gate_and_42 (
.a (net17),
.b (net17),
.out (net62)
);
and_cell gate_and_43 (
.a (net13),
.b (net14),
.out (net63)
);
and_cell gate_and_44 (
.a (net17),
.b (net17),
.out (net64)
);
and_cell gate_and_45 (
.a (net13),
.b (net14),
.out (net65)
);
and_cell gate_and_46 (
.a (net19),
.b (net19),
.out (net66)
);
and_cell gate_and_47 (
.a (net20),
.b (net21),
.out (net67)
);
and_cell gate_and_48 (
.a (net22),
.b (net23),
.out (net68)
);
and_cell gate_and_49 (
.a (net24),
.b (net25),
.out (net69)
);
and_cell gate_and_50 (
.a (net26),
.b (net27),
.out (net70)
);
and_cell gate_and_51 (
.a (net28),
.b (net29),
.out (net71)
);
and_cell gate_and_52 (
.a (net32),
.b (net33),
.out (net72)
);
and_cell gate_and_53 (
.a (net36),
.b (net37),
.out (net73)
);
and_cell gate_and_54 (
.a (net39),
.b (net40),
.out (net74)
);
and_cell gate_and_55 (
.a (net41),
.b (net42),
.out (net75)
);
and_cell gate_and_56 (
.a (net44),
.b (net43),
.out (net76)
);
and_cell gate_and_57 (
.a (net45),
.b (net46),
.out (net77)
);
and_cell gate_and_58 (
.a (net47),
.b (net48),
.out (net78)
);
and_cell gate_and_59 (
.a (net49),
.b (net50),
.out (net79)
);
and_cell gate_and_60 (
.a (net52),
.b (net51),
.out (net80)
);
and_cell gate_and_61 (
.a (net53),
.b (net54),
.out (net81)
);
and_cell gate_and_62 (
.a (net55),
.b (net56),
.out (net82)
);
and_cell gate_and_63 (
.a (net57),
.b (net58),
.out (net83)
);
and_cell gate_and_64 (
.a (net60),
.b (net59),
.out (net84)
);
and_cell gate_and_65 (
.a (net61),
.b (net62),
.out (net85)
);
and_cell gate_and_66 (
.a (net63),
.b (net64),
.out (net86)
);
and_cell gate_and_67 (
.a (net65),
.b (net66),
.out (net87)
);
or_cell gate_or_0 (
.a (net67),
.b (net68),
.out (net88)
);
or_cell gate_or_1 (
.a (net69),
.b (net70),
.out (net89)
);
or_cell gate_or_2 (
.a (net71),
.b (net30),
.out (net90)
);
or_cell gate_or_3 (
.a (net31),
.b (net72),
.out (net91)
);
or_cell gate_or_4 (
.a (net34),
.b (net35),
.out (net92)
);
or_cell gate_or_5 (
.a (net73),
.b (net38),
.out (net93)
);
or_cell gate_or_6 (
.a (net74),
.b (net75),
.out (net94)
);
or_cell gate_or_7 (
.a (net76),
.b (net77),
.out (net95)
);
or_cell gate_or_8 (
.a (net78),
.b (net79),
.out (net96)
);
or_cell gate_or_9 (
.a (net80),
.b (net81),
.out (net97)
);
or_cell gate_or_10 (
.a (net82),
.b (net83),
.out (net98)
);
or_cell gate_or_11 (
.a (net84),
.b (net85),
.out (net99)
);
or_cell gate_or_12 (
.a (net86),
.b (net87),
.out (net100)
);
or_cell gate_or_13 (
.a (net88),
.b (net89),
.out (net101)
);
or_cell gate_or_14 (
.a (net90),
.b (net91),
.out (net102)
);
or_cell gate_or_15 (
.a (net92),
.b (net93),
.out (net103)
);
or_cell gate_or_16 (
.a (net94),
.b (net95),
.out (net104)
);
or_cell gate_or_17 (
.a (net97),
.b (net98),
.out (net105)
);
or_cell gate_or_18 (
.a (net99),
.b (net100),
.out (net106)
);
buffer_cell output_A (
.in (net101),
.out (net5)
);
buffer_cell output_B (
.in (net102),
.out (net6)
);
buffer_cell output_C (
.in (net103),
.out (net7)
);
buffer_cell output_D (
.in (net104),
.out (net8)
);
buffer_cell output_E (
.in (net96),
.out (net9)
);
buffer_cell output_F (
.in (net105),
.out (net10)
);
buffer_cell output_G (
.in (net106),
.out (net11)
);
endmodule |
module tt2_tholin_namebadge (
input [7:0] io_in,
output [7:0] io_out
);
wire CLK = io_in[0];
wire RST = io_in[1];
wire EF0 = io_in[2];
wire EF1 = io_in[3];
wire EF2 = io_in[4];
wire RS;
wire E;
wire D4;
wire D5;
wire D6;
wire D7;
wire LED0;
wire LED1;
assign io_out[0] = RS;
assign io_out[1] = E;
assign io_out[2] = D4;
assign io_out[3] = D5;
assign io_out[4] = D6;
assign io_out[5] = D7;
assign io_out[6] = LED0;
assign io_out[7] = LED1;
lcd lcd (
.CLK(CLK),
.RST(RST),
.EF0(EF0),
.EF1(EF1),
.EF2(EF2),
.RS(RS),
.E(E),
.D4(D4),
.D5(D5),
.D6(D6),
.D7(D7),
.LED0(LED0),
.LED1(LED1)
);
endmodule |
module rotary_encoder (
input wire [7:0] io_in,
output wire [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire encA = io_in[2];
wire encB = io_in[3];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
assign io_out[7] = 0;
reg [7:0] delay_counter;
reg [3:0] digit;
reg old_value;
always @(posedge clk) begin
// if reset, set counter to 0
if (reset) begin
digit <= 0;
old_value <= encA;
delay_counter <= 0;
end else begin
if (delay_counter != 0) begin
delay_counter <= delay_counter - 1'b1;
end
if (encA == 1 && old_value == 0 && delay_counter == 0) begin
delay_counter = 125; //IOrefreshrate = 12.5Khz => clock = 6.25KHz => delay 20ms = 125 cycles
//rising edge on A
if(encB == 0) begin
// increment digit
digit <= digit + 1'b1;
// only count from 0 to 9
if (digit == 9) begin
digit <= 0;
end
end else begin
// decrement digit
if (digit == 0) begin
digit <= 9;
end else begin
digit <= digit - 1'b1;
end
end
end
old_value = encA;
end
end
// instantiate segment display
seg7 seg7(.counter(digit), .segments(led_out));
endmodule |
module gregdavill_clock_top(
input [7:0] io_in,
output [7:0] io_out
);
clock clock_top (
.i_clk(io_in[0]),
.i_rst(io_in[1]),
.i_min_up(io_in[2]),
.i_hour_up(io_in[3]),
.o_clk(io_out[0]),
.o_latch(io_out[1]),
.o_bit(io_out[2])
);
endmodule |
module recepsaid_euclidean_algorithm(
input [7:0] io_in,
output [7:0] io_out
);
wire clk;
wire num_okey;
wire rst;
wire [3:0] number;
reg [3:0] num1;
reg [3:0] num2;
reg [6:0] ssd_out;
reg [2:0] state = S0;
reg start;
wire [3:0] gcd;
wire [6:0] decoder_out;
assign num_okey = io_in[7];
assign rst = io_in[6];
assign number = io_in[4:1];
assign clk = io_in[0];
assign io_out[6:0] = ssd_out;
localparam S0 = 3'd0,
S1 = 3'd1,
S2 = 3'd2,
S3 = 3'd3,
S4 = 3'd4;
always @(posedge clk)
begin
if(rst) begin
//ssd_out idle state
state <= S0;
ssd_out <= 7'b1000000;
end
else begin
case(state)
S0:
begin
//ssd_out idle state
start <= 1'b0;
ssd_out <= 7'b1000000;
if(num_okey) begin
state <= S1;
end
else begin
state <= S0;
end
end
S1:
begin
//ssd_out okey state
num1 <= number;
start <= 1'b0;
ssd_out <= 7'b1011100;
if(~num_okey) begin
state <= S2;
end
else begin
state <= S1;
end
end
S2:
begin
//ssd_out next state
start <= 1'b0;
ssd_out <= 7'b1010100;
if(num_okey) begin
state <= S3;
end
else begin
state <= S2;
end
end
S3:
begin
//ssd_out okey state
num2 <= number;
start <= 1'b0;
ssd_out <= 7'b1011100;
if(~num_okey) begin
state <= S4;
end
else begin
state <= S3;
end
end
S4:
begin
//ssd_out result state
start <= 1'b1;
ssd_out <= decoder_out;
if(rst) begin
state <= S0;
end
else begin
state <= S4;
end
end
default:
begin
ssd_out <= 7'b1000000;
num1 <= 4'b0000;
num2 <= 4'b0000;
start <= 1'b0;
end
endcase
end
end
gcd_top #(.DATA_BITS_TOP(4)) gcdtop(
.okey_i (start),
.rst_i (rst),
.clk_i (clk),
.x_i (num1),
.y_i (num2),
.result_o (gcd)
);
ssd_decoder decoder(
.ssd_i (gcd),
.rst_i (rst),
.ssd_o (decoder_out)
);
endmodule |
module cpldcpu_MCPU5plus(
input [7:0] io_in,
output [7:0] io_out
);
MCPU5plus MCPU5plus_top (
.clk(io_in[0]),
.rst(io_in[1]),
.inst_in(io_in[7:2]),
.cpu_out(io_out[7:0])
);
endmodule |
module pwm_gen (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
reg counter_state;
reg [5:0] pwm_counter;
reg [6:0] duty;
reg pwm;
assign io_out = {duty, pwm};
//upcounter which determines pwm period
always @(posedge clk) begin
if (reset)
pwm_counter <= 0;
else
pwm_counter <= pwm_counter + 1;
end
//duty state machine to determine countup or countdown
always @(posedge clk) begin
if (reset) begin
counter_state = 0;
end else begin
case (counter_state)
0:
if (duty == 8'b111110)
counter_state = 1;
else
counter_state = 0;
1:
if (duty == 8'b000001)
counter_state = 0;
else
counter_state = 1;
endcase
end
end
//generate duty
always @(posedge clk) begin
if (reset) begin
duty <= 0;
end else begin
if (pwm_counter == 6'b000000) begin
if (counter_state == 0) begin
duty <= duty + 1;
end else if(counter_state == 1) begin
duty <= duty - 1;
end
end
end
end
//generate pwm where duty determines it's duty cycle
always @(posedge clk) begin
if(reset) begin
pwm <= 0;
end else begin
if (pwm_counter == 6'b000000) begin
pwm <= 1;
end else if (pwm_counter == duty[6:0]) begin
pwm <= 0;
end
end
end
endmodule |
module yubex_egg_timer (
input [7:0] io_in,
output reg [7:0] io_out
);
wire clk;
localparam clk_frequency = 14'd10000; // frequency in Hz
wire rst;
wire start;
assign clk = io_in[0];
assign rst = io_in[1];
assign start = io_in[2];
reg [1:0] state;
localparam idle = 2'b00;
localparam waiting = 2'b01;
localparam alarm = 2'b10;
reg [13:0] clk_cycle_cnt;
reg [5:0] second_cnt;
reg [4:0] minute_cnt;
always @(posedge clk or posedge rst)
begin
if(rst) begin
state <= idle;
end
else begin
case(state)
idle:
begin
if (start == 1'b1)
state <= waiting;
else
state <= idle;
end
waiting:
begin
if (second_cnt == 6'b0 && minute_cnt == 5'b0 && clk_cycle_cnt == 14'b0)
state <= alarm;
else
state <= waiting;
end
alarm:
begin
if (start == 1'b0)
state <= idle;
else
state <= alarm;
end
default: state <= idle;
endcase
end
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
minute_cnt <= 5'b1;
second_cnt <= 6'd59;
clk_cycle_cnt <= clk_frequency - 1;
end
else begin
if (state == idle) begin
//load wait time from io_in
minute_cnt <= io_in[7:3] - 1;
second_cnt <= 6'd59;
clk_cycle_cnt <= clk_frequency - 1;
end
if (state == waiting) begin
if (clk_cycle_cnt == 14'b0) begin
clk_cycle_cnt <= clk_frequency - 1;
if (second_cnt == 6'b0) begin
second_cnt <= 6'd59;
if (minute_cnt != 5'b0) begin
minute_cnt <= minute_cnt - 1;
end
end
else begin
second_cnt <= second_cnt - 1;
end
end
else begin
clk_cycle_cnt <= clk_cycle_cnt - 1;
end
end
end
end
// 7 segment display
always @(posedge clk or posedge rst)
begin
if(rst) begin
io_out <= 8'b0;
end else begin
case(state)
idle:
begin
io_out <= 8'b01000000;
end
waiting:
begin
io_out [6:0] <= 7'b0;
if (clk_cycle_cnt == 14'b0)
io_out[7]<=~io_out[7];
end
alarm:
begin
io_out <= 8'b11110111;
end
default:;
endcase
end
end
endmodule |
module user_module_349833797657690706(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13 = 1'b1;
wire net14 = 1'b1;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59 = 1'b0;
wire net60 = 1'b0;
wire net61 = 1'b0;
wire net62 = 1'b0;
wire net63 = 1'b0;
wire net64 = 1'b0;
wire net65 = 1'b0;
wire net66 = 1'b0;
wire net67 = 1'b0;
wire net68 = 1'b0;
wire net69 = 1'b0;
wire net70 = 1'b0;
wire net71 = 1'b0;
wire net72 = 1'b0;
wire net73 = 1'b0;
wire net74 = 1'b0;
wire net75 = 1'b0;
wire net76;
wire net77;
wire net78;
wire net79;
wire net80;
wire net81;
wire net82;
wire net83;
wire net84;
wire net85;
wire net86;
wire net87;
wire net88;
wire net89;
wire net90;
wire net91;
wire net92;
wire net93;
wire net94;
wire net95;
wire net96;
wire net97;
wire net98;
wire net99;
wire net100;
wire net101;
wire net102;
wire net103;
wire net104;
wire net105;
wire net106;
wire net107;
wire net108;
wire net109;
wire net110;
wire net111;
wire net112;
wire net113;
wire net114;
wire net115;
wire net116;
wire net117;
wire net118;
wire net119;
wire net120 = 1'b0;
wire net121 = 1'b0;
wire net122 = 1'b0;
wire net123 = 1'b0;
wire net124 = 1'b0;
wire net125 = 1'b0;
wire net126 = 1'b0;
wire net127 = 1'b0;
wire net128 = 1'b0;
wire net129 = 1'b0;
wire net130 = 1'b0;
wire net131 = 1'b0;
wire net132 = 1'b0;
wire net133 = 1'b0;
wire net134 = 1'b0;
wire net135 = 1'b0;
wire net136;
wire net137;
wire net138;
wire net139;
wire net140;
wire net141;
wire net142;
wire net143;
wire net144;
wire net145 = 1'b0;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[4] = net11;
assign io_out[5] = net12;
and_cell gate1 (
);
or_cell gate2 (
);
xor_cell gate3 (
);
nand_cell gate4 (
);
not_cell gate5 (
);
buffer_cell gate6 (
);
mux_cell mux1 (
);
dff_cell flipflop1 (
);
dff_cell flipflop2 (
.d (net15),
.clk (net3),
.q (net16)
);
nand_cell gate7 (
.a (net17),
.b (net18),
.out (net19)
);
nand_cell gate8 (
.a (net18),
.b (net2),
.out (net20)
);
dff_cell flipflop3 (
.d (net21),
.clk (net3),
.q (net22)
);
nand_cell gate9 (
.a (net19),
.b (net20),
.out (net23)
);
nand_cell gate10 (
.a (net17),
.b (net2),
.out (net18)
);
and_cell gate11 (
.a (net1),
.b (net22),
.out (net15)
);
dff_cell flipflop4 (
.d (net24),
.clk (net3),
.q (net25)
);
and_cell gate12 (
.a (net1),
.b (net16),
.out (net24)
);
dff_cell flipflop5 (
.d (net26),
.clk (net3),
.q (net27)
);
and_cell gate13 (
.a (net1),
.b (net25),
.out (net26)
);
dff_cell flipflop6 (
.d (net28),
.clk (net3),
.q (net29)
);
and_cell gate14 (
.a (net1),
.b (net27),
.out (net28)
);
dff_cell flipflop7 (
.d (net30),
.clk (net3),
.q (net31)
);
and_cell gate15 (
.a (net1),
.b (net32),
.out (net30)
);
dff_cell flipflop8 (
.d (net33),
.clk (net3),
.q (net34)
);
and_cell gate16 (
.a (net1),
.b (net31),
.out (net33)
);
dff_cell flipflop9 (
.d (net35),
.clk (net3),
.q (net36)
);
and_cell gate17 (
.a (net1),
.b (net34),
.out (net35)
);
dff_cell flipflop10 (
.d (net37),
.clk (net3),
.q (net38)
);
and_cell gate18 (
.a (net1),
.b (net36),
.out (net37)
);
and_cell gate19 (
.a (net1),
.b (net23),
.out (net21)
);
dff_cell flipflop11 (
.d (net39),
.clk (net3),
.q (net40)
);
and_cell gate20 (
.a (net1),
.b (net38),
.out (net39)
);
dff_cell flipflop12 (
.d (net41),
.clk (net3),
.q (net42)
);
and_cell gate21 (
.a (net1),
.b (net40),
.out (net41)
);
dff_cell flipflop13 (
.d (net43),
.clk (net3),
.q (net44)
);
and_cell gate22 (
.a (net1),
.b (net42),
.out (net43)
);
dff_cell flipflop14 (
.d (net45),
.clk (net3),
.q (net46)
);
and_cell gate23 (
.a (net1),
.b (net47),
.out (net45)
);
dff_cell flipflop15 (
.d (net48),
.clk (net3),
.q (net49)
);
and_cell gate24 (
.a (net1),
.b (net46),
.out (net48)
);
dff_cell flipflop16 (
.d (net50),
.clk (net3),
.q (net51)
);
and_cell gate25 (
.a (net1),
.b (net49),
.out (net50)
);
dff_cell flipflop17 (
.d (net52),
.clk (net3),
.q (net9)
);
and_cell gate26 (
.a (net1),
.b (net51),
.out (net52)
);
nand_cell gate31 (
.a (net17),
.b (net53),
.out (net54)
);
nand_cell gate32 (
.a (net53),
.b (net29),
.out (net55)
);
nand_cell gate33 (
.a (net54),
.b (net55),
.out (net32)
);
nand_cell gate34 (
.a (net17),
.b (net29),
.out (net53)
);
nand_cell gate35 (
.a (net17),
.b (net56),
.out (net57)
);
nand_cell gate36 (
.a (net56),
.b (net44),
.out (net58)
);
nand_cell gate37 (
.a (net57),
.b (net58),
.out (net47)
);
nand_cell gate38 (
.a (net17),
.b (net44),
.out (net56)
);
and_cell gate39 (
.a (net9),
.b (net4),
.out (net17)
);
dff_cell flipflop18 (
.d (net76),
.clk (net7),
.q (net77)
);
nand_cell gate40 (
.a (net78),
.b (net79),
.out (net80)
);
nand_cell gate41 (
.a (net79),
.b (net6),
.out (net81)
);
dff_cell flipflop19 (
.d (net82),
.clk (net7),
.q (net83)
);
nand_cell gate42 (
.a (net80),
.b (net81),
.out (net84)
);
nand_cell gate43 (
.a (net78),
.b (net6),
.out (net79)
);
and_cell gate44 (
.a (net5),
.b (net83),
.out (net76)
);
dff_cell flipflop20 (
.d (net85),
.clk (net7),
.q (net86)
);
and_cell gate45 (
.a (net5),
.b (net77),
.out (net85)
);
dff_cell flipflop21 (
.d (net87),
.clk (net7),
.q (net88)
);
and_cell gate46 (
.a (net5),
.b (net86),
.out (net87)
);
dff_cell flipflop22 (
.d (net89),
.clk (net7),
.q (net90)
);
and_cell gate47 (
.a (net5),
.b (net88),
.out (net89)
);
dff_cell flipflop23 (
.d (net91),
.clk (net7),
.q (net92)
);
and_cell gate48 (
.a (net5),
.b (net93),
.out (net91)
);
dff_cell flipflop24 (
.d (net94),
.clk (net7),
.q (net95)
);
and_cell gate49 (
.a (net5),
.b (net92),
.out (net94)
);
dff_cell flipflop25 (
.d (net96),
.clk (net7),
.q (net97)
);
and_cell gate50 (
.a (net5),
.b (net95),
.out (net96)
);
dff_cell flipflop26 (
.d (net98),
.clk (net7),
.q (net99)
);
and_cell gate51 (
.a (net5),
.b (net97),
.out (net98)
);
and_cell gate52 (
.a (net5),
.b (net84),
.out (net82)
);
dff_cell flipflop27 (
.d (net100),
.clk (net7),
.q (net101)
);
and_cell gate53 (
.a (net5),
.b (net99),
.out (net100)
);
dff_cell flipflop28 (
.d (net102),
.clk (net7),
.q (net103)
);
and_cell gate54 (
.a (net5),
.b (net101),
.out (net102)
);
dff_cell flipflop29 (
.d (net104),
.clk (net7),
.q (net105)
);
and_cell gate55 (
.a (net5),
.b (net103),
.out (net104)
);
dff_cell flipflop30 (
.d (net106),
.clk (net7),
.q (net107)
);
and_cell gate56 (
.a (net5),
.b (net108),
.out (net106)
);
dff_cell flipflop31 (
.d (net109),
.clk (net7),
.q (net110)
);
and_cell gate57 (
.a (net5),
.b (net107),
.out (net109)
);
dff_cell flipflop32 (
.d (net111),
.clk (net7),
.q (net112)
);
and_cell gate58 (
.a (net5),
.b (net110),
.out (net111)
);
dff_cell flipflop33 (
.d (net113),
.clk (net7),
.q (net11)
);
and_cell gate59 (
.a (net5),
.b (net112),
.out (net113)
);
nand_cell gate60 (
.a (net78),
.b (net114),
.out (net115)
);
nand_cell gate61 (
.a (net114),
.b (net90),
.out (net116)
);
nand_cell gate62 (
.a (net115),
.b (net116),
.out (net93)
);
nand_cell gate63 (
.a (net78),
.b (net90),
.out (net114)
);
nand_cell gate64 (
.a (net78),
.b (net117),
.out (net118)
);
nand_cell gate65 (
.a (net117),
.b (net105),
.out (net119)
);
nand_cell gate66 (
.a (net118),
.b (net119),
.out (net108)
);
nand_cell gate67 (
.a (net78),
.b (net105),
.out (net117)
);
and_cell gate68 (
.a (net11),
.b (net8),
.out (net78)
);
nand_cell gate27 (
.a (net10),
.b (net136),
.out (net137)
);
nand_cell gate28 (
.a (net136),
.b (net2),
.out (net138)
);
nand_cell gate29 (
.a (net137),
.b (net138),
.out (net139)
);
nand_cell gate30 (
.a (net10),
.b (net2),
.out (net136)
);
dff_cell flipflop34 (
.d (net140),
.clk (net3),
.q (net10)
);
nand_cell gate69 (
.a (net12),
.b (net141),
.out (net142)
);
nand_cell gate70 (
.a (net141),
.b (net6),
.out (net143)
);
nand_cell gate71 (
.a (net142),
.b (net143),
.out (net144)
);
nand_cell gate72 (
.a (net12),
.b (net6),
.out (net141)
);
dff_cell flipflop35 (
.d (net144),
.clk (net7),
.q (net12)
);
and_cell gate73 (
.a (net1),
.b (net139),
.out (net140)
);
endmodule |
module voice(
input clk,
input addr,
input write_data,
input [5:0] data,
output out
);
reg [5:0] max_clk_div_counter;
always @(posedge clk) begin
if (write_data & ~addr)
max_clk_div_counter <= data;
end
reg [5:0] clk_div_counter;
wire tick = clk_div_counter >= max_clk_div_counter;
always @(posedge clk) begin
if (tick) begin
clk_div_counter <= 6'h00;
end
else begin
clk_div_counter <= clk_div_counter + 6'h01;
end
end
reg [3:0] lfsr_tap_mask;
always @(posedge clk) begin
if (write_data & addr)
lfsr_tap_mask <= data[3:0];
end
reg [9:0] lfsr;
wire tap1 = lfsr[1] & lfsr_tap_mask[0];
wire tap4 = lfsr[4] & lfsr_tap_mask[1];
wire tap6 = lfsr[6] & lfsr_tap_mask[2];
wire tap9 = lfsr[9] & lfsr_tap_mask[3];
always @(posedge clk) begin
if (tick) begin
if (lfsr == 10'h00) begin
lfsr <= 10'h01;
end
else begin
lfsr <= {lfsr[8:0], tap1 ^ tap4 ^ tap6 ^ tap9};
end
end
end
assign out = lfsr[0];
endmodule |
module mixer(
input clk,
input write_data,
input [5:0] data,
input voice0_out,
input voice1_out,
output [3:0] out
);
reg [5:0] voice_volumes;
always @(posedge clk) begin
if (write_data)
voice_volumes <= data;
end
wire [2:0] voice0_volume = voice_volumes[2:0];
wire [2:0] voice1_volume = voice_volumes[5:3];
wire [2:0] scaled_voice0_out = voice0_out ? voice0_volume : 3'h00;
wire [2:0] scaled_voice1_out = voice1_out ? voice1_volume : 3'h00;
assign out = scaled_voice0_out + scaled_voice1_out;
endmodule |
module yupferris_bitslam(
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire addr_data_sel = io_in[1];
wire write_addr = ~addr_data_sel;
wire write_data = addr_data_sel;
wire [5:0] addr_data = io_in[7:2];
wire [5:0] data = addr_data;
reg [2:0] addr;
always @(posedge clk) begin
if (write_addr)
addr <= addr_data[2:0];
end
wire voice_select = addr[1];
wire mixer_select = addr[2];
wire voice0_select = ~voice_select & ~mixer_select;
wire voice1_select = voice_select & ~mixer_select;
wire voice0_out;
voice voice0(
.clk(clk),
.addr(addr[0]),
.write_data(write_data & voice0_select),
.data(data),
.out(voice0_out)
);
wire voice1_out;
voice voice1(
.clk(clk),
.addr(addr[0]),
.write_data(write_data & voice1_select),
.data(data),
.out(voice1_out)
);
wire [3:0] mixer_out;
mixer mixer(
.clk(clk),
.write_data(write_data & mixer_select),
.data(data),
.voice0_out(voice0_out),
.voice1_out(voice1_out),
.out(mixer_out)
);
assign io_out = {4'h00, mixer_out};
endmodule |
module chrisruk_matrix #( parameter MAX_COUNT = 1000 ) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0]; // Input clock line
wire reset = io_in[1]; // Input reset line
wire digit1 = io_in[2]; // Digit to display
reg [0:0] digit1_cache; // Cache of first digit
reg [0:0] digit2_cache; // Cache of second digit
reg [0:0] clock_1; // Clock output
reg [0:0] strip_1; // Data output
reg [0:0] first; // Whether this is first digit displayed, if so display 'blank' character
assign io_out[0] = clock_1; // Clock output for LED matrix
assign io_out[1] = strip_1; // Data output for LED matrix
reg [0:40-1] fonts [0:2-1]; // Font array
reg [11:0] counter1; // Count where we are in bit pattern
reg [2:0] shift; // Amount to left shift character
reg [3-1:0] rowno; // Row number in 8x8 matrix
reg [6-1:0] idx; // Bit index within colour register
reg [6-1:0] pidx; // Bit index within character, we apply processing on top of this
// value to create the bitidx value
reg [6-1:0] bitidx; // Index of bit we are within of character
reg [0:32-1] ledreg1; // Colour 1
reg [0:32-1] ledreg2; // Colour 2
reg [0:64-1] display; // Display buffer
`ifdef FPGA
// Generate 6kHz clock from input 12MHz clock
reg [0:0] clk2;
integer counter;
reg [0:0] resetflag;
initial begin
first <= 1; // For FPGA for some reason need to have this here too, otherwise we get duplicate first value
clk2 <= 0;
counter <= 0;
resetflag <= 1; // Reset flag, only used by FPGA
end
always @(posedge clk) begin
if (counter == 2000) begin // Create 6kHz clock
clk2 <= ~clk2;
counter <= 0;
end else begin
counter <= counter + 1;
end
end
always @(posedge clk2) begin
if (reset || resetflag) begin
resetflag <= 0;
`else
always @(posedge clk) begin
if (reset) begin
`endif
// Setup variables
shift <= 0;
counter1 <= 0;
idx <= 0;
bitidx <= 0;
pidx <= 0;
strip_1 <= 0;
clock_1 <= 0;
ledreg1 <= 32'hf0000f00; // Number colour
ledreg2 <= 32'hf0070000; // Background colour
fonts[0] <= 40'h18_24_24_24_18; // 0
fonts[1] <= 40'h18_28_08_08_3e; // 1
digit1_cache <= 0;
digit2_cache <= digit1;
first <= 1;
end else begin
clock_1 <= ~clock_1 ;
if (clock_1 == 1) begin
if (counter1 < 32) begin
strip_1 <= 0;
if(counter1 == 1) begin
// Provided we're not displaying first digit in scrolling marquee pattern, display digit
// and shift each time
if(!first) begin
display <= {16'b0,
fonts[digit1_cache][32:39] << shift,
fonts[digit1_cache][24:31] << shift,
fonts[digit1_cache][16:23] << shift,
fonts[digit1_cache][8:15] << shift,
fonts[digit1_cache][0:7] << shift,
8'b0};
end else begin
display <= 0;
end
end else if(counter1 == 2) begin
// Display part of next digit too
display <= display | {16'b0,
fonts[digit2_cache][32:39] >> 8 - shift,
fonts[digit2_cache][24:31] >> 8 - shift,
fonts[digit2_cache][16:23] >> 8 - shift,
fonts[digit2_cache][8:15] >> 8 - shift,
fonts[digit2_cache][0:7] >> 8 - shift,
8'b0};
end
counter1 <= counter1 + 1;
end else if (counter1 < 32 + (32 * (8*8))) begin
rowno = pidx / 8;
// Flip bit order if even row, as matrix of LEDs
// is in a 'snake' like pattern
if(rowno % 2 == 0) begin
bitidx = ((rowno * 16) + 8) - 1 - pidx;
end else begin
bitidx = pidx;
end
// Extract bit from display buffer
if (display[bitidx] == 1) begin
strip_1 <= ledreg1[idx];
end else begin
strip_1 <= ledreg2[idx];
end
if (idx == 31) begin
idx <= 0;
pidx <= pidx + 1;
end else begin
idx <= idx + 1;
end
counter1 <= counter1 + 1;
end else if (counter1 < 32 + (32 * (8*8)) + 32 + 32) begin
// Need zeros at end of pattern
strip_1 <= 0;
counter1 <= counter1 + 1;
end else begin
counter1 <= 0;
pidx <= 0;
idx <= 0;
if (shift == 7) begin
digit1_cache <= digit2_cache;
digit2_cache <= digit1; // Grab next digit to be displayed from input pin
shift <= 0;
first <= 0;
end else begin
// Need to wrap back to first letter
shift <= shift + 1;
end
end
end
end
end
endmodule |
module gregdavill_serv_top(
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[7];
wire data = io_in[4];
wire scan_select = io_in[5];
wire latch_enable = io_in[6];
wire serv_clk = io_in[7];
wire timer_irq;
parameter reset_strategy = "MINI";
parameter sim = 0;
parameter with_csr = 0;
parameter [0:0] compress = 0;
parameter [0:0] align = 0;
wire [4+with_csr:0] wreg0;
wire [4+with_csr:0] wreg1;
wire [4+with_csr:0] rreg0;
wire [4+with_csr:0] rreg1;
wire rf_wreq;
wire rf_rreq;
wire wen0;
wire wen1;
wire wdata0;
wire wdata1;
wire rf_ready;
wire rdata0;
wire rdata1;
wire [31:0] wb_ibus_adr;
wire [31:0] wb_ibus_rdt;
wire wb_ibus_cyc;
wire wb_ibus_ack;
wire [31:0] wb_dbus_adr;
wire [31:0] wb_dbus_dat;
wire [3:0] wb_dbus_sel;
wire [31:0] wb_dbus_rdt;
wire wb_dbus_we;
wire wb_dbus_cyc;
wire wb_dbus_ack;
wire [31:0] wb_dmem_adr;
wire [31:0] wb_dmem_dat;
wire [3:0] wb_dmem_sel;
wire [31:0] wb_dmem_rdt;
wire wb_dmem_we;
wire wb_dmem_cyc;
wire wb_dmem_ack;
wire [31:0] wb_mem_adr;
wire [31:0] wb_mem_dat;
wire [3:0] wb_mem_sel;
wire [31:0] wb_mem_rdt;
wire wb_mem_we;
wire wb_mem_cyc;
wire wb_mem_ack;
wire wb_gpio_dat;
wire wb_gpio_we;
wire wb_gpio_cyc;
wire wb_gpio_rdt;
servant_arbiter u_arbiter (
.i_wb_cpu_dbus_adr (wb_dbus_adr),
.i_wb_cpu_dbus_dat (wb_dbus_dat),
.i_wb_cpu_dbus_sel (wb_dbus_sel),
.i_wb_cpu_dbus_we (wb_dbus_we ),
.i_wb_cpu_dbus_cyc (wb_dbus_cyc),
.o_wb_cpu_dbus_rdt (wb_dbus_rdt),
.o_wb_cpu_dbus_ack (wb_dbus_ack),
.i_wb_cpu_ibus_adr (wb_ibus_adr),
.i_wb_cpu_ibus_cyc (wb_ibus_cyc),
.o_wb_cpu_ibus_rdt (wb_ibus_rdt),
.o_wb_cpu_ibus_ack (wb_ibus_ack),
.o_wb_cpu_adr (wb_mem_adr),
.o_wb_cpu_dat (wb_mem_dat),
.o_wb_cpu_sel (wb_mem_sel),
.o_wb_cpu_we (wb_mem_we ),
.o_wb_cpu_cyc (wb_mem_cyc),
.i_wb_cpu_rdt (wb_mem_rdt),
.i_wb_cpu_ack (wb_mem_ack)
);
serv_top #(
.RESET_PC (32'h0000_0000),
.PRE_REGISTER(1),
.RESET_STRATEGY (reset_strategy),
.WITH_CSR (with_csr),
.COMPRESSED(compress),
.ALIGN(align))
cpu
(
.clk (serv_clk),
.i_rst (reset),
.i_timer_irq (timer_irq),
.o_rf_rreq (rf_rreq),
.o_rf_wreq (rf_wreq),
.i_rf_ready (rf_ready),
.o_wreg0 (wreg0),
.o_wreg1 (wreg1),
.o_wen0 (wen0),
.o_wen1 (wen1),
.o_wdata0 (wdata0),
.o_wdata1 (wdata1),
.o_rreg0 (rreg0),
.o_rreg1 (rreg1),
.i_rdata0 (rdata0),
.i_rdata1 (rdata1),
.o_ibus_adr (wb_ibus_adr),
.o_ibus_cyc (wb_ibus_cyc),
.i_ibus_rdt (wb_ibus_rdt),
.i_ibus_ack (wb_ibus_ack),
.o_dbus_adr (wb_dbus_adr),
.o_dbus_dat (wb_dbus_dat),
.o_dbus_sel (wb_dbus_sel),
.o_dbus_we (wb_dbus_we),
.o_dbus_cyc (wb_dbus_cyc),
.i_dbus_rdt (wb_dbus_rdt),
.i_dbus_ack (wb_dbus_ack)
);
scanchain_local #(
.SCAN_LENGTH(96))
u_scanchain_local
(
// Inputs from TinyTapeout scanchain to our internal scanchain
.clk_in (clk),
.data_in (data),
.scan_select_in (scan_select),
// Pass all signals out from our internal scanchain, only really need data
.clk_out (io_out[0]),
.data_out (io_out[1]),
.scan_select_out (io_out[2]),
// data
.module_data_out ({
// Bus interface
wb_mem_adr[31:0], // 32
wb_mem_dat, // 32
wb_mem_sel, // 4
wb_mem_we, // 1
wb_mem_cyc, // 1
// RF interface
rf_wreq, // 1
rf_rreq, // 1
wreg0, // 5
wreg1, // 5
wen0, // 1
wen1, // 1
wdata0, // 1
wdata1, // 1
rreg0, // 5
rreg1}), // 5
.module_data_in ({
// Bus interface
wb_mem_rdt, // 32
wb_mem_ack, // 1
timer_irq, // 1
rf_ready, // 1
rdata0, // 1
rdata1}) // 1
);
endmodule |
module user_module_348195845106041428(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4;
wire net5;
wire net6 = 1'b1;
wire net7;
wire net8;
wire net9;
wire net10;
wire net11 = 1'b0;
wire net12 = 1'b0;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
assign io_out[0] = net4;
assign io_out[1] = net5;
or_cell gate2 (
);
nand_cell gate4 (
.a (net7),
.b (net1),
.out (net8)
);
not_cell gate5 (
.in (net7),
.out (net4)
);
buffer_cell gate6 (
.in (net9),
.out (net10)
);
mux_cell mux1 (
);
dff_cell flipflop1 (
);
nand_cell nand1 (
.a (net8),
.b (net13),
.out (net14)
);
nand_cell nand2 (
.a (net14),
.b (net10),
.out (net13)
);
nand_cell nand3 (
.a (net10),
.b (net15),
.out (net16)
);
nand_cell nand4 (
.a (net16),
.b (net17),
.out (net15)
);
nand_cell nand5 (
.a (net2),
.b (net5),
.out (net17)
);
and_cell and1 (
.a (net8),
.b (net14),
.out (net18)
);
nand_cell nand6 (
.a (net18),
.b (net10),
.out (net7)
);
nand_cell nand7 (
.a (net14),
.b (net8),
.out (net19)
);
nand_cell nand8 (
.a (net17),
.b (net15),
.out (net20)
);
nand_cell nand9 (
.a (net19),
.b (net19),
.out (net21)
);
nand_cell nand10 (
.a (net20),
.b (net20),
.out (net22)
);
nand_cell nand11 (
.a (net21),
.b (net22),
.out (net23)
);
nand_cell nand12 (
.a (net23),
.b (net3),
.out (net24)
);
not_cell not1 (
.in (net24),
.out (net9)
);
and_cell and2 (
.a (net10),
.b (net15),
.out (net25)
);
nand_cell nand13 (
.a (net25),
.b (net17),
.out (net5)
);
endmodule |
module secretFile (
input [7:0] io_in,
output reg [7:0] io_out
);
wire clk = io_in[0];
reg [8:0] index;
always@(posedge clk) begin
// if(index == 9'd487)
// index <= 9'd0;
// else
index <= index + 1'd1;
case(index)
9'b000000000: io_out <= 8'b01000111;
9'b000000001: io_out <= 8'b01001001;
9'b000000010: io_out <= 8'b01000110;
9'b000000011: io_out <= 8'b00111000;
9'b000000100: io_out <= 8'b00111001;
9'b000000101: io_out <= 8'b01100001;
9'b000000110: io_out <= 8'b00100000;
9'b000001000: io_out <= 8'b00100000;
9'b000001010: io_out <= 8'b11110001;
9'b000001101: io_out <= 8'b01000001;
9'b000001110: io_out <= 8'b00111000;
9'b000001111: io_out <= 8'b00101110;
9'b000010000: io_out <= 8'b10010111;
9'b000010001: io_out <= 8'b01101000;
9'b000010010: io_out <= 8'b01100110;
9'b000010011: io_out <= 8'b10100001;
9'b000010100: io_out <= 8'b10100010;
9'b000010101: io_out <= 8'b10110010;
9'b000011001: io_out <= 8'b00100001;
9'b000011010: io_out <= 8'b11111111;
9'b000011011: io_out <= 8'b00001011;
9'b000011100: io_out <= 8'b01001110;
9'b000011101: io_out <= 8'b01000101;
9'b000011110: io_out <= 8'b01010100;
9'b000011111: io_out <= 8'b01010011;
9'b000100000: io_out <= 8'b01000011;
9'b000100001: io_out <= 8'b01000001;
9'b000100010: io_out <= 8'b01010000;
9'b000100011: io_out <= 8'b01000101;
9'b000100100: io_out <= 8'b00110010;
9'b000100101: io_out <= 8'b00101110;
9'b000100110: io_out <= 8'b00110000;
9'b000100111: io_out <= 8'b00000011;
9'b000101000: io_out <= 8'b00000001;
9'b000101100: io_out <= 8'b00100001;
9'b000101101: io_out <= 8'b11111001;
9'b000101110: io_out <= 8'b00000100;
9'b000101111: io_out <= 8'b00000100;
9'b000110000: io_out <= 8'b00011110;
9'b000110010: io_out <= 8'b11111111;
9'b000110100: io_out <= 8'b00101100;
9'b000111001: io_out <= 8'b00100000;
9'b000111011: io_out <= 8'b00100000;
9'b000111110: io_out <= 8'b00000010;
9'b000111111: io_out <= 8'b01110001;
9'b001000000: io_out <= 8'b10010100;
9'b001000001: io_out <= 8'b10001111;
9'b001000010: io_out <= 8'b10101001;
9'b001000011: io_out <= 8'b11001011;
9'b001000100: io_out <= 8'b11101101;
9'b001000101: io_out <= 8'b00001111;
9'b001000110: io_out <= 8'b10100011;
9'b001000111: io_out <= 8'b10011100;
9'b001001000: io_out <= 8'b00110100;
9'b001001001: io_out <= 8'b10000001;
9'b001001010: io_out <= 8'b00001011;
9'b001001011: io_out <= 8'b01000010;
9'b001001100: io_out <= 8'b01110101;
9'b001001101: io_out <= 8'b00011000;
9'b001001110: io_out <= 8'b11101111;
9'b001001111: io_out <= 8'b00010101;
9'b001010000: io_out <= 8'b01100100;
9'b001010001: io_out <= 8'b01000001;
9'b001010010: io_out <= 8'b00001000;
9'b001010011: io_out <= 8'b01111100;
9'b001010100: io_out <= 8'b11001010;
9'b001010101: io_out <= 8'b10001000;
9'b001010110: io_out <= 8'b10001110;
9'b001010111: io_out <= 8'b11100110;
9'b001011000: io_out <= 8'b10011001;
9'b001011001: io_out <= 8'b01101010;
9'b001011010: io_out <= 8'b00101011;
9'b001011011: io_out <= 8'b11010010;
9'b001011100: io_out <= 8'b10111010;
9'b001011101: io_out <= 8'b10101111;
9'b001011110: io_out <= 8'b00010001;
9'b001011111: io_out <= 8'b11001111;
9'b001100000: io_out <= 8'b01000111;
9'b001100001: io_out <= 8'b01101011;
9'b001100010: io_out <= 8'b11011111;
9'b001100011: io_out <= 8'b01101001;
9'b001100100: io_out <= 8'b10101110;
9'b001100101: io_out <= 8'b10101011;
9'b001100110: io_out <= 8'b01111100;
9'b001100111: io_out <= 8'b11101100;
9'b001101000: io_out <= 8'b00110011;
9'b001101001: io_out <= 8'b10000101;
9'b001101010: io_out <= 8'b01110000;
9'b001101011: io_out <= 8'b00011101;
9'b001101100: io_out <= 8'b10011001;
9'b001101101: io_out <= 8'b10000100;
9'b001101110: io_out <= 8'b10010100;
9'b001101111: io_out <= 8'b00010001;
9'b001110000: io_out <= 8'b11111000;
9'b001110001: io_out <= 8'b00111010;
9'b001110010: io_out <= 8'b00010111;
9'b001110011: io_out <= 8'b01100011;
9'b001110100: io_out <= 8'b01100011;
9'b001110101: io_out <= 8'b01010100;
9'b001110110: io_out <= 8'b01010100;
9'b001110111: io_out <= 8'b11010010;
9'b001111000: io_out <= 8'b10011000;
9'b001111001: io_out <= 8'b01001001;
9'b001111010: io_out <= 8'b00001000;
9'b001111011: io_out <= 8'b10110101;
9'b001111100: io_out <= 8'b00001001;
9'b001111101: io_out <= 8'b10111101;
9'b001111110: io_out <= 8'b01000110;
9'b001111111: io_out <= 8'b10101110;
9'b010000000: io_out <= 8'b00100010;
9'b010000001: io_out <= 8'b01101110;
9'b010000010: io_out <= 8'b11001001;
9'b010000011: io_out <= 8'b01111010;
9'b010000100: io_out <= 8'b11001101;
9'b010000101: io_out <= 8'b01101010;
9'b010000110: io_out <= 8'b11000001;
9'b010000111: io_out <= 8'b01010100;
9'b010001000: io_out <= 8'b00010010;
9'b010001001: io_out <= 8'b10001010;
9'b010001010: io_out <= 8'b10111001;
9'b010001011: io_out <= 8'b11100101;
9'b010001100: io_out <= 8'b00001110;
9'b010001101: io_out <= 8'b11000101;
9'b010001110: io_out <= 8'b10010111;
9'b010001111: io_out <= 8'b10110100;
9'b010010000: io_out <= 8'b11110111;
9'b010010001: io_out <= 8'b11011100;
9'b010010010: io_out <= 8'b01110001;
9'b010010011: io_out <= 8'b10111111;
9'b010010100: io_out <= 8'b10010001;
9'b010010101: io_out <= 8'b01001101;
9'b010010110: io_out <= 8'b10110010;
9'b010010111: io_out <= 8'b10010111;
9'b010011000: io_out <= 8'b11111011;
9'b010011001: io_out <= 8'b01100000;
9'b010011010: io_out <= 8'b11011111;
9'b010011011: io_out <= 8'b10011001;
9'b010011100: io_out <= 8'b11001110;
9'b010011101: io_out <= 8'b00000100;
9'b010011110: io_out <= 8'b01111100;
9'b010011111: io_out <= 8'b10001111;
9'b010100000: io_out <= 8'b11110110;
9'b010100001: io_out <= 8'b11110100;
9'b010100010: io_out <= 8'b00000111;
9'b010100011: io_out <= 8'b01011000;
9'b010100100: io_out <= 8'b11100111;
9'b010100101: io_out <= 8'b10100000;
9'b010100110: io_out <= 8'b00000111;
9'b010100111: io_out <= 8'b11011000;
9'b010101000: io_out <= 8'b01110111;
9'b010101001: io_out <= 8'b01000010;
9'b010101010: io_out <= 8'b01011000;
9'b010101011: io_out <= 8'b01111000;
9'b010101100: io_out <= 8'b10100100;
9'b010101101: io_out <= 8'b11000110;
9'b010101110: io_out <= 8'b11010111;
9'b010101111: io_out <= 8'b01010000;
9'b010110010: io_out <= 8'b00100001;
9'b010110011: io_out <= 8'b11111001;
9'b010110100: io_out <= 8'b00000100;
9'b010110101: io_out <= 8'b00000101;
9'b010110110: io_out <= 8'b00011110;
9'b010111000: io_out <= 8'b00000011;
9'b010111010: io_out <= 8'b00101100;
9'b010111011: io_out <= 8'b00000101;
9'b010111101: io_out <= 8'b00000011;
9'b010111111: io_out <= 8'b00011000;
9'b011000001: io_out <= 8'b00011101;
9'b011000100: io_out <= 8'b00000010;
9'b011000101: io_out <= 8'b01100010;
9'b011000110: io_out <= 8'b10010100;
9'b011000111: io_out <= 8'b10001111;
9'b011001000: io_out <= 8'b00010010;
9'b011001010: io_out <= 8'b11101001;
9'b011001011: io_out <= 8'b10101111;
9'b011001100: io_out <= 8'b00011000;
9'b011001101: io_out <= 8'b00001011;
9'b011001110: io_out <= 8'b10110000;
9'b011001111: io_out <= 8'b00001010;
9'b011010000: io_out <= 8'b10111001;
9'b011010001: io_out <= 8'b10011010;
9'b011010010: io_out <= 8'b01111101;
9'b011010011: io_out <= 8'b00100000;
9'b011010100: io_out <= 8'b01111000;
9'b011010101: io_out <= 8'b10111111;
9'b011010110: io_out <= 8'b00111001;
9'b011010111: io_out <= 8'b11011111;
9'b011011000: io_out <= 8'b00011000;
9'b011011001: io_out <= 8'b10001010;
9'b011011010: io_out <= 8'b00100011;
9'b011011011: io_out <= 8'b01010101;
9'b011011100: io_out <= 8'b00100010;
9'b011011101: io_out <= 8'b00100111;
9'b011011110: io_out <= 8'b10011010;
9'b011011111: io_out <= 8'b00011010;
9'b011100000: io_out <= 8'b01101011;
9'b011100001: io_out <= 8'b10101011;
9'b011100010: io_out <= 8'b01111110;
9'b011100011: io_out <= 8'b01110000;
9'b011100100: io_out <= 8'b00101100;
9'b011100101: io_out <= 8'b11001111;
9'b011100110: io_out <= 8'b11101110;
9'b011100111: io_out <= 8'b01101001;
9'b011101000: io_out <= 8'b11001011;
9'b011101001: io_out <= 8'b01011001;
9'b011101010: io_out <= 8'b11000111;
9'b011101011: io_out <= 8'b01010110;
9'b011101100: io_out <= 8'b10010100;
9'b011101101: io_out <= 8'b00101110;
9'b011101110: io_out <= 8'b11000001;
9'b011101111: io_out <= 8'b11111000;
9'b011110000: io_out <= 8'b01111110;
9'b011110001: io_out <= 8'b10100000;
9'b011110010: io_out <= 8'b01100000;
9'b011110011: io_out <= 8'b00010000;
9'b011110100: io_out <= 8'b10010010;
9'b011110101: io_out <= 8'b00011001;
9'b011110110: io_out <= 8'b00011001;
9'b011110111: io_out <= 8'b10001111;
9'b011111000: io_out <= 8'b10001001;
9'b011111001: io_out <= 8'b00011101;
9'b011111010: io_out <= 8'b11001111;
9'b011111011: io_out <= 8'b10110011;
9'b011111100: io_out <= 8'b10010100;
9'b011111101: io_out <= 8'b10001000;
9'b011111110: io_out <= 8'b10001100;
9'b011111111: io_out <= 8'b10011111;
9'b100000000: io_out <= 8'b00101000;
9'b100000001: io_out <= 8'b01100011;
9'b100000010: io_out <= 8'b00011010;
9'b100000011: io_out <= 8'b01110100;
9'b100000100: io_out <= 8'b01000110;
9'b100000101: io_out <= 8'b10110001;
9'b100000110: io_out <= 8'b01011001;
9'b100000111: io_out <= 8'b11101011;
9'b100001000: io_out <= 8'b10100100;
9'b100001001: io_out <= 8'b10111001;
9'b100001010: io_out <= 8'b11010100;
9'b100001011: io_out <= 8'b01010010;
9'b100001100: io_out <= 8'b11000001;
9'b100001101: io_out <= 8'b01011101;
9'b100001110: io_out <= 8'b11101111;
9'b100001111: io_out <= 8'b00110101;
9'b100010000: io_out <= 8'b01100001;
9'b100010001: io_out <= 8'b10110110;
9'b100010010: io_out <= 8'b00110110;
9'b100010011: io_out <= 8'b11000101;
9'b100010100: io_out <= 8'b01101001;
9'b100010101: io_out <= 8'b01110010;
9'b100010110: io_out <= 8'b11011010;
9'b100010111: io_out <= 8'b11101000;
9'b100011000: io_out <= 8'b01111110;
9'b100011001: io_out <= 8'b01001011;
9'b100011010: io_out <= 8'b00001111;
9'b100011011: io_out <= 8'b01010101;
9'b100011100: io_out <= 8'b11111001;
9'b100011101: io_out <= 8'b11111100;
9'b100011110: io_out <= 8'b11000110;
9'b100011111: io_out <= 8'b00110110;
9'b100100000: io_out <= 8'b11010011;
9'b100100001: io_out <= 8'b10101000;
9'b100100010: io_out <= 8'b11100110;
9'b100100011: io_out <= 8'b01011110;
9'b100100100: io_out <= 8'b00111110;
9'b100100101: io_out <= 8'b11011111;
9'b100100110: io_out <= 8'b01010001;
9'b100101001: io_out <= 8'b00100001;
9'b100101010: io_out <= 8'b11111001;
9'b100101011: io_out <= 8'b00000100;
9'b100101100: io_out <= 8'b00000101;
9'b100101101: io_out <= 8'b00011110;
9'b100101111: io_out <= 8'b00000011;
9'b100110001: io_out <= 8'b00101100;
9'b100110110: io_out <= 8'b00011101;
9'b100111000: io_out <= 8'b00100000;
9'b100111011: io_out <= 8'b00000010;
9'b100111100: io_out <= 8'b01111101;
9'b100111101: io_out <= 8'b10010100;
9'b100111110: io_out <= 8'b10001111;
9'b100111111: io_out <= 8'b00010110;
9'b101000000: io_out <= 8'b00011011;
9'b101000001: io_out <= 8'b11101001;
9'b101000010: io_out <= 8'b11101111;
9'b101000011: io_out <= 8'b00000010;
9'b101000100: io_out <= 8'b10011000;
9'b101000101: io_out <= 8'b10100000;
9'b101000110: io_out <= 8'b11000001;
9'b101000111: io_out <= 8'b10001011;
9'b101001000: io_out <= 8'b00100100;
9'b101001001: io_out <= 8'b10011101;
9'b101001010: io_out <= 8'b10111000;
9'b101001011: io_out <= 8'b10001011;
9'b101001100: io_out <= 8'b11001101;
9'b101001101: io_out <= 8'b01111000;
9'b101001110: io_out <= 8'b10010111;
9'b101001111: io_out <= 8'b11000110;
9'b101010000: io_out <= 8'b00101100;
9'b101010001: io_out <= 8'b00100010;
9'b101010010: io_out <= 8'b01000100;
9'b101010011: io_out <= 8'b10010101;
9'b101010100: io_out <= 8'b11010110;
9'b101010101: io_out <= 8'b10011001;
9'b101010110: io_out <= 8'b10010000;
9'b101010111: io_out <= 8'b00100101;
9'b101011000: io_out <= 8'b00011011;
9'b101011001: io_out <= 8'b10101001;
9'b101011010: io_out <= 8'b00100110;
9'b101011011: io_out <= 8'b11011100;
9'b101011100: io_out <= 8'b11001010;
9'b101011101: io_out <= 8'b01110100;
9'b101011110: io_out <= 8'b10101101;
9'b101011111: io_out <= 8'b11011110;
9'b101100000: io_out <= 8'b10000111;
9'b101100001: io_out <= 8'b10111100;
9'b101100010: io_out <= 8'b11011110;
9'b101100011: io_out <= 8'b10010010;
9'b101100100: io_out <= 8'b01001101;
9'b101100101: io_out <= 8'b11010011;
9'b101100110: io_out <= 8'b01001100;
9'b101100111: io_out <= 8'b01111000;
9'b101101000: io_out <= 8'b01000011;
9'b101101001: io_out <= 8'b10001111;
9'b101101010: io_out <= 8'b01110000;
9'b101101011: io_out <= 8'b00100011;
9'b101101100: io_out <= 8'b00110000;
9'b101101101: io_out <= 8'b00101101;
9'b101101110: io_out <= 8'b01010010;
9'b101101111: io_out <= 8'b10011101;
9'b101110000: io_out <= 8'b00001101;
9'b101110001: io_out <= 8'b00110010;
9'b101110010: io_out <= 8'b10011001;
9'b101110011: io_out <= 8'b00010100;
9'b101110100: io_out <= 8'b11110110;
9'b101110101: io_out <= 8'b00100010;
9'b101110110: io_out <= 8'b11001110;
9'b101110111: io_out <= 8'b11010100;
9'b101111000: io_out <= 8'b10110010;
9'b101111001: io_out <= 8'b11110010;
9'b101111010: io_out <= 8'b01000100;
9'b101111011: io_out <= 8'b01010101;
9'b101111100: io_out <= 8'b10101101;
9'b101111101: io_out <= 8'b11000011;
9'b101111110: io_out <= 8'b11101100;
9'b101111111: io_out <= 8'b01100011;
9'b110000000: io_out <= 8'b11001011;
9'b110000001: io_out <= 8'b00000101;
9'b110000010: io_out <= 8'b01111100;
9'b110000011: io_out <= 8'b00101000;
9'b110000100: io_out <= 8'b00100011;
9'b110000101: io_out <= 8'b11110000;
9'b110000110: io_out <= 8'b11110000;
9'b110000111: io_out <= 8'b01001000;
9'b110001000: io_out <= 8'b10000110;
9'b110001001: io_out <= 8'b10100000;
9'b110001010: io_out <= 8'b10101011;
9'b110001011: io_out <= 8'b01101011;
9'b110001100: io_out <= 8'b10110001;
9'b110001101: io_out <= 8'b11010110;
9'b110001110: io_out <= 8'b01101100;
9'b110001111: io_out <= 8'b10111110;
9'b110010000: io_out <= 8'b11000000;
9'b110010001: io_out <= 8'b11100001;
9'b110010010: io_out <= 8'b11010011;
9'b110010011: io_out <= 8'b11000011;
9'b110010100: io_out <= 8'b00011100;
9'b110010101: io_out <= 8'b10111011;
9'b110010110: io_out <= 8'b00001101;
9'b110010111: io_out <= 8'b00100001;
9'b110011000: io_out <= 8'b11100110;
9'b110011001: io_out <= 8'b10001100;
9'b110011010: io_out <= 8'b11111100;
9'b110011011: io_out <= 8'b01001100;
9'b110011100: io_out <= 8'b11000001;
9'b110011101: io_out <= 8'b01110111;
9'b110011110: io_out <= 8'b11000101;
9'b110011111: io_out <= 8'b00110110;
9'b110100000: io_out <= 8'b01110101;
9'b110100001: io_out <= 8'b11010111;
9'b110100010: io_out <= 8'b01110110;
9'b110100011: io_out <= 8'b00000110;
9'b110100100: io_out <= 8'b00000101;
9'b110100101: io_out <= 8'b01111000;
9'b110100110: io_out <= 8'b00000111;
9'b110100111: io_out <= 8'b10100110;
9'b110101000: io_out <= 8'b10110111;
9'b110101001: io_out <= 8'b10100011;
9'b110101010: io_out <= 8'b01001000;
9'b110101011: io_out <= 8'b10010110;
9'b110101100: io_out <= 8'b11110011;
9'b110101101: io_out <= 8'b11100101;
9'b110101110: io_out <= 8'b01111000;
9'b110101111: io_out <= 8'b11100010;
9'b110110000: io_out <= 8'b01011000;
9'b110110001: io_out <= 8'b00100001;
9'b110110010: io_out <= 8'b01000010;
9'b110110011: io_out <= 8'b01011001;
9'b110110100: io_out <= 8'b01000111;
9'b110110101: io_out <= 8'b11100101;
9'b110110110: io_out <= 8'b10001000;
9'b110110111: io_out <= 8'b01101001;
9'b110111000: io_out <= 8'b01010000;
9'b110111011: io_out <= 8'b00111011;
9'b110111100: io_out <= 8'b01100010;
9'b110111101: io_out <= 8'b01101001;
9'b110111110: io_out <= 8'b01110100;
9'b110111111: io_out <= 8'b01101100;
9'b111000000: io_out <= 8'b01110101;
9'b111000001: io_out <= 8'b01101110;
9'b111000010: io_out <= 8'b01101001;
default: io_out <= 8'b00000000;
endcase;
end
endmodule |
module tiny_fft (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire wrEn = io_in[2];
wire [3:0] data_in = io_in[7:4];
reg [1:0] wrIdx;
reg [2:0] rdIdx;
reg signed [3:0] input_reg[0:3];
assign io_out[0] = (rdIdx == 0) ? 1'b1 : 1'b0;
// Signal high when output value is real
assign io_out[1] = ~rdIdx[0];
always @(posedge clk) begin
if (reset) begin
wrIdx <= 0;
end else if(wrEn) begin
input_reg[wrIdx] <= data_in;
wrIdx <= wrIdx + 1;
end
end
wire [5:0] stage0_0 = input_reg[0] + input_reg[2];
wire [5:0] stage0_1 = input_reg[0] + ((~input_reg[2]) + 1);
wire [5:0] stage0_2 = input_reg[1] + input_reg[3];
wire [5:0] stage0_3 = input_reg[1] + ((~input_reg[3]) + 1);
wire [5:0] stage1[0:7];
// Freq bin 0 real + complex
assign stage1[0] = stage0_0 + stage0_2;
assign stage1[1] = 0;
// Freq bin 1 real + complex
assign stage1[2] = stage0_1;
assign stage1[3] = ((~stage0_3) + 1);
// Freq bin 2 real + complex
assign stage1[4] = ((~stage0_2) + 1) + stage0_0;
assign stage1[5] = 0;
// Freq bin 3 real + complex
assign stage1[6] = stage0_1;
assign stage1[7] = stage0_3;
assign io_out[7:2] = stage1[rdIdx];
always @(posedge clk) begin
if (reset) begin
rdIdx <= 0;
end else begin
rdIdx <= rdIdx + 1;
end
end
endmodule |
module tt2_tholin_multiplexed_counter(
input [7:0] io_in,
output [7:0] io_out
);
wire s_A;
wire s_B;
wire s_C;
wire s_CLK = io_in[0];
wire s_D;
wire s_E;
wire s_F;
wire s_G;
wire s_RST = io_in[1];
wire s_SEL;
assign io_out[0] = s_A;
assign io_out[1] = s_B;
assign io_out[2] = s_C;
assign io_out[3] = s_D;
assign io_out[4] = s_E;
assign io_out[5] = s_F;
assign io_out[6] = s_G;
assign io_out[7] = s_SEL;
main CIRCUIT_0 (.A(s_A),
.B(s_B),
.C(s_C),
.CLK(s_CLK),
.D(s_D),
.E(s_E),
.F(s_F),
.G(s_G),
.RST(s_RST),
.SEL(s_SEL));
endmodule |
module user_module_348121131386929746(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4;
wire net5;
wire net6;
wire net7;
wire net8;
wire net9;
wire net10;
wire net11 = 1'b0;
wire net12 = 1'b1;
wire net13 = 1'b1;
wire net14 = 1'b0;
wire net15;
wire net16;
wire net17;
wire net18 = 1'b1;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
assign io_out[0] = net4;
assign io_out[1] = net5;
assign io_out[2] = net6;
assign io_out[3] = net7;
assign io_out[4] = net8;
assign io_out[5] = net9;
assign io_out[7] = net10;
mux_cell mux1 (
.a (net14),
.b (net15),
.sel (net16),
.out (net17)
);
mux_cell mux2 (
.a (net14),
.b (net19),
.sel (net16),
.out (net20)
);
mux_cell mux3 (
.a (net14),
.b (net21),
.sel (net16),
.out (net22)
);
mux_cell mux4 (
.a (net14),
.b (net23),
.sel (net16),
.out (net24)
);
mux_cell mux5 (
.a (net14),
.b (net25),
.sel (net16),
.out (net26)
);
mux_cell mux6 (
.a (net18),
.b (net27),
.sel (net16),
.out (net28)
);
dff_cell flop3 (
.d (net17),
.clk (net29),
.q (net19)
);
dff_cell flop4 (
.d (net20),
.clk (net29),
.q (net21)
);
dff_cell flop5 (
.d (net22),
.clk (net29),
.q (net23)
);
dff_cell flop6 (
.d (net24),
.clk (net29),
.q (net25)
);
dff_cell flop7 (
.d (net26),
.clk (net29),
.q (net27)
);
dff_cell flop8 (
.d (net28),
.clk (net29),
.q (net15)
);
dff_cell flop2 (
.d (net30),
.clk (net31),
.notq (net30)
);
dff_cell flop9 (
.d (net32),
.clk (net30),
.notq (net32)
);
dff_cell flop10 (
.d (net33),
.clk (net32),
.notq (net33)
);
dff_cell flop11 (
.d (net34),
.clk (net33),
.notq (net34)
);
dff_cell flop12 (
.d (net35),
.clk (net34),
.notq (net35)
);
dff_cell flop13 (
.d (net36),
.clk (net35),
.notq (net36)
);
dff_cell flop14 (
.d (net37),
.clk (net36),
.notq (net37)
);
dff_cell flop15 (
.d (net38),
.clk (net37),
.notq (net38)
);
dff_cell flop16 (
.d (net39),
.clk (net38),
.notq (net39)
);
dff_cell flop17 (
.d (net40),
.clk (net39),
.q (net41),
.notq (net40)
);
mux_cell mux7 (
.a (net41),
.b (net42),
.sel (net43),
.out (net44)
);
dff_cell flop18 (
.d (net31),
.clk (net42),
.notq (net31)
);
buffer_cell gate1 (
.in (net1),
.out (net42)
);
buffer_cell gate2 (
.in (net2),
.out (net16)
);
buffer_cell gate3 (
.in (net3),
.out (net43)
);
buffer_cell gate4 (
.in (net19),
.out (net4)
);
buffer_cell gate5 (
.in (net21),
.out (net5)
);
buffer_cell gate6 (
.in (net23),
.out (net6)
);
buffer_cell gate7 (
.in (net25),
.out (net7)
);
buffer_cell gate8 (
.in (net27),
.out (net8)
);
buffer_cell gate9 (
.in (net15),
.out (net9)
);
buffer_cell gate10 (
.in (net44),
.out (net29)
);
buffer_cell gate11 (
.in (net29),
.out (net10)
);
endmodule |
module msaghir_top_level
(
input [7:0] io_in,
output [7:0] io_out
);
wire w_clk = io_in[0];
wire w_rst = io_in[1];
wire [3:0] w_sel = io_in[5:2];
wire w_blink = io_in[6];
wire w_fx = io_in[7];
wire [6:0] w_segment;
wire w_clk2Hz;
wire [6:0] w_bus0;
wire [6:0] w_bus1;
assign io_out = {1'b0, w_segment};
digit_gen b0 (.i_digit(w_sel), .i_blink(w_blink), .i_clk2Hz(w_clk2Hz), .o_segment(w_bus0));
fx_gen b1 (.i_clk(w_clk), .i_rst(w_rst), .i_sel(w_sel), .o_clk2Hz(w_clk2Hz), .o_segment(w_bus1));
mux2 b2 (.i_in0(w_bus0), .i_in1(w_bus1), .i_sel(w_fx), .o_out(w_segment));
endmodule |
module phasenoisepon_seven_segment_seconds #( parameter MAX_COUNT = 1000 ) (
input [7:0] io_in,
output [7:0] io_out
);
// setup registers
reg [3:0] nibble_low;
reg [3:0] nibble_high;
reg [7:0] output_reg;
// declare wires
wire clk = io_in[0];
wire reset = io_in[1];
wire [1:0] ctl = io_in[3:2];
wire [3:0] data_in = io_in[7:4];
assign io_out[7:0] = output_reg;
// define useful FSM states
localparam CTL_LOW_NIBBLE = 2'b00;
localparam CTL_HIGH_NIBBLE = 2'b01;
always @(posedge clk) begin
// if reset, then reset all reg's to 0
if (reset) begin
nibble_low <= 0;
nibble_high <= 0;
output_reg <= 0;
end else begin
// read control lines
if (ctl == CTL_LOW_NIBBLE) begin
output_reg <= 8'h0F;
nibble_low <= data_in;
end else if (ctl == CTL_HIGH_NIBBLE) begin
output_reg <= 8'hF0;
nibble_high <= data_in;
end else if (ctl[1] == 1'b1) begin
//output_reg <= 8'hFF; // stub
case ({nibble_high,nibble_low})
8'h00: output_reg <= 8'h00; //rot13(0x00)=0x00, '\x00'->'\x00'
8'h01: output_reg <= 8'h01; //rot13(0x01)=0x01, '\x01'->'\x01'
8'h02: output_reg <= 8'h02; //rot13(0x02)=0x02, '\x02'->'\x02'
8'h03: output_reg <= 8'h03; //rot13(0x03)=0x03, '\x03'->'\x03'
8'h04: output_reg <= 8'h04; //rot13(0x04)=0x04, '\x04'->'\x04'
8'h05: output_reg <= 8'h05; //rot13(0x05)=0x05, '\x05'->'\x05'
8'h06: output_reg <= 8'h06; //rot13(0x06)=0x06, '\x06'->'\x06'
8'h07: output_reg <= 8'h07; //rot13(0x07)=0x07, '\x07'->'\x07'
8'h08: output_reg <= 8'h08; //rot13(0x08)=0x08, '\x08'->'\x08'
8'h09: output_reg <= 8'h09; //rot13(0x09)=0x09, '\t'->'\t'
8'h0a: output_reg <= 8'h0a; //rot13(0x0a)=0x0a, '\n'->'\n'
8'h0b: output_reg <= 8'h0b; //rot13(0x0b)=0x0b, '\x0b'->'\x0b'
8'h0c: output_reg <= 8'h0c; //rot13(0x0c)=0x0c, '\x0c'->'\x0c'
8'h0d: output_reg <= 8'h0d; //rot13(0x0d)=0x0d, '\r'->'\r'
8'h0e: output_reg <= 8'h0e; //rot13(0x0e)=0x0e, '\x0e'->'\x0e'
8'h0f: output_reg <= 8'h0f; //rot13(0x0f)=0x0f, '\x0f'->'\x0f'
8'h10: output_reg <= 8'h10; //rot13(0x10)=0x10, '\x10'->'\x10'
8'h11: output_reg <= 8'h11; //rot13(0x11)=0x11, '\x11'->'\x11'
8'h12: output_reg <= 8'h12; //rot13(0x12)=0x12, '\x12'->'\x12'
8'h13: output_reg <= 8'h13; //rot13(0x13)=0x13, '\x13'->'\x13'
8'h14: output_reg <= 8'h14; //rot13(0x14)=0x14, '\x14'->'\x14'
8'h15: output_reg <= 8'h15; //rot13(0x15)=0x15, '\x15'->'\x15'
8'h16: output_reg <= 8'h16; //rot13(0x16)=0x16, '\x16'->'\x16'
8'h17: output_reg <= 8'h17; //rot13(0x17)=0x17, '\x17'->'\x17'
8'h18: output_reg <= 8'h18; //rot13(0x18)=0x18, '\x18'->'\x18'
8'h19: output_reg <= 8'h19; //rot13(0x19)=0x19, '\x19'->'\x19'
8'h1a: output_reg <= 8'h1a; //rot13(0x1a)=0x1a, '\x1a'->'\x1a'
8'h1b: output_reg <= 8'h1b; //rot13(0x1b)=0x1b, '\x1b'->'\x1b'
8'h1c: output_reg <= 8'h1c; //rot13(0x1c)=0x1c, '\x1c'->'\x1c'
8'h1d: output_reg <= 8'h1d; //rot13(0x1d)=0x1d, '\x1d'->'\x1d'
8'h1e: output_reg <= 8'h1e; //rot13(0x1e)=0x1e, '\x1e'->'\x1e'
8'h1f: output_reg <= 8'h1f; //rot13(0x1f)=0x1f, '\x1f'->'\x1f'
8'h20: output_reg <= 8'h20; //rot13(0x20)=0x20, ' '->' '
8'h21: output_reg <= 8'h21; //rot13(0x21)=0x21, '!'->'!'
8'h22: output_reg <= 8'h22; //rot13(0x22)=0x22, '"'->'"'
8'h23: output_reg <= 8'h23; //rot13(0x23)=0x23, '#'->'#'
8'h24: output_reg <= 8'h24; //rot13(0x24)=0x24, '$'->'$'
8'h25: output_reg <= 8'h25; //rot13(0x25)=0x25, '%'->'%'
8'h26: output_reg <= 8'h26; //rot13(0x26)=0x26, '&'->'&'
8'h27: output_reg <= 8'h27; //rot13(0x27)=0x27, "'"->"'"
8'h28: output_reg <= 8'h28; //rot13(0x28)=0x28, '('->'('
8'h29: output_reg <= 8'h29; //rot13(0x29)=0x29, ')'->')'
8'h2a: output_reg <= 8'h2a; //rot13(0x2a)=0x2a, '*'->'*'
8'h2b: output_reg <= 8'h2b; //rot13(0x2b)=0x2b, '+'->'+'
8'h2c: output_reg <= 8'h2c; //rot13(0x2c)=0x2c, ','->','
8'h2d: output_reg <= 8'h2d; //rot13(0x2d)=0x2d, '-'->'-'
8'h2e: output_reg <= 8'h2e; //rot13(0x2e)=0x2e, '.'->'.'
8'h2f: output_reg <= 8'h2f; //rot13(0x2f)=0x2f, '/'->'/'
8'h30: output_reg <= 8'h30; //rot13(0x30)=0x30, '0'->'0'
8'h31: output_reg <= 8'h31; //rot13(0x31)=0x31, '1'->'1'
8'h32: output_reg <= 8'h32; //rot13(0x32)=0x32, '2'->'2'
8'h33: output_reg <= 8'h33; //rot13(0x33)=0x33, '3'->'3'
8'h34: output_reg <= 8'h34; //rot13(0x34)=0x34, '4'->'4'
8'h35: output_reg <= 8'h35; //rot13(0x35)=0x35, '5'->'5'
8'h36: output_reg <= 8'h36; //rot13(0x36)=0x36, '6'->'6'
8'h37: output_reg <= 8'h37; //rot13(0x37)=0x37, '7'->'7'
8'h38: output_reg <= 8'h38; //rot13(0x38)=0x38, '8'->'8'
8'h39: output_reg <= 8'h39; //rot13(0x39)=0x39, '9'->'9'
8'h3a: output_reg <= 8'h3a; //rot13(0x3a)=0x3a, ':'->':'
8'h3b: output_reg <= 8'h3b; //rot13(0x3b)=0x3b, ';'->';'
8'h3c: output_reg <= 8'h3c; //rot13(0x3c)=0x3c, '<'->'<'
8'h3d: output_reg <= 8'h3d; //rot13(0x3d)=0x3d, '='->'='
8'h3e: output_reg <= 8'h3e; //rot13(0x3e)=0x3e, '>'->'>'
8'h3f: output_reg <= 8'h3f; //rot13(0x3f)=0x3f, '?'->'?'
8'h40: output_reg <= 8'h40; //rot13(0x40)=0x40, '@'->'@'
8'h41: output_reg <= 8'h4e; //rot13(0x41)=0x4e, 'A'->'N'
8'h42: output_reg <= 8'h4f; //rot13(0x42)=0x4f, 'B'->'O'
8'h43: output_reg <= 8'h50; //rot13(0x43)=0x50, 'C'->'P'
8'h44: output_reg <= 8'h51; //rot13(0x44)=0x51, 'D'->'Q'
8'h45: output_reg <= 8'h52; //rot13(0x45)=0x52, 'E'->'R'
8'h46: output_reg <= 8'h53; //rot13(0x46)=0x53, 'F'->'S'
8'h47: output_reg <= 8'h54; //rot13(0x47)=0x54, 'G'->'T'
8'h48: output_reg <= 8'h55; //rot13(0x48)=0x55, 'H'->'U'
8'h49: output_reg <= 8'h56; //rot13(0x49)=0x56, 'I'->'V'
8'h4a: output_reg <= 8'h57; //rot13(0x4a)=0x57, 'J'->'W'
8'h4b: output_reg <= 8'h58; //rot13(0x4b)=0x58, 'K'->'X'
8'h4c: output_reg <= 8'h59; //rot13(0x4c)=0x59, 'L'->'Y'
8'h4d: output_reg <= 8'h5a; //rot13(0x4d)=0x5a, 'M'->'Z'
8'h4e: output_reg <= 8'h41; //rot13(0x4e)=0x41, 'N'->'A'
8'h4f: output_reg <= 8'h42; //rot13(0x4f)=0x42, 'O'->'B'
8'h50: output_reg <= 8'h43; //rot13(0x50)=0x43, 'P'->'C'
8'h51: output_reg <= 8'h44; //rot13(0x51)=0x44, 'Q'->'D'
8'h52: output_reg <= 8'h45; //rot13(0x52)=0x45, 'R'->'E'
8'h53: output_reg <= 8'h46; //rot13(0x53)=0x46, 'S'->'F'
8'h54: output_reg <= 8'h47; //rot13(0x54)=0x47, 'T'->'G'
8'h55: output_reg <= 8'h48; //rot13(0x55)=0x48, 'U'->'H'
8'h56: output_reg <= 8'h49; //rot13(0x56)=0x49, 'V'->'I'
8'h57: output_reg <= 8'h4a; //rot13(0x57)=0x4a, 'W'->'J'
8'h58: output_reg <= 8'h4b; //rot13(0x58)=0x4b, 'X'->'K'
8'h59: output_reg <= 8'h4c; //rot13(0x59)=0x4c, 'Y'->'L'
8'h5a: output_reg <= 8'h4d; //rot13(0x5a)=0x4d, 'Z'->'M'
8'h5b: output_reg <= 8'h5b; //rot13(0x5b)=0x5b, '['->'['
8'h5c: output_reg <= 8'h5c; //rot13(0x5c)=0x5c, '\\'->'\\'
8'h5d: output_reg <= 8'h5d; //rot13(0x5d)=0x5d, ']'->']'
8'h5e: output_reg <= 8'h5e; //rot13(0x5e)=0x5e, '^'->'^'
8'h5f: output_reg <= 8'h5f; //rot13(0x5f)=0x5f, '_'->'_'
8'h60: output_reg <= 8'h60; //rot13(0x60)=0x60, '`'->'`'
8'h61: output_reg <= 8'h6e; //rot13(0x61)=0x6e, 'a'->'n'
8'h62: output_reg <= 8'h6f; //rot13(0x62)=0x6f, 'b'->'o'
8'h63: output_reg <= 8'h70; //rot13(0x63)=0x70, 'c'->'p'
8'h64: output_reg <= 8'h71; //rot13(0x64)=0x71, 'd'->'q'
8'h65: output_reg <= 8'h72; //rot13(0x65)=0x72, 'e'->'r'
8'h66: output_reg <= 8'h73; //rot13(0x66)=0x73, 'f'->'s'
8'h67: output_reg <= 8'h74; //rot13(0x67)=0x74, 'g'->'t'
8'h68: output_reg <= 8'h75; //rot13(0x68)=0x75, 'h'->'u'
8'h69: output_reg <= 8'h76; //rot13(0x69)=0x76, 'i'->'v'
8'h6a: output_reg <= 8'h77; //rot13(0x6a)=0x77, 'j'->'w'
8'h6b: output_reg <= 8'h78; //rot13(0x6b)=0x78, 'k'->'x'
8'h6c: output_reg <= 8'h79; //rot13(0x6c)=0x79, 'l'->'y'
8'h6d: output_reg <= 8'h7a; //rot13(0x6d)=0x7a, 'm'->'z'
8'h6e: output_reg <= 8'h61; //rot13(0x6e)=0x61, 'n'->'a'
8'h6f: output_reg <= 8'h62; //rot13(0x6f)=0x62, 'o'->'b'
8'h70: output_reg <= 8'h63; //rot13(0x70)=0x63, 'p'->'c'
8'h71: output_reg <= 8'h64; //rot13(0x71)=0x64, 'q'->'d'
8'h72: output_reg <= 8'h65; //rot13(0x72)=0x65, 'r'->'e'
8'h73: output_reg <= 8'h66; //rot13(0x73)=0x66, 's'->'f'
8'h74: output_reg <= 8'h67; //rot13(0x74)=0x67, 't'->'g'
8'h75: output_reg <= 8'h68; //rot13(0x75)=0x68, 'u'->'h'
8'h76: output_reg <= 8'h69; //rot13(0x76)=0x69, 'v'->'i'
8'h77: output_reg <= 8'h6a; //rot13(0x77)=0x6a, 'w'->'j'
8'h78: output_reg <= 8'h6b; //rot13(0x78)=0x6b, 'x'->'k'
8'h79: output_reg <= 8'h6c; //rot13(0x79)=0x6c, 'y'->'l'
8'h7a: output_reg <= 8'h6d; //rot13(0x7a)=0x6d, 'z'->'m'
8'h7b: output_reg <= 8'h7b; //rot13(0x7b)=0x7b, '{'->'{'
8'h7c: output_reg <= 8'h7c; //rot13(0x7c)=0x7c, '|'->'|'
8'h7d: output_reg <= 8'h7d; //rot13(0x7d)=0x7d, '}'->'}'
8'h7e: output_reg <= 8'h7e; //rot13(0x7e)=0x7e, '~'->'~'
8'h7f: output_reg <= 8'h7f; //rot13(0x7f)=0x7f, '\x7f'->'\x7f'
default: output_reg <= 0; //should cause a noticeable error in the TB
endcase
end
end
end
endmodule |
module user_module_348255968419643987(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13 = 1'b1;
wire net14;
wire net15;
wire net16;
wire net17 = 1'b0;
wire net18;
wire net19;
wire net20 = 1'b0;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25 = 1'b0;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30 = 1'b0;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35 = 1'b0;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40 = 1'b0;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59;
wire net60;
wire net61;
wire net62;
wire net63;
wire net64;
wire net65;
wire net66;
wire net67;
wire net68;
wire net69;
wire net70;
wire net71;
wire net72;
wire net73;
wire net74;
wire net75;
wire net76;
wire net77;
wire net78 = 1'b0;
wire net79;
wire net80;
wire net81;
wire net82;
wire net83;
wire net84;
wire net85;
wire net86 = 1'b0;
wire net87;
wire net88;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net11;
assign io_out[3] = net12;
and_cell gate1 (
.a (net14),
.b (net15),
.out (net16)
);
mux_cell mux2 (
.a (net15),
.b (net17),
.sel (net9),
.out (net18)
);
dff_cell flipflop2 (
.d (net18),
.clk (net1),
.q (net19),
.notq (net15)
);
mux_cell mux3 (
.a (net14),
.b (net20),
.sel (net9),
.out (net21)
);
dff_cell flipflop3 (
.d (net21),
.clk (net22),
.q (net23),
.notq (net14)
);
mux_cell mux4 (
.a (net24),
.b (net25),
.sel (net9),
.out (net26)
);
dff_cell flipflop4 (
.d (net26),
.clk (net27),
.q (net28),
.notq (net24)
);
mux_cell mux5 (
.a (net29),
.b (net30),
.sel (net9),
.out (net31)
);
dff_cell flipflop5 (
.d (net31),
.clk (net32),
.q (net33),
.notq (net29)
);
mux_cell mux6 (
.a (net34),
.b (net35),
.sel (net9),
.out (net36)
);
dff_cell flipflop6 (
.d (net36),
.clk (net37),
.q (net38),
.notq (net34)
);
mux_cell mux7 (
.a (net39),
.b (net40),
.sel (net9),
.out (net41)
);
dff_cell flipflop7 (
.d (net41),
.clk (net42),
.q (net43),
.notq (net39)
);
mux_cell mux8 (
.a (net34),
.b (net1),
.sel (net9),
.out (net42)
);
mux_cell mux9 (
.a (net29),
.b (net1),
.sel (net9),
.out (net37)
);
mux_cell mux10 (
.a (net24),
.b (net1),
.sel (net9),
.out (net32)
);
mux_cell mux11 (
.a (net14),
.b (net1),
.sel (net9),
.out (net27)
);
mux_cell mux12 (
.a (net15),
.b (net1),
.sel (net9),
.out (net22)
);
and_cell gate7 (
.a (net24),
.b (net16),
.out (net44)
);
and_cell gate8 (
.a (net29),
.b (net44),
.out (net45)
);
and_cell gate9 (
.a (net38),
.b (net45),
.out (net46)
);
and_cell gate10 (
.a (net43),
.b (net46),
.out (net47)
);
and_cell gate11 (
.a (net23),
.b (net19),
.out (net48)
);
and_cell gate12 (
.a (net24),
.b (net48),
.out (net49)
);
and_cell gate13 (
.a (net33),
.b (net49),
.out (net50)
);
and_cell gate14 (
.a (net34),
.b (net50),
.out (net51)
);
and_cell gate15 (
.a (net43),
.b (net51),
.out (net52)
);
and_cell gate16 (
.a (net23),
.b (net15),
.out (net53)
);
and_cell gate17 (
.a (net28),
.b (net53),
.out (net54)
);
and_cell gate18 (
.a (net29),
.b (net54),
.out (net55)
);
and_cell gate19 (
.a (net34),
.b (net55),
.out (net56)
);
and_cell gate20 (
.a (net43),
.b (net56),
.out (net57)
);
and_cell gate21 (
.a (net14),
.b (net15),
.out (net58)
);
and_cell gate22 (
.a (net28),
.b (net58),
.out (net59)
);
and_cell gate23 (
.a (net29),
.b (net59),
.out (net60)
);
and_cell gate24 (
.a (net34),
.b (net60),
.out (net61)
);
and_cell gate25 (
.a (net43),
.b (net61),
.out (net62)
);
and_cell gate26 (
.a (net14),
.b (net15),
.out (net63)
);
and_cell gate27 (
.a (net24),
.b (net63),
.out (net64)
);
and_cell gate28 (
.a (net29),
.b (net64),
.out (net65)
);
and_cell gate29 (
.a (net34),
.b (net65),
.out (net66)
);
and_cell gate30 (
.a (net43),
.b (net66),
.out (net67)
);
and_cell gate31 (
.a (net23),
.b (net19),
.out (net68)
);
and_cell gate32 (
.a (net28),
.b (net68),
.out (net69)
);
and_cell gate33 (
.a (net33),
.b (net69),
.out (net70)
);
and_cell gate34 (
.a (net38),
.b (net70),
.out (net71)
);
and_cell gate35 (
.a (net39),
.b (net71),
.out (net72)
);
and_cell gate36 (
.a (net14),
.b (net15),
.out (net73)
);
and_cell gate37 (
.a (net24),
.b (net73),
.out (net74)
);
and_cell gate38 (
.a (net33),
.b (net74),
.out (net75)
);
and_cell gate39 (
.a (net38),
.b (net75),
.out (net76)
);
and_cell gate40 (
.a (net39),
.b (net76),
.out (net77)
);
mux_cell mux13 (
.a (net78),
.b (net47),
.sel (net2),
.out (net79)
);
mux_cell mux14 (
.a (net79),
.b (net52),
.sel (net3),
.out (net80)
);
mux_cell mux15 (
.a (net80),
.b (net57),
.sel (net4),
.out (net81)
);
mux_cell mux16 (
.a (net81),
.b (net62),
.sel (net5),
.out (net82)
);
mux_cell mux17 (
.a (net82),
.b (net67),
.sel (net6),
.out (net83)
);
mux_cell mux18 (
.a (net83),
.b (net72),
.sel (net7),
.out (net84)
);
mux_cell mux19 (
.a (net84),
.b (net77),
.sel (net8),
.out (net9)
);
dff_cell flipflop8 (
.d (net85),
.clk (net9),
.q (net10),
.notq (net85)
);
dff_cell flipflop1 (
.d (net87),
.clk (net10),
.q (net11),
.notq (net87)
);
dff_cell flipflop9 (
.d (net88),
.clk (net11),
.q (net12),
.notq (net88)
);
endmodule |
module tomkeddie_top_tto_a
#(parameter CLOCK_RATE=1000)
(
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire uart_tx_pin0;
wire uart_tx_pin1;
wire uart_tx_pin2;
assign io_out[0] = uart_tx_pin0;
assign io_out[1] = uart_tx_pin1;
assign io_out[2] = uart_tx_pin2;
// instatiate lcd
uart_tx uart_tx(.clk(clk), .reset(reset), .tx_pin0(uart_tx_pin0), .tx_pin1(uart_tx_pin1), .tx_pin2(uart_tx_pin2));
endmodule |
module user_module_347690870424732244(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3;
wire net4;
wire net5;
wire net6;
wire net7;
wire net8;
wire net9;
wire net10;
wire net11 = 1'b0;
wire net12 = 1'b1;
wire net13 = 1'b1;
wire net14;
wire net15;
wire net16;
wire net17 = 1'b1;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34 = 1'b0;
wire net35;
wire net36;
wire net37 = 1'b0;
wire net38;
wire net39 = 1'b0;
wire net40;
wire net41 = 1'b0;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59;
wire net60;
wire net61;
wire net62;
wire net63;
wire net64;
wire net65;
wire net66;
wire net67;
wire net68;
wire net69;
wire net70;
wire net71;
wire net72;
wire net73;
wire net74;
wire net75;
wire net76;
wire net77;
wire net78;
wire net79 = 1'b0;
wire net80;
wire net81;
wire net82;
wire net83;
wire net84;
wire net85;
wire net86 = 1'b1;
wire net87;
wire net88;
wire net89;
wire net90;
wire net91;
wire net92;
wire net93;
wire net94;
wire net95;
wire net96;
wire net97;
wire net98;
wire net99;
wire net100 = 1'b0;
wire net101;
wire net102 = 1'b0;
wire net103 = 1'b0;
wire net104 = 1'b0;
wire net105;
wire net106;
wire net107;
wire net108;
wire net109;
wire net110;
wire net111;
wire net112;
wire net113;
wire net114 = 1'b0;
assign io_out[0] = net3;
assign io_out[1] = net4;
assign io_out[2] = net5;
assign io_out[3] = net6;
assign io_out[4] = net7;
assign io_out[5] = net8;
assign io_out[6] = net9;
assign io_out[7] = net10;
dff_cell flop1 (
.d (net14),
.clk (net1),
.q (net15),
.notq (net16)
);
xor_cell xor1 (
.a (net15),
.b (net17),
.out (net18)
);
dff_cell flop2 (
.d (net19),
.clk (net1),
.q (net20),
.notq (net21)
);
xor_cell xor2 (
.a (net20),
.b (net22),
.out (net23)
);
dff_cell flop3 (
.d (net24),
.clk (net1),
.q (net25),
.notq (net26)
);
xor_cell xor3 (
.a (net25),
.b (net27),
.out (net28)
);
dff_cell flop4 (
.d (net29),
.clk (net1),
.q (net30),
.notq (net31)
);
xor_cell xor4 (
.a (net30),
.b (net32),
.out (net33)
);
and_cell and1 (
.a (net17),
.b (net15),
.out (net22)
);
and_cell and2 (
.a (net22),
.b (net20),
.out (net27)
);
and_cell and3 (
.a (net27),
.b (net25),
.out (net32)
);
mux_cell mux1 (
.a (net34),
.b (net35),
.sel (net36),
.out (net14)
);
mux_cell mux2 (
.a (net37),
.b (net38),
.sel (net36),
.out (net19)
);
mux_cell mux3 (
.a (net39),
.b (net40),
.sel (net36),
.out (net24)
);
mux_cell mux4 (
.a (net41),
.b (net42),
.sel (net36),
.out (net29)
);
or_cell or2 (
.a (net43),
.b (net44),
.out (net45)
);
or_cell or3 (
.a (net45),
.b (net46),
.out (net47)
);
and_cell and4 (
.a (net26),
.b (net21),
.out (net43)
);
and_cell and5 (
.a (net25),
.b (net20),
.out (net44)
);
and_cell and6 (
.a (net25),
.b (net15),
.out (net46)
);
or_cell or5 (
.a (net48),
.b (net49),
.out (net50)
);
and_cell and7 (
.a (net31),
.b (net26),
.out (net51)
);
and_cell and8 (
.a (net21),
.b (net15),
.out (net52)
);
and_cell and10 (
.a (net51),
.b (net52),
.out (net48)
);
and_cell and11 (
.a (net25),
.b (net21),
.out (net53)
);
and_cell and13 (
.a (net53),
.b (net16),
.out (net49)
);
and_cell and9 (
.a (net26),
.b (net20),
.out (net54)
);
and_cell and12 (
.a (net26),
.b (net20),
.out (net55)
);
and_cell and14 (
.a (net55),
.b (net16),
.out (net56)
);
or_cell or4 (
.a (net57),
.b (net58),
.out (net59)
);
or_cell or6 (
.a (net59),
.b (net60),
.out (net61)
);
and_cell and15 (
.a (net31),
.b (net16),
.out (net57)
);
and_cell and16 (
.a (net31),
.b (net21),
.out (net58)
);
and_cell and17 (
.a (net31),
.b (net26),
.out (net60)
);
or_cell or7 (
.a (net62),
.b (net63),
.out (net64)
);
and_cell and19 (
.a (net25),
.b (net20),
.out (net65)
);
and_cell and20 (
.a (net30),
.b (net15),
.out (net63)
);
and_cell and21 (
.a (net65),
.b (net16),
.out (net62)
);
or_cell or8 (
.a (net66),
.b (net67),
.out (net68)
);
and_cell and18 (
.a (net25),
.b (net20),
.out (net69)
);
and_cell and22 (
.a (net30),
.b (net16),
.out (net67)
);
and_cell and23 (
.a (net69),
.b (net15),
.out (net66)
);
and_cell and25 (
.a (net25),
.b (net20),
.out (net70)
);
and_cell and26 (
.a (net70),
.b (net15),
.out (net71)
);
and_cell and24 (
.a (net72),
.b (net30),
.out (net73)
);
or_cell or1 (
.a (net74),
.b (net2),
.out (net75)
);
not_cell not1 (
.in (net75),
.out (net36)
);
and_cell and27 (
.a (net68),
.b (net71),
.out (net76)
);
or_cell or11 (
.a (net77),
.b (net76),
.out (net78)
);
and_cell and28 (
.a (net54),
.b (net56),
.out (net77)
);
or_cell or9 (
.a (net50),
.b (net64),
.out (net80)
);
and_cell and29 (
.a (net81),
.b (net82),
.out (net83)
);
not_cell not2 (
.in (net78),
.out (net81)
);
not_cell not3 (
.in (net80),
.out (net82)
);
dff_cell flop5 (
.d (net84),
.clk (net1),
.q (net85)
);
xor_cell xor5 (
.a (net85),
.b (net86),
.out (net87)
);
dff_cell flop6 (
.d (net88),
.clk (net1),
.q (net89)
);
xor_cell xor6 (
.a (net89),
.b (net90),
.out (net91)
);
dff_cell flop7 (
.d (net92),
.clk (net1),
.q (net93)
);
xor_cell xor7 (
.a (net93),
.b (net94),
.out (net95)
);
dff_cell flop8 (
.d (net96),
.clk (net1),
.q (net97)
);
xor_cell xor8 (
.a (net97),
.b (net98),
.out (net99)
);
and_cell and30 (
.a (net86),
.b (net85),
.out (net90)
);
and_cell and31 (
.a (net90),
.b (net89),
.out (net94)
);
and_cell and32 (
.a (net94),
.b (net93),
.out (net98)
);
mux_cell mux5 (
.a (net100),
.b (net87),
.sel (net101),
.out (net84)
);
mux_cell mux6 (
.a (net102),
.b (net91),
.sel (net101),
.out (net88)
);
mux_cell mux7 (
.a (net103),
.b (net95),
.sel (net101),
.out (net92)
);
mux_cell mux8 (
.a (net104),
.b (net99),
.sel (net101),
.out (net96)
);
or_cell or10 (
.a (net105),
.b (net106),
.out (net107)
);
not_cell not4 (
.in (net107),
.out (net101)
);
or_cell or12 (
.a (net108),
.b (net2),
.out (net106)
);
or_cell or13 (
.a (net109),
.b (net110),
.out (net105)
);
and_cell and33 (
.a (net97),
.b (net78),
.out (net108)
);
and_cell and34 (
.a (net93),
.b (net83),
.out (net110)
);
and_cell and35 (
.a (net85),
.b (net80),
.out (net109)
);
mux_cell mux9 (
.a (net30),
.b (net33),
.sel (net107),
.out (net42)
);
mux_cell mux10 (
.a (net25),
.b (net28),
.sel (net107),
.out (net40)
);
mux_cell mux11 (
.a (net20),
.b (net23),
.sel (net107),
.out (net38)
);
mux_cell mux12 (
.a (net15),
.b (net18),
.sel (net107),
.out (net35)
);
and_cell and39 (
.a (net73),
.b (net107),
.out (net74)
);
or_cell or14 (
.a (net15),
.b (net20),
.out (net111)
);
or_cell or15 (
.a (net111),
.b (net25),
.out (net72)
);
dff_cell flop9 (
.d (net112),
.clk (net1),
.q (net113),
.notq (net112)
);
mux_cell mux13 (
.a (net47),
.b (net114),
.sel (net2),
.out (net3)
);
mux_cell mux14 (
.a (net50),
.b (net114),
.sel (net2),
.out (net4)
);
mux_cell mux15 (
.a (net54),
.b (net114),
.sel (net2),
.out (net5)
);
mux_cell mux16 (
.a (net56),
.b (net114),
.sel (net2),
.out (net6)
);
mux_cell mux17 (
.a (net61),
.b (net114),
.sel (net2),
.out (net7)
);
mux_cell mux18 (
.a (net64),
.b (net113),
.sel (net2),
.out (net8)
);
mux_cell mux19 (
.a (net68),
.b (net114),
.sel (net2),
.out (net9)
);
mux_cell mux20 (
.a (net71),
.b (net114),
.sel (net2),
.out (net10)
);
endmodule |
module user_module_349729432862196307(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10 = 1'b1;
wire net11 = 1'b0;
wire net12 = 1'b1;
wire net13 = 1'b1;
wire net14;
wire net15 = 1'b0;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29 = 1'b0;
wire net30 = 1'b0;
wire net31 = 1'b0;
wire net32 = 1'b0;
wire net33 = 1'b0;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51 = 1'b0;
wire net52 = 1'b0;
wire net53 = 1'b0;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59;
wire net60 = 1'b0;
wire net61 = 1'b0;
wire net62 = 1'b0;
wire net63 = 1'b0;
wire net64 = 1'b0;
wire net65 = 1'b0;
wire net66 = 1'b0;
wire net67 = 1'b0;
wire net68 = 1'b0;
wire net69 = 1'b0;
wire net70 = 1'b0;
wire net71 = 1'b0;
wire net72 = 1'b0;
wire net73;
wire net74 = 1'b0;
wire net75 = 1'b0;
wire net76;
wire net77;
wire net78;
wire net79 = 1'b0;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net10;
assign io_out[3] = net9;
assign io_out[4] = net9;
assign io_out[5] = net9;
assign io_out[7] = net1;
or_cell gate2 (
.a (net14),
.b (net15),
.out (net9)
);
xor_cell gate3 (
);
nand_cell gate4 (
);
buffer_cell gate6 (
);
dff_cell flipflop1 (
.d (net16),
.clk (net1),
.q (net17),
.notq (net18)
);
dff_cell flipflop2 (
.d (net8),
.clk (net19),
.q (net20)
);
mux_cell mux3 (
.a (net20),
.b (net7),
.sel (net2),
.out (net21)
);
dff_cell flipflop3 (
.d (net21),
.clk (net19),
.q (net22)
);
mux_cell mux4 (
.a (net22),
.b (net6),
.sel (net2),
.out (net23)
);
dff_cell flipflop4 (
.d (net23),
.clk (net19),
.q (net24)
);
mux_cell mux5 (
.a (net24),
.b (net5),
.sel (net2),
.out (net25)
);
dff_cell flipflop5 (
.d (net25),
.clk (net19),
.q (net26)
);
mux_cell mux6 (
.a (net26),
.b (net4),
.sel (net2),
.out (net27)
);
dff_cell flipflop6 (
.d (net27),
.clk (net19),
.q (net28)
);
dff_cell flipflop8 (
.d (net34),
.clk (net19),
.q (net35)
);
dff_cell flipflop9 (
.d (net36),
.clk (net19),
.q (net37)
);
dff_cell flipflop10 (
.d (net38),
.clk (net19),
.q (net39)
);
dff_cell flipflop11 (
.d (net40),
.clk (net19),
.q (net41)
);
dff_cell flipflop12 (
.d (net42),
.clk (net19),
.q (net43)
);
dff_cell flipflop13 (
.d (net44),
.clk (net19),
.q (net45)
);
not_cell not1 (
.in (net46),
.out (net47)
);
mux_cell mux1 (
.a (net48),
.b (net47),
.sel (net49),
.out (net50)
);
not_cell not3 (
.in (net50),
.out (net14)
);
xor_cell gate15 (
.a (net34),
.b (net35),
.out (net54)
);
xor_cell gate19 (
.a (net54),
.b (net37),
.out (net55)
);
xor_cell gate20 (
.a (net55),
.b (net39),
.out (net56)
);
xor_cell gate21 (
.a (net56),
.b (net45),
.out (net48)
);
xor_cell gate22 (
.a (net37),
.b (net34),
.out (net57)
);
xor_cell gate23 (
.a (net39),
.b (net57),
.out (net58)
);
xor_cell gate24 (
.a (net43),
.b (net58),
.out (net59)
);
xor_cell gate25 (
.a (net45),
.b (net59),
.out (net46)
);
mux_cell mux8 (
.a (net35),
.b (net65),
.sel (net2),
.out (net36)
);
mux_cell mux9 (
.a (net37),
.b (net66),
.sel (net2),
.out (net38)
);
mux_cell mux10 (
.a (net39),
.b (net67),
.sel (net2),
.out (net40)
);
mux_cell mux11 (
.a (net41),
.b (net68),
.sel (net2),
.out (net42)
);
mux_cell mux12 (
.a (net43),
.b (net69),
.sel (net2),
.out (net44)
);
mux_cell mux7 (
.a (net73),
.b (net71),
.sel (net2),
.out (net34)
);
mux_cell mux14 (
.a (net17),
.b (net1),
.sel (net2),
.out (net19)
);
mux_cell mux2 (
.a (net18),
.b (net75),
.sel (net2),
.out (net16)
);
not_cell not2 (
.in (net19),
.out (net49)
);
mux_cell mux15 (
.a (net28),
.b (net3),
.sel (net2),
.out (net76)
);
dff_cell flipflop7 (
.d (net76),
.clk (net19),
.q (net77)
);
dff_cell flipflop14 (
.d (net78),
.clk (net19),
.q (net73)
);
mux_cell mux16 (
.a (net77),
.b (net79),
.sel (net2),
.out (net78)
);
endmodule |
module option22 (
input wire [7:0] io_in,
output wire [7:0] io_out
);
parameter WORD_COUNT = 22;
wire clk = io_in[0];
wire reset = io_in[1];
wire write = io_in[2];
wire din = io_in[3];
assign io_out = buffer[7:0];
reg [2:0] count;
reg [8 * WORD_COUNT - 1:0] buffer;
wire [7:0] bh = (write & din) | (!write & buffer[15]);
always@(posedge clk or posedge reset) begin
if(reset) begin
count <= 3'd0;
end else begin
if(count == 3'b111) begin
buffer <= {buffer[7:0], buffer[WORD_COUNT * 8 - 1:16], bh, buffer[15:9]};
end else begin
buffer[15:8] <= {bh, buffer[15:9]};
end
count <= count + 3'd1;
end
end
endmodule |
module user_module_347619669052490324(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10 = 1'b0;
wire net11 = 1'b1;
wire net12 = 1'b1;
wire net13;
wire net14;
wire net15 = 1'b1;
wire net16;
wire net17;
wire net18 = 1'b1;
wire net19;
wire net20;
wire net21 = 1'b1;
wire net22;
wire net23;
wire net24 = 1'b1;
wire net25;
wire net26;
wire net27 = 1'b0;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40 = 1'b0;
wire net41;
wire net42;
wire net43 = 1'b1;
wire net44;
wire net45;
wire net46 = 1'b0;
wire net47;
wire net48;
wire net49 = 1'b1;
wire net50;
wire net51;
wire net52 = 1'b1;
wire net53;
wire net54;
wire net55 = 1'b1;
wire net56;
wire net57;
wire net58 = 1'b1;
wire net59 = 1'b0;
wire net60 = 1'b0;
wire net61 = 1'b1;
wire net62 = 1'b0;
assign io_out[0] = net7;
assign io_out[5] = net8;
assign io_out[7] = net9;
dff_cell flop1 (
.d (net13),
.clk (net1),
.q (net14)
);
mux_cell mux1 (
.a (net15),
.b (net16),
.sel (net7),
.out (net13)
);
dff_cell flop3 (
.d (net17),
.clk (net1),
.q (net16)
);
mux_cell mux3 (
.a (net18),
.b (net19),
.sel (net7),
.out (net17)
);
dff_cell flop4 (
.d (net20),
.clk (net1),
.q (net19)
);
mux_cell mux4 (
.a (net21),
.b (net22),
.sel (net7),
.out (net20)
);
dff_cell flop5 (
.d (net23),
.clk (net1),
.q (net22)
);
mux_cell mux5 (
.a (net24),
.b (net25),
.sel (net7),
.out (net23)
);
dff_cell flop6 (
.d (net26),
.clk (net1),
.q (net25)
);
mux_cell mux6 (
.a (net27),
.b (net28),
.sel (net7),
.out (net26)
);
dff_cell flop7 (
.d (net29),
.clk (net1),
.q (net28)
);
mux_cell mux7 (
.a (net2),
.b (net30),
.sel (net7),
.out (net29)
);
dff_cell flop8 (
.d (net31),
.clk (net1),
.q (net30)
);
mux_cell mux8 (
.a (net3),
.b (net32),
.sel (net7),
.out (net31)
);
dff_cell flop9 (
.d (net33),
.clk (net1),
.q (net32)
);
mux_cell mux9 (
.a (net4),
.b (net34),
.sel (net7),
.out (net33)
);
dff_cell flop10 (
.d (net35),
.clk (net1),
.q (net34)
);
mux_cell mux10 (
.a (net5),
.b (net36),
.sel (net7),
.out (net35)
);
dff_cell flop11 (
.d (net37),
.clk (net1),
.q (net36)
);
mux_cell mux11 (
.a (net6),
.b (net38),
.sel (net7),
.out (net37)
);
dff_cell flop12 (
.d (net39),
.clk (net1),
.q (net38)
);
mux_cell mux12 (
.a (net40),
.b (net41),
.sel (net7),
.out (net39)
);
dff_cell flop13 (
.d (net42),
.clk (net1),
.q (net41)
);
mux_cell mux13 (
.a (net43),
.b (net44),
.sel (net7),
.out (net42)
);
dff_cell flop14 (
.d (net45),
.clk (net1),
.q (net44)
);
mux_cell mux14 (
.a (net46),
.b (net47),
.sel (net7),
.out (net45)
);
dff_cell flop15 (
.d (net48),
.clk (net1),
.q (net47)
);
mux_cell mux15 (
.a (net49),
.b (net50),
.sel (net7),
.out (net48)
);
dff_cell flop16 (
.d (net51),
.clk (net1),
.q (net50)
);
mux_cell mux16 (
.a (net52),
.b (net53),
.sel (net7),
.out (net51)
);
dff_cell flop17 (
.d (net54),
.clk (net1),
.q (net53)
);
mux_cell mux17 (
.a (net55),
.b (net56),
.sel (net7),
.out (net54)
);
dff_cell flop18 (
.d (net57),
.clk (net1),
.q (net56)
);
mux_cell mux18 (
.a (net58),
.b (net9),
.sel (net7),
.out (net57)
);
mux_cell mux2 (
.a (net61),
.b (net14),
.sel (net8),
.out (net9)
);
endmodule |
module user_module_347787021138264660(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16 = 1'b0;
wire net17 = 1'b1;
wire net18 = 1'b1;
wire net19 = 1'b0;
wire net20;
wire net21;
wire net22 = 1'b0;
wire net23;
wire net24;
wire net25 = 1'b0;
wire net26;
wire net27;
wire net28 = 1'b0;
wire net29;
wire net30;
wire net31 = 1'b0;
wire net32;
wire net33;
wire net34 = 1'b0;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59;
wire net60;
wire net61;
wire net62 = 1'b0;
wire net63;
wire net64;
wire net65;
wire net66;
wire net67;
wire net68;
wire net69;
wire net70;
wire net71;
wire net72;
wire net73;
wire net74;
wire net75;
wire net76;
wire net77;
wire net78;
wire net79;
wire net80;
wire net81;
wire net82;
wire net83;
wire net84;
wire net85;
wire net86;
wire net87;
wire net88;
wire net89;
wire net90;
wire net91;
wire net92;
wire net93;
wire net94;
wire net95;
wire net96;
wire net97;
wire net98;
wire net99;
wire net100;
wire net101;
wire net102;
wire net103;
wire net104;
wire net105;
wire net106;
wire net107;
wire net108;
wire net109;
wire net110;
wire net111;
wire net112;
wire net113;
wire net114;
wire net115;
wire net116;
wire net117;
wire net118;
wire net119;
wire net120;
wire net121;
wire net122;
wire net123;
wire net124;
wire net125;
wire net126;
wire net127;
wire net128;
wire net129;
wire net130;
wire net131;
wire net132;
wire net133;
wire net134;
wire net135;
wire net136;
wire net137;
wire net138;
wire net139;
wire net140;
wire net141;
wire net142;
wire net143;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net11;
assign io_out[3] = net12;
assign io_out[4] = net13;
assign io_out[5] = net14;
assign io_out[6] = net15;
and_cell gate1 (
);
or_cell gate2 (
);
xor_cell gate3 (
);
nand_cell gate4 (
);
buffer_cell gate6 (
);
mux_cell mux1 (
);
dff_cell flipflop1 (
);
not_cell gate12 (
.in (net19),
.out (net20)
);
and_cell gate14 (
.a (net4),
.b (net20),
.out (net21)
);
not_cell gate21 (
.in (net22),
.out (net23)
);
and_cell gate23 (
.a (net5),
.b (net23),
.out (net24)
);
not_cell gate30 (
.in (net25),
.out (net26)
);
and_cell gate32 (
.a (net3),
.b (net26),
.out (net27)
);
not_cell gate39 (
.in (net28),
.out (net29)
);
and_cell gate41 (
.a (net6),
.b (net29),
.out (net30)
);
not_cell gate48 (
.in (net31),
.out (net32)
);
and_cell gate50 (
.a (net7),
.b (net32),
.out (net33)
);
not_cell gate57 (
.in (net34),
.out (net35)
);
and_cell gate59 (
.a (net2),
.b (net35),
.out (net36)
);
dff_cell flipflop2 (
.d (net30),
.clk (net37),
.q (net38)
);
dff_cell flipflop3 (
.d (net24),
.clk (net39),
.q (net40)
);
dff_cell flipflop4 (
.d (net21),
.clk (net41),
.q (net42)
);
dff_cell flipflop5 (
.d (net27),
.clk (net43),
.q (net44)
);
dff_cell flipflop6 (
.d (net36),
.clk (net45),
.q (net46)
);
dff_cell flipflop7 (
.d (net33),
.clk (net47),
.q (net48)
);
xor_cell gate5 (
.a (net46),
.b (net44),
.out (net49)
);
and_cell gate7 (
.a (net46),
.b (net44),
.out (net50)
);
xor_cell gate8 (
.a (net42),
.b (net40),
.out (net51)
);
and_cell gate9 (
.a (net42),
.b (net40),
.out (net52)
);
xor_cell gate10 (
.a (net38),
.b (net48),
.out (net53)
);
and_cell gate11 (
.a (net38),
.b (net48),
.out (net54)
);
xor_cell gate13 (
.a (net49),
.b (net51),
.out (net55)
);
and_cell gate15 (
.a (net49),
.b (net51),
.out (net56)
);
xor_cell gate16 (
.a (net50),
.b (net52),
.out (net57)
);
xor_cell gate17 (
.a (net57),
.b (net56),
.out (net58)
);
and_cell gate18 (
.a (net56),
.b (net57),
.out (net59)
);
and_cell gate19 (
.a (net52),
.b (net50),
.out (net60)
);
or_cell gate20 (
.a (net59),
.b (net60),
.out (net61)
);
xor_cell gate22 (
.a (net53),
.b (net62),
.out (net63)
);
and_cell gate24 (
.a (net53),
.b (net62),
.out (net64)
);
xor_cell gate25 (
.a (net54),
.b (net62),
.out (net65)
);
xor_cell gate26 (
.a (net65),
.b (net64),
.out (net66)
);
and_cell gate27 (
.a (net64),
.b (net65),
.out (net67)
);
and_cell gate28 (
.a (net62),
.b (net54),
.out (net68)
);
or_cell gate29 (
.a (net67),
.b (net68),
.out (net69)
);
xor_cell gate36 (
.a (net55),
.b (net63),
.out (net70)
);
and_cell gate37 (
.a (net55),
.b (net63),
.out (net71)
);
xor_cell gate38 (
.a (net58),
.b (net66),
.out (net72)
);
xor_cell gate40 (
.a (net72),
.b (net71),
.out (net73)
);
and_cell gate42 (
.a (net71),
.b (net72),
.out (net74)
);
and_cell gate43 (
.a (net66),
.b (net58),
.out (net75)
);
or_cell gate44 (
.a (net74),
.b (net75),
.out (net76)
);
xor_cell gate31 (
.a (net61),
.b (net69),
.out (net77)
);
xor_cell gate33 (
.a (net77),
.b (net76),
.out (net78)
);
or_cell gate34 (
.a (net79),
.b (net73),
.out (net80)
);
or_cell gate35 (
.a (net80),
.b (net81),
.out (net9)
);
and_cell gate45 (
.a (net70),
.b (net78),
.out (net81)
);
and_cell gate47 (
.a (net82),
.b (net83),
.out (net79)
);
not_cell not1 (
.in (net70),
.out (net82)
);
not_cell not2 (
.in (net78),
.out (net83)
);
or_cell gate46 (
.a (net84),
.b (net85),
.out (net86)
);
or_cell gate49 (
.a (net86),
.b (net83),
.out (net10)
);
and_cell gate51 (
.a (net73),
.b (net70),
.out (net84)
);
and_cell gate52 (
.a (net82),
.b (net87),
.out (net85)
);
not_cell not3 (
.in (net73),
.out (net87)
);
or_cell gate53 (
.a (net87),
.b (net70),
.out (net88)
);
or_cell gate54 (
.a (net88),
.b (net78),
.out (net11)
);
or_cell gate55 (
.a (net89),
.b (net90),
.out (net91)
);
or_cell gate56 (
.a (net91),
.b (net92),
.out (net12)
);
or_cell gate58 (
.a (net93),
.b (net94),
.out (net92)
);
and_cell gate60 (
.a (net83),
.b (net82),
.out (net89)
);
and_cell gate61 (
.a (net83),
.b (net73),
.out (net90)
);
and_cell gate62 (
.a (net73),
.b (net82),
.out (net93)
);
and_cell gate63 (
.a (net87),
.b (net78),
.out (net95)
);
and_cell gate64 (
.a (net95),
.b (net70),
.out (net94)
);
or_cell gate65 (
.a (net96),
.b (net97),
.out (net13)
);
and_cell gate67 (
.a (net98),
.b (net82),
.out (net96)
);
and_cell gate69 (
.a (net73),
.b (net82),
.out (net97)
);
not_cell not4 (
.in (net78),
.out (net98)
);
or_cell gate70 (
.a (net99),
.b (net100),
.out (net101)
);
or_cell gate71 (
.a (net101),
.b (net102),
.out (net14)
);
and_cell gate72 (
.a (net82),
.b (net103),
.out (net99)
);
not_cell not5 (
.in (net73),
.out (net103)
);
and_cell gate73 (
.a (net103),
.b (net78),
.out (net100)
);
and_cell gate74 (
.a (net78),
.b (net82),
.out (net102)
);
or_cell gate75 (
.a (net104),
.b (net105),
.out (net106)
);
or_cell gate76 (
.a (net106),
.b (net107),
.out (net15)
);
and_cell gate77 (
.a (net98),
.b (net73),
.out (net104)
);
and_cell gate78 (
.a (net73),
.b (net82),
.out (net105)
);
and_cell gate79 (
.a (net78),
.b (net103),
.out (net107)
);
xor_cell gate80 (
.a (net108),
.b (net8),
.out (net109)
);
dff_cell flipflop9 (
.d (net109),
.clk (net1),
.q (net108)
);
xor_cell gate82 (
.a (net110),
.b (net111),
.out (net112)
);
dff_cell flipflop10 (
.d (net112),
.clk (net1),
.q (net111)
);
xor_cell gate84 (
.a (net113),
.b (net114),
.out (net115)
);
dff_cell flipflop11 (
.d (net115),
.clk (net1),
.q (net114)
);
and_cell gate88 (
.a (net108),
.b (net8),
.out (net110)
);
and_cell gate83 (
.a (net111),
.b (net110),
.out (net113)
);
and_cell gate89 (
.a (net114),
.b (net113),
.out (net116)
);
xor_cell gate85 (
.a (net116),
.b (net117),
.out (net118)
);
dff_cell flipflop12 (
.d (net118),
.clk (net1),
.q (net117)
);
xor_cell gate86 (
.a (net119),
.b (net120),
.out (net121)
);
dff_cell flipflop13 (
.d (net121),
.clk (net1),
.q (net120)
);
and_cell gate87 (
.a (net117),
.b (net116),
.out (net119)
);
and_cell gate90 (
.a (net120),
.b (net119),
.out (net122)
);
xor_cell gate81 (
.a (net122),
.b (net123),
.out (net124)
);
dff_cell flipflop14 (
.d (net124),
.clk (net1),
.q (net123)
);
and_cell gate91 (
.a (net123),
.b (net122),
.out (net125)
);
xor_cell gate92 (
.a (net125),
.b (net126),
.out (net127)
);
dff_cell flipflop15 (
.d (net127),
.clk (net1),
.q (net126)
);
and_cell gate94 (
.a (net126),
.b (net125),
.out (net128)
);
xor_cell gate95 (
.a (net128),
.b (net129),
.out (net130)
);
dff_cell flipflop16 (
.d (net130),
.clk (net1),
.q (net129)
);
xor_cell gate96 (
.a (net131),
.b (net132),
.out (net133)
);
dff_cell flipflop17 (
.d (net133),
.clk (net1),
.q (net132)
);
and_cell gate97 (
.a (net129),
.b (net128),
.out (net131)
);
and_cell gate98 (
.a (net132),
.b (net131),
.out (net134)
);
xor_cell gate99 (
.a (net134),
.b (net135),
.out (net136)
);
dff_cell flipflop18 (
.d (net136),
.clk (net1),
.q (net135)
);
and_cell gate100 (
.a (net135),
.b (net134),
.out (net137)
);
xor_cell gate101 (
.a (net137),
.b (net138),
.out (net139)
);
dff_cell flipflop19 (
.d (net139),
.clk (net1),
.q (net138)
);
and_cell gate102 (
.a (net138),
.b (net137),
.out (net140)
);
xor_cell gate103 (
.a (net140),
.b (net141),
.out (net142)
);
dff_cell flipflop20 (
.d (net142),
.clk (net1),
.q (net141)
);
and_cell gate104 (
.a (net141),
.b (net140),
.out (net143)
);
mux_cell mux2 (
.a (net1),
.b (net143),
.sel (net8),
.out (net47)
);
mux_cell mux3 (
.a (net1),
.b (net143),
.sel (net8),
.out (net37)
);
mux_cell mux4 (
.a (net1),
.b (net143),
.sel (net8),
.out (net39)
);
mux_cell mux5 (
.a (net1),
.b (net143),
.sel (net8),
.out (net41)
);
mux_cell mux6 (
.a (net1),
.b (net143),
.sel (net8),
.out (net43)
);
mux_cell mux7 (
.a (net1),
.b (net143),
.sel (net8),
.out (net45)
);
endmodule |
module user_module_349255310782759507(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11 = 1'b0;
wire net12 = 1'b1;
wire net13 = 1'b1;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19 = 1'b1;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
assign io_out[0] = net9;
assign io_out[3] = net10;
mux_cell mux1 (
.a (net14),
.b (net15),
.sel (net16),
.out (net17)
);
mux_cell mux2 (
.a (net18),
.b (net19),
.sel (net16),
.out (net20)
);
mux_cell mux3 (
.a (net17),
.b (net20),
.sel (net21),
.out (net9)
);
buffer_cell gate1 (
.in (net1),
.out (net16)
);
buffer_cell gate2 (
.in (net2),
.out (net21)
);
buffer_cell gate3 (
.in (net3),
.out (net14)
);
mux_cell mux4 (
.a (net22),
.b (net23),
.sel (net16),
.out (net24)
);
mux_cell mux5 (
.a (net25),
.b (net19),
.sel (net16),
.out (net26)
);
mux_cell mux6 (
.a (net24),
.b (net26),
.sel (net21),
.out (net10)
);
buffer_cell gate4 (
.in (net4),
.out (net22)
);
buffer_cell gate5 (
.in (net5),
.out (net15)
);
buffer_cell gate6 (
.in (net6),
.out (net23)
);
buffer_cell gate7 (
.in (net7),
.out (net18)
);
buffer_cell gate8 (
.in (net8),
.out (net25)
);
endmodule |
module afoote_w5s8_tt02_utm_core(
input clock,
input reset,
input mode,
input [2:0] encoded_state_in,
input [2:0] sym_in,
input sym_in_valid,
output [2:0] new_sym,
output direction,
output [2:0] encoded_next_state
);
reg [7:0] stored_state;
reg [2:0] symbuf;
reg symbuf_valid;
wire [7:0] state_in;
wire [7:0] state;
wire [7:0] next_state;
wire [2:0] sym;
always @(posedge clock) begin
if (reset) begin
stored_state <= 8'h01;
end
else if (sym_in_valid && symbuf_valid) begin
stored_state <= next_state;
end
else begin
stored_state <= stored_state;
end
end
always @(posedge clock) begin
if (reset) begin
symbuf <= 3'b0;
end
else if (sym_in_valid) begin
symbuf <= sym_in;
end
else begin
symbuf <= symbuf;
end
end
always @(posedge clock) begin
if (reset) begin
symbuf_valid <= 0;
end
else if (sym_in_valid) begin
symbuf_valid <= 1;
end
else begin
symbuf_valid <= symbuf_valid;
end
end
afoote_w5s8_tt02_decoder_3to8 decode_state_in(
.in(encoded_state_in),
.out(state_in)
);
assign state = (mode == 0) ? state_in : stored_state;
assign sym = (mode == 0) ? sym_in : symbuf;
afoote_w5s8_tt02_direction direction_block(
.state(state),
.s2(sym[2]),
.s1(sym[1]),
.s0(sym[0]),
.direction(direction)
);
afoote_w5s8_tt02_next_state next_state_block(
.state_in(state),
.s2(sym[2]),
.s1(sym[1]),
.s0(sym[0]),
.state_out(next_state));
afoote_w5s8_tt02_new_symbol new_sym_block(
.state_in(state),
.s2(sym[2]),
.s1(sym[1]),
.s0(sym[0]),
.z2(new_sym[2]),
.z1(new_sym[1]),
.z0(new_sym[0])
);
afoote_w5s8_tt02_encoder_8to3 encode_state_out(
.in(next_state),
.out(encoded_next_state)
);
endmodule |
module afoote_w5s8_tt02_new_symbol(
input [7:0] state_in,
input s2,
input s1,
input s0,
output z2,
output z1,
output z0
);
wire a,b,c,d,e,f,g,h;
assign a = state_in[0];
assign b = state_in[1];
assign c = state_in[2];
assign d = state_in[3];
assign e = state_in[4];
assign f = state_in[5];
assign g = state_in[6];
assign h = state_in[7];
assign z2 = ((~s2) & b) | (d & s0) | c | (e & (s0 | s1)) | (f & (~(s2 | s1)));
assign z1 = (a & (~s2)) | (d & (s2 | s1) & (~s0)) | (e & s2 & (~s0));
assign z0 = (s0 & ((a & s2) | (~a))) | (h & s1);
endmodule |
module AidanMedcalf_pid_controller (
input [7:0] io_in,
output [7:0] io_out
);
wire clk;
wire reset;
//wire enable;
wire cfg_clk;
wire cfg_mosi;
wire cfg_cs;
wire pv_in_miso;
assign clk = io_in[0];
assign reset = io_in[1];
// io_in[2] not used
//assign enable = io_in[2];
assign cfg_clk = io_in[3];
assign cfg_mosi = io_in[4];
// io_in[5] not used
assign cfg_cs = io_in[6];
assign pv_in_miso = io_in[7];
wire pv_in_clk;
wire pv_in_cs;
reg [1:0] pv_in_cs_hist;
wire out_clk, out_cs, out_mosi;
assign io_out[0] = pv_in_clk;
assign io_out[1] = pv_in_cs;
//assign io_out[2] = 1'b0; // io_out[2] not used
//assign io_out[3] = pid_stb_d1;
//assign io_out[7:4] = out;
assign io_out[2] = out_clk;
assign io_out[3] = out_mosi;
assign io_out[4] = out_cs;
assign io_out[7:5] = 1'b0; // not used
// Configuration registers
//reg [7:0] cfg_buf[4];
wire [7:0] sp;
wire [7:0] kp;
wire [7:0] ki;
//wire [7:0] kd;
//assign sp = cfg_buf[0][3:0];
//assign kp = cfg_buf[0][7:4];
//assign ki = cfg_buf[1][3:0];
//assign kd = cfg_buf[1][7:4];
//assign stb_level[7:0] = cfg_buf[2];
//assign stb_level[15:8] = cfg_buf[3];
assign sp = cfg_spi_buffer[7:0];
assign kp = cfg_spi_buffer[15:8];
assign ki = cfg_spi_buffer[23:16];
//assign kd = cfg_spi_buffer[31:24];
wire pv_stb;
wire pid_stb;
reg pid_stb_d1;
wire pid_rst;
assign pid_rst = reset || !cfg_cs;
// I/O registers
reg [7:0] in_pv;
reg [7:0] out;
// Slave SPI for configuration
//wire cfg_spi_done;
wire [23:0] cfg_spi_buffer;
spi_slave_in #(.BITS(24)) cfg_spi(.reset(reset), .clk(clk), .cs(cfg_cs), .sck(cfg_clk), .mosi(cfg_mosi), .out_buf(cfg_spi_buffer));
// Shift input in
spi_master_in spi_in(.reset(pid_rst), .clk(clk),
.miso(pv_in_miso), .start(pv_stb),
.out_buf(in_pv), .sck(pv_in_clk), .cs(pv_in_cs));
// Shift output out
spi_master_out spi_out(.reset(pid_rst), .clk(clk), .in_buf(out),
.start(pid_stb_d1),
.sck(out_clk), .cs(out_cs), .mosi(out_mosi));
// PID core
pid pid (.reset(pid_rst), .clk(clk), .pv_stb(pid_stb),
.sp(sp), .pv(in_pv),
.kp(kp), .ki(ki),
.stimulus(out));
strobe #(.BITS(16)) pv_stb_gen(.reset(reset), .clk(clk), .out(pv_stb));
assign pid_stb = pv_in_cs_hist[0] && !pv_in_cs_hist[1];
always @(posedge clk) begin
if (reset) begin
pid_stb_d1 <= 'b0;
pv_in_cs_hist <= 'b0;
end else begin
pv_in_cs_hist <= { pv_in_cs_hist[0], pv_in_cs };
pid_stb_d1 <= pid_stb;
end
end
endmodule |
module edge_detect (
input reset,
input clk,
input sig,
input pol,
output out
);
reg sigin;
reg siglast;
assign out = reset ? 1'b0 : (pol ? ((!siglast) && sigin) : (siglast && (!sigin)));
always @(posedge clk) begin
{ siglast, sigin } <= { sigin, sig };
//sigin <= sig;
//siglast <= sigin;
end
endmodule |
module strobe #(
parameter BITS=8
) (
input reset,
input clk,
output out
);
reg [BITS-1:0] count;
wire [BITS-1:0] next;
assign next = count + 'b1;
assign out = next == 'b0;
always @(posedge clk) begin
if (reset) begin
count <= 'b0;
end else begin
count <= next;
end
end
endmodule |
module rglenn_hex_to_7_seg (
input [7:0] io_in,
output [7:0] io_out
);
wire latch = io_in[0];
wire blank = io_in[1];
wire [4:0] data = io_in[5:2];
wire [6:0] led_out;
assign io_out[6:0] = blank ? 7'b0000000 : led_out;
assign io_out[7] = io_in[6]; // decimal point
// external clock is 1000Hz, so need 10 bit counter
reg [3:0] data_reg;
always @(posedge latch) begin
data_reg <= data;
end
// instantiate segment display
hex2seg7 hex2seg7(.data(data_reg), .segments(led_out));
endmodule |
module browndeer_rv8u(
// input in_clk,
// input [7:1] io_in,
input [7:0] io_in, // ZZZ
output [7:0] io_out
// output [BITS-3:0] debug_pc,
// output [IBITS-1:0] debug_instr,
// output [3:0] debug_valid_out,
//
// input [RBITS-1:0] debug_reg_sel,
// output reg [BITS-1:0] debug_reg_dout
);
wire in_clk; // ZZZ
///////////////////////////////////////////////////////////////////////////
////////////////////////////////
////////// Parameters //////////
////////////////////////////////
parameter BITS = 8;
parameter IBITS = 16;
parameter RBITS = 3;
parameter NREG = 8;
///////////////////////////////////////////////////////////////////////////
//////////////////////////////////
////////// Declarations //////////
//////////////////////////////////
/// pipeline control
wire inval;
wire valid_out0;
wire valid_out1;
reg valid_out3;
/// flow control
reg [BITS-3:0] pc;
reg [BITS-3:0] pc_1;
reg [BITS-3:0] pc_2;
wire pc_jump;
reg [BITS-3:0] jump_addr;
/// instr
reg [IBITS-1:0] instr;
reg [IBITS-1:0] instr_2;
/// hazard
reg [NREG-1:0] ldr_hzd;
/// reg control
wire [RBITS-1:0] rd;
wire [RBITS-1:0] rs1;
wire [RBITS-1:0] rs2;
wire reg_we;
wire reg_we_arb;
reg [BITS-1:0] rd_din;
reg [BITS-1:0] nxt_rd_din;
reg [RBITS-1:0] rd_sel_arb;
reg [BITS-1:0] rs1_dout;
reg [BITS-1:0] rs2_dout;
reg [RBITS-1:0] rd_3;
/// imm operand
wire ri;
reg [BITS-1:0] imm;
/// reg dependency
wire use_rd_e1;
wire use_rd_e2;
wire use_rs1;
wire use_rs2;
/// IALU
reg [3:0] op;
wire [BITS-1:0] op_result;
wire cc_zero;
wire cc_neg;
wire cc_v;
/// ins_
wire reg_wen;
wire ins_br;
wire ins_jal;
wire ins_jalr;
wire ins_str;
wire ins_ldr;
wire ins_halt;
wire ins_lui;
reg ins_ldr_3;
reg ri_3;
/// bits alias probably not necessary
wire [2:0] funct3;
///////////////////////////////////////////////////////
////////// Declarations PIPELINE_STAGE_0_ILR //////////
///////////////////////////////////////////////////////
// pipeline control
reg nxt_valid0;
// flow control
reg [BITS-3:0] pc0;
reg [BITS-3:0] nxt_pc, nxt_pc0;
reg valid0;
///////////////////////////////////////////////////////
/////////// Declarations PIPELINE STAGE 1 IL //////////
///////////////////////////////////////////////////////
wire [IBITS-1:0] nxt_instr;
reg valid1;
///////////////////////////////////////////////////////////////////////////
////////// Declarations PIPELINE STAGE 2 ID ///////////////////////////////
///////////////////////////////////////////////////////////////////////////
wire en2;
reg [3:0] imm3210;
reg valid2;
///////////////////////////////////////////////////////////////////////////
////////// Pipeline Stage 3 E1 Declarations ///////////////////////////////
///////////////////////////////////////////////////////////////////////////
wire [BITS-1:0] arg0;
reg [BITS-1:0] arg1;
reg stall;
reg ben;
///////////////////////////////////////////////////////////////////////////
////////// Pipeline Stage 4 E2 Declarations ///////////////////////////////
///////////////////////////////////////////////////////////////////////////
wire en4;
//////////////////////////////////////////////
////////// ISA Decoder Declarations //////////
//////////////////////////////////////////////
wire rv_itype, rv_stype, rv_btype;
wire rv_op, rv_op_imm;
///////////////////////////////////////
////////// IALU Declarations //////////
///////////////////////////////////////
wire [BITS-1:0] a_result_sub;
wire [BITS-1:0] a_result_srl;
reg [BITS-1:0] a_result;
reg [7:0] a_sx;
reg [BITS-1:0] a_sign_extend;
wire [4:0] a_shamt;
wire run;
wire run_not_stall;
assign run = (~ rst);
assign run_not_stall = run & (~ stall);
/////////////////////////
////////// DES //////////
/////////////////////////
wire des_clk_out;
wire [5:0] des_sin;
wire [7:0] des_sout;
wire [31:0] des_din;
wire [23:0] des_dout;
//////////////////////////
////////// core //////////
//////////////////////////
wire clk;
wire rst;
reg halt;
wire [BITS-3:0] imem_addr;
wire [IBITS-1:0] imem_dout;
wire [BITS-1:0] dmem_addr;
wire [BITS-1:0] dmem_din;
wire [BITS-1:0] dmem_dout;
wire dmem_we;
wire dmem_en;
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
////////// DES ////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
des des(
.in_clk (in_clk),
.rst (rst),
.des_sin (des_sin),
.des_sout (des_sout),
.des_din (des_din),
.des_dout (des_dout),
.des_clk_out (des_clk_out)
);
assign in_clk = io_in[0]; // ZZZ
assign rst = io_in[1];
assign des_sin = io_in[7:2];
assign io_out = des_sout;
assign clk = des_clk_out;
assign imem_dout[15:0] = des_dout[15:0];
assign dmem_dout = des_dout[23:16];
assign des_din[5:0] = imem_addr;
assign des_din[13:6] = dmem_addr;
assign des_din[21:14] = dmem_din;
assign des_din[22] = dmem_we;
assign des_din[23] = dmem_en;
assign des_din[24] = halt;
assign des_din[31:25] = 7'd0;
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
////////// PIPELINE STAGE 0 (ILR) /////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
/// pipeline control ///
assign valid_out0 = valid0 & ~ inval;
always @ (posedge clk)
begin
if (rst) begin
valid0 <= 0;
end
else if (run) begin
if (stall)
valid0 <= valid_out0;
else
valid0 <= 1;
end
else begin
valid0 <= valid_out0;
end
end
/// flow control ///
always @ (*)
begin
if (pc_jump) begin
nxt_pc0 = jump_addr;
nxt_pc = jump_addr + 1;
end
else if (stall) begin
nxt_pc0 = pc0;
nxt_pc = pc;
end
else begin
nxt_pc0 = pc;
nxt_pc = pc + 1;
end
end
assign imem_addr = nxt_pc0;
always @ (posedge clk)
begin
if (rst) begin
pc0 <= 0;
pc <= 0;
end
else if (run) begin
pc0 <= nxt_pc0;
pc <= nxt_pc;
end
else begin
pc0 <= pc0;
pc <= pc;
end
end
///////////////////////////////////////////////////////////////////////////
////////// PIPELINE STAGE 1 (IL) //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
/// pipeline control ///
assign valid_out1 = valid1 & ~ inval;
always @ (posedge clk)
begin
if (rst) begin
valid1 <= 0;
pc_1 <= 0;
end
else if (run_not_stall) begin
valid1 <= valid_out0;
pc_1 <= pc;
end
else begin
valid1 <= valid_out1;
pc_1 <= pc_1;
end
end
/// generate instruction ///
assign nxt_instr = imem_dout[IBITS-1:0];
always @ (posedge clk)
begin
if (rst)
instr <= 0;
else if (run_not_stall & valid_out0)
instr <= nxt_instr;
else
instr <= instr;
end
///////////////////////////////////////////////////////////////////////////
////////// PIPELINE STAGE 2 (ID) //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
/// pipeline control ///
assign en2 = valid_out1;
always @ (posedge clk)
begin
if (rst) begin
valid2 <= 0;
end
else if (run_not_stall) begin
valid2 <= valid_out1;
end
else begin
valid2 <= valid2;
end
end
/// pc, instr data flow
always @ (posedge clk)
begin
if (rst) begin
pc_2 <= 0;
instr_2 <= 0;
end
else if (run_not_stall) begin
pc_2 <= pc_1;
if (valid_out1)
instr_2 <= instr;
else
instr_2 <= 16'hffff;
end
else begin
pc_2 <= pc_2;
instr_2 <= instr_2;
end
end
///////////////////////////////////////////////////////////////////////////
////////// PIPELINE STAGE 3 (E1) //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
always @ (posedge clk)
begin
if (rst)
valid_out3 <= 0;
else if (run_not_stall)
valid_out3 <= valid2;
else if (run & en4)
valid_out3 <= 0;
else
valid_out3 <= valid_out3;
end
assign rd = instr_2[5:3];
assign funct3 = instr_2[8:6];
assign rs1 = instr_2[11:9];
assign rs2[1:0] = instr_2[13:12];
assign rs2[2] = 0;
assign ins_lui = (instr_2[2:0] == 3'b111);
assign ins_jal = (instr_2[2:0] == 3'b110);
assign ins_jalr = (instr_2[2:0] == 3'b100);
assign rv_op_imm = (instr_2[2:0] == 3'b001);
assign rv_op = (instr_2[2:0] == 3'b011);
assign ins_br = (instr_2[2:0] == 3'b010);
assign ins_ldr = ((instr_2[2:0] == 3'b000) & (~ funct3[2]));
assign ins_str = ((instr_2[2:0] == 3'b000) & funct3[2]);
assign use_rd_e1 = reg_wen | ins_jal | ins_jalr | ins_lui;
assign use_rd_e2 = (~ funct3[2]) & ins_ldr;
assign use_rs1 = ins_ldr | reg_wen | ins_jalr | ins_br | ins_str;
assign use_rs2 = (reg_wen & ~ ri_3) | ins_br | ins_str;
assign ins_halt = (instr_2[2:0] == 3'b000) & (funct3 == 3'b000);
assign rv_itype = ins_ldr | rv_op_imm | ins_jalr;
assign rv_stype = ins_str;
assign rv_btype = ins_br;
assign ri = rv_itype | rv_stype;
assign reg_wen = rv_op | rv_op_imm;
always @ (*)
begin
if (ins_str | ins_ldr | ins_br)
op[2:0] = 3'b000;
else
op[2:0] = funct3;
op[3] = ins_br | ((rv_op | ( rv_op_imm & funct3[2])) & instr_2[15]);
end
always @ (*)
begin
if (rv_itype)
imm3210 = { instr_2[15:12] };
else
imm3210 = { instr_2[14], instr_2[5:3] };
end
always @ (*)
begin
if (rv_itype|rv_btype|rv_stype)
imm = { instr_2[15], instr_2[15], instr_2[15], instr_2[15], imm3210 };
else
imm = instr_2[13:6];
end
assign reg_we = valid2
& (reg_wen|ins_jal|ins_jalr|ins_lui) & (~ stall);
assign dmem_we = valid2 & ins_str & (~ stall);
assign arg0 = rs1_dout;
always @ (*)
begin
if (ri) begin
arg1 = imm[BITS-1:0];
end
else
arg1 = rs2_dout;
end
/// IALU ///
assign a_shamt = arg1[4:0];
assign a_result_sub = arg0 - arg1;
assign a_result_srl = arg0 >> a_shamt;
always @ (*)
begin
case (arg1[2:0])
3'b000: a_sx = 8'b00000000;
3'b001: a_sx = 8'b10000000;
3'b010: a_sx = 8'b11000000;
3'b011: a_sx = 8'b11100000;
3'b100: a_sx = 8'b11110000;
3'b101: a_sx = 8'b11111000;
3'b110: a_sx = 8'b11111100;
3'b111: a_sx = 8'b11111110;
endcase
if (arg0[BITS-1])
a_sign_extend = a_sx;
else
a_sign_extend = 8'd0;
end
always @ (*)
begin
case (op[2:0])
3'b000: begin
if (op[3])
a_result = a_result_sub;
else
a_result = arg0 + arg1;
end
3'b001: begin
a_result = arg0 << a_shamt; // sll
end
3'b010: begin
a_result = { 7'd0, cc_neg }; // slt
end
3'b011: begin
a_result = { 7'd0, cc_v}; // sltu
end
3'b100: begin
a_result = arg0 ^ arg1; // xor
end
3'b101: begin
if (op[3])
a_result = a_sign_extend | a_result_srl; // sra
else
a_result = a_result_srl; // srl
end
3'b110: begin
a_result = arg0 | arg1;
end
3'b111: begin
a_result = arg0 & arg1;
end
endcase
end
assign cc_neg = a_result_sub[BITS-1];
assign cc_zero = (a_result_sub == 0);
assign cc_v = ( cc_neg & ~(arg0[BITS-1] ^ arg1[BITS-1]))
| ((~arg0[BITS-1]) & arg1[BITS-1] );
assign op_result = a_result;
assign dmem_addr = op_result[BITS-1:0];
assign dmem_din[BITS-1:0] = rs2_dout;
assign dmem_en = (ins_str | ins_ldr) & valid2 & (~ stall);
always @ (*)
begin
if (ins_lui)
rd_din = { imm[4:0], 3'd0 };
else if (ins_jal|ins_jalr)
rd_din = { 2'b00, pc_2 };
else
rd_din = op_result;
end
always @ (*)
begin
case(funct3)
3'b000 : ben = cc_zero; // eq
3'b001 : ben = (~cc_zero); // ne
3'b010 : ben = 0;
3'b011 : ben = 0;
3'b100 : ben = cc_neg; // lt
3'b101 : ben = (cc_zero | (~cc_neg)); // ge
3'b110 : ben = cc_v; // ltu
3'b111 : ben = (cc_zero | (~cc_v)); // geu
endcase
end
always @ (*)
begin
if (ins_jalr)
jump_addr = op_result[BITS-3:0];
else
jump_addr = pc_2 + { imm[BITS-3:0] };
end
assign pc_jump = valid2 & ((ben & ins_br) | ins_jal | ins_jalr);
assign inval = pc_jump & (~ stall);
always @ (posedge clk)
begin
if (rst) begin
halt <= 0;
end
else if (run_not_stall & valid2) begin
halt <= ins_halt;
end
else begin
halt <= halt;
end
end
always @ (posedge clk)
begin
if (rst) begin
ins_ldr_3 <= 0;
rd_3 <= 0;
ri_3 <= 0;
end
else if (run_not_stall) begin
ins_ldr_3 <= ins_ldr;
rd_3 <= rd;
ri_3 <= ri;
end
else begin
ins_ldr_3 <= ins_ldr_3;
rd_3 <= rd_3;
ri_3 <= ri_3;
end
end
always @ (*)
begin
if ( ldr_hzd == 'd0 )
stall = 0;
else if ( (use_rs1 & ldr_hzd[rs1]) | (use_rs2 & ldr_hzd[rs2])) // RAW HZD
stall = 1;
else if ( (use_rd_e2 & ldr_hzd[rd]) | (use_rd_e1) ) // WAW conflict
stall = 1;
else
stall = 0;
end
///////////////////////////////////////////////////////////////////////////
////////// PIPELINE STAGE 4 (E2) //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
assign en4 = valid_out3 & (ins_ldr_3 );
always @ (*)
begin
if (en4 & ins_ldr_3) begin
rd_sel_arb = rd_3;
end
else begin
rd_sel_arb = rd;
end
end
assign reg_we_arb = reg_we | (en4 & ins_ldr_3);
///////////////////////////////////////////////////////////////////////////
////////// REGISTERS //////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
/// write register
always @ (*)
begin
if (en4 & ins_ldr_3) begin
nxt_rd_din = dmem_dout[BITS-1:0];
end
else begin
nxt_rd_din = rd_din;
end
end
registers registers(
.clk (clk),
.run (run),
.we (reg_we_arb),
.rd (rd_sel_arb),
.rs1 (rs1),
.rs2 (rs2),
.rd_din (nxt_rd_din),
.rs1_dout (rs1_dout),
.rs2_dout (rs2_dout)
// .debug_reg_sel (debug_reg_sel),
// .debug_reg_dout (debug_reg_dout)
);
///////////////////////////////////////////////////////////////////////////
/////////////////////////////
//////// Hazard ////////
/////////////////////////////
always @ (posedge clk)
begin
if (rst) begin
ldr_hzd <= 0;
end
else if (run)
if (( ~(rd==0)) & (ins_ldr ) & ~ stall) begin
ldr_hzd <= ('d1 << rd);
end
else begin
ldr_hzd <= 0;
end
else begin
ldr_hzd <= ldr_hzd;
end
end
///////////////////////////////////////////////////////////////////////////
///////////////////////////
//////// DEBUG ////////
///////////////////////////
// assign debug_pc = pc_2;
// assign debug_instr[15:0] = instr_2;
// assign debug_valid_out = { valid_out0, valid_out1, valid2, valid_out3 };
endmodule |
module user_module_347417602591556180(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[7];
wire net7;
wire net8;
wire net9 = 1'b0;
wire net10 = 1'b1;
wire net11 = 1'b1;
wire net12;
wire net13;
wire net14;
wire net15 = 1'b0;
wire net16 = 1'b0;
wire net17 = 1'b0;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52;
wire net53;
assign io_out[1] = net7;
assign io_out[2] = net7;
assign io_out[3] = net8;
assign io_out[4] = net8;
assign io_out[5] = net8;
dff_cell flipflop1 (
.d (net12),
.clk (net1),
.q (net13)
);
dff_cell flipflop2 (
.d (net14),
.clk (net1),
.q (net7)
);
or_cell gate1 (
.a (net13),
.b (net7),
.out (net8)
);
and_cell gate2 (
.a (net18),
.b (net19),
.out (net20)
);
and_cell gate3 (
.a (net20),
.b (net13),
.out (net21)
);
or_cell gate4 (
.a (net21),
.b (net22),
.out (net23)
);
or_cell gate5 (
.a (net23),
.b (net24),
.out (net25)
);
and_cell gate6 (
.a (net18),
.b (net26),
.out (net27)
);
and_cell gate7 (
.a (net27),
.b (net13),
.out (net22)
);
and_cell gate8 (
.a (net18),
.b (net28),
.out (net29)
);
and_cell gate9 (
.a (net29),
.b (net13),
.out (net24)
);
not_cell not1 (
.in (net30),
.out (net18)
);
buffer_cell not2 (
.in (net31),
.out (net26)
);
buffer_cell not3 (
.in (net32),
.out (net28)
);
or_cell gate10 (
.a (net30),
.b (net25),
.out (net12)
);
and_cell gate11 (
.a (net13),
.b (net18),
.out (net33)
);
and_cell gate12 (
.a (net33),
.b (net34),
.out (net35)
);
and_cell gate13 (
.a (net35),
.b (net36),
.out (net37)
);
and_cell gate14 (
.a (net18),
.b (net7),
.out (net38)
);
or_cell gate15 (
.a (net39),
.b (net38),
.out (net14)
);
and_cell gate16 (
.a (net37),
.b (net40),
.out (net39)
);
buffer_cell not4 (
.in (net41),
.out (net40)
);
buffer_cell gate17 (
.in (net2),
.out (net30)
);
buffer_cell gate21 (
.in (net42),
.out (net19)
);
buffer_cell gate22 (
.in (net43),
.out (net36)
);
buffer_cell gate23 (
.in (net44),
.out (net34)
);
not_cell gate27 (
.in (net4),
.out (net45)
);
buffer_cell not8 (
.in (net4),
.out (net46)
);
mux_cell mux7 (
.a (net46),
.b (net45),
.sel (net47),
.out (net31)
);
mux_cell mux8 (
.a (net45),
.b (net46),
.sel (net47),
.out (net44)
);
dff_cell flipflop4 (
.d (net4),
.clk (net6),
.q (net47)
);
not_cell gate18 (
.in (net3),
.out (net48)
);
buffer_cell not9 (
.in (net3),
.out (net49)
);
mux_cell mux9 (
.a (net49),
.b (net48),
.sel (net50),
.out (net42)
);
mux_cell mux10 (
.a (net48),
.b (net49),
.sel (net50),
.out (net41)
);
dff_cell flipflop5 (
.d (net3),
.clk (net6),
.q (net50)
);
not_cell gate28 (
.in (net5),
.out (net51)
);
buffer_cell not10 (
.in (net5),
.out (net52)
);
mux_cell mux11 (
.a (net52),
.b (net51),
.sel (net53),
.out (net32)
);
mux_cell mux12 (
.a (net51),
.b (net52),
.sel (net53),
.out (net43)
);
dff_cell flipflop6 (
.d (net5),
.clk (net6),
.q (net53)
);
endmodule |
module user_module_348540666182107731(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17 = 1'b0;
wire net18 = 1'b1;
wire net19 = 1'b1;
wire net20;
wire net21;
wire net22;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net11;
assign io_out[3] = net12;
assign io_out[4] = net13;
assign io_out[5] = net14;
assign io_out[6] = net15;
assign io_out[7] = net16;
and_cell gate1 (
);
or_cell gate2 (
);
xor_cell gate3 (
);
nand_cell gate4 (
.a (net6),
.b (net14),
.out (net13)
);
not_cell gate5 (
);
buffer_cell gate6 (
);
mux_cell mux1 (
);
dff_cell flipflop1 (
.d (net2),
.clk (net1),
.q (net9),
.notq (net10)
);
dff_cell flop1 (
);
dffsr_cell flipflop2 (
.d (net2),
.clk (net3),
.s (net4),
.r (net5),
.q (net11),
.notq (net12)
);
nand_cell gate7 (
.a (net13),
.b (net7),
.out (net14)
);
and_cell gate8 (
.a (net2),
.b (net8),
.out (net20)
);
or_cell gate9 (
.a (net2),
.b (net8),
.out (net21)
);
and_cell gate10 (
.a (net21),
.b (net15),
.out (net22)
);
or_cell gate11 (
.a (net20),
.b (net22),
.out (net15)
);
not_cell gate12 (
.in (net1),
.out (net16)
);
endmodule |
module jleightcap_top( input wire [7:0] io_in
, output wire [7:0] io_out
);
top _top( .clk(io_in[0])
, .rst(io_in[1])
, .instr(io_in[7:2])
, .io_out(io_out)
);
endmodule |
module user_module_346553315158393428(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6;
wire net7 = 1'b0;
wire net8 = 1'b1;
wire net9;
wire net10;
assign io_out[0] = net6;
xor_cell gate3 (
.a (net9),
.b (net4),
.out (net10)
);
mux_cell mux1 (
.a (net1),
.b (net2),
.sel (net3),
.out (net9)
);
xor_cell gate1 (
.a (net10),
.b (net5),
.out (net6)
);
endmodule |
module femto_top
#(
parameter OPSIZE = 3, //Number of opcodes, power of 2 (3 => 2**3 = 8 opcodes)
parameter NUMRF = 2, //Number of registers in register file, power of 2 (2 => 2**2 = 4 registers)
parameter SIZE = 4 //Size of data in bits
)
(
input [7:0] io_in,
output [7:0] io_out
);
wire clk=io_in[0];
reg[1:0] mode;
reg change_state;
reg[1:0] next_mode;
always @(*) begin
if(io_in[3:1]==0&&io_in[7:6]==2'b10)
begin
change_state=1'b1;
next_mode=io_in[5:4];
end
else begin
change_state=0;
next_mode=0;
end
end
always @(posedge clk) begin
if(change_state==1) begin
mode<=next_mode;
end
end
//Mode:
//00: No action
//01: Run (Read instruction buffer)
//10: Fill (Write instruction buffer)
//11: N/A
wire wren=mode[1]&&(io_in[3:1]!=0&&io_in[7:6]!=2'b10); //Don't write when changing state
wire rden=mode[0];
wire[6:0] instr_in=io_in[7:1];
wire[6:0] instr_out;
ibuffer
#(
.ENTRIES(6)
)
ibuf
(
.clk(clk), .wren(wren), .rden(rden),
.instr_in(instr_in),
.instr_out(instr_out)
);
//Decode (from interface)
// wire[OPSIZE-1:0] op=io_in[1+:OPSIZE]; //opcode wire
// wire [NUMRF-1:0] reg_0=io_in[1+OPSIZE+:NUMRF]; //register address 0 (Dest)
// wire [NUMRF-1:0] reg_1=io_in[1+OPSIZE+NUMRF+:NUMRF]; //register address 1 (Src)
wire[OPSIZE-1:0] op=instr_out[2:0]; //opcode wire
wire [NUMRF-1:0] reg_0=instr_out[4:3]; //register address 0 (Dest)
wire [NUMRF-1:0] reg_1=instr_out[6:5]; //register address 1 (Src)
wire valid=(op=={(OPSIZE){1'b1}})?1:0;
wire rd=(op!=3'h6&&op!=3'h0&&op!=3'h1);
wire wr=(op==3'h6);
reg[3:0] value;
wire [SIZE-1:0] data_0,data_1,data_out;
reg_file #( .NUMRF(NUMRF), .SIZE(SIZE)) rf (.clk(clk), .rd(rd), .wr(wr), .reg_out(reg_1),.reg_in(reg_0),.data_in(data_0),.data_out(data_1));
//Execute
alu_gen #(.OPSIZE(OPSIZE), .SIZE(SIZE)) alu (.clk(clk), .op(op),.inp(data_1),.outp(data_out));
//Output
assign data_0=data_out;
always @(posedge clk) begin
if(valid==1) begin
value<=data_out;
end
end
seg7 seg(.value(value),.segments(io_out[6:0]));
endmodule |
module krasin_3_bit_8_channel_pwm_driver (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire pset = io_in[1];
wire [2:0] addr = io_in[4:2];
wire [2:0] level = io_in[7:5];
wire [7:0] pwm_out;
assign io_out[7:0] = pwm_out;
// This register is used to determine if the execution just started and we need to reset.
// It's a bullshit implementation and will most likely not work. I am curious to test it anyway.
// The idea is that initially this register has a somewhat random value. If it does not match what we expect,
// we're in a reset mode and set this register to the expected state + reset all other registers.
// This is not a great way, as it does not guarantee anything, but I already use all input pins and
// like to live dangerously.
reg[8:0] reset_canary = 0;
// 3-bit PWM counter that goes from 0 to 7.
reg [2:0] counter;
function is_reset (input [8:0] a);
begin
is_reset = (a != 8'b01010101);
end
endfunction
// PWM level for channel0.
// 0 means always off.
// 1 means that PWM will be on for just 1 clock cycle and then off for the other 6, giving 1/7 on average.
// 6 means 6/7 on.
// 7 means always on.
reg [2:0] pwm0_level;
// The rest of the channels.
reg [2:0] pwm1_level;
reg [2:0] pwm2_level;
reg [2:0] pwm3_level;
reg [2:0] pwm4_level;
reg [2:0] pwm5_level;
reg [2:0] pwm6_level;
reg [2:0] pwm7_level;
function is_on(input [3:0] level, input[3:0] counter);
begin
is_on = (counter < level);
end
endfunction // is_on
assign pwm_out[0] = is_on(pwm0_level, counter);
assign pwm_out[1] = is_on(pwm1_level, counter);
assign pwm_out[2] = is_on(pwm2_level, counter);
assign pwm_out[3] = is_on(pwm3_level, counter);
assign pwm_out[4] = is_on(pwm4_level, counter);
assign pwm_out[5] = is_on(pwm5_level, counter);
assign pwm_out[6] = is_on(pwm6_level, counter);
assign pwm_out[7] = is_on(pwm7_level, counter);
// external clock is 1000Hz.
always @(posedge clk) begin
// if reset, set counter and pwm levels to 0
if (is_reset(reset_canary)) begin
reset_canary = 8'b01010101;
counter <= 0;
pwm0_level <= 0;
pwm1_level <= 0;
pwm2_level <= 0;
pwm3_level <= 0;
pwm4_level <= 0;
pwm5_level <= 0;
pwm6_level <= 0;
pwm7_level <= 0;
end else begin // if (is_reset(reset_canary))
if (counter == 6) begin
// Roll over.
counter <= 0;
end else begin
// increment counter
counter <= counter + 1'b1;
end
if (pset) begin
case (addr)
0: pwm0_level <= level;
1: pwm1_level <= level;
2: pwm2_level <= level;
3: pwm3_level <= level;
4: pwm4_level <= level;
5: pwm5_level <= level;
6: pwm6_level <= level;
7: pwm7_level <= level;
endcase
end // if (set)
end
end // always @ (posedge clk)
endmodule |
module user_module_348242239268323922(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[7];
wire net3;
wire net4;
wire net5;
wire net6;
wire net7;
wire net8;
wire net9;
wire net10;
wire net11 = 1'b0;
wire net12 = 1'b1;
wire net13 = 1'b1;
wire net14 = 1'b0;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48 = 1'b0;
wire net49 = 1'b0;
wire net50 = 1'b0;
wire net51 = 1'b0;
wire net52;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59;
wire net60;
wire net61;
wire net62;
wire net63;
wire net64;
wire net65;
wire net66;
wire net67;
wire net68;
wire net69;
wire net70;
wire net71;
wire net72;
wire net73;
wire net74;
wire net75;
wire net76;
wire net77;
wire net78;
wire net79 = 1'b0;
wire net80;
wire net81;
wire net82;
wire net83;
wire net84;
wire net85;
wire net86 = 1'b0;
wire net87 = 1'b0;
wire net88;
wire net89;
wire net90;
wire net91;
wire net92;
wire net93;
wire net94;
wire net95;
wire net96;
wire net97;
wire net98;
wire net99;
wire net100;
wire net101;
wire net102;
wire net103;
wire net104;
wire net105;
wire net106;
wire net107;
wire net108;
wire net109;
wire net110;
wire net111;
wire net112;
wire net113;
wire net114;
wire net115;
wire net116;
wire net117;
wire net118;
wire net119;
wire net120;
wire net121;
wire net122;
assign io_out[0] = net3;
assign io_out[1] = net4;
assign io_out[2] = net5;
assign io_out[3] = net6;
assign io_out[4] = net7;
assign io_out[5] = net8;
assign io_out[6] = net9;
assign io_out[7] = net10;
or_cell gate2 (
);
xor_cell gate3 (
);
nand_cell gate4 (
);
not_cell gate5 (
);
buffer_cell gate6 (
);
dff_cell flipflop (
);
mux_cell mux1 (
);
dff_cell flipflop1 (
.d (net15),
.clk (net1),
.q (net16),
.notq (net15)
);
dff_cell flipflop2 (
.d (net17),
.clk (net16),
.q (net18),
.notq (net17)
);
dff_cell flipflop3 (
.d (net19),
.clk (net18),
.q (net20),
.notq (net19)
);
dff_cell flipflop4 (
.d (net21),
.clk (net20),
.q (net22),
.notq (net21)
);
dff_cell flipflop5 (
.d (net23),
.clk (net22),
.q (net24),
.notq (net23)
);
dff_cell flipflop6 (
.d (net25),
.clk (net24),
.q (net26),
.notq (net25)
);
dff_cell flipflop7 (
.d (net27),
.clk (net26),
.q (net28),
.notq (net27)
);
dff_cell flipflop8 (
.d (net29),
.clk (net28),
.q (net30),
.notq (net29)
);
dff_cell flipflop9 (
.d (net31),
.clk (net30),
.q (net32),
.notq (net31)
);
dff_cell flipflop10 (
.d (net33),
.clk (net32),
.q (net34),
.notq (net33)
);
dff_cell flipflop11 (
.d (net35),
.clk (net34),
.q (net36),
.notq (net35)
);
dff_cell flipflop12 (
.d (net37),
.clk (net36),
.q (net38),
.notq (net37)
);
dff_cell flipflop13 (
.d (net39),
.clk (net38),
.q (net40),
.notq (net39)
);
dff_cell flipflop14 (
.d (net41),
.clk (net40),
.q (net42),
.notq (net41)
);
dff_cell flipflop15 (
.d (net43),
.clk (net42),
.q (net44),
.notq (net43)
);
dff_cell flipflop16 (
.d (net45),
.clk (net44),
.q (net46),
.notq (net45)
);
mux_cell mux2 (
.a (net24),
.b (net26),
.sel (net42),
.out (net47)
);
mux_cell mux3 (
.a (net24),
.b (net22),
.sel (net42),
.out (net52)
);
mux_cell mux4 (
.a (net52),
.b (net47),
.sel (net53),
.out (net10)
);
not_cell gate7 (
.in (net40),
.out (net54)
);
not_cell gate8 (
.in (net38),
.out (net55)
);
dff_cell flipflop17 (
.d (net56),
.clk (net46),
.q (net53),
.notq (net56)
);
and_cell gate9 (
.a (net54),
.b (net55),
.out (net57)
);
and_cell gate10 (
.a (net54),
.b (net38),
.out (net58)
);
and_cell gate11 (
.a (net40),
.b (net55),
.out (net59)
);
and_cell gate12 (
.a (net40),
.b (net38),
.out (net60)
);
not_cell gate20 (
.in (net1),
.out (net61)
);
dff_cell flipflop18 (
.d (net62),
.clk (net61),
.q (net3)
);
dff_cell flipflop19 (
.d (net63),
.clk (net61),
.q (net4)
);
dff_cell flipflop20 (
.d (net64),
.clk (net61),
.q (net5)
);
dff_cell flipflop21 (
.d (net65),
.clk (net61),
.q (net6)
);
dff_cell flipflop22 (
.d (net66),
.clk (net61),
.q (net7)
);
dff_cell flipflop23 (
.d (net67),
.clk (net61),
.q (net8)
);
dff_cell flipflop24 (
.d (net68),
.clk (net61),
.q (net9)
);
mux_cell mux7 (
.a (net60),
.b (net69),
.sel (net2),
.out (net62)
);
mux_cell mux8 (
.a (net70),
.b (net71),
.sel (net2),
.out (net63)
);
mux_cell mux9 (
.a (net70),
.b (net72),
.sel (net2),
.out (net64)
);
mux_cell mux10 (
.a (net73),
.b (net74),
.sel (net2),
.out (net65)
);
mux_cell mux11 (
.a (net75),
.b (net76),
.sel (net2),
.out (net66)
);
mux_cell mux12 (
.a (net75),
.b (net77),
.sel (net2),
.out (net67)
);
mux_cell mux13 (
.a (net78),
.b (net79),
.sel (net2),
.out (net68)
);
dff_cell flipflop26 (
.d (net80),
.clk (net53),
.q (net81),
.notq (net80)
);
dff_cell flipflop27 (
.d (net82),
.clk (net81),
.q (net83),
.notq (net82)
);
buffer_cell gate13 (
.in (net81),
.out (net84)
);
buffer_cell gate14 (
.in (net83),
.out (net85)
);
mux_cell mux15 (
.a (net59),
.b (net57),
.sel (net84),
.out (net70)
);
mux_cell mux5 (
.a (net57),
.b (net59),
.sel (net84),
.out (net75)
);
mux_cell mux6 (
.a (net60),
.b (net58),
.sel (net85),
.out (net73)
);
mux_cell mux14 (
.a (net58),
.b (net88),
.sel (net85),
.out (net78)
);
or_cell gate15 (
.a (net60),
.b (net58),
.out (net88)
);
dff_cell flipflop25 (
.d (net89),
.clk (net1),
.q (net90),
.notq (net91)
);
dff_cell flipflop30 (
.d (net36),
.clk (net1),
.notq (net92)
);
and_cell gate16 (
.a (net36),
.b (net92),
.out (net93)
);
xor_cell gate17 (
.a (net90),
.b (net93),
.out (net89)
);
and_cell gate18 (
.a (net90),
.b (net93),
.out (net94)
);
dff_cell flipflop28 (
.d (net95),
.clk (net1),
.q (net96),
.notq (net97)
);
xor_cell gate19 (
.a (net96),
.b (net94),
.out (net98)
);
and_cell gate21 (
.a (net96),
.b (net94),
.out (net99)
);
dff_cell flipflop29 (
.d (net100),
.clk (net1),
.q (net101),
.notq (net102)
);
xor_cell gate22 (
.a (net101),
.b (net99),
.out (net103)
);
and_cell gate24 (
);
and_cell gate23 (
.a (net90),
.b (net101),
.out (net104)
);
nand_cell gate25 (
.a (net93),
.b (net104),
.out (net105)
);
and_cell gate26 (
.a (net98),
.b (net105),
.out (net95)
);
and_cell gate27 (
.a (net103),
.b (net105),
.out (net100)
);
and_cell gate1 (
.a (net91),
.b (net97),
.out (net106)
);
and_cell gate29 (
.a (net90),
.b (net97),
.out (net107)
);
and_cell gate31 (
.a (net91),
.b (net96),
.out (net108)
);
and_cell gate33 (
.a (net90),
.b (net96),
.out (net109)
);
and_cell gate28 (
.a (net106),
.b (net102),
.out (net110)
);
and_cell gate30 (
.a (net102),
.b (net107),
.out (net111)
);
and_cell gate32 (
.a (net107),
.b (net101),
.out (net112)
);
and_cell gate34 (
.a (net106),
.b (net101),
.out (net113)
);
or_cell gate35 (
.a (net110),
.b (net109),
.out (net114)
);
or_cell gate36 (
.a (net111),
.b (net113),
.out (net115)
);
or_cell gate37 (
.a (net108),
.b (net112),
.out (net116)
);
mux_cell mux16 (
.a (net110),
.b (net114),
.sel (net85),
.out (net69)
);
mux_cell mux17 (
.a (net111),
.b (net112),
.sel (net84),
.out (net117)
);
mux_cell mux18 (
.a (net115),
.b (net116),
.sel (net84),
.out (net118)
);
mux_cell mux19 (
.a (net117),
.b (net118),
.sel (net85),
.out (net71)
);
mux_cell mux20 (
.a (net108),
.b (net113),
.sel (net84),
.out (net119)
);
mux_cell mux21 (
.a (net116),
.b (net115),
.sel (net84),
.out (net120)
);
mux_cell mux22 (
.a (net119),
.b (net120),
.sel (net85),
.out (net72)
);
mux_cell mux23 (
.a (net109),
.b (net114),
.sel (net85),
.out (net74)
);
mux_cell mux24 (
.a (net113),
.b (net108),
.sel (net84),
.out (net121)
);
mux_cell mux25 (
.a (net121),
.b (net118),
.sel (net85),
.out (net76)
);
mux_cell mux26 (
.a (net112),
.b (net111),
.sel (net84),
.out (net122)
);
mux_cell mux27 (
.a (net122),
.b (net120),
.sel (net85),
.out (net77)
);
endmodule |
module mul4_341521390605697619
(
input [3:0] a,
input [3:0] b,
output [7:0] c
);
wire [3:0]x = b[0] ? a : 0;
wire [3:0]y = b[1] ? a : 0;
wire [3:0]z = b[2] ? a : 0;
wire [3:0]t = b[3] ? a : 0;
assign c = {
add3,
add2[0],
add1[0],
x[0]
};
wire [4:0]add1;
add_341521390605697619 #(.WIDTH(4)) add_1(
.a({1'b0, x[3:1]}),
.b(y),
.c(add1)
);
wire [4:0]add2;
add_341521390605697619 #(.WIDTH(4)) add_2(
.a(add1[4:1]),
.b(z),
.c(add2)
);
wire [4:0]add3;
add_341521390605697619 #(.WIDTH(4)) add_3(
.a(add2[4:1]),
.b(t),
.c(add3)
);
endmodule |
module tt2_tholin_diceroll(
input [7:0] io_in,
output [7:0] io_out
);
wire CLK = io_in[0];
wire RST = io_in[1];
wire ROLL = io_in[2];
wire [7:0] LEDS;
assign io_out[7:0] = LEDS;
dice dice (
.CLK(CLK),
.RST(RST),
.ROLL(ROLL),
.LEDS(LEDS)
);
endmodule |
module c_tt2_mrcs_test (
input [7:0] io_in,
output [7:0] io_out
);
wire net_0 = io_in[0];
wire net_1 = net_0;
wire net_2 = net_0;
wire net_3 = net_0;
wire net_4 = net_0;
wire net_5 = io_in[1];
wire net_6 = net_5;
wire net_7 = net_5;
wire net_8 = net_5;
wire net_9;
wire net_10;
wire net_11;
wire net_12;
wire net_13;
wire net_14;
wire net_15;
wire net_16;
wire net_17;
wire net_18;
assign io_out[0] = net_9;
assign io_out[1] = net_10;
assign io_out[2] = net_11;
assign io_out[3] = net_12;
assign io_out[4] = net_13;
assign io_out[5] = net_14;
assign io_out[6] = net_15;
assign io_out[7] = net_16;
c_BIN_DFF SavedGate_0 (
.in_0(net_1),
.in_1(net_6),
.out_0(net_10),
.out_1(net_11),
.out_2(net_17),
.out_3(net_18)
);
c_BIN_ZOOK_DLATCH SavedGate_1 (
.in_0(net_0),
.in_1(net_5),
.out_0(net_9)
);
c_BIN_NAND_DLATCH SavedGate_2 (
.in_1(net_2),
.in_0(net_7),
.out_0(net_12),
.out_1(net_13)
);
c_BIN_EDGE_DETECTOR SavedGate_3 (
.in_0(net_4),
.out_0(net_16)
);
c_BIN_NAND_SR_LATCH SavedGate_4 (
.in_0(net_3),
.in_1(net_8),
.out_0(net_14),
.out_1(net_15)
);
endmodule |
module c_BIN_DFF (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0,
output [0:0] out_1,
output [0:0] out_2,
output [0:0] out_3
);
wire net_0 = in_0;
wire net_1 = net_0;
wire net_2 = in_1;
wire net_3;
wire net_4;
wire net_5;
wire net_6 = net_4;
wire net_7;
wire net_8;
assign out_0 = net_5;
assign out_1 = net_6;
assign out_2 = net_7;
assign out_3 = net_8;
f_2 LogicGate_0 (
.in_0(net_0),
.out_0(net_3)
);
c_BIN_NAND_DLATCH SavedGate_0 (
.in_0(net_2),
.in_1(net_3),
.out_0(net_4),
.out_1(net_8)
);
c_BIN_NAND_DLATCH SavedGate_1 (
.in_1(net_1),
.in_0(net_4),
.out_0(net_5),
.out_1(net_7)
);
endmodule |
module c_BIN_EDGE_DETECTOR (
input [0:0] in_0,
output [0:0] out_0
);
wire net_0 = in_0;
wire net_1 = net_0;
wire net_2;
wire net_3;
wire net_4;
wire net_5;
assign out_0 = net_5;
f_K00 LogicGate_0 (
.in_1(net_0),
.in_0(net_4),
.out_0(net_5)
);
f_2 LogicGate_1 (
.in_0(net_1),
.out_0(net_2)
);
f_2 LogicGate_2 (
.in_0(net_2),
.out_0(net_3)
);
f_2 LogicGate_3 (
.in_0(net_3),
.out_0(net_4)
);
endmodule |
module c_BIN_NAND_DLATCH (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0,
output [0:0] out_1
);
wire net_0 = in_0;
wire net_1 = net_0;
wire net_2 = in_1;
wire net_3 = net_2;
wire net_4;
wire net_5;
wire net_6;
wire net_7;
wire net_8;
assign out_0 = net_7;
assign out_1 = net_8;
f_22Z LogicGate_0 (
.in_1(net_0),
.in_0(net_2),
.out_0(net_4)
);
f_22Z LogicGate_1 (
.in_1(net_3),
.in_0(net_6),
.out_0(net_5)
);
f_2 LogicGate_2 (
.in_0(net_1),
.out_0(net_6)
);
c_BIN_NAND_SR_LATCH SavedGate_0 (
.in_0(net_4),
.in_1(net_5),
.out_0(net_7),
.out_1(net_8)
);
endmodule |
module c_BIN_NAND_SR_LATCH (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0,
output [0:0] out_1
);
wire net_0 = in_0;
wire net_1 = in_1;
wire net_2;
wire net_3;
wire net_4 = net_2;
wire net_5 = net_3;
assign out_0 = net_4;
assign out_1 = net_5;
f_22Z LogicGate_0 (
.in_1(net_0),
.in_0(net_3),
.out_0(net_2)
);
f_22Z LogicGate_1 (
.in_1(net_2),
.in_0(net_1),
.out_0(net_3)
);
endmodule |
module c_BIN_ZOOK_DLATCH (
input [0:0] in_0,
input [0:0] in_1,
output [0:0] out_0
);
wire net_0 = in_0;
wire net_1 = in_1;
wire net_2;
wire net_3 = net_2;
assign out_0 = net_3;
f_Z00K00KKK LogicGate_0 (
.in_2(net_0),
.in_0(net_2),
.in_1(net_1),
.out_0(net_2)
);
endmodule |
module f_2 (
input wire in_0,
output wire out_0
);
assign out_0 = (in_0 == 0);
endmodule |
module f_22Z (
input wire in_0,
input wire in_1,
output wire out_0
);
assign out_0 = (in_0 == 0 & in_1 == 0) | (in_0 == 0 & in_1 == 1) | (in_0 == 1 & in_1 == 0);
endmodule |
module f_K00 (
input wire in_0,
input wire in_1,
output wire out_0
);
assign out_0 = (in_0 == 1 & in_1 == 1);
endmodule |
module f_Z00K00KKK (
input wire in_0,
input wire in_1,
input wire in_2,
output wire out_0
);
assign out_0 = (in_0 == 0 & in_1 == 1 & in_2 == 0) | (in_0 == 1 & in_1 == 1 & in_2 == 0) | (in_0 == 1 & in_1 == 0 & in_2 == 1) | (in_0 == 1 & in_1 == 1 & in_2 == 1);
endmodule |
module alu_top (
input [7:0] io_in,
output [7:0] io_out
);
alu alu(.A(io_in[7:6]), .B(io_in[5:4]), .ALU_Sel(io_in[3:0]),
.ALU_Out(io_out[6:0]), .CarryOut(io_out[7])
);
endmodule |
module user_module_349803790984020562(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = 1'b1;
wire net8;
wire net9 = 1'b0;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21 = 1'b0;
xor_cell gate11 (
.a (net2),
.b (net5),
.out (net8)
);
xor_cell gate7 (
.a (net8),
.b (net10),
.out (net11)
);
and_cell gate8 (
.a (net8),
.b (net10),
.out (net12)
);
and_cell gate9 (
.a (net2),
.b (net5),
.out (net13)
);
or_cell gate10 (
.a (net12),
.b (net13),
.out (net14)
);
xor_cell gate1 (
.a (net3),
.b (net6),
.out (net15)
);
xor_cell gate2 (
.a (net15),
.b (net14),
.out (net16)
);
and_cell gate3 (
.a (net15),
.b (net14),
.out (net17)
);
and_cell gate4 (
.a (net3),
.b (net6),
.out (net18)
);
or_cell gate5 (
.a (net17),
.b (net18),
.out (net19)
);
and_cell gate6 (
.a (net1),
.b (net4),
.out (net10)
);
xor_cell gate12 (
.a (net1),
.b (net4),
.out (net20)
);
endmodule |
module user_module_348787952842703444(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14 = 1'b0;
wire net15 = 1'b1;
wire net16 = 1'b1;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34 = 1'b0;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net11;
assign io_out[3] = net12;
assign io_out[4] = net13;
xor_cell gate3 (
.a (net17),
.b (net18),
.out (net19)
);
nand_cell gate4 (
.a (net1),
.b (net6),
.out (net17)
);
nand_cell gate1 (
.a (net1),
.b (net5),
.out (net20)
);
nand_cell gate7 (
.a (net2),
.b (net5),
.out (net18)
);
nand_cell gate8 (
.a (net2),
.b (net6),
.out (net21)
);
nand_cell gate9 (
.a (net17),
.b (net18),
.out (net22)
);
nand_cell gate10 (
.a (net22),
.b (net21),
.out (net23)
);
xor_cell gate11 (
.a (net22),
.b (net21),
.out (net24)
);
xor_cell gate2 (
.a (net25),
.b (net26),
.out (net27)
);
nand_cell gate5 (
.a (net3),
.b (net8),
.out (net25)
);
nand_cell gate6 (
.a (net3),
.b (net7),
.out (net28)
);
nand_cell gate12 (
.a (net4),
.b (net7),
.out (net26)
);
nand_cell gate13 (
.a (net4),
.b (net8),
.out (net29)
);
nand_cell gate14 (
.a (net25),
.b (net26),
.out (net30)
);
nand_cell gate15 (
.a (net30),
.b (net29),
.out (net31)
);
xor_cell gate16 (
.a (net30),
.b (net29),
.out (net32)
);
xor_cell xor1 (
.a (net20),
.b (net28),
.out (net33)
);
xor_cell xor2 (
.a (net33),
.b (net34),
.out (net9)
);
nand_cell gate17 (
.a (net34),
.b (net33),
.out (net35)
);
nand_cell gate18 (
.a (net28),
.b (net20),
.out (net36)
);
or_cell or1 (
.a (net35),
.b (net36),
.out (net37)
);
xor_cell xor3 (
.a (net19),
.b (net27),
.out (net38)
);
xor_cell xor4 (
.a (net38),
.b (net37),
.out (net10)
);
nand_cell gate19 (
.a (net37),
.b (net38),
.out (net39)
);
nand_cell gate20 (
.a (net27),
.b (net19),
.out (net40)
);
or_cell or2 (
.a (net39),
.b (net40),
.out (net41)
);
xor_cell xor5 (
.a (net24),
.b (net32),
.out (net42)
);
xor_cell xor6 (
.a (net42),
.b (net41),
.out (net11)
);
nand_cell gate21 (
.a (net41),
.b (net42),
.out (net43)
);
nand_cell gate22 (
.a (net32),
.b (net24),
.out (net44)
);
or_cell or3 (
.a (net43),
.b (net44),
.out (net45)
);
xor_cell xor7 (
.a (net23),
.b (net31),
.out (net46)
);
xor_cell xor8 (
.a (net46),
.b (net45),
.out (net12)
);
nand_cell gate23 (
.a (net45),
.b (net46),
.out (net47)
);
nand_cell gate24 (
.a (net31),
.b (net23),
.out (net48)
);
or_cell or4 (
.a (net47),
.b (net48),
.out (net13)
);
endmodule |
module zoechip #( parameter MAX_COUNT = 1000 ) (
input [7:0] io_in,
output [7:0] io_out
);
wire A,B,C,D,F,G,M;
assign io_out = { 1'b0, D,B,G,F,M,C,A };
wire Z = io_in[0];
wire O = io_in[1];
wire E = io_in[2];
wire f = io_in[3];
assign A = Z+O+E;
assign B =O+E+f;
assign C =Z+O+f;
assign D =Z+O+E+f;
assign F = E+Z;
assign G =E+Z;
assign M = f;
endmodule |
module user_module_skylersaleh(
input [7:0] io_in,
output [7:0] io_out
);
hello_skylersaleh hello_core(
.clk(io_in[0]),
.dip_switch(io_in[7:1]),
.segments(io_out[6:0]),
.decimal(io_out[7])
);
endmodule |
module SPIController (
// System Interfaces
input wire clk,
input wire rst,
// SPI Bus Interfaces
output reg CS0,
output reg CS1,
output reg SPICLK,
output reg MOSI,
input wire MISO,
// Input Signals
input wire Addr15, // Sampled on Phase 01
input wire Read_notWrite, // Sampled on Phase 16
input wire Addr, // Sampled on Phase 18[bit0/LSB], 20[bit1], ..., 44[bit13], 46[bit14/MSB], bit 15 not sampled (see Addr15)
input wire Data, // Sampled on Phase 50[bit0/LSB], 52[bit1], ..., 78[bit14], 80[bit15/MSB]
// Timing Output Signals
output reg ShiftAddr, // Asserted when the Address should be shifted
output reg ShiftDataRead, // Asserted when the data register collecting data read from memory should be shifted
output reg ShiftDataWrite, // Asserted when the data regsiter providing data to be written to memory should be shifted
output reg PresetCarry, // Asserted the clock before data motion starts
output reg EndOfPhase, //
output reg PrepOutput
);
// SPI sequencer
reg [6:0] SPIphase;
always @(posedge clk) begin
if (rst)
SPIphase <= 0;
else if (SPIphase == 83)
SPIphase <= 0;
else
SPIphase <= SPIphase + 1;
end
// SPI bus signal generator
always @(posedge clk) begin
if (SPIphase <= 1) begin
CS0 <= 1;
CS1 <= 1;
SPICLK <= 0;
MOSI <= 0;
end else begin
CS0 <= CSreg;
CS1 <= !CSreg;
if (SPIphase <= 81)
SPICLK <= SPIphase[0];
else
SPICLK <= 0;
if (SPIphase <= 13)
MOSI <= 0;
else if (SPIphase <= 15)
MOSI <= 1;
else if (SPIphase <= 17) begin
if (SPIphase[0] == 0)
MOSI <= Read_notWrite;
end else if (SPIphase <= 47) begin
if (SPIphase[0] == 0)
MOSI <= Addr;
end else if (SPIphase <= 49)
MOSI <= 0;
else begin
if (Read_notWrite)
MOSI <= 0;
else begin
if (SPIphase[0] == 0)
MOSI <= Data;
end
end
end
end
// Generate Address Shift Enable Signals
always @(posedge clk) begin
ShiftAddr <= ((SPIphase >= 18) && (SPIphase <= 48) && (SPIphase[0] == 0));
ShiftDataRead <= ((SPIphase >= 51) && (SPIphase <= 81) && (SPIphase[0] == 1) && Read_notWrite);
ShiftDataWrite <= ((SPIphase >= 50) && (SPIphase <= 80) && (SPIphase[0] == 0) && !Read_notWrite);
PresetCarry <= (SPIphase == 17);
EndOfPhase <= (SPIphase == 83);
PrepOutput <= (SPIphase == 49);
end
reg CSreg;
always @(posedge clk) begin
if (SPIphase == 1)
CSreg <= Addr15;
end
endmodule |
module moyes0_top_module (
input [7:0] io_in,
output [7:0] io_out
);
// --- ASIC Inputs ---
wire clk = io_in[0]; // System clock (~6000 Hz)
wire rst = io_in[1]; // Reset line, active high
wire spi_miso= io_in[2]; // SPI bus, ASIC input, target output
wire uart_rx = io_in[3]; // Serial port, ASIC Receive
wire in4 = io_in[4];
wire in5 = io_in[5];
wire in6 = io_in[6];
wire in7 = io_in[7];
// --- ASIC Outputs ---
wire spi_cs0;
wire spi_cs1;
wire spi_clk;
wire spi_mosi;
wire uart_tx;
wire out5;
wire out6;
wire out7;
wire [7:0] io_out;
assign io_out[0] = spi_cs0; // SPI bus, Chip Select for RAM, Words 0000-7FFF
assign io_out[1] = spi_cs1; // SPI bus, Chip Select for ROM, Words 8000-FFFF
assign io_out[2] = spi_clk; // SPI bus, Clock
assign io_out[3] = spi_mosi; // SPI bus, ASIC output, target input
assign io_out[4] = uart_tx; // Serial port, ASIC Transmit
assign io_out[5] = out5;
assign io_out[6] = out6;
assign io_out[7] = out7;
// --- Internal Timing Signals ---
wire ShiftAddr;
wire ShiftDataRead;
wire ShiftDataWrite;
wire PresetCarry;
wire EndOfPhase;
wire PrepOutput;
// --- SPI Control Signals
wire Addr15;
wire Read_notWrite;
wire SPIAddr;
wire SPIDataIn;
// --- CPU Registers ---
reg [15:0] PC;
reg [15:0] TMP;
reg [15:0] ADR;
reg PCCarry;
reg TBorrow;
reg TZero;
reg LEQ;
assign out7 = !in7; // For bring-up testing, out7 = !in7. No other internal connections
SPIController spi (
// System Interfaces
.clk(clk),
.rst(rst),
// SPI Bus Interfaces
.CS0(spi_cs0),
.CS1(spi_cs1),
.SPICLK(spi_clk),
.MOSI(spi_mosi),
.MISO(spi_miso),
// Input Signals
.Addr15(Addr15),
.Read_notWrite(Read_notWrite),
.Addr(SPIAddr),
.Data(SPIDataIn),
// Timing Output Signals
.ShiftAddr(ShiftAddr),
.ShiftDataRead(ShiftDataRead),
.ShiftDataWrite(ShiftDataWrite),
.PresetCarry(PresetCarry),
.EndOfPhase(EndOfPhase),
.PrepOutput(PrepOutput)
);
reg [2:0] CPUphase;
always @(posedge clk) begin
if (rst)
CPUphase <= 3'd0;
else if (!EndOfPhase)
CPUphase <= CPUphase;
else begin
if (CPUphase == 3'd5)
CPUphase <= 3'd0;
else
CPUphase <= CPUphase + 3'd1;
end
end
wire PCphase = (CPUphase == 0) || (CPUphase == 2) || (CPUphase == 5);
assign Addr15 = PCphase ? PC[15] : ADR[15];
assign Read_notWrite = (CPUphase != 4);
always @(posedge clk) begin
if (rst)
PC <= 16'h8000;
else begin
if (PresetCarry)
PCCarry <= 1;
if (PCphase && ShiftAddr) begin
PCCarry <= PC[0] & PCCarry;
PC <= {PC[0] ^ PCCarry, PC[15:1]};
end
if ((CPUphase == 5) && ShiftDataRead) begin
PC <= {LEQ ? spi_miso : PC[0], PC[15:1]};
end
end
end
assign SPIAddr = PCphase ? PC[0] : ADR[0];
assign SPIDataIn = TMP[0];
wire ReadADR = (CPUphase == 0) || (CPUphase == 2);
wire ReadTMP = (CPUphase == 1) || (CPUphase == 3);
always @(posedge clk) begin
if (ReadADR & ShiftDataRead)
ADR <= {spi_miso, ADR[15:1]};
if (!PCphase & ShiftAddr)
ADR <= {ADR[0], ADR[15:1]};
end
// Transmit UART
reg BwasFFFF;
reg UARTout;
assign uart_tx = UARTout;
reg [4:0] UARTcount;
always @(posedge clk) begin
if (EndOfPhase) begin
BwasFFFF <= 1;
UARTout <= 1;
UARTcount <= 0;
end
if (ShiftAddr & !ADR[0])
BwasFFFF <= 0;
if (BwasFFFF & (CPUphase == 3)& PrepOutput) begin
UARTout <= 0;
UARTcount <= 9;
end
if ((UARTcount != 0) & ShiftDataRead) begin
UARTcount <= UARTcount - 1;
UARTout <= (UARTcount != 1) ? TMP[0] : 1;
end;
end
wire sub_b;
wire sub_r;
assign {sub_b, sub_r} = spi_miso - TMP[0] - TBorrow;
always @(posedge clk) begin
if (PresetCarry) begin
TBorrow <= 0;
TZero <= 1;
end
if ((CPUphase == 1) & ShiftDataRead)
TMP <= {spi_miso, TMP[15:1]};
if ((CPUphase == 3) & ShiftDataRead) begin
TBorrow <= sub_b;
TMP <= {sub_r, TMP[15:1]};
if (sub_r)
TZero <= 0;
end
if (!Read_notWrite & ShiftDataWrite)
TMP <= {TMP[0], TMP[15:1]};
end
always @(posedge clk) begin
if (EndOfPhase & (CPUphase == 3)) begin
LEQ <= TZero | TMP[15];
end
end
endmodule |
module tomkeddie_top_tto
#(parameter CLOCK_RATE=1000)
(
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire hour_inc = io_in[6];
wire min_inc = io_in[7];
wire lcd_en;
wire lcd_rs;
wire [3:0] lcd_data;
assign io_out[0] = lcd_data[0];
assign io_out[1] = lcd_data[1];
assign io_out[2] = lcd_data[2];
assign io_out[3] = lcd_data[3];
assign io_out[4] = lcd_en;
assign io_out[5] = lcd_rs;
// instatiate lcd
lcd lcd(.clk(clk), .reset(reset), .hour_inc(hour_inc), .min_inc(min_inc), .en(lcd_en), .rs(lcd_rs), .data(lcd_data));
endmodule |
module hex_sr #( parameter LENGTH = 40 ) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk;
wire recirc;
wire [5:0] data_in;
wire [5:0] data_out;
assign clk = io_in[0];
assign recirc = io_in[1];
assign data_in = io_in[7:2];
assign io_out[7:2] = data_out;
assign io_out[1:0] = 2'b0;
genvar i;
generate
for (i = 0; i < 6; i = i + 1)
sr_recirc #(.LENGTH(LENGTH)) sr0(clk, recirc, data_in[i], data_out[i]);
endgenerate
endmodule |
module cpldcpu_TrainLED2top(
input [7:0] io_in,
output [7:0] io_out
);
// Instance 1
TrainLED2 TrainLED2_top1 (
.clk(io_in[0]),
.rst(io_in[1]),
.din(io_in[2]),
.dout(io_out[0]),
.led1(io_out[1]),
.led2(io_out[2]),
.led3(io_out[3])
);
endmodule |
module xor_shift32_evango #( parameter MAX_COUNT = 1000 ) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
wire [5:0] seed_input = io_in[7:2];
// external clock is 1000Hz, so need 10 bit counter
reg [9:0] second_counter;
reg [3:0] digit;
reg unsigned [31:0] inital_state;
always @(posedge clk) begin
// Seed Setting
if (reset) begin
inital_state <= {26'b00000000000000000000000000, seed_input};
second_counter <= 0;
digit <= 0;
end else begin
// if up to 16e6
if (second_counter == MAX_COUNT) begin
// reset
second_counter <= 0;
inital_state = inital_state ^ (inital_state << 13);
inital_state = inital_state ^ (inital_state >> 17);
inital_state = inital_state ^ (inital_state << 5);
// increment digit
digit <= {1'b0, inital_state[2:0]};
end else
// increment counter
second_counter <= second_counter + 1'b1;
end
end
// instantiate segment display
seg7 seg7(.counter(digit), .segments(led_out));
endmodule |
module flygoat_tt02_play_tune #( parameter MAX_COUNT = 100 ) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire [1:0] db_sel_in = io_in[3:2];
wire [10:0] db_entry;
wire [10:0] flygoat_db_entry;
wire [10:0] bh5hso_db_entry;
wire [10:0] gm3hso_db_entry;
wire [10:0] planetes_db_entry;
reg [6:0] note_address;
reg [12:0] ticks;
reg [6:0] freq, counter;
reg [1:0] db_sel_r;
reg speaker;
reg [3:0] led_out;
assign io_out[0] = speaker;
assign io_out[1] = ~speaker;
assign io_out[5:2] = led_out;
assign io_out[7:6] = 2'bzz;
always @(posedge clk) begin
// if reset, set note_address to 0
if (reset) begin
note_address <= 0;
ticks <= 0;
freq <= 0;
counter <= 0;
speaker <= 0;
db_sel_r <= db_sel_in;
end else begin
if (!ticks) begin
if (note_address<MAX_COUNT) begin
note_address <= note_address + 1'b1;
end else begin
note_address <= 0;
end
end
// tone frequency divider
if (counter>0) begin
counter <= counter - 1'b1;
speaker <= counter >= (freq/2);
end else begin
counter <= freq;
speaker <= 1'b0;
end
end
end
always @(negedge clk) begin
if (!reset) begin
if (ticks>0) begin
ticks <= ticks - 1'b1;
end else begin
// update per-note delay
ticks[12:9] <= db_entry[3:0];
ticks[8:0] <= 0;
// reset tone generator
counter <= db_entry[10:4];
freq <= db_entry[10:4];
end
end
end
// instantiate tune database
flygoat_tune_db flygoat_tune_db(.address(note_address), .db_entry(flygoat_db_entry));
gm3hso_tune_db gm3hso_tune_db(.address(note_address), .db_entry(gm3hso_db_entry));
bh5hso_tune_db bh5hso_tune_db(.address(note_address), .db_entry(bh5hso_db_entry));
planetes_tune_db planetes_tune_db(.address(note_address), .db_entry(planetes_db_entry));
genvar i;
generate
for (i=0; i < 11; i=i+1) begin
mux4_cell tune_db_mux (
.a(flygoat_db_entry[i]),
.b(gm3hso_db_entry[i]),
.c(bh5hso_db_entry[i]),
.d(planetes_db_entry[i]),
.sel(db_sel_r),
.out(db_entry[i])
);
end
endgenerate
reg [24:0] cnt;
always@(posedge clk) begin
if(reset) begin
cnt <= 25'd0;
// 10 khz clk, 1s led peroid
end else if(cnt>=(10000-1)) begin
cnt <= 25'd0;
end else begin
cnt <= cnt + 25'd1;
end
end
reg [1:0] led_cnt = 2'd0;
always@(posedge clk) begin
if(reset) begin
led_cnt <= 2'd0;
end else if(cnt==(10000-1)) begin
if(led_cnt==2'd3) led_cnt <= 2'd0;
else led_cnt <= led_cnt + 2'd1;
end
end
always@(*) begin
if (reset) begin
led_out = 4'b0000;
end else begin
case(led_cnt)
3'd0: led_out = 4'b1110;
3'd1: led_out = 4'b1101;
3'd2: led_out = 4'b1011;
3'd3: led_out = 4'b0111;
default: led_out = 4'b1111;
endcase
end
end
endmodule |
module klei22_ra #(
parameter RA_SIZE = 8,
parameter BITS_PER_ELEM = 5
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire rst = io_in[1];
wire i_data_clk = io_in[2];
wire start_calc;
wire [4:0] i_value = io_in[7:3];
wire [BITS_PER_ELEM - 1:0] ra_out;
assign io_out[BITS_PER_ELEM-1:0] = {3'b000, ra_out[4:0]};
parameter SRL_SIZE = RA_SIZE + 1; // RA_SIZE valid inputs and one stale input
parameter TOTAL_SRL_BITS = 5 * SRL_SIZE;
wire [TOTAL_SRL_BITS - 1:0] taps;
shift_register_line #(
.TOTAL_TAPS(SRL_SIZE),
.BITS_PER_ELEM(BITS_PER_ELEM),
.TOTAL_BITS(TOTAL_SRL_BITS)
) srl_1 (
.clk(clk),
.rst(rst),
.i_value(i_value[4:0]),
.i_data_clk(i_data_clk),
.o_start_calc(start_calc),
.o_taps(taps[TOTAL_SRL_BITS-1:0])
);
// rolling sums RA_SIZE elements + 1 stale element
parameter RA_NUM_ELEM = RA_SIZE;
parameter MAX_BITS = 8; // log_2(31 * 8) = 7.9 ~ 8; where 31 is largest valut for 5 bit elem
rolling_average #(
.BITS_PER_ELEM(BITS_PER_ELEM),
.MAX_BITS(8)
) ra_1 (
.clk(clk),
.rst(rst),
.i_new(taps[4:0]),
.i_old(taps[(4 + 5 * 9):(0 + 5 * 8)]),
.i_start_calc(start_calc),
.o_ra(ra_out[BITS_PER_ELEM-1:0])
);
endmodule |
module meriac_tt02_play_tune #( parameter MAX_COUNT = 100 ) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire [10:0] db_entry;
reg [6:0] note_address;
reg [10:0] ticks;
reg [6:0] freq, counter;
reg speaker;
assign io_out[0] = speaker;
assign io_out[1] = ~speaker;
always @(posedge clk) begin
// if reset, set note_address to 0
if (reset) begin
note_address <= 0;
ticks <= 0;
freq <= 0;
counter <= 0;
speaker <= 0;
end else begin
if (!ticks) begin
if (note_address<MAX_COUNT) begin
note_address <= note_address + 1'b1;
end else begin
note_address <= 0;
end
end
// tone frequency divider
if (counter>0) begin
counter <= counter - 1'b1;
speaker <= counter >= (freq/2);
end else begin
counter <= freq;
speaker <= 1'b0;
end
end
end
always @(negedge clk) begin
if (!reset) begin
if (ticks>0) begin
ticks <= ticks - 1'b1;
end else begin
// update per-note delay
ticks[10:7] <= db_entry[3:0];
ticks[6:0] <= 0;
// reset tone generator
counter <= db_entry[10:4];
freq <= db_entry[10:4];
end
end
end
// instantiate tune database
meriac_tune_db meriac_tune_db(.address(note_address), .db_entry(db_entry));
endmodule |
module xyz_peppergray_Potato1_top(
input [7:0] io_in,
output [7:0] io_out
);
localparam INSTR_WITH = 4;
localparam INSTR_NUM = 9;
localparam CNTRL_WITH = 9;
localparam CMD_WITH = 8;
localparam LOOPCTR_WITH = 16;
localparam CTRL_X_INC = 0;
localparam CTRL_X_DEC = 1;
localparam CTRL_A_INC = 2;
localparam CTRL_A_DEC = 3;
localparam CTRL_PUT = 4;
localparam CTRL_GET = 5;
localparam CTRL_LOOP = 6;
localparam CTRL_DONE = 7;
localparam CTRL_HALT = 8;
localparam X_PC_INC = 0;
localparam X_PC_DEC = 1;
localparam CMD_OFFSET = 2;
wire Clock = io_in[0];
wire Reset_n = io_in[1];
reg ZeroFlag;
reg IOWait;
reg [INSTR_WITH-1:0] Instruction;
/* Input */
always @(posedge Clock or negedge Reset_n) begin
if(~Reset_n) begin
Instruction <= 4'b1111; /* Halt */
ZeroFlag <= 0;
IOWait <= 0;
end
else begin
Instruction <= io_in[7:4];
ZeroFlag <= io_in[3];
IOWait <= (IOActivity && io_in[2]);
end
end
/* Instruction Decode */
reg [INSTR_NUM-1:0] MicroInstruction;
always @ * begin
case(Instruction)
4'b0000: begin MicroInstruction <= (1 << CTRL_X_INC); end
4'b0001: begin MicroInstruction <= (1 << CTRL_X_DEC); end
4'b0010: begin MicroInstruction <= (1 << CTRL_A_INC); end
4'b0011: begin MicroInstruction <= (1 << CTRL_A_DEC); end
4'b0100: begin MicroInstruction <= (1 << CTRL_PUT); end
4'b0101: begin MicroInstruction <= (1 << CTRL_GET); end
4'b0110: begin MicroInstruction <= (1 << CTRL_LOOP); end
4'b0111: begin MicroInstruction <= (1 << CTRL_DONE); end
4'b1111: begin MicroInstruction <= (1 << CTRL_HALT); end
default: begin MicroInstruction <= 0; /* CTRL_NOP */ end
endcase
end
/* Loop Control */
reg reverse;
reg skipCmd;
wire Reverse = setReverse | (reverse & ~clrReverse);
wire SkipCmd = setSkipCmd | (skipCmd & ~clrSkipCmd);
wire Loop = MicroInstruction[CTRL_LOOP];
wire Done = MicroInstruction[CTRL_DONE];
wire setSkipCmd_L =!reverse && !skipCmd & ZeroFlag;
wire clrReverse_L = reverse && markMatch;
wire clrSkipCmd_L = skipCmd && clrReverse;
wire setReverse_D = !reverse && !skipCmd && !ZeroFlag;
wire setSkipCmd_D = setReverse;
wire clrSkipCmd_D = skipCmd && markMatch;
wire setSkipCmd = Loop ? setSkipCmd_L : Done ? setSkipCmd_D : 0;
wire clrSkipCmd = Loop ? clrSkipCmd_L : Done ? clrSkipCmd_D : 0;
wire setReverse = Done ? setReverse_D : 0;
wire clrReverse = Loop ? clrReverse_L : 0;
wire Count = !((!reverse && setReverse) || (reverse && clrReverse));
wire Up = Count && (reverse ? Done : Loop);
wire Down = Count && (reverse ? Loop : Done);
wire Store = setSkipCmd;
reg [LOOPCTR_WITH-1:0] LoopCounter;
reg [LOOPCTR_WITH-1:0] LoopJmpMark;
wire markMatch = (LoopJmpMark == LoopCounter);
always @(negedge Clock or negedge Reset_n) begin
if(~Reset_n) begin
LoopCounter <= 0;
LoopJmpMark <= 0;
reverse <= 0;
skipCmd <= 0;
end
else begin
LoopCounter <= LoopCounter + (Count ? (Up ? 1 : Down ? -1 : 0) : 0);
LoopJmpMark <= (Store ? LoopCounter + (Up ? 1 : Down ? -1 : 0) : LoopJmpMark);
reverse <= clrReverse ? 0 : setReverse ? 1 : reverse;
skipCmd <= clrSkipCmd ? 0 : setSkipCmd ? 1 : skipCmd;
end
end
/* Execution Control */
reg [CNTRL_WITH-1:0] Control;
always @ * begin
Control = IOWait ? Control : SkipCmd ? 0 : MicroInstruction;
end
/* ProgramCounter */
wire [1:0] Control_PC;
assign Control_PC[X_PC_INC] = ~Reverse & ~(Control[CTRL_HALT] | IOWait);
assign Control_PC[X_PC_DEC] = Reverse & ~(Control[CTRL_HALT] | IOWait);
/* Output */
reg [CMD_WITH-1:0] Command;
assign io_out = Command;
wire IOActivity = (Command[CMD_OFFSET + CTRL_GET] || Command[CMD_OFFSET + CTRL_PUT]);
always @(negedge Clock or negedge Reset_n) begin
if(~Reset_n) begin
Command <= 0;
end
else begin
Command <= { Control[5:0], Control_PC[1:0]};
end
end
endmodule |
module chase_the_beat (
input [7:0] io_in,
output [7:0] io_out
);
top top(.o(io_out), .clk(io_in[0]), .rst(io_in[1]), .tap(io_in[2]), .mode(io_in[3]));
endmodule |
module shan1293_2bitalu(
input [7:0] io_in,
output [7:0] io_out
);
alu alu(
.A(io_in[7:6]),
.B(io_in[5:4]),
.opcode(io_in[3:0]),
.ALU_Out(io_out[7:0])
);
endmodule |
module alu(
input [1:0] A,
input [1:0] B,
input [3:0] opcode,
output [7:0] ALU_Out
);
reg [7:0] ALU_Result;
assign ALU_Out = ALU_Result; // ALU out
always @(*)
begin
case(opcode)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left one time
ALU_Result = A<<1;
4'b0101: // Logical shift right one time
ALU_Result = A>>1;
4'b0110: // Logical shift left B times
ALU_Result = A<<B;
4'b0111: // Logical shift right B times
ALU_Result = A>>B;
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?4'd1:4'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?4'd1:4'd0 ;
default: ALU_Result = A + B ;
endcase
end
endmodule |
module user_module_342981109408072274(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19 = 1'b0;
wire net20 = 1'b1;
wire net21 = 1'b1;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33 = 1'b0;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41 = 1'b0;
wire net42;
wire net43 = 1'b0;
wire net44 = 1'b0;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net11;
assign io_out[3] = net12;
assign io_out[4] = net13;
assign io_out[5] = net14;
assign io_out[6] = net15;
assign io_out[7] = net16;
not_cell not3 (
.in (net17),
.out (net18)
);
and_cell gate1 (
);
or_cell gate2 (
.a (net22),
.b (net23),
.out (net17)
);
xor_cell gate3 (
);
mux_cell mux1 (
.a (net19),
.b (net18),
.sel (net3),
.out (net24)
);
dff_cell flipflop1 (
.d (net24),
.clk (net25),
.q (net22),
.notq (net26)
);
xor_cell gate7 (
);
and_cell gate4 (
);
xor_cell gate5 (
);
dff_cell flipflop2 (
.d (net22),
.clk (net25),
.q (net23)
);
dff_cell flipflop3 (
.d (net23),
.clk (net25),
.q (net27)
);
dff_cell flipflop4 (
.d (net27),
.clk (net25),
.q (net28)
);
dff_cell flipflop5 (
.d (net28),
.clk (net25),
.q (net29)
);
dff_cell flipflop6 (
.d (net29),
.clk (net25),
.q (net30)
);
dff_cell flipflop7 (
.d (net30),
.clk (net25),
.q (net31)
);
dff_cell flipflop8 (
.d (net31),
.clk (net25),
.q (net32)
);
mux_cell mux2 (
.a (net33),
.b (net26),
.sel (net2),
.out (net24)
);
or_cell gate8 (
.a (net28),
.b (net34),
.out (net35)
);
or_cell gate9 (
);
or_cell gate10 (
.a (net32),
.b (net36),
.out (net37)
);
or_cell gate11 (
.a (net31),
.b (net38),
.out (net36)
);
or_cell gate13 (
.a (net27),
.b (net17),
.out (net34)
);
or_cell gate14 (
.a (net30),
.b (net39),
.out (net38)
);
or_cell gate15 (
.a (net29),
.b (net35),
.out (net39)
);
not_cell not1 (
.in (net37),
.out (net40)
);
mux_cell mux3 (
.a (net41),
.b (net40),
.sel (net5),
.out (net24)
);
not_cell not2 (
.in (net34),
.out (net42)
);
mux_cell mux4 (
.a (net43),
.b (net42),
.sel (net4),
.out (net24)
);
mux_cell mux5 (
.a (net22),
.b (net32),
.sel (net45),
.out (net9)
);
mux_cell mux6 (
.a (net32),
.b (net22),
.sel (net45),
.out (net16)
);
mux_cell mux7 (
.a (net23),
.b (net31),
.sel (net45),
.out (net10)
);
mux_cell mux8 (
.a (net27),
.b (net30),
.sel (net45),
.out (net11)
);
mux_cell mux9 (
.a (net28),
.b (net29),
.sel (net45),
.out (net12)
);
mux_cell mux10 (
.a (net29),
.b (net28),
.sel (net45),
.out (net13)
);
mux_cell mux11 (
.a (net30),
.b (net27),
.sel (net45),
.out (net14)
);
mux_cell mux12 (
.a (net31),
.b (net23),
.sel (net45),
.out (net15)
);
dff_cell flipflop9 (
.d (net46),
.clk (net40),
.q (net47),
.notq (net46)
);
mux_cell mux13 (
.a (net47),
.b (net6),
.sel (net7),
.out (net45)
);
dff_cell flipflop10 (
.d (net48),
.clk (net1),
.notq (net48)
);
dff_cell flipflop11 (
.d (net49),
.clk (net48),
.notq (net49)
);
dff_cell flipflop12 (
.d (net50),
.clk (net49),
.notq (net50)
);
dff_cell flipflop13 (
.d (net51),
.clk (net50),
.notq (net51)
);
dff_cell flipflop14 (
.d (net52),
.clk (net51),
.notq (net52)
);
dff_cell flipflop15 (
.d (net53),
.clk (net52),
.notq (net53)
);
dff_cell flipflop16 (
.d (net54),
.clk (net53),
.notq (net54)
);
dff_cell flipflop17 (
.d (net55),
.clk (net54),
.notq (net55)
);
dff_cell flipflop18 (
.d (net56),
.clk (net55),
.notq (net56)
);
dff_cell flipflop19 (
.d (net57),
.clk (net56),
.notq (net57)
);
mux_cell mux14 (
.a (net1),
.b (net58),
.sel (net8),
.out (net25)
);
dff_cell flipflop20 (
.d (net58),
.clk (net57),
.notq (net58)
);
endmodule |
module tholin_avalonsemi_5401(
input [7:0] io_in,
output [7:0] io_out
);
wire s_CLK = io_in[0];
wire s_RST = io_in[1];
wire s_D0 = io_in[2];
wire s_D1 = io_in[3];
wire s_D2 = io_in[4];
wire s_D3 = io_in[5];
wire s_EF0 = io_in[6];
wire s_EF1 = io_in[7];
wire s_O_D0_RR0;
wire s_O_D1_RR1;
wire s_O_D2_RR2;
wire s_O_D3_RR3;
wire s_O_4_MAR;
wire s_O_5_WRITE;
wire s_O_6_JMP;
wire s_O_7_I;
assign io_out[0] = s_O_D0_RR0;
assign io_out[1] = s_O_D1_RR1;
assign io_out[2] = s_O_D2_RR2;
assign io_out[3] = s_O_D3_RR3;
assign io_out[4] = s_O_4_MAR;
assign io_out[5] = s_O_5_WRITE;
assign io_out[6] = s_O_6_JMP;
assign io_out[7] = s_O_7_I;
CPU CIRCUIT_0 (.CLK(s_CLK),
.D0(s_D0),
.D1(s_D1),
.D2(s_D2),
.D3(s_D3),
.EF0(s_EF0),
.EF1(s_EF1),
.O_4_MAR(s_O_4_MAR),
.O_5_WRITE(s_O_5_WRITE),
.O_6_JMP(s_O_6_JMP),
.O_7_I(s_O_7_I),
.O_D0_RR0(s_O_D0_RR0),
.O_D1_RR1(s_O_D1_RR1),
.O_D2_RR2(s_O_D2_RR2),
.O_D3_RR3(s_O_D3_RR3),
.RST(s_RST));
endmodule |
module lms_ctr (
clk_clk,
exfifo_if_d_export,
exfifo_if_rd_export,
exfifo_if_rdempty_export,
exfifo_of_d_export,
exfifo_of_wr_export,
exfifo_of_wrfull_export,
exfifo_rst_export,
leds_external_connection_export,
lms_ctr_gpio_external_connection_export,
scl_exp_export,
sda_exp_export,
spi_1_adf_external_MISO,
spi_1_adf_external_MOSI,
spi_1_adf_external_SCLK,
spi_1_adf_external_SS_n,
spi_1_dac_external_MISO,
spi_1_dac_external_MOSI,
spi_1_dac_external_SCLK,
spi_1_dac_external_SS_n,
spi_lms_external_MISO,
spi_lms_external_MOSI,
spi_lms_external_SCLK,
spi_lms_external_SS_n,
switch_external_connection_export);
input clk_clk;
input [31:0] exfifo_if_d_export;
output exfifo_if_rd_export;
input exfifo_if_rdempty_export;
output [31:0] exfifo_of_d_export;
output exfifo_of_wr_export;
input exfifo_of_wrfull_export;
output exfifo_rst_export;
output [7:0] leds_external_connection_export;
output [3:0] lms_ctr_gpio_external_connection_export;
inout scl_exp_export;
inout sda_exp_export;
input spi_1_adf_external_MISO;
output spi_1_adf_external_MOSI;
output spi_1_adf_external_SCLK;
output spi_1_adf_external_SS_n;
input spi_1_dac_external_MISO;
output spi_1_dac_external_MOSI;
output spi_1_dac_external_SCLK;
output spi_1_dac_external_SS_n;
input spi_lms_external_MISO;
output spi_lms_external_MOSI;
output spi_lms_external_SCLK;
output [4:0] spi_lms_external_SS_n;
input [7:0] switch_external_connection_export;
endmodule |
module lms_ctr_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1476792439 : 4920;
endmodule |
module ddr2_phy_alt_mem_phy_seq_wrapper (
// dss ports
phy_clk_1x,
reset_phy_clk_1x_n,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
ctl_cal_req,
int_RANK_HAS_ADDR_SWAP,
ctl_cal_byte_lane_sel_n,
seq_pll_inc_dec_n,
seq_pll_start_reconfig,
seq_pll_select,
phs_shft_busy,
pll_resync_clk_index,
pll_measure_clk_index,
sc_clk_dp,
scan_enable_dqs_config,
scan_update,
scan_din,
scan_enable_ck,
scan_enable_dqs,
scan_enable_dqsn,
scan_enable_dq,
scan_enable_dm,
hr_rsc_clk,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n,
seq_ac_sel,
seq_mem_clk_disable,
ctl_add_1t_ac_lat_internal,
ctl_add_1t_odt_lat_internal,
ctl_add_intermediate_regs_internal,
seq_rdv_doing_rd,
seq_rdp_reset_req_n,
seq_rdp_inc_read_lat_1x,
seq_rdp_dec_read_lat_1x,
ctl_rdata,
int_rdata_valid_1t,
seq_rdata_valid_lat_inc,
seq_rdata_valid_lat_dec,
ctl_rlat,
seq_poa_lat_dec_1x,
seq_poa_lat_inc_1x,
seq_poa_protection_override_1x,
seq_oct_oct_delay,
seq_oct_oct_extend,
seq_oct_val,
seq_wdp_dqs_burst,
seq_wdp_wdata_valid,
seq_wdp_wdata,
seq_wdp_dm,
seq_wdp_dqs,
seq_wdp_ovride,
seq_dqs_add_2t_delay,
ctl_wlat,
seq_mmc_start,
mmc_seq_done,
mmc_seq_value,
mem_err_out_n,
parity_error_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
//Inserted Generics
localparam SPEED_GRADE = "C8";
localparam MEM_IF_DQS_WIDTH = 2;
localparam MEM_IF_DWIDTH = 16;
localparam MEM_IF_DM_WIDTH = 2;
localparam MEM_IF_DQ_PER_DQS = 8;
localparam DWIDTH_RATIO = 2;
localparam CLOCK_INDEX_WIDTH = 3;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_ADDR_WIDTH = 13;
localparam MEM_IF_BANKADDR_WIDTH = 3;
localparam MEM_IF_CS_WIDTH = 1;
localparam RESYNCHRONISE_AVALON_DBG = 0;
localparam DBG_A_WIDTH = 13;
localparam DQS_PHASE_SETTING = 2;
localparam SCAN_CLK_DIVIDE_BY = 2;
localparam PLL_STEPS_PER_CYCLE = 64;
localparam MEM_IF_CLK_PS = 6667;
localparam DQS_DELAY_CTL_WIDTH = 6;
localparam MEM_IF_MEMTYPE = "DDR2";
localparam RANK_HAS_ADDR_SWAP = 0;
localparam MEM_IF_MR_0 = 1074;
localparam MEM_IF_MR_1 = 1024;
localparam MEM_IF_MR_2 = 0;
localparam MEM_IF_MR_3 = 0;
localparam MEM_IF_OCT_EN = 0;
localparam IP_BUILDNUM = 0;
localparam FAMILY = "Cyclone IV E";
localparam FAMILYGROUP_ID = 2;
localparam MEM_IF_ADDR_CMD_PHASE = 90;
localparam CAPABILITIES = 2048;
localparam WRITE_DESKEW_T10 = 0;
localparam WRITE_DESKEW_HC_T10 = 0;
localparam WRITE_DESKEW_T9NI = 0;
localparam WRITE_DESKEW_HC_T9NI = 0;
localparam WRITE_DESKEW_T9I = 0;
localparam WRITE_DESKEW_HC_T9I = 0;
localparam WRITE_DESKEW_RANGE = 0;
localparam IOE_PHASES_PER_TCK = 12;
localparam ADV_LAT_WIDTH = 5;
localparam RDP_ADDR_WIDTH = 4;
localparam IOE_DELAYS_PER_PHS = 5;
localparam SINGLE_DQS_DELAY_CONTROL_CODE = 0;
localparam PRESET_RLAT = 0;
localparam FORCE_HC = 0;
localparam MEM_IF_DQS_CAPTURE_EN = 0;
localparam REDUCE_SIM_TIME = 0;
localparam TINIT_TCK = 30004;
localparam TINIT_RST = 0;
localparam GENERATE_ADDITIONAL_DBG_RTL = 0;
localparam MEM_IF_CS_PER_RANK = 1;
localparam MEM_IF_RANKS_PER_SLOT = 1;
localparam CHIP_OR_DIMM = "Discrete Device";
localparam RDIMM_CONFIG_BITS = "0000000000000000000000000000000000000000000000000000000000000000";
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
localparam GENERATE_TRACKING_PHASE_STORE = 0;
// note that num_ranks if the number of discrete chip select signals output from the sequencer
// cs_width is the total number of chip selects which go from the phy to the memory (there can
// be more than one chip select per rank).
localparam MEM_IF_NUM_RANKS = MEM_IF_CS_WIDTH/MEM_IF_CS_PER_RANK;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
input wire ctl_cal_req;
input wire [MEM_IF_NUM_RANKS - 1 : 0] int_RANK_HAS_ADDR_SWAP;
input wire [MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
output wire seq_pll_inc_dec_n;
output wire seq_pll_start_reconfig;
output wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
input wire phs_shft_busy;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
output [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs_config;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_update;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_din;
output wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqsn;
output wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
output wire [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
input wire hr_rsc_clk;
output wire [(DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 : 0] seq_ac_addr;
output wire [(DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 : 0] seq_ac_ba;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_cas_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_ras_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_we_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_cke;
output wire [(DWIDTH_RATIO/2) * MEM_IF_CS_WIDTH - 1 : 0] seq_ac_cs_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_odt;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_rst_n;
output wire seq_ac_sel;
output wire seq_mem_clk_disable;
output wire ctl_add_1t_ac_lat_internal;
output wire ctl_add_1t_odt_lat_internal;
output wire ctl_add_intermediate_regs_internal;
output wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_rdv_doing_rd;
output wire seq_rdp_reset_req_n;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_inc_read_lat_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_dec_read_lat_1x;
input wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] ctl_rdata;
input wire [DWIDTH_RATIO/2 - 1 : 0] int_rdata_valid_1t;
output wire seq_rdata_valid_lat_inc;
output wire seq_rdata_valid_lat_dec;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_rlat;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_dec_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_inc_1x;
output wire seq_poa_protection_override_1x;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend;
output wire seq_oct_val;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_dqs_burst;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_wdata_valid;
output wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] seq_wdp_wdata;
output wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0] seq_wdp_dm;
output wire [DWIDTH_RATIO - 1 : 0] seq_wdp_dqs;
output wire seq_wdp_ovride;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_dqs_add_2t_delay;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_wlat;
output wire seq_mmc_start;
input wire mmc_seq_done;
input wire mmc_seq_value;
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH - 1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [ 31 : 0] dbg_wr_data;
output wire [ 31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
input wire mem_err_out_n;
output wire parity_error_n;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// instantiate the deskew (DDR3) or non-deskew (DDR/DDR2/DDR3) sequencer:
//
ddr2_phy_alt_mem_phy_seq #(
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.DWIDTH_RATIO (DWIDTH_RATIO),
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_ADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
.MEM_IF_RANKS_PER_SLOT (MEM_IF_RANKS_PER_SLOT),
.ADV_LAT_WIDTH (ADV_LAT_WIDTH),
.RESYNCHRONISE_AVALON_DBG (RESYNCHRONISE_AVALON_DBG),
.AV_IF_ADDR_WIDTH (DBG_A_WIDTH),
.NOM_DQS_PHASE_SETTING (DQS_PHASE_SETTING),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.RDP_ADDR_WIDTH (RDP_ADDR_WIDTH),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE),
.IOE_PHASES_PER_TCK (IOE_PHASES_PER_TCK),
.IOE_DELAYS_PER_PHS (IOE_DELAYS_PER_PHS),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.PHY_DEF_MR_1ST (MEM_IF_MR_0),
.PHY_DEF_MR_2ND (MEM_IF_MR_1),
.PHY_DEF_MR_3RD (MEM_IF_MR_2),
.PHY_DEF_MR_4TH (MEM_IF_MR_3),
.MEM_IF_DQSN_EN (0),
.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
.FAMILY (FAMILY),
.FAMILYGROUP_ID (FAMILYGROUP_ID),
.SPEED_GRADE (SPEED_GRADE),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.WRITE_DESKEW_T10 (WRITE_DESKEW_T10),
.WRITE_DESKEW_HC_T10 (WRITE_DESKEW_HC_T10),
.WRITE_DESKEW_T9NI (WRITE_DESKEW_T9NI),
.WRITE_DESKEW_HC_T9NI (WRITE_DESKEW_HC_T9NI),
.WRITE_DESKEW_T9I (WRITE_DESKEW_T9I),
.WRITE_DESKEW_HC_T9I (WRITE_DESKEW_HC_T9I),
.WRITE_DESKEW_RANGE (WRITE_DESKEW_RANGE),
.SINGLE_DQS_DELAY_CONTROL_CODE (SINGLE_DQS_DELAY_CONTROL_CODE),
.PRESET_RLAT (PRESET_RLAT),
.EN_OCT (MEM_IF_OCT_EN),
.SIM_TIME_REDUCTIONS (REDUCE_SIM_TIME),
.FORCE_HC (FORCE_HC),
.CAPABILITIES (CAPABILITIES),
.GENERATE_ADDITIONAL_DBG_RTL (GENERATE_ADDITIONAL_DBG_RTL),
.TINIT_TCK (TINIT_TCK),
.TINIT_RST (TINIT_RST),
.GENERATE_TRACKING_PHASE_STORE (0),
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
.IP_BUILDNUM (IP_BUILDNUM),
.CHIP_OR_DIMM (CHIP_OR_DIMM),
.RDIMM_CONFIG_BITS (RDIMM_CONFIG_BITS)
) seq_inst (
.clk (phy_clk_1x),
.rst_n (reset_phy_clk_1x_n),
.ctl_init_success (ctl_cal_success),
.ctl_init_fail (ctl_cal_fail),
.ctl_init_warning (ctl_cal_warning),
.ctl_recalibrate_req (ctl_cal_req),
.MEM_AC_SWAPPED_RANKS (int_RANK_HAS_ADDR_SWAP),
.ctl_cal_byte_lanes (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.seq_pll_phs_shift_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.seq_scan_clk (sc_clk_dp),
.seq_scan_enable_dqs_config (scan_enable_dqs_config),
.seq_scan_update (scan_update),
.seq_scan_din (scan_din),
.seq_scan_enable_ck (scan_enable_ck),
.seq_scan_enable_dqs (scan_enable_dqs),
.seq_scan_enable_dqsn (scan_enable_dqsn),
.seq_scan_enable_dq (scan_enable_dq),
.seq_scan_enable_dm (scan_enable_dm),
.hr_rsc_clk (hr_rsc_clk),
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.seq_ac_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.seq_ac_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.seq_ac_add_2t (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_rdv_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.rdata (ctl_rdata),
.rdata_valid (int_rdata_valid_1t),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_value (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.seq_ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (mem_err_out_n),
.parity_error_n (parity_error_n),
.dbg_seq_clk (dbg_clk),
.dbg_seq_rst_n (dbg_reset_n),
.dbg_seq_addr (dbg_addr),
.dbg_seq_wr (dbg_wr),
.dbg_seq_rd (dbg_rd),
.dbg_seq_cs (dbg_cs),
.dbg_seq_wr_data (dbg_wr_data),
.seq_dbg_rd_data (dbg_rd_data),
.seq_dbg_waitrequest (dbg_waitrequest)
);
endmodule |
module ddr2_alt_mem_ddrx_controller_top(
clk,
half_clk,
reset_n,
local_ready,
local_write,
local_read,
local_address,
local_byteenable,
local_writedata,
local_burstcount,
local_beginbursttransfer,
local_readdata,
local_readdatavalid,
afi_rst_n,
afi_cs_n,
afi_cke,
afi_odt,
afi_addr,
afi_ba,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_rlat,
afi_cal_success,
afi_cal_fail,
afi_cal_req,
afi_mem_clk_disable,
afi_cal_byte_lane_sel_n,
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
local_init_done,
local_refresh_ack,
local_powerdn_ack,
local_self_rfsh_ack,
local_autopch_req,
local_refresh_req,
local_refresh_chip,
local_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_multicast,
local_priority,
ecc_interrupt,
csr_read_req,
csr_write_req,
csr_burst_count,
csr_beginbursttransfer,
csr_addr,
csr_wdata,
csr_rdata,
csr_be,
csr_rdata_valid,
csr_waitrequest
);
//////////////////////////////////////////////////////////////////////////////
// << START MEGAWIZARD INSERT GENERICS
// Inserted Generics
localparam MEM_TYPE = "DDR2";
localparam LOCAL_SIZE_WIDTH = 2;
localparam LOCAL_ADDR_WIDTH = 25;
localparam LOCAL_DATA_WIDTH = 32;
localparam LOCAL_BE_WIDTH = 4;
localparam LOCAL_IF_TYPE = "AVALON";
localparam MEM_IF_CS_WIDTH = 1;
localparam MEM_IF_CKE_WIDTH = 1;
localparam MEM_IF_ODT_WIDTH = 1;
localparam MEM_IF_ADDR_WIDTH = 13;
localparam MEM_IF_ROW_WIDTH = 13;
localparam MEM_IF_COL_WIDTH = 10;
localparam MEM_IF_BA_WIDTH = 3;
localparam MEM_IF_DQS_WIDTH = 2;
localparam MEM_IF_DQ_WIDTH = 16;
localparam MEM_IF_DM_WIDTH = 2;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_CS_PER_DIMM = 1;
localparam DWIDTH_RATIO = 2;
localparam CTL_LOOK_AHEAD_DEPTH = 4;
localparam CTL_CMD_QUEUE_DEPTH = 8;
localparam CTL_HRB_ENABLED = 0;
localparam CTL_ECC_ENABLED = 0;
localparam CTL_ECC_RMW_ENABLED = 0;
localparam CTL_ECC_CSR_ENABLED = 0;
localparam CTL_CSR_ENABLED = 0;
localparam CTL_ODT_ENABLED = 0;
localparam CSR_ADDR_WIDTH = 16;
localparam CSR_DATA_WIDTH = 32;
localparam CSR_BE_WIDTH = 4;
localparam CTL_OUTPUT_REGD = 0;
localparam MEM_CAS_WR_LAT = 5;
localparam MEM_ADD_LAT = 0;
localparam MEM_TCL = 3;
localparam MEM_TRRD = 2;
localparam MEM_TFAW = 7;
localparam MEM_TRFC = 20;
localparam MEM_TREFI = 1170;
localparam MEM_TRCD = 2;
localparam MEM_TRP = 2;
localparam MEM_TWR = 3;
localparam MEM_TWTR = 2;
localparam MEM_TRTP = 2;
localparam MEM_TRAS = 7;
localparam MEM_TRC = 9;
localparam ADDR_ORDER = 0;
localparam MEM_AUTO_PD_CYCLES = 0;
localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 3;
localparam MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0;
localparam CTL_RD_TO_PCH_EXTRA_CLK = 0;
localparam CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK = 0;
localparam CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK = 0;
localparam CTL_ECC_MULTIPLES_16_24_40_72 = 1;
localparam CTL_USR_REFRESH = 0;
localparam CTL_REGDIMM_ENABLED = 0;
localparam MULTICAST_WR_EN = 0;
localparam LOW_LATENCY = 0;
localparam CTL_DYNAMIC_BANK_ALLOCATION = 0;
localparam CTL_DYNAMIC_BANK_NUM = 4;
localparam ENABLE_BURST_MERGE = 0;
localparam LOCAL_ID_WIDTH = 8;
localparam LOCAL_CS_WIDTH = 0;
localparam CTL_TBP_NUM = 4;
localparam WRBUFFER_ADDR_WIDTH = 6;
localparam RDBUFFER_ADDR_WIDTH = 8;
localparam MEM_IF_CHIP = 1;
localparam MEM_IF_BANKADDR_WIDTH = 3;
localparam MEM_IF_DWIDTH = 16;
localparam MAX_MEM_IF_CS_WIDTH = 30;
localparam MAX_MEM_IF_CHIP = 4;
localparam MAX_MEM_IF_BANKADDR_WIDTH = 3;
localparam MAX_MEM_IF_ROWADDR_WIDTH = 16;
localparam MAX_MEM_IF_COLADDR_WIDTH = 12;
localparam MAX_MEM_IF_ODT_WIDTH = 1;
localparam MAX_MEM_IF_DQS_WIDTH = 5;
localparam MAX_MEM_IF_DQ_WIDTH = 40;
localparam MAX_MEM_IF_MASK_WIDTH = 5;
localparam MAX_LOCAL_DATA_WIDTH = 80;
localparam CFG_TYPE = 'b001;
localparam CFG_INTERFACE_WIDTH = 16;
localparam CFG_BURST_LENGTH = 'b00100;
localparam CFG_DEVICE_WIDTH = 1;
localparam CFG_REORDER_DATA = 1;
localparam CFG_DATA_REORDERING_TYPE = "INTER_BANK";
localparam CFG_STARVE_LIMIT = 10;
localparam CFG_ADDR_ORDER = 'b00;
localparam CFG_TCCD = 2;
localparam CFG_SELF_RFSH_EXIT_CYCLES = 200;
localparam CFG_PDN_EXIT_CYCLES = 3;
localparam CFG_POWER_SAVING_EXIT_CYCLES = 5;
localparam CFG_MEM_CLK_ENTRY_CYCLES = 10;
localparam CTL_ENABLE_BURST_INTERRUPT = 0;
localparam CTL_ENABLE_BURST_TERMINATE = 0;
localparam MEM_TMRD_CK = 14;
localparam CFG_GEN_SBE = 0;
localparam CFG_GEN_DBE = 0;
localparam CFG_ENABLE_INTR = 0;
localparam CFG_MASK_SBE_INTR = 0;
localparam CFG_MASK_DBE_INTR = 0;
localparam CFG_MASK_CORRDROP_INTR = 0;
localparam CFG_CLR_INTR = 0;
localparam CFG_WRITE_ODT_CHIP = 'h1;
localparam CFG_READ_ODT_CHIP = 'h0;
localparam CFG_PORT_WIDTH_WRITE_ODT_CHIP = 1;
localparam CFG_PORT_WIDTH_READ_ODT_CHIP = 1;
localparam CFG_ENABLE_NO_DM = 0;
// << END MEGAWIZARD INSERT GENERICS
//////////////////////////////////////////////////////////////////////////////
localparam CFG_LOCAL_SIZE_WIDTH = LOCAL_SIZE_WIDTH;
localparam CFG_LOCAL_ADDR_WIDTH = LOCAL_ADDR_WIDTH;
localparam CFG_LOCAL_DATA_WIDTH = LOCAL_DATA_WIDTH;
localparam CFG_LOCAL_BE_WIDTH = LOCAL_BE_WIDTH;
localparam CFG_LOCAL_ID_WIDTH = LOCAL_ID_WIDTH;
localparam CFG_LOCAL_IF_TYPE = LOCAL_IF_TYPE;
localparam CFG_MEM_IF_ADDR_WIDTH = MEM_IF_ADDR_WIDTH;
localparam CFG_MEM_IF_CLK_PAIR_COUNT = MEM_IF_CLK_PAIR_COUNT;
localparam CFG_DWIDTH_RATIO = DWIDTH_RATIO;
localparam CFG_ODT_ENABLED = CTL_ODT_ENABLED;
localparam CFG_CTL_TBP_NUM = CTL_TBP_NUM;
localparam CFG_WRBUFFER_ADDR_WIDTH = WRBUFFER_ADDR_WIDTH;
localparam CFG_RDBUFFER_ADDR_WIDTH = RDBUFFER_ADDR_WIDTH;
localparam CFG_MEM_IF_CS_WIDTH = MEM_IF_CS_WIDTH;
localparam CFG_MEM_IF_CHIP = MEM_IF_CHIP;
localparam CFG_MEM_IF_BA_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_MEM_IF_ROW_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_MEM_IF_COL_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_MEM_IF_CKE_WIDTH = MEM_IF_CKE_WIDTH;
localparam CFG_MEM_IF_ODT_WIDTH = MEM_IF_ODT_WIDTH;
localparam CFG_MEM_IF_DQS_WIDTH = MEM_IF_DQS_WIDTH;
localparam CFG_MEM_IF_DQ_WIDTH = MEM_IF_DWIDTH;
localparam CFG_MEM_IF_DM_WIDTH = MEM_IF_DM_WIDTH;
localparam CFG_COL_ADDR_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_ROW_ADDR_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_BANK_ADDR_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_CS_ADDR_WIDTH = LOCAL_CS_WIDTH;
localparam CFG_CAS_WR_LAT = MEM_CAS_WR_LAT;
localparam CFG_ADD_LAT = MEM_ADD_LAT;
localparam CFG_TCL = MEM_TCL;
localparam CFG_TRRD = MEM_TRRD;
localparam CFG_TFAW = MEM_TFAW;
localparam CFG_TRFC = MEM_TRFC;
localparam CFG_TREFI = MEM_TREFI;
localparam CFG_TRCD = MEM_TRCD;
localparam CFG_TRP = MEM_TRP;
localparam CFG_TWR = MEM_TWR;
localparam CFG_TWTR = MEM_TWTR;
localparam CFG_TRTP = MEM_TRTP;
localparam CFG_TRAS = MEM_TRAS;
localparam CFG_TRC = MEM_TRC;
localparam CFG_AUTO_PD_CYCLES = MEM_AUTO_PD_CYCLES;
localparam CFG_TMRD = MEM_TMRD_CK;
localparam CFG_ENABLE_ECC = CTL_ECC_ENABLED;
localparam CFG_ENABLE_AUTO_CORR = CTL_ECC_RMW_ENABLED;
localparam CFG_ECC_MULTIPLES_16_24_40_72 = CTL_ECC_MULTIPLES_16_24_40_72;
localparam CFG_ENABLE_ECC_CODE_OVERWRITES = 1'b1;
localparam CFG_CAL_REQ = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_RDWR = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_BC = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_BC = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 0;
localparam CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_PERIOD = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_PERIOD = 0;
localparam CFG_ENABLE_DQS_TRACKING = 0;
localparam CFG_OUTPUT_REGD = CTL_OUTPUT_REGD;
localparam CFG_MASK_CORR_DROPPED_INTR = 0;
localparam CFG_USER_RFSH = CTL_USR_REFRESH;
localparam CFG_REGDIMM_ENABLE = CTL_REGDIMM_ENABLED;
localparam CFG_PORT_WIDTH_TYPE = 3;
localparam CFG_PORT_WIDTH_INTERFACE_WIDTH = 8;
localparam CFG_PORT_WIDTH_BURST_LENGTH = 5;
localparam CFG_PORT_WIDTH_DEVICE_WIDTH = 4;
localparam CFG_PORT_WIDTH_REORDER_DATA = 1;
localparam CFG_PORT_WIDTH_STARVE_LIMIT = 6;
localparam CFG_PORT_WIDTH_OUTPUT_REGD = 2;
localparam CFG_PORT_WIDTH_ADDR_ORDER = 2;
localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CAS_WR_LAT = 4;
localparam CFG_PORT_WIDTH_ADD_LAT = 4;
localparam CFG_PORT_WIDTH_TCL = 4;
localparam CFG_PORT_WIDTH_TRRD = 4;
localparam CFG_PORT_WIDTH_TFAW = 6;
localparam CFG_PORT_WIDTH_TRFC = 9; //case:234203
localparam CFG_PORT_WIDTH_TREFI = 14; //case:234203
localparam CFG_PORT_WIDTH_TRCD = 4;
localparam CFG_PORT_WIDTH_TRP = 4;
localparam CFG_PORT_WIDTH_TWR = 5; //case:234203
localparam CFG_PORT_WIDTH_TWTR = 4;
localparam CFG_PORT_WIDTH_TRTP = 4;
localparam CFG_PORT_WIDTH_TRAS = 6; //case:234203
localparam CFG_PORT_WIDTH_TRC = 6;
localparam CFG_PORT_WIDTH_TCCD = 4;
localparam CFG_PORT_WIDTH_TMRD = 3;
localparam CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10;
localparam CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4;
localparam CFG_PORT_WIDTH_ENABLE_ECC = 1;
localparam CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1;
localparam CFG_PORT_WIDTH_GEN_SBE = 1;
localparam CFG_PORT_WIDTH_GEN_DBE = 1;
localparam CFG_PORT_WIDTH_ENABLE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_SBE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_DBE_INTR = 1;
localparam CFG_PORT_WIDTH_CLR_INTR = 1;
localparam CFG_PORT_WIDTH_USER_RFSH = 1;
localparam CFG_PORT_WIDTH_SELF_RFSH = 1;
localparam CFG_PORT_WIDTH_REGDIMM_ENABLE = 1;
localparam CFG_WLAT_BUS_WIDTH = 5;
localparam CFG_RDATA_RETURN_MODE = (CFG_REORDER_DATA == 1) ? "INORDER" : "PASSTHROUGH";
localparam CFG_LPDDR2_ENABLED = (CFG_TYPE == `MMR_TYPE_LPDDR2) ? 1 : 0;
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = (CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH);
localparam STS_PORT_WIDTH_SBE_ERROR = 1;
localparam STS_PORT_WIDTH_DBE_ERROR = 1;
localparam STS_PORT_WIDTH_CORR_DROP_ERROR = 1;
localparam STS_PORT_WIDTH_SBE_COUNT = 8;
localparam STS_PORT_WIDTH_DBE_COUNT = 8;
localparam STS_PORT_WIDTH_CORR_DROP_COUNT = 8;
// KALEN HACK: We are supposed to use these parameters when the CSR is enabled
// but the MAX_ parameters are not defined
//localparam AFI_CS_WIDTH = (MAX_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CKE_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ODT_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ADDR_WIDTH = (MAX_CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_BA_WIDTH = (MAX_CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * MAX_CFG_MEM_IF_CHIP);
localparam AFI_CS_WIDTH = (CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CKE_WIDTH = (CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ODT_WIDTH = (CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ADDR_WIDTH = (CFG_AFI_IF_FR_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_BA_WIDTH = (CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP);
localparam AFI_CMD_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_DQS_BURST_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_VALID_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_DM_WIDTH = (CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_WLAT_WIDTH = CFG_WLAT_BUS_WIDTH;
localparam AFI_RDATA_EN_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_RDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_RDATA_VALID_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_RLAT_WIDTH = 5;
localparam AFI_OTF_BITNUM = 12;
localparam AFI_AUTO_PRECHARGE_BITNUM = 10;
localparam AFI_MEM_CLK_DISABLE_WIDTH = CFG_MEM_IF_CLK_PAIR_COUNT;
localparam CFG_MM_ST_CONV_REG = 0;
localparam CFG_ECC_DECODER_REG = 0;
localparam CFG_ERRCMD_FIFO_REG = 0;
//////////////////////////////////////////////////////////////////////////////
// BEGIN PORT SECTION
// Clk and reset signals
input clk;
input half_clk;
input reset_n;
// Avalon signals
output local_ready;
input local_write;
input local_read;
input [LOCAL_ADDR_WIDTH - 1 : 0] local_address;
input [LOCAL_BE_WIDTH - 1 : 0] local_byteenable;
input [LOCAL_DATA_WIDTH - 1 : 0] local_writedata;
input [LOCAL_SIZE_WIDTH - 1 : 0] local_burstcount;
input local_beginbursttransfer;
output [LOCAL_DATA_WIDTH - 1 : 0] local_readdata;
output local_readdatavalid;
// AFI signals
output [AFI_CMD_WIDTH - 1 : 0] afi_rst_n;
output [AFI_CS_WIDTH - 1 : 0] afi_cs_n;
output [AFI_CKE_WIDTH - 1 : 0] afi_cke;
output [AFI_ODT_WIDTH - 1 : 0] afi_odt;
output [AFI_ADDR_WIDTH - 1 : 0] afi_addr;
output [AFI_BA_WIDTH - 1 : 0] afi_ba;
output [AFI_CMD_WIDTH - 1 : 0] afi_ras_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_cas_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_we_n;
output [AFI_DQS_BURST_WIDTH - 1 : 0] afi_dqs_burst;
output [AFI_WDATA_VALID_WIDTH - 1 : 0] afi_wdata_valid;
output [AFI_WDATA_WIDTH - 1 : 0] afi_wdata;
output [AFI_DM_WIDTH - 1 : 0] afi_dm;
input [AFI_WLAT_WIDTH - 1 : 0] afi_wlat;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en_full;
input [AFI_RDATA_WIDTH - 1 : 0] afi_rdata;
input [AFI_RDATA_VALID_WIDTH - 1 : 0] afi_rdata_valid;
input [AFI_RLAT_WIDTH - 1 : 0] afi_rlat;
input afi_cal_success;
input afi_cal_fail;
output afi_cal_req;
output [AFI_MEM_CLK_DISABLE_WIDTH - 1 : 0] afi_mem_clk_disable;
output [AFI_CAL_BYTE_LANE_SEL_N_WIDTH - 1 : 0] afi_cal_byte_lane_sel_n;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// Sideband signals
output local_init_done;
output local_refresh_ack;
output local_powerdn_ack;
output local_self_rfsh_ack;
input local_autopch_req;
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_powerdn_req;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
input local_multicast;
input local_priority;
// Csr & ecc signals
output ecc_interrupt;
input csr_read_req;
input csr_write_req;
input [1 - 1 : 0] csr_burst_count;
input csr_beginbursttransfer;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
input [CSR_BE_WIDTH - 1 : 0] csr_be;
output csr_rdata_valid;
output csr_waitrequest;
// END PORT SECTION
//////////////////////////////////////////////////////////////////////////////
wire itf_cmd_ready;
wire itf_cmd_valid;
wire itf_cmd;
wire [LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
wire [LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
wire itf_cmd_id;
wire itf_cmd_priority;
wire itf_cmd_autopercharge;
wire itf_cmd_multicast;
wire itf_wr_data_ready;
wire itf_wr_data_valid;
wire [LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
wire [LOCAL_BE_WIDTH - 1 : 0] itf_wr_data_byte_en;
wire itf_wr_data_begin;
wire itf_wr_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
wire itf_rd_data_ready;
wire itf_rd_data_valid;
wire [LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
wire [2 - 1 : 0] itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
// Converter
alt_mem_ddrx_mm_st_converter # (
.AVL_SIZE_WIDTH ( LOCAL_SIZE_WIDTH ),
.AVL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ),
.AVL_DATA_WIDTH ( LOCAL_DATA_WIDTH ),
.CFG_MM_ST_CONV_REG ( CFG_MM_ST_CONV_REG )
) mm_st_converter_inst (
.ctl_clk ( clk ),
.ctl_reset_n ( reset_n ),
.ctl_half_clk ( half_clk ),
.ctl_half_clk_reset_n ( reset_n ),
.avl_ready ( local_ready ),
.avl_read_req ( local_read ),
.avl_write_req ( local_write ),
.avl_size ( local_burstcount ),
.avl_burstbegin ( local_beginbursttransfer ),
.avl_addr ( local_address ),
.avl_rdata_valid ( local_readdatavalid ),
.local_rdata_error ( ),
.avl_rdata ( local_readdata ),
.avl_wdata ( local_writedata ),
.avl_be ( local_byteenable ),
.local_multicast ( local_multicast ),
.local_autopch_req ( local_autopch_req ),
.local_priority ( local_priority ),
.itf_cmd_ready ( itf_cmd_ready ),
.itf_cmd_valid ( itf_cmd_valid ),
.itf_cmd ( itf_cmd ),
.itf_cmd_address ( itf_cmd_address ),
.itf_cmd_burstlen ( itf_cmd_burstlen ),
.itf_cmd_id ( itf_cmd_id ),
.itf_cmd_priority ( itf_cmd_priority ),
.itf_cmd_autopercharge ( itf_cmd_autopercharge ),
.itf_cmd_multicast ( itf_cmd_multicast ),
.itf_wr_data_ready ( itf_wr_data_ready ),
.itf_wr_data_valid ( itf_wr_data_valid ),
.itf_wr_data ( itf_wr_data ),
.itf_wr_data_byte_en ( itf_wr_data_byte_en ),
.itf_wr_data_begin ( itf_wr_data_begin ),
.itf_wr_data_last ( itf_wr_data_last ),
.itf_wr_data_id ( itf_wr_data_id ),
.itf_rd_data_ready ( itf_rd_data_ready ),
.itf_rd_data_valid ( itf_rd_data_valid ),
.itf_rd_data ( itf_rd_data ),
.itf_rd_data_error ( itf_rd_data_error ),
.itf_rd_data_begin ( itf_rd_data_begin ),
.itf_rd_data_last ( itf_rd_data_last ),
.itf_rd_data_id ( itf_rd_data_id )
);
// Next Gen Controller
//////////////////////////////////////////////////////////////////////////////
alt_mem_ddrx_controller_st_top #(
.LOCAL_SIZE_WIDTH(LOCAL_SIZE_WIDTH),
.LOCAL_ADDR_WIDTH(LOCAL_ADDR_WIDTH),
.LOCAL_DATA_WIDTH(LOCAL_DATA_WIDTH),
.LOCAL_BE_WIDTH(LOCAL_BE_WIDTH),
.LOCAL_ID_WIDTH(LOCAL_ID_WIDTH),
.LOCAL_CS_WIDTH(LOCAL_CS_WIDTH),
.MEM_IF_ADDR_WIDTH(MEM_IF_ADDR_WIDTH),
.MEM_IF_CLK_PAIR_COUNT(MEM_IF_CLK_PAIR_COUNT),
.LOCAL_IF_TYPE(LOCAL_IF_TYPE),
.DWIDTH_RATIO(DWIDTH_RATIO),
.CTL_ODT_ENABLED(CTL_ODT_ENABLED),
.CTL_OUTPUT_REGD(CTL_OUTPUT_REGD),
.CTL_TBP_NUM(CTL_TBP_NUM),
.WRBUFFER_ADDR_WIDTH(WRBUFFER_ADDR_WIDTH),
.RDBUFFER_ADDR_WIDTH(RDBUFFER_ADDR_WIDTH),
.MEM_IF_CS_WIDTH(MEM_IF_CS_WIDTH),
.MEM_IF_CHIP(MEM_IF_CHIP),
.MEM_IF_BANKADDR_WIDTH(MEM_IF_BANKADDR_WIDTH),
.MEM_IF_ROW_WIDTH(MEM_IF_ROW_WIDTH),
.MEM_IF_COL_WIDTH(MEM_IF_COL_WIDTH),
.MEM_IF_ODT_WIDTH(MEM_IF_ODT_WIDTH),
.MEM_IF_DQS_WIDTH(MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH(MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH(MEM_IF_DM_WIDTH),
.MAX_MEM_IF_CS_WIDTH(MAX_MEM_IF_CS_WIDTH),
.MAX_MEM_IF_CHIP(MAX_MEM_IF_CHIP),
.MAX_MEM_IF_BANKADDR_WIDTH(MAX_MEM_IF_BANKADDR_WIDTH),
.MAX_MEM_IF_ROWADDR_WIDTH(MAX_MEM_IF_ROWADDR_WIDTH),
.MAX_MEM_IF_COLADDR_WIDTH(MAX_MEM_IF_COLADDR_WIDTH),
.MAX_MEM_IF_ODT_WIDTH(MAX_MEM_IF_ODT_WIDTH),
.MAX_MEM_IF_DQS_WIDTH(MAX_MEM_IF_DQS_WIDTH),
.MAX_MEM_IF_DQ_WIDTH(MAX_MEM_IF_DQ_WIDTH),
.MAX_MEM_IF_MASK_WIDTH(MAX_MEM_IF_MASK_WIDTH),
.MAX_LOCAL_DATA_WIDTH(MAX_LOCAL_DATA_WIDTH),
.CFG_TYPE(CFG_TYPE),
.CFG_INTERFACE_WIDTH(CFG_INTERFACE_WIDTH),
.CFG_BURST_LENGTH(CFG_BURST_LENGTH),
.CFG_DEVICE_WIDTH(CFG_DEVICE_WIDTH),
.CFG_REORDER_DATA(CFG_REORDER_DATA),
.CFG_DATA_REORDERING_TYPE(CFG_DATA_REORDERING_TYPE),
.CFG_STARVE_LIMIT(CFG_STARVE_LIMIT),
.CFG_ADDR_ORDER(CFG_ADDR_ORDER),
.MEM_CAS_WR_LAT(MEM_CAS_WR_LAT),
.MEM_ADD_LAT(MEM_ADD_LAT),
.MEM_TCL(MEM_TCL),
.MEM_TRRD(MEM_TRRD),
.MEM_TFAW(MEM_TFAW),
.MEM_TRFC(MEM_TRFC),
.MEM_TREFI(MEM_TREFI),
.MEM_TRCD(MEM_TRCD),
.MEM_TRP(MEM_TRP),
.MEM_TWR(MEM_TWR),
.MEM_TWTR(MEM_TWTR),
.MEM_TRTP(MEM_TRTP),
.MEM_TRAS(MEM_TRAS),
.MEM_TRC(MEM_TRC),
.CFG_TCCD(CFG_TCCD),
.MEM_AUTO_PD_CYCLES(MEM_AUTO_PD_CYCLES),
.CFG_SELF_RFSH_EXIT_CYCLES(CFG_SELF_RFSH_EXIT_CYCLES),
.CFG_PDN_EXIT_CYCLES(CFG_PDN_EXIT_CYCLES),
.CFG_POWER_SAVING_EXIT_CYCLES(CFG_POWER_SAVING_EXIT_CYCLES),
.CFG_MEM_CLK_ENTRY_CYCLES(CFG_MEM_CLK_ENTRY_CYCLES),
.MEM_TMRD_CK(MEM_TMRD_CK),
.CTL_ECC_ENABLED(CTL_ECC_ENABLED),
.CTL_ECC_RMW_ENABLED(CTL_ECC_RMW_ENABLED),
.CTL_ECC_MULTIPLES_16_24_40_72(CTL_ECC_MULTIPLES_16_24_40_72),
.CFG_GEN_SBE(CFG_GEN_SBE),
.CFG_GEN_DBE(CFG_GEN_DBE),
.CFG_ENABLE_INTR(CFG_ENABLE_INTR),
.CFG_MASK_SBE_INTR(CFG_MASK_SBE_INTR),
.CFG_MASK_DBE_INTR(CFG_MASK_DBE_INTR),
.CFG_MASK_CORRDROP_INTR(CFG_MASK_CORRDROP_INTR),
.CFG_CLR_INTR(CFG_CLR_INTR),
.CTL_USR_REFRESH(CTL_USR_REFRESH),
.CTL_REGDIMM_ENABLED(CTL_REGDIMM_ENABLED),
.CFG_WRITE_ODT_CHIP(CFG_WRITE_ODT_CHIP),
.CFG_READ_ODT_CHIP(CFG_READ_ODT_CHIP),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP(CFG_PORT_WIDTH_WRITE_ODT_CHIP),
.CFG_PORT_WIDTH_READ_ODT_CHIP(CFG_PORT_WIDTH_READ_ODT_CHIP),
.MEM_IF_CKE_WIDTH(MEM_IF_CKE_WIDTH),
.CTL_CSR_ENABLED(CTL_CSR_ENABLED),
.CFG_ENABLE_NO_DM(CFG_ENABLE_NO_DM),
.CSR_ADDR_WIDTH(CSR_ADDR_WIDTH),
.CSR_DATA_WIDTH(CSR_DATA_WIDTH),
.CSR_BE_WIDTH(CSR_BE_WIDTH),
.CFG_WLAT_BUS_WIDTH(AFI_WLAT_WIDTH),
.CFG_RLAT_BUS_WIDTH(AFI_RLAT_WIDTH),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT(MEM_IF_RD_TO_WR_TURNAROUND_OCT),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT(MEM_IF_WR_TO_RD_TURNAROUND_OCT),
.CTL_RD_TO_PCH_EXTRA_CLK(CTL_RD_TO_PCH_EXTRA_CLK),
.CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK(CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK),
.CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK(CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK),
.CFG_ECC_DECODER_REG(CFG_ECC_DECODER_REG),
.CFG_ERRCMD_FIFO_REG(CFG_ERRCMD_FIFO_REG)
) controller_inst (
.clk(clk),
.half_clk(half_clk),
.reset_n(reset_n),
.itf_cmd_ready(itf_cmd_ready),
.itf_cmd_valid(itf_cmd_valid),
.itf_cmd(itf_cmd),
.itf_cmd_address(itf_cmd_address),
.itf_cmd_burstlen(itf_cmd_burstlen),
.itf_cmd_id(itf_cmd_id),
.itf_cmd_priority(itf_cmd_priority),
.itf_cmd_autopercharge(itf_cmd_autopercharge),
.itf_cmd_multicast(itf_cmd_multicast),
.itf_wr_data_ready(itf_wr_data_ready),
.itf_wr_data_valid(itf_wr_data_valid),
.itf_wr_data(itf_wr_data),
.itf_wr_data_byte_en(itf_wr_data_byte_en),
.itf_wr_data_begin(itf_wr_data_begin),
.itf_wr_data_last(itf_wr_data_last),
.itf_wr_data_id(itf_wr_data_id),
.itf_rd_data_ready(itf_rd_data_ready),
.itf_rd_data_valid(itf_rd_data_valid),
.itf_rd_data(itf_rd_data),
.itf_rd_data_error(itf_rd_data_error),
.itf_rd_data_begin(itf_rd_data_begin),
.itf_rd_data_last(itf_rd_data_last),
.itf_rd_data_id(itf_rd_data_id),
.afi_rst_n(afi_rst_n),
.afi_cs_n(afi_cs_n),
.afi_cke(afi_cke),
.afi_odt(afi_odt),
.afi_addr(afi_addr),
.afi_ba(afi_ba),
.afi_ras_n(afi_ras_n),
.afi_cas_n(afi_cas_n),
.afi_we_n(afi_we_n),
.afi_dqs_burst(afi_dqs_burst),
.afi_wdata_valid(afi_wdata_valid),
.afi_wdata(afi_wdata),
.afi_dm(afi_dm),
.afi_wlat(afi_wlat),
.afi_rdata_en(afi_rdata_en),
.afi_rdata_en_full(afi_rdata_en_full),
.afi_rdata(afi_rdata),
.afi_rdata_valid(afi_rdata_valid),
.afi_rlat(afi_rlat),
.afi_cal_success(afi_cal_success),
.afi_cal_fail(afi_cal_fail),
.afi_cal_req(afi_cal_req),
.afi_mem_clk_disable(afi_mem_clk_disable),
.afi_cal_byte_lane_sel_n(afi_cal_byte_lane_sel_n),
.afi_ctl_refresh_done(afi_ctl_refresh_done),
.afi_seq_busy(afi_seq_busy),
.afi_ctl_long_idle(afi_ctl_long_idle),
.local_init_done(local_init_done),
.local_refresh_ack(local_refresh_ack),
.local_powerdn_ack(local_powerdn_ack),
.local_self_rfsh_ack(local_self_rfsh_ack),
.local_refresh_req(local_refresh_req),
.local_refresh_chip(local_refresh_chip),
.local_powerdn_req(local_powerdn_req),
.local_self_rfsh_req(local_self_rfsh_req),
.local_self_rfsh_chip(local_self_rfsh_chip),
.local_multicast(local_multicast),
.local_priority(local_priority),
.ecc_interrupt(ecc_interrupt),
.csr_read_req(csr_read_req),
.csr_write_req(csr_write_req),
.csr_burst_count(csr_burst_count),
.csr_beginbursttransfer(csr_beginbursttransfer),
.csr_addr(csr_addr),
.csr_wdata(csr_wdata),
.csr_rdata(csr_rdata),
.csr_be(csr_be),
.csr_rdata_valid(csr_rdata_valid),
.csr_waitrequest(csr_waitrequest)
);
endmodule |
module Serial_flash_loader (
input wire noe_in // noe_in.noe
);
altera_serial_flash_loader #(
.INTENDED_DEVICE_FAMILY ("Cyclone IV E"),
.ENHANCED_MODE (1),
.ENABLE_SHARED_ACCESS ("OFF"),
.ENABLE_QUAD_SPI_SUPPORT (0),
.NCSO_WIDTH (1)
) serial_flash_loader_0 (
.noe_in (noe_in) // noe_in.noe
);
endmodule |
module altera_serial_flash_loader (
asmi_access_granted,
asdo_in,
data_in,
data_oe,
dclk_in,
ncso_in,
noe_in,
asmi_access_request,
data0_out,
data_out);
parameter
ENABLE_QUAD_SPI_SUPPORT = 1,
ENABLE_SHARED_ACCESS = "ON",
ENHANCED_MODE = 1,
INTENDED_DEVICE_FAMILY = "Arria 10",
NCSO_WIDTH = 3;
input asmi_access_granted;
input asdo_in;
input [3:0] data_in;
input [3:0] data_oe;
input dclk_in;
input [NCSO_WIDTH-1:0] ncso_in;
input noe_in;
output asmi_access_request;
output data0_out;
output [3:0] data_out;
wire sub_wire0;
wire sub_wire1;
wire [3:0] sub_wire2;
wire asmi_access_request = sub_wire0;
wire data0_out = sub_wire1;
wire [3:0] data_out = sub_wire2[3:0];
altserial_flash_loader altserial_flash_loader_component (
.asmi_access_granted (asmi_access_granted),
.data_in (data_in),
.data_oe (data_oe),
.dclkin (dclk_in),
.noe (noe_in),
.scein (ncso_in),
.asmi_access_request (sub_wire0),
.data_out (sub_wire2),
.data0out (sub_wire1),
.sdoin (asdo_in)
);
defparam
altserial_flash_loader_component.enable_quad_spi_support = ENABLE_QUAD_SPI_SUPPORT,
altserial_flash_loader_component.enable_shared_access = ENABLE_SHARED_ACCESS,
altserial_flash_loader_component.enhanced_mode = ENHANCED_MODE,
altserial_flash_loader_component.intended_device_family = INTENDED_DEVICE_FAMILY,
altserial_flash_loader_component.ncso_width = NCSO_WIDTH;
endmodule |
module ddr2_traffic_gen (
clk,
reset_n,
pass,
fail,
test_complete,
avl_ready,
avl_addr,
avl_size,
avl_wdata,
avl_rdata,
avl_write_req,
avl_read_req,
avl_rdata_valid,
avl_be,
avl_burstbegin,
pnf_per_bit,
pnf_per_bit_persist);
input clk;
input reset_n;
output pass;
output fail;
output test_complete;
input avl_ready;
output [24:0] avl_addr;
output [1:0] avl_size;
output [31:0] avl_wdata;
input [31:0] avl_rdata;
output avl_write_req;
output avl_read_req;
input avl_rdata_valid;
output [3:0] avl_be;
output avl_burstbegin;
output [31:0] pnf_per_bit;
output [31:0] pnf_per_bit_persist;
endmodule |
module ddr2_traffic_gen_mm_traffic_generator_0 #(
parameter DEVICE_FAMILY = "Cyclone IV E",
parameter TG_AVL_DATA_WIDTH = 32,
parameter TG_AVL_ADDR_WIDTH = 25,
parameter TG_AVL_WORD_ADDR_WIDTH = 23,
parameter TG_AVL_SIZE_WIDTH = 2,
parameter TG_AVL_BE_WIDTH = 4,
parameter DRIVER_SIGNATURE = 1431634071,
parameter TG_GEN_BYTE_ADDR = 1,
parameter TG_NUM_DRIVER_LOOP = 1000,
parameter TG_ENABLE_UNIX_ID = 0,
parameter TG_USE_UNIX_ID = 0,
parameter TG_RANDOM_BYTE_ENABLE = 0,
parameter TG_ENABLE_READ_COMPARE = 1,
parameter TG_POWER_OF_TWO_BURSTS_ONLY = 0,
parameter TG_BURST_ON_BURST_BOUNDARY = 0,
parameter TG_DO_NOT_CROSS_4KB_BOUNDARY = 0,
parameter TG_TIMEOUT_COUNTER_WIDTH = 32,
parameter TG_MAX_READ_LATENCY = 20,
parameter TG_SINGLE_RW_SEQ_ADDR_COUNT = 32,
parameter TG_SINGLE_RW_RAND_ADDR_COUNT = 32,
parameter TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT = 32,
parameter TG_BLOCK_RW_SEQ_ADDR_COUNT = 8,
parameter TG_BLOCK_RW_RAND_ADDR_COUNT = 8,
parameter TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT = 8,
parameter TG_BLOCK_RW_BLOCK_SIZE = 8,
parameter TG_TEMPLATE_STAGE_COUNT = 4,
parameter TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT = 1,
parameter TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT = 2,
parameter TG_RAND_ADDR_GEN_MIN_BURSTCOUNT = 1,
parameter TG_RAND_ADDR_GEN_MAX_BURSTCOUNT = 2,
parameter TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT = 1,
parameter TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT = 2,
parameter TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT = 50
) (
input wire clk, // avl_clock.clk
input wire reset_n, // avl_reset.reset_n
output wire pass, // status.pass
output wire fail, // .fail
output wire test_complete, // .test_complete
output wire [31:0] pnf_per_bit, // pnf.pnf_per_bit
output wire [31:0] pnf_per_bit_persist, // .pnf_per_bit_persist
input wire avl_ready, // avl.waitrequest_n
output wire [24:0] avl_addr, // .address
output wire [1:0] avl_size, // .burstcount
output wire [31:0] avl_wdata, // .writedata
input wire [31:0] avl_rdata, // .readdata
output wire avl_write_req, // .write
output wire avl_read_req, // .read
input wire avl_rdata_valid, // .readdatavalid
output wire [3:0] avl_be, // .byteenable
output wire avl_burstbegin // .beginbursttransfer
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (DEVICE_FAMILY != "Cyclone IV E")
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
device_family_check ( .error(1'b1) );
end
if (TG_AVL_DATA_WIDTH != 32)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_data_width_check ( .error(1'b1) );
end
if (TG_AVL_ADDR_WIDTH != 25)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_addr_width_check ( .error(1'b1) );
end
if (TG_AVL_WORD_ADDR_WIDTH != 23)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_word_addr_width_check ( .error(1'b1) );
end
if (TG_AVL_SIZE_WIDTH != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_size_width_check ( .error(1'b1) );
end
if (TG_AVL_BE_WIDTH != 4)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_avl_be_width_check ( .error(1'b1) );
end
if (DRIVER_SIGNATURE != 1431634071)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
driver_signature_check ( .error(1'b1) );
end
if (TG_GEN_BYTE_ADDR != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_gen_byte_addr_check ( .error(1'b1) );
end
if (TG_NUM_DRIVER_LOOP != 1000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_num_driver_loop_check ( .error(1'b1) );
end
if (TG_ENABLE_UNIX_ID != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_enable_unix_id_check ( .error(1'b1) );
end
if (TG_USE_UNIX_ID != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_use_unix_id_check ( .error(1'b1) );
end
if (TG_RANDOM_BYTE_ENABLE != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_random_byte_enable_check ( .error(1'b1) );
end
if (TG_ENABLE_READ_COMPARE != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_enable_read_compare_check ( .error(1'b1) );
end
if (TG_POWER_OF_TWO_BURSTS_ONLY != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_power_of_two_bursts_only_check ( .error(1'b1) );
end
if (TG_BURST_ON_BURST_BOUNDARY != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_burst_on_burst_boundary_check ( .error(1'b1) );
end
if (TG_DO_NOT_CROSS_4KB_BOUNDARY != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_do_not_cross_4kb_boundary_check ( .error(1'b1) );
end
if (TG_TIMEOUT_COUNTER_WIDTH != 32)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_timeout_counter_width_check ( .error(1'b1) );
end
if (TG_MAX_READ_LATENCY != 20)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_max_read_latency_check ( .error(1'b1) );
end
if (TG_SINGLE_RW_SEQ_ADDR_COUNT != 32)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_single_rw_seq_addr_count_check ( .error(1'b1) );
end
if (TG_SINGLE_RW_RAND_ADDR_COUNT != 32)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_single_rw_rand_addr_count_check ( .error(1'b1) );
end
if (TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT != 32)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_single_rw_rand_seq_addr_count_check ( .error(1'b1) );
end
if (TG_BLOCK_RW_SEQ_ADDR_COUNT != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_block_rw_seq_addr_count_check ( .error(1'b1) );
end
if (TG_BLOCK_RW_RAND_ADDR_COUNT != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_block_rw_rand_addr_count_check ( .error(1'b1) );
end
if (TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_block_rw_rand_seq_addr_count_check ( .error(1'b1) );
end
if (TG_BLOCK_RW_BLOCK_SIZE != 8)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_block_rw_block_size_check ( .error(1'b1) );
end
if (TG_TEMPLATE_STAGE_COUNT != 4)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_template_stage_count_check ( .error(1'b1) );
end
if (TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_seq_addr_gen_min_burstcount_check ( .error(1'b1) );
end
if (TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_seq_addr_gen_max_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_ADDR_GEN_MIN_BURSTCOUNT != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_addr_gen_min_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_ADDR_GEN_MAX_BURSTCOUNT != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_addr_gen_max_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_seq_addr_gen_min_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_seq_addr_gen_max_burstcount_check ( .error(1'b1) );
end
if (TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT != 50)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
tg_rand_seq_addr_gen_rand_addr_percent_check ( .error(1'b1) );
end
endgenerate
driver_avl_use_be_avl_use_burstbegin #(
.DEVICE_FAMILY ("Cyclone IV E"),
.TG_AVL_DATA_WIDTH (32),
.TG_AVL_ADDR_WIDTH (25),
.TG_AVL_WORD_ADDR_WIDTH (23),
.TG_AVL_SIZE_WIDTH (2),
.TG_AVL_BE_WIDTH (4),
.DRIVER_SIGNATURE (1431634071),
.TG_GEN_BYTE_ADDR (1),
.TG_NUM_DRIVER_LOOP (1000),
.TG_ENABLE_UNIX_ID (0),
.TG_USE_UNIX_ID (0),
.TG_RANDOM_BYTE_ENABLE (0),
.TG_ENABLE_READ_COMPARE (1),
.TG_POWER_OF_TWO_BURSTS_ONLY (0),
.TG_BURST_ON_BURST_BOUNDARY (0),
.TG_DO_NOT_CROSS_4KB_BOUNDARY (0),
.TG_TIMEOUT_COUNTER_WIDTH (32),
.TG_MAX_READ_LATENCY (20),
.TG_SINGLE_RW_SEQ_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT (32),
.TG_BLOCK_RW_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_BLOCK_SIZE (8),
.TG_TEMPLATE_STAGE_COUNT (4),
.TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT (2),
.TG_RAND_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_ADDR_GEN_MAX_BURSTCOUNT (2),
.TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT (2),
.TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT (50)
) traffic_generator_0 (
.pass (pass), // status.pass
.fail (fail), // .fail
.test_complete (test_complete), // .test_complete
.pnf_per_bit (pnf_per_bit), // pnf.pnf_per_bit
.pnf_per_bit_persist (pnf_per_bit_persist), // .pnf_per_bit_persist
.clk (clk), // avl_clock.clk
.reset_n (reset_n), // avl_reset.reset_n
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_addr (avl_addr), // .address
.avl_size (avl_size), // .burstcount
.avl_wdata (avl_wdata), // .writedata
.avl_rdata (avl_rdata), // .readdata
.avl_write_req (avl_write_req), // .write
.avl_read_req (avl_read_req), // .read
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_be (avl_be), // .byteenable
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.csr_address (13'b0000000000000), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_be (4'b0000) // (terminated)
);
endmodule |
module clkctrl (
inclk,
ena,
outclk);
input inclk;
input ena;
output outclk;
endmodule |
module clkctrl (
input wire inclk, // altclkctrl_input.inclk
input wire ena, // .ena
output wire outclk // altclkctrl_output.outclk
);
clkctrl_altclkctrl_0 altclkctrl_0 (
.inclk (inclk), // altclkctrl_input.inclk
.ena (ena), // .ena
.outclk (outclk) // altclkctrl_output.outclk
);
endmodule |
module mgqo8
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [3:0] data;
output [15:0] eq;
wire [15:0] wire_mgl_prim1_eq;
lpm_decode mgl_prim1
(
.data(data),
.eq(wire_mgl_prim1_eq));
defparam
mgl_prim1.lpm_decodes = 16,
mgl_prim1.lpm_type = "LPM_DECODE",
mgl_prim1.lpm_width = 4;
assign
eq = wire_mgl_prim1_eq;
endmodule //mgqo8 |
module mg4h8
(
data) /* synthesis synthesis_clearbox=1 */;
input [3:0] data;
lpm_decode mgl_prim1
(
.data(data));
defparam
mgl_prim1.lpm_decodes = 16,
mgl_prim1.lpm_type = "LPM_DECODE",
mgl_prim1.lpm_width = 4;
endmodule //mg4h8 |
module IQSerializer(
input clk,
input start,
input [`ILength-1:0] I,
input [`QLength-1:0] Q,
output serial_N,
output serial,
output serial_clk
);
parameter VCC = 1'b1;
parameter VSS = 1'b0;
//states
reg [3:0] current_state;
reg [3:0] next_state;
parameter [3:0] Init0 = 4'h0, Init1 = 4'h1, ISYNC = 4'h2, IDATA = 4'h3, QSYNC = 4'h4, QDATA = 4'h5;
(* syn_preserve = "TRUE" *) reg [3:0] ICounter;
(* syn_preserve = "TRUE" *) reg [3:0] QCounter;
//output clock
assign serial_clk = clk;
//Double Edge DFF
reg DEDFF_D0;
reg DEDFF_D1;
wire DEDFF_Q;
wire DEDFF_rst;
assign serial = DEDFF_Q;
assign serial_N = ~DEDFF_Q;
assign DEDFF_rst = start;
/*
* Update Double Edge DFF
*/
always @(*) begin
case(current_state)
Init0: begin
DEDFF_D0 = VSS;
DEDFF_D1 = VSS;
end
Init1: begin
DEDFF_D0 = VSS;
DEDFF_D1 = VSS;
end
ISYNC: begin
DEDFF_D0 = VCC;
DEDFF_D1 = VSS;
end
IDATA: begin
DEDFF_D0 = I[`ILength-ICounter-1];
DEDFF_D1 = I[`ILength-ICounter-2];
end
QSYNC: begin
DEDFF_D0 = VSS;
DEDFF_D1 = VCC;
end
QDATA: begin
DEDFF_D0 = Q[`QLength-QCounter-1];
DEDFF_D1 = Q[`QLength-QCounter-2];
end
default: begin
DEDFF_D0 = VSS;
DEDFF_D1 = VSS;
end
endcase
end
/*
* Update Counters
*/
always @(negedge clk) begin
if (start == VSS) begin
ICounter <= 4'd0;
QCounter <= 4'd0;
//I <= `ILength'd0;
//Q <= `QLength'h0;
end else begin
if (current_state == IDATA) ICounter <= ICounter + 4'd2;
else ICounter <= 4'd0;
if (current_state == QDATA) QCounter <= QCounter + 4'd2;
else QCounter <= 4'd0;
//uncomment this for constant I/Q
//I <= `ILength'b11000000000011;
//Q <= `QLength'b00111111111100;
//if (current_state == QSYNC) I <= I + 1;
//else I <= I;
//
//if (current_state == ISYNC) Q <= Q + 1;
//else Q <= Q;
end
end
/*
* Next States
*/
always @(negedge clk) begin
current_state <= next_state;
end
always @(*) begin
if (start == VSS) begin
next_state = Init0;
end else begin
case(current_state)
Init0: begin
next_state = ISYNC;
end
Init1: begin
next_state = ISYNC;
end
ISYNC: begin
next_state = IDATA;
end
IDATA: begin
if (ICounter == 4'd12) begin
next_state = QSYNC;
end else begin
next_state = IDATA;
end
end
QSYNC: begin
next_state = QDATA;
end
QDATA: begin
if (QCounter == 4'd12) begin
next_state = ISYNC;
end else begin
next_state = QDATA;
end
end
default: begin
next_state = Init0;
end
endcase
end
end
DEDFF DEDFF_0(
// Inputs
.clk(clk),
.rst(DEDFF_rst),
.D0(DEDFF_D0),
.D1(DEDFF_D1),
// Outputs
.Q(DEDFF_Q)
);
endmodule |
module sinIdeal(angle, sinOut);
input [`PRECISION-1:0] angle;
output reg [`SinSize-1:0] sinOut;
reg [`PRECISION-1:0] index;
always @(*) begin
index = angle >> (25-`Sine_SR_Bits);
end
always @(index) begin
if (index < 12)
sinOut = `SinSize'b0000000000000;
else if (index < 22)
sinOut = `SinSize'b0000000111111;
else if (index < 32)
sinOut = `SinSize'b0000001111111;
else if (index < 42)
sinOut = `SinSize'b0000010111111;
else if (index < 52)
sinOut = `SinSize'b0000011111111;
else if (index < 62)
sinOut = `SinSize'b0000100111111;
else if (index < 72)
sinOut = `SinSize'b0000101111111;
else if (index < 84)
sinOut = `SinSize'b0000110111111;
else if (index < 94)
sinOut = `SinSize'b0000111111111;
else if (index < 104)
sinOut = `SinSize'b0001000111111;
else if (index < 114)
sinOut = `SinSize'b0001001111111;
else if (index < 124)
sinOut = `SinSize'b0001010111111;
else if (index < 134)
sinOut = `SinSize'b0001011111111;
else if (index < 144)
sinOut = `SinSize'b0001100111111;
else if (index < 154)
sinOut = `SinSize'b0001101111111;
else if (index < 166)
sinOut = `SinSize'b0001110111111;
else if (index < 176)
sinOut = `SinSize'b0001111111111;
else if (index < 186)
sinOut = `SinSize'b0010000111111;
else if (index < 196)
sinOut = `SinSize'b0010001111111;
else if (index < 208)
sinOut = `SinSize'b0010010111111;
else if (index < 218)
sinOut = `SinSize'b0010011111111;
else if (index < 228)
sinOut = `SinSize'b0010100111111;
else if (index < 240)
sinOut = `SinSize'b0010101111111;
else if (index < 250)
sinOut = `SinSize'b0010110111111;
else if (index < 262)
sinOut = `SinSize'b0010111111111;
else if (index < 272)
sinOut = `SinSize'b0011000111111;
else if (index < 284)
sinOut = `SinSize'b0011001111111;
else if (index < 294)
sinOut = `SinSize'b0011010111111;
else if (index < 306)
sinOut = `SinSize'b0011011111111;
else if (index < 318)
sinOut = `SinSize'b0011100111111;
else if (index < 328)
sinOut = `SinSize'b0011101111111;
else if (index < 341)
sinOut = `SinSize'b0011110111111;
else if (index < 352)
sinOut = `SinSize'b0011111111111;
else if (index < 364)
sinOut = `SinSize'b0100000111111;
else if (index < 377)
sinOut = `SinSize'b0100001111111;
else if (index < 388)
sinOut = `SinSize'b0100010111111;
else if (index < 401)
sinOut = `SinSize'b0100011111111;
else if (index < 412)
sinOut = `SinSize'b0100100111111;
else if (index < 427)
sinOut = `SinSize'b0100101111111;
else if (index < 438)
sinOut = `SinSize'b0100110111111;
else if (index < 452)
sinOut = `SinSize'b0100111111111;
else if (index < 465)
sinOut = `SinSize'b0101000111111;
else if (index < 478)
sinOut = `SinSize'b0101001111111;
else if (index < 492)
sinOut = `SinSize'b0101010111111;
else if (index < 507)
sinOut = `SinSize'b0101011111111;
else if (index < 520)
sinOut = `SinSize'b0101100111111;
else if (index < 535)
sinOut = `SinSize'b0101101111111;
else if (index < 551)
sinOut = `SinSize'b0101110111111;
else if (index < 564)
sinOut = `SinSize'b0101111111111;
else if (index < 580)
sinOut = `SinSize'b0110000111111;
else if (index < 597)
sinOut = `SinSize'b0110001111111;
else if (index < 615)
sinOut = `SinSize'b0110010111111;
else if (index < 630)
sinOut = `SinSize'b0110011111111;
else if (index < 648)
sinOut = `SinSize'b0110100111111;
else if (index < 668)
sinOut = `SinSize'b0110101111111;
else if (index < 688)
sinOut = `SinSize'b0110110111111;
else if (index < 708)
sinOut = `SinSize'b0110111111111;
else if (index < 730)
sinOut = `SinSize'b0111000111111;
else if (index < 754)
sinOut = `SinSize'b0111001111111;
else if (index < 780)
sinOut = `SinSize'b0111010111111;
else if (index < 810)
sinOut = `SinSize'b0111011111111;
else if (index < 844)
sinOut = `SinSize'b0111100111111;
else if (index < 884)
sinOut = `SinSize'b0111101111111;
else if (index < 944)
sinOut = `SinSize'b0111110111111;
else if (index < 1108)
sinOut = `SinSize'b0111111111111;
else if (index < 1168)
sinOut = `SinSize'b0111110111111;
else if (index < 1208)
sinOut = `SinSize'b0111101111111;
else if (index < 1242)
sinOut = `SinSize'b0111100111111;
else if (index < 1272)
sinOut = `SinSize'b0111011111111;
else if (index < 1298)
sinOut = `SinSize'b0111010111111;
else if (index < 1322)
sinOut = `SinSize'b0111001111111;
else if (index < 1344)
sinOut = `SinSize'b0111000111111;
else if (index < 1364)
sinOut = `SinSize'b0110111111111;
else if (index < 1384)
sinOut = `SinSize'b0110110111111;
else if (index < 1405)
sinOut = `SinSize'b0110101111111;
else if (index < 1422)
sinOut = `SinSize'b0110100111111;
else if (index < 1438)
sinOut = `SinSize'b0110011111111;
else if (index < 1457)
sinOut = `SinSize'b0110010111111;
else if (index < 1472)
sinOut = `SinSize'b0110001111111;
else if (index < 1488)
sinOut = `SinSize'b0110000111111;
else if (index < 1502)
sinOut = `SinSize'b0101111111111;
else if (index < 1518)
sinOut = `SinSize'b0101110111111;
else if (index < 1532)
sinOut = `SinSize'b0101101111111;
else if (index < 1546)
sinOut = `SinSize'b0101100111111;
else if (index < 1560)
sinOut = `SinSize'b0101011111111;
else if (index < 1574)
sinOut = `SinSize'b0101010111111;
else if (index < 1589)
sinOut = `SinSize'b0101001111111;
else if (index < 1600)
sinOut = `SinSize'b0101000111111;
else if (index < 1614)
sinOut = `SinSize'b0100111111111;
else if (index < 1626)
sinOut = `SinSize'b0100110111111;
else if (index < 1640)
sinOut = `SinSize'b0100101111111;
else if (index < 1653)
sinOut = `SinSize'b0100100111111;
else if (index < 1664)
sinOut = `SinSize'b0100011111111;
else if (index < 1676)
sinOut = `SinSize'b0100010111111;
else if (index < 1689)
sinOut = `SinSize'b0100001111111;
else if (index < 1700)
sinOut = `SinSize'b0100000111111;
else if (index < 1713)
sinOut = `SinSize'b0011111111111;
else if (index < 1724)
sinOut = `SinSize'b0011110111111;
else if (index < 1735)
sinOut = `SinSize'b0011101111111;
else if (index < 1746)
sinOut = `SinSize'b0011100111111;
else if (index < 1758)
sinOut = `SinSize'b0011011111111;
else if (index < 1768)
sinOut = `SinSize'b0011010111111;
else if (index < 1780)
sinOut = `SinSize'b0011001111111;
else if (index < 1790)
sinOut = `SinSize'b0011000111111;
else if (index < 1802)
sinOut = `SinSize'b0010111111111;
else if (index < 1812)
sinOut = `SinSize'b0010110111111;
else if (index < 1824)
sinOut = `SinSize'b0010101111111;
else if (index < 1834)
sinOut = `SinSize'b0010100111111;
else if (index < 1845)
sinOut = `SinSize'b0010011111111;
else if (index < 1856)
sinOut = `SinSize'b0010010111111;
else if (index < 1867)
sinOut = `SinSize'b0010001111111;
else if (index < 1876)
sinOut = `SinSize'b0010000111111;
else if (index < 1887)
sinOut = `SinSize'b0001111111111;
else if (index < 1898)
sinOut = `SinSize'b0001110111111;
else if (index < 1909)
sinOut = `SinSize'b0001101111111;
else if (index < 1918)
sinOut = `SinSize'b0001100111111;
else if (index < 1928)
sinOut = `SinSize'b0001011111111;
else if (index < 1939)
sinOut = `SinSize'b0001010111111;
else if (index < 1948)
sinOut = `SinSize'b0001001111111;
else if (index < 1958)
sinOut = `SinSize'b0001000111111;
else if (index < 1969)
sinOut = `SinSize'b0000111111111;
else if (index < 1980)
sinOut = `SinSize'b0000110111111;
else if (index < 1991)
sinOut = `SinSize'b0000101111111;
else if (index < 2000)
sinOut = `SinSize'b0000100111111;
else if (index < 2011)
sinOut = `SinSize'b0000011111111;
else if (index < 2020)
sinOut = `SinSize'b0000010111111;
else if (index < 2030)
sinOut = `SinSize'b0000001111111;
else if (index < 2041)
sinOut = `SinSize'b0000000111111;
else if (index < 2060)
sinOut = `SinSize'b0000000000000;
else if (index < 2071)
sinOut = `SinSize'b1111111000001;
else if (index < 2080)
sinOut = `SinSize'b1111110000001;
else if (index < 2090)
sinOut = `SinSize'b1111101000001;
else if (index < 2101)
sinOut = `SinSize'b1111100000001;
else if (index < 2110)
sinOut = `SinSize'b1111011000001;
else if (index < 2121)
sinOut = `SinSize'b1111010000001;
else if (index < 2132)
sinOut = `SinSize'b1111001000001;
else if (index < 2143)
sinOut = `SinSize'b1111000000001;
else if (index < 2152)
sinOut = `SinSize'b1110111000001;
else if (index < 2162)
sinOut = `SinSize'b1110110000001;
else if (index < 2173)
sinOut = `SinSize'b1110101000001;
else if (index < 2182)
sinOut = `SinSize'b1110100000001;
else if (index < 2192)
sinOut = `SinSize'b1110011000001;
else if (index < 2203)
sinOut = `SinSize'b1110010000001;
else if (index < 2214)
sinOut = `SinSize'b1110001000001;
else if (index < 2225)
sinOut = `SinSize'b1110000000001;
else if (index < 2234)
sinOut = `SinSize'b1101111000001;
else if (index < 2245)
sinOut = `SinSize'b1101110000001;
else if (index < 2256)
sinOut = `SinSize'b1101101000001;
else if (index < 2267)
sinOut = `SinSize'b1101100000001;
else if (index < 2276)
sinOut = `SinSize'b1101011000001;
else if (index < 2289)
sinOut = `SinSize'b1101010000001;
else if (index < 2298)
sinOut = `SinSize'b1101001000001;
else if (index < 2311)
sinOut = `SinSize'b1101000000001;
else if (index < 2320)
sinOut = `SinSize'b1100111000001;
else if (index < 2333)
sinOut = `SinSize'b1100110000001;
else if (index < 2342)
sinOut = `SinSize'b1100101000001;
else if (index < 2355)
sinOut = `SinSize'b1100100000001;
else if (index < 2366)
sinOut = `SinSize'b1100011000001;
else if (index < 2377)
sinOut = `SinSize'b1100010000001;
else if (index < 2388)
sinOut = `SinSize'b1100001000001;
else if (index < 2401)
sinOut = `SinSize'b1100000000001;
else if (index < 2412)
sinOut = `SinSize'b1011111000001;
else if (index < 2424)
sinOut = `SinSize'b1011110000001;
else if (index < 2437)
sinOut = `SinSize'b1011101000001;
else if (index < 2448)
sinOut = `SinSize'b1011100000001;
else if (index < 2460)
sinOut = `SinSize'b1011011000001;
else if (index < 2474)
sinOut = `SinSize'b1011010000001;
else if (index < 2487)
sinOut = `SinSize'b1011001000001;
else if (index < 2501)
sinOut = `SinSize'b1011000000001;
else if (index < 2512)
sinOut = `SinSize'b1010111000001;
else if (index < 2526)
sinOut = `SinSize'b1010110000001;
else if (index < 2540)
sinOut = `SinSize'b1010101000001;
else if (index < 2554)
sinOut = `SinSize'b1010100000001;
else if (index < 2569)
sinOut = `SinSize'b1010011000001;
else if (index < 2583)
sinOut = `SinSize'b1010010000001;
else if (index < 2598)
sinOut = `SinSize'b1010001000001;
else if (index < 2612)
sinOut = `SinSize'b1010000000001;
else if (index < 2628)
sinOut = `SinSize'b1001111000001;
else if (index < 2644)
sinOut = `SinSize'b1001110000001;
else if (index < 2662)
sinOut = `SinSize'b1001101000001;
else if (index < 2678)
sinOut = `SinSize'b1001100000001;
else if (index < 2697)
sinOut = `SinSize'b1001011000001;
else if (index < 2716)
sinOut = `SinSize'b1001010000001;
else if (index < 2736)
sinOut = `SinSize'b1001001000001;
else if (index < 2756)
sinOut = `SinSize'b1001000000001;
else if (index < 2778)
sinOut = `SinSize'b1000111000001;
else if (index < 2802)
sinOut = `SinSize'b1000110000001;
else if (index < 2828)
sinOut = `SinSize'b1000101000001;
else if (index < 2858)
sinOut = `SinSize'b1000100000001;
else if (index < 2892)
sinOut = `SinSize'b1000011000001;
else if (index < 2932)
sinOut = `SinSize'b1000010000001;
else if (index < 2992)
sinOut = `SinSize'b1000001000001;
else if (index < 3156)
sinOut = `SinSize'b1000000000001;
else if (index < 3216)
sinOut = `SinSize'b1000001000001;
else if (index < 3256)
sinOut = `SinSize'b1000010000001;
else if (index < 3290)
sinOut = `SinSize'b1000011000001;
else if (index < 3320)
sinOut = `SinSize'b1000100000001;
else if (index < 3347)
sinOut = `SinSize'b1000101000001;
else if (index < 3370)
sinOut = `SinSize'b1000110000001;
else if (index < 3392)
sinOut = `SinSize'b1000111000001;
else if (index < 3413)
sinOut = `SinSize'b1001000000001;
else if (index < 3432)
sinOut = `SinSize'b1001001000001;
else if (index < 3452)
sinOut = `SinSize'b1001010000001;
else if (index < 3470)
sinOut = `SinSize'b1001011000001;
else if (index < 3486)
sinOut = `SinSize'b1001100000001;
else if (index < 3504)
sinOut = `SinSize'b1001101000001;
else if (index < 3520)
sinOut = `SinSize'b1001110000001;
else if (index < 3536)
sinOut = `SinSize'b1001111000001;
else if (index < 3551)
sinOut = `SinSize'b1010000000001;
else if (index < 3567)
sinOut = `SinSize'b1010001000001;
else if (index < 3580)
sinOut = `SinSize'b1010010000001;
else if (index < 3595)
sinOut = `SinSize'b1010011000001;
else if (index < 3608)
sinOut = `SinSize'b1010100000001;
else if (index < 3622)
sinOut = `SinSize'b1010101000001;
else if (index < 3636)
sinOut = `SinSize'b1010110000001;
else if (index < 3648)
sinOut = `SinSize'b1010111000001;
else if (index < 3662)
sinOut = `SinSize'b1011000000001;
else if (index < 3674)
sinOut = `SinSize'b1011001000001;
else if (index < 3688)
sinOut = `SinSize'b1011010000001;
else if (index < 3700)
sinOut = `SinSize'b1011011000001;
else if (index < 3712)
sinOut = `SinSize'b1011100000001;
else if (index < 3724)
sinOut = `SinSize'b1011101000001;
else if (index < 3736)
sinOut = `SinSize'b1011110000001;
else if (index < 3749)
sinOut = `SinSize'b1011111000001;
else if (index < 3760)
sinOut = `SinSize'b1100000000001;
else if (index < 3772)
sinOut = `SinSize'b1100001000001;
else if (index < 3782)
sinOut = `SinSize'b1100010000001;
else if (index < 3794)
sinOut = `SinSize'b1100011000001;
else if (index < 3806)
sinOut = `SinSize'b1100100000001;
else if (index < 3816)
sinOut = `SinSize'b1100101000001;
else if (index < 3828)
sinOut = `SinSize'b1100110000001;
else if (index < 3838)
sinOut = `SinSize'b1100111000001;
else if (index < 3850)
sinOut = `SinSize'b1101000000001;
else if (index < 3860)
sinOut = `SinSize'b1101001000001;
else if (index < 3872)
sinOut = `SinSize'b1101010000001;
else if (index < 3882)
sinOut = `SinSize'b1101011000001;
else if (index < 3892)
sinOut = `SinSize'b1101100000001;
else if (index < 3904)
sinOut = `SinSize'b1101101000001;
else if (index < 3914)
sinOut = `SinSize'b1101110000001;
else if (index < 3925)
sinOut = `SinSize'b1101111000001;
else if (index < 3934)
sinOut = `SinSize'b1110000000001;
else if (index < 3947)
sinOut = `SinSize'b1110001000001;
else if (index < 3956)
sinOut = `SinSize'b1110010000001;
else if (index < 3966)
sinOut = `SinSize'b1110011000001;
else if (index < 3976)
sinOut = `SinSize'b1110100000001;
else if (index < 3986)
sinOut = `SinSize'b1110101000001;
else if (index < 3997)
sinOut = `SinSize'b1110110000001;
else if (index < 4006)
sinOut = `SinSize'b1110111000001;
else if (index < 4016)
sinOut = `SinSize'b1111000000001;
else if (index < 4028)
sinOut = `SinSize'b1111001000001;
else if (index < 4038)
sinOut = `SinSize'b1111010000001;
else if (index < 4048)
sinOut = `SinSize'b1111011000001;
else if (index < 4058)
sinOut = `SinSize'b1111100000001;
else if (index < 4068)
sinOut = `SinSize'b1111101000001;
else if (index < 4079)
sinOut = `SinSize'b1111110000001;
else if (index < 4088)
sinOut = `SinSize'b1111111000001;
else
sinOut = `SinSize'b0000000000000;
end
endmodule |
module chirpGenerator(
input chirpReset,
input clk,
input signed [`PRECISION-1:0] basephase,
input [`CHIRP_TYPE_SIZE-1:0] chirpType,
input [`PRECISION-1:0] BW_SR,
input [`PRECISION-1:0] phaseInc_val,
input [`PRECISION-1:0] symbol_size,
output wire [`SinSize-1:0] outcos,
output wire [`SinSize-1:0] outsin,
output reg done
);
reg signed [`PRECISION-1:0] acc;
reg signed [`PRECISION-1:0] accNext;
reg signed [`PRECISION-1:0] phase;
reg signed [`PRECISION-1:0] phaseNext;
reg [`PRECISION-1:0] chirp_count;
wire signed [`PRECISION-1:0] phaseNextOut;
wire signed [`PRECISION-1:0] accNextOut;
parameter const1 = 2'd1;
parameter const2 = 2'd2;
parameter const3 = 2'd3;
parameter VSS = 1'b0;
always @(*) begin
if (chirpReset == VSS) begin
accNext = `PRECISION'd0;
phaseNext = `PRECISION'd0;
end else begin
accNext = accNextOut;
phaseNext = phaseNextOut;
end
end
always @(posedge clk) begin
if (chirpReset == VSS) begin
chirp_count <= `PRECISION'd0;
acc <= `PRECISION'd0;
phase <= `PRECISION'd0;
done <= 1'b0;
end else begin
phase <= (chirp_count == `PRECISION'd0) ? basephase : phaseNext;
acc <= accNext;
if (chirpType == `TYPE_Q_DOWNCHIRP) begin
//chirp_count <= (chirp_count == symbol_size/4-1) ? 0 : chirp_count + 1;
if ((chirp_count + `PRECISION'd1) == symbol_size) begin
chirp_count <= `PRECISION'd0;
done <= 1'b1;
end else begin
chirp_count <= chirp_count + `PRECISION'd1;
done <= 1'b0;
end
end else begin
//chirp_count <= (chirp_count+1 == symbol_size) ? 0 : chirp_count + 1;
if ((chirp_count + `PRECISION'd1) == symbol_size) begin
chirp_count <= `PRECISION'd0;
done <= 1'b1;
end else begin
chirp_count <= chirp_count + `PRECISION'd1;
done <= 1'b0;
end
end
end
end
phaseInc phase_u1(
.phaseIn(phase),
.chirpType(chirpType),
.BW_SR(BW_SR),
.phaseInc_val(phaseInc_val),
.phaseOut(phaseNextOut)
);
accInc accInc_u1(
.phaseIn(phase),
.accIn(acc),
.accOut(accNextOut)
);
//squareCos squareCos_u1(
//.angle(acc),
//.cosOut(outcos)
//);
//squareSin squareSin_u1(
//.angle(acc),
//.sinOut(outsin)
//);
cosIdeal cosIdeal_0(
.angle(acc),
.cosOut(outcos)
);
sinIdeal sinIdeal_0(
.angle(acc),
.sinOut(outsin)
);
endmodule |
module DEDFF(
input clk,
input rst,
input D0,
input D1,
output Q
);
parameter VSS = 1'b0;
parameter VCC = 1'b1;
reg pose_edge;
reg neg_edge;
wire Q1;
wire Q2;
assign Q1 = neg_edge ^ D0;
assign Q2 = pose_edge ^ D1;
assign Q = neg_edge ^ pose_edge;
//Pose Edge
always @(posedge clk) begin
if (rst == VSS) pose_edge <= VSS;
else pose_edge <= Q1;
end
//Neg Edge
always @(negedge clk) begin
if (rst == VSS) neg_edge <= VSS;
else neg_edge <= Q2;
end
endmodule |
module loraModulator(
input clk,
input rst,
input [`SYMBOL_PRECISION-1:0] symVal, //FORMAT IS: Tn = 257 + 2n
input [`CHIRP_TYPE_SIZE-1:0] symType, //Upchirp(00), Downchirp(01), Quarter Downchirp(10)
input [`SF_SELECT_SIZE-1:0] SF_select,
input [`BW_SELECT_SIZE-1:0] BW_select,
output [`ILength-1:0] I,
output [`QLength-1:0] Q,
output reg IQStart,
output symDone
);
reg [`SF_SIZE-1:0] SF;
reg [`SIZE_8-1:0] BW_shift_scale;
reg [`SYMBOL_PRECISION-1:0] offset;
reg [`SYMBOL_PRECISION-1:0] chirp_size;
//constant module connections
wire [`PRECISION-1:0] BW_SR;
wire [`PRECISION-1:0] phaseInc_val;
wire [`PRECISION-1:0] symbol_size;
//chirpGenerator module connections
wire signed [`PRECISION-1:0] initPhase_phaseOut;
wire [`SinSize-1:0] chirp_I;
wire [`SinSize-1:0] chirp_Q;
assign I = {chirp_I, 1'b0};
assign Q = {chirp_Q, 1'b0};
//###################################################################################################
//reg and wires assignments
always @(posedge clk) begin
if (rst == 1'b0) begin
IQStart <= 1'b0;
end else begin
IQStart <= 1'b1;
end
end
//###################################################################################################
/** Spreading factor selection**/
always @(*) begin
case (SF_select)
`SF_SELECT_12: begin
SF = `SF_12;
offset = `OFFSET_SF12;
chirp_size = `CHIRP_SIZE_SF12;
end
`SF_SELECT_11: begin
SF = `SF_11;
offset = `OFFSET_SF11;
chirp_size = `CHIRP_SIZE_SF11;
end
`SF_SELECT_10: begin
SF = `SF_10;
offset = `OFFSET_SF10;
chirp_size = `CHIRP_SIZE_SF10;
end
`SF_SELECT_9: begin
SF = `SF_9;
offset = `OFFSET_SF9;
chirp_size = `CHIRP_SIZE_SF9;
end
`SF_SELECT_8: begin
SF = `SF_8;
offset = `OFFSET_SF8;
chirp_size = `CHIRP_SIZE_SF8;
end
`SF_SELECT_7: begin
SF = `SF_7;
offset = `OFFSET_SF7;
chirp_size = `CHIRP_SIZE_SF7;
end
default: begin
SF = `SF_12;
offset = `OFFSET_SF12;
chirp_size = `CHIRP_SIZE_SF12;
end
endcase
end
//###################################################################################################
/*
* Spreading factor selection.
* This supports up to BW125k.
* For more BWs, needs to update this statement.
*/
always @(*) begin
case (BW_select)
`BW_SELECT_500: begin
BW_shift_scale = `minBW_SR_Ratio_Power - 3;
end
`BW_SELECT_250: begin
BW_shift_scale = `minBW_SR_Ratio_Power - 4;
end
`BW_SELECT_125: begin
BW_shift_scale = `minBW_SR_Ratio_Power - 5;
end
`BW_SELECT_62_5: begin
BW_shift_scale = `minBW_SR_Ratio_Power - 6;
end
`BW_SELECT_31_25: begin
BW_shift_scale = `minBW_SR_Ratio_Power - 7;
end
default: begin
BW_shift_scale = `minBW_SR_Ratio_Power - 3;
end
endcase
end
//###################################################################################################
constant constant0(
.clk(clk),
.chirp_type(symType),
.SF_select(SF_select),
.BW_shift_scale(BW_shift_scale),
.BW_SR(BW_SR),
.phaseInc_val(phaseInc_val),
.symbol_size(symbol_size)
);
initialPhase initPhase0(
.clk(clk),
.chirp_type(symType),
.symbol(symVal),
.BW_shift_scale(BW_shift_scale),
.offset(offset),
.chirp_size(chirp_size),
.SF(SF),
.BW_SR(BW_SR),
.phaseOut(initPhase_phaseOut)
)/* syn_preserve = "TRUE" */;
chirpGenerator chirpGen0(
.chirpReset(rst),
.clk(clk),
.basephase(initPhase_phaseOut),
.chirpType(symType),
.BW_SR(BW_SR),
.phaseInc_val(phaseInc_val),
.symbol_size(symbol_size),
.outcos(chirp_I),
.outsin(chirp_Q),
.done(symDone)
);
endmodule |
module clockDivider(
input clk,
input pll_lock,
output reg clkOut,
output reg clkLock
);
parameter [7:0] Freq = 4;
reg [7:0] maxWait;
always @(pll_lock) begin
maxWait = (64/Freq)/2;
end
reg [7:0] lockCounter;
reg [7:0] counter;
always @(posedge clk) begin
if (pll_lock == 1'b0) begin
counter <= 8'd0;
clkOut <= 1'b0;
lockCounter <= 8'd0;
clkLock <= 1'b0;
end else begin
counter <= counter + 8'd1;
if (counter == (maxWait-1)) begin
clkOut <= ~clkOut;
counter <= 8'd0;
end else begin
clkOut <= clkOut;
end
lockCounter <= lockCounter + 8'd1;
if (lockCounter >= 4*2*2*maxWait)
clkLock <= 1'b1;
else
clkLock <= clkLock;
end
end
endmodule |
module counter(
input clk,
input clkLock,
output reg countDone
);
reg [`WAIT_SIZE-1:0] waitcount;
always @(posedge clk) begin
if (clkLock == 1'b0) begin
countDone <= 1'b0;
waitcount <= `WAIT_SIZE'd0;
end else begin
waitcount <= (waitcount < `maxWait) ? waitcount + `WAIT_SIZE'd1 : `WAIT_SIZE'd0;
if (waitcount > `WAIT_SIZE'd50) begin
countDone <= 1'b1;
end else begin
countDone <= 1'b0;
end
end
end
endmodule |
module accInc(
input signed [`PRECISION-1:0] phaseIn,
input signed [`PRECISION-1:0] accIn,
output reg signed [`PRECISION-1:0] accOut
);
//###################################################################################################
always @(*) begin
accOut = $signed(accIn + phaseIn);
// hangle negative
if ($signed(accOut) < 0) begin
accOut = $signed(accOut + `SCALE_2X);
end
// mod(accInc,2)
if ($signed(accOut) >= $signed(`SCALE_2X)) begin
accOut = $signed(accOut - `SCALE_2X);
end
end
endmodule |
module initialPhase(
input clk,
input [`CHIRP_TYPE_SIZE-1:0] chirp_type,
input [`SYMBOL_PRECISION-1:0] symbol,
input [`SIZE_8-1:0] BW_shift_scale,
input [`SYMBOL_PRECISION-1:0] offset,
input [`SYMBOL_PRECISION-1:0] chirp_size,
input [`SF_SIZE-1:0] SF,
input [`PRECISION-1:0] BW_SR,
(* syn_preserve = "TRUE" *) output reg signed [`PRECISION-1:0] phaseOut
);
reg [`SYMBOL_PRECISION-1:0] phaseStart;
reg signed [`PRECISION-1:0] phaseOut0;
always @(*) begin
//phaseStart = $signed(symbol - offset);
//if ($signed(phaseStart) < 0) begin
//phaseStart = $signed(phaseStart + chirp_size);
//end
phaseStart = $signed(symbol);
//new version
phaseOut0 = `BW_SCALE_SR_MIN >> (SF-1-BW_shift_scale);
phaseOut0 = $signed(phaseOut0 * phaseStart);
//phaseOut0 = dir ? $signed(phaseOut0 - BW_SR) : $signed(phaseOut0 + BW_SR);
if (chirp_type == `TYPE_UPCHIRP)
phaseOut0 = $signed(phaseOut0 - BW_SR);
else
phaseOut0 = $signed(phaseOut0 + BW_SR);
end
always @(posedge clk) begin
phaseOut <= phaseOut0;
end
endmodule |
module cosIdeal(angle, cosOut);
input [`PRECISION-1:0] angle;
output reg [`SinSize-1:0] cosOut;
reg [`PRECISION-1:0] index;
always @(*) begin
index = angle >> (25-`Sine_SR_Bits);
end
always @(index) begin
if (index < 84)
cosOut = `SinSize'b0111111111111;
else if (index < 144)
cosOut = `SinSize'b0111110111111;
else if (index < 184)
cosOut = `SinSize'b0111101111111;
else if (index < 218)
cosOut = `SinSize'b0111100111111;
else if (index < 248)
cosOut = `SinSize'b0111011111111;
else if (index < 274)
cosOut = `SinSize'b0111010111111;
else if (index < 298)
cosOut = `SinSize'b0111001111111;
else if (index < 320)
cosOut = `SinSize'b0111000111111;
else if (index < 341)
cosOut = `SinSize'b0110111111111;
else if (index < 361)
cosOut = `SinSize'b0110110111111;
else if (index < 381)
cosOut = `SinSize'b0110101111111;
else if (index < 399)
cosOut = `SinSize'b0110100111111;
else if (index < 414)
cosOut = `SinSize'b0110011111111;
else if (index < 432)
cosOut = `SinSize'b0110010111111;
else if (index < 449)
cosOut = `SinSize'b0110001111111;
else if (index < 465)
cosOut = `SinSize'b0110000111111;
else if (index < 478)
cosOut = `SinSize'b0101111111111;
else if (index < 494)
cosOut = `SinSize'b0101110111111;
else if (index < 509)
cosOut = `SinSize'b0101101111111;
else if (index < 522)
cosOut = `SinSize'b0101100111111;
else if (index < 536)
cosOut = `SinSize'b0101011111111;
else if (index < 551)
cosOut = `SinSize'b0101010111111;
else if (index < 564)
cosOut = `SinSize'b0101001111111;
else if (index < 577)
cosOut = `SinSize'b0101000111111;
else if (index < 591)
cosOut = `SinSize'b0100111111111;
else if (index < 602)
cosOut = `SinSize'b0100110111111;
else if (index < 617)
cosOut = `SinSize'b0100101111111;
else if (index < 628)
cosOut = `SinSize'b0100100111111;
else if (index < 641)
cosOut = `SinSize'b0100011111111;
else if (index < 652)
cosOut = `SinSize'b0100010111111;
else if (index < 664)
cosOut = `SinSize'b0100001111111;
else if (index < 676)
cosOut = `SinSize'b0100000111111;
else if (index < 688)
cosOut = `SinSize'b0011111111111;
else if (index < 700)
cosOut = `SinSize'b0011110111111;
else if (index < 710)
cosOut = `SinSize'b0011101111111;
else if (index < 722)
cosOut = `SinSize'b0011100111111;
else if (index < 734)
cosOut = `SinSize'b0011011111111;
else if (index < 744)
cosOut = `SinSize'b0011010111111;
else if (index < 756)
cosOut = `SinSize'b0011001111111;
else if (index < 766)
cosOut = `SinSize'b0011000111111;
else if (index < 778)
cosOut = `SinSize'b0010111111111;
else if (index < 788)
cosOut = `SinSize'b0010110111111;
else if (index < 800)
cosOut = `SinSize'b0010101111111;
else if (index < 810)
cosOut = `SinSize'b0010100111111;
else if (index < 820)
cosOut = `SinSize'b0010011111111;
else if (index < 832)
cosOut = `SinSize'b0010010111111;
else if (index < 842)
cosOut = `SinSize'b0010001111111;
else if (index < 852)
cosOut = `SinSize'b0010000111111;
else if (index < 862)
cosOut = `SinSize'b0001111111111;
else if (index < 874)
cosOut = `SinSize'b0001110111111;
else if (index < 884)
cosOut = `SinSize'b0001101111111;
else if (index < 894)
cosOut = `SinSize'b0001100111111;
else if (index < 904)
cosOut = `SinSize'b0001011111111;
else if (index < 914)
cosOut = `SinSize'b0001010111111;
else if (index < 924)
cosOut = `SinSize'b0001001111111;
else if (index < 934)
cosOut = `SinSize'b0001000111111;
else if (index < 944)
cosOut = `SinSize'b0000111111111;
else if (index < 956)
cosOut = `SinSize'b0000110111111;
else if (index < 966)
cosOut = `SinSize'b0000101111111;
else if (index < 976)
cosOut = `SinSize'b0000100111111;
else if (index < 986)
cosOut = `SinSize'b0000011111111;
else if (index < 996)
cosOut = `SinSize'b0000010111111;
else if (index < 1006)
cosOut = `SinSize'b0000001111111;
else if (index < 1016)
cosOut = `SinSize'b0000000111111;
else if (index < 1036)
cosOut = `SinSize'b0000000000000;
else if (index < 1046)
cosOut = `SinSize'b1111111000001;
else if (index < 1056)
cosOut = `SinSize'b1111110000001;
else if (index < 1066)
cosOut = `SinSize'b1111101000001;
else if (index < 1076)
cosOut = `SinSize'b1111100000001;
else if (index < 1086)
cosOut = `SinSize'b1111011000001;
else if (index < 1096)
cosOut = `SinSize'b1111010000001;
else if (index < 1108)
cosOut = `SinSize'b1111001000001;
else if (index < 1118)
cosOut = `SinSize'b1111000000001;
else if (index < 1128)
cosOut = `SinSize'b1110111000001;
else if (index < 1138)
cosOut = `SinSize'b1110110000001;
else if (index < 1148)
cosOut = `SinSize'b1110101000001;
else if (index < 1158)
cosOut = `SinSize'b1110100000001;
else if (index < 1168)
cosOut = `SinSize'b1110011000001;
else if (index < 1178)
cosOut = `SinSize'b1110010000001;
else if (index < 1190)
cosOut = `SinSize'b1110001000001;
else if (index < 1200)
cosOut = `SinSize'b1110000000001;
else if (index < 1210)
cosOut = `SinSize'b1101111000001;
else if (index < 1220)
cosOut = `SinSize'b1101110000001;
else if (index < 1232)
cosOut = `SinSize'b1101101000001;
else if (index < 1242)
cosOut = `SinSize'b1101100000001;
else if (index < 1252)
cosOut = `SinSize'b1101011000001;
else if (index < 1264)
cosOut = `SinSize'b1101010000001;
else if (index < 1274)
cosOut = `SinSize'b1101001000001;
else if (index < 1286)
cosOut = `SinSize'b1101000000001;
else if (index < 1296)
cosOut = `SinSize'b1100111000001;
else if (index < 1309)
cosOut = `SinSize'b1100110000001;
else if (index < 1318)
cosOut = `SinSize'b1100101000001;
else if (index < 1331)
cosOut = `SinSize'b1100100000001;
else if (index < 1342)
cosOut = `SinSize'b1100011000001;
else if (index < 1353)
cosOut = `SinSize'b1100010000001;
else if (index < 1364)
cosOut = `SinSize'b1100001000001;
else if (index < 1377)
cosOut = `SinSize'b1100000000001;
else if (index < 1388)
cosOut = `SinSize'b1011111000001;
else if (index < 1400)
cosOut = `SinSize'b1011110000001;
else if (index < 1413)
cosOut = `SinSize'b1011101000001;
else if (index < 1424)
cosOut = `SinSize'b1011100000001;
else if (index < 1436)
cosOut = `SinSize'b1011011000001;
else if (index < 1450)
cosOut = `SinSize'b1011010000001;
else if (index < 1463)
cosOut = `SinSize'b1011001000001;
else if (index < 1477)
cosOut = `SinSize'b1011000000001;
else if (index < 1488)
cosOut = `SinSize'b1010111000001;
else if (index < 1502)
cosOut = `SinSize'b1010110000001;
else if (index < 1516)
cosOut = `SinSize'b1010101000001;
else if (index < 1530)
cosOut = `SinSize'b1010100000001;
else if (index < 1545)
cosOut = `SinSize'b1010011000001;
else if (index < 1559)
cosOut = `SinSize'b1010010000001;
else if (index < 1574)
cosOut = `SinSize'b1010001000001;
else if (index < 1589)
cosOut = `SinSize'b1010000000001;
else if (index < 1604)
cosOut = `SinSize'b1001111000001;
else if (index < 1620)
cosOut = `SinSize'b1001110000001;
else if (index < 1639)
cosOut = `SinSize'b1001101000001;
else if (index < 1655)
cosOut = `SinSize'b1001100000001;
else if (index < 1672)
cosOut = `SinSize'b1001011000001;
else if (index < 1692)
cosOut = `SinSize'b1001010000001;
else if (index < 1713)
cosOut = `SinSize'b1001001000001;
else if (index < 1733)
cosOut = `SinSize'b1001000000001;
else if (index < 1755)
cosOut = `SinSize'b1000111000001;
else if (index < 1779)
cosOut = `SinSize'b1000110000001;
else if (index < 1804)
cosOut = `SinSize'b1000101000001;
else if (index < 1834)
cosOut = `SinSize'b1000100000001;
else if (index < 1868)
cosOut = `SinSize'b1000011000001;
else if (index < 1909)
cosOut = `SinSize'b1000010000001;
else if (index < 1969)
cosOut = `SinSize'b1000001000001;
else if (index < 2132)
cosOut = `SinSize'b1000000000001;
else if (index < 2192)
cosOut = `SinSize'b1000001000001;
else if (index < 2232)
cosOut = `SinSize'b1000010000001;
else if (index < 2267)
cosOut = `SinSize'b1000011000001;
else if (index < 2297)
cosOut = `SinSize'b1000100000001;
else if (index < 2322)
cosOut = `SinSize'b1000101000001;
else if (index < 2346)
cosOut = `SinSize'b1000110000001;
else if (index < 2368)
cosOut = `SinSize'b1000111000001;
else if (index < 2388)
cosOut = `SinSize'b1001000000001;
else if (index < 2408)
cosOut = `SinSize'b1001001000001;
else if (index < 2429)
cosOut = `SinSize'b1001010000001;
else if (index < 2446)
cosOut = `SinSize'b1001011000001;
else if (index < 2462)
cosOut = `SinSize'b1001100000001;
else if (index < 2481)
cosOut = `SinSize'b1001101000001;
else if (index < 2496)
cosOut = `SinSize'b1001110000001;
else if (index < 2512)
cosOut = `SinSize'b1001111000001;
else if (index < 2526)
cosOut = `SinSize'b1010000000001;
else if (index < 2542)
cosOut = `SinSize'b1010001000001;
else if (index < 2556)
cosOut = `SinSize'b1010010000001;
else if (index < 2570)
cosOut = `SinSize'b1010011000001;
else if (index < 2584)
cosOut = `SinSize'b1010100000001;
else if (index < 2598)
cosOut = `SinSize'b1010101000001;
else if (index < 2612)
cosOut = `SinSize'b1010110000001;
else if (index < 2624)
cosOut = `SinSize'b1010111000001;
else if (index < 2638)
cosOut = `SinSize'b1011000000001;
else if (index < 2650)
cosOut = `SinSize'b1011001000001;
else if (index < 2664)
cosOut = `SinSize'b1011010000001;
else if (index < 2676)
cosOut = `SinSize'b1011011000001;
else if (index < 2688)
cosOut = `SinSize'b1011100000001;
else if (index < 2700)
cosOut = `SinSize'b1011101000001;
else if (index < 2712)
cosOut = `SinSize'b1011110000001;
else if (index < 2725)
cosOut = `SinSize'b1011111000001;
else if (index < 2736)
cosOut = `SinSize'b1100000000001;
else if (index < 2748)
cosOut = `SinSize'b1100001000001;
else if (index < 2758)
cosOut = `SinSize'b1100010000001;
else if (index < 2770)
cosOut = `SinSize'b1100011000001;
else if (index < 2782)
cosOut = `SinSize'b1100100000001;
else if (index < 2792)
cosOut = `SinSize'b1100101000001;
else if (index < 2804)
cosOut = `SinSize'b1100110000001;
else if (index < 2814)
cosOut = `SinSize'b1100111000001;
else if (index < 2826)
cosOut = `SinSize'b1101000000001;
else if (index < 2836)
cosOut = `SinSize'b1101001000001;
else if (index < 2848)
cosOut = `SinSize'b1101010000001;
else if (index < 2858)
cosOut = `SinSize'b1101011000001;
else if (index < 2868)
cosOut = `SinSize'b1101100000001;
else if (index < 2880)
cosOut = `SinSize'b1101101000001;
else if (index < 2890)
cosOut = `SinSize'b1101110000001;
else if (index < 2901)
cosOut = `SinSize'b1101111000001;
else if (index < 2910)
cosOut = `SinSize'b1110000000001;
else if (index < 2923)
cosOut = `SinSize'b1110001000001;
else if (index < 2932)
cosOut = `SinSize'b1110010000001;
else if (index < 2942)
cosOut = `SinSize'b1110011000001;
else if (index < 2952)
cosOut = `SinSize'b1110100000001;
else if (index < 2962)
cosOut = `SinSize'b1110101000001;
else if (index < 2973)
cosOut = `SinSize'b1110110000001;
else if (index < 2982)
cosOut = `SinSize'b1110111000001;
else if (index < 2992)
cosOut = `SinSize'b1111000000001;
else if (index < 3004)
cosOut = `SinSize'b1111001000001;
else if (index < 3014)
cosOut = `SinSize'b1111010000001;
else if (index < 3024)
cosOut = `SinSize'b1111011000001;
else if (index < 3034)
cosOut = `SinSize'b1111100000001;
else if (index < 3044)
cosOut = `SinSize'b1111101000001;
else if (index < 3055)
cosOut = `SinSize'b1111110000001;
else if (index < 3064)
cosOut = `SinSize'b1111111000001;
else if (index < 3084)
cosOut = `SinSize'b0000000000000;
else if (index < 3094)
cosOut = `SinSize'b0000000111111;
else if (index < 3105)
cosOut = `SinSize'b0000001111111;
else if (index < 3114)
cosOut = `SinSize'b0000010111111;
else if (index < 3124)
cosOut = `SinSize'b0000011111111;
else if (index < 3134)
cosOut = `SinSize'b0000100111111;
else if (index < 3144)
cosOut = `SinSize'b0000101111111;
else if (index < 3156)
cosOut = `SinSize'b0000110111111;
else if (index < 3166)
cosOut = `SinSize'b0000111111111;
else if (index < 3176)
cosOut = `SinSize'b0001000111111;
else if (index < 3187)
cosOut = `SinSize'b0001001111111;
else if (index < 3196)
cosOut = `SinSize'b0001010111111;
else if (index < 3206)
cosOut = `SinSize'b0001011111111;
else if (index < 3216)
cosOut = `SinSize'b0001100111111;
else if (index < 3226)
cosOut = `SinSize'b0001101111111;
else if (index < 3238)
cosOut = `SinSize'b0001110111111;
else if (index < 3248)
cosOut = `SinSize'b0001111111111;
else if (index < 3259)
cosOut = `SinSize'b0010000111111;
else if (index < 3268)
cosOut = `SinSize'b0010001111111;
else if (index < 3281)
cosOut = `SinSize'b0010010111111;
else if (index < 3290)
cosOut = `SinSize'b0010011111111;
else if (index < 3300)
cosOut = `SinSize'b0010100111111;
else if (index < 3312)
cosOut = `SinSize'b0010101111111;
else if (index < 3322)
cosOut = `SinSize'b0010110111111;
else if (index < 3334)
cosOut = `SinSize'b0010111111111;
else if (index < 3344)
cosOut = `SinSize'b0011000111111;
else if (index < 3356)
cosOut = `SinSize'b0011001111111;
else if (index < 3366)
cosOut = `SinSize'b0011010111111;
else if (index < 3378)
cosOut = `SinSize'b0011011111111;
else if (index < 3391)
cosOut = `SinSize'b0011100111111;
else if (index < 3400)
cosOut = `SinSize'b0011101111111;
else if (index < 3413)
cosOut = `SinSize'b0011110111111;
else if (index < 3424)
cosOut = `SinSize'b0011111111111;
else if (index < 3436)
cosOut = `SinSize'b0100000111111;
else if (index < 3448)
cosOut = `SinSize'b0100001111111;
else if (index < 3460)
cosOut = `SinSize'b0100010111111;
else if (index < 3472)
cosOut = `SinSize'b0100011111111;
else if (index < 3485)
cosOut = `SinSize'b0100100111111;
else if (index < 3498)
cosOut = `SinSize'b0100101111111;
else if (index < 3510)
cosOut = `SinSize'b0100110111111;
else if (index < 3524)
cosOut = `SinSize'b0100111111111;
else if (index < 3536)
cosOut = `SinSize'b0101000111111;
else if (index < 3551)
cosOut = `SinSize'b0101001111111;
else if (index < 3564)
cosOut = `SinSize'b0101010111111;
else if (index < 3578)
cosOut = `SinSize'b0101011111111;
else if (index < 3592)
cosOut = `SinSize'b0101100111111;
else if (index < 3606)
cosOut = `SinSize'b0101101111111;
else if (index < 3622)
cosOut = `SinSize'b0101110111111;
else if (index < 3636)
cosOut = `SinSize'b0101111111111;
else if (index < 3652)
cosOut = `SinSize'b0110000111111;
else if (index < 3668)
cosOut = `SinSize'b0110001111111;
else if (index < 3686)
cosOut = `SinSize'b0110010111111;
else if (index < 3702)
cosOut = `SinSize'b0110011111111;
else if (index < 3721)
cosOut = `SinSize'b0110100111111;
else if (index < 3740)
cosOut = `SinSize'b0110101111111;
else if (index < 3760)
cosOut = `SinSize'b0110110111111;
else if (index < 3780)
cosOut = `SinSize'b0110111111111;
else if (index < 3802)
cosOut = `SinSize'b0111000111111;
else if (index < 3826)
cosOut = `SinSize'b0111001111111;
else if (index < 3852)
cosOut = `SinSize'b0111010111111;
else if (index < 3882)
cosOut = `SinSize'b0111011111111;
else if (index < 3916)
cosOut = `SinSize'b0111100111111;
else if (index < 3956)
cosOut = `SinSize'b0111101111111;
else if (index < 4016)
cosOut = `SinSize'b0111110111111;
else
cosOut = `SinSize'b0111111111111;
end
endmodule |
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