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module topModule(
// Inputs
top_rst_n,
top_clk,
// Outputs
osc_en,
serial_iq,
serial_clk,
LED,
clk_test
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input top_clk;
input top_rst_n;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output osc_en;
output serial_iq /* synthesis IO_TYPES="LVDS*/;
output serial_clk /* synthesis IO_TYPES="LVDS*/;
output wire LED;
output wire clk_test;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire clockDivider_0_clkLock;
wire clockDivider_0_clk_4M;
wire pll_clko;
wire pll_lock;
wire pll_clki;
wire counter_0_countDone;
wire loraModulator_0_symDone;
wire [2:0] loraPacketGenerator_0_BW_select;
wire loraPacketGenerator_0_chirpReset;
wire [2:0] loraPacketGenerator_0_SF_select;
wire [1:0] loraPacketGenerator_0_symType;
wire [11:0] loraPacketGenerator_0_symVal;
wire loraModulator_0_IQStart;
wire [13:0] I;
wire [13:0] Q;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign osc_en = 1'b1;
assign pll_clki = top_clk;
//debugg
assign clk_test = clockDivider_0_clk_4M;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign LED = 1'b1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
my_pll_64mhz my_pll_instance (
// Inputs
.SEL (1'b1),
.CLKI (),
.CLKI2 (pll_clki),
.RST (~top_rst_n),
// Outputs
.CLKOP (pll_clko),
.LOCK (pll_lock)
);
//--------clockDivider
clockDivider clockDivider_0(
// Inputs
.clk (pll_clko),
.pll_lock (pll_lock),
// Outputs
.clkOut (clockDivider_0_clk_4M),
.clkLock (clockDivider_0_clkLock)
);
//--------counter
counter counter_0(
// Inputs
.clk (clockDivider_0_clk_4M),
.clkLock (clockDivider_0_clkLock),
// Outputs
.countDone (counter_0_countDone)
);
//--------loraPacketGenerator
loraPacketGenerator loraPacketGenerator_0(
// Inputs
.clk (clockDivider_0_clk_4M),
.clkLock (clockDivider_0_clkLock),
.rst (counter_0_countDone),
.symDone (loraModulator_0_symDone),
// Outputs
.chirpReset (loraPacketGenerator_0_chirpReset),
.SF_select (loraPacketGenerator_0_SF_select),
.BW_select (loraPacketGenerator_0_BW_select),
.symVal (loraPacketGenerator_0_symVal),
.symType (loraPacketGenerator_0_symType)
);
//--------loraModulator
loraModulator loraModulator_0(
// Inputs
.clk (clockDivider_0_clk_4M),
.rst (loraPacketGenerator_0_chirpReset),
.symVal (loraPacketGenerator_0_symVal),
.symType (loraPacketGenerator_0_symType),
.SF_select (loraPacketGenerator_0_SF_select),
.BW_select (loraPacketGenerator_0_BW_select),
// Outputs
.IQStart (loraModulator_0_IQStart),
.symDone (loraModulator_0_symDone),
.I (I),
.Q (Q)
);
//--------IQSerializer
IQSerializer IQSerializer_0(
// Inputs
.clk (pll_clko),
.start (loraModulator_0_IQStart),
.I (I),
.Q (Q),
// Outputs
.serial_N (serial_iq),
.serial ( ),
.serial_clk (serial_clk)
);
endmodule |
module loraPacketGenerator(
input clk,
input clkLock,
input rst,
input symDone,
output reg [`SF_SELECT_SIZE-1:0] SF_select,
output reg [`BW_SELECT_SIZE-1:0] BW_select,
(* syn_preserve = "TRUE" *) output reg [`SYMBOL_PRECISION-1:0] symVal,
output reg [`CHIRP_TYPE_SIZE-1:0] symType,
output reg chirpReset
);
//Counters
reg [`DATA_PRECISION-1:0] preambleCounter;
reg [`DATA_PRECISION-1:0] payloadCounter;
//symbol type and value
reg [`SYMBOL_PRECISION-1:0] next_symVal;
reg [`CHIRP_TYPE_SIZE-1:0] next_symType;
/*** States ***/
parameter [`STATE_SIZE-1:0] STATE_PREAMBLE = `STATE_SIZE'd0, STATE_SYNC_0 = `STATE_SIZE'd1, STATE_SYNC_1 = `STATE_SIZE'd2,
STATE_DOWNCHIRP_0 = `STATE_SIZE'd3, STATE_DOWNCHIRP_1 = `STATE_SIZE'd4, STATE_QDOWNCHIRP = `STATE_SIZE'd5, STATE_PAYLOAD = `STATE_SIZE'd6,
STATE_DONE = `STATE_SIZE'd7, STATE_CONST0 = `STATE_SIZE'd8, STATE_CONST1 = `STATE_SIZE'd9;
reg [`STATE_SIZE-1:0] current_state;
reg [`STATE_SIZE-1:0] next_state;
//TopModule Regs and Wires
//peamble, downchip and payload
reg [`SYMBOL_PRECISION-1:0] preambleSym;
reg [`SYMBOL_PRECISION-1:0] downSym;
reg [`DATA_PRECISION-1:0] payloadSize;
reg [`DATA_PRECISION-1:0] preambleSize;
reg [`SYMBOL_PRECISION-1:0] symbols [17:0];
//parameters
parameter VSS = 1'b0;
parameter VCC = 1'b1;
//########################################################################################
/*** Assign BW and SF ***/
always @(posedge clk) begin
SF_select = `SF_SELECT_8;
BW_select = `BW_SELECT_250;
end
/*
* Assign preambe and payload size
*/
always @(posedge clk) begin
preambleSize = `DATA_PRECISION'd8;
payloadSize = `DATA_PRECISION'd16;
end
/*
* Assign preambe and downchirp
*/
always @(SF_select) begin
//preambleSym = (1 << (12 - SF_select - 1)) + 1;
//downSym = (1 << (12 - SF_select - 1)) + 1;
//new version, corrected
preambleSym = `SYMBOL_PRECISION'd0;
case (SF_select)
`SF_SELECT_12: begin
//wrong
downSym = `SYMBOL_PRECISION'd4079;
end
`SF_SELECT_11: begin
//wrong
downSym = `SYMBOL_PRECISION'd4079;
end
`SF_SELECT_10: begin
//wrong
downSym = `SYMBOL_PRECISION'd4079;
end
`SF_SELECT_9: begin
//wrong
downSym = `SYMBOL_PRECISION'd4079;
end
`SF_SELECT_8: begin
downSym = `SYMBOL_PRECISION'd254;
end
`SF_SELECT_7: begin
//wrong
downSym = `SYMBOL_PRECISION'd4079;
end
default: begin
downSym = `SYMBOL_PRECISION'd4079;
end
endcase
end
/*** Update State ***/
always @(posedge clk) begin
current_state <= next_state;
symVal <= next_symVal;
symType <= next_symType;
end
/*** Preamble Counter and payload counter***/
always @(posedge clk) begin
if (clkLock == VCC) begin
if (rst == VSS) begin
preambleCounter <= `DATA_PRECISION'd0;
payloadCounter <= `DATA_PRECISION'd0;
end else begin
if (symDone) begin
if (current_state == STATE_PREAMBLE) begin
preambleCounter <= preambleCounter + `DATA_PRECISION'd1;
end else begin
preambleCounter <= `DATA_PRECISION'd0;
end
if (current_state == STATE_PAYLOAD) begin
payloadCounter <= payloadCounter + `DATA_PRECISION'd1;
end else begin
payloadCounter <= `DATA_PRECISION'd0;
end
end else begin
preambleCounter <= preambleCounter;
payloadCounter <= payloadCounter;
end
end
end
end
/**
* symbol selection
*/
always @(SF_select) begin
case (SF_select)
`SF_SELECT_12: begin
////sync symbols
//symbols[0] = `SYMBOL_PRECISION'd2057;
//symbols[1] = `SYMBOL_PRECISION'd2065;
////payload symbols
//symbols[2] = `SYMBOL_PRECISION'd2555;
//symbols[3] = `SYMBOL_PRECISION'd2635;
//symbols[4] = `SYMBOL_PRECISION'd399;
//symbols[5] = `SYMBOL_PRECISION'd1003;
//symbols[6] = `SYMBOL_PRECISION'd55;
//symbols[7] = `SYMBOL_PRECISION'd2543;
//symbols[8] = `SYMBOL_PRECISION'd3051;
//symbols[9] = `SYMBOL_PRECISION'd3279;
//
//symbols[10] = `SYMBOL_PRECISION'd0;
//symbols[11] = `SYMBOL_PRECISION'd0;
//symbols[12] = `SYMBOL_PRECISION'd0;
//symbols[13] = `SYMBOL_PRECISION'd0;
//symbols[14] = `SYMBOL_PRECISION'd0;
//symbols[15] = `SYMBOL_PRECISION'd0;
//symbols[16] = `SYMBOL_PRECISION'd0;
//symbols[17] = `SYMBOL_PRECISION'd0;
//new version, not correct
//sync symbols
symbols[0] = `SYMBOL_PRECISION'd8;
symbols[1] = `SYMBOL_PRECISION'd16;
//payload symbols
symbols[2] = `SYMBOL_PRECISION'd488;
symbols[3] = `SYMBOL_PRECISION'd568;
symbols[4] = `SYMBOL_PRECISION'd2427;
symbols[5] = `SYMBOL_PRECISION'd3032;
symbols[6] = `SYMBOL_PRECISION'd2083;
symbols[7] = `SYMBOL_PRECISION'd476;
symbols[8] = `SYMBOL_PRECISION'd984;
symbols[9] = `SYMBOL_PRECISION'd1211;
symbols[10] = `SYMBOL_PRECISION'd0;
symbols[11] = `SYMBOL_PRECISION'd0;
symbols[12] = `SYMBOL_PRECISION'd0;
symbols[13] = `SYMBOL_PRECISION'd0;
symbols[14] = `SYMBOL_PRECISION'd0;
symbols[15] = `SYMBOL_PRECISION'd0;
symbols[16] = `SYMBOL_PRECISION'd0;
symbols[17] = `SYMBOL_PRECISION'd0;
end
`SF_SELECT_11: begin
//sync symbols
symbols[0] = `SYMBOL_PRECISION'd1033;
symbols[1] = `SYMBOL_PRECISION'd1041;
//payload symbols
symbols[2] = `SYMBOL_PRECISION'd1530;
symbols[3] = `SYMBOL_PRECISION'd1610;
symbols[4] = `SYMBOL_PRECISION'd398;
symbols[5] = `SYMBOL_PRECISION'd490;
symbols[6] = `SYMBOL_PRECISION'd54;
symbols[7] = `SYMBOL_PRECISION'd1262;
symbols[8] = `SYMBOL_PRECISION'd1514;
symbols[9] = `SYMBOL_PRECISION'd1646;
symbols[10] = `SYMBOL_PRECISION'd578;
symbols[11] = `SYMBOL_PRECISION'd1207;
symbols[12] = `SYMBOL_PRECISION'd543;
symbols[13] = `SYMBOL_PRECISION'd153;
symbols[14] = `SYMBOL_PRECISION'd1036;
symbols[15] = `SYMBOL_PRECISION'd751;
symbols[16] = `SYMBOL_PRECISION'd1552;
symbols[17] = `SYMBOL_PRECISION'd780;
end
`SF_SELECT_10: begin
//sync symbols
symbols[0] = `SYMBOL_PRECISION'd521;
symbols[1] = `SYMBOL_PRECISION'd529;
//payload symbols
symbols[2] = `SYMBOL_PRECISION'd1019;
symbols[3] = `SYMBOL_PRECISION'd951;
symbols[4] = `SYMBOL_PRECISION'd115;
symbols[5] = `SYMBOL_PRECISION'd234;
symbols[6] = `SYMBOL_PRECISION'd55;
symbols[7] = `SYMBOL_PRECISION'd622;
symbols[8] = `SYMBOL_PRECISION'd757;
symbols[9] = `SYMBOL_PRECISION'd819;
symbols[10] = `SYMBOL_PRECISION'd385;
symbols[11] = `SYMBOL_PRECISION'd149;
symbols[12] = `SYMBOL_PRECISION'd966;
symbols[13] = `SYMBOL_PRECISION'd467;
symbols[14] = `SYMBOL_PRECISION'd534;
symbols[15] = `SYMBOL_PRECISION'd795;
symbols[16] = `SYMBOL_PRECISION'd29;
symbols[17] = `SYMBOL_PRECISION'd758;
end
`SF_SELECT_9: begin
//sync symbols
symbols[0] = `SYMBOL_PRECISION'd265;
symbols[1] = `SYMBOL_PRECISION'd273;
//payload symbols
symbols[2] = `SYMBOL_PRECISION'd250;
symbols[3] = `SYMBOL_PRECISION'd330;
symbols[4] = `SYMBOL_PRECISION'd114;
symbols[5] = `SYMBOL_PRECISION'd106;
symbols[6] = `SYMBOL_PRECISION'd11;
symbols[7] = `SYMBOL_PRECISION'd306;
symbols[8] = `SYMBOL_PRECISION'd378;
symbols[9] = `SYMBOL_PRECISION'd411;
symbols[10] = `SYMBOL_PRECISION'd3;
symbols[11] = `SYMBOL_PRECISION'd44;
symbols[12] = `SYMBOL_PRECISION'd141;
symbols[13] = `SYMBOL_PRECISION'd292;
symbols[14] = `SYMBOL_PRECISION'd298;
symbols[15] = `SYMBOL_PRECISION'd23;
symbols[16] = `SYMBOL_PRECISION'd235;
symbols[17] = `SYMBOL_PRECISION'd502;
end
`SF_SELECT_8: begin
////sync symbols
//symbols[0] = `SYMBOL_PRECISION'd137;
//symbols[1] = `SYMBOL_PRECISION'd145;
////payload symbols
//symbols[2] = `SYMBOL_PRECISION'd134;
//symbols[3] = `SYMBOL_PRECISION'd202;
//symbols[4] = `SYMBOL_PRECISION'd13;
//symbols[5] = `SYMBOL_PRECISION'd41;
//symbols[6] = `SYMBOL_PRECISION'd9;
//symbols[7] = `SYMBOL_PRECISION'd158;
//symbols[8] = `SYMBOL_PRECISION'd190;
//symbols[9] = `SYMBOL_PRECISION'd50;
//symbols[10] = `SYMBOL_PRECISION'd131;
//symbols[11] = `SYMBOL_PRECISION'd211;
//symbols[12] = `SYMBOL_PRECISION'd234;
//symbols[13] = `SYMBOL_PRECISION'd134;
//symbols[14] = `SYMBOL_PRECISION'd178;
//symbols[15] = `SYMBOL_PRECISION'd107;
//symbols[16] = `SYMBOL_PRECISION'd151;
//symbols[17] = `SYMBOL_PRECISION'd114;
//new version, corrected
//sync symbols
symbols[0] = `SYMBOL_PRECISION'd8;
symbols[1] = `SYMBOL_PRECISION'd16;
//payload symbols
symbols[2] = `SYMBOL_PRECISION'd5;
symbols[3] = `SYMBOL_PRECISION'd73;
symbols[4] = `SYMBOL_PRECISION'd141;
symbols[5] = `SYMBOL_PRECISION'd169;
symbols[6] = `SYMBOL_PRECISION'd137;
symbols[7] = `SYMBOL_PRECISION'd29;
symbols[8] = `SYMBOL_PRECISION'd61;
symbols[9] = `SYMBOL_PRECISION'd177;
symbols[10] = `SYMBOL_PRECISION'd2;
symbols[11] = `SYMBOL_PRECISION'd83;
symbols[12] = `SYMBOL_PRECISION'd106;
symbols[13] = `SYMBOL_PRECISION'd5;
symbols[14] = `SYMBOL_PRECISION'd49;
symbols[15] = `SYMBOL_PRECISION'd234;
symbols[16] = `SYMBOL_PRECISION'd22;
symbols[17] = `SYMBOL_PRECISION'd241;
end
`SF_SELECT_7: begin
//sync symbols
symbols[0] = `SYMBOL_PRECISION'd73;
symbols[1] = `SYMBOL_PRECISION'd81;
//payload symbols
symbols[2] = `SYMBOL_PRECISION'd70;
symbols[3] = `SYMBOL_PRECISION'd117;
symbols[4] = `SYMBOL_PRECISION'd13;
symbols[5] = `SYMBOL_PRECISION'd21;
symbols[6] = `SYMBOL_PRECISION'd5;
symbols[7] = `SYMBOL_PRECISION'd78;
symbols[8] = `SYMBOL_PRECISION'd94;
symbols[9] = `SYMBOL_PRECISION'd101;
symbols[10] = `SYMBOL_PRECISION'd69;
symbols[11] = `SYMBOL_PRECISION'd28;
symbols[12] = `SYMBOL_PRECISION'd46;
symbols[13] = `SYMBOL_PRECISION'd89;
symbols[14] = `SYMBOL_PRECISION'd113;
symbols[15] = `SYMBOL_PRECISION'd84;
symbols[16] = `SYMBOL_PRECISION'd89;
symbols[17] = `SYMBOL_PRECISION'd80;
end
default: begin
//sync symbols
symbols[0] = `SYMBOL_PRECISION'd2057;
symbols[1] = `SYMBOL_PRECISION'd2065;
//payload symbols
symbols[2] = `SYMBOL_PRECISION'd2555;
symbols[3] = `SYMBOL_PRECISION'd2635;
symbols[4] = `SYMBOL_PRECISION'd399;
symbols[5] = `SYMBOL_PRECISION'd1003;
symbols[6] = `SYMBOL_PRECISION'd55;
symbols[7] = `SYMBOL_PRECISION'd2543;
symbols[8] = `SYMBOL_PRECISION'd3051;
symbols[9] = `SYMBOL_PRECISION'd3279;
symbols[10] = `SYMBOL_PRECISION'd0;
symbols[11] = `SYMBOL_PRECISION'd0;
symbols[12] = `SYMBOL_PRECISION'd0;
symbols[13] = `SYMBOL_PRECISION'd0;
symbols[14] = `SYMBOL_PRECISION'd0;
symbols[15] = `SYMBOL_PRECISION'd0;
symbols[16] = `SYMBOL_PRECISION'd0;
symbols[17] = `SYMBOL_PRECISION'd0;
end
endcase
end
/*** State Machine ***/
always @(*) begin
if (clkLock == VCC) begin
if (rst == VSS) begin
chirpReset = VSS;
next_symVal = preambleSym;
next_symType = `TYPE_UPCHIRP;
next_state = STATE_PREAMBLE;
end else begin
next_symVal = next_symVal;
case(current_state)
STATE_CONST0: begin
chirpReset = VSS;
next_state = STATE_CONST1;
next_symVal = preambleSym;
next_symType = `TYPE_UPCHIRP;
end
STATE_CONST1: begin
chirpReset = VSS;
next_state = STATE_PREAMBLE;
next_symVal = preambleSym;
next_symType = `TYPE_UPCHIRP;
end
STATE_PREAMBLE: begin
chirpReset = VCC;
if (preambleCounter < preambleSize-`DATA_PRECISION'd1) begin
next_symVal = preambleSym;
end else begin
next_symVal = symbols[0];
end
if (symDone) begin
if (preambleCounter < preambleSize-`DATA_PRECISION'd1) begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_PREAMBLE;
end else begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_SYNC_0;
end
end else begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_PREAMBLE;
end
end
STATE_SYNC_0: begin
chirpReset = VCC;
next_symVal = symbols[1];
if (symDone) begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_SYNC_1;
end else begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_SYNC_0;
end
end
STATE_SYNC_1: begin
chirpReset = VCC;
next_symVal = downSym;
if (symDone) begin
next_symType = `TYPE_DOWNCHIRP;
next_state = STATE_DOWNCHIRP_0;
end else begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_SYNC_1;
end
end
STATE_DOWNCHIRP_0: begin
chirpReset = VCC;
next_symVal = downSym;
if (symDone) begin
next_symType = `TYPE_DOWNCHIRP;
next_state = STATE_DOWNCHIRP_1;
end else begin
next_symType = `TYPE_DOWNCHIRP;
next_state = STATE_DOWNCHIRP_0;
end
end
STATE_DOWNCHIRP_1: begin
chirpReset = VCC;
next_symVal = downSym;
if (symDone) begin
next_symType = `TYPE_Q_DOWNCHIRP;
next_state = STATE_QDOWNCHIRP;
end else begin
next_symType = `TYPE_DOWNCHIRP;
next_state = STATE_DOWNCHIRP_1;
end
end
STATE_QDOWNCHIRP: begin
chirpReset = VCC;
next_symVal = symbols[2];
if (symDone) begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_PAYLOAD;
end else begin
next_symType = `TYPE_Q_DOWNCHIRP;
next_state = STATE_QDOWNCHIRP;
end
end
STATE_PAYLOAD: begin
chirpReset = VCC;
if (payloadCounter < payloadSize-`DATA_PRECISION'd1) begin
//constant offset because of sync symbols
next_symVal = symbols[payloadCounter + `DATA_PRECISION'd3];
end else begin
next_symVal = preambleSym;
end
if (symDone) begin
if (payloadCounter < payloadSize-`DATA_PRECISION'd1) begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_PAYLOAD;
end else begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_DONE;
end
end else begin
next_symType = `TYPE_UPCHIRP;
next_state = STATE_PAYLOAD;
end
end
STATE_DONE: begin
next_symVal = preambleSym;
chirpReset = VSS;
next_symType = `TYPE_UPCHIRP;
next_state = STATE_DONE;
end
default: begin
next_symVal = preambleSym;
chirpReset = VSS;
next_symType = `TYPE_UPCHIRP;
next_state = STATE_CONST0;
end
endcase
end
end else begin
chirpReset = VSS;
next_symVal = preambleSym;
next_symType = `TYPE_UPCHIRP;
next_state = STATE_PREAMBLE;
end
end
endmodule |
module constant(
input clk,
input [`CHIRP_TYPE_SIZE-1:0] chirp_type,
input [`SF_SELECT_SIZE-1:0] SF_select,
input [`SIZE_8-1:0] BW_shift_scale,
(* syn_preserve = "TRUE" *) output reg [`PRECISION-1:0] BW_SR,
(* syn_preserve = "TRUE" *) output reg [`PRECISION-1:0] phaseInc_val,
(* syn_preserve = "TRUE" *) output reg [`PRECISION-1:0] symbol_size
);
reg [`SF_SIZE-1:0] SF;
reg [`PRECISION-1:0] phaseInc_val0;
reg [`PRECISION-1:0] symbol_size0;
always @(*) begin
case (SF_select)
`SF_SELECT_12: begin
SF = `SF_12;
end
`SF_SELECT_11: begin
SF = `SF_11;
end
`SF_SELECT_10: begin
SF = `SF_10;
end
`SF_SELECT_9: begin
SF = `SF_9;
end
`SF_SELECT_8: begin
SF = `SF_8;
end
`SF_SELECT_7: begin
SF = `SF_7;
end
`SF_SELECT_6: begin
SF = `SF_6;
end
default: begin
SF = `SF_12;
end
endcase
end
always @(*) begin
phaseInc_val0 = (`BW2_SCALE_SR2_MIN << (2*BW_shift_scale + 1));
phaseInc_val0 = (phaseInc_val0 >> SF);
end
always @(*) begin
symbol_size0 = (1 << (`minBW_SR_Ratio_Power - BW_shift_scale));
symbol_size0 = (symbol_size0 << SF);
////commented this line, since SR is not 12M.
//symbol_size0 = symbol_size0 * 3;
if (chirp_type == `TYPE_Q_DOWNCHIRP)
symbol_size0 = symbol_size0 >> 2;
end
always @(posedge clk) begin
BW_SR <= (`BW_SCALE_SR_MIN << BW_shift_scale);
phaseInc_val <= phaseInc_val0;
symbol_size <= symbol_size0;
end
endmodule |
module phaseInc(
input signed [`PRECISION-1:0] phaseIn,
input [`CHIRP_TYPE_SIZE-1:0] chirpType,
input [`PRECISION-1:0] BW_SR,
input [`PRECISION-1:0] phaseInc_val,
output reg signed [`PRECISION-1:0] phaseOut
);
reg [`PRECISION-1:0] BW_SR_2x;
always @(*) begin
BW_SR_2x = $signed(BW_SR << 1);
//if (chirpType == `TYPE_UPCHIRP) begin
//phaseOut = $signed(phaseIn + phaseInc_val);
//
//////clip chirp symbol at sampling rate
//if ($signed(phaseOut) > $signed(BW_SR)) begin
//phaseOut = $signed(phaseOut - BW_SR_2x);
//end
//end else begin
//phaseOut = $signed(phaseIn - phaseInc_val);
//////clip chirp symbol at bandwidth
//if ($signed(phaseOut) < $signed(-1*BW_SR)) begin
//phaseOut = $signed(phaseOut + BW_SR_2x);
//end else if ($signed(phaseOut) > $signed(BW_SR)) begin
//phaseOut = $signed(phaseOut - BW_SR_2x);
//end
//end
//new version
if (chirpType == `TYPE_UPCHIRP) begin
phaseOut = $signed(phaseIn + phaseInc_val);
end else begin
phaseOut = $signed(phaseIn - phaseInc_val);
end
////clip chirp symbol at sampling rate
if ($signed(phaseOut) > $signed(BW_SR)) begin
phaseOut = $signed(phaseOut - BW_SR_2x);
end else if ($signed(phaseOut) < $signed(-1*BW_SR)) begin
phaseOut = $signed(phaseOut + BW_SR_2x);
end
end
endmodule |
module register8(input clk, input [7:0] D, input EI, output reg [7:0] Q);
wire CLK;
assign CLK=(clk & EI);
always @(posedge CLK)
begin
Q <= D;
end
endmodule |
module ALU(input op, input [7:0] A, input [7:0] B, output [8:0] res);
assign res[8:0] = op ? (A[7:0] - B[7:0]) : (A[7:0] + B[7:0]);
endmodule |
module CPU(input clkin, output [7:0] OutPut, output [6:0] LED1, output [6:0] LED2);
wire [7:0] bus;
wire [3:0] MemAddr;
wire [7:0] Aout;
wire [7:0] Bout;
wire [7:0] Instout;
wire [3:0] Pcount;
wire [3:0] Addr_in;
wire [7:0] Dispout;
wire [7:0] aluOut;
wire HLT, MI, RI, RO, IO, II, AI, AO, SO, SU, BI, OI, CE, CO, J;
wire PCrst, flag;
assign clk = (clkin & ~HLT);
register8 A(.clk(clk), .D(bus), .Q(Aout), .EI(AI));
tristateBuff triA(.data(Aout), .dataOut(bus), .enable(AO));
register8 B(.clk(clk), .D(bus), .Q(Bout), .EI(BI));
register8 InstReg(.clk(clk), .D(bus), .Q(Instout), .EI(II));
triBuff4 triInstReg(.data(Instout[3:0]), .dataOut(bus[3:0]), .enable(IO));
ALU alu(.A(Aout), .B(Bout), .op(SU), .res({flag,aluOut}));
tristateBuff tri_alu(.data(aluOut), .enable(SO), .dataOut(bus));
PC pc(.clk(clk), .rst(1'b0), .enable(CE), .jmp(J), .jmploc(bus[3:0]), .count(Pcount));
triBuff4 tripc(.data(Pcount), .dataOut(bus[3:0]), .enable(CO));
register4 MemAdd(.clk(clk), .D(bus[3:0]), .Q(Addr_in), .EI(MI));
RAM ram(.clk(~clk), .address(Addr_in), .write_enable(RI), .read_enable(RO), .data(bus));
IC ic(.clk(clk), .enable(1'b1), .Instruction(Instout[7:4]), .ctrl_wrd({HLT, MI, RI, RO, IO, II, AI, AO, SO, SU, BI, OI, CE, CO, J}));
register8 O(.clk(clk), .D(bus), .Q(OutPut), .EI(OI));
bcd2sevenseg seg0(.bcd(OutPut[3:0]), .seg(LED1));
bcd2sevenseg seg1(.bcd(OutPut[7:4]), .seg(LED2));
endmodule |
module CPUtb();
reg clk;
wire [7:0] outPut;
wire [6:0] LED1;
wire [6:0] LED2;
initial begin
clk <= 0;
forever begin
#10;
clk <= ~clk;
end
end
CPU cpu(.clkin(clk), .OutPut(outPut), .LED1(LED1), .LED2(LED2));
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, CPUtb);
#1000;
$finish;
end
endmodule |
module register4(input clk, input [3:0] D, input EI, output reg [3:0] Q);
wire CLK;
assign CLK=(clk & EI);
always @(posedge CLK)
begin
Q <= D;
end
endmodule |
module RAM(input clk, input [3:0] address, input write_enable, input read_enable, inout [7:0] data);
reg [7:0] Memory[15:0];
reg [7:0] buffer;
initial begin
Memory[0] <= 8'b0001_1010;
Memory[1] <= 8'b0010_1011;
Memory[2] <= 8'b0100_0101;
Memory[3] <= 8'b0011_1100;
Memory[4] <= 8'b0010_1101;
Memory[5] <= 8'b1110_0000;
Memory[6] <= 8'b0001_1110;
Memory[7] <= 8'b0010_1111;
Memory[8] <= 8'b1110_0000;
Memory[9] <= 8'b1111_0000;
Memory[10] <= 8'b0000_0011;
Memory[11] <= 8'b0000_0010;
Memory[12] <= 8'b0000_0001;
Memory[13] <= 8'b0000_0101;
Memory[14] <= 8'b0000_1010;
Memory[15] <= 8'b0000_1011;
end
always @(posedge clk)
begin
if(write_enable & ~read_enable)
begin
Memory[address] <= data;
end
else
begin
buffer <= Memory[address];
end
end
assign data = (read_enable & ~write_enable) ? buffer : 8'bzzzzzzzz;
endmodule |
module tristateBuff(input [7:0] data, input enable, output [7:0] dataOut);
assign dataOut = enable ? data : 8'bzzzzzzzz;
endmodule |
module triBuff4(input [3:0] data, input enable, output [3:0] dataOut);
assign dataOut = enable ? data : 4'bzzzz;
endmodule |
module bcd2sevenseg(
input [3:0] bcd,
output reg [6:0] seg
);
always @(bcd)
begin
case (bcd)
0 : seg <= 7'b1111110;
1 : seg <= 7'b0110000;
2 : seg <= 7'b1101101;
3 : seg <= 7'b1111001;
4 : seg <= 7'b0110011;
5 : seg <= 7'b1011011;
6 : seg <= 7'b1011111;
7 : seg <= 7'b1110000;
8 : seg <= 7'b1111111;
9 : seg <= 7'b1111011;
10 : seg <= 7'b1110111;
11 : seg <= 7'b0011111;
12 : seg <= 7'b1001110;
13 : seg <= 7'b0111101;
14 : seg <= 7'b1001111;
15 : seg <= 7'b1000111;
default : seg <= 7'b0000000;
endcase
end
endmodule |
module PC(input clk, input rst, input enable, input [3:0] jmploc, input jmp, output reg [3:0] count);
wire CLK;
assign CLK = (clk & enable);
initial begin
count <= 4'b0000;
end
always @(posedge CLK)
begin
if(rst)
begin
count <= 4'b0000;
end
else
begin
count <= count + 1;
end
end
always @(posedge clk)
begin
if(jmp)
begin
count <= jmploc;
end
end
endmodule |
module IC(input clk, input enable, input [3:0] Instruction, output reg [14:0] ctrl_wrd);
wire CLK;
//reg [3:0] Instruction;
assign CLK = (~clk & enable);
reg [2:0] Inst_count;
reg reset_in;
initial begin
Inst_count <= 3'b111;
reset_in <= 1'b0;
end
always @ (posedge CLK)
begin
Inst_count <= reset_in ? 3'b000 : Inst_count+1;
reset_in <= 1'b0;
case(Inst_count)//HLT, MI, RI, RO, IO, II, AI, AO, SO, SU, BI, OI, CE, CO, J;
3'b000: ctrl_wrd <= 15'b010000000000010;
3'b001: ctrl_wrd <= 15'b000101000000100;
3'b010: begin
case(Instruction)
4'b0001: ctrl_wrd <= 15'b010010000000000; // LDA
4'b0010: ctrl_wrd <= 15'b010010000000000; //ADD
4'b0011: ctrl_wrd <= 15'b010010000000000; //SUBT
4'b1110: ctrl_wrd <= 15'b000000010001000; // OUT
4'b0100: ctrl_wrd <= 15'b000010000000001; // JMP
4'b1111: ctrl_wrd <= 15'b100000000000000; // HLT
default: ctrl_wrd <= 15'b000000000000000;
endcase
end
3'b011: begin
case(Instruction)
4'b0001: ctrl_wrd <= 15'b000100100000000; // LDA
4'b0010: ctrl_wrd <= 15'b000100000010000; //ADD
4'b0011: ctrl_wrd <= 15'b000100000010000; //SUBT
4'b1110: ctrl_wrd <= 15'b000000000000000; // OUT
4'b0100: ctrl_wrd <= 15'b000000000000000; // JMP
4'b1111: ctrl_wrd <= 15'b000000000000000; // HLT
default: ctrl_wrd <= 15'b000000000000000;
endcase
end
3'b100: begin
case(Instruction)
4'b0001: ctrl_wrd <= 15'b000000000000000; // LDA done
4'b0010: ctrl_wrd <= 15'b000000101000000; //ADD
4'b0011: ctrl_wrd <= 15'b000000101100000; //SUBT
4'b1110: ctrl_wrd <= 15'b000000000000000; // OUT
4'b0100: ctrl_wrd <= 15'b000000000000000; // JMP
4'b1111: ctrl_wrd <= 15'b000000000000000; // HLT
default: ctrl_wrd <= 15'b000000000000000;
endcase
reset_in <= 1'b1; // Have some doubt here..... Maybe this part can go wrong .....
end
default: ctrl_wrd <= 15'b000000000000000;
endcase
end
endmodule |
module dff #(
parameter gp_data_width = 8 // Set input & output bit-width
)
(
input wire i_rst_an, // Asynchronous active low reset
input wire i_ena, // Synchronous active high enable
input wire i_clk, // Rising-edge clock
input wire [gp_data_width-1:0] i_data, // Input data with gp_data_width bits MSB:LSB, signed or unsigned
output wire [gp_data_width-1:0] o_data // Output data with gp_data_width bits MSB:LSB, signed or unsigned
);
// -------------------------------------------------------------------
reg [gp_data_width-1:0] r_data;
// -------------------------------------------------------------------
always @(posedge i_clk or negedge i_rst_an)
begin: p_dff
if (!i_rst_an)
r_data <= 'd0;
else if (i_ena)
r_data <= i_data;
end
assign o_data = r_data;
endmodule |
module commutator #(
parameter gp_ccw = 1, // Select: Counter Clock Wise | Clock Wise
parameter gp_idata_width = 26, // Set input data width
parameter gp_interpolation_factor = 32 // Set number of output channels
)
(
input wire i_rst_an, // Asynchronous active low reset
input wire i_ena, // Synchronous active high enable
input wire i_clk, // Rising-edge clock
input wire signed [gp_interpolation_factor*gp_idata_width-1:0] i_data, // Input data with gp_idata_width bits MSB:LSB, signed
output wire signed [gp_idata_width-1:0] o_data, // Unsigned data with gp_interpolation_factor x gp_idata_width width MSB:LSB
output wire o_clk // Slow clock pulsed output
);
// -------------------------------------------------------------------
// CONSTANT DECLARATION
localparam c_cnt_width = gp_interpolation_factor;
localparam c_idx_width = $clog2(gp_interpolation_factor)+1;
// REGISTER DECLARATION
reg [c_cnt_width-1:0] r_ring_cnt;
reg [c_idx_width-1:0] r_idx;
reg r_done;
// WIRE DECLARATION
wire signed [gp_interpolation_factor*gp_idata_width-1:0] w_data;
wire w_done;
genvar x;
// -------------------------------------------------------------------
generate
/**************/
/* Clock Wise */
/**************/
if (!gp_ccw)
begin: g_commutator_cw
// Ring counter clock-wise direction
always @(posedge i_clk or negedge i_rst_an)
begin: p_ring_counter_cw
if (!i_rst_an)
begin
r_ring_cnt <= 'd0;
r_idx <= {c_idx_width{1'b1}};
r_done <= 1'b0;
end
else if (i_ena)
begin
if (r_ring_cnt == 'd0)
begin
r_ring_cnt[c_cnt_width-1] <= 1'b1;
end
else
begin
r_ring_cnt[c_cnt_width-1] <= r_ring_cnt[0];
r_ring_cnt[c_cnt_width-2:0] <= r_ring_cnt[c_cnt_width-1:1];
end
if (r_idx < gp_interpolation_factor-1)
r_idx <= r_idx+1'b1;
else
r_idx <= 'd0;
r_done <= w_done;
end
end//ALWAYS
// Capture input data in clock-wise order MSB->LSB
for (x=gp_interpolation_factor; x>0; x=x-1)
begin: g_reg_comm_inp
dff #(
.gp_data_width (gp_idata_width)
) REG_COMMUTATOR_INP_DATA (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (r_ring_cnt[x-1]),
.i_data (i_data[x*gp_idata_width-1 -: gp_idata_width]),
.o_data (w_data[x*gp_idata_width-1 -: gp_idata_width])
);
end
assign o_data = w_data[(gp_interpolation_factor-r_idx)*gp_idata_width-1 -: gp_idata_width];
assign w_done = (r_ring_cnt[0]) ? 1'b1 : 1'b0;
end//IF_GEN
/**********************/
/* Counter Clock Wise */
/**********************/
else
begin: g_commutator_ccw
always @(negedge i_clk or negedge i_rst_an)
begin: p_ring_counter_ccw
if (!i_rst_an)
begin
r_ring_cnt <= 'd0;
r_idx <= {c_idx_width{1'b1}};
r_done <= 1'b0;
end
else if (i_ena)
begin
if (r_ring_cnt == 'd0)
begin
r_ring_cnt[0] <= 1'b1;
end
else
begin
r_ring_cnt[0] <= r_ring_cnt[c_cnt_width-1];
r_ring_cnt[c_cnt_width-1:1] <= r_ring_cnt[c_cnt_width-2:0];
end
if (r_idx < gp_interpolation_factor-1)
r_idx <= r_idx+1'b1;
else
r_idx <= 'd0;
r_done <= w_done;
end
end//ALWAYS
for (x=0; x<gp_interpolation_factor; x=x+1)
begin: g_reg_comm_inp
dff #(
.gp_data_width (gp_idata_width)
) REG_COMMUTATOR_INP_DATA (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (r_ring_cnt[x]),
.i_data (i_data[(x+1)*gp_idata_width-1:x*gp_idata_width]),
.o_data (w_data[(x+1)*gp_idata_width-1:x*gp_idata_width])
);
end
assign o_data = (r_idx<gp_interpolation_factor) ? w_data[(r_idx+1)*gp_idata_width-1 -: gp_idata_width] : 'd0;
//assign o_data = w_data[(r_idx+1)*gp_idata_width-1 -: gp_idata_width];
assign w_done = (r_ring_cnt[c_cnt_width-1]) ? 1'b1 : 1'b0;
end//ELSE_GEN
endgenerate
assign o_clk = r_done;
endmodule |
module shift_register #(
parameter gp_data_width = 8, // Input & output bit-width
parameter gp_nr_stages = 4 // Number of shift registers
) (
input wire i_rst_an, // Asynchronous active low reset
input wire i_ena, // Synchronous active high enable
input wire i_clk, // Rising-edge clock
input wire [gp_data_width-1:0] i_data, // Input data with p_data_width bits MSB:LSB, signed
output wire [gp_data_width-1:0] o_data, // Output data with p_data_width bits MSB:LSB, signed
output wire o_shift_done // Flag indicates inital shift operation is done
);
// -------------------------------------------------------------------
// CONSTANT DECLARATION
localparam c_cnt_width = $clog2(gp_nr_stages);
// REGISTER DECLARATION
reg [c_cnt_width-1:0] r_cnt;
reg r_shift_done;
// WIRE DECLARATION
wire w_shift_done;
wire [gp_nr_stages*gp_data_width-1:0] w_data;
// -------------------------------------------------------------------
genvar i;
generate
//begin: g_shift_register
for (i=0; i<gp_nr_stages; i=i+1)
begin: g_shift_register_loop
if (i==0)
begin: g_shift_register_0
dff #(
.gp_data_width (gp_data_width)
) REG_COMMUTATOR_INP_DATA (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (w_data[(i+1)*gp_data_width-1 -: gp_data_width])
);
end
else
begin: g_shift_register_1_n
dff #(
.gp_data_width (gp_data_width)
) REG_COMMUTATOR_INP_DATA (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (w_data[(i)*gp_data_width-1 -: gp_data_width]),
.o_data (w_data[(i+1)*gp_data_width-1 -: gp_data_width])
);
end
end
//end
endgenerate
always @(posedge i_clk or negedge i_rst_an)
begin: p_count_done
if (!i_rst_an)
begin
r_cnt <= {c_cnt_width{1'b1}};
r_shift_done <= 1'b0;
end
else if (i_ena)
begin
if (r_cnt<gp_nr_stages)
r_cnt <= r_cnt + 1'b1;
else
r_cnt <= 'd0;
if (w_shift_done)
r_shift_done <= 1'b1;
end
end
assign w_shift_done = (r_cnt == (gp_nr_stages-1)) ? 1'b1 : r_shift_done;
assign o_shift_done = w_shift_done;
assign o_data = w_data[gp_nr_stages*gp_data_width-1 -: gp_data_width];
endmodule |
module filt_ppi #(
parameter gp_idata_width = 8, // Set input data width
parameter gp_interpolation_factor = 30, // Set number of output channels
parameter gp_coeff_length = 53, // Set filter coefficient length
parameter gp_coeff_width = 16, // Set filter coefficient filter bit-width
parameter gp_tf_df = 1, // Select filter topology 1-> TF | 0-> DF
parameter gp_comm_ccw = 1, // Select commutator 1-> Counter Clock Wise | 0 -> Clock Wise
parameter gp_mul_ccw = 1, // Select multiplier 1-> Counter Clock Wise | 0 -> Clock Wise
parameter gp_comm_phase = 0, // Select downsample phase 0:gp_interpolation_factor-1
parameter gp_odata_width = gp_idata_width+gp_coeff_width+(`DIV(gp_coeff_length,gp_interpolation_factor))
// Set output bit-width
) (
input wire i_rst_an, // Asynchronous active low reset
input wire i_ena, // Synchronous active high enable
input wire i_clk, // Rising-edge clock
input wire i_fclk, // Rising-edge clock
input wire signed [gp_idata_width-1:0] i_data, // Input data with gp_idata_width bits MSB:LSB, signed
output wire signed [gp_odata_width-1:0] o_data, // Output data with gp_interpolation_factor x gp_idata_width width MSB:LSB, signed
output wire o_sclk // Slow clock pulsed output
);
// -------------------------------------------------------------------
wire [gp_interpolation_factor*gp_odata_width-1:0] mul_add_2_comm;
wire [gp_odata_width-1 :0] w_data;
// -------------------------------------------------------------------
mul_add #(
.gp_idata_width (gp_idata_width),
.gp_interpolation_factor (gp_interpolation_factor),
.gp_coeff_length (gp_coeff_length),
.gp_coeff_width (gp_coeff_width),
.gp_tf_df (gp_tf_df),
.gp_ccw (gp_mul_ccw),
.gp_odata_width (gp_odata_width*gp_interpolation_factor)
) ppi_mul_add (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (mul_add_2_comm)
);
commutator #(
.gp_ccw (1'b1),
.gp_idata_width (gp_odata_width),
.gp_interpolation_factor (gp_interpolation_factor)
) ppi_commutator (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_fclk),
.i_data (mul_add_2_comm),
.o_data (w_data),
.o_clk (o_sclk)
);
generate
if (gp_comm_phase==0)
begin: SR_PHASE_EQ_0
assign o_data = w_data;
end
else
begin: g_phase_alignment
shift_register #(
.gp_data_width (gp_odata_width),
.gp_nr_stages (gp_comm_phase)
) SR_PHASE_LT_0 (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_fclk),
.i_data (w_data),
.o_data (o_data),
.o_shift_done ()
);
end
endgenerate
endmodule |
module commutator #(
parameter gp_ccw = 1, // Select: Counter Clock Wise | Clock Wise
parameter gp_idata_width = 8, // Set input data width
parameter gp_decimation_factor = 4, // Set number of output channels
parameter gp_reg_oup = 1, // Select: registered output | none-registered
parameter gp_phase = 0 // Select downsample phase: 0:gp_decimation_factor-1
)
(
input wire i_rst_an, // Asynchronous active low reset
input wire i_ena, // Synchronous active high enable
input wire i_clk, // Rising-edge clock
input wire signed [gp_idata_width-1:0] i_data, // Input data with gp_idata_width bits MSB:LSB, signed
output wire signed [gp_decimation_factor*gp_idata_width-1:0] o_data, // Unsigned data with gp_decimation_factor x gp_idata_width width MSB:LSB
output wire o_clk // Slow clock pulsed output
);
// -------------------------------------------------------------------
// CONSTANT DECLARATION
localparam c_cnt_width = gp_decimation_factor;
// REGISTER DECLARATION
reg [c_cnt_width-1:0] r_ring_cnt;
reg r_done;
// WIRE DECLARATION
wire [c_cnt_width-1:0] w_phase_to_idx;
wire [gp_decimation_factor*gp_idata_width-1:0] w_data;
wire w_ena;
wire w_done;
wire signed [gp_idata_width-1:0] d_data;
genvar x;
// -------------------------------------------------------------------
generate
/**************/
/* Clock Wise */
/**************/
if (!gp_ccw)
begin: g_commutator_cw
// Ring counter clock-wise direction
always @(posedge i_clk or negedge i_rst_an)
begin: p_ring_counter_cw
if (!i_rst_an)
begin
r_ring_cnt <= 'd0;
r_done <= 1'b0;
end
else if (i_ena)
begin
if (r_ring_cnt == 'd0)
begin
r_ring_cnt[c_cnt_width-1] <= 1'b1;
end
else
begin
r_ring_cnt[c_cnt_width-1] <= r_ring_cnt[0];
r_ring_cnt[c_cnt_width-2:0] <= r_ring_cnt[c_cnt_width-1:1];
end
r_done <= w_done;
end
end//ALWAYS
if (gp_phase==0)
begin: SR_PHASE_EQ_0
assign d_data = i_data;
end
else
begin: g_phase_alignment
shift_register #(
.gp_data_width (gp_idata_width),
.gp_nr_stages (gp_phase)
) SR_PHASE_LT_0 (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (d_data),
.o_shift_done (w_ena)
);
end
// Capture input data in clock-wise order MSB->LSB
for (x=gp_decimation_factor; x>0; x=x-1)
begin: g_reg_comm_inp
dff #(
.gp_data_width (gp_idata_width)
) REG_COMMUTATOR_INP_DATA (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (r_ring_cnt[x-1]),
.i_data (d_data),
.o_data (w_data[x*gp_idata_width-1 -: gp_idata_width])
);
end
// Registered output
if (gp_reg_oup)
begin: g_reg_comm_oup
for (x=gp_decimation_factor; x>0; x=x-1)
begin: g_dff
dff #(
.gp_data_width (gp_idata_width)
) REG_COMMUTATOR_OUP_DATA (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (r_done),
.i_data (w_data[x*gp_idata_width-1 -: gp_idata_width]),
.o_data (o_data[x*gp_idata_width-1 -: gp_idata_width])
);
end
end
// Non-registered output
else
begin
assign o_data = w_data;
end
assign w_done = (r_ring_cnt[0]) ? 1'b1 : 1'b0;
end//IF_GEN
/**********************/
/* Counter Clock Wise */
/**********************/
else
begin: g_commutator_ccw
always @(posedge i_clk or negedge i_rst_an)
begin: p_ring_counter_ccw
if (!i_rst_an)
begin
r_ring_cnt <= 'd0;
r_done <= 1'b0;
end
else if (i_ena)
begin
if (r_ring_cnt == 'd0)
begin
r_ring_cnt[0] <= 1'b1;
end
else
begin
r_ring_cnt[0] <= r_ring_cnt[c_cnt_width-1];
r_ring_cnt[c_cnt_width-1:1] <= r_ring_cnt[c_cnt_width-2:0];
end
r_done <= w_done;
end
end//ALWAYS
if (gp_phase==0)
begin: SR_PHASE_EQ_0
assign d_data = i_data;
end
else
begin: g_phase_alignment
shift_register #(
.gp_data_width (gp_idata_width),
.gp_nr_stages (gp_phase)
) SR_PHASE_LT_0 (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (d_data),
.o_shift_done (w_ena)
);
end
for (x=0; x<gp_decimation_factor; x=x+1)
begin: g_reg_comm_inp
dff #(
.gp_data_width (gp_idata_width)
) REG_COMMUTATOR_INP_DATA (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (r_ring_cnt[x]),
.i_data (d_data),
.o_data (w_data[(x+1)*gp_idata_width-1:x*gp_idata_width])
);
end
if (gp_reg_oup)
begin: g_reg_comm_oup
for (x=0; x<gp_decimation_factor; x=x+1)
begin: g_dff
dff #(
.gp_data_width (gp_idata_width)
) REG_COMMUTATOR_OUP_DATA (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (r_done),
.i_data (w_data[(x+1)*gp_idata_width-1:x*gp_idata_width]),
.o_data (o_data[(x+1)*gp_idata_width-1:x*gp_idata_width])
);
end
end
else
begin
assign o_data = w_data;
end
assign w_done = (r_ring_cnt[c_cnt_width-1]) ? 1'b1 : 1'b0;
end//ELSE_GEN
endgenerate
assign o_clk = r_done;
endmodule |
module filt_ppd #(
parameter gp_idata_width = 6, // Set input data width
parameter gp_decimation_factor = 31, // Set number of output channels
parameter gp_coeff_length = 53, // Set filter coefficient length
parameter gp_coeff_width = 16, // Set filter coefficient filter bit-width
parameter gp_tf_df = 0, // Select filter topology 1-> TF | 0-> DF
parameter gp_comm_reg_oup = 1, // Select commutator 1-> registered output | 0 -> none-registered
parameter gp_comm_ccw = 1, // Select commutator 1-> Counter Clock Wise | 0 -> Clock Wise
parameter gp_mul_ccw = 0, // Select multiplier 1-> Counter Clock Wise | 0 -> Clock Wise
parameter gp_comm_phase = 0, // Select downsample phase 0:gp_decimation_factor-1
parameter gp_odata_width = gp_idata_width+gp_coeff_width+$clog2(gp_decimation_factor)+$clog2(`DIV(gp_coeff_length,gp_decimation_factor))
// Set output bit-width
) (
input wire i_rst_an, // Asynchronous active low reset
input wire i_ena, // Synchronous active high enable
input wire i_clk, // Rising-edge clock
input wire signed [gp_idata_width-1:0] i_data, // Input data with gp_idata_width bits MSB:LSB, signed
output wire signed [gp_odata_width-1:0] o_data, // Output data with gp_decimation_factor x gp_idata_width width MSB:LSB, signed
output wire o_sclk // Slow clock pulsed output
);
// -------------------------------------------------------------------
// WIRE DECLARATION
wire s_clk;
wire [gp_decimation_factor*gp_idata_width-1:0] comm_data;
// -------------------------------------------------------------------
commutator #(
.gp_ccw (gp_comm_ccw ),
.gp_idata_width (gp_idata_width ),
.gp_decimation_factor (gp_decimation_factor),
.gp_reg_oup (gp_comm_reg_oup ),
.gp_phase (gp_comm_phase )
) ppd_commutator
(
.i_rst_an (i_rst_an ),
.i_ena (i_ena ),
.i_clk (i_clk ),
.i_data (i_data ),
.o_data (comm_data),
.o_clk (s_clk )
);
mul_add #(
.gp_idata_width (gp_idata_width ),
.gp_decimation_factor (gp_decimation_factor),
.gp_coeff_length (gp_coeff_length ),
.gp_coeff_width (gp_coeff_width ),
.gp_tf_df (gp_tf_df ),
.gp_ccw (gp_mul_ccw ),
.gp_odata_width (gp_odata_width )
) ppd_mul_add (
.i_rst_an (i_rst_an ),
.i_ena (i_ena ),
.i_clk (s_clk ),
.i_data (comm_data),
.o_data (o_data )
);
assign o_sclk = s_clk;
endmodule |
module upsample #(
parameter gp_data_width = 8, // Input & output bit-width
parameter gp_nr_stages = 4, // Number of shift registers
parameter gp_phase = 0
) (
input wire i_rst_an, // Asynchronous active low reset
input wire i_ena, // Synchronous active high enable
input wire i_clk, // Rising-edge clock
input wire [gp_data_width-1:0] i_data, // Input data with p_data_width bits MSB:LSB, signed
output wire [gp_data_width-1:0] o_data, // Output data with p_data_width bits MSB:LSB, signed
output wire o_shift_done // Flag indicates inital shift operation is done
);
// -------------------------------------------------------------------
// CONSTANT DECLARATION
localparam c_cnt_width = $clog2(gp_nr_stages)+1;
localparam c_phase_offset = (gp_phase == 0) ? 1 : gp_phase;
// REGISTER DECLARATION
reg [c_cnt_width-1 :0] r_cnt;
reg r_shift_done;
// WIRE DECLARATION
wire w_shift_done;
wire w_load;
wire [gp_data_width-1 :0] w_upsample_data;
wire [c_phase_offset*gp_data_width-1 :0] w_phase_offset;
wire [(gp_nr_stages-1)*gp_data_width-1:0] w_zero_insertion;
// -------------------------------------------------------------------
// INPUT DATA MUX
assign w_upsample_data = (w_load) ? i_data : w_zero_insertion[gp_data_width-1:0];
genvar i, j;
generate
for (i=0; i<c_phase_offset; i=i+1)
begin: g_offset_zero_insertion
if (gp_phase == 0)
begin
assign w_phase_offset = w_upsample_data;
end
else
begin
if (i==0)
begin: g_shiftreg_dff
dff #(
.gp_data_width (gp_data_width)
) upsample_shiftreg_dff (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (w_upsample_data),
.o_data (w_phase_offset[(i+1)*gp_data_width-1 -: gp_data_width])
);
end
else
begin
dff #(
.gp_data_width (gp_data_width)
) upsample_shiftreg_dff (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (w_phase_offset[(i)*gp_data_width-1 -: gp_data_width]),
.o_data (w_phase_offset[(i+1)*gp_data_width-1 -: gp_data_width])
);
end
end
end//FOR
endgenerate
generate
for (j=0; j<gp_nr_stages-1; j=j+1)
begin: g_upsample_zero_insertion
if (j!=gp_nr_stages-2)
begin
dff #(
.gp_data_width (gp_data_width)
) upsample_shiftreg_dff (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (w_zero_insertion[(j+2)*gp_data_width-1 -: gp_data_width]),
.o_data (w_zero_insertion[(j+1)*gp_data_width-1 -: gp_data_width])
);
end
else
begin
assign w_zero_insertion[(j+1)*gp_data_width-1 -: gp_data_width] = 'd0;
end
end
endgenerate
always @(posedge i_clk or negedge i_rst_an)
begin: p_count_stages
if (!i_rst_an)
begin
r_cnt <= gp_nr_stages;
r_shift_done <= 1'b0;
end
else if (i_ena)
begin
if (r_cnt<gp_nr_stages-1)
r_cnt <= r_cnt + 1'b1;
else
r_cnt <= 'd0;
if (w_shift_done)
r_shift_done <= 1'b1;
end
end
assign w_load = (r_cnt == 0) ? 1'b1 : 1'b0;
assign w_shift_done = (r_cnt == gp_nr_stages) ? 1'b1 : r_shift_done;
assign o_shift_done = w_shift_done;
assign o_data = w_phase_offset[c_phase_offset*gp_data_width-1 -: gp_data_width];
endmodule |
module filt_cici #(
parameter gp_interpolation_factor = 4,
parameter gp_order = 3,
parameter gp_diff_delay = 1,
parameter gp_phase = 0,
parameter gp_inp_width = 8,
parameter gp_oup_width = gp_inp_width + gp_order*$clog2(gp_interpolation_factor*gp_diff_delay)
) (
input wire i_rst_an,
input wire i_ena,
input wire i_clk,
input wire i_fclk,
input wire signed [gp_inp_width-1:0] i_data,
output wire signed [gp_oup_width-1:0] o_data
);
// -------------------------------------------------------------------
// CONSTANT DECLARATION
localparam c_fill_width = gp_oup_width - gp_inp_width;
// REGISTER DECLARATION
//wire w_sclk;
wire signed [gp_oup_width-1 :0] r_int_inp;
wire signed [gp_order*gp_oup_width-1:0] r_int_dly;
wire signed [gp_order*gp_oup_width-1:0] r_comb_dly;
// WIRE DECLARATION
wire signed [gp_oup_width-1 :0] w_data;
wire signed [gp_oup_width-1 :0] w_upsample_inp;
wire signed [gp_order*gp_oup_width-1:0] w_int_add;
wire signed [gp_order*gp_oup_width-1:0] w_comb_diff;
// -------------------------------------------------------------------
genvar i;
// -------------------------------------------------------------------
/*********************/
/* INPUT MSB PADDING */
/*********************/
assign w_data = $signed({{c_fill_width{i_data[gp_inp_width-1]}},i_data});
/****************/
/* COMB SECTION */
/****************/
generate
for (i=0; i<gp_order; i=i+1)
begin: g_comb
if (i==0)
begin: g_comb_0
shift_register #(
.gp_data_width (gp_oup_width),
.gp_nr_stages (gp_diff_delay)
) CIC_COMB_SR (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (w_data),
.o_data (r_comb_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]),
.o_shift_done ()
);
assign w_comb_diff[(i+1)*gp_oup_width-1 -: gp_oup_width] = $signed(w_data) - $signed(r_comb_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]);
end
else
begin: g_comb_1_n
shift_register #(
.gp_data_width (gp_oup_width),
.gp_nr_stages (gp_diff_delay)
) CIC_COMB_SR (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (w_comb_diff[i*gp_oup_width-1 -: gp_oup_width]),
.o_data (r_comb_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]),
.o_shift_done ()
);
assign w_comb_diff[(i+1)*gp_oup_width-1 -: gp_oup_width] = $signed(w_comb_diff[i*gp_oup_width-1 -: gp_oup_width]) - $signed(r_comb_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]);
end
end
endgenerate
/**********************/
/* UPSAMPLE SECTION */
/**********************/
assign w_upsample_inp = $signed(w_comb_diff[gp_order*gp_oup_width-1 -: gp_oup_width]); // for debugging
upsample #(
.gp_data_width (gp_oup_width),
.gp_nr_stages (gp_interpolation_factor),
.gp_phase (gp_phase)
) cici_upsample (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_fclk),
.i_data (w_upsample_inp),
.o_data (r_int_inp),
.o_shift_done ()
);
/**********************/
/* INTEGRATOR SECTION */
/**********************/
generate
for (i=0; i<gp_order; i=i+1)
begin: g_integrator
if (i==0)
begin: g_int_0
assign w_int_add[(i+1)*gp_oup_width-1 -: gp_oup_width] = $signed(r_int_inp) + $signed(r_int_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]);
dff #(
.gp_data_width (gp_oup_width)
) CIC_INT_DLY (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_fclk),
.i_data (w_int_add[(i+1)*gp_oup_width-1 -: gp_oup_width]),
.o_data (r_int_dly[(i+1)*gp_oup_width-1 -: gp_oup_width])
);
end
else
begin: g_int_1_n
assign w_int_add[(i+1)*gp_oup_width-1 -: gp_oup_width] = $signed(w_int_add[i*gp_oup_width-1 -: gp_oup_width]) + $signed(r_int_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]);
dff #(
.gp_data_width (gp_oup_width)
) CIC_INT_DLY (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_fclk),
.i_data (w_int_add[(i+1)*gp_oup_width-1 -: gp_oup_width]),
.o_data (r_int_dly[(i+1)*gp_oup_width-1 -: gp_oup_width])
);
end
end
endgenerate
assign o_data = w_int_add[gp_order*gp_oup_width-1 -: gp_oup_width];
endmodule |
module filt_cicd #(
parameter gp_decimation_factor = 4,
parameter gp_order = 3,
parameter gp_diff_delay = 1,
parameter gp_phase = 0,
parameter gp_inp_width = 8,
parameter gp_oup_width = gp_inp_width + gp_order*$clog2(gp_decimation_factor*gp_diff_delay)
) (
input wire i_rst_an,
input wire i_ena,
input wire i_clk,
input wire signed [gp_inp_width-1:0] i_data,
output wire signed [gp_oup_width-1:0] o_data
);
// -------------------------------------------------------------------
// CONSTANT DECLARATION
localparam c_fill_width = gp_oup_width - gp_inp_width;
// REGISTER DECLARATION
wire w_sclk;
wire signed [gp_oup_width-1 :0] r_comb_inp;
reg [gp_decimation_factor-1 :0] r_count;
wire signed [gp_order*gp_oup_width-1:0] r_int_dly;
wire signed [gp_order*gp_oup_width-1:0] r_comb_dly;
// WIRE DECLARATION
wire signed [gp_oup_width-1 :0] w_data;
wire signed [gp_order*gp_oup_width-1:0] w_int_add;
wire signed [gp_order*gp_oup_width-1:0] w_comb_diff;
// -------------------------------------------------------------------
genvar i;
// -------------------------------------------------------------------
/****************/
/* RING COUNTER */
/****************/
always @(posedge i_clk or negedge i_rst_an)
begin: p_ring_counter
if (!i_rst_an)
begin
r_count <= 'd0;
end
else if (i_ena)
begin
if (r_count=='d0)
r_count[0] <= 1'b1;
else
begin
r_count[0] <= r_count[gp_decimation_factor-1];
r_count[gp_decimation_factor-1:1] <= r_count[gp_decimation_factor-2:0];
end
end
end
/*********************/
/* INPUT MSB PADDING */
/*********************/
assign w_data = {{c_fill_width{i_data[gp_inp_width-1]}},i_data};
/**********************/
/* INTEGRATOR SECTION */
/**********************/
generate
for (i=0; i<gp_order; i=i+1)
begin: g_integrator
if (i==0)
begin: g_int_0
assign w_int_add[(i+1)*gp_oup_width-1 -: gp_oup_width] = $signed(w_data) + $signed(r_int_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]);
dff #(
.gp_data_width (gp_oup_width)
) CIC_INT_DLY (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (w_int_add[(i+1)*gp_oup_width-1 -: gp_oup_width]),
.o_data (r_int_dly[(i+1)*gp_oup_width-1 -: gp_oup_width])
);
end
else
begin: g_int_1_n
assign w_int_add[(i+1)*gp_oup_width-1 -: gp_oup_width] = $signed(w_int_add[i*gp_oup_width-1 -: gp_oup_width]) + $signed(r_int_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]);
dff #(
.gp_data_width (gp_oup_width)
) CIC_INT_DLY (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (w_int_add[(i+1)*gp_oup_width-1 -: gp_oup_width]),
.o_data (r_int_dly[(i+1)*gp_oup_width-1 -: gp_oup_width])
);
end
end
endgenerate
/**********************/
/* DOWNSAMPLE SECTION */
/**********************/
assign w_sclk = r_count[gp_phase];
dff #(
.gp_data_width (gp_oup_width)
) cicd_downsample (
.i_rst_an (i_rst_an),
.i_ena (w_sclk),
.i_clk (i_clk),
.i_data (w_int_add[gp_order*gp_oup_width-1 -: gp_oup_width]),
.o_data (r_comb_inp)
);
/****************/
/* COMB SECTION */
/****************/
generate
for (i=0; i<gp_order; i=i+1)
begin: g_comb
if (i==0)
begin: g_comb_0
shift_register #(
.gp_data_width (gp_oup_width),
.gp_nr_stages (gp_diff_delay)
) CIC_COMB_SR (
.i_rst_an (i_rst_an),
.i_ena (r_count[gp_phase]),
.i_clk (i_clk),
.i_data (r_comb_inp),
.o_data (r_comb_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]),
.o_shift_done ()
);
assign w_comb_diff[(i+1)*gp_oup_width-1 -: gp_oup_width] = $signed(r_comb_inp) - $signed(r_comb_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]);
end
else
begin: g_comb_1_n
shift_register #(
.gp_data_width (gp_oup_width),
.gp_nr_stages (gp_diff_delay)
) CIC_COMB_SR (
.i_rst_an (i_rst_an),
.i_ena (r_count[gp_phase]),
.i_clk (i_clk),
.i_data (w_comb_diff[i*gp_oup_width-1 -: gp_oup_width]),
.o_data (r_comb_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]),
.o_shift_done ()
);
assign w_comb_diff[(i+1)*gp_oup_width-1 -: gp_oup_width] = $signed(w_comb_diff[i*gp_oup_width-1 -: gp_oup_width]) - $signed(r_comb_dly[(i+1)*gp_oup_width-1 -: gp_oup_width]);
end
end
endgenerate
assign o_data = w_comb_diff[gp_order*gp_oup_width-1 -: gp_oup_width];
endmodule |
module CPU_TEST;
/* CPU Signals */
reg RESET;
reg CLOCK;
/* Connect CPU to Instruction Memory */
wire [63:0] PC_wire;
wire [31:0] IC_wire;
/* Connect CPU to Data Memory */
wire [63:0] mem_address;
wire [63:0] mem_data_in;
wire control_memwrite;
wire control_memread;
wire [63:0] mem_data_out;
ARM_CPU core (RESET, CLOCK, IC_wire, mem_data_out, PC_wire, mem_address, mem_data_in, control_memwrite, control_memread);
IC mem1 (PC_wire, IC_wire);
Data_Memory mem2 (mem_address, mem_data_in, control_memwrite, control_memread, mem_data_out);
/* Setup the clock */
initial begin
CLOCK = 1'b0;
RESET = 1'b1;
#30 $finish;
end
/* Toggle the clock */
always begin
#1 CLOCK = ~CLOCK; RESET = 1'b0;
end
endmodule |
module ARM_CPU
(
input RESET,
input CLOCK,
input [31:0] IC,
input [63:0] mem_data_in,
output reg [63:0] PC,
output [63:0] mem_address_out,
output [63:0] mem_data_out,
output control_memwrite_out,
output control_memread_out
);
wire Hazard_PCWrite;
wire Hazard_IFIDWrite;
always @(posedge CLOCK) begin
if (Hazard_PCWrite !== 1'b1) begin
if (PC === 64'bx) begin
PC <= 0;
end else if (PCSrc_wire == 1'b1) begin
PC <= jump_PC_wire;
end else begin
PC <= PC + 4;
end
end
end
/* Stage : Instruction Fetch */
wire PCSrc_wire;
wire [63:0] jump_PC_wire;
wire [63:0] IFID_PC;
wire [31:0] IFID_IC;
IFID cache1 (CLOCK, PC, IC, Hazard_IFIDWrite, IFID_PC, IFID_IC);
/* Stage : Instruction Decode */
wire IDEX_memRead;
wire [4:0] IDEX_write_reg;
wire Control_mux_wire;
HazardDetection moda (IDEX_memRead, IDEX_write_reg, IFID_PC, IFID_IC, Hazard_IFIDWrite, Hazard_PCWrite, Control_mux_wire);
wire [1:0] CONTROL_aluop; // EX
wire CONTROL_alusrc; // EX
wire CONTROL_isZeroBranch; // M
wire CONTROL_isUnconBranch; // M
wire CONTROL_memRead; // M
wire CONTROL_memwrite; // M
wire CONTROL_regwrite; // WB
wire CONTROL_mem2reg; // WB
ARM_Control unit1 (IFID_IC[31:21], CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUnconBranch, CONTROL_memRead, CONTROL_memwrite, CONTROL_regwrite, CONTROL_mem2reg);
wire [1:0] CONTROL_aluop_wire; // EX
wire CONTROL_alusrc_wire; // EX
wire CONTROL_isZeroBranch_wire; // M
wire CONTROL_isUnconBranch_wire; // M
wire CONTROL_memRead_wire; // M
wire CONTROL_memwrite_wire; // M
wire CONTROL_regwrite_wire; // WB
wire CONTROL_mem2reg_wire; // WB
Control_Mux maaa (CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUnconBranch, CONTROL_memRead, CONTROL_memwrite, CONTROL_regwrite, CONTROL_mem2reg, Control_mux_wire, CONTROL_aluop_wire, CONTROL_alusrc_wire, CONTROL_isZeroBranch_wire, CONTROL_isUnconBranch_wire, CONTROL_memRead_wire, CONTROL_memwrite_wire, CONTROL_regwrite_wire, CONTROL_mem2reg_wire);
wire [4:0] reg2_wire;
ID_Mux unit2(IFID_IC[20:16], IFID_IC[4:0], IFID_IC[28], reg2_wire);
wire [63:0] reg1_data, reg2_data;
wire MEMWB_regwrite;
wire [4:0] MEMWB_write_reg;
wire [63:0] write_reg_data;
Registers unit3(CLOCK, IFID_IC[9:5], reg2_wire, MEMWB_write_reg, write_reg_data, MEMWB_regwrite, reg1_data, reg2_data);
wire [63:0] sign_extend_wire;
SignExtend unit4 (IFID_IC, sign_extend_wire);
wire [1:0] IDEX_aluop;
wire IDEX_alusrc;
wire IDEX_isZeroBranch;
wire IDEX_isUnconBranch;
wire IDEX_memwrite;
wire IDEX_regwrite;
wire IDEX_mem2reg;
wire [63:0] IDEX_reg1_data;
wire [63:0] IDEX_reg2_data;
wire [63:0] IDEX_PC;
wire [63:0] IDEX_sign_extend;
wire [10:0] IDEX_alu_control;
wire [4:0] IDEX_forward_reg1;
wire [4:0] IDEX_forward_reg2;
IDEX cache2 (CLOCK, CONTROL_aluop_wire, CONTROL_alusrc_wire, CONTROL_isZeroBranch_wire, CONTROL_isUnconBranch_wire, CONTROL_memRead_wire, CONTROL_memwrite_wire, CONTROL_regwrite_wire, CONTROL_mem2reg_wire, IFID_PC, reg1_data, reg2_data, sign_extend_wire, IFID_IC[31:21], IFID_IC[4:0], IFID_IC[9:5], reg2_wire, IDEX_aluop, IDEX_alusrc, IDEX_isZeroBranch, IDEX_isUnconBranch, IDEX_memRead, IDEX_memwrite, IDEX_regwrite, IDEX_mem2reg, IDEX_PC, IDEX_reg1_data, IDEX_reg2_data, IDEX_sign_extend, IDEX_alu_control, IDEX_write_reg, IDEX_forward_reg1, IDEX_forward_reg2);
/* Stage : Execute */
wire [63:0] shift_left_wire;
wire [63:0] PC_jump;
wire jump_is_zero;
Shift_Left unit5 (IDEX_sign_extend, shift_left_wire);
ALU unit6 (IDEX_PC, shift_left_wire, 4'b0010, PC_jump, jump_is_zero);
wire [4:0] EXMEM_write_reg;
wire EXMEM_regwrite;
wire EXMEM_mem2reg;
wire [1:0] Forward_A;
wire [1:0] Forward_B;
ForwardingUnit modd (IDEX_forward_reg1, IDEX_forward_reg2, EXMEM_write_reg, MEMWB_write_reg, EXMEM_regwrite, MEMWB_regwrite, Forward_A, Forward_B);
wire [63:0] alu_1_wire;
Forward_ALU_Mux lal1 (IDEX_reg1_data, write_reg_data, mem_address_out, Forward_A, alu_1_wire);
wire [63:0] alu_2_wire;
Forward_ALU_Mux lal2 (IDEX_reg2_data, write_reg_data, mem_address_out, Forward_B, alu_2_wire);
wire [3:0] alu_main_control_wire;
ALU_Control unit7(IDEX_aluop, IDEX_alu_control, alu_main_control_wire);
wire [63:0] alu_data2_wire;
ALU_Mux mux3(alu_2_wire, IDEX_sign_extend, IDEX_alusrc, alu_data2_wire);
wire alu_main_is_zero;
wire [63:0] alu_main_result;
ALU main_alu(alu_1_wire, alu_data2_wire, alu_main_control_wire, alu_main_result, alu_main_is_zero);
wire EXMEM_isZeroBranch;
wire EXMEM_isUnconBranch;
wire EXMEM_alu_zero;
EXMEM cache3(CLOCK, IDEX_isZeroBranch, IDEX_isUnconBranch, IDEX_memRead, IDEX_memwrite, IDEX_regwrite, IDEX_mem2reg, PC_jump, alu_main_is_zero, alu_main_result, IDEX_reg2_data, IDEX_write_reg, EXMEM_isZeroBranch, EXMEM_isUnconBranch, control_memread_out, control_memwrite_out, EXMEM_regwrite, EXMEM_mem2reg, jump_PC_wire, EXMEM_alu_zero, mem_address_out, mem_data_out, EXMEM_write_reg);
/* Stage : Memory */
Branch unit8 (EXMEM_isUnconBranch, EXMEM_isZeroBranch, EXMEM_alu_zero, PCSrc_wire);
wire [63:0] MEMWB_address;
wire [63:0] MEMWB_read_data;
MEMWB cache4(CLOCK, mem_address_out, mem_data_in, EXMEM_write_reg, EXMEM_regwrite, EXMEM_mem2reg, MEMWB_address, MEMWB_read_data, MEMWB_write_reg, MEMWB_regwrite, MEMWB_mem2reg);
/* Stage : Writeback */
WB_Mux unit9 (MEMWB_address, MEMWB_read_data, MEMWB_mem2reg, write_reg_data);
endmodule |
module ForwardingUnit
(
input [4:0] EX_Rn_in,
input [4:0] EX_Rm_in,
input [4:0] MEM_Rd_in,
input [4:0] WB_Rd_in,
input MEM_regwrite_in,
input WB_regwrite_in,
output reg [1:0] A_out,
output reg [1:0] B_out
);
always @(*) begin
if ((WB_regwrite_in == 1'b1) &&
(WB_Rd_in !== 31) &&
/* (!((MEM_regwrite_in == 1'b1) && (MEM_Rd_in !== 31) && (MEM_Rd_in !== EX_Rn_in))) && */
(WB_Rd_in === EX_Rn_in)) begin
A_out <= 2'b01;
end else if ((MEM_regwrite_in == 1'b1) &&
(MEM_Rd_in !== 31) &&
(MEM_Rd_in === EX_Rn_in)) begin
A_out <= 2'b10;
end else begin
A_out <= 2'b00;
end
if ((WB_regwrite_in == 1'b1) &&
(WB_Rd_in !== 31) &&
/* (!((MEM_regwrite_in == 1'b1) && (MEM_Rd_in !== 31) && (MEM_Rd_in !== EX_Rm_in))) && */
(WB_Rd_in === EX_Rm_in)) begin
B_out <= 2'b01;
end else if ((MEM_regwrite_in == 1'b1) &&
(MEM_Rd_in !== 31) &&
(MEM_Rd_in === EX_Rm_in)) begin
B_out <= 2'b10;
end else begin
B_out <= 2'b00;
end
end
endmodule |
module HazardDetection
(
input EX_memRead_in,
input [4:0] EX_write_reg,
input [63:0] ID_PC,
input [31:0] ID_IC,
output reg IFID_write_out,
output reg PC_Write_out,
output reg Control_mux_out
);
always @(*) begin
if (EX_memRead_in == 1'b1 && ((EX_write_reg === ID_IC[9:5]) || (EX_write_reg === ID_IC[20:16]))) begin
IFID_write_out <= 1'b1;
PC_Write_out <= 1'b1;
Control_mux_out <= 1'b1;
end else begin
IFID_write_out <= 1'b0;
PC_Write_out <= 1'b0;
Control_mux_out <= 1'b0;
end
end
endmodule |
module IFID
(
input CLOCK,
input [63:0] PC_in,
input [31:0] IC_in,
input Hazard_in,
output reg [63:0] PC_out,
output reg [31:0] IC_out
);
always @(negedge CLOCK) begin
if (Hazard_in !== 1'b1) begin
PC_out <= PC_in;
IC_out <= IC_in;
end
end
endmodule |
module IDEX
(
input CLOCK,
input [1:0] aluop_in,
input alusrc_in,
input isZeroBranch_in,
input isUnconBranch_in,
input memRead_in,
input memwrite_in,
input regwrite_in,
input mem2reg_in,
input [63:0] PC_in,
input [63:0] regdata1_in,
input [63:0] regdata2_in,
input [63:0] sign_extend_in,
input [10:0] alu_control_in,
input [4:0] write_reg_in,
input [4:0] forward_reg_1_in, // Forwarding
input [4:0] forward_reg_2_in, // Forwarding
output reg [1:0] aluop_out,
output reg alusrc_out,
output reg isZeroBranch_out,
output reg isUnconBranch_out,
output reg memRead_out,
output reg memwrite_out,
output reg regwrite_out,
output reg mem2reg_out,
output reg [63:0] PC_out,
output reg [63:0] regdata1_out,
output reg [63:0] regdata2_out,
output reg [63:0] sign_extend_out,
output reg [10:0] alu_control_out,
output reg [4:0] write_reg_out,
output reg [4:0] forward_reg_1_out, // Forwarding
output reg [4:0] forward_reg_2_out // Forwarding
);
always @(negedge CLOCK) begin
/* Values for EX */
aluop_out <= aluop_in;
alusrc_out <= alusrc_in;
/* Values for M */
isZeroBranch_out <= isZeroBranch_in;
isUnconBranch_out <= isUnconBranch_in;
memRead_out <= memRead_in;
memwrite_out <= memwrite_in;
/* Values for WB */
regwrite_out <= regwrite_in;
mem2reg_out <= mem2reg_in;
/* Values for all Stages */
PC_out <= PC_in;
regdata1_out <= regdata1_in;
regdata2_out <= regdata2_in;
/* Values for variable stages */
sign_extend_out <= sign_extend_in;
alu_control_out <= alu_control_in;
write_reg_out <= write_reg_in;
forward_reg_1_out <= forward_reg_1_in;
forward_reg_2_out <= forward_reg_2_in;
end
endmodule |
module EXMEM
(
input CLOCK,
input isZeroBranch_in, // M Stage
input isUnconBranch_in, // M Stage
input memRead_in, // M Stage
input memwrite_in, // M Stage
input regwrite_in, // WB Stage
input mem2reg_in, // WB Stage
input [63:0] shifted_PC_in,
input alu_zero_in,
input [63:0] alu_result_in,
input [63:0] write_data_mem_in,
input [4:0] write_reg_in,
output reg isZeroBranch_out, // M Stage
output reg isUnconBranch_out, // M Stage
output reg memRead_out, // M Stage
output reg memwrite_out, // M Stage
output reg regwrite_out, // WB Stage
output reg mem2reg_out, // WB Stage
output reg [63:0] shifted_PC_out,
output reg alu_zero_out,
output reg [63:0] alu_result_out,
output reg [63:0] write_data_mem_out,
output reg [4:0] write_reg_out
);
always @(negedge CLOCK) begin
/* Values for M */
isZeroBranch_out <= isZeroBranch_in;
isUnconBranch_out <= isUnconBranch_in;
memRead_out <= memRead_in;
memwrite_out <= memwrite_in;
/* Values for WB */
regwrite_out <= regwrite_in;
mem2reg_out <= mem2reg_in;
/* Values for all Stages */
shifted_PC_out <= shifted_PC_in;
alu_zero_out <= alu_zero_in;
alu_result_out <= alu_result_in;
write_data_mem_out <= write_data_mem_in;
write_reg_out <= write_reg_in;
end
endmodule |
module MEMWB
(
input CLOCK,
input [63:0] mem_address_in,
input [63:0] mem_data_in,
input [4:0] write_reg_in,
input regwrite_in,
input mem2reg_in,
output reg [63:0] mem_address_out,
output reg [63:0] mem_data_out,
output reg [4:0] write_reg_out,
output reg regwrite_out,
output reg mem2reg_out
);
always @(negedge CLOCK) begin
regwrite_out <= regwrite_in;
mem2reg_out <= mem2reg_in;
mem_address_out <= mem_address_in;
mem_data_out <= mem_data_in;
write_reg_out <= write_reg_in;
end
endmodule |
module Registers
(
input CLOCK,
input [4:0] read1,
input [4:0] read2,
input [4:0] writeReg,
input [63:0] writeData,
input CONTROL_REGWRITE,
output reg [63:0] data1,
output reg [63:0] data2
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 31; initCount = initCount + 1) begin
Data[initCount] = initCount;
end
Data[31] = 64'h00000000;
end
always @(posedge CLOCK) begin
if (CONTROL_REGWRITE == 1'b1) begin
Data[writeReg] = writeData;
end
data1 = Data[read1];
data2 = Data[read2];
// Debug use only
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
$display("REGISTER[%0d] = %0d", initCount, Data[initCount]);
end
end
endmodule |
module IC
(
input [63:0] PC_in,
output reg [31:0] instruction_out
);
reg [8:0] Data[63:0];
initial begin
// LDUR x0, [x2, #3]
Data[0] = 8'hf8; Data[1] = 8'h40; Data[2] = 8'h30; Data[3] = 8'h40;
// ADD x9, x0, x5
Data[4] = 8'h8b; Data[5] = 8'h05; Data[6] = 8'h00; Data[7] = 8'h09;
// ORR x10, x1, x9
Data[8] = 8'haa; Data[9] = 8'h09; Data[10] = 8'h00; Data[11] = 8'h2a;
// AND x11, x9, x0
Data[12] = 8'h8a; Data[13] = 8'h00; Data[14] = 8'h01; Data[15] = 8'h2b;
// SUB x12 x0 x11
Data[16] = 8'hcb; Data[17] = 8'h0b; Data[18] = 8'h00; Data[19] = 8'h0c;
// STUR x9, [x3, #6]
Data[20] = 8'hf8; Data[21] = 8'h00; Data[22] = 8'h60; Data[23] = 8'h69;
// STUR x10, [x4, #6]
Data[24] = 8'hf8; Data[25] = 8'h00; Data[26] = 8'h60; Data[27] = 8'h8a;
// STUR x11, [x5, #6]
Data[28] = 8'hf8; Data[29] = 8'h00; Data[30] = 8'h60; Data[31] = 8'hab;
// STUR x12, [x6, #6]
Data[32] = 8'hf8; Data[33] = 8'h00; Data[34] = 8'h60; Data[35] = 8'hcc;
// B #10
Data[36] = 8'h14; Data[37] = 8'h00; Data[38] = 8'h00; Data[39] = 8'h0a;
end
always @(PC_in) begin
instruction_out[8:0] = Data[PC_in + 3];
instruction_out[16:8] = Data[PC_in + 2];
instruction_out[24:16] = Data[PC_in + 1];
instruction_out[31:24] = Data[PC_in];
end
endmodule |
module Data_Memory
(
input [63:0] inputAddress,
input [63:0] inputData,
input CONTROL_MemWrite,
input CONTROL_MemRead,
output reg [63:0] outputData
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
Data[initCount] = initCount * 5;
end
end
always @(*) begin
if (CONTROL_MemWrite == 1'b1) begin
Data[inputAddress] = inputData;
end else if (CONTROL_MemRead == 1'b1) begin
outputData = Data[inputAddress];
end else begin
outputData = 64'hxxxxxxxx;
end
// Debug use only
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
$display("RAM[%0d] = %0d", initCount, Data[initCount]);
end
end
endmodule |
module ALU
(
input [63:0] A,
input [63:0] B,
input [3:0] CONTROL,
output reg [63:0] RESULT,
output reg ZEROFLAG
);
always @(*) begin
case (CONTROL)
4'b0000 : RESULT = A & B;
4'b0001 : RESULT = A | B;
4'b0010 : RESULT = A + B;
4'b0110 : RESULT = A - B;
4'b0111 : RESULT = B;
4'b1100 : RESULT = ~(A | B);
default : RESULT = 64'hxxxxxxxx;
endcase
if (RESULT == 0) begin
ZEROFLAG = 1'b1;
end else if (RESULT != 0) begin
ZEROFLAG = 1'b0;
end else begin
ZEROFLAG = 1'bx;
end
end
endmodule |
module ALU_Control
(
input [1:0] ALU_Op,
input [10:0] ALU_INSTRUCTION,
output reg [3:0] ALU_Out
);
always @(ALU_Op or ALU_INSTRUCTION) begin
case (ALU_Op)
2'b00 : ALU_Out <= 4'b0010;
2'b01 : ALU_Out <= 4'b0111;
2'b10 : begin
case (ALU_INSTRUCTION)
11'b10001011000 : ALU_Out <= 4'b0010; // ADD
11'b11001011000 : ALU_Out <= 4'b0110; // SUB
11'b10001010000 : ALU_Out <= 4'b0000; // AND
11'b10101010000 : ALU_Out <= 4'b0001; // ORR
endcase
end
default : ALU_Out = 4'bxxxx;
endcase
end
endmodule |
module Control_Mux
(
input [1:0] CONTROL_aluop_in,
input CONTROL_alusrc_in,
input CONTROL_isZeroBranch_in,
input CONTROL_isUnconBranch_in,
input CONTROL_memRead_in,
input CONTROL_memwrite_in,
input CONTROL_regwrite_in,
input CONTROL_mem2reg_in,
input mux_control_in,
output reg [1:0] CONTROL_aluop_out,
output reg CONTROL_alusrc_out,
output reg CONTROL_isZeroBranch_out,
output reg CONTROL_isUnconBranch_out,
output reg CONTROL_memRead_out,
output reg CONTROL_memwrite_out,
output reg CONTROL_regwrite_out,
output reg CONTROL_mem2reg_out
);
always @(*) begin
if (mux_control_in === 1'b1) begin
CONTROL_aluop_out <= 2'b00;
CONTROL_alusrc_out <= 1'b0;
CONTROL_isZeroBranch_out <= 1'b0;
CONTROL_isUnconBranch_out <= 1'b0;
CONTROL_memRead_out <= 1'b0;
CONTROL_memwrite_out <= 1'b0;
CONTROL_regwrite_out <= 1'b0;
CONTROL_mem2reg_out <= 1'b0;
end else begin
CONTROL_aluop_out <= CONTROL_aluop_in;
CONTROL_alusrc_out <= CONTROL_alusrc_in;
CONTROL_isZeroBranch_out <= CONTROL_isZeroBranch_in;
CONTROL_isUnconBranch_out <= CONTROL_isUnconBranch_in;
CONTROL_memRead_out <= CONTROL_memRead_in;
CONTROL_memwrite_out <= CONTROL_memwrite_in;
CONTROL_regwrite_out <= CONTROL_regwrite_in;
CONTROL_mem2reg_out <= CONTROL_mem2reg_in;
end
end
endmodule |
module Forward_ALU_Mux
(
input [63:0] reg_ex_in,
input [63:0] reg_wb_in,
input [63:0] reg_mem_in,
input [1:0] forward_control_in,
output reg [63:0] reg_out
);
always @(*) begin
case (forward_control_in)
2'b01 : reg_out <= reg_wb_in;
2'b10 : reg_out <= reg_mem_in;
default : reg_out <= reg_ex_in;
endcase
end
endmodule |
module ALU_Mux
(
input [63:0] input1,
input [63:0] input2,
input CONTROL_ALUSRC,
output reg [63:0] out
);
always @(input1, input2, CONTROL_ALUSRC, out) begin
if (CONTROL_ALUSRC === 0) begin
out <= input1;
end
else begin
out <= input2;
end
end
endmodule |
module ID_Mux
(
input [4:0] read1_in,
input [4:0] read2_in,
input reg2loc_in,
output reg [4:0] reg_out
);
always @(read1_in, read2_in, reg2loc_in) begin
case (reg2loc_in)
1'b0 : begin
reg_out <= read1_in;
end
1'b1 : begin
reg_out <= read2_in;
end
default : begin
reg_out <= 1'bx;
end
endcase
end
endmodule |
module WB_Mux
(
input [63:0] input1,
input [63:0] input2,
input mem2reg_control,
output reg [63:0] out
);
always @(*) begin
if (mem2reg_control == 0) begin
out <= input1;
end
else begin
out <= input2;
end
end
endmodule |
module Shift_Left
(
input [63:0] data_in,
output reg [63:0] data_out
);
always @(data_in) begin
data_out <= data_in << 2;
end
endmodule |
module SignExtend
(
input [31:0] inputInstruction,
output reg [63:0] outImmediate
);
always @(inputInstruction) begin
if (inputInstruction[31:26] == 6'b000101) begin // B
outImmediate[25:0] = inputInstruction[25:0];
outImmediate[63:26] = {64{outImmediate[25]}};
end else if (inputInstruction[31:24] == 8'b10110100) begin // CBZ
outImmediate[19:0] = inputInstruction[23:5];
outImmediate[63:20] = {64{outImmediate[19]}};
end else begin // D Type, ignored if R type
outImmediate[9:0] = inputInstruction[20:12];
outImmediate[63:10] = {64{outImmediate[9]}};
end
end
endmodule |
module Branch
(
input unconditional_branch_in,
input conditional_branch_in,
input alu_main_is_zero,
output reg PC_src_out
);
reg conditional_branch_temp;
always @(unconditional_branch_in, conditional_branch_in, alu_main_is_zero) begin
conditional_branch_temp <= conditional_branch_in & alu_main_is_zero;
PC_src_out <= unconditional_branch_in | conditional_branch_temp;
end
endmodule |
module ARM_Control
(
input [10:0] instruction,
output reg [1:0] control_aluop,
output reg control_alusrc,
output reg control_isZeroBranch,
output reg control_isUnconBranch,
output reg control_memRead,
output reg control_memwrite,
output reg control_regwrite,
output reg control_mem2reg
);
always @(instruction) begin
if (instruction[10:5] == 6'b000101) begin // B
control_mem2reg <= 1'bx;
control_memRead <= 1'b0;
control_memwrite <= 1'b0;
control_alusrc <= 1'b0;
control_aluop <= 2'b01;
control_isZeroBranch <= 1'b0;
control_isUnconBranch <= 1'b1;
control_regwrite <= 1'b0;
end else if (instruction[10:3] == 8'b10110100) begin // CBZ
control_mem2reg <= 1'bx;
control_memRead <= 1'b0;
control_memwrite <= 1'b0;
control_alusrc <= 1'b0;
control_aluop <= 2'b01;
control_isZeroBranch <= 1'b1;
control_isUnconBranch <= 1'b0;
control_regwrite <= 1'b0;
end else begin // R-Type Instructions
control_isZeroBranch <= 1'b0;
control_isUnconBranch <= 1'b0;
case (instruction[10:0])
11'b11111000010 : begin // LDUR
control_mem2reg <= 1'b1;
control_memRead <= 1'b1;
control_memwrite <= 1'b0;
control_alusrc <= 1'b1;
control_aluop <= 2'b00;
control_regwrite <= 1'b1;
end
11'b11111000000 : begin // STUR
control_mem2reg <= 1'bx;
control_memRead <= 1'b0;
control_memwrite <= 1'b1;
control_alusrc <= 1'b1;
control_aluop <= 2'b00;
control_regwrite <= 1'b0;
end
11'b10001011000 : begin // ADD
control_mem2reg <= 1'b0;
control_memRead <= 1'b0;
control_memwrite <= 1'b0;
control_alusrc <= 1'b0;
control_aluop <= 2'b10;
control_regwrite <= 1'b1;
end
11'b11001011000 : begin // SUB
control_mem2reg <= 1'b0;
control_memRead <= 1'b0;
control_memwrite <= 1'b0;
control_alusrc <= 1'b0;
control_aluop <= 2'b10;
control_regwrite <= 1'b1;
end
11'b10001010000 : begin // AND
control_mem2reg <= 1'b0;
control_memRead <= 1'b0;
control_memwrite <= 1'b0;
control_alusrc <= 1'b0;
control_aluop <= 2'b10;
control_regwrite <= 1'b1;
end
11'b10101010000 : begin // ORR
control_mem2reg <= 1'b0;
control_memRead <= 1'b0;
control_memwrite <= 1'b0;
control_alusrc <= 1'b0;
control_aluop <= 2'b10;
control_regwrite <= 1'b1;
end
default : begin // NOP
control_isZeroBranch <= 1'bx;
control_isUnconBranch <= 1'bx;
control_mem2reg <= 1'bx;
control_memRead <= 1'bx;
control_memwrite <= 1'bx;
control_alusrc <= 1'bx;
control_aluop <= 2'bxx;
control_regwrite <= 1'bx;
end
endcase
end
end
endmodule |
module ARM_CPU
(
input RESET,
input CLOCK,
input [31:0] IC,
input [63:0] mem_data_in,
output reg [63:0] PC,
output [63:0] mem_address_out,
output [63:0] mem_data_out,
output control_memwrite_out,
output control_memread_out
);
always @(posedge CLOCK) begin
if (PC === 64'bx) begin
PC <= 0;
end else if (PCSrc_wire == 1'b1) begin
PC <= jump_PC_wire;
end else begin
PC <= PC + 4;
end
//$display("Current = %0d | Jump = %0d | Natural Next = %0d", PC, jump_PC_wire, (PC + 4));
end
/* Stage : Instruction Fetch */
wire PCSrc_wire;
wire [63:0] jump_PC_wire;
wire [63:0] IFID_PC;
wire [31:0] IFID_IC;
IFID cache1 (CLOCK, PC, IC, IFID_PC, IFID_IC);
/* Stage : Instruction Decode */
wire [1:0] CONTROL_aluop; // EX
wire CONTROL_alusrc; // EX
wire CONTROL_isZeroBranch; // M
wire CONTROL_isUnconBranch; // M
wire CONTROL_memRead; // M
wire CONTROL_memwrite; // M
wire CONTROL_regwrite; // WB
wire CONTROL_mem2reg; // WB
ARM_Control unit1 (IFID_IC[31:21], CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUnconBranch, CONTROL_memRead, CONTROL_memwrite, CONTROL_regwrite, CONTROL_mem2reg);
wire [4:0] reg2_wire;
ID_Mux unit2(IFID_IC[20:16], IFID_IC[4:0], IFID_IC[28], reg2_wire);
wire [63:0] reg1_data, reg2_data;
wire MEMWB_regwrite;
wire [4:0] MEMWB_write_reg;
wire [63:0] write_reg_data;
Registers unit3(CLOCK, IFID_IC[9:5], reg2_wire, MEMWB_write_reg, write_reg_data, MEMWB_regwrite, reg1_data, reg2_data);
wire [63:0] sign_extend_wire;
SignExtend unit4 (IFID_IC, sign_extend_wire);
wire [1:0] IDEX_aluop;
wire IDEX_alusrc;
wire IDEX_isZeroBranch;
wire IDEX_isUnconBranch;
wire IDEX_memRead;
wire IDEX_memwrite;
wire IDEX_regwrite;
wire IDEX_mem2reg;
wire [63:0] IDEX_reg1_data;
wire [63:0] IDEX_reg2_data;
wire [63:0] IDEX_PC;
wire [63:0] IDEX_sign_extend;
wire [10:0] IDEX_alu_control;
wire [4:0] IDEX_write_reg;
IDEX cache2 (CLOCK, CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUnconBranch, CONTROL_memRead, CONTROL_memwrite, CONTROL_regwrite, CONTROL_mem2reg, IFID_PC, reg1_data, reg2_data, sign_extend_wire, IFID_IC[31:21], IFID_IC[4:0], IDEX_aluop, IDEX_alusrc, IDEX_isZeroBranch, IDEX_isUnconBranch, IDEX_memRead, IDEX_memwrite, IDEX_regwrite, IDEX_mem2reg, IDEX_PC, IDEX_reg1_data, IDEX_reg2_data, IDEX_sign_extend, IDEX_alu_control, IDEX_write_reg);
/* Stage : Execute */
wire [63:0] shift_left_wire;
wire [63:0] PC_jump;
wire jump_is_zero;
Shift_Left unit5 (IDEX_sign_extend, shift_left_wire);
ALU unit6 (IDEX_PC, shift_left_wire, 4'b0010, PC_jump, jump_is_zero);
wire [3:0] alu_main_control_wire;
wire [63:0] alu_data2_wire;
wire alu_main_is_zero;
wire [63:0] alu_main_result;
ALU_Control unit7(IDEX_aluop, IDEX_alu_control, alu_main_control_wire);
ALU_Mux mux3(IDEX_reg2_data, IDEX_sign_extend, IDEX_alusrc, alu_data2_wire);
ALU main_alu(IDEX_reg1_data, alu_data2_wire, alu_main_control_wire, alu_main_result, alu_main_is_zero);
wire EXMEM_isZeroBranch;
wire EXMEM_isUnconBranch;
wire EXMEM_regwrite;
wire EXMEM_mem2reg;
wire EXMEM_alu_zero;
wire [4:0] EXMEM_write_reg;
EXMEM cache3(CLOCK, IDEX_isZeroBranch, IDEX_isUnconBranch, IDEX_memRead, IDEX_memwrite, IDEX_regwrite, IDEX_mem2reg, PC_jump, alu_main_is_zero, alu_main_result, IDEX_reg2_data, IDEX_write_reg, EXMEM_isZeroBranch, EXMEM_isUnconBranch, control_memread_out, control_memwrite_out, EXMEM_regwrite, EXMEM_mem2reg, jump_PC_wire, EXMEM_alu_zero, mem_address_out, mem_data_out, EXMEM_write_reg);
/* Stage : Memory */
Branch unit8 (EXMEM_isUnconBranch, EXMEM_isZeroBranch, EXMEM_alu_zero, PCSrc_wire);
wire MEMWB_mem2reg;
wire [63:0] MEMWB_address;
wire [63:0] MEMWB_read_data;
MEMWB cache4(CLOCK, mem_address_out, mem_data_in, EXMEM_write_reg, EXMEM_regwrite, EXMEM_mem2reg, MEMWB_address, MEMWB_read_data, MEMWB_write_reg, MEMWB_regwrite, MEMWB_mem2reg);
/* Stage : Writeback */
WB_Mux unit9 (MEMWB_address, MEMWB_read_data, MEMWB_mem2reg, write_reg_data);
endmodule |
module IFID
(
input CLOCK,
input [63:0] PC_in,
input [31:0] IC_in,
output reg [63:0] PC_out,
output reg [31:0] IC_out
);
always @(negedge CLOCK) begin
PC_out <= PC_in;
IC_out <= IC_in;
end
endmodule |
module IC
(
input [63:0] PC_in,
output reg [31:0] instruction_out
);
reg [8:0] Data[63:0];
initial begin
// CBZ x31 #5 (Set PC = (5*4) = 20)
/*
Data[0] = 8'hb4;
Data[1] = 8'h00;
Data[2] = 8'h00;
Data[3] = 8'hbf;
/*
// B #1 (Set PC = (1*4) = 8)
/*
Data[0] = 8'h14;
Data[1] = 8'h00;
Data[2] = 8'h00;
Data[3] = 8'h01;
*/
// LDUR x2, [x9, #1]
Data[0] = 8'hf8;
Data[1] = 8'h40;
Data[2] = 8'h11;
Data[3] = 8'h22;
// ADD x3, x10, x5
Data[4] = 8'h8b;
Data[5] = 8'h05;
Data[6] = 8'h01;
Data[7] = 8'h43;
// SUB x4, x10, x5
Data[8] = 8'hcb;
Data[9] = 8'h05;
Data[10] = 8'h01;
Data[11] = 8'h44;
// ORR x5, x30, x10
Data[12] = 8'haa;
Data[13] = 8'h0a;
Data[14] = 8'h03;
Data[15] = 8'hc5;
// AND x6, x30, x10
Data[16] = 8'h8a;
Data[17] = 8'h0a;
Data[18] = 8'h03;
Data[19] = 8'hc6;
// STUR x2, [x31]
Data[20] = 8'hf8;
Data[21] = 8'h00;
Data[22] = 8'h03;
Data[23] = 8'he2;
end
always @(PC_in) begin
instruction_out[8:0] = Data[PC_in + 3];
instruction_out[16:8] = Data[PC_in + 2];
instruction_out[24:16] = Data[PC_in + 1];
instruction_out[31:24] = Data[PC_in];
end
endmodule |
module Data_Memory
(
input [63:0] inputAddress,
input [63:0] inputData,
input CONTROL_MemWrite,
input CONTROL_MemRead,
output reg [63:0] outputData
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
Data[initCount] = initCount * 100;
end
Data[10] = 1540;
Data[11] = 2117;
end
always @(*) begin
if (CONTROL_MemWrite == 1'b1) begin
Data[inputAddress] = inputData;
end else if (CONTROL_MemRead == 1'b1) begin
outputData = Data[inputAddress];
end else begin
outputData = 64'hxxxxxxxx;
end
// Debug use only
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
$display("RAM[%0d] = %0d", initCount, Data[initCount]);
end
end
endmodule |
module CPU_TEST;
/* Clock Signal */
reg CLOCK;
/* Wires to connect instruction memory to CPU */
wire [63:0] instructionPC;
wire [31:0] instructionOut;
/* Wires to connect registers to CPU */
wire [4:0] READ_REG_1;
wire [4:0] READ_REG_2;
wire [4:0] WRITE_REG;
wire [63:0] WRITE_DATA;
wire [63:0] DATA_OUT_1;
wire [63:0] DATA_OUT_2;
/* Wires to connect Data Memory to CPU */
wire [63:0] data_memory_out;
wire [63:0] ALU_Result_Out;
/* Wires to connect CPU Control Lines to Memories */
wire CONTROL_REG2LOC;
wire CONTROL_REGWRITE;
wire CONTROL_MEMREAD;
wire CONTROL_MEMWRITE;
wire CONTROL_BRANCH;
/* Instruction Memory Module */
Instruction_Memory mem1
(
instructionPC,
instructionOut
);
/* Registers Module */
Registers mem2
(
READ_REG_1,
READ_REG_2,
WRITE_REG,
WRITE_DATA,
CONTROL_REGWRITE,
DATA_OUT_1,
DATA_OUT_2
);
/* Data Memory Module */
Data_Memory mem3
(
ALU_Result_Out,
DATA_OUT_2,
CONTROL_MEMREAD,
CONTROL_MEMWRITE,
data_memory_out
);
/* CPU Module */
ARM_CPU core
(
.CLOCK(CLOCK),
.INSTRUCTION(instructionOut),
.PC(instructionPC),
.CONTROL_REG2LOC(CONTROL_REG2LOC),
.CONTROL_REGWRITE(CONTROL_REGWRITE),
.CONTROL_MEMREAD(CONTROL_MEMREAD),
.CONTROL_MEMWRITE(CONTROL_MEMWRITE),
.CONTROL_BRANCH(CONTROL_BRANCH),
.READ_REG_1(READ_REG_1),
.READ_REG_2(READ_REG_2),
.WRITE_REG(WRITE_REG),
.REG_DATA1(DATA_OUT_1),
.REG_DATA2(DATA_OUT_2),
.ALU_Result_Out(ALU_Result_Out),
.data_memory_out(data_memory_out),
.WRITE_REG_DATA(WRITE_DATA)
);
/* Setup the clock */
initial begin
CLOCK = 1'b0;
#30 $finish;
end
/* Toggle the clock */
always begin
#1 CLOCK = ~CLOCK;
end
endmodule |
module tri_st_add_csmux(
sum_0,
sum_1,
ci_b,
sum
);
input [0:7] sum_0; // after xor
input [0:7] sum_1;
input ci_b;
output [0:7] sum;
wire [0:7] sum0_b;
wire [0:7] sum1_b;
wire int_ci;
wire int_ci_t;
wire int_ci_b;
assign int_ci = (~ci_b);
assign int_ci_t = (~ci_b);
assign int_ci_b = (~int_ci_t);
assign sum0_b[0] = (~(sum_0[0] & int_ci_b));
assign sum0_b[1] = (~(sum_0[1] & int_ci_b));
assign sum0_b[2] = (~(sum_0[2] & int_ci_b));
assign sum0_b[3] = (~(sum_0[3] & int_ci_b));
assign sum0_b[4] = (~(sum_0[4] & int_ci_b));
assign sum0_b[5] = (~(sum_0[5] & int_ci_b));
assign sum0_b[6] = (~(sum_0[6] & int_ci_b));
assign sum0_b[7] = (~(sum_0[7] & int_ci_b));
assign sum1_b[0] = (~(sum_1[0] & int_ci));
assign sum1_b[1] = (~(sum_1[1] & int_ci));
assign sum1_b[2] = (~(sum_1[2] & int_ci));
assign sum1_b[3] = (~(sum_1[3] & int_ci));
assign sum1_b[4] = (~(sum_1[4] & int_ci));
assign sum1_b[5] = (~(sum_1[5] & int_ci));
assign sum1_b[6] = (~(sum_1[6] & int_ci));
assign sum1_b[7] = (~(sum_1[7] & int_ci));
assign sum[0] = (~(sum0_b[0] & sum1_b[0]));
assign sum[1] = (~(sum0_b[1] & sum1_b[1]));
assign sum[2] = (~(sum0_b[2] & sum1_b[2]));
assign sum[3] = (~(sum0_b[3] & sum1_b[3]));
assign sum[4] = (~(sum0_b[4] & sum1_b[4]));
assign sum[5] = (~(sum0_b[5] & sum1_b[5]));
assign sum[6] = (~(sum0_b[6] & sum1_b[6]));
assign sum[7] = (~(sum0_b[7] & sum1_b[7]));
endmodule |
module tri_rot16_ru(
opsize,
le,
le_rotate_sel,
be_rotate_sel,
arr_data,
stq7_byp_val,
stq_byp_val,
stq7_rmw_data,
stq8_rmw_data,
data_latched,
data_rot,
nclk,
vdd,
gnd,
delay_lclkr_dc,
mpw1_dc_b,
mpw2_dc_b,
func_sl_force,
func_sl_thold_0_b,
sg_0,
act,
scan_in,
scan_out
);
input [0:4] opsize; // (0)16B (1)8B (2)4B (3)2B (4)1B
input le;
input [0:3] le_rotate_sel;
input [0:3] be_rotate_sel;
input [0:15] arr_data; // data to rotate
input stq7_byp_val;
input stq_byp_val;
input [0:15] stq7_rmw_data;
input [0:15] stq8_rmw_data;
output [0:15] data_latched; // latched data, not rotated
output [0:15] data_rot; // rotated data out
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
input [0:`NCLK_WIDTH-1] nclk;
inout vdd;
inout gnd;
input delay_lclkr_dc;
input mpw1_dc_b;
input mpw2_dc_b;
input func_sl_force;
input func_sl_thold_0_b;
input sg_0;
input act;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out;
// tri_rot16_ru
wire my_d1clk;
wire my_d2clk;
wire [0:`NCLK_WIDTH-1] my_lclk;
wire [0:15] data_latched_b;
//signal bele_gp0_q_b, bele_gp0_q, bele_gp0_din :std_ulogic_vector(0 to 1);
wire [0:0] bele_gp0_q_b;
wire [0:0] bele_gp0_q;
wire [0:0] bele_gp0_din;
wire [0:3] be_shx04_gp0_q_b;
wire [0:3] be_shx04_gp0_q;
wire [0:3] be_shx04_gp0_din;
wire [0:3] le_shx04_gp0_q_b;
wire [0:3] le_shx04_gp0_q;
wire [0:3] le_shx04_gp0_din;
wire [0:3] be_shx01_gp0_q_b;
wire [0:3] be_shx01_gp0_q;
wire [0:3] be_shx01_gp0_din;
wire [0:3] le_shx01_gp0_q_b;
wire [0:3] le_shx01_gp0_q;
wire [0:3] le_shx01_gp0_din;
wire [0:4] mask_q_b;
wire [0:4] mask_q;
wire [0:4] mask_din;
wire [0:15] mxbele_b;
wire [0:15] mxbele;
wire [0:15] mx1_0_b;
wire [0:15] mx1_1_b;
wire [0:15] mx1;
wire [0:15] mx2_0_b;
wire [0:15] mx2_1_b;
wire [0:15] mx2;
wire [0:15] do_b;
wire [0:15] mxbele_d0;
wire [0:15] mxbele_d1;
wire [0:15] bele_s0;
wire [0:15] bele_s1;
wire [0:3] shx04_gp0_sel_b;
wire [0:3] shx04_gp0_sel;
wire [0:3] shx01_gp0_sel_b;
wire [0:3] shx01_gp0_sel;
wire [0:15] mx1_d0;
wire [0:15] mx1_d1;
wire [0:15] mx1_d2;
wire [0:15] mx1_d3;
wire [0:15] mx2_d0;
wire [0:15] mx2_d1;
wire [0:15] mx2_d2;
wire [0:15] mx2_d3;
wire [0:15] mx1_s0;
wire [0:15] mx1_s1;
wire [0:15] mx1_s2;
wire [0:15] mx1_s3;
wire [0:15] mx2_s0;
wire [0:15] mx2_s1;
wire [0:15] mx2_s2;
wire [0:15] mx2_s3;
wire [0:15] mask_en;
wire [0:3] be_shx04_sel;
wire [0:3] be_shx01_sel;
wire [0:3] le_shx04_sel;
wire [0:3] le_shx01_sel;
wire [0:15] stq_byp_data;
wire [0:15] rotate_data;
//--------------------------
// constants
//--------------------------
parameter bele_gp0_din_offset = 0;
parameter be_shx04_gp0_din_offset = bele_gp0_din_offset + 1;
parameter le_shx04_gp0_din_offset = be_shx04_gp0_din_offset + 4;
parameter be_shx01_gp0_din_offset = le_shx04_gp0_din_offset + 4;
parameter le_shx01_gp0_din_offset = be_shx01_gp0_din_offset + 4;
parameter mask_din_offset = le_shx01_gp0_din_offset + 4;
parameter scan_right = mask_din_offset + 5 - 1;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
// #############################################################################################
// Little Endian Rotate Support
// Optype2 Optype4 Optype8
// B31 => rot_data(248:255)
// B30 => rot_data(240:247)
// B29 => rot_data(232:239)
// B28 => rot_data(224:231)
// B31 => rot_data(248:255) B27 => rot_data(216:223)
// B30 => rot_data(240:247) B26 => rot_data(208:215)
// B15 => rot_data(248:255) B29 => rot_data(232:239) B25 => rot_data(200:207)
// B14 => rot_data(240:247) B28 => rot_data(224:231) B24 => rot_data(192:199)
//
// Optype16
// B31 => rot_data(248:255) B23 => rot_data(184:191)
// B30 => rot_data(240:247) B22 => rot_data(176:183)
// B29 => rot_data(232:239) B21 => rot_data(168:175)
// B28 => rot_data(224:231) B20 => rot_data(160:167)
// B27 => rot_data(216:223) B19 => rot_data(152:159)
// B26 => rot_data(208:215) B18 => rot_data(144:151)
// B25 => rot_data(200:207) B17 => rot_data(136:143)
// B24 => rot_data(192:199) B16 => rot_data(128:135)
//
// #############################################################################################
//-- 0,1,2,3 byte rotation
//with rot_sel(2 to 3) select
// rot3210 <= rot_data(104 to 127) & rot_data(0 to 103) when "11",
// rot_data(112 to 127) & rot_data(0 to 111) when "10",
// rot_data(120 to 127) & rot_data(0 to 119) when "01",
// rot_data(0 to 127) when others;
//
//-- 0-3,4,8,12 byte rotation
//with rot_sel(0 to 1) select
// rotC840 <= rot3210(32 to 127) & rot3210(0 to 31) when "11",
// rot3210(64 to 127) & rot3210(0 to 63) when "10",
// rot3210(96 to 127) & rot3210(0 to 95) when "01",
// rot3210(0 to 127) when others;
// ######################################################################
// ## BEFORE ROTATE CYCLE
// ######################################################################
// Rotate Control
// ----------------------------------
assign be_shx04_sel[0] = (~be_rotate_sel[0]) & (~be_rotate_sel[1]);
assign be_shx04_sel[1] = (~be_rotate_sel[0]) & be_rotate_sel[1];
assign be_shx04_sel[2] = be_rotate_sel[0] & (~be_rotate_sel[1]);
assign be_shx04_sel[3] = be_rotate_sel[0] & be_rotate_sel[1];
assign be_shx01_sel[0] = (~be_rotate_sel[2]) & (~be_rotate_sel[3]);
assign be_shx01_sel[1] = (~be_rotate_sel[2]) & be_rotate_sel[3];
assign be_shx01_sel[2] = be_rotate_sel[2] & (~be_rotate_sel[3]);
assign be_shx01_sel[3] = be_rotate_sel[2] & be_rotate_sel[3];
assign le_shx04_sel[0] = (~le_rotate_sel[0]) & (~le_rotate_sel[1]);
assign le_shx04_sel[1] = (~le_rotate_sel[0]) & le_rotate_sel[1];
assign le_shx04_sel[2] = le_rotate_sel[0] & (~le_rotate_sel[1]);
assign le_shx04_sel[3] = le_rotate_sel[0] & le_rotate_sel[1];
assign le_shx01_sel[0] = (~le_rotate_sel[2]) & (~le_rotate_sel[3]);
assign le_shx01_sel[1] = (~le_rotate_sel[2]) & le_rotate_sel[3];
assign le_shx01_sel[2] = le_rotate_sel[2] & (~le_rotate_sel[3]);
assign le_shx01_sel[3] = le_rotate_sel[2] & le_rotate_sel[3];
// Opsize Mask Generation
// ----------------------------------
assign mask_din[0] = opsize[0]; // for 16:23
assign mask_din[1] = opsize[0] | opsize[1]; // for 24:27
assign mask_din[2] = opsize[0] | opsize[1] | opsize[2]; // for 28:29
assign mask_din[3] = opsize[0] | opsize[1] | opsize[2] | opsize[3]; // for 30
assign mask_din[4] = opsize[0] | opsize[1] | opsize[2] | opsize[3] | opsize[4]; // for 31
// Latch Inputs
// ----------------------------------
assign bele_gp0_din[0] = le;
assign be_shx04_gp0_din[0:3] = be_shx04_sel[0:3];
assign le_shx04_gp0_din[0:3] = le_shx04_sel[0:3];
assign be_shx01_gp0_din[0:3] = be_shx01_sel[0:3];
assign le_shx01_gp0_din[0:3] = le_shx01_sel[0:3];
// ######################################################################
// ## BIG-ENDIAN ROTATE CYCLE
// ######################################################################
// -------------------------------------------------------------------
// local latch inputs
// -------------------------------------------------------------------
tri_inv bele_gp0_q_0 (.y(bele_gp0_q), .a(bele_gp0_q_b));
tri_inv #(.WIDTH(4)) be_shx04_gp0_q_0 (.y(be_shx04_gp0_q[0:3]), .a(be_shx04_gp0_q_b[0:3]));
tri_inv #(.WIDTH(4)) le_shx04_gp0_q_0 (.y(le_shx04_gp0_q[0:3]), .a(le_shx04_gp0_q_b[0:3]));
tri_inv #(.WIDTH(4)) be_shx01_gp0_q_0 (.y(be_shx01_gp0_q[0:3]), .a(be_shx01_gp0_q_b[0:3]));
tri_inv #(.WIDTH(4)) le_shx01_gp0_q_0 (.y(le_shx01_gp0_q[0:3]), .a(le_shx01_gp0_q_b[0:3]));
assign mask_q[0:4] = (~mask_q_b[0:4]);
// ----------------------------------------------------------------------------------------
// Read-Modify-Write Bypass Data Muxing
// ----------------------------------------------------------------------------------------
assign stq_byp_data = ({16{stq7_byp_val}} & stq7_rmw_data) | ({16{~stq7_byp_val}} & stq8_rmw_data);
assign rotate_data = ({16{stq_byp_val}} & stq_byp_data) | ({16{~stq_byp_val}} & arr_data);
// ----------------------------------------------------------------------------------------
// Little/Big Endian Muxing
// ----------------------------------------------------------------------------------------
assign bele_s0[0:15] = {16{~bele_gp0_q[0]}};
assign bele_s1[0:15] = {16{ bele_gp0_q[0]}};
tri_aoi22 #(.WIDTH(4)) shx04_gp0_sel_b_0 (.y(shx04_gp0_sel_b[0:3]), .a0(be_shx04_gp0_q[0:3]), .a1(bele_s0[0:3]), .b0(le_shx04_gp0_q[0:3]), .b1(bele_s1[0:3]));
tri_aoi22 #(.WIDTH(4)) shx01_gp0_sel_b_0 (.y(shx01_gp0_sel_b[0:3]), .a0(be_shx01_gp0_q[0:3]), .a1(bele_s0[4:7]), .b0(le_shx01_gp0_q[0:3]), .b1(bele_s1[4:7]));
assign shx04_gp0_sel = (~shx04_gp0_sel_b);
assign shx01_gp0_sel = (~shx01_gp0_sel_b);
assign mxbele_d0[0] = rotate_data[0]; assign mxbele_d1[0] = rotate_data[15];
assign mxbele_d0[1] = rotate_data[1]; assign mxbele_d1[1] = rotate_data[14];
assign mxbele_d0[2] = rotate_data[2]; assign mxbele_d1[2] = rotate_data[13];
assign mxbele_d0[3] = rotate_data[3]; assign mxbele_d1[3] = rotate_data[12];
assign mxbele_d0[4] = rotate_data[4]; assign mxbele_d1[4] = rotate_data[11];
assign mxbele_d0[5] = rotate_data[5]; assign mxbele_d1[5] = rotate_data[10];
assign mxbele_d0[6] = rotate_data[6]; assign mxbele_d1[6] = rotate_data[9];
assign mxbele_d0[7] = rotate_data[7]; assign mxbele_d1[7] = rotate_data[8];
assign mxbele_d0[8] = rotate_data[8]; assign mxbele_d1[8] = rotate_data[7];
assign mxbele_d0[9] = rotate_data[9]; assign mxbele_d1[9] = rotate_data[6];
assign mxbele_d0[10] = rotate_data[10]; assign mxbele_d1[10] = rotate_data[5];
assign mxbele_d0[11] = rotate_data[11]; assign mxbele_d1[11] = rotate_data[4];
assign mxbele_d0[12] = rotate_data[12]; assign mxbele_d1[12] = rotate_data[3];
assign mxbele_d0[13] = rotate_data[13]; assign mxbele_d1[13] = rotate_data[2];
assign mxbele_d0[14] = rotate_data[14]; assign mxbele_d1[14] = rotate_data[1];
assign mxbele_d0[15] = rotate_data[15]; assign mxbele_d1[15] = rotate_data[0];
tri_aoi22 #(.WIDTH(16)) mxbele_b_0 (.y(mxbele_b[0:15]), .a0(mxbele_d0[0:15]), .a1(bele_s0[0:15]), .b0(mxbele_d1[0:15]), .b1(bele_s1[0:15]));
tri_inv #(.WIDTH(16)) mxbele_0 (.y(mxbele[0:15]), .a(mxbele_b[0:15]));
// ----------------------------------------------------------------------------------------
// First level of muxing <0,4,8,12 bytes>
// ----------------------------------------------------------------------------------------
assign mx1_s0[0:15] = {16{shx04_gp0_sel[0]}};
assign mx1_s1[0:15] = {16{shx04_gp0_sel[1]}};
assign mx1_s2[0:15] = {16{shx04_gp0_sel[2]}};
assign mx1_s3[0:15] = {16{shx04_gp0_sel[3]}};
assign mx1_d0[0] = mxbele[0]; assign mx1_d1[0] = mxbele[12]; assign mx1_d2[0] = mxbele[8]; assign mx1_d3[0] = mxbele[4];
assign mx1_d0[1] = mxbele[1]; assign mx1_d1[1] = mxbele[13]; assign mx1_d2[1] = mxbele[9]; assign mx1_d3[1] = mxbele[5];
assign mx1_d0[2] = mxbele[2]; assign mx1_d1[2] = mxbele[14]; assign mx1_d2[2] = mxbele[10]; assign mx1_d3[2] = mxbele[6];
assign mx1_d0[3] = mxbele[3]; assign mx1_d1[3] = mxbele[15]; assign mx1_d2[3] = mxbele[11]; assign mx1_d3[3] = mxbele[7];
assign mx1_d0[4] = mxbele[4]; assign mx1_d1[4] = mxbele[0]; assign mx1_d2[4] = mxbele[12]; assign mx1_d3[4] = mxbele[8];
assign mx1_d0[5] = mxbele[5]; assign mx1_d1[5] = mxbele[1]; assign mx1_d2[5] = mxbele[13]; assign mx1_d3[5] = mxbele[9];
assign mx1_d0[6] = mxbele[6]; assign mx1_d1[6] = mxbele[2]; assign mx1_d2[6] = mxbele[14]; assign mx1_d3[6] = mxbele[10];
assign mx1_d0[7] = mxbele[7]; assign mx1_d1[7] = mxbele[3]; assign mx1_d2[7] = mxbele[15]; assign mx1_d3[7] = mxbele[11];
assign mx1_d0[8] = mxbele[8]; assign mx1_d1[8] = mxbele[4]; assign mx1_d2[8] = mxbele[0]; assign mx1_d3[8] = mxbele[12];
assign mx1_d0[9] = mxbele[9]; assign mx1_d1[9] = mxbele[5]; assign mx1_d2[9] = mxbele[1]; assign mx1_d3[9] = mxbele[13];
assign mx1_d0[10] = mxbele[10]; assign mx1_d1[10] = mxbele[6]; assign mx1_d2[10] = mxbele[2]; assign mx1_d3[10] = mxbele[14];
assign mx1_d0[11] = mxbele[11]; assign mx1_d1[11] = mxbele[7]; assign mx1_d2[11] = mxbele[3]; assign mx1_d3[11] = mxbele[15];
assign mx1_d0[12] = mxbele[12]; assign mx1_d1[12] = mxbele[8]; assign mx1_d2[12] = mxbele[4]; assign mx1_d3[12] = mxbele[0];
assign mx1_d0[13] = mxbele[13]; assign mx1_d1[13] = mxbele[9]; assign mx1_d2[13] = mxbele[5]; assign mx1_d3[13] = mxbele[1];
assign mx1_d0[14] = mxbele[14]; assign mx1_d1[14] = mxbele[10]; assign mx1_d2[14] = mxbele[6]; assign mx1_d3[14] = mxbele[2];
assign mx1_d0[15] = mxbele[15]; assign mx1_d1[15] = mxbele[11]; assign mx1_d2[15] = mxbele[7]; assign mx1_d3[15] = mxbele[3];
tri_aoi22 #(.WIDTH(16)) mx1_0_b_0 (.y(mx1_0_b[0:15]), .a0(mx1_s0[0:15]), .a1(mx1_d0[0:15]), .b0(mx1_s1[0:15]), .b1(mx1_d1[0:15]));
tri_aoi22 #(.WIDTH(16)) mx1_1_b_0 (.y(mx1_1_b[0:15]), .a0(mx1_s2[0:15]), .a1(mx1_d2[0:15]), .b0(mx1_s3[0:15]), .b1(mx1_d3[0:15]));
tri_nand2 #(.WIDTH(16)) mx1_0 (.y(mx1[0:15]), .a(mx1_0_b[0:15]), .b(mx1_1_b[0:15]));
// ----------------------------------------------------------------------------------------
// third level of muxing <0,1,2,3 bytes> , include mask on selects
// ----------------------------------------------------------------------------------------
assign mask_en[0:7] = {8{mask_q[0]}}; // 128
assign mask_en[8:11] = {4{mask_q[1]}}; // 128,64
assign mask_en[12:13] = {2{mask_q[2]}}; // 128,64,32
assign mask_en[14] = mask_q[3]; // 128,64,32,16
assign mask_en[15] = mask_q[4]; // 128,64,32,16,8 <not sure you really need this one>
assign mx2_s0[0:7] = {8{shx01_gp0_sel[0]}} & mask_en[0:7];
assign mx2_s1[0:7] = {8{shx01_gp0_sel[1]}} & mask_en[0:7];
assign mx2_s2[0:7] = {8{shx01_gp0_sel[2]}} & mask_en[0:7];
assign mx2_s3[0:7] = {8{shx01_gp0_sel[3]}} & mask_en[0:7];
assign mx2_s0[8:15] = {8{shx01_gp0_sel[0]}} & mask_en[8:15];
assign mx2_s1[8:15] = {8{shx01_gp0_sel[1]}} & mask_en[8:15];
assign mx2_s2[8:15] = {8{shx01_gp0_sel[2]}} & mask_en[8:15];
assign mx2_s3[8:15] = {8{shx01_gp0_sel[3]}} & mask_en[8:15];
assign mx2_d0[0] = mx1[0]; assign mx2_d1[0] = mx1[15]; assign mx2_d2[0] = mx1[14]; assign mx2_d3[0] = mx1[13];
assign mx2_d0[1] = mx1[1]; assign mx2_d1[1] = mx1[0]; assign mx2_d2[1] = mx1[15]; assign mx2_d3[1] = mx1[14];
assign mx2_d0[2] = mx1[2]; assign mx2_d1[2] = mx1[1]; assign mx2_d2[2] = mx1[0]; assign mx2_d3[2] = mx1[15];
assign mx2_d0[3] = mx1[3]; assign mx2_d1[3] = mx1[2]; assign mx2_d2[3] = mx1[1]; assign mx2_d3[3] = mx1[0];
assign mx2_d0[4] = mx1[4]; assign mx2_d1[4] = mx1[3]; assign mx2_d2[4] = mx1[2]; assign mx2_d3[4] = mx1[1];
assign mx2_d0[5] = mx1[5]; assign mx2_d1[5] = mx1[4]; assign mx2_d2[5] = mx1[3]; assign mx2_d3[5] = mx1[2];
assign mx2_d0[6] = mx1[6]; assign mx2_d1[6] = mx1[5]; assign mx2_d2[6] = mx1[4]; assign mx2_d3[6] = mx1[3];
assign mx2_d0[7] = mx1[7]; assign mx2_d1[7] = mx1[6]; assign mx2_d2[7] = mx1[5]; assign mx2_d3[7] = mx1[4];
assign mx2_d0[8] = mx1[8]; assign mx2_d1[8] = mx1[7]; assign mx2_d2[8] = mx1[6]; assign mx2_d3[8] = mx1[5];
assign mx2_d0[9] = mx1[9]; assign mx2_d1[9] = mx1[8]; assign mx2_d2[9] = mx1[7]; assign mx2_d3[9] = mx1[6];
assign mx2_d0[10] = mx1[10]; assign mx2_d1[10] = mx1[9]; assign mx2_d2[10] = mx1[8]; assign mx2_d3[10] = mx1[7];
assign mx2_d0[11] = mx1[11]; assign mx2_d1[11] = mx1[10]; assign mx2_d2[11] = mx1[9]; assign mx2_d3[11] = mx1[8];
assign mx2_d0[12] = mx1[12]; assign mx2_d1[12] = mx1[11]; assign mx2_d2[12] = mx1[10]; assign mx2_d3[12] = mx1[9];
assign mx2_d0[13] = mx1[13]; assign mx2_d1[13] = mx1[12]; assign mx2_d2[13] = mx1[11]; assign mx2_d3[13] = mx1[10];
assign mx2_d0[14] = mx1[14]; assign mx2_d1[14] = mx1[13]; assign mx2_d2[14] = mx1[12]; assign mx2_d3[14] = mx1[11];
assign mx2_d0[15] = mx1[15]; assign mx2_d1[15] = mx1[14]; assign mx2_d2[15] = mx1[13]; assign mx2_d3[15] = mx1[12];
tri_aoi22 #(.WIDTH(16)) mx2_0_b_0 (.y(mx2_0_b[0:15]), .a0(mx2_s0[0:15]), .a1(mx2_d0[0:15]), .b0(mx2_s1[0:15]), .b1(mx2_d1[0:15]));
tri_aoi22 #(.WIDTH(16)) mx2_1_b_0 (.y(mx2_1_b[0:15]), .a0(mx2_s2[0:15]), .a1(mx2_d2[0:15]), .b0(mx2_s3[0:15]), .b1(mx2_d3[0:15]));
tri_nand2 #(.WIDTH(16)) mx2_0 (.y(mx2[0:15]), .a(mx2_0_b[0:15]), .b(mx2_1_b[0:15]));
tri_inv #(.WIDTH(16)) do_b_0 (.y(do_b[0:15]), .a(mx2[0:15]));
tri_inv #(.WIDTH(16)) data_rot_0 (.y(data_rot[0:15]), .a(do_b[0:15]));
tri_inv #(.WIDTH(16)) data_latched_b_0 (.y(data_latched_b), .a(arr_data));
tri_inv #(.WIDTH(16)) data_latched_0 (.y(data_latched), .a(data_latched_b));
// top funny physical placement to minimize wrap wires ... also nice for LE adjust
//---------
// 0 31
// 1 30
// 2 29
// 3 28
// 4 27
// 5 26
// 6 25
// 7 24
//---------
// 8 23
// 9 22
// 10 21
// 11 20
// 12 19
// 13 18
// 14 17
// 15 16
//---------
// bot
// ###############################################################
// ## LCBs
// ###############################################################
tri_lcbnd my_lcb(
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.force_t(func_sl_force),
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(act),
.sg(sg_0),
.thold_b(func_sl_thold_0_b),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.lclk(my_lclk)
);
// ###############################################################
// ## Latches
// ###############################################################
tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) bele_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]),
.scanout(sov[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]),
.d(bele_gp0_din),
.qb(bele_gp0_q_b)
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]),
.scanout(sov[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]),
.d(be_shx04_gp0_din),
.qb(be_shx04_gp0_q_b[0:3])
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]),
.scanout(sov[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]),
.d(le_shx04_gp0_din),
.qb(le_shx04_gp0_q_b[0:3])
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]),
.scanout(sov[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]),
.d(be_shx01_gp0_din),
.qb(be_shx01_gp0_q_b[0:3])
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]),
.scanout(sov[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]),
.d(le_shx01_gp0_din),
.qb(le_shx01_gp0_q_b[0:3])
);
tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) mask_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[mask_din_offset:mask_din_offset + 5 - 1]),
.scanout(sov[mask_din_offset:mask_din_offset + 5 - 1]),
.d(mask_din),
.qb(mask_q_b[0:4])
);
assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
assign scan_out = sov[0];
endmodule |
module tri_debug_mux32(
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
dbg_group4,
dbg_group5,
dbg_group6,
dbg_group7,
dbg_group8,
dbg_group9,
dbg_group10,
dbg_group11,
dbg_group12,
dbg_group13,
dbg_group14,
dbg_group15,
dbg_group16,
dbg_group17,
dbg_group18,
dbg_group19,
dbg_group20,
dbg_group21,
dbg_group22,
dbg_group23,
dbg_group24,
dbg_group25,
dbg_group26,
dbg_group27,
dbg_group28,
dbg_group29,
dbg_group30,
dbg_group31,
trace_data_in,
trace_data_out,
// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);
// Include model build parameters
parameter DBG_WIDTH = 32; // A2o=32; A2i=88
//=====================================================================
// Port Definitions
//=====================================================================
input [0:10] select_bits;
input [0:DBG_WIDTH-1] dbg_group0;
input [0:DBG_WIDTH-1] dbg_group1;
input [0:DBG_WIDTH-1] dbg_group2;
input [0:DBG_WIDTH-1] dbg_group3;
input [0:DBG_WIDTH-1] dbg_group4;
input [0:DBG_WIDTH-1] dbg_group5;
input [0:DBG_WIDTH-1] dbg_group6;
input [0:DBG_WIDTH-1] dbg_group7;
input [0:DBG_WIDTH-1] dbg_group8;
input [0:DBG_WIDTH-1] dbg_group9;
input [0:DBG_WIDTH-1] dbg_group10;
input [0:DBG_WIDTH-1] dbg_group11;
input [0:DBG_WIDTH-1] dbg_group12;
input [0:DBG_WIDTH-1] dbg_group13;
input [0:DBG_WIDTH-1] dbg_group14;
input [0:DBG_WIDTH-1] dbg_group15;
input [0:DBG_WIDTH-1] dbg_group16;
input [0:DBG_WIDTH-1] dbg_group17;
input [0:DBG_WIDTH-1] dbg_group18;
input [0:DBG_WIDTH-1] dbg_group19;
input [0:DBG_WIDTH-1] dbg_group20;
input [0:DBG_WIDTH-1] dbg_group21;
input [0:DBG_WIDTH-1] dbg_group22;
input [0:DBG_WIDTH-1] dbg_group23;
input [0:DBG_WIDTH-1] dbg_group24;
input [0:DBG_WIDTH-1] dbg_group25;
input [0:DBG_WIDTH-1] dbg_group26;
input [0:DBG_WIDTH-1] dbg_group27;
input [0:DBG_WIDTH-1] dbg_group28;
input [0:DBG_WIDTH-1] dbg_group29;
input [0:DBG_WIDTH-1] dbg_group30;
input [0:DBG_WIDTH-1] dbg_group31;
input [0:DBG_WIDTH-1] trace_data_in;
output [0:DBG_WIDTH-1] trace_data_out;
// Instruction Trace (HTM) Control Signals:
// 0 - ac_an_coretrace_first_valid
// 1 - ac_an_coretrace_valid
// 2:3 - ac_an_coretrace_type[0:1]
input [0:3] coretrace_ctrls_in;
output [0:3] coretrace_ctrls_out;
//=====================================================================
// Signal Declarations / Misc
//=====================================================================
parameter DBG_1FOURTH = DBG_WIDTH/4;
parameter DBG_2FOURTH = DBG_WIDTH/2;
parameter DBG_3FOURTH = 3 * DBG_WIDTH/4;
wire [0:DBG_WIDTH-1] debug_grp_selected;
wire [0:DBG_WIDTH-1] debug_grp_rotated;
// Instruction Trace controls are passed-through:
assign coretrace_ctrls_out = coretrace_ctrls_in ;
//=====================================================================
// Mux Function
//=====================================================================
// Debug Mux
assign debug_grp_selected = (select_bits[0:4] == 5'b00000) ? dbg_group0 :
(select_bits[0:4] == 5'b00001) ? dbg_group1 :
(select_bits[0:4] == 5'b00010) ? dbg_group2 :
(select_bits[0:4] == 5'b00011) ? dbg_group3 :
(select_bits[0:4] == 5'b00100) ? dbg_group4 :
(select_bits[0:4] == 5'b00101) ? dbg_group5 :
(select_bits[0:4] == 5'b00110) ? dbg_group6 :
(select_bits[0:4] == 5'b00111) ? dbg_group7 :
(select_bits[0:4] == 5'b01000) ? dbg_group8 :
(select_bits[0:4] == 5'b01001) ? dbg_group9 :
(select_bits[0:4] == 5'b01010) ? dbg_group10 :
(select_bits[0:4] == 5'b01011) ? dbg_group11 :
(select_bits[0:4] == 5'b01100) ? dbg_group12 :
(select_bits[0:4] == 5'b01101) ? dbg_group13 :
(select_bits[0:4] == 5'b01110) ? dbg_group14 :
(select_bits[0:4] == 5'b01111) ? dbg_group15 :
(select_bits[0:4] == 5'b10000) ? dbg_group16 :
(select_bits[0:4] == 5'b10001) ? dbg_group17 :
(select_bits[0:4] == 5'b10010) ? dbg_group18 :
(select_bits[0:4] == 5'b10011) ? dbg_group19 :
(select_bits[0:4] == 5'b10100) ? dbg_group20 :
(select_bits[0:4] == 5'b10101) ? dbg_group21 :
(select_bits[0:4] == 5'b10110) ? dbg_group22 :
(select_bits[0:4] == 5'b10111) ? dbg_group23 :
(select_bits[0:4] == 5'b11000) ? dbg_group24 :
(select_bits[0:4] == 5'b11001) ? dbg_group25 :
(select_bits[0:4] == 5'b11010) ? dbg_group26 :
(select_bits[0:4] == 5'b11011) ? dbg_group27 :
(select_bits[0:4] == 5'b11100) ? dbg_group28 :
(select_bits[0:4] == 5'b11101) ? dbg_group29 :
(select_bits[0:4] == 5'b11110) ? dbg_group30 :
dbg_group31;
assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
debug_grp_selected[0:DBG_WIDTH - 1];
assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
debug_grp_rotated[0:DBG_1FOURTH - 1];
assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
endmodule |
module tri_st_cntlz_8b(
a,
y,
z_b
);
input [0:7] a;
output [0:2] y;
output z_b;
wire [0:7] a0;
wire [0:7] a1;
wire [0:7] a2;
wire [0:6] ax;
assign a0[1:7] = ~( a[0:6] | a[1:7]);
assign a1[2:7] = ~(a0[0:5] & a0[2:7]);
assign a2[4:7] = ~(a1[0:3] | a1[4:7]);
assign a0[0:0] = (~a[0:0]);
assign a1[0:1] = (~a0[0:1]);
assign a2[0:3] = (~a1[0:3]);
assign ax[0:6] = ~(a2[0:6] & a[1:7]);
assign z_b = (~a2[7]);
assign y[0] = ~(ax[3] & ax[4]) | ~(ax[5] & ax[6]);
assign y[1] = ~(ax[1] & ax[2]) | ~(ax[5] & ax[6]);
assign y[2] = ~(ax[0] & ax[2]) | ~(ax[4] & ax[6]);
endmodule |
module tri_lq_rmw(
ex2_stq4_rd_stg_act,
ex2_stq4_rd_addr,
stq6_rd_data_wa,
stq6_rd_data_wb,
stq6_rd_data_wc,
stq6_rd_data_wd,
stq6_rd_data_we,
stq6_rd_data_wf,
stq6_rd_data_wg,
stq6_rd_data_wh,
stq5_stg_act,
stq5_arr_wren,
stq5_arr_wr_way,
stq5_arr_wr_addr,
stq5_arr_wr_bytew,
stq5_arr_wr_data,
stq7_byp_val_wabcd,
stq7_byp_val_wefgh,
stq7_byp_data_wabcd,
stq7_byp_data_wefgh,
stq8_byp_data_wabcd,
stq8_byp_data_wefgh,
stq_byp_val_wabcd,
stq_byp_val_wefgh,
dcarr_rd_stg_act,
dcarr_wr_stg_act,
dcarr_wr_way,
dcarr_wr_addr,
dcarr_wr_data_wabcd,
dcarr_wr_data_wefgh,
nclk,
vdd,
gnd,
d_mode_dc,
delay_lclkr_dc,
mpw1_dc_b,
mpw2_dc_b,
func_sl_force,
func_sl_thold_0_b,
sg_0,
scan_in,
scan_out
);
// EX2/STQ4 Read Operation
input ex2_stq4_rd_stg_act;
input [52:59] ex2_stq4_rd_addr;
// Read data for Read-Modify-Write
input [0:143] stq6_rd_data_wa;
input [0:143] stq6_rd_data_wb;
input [0:143] stq6_rd_data_wc;
input [0:143] stq6_rd_data_wd;
input [0:143] stq6_rd_data_we;
input [0:143] stq6_rd_data_wf;
input [0:143] stq6_rd_data_wg;
input [0:143] stq6_rd_data_wh;
// Write Data for Read-Modify-Write
input stq5_stg_act;
input stq5_arr_wren;
input [0:7] stq5_arr_wr_way;
input [52:59] stq5_arr_wr_addr;
input [0:15] stq5_arr_wr_bytew;
input [0:143] stq5_arr_wr_data;
// EX4 Load Bypass Data for Read/Write Collision detected in EX2
output [0:3] stq7_byp_val_wabcd;
output [0:3] stq7_byp_val_wefgh;
output [0:143] stq7_byp_data_wabcd;
output [0:143] stq7_byp_data_wefgh;
output [0:143] stq8_byp_data_wabcd;
output [0:143] stq8_byp_data_wefgh;
output [0:3] stq_byp_val_wabcd;
output [0:3] stq_byp_val_wefgh;
// Data Cache Array Write
output [0:7] dcarr_rd_stg_act;
output [0:7] dcarr_wr_stg_act;
output [0:7] dcarr_wr_way;
output [52:59] dcarr_wr_addr;
output [0:143] dcarr_wr_data_wabcd;
output [0:143] dcarr_wr_data_wefgh;
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
input [0:`NCLK_WIDTH-1] nclk;
inout vdd;
inout gnd;
input d_mode_dc;
input delay_lclkr_dc;
input mpw1_dc_b;
input mpw2_dc_b;
input func_sl_force;
input func_sl_thold_0_b;
input sg_0;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out;
wire [52:59] ex3_stq5_rd_addr_d;
wire [52:59] ex3_stq5_rd_addr_q;
wire stq6_stg_act_d;
wire stq6_stg_act_q;
wire stq7_stg_act_d;
wire stq7_stg_act_q;
wire stq6_wren_d;
wire stq6_wren_q;
wire stq7_wren_d;
wire stq7_wren_q;
wire [0:7] stq6_way_en_d;
wire [0:7] stq6_way_en_q;
wire [0:7] stq7_way_en_d;
wire [0:7] stq7_way_en_q;
wire [0:7] stq6_wr_way;
wire [52:59] stq6_addr_d;
wire [52:59] stq6_addr_q;
wire [52:59] stq7_addr_d;
wire [52:59] stq7_addr_q;
wire [0:143] stq6_gate_rd_data_wa;
wire [0:143] stq6_gate_rd_data_wb;
wire [0:143] stq6_gate_rd_data_wc;
wire [0:143] stq6_gate_rd_data_wd;
wire [0:143] stq6_gate_rd_data_we;
wire [0:143] stq6_gate_rd_data_wf;
wire [0:143] stq6_gate_rd_data_wg;
wire [0:143] stq6_gate_rd_data_wh;
wire [0:143] stq6_rd_data_wabcd;
wire [0:143] stq6_wr_data_wabcd;
wire [0:143] stq7_wr_data_wabcd_d;
wire [0:143] stq7_wr_data_wabcd_q;
wire [0:143] stq8_wr_data_wabcd_d;
wire [0:143] stq8_wr_data_wabcd_q;
wire [0:143] stq6_rd_data_wefgh;
wire [0:143] stq6_wr_data_wefgh;
wire [0:143] stq7_wr_data_wefgh_d;
wire [0:143] stq7_wr_data_wefgh_q;
wire [0:143] stq8_wr_data_wefgh_d;
wire [0:143] stq8_wr_data_wefgh_q;
wire ex2_stq4_addr_coll;
wire [0:7] ex2_stq4_way_coll;
wire stq6_rd_byp_val;
wire stq7_rd_byp_val;
wire stq6_wr_byp_val;
wire stq7_wr_byp_val;
wire stq5_byp_val;
wire [0:143] stq5_wr_bit;
wire [0:143] stq5_msk_bit;
wire [0:15] stq5_byte_en;
wire [0:15] stq6_byte_en_wabcd_d;
wire [0:15] stq6_byte_en_wabcd_q;
wire [0:143] stq6_wr_bit_wabcd;
wire [0:143] stq6_msk_bit_wabcd;
wire [0:15] stq6_byte_en_wefgh_d;
wire [0:15] stq6_byte_en_wefgh_q;
wire [0:143] stq6_wr_bit_wefgh;
wire [0:143] stq6_msk_bit_wefgh;
wire [0:143] stq6_stq7_byp_data_wabcd;
wire [0:143] stq5_byp_wr_data_wabcd;
wire [0:143] stq6_byp_wr_data_wabcd_d;
wire [0:143] stq6_byp_wr_data_wabcd_q;
wire [0:143] stq6_stq7_byp_data_wefgh;
wire [0:143] stq5_byp_wr_data_wefgh;
wire [0:143] stq6_byp_wr_data_wefgh_d;
wire [0:143] stq6_byp_wr_data_wefgh_q;
wire [0:3] stq7_byp_val_wabcd_d;
wire [0:3] stq7_byp_val_wabcd_q;
wire [0:3] stq7_byp_val_wefgh_d;
wire [0:3] stq7_byp_val_wefgh_q;
wire [0:3] stq_byp_val_wabcd_d;
wire [0:3] stq_byp_val_wabcd_q;
wire [0:3] stq_byp_val_wefgh_d;
wire [0:3] stq_byp_val_wefgh_q;
parameter stq6_stg_act_offset = 0;
parameter stq7_stg_act_offset = stq6_stg_act_offset + 1;
parameter ex3_stq5_rd_addr_offset = stq7_stg_act_offset + 1;
parameter stq6_wren_offset = ex3_stq5_rd_addr_offset + 8;
parameter stq7_wren_offset = stq6_wren_offset + 1;
parameter stq6_way_en_offset = stq7_wren_offset + 1;
parameter stq7_way_en_offset = stq6_way_en_offset + 8;
parameter stq6_addr_offset = stq7_way_en_offset + 8;
parameter stq7_addr_offset = stq6_addr_offset + 8;
parameter stq7_wr_data_wabcd_offset = stq7_addr_offset + 8;
parameter stq7_wr_data_wefgh_offset = stq7_wr_data_wabcd_offset + 144;
parameter stq8_wr_data_wabcd_offset = stq7_wr_data_wefgh_offset + 144;
parameter stq8_wr_data_wefgh_offset = stq8_wr_data_wabcd_offset + 144;
parameter stq6_byte_en_wabcd_offset = stq8_wr_data_wefgh_offset + 144;
parameter stq6_byte_en_wefgh_offset = stq6_byte_en_wabcd_offset + 16;
parameter stq6_byp_wr_data_wabcd_offset = stq6_byte_en_wefgh_offset + 16;
parameter stq6_byp_wr_data_wefgh_offset = stq6_byp_wr_data_wabcd_offset + 144;
parameter stq7_byp_val_wabcd_offset = stq6_byp_wr_data_wefgh_offset + 144;
parameter stq7_byp_val_wefgh_offset = stq7_byp_val_wabcd_offset + 4;
parameter stq_byp_val_wabcd_offset = stq7_byp_val_wefgh_offset + 4;
parameter stq_byp_val_wefgh_offset = stq_byp_val_wabcd_offset + 4;
parameter scan_right = stq_byp_val_wefgh_offset + 4 - 1;
wire tiup;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
assign tiup = 1'b1;
assign ex3_stq5_rd_addr_d = ex2_stq4_rd_addr;
assign stq6_stg_act_d = stq5_stg_act;
assign stq7_stg_act_d = stq6_stg_act_q;
assign stq6_wren_d = stq5_arr_wren;
assign stq7_wren_d = stq6_wren_q;
assign stq6_way_en_d = stq5_arr_wr_way;
assign stq7_way_en_d = stq6_way_en_q;
assign stq6_wr_way = {8{stq6_wren_q}} & stq6_way_en_q;
assign stq6_addr_d = stq5_arr_wr_addr;
assign stq7_addr_d = stq6_addr_q;
// #############################################################################################
// Data Cache Read/Write Merge
// #############################################################################################
// Gate Way that is being updated
assign stq6_gate_rd_data_wa = {144{stq6_way_en_q[0]}} & stq6_rd_data_wa;
assign stq6_gate_rd_data_wb = {144{stq6_way_en_q[1]}} & stq6_rd_data_wb;
assign stq6_gate_rd_data_wc = {144{stq6_way_en_q[2]}} & stq6_rd_data_wc;
assign stq6_gate_rd_data_wd = {144{stq6_way_en_q[3]}} & stq6_rd_data_wd;
assign stq6_gate_rd_data_we = {144{stq6_way_en_q[4]}} & stq6_rd_data_we;
assign stq6_gate_rd_data_wf = {144{stq6_way_en_q[5]}} & stq6_rd_data_wf;
assign stq6_gate_rd_data_wg = {144{stq6_way_en_q[6]}} & stq6_rd_data_wg;
assign stq6_gate_rd_data_wh = {144{stq6_way_en_q[7]}} & stq6_rd_data_wh;
// Merge Data Way A,B,C,D
assign stq6_rd_data_wabcd = stq6_gate_rd_data_wa | stq6_gate_rd_data_wb |
stq6_gate_rd_data_wc | stq6_gate_rd_data_wd;
assign stq6_wr_data_wabcd = (stq6_wr_bit_wabcd & stq6_byp_wr_data_wabcd_q) | (stq6_msk_bit_wabcd & stq6_rd_data_wabcd);
assign stq7_wr_data_wabcd_d = stq6_wr_data_wabcd;
assign stq8_wr_data_wabcd_d = stq7_wr_data_wabcd_q;
// Merge Data Way E,F,G,H
assign stq6_rd_data_wefgh = stq6_gate_rd_data_we | stq6_gate_rd_data_wf |
stq6_gate_rd_data_wg | stq6_gate_rd_data_wh;
assign stq6_wr_data_wefgh = (stq6_wr_bit_wefgh & stq6_byp_wr_data_wefgh_q) | (stq6_msk_bit_wefgh & stq6_rd_data_wefgh);
assign stq7_wr_data_wefgh_d = stq6_wr_data_wefgh;
assign stq8_wr_data_wefgh_d = stq7_wr_data_wefgh_q;
// #############################################################################################
// Data Cache Write Data Bypass
// #############################################################################################
// Read/Write Address Match
assign ex2_stq4_addr_coll = (ex2_stq4_rd_addr == stq6_addr_q);
assign ex2_stq4_way_coll = {8{ex2_stq4_addr_coll}} & stq6_wr_way;
// Bypass Select Control
assign stq6_rd_byp_val = (ex3_stq5_rd_addr_q == stq6_addr_q) & stq6_wren_q;
assign stq7_rd_byp_val = (ex3_stq5_rd_addr_q == stq7_addr_q) & stq7_wren_q;
assign stq6_wr_byp_val = stq6_rd_byp_val & |(stq5_arr_wr_way & stq6_way_en_q);
assign stq7_wr_byp_val = stq7_rd_byp_val & |(stq5_arr_wr_way & stq7_way_en_q);
assign stq5_byp_val = stq6_wr_byp_val | stq7_wr_byp_val;
// Byte Enable and Byte Mask generation
assign stq5_wr_bit = {9{ stq5_arr_wr_bytew}};
assign stq5_msk_bit = {9{~stq5_arr_wr_bytew}};
assign stq5_byte_en = stq5_arr_wr_bytew | {16{stq5_byp_val}};
assign stq6_byte_en_wabcd_d = stq5_byte_en;
assign stq6_wr_bit_wabcd = {9{ stq6_byte_en_wabcd_q}};
assign stq6_msk_bit_wabcd = {9{~stq6_byte_en_wabcd_q}};
assign stq6_byte_en_wefgh_d = stq5_byte_en;
assign stq6_wr_bit_wefgh = {9{ stq6_byte_en_wefgh_q}};
assign stq6_msk_bit_wefgh = {9{~stq6_byte_en_wefgh_q}};
// Need to add bypass logic with merged data from stq6 and stq7 for Way A,B,C,D groups
assign stq6_stq7_byp_data_wabcd = ({144{~stq6_wr_byp_val}} & stq7_wr_data_wabcd_q) | ({144{stq6_wr_byp_val}} & stq6_wr_data_wabcd);
assign stq5_byp_wr_data_wabcd = (stq5_wr_bit & stq5_arr_wr_data) | (stq5_msk_bit & stq6_stq7_byp_data_wabcd);
assign stq6_byp_wr_data_wabcd_d = stq5_byp_wr_data_wabcd;
// Need to add bypass logic with merged data from stq6 and stq7 for Way E,F,G,H groups
assign stq6_stq7_byp_data_wefgh = ({144{~stq6_wr_byp_val}} & stq7_wr_data_wefgh_q) | ({144{stq6_wr_byp_val}} & stq6_wr_data_wefgh);
assign stq5_byp_wr_data_wefgh = (stq5_wr_bit & stq5_arr_wr_data) | (stq5_msk_bit & stq6_stq7_byp_data_wefgh);
assign stq6_byp_wr_data_wefgh_d = stq5_byp_wr_data_wefgh;
// Data that needs to be bypassed between EX2 Load Pipe Read collision detected with STQ6 Store Pipe Write
assign stq7_byp_val_wabcd_d = {4{stq6_rd_byp_val}} & stq6_way_en_q[0:3];
assign stq7_byp_val_wefgh_d = {4{stq6_rd_byp_val}} & stq6_way_en_q[4:7];
//assign stq7_byp_data_wefgh = stq7_wr_data_wefgh_q;
assign stq_byp_val_wabcd_d = ({4{stq7_rd_byp_val}} & stq7_way_en_q[0:3]) | ({4{stq6_rd_byp_val}} & stq6_way_en_q[0:3]);
assign stq_byp_val_wefgh_d = ({4{stq7_rd_byp_val}} & stq7_way_en_q[4:7]) | ({4{stq6_rd_byp_val}} & stq6_way_en_q[4:7]);
// #############################################################################################
// Outputs
// #############################################################################################
// Data Cache Array Read ACT
assign dcarr_rd_stg_act = {8{ex2_stq4_rd_stg_act}} & ~ex2_stq4_way_coll;
// Data Cache Array Update
assign dcarr_wr_stg_act = stq6_wr_way;
assign dcarr_wr_way = stq6_wr_way;
assign dcarr_wr_addr = stq6_addr_q;
assign dcarr_wr_data_wabcd = stq6_wr_data_wabcd;
assign dcarr_wr_data_wefgh = stq6_wr_data_wefgh;
// EX4 Load Data Bypass
assign stq7_byp_val_wabcd = stq7_byp_val_wabcd_q;
assign stq7_byp_val_wefgh = stq7_byp_val_wefgh_q;
assign stq7_byp_data_wabcd = stq7_wr_data_wabcd_q;
assign stq7_byp_data_wefgh = stq7_wr_data_wefgh_q;
assign stq8_byp_data_wabcd = stq8_wr_data_wabcd_q;
assign stq8_byp_data_wefgh = stq8_wr_data_wefgh_q;
assign stq_byp_val_wabcd = stq_byp_val_wabcd_q;
assign stq_byp_val_wefgh = stq_byp_val_wefgh_q;
// #############################################################################################
// Registers
// #############################################################################################
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_stg_act_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq6_stg_act_offset]),
.scout(sov[stq6_stg_act_offset]),
.din(stq6_stg_act_d),
.dout(stq6_stg_act_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_stg_act_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq7_stg_act_offset]),
.scout(sov[stq7_stg_act_offset]),
.din(stq7_stg_act_d),
.dout(stq7_stg_act_q)
);
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_stq5_rd_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[ex3_stq5_rd_addr_offset:ex3_stq5_rd_addr_offset + 8 - 1]),
.scout(sov[ex3_stq5_rd_addr_offset:ex3_stq5_rd_addr_offset + 8 - 1]),
.din(ex3_stq5_rd_addr_d),
.dout(ex3_stq5_rd_addr_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_arr_wren_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq6_wren_offset]),
.scout(sov[stq6_wren_offset]),
.din(stq6_wren_d),
.dout(stq6_wren_q)
);
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_arr_wren_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq7_wren_offset]),
.scout(sov[stq7_wren_offset]),
.din(stq7_wren_d),
.dout(stq7_wren_q)
);
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_way_en_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq5_stg_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq6_way_en_offset:stq6_way_en_offset + 8 - 1]),
.scout(sov[stq6_way_en_offset:stq6_way_en_offset + 8 - 1]),
.din(stq6_way_en_d),
.dout(stq6_way_en_q)
);
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_way_en_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq6_stg_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq7_way_en_offset:stq7_way_en_offset + 8 - 1]),
.scout(sov[stq7_way_en_offset:stq7_way_en_offset + 8 - 1]),
.din(stq7_way_en_d),
.dout(stq7_way_en_q)
);
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq5_stg_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq6_addr_offset:stq6_addr_offset + 8 - 1]),
.scout(sov[stq6_addr_offset:stq6_addr_offset + 8 - 1]),
.din(stq6_addr_d),
.dout(stq6_addr_q)
);
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq6_stg_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq7_addr_offset:stq7_addr_offset + 8 - 1]),
.scout(sov[stq7_addr_offset:stq7_addr_offset + 8 - 1]),
.din(stq7_addr_d),
.dout(stq7_addr_q)
);
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wabcd_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq6_stg_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq7_wr_data_wabcd_offset:stq7_wr_data_wabcd_offset + 144 - 1]),
.scout(sov[stq7_wr_data_wabcd_offset:stq7_wr_data_wabcd_offset + 144 - 1]),
.din(stq7_wr_data_wabcd_d),
.dout(stq7_wr_data_wabcd_q)
);
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wefgh_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq6_stg_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq7_wr_data_wefgh_offset:stq7_wr_data_wefgh_offset + 144 - 1]),
.scout(sov[stq7_wr_data_wefgh_offset:stq7_wr_data_wefgh_offset + 144 - 1]),
.din(stq7_wr_data_wefgh_d),
.dout(stq7_wr_data_wefgh_q)
);
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wabcd_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq7_stg_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq8_wr_data_wabcd_offset:stq8_wr_data_wabcd_offset + 144 - 1]),
.scout(sov[stq8_wr_data_wabcd_offset:stq8_wr_data_wabcd_offset + 144 - 1]),
.din(stq8_wr_data_wabcd_d),
.dout(stq8_wr_data_wabcd_q)
);
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wefgh_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq7_stg_act_q),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq8_wr_data_wefgh_offset:stq8_wr_data_wefgh_offset + 144 - 1]),
.scout(sov[stq8_wr_data_wefgh_offset:stq8_wr_data_wefgh_offset + 144 - 1]),
.din(stq8_wr_data_wefgh_d),
.dout(stq8_wr_data_wefgh_q)
);
tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wabcd_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq5_stg_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq6_byte_en_wabcd_offset:stq6_byte_en_wabcd_offset + 16 - 1]),
.scout(sov[stq6_byte_en_wabcd_offset:stq6_byte_en_wabcd_offset + 16 - 1]),
.din(stq6_byte_en_wabcd_d),
.dout(stq6_byte_en_wabcd_q)
);
tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wefgh_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq5_stg_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq6_byte_en_wefgh_offset:stq6_byte_en_wefgh_offset + 16 - 1]),
.scout(sov[stq6_byte_en_wefgh_offset:stq6_byte_en_wefgh_offset + 16 - 1]),
.din(stq6_byte_en_wefgh_d),
.dout(stq6_byte_en_wefgh_q)
);
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wabcd_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq5_stg_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq6_byp_wr_data_wabcd_offset:stq6_byp_wr_data_wabcd_offset + 144 - 1]),
.scout(sov[stq6_byp_wr_data_wabcd_offset:stq6_byp_wr_data_wabcd_offset + 144 - 1]),
.din(stq6_byp_wr_data_wabcd_d),
.dout(stq6_byp_wr_data_wabcd_q)
);
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wefgh_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(stq5_stg_act),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq6_byp_wr_data_wefgh_offset:stq6_byp_wr_data_wefgh_offset + 144 - 1]),
.scout(sov[stq6_byp_wr_data_wefgh_offset:stq6_byp_wr_data_wefgh_offset + 144 - 1]),
.din(stq6_byp_wr_data_wefgh_d),
.dout(stq6_byp_wr_data_wefgh_q)
);
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wabcd_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq7_byp_val_wabcd_offset:stq7_byp_val_wabcd_offset + 4 - 1]),
.scout(sov[stq7_byp_val_wabcd_offset:stq7_byp_val_wabcd_offset + 4 - 1]),
.din(stq7_byp_val_wabcd_d),
.dout(stq7_byp_val_wabcd_q)
);
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wefgh_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq7_byp_val_wefgh_offset:stq7_byp_val_wefgh_offset + 4 - 1]),
.scout(sov[stq7_byp_val_wefgh_offset:stq7_byp_val_wefgh_offset + 4 - 1]),
.din(stq7_byp_val_wefgh_d),
.dout(stq7_byp_val_wefgh_q)
);
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wabcd_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq_byp_val_wabcd_offset:stq_byp_val_wabcd_offset + 4 - 1]),
.scout(sov[stq_byp_val_wabcd_offset:stq_byp_val_wabcd_offset + 4 - 1]),
.din(stq_byp_val_wabcd_d),
.dout(stq_byp_val_wabcd_q)
);
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wefgh_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.force_t(func_sl_force),
.d_mode(d_mode_dc),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.sg(sg_0),
.scin(siv[stq_byp_val_wefgh_offset:stq_byp_val_wefgh_offset + 4 - 1]),
.scout(sov[stq_byp_val_wefgh_offset:stq_byp_val_wefgh_offset + 4 - 1]),
.din(stq_byp_val_wefgh_d),
.dout(stq_byp_val_wefgh_q)
);
assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
assign scan_out = sov[0];
endmodule |
module tri_eccgen(
din,
syn
);
parameter REGSIZE = 64;
input [0:REGSIZE+8-(64/REGSIZE)] din;
output [0:8-(64/REGSIZE)] syn;
generate // syndrome bits inverted
if (REGSIZE == 64)
begin : ecc64
wire [0:71] e;
wire [0:22] l1term;
// ====================================================================
// 64 data bits, 8 check bits
// single bit error correction, double bit error detection
// ====================================================================
// ecc matrix description
// ====================================================================
// syn 0 111011010011101001100101101101001100101101001011001101001110100110000000
// syn 1 110110101011010101010101011010101010101010101010101010101101010101000000
// syn 2 101101100110110011001100110110011001100110011001100110011011001100100000
// syn 3 011100011110001111000011110001111000011110000111100001111000111100010000
// syn 4 000011111110000000111111110000000111111110000000011111111000000000001000
// syn 5 000000000001111111111111110000000000000001111111111111111000000000000100
// syn 6 000000000000000000000000001111111111111111111111111111111000000000000010
// syn 7 000000000000000000000000000000000000000000000000000000000111111100000001
assign e[0:71] = din[0:71];
assign l1term[0] = e[0] ^ e[10] ^ e[17] ^ e[21] ^ e[32] ^ e[36] ^ e[44] ^ e[56];
assign l1term[1] = e[22] ^ e[23] ^ e[24] ^ e[25] ^ e[53] ^ e[54] ^ e[55] ^ e[56];
assign l1term[2] = e[1] ^ e[4] ^ e[11] ^ e[23] ^ e[26] ^ e[38] ^ e[46] ^ e[50];
assign l1term[3] = e[2] ^ e[5] ^ e[12] ^ e[24] ^ e[27] ^ e[39] ^ e[47] ^ e[51];
assign l1term[4] = e[3] ^ e[6] ^ e[13] ^ e[25] ^ e[28] ^ e[40] ^ e[48] ^ e[52];
assign l1term[5] = e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[37] ^ e[38] ^ e[39] ^ e[40];
assign l1term[6] = e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[45] ^ e[46] ^ e[47] ^ e[48];
assign l1term[7] = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[49] ^ e[50] ^ e[51] ^ e[52];
assign l1term[8] = e[7] ^ e[14] ^ e[18] ^ e[29] ^ e[33] ^ e[41] ^ e[53] ^ e[57];
assign l1term[9] = e[58] ^ e[60] ^ e[63] ^ e[64];
assign l1term[10] = e[8] ^ e[15] ^ e[19] ^ e[30] ^ e[34] ^ e[42] ^ e[54] ^ e[57];
assign l1term[11] = e[59] ^ e[61] ^ e[63] ^ e[65];
assign l1term[12] = e[9] ^ e[16] ^ e[20] ^ e[31] ^ e[35] ^ e[43] ^ e[55] ^ e[58];
assign l1term[13] = e[59] ^ e[62] ^ e[63] ^ e[66];
assign l1term[14] = e[1] ^ e[2] ^ e[3] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[60];
assign l1term[15] = e[61] ^ e[62] ^ e[63] ^ e[67];
assign l1term[16] = e[4] ^ e[5] ^ e[6] ^ e[33] ^ e[34] ^ e[35] ^ e[36] ^ e[68];
assign l1term[17] = e[11] ^ e[12] ^ e[13] ^ e[41] ^ e[42] ^ e[43] ^ e[44] ^ e[69];
assign l1term[18] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[33];
assign l1term[19] = e[34] ^ e[35] ^ e[36] ^ e[37] ^ e[38] ^ e[39] ^ e[40] ^ e[41];
assign l1term[20] = e[42] ^ e[43] ^ e[44] ^ e[45] ^ e[46] ^ e[47] ^ e[48] ^ e[49];
assign l1term[21] = e[50] ^ e[51] ^ e[52] ^ e[53] ^ e[54] ^ e[55] ^ e[56] ^ e[70];
assign l1term[22] = e[57] ^ e[58] ^ e[59] ^ e[60] ^ e[61] ^ e[62] ^ e[63] ^ e[71];
assign syn[0] = l1term[0] ^ l1term[2] ^ l1term[3] ^ l1term[8] ^ l1term[9];
assign syn[1] = l1term[0] ^ l1term[2] ^ l1term[4] ^ l1term[10] ^ l1term[11];
assign syn[2] = l1term[0] ^ l1term[3] ^ l1term[4] ^ l1term[12] ^ l1term[13];
assign syn[3] = l1term[1] ^ l1term[5] ^ l1term[6] ^ l1term[14] ^ l1term[15];
assign syn[4] = l1term[1] ^ l1term[5] ^ l1term[7] ^ l1term[16];
assign syn[5] = l1term[1] ^ l1term[6] ^ l1term[7] ^ l1term[17];
assign syn[6] = l1term[18] ^ l1term[19] ^ l1term[20] ^ l1term[21];
assign syn[7] = l1term[22];
end
endgenerate
generate // syndrome bits inverted
if (REGSIZE == 32)
begin : ecc32
wire [0:38] e;
wire [0:13] l1term;
// ====================================================================
// 32 Data Bits, 7 Check bits
// Single bit error correction, Double bit error detection
// ====================================================================
// ECC Matrix Description
// ====================================================================
// Syn 0 111011010011101001100101101101001000000
// Syn 1 110110101011010101010101011010100100000
// Syn 2 101101100110110011001100110110010010000
// Syn 3 011100011110001111000011110001110001000
// Syn 4 000011111110000000111111110000000000100
// Syn 5 000000000001111111111111110000000000010
// Syn 6 000000000000000000000000001111110000001
assign e[0:38] = din[0:38];
assign l1term[0] = e[0] ^ e[1] ^ e[4] ^ e[10] ^ e[11] ^ e[17] ^ e[21] ^ e[23];
assign l1term[1] = e[2] ^ e[3] ^ e[9] ^ e[10] ^ e[16] ^ e[17] ^ e[24] ^ e[25];
assign l1term[2] = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[22] ^ e[23] ^ e[24] ^ e[25];
assign l1term[3] = e[2] ^ e[5] ^ e[7] ^ e[12] ^ e[14] ^ e[18] ^ e[24] ^ e[26];
assign l1term[4] = e[27] ^ e[29] ^ e[32];
assign l1term[5] = e[3] ^ e[6] ^ e[8] ^ e[13] ^ e[15] ^ e[19] ^ e[25] ^ e[26];
assign l1term[6] = e[28] ^ e[30] ^ e[33];
assign l1term[7] = e[0] ^ e[5] ^ e[6] ^ e[12] ^ e[13] ^ e[20] ^ e[21] ^ e[27];
assign l1term[8] = e[28] ^ e[31] ^ e[34];
assign l1term[9] = e[1] ^ e[7] ^ e[8] ^ e[14] ^ e[15] ^ e[22] ^ e[23] ^ e[29];
assign l1term[10] = e[30] ^ e[31] ^ e[35];
assign l1term[11] = e[4] ^ e[5] ^ e[6] ^ e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[36];
assign l1term[12] = e[11] ^ e[12] ^ e[13] ^ e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[37];
assign l1term[13] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[38];
assign syn[0] = l1term[0] ^ l1term[3] ^ l1term[4];
assign syn[1] = l1term[0] ^ l1term[5] ^ l1term[6];
assign syn[2] = l1term[1] ^ l1term[7] ^ l1term[8];
assign syn[3] = l1term[1] ^ l1term[9] ^ l1term[10];
assign syn[4] = l1term[2] ^ l1term[11];
assign syn[5] = l1term[2] ^ l1term[12];
assign syn[6] = l1term[13];
end
endgenerate
endmodule |
module tri_nlat_scan(
vd,
gd,
d1clk,
d2clk,
lclk,
din,
scan_in,
q,
q_b,
scan_out
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter RESET_INVERTS_SCAN = 1'b1;
parameter SYNTHCLONEDLATCH = "";
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0; // 0 - Internal Flop, 1 - Domain Crossing Input Flop (requires extra logic for ASICs)
inout vd;
inout gd;
input d1clk;
input d2clk;
input [0:`NCLK_WIDTH-1] lclk;
input [OFFSET:OFFSET+WIDTH-1] din;
input [OFFSET:OFFSET+WIDTH-1] scan_in;
output [OFFSET:OFFSET+WIDTH-1] q;
output [OFFSET:OFFSET+WIDTH-1] q_b;
output [OFFSET:OFFSET+WIDTH-1] scan_out;
// tri_nlat_scan
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{d1clk}};
assign vact_b = {WIDTH{~d1clk}};
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};
always @(posedge lclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign q = int_dout;
assign q_b = (~int_dout);
assign scan_out = ZEROS;
assign unused = | {vd, gd, lclk, scan_in};
end
endgenerate
endmodule |
module tri_nand2(
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "NAND2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
// tri_nand2
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
nand I0(y[i], a[i], b[i]);
end // block: w
end
endgenerate
endmodule |
module tri_st_or3232(
d,
or_hi_b,
or_lo_b
);
input [0:63] d; //data
output or_hi_b; // upper 32 ORed together
output or_lo_b; // lower 32 ORed together
wire [0:31] or_lv1_b;
wire [0:15] or_lv2;
wire [0:7] or_lv3_b;
wire [0:3] or_lv4;
wire [0:1] or_lv5_b;
assign or_lv1_b[0] = (~(d[0] | d[1]));
assign or_lv1_b[1] = (~(d[2] | d[3]));
assign or_lv1_b[2] = (~(d[4] | d[5]));
assign or_lv1_b[3] = (~(d[6] | d[7]));
assign or_lv1_b[4] = (~(d[8] | d[9]));
assign or_lv1_b[5] = (~(d[10] | d[11]));
assign or_lv1_b[6] = (~(d[12] | d[13]));
assign or_lv1_b[7] = (~(d[14] | d[15]));
assign or_lv1_b[8] = (~(d[16] | d[17]));
assign or_lv1_b[9] = (~(d[18] | d[19]));
assign or_lv1_b[10] = (~(d[20] | d[21]));
assign or_lv1_b[11] = (~(d[22] | d[23]));
assign or_lv1_b[12] = (~(d[24] | d[25]));
assign or_lv1_b[13] = (~(d[26] | d[27]));
assign or_lv1_b[14] = (~(d[28] | d[29]));
assign or_lv1_b[15] = (~(d[30] | d[31]));
assign or_lv1_b[16] = (~(d[32] | d[33]));
assign or_lv1_b[17] = (~(d[34] | d[35]));
assign or_lv1_b[18] = (~(d[36] | d[37]));
assign or_lv1_b[19] = (~(d[38] | d[39]));
assign or_lv1_b[20] = (~(d[40] | d[41]));
assign or_lv1_b[21] = (~(d[42] | d[43]));
assign or_lv1_b[22] = (~(d[44] | d[45]));
assign or_lv1_b[23] = (~(d[46] | d[47]));
assign or_lv1_b[24] = (~(d[48] | d[49]));
assign or_lv1_b[25] = (~(d[50] | d[51]));
assign or_lv1_b[26] = (~(d[52] | d[53]));
assign or_lv1_b[27] = (~(d[54] | d[55]));
assign or_lv1_b[28] = (~(d[56] | d[57]));
assign or_lv1_b[29] = (~(d[58] | d[59]));
assign or_lv1_b[30] = (~(d[60] | d[61]));
assign or_lv1_b[31] = (~(d[62] | d[63]));
assign or_lv2[0] = (~(or_lv1_b[0] & or_lv1_b[1]));
assign or_lv2[1] = (~(or_lv1_b[2] & or_lv1_b[3]));
assign or_lv2[2] = (~(or_lv1_b[4] & or_lv1_b[5]));
assign or_lv2[3] = (~(or_lv1_b[6] & or_lv1_b[7]));
assign or_lv2[4] = (~(or_lv1_b[8] & or_lv1_b[9]));
assign or_lv2[5] = (~(or_lv1_b[10] & or_lv1_b[11]));
assign or_lv2[6] = (~(or_lv1_b[12] & or_lv1_b[13]));
assign or_lv2[7] = (~(or_lv1_b[14] & or_lv1_b[15]));
assign or_lv2[8] = (~(or_lv1_b[16] & or_lv1_b[17]));
assign or_lv2[9] = (~(or_lv1_b[18] & or_lv1_b[19]));
assign or_lv2[10] = (~(or_lv1_b[20] & or_lv1_b[21]));
assign or_lv2[11] = (~(or_lv1_b[22] & or_lv1_b[23]));
assign or_lv2[12] = (~(or_lv1_b[24] & or_lv1_b[25]));
assign or_lv2[13] = (~(or_lv1_b[26] & or_lv1_b[27]));
assign or_lv2[14] = (~(or_lv1_b[28] & or_lv1_b[29]));
assign or_lv2[15] = (~(or_lv1_b[30] & or_lv1_b[31]));
assign or_lv3_b[0] = (~(or_lv2[0] | or_lv2[1]));
assign or_lv3_b[1] = (~(or_lv2[2] | or_lv2[3]));
assign or_lv3_b[2] = (~(or_lv2[4] | or_lv2[5]));
assign or_lv3_b[3] = (~(or_lv2[6] | or_lv2[7]));
assign or_lv3_b[4] = (~(or_lv2[8] | or_lv2[9]));
assign or_lv3_b[5] = (~(or_lv2[10] | or_lv2[11]));
assign or_lv3_b[6] = (~(or_lv2[12] | or_lv2[13]));
assign or_lv3_b[7] = (~(or_lv2[14] | or_lv2[15]));
assign or_lv4[0] = (~(or_lv3_b[0] & or_lv3_b[1]));
assign or_lv4[1] = (~(or_lv3_b[2] & or_lv3_b[3]));
assign or_lv4[2] = (~(or_lv3_b[4] & or_lv3_b[5]));
assign or_lv4[3] = (~(or_lv3_b[6] & or_lv3_b[7]));
assign or_lv5_b[0] = (~(or_lv4[0] | or_lv4[1]));
assign or_lv5_b[1] = (~(or_lv4[2] | or_lv4[3]));
assign or_hi_b = or_lv5_b[0]; // rename --output--
assign or_lo_b = or_lv5_b[1]; // rename --output--
endmodule |
module tri_xnor2(
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "XNOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
xnor I0(y[i], a[i], b[i]);
end // block: w
end
endgenerate
endmodule |
module tri_xor2(
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "XOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
xor I0(y[i], a[i], b[i]);
end // block: w
end
endgenerate
endmodule |
module tri_aoi21(
y,
a0,
a1,
b0
);
parameter WIDTH = 1;
parameter BTR = "AOI21_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
// tri_aoi21
genvar i;
wire [0:WIDTH-1] outA;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
and I0(outA[i], a0[i], a1[i]);
nor I2(y[i], outA[i], b0[i]);
end // block: w
end
endgenerate
endmodule |
module tri_nor3(
y,
a,
b,
c
);
parameter WIDTH = 1;
parameter BTR = "NOR3_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
// tri_nor3
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
nor I0(y[i], a[i], b[i], c[i]);
end // block: w
end
endgenerate
endmodule |
module tri_st_rot_dec(
i,
ex1_zm_ins,
ex1_mb_ins,
ex1_me_ins_b,
ex1_sh_amt,
ex1_sh_right,
ex1_sh_word,
ex1_use_rb_amt_hi,
ex1_use_rb_amt_lo,
ex1_use_me_rb_hi,
ex1_use_me_rb_lo,
ex1_use_mb_rb_hi,
ex1_use_mb_rb_lo,
ex1_use_me_ins_hi,
ex1_use_me_ins_lo,
ex1_use_mb_ins_hi,
ex1_use_mb_ins_lo,
ex1_ins_prtyw,
ex1_ins_prtyd,
ex1_chk_shov_wd,
ex1_chk_shov_dw,
ex1_mb_gt_me,
ex1_cmp_byt,
ex1_sgnxtd_byte,
ex1_sgnxtd_half,
ex1_sgnxtd_wd,
ex1_sra_dw,
ex1_sra_wd,
ex1_log_fcn,
ex1_sel_rot_log
);
input [0:31] i;
output ex1_zm_ins;
output [0:5] ex1_mb_ins;
output [0:5] ex1_me_ins_b;
output [0:5] ex1_sh_amt;
output ex1_sh_right;
output ex1_sh_word;
output ex1_use_rb_amt_hi;
output ex1_use_rb_amt_lo;
output ex1_use_me_rb_hi;
output ex1_use_me_rb_lo;
output ex1_use_mb_rb_hi;
output ex1_use_mb_rb_lo;
output ex1_use_me_ins_hi;
output ex1_use_me_ins_lo;
output ex1_use_mb_ins_hi;
output ex1_use_mb_ins_lo;
output ex1_ins_prtyw;
output ex1_ins_prtyd;
output ex1_chk_shov_wd;
output ex1_chk_shov_dw;
output ex1_mb_gt_me;
output ex1_cmp_byt;
output ex1_sgnxtd_byte;
output ex1_sgnxtd_half;
output ex1_sgnxtd_wd;
output ex1_sra_dw;
output ex1_sra_wd;
output [0:3] ex1_log_fcn;
output ex1_sel_rot_log;
wire cmp_byt;
wire rotlw;
wire imm_log;
wire rotld;
wire x31;
wire f0_xxxx00;
wire f0_xxx0xx;
wire f0_xxxx0x;
wire f1_1xxxx;
wire f1_111xx;
wire f1_110xx;
wire f1_x1x1x;
wire f1_x1xx0;
wire f1_x1xx1;
wire f1_xxx00;
wire f1_xxx11;
wire f1_xx10x;
wire f2_11xxx;
wire f2_xx0xx;
wire f2_xxx00;
wire f2_xxx0x;
wire f2_111xx;
wire f1_xxx01;
wire f1_xxx10;
wire f2_xx01x;
wire f2_xx00x;
wire rotlw_nm;
wire rotlw_pass;
wire rotld_pass;
wire sh_lft_rb;
wire sh_lft_rb_dw;
wire sh_rgt;
wire sh_rgt_rb;
wire sh_rgt_rb_dw;
wire shift_imm;
wire sh_rb;
wire sh_rb_dw;
wire sh_rb_wd;
wire x31_sh_log_sgn;
wire op_sgn_xtd;
wire op_sra;
wire wd_if_sh;
wire xtd_log;
wire sh_word_int;
wire imm_xor_or;
wire imm_and_or;
wire xtd_nor;
wire xtd_eqv_orc_nand;
wire xtd_nand;
wire xtd_andc_xor_or;
wire xtd_and_eqv_orc;
wire xtd_or_orc;
wire xtd_xor_or;
wire sel_ins_amt_hi;
wire sel_ins_me_lo_wd;
wire sel_ins_me_lo_dw;
wire sel_ins_amt_lo;
wire sel_ins_me_hi;
wire rot_imm_mb;
wire gt5_g_45;
wire gt5_g_23;
wire gt5_g_1;
wire gt5_t_23;
wire gt5_t_1;
wire mb_gt_me_cmp_wd0_b;
wire mb_gt_me_cmp_wd1_b;
wire mb_gt_me_cmp_wd2_b;
wire mb_gt_me_cmp_wd;
wire gt6_g_45;
wire gt6_g_23;
wire gt6_g_01;
wire gt6_t_23;
wire gt6_t_01;
wire mb_gt_me_cmp_dw0_b;
wire mb_gt_me_cmp_dw1_b;
wire mb_gt_me_cmp_dw2_b;
wire mb_gt_me_cmp_dw;
wire [0:5] me_ins;
wire [1:5] gt5_in0;
wire [1:5] gt5_in1;
wire [0:5] gt6_in0;
wire [0:5] gt6_in1;
wire [1:5] gt5_g_b;
wire [1:4] gt5_t_b;
wire [0:5] gt6_g_b;
wire [0:4] gt6_t_b;
wire f0_xxxx11;
wire f1_0xxxx;
wire f1_1xxx0;
wire f1_xxxx0;
wire f1_xxxx1;
wire f2_xxx1x;
wire f1_xx1xx;
wire xtd_nand_or_orc;
wire rld_cr;
wire rld_cl;
wire rld_icr;
wire rld_icl;
wire rld_ic;
wire rld_imi;
wire sh_lft_imm_dw;
wire sh_lft_imm;
wire sh_rgt_imm_dw;
wire sh_rgt_imm;
wire rotld_en_mbgtme;
wire [0:3] rf1_log_fcn;
wire isel;
wire prtyw;
wire prtyd;
//--------------------------------------------------
// decode primary field opcode bits [0:5] ---
//--------------------------------------------------
assign ex1_ins_prtyw = prtyw;
assign ex1_ins_prtyd = prtyd;
assign isel = (x31 == 1'b1 & i[26:30] == 5'b01111) ? 1'b1 :
1'b0;
assign cmp_byt = (x31 == 1'b1 & i[21:30] == 10'b0111111100) ? 1'b1 : // 31/508
1'b0;
assign prtyw = (x31 == 1'b1 & i[21:30] == 10'b0010011010) ? 1'b1 : // 31/154
1'b0;
assign prtyd = (x31 == 1'b1 & i[21:30] == 10'b0010111010) ? 1'b1 : // 31/186
1'b0;
assign rotlw = (~i[0]) & i[1] & (~i[2]) & i[3]; //0101xx (20:23)
assign imm_log = (~i[0]) & i[1] & i[2] & ((~i[3]) | (~i[4])); //0110xx (24:27)
//01110x (28,29)
assign rotld = (~i[0]) & i[1] & i[2] & i[3] & i[4] & (~i[5]); //011110 (30)
assign x31 = (~i[0]) & i[1] & i[2] & i[3] & i[4] & i[5]; //011111 (31)
assign f0_xxxx00 = (~i[4]) & (~i[5]);
assign f0_xxx0xx = (~i[3]);
assign f0_xxxx0x = (~i[4]);
assign f0_xxxx11 = i[4] & i[5];
//---------------------------------------------------
// decode i(21:25)
//---------------------------------------------------
assign f1_0xxxx = (~i[21]);
assign f1_110xx = i[21] & i[22] & (~i[23]);
assign f1_111xx = i[21] & i[22] & i[23];
assign f1_1xxx0 = i[21] & (~i[25]);
assign f1_1xxxx = i[21];
assign f1_x1x1x = i[22] & i[24];
assign f1_xx1xx = i[23];
assign f1_x1xx0 = i[22] & (~i[25]);
assign f1_x1xx1 = i[22] & i[25];
assign f1_xx10x = i[23] & (~i[24]);
assign f1_xxx01 = (~i[24]) & i[25];
assign f1_xxx11 = i[24] & i[25];
assign f1_xxxx0 = (~i[25]);
assign f1_xxxx1 = i[25];
assign f1_xxx00 = (~i[24]) & (~i[25]);
assign f1_xxx10 = i[24] & (~i[25]);
//---------------------------------------------------
// decode i(26:30)
//---------------------------------------------------
assign f2_11xxx = i[26] & i[27]; // shifts / logicals / sign_xtd
assign f2_xxx0x = (~i[29]); // word / double
assign f2_111xx = i[26] & i[27] & i[28];
assign f2_xx01x = (~i[28]) & i[29];
assign f2_xx00x = (~i[28]) & (~i[29]);
assign f2_xxx1x = i[29];
assign f2_xx0xx = (~i[28]);
assign f2_xxx00 = (~i[29]) & (~i[30]);
assign rotlw_nm = rotlw & f0_xxxx11;
assign rotlw_pass = rotlw & f0_xxxx00;
assign rotld_pass = rld_imi;
assign sh_lft_rb = x31 & f1_0xxxx;
assign sh_lft_rb_dw = x31 & f1_0xxxx & f2_xxx1x;
assign sh_rgt = x31 & f1_1xxxx;
assign sh_rgt_rb = x31 & f1_1xxx0;
assign sh_rgt_rb_dw = x31 & f1_1xxx0 & f2_xxx1x;
assign shift_imm = x31 & f1_xxxx1;
assign sh_rb = x31 & f1_xxxx0;
assign sh_rb_dw = x31 & f1_xxxx0 & f2_xxx1x;
assign sh_rb_wd = x31 & f1_xxxx0 & f2_xxx0x;
assign x31_sh_log_sgn = x31 & f2_11xxx & (f2_xx0xx | f2_xxx00); // Exclude loads/stores
assign op_sgn_xtd = x31 & f1_111xx;
assign op_sra = x31 & f1_110xx;
assign wd_if_sh = x31 & f2_xxx0x;
assign xtd_log = x31 & f2_111xx;
assign sh_lft_imm_dw = 0;
assign sh_lft_imm = 0;
assign sh_rgt_imm_dw = x31 & i[21] & i[25] & i[29];
assign sh_rgt_imm = x31 & i[21] & i[25];
//---------------------------------------------------
// output signal
//---------------------------------------------------
assign ex1_cmp_byt = cmp_byt;
// (select to rot/log result instead of the adder result)
assign ex1_sel_rot_log = (cmp_byt) | (rotlw) | (imm_log) | (rotld) | (isel) | (x31_sh_log_sgn);
// prtyw, prtyd already included here....
// (zero out the mask to pass "insert_data" as the result)
// This latched, full decode ok.
assign ex1_zm_ins = (isel) | (cmp_byt) | (xtd_log) | (imm_log) | (op_sgn_xtd) | (prtyw) | (prtyd); // sgn extends
// (only needs to be correct when shifting)
assign ex1_sh_right = sh_rgt;
assign sh_word_int = (rotlw) | (wd_if_sh);
// (only needs to be correct when shifting)
assign ex1_sh_word = sh_word_int;
assign ex1_sgnxtd_byte = op_sgn_xtd & f1_xxx01 & (~isel);
assign ex1_sgnxtd_half = op_sgn_xtd & f1_xxx00 & (~isel);
assign ex1_sgnxtd_wd = op_sgn_xtd & f1_xxx10 & (~isel);
assign ex1_sra_dw = op_sra & f2_xx01x & (~isel);
assign ex1_sra_wd = op_sra & f2_xx00x & (~isel);
assign imm_xor_or = f0_xxx0xx;
assign imm_and_or = f0_xxxx0x;
assign xtd_nor = f1_xxx11;
assign xtd_eqv_orc_nand = f1_x1xx0;
assign xtd_nand = f1_x1x1x;
assign xtd_nand_or_orc = f1_xx1xx;
assign xtd_andc_xor_or = f1_xxx01;
assign xtd_and_eqv_orc = f1_xxx00;
assign xtd_or_orc = f1_xx10x;
assign xtd_xor_or = f1_x1xx1;
assign ex1_log_fcn = (cmp_byt == 1'b1) ? 4'b1001 : // xtd_log nor
rf1_log_fcn;
assign rf1_log_fcn[0] = (xtd_log & xtd_nor) | (xtd_log & xtd_eqv_orc_nand) | (cmp_byt); // xtd_log eqv,orc,nand
// xnor
// xtd_log xor,or
// xor,or
// pass rlwimi
assign rf1_log_fcn[1] = (xtd_log & xtd_xor_or) | (xtd_log & xtd_nand) | (imm_log & imm_xor_or) | (rotlw_pass) | (rotld_pass); // xtd_log nand
// pass rldimi
// xtd_log andc,xor,or
assign rf1_log_fcn[2] = (xtd_log & xtd_andc_xor_or) | (xtd_log & xtd_nand_or_orc) | (imm_log & imm_xor_or); // xtd_log nand_or_orc
// xor,or
// xnor
// xtd_log or,orc
// and,or
// pass rlwimi
assign rf1_log_fcn[3] = (cmp_byt) | (xtd_log & xtd_and_eqv_orc) | (xtd_log & xtd_or_orc) | (imm_log & imm_and_or) | (rotlw_pass) | (rotld_pass); // xtd_log and,eqv_orc
// pass rldimi
assign ex1_chk_shov_dw = (sh_rb_dw);
assign ex1_chk_shov_wd = (sh_rb_wd);
//---------------------------------------------
assign ex1_me_ins_b[0:5] = (~me_ins[0:5]);
assign me_ins[0] = (rotlw) | (i[26] & sel_ins_me_hi) | ((~i[30]) & sel_ins_amt_hi); // force_msb
assign me_ins[1:5] = (i[26:30] & {5{sel_ins_me_lo_wd}}) | (i[21:25] & {5{sel_ins_me_lo_dw}}) | ((~i[16:20]) & {5{sel_ins_amt_lo}});
assign sel_ins_me_lo_wd = rotlw;
assign sel_ins_me_lo_dw = rld_cr | rld_icr;
assign sel_ins_amt_lo = rld_ic | rld_imi | sh_lft_rb;
assign sel_ins_amt_hi = rld_ic | rld_imi | sh_lft_rb_dw;
assign sel_ins_me_hi = rld_cr | rld_icr;
assign ex1_use_me_rb_hi = (sh_lft_rb_dw);
assign ex1_use_me_rb_lo = (sh_lft_rb);
assign ex1_use_me_ins_hi = rld_cr | rld_icr | rld_imi | rld_ic | rotlw | sh_lft_imm_dw;
assign ex1_use_me_ins_lo = rld_cr | rld_icr | rld_imi | rld_ic | rotlw | sh_lft_imm;
assign rld_icl = rotld & (~i[27]) & (~i[28]) & (~i[29]);
assign rld_icr = rotld & (~i[27]) & (~i[28]) & i[29];
assign rld_ic = rotld & (~i[27]) & i[28] & (~i[29]);
assign rld_imi = rotld & (~i[27]) & i[28] & i[29];
assign rld_cl = rotld & i[27] & (~i[30]);
assign rld_cr = rotld & i[27] & i[30];
//---------------------------------------------
assign ex1_mb_ins[0] = (i[26] & rot_imm_mb) | (i[30] & shift_imm) | (rotlw) | (wd_if_sh); // force_msb
// force_msb
assign ex1_mb_ins[1:5] = (i[21:25] & {5{rot_imm_mb}}) | (i[16:20] & {5{shift_imm}});
assign rot_imm_mb = (rotlw) | (rld_cl | rld_icl | rld_ic | rld_imi);
assign ex1_use_mb_rb_lo = sh_rgt_rb;
assign ex1_use_mb_rb_hi = sh_rgt_rb_dw;
assign ex1_use_mb_ins_hi = rld_cl | rld_icl | rld_imi | rld_ic | rotlw | sh_rgt_imm_dw | wd_if_sh;
assign ex1_use_mb_ins_lo = rld_cl | rld_icl | rld_imi | rld_ic | rotlw | sh_rgt_imm;
//---------------------------------------------
assign ex1_use_rb_amt_hi = (rld_cr) | (rld_cl) | (sh_rb_dw);
assign ex1_use_rb_amt_lo = (rld_cr) | (rld_cl) | (rotlw_nm) | (sh_rb); // rlwnm
assign ex1_sh_amt[0] = i[30] & (~sh_word_int);
assign ex1_sh_amt[1:5] = i[16:20];
//---------------------------------------------
assign rotld_en_mbgtme = rld_imi | rld_ic;
assign ex1_mb_gt_me = (mb_gt_me_cmp_wd & rotlw) | (mb_gt_me_cmp_dw & rotld_en_mbgtme); // rldic,rldimi
//-------------------------------------------
assign gt5_in1[1:5] = i[21:25]; // mb
assign gt5_in0[1:5] = (~i[26:30]); // me
assign gt6_in1[0:5] = {i[26], i[21:25]}; // mb
assign gt6_in0[0:5] = {i[30], i[16:20]}; // me not( not amt )
//------------------------------------------
assign gt5_g_b[1:5] = (~(gt5_in0[1:5] & gt5_in1[1:5]));
assign gt5_t_b[1:4] = (~(gt5_in0[1:4] | gt5_in1[1:4]));
assign gt5_g_45 = (~(gt5_g_b[4] & (gt5_t_b[4] | gt5_g_b[5])));
assign gt5_g_23 = (~(gt5_g_b[2] & (gt5_t_b[2] | gt5_g_b[3])));
assign gt5_g_1 = (~(gt5_g_b[1]));
assign gt5_t_23 = (~(gt5_t_b[2] | gt5_t_b[3]));
assign gt5_t_1 = (~(gt5_t_b[1]));
assign mb_gt_me_cmp_wd0_b = (~(gt5_g_1));
assign mb_gt_me_cmp_wd1_b = (~(gt5_g_23 & gt5_t_1));
assign mb_gt_me_cmp_wd2_b = (~(gt5_g_45 & gt5_t_1 & gt5_t_23));
assign mb_gt_me_cmp_wd = (~(mb_gt_me_cmp_wd0_b & mb_gt_me_cmp_wd1_b & mb_gt_me_cmp_wd2_b));
//--------------------------------------------
assign gt6_g_b[0:5] = (~(gt6_in0[0:5] & gt6_in1[0:5]));
assign gt6_t_b[0:4] = (~(gt6_in0[0:4] | gt6_in1[0:4]));
assign gt6_g_45 = (~(gt6_g_b[4] & (gt6_t_b[4] | gt6_g_b[5])));
assign gt6_g_23 = (~(gt6_g_b[2] & (gt6_t_b[2] | gt6_g_b[3])));
assign gt6_g_01 = (~(gt6_g_b[0] & (gt6_t_b[0] | gt6_g_b[1])));
assign gt6_t_23 = (~(gt6_t_b[2] | gt6_t_b[3]));
assign gt6_t_01 = (~(gt6_t_b[0] | gt6_t_b[1]));
assign mb_gt_me_cmp_dw0_b = (~(gt6_g_01));
assign mb_gt_me_cmp_dw1_b = (~(gt6_g_23 & gt6_t_01));
assign mb_gt_me_cmp_dw2_b = (~(gt6_g_45 & gt6_t_01 & gt6_t_23));
assign mb_gt_me_cmp_dw = (~(mb_gt_me_cmp_dw0_b & mb_gt_me_cmp_dw1_b & mb_gt_me_cmp_dw2_b));
endmodule |
module tri_lcbor(clkoff_b, thold, sg, act_dis, force_t, thold_b);
input clkoff_b;
input thold;
input sg;
input act_dis;
output force_t;
output thold_b;
(* analysis_not_referenced="true" *)
wire unused;
assign unused = clkoff_b | sg | act_dis;
assign force_t = 1'b0;
assign thold_b = (~thold);
endmodule |
module tri_aoi22(
y,
a0,
a1,
b0,
b1
);
parameter WIDTH = 1;
parameter BTR = "AOI22_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
input [0:WIDTH-1] b1;
// tri_aoi22
genvar i;
wire [0:WIDTH-1] outA;
wire [0:WIDTH-1] outB;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
and I0(outA[i], a0[i], a1[i]);
and I1(outB[i], b0[i], b1[i]);
nor I2(y[i], outA[i], outB[i]);
end // block: w
end
endgenerate
endmodule |
module tri_bht_512x4_1r1w(
gnd,
vdd,
vcs,
nclk,
pc_iu_func_sl_thold_2,
pc_iu_sg_2,
pc_iu_time_sl_thold_2,
pc_iu_abst_sl_thold_2,
pc_iu_ary_nsl_thold_2,
pc_iu_repr_sl_thold_2,
pc_iu_bolt_sl_thold_2,
tc_ac_ccflush_dc,
tc_ac_scan_dis_dc_b,
clkoff_b,
scan_diag_dc,
act_dis,
d_mode,
delay_lclkr,
mpw1_b,
mpw2_b,
g8t_clkoff_b,
g8t_d_mode,
g8t_delay_lclkr,
g8t_mpw1_b,
g8t_mpw2_b,
func_scan_in,
time_scan_in,
abst_scan_in,
repr_scan_in,
func_scan_out,
time_scan_out,
abst_scan_out,
repr_scan_out,
pc_iu_abist_di_0,
pc_iu_abist_g8t_bw_1,
pc_iu_abist_g8t_bw_0,
pc_iu_abist_waddr_0,
pc_iu_abist_g8t_wenb,
pc_iu_abist_raddr_0,
pc_iu_abist_g8t1p_renb_0,
an_ac_lbist_ary_wrt_thru_dc,
pc_iu_abist_ena_dc,
pc_iu_abist_wl128_comp_ena,
pc_iu_abist_raw_dc_b,
pc_iu_abist_g8t_dcomp,
pc_iu_bo_enable_2,
pc_iu_bo_reset,
pc_iu_bo_unload,
pc_iu_bo_repair,
pc_iu_bo_shdata,
pc_iu_bo_select,
iu_pc_bo_fail,
iu_pc_bo_diagout,
r_act,
w_act,
r_addr,
w_addr,
data_in,
data_out0,
data_out1,
data_out2,
data_out3,
pc_iu_init_reset
);
// power pins
inout gnd;
inout vdd;
inout vcs;
// clock and clockcontrol ports
input [0:`NCLK_WIDTH-1] nclk;
input pc_iu_func_sl_thold_2;
input pc_iu_sg_2;
input pc_iu_time_sl_thold_2;
input pc_iu_abst_sl_thold_2;
input pc_iu_ary_nsl_thold_2;
input pc_iu_repr_sl_thold_2;
input pc_iu_bolt_sl_thold_2;
input tc_ac_ccflush_dc;
input tc_ac_scan_dis_dc_b;
input clkoff_b;
input scan_diag_dc;
input act_dis;
input d_mode;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input g8t_clkoff_b;
input g8t_d_mode;
input [0:4] g8t_delay_lclkr;
input [0:4] g8t_mpw1_b;
input g8t_mpw2_b;
input func_scan_in;
input time_scan_in;
input abst_scan_in;
input repr_scan_in;
output func_scan_out;
output time_scan_out;
output abst_scan_out;
output repr_scan_out;
input [0:3] pc_iu_abist_di_0;
input pc_iu_abist_g8t_bw_1;
input pc_iu_abist_g8t_bw_0;
input [3:9] pc_iu_abist_waddr_0;
input pc_iu_abist_g8t_wenb;
input [3:9] pc_iu_abist_raddr_0;
input pc_iu_abist_g8t1p_renb_0;
input an_ac_lbist_ary_wrt_thru_dc;
input pc_iu_abist_ena_dc;
input pc_iu_abist_wl128_comp_ena;
input pc_iu_abist_raw_dc_b;
input [0:3] pc_iu_abist_g8t_dcomp;
// BOLT-ON
input pc_iu_bo_enable_2; // general bolt-on enable
input pc_iu_bo_reset; // reset
input pc_iu_bo_unload; // unload sticky bits
input pc_iu_bo_repair; // execute sticky bit decode
input pc_iu_bo_shdata; // shift data for timing write and diag loop
input pc_iu_bo_select; // select for mask and hier writes
output iu_pc_bo_fail; // fail/no-fix reg
output iu_pc_bo_diagout;
// ports
input r_act;
input [0:3] w_act;
input [0:8] r_addr;
input [0:8] w_addr;
input data_in;
output data_out0;
output data_out1;
output data_out2;
output data_out3;
input pc_iu_init_reset;
//--------------------------
// constants
//--------------------------
parameter data_in_offset = 0;
parameter w_act_offset = data_in_offset + 1;
parameter r_act_offset = w_act_offset + 4;
parameter w_addr_offset = r_act_offset + 1;
parameter r_addr_offset = w_addr_offset + 9;
parameter data_out_offset = r_addr_offset + 9;
parameter reset_w_addr_offset = data_out_offset + 4;
parameter array_offset = reset_w_addr_offset + 9;
parameter scan_right = array_offset + 1 - 1;
//--------------------------
// signals
//--------------------------
wire pc_iu_func_sl_thold_1;
wire pc_iu_func_sl_thold_0;
wire pc_iu_func_sl_thold_0_b;
wire pc_iu_time_sl_thold_1;
wire pc_iu_time_sl_thold_0;
wire pc_iu_ary_nsl_thold_1;
wire pc_iu_ary_nsl_thold_0;
wire pc_iu_abst_sl_thold_1;
wire pc_iu_abst_sl_thold_0;
wire pc_iu_repr_sl_thold_1;
wire pc_iu_repr_sl_thold_0;
wire pc_iu_bolt_sl_thold_1;
wire pc_iu_bolt_sl_thold_0;
wire pc_iu_sg_1;
wire pc_iu_sg_0;
wire force_t;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
wire tiup;
wire [0:3] data_out_d;
wire [0:3] data_out_q;
wire ary_w_en;
wire [0:8] ary_w_addr;
wire [0:15] ary_w_sel;
wire [0:15] ary_w_data;
wire ary_r_en;
wire [0:8] ary_r_addr;
wire [0:15] ary_r_data;
wire [0:3] data_out;
wire [0:3] write_thru;
wire data_in_d;
wire data_in_q;
wire [0:3] w_act_d;
wire [0:3] w_act_q;
wire r_act_d;
wire r_act_q;
wire [0:8] w_addr_d;
wire [0:8] w_addr_q;
wire [0:8] r_addr_d;
wire [0:8] r_addr_q;
wire lat_wi_act;
wire lat_ri_act;
wire lat_ro_act;
wire reset_act;
wire [0:8] reset_w_addr_d;
wire [0:8] reset_w_addr_q;
assign tiup = 1'b1;
assign reset_act = pc_iu_init_reset;
assign reset_w_addr_d[0:8] = reset_w_addr_q[0:8] + 9'b000000001;
assign data_out0 = data_out_q[0];
assign data_out1 = data_out_q[1];
assign data_out2 = data_out_q[2];
assign data_out3 = data_out_q[3];
assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[0:8] == r_addr[0:8]) & r_act == 1'b1)));
assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[0:8];
assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0];
assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[1];
assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[2];
assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[3];
assign ary_w_sel[4] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[5] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[6] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[7] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[8] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[9] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[10] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[11] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[12] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[13] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[14] = reset_act ? 1'b1 : 1'b0;
assign ary_w_sel[15] = reset_act ? 1'b1 : 1'b0;
assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000:
{data_in, data_in, data_in, data_in, 12'b000000000000};
assign ary_r_en = r_act;
assign ary_r_addr[0:8] = r_addr[0:8];
assign data_out[0:3] = ary_r_data[0:3];
//write through support
assign data_in_d = data_in;
assign w_act_d[0:3] = w_act[0:3];
assign r_act_d = r_act;
assign w_addr_d[0:8] = w_addr[0:8];
assign r_addr_d[0:8] = r_addr[0:8];
assign write_thru[0:3] = ((w_addr_q[0:8] == r_addr_q[0:8]) & r_act_q == 1'b1) ? w_act_q[0:3] :
4'b0000;
assign data_out_d[0] = (write_thru[0] == 1'b1) ? data_in_q :
data_out[0];
assign data_out_d[1] = (write_thru[1] == 1'b1) ? data_in_q :
data_out[1];
assign data_out_d[2] = (write_thru[2] == 1'b1) ? data_in_q :
data_out[2];
assign data_out_d[3] = (write_thru[3] == 1'b1) ? data_in_q :
data_out[3];
//latch acts
assign lat_wi_act = |(w_act[0:3]);
assign lat_ri_act = r_act;
assign lat_ro_act = r_act_q;
//-----------------------------------------------
// array
//-----------------------------------------------
tri_512x16_1r1w_1 bht0(
.gnd(gnd),
.vdd(vdd),
.vcs(vcs),
.nclk(nclk),
.rd_act(ary_r_en),
.wr_act(ary_w_en),
.lcb_d_mode_dc(g8t_d_mode),
.lcb_clkoff_dc_b(g8t_clkoff_b),
.lcb_mpw1_dc_b(g8t_mpw1_b),
.lcb_mpw2_dc_b(g8t_mpw2_b),
.lcb_delay_lclkr_dc(g8t_delay_lclkr),
.ccflush_dc(tc_ac_ccflush_dc),
.scan_dis_dc_b(tc_ac_scan_dis_dc_b),
.scan_diag_dc(scan_diag_dc),
.func_scan_in(siv[array_offset]),
.func_scan_out(sov[array_offset]),
.lcb_sg_0(pc_iu_sg_0),
.lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.lcb_time_sl_thold_0(pc_iu_time_sl_thold_0),
.lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0),
.lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0),
.lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0),
.time_scan_in(time_scan_in),
.time_scan_out(time_scan_out),
.abst_scan_in(abst_scan_in),
.abst_scan_out(abst_scan_out),
.repr_scan_in(repr_scan_in),
.repr_scan_out(repr_scan_out),
.abist_di(pc_iu_abist_di_0),
.abist_bw_odd(pc_iu_abist_g8t_bw_1),
.abist_bw_even(pc_iu_abist_g8t_bw_0),
.abist_wr_adr(pc_iu_abist_waddr_0),
.wr_abst_act(pc_iu_abist_g8t_wenb),
.abist_rd0_adr(pc_iu_abist_raddr_0),
.rd0_abst_act(pc_iu_abist_g8t1p_renb_0),
.tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
.abist_ena_1(pc_iu_abist_ena_dc),
.abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena),
.abist_raw_dc_b(pc_iu_abist_raw_dc_b),
.obs0_abist_cmp(pc_iu_abist_g8t_dcomp),
.lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0),
.pc_bo_enable_2(pc_iu_bo_enable_2),
.pc_bo_reset(pc_iu_bo_reset),
.pc_bo_unload(pc_iu_bo_unload),
.pc_bo_repair(pc_iu_bo_repair),
.pc_bo_shdata(pc_iu_bo_shdata),
.pc_bo_select(pc_iu_bo_select),
.bo_pc_failout(iu_pc_bo_fail),
.bo_pc_diagloop(iu_pc_bo_diagout),
.tri_lcb_mpw1_dc_b(mpw1_b),
.tri_lcb_mpw2_dc_b(mpw2_b),
.tri_lcb_delay_lclkr_dc(delay_lclkr),
.tri_lcb_clkoff_dc_b(clkoff_b),
.tri_lcb_act_dis_dc(act_dis),
.bw(ary_w_sel),
.wr_adr(ary_w_addr),
.rd_adr(ary_r_addr),
.di(ary_w_data),
.do(ary_r_data)
);
//-----------------------------------------------
// latches
//-----------------------------------------------
tri_rlmlatch_p #(.INIT(0)) data_in_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[data_in_offset:data_in_offset]),
.scout(sov[data_in_offset:data_in_offset]),
.din(data_in_d),
.dout(data_in_q)
);
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[w_act_offset:w_act_offset + 4 - 1]),
.scout(sov[w_act_offset:w_act_offset + 4 - 1]),
.din(w_act_d),
.dout(w_act_q)
);
tri_rlmlatch_p #(.INIT(0)) r_act_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[r_act_offset]),
.scout(sov[r_act_offset]),
.din(r_act_d),
.dout(r_act_q)
);
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) w_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[w_addr_offset:w_addr_offset + 9 - 1]),
.scout(sov[w_addr_offset:w_addr_offset + 9 - 1]),
.din(w_addr_d),
.dout(w_addr_q)
);
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) r_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_ri_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[r_addr_offset:r_addr_offset + 9 - 1]),
.scout(sov[r_addr_offset:r_addr_offset + 9 - 1]),
.din(r_addr_d),
.dout(r_addr_q)
);
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) data_out_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(lat_ro_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[data_out_offset:data_out_offset + 4 - 1]),
.scout(sov[data_out_offset:data_out_offset + 4 - 1]),
.din(data_out_d),
.dout(data_out_q)
);
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.act(reset_act),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),
.force_t(force_t),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.d_mode(d_mode),
.scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
.scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
.din(reset_w_addr_d),
.dout(reset_w_addr_q)
);
//-----------------------------------------------
// pervasive
//-----------------------------------------------
tri_plat #(.WIDTH(7)) perv_2to1_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}),
.q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1})
);
tri_plat #(.WIDTH(7)) perv_1to0_reg(
.vd(vdd),
.gd(gnd),
.nclk(nclk),
.flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}),
.q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0})
);
tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b),
.thold(pc_iu_func_sl_thold_0),
.sg(pc_iu_sg_0),
.act_dis(act_dis),
.force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b)
);
//-----------------------------------------------
// scan
//-----------------------------------------------
assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]};
assign func_scan_out = sov[scan_right];
endmodule |
module tri_nand2_nlats(
vd,
gd,
lclk,
d1clk,
d2clk,
scanin,
scanout,
a1,
a2,
qb
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "NLA0001_X1_A12TH";
parameter NEEDS_SRESET = 1; // for inferred latches
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] lclk;
input d1clk;
input d2clk;
input [OFFSET:OFFSET+WIDTH-1] scanin;
output [OFFSET:OFFSET+WIDTH-1] scanout;
input [OFFSET:OFFSET+WIDTH-1] a1;
input [OFFSET:OFFSET+WIDTH-1] a2;
output [OFFSET:OFFSET+WIDTH-1] qb;
// tri_nand2_nlats
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
wire [0:WIDTH-1] din;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign din = a1 & a2; // Output is inverted, so just AND2 here
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{d1clk}};
assign vact_b = {WIDTH{~d1clk}};
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};
always @(posedge lclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign qb = (~int_dout);
assign scanout = ZEROS;
assign unused = | {vd, gd, lclk, scanin};
end
endgenerate
endmodule |
module tri_aoi22_nlats_wlcb(
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
scout,
a1,
a2,
b1,
b2,
qb
);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter IBUF = 1'b0; //inverted latch IOs, if set to true.
parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius
parameter NEEDS_SRESET = 1; // for inferred latches
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "NLL0001_X2_A12TH";
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock
input d_mode; // 1: disable pulse mode, 0: pulse mode
input sg; // 0: functional, 1: scan
input delay_lclkr; // 0: functional
input mpw1_b; // pulse width control bit
input mpw2_b; // pulse width control bit
input [OFFSET:OFFSET+WIDTH-1] scin; // scan in
output [OFFSET:OFFSET+WIDTH-1] scout;
input [OFFSET:OFFSET+WIDTH-1] a1;
input [OFFSET:OFFSET+WIDTH-1] a2;
input [OFFSET:OFFSET+WIDTH-1] b1;
input [OFFSET:OFFSET+WIDTH-1] b2;
output [OFFSET:OFFSET+WIDTH-1] qb;
// tri_aoi22_nlats_wlcb
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
wire [0:WIDTH-1] din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1)
begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign din = (a1 & a2) | (b1 & b2); // Output is inverted, so just AND-OR here
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{act | force_t}};
assign vact_b = {WIDTH{~(act | force_t)}};
assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}};
always @(posedge nclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign qb = (~int_dout);
assign scout = ZEROS;
assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk) | (|scin);
end
endgenerate
endmodule |
module tri_plat(vd, gd, nclk, flush, din, q);
parameter WIDTH = 1;
parameter OFFSET = 0;
parameter INIT = 0; // will be converted to the least signficant 31 bits of init_v
parameter SYNTHCLONEDLATCH = "";
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input flush;
input [OFFSET:OFFSET+WIDTH-1] din;
output [OFFSET:OFFSET+WIDTH-1] q;
// tri_plat
reg [OFFSET:OFFSET+WIDTH-1] int_dout;
(* analysis_not_referenced="true" *)
wire unused;
assign unused = | {vd, gd, nclk[1:`NCLK_WIDTH-1]};
always @ (posedge nclk[0])
begin
int_dout <= din;
end
assign q = (flush == 1'b1) ? din : int_dout ;
endmodule |
module tri_csa22(
a,
b,
car,
sum
);
input a;
input b;
output car;
output sum;
wire car_b;
wire sum_b;
assign car_b = (~(a & b));
assign sum_b = (~(car_b & (a | b))); // this is equiv to an xnor
assign car = (~car_b);
assign sum = (~sum_b);
endmodule |
module tri_fu_mul_bthmux(
x,
sneg,
sx,
sx2,
right,
left,
q
);
input x;
input sneg; // do not flip the input (add)
input sx; // shift by 1
input sx2; // shift by 2
input right; // bit from the right (lsb)
output left; // bit from the left
output q; // final output
wire center;
wire q_b;
assign center = x ^ sneg;
assign left = center; //output-- rename, no gate
assign q_b = (~((sx & center) | (sx2 & right)));
assign q = (~q_b); // output--
endmodule |
module tri_lcbcntl_array_mac(
vdd,
gnd,
sg,
nclk,
scan_in,
scan_diag_dc,
thold,
clkoff_dc_b,
delay_lclkr_dc,
act_dis_dc,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
scan_out
);
inout vdd;
inout gnd;
input sg;
input [0:`NCLK_WIDTH-1] nclk;
input scan_in;
input scan_diag_dc;
input thold;
output clkoff_dc_b;
output [0:4] delay_lclkr_dc;
output act_dis_dc;
output d_mode_dc;
output [0:4] mpw1_dc_b;
output mpw2_dc_b;
output scan_out;
// tri_lcbcntl_array_mac
(* analysis_not_referenced="true" *)
wire unused;
assign clkoff_dc_b = 1'b1;
assign delay_lclkr_dc = 5'b00000;
assign act_dis_dc = 1'b0;
assign d_mode_dc = 1'b0;
assign mpw1_dc_b = 5'b11111;
assign mpw2_dc_b = 1'b1;
assign scan_out = 1'b0;
assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold;
endmodule |
module tri_st_rot_mask(
mb,
me_b,
zm,
mb_gt_me,
mask
);
input [0:5] mb; // where the mask begins
input [0:5] me_b; // where the mask ends
input zm; // set mask to all zeroes. ... not a rot/sh op ... all bits are shifted out
input mb_gt_me;
output [0:63] mask; // mask shows which rotator bits to keep in the result.
wire mask_en_and;
wire mask_en_mb;
wire mask_en_me;
wire [0:63] mask0_b;
wire [0:63] mask1_b;
wire [0:63] mask2_b;
wire [0:63] mb_mask;
wire [0:63] me_mask;
wire [0:2] mb_msk45;
wire [0:2] mb_msk45_b;
wire [0:2] mb_msk23;
wire [0:2] mb_msk23_b;
wire [0:2] mb_msk01;
wire [0:2] mb_msk01_b;
wire [0:14] mb_msk25;
wire [0:14] mb_msk25_b;
wire [0:2] mb_msk01bb;
wire [0:2] mb_msk01bbb;
wire [1:3] me_msk01;
wire [1:3] me_msk01_b;
wire [1:3] me_msk23;
wire [1:3] me_msk23_b;
wire [1:3] me_msk45;
wire [1:3] me_msk45_b;
wire [1:15] me_msk25;
wire [1:15] me_msk25_b;
wire [1:3] me_msk01bbb;
wire [1:3] me_msk01bb;
// -----------------------------------------------------------------------------------------
// generate the MB mask
// -----------------------------------------------------------------------------------------
// 0123
// ------
// 00 => 1111 (ge)
// 01 => 0111
// 10 => 0011
// 11 => 0001
// level 1 (4 bit results) ------------ <3 loads on input>
assign mb_msk45[0] = (~(mb[4] | mb[5]));
assign mb_msk45[1] = (~(mb[4]));
assign mb_msk45[2] = (~(mb[4] & mb[5]));
assign mb_msk23[0] = (~(mb[2] | mb[3]));
assign mb_msk23[1] = (~(mb[2]));
assign mb_msk23[2] = (~(mb[2] & mb[3]));
assign mb_msk01[0] = (~(mb[0] | mb[1]));
assign mb_msk01[1] = (~(mb[0]));
assign mb_msk01[2] = (~(mb[0] & mb[1]));
assign mb_msk45_b[0] = (~(mb_msk45[0]));
assign mb_msk45_b[1] = (~(mb_msk45[1]));
assign mb_msk45_b[2] = (~(mb_msk45[2]));
assign mb_msk23_b[0] = (~(mb_msk23[0])); // 7 loads on output
assign mb_msk23_b[1] = (~(mb_msk23[1]));
assign mb_msk23_b[2] = (~(mb_msk23[2]));
assign mb_msk01_b[0] = (~(mb_msk01[0]));
assign mb_msk01_b[1] = (~(mb_msk01[1]));
assign mb_msk01_b[2] = (~(mb_msk01[2]));
// level 2 (16 bit results) -------------
assign mb_msk25[0] = (~(mb_msk23_b[0] | mb_msk45_b[0]));
assign mb_msk25[1] = (~(mb_msk23_b[0] | mb_msk45_b[1]));
assign mb_msk25[2] = (~(mb_msk23_b[0] | mb_msk45_b[2]));
assign mb_msk25[3] = (~(mb_msk23_b[0]));
assign mb_msk25[4] = (~(mb_msk23_b[0] & (mb_msk23_b[1] | mb_msk45_b[0])));
assign mb_msk25[5] = (~(mb_msk23_b[0] & (mb_msk23_b[1] | mb_msk45_b[1])));
assign mb_msk25[6] = (~(mb_msk23_b[0] & (mb_msk23_b[1] | mb_msk45_b[2])));
assign mb_msk25[7] = (~(mb_msk23_b[1]));
assign mb_msk25[8] = (~(mb_msk23_b[1] & (mb_msk23_b[2] | mb_msk45_b[0])));
assign mb_msk25[9] = (~(mb_msk23_b[1] & (mb_msk23_b[2] | mb_msk45_b[1])));
assign mb_msk25[10] = (~(mb_msk23_b[1] & (mb_msk23_b[2] | mb_msk45_b[2])));
assign mb_msk25[11] = (~(mb_msk23_b[2]));
assign mb_msk25[12] = (~(mb_msk23_b[2] & mb_msk45_b[0]));
assign mb_msk25[13] = (~(mb_msk23_b[2] & mb_msk45_b[1]));
assign mb_msk25[14] = (~(mb_msk23_b[2] & mb_msk45_b[2]));
assign mb_msk01bb[0] = (~(mb_msk01_b[0]));
assign mb_msk01bb[1] = (~(mb_msk01_b[1]));
assign mb_msk01bb[2] = (~(mb_msk01_b[2]));
assign mb_msk25_b[0] = (~(mb_msk25[0]));
assign mb_msk25_b[1] = (~(mb_msk25[1]));
assign mb_msk25_b[2] = (~(mb_msk25[2]));
assign mb_msk25_b[3] = (~(mb_msk25[3]));
assign mb_msk25_b[4] = (~(mb_msk25[4]));
assign mb_msk25_b[5] = (~(mb_msk25[5]));
assign mb_msk25_b[6] = (~(mb_msk25[6]));
assign mb_msk25_b[7] = (~(mb_msk25[7]));
assign mb_msk25_b[8] = (~(mb_msk25[8]));
assign mb_msk25_b[9] = (~(mb_msk25[9]));
assign mb_msk25_b[10] = (~(mb_msk25[10]));
assign mb_msk25_b[11] = (~(mb_msk25[11]));
assign mb_msk25_b[12] = (~(mb_msk25[12]));
assign mb_msk25_b[13] = (~(mb_msk25[13]));
assign mb_msk25_b[14] = (~(mb_msk25[14]));
assign mb_msk01bbb[0] = (~(mb_msk01bb[0]));
assign mb_msk01bbb[1] = (~(mb_msk01bb[1]));
assign mb_msk01bbb[2] = (~(mb_msk01bb[2]));
// level 3 -------------------------------------------------------
assign mb_mask[0] = (~(mb_msk01bbb[0] | mb_msk25_b[0]));
assign mb_mask[1] = (~(mb_msk01bbb[0] | mb_msk25_b[1]));
assign mb_mask[2] = (~(mb_msk01bbb[0] | mb_msk25_b[2]));
assign mb_mask[3] = (~(mb_msk01bbb[0] | mb_msk25_b[3]));
assign mb_mask[4] = (~(mb_msk01bbb[0] | mb_msk25_b[4]));
assign mb_mask[5] = (~(mb_msk01bbb[0] | mb_msk25_b[5]));
assign mb_mask[6] = (~(mb_msk01bbb[0] | mb_msk25_b[6]));
assign mb_mask[7] = (~(mb_msk01bbb[0] | mb_msk25_b[7]));
assign mb_mask[8] = (~(mb_msk01bbb[0] | mb_msk25_b[8]));
assign mb_mask[9] = (~(mb_msk01bbb[0] | mb_msk25_b[9]));
assign mb_mask[10] = (~(mb_msk01bbb[0] | mb_msk25_b[10]));
assign mb_mask[11] = (~(mb_msk01bbb[0] | mb_msk25_b[11]));
assign mb_mask[12] = (~(mb_msk01bbb[0] | mb_msk25_b[12]));
assign mb_mask[13] = (~(mb_msk01bbb[0] | mb_msk25_b[13]));
assign mb_mask[14] = (~(mb_msk01bbb[0] | mb_msk25_b[14]));
assign mb_mask[15] = (~(mb_msk01bbb[0]));
assign mb_mask[16] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[0])));
assign mb_mask[17] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[1])));
assign mb_mask[18] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[2])));
assign mb_mask[19] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[3])));
assign mb_mask[20] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[4])));
assign mb_mask[21] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[5])));
assign mb_mask[22] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[6])));
assign mb_mask[23] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[7])));
assign mb_mask[24] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[8])));
assign mb_mask[25] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[9])));
assign mb_mask[26] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[10])));
assign mb_mask[27] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[11])));
assign mb_mask[28] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[12])));
assign mb_mask[29] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[13])));
assign mb_mask[30] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[14])));
assign mb_mask[31] = (~(mb_msk01bbb[1]));
assign mb_mask[32] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[0])));
assign mb_mask[33] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[1])));
assign mb_mask[34] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[2])));
assign mb_mask[35] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[3])));
assign mb_mask[36] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[4])));
assign mb_mask[37] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[5])));
assign mb_mask[38] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[6])));
assign mb_mask[39] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[7])));
assign mb_mask[40] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[8])));
assign mb_mask[41] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[9])));
assign mb_mask[42] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[10])));
assign mb_mask[43] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[11])));
assign mb_mask[44] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[12])));
assign mb_mask[45] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[13])));
assign mb_mask[46] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[14])));
assign mb_mask[47] = (~(mb_msk01bbb[2]));
assign mb_mask[48] = (~(mb_msk01bbb[2] & mb_msk25_b[0]));
assign mb_mask[49] = (~(mb_msk01bbb[2] & mb_msk25_b[1]));
assign mb_mask[50] = (~(mb_msk01bbb[2] & mb_msk25_b[2]));
assign mb_mask[51] = (~(mb_msk01bbb[2] & mb_msk25_b[3]));
assign mb_mask[52] = (~(mb_msk01bbb[2] & mb_msk25_b[4]));
assign mb_mask[53] = (~(mb_msk01bbb[2] & mb_msk25_b[5]));
assign mb_mask[54] = (~(mb_msk01bbb[2] & mb_msk25_b[6]));
assign mb_mask[55] = (~(mb_msk01bbb[2] & mb_msk25_b[7]));
assign mb_mask[56] = (~(mb_msk01bbb[2] & mb_msk25_b[8]));
assign mb_mask[57] = (~(mb_msk01bbb[2] & mb_msk25_b[9]));
assign mb_mask[58] = (~(mb_msk01bbb[2] & mb_msk25_b[10]));
assign mb_mask[59] = (~(mb_msk01bbb[2] & mb_msk25_b[11]));
assign mb_mask[60] = (~(mb_msk01bbb[2] & mb_msk25_b[12]));
assign mb_mask[61] = (~(mb_msk01bbb[2] & mb_msk25_b[13]));
assign mb_mask[62] = (~(mb_msk01bbb[2] & mb_msk25_b[14]));
assign mb_mask[63] = 1;
// -----------------------------------------------------------------------------------------
// generate the ME mask
// -----------------------------------------------------------------------------------------
// level 1 (4 bit results) ------------ <3 loads on input>
assign me_msk45[1] = (~(me_b[4] & me_b[5]));
assign me_msk45[2] = (~(me_b[4]));
assign me_msk45[3] = (~(me_b[4] | me_b[5]));
assign me_msk23[1] = (~(me_b[2] & me_b[3]));
assign me_msk23[2] = (~(me_b[2]));
assign me_msk23[3] = (~(me_b[2] | me_b[3]));
assign me_msk01[1] = (~(me_b[0] & me_b[1]));
assign me_msk01[2] = (~(me_b[0]));
assign me_msk01[3] = (~(me_b[0] | me_b[1]));
assign me_msk45_b[1] = (~(me_msk45[1]));
assign me_msk45_b[2] = (~(me_msk45[2]));
assign me_msk45_b[3] = (~(me_msk45[3]));
assign me_msk23_b[1] = (~(me_msk23[1])); // 7 loads on output
assign me_msk23_b[2] = (~(me_msk23[2]));
assign me_msk23_b[3] = (~(me_msk23[3]));
assign me_msk01_b[1] = (~(me_msk01[1]));
assign me_msk01_b[2] = (~(me_msk01[2]));
assign me_msk01_b[3] = (~(me_msk01[3]));
// level 2 (16 bit results) -------------
assign me_msk25[1] = (~(me_msk23_b[1] & me_msk45_b[1])); // amt >= 1 4:15 + 1:3
assign me_msk25[2] = (~(me_msk23_b[1] & me_msk45_b[2])); // amt >= 2 4:15 + 2:3
assign me_msk25[3] = (~(me_msk23_b[1] & me_msk45_b[3])); // amt >= 3 4:15 + 3:3
assign me_msk25[4] = (~(me_msk23_b[1])); // amt >= 4 4:15
assign me_msk25[5] = (~(me_msk23_b[2] & (me_msk23_b[1] | me_msk45_b[1]))); // amt >= 5 8:15 + (4:15 * 1:3)
assign me_msk25[6] = (~(me_msk23_b[2] & (me_msk23_b[1] | me_msk45_b[2]))); // amt >= 6 8:15 + (4:15 * 2:3)
assign me_msk25[7] = (~(me_msk23_b[2] & (me_msk23_b[1] | me_msk45_b[3]))); // amt >= 7 8:15 + (4:15 * 3:3)
assign me_msk25[8] = (~(me_msk23_b[2])); // amt >= 8 8:15
assign me_msk25[9] = (~(me_msk23_b[3] & (me_msk23_b[2] | me_msk45_b[1]))); // amt >= 9 12:15 + (8:15 * 1:3)
assign me_msk25[10] = (~(me_msk23_b[3] & (me_msk23_b[2] | me_msk45_b[2]))); // amt >= 10 12:15 + (8:15 * 2:3)
assign me_msk25[11] = (~(me_msk23_b[3] & (me_msk23_b[2] | me_msk45_b[3]))); // amt >= 11 12:15 + (8:15 * 3:3)
assign me_msk25[12] = (~(me_msk23_b[3])); // amt >= 12 12:15
assign me_msk25[13] = (~(me_msk23_b[3] | me_msk45_b[1])); // amt >= 13 12:15 & 1:3
assign me_msk25[14] = (~(me_msk23_b[3] | me_msk45_b[2])); // amt >= 14 12:15 & 2:3
assign me_msk25[15] = (~(me_msk23_b[3] | me_msk45_b[3])); // amt >= 15 12:15 & 3:3
assign me_msk01bb[1] = (~(me_msk01_b[1]));
assign me_msk01bb[2] = (~(me_msk01_b[2]));
assign me_msk01bb[3] = (~(me_msk01_b[3]));
assign me_msk25_b[1] = (~(me_msk25[1]));
assign me_msk25_b[2] = (~(me_msk25[2]));
assign me_msk25_b[3] = (~(me_msk25[3]));
assign me_msk25_b[4] = (~(me_msk25[4]));
assign me_msk25_b[5] = (~(me_msk25[5]));
assign me_msk25_b[6] = (~(me_msk25[6]));
assign me_msk25_b[7] = (~(me_msk25[7]));
assign me_msk25_b[8] = (~(me_msk25[8]));
assign me_msk25_b[9] = (~(me_msk25[9]));
assign me_msk25_b[10] = (~(me_msk25[10]));
assign me_msk25_b[11] = (~(me_msk25[11]));
assign me_msk25_b[12] = (~(me_msk25[12]));
assign me_msk25_b[13] = (~(me_msk25[13]));
assign me_msk25_b[14] = (~(me_msk25[14]));
assign me_msk25_b[15] = (~(me_msk25[15]));
assign me_msk01bbb[1] = (~(me_msk01bb[1]));
assign me_msk01bbb[2] = (~(me_msk01bb[2]));
assign me_msk01bbb[3] = (~(me_msk01bb[3]));
// level 3 (16 bit results) -------------
assign me_mask[0] = 1;
assign me_mask[1] = (~(me_msk01bbb[1] & me_msk25_b[1]));
assign me_mask[2] = (~(me_msk01bbb[1] & me_msk25_b[2]));
assign me_mask[3] = (~(me_msk01bbb[1] & me_msk25_b[3]));
assign me_mask[4] = (~(me_msk01bbb[1] & me_msk25_b[4]));
assign me_mask[5] = (~(me_msk01bbb[1] & me_msk25_b[5]));
assign me_mask[6] = (~(me_msk01bbb[1] & me_msk25_b[6]));
assign me_mask[7] = (~(me_msk01bbb[1] & me_msk25_b[7]));
assign me_mask[8] = (~(me_msk01bbb[1] & me_msk25_b[8]));
assign me_mask[9] = (~(me_msk01bbb[1] & me_msk25_b[9]));
assign me_mask[10] = (~(me_msk01bbb[1] & me_msk25_b[10]));
assign me_mask[11] = (~(me_msk01bbb[1] & me_msk25_b[11]));
assign me_mask[12] = (~(me_msk01bbb[1] & me_msk25_b[12]));
assign me_mask[13] = (~(me_msk01bbb[1] & me_msk25_b[13]));
assign me_mask[14] = (~(me_msk01bbb[1] & me_msk25_b[14]));
assign me_mask[15] = (~(me_msk01bbb[1] & me_msk25_b[15]));
assign me_mask[16] = (~(me_msk01bbb[1]));
assign me_mask[17] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[1])));
assign me_mask[18] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[2])));
assign me_mask[19] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[3])));
assign me_mask[20] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[4])));
assign me_mask[21] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[5])));
assign me_mask[22] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[6])));
assign me_mask[23] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[7])));
assign me_mask[24] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[8])));
assign me_mask[25] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[9])));
assign me_mask[26] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[10])));
assign me_mask[27] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[11])));
assign me_mask[28] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[12])));
assign me_mask[29] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[13])));
assign me_mask[30] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[14])));
assign me_mask[31] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[15])));
assign me_mask[32] = (~(me_msk01bbb[2]));
assign me_mask[33] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[1])));
assign me_mask[34] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[2])));
assign me_mask[35] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[3])));
assign me_mask[36] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[4])));
assign me_mask[37] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[5])));
assign me_mask[38] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[6])));
assign me_mask[39] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[7])));
assign me_mask[40] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[8])));
assign me_mask[41] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[9])));
assign me_mask[42] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[10])));
assign me_mask[43] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[11])));
assign me_mask[44] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[12])));
assign me_mask[45] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[13])));
assign me_mask[46] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[14])));
assign me_mask[47] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[15])));
assign me_mask[48] = (~(me_msk01bbb[3]));
assign me_mask[49] = (~(me_msk01bbb[3] | me_msk25_b[1]));
assign me_mask[50] = (~(me_msk01bbb[3] | me_msk25_b[2]));
assign me_mask[51] = (~(me_msk01bbb[3] | me_msk25_b[3]));
assign me_mask[52] = (~(me_msk01bbb[3] | me_msk25_b[4]));
assign me_mask[53] = (~(me_msk01bbb[3] | me_msk25_b[5]));
assign me_mask[54] = (~(me_msk01bbb[3] | me_msk25_b[6]));
assign me_mask[55] = (~(me_msk01bbb[3] | me_msk25_b[7]));
assign me_mask[56] = (~(me_msk01bbb[3] | me_msk25_b[8]));
assign me_mask[57] = (~(me_msk01bbb[3] | me_msk25_b[9]));
assign me_mask[58] = (~(me_msk01bbb[3] | me_msk25_b[10]));
assign me_mask[59] = (~(me_msk01bbb[3] | me_msk25_b[11]));
assign me_mask[60] = (~(me_msk01bbb[3] | me_msk25_b[12]));
assign me_mask[61] = (~(me_msk01bbb[3] | me_msk25_b[13]));
assign me_mask[62] = (~(me_msk01bbb[3] | me_msk25_b[14]));
assign me_mask[63] = (~(me_msk01bbb[3] | me_msk25_b[15]));
// ------------------------------------------------------------------------------------------
// Generally the mask starts at bit MB[] and ends at bit ME[] ... (MB[] and ME[])
// For non-rotate/shift operations the mask is forced to zero by the ZM control.
// There are 3 rotate-word operations where MB could be greater than ME.
// in that case the mask is speced to be (MB[] or ME[]).
// For those cases, the mask always comes from the instruction bits, is always word mode,
// and the MB>ME compare can be done during the instruction decode cycle.
// -------------------------------------------------------------------------------------------
assign mask_en_and = (~mb_gt_me) & (~zm); // could restrict this to only rotates if shifts included below
assign mask_en_mb = mb_gt_me & (~zm); // could alternatively include shift right
assign mask_en_me = mb_gt_me & (~zm); // could alternatively include shift left
assign mask0_b[0:63] = (~(mb_mask[0:63] & me_mask[0:63] & {64{mask_en_and}}));
assign mask1_b[0:63] = (~(mb_mask[0:63] & {64{mask_en_mb}}));
assign mask2_b[0:63] = (~(me_mask[0:63] & {64{mask_en_me}}));
assign mask[0:63] = (~(mask0_b[0:63] & mask1_b[0:63] & mask2_b[0:63]));
endmodule |
module tri_rot16_lu(
rot_sel1,
rot_sel2,
rot_sel3,
rot_data,
data_rot,
vdd,
gnd
);
// Rotator Controls and Data
input [0:7] rot_sel1;
input [0:7] rot_sel2;
input [0:7] rot_sel3;
input [0:15] rot_data;
// Rotated Data
output [0:15] data_rot;
// Pervasive
inout vdd;
inout gnd;
// tri_rot16_lu
wire [0:15] mxbele_d0;
wire [0:15] mxbele_d1;
wire [0:15] bele_s0;
wire [0:15] bele_s1;
wire [0:15] mxbele_b;
wire [0:15] mxbele;
wire [0:15] mx1_d0;
wire [0:15] mx1_d1;
wire [0:15] mx1_d2;
wire [0:15] mx1_d3;
wire [0:15] mx2_d0;
wire [0:15] mx2_d1;
wire [0:15] mx2_d2;
wire [0:15] mx2_d3;
wire [0:15] mx1_s0;
wire [0:15] mx1_s1;
wire [0:15] mx1_s2;
wire [0:15] mx1_s3;
wire [0:15] mx2_s0;
wire [0:15] mx2_s1;
wire [0:15] mx2_s2;
wire [0:15] mx2_s3;
wire [0:15] mx1_0_b;
wire [0:15] mx1_1_b;
wire [0:15] mx1;
wire [0:15] mx2_0_b;
wire [0:15] mx2_1_b;
wire [0:15] mx2;
(* analysis_not_referenced="true" *)
wire unused;
assign unused = vdd | gnd;
// #############################################################################################
// 16 Byte Rotator
// B0 => data(0:7) B8 => data(64:71)
// B1 => data(8:15) B9 => data(72:79)
// B2 => data(16:23) B10 => data(80:87)
// B3 => data(24:31) B11 => data(88:95)
// B4 => data(32:39) B12 => data(96:103)
// B5 => data(40:47) B13 => data(104:111)
// B6 => data(48:55) B14 => data(112:119)
// B7 => data(56:63) B15 => data(120:127)
// #############################################################################################
//-- 0,1,2,3 byte rotation
//with rot_sel(2 to 3) select
// rot3210 <= rot_data(24 to 127) & rot_data(0 to 23) when "11",
// rot_data(16 to 127) & rot_data(0 to 15) when "10",
// rot_data(8 to 127) & rot_data(0 to 7) when "01",
// rot_data(0 to 127) when others;
//
//-- 0-3,4,8,12 byte rotation
//with rot_sel(0 to 1) select
// rotC840 <= rot3210(96 to 127) & rot3210(0 to 95) when "11",
// rot3210(64 to 127) & rot3210(0 to 63) when "10",
// rot3210(32 to 127) & rot3210(0 to 31) when "01",
// rot3210(0 to 127) when others;
// ----------------------------------------------------------------------------------------
// Little/Big Endian Muxing
// ----------------------------------------------------------------------------------------
assign bele_s0[0:3] = {4{rot_sel1[0]}};
assign bele_s0[4:7] = {4{rot_sel1[2]}};
assign bele_s0[8:11] = {4{rot_sel1[4]}};
assign bele_s0[12:15] = {4{rot_sel1[6]}};
assign bele_s1[0:3] = {4{rot_sel1[1]}};
assign bele_s1[4:7] = {4{rot_sel1[3]}};
assign bele_s1[8:11] = {4{rot_sel1[5]}};
assign bele_s1[12:15] = {4{rot_sel1[7]}};
assign mxbele_d0[0] = rot_data[0]; assign mxbele_d1[0] = rot_data[15];
assign mxbele_d0[1] = rot_data[1]; assign mxbele_d1[1] = rot_data[14];
assign mxbele_d0[2] = rot_data[2]; assign mxbele_d1[2] = rot_data[13];
assign mxbele_d0[3] = rot_data[3]; assign mxbele_d1[3] = rot_data[12];
assign mxbele_d0[4] = rot_data[4]; assign mxbele_d1[4] = rot_data[11];
assign mxbele_d0[5] = rot_data[5]; assign mxbele_d1[5] = rot_data[10];
assign mxbele_d0[6] = rot_data[6]; assign mxbele_d1[6] = rot_data[9];
assign mxbele_d0[7] = rot_data[7]; assign mxbele_d1[7] = rot_data[8];
assign mxbele_d0[8] = rot_data[8]; assign mxbele_d1[8] = rot_data[7];
assign mxbele_d0[9] = rot_data[9]; assign mxbele_d1[9] = rot_data[6];
assign mxbele_d0[10] = rot_data[10]; assign mxbele_d1[10] = rot_data[5];
assign mxbele_d0[11] = rot_data[11]; assign mxbele_d1[11] = rot_data[4];
assign mxbele_d0[12] = rot_data[12]; assign mxbele_d1[12] = rot_data[3];
assign mxbele_d0[13] = rot_data[13]; assign mxbele_d1[13] = rot_data[2];
assign mxbele_d0[14] = rot_data[14]; assign mxbele_d1[14] = rot_data[1];
assign mxbele_d0[15] = rot_data[15]; assign mxbele_d1[15] = rot_data[0];
tri_aoi22 #(.WIDTH(16)) mxbele_b_0 (.y(mxbele_b[0:15]), .a0(mxbele_d0[0:15]), .a1(bele_s0[0:15]), .b0(mxbele_d1[0:15]), .b1(bele_s1[0:15]));
tri_inv #(.WIDTH(16)) mxbele_0 (.y(mxbele[0:15]), .a(mxbele_b[0:15]));
// ----------------------------------------------------------------------------------------
// First level of muxing <0,4,8,12 bytes>
// ----------------------------------------------------------------------------------------
assign mx1_s0[0:7] = {8{rot_sel2[0]}};
assign mx1_s1[0:7] = {8{rot_sel2[1]}};
assign mx1_s2[0:7] = {8{rot_sel2[2]}};
assign mx1_s3[0:7] = {8{rot_sel2[3]}};
assign mx1_s0[8:15] = {8{rot_sel2[4]}};
assign mx1_s1[8:15] = {8{rot_sel2[5]}};
assign mx1_s2[8:15] = {8{rot_sel2[6]}};
assign mx1_s3[8:15] = {8{rot_sel2[7]}};
assign mx1_d0[0] = mxbele[0]; assign mx1_d1[0] = mxbele[4]; assign mx1_d2[0] = mxbele[8]; assign mx1_d3[0] = mxbele[12];
assign mx1_d0[1] = mxbele[1]; assign mx1_d1[1] = mxbele[5]; assign mx1_d2[1] = mxbele[9]; assign mx1_d3[1] = mxbele[13];
assign mx1_d0[2] = mxbele[2]; assign mx1_d1[2] = mxbele[6]; assign mx1_d2[2] = mxbele[10]; assign mx1_d3[2] = mxbele[14];
assign mx1_d0[3] = mxbele[3]; assign mx1_d1[3] = mxbele[7]; assign mx1_d2[3] = mxbele[11]; assign mx1_d3[3] = mxbele[15];
assign mx1_d0[4] = mxbele[4]; assign mx1_d1[4] = mxbele[8]; assign mx1_d2[4] = mxbele[12]; assign mx1_d3[4] = mxbele[0];
assign mx1_d0[5] = mxbele[5]; assign mx1_d1[5] = mxbele[9]; assign mx1_d2[5] = mxbele[13]; assign mx1_d3[5] = mxbele[1];
assign mx1_d0[6] = mxbele[6]; assign mx1_d1[6] = mxbele[10]; assign mx1_d2[6] = mxbele[14]; assign mx1_d3[6] = mxbele[2];
assign mx1_d0[7] = mxbele[7]; assign mx1_d1[7] = mxbele[11]; assign mx1_d2[7] = mxbele[15]; assign mx1_d3[7] = mxbele[3];
assign mx1_d0[8] = mxbele[8]; assign mx1_d1[8] = mxbele[12]; assign mx1_d2[8] = mxbele[0]; assign mx1_d3[8] = mxbele[4];
assign mx1_d0[9] = mxbele[9]; assign mx1_d1[9] = mxbele[13]; assign mx1_d2[9] = mxbele[1]; assign mx1_d3[9] = mxbele[5];
assign mx1_d0[10] = mxbele[10]; assign mx1_d1[10] = mxbele[14]; assign mx1_d2[10] = mxbele[2]; assign mx1_d3[10] = mxbele[6];
assign mx1_d0[11] = mxbele[11]; assign mx1_d1[11] = mxbele[15]; assign mx1_d2[11] = mxbele[3]; assign mx1_d3[11] = mxbele[7];
assign mx1_d0[12] = mxbele[12]; assign mx1_d1[12] = mxbele[0]; assign mx1_d2[12] = mxbele[4]; assign mx1_d3[12] = mxbele[8];
assign mx1_d0[13] = mxbele[13]; assign mx1_d1[13] = mxbele[1]; assign mx1_d2[13] = mxbele[5]; assign mx1_d3[13] = mxbele[9];
assign mx1_d0[14] = mxbele[14]; assign mx1_d1[14] = mxbele[2]; assign mx1_d2[14] = mxbele[6]; assign mx1_d3[14] = mxbele[10];
assign mx1_d0[15] = mxbele[15]; assign mx1_d1[15] = mxbele[3]; assign mx1_d2[15] = mxbele[7]; assign mx1_d3[15] = mxbele[11];
tri_aoi22 #(.WIDTH(16)) mx1_0_b_0 (.y(mx1_0_b[0:15]), .a0(mx1_s0[0:15]), .a1(mx1_d0[0:15]), .b0(mx1_s1[0:15]), .b1(mx1_d1[0:15]));
tri_aoi22 #(.WIDTH(16)) mx1_1_b_0 (.y(mx1_1_b[0:15]), .a0(mx1_s2[0:15]), .a1(mx1_d2[0:15]), .b0(mx1_s3[0:15]), .b1(mx1_d3[0:15]));
tri_nand2 #(.WIDTH(16)) mx1_0 (.y(mx1[0:15]), .a(mx1_0_b[0:15]), .b(mx1_1_b[0:15]));
// ----------------------------------------------------------------------------------------
// third level of muxing <0,1,2,3 bytes>
// ----------------------------------------------------------------------------------------
assign mx2_s0[0:7] = {8{rot_sel3[0]}};
assign mx2_s1[0:7] = {8{rot_sel3[1]}};
assign mx2_s2[0:7] = {8{rot_sel3[2]}};
assign mx2_s3[0:7] = {8{rot_sel3[3]}};
assign mx2_s0[8:15] = {8{rot_sel3[4]}};
assign mx2_s1[8:15] = {8{rot_sel3[5]}};
assign mx2_s2[8:15] = {8{rot_sel3[6]}};
assign mx2_s3[8:15] = {8{rot_sel3[7]}};
assign mx2_d0[0] = mx1[0]; assign mx2_d1[0] = mx1[1]; assign mx2_d2[0] = mx1[2]; assign mx2_d3[0] = mx1[3];
assign mx2_d0[1] = mx1[1]; assign mx2_d1[1] = mx1[2]; assign mx2_d2[1] = mx1[3]; assign mx2_d3[1] = mx1[4];
assign mx2_d0[2] = mx1[2]; assign mx2_d1[2] = mx1[3]; assign mx2_d2[2] = mx1[4]; assign mx2_d3[2] = mx1[5];
assign mx2_d0[3] = mx1[3]; assign mx2_d1[3] = mx1[4]; assign mx2_d2[3] = mx1[5]; assign mx2_d3[3] = mx1[6];
assign mx2_d0[4] = mx1[4]; assign mx2_d1[4] = mx1[5]; assign mx2_d2[4] = mx1[6]; assign mx2_d3[4] = mx1[7];
assign mx2_d0[5] = mx1[5]; assign mx2_d1[5] = mx1[6]; assign mx2_d2[5] = mx1[7]; assign mx2_d3[5] = mx1[8];
assign mx2_d0[6] = mx1[6]; assign mx2_d1[6] = mx1[7]; assign mx2_d2[6] = mx1[8]; assign mx2_d3[6] = mx1[9];
assign mx2_d0[7] = mx1[7]; assign mx2_d1[7] = mx1[8]; assign mx2_d2[7] = mx1[9]; assign mx2_d3[7] = mx1[10];
assign mx2_d0[8] = mx1[8]; assign mx2_d1[8] = mx1[9]; assign mx2_d2[8] = mx1[10]; assign mx2_d3[8] = mx1[11];
assign mx2_d0[9] = mx1[9]; assign mx2_d1[9] = mx1[10]; assign mx2_d2[9] = mx1[11]; assign mx2_d3[9] = mx1[12];
assign mx2_d0[10] = mx1[10]; assign mx2_d1[10] = mx1[11]; assign mx2_d2[10] = mx1[12]; assign mx2_d3[10] = mx1[13];
assign mx2_d0[11] = mx1[11]; assign mx2_d1[11] = mx1[12]; assign mx2_d2[11] = mx1[13]; assign mx2_d3[11] = mx1[14];
assign mx2_d0[12] = mx1[12]; assign mx2_d1[12] = mx1[13]; assign mx2_d2[12] = mx1[14]; assign mx2_d3[12] = mx1[15];
assign mx2_d0[13] = mx1[13]; assign mx2_d1[13] = mx1[14]; assign mx2_d2[13] = mx1[15]; assign mx2_d3[13] = mx1[0];
assign mx2_d0[14] = mx1[14]; assign mx2_d1[14] = mx1[15]; assign mx2_d2[14] = mx1[0]; assign mx2_d3[14] = mx1[1];
assign mx2_d0[15] = mx1[15]; assign mx2_d1[15] = mx1[0]; assign mx2_d2[15] = mx1[1]; assign mx2_d3[15] = mx1[2];
tri_aoi22 #(.WIDTH(16)) mx2_0_b_0 (.y(mx2_0_b[0:15]), .a0(mx2_s0[0:15]), .a1(mx2_d0[0:15]), .b0(mx2_s1[0:15]), .b1(mx2_d1[0:15]));
tri_aoi22 #(.WIDTH(16)) mx2_1_b_0 (.y(mx2_1_b[0:15]), .a0(mx2_s2[0:15]), .a1(mx2_d2[0:15]), .b0(mx2_s3[0:15]), .b1(mx2_d3[0:15]));
tri_nand2 #(.WIDTH(16)) mx2_0 (.y(mx2[0:15]), .a(mx2_0_b[0:15]), .b(mx2_1_b[0:15]));
// #############################################################################################
// #############################################################################################
// Outputs
// #############################################################################################
assign data_rot = mx2;
// #############################################################################################
endmodule |
module tri_fu_tblmul_bthrow(
x,
s_neg,
s_x,
s_x2,
q
);
input [0:15] x; //
input s_neg; // negate the row
input s_x; // shift by 1
input s_x2; // shift by 2
output [0:16] q; // final output
// ENTITY
parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [0:16] left;
wire unused;
////################################################################
////# A row of the repeated part of the booth_mux row
////################################################################
assign unused = left[0];
tri_fu_mul_bthmux u00(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(tidn), //i-- ********
.left(left[0]), //o-- [n]
.right(left[1]), //i-- [n+1]
.q(q[0]) //o--
);
tri_fu_mul_bthmux u01(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[0]), //i-- [n-1]
.left(left[1]), //o-- [n]
.right(left[2]), //i-- [n+1]
.q(q[1]) //o--
);
tri_fu_mul_bthmux u02(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[1]), //i--
.left(left[2]), //o--
.right(left[3]), //i--
.q(q[2]) //o--
);
tri_fu_mul_bthmux u03(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[2]), //i--
.left(left[3]), //o--
.right(left[4]), //i--
.q(q[3]) //o--
);
tri_fu_mul_bthmux u04(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[3]), //i--
.left(left[4]), //o--
.right(left[5]), //i--
.q(q[4]) //o--
);
tri_fu_mul_bthmux u05(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[4]), //i--
.left(left[5]), //o--
.right(left[6]), //i--
.q(q[5]) //o--
);
tri_fu_mul_bthmux u06(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[5]), //i--
.left(left[6]), //o--
.right(left[7]), //i--
.q(q[6]) //o--
);
tri_fu_mul_bthmux u07(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[6]), //i--
.left(left[7]), //o--
.right(left[8]), //i--
.q(q[7]) //o--
);
tri_fu_mul_bthmux u08(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[7]), //i--
.left(left[8]), //o--
.right(left[9]), //i--
.q(q[8]) //o--
);
tri_fu_mul_bthmux u09(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[8]), //i--
.left(left[9]), //o--
.right(left[10]), //i--
.q(q[9]) //o--
);
tri_fu_mul_bthmux u10(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[9]), //i--
.left(left[10]), //o--
.right(left[11]), //i--
.q(q[10]) //o--
);
tri_fu_mul_bthmux u11(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[10]), //i--
.left(left[11]), //o--
.right(left[12]), //i--
.q(q[11]) //o--
);
tri_fu_mul_bthmux u12(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[11]), //i--
.left(left[12]), //o--
.right(left[13]), //i--
.q(q[12]) //o--
);
tri_fu_mul_bthmux u13(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[12]), //i--
.left(left[13]), //o--
.right(left[14]), //i--
.q(q[13]) //o--
);
tri_fu_mul_bthmux u14(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[13]), //i--
.left(left[14]), //o--
.right(left[15]), //i--
.q(q[14]) //o--
);
tri_fu_mul_bthmux u15(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[14]), //i--
.left(left[15]), //o--
.right(left[16]), //i--
.q(q[15]) //o--
);
tri_fu_mul_bthmux u16(
.sneg(s_neg), //i--
.sx(s_x), //i--
.sx2(s_x2), //i--
.x(x[15]), //i--
.left(left[16]), //o--
.right(s_neg), //i--
.q(q[16]) //o--
);
endmodule |
module tri_cam_32x143_1r1w1c_matchline(
addr_in,
addr_enable,
comp_pgsize,
pgsize_enable,
entry_size,
entry_cmpmask,
entry_xbit,
entry_xbitmask,
entry_epn,
comp_class,
entry_class,
class_enable,
comp_extclass,
entry_extclass,
extclass_enable,
comp_state,
entry_hv,
entry_ds,
state_enable,
entry_thdid,
comp_thdid,
thdid_enable,
entry_pid,
comp_pid,
pid_enable,
entry_v,
comp_invalidate,
match
);
parameter HAVE_XBIT = 1;
parameter NUM_PGSIZES = 5;
parameter HAVE_CMPMASK = 1;
parameter CMPMASK_WIDTH = 4;
// @{default:nclk}@
input [0:51] addr_in;
input [0:1] addr_enable;
input [0:2] comp_pgsize;
input pgsize_enable;
input [0:2] entry_size;
input [0:CMPMASK_WIDTH-1] entry_cmpmask;
input entry_xbit;
input [0:CMPMASK_WIDTH-1] entry_xbitmask;
input [0:51] entry_epn;
input [0:1] comp_class;
input [0:1] entry_class;
input [0:2] class_enable;
input [0:1] comp_extclass;
input [0:1] entry_extclass;
input [0:1] extclass_enable;
input [0:1] comp_state;
input entry_hv;
input entry_ds;
input [0:1] state_enable;
input [0:3] entry_thdid;
input [0:3] comp_thdid;
input [0:1] thdid_enable;
input [0:7] entry_pid;
input [0:7] comp_pid;
input pid_enable;
input entry_v;
input comp_invalidate;
output match;
// tri_cam_32x143_1r1w1c_matchline
//----------------------------------------------------------------------
// Signals
//----------------------------------------------------------------------
wire [34:51] entry_epn_b;
wire function_50_51;
wire function_48_51;
wire function_46_51;
wire function_44_51;
wire function_40_51;
wire function_36_51;
wire function_34_51;
wire pgsize_eq_16K;
wire pgsize_eq_64K;
wire pgsize_eq_256K;
wire pgsize_eq_1M;
wire pgsize_eq_16M;
wire pgsize_eq_256M;
wire pgsize_eq_1G;
wire pgsize_gte_16K;
wire pgsize_gte_64K;
wire pgsize_gte_256K;
wire pgsize_gte_1M;
wire pgsize_gte_16M;
wire pgsize_gte_256M;
wire pgsize_gte_1G;
wire comp_or_34_35;
wire comp_or_34_39;
wire comp_or_36_39;
wire comp_or_40_43;
wire comp_or_44_45;
wire comp_or_44_47;
wire comp_or_46_47;
wire comp_or_48_49;
wire comp_or_48_51;
wire comp_or_50_51;
wire [0:72] match_line;
wire pgsize_match;
wire addr_match;
wire class_match;
wire extclass_match;
wire state_match;
wire thdid_match;
wire pid_match;
(* analysis_not_referenced="true" *)
wire [0:2] unused;
assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^
{addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]}));
generate
begin
if (NUM_PGSIZES == 8)
begin : numpgsz8
// tie off unused signals
assign comp_or_34_39 = 1'b0;
assign comp_or_44_47 = 1'b0;
assign comp_or_48_51 = 1'b0;
assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51};
assign entry_epn_b[34:51] = (~(entry_epn[34:51]));
if (HAVE_CMPMASK == 0)
begin
assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & entry_size[2]);
assign pgsize_eq_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
assign pgsize_eq_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]);
assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])));
assign pgsize_eq_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]);
assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])));
assign pgsize_eq_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]);
assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & entry_size[2]);
assign pgsize_gte_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_1G;
assign pgsize_gte_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_256M;
assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M;
assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M;
assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_256K;
assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_64K;
assign unused[1] = |{entry_cmpmask, entry_xbitmask};
end
if (HAVE_CMPMASK == 1)
begin
// size entry_cmpmask: 0123456
// 1GB 0000000
// 256MB 1000000
// 16MB 1100000
// 1MB 1110000
// 256KB 1111000
// 64KB 1111100
// 16KB 1111110
// 4KB 1111111
assign pgsize_gte_1G = (~entry_cmpmask[0]);
assign pgsize_gte_256M = (~entry_cmpmask[1]);
assign pgsize_gte_16M = (~entry_cmpmask[2]);
assign pgsize_gte_1M = (~entry_cmpmask[3]);
assign pgsize_gte_256K = (~entry_cmpmask[4]);
assign pgsize_gte_64K = (~entry_cmpmask[5]);
assign pgsize_gte_16K = (~entry_cmpmask[6]);
// size entry_xbitmask: 0123456
// 1GB 1000000
// 256MB 0100000
// 16MB 0010000
// 1MB 0001000
// 256KB 0000100
// 64KB 0000010
// 16KB 0000001
// 4KB 0000000
assign pgsize_eq_1G = entry_xbitmask[0];
assign pgsize_eq_256M = entry_xbitmask[1];
assign pgsize_eq_16M = entry_xbitmask[2];
assign pgsize_eq_1M = entry_xbitmask[3];
assign pgsize_eq_256K = entry_xbitmask[4];
assign pgsize_eq_64K = entry_xbitmask[5];
assign pgsize_eq_16K = entry_xbitmask[6];
assign unused[1] = 1'b0;
end
if (HAVE_XBIT == 0)
begin
assign function_34_51 = 1'b0;
assign function_36_51 = 1'b0;
assign function_40_51 = 1'b0;
assign function_44_51 = 1'b0;
assign function_46_51 = 1'b0;
assign function_48_51 = 1'b0;
assign function_50_51 = 1'b0;
assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51,
function_46_51, function_48_51, function_50_51, entry_xbit,
entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M,
pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K};
end
if (HAVE_XBIT != 0)
begin
assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51]));
assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51]));
assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51]));
assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51]));
assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | (|(entry_epn_b[50:51] & addr_in[50:51]));
assign unused[2] = 1'b0;
end
assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K;
assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K;
assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K;
assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M;
assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M;
assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G;
if (HAVE_XBIT == 0)
begin
assign addr_match = (comp_or_34_35 & // Ignore functions based on page size
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
comp_or_50_51 &
(&(match_line[31:33])) & // Regular compare largest page size
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end
if (HAVE_XBIT != 0)
begin
assign addr_match = (function_50_51 & // Exclusion functions
function_48_51 &
function_46_51 &
function_44_51 &
function_40_51 &
function_36_51 &
function_34_51 &
comp_or_34_35 & // Ignore functions based on page size
comp_or_36_39 &
comp_or_40_43 &
comp_or_44_45 &
comp_or_46_47 &
comp_or_48_49 &
comp_or_50_51 &
(&(match_line[31:33])) & // Regular compare largest page size
(&(match_line[0:30]) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end
end // numpgsz8: NUM_PGSIZES = 8
if (NUM_PGSIZES == 5)
begin : numpgsz5
// tie off unused signals
assign function_50_51 = 1'b0;
assign function_46_51 = 1'b0;
assign function_36_51 = 1'b0;
assign pgsize_eq_16K = 1'b0;
assign pgsize_eq_256K = 1'b0;
assign pgsize_eq_256M = 1'b0;
assign pgsize_gte_16K = 1'b0;
assign pgsize_gte_256K = 1'b0;
assign pgsize_gte_256M = 1'b0;
assign comp_or_34_35 = 1'b0;
assign comp_or_36_39 = 1'b0;
assign comp_or_44_45 = 1'b0;
assign comp_or_46_47 = 1'b0;
assign comp_or_48_49 = 1'b0;
assign comp_or_50_51 = 1'b0;
assign unused[0] = |{function_50_51, function_46_51, function_36_51,
pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M,
pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M,
comp_or_34_35, comp_or_36_39, comp_or_44_45,
comp_or_46_47, comp_or_48_49, comp_or_50_51};
assign entry_epn_b[34:51] = (~(entry_epn[34:51]));
if (HAVE_CMPMASK == 0)
begin
// 110
assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
// 111
assign pgsize_eq_16M = ( entry_size[0] & entry_size[1] & entry_size[2]);
// 101
assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]);
// 011
assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]);
assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
assign pgsize_gte_16M = ( entry_size[0] & entry_size[1] & entry_size[2]) | pgsize_gte_1G;
assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M;
assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M;
assign unused[1] = |{entry_cmpmask, entry_xbitmask};
end
if (HAVE_CMPMASK == 1)
begin
// size entry_cmpmask: 0123
// 1GB 0000
// 16MB 1000
// 1MB 1100
// 64KB 1110
// 4KB 1111
assign pgsize_gte_1G = (~entry_cmpmask[0]);
assign pgsize_gte_16M = (~entry_cmpmask[1]);
assign pgsize_gte_1M = (~entry_cmpmask[2]);
assign pgsize_gte_64K = (~entry_cmpmask[3]);
// size entry_xbitmask: 0123
// 1GB 1000
// 16MB 0100
// 1MB 0010
// 64KB 0001
// 4KB 0000
assign pgsize_eq_1G = entry_xbitmask[0];
assign pgsize_eq_16M = entry_xbitmask[1];
assign pgsize_eq_1M = entry_xbitmask[2];
assign pgsize_eq_64K = entry_xbitmask[3];
assign unused[1] = 1'b0;
end
if (HAVE_XBIT == 0)
begin
assign function_34_51 = 1'b0;
assign function_40_51 = 1'b0;
assign function_44_51 = 1'b0;
assign function_48_51 = 1'b0;
assign unused[2] = |{function_34_51, function_40_51, function_44_51,
function_48_51, entry_xbit, entry_epn_b,
pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K};
end
if (HAVE_XBIT != 0)
begin
// 1G
assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51]));
// 16M
assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
// 1M
assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51]));
// 64K
assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
assign unused[2] = 1'b0;
end
assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K;
assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M;
assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G;
if (HAVE_XBIT == 0)
begin
assign addr_match = (comp_or_34_39 & // Ignore functions based on page size
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51 &
(&(match_line[31:33])) & // Regular compare largest page size
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end
if (HAVE_XBIT != 0)
begin
assign addr_match = (function_48_51 &
function_44_51 &
function_40_51 &
function_34_51 &
comp_or_34_39 & // Ignore functions based on page size
comp_or_40_43 &
comp_or_44_47 &
comp_or_48_51 &
(&(match_line[31:33])) & // Regular compare largest page size
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
(~(addr_enable[0])); // Include address as part of compare,
// should never ignore for regular compare/read.
// Could ignore for compare/invalidate
end
end // numpgsz5: NUM_PGSIZES = 5
assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable));
assign class_match = (match_line[55] | (~(class_enable[0]))) &
(match_line[56] | (~(class_enable[1]))) &
((&(match_line[55:56])) | (~(class_enable[2])) |
((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit
assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) & // iprot bit
(match_line[58] | (~(extclass_enable[1]))); // pid_nz bit
assign state_match = (match_line[59] | (~(state_enable[0]))) &
(match_line[60] | (~(state_enable[1])));
assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) &
(&(match_line[69:72]) | (~(thdid_enable[1])) |
((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit
assign pid_match = (&(match_line[61:68])) |
// entry_pid=0 ignores pid match for compares,
// but not for invalidates.
((~(entry_extclass[1])) & (~comp_invalidate)) | // pid_nz bit
(~(pid_enable));
assign match = addr_match & // Address compare
pgsize_match & // Size compare
class_match & // Class compare
extclass_match & // ExtClass compare
state_match & // State compare
thdid_match & // ThdID compare
pid_match & // PID compare
entry_v; // Valid
end
endgenerate
endmodule |
module tri_oai21(
y,
a0,
a1,
b0
);
parameter WIDTH = 1;
parameter BTR = "OAI21_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
// tri_oai21
genvar i;
wire [0:WIDTH-1] outA;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
or I0(outA[i], a0[i], a1[i]);
nand I2(y[i], outA[i], b0[i]);
end // block: w
end
endgenerate
endmodule |
module tri_st_popcnt_byte(
b0,
y,
vdd,
gnd
);
input [0:7] b0;
output [0:3] y;
inout vdd;
inout gnd;
wire [0:2] s0;
wire [0:3] c1;
wire [0:0] s1;
wire [0:1] c2;
// Level 0
tri_csa32 csa_l0_0(
.vd(vdd),
.gd(gnd),
.a(b0[0]),
.b(b0[1]),
.c(b0[2]),
.sum(s0[0]),
.car(c1[0])
);
tri_csa32 csa_l0_1(
.vd(vdd),
.gd(gnd),
.a(b0[3]),
.b(b0[4]),
.c(b0[5]),
.sum(s0[1]),
.car(c1[1])
);
tri_csa22 csa_l0_2(
.a(b0[6]),
.b(b0[7]),
.sum(s0[2]),
.car(c1[2])
);
tri_csa32 csa_l0_3(
.vd(vdd),
.gd(gnd),
.a(s0[0]),
.b(s0[1]),
.c(s0[2]),
.sum(y[3]),
.car(c1[3])
);
// Level 1
tri_csa32 csa_l1_0(
.vd(vdd),
.gd(gnd),
.a(c1[0]),
.b(c1[1]),
.c(c1[2]),
.sum(s1[0]),
.car(c2[0])
);
tri_csa22 csa_l1_1(
.a(c1[3]),
.b(s1[0]),
.sum(y[2]),
.car(c2[1])
);
// Level 2/3
tri_csa22 csa_l2_0(
.a(c2[0]),
.b(c2[1]),
.sum(y[1]),
.car(y[0])
);
endmodule |
module tri_st_rot_rol64(
word,
right,
amt,
data_i,
res_rot
);
input [0:1] word; // PPC word mode rotate <2 copies>
input [0:2] right; // emulate a shift right with a rotate left <2 copies>
input [0:5] amt; // shift amout [0:63]
input [0:63] data_i; // data to be shifted
output [0:63] res_rot; // mask shows which rotator bits to keep in the result.
wire [0:2] right_b;
wire [0:5] amt_b;
wire [0:1] word_b;
wire [0:31] word_bus;
wire [0:31] word_bus_b;
wire [0:31] data_i0_adj_b;
wire [0:63] data_i_adj;
wire [0:63] data_i1_adj_b;
wire [0:63] rolx16_0;
wire [0:63] rolx16_1;
wire [0:63] rolx16_2;
wire [0:63] rolx16_3;
wire [0:63] rolx04_0;
wire [0:63] rolx04_1;
wire [0:63] rolx04_2;
wire [0:63] rolx04_3;
wire [0:63] rolx01_0;
wire [0:63] rolx01_1;
wire [0:63] rolx01_2;
wire [0:63] rolx01_3;
wire [0:63] rolx01_4;
wire [0:63] shd16;
wire [0:63] shd16_0_b;
wire [0:63] shd16_1_b;
wire [0:63] shd04;
wire [0:63] shd04_0_b;
wire [0:63] shd04_1_b;
wire [0:63] shd01_0_b;
wire [0:63] shd01_1_b;
wire [0:63] shd01_2_b;
wire [0:3] x16_lft_b;
wire [0:3] x16_rgt_b;
wire [0:3] lftx16;
wire [0:3] x04_lft_b;
wire [0:3] x04_rgt_b;
wire [0:3] lftx04;
wire [0:3] x01_lft_b;
wire [0:3] x01_rgt_b;
wire [0:4] lftx01;
wire [0:4] lftx01_inv;
wire [0:4] lftx01_buf0;
wire [0:4] lftx01_buf1;
wire [0:3] lftx04_inv;
wire [0:3] lftx04_buf0;
wire [0:3] lftx04_buf1;
wire [0:3] lftx16_inv;
wire [0:3] lftx16_buf0;
wire [0:3] lftx16_buf1;
wire [0:63] lftx16_0_bus;
wire [0:63] lftx16_1_bus;
wire [0:63] lftx16_2_bus;
wire [0:63] lftx16_3_bus;
wire [0:63] lftx04_0_bus;
wire [0:63] lftx04_1_bus;
wire [0:63] lftx04_2_bus;
wire [0:63] lftx04_3_bus;
wire [0:63] lftx01_0_bus;
wire [0:63] lftx01_1_bus;
wire [0:63] lftx01_2_bus;
wire [0:63] lftx01_3_bus;
wire [0:63] lftx01_4_bus;
// -------------------------------------------------------------
// how the ppc emulates a rot32 using rot64 hardware.
// this makes the wrapping corect for the low order 32 bits.
// upper 32 result bits a garbage
//--------------------------------------------------------------
assign word_b[0:1] = (~word[0:1]);
assign word_bus_b[0:15] = {16{word_b[0]}};
assign word_bus_b[16:31] = {16{word_b[1]}};
assign word_bus[0:15] = {16{word[0]}};
assign word_bus[16:31] = {16{word[1]}};
assign data_i0_adj_b[0:31] = (~(data_i[0:31] & word_bus_b[0:31]));
assign data_i1_adj_b[0:31] = (~(data_i[32:63] & word_bus[0:31]));
assign data_i_adj[0:31] = (~(data_i0_adj_b[0:31] & data_i1_adj_b[0:31]));
assign data_i1_adj_b[32:63] = (~(data_i[32:63]));
assign data_i_adj[32:63] = (~(data_i1_adj_b[32:63]));
//---------------------------------------------------------------
// decoder without the adder
//---------------------------------------------------------------
//rotate right by [n] == rotate_left by width -[n] == !n + 1
assign right_b[0:2] = (~right[0:2]);
assign amt_b[0:5] = (~amt[0:5]);
assign x16_lft_b[0] = (~(right_b[0] & amt_b[0] & amt_b[1]));
assign x16_lft_b[1] = (~(right_b[0] & amt_b[0] & amt[1]));
assign x16_lft_b[2] = (~(right_b[0] & amt[0] & amt_b[1]));
assign x16_lft_b[3] = (~(right_b[0] & amt[0] & amt[1]));
assign x16_rgt_b[0] = (~(right[0] & amt_b[0] & amt_b[1]));
assign x16_rgt_b[1] = (~(right[0] & amt_b[0] & amt[1]));
assign x16_rgt_b[2] = (~(right[0] & amt[0] & amt_b[1]));
assign x16_rgt_b[3] = (~(right[0] & amt[0] & amt[1]));
assign lftx16[0] = (~(x16_lft_b[0] & x16_rgt_b[3]));
assign lftx16[1] = (~(x16_lft_b[1] & x16_rgt_b[2]));
assign lftx16[2] = (~(x16_lft_b[2] & x16_rgt_b[1]));
assign lftx16[3] = (~(x16_lft_b[3] & x16_rgt_b[0]));
assign x04_lft_b[0] = (~(right_b[1] & amt_b[2] & amt_b[3]));
assign x04_lft_b[1] = (~(right_b[1] & amt_b[2] & amt[3]));
assign x04_lft_b[2] = (~(right_b[1] & amt[2] & amt_b[3]));
assign x04_lft_b[3] = (~(right_b[1] & amt[2] & amt[3]));
assign x04_rgt_b[0] = (~(right[1] & amt_b[2] & amt_b[3]));
assign x04_rgt_b[1] = (~(right[1] & amt_b[2] & amt[3]));
assign x04_rgt_b[2] = (~(right[1] & amt[2] & amt_b[3]));
assign x04_rgt_b[3] = (~(right[1] & amt[2] & amt[3]));
assign lftx04[0] = (~(x04_lft_b[0] & x04_rgt_b[3]));
assign lftx04[1] = (~(x04_lft_b[1] & x04_rgt_b[2]));
assign lftx04[2] = (~(x04_lft_b[2] & x04_rgt_b[1]));
assign lftx04[3] = (~(x04_lft_b[3] & x04_rgt_b[0]));
assign x01_lft_b[0] = (~(right_b[2] & amt_b[4] & amt_b[5]));
assign x01_lft_b[1] = (~(right_b[2] & amt_b[4] & amt[5]));
assign x01_lft_b[2] = (~(right_b[2] & amt[4] & amt_b[5]));
assign x01_lft_b[3] = (~(right_b[2] & amt[4] & amt[5]));
assign x01_rgt_b[0] = (~(right[2] & amt_b[4] & amt_b[5]));
assign x01_rgt_b[1] = (~(right[2] & amt_b[4] & amt[5]));
assign x01_rgt_b[2] = (~(right[2] & amt[4] & amt_b[5]));
assign x01_rgt_b[3] = (~(right[2] & amt[4] & amt[5]));
assign lftx01[0] = (~(x01_lft_b[0])); // the shift is like the +1
assign lftx01[1] = (~(x01_lft_b[1] & x01_rgt_b[3]));
assign lftx01[2] = (~(x01_lft_b[2] & x01_rgt_b[2]));
assign lftx01[3] = (~(x01_lft_b[3] & x01_rgt_b[1]));
assign lftx01[4] = (~(x01_rgt_b[0]));
assign lftx16_inv[0:3] = (~(lftx16[0:3]));
assign lftx16_buf0[0:3] = (~(lftx16_inv[0:3]));
assign lftx16_buf1[0:3] = (~(lftx16_inv[0:3]));
assign lftx04_inv[0:3] = (~(lftx04[0:3]));
assign lftx04_buf0[0:3] = (~(lftx04_inv[0:3]));
assign lftx04_buf1[0:3] = (~(lftx04_inv[0:3]));
assign lftx01_inv[0:4] = (~(lftx01[0:4]));
assign lftx01_buf0[0:4] = (~(lftx01_inv[0:4]));
assign lftx01_buf1[0:4] = (~(lftx01_inv[0:4]));
assign lftx16_0_bus[0:31] = {32{lftx16_buf0[0]}};
assign lftx16_0_bus[32:63] = {32{lftx16_buf1[0]}};
assign lftx16_1_bus[0:31] = {32{lftx16_buf0[1]}};
assign lftx16_1_bus[32:63] = {32{lftx16_buf1[1]}};
assign lftx16_2_bus[0:31] = {32{lftx16_buf0[2]}};
assign lftx16_2_bus[32:63] = {32{lftx16_buf1[2]}};
assign lftx16_3_bus[0:31] = {32{lftx16_buf0[3]}};
assign lftx16_3_bus[32:63] = {32{lftx16_buf1[3]}};
assign lftx04_0_bus[0:31] = {32{lftx04_buf0[0]}};
assign lftx04_0_bus[32:63] = {32{lftx04_buf1[0]}};
assign lftx04_1_bus[0:31] = {32{lftx04_buf0[1]}};
assign lftx04_1_bus[32:63] = {32{lftx04_buf1[1]}};
assign lftx04_2_bus[0:31] = {32{lftx04_buf0[2]}};
assign lftx04_2_bus[32:63] = {32{lftx04_buf1[2]}};
assign lftx04_3_bus[0:31] = {32{lftx04_buf0[3]}};
assign lftx04_3_bus[32:63] = {32{lftx04_buf1[3]}};
assign lftx01_0_bus[0:31] = {32{lftx01_buf0[0]}};
assign lftx01_0_bus[32:63] = {32{lftx01_buf1[0]}};
assign lftx01_1_bus[0:31] = {32{lftx01_buf0[1]}};
assign lftx01_1_bus[32:63] = {32{lftx01_buf1[1]}};
assign lftx01_2_bus[0:31] = {32{lftx01_buf0[2]}};
assign lftx01_2_bus[32:63] = {32{lftx01_buf1[2]}};
assign lftx01_3_bus[0:31] = {32{lftx01_buf0[3]}};
assign lftx01_3_bus[32:63] = {32{lftx01_buf1[3]}};
assign lftx01_4_bus[0:31] = {32{lftx01_buf0[4]}};
assign lftx01_4_bus[32:63] = {32{lftx01_buf1[4]}};
//---------------------------------------------------------------
// the shifter
//---------------------------------------------------------------
assign rolx16_0[0:63] = data_i_adj[0:63];
assign rolx16_1[0:63] = {data_i_adj[16:63], data_i_adj[0:15]};
assign rolx16_2[0:63] = {data_i_adj[32:63], data_i_adj[0:31]};
assign rolx16_3[0:63] = {data_i_adj[48:63], data_i_adj[0:47]};
assign shd16_0_b[0:63] = (~((lftx16_0_bus[0:63] & rolx16_0[0:63]) | (lftx16_1_bus[0:63] & rolx16_1[0:63])));
assign shd16_1_b[0:63] = (~((lftx16_2_bus[0:63] & rolx16_2[0:63]) | (lftx16_3_bus[0:63] & rolx16_3[0:63])));
assign shd16[0:63] = (~(shd16_0_b[0:63] & shd16_1_b[0:63]));
assign rolx04_0[0:63] = shd16[0:63];
assign rolx04_1[0:63] = {shd16[4:63], shd16[0:3]};
assign rolx04_2[0:63] = {shd16[8:63], shd16[0:7]};
assign rolx04_3[0:63] = {shd16[12:63], shd16[0:11]};
assign shd04_0_b[0:63] = (~((lftx04_0_bus[0:63] & rolx04_0[0:63]) | (lftx04_1_bus[0:63] & rolx04_1[0:63])));
assign shd04_1_b[0:63] = (~((lftx04_2_bus[0:63] & rolx04_2[0:63]) | (lftx04_3_bus[0:63] & rolx04_3[0:63])));
assign shd04[0:63] = (~(shd04_0_b[0:63] & shd04_1_b[0:63]));
assign rolx01_0[0:63] = shd04[0:63];
assign rolx01_1[0:63] = {shd04[1:63], shd04[0]};
assign rolx01_2[0:63] = {shd04[2:63], shd04[0:1]};
assign rolx01_3[0:63] = {shd04[3:63], shd04[0:2]};
assign rolx01_4[0:63] = {shd04[4:63], shd04[0:3]};
assign shd01_0_b[0:63] = (~((lftx01_0_bus[0:63] & rolx01_0[0:63]) | (lftx01_1_bus[0:63] & rolx01_1[0:63])));
assign shd01_1_b[0:63] = (~((lftx01_2_bus[0:63] & rolx01_2[0:63]) | (lftx01_3_bus[0:63] & rolx01_3[0:63])));
assign shd01_2_b[0:63] = (~(lftx01_4_bus[0:63] & rolx01_4[0:63]));
assign res_rot[0:63] = (~(shd01_0_b[0:63] & shd01_1_b[0:63] & shd01_2_b[0:63]));
endmodule |
module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter IBUF = 1'b0; //inverted latch IOs, if set to true.
parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock
input d_mode; // 1: disable pulse mode, 0: pulse mode
input sg; // 0: functional, 1: scan
input delay_lclkr; // 0: functional
input mpw1_b; // pulse width control bit
input mpw2_b; // pulse width control bit
input [OFFSET:OFFSET+WIDTH-1] scin; // scan in
input [OFFSET:OFFSET+WIDTH-1] din; // data in
output [OFFSET:OFFSET+WIDTH-1] scout;
output [OFFSET:OFFSET+WIDTH-1] dout;
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
// tri_rlmreg_p
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire [0:WIDTH] unused;
if (NEEDS_SRESET == 1)
begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
if (IBUF == 1'b1)
begin : cib
assign int_din = (vsreset_b & (~din)) | (vsreset & init_v);
end
if (IBUF == 1'b0)
begin : cnib
assign int_din = (vsreset_b & din) | (vsreset & init_v);
end
assign vact = {WIDTH{act | force_t}};
assign vact_b = {WIDTH{~(act | force_t)}};
assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}};
always @(posedge nclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
if (IBUF == 1'b1)
begin : cob
assign dout = (~int_dout);
end
if (IBUF == 1'b0)
begin : cnob
assign dout = int_dout;
end
assign scout = ZEROS;
assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk);
assign unused[1:WIDTH] = scin;
end
endgenerate
endmodule |
module tri_nand4(
y,
a,
b,
c,
d
);
parameter WIDTH = 1;
parameter BTR = "NAND4_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
input [0:WIDTH-1] d;
// tri_nand3
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
nand I0(y[i], a[i], b[i], c[i], d[i]);
end // block: w
end
endgenerate
endmodule |
module tri_parity_recovery(
perr_si,
perr_so,
delay_lclkr,
mpw1_b,
mpw2_b,
nclk,
force_t,
thold_0_b,
sg_0,
gnd,
vdd,
ex3_hangcounter_trigger,
ex3_a_parity_check,
ex3_b_parity_check,
ex3_c_parity_check,
ex3_s_parity_check,
rf0_instr_fra,
rf0_instr_frb,
rf0_instr_frc,
rf0_tid,
rf0_dcd_fra,
rf0_dcd_frb,
rf0_dcd_frc,
rf0_dcd_tid,
ex1_instr_fra,
ex1_instr_frb,
ex1_instr_frc,
ex1_instr_frs,
ex3_fra_v,
ex3_frb_v,
ex3_frc_v,
ex3_str_v,
ex3_frs_byp,
ex3_fdivsqrt_start,
ex3_instr_v,
msr_fp_act,
cp_flush_1d,
ex7_is_fixperr,
xx_ex4_regfile_err_det,
xx_ex5_regfile_err_det,
xx_ex6_regfile_err_det,
xx_ex7_regfile_err_det,
xx_ex8_regfile_err_det,
xx_ex1_perr_sm_instr_v,
xx_ex2_perr_sm_instr_v,
xx_ex3_perr_sm_instr_v,
xx_ex4_perr_sm_instr_v,
xx_ex5_perr_sm_instr_v,
xx_ex6_perr_sm_instr_v,
xx_ex7_perr_sm_instr_v,
xx_ex8_perr_sm_instr_v,
xx_perr_sm_running,
xx_ex2_perr_force_c,
xx_ex2_perr_fsel_ovrd,
xx_perr_tid_l2,
xx_perr_sm_l2,
xx_perr_addr_l2,
ex3_sto_parity_err,
xx_rv_hold_all,
xx_ex0_regfile_ue,
xx_ex0_regfile_ce,
xx_pc_err_regfile_parity,
xx_pc_err_regfile_ue
);
parameter THREADS = 2;
input perr_si;
output perr_so;
input [0:9] delay_lclkr;
input [0:9] mpw1_b;
input [0:1] mpw2_b;
input [0:`NCLK_WIDTH-1] nclk;
input force_t;
input thold_0_b;
input sg_0;
inout gnd;
inout vdd;
input ex3_hangcounter_trigger;
input ex3_a_parity_check;
input ex3_b_parity_check;
input ex3_c_parity_check;
input ex3_s_parity_check;
input [0:5] rf0_instr_fra;
input [0:5] rf0_instr_frb;
input [0:5] rf0_instr_frc;
input [0:1] rf0_tid;
output [0:5] rf0_dcd_fra;
output [0:5] rf0_dcd_frb;
output [0:5] rf0_dcd_frc;
output [0:1] rf0_dcd_tid;
input [0:5] ex1_instr_fra;
input [0:5] ex1_instr_frb;
input [0:5] ex1_instr_frc;
input [0:5] ex1_instr_frs;
input ex3_fra_v;
input ex3_frb_v;
input ex3_frc_v;
input ex3_str_v;
input ex3_frs_byp;
input [0:1] ex3_fdivsqrt_start;
input [0:1] ex3_instr_v;
input msr_fp_act;
input [0:1] cp_flush_1d;
output ex7_is_fixperr;
output [0:1] xx_ex4_regfile_err_det;
output [0:1] xx_ex5_regfile_err_det;
output [0:1] xx_ex6_regfile_err_det;
output [0:1] xx_ex7_regfile_err_det;
output [0:1] xx_ex8_regfile_err_det;
output xx_ex1_perr_sm_instr_v;
output xx_ex2_perr_sm_instr_v;
output xx_ex3_perr_sm_instr_v;
output xx_ex4_perr_sm_instr_v;
output xx_ex5_perr_sm_instr_v;
output xx_ex6_perr_sm_instr_v;
output xx_ex7_perr_sm_instr_v;
output xx_ex8_perr_sm_instr_v;
output xx_perr_sm_running;
output xx_ex2_perr_force_c;
output xx_ex2_perr_fsel_ovrd;
output [0:1] xx_perr_tid_l2;
output [0:2] xx_perr_sm_l2;
output [0:5] xx_perr_addr_l2;
output ex3_sto_parity_err;
output xx_rv_hold_all;
output xx_ex0_regfile_ue;
output xx_ex0_regfile_ce;
output [0:`THREADS-1] xx_pc_err_regfile_parity;
output [0:`THREADS-1] xx_pc_err_regfile_ue;
// parity err ---------
(* analysis_not_referenced="TRUE" *) // unused
wire [0:2] spare_unused;
wire perr_sm_running;
wire [0:23] ex3_perr_si;
wire [0:23] ex3_perr_so;
wire [0:1] ex3_fpr_perr;
wire [0:1] ex3_fpr_reg_perr;
wire ex3_regfile_err_det_any;
wire ex3_capture_addr;
wire [0:1] ex4_regfile_err_det_din;
wire [0:1] ex5_regfile_err_det_din;
wire [0:1] ex6_regfile_err_det_din;
wire [0:1] ex7_regfile_err_det_din;
wire regfile_seq_beg;
wire regfile_seq_end;
wire ex4_regfile_err_det_any;
wire ex5_regfile_err_det_any;
wire ex6_regfile_err_det_any;
wire [0:1] ex4_sto_err_det;
wire [0:1] ex4_regfile_err_det;
wire [0:1] ex5_regfile_err_det;
wire [0:1] ex6_regfile_err_det;
wire [0:1] ex7_regfile_err_det;
wire [0:1] ex8_regfile_err_det;
wire ex3_f0a_perr;
wire ex3_f0c_perr;
wire ex3_f1b_perr;
wire ex3_f1s_perr;
wire [0:1] ex3_sto_perr;
wire [0:0] holdall_si;
wire [0:0] holdall_so;
wire rv_hold_all_din;
wire rv_hold_all_q;
wire [0:1] err_regfile_parity;
wire [0:1] err_regfile_ue;
wire [0:1] ex3_abc_perr;
wire [0:1] ex3_abc_perr_x;
wire [0:1] ex3_abc_perr_y;
wire ex1_perr_move_f0_to_f1;
wire ex1_perr_move_f1_to_f0;
wire ex0_regfile_ce;
wire ex0_regfile_ue;
wire [0:23] ex2_perr_si;
wire [0:23] ex2_perr_so;
wire [0:5] ex3_instr_fra;
wire [0:5] ex3_instr_frb;
wire [0:5] ex3_instr_frc;
wire [0:5] ex3_instr_frs;
wire [0:5] ex2_instr_fra;
wire [0:5] ex2_instr_frb;
wire [0:5] ex2_instr_frc;
wire [0:5] ex2_instr_frs;
wire new_perr_sm_instr_v;
wire rf0_perr_sm_instr_v;
wire rf0_perr_sm_instr_v_b;
wire ex0_perr_sm_instr_v;
wire ex1_perr_sm_instr_v;
wire ex2_perr_sm_instr_v;
wire ex3_perr_sm_instr_v;
wire ex4_perr_sm_instr_v;
wire ex5_perr_sm_instr_v;
wire ex6_perr_sm_instr_v;
wire ex7_perr_sm_instr_v;
wire ex8_perr_sm_instr_v;
wire rf0_perr_move_f0_to_f1;
wire rf0_perr_move_f1_to_f0;
wire rf0_perr_fixed_itself;
wire perr_move_f0_to_f1_l2;
wire perr_move_f1_to_f0_l2;
wire rf0_perr_force_c;
wire ex0_perr_force_c;
wire ex1_perr_force_c;
wire ex2_perr_force_c;
wire [0:5] perr_addr_din;
wire [0:5] perr_addr_l2;
wire [0:30] perr_ctl_si;
wire [0:30] perr_ctl_so;
wire perr_move_f0_to_f1;
wire perr_move_f1_to_f0;
wire [0:2] perr_sm_din;
wire [0:2] perr_sm_l2;
wire [0:2] perr_sm_ns;
wire [0:2] perr_sm_si;
wire [0:2] perr_sm_so;
wire [0:1] perr_tid_din;
wire [0:1] perr_tid_l2;
wire rf0_regfile_ce;
wire rf0_regfile_ue;
wire [0:3] ex4_ctl_perr_si;
wire [0:3] ex4_ctl_perr_so;
wire [0:8] exx_regfile_err_det_si;
wire [0:8] exx_regfile_err_det_so;
wire [0:5] rf0_frb_iu_x_b;
wire [0:5] rf0_frb_perr_x_b;
wire [0:5] rf0_frc_iu_x_b;
wire [0:5] rf0_frc_perr_x_b;
wire ex3_a_perr_check;
wire ex3_b_perr_check;
wire ex3_c_perr_check;
wire ex3_s_perr_check;
//------------- end parity
wire tilo;
wire tihi;
wire tidn;
wire tiup;
//-------------------------------------------------------------------------------------------------
assign tilo = 1'b0;
assign tihi = 1'b1;
assign tidn = 1'b0;
assign tiup = 1'b1;
//----------------------------------------------------------------------
// Parity State Machine / parity section
assign xx_ex4_regfile_err_det = ex4_regfile_err_det;
assign xx_ex5_regfile_err_det = ex5_regfile_err_det;
assign xx_ex6_regfile_err_det = ex6_regfile_err_det;
assign xx_ex7_regfile_err_det = ex7_regfile_err_det;
assign xx_ex8_regfile_err_det = ex8_regfile_err_det;
assign xx_ex1_perr_sm_instr_v = ex1_perr_sm_instr_v;
assign xx_ex2_perr_sm_instr_v = ex2_perr_sm_instr_v;
assign xx_ex3_perr_sm_instr_v = ex3_perr_sm_instr_v;
assign xx_ex4_perr_sm_instr_v = ex4_perr_sm_instr_v;
assign xx_ex5_perr_sm_instr_v = ex5_perr_sm_instr_v;
assign xx_ex6_perr_sm_instr_v = ex6_perr_sm_instr_v;
assign xx_ex7_perr_sm_instr_v = ex7_perr_sm_instr_v;
assign xx_ex8_perr_sm_instr_v = ex8_perr_sm_instr_v;
assign xx_perr_tid_l2 = perr_tid_l2;
assign xx_perr_sm_l2 = perr_sm_l2;
assign ex4_regfile_err_det_din[0:1] = ex4_regfile_err_det[0:1] & (~cp_flush_1d[0:1]);
assign ex5_regfile_err_det_din[0:1] = ex5_regfile_err_det[0:1] & (~cp_flush_1d[0:1]);
assign ex6_regfile_err_det_din[0:1] = ex6_regfile_err_det[0:1] & (~cp_flush_1d[0:1]);
assign ex7_regfile_err_det_din[0:1] = ex7_regfile_err_det[0:1] & (~cp_flush_1d[0:1]);
assign xx_ex0_regfile_ue = ex0_regfile_ue;
assign xx_ex0_regfile_ce = ex0_regfile_ce;
assign xx_perr_addr_l2 = perr_addr_l2;
tri_rlmreg_p #(.INIT(0), .WIDTH(9)) exx_regfile_err_det_lat(
.nclk(nclk),
.act(tihi),
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[9]),
.mpw1_b(mpw1_b[9]),
.mpw2_b(mpw2_b[1]),
.thold_b(thold_0_b),
.sg(sg_0),
.vd(vdd),
.gd(gnd),
.scin(exx_regfile_err_det_si[0:8]),
.scout(exx_regfile_err_det_so[0:8]),
//-------------------------------------------
.din({ ex4_regfile_err_det_din[0:1],
ex5_regfile_err_det_din[0:1],
ex6_regfile_err_det_din[0:1],
ex7_regfile_err_det_din[0:1],
ex6_perr_sm_instr_v
}),
//-------------------------------------------
.dout({ ex5_regfile_err_det[0:1],
ex6_regfile_err_det[0:1],
ex7_regfile_err_det[0:1],
ex8_regfile_err_det[0:1],
ex7_is_fixperr
})
);
//-------------------------------------------
tri_rlmreg_p #(.INIT(0), .WIDTH(4)) ex4_ctl_perr(
.nclk(nclk),
.act(tihi),
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[4]),
.mpw1_b(mpw1_b[4]),
.mpw2_b(mpw2_b[0]),
.thold_b(thold_0_b),
.sg(sg_0),
.vd(vdd),
.gd(gnd),
.scin(ex4_ctl_perr_si[0:3]),
.scout(ex4_ctl_perr_so[0:3]),
//-------------------------------------------
.din({
ex3_fpr_reg_perr[0:1],
ex3_sto_perr[0:1]
}),
//-------------------------------------------
.dout( {
ex4_regfile_err_det[0:1],
ex4_sto_err_det[0:1]
})
);
//-------------------------------------------
tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex2_perr(
.nclk(nclk),
.act(tiup),
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[2]),
.mpw1_b(mpw1_b[2]),
.mpw2_b(mpw2_b[0]),
.thold_b(thold_0_b),
.sg(sg_0),
.vd(vdd),
.gd(gnd),
.scin(ex2_perr_si[0:23]),
.scout(ex2_perr_so[0:23]),
.din({ex1_instr_frs[0:5],
ex1_instr_fra[0:5],
ex1_instr_frb[0:5],
ex1_instr_frc[0:5]
}),
//-------------------------------------------
.dout({ex2_instr_frs[0:5],
ex2_instr_fra[0:5],
ex2_instr_frb[0:5],
ex2_instr_frc[0:5]
})
);
//-------------------------------------------
tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_perr(
.nclk(nclk),
.act(tiup),
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[3]),
.mpw1_b(mpw1_b[3]),
.mpw2_b(mpw2_b[0]),
.thold_b(thold_0_b),
.sg(sg_0),
.vd(vdd),
.gd(gnd),
.scin(ex3_perr_si[0:23]),
.scout(ex3_perr_so[0:23]),
.din({ex2_instr_frs[0:5],
ex2_instr_fra[0:5],
ex2_instr_frb[0:5],
ex2_instr_frc[0:5]
}),
//-------------------------------------------
.dout( {ex3_instr_frs[0:5],
ex3_instr_fra[0:5],
ex3_instr_frb[0:5],
ex3_instr_frc[0:5]
})
);
//-------------------------------------------
// Parity Checking
assign ex3_a_perr_check = ex3_a_parity_check;
assign ex3_b_perr_check = ex3_b_parity_check;
assign ex3_c_perr_check = ex3_c_parity_check;
assign ex3_s_perr_check = ex3_s_parity_check;
assign ex3_sto_perr[0:1] = {2{(ex3_s_perr_check & ex3_str_v & ~ex3_frs_byp)}} & ex3_instr_v[0:1];
assign ex3_sto_parity_err = |(ex3_sto_perr);
assign ex3_abc_perr_x = {2{((ex3_a_perr_check & ex3_fra_v) |
(ex3_b_perr_check & ex3_frb_v) |
(ex3_c_perr_check & ex3_frc_v)) }};
assign ex3_abc_perr_y = (ex3_instr_v[0:1] | ex3_fdivsqrt_start[0:1]);
assign ex3_abc_perr[0:1] = ex3_abc_perr_x[0:1] & ex3_abc_perr_y[0:1];
assign ex3_fpr_perr[0:1] = (ex3_sto_perr[0:1] | ex3_abc_perr[0:1]) & (~cp_flush_1d[0:1]) & {2{msr_fp_act}};
assign ex3_regfile_err_det_any = |(ex3_fpr_perr);
assign ex3_fpr_reg_perr[0:1] = ( ex3_abc_perr[0:1]) & (~cp_flush_1d[0:1]) & {2{msr_fp_act}};
assign ex3_f0a_perr = ex3_a_perr_check & ex3_fra_v;
assign ex3_f0c_perr = ex3_c_perr_check & (ex3_frc_v | (perr_sm_l2[1] & ex3_perr_sm_instr_v));
assign ex3_f1b_perr = ex3_b_perr_check & (ex3_frb_v | (perr_sm_l2[1] & ex3_perr_sm_instr_v));
assign ex3_f1s_perr = ex3_s_perr_check & ex3_str_v;
assign ex4_regfile_err_det_any = |(ex4_regfile_err_det[0:1]) | |(ex4_sto_err_det[0:1]);
tri_rlmreg_p #(.INIT(4), .WIDTH(3)) perr_sm(
.nclk(nclk),
.act(tihi),
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[9]),
.mpw1_b(mpw1_b[9]),
.mpw2_b(mpw2_b[1]),
.thold_b(thold_0_b),
.sg(sg_0),
.vd(vdd),
.gd(gnd),
.scin(perr_sm_si[0:2]),
.scout(perr_sm_so[0:2]),
.din(perr_sm_din[0:2]),
//-------------------------------------------
.dout( perr_sm_l2[0:2])
);
//-------------------------------------------
tri_rlmreg_p #(.INIT(0), .WIDTH(31)) perr_ctl(
.nclk(nclk),
.act(tiup),
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[9]),
.mpw1_b(mpw1_b[9]),
.mpw2_b(mpw2_b[1]),
.thold_b(thold_0_b),
.sg(sg_0),
.vd(vdd),
.gd(gnd),
.scin(perr_ctl_si[0:30]),
.scout(perr_ctl_so[0:30]),
.din({ perr_addr_din[0:5],
perr_tid_din[0:1],
spare_unused[0:1],
perr_move_f0_to_f1,
perr_move_f1_to_f0,
rf0_perr_force_c,
ex0_perr_force_c,
ex1_perr_force_c,
new_perr_sm_instr_v,
rf0_perr_sm_instr_v,
ex0_perr_sm_instr_v,
ex1_perr_sm_instr_v,
ex2_perr_sm_instr_v,
ex3_perr_sm_instr_v,
ex4_perr_sm_instr_v,
ex5_perr_sm_instr_v,
ex6_perr_sm_instr_v,
ex7_perr_sm_instr_v,
ex4_regfile_err_det_any,
ex5_regfile_err_det_any, // ex3_regfile_err_det, //xu_fu_regfile_seq_beg, // need extra cycles for holdall to take effect
ex6_regfile_err_det_any,
regfile_seq_end,
rf0_regfile_ue,
rf0_regfile_ce}),
//-------------------------------------------
.dout({ perr_addr_l2[0:5],
perr_tid_l2[0:1],
spare_unused[0:1],
perr_move_f0_to_f1_l2,
perr_move_f1_to_f0_l2,
ex0_perr_force_c,
ex1_perr_force_c,
ex2_perr_force_c,
rf0_perr_sm_instr_v,
ex0_perr_sm_instr_v,
ex1_perr_sm_instr_v,
ex2_perr_sm_instr_v,
ex3_perr_sm_instr_v,
ex4_perr_sm_instr_v,
ex5_perr_sm_instr_v,
ex6_perr_sm_instr_v,
ex7_perr_sm_instr_v,
ex8_perr_sm_instr_v,
ex5_regfile_err_det_any,
ex6_regfile_err_det_any,
regfile_seq_beg,
spare_unused[2],
ex0_regfile_ue,
ex0_regfile_ce})
);
//-------------------------------------------
assign rf0_perr_sm_instr_v_b = (~rf0_perr_sm_instr_v);
// State 0 = 100 = Default, no parity error
// State 1 = 010 = Parity error detected. Flush System, and read out both entries
// State 2 = 001 = Move good to bad, or UE
assign perr_sm_running = (~perr_sm_l2[0]);
assign xx_perr_sm_running = (~perr_sm_l2[0]);
// Goto State0 at the end of the sequence. That's either after a UE, or writeback is done
assign perr_sm_ns[0] = (perr_sm_l2[2] & rf0_regfile_ue) | (perr_sm_l2[2] & ex7_perr_sm_instr_v);
assign regfile_seq_end = perr_sm_ns[0];
// Goto State1 when a parity error is detected.
assign perr_sm_ns[1] = perr_sm_l2[0] & regfile_seq_beg;
// Goto State2 when both sets of data have been read out
assign perr_sm_ns[2] = perr_sm_l2[1] & ex7_perr_sm_instr_v;
// set move decision. Both means Uncorrectable Error
assign perr_move_f0_to_f1 = (ex3_f1b_perr & ( (perr_sm_l2[1] & ex3_perr_sm_instr_v))) |
(perr_move_f0_to_f1_l2 & (~(perr_sm_l2[1] & ex3_perr_sm_instr_v)));
assign perr_move_f1_to_f0 = (ex3_f0c_perr & ( (perr_sm_l2[1] & ex3_perr_sm_instr_v))) |
(perr_move_f1_to_f0_l2 & (~(perr_sm_l2[1] & ex3_perr_sm_instr_v)));
assign rf0_perr_move_f0_to_f1 = perr_move_f0_to_f1_l2 & (perr_sm_l2[2] & rf0_perr_sm_instr_v);
assign rf0_perr_move_f1_to_f0 = perr_move_f1_to_f0_l2 & (perr_sm_l2[2] & rf0_perr_sm_instr_v);
assign rf0_perr_fixed_itself = (~(perr_move_f1_to_f0_l2 | perr_move_f0_to_f1_l2)) & (perr_sm_l2[2] & rf0_perr_sm_instr_v); // this is for the case where initially a parity error was detected, but when re-read out of the regfile both copies are correct. We still want to report this.
assign rf0_perr_force_c = rf0_perr_move_f0_to_f1 & (~rf0_perr_move_f1_to_f0);
assign xx_ex2_perr_force_c = ex2_perr_force_c;
assign xx_ex2_perr_fsel_ovrd = ex2_perr_sm_instr_v & perr_sm_l2[2]; //cyc // perr_insert
assign perr_sm_din[0:2] = (3'b100 & {3{perr_sm_ns[0]}}) |
(3'b010 & {3{perr_sm_ns[1]}}) |
(3'b001 & {3{perr_sm_ns[2]}}) |
(perr_sm_l2 & {3{(~(|(perr_sm_ns[0:2])))}});
// Send a dummy instruction down the pipe for reading or writing the regfiles
assign new_perr_sm_instr_v = perr_sm_ns[1] | perr_sm_ns[2];
// Save the offending address and tid on any parity error and hold.
assign ex3_capture_addr = ex3_regfile_err_det_any & perr_sm_l2[0] &
(~ex4_regfile_err_det_any) &
(~ex5_regfile_err_det_any) & // need to cover the cycles while waiting for rv to hold_all
(~ex6_regfile_err_det_any) & // safety cycle
(~regfile_seq_beg);
assign perr_addr_din[0:5] = ((ex3_f0a_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_fra[0:5] :
((ex3_f1b_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_frb[0:5] :
((ex3_f0c_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_frc[0:5] :
((ex3_f1s_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_frs[0:5] :
perr_addr_l2[0:5];
assign perr_tid_din[0:1] = (ex3_fpr_perr[0:1] & {2{ (ex3_capture_addr)}}) |
(perr_tid_l2[0:1] & {2{~(ex3_capture_addr)}});
//Mux into the FPR address
// perr_insert
assign rf0_frc_perr_x_b[0:5] = (~(perr_addr_l2[0:5] & {6{rf0_perr_sm_instr_v}}));
assign rf0_frc_iu_x_b[0:5] = (~(rf0_instr_frc[0:5] & {6{rf0_perr_sm_instr_v_b}}));
assign rf0_dcd_frc[0:5] = (~(rf0_frc_perr_x_b[0:5] & rf0_frc_iu_x_b[0:5]));
assign rf0_frb_perr_x_b[0:5] = (~(perr_addr_l2[0:5] & {6{rf0_perr_sm_instr_v}}));
assign rf0_frb_iu_x_b[0:5] = (~(rf0_instr_frb[0:5] & {6{rf0_perr_sm_instr_v_b}}));
assign rf0_dcd_frb[0:5] = (~(rf0_frb_perr_x_b[0:5] & rf0_frb_iu_x_b[0:5]));
assign rf0_dcd_fra[0:5] = rf0_instr_fra[0:5];
assign rf0_dcd_tid[0:1] = (rf0_tid[0:1] & {2{rf0_perr_sm_instr_v_b}}) |
(perr_tid_l2[0:1] & {2{rf0_perr_sm_instr_v}});
// Determine if we have a ue or ce to report to PC
// state prefixes are for the recirc, not relevant to PC
assign rf0_regfile_ce = (rf0_perr_move_f0_to_f1 | rf0_perr_move_f1_to_f0 | rf0_perr_fixed_itself) & (~(rf0_perr_move_f0_to_f1 & rf0_perr_move_f1_to_f0));
assign rf0_regfile_ue = rf0_perr_move_f0_to_f1 & rf0_perr_move_f1_to_f0;
assign err_regfile_parity[0:1] = perr_tid_l2[0:1] & {2{ex0_regfile_ce}};
assign err_regfile_ue[0:1] = perr_tid_l2[0:1] & {2{ex0_regfile_ue}};
generate
if (THREADS == 1)
begin : dcd_err_rpt_thr1
tri_direct_err_rpt #(.WIDTH(2)) fu_err_rpt(
.vd(vdd),
.gd(gnd),
.err_in({ err_regfile_parity[0],
err_regfile_ue[0]}),
.err_out({xx_pc_err_regfile_parity[0],
xx_pc_err_regfile_ue[0] })
);
end
endgenerate
generate
if (THREADS == 2)
begin : dcd_err_rpt_thr2
tri_direct_err_rpt #(.WIDTH(4)) fu_err_rpt(
.vd(vdd),
.gd(gnd),
.err_in({ err_regfile_parity[0],
err_regfile_parity[1],
err_regfile_ue[0],
err_regfile_ue[1]
}),
.err_out({xx_pc_err_regfile_parity[0],
xx_pc_err_regfile_parity[1],
xx_pc_err_regfile_ue[0],
xx_pc_err_regfile_ue[1] })
);
end
endgenerate
//----------------------------------------------------------------------
assign rv_hold_all_din = ex3_hangcounter_trigger |
ex3_regfile_err_det_any |
ex4_regfile_err_det_any |
ex5_regfile_err_det_any |
ex6_regfile_err_det_any |
regfile_seq_beg | perr_sm_running;
tri_rlmreg_p #(.INIT(0), .WIDTH(1)) holdall_lat(
.nclk(nclk),
.act(tihi),
.force_t(force_t),
.d_mode(tiup),
.delay_lclkr(delay_lclkr[9]),
.mpw1_b(mpw1_b[9]),
.mpw2_b(mpw2_b[1]),
.thold_b(thold_0_b),
.sg(sg_0),
.vd(vdd),
.gd(gnd),
.scin(holdall_si[0:0]),
.scout(holdall_so[0:0]),
.din(rv_hold_all_din),
//-------------------------------------------
.dout(rv_hold_all_q)
);
//-------------------------------------------
assign xx_rv_hold_all = rv_hold_all_q;
//-------------------------------------------
// perr
assign ex2_perr_si[0:23] = {ex2_perr_so[1:23], perr_si};
assign ex3_perr_si[0:23] = {ex3_perr_so[1:23], ex2_perr_so[0]};
assign perr_sm_si[0:2] = {perr_sm_so[1:2], ex3_perr_so[0]};
assign perr_ctl_si[0:30] = {perr_ctl_so[1:30], perr_sm_so[0]};
assign ex4_ctl_perr_si[0:3] = {ex4_ctl_perr_so[1:3], perr_ctl_so[0]};
assign holdall_si[0] = {ex4_ctl_perr_so[0]};
assign exx_regfile_err_det_si[0:8] = {exx_regfile_err_det_so[1:8], holdall_so[0]};
assign perr_so = exx_regfile_err_det_so[0];
// end perr
endmodule |
module tri_csa42(
a,
b,
c,
d,
ki,
ko,
car,
sum,
vd,
gd
);
input a;
input b;
input c;
input d;
input ki;
output ko;
output car;
output sum;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout gd;
wire s1;
wire carn1;
wire carn2;
wire carn3;
wire kon1;
wire kon2;
wire kon3;
// assign s1 = b ^ c ^ d;
tri_xor3 CSA42_XOR3_1(s1,b,c,d);
// assign sum = s1 ^ a ^ ki;
tri_xor3 CSA42_XOR3_2(sum,s1,a,ki);
// assign car = (s1 & a) | (s1 & ki) | (a & ki);
tri_nand2 CSA42_NAND2_1(carn1,s1,a);
tri_nand2 CSA42_NAND2_2(carn2,s1,ki);
tri_nand2 CSA42_NAND2_3(carn3,a,ki);
tri_nand3 CSA42_NAND3_4(car,carn1,carn2,carn3);
// assign ko = (b & c) | (b & d) | (c & d);
tri_nand2 CSA42_NAND2_5(kon1,b,c);
tri_nand2 CSA42_NAND2_6(kon2,b,d);
tri_nand2 CSA42_NAND2_7(kon3,c,d);
tri_nand3 CSA42_NAND3_8(ko,kon1,kon2,kon3);
endmodule |
module tri_st_or3232_b(
d_b,
or_hi,
or_lo
);
input [0:63] d_b; //data
output or_hi; // upper 32 ORed together
output or_lo; // lower 32 ORed together
wire [0:31] ca_or_lv1;
wire [0:15] ca_or_lv2_b;
wire [0:7] ca_or_lv3;
wire [0:3] ca_or_lv4_b;
wire [0:1] ca_or_lv5;
assign ca_or_lv1[0] = (~(d_b[0] & d_b[1]));
assign ca_or_lv1[1] = (~(d_b[2] & d_b[3]));
assign ca_or_lv1[2] = (~(d_b[4] & d_b[5]));
assign ca_or_lv1[3] = (~(d_b[6] & d_b[7]));
assign ca_or_lv1[4] = (~(d_b[8] & d_b[9]));
assign ca_or_lv1[5] = (~(d_b[10] & d_b[11]));
assign ca_or_lv1[6] = (~(d_b[12] & d_b[13]));
assign ca_or_lv1[7] = (~(d_b[14] & d_b[15]));
assign ca_or_lv1[8] = (~(d_b[16] & d_b[17]));
assign ca_or_lv1[9] = (~(d_b[18] & d_b[19]));
assign ca_or_lv1[10] = (~(d_b[20] & d_b[21]));
assign ca_or_lv1[11] = (~(d_b[22] & d_b[23]));
assign ca_or_lv1[12] = (~(d_b[24] & d_b[25]));
assign ca_or_lv1[13] = (~(d_b[26] & d_b[27]));
assign ca_or_lv1[14] = (~(d_b[28] & d_b[29]));
assign ca_or_lv1[15] = (~(d_b[30] & d_b[31]));
assign ca_or_lv1[16] = (~(d_b[32] & d_b[33]));
assign ca_or_lv1[17] = (~(d_b[34] & d_b[35]));
assign ca_or_lv1[18] = (~(d_b[36] & d_b[37]));
assign ca_or_lv1[19] = (~(d_b[38] & d_b[39]));
assign ca_or_lv1[20] = (~(d_b[40] & d_b[41]));
assign ca_or_lv1[21] = (~(d_b[42] & d_b[43]));
assign ca_or_lv1[22] = (~(d_b[44] & d_b[45]));
assign ca_or_lv1[23] = (~(d_b[46] & d_b[47]));
assign ca_or_lv1[24] = (~(d_b[48] & d_b[49]));
assign ca_or_lv1[25] = (~(d_b[50] & d_b[51]));
assign ca_or_lv1[26] = (~(d_b[52] & d_b[53]));
assign ca_or_lv1[27] = (~(d_b[54] & d_b[55]));
assign ca_or_lv1[28] = (~(d_b[56] & d_b[57]));
assign ca_or_lv1[29] = (~(d_b[58] & d_b[59]));
assign ca_or_lv1[30] = (~(d_b[60] & d_b[61]));
assign ca_or_lv1[31] = (~(d_b[62] & d_b[63]));
assign ca_or_lv2_b[0] = (~(ca_or_lv1[0] | ca_or_lv1[1]));
assign ca_or_lv2_b[1] = (~(ca_or_lv1[2] | ca_or_lv1[3]));
assign ca_or_lv2_b[2] = (~(ca_or_lv1[4] | ca_or_lv1[5]));
assign ca_or_lv2_b[3] = (~(ca_or_lv1[6] | ca_or_lv1[7]));
assign ca_or_lv2_b[4] = (~(ca_or_lv1[8] | ca_or_lv1[9]));
assign ca_or_lv2_b[5] = (~(ca_or_lv1[10] | ca_or_lv1[11]));
assign ca_or_lv2_b[6] = (~(ca_or_lv1[12] | ca_or_lv1[13]));
assign ca_or_lv2_b[7] = (~(ca_or_lv1[14] | ca_or_lv1[15]));
assign ca_or_lv2_b[8] = (~(ca_or_lv1[16] | ca_or_lv1[17]));
assign ca_or_lv2_b[9] = (~(ca_or_lv1[18] | ca_or_lv1[19]));
assign ca_or_lv2_b[10] = (~(ca_or_lv1[20] | ca_or_lv1[21]));
assign ca_or_lv2_b[11] = (~(ca_or_lv1[22] | ca_or_lv1[23]));
assign ca_or_lv2_b[12] = (~(ca_or_lv1[24] | ca_or_lv1[25]));
assign ca_or_lv2_b[13] = (~(ca_or_lv1[26] | ca_or_lv1[27]));
assign ca_or_lv2_b[14] = (~(ca_or_lv1[28] | ca_or_lv1[29]));
assign ca_or_lv2_b[15] = (~(ca_or_lv1[30] | ca_or_lv1[31]));
assign ca_or_lv3[0] = (~(ca_or_lv2_b[0] & ca_or_lv2_b[1]));
assign ca_or_lv3[1] = (~(ca_or_lv2_b[2] & ca_or_lv2_b[3]));
assign ca_or_lv3[2] = (~(ca_or_lv2_b[4] & ca_or_lv2_b[5]));
assign ca_or_lv3[3] = (~(ca_or_lv2_b[6] & ca_or_lv2_b[7]));
assign ca_or_lv3[4] = (~(ca_or_lv2_b[8] & ca_or_lv2_b[9]));
assign ca_or_lv3[5] = (~(ca_or_lv2_b[10] & ca_or_lv2_b[11]));
assign ca_or_lv3[6] = (~(ca_or_lv2_b[12] & ca_or_lv2_b[13]));
assign ca_or_lv3[7] = (~(ca_or_lv2_b[14] & ca_or_lv2_b[15]));
assign ca_or_lv4_b[0] = (~(ca_or_lv3[0] | ca_or_lv3[1]));
assign ca_or_lv4_b[1] = (~(ca_or_lv3[2] | ca_or_lv3[3]));
assign ca_or_lv4_b[2] = (~(ca_or_lv3[4] | ca_or_lv3[5]));
assign ca_or_lv4_b[3] = (~(ca_or_lv3[6] | ca_or_lv3[7]));
assign ca_or_lv5[0] = (~(ca_or_lv4_b[0] & ca_or_lv4_b[1]));
assign ca_or_lv5[1] = (~(ca_or_lv4_b[2] & ca_or_lv4_b[3]));
assign or_hi = ca_or_lv5[0]; // rename
assign or_lo = ca_or_lv5[1]; // rename
// ///////// in placement order //////////////////////////////////////////////
// u_ca_or_00: ca_or_lv1 ( 0) <= not( d_b ( 0) and d_b ( 1) );
// u_ca_or_01: ca_or_lv2_b( 0) <= not( ca_or_lv1 ( 0) or ca_or_lv1 ( 1) );
// u_ca_or_02: ca_or_lv1 ( 1) <= not( d_b ( 2) and d_b ( 3) );
// u_ca_or_03: ca_or_lv3 ( 0) <= not( ca_or_lv2_b( 0) and ca_or_lv2_b( 1) );
// u_ca_or_04: ca_or_lv1 ( 2 <= not( d_b ( 4) and d_b ( 5) );
// u_ca_or_05: ca_or_lv2_b( 1) <= not( ca_or_lv1 ( 2) or ca_or_lv1 ( 3) );
// u_ca_or_06: ca_or_lv1 ( 3) <= not( d_b ( 6) and d_b ( 7) );
// u_ca_or_07: ca_or_lv4_b( 0) <= not( ca_or_lv3 ( 0) or ca_or_lv3 ( 1) );
// u_ca_or_08: ca_or_lv1 ( 4) <= not( d_b ( 8) and d_b ( 9) );
// u_ca_or_09: ca_or_lv2_b( 2) <= not( ca_or_lv1 ( 4) or ca_or_lv1 ( 5) );
// u_ca_or_10: ca_or_lv1 ( 5) <= not( d_b (10) and d_b (11) );
// u_ca_or_11: ca_or_lv3 ( 1) <= not( ca_or_lv2_b( 2) and ca_or_lv2_b( 3) );
// u_ca_or_12: ca_or_lv1 ( 6) <= not( d_b (12) and d_b (13) );
// u_ca_or_13: ca_or_lv2_b( 3) <= not( ca_or_lv1 ( 6) or ca_or_lv1 ( 7) );
// u_ca_or_14: ca_or_lv1 ( 7) <= not( d_b (14) and d_b (15) );
// u_ca_or_15: ca_or_lv5 ( 0) <= not( ca_or_lv4_b( 0) and ca_or_lv4_b( 1) );
// u_ca_or_16: ca_or_lv1 ( 8) <= not( d_b (16) and d_b (17) );
// u_ca_or_17: ca_or_lv2_b( 4) <= not( ca_or_lv1 ( 8) or ca_or_lv1 ( 9) );
// u_ca_or_18: ca_or_lv1 ( 9) <= not( d_b (18) and d_b (19) );
// u_ca_or_19: ca_or_lv3 ( 2) <= not( ca_or_lv2_b( 4) and ca_or_lv2_b( 5) );
// u_ca_or_20: ca_or_lv1 (10) <= not( d_b (20) and d_b (21) );
// u_ca_or_21: ca_or_lv2_b( 5) <= not( ca_or_lv1 (10) or ca_or_lv1 (11) );
// u_ca_or_22: ca_or_lv1 (11) <= not( d_b (22) and d_b (23) );
// u_ca_or_23: ca_or_lv4_b( 1) <= not( ca_or_lv3 ( 2) or ca_or_lv3 ( 3) );
// u_ca_or_24: ca_or_lv1 (12) <= not( d_b (24) and d_b (25) );
// u_ca_or_25: ca_or_lv2_b( 6) <= not( ca_or_lv1 (12) or ca_or_lv1 (13) );
// u_ca_or_26: ca_or_lv1 (13) <= not( d_b (26) and d_b (27) );
// u_ca_or_27: ca_or_lv3 ( 3) <= not( ca_or_lv2_b( 6) and ca_or_lv2_b( 7) );
// u_ca_or_28: ca_or_lv1 (14) <= not( d_b (28) and d_b (29) );
// u_ca_or_29: ca_or_lv2_b( 7) <= not( ca_or_lv1 (14) or ca_or_lv1 (15) );
// u_ca_or_30: ca_or_lv1 (15) <= not( d_b (30) and d_b (31) );
// u_ca_or_32: ca_or_lv1 (16) <= not( d_b (32) and d_b (33) );
// u_ca_or_33: ca_or_lv2_b( 8) <= not( ca_or_lv1 (16) or ca_or_lv1 (17) );
// u_ca_or_34: ca_or_lv1 (17) <= not( d_b (34) and d_b (35) );
// u_ca_or_35: ca_or_lv3 ( 4) <= not( ca_or_lv2_b( 8) and ca_or_lv2_b( 9) );
// u_ca_or_36: ca_or_lv1 (18) <= not( d_b (36) and d_b (37) );
// u_ca_or_37: ca_or_lv2_b( 9) <= not( ca_or_lv1 (18) or ca_or_lv1 (19) );
// u_ca_or_38: ca_or_lv1 (19) <= not( d_b (38) and d_b (39) );
// u_ca_or_39: ca_or_lv4_b( 2) <= not( ca_or_lv3 ( 4) or ca_or_lv3 ( 5) );
// u_ca_or_40: ca_or_lv1 (20) <= not( d_b (40) and d_b (41) );
// u_ca_or_41: ca_or_lv2_b(10) <= not( ca_or_lv1 (20) or ca_or_lv1 (21) );
// u_ca_or_42: ca_or_lv1 (21) <= not( d_b (42) and d_b (43) );
// u_ca_or_43: ca_or_lv3 ( 5) <= not( ca_or_lv2_b(10) and ca_or_lv2_b(11) );
// u_ca_or_44: ca_or_lv1 (22) <= not( d_b (44) and d_b (45) );
// u_ca_or_45: ca_or_lv2_b(11) <= not( ca_or_lv1 (22) or ca_or_lv1 (23) );
// u_ca_or_46: ca_or_lv1 (23) <= not( d_b (46) and d_b (47) );
// u_ca_or_47: ca_or_lv5 ( 1) <= not( ca_or_lv4_b( 2) and ca_or_lv4_b( 3) );
// u_ca_or_48: ca_or_lv1 (24) <= not( d_b (48) and d_b (49) );
// u_ca_or_49: ca_or_lv2_b(12) <= not( ca_or_lv1 (24) or ca_or_lv1 (25) );
// u_ca_or_50: ca_or_lv1 (25) <= not( d_b (50) and d_b (51) );
// u_ca_or_51: ca_or_lv3 ( 6) <= not( ca_or_lv2_b(12) and ca_or_lv2_b(13) );
// u_ca_or_52: ca_or_lv1 (26) <= not( d_b (52) and d_b (53) );
// u_ca_or_53: ca_or_lv2_b(13) <= not( ca_or_lv1 (26) or ca_or_lv1 (27) );
// u_ca_or_54: ca_or_lv1 (27) <= not( d_b (54) and d_b (55) );
// u_ca_or_55: ca_or_lv4_b( 3) <= not( ca_or_lv3 ( 6) or ca_or_lv3 ( 7) );
// u_ca_or_56: ca_or_lv1 (28) <= not( d_b (56) and d_b (57) );
// u_ca_or_57: ca_or_lv2_b(14) <= not( ca_or_lv1 (28) or ca_or_lv1 (29) );
// u_ca_or_58: ca_or_lv1 (29) <= not( d_b (58) and d_b (59) );
// u_ca_or_59: ca_or_lv3 ( 7) <= not( ca_or_lv2_b(14) and ca_or_lv2_b(15) );
// u_ca_or_60: ca_or_lv1 (30) <= not( d_b (60) and d_b (61) );
// u_ca_or_61: ca_or_lv2_b(15) <= not( ca_or_lv1 (30) or ca_or_lv1 (31) );
// u_ca_or_62: ca_or_lv1 (31) <= not( d_b (62) and d_b (63) );
//
// -- --
endmodule |
module tri_inv(
y,
a
);
parameter WIDTH = 1;
parameter BTR = "INV_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
// tri_nand2
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w
not I0(y[i], a[i]);
end // block: w
end
endgenerate
endmodule |
module tri_csa32(
a,
b,
c,
car,
sum,
vd,
gd
);
input a;
input b;
input c;
output car;
output sum;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout gd;
wire carn1;
wire carn2;
wire carn3;
// assign sum = a ^ b ^ c;
tri_xor3 CSA42_XOR3_1(sum, a, b, c);
// assign car = (a & b) | (a & c) | (b & c);
tri_nand2 CSA42_NAND2_1(carn1, a, b);
tri_nand2 CSA42_NAND2_2(carn2, a, c);
tri_nand2 CSA42_NAND2_3(carn3, b, c);
tri_nand3 CSA42_NAND3_4(car, carn1, carn2, carn3);
endmodule |
module tri_eccchk(
din,
encorr,
nsyn,
corrd,
sbe,
ue
);
parameter REGSIZE = 64;
input [0:REGSIZE-1] din;
input encorr;
input [0:8-(64/REGSIZE)] nsyn;
output [0:REGSIZE-1] corrd;
output sbe;
output ue;
generate // syndrome bits inverted
if (REGSIZE == 64)
begin : ecc64
wire [0:7] syn;
wire [0:71] DcdD; // decode data bits
wire synzero;
wire sbe_int;
wire [0:3] A0to1;
wire [0:3] A2to3;
wire [0:3] A4to5;
wire [0:2] A6to7;
// ====================================================================
// 64 Data Bits, 8 Check bits
// Single bit error correction, Double bit error detection
// ====================================================================
// ECC Matrix Description
// ====================================================================
// Syn 0 111011010011101001100101101101001100101101001011001101001110100110000000
// Syn 1 110110101011010101010101011010101010101010101010101010101101010101000000
// Syn 2 101101100110110011001100110110011001100110011001100110011011001100100000
// Syn 3 011100011110001111000011110001111000011110000111100001111000111100010000
// Syn 4 000011111110000000111111110000000111111110000000011111111000000000001000
// Syn 5 000000000001111111111111110000000000000001111111111111111000000000000100
// Syn 6 000000000000000000000000001111111111111111111111111111111000000000000010
// Syn 7 000000000000000000000000000000000000000000000000000000000111111100000001
assign syn = (~nsyn[0:7]);
assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr));
assign A0to1[1] = (~(nsyn[0] & syn[1] & encorr));
assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr));
assign A0to1[3] = (~( syn[0] & syn[1] & encorr));
assign A2to3[0] = (~(nsyn[2] & nsyn[3]));
assign A2to3[1] = (~(nsyn[2] & syn[3]));
assign A2to3[2] = (~( syn[2] & nsyn[3]));
assign A2to3[3] = (~( syn[2] & syn[3]));
assign A4to5[0] = (~(nsyn[4] & nsyn[5]));
assign A4to5[1] = (~(nsyn[4] & syn[5]));
assign A4to5[2] = (~( syn[4] & nsyn[5]));
assign A4to5[3] = (~( syn[4] & syn[5]));
assign A6to7[0] = (~(nsyn[6] & nsyn[7]));
assign A6to7[1] = (~(nsyn[6] & syn[7]));
assign A6to7[2] = (~( syn[6] & nsyn[7]));
//assign A6to7[3] = (~( syn[6] & syn[7]));
assign DcdD[0] = (~(A0to1[3] | A2to3[2] | A4to5[0] | A6to7[0])); // 11 10 00 00
assign DcdD[1] = (~(A0to1[3] | A2to3[1] | A4to5[0] | A6to7[0])); // 11 01 00 00
assign DcdD[2] = (~(A0to1[2] | A2to3[3] | A4to5[0] | A6to7[0])); // 10 11 00 00
assign DcdD[3] = (~(A0to1[1] | A2to3[3] | A4to5[0] | A6to7[0])); // 01 11 00 00
assign DcdD[4] = (~(A0to1[3] | A2to3[0] | A4to5[2] | A6to7[0])); // 11 00 10 00
assign DcdD[5] = (~(A0to1[2] | A2to3[2] | A4to5[2] | A6to7[0])); // 10 10 10 00
assign DcdD[6] = (~(A0to1[1] | A2to3[2] | A4to5[2] | A6to7[0])); // 01 10 10 00
assign DcdD[7] = (~(A0to1[2] | A2to3[1] | A4to5[2] | A6to7[0])); // 10 01 10 00
assign DcdD[8] = (~(A0to1[1] | A2to3[1] | A4to5[2] | A6to7[0])); // 01 01 10 00
assign DcdD[9] = (~(A0to1[0] | A2to3[3] | A4to5[2] | A6to7[0])); // 00 11 10 00
assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to5[2] | A6to7[0])); // 11 11 10 00
assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to5[1] | A6to7[0])); // 11 00 01 00
assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to5[1] | A6to7[0])); // 10 10 01 00
assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to5[1] | A6to7[0])); // 01 10 01 00
assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to5[1] | A6to7[0])); // 10 01 01 00
assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to5[1] | A6to7[0])); // 01 01 01 00
assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to5[1] | A6to7[0])); // 00 11 01 00
assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to5[1] | A6to7[0])); // 11 11 01 00
assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to5[3] | A6to7[0])); // 10 00 11 00
assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to5[3] | A6to7[0])); // 01 00 11 00
assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to5[3] | A6to7[0])); // 00 10 11 00
assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to5[3] | A6to7[0])); // 11 10 11 00
assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to5[3] | A6to7[0])); // 00 01 11 00
assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to5[3] | A6to7[0])); // 11 01 11 00
assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to5[3] | A6to7[0])); // 10 11 11 00
assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to5[3] | A6to7[0])); // 01 11 11 00
assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[2])); // 11 00 00 10
assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[2])); // 10 10 00 10
assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[2])); // 01 10 00 10
assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[2])); // 10 01 00 10
assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[2])); // 01 01 00 10
assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[2])); // 00 11 00 10
assign DcdD[32] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[2])); // 11 11 00 10
assign DcdD[33] = (~(A0to1[2] | A2to3[0] | A4to5[2] | A6to7[2])); // 10 00 10 10
assign DcdD[34] = (~(A0to1[1] | A2to3[0] | A4to5[2] | A6to7[2])); // 01 00 10 10
assign DcdD[35] = (~(A0to1[0] | A2to3[2] | A4to5[2] | A6to7[2])); // 00 10 10 10
assign DcdD[36] = (~(A0to1[3] | A2to3[2] | A4to5[2] | A6to7[2])); // 11 10 10 10
assign DcdD[37] = (~(A0to1[0] | A2to3[1] | A4to5[2] | A6to7[2])); // 00 01 10 10
assign DcdD[38] = (~(A0to1[3] | A2to3[1] | A4to5[2] | A6to7[2])); // 11 01 10 10
assign DcdD[39] = (~(A0to1[2] | A2to3[3] | A4to5[2] | A6to7[2])); // 10 11 10 10
assign DcdD[40] = (~(A0to1[1] | A2to3[3] | A4to5[2] | A6to7[2])); // 01 11 10 10
assign DcdD[41] = (~(A0to1[2] | A2to3[0] | A4to5[1] | A6to7[2])); // 10 00 01 10
assign DcdD[42] = (~(A0to1[1] | A2to3[0] | A4to5[1] | A6to7[2])); // 01 00 01 10
assign DcdD[43] = (~(A0to1[0] | A2to3[2] | A4to5[1] | A6to7[2])); // 00 10 01 10
assign DcdD[44] = (~(A0to1[3] | A2to3[2] | A4to5[1] | A6to7[2])); // 11 10 01 10
assign DcdD[45] = (~(A0to1[0] | A2to3[1] | A4to5[1] | A6to7[2])); // 00 01 01 10
assign DcdD[46] = (~(A0to1[3] | A2to3[1] | A4to5[1] | A6to7[2])); // 11 01 01 10
assign DcdD[47] = (~(A0to1[2] | A2to3[3] | A4to5[1] | A6to7[2])); // 10 11 01 10
assign DcdD[48] = (~(A0to1[1] | A2to3[3] | A4to5[1] | A6to7[2])); // 01 11 01 10
assign DcdD[49] = (~(A0to1[0] | A2to3[0] | A4to5[3] | A6to7[2])); // 00 00 11 10
assign DcdD[50] = (~(A0to1[3] | A2to3[0] | A4to5[3] | A6to7[2])); // 11 00 11 10
assign DcdD[51] = (~(A0to1[2] | A2to3[2] | A4to5[3] | A6to7[2])); // 10 10 11 10
assign DcdD[52] = (~(A0to1[1] | A2to3[2] | A4to5[3] | A6to7[2])); // 01 10 11 10
assign DcdD[53] = (~(A0to1[2] | A2to3[1] | A4to5[3] | A6to7[2])); // 10 01 11 10
assign DcdD[54] = (~(A0to1[1] | A2to3[1] | A4to5[3] | A6to7[2])); // 01 01 11 10
assign DcdD[55] = (~(A0to1[0] | A2to3[3] | A4to5[3] | A6to7[2])); // 00 11 11 10
assign DcdD[56] = (~(A0to1[3] | A2to3[3] | A4to5[3] | A6to7[2])); // 11 11 11 10
assign DcdD[57] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[1])); // 11 00 00 01
assign DcdD[58] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[1])); // 10 10 00 01
assign DcdD[59] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[1])); // 01 10 00 01
assign DcdD[60] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[1])); // 10 01 00 01
assign DcdD[61] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[1])); // 01 01 00 01
assign DcdD[62] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[1])); // 00 11 00 01
assign DcdD[63] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[1])); // 11 11 00 01
assign DcdD[64] = (~(A0to1[2] | A2to3[0] | A4to5[0] | A6to7[0])); // 10 00 00 00
assign DcdD[65] = (~(A0to1[1] | A2to3[0] | A4to5[0] | A6to7[0])); // 01 00 00 00
assign DcdD[66] = (~(A0to1[0] | A2to3[2] | A4to5[0] | A6to7[0])); // 00 10 00 00
assign DcdD[67] = (~(A0to1[0] | A2to3[1] | A4to5[0] | A6to7[0])); // 00 01 00 00
assign DcdD[68] = (~(A0to1[0] | A2to3[0] | A4to5[2] | A6to7[0])); // 00 00 10 00
assign DcdD[69] = (~(A0to1[0] | A2to3[0] | A4to5[1] | A6to7[0])); // 00 00 01 00
assign DcdD[70] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[2])); // 00 00 00 10
assign DcdD[71] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[1])); // 00 00 00 01
assign synzero = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[0])); // 00 00 00 00
assign corrd[0:63] = din[0:63] ^ DcdD[0:63];
assign sbe_int = (DcdD[0:71] != {72{1'b0}}) ? 1'b1 :
1'b0;
assign sbe = sbe_int;
assign ue = (~sbe_int) & (~synzero) & encorr;
end
endgenerate
generate // syndrome bits inverted
if (REGSIZE == 32)
begin : ecc32
wire [0:6] syn;
wire [0:38] DcdD; // decode data bits
wire synzero;
wire sbe_int;
wire [0:3] A0to1;
wire [0:3] A2to3;
wire [0:7] A4to6;
// ====================================================================
// 32 Data Bits, 7 Check bits
// Single bit error correction, Double bit error detection
// ====================================================================
// ECC Matrix Description
// ====================================================================
// Syn 0 111011010011101001100101101101001000000
// Syn 1 110110101011010101010101011010100100000
// Syn 2 101101100110110011001100110110010010000
// Syn 3 011100011110001111000011110001110001000
// Syn 4 000011111110000000111111110000000000100
// Syn 5 000000000001111111111111110000000000010
// Syn 6 000000000000000000000000001111110000001
assign syn = (~nsyn[0:6]);
assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr));
assign A0to1[1] = (~(nsyn[0] & syn[1] & encorr));
assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr));
assign A0to1[3] = (~( syn[0] & syn[1] & encorr));
assign A2to3[0] = (~(nsyn[2] & nsyn[3]));
assign A2to3[1] = (~(nsyn[2] & syn[3]));
assign A2to3[2] = (~( syn[2] & nsyn[3]));
assign A2to3[3] = (~( syn[2] & syn[3]));
assign A4to6[0] = (~(nsyn[4] & nsyn[5] & nsyn[6]));
assign A4to6[1] = (~(nsyn[4] & nsyn[5] & syn[6]));
assign A4to6[2] = (~(nsyn[4] & syn[5] & nsyn[6]));
assign A4to6[3] = (~(nsyn[4] & syn[5] & syn[6]));
assign A4to6[4] = (~( syn[4] & nsyn[5] & nsyn[6]));
assign A4to6[5] = (~( syn[4] & nsyn[5] & syn[6]));
assign A4to6[6] = (~( syn[4] & syn[5] & nsyn[6]));
assign A4to6[7] = (~( syn[4] & syn[5] & syn[6]));
assign DcdD[0] = (~(A0to1[3] | A2to3[2] | A4to6[0])); // 11 10 000
assign DcdD[1] = (~(A0to1[3] | A2to3[1] | A4to6[0])); // 11 01 000
assign DcdD[2] = (~(A0to1[2] | A2to3[3] | A4to6[0])); // 10 11 000
assign DcdD[3] = (~(A0to1[1] | A2to3[3] | A4to6[0])); // 01 11 000
assign DcdD[4] = (~(A0to1[3] | A2to3[0] | A4to6[4])); // 11 00 100
assign DcdD[5] = (~(A0to1[2] | A2to3[2] | A4to6[4])); // 10 10 100
assign DcdD[6] = (~(A0to1[1] | A2to3[2] | A4to6[4])); // 01 10 100
assign DcdD[7] = (~(A0to1[2] | A2to3[1] | A4to6[4])); // 10 01 100
assign DcdD[8] = (~(A0to1[1] | A2to3[1] | A4to6[4])); // 01 01 100
assign DcdD[9] = (~(A0to1[0] | A2to3[3] | A4to6[4])); // 00 11 100
assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to6[4])); // 11 11 100
assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to6[2])); // 11 00 010
assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to6[2])); // 10 10 010
assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to6[2])); // 01 10 010
assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to6[2])); // 10 01 010
assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to6[2])); // 01 01 010
assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to6[2])); // 00 11 010
assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to6[2])); // 11 11 010
assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to6[6])); // 10 00 110
assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to6[6])); // 01 00 110
assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to6[6])); // 00 10 110
assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to6[6])); // 11 10 110
assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to6[6])); // 00 01 110
assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to6[6])); // 11 01 110
assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to6[6])); // 10 11 110
assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to6[6])); // 01 11 110
assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to6[1])); // 11 00 001
assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to6[1])); // 10 10 001
assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to6[1])); // 01 10 001
assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to6[1])); // 10 01 001
assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to6[1])); // 01 01 001
assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to6[1])); // 00 11 001
assign DcdD[32] = (~(A0to1[2] | A2to3[0] | A4to6[0])); // 10 00 000
assign DcdD[33] = (~(A0to1[1] | A2to3[0] | A4to6[0])); // 01 00 000
assign DcdD[34] = (~(A0to1[0] | A2to3[2] | A4to6[0])); // 00 10 000
assign DcdD[35] = (~(A0to1[0] | A2to3[1] | A4to6[0])); // 00 01 000
assign DcdD[36] = (~(A0to1[0] | A2to3[0] | A4to6[4])); // 00 00 100
assign DcdD[37] = (~(A0to1[0] | A2to3[0] | A4to6[2])); // 00 00 010
assign DcdD[38] = (~(A0to1[0] | A2to3[0] | A4to6[1])); // 00 00 001
assign synzero = (~(A0to1[0] | A2to3[0] | A4to6[0])); // 00 00 000
assign corrd[0:31] = din[0:31] ^ DcdD[0:31];
assign sbe_int = (DcdD[0:38] != {39{1'b0}}) ? 1'b1 :
1'b0;
assign sbe = sbe_int;
assign ue = (~sbe_int) & (~synzero) & encorr;
//mark_unused(A4to6(3));
//mark_unused(A4to6(5));
//mark_unused(A4to6(7));
end
endgenerate
endmodule |
module tri_debug_mux8(
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
dbg_group4,
dbg_group5,
dbg_group6,
dbg_group7,
trace_data_in,
trace_data_out,
// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);
// Include model build parameters
parameter DBG_WIDTH = 32; // A2o=32; A2i=88
//=====================================================================
// Port Definitions
//=====================================================================
input [0:10] select_bits;
input [0:DBG_WIDTH-1] dbg_group0;
input [0:DBG_WIDTH-1] dbg_group1;
input [0:DBG_WIDTH-1] dbg_group2;
input [0:DBG_WIDTH-1] dbg_group3;
input [0:DBG_WIDTH-1] dbg_group4;
input [0:DBG_WIDTH-1] dbg_group5;
input [0:DBG_WIDTH-1] dbg_group6;
input [0:DBG_WIDTH-1] dbg_group7;
input [0:DBG_WIDTH-1] trace_data_in;
output [0:DBG_WIDTH-1] trace_data_out;
// Instruction Trace (HTM) Control Signals:
// 0 - ac_an_coretrace_first_valid
// 1 - ac_an_coretrace_valid
// 2:3 - ac_an_coretrace_type[0:1]
input [0:3] coretrace_ctrls_in;
output [0:3] coretrace_ctrls_out;
//=====================================================================
// Signal Declarations / Misc
//=====================================================================
parameter DBG_1FOURTH = DBG_WIDTH/4;
parameter DBG_2FOURTH = DBG_WIDTH/2;
parameter DBG_3FOURTH = 3 * DBG_WIDTH/4;
wire [0:DBG_WIDTH-1] debug_grp_selected;
wire [0:DBG_WIDTH-1] debug_grp_rotated;
// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
wire unused;
assign unused = (|select_bits[3:4]) ;
// Instruction Trace controls are passed-through:
assign coretrace_ctrls_out = coretrace_ctrls_in ;
//=====================================================================
// Mux Function
//=====================================================================
// Debug Mux
assign debug_grp_selected = (select_bits[0:2] == 3'b000) ? dbg_group0 :
(select_bits[0:2] == 3'b001) ? dbg_group1 :
(select_bits[0:2] == 3'b010) ? dbg_group2 :
(select_bits[0:2] == 3'b011) ? dbg_group3 :
(select_bits[0:2] == 3'b100) ? dbg_group4 :
(select_bits[0:2] == 3'b101) ? dbg_group5 :
(select_bits[0:2] == 3'b110) ? dbg_group6 :
dbg_group7;
assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
debug_grp_selected[0:DBG_WIDTH - 1];
assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
debug_grp_rotated[0:DBG_1FOURTH - 1];
assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
endmodule |
module tri_regk(
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter SYNTHCLONEDLATCH = "";
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock
input d_mode; // 1: disable pulse mode, 0: pulse mode
input sg; // 0: functional, 1: scan
input delay_lclkr; // 0: functional
input mpw1_b; // pulse width control bit
input mpw2_b; // pulse width control bit
input [OFFSET:OFFSET+WIDTH-1] scin; // scan in
input [OFFSET:OFFSET+WIDTH-1] din; // data in
output [OFFSET:OFFSET+WIDTH-1] scout;
output [OFFSET:OFFSET+WIDTH-1] dout;
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
// tri_regk
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1)
begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{act | force_t}};
assign vact_b = {WIDTH{~(act | force_t)}};
assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}};
always @(posedge nclk[0])
begin: l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign dout = int_dout;
assign scout = ZEROS;
assign unused = | {vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin};
end
endgenerate
endmodule |
module tri_debug_mux16(
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
dbg_group4,
dbg_group5,
dbg_group6,
dbg_group7,
dbg_group8,
dbg_group9,
dbg_group10,
dbg_group11,
dbg_group12,
dbg_group13,
dbg_group14,
dbg_group15,
trace_data_in,
trace_data_out,
// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);
// Include model build parameters
parameter DBG_WIDTH = 32; // A2o=32; A2i=88
//=====================================================================
// Port Definitions
//=====================================================================
input [0:10] select_bits;
input [0:DBG_WIDTH-1] dbg_group0;
input [0:DBG_WIDTH-1] dbg_group1;
input [0:DBG_WIDTH-1] dbg_group2;
input [0:DBG_WIDTH-1] dbg_group3;
input [0:DBG_WIDTH-1] dbg_group4;
input [0:DBG_WIDTH-1] dbg_group5;
input [0:DBG_WIDTH-1] dbg_group6;
input [0:DBG_WIDTH-1] dbg_group7;
input [0:DBG_WIDTH-1] dbg_group8;
input [0:DBG_WIDTH-1] dbg_group9;
input [0:DBG_WIDTH-1] dbg_group10;
input [0:DBG_WIDTH-1] dbg_group11;
input [0:DBG_WIDTH-1] dbg_group12;
input [0:DBG_WIDTH-1] dbg_group13;
input [0:DBG_WIDTH-1] dbg_group14;
input [0:DBG_WIDTH-1] dbg_group15;
input [0:DBG_WIDTH-1] trace_data_in;
output [0:DBG_WIDTH-1] trace_data_out;
// Instruction Trace (HTM) Control Signals:
// 0 - ac_an_coretrace_first_valid
// 1 - ac_an_coretrace_valid
// 2:3 - ac_an_coretrace_type[0:1]
input [0:3] coretrace_ctrls_in;
output [0:3] coretrace_ctrls_out;
//=====================================================================
// Signal Declarations / Misc
//=====================================================================
parameter DBG_1FOURTH = DBG_WIDTH/4;
parameter DBG_2FOURTH = DBG_WIDTH/2;
parameter DBG_3FOURTH = 3 * DBG_WIDTH/4;
wire [0:DBG_WIDTH-1] debug_grp_selected;
wire [0:DBG_WIDTH-1] debug_grp_rotated;
// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
wire unused;
assign unused = select_bits[4];
// Instruction Trace controls are passed-through:
assign coretrace_ctrls_out = coretrace_ctrls_in ;
//=====================================================================
// Mux Function
//=====================================================================
// Debug Mux
assign debug_grp_selected = (select_bits[0:3] == 4'b0000) ? dbg_group0 :
(select_bits[0:3] == 4'b0001) ? dbg_group1 :
(select_bits[0:3] == 4'b0010) ? dbg_group2 :
(select_bits[0:3] == 4'b0011) ? dbg_group3 :
(select_bits[0:3] == 4'b0100) ? dbg_group4 :
(select_bits[0:3] == 4'b0101) ? dbg_group5 :
(select_bits[0:3] == 4'b0110) ? dbg_group6 :
(select_bits[0:3] == 4'b0111) ? dbg_group7 :
(select_bits[0:3] == 4'b1000) ? dbg_group8 :
(select_bits[0:3] == 4'b1001) ? dbg_group9 :
(select_bits[0:3] == 4'b1010) ? dbg_group10 :
(select_bits[0:3] == 4'b1011) ? dbg_group11 :
(select_bits[0:3] == 4'b1100) ? dbg_group12 :
(select_bits[0:3] == 4'b1101) ? dbg_group13 :
(select_bits[0:3] == 4'b1110) ? dbg_group14 :
dbg_group15;
assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
debug_grp_selected[0:DBG_WIDTH - 1];
assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
debug_grp_rotated[0:DBG_1FOURTH - 1];
assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
endmodule |
module tri_rot16s_ru(
opsize,
le,
le_rotate_sel,
be_rotate_sel,
algebraic,
le_algebraic_sel,
be_algebraic_sel,
arr_data,
stq7_byp_val,
stq_byp_val,
stq7_rmw_data,
stq8_rmw_data,
data_latched,
data_rot,
algebraic_bit,
nclk,
vdd,
gnd,
delay_lclkr_dc,
mpw1_dc_b,
mpw2_dc_b,
func_sl_force,
func_sl_thold_0_b,
sg_0,
act,
scan_in,
scan_out
);
input [0:4] opsize; // (0)16B (1)8B (2)4B (3)2B (4)1B
input le;
input [0:3] le_rotate_sel;
input [0:3] be_rotate_sel;
input algebraic;
input [0:3] le_algebraic_sel;
input [0:3] be_algebraic_sel;
input [0:15] arr_data; // data to rotate
input stq7_byp_val;
input stq_byp_val;
input [0:15] stq7_rmw_data;
input [0:15] stq8_rmw_data;
output [0:15] data_latched; // latched data, not rotated
output [0:15] data_rot; // rotated data out
output [0:5] algebraic_bit;
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
input [0:`NCLK_WIDTH-1] nclk;
inout vdd;
inout gnd;
input delay_lclkr_dc;
input mpw1_dc_b;
input mpw2_dc_b;
input func_sl_force;
input func_sl_thold_0_b;
input sg_0;
input act;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out;
// tri_rot16s_ru
wire my_d1clk;
wire my_d2clk;
wire [0:`NCLK_WIDTH-1] my_lclk;
wire [0:15] data_latched_b;
wire [0:0] bele_gp0_q_b;
wire [0:0] bele_gp0_q;
wire [0:0] bele_gp0_din;
wire [0:3] be_shx04_gp0_q_b;
wire [0:3] be_shx04_gp0_q;
wire [0:3] be_shx04_gp0_din;
wire [0:3] le_shx04_gp0_q_b;
wire [0:3] le_shx04_gp0_q;
wire [0:3] le_shx04_gp0_din;
wire [0:3] be_shx01_gp0_q_b;
wire [0:3] be_shx01_gp0_q;
wire [0:3] be_shx01_gp0_din;
wire [0:3] le_shx01_gp0_q_b;
wire [0:3] le_shx01_gp0_q;
wire [0:3] le_shx01_gp0_din;
wire [0:4] mask_q_b;
wire [0:4] mask_q;
wire [0:4] mask_din;
wire [0:3] be_shx04_sgn0_q_b;
wire [0:3] be_shx04_sgn0_q;
wire [0:3] be_shx04_sgn0_din;
wire [0:3] le_shx04_sgn0_q_b;
wire [0:3] le_shx04_sgn0_q;
wire [0:3] le_shx04_sgn0_din;
wire [0:3] be_shx01_sgn0_q_b;
wire [0:3] be_shx01_sgn0_q;
wire [0:3] be_shx01_sgn0_din;
wire [0:3] le_shx01_sgn0_q_b;
wire [0:3] le_shx01_sgn0_q;
wire [0:3] le_shx01_sgn0_din;
wire [0:15] mxbele_b;
wire [0:15] mxbele;
wire [0:15] mx1_0_b;
wire [0:15] mx1_1_b;
wire [0:15] mx1;
wire [0:15] mx2_0_b;
wire [0:15] mx2_1_b;
wire [0:15] mx2;
wire [0:7] sx1_0_b;
wire [0:7] sx1_1_b;
wire [0:7] sx1;
wire [0:5] sx2_0_b;
wire [0:5] sx2_1_b;
wire [0:5] sx2;
wire [0:15] do_b;
wire [0:5] sign_copy_b;
wire [0:15] mxbele_d0;
wire [0:15] mxbele_d1;
wire [0:15] bele_s0;
wire [0:15] bele_s1;
wire [0:3] shx04_gp0_sel_b;
wire [0:3] shx04_gp0_sel;
wire [0:3] shx04_sgn0_sel_b;
wire [0:3] shx04_sgn0_sel;
wire [0:3] shx01_gp0_sel_b;
wire [0:3] shx01_gp0_sel;
wire [0:3] shx01_sgn0_sel_b;
wire [0:3] shx01_sgn0_sel;
wire [0:15] mx1_d0;
wire [0:15] mx1_d1;
wire [0:15] mx1_d2;
wire [0:15] mx1_d3;
wire [0:15] mx2_d0;
wire [0:15] mx2_d1;
wire [0:15] mx2_d2;
wire [0:15] mx2_d3;
wire [0:15] mx1_s0;
wire [0:15] mx1_s1;
wire [0:15] mx1_s2;
wire [0:15] mx1_s3;
wire [0:15] mx2_s0;
wire [0:15] mx2_s1;
wire [0:15] mx2_s2;
wire [0:15] mx2_s3;
wire [0:7] sx1_d0;
wire [0:7] sx1_d1;
wire [0:7] sx1_d2;
wire [0:7] sx1_d3;
wire [0:5] sx2_d0;
wire [0:5] sx2_d1;
wire [0:5] sx2_d2;
wire [0:5] sx2_d3;
wire [0:7] sx1_s0;
wire [0:7] sx1_s1;
wire [0:7] sx1_s2;
wire [0:7] sx1_s3;
wire [0:5] sx2_s0;
wire [0:5] sx2_s1;
wire [0:5] sx2_s2;
wire [0:5] sx2_s3;
wire [0:15] mask_en;
wire [0:3] be_shx04_sel;
wire [0:3] be_shx01_sel;
wire [0:3] le_shx04_sel;
wire [0:3] le_shx01_sel;
wire [0:3] be_shx04_sgn;
wire [0:3] be_shx01_sgn;
wire [0:3] le_shx04_sgn;
wire [0:3] le_shx01_sgn;
wire [0:15] stq_byp_data;
wire [0:15] rotate_data;
//--------------------------
// constants
//--------------------------
parameter bele_gp0_din_offset = 0;
parameter be_shx04_gp0_din_offset = bele_gp0_din_offset + 1;
parameter le_shx04_gp0_din_offset = be_shx04_gp0_din_offset + 4;
parameter be_shx01_gp0_din_offset = le_shx04_gp0_din_offset + 4;
parameter le_shx01_gp0_din_offset = be_shx01_gp0_din_offset + 4;
parameter mask_din_offset = le_shx01_gp0_din_offset + 4;
parameter be_shx04_sgn0_din_offset = mask_din_offset + 5;
parameter be_shx01_sgn0_din_offset = be_shx04_sgn0_din_offset + 4;
parameter le_shx04_sgn0_din_offset = be_shx01_sgn0_din_offset + 4;
parameter le_shx01_sgn0_din_offset = le_shx04_sgn0_din_offset + 4;
parameter scan_right = le_shx01_sgn0_din_offset + 4 - 1;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
// #############################################################################################
// Little Endian Rotate Support
// Optype2 Optype4 Optype8
// B31 => rot_data(248:255)
// B30 => rot_data(240:247)
// B29 => rot_data(232:239)
// B28 => rot_data(224:231)
// B31 => rot_data(248:255) B27 => rot_data(216:223)
// B30 => rot_data(240:247) B26 => rot_data(208:215)
// B15 => rot_data(248:255) B29 => rot_data(232:239) B25 => rot_data(200:207)
// B14 => rot_data(240:247) B28 => rot_data(224:231) B24 => rot_data(192:199)
//
// Optype16
// B31 => rot_data(248:255) B23 => rot_data(184:191)
// B30 => rot_data(240:247) B22 => rot_data(176:183)
// B29 => rot_data(232:239) B21 => rot_data(168:175)
// B28 => rot_data(224:231) B20 => rot_data(160:167)
// B27 => rot_data(216:223) B19 => rot_data(152:159)
// B26 => rot_data(208:215) B18 => rot_data(144:151)
// B25 => rot_data(200:207) B17 => rot_data(136:143)
// B24 => rot_data(192:199) B16 => rot_data(128:135)
//
// #############################################################################################
//-- 0,1,2,3 byte rotation
//with rot_sel(2 to 3) select
// rot3210 <= rot_data(104 to 127) & rot_data(0 to 103) when "11",
// rot_data(112 to 127) & rot_data(0 to 111) when "10",
// rot_data(120 to 127) & rot_data(0 to 119) when "01",
// rot_data(0 to 127) when others;
//
//-- 0-3,4,8,12 byte rotation
//with rot_sel(0 to 1) select
// rotC840 <= rot3210(32 to 127) & rot3210(0 to 31) when "11",
// rot3210(64 to 127) & rot3210(0 to 63) when "10",
// rot3210(96 to 127) & rot3210(0 to 95) when "01",
// rot3210(0 to 127) when others;
// ######################################################################
// ## BEFORE ROTATE CYCLE
// ######################################################################
// Rotate Control
// ----------------------------------
assign be_shx04_sel[0] = (~be_rotate_sel[0]) & (~be_rotate_sel[1]);
assign be_shx04_sel[1] = (~be_rotate_sel[0]) & be_rotate_sel[1];
assign be_shx04_sel[2] = be_rotate_sel[0] & (~be_rotate_sel[1]);
assign be_shx04_sel[3] = be_rotate_sel[0] & be_rotate_sel[1];
assign be_shx01_sel[0] = (~be_rotate_sel[2]) & (~be_rotate_sel[3]);
assign be_shx01_sel[1] = (~be_rotate_sel[2]) & be_rotate_sel[3];
assign be_shx01_sel[2] = be_rotate_sel[2] & (~be_rotate_sel[3]);
assign be_shx01_sel[3] = be_rotate_sel[2] & be_rotate_sel[3];
assign le_shx04_sel[0] = (~le_rotate_sel[0]) & (~le_rotate_sel[1]);
assign le_shx04_sel[1] = (~le_rotate_sel[0]) & le_rotate_sel[1];
assign le_shx04_sel[2] = le_rotate_sel[0] & (~le_rotate_sel[1]);
assign le_shx04_sel[3] = le_rotate_sel[0] & le_rotate_sel[1];
assign le_shx01_sel[0] = (~le_rotate_sel[2]) & (~le_rotate_sel[3]);
assign le_shx01_sel[1] = (~le_rotate_sel[2]) & le_rotate_sel[3];
assign le_shx01_sel[2] = le_rotate_sel[2] & (~le_rotate_sel[3]);
assign le_shx01_sel[3] = le_rotate_sel[2] & le_rotate_sel[3];
// Algebraic Sign Extension Control
// ----------------------------------
// come up with amount to pick the sign extend bit hw(0->30), wd(0->28) 1_1110,1_1100
assign be_shx04_sgn[0] = (~be_algebraic_sel[0]) & (~be_algebraic_sel[1]);
assign be_shx04_sgn[1] = (~be_algebraic_sel[0]) & be_algebraic_sel[1];
assign be_shx04_sgn[2] = be_algebraic_sel[0] & (~be_algebraic_sel[1]);
assign be_shx04_sgn[3] = be_algebraic_sel[0] & be_algebraic_sel[1];
assign le_shx04_sgn[0] = (~le_algebraic_sel[0]) & (~le_algebraic_sel[1]);
assign le_shx04_sgn[1] = (~le_algebraic_sel[0]) & le_algebraic_sel[1];
assign le_shx04_sgn[2] = le_algebraic_sel[0] & (~le_algebraic_sel[1]);
assign le_shx04_sgn[3] = le_algebraic_sel[0] & le_algebraic_sel[1];
assign be_shx01_sgn[0] = (~be_algebraic_sel[2]) & (~be_algebraic_sel[3]) & algebraic;
assign be_shx01_sgn[1] = (~be_algebraic_sel[2]) & be_algebraic_sel[3] & algebraic;
assign be_shx01_sgn[2] = be_algebraic_sel[2] & (~be_algebraic_sel[3]) & algebraic;
assign be_shx01_sgn[3] = be_algebraic_sel[2] & be_algebraic_sel[3] & algebraic;
assign le_shx01_sgn[0] = (~le_algebraic_sel[2]) & (~le_algebraic_sel[3]) & algebraic;
assign le_shx01_sgn[1] = (~le_algebraic_sel[2]) & le_algebraic_sel[3] & algebraic;
assign le_shx01_sgn[2] = le_algebraic_sel[2] & (~le_algebraic_sel[3]) & algebraic;
assign le_shx01_sgn[3] = le_algebraic_sel[2] & le_algebraic_sel[3] & algebraic;
// Opsize Mask Generation
// ----------------------------------
assign mask_din[0] = opsize[0]; // for 16:23
assign mask_din[1] = opsize[0] | opsize[1]; // for 24:27
assign mask_din[2] = opsize[0] | opsize[1] | opsize[2]; // for 28:29
assign mask_din[3] = opsize[0] | opsize[1] | opsize[2] | opsize[3]; // for 30
assign mask_din[4] = opsize[0] | opsize[1] | opsize[2] | opsize[3] | opsize[4]; // for 31
// Latch Inputs
// ----------------------------------
assign bele_gp0_din[0] = le;
assign be_shx04_gp0_din[0:3] = be_shx04_sel[0:3];
assign le_shx04_gp0_din[0:3] = le_shx04_sel[0:3];
assign be_shx01_gp0_din[0:3] = be_shx01_sel[0:3];
assign le_shx01_gp0_din[0:3] = le_shx01_sel[0:3];
assign be_shx04_sgn0_din[0:3] = be_shx04_sgn[0:3];
assign be_shx01_sgn0_din[0:3] = be_shx01_sgn[0:3];
assign le_shx04_sgn0_din[0:3] = le_shx04_sgn[0:3];
assign le_shx01_sgn0_din[0:3] = le_shx01_sgn[0:3];
// ######################################################################
// ## BIG-ENDIAN ROTATE CYCLE
// ######################################################################
// -------------------------------------------------------------------
// local latch inputs
// -------------------------------------------------------------------
tri_inv bele_gp0_q_0 (.y(bele_gp0_q), .a(bele_gp0_q_b));
tri_inv #(.WIDTH(4)) be_shx04_gp0_q_0 (.y(be_shx04_gp0_q[0:3]), .a(be_shx04_gp0_q_b[0:3]));
tri_inv #(.WIDTH(4)) le_shx04_gp0_q_0 (.y(le_shx04_gp0_q[0:3]), .a(le_shx04_gp0_q_b[0:3]));
tri_inv #(.WIDTH(4)) be_shx01_gp0_q_0 (.y(be_shx01_gp0_q[0:3]), .a(be_shx01_gp0_q_b[0:3]));
tri_inv #(.WIDTH(4)) le_shx01_gp0_q_0 (.y(le_shx01_gp0_q[0:3]), .a(le_shx01_gp0_q_b[0:3]));
tri_inv #(.WIDTH(4)) be_shx04_sgn0_q_0 (.y(be_shx04_sgn0_q[0:3]), .a(be_shx04_sgn0_q_b[0:3]));
tri_inv #(.WIDTH(4)) le_shx04_sgn0_q_0 (.y(le_shx04_sgn0_q[0:3]), .a(le_shx04_sgn0_q_b[0:3]));
tri_inv #(.WIDTH(4)) be_shx01_sgn0_q_0 (.y(be_shx01_sgn0_q[0:3]), .a(be_shx01_sgn0_q_b[0:3]));
tri_inv #(.WIDTH(4)) le_shx01_sgn0_q_0 (.y(le_shx01_sgn0_q[0:3]), .a(le_shx01_sgn0_q_b[0:3]));
assign mask_q[0:4] = (~mask_q_b[0:4]);
// ----------------------------------------------------------------------------------------
// Read-Modify-Write Bypass Data Muxing
// ----------------------------------------------------------------------------------------
assign stq_byp_data = ({16{stq7_byp_val}} & stq7_rmw_data) | ({16{~stq7_byp_val}} & stq8_rmw_data);
assign rotate_data = ({16{stq_byp_val}} & stq_byp_data) | ({16{~stq_byp_val}} & arr_data);
// ----------------------------------------------------------------------------------------
// Little/Big Endian Muxing
// ----------------------------------------------------------------------------------------
assign bele_s0[0:15] = {16{~bele_gp0_q[0]}};
assign bele_s1[0:15] = {16{ bele_gp0_q[0]}};
tri_aoi22 #(.WIDTH(4)) shx04_gp0_sel_b_0 (.y(shx04_gp0_sel_b[0:3]), .a0(be_shx04_gp0_q[0:3]), .a1(bele_s0[0:3]), .b0(le_shx04_gp0_q[0:3]), .b1(bele_s1[0:3]));
tri_aoi22 #(.WIDTH(4)) shx01_gp0_sel_b_0 (.y(shx01_gp0_sel_b[0:3]), .a0(be_shx01_gp0_q[0:3]), .a1(bele_s0[4:7]), .b0(le_shx01_gp0_q[0:3]), .b1(bele_s1[4:7]));
tri_aoi22 #(.WIDTH(4)) shx04_sgn0_sel_b_0 (.y(shx04_sgn0_sel_b[0:3]), .a0(be_shx04_sgn0_q[0:3]), .a1(bele_s0[8:11]), .b0(le_shx04_sgn0_q[0:3]), .b1(bele_s1[8:11]));
tri_aoi22 #(.WIDTH(4)) shx01_sgn0_sel_b_0 (.y(shx01_sgn0_sel_b[0:3]), .a0(be_shx01_sgn0_q[0:3]), .a1(bele_s0[12:15]), .b0(le_shx01_sgn0_q[0:3]), .b1(bele_s1[12:15]));
assign shx04_gp0_sel = (~shx04_gp0_sel_b);
assign shx01_gp0_sel = (~shx01_gp0_sel_b);
assign shx04_sgn0_sel = (~shx04_sgn0_sel_b);
assign shx01_sgn0_sel = (~shx01_sgn0_sel_b);
assign mxbele_d0[0] = rotate_data[0]; assign mxbele_d1[0] = rotate_data[15];
assign mxbele_d0[1] = rotate_data[1]; assign mxbele_d1[1] = rotate_data[14];
assign mxbele_d0[2] = rotate_data[2]; assign mxbele_d1[2] = rotate_data[13];
assign mxbele_d0[3] = rotate_data[3]; assign mxbele_d1[3] = rotate_data[12];
assign mxbele_d0[4] = rotate_data[4]; assign mxbele_d1[4] = rotate_data[11];
assign mxbele_d0[5] = rotate_data[5]; assign mxbele_d1[5] = rotate_data[10];
assign mxbele_d0[6] = rotate_data[6]; assign mxbele_d1[6] = rotate_data[9];
assign mxbele_d0[7] = rotate_data[7]; assign mxbele_d1[7] = rotate_data[8];
assign mxbele_d0[8] = rotate_data[8]; assign mxbele_d1[8] = rotate_data[7];
assign mxbele_d0[9] = rotate_data[9]; assign mxbele_d1[9] = rotate_data[6];
assign mxbele_d0[10] = rotate_data[10]; assign mxbele_d1[10] = rotate_data[5];
assign mxbele_d0[11] = rotate_data[11]; assign mxbele_d1[11] = rotate_data[4];
assign mxbele_d0[12] = rotate_data[12]; assign mxbele_d1[12] = rotate_data[3];
assign mxbele_d0[13] = rotate_data[13]; assign mxbele_d1[13] = rotate_data[2];
assign mxbele_d0[14] = rotate_data[14]; assign mxbele_d1[14] = rotate_data[1];
assign mxbele_d0[15] = rotate_data[15]; assign mxbele_d1[15] = rotate_data[0];
tri_aoi22 #(.WIDTH(16)) mxbele_b_0 (.y(mxbele_b[0:15]), .a0(mxbele_d0[0:15]), .a1(bele_s0[0:15]), .b0(mxbele_d1[0:15]), .b1(bele_s1[0:15]));
tri_inv #(.WIDTH(16)) mxbele_0 (.y(mxbele[0:15]), .a(mxbele_b[0:15]));
// ----------------------------------------------------------------------------------------
// First level of muxing <0,4,8,12 bytes>
// ----------------------------------------------------------------------------------------
assign mx1_s0[0:15] = {16{shx04_gp0_sel[0]}};
assign mx1_s1[0:15] = {16{shx04_gp0_sel[1]}};
assign mx1_s2[0:15] = {16{shx04_gp0_sel[2]}};
assign mx1_s3[0:15] = {16{shx04_gp0_sel[3]}};
assign mx1_d0[0] = mxbele[0]; assign mx1_d1[0] = mxbele[12]; assign mx1_d2[0] = mxbele[8]; assign mx1_d3[0] = mxbele[4];
assign mx1_d0[1] = mxbele[1]; assign mx1_d1[1] = mxbele[13]; assign mx1_d2[1] = mxbele[9]; assign mx1_d3[1] = mxbele[5];
assign mx1_d0[2] = mxbele[2]; assign mx1_d1[2] = mxbele[14]; assign mx1_d2[2] = mxbele[10]; assign mx1_d3[2] = mxbele[6];
assign mx1_d0[3] = mxbele[3]; assign mx1_d1[3] = mxbele[15]; assign mx1_d2[3] = mxbele[11]; assign mx1_d3[3] = mxbele[7];
assign mx1_d0[4] = mxbele[4]; assign mx1_d1[4] = mxbele[0]; assign mx1_d2[4] = mxbele[12]; assign mx1_d3[4] = mxbele[8];
assign mx1_d0[5] = mxbele[5]; assign mx1_d1[5] = mxbele[1]; assign mx1_d2[5] = mxbele[13]; assign mx1_d3[5] = mxbele[9];
assign mx1_d0[6] = mxbele[6]; assign mx1_d1[6] = mxbele[2]; assign mx1_d2[6] = mxbele[14]; assign mx1_d3[6] = mxbele[10];
assign mx1_d0[7] = mxbele[7]; assign mx1_d1[7] = mxbele[3]; assign mx1_d2[7] = mxbele[15]; assign mx1_d3[7] = mxbele[11];
assign mx1_d0[8] = mxbele[8]; assign mx1_d1[8] = mxbele[4]; assign mx1_d2[8] = mxbele[0]; assign mx1_d3[8] = mxbele[12];
assign mx1_d0[9] = mxbele[9]; assign mx1_d1[9] = mxbele[5]; assign mx1_d2[9] = mxbele[1]; assign mx1_d3[9] = mxbele[13];
assign mx1_d0[10] = mxbele[10]; assign mx1_d1[10] = mxbele[6]; assign mx1_d2[10] = mxbele[2]; assign mx1_d3[10] = mxbele[14];
assign mx1_d0[11] = mxbele[11]; assign mx1_d1[11] = mxbele[7]; assign mx1_d2[11] = mxbele[3]; assign mx1_d3[11] = mxbele[15];
assign mx1_d0[12] = mxbele[12]; assign mx1_d1[12] = mxbele[8]; assign mx1_d2[12] = mxbele[4]; assign mx1_d3[12] = mxbele[0];
assign mx1_d0[13] = mxbele[13]; assign mx1_d1[13] = mxbele[9]; assign mx1_d2[13] = mxbele[5]; assign mx1_d3[13] = mxbele[1];
assign mx1_d0[14] = mxbele[14]; assign mx1_d1[14] = mxbele[10]; assign mx1_d2[14] = mxbele[6]; assign mx1_d3[14] = mxbele[2];
assign mx1_d0[15] = mxbele[15]; assign mx1_d1[15] = mxbele[11]; assign mx1_d2[15] = mxbele[7]; assign mx1_d3[15] = mxbele[3];
tri_aoi22 #(.WIDTH(16)) mx1_0_b_0 (.y(mx1_0_b[0:15]), .a0(mx1_s0[0:15]), .a1(mx1_d0[0:15]), .b0(mx1_s1[0:15]), .b1(mx1_d1[0:15]));
tri_aoi22 #(.WIDTH(16)) mx1_1_b_0 (.y(mx1_1_b[0:15]), .a0(mx1_s2[0:15]), .a1(mx1_d2[0:15]), .b0(mx1_s3[0:15]), .b1(mx1_d3[0:15]));
tri_nand2 #(.WIDTH(16)) mx1_0 (.y(mx1[0:15]), .a(mx1_0_b[0:15]), .b(mx1_1_b[0:15]));
assign sx1_s0[0:7] = {8{shx04_sgn0_sel[0]}};
assign sx1_s1[0:7] = {8{shx04_sgn0_sel[1]}};
assign sx1_s2[0:7] = {8{shx04_sgn0_sel[2]}};
assign sx1_s3[0:7] = {8{shx04_sgn0_sel[3]}};
assign sx1_d0[0] = rotate_data[0]; assign sx1_d1[0] = rotate_data[4]; assign sx1_d2[0] = rotate_data[8]; assign sx1_d3[0] = rotate_data[12];
assign sx1_d0[1] = rotate_data[1]; assign sx1_d1[1] = rotate_data[5]; assign sx1_d2[1] = rotate_data[9]; assign sx1_d3[1] = rotate_data[13];
assign sx1_d0[2] = rotate_data[2]; assign sx1_d1[2] = rotate_data[6]; assign sx1_d2[2] = rotate_data[10]; assign sx1_d3[2] = rotate_data[14];
assign sx1_d0[3] = rotate_data[3]; assign sx1_d1[3] = rotate_data[7]; assign sx1_d2[3] = rotate_data[11]; assign sx1_d3[3] = rotate_data[15];
assign sx1_d0[4] = rotate_data[0]; assign sx1_d1[4] = rotate_data[4]; assign sx1_d2[4] = rotate_data[8]; assign sx1_d3[4] = rotate_data[12];
assign sx1_d0[5] = rotate_data[1]; assign sx1_d1[5] = rotate_data[5]; assign sx1_d2[5] = rotate_data[9]; assign sx1_d3[5] = rotate_data[13];
assign sx1_d0[6] = rotate_data[2]; assign sx1_d1[6] = rotate_data[6]; assign sx1_d2[6] = rotate_data[10]; assign sx1_d3[6] = rotate_data[14];
assign sx1_d0[7] = rotate_data[3]; assign sx1_d1[7] = rotate_data[7]; assign sx1_d2[7] = rotate_data[11]; assign sx1_d3[7] = rotate_data[15];
tri_aoi22 #(.WIDTH(8)) sx1_0_b_0 (.y(sx1_0_b[0:7]), .a0(sx1_s0[0:7]), .a1(sx1_d0[0:7]), .b0(sx1_s1[0:7]), .b1(sx1_d1[0:7]));
tri_aoi22 #(.WIDTH(8)) sx1_1_b_0 (.y(sx1_1_b[0:7]), .a0(sx1_s2[0:7]), .a1(sx1_d2[0:7]), .b0(sx1_s3[0:7]), .b1(sx1_d3[0:7]));
tri_nand2 #(.WIDTH(8)) sx1_0 (.y(sx1[0:7]), .a(sx1_0_b[0:7]), .b(sx1_1_b[0:7]));
// ----------------------------------------------------------------------------------------
// third level of muxing <0,1,2,3 bytes> , include mask on selects
// ----------------------------------------------------------------------------------------
assign mask_en[0:7] = {8{mask_q[0]}}; // 128
assign mask_en[8:11] = {4{mask_q[1]}}; // 128,64
assign mask_en[12:13] = {2{mask_q[2]}}; // 128,64,32
assign mask_en[14] = mask_q[3]; // 128,64,32,16
assign mask_en[15] = mask_q[4]; // 128,64,32,16,8 <not sure you really need this one>
assign mx2_s0[0:7] = {8{shx01_gp0_sel[0]}} & mask_en[0:7];
assign mx2_s1[0:7] = {8{shx01_gp0_sel[1]}} & mask_en[0:7];
assign mx2_s2[0:7] = {8{shx01_gp0_sel[2]}} & mask_en[0:7];
assign mx2_s3[0:7] = {8{shx01_gp0_sel[3]}} & mask_en[0:7];
assign mx2_s0[8:15] = {8{shx01_gp0_sel[0]}} & mask_en[8:15];
assign mx2_s1[8:15] = {8{shx01_gp0_sel[1]}} & mask_en[8:15];
assign mx2_s2[8:15] = {8{shx01_gp0_sel[2]}} & mask_en[8:15];
assign mx2_s3[8:15] = {8{shx01_gp0_sel[3]}} & mask_en[8:15];
assign mx2_d0[0] = mx1[0]; assign mx2_d1[0] = mx1[15]; assign mx2_d2[0] = mx1[14]; assign mx2_d3[0] = mx1[13];
assign mx2_d0[1] = mx1[1]; assign mx2_d1[1] = mx1[0]; assign mx2_d2[1] = mx1[15]; assign mx2_d3[1] = mx1[14];
assign mx2_d0[2] = mx1[2]; assign mx2_d1[2] = mx1[1]; assign mx2_d2[2] = mx1[0]; assign mx2_d3[2] = mx1[15];
assign mx2_d0[3] = mx1[3]; assign mx2_d1[3] = mx1[2]; assign mx2_d2[3] = mx1[1]; assign mx2_d3[3] = mx1[0];
assign mx2_d0[4] = mx1[4]; assign mx2_d1[4] = mx1[3]; assign mx2_d2[4] = mx1[2]; assign mx2_d3[4] = mx1[1];
assign mx2_d0[5] = mx1[5]; assign mx2_d1[5] = mx1[4]; assign mx2_d2[5] = mx1[3]; assign mx2_d3[5] = mx1[2];
assign mx2_d0[6] = mx1[6]; assign mx2_d1[6] = mx1[5]; assign mx2_d2[6] = mx1[4]; assign mx2_d3[6] = mx1[3];
assign mx2_d0[7] = mx1[7]; assign mx2_d1[7] = mx1[6]; assign mx2_d2[7] = mx1[5]; assign mx2_d3[7] = mx1[4];
assign mx2_d0[8] = mx1[8]; assign mx2_d1[8] = mx1[7]; assign mx2_d2[8] = mx1[6]; assign mx2_d3[8] = mx1[5];
assign mx2_d0[9] = mx1[9]; assign mx2_d1[9] = mx1[8]; assign mx2_d2[9] = mx1[7]; assign mx2_d3[9] = mx1[6];
assign mx2_d0[10] = mx1[10]; assign mx2_d1[10] = mx1[9]; assign mx2_d2[10] = mx1[8]; assign mx2_d3[10] = mx1[7];
assign mx2_d0[11] = mx1[11]; assign mx2_d1[11] = mx1[10]; assign mx2_d2[11] = mx1[9]; assign mx2_d3[11] = mx1[8];
assign mx2_d0[12] = mx1[12]; assign mx2_d1[12] = mx1[11]; assign mx2_d2[12] = mx1[10]; assign mx2_d3[12] = mx1[9];
assign mx2_d0[13] = mx1[13]; assign mx2_d1[13] = mx1[12]; assign mx2_d2[13] = mx1[11]; assign mx2_d3[13] = mx1[10];
assign mx2_d0[14] = mx1[14]; assign mx2_d1[14] = mx1[13]; assign mx2_d2[14] = mx1[12]; assign mx2_d3[14] = mx1[11];
assign mx2_d0[15] = mx1[15]; assign mx2_d1[15] = mx1[14]; assign mx2_d2[15] = mx1[13]; assign mx2_d3[15] = mx1[12];
tri_aoi22 #(.WIDTH(16)) mx2_0_b_0 (.y(mx2_0_b[0:15]), .a0(mx2_s0[0:15]), .a1(mx2_d0[0:15]), .b0(mx2_s1[0:15]), .b1(mx2_d1[0:15]));
tri_aoi22 #(.WIDTH(16)) mx2_1_b_0 (.y(mx2_1_b[0:15]), .a0(mx2_s2[0:15]), .a1(mx2_d2[0:15]), .b0(mx2_s3[0:15]), .b1(mx2_d3[0:15]));
tri_nand2 #(.WIDTH(16)) mx2_0 (.y(mx2[0:15]), .a(mx2_0_b[0:15]), .b(mx2_1_b[0:15]));
tri_inv #(.WIDTH(16)) do_b_0 (.y(do_b[0:15]), .a(mx2[0:15]));
tri_inv #(.WIDTH(16)) data_rot_0 (.y(data_rot[0:15]), .a(do_b[0:15]));
tri_inv #(.WIDTH(16)) data_latched_b_0 (.y(data_latched_b), .a(arr_data));
tri_inv #(.WIDTH(16)) data_latched_0 (.y(data_latched), .a(data_latched_b));
assign sx2_s0[0:3] = {4{shx01_sgn0_sel[0]}};
assign sx2_s1[0:3] = {4{shx01_sgn0_sel[1]}};
assign sx2_s2[0:3] = {4{shx01_sgn0_sel[2]}};
assign sx2_s3[0:3] = {4{shx01_sgn0_sel[3]}};
assign sx2_s0[4:5] = {2{shx01_sgn0_sel[0] & (~mask_q[2])}};
assign sx2_s1[4:5] = {2{shx01_sgn0_sel[1] & (~mask_q[2])}};
assign sx2_s2[4:5] = {2{shx01_sgn0_sel[2] & (~mask_q[2])}};
assign sx2_s3[4:5] = {2{shx01_sgn0_sel[3] & (~mask_q[2])}};
// 6 logically identical copies (1 per byte needing extension)
assign sx2_d0[0] = sx1[0]; assign sx2_d1[0] = sx1[1]; assign sx2_d2[0] = sx1[2]; assign sx2_d3[0] = sx1[3];
assign sx2_d0[1] = sx1[0]; assign sx2_d1[1] = sx1[1]; assign sx2_d2[1] = sx1[2]; assign sx2_d3[1] = sx1[3];
assign sx2_d0[2] = sx1[0]; assign sx2_d1[2] = sx1[1]; assign sx2_d2[2] = sx1[2]; assign sx2_d3[2] = sx1[3];
assign sx2_d0[3] = sx1[4]; assign sx2_d1[3] = sx1[5]; assign sx2_d2[3] = sx1[6]; assign sx2_d3[3] = sx1[7];
assign sx2_d0[4] = sx1[4]; assign sx2_d1[4] = sx1[5]; assign sx2_d2[4] = sx1[6]; assign sx2_d3[4] = sx1[7];
assign sx2_d0[5] = sx1[4]; assign sx2_d1[5] = sx1[5]; assign sx2_d2[5] = sx1[6]; assign sx2_d3[5] = sx1[7];
tri_aoi22 #(.WIDTH(6)) sx2_0_b_0 (.y(sx2_0_b[0:5]), .a0(sx2_s0[0:5]), .a1(sx2_d0[0:5]), .b0(sx2_s1[0:5]), .b1(sx2_d1[0:5]));
tri_aoi22 #(.WIDTH(6)) sx2_1_b_0 (.y(sx2_1_b[0:5]), .a0(sx2_s2[0:5]), .a1(sx2_d2[0:5]), .b0(sx2_s3[0:5]), .b1(sx2_d3[0:5]));
tri_nand2 #(.WIDTH(6)) sx2_0 (.y(sx2[0:5]), .a(sx2_0_b[0:5]), .b(sx2_1_b[0:5]));
tri_inv #(.WIDTH(6)) sign_copy_b_0 (.y(sign_copy_b[0:5]), .a(sx2[0:5]));
tri_inv #(.WIDTH(6)) algebraic_bit_0 (.y(algebraic_bit[0:5]), .a(sign_copy_b[0:5]));
// top funny physical placement to minimize wrap wires ... also nice for LE adjust
//---------
// 0 31
// 1 30
// 2 29
// 3 28
// 4 27
// 5 26
// 6 25
// 7 24
//---------
// 8 23
// 9 22
// 10 21
// 11 20
// 12 19
// 13 18
// 14 17
// 15 16
//---------
// bot
// ###############################################################
// ## LCBs
// ###############################################################
tri_lcbnd my_lcb(
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.force_t(func_sl_force),
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(act),
.sg(sg_0),
.thold_b(func_sl_thold_0_b),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.lclk(my_lclk)
);
// ###############################################################
// ## Latches
// ###############################################################
tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) bele_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]),
.scanout(sov[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]),
.d(bele_gp0_din),
.qb(bele_gp0_q_b)
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]),
.scanout(sov[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]),
.d(be_shx04_gp0_din),
.qb(be_shx04_gp0_q_b[0:3])
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]),
.scanout(sov[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]),
.d(le_shx04_gp0_din),
.qb(le_shx04_gp0_q_b[0:3])
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]),
.scanout(sov[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]),
.d(be_shx01_gp0_din),
.qb(be_shx01_gp0_q_b[0:3])
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]),
.scanout(sov[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]),
.d(le_shx01_gp0_din),
.qb(le_shx01_gp0_q_b[0:3])
);
tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) mask_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[mask_din_offset:mask_din_offset + 5 - 1]),
.scanout(sov[mask_din_offset:mask_din_offset + 5 - 1]),
.d(mask_din),
.qb(mask_q_b[0:4])
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx04_sgn0_din_offset:be_shx04_sgn0_din_offset + 4 - 1]),
.scanout(sov[be_shx04_sgn0_din_offset:be_shx04_sgn0_din_offset + 4 - 1]),
.d(be_shx04_sgn0_din),
.qb(be_shx04_sgn0_q_b)
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx01_sgn0_din_offset:be_shx01_sgn0_din_offset + 4 - 1]),
.scanout(sov[be_shx01_sgn0_din_offset:be_shx01_sgn0_din_offset + 4 - 1]),
.d(be_shx01_sgn0_din),
.qb(be_shx01_sgn0_q_b)
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx04_sgn0_din_offset:le_shx04_sgn0_din_offset + 4 - 1]),
.scanout(sov[le_shx04_sgn0_din_offset:le_shx04_sgn0_din_offset + 4 - 1]),
.d(le_shx04_sgn0_din),
.qb(le_shx04_sgn0_q_b)
);
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx01_sgn0_din_offset:le_shx01_sgn0_din_offset + 4 - 1]),
.scanout(sov[le_shx01_sgn0_din_offset:le_shx01_sgn0_din_offset + 4 - 1]),
.d(le_shx01_sgn0_din),
.qb(le_shx01_sgn0_q_b)
);
assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
assign scan_out = sov[0];
endmodule |
module tri_fu_mul_bthdcd(
i0,
i1,
i2,
s_neg,
s_x,
s_x2
);
input i0;
input i1;
input i2;
output s_neg;
output s_x;
output s_x2;
// ATTRIBUTE btr_name OF tri_fu_mul_bthdcd : ENTITY IS "tri_fu_mul_bthdcd";
wire s_add;
wire sx1_a0_b;
wire sx1_a1_b;
wire sx1_t;
wire sx1_i;
wire sx2_a0_b;
wire sx2_a1_b;
wire sx2_t;
wire sx2_i;
wire i0_b;
wire i1_b;
wire i2_b;
// i0:2 booth recode table
//--------------------------------
// 000 add sh1=0 sh2=0 sub_adj=0
// 001 add sh1=1 sh2=0 sub_adj=0
// 010 add sh1=1 sh2=0 sub_adj=0
// 011 add sh1=0 sh2=1 sub_adj=0
// 100 sub sh1=0 sh2=1 sub_adj=1
// 101 sub sh1=1 sh2=0 sub_adj=1
// 110 sub sh1=1 sh2=0 sub_adj=1
// 111 sub sh1=0 sh2=0 sub_adj=0
// logically correct
//----------------------------------
// s_neg <= (i0);
// s_x <= ( not i1 and i2) or ( i1 and not i2);
// s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2);
assign i0_b = (~(i0));
assign i1_b = (~(i1));
assign i2_b = (~(i2));
assign s_add = (~(i0));
assign s_neg = (~(s_add));
assign sx1_a0_b = (~(i1_b & i2));
assign sx1_a1_b = (~(i1 & i2_b));
assign sx1_t = (~(sx1_a0_b & sx1_a1_b));
assign sx1_i = (~(sx1_t));
assign s_x = (~(sx1_i));
assign sx2_a0_b = (~(i0 & i1_b & i2_b));
assign sx2_a1_b = (~(i0_b & i1 & i2));
assign sx2_t = (~(sx2_a0_b & sx2_a1_b));
assign sx2_i = (~(sx2_t));
assign s_x2 = (~(sx2_i));
endmodule |
module tri_serial_scom2(
nclk,
vdd,
gnd,
scom_func_thold,
sg,
act_dis_dc,
clkoff_dc_b,
mpw1_dc_b,
mpw2_dc_b,
d_mode_dc,
delay_lclkr_dc,
func_scan_in,
func_scan_out,
dcfg_scan_dclk,
dcfg_scan_lclk,
dcfg_d1clk,
dcfg_d2clk,
dcfg_lclk,
dcfg_scan_in,
dcfg_scan_out,
scom_local_act,
sat_id,
scom_dch_in,
scom_cch_in,
scom_dch_out,
scom_cch_out,
sc_req,
sc_ack,
sc_ack_info,
sc_r_nw,
sc_addr,
addr_v,
sc_rdata,
sc_wdata,
sc_wparity,
scom_err,
fsm_reset
);
//=====================================================================
// I/O Definition
//=====================================================================
parameter WIDTH = 64; // 64 is the maximum allowed
parameter INTERNAL_ADDR_DECODE = 1'b0;
// Made these parameters local (they don't play nice with vhdl wrapper)
//parameter [0:WIDTH-1] USE_ADDR = 64'b1000000000000000000000000000000000000000000000000000000000000000;
//parameter [0:WIDTH-1] ADDR_IS_RDABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000;
//parameter [0:WIDTH-1] ADDR_IS_WRABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000;
//parameter [0:WIDTH-1] PIPELINE_ADDR_V = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter PIPELINE_PARITYCHK = 1'b0; // pipeline parcheck for timing
parameter SATID_NOBITS = 4; // should not be set by user
parameter REGID_NOBITS = 6;
parameter RINGID_NOBITS = 3;
// clock, scan and misc interfaces
input [0:`NCLK_WIDTH-1] nclk;
inout vdd;
inout gnd;
input scom_func_thold;
input sg;
input act_dis_dc;
input clkoff_dc_b;
input mpw1_dc_b;
input mpw2_dc_b;
input d_mode_dc;
input delay_lclkr_dc;
//lcb_align_0 : in std_ulogic;
//! scan chain should evaluate to 0:176 for WIDTH=64 and 6 REGID_NOBITS (=64 SCOM addresses)
//! scan chain vector is longer than number of latches being used due to
//! vhdl generics formulation and shortings
input [0:WIDTH+2*((WIDTH-1)/16+1)+(2**REGID_NOBITS)+40] func_scan_in;
output [0:WIDTH+2*((WIDTH-1)/16+1)+(2**REGID_NOBITS)+40] func_scan_out;
// for mask slat inside of c_err_rpt
input dcfg_scan_dclk;
input [0:`NCLK_WIDTH-1] dcfg_scan_lclk;
//! for nlats inside of c_err_rpt
input dcfg_d1clk; // needed for one bit only, always or scom_local_act clocked dcfg
input dcfg_d2clk; // needed for one bit only, always or scom_local_act clocked dcfg
input [0:`NCLK_WIDTH-1] dcfg_lclk; // needed for one bit only, always or scom_local_act clocked dcfg
// contains mask slat and hold nlat of c_err_rpt
input [0:1] dcfg_scan_in;
output [0:1] dcfg_scan_out;
// denotes SCOM sat active if set to '1', can be used for local clock gating
output scom_local_act;
//---------------------------------------------------------------------
// SCOM Interface
//---------------------------------------------------------------------
// SCOM satellite ID tied to a specific pattern
input [0:SATID_NOBITS-1] sat_id;
// SCOM Data Channel input (carry both address and data)
input scom_dch_in;
// SCOM Control Channel input
input scom_cch_in;
// SCOM Data Channel output
output scom_dch_out;
// SCOM Control Channel output
output scom_cch_out;
//---------------------------------------------------------------------
// Interface between SCOM satellite and internal macro logic
//---------------------------------------------------------------------
// denotes a request if asserted to '1', level
output sc_req;
// acknowledge a pending request with sc_ack_info+sc_rdata+sc_rparity
// being valid
input sc_ack;
// acknowledge information
// 0: '1' if access violation, otherwise '0'
// 1: '1' if register address invalid
input [0:1] sc_ack_info;
// '1' if read access, '0' write access
output sc_r_nw;
// Register address, default 6 bits for up to 64 register addresses
output [0:REGID_NOBITS-1] sc_addr;
// one-hot address, valid only if INTERNAL_ADDR_DECODE=TRUE, else zeros
output [0:WIDTH-1] addr_v;
// Read data delivered by macro logic as response to a read request
input [0:WIDTH-1] sc_rdata;
// Write data delivered from SCOM satellite for a write request
output [0:WIDTH-1] sc_wdata;
// Write data parity bit over sc_wdata, optional usage
output sc_wparity;
//---------------------------------------------------------------------
// parity error of fsm state vector, wire to next local fir
output scom_err;
// reset fsm (optional), tie to '0' if unused
input fsm_reset;
//=====================================================================
// Signal Declarations
//=====================================================================
parameter [0:WIDTH-1] USE_ADDR = 64'b1000000000000000000000000000000000000000000000000000000000000000;
parameter [0:WIDTH-1] ADDR_IS_RDABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000;
parameter [0:WIDTH-1] ADDR_IS_WRABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000;
parameter [0:WIDTH-1] PIPELINE_ADDR_V = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter STATE_WIDTH = 5;
parameter PAR_NOBITS = (WIDTH - 1)/16 + 1;
parameter REG_NOBITS = REGID_NOBITS;
parameter SATID_REGID_NOBITS = SATID_NOBITS + REGID_NOBITS;
parameter RW_BIT_INDEX = SATID_REGID_NOBITS + 1;
parameter PARBIT_INDEX = RW_BIT_INDEX + 1;
parameter HEAD_WIDTH = PARBIT_INDEX + 1;
parameter [0:HEAD_WIDTH-1] HEAD_INIT = 13'b0000000000000;
// 0123Parity
parameter [0:STATE_WIDTH-1] IDLE = 5'b00000; // 0 = x00
parameter [0:STATE_WIDTH-1] REC_HEAD = 5'b00011; // 1 = x03
parameter [0:STATE_WIDTH-1] CHECK_BEFORE= 5'b00101; // 2 = x05
parameter [0:STATE_WIDTH-1] REC_WDATA = 5'b00110; // 3 = x06
parameter [0:STATE_WIDTH-1] REC_WPAR = 5'b01001; // 4 = x09
parameter [0:STATE_WIDTH-1] EXE_CMD = 5'b01010; // 5 = x0A
parameter [0:STATE_WIDTH-1] FILLER0 = 5'b01100; // 6 = x0C
parameter [0:STATE_WIDTH-1] FILLER1 = 5'b01111; // 7 = x0F
parameter [0:STATE_WIDTH-1] GEN_ULINFO = 5'b10001; // 8 = x11
parameter [0:STATE_WIDTH-1] SEND_ULINFO = 5'b10010; // 9 = x12
parameter [0:STATE_WIDTH-1] SEND_RDATA = 5'b10100; // 10 = x14
parameter [0:STATE_WIDTH-1] SEND_0 = 5'b10111; // 11 = x17
parameter [0:STATE_WIDTH-1] SEND_1 = 5'b11000; // 12 = x18
parameter [0:STATE_WIDTH-1] CHECK_WPAR = 5'b11011; // 13 = x1B
// 14 = x1D
parameter [0:STATE_WIDTH-1] NOT_SELECTED= 5'b11110; // 15 = x1E
parameter EOF_WDATA = PARBIT_INDEX - 1 + 64; // here max width, it is 64
parameter EOF_WPAR = EOF_WDATA + 4;
parameter EOF_WDATA_N = PARBIT_INDEX - 1 + WIDTH;
parameter EOF_WPAR_M = EOF_WDATA + PAR_NOBITS;
parameter CNT_SIZE = 7;
wire is_idle;
wire is_rec_head;
wire is_check_before;
wire is_rec_wdata;
wire is_rec_wpar;
wire is_exe_cmd;
wire is_gen_ulinfo;
wire is_send_ulinfo;
wire is_send_rdata;
wire is_send_0;
wire is_send_1;
wire is_filler_0;
wire is_filler_1;
reg [0:STATE_WIDTH-1] next_state;
wire [0:STATE_WIDTH-1] state_in;
wire [0:STATE_WIDTH-1] state_lt;
wire dch_lt;
wire [0:1] cch_in;
wire [0:1] cch_lt;
wire reset;
wire got_head;
wire gor_eofwdata;
wire got_eofwpar;
wire sent_rdata;
wire got_ulhead;
wire do_send_par;
wire cntgtheadpluswidth;
wire cntgteofwdataplusparity;
wire p0_err;
wire any_ack_error;
wire match;
wire do_write;
wire do_read;
wire [0:CNT_SIZE-1] cnt_in;
wire [0:CNT_SIZE-1] cnt_lt;
wire [0:HEAD_WIDTH-1] head_in;
wire [0:HEAD_WIDTH-1] head_lt;
wire [0:4] tail_in;
wire [0:4] tail_lt;
wire [0:1] sc_ack_info_in;
wire [0:1] sc_ack_info_lt;
wire head_mux;
wire [0:WIDTH-1] data_shifter_in;
wire [0:WIDTH-1] data_shifter_lt;
wire [0:63] data_shifter_lt_tmp;
wire [0:PAR_NOBITS-1] datapar_shifter_in;
wire [0:PAR_NOBITS-1] datapar_shifter_lt;
wire data_mux;
wire par_mux;
wire dch_out_internal_in;
wire dch_out_internal_lt;
wire parity_satid_regaddr;
wire func_force;
wire func_thold_b;
wire d1clk;
wire d2clk;
wire [0:`NCLK_WIDTH-1] lclk;
wire local_act;
wire local_act_int;
wire scom_err_in;
wire scom_err_lt;
wire scom_local_act_in;
wire scom_local_act_lt;
wire wpar_err;
wire [0:PAR_NOBITS-1] par_data_in;
wire [0:PAR_NOBITS-1] par_data_lt;
wire [0:PAR_NOBITS-1] sc_rparity;
wire read_valid;
wire write_valid;
wire [0:WIDTH-1] dec_addr_in;
wire [0:WIDTH-1] dec_addr_q;
wire addr_nvld;
wire write_nvld;
wire read_nvld;
wire state_par_error;
wire [0:SATID_NOBITS-1] sat_id_net;
wire spare_latch1_in;
wire spare_latch1_lt;
wire spare_latch2_in;
wire spare_latch2_lt;
// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
wire [0:1] unused;
(* analysis_not_referenced="true" *)
wire unused_signals;
tri_lcbor lcbor_func(
.clkoff_b(clkoff_dc_b),
.thold(scom_func_thold),
.sg(sg),
.act_dis(act_dis_dc),
.force_t(func_force),
.thold_b(func_thold_b)
);
tri_lcbnd lcb_func(
.vd(vdd),
.gd(gnd),
.act(local_act_int),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.nclk(nclk),
.force_t(func_force),
.sg(sg),
.thold_b(func_thold_b),
//--------------------------
.d1clk(d1clk),
.d2clk(d2clk),
.lclk(lclk)
);
//-----------------------------------------------------------------------------
tri_err_rpt #(.WIDTH(1), // use to bundle error reporting checkers of the same exact type
.INLINE(1'b0), // make hold latch be inline
.MASK_RESET_VALUE(1'b0), // do not report address and data parity errors by default
.NEEDS_SRESET(1) // since already reported to PCB through error reply
) parity_err(
.vd(vdd),
.gd(gnd),
.err_d1clk(dcfg_d1clk),
.err_d2clk(dcfg_d2clk),
.err_lclk(dcfg_lclk),
.err_scan_in(dcfg_scan_in[0:0]),
.err_scan_out(dcfg_scan_out[0:0]),
.mode_dclk(dcfg_scan_dclk),
.mode_lclk(dcfg_scan_lclk),
.mode_scan_in(dcfg_scan_in[1:1]),
.mode_scan_out(dcfg_scan_out[1:1]),
//--------------------------
.err_in(state_par_error),
.err_out(scom_err_in)
);
assign scom_err = scom_err_lt; // drive this output with a latch / 1.35
//-----------------------------------------------------------------------------
// fill spares of scan vector
assign func_scan_out[STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22+(2**REGID_NOBITS):WIDTH+(2*((WIDTH-1)/16+1))+(2**REGID_NOBITS)+40] =
func_scan_in[ STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22+(2**REGID_NOBITS):WIDTH+(2*((WIDTH-1)/16+1))+(2**REGID_NOBITS)+40];
//-----------------------------------------------------------------------------
assign sat_id_net = sat_id;
assign cch_in = {scom_cch_in, cch_lt[0]};
assign reset = (cch_lt[0] & (~scom_cch_in)) | // with falling edge of scom_cch_in
fsm_reset | // or with fsm_reset
scom_err_lt; // MP timing fix -- or state_par_error;
assign local_act = (|{scom_cch_in, cch_lt}); // active with scom_cch_in and as long as cch_lt
assign local_act_int = local_act | scom_local_act_lt; // MP... and scom_local_act_lt is cleared
assign scom_local_act_in = local_act; // drive this output with a latch / 1.35
assign scom_local_act = scom_local_act_lt;
assign scom_cch_out = cch_lt[0];
assign dch_out_internal_in = (is_send_ulinfo == 1'b1) ? head_lt[0] :
(is_send_0 == 1'b1) ? 1'b0 :
(is_send_1 == 1'b1) ? 1'b1 :
((is_send_rdata & (~do_send_par)) == 1'b1) ? data_shifter_lt[0] :
((is_send_rdata & do_send_par) == 1'b1) ? datapar_shifter_lt[0] :
dch_lt;
assign scom_dch_out = dch_out_internal_lt;
assign sc_req = is_exe_cmd;
assign sc_addr = head_lt[SATID_NOBITS + 1:SATID_REGID_NOBITS];
assign sc_r_nw = head_lt[RW_BIT_INDEX];
assign sc_wdata = data_shifter_lt;
assign sc_wparity = (^datapar_shifter_lt);
//-----------------------------------------------------------------------------
// FSM: serial => parallel => serial state machine
//
always @(state_lt or got_head or gor_eofwdata or got_eofwpar or got_ulhead or sent_rdata or
p0_err or any_ack_error or match or do_write or do_read or cch_lt[0] or dch_lt or
sc_ack or wpar_err or read_nvld)
begin: fsm_transition
next_state <= state_lt;
case (state_lt)
IDLE :
if (dch_lt == 1'b1)
next_state <= REC_HEAD;
REC_HEAD :
if ((got_head) == 1'b1)
next_state <= CHECK_BEFORE;
CHECK_BEFORE :
if (match == 1'b0)
next_state <= NOT_SELECTED;
else if (((read_nvld | p0_err) & do_read) == 1'b1)
next_state <= FILLER0;
else if (((~p0_err) & (~read_nvld) & do_read) == 1'b1)
next_state <= EXE_CMD;
else
next_state <= REC_WDATA;
REC_WDATA :
if (gor_eofwdata == 1'b1)
next_state <= REC_WPAR;
REC_WPAR :
if ((got_eofwpar & (~p0_err)) == 1'b1)
// next_state <= EXE_CMD;
next_state <= CHECK_WPAR;
else if ((got_eofwpar & p0_err) == 1'b1)
next_state <= FILLER0;
CHECK_WPAR :
if (wpar_err == 1'b0)
next_state <= EXE_CMD;
else
next_state <= FILLER1;
EXE_CMD :
if (sc_ack == 1'b1)
next_state <= FILLER1;
FILLER0 :
next_state <= FILLER1;
FILLER1 :
next_state <= GEN_ULINFO;
GEN_ULINFO :
next_state <= SEND_ULINFO;
SEND_ULINFO :
if ((got_ulhead & (do_write | (do_read & any_ack_error))) == 1'b1)
next_state <= SEND_0;
else if ((got_ulhead & do_read & (~any_ack_error)) == 1'b1)
next_state <= SEND_RDATA;
SEND_RDATA :
if (sent_rdata == 1'b1)
next_state <= SEND_0;
SEND_0 :
next_state <= SEND_1;
SEND_1 :
next_state <= IDLE;
NOT_SELECTED :
if (cch_lt[0] == 1'b0)
next_state <= IDLE;
default :
next_state <= IDLE;
endcase
end
assign state_in = (local_act == 1'b0) ? state_lt :
(reset == 1'b1) ? IDLE :
next_state;
assign state_par_error = (^state_lt);
//-----------------------------------------------------------------------------
assign is_idle = (state_lt == IDLE);
assign is_rec_head = (state_lt == REC_HEAD);
assign is_check_before = (state_lt == CHECK_BEFORE);
assign is_rec_wdata = (state_lt == REC_WDATA);
assign is_rec_wpar = (state_lt == REC_WPAR);
assign is_exe_cmd = (state_lt == EXE_CMD);
assign is_gen_ulinfo = (state_lt == GEN_ULINFO);
assign is_send_ulinfo = (state_lt == SEND_ULINFO);
assign is_send_rdata = (state_lt == SEND_RDATA);
assign is_send_0 = (state_lt == SEND_0);
assign is_send_1 = (state_lt == SEND_1);
assign is_filler_0 = (state_lt == FILLER0);
assign is_filler_1 = (state_lt == FILLER1);
//-----------------------------------------------------------------------------
assign cnt_in = ((is_idle | is_gen_ulinfo) == 1'b1) ? 7'b0000000 :
((is_rec_head | is_check_before | is_rec_wdata |
is_rec_wpar | is_send_ulinfo | is_send_rdata |
is_send_0 | is_send_1) == 1'b1) ? cnt_lt + 7'b0000001 :
cnt_lt;
// downlink head (command) has been received when start bit, satellite id and register id have been received
assign got_head = ({{32-CNT_SIZE{1'b0}},cnt_lt} == (1 + SATID_NOBITS + REGID_NOBITS));
// uplink head (response) has been received when start bit, satellite id, register id and 4 ack bits have been received
assign got_ulhead = ({{32-CNT_SIZE{1'b0}},cnt_lt} == (1 + SATID_NOBITS + REGID_NOBITS + 4));
assign gor_eofwdata = ({{32-CNT_SIZE{1'b0}},cnt_lt} == EOF_WDATA);
assign got_eofwpar = ({{32-CNT_SIZE{1'b0}},cnt_lt} == EOF_WPAR);
// for sent_rdata: 1 start, 10 sat_id + reg, 4 ack, 1 p, 64 data = 84, but count from 0 is 1st bit => 83 is end
assign sent_rdata = (cnt_lt == 7'd83);
assign cntgtheadpluswidth = ({{32-CNT_SIZE{1'b0}},cnt_lt} > EOF_WDATA_N);
assign cntgteofwdataplusparity = ({{32-CNT_SIZE{1'b0}},cnt_lt} > EOF_WPAR_M);
assign do_send_par = ({{32-CNT_SIZE{1'b0}},cnt_lt} > 79); // 78 bits=15 ulhead + 64 data
//-----------------------------------------------------------------------------
// shift downlink command (for this or any subsequent satellite) or uplink response (from previous satellite)
assign head_in[HEAD_WIDTH-2:HEAD_WIDTH-1] = ((is_rec_head | (is_idle & dch_lt)) == 1'b1) ? {head_lt[HEAD_WIDTH-1], dch_lt} :
head_lt[HEAD_WIDTH-2:HEAD_WIDTH-1];
assign head_in[0:SATID_REGID_NOBITS] = ((is_rec_head | is_send_ulinfo) == 1'b1) ? {head_lt[1:SATID_REGID_NOBITS], head_mux} :
head_lt[0:SATID_REGID_NOBITS];
assign head_mux = (is_rec_head == 1'b1) ? head_lt[RW_BIT_INDEX] :
tail_lt[0];
// calculate parity P0 of uplink frame
assign tail_in[4] = (is_gen_ulinfo == 1'b1 & (INTERNAL_ADDR_DECODE == 1'b0)) ? (^({parity_satid_regaddr, tail_lt[0], (wpar_err & do_write), sc_ack_info_lt[0:1]})) :
(is_gen_ulinfo == 1'b1 & (INTERNAL_ADDR_DECODE == 1'b1)) ? (^({parity_satid_regaddr, tail_lt[0], (wpar_err & do_write), (write_nvld | read_nvld), addr_nvld})) :
tail_lt[4];
// copy sampled ack_info coming from logic
assign tail_in[2:3] = (is_gen_ulinfo == 1'b1 & INTERNAL_ADDR_DECODE == 1'b0) ? sc_ack_info_lt[0:1] :
(is_gen_ulinfo == 1'b1 & INTERNAL_ADDR_DECODE == 1'b1) ? {(write_nvld | read_nvld), addr_nvld} :
(is_send_ulinfo == 1'b1) ? tail_lt[3:4] : // shift out
tail_lt[2:3];
// Write Data Parity error
assign tail_in[1] = (is_gen_ulinfo == 1'b1) ? (wpar_err & do_write) : // parity error on write operation
(is_send_ulinfo == 1'b1) ? tail_lt[2] : // shift out
tail_lt[1];
// parity check of of downlink P0 yields error
assign tail_in[0] = (is_check_before == 1'b1) ? (~p0_err) : // set to '1' if a downlink parity error is detected by satellite, otherwise '0'
(is_send_ulinfo == 1'b1) ? tail_lt[1] : // shift out
tail_lt[0];
// sample and hold ack_info, one spare bit
assign sc_ack_info_in = ((is_exe_cmd & sc_ack) == 1'b1) ? sc_ack_info :
(is_idle == 1'b1) ? 2'b00 :
sc_ack_info_lt;
//-----------------------------------------------------------------------------
assign do_write = (~do_read);
assign do_read = head_lt[RW_BIT_INDEX];
assign match = (head_lt[1:SATID_NOBITS] == sat_id_net);
// if downlink parity error then set p0_err
assign p0_err = (is_check_before & (^(head_lt[1:PARBIT_INDEX])));
// why constant 11 here: ???
// first part sat id; second part reg address (curr. 6 bits) => 10 instead of 11
// now new constant SATID_REGID_NOBITS
assign parity_satid_regaddr = (^{sat_id_net, head_lt[SATID_NOBITS+1:SATID_REGID_NOBITS]});
assign any_ack_error = (|sc_ack_info_lt);
//-----------------------------------------------------------------------------
assign data_mux = ((is_check_before | is_rec_wdata) == 1'b1) ? dch_lt : 1'b0;
assign data_shifter_in = ((is_check_before | (is_rec_wdata & (~cntgtheadpluswidth)) | is_send_rdata) == 1'b1) ? {data_shifter_lt[1:WIDTH-1], data_mux} :
((is_exe_cmd & sc_ack & do_read) == 1'b1) ? sc_rdata :
data_shifter_lt;
//-----------------------------------------------------------------------------
// parity handling
assign par_mux = ((is_rec_wpar) == 1'b1) ? dch_lt : 1'b0;
// receiving parity: shift when receiving write data parity
// sending parity of read data: shift when sending read data parity
// latch generated parity of read data when read data is accepted
assign datapar_shifter_in = (((is_rec_wpar & (~cntgteofwdataplusparity)) | (is_send_rdata & do_send_par)) == 1'b1) ? {datapar_shifter_lt[1:PAR_NOBITS-1], par_mux} :
((is_filler_1 == 1'b1)) ? sc_rparity :
datapar_shifter_lt;
//----------------------------------------------------------------------------
assign data_shifter_lt_tmp[0:WIDTH-1] = data_shifter_lt;
generate
if (WIDTH < 64)
begin : data_shifter_padding
assign data_shifter_lt_tmp[WIDTH:63] = {64-WIDTH {1'b0}};
end
endgenerate
generate
begin : xhdl0
genvar i;
for (i=0; i<=PAR_NOBITS-1; i=i+1)
begin : wdata_par_check
assign par_data_in[i] = (^data_shifter_lt_tmp[16*i:16*(i+1)-1]);
end
end
endgenerate
generate
if (PIPELINE_PARITYCHK == 1'b1)
begin : wdata_par_check_pipe
tri_nlat_scan #(.WIDTH(PAR_NOBITS), .NEEDS_SRESET(1)) state(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21]),
.din(par_data_in),
.q(par_data_lt)
);
end
endgenerate
generate
if (PIPELINE_PARITYCHK == 1'b0)
begin : wdata_par_check_nopipe
assign par_data_lt = par_data_in;
assign func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21] =
func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21];
end
endgenerate
assign wpar_err = (^{par_data_lt, datapar_shifter_lt});
//-----------------------------------------------------------------------------
generate
begin : xhdl1
genvar i;
for (i=0; i<=PAR_NOBITS-1; i=i+1)
begin : rdata_parity_gen
assign sc_rparity[i] = (^data_shifter_lt_tmp[16*i:16*(i+1)-1]);
end
end
endgenerate
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------
// address decoding section
// Generate onehot Address (binary to one-hot)
//-----------------------------------------------------------------
//-----------------------------------------------------------------------------
generate
if (INTERNAL_ADDR_DECODE == 1'b1)
begin : internal_addr_decoding
//-----------------------------------------------------------------------------
genvar i;
for (i=0; i<WIDTH; i=i+1)
begin : foralladdresses
if ( USE_ADDR[i] == 1'b1)
begin : addr_bit_set
assign dec_addr_in[i] = (head_lt[SATID_NOBITS+1:SATID_REGID_NOBITS] == i);
// generate latch to hold addr_v only if required
if ( PIPELINE_ADDR_V[i] == 1'b1)
begin : latch_for_onehot
tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) dec_addr(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.d2clk(d2clk),
.lclk(lclk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i]),
.din(dec_addr_in[i]),
.q(dec_addr_q[i])
);
end
// otherwise no latch
if ( PIPELINE_ADDR_V[i] == 1'b0)
begin : no_latch_for_onehot
assign func_scan_out[STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i] =
func_scan_in[ STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i];
assign dec_addr_q[i] = dec_addr_in[i];
end
end
//----------------------------------------------------------------------
if ( USE_ADDR[i] != 1'b1) // do not generate hardware for unused addresses
begin : addr_bit_notset
assign func_scan_out[STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i] =
func_scan_in[ STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i];
assign dec_addr_in[i] = 1'b0;
assign dec_addr_q[i] = dec_addr_in[i];
end
end
//------------------------------------------------------------------------
// check writable and/or readable
assign read_valid = (|(dec_addr_q & ADDR_IS_RDABLE));
assign write_valid = (|(dec_addr_q & ADDR_IS_WRABLE));
assign addr_nvld = (~(|dec_addr_q));
assign write_nvld = ((~write_valid) & (~addr_nvld)) & do_write;
assign read_nvld = ((~read_valid) & (~addr_nvld)) & do_read;
assign unused = 2'b00;
end
endgenerate
generate
if (INTERNAL_ADDR_DECODE == 1'b0)
begin : external_addr_decoding
genvar i;
for (i=0; i<WIDTH ; i=i+1)
begin : foralladdresses
assign func_scan_out[STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i] =
func_scan_in[ STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i];
assign dec_addr_in[i] = 1'b0;
assign dec_addr_q[i] = dec_addr_in[i];
end
assign read_valid = 1'b1; // suppressing wrong error generation
assign write_valid = 1'b1; // suppressing wrong error generation
assign addr_nvld = 1'b0;
assign write_nvld = 1'b0;
assign read_nvld = 1'b0;
assign unused = {write_valid, read_valid};
end
endgenerate
// This was for unused addresses if USE_ADDR was smaller than the 64 bit width.
// From VHDL: short_unused_addr_range: for i in use_addr'high+1 to 63 generate
// Shouldn't be needed for A2, since we always define 64 SCOM addresses.
generate
begin : xhdl4
genvar i;
for (i=WIDTH; i<64; i=i+1)
begin : short_unused_addr_range
assign func_scan_out[STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i] =
func_scan_in[ STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i];
end
end
endgenerate
assign addr_v = dec_addr_q[0:WIDTH-1];
//-----------------------------------------------------------------------------
tri_nlat_scan #(.WIDTH(STATE_WIDTH), .INIT(IDLE), .NEEDS_SRESET(1)) state(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ 0:STATE_WIDTH-1]),
.scan_out(func_scan_out[0:STATE_WIDTH-1]),
.din(state_in),
.q(state_lt)
);
tri_nlat_scan #(.WIDTH(7), .INIT(7'b0000000), .NEEDS_SRESET(1)) counter(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH:STATE_WIDTH+6]),
.scan_out(func_scan_out[STATE_WIDTH:STATE_WIDTH+6]),
.din(cnt_in),
.q(cnt_lt)
);
tri_nlat_scan #(.WIDTH(WIDTH), .NEEDS_SRESET(1)) data_shifter(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+7:STATE_WIDTH+WIDTH+6]),
.scan_out(func_scan_out[STATE_WIDTH+7:STATE_WIDTH+WIDTH+6]),
.din(data_shifter_in),
.q(data_shifter_lt)
);
tri_nlat_scan #(.WIDTH(PAR_NOBITS), .NEEDS_SRESET(1)) datapar_shifter(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+6]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+6]),
.din(datapar_shifter_in),
.q(datapar_shifter_lt)
);
tri_nlat_scan #(.WIDTH(HEAD_WIDTH), .INIT(HEAD_INIT), .NEEDS_SRESET(1)) head_lat(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+6]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+6]),
.din(head_in),
.q(head_lt)
);
tri_nlat_scan #(.WIDTH(5), .INIT(5'b00000), .NEEDS_SRESET(1)) tail_lat(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+11]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+11]),
.din(tail_in),
.q(tail_lt)
);
tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) dch_inlatch(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+12]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+12]),
.din(scom_dch_in),
.q(dch_lt)
);
tri_nlat_scan #(.WIDTH(2), .NEEDS_SRESET(1)) ack_info(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+13:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+14]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+13:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+14]),
.din(sc_ack_info_in),
.q(sc_ack_info_lt)
);
tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) dch_outlatch(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+15]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+15]),
.din(dch_out_internal_in),
.q(dch_out_internal_lt)
);
tri_nlat_scan #(.WIDTH(2), .NEEDS_SRESET(1)) cch_latches(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+16:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+17]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+16:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+17]),
.din(cch_in),
.q(cch_lt)
);
tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) scom_err_latch(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+18]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+18]),
.din(scom_err_in),
.q(scom_err_lt)
);
tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) scom_local_act_latch(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+19]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+19]),
.din(scom_local_act_in),
.q(scom_local_act_lt)
);
tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) spare_latch1(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+20]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+20]),
.din(spare_latch1_in),
.q(spare_latch1_lt)
);
tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) spare_latch2(
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+21]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+21]),
.din(spare_latch2_in),
.q(spare_latch2_lt)
);
//-----------------------------------------------------------------------------
assign unused_signals = |({is_filler_0, is_filler_1, spare_latch1_lt, spare_latch2_lt, d_mode_dc});
assign spare_latch1_in = 1'b0;
assign spare_latch2_in = 1'b0;
endmodule |
module tri_st_add_loc(
g01_b,
t01_b,
sum_0,
sum_1
);
input [0:7] g01_b; // after xor
input [0:7] t01_b;
output [0:7] sum_0;
output [0:7] sum_1;
wire [0:7] g01_t;
wire [0:7] g01_not;
wire [0:7] z01_b;
wire [0:7] p01;
wire [0:7] p01_b;
wire [0:7] g02;
wire [0:7] t02;
wire [0:7] g04_b;
wire [0:7] t04_b;
wire [0:7] g08;
wire [0:7] t08;
(* ANALYSIS_NOT_REFERENCED="<0>TRUE" *)
wire [0:7] g08_b;
(* ANALYSIS_NOT_REFERENCED="<0>TRUE" *)
wire [0:7] t08_b;
//####################################################################
//# funny way to make xor
//####################################################################
assign g01_t[0:7] = (~g01_b[0:7]); //small (buffer off)
assign g01_not[0:7] = (~g01_t[0:7]); //small (buffer off)
assign z01_b[0:7] = (~t01_b[0:7]);
assign p01_b[0:7] = (~(g01_not[0:7] & z01_b[0:7]));
assign p01[0:7] = (~(p01_b[0:7]));
//####################################################################
//# conditional sums // may need to make NON-xor implementation
//####################################################################
//xx u_sum_0: sum_0(0 to 7) <= not( p01_b(0 to 7) xor g08(0 to 7) ); --output--
//xx u_sum_1: sum_1(0 to 7) <= not( p01_b(0 to 7) xor t08(0 to 7) ); --output--
assign g08_b[0] = (~g08[0]);
assign g08_b[1] = (~g08[1]);
assign g08_b[2] = (~g08[2]);
assign g08_b[3] = (~g08[3]);
assign g08_b[4] = (~g08[4]);
assign g08_b[5] = (~g08[5]);
assign g08_b[6] = (~g08[6]);
assign g08_b[7] = (~g08[7]);
assign t08_b[0] = (~t08[0]);
assign t08_b[1] = (~t08[1]);
assign t08_b[2] = (~t08[2]);
assign t08_b[3] = (~t08[3]);
assign t08_b[4] = (~t08[4]);
assign t08_b[5] = (~t08[5]);
assign t08_b[6] = (~t08[6]);
assign t08_b[7] = (~t08[7]);
assign sum_0[0] = (~((p01[0] & g08[1]) | (p01_b[0] & g08_b[1]))); //output--
assign sum_0[1] = (~((p01[1] & g08[2]) | (p01_b[1] & g08_b[2]))); //output--
assign sum_0[2] = (~((p01[2] & g08[3]) | (p01_b[2] & g08_b[3]))); //output--
assign sum_0[3] = (~((p01[3] & g08[4]) | (p01_b[3] & g08_b[4]))); //output--
assign sum_0[4] = (~((p01[4] & g08[5]) | (p01_b[4] & g08_b[5]))); //output--
assign sum_0[5] = (~((p01[5] & g08[6]) | (p01_b[5] & g08_b[6]))); //output--
assign sum_0[6] = (~((p01[6] & g08[7]) | (p01_b[6] & g08_b[7]))); //output--
assign sum_0[7] = (~(p01_b[7])); //output--
assign sum_1[0] = (~((p01[0] & t08[1]) | (p01_b[0] & t08_b[1]))); //output--
assign sum_1[1] = (~((p01[1] & t08[2]) | (p01_b[1] & t08_b[2]))); //output--
assign sum_1[2] = (~((p01[2] & t08[3]) | (p01_b[2] & t08_b[3]))); //output--
assign sum_1[3] = (~((p01[3] & t08[4]) | (p01_b[3] & t08_b[4]))); //output--
assign sum_1[4] = (~((p01[4] & t08[5]) | (p01_b[4] & t08_b[5]))); //output--
assign sum_1[5] = (~((p01[5] & t08[6]) | (p01_b[5] & t08_b[6]))); //output--
assign sum_1[6] = (~((p01[6] & t08[7]) | (p01_b[6] & t08_b[7]))); //output--
assign sum_1[7] = (~(p01[7])); //output--
//####################################################################
//# local carry
//####################################################################
assign g02[0] = (~(g01_b[0] & (t01_b[0] | g01_b[1])));
assign g02[1] = (~(g01_b[1] & (t01_b[1] | g01_b[2])));
assign g02[2] = (~(g01_b[2] & (t01_b[2] | g01_b[3])));
assign g02[3] = (~(g01_b[3] & (t01_b[3] | g01_b[4])));
assign g02[4] = (~(g01_b[4] & (t01_b[4] | g01_b[5])));
assign g02[5] = (~(g01_b[5] & (t01_b[5] | g01_b[6])));
assign g02[6] = (~(g01_b[6] & (t01_b[6] | g01_b[7]))); //final--
assign g02[7] = (~(g01_b[7]));
assign t02[0] = (~(t01_b[0] | t01_b[1]));
assign t02[1] = (~(t01_b[1] | t01_b[2]));
assign t02[2] = (~(t01_b[2] | t01_b[3]));
assign t02[3] = (~(t01_b[3] | t01_b[4]));
assign t02[4] = (~(t01_b[4] | t01_b[5]));
assign t02[5] = (~(t01_b[5] | t01_b[6]));
assign t02[6] = (~(g01_b[6] & (t01_b[6] | t01_b[7]))); //final--
assign t02[7] = (~(t01_b[7]));
assign g04_b[0] = (~(g02[0] | (t02[0] & g02[2])));
assign g04_b[1] = (~(g02[1] | (t02[1] & g02[3])));
assign g04_b[2] = (~(g02[2] | (t02[2] & g02[4])));
assign g04_b[3] = (~(g02[3] | (t02[3] & g02[5])));
assign g04_b[4] = (~(g02[4] | (t02[4] & g02[6]))); //final--
assign g04_b[5] = (~(g02[5] | (t02[5] & g02[7]))); //final--
assign g04_b[6] = (~(g02[6]));
assign g04_b[7] = (~(g02[7]));
assign t04_b[0] = (~(t02[0] & t02[2]));
assign t04_b[1] = (~(t02[1] & t02[3]));
assign t04_b[2] = (~(t02[2] & t02[4]));
assign t04_b[3] = (~(t02[3] & t02[5]));
assign t04_b[4] = (~(g02[4] | (t02[4] & t02[6]))); //final--
assign t04_b[5] = (~(g02[5] | (t02[5] & t02[7]))); //final--
assign t04_b[6] = (~(t02[6]));
assign t04_b[7] = (~(t02[7]));
assign g08[0] = (~(g04_b[0] & (t04_b[0] | g04_b[4]))); //final--
assign g08[1] = (~(g04_b[1] & (t04_b[1] | g04_b[5]))); //final--
assign g08[2] = (~(g04_b[2] & (t04_b[2] | g04_b[6]))); //final--
assign g08[3] = (~(g04_b[3] & (t04_b[3] | g04_b[7]))); //final--
assign g08[4] = (~(g04_b[4]));
assign g08[5] = (~(g04_b[5]));
assign g08[6] = (~(g04_b[6]));
assign g08[7] = (~(g04_b[7]));
assign t08[0] = (~(g04_b[0] & (t04_b[0] | t04_b[4]))); //final--
assign t08[1] = (~(g04_b[1] & (t04_b[1] | t04_b[5]))); //final--
assign t08[2] = (~(g04_b[2] & (t04_b[2] | t04_b[6]))); //final--
assign t08[3] = (~(g04_b[3] & (t04_b[3] | t04_b[7]))); //final--
assign t08[4] = (~(t04_b[4]));
assign t08[5] = (~(t04_b[5]));
assign t08[6] = (~(t04_b[6]));
assign t08[7] = (~(t04_b[7]));
endmodule |
module tri_st_add_glbglbci(
g08,
t08,
ci,
c64_b
);
input [0:7] g08;
input [0:7] t08;
input ci;
output [0:7] c64_b;
wire [0:3] b0_g16_b;
wire [0:2] b0_t16_b;
wire [0:1] b0_g32;
wire [0:0] b0_t32;
wire [0:3] b1_g16_b;
wire [0:2] b1_t16_b;
wire [0:1] b1_g32;
wire [0:0] b1_t32;
wire [0:3] b2_g16_b;
wire [0:2] b2_t16_b;
wire [0:1] b2_g32;
wire [0:0] b2_t32;
wire [0:3] b3_g16_b;
wire [0:2] b3_t16_b;
wire [0:1] b3_g32;
wire [0:0] b3_t32;
wire [0:3] b4_g16_b;
wire [0:2] b4_t16_b;
wire [0:1] b4_g32;
wire [0:0] b4_t32;
wire [0:2] b5_g16_b;
wire [0:1] b5_t16_b;
wire [0:1] b5_g32;
wire [0:0] b5_t32;
wire [0:1] b6_g16_b;
wire [0:0] b6_t16_b;
wire [0:0] b6_g32;
wire [0:0] b7_g16_b;
wire [0:0] b7_g32;
wire b0_g56_b;
wire b0_c64;
wire [0:0] g08_b;
wire [0:0] t08_b;
////#############################
////## byte 0 <for CO only ??
////#############################
assign b0_g16_b[0] = (~(g08[1] | (t08[1] & g08[2])));
assign b0_g16_b[1] = (~(g08[3] | (t08[3] & g08[4])));
assign b0_g16_b[2] = (~(g08[5] | (t08[5] & g08[6])));
assign b0_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
assign b0_t16_b[0] = (~(t08[1] & t08[2]));
assign b0_t16_b[1] = (~(t08[3] & t08[4]));
assign b0_t16_b[2] = (~(t08[5] & t08[6]));
assign b0_g32[0] = (~(b0_g16_b[0] & (b0_t16_b[0] | b0_g16_b[1])));
assign b0_g32[1] = (~(b0_g16_b[2] & (b0_t16_b[2] | b0_g16_b[3])));
assign b0_t32[0] = (~(b0_t16_b[0] | b0_t16_b[1]));
assign g08_b[0] = (~g08[0]);
assign t08_b[0] = (~t08[0]);
assign b0_g56_b = (~(b0_g32[0] | (b0_t32[0] & b0_g32[1]))); //output--
assign b0_c64 = (~(g08_b[0] & (t08_b[0] | b0_g56_b)));
assign c64_b[0] = (~(b0_c64));
////#############################
////## byte 1
////#############################
assign b1_g16_b[0] = (~(g08[1] | (t08[1] & g08[2])));
assign b1_g16_b[1] = (~(g08[3] | (t08[3] & g08[4])));
assign b1_g16_b[2] = (~(g08[5] | (t08[5] & g08[6])));
assign b1_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
assign b1_t16_b[0] = (~(t08[1] & t08[2]));
assign b1_t16_b[1] = (~(t08[3] & t08[4]));
assign b1_t16_b[2] = (~(t08[5] & t08[6]));
assign b1_g32[0] = (~(b1_g16_b[0] & (b1_t16_b[0] | b1_g16_b[1])));
assign b1_g32[1] = (~(b1_g16_b[2] & (b1_t16_b[2] | b1_g16_b[3])));
assign b1_t32[0] = (~(b1_t16_b[0] | b1_t16_b[1]));
assign c64_b[1] = (~(b1_g32[0] | (b1_t32[0] & b1_g32[1]))); //output--
////#############################
////## byte 2
////#############################
assign b2_g16_b[0] = (~(g08[2] | (t08[2] & g08[3])));
assign b2_g16_b[1] = (~(g08[4] | (t08[4] & g08[5])));
assign b2_g16_b[2] = (~(g08[6]));
assign b2_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
assign b2_t16_b[0] = (~(t08[2] & t08[3]));
assign b2_t16_b[1] = (~(t08[4] & t08[5]));
assign b2_t16_b[2] = (~(t08[6]));
assign b2_g32[0] = (~(b2_g16_b[0] & (b2_t16_b[0] | b2_g16_b[1])));
assign b2_g32[1] = (~(b2_g16_b[2] & (b2_t16_b[2] | b2_g16_b[3])));
assign b2_t32[0] = (~(b2_t16_b[0] | b2_t16_b[1]));
assign c64_b[2] = (~(b2_g32[0] | (b2_t32[0] & b2_g32[1]))); //output--
////#############################
////## byte 3
////#############################
assign b3_g16_b[0] = (~(g08[3] | (t08[3] & g08[4])));
assign b3_g16_b[1] = (~(g08[5]));
assign b3_g16_b[2] = (~(g08[6]));
assign b3_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
assign b3_t16_b[0] = (~(t08[3] & t08[4]));
assign b3_t16_b[1] = (~(t08[5]));
assign b3_t16_b[2] = (~(t08[6]));
assign b3_g32[0] = (~(b3_g16_b[0] & (b3_t16_b[0] | b3_g16_b[1])));
assign b3_g32[1] = (~(b3_g16_b[2] & (b3_t16_b[2] | b3_g16_b[3])));
assign b3_t32[0] = (~(b3_t16_b[0] | b3_t16_b[1]));
assign c64_b[3] = (~(b3_g32[0] | (b3_t32[0] & b3_g32[1]))); //output--
////#############################
////## byte 4
////#############################
assign b4_g16_b[0] = (~(g08[4]));
assign b4_g16_b[1] = (~(g08[5]));
assign b4_g16_b[2] = (~(g08[6]));
assign b4_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
assign b4_t16_b[0] = (~(t08[4]));
assign b4_t16_b[1] = (~(t08[5]));
assign b4_t16_b[2] = (~(t08[6]));
assign b4_g32[0] = (~(b4_g16_b[0] & (b4_t16_b[0] | b4_g16_b[1])));
assign b4_g32[1] = (~(b4_g16_b[2] & (b4_t16_b[2] | b4_g16_b[3])));
assign b4_t32[0] = (~(b4_t16_b[0] | b4_t16_b[1]));
assign c64_b[4] = (~(b4_g32[0] | (b4_t32[0] & b4_g32[1]))); //output--
////#############################
////## byte 5
////#############################
assign b5_g16_b[0] = (~(g08[5]));
assign b5_g16_b[1] = (~(g08[6]));
assign b5_g16_b[2] = (~(g08[7] | (t08[7] & ci)));
assign b5_t16_b[0] = (~(t08[5]));
assign b5_t16_b[1] = (~(t08[6]));
assign b5_g32[0] = (~(b5_g16_b[0] & (b5_t16_b[0] | b5_g16_b[1])));
assign b5_g32[1] = (~(b5_g16_b[2]));
assign b5_t32[0] = (~(b5_t16_b[0] | b5_t16_b[1]));
assign c64_b[5] = (~(b5_g32[0] | (b5_t32[0] & b5_g32[1]))); //output--
////#############################
////## byte 6
////#############################
assign b6_g16_b[0] = (~(g08[6]));
assign b6_g16_b[1] = (~(g08[7] | (t08[7] & ci)));
assign b6_t16_b[0] = (~(t08[6]));
assign b6_g32[0] = (~(b6_g16_b[0] & (b6_t16_b[0] | b6_g16_b[1])));
assign c64_b[6] = (~(b6_g32[0])); //output--
////#############################
////## byte 7
////#############################
assign b7_g16_b[0] = (~(g08[7] | (t08[7] & ci)));
assign b7_g32[0] = (~(b7_g16_b[0]));
assign c64_b[7] = (~(b7_g32[0])); //output--
endmodule |
module tri_lcbnd(
vd,
gd,
act,
delay_lclkr,
mpw1_b,
mpw2_b,
nclk,
force_t,
sg,
thold_b,
d1clk,
d2clk,
lclk
);
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input act;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input[0:`NCLK_WIDTH-1] nclk;
input force_t;
input sg;
input thold_b;
output d1clk;
output d2clk;
output[0:`NCLK_WIDTH-1] lclk;
// tri_lcbnd
wire gate_b;
(* analysis_not_referenced="true" *)
wire unused;
assign unused = vd | gd | delay_lclkr | mpw1_b | mpw2_b | sg;
assign gate_b = force_t | act;
assign d1clk = gate_b;
assign d2clk = thold_b;
assign lclk = nclk;
endmodule |
module tri_st_mult_boothdcd(
i0,
i1,
i2,
s_neg,
s_x,
s_x2
);
input i0;
input i1;
input i2;
output s_neg;
output s_x;
output s_x2;
wire s_add;
wire sx1_a0_b;
wire sx1_a1_b;
wire sx1_t;
wire sx1_i;
wire sx2_a0_b;
wire sx2_a1_b;
wire sx2_t;
wire sx2_i;
wire i0_b;
wire i1_b;
wire i2_b;
// i0:2 booth recode table
//--------------------------------
// 000 add sh1=0 sh2=0 sub_adj=0
// 001 add sh1=1 sh2=0 sub_adj=0
// 010 add sh1=1 sh2=0 sub_adj=0
// 011 add sh1=0 sh2=1 sub_adj=0
// 100 sub sh1=0 sh2=1 sub_adj=1
// 101 sub sh1=1 sh2=0 sub_adj=1
// 110 sub sh1=1 sh2=0 sub_adj=1
// 111 sub sh1=0 sh2=0 sub_adj=0
// logically correct
//----------------------------------
// s_neg <= (i0);
// s_x <= ( not i1 and i2) or ( i1 and not i2);
// s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2);
assign i0_b = (~(i0));
assign i1_b = (~(i1));
assign i2_b = (~(i2));
assign s_add = (~(i0));
assign s_neg = (~(s_add));
assign sx1_a0_b = (~(i1_b & i2));
assign sx1_a1_b = (~(i1 & i2_b));
assign sx1_t = (~(sx1_a0_b & sx1_a1_b));
assign sx1_i = (~(sx1_t));
assign s_x = (~(sx1_i));
assign sx2_a0_b = (~(i0 & i1_b & i2_b));
assign sx2_a1_b = (~(i0_b & i1 & i2));
assign sx2_t = (~(sx2_a0_b & sx2_a1_b));
assign sx2_i = (~(sx2_t));
assign s_x2 = (~(sx2_i));
endmodule |
module tri_debug_mux4(
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
trace_data_in,
trace_data_out,
// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);
// Include model build parameters
parameter DBG_WIDTH = 32; // A2o=32; A2i=88
//=====================================================================
// Port Definitions
//=====================================================================
input [0:10] select_bits;
input [0:DBG_WIDTH-1] dbg_group0;
input [0:DBG_WIDTH-1] dbg_group1;
input [0:DBG_WIDTH-1] dbg_group2;
input [0:DBG_WIDTH-1] dbg_group3;
input [0:DBG_WIDTH-1] trace_data_in;
output [0:DBG_WIDTH-1] trace_data_out;
// Instruction Trace (HTM) Control Signals:
// 0 - ac_an_coretrace_first_valid
// 1 - ac_an_coretrace_valid
// 2:3 - ac_an_coretrace_type[0:1]
input [0:3] coretrace_ctrls_in;
output [0:3] coretrace_ctrls_out;
//=====================================================================
// Signal Declarations / Misc
//=====================================================================
parameter DBG_1FOURTH = DBG_WIDTH/4;
parameter DBG_2FOURTH = DBG_WIDTH/2;
parameter DBG_3FOURTH = 3 * DBG_WIDTH/4;
wire [0:DBG_WIDTH-1] debug_grp_selected;
wire [0:DBG_WIDTH-1] debug_grp_rotated;
// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
wire unused;
assign unused = (|select_bits[2:4]) ;
// Instruction Trace controls are passed-through:
assign coretrace_ctrls_out = coretrace_ctrls_in ;
//=====================================================================
// Mux Function
//=====================================================================
// Debug Mux
assign debug_grp_selected = (select_bits[0:1] == 2'b00) ? dbg_group0 :
(select_bits[0:1] == 2'b01) ? dbg_group1 :
(select_bits[0:1] == 2'b10) ? dbg_group2 :
dbg_group3;
assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
debug_grp_selected[0:DBG_WIDTH - 1];
assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
debug_grp_rotated[0:DBG_1FOURTH - 1];
assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
endmodule |
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