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module CSkipA8(output [7:0] sum, output cout, input [7:0] a, b);
wire cout0, cout1, e;
RCA4 rca0(sum[3:0], cout0, a[3:0], b[3:0], 0);
RCA4 rca1(sum[7:4], cout1, a[7:4], b[7:4], e);
SkipLogic skip0(e, a[3:0], b[3:0], 0, cout0);
SkipLogic skip1(cout, a[7:4], b[7:4], e, cout1);
endmodule |
module CSkipA16(output [15:0] sum, output cout, input [15:0] a, b);
wire [3:0] couts;
wire [2:0] e;
RCA4 rca0(sum[3:0], couts[0], a[3:0], b[3:0], 0);
RCA4 rca[3:1](sum[15:4], couts[3:1], a[15:4], b[15:4], e[2:0]);
SkipLogic skip0(e[0], a[3:0], b[3:0], 0, couts[0]);
SkipLogic skip[2:1](e[2:1], a[11:4], b[11:4], e[1:0], couts[2:1]);
SkipLogic skip3(cout, a[15:12], b[15:12], e[2], couts[3]);
endmodule |
module CSkipA32(output [31:0] sum, output cout, input [31:0] a, b);
wire [7:0] couts;
wire [6:0] e;
RCA4 rca0(sum[3:0], couts[0], a[3:0], b[3:0], 0);
RCA4 rca[7:1](sum[31:4], couts[7:1], a[31:4], b[31:4], e[6:0]);
SkipLogic skip0(e[0], a[3:0], b[3:0], 0, couts[0]);
SkipLogic skip[6:1](e[6:1], a[27:4], b[27:4], e[5:0], couts[6:1]);
SkipLogic skip7(cout, a[31:28], b[31:24], e[6], couts[7]);
endmodule |
module CSkipA64(output [63:0] sum, output cout, input [63:0] a, b);
wire [15:0] couts;
wire [14:0] e;
RCA4 rca0(sum[3:0], couts[0], a[3:0], b[3:0], 0);
RCA4 rca[15:1](sum[63:4], couts[15:1], a[63:4], b[63:4], e[14:0]);
SkipLogic skip0(e[0], a[3:0], b[3:0], 0, couts[0]);
SkipLogic skip[14:1](e[14:1], a[59:4], b[59:4], e[13:0], couts[14:1]);
SkipLogic skip15(cout, a[63:60], b[63:60], e[14], couts[15]);
endmodule |
module tb_CSelA8;
wire [7:0] sum;
wire cout;
reg [7:0] a, b;
reg cin;
CSelA8 csa8(sum[7:0], cout, a[7:0], b[7:0]);
initial
begin
$display("a |b ||cout|sum ");
end
initial
begin
$monitor("%b|%b||%b |%b", a[7:0], b[7:0], cout, sum[7:0]);
end
initial
begin
a=8'b10100000; b=8'b10100000;
#10 a=8'b01011000; b=8'b11110100;
#10 a=8'b00111101; b=8'b00001111;
#10 a=8'b11001010; b=8'b11001000;
#10 a=8'b10100110; b=8'b11110100;
#10 a=8'b11110011; b=8'b11001100;
#10 a=8'b11110011; b=8'b01010111;
end
endmodule |
module tb_CSelA16;
wire [15:0] sum;
wire cout;
reg [15:0] a, b;
reg cin;
CSelA16 csa16(sum[15:0], cout, a[15:0], b[15:0]);
initial
begin
$display("a |b ||cout|sum ");
end
initial
begin
$monitor("%b|%b||%b |%b", a[15:0], b[15:0], cout, sum[15:0]);
end
initial
begin
a=16'b1010000010100000; b=16'b1010000010100000;
#10 a=16'b0101100011110100; b=16'b1111010011110100;
#10 a=16'b0000111100111101; b=16'b0000111100001111;
#10 a=16'b1100100011001010; b=16'b1100100011001010;
end
endmodule |
module tb_CSelA32;
wire [31:0] sum;
wire cout;
reg [31:0] a, b;
reg cin;
CSelA32 csa32(sum[31:0], cout, a[31:0], b[31:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%h|%h||%b|%h", a[31:0], b[31:0], cout, sum[31:0]);
end
initial
begin
a='b10100000101000001111111111111111; b='b10100000101111111111111111100000;
#10 a='b01011000111111111111111111110100; b='b11110100111101001111111111111111;
#10 a='b11111111111111110000111100111101; b='b00001111000011111111111111111111;
#10 a='b11011111111111111110100011001010; b='b11001111111111111111100011001010;
end
endmodule |
module tb_CSelA64;
wire [63:0] sum;
wire cout;
reg [63:0] a, b;
reg cin;
CSelA64 csa64(sum[63:0], cout, a[63:0], b[63:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%d|%d||%d|%d", a[63:0], b[63:0], cout, sum[63:0]);
end
initial
begin
a=64'd998; b=64'd128;
#10 a=64'd9998; b=64'd9028;
#10 a=64'd09989998; b=64'd769028;
end
endmodule |
module MUX2to1_w1(output y, input i0, i1, s);
wire e0, e1;
not #(1) (sn, s);
and #(1) (e0, i0, sn);
and #(1) (e1, i1, s);
or #(1) (y, e0, e1);
endmodule |
module MUX2to1_w4(output [3:0] y, input [3:0] i0, i1, input s);
wire [3:0] e0, e1;
not #(1) (sn, s);
and #(1) (e0[0], i0[0], sn);
and #(1) (e0[1], i0[1], sn);
and #(1) (e0[2], i0[2], sn);
and #(1) (e0[3], i0[3], sn);
and #(1) (e1[0], i1[0], s);
and #(1) (e1[1], i1[1], s);
and #(1) (e1[2], i1[2], s);
and #(1) (e1[3], i1[3], s);
or #(1) (y[0], e0[0], e1[0]);
or #(1) (y[1], e0[1], e1[1]);
or #(1) (y[2], e0[2], e1[2]);
or #(1) (y[3], e0[3], e1[3]);
endmodule |
module CSelA8(output [7:0] sum, output cout, input [7:0] a, b);
wire [7:0] sum0, sum1;
wire c1;
RCA4 rca0_0(sum0[3:0], cout0_0, a[3:0], b[3:0], 0);
RCA4 rca0_1(sum1[3:0], cout0_1, a[3:0], b[3:0], 1);
MUX2to1_w4 mux0_sum(sum[3:0], sum0[3:0], sum1[3:0], 0);
MUX2to1_w1 mux0_cout(c1, cout0_0, cout0_1, 0);
RCA4 rca1_0(sum0[7:4], cout1_0, a[7:4], b[7:4], 0);
RCA4 rca1_1(sum1[7:4], cout1_1, a[7:4], b[7:4], 1);
MUX2to1_w4 mux1_sum(sum[7:4], sum0[7:4], sum1[7:4], c1);
MUX2to1_w1 mux1_cout(cout, cout1_0, cout1_1, c1);
endmodule |
module CSelA16(output [15:0] sum, output cout, input [15:0] a, b);
wire [15:0] sum0, sum1;
wire c1, c2, c3;
RCA4 rca0_0(sum0[3:0], cout0_0, a[3:0], b[3:0], 0);
RCA4 rca0_1(sum1[3:0], cout0_1, a[3:0], b[3:0], 1);
MUX2to1_w4 mux0_sum(sum[3:0], sum0[3:0], sum1[3:0], 0);
MUX2to1_w1 mux0_cout(c1, cout0_0, cout0_1, 0);
RCA4 rca1_0(sum0[7:4], cout1_0, a[7:4], b[7:4], 0);
RCA4 rca1_1(sum1[7:4], cout1_1, a[7:4], b[7:4], 1);
MUX2to1_w4 mux1_sum(sum[7:4], sum0[7:4], sum1[7:4], c1);
MUX2to1_w1 mux1_cout(c2, cout1_0, cout1_1, c1);
RCA4 rca2_0(sum0[11:8], cout2_0, a[11:8], b[11:8], 0);
RCA4 rca2_1(sum1[11:8], cout2_1, a[11:8], b[11:8], 1);
MUX2to1_w4 mux2_sum(sum[11:8], sum0[11:8], sum1[11:8], c2);
MUX2to1_w1 mux2_cout(c3, cout2_0, cout2_1, c1);
RCA4 rca3_0(sum0[15:12], cout3_0, a[15:12], b[15:12], 0);
RCA4 rca3_1(sum1[15:12], cout3_1, a[15:12], b[15:12], 1);
MUX2to1_w4 mux3_sum(sum[15:12], sum0[15:12], sum1[15:12], c3);
MUX2to1_w1 mux3_cout(cout, cout3_0, cout3_1, c1);
endmodule |
module CSelA32(output [31:0] sum, output cout, input [31:0] a, b);
wire [31:0] sum0, sum1;
wire [7:1] c;
wire [7:0] cout0, cout1;
RCA4 rca0_0(sum0[3:0], cout0[0], a[3:0], b[3:0], 0);
RCA4 rca0_1(sum1[3:0], cout1[0], a[3:0], b[3:0], 1);
MUX2to1_w4 mux0_sum(sum[3:0], sum0[3:0], sum1[3:0], 0);
MUX2to1_w1 mux0_cout(c[1], cout0[0], cout1[0], 0);
RCA4 rca_other_0[6:1](sum0[27:4], cout0[6:1], a[27:4], b[27:4], 1'b0);
RCA4 rca_other_1[6:1](sum1[27:4], cout1[6:1], a[27:4], b[27:4], 1'b1);
MUX2to1_w4 mux_other_sum[6:1](sum[27:4], sum0[27:4], sum1[27:4], c[6:1]);
MUX2to1_w1 mux_other_cout[6:1](c[7:2], cout0[6:1], cout1[6:1], c[6:1]);
RCA4 rca_last_0(sum0[31:28], cout0[7], a[31:28], b[31:28], 0);
RCA4 rca_last_1(sum1[31:28], cout1[7], a[31:28], b[31:28], 1);
MUX2to1_w4 mux_last_sum(sum[31:28], sum0[31:28], sum1[31:28], c[7]);
MUX2to1_w1 mux_last_cout(cout, cout0[7], cout1[7], c[7]);
endmodule |
module CSelA64(output [63:0] sum, output cout, input [63:0] a, b);
wire [63:0] sum0, sum1;
wire [15:1] c;
wire [15:0] cout0, cout1;
RCA4 rca0_0(sum0[3:0], cout0[0], a[3:0], b[3:0], 0);
RCA4 rca0_1(sum1[3:0], cout1[0], a[3:0], b[3:0], 1);
MUX2to1_w4 mux0_sum(sum[3:0], sum0[3:0], sum1[3:0], 0);
MUX2to1_w1 mux0_cout(c[1], cout0[0], cout1[0], 0);
RCA4 rca_other_0[14:1](sum0[59:4], cout0[14:1], a[59:4], b[59:4], 1'b0);
RCA4 rca_other_1[14:1](sum1[59:4], cout1[14:1], a[59:4], b[59:4], 1'b1);
MUX2to1_w4 mux_other_sum[14:1](sum[59:4], sum0[59:4], sum1[59:4], c[14:1]);
MUX2to1_w1 mux_other_cout[14:1](c[15:2], cout0[14:1], cout1[14:1], c[14:1]);
RCA4 rca_last_0(sum0[63:60], cout0[15], a[63:60], b[63:60], 0);
RCA4 rca_last_1(sum1[63:60], cout1[15], a[63:60], b[63:60], 1);
MUX2to1_w4 mux_last_sum(sum[63:60], sum0[63:60], sum1[63:60], c[15]);
MUX2to1_w1 mux_last_cout(cout, cout0[15], cout1[15], c[15]);
endmodule |
module tb_HA8;
wire [7:0] sum;
wire cout;
reg [7:0] a, b;
reg cin;
HA8 ha8(sum, cout, a, b);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b|%b", a, b, cout, sum);
end
initial
begin
a=8'b11111010; b=8'b11110000;
#40 a=8'b11111010; b=8'b11110001;
#40 a=8'b00111000; b=8'b10010000;
#40 a=8'b11000010; b=8'b10110000;
end
endmodule |
module tb_HA16;
wire [15:0] sum;
wire cout;
reg [15:0] a, b;
reg cin;
HA16 ha16(sum, cout, a, b);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b|%b", a, b, cout, sum);
end
initial
begin
a=16'b1111101011111010; b=16'b1111101011110000;
#40 a=16'b1111101000111000; b=16'b0000000011110001;
#40 a=16'b0011100000111000; b=16'b1001000011110001;
#40 a=16'b1111110001000010; b=16'b1011111100010000;
end
endmodule |
module tb_HA32;
wire [31:0] sum;
wire cout;
reg [31:0] a, b;
reg cin;
HA32 ha32(sum, cout, a, b);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b|%b", a, b, cout, sum);
end
initial
begin
a=32'b11111010111110000000011110001111; b=32'b01010101111100000000000011110001;
#100 a=32'b11111010001110001111111111111111; b=32'b00000000111100101010101001010001;
#100 a=32'b00111000001110010101010011101010; b=32'b10010000111100000111111100011101;
#100 a=32'b11111100010011111100000111110010; b=32'b10111111000100111100011100010100;
end
endmodule |
module tb_HA64;
wire [63:0] sum;
wire cout;
reg [63:0] a, b;
reg cin;
HA64 ha64(sum, cout, a, b);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b|%b", a, b, cout, sum);
end
initial
begin
a=64'b1111111101011111000000001111000111111010111110000000011110001111; b=64'b0101010111110000000111110101111100000000111100011110000011110001;
#200 a=64'b1111101011111000111110101111100000000111100011110000011110001111; b=64'b0101010111110111110101111100000000111100011110000000000011110001;
end
endmodule |
module tb_FA;
wire sum, cout;
reg a, b, cin;
FA fa(sum, cout, a, b, cin);
initial
begin
$display("a|b|cin||cout|sum");
end
initial
begin
$monitor("%b|%b|%b ||%b |%b ", a, b, cin, cout, sum);
end
initial
begin
a=0; b=0; cin=0;
#10 a=0; b=0; cin=1;
#10 a=0; b=1; cin=0;
#10 a=0; b=1; cin=1;
#10 a=1; b=0; cin=0;
#10 a=1; b=0; cin=1;
#10 a=1; b=1; cin=0;
#10 a=1; b=1; cin=1;
end
endmodule |
module tb_RCA8;
wire [7:0] sum;
wire cout;
reg [7:0] a, b;
reg cin;
reg [15:0] i;
RCA8 rca8(sum[7:0], cout, a[7:0], b[7:0]);
initial
begin
$display("a|b||cout|sum");
end
reg checkCarry;
reg [7:0] checkSum;
initial
begin
for(i=0; i<65536; i=i+1)
begin
#20; {checkCarry,checkSum} = a+b;
$display("a=%b|b=%b||carry=%b|sum=%b", a[7:0], b[7:0], cout, sum[7:0]);
$display("isCarryOK=%b|isSumOK=%b", ~(checkCarry^cout), ~|(checkSum^sum[7:0]));
$display("---------------------------");
{a[7:0], b[7:0]}=i;
end
end
endmodule |
module tb_RCA16;
wire [15:0] sum;
wire cout;
reg [15:0] a, b;
reg cin;
RCA16 rca16(sum[15:0], cout, a[15:0], b[15:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b |%b", a[15:0], b[15:0], cout, sum[15:0]);
end
initial
begin
a=16'b1010000010100000; b=16'b1010000010100000;
#10 a=16'b0101100011110100; b=16'b1111010011110100;
#10 a=16'b0000111100111101; b=16'b0000111100001111;
#10 a=16'b1100100011001010; b=16'b1100100011001010;
end
endmodule |
module tb_RCA32;
wire [31:0] sum;
wire cout;
reg [31:0] a, b;
reg cin;
RCA32 rca32(sum[31:0], cout, a[31:0], b[31:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b|%b", a[31:0], b[31:0], cout, sum[31:0]);
end
initial
begin
a='b10100000101000001111111111111111; b='b10100000101111111111111111100000;
#10 a='b01011000111111111111111111110100; b='b11110100111101001111111111111111;
#10 a='b11111111111111110000111100111101; b='b00001111000011111111111111111111;
#10 a='b11011111111111111110100011001010; b='b11001111111111111111100011001010;
end
endmodule |
module tb_RCA64;
wire [63:0] sum;
wire cout;
reg [63:0] a, b;
reg cin;
RCA64 rca64(sum[63:0], cout, a[63:0], b[63:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%d|%d||%d|%d", a[63:0], b[63:0], cout, sum[63:0]);
end
initial
begin
a=64'd998; b=64'd128;
#10 a=64'd9998; b=64'd9028;
#10 a=64'd09989998; b=64'd769028;
end
endmodule |
module RCA8(output [7:0] sum, output cout, input [7:0] a, b);
wire [7:1] c;
FA fa0(sum[0], c[1], a[0], b[0], 0);
FA fa[6:1](sum[6:1], c[7:2], a[6:1], b[6:1], c[6:1]);
FA fa31(sum[7], cout, a[7], b[7], c[7]);
endmodule |
module RCA16(output [15:0] sum, output cout, input [15:0] a, b);
wire [15:1] c;
FA fa0(sum[0], c[1], a[0], b[0], 0);
FA fa[14:1](sum[14:1], c[15:2], a[14:1], b[14:1], c[14:1]);
FA fa31(sum[15], cout, a[15], b[15], c[15]);
endmodule |
module RCA32(output [31:0] sum, output cout, input [31:0] a, b);
wire [31:1] c;
FA fa0(sum[0], c[1], a[0], b[0], 0);
FA fa[30:1](sum[30:1], c[31:2], a[30:1], b[30:1], c[30:1]);
FA fa31(sum[31], cout, a[31], b[31], c[31]);
endmodule |
module RCA64(output [63:0] sum, output cout, input [63:0] a, b);
wire [63:1] c;
FA fa0(sum[0], c[1], a[0], b[0], 0);
FA fa[62:1](sum[62:1], c[63:2], a[62:1], b[62:1], c[62:1]);
FA fa31(sum[63], cout, a[63], b[63], c[63]);
endmodule |
module tb_CLA8;
wire [7:0] sum;
wire cout;
reg [7:0] a, b;
reg cin;
CLA8 cla8(sum[7:0], cout, a[7:0], b[7:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b|%b", a[7:0], b[7:0], cout, sum[7:0]);
end
initial
begin
a=8'b11111010; b=8'b11110000;
#10 a=8'b11111010; b=8'b11110001;
#10 a=8'b00111000; b=8'b10010000;
#10 a=8'b11000010; b=8'b10110000;
end
endmodule |
module tb_CLA16;
wire [15:0] sum;
wire cout;
reg [15:0] a, b;
reg cin;
CLA16 cla16(sum[15:0], cout, a[15:0], b[15:0]);
initial
begin
$display("a |b ||cout|sum ");
end
initial
begin
$monitor("%b|%b||%b |%b", a[15:0], b[15:0], cout, sum[15:0]);
end
initial
begin
a=16'b1010000010100000; b=16'b1010000010100000;
#10 a=16'b0101100011110100; b=16'b1111010011110100;
#10 a=16'b0000111100111101; b=16'b0000111100001111;
#10 a=16'b1100100011001010; b=16'b1100100011001010;
end
endmodule |
module tb_CLA32;
wire [31:0] sum;
wire cout;
reg [31:0] a, b;
reg cin;
CLA32 cla32(sum[31:0], cout, a[31:0], b[31:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%d|%d||%d|%d", a[31:0], b[31:0], cout, sum[31:0]);
end
initial
begin
a='d999; b='d98999;
end
endmodule |
module tb_CLA64;
wire [63:0] sum;
wire cout;
reg [63:0] a, b;
reg cin;
CLA64 cla64(sum[63:0], cout, a[63:0], b[63:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%d|%d||%d|%d", a[63:0], b[63:0], cout, sum[63:0]);
end
initial
begin
a=64'd9991; b=64'd8810;
end
endmodule |
module BigCircle(output G, P, input Gi, Pi, GiPrev, PiPrev);
wire e;
and #(1) (e, Pi, GiPrev);
or #(1) (G, e, Gi);
and #(1) (P, Pi, PiPrev);
endmodule |
module SmallCircle(output Ci, input Gi);
buf #(1) (Ci, Gi);
endmodule |
module Square(output G, P, input Ai, Bi);
and #(1) (G, Ai, Bi);
xor #(2) (P, Ai, Bi);
endmodule |
module Triangle(output Si, input Pi, CiPrev);
xor #(2) (Si, Pi, CiPrev);
endmodule |
module KSA8(output [7:0] sum, output cout, input [7:0] a, b);
wire cin = 1'b0;
wire [7:0] c;
wire [7:0] g, p;
Square sq[7:0](g, p, a, b);
// first line of circles
wire [7:1] g2, p2;
SmallCircle sc0_0(c[0], g[0]);
BigCircle bc0[7:1](g2[7:1], p2[7:1], g[7:1], p[7:1], g[6:0], p[6:0]);
// second line of circle
wire [7:3] g3, p3;
SmallCircle sc1[2:1](c[2:1], g2[2:1]);
BigCircle bc1[7:3](g3[7:3], p3[7:3], g2[7:3], p2[7:3], g2[5:1], p2[5:1]);
// third line of circle
wire [7:7] g4, p4;
SmallCircle sc2[6:3](c[6:3], g3[6:3]);
BigCircle bc2_7(g4[7], p4[7], g3[7], p3[7], g3[3], p3[3]);
// fourth line of circle
SmallCircle sc3_7(c[7], g4[7]);
// last line - triangles
Triangle tr0(sum[0], p[0], cin);
Triangle tr[7:1](sum[7:1], p[7:1], c[6:0]);
// generate cout
buf #(1) (cout, c[7]);
endmodule |
module KSA16(output [15:0] sum, output cout, input [15:0] a, b);
wire cin = 1'b0;
wire [15:0] c;
wire [15:0] g, p;
Square sq[15:0](g, p, a, b);
// first line of circles
wire [15:1] g2, p2;
SmallCircle sc0_0(c[0], g[0]);
BigCircle bc0[15:1](g2[15:1], p2[15:1], g[15:1], p[15:1], g[14:0], p[14:0]);
// second line of circle
wire [15:3] g3, p3;
SmallCircle sc1[2:1](c[2:1], g2[2:1]);
BigCircle bc1[15:3](g3[15:3], p3[15:3], g2[15:3], p2[15:3], g2[13:1], p2[13:1]);
// third line of circle
wire [15:7] g4, p4;
SmallCircle sc2[6:3](c[6:3], g3[6:3]);
BigCircle bc2[15:7](g4[15:7], p4[15:7], g3[15:7], p3[15:7], g3[11:3], p3[11:3]);
// fourth line of circle
wire [15:15] g5, p5;
SmallCircle sc3[14:7](c[14:7], g4[14:7]);
BigCircle bc3_15(g5[15], p5[15], g4[15], p4[15], g4[7], p4[7]);
// fifth line of circle
SmallCircle sc4_15(c[15], g5[15]);
// last line - triangles
Triangle tr0(sum[0], p[0], cin);
Triangle tr[15:1](sum[15:1], p[15:1], c[14:0]);
// generate cout
buf #(1) (cout, c[15]);
endmodule |
module KSA32(output [31:0] sum, output cout, input [31:0] a, b);
wire cin = 1'b0;
wire [31:0] c;
wire [31:0] g, p;
Square sq[31:0](g, p, a, b);
// first line of circles
wire [31:1] g2, p2;
SmallCircle sc0_0(c[0], g[0]);
BigCircle bc0[31:1](g2[31:1], p2[31:1], g[31:1], p[31:1], g[30:0], p[30:0]);
// second line of circles
wire [31:3] g3, p3;
SmallCircle sc1[2:1](c[2:1], g2[2:1]);
BigCircle bc1[31:3](g3[31:3], p3[31:3], g2[31:3], p2[31:3], g2[29:1], p2[29:1]);
// third line of circles
wire [31:7] g4, p4;
SmallCircle sc2[6:3](c[6:3], g3[6:3]);
BigCircle bc2[31:7](g4[31:7], p4[31:7], g3[31:7], p3[31:7], g3[27:3], p3[27:3]);
// fourth line of circles
wire [31:15] g5, p5;
SmallCircle sc3[14:7](c[14:7], g4[14:7]);
BigCircle bc3[31:15](g5[31:15], p5[31:15], g4[31:15], p4[31:15], g4[23:7], p4[23:7]);
// fifth line of circles
wire [31:31] g6, p6;
SmallCircle sc4[30:15](c[30:15], g5[30:15]);
BigCircle bc4_31(g6[31], p6[31], g5[31], p5[31], g5[15], p5[15]);
// sixth line of circles
SmallCircle sc5_31(c[31], g6[31]);
// last line - triangless
Triangle tr0(sum[0], p[0], cin);
Triangle tr[31:1](sum[31:1], p[31:1], c[30:0]);
// generate cout
buf #(1) (cout, c[31]);
endmodule |
module KSA64(output [63:0] sum, output cout, input [63:0] a, b);
wire cin = 1'b0;
wire [63:0] c;
wire [63:0] g, p;
Square sq[63:0](g, p, a, b);
// first line of circles
wire [63:1] g2, p2;
SmallCircle sc0_0(c[0], g[0]);
BigCircle bc0[63:1](g2[63:1], p2[63:1], g[63:1], p[63:1], g[62:0], p[62:0]);
// second line of circles
wire [63:3] g3, p3;
SmallCircle sc1[2:1](c[2:1], g2[2:1]);
BigCircle bc1[63:3](g3[63:3], p3[63:3], g2[63:3], p2[63:3], g2[61:1], p2[61:1]);
// third line of circles
wire [63:7] g4, p4;
SmallCircle sc2[6:3](c[6:3], g3[6:3]);
BigCircle bc2[63:7](g4[63:7], p4[63:7], g3[63:7], p3[63:7], g3[59:3], p3[59:3]);
// fourth line of circles
wire [63:15] g5, p5;
SmallCircle sc3[14:7](c[14:7], g4[14:7]);
BigCircle bc3[63:15](g5[63:15], p5[63:15], g4[63:15], p4[63:15], g4[55:7], p4[55:7]);
// fifth line of circles
wire [63:31] g6, p6;
SmallCircle sc4[30:15](c[30:15], g5[30:15]);
BigCircle bc4[63:31](g6[63:31], p6[63:31], g5[63:31], p5[63:31], g5[47:15], p5[47:15]);
// sixth line of circles
wire [63:63] g7, p7;
SmallCircle sc5[62:31](c[62:31], g6[62:31]);
BigCircle bc4_63(g7[63], p7[63], g6[63], p6[63], g6[31], p6[31]);
// seventh line of circles
SmallCircle sc6(c[63], g7[63]);
// last line - triangles
Triangle tr0(sum[0], p[0], cin);
Triangle tr[63:1](sum[63:1], p[63:1], c[62:0]);
// generate cout
buf #(1) (cout, c[63]);
endmodule |
module tb_KSA8;
wire [7:0] sum;
wire cout;
reg [7:0] a, b;
reg cin;
KSA8 ksa8(sum[7:0], cout, a[7:0], b[7:0]);
initial
begin
$display("a |b ||cout|sum ");
end
initial
begin
$monitor("%b|%b||%b |%b", a[7:0], b[7:0], cout, sum[7:0]);
end
initial
begin
a=8'b10100000; b=8'b10100000;
#10 a=8'b01011000; b=8'b11110100;
#10 a=8'b00111101; b=8'b00001111;
#10 a=8'b11001010; b=8'b11001000;
#10 a=8'b10100110; b=8'b11110100;
#10 a=8'b11110011; b=8'b11001100;
#10 a=8'b11110011; b=8'b01010111;
end
endmodule |
module tb_KSA16;
wire [15:0] sum;
wire cout;
reg [15:0] a, b;
reg cin;
KSA16 ksa16(sum[15:0], cout, a[15:0], b[15:0]);
initial
begin
$display("a |b ||cout|sum ");
end
initial
begin
$monitor("%b|%b||%b |%b", a[15:0], b[15:0], cout, sum[15:0]);
end
initial
begin
a=16'b1010000010100000; b=16'b1010000010100000;
#10 a=16'b0101100011110100; b=16'b1111010011110100;
#10 a=16'b0000111100111101; b=16'b0000111100001111;
#10 a=16'b1100100011001010; b=16'b1100100011001010;
end
endmodule |
module tb_KSA32;
wire [31:0] sum;
wire cout;
reg [31:0] a, b;
reg cin;
KSA32 ksa32(sum[31:0], cout, a[31:0], b[31:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b|%b", a[31:0], b[31:0], cout, sum[31:0]);
end
initial
begin
a='b10100000101000001111111111111111; b='b10100000101111111111111111100000;
#10 a='b01011000111111111111111111110100; b='b11110100111101001111111111111111;
#10 a='b11111111111111110000111100111101; b='b00001111000011111111111111111111;
#10 a='b11011111111111111110100011001010; b='b11001111111111111111100011001010;
end
endmodule |
module tb_KSA64;
wire [63:0] sum;
wire cout;
reg [63:0] a, b;
reg cin;
KSA64 ksa64(sum[63:0], cout, a[63:0], b[63:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%d|%d||%d|%h", a[63:0], b[63:0], cout, sum[63:0]);
end
initial
begin
a=64'd998; b=64'd128;
#10 a=64'd9998; b=64'd9028;
#10 a=64'hfaaaaaaafaaaaaaa; b=64'hfaaaaaaadbbbbbbb;
end
endmodule |
module mm21_LEDMatrixTop(
input [7:0] io_in,
output [7:0] io_out
);
wire clock;
wire reset_async;
wire reset_sync;
// LED matrix wires
wire sclk;
wire mosi;
wire n_cs;
// 7-seg wires
wire up;
wire right;
wire down;
wire left;
assign clock = io_in[0];
assign reset_async = io_in[1];
// drive LED matrix
assign io_out[0] = sclk;
assign io_out[1] = mosi;
assign io_out[5] = n_cs;
// use lower 7-seg LEDs for animation
assign io_out[6] = up;
assign io_out[2] = right;
assign io_out[3] = down;
assign io_out[4] = left;
assign io_out[7] = 1'b1;
mm21_AsyncReset async_reset_inst(
.clock(clock),
.reset_async(reset_async),
.reset_sync(reset_sync)
);
mm21_LEDMatrixDriver ledmatrix_driver_inst(
.clock(clock),
.reset(reset_sync),
.sclk(sclk),
.mosi(mosi),
.n_cs(n_cs)
);
mm21_SevenSeg sevenseg_inst(
.clock(clock),
.reset(reset_sync),
.up(up),
.right(right),
.down(down),
.left(left)
);
endmodule |
module moonbase_cpu_4bit #(parameter MAX_COUNT=1000) (input [7:0] io_in, output [7:0] io_out);
//
// External interfacex
//
// external address latch
// the external 7 bit address latch is loaded from io_out[6:0] when io_out[7] is 1
// external SRAM (eg MWS5101AEL3):
// the external RAM always produces what is at the latch's addresses on io_in[5:2]
// the external SRAM is written when io_out[7] is 0 and io_out[5] is 0
// io_out[6] can be used as an extra address bit to split the address space between
// code (1) and data (0) to use a 256-nibble sram (woot!)
// external devices:
// external devices can be read from io_in[7:6] (at address pointed to by the address latch)
// external devices can be written from io_out[3:0] (at address pointed to by the address latch)
// when io_out[7] is 0 and io_out[4] is 0
//
//
// SRAM address space (data accesses):
// 0-127 external
// 128-131 internal (internal ram cells, for filling up the die :-)
//
localparam N_LOCAL_RAM = 24;
wire clk = io_in[0];
wire reset = io_in[1];
wire [3:0]ram_in = io_in[5:2];
wire [1:0]data_in = io_in[7:6];
reg strobe_out; // address strobe - designed to be wired to a 7 bit latch and a MWS5101AEL3
reg write_data_n; // write enable for data
reg write_ram_n; // write enable for ram
reg addr_pc;
reg data_pc;
wire [6:0]data_addr = ((r_tmp[3]?r_y[6:0]:r_x[6:0])+{4'b000, r_tmp[2:0]});
wire is_local_ram = (r_tmp[3]?r_y[7]:r_x[7]);
wire write_local_ram = is_local_ram & !write_ram_n;
wire [$clog2(N_LOCAL_RAM)-1:0]local_ram_addr = data_addr[$clog2(N_LOCAL_RAM)-1:0];
wire [6:0]addr_out = addr_pc ? r_pc : data_addr; // address out mux (PC or X/Y+off)
assign io_out = {strobe_out, strobe_out? addr_out : {data_pc, write_ram_n|is_local_ram, write_data_n, r_a}}; // mux address and data out
reg [6:0]r_pc, c_pc; // program counter // actual flops in the system
reg [7:0]r_x, c_x; // x index register // by convention r_* is a flop, c_* is the combinatorial that feeds it
reg [7:0]r_y, c_y; // y index register
reg [3:0]r_a, c_a; // accumulator
reg r_c, c_c; // carry flag
reg [3:0]r_tmp2, c_tmp2;// operand temp (high)
reg [3:0]r_tmp, c_tmp;// operand temp (low)
reg [6:0]r_s0, c_s0; // call stack
reg [6:0]r_s1, c_s1;
reg [6:0]r_s2, c_s2;
reg [6:0]r_s3, c_s3;
//
// phase:
// 0 - instruction fetch addr
// 1 - instruction fetch data
// 2 - const fetch addr
// 3 - const fetch data
// 4 - data/const fetch addr
// 5 - data/const fetch data
// 6 - execute/data store addr
// 7 - data store data (might not do this)
//
reg [2:0]r_phase, c_phase; // CPU internal state machine
// instructions
//
// 0 v: add a, v(x/y) - sets C
// 1 v: sub a, v(x/y) - sets C
// 2 v: or a, v(x/y)
// 3 v: and a, v(x/y)
// 4 v: xor a, v(x/y)
// 5 v: mov a, v(x/y)
// 6 v: movd a, v(x/y)
// 7 0: swap x, y
// 1: add a, c
// 2: mov x.l, a
// 3: ret
// 4: add y, a
// 5: add x, a
// 6: add y, #1
// 7: add x, #1
// 8 v: mov a, #v
// 9 v: add a, #v
// a v: movd v(x/y), a
// b v: mov v(x/y), a
// c h l: mov x, #hl
// d h l: jne a/c, hl if h[3] the test c otherwise test a
// e h l: jeq a/c, hl if h[3] the test c otherwise test a
// f h l: jmp/call hl
//
// Memory access - addresses are 7 bits - v(X/y) is a 3-bit offset v[2:0]
// if v[3] it's Y+v[2:0]
// if !v[3] it's X+v[2:0]
//
// The general idea is that X normally points to a bank of in sram 8 'registers',
// a bit like an 8051's r0-7, while X is a more general index register
// (but you can use both if you need to do some copying)
//
reg [3:0]r_ins, c_ins; // fetched instruction
wire [4:0]c_add = {1'b0, r_a}+{1'b0, r_tmp}; // ALUs
wire [4:0]c_sub = {1'b0, r_a}-{1'b0, r_tmp};
wire [6:0]c_i_add = (r_tmp[0]?r_x:r_y)+(r_tmp[1]?7'b1:{3'b0, r_a});
wire [6:0]c_pc_inc = r_pc+1;
reg [3:0] r_local_ram[0:N_LOCAL_RAM-1];
wire [3:0] local_ram = r_local_ram[local_ram_addr];
always @(posedge clk)
if (write_local_ram)
r_local_ram[local_ram_addr] <= r_a;
always @(*) begin
c_ins = r_ins;
c_x = r_x;
c_y = r_y;
c_a = r_a;
c_s0 = r_s0;
c_s1 = r_s1;
c_s2 = r_s2;
c_s3 = r_s3;
c_tmp = r_tmp;
c_tmp2 = r_tmp2;
c_pc = r_pc;
c_c = r_c;
write_data_n = 1;
write_ram_n = 1;
addr_pc = 'bx;
data_pc = 'bx;
if (reset) begin // reset clears the state machine and sets PC to 0
c_pc = 0;
c_phase = 0;
strobe_out = 1;
end else
case (r_phase) // synthesis full_case parallel_case
0: begin // 0: address latch instruction PC
strobe_out = 1;
addr_pc = 1;
c_phase = 1;
end
1: begin // 1: read data in
strobe_out = 0;
data_pc = 1;
c_ins = ram_in;
c_pc = c_pc_inc;
c_phase = 2;
end
2: begin
strobe_out = 1; // 2: address latch operand PC
addr_pc = 1;
c_phase = 3;
end
3: begin
strobe_out = 0; // 3: read operand
c_tmp = ram_in;
c_pc = c_pc_inc;
data_pc = 1;
case (r_ins) // synthesis full_case parallel_case
7, 8, 9, 10, 11: c_phase = 6;// some instructions don't have a 2nd fetch
default: c_phase = 4;
endcase
end
4: begin // 4 address latch for next operand
strobe_out = 1;
addr_pc = r_ins[3:2] == 3; // some instructions read a 2nd operand, the rest the come here read a memory location
c_phase = 5;
end
5: begin // 5 read next operand
strobe_out = 0;
data_pc = r_ins[3:2] == 3;
c_tmp2 = r_tmp; // low->high for 2 byte cases
c_tmp = (r_ins[3:1] == 3?{2'b0,data_in}:is_local_ram&&r_ins[3:2] != 3?local_ram:ram_in); // read the actial data, movd comes from upper bits
if (r_ins[3:2] == 3) // if we fetched from PC increment it
c_pc = c_pc_inc;
c_phase = 6;
end
6: begin // 6 execute stage
strobe_out = r_ins[3:1] == 5; // if writing to anything latch address
addr_pc = 0;
c_phase = 0; // if not writing go back
case (r_ins)// synthesis full_case parallel_case
0, // add a, v(x)
9: begin c_c = c_add[4]; c_a = c_add[3:0]; end // add a, #v
1: begin c_c = c_sub[4]; c_a = c_sub[3:0]; end // sub a, v(x)
2: c_a = r_a|r_tmp; // or a, v(x)
3: c_a = r_a&r_tmp; // sub a, v(x)
4: c_a = r_a^r_tmp; // xor a, v(x)
5, // mov a, v(x)
6, // movd a, v(x)
8: c_a = r_tmp; // mov a, #v
7: case (r_tmp) // synthesis full_case parallel_case
0: begin c_x = r_y; c_y = r_x; end // 0 swap y, x
1: c_a = r_a+{3'b000, r_c}; // 1 add a, c
2: c_x[3:0] = r_a; // 2 mov x.l, a
3: begin // 3 ret
c_pc = r_s0;
c_s0 = r_s1;
c_s1 = r_s2;
c_s2 = r_s3;
end
4: c_y = c_i_add; // 4 add y, a
5: c_x = c_i_add; // 5 add x, a
6: c_y = c_i_add; // 6 add y, #1
7: c_x = c_i_add; // 7 add y, #1
default: ;
endcase
10, // movd v(x), a
11: c_phase = 7; // mov v(x), a
12: c_x = {r_tmp2, r_tmp}; // mov x, #VV
13: c_pc = (r_tmp2[3]?!r_c : r_a != 0) ? {r_tmp2[2:0], r_tmp} : r_pc; // jne a/c, VV
14: c_pc = (r_tmp2[3]? r_c : r_a == 0) ? {r_tmp2[2:0], r_tmp} : r_pc; // jeq a/c, VV
15: begin c_pc = {r_tmp2[2:0], r_tmp}; // jmp VV
if (r_tmp2[3]) begin // call
c_s0 = r_pc;
c_s1 = r_s0;
c_s2 = r_s1;
c_s3 = r_s2;
end
end
endcase
end
7: begin // 7 write data stage - assert appropriate write strobe
strobe_out = 0;
data_pc = 0;
write_data_n = r_ins[0];
write_ram_n = ~r_ins[0];
c_phase = 0;
end
endcase
end
always @(posedge clk) begin
r_a <= c_a;
r_c <= c_c;
r_x <= c_x;
r_y <= c_y;
r_ins <= c_ins;
r_tmp <= c_tmp;
r_tmp2 <= c_tmp2;
r_pc <= c_pc;
r_phase <= c_phase;
r_s0 <= c_s0;
r_s1 <= c_s1;
r_s2 <= c_s2;
r_s3 <= c_s3;
end
endmodule |
module Asma_Mohsin_conv_enc_core(// Inputs
input [7:0]io_in,
// Output
output [7:0]io_out
);
parameter [4:0] POLY_1 = 5'b10111 ;
parameter [4:0] POLY_2 = 5'b11001 ;
// Inputs
wire clk ;
wire rst_n ;
wire data_valid ;
wire d_in ;
assign clk = io_in[0];
assign rst_n=io_in[1];
assign data_valid=io_in[2];
assign d_in=io_in[3];
// Output
//output [1:0] enc_dout ;
reg [4:0] shift_reg ;
reg [1:0] codeword ;
wire [1:0] enc_dout ;
// Shift Input Data in 5 bits lenght register
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
shift_reg <= 5'd0 ;
else if(data_valid)
shift_reg <= {d_in, shift_reg[4:1]} ;
else
shift_reg <= 5'd0 ;
end
always @(shift_reg)
begin
codeword[0] = ^(POLY_2 & shift_reg) ;
codeword[1] = ^(POLY_1 & shift_reg) ;
end
assign io_out = codeword ;
endmodule |
module moonbase_cpu_8bit #(parameter MAX_COUNT=1000) (input [7:0] io_in, output [7:0] io_out);
//
// External interface
//
// external address latch
// the external 12 bit address latch is loaded [5:0] from io_out[5:0] when io_out[7:6] is 10
// the external 12 bit address latch is loaded [11:6] from io_out[5:0] when io_out[7:6] is 11
// external SRAM (eg MWS5101AEL3) when io_out[7] is 0
// which nibble is from io_out[6]
// the external RAM always produces what is at the latch's addresses on io_in[5:2] when
// the external SRAM is written when io_out[7] is 0 and io_out[5] is 0
// io_out[6] can be used as an extra address bit to split the address space between
// code (1) and data (0) to use a 256-nibble sram (woot!)
// external devices when io_out[7] is 0:
// which nibble is from io_out[6]
// external devices can be read from io_in[7:6] (at address pointed to by the address latch)
// external devices can be written from io_out[3:0] (at address pointed to by the address latch)
// when io_out[4] is 0
//
// SRAM address space (data accesses):
// 0-0xfff external
// 0x1000-131 internal (internal ram cells, for filling up the die :-)
//
localparam N_LOCAL_RAM = 4;
wire clk = io_in[0];
wire reset = io_in[1];
wire [3:0]ram_in = io_in[5:2];
wire [1:0]data_in = io_in[7:6];
reg strobe_out; // address strobe - designed to be wired to a 7 bit latch and a MWS5101AEL3
reg nibble; // address/data nibble
reg write_data_n; // write enable for data
reg write_ram_n; // write enable for ram
reg addr_pc;
wire [11:0]data_addr = ((r_v[3]?r_y[11:0]:r_x[11:0])+{8'b000, r_v[2:0]});
wire is_local_ram = (r_v[3]?r_y[12]:r_x[12]);
wire write_local_ram = is_local_ram & !write_ram_n;
wire write_ext_ram_n = is_local_ram | write_ram_n;
wire [$clog2(N_LOCAL_RAM)-1:0]local_ram_addr = data_addr[$clog2(N_LOCAL_RAM)-1:0];
wire [11:0]addr_out = addr_pc ? r_pc : data_addr; // address out mux (PC or X/Y+off)
wire [5:0]addr_out_mux = (nibble?addr_out[11:6]:addr_out[5:0]); // mux-d by portion
assign io_out = {strobe_out, nibble, strobe_out? addr_out_mux : {write_ext_ram_n, write_data_n, !nibble?r_a[7:4]:r_a[3:0]}}; // mux address and data out
reg [11:0]r_pc, c_pc; // program counter // actual flops in the system
reg [12:0]r_x, c_x; // x index register // by convention r_* is a flop, c_* is the combinatorial that feeds it
reg [12:0]r_y, c_y; // y index register
reg [7:0]r_a, c_a; // accumulator
reg [7:0]r_b, c_b; // temp accumulator
reg r_c, c_c; // carry flag
reg [3:0]r_h, c_h; // operand temp (high)
reg [3:0]r_l, c_l; // operand temp (low)
reg [4:0]r_ee, c_ee; // extended const (bits 12:4)
reg [3:0]r_v, c_v; // operand temp (low)
reg [11:0]r_s0, c_s0; // call stack
reg [11:0]r_s1, c_s1;
//
// phase:
// 0 - instruction fetch addr
// 1 - instruction fetch dataL ins
// 2 - instruction fetch dataH V
// 4 - data/const fetch addr
// 5 - data/const fetch dataL tmp
// 6 - data/const fetch dataH tmp2
// 8 - execute/data store addr
// 9 - data store dataL (might not do this)
// a - data store dataH (might not do this)
//
reg [3:0]r_phase, c_phase; // CPU internal state machine
// instructions
//
// Registers: a,b 8 bit, x,y 13 bits, pc 12 bits
//
// 0v: add a, v(x/y) - sets C
// 1v: sub a, v(x/y) - sets C
// 2v: or a, v(x/y)
// 3v: and a, v(x/y)
// 4v: xor a, v(x/y)
// 5v: mov a, v(x/y)
// 6v: movd a, v(x/y)
// 70: add a, c
// 71: inc a
// 72: swap x, y
// 73: ret
// 74: add y, a
// 75: add x, a
// 76: inc y
// 77: inc x
// 78: mov a, y
// 79: mov a, x
// 7a: mov b, a
// 7b: swap b, a
// 7c: mov y, a
// 7d: mov x, a
// 7e: clr a
// 7f: mov a, pc
// 8v: nop
// 9v: nop
// av: movd v(x/y), a
// bv: mov v(x/y), a
// cv: nop
// dv: nop
// ev: nop
// f0 HL: mov a, #HL
// f1 HL: add a, #HL
// f2 HL: mov y, #EELL
// f3 HL: mov x, #EEHL
// f4 HL: jne a/c, EEHL if EE[4] then test c otherwise test a
// f5 HL: jeq a/c, EEHL if EE[4] then test c otherwise test a
// f6 HL: jmp/call EEHL if EE[4] call else jmp
// f7 HL: nop
//
// Memory access - addresses are 7 bits - v(X/y) is a 3-bit offset v[2:0]
// if v[3] it's Y+v[2:0]
// if !v[3] it's X+v[2:0]
//
// The general idea is that X normally points to a bank of in sram 8 'registers',
// a bit like an 8051's r0-7, while X is a more general index register
// (but you can use both if you need to do some copying)
//
reg [3:0]r_ins, c_ins; // fetched instruction
wire [8:0]c_add = {1'b0, r_a}+{1'b0, r_h, r_l}; // ALUs
wire [8:0]c_sub = {1'b0, r_a}-{1'b0, r_h, r_l};
wire [12:0]c_i_add = {r_v[0]?r_x[12]:r_y[12], (r_v[0]?r_x[11:0]:r_y[11:0])+(r_v[1]?12'b1:{4'b0,r_a})};
wire [11:0]c_pc_inc = r_pc+1;
wire [7:0]c_a_inc = r_a + {7'b0, r_c|r_v[0]};
reg [7:0]r_local_ram[0:N_LOCAL_RAM-1];
wire [7:0]local_ram = r_local_ram[local_ram_addr];
always @(posedge clk)
if (write_local_ram)
r_local_ram[local_ram_addr] <= r_a;
always @(*) begin
c_ins = r_ins;
c_x = r_x;
c_y = r_y;
c_a = r_a;
c_b = r_b;
c_s0 = r_s0;
c_s1 = r_s1;
c_l = r_l;
c_h = r_h;
c_ee = r_ee;
c_pc = r_pc;
c_c = r_c;
c_v = r_v;
write_data_n = 1;
write_ram_n = 1;
addr_pc = 'bx;
nibble = 'bx;
if (reset) begin // reset clears the state machine and sets PC to 0
c_y = 13'h1000; // point at internal sram
c_pc = 0;
c_phase = 0;
strobe_out = 1;
end else
case (r_phase) // synthesis full_case parallel_case
0: begin // 0: address latch instruction PC
strobe_out = 1;
addr_pc = 1;
nibble = 0;
c_phase = 1;
end
1: begin // 0: address latch instruction PC
strobe_out = 1;
addr_pc = 1;
nibble = 1;
c_phase = 2;
end
2: begin // 1: read data in r_ins
strobe_out = 0;
c_ins = ram_in;
nibble = 0;
c_phase = 3;
end
3: begin // 3: read data in r_v
strobe_out = 0;
c_v = ram_in;
nibble = 1;
c_pc = c_pc_inc;
case (r_ins) // synthesis full_case parallel_case
7, 8, 9, 10, 11, 12, 13, 14: c_phase = 12;// some instructions don't have a 2nd fetch
default: c_phase = 4;
endcase
end
4: begin // 4 address latch for next operand
strobe_out = 1;
addr_pc = r_ins[3:2] == 3; // some instructions read a 2nd operand, the rest the come here read a memory location
nibble = 0;
c_phase = r_ins[3:2] != 3 && is_local_ram ? 7 : 5;
end
5: begin // 4 address latch for next operand
strobe_out = 1;
addr_pc = r_ins[3:2] == 3; // some instructions read a 2nd operand, the rest the come here read a memory location
nibble = 1;
c_phase = 6;
end
6: begin // 5 read next operand r_hi
strobe_out = 0;
nibble = 0;
c_h = ((r_ins[3:1] == 3)? 4'b0 : ram_in);
c_phase = 7;
end
7: begin // 5 read next operand r_lo
strobe_out = 0;
nibble = 1;
if (is_local_ram&&r_ins != 4'hf) begin
c_h = local_ram[7:4];
c_l = local_ram[3:0];
end else begin
c_l = ((r_ins[3:1] == 3)?{2'b0,data_in}:ram_in); // read the actial data, movd comes from upper bits
end
if (r_ins == 4'hf) // if we fetched from PC increment it
c_pc = c_pc_inc;
c_phase = (r_ins == 4'hf && r_v[3:1] != 0) ? 8: 12;
end
8: begin // 4 address latch for next operand
strobe_out = 1;
addr_pc = 1;
nibble = 0;
c_phase = 9;
end
9: begin // 4 address latch for next operand
strobe_out = 1;
addr_pc = 1;
nibble = 1;
c_phase = 10;
end
10: begin // 5 read next operand r_hi
strobe_out = 0;
nibble = 0;
c_ee[4] = ram_in[0];
c_phase = 11;
end
11: begin // 5 read next operand r_lo
strobe_out = 0;
nibble = 1;
c_ee[3:0] = ram_in;
c_pc = c_pc_inc;
c_phase = 12;
end
12: begin // 6 execute stage
strobe_out = r_ins[3:1] == 5; // if writing to anything latch address
addr_pc = 0;
c_phase = 0; // if not writing go back
nibble = 0;
case (r_ins)// synthesis full_case parallel_case
0: begin c_c = c_add[8]; c_a = c_add[7:0]; end // add a, v(x)
1: begin c_c = c_sub[8]; c_a = c_sub[7:0]; end // sub a, v(x)
2: c_a = r_a|{r_h, r_l}; // or a, v(x)
3: c_a = r_a&{r_h, r_l}; // sub a, v(x)
4: c_a = r_a^{r_h, r_l}; // xor a, v(x)
5, // mov a, v(x)
6: c_a = {r_h, r_l}; // movd a, v(x)
7: case (r_v) // synthesis full_case parallel_case
0: c_a = c_a_inc; // 0 add a, c
1: c_a = c_a_inc; // 1 inc a
2: begin c_x = r_y; c_y = r_x; end // 2 swap y, x
3: begin // 3 ret
c_pc = r_s0;
c_s0 = r_s1;
end
4: c_y = c_i_add; // 4 add y, a
5: c_x = c_i_add; // 5 add x, a
6: c_y = c_i_add; // 6 add y, #1
7: c_x = c_i_add; // 7 add y, #1
8: c_a = r_y[7:0]; // 8 mov a, y
9: c_a = r_x[7:0]; // 9 mov a, x
10: c_b = r_a; // a mov b, a
11: begin c_b = r_a; c_a = r_b; end // b swap b, a
12: c_y[7:0] = r_a; // c mov y, a
13: c_x[7:0] = r_a; // d mov x, a
14: c_a = 0; // e clr a
15: c_a = r_pc; // f mov a, pc
default: ;
endcase
8: ; // noop
9: ; // noop
10, // movd v(x), a
11: c_phase = is_local_ram ? 15:13; // mov v(x), a
12: ; // noop
13: ; // noop
14: ; // noop
15: case (r_v) // synthesis full_case parallel_case
0: c_a = {r_h, r_l}; // mov a, #HL
1: begin c_c = c_add[8]; c_a = c_add[7:0]; end // add a, #HL
2: c_y = {r_ee, r_h, r_l}; // mov y, #VV
3: c_x = {r_ee, r_h, r_l}; // mov x, #VV
4: c_pc = (r_ee[4]?!r_c : r_a != 0) ? {r_ee[3:0], r_h, r_l} : r_pc; // jne a/c, VV
5: c_pc = (r_ee[4]? r_c : r_a == 0) ? {r_ee[3:0], r_h, r_l} : r_pc; // jeq a/c, VV
6: begin c_pc = {r_ee[3:0], r_h, r_l}; // jmp VV
if (r_ee[4]) begin // call
c_s0 = r_pc;
c_s1 = r_s0;
end
end
default: ;
endcase
endcase
end
13: begin
strobe_out = 1;
addr_pc = 0;
nibble = 1;
c_phase = 14;
end
14: begin // 7 write data stage - assert appropriate write strobe
strobe_out = 0;
write_data_n = r_ins[0];
write_ram_n = ~r_ins[0];
nibble = 0;
c_phase = 15;
end
15: begin // 7 write data stage - assert appropriate write strobe
strobe_out = 0;
nibble = 1;
write_data_n = r_ins[0];
write_ram_n = ~r_ins[0];
c_phase = 0;
end
endcase
end
always @(posedge clk) begin
r_a <= c_a;
r_b <= c_b;
r_c <= c_c;
r_x <= c_x;
r_y <= c_y;
r_ins <= c_ins;
r_v <= c_v;
r_l <= c_l;
r_h <= c_h;
r_ee <= c_ee;
r_pc <= c_pc;
r_phase <= c_phase;
r_s0 <= c_s0;
r_s1 <= c_s1;
end
endmodule |
module pic10_core(input clock, reset, output [3:0] prog_adr, input [11:0] prog_data, input [3:0] gpi, output reg [7:0] gpo);
wire [7:0] reg_rdata;
reg [7:0] result;
reg [7:0] w;
reg [1:0] phase;
reg [3:0] pc;
reg [3:0] next_pc;
reg skip, next_skip, next_skip_zero;
reg reg_we, w_we;
assign prog_adr = pc;
always @(posedge clock, negedge reset)
begin
if (!reset) begin
phase <= 2'b0;
end else begin
phase <= phase + 1'b1;
end
end
always @(posedge clock, negedge reset)
begin
if (!reset) begin
pc <= 1'b0;
next_pc <= 1'b0;
w <= 1'b0;
next_skip <= 1'b0;
end else begin
if (phase == 0) begin
skip <= next_skip;
next_skip <= 1'b0;
next_skip_zero <= 1'b0;
reg_we <= 1'b0;
w_we <= 1'b0;
pc <= next_pc;
end else if (phase == 1) begin
next_pc <= prog_adr + 1'b1;
if (prog_data[11:10] == 2'b00) begin
reg_we <= prog_data[5];
w_we <= ~prog_data[5];
case (prog_data[9:6])
4'b0000: result <= w;
4'b0001: result <= 0;
4'b0010: result <= reg_rdata - w;
4'b0011: result <= reg_rdata - 1;
4'b0100: result <= reg_rdata | w;
4'b0101: result <= reg_rdata & w;
4'b0110: result <= reg_rdata ^ w;
4'b0111: result <= reg_rdata + w;
4'b1000: result <= reg_rdata;
4'b1001: result <= ~reg_rdata;
4'b1010: result <= reg_rdata + 1;
4'b1011: begin result <= reg_rdata - 1; next_skip_zero <= 1'b1; end
4'b1111: begin result <= reg_rdata + 1; next_skip_zero <= 1'b1; end
endcase
end else if (prog_data[11:10] == 2'b01) begin
reg_we <= 1'b1;
case (prog_data[9:8])
2'b00: result <= reg_rdata & ~(1 << prog_data[7:5]);
2'b01: result <= reg_rdata | (1 << prog_data[7:5]);
2'b10: begin result <= reg_rdata; next_skip <= ~reg_rdata[prog_data[7:5]]; end
2'b11: begin result <= reg_rdata; next_skip <= reg_rdata[prog_data[7:5]]; end
endcase
end else if (prog_data[11:10] == 2'b10) begin
// no call, return
if (!skip)
next_pc <= prog_data[3:0];
end else if (prog_data[11:10] == 2'b11) begin
w_we <= 1'b1;
case (prog_data[9:8])
2'b00: result <= prog_data[7:0];
2'b01: result <= prog_data[7:0] | w;
2'b10: result <= prog_data[7:0] & w;
2'b11: result <= prog_data[7:0] ^ w;
endcase
end
end else if (phase == 2) begin
if (next_skip_zero) begin
next_skip <= (result == 0);
end
if (!skip) begin
if (w_we)
w <= result;
end
end else if (phase == 3) begin
// ...
end
end
end
wire [2:0] reg_addr = prog_data[2:0];
always @(posedge clock) begin
if (reg_we && regf_we && (reg_addr == 7))
gpo <= result;
end
wire [7:0] regf_data[0:7];
assign regf_data[6] = {4'b0000, gpi};
assign regf_data[7] = gpo;
assign reg_rdata = regf_data[reg_addr];
// register file
wire regf_we = phase[1] & !skip;
generate
genvar ii, jj;
for (ii = 0; ii < 6; ii = ii + 1'b1) begin:word
wire word_we;
sky130_fd_sc_hd__and3_1 word_we_i ( // make sure this is really glitch free
.A(reg_addr[2:0] == ii),
.B(regf_we),
.C(reg_we),
.X(word_we)
);
for (jj = 0; jj < 8; jj = jj + 1'b1) begin:bits
sky130_fd_sc_hd__dlrtp_1 rfbit_i (
.GATE(word_we),
.RESET_B(reset),
.D(result[jj]),
.Q(regf_data[ii][jj])
);
end
end
endgenerate
endmodule |
module sky130_fd_sc_hd__dlrtp_1(input GATE, RESET_B, D, output reg Q);
always @*
if (~RESET_B)
Q <= 0;
else if (GATE)
Q <= D;
endmodule |
module sky130_fd_sc_hd__dlxtp_1(input GATE, D, output reg Q);
always @*
if (GATE)
Q <= D;
endmodule |
module sky130_fd_sc_hd__and3_1(input A, B, C, output X);
assign X = A & B & C;
endmodule |
module pic_progmem(input clock, write_data, write_strobe, input [3:0] adr, output [11:0] rdata);
localparam K = 16;
// the program logic
reg [27:0] write_sr;
always @(posedge clock)
write_sr <= {write_data, write_sr[27:1]};
wire [11:0] data[0:K-1];
generate
genvar ii, jj;
for (ii = 0; ii < K; ii = ii + 1'b1) begin:word
for (jj = 0; jj < 12; jj = jj + 1'b1) begin:bits
sky130_fd_sc_hd__dlxtp_1 rfbit_i (
.GATE(write_sr[ii + 12] && write_strobe),
.D(write_sr[jj]),
.Q(data[ii][jj])
);
end
end
endgenerate
assign rdata = data[adr];
endmodule |
module tiny_kinda_pic(input [7:0] io_in, output [7:0] io_out);
wire clk = io_in[0];
wire reset = io_in[1];
wire [3:0] prog_adr;
wire [11:0] prog_data;
pic10_core pic_i (
.clock(clk),
.reset(reset),
.prog_adr(prog_adr),
.prog_data(prog_data),
.gpi(io_in[7:4]),
.gpo(io_out)
);
pic_progmem progmem_i (
.clock(clk),
.write_strobe(io_in[2]),
.write_data(io_in[3]),
.adr(prog_adr),
.rdata(prog_data)
);
endmodule |
module user_module_349952820323025491(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17 = 1'b1;
wire net18 = 1'b0;
wire net19 = 1'b0;
wire net20 = 1'b0;
wire net21;
wire net22 = 1'b0;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28 = 1'b0;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34 = 1'b0;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41 = 1'b0;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47 = 1'b0;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net11;
assign io_out[3] = net12;
assign io_out[4] = net13;
assign io_out[5] = net14;
assign io_out[6] = net15;
assign io_out[7] = net16;
xor_cell gate43 (
.a (net21),
.b (net22),
.out (net9)
);
and_cell gate44 (
.a (net22),
.b (net21),
.out (net23)
);
or_cell gate45 (
.a (net23),
.b (net24),
.out (net25)
);
and_cell gate46 (
.a (net1),
.b (net5),
.out (net24)
);
xor_cell gate47 (
.a (net1),
.b (net5),
.out (net21)
);
xor_cell gate48 (
.a (net26),
.b (net25),
.out (net10)
);
xor_cell gate52 (
.a (net2),
.b (net6),
.out (net26)
);
xor_cell gate7 (
.a (net27),
.b (net28),
.out (net11)
);
and_cell gate8 (
.a (net28),
.b (net27),
.out (net29)
);
or_cell gate9 (
.a (net29),
.b (net30),
.out (net31)
);
and_cell gate10 (
.a (net3),
.b (net7),
.out (net30)
);
xor_cell gate11 (
.a (net3),
.b (net7),
.out (net27)
);
xor_cell gate12 (
.a (net32),
.b (net31),
.out (net12)
);
xor_cell gate16 (
.a (net4),
.b (net8),
.out (net32)
);
xor_cell gate17 (
.a (net33),
.b (net34),
.out (net13)
);
and_cell gate18 (
.a (net34),
.b (net33),
.out (net35)
);
or_cell gate19 (
.a (net35),
.b (net36),
.out (net37)
);
and_cell gate20 (
.a (net1),
.b (net5),
.out (net36)
);
xor_cell gate21 (
.a (net1),
.b (net5),
.out (net33)
);
xor_cell gate22 (
.a (net38),
.b (net37),
.out (net14)
);
xor_cell gate26 (
.a (net2),
.b (net39),
.out (net38)
);
xor_cell gate27 (
.a (net40),
.b (net41),
.out (net15)
);
and_cell gate28 (
.a (net41),
.b (net40),
.out (net42)
);
or_cell gate29 (
.a (net42),
.b (net43),
.out (net44)
);
and_cell gate30 (
.a (net3),
.b (net7),
.out (net43)
);
xor_cell gate31 (
.a (net3),
.b (net7),
.out (net40)
);
xor_cell gate32 (
.a (net45),
.b (net44),
.out (net16)
);
xor_cell gate36 (
.a (net4),
.b (net46),
.out (net45)
);
xor_cell gate37 (
.a (net5),
.b (net6),
.out (net39)
);
xor_cell gate38 (
.a (net7),
.b (net8),
.out (net46)
);
endmodule |
module github_com_proppy_tt02_xls_popcount(
input wire [7:0] io_in,
output wire [7:0] io_out
);
user_module user_module0(io_in, io_out);
endmodule |
module user_module_349934460979905106(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11 = 1'b0;
wire net12 = 1'b1;
wire net13 = 1'b1;
wire net14;
wire net15;
wire net16 = 1'b0;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46 = 1'b1;
wire net47;
wire net48 = 1'b1;
wire net49;
wire net50;
wire net51;
wire net52 = 1'b0;
wire net53;
wire net54;
wire net55 = 1'b1;
wire net56;
wire net57;
wire net58 = 1'b1;
wire net59;
wire net60;
wire net61 = 1'b1;
wire net62;
wire net63;
wire net64 = 1'b1;
wire net65;
wire net66;
wire net67 = 1'b0;
wire net68;
wire net69;
wire net70 = 1'b0;
wire net71;
wire net72;
wire net73 = 1'b0;
wire net74;
wire net75;
wire net76 = 1'b0;
wire net77;
wire net78;
wire net79 = 1'b1;
wire net80;
wire net81;
wire net82 = 1'b1;
wire net83;
wire net84;
wire net85;
wire net86 = 1'b0;
wire net87;
wire net88;
wire net89;
wire net90;
wire net91;
wire net92;
wire net93;
wire net94;
wire net95;
wire net96;
wire net97;
wire net98;
wire net99;
wire net100;
wire net101;
wire net102;
wire net103;
wire net104;
wire net105;
wire net106;
wire net107 = 1'b1;
wire net108;
wire net109;
wire net110;
wire net111;
wire net112;
wire net113;
wire net114;
wire net115;
wire net116;
wire net117;
wire net118;
wire net119;
wire net120;
wire net121;
wire net122;
wire net123;
wire net124;
wire net125;
wire net126;
wire net127;
wire net128;
wire net129;
wire net130;
wire net131;
wire net132;
wire net133;
wire net134;
wire net135;
wire net136;
wire net137;
wire net138;
wire net139;
wire net140;
wire net141;
wire net142;
wire net143;
wire net144 = 1'b1;
wire net145;
wire net146;
wire net147 = 1'b1;
wire net148;
wire net149;
wire net150 = 1'b1;
wire net151;
wire net152;
wire net153 = 1'b1;
wire net154;
wire net155;
wire net156 = 1'b1;
wire net157;
wire net158;
wire net159 = 1'b1;
wire net160;
wire net161;
wire net162 = 1'b1;
wire net163;
wire net164;
wire net165 = 1'b1;
wire net166;
wire net167;
wire net168 = 1'b1;
wire net169;
wire net170;
wire net171 = 1'b1;
wire net172;
wire net173;
wire net174 = 1'b1;
wire net175;
wire net176;
wire net177 = 1'b1;
wire net178 = 1'b1;
wire net179;
wire net180 = 1'b1;
wire net181;
wire net182 = 1'b1;
wire net183;
wire net184 = 1'b1;
wire net185;
wire net186;
wire net187;
wire net188;
wire net189;
wire net190;
wire net191;
wire net192;
wire net193 = 1'b0;
wire net194 = 1'b0;
wire net195 = 1'b0;
wire net196 = 1'b0;
assign io_out[6] = net9;
assign io_out[7] = net10;
dff_cell flop6 (
.d (net14),
.clk (net1),
.q (net15)
);
mux_cell mux6 (
.a (net16),
.b (net17),
.sel (net8),
.out (net14)
);
dff_cell flop7 (
.d (net18),
.clk (net1),
.q (net17)
);
mux_cell mux7 (
.a (net19),
.b (net20),
.sel (net8),
.out (net18)
);
dff_cell flop8 (
.d (net21),
.clk (net1),
.q (net20)
);
mux_cell mux8 (
.a (net22),
.b (net23),
.sel (net8),
.out (net21)
);
dff_cell flop9 (
.d (net24),
.clk (net1),
.q (net23)
);
mux_cell mux9 (
.a (net25),
.b (net26),
.sel (net8),
.out (net24)
);
dff_cell flop10 (
.d (net27),
.clk (net1),
.q (net26)
);
mux_cell mux10 (
.a (net28),
.b (net29),
.sel (net8),
.out (net27)
);
dff_cell flop11 (
.d (net30),
.clk (net1),
.q (net29)
);
mux_cell mux11 (
.a (net31),
.b (net32),
.sel (net8),
.out (net30)
);
dff_cell flop12 (
.d (net33),
.clk (net1),
.q (net32)
);
mux_cell mux12 (
.a (net34),
.b (net35),
.sel (net8),
.out (net33)
);
dff_cell flop13 (
.d (net36),
.clk (net1),
.q (net35)
);
mux_cell mux13 (
.a (net37),
.b (net38),
.sel (net8),
.out (net36)
);
dff_cell flop14 (
.d (net39),
.clk (net1),
.q (net38)
);
mux_cell mux14 (
.a (net40),
.b (net41),
.sel (net8),
.out (net39)
);
dff_cell flop15 (
.d (net42),
.clk (net1),
.q (net41)
);
mux_cell mux15 (
.a (net43),
.b (net44),
.sel (net8),
.out (net42)
);
dff_cell flop16 (
.d (net45),
.clk (net1),
.q (net44)
);
mux_cell mux16 (
.a (net46),
.b (net47),
.sel (net8),
.out (net45)
);
mux_cell mux2 (
.a (net48),
.b (net49),
.sel (net8),
.out (net10)
);
dff_cell flop1 (
.d (net50),
.clk (net1),
.q (net51)
);
mux_cell mux1 (
.a (net52),
.b (net53),
.sel (net8),
.out (net50)
);
dff_cell flop2 (
.d (net54),
.clk (net1),
.q (net53)
);
mux_cell mux3 (
.a (net55),
.b (net56),
.sel (net8),
.out (net54)
);
dff_cell flop3 (
.d (net57),
.clk (net1),
.q (net56)
);
mux_cell mux4 (
.a (net58),
.b (net59),
.sel (net8),
.out (net57)
);
dff_cell flop4 (
.d (net60),
.clk (net1),
.q (net59)
);
mux_cell mux5 (
.a (net61),
.b (net62),
.sel (net8),
.out (net60)
);
dff_cell flop5 (
.d (net63),
.clk (net1),
.q (net62)
);
mux_cell mux17 (
.a (net64),
.b (net65),
.sel (net8),
.out (net63)
);
dff_cell flop17 (
.d (net66),
.clk (net1),
.q (net65)
);
mux_cell mux18 (
.a (net67),
.b (net68),
.sel (net8),
.out (net66)
);
dff_cell flop18 (
.d (net69),
.clk (net1),
.q (net68)
);
mux_cell mux19 (
.a (net70),
.b (net71),
.sel (net8),
.out (net69)
);
dff_cell flop19 (
.d (net72),
.clk (net1),
.q (net71)
);
mux_cell mux20 (
.a (net73),
.b (net74),
.sel (net8),
.out (net72)
);
dff_cell flop20 (
.d (net75),
.clk (net1),
.q (net74)
);
mux_cell mux21 (
.a (net76),
.b (net77),
.sel (net8),
.out (net75)
);
dff_cell flop21 (
.d (net78),
.clk (net1),
.q (net77)
);
mux_cell mux22 (
.a (net79),
.b (net80),
.sel (net8),
.out (net78)
);
dff_cell flop22 (
.d (net81),
.clk (net1),
.q (net80)
);
mux_cell mux23 (
.a (net82),
.b (net83),
.sel (net8),
.out (net81)
);
dff_cell flop23 (
.d (net84),
.clk (net1),
.q (net85)
);
mux_cell mux24 (
.a (net86),
.b (net87),
.sel (net8),
.out (net84)
);
dff_cell flop24 (
.d (net88),
.clk (net1),
.q (net87)
);
mux_cell mux25 (
.a (net19),
.b (net89),
.sel (net8),
.out (net88)
);
dff_cell flop25 (
.d (net90),
.clk (net1),
.q (net89)
);
mux_cell mux26 (
.a (net22),
.b (net91),
.sel (net8),
.out (net90)
);
dff_cell flop26 (
.d (net92),
.clk (net1),
.q (net91)
);
mux_cell mux27 (
.a (net25),
.b (net93),
.sel (net8),
.out (net92)
);
dff_cell flop27 (
.d (net94),
.clk (net1),
.q (net93)
);
mux_cell mux28 (
.a (net28),
.b (net95),
.sel (net8),
.out (net94)
);
dff_cell flop28 (
.d (net96),
.clk (net1),
.q (net95)
);
mux_cell mux29 (
.a (net31),
.b (net97),
.sel (net8),
.out (net96)
);
dff_cell flop29 (
.d (net98),
.clk (net1),
.q (net97)
);
mux_cell mux30 (
.a (net34),
.b (net99),
.sel (net8),
.out (net98)
);
dff_cell flop30 (
.d (net100),
.clk (net1),
.q (net99)
);
mux_cell mux31 (
.a (net37),
.b (net101),
.sel (net8),
.out (net100)
);
dff_cell flop31 (
.d (net102),
.clk (net1),
.q (net101)
);
mux_cell mux32 (
.a (net40),
.b (net103),
.sel (net8),
.out (net102)
);
dff_cell flop32 (
.d (net104),
.clk (net1),
.q (net103)
);
mux_cell mux33 (
.a (net43),
.b (net105),
.sel (net8),
.out (net104)
);
dff_cell flop33 (
.d (net106),
.clk (net1),
.q (net105)
);
mux_cell mux34 (
.a (net107),
.b (net108),
.sel (net8),
.out (net106)
);
xor_cell xor1 (
.a (net109),
.b (net110),
.out (net111)
);
xor_cell xor2 (
.a (net19),
.b (net22),
.out (net109)
);
xor_cell xor3 (
.a (net25),
.b (net28),
.out (net110)
);
xor_cell xor4 (
.a (net31),
.b (net34),
.out (net112)
);
xor_cell xor5 (
.a (net37),
.b (net40),
.out (net113)
);
xor_cell xor6 (
.a (net112),
.b (net113),
.out (net114)
);
xor_cell xor7 (
.a (net111),
.b (net114),
.out (net43)
);
dff_cell flop34 (
.d (net115),
.clk (net1),
.q (net116),
.notq (net117)
);
dff_cell flop35 (
.d (net118),
.clk (net1),
.q (net119),
.notq (net120)
);
dff_cell flop36 (
.d (net121),
.clk (net1),
.q (net122),
.notq (net123)
);
dff_cell flop37 (
.d (net124),
.clk (net1),
.q (net125),
.notq (net126)
);
and_cell and17 (
.a (net122),
.b (net117),
.out (net127)
);
and_cell and18 (
.a (net128),
.b (net129),
.out (net130)
);
and_cell and19 (
.a (net116),
.b (net125),
.out (net129)
);
and_cell and20 (
.a (net119),
.b (net123),
.out (net131)
);
and_cell and21 (
.a (net119),
.b (net117),
.out (net132)
);
and_cell and22 (
.a (net120),
.b (net122),
.out (net128)
);
and_cell and23 (
.a (net119),
.b (net126),
.out (net133)
);
xor_cell xor8 (
.a (net125),
.b (net116),
.out (net134)
);
or_cell or8 (
.a (net135),
.b (net136),
.out (net137)
);
or_cell or11 (
.a (net127),
.b (net138),
.out (net135)
);
or_cell or12 (
.a (net139),
.b (net140),
.out (net141)
);
or_cell or13 (
.a (net133),
.b (net130),
.out (net140)
);
or_cell or14 (
.a (net131),
.b (net132),
.out (net139)
);
and_cell and24 (
.a (net122),
.b (net126),
.out (net138)
);
and_cell and25 (
.a (net123),
.b (net125),
.out (net142)
);
and_cell and26 (
.a (net142),
.b (net116),
.out (net136)
);
dff_cell flop38 (
.d (net143),
.clk (net1),
.q (net47)
);
mux_cell mux35 (
.a (net144),
.b (net145),
.sel (net8),
.out (net143)
);
dff_cell flop39 (
.d (net146),
.clk (net1),
.q (net145)
);
mux_cell mux36 (
.a (net147),
.b (net148),
.sel (net8),
.out (net146)
);
dff_cell flop40 (
.d (net149),
.clk (net1),
.q (net148)
);
mux_cell mux37 (
.a (net150),
.b (net151),
.sel (net8),
.out (net149)
);
dff_cell flop41 (
.d (net152),
.clk (net1),
.q (net151)
);
mux_cell mux38 (
.a (net153),
.b (net154),
.sel (net8),
.out (net152)
);
dff_cell flop42 (
.d (net155),
.clk (net1),
.q (net83)
);
mux_cell mux39 (
.a (net156),
.b (net157),
.sel (net8),
.out (net155)
);
dff_cell flop43 (
.d (net158),
.clk (net1),
.q (net157)
);
mux_cell mux40 (
.a (net159),
.b (net160),
.sel (net8),
.out (net158)
);
dff_cell flop44 (
.d (net161),
.clk (net1),
.q (net160)
);
mux_cell mux41 (
.a (net162),
.b (net163),
.sel (net8),
.out (net161)
);
dff_cell flop45 (
.d (net164),
.clk (net1),
.q (net163)
);
mux_cell mux42 (
.a (net165),
.b (net166),
.sel (net8),
.out (net164)
);
dff_cell flop46 (
.d (net167),
.clk (net1),
.q (net108)
);
mux_cell mux43 (
.a (net168),
.b (net169),
.sel (net8),
.out (net167)
);
dff_cell flop47 (
.d (net170),
.clk (net1),
.q (net169)
);
mux_cell mux44 (
.a (net171),
.b (net172),
.sel (net8),
.out (net170)
);
dff_cell flop48 (
.d (net173),
.clk (net1),
.q (net172)
);
mux_cell mux45 (
.a (net174),
.b (net175),
.sel (net8),
.out (net173)
);
dff_cell flop49 (
.d (net176),
.clk (net1),
.q (net175)
);
mux_cell mux46 (
.a (net177),
.b (net178),
.sel (net8),
.out (net176)
);
dff_cell flop58 (
.d (net179),
.clk (net1),
.q (net49)
);
mux_cell mux47 (
.a (net180),
.b (net15),
.sel (net8),
.out (net179)
);
dff_cell flop59 (
.d (net181),
.clk (net1),
.q (net154)
);
mux_cell mux48 (
.a (net182),
.b (net51),
.sel (net8),
.out (net181)
);
dff_cell flop60 (
.d (net183),
.clk (net1),
.q (net166)
);
mux_cell mux49 (
.a (net184),
.b (net85),
.sel (net8),
.out (net183)
);
dff_cell flop50 (
.d (net2),
.clk (net6),
.q (net19)
);
dff_cell flop51 (
.d (net5),
.clk (net6),
.q (net28)
);
dff_cell flop52 (
.d (net4),
.clk (net6),
.q (net25)
);
dff_cell flop53 (
.d (net3),
.clk (net6),
.q (net22)
);
dff_cell flop54 (
.d (net2),
.clk (net7),
.q (net31)
);
dff_cell flop55 (
.d (net3),
.clk (net7),
.q (net34)
);
dff_cell flop56 (
.d (net4),
.clk (net7),
.q (net37)
);
dff_cell flop57 (
.d (net5),
.clk (net7),
.q (net40)
);
or_cell or17 (
.a (net116),
.b (net125),
.out (net185)
);
or_cell or18 (
.a (net122),
.b (net119),
.out (net186)
);
or_cell or19 (
.a (net185),
.b (net186),
.out (net187)
);
not_cell not7 (
.in (net187),
.out (net188)
);
or_cell or20 (
.a (net188),
.b (net187),
.out (net189)
);
and_cell and31 (
.a (net189),
.b (net190),
.out (net191)
);
or_cell or15 (
.a (net191),
.b (net192),
.out (net9)
);
and_cell and28 (
.a (net122),
.b (net119),
.out (net190)
);
mux_cell mux50 (
.a (net193),
.b (net117),
.sel (net8),
.out (net115)
);
mux_cell mux51 (
.a (net194),
.b (net134),
.sel (net8),
.out (net124)
);
mux_cell mux52 (
.a (net195),
.b (net137),
.sel (net8),
.out (net121)
);
mux_cell mux53 (
.a (net196),
.b (net141),
.sel (net8),
.out (net118)
);
and_cell and1 (
.a (net1),
.b (net8),
.out (net192)
);
endmodule |
module rc5_top (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire ir = io_in[2];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
wire valid;
wire [5:0] command;
wire control;
reg control_d;
localparam [5:0] RC5_INCR_VOLUME=16;
localparam [5:0] RC5_DECR_VOLUME=17;
rc5 rc5(
.i_clk(clk),
.i_rst(reset),
.i_rc5(ir),
.o_valid(valid),
.o_command(command),
.o_control(control)
);
reg [3:0] counter;
always @(posedge clk) begin
if (reset) begin
counter <= 0;
control_d <= 1'b0;
end else begin
if (valid) begin
control_d <= control;
if (control != control_d) begin
if (command == RC5_INCR_VOLUME) begin
counter <= counter+1;
end else if (command == RC5_DECR_VOLUME) begin
counter <= counter-1;
end
end
end
end
end
// instantiate segment display
seg7 seg7(.counter(counter), .segments(led_out));
endmodule |
module user_module_349011320806310484(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12 = 1'b0;
wire net13 = 1'b1;
wire net14 = 1'b1;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59;
wire net60;
wire net61;
wire net62;
wire net63;
wire net64;
wire net65;
wire net66;
wire net67;
wire net68;
wire net69 = 1'b0;
wire net70;
wire net71 = 1'b1;
wire net72;
wire net73;
wire net74;
wire net75;
wire net76;
wire net77;
wire net78;
wire net79;
wire net80 = 1'b0;
wire net81;
wire net82;
wire net83;
wire net84;
wire net85;
wire net86;
wire net87;
wire net88;
wire net89;
wire net90;
wire net91;
wire net92;
wire net93;
wire net94;
wire net95;
assign io_out[0] = net9;
assign io_out[1] = net9;
assign io_out[3] = net10;
assign io_out[5] = net9;
assign io_out[6] = net9;
assign io_out[7] = net11;
dff_cell flipflop1 (
.d (net15),
.clk (net16),
.q (net17)
);
not_cell gate7 (
.in (net1),
.out (net11)
);
not_cell gate8 (
.in (net2),
.out (net18)
);
and_cell gate9 (
.a (net18),
.b (net4),
.out (net15)
);
not_cell gate10 (
.in (net3),
.out (net19)
);
and_cell gate11 (
.a (net20),
.b (net1),
.out (net16)
);
dff_cell flop2 (
.d (net15),
.clk (net21),
.q (net22)
);
and_cell gate12 (
.a (net23),
.b (net1),
.out (net21)
);
or_cell gate13 (
.a (net19),
.b (net2),
.out (net20)
);
or_cell gate14 (
.a (net3),
.b (net2),
.out (net23)
);
dff_cell flipflop3 (
.d (net24),
.clk (net25),
.q (net26)
);
not_cell gate15 (
.in (net2),
.out (net27)
);
and_cell gate16 (
.a (net27),
.b (net5),
.out (net24)
);
not_cell gate17 (
.in (net3),
.out (net28)
);
and_cell gate18 (
.a (net29),
.b (net1),
.out (net25)
);
dff_cell flop3 (
.d (net24),
.clk (net30),
.q (net31)
);
and_cell gate19 (
.a (net32),
.b (net1),
.out (net30)
);
or_cell gate20 (
.a (net28),
.b (net2),
.out (net29)
);
or_cell gate21 (
.a (net3),
.b (net2),
.out (net32)
);
dff_cell flipflop4 (
.d (net33),
.clk (net34),
.q (net35)
);
not_cell gate22 (
.in (net2),
.out (net36)
);
and_cell gate23 (
.a (net36),
.b (net6),
.out (net33)
);
not_cell gate24 (
.in (net3),
.out (net37)
);
and_cell gate25 (
.a (net38),
.b (net1),
.out (net34)
);
dff_cell flop4 (
.d (net33),
.clk (net39),
.q (net40)
);
and_cell gate26 (
.a (net41),
.b (net1),
.out (net39)
);
or_cell gate27 (
.a (net37),
.b (net2),
.out (net38)
);
or_cell gate28 (
.a (net3),
.b (net2),
.out (net41)
);
dff_cell flipflop5 (
.d (net42),
.clk (net43),
.q (net44)
);
not_cell gate29 (
.in (net2),
.out (net45)
);
and_cell gate30 (
.a (net45),
.b (net7),
.out (net42)
);
not_cell gate31 (
.in (net3),
.out (net46)
);
and_cell gate32 (
.a (net47),
.b (net1),
.out (net43)
);
dff_cell flop5 (
.d (net42),
.clk (net48),
.q (net49)
);
and_cell gate33 (
.a (net50),
.b (net1),
.out (net48)
);
or_cell gate34 (
.a (net46),
.b (net2),
.out (net47)
);
or_cell gate35 (
.a (net3),
.b (net2),
.out (net50)
);
dff_cell flipflop6 (
.d (net51),
.clk (net52),
.q (net53)
);
not_cell gate36 (
.in (net2),
.out (net54)
);
and_cell gate37 (
.a (net54),
.b (net8),
.out (net51)
);
not_cell gate38 (
.in (net3),
.out (net55)
);
and_cell gate39 (
.a (net56),
.b (net1),
.out (net52)
);
dff_cell flop6 (
.d (net51),
.clk (net57),
.q (net58)
);
and_cell gate40 (
.a (net59),
.b (net1),
.out (net57)
);
or_cell gate41 (
.a (net55),
.b (net2),
.out (net56)
);
or_cell gate42 (
.a (net3),
.b (net2),
.out (net59)
);
buffer_cell gate43 (
.in (net17),
.out (net60)
);
buffer_cell gate44 (
.in (net26),
.out (net61)
);
buffer_cell gate45 (
.in (net35),
.out (net62)
);
buffer_cell gate46 (
.in (net44),
.out (net63)
);
buffer_cell gate47 (
.in (net53),
.out (net64)
);
buffer_cell gate48 (
.in (net22),
.out (net65)
);
buffer_cell gate49 (
.in (net31),
.out (net66)
);
buffer_cell gate50 (
.in (net40),
.out (net67)
);
buffer_cell gate51 (
.in (net49),
.out (net68)
);
buffer_cell gate52 (
.in (net58),
.out (net10)
);
mux_cell mux1 (
.a (net69),
.b (net64),
.sel (net60),
.out (net70)
);
mux_cell mux4 (
.a (net64),
.b (net71),
.sel (net60),
.out (net72)
);
not_cell not1 (
.in (net60),
.out (net73)
);
mux_cell mux5 (
.a (net74),
.b (net75),
.sel (net66),
.out (net76)
);
mux_cell mux6 (
.a (net69),
.b (net70),
.sel (net61),
.out (net77)
);
mux_cell mux7 (
.a (net70),
.b (net72),
.sel (net61),
.out (net78)
);
mux_cell mux8 (
.a (net72),
.b (net73),
.sel (net61),
.out (net79)
);
mux_cell mux9 (
.a (net73),
.b (net80),
.sel (net61),
.out (net81)
);
mux_cell mux10 (
.a (net77),
.b (net78),
.sel (net62),
.out (net82)
);
mux_cell mux11 (
.a (net78),
.b (net79),
.sel (net62),
.out (net83)
);
mux_cell mux12 (
.a (net79),
.b (net81),
.sel (net62),
.out (net84)
);
mux_cell mux13 (
.a (net81),
.b (net80),
.sel (net62),
.out (net85)
);
mux_cell mux14 (
.a (net82),
.b (net83),
.sel (net63),
.out (net86)
);
mux_cell mux15 (
.a (net83),
.b (net84),
.sel (net63),
.out (net87)
);
mux_cell mux16 (
.a (net84),
.b (net85),
.sel (net63),
.out (net88)
);
mux_cell mux17 (
.a (net85),
.b (net80),
.sel (net63),
.out (net89)
);
mux_cell mux18 (
.a (net86),
.b (net87),
.sel (net65),
.out (net74)
);
mux_cell mux19 (
.a (net87),
.b (net88),
.sel (net65),
.out (net75)
);
mux_cell mux20 (
.a (net88),
.b (net89),
.sel (net65),
.out (net90)
);
mux_cell mux21 (
.a (net89),
.b (net80),
.sel (net65),
.out (net91)
);
mux_cell mux2 (
.a (net75),
.b (net90),
.sel (net66),
.out (net92)
);
mux_cell mux3 (
.a (net90),
.b (net91),
.sel (net66),
.out (net93)
);
mux_cell mux22 (
.a (net76),
.b (net92),
.sel (net67),
.out (net94)
);
mux_cell mux23 (
.a (net92),
.b (net93),
.sel (net67),
.out (net95)
);
mux_cell mux24 (
.a (net94),
.b (net95),
.sel (net68),
.out (net9)
);
endmodule |
module aidan_McCoy(
input [7:0] io_in,
output [7:0] io_out);
// map i/o to proper labels
wire clk = io_in[0];
wire reset = io_in[1];
wire [5:0] instr = io_in[7:2];
// decode signals
wire bez;
wire ja;
//wire aluFun;
wire op1Sel;
wire op2Sel;
wire writeReg;
wire writex8;
wire [1:0] x8Sel;
// Other wires
wire [7:0] pc;
wire [7:0] pc1;
wire [7:0] nextPC;
wire pcSel;
wire [7:0] aluOut;
wire [7:0] x8;
wire [7:0] newx8;
wire [7:0] op1;
wire [7:0] op2;
wire [7:0] regOut;
wire [7:0] imm;
wire [7:0] notx8;
/* Misc. blocks */
decoder decoderBlock( .opcode(instr[2:0]), .bez(bez), .ja(ja), /*.aluFun(aluFun),*/ .op1(op1Sel), .op2(op2Sel),
.writeReg(writeReg), .writex8(writex8), .x8Sel(x8Sel));
iSign signBlock( .imm(instr[5:3]), .out(imm));
/* PC related blocks */
mux2 pcMux( .in0(aluOut), .in1(pc1), .sel(pcSel), .out(nextPC));
pc pcBlock( .clk(clk), .reset(reset), .nextPC(nextPC), .PC(pc));
add1 adder( .in(pc), .out(pc1));
branch branchBlock( .x8(x8), .bez(bez), .ja(ja), .reset(reset), .pcSel(pcSel));
/* ALU blocks */
mux2 op1Mux( .in0(regOut), .in1(x8), .sel(op1Sel), .out(op1));
mux2 op2Mux( .in0(regOut), .in1(pc), .sel(op2Sel), .out(op2));
alu aluBlock( .op1(op1), .op2(op2), /*.aluFun(aluFun),*/ .aluOut(aluOut));
/* x8 and other register blocks */
register regBlock( .clk(clk), .reset(reset), .regAddr(instr[5:3]), .x8(x8), .writeReg(writeReg),
.out(regOut));
x8 x8Block( .clk(clk), .writex8(writex8), .newx8(newx8), .x8(x8));
notx8 nx8( .x8(x8), .out(notx8));
mux4 x8Mux( .in0(regOut), .in1(imm), .in2(aluOut), .in3(notx8), .sel(x8Sel), .out(newx8));
assign io_out = clk ? pc : x8;
endmodule |
module user_module_349047610915422802(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[6];
wire net6 = io_in[7];
wire net7;
wire net8;
wire net9;
wire net10;
wire net11;
wire net12;
wire net13 = 1'b0;
wire net14 = 1'b1;
wire net15 = 1'b1;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
assign io_out[0] = net7;
assign io_out[1] = net8;
assign io_out[2] = net9;
assign io_out[3] = net10;
assign io_out[4] = net11;
assign io_out[7] = net12;
dff_cell flipflop2 (
.d (net5),
.clk (net6),
.q (net16),
.notq (net17)
);
dff_cell flipflop3 (
.d (net17),
.clk (net6),
.q (net18),
.notq (net19)
);
dff_cell flipflop4 (
.d (net19),
.clk (net6),
.q (net20),
.notq (net21)
);
dff_cell flipflop5 (
.d (net21),
.clk (net6),
.q (net22),
.notq (net12)
);
xor_cell gate7 (
.a (net1),
.b (net16),
.out (net7)
);
xor_cell gate8 (
.a (net2),
.b (net18),
.out (net23)
);
xor_cell gate9 (
.a (net3),
.b (net20),
.out (net24)
);
xor_cell gate10 (
.a (net4),
.b (net22),
.out (net25)
);
and_cell gate11 (
.a (net23),
.b (net26),
.out (net27)
);
and_cell gate12 (
.a (net2),
.b (net18),
.out (net28)
);
and_cell gate13 (
.a (net3),
.b (net20),
.out (net29)
);
and_cell gate14 (
.a (net4),
.b (net22),
.out (net30)
);
and_cell gate16 (
.a (net1),
.b (net16),
.out (net26)
);
xor_cell gate17 (
.a (net23),
.b (net26),
.out (net8)
);
and_cell gate18 (
.a (net24),
.b (net31),
.out (net32)
);
xor_cell gate19 (
.a (net25),
.b (net33),
.out (net10)
);
and_cell gate20 (
.a (net25),
.b (net33),
.out (net34)
);
or_cell gate21 (
.a (net34),
.b (net30),
.out (net11)
);
or_cell gate22 (
.a (net32),
.b (net29),
.out (net33)
);
or_cell gate25 (
.a (net27),
.b (net28),
.out (net31)
);
xor_cell gate26 (
.a (net24),
.b (net31),
.out (net9)
);
endmodule |
module stevenmburns_toplevel(
input [7:0] io_in,
output [7:0] io_out
);
ScanBinary u0(.clock(io_in[0]),
.reset(io_in[1]),
.io_ld(io_in[2]),
.io_u_bit(io_in[3]),
.io_v_bit(io_in[4]),
.io_z_bit(io_out[0]),
.io_done(io_out[1]));
assign io_out[7:2] = 6'b0;
endmodule |
module user_module_349228308755382868(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17 = 1'b0;
wire net18 = 1'b1;
wire net19 = 1'b1;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28 = 1'b0;
wire net29;
wire net30;
wire net31;
wire net32 = 1'b1;
wire net33 = 1'b0;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59;
wire net60;
wire net61;
wire net62;
wire net63;
wire net64;
wire net65;
wire net66;
wire net67;
wire net68;
wire net69;
wire net70;
wire net71;
wire net72;
wire net73;
wire net74;
wire net75;
wire net76;
wire net77;
wire net78;
wire net79;
wire net80;
wire net81;
wire net82;
wire net83;
wire net84;
wire net85;
wire net86;
wire net87;
wire net88;
wire net89;
wire net90;
wire net91;
wire net92;
wire net93;
wire net94;
wire net95;
wire net96;
wire net97;
wire net98;
wire net99;
wire net100;
wire net101;
wire net102;
wire net103;
wire net104;
wire net105;
wire net106;
wire net107;
wire net108;
wire net109;
wire net110;
wire net111;
wire net112;
wire net113;
wire net114;
wire net115;
wire net116;
wire net117;
wire net118;
wire net119;
wire net120;
wire net121;
wire net122;
wire net123;
wire net124;
wire net125;
wire net126;
wire net127;
wire net128;
wire net129;
wire net130;
wire net131;
wire net132;
wire net133;
wire net134;
wire net135 = 1'b0;
wire net136 = 1'b0;
wire net137 = 1'b0;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net11;
assign io_out[3] = net12;
assign io_out[4] = net13;
assign io_out[5] = net14;
assign io_out[6] = net15;
assign io_out[7] = net16;
and_cell gate1 (
.a (net20),
.b (net21),
.out (net22)
);
xor_cell gate3 (
.a (net23),
.b (net24),
.out (net25)
);
not_cell gate5 (
.in (net1),
.out (net26)
);
buffer_cell gate6 (
.in (net1),
.out (net27)
);
mux_cell mux1 (
.a (net28),
.b (net29),
.sel (net21),
.out (net30)
);
dff_cell flipflop1 (
.d (net2),
.clk (net27),
.notq (net31)
);
dff_cell flop1 (
.d (net34),
.clk (net27),
.q (net35)
);
dff_cell flop2 (
.d (net36),
.clk (net27),
.q (net37)
);
dff_cell flop3 (
.d (net38),
.clk (net27),
.q (net23),
.notq (net39)
);
dff_cell flop4 (
.d (net40),
.clk (net27),
.q (net41),
.notq (net42)
);
dff_cell flop5 (
.d (net43),
.clk (net27),
.q (net44),
.notq (net45)
);
dff_cell flop6 (
.d (net22),
.clk (net27),
.q (net24),
.notq (net20)
);
and_cell gate7 (
.a (net25),
.b (net21),
.out (net38)
);
xor_cell gate8 (
.a (net41),
.b (net46),
.out (net47)
);
and_cell gate9 (
.a (net47),
.b (net21),
.out (net40)
);
and_cell gate10 (
.a (net24),
.b (net23),
.out (net46)
);
xor_cell gate11 (
.a (net44),
.b (net48),
.out (net49)
);
and_cell gate12 (
.a (net49),
.b (net21),
.out (net43)
);
and_cell gate13 (
.a (net46),
.b (net41),
.out (net48)
);
xor_cell gate14 (
.a (net37),
.b (net50),
.out (net51)
);
and_cell gate15 (
.a (net51),
.b (net21),
.out (net36)
);
and_cell gate16 (
.a (net48),
.b (net44),
.out (net50)
);
xor_cell gate17 (
.a (net35),
.b (net52),
.out (net53)
);
and_cell gate18 (
.a (net53),
.b (net21),
.out (net34)
);
and_cell gate19 (
.a (net50),
.b (net37),
.out (net52)
);
and_cell gate20 (
.a (net20),
.b (net39),
.out (net54)
);
and_cell gate21 (
.a (net54),
.b (net42),
.out (net55)
);
and_cell gate22 (
.a (net45),
.b (net56),
.out (net57)
);
and_cell gate23 (
.a (net37),
.b (net35),
.out (net56)
);
and_cell and1 (
.a (net31),
.b (net58),
.out (net21)
);
nand_cell nand1 (
.a (net55),
.b (net57),
.out (net58)
);
dff_cell flop7 (
.d (net59),
.clk (net26),
.q (net10)
);
dff_cell flop8 (
.d (net60),
.clk (net26),
.q (net11)
);
dff_cell flop10 (
.d (net21),
.clk (net26),
.notq (net9)
);
dff_cell flop15 (
.d (net61),
.clk (net27),
.q (net62)
);
dff_cell flop16 (
.d (net63),
.clk (net27),
.q (net64)
);
dff_cell flop17 (
.d (net65),
.clk (net27),
.q (net66)
);
dff_cell flop18 (
.d (net30),
.clk (net27),
.q (net67)
);
mux_cell mux2 (
.a (net28),
.b (net67),
.sel (net21),
.out (net61)
);
mux_cell mux3 (
.a (net28),
.b (net62),
.sel (net21),
.out (net63)
);
mux_cell mux4 (
.a (net28),
.b (net64),
.sel (net21),
.out (net65)
);
mux_cell mux5 (
.a (net28),
.b (net66),
.sel (net21),
.out (net68)
);
dff_cell flop19 (
.d (net69),
.clk (net27),
.q (net70)
);
dff_cell flop20 (
.d (net71),
.clk (net27),
.q (net72)
);
dff_cell flop21 (
.d (net73),
.clk (net27),
.q (net74)
);
dff_cell flop22 (
.d (net68),
.clk (net27),
.q (net75)
);
mux_cell mux6 (
.a (net28),
.b (net75),
.sel (net21),
.out (net69)
);
mux_cell mux7 (
.a (net28),
.b (net70),
.sel (net21),
.out (net71)
);
mux_cell mux8 (
.a (net28),
.b (net72),
.sel (net21),
.out (net73)
);
mux_cell mux9 (
.a (net32),
.b (net74),
.sel (net21),
.out (net76)
);
dff_cell flop23 (
.d (net77),
.clk (net27),
.q (net78)
);
dff_cell flop24 (
.d (net79),
.clk (net27),
.q (net80)
);
dff_cell flop25 (
.d (net81),
.clk (net27),
.q (net82)
);
dff_cell flop26 (
.d (net76),
.clk (net27),
.q (net83)
);
mux_cell mux10 (
.a (net32),
.b (net83),
.sel (net21),
.out (net77)
);
mux_cell mux11 (
.a (net28),
.b (net78),
.sel (net21),
.out (net79)
);
mux_cell mux12 (
.a (net28),
.b (net80),
.sel (net21),
.out (net81)
);
mux_cell mux13 (
.a (net28),
.b (net82),
.sel (net21),
.out (net84)
);
dff_cell flop27 (
.d (net85),
.clk (net27),
.q (net86)
);
dff_cell flop28 (
.d (net87),
.clk (net27),
.q (net88)
);
dff_cell flop29 (
.d (net89),
.clk (net27),
.q (net59)
);
dff_cell flop30 (
.d (net84),
.clk (net27),
.q (net90)
);
mux_cell mux14 (
.a (net28),
.b (net90),
.sel (net21),
.out (net85)
);
mux_cell mux15 (
.a (net28),
.b (net86),
.sel (net21),
.out (net87)
);
mux_cell mux16 (
.a (net28),
.b (net88),
.sel (net21),
.out (net89)
);
mux_cell mux33 (
.a (net91),
.b (net11),
.sel (net21),
.out (net60)
);
dff_cell flop9 (
.d (net92),
.clk (net26),
.q (net12)
);
mux_cell mux34 (
.a (net93),
.b (net12),
.sel (net21),
.out (net92)
);
dff_cell flop11 (
.d (net94),
.clk (net26),
.q (net13)
);
mux_cell mux35 (
.a (net95),
.b (net13),
.sel (net21),
.out (net94)
);
dff_cell flop12 (
.d (net96),
.clk (net26),
.q (net14)
);
mux_cell mux36 (
.a (net97),
.b (net14),
.sel (net21),
.out (net96)
);
dff_cell flop13 (
.d (net98),
.clk (net26),
.q (net15)
);
mux_cell mux37 (
.a (net99),
.b (net15),
.sel (net21),
.out (net98)
);
dff_cell flop14 (
.d (net100),
.clk (net26),
.q (net16)
);
mux_cell mux38 (
.a (net101),
.b (net16),
.sel (net21),
.out (net100)
);
and_cell gate2 (
.a (net3),
.b (net31),
.out (net102)
);
dff_cell flop31 (
.d (net102),
.clk (net27),
.q (net91)
);
and_cell gate24 (
.a (net103),
.b (net31),
.out (net104)
);
dff_cell flop32 (
.d (net104),
.clk (net27),
.q (net93)
);
and_cell gate25 (
.a (net105),
.b (net31),
.out (net106)
);
dff_cell flop33 (
.d (net106),
.clk (net27),
.q (net95)
);
and_cell gate26 (
.a (net107),
.b (net31),
.out (net108)
);
dff_cell flop34 (
.d (net108),
.clk (net27),
.q (net97)
);
and_cell gate27 (
.a (net109),
.b (net31),
.out (net110)
);
dff_cell flop35 (
.d (net110),
.clk (net27),
.q (net99)
);
and_cell gate28 (
.a (net111),
.b (net31),
.out (net112)
);
dff_cell flop36 (
.d (net112),
.clk (net27),
.q (net101)
);
and_cell gate29 (
.a (net113),
.b (net31),
.out (net114)
);
dff_cell flop37 (
.d (net114),
.clk (net27),
.q (net115)
);
and_cell gate30 (
.a (net115),
.b (net31),
.out (net116)
);
dff_cell flop38 (
.d (net116),
.clk (net27),
.q (net117)
);
and_cell gate31 (
.a (net117),
.b (net31),
.out (net118)
);
dff_cell flop39 (
.d (net118),
.clk (net27),
.q (net119)
);
and_cell gate32 (
.a (net119),
.b (net31),
.out (net120)
);
dff_cell flop40 (
.d (net120),
.clk (net27),
.q (net121)
);
and_cell gate33 (
.a (net121),
.b (net31),
.out (net122)
);
dff_cell flop41 (
.d (net122),
.clk (net27),
.q (net123)
);
and_cell gate34 (
.a (net123),
.b (net31),
.out (net124)
);
dff_cell flop42 (
.d (net124),
.clk (net27),
.q (net125)
);
and_cell gate35 (
.a (net125),
.b (net31),
.out (net126)
);
dff_cell flop43 (
.d (net126),
.clk (net27),
.q (net127)
);
and_cell gate36 (
.a (net127),
.b (net31),
.out (net128)
);
dff_cell flop44 (
.d (net128),
.clk (net27),
.q (net129)
);
and_cell gate37 (
.a (net129),
.b (net31),
.out (net130)
);
dff_cell flop45 (
.d (net130),
.clk (net27),
.q (net131)
);
and_cell gate38 (
.a (net131),
.b (net31),
.out (net132)
);
dff_cell flop46 (
.d (net132),
.clk (net27),
.q (net133)
);
and_cell gate39 (
.a (net133),
.b (net31),
.out (net134)
);
dff_cell flop47 (
.d (net134),
.clk (net27),
.q (net29)
);
mux_cell mux17 (
.a (net135),
.b (net91),
.sel (net21),
.out (net103)
);
mux_cell mux18 (
.a (net4),
.b (net93),
.sel (net21),
.out (net105)
);
mux_cell mux19 (
.a (net5),
.b (net95),
.sel (net21),
.out (net107)
);
mux_cell mux20 (
.a (net6),
.b (net97),
.sel (net21),
.out (net109)
);
mux_cell mux21 (
.a (net7),
.b (net99),
.sel (net21),
.out (net111)
);
mux_cell mux22 (
.a (net8),
.b (net101),
.sel (net21),
.out (net113)
);
endmodule |
module user_module_347497504164545108(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[3];
wire net4 = io_in[4];
wire net5 = io_in[5];
wire net6 = io_in[6];
wire net7 = io_in[7];
wire net8;
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32 = 1'b1;
wire net33 = 1'b1;
wire net34 = 1'b0;
wire net35 = 1'b0;
wire net36;
wire net37;
wire net38;
wire net39 = 1'b0;
wire net40 = 1'b0;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45;
wire net46;
wire net47;
wire net48;
wire net49;
wire net50;
wire net51;
wire net52 = 1'b0;
wire net53;
wire net54;
wire net55;
wire net56;
wire net57;
wire net58;
wire net59;
wire net60;
wire net61 = 1'b0;
wire net62;
wire net63;
wire net64;
wire net65;
wire net66;
wire net67;
wire net68;
wire net69;
wire net70;
wire net71 = 1'b0;
wire net72 = 1'b0;
wire net73;
wire net74;
wire net75;
wire net76;
wire net77 = 1'b0;
wire net78;
wire net79;
wire net80;
wire net81;
wire net82;
wire net83;
wire net84;
wire net85;
wire net86;
wire net87;
wire net88;
wire net89;
wire net90;
wire net91;
wire net92;
wire net93;
wire net94;
wire net95;
wire net96;
wire net97;
wire net98;
wire net99 = 1'b0;
wire net100 = 1'b0;
assign io_out[0] = net8;
assign io_out[1] = net9;
assign io_out[2] = net10;
assign io_out[3] = net11;
assign io_out[4] = net12;
assign io_out[5] = net13;
assign io_out[6] = net14;
buffer_cell gate53 (
.in (net15),
.out (net16)
);
not_cell gate54 (
.in (net15),
.out (net17)
);
not_cell gate55 (
.in (net18),
.out (net19)
);
buffer_cell gate56 (
.in (net18),
.out (net20)
);
not_cell gate57 (
.in (net21),
.out (net22)
);
not_cell gate58 (
.in (net23),
.out (net24)
);
buffer_cell gate59 (
.in (net21),
.out (net25)
);
buffer_cell gate60 (
.in (net23),
.out (net26)
);
and_cell gate61 (
.a (net17),
.b (net20),
.out (net27)
);
and_cell gate74 (
.a (net27),
.b (net25),
.out (net28)
);
or_cell gate75 (
.a (net28),
.b (net29),
.out (net8)
);
and_cell gate76 (
.a (net16),
.b (net19),
.out (net30)
);
and_cell gate77 (
.a (net30),
.b (net22),
.out (net31)
);
and_cell gate78 (
.a (net31),
.b (net24),
.out (net29)
);
or_cell gate79 (
.a (net28),
.b (net36),
.out (net37)
);
or_cell gate80 (
.a (net37),
.b (net29),
.out (net9)
);
and_cell gate81 (
.a (net17),
.b (net25),
.out (net38)
);
and_cell gate82 (
.a (net38),
.b (net26),
.out (net36)
);
or_cell gate83 (
.a (net41),
.b (net42),
.out (net43)
);
or_cell gate84 (
.a (net43),
.b (net44),
.out (net45)
);
and_cell gate87 (
.a (net17),
.b (net19),
.out (net46)
);
and_cell gate88 (
.a (net46),
.b (net25),
.out (net41)
);
and_cell gate89 (
.a (net19),
.b (net25),
.out (net47)
);
and_cell gate90 (
.a (net47),
.b (net24),
.out (net42)
);
and_cell gate91 (
.a (net24),
.b (net25),
.out (net48)
);
and_cell gate92 (
.a (net48),
.b (net17),
.out (net44)
);
and_cell gate93 (
.a (net16),
.b (net49),
.out (net50)
);
and_cell gate85 (
.a (net19),
.b (net51),
.out (net49)
);
and_cell gate86 (
.a (net22),
.b (net26),
.out (net51)
);
or_cell gate94 (
.a (net45),
.b (net50),
.out (net10)
);
xor_cell gate95 (
.a (net25),
.b (net26),
.out (net53)
);
and_cell gate96 (
.a (net17),
.b (net54),
.out (net55)
);
and_cell gate97 (
.a (net20),
.b (net56),
.out (net54)
);
and_cell gate98 (
.a (net22),
.b (net26),
.out (net56)
);
and_cell gate99 (
.a (net16),
.b (net19),
.out (net57)
);
and_cell gate100 (
.a (net58),
.b (net19),
.out (net59)
);
not_cell gate101 (
.in (net53),
.out (net58)
);
or_cell gate102 (
.a (net57),
.b (net59),
.out (net60)
);
or_cell gate103 (
.a (net60),
.b (net55),
.out (net11)
);
and_cell gate104 (
.a (net16),
.b (net19),
.out (net62)
);
and_cell gate105 (
.a (net19),
.b (net22),
.out (net63)
);
and_cell gate106 (
.a (net17),
.b (net20),
.out (net64)
);
or_cell gate107 (
.a (net25),
.b (net26),
.out (net65)
);
and_cell gate108 (
.a (net17),
.b (net66),
.out (net67)
);
and_cell gate109 (
.a (net25),
.b (net24),
.out (net66)
);
or_cell gate110 (
.a (net62),
.b (net63),
.out (net68)
);
or_cell gate111 (
.a (net68),
.b (net69),
.out (net70)
);
or_cell gate112 (
.a (net70),
.b (net67),
.out (net12)
);
and_cell gate113 (
.a (net64),
.b (net65),
.out (net69)
);
or_cell gate114 (
.a (net59),
.b (net69),
.out (net13)
);
or_cell gate115 (
.a (net73),
.b (net74),
.out (net75)
);
or_cell gate116 (
.a (net75),
.b (net76),
.out (net14)
);
and_cell gate118 (
.a (net17),
.b (net25),
.out (net73)
);
and_cell gate119 (
.a (net78),
.b (net26),
.out (net74)
);
xor_cell gate120 (
.a (net16),
.b (net20),
.out (net78)
);
and_cell gate117 (
.a (net19),
.b (net79),
.out (net76)
);
and_cell gate121 (
.a (net22),
.b (net24),
.out (net79)
);
dff_cell flipflop4 (
.d (net80),
.clk (net1),
.q (net81),
.notq (net82)
);
or_cell gate2 (
.a (net82),
.b (net83),
.out (net80)
);
dff_cell flipflop7 (
.d (net84),
.clk (net85),
.q (net86),
.notq (net87)
);
or_cell gate3 (
.a (net87),
.b (net83),
.out (net84)
);
dff_cell flipflop8 (
.d (net88),
.clk (net89),
.q (net90),
.notq (net91)
);
or_cell gate4 (
.a (net91),
.b (net83),
.out (net88)
);
dff_cell flipflop9 (
.d (net92),
.clk (net93),
.notq (net94)
);
or_cell gate5 (
.a (net94),
.b (net83),
.out (net92)
);
dff_cell flipflop10 (
.d (net95),
.clk (net1),
.q (net83)
);
or_cell gate6 (
.a (net96),
.b (net2),
.out (net95)
);
mux_cell mux1 (
.a (net81),
.b (net1),
.sel (net83),
.out (net85)
);
mux_cell mux5 (
.a (net86),
.b (net1),
.sel (net83),
.out (net89)
);
mux_cell mux6 (
.a (net90),
.b (net1),
.sel (net83),
.out (net93)
);
and_cell gate17 (
.a (net90),
.b (net94),
.out (net97)
);
and_cell gate18 (
.a (net87),
.b (net97),
.out (net98)
);
and_cell gate19 (
.a (net81),
.b (net98),
.out (net96)
);
mux_cell mux2 (
.a (net94),
.b (net4),
.sel (net3),
.out (net15)
);
mux_cell mux3 (
.a (net91),
.b (net5),
.sel (net3),
.out (net18)
);
mux_cell mux4 (
.a (net87),
.b (net6),
.sel (net3),
.out (net21)
);
mux_cell mux7 (
.a (net82),
.b (net7),
.sel (net3),
.out (net23)
);
endmodule |
module rdffe(input clk,d,en,rst, output q);
`ifdef COCOTB_SIM
reg rq;
assign #0.1 q = rq;
always @(posedge clk or posedge rst)
rq <= rst ? 1'b0 : ( en ? d : q);
`else
wire b;
assign b = en ? d : q;
sky130_fd_sc_hd__dfrtp_4 dfrtp(
.D(b),
.RESET_B(~rst),
.CLK(clk),
.Q(q)
);
`endif
endmodule |
module sdffe(input clk,d,en,pre, output q);
`ifdef COCOTB_SIM
reg rq;
assign #0.1 q = rq;
always @(posedge clk or posedge pre)
rq <= pre ? 1'b1 : ( en ? d : q);
`else
wire b;
assign b = en ? d : q;
sky130_fd_sc_hd__dfstp_4 dfstp(
.D(b),
.SET_B(~pre),
.CLK(clk),
.Q(q)
);
`endif
endmodule |
module inv_with_delay(input A,output Y);
`ifdef COCOTB_SIM
assign #0.02 Y = ~A; // pick a fairly quick delay from the tt_025C_1v80 liberty file
// the actualy delay per stage is going to be slower
`else
sky130_fd_sc_hd__inv_2 inv(.A(A),.Y(Y));
`endif
endmodule |
module nand2_with_delay(input A,input B,output Y);
`ifdef COCOTB_SIM
assign #0.05 Y = ~(A & B);
`else
sky130_fd_sc_hd__nand2_2 nand2(.A(A),.B(B),.Y(Y));
`endif
endmodule |
module ring_osc(input nrst,output osc);
// We count for 1 scan_clk period which expected at 166uS (6KHz).
// If the delay of one inverter is 20ps and the ring is 150 inverters long,
// then the ring period is 6nS (2*150inv*20pS/inv)
// This is 166MHz so expect a count of 166*166 nominally.
// For more time resolution make scan_clk slower but that requires more
// counter depth.
// scan clk slowing can be done externally to the TT IC or with the clk div.
localparam NUM_INVERTERS = 150; // must be an even number
// setup loop of inverters
// http://svn.clairexen.net/handicraft/2015/ringosc/ringosc.v
wire [NUM_INVERTERS-1:0] delay_in, delay_out;
wire osc_out;
inv_with_delay idelay [NUM_INVERTERS-1:0] (
.A(delay_in),
.Y(delay_out)
);
assign delay_in = {delay_out[NUM_INVERTERS-2:0], osc_out};
nand2_with_delay nand2_with_delay(.A(nrst),.B(delay_out[NUM_INVERTERS-1]),.Y(osc_out));
assign osc = osc_out;
endmodule |
module ring_with_counter #(parameter WIDTH=24) (input nrst, ring_en, count_en, output [WIDTH-1:0] count);
wire [WIDTH:0] value;
wire rst,count_en_s0,count_en_s1,osc,nosc_buf;
genvar i;
ring_osc ring_osc(.nrst(ring_en),.osc(osc));
inv_with_delay inv_r(.A(nrst),.Y(rst));
// logic in this module should minimize loading the ring, so buffer the ring output
inv_with_delay inv_b(.A(osc),.Y(nosc_buf));
// synchronize the counter enable time to the ring oscillator frequency
// so metastability doesnt corrupt the count. note: we count on the ring frequency domain
rdffe ds0(.clk(nosc_buf),.rst(rst),.en(1'b1), .d(count_en), .q(count_en_s0));
rdffe ds1(.clk(nosc_buf),.rst(rst),.en(1'b1), .d(count_en_s0), .q(count_en_s1));
// Count down toward zero from (signed)-1
assign value[0] = nosc_buf;
generate
for (i = 1; i < WIDTH; i = i + 1)
sdffe dcg(.clk(value[i-1]),.pre(rst),.en(count_en_s1),.d(~value[i]),.q(value[i]));
endgenerate
// value[WIDTH] is the overflow bit. Make it sticky.
// This bit should never be cleared if the measurement is designed correctly.
sdffe dcg(.clk(value[WIDTH-1]),.pre(rst),.en(count_en_s1),.d(1'b0),.q(value[WIDTH]));
assign count[WIDTH-1:0] = value[WIDTH:1];
endmodule |
module ericsmi_speed_test(
input [7:0] io_in,
output [7:0] io_out
);
parameter WIDTH=24;
localparam COUNTER_WIDTH = 23; // TinyTapeout is small, so find a value that fits by trial and error
wire force_trig, fired, count_en;
wire [2:0] sel;
wire [2:0] trig_q;
wire [1:0] ring_en;
wire [WIDTH-1:0] value0,value1;
wire [COUNTER_WIDTH-1:0] count0,count1;
wire clk = io_in[0];
wire nrst = io_in[1];
wire trig = io_in[2];
assign sel[2:0] = io_in[5:3];
assign ring_en[1:0] = io_in[7:6];
assign force_trig = &sel; // force the oscillators and counters to run to test their operation
// not really a controlled measurement. Only for debug.
inv_with_delay inv_r(.A(nrst),.Y(rst));
// Enable the counters for one clk period upon trig rising edge.
// Asserting nrst arms the measurements. Clear nrst before fire.
rdffe dt0(.clk(clk),.rst(rst),.en(1'b1), .d(trig ), .q(trig_q[0]));
rdffe dt1(.clk(clk),.rst(rst),.en(1'b1), .d(trig_q[0]), .q(trig_q[1]));
rdffe dt2(
.clk(clk),
.rst(rst),
.en(1'b1),
.d((trig_q[0] & ~trig_q[1])),
.q(trig_q[2])
);
rdffe dt3(
.clk(clk),
.rst(rst),
.en(1'b1),
.d(trig_q[2] | fired),
.q(fired)
);
assign count_en = force_trig | trig_q[2];
ring_with_counter #(.WIDTH(COUNTER_WIDTH)) ring0(
.nrst(nrst),
.ring_en(ring_en[0]),
.count_en(count_en),
.count(count0[COUNTER_WIDTH-1:0])
);
assign value0[WIDTH-1:0] = {{WIDTH-COUNTER_WIDTH{count0[COUNTER_WIDTH-1]}},count0[COUNTER_WIDTH-1:0]};
ring_with_counter #(.WIDTH(COUNTER_WIDTH)) ring1(
.nrst(nrst),
.ring_en(ring_en[1]),
.count_en(count_en),
.count(count1[COUNTER_WIDTH-1:0])
);
assign value1[WIDTH-1:0] = {{WIDTH-COUNTER_WIDTH{count1[COUNTER_WIDTH-1]}},count1[COUNTER_WIDTH-1:0]};
wire [7:0] status;
// when force_trigger is asserted put the status byte on the output, everything is free running.
assign status[7:0] = {1'b1,
fired,
value1[COUNTER_WIDTH-1], // overflow
value0[COUNTER_WIDTH-1], // overflow
value1[COUNTER_WIDTH-2],
value0[COUNTER_WIDTH-2],
value1[16], // 16=Ceiling@Log2[166*166]+1
value0[16]};
assign io_out[7:0] = sel[2:0] == 3'b000 ? 8'd0 :
sel[2:0] == 3'b001 ? {value0[7:0]} :
sel[2:0] == 3'b010 ? {value0[15:8]} :
sel[2:0] == 3'b011 ? {value0[23:16]} :
sel[2:0] == 3'b100 ? {value1[7:0]} :
sel[2:0] == 3'b101 ? {value1[15:8]} :
sel[2:0] == 3'b110 ? {value1[23:16]} :
status[7:0] ;
endmodule |
module loxodes_sequencer (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire enable = io_in[2];
wire [4:0] delay;
assign delay = io_in[7:3];
wire [7:0] channel;
assign io_out[7:0] = channel;
assign channel = channel_state;
reg [4:0] counter;
reg [7:0] channel_state;
reg [3:0] channel_index;
always @(posedge clk) begin
// if reset, set counter to 0
if (reset) begin
counter <= 0;
channel_state <= 0;
channel_index <= 0;
end else begin
if (enable) begin
if (counter == delay && channel_index < 8) begin
counter <= 0;
channel_index <= channel_index + 1'b1;
channel_state <= channel_state + (1'b1 << channel_index);
end else begin
counter <= counter + 1'b1;
end
end else begin
if (counter == delay && channel_index > 0) begin
counter <= 0;
channel_index <= channel_index - 1'b1;
channel_state <= (channel_state >> 1);
end else begin
counter <= counter + 1'b1;
end
end
end
end
endmodule |
module user_module_348260124451668562(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5;
wire net6;
wire net7;
wire net8 = 1'b1;
wire net9 = 1'b0;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net20;
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26 = 1'b1;
wire net27;
wire net28;
wire net29;
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
wire net39;
wire net40;
wire net41;
wire net42;
wire net43;
wire net44;
wire net45 = 1'b1;
wire net46;
wire net47 = 1'b1;
assign io_out[0] = net1;
assign io_out[1] = net5;
assign io_out[2] = net6;
assign io_out[3] = net7;
dff_cell flop1 (
.d (net10),
.clk (net1),
.q (net11)
);
dff_cell flop2 (
.d (net11),
.clk (net1),
.q (net12)
);
dff_cell flop3 (
.d (net12),
.clk (net1),
.q (net13)
);
dff_cell flop4 (
.d (net13),
.clk (net1),
.q (net14)
);
dff_cell flop5 (
.d (net14),
.clk (net1),
.q (net15)
);
dff_cell flop6 (
.d (net15),
.clk (net1),
.q (net16)
);
dff_cell flop7 (
.d (net16),
.clk (net1),
.q (net17)
);
dff_cell flop8 (
.d (net17),
.clk (net1),
.q (net18)
);
dff_cell flop9 (
.d (net18),
.clk (net1),
.q (net19)
);
dff_cell flop10 (
.d (net19),
.clk (net1),
.q (net20)
);
dff_cell flop11 (
.d (net20),
.clk (net1),
.q (net21)
);
dff_cell flop12 (
.d (net21),
.clk (net1),
.q (net22)
);
dff_cell flop13 (
.d (net22),
.clk (net1),
.q (net23)
);
dff_cell flop14 (
.d (net23),
.clk (net1),
.q (net24)
);
dff_cell flop15 (
.d (net24),
.clk (net1),
.q (net5)
);
xor_cell xor1 (
.a (net5),
.b (net24),
.out (net25)
);
xor_cell xor2 (
.a (net25),
.b (net26),
.out (net27)
);
mux_cell mux1 (
.a (net2),
.b (net27),
.sel (net3),
.out (net10)
);
dff_cell flop16 (
.d (net28),
.clk (net1),
.q (net29)
);
dff_cell flop17 (
.d (net29),
.clk (net1),
.q (net30)
);
dff_cell flop18 (
.d (net30),
.clk (net1),
.q (net31)
);
dff_cell flop19 (
.d (net31),
.clk (net1),
.q (net32)
);
dff_cell flop20 (
.d (net32),
.clk (net1),
.q (net33)
);
dff_cell flop21 (
.d (net33),
.clk (net1),
.q (net34)
);
dff_cell flop22 (
.d (net34),
.clk (net1),
.q (net35)
);
dff_cell flop23 (
.d (net35),
.clk (net1),
.q (net36)
);
dff_cell flop24 (
.d (net36),
.clk (net1),
.q (net37)
);
dff_cell flop25 (
.d (net37),
.clk (net1),
.q (net38)
);
dff_cell flop26 (
.d (net38),
.clk (net1),
.q (net39)
);
dff_cell flop27 (
.d (net39),
.clk (net1),
.q (net40)
);
dff_cell flop28 (
.d (net40),
.clk (net1),
.q (net41)
);
dff_cell flop29 (
.d (net41),
.clk (net1),
.q (net42)
);
dff_cell flop30 (
.d (net42),
.clk (net1),
.q (net43)
);
xor_cell xor3 (
.a (net43),
.b (net42),
.out (net44)
);
xor_cell xor4 (
.a (net44),
.b (net45),
.out (net7)
);
not_cell not1 (
.in (net4),
.out (net28)
);
xor_cell xor5 (
.a (net7),
.b (net28),
.out (net46)
);
xor_cell xor6 (
.a (net46),
.b (net47),
.out (net6)
);
endmodule |
module github_com_proppy_tt02_xls_counter(
input wire [7:0] io_in,
output wire [7:0] io_out
);
wire rdy = 1;
wire vld;
user_module counter0(io_in[0], io_in[1], rdy, io_out, vld);
endmodule |
module tholin_avalonsemi_tbb1143(
input [7:0] io_in,
output [7:0] io_out
);
wire s_A0 = io_in[6];
wire s_CLK = io_in[0];
wire s_D0 = io_in[2];
wire s_D1 = io_in[3];
wire s_D2 = io_in[4];
wire s_D3 = io_in[5];
wire s_RST = io_in[1];
wire s_WR = io_in[7];
wire [5:0] s_SOUT;
wire LED0;
wire LED1;
assign io_out[5:0] = s_SOUT;
assign io_out[6] = LED0;
assign io_out[7] = LED1;
reg [4:0] shifter;
always @(posedge s_CLK)
begin
shifter[4:1] <= shifter[3:0];
shifter[0] <= ~s_RST;
end
wire c2_1, c2_2, c2_3, c2_4, c2_5;
assign c2_1 = c2_5 & shifter[0];
assign c2_2 = c2_1 & shifter[1];
assign c2_3 = c2_2 & shifter[2];
assign c2_4 = c2_3 & shifter[3];
assign c2_5 = c2_4 & shifter[4];
main CIRCUIT_0 (.A0(s_A0),
.CLK(s_CLK),
.D0(s_D0),
.D1(s_D1),
.D2(s_D2),
.D3(s_D3),
.FCLK(c2_5),
.RST(s_RST),
.WR(s_WR),
.S0(s_SOUT[0]),
.S1(s_SOUT[1]),
.S2(s_SOUT[2]),
.S3(s_SOUT[3]),
.S4(s_SOUT[4]),
.S5(s_SOUT[5]),
.LED0(LED0),
.LED1(LED1)
);
endmodule |
module user_module_346916357828248146(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17 = 1'b0;
wire net18 = 1'b1;
wire net19 = 1'b1;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net11;
assign io_out[3] = net12;
assign io_out[4] = net13;
assign io_out[5] = net14;
assign io_out[6] = net15;
assign io_out[7] = net16;
xor_cell gate3 (
.a (net9),
.b (net4),
.out (net10)
);
nand_cell gate4 (
.a (net10),
.b (net15),
.out (net11)
);
mux_cell mux1 (
.a (net1),
.b (net2),
.sel (net3),
.out (net9)
);
nand_cell nand1 (
.a (net14),
.b (net11),
.out (net15)
);
mux_cell mux2 (
.a (net5),
.b (net6),
.sel (net7),
.out (net13)
);
xor_cell xor1 (
.a (net13),
.b (net8),
.out (net14)
);
dff_cell flop1 (
.d (net14),
.clk (net10),
.q (net12),
.notq (net16)
);
endmodule |
module user_module_349813388252021330(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[6];
wire net5 = io_in[7];
wire net6;
wire net7;
wire net8;
wire net9 = 1'b1;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
assign io_out[0] = net6;
assign io_out[1] = net7;
assign io_out[2] = net8;
and_cell gate1 (
.a (net10),
.b (net3),
.out (net11)
);
or_cell gate2 (
.a (net11),
.b (net12),
.out (net6)
);
xor_cell gate3 (
.a (net10),
.b (net3),
.out (net13)
);
xor_cell gate7 (
.a (net1),
.b (net2),
.out (net10)
);
and_cell gate4 (
.a (net1),
.b (net3),
.out (net12)
);
and_cell gate5 (
.a (net14),
.b (net5),
.out (net15)
);
or_cell gate6 (
.a (net15),
.b (net16),
.out (net7)
);
xor_cell gate8 (
.a (net14),
.b (net5),
.out (net8)
);
xor_cell gate9 (
.a (net13),
.b (net4),
.out (net14)
);
and_cell gate10 (
.a (net13),
.b (net5),
.out (net16)
);
endmodule |
module thezoq2_yafpga (
input [7:0] io_in,
output [7:0] io_out
);
wire[3:0] dummy;
e_main main
( .clk_i(io_in[0])
, .cfg_value_i(io_in[1])
, .cfg_clk_i(io_in[2])
, .inputs_unsync_i(io_in[7:3])
, .output__({dummy, io_out[3:0]})
);
endmodule |
module mbikovitsky_top #(
parameter CLOCK_HZ = 625,
parameter BAUD = 78,
parameter ROM_WORDS = 4
) (
input [7:0] io_in,
output [7:0] io_out
);
localparam LFSR_BITS = 5;
wire clk = io_in[0];
wire mode_cpu = reset_lfsr & reset_taps;
assign io_out = mode_cpu ? cpu_io_out[7:0] : segments;
//
// LFSR
//
wire reset_lfsr = io_in[1];
wire reset_taps = io_in[2];
wire [LFSR_BITS-1:0] data_in = io_in[3+LFSR_BITS-1:3];
wire [7:0] segments;
seven_segment seven_segment (
.value_i(lfsr_out),
.segments_o(segments)
);
wire [LFSR_BITS-1:0] lfsr_out;
lfsr #(.BITS(LFSR_BITS), .TICKS(CLOCK_HZ)) lfsr(
.clk(clk),
.reset_lfsr_i(reset_lfsr),
.initial_state_i(data_in),
.reset_taps_i(reset_taps),
.taps_i(data_in),
.state_o(lfsr_out)
);
//
// CPU
//
wire cpu_reset = (!mode_cpu) || (mode_cpu && io_in[3]);
wire mem_reset = (!mode_cpu) || (mode_cpu && io_in[4]);
wire uart_reset = (!mode_cpu) || (mode_cpu && io_in[6]);
wire uart_rx = io_in[5];
CPU cpu (
.clk(clk),
.reset(cpu_reset),
.instruction(instruction),
.next_instruction_addr_o(next_instruction_addr),
.memory_we_o(memory_we),
.memory_i(cpu_io_out),
.memory_o(cpu_memory_out)
);
wire [15:0] instruction;
wire [14:0] next_instruction_addr;
wire memory_we;
wire [15:0] cpu_memory_out;
// All memory reads and writes always go to (cpu_io_out), regardless
// of the address output by the CPU.
// I/O output
reg [15:0] cpu_io_out;
always @(posedge clk) begin
if (mem_reset) begin
cpu_io_out <= 0;
end else begin
if (!cpu_reset && memory_we) begin
cpu_io_out <= cpu_memory_out;
end
end
end
// PROM
reg [16-1:0] prom [ROM_WORDS];
assign instruction = prom[next_instruction_addr[$clog2(ROM_WORDS)-1:0]];
// UART to fill the PROM
UART #(
.CLOCK_HZ(CLOCK_HZ),
.BAUD(BAUD)
) uart(
.reset(uart_reset),
.clk(clk),
.rx_i(uart_rx),
.rx_data_o(rx_data),
.rx_ready_o(rx_ready),
.rx_ack_i(1'b1)
);
wire [7:0] rx_data;
wire rx_ready;
reg [$clog2(ROM_WORDS)-1:0] uart_write_address;
reg [0:0] uart_state;
localparam UART_RECEIVE_LOW = 2'd0,
UART_RECEIVE_HIGH = 2'd1;
always @(posedge clk) begin
if (uart_reset) begin
uart_write_address <= 0;
uart_state <= UART_RECEIVE_LOW;
end else begin
case (uart_state)
UART_RECEIVE_LOW: begin
if (rx_ready) begin
prom[uart_write_address][7:0] <= rx_data;
uart_state <= UART_RECEIVE_HIGH;
end
end
UART_RECEIVE_HIGH: begin
if (rx_ready) begin
prom[uart_write_address][15:8] <= rx_data;
uart_state <= UART_RECEIVE_LOW;
if (uart_write_address == ROM_WORDS - 1) begin
uart_write_address <= 0;
end else begin
uart_write_address <= uart_write_address + 1;
end
end
end
endcase
end
end
endmodule |
module option23ser (
input wire [7:0] io_in,
output reg [7:0] io_out
);
parameter WORD_COUNT = 30;
wire clk = io_in[0];
wire reset = io_in[1];
wire write = io_in[2];
wire din = io_in[3];
wire under = io_in[4];
wire over = io_in[5];
reg [2:0] counter;
reg [7 * WORD_COUNT - 1: 0] buffer;
always@(posedge clk or posedge reset) begin
if(reset)
counter <= 3'd0;
else begin
if(counter == 3'b111 || (!write && !buffer[6]))
buffer[7 * WORD_COUNT - 1 - 7:0] <= buffer[7 * WORD_COUNT - 1:7];
if(!(counter == 3'b111) && write)
buffer[7 * WORD_COUNT - 1:7 * WORD_COUNT - 7] <= {din, buffer[7 * WORD_COUNT - 1:7 * WORD_COUNT - 7 +1]};
if(counter == 3'b111 || (!write && !buffer[6]))
buffer[7 * WORD_COUNT - 1:7 * WORD_COUNT - 7] <= buffer[6:0];
if(counter == 3'b111 || (!write && !buffer[6]))
counter <= 3'd0;
else
counter <= counter + 1'd1;
end
end
always @ (buffer[6:0] or over or under or counter[2:0]) begin
if(!buffer[6])
io_out <= {under, buffer[5:0], over};
else
case({buffer[5:0], counter[2:0]})
9'b000001010: io_out <= 8'b00000110;
9'b000001011: io_out <= 8'b01011111;
9'b000001100: io_out <= 8'b00000110;
9'b000010010: io_out <= 8'b00000111;
9'b000010101: io_out <= 8'b00000111;
9'b000011001: io_out <= 8'b00010100;
9'b000011010: io_out <= 8'b01111111;
9'b000011011: io_out <= 8'b00010100;
9'b000011100: io_out <= 8'b00010100;
9'b000011101: io_out <= 8'b01111111;
9'b000011110: io_out <= 8'b00010100;
9'b000101001: io_out <= 8'b01000110;
9'b000101010: io_out <= 8'b00100110;
9'b000101011: io_out <= 8'b00010000;
9'b000101100: io_out <= 8'b00001000;
9'b000101101: io_out <= 8'b01100100;
9'b000101110: io_out <= 8'b01100010;
9'b000111010: io_out <= 8'b00000100;
9'b000111011: io_out <= 8'b00000011;
9'b001011001: io_out <= 8'b00001000;
9'b001011010: io_out <= 8'b00001000;
9'b001011011: io_out <= 8'b00111110;
9'b001011100: io_out <= 8'b00001000;
9'b001011101: io_out <= 8'b00001000;
9'b001100010: io_out <= 8'b10000000;
9'b001100011: io_out <= 8'b01100000;
9'b001101001: io_out <= 8'b00001000;
9'b001101010: io_out <= 8'b00001000;
9'b001101011: io_out <= 8'b00001000;
9'b001101100: io_out <= 8'b00001000;
9'b001101101: io_out <= 8'b00001000;
9'b001101110: io_out <= 8'b00001000;
9'b001110011: io_out <= 8'b01100000;
9'b001111001: io_out <= 8'b01000000;
9'b001111010: io_out <= 8'b00100000;
9'b001111011: io_out <= 8'b00010000;
9'b001111100: io_out <= 8'b00001000;
9'b001111101: io_out <= 8'b00000100;
9'b001111110: io_out <= 8'b00000010;
9'b010000001: io_out <= 8'b00111110;
9'b010000010: io_out <= 8'b01100001;
9'b010000011: io_out <= 8'b01010001;
9'b010000100: io_out <= 8'b01001001;
9'b010000101: io_out <= 8'b01000101;
9'b010000110: io_out <= 8'b00111110;
9'b010001001: io_out <= 8'b01000100;
9'b010001010: io_out <= 8'b01000010;
9'b010001011: io_out <= 8'b01111111;
9'b010001100: io_out <= 8'b01000000;
9'b010001101: io_out <= 8'b01000000;
9'b010010001: io_out <= 8'b01100010;
9'b010010010: io_out <= 8'b01010001;
9'b010010011: io_out <= 8'b01010001;
9'b010010100: io_out <= 8'b01001001;
9'b010010101: io_out <= 8'b01001001;
9'b010010110: io_out <= 8'b01100110;
9'b010011001: io_out <= 8'b00100010;
9'b010011010: io_out <= 8'b01000001;
9'b010011011: io_out <= 8'b01001001;
9'b010011100: io_out <= 8'b01001001;
9'b010011101: io_out <= 8'b01001001;
9'b010011110: io_out <= 8'b00110110;
9'b010100000: io_out <= 8'b00010000;
9'b010100001: io_out <= 8'b00011000;
9'b010100010: io_out <= 8'b00010100;
9'b010100011: io_out <= 8'b01010010;
9'b010100100: io_out <= 8'b01111111;
9'b010100101: io_out <= 8'b01010000;
9'b010100110: io_out <= 8'b00010000;
9'b010101001: io_out <= 8'b00100111;
9'b010101010: io_out <= 8'b01000101;
9'b010101011: io_out <= 8'b01000101;
9'b010101100: io_out <= 8'b01000101;
9'b010101101: io_out <= 8'b01000101;
9'b010101110: io_out <= 8'b00111001;
9'b010110001: io_out <= 8'b00111100;
9'b010110010: io_out <= 8'b01001010;
9'b010110011: io_out <= 8'b01001001;
9'b010110100: io_out <= 8'b01001001;
9'b010110101: io_out <= 8'b01001001;
9'b010110110: io_out <= 8'b00110000;
9'b010111001: io_out <= 8'b00000011;
9'b010111010: io_out <= 8'b00000001;
9'b010111011: io_out <= 8'b01110001;
9'b010111100: io_out <= 8'b00001001;
9'b010111101: io_out <= 8'b00000101;
9'b010111110: io_out <= 8'b00000011;
9'b011000001: io_out <= 8'b00110110;
9'b011000010: io_out <= 8'b01001001;
9'b011000011: io_out <= 8'b01001001;
9'b011000100: io_out <= 8'b01001001;
9'b011000101: io_out <= 8'b01001001;
9'b011000110: io_out <= 8'b00110110;
9'b011001001: io_out <= 8'b00000110;
9'b011001010: io_out <= 8'b01001001;
9'b011001011: io_out <= 8'b01001001;
9'b011001100: io_out <= 8'b01001001;
9'b011001101: io_out <= 8'b00101001;
9'b011001110: io_out <= 8'b00011110;
9'b011010011: io_out <= 8'b01100110;
9'b011011010: io_out <= 8'b10000000;
9'b011011011: io_out <= 8'b01100110;
9'b011111001: io_out <= 8'b00000010;
9'b011111010: io_out <= 8'b00000001;
9'b011111011: io_out <= 8'b00000001;
9'b011111100: io_out <= 8'b01010001;
9'b011111101: io_out <= 8'b00001001;
9'b011111110: io_out <= 8'b00000110;
9'b100000001: io_out <= 8'b00111110;
9'b100000010: io_out <= 8'b01000001;
9'b100000011: io_out <= 8'b01011101;
9'b100000100: io_out <= 8'b01010101;
9'b100000101: io_out <= 8'b01010101;
9'b100000110: io_out <= 8'b00011110;
9'b100001001: io_out <= 8'b01111100;
9'b100001010: io_out <= 8'b00010010;
9'b100001011: io_out <= 8'b00010001;
9'b100001100: io_out <= 8'b00010001;
9'b100001101: io_out <= 8'b00010010;
9'b100001110: io_out <= 8'b01111100;
9'b100010001: io_out <= 8'b01000001;
9'b100010010: io_out <= 8'b01111111;
9'b100010011: io_out <= 8'b01001001;
9'b100010100: io_out <= 8'b01001001;
9'b100010101: io_out <= 8'b01001001;
9'b100010110: io_out <= 8'b00110110;
9'b100011001: io_out <= 8'b00011100;
9'b100011010: io_out <= 8'b00100010;
9'b100011011: io_out <= 8'b01000001;
9'b100011100: io_out <= 8'b01000001;
9'b100011101: io_out <= 8'b01000001;
9'b100011110: io_out <= 8'b00100010;
9'b100100001: io_out <= 8'b01000001;
9'b100100010: io_out <= 8'b01111111;
9'b100100011: io_out <= 8'b01000001;
9'b100100100: io_out <= 8'b01000001;
9'b100100101: io_out <= 8'b00100010;
9'b100100110: io_out <= 8'b00011100;
9'b100101001: io_out <= 8'b01000001;
9'b100101010: io_out <= 8'b01111111;
9'b100101011: io_out <= 8'b01001001;
9'b100101100: io_out <= 8'b01011101;
9'b100101101: io_out <= 8'b01000001;
9'b100101110: io_out <= 8'b01100011;
9'b100110001: io_out <= 8'b01000001;
9'b100110010: io_out <= 8'b01111111;
9'b100110011: io_out <= 8'b01001001;
9'b100110100: io_out <= 8'b00011101;
9'b100110101: io_out <= 8'b00000001;
9'b100110110: io_out <= 8'b00000011;
9'b100111001: io_out <= 8'b00011100;
9'b100111010: io_out <= 8'b00100010;
9'b100111011: io_out <= 8'b01000001;
9'b100111100: io_out <= 8'b01010001;
9'b100111101: io_out <= 8'b01010001;
9'b100111110: io_out <= 8'b01110010;
9'b101000001: io_out <= 8'b01111111;
9'b101000010: io_out <= 8'b00001000;
9'b101000011: io_out <= 8'b00001000;
9'b101000100: io_out <= 8'b00001000;
9'b101000101: io_out <= 8'b00001000;
9'b101000110: io_out <= 8'b01111111;
9'b101001010: io_out <= 8'b01000001;
9'b101001011: io_out <= 8'b01111111;
9'b101001100: io_out <= 8'b01000001;
9'b101010001: io_out <= 8'b00110000;
9'b101010010: io_out <= 8'b01000000;
9'b101010011: io_out <= 8'b01000000;
9'b101010100: io_out <= 8'b01000001;
9'b101010101: io_out <= 8'b00111111;
9'b101010110: io_out <= 8'b00000001;
9'b101011001: io_out <= 8'b01000001;
9'b101011010: io_out <= 8'b01111111;
9'b101011011: io_out <= 8'b00001000;
9'b101011100: io_out <= 8'b00010100;
9'b101011101: io_out <= 8'b00100010;
9'b101011110: io_out <= 8'b01000001;
9'b101011111: io_out <= 8'b01000000;
9'b101100001: io_out <= 8'b01000001;
9'b101100010: io_out <= 8'b01111111;
9'b101100011: io_out <= 8'b01000001;
9'b101100100: io_out <= 8'b01000000;
9'b101100101: io_out <= 8'b01000000;
9'b101100110: io_out <= 8'b01100000;
9'b101101001: io_out <= 8'b01111111;
9'b101101010: io_out <= 8'b00000001;
9'b101101011: io_out <= 8'b00000010;
9'b101101100: io_out <= 8'b00000100;
9'b101101101: io_out <= 8'b00000010;
9'b101101110: io_out <= 8'b00000001;
9'b101101111: io_out <= 8'b01111111;
9'b101110001: io_out <= 8'b01111111;
9'b101110010: io_out <= 8'b00000001;
9'b101110011: io_out <= 8'b00000010;
9'b101110100: io_out <= 8'b00000100;
9'b101110101: io_out <= 8'b00001000;
9'b101110110: io_out <= 8'b01111111;
9'b101111001: io_out <= 8'b00011100;
9'b101111010: io_out <= 8'b00100010;
9'b101111011: io_out <= 8'b01000001;
9'b101111100: io_out <= 8'b01000001;
9'b101111101: io_out <= 8'b00100010;
9'b101111110: io_out <= 8'b00011100;
9'b110000001: io_out <= 8'b01000001;
9'b110000010: io_out <= 8'b01111111;
9'b110000011: io_out <= 8'b01001001;
9'b110000100: io_out <= 8'b00001001;
9'b110000101: io_out <= 8'b00001001;
9'b110000110: io_out <= 8'b00000110;
9'b110001001: io_out <= 8'b00011110;
9'b110001010: io_out <= 8'b00100001;
9'b110001011: io_out <= 8'b00100001;
9'b110001100: io_out <= 8'b00110001;
9'b110001101: io_out <= 8'b00100001;
9'b110001110: io_out <= 8'b01011110;
9'b110001111: io_out <= 8'b01000000;
9'b110010001: io_out <= 8'b01000001;
9'b110010010: io_out <= 8'b01111111;
9'b110010011: io_out <= 8'b01001001;
9'b110010100: io_out <= 8'b00011001;
9'b110010101: io_out <= 8'b00101001;
9'b110010110: io_out <= 8'b01000110;
9'b110011001: io_out <= 8'b00100110;
9'b110011010: io_out <= 8'b01001001;
9'b110011011: io_out <= 8'b01001001;
9'b110011100: io_out <= 8'b01001001;
9'b110011101: io_out <= 8'b01001001;
9'b110011110: io_out <= 8'b00110010;
9'b110100001: io_out <= 8'b00000011;
9'b110100010: io_out <= 8'b00000001;
9'b110100011: io_out <= 8'b01000001;
9'b110100100: io_out <= 8'b01111111;
9'b110100101: io_out <= 8'b01000001;
9'b110100110: io_out <= 8'b00000001;
9'b110100111: io_out <= 8'b00000011;
9'b110101001: io_out <= 8'b00111111;
9'b110101010: io_out <= 8'b01000000;
9'b110101011: io_out <= 8'b01000000;
9'b110101100: io_out <= 8'b01000000;
9'b110101101: io_out <= 8'b01000000;
9'b110101110: io_out <= 8'b00111111;
9'b110110001: io_out <= 8'b00001111;
9'b110110010: io_out <= 8'b00010000;
9'b110110011: io_out <= 8'b00100000;
9'b110110100: io_out <= 8'b01000000;
9'b110110101: io_out <= 8'b00100000;
9'b110110110: io_out <= 8'b00010000;
9'b110110111: io_out <= 8'b00001111;
9'b110111001: io_out <= 8'b00111111;
9'b110111010: io_out <= 8'b01000000;
9'b110111011: io_out <= 8'b01000000;
9'b110111100: io_out <= 8'b00111000;
9'b110111101: io_out <= 8'b01000000;
9'b110111110: io_out <= 8'b01000000;
9'b110111111: io_out <= 8'b00111111;
9'b111000001: io_out <= 8'b01000001;
9'b111000010: io_out <= 8'b00100010;
9'b111000011: io_out <= 8'b00010100;
9'b111000100: io_out <= 8'b00001000;
9'b111000101: io_out <= 8'b00010100;
9'b111000110: io_out <= 8'b00100010;
9'b111000111: io_out <= 8'b01000001;
9'b111001001: io_out <= 8'b00000001;
9'b111001010: io_out <= 8'b00000010;
9'b111001011: io_out <= 8'b01000100;
9'b111001100: io_out <= 8'b01111000;
9'b111001101: io_out <= 8'b01000100;
9'b111001110: io_out <= 8'b00000010;
9'b111001111: io_out <= 8'b00000001;
9'b111010001: io_out <= 8'b01000011;
9'b111010010: io_out <= 8'b01100001;
9'b111010011: io_out <= 8'b01010001;
9'b111010100: io_out <= 8'b01001001;
9'b111010101: io_out <= 8'b01000101;
9'b111010110: io_out <= 8'b01000011;
9'b111010111: io_out <= 8'b01100001;
default: io_out <= 8'b00000000;
endcase;
end
endmodule |
module prog_melody_gen (
input [7:0] io_in,
output [7:0] io_out
);
reg [9:0] div_tmr = 0;
reg tick;
reg state;
reg [7:0] curr_tone;
reg [5:0] tone_seq;
wire [3:0] rom_rdata;
wire clock = io_in[0];
wire reload = io_in[1];
wire restart = io_in[2];
wire pgm_data = io_in[3];
wire pgm_strobe = io_in[4];
assign io_out[7:1] = 1'b0;
always @(posedge clock, posedge restart) begin
if (restart) begin
div_tmr <= 0;
tone_seq <= 0;
curr_tone <= 0;
tick <= 1'b0;
state <= 1'b0;
end else begin
{tick, div_tmr} <= div_tmr + 1'b1;
if (tick) begin
if (!state) begin
tone_seq <= tone_seq + 1'b1;
if (rom_rdata == 15)
curr_tone <= 0; // silence
else
curr_tone <= 12 + rom_rdata; // note
end else begin
curr_tone <= 0; // gap between notes
end
state <= ~state;
end
end
end
reg [7:0] mel_gen = 0;
reg mel_out;
always @(posedge clock) begin
if (mel_gen >= curr_tone)
mel_gen <= 0;
else
mel_gen <= mel_gen + 1'b1;
mel_out <= mel_gen > (curr_tone / 2);
end
assign io_out[0] = mel_out;
localparam C = 4'd11, CS = 4'd10, D = 4'd9, E = 4'd7, F = 4'd6, FS = 4'd5, G = 4'd4, GS = 4'd3, A = 4'd2, AS = 4'd1, B = 4'd0, S = 4'd15;
localparam [4*64:0] JINGLE_BELS = {
E, E, E, S, E, E, E, S,
E, G, C, D, E, S, F, F,
F, F, F, E, E, E, E, E,
D, D, E, D, S, G, S, E,
E, E, S, E, E, E, S, E,
G, C, D, E, S, F, F, F,
F, F, E, E, E, E, F, F,
E, D, C, S, S, S, S, S
};
wire [3:0] tone_rom[0:63];
// program shift register
reg [10:0] write_sr;
always @(posedge clock)
write_sr <= {pgm_data, write_sr[10:1]};
wire [5:0] pgm_word_sel = write_sr[10:5];
wire [3:0] pgm_write_data = write_sr[3:0];
// the tone RAM
generate
genvar ii;
genvar jj;
for (ii = 0; ii < 64; ii = ii + 1'b1) begin : words
wire word_we;
sky130_fd_sc_hd__and2_1 word_we_i ( // make sure this is really glitch free
.A(pgm_word_sel == ii),
.B(pgm_strobe),
.X(word_we)
);
for (jj = 0; jj < 4; jj = jj + 1'b1) begin : bits
localparam pgm_bit = JINGLE_BELS[(63 - ii) * 4 + jj];
wire lat_o;
sky130_fd_sc_hd__dlrtp_1 rfbit_i (
.GATE(word_we),
.RESET_B(reload),
.D(pgm_write_data[jj]),
.Q(lat_o)
);
assign tone_rom[ii][jj] = lat_o ^ pgm_bit;
end
end
endgenerate
assign rom_rdata = tone_rom[tone_seq];
endmodule |
module sky130_fd_sc_hd__and2_1(input A, B, output X);
assign X = A & B;
endmodule |
module seven_segment_seconds #( parameter MAX_COUNT = 1000 ) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
// external clock is 1000Hz, so need 10 bit counter
reg [9:0] second_counter;
reg [3:0] digit;
always @(posedge clk) begin
// if reset, set counter to 0
if (reset) begin
second_counter <= 0;
digit <= 0;
end else begin
// if up to 16e6
if (second_counter == MAX_COUNT) begin
// reset
second_counter <= 0;
// increment digit
digit <= digit + 1'b1;
// only count from 0 to 9
if (digit == 9)
digit <= 0;
end else
// increment counter
second_counter <= second_counter + 1'b1;
end
end
// instantiate segment display
seg7 seg7(.counter(digit), .segments(led_out));
endmodule |
module aramsey118_freq_counter #(
parameter DEPTH = 200
) (
input wire [7:0] io_in,
output wire [7:0] io_out
);
// Precalculate the boundaries
localparam integer freq_0 = $ceil(DEPTH * 0.0); // not used, here for completeness
localparam integer freq_1 = $ceil(DEPTH * 0.1);
localparam integer freq_2 = $ceil(DEPTH * 0.2);
localparam integer freq_3 = $ceil(DEPTH * 0.3);
localparam integer freq_4 = $ceil(DEPTH * 0.4);
localparam integer freq_5 = $ceil(DEPTH * 0.5);
localparam integer freq_6 = $ceil(DEPTH * 0.6);
localparam integer freq_7 = $ceil(DEPTH * 0.7);
localparam integer freq_8 = $ceil(DEPTH * 0.8);
localparam integer freq_9 = $ceil(DEPTH * 0.9);
wire clk = io_in[0];
wire reset = io_in[1];
wire sig = io_in[2];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
assign io_out[7] = sig;
wire [$clog2(DEPTH)-1:0] avg;
reg sig_d1;
reg diff;
reg [3:0] digit;
always @(posedge clk) begin
// if reset, set counter to 0
if (reset) begin
sig_d1 <= 0;
diff <= 0;
digit <= 0;
end else begin
sig_d1 <= sig;
diff <= (sig ^ sig_d1);
if ((avg <= $unsigned(freq_1))) begin
digit <= 0;
end else if ((avg > $unsigned(freq_1)) && (avg <= $unsigned(freq_2))) begin
digit <= 1;
end else if ((avg > $unsigned(freq_2)) && (avg <= $unsigned(freq_3))) begin
digit <= 2;
end else if ((avg > $unsigned(freq_3)) && (avg <= $unsigned(freq_4))) begin
digit <= 3;
end else if ((avg > $unsigned(freq_4)) && (avg <= $unsigned(freq_5))) begin
digit <= 4;
end else if ((avg > $unsigned(freq_5)) && (avg <= $unsigned(freq_6))) begin
digit <= 5;
end else if ((avg > $unsigned(freq_6)) && (avg <= $unsigned(freq_7))) begin
digit <= 6;
end else if ((avg > $unsigned(freq_7)) && (avg <= $unsigned(freq_8))) begin
digit <= 7;
end else if ((avg > $unsigned(freq_8)) && (avg <= $unsigned(freq_9))) begin
digit <= 8;
end else begin
digit <= 9;
end
end
end
// instantiate segment display
seg7 seg7(.counter(digit), .segments(led_out));
// instantiate moving average
moving_avg #(.DEPTH(DEPTH)) moving_avg(.data_i(diff), .reset, .clk, .avg_o(avg));
endmodule |
module razhas_top_level
(
input [7:0] io_in,
output [7:0] io_out
);
wire w_clk = io_in[0];
wire w_rst = io_in[1];
wire [3:0] w_duty = io_in[5:2]; // selects pwm signal duty cycle: 0% to 100% in increments of 10%. Values of 11-15 treated as 100%.
wire [1:0] w_freq = io_in[7:6]; // selects pwm signal frequency: 156.25 Hz, 312.5 Hz, 625 Hz, or 1250 Hz.
wire w_pwm; // pwm signal
assign io_out = {7'b0000000, w_pwm};
pwm_gen u0 (.i_clk(w_clk), .i_rst(w_rst), .i_duty(w_duty), .i_freq(w_freq), .o_pwm(w_pwm));
endmodule |
module vaishnavachath_rotary_toplevel (
input [7:0] io_in,
output [7:0] io_out
);
wire clk_in = io_in[0];
wire reset = io_in[1];
wire rt_a;
wire rt_b;
wire tm_enable = io_in[4];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
reg [3:0] enc_byte = 0;
reg [3:0] counter = 0;
reg rt_a_delayed, rt_b_delayed, clk_msb_delayed;
assign rt_a = tm_enable ? counter[3] : io_in[2];
assign rt_b = tm_enable ? clk_msb_delayed : io_in[3];
wire count_enable = rt_a ^ rt_a_delayed ^ rt_b ^ rt_b_delayed;
wire count_direction = rt_a ^ rt_b_delayed;
always @(posedge clk_in) rt_a_delayed <= rt_a;
always @(posedge clk_in) rt_b_delayed <= rt_b;
always @(posedge clk_in) clk_msb_delayed <= counter[3];
always @(posedge clk_in) begin
if(count_enable) begin
if(count_direction) enc_byte<=enc_byte+1; else enc_byte<=enc_byte-1;
end
end
always @(posedge clk_in) begin
if (reset) begin
counter <= 0;
end else begin
counter <= counter + 1'b1;
end
end
seg7 seg7(.counter(enc_byte), .segments(led_out));
endmodule |
module udxs_sqrt_top(
input [7:0] io_in,
output [7:0] io_out
);
wire [10:0] result;
assign io_out = result[7:0];
udxs_sqrt sqrt_core(
.clk(io_in[0]),
.query({io_in[7:1], 4'b0}),
.result(result)
);
endmodule |
module user_module_341535056611770964(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2 = io_in[1];
wire net3 = io_in[2];
wire net4 = io_in[3];
wire net5 = io_in[4];
wire net6 = io_in[5];
wire net7 = io_in[6];
wire net8 = io_in[7];
wire net9;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17 = 1'b0;
wire net18 = 1'b1;
wire net19 = 1'b1;
assign io_out[0] = net9;
assign io_out[1] = net10;
assign io_out[2] = net11;
assign io_out[3] = net12;
assign io_out[4] = net13;
assign io_out[5] = net14;
assign io_out[6] = net15;
assign io_out[7] = net16;
not_cell not1 (
.in (net1),
.out (net9)
);
not_cell not2 (
.in (net2),
.out (net10)
);
not_cell not3 (
.in (net3),
.out (net11)
);
not_cell not4 (
.in (net4),
.out (net12)
);
and_cell gate1 (
);
or_cell gate2 (
);
xor_cell gate3 (
);
nand_cell gate4 (
);
not_cell gate5 (
);
buffer_cell gate6 (
);
mux_cell mux1 (
);
dff_cell flipflop1 (
);
not_cell not5 (
.in (net5),
.out (net13)
);
not_cell not6 (
.in (net6),
.out (net14)
);
not_cell not7 (
.in (net7),
.out (net15)
);
not_cell not8 (
.in (net8),
.out (net16)
);
endmodule |
module thunderbird_taillight_ctrl #(
parameter MAX_COUNT = 1000,
parameter SYSTEM_FREQ = 6250,
parameter HZ = 8
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire left = io_in[2];
wire right = io_in[3];
wire haz = io_in[4];
wire [5:0] lights = state;
assign io_out[7:0] = {2'b00, lights};
wire div;
divider #(
.SYSTEM_FREQ(SYSTEM_FREQ),
.HZ (HZ)
) divider_i (
.clk (clk),
.reset (reset),
.divider(div)
);
localparam IDLE = 6'b000_000;
localparam L3 = 6'b111_000;
localparam L2 = 6'b011_000;
localparam L1 = 6'b001_000;
localparam R3 = 6'b000_111;
localparam R2 = 6'b000_110;
localparam R1 = 6'b000_100;
localparam LR3 = 6'b111_111;
reg [5:0] state, next_state;
always @(posedge clk) begin
if (reset) begin
state <= IDLE;
end else begin
if (div) begin
state <= next_state;
end
end
end
always @(*) begin
next_state = state;
case (state)
IDLE: begin
case (1'b1)
haz | (left & right): next_state = LR3;
left: next_state = L1;
right: next_state = R1;
default: next_state = IDLE;
endcase
end
L1: next_state = haz ? LR3 : L2;
L2: next_state = haz ? LR3 : L3;
L3: next_state = haz ? LR3 : IDLE;
R1: next_state = haz ? LR3 : R2;
R2: next_state = haz ? LR3 : R3;
R3: next_state = haz ? LR3 : IDLE;
LR3: next_state = IDLE;
default: next_state = state;
endcase
end
endmodule |
module divider #(
parameter SYSTEM_FREQ = 6250,
parameter HZ = 8
) (
input clk,
input reset,
output divider
);
localparam CYCLES = SYSTEM_FREQ / HZ;
reg [$clog2(CYCLES) -1:0] cnt;
always @(posedge clk) begin
if (reset) begin
cnt <= 0;
end else begin
cnt <= cnt + 1;
/* verilator lint_off WIDTH */
if (cnt >= (CYCLES - 1)) begin
cnt <= 0;
end
/* verilator lint_on WIDTH */
end
end
assign divider = cnt == 0;
endmodule |
module rolfmobile99_alu_fsm_top(
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[7];
wire reset = io_in[6];
wire ctl_in = io_in[5];
wire notused = io_in[4];
wire [3:0] databus = io_in[3:0];
assign io_out[4] = aluCout;
assign io_out[3:0] = aluOut[3:0];
wire [2:0] state_out;
wire enA, enB, enM, enC, selC;
wire rst_out;
wire [3:0] aluA, aluB; // tmp: to alu A input
wire aluCout;
wire aluZ; // notused
wire [3:0] aluOut;
wire [3:0] aluOp; // bit0: add=0, sub=1 bit1: enCin bit2,3: unused
wire op0; // bit0 of above
assign op0 = aluOp[0];
// connect modules
alu_fsm alu_fsm(
.ctl(ctl_in),
.curstate(state_out),
.rst_out(rst_out),
.enA(enA),
.enB(enB),
.enM(enM),
.enC(enC),
.selC(selC),
.reset(reset),
.clk(clk) ); // clk with 'clk' signal
flop_4 regA(
.dd(databus),
.qq(aluA),
.qEn(1'b1), // always enable output
.reset(rst_out),// clear on reset state
.cEn(enA),
.clk(clk) ); // clk with 'clk' signal
flop_4 regB(
.dd(databus),
.qq(aluB),
.qEn(1'b1), // always enable output
.reset(rst_out),// clear on reset state
.cEn(enB),
.clk(clk) ); // clk with 'clk' signal
flop_4 regM(
.dd(databus),
.qq(aluOp), // note: regM drives aluOp lines
.qEn(1'b1), // always enable output
.reset(rst_out),// clear on reset state
.cEn(enM),
.clk(clk) ); // clk with 'clk' signal
alu_4 alu(
.op(op0), // controls add/sub
.a(aluA),
.b(aluB),
.cin(1'b0), // tmp: carryin=0
.out(aluOut),
.z(aluZ), // alu zero (notused)
.cout(aluCout),
.outEn(1'b1) ); // always enable output
endmodule |
module migcorre_pwm (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0]; // clock input 12.5KHz
wire reset = io_in[1]; // reset active high
wire increase_duty_in = io_in[2]; // increase duty cycle by 10%
wire decrease_duty_in = io_in[3]; // decrease duty cycle by 10%
wire disable_debouncer_in = io_in[4];
wire pwm_out; // 1.2kHz PWM output signal
wire increase_duty_sync;
wire decrease_duty_sync;
wire disable_debouncer_sync;
wire increase_duty_deb;
wire decrease_duty_deb;
wire increase_duty;
wire decrease_duty;
// Sinchronizers ------------------------/
synchronizer #(
.NUM_STAGES(2)
) synchronizer_increase_duty (
.clk(clk),
.async_in(increase_duty_in),
.sync_out(increase_duty_sync)
);
synchronizer #(
.NUM_STAGES(2)
) synchronizer_decrease_duty (
.clk(clk),
.async_in(decrease_duty_in),
.sync_out(decrease_duty_sync)
);
synchronizer #(
.NUM_STAGES(2)
) synchronizer_sisable_debouncer (
.clk(clk),
.async_in(disable_debouncer_in),
.sync_out(disable_debouncer_sync)
);
// Debuncers ------------------------/
debouncer #(
.N(8)
) increase_debuncer (
.clk(clk),
.reset(reset),
.signal_in(increase_duty_sync),
.signal_out(increase_duty_deb)
);
debouncer #(
.N(8)
) decrease_debuncer (
.clk(clk),
.reset(reset),
.signal_in(decrease_duty_sync),
.signal_out(decrease_duty_deb)
);
assign increase_duty = disable_debouncer_sync == 1 ? increase_duty_sync : increase_duty_deb;
assign decrease_duty = disable_debouncer_sync == 1 ? decrease_duty_sync : decrease_duty_deb;
// PWM ------------------------/
pwm #(
.INITIAL_DUTY(5)
) pwm_dc (
.clk(clk),
.reset(reset),
.increase_duty_in(increase_duty),
.decrease_duty_in(decrease_duty),
.pwm_out(pwm_out)
);
assign io_out[0] = pwm_out;
assign io_out[1] = ~pwm_out;
assign io_out[2] = increase_duty_sync;
assign io_out[3] = decrease_duty_sync;
endmodule |
module davidsiaw_stackcalc (
input wire [7:0] io_in,
output wire [7:0] io_out
);
stack_cpu cpu(.io_in(io_in), .io_out(io_out));
endmodule |
module user_module_349886696875098706(
input [7:0] io_in,
output [7:0] io_out
);
wire net1 = io_in[0];
wire net2;
wire net3;
wire net4;
wire net5;
wire net6 = 1'b1;
wire net7;
wire net8 = 1'b0;
wire net9 = 1'b0;
wire net10 = 1'b1;
wire net11 = 1'b1;
wire net12;
wire net13;
wire net14;
wire net15 = 1'b0;
wire net16 = 1'b0;
assign io_out[0] = net2;
assign io_out[1] = net3;
assign io_out[2] = net3;
assign io_out[3] = net4;
assign io_out[4] = net5;
assign io_out[5] = net6;
assign io_out[6] = net7;
assign io_out[7] = net8;
and_cell gate1 (
);
or_cell gate2 (
);
xor_cell gate3 (
);
nand_cell gate4 (
);
not_cell gate5 (
);
buffer_cell gate6 (
);
mux_cell mux1 (
);
dff_cell flipflop1 (
);
dff_cell flipflop2 (
.d (net12),
.clk (net1),
.q (net3),
.notq (net13)
);
dff_cell flipflop3 (
.d (net13),
.clk (net1),
.q (net12),
.notq (net14)
);
nand_cell gate7 (
.a (net13),
.b (net12),
.out (net2)
);
nand_cell gate8 (
.a (net3),
.b (net12),
.out (net4)
);
nand_cell gate9 (
.a (net3),
.b (net14),
.out (net5)
);
nand_cell gate10 (
.a (net13),
.b (net14),
.out (net7)
);
endmodule |
module cchan_fp8_multiplier (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire [2:0] ctrl = io_in[3:1];
wire [3:0] data = io_in[7:4];
// wire [6:0] led_out;
// assign io_out[6:0] = led_out;
// wire [5:0] seed_input = io_in[7:2];
reg [8:0] operand1;
reg [8:0] operand2;
// For now we're commenting this out and leaving the results unbuffered.
// reg [8:0] result_out;
// assign io_out = result_out;
always @(posedge clk) begin
if (!ctrl[0]) begin // if first CTRL bit is off, we're in STORE mode
if (!ctrl[1]) begin // second CTRL bit controls whether it's the first or second operand
if (!ctrl[2]) begin // third CTRL bit controls whether it's the upper or lower half
operand1[3:0] <= data;
end else begin
operand1[7:4] <= data;
end
end else begin
if (!ctrl[2]) begin
operand2[3:0] <= data;
end else begin
operand2[7:4] <= data;
end
end
end else begin // if first CTRL bit is on, this is reserved.
// TODO
// if (!ctrl[1] && !ctrl[2]) begin
// result_out[7:0] <= 0;
// end
end
end
// Compute result_out in terms of operand1, operand2
fp8mul mul1(
.sign1(operand1[7]),
.exp1(operand1[6:3]),
.mant1(operand1[2:0]),
.sign2(operand2[7]),
.exp2(operand2[6:3]),
.mant2(operand2[2:0]),
.sign_out(io_out[7]),
.exp_out(io_out[6:3]),
.mant_out(io_out[2:0])
);
endmodule |
module fp8mul (
input sign1,
input [3:0] exp1,
input [2:0] mant1,
input sign2,
input [3:0] exp2,
input [2:0] mant2,
output sign_out,
output [3:0] exp_out,
output [2:0] mant_out
);
parameter EXP_BIAS = 7;
wire isnan = (sign1 == 1 && exp1 == 0 && mant1 == 0) || (sign2 == 1 && exp2 == 0 && mant2 == 0);
wire [7:0] full_mant = ({exp1 != 0, mant1} * {exp2 != 0, mant2});
wire overflow_mant = full_mant[7];
wire [6:0] shifted_mant = overflow_mant ? full_mant[6:0] : {full_mant[5:0], 1'b0};
// is the mantissa overflowing up to the next exponent?
wire roundup = (exp1 + exp2 + overflow_mant < 1 + EXP_BIAS) && (shifted_mant[6:0] != 0)
|| (shifted_mant[6:4] == 3'b111 && shifted_mant[3]);
wire underflow = (exp1 + exp2 + overflow_mant) < 1 - roundup + EXP_BIAS;
wire is_zero = exp1 == 0 || exp2 == 0 || isnan || underflow;
// note: you can't use negative numbers reliably. just keep things positive during compares.
wire [4:0] exp_out_tmp = (exp1 + exp2 + overflow_mant + roundup) < EXP_BIAS ? 0 : (exp1 + exp2 + overflow_mant + roundup - EXP_BIAS);
assign exp_out = exp_out_tmp > 15 ? 4'b1111 : (is_zero) ? 0 : exp_out_tmp[3:0]; // Exponent bias is 7
assign mant_out = exp_out_tmp > 15 ? 3'b111 : (is_zero || roundup) ? 0 : (shifted_mant[6:4] + (shifted_mant[3:0] > 8 || (shifted_mant[3:0] == 8 && shifted_mant[4])));
assign sign_out = ((sign1 ^ sign2) && !(is_zero)) || isnan;
endmodule |
module krasin_tt02_verilog_spi_7_channel_pwm_driver (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire sclk = io_in[2];
wire cs = io_in[3];
wire mosi = io_in[4];
wire [6:0] pwm_out;
assign io_out[6:0] = pwm_out;
wire miso;
assign io_out[7] = miso;
// Previous value of sclk.
// This is to track SPI clock transitions within the main clock trigger.
reg prev_sclk;
// SPI counter that tracks 8 bit.
reg [2:0] spi_counter;
// is_writing is set if we received a write command.
reg is_writing;
reg is_reading;
reg [2:0] cur_addr;
// Buffer from mosi.
reg [7:0] in_buf;
// Buffer for miso.
reg [7:0] out_buf;
// out_buf is advanced on each falling sclk.
assign miso = out_buf[7];
// 8-bit PWM counter that goes from 0 to 254.
reg [7:0] counter;
// PWM levels for each channel.
// 0 means always off.
// 1 means that PWM will be on for just 1 clock cycle and then off for the other 254, giving 1/255 on average.
// 254 means 254/255 on.
// 255 means always on.
reg [7:0] pwm_level[6:0];
function is_on(input [7:0] level, input[7:0] counter);
begin
is_on = (counter < level);
end
endfunction // is_on
assign pwm_out[0] = is_on(pwm_level[0], counter);
assign pwm_out[1] = is_on(pwm_level[1], counter);
assign pwm_out[2] = is_on(pwm_level[2], counter);
assign pwm_out[3] = is_on(pwm_level[3], counter);
assign pwm_out[4] = is_on(pwm_level[4], counter);
assign pwm_out[5] = is_on(pwm_level[5], counter);
assign pwm_out[6] = is_on(pwm_level[6], counter);
// external clock is 1000Hz.
// PWM logic.
always @(posedge clk) begin
// if reset, set counter and pwm levels to 0
if (reset) begin
counter <= 0;
pwm_level[0] <= 0;
pwm_level[1] <= 0;
pwm_level[2] <= 0;
pwm_level[3] <= 0;
pwm_level[4] <= 0;
pwm_level[5] <= 0;
pwm_level[6] <= 0;
end else begin // if (reset)
if (counter == 254) begin
// Roll over.
counter <= 0;
end else begin
// increment counter
counter <= counter + 1'b1;
end
end // if (reset)
// SPI reset logic.
if (reset || cs) begin
// The chip is not selected or we are being reset. Reset all SPI registers.
in_buf <= 0;
out_buf <= 0;
prev_sclk <= 0;
spi_counter <= 0;
is_writing <= 0;
is_reading <= 0;
cur_addr <= 0;
end // if (reset || cs)
// regular SPI logic.
if (~reset && ~cs && (prev_sclk != sclk)) begin
// The chip is selected and the SPI clock changed.
// On rising edge we read from mosi, on falling edge, we write to miso.
if (sclk) begin
// Rising SCLK edge: reading from mosi.
in_buf <= (in_buf << 1) | mosi;
spi_counter <= spi_counter + 1'b1;
end else begin // if (sclk)
// Falling SCLK edge
if ((spi_counter == 0) && is_writing) begin
// Writing. We saved the cur_addr after reading the first byte.
if (cur_addr <= 6) begin
pwm_level[cur_addr] <= in_buf;
end
is_writing <= 0;
is_reading <= 1;
end // if ((spi_counter == 0) && is_writing
if ((spi_counter == 0) && ~is_writing) begin
if (in_buf[7]) begin
// We're writing, but the value will come as the next byte.
is_writing <= 1;
end else begin
is_reading <= 1;
end
cur_addr <= in_buf[2:0];
end // ((spi_counter == 0) && ~is_writing)
if ((spi_counter == 1) && is_reading) begin
if (cur_addr <= 6) begin
out_buf <= pwm_level[cur_addr];
end else begin
out_buf <= 0;
end
is_reading <= 0;
cur_addr <= 0;
end else begin // if ((spi_counter == 1) && is_reading)
// Advancing out_buf, so that miso sees a new value.
out_buf <= out_buf << 1;
end
end
prev_sclk <= sclk;
end // if (~reset && ~cs && (prev_sclk != sclk))
end // always @ (posedge clk)
endmodule |
module luthor2k_top_tto
#(parameter CLOCK_RATE=9600)
(
input [7:0] io_in,
output [7:0] io_out
);
// INPUTS
wire clk_ascii = io_in[0];
wire clk_baudot = io_in[1];
wire baudot_input = io_in[2];
// OUTPUTS
wire ascii_serial_output;
wire baudot_ready_out;
wire [4:0] baudot_byte_out;
assign io_out[0] = ascii_serial_output;
assign io_out[1] = baudot_ready_out;
//assign io_out[2] =
assign io_out[3] = baudot_byte_out[0];
assign io_out[4] = baudot_byte_out[1];
assign io_out[5] = baudot_byte_out[2];
assign io_out[6] = baudot_byte_out[3];
assign io_out[7] = baudot_byte_out[4];
// instatiate converter .function_pin(top_pin)
main main(.v65b531(clk_ascii), .v3c4a34(clk_baudot), .vcb44a7(baudot_input), .v7c2fea(ascii_serial_output), .v40cda4(baudot_ready_out), .v4d3fdd(baudot_byte_out));
endmodule |
module fraserbc_simon (
io_in,
io_out
);
input wire [7:0] io_in;
output wire [7:0] io_out;
assign io_out[7:4] = 4'b0;
/* Instantiate main module */
simon simon0 (
.i_clk(io_in[0]),
.i_shift(io_in[1]),
.i_data(io_in[5:2]),
.o_data(io_out[3:0])
);
endmodule |
module lfsr_z0(
i_clk,
i_rst,
o_data
);
input wire i_clk;
input wire i_rst;
output wire o_data;
reg [4:0] r_lfsr;
assign o_data = r_lfsr[0];
always @(posedge i_clk)
if(i_rst)
r_lfsr <= 5'b00001;
else begin
r_lfsr[4] <= r_lfsr[3];
r_lfsr[3] <= r_lfsr[2];
r_lfsr[2] <= r_lfsr[4] ^ r_lfsr[1];
r_lfsr[1] <= r_lfsr[0];
r_lfsr[0] <= r_lfsr[4] ^ r_lfsr[0];
end
endmodule |
module simon (
i_clk,
i_shift,
i_data,
o_data
);
input wire i_clk;
input wire i_shift;
input wire [3:0] i_data;
output wire [3:0] o_data;
assign o_data = r_round[3:0];
/* z0 Sequence */
wire w_z0;
lfsr_z0 lfsr0 (
.i_clk(i_clk),
.i_rst(i_shift),
.o_data(w_z0)
);
/* Key Schedule */
reg [63:0] r_key;
wire [15:0] w_temp = r_key[31:16] ^ {r_key[50:48],r_key[63:51]}; // Right circular shift
always @(posedge i_clk) begin
if (i_shift)
r_key <= {i_data, r_key[63:4]};
else begin
r_key[15:0] <= r_key[31:16];
r_key[31:16] <= r_key[47:32];
r_key[47:32] <= r_key[63:48];
r_key[63:48] <= (2**16 - 4) ^ {{15{1'b0}}, w_z0} ^ w_temp ^ r_key[15:0] ^ {w_temp[0],w_temp[15:1]};
end
end
/* Encrypt */
reg [31:0] r_round;
always @(posedge i_clk) begin
if (i_shift)
r_round <= {r_key[3:0], r_round[31:4]};
else begin
r_round[15:0] <= r_round[31:16];
r_round[31:16] <= (({r_round[30:16],r_round[31]} & {r_round[23:16],r_round[31:24]})) ^ {r_round[29:16],r_round[31:30]} ^ r_key[15:0] ^ r_round[15:0];
end
end
endmodule |
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