module
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module verified_multi_booth_8bit (p, rdy, clk, reset, a, b);
input clk, reset;
input [7:0] a, b;
output [15:0] p;
output rdy;
reg [15:0] p;
reg [15:0] multiplier;
reg [15:0] multiplicand;
reg rdy;
reg [4:0] ctr;
always @(posedge clk or posedge reset) begin
if (reset)
begin
rdy <= 0;
p <= 0;
ctr <= 0;
multiplier <= {{8{a[7]}}, a};
multiplicand <= {{8{b[7]}}, b};
end
else
begin
if(ctr < 16)
begin
multiplicand <= multiplicand << 1;
if (multiplier[ctr] == 1)
begin
p <= p + multiplicand;
end
ctr <= ctr + 1;
end
else
begin
rdy <= 1;
end
end
end //End of always block
endmodule
|
module booth4_mul_tb () ;
reg signed [`width-1:0] a, b;
reg clk, reset;
wire signed [2*`width-1:0] p;
wire rdy;
integer total, err;
integer i, s, fp, numtests;
wire signed [2*`width-1:0] ans = a*b;
multi_booth_8bit dut( .clk(clk),
.reset(reset),
.a(a),
.b(b),
.p(p),
.rdy(rdy));
// Set up 10ns clock
always #5 clk = ~clk;
task apply_and_check;
input [`width-1:0] ain;
input [`width-1:0] bin;
begin
// Set the inputs
a = ain;
b = bin;
// Reset the DUT for one clock cycle
reset = 1;
@(posedge clk);
// Remove reset
#1 reset = 0;
while (rdy == 0) begin
@(posedge clk); // Wait for one clock cycle
end
if (p == ans) begin
// $display($time, " Passed %d * %d = %d", a, b, p);
end else begin
// $display($time, " Fail %d * %d: %d instead of %d", a, b, p, ans);
err = err + 1;
end
total = total + 1;
end
endtask // apply_and_check
initial begin
clk = 1;
total = 0;
err = 0;
// Get all inputs from file: 1st line has number of inputs
fp = $fopen(`TESTFILE, "r");
s = $fscanf(fp, "%d\n", numtests);
// Sequences of values pumped through DUT
for (i=0; i<numtests; i=i+1) begin
s = $fscanf(fp, "%d %d\n", a, b);
apply_and_check(a, b);
end
if (err > 0) begin
$display("=========== Failed ===========");
end else begin
$display("===========Your Design Passed===========");
end
$finish;
end
endmodule
|
module right_shifter_tb;
reg clk;
reg d;
wire [7:0] q;
// Instantiate the DUT (Design Under Test)
right_shifter dut (
.clk(clk),
.d(d),
.q(q)
);
// Generate clock
always #5 clk = ~clk;
initial begin
// Initialize inputs
clk = 0;
d = 0;
#20;
d = 1;
#10;
d = 0;
#10;
d = 1;
#10;
d = 0;
#10;
d = 1;
#10;
d = 1;
#10;
d = 1;
#10;
// Check the output
if(q==8'b11101010) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Failed===========");
end
// Finish simulation
$finish;
end
endmodule
|
module verified_right_shifter(clk, q,d);
input clk;
input d;
output [7:0] q;
reg [7:0] q;
initial q = 0;
always @(posedge clk)
begin
q <= (q >> 1);
q[7] <= d;
end
endmodule
|
module calendar(
input wire CLK, // Clock input
input wire RST, // Active high reset signal
output reg [5:0] Hours, // 6-bit output for hours (0-23)
output reg [5:0] Mins, // 6-bit output for minutes (0-59)
output reg [5:0] Secs // 6-bit output for seconds (0-59)
);
// Always block for seconds
always @(posedge CLK or posedge RST) begin
if (RST) begin
// Reset seconds to 0
Secs <= 0;
end else if (Secs == 59) begin
// Wrap around and increment minutes
Secs <= 0;
end else begin
// Increment seconds
Secs <= Secs + 1;
end
end
// Always block for minutes
always @(posedge CLK or posedge RST) begin
if (RST) begin
// Reset minutes to 0
Mins <= 0;
end else if (Secs == 59 && Mins == 59) begin
// Wrap around and increment hours
Mins <= 0;
end else if (Secs == 59) begin
// Increment minutes
Mins <= Mins + 1;
end
// No else part needed, minutes stay the same if Secs is not 59
end
// Always block for hours
always @(posedge CLK or posedge RST) begin
if (RST) begin
// Reset hours to 0
Hours <= 0;
end else if (Secs == 59 && Mins == 59 && Hours == 23) begin
// Wrap around to 0 after 23:59:59
Hours <= 0;
end else if (Secs == 59 && Mins == 59) begin
// Increment hours
Hours <= Hours + 1;
end
// No else part needed, hours stay the same if Secs and Mins are not 59
end
endmodule
|
module traffic_light(
input wire rst_n,
input wire clk,
input wire pass_request,
output reg red,
output reg yellow,
output reg green,
output [7:0] clock
);
// State encoding
parameter s1_red = 2'b00,
s2_yellow = 2'b01,
s3_green = 2'b10;
// Internal variables
reg [7:0] cnt;
reg [1:0] state, next_state;
// Counter logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 8'd60; // Reset count to default green time
end else if (state == s3_green && pass_request && cnt > 10) begin
cnt <= 8'd10; // Pedestrian request, shorten green if > 10
end else if (cnt == 0) begin
case (state)
s1_red: cnt <= 8'd60; // Red to green
s2_yellow: cnt <= 8'd10; // Yellow to red
s3_green: cnt <= 8'd5; // Green to yellow
default: cnt <= 8'd60;
endcase
end else begin
cnt <= cnt - 1; // Decrement counter
end
end
// FSM logic for state transitions
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= s1_red; // Reset to red state
end else begin
state <= next_state;
end
end
// FSM next state logic
always @(*) begin
case (state)
s1_red: next_state = (cnt == 0) ? s3_green : s1_red;
s2_yellow: next_state = (cnt == 0) ? s1_red : s2_yellow;
s3_green: next_state = (cnt == 0 || (pass_request && cnt <= 10)) ? s2_yellow : s3_green;
default: next_state = s1_red;
endcase
end
// Output logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
red <= 1;
yellow <= 0;
green <= 0;
end else begin
case (state)
s1_red: begin
red <= 1;
yellow <= 0;
green <= 0;
end
s2_yellow: begin
red <= 0;
yellow <= 1;
green <= 0;
end
s3_green: begin
red <= 0;
yellow <= 0;
green <= 1;
end
endcase
end
end
// Assign the internal counter to an output port for monitoring
assign clock = cnt;
endmodule
|
module width_8to16 (
input wire clk,
input wire rst_n,
input wire valid_in,
input wire [7:0] data_in,
output reg valid_out,
output reg [15:0] data_out
);
// Internal register to store the first half of the data
reg [7:0] data_lock;
reg data_lock_valid;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset the output and internal registers
data_out <= 16'd0;
valid_out <= 1'b0;
data_lock <= 8'd0;
data_lock_valid <= 1'b0;
end else begin
if (valid_in) begin
if (data_lock_valid) begin
// If we have valid data locked, concatenate with new data
data_out <= {data_lock, data_in};
data_lock <= 8'd0; // Clear the lock register
valid_out <= 1'b1; // Set output valid
data_lock_valid <= 1'b0; // Clear the lock valid flag
end else begin
// Store the first half of the data
data_lock <= data_in;
data_lock_valid <= 1'b1; // Set the lock valid flag
valid_out <= 1'b0; // Clear the output valid as we wait for next data
end
end else if (data_lock_valid) begin
// If no new valid data, but we have data locked
// we don't update the output
valid_out <= 1'b0;
end
// If no valid input and no data locked, maintain the current state
end
end
endmodule
|
module JC_counter(
input clk, // Clock signal
input rst_n, // Active-low reset
output reg [63:0] Q // 64-bit counter value
);
// Counter update logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Reset condition
Q <= 64'b0;
end else begin
if (Q[0] == 1'b0) begin
// Increment (shift left and append '1' at LSB)
Q <= {Q[62:0], 1'b1};
end else begin
// Decrement (shift left and append '0' at LSB)
Q <= {Q[62:0], 1'b0};
end
end
end
endmodule
|
module adder_pipe_64bit(
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
// Pipeline stage registers
reg [63:0] stage_adda;
reg [63:0] stage_addb;
reg stage_i_en;
// Temp register for the sum of A and B
reg [64:0] sum;
// Pipeline registers for the sum
reg [64:0] stage_sum;
reg stage_sum_valid;
// Synchronous reset and pipeline register control
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset all pipeline registers
stage_adda <= 64'd0;
stage_addb <= 64'd0;
stage_i_en <= 1'b0;
stage_sum <= 65'd0;
stage_sum_valid <= 1'b0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
// Move data through the pipeline on each clock edge
if (i_en) begin
// Latch inputs into the pipeline
stage_adda <= adda;
stage_addb <= addb;
stage_i_en <= i_en;
end
// Perform addition in the first pipeline stage
sum <= stage_adda + stage_addb;
// Move result to the next pipeline stage
stage_sum <= sum;
stage_sum_valid <= stage_i_en;
// The final result and output enable are updated in the last pipeline stage
result <= stage_sum;
o_en <= stage_sum_valid;
end
end
endmodule
|
module right_shifter (
input clk,
input d,
output reg [7:0] q
);
// Initialize the register 'q' to 0
initial q = 8'b00000000;
// On each rising edge of the clock, perform the right shift operation
always @(posedge clk) begin
q <= {d, q[7:1]}; // Insert input 'd' into the MSB position after the shift
end
endmodule
|
module serial2parallel (
input clk,
input rst_n,
input din_serial,
input din_valid,
output reg [7:0] dout_parallel,
output reg dout_valid
);
// 3-bit counter to count up to 8 bits
reg [2:0] cnt;
// Reset and count logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Asynchronous reset
cnt <= 3'd0;
dout_parallel <= 8'd0;
dout_valid <= 1'b0;
end
else if (din_valid) begin
if (cnt < 3'd7) begin
// Shift in the serial data starting from the MSB
dout_parallel <= {din_serial, dout_parallel[7:1]};
cnt <= cnt + 3'd1;
dout_valid <= 1'b0; // Not valid until 8 bits are received
end
else begin
// Shift in the last bit and assert the valid signal
dout_parallel <= {din_serial, dout_parallel[7:1]};
dout_valid <= 1'b1;
cnt <= 3'd0; // Reset the counter
end
end
end
endmodule
|
module multi_16bit (
input clk,
input rst_n,
input start,
input [15:0] ain,
input [15:0] bin,
output reg [31:0] yout,
output done
);
reg [3:0] i; // Shift count register
reg [15:0] areg, breg; // Registers for multiplicand and multiplier
reg [31:0] yout_r; // Register for the product
reg done_r; // Register for the done signal
// Initialize the output and internal registers
initial begin
i = 0;
areg = 0;
breg = 0;
yout_r = 0;
done_r = 0;
yout = 0;
end
// Assign the done signal to the done_r register
assign done = done_r;
// Control logic for multiplication
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset condition
i <= 0;
areg <= 0;
breg <= 0;
yout_r <= 0;
done_r <= 0;
end else if (start) begin
if (i == 0) begin
// Load the input values into registers
areg <= ain;
breg <= bin;
yout_r <= 0; // Clear the accumulator
end else if (i < 17) begin
// Perform shift and accumulate if the corresponding bit in areg is set
if (areg[i-1])
yout_r <= yout_r + (breg << (i - 1));
end
// Increment the shift count register
if (i < 17) begin
i <= i + 1;
end
// Update the done flag
done_r <= (i == 16);
end else begin
// If start is not active, reset the shift count and done flag
i <= 0;
done_r <= 0;
end
end
// Update the output register at the end of multiplication
always @(posedge clk) begin
if (done_r) begin
yout <= yout_r; // Assign the accumulated product to the output
end
end
endmodule
|
module multi_pipe_4bit #(
parameter size = 4
) (
input wire clk,
input wire rst_n,
input wire [size-1:0] mul_a,
input wire [size-1:0] mul_b,
output wire [2*size-1:0] mul_out
);
// Intermediate registers for pipeline stages
reg [2*size-1:0] partial_products[size-1:0];
reg [2*size-1:0] sum_stage1;
reg [2*size-1:0] sum_stage2;
reg [2*size-1:0] final_product;
// Output assignment
assign mul_out = final_product;
// Generate block to create partial products
genvar i;
generate
for (i = 0; i < size; i = i + 1) begin : gen_partial_products
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
partial_products[i] <= 0;
end else begin
// If the corresponding bit in the multiplier is 1,
// left-shift the multiplicand by i positions.
// Otherwise, the partial product is 0.
partial_products[i] <= mul_b[i] ? (mul_a << i) : 0;
end
end
end
endgenerate
// Pipeline stage 1: Add partial products
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum_stage1 <= 0;
end else begin
sum_stage1 <= partial_products[0] + partial_products[1] +
partial_products[2] + partial_products[3];
end
end
// Pipeline stage 2: Store the result of addition
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum_stage2 <= 0;
end else begin
sum_stage2 <= sum_stage1;
end
end
// Final product calculation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
final_product <= 0;
end else begin
final_product <= sum_stage2;
end
end
endmodule
|
module freq_div (
input CLK_in,
input RST,
output reg CLK_50,
output reg CLK_10,
output reg CLK_1
);
// Internal counters for CLK_10 and CLK_1 generation
reg [3:0] cnt_10 = 0;
reg [6:0] cnt_100 = 0;
// CLK_50 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_50 <= 0;
end else begin
CLK_50 <= ~CLK_50; // Toggle the CLK_50 output
end
end
// CLK_10 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
cnt_10 <= 0;
CLK_10 <= 0;
end else begin
if (cnt_10 == 4) begin
CLK_10 <= ~CLK_10; // Toggle the CLK_10 output
cnt_10 <= 0;
end else begin
cnt_10 <= cnt_10 + 1;
end
end
end
// CLK_1 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
cnt_100 <= 0;
CLK_1 <= 0;
end else begin
if (cnt_100 == 49) begin
CLK_1 <= ~CLK_1; // Toggle the CLK_1 output
cnt_100 <= 0;
end else begin
cnt_100 <= cnt_100 + 1;
end
end
end
endmodule
|
module counter_12 (
input rst_n,
input clk,
input valid_count,
output reg [3:0] out
);
// Define the maximum count value as a parameter for easy changes
parameter MAX_COUNT = 4'd11;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Active low reset signal
out <= 4'b0000;
end else if (valid_count) begin
// Only increment the counter if valid_count is high
if (out == MAX_COUNT) begin
// Reset to 0 if the counter reaches the maximum count value
out <= 4'b0000;
end else begin
// Increment the counter
out <= out + 1;
end
end
// If valid_count is 0, do nothing (counter is paused)
end
endmodule
|
module edge_detect(
input wire clk, // Clock signal
input wire rst_n, // Active low reset
input wire a, // Input signal
output reg rise, // Output signal for rising edge
output reg down // Output signal for falling edge
);
// Register to hold the previous state of `a`
reg a_prev;
// On every positive edge of the clock, check for edges
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Active low reset: reset all the outputs and previous state
rise <= 0;
down <= 0;
a_prev <= 0;
end else begin
// Reset the rise and down signals on every clock cycle
rise <= 0;
down <= 0;
// Check for a rising edge
if (a == 1 && a_prev == 0) begin
rise <= 1;
end
// Check for a falling edge
if (a == 0 && a_prev == 1) begin
down <= 1;
end
// Update previous state of `a`
a_prev <= a;
end
end
endmodule
|
module adder_8bit (
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
// Internal wires for the carry bits between full adders
wire [6:0] carry;
// Instantiate the full adders
full_adder fa0 (.a(a[0]), .b(b[0]), .cin(cin), .sum(sum[0]), .cout(carry[0]));
full_adder fa1 (.a(a[1]), .b(b[1]), .cin(carry[0]), .sum(sum[1]), .cout(carry[1]));
full_adder fa2 (.a(a[2]), .b(b[2]), .cin(carry[1]), .sum(sum[2]), .cout(carry[2]));
full_adder fa3 (.a(a[3]), .b(b[3]), .cin(carry[2]), .sum(sum[3]), .cout(carry[3]));
full_adder fa4 (.a(a[4]), .b(b[4]), .cin(carry[3]), .sum(sum[4]), .cout(carry[4]));
full_adder fa5 (.a(a[5]), .b(b[5]), .cin(carry[4]), .sum(sum[5]), .cout(carry[5]));
full_adder fa6 (.a(a[6]), .b(b[6]), .cin(carry[5]), .sum(sum[6]), .cout(carry[6]));
full_adder fa7 (.a(a[7]), .b(b[7]), .cin(carry[6]), .sum(sum[7]), .cout(cout));
endmodule
|
module multi_pipe_8bit(
input wire clk,
input wire rst_n,
input wire mul_en_in,
input wire [7:0] mul_a,
input wire [7:0] mul_b,
output reg mul_en_out,
output reg [15:0] mul_out
);
reg [7:0] mul_a_reg, mul_b_reg;
reg mul_en_in_reg;
reg [15:0] partials[7:0]; // Array to store partial products
reg [15:0] partial_sum; // Register to store partial sum
// Pipeline stage registers
reg [15:0] stage1, stage2, stage3, stage4, stage5, stage6, stage7;
// Input control logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
mul_a_reg <= 0;
mul_b_reg <= 0;
mul_en_in_reg <= 0;
end else if (mul_en_in) begin
mul_a_reg <= mul_a;
mul_b_reg <= mul_b;
mul_en_in_reg <= mul_en_in;
end
end
// Generate partial products
integer i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < 8; i = i + 1)
partials[i] <= 0;
end else if (mul_en_in_reg) begin
for (i = 0; i < 8; i = i + 1)
partials[i] <= mul_b_reg[i] ? (mul_a_reg << i) : 0;
end
end
// Calculate partial sums and pipeline them through the stages
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
partial_sum <= 0;
stage1 <= 0;
stage2 <= 0;
stage3 <= 0;
stage4 <= 0;
stage5 <= 0;
stage6 <= 0;
stage7 <= 0;
end else begin
partial_sum <= partials[0] + partials[1];
stage1 <= partial_sum + partials[2];
stage2 <= stage1 + partials[3];
stage3 <= stage2 + partials[4];
stage4 <= stage3 + partials[5];
stage5 <= stage4 + partials[6];
stage6 <= stage5 + partials[7];
stage7 <= stage6;
end
end
// Output logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
mul_out <= 0;
mul_en_out <= 0;
end else begin
mul_out <= stage7;
mul_en_out <= mul_en_in_reg;
end
end
endmodule
|
module parallel2serial(
input wire clk,
input wire rst_n,
input wire [3:0] d,
output reg valid_out,
output reg dout
);
// State representation
reg [1:0] cnt; // 2-bit counter to keep track of the shifting
reg [3:0] data; // Register to hold the current data
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Synchronous reset: reset counter and output
cnt <= 2'b00;
valid_out <= 1'b0;
dout <= 1'b0;
data <= 4'd0;
end else begin
if (cnt == 3) begin
// Last bit was shifted out, load new data and reset counter
data <= d;
cnt <= 2'b00;
valid_out <= 1'b1; // Indicate that valid data is available
dout <= d[3]; // Output MSB
end else begin
// Shift data and increment counter
data <= data << 1; // Shift left by 1 bit
dout <= data[3]; // Output next bit
cnt <= cnt + 1'b1;
valid_out <= (cnt == 2'b00)? 1'b1 : 1'b0; // Set valid_out only when new data is loaded
end
end
end
endmodule
|
module radix2_div #(
parameter DATAWIDTH = 8
)(
input clk,
input rstn,
input en,
input [DATAWIDTH-1:0] dividend,
input [DATAWIDTH-1:0] divisor,
output reg ready,
output reg [DATAWIDTH-1:0] quotient,
output reg [DATAWIDTH-1:0] remainder,
output reg vld_out
);
// FSM states
localparam IDLE = 2'b00,
SUB = 2'b01,
SHIFT = 2'b10,
DONE = 2'b11;
// Registers for FSM, counters and extended operands
reg [1:0] current_state, next_state;
reg [DATAWIDTH:0] dividend_e, divisor_e, remainder_e;
reg [DATAWIDTH-1:0] quotient_e;
reg [DATAWIDTH-1:0] count;
// FSM state transition and data computation
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
current_state <= IDLE;
quotient_e <= 0;
remainder_e <= 0;
dividend_e <= 0;
divisor_e <= 0;
count <= 0;
ready <= 1;
vld_out <= 0;
end else begin
case (current_state)
IDLE: begin
if (en) begin
current_state <= SUB;
dividend_e <= {1'b0, dividend};
divisor_e <= {1'b0, divisor};
quotient_e <= 0;
remainder_e <= 0;
count <= DATAWIDTH;
ready <= 0;
vld_out <= 0;
end
end
SUB: begin
if (dividend_e >= divisor_e) begin
remainder_e <= dividend_e - divisor_e;
quotient_e[0] <= 1;
end else begin
remainder_e <= dividend_e;
quotient_e[0] <= 0;
end
current_state <= SHIFT;
end
SHIFT: begin
if (count > 0) begin
count <= count - 1;
quotient_e <= {quotient_e[DATAWIDTH-2:0], 1'b0};
dividend_e <= {remainder_e[DATAWIDTH-2:0], dividend_e[0], 1'b0};
current_state <= SUB;
end else begin
current_state <= DONE;
end
end
DONE: begin
quotient <= quotient_e;
remainder <= remainder_e[DATAWIDTH-1:0];
ready <= 1;
vld_out <= 1;
if (!en) current_state <= IDLE;
end
endcase
end
end
// Output assignments
always @(*) begin
case (current_state)
IDLE: begin
ready = 1'b1;
end
DONE: begin
vld_out = 1'b1;
end
default: begin
ready = 1'b0;
vld_out = 1'b0;
end
endcase
end
endmodule
|
module accu (
input clk,
input rst_n,
input [7:0] data_in,
input valid_in,
output reg valid_out,
output reg [9:0] data_out
);
// Internal variables
reg [9:0] sum; // 10-bit sum to hold the accumulated value
reg [1:0] count; // Counter to count the number of valid inputs
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset all registers when reset is active
sum <= 10'd0;
count <= 2'd0;
data_out <= 10'd0;
valid_out <= 1'b0;
end else if (valid_in) begin
// If valid_in is high, accumulate the data_in
if (count == 3) begin
// If already received 3 inputs, then this is the 4th one
sum <= sum + data_in; // Add the current data to the sum
data_out <= sum + data_in; // Update the data_out with the full sum
valid_out <= 1'b1; // Set the valid_out high for one cycle
count <= 2'd0; // Reset the count for the next set of inputs
sum <= 10'd0; // Reset the sum for the next set of inputs
end else begin
// If count is less than 3, accumulate the sum
sum <= sum + data_in; // Add the current data to the sum
count <= count + 1'b1; // Increment the count
valid_out <= 1'b0; // Make sure valid_out is low
end
end else begin
// If valid_in is not high, do not accumulate and keep valid_out low
valid_out <= 1'b0;
end
end
endmodule
|
module div_16bit (
input [15:0] A,
input [7:0] B,
output reg [15:0] result,
output reg [15:0] odd
);
// Temporary variables for intermediate values
reg [15:0] temp_dividend;
reg [7:0] temp_divisor;
reg [15:0] temp_result;
reg [15:0] temp_odd;
integer i;
always @* begin
// Initial assignments
temp_dividend = A;
temp_divisor = B;
temp_result = 0;
temp_odd = 0;
// Check for divide by zero case
if (temp_divisor != 0) begin
for (i = 15; i >= 0; i = i - 1) begin
// Shift left the odd to make room for the new bit
temp_odd = temp_odd << 1;
// Bring down the next bit from the dividend
temp_odd[0] = temp_dividend[i];
// Compare the higher bits of dividend with the divisor
if (temp_odd >= {8'b0, temp_divisor}) begin
// Subtract the divisor from the current portion of the dividend
temp_odd = temp_odd - {8'b0, temp_divisor};
// Set the current bit in the quotient
temp_result[i] = 1'b1;
end
end
end else begin
// If B is 0, it's an undefined operation, typically handled separately
// For this example, just set result and odd to all zeros
temp_result = 16'b0;
temp_odd = 16'b0;
end
// Assign the results to the outputs
result = temp_result;
odd = temp_odd;
end
endmodule
|
module signal_generator (
input clk,
input rst_n,
output reg [4:0] wave // 5-bit output for wave
);
// State register declaration
reg state;
// Define states for readability
localparam STATE_INCREASING = 1'b0;
localparam STATE_DECREASING = 1'b1;
// Waveform generation and state management
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset condition
wave <= 5'd0;
state <= STATE_INCREASING;
end else begin
case (state)
STATE_INCREASING: begin
if (wave == 5'd31) begin
// Transition to decreasing state
state <= STATE_DECREASING;
wave <= wave - 5'd1;
end else begin
// Increment wave
wave <= wave + 5'd1;
end
end
STATE_DECREASING: begin
if (wave == 5'd0) begin
// Transition to increasing state
state <= STATE_INCREASING;
wave <= wave + 5'd1;
end else begin
// Decrement wave
wave <= wave - 5'd1;
end
end
default: begin
// Just in case we get into an unknown state, reset to a known state
state <= STATE_INCREASING;
wave <= 5'd0;
end
endcase
end
end
endmodule
|
module multi_booth_8bit(
input clk,
input reset,
input [7:0] a,
input [7:0] b,
output reg [15:0] p,
output reg rdy
);
reg [7:0] multiplicand;
reg [8:0] multiplier; // Extra bit for the Booth algorithm
reg [3:0] ctr; // Counter for iterations
reg [1:0] booth_code;
always @(posedge clk or posedge reset) begin
if (reset) begin
// Initialize the multiplier module
multiplicand <= 0;
multiplier <= {1'b0, b};
p <= 0;
ctr <= 0;
rdy <= 0;
end else begin
// Check if the multiplication process is completed
if (ctr < 8) begin
booth_code <= {multiplier[1:0], 1'b0}; // Radix-4 Booth encoding
case (booth_code)
3'b001, 3'b010: p <= p + (multiplicand << (2 * ctr)); // +A operation
3'b101, 3'b110: p <= p - (multiplicand << (2 * ctr)); // -A operation
// For 3'b000, 3'b011, 3'b100, and 3'b111, no operation is performed on p
endcase
// Prepare for the next iteration
multiplier <= multiplier >> 2; // Radix-4 right shift
ctr <= ctr + 1;
end else if (ctr == 8) begin
// Indicate that the multiplication process is completed
rdy <= 1;
ctr <= ctr + 1; // Increment ctr to stop the operation
end
end
end
endmodule
|
module pe(
input wire clk,
input wire rst,
input wire [31:0] a,
input wire [31:0] b,
output reg [31:0] c
);
// Intermediate register to store the product of a and b
reg [63:0] product;
always @(posedge clk or posedge rst) begin
if (rst) begin
// Reset the accumulator to 0 when rst is high
c <= 32'd0;
end else begin
// Perform the multiply-accumulate operation
product <= a * b; // Multiply a by b
c <= c + product[31:0]; // Accumulate the lower 32 bits of the product
end
end
endmodule
|
module alu (
input [31:0] a,
input [31:0] b,
input [5:0] aluc,
output reg [31:0] r,
output zero,
output reg carry,
output reg negative,
output reg overflow,
output reg flag
);
// Define the operation parameters
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter LUI = 6'b001111;
// Set the zero flag
assign zero = (r == 32'b0);
always @(*) begin
// Initialize outputs
carry = 0;
overflow = 0;
negative = 0;
flag = 0;
case (aluc)
ADD: begin
// Signed addition
{carry, r} = a + b;
overflow = (a[31] & b[31] & ~r[31]) | (~a[31] & ~b[31] & r[31]);
negative = r[31];
end
ADDU: begin
// Unsigned addition
{carry, r} = a + b;
// No overflow for unsigned addition
end
SUB: begin
// Signed subtraction
{carry, r} = a - b;
overflow = (~a[31] & b[31] & r[31]) | (a[31] & ~b[31] & ~r[31]);
negative = r[31];
end
SUBU: begin
// Unsigned subtraction
{carry, r} = a - b;
// No overflow for unsigned subtraction
end
AND: r = a & b;
OR: r = a | b;
XOR: r = a ^ b;
NOR: r = ~(a | b);
SLT: begin
// Set flag if a < b (signed)
flag = $signed(a) < $signed(b);
r = flag;
negative = r[31];
end
SLTU: begin
// Set flag if a < b (unsigned)
flag = a < b;
r = flag;
end
SLL: r = b << a[4:0];
SRL: r = b >> a[4:0];
SRA: r = $signed(b) >>> a[4:0];
SLLV: r = b << a;
SRLV: r = b >> a;
SRAV: r = $signed(b) >>> a;
LUI: r = {b[15:0], 16'b0};
default: r = 32'bx; // Undefined operation
endcase
end
endmodule
|
module full_adder_1bit(
input a,
input b,
input cin,
output sum,
output cout
);
assign {cout, sum} = a + b + cin;
endmodule
|
module adder_8bit(
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
wire[6:0] carry;
genvar i;
generate
for(i = 0; i < 7; i = i + 1) begin : gen_full_adder
if (i == 0) begin
full_adder_1bit fa(a[i], b[i], cin, sum[i], carry[i]);
end else begin
full_adder_1bit fa(a[i], b[i], carry[i-1], sum[i], carry[i]);
end
end
endgenerate
full_adder_1bit fa_last(a[7], b[7], carry[6], sum[7], cout);
endmodule
|
module adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire cout_first; // Carry out from the first 8-bit adder
// First 8-bit adder
adder_8bit adder_lower(
.a(a[7:0]),
.b(b[7:0]),
.cin(Cin),
.sum(y[7:0]),
.cout(cout_first)
);
// Second 8-bit adder
adder_8bit adder_upper(
.a(a[15:8]),
.b(b[15:8]),
.cin(cout_first),
.sum(y[15:8]),
.cout(Co)
);
endmodule
|
module pulse_detect(
input clk,
input rst_n,
input data_in,
output reg data_out
);
// State definition
parameter IDLE = 2'b00;
parameter PULSE_START = 2'b01;
parameter PULSE_END = 2'b11;
// State register
reg [1:0] current_state, next_state;
// State transition logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Reset condition
current_state <= IDLE;
end else begin
// Update state
current_state <= next_state;
end
end
// Next state logic
always @(*) begin
// Default assignment
next_state = current_state;
case (current_state)
IDLE: begin
if (data_in == 1'b1) begin
next_state = PULSE_START;
end
end
PULSE_START: begin
if (data_in == 1'b0) begin
next_state = PULSE_END;
end
end
PULSE_END: begin
next_state = IDLE;
end
default: next_state = IDLE;
endcase
end
// Output logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Reset condition
data_out <= 1'b0;
end else begin
// Generate output based on current state
case (current_state)
PULSE_START: data_out <= 1'b0;
PULSE_END: data_out <= 1'b1;
default: data_out <= 1'b0;
endcase
end
end
endmodule
|
module synchronizer (
input clk_a,
input clk_b,
input arstn,
input brstn,
input [3:0] data_in,
input data_en,
output reg [3:0] dataout
);
// Data and enable registers for clk_a domain
reg [3:0] data_reg;
reg en_data_reg;
// Double-registering for en_data_reg in clk_b domain for synchronization
reg en_clap_one;
reg en_clap_two;
// Register data_in on clk_a domain
always @(posedge clk_a or negedge arstn) begin
if (!arstn) begin
data_reg <= 4'd0;
en_data_reg <= 1'b0;
end else begin
data_reg <= data_in;
en_data_reg <= data_en;
end
end
// Synchronize the enable signal to clk_b domain
always @(posedge clk_b or negedge brstn) begin
if (!brstn) begin
en_clap_one <= 1'b0;
en_clap_two <= 1'b0;
end else begin
en_clap_one <= en_data_reg; // First D flip-flop for en_data_reg
en_clap_two <= en_clap_one; // Second D flip-flop for en_data_reg
end
end
// Assign dataout based on synchronized enable signal (en_clap_two)
always @(posedge clk_b or negedge brstn) begin
if (!brstn) begin
dataout <= 4'd0;
end else if (en_clap_two) begin
// Only update dataout when the enable signal has been stable high for two clk_b cycles
dataout <= data_reg;
end
// If en_clap_two is low, retain the previous value (no need for an else statement)
end
endmodule
|
module calendar(
input CLK, // Clock input
input RST, // Active high reset signal
output reg [5:0] Hours, // 6-bit output for hours
output reg [5:0] Mins, // 6-bit output for minutes
output reg [5:0] Secs // 6-bit output for seconds
);
// Update seconds
always @(posedge CLK or posedge RST) begin
if (RST) begin
Secs <= 0;
end else if (Secs == 59) begin
Secs <= 0;
end else begin
Secs <= Secs + 1;
end
end
// Update minutes
always @(posedge CLK or posedge RST) begin
if (RST) begin
Mins <= 0;
end else if (Secs == 59 && Mins == 59) begin
Mins <= 0;
end else if (Secs == 59) begin
Mins <= Mins + 1;
end
end
// Update hours
always @(posedge CLK or posedge RST) begin
if (RST) begin
Hours <= 0;
end else if (Secs == 59 && Mins == 59 && Hours == 23) begin
Hours <= 0;
end else if (Secs == 59 && Mins == 59) begin
Hours <= Hours + 1;
end
end
endmodule
|
module width_8to16(
input wire clk,
input wire rst_n,
input wire valid_in,
input wire [7:0] data_in,
output reg valid_out,
output reg [15:0] data_out
);
// Internal signal to store the first half of the data
reg [7:0] data_lock;
// Flag to indicate that the first half is stored
reg flag;
// Data handling and output generation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset the output and internal registers
data_out <= 16'd0;
valid_out <= 1'b0;
data_lock <= 8'd0;
flag <= 1'b0;
end else if (valid_in) begin
if (flag) begin
// If we have a stored first half, concatenate with the new input
data_out <= {data_lock, data_in};
valid_out <= 1'b1; // Output is now valid
flag <= 1'b0; // Clear the flag as we've used the stored half
end else begin
// Store the first half of the data
data_lock <= data_in;
flag <= 1'b1;
valid_out <= 1'b0; // Output is not valid until we get the second half
end
end else if (!valid_in && flag) begin
// If no valid input and we have a stored first half, do not change the state
valid_out <= 1'b0;
end
end
endmodule
|
module JC_counter (
input wire clk,
input wire rst_n,
output reg [63:0] Q
);
// Johnson counter update logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Active-low reset is asserted, initialize the counter
Q <= 64'b0;
end else begin
// Shift the counter and append bits at the ends according to the pattern
Q <= {Q[62:0], ~Q[63]};
end
end
endmodule
|
module adder_pipe_64bit(
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
// Internal signals for pipeline stages
reg [63:0] adda_reg, addb_reg;
reg [64:0] sum_reg;
reg i_en_reg, i_en_reg2; // Registered versions of i_en to create pipeline stages
// Pipeline stage 1: Register inputs and i_en
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_reg <= 0;
addb_reg <= 0;
i_en_reg <= 0;
end else begin
if (i_en) begin
adda_reg <= adda;
addb_reg <= addb;
end
i_en_reg <= i_en; // Capture the enable signal
end
end
// Pipeline stage 2: Perform addition
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum_reg <= 0;
i_en_reg2 <= 0;
end else begin
if (i_en_reg) begin
sum_reg <= adda_reg + addb_reg; // Perform the addition
end
i_en_reg2 <= i_en_reg; // Move enable signal down the pipeline
end
end
// Pipeline stage 3: Output result and o_en
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
result <= 0;
o_en <= 0;
end else begin
result <= sum_reg; // Pass the sum to the output
o_en <= i_en_reg2; // Output enable signal goes high when the result is valid
end
end
endmodule
|
module right_shifter(
input wire clk,
input wire d,
output reg [7:0] q
);
// Initialize the q register to 0
initial begin
q = 8'b00000000;
end
// Perform the shift operation on the rising edge of the clock
always @(posedge clk) begin
q <= {d, q[7:1]}; // Shift right q and insert d at the MSB
end
endmodule
|
module serial2parallel (
input wire clk,
input wire rst_n,
input wire din_serial,
input wire din_valid,
output reg [7:0] dout_parallel,
output reg dout_valid
);
// Internal counter to track the number of received bits
reg [2:0] cnt; // 3 bits to count up to 8
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Asynchronous reset: clear the counter and output registers
cnt <= 3'b000;
dout_parallel <= 8'b00000000;
dout_valid <= 1'b0;
end else if (din_valid) begin
// If input is valid, shift in the new bit and increment the counter
dout_parallel <= {din_serial, dout_parallel[7:1]};
cnt <= cnt + 1'b1;
// Check if 8 bits have been shifted in
if (cnt == 3'b111) begin
// Indicate that the output is valid on the 8th bit
dout_valid <= 1'b1;
cnt <= 3'b000; // Reset the counter for the next cycle
end else begin
// Output is not yet valid
dout_valid <= 1'b0;
end
end else begin
// If input is not valid, just clear the valid output signal
dout_valid <= 1'b0;
end
end
endmodule
|
module multi_16bit (
input wire clk,
input wire rst_n,
input wire start,
input wire [15:0] ain,
input wire [15:0] bin,
output reg [31:0] yout,
output reg done
);
reg [31:0] product;
reg [4:0] count;
reg [15:0] multiplicand, multiplier;
reg multiply_started;
// Control logic for starting the multiplication
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
multiply_started <= 1'b0;
count <= 5'b0;
done <= 1'b0;
end else if (start && !multiply_started) begin
multiply_started <= 1'b1;
multiplicand <= ain;
multiplier <= bin;
product <= 32'b0;
count <= 5'b0;
done <= 1'b0;
end else if (multiply_started) begin
if (count < 16) begin
// Shift and accumulate
if (multiplier[0]) begin
product <= product + (multiplicand << count);
end
multiplier <= multiplier >> 1;
count <= count + 1;
end else begin
// Finish the multiplication
multiply_started <= 1'b0;
done <= 1'b1;
end
end else if (done) begin
done <= 1'b0; // Clear the done flag once multiplication is complete
end
end
// Assign the product to the output
always @(posedge clk) begin
if (done) begin
yout <= product; // Output the final product
end
end
endmodule
|
module freq_div(
input CLK_in, // Input clock signal
input RST, // Reset signal
output reg CLK_50, // Output clock signal with a frequency of CLK_in divided by 2
output reg CLK_10, // Output clock signal with a frequency of CLK_in divided by 10
output reg CLK_1 // Output clock signal with a frequency of CLK_in divided by 100
);
// Counter for the CLK_10 generation
reg [3:0] cnt_10 = 4'd0; // 4 bits counter to count up to 9 (10 states)
// Counter for the CLK_1 generation
reg [6:0] cnt_100 = 7'd0; // 7 bits counter to count up to 99 (100 states)
// CLK_50 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_50 <= 1'b0;
end else begin
CLK_50 <= ~CLK_50;
end
end
// CLK_10 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
cnt_10 <= 4'd0;
CLK_10 <= 1'b0;
end else begin
if (cnt_10 == 4'd4) begin
CLK_10 <= ~CLK_10;
cnt_10 <= 4'd0;
end else begin
cnt_10 <= cnt_10 + 1'b1;
end
end
end
// CLK_1 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
cnt_100 <= 7'd0;
CLK_1 <= 1'b0;
end else begin
if (cnt_100 == 7'd49) begin
CLK_1 <= ~CLK_1;
cnt_100 <= 7'd0;
end else begin
cnt_100 <= cnt_100 + 1'b1;
end
end
end
endmodule
|
module counter_12(
input rst_n, // Active low reset
input clk, // Clock signal
input valid_count, // Enable counting
output reg [3:0] out // 4-bit counter output
);
// Counter operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset condition
out <= 4'b0000;
end else if (valid_count) begin
// Counting enabled
if (out == 4'd11) begin
// Wrap the counter after reaching 11
out <= 4'b0000;
end else begin
// Increment the counter
out <= out + 1;
end
end
// When valid_count is not active, counter holds the value (no 'else' needed)
end
endmodule
|
module edge_detect(
input wire clk,
input wire rst_n,
input wire a,
output reg rise,
output reg down
);
// Register to hold the previous value of 'a'
reg a_prev;
// Always block for edge detection and output signal generation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Asynchronous reset: active low
rise <= 0;
down <= 0;
a_prev <= 0;
end else begin
// Check for rising edge
if (a == 1 && a_prev == 0) begin
rise <= 1;
end else begin
rise <= 0;
end
// Check for falling edge
if (a == 0 && a_prev == 1) begin
down <= 1;
end else begin
down <= 0;
end
// Update the previous value of 'a'
a_prev <= a;
end
end
endmodule
|
module adder_32bit(
input [32:1] A, // 32-bit input operand A
input [32:1] B, // 32-bit input operand B
output [32:1] S, // 32-bit output sum
output C32 // Carry-out output
);
wire C16; // Intermediate carry between lower and upper CLA blocks
// Instantiate the lower 16-bit CLA block
cla_16bit cla_lower(
.A(A[16:1]),
.B(B[16:1]),
.Cin(1'b0), // Assuming there is no initial carry-in
.S(S[16:1]),
.Cout(C16)
);
// Instantiate the upper 16-bit CLA block
cla_16bit cla_upper(
.A(A[32:17]),
.B(B[32:17]),
.Cin(C16),
.S(S[32:17]),
.Cout(C32)
);
endmodule
|
module cla_16bit(
input [16:1] A,
input [16:1] B,
input Cin,
output [16:1] S,
output Cout
);
wire [16:0] C; // Internal carry bits, C[0] is Cin
wire [16:1] G; // Generate terms
wire [16:1] P; // Propagate terms
assign C[0] = Cin;
// Generate and propagate terms
genvar i;
generate
for (i = 1; i <= 16; i = i + 1) begin : gen_prop
assign G[i] = A[i] & B[i]; // Generate
assign P[i] = A[i] | B[i]; // Propagate
assign C[i] = G[i] | (P[i] & C[i-1]); // Carry
end
endgenerate
// Calculate sum and carry out
for (i = 1; i <= 16; i = i + 1) begin : sum_loop
assign S[i] = A[i] ^ B[i] ^ C[i-1]; // Sum bit
end
assign Cout = C[16]; // Final carry-out
endmodule
|
module RAM #(
parameter WIDTH = 6,
parameter DEPTH = 8
)(
input wire clk,
input wire rst_n,
input wire write_en,
input wire [DEPTH-1:0] write_addr,
input wire [WIDTH-1:0] write_data,
input wire read_en,
input wire [DEPTH-1:0] read_addr,
output reg [WIDTH-1:0] read_data
);
// Memory array
reg [WIDTH-1:0] RAM [(1<<DEPTH)-1:0];
integer i;
// Write operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset RAM contents to 0 on reset
for (i = 0; i < (1<<DEPTH); i = i + 1) begin
RAM[i] <= 0;
end
end else if (write_en) begin
// Write data to RAM
RAM[write_addr] <= write_data;
end
end
// Read operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Clear read_data on reset
read_data <= 0;
end else if (read_en) begin
// Read data from RAM
read_data <= RAM[read_addr];
end else begin
// Optionally clear read_data if not reading
read_data <= read_data; // Or you could clear it or do nothing
end
end
endmodule
|
module multi_pipe_8bit(
input wire clk,
input wire rst_n,
input wire mul_en_in,
input wire [7:0] mul_a,
input wire [7:0] mul_b,
output reg mul_en_out,
output reg [15:0] mul_out
);
// Intermediate registers for pipelined stages
reg [7:0] mul_a_reg, mul_b_reg;
reg [15:0] partial_products [7:0];
reg [15:0] sum [6:0]; // 7 intermediate sums
reg mul_en_out_reg; // Register for mul_en_in signal
// Input control logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
mul_a_reg <= 0;
mul_b_reg <= 0;
mul_en_out_reg <= 0;
end else if (mul_en_in) begin
mul_a_reg <= mul_a;
mul_b_reg <= mul_b;
mul_en_out_reg <= mul_en_in;
end
end
// Generate partial products
integer i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < 8; i = i + 1) begin
partial_products[i] <= 0;
end
end else begin
for (i = 0; i < 8; i = i + 1) begin
partial_products[i] <= mul_b_reg[i] ? (mul_a_reg << i) : 0;
end
end
end
// Calculate the intermediate sums
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < 7; i = i + 1) begin
sum[i] <= 0;
end
end else begin
sum[0] <= partial_products[0] + partial_products[1];
sum[1] <= partial_products[2] + partial_products[3];
sum[2] <= partial_products[4] + partial_products[5];
sum[3] <= partial_products[6] + partial_products[7];
sum[4] <= sum[0] + sum[1];
sum[5] <= sum[2] + sum[3];
sum[6] <= sum[4] + sum[5];
end
end
// Final product calculation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
mul_out <= 0;
mul_en_out <= 0;
end else begin
mul_out <= sum[6];
mul_en_out <= mul_en_out_reg;
end
end
endmodule
|
module parallel2serial (
input wire clk,
input wire rst_n,
input wire [3:0] d,
output reg valid_out,
output reg dout
);
// Internal counter to keep track of bit position
reg [1:0] cnt; // 2-bit counter for 4 clock cycles
// Register to hold the current state of the data
reg [3:0] data;
// On every clock edge...
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset the state and outputs
cnt <= 2'b0;
valid_out <= 1'b0;
dout <= 1'b0;
data <= 4'b0;
end else begin
// Check if it is time to load new data and reset the counter
if (cnt == 2'b11) begin
data <= d; // Load the new data
cnt <= 2'b0; // Reset the counter
valid_out <= 1'b1; // Output is valid
dout <= d[3]; // Start with MSB
end else begin
cnt <= cnt + 2'b1; // Increment the counter
valid_out <= (cnt == 2'b0) ? 1'b1 : 1'b0; // Valid only after loading new data or when counter is 0
data <= {data[2:0], 1'b0}; // Shift left the data
dout <= data[3]; // Output the leftmost bit
end
end
end
endmodule
|
module radix2_div #(parameter DATAWIDTH = 8) (
input wire clk,
input wire rstn,
input wire en,
input wire [DATAWIDTH-1:0] dividend,
input wire [DATAWIDTH-1:0] divisor,
output reg ready,
output reg [DATAWIDTH-1:0] quotient,
output reg [DATAWIDTH-1:0] remainder,
output reg vld_out
);
// State definitions
localparam IDLE = 2'b00,
SUB = 2'b01,
SHIFT = 2'b10,
DONE = 2'b11;
// FSM and data registers
reg [1:0] current_state, next_state;
reg [DATAWIDTH-1:0] dividend_e, divisor_e;
reg [DATAWIDTH-1:0] quotient_e, remainder_e;
reg [DATAWIDTH:0] count;
// Next state logic
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
current_state <= IDLE;
end else begin
current_state <= next_state;
end
end
// FSM, data registers, and output logic
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
dividend_e <= 0;
divisor_e <= 0;
quotient_e <= 0;
remainder_e <= 0;
count <= 0;
ready <= 1;
vld_out <= 0;
end else begin
case (current_state)
IDLE: begin
ready <= 1;
vld_out <= 0;
if (en) begin
dividend_e <= dividend;
divisor_e <= divisor;
quotient_e <= 0;
remainder_e <= 0;
count <= DATAWIDTH; // Set counter for number of iterations
next_state <= SUB;
ready <= 0;
end
end
SUB: begin
// Subtraction stage
if (dividend_e >= divisor_e) begin
remainder_e <= dividend_e - divisor_e;
quotient_e <= (quotient_e << 1) | 1;
end else begin
remainder_e <= dividend_e;
quotient_e <= quotient_e << 1;
end
next_state <= SHIFT;
end
SHIFT: begin
// Shifting stage
if (count > 0) begin
dividend_e <= remainder_e << 1;
count <= count - 1;
next_state <= SUB;
end else begin
next_state <= DONE;
end
end
DONE: begin
// Completion stage
quotient <= quotient_e;
remainder <= remainder_e;
vld_out <= 1;
next_state <= IDLE;
end
default: begin
next_state <= IDLE;
end
endcase
end
end
endmodule
|
module accu (
input wire clk,
input wire rst_n,
input wire [7:0] data_in,
input wire valid_in,
output reg valid_out,
output reg [9:0] data_out
);
// Define state to store input data and count the number of inputs
reg [9:0] sum;
reg [1:0] count;
// Always block to handle the accumulation and output generation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset state
sum <= 10'd0;
count <= 2'd0;
valid_out <= 1'b0;
data_out <= 10'd0;
end else begin
if (valid_in) begin
// When a valid input is provided, add it to the sum
sum <= sum + data_in;
count <= count + 1'b1; // Increment the count of valid inputs
// Reset the valid_out flag each cycle unless it's being set this cycle
valid_out <= 1'b0;
if (count == 2'd3) begin
// If four valid inputs have been accumulated, output the sum
data_out <= sum + data_in; // Include the current data_in in the sum
valid_out <= 1'b1; // Set valid_out high to indicate valid output
sum <= 10'd0; // Reset sum for the next round of accumulation
count <= 2'd0; // Reset count for the next round of accumulation
end
end
end
end
endmodule
|
module div_16bit(
input [15:0] A,
input [7:0] B,
output reg [15:0] result,
output reg [15:0] odd
);
integer i;
always @(*) begin
// Initialize the outputs
result = 0;
odd = A; // Start with the full dividend as the initial remainder
// Check for division by zero. This check can be enhanced to handle the error.
if (B == 0) begin
result = 16'hFFFF; // Indicate an error or overflow
odd = A;
end else begin
// Perform the division using a for loop to iterate over each bit
for (i = 15; i >= 0; i = i - 1) begin
// Shift left the result to make room for the next bit
result = result << 1;
// Extract the highest bits of the remainder to match divisor width
if (odd[15:8] >= B) begin
// Subtract the divisor from the extracted bits and get the new remainder
odd[15:8] = odd[15:8] - B;
// Since the remainder is larger, set the quotient bit to 1
result[0] = 1;
end
// Shift up the remainder to bring in the next bit of the dividend
if (i > 0) begin
odd = odd << 1;
odd[0] = A[i-1];
end
end
end
end
endmodule
|
module signal_generator (
input wire clk,
input wire rst_n,
output reg [4:0] wave // 5-bit signal for the waveform
);
// State declaration
reg state; // Use a 1-bit signal to store the state, 0 for incrementing, 1 for decrementing
// Waveform generation logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Active-low reset: clear the state and wave registers
state <= 0;
wave <= 5'b00000;
end else begin
case (state)
// State 0: Increment wave until it reaches 31
0: begin
if (wave == 5'b11111) begin
state <= 1; // Transition to state 1 to start decrementing
end else begin
wave <= wave + 1;
end
end
// State 1: Decrement wave until it reaches 0
1: begin
if (wave == 5'b00000) begin
state <= 0; // Transition back to state 0 to start incrementing
end else begin
wave <= wave - 1;
end
end
// Handle undefined states (should never occur with a well-defined 1-bit state)
default: begin
state <= 0;
wave <= 5'b00000;
end
endcase
end
end
endmodule
|
module multi_booth_8bit (
input clk,
input reset,
input [7:0] a,
input [7:0] b,
output reg [15:0] p,
output reg rdy
);
reg [7:0] multiplicand;
reg [8:0] multiplier; // extra bit for the booth algorithm
reg [3:0] ctr; // counter for the iterations
always @(posedge clk or posedge reset) begin
if (reset) begin
// Synchronous reset initialization
p <= 16'b0;
multiplicand <= a;
multiplier <= {1'b0, b}; // extra bit for the booth algorithm
ctr <= 4'b0;
rdy <= 1'b0;
end else begin
if (ctr < 8) begin
case (multiplier[1:0])
2'b01: p[15:0] <= p + {multiplicand, ctr[2:0]};
2'b10: p[15:0] <= p - {multiplicand, ctr[2:0]};
default: p <= p; // cases 2'b00 and 2'b11 result in no operation
endcase
// Shift multiplier to bring next pair of bits into position
multiplier <= multiplier >> 2;
ctr <= ctr + 1;
end else begin
rdy <= 1'b1; // Multiplication process is completed
end
end
end
endmodule
|
module pe (
input wire clk,
input wire rst,
input wire [31:0] a,
input wire [31:0] b,
output reg [63:0] c // Changed to 64 bits to avoid overflow
);
// Perform multiplication and accumulation on the positive edge of the clock
always @(posedge clk or posedge rst) begin
if (rst) begin
// Reset the accumulator to 0 when rst is high
c <= 64'b0; // Extended to 64 bits to hold the result without overflow
end else begin
// Multiply a and b, and accumulate the result
c <= c + (a * b); // Here, a * b is a 64-bit operation
end
end
endmodule
|
module alu (
input [31:0] a, b,
input [5:0] aluc,
output reg [31:0] r,
output zero,
output carry,
output negative,
output overflow,
output reg flag
);
// ALU control codes
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter LUI = 6'b001111;
// Temporary variables for calculations
reg [31:0] temp;
reg [63:0] extended_result;
// Set the zero flag
assign zero = (r == 32'b0);
// Set the negative flag
assign negative = r[31];
// Set the carry flag - only makes sense for addition/subtraction
assign carry = (aluc == ADD || aluc == SUB) && (extended_result[32]);
// Set the overflow flag - only makes sense for addition/subtraction
assign overflow = ((aluc == ADD || aluc == SUB) &&
((a[31] && b[31] && !r[31]) ||
(!a[31] && !b[31] && r[31])));
always @(*) begin
flag = 1'b0; // Default flag
case (aluc)
ADD: begin
extended_result = {1'b0, a} + {1'b0, b};
r = extended_result[31:0];
end
ADDU: r = a + b;
SUB: begin
extended_result = {1'b0, a} - {1'b0, b};
r = extended_result[31:0];
end
SUBU: r = a - b;
AND: r = a & b;
OR: r = a | b;
XOR: r = a ^ b;
NOR: r = ~(a | b);
SLT: begin
r = $signed(a) < $signed(b);
flag = r;
end
SLTU: begin
r = a < b;
flag = r;
end
SLL: r = b << a[4:0];
SRL: r = b >> a[4:0];
SRA: r = $signed(b) >>> a[4:0];
SLLV: r = b << a;
SRLV: r = b >> a;
SRAV: r = $signed(b) >>> a;
LUI: r = {b[15:0], 16'b0};
default: r = 32'bz; // High-impedance for undefined operation
endcase
end
endmodule
|
module adder_16bit (
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
// Wires for the carry between lower and upper 8-bit adders
wire carry;
// Instantiate the 8-bit adders
adder_8bit lower_adder (
.a(a[7:0]),
.b(b[7:0]),
.cin(Cin),
.sum(y[7:0]),
.cout(carry) // Carry from lower 8 bits
);
adder_8bit upper_adder (
.a(a[15:8]),
.b(b[15:8]),
.cin(carry), // Carry from lower 8 bits
.sum(y[15:8]),
.cout(Co) // Carry out from the entire 16-bit adder
);
endmodule
|
module adder_8bit (
input wire [7:0] a,
input wire [7:0] b,
input wire cin,
output wire [7:0] sum,
output wire cout
);
wire [6:0] carry;
// Instantiate the 1-bit full adders
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : full_adder_loop
if (i == 0) begin
full_adder fa (
.a(a[i]),
.b(b[i]),
.cin(cin),
.sum(sum[i]),
.cout(carry[i])
);
end else if (i == 7) begin
full_adder fa (
.a(a[i]),
.b(b[i]),
.cin(carry[i-1]),
.sum(sum[i]),
.cout(cout)
);
end else begin
full_adder fa (
.a(a[i]),
.b(b[i]),
.cin(carry[i-1]),
.sum(sum[i]),
.cout(carry[i])
);
end
end
endgenerate
endmodule
|
module full_adder (
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule
|
module pulse_detect(
input wire clk,
input wire rst_n,
input wire data_in,
output reg data_out
);
// State declaration to keep track of the previous, current, and next input states
reg [2:0] shift_reg;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset condition
shift_reg <= 3'b000;
data_out <= 1'b0;
end else begin
// Shift the register and input the new data
shift_reg <= {shift_reg[1:0], data_in};
// Detecting a pulse
// A pulse is detected when the register holds 010
if (shift_reg == 3'b010) begin
data_out <= 1'b1; // Pulse detected, set output high
end else begin
data_out <= 1'b0; // No pulse, set output low
end
end
end
endmodule
|
module synchronizer (
input wire clk_a,
input wire clk_b,
input wire arstn,
input wire brstn,
input wire [3:0] data_in,
input wire data_en,
output reg [3:0] dataout
);
// Internal register declarations
reg [3:0] data_reg_a; // Register on clock A domain
reg en_data_reg_a; // Enable register on clock A domain
reg en_data_reg_b; // Enable register on clock B domain (first stage)
reg en_data_reg_bb; // Enable register on clock B domain (second stage)
// Data register update with clock A
always @(posedge clk_a or negedge arstn) begin
if (!arstn) begin
data_reg_a <= 4'b0000;
en_data_reg_a <= 1'b0;
end else begin
data_reg_a <= data_in;
en_data_reg_a <= data_en;
end
end
// Enable signal synchronization with clock B
always @(posedge clk_b or negedge brstn) begin
if (!brstn) begin
en_data_reg_b <= 1'b0;
en_data_reg_bb <= 1'b0;
end else begin
en_data_reg_b <= en_data_reg_a;
en_data_reg_bb <= en_data_reg_b;
end
end
// Output assignment with clock B
always @(posedge clk_b or negedge brstn) begin
if (!brstn) begin
dataout <= 4'b0000;
end else if (en_data_reg_bb) begin
dataout <= data_reg_a; // Synchronized data transfer on the second enable activation
end
// No need for an else clause to retain the previous value, as this is implicit with registers
end
endmodule
|
module calendar(
input CLK, // Clock input
input RST, // Active high reset
output reg [5:0] Hours, // 6-bit hours (0-23)
output reg [5:0] Mins, // 6-bit minutes (0-59)
output reg [5:0] Secs // 6-bit seconds (0-59)
);
// Seconds logic
always @(posedge CLK or posedge RST) begin
if (RST) begin
Secs <= 0;
end else if (Secs == 59) begin
Secs <= 0;
end else begin
Secs <= Secs + 1;
end
end
// Minutes logic
always @(posedge CLK or posedge RST) begin
if (RST) begin
Mins <= 0;
end else if (Secs == 59 && Mins == 59) begin
Mins <= 0;
end else if (Secs == 59) begin
Mins <= Mins + 1;
end
end
// Hours logic
always @(posedge CLK or posedge RST) begin
if (RST) begin
Hours <= 0;
end else if (Secs == 59 && Mins == 59 && Hours == 23) begin
Hours <= 0;
end else if (Secs == 59 && Mins == 59) begin
Hours <= Hours + 1;
end
end
endmodule
|
module traffic_light(
input wire rst_n,
input wire clk,
input wire pass_request,
output reg [7:0] clock,
output reg red,
output reg yellow,
output reg green
);
// Parameters for the traffic light timing
parameter GREEN_TIME = 60;
parameter YELLOW_TIME = 5;
parameter RED_TIME = 10;
// State enumeration
parameter IDLE = 2'b00, S1_RED = 2'b01, S2_YELLOW = 2'b10, S3_GREEN = 2'b11;
// Registers
reg [7:0] cnt;
reg [1:0] state;
reg [1:0] next_state;
// State transition logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
// Next state logic and timer count down
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= RED_TIME;
next_state <= S1_RED;
end else begin
case (state)
IDLE: begin
cnt <= RED_TIME;
next_state <= S1_RED;
end
S1_RED: begin
if (cnt == 0) begin
cnt <= GREEN_TIME;
next_state <= S3_GREEN;
end else begin
cnt <= cnt - 1;
end
end
S2_YELLOW: begin
if (cnt == 0) begin
cnt <= RED_TIME;
next_state <= S1_RED;
end else begin
cnt <= cnt - 1;
end
end
S3_GREEN: begin
if (pass_request && cnt > 10) begin
cnt <= 10;
end else if (cnt == 0) begin
cnt <= YELLOW_TIME;
next_state <= S2_YELLOW;
end else begin
cnt <= cnt - 1;
end
end
default: begin
cnt <= RED_TIME;
next_state <= S1_RED;
end
endcase
end
end
// Output logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
red <= 1'b0;
yellow <= 1'b0;
green <= 1'b0;
end else begin
case (next_state)
S1_RED: begin
red <= 1'b1;
yellow <= 1'b0;
green <= 1'b0;
end
S2_YELLOW: begin
red <= 1'b0;
yellow <= 1'b1;
green <= 1'b0;
end
S3_GREEN: begin
red <= 1'b0;
yellow <= 1'b0;
green <= 1'b1;
end
default: begin
red <= 1'b0;
yellow <= 1'b0;
green <= 1'b0;
end
endcase
end
end
// Assign the count value to the output clock
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
clock <= 8'b0;
end else begin
clock <= cnt;
end
end
endmodule
|
module width_8to16(
input wire clk,
input wire rst_n,
input wire valid_in,
input wire [7:0] data_in,
output reg valid_out,
output reg [15:0] data_out
);
// Internal signal to track the stored byte
reg [7:0] data_lock;
// Internal signal to indicate if we've stored the first byte
reg flag;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset the state
data_out <= 16'd0;
valid_out <= 1'b0;
data_lock <= 8'd0;
flag <= 1'b0;
end else if (valid_in) begin
if (flag) begin
// We've received the second byte, concatenate
data_out <= {data_lock, data_in};
valid_out <= 1'b1;
flag <= 1'b0; // Reset the flag as we've used the stored byte
end else begin
// Store the first byte and wait for the second byte
data_lock <= data_in;
flag <= 1'b1;
valid_out <= 1'b0; // Output is not valid until we have two bytes
end
end else if (flag) begin
// If we have a stored byte but no new valid input, keep outputs invalid
valid_out <= 1'b0;
end
end
endmodule
|
module JC_counter(
input clk,
input rst_n,
output reg [63:0] Q
);
// On every rising edge of the clock or falling edge of reset
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Active-low reset condition; reset the counter value
Q <= 64'b0;
end else begin
// Check the least significant bit to decide on appending a '1' or '0'
if (Q[0] == 1'b0) begin
// LSB is '0', so shift left and append '1' at the MSB
Q <= {Q[62:0], 1'b1};
end else begin
// LSB is '1', so shift left and append '0' at the MSB (inverting the sequence)
Q <= {Q[62:0], 1'b0};
end
end
end
endmodule
|
module adder_pipe_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
// Pipeline stage registers
reg [31:0] adda_stage1, addb_stage1;
reg [63:0] sum_stage1;
reg carry_stage1;
reg stage1_en, stage2_en;
// Intermediate sum and carry
wire [31:0] sum_lower, sum_upper;
wire carry_lower, carry_upper;
// Lower 32-bit adder
assign {carry_lower, sum_lower} = adda[31:0] + addb[31:0];
// Upper 32-bit adder with carry-in
assign {carry_upper, sum_upper} = adda[63:32] + addb[63:32] + carry_stage1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset all pipeline registers and outputs
{adda_stage1, addb_stage1} <= 0;
sum_stage1 <= 0;
carry_stage1 <= 0;
result <= 0;
stage1_en <= 0;
stage2_en <= 0;
o_en <= 0;
end else begin
// Pipeline stage 1
if (i_en) begin
adda_stage1 <= adda[31:0];
addb_stage1 <= addb[31:0];
sum_stage1 <= {sum_upper, sum_lower};
carry_stage1 <= carry_lower;
stage1_en <= 1;
end
// Pipeline stage 2
if (stage1_en) begin
result <= {carry_upper, sum_stage1};
stage2_en <= 1;
end
// Output enable logic
o_en <= stage2_en;
if (stage2_en) begin
// Clear enable signals for the next operation
stage1_en <= 0;
stage2_en <= 0;
end
end
end
endmodule
|
module right_shifter (
input wire clk,
input wire d,
output reg [7:0] q
);
// Initialize the q register to 0
initial begin
q = 8'b00000000;
end
// Perform the right shift operation on the rising edge of the clock
always @(posedge clk) begin
q <= {d, q[7:1]}; // Insert the input bit d into the most significant bit of q, and shift the rest right
end
endmodule
|
module serial2parallel(
input wire clk,
input wire rst_n,
input wire din_serial,
input wire din_valid,
output reg [7:0] dout_parallel,
output reg dout_valid
);
// Internal counter to keep track of the number of bits received
reg [2:0] cnt;
// Reset and data shifting is handled on the rising edge of the clock
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// When reset is asserted, clear the counter and output registers
cnt <= 3'b000;
dout_parallel <= 8'b00000000;
dout_valid <= 1'b0;
end else if (din_valid) begin
// Shift in the serial data into dout_parallel starting with the MSB
dout_parallel <= {din_serial, dout_parallel[7:1]};
// Increment the counter
cnt <= cnt + 3'b001;
// If 8 bits have been received, indicate that dout_parallel is valid
if (cnt == 3'b111) begin
dout_valid <= 1'b1;
cnt <= 3'b000; // Reset the counter for the next batch of 8 bits
end else begin
dout_valid <= 1'b0;
end
end else begin
// When din_valid is not high, do not shift in new data
dout_valid <= 1'b0;
end
end
endmodule
|
module multi_16bit (
input wire clk,
input wire rst_n,
input wire start,
input wire [15:0] ain,
input wire [15:0] bin,
output reg [31:0] yout,
output reg done
);
// Internal signals
reg [31:0] product;
reg [15:0] multiplicand;
reg [15:0] multiplier;
reg [4:0] count; // 16-bit multiplier requires a 5-bit counter
// Control FSM states
localparam IDLE = 0, MULTIPLY = 1, DONE = 2;
reg [1:0] state;
// FSM for controlling the multiplication process
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Synchronous reset
state <= IDLE;
product <= 0;
multiplicand <= 0;
multiplier <= 0;
count <= 0;
done <= 0;
end else begin
case (state)
IDLE: begin
if (start) begin
multiplicand <= ain;
multiplier <= bin;
product <= 0;
count <= 0;
state <= MULTIPLY;
done <= 0;
end
end
MULTIPLY: begin
if (count < 16) begin
// Perform shift and add
if (multiplier[0]) begin
product <= product + (multiplicand << count);
end
multiplier <= multiplier >> 1;
count <= count + 1;
end else begin
state <= DONE;
end
end
DONE: begin
// Multiplication done, assert done signal
done <= 1;
state <= IDLE; // Optionally, go back to IDLE or wait for a reset or a new start
end
default: state <= IDLE;
endcase
end
end
// Assign the output
always @(posedge clk) begin
if (state == DONE) begin
yout <= product; // Assign the product to output when done
end
end
endmodule
|
module freq_div(
input CLK_in, // Input clock signal at 100MHz
input RST, // Active high reset signal
output reg CLK_50, // Output clock signal at 50MHz
output reg CLK_10, // Output clock signal at 10MHz
output reg CLK_1 // Output clock signal at 1MHz
);
// Counter for the 10MHz clock generation
reg [2:0] cnt_10; // 3-bit counter for dividing by 10
// Counter for the 1MHz clock generation
reg [5:0] cnt_100; // 6-bit counter for dividing by 100
// CLK_50 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
// Reset condition
CLK_50 <= 1'b0;
end else begin
// Toggle CLK_50 every clock cycle to divide the frequency by 2
CLK_50 <= ~CLK_50;
end
end
// CLK_10 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
// Reset condition
CLK_10 <= 1'b0;
cnt_10 <= 3'd0;
end else begin
if (cnt_10 == 3'd4) begin
// Toggle CLK_10 and reset the counter
CLK_10 <= ~CLK_10;
cnt_10 <= 3'd0;
end else begin
// Increment the counter
cnt_10 <= cnt_10 + 1;
end
end
end
// CLK_1 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
// Reset condition
CLK_1 <= 1'b0;
cnt_100 <= 6'd0;
end else begin
if (cnt_100 == 6'd49) begin
// Toggle CLK_1 and reset the counter
CLK_1 <= ~CLK_1;
cnt_100 <= 6'd0;
end else begin
// Increment the counter
cnt_100 <= cnt_100 + 1;
end
end
end
endmodule
|
module counter_12 (
input wire rst_n,
input wire clk,
input wire valid_count,
output reg [3:0] out
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Active low reset
out <= 4'b0000;
end else if (valid_count) begin
if (out == 4'd11) begin
// Reset to 0 if the counter reaches 11
out <= 4'b0000;
end else begin
// Increment the counter
out <= out + 1;
end
end
// Counter holds the value if valid_count is 0
end
endmodule
|
module edge_detect(
input clk, // Clock signal
input rst_n, // Reset signal (active low)
input a, // Input signal
output reg rise, // Output signal indicating a rising edge
output reg down // Output signal indicating a falling edge
);
// Register to hold the previous value of 'a'
reg a_prev;
// Edge detection is done on positive clock edge
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Asynchronous reset: outputs and previous value register are reset
rise <= 1'b0;
down <= 1'b0;
a_prev <= 1'b0;
end else begin
// On every clock edge, update the rise and down signals
rise <= (a_prev == 1'b0 && a == 1'b1); // Rising edge detected
down <= (a_prev == 1'b1 && a == 1'b0); // Falling edge detected
// Update the previous value of 'a'
a_prev <= a;
end
end
endmodule
|
module adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire C16; // Carry out from the lower 16-bit CLA block
// Instantiate two 16-bit CLA blocks
cla_16bit cla_lower(
.A(A[16:1]),
.B(B[16:1]),
.cin(1'b0), // no carry-in for the least significant block
.S(S[16:1]),
.cout(C16)
);
cla_16bit cla_upper(
.A(A[32:17]),
.B(B[32:17]),
.cin(C16), // carry-in is the carry-out from the lower 16-bit block
.S(S[32:17]),
.cout(C32)
);
endmodule
|
module cla_16bit(
input [16:1] A,
input [16:1] B,
input cin,
output [16:1] S,
output cout
);
wire [4:0] c; // intermediate carries between CLA blocks, c[0] is cin
assign c[0] = cin;
// Instantiate four 4-bit CLA blocks
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : cla_block
cla_4bit cla_unit(
.A(A[i*4+4:i*4+1]),
.B(B[i*4+4:i*4+1]),
.cin(c[i]),
.S(S[i*4+4:i*4+1]),
.cout(c[i+1])
);
end
endgenerate
assign cout = c[4]; // The carry-out of the last CLA block is the carry-out of the entire 16-bit block
endmodule
|
module cla_4bit(
input [4:1] A,
input [4:1] B,
input cin,
output [4:1] S,
output cout
);
wire [4:1] g; // generate
wire [4:1] p; // propagate
wire [4:0] c; // carries, c[0] is cin
// Generate and propagate terms
assign g = A & B;
assign p = A ^ B;
// Calculate carries
assign c[0] = cin;
assign c[1] = g[1] | (p[1] & c[0]);
assign c[2] = g[2] | (p[2] & c[1]);
assign c[3] = g[3] | (p[3] & c[2]);
assign c[4] = g[4] | (p[4] & c[3]);
// Calculate the sum
assign S = p ^ c[4:1];
// Carry-out is the last carry bit
assign cout = c[4];
endmodule
|
module adder_8bit (
input wire [7:0] a,
input wire [7:0] b,
input wire cin,
output wire [7:0] sum,
output wire cout
);
wire [6:0] carry; // Internal carry wires
// Instantiate 8 full adders
full_adder FA0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(carry[0])
);
full_adder FA1 (
.a(a[1]),
.b(b[1]),
.cin(carry[0]),
.sum(sum[1]),
.cout(carry[1])
);
full_adder FA2 (
.a(a[2]),
.b(b[2]),
.cin(carry[1]),
.sum(sum[2]),
.cout(carry[2])
);
full_adder FA3 (
.a(a[3]),
.b(b[3]),
.cin(carry[2]),
.sum(sum[3]),
.cout(carry[3])
);
full_adder FA4 (
.a(a[4]),
.b(b[4]),
.cin(carry[3]),
.sum(sum[4]),
.cout(carry[4])
);
full_adder FA5 (
.a(a[5]),
.b(b[5]),
.cin(carry[4]),
.sum(sum[5]),
.cout(carry[5])
);
full_adder FA6 (
.a(a[6]),
.b(b[6]),
.cin(carry[5]),
.sum(sum[6]),
.cout(carry[6])
);
full_adder FA7 (
.a(a[7]),
.b(b[7]),
.cin(carry[6]),
.sum(sum[7]),
.cout(cout)
);
endmodule
|
module multi_pipe_8bit (
input wire clk,
input wire rst_n,
input wire mul_en_in,
input wire [7:0] mul_a,
input wire [7:0] mul_b,
output reg mul_en_out,
output reg [15:0] mul_out
);
// Register declarations for pipeline stages
reg [7:0] reg_a, reg_b; // Registers to hold inputs in the first stage
reg [15:0] partial_product; // Register to hold the partial product
reg mul_en_in_reg; // Register to hold the input enable signal
// Pipeline stage 1 - capturing the inputs and enabling the multiplication
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg_a <= 0;
reg_b <= 0;
mul_en_in_reg <= 0;
end else if (mul_en_in) begin
reg_a <= mul_a;
reg_b <= mul_b;
mul_en_in_reg <= mul_en_in;
end
end
// Pipeline stage 2 - performing the multiplication
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
partial_product <= 0;
mul_en_out <= 0;
end else begin
if (mul_en_in_reg) begin
// Perform multiplication when enabled
partial_product <= reg_a * reg_b;
mul_en_out <= mul_en_in_reg; // Propagate the enable signal to the output
end else begin
partial_product <= 0; // Reset partial product if not enabled
mul_en_out <= 0; // Reset output enable signal
end
end
end
// Output assignment
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
mul_out <= 0;
end else begin
if (mul_en_out) begin
// Output the final product when enabled
mul_out <= partial_product;
end else begin
mul_out <= 0; // Reset output if not enabled
end
end
end
endmodule
|
module parallel2serial(
input wire clk,
input wire rst_n,
input wire [3:0] d,
output reg valid_out,
output reg dout
);
// Internal registers
reg [2:0] cnt; // 3-bit counter to track the bit position
reg [3:0] data; // Register to hold the current state of data being serialized
// Sequential logic for counter and data register
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Asynchronous reset
cnt <= 3'd0;
data <= 4'd0;
valid_out <= 1'b0;
end else begin
// Check if we are on the last bit
if (cnt == 3'd3) begin
// Load new data and reset counter
data <= d;
cnt <= 3'd0;
valid_out <= 1'b1; // Output is valid on the loading of new data
end else begin
// Shift data and increment counter
data <= {data[2:0], 1'b0};
cnt <= cnt + 3'd1;
valid_out <= (cnt == 3'd0) ? 1'b1 : 1'b0; // Output is valid only if the counter was 0 before incrementing
end
end
end
// Combinational logic for serial output
always @(*) begin
// dout is assigned the MSB of the data register
dout = data[3];
end
endmodule
|
module radix2_div #(
parameter DATAWIDTH = 8
)(
input wire clk,
input wire rstn,
input wire en,
input wire [DATAWIDTH-1:0] dividend,
input wire [DATAWIDTH-1:0] divisor,
output reg ready,
output reg [DATAWIDTH-1:0] quotient,
output reg [DATAWIDTH-1:0] remainder,
output reg vld_out
);
// State definitions
localparam IDLE = 2'b00,
SUB = 2'b01,
SHIFT = 2'b10,
DONE = 2'b11;
// FSM and data registers
reg [1:0] current_state, next_state;
reg [DATAWIDTH-1:0] dividend_e, divisor_e, quotient_e, remainder_e;
reg [DATAWIDTH:0] count; // Count needs an extra bit to go up to DATAWIDTH
// State transition logic
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
current_state <= IDLE;
end else begin
current_state <= next_state;
end
end
// Next state and data computation logic
always @(*) begin
// Default assignments
next_state = current_state;
ready = 1'b0;
vld_out = 1'b0;
dividend_e = dividend_e;
divisor_e = divisor_e << 1;
quotient_e = quotient_e;
remainder_e = remainder_e;
case (current_state)
IDLE: begin
ready = 1'b1;
if (en) begin
dividend_e = dividend;
divisor_e = divisor;
quotient_e = 0;
remainder_e = 0;
count = DATAWIDTH;
next_state = SUB;
end
end
SUB: begin
// Perform subtraction if the remainder is greater or equal to divisor
if (remainder_e >= divisor_e) begin
remainder_e = remainder_e - divisor_e;
quotient_e = (quotient_e << 1) | 1'b1;
end else begin
quotient_e = quotient_e << 1;
end
next_state = SHIFT;
end
SHIFT: begin
if (count == 0) begin
next_state = DONE;
end else begin
remainder_e = remainder_e << 1;
remainder_e[0] = dividend_e[DATAWIDTH-1];
dividend_e = dividend_e << 1;
count = count - 1'b1;
next_state = SUB;
end
end
DONE: begin
quotient = quotient_e;
remainder = remainder_e;
vld_out = 1'b1;
if (!en) begin
next_state = IDLE;
end
end
endcase
end
// Asynchronous reset logic
always @(negedge rstn) begin
if (!rstn) begin
quotient <= 0;
remainder <= 0;
dividend_e <= 0;
divisor_e <= 0;
quotient_e <= 0;
remainder_e <= 0;
count <= 0;
ready <= 0;
vld_out <= 0;
current_state <= IDLE;
end
end
endmodule
|
module accu (
input wire clk,
input wire rst_n,
input wire [7:0] data_in,
input wire valid_in,
output reg valid_out,
output reg [9:0] data_out
);
// Internal signals
reg [9:0] sum;
reg [1:0] count;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset
sum <= 10'd0;
count <= 2'd0;
data_out <= 10'd0;
valid_out <= 1'b0;
end else begin
if (valid_in) begin
// When valid_in is high, accumulate the data
if (count < 3) begin
// Accumulate data if count is less than 3
sum <= sum + data_in;
count <= count + 1'b1;
valid_out <= 1'b0;
end else begin
// On the 4th data, output the sum and reset
sum <= sum + data_in;
data_out <= sum + data_in;
valid_out <= 1'b1;
sum <= 10'd0; // Reset sum
count <= 2'd0; // Reset count
end
end else if (valid_out) begin
// Ensure valid_out is high for only 1 cycle
valid_out <= 1'b0;
end
end
end
endmodule
|
module div_16bit(
input [15:0] A, // 16-bit dividend
input [7:0] B, // 8-bit divisor
output reg [15:0] result, // 16-bit quotient
output reg [15:0] odd // 16-bit remainder
);
// Internal signals for the operation
reg [15:0] dividend;
reg [8:0] divisor; // 9 bits to accommodate subtraction
reg [15:0] quotient;
reg [15:0] remainder;
integer i;
always @(*) begin
// Initialize the internal signals
dividend = A;
divisor = {1'b0, B}; // Extend divisor to 9 bits for subtraction
quotient = 0;
remainder = 0;
// Perform division operation
for (i = 15; i >= 0; i = i - 1) begin
// Shift the remainder to the left by 1 bit
remainder = remainder << 1;
// Bring down the next bit from the dividend
remainder[0] = dividend[i];
// Compare the upper bits of the remainder with the divisor
if (remainder[8:1] >= divisor) begin
// If remainder is greater or equal, subtract divisor from remainder
remainder = remainder - divisor;
// Set the quotient bit to 1
quotient[i] = 1'b1;
end
else begin
// Otherwise, the quotient bit remains 0
quotient[i] = 1'b0;
end
end
// Set the output values
result = quotient;
odd = remainder;
end
endmodule
|
module signal_generator(
input wire clk,
input wire rst_n,
output reg [4:0] wave
);
// Internal state register to control the direction of the count
reg state;
// Define the state values for clarity
localparam STATE_UP = 1'b0;
localparam STATE_DOWN = 1'b1;
// Reset and waveform generation are handled on the rising edge of the clock
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Resetting the module
wave <= 5'b00000;
state <= STATE_UP; // Start by incrementing
end else begin
case (state)
STATE_UP: begin
// Check if wave reached the max value
if (wave == 5'b11111) begin
state <= STATE_DOWN; // Change state to down
wave <= wave - 1'b1;
end else begin
wave <= wave + 1'b1; // Increment wave
end
end
STATE_DOWN: begin
// Check if wave reached the min value
if (wave == 5'b00000) begin
state <= STATE_UP; // Change state to up
wave <= wave + 1'b1;
end else begin
wave <= wave - 1'b1; // Decrement wave
end
end
default: begin
// In case of an undefined state, reset to known state
state <= STATE_UP;
wave <= 5'b00000;
end
endcase
end
end
endmodule
|
module multi_booth_8bit (
input wire clk,
input wire reset,
input wire [7:0] a,
input wire [7:0] b,
output reg [15:0] p,
output reg rdy
);
// Internal signals
reg [7:0] multiplicand; // Extended multiplicand
reg [8:0] multiplier; // Extended multiplier and an extra bit for the algorithm
reg [4:0] ctr; // 5-bit counter (for 8-bit multiplication, we need 8*2 steps)
reg [16:0] product; // Extended product to hold intermediate values (1 extra bit)
reg neg;
// Booth multiplier control logic
always @(posedge clk or posedge reset) begin
if (reset) begin
// Reset the multiplier
multiplicand <= 0;
multiplier <= {1'b0, b};
product <= 0;
ctr <= 0;
rdy <= 0;
neg <= 0;
end else begin
if (ctr < 9) begin
// Radix-2 Booth's algorithm operations
case ({multiplier[1], multiplier[0]})
2'b01: product[16:1] <= product[16:1] + {a, 1'b0};
2'b10: product[16:1] <= product[16:1] - {a, 1'b0};
default: ; // No operation for 00 and 11
endcase
// Prepare for the next iteration
product <= product >> 1; // Arithmetic shift right
product[16] <= product[15]; // Sign extension
multiplier <= multiplier >> 1; // Logical shift right
ctr <= ctr + 1;
end else if (ctr == 9) begin
// Final step: adjust for sign extension if needed
if (neg) begin
product <= product - {a, 8'h00};
end
p <= product[16:1]; // Assign the final product
rdy <= 1; // Indicate completion
ctr <= ctr + 1; // Increment counter to stop the process
end
end
end
endmodule
|
module pe(
input wire clk,
input wire rst,
input wire [31:0] a,
input wire [31:0] b,
output reg [31:0] c
);
// Multiplication and accumulation
always @(posedge clk or posedge rst) begin
if (rst) begin
// Synchronous reset: set the accumulator to zero
c <= 32'd0;
end else begin
// Multiply and accumulate
c <= c + (a * b);
end
end
endmodule
|
module alu (
input [31:0] a,
input [31:0] b,
input [5:0] aluc,
output reg [31:0] r,
output zero,
output reg carry,
output reg negative,
output reg overflow,
output reg flag
);
// Opcodes for the operations
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter LUI = 6'b001111;
// Assign zero flag
assign zero = (r == 32'b0);
always @(*) begin
carry = 1'b0;
overflow = 1'b0;
negative = 1'b0;
flag = 1'b0;
case (aluc)
ADD: begin
{carry, r} = a + b;
overflow = (a[31] & b[31] & ~r[31]) | (~a[31] & ~b[31] & r[31]);
end
ADDU: begin
r = a + b; // Carry is ignored in ADDU.
end
SUB: begin
{carry, r} = a - b;
overflow = (~a[31] & b[31] & r[31]) | (a[31] & ~b[31] & ~r[31]);
end
SUBU: begin
r = a - b; // Carry is ignored in SUBU.
end
AND: r = a & b;
OR: r = a | b;
XOR: r = a ^ b;
NOR: r = ~(a | b);
SLT: begin
r = $signed(a) < $signed(b);
flag = r[0];
end
SLTU: begin
r = a < b;
flag = r[0];
end
SLL: r = b << a[4:0];
SRL: r = b >> a[4:0];
SRA: r = $signed(b) >>> a[4:0];
SLLV: r = b << a;
SRLV: r = b >> a;
SRAV: r = $signed(b) >>> a;
LUI: r = {b[15:0], 16'b0};
default: r = 32'hz; // High-impedance for undefined operations
endcase
negative = r[31]; // Set the negative flag based on the result's sign bit.
end
endmodule
|
module pulse_detect (
input wire clk,
input wire rst_n,
input wire data_in,
output reg data_out
);
// State definitions (one-hot encoding for clarity)
localparam [2:0] IDLE = 3'b001,
PULSE_START = 3'b010,
PULSE_END = 3'b100;
// State register
reg [2:0] current_state, next_state;
// Sequential logic for state transition
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Synchronous reset (active low)
current_state <= IDLE;
data_out <= 1'b0;
end else begin
current_state <= next_state; // State transition
end
end
// Combinatorial logic for next state and output
always @(*) begin
// Default assignments
next_state = current_state;
data_out = 1'b0;
case (current_state)
IDLE: begin
// Waiting for pulse start
if (data_in == 1'b1) begin
next_state = PULSE_START;
end
end
PULSE_START: begin
// Pulse started, waiting for pulse end
if (data_in == 1'b0) begin
next_state = PULSE_END;
end
end
PULSE_END: begin
// End of pulse detected, generate output pulse
data_out = 1'b1;
// Wait for next pulse
if (data_in == 1'b0) begin
next_state = IDLE;
end else if (data_in == 1'b1) begin
// Handle case where pulse remains high and goes back to low
next_state = PULSE_START;
end
end
default: begin
// Should not reach here, but return to a known state
next_state = IDLE;
end
endcase
end
endmodule
|
module synchronizer(
input wire clk_a,
input wire clk_b,
input wire arstn,
input wire brstn,
input wire [3:0] data_in,
input wire data_en,
output reg [3:0] dataout
);
// Register to store the input data
reg [3:0] data_reg;
// Register to store the input enable signal
reg en_data_reg;
// Registers to synchronize the enable signal with clk_b
reg en_clk_b_one;
reg en_clk_b_two;
// Synchronize data_in with clk_a
always @(posedge clk_a or negedge arstn) begin
if (~arstn) begin
data_reg <= 4'b0000; // Clear data register on reset
end else if (data_en) begin
data_reg <= data_in; // Update data register when data_en is high
end
end
// Synchronize data_en with clk_a
always @(posedge clk_a or negedge arstn) begin
if (~arstn) begin
en_data_reg <= 1'b0; // Clear enable data register on reset
end else begin
en_data_reg <= data_en; // Update enable data register
end
end
// Two-stage synchronizer for enable signal with clk_b
always @(posedge clk_b or negedge brstn) begin
if (~brstn) begin
en_clk_b_one <= 1'b0;
en_clk_b_two <= 1'b0;
end else begin
en_clk_b_one <= en_data_reg; // First D flip-flop stage
en_clk_b_two <= en_clk_b_one; // Second D flip-flop stage
end
end
// Dataout based on the synchronized enable signal
always @(posedge clk_b or negedge brstn) begin
if (~brstn) begin
dataout <= 4'b0000; // Clear output data on reset
end else if (en_clk_b_two) begin
dataout <= data_reg; // Update output data when enable signal is high
end
end
endmodule
|
module calendar (
input CLK, // Clock input
input RST, // Active high reset signal
output reg [5:0] Hours, // 6-bit output for hours (0-23)
output reg [5:0] Mins, // 6-bit output for minutes (0-59)
output reg [5:0] Secs // 6-bit output for seconds (0-59)
);
// Update seconds
always @(posedge CLK or posedge RST) begin
if (RST) begin
// Reset seconds to 0
Secs <= 6'd0;
end else if (Secs == 6'd59) begin
// Reset seconds and increment minutes
Secs <= 6'd0;
end else begin
// Increment seconds
Secs <= Secs + 6'd1;
end
end
// Update minutes
always @(posedge CLK or posedge RST) begin
if (RST) begin
// Reset minutes to 0
Mins <= 6'd0;
end else if (Secs == 6'd59) begin
if (Mins == 6'd59) begin
// Reset minutes when seconds and minutes are both 59
Mins <= 6'd0;
end else begin
// Increment minutes
Mins <= Mins + 6'd1;
end
end
// If Secs is not 59, keep Mins unchanged
end
// Update hours
always @(posedge CLK or posedge RST) begin
if (RST) begin
// Reset hours to 0
Hours <= 6'd0;
end else if ((Mins == 6'd59) && (Secs == 6'd59)) begin
if (Hours == 6'd23) begin
// Reset hours when seconds, minutes, and hours are at their max
Hours <= 6'd0;
end else begin
// Increment hours
Hours <= Hours + 6'd1;
end
end
// If Secs is not 59 or Mins is not 59, keep Hours unchanged
end
endmodule
|
module traffic_light(
input wire rst_n,
input wire clk,
input wire pass_request,
output reg [7:0] clock,
output reg red,
output reg yellow,
output reg green
);
// State declarations
parameter idle = 2'b00, s1_red = 2'b01, s2_yellow = 2'b10, s3_green = 2'b11;
// Internal counter
reg [7:0] cnt;
// Current state
reg [1:0] state;
// Next state logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= idle;
end else begin
case (state)
idle: state <= s1_red; // Start with red
s1_red: if (cnt == 0) state <= s3_green; // Move to green after red
s2_yellow: if (cnt == 0) state <= s1_red; // Move to red after yellow
s3_green: if (cnt == 0) state <= s2_yellow; // Move to yellow after green
default: state <= idle;
endcase
end
end
// Counter logic to handle timing and pedestrian button
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 10; // Reset to 10 at start
end else begin
if (cnt == 0) begin
// Set the counter based on the current state when count reaches 0
case (state)
s1_red: cnt <= 60;
s2_yellow: cnt <= 5;
s3_green: cnt <= 10;
default: cnt <= 10;
endcase
end else if (pass_request && state == s3_green && cnt > 10) begin
cnt <= 10; // Shorten green time if pass_request is active
end else begin
cnt <= cnt - 1; // Normal countdown
end
end
end
// Assign the current count value to the clock output
always @(cnt) begin
clock <= cnt;
end
// Output logic for the traffic light signals
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
red <= 1'b0;
yellow <= 1'b0;
green <= 1'b0;
end else begin
case (state)
s1_red: begin
red <= 1'b1;
yellow <= 1'b0;
green <= 1'b0;
end
s2_yellow: begin
red <= 1'b0;
yellow <= 1'b1;
green <= 1'b0;
end
s3_green: begin
red <= 1'b0;
yellow <= 1'b0;
green <= 1'b1;
end
default: begin
red <= 1'b0;
yellow <= 1'b0;
green <= 1'b0;
end
endcase
end
end
endmodule
|
module dual_port_RAM #(
parameter DEPTH = 16,
parameter WIDTH = 8
)(
input wclk,
input wenc,
input [$clog2(DEPTH)-1:0] waddr,
input [WIDTH-1:0] wdata,
input rclk,
input renc,
input [$clog2(DEPTH)-1:0] raddr,
output reg [WIDTH-1:0] rdata
);
// Memory array
reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];
// Handle write operation
always @(posedge wclk) begin
if (wenc) begin
RAM_MEM[waddr] <= wdata;
end
end
// Handle read operation
always @(posedge rclk) begin
if (renc) begin
rdata <= RAM_MEM[raddr];
end
end
endmodule
|
module asyn_fifo #(
parameter WIDTH = 8,
parameter DEPTH = 16
)(
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [WIDTH-1:0] wdata,
output wfull,
output rempty,
output [WIDTH-1:0] rdata
);
// Internal signals
reg [$clog2(DEPTH):0] wptr, rptr, wptr_gray, rptr_gray;
wire [$clog2(DEPTH):0] wptr_gray_next, rptr_gray_next;
reg [$clog2(DEPTH):0] rptr_gray_sync1, rptr_gray_sync2;
reg [$clog2(DEPTH):0] wptr_gray_sync1, wptr_gray_sync2;
// Dual-port RAM instance
dual_port_RAM #(.DEPTH(DEPTH), .WIDTH(WIDTH)) RAM_inst (
.wclk(wclk),
.wenc(winc & ~wfull),
.waddr(wptr[$clog2(DEPTH)-1:0]),
.wdata(wdata),
.rclk(rclk),
.renc(rinc & ~rempty),
.raddr(rptr[$clog2(DEPTH)-1:0]),
.rdata(rdata)
);
// Generate Gray code from binary pointer
function [$clog2(DEPTH):0] bin_to_gray(input [$clog2(DEPTH):0] bin);
bin_to_gray = (bin >> 1) ^ bin;
endfunction
// Convert Gray code to binary
function [$clog2(DEPTH):0] gray_to_bin(input [$clog2(DEPTH):0] gray);
integer i;
begin
for (i = 0; i < $clog2(DEPTH); i = i + 1) begin
if (i == 0)
gray_to_bin[i] = gray[i];
else
gray_to_bin[i] = gray_to_bin[i-1] ^ gray[i];
end
end
endfunction
// Next gray code calculation
assign wptr_gray_next = bin_to_gray(wptr + winc);
assign rptr_gray_next = bin_to_gray(rptr + rinc);
// Write pointer and Gray code update
always @(posedge wclk or negedge wrstn) begin
if (!wrstn) begin
wptr <= 0;
wptr_gray <= 0;
end else if (winc && !wfull) begin
wptr <= wptr + 1;
wptr_gray <= wptr_gray_next;
end
end
// Read pointer and Gray code update
always @(posedge rclk or negedge rrstn) begin
if (!rrstn) begin
rptr <= 0;
rptr_gray <= 0;
end else if (rinc && !rempty) begin
rptr <= rptr + 1;
rptr_gray <= rptr_gray_next;
end
end
// Synchronize the read pointer to the write clock domain
always @(posedge wclk or negedge wrstn) begin
if (!wrstn) begin
rptr_gray_sync1 <= 0;
rptr_gray_sync2 <= 0;
end else begin
rptr_gray_sync1 <= rptr_gray;
rptr_gray_sync2 <= rptr_gray_sync1;
end
end
// Synchronize the write pointer to the read clock domain
always @(posedge rclk or negedge rrstn) begin
if (!rrstn) begin
wptr_gray_sync1 <= 0;
wptr_gray_sync2 <= 0;
end else begin
wptr_gray_sync1 <= wptr_gray;
wptr_gray_sync2 <= wptr_gray_sync1;
end
end
// Full flag generation
wire full_cond = (wptr_gray_next[$clog2(DEPTH)] != rptr_gray_sync2[$clog2(DEPTH)] &&
wptr_gray_next[$clog2(DEPTH)-1] != rptr_gray_sync2[$clog2(DEPTH)-1] &&
wptr_gray_next[$clog2(DEPTH)-2:0] == rptr_gray_sync2[$clog2(DEPTH)-2:0]);
assign wfull = full_cond;
// Empty flag generation
wire empty_cond = (wptr_gray_sync2 == rptr_gray);
assign rempty = empty_cond;
endmodule
|
module width_8to16(
input wire clk,
input wire rst_n,
input wire valid_in,
input wire [7:0] data_in,
output reg valid_out,
output reg [15:0] data_out
);
// Intermediate storage for the first 8-bit data
reg [7:0] data_lock;
// Flag to indicate that the first data byte has been stored and is waiting for the second byte
reg data_lock_valid;
// Synchronous process for capturing and concatenating input data
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Synchronous reset
data_out <= 16'b0;
valid_out <= 1'b0;
data_lock <= 8'b0;
data_lock_valid <= 1'b0;
end else begin
if (valid_in) begin
if (data_lock_valid) begin
// If we have valid data locked, concatenate it with new data
data_out <= {data_lock, data_in};
valid_out <= 1'b1; // Output is valid now
data_lock_valid <= 1'b0; // Clear the lock flag as data is now used
end else begin
// If no valid data is locked, lock the current input and wait for the next
data_lock <= data_in;
data_lock_valid <= 1'b1; // Set the lock flag
valid_out <= 1'b0; // Output is not valid until we get the second byte
end
end else if (!data_lock_valid) begin
// If input is not valid and no data is locked, maintain the output as invalid
valid_out <= 1'b0;
end
// No else clause for data_lock_valid and !valid_in, since we want to keep the locked data
end
end
endmodule
|
module JC_counter (
input clk,
input rst_n,
output reg [63:0] Q
);
// Johnson counter sequence update
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset condition
Q <= 64'b0; // Set all bits to 0
end else begin
// Normal operation
if (Q[0] == 1'b0) begin
// If the LSB is 0, shift left and insert 1 at MSB
Q <= {Q[62:0], 1'b1};
end else begin
// If the LSB is 1, shift left and insert 0 at MSB
Q <= {Q[62:0], 1'b0};
end
end
end
endmodule
|
module adder_pipe_64bit(
input clk, // Clock input
input rst_n, // Active low reset signal
input i_en, // Enable signal for addition operation
input [63:0] adda, // 64-bit input operand A
input [63:0] addb, // 64-bit input operand B
output reg [64:0] result, // 65-bit output representing the sum of adda and addb
output reg o_en // Output enable signal
);
// Intermediate registers for pipeline stages
reg [63:0] reg_adda_stage1, reg_addb_stage1;
reg [64:0] reg_sum_stage2;
reg reg_i_en_stage1, reg_i_en_stage2;
// Combinational logic for addition
wire [64:0] sum_stage1; // 65-bit to store sum and carry out
// First stage addition
assign sum_stage1 = reg_adda_stage1 + reg_addb_stage1;
// Sequential logic for registers
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset all registers and output enable
reg_adda_stage1 <= 0;
reg_addb_stage1 <= 0;
reg_sum_stage2 <= 0;
reg_i_en_stage1 <= 0;
reg_i_en_stage2 <= 0;
o_en <= 0;
result <= 0;
end else begin
// Pipeline stage 1
if (i_en) begin
reg_adda_stage1 <= adda; // Load inputs into pipeline stage 1
reg_addb_stage1 <= addb;
reg_i_en_stage1 <= i_en; // Enable signal for stage 1
end
// Pipeline stage 2
reg_sum_stage2 <= sum_stage1; // Output of adder goes into stage 2
reg_i_en_stage2 <= reg_i_en_stage1; // Enable signal for stage 2
// Result and output enable
result <= reg_sum_stage2; // Result is stored in output register
o_en <= reg_i_en_stage2; // Output enable signal
end
end
endmodule
|
module right_shifter(
input wire clk,
input wire d,
output reg [7:0] q
);
// Initialize the shift register to 0
initial begin
q = 8'b00000000;
end
// Perform the shift operation on the rising edge of the clock
always @(posedge clk) begin
q <= {d, q[7:1]}; // Concatenate new bit 'd' at the MSB and shift right
end
endmodule
|
module serial2parallel (
input wire clk,
input wire rst_n,
input wire din_serial,
input wire din_valid,
output reg [7:0] dout_parallel,
output reg dout_valid
);
// 4-bit counter to count the number of bits received
reg [2:0] cnt;
// On every positive edge of the clock, perform the series to parallel conversion
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// If reset is active, clear the counter and output registers
cnt <= 3'd0;
dout_parallel <= 8'd0;
dout_valid <= 1'b0;
end else if (din_valid) begin
// If the input data is valid, shift in the serial data
dout_parallel <= {din_serial, dout_parallel[7:1]};
// Increment the counter
cnt <= cnt + 1;
// If 8 bits have been received, indicate that output is valid
if (cnt == 3'd7) begin
dout_valid <= 1'b1;
cnt <= 3'd0; // reset the counter after 8 bits
end else begin
dout_valid <= 1'b0;
end
end else begin
// If din_valid is not high, do not shift in new data
// and clear the valid flag
dout_valid <= 1'b0;
end
end
endmodule
|
module multi_16bit(
input clk,
input rst_n,
input start,
input [15:0] ain,
input [15:0] bin,
output reg [31:0] yout,
output reg done
);
reg [15:0] areg, breg;
reg [4:0] i; // 5 bits to represent the count from 0 to 16
reg [31:0] yout_r;
reg done_r;
// Reset and start conditions
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset condition
areg <= 16'b0;
breg <= 16'b0;
yout_r <= 32'b0;
i <= 5'b0;
done <= 1'b0;
end else begin
if (start) begin
if (i < 17) begin
if (i == 0) begin
// Load the registers with the inputs
areg <= ain;
breg <= bin;
yout_r <= 32'b0;
end else begin
// Shift and accumulate
yout_r <= yout_r + ({16'b0, areg[0] ? breg : 16'b0} << (i - 1));
areg <= areg >> 1; // Shift the multiplicand right
end
i <= i + 1'b1;
done <= 1'b0;
end else begin
// Multiplication is done
done <= 1'b1;
i <= 5'b0; // Reset the counter for the next operation
end
end else begin
// Start is not active, reset the counter
i <= 5'b0;
done <= 1'b0;
end
end
end
// Assign the internal register to the output
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
yout <= 32'b0;
end else begin
if (done) begin
yout <= yout_r;
end
end
end
endmodule
|
module freq_div(
input wire CLK_in,
input wire RST,
output reg CLK_50,
output reg CLK_10,
output reg CLK_1
);
// Counters for the 10MHz and 1MHz clocks
reg [3:0] cnt_10 = 0; // 4-bit counter for 10MHz
reg [6:0] cnt_100 = 0; // 7-bit counter for 1MHz
// CLK_50 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_50 <= 0;
end else begin
CLK_50 <= ~CLK_50;
end
end
// CLK_10 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_10 <= 0;
cnt_10 <= 0;
end else begin
if (cnt_10 == 4'd4) begin
CLK_10 <= ~CLK_10;
cnt_10 <= 0;
end else begin
cnt_10 <= cnt_10 + 1;
end
end
end
// CLK_1 generation
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_1 <= 0;
cnt_100 <= 0;
end else begin
if (cnt_100 == 7'd49) begin
CLK_1 <= ~CLK_1;
cnt_100 <= 0;
end else begin
cnt_100 <= cnt_100 + 1;
end
end
end
endmodule
|
module counter_12 (
input wire rst_n, // Active low reset
input wire clk, // Clock signal
input wire valid_count, // Enable counting
output reg [3:0] out // 4-bit count output
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset condition
out <= 4'b0000;
end else if (valid_count) begin
if (out == 4'd11) begin
// Wrap counter back to 0 after reaching 11
out <= 4'b0000;
end else begin
// Increment counter
out <= out + 4'd1;
end
end
// If valid_count is 0, do nothing (counter is paused)
end
endmodule
|
module edge_detect(
input clk, // Clock signal
input rst_n, // Active low reset signal
input a, // Input signal for edge detection
output reg rise, // Output signal indicating a rising edge
output reg down // Output signal indicating a falling edge
);
// Register to hold the previous state of 'a'
reg a_prev;
// Edge detection logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset condition, set everything to zero
a_prev <= 1'b0;
rise <= 1'b0;
down <= 1'b0;
end else begin
// Detect rising edge
rise <= (a == 1'b1) && (a_prev == 1'b0);
// Detect falling edge
down <= (a == 1'b0) && (a_prev == 1'b1);
// Update previous state of 'a'
a_prev <= a;
end
end
endmodule
|
module full_adder (
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
// Sum is the XOR of the three inputs
assign sum = a ^ b ^ cin;
// Carry out is the majority function of the three inputs
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule
|
module multi_pipe_8bit (
input wire clk,
input wire rst_n,
input wire mul_en_in,
input wire [7:0] mul_a,
input wire [7:0] mul_b,
output reg mul_en_out,
output reg [15:0] mul_out
);
// Define internal registers
reg [7:0] reg_mul_a, reg_mul_b;
reg [15:0] reg_mul_out;
reg [7:0] partial_products[7:0];
reg [15:0] sum[6:0]; // 7 stages of addition
reg [7:0] mul_en_pipeline;
// Input register stage
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg_mul_a <= 0;
reg_mul_b <= 0;
mul_en_pipeline <= 0;
end else if (mul_en_in) begin
reg_mul_a <= mul_a;
reg_mul_b <= mul_b;
mul_en_pipeline <= {mul_en_pipeline[6:0], mul_en_in}; // Shift enable signal through the pipeline
end
end
// Generate partial products
integer i;
always @(posedge clk) begin
for (i = 0; i < 8; i = i + 1) begin
partial_products[i] <= reg_mul_a & {8{reg_mul_b[i]}};
end
end
// Addition pipeline stages
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum[0] <= 0;
sum[1] <= 0;
sum[2] <= 0;
sum[3] <= 0;
sum[4] <= 0;
sum[5] <= 0;
sum[6] <= 0;
reg_mul_out <= 0;
end else begin
// Perform the additions in a pipelined manner
sum[0] <= partial_products[0] + (partial_products[1] << 1);
sum[1] <= partial_products[2] + (partial_products[3] << 2);
sum[2] <= partial_products[4] + (partial_products[5] << 4);
sum[3] <= partial_products[6] + (partial_products[7] << 6);
sum[4] <= sum[0] + (sum[1] << 2);
sum[5] <= sum[2] + (sum[3] << 4);
sum[6] <= sum[4] + (sum[5] << 4);
reg_mul_out <= sum[6];
end
end
// Output stage
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
mul_out <= 0;
mul_en_out <= 0;
end else begin
mul_out <= reg_mul_out;
mul_en_out <= mul_en_pipeline[7];
end
end
endmodule
|
module parallel2serial(
input wire clk,
input wire rst_n,
input wire [3:0] d,
output reg valid_out,
output reg dout
);
// Internal registers
reg [3:0] data_reg;
reg [1:0] cnt; // 2-bit counter to handle 4 clock cycles for 4 bits
// On every positive edge of the clock
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Resetting all registers when rst_n is 0
data_reg <= 4'b0000;
cnt <= 2'b00;
valid_out <= 1'b0;
dout <= 1'b0;
end else begin
// If counter is 3, indicating the last bit is being outputted, load new data
if (cnt == 2'b11) begin
data_reg <= d; // Load the parallel data
cnt <= 2'b00; // Reset the counter
valid_out <= 1'b1; // Set valid_out high as data is ready to be outputted
end else begin
cnt <= cnt + 1; // Increment the counter
data_reg <= {data_reg[2:0], 1'b0}; // Shift left the data register
valid_out <= (cnt == 2'b00) ? 1'b1 : 1'b0; // valid_out high only when cnt is 0
end
dout <= data_reg[3]; // Assign MSB of data_reg to dout
end
end
endmodule
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