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module fm_3d_frcp (
clk_core,
i_en,
i_a,
o_c
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input i_en;
input [21:0] i_a; // input A
output [21:0] o_c; // result
///////////////////////////////////////////
// register definition
///////////////////////////////////////////
reg [21:0] r_c; // result
reg r_a_sign;
reg [4:0] r_ce_tmp;
reg [7:0] r_a_frac_l;
///////////////////////////////////////////
// wire
///////////////////////////////////////////
wire w_a_sign;
wire [4:0] w_a_exp;
wire [15:0] w_a_fraction;
wire [4:0] w_2bias;
wire [4:0] w_ce_tmp;
wire [15:0] w_cf_tmp;
wire [31:0] w_rom_out;
wire [15:0] w_rom_base;
wire [15:0] w_rom_diff;
wire [6:0] w_rom_address;
wire [7:0] w_a_frac_l;
//wire [31:0] w_rom_correct;
wire [23:0] w_rom_correct;
wire [21:0] w_c;
wire w_zero_flag;
///////////////////////////////////////////
// assign
///////////////////////////////////////////
assign w_a_sign = i_a[21];
assign w_a_exp = i_a[20:16];
assign w_a_fraction = i_a[15:0];
assign w_2bias = 5'h1e; // x2
assign w_ce_tmp = w_2bias - w_a_exp;
assign w_rom_address = w_a_fraction[14:8];
assign w_a_frac_l = w_a_fraction[7:0];
/* // original implementation
assign w_rom_base = w_rom_out[31:16]; // 1.15
assign w_rom_diff = w_rom_out[15:0]; // 0.16
assign w_rom_correct = w_rom_diff * {r_a_frac_l,8'b0};
assign w_cf_tmp = w_rom_base - {1'b0,w_rom_correct[31:17]};
*/
// timing improvement
assign w_rom_base = w_rom_out[31:16]; // 1.15
assign w_rom_diff = w_rom_out[15:0]; // 0.16
assign w_rom_correct = w_rom_diff * r_a_frac_l;
assign w_cf_tmp = w_rom_base - {1'b0,w_rom_correct[23:9]};
assign w_zero_flag = (w_a_exp == 5'h0);
// output port
assign o_c = r_c;
///////////////////////////////////////////
// always statement
///////////////////////////////////////////
always @(posedge clk_core) begin
if (i_en) begin
r_a_sign <= w_a_sign;
r_ce_tmp <= w_ce_tmp;
r_a_frac_l <= w_a_frac_l;
end
end
always @(posedge clk_core) begin
if (i_en) begin
r_c <= (w_zero_flag) ? 16'h0 : w_c;
end
end
///////////////////////////////////////////
// module instance
///////////////////////////////////////////
// table rom
fm_3d_frcp_rom frcp_rom (
.clk_core(clk_core),
.i_a(w_rom_address),
.o_c(w_rom_out)
);
// normalize
fm_3d_norm norm (
.i_s(r_a_sign),
.i_e(r_ce_tmp),
.i_f({1'b0,w_cf_tmp[15:0]}),
.o_b(w_c)
);
endmodule
|
module fm_3d_ru_outline_edge (
clk_core,
rst_x,
// outline parameters
i_ml,
i_is_first,
i_is_second,
i_valid,
i_aa_mode,
// idle state indicator
o_idle,
// edge0
i_start_x_e0,
i_start_x_05_e0,
i_start_y_e0,
i_end_y_e0,
i_delta_e0,
i_delta_t_e0,
i_delta_a_e0,
// edge1
i_start_x_e1,
i_start_x_05_e1,
i_start_y_e1,
i_end_y_e1,
i_delta_e1,
i_delta_t_e1,
i_delta_a_e1,
// edge2
i_start_x_e2,
i_start_x_05_e2,
i_start_y_e2,
i_end_y_e2,
i_delta_e2,
i_delta_t_e2,
i_delta_a_e2,
o_ack,
// triangle data
i_vtx0_z,
i_vtx0_iw,
i_vtx0_p00,
i_vtx0_p01,
i_vtx0_p02,
i_vtx0_p03,
i_vtx0_p10,
i_vtx0_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx0_p12,
i_vtx0_p13,
`endif
i_vtx1_z,
i_vtx1_iw,
i_vtx1_p00,
i_vtx1_p01,
i_vtx1_p02,
i_vtx1_p03,
i_vtx1_p10,
i_vtx1_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx1_p12,
i_vtx1_p13,
`endif
i_vtx2_z,
i_vtx2_iw,
i_vtx2_p00,
i_vtx2_p01,
i_vtx2_p02,
i_vtx2_p03,
i_vtx2_p10,
i_vtx2_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx2_p12,
i_vtx2_p13,
`endif
// control registers
i_param0_en,
i_param1_en,
i_param0_size,
i_param1_size,
// output left
o_valid_l,
i_busy_l,
o_x_l,
o_y_l,
o_z_l,
o_iw_l,
o_param00_l,
o_param01_l,
o_param02_l,
o_param03_l,
o_param10_l,
o_param11_l,
`ifdef VTX_PARAM1_REDUCE
`else
o_param12_l,
o_param13_l,
`endif
// output right
o_valid_r,
i_busy_r,
o_x_r,
o_y_r,
o_z_r,
o_iw_r,
o_param00_r,
o_param01_r,
o_param02_r,
o_param03_r,
o_param10_r,
o_param11_r
`ifdef VTX_PARAM1_REDUCE
`else
,o_param12_r,
o_param13_r
`endif
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// outline parameters
input i_ml;
input i_is_first;
input i_is_second;
input i_valid;
input i_aa_mode;
// idle state indicator
output o_idle;
// edge0
input [20:0] i_start_x_e0;
input [20:0] i_start_x_05_e0;
input [20:0] i_start_y_e0;
input [20:0] i_end_y_e0;
input [21:0] i_delta_e0;
input [21:0] i_delta_t_e0;
input [21:0] i_delta_a_e0;
// edge1
input [20:0] i_start_x_e1;
input [20:0] i_start_x_05_e1;
input [20:0] i_start_y_e1;
input [20:0] i_end_y_e1;
input [21:0] i_delta_e1;
input [21:0] i_delta_t_e1;
input [21:0] i_delta_a_e1;
// edge2
input [20:0] i_start_x_e2;
input [20:0] i_start_x_05_e2;
input [20:0] i_start_y_e2;
input [20:0] i_end_y_e2;
input [21:0] i_delta_e2;
input [21:0] i_delta_t_e2;
input [21:0] i_delta_a_e2;
output o_ack;
// triangle data
input [20:0] i_vtx0_z;
input [20:0] i_vtx0_iw;
input [20:0] i_vtx0_p00;
input [20:0] i_vtx0_p01;
input [20:0] i_vtx0_p02;
input [20:0] i_vtx0_p03;
input [20:0] i_vtx0_p10;
input [20:0] i_vtx0_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx0_p12;
input [20:0] i_vtx0_p13;
`endif
input [20:0] i_vtx1_z;
input [20:0] i_vtx1_iw;
input [20:0] i_vtx1_p00;
input [20:0] i_vtx1_p01;
input [20:0] i_vtx1_p02;
input [20:0] i_vtx1_p03;
input [20:0] i_vtx1_p10;
input [20:0] i_vtx1_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx1_p12;
input [20:0] i_vtx1_p13;
`endif
input [20:0] i_vtx2_z;
input [20:0] i_vtx2_iw;
input [20:0] i_vtx2_p00;
input [20:0] i_vtx2_p01;
input [20:0] i_vtx2_p02;
input [20:0] i_vtx2_p03;
input [20:0] i_vtx2_p10;
input [20:0] i_vtx2_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx2_p12;
input [20:0] i_vtx2_p13;
`endif
// control registers
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
// output left
output o_valid_l;
input i_busy_l;
output [20:0] o_x_l;
output [8:0] o_y_l;
output [20:0] o_z_l;
output [20:0] o_iw_l;
output [20:0] o_param00_l;
output [20:0] o_param01_l;
output [20:0] o_param02_l;
output [20:0] o_param03_l;
output [20:0] o_param10_l;
output [20:0] o_param11_l;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_param12_l;
output [20:0] o_param13_l;
`endif
// output right
output o_valid_r;
input i_busy_r;
output [20:0] o_x_r;
output [8:0] o_y_r;
output [20:0] o_z_r;
output [20:0] o_iw_r;
output [20:0] o_param00_r;
output [20:0] o_param01_r;
output [20:0] o_param02_r;
output [20:0] o_param03_r;
output [20:0] o_param10_r;
output [20:0] o_param11_r;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_param12_r;
output [20:0] o_param13_r;
`endif
////////////////////////////
// wire
////////////////////////////
wire w_valid_l;
wire [20:0] w_start_x_l;
wire [20:0] w_start_x_05_l;
wire [20:0] w_start_y_l;
wire [20:0] w_end_y_l;
wire [21:0] w_delta_x_l;
wire [21:0] w_delta_t_l;
wire [21:0] w_delta_a_l;
wire [20:0] w_z_s_l;
wire [20:0] w_iw_s_l;
wire [20:0] w_p00_s_l;
wire [20:0] w_p01_s_l;
wire [20:0] w_p02_s_l;
wire [20:0] w_p03_s_l;
wire [20:0] w_p10_s_l;
wire [20:0] w_p11_s_l;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_p12_s_l;
wire [20:0] w_p13_s_l;
`endif
wire [20:0] w_z_e_l;
wire [20:0] w_iw_e_l;
wire [20:0] w_p00_e_l;
wire [20:0] w_p01_e_l;
wire [20:0] w_p02_e_l;
wire [20:0] w_p03_e_l;
wire [20:0] w_p10_e_l;
wire [20:0] w_p11_e_l;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_p12_e_l;
wire [20:0] w_p13_e_l;
`endif
wire w_valid_r;
wire [20:0] w_start_x_r;
wire [20:0] w_start_x_05_r;
wire [20:0] w_start_y_r;
wire [20:0] w_end_y_r;
wire [21:0] w_delta_x_r;
wire [21:0] w_delta_t_r;
wire [21:0] w_delta_a_r;
wire [20:0] w_z_s_r;
wire [20:0] w_iw_s_r;
wire [20:0] w_p00_s_r;
wire [20:0] w_p01_s_r;
wire [20:0] w_p02_s_r;
wire [20:0] w_p03_s_r;
wire [20:0] w_p10_s_r;
wire [20:0] w_p11_s_r;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_p12_s_r;
wire [20:0] w_p13_s_r;
`endif
wire [20:0] w_z_e_r;
wire [20:0] w_iw_e_r;
wire [20:0] w_p00_e_r;
wire [20:0] w_p01_e_r;
wire [20:0] w_p02_e_r;
wire [20:0] w_p03_e_r;
wire [20:0] w_p10_e_r;
wire [20:0] w_p11_e_r;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_p12_e_r;
wire [20:0] w_p13_e_r;
`endif
wire w_ack_l;
wire w_ack_r;
wire w_has_bottom;
wire w_idle_ctrl;
wire w_idle_edge_l;
wire w_idle_edge_r;
/////////////////////////
// assign statement
/////////////////////////
assign o_idle = w_idle_ctrl & w_idle_edge_l * w_idle_edge_r;
////////////////////////////
// module instance
////////////////////////////
// edge select control
fm_3d_ru_outline_edge_ctrl edge_ctrl (
.clk_core(clk_core),
.rst_x(rst_x),
// outline parameters
.i_valid(i_valid),
.i_ml(i_ml),
.i_is_first(i_is_first),
.i_is_second(i_is_second),
// idle state indicator
.o_idle(w_idle_ctrl),
// edge0
.i_start_x_e0(i_start_x_e0),
.i_start_x_05_e0(i_start_x_05_e0),
.i_start_y_e0(i_start_y_e0),
.i_end_y_e0(i_end_y_e0),
.i_delta_e0(i_delta_e0),
.i_delta_t_e0(i_delta_t_e0),
.i_delta_a_e0(i_delta_a_e0),
// edge1
.i_start_x_e1(i_start_x_e1),
.i_start_x_05_e1(i_start_x_05_e1),
.i_start_y_e1(i_start_y_e1),
.i_end_y_e1(i_end_y_e1),
.i_delta_e1(i_delta_e1),
.i_delta_t_e1(i_delta_t_e1),
.i_delta_a_e1(i_delta_a_e1),
// edge2
.i_start_x_e2(i_start_x_e2),
.i_start_x_05_e2(i_start_x_05_e2),
.i_start_y_e2(i_start_y_e2),
.i_end_y_e2(i_end_y_e2),
.i_delta_e2(i_delta_e2),
.i_delta_t_e2(i_delta_t_e2),
.i_delta_a_e2(i_delta_a_e2),
.o_ack(o_ack),
// triangle data
.i_vtx0_z(i_vtx0_z),
.i_vtx0_iw(i_vtx0_iw),
.i_vtx0_p00(i_vtx0_p00),
.i_vtx0_p01(i_vtx0_p01),
.i_vtx0_p02(i_vtx0_p02),
.i_vtx0_p03(i_vtx0_p03),
.i_vtx0_p10(i_vtx0_p10),
.i_vtx0_p11(i_vtx0_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx0_p12(i_vtx0_p12),
.i_vtx0_p13(i_vtx0_p13),
`endif
.i_vtx1_z(i_vtx1_z),
.i_vtx1_iw(i_vtx1_iw),
.i_vtx1_p00(i_vtx1_p00),
.i_vtx1_p01(i_vtx1_p01),
.i_vtx1_p02(i_vtx1_p02),
.i_vtx1_p03(i_vtx1_p03),
.i_vtx1_p10(i_vtx1_p10),
.i_vtx1_p11(i_vtx1_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx1_p12(i_vtx1_p12),
.i_vtx1_p13(i_vtx1_p13),
`endif
.i_vtx2_z(i_vtx2_z),
.i_vtx2_iw(i_vtx2_iw),
.i_vtx2_p00(i_vtx2_p00),
.i_vtx2_p01(i_vtx2_p01),
.i_vtx2_p02(i_vtx2_p02),
.i_vtx2_p03(i_vtx2_p03),
.i_vtx2_p10(i_vtx2_p10),
.i_vtx2_p11(i_vtx2_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx2_p12(i_vtx2_p12),
.i_vtx2_p13(i_vtx2_p13),
`endif
// control flag
.o_has_bottom(w_has_bottom),
// left edge data out
.o_valid_l(w_valid_l),
.o_start_x_l(w_start_x_l),
.o_start_x_05_l(w_start_x_05_l),
.o_start_y_l(w_start_y_l),
.o_end_y_l(w_end_y_l),
.o_delta_l(w_delta_x_l),
.o_delta_t_l(w_delta_t_l),
.o_delta_a_l(w_delta_a_l),
.i_ack_l(w_ack_l),
// left vertex parameters
.o_z_s_l(w_z_s_l),
.o_iw_s_l(w_iw_s_l),
.o_p00_s_l(w_p00_s_l),
.o_p01_s_l(w_p01_s_l),
.o_p02_s_l(w_p02_s_l),
.o_p03_s_l(w_p03_s_l),
.o_p10_s_l(w_p10_s_l),
.o_p11_s_l(w_p11_s_l),
`ifdef VTX_PARAM1_REDUCE
`else
.o_p12_s_l(w_p12_s_l),
.o_p13_s_l(w_p13_s_l),
`endif
.o_z_e_l(w_z_e_l),
.o_iw_e_l(w_iw_e_l),
.o_p00_e_l(w_p00_e_l),
.o_p01_e_l(w_p01_e_l),
.o_p02_e_l(w_p02_e_l),
.o_p03_e_l(w_p03_e_l),
.o_p10_e_l(w_p10_e_l),
.o_p11_e_l(w_p11_e_l),
`ifdef VTX_PARAM1_REDUCE
`else
.o_p12_e_l(w_p12_e_l),
.o_p13_e_l(w_p13_e_l),
`endif
// right edge data out
.o_valid_r(w_valid_r),
.o_start_x_r(w_start_x_r),
.o_start_x_05_r(w_start_x_05_r),
.o_start_y_r(w_start_y_r),
.o_end_y_r(w_end_y_r),
.o_delta_r(w_delta_x_r),
.o_delta_t_r(w_delta_t_r),
.o_delta_a_r(w_delta_a_r),
.i_ack_r(w_ack_r),
// right vertex parameters
.o_z_s_r(w_z_s_r),
.o_iw_s_r(w_iw_s_r),
.o_p00_s_r(w_p00_s_r),
.o_p01_s_r(w_p01_s_r),
.o_p02_s_r(w_p02_s_r),
.o_p03_s_r(w_p03_s_r),
.o_p10_s_r(w_p10_s_r),
.o_p11_s_r(w_p11_s_r),
`ifdef VTX_PARAM1_REDUCE
`else
.o_p12_s_r(w_p12_s_r),
.o_p13_s_r(w_p13_s_r),
`endif
.o_z_e_r(w_z_e_r),
.o_iw_e_r(w_iw_e_r),
.o_p00_e_r(w_p00_e_r),
.o_p01_e_r(w_p01_e_r),
.o_p02_e_r(w_p02_e_r),
.o_p03_e_r(w_p03_e_r),
.o_p10_e_r(w_p10_e_r),
.o_p11_e_r(w_p11_e_r)
`ifdef VTX_PARAM1_REDUCE
`else
,.o_p12_e_r(w_p12_e_r),
.o_p13_e_r(w_p13_e_r)
`endif
);
// left edge
fm_3d_ru_outline_edge_core edge_left (
.clk_core(clk_core),
.rst_x(rst_x),
// idle state indicator
.o_idle(w_idle_edge_l),
// outline parameters
.i_valid(w_valid_l),
.i_has_bottom(w_has_bottom),
.i_start_x(w_start_x_l),
.i_start_x_05(w_start_x_05_l),
.i_start_y(w_start_y_l),
.i_end_y(w_end_y_l),
.i_delta_x(w_delta_x_l),
.i_delta_t(w_delta_t_l),
.i_delta_a(w_delta_a_l),
.o_ack(w_ack_l),
// vertex parameters
.i_z_s(w_z_s_l),
.i_iw_s(w_iw_s_l),
.i_param00_s(w_p00_s_l),
.i_param01_s(w_p01_s_l),
.i_param02_s(w_p02_s_l),
.i_param03_s(w_p03_s_l),
.i_param10_s(w_p10_s_l),
.i_param11_s(w_p11_s_l),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_s(w_p12_s_l),
.i_param13_s(w_p13_s_l),
`endif
.i_z_e(w_z_e_l),
.i_iw_e(w_iw_e_l),
.i_param00_e(w_p00_e_l),
.i_param01_e(w_p01_e_l),
.i_param02_e(w_p02_e_l),
.i_param03_e(w_p03_e_l),
.i_param10_e(w_p10_e_l),
.i_param11_e(w_p11_e_l),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_e(w_p12_e_l),
.i_param13_e(w_p13_e_l),
`endif
// control registers
.i_aa_mode(i_aa_mode),
.i_param0_en(i_param0_en),
.i_param1_en(i_param1_en),
.i_param0_size(i_param0_size),
.i_param1_size(i_param1_size),
// output
.o_valid(o_valid_l),
.i_busy(i_busy_l),
.o_x(o_x_l),
.o_y(o_y_l),
.o_z(o_z_l),
.o_iw(o_iw_l),
.o_param00(o_param00_l),
.o_param01(o_param01_l),
.o_param02(o_param02_l),
.o_param03(o_param03_l),
.o_param10(o_param10_l),
.o_param11(o_param11_l)
`ifdef VTX_PARAM1_REDUCE
`else
,.o_param12(o_param12_l),
.o_param13(o_param13_l)
`endif
);
// right edge
fm_3d_ru_outline_edge_core edge_right (
.clk_core(clk_core),
.rst_x(rst_x),
// idle state indicator
.o_idle(w_idle_edge_r),
// outline parameters
.i_valid(w_valid_r),
.i_has_bottom(w_has_bottom),
.i_start_x(w_start_x_r),
.i_start_x_05(w_start_x_05_r),
.i_start_y(w_start_y_r),
.i_end_y(w_end_y_r),
.i_delta_x(w_delta_x_r),
.i_delta_t(w_delta_t_r),
.i_delta_a(w_delta_a_r),
.o_ack(w_ack_r),
// vertex parameters
.i_z_s(w_z_s_r),
.i_iw_s(w_iw_s_r),
.i_param00_s(w_p00_s_r),
.i_param01_s(w_p01_s_r),
.i_param02_s(w_p02_s_r),
.i_param03_s(w_p03_s_r),
.i_param10_s(w_p10_s_r),
.i_param11_s(w_p11_s_r),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_s(w_p12_s_r),
.i_param13_s(w_p13_s_r),
`endif
.i_z_e(w_z_e_r),
.i_iw_e(w_iw_e_r),
.i_param00_e(w_p00_e_r),
.i_param01_e(w_p01_e_r),
.i_param02_e(w_p02_e_r),
.i_param03_e(w_p03_e_r),
.i_param10_e(w_p10_e_r),
.i_param11_e(w_p11_e_r),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_e(w_p12_e_r),
.i_param13_e(w_p13_e_r),
`endif
// control registers
.i_aa_mode(i_aa_mode),
.i_param0_en(i_param0_en),
.i_param1_en(i_param1_en),
.i_param0_size(i_param0_size),
.i_param1_size(i_param1_size),
// output
.o_valid(o_valid_r),
.i_busy(i_busy_r),
.o_x(o_x_r),
.o_y(o_y_r),
.o_z(o_z_r),
.o_iw(o_iw_r),
.o_param00(o_param00_r),
.o_param01(o_param01_r),
.o_param02(o_param02_r),
.o_param03(o_param03_r),
.o_param10(o_param10_r),
.o_param11(o_param11_r)
`ifdef VTX_PARAM1_REDUCE
`else
,.o_param12(o_param12_r),
.o_param13(o_param13_r)
`endif
);
endmodule
|
module fm_sys (
clk_core,
rst_x,
// internal interface
i_req,
i_wr,
i_adrs,
o_ack,
i_be,
i_wd,
o_rstr,
o_rd,
// configuration output
// Video controller
o_video_start,
o_aa_en,
o_fb0_offset,
o_fb0_ms_offset,
o_fb1_offset,
o_fb1_ms_offset,
o_color_mode,
o_front_buffer,
o_fb_blend_en,
// status from Video controller
i_vint_x,
i_vint_edge,
// status from 3D core
i_vtx_int,
// int out to sh4
o_int_x,
`ifdef PSOC_IN
i_psoc,
`endif
// DMA
o_dma_start,
o_dma_mode,
i_dma_end,
o_dma_top_address0,
o_dma_top_address1,
o_dma_top_address2,
o_dma_top_address3,
o_dma_length,
o_dma_be,
o_dma_wd0,
o_dma_wd1,
// AXI Configuration
o_conf_arcache_m,
o_conf_aruser_m,
o_conf_awcache_m,
o_conf_awuser_m
`ifdef USE_AXI_MONITOR
// result out
,
o_stop_trigger,
i_bukets_no_wait_aw,
i_bukets_0_aw,
i_bukets_1_aw,
i_bukets_2_aw,
i_bukets_3_aw,
i_bukets_more_aw,
i_max_count_aw,
i_min_count_aw,
i_bukets_len_0_aw,
i_bukets_len_1_aw,
i_bukets_len_2_aw,
i_bukets_len_3_aw,
i_total_bytes_w,
i_cont_w,
i_discont_w,
i_bukets_nrdy_0_w,
i_bukets_nrdy_1_w,
i_bukets_nrdy_2_w,
i_bukets_nrdy_3_w,
i_bukets_no_wait_ar,
i_bukets_0_ar,
i_bukets_1_ar,
i_bukets_2_ar,
i_bukets_3_ar,
i_bukets_more_ar,
i_max_count_ar,
i_min_count_ar,
i_bukets_len_0_ar,
i_bukets_len_1_ar,
i_bukets_len_2_ar,
i_bukets_len_3_ar,
i_cont_ar,
i_discont_ar,
i_bukets_no_wait_b,
i_bukets_0_b,
i_bukets_1_b,
i_bukets_2_b,
i_bukets_3_b,
i_bukets_more_b,
i_num_of_cmd_b,
i_num_of_b,
i_bukets_no_wait_r,
i_bukets_0_r,
i_bukets_1_r,
i_bukets_2_r,
i_bukets_3_r,
i_bukets_more_r,
i_total_bytes_r,
i_rd_cont,
i_rd_discont,
i_bukets_nrdy_0_r,
i_bukets_nrdy_1_r,
i_bukets_nrdy_2_r,
i_bukets_nrdy_3_r
`endif
);
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
// internal interface
input i_req;
input i_wr;
input [21:0] i_adrs;
output o_ack;
input [3:0] i_be;
input [31:0] i_wd;
output o_rstr;
output [31:0] o_rd;
// configuration output
// Video controller
output [1:0] o_video_start;
output [2:0] o_aa_en;
output [11:0] o_fb0_offset;
output [11:0] o_fb0_ms_offset;
output [11:0] o_fb1_offset;
output [11:0] o_fb1_ms_offset;
output [1:0] o_color_mode;
output o_front_buffer;
output o_fb_blend_en;
// status from Video controller
input i_vint_x;
input i_vint_edge;
// status from 3D core
input i_vtx_int;
// int out to sh4
output o_int_x;
`ifdef PSOC_IN
input [1:0] i_psoc;
`endif
// DMA
output o_dma_start;
output [3:0] o_dma_mode;
input i_dma_end;
output [19:0] o_dma_top_address0;
output [19:0] o_dma_top_address1;
output [19:0] o_dma_top_address2;
output [19:0] o_dma_top_address3;
output [17:0] o_dma_length;
output [3:0] o_dma_be;
output [31:0] o_dma_wd0;
output [31:0] o_dma_wd1;
// AXI Configuration
output [3:0] o_conf_arcache_m;
output [4:0] o_conf_aruser_m;
output [3:0] o_conf_awcache_m;
output [4:0] o_conf_awuser_m;
`ifdef USE_AXI_MONITOR
localparam P_BUCKET_SIZE = 'd32;
output o_stop_trigger;
// result out
input [P_BUCKET_SIZE-1:0] i_bukets_no_wait_aw;
input [P_BUCKET_SIZE-1:0] i_bukets_0_aw;
input [P_BUCKET_SIZE-1:0] i_bukets_1_aw;
input [P_BUCKET_SIZE-1:0] i_bukets_2_aw;
input [P_BUCKET_SIZE-1:0] i_bukets_3_aw;
input [P_BUCKET_SIZE-1:0] i_bukets_more_aw;
input [P_BUCKET_SIZE-1:0] i_max_count_aw;
input [P_BUCKET_SIZE-1:0] i_min_count_aw;
input [P_BUCKET_SIZE-1:0] i_bukets_len_0_aw;
input [P_BUCKET_SIZE-1:0] i_bukets_len_1_aw;
input [P_BUCKET_SIZE-1:0] i_bukets_len_2_aw;
input [P_BUCKET_SIZE-1:0] i_bukets_len_3_aw;
input [P_BUCKET_SIZE-1:0] i_total_bytes_w;
input [P_BUCKET_SIZE-1:0] i_cont_w;
input [P_BUCKET_SIZE-1:0] i_discont_w;
input [P_BUCKET_SIZE-1:0] i_bukets_nrdy_0_w;
input [P_BUCKET_SIZE-1:0] i_bukets_nrdy_1_w;
input [P_BUCKET_SIZE-1:0] i_bukets_nrdy_2_w;
input [P_BUCKET_SIZE-1:0] i_bukets_nrdy_3_w;
input [P_BUCKET_SIZE-1:0] i_bukets_no_wait_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_0_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_1_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_2_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_3_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_more_ar;
input [P_BUCKET_SIZE-1:0] i_max_count_ar;
input [P_BUCKET_SIZE-1:0] i_min_count_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_len_0_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_len_1_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_len_2_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_len_3_ar;
input [P_BUCKET_SIZE-1:0] i_cont_ar;
input [P_BUCKET_SIZE-1:0] i_discont_ar;
input [P_BUCKET_SIZE-1:0] i_bukets_no_wait_b;
input [P_BUCKET_SIZE-1:0] i_bukets_0_b;
input [P_BUCKET_SIZE-1:0] i_bukets_1_b;
input [P_BUCKET_SIZE-1:0] i_bukets_2_b;
input [P_BUCKET_SIZE-1:0] i_bukets_3_b;
input [P_BUCKET_SIZE-1:0] i_bukets_more_b;
input [P_BUCKET_SIZE-1:0] i_num_of_cmd_b;
input [P_BUCKET_SIZE-1:0] i_num_of_b;
input [P_BUCKET_SIZE-1:0] i_bukets_no_wait_r;
input [P_BUCKET_SIZE-1:0] i_bukets_0_r;
input [P_BUCKET_SIZE-1:0] i_bukets_1_r;
input [P_BUCKET_SIZE-1:0] i_bukets_2_r;
input [P_BUCKET_SIZE-1:0] i_bukets_3_r;
input [P_BUCKET_SIZE-1:0] i_bukets_more_r;
input [P_BUCKET_SIZE-1:0] i_total_bytes_r;
input [P_BUCKET_SIZE-1:0] i_rd_cont;
input [P_BUCKET_SIZE-1:0] i_rd_discont;
input [P_BUCKET_SIZE-1:0] i_bukets_nrdy_0_r;
input [P_BUCKET_SIZE-1:0] i_bukets_nrdy_1_r;
input [P_BUCKET_SIZE-1:0] i_bukets_nrdy_2_r;
input [P_BUCKET_SIZE-1:0] i_bukets_nrdy_3_r;
`endif
//////////////////////////////////
// regs
//////////////////////////////////
reg [1:0] r_video_start;
reg [2:0] r_aa_en;
reg [11:0] r_fb0_offset;
reg [11:0] r_fb0_ms_offset;
reg [11:0] r_fb1_offset;
reg [11:0] r_fb1_ms_offset;
reg [1:0] r_color_mode;
reg r_fb_blend_en;
reg r_rstr;
reg [31:0] r_rd;
reg r_vint_x;
reg [2:0] r_mask;
reg r_front_buffer;
reg r_dma_start;
reg [3:0] r_dma_mode;
reg r_dma_int;
reg [19:0] r_dma_top_address0;
reg [19:0] r_dma_top_address1;
reg [19:0] r_dma_top_address2;
reg [19:0] r_dma_top_address3;
reg [17:0] r_dma_length;
reg [3:0] r_dma_be;
reg [31:0] r_dma_wd0;
reg [31:0] r_dma_wd1;
reg r_vint_clear;
reg [3:0] r_conf_arcache_m;
reg [4:0] r_conf_aruser_m;
reg [3:0] r_conf_awcache_m;
reg [4:0] r_conf_awuser_m;
`ifdef USE_AXI_MONITOR
reg r_stop_trigger;
reg r_rw_select;
`endif
//////////////////////////////////
// wire
//////////////////////////////////
wire w_hit0;
wire w_hit1;
wire w_hit2;
wire w_hit3;
wire w_hit4;
wire w_hit5;
wire w_hit8;
wire w_hit9;
wire w_hitA;
wire w_hitB;
wire w_hitC;
wire w_hitD;
wire w_hitE;
wire w_hitF;
wire w_hit10;
wire w_hit11;
wire w_hit12;
wire w_hit13;
wire w_hit14;
wire w_hit15;
wire w_hit16;
wire w_hit0_w;
wire w_hit1_w;
wire w_hit2_w;
wire w_hit3_w;
wire w_hit4_w;
wire w_hit5_w;
wire w_hit6_w;
wire w_hit9_w;
wire w_hitA_w;
wire w_hitB_w;
wire w_hitC_w;
wire w_hitD_w;
wire w_hitE_w;
wire w_hitF_w;
wire w_hit10_w;
wire w_hit11_w;
wire w_hit12_w;
wire w_hit13_w;
`ifdef USE_AXI_MONITOR
wire w_hit16_w;
`endif
wire [31:0] w_rd;
wire w_rstr;
wire w_vint_x;
wire w_vint_on;
wire [2:0] w_int;
`ifdef USE_AXI_MONITOR
wire w_hit32;
wire w_hit33;
wire w_hit34;
wire w_hit35;
wire w_hit36;
wire w_hit37;
wire w_hit38;
wire w_hit39;
wire w_hit40;
wire w_hit41;
wire w_hit42;
wire w_hit43;
wire w_hit44;
wire w_hit45;
wire w_hit46;
wire w_hit47;
wire w_hit48;
wire w_hit49;
wire w_hit50;
wire w_hit51;
wire w_hit52;
wire w_hit53;
wire w_hit54;
wire w_hit55;
wire w_hit56;
wire w_hit57;
wire w_hit58;
wire w_hit59;
wire w_hit60;
wire w_hit61;
wire w_hit62;
wire w_hit63;
wire w_hit64;
wire w_hit65;
wire w_hit66;
wire w_hit67;
wire w_hit68;
wire w_hit69;
wire [31:0] w_hit32_dat;
wire [31:0] w_hit33_dat;
wire [31:0] w_hit34_dat;
wire [31:0] w_hit35_dat;
wire [31:0] w_hit36_dat;
wire [31:0] w_hit37_dat;
wire [31:0] w_hit38_dat;
wire [31:0] w_hit39_dat;
wire [31:0] w_hit40_dat;
wire [31:0] w_hit41_dat;
wire [31:0] w_hit42_dat;
wire [31:0] w_hit43_dat;
wire [31:0] w_hit44_dat;
wire [31:0] w_hit45_dat;
wire [31:0] w_hit46_dat;
wire [31:0] w_hit47_dat;
wire [31:0] w_hit48_dat;
wire [31:0] w_hit49_dat;
wire [31:0] w_hit50_dat;
wire [31:0] w_hit51_dat;
wire [31:0] w_hit52_dat;
wire [31:0] w_hit53_dat;
wire [31:0] w_hit54_dat;
wire [31:0] w_hit55_dat;
wire [31:0] w_hit56_dat;
wire [31:0] w_hit57_dat;
wire [31:0] w_hit58_dat;
wire [31:0] w_hit59_dat;
wire [31:0] w_hit60_dat;
`endif
//////////////////////////////////
// assign
//////////////////////////////////
assign w_hit0 = (i_adrs[7:2] == 6'h00); // 0
assign w_hit1 = (i_adrs[7:2] == 6'h01); // 4
assign w_hit2 = (i_adrs[7:2] == 6'h02); // 8
assign w_hit3 = (i_adrs[7:2] == 6'h03); // c
assign w_hit4 = (i_adrs[7:2] == 6'h04); // 10
assign w_hit5 = (i_adrs[7:2] == 6'h05); // 14
assign w_hit6 = (i_adrs[7:2] == 6'h06); // 18
assign w_hit8 = (i_adrs[7:2] == 6'h08); // 20
assign w_hit9 = (i_adrs[7:2] == 6'h09); // 24
assign w_hitA = (i_adrs[7:2] == 6'h0a); // 28
assign w_hitB = (i_adrs[7:2] == 6'h0b); // 2c
assign w_hitC = (i_adrs[7:2] == 6'h0c); // 30
assign w_hitD = (i_adrs[7:2] == 6'h0d); // 34
assign w_hitE = (i_adrs[7:2] == 6'h0e); // 38
assign w_hitF = (i_adrs[7:2] == 6'h0f); // 3c
assign w_hit10 = (i_adrs[7:2] == 6'h10); // 40
assign w_hit11 = (i_adrs[7:2] == 6'h11); // 44
assign w_hit12 = (i_adrs[7:2] == 6'h12); // 48
assign w_hit13 = (i_adrs[7:2] == 6'h13); // 4c
assign w_hit14 = (i_adrs[7:2] == 6'h14); // 50
assign w_hit15 = (i_adrs[7:2] == 6'h15); // 54
`ifdef USE_AXI_MONITOR
assign w_hit16 = (i_adrs[7:2] == 6'h16); // 58
assign w_hit32 = (i_adrs[7:2] == 6'h20); // 80
assign w_hit33 = (i_adrs[7:2] == 6'h21); // 84
assign w_hit34 = (i_adrs[7:2] == 6'h22); // 88
assign w_hit35 = (i_adrs[7:2] == 6'h23); // 8c
assign w_hit36 = (i_adrs[7:2] == 6'h24); // 90
assign w_hit37 = (i_adrs[7:2] == 6'h25); // 94
assign w_hit38 = (i_adrs[7:2] == 6'h26); // 98
assign w_hit39 = (i_adrs[7:2] == 6'h27); // 9c
assign w_hit40 = (i_adrs[7:2] == 6'h28); // a0
assign w_hit41 = (i_adrs[7:2] == 6'h29); // a4
assign w_hit42 = (i_adrs[7:2] == 6'h2a); // a8
assign w_hit43 = (i_adrs[7:2] == 6'h2b); // ac
assign w_hit44 = (i_adrs[7:2] == 6'h2c); // b0
assign w_hit45 = (i_adrs[7:2] == 6'h2d); // b4
assign w_hit46 = (i_adrs[7:2] == 6'h2e); // b8
assign w_hit47 = (i_adrs[7:2] == 6'h2f); // bc
assign w_hit48 = (i_adrs[7:2] == 6'h30); // c0
assign w_hit49 = (i_adrs[7:2] == 6'h31); // c4
assign w_hit50 = (i_adrs[7:2] == 6'h32); // c8
assign w_hit51 = (i_adrs[7:2] == 6'h33); // cc
assign w_hit52 = (i_adrs[7:2] == 6'h34); // d0
assign w_hit53 = (i_adrs[7:2] == 6'h35); // d4
assign w_hit54 = (i_adrs[7:2] == 6'h36); // d8
assign w_hit55 = (i_adrs[7:2] == 6'h37); // dc
assign w_hit56 = (i_adrs[7:2] == 6'h38); // e0
assign w_hit57 = (i_adrs[7:2] == 6'h39); // e4
assign w_hit58 = (i_adrs[7:2] == 6'h3a); // e8
assign w_hit59 = (i_adrs[7:2] == 6'h3b); // ec
assign w_hit60 = (i_adrs[7:2] == 6'h3c); // f0
assign w_hit61 = (i_adrs[7:2] == 6'h3d); // f4
assign w_hit62 = (i_adrs[7:2] == 6'h3e); // f8
assign w_hit63 = (i_adrs[7:2] == 6'h3f); // fc
`endif
assign w_hit0_w = w_hit0 & i_wr & i_req;
assign w_hit1_w = w_hit1 & i_wr & i_req;
assign w_hit2_w = w_hit2 & i_wr & i_req;
assign w_hit3_w = w_hit3 & i_wr & i_req;
assign w_hit4_w = w_hit4 & i_wr & i_req;
assign w_hit5_w = w_hit5 & i_wr & i_req;
assign w_hit6_w = w_hit6 & i_wr & i_req;
assign w_hit9_w = w_hit9 & i_wr & i_req;
assign w_hitA_w = w_hitA & i_wr & i_req;
assign w_hitB_w = w_hitB & i_wr & i_req;
assign w_hitC_w = w_hitC & i_wr & i_req;
assign w_hitD_w = w_hitD & i_wr & i_req;
assign w_hitE_w = w_hitE & i_wr & i_req;
assign w_hitF_w = w_hitF & i_wr & i_req;
assign w_hit10_w = w_hit10 & i_wr & i_req;
assign w_hit11_w = w_hit11 & i_wr & i_req;
assign w_hit12_w = w_hit12 & i_wr & i_req;
assign w_hit13_w = w_hit13 & i_wr & i_req;
`ifdef USE_AXI_MONITOR
assign w_hit16_w = w_hit16 & i_wr & i_req;
assign w_hit32_dat = (r_rw_select) ? i_bukets_no_wait_ar : i_bukets_no_wait_aw;
assign w_hit33_dat = (r_rw_select) ? i_bukets_0_ar : i_bukets_0_aw;
assign w_hit34_dat = (r_rw_select) ? i_bukets_1_ar : i_bukets_1_aw;
assign w_hit35_dat = (r_rw_select) ? i_bukets_2_ar : i_bukets_2_aw;
assign w_hit36_dat = (r_rw_select) ? i_bukets_3_ar : i_bukets_3_aw;
assign w_hit37_dat = (r_rw_select) ? i_bukets_more_ar : i_bukets_more_aw;
assign w_hit38_dat = (r_rw_select) ? i_max_count_ar : i_max_count_aw;
assign w_hit39_dat = (r_rw_select) ? i_min_count_ar : i_min_count_aw;
assign w_hit40_dat = (r_rw_select) ? i_bukets_len_0_ar : i_bukets_len_0_aw;
assign w_hit41_dat = (r_rw_select) ? i_bukets_len_1_ar : i_bukets_len_1_aw;
assign w_hit42_dat = (r_rw_select) ? i_bukets_len_2_ar : i_bukets_len_2_aw;
assign w_hit43_dat = (r_rw_select) ? i_bukets_len_3_ar : i_bukets_len_3_aw;
assign w_hit44_dat = (r_rw_select) ? i_cont_ar : i_total_bytes_w;
assign w_hit45_dat = (r_rw_select) ? i_discont_ar : i_cont_w;
assign w_hit46_dat = (r_rw_select) ? i_bukets_no_wait_r : i_discont_w;
assign w_hit47_dat = (r_rw_select) ? i_bukets_0_r : i_bukets_no_wait_b;
assign w_hit48_dat = (r_rw_select) ? i_bukets_1_r : i_bukets_0_b;
assign w_hit49_dat = (r_rw_select) ? i_bukets_2_r : i_bukets_1_b;
assign w_hit50_dat = (r_rw_select) ? i_bukets_3_r : i_bukets_2_b;
assign w_hit51_dat = (r_rw_select) ? i_bukets_more_r : i_bukets_3_b;
assign w_hit52_dat = (r_rw_select) ? i_total_bytes_r : i_bukets_more_b;
assign w_hit53_dat = (r_rw_select) ? i_rd_cont : i_num_of_cmd_b;
assign w_hit54_dat = (r_rw_select) ? i_rd_discont : i_num_of_b;
assign w_hit55_dat = (r_rw_select) ? i_bukets_nrdy_0_r : i_bukets_nrdy_0_w;
assign w_hit56_dat = (r_rw_select) ? i_bukets_nrdy_1_r : i_bukets_nrdy_1_w;
assign w_hit57_dat = (r_rw_select) ? i_bukets_nrdy_2_r : i_bukets_nrdy_2_w;
assign w_hit58_dat = (r_rw_select) ? i_bukets_nrdy_3_r : i_bukets_nrdy_3_w;
`endif
assign w_rstr = i_req & !i_wr;
assign w_rd = (w_hit0) ? {15'b0,r_fb_blend_en,5'b0,r_aa_en,6'b0,r_video_start} :
(w_hit1) ? {r_fb0_offset,20'b0} :
(w_hit2) ? {r_fb1_offset,20'b0} :
(w_hit3) ? {r_fb0_ms_offset,20'b0} :
(w_hit4) ? {r_fb1_ms_offset,20'b0} :
(w_hit5) ? {30'b0,r_color_mode} :
(w_hit6) ? {
3'b0,
r_conf_awuser_m,
4'b0,
r_conf_awcache_m,
3'b0,
r_conf_aruser_m,
4'b0,
r_conf_arcache_m
} :
`ifdef PSOC_IN
(w_hit8) ? {27'b0,i_psoc,i_vtx_int,r_dma_int,!r_vint_x} :
`else
(w_hit8) ? {29'b0,i_vtx_int,r_dma_int,!r_vint_x} :
`endif
(w_hit9) ? {31'b0,r_vint_clear} :
(w_hitA) ? {29'b0,r_mask} :
(w_hitB) ? {31'b0,r_front_buffer} :
(w_hitC) ? {r_dma_top_address0,12'b0} :
(w_hitD) ? {r_dma_top_address1,12'b0} :
(w_hitE) ? {r_dma_top_address2,12'b0} :
(w_hitF) ? {r_dma_top_address3,12'b0} :
(w_hit10) ? {4'b0,r_dma_be,6'b0,r_dma_length} :
(w_hit11) ? r_dma_wd0 :
(w_hit12) ? r_dma_wd1 :
(w_hit14) ? 32'h50475055 : // PGPU
(w_hit15) ? 32'h76415849 : // vAXI
`ifdef USE_AXI_MONITOR
(w_hit16) ? {16'b0,7'b0,r_rw_select,7'b0,r_stop_trigger} :
`endif
`ifdef USE_AXI_MONITOR
(w_hit32) ? w_hit32_dat:
(w_hit33) ? w_hit33_dat:
(w_hit34) ? w_hit34_dat:
(w_hit35) ? w_hit35_dat:
(w_hit36) ? w_hit36_dat:
(w_hit37) ? w_hit37_dat:
(w_hit38) ? w_hit38_dat:
(w_hit39) ? w_hit39_dat:
(w_hit40) ? w_hit40_dat:
(w_hit41) ? w_hit41_dat:
(w_hit42) ? w_hit42_dat:
(w_hit43) ? w_hit43_dat:
(w_hit44) ? w_hit44_dat:
(w_hit45) ? w_hit45_dat:
(w_hit46) ? w_hit46_dat:
(w_hit47) ? w_hit47_dat:
(w_hit48) ? w_hit48_dat:
(w_hit49) ? w_hit49_dat:
(w_hit50) ? w_hit50_dat:
(w_hit51) ? w_hit51_dat:
(w_hit52) ? w_hit52_dat:
(w_hit53) ? w_hit53_dat:
(w_hit54) ? w_hit54_dat:
(w_hit55) ? w_hit55_dat:
(w_hit56) ? w_hit56_dat:
(w_hit57) ? w_hit57_dat:
(w_hit58) ? w_hit58_dat:
`endif
{23'b0,r_dma_int, r_dma_mode,3'b0,r_dma_start}; // w_hit13
assign w_vint_on = i_vint_edge; // falling edge detect
assign w_vint_x = ~r_vint_clear | i_vint_x;
assign w_int[0] = (r_mask[0]) ? 1'b0 : ~r_vint_x;
assign w_int[1] = (r_mask[1]) ? 1'b0 : r_dma_int;
assign w_int[2] = (r_mask[2]) ? 1'b0 : i_vtx_int;
assign o_int_x = !(|w_int);
assign o_rstr = r_rstr;
assign o_rd = r_rd;
assign o_ack = i_req;
assign o_video_start = r_video_start;
assign o_aa_en = r_aa_en;
assign o_fb0_offset = r_fb0_offset;
assign o_fb0_ms_offset = r_fb0_ms_offset;
assign o_fb1_offset = r_fb1_offset;
assign o_fb1_ms_offset = r_fb1_ms_offset;
assign o_color_mode = r_color_mode;
assign o_front_buffer = r_front_buffer;
assign o_fb_blend_en = r_fb_blend_en;
assign o_dma_start = r_dma_start;
assign o_dma_mode = r_dma_mode;
assign o_dma_top_address0 = r_dma_top_address0;
assign o_dma_top_address1 = r_dma_top_address1;
assign o_dma_top_address2 = r_dma_top_address2;
assign o_dma_top_address3 = r_dma_top_address3;
assign o_dma_length = r_dma_length;
assign o_dma_be = r_dma_be;
assign o_dma_wd0 = r_dma_wd0;
assign o_dma_wd1 = r_dma_wd1;
assign o_conf_arcache_m = r_conf_arcache_m;
assign o_conf_aruser_m = r_conf_aruser_m;
assign o_conf_awcache_m = r_conf_awcache_m;
assign o_conf_awuser_m = r_conf_awuser_m;
`ifdef USE_AXI_MONITOR
assign o_stop_trigger = r_stop_trigger;
`endif
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_video_start <= 2'b0;
end else begin
if (w_hit0_w) begin
if (i_be[0]) r_video_start <= i_wd[1:0];
if (i_be[1]) r_aa_en <= i_wd[10:8];
if (i_be[2]) r_fb_blend_en <= i_wd[16];
end
end
end
// register holds 32-bit address
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_fb0_offset <= 12'b0;
r_fb0_ms_offset <= 12'b0;
end else begin
if (w_hit1_w) begin
if (i_be[2]) r_fb0_offset[3:0] <= i_wd[23:20];
if (i_be[3]) r_fb0_offset[11:4] <= i_wd[31:24];
end
if (w_hit3_w) begin
if (i_be[2]) r_fb0_ms_offset[3:0] <= i_wd[23:20];
if (i_be[3]) r_fb0_ms_offset[11:4] <= i_wd[31:24];
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_fb1_offset <= 12'b0;
r_fb1_ms_offset <= 12'b0;
end else begin
if (w_hit2_w) begin
if (i_be[2]) r_fb1_offset[3:0] <= i_wd[23:20];
if (i_be[3]) r_fb1_offset[11:4] <= i_wd[31:24];
end
if (w_hit4_w) begin
if (i_be[2]) r_fb1_ms_offset[3:0] <= i_wd[23:20];
if (i_be[3]) r_fb1_ms_offset[11:4] <= i_wd[31:24];
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_color_mode <= 2'b0;
end else begin
if (w_hit5_w) begin
if (i_be[0]) r_color_mode <= i_wd[1:0];
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_conf_arcache_m <= 4'h0;
r_conf_aruser_m <= 5'h0;
r_conf_awcache_m <= 4'h0;
r_conf_awuser_m <= 5'h0;
end else begin
if (w_hit6_w) begin
if (i_be[0]) r_conf_arcache_m <= i_wd[3:0];
if (i_be[1]) r_conf_aruser_m <= i_wd[12:8];
if (i_be[2]) r_conf_awcache_m <= i_wd[19:16];
if (i_be[3]) r_conf_awuser_m <= i_wd[29:24];
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_vint_clear <= 1'b0;
end else begin
if (w_hit9_w) begin
if (i_be[0]) r_vint_clear <= i_wd[0];
end else if (w_vint_on) begin
r_vint_clear <= 1'b1;
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_mask <= 2'b11;
end else begin
if (w_hitA_w) begin
if (i_be[0]) r_mask <= i_wd[1:0];
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_front_buffer <= 1'b0;
end else begin
if (w_hitB_w) begin
if (i_be[0]) r_front_buffer <= i_wd[0];
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_dma_top_address0 <= 20'b0;
r_dma_top_address1 <= 20'b0;
r_dma_top_address2 <= 20'b0;
r_dma_top_address3 <= 20'b0;
end else begin
if (w_hitC_w) begin
r_dma_top_address0[11:0] <= i_wd[23:12];
r_dma_top_address0[19:12] <= i_wd[31:24];
end
if (w_hitD_w) begin
r_dma_top_address1[11:0] <= i_wd[23:12];
r_dma_top_address1[19:12] <= i_wd[31:24];
end
if (w_hitE_w) begin
r_dma_top_address2[11:0] <= i_wd[23:12];
r_dma_top_address2[19:12] <= i_wd[31:24];
end
if (w_hitF_w) begin
r_dma_top_address3[11:0] <= i_wd[23:12];
r_dma_top_address3[19:12] <= i_wd[31:24];
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_dma_length <= 18'b0;
r_dma_be <= 4'hf;
end else begin
if (w_hit10_w) begin
if (i_be[0]) r_dma_length[7:0] <= i_wd[7:0];
if (i_be[1]) r_dma_length[15:8] <= i_wd[15:8];
if (i_be[2]) r_dma_length[17:16] <= i_wd[17:16];
if (i_be[3]) r_dma_be <= i_wd[27:24];
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_dma_wd0 <= 32'b0;
r_dma_wd1 <= 32'b0;
end else begin
if (w_hit11_w) begin
r_dma_wd0 <= i_wd;
end
if (w_hit12_w) begin
r_dma_wd1 <= i_wd;
end
end
end
`ifdef USE_AXI_MONITOR
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_stop_trigger <= 1'b0;
r_rw_select <= 1'b0;
end else begin
if (w_hit16_w) begin
if (i_be[0]) r_stop_trigger <= i_wd[0];
if (i_be[1]) r_rw_select <= i_wd[8];
end
end
end
`endif
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_dma_start <= 1'b0;
r_dma_mode <= 4'b0;
r_dma_int <= 1'b0;
end else begin
if (w_hit13_w) begin
if (i_be[0]) r_dma_start <= i_wd[0];
if (i_be[0]) r_dma_mode <= i_wd[7:4];
if (i_be[1]) r_dma_int <= i_wd[8];
end else begin
if (i_dma_end) begin
r_dma_start <= 1'b0;
r_dma_mode <= 1'b0;
r_dma_int <= 1'b1;
end
end
end
end
always @(posedge clk_core) begin
r_rd <= w_rd;
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_rstr <= 1'b0;
end else begin
r_rstr <= w_rstr;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_vint_x <= 1'b1;
end else begin
r_vint_x <= w_vint_x;
end
end
endmodule
|
module fm_line_mem (
clk_vi,
rst_x,
i_clear,
i_dt,
i_renable,
o_dt
);
// set default parameters
parameter P_WIDTH = 16;
parameter P_RANGE = 10;
parameter P_DEPTH = 640;
////////////////////////////
// I/O definition
////////////////////////////
input clk_vi; // system clock
input rst_x; // system reset
input i_clear; // write strobe
input [P_WIDTH-1:0] i_dt; // write data
input i_renable; // read enable
output [P_WIDTH-1:0] o_dt; // read data
/////////////////////////
// Register definition
/////////////////////////
reg [P_RANGE-1:0] r_write_counter;
reg [P_RANGE-1:0] r_read_counter;
/////////////////////////
// wire definition
/////////////////////////
wire w_we;
wire w_re;
wire [P_RANGE-1:0] w_read_counter_inc;
wire [P_RANGE-1:0] w_read_counter;
/////////////////////////
// assign statement
/////////////////////////
assign w_read_counter_inc = r_read_counter + 1'b1;
assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
assign w_we = i_renable;
assign w_re = i_renable;
////////////////////////
// always statement
///////////////////////
// write side
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_write_counter <= 'd0;
end else begin
if (i_clear) r_write_counter <= 'd0;
else if (w_we) r_write_counter <= r_write_counter + 1'b1;
end
end
// read side
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_read_counter <= 'd0;
end else begin
if (i_clear) r_read_counter <= 'd0;
else if (w_re) r_read_counter <= w_read_counter_inc;
end
end
///////////////////
// module instance
///////////////////
fm_cmn_bram_01 #(P_WIDTH, P_RANGE) bram_00 (
.clk(clk_vi),
.we(w_we),
.a(r_write_counter),
.dpra(w_read_counter),
.di(i_dt),
.spo(),
.dpo(o_dt)
);
endmodule
|
module fm_hvc (
clk_core,
clk_vi,
rst_x,
// debug
o_debug,
// configuration registers
i_video_start,
i_fb0_offset,
i_fb0_ms_offset,
i_fb1_offset,
i_fb1_ms_offset,
i_color_mode,
i_front_buffer,
i_aa_en,
i_fb_blend_en,
// status out
o_vint_x,
o_vint_edge,
// dram if
o_req,
o_adrs,
o_len,
i_ack,
i_rstr,
i_rd,
// video out
clk_vo,
o_r_neg,
o_g_neg,
o_b_neg,
o_vsync_x_neg,
o_hsync_x_neg,
o_r,
o_g,
o_b,
o_vsync_x,
o_hsync_x,
o_blank_x
);
`include "polyphony_params.v"
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input clk_vi; // 25MHz
input rst_x;
// debug
output [1:0] o_debug;
// configuration registers
input [1:0] i_video_start;
input [11:0] i_fb0_offset;
input [11:0] i_fb0_ms_offset;
input [11:0] i_fb1_offset;
input [11:0] i_fb1_ms_offset;
input [1:0] i_color_mode;
input i_front_buffer;
input [2:0] i_aa_en;
input i_fb_blend_en;
// status out
output o_vint_x;
output o_vint_edge;
// dram if
/*(* mark_debug = "true" *)*/ output o_req;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs;
output [P_IB_LEN_WIDTH-1:0]
o_len;
input i_ack;
input i_rstr;
input [P_IB_DATA_WIDTH-1:0]
i_rd;
output clk_vo;
output [7:0] o_r_neg;
output [7:0] o_g_neg;
output [7:0] o_b_neg;
output o_vsync_x_neg;
output o_hsync_x_neg;
output [7:0] o_r;
output [7:0] o_g;
output [7:0] o_b;
output o_vsync_x;
output o_hsync_x;
output o_blank_x;
//////////////////////////////////
// wire
//////////////////////////////////
wire [7:0] w_test_r;
wire [7:0] w_test_g;
wire [7:0] w_test_b;
wire w_vsync_i;
wire w_hsync_i;
wire w_active;
wire w_first_line;
wire w_fifo_available;
wire w_fifo_available_ack;
//////////////////////////////////
// assign
//////////////////////////////////
assign clk_vo = clk_vi;
///////////////////////////
// module instance
//////////////////////////
fm_hvc_core fm_hvc_core (
.clk_vi(clk_vi),
.rst_x(rst_x),
// configuration registers
.i_video_start(i_video_start[0]),
// control out (only for internal use)
.o_vsync_i(w_vsync_i),
.o_hsync_i(w_hsync_i),
// video out timing
.o_active(w_active),
.o_first_line(w_first_line),
.o_r(w_test_r),
.o_g(w_test_g),
.o_b(w_test_b),
.o_vsync_x_neg(o_vsync_x_neg),
.o_hsync_x_neg(o_hsync_x_neg),
.o_vsync_x(o_vsync_x),
.o_hsync_x(o_hsync_x),
.o_blank_x(o_blank_x)
);
`ifdef PP_BUSWIDTH_64
`else
wire w_req;
wire [P_IB_ADDR_WIDTH-1:0]
w_adrs;
wire [P_IB_LEN_WIDTH-1:0]
w_len;
wire w_ack;
fm_rd_split fm_rd_split (
.clk_core(clk_core),
.rst_x(rst_x),
.i_req(w_req),
.i_adrs(w_adrs),
.i_len(w_len),
.o_ack(w_ack),
// dram if
.o_req(o_req),
.o_adrs(o_adrs),
.o_len(o_len),
.i_ack(i_ack)
);
`endif
fm_hvc_dma fm_hvc_dma (
.clk_core(clk_core),
.rst_x(rst_x),
.i_video_start(i_video_start[1]),
.i_vsync(w_vsync_i),
.i_hsync(w_hsync_i),
.i_fb0_offset(i_fb0_offset),
.i_fb0_ms_offset(i_fb0_ms_offset),
.i_fb1_offset(i_fb1_offset),
.i_fb1_ms_offset(i_fb1_ms_offset),
.i_front_buffer(i_front_buffer),
.i_aa_en(i_aa_en[0]),
.i_fifo_available(w_fifo_available),
.o_fifo_available_ack(w_fifo_available_ack),
.o_vsync(o_vint_x),
.o_vsync_edge(o_vint_edge),
// dram if
`ifdef PP_BUSWIDTH_64
.o_req(o_req),
.o_adrs(o_adrs),
.o_len(o_len),
.i_ack(i_ack)
`else
.o_req(w_req),
.o_adrs(w_adrs),
.o_len(w_len),
.i_ack(w_ack)
`endif
);
fm_hvc_data fm_hvc_data (
.clk_core(clk_core),
.clk_vi(clk_vi),
.rst_x(rst_x),
// debug
.o_debug(o_debug),
// sdram interface
.i_rstr(i_rstr),
.i_rd(i_rd),
// timing control
.i_h_active(w_active),
.i_first_line(w_first_line),
.i_hsync(w_hsync_i),
.i_vsync(w_vsync_i),
.o_fifo_available(w_fifo_available),
.i_fifo_available_ack(w_fifo_available_ack),
// configuration
.i_video_start(i_video_start[0]),
.i_color_mode(i_color_mode),
.i_aa_en(i_aa_en),
.i_fb_blend_en(i_fb_blend_en),
// test color input
.i_test_r(w_test_r),
.i_test_g(w_test_g),
.i_test_b(w_test_b),
// color out
.o_r_neg(o_r_neg),
.o_g_neg(o_g_neg),
.o_b_neg(o_b_neg),
.o_r(o_r),
.o_g(o_g),
.o_b(o_b),
.o_a()
);
endmodule
|
module fm_afifo (
clk_core,
clk_vi,
rst_x,
i_wstrobe,
i_dt,
o_full,
i_renable,
o_dt,
o_empty,
o_dnum
);
// set default parameters
parameter P_RANGE = 7;
parameter P_DEPTH = 1 << P_RANGE; // 128
`include "polyphony_params.v"
////////////////////////////
// I/O definition
////////////////////////////
input clk_core; // system clock
input clk_vi;
input rst_x; // system reset
input i_wstrobe; // write strobe
input [P_IB_DATA_WIDTH-1:0]
i_dt; // write data
output o_full; // write data full
input i_renable; // read enable
output [15:0] o_dt; // read data
output o_empty; // read data empty
output [P_RANGE:0] o_dnum; // written data number
/////////////////////////
// Register definition
/////////////////////////
reg [P_RANGE-1:0] r_write_counter;
reg [P_RANGE-1:0] r_read_counter;
// data registers
`ifdef PP_BUSWIDTH_64
reg [1:0] r_select_hw;
`else
reg r_select_hw;
`endif
/////////////////////////
// wire definition
/////////////////////////
wire o_full;
wire o_empty;
wire [15:0] o_dt;
wire w_we;
wire w_re;
wire [P_IB_DATA_WIDTH-1:0]
w_dt;
wire [P_RANGE-1:0] w_read_counter_inc;
wire [P_RANGE-1:0] w_read_counter;
/////////////////////////
// assign statement
/////////////////////////
`ifdef PP_BUSWIDTH_64
assign o_dt = (r_select_hw == 'd1) ? w_dt[31:16] :
(r_select_hw == 'd2) ? w_dt[47:32] :
(r_select_hw == 'd3) ? w_dt[63:48] :
w_dt[15:0];
`else
assign o_dt = (r_select_hw) ? w_dt[31:16] : w_dt[15:0];
`endif
assign o_dnum = 0;
assign o_full = 1'b0;
assign o_empty = 1'b0;
assign w_we = i_wstrobe;
`ifdef PP_BUSWIDTH_64
assign w_re = i_renable & (r_select_hw == 'd3);
`else
assign w_re = i_renable & r_select_hw;
`endif
assign w_read_counter_inc = r_read_counter + 1'b1;
assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
////////////////////////
// always
///////////////////////
// write side (clk_core)
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_write_counter <= 'd0;
end else begin
if (w_we) begin
r_write_counter <= r_write_counter + 1'b1;
end
end
end
// read side (clk_vi)
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_read_counter <= 'd0;
end else begin
if (w_re) begin
r_read_counter <= w_read_counter_inc;
end
end
end
// select half word
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_select_hw <= 'd0;
end else begin
if (i_renable) r_select_hw <= r_select_hw + 1'b1;
end
end
///////////////////
// module instance
///////////////////
fm_cmn_bram_02 #(P_IB_DATA_WIDTH, P_RANGE) bram_00 (
.clka(clk_core),
.clkb(clk_vi),
.wea(w_we),
.addra(r_write_counter),
.addrb(w_read_counter),
.dia(i_dt),
.doa(),
.dob(w_dt)
);
endmodule
|
module fm_hvc_data (
clk_core,
clk_vi,
rst_x,
// debug
o_debug,
// sdram interface
i_rstr,
i_rd,
// timing input
i_h_active,
i_first_line,
i_hsync,
i_vsync,
o_fifo_available,
i_fifo_available_ack,
// configuration
i_video_start,
i_color_mode,
i_aa_en,
i_fb_blend_en,
// test color input
i_test_r,
i_test_g,
i_test_b,
// color out
o_r_neg,
o_g_neg,
o_b_neg,
o_r,
o_g,
o_b,
o_a
);
`include "polyphony_params.v"
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input clk_vi; // 25MHz
input rst_x;
// debug
output [1:0] o_debug;
// sdram interface
input i_rstr;
input [P_IB_DATA_WIDTH-1:0]
i_rd;
// timing input
input i_h_active;
input i_first_line;
input i_hsync;
input i_vsync;
output o_fifo_available;
input i_fifo_available_ack;
// configuration
input i_video_start;
input [1:0] i_color_mode;
input [2:0] i_aa_en;
input i_fb_blend_en;
// test color input
input [7:0] i_test_r;
input [7:0] i_test_g;
input [7:0] i_test_b;
output [7:0] o_r_neg;
output [7:0] o_g_neg;
output [7:0] o_b_neg;
output [7:0] o_r;
output [7:0] o_g;
output [7:0] o_b;
output [7:0] o_a;
//////////////////////////////////
// reg
//////////////////////////////////
reg r_rkind;
reg [4:0] r_rd_cnt;
reg [5:0] r_pix_cnt;
reg r_fifo_available;
reg [7:0] r_r;
reg [7:0] r_g;
reg [7:0] r_b;
reg [7:0] r_r_neg;
reg [7:0] r_g_neg;
reg [7:0] r_b_neg;
reg r_fifo_available_ack_1z;
reg r_fifo_available_ack_2z;
reg r_fifo_available_ack_3z;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_switch_fifo_ren;
wire w_rstr_base;
wire w_rstr_upper;
wire [15:0] w_di;
wire [15:0] w_di_upper;
wire [15:0] w_di_lower;
wire [31:0] w_do;
wire [31:0] w_do_normal;
wire [7:0] w_r_aa;
wire [7:0] w_g_aa;
wire [7:0] w_b_aa;
wire [7:0] w_r_f;
wire [7:0] w_g_f;
wire [7:0] w_b_f;
wire [7:0] w_r;
wire [7:0] w_g;
wire [7:0] w_b;
wire w_ren;
wire w_fifo_reset_x;
wire w_fifo_available_ack_rise;
wire w_full;
wire w_empty;
wire w_full_u;
wire w_empty_u;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_fifo_available_ack_rise = r_fifo_available_ack_2z &
!r_fifo_available_ack_3z;
assign w_fifo_reset_x = i_vsync & rst_x;
`ifdef PP_BUSWIDTH_64
assign w_switch_fifo_ren = (r_rd_cnt == 5'd15) & i_rstr;
`else
assign w_switch_fifo_ren = (r_rd_cnt == 5'd31) & i_rstr;
`endif
assign w_rstr_base = (i_aa_en[0]) ? !r_rkind & i_rstr : i_rstr;
assign w_rstr_upper = (i_aa_en[0]) ? r_rkind & i_rstr : i_rstr;
assign w_ren = i_h_active;
assign w_r_f = (i_aa_en[1]) ? w_r_aa : w_do_normal[31:24];
assign w_g_f = (i_aa_en[1]) ? w_g_aa : w_do_normal[23:16];
assign w_b_f = (i_aa_en[1]) ? w_b_aa : w_do_normal[15:8];
assign w_do_normal = f_get_color(w_di,i_color_mode);
assign w_b = (!i_video_start) ? i_test_b :
(i_h_active )? w_b_f :
8'h00;
assign w_g = (!i_video_start) ? i_test_g :
(i_h_active )? w_g_f :
8'h00;
assign w_r = (!i_video_start) ? i_test_r :
(i_h_active )? w_r_f :
8'h00;
assign o_b_neg = r_b_neg;
assign o_g_neg = r_g_neg;
assign o_r_neg = r_r_neg;
assign o_b = r_b;
assign o_g = r_g;
assign o_r = r_r;
assign o_fifo_available = r_fifo_available;
// debug port
`ifdef PP_COREGEN_FIFO
reg r_error_1z;
reg r_error_2z;
assign o_debug[0] = w_full & w_rstr_base;
assign o_debug[1] = r_error_2z;
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_error_1z <= 1'b0;
r_error_2z <= 1'b0;
end else begin
r_error_1z <= w_empty & w_ren;
r_error_2z <= r_error_1z;
end
end
`else
assign o_debug = 2'd0;
`endif
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core or negedge w_fifo_reset_x) begin
if (~w_fifo_reset_x) begin
r_rkind <= 1'b0;
end else begin
if (w_switch_fifo_ren) r_rkind <= ~r_rkind;
end
end
always @(posedge clk_core or negedge w_fifo_reset_x) begin
if (~w_fifo_reset_x) begin
r_rd_cnt <= 5'd0;
end else begin
if (i_rstr) r_rd_cnt <= r_rd_cnt + 1'b1;
end
end
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_pix_cnt <= 6'd0;
end else begin
if (~i_hsync) r_pix_cnt <= 6'd0;
else if (w_ren) r_pix_cnt <= r_pix_cnt + 1'b1;
end
end
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_fifo_available <= 1'b0;
end else begin
if (r_pix_cnt == 6'd63) r_fifo_available <= 1'b1;
else if (~i_hsync | w_fifo_available_ack_rise) r_fifo_available <= 1'b0;
end
end
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_fifo_available_ack_1z <= 1'b0;
r_fifo_available_ack_2z <= 1'b0;
r_fifo_available_ack_3z <= 1'b0;
end else begin
r_fifo_available_ack_1z <= i_fifo_available_ack;
r_fifo_available_ack_2z <= r_fifo_available_ack_1z;
r_fifo_available_ack_3z <= r_fifo_available_ack_2z;
end
end
always @(posedge clk_vi) begin
r_r <= w_r;
r_g <= w_g;
r_b <= w_b;
end
// neg-edge registers for output timing adjustment
always @(negedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_r_neg <= 8'h0;
r_g_neg <= 8'h0;
r_b_neg <= 8'h0;
end else begin
r_r_neg <= r_r;
r_g_neg <= r_g;
r_b_neg <= r_b;
end
end
//////////////////////////////////
// function
//////////////////////////////////
function [31:0] f_get_color;
input [15:0] idata;
input [1:0] mode;
reg [7:0] r;
reg [7:0] g;
reg [7:0] b;
reg [7:0] a;
begin
case (mode)
2'b00 : begin
// color mode 5:6:5
r = {idata[15:11],idata[15:13]};
g = {idata[10:5],idata[10:9]};
b = {idata[4:0],idata[4:2]};
a = 8'h0;
end
2'b01 : begin
// color mode 5:5:5:1
r = {idata[15:11],idata[15:13]};
g = {idata[10:6],idata[10:8]};
b = {idata[5:1],idata[5:3]};
a = {idata[0],7'b0};
end
2'b10 : begin
// color mode 4:4:4:4
r = {idata[15:12],idata[15:12]};
g = {idata[11:8],idata[11:8]};
b = {idata[7:4],idata[7:4]};
a = {idata[3:0],idata[3:0]};
end
default : begin
// color mode 4:4:4:4
r = {idata[15:12],idata[15:12]};
g = {idata[11:8],idata[11:8]};
b = {idata[7:4],idata[7:4]};
a = {idata[3:0],idata[3:0]};
end
endcase
f_get_color = {r,g,b,a};
end
endfunction
//////////////////////////////////
// module instance
//////////////////////////////////
// Anti-aliasing filter module
fm_hvc_aa_filter aa_filter (
.clk_vi(clk_vi),
.rst_x(rst_x),
// configuration
.i_fb_blend_en(i_fb_blend_en),
// incoming color
.i_h_active(i_h_active),
.i_first_line(i_first_line),
.i_r_base(w_do_normal[31:24]),
.i_g_base(w_do_normal[23:16]),
.i_b_base(w_do_normal[15:8]),
.i_upper(w_di_upper),
.i_lower(w_di_lower),
// outgoing color
.o_r(w_r_aa),
.o_g(w_g_aa),
.o_b(w_b_aa)
);
`ifdef PP_COREGEN_FIFO
// 32bit x 128 entry fifo for current line
// (16bit output)
fifo_generator_v9_3_0 u_afifo_c (
.rst(~w_fifo_reset_x), // input rst
.wr_clk(clk_core), // input wr_clk
.rd_clk(clk_vi), // input rd_clk
.din({i_rd[15:0],i_rd[31:16]}), // input [31 : 0] din
.wr_en(w_rstr_base), // input wr_en
.rd_en(w_ren), // input rd_en
.dout(w_di), // output [31 : 0] dout
.full(w_full), // output full
.empty(w_empty) // output empty
);
// 32bit x 128 entry fifo for upper line
fifo_generator_v9_3_0 u_afifo_upper (
.rst(~w_fifo_reset_x),
.wr_clk(clk_core),
.rd_clk(clk_vi),
.wr_en(w_rstr_upper),
.din({i_rd[15:0],i_rd[31:16]}),
.full(w_full_u),
.rd_en(w_ren),
.dout(w_di_upper),
.empty(w_empty_u)
);
`else
// 32bit x 128 entry fifo for current line
fm_afifo fm_afifo_c (
.clk_core(clk_core),
.clk_vi(clk_vi),
.rst_x(w_fifo_reset_x),
.i_wstrobe(w_rstr_base),
.i_dt(i_rd),
.o_full(),
.i_renable(w_ren),
.o_dt(w_di),
.o_empty(),
.o_dnum()
);
// 32bit x 128 entry fifo for upper line
fm_afifo fm_afifo_upper (
.clk_core(clk_core),
.clk_vi(clk_vi),
.rst_x(w_fifo_reset_x),
.i_wstrobe(w_rstr_upper),
.i_dt(i_rd),
.o_full(),
.i_renable(w_ren),
.o_dt(w_di_upper),
.o_empty(),
.o_dnum()
);
`endif
// 32bit x 640 entry fifo for lower line
fm_line_mem fm_line_lower (
.clk_vi(clk_vi),
.rst_x(w_fifo_reset_x),
.i_clear(~i_hsync),
.i_dt(w_di_upper),
.i_renable(w_ren),
.o_dt(w_di_lower)
);
/*
wire [35:0] CONTROL0;
wire [35:0] TRIG0;
chipscope_icon_v1_06_a_0 u_icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_ila_v1_05_a_0 u_chipscope (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(clk_vi), // IN
.TRIG0(TRIG0) // IN BUS [255:0]
// .DATA(DATA)
);
assign TRIG0[0] = w_fifo_reset_x;
assign TRIG0[1] = w_ren;
assign TRIG0[2] = w_empty;
assign TRIG0[3] = w_empty_u;
assign TRIG0[35:4] = w_di;
*/
endmodule
|
module fm_hvc_aa_filter (
clk_vi,
rst_x,
// configuration
i_fb_blend_en,
// incoming color
i_h_active,
i_first_line,
i_r_base,
i_g_base,
i_b_base,
i_upper,
i_lower,
// outgoing color
o_r,
o_g,
o_b
);
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_vi; // 25MHz
input rst_x;
// configuration
input i_fb_blend_en;
// incoming color
input i_h_active;
input i_first_line;
input [7:0] i_r_base;
input [7:0] i_g_base;
input [7:0] i_b_base;
input [15:0] i_upper;
input [15:0] i_lower;
// outgoing color
output [7:0] o_r;
output [7:0] o_g;
output [7:0] o_b;
//////////////////////////////////
// reg
//////////////////////////////////
reg [15:0] r_upper;
reg [15:0] r_lower;
//////////////////////////////////
// wire
//////////////////////////////////
wire [7:0] w_r_tr;
wire [7:0] w_g_tr;
wire [7:0] w_b_tr;
wire [7:0] w_r_tl;
wire [7:0] w_g_tl;
wire [7:0] w_b_tl;
wire [7:0] w_r_br;
wire [7:0] w_g_br;
wire [7:0] w_b_br;
wire [7:0] w_r_bl;
wire [7:0] w_g_bl;
wire [7:0] w_b_bl;
//////////////////////////////////
// assign
//////////////////////////////////
// extend 5:6:5 to 8:8:8
assign w_r_tr = {i_upper[15:11],i_upper[15:13]};
assign w_g_tr = {i_upper[10:5],i_upper[10:9]};
assign w_b_tr = {i_upper[4:0],i_upper[4:2]};
assign w_r_tl = {r_upper[15:11],r_upper[15:13]};
assign w_g_tl = {r_upper[10:5],r_upper[10:9]};
assign w_b_tl = {r_upper[4:0],r_upper[4:2]};
assign w_r_br = (i_first_line) ? w_r_tr : {i_lower[15:11],i_lower[15:13]};
assign w_g_br = (i_first_line) ? w_g_tr : {i_lower[10:5],i_lower[10:9]};
assign w_b_br = (i_first_line) ? w_b_tr : {i_lower[4:0],i_lower[4:2]};
assign w_r_bl = (i_first_line) ? w_r_tl : {r_lower[15:11],r_lower[15:13]};
assign w_g_bl = (i_first_line) ? w_g_tl : {r_lower[10:5],r_lower[10:9]};
assign w_b_bl = (i_first_line) ? w_b_tl : {r_lower[4:0],r_lower[4:2]};
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_vi) begin
r_upper <= i_upper;
r_lower <= i_lower;
end
//////////////////////////////////
// module instance
//////////////////////////////////
// r component
fm_hvc_aa_filter_core filter_r (
.clk_vi(clk_vi),
// configuration
.i_fb_blend_en(i_fb_blend_en),
// incoming color
.i_base(i_r_base),
.i_br(w_r_br),
.i_bl(w_r_bl),
.i_tr(w_r_tr),
.i_tl(w_r_tl),
// outgoing color
.o_c(o_r)
);
// g component
fm_hvc_aa_filter_core filter_g (
.clk_vi(clk_vi),
// configuration
.i_fb_blend_en(i_fb_blend_en),
// incoming color
.i_base(i_g_base),
.i_br(w_g_br),
.i_bl(w_g_bl),
.i_tr(w_g_tr),
.i_tl(w_g_tl),
// outgoing color
.o_c(o_g)
);
// b component
fm_hvc_aa_filter_core filter_b (
.clk_vi(clk_vi),
// configuration
.i_fb_blend_en(i_fb_blend_en),
// incoming color
.i_base(i_b_base),
.i_br(w_b_br),
.i_bl(w_b_bl),
.i_tr(w_b_tr),
.i_tl(w_b_tl),
// outgoing color
.o_c(o_b)
);
endmodule
|
module fm_hvc_core (
clk_vi,
rst_x,
// configuration registers
i_video_start,
// control out (only for internal use)
o_vsync_i,
o_hsync_i,
// video out timing
o_active,
o_first_line,
// video out
o_r,
o_g,
o_b,
o_vsync_x_neg,
o_hsync_x_neg,
o_vsync_x,
o_hsync_x,
o_blank_x
);
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_vi; // 25MHz
input rst_x;
// configuration registers
input i_video_start;
// control out (only for internal use)
output o_vsync_i;
output o_hsync_i;
// video out timing
output o_active;
output o_first_line;
output [7:0] o_r;
output [7:0] o_g;
output [7:0] o_b;
output o_vsync_x_neg;
output o_hsync_x_neg;
output o_vsync_x;
output o_hsync_x;
output o_blank_x;
//////////////////////////////////
// reg
//////////////////////////////////
reg [9:0] r_hcnt;
reg [9:0] r_vcnt;
reg r_vsync_x;
reg r_hsync_x;
reg r_hsync_x_i; // internal use, vactive only
reg r_blank_x;
reg r_vsync_neg;
reg r_hsync_neg;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_h_end;
wire w_v_end;
wire w_vsync;
wire w_hsync;
wire w_hsync_dma;
wire w_hactive;
wire w_vactive_first; // for aa
wire w_vactive;
wire w_active;
wire w_active_first; // for aa
// color bar
wire w_r_test_en = ((r_hcnt >= 160) & (r_hcnt <= 251)) |
((r_hcnt >= 252) & (r_hcnt <= 343)) |
((r_hcnt >= 527) & (r_hcnt <= 617)) |
((r_hcnt >= 618) & (r_hcnt <= 708));
wire w_g_test_en = ((r_hcnt >= 160) & (r_hcnt <= 251)) |
((r_hcnt >= 252) & (r_hcnt <= 343)) |
((r_hcnt >= 344) & (r_hcnt <= 435)) |
((r_hcnt >= 436) & (r_hcnt <= 526));
wire w_b_test_en = ((r_hcnt >= 160) & (r_hcnt <= 251)) |
((r_hcnt >= 344) & (r_hcnt <= 435)) |
((r_hcnt >= 527) & (r_hcnt <= 617)) |
((r_hcnt >= 709) & (r_hcnt <= 799));
wire [7:0] w_r_test = {8{w_r_test_en}};
wire [7:0] w_g_test = {8{w_g_test_en}};
wire [7:0] w_b_test = {8{w_b_test_en}};
wire w_hsync_x_i;
//////////////////////////////////
// assign
//////////////////////////////////
// VGA : 60Hz
assign w_h_end = (r_hcnt == 'd799); // 800 clock
assign w_v_end = w_h_end & (r_vcnt == 'd524); // 525 line
assign w_vsync = ((r_vcnt == 10'd10) | (r_vcnt == 10'd11)) ? 1'b0 : 1'b1;
assign w_hsync = ((r_hcnt >= 10'd16)&(r_hcnt <= 10'd111)) ? 1'b0 : 1'b1;
assign w_hsync_dma = ((r_hcnt >= 10'd16)&(r_hcnt <= 10'd39)) ? 1'b0 : 1'b1;
assign w_hactive = ((r_hcnt >= 10'd160)&(r_hcnt <= 10'd799)) ? 1'b1 : 1'b0;
assign w_vactive = ((r_vcnt >= 10'd45)&(r_vcnt <= 10'd524)) ? 1'b1 : 1'b0;
assign w_vactive_first = (r_vcnt == 10'd45);
assign w_active = w_hactive & w_vactive;
assign w_active_first = w_vactive_first;
assign w_hsync_x_i = w_vactive & w_hsync_dma;
// color should be black in blanking
//assign w_r = (w_active) ? w_rgb[7:0] : 8'h00;
//assign w_g = (w_active) ? w_rgb[15:8] : 8'h00;
//assign w_b = (w_active) ? w_rgb[23:16] : 8'h00;
assign o_vsync_x_neg = r_vsync_neg;
assign o_hsync_x_neg = r_hsync_neg;
assign o_vsync_x = r_vsync_x;
assign o_hsync_x = r_hsync_x;
assign o_blank_x = r_blank_x;
assign o_r = w_r_test;
assign o_g = w_g_test;
assign o_b = w_b_test;
assign o_vsync_i = r_vsync_x;
assign o_hsync_i = r_hsync_x_i;
assign o_active = w_active;
assign o_first_line = w_active_first;
//////////////////////////////////
// always
//////////////////////////////////
// H counter
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_hcnt <= 11'b0;
end else begin
if (w_h_end) r_hcnt <= 11'b0;
else r_hcnt <= r_hcnt + 1'b1;
end
end
// V counter
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
// r_vcnt <= 10'd0;
// r_vcnt <= 10'd36; // this is only for faster simulatin
r_vcnt <= 10'd9; // this is only for faster simulatin (v rise)
end else begin
if (w_v_end) r_vcnt <= 10'd0;
else if (w_h_end) r_vcnt <= r_vcnt + 1'b1;
end
end
// sync
always @(posedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_vsync_x <= 1'b1;
r_hsync_x <= 1'b1;
r_blank_x <= 1'b1;
end else begin
r_vsync_x <= w_vsync;
r_hsync_x <= w_hsync;
r_hsync_x_i <= w_hsync_x_i;
r_blank_x <= w_active;
end
end
// neg-edge registers for output timing adjustment
always @(negedge clk_vi or negedge rst_x) begin
if (~rst_x) begin
r_vsync_neg <= 1'b1;
r_hsync_neg <= 1'b1;
end else begin
r_vsync_neg <= r_vsync_x;
r_hsync_neg <= r_hsync_x;
end
end
endmodule
|
module fm_hvc_dma (
clk_core,
rst_x,
i_video_start,
i_vsync,
i_hsync,
i_fb0_offset,
i_fb0_ms_offset,
i_fb1_offset,
i_fb1_ms_offset,
i_front_buffer,
i_aa_en,
i_fifo_available,
o_fifo_available_ack,
o_vsync,
o_vsync_edge,
// dram if
o_req,
o_adrs,
o_len,
i_ack
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
parameter P_IDLE = 3'd0;
parameter P_REQ = 3'd1;
parameter P_REQ_AA = 3'd2;
parameter P_WAIT_FIFO_AVL = 3'd3;
parameter P_WAIT_AVL_FALL = 3'd4;
parameter P_BURST_SIZE = 6'd32;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
input i_video_start;
input i_vsync;
input i_hsync;
input [11:0] i_fb0_offset;
input [11:0] i_fb0_ms_offset;
input [11:0] i_fb1_offset;
input [11:0] i_fb1_ms_offset;
input i_front_buffer;
input i_aa_en;
input i_fifo_available;
output o_fifo_available_ack;
output o_vsync;
output o_vsync_edge;
// dram if
output o_req;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs;
output [P_IB_LEN_WIDTH-1:0]
o_len; // 32 burst x 10
input i_ack;
//////////////////////////////////
// reg
//////////////////////////////////
reg [2:0] r_state;
reg r_req;
// reg [17:0] r_cur_adrs_l;
reg [12:0] r_cur_adrs_l;
reg [3:0] r_req_cnt;
// syncro register
reg r_vsync_1z;
reg r_vsync_2z;
reg r_vsync_3z;
reg r_hsync_1z;
reg r_hsync_2z;
reg r_hsync_3z;
reg r_fifo_available_1z;
reg r_fifo_available_2z;
reg r_fifo_available_3z;
reg r_fifo_available_ack;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_set_initial_adrs;
wire w_v_rise;
wire w_h_start;
wire w_adrs_inc;
wire w_line_end;
wire w_req_cnt_clear;
wire [11:0] w_fb_offset;
wire [11:0] w_fb_ms_offset;
wire [11:0] w_offset;
//////////////////////////////////
// assign
//////////////////////////////////
assign o_req = r_req;
`ifdef PP_BUSWIDTH_64
assign o_len = P_BURST_SIZE >> 1;
`else
assign o_len = P_BURST_SIZE;
`endif
assign o_fifo_available_ack = r_fifo_available_ack;
assign w_set_initial_adrs = w_v_rise;
assign w_adrs_inc = (i_aa_en) ? (r_state == P_REQ_AA) & i_ack:
(r_state == P_REQ) & i_ack;
assign w_h_start = i_video_start & r_hsync_2z & !r_hsync_3z; // rise of hsync
assign w_v_rise = r_vsync_2z & !r_vsync_3z; // rising edge of vsync
assign w_line_end = (r_req_cnt == 4'd10); // 320 times
assign w_req_cnt_clear = w_line_end & !r_fifo_available_2z &
(r_state == P_WAIT_AVL_FALL);
`ifdef PP_BUSWIDTH_64
assign o_adrs = {w_offset, r_cur_adrs_l,4'b0};
`else
assign o_adrs = {w_offset, r_cur_adrs_l,5'b0};
`endif
assign w_fb_offset = (i_front_buffer) ? i_fb1_offset : i_fb0_offset;
assign w_fb_ms_offset = (i_front_buffer) ? i_fb1_ms_offset : i_fb0_ms_offset;
assign w_offset = (r_state == P_REQ_AA) ? w_fb_ms_offset : w_fb_offset;
assign o_vsync = r_vsync_2z;
assign o_vsync_edge = !r_vsync_2z & r_vsync_3z; // falling edge
//////////////////////////////////
// always
//////////////////////////////////
// request state
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
r_req <= 1'b0;
r_fifo_available_ack <= 1'b0;
end else begin
case (r_state)
P_IDLE: begin
if (w_h_start) begin
r_req <= 1'b1;
r_state <= P_REQ;
end
end
P_REQ: begin
if (i_ack) begin
if (i_aa_en) begin
r_req <= 1'b1;
r_state <= P_REQ_AA;
end else begin
r_req <= 1'b0;
r_state <= P_WAIT_FIFO_AVL;
end
end
end
P_REQ_AA: begin
if (i_ack) begin
r_req <= 1'b0;
r_state <= P_WAIT_FIFO_AVL;
end
end
P_WAIT_FIFO_AVL: begin
if (r_req_cnt < 4'd4) begin
r_req <= 1'b1;
r_state <= P_REQ;
end else begin
if (r_fifo_available_2z) begin
r_fifo_available_ack <= 1'b1;
r_state <= P_WAIT_AVL_FALL;
end
end
end
P_WAIT_AVL_FALL: begin
if (!r_fifo_available_2z) begin
r_fifo_available_ack <= 1'b0;
if (w_line_end) begin
r_state <= P_IDLE;
end else begin
r_req <= 1'b1;
r_state <= P_REQ;
end
end
end
endcase
end
end
// current address
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_cur_adrs_l <= 13'h0; // for simulation
end else begin
if (w_set_initial_adrs) begin
r_cur_adrs_l <= 13'h0;
end else if (w_adrs_inc) begin
r_cur_adrs_l <= r_cur_adrs_l + 1'b1; // same as + 32
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_req_cnt <= 4'd0;
end else begin
if (w_req_cnt_clear) r_req_cnt <= 4'd0;
else if (w_adrs_inc) r_req_cnt <= r_req_cnt + 1'b1;
end
end
// syncro register
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_vsync_1z <= 1'b1;
r_vsync_2z <= 1'b1;
r_vsync_3z <= 1'b1;
r_hsync_1z <= 1'b1;
r_hsync_2z <= 1'b1;
r_hsync_3z <= 1'b1;
r_fifo_available_1z <= 1'b0;
r_fifo_available_2z <= 1'b0;
end else begin
r_vsync_1z <= i_vsync;
r_vsync_2z <= r_vsync_1z;
r_vsync_3z <= r_vsync_2z;
r_hsync_1z <= i_hsync;
r_hsync_2z <= r_hsync_1z;
r_hsync_3z <= r_hsync_2z;
r_fifo_available_1z <= i_fifo_available;
r_fifo_available_2z <= r_fifo_available_1z;
end
end
endmodule
|
module fm_hvc_aa_filter_core (
clk_vi,
// configuration
i_fb_blend_en,
// incoming color
i_base,
i_br,
i_bl,
i_tr,
i_tl,
// outgoing color
o_c
);
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_vi; // 25MHz
// configuration
input i_fb_blend_en;
// incoming color
input [7:0] i_base; // 7.1 or 8.0
input [7:0] i_br; // 5.3
input [7:0] i_bl; // 5.3
input [7:0] i_tr; // 5.3 or 8.0
input [7:0] i_tl; // 5.3
// outgoing color
output [7:0] o_c;
//////////////////////////////////
// reg
//////////////////////////////////
//reg [7:0] r_c;
//////////////////////////////////
// wire
//////////////////////////////////
wire [8:0] w_b; // intermediate 6.3
wire [8:0] w_t; // intermediate 6.3
wire [9:0] w_m; // intermediate 7.3
wire [10:0] w_f; // intermediate 8.3
wire [8:0] w_ff; // intermediate 9.0
wire [7:0] w_r; // rounded final color
// for buffer blend function
wire [8:0] w_ff_a; // intermediate 9.0
wire [8:0] w_ff_b; // intermediate 9.0
//////////////////////////////////
// assign
//////////////////////////////////
assign w_b = i_br + i_bl; // 6.3
assign w_t = i_tr + i_tl; // 6.3
assign w_m = w_b + w_t; // 7.3
assign w_f = w_m + {i_base,2'b00}; // 8.3
assign w_ff_a = (w_f[2]) ? w_f[10:3] : w_f[10:3] + 1'b1; // 9.0 for aa
assign w_ff_b = i_base + i_tr; // 9.0 for blend
assign w_ff = (!i_fb_blend_en) ? w_ff_a : w_ff_b;
assign w_r = (w_ff[8]) ? 8'hff : w_ff[7:0];
// assign o_c = r_c;
assign o_c = w_r;
//////////////////////////////////
// always
//////////////////////////////////
/*
always @(posedge clk_vi) begin
r_c = w_r;
end
*/
endmodule
|
module fm_axi_s (
// system
clk_core,
rst_x,
// AXI write port
i_awid_s,
i_awaddr_s,
i_awlen_s,
i_awsize_s,
i_awburst_s,
i_awlock_s,
i_awcache_s,
i_awprot_s,
i_awvalid_s,
o_awready_s,
i_wid_s,
i_wdata_s,
i_wstrb_s,
i_wlast_s,
i_wvalid_s,
o_wready_s,
o_bid_s,
o_bresp_s,
o_bvalid_s,
i_bready_s,
// AXI read port
i_arid_s,
i_araddr_s,
i_arlen_s,
i_arsize_s,
i_arburst_s,
i_arlock_s,
i_arcache_s,
i_arprot_s,
i_arvalid_s,
o_arready_s,
o_rid_s,
o_rdata_s,
o_rresp_s,
o_rlast_s,
o_rvalid_s,
i_rready_s,
// internal bus
o_req,
o_wr,
o_adrs,
i_ack,
o_be,
o_wd,
i_rstr,
i_rd
);
`include "polyphony_axi_def.v"
//////////////////////////////////
// I/O port definition
//////////////////////////////////
// system
input clk_core;
input rst_x;
// AXI Slave
// write port
input [P_AXI_S_AWID-1:0] i_awid_s;
input [P_AXI_S_AWADDR-1:0] i_awaddr_s;
input [P_AXI_S_AWLEN-1:0] i_awlen_s;
input [P_AXI_S_AWSIZE-1:0] i_awsize_s;
input [P_AXI_S_AWBURST-1:0] i_awburst_s;
input [P_AXI_S_AWLOCK-1:0] i_awlock_s;
input [P_AXI_S_AWCACHE-1:0] i_awcache_s;
input [P_AXI_S_AWPROT-1:0] i_awprot_s;
input i_awvalid_s;
output o_awready_s;
input [P_AXI_S_WID-1:0] i_wid_s;
input [P_AXI_S_WDATA-1:0] i_wdata_s;
input [P_AXI_S_WSTRB-1:0] i_wstrb_s;
input i_wlast_s;
input i_wvalid_s;
output o_wready_s;
output [P_AXI_S_BID-1:0] o_bid_s;
output [P_AXI_S_BRESP-1:0] o_bresp_s;
output o_bvalid_s;
input i_bready_s;
// read port
input [P_AXI_S_ARID-1:0] i_arid_s;
input [P_AXI_S_ARADDR-1:0] i_araddr_s;
input [P_AXI_S_ARLEN-1:0] i_arlen_s;
input [P_AXI_S_ARSIZE-1:0] i_arsize_s;
input [P_AXI_S_ARBURST-1:0] i_arburst_s;
input [P_AXI_S_ARLOCK-1:0] i_arlock_s;
input [P_AXI_S_ARCACHE-1:0] i_arcache_s;
input [P_AXI_S_ARPROT-1:0] i_arprot_s;
input i_arvalid_s;
output o_arready_s;
// read response
output [P_AXI_S_RID-1:0] o_rid_s;
output [P_AXI_S_RDATA-1:0] o_rdata_s;
output [P_AXI_S_RRESP-1:0] o_rresp_s;
output o_rlast_s;
output o_rvalid_s;
input i_rready_s;
// internal side
output o_req;
output o_wr;
output [23:0] o_adrs;
input i_ack;
output [3:0] o_be;
output [31:0] o_wd;
input i_rstr;
input [31:0] i_rd;
//////////////////////////////////
// parameter definition
//////////////////////////////////
localparam P_IDLE = 'd0;
localparam P_WRITE_CMD = 'd1;
localparam P_READ_CMD = 'd2;
localparam P_READ_DT = 'd3;
localparam P_WC_FIFO_W = P_AXI_S_AWID +
P_AXI_S_AWADDR +
P_AXI_S_AWLEN +
P_AXI_S_AWSIZE +
P_AXI_S_AWBURST +
P_AXI_S_AWLOCK +
P_AXI_S_AWCACHE +
P_AXI_S_AWPROT;
localparam P_WD_FIFO_W = P_AXI_S_WID +
P_AXI_S_WDATA +
P_AXI_S_WSTRB + 1;
localparam P_WR_FIFO_W = P_AXI_S_BID +
P_AXI_S_BRESP;
localparam P_RC_FIFO_W = P_AXI_S_ARID +
P_AXI_S_ARADDR +
P_AXI_S_ARLEN +
P_AXI_S_ARSIZE +
P_AXI_S_ARBURST +
P_AXI_S_ARLOCK +
P_AXI_S_ARCACHE +
P_AXI_S_ARPROT;
localparam P_RR_FIFO_W = P_AXI_S_RID +
P_AXI_S_RDATA +
P_AXI_S_RRESP + 1;
//////////////////////////////////
// reg
//////////////////////////////////
reg [1:0] r_state;
reg [P_AXI_S_ARID-1:0] r_arid_s;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_w_access;
wire w_r_access;
// write command
wire [P_AXI_S_AWID-1:0] w_awid_s;
wire [P_AXI_S_AWADDR-1:0] w_awaddr_s;
wire [P_AXI_S_AWLEN-1:0] w_awlen_s;
wire [P_AXI_S_AWSIZE-1:0] w_awsize_s;
wire [P_AXI_S_AWBURST-1:0] w_awburst_s;
wire [P_AXI_S_AWLOCK-1:0] w_awlock_s;
wire [P_AXI_S_AWCACHE-1:0] w_awcache_s;
wire [P_AXI_S_AWPROT-1:0] w_awprot_s;
wire [P_WC_FIFO_W-1:0] w_wc_fifo_in;
wire [P_WC_FIFO_W-1:0] w_wc_fifo_out;
wire w_wc_full;
wire w_wc_empty;
wire w_wc_ren;
// write data
wire [P_AXI_S_WID-1:0] w_wid_s;
wire [P_AXI_S_WDATA-1:0] w_wdata_s;
wire [P_AXI_S_WSTRB-1:0] w_wstrb_s;
wire w_wlast_s;
wire [P_WD_FIFO_W-1:0] w_wd_fifo_in;
wire [P_WD_FIFO_W-1:0] w_wd_fifo_out;
wire w_wd_full;
wire w_wd_empty;
wire w_wd_ren;
// write response
wire [P_AXI_S_BID-1:0] w_bid_s;
wire [P_AXI_S_BRESP-1:0] w_bresp_s;
wire [P_WR_FIFO_W-1:0] w_wr_fifo_in;
wire [P_WR_FIFO_W-1:0] w_wr_fifo_out;
wire w_wr_full;
wire w_wr_empty;
wire w_wr_ren;
// read command
wire [P_AXI_S_ARID-1:0] w_arid_s;
wire [P_AXI_S_ARADDR-1:0] w_araddr_s;
wire [P_AXI_S_ARLEN-1:0] w_arlen_s;
wire [P_AXI_S_ARSIZE-1:0] w_arsize_s;
wire [P_AXI_S_ARBURST-1:0] w_arburst_s;
wire [P_AXI_S_ARLOCK-1:0] w_arlock_s;
wire [P_AXI_S_ARCACHE-1:0] w_arcache_s;
wire [P_AXI_S_ARPROT-1:0] w_arprot_s;
wire [P_RC_FIFO_W-1:0] w_rc_fifo_in;
wire [P_RC_FIFO_W-1:0] w_rc_fifo_out;
wire w_rc_full;
wire w_rc_empty;
wire w_rc_ren;
// read response
wire [P_AXI_S_RID-1:0] w_rid_s;
wire [P_AXI_S_RDATA-1:0] w_rdata_s;
wire [P_AXI_S_RRESP-1:0] w_rresp_s;
wire w_rlast_s;
wire [P_RR_FIFO_W-1:0] w_rr_fifo_in;
wire [P_RR_FIFO_W-1:0] w_rr_fifo_out;
wire w_rr_full;
wire w_rr_empty;
wire w_rr_ren;
//////////////////////////////////
// assign
//////////////////////////////////
assign o_awready_s = ~w_wc_full;
assign w_wc_fifo_in = {
i_awid_s,
i_awaddr_s,
i_awlen_s,
i_awsize_s,
i_awburst_s,
i_awlock_s,
i_awcache_s,
i_awprot_s
};
assign {
w_awid_s,
w_awaddr_s,
w_awlen_s,
w_awsize_s,
w_awburst_s,
w_awlock_s,
w_awcache_s,
w_awprot_s
} = w_wc_fifo_out;
assign o_wready_s = ~w_wd_full;
assign w_wd_fifo_in = {
i_wid_s,
i_wdata_s,
i_wstrb_s,
i_wlast_s};
assign {
w_wid_s,
w_wdata_s,
w_wstrb_s,
w_wlast_s} = w_wd_fifo_out;
assign w_bid_s = w_awid_s;
assign w_bresp_s = {P_AXI_S_BRESP{1'b0}};
assign w_wr_fifo_in = {
w_bid_s,
w_bresp_s};
assign {
o_bid_s,
o_bresp_s} = w_wr_fifo_out;
assign o_bvalid_s = !w_wr_empty;
assign w_rc_fifo_in = {
i_arid_s,
i_araddr_s,
i_arlen_s,
i_arsize_s,
i_arburst_s,
i_arlock_s,
i_arcache_s,
i_arprot_s};
assign o_arready_s = ~w_rc_full;
assign {
w_arid_s,
w_araddr_s,
w_arlen_s,
w_arsize_s,
w_arburst_s,
w_arlock_s,
w_arcache_s,
w_arprot_s} = w_rc_fifo_out;
assign {
o_rid_s,
o_rdata_s,
o_rresp_s,
o_rlast_s} = w_rr_fifo_out;
assign w_rresp_s = {P_AXI_S_RRESP{1'b0}};
assign w_rlast_s = 1'b1;
assign w_rr_fifo_in = {
r_arid_s,
i_rd,
w_rresp_s,
w_rlast_s};
assign o_rvalid_s = !w_rr_empty;
assign w_w_access = !w_wc_empty & !w_wd_empty;
assign w_r_access = !w_rc_empty;
assign w_wc_ren = (r_state == P_WRITE_CMD) & i_ack;
assign w_wd_ren = (r_state == P_WRITE_CMD) & i_ack;
assign w_rc_ren = (r_state == P_READ_CMD) & i_ack;
assign o_req = (r_state == P_WRITE_CMD) | (r_state == P_READ_CMD);
assign o_wr = (r_state == P_WRITE_CMD);
assign o_adrs = (r_state == P_WRITE_CMD) ? w_awaddr_s[23:0] : w_araddr_s[23:0];
assign o_be = w_wstrb_s;
assign o_wd = w_wdata_s;
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core) begin
if ((r_state == P_IDLE) & w_r_access) r_arid_s <= w_arid_s;
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE : begin
if (w_w_access) r_state <= P_WRITE_CMD;
else if (w_r_access) r_state <= P_READ_CMD;
end
P_WRITE_CMD : begin
if (i_ack) r_state <= P_IDLE;
end
P_READ_CMD : begin
if (i_ack) begin
if (i_rstr) r_state <= P_IDLE;
else r_state <= P_READ_DT;
end
end
P_READ_DT : begin
if (i_rstr) r_state <= P_IDLE;
end
endcase
end
end
//////////////////////////////////
// module instance
//////////////////////////////////
// AXI write command
fm_fifo #(P_WC_FIFO_W) u_wc_fifo (
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(i_awvalid_s),
.i_dt(w_wc_fifo_in),
.o_full(w_wc_full),
.i_renable(w_wc_ren),
.o_dt(w_wc_fifo_out),
.o_empty(w_wc_empty),
.o_dnum()
);
// AXI write data
fm_fifo #(P_WD_FIFO_W) u_wd_fifo (
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(i_wvalid_s),
.i_dt(w_wd_fifo_in),
.o_full(w_wd_full),
.i_renable(w_wd_ren),
.o_dt(w_wd_fifo_out),
.o_empty(w_wd_empty),
.o_dnum()
);
// AXI write response
fm_fifo #(P_WR_FIFO_W) u_wr_fifo (
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(w_wd_ren),
.i_dt(w_wr_fifo_in),
.o_full(w_wr_full),
.i_renable(i_bready_s),
.o_dt(w_wr_fifo_out),
.o_empty(w_wr_empty),
.o_dnum()
);
// AXI read command
fm_fifo #(P_RC_FIFO_W) u_rc_fifo (
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(i_arvalid_s),
.i_dt(w_rc_fifo_in),
.o_full(w_rc_full),
.i_renable(w_rc_ren),
.o_dt(w_rc_fifo_out),
.o_empty(w_rc_empty),
.o_dnum()
);
// AXI read data
fm_fifo #(P_RR_FIFO_W) u_rr_fifo (
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(i_rstr),
.i_dt(w_rr_fifo_in),
.o_full(w_rr_full),
.i_renable(i_rready_s),
.o_dt(w_rr_fifo_out),
.o_empty(w_rr_empty),
.o_dnum()
);
endmodule
|
module const_mult
(
Clock,
ClockEnable,
Reset,
Color,
Color_Out
);
parameter IN_SIZE = 8;
parameter OUT_SIZE = 16; // output size width (integer)
parameter CST_MULT = 66; // constant multiplicand (integer)
input Clock;
input ClockEnable;
input Reset;
input [ (IN_SIZE - 1):0] Color;
output[(OUT_SIZE - 1):0] Color_Out;
reg [(OUT_SIZE - 1):0] Color_Out;
// ------------------------------
// RTL code for COLOR_KCM process
// ------------------------------
always @(posedge Clock or posedge Reset)
begin : COLOR_KCM
if (Reset)
Color_Out <= 0;
else if (ClockEnable)
Color_Out <= CST_MULT * Color;
end
endmodule
|
module fm_hdmi (
clk_v,
rst_x,
// video in
i_vsync,
i_hsync,
i_de,
i_cr,
i_cg,
i_cb,
// video out
o_hd_vsync,
o_hd_hsync,
o_hd_de,
o_hd_d
);
input clk_v;
input rst_x;
// video in
input i_vsync;
input i_hsync;
input i_de;
input [7:0] i_cr;
input [7:0] i_cg;
input [7:0] i_cb;
// video out
output o_hd_vsync;
output o_hd_hsync;
output o_hd_de;
output [15:0] o_hd_d;
//////////////////////////////////
// wire
//////////////////////////////////
wire [7:0] w_y;
wire [7:0] w_cb;
wire [7:0] w_cr;
wire w_de;
wire [7:0] w_y_422;
wire [7:0] w_cb_422;
wire [7:0] w_cr_422;
wire w_de_422;
wire [15:0] w_d;
wire w_hsync_rise;
//////////////////////////////////
// reg
//////////////////////////////////
reg [7:0] r_cr_1z;
reg r_state;
reg [15:0] r_d;
reg r_de;
reg r_hsync_1z;
`ifdef PP_HDMI_NEG_OUT
wire w_hd_vsync;
wire w_hd_hsync;
wire w_hd_de;
wire [15:0] w_hd_d;
// video out
reg r_hd_vsync_neg;
reg r_hd_hsync_neg;
reg r_hd_de_neg;
reg [15:0] r_hd_d_neg;
`endif
//////////////////////////////////
// assign
//////////////////////////////////
assign w_hsync_rise = (!r_hsync_1z) & i_hsync;
assign w_d = (r_state) ? {w_y_422,r_cr_1z} : // 2nd
{w_y_422,w_cb_422}; // 1st
`ifdef PP_HDMI_NEG_OUT
assign o_hd_vsync = r_hd_vsync_neg;
assign o_hd_hsync = r_hd_hsync_neg;
assign o_hd_d = r_hd_d_neg;
assign o_hd_de = r_hd_de_neg;
`else
assign o_hd_d = r_d;
assign o_hd_de = r_de;
`endif
//////////////////////////////////
// module instantiation
//////////////////////////////////
fm_vout_delay #(1,5) u_delay_de (
.i_in(i_de),
.o_out(w_de),
.clk_sys(clk_v),
.rst_x(rst_x)
);
fm_vout_delay #(1,2) u_delay_de_422 (
.i_in(w_de),
.o_out(w_de_422),
.clk_sys(clk_v),
.rst_x(rst_x)
);
// RGB-> YCrCb conversion
fm_ycbcr u_ycbcr ( // 5 clock
.clk_v(clk_v),
.rst_x(rst_x),
.i_r(i_cr),
.i_g(i_cg),
.i_b(i_cb),
.o_y(w_y),
.o_cb(w_cb),
.o_cr(w_cr)
);
// 4:4:4 -> 4:2:2
fm_444_422 u_444_422 (
.clk_v(clk_v),
.rst_x(rst_x),
// video in
.i_state(r_state),
.i_y(w_y),
.i_cr(w_cr),
.i_cb(w_cb),
// video out
.o_y(w_y_422),
.o_cr(w_cr_422),
.o_cb(w_cb_422)
);
fm_vout_delay #(1,8) u_delay_vs (
.i_in(i_vsync),
`ifdef PP_HDMI_NEG_OUT
.o_out(w_hd_vsync),
`else
.o_out(o_hd_vsync),
`endif
.clk_sys(clk_v),
.rst_x(rst_x)
);
fm_vout_delay #(1,8) u_delay_hs (
.i_in(i_hsync),
`ifdef PP_HDMI_NEG_OUT
.o_out(w_hd_hsync),
`else
.o_out(o_hd_hsync),
`endif
.clk_sys(clk_v),
.rst_x(rst_x)
);
always @(posedge clk_v or negedge rst_x) begin
if (~rst_x) begin
r_state <= 1'b0;
r_hsync_1z <= 1'b0;
end else begin
r_hsync_1z <= i_hsync;
if (w_hsync_rise) r_state <= 1'b0;
else if (w_de) r_state <= ~r_state;
end
end
always @(posedge clk_v or negedge rst_x) begin
if (~rst_x) begin
r_de <= 1'b0;
end else begin
r_de <= w_de_422;
end
end
always @(posedge clk_v) begin
r_cr_1z <= w_cr_422;
r_d <= w_d;
end
`ifdef PP_HDMI_NEG_OUT
always @(posedge clk_v or negedge rst_x) begin
if (~rst_x) begin
r_hd_vsync_neg <= 1'b1;
r_hd_hsync_neg <= 1'b1;
r_hd_de_neg <= 1'b0;
end else begin
r_hd_vsync_neg <= w_hd_vsync;
r_hd_hsync_neg <= w_hd_hsync;
r_hd_de_neg <= r_de;
end
end
always @(negedge clk_v) begin
r_hd_d_neg <= r_d;
end
`endif
endmodule
|
module fm_ycbcr(
clk_v,
rst_x,
i_r,
i_g,
i_b,
o_y,
o_cb,
o_cr
);
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_v; // 27MHz
input rst_x;
input [7:0] i_r;
input [7:0] i_g;
input [7:0] i_b;
output [7:0] o_y;
output [7:0] o_cb;
output [7:0] o_cr;
//////////////////////////////////
// module instantiation
//////////////////////////////////
csc_top csc_top (
.Clock(clk_v),
.ClockEnable(1'b1),
.Reset(~rst_x),
.Red(i_r),
.Green(i_g),
.Blue(i_b),
.Y(o_y),
.Cb(o_cb),
.Cr(o_cr)
);
endmodule
|
module fm_444_422 (
clk_v,
rst_x,
// video in
i_state,
i_y,
i_cr,
i_cb,
// video out
o_y,
o_cr,
o_cb
);
input clk_v;
input rst_x;
input i_state;
// video in
input [7:0] i_y;
input [7:0] i_cr;
input [7:0] i_cb;
// video out
output [7:0] o_y;
output [7:0] o_cr;
output [7:0] o_cb;
//////////////////////////////////
// wire
//////////////////////////////////
wire [8:0] w_cb;
wire [8:0] w_cr;
//////////////////////////////////
// reg
//////////////////////////////////
reg [7:0] r_y_1z;
reg [7:0] r_y_2z;
reg [7:0] r_cr_1z;
reg [7:0] r_cb_1z;
reg [7:0] r_cr;
reg [7:0] r_cb;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_cr = i_cr + r_cr_1z;
assign w_cb = i_cb + r_cb_1z;
assign o_y = r_y_2z;
assign o_cr = r_cr;
assign o_cb = r_cb;
//////////////////////////////////
// module instantiation
//////////////////////////////////
always @(posedge clk_v) begin
r_y_1z <= i_y;
r_y_2z <= r_y_1z;
r_cr_1z <= i_cr;
r_cb_1z <= i_cb;
if (i_state) begin
r_cr <= w_cr[8:1];
r_cb <= w_cb[8:1];
end
end
endmodule
|
module csc_top
(
Clock,
ClockEnable,
Reset,
Red,
Green,
Blue,
Y,
Cb,
Cr
);
parameter TOP_OUT_SIZE = 8; // uncomment to get 8-bit input & output...
// parameter TOP_OUT_SIZE = 10; // uncomment to get 10-bit input & output...
input Clock;
input ClockEnable;
input Reset;
input [(TOP_OUT_SIZE - 1):0] Red;
input [(TOP_OUT_SIZE - 1):0] Green;
input [(TOP_OUT_SIZE - 1):0] Blue;
output [(TOP_OUT_SIZE - 1):0] Y;
output [(TOP_OUT_SIZE - 1):0] Cb;
output [(TOP_OUT_SIZE - 1):0] Cr;
reg [(TOP_OUT_SIZE - 1):0] Y;
reg [(TOP_OUT_SIZE - 1):0] Cb;
reg [(TOP_OUT_SIZE - 1):0] Cr;
// Define internal signals
reg [(TOP_OUT_SIZE - 1):0] R;
reg [(TOP_OUT_SIZE - 1):0] G;
reg [(TOP_OUT_SIZE - 1):0] B;
wire [(TOP_OUT_SIZE - 1):0] Y_sig;
wire [(TOP_OUT_SIZE - 1):0] Cb_sig;
wire [(TOP_OUT_SIZE - 1):0] Cr_sig;
// Input registers (should be pushed into IOBs)
always @(posedge Clock or posedge Reset)
begin : In_Reg
if (Reset)
begin
R <= 0;
G <= 0;
B <= 0;
end
else if (ClockEnable)
begin
R <= Red ;
G <= Green ;
B <= Blue ;
end
end
// Output registers (should be pushed into IOBs)
always @(posedge Clock or posedge Reset)
begin : Out_Reg
if (Reset)
begin
Y <= 0;
Cb <= 0;
Cr <= 0;
end
else if (ClockEnable)
begin
Y <= Y_sig ;
Cb <= Cb_sig ;
Cr <= Cr_sig ;
end
end
// CSC instantiation
csc #(TOP_OUT_SIZE) CSC_module
(
.Clock(Clock),
.ClockEnable(ClockEnable),
.Reset(Reset),
.R(R),
.G(G),
.B(B),
.Y(Y_sig),
.Cb(Cb_sig),
.Cr(Cr_sig)
);
endmodule
|
module csc
(
Clock,
ClockEnable,
Reset,
R,
G,
B,
Y,
Cb,
Cr
);
parameter OUT_SIZE = 8; // uncomment to get 8-bit input & output...
// parameter OUT_SIZE = 10; // uncomment to get 10-bit input & output...
input Clock;
input ClockEnable;
input Reset;
input [(OUT_SIZE - 1):0] R;
input [(OUT_SIZE - 1):0] G;
input [(OUT_SIZE - 1):0] B;
output [(OUT_SIZE - 1):0] Y;
output [(OUT_SIZE - 1):0] Cb;
output [(OUT_SIZE - 1):0] Cr;
reg [(OUT_SIZE - 1):0] Y;
reg [(OUT_SIZE - 1):0] Cb;
reg [(OUT_SIZE - 1):0] Cr;
// Constants and precision for each coefficients...
//
//-- 8-bit for Y601, Cb and Cr...
//parameter CST_Y601_red = 66;
//parameter CST_Y601_green = 129;
//parameter CST_Y601_blue = 25;
//parameter CST_Y601_Prec = 8; -- 8-bit (256)
//--
//parameter CST_Cb_red = 38;
//parameter CST_Cb_green = 74;
//parameter CST_Cb_blue = 112;
//parameter CST_Cb_Prec = 8; -- 8-bit (256)
//--
//parameter CST_Cr_red = 112;
//parameter CST_Cr_green = 94;
//parameter CST_Cr_blue = 18;
//parameter CST_Cr_Prec = 8; -- 8-bit (256)
//
//-- 9-bit for Y601, Cb and Cr...
//parameter CST_Y601_red = 132;
//parameter CST_Y601_green = 258;
//parameter CST_Y601_blue = 50;
//parameter CST_Y601_Prec = 9; -- 9-bit (512)
//--
//parameter CST_Cb_red = 76;
//parameter CST_Cb_green = 149;
//parameter CST_Cb_blue = 225;
//parameter CST_Cb_Prec = 9; -- 9-bit (512)
//--
//parameter CST_Cr_red = 225;
//parameter CST_Cr_green = 188;
//parameter CST_Cr_blue = 36;
//parameter CST_Cr_Prec = 9; -- 9-bit (512)
//
//-- 10-bit for Y601, Cb and Cr...
//parameter CST_Y601_red = 263;
//parameter CST_Y601_green = 516;
//parameter CST_Y601_blue = 100;
//parameter CST_Y601_Prec = 10; -- 10-bit (1024)
//--
//parameter CST_Cb_red = 152;
//parameter CST_Cb_green = 298;
//parameter CST_Cb_blue = 450;
//parameter CST_Cb_Prec = 10; -- 10-bit (1024)
//--
parameter CST_Cr_red = 450;
parameter CST_Cr_green = 377;
parameter CST_Cr_blue = 73;
parameter CST_Cr_Prec = 10; // 10-bit (1024)
//
//-- 11-bit for Y601, Cb and Cr...
//parameter CST_Y601_red = 526;
//parameter CST_Y601_green = 1032;
//parameter CST_Y601_blue = 201;
//parameter CST_Y601_Prec = 11; -- 11-bit (2048)
//--
parameter CST_Cb_red = 303;
parameter CST_Cb_green = 596;
parameter CST_Cb_blue = 899;
parameter CST_Cb_Prec = 11; // 11-bit (2048)
//--
//parameter CST_Cr_red = 899;
//parameter CST_Cr_green = 754;
//parameter CST_Cr_blue = 145;
//parameter CST_Cr_Prec = 11; -- 11-bit (2048)
//
//--12-bit for Y601, Cb and Cr...
//parameter CST_Y601_red = 1053;
//parameter CST_Y601_green = 2064;
//parameter CST_Y601_blue = 401;
//parameter CST_Y601_Prec = 12; -- 12-bit (4096)
//--
//parameter CST_Cb_red = 606;
//parameter CST_Cb_green = 1192;
//parameter CST_Cb_blue = 1798;
//parameter CST_Cb_Prec = 12; -- 12-bit (4096)
//--
//parameter CST_Cr_red = 1798;
//parameter CST_Cr_green = 1507;
//parameter CST_Cr_blue = 291;
//parameter CST_Cr_Prec = 12; -- 12-bit (4096)
//
//-- 13-bit for Y601, Cb and Cr...
parameter CST_Y601_red = 2105;
parameter CST_Y601_green = 4129;
parameter CST_Y601_blue = 803;
parameter CST_Y601_Prec = 13; // 13-bit (8192)
//--
//parameter CST_Cb_red = 1212;
//parameter CST_Cb_green = 2384;
//parameter CST_Cb_blue = 3596;
//parameter CST_Cb_Prec = 13; -- 13-bit (8192)
//--
//parameter CST_Cr_red = 3596;
//parameter CST_Cr_green = 3015;
//parameter CST_Cr_blue = 582;
//parameter CST_Cr_Prec = 13; -- 13-bit (8192)
//
//
//
// Combined constants...
parameter CST_Y601_OutSize = CST_Y601_Prec + OUT_SIZE;
parameter CST_Cb_OutSize = CST_Cb_Prec + OUT_SIZE;
parameter CST_Cr_OutSize = CST_Cr_Prec + OUT_SIZE;
// Takes care of offset for 8- and 10-bit input/output entity
parameter CST_Offset_Y601 = ( ( 33 << (OUT_SIZE - 8) ) << (CST_Y601_Prec - 1) ); // ( 16 + 0.5 ) * 2 * 2^(CST_Y601_Prec-1)
parameter CST_Offset_Cb = ( (257 << (OUT_SIZE - 8) ) << ( CST_Cb_Prec - 1) ); // ( 128 + 0.5 ) * 2 * 2^(CST_Cb_Prec-1)
parameter CST_Offset_Cr = ( (257 << (OUT_SIZE - 8) ) << ( CST_Cr_Prec - 1) ); // ( 128 + 0.5 ) * 2 * 2^(CST_Cr_Prec-1)
//
//
// Component Declarations
// Constant multipliers Y601, Cb and Cr components...
// Define internal signals
wire [(CST_Y601_OutSize - 1):0] Y_R_KCM;
wire [(CST_Y601_OutSize - 1):0] Y_G_KCM;
wire [(CST_Y601_OutSize - 1):0] Y_B_KCM;
wire [ (CST_Cb_OutSize - 1):0] Cb_R_KCM;
wire [ (CST_Cb_OutSize - 1):0] Cb_G_KCM;
wire [ (CST_Cb_OutSize - 1):0] Cb_B_KCM;
wire [ (CST_Cr_OutSize - 1):0] Cr_R_KCM;
wire [ (CST_Cr_OutSize - 1):0] Cr_G_KCM;
wire [ (CST_Cr_OutSize - 1):0] Cr_B_KCM;
//
reg [ (CST_Y601_OutSize - 1):0] Y_cst_G;
reg [ (CST_Cb_OutSize - 1):0] Cb_cst_B;
reg [ (CST_Cr_OutSize - 1):0] Cr_cst_R;
//
reg [(CST_Y601_OutSize - 1):0] Y_Red_Blue;
reg [(CST_Y601_OutSize - 1):0] Y601_full;
reg [ (CST_Cb_OutSize - 1):0] Cb_Red_Green;
reg [ (CST_Cb_OutSize - 1):0] Cb_full;
reg [ (CST_Cr_OutSize - 1):0] Cr_Green_Blue;
reg [ (CST_Cr_OutSize - 1):0] Cr_full;
// ---------------------------------
// Compute the Y601 component...
// ---------------------------------
const_mult #(OUT_SIZE, CST_Y601_OutSize, CST_Y601_red) Y601_KCM_red(.Clock(Clock), .ClockEnable(ClockEnable), .Reset(Reset), .Color(R), .Color_Out(Y_R_KCM));
const_mult #(OUT_SIZE, CST_Y601_OutSize, CST_Y601_green) Y601_KCM_green(.Clock(Clock), .ClockEnable(ClockEnable), .Reset(Reset), .Color(G), .Color_Out(Y_G_KCM));
const_mult #(OUT_SIZE, CST_Y601_OutSize, CST_Y601_blue) Y601_KCM_blue(.Clock(Clock), .ClockEnable(ClockEnable), .Reset(Reset), .Color(B), .Color_Out(Y_B_KCM));
// Adder for (G + constant), where constant "16" is scaled up by Y601 coefficient precision
// Constant is also modified to perform rounding (+0.5)
always @(posedge Clock or posedge Reset)
begin : CST_Green_Adder
if (Reset)
Y_cst_G <= 0;
else if (ClockEnable)
Y_cst_G <= Y_G_KCM + CST_Offset_Y601; // add 16.5 (scaled up by coefficient precision)
end
// Adder for (R + B)
always @(posedge Clock or posedge Reset)
begin : Y_Red_Blue_Adder
if (Reset)
Y_Red_Blue <= 0;
else if (ClockEnable)
Y_Red_Blue <= Y_R_KCM + Y_B_KCM;
end
// Adder for Y601 => (R + B) + (G + constant), where constant "16.5" is scaled up by coefficient precision
always @(posedge Clock or posedge Reset)
begin : Y601_Adder
if (Reset)
Y601_full <= 0;
else if (ClockEnable)
Y601_full <= Y_Red_Blue + Y_cst_G;
end
// ---------------------------------
// Compute the Cb component...
// ---------------------------------
const_mult #(OUT_SIZE, CST_Cb_OutSize, CST_Cb_red) Cb_KCM_red(.Clock(Clock), .ClockEnable(ClockEnable), .Reset(Reset), .Color(R), .Color_Out(Cb_R_KCM));
const_mult #(OUT_SIZE, CST_Cb_OutSize, CST_Cb_green) Cb_KCM_green(.Clock(Clock), .ClockEnable(ClockEnable), .Reset(Reset), .Color(G), .Color_Out(Cb_G_KCM));
const_mult #(OUT_SIZE, CST_Cb_OutSize, CST_Cb_blue) Cb_KCM_blue(.Clock(Clock), .ClockEnable(ClockEnable), .Reset(Reset), .Color(B), .Color_Out(Cb_B_KCM));
// Adder for (B + constant), where constant "128" is scaled up by Cb coefficient precision
// Constant is also modified to perform rounding (+0.5)
always @(posedge Clock or posedge Reset)
begin : CST_Blue_Adder
if (Reset)
Cb_cst_B <= 0;
else if (ClockEnable)
Cb_cst_B <= Cb_B_KCM + CST_Offset_Cb; // add 128.5 (scaled up by coefficient precision)
end
// Adder for R + G
always @(posedge Clock or posedge Reset)
begin : Cb_Red_Green_Adder
if (Reset)
Cb_Red_Green <= 0;
else if (ClockEnable)
Cb_Red_Green <= Cb_R_KCM + Cb_G_KCM;
end
// Subtractor for Cb => (B + constant) - (R + G), where constant "128.5" is scaled up by coefficient precision
always @(posedge Clock or posedge Reset)
begin : Cb_Subt
if (Reset)
Cb_full <= 0;
else if (ClockEnable)
Cb_full <= Cb_cst_B - Cb_Red_Green;
end
// ---------------------------------
// Compute the Cr component...
// ---------------------------------
const_mult #(OUT_SIZE, CST_Cr_OutSize, CST_Cr_red) Cr_KCM_red(.Clock(Clock), .ClockEnable(ClockEnable), .Reset(Reset), .Color(R), .Color_Out(Cr_R_KCM));
const_mult #(OUT_SIZE, CST_Cr_OutSize, CST_Cr_green) Cr_KCM_green(.Clock(Clock), .ClockEnable(ClockEnable), .Reset(Reset), .Color(G), .Color_Out(Cr_G_KCM));
const_mult #(OUT_SIZE, CST_Cr_OutSize, CST_Cr_blue) Cr_KCM_blue(.Clock(Clock), .ClockEnable(ClockEnable), .Reset(Reset), .Color(B), .Color_Out(Cr_B_KCM));
// Adder for (R + constant), where constant "128" is scaled up by Cr coefficient precision
// Constant is also modified to perform rounding (+0.5)
always @(posedge Clock or posedge Reset)
begin : CST_Red_Adder
if (Reset)
Cr_cst_R <= 0;
else if (ClockEnable)
Cr_cst_R <= Cr_R_KCM + CST_Offset_Cr; // add 128.5 (scaled up by coefficient precision)
end
// Adder for G + B
always @(posedge Clock or posedge Reset)
begin : Cr_Green_Blue_Adder
if (Reset)
Cr_Green_Blue <= 0;
else if (ClockEnable)
Cr_Green_Blue <= Cr_G_KCM + Cr_B_KCM;
end
// Subtractor for Cr => (R + constant) - (G + B), where constant "128.5" is scaled up by coefficient precision
always @(posedge Clock or posedge Reset)
begin : Cr_Subt
if (Reset)
Cr_full <= 0;
else if (ClockEnable)
Cr_full <= Cr_cst_R - Cr_Green_Blue;
end
// Limit and rounding: discard unwanted precision bits
// Rounding already computed in result...
always @(Y601_full or Cb_full or Cr_full)
begin
Y = Y601_full [(CST_Y601_OutSize - 1):(CST_Y601_OutSize - OUT_SIZE)] ; // divide by 2^(CST_Y601_OutSize-8)...
Cb = Cb_full [ (CST_Cb_OutSize - 1): (CST_Cb_OutSize - OUT_SIZE)] ; // divide by 2^(CST_Cb_OutSize-8)...
Cr = Cr_full [ (CST_Cr_OutSize - 1): (CST_Cr_OutSize - OUT_SIZE)] ; // divide by 2^(CST_Cr_OutSize-8)...
end
endmodule
|
module fm_vout_delay (
i_in,
o_out,
clk_sys,
rst_x
);
parameter P_WIDTH = 4;
// P_NUM_DELAY should be greater than 1
parameter P_NUM_DELAY = 6;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input [P_WIDTH-1:0] i_in;
output [P_WIDTH-1:0] o_out;
input clk_sys;
input rst_x;
//////////////////////////////////
// regs
//////////////////////////////////
reg [P_WIDTH-1:0] r_delay[0:P_NUM_DELAY-1];
//////////////////////////////////
// assign statement
//////////////////////////////////
assign o_out = r_delay[P_NUM_DELAY-1];
//////////////////////////////////
// always statement
//////////////////////////////////
always @(posedge clk_sys or negedge rst_x) begin
if (~rst_x) begin
r_delay[0] <= {P_WIDTH{1'b0}};
end else begin
r_delay[0] <= i_in;
end
end
// delay register connection
integer i;
always @(posedge clk_sys or negedge rst_x) begin
if (~rst_x) begin
for ( i = 1; i < P_NUM_DELAY; i = i + 1) begin
r_delay[i] <= {P_WIDTH{1'b0}};
end
end else begin
for ( i = 1; i < P_NUM_DELAY; i = i + 1) begin
r_delay[i] <= r_delay[i-1];
end
end
end
endmodule
|
module fm_dispatch (
clk_core,
rst_x,
// local interface
i_req,
i_wr,
i_adrs,
o_ack,
i_be,
i_wd,
o_rstr,
o_rd,
// internal side
o_req_sys,
o_req_3d,
o_wr,
o_adrs,
i_ack_sys,
i_ack_3d,
o_be,
o_wd,
i_rstr_sys,
i_rstr_3d,
i_rd_sys,
i_rd_3d,
// I2C wishbone
o_wb_adr,
o_wb_dat,
i_wb_dat,
o_wb_we,
o_wb_stb,
o_wb_cyc,
i_wb_ack
);
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
// sh4 local interface
input i_req;
input i_wr;
input [23:0] i_adrs;
output o_ack;
input [3:0] i_be;
input [31:0] i_wd;
output o_rstr;
output [31:0] o_rd;
// internal side
output o_req_sys;
output o_req_3d;
output o_wr;
output [21:0] o_adrs;
input i_ack_sys;
input i_ack_3d;
output [3:0] o_be;
output [31:0] o_wd;
input i_rstr_sys;
input i_rstr_3d;
input [31:0] i_rd_sys;
input [31:0] i_rd_3d;
// wishbone signals
output [2:0] o_wb_adr; // lower address bits
output [7:0] o_wb_dat; // databus input
input [7:0] i_wb_dat; // databus output
output o_wb_we; // write enable input
output o_wb_stb; // stobe/core select signal
output o_wb_cyc; // valid bus cycle input
input i_wb_ack; // bus cycle acknowledge output
//////////////////////////////////
// reg
//////////////////////////////////
//////////////////////////////////
// wire
//////////////////////////////////
wire w_sys_hit;
wire w_3d_hit;
wire w_i2c_hit;
wire [23:0] w_adrs;
wire w_req;
wire w_rstr_i2c;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_adrs = i_adrs;
assign w_req = i_req;
assign w_sys_hit = (w_adrs[9:8] == 2'b00); // byte address
assign w_i2c_hit = (w_adrs[9:8] == 2'b01);
assign w_3d_hit = (w_adrs[9] == 1'b1);
assign o_ack = (w_sys_hit & i_ack_sys)|
(w_i2c_hit & i_wb_ack)|
(w_3d_hit &i_ack_3d);
assign o_rstr = i_rstr_sys | i_rstr_3d | w_rstr_i2c;
assign o_rd = (i_rstr_sys) ? i_rd_sys :
(i_rstr_3d) ? i_rd_3d :
(w_rstr_i2c) ? {24'h0,i_wb_dat} :
32'h0;
assign o_req_sys = w_req & w_sys_hit;
assign o_req_3d = w_req & w_3d_hit;
assign o_adrs = w_adrs[21:0];
assign o_wr = i_wr;
assign o_be = i_be;
assign o_wd = i_wd;
assign o_wb_adr[2:0] = i_adrs[4:2];
assign o_wb_dat = i_wd[7:0];
assign o_wb_we = i_wr;
assign o_wb_stb = w_req & w_i2c_hit;
assign o_wb_cyc = o_wb_stb;
assign w_rstr_i2c = o_wb_stb & (!o_wb_we) & i_wb_ack;
endmodule
|
module zedboard
(CLK_100,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
btns_5bits_tri_i,
leds_8bits_tri_o,
sws_8bits_tri_i,
o_hsync_x,
o_vsync_x,
o_vr,
o_vg,
o_vb
`ifdef PP_USE_HDMI
,io_scl,
io_sda,
clk_vo,
o_hd_vsync,
o_hd_hsync,
o_hd_de,
o_hd_d
`endif
);
input CLK_100;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [4:0]btns_5bits_tri_i;
output [7:0]leds_8bits_tri_o;
input [7:0]sws_8bits_tri_i;
output o_hsync_x;
output o_vsync_x;
output [3:0] o_vr;
output [3:0] o_vg;
output [3:0] o_vb;
`ifdef PP_USE_HDMI
// HDMI
inout io_scl;
inout io_sda;
output clk_vo;
output o_hd_vsync;
output o_hd_hsync;
output o_hd_de;
output [15:0] o_hd_d;
`endif
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [31:0]M_AXI_araddr;
wire [1:0]M_AXI_arburst;
wire [3:0]M_AXI_arcache;
wire [11:0]M_AXI_arid;
wire [3:0]M_AXI_arlen;
wire [1:0]M_AXI_arlock;
wire [2:0]M_AXI_arprot;
wire [3:0]M_AXI_arqos;
wire M_AXI_arready;
wire [2:0]M_AXI_arsize;
wire M_AXI_arvalid;
wire [31:0]M_AXI_awaddr;
wire [1:0]M_AXI_awburst;
wire [3:0]M_AXI_awcache;
wire [11:0]M_AXI_awid;
wire [3:0]M_AXI_awlen;
wire [1:0]M_AXI_awlock;
wire [2:0]M_AXI_awprot;
wire [3:0]M_AXI_awqos;
wire M_AXI_awready;
wire [2:0]M_AXI_awsize;
wire M_AXI_awvalid;
wire [11:0]M_AXI_bid;
wire M_AXI_bready;
wire [1:0]M_AXI_bresp;
wire M_AXI_bvalid;
wire [31:0]M_AXI_rdata;
wire [11:0]M_AXI_rid;
wire M_AXI_rlast;
wire M_AXI_rready;
wire [1:0]M_AXI_rresp;
wire M_AXI_rvalid;
wire [31:0]M_AXI_wdata;
wire [11:0]M_AXI_wid;
wire M_AXI_wlast;
wire M_AXI_wready;
wire [3:0]M_AXI_wstrb;
wire M_AXI_wvalid;
wire [31:0]S_AXI_araddr;
wire [1:0]S_AXI_arburst;
wire [3:0]S_AXI_arcache;
wire [2:0]S_AXI_arid;
wire [7:0]S_AXI_arlen;
wire [0:0]S_AXI_arlock;
wire [2:0]S_AXI_arprot;
wire [3:0]S_AXI_arqos;
wire S_AXI_arready;
wire [3:0]S_AXI_arregion;
wire [2:0]S_AXI_arsize;
wire [4:0]S_AXI_aruser;
wire S_AXI_arvalid;
wire [31:0]S_AXI_awaddr;
wire [1:0]S_AXI_awburst;
wire [3:0]S_AXI_awcache;
wire [2:0]S_AXI_awid;
wire [7:0]S_AXI_awlen;
wire [0:0]S_AXI_awlock;
wire [2:0]S_AXI_awprot;
wire [3:0]S_AXI_awqos;
wire S_AXI_awready;
wire [3:0]S_AXI_awregion;
wire [2:0]S_AXI_awsize;
wire [4:0]S_AXI_awuser;
wire S_AXI_awvalid;
wire [2:0]S_AXI_bid;
wire S_AXI_bready;
wire [1:0]S_AXI_bresp;
wire S_AXI_bvalid;
wire [63:0]S_AXI_rdata;
wire [2:0]S_AXI_rid;
wire S_AXI_rlast;
wire S_AXI_rready;
wire [1:0]S_AXI_rresp;
wire [4:0]S_AXI_ruser;
wire S_AXI_rvalid;
wire [63:0]S_AXI_wdata;
wire S_AXI_wlast;
wire S_AXI_wready;
wire [7:0]S_AXI_wstrb;
wire [4:0]S_AXI_wuser;
wire S_AXI_wvalid;
wire [4:0]btns_5bits_tri_i;
wire [7:0]leds_8bits_tri_o;
wire [7:0]sws_8bits_tri_i;
wire [7:0] w_vr;
wire [7:0] w_vg;
wire [7:0] w_vb;
wire w_int;
assign o_vr = w_vr[7:4];
assign o_vg = w_vg[7:4];
assign o_vb = w_vb[7:4];
wire [1:0] w_debug;
wire clk_v_pll;
wire clk_v_pll_90;
wire clkfb;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(8),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(32),
.CLKOUT1_DIVIDE(32),
.CLKOUT2_DIVIDE(32),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(135.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.0),
.STARTUP_WAIT("FALSE")
) u_PLLE2_BASE
(
.CLKOUT0(),
.CLKOUT1(clk_v_pll),
.CLKOUT2(clk_v_pll_90),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(clkfb),
.LOCKED(),
.CLKIN1(CLK_100),
.PWRDWN(),
.RST(0),
.CLKFBIN(clkfb)
);
pp_top u_pp_top (
// system
.clk_core(FCLK_CLK0),
.rst_x(FCLK_RESET0_N),
.o_int(w_int),
.o_debug(w_debug),
// AXI Slave
// write port
.i_awid_s(M_AXI_awid[7:0]),
.i_awaddr_s(M_AXI_awaddr),
.i_awlen_s({1'b0,M_AXI_awlen[3:0]}),
.i_awsize_s(M_AXI_awsize),
.i_awburst_s(M_AXI_awburst),
.i_awlock_s('d0),
.i_awcache_s('d0),
.i_awprot_s('d0),
.i_awvalid_s(M_AXI_awvalid),
.o_awready_s(M_AXI_awready),
.i_wid_s(M_AXI_awid[7:0]),
.i_wdata_s(M_AXI_wdata),
.i_wstrb_s(M_AXI_wstrb),
.i_wlast_s(M_AXI_wlast),
.i_wvalid_s(M_AXI_wvalid),
.o_wready_s(M_AXI_wready),
.o_bid_s(M_AXI_bid[7:0]),
.o_bresp_s(M_AXI_bresp),
.o_bvalid_s(M_AXI_bvalid),
.i_bready_s(M_AXI_bready),
// read port
.i_arid_s(M_AXI_arid[7:0]),
.i_araddr_s(M_AXI_araddr),
.i_arlen_s({1'b0,M_AXI_arlen[3:0]}),
.i_arsize_s(M_AXI_arsize),
.i_arburst_s(M_AXI_arburst),
.i_arlock_s('d0),
.i_arcache_s('d0),
.i_arprot_s('d0),
.i_arvalid_s(M_AXI_arvalid),
.o_arready_s(M_AXI_arready),
.o_rid_s(M_AXI_rid[7:0]),
.o_rdata_s(M_AXI_rdata),
.o_rresp_s(M_AXI_rresp),
.o_rlast_s(M_AXI_rlast),
.o_rvalid_s(M_AXI_rvalid),
.i_rready_s(M_AXI_rready),
// AXI Master
.o_awid_m(S_AXI_awid),
.o_awaddr_m(S_AXI_awaddr),
.o_awlen_m(S_AXI_awlen[4:0]),
.o_awsize_m(S_AXI_awsize),
.o_awburst_m(S_AXI_awburst),
.o_awlock_m(S_AXI_awlock),
.o_awcache_m(S_AXI_awcache),
.o_awuser_m(S_AXI_awuser),
.o_awprot_m(S_AXI_awprot),
.o_awvalid_m(S_AXI_awvalid),
.i_awready_m(S_AXI_awready),
.o_wid_m(),
.o_wdata_m(S_AXI_wdata),
.o_wstrb_m(S_AXI_wstrb),
.o_wlast_m(S_AXI_wlast),
.o_wvalid_m(S_AXI_wvalid),
.i_wready_m(S_AXI_wready),
.i_bid_m(S_AXI_bid),
.i_bresp_m(S_AXI_bresp),
.i_bvalid_m(S_AXI_bvalid),
.o_bready_m(S_AXI_bready),
.o_arid_m(S_AXI_arid),
.o_araddr_m(S_AXI_araddr),
.o_arlen_m(S_AXI_arlen[4:0]),
.o_arsize_m(S_AXI_arsize),
.o_arburst_m(S_AXI_arburst),
.o_arlock_m(S_AXI_arlock),
.o_arcache_m(S_AXI_arcache),
.o_aruser_m(S_AXI_aruser),
.o_arprot_m(S_AXI_arprot),
.o_arvalid_m(S_AXI_arvalid),
.i_arready_m(S_AXI_arready),
.i_rid_m(S_AXI_rid),
.i_rdata_m(S_AXI_rdata),
.i_rresp_m(S_AXI_rresp),
.i_rlast_m(S_AXI_rlast),
.i_rvalid_m(S_AXI_rvalid),
.o_rready_m(S_AXI_rready),
// Video out
/*
.clk_v(FCLK_CLK3),
.clk_v_90(FCLK_CLK3),
*/
.clk_v(clk_v_pll),
// .clk_v_90(clk_v_pll_90), HDMI Test
.o_blank_x(),
.o_hsync_x(o_hsync_x),
.o_vsync_x(o_vsync_x),
.o_vr(w_vr),
.o_vg(w_vg),
.o_vb(w_vb)
`ifdef PP_USE_HDMI
// HDMI
,.io_scl(io_scl),
.io_sda(io_sda),
.clk_vo(clk_vo),
.o_hd_vsync(o_hd_vsync),
.o_hd_hsync(o_hd_hsync),
.o_hd_de(o_hd_de),
.o_hd_d(o_hd_d)
`endif
);
zed_base zed_base_i
(.IRQ_F2P(w_int),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.M_AXI_araddr(M_AXI_araddr),
.M_AXI_arburst(M_AXI_arburst),
.M_AXI_arcache(M_AXI_arcache),
.M_AXI_arid(M_AXI_arid),
.M_AXI_arlen(M_AXI_arlen),
.M_AXI_arlock(M_AXI_arlock),
.M_AXI_arprot(M_AXI_arprot),
.M_AXI_arqos(M_AXI_arqos),
.M_AXI_arready(M_AXI_arready),
.M_AXI_arsize(M_AXI_arsize),
.M_AXI_arvalid(M_AXI_arvalid),
.M_AXI_awaddr(M_AXI_awaddr),
.M_AXI_awburst(M_AXI_awburst),
.M_AXI_awcache(M_AXI_awcache),
.M_AXI_awid(M_AXI_awid),
.M_AXI_awlen(M_AXI_awlen),
.M_AXI_awlock(M_AXI_awlock),
.M_AXI_awprot(M_AXI_awprot),
.M_AXI_awqos(M_AXI_awqos),
.M_AXI_awready(M_AXI_awready),
.M_AXI_awsize(M_AXI_awsize),
.M_AXI_awvalid(M_AXI_awvalid),
.M_AXI_bid(M_AXI_bid),
.M_AXI_bready(M_AXI_bready),
.M_AXI_bresp(M_AXI_bresp),
.M_AXI_bvalid(M_AXI_bvalid),
.M_AXI_rdata(M_AXI_rdata),
.M_AXI_rid(M_AXI_rid),
.M_AXI_rlast(M_AXI_rlast),
.M_AXI_rready(M_AXI_rready),
.M_AXI_rresp(M_AXI_rresp),
.M_AXI_rvalid(M_AXI_rvalid),
.M_AXI_wdata(M_AXI_wdata),
.M_AXI_wid(M_AXI_wid),
.M_AXI_wlast(M_AXI_wlast),
.M_AXI_wready(M_AXI_wready),
.M_AXI_wstrb(M_AXI_wstrb),
.M_AXI_wvalid(M_AXI_wvalid),
.S_AXI_araddr(S_AXI_araddr),
.S_AXI_arburst(S_AXI_arburst),
.S_AXI_arcache(S_AXI_arcache),
.S_AXI_arlen(S_AXI_arlen),
.S_AXI_arlock(S_AXI_arlock),
.S_AXI_arprot(S_AXI_arprot),
.S_AXI_arqos(S_AXI_arqos),
.S_AXI_arready(S_AXI_arready),
.S_AXI_arregion(S_AXI_arregion),
.S_AXI_arsize(S_AXI_arsize),
// .S_AXI_aruser(S_AXI_aruser),
.S_AXI_arvalid(S_AXI_arvalid),
.S_AXI_awaddr(S_AXI_awaddr),
.S_AXI_awburst(S_AXI_awburst),
.S_AXI_awcache(S_AXI_awcache),
.S_AXI_awlen(S_AXI_awlen),
.S_AXI_awlock(S_AXI_awlock),
.S_AXI_awprot(S_AXI_awprot),
.S_AXI_awqos(S_AXI_awqos),
.S_AXI_awready(S_AXI_awready),
.S_AXI_awregion(S_AXI_awregion),
.S_AXI_awsize(S_AXI_awsize),
// .S_AXI_awuser(S_AXI_awuser),
.S_AXI_awvalid(S_AXI_awvalid),
.S_AXI_bready(S_AXI_bready),
.S_AXI_bresp(S_AXI_bresp),
.S_AXI_bvalid(S_AXI_bvalid),
.S_AXI_rdata(S_AXI_rdata),
.S_AXI_rlast(S_AXI_rlast),
.S_AXI_rready(S_AXI_rready),
.S_AXI_rresp(S_AXI_rresp),
.S_AXI_rvalid(S_AXI_rvalid),
.S_AXI_wdata(S_AXI_wdata),
.S_AXI_wlast(S_AXI_wlast),
.S_AXI_wready(S_AXI_wready),
.S_AXI_wstrb(S_AXI_wstrb),
.S_AXI_wvalid(S_AXI_wvalid),
.btns_5bits_tri_i(btns_5bits_tri_i),
.leds_8bits_tri_o(leds_8bits_tri_o),
.sws_8bits_tri_i(sws_8bits_tri_i));
endmodule
|
module top (
fpga_clk_50,
// fpga_reset_n,
//fpga_led_output,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
hps_usb1_D0,
hps_usb1_D1,
hps_usb1_D2,
hps_usb1_D3,
hps_usb1_D4,
hps_usb1_D5,
hps_usb1_D6,
hps_usb1_D7,
hps_usb1_CLK,
hps_usb1_STP,
hps_usb1_DIR,
hps_usb1_NXT,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl,
//////////// HDMI //////////
HDMI_I2C_SCL,
HDMI_I2C_SDA,
HDMI_I2S,
HDMI_LRCLK,
HDMI_MCLK,
HDMI_SCLK,
HDMI_TX_CLK,
HDMI_TX_D,
HDMI_TX_DE,
HDMI_TX_HS,
HDMI_TX_INT,
HDMI_TX_VS,
//////////// KEY //////////
KEY,
//////////// LED //////////
LED,
//////////// SW //////////
SW
);
input wire fpga_clk_50;
wire fpga_reset_n;
//output wire [3:0] fpga_led_output;
//////////// HDMI //////////
inout wire HDMI_I2C_SCL;
inout wire HDMI_I2C_SDA;
inout wire HDMI_I2S;
inout wire HDMI_LRCLK;
inout wire HDMI_MCLK;
inout wire HDMI_SCLK;
output wire HDMI_TX_CLK;
output wire [23:0] HDMI_TX_D;
output wire HDMI_TX_DE;
output wire HDMI_TX_HS;
input wire HDMI_TX_INT;
output wire HDMI_TX_VS;
//////////// KEY //////////
input wire [1:0] KEY;
//////////// LED //////////
output wire [7:0] LED;
//////////// SW //////////
input wire [3:0] SW;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire hps_usb1_D0;
inout wire hps_usb1_D1;
inout wire hps_usb1_D2;
inout wire hps_usb1_D3;
inout wire hps_usb1_D4;
inout wire hps_usb1_D5;
inout wire hps_usb1_D6;
inout wire hps_usb1_D7;
input wire hps_usb1_CLK;
output wire hps_usb1_STP;
input wire hps_usb1_DIR;
input wire hps_usb1_NXT;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
wire [29:0] fpga_internal_led;
wire kernel_clk;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire fpga_debounced_button;
wire clk_65;
wire clk_130;
// connection of internal logics
assign fpga_reset_n = KEY[0];
//=======================================================
// Structural coding
//=======================================================
I2C_HDMI_Config u_I2C_HDMI_Config (
.iCLK(fpga_clk_50),
.iRST_N( 1'b1),
.I2C_SCLK(HDMI_I2C_SCL),
.I2C_SDAT(HDMI_I2C_SDA),
.HDMI_TX_INT(HDMI_TX_INT)
);
vga_pll vga_pll_inst(
.refclk(fpga_clk_50), // refclk.clk
.rst(1'b0), // reset.reset
.outclk_0(clk_65), // outclk0.clk
.outclk_1(clk_130), // outclk1.clk
.locked() // locked.export
);
assign HDMI_TX_CLK = clk_65;
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl),
.peripheral_hps_io_usb1_inst_D0 (hps_usb1_D0), // .hps_io_usb1_inst_D0
.peripheral_hps_io_usb1_inst_D1 (hps_usb1_D1), // .hps_io_usb1_inst_D1
.peripheral_hps_io_usb1_inst_D2 (hps_usb1_D2), // .hps_io_usb1_inst_D2
.peripheral_hps_io_usb1_inst_D3 (hps_usb1_D3), // .hps_io_usb1_inst_D3
.peripheral_hps_io_usb1_inst_D4 (hps_usb1_D4), // .hps_io_usb1_inst_D4
.peripheral_hps_io_usb1_inst_D5 (hps_usb1_D5), // .hps_io_usb1_inst_D5
.peripheral_hps_io_usb1_inst_D6 (hps_usb1_D6), // .hps_io_usb1_inst_D6
.peripheral_hps_io_usb1_inst_D7 (hps_usb1_D7), // .hps_io_usb1_inst_D7
.peripheral_hps_io_usb1_inst_CLK (hps_usb1_CLK), // .hps_io_usb1_inst_CLK
.peripheral_hps_io_usb1_inst_STP (hps_usb1_STP), // .hps_io_usb1_inst_STP
.peripheral_hps_io_usb1_inst_DIR (hps_usb1_DIR), // .hps_io_usb1_inst_DIR
.peripheral_hps_io_usb1_inst_NXT (hps_usb1_NXT), // .hps_io_usb1_inst_NXT
.acl_iface_clock_130_clk (clk_130), // acl_iface_clock_130.clk
.acl_iface_alt_vip_itc_0_clocked_video_vid_clk (HDMI_TX_CLK), // acl_iface_alt_vip_itc_0_clocked_video.vid_clk
.acl_iface_alt_vip_itc_0_clocked_video_vid_data (HDMI_TX_D), // .vid_data
.acl_iface_alt_vip_itc_0_clocked_video_underflow (), // .underflow
.acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid (HDMI_TX_DE), // .vid_datavalid
.acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync (HDMI_TX_VS), // .vid_v_sync
.acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync (HDMI_TX_HS), // .vid_h_sync
.acl_iface_alt_vip_itc_0_clocked_video_vid_f (), // .vid_f
.acl_iface_alt_vip_itc_0_clocked_video_vid_h (), // .vid_h
.acl_iface_alt_vip_itc_0_clocked_video_vid_v (), // .vid_v
.acl_iface_led_pio_external_connection_export (LED[7:4]), // acl_iface_led_pio_external_connection.export
.acl_iface_dipsw_pio_external_connection_export (SW), // acl_iface_dipsw_pio_external_connection.export
.acl_iface_button_pio_external_connection_export (fpga_debounced_button) // acl_iface_button_pio_external_connection.export
);
// Debounce logic to clean out glitches within 1ms
debounce debounce_inst (
.clk (fpga_clk_50),
.reset_n (fpga_reset_n),
.data_in (KEY[1]),
.data_out (fpga_debounced_button)
);
defparam debounce_inst.WIDTH = 1;
defparam debounce_inst.POLARITY = "LOW";
defparam debounce_inst.TIMEOUT = 50000; // at 50Mhz this is a debounce time of 1ms
defparam debounce_inst.TIMEOUT_WIDTH = 16; // ceil(log2(TIMEOUT))
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
assign LED[3:0] = ~fpga_internal_led[29:26];
endmodule
|
module async_counter_30(clk, count);
input clk;
output [29:0] count;
reg [14:0] count_a;
reg [14:0] count_b;
initial count_a = 15'b0;
initial count_b = 15'b0;
always @(negedge clk)
count_a <= count_a + 1'b1;
always @(negedge count_a[14])
count_b <= count_b + 1'b1;
assign count = {count_b, count_a};
endmodule
|
module top (
fpga_clk_50,
fpga_reset_n,
fpga_led_output,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
hps_usb1_D0,
hps_usb1_D1,
hps_usb1_D2,
hps_usb1_D3,
hps_usb1_D4,
hps_usb1_D5,
hps_usb1_D6,
hps_usb1_D7,
hps_usb1_CLK,
hps_usb1_STP,
hps_usb1_DIR,
hps_usb1_NXT,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl,
LCD_TE,
LCD_SDI,
LCD_WR_SCLK,
LCD_CS,
LCD_RS_HSD,
LCD_RD_VSD,
LCD_DATA,
LCD_ENABLE,
LCD_PCLK,
TOUCH_SCK,
TOUCH_SDA,
TOUCH_INT
);
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [3:0] fpga_led_output;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire hps_usb1_D0;
inout wire hps_usb1_D1;
inout wire hps_usb1_D2;
inout wire hps_usb1_D3;
inout wire hps_usb1_D4;
inout wire hps_usb1_D5;
inout wire hps_usb1_D6;
inout wire hps_usb1_D7;
input wire hps_usb1_CLK;
output wire hps_usb1_STP;
input wire hps_usb1_DIR;
input wire hps_usb1_NXT;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
/// GPIO_0
input wire LCD_TE;
inout wire LCD_SDI;
output wire LCD_WR_SCLK;
output wire LCD_CS;
output wire LCD_RS_HSD;
output wire LCD_RD_VSD;
inout wire [23:0] LCD_DATA;
output wire LCD_ENABLE;
output wire LCD_PCLK;
output wire TOUCH_SCK;
inout wire TOUCH_SDA;
input wire TOUCH_INT;
wire [29:0] fpga_internal_led;
wire kernel_clk;
wire [7:0] NC_wire;
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl),
.peripheral_hps_io_usb1_inst_D0 (hps_usb1_D0), // .hps_io_usb1_inst_D0
.peripheral_hps_io_usb1_inst_D1 (hps_usb1_D1), // .hps_io_usb1_inst_D1
.peripheral_hps_io_usb1_inst_D2 (hps_usb1_D2), // .hps_io_usb1_inst_D2
.peripheral_hps_io_usb1_inst_D3 (hps_usb1_D3), // .hps_io_usb1_inst_D3
.peripheral_hps_io_usb1_inst_D4 (hps_usb1_D4), // .hps_io_usb1_inst_D4
.peripheral_hps_io_usb1_inst_D5 (hps_usb1_D5), // .hps_io_usb1_inst_D5
.peripheral_hps_io_usb1_inst_D6 (hps_usb1_D6), // .hps_io_usb1_inst_D6
.peripheral_hps_io_usb1_inst_D7 (hps_usb1_D7), // .hps_io_usb1_inst_D7
.peripheral_hps_io_usb1_inst_CLK (hps_usb1_CLK), // .hps_io_usb1_inst_CLK
.peripheral_hps_io_usb1_inst_STP (hps_usb1_STP), // .hps_io_usb1_inst_STP
.peripheral_hps_io_usb1_inst_DIR (hps_usb1_DIR), // .hps_io_usb1_inst_DIR
.peripheral_hps_io_usb1_inst_NXT (hps_usb1_NXT), // .hps_io_usb1_inst_NXT
.acl_iface_tft_lcd_export_cs (LCD_CS), // acl_iface_tft_lcd_export.cs
.acl_iface_tft_lcd_export_rs (LCD_RS_HSD), // .rs
.acl_iface_tft_lcd_export_wr (LCD_WR_SCLK), // .wr
.acl_iface_tft_lcd_export_rd (LCD_RD_VSD), // .rd
.acl_iface_tft_lcd_export_data ({NC_wire,LCD_DATA}) // .data
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
endmodule
|
module top (
fpga_clk_50,
fpga_reset_n,
fpga_led_output,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
hps_usb1_D0,
hps_usb1_D1,
hps_usb1_D2,
hps_usb1_D3,
hps_usb1_D4,
hps_usb1_D5,
hps_usb1_D6,
hps_usb1_D7,
hps_usb1_CLK,
hps_usb1_STP,
hps_usb1_DIR,
hps_usb1_NXT,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl,
///////// VGA /////////
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS
);
///////// VGA /////////
output wire [7:0] VGA_B;
output wire VGA_BLANK_N;
output wire VGA_CLK;
output wire [7:0] VGA_G;
output wire VGA_HS;
output wire [7:0] VGA_R;
output wire VGA_SYNC_N;
output wire VGA_VS;
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [3:0] fpga_led_output;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire hps_usb1_D0;
inout wire hps_usb1_D1;
inout wire hps_usb1_D2;
inout wire hps_usb1_D3;
inout wire hps_usb1_D4;
inout wire hps_usb1_D5;
inout wire hps_usb1_D6;
inout wire hps_usb1_D7;
input wire hps_usb1_CLK;
output wire hps_usb1_STP;
input wire hps_usb1_DIR;
input wire hps_usb1_NXT;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
//=======================================================
// REG/WIRE declarations
//=======================================================
// internal wires and registers declaration
wire clk_65;
wire clk_130;
wire [7:0] vid_r,vid_g,vid_b;
wire vid_v_sync ;
wire vid_h_sync ;
wire vid_datavalid;
wire [29:0] fpga_internal_led;
wire kernel_clk;
//=======================================================
// Structural coding
//=======================================================
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b0;
assign VGA_CLK = clk_65;
assign {VGA_B,VGA_G,VGA_R} = {vid_b,vid_g,vid_r};
assign VGA_VS = vid_v_sync;
assign VGA_HS = vid_h_sync;
vga_pll vga_pll_inst(
.refclk(fpga_clk_50), // refclk.clk
.rst(1'b0), // reset.reset
.outclk_0(clk_65), // outclk0.clk
.outclk_1(clk_130), // outclk1.clk
.locked() // locked.export
);
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl),
//itc
.acl_iface_clock_130_clk (clk_130),
.acl_iface_alt_vip_itc_0_clocked_video_vid_clk (clk_65), // alt_vip_itc_0_clocked_video.vid_clk
.acl_iface_alt_vip_itc_0_clocked_video_vid_data ({vid_r,vid_g,vid_b}), // .vid_data
.acl_iface_alt_vip_itc_0_clocked_video_underflow (), // .underflow
.acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid (vid_datavalid), // .vid_datavalid
.acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync (vid_v_sync), // .vid_v_sync
.acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync (vid_h_sync), // .vid_h_sync
.acl_iface_alt_vip_itc_0_clocked_video_vid_f (), // .vid_f
.acl_iface_alt_vip_itc_0_clocked_video_vid_h (), // .vid_h
.acl_iface_alt_vip_itc_0_clocked_video_vid_v (),
.peripheral_hps_io_usb1_inst_D0 (hps_usb1_D0), // .hps_io_usb1_inst_D0
.peripheral_hps_io_usb1_inst_D1 (hps_usb1_D1), // .hps_io_usb1_inst_D1
.peripheral_hps_io_usb1_inst_D2 (hps_usb1_D2), // .hps_io_usb1_inst_D2
.peripheral_hps_io_usb1_inst_D3 (hps_usb1_D3), // .hps_io_usb1_inst_D3
.peripheral_hps_io_usb1_inst_D4 (hps_usb1_D4), // .hps_io_usb1_inst_D4
.peripheral_hps_io_usb1_inst_D5 (hps_usb1_D5), // .hps_io_usb1_inst_D5
.peripheral_hps_io_usb1_inst_D6 (hps_usb1_D6), // .hps_io_usb1_inst_D6
.peripheral_hps_io_usb1_inst_D7 (hps_usb1_D7), // .hps_io_usb1_inst_D7
.peripheral_hps_io_usb1_inst_CLK (hps_usb1_CLK), // .hps_io_usb1_inst_CLK
.peripheral_hps_io_usb1_inst_STP (hps_usb1_STP), // .hps_io_usb1_inst_STP
.peripheral_hps_io_usb1_inst_DIR (hps_usb1_DIR), // .hps_io_usb1_inst_DIR
.peripheral_hps_io_usb1_inst_NXT (hps_usb1_NXT) // .hps_io_usb1_inst_NXT
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
endmodule
|
module vga_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
vga_pll_0002 vga_pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule
|
module top (
fpga_clk_50,
fpga_reset_n,
ledr, // LEDR
hex0, //HEX0
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
hps_usb1_D0,
hps_usb1_D1,
hps_usb1_D2,
hps_usb1_D3,
hps_usb1_D4,
hps_usb1_D5,
hps_usb1_D6,
hps_usb1_D7,
hps_usb1_CLK,
hps_usb1_STP,
hps_usb1_DIR,
hps_usb1_NXT,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl
);
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [9:0] ledr;
output wire [3:0] hex0;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire hps_usb1_D0;
inout wire hps_usb1_D1;
inout wire hps_usb1_D2;
inout wire hps_usb1_D3;
inout wire hps_usb1_D4;
inout wire hps_usb1_D5;
inout wire hps_usb1_D6;
inout wire hps_usb1_D7;
input wire hps_usb1_CLK;
output wire hps_usb1_STP;
input wire hps_usb1_DIR;
input wire hps_usb1_NXT;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
wire [29:0] fpga_internal_led;
wire kernel_clk;
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_usb1_inst_D0 (hps_usb1_D0 ), // .hps_io_usb1_inst_D0
.peripheral_hps_io_usb1_inst_D1 (hps_usb1_D1 ), // .hps_io_usb1_inst_D1
.peripheral_hps_io_usb1_inst_D2 (hps_usb1_D2 ), // .hps_io_usb1_inst_D2
.peripheral_hps_io_usb1_inst_D3 (hps_usb1_D3 ), // .hps_io_usb1_inst_D3
.peripheral_hps_io_usb1_inst_D4 (hps_usb1_D4), // .hps_io_usb1_inst_D4
.peripheral_hps_io_usb1_inst_D5 (hps_usb1_D5 ), // .hps_io_usb1_inst_D5
.peripheral_hps_io_usb1_inst_D6 (hps_usb1_D6 ), // .hps_io_usb1_inst_D6
.peripheral_hps_io_usb1_inst_D7 (hps_usb1_D7 ), // .hps_io_usb1_inst_D7
.peripheral_hps_io_usb1_inst_CLK (hps_usb1_CLK ), // .hps_io_usb1_inst_CLK
.peripheral_hps_io_usb1_inst_STP (hps_usb1_STP ), // .hps_io_usb1_inst_STP
.peripheral_hps_io_usb1_inst_DIR (hps_usb1_DIR), // .hps_io_usb1_inst_DIR
.peripheral_hps_io_usb1_inst_NXT (hps_usb1_NXT ), // .hps_io_usb1_inst_NXT
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.acl_iface_led_pio_external_connection_export (ledr[7:0]), //FPGA LED_PIO
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl)
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
// assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
assign hex0[3:0] = ~fpga_internal_led[29:26];
endmodule
|
module system (
clk_50_clk,
kernel_clk_clk,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
peripheral_hps_io_emac1_inst_TX_CLK,
peripheral_hps_io_emac1_inst_TXD0,
peripheral_hps_io_emac1_inst_TXD1,
peripheral_hps_io_emac1_inst_TXD2,
peripheral_hps_io_emac1_inst_TXD3,
peripheral_hps_io_emac1_inst_RXD0,
peripheral_hps_io_emac1_inst_MDIO,
peripheral_hps_io_emac1_inst_MDC,
peripheral_hps_io_emac1_inst_RX_CTL,
peripheral_hps_io_emac1_inst_TX_CTL,
peripheral_hps_io_emac1_inst_RX_CLK,
peripheral_hps_io_emac1_inst_RXD1,
peripheral_hps_io_emac1_inst_RXD2,
peripheral_hps_io_emac1_inst_RXD3,
peripheral_hps_io_sdio_inst_CMD,
peripheral_hps_io_sdio_inst_D0,
peripheral_hps_io_sdio_inst_D1,
peripheral_hps_io_sdio_inst_CLK,
peripheral_hps_io_sdio_inst_D2,
peripheral_hps_io_sdio_inst_D3,
peripheral_hps_io_usb1_inst_D0,
peripheral_hps_io_usb1_inst_D1,
peripheral_hps_io_usb1_inst_D2,
peripheral_hps_io_usb1_inst_D3,
peripheral_hps_io_usb1_inst_D4,
peripheral_hps_io_usb1_inst_D5,
peripheral_hps_io_usb1_inst_D6,
peripheral_hps_io_usb1_inst_D7,
peripheral_hps_io_usb1_inst_CLK,
peripheral_hps_io_usb1_inst_STP,
peripheral_hps_io_usb1_inst_DIR,
peripheral_hps_io_usb1_inst_NXT,
peripheral_hps_io_uart0_inst_RX,
peripheral_hps_io_uart0_inst_TX,
peripheral_hps_io_i2c1_inst_SDA,
peripheral_hps_io_i2c1_inst_SCL,
peripheral_hps_io_gpio_inst_GPIO53,
reset_50_reset_n,
acl_iface_clock_130_clk,
acl_iface_alt_vip_itc_0_clocked_video_vid_clk,
acl_iface_alt_vip_itc_0_clocked_video_vid_data,
acl_iface_alt_vip_itc_0_clocked_video_underflow,
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid,
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync,
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync,
acl_iface_alt_vip_itc_0_clocked_video_vid_f,
acl_iface_alt_vip_itc_0_clocked_video_vid_h,
acl_iface_alt_vip_itc_0_clocked_video_vid_v);
input clk_50_clk;
output kernel_clk_clk;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
output peripheral_hps_io_emac1_inst_TX_CLK;
output peripheral_hps_io_emac1_inst_TXD0;
output peripheral_hps_io_emac1_inst_TXD1;
output peripheral_hps_io_emac1_inst_TXD2;
output peripheral_hps_io_emac1_inst_TXD3;
input peripheral_hps_io_emac1_inst_RXD0;
inout peripheral_hps_io_emac1_inst_MDIO;
output peripheral_hps_io_emac1_inst_MDC;
input peripheral_hps_io_emac1_inst_RX_CTL;
output peripheral_hps_io_emac1_inst_TX_CTL;
input peripheral_hps_io_emac1_inst_RX_CLK;
input peripheral_hps_io_emac1_inst_RXD1;
input peripheral_hps_io_emac1_inst_RXD2;
input peripheral_hps_io_emac1_inst_RXD3;
inout peripheral_hps_io_sdio_inst_CMD;
inout peripheral_hps_io_sdio_inst_D0;
inout peripheral_hps_io_sdio_inst_D1;
output peripheral_hps_io_sdio_inst_CLK;
inout peripheral_hps_io_sdio_inst_D2;
inout peripheral_hps_io_sdio_inst_D3;
inout peripheral_hps_io_usb1_inst_D0;
inout peripheral_hps_io_usb1_inst_D1;
inout peripheral_hps_io_usb1_inst_D2;
inout peripheral_hps_io_usb1_inst_D3;
inout peripheral_hps_io_usb1_inst_D4;
inout peripheral_hps_io_usb1_inst_D5;
inout peripheral_hps_io_usb1_inst_D6;
inout peripheral_hps_io_usb1_inst_D7;
input peripheral_hps_io_usb1_inst_CLK;
output peripheral_hps_io_usb1_inst_STP;
input peripheral_hps_io_usb1_inst_DIR;
input peripheral_hps_io_usb1_inst_NXT;
input peripheral_hps_io_uart0_inst_RX;
output peripheral_hps_io_uart0_inst_TX;
inout peripheral_hps_io_i2c1_inst_SDA;
inout peripheral_hps_io_i2c1_inst_SCL;
inout peripheral_hps_io_gpio_inst_GPIO53;
input reset_50_reset_n;
input acl_iface_clock_130_clk;
input acl_iface_alt_vip_itc_0_clocked_video_vid_clk;
output [31:0] acl_iface_alt_vip_itc_0_clocked_video_vid_data;
output acl_iface_alt_vip_itc_0_clocked_video_underflow;
output acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid;
output acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync;
output acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync;
output acl_iface_alt_vip_itc_0_clocked_video_vid_f;
output acl_iface_alt_vip_itc_0_clocked_video_vid_h;
output acl_iface_alt_vip_itc_0_clocked_video_vid_v;
endmodule
|
module acl_iface_system (
config_clk_clk,
reset_n,
kernel_clk_clk,
kernel_clk_snoop_clk,
kernel_mem0_waitrequest,
kernel_mem0_readdata,
kernel_mem0_readdatavalid,
kernel_mem0_burstcount,
kernel_mem0_writedata,
kernel_mem0_address,
kernel_mem0_write,
kernel_mem0_read,
kernel_mem0_byteenable,
kernel_mem0_debugaccess,
kernel_reset_reset_n,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
peripheral_hps_io_emac1_inst_TX_CLK,
peripheral_hps_io_emac1_inst_TXD0,
peripheral_hps_io_emac1_inst_TXD1,
peripheral_hps_io_emac1_inst_TXD2,
peripheral_hps_io_emac1_inst_TXD3,
peripheral_hps_io_emac1_inst_RXD0,
peripheral_hps_io_emac1_inst_MDIO,
peripheral_hps_io_emac1_inst_MDC,
peripheral_hps_io_emac1_inst_RX_CTL,
peripheral_hps_io_emac1_inst_TX_CTL,
peripheral_hps_io_emac1_inst_RX_CLK,
peripheral_hps_io_emac1_inst_RXD1,
peripheral_hps_io_emac1_inst_RXD2,
peripheral_hps_io_emac1_inst_RXD3,
peripheral_hps_io_sdio_inst_CMD,
peripheral_hps_io_sdio_inst_D0,
peripheral_hps_io_sdio_inst_D1,
peripheral_hps_io_sdio_inst_CLK,
peripheral_hps_io_sdio_inst_D2,
peripheral_hps_io_sdio_inst_D3,
peripheral_hps_io_usb1_inst_D0,
peripheral_hps_io_usb1_inst_D1,
peripheral_hps_io_usb1_inst_D2,
peripheral_hps_io_usb1_inst_D3,
peripheral_hps_io_usb1_inst_D4,
peripheral_hps_io_usb1_inst_D5,
peripheral_hps_io_usb1_inst_D6,
peripheral_hps_io_usb1_inst_D7,
peripheral_hps_io_usb1_inst_CLK,
peripheral_hps_io_usb1_inst_STP,
peripheral_hps_io_usb1_inst_DIR,
peripheral_hps_io_usb1_inst_NXT,
peripheral_hps_io_uart0_inst_RX,
peripheral_hps_io_uart0_inst_TX,
peripheral_hps_io_i2c1_inst_SDA,
peripheral_hps_io_i2c1_inst_SCL,
peripheral_hps_io_gpio_inst_GPIO53);
input config_clk_clk;
input reset_n;
output kernel_clk_clk;
output kernel_clk_snoop_clk;
output kernel_mem0_waitrequest;
output [255:0] kernel_mem0_readdata;
output kernel_mem0_readdatavalid;
input [4:0] kernel_mem0_burstcount;
input [255:0] kernel_mem0_writedata;
input [24:0] kernel_mem0_address;
input kernel_mem0_write;
input kernel_mem0_read;
input [31:0] kernel_mem0_byteenable;
input kernel_mem0_debugaccess;
output kernel_reset_reset_n;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
output peripheral_hps_io_emac1_inst_TX_CLK;
output peripheral_hps_io_emac1_inst_TXD0;
output peripheral_hps_io_emac1_inst_TXD1;
output peripheral_hps_io_emac1_inst_TXD2;
output peripheral_hps_io_emac1_inst_TXD3;
input peripheral_hps_io_emac1_inst_RXD0;
inout peripheral_hps_io_emac1_inst_MDIO;
output peripheral_hps_io_emac1_inst_MDC;
input peripheral_hps_io_emac1_inst_RX_CTL;
output peripheral_hps_io_emac1_inst_TX_CTL;
input peripheral_hps_io_emac1_inst_RX_CLK;
input peripheral_hps_io_emac1_inst_RXD1;
input peripheral_hps_io_emac1_inst_RXD2;
input peripheral_hps_io_emac1_inst_RXD3;
inout peripheral_hps_io_sdio_inst_CMD;
inout peripheral_hps_io_sdio_inst_D0;
inout peripheral_hps_io_sdio_inst_D1;
output peripheral_hps_io_sdio_inst_CLK;
inout peripheral_hps_io_sdio_inst_D2;
inout peripheral_hps_io_sdio_inst_D3;
inout peripheral_hps_io_usb1_inst_D0;
inout peripheral_hps_io_usb1_inst_D1;
inout peripheral_hps_io_usb1_inst_D2;
inout peripheral_hps_io_usb1_inst_D3;
inout peripheral_hps_io_usb1_inst_D4;
inout peripheral_hps_io_usb1_inst_D5;
inout peripheral_hps_io_usb1_inst_D6;
inout peripheral_hps_io_usb1_inst_D7;
input peripheral_hps_io_usb1_inst_CLK;
output peripheral_hps_io_usb1_inst_STP;
input peripheral_hps_io_usb1_inst_DIR;
input peripheral_hps_io_usb1_inst_NXT;
input peripheral_hps_io_uart0_inst_RX;
output peripheral_hps_io_uart0_inst_TX;
inout peripheral_hps_io_i2c1_inst_SDA;
inout peripheral_hps_io_i2c1_inst_SCL;
inout peripheral_hps_io_gpio_inst_GPIO53;
endmodule
|
module AUDIO_IF(
avs_s1_clk,
avs_s1_reset,
avs_s1_address,
avs_s1_read,
avs_s1_readdata,
avs_s1_write,
avs_s1_writedata,
//
avs_s1_export_BCLK,
avs_s1_export_DACLRC,
avs_s1_export_DACDAT,
avs_s1_export_ADCLRC,
avs_s1_export_ADCDAT,
avs_s1_export_XCK
);
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
`define DAC_LFIFO_ADDR 0
`define DAC_RFIFO_ADDR 1
`define ADC_LFIFO_ADDR 2
`define ADC_RFIFO_ADDR 3
`define CMD_ADDR 4
`define STATUS_ADDR 5
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input avs_s1_clk;
input avs_s1_reset;
input [2:0] avs_s1_address;
input avs_s1_read;
output [15:0] avs_s1_readdata;
input avs_s1_write;
input [15:0] avs_s1_writedata;
//
input avs_s1_export_BCLK;
input avs_s1_export_DACLRC;
output avs_s1_export_DACDAT;
input avs_s1_export_ADCLRC;
input avs_s1_export_ADCDAT;
output avs_s1_export_XCK;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// host
reg [15:0] reg_readdata;
reg fifo_clear;
// dac
wire dacfifo_full;
reg dacfifo_write;
reg [31:0] dacfifo_writedata;
// adc
wire adcfifo_empty;
reg adcfifo_read;
wire [31:0] adcfifo_readdata;
reg [31:0] data32_from_adcfifo;
reg [31:0] data32_from_adcfifo_2;
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
////////// fifo clear
always @ (posedge avs_s1_clk)
begin
if (avs_s1_reset)
fifo_clear <= 1'b0;
else if (avs_s1_write && (avs_s1_address == `CMD_ADDR))
fifo_clear <= avs_s1_writedata[0];
else if (fifo_clear)
fifo_clear <= 1'b0;
end
////////// write audio data(left&right) to dac-fifo
always @ (posedge avs_s1_clk)
begin
if (avs_s1_reset || fifo_clear)
begin
dacfifo_write <= 1'b0;
end
else if (avs_s1_write && (avs_s1_address == `DAC_LFIFO_ADDR))
begin
dacfifo_writedata[31:16] <= avs_s1_writedata;
dacfifo_write <= 1'b0;
end
else if (avs_s1_write && (avs_s1_address == `DAC_RFIFO_ADDR))
begin
dacfifo_writedata[15:0] <= avs_s1_writedata;
dacfifo_write <= 1'b1;
end
else
dacfifo_write <= 1'b0;
end
////////// response data to avalon-mm
always @ (negedge avs_s1_clk)
begin
if (avs_s1_reset || fifo_clear)
data32_from_adcfifo = 0;
else if (avs_s1_read && (avs_s1_address == `STATUS_ADDR))
reg_readdata <= {adcfifo_empty, dacfifo_full};
else if (avs_s1_read && (avs_s1_address == `ADC_LFIFO_ADDR))
reg_readdata <= data32_from_adcfifo[31:16];
else if (avs_s1_read && (avs_s1_address == `ADC_RFIFO_ADDR))
begin
reg_readdata <= data32_from_adcfifo[15:0];
data32_from_adcfifo <= data32_from_adcfifo_2;
end
end
////////// read audio data from adc fifo
always @ (negedge avs_s1_clk)
begin
if (avs_s1_reset)
begin
adcfifo_read <= 1'b0;
data32_from_adcfifo_2 <= 0;
end
else if ((avs_s1_address == `ADC_LFIFO_ADDR) & avs_s1_read & ~adcfifo_empty)
begin
adcfifo_read <= 1'b1;
end
else if (adcfifo_read)
begin
data32_from_adcfifo_2 = adcfifo_readdata;
adcfifo_read <= 1'b0;
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign avs_s1_readdata = reg_readdata;
assign avs_s1_export_XCK = avs_s1_clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
AUDIO_DAC DAC_Instance(
// host
.clk(avs_s1_clk),
.reset(avs_s1_reset),
.write(dacfifo_write),
.writedata(dacfifo_writedata),
.full(dacfifo_full),
.clear(fifo_clear),
// dac
.bclk(avs_s1_export_BCLK),
.daclrc(avs_s1_export_DACLRC),
.dacdat(avs_s1_export_DACDAT)
);
AUDIO_ADC ADC_Instance(
// host
.clk(avs_s1_clk),
.reset(avs_s1_reset),
.read(adcfifo_read),
.readdata(adcfifo_readdata),
.empty(adcfifo_empty),
.clear(fifo_clear),
// dac
.bclk(avs_s1_export_BCLK),
.adclrc(avs_s1_export_ADCLRC),
.adcdat(avs_s1_export_ADCDAT)
);
defparam
DAC_Instance.DATA_WIDTH = 32;
defparam
ADC_Instance.DATA_WIDTH = 32;
endmodule
|
module audio_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
|
module AUDIO_ADC(
// host
clk,
reset,
read,
readdata,
//available,
empty,
clear,
// dac
bclk,
adclrc,
adcdat
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DATA_WIDTH = 32;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input clk;
input reset;
input read;
output [(DATA_WIDTH-1):0] readdata;
output empty;
input clear;
input bclk;
input adclrc;
input adcdat;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
reg [4:0] bit_index; //0~31
reg valid_bit;
reg reg_adc_left;
reg [(DATA_WIDTH-1):0] reg_adc_serial_data;
reg [(DATA_WIDTH-1):0] adcfifo_writedata;
reg adcfifo_write;
wire adcfifo_full;
reg wait_one_clk;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
//===== Serialize data (I2S) to ADC-FIFO =====
wire is_left_ch;
assign is_left_ch = ~adclrc;
always @ (posedge bclk)
begin
if (reset || clear)
begin
bit_index = DATA_WIDTH;
reg_adc_left = is_left_ch;
adcfifo_write = 1'b0;
valid_bit = 0;
end
else
begin
if (adcfifo_write)
adcfifo_write = 1'b0; // disable write at second cycle
if (reg_adc_left ^ is_left_ch)
begin // channel change
reg_adc_left = is_left_ch;
valid_bit = 1'b1;
wait_one_clk = 1'b1;
if (reg_adc_left)
bit_index = DATA_WIDTH;
end
// serial bit to adcfifo
if (valid_bit && wait_one_clk)
wait_one_clk = 1'b0;
else if (valid_bit && !wait_one_clk)
begin
bit_index = bit_index - 1'b1;
reg_adc_serial_data[bit_index] = adcdat;
if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
begin
if (bit_index == 0 && !adcfifo_full)
begin // write data to adcfifo
adcfifo_writedata = reg_adc_serial_data;
adcfifo_write = 1'b1; // enable write at first cycle
end
valid_bit = 0;
end
end
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
audio_fifo adc_fifo(
// write (adc write to fifo)
.wrclk(bclk),
.wrreq(adcfifo_write),
.data(adcfifo_writedata),
.wrfull(adcfifo_full),
.aclr(clear), // sync with wrclk
// read (host read from fifo)
.rdclk(clk),
.rdreq(read),
.q(readdata),
.rdempty(empty)
);
endmodule
|
module AUDIO_DAC(
// host
clk,
reset,
write,
writedata,
full,
clear,
// dac
bclk,
daclrc,
dacdat
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DATA_WIDTH = 32;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input clk;
input reset;
input write;
input [(DATA_WIDTH-1):0] writedata;
output full;
input clear;
input bclk;
input daclrc;
output dacdat;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Note. Left Justified Mode
reg request_bit;
reg bit_to_dac;
reg [4:0] bit_index; //0~31
reg dac_is_left;
reg [(DATA_WIDTH-1):0] data_to_dac;
reg [(DATA_WIDTH-1):0] shift_data_to_dac;
//
wire dacfifo_empty;
wire dacfifo_read;
wire [(DATA_WIDTH-1):0] dacfifo_readdata;
wire is_left_ch;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
//////////// read data from fifo
assign dacfifo_read = (dacfifo_empty)?1'b0:1'b1;
always @ (negedge is_left_ch)
begin
if (dacfifo_empty)
data_to_dac = 0;
else
data_to_dac = dacfifo_readdata;
end
//////////// streaming data(32-bits) to dac chip(I2S 1-bits port)
assign is_left_ch = ~daclrc;
always @ (negedge bclk)
begin
if (reset || clear)
begin
request_bit = 0;
bit_index = 0;
dac_is_left = is_left_ch;
bit_to_dac = 1'b0;
end
else
begin
if (dac_is_left ^ is_left_ch)
begin // channel change
dac_is_left = is_left_ch;
request_bit = 1;
if (dac_is_left)
begin
shift_data_to_dac = data_to_dac;
bit_index = DATA_WIDTH;
end
end
// serial data to dac
if (request_bit)
begin
bit_index = bit_index - 1'b1;
bit_to_dac = shift_data_to_dac[bit_index]; // MSB as first bit
if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
request_bit = 0;
end
else
bit_to_dac = 1'b0;
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign dacdat = bit_to_dac;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
audio_fifo dac_fifo(
// write
.wrclk(clk),
.wrreq(write),
.data(writedata),
.wrfull(full),
.aclr(clear), // sync with wrclk
// read
//.rdclk(bclk),
.rdclk(is_left_ch),
.rdreq(dacfifo_read),
.q(dacfifo_readdata),
.rdempty(dacfifo_empty)
);
endmodule
|
module TERASIC_IRM(
clk, // must be 50 MHZ
reset_n,
// interrrupt
irq,
// avalon slave
s_cs_n,
s_read,
s_readdata,
s_write,
s_writedata,
// export
ir
);
input clk;
input reset_n;
output reg irq;
input s_cs_n;
input s_read;
output [31:0] s_readdata;
input s_write;
input [31:0] s_writedata;
input ir;
// write to clear interrupt
wire data_ready;
//always @ (posedge clk or posedge data_ready or negedge reset_n)
reg pre_data_ready;
always @ (posedge clk or negedge reset_n)
begin
if (~reset_n)
pre_data_ready <= 1'b0;
else
pre_data_ready <= data_ready;
end
always @ (posedge clk or negedge reset_n)
begin
if (~reset_n)
irq <= 1'b0;
else if (~pre_data_ready & data_ready)
irq <= 1'b1;
else if (~s_cs_n & s_write)
irq <= 1'b0; // write any valud to clear interrupt flga
end
IRDA_RECEIVE_Terasic IRDA_RECEIVE_Terasic_inst(
.iCLK(clk), //clk 50MHz
.iRST_n(reset_n), //reset
.iIRDA(ir), //IRDA code input
.iREAD(~s_cs_n & s_read), //read command
.oDATA_REAY(data_ready), //data ready
.oDATA(s_readdata) //decode data output
);
endmodule
|
module IRDA_RECEIVE_Terasic(
iCLK, //clk 50MHz
iRST_n, //reset
iIRDA, //IRDA code input
iREAD, //read command
oDATA_REAY, //data ready
oDATA //decode data output
);
///////////////parameter///////////////
parameter IDLE = 2'b00; //always high voltage level
parameter GUIDANCE = 2'b01; //9 ms low voltage and 4.5 ms high voltage
parameter DATAREAD = 2'b10; //0.6ms low voltage start and with 0.52ms high voltage is 0,with 1.66ms high voltage is 1, 32bit in sum.
parameter IDLE_HIGH_DUR = 262143; // data_count 131071*0.02us = 5.24ms, threshold for DATAREAD-----> IDLE
parameter GUIDE_LOW_DUR = 230000; // idle_count 230000*0.02us = 4.60ms, threshold for IDLE--------->GUIDANCE
parameter GUIDE_HIGH_DUR = 210000; // state_count 210000*0.02us = 4.20ms, 4.5-4.2 = 0.3ms<BIT_AVAILABLE_DUR = 0.4ms,threshold for GUIDANCE------->DATAREAD
parameter DATA_HIGH_DUR = 41500; // data_count 41500 *0.02us = 0.83ms, sample time from the posedge of iIRDA
parameter BIT_AVAILABLE_DUR = 20000; // data_count 20000.0.02us = 0.4ms,the sample bit pointer,can inhibit the interference from iIRDA signal
////////port ////////////
input iCLK; //input clk,50MHz
input iRST_n; //rst
input iIRDA; //Irda RX output decoded data
input iREAD; //read command
output oDATA_REAY; //data ready flag
output [31:0] oDATA; //output data ,32bit
/////////reg or wire/////////////////////
reg DATA_REAY; //data ready flag
reg [17:0] idle_count; //idle_count counter work under data_read state
reg idle_count_flag; //idle_count conter flag
reg [17:0] state_count; //state_count counter work under guide state
reg state_count_flag; //state_count conter flag
reg [17:0] data_count; //data_count counter work under data_read state
reg data_count_flag; //data_count conter flag
reg [5:0] bitcount; //sample bit pointer
reg [1:0] state; //state reg
reg [31:0] DATA; //data reg
reg [31:0] DATA_BUF; //data buf
reg [31:0] oDATA; //data output reg
////////////////////stuctural code//////////////////////////////////
// initial
initial
begin
state = IDLE; //state initial
DATA_REAY = 1'b0; //set the dataready flag to 0
bitcount = 0; //set the data reg pointer to 0
DATA = 0; //clear the data reg
DATA_BUF = 0; //clear the data buf
state_count = 0; //guide high level time counter 0
data_count = 0; //dataread state time counter 0
idle_count = 0; //start low voltage level time counter 0
end
assign oDATA_REAY = DATA_REAY;
//idle count work on iclk under IDLE state only
always @(negedge iRST_n or posedge iCLK )
begin
if(!iRST_n)
idle_count <= 0; //rst
else
begin
if( idle_count_flag ) //the counter start when the flag is set 1
idle_count <= idle_count + 1'b1;
else
idle_count <= 0; //the counter stop when the flag is set 0
end
end
//idle counter switch when iIRDA is low under IDLE state
always @( negedge iRST_n or posedge iCLK)
begin
if( !iRST_n )
idle_count_flag <= 1'b0; // reset off
else
begin
if((state == IDLE) &&(!iIRDA)) // negedge start
idle_count_flag <= 1'b1; //on
else //negedge
idle_count_flag <= 1'b0; //off
end
end
//state count work on iclk under GUIDE state only
always @(negedge iRST_n or posedge iCLK )
begin
if(!iRST_n)
state_count <= 0; //rst
else
begin
if( state_count_flag ) //the counter start when the flag is set 1
state_count <= state_count + 1'b1;
else
state_count <= 0; //the counter stop when the flag is set 0
end
end
//state counter switch when iIRDA is high under GUIDE state
always @( negedge iRST_n or posedge iCLK)
begin
if( !iRST_n )
state_count_flag <= 1'b0; // reset off
else
begin
if((state == GUIDANCE) &&(iIRDA)) // posedge start
state_count_flag <= 1'b1; //on
else //negedge
state_count_flag <= 1'b0; //off
end
end
//state change between IDLE,GUIDE,DATA_READ according to irda edge or counter
always @(negedge iRST_n or posedge iCLK )
begin
if(!iRST_n)
state <= IDLE; //RST
else
begin
if( (state == IDLE) &&(idle_count > GUIDE_LOW_DUR)) // state chang from IDLE to Guidance when detect the negedge and the low voltage last for >2.6ms
state <= GUIDANCE;
else if ( state == GUIDANCE ) //state change from GUIDANCE to dataread if state_coun>13107 =2.6ms
begin
if( state_count > GUIDE_HIGH_DUR )
state <= DATAREAD;
end
else if(state == DATAREAD) //state change from DATAREAD to IDLE when data_count >IDLE_HIGH_DUR = 5.2ms,or the bit count = 33
begin
if( (data_count >= IDLE_HIGH_DUR ) || (bitcount>= 6'b100001) )
state <= IDLE;
end
else
state <= IDLE; //default
end
end
// data read decode counter based on iCLK
always @(negedge iRST_n or posedge iCLK)
begin
if(!iRST_n)
data_count <= 1'b0; //clear
else
begin
if(data_count_flag)
data_count <= data_count + 1'b1;
else
data_count <= 1'b0; //stop and clear
end
end
//data counter switch
always @(negedge iRST_n or posedge iCLK )
begin
if(!iRST_n)
data_count_flag <= 0; //reset off the counter
else
begin
if(state == DATAREAD)
begin
if(iIRDA)
data_count_flag <= 1'b1; //on when posedge
else
data_count_flag <= 1'b0; //off when negedge
end
else
data_count_flag <= 1'b0; //off when other state
end
end
// data decode base on the value of data_count
always @(negedge iRST_n or posedge iCLK )
begin
if( (!iRST_n) )
DATA <= 0; //rst
else
begin
if (state == DATAREAD )
begin
if(data_count >= DATA_HIGH_DUR )//2^15 = 32767*0.02us = 0.64us
DATA[bitcount-1'b1] <= 1'b1; //>0.52ms sample the bit 1
else
begin
if(DATA[bitcount-1'b1]==1)
DATA[bitcount-1'b1] <= DATA[bitcount-1'b1]; //<=0.52 sample the bit 0
else
DATA[bitcount-1'b1] <= 1'b0;
end
end
else
DATA <= 0;
end
end
// data reg pointer counter
always @(negedge iRST_n or posedge iCLK )
begin
if (!iRST_n)
bitcount <= 1'b0; //rst
else
begin
if(state == DATAREAD)
begin
if( data_count == 20000 )
bitcount <= bitcount + 1'b1; //add 1 when iIRDA posedge
end
else
bitcount <= 1'b0;
end
end
// set the data_ready flag
always @(negedge iRST_n or posedge iCLK)
begin
if(!iRST_n)
DATA_REAY <=1'b0 ; //rst
else
begin
if(bitcount == 6'b100000) //32bit sample over
begin
if( DATA[31:24]== ~DATA[23:16])
begin
DATA_BUF <= DATA; //fetch the value to the databuf from the data reg
DATA_REAY <= 1'b1; //set the data ready flag
end
else
DATA_REAY <=1'b0 ; //data error
end
else
DATA_REAY <=1'b0 ; //not ready
end
end
//read data
always @(negedge iRST_n or posedge iCLK)
begin
if(!iRST_n)
oDATA <= 32'b0000; //rst
else
begin
if(iREAD && DATA_REAY)
oDATA <= DATA_BUF; //output
end
end
endmodule
|
module r8051 (
input wire clk,
input wire rst,
input wire cpu_en,
input wire cpu_restart,
output reg rom_en,
output reg [15:0] rom_addr,
input wire [7:0] rom_byte,
output wire ram_rd_en_data,
output wire ram_rd_en_sfr,
`ifdef TYPE8052
output wire ram_rd_en_idata,
`endif
output wire ram_rd_en_xdata,
output wire [15:0] ram_rd_addr,
input wire [7:0] ram_rd_byte,
input wire ram_rd_vld,
output wire ram_wr_en_data,
output wire ram_wr_en_sfr,
`ifdef TYPE8052
output wire ram_wr_en_idata,
`endif
output wire ram_wr_en_xdata,
output wire [15:0] ram_wr_addr,
output wire [7:0] ram_wr_byte
);
`include "instruction.v"
/*********************************************************/
//register definition
reg rd_wait;
reg [7:0] cmd1;
reg [7:0] cmd2;
reg [2:0] cmd_flag;
reg [15:0] pc;
reg [7:0] acc;
reg psw_ov;
reg psw_ac;
reg psw_c;
reg [3:0] psw_other;
reg [15:0] dp;
reg [7:0] sp;
reg [7:0] b;
reg same_flag;
reg [7:0] same_byte;
reg [7:0] data1;
/*********************************************************/
//wire definition
wire work_en;
wire [7:0] cmd0;
wire [7:0] cmda;
wire [7:0] cmdb;
wire [7:0] cmdc;
reg pc_en;
wire [15:0] pc_add1;
wire [15:0] code_base;
wire [15:0] code_rel;
wire [15:0] code_addr;
wire length1;
wire length2r1;
wire length2;
wire length3;
wire rd_en_data_sfr;
wire rd_en_data_idata;
wire rd_en_xdata;
wire rd_en_data;
wire rd_en_sfr;
`ifdef TYPE8052
wire rd_en_idata;
`endif
wire same_flag_data;
wire same_flag_sfr;
`ifdef TYPE8052
wire same_flag_idata;
`endif
wire same_flag_xdata;
wire read_internal;
reg [15:0] rd_addr;
wire use_psw_rs;
wire use_dp;
wire use_acc;
wire use_sp;
wire wait_en;
wire wr_en_data_sfr;
wire wr_en_data_idata;
wire wr_en_xdata;
wire wr_en_data;
wire wr_en_sfr;
`ifdef TYPE8052
wire wr_en_idata;
`endif
wire write_internal;
reg [15:0] wr_addr;
reg [7:0] wr_bit_byte;
reg [7:0] wr_byte;
reg [7:0] add_a;
reg [7:0] add_b;
reg add_c;
reg sub_flag;
wire bit_ac;
wire [3:0] low;
wire [3:0] high;
wire bit_c;
wire bit_high;
wire bit_ov;
wire [7:0] add_byte;
wire [15:0] mult;
wire [7:0] and_out;
wire [7:0] or_out;
wire [7:0] xor_out;
wire wr_acc;
wire psw_p;
wire [1:0] psw_rs;
wire wr_psw_rs;
wire [7:0] psw;
wire wr_dp;
wire [7:0] sp_sub1;
wire [7:0] sp_add1;
wire wr_sp;
wire [7:0] div_ans;
wire [7:0] div_rem;
reg [7:0] data0;
/*********************************************************/
/*********************************************************/
//work_en
always @ ( posedge clk or posedge rst )
if ( rst )
rd_wait <= #`DEL 1'b0;
else if ( cpu_restart )
rd_wait <= #`DEL 1'b0;
else if ( work_en )
`ifdef TYPE8052
if ( ram_rd_en_data|ram_rd_en_sfr|ram_rd_en_idata|ram_rd_en_xdata )
`else
if ( ram_rd_en_data|ram_rd_en_sfr|ram_rd_en_xdata )
`endif
rd_wait <= #`DEL 1'b1;
else if ( ram_rd_vld )
rd_wait <= #`DEL 1'b0;
else;
else;
assign work_en = ( rd_wait & ~ram_rd_vld ) ? 1'b0 : cpu_en;
/*********************************************************/
/*********************************************************/
//cmd0/cmd1/cmd2 cmda/cmdb/cmdc
assign cmd0 = rom_byte;
always @ ( posedge clk or posedge rst )
if ( rst )
cmd1 <= #`DEL 8'b0;
else if ( work_en )
cmd1 <= #`DEL cmd0;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
cmd2 <= #`DEL 8'b0;
else if ( work_en )
cmd2 <= #`DEL cmdb;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
cmd_flag <= #`DEL 3'b1;
else if ( cpu_restart )
cmd_flag <= #`DEL 3'b1;
else if ( work_en )
if ( wait_en )
cmd_flag <= {1'b0,cmd_flag[1:0]};
else if ( length2|length2r1 )
cmd_flag <= #`DEL 3'b101;
else if ( length3 )
cmd_flag <= #`DEL 3'b100;
else
cmd_flag <= #`DEL { cmd_flag[1:0],1'b1};
else;
assign cmda = cmd_flag[1] ? cmd0 : 8'b0;
assign cmdb = cmd_flag[2] ? cmd1 : 8'b0;
assign cmdc = cmd2;
/*********************************************************/
/*********************************************************/
//rom_en rom_addr
always @*
if ( ~work_en )
pc_en = 1'b0;
else if ( wait_en|length2r1 )
pc_en = 1'b0;
else
pc_en = 1'b1;
always @ ( posedge clk or posedge rst )
if ( rst )
pc <= #`DEL 16'd0;
else if ( cpu_restart )
pc <= #`DEL 16'd0;
else if ( work_en )
if ( pc_en )
pc <= #`DEL pc_add1;
else;
else;
assign pc_add1 = rom_addr + 1'b1;
always @*
if ( ~work_en )
rom_en = 1'b0;
else if ( wait_en )
rom_en = 1'b0;
else if ( length2r1 )
rom_en = movc_a_dp(cmda)|movc_a_pc(cmda);
else
rom_en = 1'b1;
assign code_base = movc_a_dp(cmda) ? dp : pc;
assign code_rel = 1'b0 ? {{8{cmd0[7]}},cmd0} : {{8{acc[7]}},acc};
assign code_addr = code_base + code_rel;
always @*
rom_addr = ( movc_a_dp(cmda)|movc_a_pc(cmda) ) ? code_addr : pc;
/*********************************************************/
/*********************************************************/
//command length
assign length1 = mov_a_rn(cmda)|mov_rn_a(cmda)|mov_ri_a(cmda)|movx_a_dp(cmda)|movx_ri_a(cmda)|movx_dp_a(cmda)|xch_a_rn(cmda);
assign length2r1 = mov_a_ri(cmda)|movc_a_dp(cmda)|movc_a_pc(cmda)|movx_a_ri(cmda)|xch_a_ri(cmda)|xchd(cmda);
assign length2 = mov_a_di(cmda)|mov_a_da(cmda)|mov_rn_di(cmda)|mov_rn_da(cmda)|mov_di_a(cmda)|mov_di_rn(cmda)|mov_di_ri(cmda)|mov_ri_di(cmda)|mov_ri_da(cmda)|push(cmda)|pop(cmda)|xch_a_di(cmda);
assign length3 = mov_di_di(cmda)|mov_di_da(cmda)|mov_dp_da(cmda);
/*********************************************************/
/*********************************************************/
//ram_rd_en ram_rd_addr
assign rd_en_data_sfr = mov_a_rn(cmda)|mov_a_di(cmdb)|mov_a_ri(cmda)|mov_rn_di(cmdb)|mov_di_rn(cmda)|mov_di_di(cmdb)|mov_di_ri(cmda)|mov_ri_a(cmda)|mov_ri_di(cmda)|mov_ri_di(cmdb)|mov_ri_da(cmda)|movx_a_ri(cmda)|movx_ri_a(cmda)|push(cmdb)|pop(cmda)|xch_a_rn(cmda)|xch_a_di(cmdb)|xch_a_ri(cmda)|xchd(cmda);
assign rd_en_data_idata = mov_a_ri(cmdb)|mov_di_ri(cmdb)|xch_a_ri(cmda)|xchd(cmdb);
assign rd_en_xdata = movx_a_ri(cmdb)|movx_a_dp(cmda);
assign rd_en_data = (rd_en_data_sfr|rd_en_data_idata) & ~rd_addr[7];
`ifdef TYPE8052
assign rd_en_sfr = rd_en_data_sfr & rd_addr[7];
assign rd_en_idata = rd_en_data_idata & rd_addr[7];
`else
assign rd_en_sfr = (rd_en_data_sfr|rd_en_data_idata) & rd_addr[7];
`endif
assign same_flag_data = rd_en_data & wr_en_data & (rd_addr[7:0]==wr_addr[7:0]);
assign same_flag_sfr = rd_en_sfr & wr_en_sfr & (rd_addr[7:0]==wr_addr[7:0]);
`ifdef TYPE8052
assign same_flag_idata = rd_en_idata & wr_en_idata & (rd_addr[7:0]==wr_addr[7:0]);
`endif
assign same_flag_xdata = rd_en_xdata & wr_en_xdata & (rd_addr[15:0]==wr_addr[15:0]);
assign read_internal = rd_en_sfr & ( (rd_addr[7:0]==8'he0)|(rd_addr[7:0]==8'hd0)|(rd_addr[7:0]==8'h83)|(rd_addr[7:0]==8'h82)|(rd_addr[7:0]==8'h81)|(rd_addr[7:0]==8'hf0) );
assign ram_rd_en_data = work_en & rd_en_data & ~same_flag_data & ~wait_en;
assign ram_rd_en_sfr = work_en & rd_en_sfr & ~same_flag_sfr & ~read_internal & ~wait_en;
`ifdef TYPE8052
assign ram_rd_en_idata = work_en & rd_en_idata & ~same_flag_idata & ~wait_en;
`endif
assign ram_rd_en_xdata = work_en & rd_en_xdata & ~same_flag_xdata & ~wait_en;
always @*
if ( mov_a_rn(cmda)|mov_di_rn(cmda)|xch_a_rn(cmda) )
rd_addr = { psw_rs,cmd0[2:0] };
else if ( mov_a_di(cmdb)|mov_rn_di(cmdb)|mov_di_di(cmdb)|mov_ri_di(cmdb)|push(cmdb)|xch_a_di(cmdb) )
rd_addr = cmd0;
else if ( mov_a_ri(cmda)|mov_di_ri(cmda)|mov_ri_a(cmda)|mov_ri_di(cmda)|mov_ri_da(cmda)|movx_a_ri(cmda)|movx_ri_a(cmda)|xch_a_ri(cmda)|xchd(cmda) )
rd_addr = { psw_rs,2'b0,cmd0[0] };
else if ( mov_a_ri(cmdb)|mov_di_ri(cmdb)|movx_a_ri(cmdb)|xch_a_ri(cmdb)|xchd(cmdb) )
rd_addr = data0;
else if ( movx_a_dp(cmda) )
rd_addr = dp;
else if ( pop(cmda) )
rd_addr = sp;
else
rd_addr = 16'd0;
assign ram_rd_addr = rd_addr;
assign use_psw_rs = mov_a_rn(cmda)|mov_a_ri(cmda)|mov_di_rn(cmda)|mov_di_ri(cmda)|mov_ri_a(cmda)|mov_ri_di(cmda)|mov_ri_da(cmda)|movx_a_ri(cmda)|movx_ri_a(cmda)|xch_a_rn(cmda)|xch_a_ri(cmda);
assign use_dp = movc_a_dp(cmda)|movx_a_dp(cmda);
assign use_acc = movc_a_dp(cmda)|movc_a_pc(cmda);
assign use_sp = pop(cmda);
assign wait_en = (use_psw_rs&wr_psw_rs)|(use_dp&wr_dp)|(use_acc&wr_acc)|(use_sp&wr_sp);
/*********************************************************/
/*********************************************************/
//ram_wr_en ram_wr_addr
assign wr_en_data_sfr = mov_rn_a(cmdb)|mov_rn_di(cmdc)|mov_rn_da(cmdb)|mov_di_a(cmdb)|mov_di_rn(cmdb)|mov_di_di(cmdc)|mov_di_ri(cmdc)|mov_di_da(cmdc)|push(cmdc)|pop(cmdb)|xch_a_rn(cmdb)|xch_a_di(cmdc);
assign wr_en_data_idata = mov_ri_a(cmdb)|mov_ri_di(cmdc)|mov_ri_da(cmdb)|xch_a_ri(cmdc)|xchd(cmdc);
assign wr_en_xdata = movx_ri_a(cmdb)|movx_dp_a(cmdb);
assign wr_en_data = (wr_en_data_sfr|wr_en_data_idata) & ~wr_addr[7];
`ifdef TYPE8052
assign wr_en_sfr = wr_en_data_sfr & wr_addr[7];
assign wr_en_idata = wr_en_data_idata & wr_addr[7];
`else
assign wr_en_sfr = (wr_en_data_sfr|wr_en_data_idata) & wr_addr[7];
`endif
assign write_internal = wr_en_sfr & ( (wr_addr[7:0]==8'he0)|(wr_addr[7:0]==8'hd0)|(wr_addr[7:0]==8'h83)|(wr_addr[7:0]==8'h82)|(wr_addr[7:0]==8'h81)|(wr_addr[7:0]==8'hf0) );
assign ram_wr_en_data = work_en & wr_en_data;
assign ram_wr_en_sfr = work_en & wr_en_sfr & ~write_internal;
`ifdef TYPE8052
assign ram_wr_en_idata = work_en & wr_en_idata;
`endif
assign ram_wr_en_xdata = work_en & wr_en_xdata;
always @*
if ( mov_rn_a(cmdb)|mov_rn_da(cmdb)|xch_a_rn(cmdb) )
wr_addr = { psw_rs,cmd1[2:0] };
else if ( mov_rn_di(cmdc) )
wr_addr = { psw_rs,cmd2[2:0] };
else if ( mov_di_a(cmdb)|mov_di_rn(cmdb)|mov_di_di(cmdc)|pop(cmdb) )
wr_addr = cmd0;
else if ( mov_di_ri(cmdc)|mov_di_da(cmdc)|xch_a_di(cmdc) )
wr_addr = cmd1;
else if ( mov_ri_a(cmdb)|mov_ri_da(cmdb)|movx_ri_a(cmdb) )
wr_addr = data0;
else if ( mov_ri_di(cmdc)|xch_a_ri(cmdc)|xchd(cmdc) )
wr_addr = data1;
else if ( movx_dp_a(cmdb) )
wr_addr = dp;
else if ( push(cmdc) )
wr_addr = sp;
else
wr_addr = 16'd0;
assign ram_wr_addr = wr_addr;
/*********************************************************/
/*********************************************************/
//ram_wr_byte
always @* begin
wr_bit_byte = data0;
end
always @*
if ( mov_rn_a(cmdb)|mov_di_a(cmdb)|mov_ri_a(cmdb)|movx_ri_a(cmdb)|movx_dp_a(cmdb)|xch_a_rn(cmdb)|xch_a_di(cmdc)|xch_a_ri(cmdc) )
wr_byte = acc;
else if ( mov_rn_di(cmdc)|mov_di_rn(cmdb)|mov_di_di(cmdc)|mov_di_ri(cmdc)|mov_ri_di(cmdc)|pop(cmdb) )
wr_byte = data0;
else if ( mov_rn_da(cmdb)|mov_di_da(cmdc)|mov_ri_da(cmdb) )
wr_byte = cmd0;
else if ( xchd(cmdc) )
wr_byte = { data0[7:4],acc[3:0] };
else
wr_byte = 8'd0;
assign ram_wr_byte = wr_byte;
/*********************************************************/
/*********************************************************/
//acc register
always @*
add_a = 8'b0;
always @*
add_b = 8'b0;
always @*
add_c = 1'b0;
always @*
sub_flag = 1'b0;
assign {bit_ac,low} = sub_flag ? (add_a[3:0]-add_b[3:0]-add_c) : (add_a[3:0]+add_b[3:0]+add_c);
assign high = sub_flag ? (add_a[6:4]-add_b[6:4]-bit_ac) : (add_a[6:4]+add_b[6:4]+bit_ac);
assign {bit_c,bit_high} = sub_flag ? (add_a[7]-add_b[7]-high[3]) : (add_a[7]+add_b[7]+high[3]);
assign bit_ov = bit_c ^ high[3];
assign add_byte = {bit_high,high[2:0],low};
assign mult = acc * b;
assign {div_rem,div_ans} = divide(acc,b);
assign and_out = acc & data0;
assign or_out = acc | data0;
assign xor_out = acc ^ data0;
always @ ( posedge clk or posedge rst )
if ( rst )
acc <= #`DEL 8'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'he0 ) )
acc <= #`DEL wr_byte;
else if ( mov_a_rn(cmdb)|mov_a_di(cmdc)|mov_a_ri(cmdc)|movx_a_ri(cmdc)|movx_a_dp(cmdb)|xch_a_rn(cmdb)|xch_a_di(cmdc)|xch_a_ri(cmdc) )
acc <= #`DEL data0;
else if ( mov_a_da(cmdb)|movc_a_dp(cmdb)|movc_a_pc(cmdb) )
acc <= #`DEL cmd0;
else if ( xchd(cmdc) )
acc[3:0] <= #`DEL data0[3:0];
else;
else;
assign wr_acc = (wr_en_sfr & (wr_addr[7:0]==8'he0))|mov_a_rn(cmdb)|mov_a_di(cmdc)|mov_a_ri(cmdc)|mov_a_da(cmdb)|movx_a_ri(cmdc)|movx_a_dp(cmdb)|xch_a_rn(cmdb)|xch_a_di(cmdc)|xch_a_ri(cmdc)|xchd(cmdc);
/*********************************************************/
/*********************************************************/
//psw register
assign psw_p = ^acc;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_ov <= #`DEL 1'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_ov <= #`DEL wr_byte[2];
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_ac <= #`DEL 1'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_ac <= #`DEL wr_byte[6];
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_c <= #`DEL 1'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_c <= #`DEL wr_byte[7];
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_other <= #`DEL 4'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_other <= #`DEL {wr_byte[5:3],wr_byte[1]};
else;
else;
assign psw_rs = psw_other[2:1];
assign wr_psw_rs = wr_en_sfr & (wr_addr[7:0]==8'hd0);
assign psw = {psw_c,psw_ac,psw_other[3:1],psw_ov,psw_other[0],psw_p};
/*********************************************************/
/*********************************************************/
//dp sp registers
always @ ( posedge clk or posedge rst )
if ( rst )
dp <= #`DEL 16'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'h82 ) )
dp[7:0] <= #`DEL wr_byte;
else if ( wr_en_sfr & (wr_addr[7:0]==8'h83 ) )
dp[15:8] <= #`DEL wr_byte;
else if ( mov_dp_da(cmdc) )
dp <= #`DEL {cmd1,cmd0};
else;
else;
assign wr_dp = (wr_en_sfr & ((wr_addr[7:0]==8'h82)|(wr_addr[7:0]==8'h83)));
always @ ( posedge clk or posedge rst )
if ( rst )
sp <= #`DEL 8'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'h81) )
sp <= #`DEL wr_byte;
else if ( push(cmdb) )
sp <= #`DEL sp_add1;
else if ( pop(cmdb) )
sp <= #`DEL sp_sub1;
else;
else;
assign sp_sub1 = sp - 1'b1;
assign sp_add1 = sp + 1'b1;
assign wr_sp = (wr_en_sfr & (wr_addr[7:0]==8'h81));
always @ ( posedge clk or posedge rst )
if ( rst )
b <= #`DEL 8'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hf0) )
b <= #`DEL wr_byte;
else;
else;
/*********************************************************/
/*********************************************************/
//ram output
always @*
if ( same_flag )
data0 = same_byte;
else if ( same_byte[7] )
data0 = acc;
else if ( same_byte[6] )
data0 = psw;
else if ( same_byte[5] )
data0 = dp[15:8];
else if ( same_byte[4] )
data0 = dp[7:0];
else if ( same_byte[3] )
data0 = sp;
else if ( same_byte[2] )
data0 = b;
else
data0 = ram_rd_byte;
always @ ( posedge clk or posedge rst )
if ( rst )
data1 <= #`DEL 8'b0;
else if ( work_en )
data1 <= #`DEL data0;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
same_flag <= #`DEL 1'b0;
else if ( work_en )
`ifdef TYPE8052
if ( same_flag_data|same_flag_sfr|same_flag_idata|same_flag_xdata )
`else
if ( same_flag_data|same_flag_sfr|same_flag_xdata )
`endif
same_flag <= #`DEL 1'b1;
else
same_flag <= #`DEL 1'b0;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
same_byte <= #`DEL 8'd0;
else if ( work_en )
`ifdef TYPE8052
if ( same_flag_data|same_flag_sfr|same_flag_idata|same_flag_xdata )
`else
if ( same_flag_data|same_flag_sfr|same_flag_xdata )
`endif
same_byte <= #`DEL wr_byte;
else if ( rd_en_sfr & (rd_addr[7:0]==8'he0) ) //acc
same_byte <= #`DEL 1'b1<<7;
else if ( rd_en_sfr & (rd_addr[7:0]==8'hd0) ) //psw
same_byte <= #`DEL 1'b1<<6;
else if ( rd_en_sfr & (rd_addr[7:0]==8'h83) ) //dph
same_byte <= #`DEL 1'b1<<5;
else if ( rd_en_sfr & (rd_addr[7:0]==8'h82) ) //dpl
same_byte <= #`DEL 1'b1<<4;
else if ( rd_en_sfr & (rd_addr[7:0]==8'h81) ) //sp
same_byte <= #`DEL 1'b1<<3;
else if ( rd_en_sfr & (rd_addr[7:0]==8'hf0) ) //b
same_byte <= #`DEL 1'b1<<2;
else
same_byte <= #`DEL 8'b0;
else;
/*********************************************************/
endmodule
|
module r8051 (
input wire clk,
input wire rst,
input wire cpu_en,
input wire cpu_restart,
output reg rom_en,
output reg [15:0] rom_addr,
input wire [7:0] rom_byte,
output wire ram_rd_en_data,
output wire ram_rd_en_sfr,
`ifdef TYPE8052
output wire ram_rd_en_idata,
`endif
output wire ram_rd_en_xdata,
output wire [15:0] ram_rd_addr,
input wire [7:0] ram_rd_byte,
input wire ram_rd_vld,
output wire ram_wr_en_data,
output wire ram_wr_en_sfr,
`ifdef TYPE8052
output wire ram_wr_en_idata,
`endif
output wire ram_wr_en_xdata,
output wire [15:0] ram_wr_addr,
output wire [7:0] ram_wr_byte
);
`include "instruction.v"
/*********************************************************/
//register definition
reg rd_wait;
reg [7:0] cmd1;
reg [7:0] cmd2;
reg [2:0] cmd_flag;
reg [15:0] pc;
reg [7:0] acc;
reg psw_ov;
reg psw_ac;
reg psw_c;
reg [3:0] psw_other;
reg [15:0] dp;
reg [7:0] sp;
reg [7:0] b;
reg same_flag;
reg [7:0] same_byte;
reg [7:0] data1;
/*********************************************************/
//wire definition
wire work_en;
wire [7:0] cmd0;
wire [7:0] cmda;
wire [7:0] cmdb;
wire [7:0] cmdc;
reg pc_en;
wire [15:0] pc_add1;
wire [15:0] code_base;
wire [15:0] code_rel;
wire [15:0] code_addr;
wire length1;
wire length2r1;
wire length2;
wire length3;
wire rd_en_data_sfr;
wire rd_en_data_idata;
wire rd_en_xdata;
wire rd_en_data;
wire rd_en_sfr;
`ifdef TYPE8052
wire rd_en_idata;
`endif
wire same_flag_data;
wire same_flag_sfr;
`ifdef TYPE8052
wire same_flag_idata;
`endif
wire same_flag_xdata;
wire read_internal;
reg [15:0] rd_addr;
wire use_psw_rs;
wire use_dp;
wire use_acc;
wire use_sp;
wire wait_en;
wire wr_en_data_sfr;
wire wr_en_data_idata;
wire wr_en_xdata;
wire wr_en_data;
wire wr_en_sfr;
`ifdef TYPE8052
wire wr_en_idata;
`endif
wire write_internal;
reg [15:0] wr_addr;
reg [7:0] wr_bit_byte;
reg [7:0] wr_byte;
reg [7:0] add_a;
reg [7:0] add_b;
reg add_c;
reg sub_flag;
wire bit_ac;
wire [3:0] low;
wire [3:0] high;
wire bit_c;
wire bit_high;
wire bit_ov;
wire [7:0] add_byte;
wire [15:0] mult;
wire [7:0] and_out;
wire [7:0] or_out;
wire [7:0] xor_out;
wire wr_acc;
wire psw_p;
wire [1:0] psw_rs;
wire wr_psw_rs;
wire [7:0] psw;
wire wr_dp;
wire [7:0] sp_sub1;
wire [7:0] sp_add1;
wire wr_sp;
wire [7:0] div_ans;
wire [7:0] div_rem;
reg [7:0] data0;
/*********************************************************/
/*********************************************************/
//work_en
always @ ( posedge clk or posedge rst )
if ( rst )
rd_wait <= #`DEL 1'b0;
else if ( cpu_restart )
rd_wait <= #`DEL 1'b0;
else if ( work_en )
`ifdef TYPE8052
if ( ram_rd_en_data|ram_rd_en_sfr|ram_rd_en_idata|ram_rd_en_xdata )
`else
if ( ram_rd_en_data|ram_rd_en_sfr|ram_rd_en_xdata )
`endif
rd_wait <= #`DEL 1'b1;
else if ( ram_rd_vld )
rd_wait <= #`DEL 1'b0;
else;
else;
assign work_en = ( rd_wait & ~ram_rd_vld ) ? 1'b0 : cpu_en;
/*********************************************************/
/*********************************************************/
//cmd0/cmd1/cmd2 cmda/cmdb/cmdc
assign cmd0 = rom_byte;
always @ ( posedge clk or posedge rst )
if ( rst )
cmd1 <= #`DEL 8'b0;
else if ( work_en )
cmd1 <= #`DEL cmd0;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
cmd2 <= #`DEL 8'b0;
else if ( work_en )
cmd2 <= #`DEL cmdb;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
cmd_flag <= #`DEL 3'b1;
else if ( cpu_restart )
cmd_flag <= #`DEL 3'b1;
else if ( work_en )
if ( wait_en )
cmd_flag <= {1'b0,cmd_flag[1:0]};
else if ( length2|length2r1 )
cmd_flag <= #`DEL 3'b101;
else if ( length3 )
cmd_flag <= #`DEL 3'b100;
else
cmd_flag <= #`DEL { cmd_flag[1:0],1'b1};
else;
assign cmda = cmd_flag[1] ? cmd0 : 8'b0;
assign cmdb = cmd_flag[2] ? cmd1 : 8'b0;
assign cmdc = cmd2;
/*********************************************************/
/*********************************************************/
//rom_en rom_addr
always @*
if ( ~work_en )
pc_en = 1'b0;
else if ( wait_en|length2r1 )
pc_en = 1'b0;
else
pc_en = 1'b1;
always @ ( posedge clk or posedge rst )
if ( rst )
pc <= #`DEL 16'd0;
else if ( cpu_restart )
pc <= #`DEL 16'd0;
else if ( work_en )
if ( pc_en )
pc <= #`DEL pc_add1;
else;
else;
assign pc_add1 = rom_addr + 1'b1;
always @*
if ( ~work_en )
rom_en = 1'b0;
else if ( wait_en )
rom_en = 1'b0;
else if ( length2r1 )
rom_en = 1'b0;
else
rom_en = 1'b1;
assign code_base = 1'b0 ? dp : pc;
assign code_rel = 1'b0 ? {{8{cmd0[7]}},cmd0} : {{8{acc[7]}},acc};
assign code_addr = code_base + code_rel;
always @*
rom_addr = 1'b0 ? code_addr : pc;
/*********************************************************/
/*********************************************************/
//command length
assign length1 = anl_a_rn(cmda)|orl_a_rn(cmda)|xrl_a_rn(cmda)|clr_a(cmda)|cpl_a(cmda)|rl(cmda)|rlc(cmda)|rr(cmda)|rrc(cmda)|swap(cmda);
assign length2r1 = anl_a_ri(cmda)|orl_a_ri(cmda)|xrl_a_ri(cmda);
assign length2 = anl_a_di(cmda)|anl_a_da(cmda)|anl_di_a(cmda)|orl_a_di(cmda)|orl_a_da(cmda)|orl_di_a(cmda)|xrl_a_di(cmda)|xrl_a_da(cmda)|xrl_di_a(cmda);
assign length3 = anl_di_da(cmda)|orl_di_da(cmda)|xrl_di_da(cmda);
/*********************************************************/
/*********************************************************/
//ram_rd_en ram_rd_addr
assign rd_en_data_sfr = anl_a_rn(cmda)|anl_a_di(cmdb)|anl_a_ri(cmda)|anl_di_a(cmdb)|anl_di_da(cmdb)|orl_a_rn(cmda)|orl_a_di(cmdb)|orl_a_ri(cmda)|orl_di_a(cmdb)|orl_di_da(cmdb)|xrl_a_rn(cmda)|xrl_a_di(cmdb)|xrl_a_ri(cmda)|xrl_di_a(cmdb)|xrl_di_da(cmdb);
assign rd_en_data_idata = anl_a_ri(cmdb)|orl_a_ri(cmdb)|xrl_a_ri(cmdb);
assign rd_en_xdata = 1'b0;
assign rd_en_data = (rd_en_data_sfr|rd_en_data_idata) & ~rd_addr[7];
`ifdef TYPE8052
assign rd_en_sfr = rd_en_data_sfr & rd_addr[7];
assign rd_en_idata = rd_en_data_idata & rd_addr[7];
`else
assign rd_en_sfr = (rd_en_data_sfr|rd_en_data_idata) & rd_addr[7];
`endif
assign same_flag_data = rd_en_data & wr_en_data & (rd_addr[7:0]==wr_addr[7:0]);
assign same_flag_sfr = rd_en_sfr & wr_en_sfr & (rd_addr[7:0]==wr_addr[7:0]);
`ifdef TYPE8052
assign same_flag_idata = rd_en_idata & wr_en_idata & (rd_addr[7:0]==wr_addr[7:0]);
`endif
assign same_flag_xdata = rd_en_xdata & wr_en_xdata & (rd_addr[15:0]==wr_addr[15:0]);
assign read_internal = rd_en_sfr & ( (rd_addr[7:0]==8'he0)|(rd_addr[7:0]==8'hd0)|(rd_addr[7:0]==8'h83)|(rd_addr[7:0]==8'h82)|(rd_addr[7:0]==8'h81)|(rd_addr[7:0]==8'hf0) );
assign ram_rd_en_data = work_en & rd_en_data & ~same_flag_data & ~wait_en;
assign ram_rd_en_sfr = work_en & rd_en_sfr & ~same_flag_sfr & ~read_internal & ~wait_en;
`ifdef TYPE8052
assign ram_rd_en_idata = work_en & rd_en_idata & ~same_flag_idata & ~wait_en;
`endif
assign ram_rd_en_xdata = work_en & rd_en_xdata & ~same_flag_xdata & ~wait_en;
always @*
if ( anl_a_rn(cmda)|orl_a_rn(cmda)|xrl_a_rn(cmda) )
rd_addr = { psw_rs,cmd0[2:0] };
else if ( anl_a_di(cmdb)|anl_di_a(cmdb)|anl_di_da(cmdb)|orl_a_di(cmdb)|orl_di_a(cmdb)|orl_di_da(cmdb)|xrl_a_di(cmdb)|xrl_di_a(cmdb)|xrl_di_da(cmdb) )
rd_addr = cmd0;
else if ( anl_a_ri(cmda)|orl_a_ri(cmda)|xrl_a_ri(cmda) )
rd_addr = { psw_rs,2'b0,cmd0[0] };
else if ( anl_a_ri(cmdb)|orl_a_ri(cmdb)|xrl_a_ri(cmdb) )
rd_addr = data0;
else
rd_addr = 16'd0;
assign ram_rd_addr = rd_addr;
assign use_psw_rs = anl_a_rn(cmda)|anl_a_ri(cmda)|orl_a_rn(cmda)|orl_a_ri(cmda)|xrl_a_rn(cmda)|xrl_a_ri(cmda);
assign use_dp = 1'b0;
assign use_acc = 1'b0;
assign use_sp = 1'b0;
assign wait_en = (use_psw_rs&wr_psw_rs)|(use_dp&wr_dp)|(use_acc&wr_acc)|(use_sp&wr_sp);
/*********************************************************/
/*********************************************************/
//ram_wr_en ram_wr_addr
assign wr_en_data_sfr = anl_di_a(cmdc)|anl_di_da(cmdc)|orl_di_a(cmdc)|orl_di_da(cmdc)|xrl_di_a(cmdc)|xrl_di_da(cmdc);
assign wr_en_data_idata = 1'b0;
assign wr_en_xdata = 1'b0;
assign wr_en_data = (wr_en_data_sfr|wr_en_data_idata) & ~wr_addr[7];
`ifdef TYPE8052
assign wr_en_sfr = wr_en_data_sfr & wr_addr[7];
assign wr_en_idata = wr_en_data_idata & wr_addr[7];
`else
assign wr_en_sfr = (wr_en_data_sfr|wr_en_data_idata) & wr_addr[7];
`endif
assign write_internal = wr_en_sfr & ( (wr_addr[7:0]==8'he0)|(wr_addr[7:0]==8'hd0)|(wr_addr[7:0]==8'h83)|(wr_addr[7:0]==8'h82)|(wr_addr[7:0]==8'h81)|(wr_addr[7:0]==8'hf0) );
assign ram_wr_en_data = work_en & wr_en_data;
assign ram_wr_en_sfr = work_en & wr_en_sfr & ~write_internal;
`ifdef TYPE8052
assign ram_wr_en_idata = work_en & wr_en_idata;
`endif
assign ram_wr_en_xdata = work_en & wr_en_xdata;
always @*
if ( anl_di_a(cmdc)|anl_di_da(cmdc)|orl_di_a(cmdc)|orl_di_da(cmdc)|xrl_di_a(cmdc)|xrl_di_da(cmdc) )
wr_addr = cmd1;
else
wr_addr = 16'd0;
assign ram_wr_addr = wr_addr;
/*********************************************************/
/*********************************************************/
//ram_wr_byte
always @* begin
wr_bit_byte = data0;
end
always @*
if ( anl_di_a(cmdc)|anl_di_da(cmdc) )
wr_byte = and_out;
else if ( orl_di_a(cmdc)|orl_di_da(cmdc) )
wr_byte = or_out;
else if ( xrl_di_a(cmdc)|xrl_di_da(cmdc) )
wr_byte = xor_out;
else
wr_byte = 8'd0;
assign ram_wr_byte = wr_byte;
/*********************************************************/
/*********************************************************/
//acc register
always @*
add_a = 8'b0;
always @*
add_b = 8'b0;
always @*
add_c = 1'b0;
always @*
sub_flag = 1'b0;
assign {bit_ac,low} = sub_flag ? (add_a[3:0]-add_b[3:0]-add_c) : (add_a[3:0]+add_b[3:0]+add_c);
assign high = sub_flag ? (add_a[6:4]-add_b[6:4]-bit_ac) : (add_a[6:4]+add_b[6:4]+bit_ac);
assign {bit_c,bit_high} = sub_flag ? (add_a[7]-add_b[7]-high[3]) : (add_a[7]+add_b[7]+high[3]);
assign bit_ov = bit_c ^ high[3];
assign add_byte = {bit_high,high[2:0],low};
assign mult = acc * b;
assign {div_rem,div_ans} = divide(acc,b);
assign and_out = ( anl_di_da(cmdc) ? cmd0 : acc ) & ( anl_a_da(cmdb) ? cmd0 : data0 );
assign or_out = ( orl_di_da(cmdc) ? cmd0 : acc ) | ( orl_a_da(cmdb) ? cmd0 : data0 );
assign xor_out = ( xrl_di_da(cmdc) ? cmd0 : acc ) ^ ( xrl_a_da(cmdb) ? cmd0 : data0 );
always @ ( posedge clk or posedge rst )
if ( rst )
acc <= #`DEL 8'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'he0 ) )
acc <= #`DEL wr_byte;
else if ( anl_a_rn(cmdb)|anl_a_di(cmdc)|anl_a_ri(cmdc)|anl_a_da(cmdb) )
acc <= #`DEL and_out;
else if ( orl_a_rn(cmdb)|orl_a_di(cmdc)|orl_a_ri(cmdc)|orl_a_da(cmdb) )
acc <= #`DEL or_out;
else if ( xrl_a_rn(cmdb)|xrl_a_di(cmdc)|xrl_a_ri(cmdc)|xrl_a_da(cmdb) )
acc <= #`DEL xor_out;
else if ( clr_a(cmdb) )
acc <= #`DEL 8'b0;
else if ( cpl_a(cmdb) )
acc <= #`DEL ~acc;
else if ( rl(cmdb) )
acc <= #`DEL {acc[6:0],acc[7]};
else if ( rlc(cmdb) )
acc <= #`DEL {acc[6:0],psw_c};
else if ( rr(cmdb) )
acc <= #`DEL {acc[0],acc[7:1]};
else if ( rrc(cmdb) )
acc <= #`DEL {psw_c,acc[7:1]};
else if ( swap(cmdb) )
acc <= #`DEL {acc[3:0],acc[7:4]};
else;
else;
assign wr_acc = (wr_en_sfr & (wr_addr[7:0]==8'he0))|anl_a_rn(cmdb)|anl_a_di(cmdc)|anl_a_ri(cmdc)|anl_a_da(cmdb)|orl_a_rn(cmdb)|orl_a_di(cmdc)|orl_a_ri(cmdc)|orl_a_da(cmdb)|xrl_a_rn(cmdb)|xrl_a_di(cmdc)|xrl_a_ri(cmdc)|xrl_a_da(cmdb)|clr_a(cmdb)|cpl_a(cmdb)|rl(cmdb)|rlc(cmdb)|rr(cmdb)|rrc(cmdb)|swap(cmdb);
/*********************************************************/
/*********************************************************/
//psw register
assign psw_p = ^acc;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_ov <= #`DEL 1'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_ov <= #`DEL wr_byte[2];
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_ac <= #`DEL 1'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_ac <= #`DEL wr_byte[6];
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_c <= #`DEL 1'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_c <= #`DEL wr_byte[7];
else if ( rlc(cmdb) )
psw_c <= #`DEL acc[7];
else if ( rrc(cmdb) )
psw_c <= #`DEL acc[0];
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_other <= #`DEL 4'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_other <= #`DEL {wr_byte[5:3],wr_byte[1]};
else;
else;
assign psw_rs = psw_other[2:1];
assign wr_psw_rs = wr_en_sfr & (wr_addr[7:0]==8'hd0);
assign psw = {psw_c,psw_ac,psw_other[3:1],psw_ov,psw_other[0],psw_p};
/*********************************************************/
/*********************************************************/
//dp sp registers
always @ ( posedge clk or posedge rst )
if ( rst )
dp <= #`DEL 16'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'h82 ) )
dp[7:0] <= #`DEL wr_byte;
else if ( wr_en_sfr & (wr_addr[7:0]==8'h83 ) )
dp[15:8] <= #`DEL wr_byte;
else;
else;
assign wr_dp = (wr_en_sfr & ((wr_addr[7:0]==8'h82)|(wr_addr[7:0]==8'h83)));
always @ ( posedge clk or posedge rst )
if ( rst )
sp <= #`DEL 8'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'h81) )
sp <= #`DEL wr_byte;
else;
else;
assign sp_sub1 = sp - 1'b1;
assign sp_add1 = sp + 1'b1;
assign wr_sp = (wr_en_sfr & (wr_addr[7:0]==8'h81));
always @ ( posedge clk or posedge rst )
if ( rst )
b <= #`DEL 8'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hf0) )
b <= #`DEL wr_byte;
else;
else;
/*********************************************************/
/*********************************************************/
//ram output
always @*
if ( same_flag )
data0 = same_byte;
else if ( same_byte[7] )
data0 = acc;
else if ( same_byte[6] )
data0 = psw;
else if ( same_byte[5] )
data0 = dp[15:8];
else if ( same_byte[4] )
data0 = dp[7:0];
else if ( same_byte[3] )
data0 = sp;
else if ( same_byte[2] )
data0 = b;
else
data0 = ram_rd_byte;
always @ ( posedge clk or posedge rst )
if ( rst )
data1 <= #`DEL 8'b0;
else if ( work_en )
data1 <= #`DEL data0;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
same_flag <= #`DEL 1'b0;
else if ( work_en )
`ifdef TYPE8052
if ( same_flag_data|same_flag_sfr|same_flag_idata|same_flag_xdata )
`else
if ( same_flag_data|same_flag_sfr|same_flag_xdata )
`endif
same_flag <= #`DEL 1'b1;
else
same_flag <= #`DEL 1'b0;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
same_byte <= #`DEL 8'd0;
else if ( work_en )
`ifdef TYPE8052
if ( same_flag_data|same_flag_sfr|same_flag_idata|same_flag_xdata )
`else
if ( same_flag_data|same_flag_sfr|same_flag_xdata )
`endif
same_byte <= #`DEL wr_byte;
else if ( rd_en_sfr & (rd_addr[7:0]==8'he0) ) //acc
same_byte <= #`DEL 1'b1<<7;
else if ( rd_en_sfr & (rd_addr[7:0]==8'hd0) ) //psw
same_byte <= #`DEL 1'b1<<6;
else if ( rd_en_sfr & (rd_addr[7:0]==8'h83) ) //dph
same_byte <= #`DEL 1'b1<<5;
else if ( rd_en_sfr & (rd_addr[7:0]==8'h82) ) //dpl
same_byte <= #`DEL 1'b1<<4;
else if ( rd_en_sfr & (rd_addr[7:0]==8'h81) ) //sp
same_byte <= #`DEL 1'b1<<3;
else if ( rd_en_sfr & (rd_addr[7:0]==8'hf0) ) //b
same_byte <= #`DEL 1'b1<<2;
else
same_byte <= #`DEL 8'b0;
else;
/*********************************************************/
endmodule
|
module r8051 (
input wire clk,
input wire rst,
input wire cpu_en,
input wire cpu_restart,
output reg rom_en,
output reg [15:0] rom_addr,
input wire [7:0] rom_byte,
input wire rom_vld,
output wire ram_rd_en_data,
output wire ram_rd_en_sfr,
`ifdef TYPE8052
output wire ram_rd_en_idata,
`endif
output wire ram_rd_en_xdata,
output wire [15:0] ram_rd_addr,
input wire [7:0] ram_rd_byte,
input wire ram_rd_vld,
output wire ram_wr_en_data,
output wire ram_wr_en_sfr,
`ifdef TYPE8052
output wire ram_wr_en_idata,
`endif
output wire ram_wr_en_xdata,
output wire [15:0] ram_wr_addr,
output wire [7:0] ram_wr_byte
);
`include "instruction.v"
/*********************************************************/
//register definition
reg rd_wait;
reg rom_wait;
reg [7:0] cmd1;
reg [7:0] cmd2;
reg [2:0] cmd_flag;
reg [15:0] pc;
reg [7:0] acc;
reg psw_ov;
reg psw_ac;
reg psw_c;
reg [3:0] psw_other;
reg [15:0] dp;
reg [7:0] sp;
reg [7:0] b;
reg same_flag;
reg [7:0] same_byte;
reg [7:0] data1;
/*********************************************************/
//wire definition
wire work_en;
wire [7:0] cmd0;
wire [7:0] cmda;
wire [7:0] cmdb;
wire [7:0] cmdc;
reg pc_en;
wire [15:0] pc_add1;
wire [15:0] code_base;
wire [15:0] code_rel;
wire [15:0] code_addr;
wire length1;
wire length2r1;
wire length2;
wire length3;
wire rd_en_data_sfr;
wire rd_en_data_idata;
wire rd_en_xdata;
wire rd_en_data;
wire rd_en_sfr;
`ifdef TYPE8052
wire rd_en_idata;
`endif
wire same_flag_data;
wire same_flag_sfr;
`ifdef TYPE8052
wire same_flag_idata;
`endif
wire same_flag_xdata;
wire read_internal;
reg [15:0] rd_addr;
wire use_psw_rs;
wire use_dp;
wire use_acc;
wire use_sp;
wire wait_en;
wire wr_en_data_sfr;
wire wr_en_data_idata;
wire wr_en_xdata;
wire wr_en_data;
wire wr_en_sfr;
`ifdef TYPE8052
wire wr_en_idata;
`endif
wire write_internal;
reg [15:0] wr_addr;
reg [7:0] wr_bit_byte;
reg [7:0] wr_byte;
reg [7:0] add_a;
reg [7:0] add_b;
reg add_c;
reg sub_flag;
wire bit_ac;
wire [3:0] low;
wire [3:0] high;
wire bit_c;
wire bit_high;
wire bit_ov;
wire [7:0] add_byte;
wire [15:0] mult;
wire [7:0] and_out;
wire [7:0] or_out;
wire [7:0] xor_out;
wire wr_acc;
wire psw_p;
wire [1:0] psw_rs;
wire wr_psw_rs;
wire [7:0] psw;
wire wr_dp;
wire [7:0] sp_sub1;
wire [7:0] sp_add1;
wire wr_sp;
wire [7:0] div_ans;
wire [7:0] div_rem;
reg [7:0] data0;
/*********************************************************/
/*********************************************************/
//work_en
always @ ( posedge clk or posedge rst )
if ( rst )
rd_wait <= #`DEL 1'b0;
else if ( cpu_restart )
rd_wait <= #`DEL 1'b0;
else if ( work_en )
`ifdef TYPE8052
if ( ram_rd_en_data|ram_rd_en_sfr|ram_rd_en_idata|ram_rd_en_xdata )
`else
if ( ram_rd_en_data|ram_rd_en_sfr|ram_rd_en_xdata )
`endif
rd_wait <= #`DEL 1'b1;
else if ( ram_rd_vld )
rd_wait <= #`DEL 1'b0;
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
rom_wait <= #`DEL 1'b0;
else if ( cpu_restart )
rom_wait <= #`DEL 1'b0;
else if ( work_en )
if ( rom_en )
rom_wait <= #`DEL 1'b1;
else if ( rom_vld )
rom_wait <= #`DEL 1'b0;
else;
else;
assign work_en = ( ( rd_wait & ~ram_rd_vld )|( rom_wait & ~rom_vld ) ) ? 1'b0 : cpu_en;
/*********************************************************/
/*********************************************************/
//cmd0/cmd1/cmd2 cmda/cmdb/cmdc
assign cmd0 = rom_byte;
always @ ( posedge clk or posedge rst )
if ( rst )
cmd1 <= #`DEL 8'b0;
else if ( work_en )
cmd1 <= #`DEL cmd0;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
cmd2 <= #`DEL 8'b0;
else if ( work_en )
cmd2 <= #`DEL cmdb;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
cmd_flag <= #`DEL 3'b1;
else if ( cpu_restart )
cmd_flag <= #`DEL 3'b1;
else if ( work_en )
if ( wait_en )
cmd_flag <= {1'b0,cmd_flag[1:0]};
else if ( length2|length2r1 )
cmd_flag <= #`DEL 3'b101;
else if ( length3 )
cmd_flag <= #`DEL 3'b100;
else
cmd_flag <= #`DEL { cmd_flag[1:0],1'b1};
else;
assign cmda = cmd_flag[1] ? cmd0 : 8'b0;
assign cmdb = cmd_flag[2] ? cmd1 : 8'b0;
assign cmdc = cmd2;
/*********************************************************/
/*********************************************************/
//rom_en rom_addr
always @*
if ( ~work_en )
pc_en = 1'b0;
else if ( wait_en|length2r1 )
pc_en = 1'b0;
else
pc_en = 1'b1;
always @ ( posedge clk or posedge rst )
if ( rst )
pc <= #`DEL 16'd0;
else if ( cpu_restart )
pc <= #`DEL 16'd0;
else if ( work_en )
if ( pc_en )
pc <= #`DEL pc_add1;
else;
else;
assign pc_add1 = rom_addr + 1'b1;
always @*
if ( ~work_en )
rom_en = 1'b0;
else if ( wait_en )
rom_en = 1'b0;
else if ( length2r1 )
rom_en = 1'b0;
else
rom_en = 1'b1;
assign code_base = 1'b0 ? dp : pc;
assign code_rel = 1'b0 ? {{8{cmd0[7]}},cmd0} : {{8{acc[7]}},acc};
assign code_addr = code_base + code_rel;
always @*
rom_addr = 1'b0 ? code_addr : pc;
/*********************************************************/
/*********************************************************/
//command length
assign length1 = 1'b0;
assign length2r1 = 1'b0;
assign length2 = 1'b0;
assign length3 = 1'b0;
/*********************************************************/
/*********************************************************/
//ram_rd_en ram_rd_addr
assign rd_en_data_sfr = 1'b0;
assign rd_en_data_idata = 1'b0;
assign rd_en_xdata = 1'b0;
assign rd_en_data = (rd_en_data_sfr|rd_en_data_idata) & ~rd_addr[7];
`ifdef TYPE8052
assign rd_en_sfr = rd_en_data_sfr & rd_addr[7];
assign rd_en_idata = rd_en_data_idata & rd_addr[7];
`else
assign rd_en_sfr = (rd_en_data_sfr|rd_en_data_idata) & rd_addr[7];
`endif
assign same_flag_data = rd_en_data & wr_en_data & (rd_addr[7:0]==wr_addr[7:0]);
assign same_flag_sfr = rd_en_sfr & wr_en_sfr & (rd_addr[7:0]==wr_addr[7:0]);
`ifdef TYPE8052
assign same_flag_idata = rd_en_idata & wr_en_idata & (rd_addr[7:0]==wr_addr[7:0]);
`endif
assign same_flag_xdata = rd_en_xdata & wr_en_xdata & (rd_addr[15:0]==wr_addr[15:0]);
assign read_internal = rd_en_sfr & ( (rd_addr[7:0]==8'he0)|(rd_addr[7:0]==8'hd0)|(rd_addr[7:0]==8'h83)|(rd_addr[7:0]==8'h82)|(rd_addr[7:0]==8'h81)|(rd_addr[7:0]==8'hf0) );
assign ram_rd_en_data = work_en & rd_en_data & ~same_flag_data & ~wait_en;
assign ram_rd_en_sfr = work_en & rd_en_sfr & ~same_flag_sfr & ~read_internal & ~wait_en;
`ifdef TYPE8052
assign ram_rd_en_idata = work_en & rd_en_idata & ~same_flag_idata & ~wait_en;
`endif
assign ram_rd_en_xdata = work_en & rd_en_xdata & ~same_flag_xdata & ~wait_en;
always @*
rd_addr = 16'd0;
assign ram_rd_addr = rd_addr;
assign use_psw_rs = 1'b0;
assign use_dp = 1'b0;
assign use_acc = 1'b0;
assign use_sp = 1'b0;
assign wait_en = (use_psw_rs&wr_psw_rs)|(use_dp&wr_dp)|(use_acc&wr_acc)|(use_sp&wr_sp);
/*********************************************************/
/*********************************************************/
//ram_wr_en ram_wr_addr
assign wr_en_data_sfr = 1'b0;
assign wr_en_data_idata = 1'b0;
assign wr_en_xdata = 1'b0;
assign wr_en_data = (wr_en_data_sfr|wr_en_data_idata) & ~wr_addr[7];
`ifdef TYPE8052
assign wr_en_sfr = wr_en_data_sfr & wr_addr[7];
assign wr_en_idata = wr_en_data_idata & wr_addr[7];
`else
assign wr_en_sfr = (wr_en_data_sfr|wr_en_data_idata) & wr_addr[7];
`endif
assign write_internal = wr_en_sfr & ( (wr_addr[7:0]==8'he0)|(wr_addr[7:0]==8'hd0)|(wr_addr[7:0]==8'h83)|(wr_addr[7:0]==8'h82)|(wr_addr[7:0]==8'h81)|(wr_addr[7:0]==8'hf0) );
assign ram_wr_en_data = work_en & wr_en_data;
assign ram_wr_en_sfr = work_en & wr_en_sfr & ~write_internal;
`ifdef TYPE8052
assign ram_wr_en_idata = work_en & wr_en_idata;
`endif
assign ram_wr_en_xdata = work_en & wr_en_xdata;
always @*
wr_addr = 16'd0;
assign ram_wr_addr = wr_addr;
/*********************************************************/
/*********************************************************/
//ram_wr_byte
always @* begin
wr_bit_byte = data0;
end
always @*
wr_byte = 8'd0;
assign ram_wr_byte = wr_byte;
/*********************************************************/
/*********************************************************/
//acc register
always @*
add_a = 8'b0;
always @*
add_b = 8'b0;
always @*
add_c = 1'b0;
always @*
sub_flag = 1'b0;
assign {bit_ac,low} = sub_flag ? (add_a[3:0]-add_b[3:0]-add_c) : (add_a[3:0]+add_b[3:0]+add_c);
assign high = sub_flag ? (add_a[6:4]-add_b[6:4]-bit_ac) : (add_a[6:4]+add_b[6:4]+bit_ac);
assign {bit_c,bit_high} = sub_flag ? (add_a[7]-add_b[7]-high[3]) : (add_a[7]+add_b[7]+high[3]);
assign bit_ov = bit_c ^ high[3];
assign add_byte = {bit_high,high[2:0],low};
assign mult = acc * b;
assign {div_rem,div_ans} = divide(acc,b);
assign and_out = acc & data0;
assign or_out = acc | data0;
assign xor_out = acc ^ data0;
always @ ( posedge clk or posedge rst )
if ( rst )
acc <= #`DEL 8'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'he0 ) )
acc <= #`DEL wr_byte;
else;
else;
assign wr_acc = (wr_en_sfr & (wr_addr[7:0]==8'he0));
/*********************************************************/
/*********************************************************/
//psw register
assign psw_p = ^acc;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_ov <= #`DEL 1'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_ov <= #`DEL wr_byte[2];
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_ac <= #`DEL 1'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_ac <= #`DEL wr_byte[6];
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_c <= #`DEL 1'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_c <= #`DEL wr_byte[7];
else;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
psw_other <= #`DEL 4'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hd0 ) )
psw_other <= #`DEL {wr_byte[5:3],wr_byte[1]};
else;
else;
assign psw_rs = psw_other[2:1];
assign wr_psw_rs = wr_en_sfr & (wr_addr[7:0]==8'hd0);
assign psw = {psw_c,psw_ac,psw_other[3:1],psw_ov,psw_other[0],psw_p};
/*********************************************************/
/*********************************************************/
//dp sp registers
always @ ( posedge clk or posedge rst )
if ( rst )
dp <= #`DEL 16'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'h82 ) )
dp[7:0] <= #`DEL wr_byte;
else if ( wr_en_sfr & (wr_addr[7:0]==8'h83 ) )
dp[15:8] <= #`DEL wr_byte;
else;
else;
assign wr_dp = (wr_en_sfr & ((wr_addr[7:0]==8'h82)|(wr_addr[7:0]==8'h83)));
always @ ( posedge clk or posedge rst )
if ( rst )
sp <= #`DEL 8'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'h81) )
sp <= #`DEL wr_byte;
else;
else;
assign sp_sub1 = sp - 1'b1;
assign sp_add1 = sp + 1'b1;
assign wr_sp = (wr_en_sfr & (wr_addr[7:0]==8'h81));
always @ ( posedge clk or posedge rst )
if ( rst )
b <= #`DEL 8'b0;
else if ( work_en )
if ( wr_en_sfr & (wr_addr[7:0]==8'hf0) )
b <= #`DEL wr_byte;
else;
else;
/*********************************************************/
/*********************************************************/
//ram output
always @*
if ( same_flag )
data0 = same_byte;
else if ( same_byte[7] )
data0 = acc;
else if ( same_byte[6] )
data0 = psw;
else if ( same_byte[5] )
data0 = dp[15:8];
else if ( same_byte[4] )
data0 = dp[7:0];
else if ( same_byte[3] )
data0 = sp;
else if ( same_byte[2] )
data0 = b;
else
data0 = ram_rd_byte;
always @ ( posedge clk or posedge rst )
if ( rst )
data1 <= #`DEL 8'b0;
else if ( work_en )
data1 <= #`DEL data0;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
same_flag <= #`DEL 1'b0;
else if ( work_en )
`ifdef TYPE8052
if ( same_flag_data|same_flag_sfr|same_flag_idata|same_flag_xdata )
`else
if ( same_flag_data|same_flag_sfr|same_flag_xdata )
`endif
same_flag <= #`DEL 1'b1;
else
same_flag <= #`DEL 1'b0;
else;
always @ ( posedge clk or posedge rst )
if ( rst )
same_byte <= #`DEL 8'd0;
else if ( work_en )
`ifdef TYPE8052
if ( same_flag_data|same_flag_sfr|same_flag_idata|same_flag_xdata )
`else
if ( same_flag_data|same_flag_sfr|same_flag_xdata )
`endif
same_byte <= #`DEL wr_byte;
else if ( rd_en_sfr & (rd_addr[7:0]==8'he0) ) //acc
same_byte <= #`DEL 1'b1<<7;
else if ( rd_en_sfr & (rd_addr[7:0]==8'hd0) ) //psw
same_byte <= #`DEL 1'b1<<6;
else if ( rd_en_sfr & (rd_addr[7:0]==8'h83) ) //dph
same_byte <= #`DEL 1'b1<<5;
else if ( rd_en_sfr & (rd_addr[7:0]==8'h82) ) //dpl
same_byte <= #`DEL 1'b1<<4;
else if ( rd_en_sfr & (rd_addr[7:0]==8'h81) ) //sp
same_byte <= #`DEL 1'b1<<3;
else if ( rd_en_sfr & (rd_addr[7:0]==8'hf0) ) //b
same_byte <= #`DEL 1'b1<<2;
else
same_byte <= #`DEL 8'b0;
else;
/*********************************************************/
endmodule
|
module tb;
reg clk = 1'b0;
always #`HALF_PERIOD clk = ~clk;
reg rst = 1'b1;
initial #`PERIOD rst = 1'b0;
wire rom_en;
wire [15:0] rom_addr;
reg [7:0] rom_byte;
reg rom_vld;
wire ram_rd_en_data;
wire ram_rd_en_sfr;
wire ram_rd_en_xdata;
wire [15:0] ram_rd_addr;
reg [7:0] ram_rd_byte;
wire ram_wr_en_data;
wire ram_wr_en_sfr;
wire ram_wr_en_xdata;
wire [15:0] ram_wr_addr;
wire [7:0] ram_wr_byte;
r8051 u_cpu (
.clk ( clk ),
.rst ( rst ),
.cpu_en ( 1'b1 ),
.cpu_restart ( 1'b0 ),
.rom_en ( rom_en ),
.rom_addr ( rom_addr ),
.rom_byte ( rom_byte ),
.rom_vld ( rom_vld ),
.ram_rd_en_data ( ram_rd_en_data ),
.ram_rd_en_sfr ( ram_rd_en_sfr ),
.ram_rd_en_xdata ( ram_rd_en_xdata ),
.ram_rd_addr ( ram_rd_addr ),
.ram_rd_byte ( ram_rd_byte ),
.ram_rd_vld ( 1'b1 ),
.ram_wr_en_data ( ram_wr_en_data ),
.ram_wr_en_sfr ( ram_wr_en_sfr ),
.ram_wr_en_xdata ( ram_wr_en_xdata ),
.ram_wr_addr ( ram_wr_addr ),
.ram_wr_byte ( ram_wr_byte )
);
reg [7:0] rom[(1'b1<<16)-1:0];
integer fd,fx;
initial begin
fd = $fopen(`CODE_FILE,"rb");
fx = $fread(rom,fd);
$fclose(fd);
end
always @ ( posedge clk )
if ( rom_en )
rom_byte <= rom[rom_addr];
else;
always @ ( posedge clk )
rom_vld <= rom_en;
reg [7:0] data [127:0];
reg [7:0] data_rd_byte;
always @ ( posedge clk )
if ( ram_rd_en_data )
data_rd_byte <= data[ram_rd_addr[6:0]];
else;
always @ ( posedge clk )
if ( ram_wr_en_data )
data[ram_wr_addr[6:0]] <= ram_wr_byte;
else;
reg [7:0] xdata [127:0];
reg [7:0] xdata_rd_byte;
always @ ( posedge clk )
if ( ram_rd_en_xdata )
xdata_rd_byte <= xdata[ram_rd_addr[6:0]];
else;
always @ ( posedge clk )
if ( ram_wr_en_xdata )
if (( ram_wr_addr[6:0]==8'h7f ) & ram_wr_byte[0] ) begin
repeat(1000) @ (posedge clk);
$display("Test over, simulation is OK!");
$stop(1);
end
else
xdata[ram_wr_addr[6:0]] <= ram_wr_byte;
else;
reg [7:0] sfr_rd_byte;
always @ ( posedge clk )
if ( ram_wr_en_sfr & ( ram_wr_addr[7:0]==8'h99 ) )
$write("%s",ram_wr_byte);
else;
always @ ( posedge clk )
if ( ram_rd_en_sfr )
if ( ram_rd_addr[7:0]==8'h98 )
sfr_rd_byte <= 8'h3;
else if ( ram_rd_addr[7:0]==8'h99 )
sfr_rd_byte <= 0;
else
begin
$display($time," ns : --- SFR READ: %2h---",ram_rd_addr[7:0]);
//$stop;
end
else;
always @ ( posedge clk )
if ( ram_wr_en_sfr )
if(( ram_wr_addr[7:0]==8'h98 )|( ram_wr_addr[7:0]==8'h99 ))
#0;
else
begin
$display($time," ns : --- SFR WRITE: %2h -> %2h---",ram_wr_addr[7:0],ram_wr_byte);
//$stop;
end
else;
reg [1:0] read_flag;
always @ ( posedge clk )
if ( ram_rd_en_sfr )
read_flag <= 2'b10;
else if ( ram_rd_en_xdata )
read_flag <= 2'b01;
else if ( ram_rd_en_data )
read_flag <= 2'b0;
else;
always @*
if ( read_flag[1] )
ram_rd_byte = sfr_rd_byte;
else if ( read_flag[0] )
ram_rd_byte = xdata_rd_byte;
else
ram_rd_byte = data_rd_byte;
endmodule
|
module verified_adder_8bit(
input [7:0] a, b,
input cin,
output [7:0] sum,
output cout);
wire [8:0] c;
full_adder FA0 (.a(a[0]), .b(b[0]), .cin(cin), .sum(sum[0]), .cout(c[0]));
full_adder FA1 (.a(a[1]), .b(b[1]), .cin(c[0]), .sum(sum[1]), .cout(c[1]));
full_adder FA2 (.a(a[2]), .b(b[2]), .cin(c[1]), .sum(sum[2]), .cout(c[2]));
full_adder FA3 (.a(a[3]), .b(b[3]), .cin(c[2]), .sum(sum[3]), .cout(c[3]));
full_adder FA4 (.a(a[4]), .b(b[4]), .cin(c[3]), .sum(sum[4]), .cout(c[4]));
full_adder FA5 (.a(a[5]), .b(b[5]), .cin(c[4]), .sum(sum[5]), .cout(c[5]));
full_adder FA6 (.a(a[6]), .b(b[6]), .cin(c[5]), .sum(sum[6]), .cout(c[6]));
full_adder FA7 (.a(a[7]), .b(b[7]), .cin(c[6]), .sum(sum[7]), .cout(c[7]));
assign cout = c[7];
endmodule
|
module testbench;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] sum;
wire cout;
integer i; // Declare the loop variable here
integer fail_count;
integer error = 0;
// Instantiate the module
adder_8bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
// Randomize inputs and check output
initial begin
for (i = 0; i < 100; i = i + 1) begin
a = $random & 8'hff;
b = $random & 8'hff;
cin = $random & 1'b1;
#10;
error = (sum !== a + b + cin) ? error+1 : error;
end
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Test completed with %d /100 failures===========", error);
end
end
endmodule
|
module verified_edge_detect(
input clk,
input rst_n,
input a,
output reg rise,
output reg down
);
reg a0;
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
rise <= 1'b0;
down <= 1'b0;
end
else begin
if(a & ~a0) begin
rise <= 1;
down <= 0;
end
else if (~a & a0) begin
rise <= 0;
down <= 1;
end else begin
rise <= 0;
down <= 0;
end
end
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
a0 <= 0;
else
a0 <= a;
end
endmodule
|
module testbench;
reg clk;
reg rst_n;
reg a;
wire rise;
wire down;
edge_detect dut (
.clk(clk),
.rst_n(rst_n),
.a(a),
.rise(rise),
.down(down)
);
integer error=0;
initial begin
// Initialize inputs
clk = 0;
rst_n = 1;
a = 0;
// Wait for a few clock cycles to ensure the module stabilizes
#5;
// Test scenario 1: No edge
a = 0;
#10;
a = 0;
#10;
// $display("rise: %b, down: %b", rise, down);
error = (rise != 0 && down != 0) ? error+1 : error;
// Test scenario 2: Rising edge
a = 0;
#10;
a = 1;
#10;
a = 1;
// $display("rise: %b, down: %b", rise, down);
error = (rise != 1 && down != 0) ? error+1 : error;
// Test scenario 3: Falling edge
a = 1;
#10;
a = 0;
#10;
a = 0;
// $display("rise: %b, down: %b", rise, down);
error = (rise != 0 && down != 1) ? error+1 : error;
// Test scenario 4: Reset
rst_n = 0;
#10;
rst_n = 1;
#10;
// $display("rise: %b, down: %b", rise, down);
error = (rise != 0 && down != 0) ? error+1 : error;
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Error===========", error);
end
// Finish simulation
$finish;
end
always #5 clk = ~clk;
endmodule
|
module testbench;
// Inputs
reg clk_a;
reg clk_b;
reg arstn;
reg brstn;
reg [3:0] data_in;
reg data_en;
// Outputs
wire [3:0] dataout;
// Instantiate the mux module
synchronizer dut(
.clk_a(clk_a),
.clk_b(clk_b),
.arstn(arstn),
.brstn(brstn),
.data_in(data_in),
.data_en(data_en),
.dataout(dataout)
);
// Clock generation
always #5 clk_a = ~clk_a;
always #10 clk_b = ~clk_b;
integer error=0;
initial begin
clk_a = 0;
clk_b = 0;
arstn = 0;
brstn = 0;
data_en = 0;
data_in = 0;
#20 arstn = 1; // Release reset
#5 brstn = 1;
#50 data_in = 4; // Set data_in to 4
#10 data_en = 1; // Enable data
// $display(dataout);
#100;
error = (dataout == 4)? error : error+1;
#10 data_en = 0; // Disable data
#100;
#50 data_in = 7; // Set data_in to 7
#10 data_en = 1; // Enable data
// $display(dataout);
#80;
error = (dataout == 7)? error : error+1;
#10 data_en = 0; // Disable data
#100;
#50;
#20 arstn = 0; // Assert reset
#100;
#20 arstn = 1; // Release reset
#50 data_in = 9; // Set data_in to 9
#10 data_en = 1; // Enable data
// $display(dataout);
#100;
error = (dataout == 9)? error : error+1;
#10 data_en = 0; // Disable data
#100;
// Display results
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Test completed with %d /3 failures===========", error);
end
$finish;
end
endmodule
|
module verified_synchronizer(
input clk_a ,
input clk_b ,
input arstn ,
input brstn ,
input [3:0] data_in ,
input data_en ,
output reg [3:0] dataout
);
reg [3:0] data_reg;
always@(posedge clk_a or negedge arstn)
begin
if(!arstn) data_reg <= 0;
else data_reg <= data_in;
end
reg en_data_reg;
always@(posedge clk_a or negedge arstn)
begin
if(!brstn) en_data_reg <= 0;
else en_data_reg <= data_en;
end
reg en_clap_one; //1
reg en_clap_two; //2
always@(posedge clk_b or negedge brstn)
begin
if(!brstn) en_clap_one <= 0;
else en_clap_one <= en_data_reg;
end
always@(posedge clk_b or negedge brstn)
begin
if(!brstn) en_clap_two <= 0;
else en_clap_two <= en_clap_one;
end
always@(posedge clk_b or negedge brstn)
begin
if(!brstn) dataout <= 0;
else dataout <= (en_clap_two) ? data_reg : dataout;
end
endmodule
|
module verified_adder_16bit (
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
wire Co_temp;
add8 add8_inst1 (
.a(a[15:8]),
.b(b[15:8]),
.Cin(Co_temp),
.y(y[15:8]),
.Co(Co)
);
add8 add8_inst2 (
.a(a[7:0]),
.b(b[7:0]),
.Cin(Cin),
.y(y[7:0]),
.Co(Co_temp)
);
endmodule
|
module add8 (
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
wire Co_temp;
add4 add4_inst1 (
.a(a[7:4]),
.b(b[7:4]),
.Cin(Co_temp),
.y(y[7:4]),
.Co(Co)
);
add4 add4_inst2 (
.a(a[3:0]),
.b(b[3:0]),
.Cin(Cin),
.y(y[3:0]),
.Co(Co_temp)
);
endmodule
|
module add4 (
input wire [3:0] a,
input wire [3:0] b,
input wire Cin,
output wire [3:0] y,
output wire Co
);
wire Co_temp;
add2 add2_inst1 (
.a(a[3:2]),
.b(b[3:2]),
.Cin(Co_temp),
.y(y[3:2]),
.Co(Co)
);
add2 add2_inst2 (
.a(a[1:0]),
.b(b[1:0]),
.Cin(Cin),
.y(y[1:0]),
.Co(Co_temp)
);
endmodule
|
module add2 (
input wire [1:0] a,
input wire [1:0] b,
input wire Cin,
output wire [1:0] y,
output wire Co
);
wire Co_temp;
add1 add1_inst1 (
.a(a[1]),
.b(b[1]),
.Cin(Co_temp),
.y(y[1]),
.Co(Co)
);
add1 add1_inst2 (
.a(a[0]),
.b(b[0]),
.Cin(Cin),
.y(y[0]),
.Co(Co_temp)
);
endmodule
|
module add1 (
input wire a,
input wire b,
input wire Cin,
output wire y,
output wire Co
);
assign y = ((~a) & (~b) & Cin | (~a) & b & (~Cin) | a & (~b) & (~Cin) | (a & b & Cin));
assign Co = ((~a & b & Cin) | (a & ~b & Cin) | (a & b & ~Cin) | (a & b & Cin));
endmodule
|
module add16_tb();
reg [15:0] a;
reg [15:0] b;
reg Cin;
wire [15:0] y;
wire Co;
wire [16:0] tb_sum;
wire tb_co;
assign tb_sum = a + b;
assign tb_co = tb_sum[16];
integer i;
integer error = 0;
initial begin
for (i = 0; i < 100; i = i + 1) begin
a = {$random};
b = {$random};
Cin = 0;
#10;
error = (y !== tb_sum[15:0] || Co !== tb_co) ? error + 1 : error;
end
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Test completed with %d / 100 failures===========", error);
end
end
adder_16bit uut (
.a(a),
.b(b),
.Cin(Cin),
.y(y),
.Co(Co)
);
endmodule
|
module verified_radix2_div(
input wire clk,
input wire rst,
input wire [7:0] dividend,
input wire [7:0] divisor,
input wire sign,
input wire opn_valid,
output reg res_valid,
input wire res_ready,
output wire [15:0] result
);
reg [7:0] dividend_save, divisor_save;
reg [15:0] SR;
reg [8 :0] NEG_DIVISOR;
wire [7:0] REMAINER, QUOTIENT;
assign REMAINER = SR[15:8];
assign QUOTIENT = SR[7: 0];
wire [7:0] divident_abs;
wire [8:0] divisor_abs;
wire [7:0] remainer, quotient;
assign divident_abs = (sign & dividend[7]) ? ~dividend + 1'b1 : dividend;
assign remainer = (sign & dividend_save[7]) ? ~REMAINER + 1'b1 : REMAINER;
assign quotient = sign & (dividend_save[7] ^ divisor_save[7]) ? ~QUOTIENT + 1'b1 : QUOTIENT;
assign result = {remainer,quotient};
wire CO;
wire [8:0] sub_result;
wire [8:0] mux_result;
assign {CO,sub_result} = {1'b0,REMAINER} + NEG_DIVISOR;
assign mux_result = CO ? sub_result : {1'b0,REMAINER};
reg [3:0] cnt;
reg start_cnt;
always @(posedge clk) begin
if(rst) begin
SR <= 0;
dividend_save <= 0;
divisor_save <= 0;
cnt <= 0;
start_cnt <= 1'b0;
end
else if(~start_cnt & opn_valid & ~res_valid) begin
cnt <= 1;
start_cnt <= 1'b1;
dividend_save <= dividend;
divisor_save <= divisor;
SR[15:0] <= {7'b0,divident_abs,1'b0};
NEG_DIVISOR <= (sign & divisor[7]) ? {1'b1,divisor} : ~{1'b0,divisor} + 1'b1;
end
else if(start_cnt) begin
if(cnt[3]) begin
cnt <= 0;
start_cnt <= 1'b0;
SR[15:8] <= mux_result[7:0];
SR[0] <= CO;
end
else begin
cnt <= cnt + 1;
SR[15:0] <= {mux_result[6:0],SR[7:1],CO,1'b0};
end
end
end
wire data_go;
assign data_go = res_valid & res_ready;
always @(posedge clk) begin
res_valid <= rst ? 1'b0 :
cnt[3] ? 1'b1 :
data_go ? 1'b0 : res_valid;
end
endmodule
|
module radix2_div_tb;
reg clk;
reg rst;
reg [7:0] dividend, divisor;
reg sign;
reg opn_valid;
reg res_ready;
wire res_valid;
wire [15:0] result;
// Instantiate the radix2_div module
radix2_div uut (
.clk(clk),
.rst(rst),
.dividend(dividend),
.divisor(divisor),
.sign(sign),
.opn_valid(opn_valid),
.res_valid(res_valid),
.res_ready(res_ready),
.result(result)
);
integer i;
integer error = 0;
reg [7:0] a_test [0:7];
reg [7:0] b_test [0:7];
reg [15:0] expected_result [0:7];
reg sign_test [0:7];
initial begin
// Initialize test vectors
a_test[0] = 8'd100; b_test[0] = 8'd10; sign_test[0] = 0; expected_result[0] = {8'd0, 8'd10};
a_test[1] = -8'd100; b_test[1] = 8'd10; sign_test[1] = 1; expected_result[1] = {8'd0, -8'd10};
a_test[2] = 8'd100; b_test[2] = -8'd10; sign_test[2] = 1; expected_result[2] = {8'd0, -8'd10};
a_test[3] = -8'd100; b_test[3] = -8'd10; sign_test[3] = 1; expected_result[3] = {8'd0, 8'd10};
a_test[4] = 8'd123; b_test[4] = 8'd123; sign_test[4] = 0; expected_result[4] = {8'd0, 8'd1};
a_test[5] = 8'd0; b_test[5] = 8'd123; sign_test[5] = 0; expected_result[5] = {8'd0, 8'd0};
a_test[6] = 8'd123; b_test[6] = 8'd251; sign_test[6] = 0; expected_result[6] = {8'd123, 8'd0};
a_test[7] = 8'd255; b_test[7] = 8'd7; sign_test[7] = 0; expected_result[7] = {8'd3, 8'd36};
// Generate clock signal
clk = 0;
forever #5 clk = ~clk;
end
initial begin
// Initialize
rst = 1;
opn_valid = 0;
res_ready = 1;
#20;
rst = 0;
for (i = 0; i < 8; i = i + 1) begin
// Apply test vectors
dividend = a_test[i];
divisor = b_test[i];
sign = sign_test[i];
opn_valid = 1;
#10;
opn_valid = 0;
// Wait for result
wait(res_valid);
#10;
// Check result
if (result !== expected_result[i]) begin
error = error + 1;
$display("Error: dividend=%d, divisor=%d, expected=%h, got=%h", a_test[i], b_test[i], expected_result[i], result);
end
res_ready = 1;
#10;
end
// Display final result
if (error == 0) begin
$display("===========Your Design Passed===========");
end else begin
$display("===========Failed===========", error);
end
$finish;
end
endmodule
|
module verified_traffic_light
(
input rst_n,
input clk,
input pass_request,
output wire[7:0]clock,
output reg red,
output reg yellow,
output reg green
);
parameter idle = 2'd0,
s1_red = 2'd1,
s2_yellow = 2'd2,
s3_green = 2'd3;
reg [7:0] cnt;
reg [1:0] state;
reg p_red,p_yellow,p_green;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
state <= idle;
p_red <= 1'b0;
p_green <= 1'b0;
p_yellow <= 1'b0;
end
else case(state)
idle:
begin
p_red <= 1'b0;
p_green <= 1'b0;
p_yellow <= 1'b0;
state <= s1_red;
end
s1_red:
begin
p_red <= 1'b1;
p_green <= 1'b0;
p_yellow <= 1'b0;
if (cnt == 3)
state <= s3_green;
else
state <= s1_red;
end
s2_yellow:
begin
p_red <= 1'b0;
p_green <= 1'b0;
p_yellow <= 1'b1;
if (cnt == 3)
state <= s1_red;
else
state <= s2_yellow;
end
s3_green:
begin
p_red <= 1'b0;
p_green <= 1'b1;
p_yellow <= 1'b0;
if (cnt == 3)
state <= s2_yellow;
else
state <= s3_green;
end
endcase
end
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt <= 7'd10;
else if (pass_request&&green&&(cnt>10))
cnt <= 7'd10;
else if (!green&&p_green)
cnt <= 7'd60;
else if (!yellow&&p_yellow)
cnt <= 7'd5;
else if (!red&&p_red)
cnt <= 7'd10;
else cnt <= cnt -1;
assign clock = cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
yellow <= 1'd0;
red <= 1'd0;
green <= 1'd0;
end
else
begin
yellow <= p_yellow;
red <= p_red;
green <= p_green;
end
endmodule
|
module tb_traffic_light;
reg clk;
reg rst_n;
reg pass_request;
wire [7:0] clock;
wire red;
wire yellow;
wire green;
integer i;
// Instantiate the module
traffic_light uut (
.clk(clk),
.rst_n(rst_n),
.pass_request(pass_request),
.clock(clock),
.red(red),
.yellow(yellow),
.green(green)
);
// Clock generation
always begin
#5 clk = ~clk;
end
integer error = 0;
integer clock_cnt;
// Test sequence
initial begin
clk = 0; // Initialize clock
rst_n = 1; // De-assert reset
pass_request = 0; // No pass request initially
// Perform reset
rst_n = 0;
#10;
rst_n = 1;
#30;
// test red
$display("At time %t, clock = %d, red = %b, yellow = %b, green = %b",
$time, clock, red, yellow, green);
error = (red==1)&&(yellow==0)&&(green==0) ?error :error+1;
#100;
// test green
$display("At time %t, clock = %d, red = %b, yellow = %b, green = %b",
$time, clock, red, yellow, green);
error = (red==0)&&(yellow==0)&&(green==1) ?error :error+1;
#600;
// test yellow
$display("At time %t, clock = %d, red = %b, yellow = %b, green = %b",
$time, clock, red, yellow, green);
error = (red==0)&&(yellow==1)&&(green==0) ?error :error+1;
#150;
$display("At time %t, clock = %d, red = %b, yellow = %b, green = %b",
$time, clock, red, yellow, green);
clock_cnt = clock;
// test pass_request
#30;
$display("At time %t, clock = %d, red = %b, yellow = %b, green = %b",
$time, clock, red, yellow, green);
error = (clock!=(clock_cnt+3)) ?error :error+1;
pass_request = 1;
#10;
$display("At time %t, clock = %d, red = %b, yellow = %b, green = %b",
$time, clock, red, yellow, green);
error = (clock==10)&&(green==1) ?error :error+1;
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Failed===========", error);
end
$finish; // End of test
end
endmodule
|
module verified_alu(
input [31:0] a,
input [31:0] b,
input [5:0] aluc,
output [31:0] r,
output zero,
output carry,
output negative,
output overflow,
output flag
);
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter JR = 6'b001000;
parameter LUI = 6'b001111;
wire signed [31:0] a_signed;
wire signed [31:0] b_signed;
reg [32:0] res;
assign a_signed = a;
assign b_signed = b;
assign r = res[31:0];
assign flag = (aluc == SLT || aluc == SLTU) ? ((aluc == SLT) ? (a_signed < b_signed) : (a < b)) : 1'bz;
assign zero = (res == 32'b0) ? 1'b1 : 1'b0;
always @ (a or b or aluc)
begin
case(aluc)
ADD: begin
res <= a_signed + b_signed;
end
ADDU: begin
res <= a + b;
end
SUB: begin
res <= a_signed - b_signed;
end
SUBU: begin
res <= a - b;
end
AND: begin
res <= a & b;
end
OR: begin
res <= a | b;
end
XOR: begin
res <= a ^ b;
end
NOR: begin
res <= ~(a | b);
end
SLT: begin
res <= a_signed < b_signed ? 1 : 0;
end
SLTU: begin
res <= a < b ? 1 : 0;
end
SLL: begin
res <= b << a;
end
SRL: begin
res <= b >> a;
end
SRA: begin
res <= b_signed >>> a_signed;
end
SLLV: begin
res <= b << a[4:0];
end
SRLV: begin
res <= b >> a[4:0];
end
SRAV: begin
res <= b_signed >>> a_signed[4:0];
end
LUI: begin
res <= {a[15:0], 16'h0000};
end
default:
begin
res <= 32'bz;
end
endcase
end
endmodule
|
module test_alu();
reg [31:0] a;
reg [31:0] b;
reg [5:0] aluc;
wire [31:0] r;
wire zero;
wire carry;
wire negative;
wire overflow;
wire flag;
reg[4:0]cnt;
alu uut(a,b,aluc,r,zero,carry,negative,overflow,flag);
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter JR = 6'b001000;
parameter LUI = 6'b001111;
reg[5:0]opcodes[0:31];
reg[31:0]reference[0:31];
reg error=0;
integer file_open;
initial begin
$readmemh("reference.dat",reference);
opcodes[0]=ADD;
opcodes[1]=ADDU;
opcodes[2]=SUB;
opcodes[3]=SUBU;
opcodes[4]=AND;
opcodes[5]=OR;
opcodes[6]=XOR;
opcodes[7]=NOR;
opcodes[8]=SLT;
opcodes[9]=SLTU;
opcodes[10]=SLL;
opcodes[11]=SRL;
opcodes[12]=SRA;
opcodes[13]=SLLV;
opcodes[14]=SRLV;
opcodes[15]=SRAV;
//opcodes[16]=JR;
opcodes[16]=LUI;
a=32'h0000001c;
b=32'h00000021;
#5;
cnt = 0;
for(cnt=0;cnt<17;cnt=cnt+1)
begin
#5;
aluc=opcodes[cnt];
#5;
error=error|(reference[cnt]!=r);
end
if(error==0)
begin
$display("===========Your Design Passed===========");
end
else
begin
$display("===========Error===========");
end
$finish;
end
endmodule
|
module verified_adder_32bit(A,B,S,C32);
input [32:1] A;
input [32:1] B;
output [32:1] S;
output C32;
wire px1,gx1,px2,gx2;
wire c16;
CLA_16 CLA1(
.A(A[16:1]),
.B(B[16:1]),
.c0(0),
.S(S[16:1]),
.px(px1),
.gx(gx1)
);
CLA_16 CLA2(
.A(A[32:17]),
.B(B[32:17]),
.c0(c16),
.S(S[32:17]),
.px(px2),
.gx(gx2)
);
assign c16 = gx1 ^ (px1 && 0), //c0 = 0
C32 = gx2 ^ (px2 && c16);
endmodule
|
module CLA_16(A,B,c0,S,px,gx);
input [16:1] A;
input [16:1] B;
input c0;
output gx,px;
output [16:1] S;
wire c4,c8,c12;
wire Pm1,Gm1,Pm2,Gm2,Pm3,Gm3,Pm4,Gm4;
adder_4 adder1(
.x(A[4:1]),
.y(B[4:1]),
.c0(c0),
.c4(),
.F(S[4:1]),
.Gm(Gm1),
.Pm(Pm1)
);
adder_4 adder2(
.x(A[8:5]),
.y(B[8:5]),
.c0(c4),
.c4(),
.F(S[8:5]),
.Gm(Gm2),
.Pm(Pm2)
);
adder_4 adder3(
.x(A[12:9]),
.y(B[12:9]),
.c0(c8),
.c4(),
.F(S[12:9]),
.Gm(Gm3),
.Pm(Pm3)
);
adder_4 adder4(
.x(A[16:13]),
.y(B[16:13]),
.c0(c12),
.c4(),
.F(S[16:13]),
.Gm(Gm4),
.Pm(Pm4)
);
assign c4 = Gm1 ^ (Pm1 & c0),
c8 = Gm2 ^ (Pm2 & Gm1) ^ (Pm2 & Pm1 & c0),
c12 = Gm3 ^ (Pm3 & Gm2) ^ (Pm3 & Pm2 & Gm1) ^ (Pm3 & Pm2 & Pm1 & c0);
assign px = Pm1 & Pm2 & Pm3 & Pm4,
gx = Gm4 ^ (Pm4 & Gm3) ^ (Pm4 & Pm3 & Gm2) ^ (Pm4 & Pm3 & Pm2 & Gm1);
endmodule
|
module adder_4(x,y,c0,c4,F,Gm,Pm);
input [4:1] x;
input [4:1] y;
input c0;
output c4,Gm,Pm;
output [4:1] F;
wire p1,p2,p3,p4,g1,g2,g3,g4;
wire c1,c2,c3;
adder adder1(
.X(x[1]),
.Y(y[1]),
.Cin(c0),
.F(F[1]),
.Cout()
);
adder adder2(
.X(x[2]),
.Y(y[2]),
.Cin(c1),
.F(F[2]),
.Cout()
);
adder adder3(
.X(x[3]),
.Y(y[3]),
.Cin(c2),
.F(F[3]),
.Cout()
);
adder adder4(
.X(x[4]),
.Y(y[4]),
.Cin(c3),
.F(F[4]),
.Cout()
);
CLA CLA(
.c0(c0),
.c1(c1),
.c2(c2),
.c3(c3),
.c4(c4),
.p1(p1),
.p2(p2),
.p3(p3),
.p4(p4),
.g1(g1),
.g2(g2),
.g3(g3),
.g4(g4)
);
assign p1 = x[1] ^ y[1],
p2 = x[2] ^ y[2],
p3 = x[3] ^ y[3],
p4 = x[4] ^ y[4];
assign g1 = x[1] & y[1],
g2 = x[2] & y[2],
g3 = x[3] & y[3],
g4 = x[4] & y[4];
assign Pm = p1 & p2 & p3 & p4,
Gm = g4 ^ (p4 & g3) ^ (p4 & p3 & g2) ^ (p4 & p3 & p2 & g1);
endmodule
|
module CLA(c0,c1,c2,c3,c4,p1,p2,p3,p4,g1,g2,g3,g4);
input c0,g1,g2,g3,g4,p1,p2,p3,p4;
output c1,c2,c3,c4;
assign c1 = g1 ^ (p1 & c0),
c2 = g2 ^ (p2 & g1) ^ (p2 & p1 & c0),
c3 = g3 ^ (p3 & g2) ^ (p3 & p2 & g1) ^ (p3 & p2 & p1 & c0),
c4 = g4^(p4&g3)^(p4&p3&g2)^(p4&p3&p2&g1)^(p4&p3&p2&p1&c0);
endmodule
|
module adder(X,Y,Cin,F,Cout);
input X,Y,Cin;
output F,Cout;
assign F = X ^ Y ^ Cin;
assign Cout = (X ^ Y) & Cin | X & Y;
endmodule
|
module adder32_tb;
reg [31:0] A;
reg [31:0] B;
wire [31:0] S;
wire C32;
integer i;
integer error = 0;
reg [33:0] expected_sum;
// Instantiate the module
adder_32bit uut (
.A(A),
.B(B),
.S(S),
.C32(C32)
);
// Randomize inputs and check output
initial begin
for (i = 0; i < 100; i = i + 1) begin
A = $random;
B = $random;
#10;
// Calculate expected sum and carry out
expected_sum = A + B;
error = (S !== expected_sum[31:0] || C32 !== expected_sum[32]) ? error+1 : error;
end
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Test completed with %d /100 failures===========", error);
end
end
endmodule
|
module tb_multi_16bit;
reg clk;
reg rst_n;
reg start;
reg [15:0] ain;
reg [15:0] bin;
wire [31:0] yout;
wire done;
integer i; // Declare the loop variable here
integer fail_count = 0; // Declare a variable to count the failures
integer timeout; // Declare a timeout counter here
reg [31:0] expected_product; // Declare a variable to store the expected product
// Instantiate the module
multi_16bit uut (
.clk(clk),
.rst_n(rst_n),
.start(start),
.ain(ain),
.bin(bin),
.yout(yout),
.done(done)
);
// Clock generation
always begin
#5 clk = ~clk;
end
// Randomize inputs and check output
initial begin
clk = 0; // Initialize clock
rst_n = 1; // De-assert reset
start = 0; // Initialize start
// Perform reset
rst_n = 0;
for (i = 0; i < 100; i = i + 1) begin
#100;
rst_n = 1;
#50;
ain = $random;
bin = $random;
#50;
start = 1; // Start the operation
while(done !== 1) begin
#10;
end
expected_product = ain * bin;
if (done == 1) begin
fail_count = (yout == expected_product)? fail_count:fail_count+1;
end
start = 0; // Stop the operation
rst_n = 0;
#100;
end
if (fail_count == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Test completed with %d / 100 failures===========", fail_count);
end
$finish;
end
initial begin
#50000;
$finish;
end
endmodule
|
module verified_multi_16bit(
input clk, // Chip clock signal.
input rst_n, // Active-low reset signal. Defined as 0 for chip reset; defined as 1 for reset signal inactive.
input start, // Chip enable signal.
input [15:0] ain, // Input a (multiplicand) with a data width of 16 bits.
input [15:0] bin, // Input b (multiplier) with a data width of 16 bits.
output [31:0] yout, // Product output with a data width of 32 bits.
output done // Chip output flag signal. Defined as 1 indicates multiplication operation completion.
);
reg [15:0] areg; // Multiplicand a register.
reg [15:0] breg; // Multiplier b register.
reg [31:0] yout_r; // Product register.
reg done_r;
reg [4:0] i; // Shift count register.
//------------------------------------------------
// Data bit control
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (start && i < 5'd17) i <= i + 1'b1;
else if (!start) i <= 5'd0;
//------------------------------------------------
// Multiplication completion flag generation
always @(posedge clk or negedge rst_n)
if (!rst_n) done_r <= 1'b0;
else if (i == 5'd16) done_r <= 1'b1; // Multiplication completion flag
else if (i == 5'd17) done_r <= 1'b0; // Flag reset
assign done = done_r;
//------------------------------------------------
// Dedicated register for shift and accumulate operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
areg <= 16'h0000;
breg <= 16'h0000;
yout_r <= 32'h00000000;
end
else if (start) begin // Start operation
if (i == 5'd0) begin // Store multiplicand and multiplier
areg <= ain;
breg <= bin;
end
else if (i > 5'd0 && i < 5'd17) begin
if (areg[i-1])
yout_r <= yout_r + ({16'h0000, breg} << (i-1)); // Accumulate and shift
end
end
end
assign yout = yout_r;
endmodule
|
module verified_parallel2serial(
input wire clk ,
input wire rst_n ,
input wire [3:0]d ,
output wire valid_out ,
output wire dout
);
reg [3:0] data = 'd0;
reg [1:0]cnt;
reg valid;
assign dout = data[3];
assign valid_out =valid;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
data<= 'd0;
cnt <= 'd0;
valid <= 'd0;
end
else begin
if (cnt == 'd3) begin
data <= d;
cnt <= 'd0;
valid <= 1;
end
else begin
cnt <= cnt + 'd1;
valid <= 0;
data <= {data[2:0],data[3]};
end
end
end
endmodule
|
module parallel2serial_tb;
reg clk;
reg rst_n;
reg [3:0] d;
wire valid_out;
wire dout;
// Instantiate the DUT (Design Under Test)
parallel2serial dut (
.clk(clk),
.rst_n(rst_n),
.d(d),
.valid_out(valid_out),
.dout(dout)
);
// Generate clock
always #5 clk = ~clk;
integer error = 0;
integer failcase = 0;
integer i = 0;
initial begin
for (i=0; i<100; i=i+1) begin
error = 0;
// Initialize inputs
clk = 0;
rst_n = 0;
d = 4'b0;
#10;
rst_n = 1;
#10;
d = $random;
while (valid_out == 0) begin
@(posedge clk); // Wait for one clock cycle
end
// $display("dout = %b, valid_out = %b", dout, valid_out);
error = (dout == d[3] && valid_out==1) ? error : error+1;
#10;
// $display("dout = %b, valid_out = %b", dout, valid_out);
error = (dout == d[2] && valid_out==0) ? error : error+1;
#10;
// $display("dout = %b, valid_out = %b", dout, valid_out);
error = (dout == d[1] && valid_out==0) ? error : error+1;
#10;
// $display("dout = %b, valid_out = %b", dout, valid_out);
error = (dout == d[0] && valid_out==0) ? error : error+1;
#10;
// $display("dout = %b, valid_out = %b", dout, valid_out);
error = (valid_out==1) ? error : error+1;
#10;
failcase = (error==0)? failcase :failcase+1;
end
if(failcase==0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Test completed with %d /100 failures===========", failcase);
end
$finish;
end
endmodule
|
module verified_adder_64bit
#(
parameter DATA_WIDTH = 64,
parameter STG_WIDTH = 16
)
(
input clk,
input rst_n,
input i_en,
input [DATA_WIDTH-1:0] adda,
input [DATA_WIDTH-1:0] addb,
output [DATA_WIDTH:0] result,
output reg o_en
);
reg stage1;
reg stage2;
reg stage3;
wire [STG_WIDTH-1:0] a1;
wire [STG_WIDTH-1:0] b1;
wire [STG_WIDTH-1:0] a2;
wire [STG_WIDTH-1:0] b2;
wire [STG_WIDTH-1:0] a3;
wire [STG_WIDTH-1:0] b3;
wire [STG_WIDTH-1:0] a4;
wire [STG_WIDTH-1:0] b4;
reg [STG_WIDTH-1:0] a2_ff1;
reg [STG_WIDTH-1:0] b2_ff1;
reg [STG_WIDTH-1:0] a3_ff1;
reg [STG_WIDTH-1:0] b3_ff1;
reg [STG_WIDTH-1:0] a3_ff2;
reg [STG_WIDTH-1:0] b3_ff2;
reg [STG_WIDTH-1:0] a4_ff1;
reg [STG_WIDTH-1:0] b4_ff1;
reg [STG_WIDTH-1:0] a4_ff2;
reg [STG_WIDTH-1:0] b4_ff2;
reg [STG_WIDTH-1:0] a4_ff3;
reg [STG_WIDTH-1:0] b4_ff3;
reg c1;
reg c2;
reg c3;
reg c4;
reg [STG_WIDTH-1:0] s1;
reg [STG_WIDTH-1:0] s2;
reg [STG_WIDTH-1:0] s3;
reg [STG_WIDTH-1:0] s4;
reg [STG_WIDTH-1:0] s1_ff1;
reg [STG_WIDTH-1:0] s1_ff2;
reg [STG_WIDTH-1:0] s1_ff3;
reg [STG_WIDTH-1:0] s2_ff1;
reg [STG_WIDTH-1:0] s2_ff2;
reg [STG_WIDTH-1:0] s3_ff1;
assign a1 = adda[STG_WIDTH-1:0];
assign b1 = addb[STG_WIDTH-1:0];
assign a2 = adda[STG_WIDTH*2-1:16];
assign b2 = addb[STG_WIDTH*2-1:16];
assign a3 = adda[STG_WIDTH*3-1:32];
assign b3 = addb[STG_WIDTH*3-1:32];
assign a4 = adda[STG_WIDTH*4-1:48];
assign b4 = addb[STG_WIDTH*4-1:48];
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
stage1 <= 1'b0;
stage2 <= 1'b0;
stage3 <= 1'b0;
o_en <= 1'b0;
end
else begin
stage1 <= i_en;
stage2 <= stage1;
stage3 <= stage2;
o_en <= stage3;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
a2_ff1 <= 'd0;
b2_ff1 <= 'd0;
a3_ff1 <= 'd0;
b3_ff1 <= 'd0;
a3_ff2 <= 'd0;
b3_ff2 <= 'd0;
a4_ff1 <= 'd0;
b4_ff1 <= 'd0;
a4_ff2 <= 'd0;
b4_ff2 <= 'd0;
a4_ff3 <= 'd0;
b4_ff3 <= 'd0;
end
else begin
a2_ff1 <= a2;
b2_ff1 <= b2;
a3_ff1 <= a3;
b3_ff1 <= b3;
a3_ff2 <= a3_ff1;
b3_ff2 <= b3_ff1;
a4_ff1 <= a4;
b4_ff1 <= b4;
a4_ff2 <= a4_ff1;
b4_ff2<= b4_ff1;
a4_ff3 <= a4_ff2;
b4_ff3 <= b4_ff2;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
s1_ff1 <= 'd0;
s1_ff2 <= 'd0;
s1_ff3 <= 'd0;
s2_ff1 <= 'd0;
s2_ff2 <= 'd0;
s3_ff1 <= 'd0;
end
else begin
s1_ff1 <= s1;
s1_ff2 <= s1_ff1;
s1_ff3 <= s1_ff2;
s2_ff1 <= s2;
s2_ff2 <= s2_ff1;
s3_ff1 <= s3;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
c1 <= 1'b0;
s1 <= 'd0;
end
else if (i_en) begin
{c1, s1} <= a1 + b1;
end
else begin
c1 <= c1;
s1 <= s1;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
c2 <= 1'b0;
s2 <= 'd0;
end
else if (stage1) begin
{c2, s2} <= a2_ff1 + b2_ff1 + c1;
end
else begin
c2 <= c2;
s2 <= s2;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
c3 <= 1'b0;
s3 <= 'd0;
end
else if (stage2) begin
{c3, s3} <= a3_ff2 + b3_ff2 + c2;
end
else begin
c3 <= c3;
s3 <= s3;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
c4 <= 1'b0;
s4 <= 'd0;
end
else if (stage3) begin
{c4, s4} <= a4_ff3 + b4_ff3 + c3;
end
else begin
c4 <= c4;
s4 <= s4;
end
end
assign result = {c4, s4, s3_ff1, s2_ff2, s1_ff3};
endmodule
|
module tb_adder64();
parameter DATA_WIDTH = 64;
parameter STG_WIDTH = 16;
reg CLK;
reg RST;
reg i_en;
wire o_en;
reg [DATA_WIDTH-1:0] PLUS_A;
reg [DATA_WIDTH-1:0] PLUS_B;
wire [DATA_WIDTH:0] SUM_OUT;
wire [DATA_WIDTH:0] sum_out_golden;
reg [DATA_WIDTH:0] sum_out_golden_ff1;
reg [DATA_WIDTH:0] sum_out_golden_ff2;
reg [DATA_WIDTH:0] sum_out_golden_ff3;
reg [DATA_WIDTH:0] sum_out_golden_ff4;
assign {sum_out_golden} = PLUS_A + PLUS_B;
always #2 CLK = ~CLK;
integer error = 0;
initial begin
CLK = 0;
repeat (100) begin
RST = 0;
i_en = 0;
#8 RST = 1;
i_en = 1'b1;
PLUS_A = $random * $random;
PLUS_B = $random * $random;
while(o_en==0) begin
@(negedge CLK);
end
error = ((PLUS_A + PLUS_B) == SUM_OUT && o_en ==1 ) ? error : error + 1;
@(negedge CLK);
end
if (error == 0) begin
$display("=========== Your Design Passed ===========");
end
else begin
$display("=========== Test completed with %d / 100 failures ===========", error);
end
$finish;
end
always @(posedge CLK, negedge RST) begin
if (!RST) begin
sum_out_golden_ff1 <= 'd0;
sum_out_golden_ff2 <= 'd0;
sum_out_golden_ff3 <= 'd0;
sum_out_golden_ff4 <= 'd0;
end
else begin
sum_out_golden_ff1 <= sum_out_golden;
sum_out_golden_ff2 <= sum_out_golden_ff1;
sum_out_golden_ff3 <= sum_out_golden_ff2;
sum_out_golden_ff4 <= sum_out_golden_ff3;
end
end
adder_pipe_64bit #(
.DATA_WIDTH(DATA_WIDTH),
.STG_WIDTH(STG_WIDTH)
)
u_pip_add64 (
.clk (CLK),
.rst_n (RST),
.i_en (i_en),
.adda (PLUS_A),
.addb (PLUS_B),
.result (SUM_OUT),
.o_en (o_en)
);
endmodule
|
module verified_RAM (
input clk,
input rst_n,
input write_en,
input [7:0]write_addr,
input [5:0]write_data,
input read_en,
input [7:0]read_addr,
output reg [5:0]read_data
);
//defination
reg [7 : 0] RAM [11:0];
//output
integer i;
always@(posedge clk or negedge rst_n)begin
if(!rst_n) begin
for(i = 0; i < 8; i = i + 1) begin
RAM[i] <= 'd0;
end
end
else if(write_en)
RAM[write_addr] <= write_data;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
read_data <= 'd0;
else if(read_en)
read_data <= RAM[read_addr];
else
read_data <= 'd0;
end
endmodule
|
module tb_RAM;
// Parameters
parameter CLK_PERIOD = 10; // Clock period in simulation time units
// Inputs
reg clk;
reg rst_n;
reg write_en;
reg [7:0] write_addr;
reg [5:0] write_data;
reg read_en;
reg [7:0] read_addr;
// Outputs
wire [5:0] read_data;
// Instantiate the module
RAM uut (
.clk(clk),
.rst_n(rst_n),
.write_en(write_en),
.write_addr(write_addr),
.write_data(write_data),
.read_en(read_en),
.read_addr(read_addr),
.read_data(read_data)
);
// Clock generation
always #((CLK_PERIOD)/2) clk = ~clk;
integer error = 0;
// Initial block for stimulus generation
initial begin
// Initialize inputs
clk = 0;
rst_n = 1;
repeat(100) begin
write_en = 0;
write_addr = 0;
write_data = 0;
read_en = 0;
read_addr = 0;
// Wait for a few clock cycles
#((CLK_PERIOD) * 5);
// Release reset
rst_n = 0;
#((CLK_PERIOD) * 2);
rst_n = 1;
// Write operation
write_en = 1;
write_addr = 3'b000;
write_data = $random;
#((CLK_PERIOD) * 1);
write_en = 0;
#((CLK_PERIOD) * 1);
// Read operation
read_en = 1;
read_addr = 3'b000;
#((CLK_PERIOD) * 1);
// $display("read_data = %b", read_data);
error = (read_data == write_data) ? error : error+1;
read_en = 0;
#((CLK_PERIOD) * 1);
// $display("read_data = %b", read_data);
error = (read_data == 0) ? error : error+1;
end
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Error===========", error);
end
// Finish simulation
$finish;
end
endmodule
|
module tb_multi_pipe();
reg [7:0] mul_a;
reg [7:0] mul_b;
reg mul_en_in;
reg clk;
reg rst_n;
wire mul_en_out;
wire [15:0] mul_out;
reg [15:0] expected_product;
multi_pipe_8bit u1(
.clk(clk),
.rst_n(rst_n),
.mul_a(mul_a),
.mul_b(mul_b),
.mul_en_in(mul_en_in),
.mul_en_out(mul_en_out),
.mul_out(mul_out)
);
initial clk = 1;
always # 10 clk = ~clk;
integer error = 0;
initial begin
rst_n = 0;
mul_a = 0;
mul_b = 0;
mul_en_in = 0;
#(`clk_period*200+1);
rst_n = 1;
#(`clk_period*10);
mul_a = 'd35;
mul_b = 'd20;
mul_en_in = 'd1;
repeat (100) begin
mul_en_in = 0;
#(`clk_period*20);
rst_n = 1;
#(`clk_period*10);
mul_a = $random;
mul_b = $random;
mul_en_in = 'd1;
#(`clk_period);
expected_product = mul_a * mul_b;
#(`clk_period);
error = ((mul_en_out==1) && (mul_out == expected_product)) ? error+1 : error;
while (mul_en_out == 0) begin
@(posedge clk); // Wait for one clock cycle
end
// //========it can be changed depending on your pipelining processing latency
// #(`clk_period*4);
// //========it can be changed depending on your pipelining processing latency
error = (mul_out != expected_product) ? error+1 : error;
// $display("mul_a = %d, mul_b = %d, mul_out = %d, expected = %d", mul_a, mul_b, mul_out, expected_product);
end
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Test completed with %d /100 failures===========", error);
end
$finish;
end
endmodule
|
module verified_multi_pipe_8bit#(
parameter size = 8
)(
clk,
rst_n,
mul_a,
mul_b,
mul_en_in,
mul_en_out,
mul_out
);
input clk;
input rst_n;
input mul_en_in;
input [size-1:0] mul_a;
input [size-1:0] mul_b;
output reg mul_en_out;
output reg [size*2-1:0] mul_out;
reg [2:0] mul_en_out_reg;
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
mul_en_out_reg <= 'd0;
mul_en_out <= 'd0;
end
else begin
mul_en_out_reg <= {mul_en_out_reg[1:0],mul_en_in};
mul_en_out <= mul_en_out_reg[2];
end
reg [7:0] mul_a_reg;
reg [7:0] mul_b_reg;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
mul_a_reg <= 'd0;
mul_a_reg <= 'd0;
end
else begin
mul_a_reg <= mul_en_in ? mul_a :'d0;
mul_b_reg <= mul_en_in ? mul_b :'d0;
end
wire [15:0] temp [size-1:0];
assign temp[0] = mul_b_reg[0]? {8'b0,mul_a_reg} : 'd0;
assign temp[1] = mul_b_reg[1]? {7'b0,mul_a_reg,1'b0} : 'd0;
assign temp[2] = mul_b_reg[2]? {6'b0,mul_a_reg,2'b0} : 'd0;
assign temp[3] = mul_b_reg[3]? {5'b0,mul_a_reg,3'b0} : 'd0;
assign temp[4] = mul_b_reg[4]? {4'b0,mul_a_reg,4'b0} : 'd0;
assign temp[5] = mul_b_reg[5]? {3'b0,mul_a_reg,5'b0} : 'd0;
assign temp[6] = mul_b_reg[6]? {2'b0,mul_a_reg,6'b0} : 'd0;
assign temp[7] = mul_b_reg[7]? {1'b0,mul_a_reg,7'b0} : 'd0;
reg [15:0] sum [3:0];//[size/2-1:1]
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
sum[0] <= 'd0;
sum[1] <= 'd0;
sum[2] <= 'd0;
sum[3] <= 'd0;
end
else begin
sum[0] <= temp[0] + temp[1];
sum[1] <= temp[2] + temp[3];
sum[2] <= temp[4] + temp[5];
sum[3] <= temp[6] + temp[7];
end
reg [15:0] mul_out_reg;
always @(posedge clk or negedge rst_n)
if(!rst_n)
mul_out_reg <= 'd0;
else
mul_out_reg <= sum[0] + sum[1] + sum[2] + sum[3];
always @(posedge clk or negedge rst_n)
if(!rst_n)
mul_out <= 'd0;
else if(mul_en_out_reg[2])
mul_out <= mul_out_reg;
else
mul_out <= 'd0;
endmodule
|
module tb();
reg clk,rst_n;
reg din_serial,din_valid;
wire dout_valid;
wire[7:0]dout_parallel;
always #5 clk = ~clk;
integer error = 0;
initial begin
clk <= 1'b0;
rst_n <= 1'b0;
#12
rst_n <= 1'b1;
din_valid <= 1'b1;
din_serial <= 1'b1; #10;
din_serial <= 1'b1; #10;
din_serial <= 1'b1; #10;
din_serial <= 1'b1; #10;
error = (dout_valid == 0) ?error:error+1;
din_serial <= 1'b0; #10;
din_serial <= 1'b0; #10;
din_serial <= 1'b0; #10;
din_serial <= 1'b0; #10;
while(dout_valid == 0) begin
#5;
end
// $display("%b",dout_parallel);
error = (dout_parallel == 8'b11110000) ?error:error+1;
din_valid <= 1'b0;
#30;
din_valid <= 1'b1;
din_serial <= 1'b1; #10
din_serial <= 1'b1; #10
din_serial <= 1'b0; #10
din_serial <= 1'b0; #10
error = (dout_valid == 0) ?error:error+1;
din_serial <= 1'b0; #10
din_serial <= 1'b0; #10
din_serial <= 1'b1; #10
din_serial <= 1'b1; #20
din_valid <= 1'b0;
while(dout_valid == 0) begin
#5;
end
// $display("%b",dout_parallel);
error = (dout_parallel == 8'b11000011) ?error:error+1;
#10
error = (dout_valid == 0) ?error:error+1;
#10
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Error===========");
end
$finish;
end
serial2parallel u0(
.clk (clk) ,
.rst_n (rst_n) ,
.din_serial (din_serial) ,
.dout_parallel (dout_parallel) ,
.din_valid (din_valid) ,
.dout_valid (dout_valid)
);
endmodule
|
module verified_serial2parallel(
input clk,
input rst_n,
input din_serial,
input din_valid,
output reg [7:0]dout_parallel,
output reg dout_valid
);
reg[7:0]din_tmp;
reg[3:0]cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt <= 0;
else if(din_valid)
cnt <= (cnt == 4'd8)?0:cnt+1'b1;
else
cnt <= 0;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
din_tmp <= 8'b0;
else if(din_valid && cnt <= 4'd7)
din_tmp <= {din_tmp[6:0],din_serial};
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
dout_valid <= 1'b0;
dout_parallel <= 8'b0;
end
else if(cnt == 4'd8)begin
dout_valid <= 1'b1;
dout_parallel <= din_tmp;
end
else begin
dout_valid <= 1'b0;
end
end
endmodule
|
module test54();
reg clk;
reg rst;
reg [31:0] a,b;
wire [31:0] c;
pe dut(clk,rst,a,b,c);
initial begin
a=0;
b=0;
clk=0;
rst=1;
#5;
clk=1;
#5;
clk=0;
rst=0;
#5;
a=1;
b=1;
#5;
clk=1;
#5;
clk=0;
a=2;
b=2;
#5;
clk=1;
#5;
clk=0;
a=3;
b=3;
#5;
clk=1;
#5;
clk=0;
//$display("%h", c);
if(c==32'h0000000e)
begin
$display("===========Your Design Passed===========");
end
else
begin
$display("===========Error===========");
end
end
endmodule
|
module verified_pe(
input clk,
input rst,
input [31:0] a,
input [31:0] b,
output [31:0] c
);
reg [31:0] c;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
c <= 0;
end
else
begin
c <= c + a*b;
end
end
endmodule
|
module freq_div (CLK_in,CLK_50,CLK_10,CLK_1,RST);
input CLK_in,RST;
output reg CLK_50,CLK_10,CLK_1;
reg [3:0] cnt_10;
reg [6:0] cnt_100;
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_50<= 1'b0;
end
else begin
CLK_50<= ~CLK_50;
end
end
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_10<= 1'b0;
cnt_10<=0;
end
else if (cnt_10==4) begin
CLK_10<= ~CLK_10;
cnt_10<=0;
end
else begin
cnt_10<=cnt_10+1;
end
end
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_1<= 1'b0;
cnt_100<=0;
end
else if (cnt_100==49) begin
CLK_1<= ~CLK_1;
cnt_100<=0;
end
else begin
cnt_100<=cnt_100+1;
end
end
endmodule
|
module test ();
reg clk,rst;
wire out1;
wire out2;
wire out3;
freq_div dut(.CLK_in(clk),.RST(rst),.CLK_50(out1),.CLK_10(out2),.CLK_1(out3));
initial begin
clk = 0;
forever #5 clk = ~clk;
end
integer error=0;
initial begin
#10;
rst = 1;
#35;
rst = 0;
// 45, clk: 1, clk50: 0, rclk10: 0, clk1: 0
error = (out1 != 0 || out2 != 0 || out3 !=0 ) ? error+1 : error;
// 55, clk: 1, clk50: 1, rclk10: 0, clk1: 0
#10;
error = (out1 != 1 || out2 != 0 || out3 !=0 ) ? error+1 : error;
// 95, clk50: 0, rclk10: 1, clk1: 0
#40;
error = (out1 != 1 || out2 != 1 || out3 !=0 ) ? error+1 : error;
// 225, clk: 1, clk50: 0, rclk10: 1, clk1: 0
#130;
error = (out1 != 0 || out2 != 1 || out3 !=0 ) ? error+1 : error;
// 625, clk: 1, clk50: 0, rclk10: 1, clk1: 1
#400;
error = (out1 != 0 || out2 != 1 || out3 !=1 ) ? error+1 : error;
// 1035, clk: 1, clk50: 1, rclk10: 1, clk1: 1
#410;
error = (out1 != 1 || out2 != 1 || out3 !=1 ) ? error+1 : error;
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Error===========", error);
end
$finish;
end
// initial begin
// repeat(500) begin
// #5
// $display("Time: %t, clk: %b, clk50: %b, rclk10: %b, clk1: %b", $time, clk, out1, out2, out3);
// end
// end
endmodule
|
module verified_width_8to16(
input clk ,
input rst_n ,
input valid_in ,
input [7:0] data_in ,
output reg valid_out,
output reg [15:0] data_out
);
reg [7:0] data_lock; //data buffer
reg flag ;
//input data buff in data_lock
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
data_lock <= 'd0;
else if(valid_in && !flag)
data_lock <= data_in;
end
//generate flag
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
flag <= 'd0;
else if(valid_in)
flag <= ~flag;
end
//generate valid_out
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
valid_out <= 'd0;
else if(valid_in && flag)
valid_out <= 1'd1;
else
valid_out <= 'd0;
end
//data stitching
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
data_out <= 'd0;
else if(valid_in && flag)
data_out <= {data_lock, data_in};
end
endmodule
|
module testbench();
reg rst,valid_in;
reg clk=1;
reg[7:0] data_in;
wire valid_out;
wire [15:0] data_out;
width_8to16 dut(
.clk (clk),
.rst_n(rst),
.valid_in(valid_in),
.data_in(data_in),
.valid_out(valid_out),
.data_out(data_out)
);
always #5 clk = ~clk;
integer error = 0;
initial
begin
rst=0;valid_in=0;
#10 rst=1;valid_in=1;data_in=8'b10100000;
// $display("data_out = %b", data_out);
// $display("valid_out = %b", valid_out);
error = valid_out ==0 ? error : error+1;
#10 data_in=8'b10100001;
// $display("data_out = %b", data_out);
#10 data_in=8'b10110000;
// $display("data_out = %b", data_out);
// $display("valid_out = %b", valid_out);
error = (data_out == 16'b1010000010100001 && valid_out ==1 )? error : error+1;
#10 valid_in=0;
#20 valid_in=1;data_in=8'b10110001;
#10 valid_in=0;
// $display("data_out = %b", data_out);
// $display("valid_out = %b", valid_out);
error = (data_out == 16'b1011000010110001 && valid_out ==1 )? error : error+1;
#30
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Test completed with %d / 3 failures===========", error);
end
$finish;
end
endmodule
|
module verified_calendar(CLK,RST,Hours,Mins,Secs);
input CLK,RST;
output [5:0] Hours,Mins,Secs;
reg [5:0] Hours,Mins,Secs;
always@(posedge CLK or posedge RST) begin
if (RST)
Secs <= 0;
else if (Secs == 59)
Secs <= 0;
else
Secs <= Secs + 1;
end
always@(posedge CLK or posedge RST) begin
if (RST)
Mins <= 0;
else if((Mins==59)&&(Secs==59))
Mins <= 0;
else if(Secs== 59)
Mins <= Mins + 1;
else
Mins <= Mins;
end
always@(posedge CLK or posedge RST) begin
if (RST)
Hours <= 0;
else if((Hours == 23)&&(Mins==59)&&(Secs==59))
Hours <= 0;
else if((Mins == 59)&&(Secs==59))
Hours <= Hours + 1;
else
Hours <= Hours;
end
endmodule
|
module main();
reg clk,rst;
wire[5:0] out1,out2,out3;
calendar dut(.CLK(clk),.RST(rst),.Hours(out1),.Mins(out2),.Secs(out3));
initial begin
clk=0;
forever #5 clk=~clk;
end
integer outfile;
reg [17:0] clocktime;
always @(posedge clk) begin
clocktime[17:12] <= out1;
clocktime[11:6] <= out2;
clocktime[5:0] <= out3;
end
reg [17:0] reference_data [0:4000];
integer i=0;
integer error = 0;
initial begin
#10;
rst = 1;
#25;
rst = 0;
// outfile = $fopen("reference.txt", "w");
$readmemh("reference.txt",reference_data);
repeat(4000) begin
// $fwrite(outfile, "%h\n", clocktime);
error = (reference_data[i] == clocktime) ? error :error +1;
i = i + 1;
#10;
end
if(error==0)
begin
$display("===========Your Design Passed===========");
end
else
begin
$display("===========Error===========");
end
// $fclose(outfile);
$finish;
end
endmodule
|
module dual_port_RAM #(parameter DEPTH = 16, parameter WIDTH = 8)
(
input wclk ,
input wenc ,
input [$clog2(DEPTH)-1:0] waddr ,
input [WIDTH-1:0] wdata ,
input rclk ,
input renc ,
input [$clog2(DEPTH)-1:0] raddr ,
output reg [WIDTH-1:0] rdata
);
reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];
always @(posedge wclk) begin
if(wenc)
RAM_MEM[waddr] <= wdata;
end
always @(posedge rclk) begin
if(renc)
rdata <= RAM_MEM[raddr];
end
endmodule
|
module verified_asyn_fifo#(
parameter WIDTH = 8,
parameter DEPTH = 16
)(
input wclk ,
input rclk ,
input wrstn ,
input rrstn ,
input winc ,
input rinc ,
input [WIDTH-1:0] wdata ,
output wire wfull ,
output wire rempty ,
output wire [WIDTH-1:0] rdata
);
parameter ADDR_WIDTH = $clog2(DEPTH);
reg [ADDR_WIDTH:0] waddr_bin;
reg [ADDR_WIDTH:0] raddr_bin;
always @(posedge wclk or negedge wrstn) begin
if(~wrstn) begin
waddr_bin <= 'd0;
end
else if(!wfull && winc)begin
waddr_bin <= waddr_bin + 1'd1;
end
end
always @(posedge rclk or negedge rrstn) begin
if(~rrstn) begin
raddr_bin <= 'd0;
end
else if(!rempty && rinc)begin
raddr_bin <= raddr_bin + 1'd1;
end
end
wire [ADDR_WIDTH:0] waddr_gray;
wire [ADDR_WIDTH:0] raddr_gray;
reg [ADDR_WIDTH:0] wptr;
reg [ADDR_WIDTH:0] rptr;
assign waddr_gray = waddr_bin ^ (waddr_bin>>1);
assign raddr_gray = raddr_bin ^ (raddr_bin>>1);
always @(posedge wclk or negedge wrstn) begin
if(~wrstn) begin
wptr <= 'd0;
end
else begin
wptr <= waddr_gray;
end
end
always @(posedge rclk or negedge rrstn) begin
if(~rrstn) begin
rptr <= 'd0;
end
else begin
rptr <= raddr_gray;
end
end
reg [ADDR_WIDTH:0] wptr_buff;
reg [ADDR_WIDTH:0] wptr_syn;
reg [ADDR_WIDTH:0] rptr_buff;
reg [ADDR_WIDTH:0] rptr_syn;
always @(posedge wclk or negedge wrstn) begin
if(~wrstn) begin
rptr_buff <= 'd0;
rptr_syn <= 'd0;
end
else begin
rptr_buff <= rptr;
rptr_syn <= rptr_buff;
end
end
always @(posedge rclk or negedge rrstn) begin
if(~rrstn) begin
wptr_buff <= 'd0;
wptr_syn <= 'd0;
end
else begin
wptr_buff <= wptr;
wptr_syn <= wptr_buff;
end
end
assign wfull = (wptr == {~rptr_syn[ADDR_WIDTH:ADDR_WIDTH-1],rptr_syn[ADDR_WIDTH-2:0]});
assign rempty = (rptr == wptr_syn);
/***********RAM*********/
wire wen ;
wire ren ;
wire wren;//high write
wire [ADDR_WIDTH-1:0] waddr;
wire [ADDR_WIDTH-1:0] raddr;
assign wen = winc & !wfull;
assign ren = rinc & !rempty;
assign waddr = waddr_bin[ADDR_WIDTH-1:0];
assign raddr = raddr_bin[ADDR_WIDTH-1:0];
dual_port_RAM #(.DEPTH(DEPTH),
.WIDTH(WIDTH)
)dual_port_RAM(
.wclk (wclk),
.wenc (wen),
.waddr(waddr[ADDR_WIDTH-1:0]), //The depth is logarithmic to 2 to get the bit width of the address
.wdata(wdata), //data_write
.rclk (rclk),
.renc (ren),
.raddr(raddr[ADDR_WIDTH-1:0]),
.rdata(rdata)
);
endmodule
|
module pulse_detect_tb;
reg clk;
reg rst_n;
reg data_in;
wire data_out;
// Instantiate the DUT (Design Under Test)
pulse_detect dut (
.clk(clk),
.rst_n(rst_n),
.data_in(data_in),
.data_out(data_out)
);
// Generate clock
initial begin
clk=0;
forever #5 clk=~clk;
end
integer error = 0;
initial begin
// Initialize inputs
#10;
rst_n = 0;
data_in = 0;
#28;
rst_n = 1;
#10 data_in = 0;
#10 data_in = 0;
#10 data_in = 0;
#10 data_in = 1;
#10 data_in = 0;
#10 data_in = 1;
#10 data_in = 0;
#10 data_in = 1;
#10 data_in = 1;
#10 data_in = 0;
#10;
// Finish simulation
$finish;
end
initial begin
#5;
#10;
error = (data_out == 0) ? error : error+1;
#10;
error = (data_out == 0) ? error : error+1;
#10;
error = (data_out == 0) ? error : error+1;
#10;
error = (data_out == 0) ? error : error+1;
#10;
error = (data_out == 0) ? error : error+1;
#10;
error = (data_out == 0) ? error : error+1;
#10;
error = (data_out == 0) ? error : error+1;
#10;
error = (data_out == 0) ? error : error+1;
#10;
error = (data_out == 1) ? error : error+1;
// $display("%b,%b,%b", data_in, data_out, dut.pulse_level1);//1
#20;
error = (data_out == 1) ? error : error+1;
#10;
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Error===========");
end
end
endmodule
|
module verified_pulse_detect(
input clk,
input rst_n,
input data_in,
output reg data_out
);
parameter s0 = 2'b00; // initial
parameter s1 = 2'b01; // 0, 00
parameter s2 = 2'b10; // 01
parameter s3 = 2'b11; // 010
reg [1:0] pulse_level1, pulse_level2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
pulse_level1 <= s0;
else
pulse_level1 <= pulse_level2;
end
always @(*) begin
case (pulse_level1)
s0: begin
if (data_in == 0)
pulse_level2 = s1;
else
pulse_level2 = s0;
end
s1: begin
if (data_in == 1)
pulse_level2 = s2;
else
pulse_level2 = s1;
end
s2: begin
if (data_in == 0)
pulse_level2 = s3;
else
pulse_level2 = s0;
end
s3: begin
if (data_in == 1)
pulse_level2 = s2;
else
pulse_level2 = s1;
end
endcase
end
// always @(posedge clk or negedge rst_n) begin
// if (~rst_n)
// data_out <= 0;
// else if (pulse_level1 == s2 && data_in == 0)
// begin
// data_out <= 1;
// end
// else
// data_out <= 0;
// end
always @(*) begin
if (~rst_n)
data_out = 0;
else if (pulse_level1 == s2 && data_in == 0)
data_out = 1;
else
data_out = 0;
end
endmodule
|
module verified_fsm(IN,MATCH,CLK,RST);
input IN,CLK,RST;
output reg MATCH;
reg [2:0] ST_cr,ST_nt;
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
parameter s5 = 3'b101;
always@(posedge CLK or posedge RST) begin
if(RST)
ST_cr <= s0;
else
ST_cr <= ST_nt;
end
always@(*) begin
case(ST_cr)
s0:begin
if (IN==0)
ST_nt = s0;
else
ST_nt = s1;
end
s1:begin
if (IN==0)
ST_nt = s2;
else
ST_nt = s1;
end
s2:begin
if (IN==0)
ST_nt = s3;
else
ST_nt = s1;
end
s3:begin
if (IN==0)
ST_nt = s0;
else
ST_nt = s4;
end
s4:begin
if (IN==0)
ST_nt = s2;
else
ST_nt = s5;
end
s5:begin
if (IN==0)
ST_nt = s2;
else
ST_nt = s1;
end
endcase
end
always@(*) begin
if(RST)
MATCH <= 0;
else if (ST_cr == s4 && IN == 1)
MATCH <= 1;
else
MATCH <= 0;
end
endmodule
|
module main();
reg clk,rst;
reg IN;
wire MATCH;
fsm DUT(.CLK(clk),.RST(rst),.IN(IN),.MATCH(MATCH));
initial begin
clk=0;
forever #5 clk=~clk;
end
integer error = 0;
initial begin
#10;
rst =1;
#28;
rst = 0;
IN = 0;
#10 IN=0;
// $display("%b, %b", MATCH, DUT.ST_cr);//0
error = (MATCH==0)? error:error+1;
#10 IN=0;
// $display("%b, %b", MATCH, DUT.ST_cr);//00
error = (MATCH==0)? error:error+1;
#10 IN=1;
// $display("%b, %b", MATCH, DUT.ST_cr);//001
error = (MATCH==0)? error:error+1;
#10 IN=1;
// $display("%b, %b", MATCH, DUT.ST_cr);//0011
error = (MATCH==0)? error:error+1;
#10 IN=0;
// $display("%b, %b", MATCH, DUT.ST_cr);//00110
error = (MATCH==0)? error:error+1;
#10 IN=0;
// $display("%b, %b", MATCH, DUT.ST_cr);//001100
error = (MATCH==0)? error:error+1;
#10 IN=1;
// $display("%b, %b", MATCH, DUT.ST_cr);//0011001
error = (MATCH==0)? error:error+1;
#10 IN=1;
// $display("%b, %b", MATCH, DUT.ST_cr);//00110011
error = (MATCH==1)? error:error+1;
#10 IN=0;
// $display("%b, %b", MATCH, DUT.ST_cr);//001100110
error = (MATCH==0)? error:error+1;
#10 IN=0;
// $display("%b, %b", MATCH, DUT.ST_cr);//0011001100
error = (MATCH==0)? error:error+1;
#10 IN=1;
// $display("%b, %b", MATCH, DUT.ST_cr);//00110011001
error = (MATCH==0)? error:error+1;
#10 IN=1;
// $display("%b, %b", MATCH, DUT.ST_cr);//001100110011
error = (MATCH==1)? error:error+1;
if(error==0)begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Error===========");
end
$finish;
end
endmodule
|
module verified_accu(
input clk ,
input rst_n ,
input [7:0] data_in ,
input valid_in ,
output reg valid_out ,
output reg [9:0] data_out
);
reg [1:0] count;
wire add_cnt;
wire ready_add;
wire end_cnt;
reg [9:0] data_out_reg;
assign add_cnt = ready_add;
assign end_cnt = ready_add && (count == 'd3);
//count
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
count <= 0;
end
else if(end_cnt) begin
count <= 0;
end
else if(add_cnt) begin
count <= count + 1;
end
end
//data_out_reg
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out_reg <= 0;
end
else if (add_cnt && count == 0) begin
data_out_reg <= data_in;
end
else if (add_cnt) begin
data_out_reg <= data_out_reg + data_in;
end
end
//data_out
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out <= 0;
end
else if (add_cnt && count == 0) begin
data_out <= data_in;
end
else if (add_cnt) begin
data_out <= data_out + data_in;
end
end
//ready_add
assign ready_add = !valid_out | valid_in;
//valid_out
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
valid_out <= 0;
end
else if(end_cnt) begin
valid_out <= 1;
end
else begin
valid_out <= 0;
end
end
endmodule
|
module tb_valid_ready;
parameter PERIOD = 10;
reg clk = 0 ;
reg rst_n = 0 ;
reg [7:0] data_in = 0 ;
reg valid_in = 0 ;
wire valid_out ;
wire [9:0] data_out ;
initial
begin
forever #(PERIOD/2) clk=~clk;
end
initial
begin
#(PERIOD*2) rst_n = 1;
end
accu uut (
.clk ( clk ),
.rst_n ( rst_n ),
.data_in ( data_in [7:0] ),
.valid_in ( valid_in ),
.valid_out ( valid_out ),
.data_out ( data_out [9:0] )
);
initial
begin
#(PERIOD*1+0.01);
#(PERIOD) data_in = 8'd1;valid_in = 1;
#(PERIOD) data_in = 8'd2;
#(PERIOD) data_in = 8'd3;
#(PERIOD) data_in = 8'd14;
#(PERIOD) data_in = 8'd5;
#(PERIOD) data_in = 8'd2;
#(PERIOD) data_in = 8'd103;
#(PERIOD) data_in = 8'd4;
#(PERIOD) data_in = 8'd5;
#(PERIOD) data_in = 8'd6;
#(PERIOD) data_in = 8'd3;
#(PERIOD) data_in = 8'd54;
#(PERIOD*2);
$finish;
end
reg [9:0] result [0:2];
initial begin
result[0] = 9'd20;
result[1] = 9'd114;
result[2] = 9'd68;
end
integer i;
integer casenum = 0;
integer error = 0;
initial
begin
for (i = 0; i < 15; i = i + 1) begin
#((PERIOD) * 1);
if (valid_out) begin
error = (data_out == result[casenum]) ? error : error + 1;
casenum = casenum + 1;
end
end
if(error==0 && casenum==3)
begin
$display("===========Your Design Passed===========");
end
else
begin
$display("===========Error===========");
end
$finish;
end
endmodule
|
module verified_counter_12
(
input rst_n,
input clk,
input valid_count,
output reg [3:0] out
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
begin
out <= 4'b0000;
end
else if (valid_count)
begin
if (out == 4'd11)
begin
out <= 4'b0000;
end
else begin
out <= out + 1;
end
end
else begin
out <= out; // Pause the count when valid_count is invalid
end
end
endmodule
|
module counter_12_tb;
reg clk, rst_n, valid_count;
wire [3:0] out;
counter_12 dut (
.rst_n(rst_n),
.clk(clk),
.valid_count(valid_count),
.out(out)
);
always #5 clk = ~clk;
integer i = 0;
integer error = 0;
initial begin
clk = 0;
rst_n = 0;
valid_count = 0;
#20 rst_n = 1;
// testcase1: validation of valid_count
repeat(15) begin
error = (out == 0) ?error:error+1;
#10;
end
// testcase2: counter
#100 valid_count = 1;
repeat(11) begin
error = (out == i) ?error:error+1;
i = i+1;
#10;
end
// testcase3: the count is paused if valid_count is invalid
valid_count = 0;
repeat(5) begin
error = (out == 11) ?error:error+1;
#10;
end
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Failed===========", error);
end
$finish;
end
endmodule
|
module verified_signal_generator(
input clk,
input rst_n,
output reg [4:0] wave
);
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= 2'b0;
wave <= 5'b0;
end
else begin
case (state)
2'b00:
begin
if (wave == 5'b11111)
state <= 2'b01;
else
wave <= wave + 1;
end
2'b01:
begin
if (wave == 5'b00000)
state <= 2'b00;
else
wave <= wave - 1;
end
endcase
end
end
endmodule
|
module tb_signal_generator;
reg clk,rst_n;
wire[4:0] wave;
signal_generator uut(
.clk(clk),
.rst_n(rst_n),
.wave(wave)
);
reg[31:0]reference[0:99];
integer i = 0;
integer error = 0;
// integer outfile;
initial begin
$readmemh("tri_gen.txt",reference);
clk = 0;
rst_n = 0;
#10
rst_n =1;
// outfile = $fopen("tri_gen.txt", "w");
repeat(100) begin
// $fwrite(outfile, "%h\n", wave);
// $display(wave);
error=(wave==reference[i])?error:error+1;
#10;
i = i+1;
end
// $fclose(outfile);
if(error==0)
begin
$display("===========Your Design Passed===========");
end
else
begin
$display("===========Error===========");
end
$finish;
end
always #5 clk =~clk;
endmodule
|
module verified_JC_counter(
input clk ,
input rst_n,
output reg [63:0] Q
);
always@(posedge clk or negedge rst_n)begin
if(!rst_n) Q <= 'd0;
else if(!Q[0]) Q <= {1'b1, Q[63 : 1]};
else Q <= {1'b0, Q[63 : 1]};
end
endmodule
|
module testbench;
// Parameters
parameter CLK_PERIOD = 10; // Clock period in simulation time units
// Inputs
reg clk;
reg rst_n;
// Outputs
wire [63:0] Q;
// Instantiate the module
JC_counter uut (
.clk(clk),
.rst_n(rst_n),
.Q(Q)
);
// Clock generation
always #((CLK_PERIOD)/2) clk = ~clk;
integer error=0;
// Initial block for stimulus generation
initial begin
// Initialize inputs
clk = 0;
rst_n = 1;
// Wait for a few clock cycles
#((CLK_PERIOD) * 2);
// Release reset
rst_n = 0;
#((CLK_PERIOD) * 2);
rst_n = 1;
// Simulate for a number of clock cycles
#((CLK_PERIOD) * 20);
error = (Q ==64'b 1111111111111111111100000000000000000000000000000000000000000000)? error : error+1;
#((CLK_PERIOD) * 44);
error = (Q ==64'b 1111111111111111111111111111111111111111111111111111111111111111)? error : error+1;
#((CLK_PERIOD) * 1);
error = (Q ==64'b 0111111111111111111111111111111111111111111111111111111111111111)? error : error+1;
#((CLK_PERIOD) * 62);
error = (Q ==64'b 0000000000000000000000000000000000000000000000000000000000000001)? error : error+1;
if (error == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Error===========");
end
// $display("Q = %b", Q);
// Finish simulation
$finish;
end
endmodule
|
module verified_div_16bit(
input wire [15:0] A,
input wire [7:0] B,
output wire [15:0] result,
output wire [15:0] odd
);
reg [15:0] a_reg;
reg [15:0] b_reg;
reg [31:0] tmp_a;
reg [31:0] tmp_b;
integer i;
always@(*) begin
a_reg = A;
b_reg = B;
end
always@(*) begin
begin
tmp_a = {16'b0, a_reg};
tmp_b = {b_reg, 16'b0};
for(i = 0;i < 16;i = i+1) begin
tmp_a = tmp_a << 1;
if (tmp_a >= tmp_b) begin
tmp_a = tmp_a - tmp_b + 1;
end
else begin
tmp_a = tmp_a;
end
end
end
end
assign odd = tmp_a[31:16];
assign result = tmp_a[15:0];
endmodule
|
module multi_pipe_tb;
reg clk;
reg rst_n;
reg [3:0] mul_a;
reg [3:0] mul_b;
wire [7:0] mul_out;
wire signed [7:0] perfect = mul_a*mul_b;
// Instantiate the DUT (Design Under Test)
multi_pipe_4bit #(.size(4)) dut (
.clk(clk),
.rst_n(rst_n),
.mul_a(mul_a),
.mul_b(mul_b),
.mul_out(mul_out)
);
// Generate clock
always #5 clk = ~clk;
integer fail_count =0;
integer i=0;
initial begin
// Initialize inputs
clk = 0;
rst_n = 0;
mul_a = 4'b0;
mul_b = 4'b0;
// Wait for a few clock cycles for reset to settle
#10;
// Apply reset
rst_n = 1;
// Perform test case
for (i = 0; i < 100; i = i + 1) begin
mul_a = $random;
mul_b = $random;
#10;
// without pipeline
fail_count = (perfect == mul_out)? fail_count+1:fail_count;
#20;
// $display("%d, %d, %d, %d", mul_a, mul_b, perfect, mul_out);
fail_count = (perfect == mul_out)? fail_count:fail_count+1;
end
if (fail_count == 0) begin
$display("===========Your Design Passed===========");
end
else begin
$display("===========Test completed with %d / 100 failures===========", fail_count);
end
$finish;
end
endmodule
|
module verified_multi_pipe#(
parameter size = 4
)(
input clk ,
input rst_n ,
input [size-1:0] mul_a ,
input [size-1:0] mul_b ,
output reg [size*2-1:0] mul_out
);
parameter N = 2 * size;
reg [N-1:0] sum_tmp1 ;
reg [N-1:0] sum_tmp2 ;
wire [N-1:0] mul_a_extend ;
wire [N-1:0] mul_b_extend ;
wire [N-1:0] mul_result[size-1:0] ;
genvar i;
generate
for(i = 0; i < size; i = i + 1) begin:add
assign mul_result[i] = mul_b[i] ? mul_a_extend << i : 'd0;
end
endgenerate
assign mul_a_extend = {{size{1'b0}}, mul_a};
assign mul_b_extend = {{size{1'b0}}, mul_b};
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
sum_tmp1 <= 'd0;
sum_tmp2 <= 'd0;
end
else begin
sum_tmp1 <= mul_result[0] + mul_result[1];
sum_tmp2 <= mul_result[2] + mul_result[3];
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
mul_out <= 'd0;
end
else begin
mul_out <= sum_tmp1 + sum_tmp2;
end
end
endmodule
|
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