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module toycpu_core(
input clk, // clock
input rst, // reset
// ICACHE port
output reg [31:0] ic_addr,
output reg ic_rq,
input [31:0] ic_data_out,
input ic_data_out_valid,
// LSU port
input [31:0] data_in, // bus data in
input data_in_ready, // bus data ready
input data_ack, // acknowledge write op
output data_wr, // request data write
output data_rd, // request data read
output [31:0] data_address, // output data address
output [31:0] data_out, // data to be written
// Interrupts
input irq, // IRQ requested
input [3:0] irqn, // IRQ number
output irq_ack, // Interrupt acknowledged and processed
output irq_busy, // Busy doing current interrupt (maintain your fifo outside!)
// Debugging
output reg [31:0] debug_reg_out,
input [3:0] debug_reg_num,
input debug,
input step,
output reg step_ack,
input stall,
// Stack
output [31:0] stack_real_addr_a,
output [31:0] stack_real_addr_b,
output stack_wr_a,
output [31:0] stack_datain_a,
input [31:0] stack_data_a,
input [31:0] stack_data_b
);
parameter STACK_MAX = `RAM_DEPTH-1; // see above
parameter IRQ_BASE = 28'h2000; // without the lowest 4 bits
reg inIRQ;
reg out_irq_ack;
reg doingIRQ; // switch to shadows
reg inCritical; // block IRQ handling
assign irq_ack = out_irq_ack;
assign irq_busy = inIRQ;
// Performance counters
reg [31:0] clk_counter;
reg [31:0] instr_counter;
reg [31:0] memop_counter;
always @(posedge clk)
begin
if (!rst) begin
clk_counter <= 0;
end else begin
clk_counter <= clk_counter + 1;
end
end
//// Definitions
// Magic numbers
parameter ENTRY_PC = 32'h20100;
// FSM states
parameter S_IFETCH = 0;
parameter S_IFETCH_WAIT = 1;
parameter S_DECODE = 2;
parameter S_EXEC_BRANCH = 3;
parameter S_EXEC_ALU = 4;
parameter S_MEMREAD_WAIT = 5;
parameter S_MEMWRITE_WAIT = 6;
parameter S_SETUP_IRQ = 7;
parameter S_STACKMAPREAD = 8;
parameter S_DECODE0 = 9;
`ifdef SYNCSTACK
parameter S_DECODE_STAGE = S_DECODE0;
`endif
`ifndef SYNCSTACK
parameter S_DECODE_STAGE = S_DECODE;
`endif
parameter S_DEBUG_WAIT = 10;
parameter S_DEBUG_WAIT_1 = 11;
parameter S_EXEC_IMUL = 12;
parameter S_EXEC_IMUL1 = 13;
parameter S_EXEC_IMUL2 = 14;
parameter S_EXEC_IMUL3 = 15;
parameter S_EXEC_IMUL4 = 16;
parameter S_CUSTOMWAIT = 17;
parameter S_STACKMAPREAD0 = 18;
`include "opcodes.v"
// CPU core registers
reg [31:0] PC;
reg [31:0] SP;
reg [31:0] FP;
reg [31:0] FPREL;
reg CND;
reg CARRY;
// Shadow registers for IRQ handling
reg [31:0] ShadowPC;
reg [31:0] ShadowSP;
reg [31:0] ShadowFP;
reg [31:0] ShadowFPREL;
reg ShadowCARRY;
// Internal registers
reg [31:0] instr;
reg [31:0] result;
reg do_data_rd;
reg do_data_wr;
reg [31:0] do_data_address;
reg [31:0] do_data_data;
// FSM state register
reg [7:0] state;
reg [31:0] operand_a;
reg [31:0] operand_b;
`ifdef ENABLE_IMUL
reg [31:0] mul_1;
reg [31:0] mul_2;
reg [31:0] mul_3;
reg [31:0] mul_4;
// Pipelined multiplication, shadowed by FSM stages
always @(posedge clk) begin
mul_1 <= operand_a * operand_b; // S_EXEC_IMUL
mul_2 <= mul_1; // S_EXEC_IMUL1
mul_3 <= mul_2; // S_EXEC_IMUL2
mul_4 <= mul_3; // S_EXEC_IMUL3
end
`endif
// Wires connecting to the stack ports
wire [31:0] stack_addr_a;
wire [31:0] stack_addr_b;
//// Instruction decode logic
wire [2:0] instr_class;
assign instr_class = instr[2:0];
wire [31:0] immed;
wire signed [31:0] signed_immed;
// sign-extended immediate
assign signed_immed = {(instr[31]==1)?8'b11111111:8'b0, instr[31:8]};
// 0-extended immediate
assign immed = {8'b0, instr[31:8]};
// opcode
wire [4:0] opcode;
assign opcode = instr[7:3];
wire signed [31:0] immed_fpaddr0;
assign immed_fpaddr0 = (opcode==READABS?0:FP) + signed_immed;
wire signed [31:0] immed_fpreladdr;
assign immed_fpreladdr = immed_fpaddr0 + FPREL;
wire signed [31:0] immed_fpaddr;
// assuming READFPREL == WRITEFPREL
assign immed_fpaddr = (opcode == READFPREL||opcode==READABS)?immed_fpreladdr:immed_fpaddr0;
// Debugging state
reg doingStep;
/// ALU
wire [32:0] alu_result; // 32 bits + carry
reg do_writeback;
reg do_writeback_fp;
wire alu_signed = immed[0];
`ifdef ENABLE_IMUL
wire alu_compop = opcode==ALU_LE || opcode == ALU_LEQ
|| opcode == ALU_GE || opcode == ALU_GEQ;
wire alu_compunsigned =
(opcode == ALU_LE)?(operand_b < operand_a):
(opcode == ALU_LEQ)?(operand_b <= operand_a):
(opcode == ALU_GE)?(operand_b > operand_a):
(opcode == ALU_GEQ)?(operand_b >= operand_a):0;
wire alu_compsigned =
(opcode == ALU_LE)?($signed(operand_b) < $signed(operand_a)):
(opcode == ALU_LEQ)?($signed(operand_b) <= $signed(operand_a)):
(opcode == ALU_GE)?($signed(operand_b) > $signed(operand_a)):
(opcode == ALU_GEQ)?($signed(operand_b) >= $signed(operand_a)):0;
`endif
assign alu_result = ((opcode == ALU_ADD)? operand_a + operand_b:
(opcode == ALU_AND)? operand_a & operand_b:
(opcode == ALU_OR)? operand_a | operand_b:
(opcode == ALU_XOR)? operand_a ^ operand_b:
(opcode == ALU_EQ)? (operand_a == operand_b):
`ifdef ENABLE_IMUL
(alu_compop)?{31'b0,alu_signed?alu_compsigned:alu_compunsigned}:
`endif
(opcode == ALU_NOT)? (~operand_a):
(opcode == ALU_SHL)? {operand_a[30:0],1'b0}:
(opcode == ALU_ASHR
|| opcode == ALU_SHR)?
{(opcode==ALU_ASHR?operand_a[31]:1'b0),operand_a[31:1]}:
(opcode == ALU_SELECT)?(CND?operand_b:operand_a):
operand_a);
// PCU
wire [31:0] branch_PC;
wire [31:0] rel_PC;
wire [31:0] INC_PC;
wire cbranch;
assign cbranch = operand_a != 0;
assign rel_PC = PC + signed_immed;
assign INC_PC = PC + 1;
assign branch_PC = ((opcode == BR_JMP)?immed:
(opcode == BR_JMPR)?rel_PC:
(opcode == BR_JMPC)?(cbranch?immed:INC_PC):
(opcode == BR_JMPRC)?(cbranch?rel_PC:INC_PC):
(opcode == BR_JMPI)?operand_a:
(opcode == BR_JMPRI)?(PC + operand_a):INC_PC);
wire branch_decsp;
assign branch_decsp = ((opcode == BR_JMPI) || (opcode == BR_JMPRI)
|| (opcode == BR_JMPC) || (opcode == BR_JMPRC));
assign stack_real_addr_a = inIRQ?(STACK_MAX - stack_addr_a):stack_addr_a;
assign stack_real_addr_b = inIRQ?(STACK_MAX - stack_addr_b):stack_addr_b;
reg mapped_stack;
reg [31:0] mapped_stack_addr;
// Stack is a 2-read 1-write port ram
/*
*/
// Combinational logic for the stack ports.
// This is one of the slowest paths, consider splitting.
assign stack_wr_a = (state == S_IFETCH) && (do_writeback||do_writeback_fp);
assign stack_addr_a =
mapped_stack?mapped_stack_addr:
( (state == S_DECODE_STAGE)? ((instr_class == IC_FPREAD)?immed_fpaddr:SP-1):
stack_wr_a? ((instr_class == IC_FPWRITE)?immed_fpaddr:SP) : 0 );
assign stack_addr_b = ( (SP>2)?SP-2:0 );
assign stack_datain_a = result;
wire [31:0] writeback_SP;
assign writeback_SP = do_writeback?(mapped_stack?SP:SP+1):SP;
assign data_address = do_data_address;
assign data_wr = do_data_wr;
assign data_rd = do_data_rd;
assign data_out = do_data_data;
// Debugging registers (can be queried via debug_reg_* interface)
reg [31:0] LAST_BRANCH;
reg [31:0] LAST_PUSH;
reg [31:0] LAST_POP1;
reg [31:0] LAST_POP2;
reg [31:0] LAST_INSTR;
reg dbgenable;
// Placeholder for the custom hoisted logic
`include "custom_hoisted.v"
// Main CPU core FSM
always @(posedge clk)
begin
if (~rst) begin // Reset logic
state <= S_IFETCH; // start fetching next instruction
PC <= ENTRY_PC; // set PC to the entry point
SP <= 32'h0; // flush stack
FP <= 32'h0;
FPREL <= 0;
dbgenable <= 0;
LAST_BRANCH <= 0;
result <= 0;
operand_a <= 0;
operand_b <= 0;
ic_rq <= 0;
do_writeback <= 0;
do_writeback_fp <= 0;
// bus control
do_data_rd <= 1'b0;
do_data_wr <= 1'b0;
do_data_address <= 32'b0;
// IRQ stuff
inIRQ <= 0;
out_irq_ack <= 0;
doingIRQ <= 0;
inCritical <= 0;
instr <= 0;
LAST_POP1 <= 0;
LAST_POP2 <= 0;
LAST_INSTR <= 0;
LAST_PUSH <= 0;
doingStep <= 0;
step_ack <= 0;
instr_counter <= 0;
memop_counter <= 0;
mapped_stack <= 0;
// Custom reset logic
`include "custom_reset.v"
/////
end else if(~stall) begin // if (!rst)
case (state) // State machine logic
S_DEBUG_WAIT: begin // wait for step to go up
if (debug && step) begin
state <= S_IFETCH;
end
end
S_DEBUG_WAIT_1: begin // wait for step to go low after ack
if (~step) begin
step_ack <= 0;
state <= S_DEBUG_WAIT;
end
end
S_IFETCH: begin // Starting fetching an instruction, set up a bus read
if (do_writeback) begin
SP <= writeback_SP;
mapped_stack <= 0;
LAST_PUSH <= result;
do_writeback <= 0;
end
if (do_writeback_fp) begin
do_writeback_fp <= 0;
end
`ifdef DEBUG
if (SP >= STACK_MAX) begin
$display("SP OVERFLOW %x", SP);
$finish;
end
`endif
if (debug && ~step) begin
state <= S_DEBUG_WAIT;
end else
if (debug && doingStep) begin
doingStep <= 0;
step_ack <= 1;
state <= S_DEBUG_WAIT_1;
end else
begin
if (step) doingStep <= 1;
if (irq && !doingIRQ && !out_irq_ack && !inCritical) begin
// set up IRQ mode
doingIRQ <= 1;
inIRQ <= 1;
// Save registers
ShadowPC <= PC;
ShadowSP <= writeback_SP;
ShadowFP <= FP;
ShadowFPREL <= FPREL;
ShadowCARRY <= CARRY;
PC <= 0; // not really
SP <= 0; // may put interrupt argument data on top of stack, probably
FP <= 0;
FPREL <= 0;
// Fetch IRQ vector data
do_data_rd <= 1;
do_data_address <= {IRQ_BASE,irqn};
state <= S_SETUP_IRQ;
end else begin
ic_rq <= 1;
ic_addr <= PC;
state <= S_IFETCH_WAIT;
out_irq_ack <= 0;
end
end // case: S_IFETCH
end // case: S_IFETCH
S_SETUP_IRQ: begin
if (data_in_ready) begin
PC <= data_in;
state <= S_IFETCH;
do_data_rd <= 0;
end else begin
state <= S_SETUP_IRQ;
end
end
S_IFETCH_WAIT: begin // Waiting for a bus to deliver a next instruction
if (ic_data_out_valid) begin
instr <= ic_data_out;
LAST_INSTR <= ic_data_out;
`ifdef SYNCSTACK
state <= S_DECODE0;
`endif
`ifndef SYNCSTACK
state <= S_DECODE;
`endif
ic_rq <= 0;
end else begin
state <= S_IFETCH_WAIT;
end
end // case: S_IFETCH_WAIT
`ifdef SYNCSTACK
S_DECODE0: begin
state <= S_DECODE;
end
`endif
S_DECODE: begin // Decode an instruction,
// fetch stack arguments, write immediate to stack, evaluate next PC, etc.
`ifdef DEBUG
if (dbgenable) begin
$display ("INSTR=%X [%X]", instr, PC);
$display ("SP=%X FP=%X", SP, FP);
$display ("STK=%X, %X", stack_data_a, stack_data_b);
end
`endif
// Perf. counter:
instr_counter <= instr_counter + 1;
// Debugging
LAST_POP1 <= stack_data_a;
LAST_POP2 <= stack_data_b;
// Decode instruction class and select next stage accordingly
case (instr_class)
IC_ALU: begin // for an ALU instruction fetch two values from the stack
// stack port reads should have been initiated by combinational logic
operand_a <= stack_data_a;
operand_b <= stack_data_b;
`ifdef DEBUG
if (opcode == ALU_DBG) begin
if (stack_data_b > 1 && stack_data_b < 999)
$display("DEBUG[%d]=%d", stack_data_b, stack_data_a);
else
if (stack_data_b == 0)
$write("%c", stack_data_a[7:0]);
else if (stack_data_b == 1) begin
$display("Registers: PC=%x, SP=%x, FP=%x", PC, SP, FP);
end
if (stack_data_b == 999) dbgenable <= stack_data_a[0];
end
`endif
// decrement stack pointer:
SP <= (opcode == ALU_NOT || opcode == ALU_SHR || opcode == ALU_ASHR
|| opcode == ALU_SHL)?SP-1:SP - 2;
`ifdef ENABLE_IMUL
if (opcode == ALU_MUL) begin
state <= S_EXEC_IMUL;
end else
`endif
state <= S_EXEC_ALU;
PC <= INC_PC; // simply the next PC
end
IC_BRANCH: begin // for a conditional or an indirect branch, use top of the stack
operand_a <= stack_data_a;
state <= S_EXEC_BRANCH;
end
IC_IMMED: begin // push an immediate
state <= S_IFETCH;
do_writeback <= 1;
PC <= INC_PC;
result <= (opcode==PUSHSE?signed_immed:
opcode==PUSH?immed:
opcode==PUSHL?immed:
opcode==PUSHH?{immed[15:0],stack_data_a[15:0]}:0);
if (opcode == PUSHH) SP <= SP - 1;
end
IC_FPREAD: begin // read FP-relative stack location
result <= stack_data_a; // by combinational logic
PC <= INC_PC;
state <= S_IFETCH;
do_writeback <= 1;
end
IC_FPWRITE: begin // write to FP-relative stack location
PC <= INC_PC;
operand_a <= stack_data_a; // why operand_a?
result <= stack_data_a;
SP <= SP - 1;
state <= S_IFETCH;
do_writeback_fp <= 1;
end
IC_MEMREAD: begin // read from the bus
// Mapped stack read
if ((stack_data_a & 32'hffff0000) == 0) begin
mapped_stack <= 1;
mapped_stack_addr <= stack_data_a;
state <= S_STACKMAPREAD0;
end else begin
memop_counter <= memop_counter + 1;
state <= S_MEMREAD_WAIT;
do_data_rd <= 1;
do_data_address <= stack_data_a;
end
SP <= SP - 1;
PC <= INC_PC;
end
IC_MEMWRITE: begin
if ((stack_data_a & 32'hffff0000) == 0) begin
state <= S_IFETCH;
do_writeback <= 1;
mapped_stack <= 1;
mapped_stack_addr <= stack_data_a;
result <= stack_data_b;
end else begin
memop_counter <= memop_counter + 1;
state <= S_MEMWRITE_WAIT;
do_data_rd <= 0;
do_data_wr <= 1;
do_data_address <= stack_data_a;
do_data_data <= stack_data_b;
end
PC <= INC_PC;
SP <= SP - 2;
end
IC_STACK: begin
if (opcode == CUSTOMOP) begin
// Custom op exec stage
`include "custom_exec.v"
///////////////////////
end else begin
if (opcode == PUSHSP
|| opcode == PUSHFP
|| opcode == PUSHPC
|| opcode == PUSHCARRY
|| opcode == PUSHCOUNTER
|| opcode == DUP) begin
state <= S_IFETCH;
do_writeback <= 1;
end
else begin
if (opcode == SETSP
|| opcode == SETFP
|| opcode == SETFPREL
|| opcode == SETPC
|| opcode == SETPCSP
|| opcode == SETCND
|| opcode == POP) begin
SP <= SP - 1;
end
state <= S_IFETCH;
end
result <= (opcode == PUSHSP)?SP:
(opcode == PUSHPC)?PC:
(opcode == PUSHFP)?FP:
(opcode == PUSHCARRY)?CARRY:
(opcode == PUSHCOUNTER)?
((immed == 0)?clk_counter:
(immed == 1)?instr_counter:
(immed == 2)?memop_counter:0):
stack_data_a;
if (opcode == SETSP) SP <= stack_data_a;
if (opcode == SETFP)
FP <= stack_data_a;
if (opcode == SETCND)
CND <= stack_data_a[0];
if (opcode == SETFPREL)
FPREL <= stack_data_a;
if (opcode == SETPC) PC <= stack_data_a;
else if (opcode == SETPCSP)
begin
PC <= stack_data_a;
SP <= FPREL;
end else PC <= INC_PC;
if (opcode == SETCRITICAL) inCritical <= 1;
else if (opcode == LIFTCRITICAL) inCritical <= 0;
end // else: !if(opcode == CUSTOMOP)
end
endcase // case (instr_class)
end // case: S_DECODE
S_EXEC_BRANCH: begin
if (opcode == BR_IRQACK) begin
PC <= ShadowPC;
SP <= ShadowSP;
FP <= ShadowFP;
FPREL <= ShadowFPREL;
CARRY <= ShadowCARRY;
out_irq_ack <= 1;
inIRQ <= 0;
doingIRQ <= 0;
state <= S_IFETCH;
end else begin // if (opcode == BR_IRQACK)
`ifdef DEBUG
if (dbgenable) begin
$display ("BRANCH_PC(%X) = %X -- %X [%X]", operand_a, PC, branch_PC, SP);
end
`endif
// Calculate the next PC
LAST_BRANCH <= PC;
PC <= branch_PC; // from combinational logic
state <= S_IFETCH;
if (branch_decsp) begin
SP <= SP - 1; // this branch op used a value from stack
end
end
end
S_EXEC_ALU: begin // execute an ALU operation, write back the result
state <= S_IFETCH;
do_writeback <= 1;
result <= alu_result[31:0]; // done by combinational logic
CARRY <= alu_result[32];
`ifdef DEBUG
if (dbgenable) begin
$display("ALU_RESULT = %x", alu_result);
end
`endif
end
`ifdef ENABLE_IMUL
// Follow the multiplication pipeline progress
S_EXEC_IMUL: state <= S_EXEC_IMUL1;
S_EXEC_IMUL1: state <= S_EXEC_IMUL2;
S_EXEC_IMUL2: state <= S_EXEC_IMUL3;
S_EXEC_IMUL3: state <= S_EXEC_IMUL4;
S_EXEC_IMUL4: begin
result <= mul_3;
state <= S_IFETCH;
do_writeback <= 1;
end
`endif
S_STACKMAPREAD0: begin
state <= S_STACKMAPREAD;
mapped_stack <= 0;
end
S_STACKMAPREAD: begin
result <= stack_data_a;
mapped_stack <= 0;
state <= S_IFETCH;
do_writeback <= 1;
end
S_MEMREAD_WAIT: begin // wait for the bus to return a sane result
if (data_in_ready) begin
result <= data_in;
state <= S_IFETCH;
do_writeback <= 1;
do_data_rd <= 0;
end else begin
state <= S_MEMREAD_WAIT;
end
end
S_MEMWRITE_WAIT: begin // wait for the bus to assert it's done writing
if (data_ack) begin
state <= S_IFETCH;
do_data_wr <= 0;
end else begin
state <= S_MEMWRITE_WAIT;
end
end
S_CUSTOMWAIT: begin
// Custom ops blocking wait stage
`include "custom_wait.v"
///////////////
end
endcase
end
end // always @ (posedge clk)
// Debugging register polling interface
always @(posedge clk)
if (!rst) begin
debug_reg_out <= 0;
end else begin
case (debug_reg_num)
`DEBUG_REG_PC: debug_reg_out <= PC;
`DEBUG_REG_SP: debug_reg_out <= SP;
`DEBUG_REG_LAST_BRANCH: debug_reg_out <= LAST_BRANCH;
`DEBUG_REG_LAST_PUSH: debug_reg_out <= LAST_PUSH;
`DEBUG_REG_LAST_POP1: debug_reg_out <= LAST_POP1;
`DEBUG_REG_LAST_POP2: debug_reg_out <= LAST_POP2;
`DEBUG_REG_LAST_INSTR: debug_reg_out <= LAST_INSTR;
endcase
end
endmodule //toycpu_core
|
module toycpu(
input clk, // clock
input rst, // reset
// Memory bus
input [31:0] bus_data_in, // bus data in
input bus_data_in_ready, // bus data ready
input bus_data_ack, // acknowledge write op
output bus_data_wr, // request data write
output bus_data_rd, // request data read
output [31:0] bus_data_address, // output data address
output [31:0] bus_data_out, // data to be written
// CPU signals
input irq, // IRQ requested
input [3:0] irqn, // IRQ number
output irq_ack, // Interrupt acknowledged and processed
output irq_busy, // Busy doing current interrupt (maintain your fifo outside!)
output [31:0] debug_reg_out,
input [3:0] debug_reg_num,
input debug,
input step,
output step_ack,
input stall
);
wire [31:0] ic_addr;
wire [31:0] ic_data_out;
wire [31:0] ic_bus_data_address;
wire [31:0] ic_data_in;
wire [31:0] data_in;
wire [31:0] data_out;
wire [31:0] data_address;
wire ic_rq;
wire ic_data_out_valid;
wire data_ack;
wire data_wr;
wire data_rd;
wire data_in_ready;
wire ic_data_in_ready;
wire ic_data_rd;
wire [31:0] stack_real_addr_a;
wire [31:0] stack_real_addr_b;
wire stack_wr_a;
wire [31:0] stack_datain_a;
wire [31:0] stack_data_a;
wire [31:0] stack_data_b;
toycpu_core core1(.clk(clk),
.rst(rst),
.ic_addr(ic_addr),
.ic_rq(ic_rq),
.ic_data_out(ic_data_out),
.ic_data_out_valid(ic_data_out_valid),
.data_in(data_in),
.data_in_ready(data_in_ready),
.data_ack(data_ack),
.data_wr(data_wr),
.data_rd(data_rd),
.data_address(data_address),
.data_out(data_out),
.irq(irq),
.irqn(irqn),
.irq_ack(irq_ack),
.irq_busy(irq_busy),
.debug_reg_out(debug_reg_out),
.debug_reg_num(debug_reg_num),
.debug(debug),
.step(step),
.step_ack(step_ack),
.stall(stall),
.stack_real_addr_a(stack_real_addr_a),
.stack_real_addr_b(stack_real_addr_b),
.stack_data_a(stack_data_a),
.stack_data_b(stack_data_b),
.stack_wr_a(stack_wr_a),
.stack_datain_a(stack_datain_a)
);
toyblockram stack ( .clk(clk),
.addr_a(stack_real_addr_a),
.data_a(stack_data_a),
.datain_a(stack_datain_a),
.wr_a(stack_wr_a),
.addr_b(stack_real_addr_b),
.data_b(stack_data_b)
);
toy_icache cache1 (.clk(clk),
.reset(rst),
.ic_addr(ic_addr),
.ic_rq(ic_rq),
.ic_data_out_valid(ic_data_out_valid),
.ic_data_out(ic_data_out),
.data_in(ic_data_in),
.data_in_ready(ic_data_in_ready),
.data_rd(ic_data_rd),
.data_address(ic_bus_data_address));
wire grant_ic;
wire grant_lsu;
reg ic_rq_cnt;
reg lsu_rq_cnt;
wire gnt2;
wire gnt3;
arbiter arb1 (.clk(clk),
.rst(!rst),
.req0(ic_rq_cnt),
.req1(lsu_rq_cnt),
.req2(0),
.req3(0),
.gnt0(grant_ic),
.gnt1(grant_lsu),
.gnt2(gnt2),
.gnt3(gnt3)
);
always @(posedge clk)
if(!rst) begin
ic_rq_cnt <= 0;
lsu_rq_cnt <= 0;
end else begin
if (ic_data_rd) ic_rq_cnt <= 1;
else if (grant_ic && !bus_data_in_ready) ic_rq_cnt <= 0;
if (data_rd|data_wr) lsu_rq_cnt <= 1;
else if (grant_lsu && !bus_data_in_ready && !bus_data_ack)
lsu_rq_cnt <= 0;
end
assign ic_data_in_ready = grant_ic?bus_data_in_ready:0;
assign data_in_ready = grant_lsu?bus_data_in_ready:0;
assign ic_data_in = grant_ic?bus_data_in:0;
assign data_in = grant_lsu?bus_data_in:0;
// Memory bus combinational logic
assign bus_data_address = grant_ic?ic_bus_data_address:data_address;
assign bus_data_wr = grant_lsu?data_wr:0;
assign bus_data_rd = grant_ic?ic_data_rd:grant_lsu?data_rd:0;
assign bus_data_out = grant_lsu?data_out:0;
assign data_ack = grant_lsu?bus_data_ack:0;
endmodule // toycpu
|
module vram(input clk,
input [12:0] p1_addr,
input [7:0] p1_data,
input p1_we,
input [12:0] p2_addr,
output reg [7:0] p2_data);
reg [7:0] mem[0:(3*2048)-1];
always @(posedge clk)
begin
if (p1_we) begin
mem[p1_addr] <= p1_data;
end
p2_data <= mem[p2_addr];
end
endmodule
|
module vgatop(input clk, // 100MHz clk
input rst,
input clk25mhz,
output hsync,
output vsync,
output rgb,
input [12:0] vmem_in_addr,
input [7:0] vmem_in_data,
input vmem_we);
wire [12:0] vmem_out_addr;
wire [7:0] vmem_out_data;
vram vram1(.clk(clk),
.p1_addr(vmem_in_addr),
.p1_data(vmem_in_data),
.p1_we(vmem_we),
.p2_addr(vmem_out_addr),
.p2_data(vmem_out_data)
);
vga vga1(.clk(clk),
.rst(rst),
.clk25mhz(clk25mhz),
.vmem_data(vmem_out_data),
.vmem_addr(vmem_out_addr),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb));
endmodule
|
module toyblockram (input clk,
input [31:0] addr_a,
output [31:0] data_a,
input [31:0] datain_a,
input wr_a,
input [31:0] addr_b,
output [31:0] data_b
);
parameter RAM_DEPTH = `RAM_DEPTH;
reg [31:0] mem [0:RAM_DEPTH-1];
assign data_a = wr_a?datain_a:mem[addr_a];
assign data_b = mem[addr_b];
// Expect 2-port (1rw+1ro) to be inferred
always @(posedge clk)
begin
if (wr_a) begin
mem[addr_a] <= datain_a;
`ifdef DEBUG
$display("STACK: [%x] <- %x",addr_a, datain_a);
`endif
end
end
endmodule // toyblockram
|
module toyblockram (input clk,
input [31:0] addr_a,
output reg [31:0] data_a,
input [31:0] datain_a,
input wr_a,
input [31:0] addr_b,
output reg [31:0] data_b
);
parameter RAM_DEPTH = `RAM_DEPTH;
(* RAM_STYLE="BLOCK" *)
reg [31:0] mem [0:RAM_DEPTH-1];
// Expect 2-port (1rw+1ro) to be inferred
always @(posedge clk)
begin
if (wr_a) begin
mem[addr_a] <= datain_a;
data_a <= datain_a;
end else data_a <= mem[addr_a];
data_b <= mem[addr_b];
end
endmodule // toyblockram
|
module vga(input clk, // system clock (100mhz)
input rst,
input clk25mhz, // vga pixel clock (25.13MHz)
// one vmem port is used by the VGA module,
// another is mmaped for the CPU.
//
// Spartan6 vmem is made of 3 x 2048*8 brams
//
// Layout:
// 0-1023 - font rows for 127 "printable" characters
// 1024-XXX - 80x60 chars vmem
input [7:0] vmem_data,
output [12:0] vmem_addr,
// Monochrome VGA pins
output hsync,
output vsync,
output rgb // monochrome output, all three channels 0 or 1
);
reg [23:0] blinkreg;
always @(posedge clk)
if (!rst)
blinkreg <= 0;
else
blinkreg <= blinkreg + 1;
// Pixels are fed via a small FIFO
// vmem fsm:
// CHR0: start fetching next character -> CHRR
// CHRR: fetch a font row -> CHRR1
// CHRR1: push it into fifo or wait, -> CHR0/EOL
// EOL: increment row -> CHR0/VSYNC
// VSYNC: start over again -> CHR0
reg fifo_en;
reg fifo_rd;
reg [7:0] fifo_in;
wire fifo_full;
wire [7:0] fifo_out;
wire fifo_empty;
smallfifo1 fifo1(.rst(rst),
.clk_in(clk),
.fifo_in(fifo_in),
.fifo_en(fifo_en),
.fifo_full(fifo_full),
.clk_out(clk25mhz),
.fifo_out(fifo_out),
.fifo_empty(fifo_empty),
.fifo_rd(fifo_rd));
reg [2:0] fontrow;
reg [12:0] chrpos;
reg [12:0] chrrowpos;
wire [12:0] chrposnxt;
assign chrposnxt = chrpos + 1;
wire chr_eol;
reg [7:0] lineno;
reg [7:0] colno;
assign chr_eol = (colno)>=79;
reg [7:0] ascii;
reg [3:0] chrstate;
wire [12:0] addr_chr0;
wire [12:0] addr_chrr;
assign addr_chr0 = chrpos;
assign addr_chrr = {4'b0,ascii[6:0],fontrow[2:0]};
parameter VMEMSTART = 1024;
parameter VMEMEND = 1024 + 80*60;
parameter S_VSYNC = 0;
parameter S_CHR0 = 1;
parameter S_CHRR = 2;
parameter S_CHRR1 = 3;
parameter S_EOL = 4;
assign vmem_addr = chrstate==S_CHR0?addr_chr0:addr_chrr;
always @(posedge clk)
if (!rst) begin
fifo_en <= 0;
fontrow <= 0;
chrpos <= VMEMSTART;
chrrowpos <= VMEMSTART;
chrstate <= S_VSYNC;
ascii <= 0;
fifo_in <= 0;
lineno <= 0;
colno <= 0;
end else begin // if (!rst)
case(chrstate)
S_VSYNC: begin
fontrow <= 0;
chrpos <= VMEMSTART;
chrrowpos <= VMEMSTART;
chrstate <= S_CHR0;
lineno <= 0;
colno <= 0;
end
S_CHR0: begin
fifo_en <= 0;
//vmem_addr <= addr_chr0;
chrstate <= S_CHRR;
end
S_CHRR: begin
ascii <= vmem_data;
//vmem_addr <= addr_chrr;
chrstate <= S_CHRR1;
end
S_CHRR1: begin
if (~fifo_full) begin
chrpos <= chrposnxt;
colno <= colno + 1;
fifo_in <= (blinkreg[23] & ascii[7])?vmem_data^8'hff:vmem_data; // bit 8 = inv
fifo_en <= 1;
if (chr_eol) begin
chrstate <= S_EOL;
end else begin
chrstate <= S_CHR0;
end
end else begin
chrstate <= S_CHRR1; // keep banging the same row
end
end // case: CHRR1
S_EOL: begin
fifo_en <= 0;
colno <= 0;
// a next font row or a next char row
if (fontrow<7) begin
fontrow <= fontrow + 1;
chrpos <= chrrowpos; // back to the beginning of the same char row
chrstate <= S_CHR0;
end else begin
fontrow <= 0;
lineno <= lineno + 1;
if (lineno >= 59) begin
chrstate <= S_VSYNC;
end else begin
chrrowpos <= chrpos; // start the next row
chrstate <= S_CHR0;
end
end
end
endcase
end
//// bang pixels
reg [9:0] hcounter;
reg [9:0] vcounter;
reg ready;
wire visible;
parameter hlen = 640;
parameter hpulse = 96;
parameter hfp = 16;
parameter hbp = 48;
parameter vlen = 480;
parameter vfp = 10;
parameter vbp = 33;
parameter vpulse = 2;
parameter hlen1 = hlen + hpulse + hfp + hbp;
parameter vlen1 = vlen + vpulse + vfp + vbp;
assign hsync = ~((hcounter > hlen+hfp) & (hcounter < hlen+hfp+hpulse));
assign vsync = ~((vcounter > vlen+vfp) & (vcounter < vlen+vfp+vpulse));
assign visible = (hcounter < hlen)&&(vcounter < vlen);
always @(posedge clk25mhz)
if (!rst || !ready) begin // only start banging when there are some bits queued already
vcounter <= 0;
hcounter <= 0;
end else begin
if (hcounter >= hlen1-1) begin
hcounter <= 0;
if (vcounter >= vlen1-1)
vcounter <= 0;
else
vcounter <= vcounter + 1;
end else hcounter <= hcounter + 1;
end // else: !if(!rst)
// While in a visible area, keep sucking bits from the fifo, hoping it is being well fed
// on the other side.
reg [7:0] fontbits;
reg [7:0] fontnext;
wire nextbit;
assign nextbit = fontbits[7];
assign rgb = visible?nextbit:0;
reg [2:0] bitcount;
reg getnext;
// What a mess!!!
always @(posedge clk25mhz)
if (!rst) begin
bitcount <= 0;
fontbits <= 0;
fontnext <= 0;
ready <= 0;
fifo_rd <= 0;
getnext <= 0;
end else begin
if (!ready) begin
if (fifo_rd) begin
fifo_rd <= 0;
fontbits <= fifo_out;
ready <= 1;
bitcount <= 7;
end else fifo_rd <= 1;
end else
if (visible) begin
if (bitcount < 7) begin
bitcount <= bitcount + 1;
fontbits <= fontbits << 1;
if (fifo_rd) begin
fontnext <= fifo_out;
fifo_rd <= 0;
getnext <= 0;
end else
if ((bitcount > 4) && getnext) begin
fifo_rd <= 1;
end
end else begin // if (bitcount < 7)
fifo_rd <= 0;
bitcount <= 0;
fontbits <= fontnext;
getnext <= 1;
end
end else begin
fifo_rd <= 0; // if (visible)
fontbits <= fontnext;
end
end
endmodule
|
module fifo(input clk,
input reset,
input [31:0] data_in,
input data_in_wr,
output reg [31:0] data_out,
input data_out_en,
output reg full,
output reg empty
);
parameter DEBUG = 0;
reg [`BUF_WIDTH :0] fifo_counter;
reg [`BUF_WIDTH -1:0] rd_ptr, wr_ptr; // pointer to read and write addresses
reg [31:0] buf_mem[`BUF_SIZE -1 : 0]; //
always @(fifo_counter)
begin
empty = (fifo_counter==0);
full = (fifo_counter== `BUF_SIZE);
end
always @(posedge clk)
begin
if( !reset )
fifo_counter <= 0;
else if( (!full && data_in_wr) &&
( !empty && data_out_en ) )
fifo_counter <= fifo_counter;
else if( !full && data_in_wr )
fifo_counter <= fifo_counter + 1;
else if( !empty && data_out_en )
fifo_counter <= fifo_counter - 1;
else
fifo_counter <= fifo_counter;
end
always @( posedge clk)
begin
if( !reset )
data_out <= 0;
else
begin
if( data_out_en && !empty ) begin
if (DEBUG)
$display("FIFO OUT -> [%x]", buf_mem[rd_ptr]);
data_out <= buf_mem[rd_ptr];
end
else
data_out <= data_out;
end
end
always @(posedge clk)
begin
if( data_in_wr && !full ) begin
if(DEBUG)
$display("FIFO IN <- [%x]", data_in);
buf_mem[ wr_ptr ] <= data_in;
end
else
buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];
end
always@(posedge clk)
begin
if( !reset )
begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else
begin
if( !full && data_in_wr ) wr_ptr <= wr_ptr + 1;
else wr_ptr <= wr_ptr;
if( !empty && data_out_en ) rd_ptr <= rd_ptr + 1;
else rd_ptr <= rd_ptr;
end
end
endmodule
|
module spi_mock(
input clk100mhz,
input reset,
// UART signals
input uart_rxd,
output uart_txd,
// Input stream
input [31:0] data_in,
output reg data_in_rdy, // When ready to send data
output reg data_in_ack, // data_in was consumed
input data_in_rq, // Data send requested
// Output stream
output reg [31:0] data_out,
output reg data_out_rdy, // Word received
input data_out_ack // consumed
);
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
uart
uart_inst (
.clk(clk100mhz),
.rst(~reset),
// axi input
.input_axis_tdata(uart_tx_axis_tdata),
.input_axis_tvalid(uart_tx_axis_tvalid),
.input_axis_tready(uart_tx_axis_tready),
// axi output
.output_axis_tdata(uart_rx_axis_tdata),
.output_axis_tvalid(uart_rx_axis_tvalid),
.output_axis_tready(uart_rx_axis_tready),
// uart
.rxd(uart_rxd),
.txd(uart_txd),
// status
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
// configuration
.prescale(100000000/(115200*8))
);
reg [2:0] uart_state;
reg [31:0] uart_send_bytes;
reg [1:0] bytecount;
reg [31:0] data_out_tmp;
reg [31:0] data_in_tmp;
parameter S_RECV = 0;
parameter S_SND = 1;
parameter S_RECV_TICK = 2;
parameter S_SND_TICK = 3;
always @(posedge clk100mhz) begin
if (!reset) begin
uart_tx_axis_tdata <= 0;
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 1;
data_out_rdy <= 0;
data_out <= 0;
bytecount <= 0;
uart_state <= S_RECV;
uart_send_bytes <= 0;
data_in_ack <= 0;
data_out_tmp <= 0;
data_in_tmp <= 0;
end else begin
case(uart_state)
S_RECV: begin // wait for an input from the Master
data_in_ack <= 0;
if (bytecount == 0) begin
data_in_tmp <= data_in;
end
if (uart_rx_axis_tvalid) begin // Master has something to say
if (bytecount == 3) begin
data_out_tmp <= 0;
data_out <= {uart_rx_axis_tdata, data_out_tmp[31:8]};
data_out_rdy <= 1;
uart_state <= S_SND;
bytecount <= 0;
uart_rx_axis_tready <= 0;
uart_send_bytes <= {8'hff,data_in_tmp[31:8]};
uart_tx_axis_tdata <= data_in_tmp[7:0];
uart_tx_axis_tvalid <= 1;
end else begin
data_out_tmp <= {uart_rx_axis_tdata, data_out_tmp[31:8]}; // Shift into data output register
bytecount <= bytecount + 1;
uart_state <= S_RECV_TICK;
uart_rx_axis_tready <= 0;
end
end
end // case: S_RECV
S_RECV_TICK: begin
uart_state <= S_RECV;
uart_rx_axis_tready <= 1;
end
S_SND: begin
data_out_rdy <= 0; // enough
// if (data_out_ack) data_out_rdy <= 0; // receipt acknowledged
if (uart_tx_axis_tready) begin // just sent
bytecount <= bytecount + 1;
uart_tx_axis_tdata <= uart_send_bytes[7:0];
uart_send_bytes <= {8'hff,uart_send_bytes[31:8]};
if (bytecount == 3) begin // done sending, enough is enough
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 1;
uart_state <= S_RECV;
data_in_ack <= 1;
bytecount <= 0;
end else begin
uart_tx_axis_tvalid <= 0;
uart_state <= S_SND_TICK;
end
end
end // case: S_SND
S_SND_TICK: begin
uart_tx_axis_tvalid <= 1;
uart_state <= S_SND;
end
endcase // case (uart_state)
end // else: !if(!reset)
end // always @ (posedge clk)
endmodule
|
module spi_wrapper(
input clk,
input reset,
// SPI signals
input mosi,
input ss,
input sck,
output miso,
// Input stream
input [31:0] data_in,
output data_in_rdy, // When ready to send data
output data_in_ack, // data_in was consumed
input data_in_rq, // Data send requested
// Output stream
output reg [31:0] data_out,
output reg data_out_rdy, // Word received
input data_out_ack, // consumed
output reg spi_led
);
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], sck};
wire SCK_risingedge = (SCKr[2:1]==3'b01);
wire SCK_fallingedge = (SCKr[2:1]==2'b10);
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], ss};
wire SSEL_active = ~SSELr[1];
wire SSEL_startmessage = (SSELr[2:1]==2'b10);
wire SSEL_endmessage = (SSELr[2:1]==2'b01);
reg [1:0] MOSIr;
always @(posedge clk) MOSIr <= {MOSIr[0], mosi};
wire MOSI_data = MOSIr[1];
reg [4:0] bitcnt;
reg [3:0] bitcnt_b;
reg [31:0] word_data_received;
reg [2:0] bytecnt;
reg [4:0] started;
reg [31:0] echo;
// Receiving
always @(posedge clk)
if (!reset) begin
started <= 0;
echo <= 0;
data_out <= 0;
data_out_rdy <= 0;
bitcnt <= 0;
bytecnt <= 0;
bitcnt_b <= 0;
end else
begin
if (data_out_ack) data_out_rdy <= 0;
if(~SSEL_active) begin
spi_led <= 1;
bitcnt_b <= 0;
started <= 5'b10101;
if (started != 5'b10101) begin
bitcnt <= 0;
word_data_sent <= data_in;
end else
if (bitcnt == 5'b11111) word_data_sent <= data_in;
end else
if(SCK_risingedge)
begin
word_data_received <= {word_data_received[30:0], MOSI_data};
if(bitcnt==5'b11111) begin
data_out <= {word_data_received[30:0], MOSI_data};
data_out_rdy <= 1;
end
end else // if (SCK_risingedge)
if (SCK_fallingedge) begin
if(bitcnt==5'b11111) begin
word_data_sent <= data_in;
end else begin
spi_led <= ~spi_led;
word_data_sent <= {word_data_sent[30:0], 1'b0};
end
bitcnt <= bitcnt + 1;
bitcnt_b <= bitcnt_b + 1;
end
end // always @ (posedge clk)
always @(posedge clk)
if(SSEL_active && SCK_fallingedge && bitcnt == 0) bytecnt <= 0;
else
if(SSEL_active && SCK_fallingedge && bitcnt_b == 3'b111) bytecnt <= bytecnt + 1;
// Sending
reg [31:0] cnt;
always @(posedge clk) if(SSEL_startmessage) cnt<=cnt+1;
reg [31:0] word_data_sent;
assign data_in_rdy = bitcnt == 5'b00000; // ready to send a new word
assign data_in_ack = bitcnt == 5'b11111; // done sending
assign miso = word_data_sent[31];
endmodule // spi_wrapper
|
module idivmodhw(input clk,
input reset,
input rq,
input [31:0] dividend,
input [31:0] divisor,
output [31:0] div_out,
output [31:0] div_mod,
output ack);
reg [31:0] div_mod;
reg [31:0] div_out;
reg ack;
reg signed [31:0] ndividend;
reg signed [31:0] ndivisor;
reg signed [31:0] nq;
reg signed [31:0] nbit;
reg signed [15:0] np;
reg [3:0] state;
parameter S_IDLE = 0;
parameter S_LOOP0 = 1;
parameter S_POSTLOOP0 = 2;
parameter S_LOOP1 = 3;
parameter S_POSTLOOP1 = 4;
always @(posedge clk)
if(!reset) begin
ack <= 0;
div_out <= 0;
div_mod <= 0;
ndividend <= 0;
ndivisor <= 0;
nbit <= 0;
state <= S_IDLE;
nq <= 0;
np <= 0;
end else begin // if (!reset)
case(state)
S_IDLE: if (rq) begin
nq <= 0;
np <= 32'hffffffff;
ndividend <= dividend;
ndivisor <= divisor;
nbit <= 1;
state <= S_LOOP0;
ack <= 0;
end
S_LOOP0: if (ndivisor < ndividend) begin
ndivisor <= ndivisor << 1;
np <= np + 1;
nbit <= nbit << 1;
end else state <= S_POSTLOOP0;
S_POSTLOOP0: begin
nbit <= nbit >> 1;
ndivisor <= ndivisor >> 1;
state <= S_LOOP1;
end
S_LOOP1: if (np >= 0) begin
if (ndividend >= ndivisor) begin
nq <= nq + nbit;
ndividend <= ndividend - ndivisor;
end
ndivisor <= ndivisor >> 1;
np <= np - 1;
nbit <= nbit >> 1;
end else state <= S_POSTLOOP1;
S_POSTLOOP1: begin
if (dividend == divisor) begin
div_out <= nq + 1;
div_mod <= 0;
end else begin
div_out <= nq;
div_mod <= ndividend;
end
ack <= 1;
state <= S_IDLE;
end
endcase
end
endmodule
|
module mand_core (input clk,
input reset,
input [31:0] cx0,
input [31:0] cxstep, // will execute 11 threads
input [31:0] cy,
input rq,
output ack,
output [(7*11)-1:0] counters);
reg ack;
reg [(7*11)-1:0] counters;
/*
Since pipeline is 11-stage deep, we can issue 11 threads
one thread per cycle.
Once thread is retired, we check the output r, if it's > 16384,
thread is finalised, otherwise it is reschedulled back into
pipeline, increasing the counter.
When there are no active threads left, raise ACK and pass all the counters
as a 7*11-bit register.
*/
// control fsm
parameter S_IDLE = 0;
parameter S_ISSUE = 1;
parameter S_REISSUE = 2;
reg [2:0] state;
// pipeline input registers
reg [31:0] cx;
reg [31:0] i_vx;
reg [31:0] i_vy;
reg [31:0] i_dvx;
reg [31:0] i_dvy;
reg [6:0] i_counter;
reg [3:0] i_thrid;
wire [31:0] vx;
wire [31:0] vy;
wire [31:0] dvx;
wire [31:0] dvy;
wire [31:0] counter;
wire [31:0] thrid;
// pipeline stages registers:
reg [31:0] s00vx1;
reg [31:0] s00tmp1;
reg [31:0] s01tmp1A;
reg [31:0] s01tmp2;
reg [31:0] s01vx;
reg [31:0] s02vx;
reg [31:0] s02tmp1B;
reg [31:0] s02tmp2A;
reg [31:0] s03tmp1C;
reg [31:0] s03tmp2B;
reg [31:0] s03vx;
reg [31:0] s04tmp1D;
reg [31:0] s04tmp2C;
reg [31:0] s04vx;
reg [31:0] s05tmp2D;
reg [31:0] s05vy1;
reg [31:0] s05tmp3;
reg [31:0] s05vx;
reg [31:0] s06tmp3A;
reg [31:0] s06vx;
reg [31:0] s06vy;
reg [31:0] s06tmp2;
reg [31:0] s07tmp3B;
reg [31:0] s07vx;
reg [31:0] s07vy;
reg [31:0] s07tmp2;
reg [31:0] s08tmp3C;
reg [31:0] s08vx;
reg [31:0] s08vy;
reg [31:0] s08tmp2;
reg [31:0] s09tmp3D;
reg [31:0] s09vx;
reg [31:0] s09vy;
reg [31:0] s09tmp2;
reg [31:0] s10dvx;
reg [31:0] s10dvy;
reg [31:0] s10r;
reg [31:0] s10vx;
reg [31:0] s10vy;
// thrid and counter pipeline registers - just passing through
reg [3:0] s00thrid;
reg [3:0] s01thrid;
reg [3:0] s02thrid;
reg [3:0] s03thrid;
reg [3:0] s04thrid;
reg [3:0] s05thrid;
reg [3:0] s06thrid;
reg [3:0] s07thrid;
reg [3:0] s08thrid;
reg [3:0] s09thrid;
reg [3:0] s10thrid;
reg [6:0] s00counter;
reg [6:0] s01counter;
reg [6:0] s02counter;
reg [6:0] s03counter;
reg [6:0] s04counter;
reg [6:0] s05counter;
reg [6:0] s06counter;
reg [6:0] s07counter;
reg [6:0] s08counter;
reg [6:0] s09counter;
reg [6:0] s10counter;
// hoisted logic
wire [31:0] s05vy1_comb;
// xilinx ise does not infer a proper arithmetic shift for >>>
wire s1;
assign s1 = s04tmp1D[31];
assign s05vy1_comb = {s1,s1,s1,s1,s1,s1,s1,s1,s1,s1,s1,s04tmp1D[31:11]} + cy;
wire [31:0] s10dvx_comb;
wire [31:0] s10dvy_comb;
wire [31:0] s10r_comb;
wire s2;
assign s2 = s09tmp2[31];
assign s10dvx_comb = {s2,s2,s2,s2,s2,s2,s2,s2,s2,s2,s2,s2,s09tmp2[31:12]};
wire s3;
assign s3 = s09tmp3D[31];
assign s10dvy_comb = {s3,s3,s3,s3,s3,s3,s3,s3,s3,s3,s3,s3,s09tmp3D[31:12]};
assign s10r_comb = s10dvx_comb + s10dvy_comb;
/* reissue logic */
wire reissue;
assign reissue = (state == S_REISSUE) && (s10r < 16384) && (s10thrid !=0);
assign vx = reissue?s10vx:i_vx;
assign vy = reissue?s10vy:i_vy;
assign dvx = reissue?s10dvx:i_dvx;
assign dvy = reissue?s10dvy:i_dvy;
assign counter = reissue?s10counter+1:i_counter;
assign thrid = reissue?s10thrid:i_thrid;
always @(posedge clk)
if (!reset) begin
s00vx1 <= 0;
s00tmp1 <= 0;
s01tmp1A <= 0;
s01tmp2 <= 0;
s01vx <= 0;
s02vx <= 0;
s02tmp1B <= 0;
s02tmp2A <= 0;
s03tmp1C <= 0;
s03tmp2B <= 0;
s03vx <= 0;
s04tmp1D <= 0;
s04tmp2C <= 0;
s04vx <= 0;
s05tmp2D <= 0;
s05vy1 <= 0;
s05tmp3 <= 0;
s05vx <= 0;
s06tmp3A <= 0;
s06vx <= 0;
s06vy <= 0;
s06tmp2 <= 0;
s07tmp3B <= 0;
s07vx <= 0;
s07vy <= 0;
s07tmp2 <= 0;
s08tmp3C <= 0;
s08vx <= 0;
s08vy <= 0;
s08tmp2 <= 0;
s09tmp3D <= 0;
s09vx <= 0;
s09vy <= 0;
s09tmp2 <= 0;
s10dvx <= 0;
s10dvy <= 0;
s10r <= 0;
s10vx <= 0;
s10vy <= 0;
s00thrid <= 0;
s01thrid <= 0;
s02thrid <= 0;
s03thrid <= 0;
s04thrid <= 0;
s05thrid <= 0;
s06thrid <= 0;
s07thrid <= 0;
s08thrid <= 0;
s09thrid <= 0;
s10thrid <= 0;
s00counter <= 0;
s01counter <= 0;
s02counter <= 0;
s03counter <= 0;
s04counter <= 0;
s05counter <= 0;
s06counter <= 0;
s07counter <= 0;
s08counter <= 0;
s09counter <= 0;
s10counter <= 0;
end else begin // if (!reset)
// Flush thrid through the pipeline
s00thrid <= thrid;
s01thrid <= s00thrid;
s02thrid <= s01thrid;
s03thrid <= s02thrid;
s04thrid <= s03thrid;
s05thrid <= s04thrid;
s06thrid <= s05thrid;
s07thrid <= s06thrid;
s08thrid <= s07thrid;
s09thrid <= s08thrid;
s10thrid <= s09thrid;
s00counter <= counter;
s01counter <= s00counter;
s02counter <= s01counter;
s03counter <= s02counter;
s04counter <= s03counter;
s05counter <= s04counter;
s06counter <= s05counter;
s07counter <= s06counter;
s08counter <= s07counter;
s09counter <= s08counter;
s10counter <= s09counter;
// Stage0
// Inputs: dvx, dvy, cx, dy, vx, vy
s00vx1 <= dvx - dvy + cx;
s00tmp1 <= vx * vy;
// Stage1
s01tmp1A <= s00tmp1;
s01tmp2 <= s00vx1 * s00vx1;
s01vx <= s00vx1;
// Stage2
s02tmp1B <= s01tmp1A;
s02tmp2A <= s01tmp2;
s02vx <= s01vx;
// Stage3
s03tmp1C <= s02tmp1B;
s03tmp2B <= s02tmp2A;
s03vx <= s02vx;
// Stage4
s04tmp1D <= s03tmp1C;
s04tmp2C <= s03tmp2B;
s04vx <= s03vx;
// Stage5
s05tmp2D <= s04tmp2C;
s05vy1 <= s05vy1_comb; // (signed s04tmp1D >>> 11) + cy
s05tmp3 <= s05vy1_comb * s05vy1_comb;
s05vx <= s04vx;
// Stage6
s06tmp3A <= s05tmp3;
s06vx <= s05vx;
s06vy <= s05vy1;
s06tmp2 <= s05tmp2D;
// Stage7
s07tmp3B <= s06tmp3A;
s07vx <= s06vx;
s07vy <= s06vy;
s07tmp2 <= s06tmp2;
// Stage8
s08tmp3C <= s07tmp3B;
s08vx <= s07vx;
s08vy <= s07vy;
s08tmp2 <= s07tmp2;
// Stage9
s09tmp3D <= s08tmp3C;
s09vx <= s08vx;
s09vy <= s08vy;
s09tmp2 <= s08tmp2;
// Stage10
s10dvx <= s10dvx_comb;
s10dvy <= s10dvy_comb;
s10r <= s10r_comb;
s10vx <= s09vx;
s10vy <= s09vy;
end
// Main loop, thread management
reg [3:0] thrid1;
reg [6:0] iterations;
wire [(11*7)-1:0] counters_comb;
assign counters_comb =
{
(s10thrid==11)?s10counter:counters[(11*7)-1:10*7],
(s10thrid==10)?s10counter:counters[(10*7)-1:9*7],
(s10thrid==9)?s10counter:counters[( 9*7)-1:8*7],
(s10thrid==8)?s10counter:counters[( 8*7)-1:7*7],
(s10thrid==7)?s10counter:counters[( 7*7)-1:6*7],
(s10thrid==6)?s10counter:counters[( 6*7)-1:5*7],
(s10thrid==5)?s10counter:counters[( 5*7)-1:4*7],
(s10thrid==4)?s10counter:counters[( 4*7)-1:3*7],
(s10thrid==3)?s10counter:counters[( 3*7)-1:2*7],
(s10thrid==2)?s10counter:counters[(2*7)-1:1*7],
(s10thrid==1)?s10counter:counters[(1*7)-1:0]};
reg [4:0] reissues;
always @(posedge clk)
if (!reset) begin
state <= S_IDLE;
i_thrid <= 0;
i_dvx <= 0;
i_dvy <= 0;
i_vx <= 0;
i_vy <= 0;
counters <= 0;
iterations <= 0;
thrid1 <= 0;
ack <= 0;
cx <= 0;
reissues <= 0;
end else begin
counters <= counters_comb;
case(state)
S_IDLE: if (rq) begin
state <= S_ISSUE;
i_thrid <= 1;
cx <= cx0;
i_dvx <= 0;
i_dvy <= 0;
i_vx <= 0;
i_vy <= 0;
counters <= 0;
iterations <= 0;
ack <= 0;
reissues <= 0;
end else ack <= 0; // if (rq)
S_ISSUE: begin
i_thrid <= i_thrid + 1;
cx <= cx + cxstep;
if (i_thrid == 11) begin
cx <= cx0;
state <= S_REISSUE;
i_thrid <= 0;
i_counter <= 0;
thrid1 <= 1;
end
end
S_REISSUE: begin
if (thrid1 == 11) begin
cx <= cx0;
thrid1 <= 1;
reissues <= 0;
if (iterations == 100 || reissues == 0) begin
state <= S_IDLE;
ack <= 1;
end else begin
iterations <= iterations + 1;
end
end else begin
cx <= cx + cxstep;
thrid1 <= thrid1 + 1;
reissues <= reissues + reissue?1:0;
end
end
endcase
end
endmodule
|
module IKAOPM #(parameter FULLY_SYNCHRONOUS = 1, parameter FAST_RESET = 0,
parameter USE_BRAM = 0) (
//chip clock
input wire i_EMUCLK, //emulator master clock
//clock endables
input wire i_phiM_PCEN_n, //phiM positive edge clock enable(negative logic)
`ifdef IKAOPM_USER_DEFINED_CLOCK_ENABLES
input wire i_phi1_PCEN_n, //phi1 positive edge clock enable(negative logic)
input wire i_phi1_NCEN_n, //phi1 negative edge clock enable(negative logic)
`endif
//chip reset
input wire i_IC_n,
//phi1
output wire o_phi1,
//bus control and address
input wire i_CS_n,
input wire i_RD_n,
input wire i_WR_n,
input wire i_A0,
//bus data
input wire [7:0] i_D,
output wire [7:0] o_D,
//output driver enable
output wire o_D_OE,
//ct
output wire o_CT2, //BIT7 of register 0x1B, pin 8
output wire o_CT1, //BIT6 of register 0x1B, pin 9
//interrupt
output wire o_IRQ_n,
//sh
output wire o_SH1,
output wire o_SH2,
//output
output wire o_SO,
output wire o_EMU_R_SAMPLE, o_EMU_L_SAMPLE,
output wire signed [15:0] o_EMU_R_EX, o_EMU_L_EX,
output wire signed [15:0] o_EMU_R, o_EMU_L
`ifdef IKAOPM_BUSY_FLAG_ENABLE
, output wire o_EMU_BUSY_FLAG
`endif
);
///////////////////////////////////////////////////////////
////// Clock enable information
////
/*
EMUCLK ¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|
phiM _______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|
phi1 ¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|________
You should provide 3 enables when `IKAOPM_USER_DEFINED_CLOCK_ENABLES is defined
phiM_PCEN ¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯
phi1_NCEN ¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯
phi1_PCEN ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
*/
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1pcen_n, phi1ncen_n;
wire mrst_n;
///////////////////////////////////////////////////////////
////// Interconnects
////
//timings
wire cycle_31, cycle_01; //to REG
wire cycle_12_28, cycle_05_21, cycle_byte; //to LFO
wire cycle_05, cycle_10; //to PG
wire cycle_03, cycle_00_16, cycle_01_to_16; //to EG
wire cycle_04_12_20_28; //to OP(algorithm state counter)
wire cycle_29, cycle_06_22; //to ACC
wire cycle_12, cycle_15_31; //to NOISE
//NOISE
wire [4:0] nfrq;
wire lfo_noise;
wire noise_attenlevel;
//LFO
wire [7:0] lfrq;
wire [6:0] pmd, amd;
wire [1:0] w;
wire lfrq_update;
wire [7:0] lfa, lfp;
//PG
wire [6:0] kc;
wire [5:0] kf;
wire [2:0] pms;
wire [1:0] dt2;
wire [2:0] dt1;
wire [3:0] mul;
wire [4:0] pdelta_shamt;
wire phase_rst;
//EG
wire kon;
wire [1:0] ks;
wire [4:0] ar;
wire [4:0] d1r;
wire [4:0] d2r;
wire [3:0] rr;
wire [3:0] d1l;
wire [6:0] tl;
wire [1:0] ams;
//OP
wire [9:0] op_attenlevel, op_phasedata;
wire [2:0] alg, fl;
//ACC
wire ne;
wire [1:0] rl;
wire acc_snd_add;
wire [13:0] acc_noise;
wire [13:0] acc_opdata;
//TIMER
wire [7:0] clka1, clkb;
wire [1:0] clka2;
wire [5:0] timerctrl;
wire timera_flag, timerb_flag, timera_ovfl;
//TEST
wire [7:0] test;
wire reg_phase_ch6_c2, reg_attenlevel_ch8_c2, reg_lfo_clk;
//write busy flag(especially for an external asynchronous fifo)
`ifdef IKAOPM_BUSY_FLAG_ENABLE
assign o_EMU_BUSY_FLAG = o_D[7];
`endif
///////////////////////////////////////////////////////////
////// Modules
////
IKAOPM_timinggen #(
.FULLY_SYNCHRONOUS (FULLY_SYNCHRONOUS ),
.FAST_RESET (FAST_RESET )
) TIMINGGEN (
.i_EMUCLK (i_EMUCLK ),
.i_IC_n (i_IC_n ),
.o_MRST_n (mrst_n ),
.i_phiM_PCEN_n (i_phiM_PCEN_n ),
`ifdef IKAOPM_USER_DEFINED_CLOCK_ENABLES
.i_phi1_PCEN_n (i_phi1_PCEN_n ),
.i_phi1_NCEN_n (i_phi1_NCEN_n ),
`endif
.o_phi1 (o_phi1 ),
.o_phi1_PCEN_n (phi1pcen_n ),
.o_phi1_NCEN_n (phi1ncen_n ),
.o_SH1 (o_SH1 ),
.o_SH2 (o_SH2 ),
.o_CYCLE_01 (cycle_01 ),
.o_CYCLE_31 (cycle_31 ),
.o_CYCLE_12_28 (cycle_12_28 ),
.o_CYCLE_05_21 (cycle_05_21 ),
.o_CYCLE_BYTE (cycle_byte ),
.o_CYCLE_05 (cycle_05 ),
.o_CYCLE_10 (cycle_10 ),
.o_CYCLE_03 (cycle_03 ),
.o_CYCLE_00_16 (cycle_00_16 ),
.o_CYCLE_01_TO_16 (cycle_01_to_16 ),
.o_CYCLE_04_12_20_28 (cycle_04_12_20_28 ),
.o_CYCLE_12 (cycle_12 ),
.o_CYCLE_15_31 (cycle_15_31 ),
.o_CYCLE_29 (cycle_29 ),
.o_CYCLE_06_22 (cycle_06_22 )
);
IKAOPM_reg #(
.USE_BRAM_FOR_D32REG (USE_BRAM ),
.FULLY_SYNCHRONOUS (FULLY_SYNCHRONOUS )
) REG (
.i_EMUCLK (i_EMUCLK ),
.i_MRST_n (mrst_n ),
.i_phi1_PCEN_n (phi1pcen_n ),
.i_phi1_NCEN_n (phi1ncen_n ),
.i_CYCLE_01 (cycle_01 ),
.i_CYCLE_31 (cycle_31 ),
.i_CS_n (i_CS_n ),
.i_RD_n (i_RD_n ),
.i_WR_n (i_WR_n ),
.i_A0 (i_A0 ),
.i_D (i_D ),
.o_D (o_D ),
.o_D_OE (o_D_OE ),
.i_TIMERA_OVFL (timera_ovfl ),
.i_TIMERA_FLAG (timera_flag ),
.i_TIMERB_FLAG (timerb_flag ),
.o_TEST (test ),
.o_CT1 (o_CT1 ),
.o_CT2 (o_CT2 ),
.o_NE (ne ),
.o_NFRQ (nfrq ),
.o_CLKA1 (clka1 ),
.o_CLKA2 (clka2 ),
.o_CLKB (clkb ),
.o_TIMERA_RUN (timerctrl[0] ),
.o_TIMERB_RUN (timerctrl[1] ),
.o_TIMERA_IRQ_EN (timerctrl[2] ),
.o_TIMERB_IRQ_EN (timerctrl[3] ),
.o_TIMERA_FRST (timerctrl[4] ),
.o_TIMERB_FRST (timerctrl[5] ),
.o_LFRQ (lfrq ),
.o_PMD (pmd ),
.o_AMD (amd ),
.o_W (w ),
.o_LFRQ_UPDATE (lfrq_update ),
.o_KC (kc ),
.o_KF (kf ),
.o_PMS (pms ),
.o_DT2 (dt2 ),
.o_DT1 (dt1 ),
.o_MUL (mul ),
.o_KON (kon ),
.o_KS (ks ),
.o_AR (ar ),
.o_D1R (d1r ),
.o_D2R (d2r ),
.o_RR (rr ),
.o_D1L (d1l ),
.o_TL (tl ),
.o_AMS (ams ),
.o_ALG (alg ),
.o_FL (fl ),
.o_RL (rl ),
.i_REG_LFO_CLK (reg_lfo_clk ),
.i_REG_PHASE_CH6_C2 (reg_phase_ch6_c2 ),
.i_REG_ATTENLEVEL_CH8_C2 (reg_attenlevel_ch8_c2 ),
.i_REG_OPDATA (acc_opdata )
);
IKAOPM_noise NOISE (
.i_EMUCLK (i_EMUCLK ),
.i_MRST_n (mrst_n ),
.i_phi1_PCEN_n (phi1pcen_n ),
.i_phi1_NCEN_n (phi1ncen_n ),
.i_CYCLE_12 (cycle_12 ),
.i_CYCLE_15_31 (cycle_15_31 ),
.i_NFRQ (nfrq ),
.i_NOISE_ATTENLEVEL (noise_attenlevel ),
.o_ACC_NOISE (acc_noise ),
.o_LFO_NOISE (lfo_noise )
);
IKAOPM_lfo LFO (
.i_EMUCLK (i_EMUCLK ),
.i_MRST_n (mrst_n ),
.i_phi1_PCEN_n (phi1pcen_n ),
.i_phi1_NCEN_n (phi1ncen_n ),
.i_CYCLE_12_28 (cycle_12_28 ),
.i_CYCLE_05_21 (cycle_05_21 ),
.i_CYCLE_BYTE (cycle_byte ),
.i_LFRQ (lfrq ),
.i_PMD (pmd ),
.i_AMD (amd ),
.i_W (w ),
.i_TEST_D1 (test[1] ),
.i_TEST_D2 (test[2] ),
.i_TEST_D3 (test[3] ),
.i_LFRQ_UPDATE (lfrq_update ),
.i_LFO_NOISE (lfo_noise ),
.o_LFA (lfa ),
.o_LFP (lfp ),
.o_REG_LFO_CLK (reg_lfo_clk )
);
IKAOPM_pg #(
.USE_BRAM_FOR_PHASEREG (USE_BRAM )
) PG (
.i_EMUCLK (i_EMUCLK ),
.i_MRST_n (mrst_n ),
.i_phi1_PCEN_n (phi1pcen_n ),
.i_phi1_NCEN_n (phi1ncen_n ),
.i_CYCLE_05 (cycle_05 ),
.i_CYCLE_10 (cycle_10 ),
.i_KC (kc ),
.i_KF (kf ),
.i_PMS (pms ),
.i_DT2 (dt2 ),
.i_DT1 (dt1 ),
.i_MUL (mul ),
.i_TEST_D3 (test[3] ),
.i_LFP (lfp ),
.i_PG_PHASE_RST (phase_rst ),
.o_EG_PDELTA_SHIFT_AMOUNT (pdelta_shamt ),
.o_OP_PHASEDATA (op_phasedata ),
.o_REG_PHASE_CH6_C2 (reg_phase_ch6_c2 )
);
IKAOPM_eg EG (
.i_EMUCLK (i_EMUCLK ),
.i_MRST_n (mrst_n ),
.i_phi1_PCEN_n (phi1pcen_n ),
.i_phi1_NCEN_n (phi1ncen_n ),
.i_CYCLE_03 (cycle_03 ),
.i_CYCLE_31 (cycle_31 ),
.i_CYCLE_00_16 (cycle_00_16 ),
.i_CYCLE_01_TO_16 (cycle_01_to_16 ),
.i_KON (kon ),
.i_KS (ks ),
.i_AR (ar ),
.i_D1R (d1r ),
.i_D2R (d2r ),
.i_RR (rr ),
.i_D1L (d1l ),
.i_TL (tl ),
.i_AMS (ams ),
.i_LFA (lfa ),
.i_TEST_D0 (test[0] ),
.i_TEST_D5 (test[5] ),
.i_EG_PDELTA_SHIFT_AMOUNT (pdelta_shamt ),
.o_PG_PHASE_RST (phase_rst ),
.o_OP_ATTENLEVEL (op_attenlevel ),
.o_NOISE_ATTENLEVEL (noise_attenlevel ),
.o_REG_ATTENLEVEL_CH8_C2 (reg_attenlevel_ch8_c2 )
);
IKAOPM_op OP (
.i_EMUCLK (i_EMUCLK ),
.i_MRST_n (mrst_n ),
.i_phi1_PCEN_n (phi1pcen_n ),
.i_phi1_NCEN_n (phi1ncen_n ),
.i_CYCLE_03 (cycle_03 ),
.i_CYCLE_12 (cycle_12 ),
.i_CYCLE_04_12_20_28 (cycle_04_12_20_28 ),
.i_ALG (alg ),
.i_FL (fl ),
.i_TEST_D4 (test[4] ),
.i_OP_PHASEDATA (op_phasedata ),
.i_OP_ATTENLEVEL (op_attenlevel ),
.o_ACC_SNDADD (acc_snd_add ),
.o_ACC_OPDATA (acc_opdata )
);
IKAOPM_acc ACC (
.i_EMUCLK (i_EMUCLK ),
.i_MRST_n (mrst_n ),
.i_phi1_PCEN_n (phi1pcen_n ),
.i_phi1_NCEN_n (phi1ncen_n ),
.i_CYCLE_12 (cycle_12 ),
.i_CYCLE_29 (cycle_29 ),
.i_CYCLE_00_16 (cycle_00_16 ),
.i_CYCLE_06_22 (cycle_06_22 ),
.i_CYCLE_01_TO_16 (cycle_01_to_16 ),
.i_NE (ne ),
.i_RL (rl ),
.i_ACC_SNDADD (acc_snd_add ),
.i_ACC_OPDATA (acc_opdata ),
.i_ACC_NOISE (acc_noise ),
.o_SO (o_SO ),
.o_EMU_R_SAMPLE (o_EMU_R_SAMPLE ),
.o_EMU_R_EX (o_EMU_R_EX ),
.o_EMU_R (o_EMU_R ),
.o_EMU_L_SAMPLE (o_EMU_L_SAMPLE ),
.o_EMU_L_EX (o_EMU_L_EX ),
.o_EMU_L (o_EMU_L )
);
IKAOPM_timer TIMER (
.i_EMUCLK (i_EMUCLK ),
.i_MRST_n (mrst_n ),
.i_phi1_PCEN_n (phi1pcen_n ),
.i_phi1_NCEN_n (phi1ncen_n ),
.i_CYCLE_31 (cycle_31 ),
.i_CLKA1 (clka1 ),
.i_CLKA2 (clka2 ),
.i_CLKB (clkb ),
.i_TIMERA_RUN (timerctrl[0] ),
.i_TIMERB_RUN (timerctrl[1] ),
.i_TIMERA_IRQ_EN (timerctrl[2] ),
.i_TIMERB_IRQ_EN (timerctrl[3] ),
.i_TIMERA_FRST (timerctrl[4] ),
.i_TIMERB_FRST (timerctrl[5] ),
.i_TEST_D2 (test[2] ),
.o_TIMERA_OVFL (timera_ovfl ),
.o_TIMERA_FLAG (timera_flag ),
.o_TIMERB_FLAG (timerb_flag ),
.o_IRQ_n (o_IRQ_n )
);
endmodule
|
module IKAOPM_timer (
//master clock
input wire i_EMUCLK, //emulator master clock
//core internal reset
input wire i_MRST_n,
//internal clock
input wire i_phi1_PCEN_n, //positive edge clock enable for emulation
input wire i_phi1_NCEN_n, //negative edge clock enable for emulation
//timings
input wire i_CYCLE_31,
//control input
input wire [7:0] i_CLKA1,
input wire [1:0] i_CLKA2,
input wire [7:0] i_CLKB,
input wire i_TIMERA_RUN,
input wire i_TIMERB_RUN,
input wire i_TIMERA_IRQ_EN,
input wire i_TIMERB_IRQ_EN,
input wire i_TIMERA_FRST,
input wire i_TIMERB_FRST,
input wire i_TEST_D2, //test register
//timer output
output wire o_TIMERA_OVFL,
output reg o_TIMERA_FLAG,
output reg o_TIMERB_FLAG,
output reg o_IRQ_n
);
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1pcen_n = i_phi1_PCEN_n;
wire phi1ncen_n = i_phi1_NCEN_n;
wire mrst_n = i_MRST_n;
///////////////////////////////////////////////////////////
////// Timer A
////
reg timera_cnt, timera_ld, timera_rst, timera_ovfl_z;
wire timera_ovfl;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
timera_cnt <= (i_CYCLE_31 & i_TIMERA_RUN) | i_TEST_D2;
timera_ld <= (i_TIMERA_RUN & timera_rst) | timera_ovfl_z; //run reg postive edge detector
timera_rst <= ~i_TIMERA_RUN;
timera_ovfl_z <= timera_ovfl;
end
primitive_counter #(.WIDTH(10)) u_timera (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(timera_cnt), .i_LD(timera_ld), .i_RST(~mrst_n | timera_rst),
.i_D({i_CLKA1, i_CLKA2}), .o_Q(), .o_CO(timera_ovfl)
);
assign o_TIMERA_OVFL = timera_ld; //for CSM
///////////////////////////////////////////////////////////
////// Timer B
////
//Prescaler
reg timerb_prescaler_cnt, timerb_prescaler_ovfl_z;
wire timerb_prescaler_ovfl;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
timerb_prescaler_ovfl_z <= timerb_prescaler_ovfl; //save carry
timerb_prescaler_cnt <= i_CYCLE_31;
end
primitive_counter #(.WIDTH(4)) u_timerb_prescaler (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(timerb_prescaler_cnt), .i_LD(1'b0), .i_RST(~mrst_n),
.i_D(4'd0), .o_Q(), .o_CO(timerb_prescaler_ovfl)
);
//Timer B
reg timerb_cnt, timerb_ld, timerb_rst, timerb_ovfl_z;
wire timerb_ovfl;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
timerb_cnt <= (timerb_prescaler_ovfl_z & i_TIMERB_RUN) | i_TEST_D2;
timerb_ld <= (i_TIMERB_RUN & timerb_rst) | timerb_ovfl_z; //run reg postive edge detector
timerb_rst <= ~i_TIMERB_RUN;
timerb_ovfl_z <= timerb_ovfl;
end
primitive_counter #(.WIDTH(8)) u_timerb (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(timerb_cnt), .i_LD(timerb_ld), .i_RST(~mrst_n | timerb_rst),
.i_D(i_CLKB), .o_Q(), .o_CO(timerb_ovfl)
);
///////////////////////////////////////////////////////////
////// Flag and IRQ generator
////
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(~mrst_n || i_TIMERA_FRST) begin
o_TIMERA_FLAG <= 1'b0;
end
else begin
if(i_TIMERA_IRQ_EN) o_TIMERA_FLAG <= timera_ovfl_z | o_TIMERA_FLAG;
else o_TIMERA_FLAG <= 1'b0;
end
if(~mrst_n || i_TIMERB_FRST) begin
o_TIMERB_FLAG <= 1'b0;
end
else begin
if(i_TIMERB_IRQ_EN) o_TIMERB_FLAG <= timerb_ovfl_z | o_TIMERB_FLAG;
else o_TIMERB_FLAG <= 1'b0;
end
o_IRQ_n <= ~(o_TIMERA_FLAG | o_TIMERB_FLAG);
end
endmodule
|
module IKAOPM_op (
//master clock
input wire i_EMUCLK, //emulator master clock
//core internal reset
input wire i_MRST_n,
//internal clock
input wire i_phi1_PCEN_n, //positive edge clock enable for emulation
input wire i_phi1_NCEN_n, //negative edge clock enable for emulation
//timings
input wire i_CYCLE_03,
input wire i_CYCLE_12,
input wire i_CYCLE_04_12_20_28,
input wire [2:0] i_ALG,
input wire [2:0] i_FL,
input wire i_TEST_D4, //test register
input wire [9:0] i_OP_PHASEDATA,
input wire [9:0] i_OP_ATTENLEVEL,
output wire o_ACC_SNDADD,
output wire [13:0] o_ACC_OPDATA
);
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1pcen_n = i_phi1_PCEN_n;
wire phi1ncen_n = i_phi1_NCEN_n;
wire mrst_n = i_MRST_n;
///////////////////////////////////////////////////////////
////// Algorithm state counter
////
wire [1:0] algst_cntr;
primitive_counter #(.WIDTH(2)) u_op_algst_cntr (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(i_CYCLE_04_12_20_28), .i_LD(1'b0), .i_RST(i_CYCLE_12 | ~mrst_n),
.i_D(2'd0), .o_Q(algst_cntr), .o_CO()
);
///////////////////////////////////////////////////////////
////// Cycle 41: Phase modulation
////
//
// combinational part
//
reg [9:0] cyc56r_phasemod_value; //get value from the end of the pipeline
wire [10:0] cyc41c_modded_phase_adder = !mrst_n ? 10'd0 : i_OP_PHASEDATA + cyc56r_phasemod_value;
//
// register part
//
reg [7:0] cyc41r_logsinrom_phase;
reg cyc41r_level_fp_sign;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc41r_logsinrom_phase <= cyc41c_modded_phase_adder[8] ? cyc41c_modded_phase_adder[7:0] :
~cyc41c_modded_phase_adder[7:0];
cyc41r_level_fp_sign <= cyc41c_modded_phase_adder[9]; //discard carry
end
///////////////////////////////////////////////////////////
////// Cycle 42: Get data from Sin ROM
////
//
// register part
//
wire [45:0] cyc42r_logsinrom_out;
op_submdl_logsinrom u_cyc42r_logsinrom (
.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_ADDR(cyc41r_logsinrom_phase[5:1]), .o_DATA(cyc42r_logsinrom_out)
);
reg cyc42r_logsinrom_phase_odd;
reg [1:0] cyc42r_logsinrom_bitsel;
reg cyc42r_level_fp_sign;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc42r_logsinrom_phase_odd <= cyc41r_logsinrom_phase[0];
cyc42r_logsinrom_bitsel <= cyc41r_logsinrom_phase[7:6];
cyc42r_level_fp_sign <= cyc41r_level_fp_sign;
end
///////////////////////////////////////////////////////////
////// Cycle 43: Choose bits from Sin ROM and add them
////
//
// combinational part
//
wire [45:0] ls = cyc42r_logsinrom_out; //alias signal
wire odd = cyc42r_logsinrom_phase_odd; //alias signal
reg [10:0] cyc43c_logsinrom_addend0, cyc43c_logsinrom_addend1;
always @(*) begin
case(cyc42r_logsinrom_bitsel)
/* D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc43c_logsinrom_addend0 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[29], ls[25], ls[18], ls[14], ls[3]};
2'd1: cyc43c_logsinrom_addend0 = { 1'b0, 1'b0, 1'b0, 1'b0, ls[37], ls[34], ls[28], ls[24], ls[17], ls[13], ls[2]};
2'd2: cyc43c_logsinrom_addend0 = { 1'b0, 1'b0, ls[43], ls[41], ls[36], ls[33], ls[27], ls[23], ls[16], ls[12], ls[1]};
2'd3: cyc43c_logsinrom_addend0 = {ls[45], ls[44], ls[42], ls[40], ls[35], ls[32], ls[26], ls[22], ls[15], ls[11], ls[0]};
endcase
case(cyc42r_logsinrom_bitsel)
/* D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc43c_logsinrom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[7]} & {2'b00, {9{odd}}};
2'd1: cyc43c_logsinrom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[10], ls[6]} & {2'b00, {9{odd}}};
2'd2: cyc43c_logsinrom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[20], ls[9], ls[5]} & {2'b00, {9{odd}}};
2'd3: cyc43c_logsinrom_addend1 = { 1'b0, 1'b0, ls[39], ls[39], ls[38], ls[31], ls[30], ls[21], ls[19], ls[8], ls[4]} & {2'b00, {9{odd}}};
endcase
end
//
// register part
//
reg [11:0] cyc43r_logsin_raw;
reg cyc43r_level_fp_sign;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc43r_logsin_raw <= cyc43c_logsinrom_addend0 + cyc43c_logsinrom_addend1;
cyc43r_level_fp_sign <= cyc42r_level_fp_sign;
end
///////////////////////////////////////////////////////////
////// Cycle 44: Apply attenuation level
////
//
// register part
//
reg [12:0] cyc44r_logsin_attenuated;
reg cyc44r_level_fp_sign;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc44r_logsin_attenuated <= cyc43r_logsin_raw + {i_OP_ATTENLEVEL, 2'b00};
cyc44r_level_fp_sign <= cyc43r_level_fp_sign;
end
///////////////////////////////////////////////////////////
////// Cycle 45: Saturation
////
//
// register part
//
reg [11:0] cyc45r_logsin_saturated;
reg cyc45r_level_fp_sign;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc45r_logsin_saturated <= cyc44r_logsin_attenuated[12] ? 12'd4095 : cyc44r_logsin_attenuated[11:0]; //discard carry
cyc45r_level_fp_sign <= cyc44r_level_fp_sign;
end
///////////////////////////////////////////////////////////
////// Cycle 46: Get data from exp ROM
////
//
// register part
//
wire [44:0] cyc46r_exprom_out;
op_submdl_exprom u_cyc46r_exprom (
.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_ADDR(cyc45r_logsin_saturated[5:1]), .o_DATA(cyc46r_exprom_out)
);
reg cyc46r_logsin_even;
reg [1:0] cyc46r_exprom_bitsel;
reg [3:0] cyc46r_level_fp_exp;
reg cyc46r_level_fp_sign;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc46r_logsin_even <= ~cyc45r_logsin_saturated[0]; //inverted!! EVEN flag!!
cyc46r_exprom_bitsel <= cyc45r_logsin_saturated[7:6];
cyc46r_level_fp_exp <= ~cyc45r_logsin_saturated[11:8]; //invert
cyc46r_level_fp_sign <= cyc45r_level_fp_sign;
end
///////////////////////////////////////////////////////////
////// Cycle 47: Choose bits from exp ROM and add them
////
//
// combinational part
//
wire [44:0] e = cyc46r_exprom_out; //alias signal
wire even = cyc46r_logsin_even; //alias signal
reg [9:0] cyc47c_exprom_addend0, cyc47c_exprom_addend1;
always @(*) begin
case(cyc46r_exprom_bitsel)
/* D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc47c_exprom_addend0 = { 1'b1, e[43], e[40], e[36], e[32], e[28], e[24], e[18], e[14], e[3]};
2'd1: cyc47c_exprom_addend0 = { e[44], e[42], e[39], e[35], e[31], e[27], e[23], e[17], e[13], e[2]};
2'd2: cyc47c_exprom_addend0 = { 1'b0, e[41], e[38], e[34], e[30], e[26], e[22], e[16], e[12], e[1]};
2'd3: cyc47c_exprom_addend0 = { 1'b0, 1'b0, e[37], e[33], e[29], e[25], e[21], e[15], e[11], e[0]};
endcase
case(cyc46r_exprom_bitsel)
/* D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc47c_exprom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, e[10], e[7]} & {7'b0000000, {3{even}}};
2'd1: cyc47c_exprom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, e[6]} & {7'b0000000, {3{even}}};
2'd2: cyc47c_exprom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, e[19], e[9], e[5]} & {7'b0000000, {3{even}}};
2'd3: cyc47c_exprom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, e[20], e[8], e[4]} & {7'b0000000, {3{even}}};
endcase
end
//
// register part
//
reg [9:0] cyc47r_level_fp_mant;
reg [3:0] cyc47r_level_fp_exp;
reg cyc47r_level_fp_sign;
reg cyc47r_level_negate;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc47r_level_fp_mant <= cyc47c_exprom_addend0 + cyc47c_exprom_addend1; //discard carry
cyc47r_level_fp_exp <= cyc46r_level_fp_exp;
cyc47r_level_fp_sign <= cyc46r_level_fp_sign;
cyc47r_level_negate <= i_TEST_D4;
end
///////////////////////////////////////////////////////////
////// Cycle 48: Floating point to integer
////
//
// combinational part
//
reg [12:0] cyc48c_shifter0, cyc48c_shifter1;
always @(*) begin
case(cyc47r_level_fp_exp[1:0])
2'b00: cyc48c_shifter0 = {3'b000, 1'b1, cyc47r_level_fp_mant[9:1]};
2'b01: cyc48c_shifter0 = {2'b00, 1'b1, cyc47r_level_fp_mant };
2'b10: cyc48c_shifter0 = {1'b0, 1'b1, cyc47r_level_fp_mant, 1'b0 };
2'b11: cyc48c_shifter0 = { 1'b1, cyc47r_level_fp_mant, 2'b00 };
endcase
case(cyc47r_level_fp_exp[3:2])
2'b00: cyc48c_shifter1 = {12'b0, cyc48c_shifter0[12] };
2'b01: cyc48c_shifter1 = { 8'b0, cyc48c_shifter0[12:8]};
2'b10: cyc48c_shifter1 = { 4'b0, cyc48c_shifter0[12:4]};
2'b11: cyc48c_shifter1 = cyc48c_shifter0;
endcase
end
//
// register part
//
reg cyc48r_level_negate;
reg cyc48r_level_sign;
reg [12:0] cyc48r_level_magnitude;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc48r_level_negate <= cyc47r_level_negate;
cyc48r_level_sign <= cyc47r_level_fp_sign;
cyc48r_level_magnitude <= cyc48c_shifter1;
end
///////////////////////////////////////////////////////////
////// Cycle 49: sign-magnitude to signed integer
////
//
// register part
//
reg [13:0] cyc49r_level_signed;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc49r_level_signed <= cyc48r_level_sign ? (~{cyc48r_level_negate, cyc48r_level_magnitude} + 14'd1) :
{cyc48r_level_negate, cyc48r_level_magnitude};
end
///////////////////////////////////////////////////////////
////// Cycle 50: delay
////
//
// register part
//
reg [13:0] cyc50r_level_signed;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc50r_level_signed <= cyc49r_level_signed;
end
///////////////////////////////////////////////////////////
////// Cycle 51: delay
////
//
// register part
//
reg [13:0] cyc51r_level_signed;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc51r_level_signed <= cyc50r_level_signed;
end
///////////////////////////////////////////////////////////
////// Cycle 52: delay / latch algorithm type and state
////
//
// register part
//
reg [1:0] cyc52r_algst;
reg [2:0] cyc52r_algtype;
reg [13:0] cyc52r_level_signed;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc52r_algst <= algst_cntr; //algorithm state counter
cyc52r_algtype <= i_ALG; //algorithm type
cyc52r_level_signed <= cyc51r_level_signed;
end
///////////////////////////////////////////////////////////
////// Cycle 53: delay / Z reg / algorithm decoder
////
//
// combinational part
//
assign o_ACC_OPDATA = cyc52r_level_signed; //OP data output
reg cyc53c_accumulation_en;
assign o_ACC_SNDADD = cyc53c_accumulation_en;
always @(*) begin
case(cyc52r_algst)
2'd0: cyc53c_accumulation_en = cyc52r_algtype == 3'd7; //Add M1?
2'd1: cyc53c_accumulation_en = cyc52r_algtype == 3'd7 || cyc52r_algtype == 3'd6 || cyc52r_algtype == 3'd5; //Add M2?
2'd2: cyc53c_accumulation_en = cyc52r_algtype == 3'd7 || cyc52r_algtype == 3'd6 || cyc52r_algtype == 3'd5 || cyc52r_algtype == 3'd4; //Add C1?
2'd3: cyc53c_accumulation_en = 1'b1; //Add C2?
endcase
end
//
// register part
//
//signed sound level
reg [1:0] cyc53r_algst;
reg [2:0] cyc53r_algtype;
reg [13:0] cyc53r_OP_current;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc53r_algst <= cyc52r_algst;
cyc53r_algtype <= cyc52r_algtype;
cyc53r_OP_current <= cyc52r_level_signed;
end
//Z registers that hold previous values
reg cyc53r_M1_z_ld, cyc53r_M1_zz_ld; //store THIS M1 value, store PREVIOUS M1 value again
reg cyc53r_C1_z_ld; //store THIS C1 value
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc53r_M1_z_ld <= cyc52r_algst == 2'd0;
cyc53r_M1_zz_ld <= cyc52r_algst == 2'd0;
cyc53r_C1_z_ld <= cyc52r_algst == 2'd2;
end
wire [13:0] cyc53r_M1_z_reg_out, cyc53r_M1_zz_reg_out, cyc53r_C1_z_reg_out;
wire [13:0] cyc46c_M1_z_reg_in = !mrst_n ? 14'd0 :
cyc53r_M1_z_ld ? cyc53r_OP_current: cyc53r_M1_z_reg_out;
wire [13:0] cyc46c_M1_zz_reg_in = !mrst_n ? 14'd0 :
cyc53r_M1_zz_ld ? cyc53r_M1_z_reg_out : cyc53r_M1_zz_reg_out;
wire [13:0] cyc46c_C1_z_reg_in = !mrst_n ? 14'd0 :
cyc53r_C1_z_ld ? cyc53r_OP_current : cyc53r_C1_z_reg_out;
//stores THIS M1
primitive_sr #(.WIDTH(14), .LENGTH(8), .TAP(8)) u_cyc46r_cyc53r_M1_z
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(cyc46c_M1_z_reg_in), .o_Q_TAP(), .o_Q_LAST(cyc53r_M1_z_reg_out));
//stores PREVIOUS M1 again, this will be used for M1 self feedback calculation
primitive_sr #(.WIDTH(14), .LENGTH(8), .TAP(8)) u_cyc46r_cyc53r_M1_zz
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(cyc46c_M1_zz_reg_in), .o_Q_TAP(), .o_Q_LAST(cyc53r_M1_zz_reg_out));
//stores THIS C1
primitive_sr #(.WIDTH(14), .LENGTH(8), .TAP(8)) u_cyc46r_cyc53r_C1_z
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(cyc46c_C1_z_reg_in), .o_Q_TAP(), .o_Q_LAST(cyc53r_C1_z_reg_out));
//misc control bits
reg cyc53r_self_fdbk_en;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc53r_self_fdbk_en <= cyc52r_algst == 2'd2;
end
///////////////////////////////////////////////////////////
////// Cycle 54: select addend 0 and 1
////
//
// register part
//
//make alias signals
wire [13:0] M1 = cyc53r_OP_current;
wire [13:0] M2 = cyc53r_OP_current;
wire [13:0] M1_z = cyc53r_M1_z_reg_out;
wire [13:0] M1_zz = cyc53r_M1_zz_reg_out;
wire [13:0] C1_z = cyc53r_C1_z_reg_out;
//selector
reg [13:0] cyc54r_op_addend0, cyc54r_op_addend1;
reg cyc54r_self_fdbk_en;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
case({cyc53r_algtype, cyc53r_algst})
//Algorithm 0
5'b000_10: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= M1_zz; end //state 2
5'b000_11: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= C1_z ; end //state 3
5'b000_00: begin cyc54r_op_addend0 <= M1 ; cyc54r_op_addend1 <= 14'd0; end //state 0
5'b000_01: begin cyc54r_op_addend0 <= M2 ; cyc54r_op_addend1 <= 14'd0; end //state 1
//Algorithm 1
5'b001_10: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= M1_zz; end //state 2
5'b001_11: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= C1_z ; end //state 3
5'b001_00: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= 14'd0; end //state 0
5'b001_01: begin cyc54r_op_addend0 <= M2 ; cyc54r_op_addend1 <= 14'd0; end //state 1
//Algorithm 2
5'b010_10: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= M1_zz; end //state 2
5'b010_11: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= C1_z ; end //state 3
5'b010_00: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= 14'd0; end //state 0
5'b010_01: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= M2 ; end //state 1
//Algorithm 3
5'b011_10: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= M1_zz; end //state 2
5'b011_11: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= 14'd0; end //state 3
5'b011_00: begin cyc54r_op_addend0 <= M1 ; cyc54r_op_addend1 <= 14'd0; end //state 0
5'b011_01: begin cyc54r_op_addend0 <= M2 ; cyc54r_op_addend1 <= C1_z ; end //state 1
//Algorithm 4
5'b100_10: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= M1_zz; end //state 2
5'b100_11: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= 14'd0; end //state 3
5'b100_00: begin cyc54r_op_addend0 <= M1 ; cyc54r_op_addend1 <= 14'd0; end //state 0
5'b100_01: begin cyc54r_op_addend0 <= M2 ; cyc54r_op_addend1 <= 14'd0; end //state 1
//Algorithm 5
5'b101_10: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= M1_zz; end //state 2
5'b101_11: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= 14'd0; end //state 3
5'b101_00: begin cyc54r_op_addend0 <= M1 ; cyc54r_op_addend1 <= 14'd0; end //state 0
5'b101_01: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= 14'd0; end //state 1
//Algorithm 6
5'b110_10: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= M1_zz; end //state 2
5'b110_11: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= 14'd0; end //state 3
5'b110_00: begin cyc54r_op_addend0 <= M1 ; cyc54r_op_addend1 <= 14'd0; end //state 0
5'b110_01: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= 14'd0; end //state 1
//Algorithm 7
5'b111_10: begin cyc54r_op_addend0 <= M1_z ; cyc54r_op_addend1 <= M1_zz; end //state 2
5'b111_11: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= 14'd0; end //state 3
5'b111_00: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= 14'd0; end //state 0
5'b111_01: begin cyc54r_op_addend0 <= 14'd0; cyc54r_op_addend1 <= 14'd0; end //state 1
endcase
cyc54r_self_fdbk_en <= cyc53r_self_fdbk_en;
end
///////////////////////////////////////////////////////////
////// Cycle 55: sum two operator outputs
////
//
// register part
//
reg cyc55r_self_fdbk_en;
reg [2:0] cyc55r_fl;
reg [14:0] cyc55r_op_sum;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc55r_self_fdbk_en <= cyc54r_self_fdbk_en;
cyc55r_fl <= cyc54r_self_fdbk_en ? i_FL : 3'd0;
cyc55r_op_sum <= {cyc54r_op_addend0[13], cyc54r_op_addend0} + {cyc54r_op_addend1[13], cyc54r_op_addend1}; //add with sign extension, carry discarded
end
///////////////////////////////////////////////////////////
////// Cycle 56: phase modulation value
////
//
// register part
//
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(cyc55r_self_fdbk_en) begin
case(cyc55r_fl)
3'd0: cyc56r_phasemod_value <= 10'd0;
3'd1: cyc56r_phasemod_value <= {{4{cyc55r_op_sum[14]}}, cyc55r_op_sum[14:9]};
3'd2: cyc56r_phasemod_value <= {{3{cyc55r_op_sum[14]}}, cyc55r_op_sum[14:8]};
3'd3: cyc56r_phasemod_value <= {{2{cyc55r_op_sum[14]}}, cyc55r_op_sum[14:7]};
3'd4: cyc56r_phasemod_value <= {{1{cyc55r_op_sum[14]}}, cyc55r_op_sum[14:6]};
3'd5: cyc56r_phasemod_value <= cyc55r_op_sum[14:5];
3'd6: cyc56r_phasemod_value <= cyc55r_op_sum[13:4];
3'd7: cyc56r_phasemod_value <= cyc55r_op_sum[12:3];
endcase
end
else cyc56r_phasemod_value <= cyc55r_op_sum[10:1];
end
endmodule
|
module op_submdl_logsinrom (
//master clock
input wire i_EMUCLK, //emulator master clock
//clock enable
input wire i_CEN_n, //positive edge clock enable for emulation
input wire [4:0] i_ADDR,
output reg [45:0] o_DATA
);
always @(posedge i_EMUCLK) if(!i_CEN_n) begin
case(i_ADDR)
5'd0 : o_DATA <= 46'b000110000010010001000100_0010101010101001010010;
5'd1 : o_DATA <= 46'b000110000011010000010000_0010010001001101000001;
5'd2 : o_DATA <= 46'b000110000011010000010011_0010001011001101100000;
5'd3 : o_DATA <= 46'b000111000001000000000011_0010110001001101110010;
5'd4 : o_DATA <= 46'b000111000001000000110000_0010111010001101101001;
5'd5 : o_DATA <= 46'b000111000001010000100110_0010000000101101111010;
5'd6 : o_DATA <= 46'b000111000001010000110110_0010010011001101011010;
5'd7 : o_DATA <= 46'b000111000001110000010101_0010111000101111111100;
5'd8 : o_DATA <= 46'b000111000011100000000111_0010101110001101110111;
5'd9 : o_DATA <= 46'b000111000011100001010011_1000011101011010100110;
5'd10: o_DATA <= 46'b000111000011110001100001_1000111100001001111010;
5'd11: o_DATA <= 46'b000111000011110001110011_1001101011001001110111;
5'd12: o_DATA <= 46'b010010000101000001000101_1001001000111010110111;
5'd13: o_DATA <= 46'b010010000101010001000100_1001110001111100101010;
5'd14: o_DATA <= 46'b010010000101010001010110_1101111110100101000110;
5'd15: o_DATA <= 46'b010010001110000000100001_1001010110101101111001;
5'd16: o_DATA <= 46'b010010001110010000100010_1011100101001011101111;
5'd17: o_DATA <= 46'b010010001110110000011101_1010000001011010110001;
5'd18: o_DATA <= 46'b010011001100100000011110_1010000010111010111111;
5'd19: o_DATA <= 46'b010011001100110000101101_1110101110110110000001;
5'd20: o_DATA <= 46'b010011001110100001101011_1011001010001101110001;
5'd21: o_DATA <= 46'b010011001110110101101011_0101111001010100001111;
5'd22: o_DATA <= 46'b011100001000000101011100_0101010101010110010111;
5'd23: o_DATA <= 46'b011100001000010101011111_0111110101010010111011;
5'd24: o_DATA <= 46'b011100001011010110100010_1100001000010000011001;
5'd25: o_DATA <= 46'b011101001001100110010001_1110100100010010010010;
5'd26: o_DATA <= 46'b011101001011101010010110_0101000000110100100011;
5'd27: o_DATA <= 46'b101000001001101010110101_1101100001110010011010;
5'd28: o_DATA <= 46'b101000001011111111110010_0111010100010000111001;
5'd29: o_DATA <= 46'b101001011111010011001000_1100111001010110100000;
5'd30: o_DATA <= 46'b101101011101001111101101_1110000100110010100001;
5'd31: o_DATA <= 46'b111001101111000111101110_0111100001110110100111;
endcase
end
endmodule
|
module op_submdl_exprom (
//master clock
input wire i_EMUCLK, //emulator master clock
//clock enable
input wire i_CEN_n, //positive edge clock enable for emulation
input wire [4:0] i_ADDR,
output reg [44:0] o_DATA
);
always @(posedge i_EMUCLK) if(!i_CEN_n) begin
case(i_ADDR)
5'd0 : o_DATA <= 45'b110111111000111111010001_011000000100110011101;
5'd1 : o_DATA <= 45'b110111111000110100111110_000001100001110110011;
5'd2 : o_DATA <= 45'b110111111000000111101101_011101110100111011010;
5'd3 : o_DATA <= 45'b110111111000000111000011_011100000010101010110;
5'd4 : o_DATA <= 45'b110111111000000100001100_010100000010101011011;
5'd5 : o_DATA <= 45'b110111010010101010111011_011000111100111011101;
5'd6 : o_DATA <= 45'b110110010110111011110100_111001011000011000000;
5'd7 : o_DATA <= 45'b110110010110111001001011_010001001100111011110;
5'd8 : o_DATA <= 45'b110110010110011010001101_011000101000111011010;
5'd9 : o_DATA <= 45'b110110010110000011100110_011110010100111010100;
5'd10: o_DATA <= 45'b110110000111000101111001_010110110100110010101;
5'd11: o_DATA <= 45'b110100001111100110011110_011111110000110011011;
5'd12: o_DATA <= 45'b110100001111100110000001_001111001101110111101;
5'd13: o_DATA <= 45'b110100001001111101101111_010110101010101010001;
5'd14: o_DATA <= 45'b110100001001111101100000_010110001100110010011;
5'd15: o_DATA <= 45'b110100001001011010110101_011001110000111010101;
5'd16: o_DATA <= 45'b110100001001011000011010_001001010101110110111;
5'd17: o_DATA <= 45'b110100001001001001010100_000000111001110110001;
5'd18: o_DATA <= 45'b110100000001100011101011_000000011101110110011;
5'd19: o_DATA <= 45'b110100000001100000101100_001011100001111110101;
5'd20: o_DATA <= 45'b110100000000100100010011_011011000100110010101;
5'd21: o_DATA <= 45'b011101000100010111011101_000010101001110110101;
5'd22: o_DATA <= 45'b011001100110011111110010_000010001101111110011;
5'd23: o_DATA <= 45'b011001100110011100100111_001001100001110110001;
5'd24: o_DATA <= 45'b001011101110111110101001_001000000001110101010;
5'd25: o_DATA <= 45'b001011101110101111000110_000000101101110111000;
5'd26: o_DATA <= 45'b001011101110101001011001_010001001000110011010;
5'd27: o_DATA <= 45'b001011101110100000110110_010011000100110010000;
5'd28: o_DATA <= 45'b001011101110000010110000_001010101001110110001;
5'd29: o_DATA <= 45'b001011101010010001001111_001010001101110111011;
5'd30: o_DATA <= 45'b001011101010010001000010_011001000100100000000;
5'd31: o_DATA <= 45'b001011100010110010001100_000000101001110110000;
endcase
end
endmodule
|
module IKAOPM_lfo (
//master clock
input wire i_EMUCLK, //emulator master clock
//core internal reset
input wire i_MRST_n,
//internal clock
input wire i_phi1_PCEN_n, //positive edge clock enable for emulation
input wire i_phi1_NCEN_n, //negative edge clock enable for emulation
//timings
input wire i_CYCLE_12_28,
input wire i_CYCLE_05_21,
input wire i_CYCLE_BYTE,
//register data
input wire [7:0] i_LFRQ, //LFO frequency
input wire [6:0] i_AMD, //amplitude modulation depth
input wire [6:0] i_PMD, //phase modulation depth
input wire [1:0] i_W, //waveform select
input wire i_TEST_D1, //test register
input wire i_TEST_D2,
input wire i_TEST_D3,
//control signal
input wire i_LFRQ_UPDATE,
//noise
input wire i_LFO_NOISE,
output wire [7:0] o_LFP,
output wire [7:0] o_LFA,
output wire o_REG_LFO_CLK
);
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1pcen_n = i_phi1_PCEN_n;
wire phi1ncen_n = i_phi1_NCEN_n;
wire mrst_n = i_MRST_n;
///////////////////////////////////////////////////////////
////// Cycle number
////
//additional cycle bits
reg cycle_06_22, cycle_13_29, cycle_14_30, cycle_15_31;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cycle_06_22 <= i_CYCLE_05_21;
cycle_13_29 <= i_CYCLE_12_28;
cycle_14_30 <= cycle_13_29;
cycle_15_31 <= cycle_14_30;
end
`ifdef IKAOPM_DEBUG
reg debug_cycle_07_23;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
debug_cycle_07_23 <= cycle_06_22;
end
`endif
///////////////////////////////////////////////////////////
////// Prescaler
////
//counter
wire [3:0] prescaler_value;
wire prescaler_cout;
primitive_counter #(.WIDTH(4)) u_lfo_prescaler (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(i_CYCLE_12_28), .i_LD(1'b0), .i_RST(~mrst_n),
.i_D(4'd0), .o_Q(prescaler_value), .o_CO(prescaler_cout)
);
//cycle 2 / cout_z
reg prescaler_cycle_2, prescaler_cout_z;
always @(posedge i_EMUCLK) begin
if(!phi1ncen_n) prescaler_cycle_2 <= prescaler_value == 4'd2;
if(!phi1ncen_n) prescaler_cout_z <= prescaler_cout;
end
///////////////////////////////////////////////////////////
////// LFO LUT and output latch
////
/*
pre-initialized LFO LUT. The bit order of the original chip is:
(LEFT) D1 - D7 / D14 - D8 (RIGHT)
D0 is controlled by row F enable signal, so the table below contains the precalculated values
lfo dout latch:
the original one uses different edges due to carry delay of the counter cells
so the counter for MSBs is delayed by a half phi1.
*/
reg [14:0] lfolut_dout;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
case(i_LFRQ[7:4])
4'hF: lfolut_dout <= 15'h7FFF;
4'hE: lfolut_dout <= 15'h7FFE;
4'hD: lfolut_dout <= 15'h7FFC;
4'hC: lfolut_dout <= 15'h7FF8;
4'hB: lfolut_dout <= 15'h7FF0;
4'hA: lfolut_dout <= 15'h7FE0;
4'h9: lfolut_dout <= 15'h7FC0;
4'h8: lfolut_dout <= 15'h7F80;
4'h7: lfolut_dout <= 15'h7F00;
4'h6: lfolut_dout <= 15'h7E00;
4'h5: lfolut_dout <= 15'h7C00;
4'h4: lfolut_dout <= 15'h7800;
4'h3: lfolut_dout <= 15'h7000;
4'h2: lfolut_dout <= 15'h6000;
4'h1: lfolut_dout <= 15'h4000;
4'h0: lfolut_dout <= 15'h1000;
endcase
end
///////////////////////////////////////////////////////////
////// LFRQ counter low bits
////
//locntr cnt up signal
reg locntr_cnt;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
locntr_cnt <= prescaler_cout_z | i_TEST_D3; //de morgan
end
//locntr preload signal
wire locntr_cout;
reg locntr_cout_z, freq_update;
reg locntr_ld;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
locntr_cout_z <= locntr_cout;
freq_update <= i_LFRQ_UPDATE;
locntr_ld <= (locntr_cout_z | freq_update);
end
//define locntr
primitive_counter #(.WIDTH(15)) u_lfo_locntr (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(locntr_cnt), .i_LD(locntr_ld), .i_RST(~mrst_n),
.i_D(lfolut_dout), .o_Q(), .o_CO(locntr_cout)
);
///////////////////////////////////////////////////////////
////// LFRQ counter high bits
////
//hicntr cout delay
reg locntr_cout_step1, locntr_cout_step2;
always @(posedge i_EMUCLK) begin
if(!phi1pcen_n) if(cycle_15_31) locntr_cout_step1 <= locntr_cout_z;
if(!phi1pcen_n) if(i_CYCLE_05_21) locntr_cout_step2 <= locntr_cout_step1; //use positive edge
end
//hicntr cnt up and output decoder enable
reg hicntr_cnt;
wire hicntr_decode_en = (cycle_13_29 & locntr_cout_step2); //de morgan
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
hicntr_cnt <= hicntr_decode_en;
end
//counter
wire [3:0] hicntr_value;
primitive_counter #(.WIDTH(4)) u_lfo_hicntr (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(hicntr_cnt), .i_LD(1'b0), .i_RST(~mrst_n),
.i_D(4'd0), .o_Q(hicntr_value), .o_CO()
);
//hicntr complete flag
reg hicntr_complete; //use positive edge
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(hicntr_decode_en) begin //decode locntr value only when decode_en == 1
casez(hicntr_value)
4'b???0: hicntr_complete <= i_LFRQ[3];
4'b??01: hicntr_complete <= i_LFRQ[2];
4'b?011: hicntr_complete <= i_LFRQ[1];
4'b0111: hicntr_complete <= i_LFRQ[0];
default: hicntr_complete <= 1'b0;
endcase
end
else hicntr_complete <= 1'b0; //disable
end
///////////////////////////////////////////////////////////
////// LFO clock generation
////
reg lfo_clk;
assign o_REG_LFO_CLK = lfo_clk;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
lfo_clk <= |{locntr_cout, hicntr_complete, i_TEST_D2};
end
///////////////////////////////////////////////////////////
////// latched LFO clock
////
//The original one used dynamic D-latch to latch lfo_clk
//I reused the signal above to eliminate a latch.
reg lfo_clk_latched = 1'b0; //dynamic d latch
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(cycle_14_30) lfo_clk_latched <= |{locntr_cout, hicntr_complete, i_TEST_D2};
end
///////////////////////////////////////////////////////////
////// waveform decoder
////
reg [1:0] wfsel;
wire wfsel_noise = (wfsel == 2'd3);
wire wfsel_tri = (wfsel == 2'd2);
//wire wfsel_sq = (wfsel == 2'd1);
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
wfsel <= i_W;
end
///////////////////////////////////////////////////////////
////// LFO phase accumulator
////
//test bit 1 latch
reg tst_bit1_latched;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
tst_bit1_latched <= i_TEST_D1;
end
//phase accumulator
reg [15:0] phase_acc; //phase accumulator shift register
wire phase_acc_lsb = phase_acc[0];
//full adder
wire [1:0] phase_acc_fa;
reg phase_acc_fa_prev_carry = 1'b0;
always @(posedge i_EMUCLK or negedge mrst_n) begin //async reset
if(!mrst_n) phase_acc_fa_prev_carry <= 1'b0;
else begin
if(!phi1ncen_n) phase_acc_fa_prev_carry <= phase_acc_fa[1]; //store previous carry(serial full adder)
end
end
//tri = enable / square, saw, noise = disable
wire phase_acc_fa_a = &{cycle_15_31, lfo_clk, ~wfsel_noise} &
wfsel_tri;
//tri, square, saw = enable / noise = temporarily disable
wire phase_acc_fa_b = mrst_n &
~tst_bit1_latched &
phase_acc_lsb &
~(lfo_clk_latched & wfsel_noise);
//tri, square, saw = enable / noise = disable
wire phase_acc_fa_cin = ~(|{cycle_15_31, ~phase_acc_fa_prev_carry, wfsel_noise} &
~&{cycle_15_31, lfo_clk, ~wfsel_noise});
assign phase_acc_fa = phase_acc_fa_a + phase_acc_fa_b + phase_acc_fa_cin;
//noise input
reg noise_input_z, noise_stream;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
noise_input_z <= i_LFO_NOISE;
noise_stream <= lfo_clk_latched & noise_input_z; //de morgan
end
//phase accumulator input
wire phase_acc_input = phase_acc_fa[0] | (wfsel_noise & noise_stream);
//shift accumulator
always @(posedge i_EMUCLK or negedge mrst_n) begin //async reset
if(!mrst_n) phase_acc <= 16'h0;
else begin
if(!phi1ncen_n) begin
phase_acc[15] <= phase_acc_input;
phase_acc[14:0] <= phase_acc[15:1];
end
end
end
//for debug
`ifdef IKAOPM_DEBUG
reg [15:0] debug_phase_acc;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(cycle_15_31) debug_phase_acc <= phase_acc;
end
`endif
///////////////////////////////////////////////////////////
////// Bit select counter for base value multiply
////
//define counter
wire [3:0] multiplier_bitselcntr_value;
primitive_counter #(.WIDTH(4)) u_lfo_multiplier_bitselcntr (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(cycle_14_30), .i_LD(1'b0), .i_RST(prescaler_cycle_2 & i_CYCLE_12_28),
.i_D(4'd0), .o_Q(multiplier_bitselcntr_value), .o_CO()
);
//this counter output value selects AMD/PMD bit
reg [2:0] multiplier_bitsel;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
multiplier_bitsel <= multiplier_bitselcntr_value[2:0]; //store value at negative edge
end
//timings/control
wire a_np_sel = ~multiplier_bitselcntr_value[3]; //AMD/PMD mux select
wire multiplier_bitselcntr_cycle_0_8 = multiplier_bitselcntr_value == 4'd0 | multiplier_bitselcntr_value == 4'd8;
wire multiplier_bitsel_0 = multiplier_bitsel == 3'd0;
wire multiplier_bitsel_7 = multiplier_bitsel == 3'd7;
///////////////////////////////////////////////////////////
////// Sigh bit latch
////
//triangle/sawtooth sign bit latch
/*
phi1 |_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯
|----(14_30)----|----(15_31)----|----(0_16)----|
d valid <--------------> <-------------> <------------->
0_8 ________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
latchen ________________|¯¯¯¯¯¯¯|_______________________
dff ^ <-- sample here
*/
reg wf_tri_sign, wf_saw_sign;
always @(posedge i_EMUCLK) if(!phi1pcen_n) begin
if(cycle_15_31 & multiplier_bitselcntr_cycle_0_8) begin
wf_tri_sign <= phase_acc[8];
wf_saw_sign <= phase_acc[7];
end
end
///////////////////////////////////////////////////////////
////// Oscillator base value generator
////
//amd/pmd select latch
reg a_np_sel_latched;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
a_np_sel_latched <= a_np_sel;
end
//base value stream, behavioral implementation
// waveform type ( AM ) : ( PM )
wire noise_value_stream = a_np_sel_latched ? phase_acc_fa_b ^ 1'b1 : (phase_acc_fa_b ^ wf_saw_sign);
wire tri_value_stream = a_np_sel_latched ? phase_acc_fa_b ^ ~wf_tri_sign : (phase_acc_fa_b ^ wf_saw_sign);
wire sq_value_stream = a_np_sel_latched ? ~wf_saw_sign : cycle_06_22 ;
wire saw_value_stream = a_np_sel_latched ? phase_acc_fa_b ^ 1'b1 : (phase_acc_fa_b ^ wf_saw_sign);
//input selector
reg base_value_input;
always @(*) begin
if(i_CYCLE_BYTE) begin
case(wfsel)
2'd3: base_value_input = noise_value_stream;
2'd2: base_value_input = tri_value_stream; //gawr gura
2'd1: base_value_input = sq_value_stream;
2'd0: base_value_input = saw_value_stream;
endcase
end
else base_value_input = 1'b0;
end
//base value shift register
reg [6:0] base_value_sr;
always @(posedge i_EMUCLK or negedge mrst_n) begin
if(!mrst_n) base_value_sr <= 7'h00;
else begin
if(!phi1ncen_n) begin
base_value_sr[6] <= base_value_input;
base_value_sr[5:0] <= base_value_sr[6:1];
end
end
end
//debug
`ifdef IKAOPM_DEBUG
reg [6:0] debug_base_value_am, debug_base_value_pm;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(debug_cycle_07_23) begin
if(a_np_sel_latched) debug_base_value_am <= base_value_sr;
else debug_base_value_pm <= base_value_sr;
end
end
`endif
///////////////////////////////////////////////////////////
////// Volume multiplier
////
/*
TAP
MSB 6 5 4 3 2 1 0 LSB
Base value shift register 0 1 1 0 1 0 1
Volume register(AMD/PMD) 1 0 0 1 1 0 0
1. pick volume_reg[6] and do AND with the base value[6:0], add serially, from the LSB
-> 0110101
2. pick volume reg[5] and do AND with the base value {1'b0, value[6:1]}, add serially, from the LSB
-> 0000000
3. pick volume reg[4] and do AND with the base value {2'b00, value[6:2]}, add serially, from the LSB
-> 0000000
...repeat for all bits of AMD/PMD
now the process above can be expressed like below
0110101
0000000
0000000
0000110
0000011
0000000
0000000 +
= 0111110 ====> this is the final value calculated
Volume format X.XXXXXX fixed point.
AMD/PMD bit 6 is decimal part, and bit 5 to 0 is fractional part. Step width 0.015625.
*/
//AMD/PMD mux
reg [6:0] ap_muxed;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
ap_muxed <= a_np_sel ? i_AMD : i_PMD;
end
//bit selector
reg multiplier_fa_b;
always @(*) begin
case(multiplier_bitsel)
3'b000: multiplier_fa_b = base_value_sr[0] & ap_muxed[6];
3'b001: multiplier_fa_b = base_value_sr[1] & ap_muxed[5];
3'b010: multiplier_fa_b = base_value_sr[2] & ap_muxed[4];
3'b011: multiplier_fa_b = base_value_sr[3] & ap_muxed[3];
3'b100: multiplier_fa_b = base_value_sr[4] & ap_muxed[2];
3'b101: multiplier_fa_b = base_value_sr[5] & ap_muxed[1];
3'b110: multiplier_fa_b = base_value_sr[6] & ap_muxed[0];
3'b111: multiplier_fa_b = 1'b0;
endcase
end
//multiplier
wire [1:0] multiplier_fa;
reg [15:0] multiplier_sr = 16'h0;
always @(posedge i_EMUCLK or negedge mrst_n) begin
if(!mrst_n) multiplier_sr <= 16'h0; //reset
else begin
if(!phi1ncen_n) begin
multiplier_sr[15] <= multiplier_fa[0];
multiplier_sr[14:0] <= multiplier_sr[15:1];
end
end
end
reg multiplier_prev_carry = 1'b0;
always @(posedge i_EMUCLK or negedge mrst_n) begin
if(!mrst_n) multiplier_prev_carry <= 1'b0; //reset
else begin
if(!phi1ncen_n) multiplier_prev_carry <= multiplier_fa[1];
end
end
wire multiplier_fa_a = ~(~multiplier_sr[0] | multiplier_bitsel_0);
wire multiplier_fa_cin = multiplier_prev_carry & ~cycle_15_31;
assign multiplier_fa = multiplier_fa_a + multiplier_fa_b + multiplier_fa_cin;
///////////////////////////////////////////////////////////
////// LFA/LFP latch
////
//LFA LFP register load
wire lfa_reg_ld = &{cycle_15_31, multiplier_bitsel_7, a_np_sel};
wire lfp_reg_ld = &{cycle_15_31, multiplier_bitsel_7, ~a_np_sel};
//LFA LFP register
reg [7:0] lfa_reg, lfp_reg;
assign o_LFA = lfa_reg;
assign o_LFP = lfp_reg;
//LFP sign/value control
wire pmd_zero = i_PMD == 7'h00;
wire lfp_sign_ctrl = wfsel_tri ? wf_tri_sign : wf_saw_sign; //AOI
//note that LFA is 8-bit unsigned, LFP is 8-bit sign(1 = negative) and magnitude output
always @(posedge i_EMUCLK) begin
//negative edge
if(!phi1ncen_n) begin
if(!mrst_n) lfa_reg <= 8'd0;
else begin
if(lfa_reg_ld) lfa_reg <= multiplier_sr[15:8];
end
end
//positive edge
if(!phi1pcen_n) begin
if(!mrst_n) lfp_reg <= 8'd0;
else begin
if(lfp_reg_ld) lfp_reg <= (pmd_zero == 1'b1) ? 8'h00 : {~(multiplier_sr[15] ^ ~lfp_sign_ctrl), multiplier_sr[14:8]};
end
end
end
//lfp debug(2's complement)
`ifdef IKAOPM_DEBUG
reg [7:0] debug_lfp_reg_pitchmod, debug_lfa_reg_attenlevel;
always @(posedge i_EMUCLK) begin
if(!phi1ncen_n)
if(lfa_reg_ld) begin
debug_lfa_reg_attenlevel <= multiplier_sr[15:8];
end
if(!phi1pcen_n) begin
if(lfp_reg_ld)
debug_lfp_reg_pitchmod <= (pmd_zero == 1'b1) ? 8'h80 :
(~(multiplier_sr[15] ^ ~lfp_sign_ctrl) == 1'b1) ? (~multiplier_sr[14:8] + 7'h1) : multiplier_sr[14:8];
end
end
`endif
endmodule
|
module IKAOPM_acc (
//master clock
input wire i_EMUCLK, //emulator master clock
//core internal reset
input wire i_MRST_n,
//internal clock
input wire i_phi1_PCEN_n, //positive edge clock enable for emulation
input wire i_phi1_NCEN_n, //engative edge clock enable for emulation
//timings
input wire i_CYCLE_12,
input wire i_CYCLE_29,
input wire i_CYCLE_00_16,
input wire i_CYCLE_06_22,
input wire i_CYCLE_01_TO_16,
//data
input wire i_NE,
input wire [1:0] i_RL,
input wire i_ACC_SNDADD,
input wire [13:0] i_ACC_OPDATA,
input wire [13:0] i_ACC_NOISE,
output reg o_SO,
output reg o_EMU_R_SAMPLE, o_EMU_L_SAMPLE,
output reg signed [15:0] o_EMU_R_EX, o_EMU_L_EX,
output reg signed [15:0] o_EMU_R, o_EMU_L
);
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1ncen_n = i_phi1_NCEN_n;
wire mrst_n = i_MRST_n;
///////////////////////////////////////////////////////////
////// Cycle number
////
//additional cycle bits
reg cycle_13, cycle_01_17, cycle_02_to_17;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cycle_13 <= i_CYCLE_12;
cycle_01_17 <= i_CYCLE_00_16;
cycle_02_to_17 <= i_CYCLE_01_TO_16;
end
///////////////////////////////////////////////////////////
////// Sound input MUX / RL acc enable
////
//noise data will be launched at master cycle 12
reg [13:0] sound_inlatch;
reg r_add, l_add;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
sound_inlatch <= (i_NE & i_CYCLE_12) ? i_ACC_NOISE : i_ACC_OPDATA;
r_add <= i_ACC_SNDADD & i_RL[1];
l_add <= i_ACC_SNDADD & i_RL[0];
end
///////////////////////////////////////////////////////////
////// R/L channel accmulators
////
reg [17:0] r_accumulator, l_accumulator;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(!mrst_n) begin
r_accumulator <= 18'd0; //original chip doesn't have this reset
l_accumulator <= 18'd0;
end
else begin
if(cycle_13) r_accumulator <= r_add ? {{4{sound_inlatch[13]}}, sound_inlatch} : 17'd0; //reset
else r_accumulator <= r_add ? {{4{sound_inlatch[13]}}, sound_inlatch} + r_accumulator : r_accumulator; //accumulation
if(i_CYCLE_29) l_accumulator <= l_add ? {{4{sound_inlatch[13]}}, sound_inlatch} : 17'd0; //reset
else l_accumulator <= l_add ? {{4{sound_inlatch[13]}}, sound_inlatch} + l_accumulator : l_accumulator; //accumulation
end
end
///////////////////////////////////////////////////////////
////// R/L PISO register
////
/*
Sign bit is inverted in this stage.
11111...(positive max)
10000...(positive min)
01111...(negative min)
00000...(negative max)
*/
reg [15:0] mcyc14_r_piso, mcyc30_l_piso;
reg [2:0] mcyc14_r_saturation_ctrl, mcyc30_l_saturation_ctrl;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(cycle_13) begin
mcyc14_r_piso <= {~r_accumulator[17], r_accumulator[14:0]}; //FLIP THE SIGN BIT!!
mcyc14_r_saturation_ctrl <= r_accumulator[17:15];
end
else begin
mcyc14_r_piso[14:0] <= mcyc14_r_piso[15:1]; //shift
end
if(i_CYCLE_29) begin
mcyc30_l_piso <= {~l_accumulator[17], l_accumulator[14:0]}; //FLIP THE SIGN BIT!!
mcyc30_l_saturation_ctrl <= l_accumulator[17:15];
end
else begin
mcyc30_l_piso[14:0] <= mcyc30_l_piso[15:1]; //shift
end
end
///////////////////////////////////////////////////////////
////// Parallel output control
////
localparam SAMPLE_STROBE_LENGTH = 1; //adjust this value to stretch the strobe width
reg [SAMPLE_STROBE_LENGTH+1:0] r_sample_det, l_sample_det;
always @(posedge i_EMUCLK) begin
if(!i_MRST_n) begin
r_sample_det[0] <= 1'b0;
l_sample_det[0] <= 1'b0;
end
else begin
r_sample_det[0] <= cycle_13;
l_sample_det[0] <= i_CYCLE_29;
end
r_sample_det[SAMPLE_STROBE_LENGTH+1:1] <= r_sample_det[SAMPLE_STROBE_LENGTH:0];
l_sample_det[SAMPLE_STROBE_LENGTH+1:1] <= l_sample_det[SAMPLE_STROBE_LENGTH:0];
//negative edge detector + pulse stretcher
o_EMU_R_SAMPLE <= {|{r_sample_det[SAMPLE_STROBE_LENGTH+1:2]}, r_sample_det[1]} == 2'b10;
o_EMU_L_SAMPLE <= {|{l_sample_det[SAMPLE_STROBE_LENGTH+1:2]}, l_sample_det[1]} == 2'b10;
end
reg signed [15:0] r_parallel, l_parallel, r_parallel_extended, l_parallel_extended; //parallel output intermediate storage
reg [2:0] r_parallel_saturation_ctrl, l_parallel_saturation_ctrl; //parallel output saturation control
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(!i_MRST_n) begin
r_parallel_saturation_ctrl <= 3'b000;
r_parallel_extended <= 16'sd0;
r_parallel <= 16'sd0;
l_parallel_saturation_ctrl <= 3'b000;
l_parallel_extended <= 16'sd0;
l_parallel <= 16'sd0;
end
else begin
if(cycle_13) begin
r_parallel_saturation_ctrl <= r_accumulator[17:15];
r_parallel_extended <= {r_accumulator[17], r_accumulator[14:0]}; //extended output, sign bit + least important 15 bits
casez(r_accumulator[14:9] ^ {6{r_accumulator[17]}})
6'b000000: r_parallel <= {r_accumulator[17], r_accumulator[14:6], r_accumulator[5:0]}; //small number
6'b000001: r_parallel <= {r_accumulator[17], r_accumulator[14:6], r_accumulator[17] ? r_accumulator[5:0] | 6'b000001 : r_accumulator[5:0] & 6'b111110};
6'b00001?: r_parallel <= {r_accumulator[17], r_accumulator[14:6], r_accumulator[17] ? r_accumulator[5:0] | 6'b000011 : r_accumulator[5:0] & 6'b111100};
6'b0001??: r_parallel <= {r_accumulator[17], r_accumulator[14:6], r_accumulator[17] ? r_accumulator[5:0] | 6'b000111 : r_accumulator[5:0] & 6'b111000};
6'b001???: r_parallel <= {r_accumulator[17], r_accumulator[14:6], r_accumulator[17] ? r_accumulator[5:0] | 6'b001111 : r_accumulator[5:0] & 6'b110000};
6'b01????: r_parallel <= {r_accumulator[17], r_accumulator[14:6], r_accumulator[17] ? r_accumulator[5:0] | 6'b011111 : r_accumulator[5:0] & 6'b100000};
6'b1?????: r_parallel <= {r_accumulator[17], r_accumulator[14:6], r_accumulator[17] ? r_accumulator[5:0] | 6'b111111 : r_accumulator[5:0] & 6'b000000}; //large number
default: r_parallel <= {r_accumulator[17], r_accumulator[14:6], r_accumulator[5:0]};
endcase
end
if(i_CYCLE_29) begin
l_parallel_saturation_ctrl <= l_accumulator[17:15];
l_parallel_extended <= {l_accumulator[17], l_accumulator[14:0]}; //extended output, sign bit + least important 15 bits
casez(l_accumulator[14:9] ^ {6{l_accumulator[17]}})
6'b000000: l_parallel <= {l_accumulator[17], l_accumulator[14:6], l_accumulator[5:0]}; //small number
6'b000001: l_parallel <= {l_accumulator[17], l_accumulator[14:6], l_accumulator[17] ? l_accumulator[5:0] | 6'b000001 : l_accumulator[5:0] & 6'b111110};
6'b00001?: l_parallel <= {l_accumulator[17], l_accumulator[14:6], l_accumulator[17] ? l_accumulator[5:0] | 6'b000011 : l_accumulator[5:0] & 6'b111100};
6'b0001??: l_parallel <= {l_accumulator[17], l_accumulator[14:6], l_accumulator[17] ? l_accumulator[5:0] | 6'b000111 : l_accumulator[5:0] & 6'b111000};
6'b001???: l_parallel <= {l_accumulator[17], l_accumulator[14:6], l_accumulator[17] ? l_accumulator[5:0] | 6'b001111 : l_accumulator[5:0] & 6'b110000};
6'b01????: l_parallel <= {l_accumulator[17], l_accumulator[14:6], l_accumulator[17] ? l_accumulator[5:0] | 6'b011111 : l_accumulator[5:0] & 6'b100000};
6'b1?????: l_parallel <= {l_accumulator[17], l_accumulator[14:6], l_accumulator[17] ? l_accumulator[5:0] | 6'b111111 : l_accumulator[5:0] & 6'b000000}; //large number
default: l_parallel <= {l_accumulator[17], l_accumulator[14:6], l_accumulator[5:0]};
endcase
end
end
end
always @(posedge i_EMUCLK) begin
if(!i_MRST_n) begin
o_EMU_R <= 16'sd0;
o_EMU_R_EX <= 16'sd0;
o_EMU_L <= 16'sd0;
o_EMU_L_EX <= 16'sd0;
end
else begin
case(r_parallel_saturation_ctrl)
3'b000: begin o_EMU_R <= r_parallel; o_EMU_R_EX <= r_parallel_extended; end
3'b001: begin o_EMU_R <= 16'h7FFF; o_EMU_R_EX <= 16'h7FFF; end //saturated to positive maximum
3'b010: begin o_EMU_R <= 16'h7FFF; o_EMU_R_EX <= 16'h7FFF; end
3'b011: begin o_EMU_R <= 16'h7FFF; o_EMU_R_EX <= 16'h7FFF; end
3'b100: begin o_EMU_R <= 16'h8000; o_EMU_R_EX <= 16'h8000; end //saturated to negative maximum
3'b101: begin o_EMU_R <= 16'h8000; o_EMU_R_EX <= 16'h8000; end
3'b110: begin o_EMU_R <= 16'h8000; o_EMU_R_EX <= 16'h8000; end
3'b111: begin o_EMU_R <= r_parallel; o_EMU_R_EX <= r_parallel_extended; end
endcase
case(l_parallel_saturation_ctrl)
3'b000: begin o_EMU_L <= l_parallel; o_EMU_L_EX <= l_parallel_extended; end
3'b001: begin o_EMU_L <= 16'h7FFF; o_EMU_L_EX <= 16'h7FFF; end //saturated to positive maximum
3'b010: begin o_EMU_L <= 16'h7FFF; o_EMU_L_EX <= 16'h7FFF; end
3'b011: begin o_EMU_L <= 16'h7FFF; o_EMU_L_EX <= 16'h7FFF; end
3'b100: begin o_EMU_L <= 16'h8000; o_EMU_L_EX <= 16'h8000; end //saturated to negative maximum
3'b101: begin o_EMU_L <= 16'h8000; o_EMU_L_EX <= 16'h8000; end
3'b110: begin o_EMU_L <= 16'h8000; o_EMU_L_EX <= 16'h8000; end
3'b111: begin o_EMU_L <= l_parallel; o_EMU_L_EX <= l_parallel_extended; end
endcase
end
end
///////////////////////////////////////////////////////////
////// R/L Saturation control
////
reg mcyc15_r_stream, mcyc31_l_stream;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
case(mcyc14_r_saturation_ctrl)
3'b000: mcyc15_r_stream <= mcyc14_r_piso[0];
3'b001: mcyc15_r_stream <= 1'b1; //saturated to positive maximum
3'b010: mcyc15_r_stream <= 1'b1;
3'b011: mcyc15_r_stream <= 1'b1;
3'b100: mcyc15_r_stream <= 1'b0; //saturated to negative maximum
3'b101: mcyc15_r_stream <= 1'b0;
3'b110: mcyc15_r_stream <= 1'b0;
3'b111: mcyc15_r_stream <= mcyc14_r_piso[0];
endcase
case(mcyc30_l_saturation_ctrl)
3'b000: mcyc31_l_stream <= mcyc30_l_piso[0];
3'b001: mcyc31_l_stream <= 1'b1; //saturated to positive maximum
3'b010: mcyc31_l_stream <= 1'b1;
3'b011: mcyc31_l_stream <= 1'b1;
3'b100: mcyc31_l_stream <= 1'b0; //saturated to negative maximum
3'b101: mcyc31_l_stream <= 1'b0;
3'b110: mcyc31_l_stream <= 1'b0;
3'b111: mcyc31_l_stream <= mcyc30_l_piso[0];
endcase
end
///////////////////////////////////////////////////////////
////// Delays
////
reg mcyc16_r_stream_z, mcyc17_r_stream_zz, mcyc18_r_stream_zzz;
reg mcyc00_l_stream_z, mcyc01_l_stream_zz, mcyc02_l_stream_zzz;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
mcyc16_r_stream_z <= mcyc15_r_stream;
mcyc00_l_stream_z <= mcyc31_l_stream;
mcyc17_r_stream_zz <= mcyc16_r_stream_z;
mcyc01_l_stream_zz <= mcyc00_l_stream_z;
mcyc18_r_stream_zzz <= mcyc17_r_stream_zz;
mcyc02_l_stream_zzz <= mcyc01_l_stream_zz;
end
///////////////////////////////////////////////////////////
////// SIPO/SO register
////
wire sound_data_lookaround_register_input_stream = cycle_02_to_17 ? mcyc02_l_stream_zzz : mcyc18_r_stream_zzz;
reg [20:0] sound_data_lookaround_register;
reg [6:0] sound_data_bit_15_9;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
//The LSB of serial sound data is placed on the MSB of lookaround register if(master cycle == 17 || 1). It flows in from the LSB.
sound_data_lookaround_register[20] <= sound_data_lookaround_register_input_stream; //sound data LSB is latched at (master cycle == 18)
sound_data_lookaround_register[19:0] <= sound_data_lookaround_register[20:1];
if(cycle_01_17) sound_data_bit_15_9 <= {sound_data_lookaround_register_input_stream, sound_data_lookaround_register[20:15]};
end
///////////////////////////////////////////////////////////
////// Output MUX
////
//original chip used shift register to select bits
reg [3:0] outmux_sel_cntr;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(i_CYCLE_06_22) outmux_sel_cntr <= 4'd1;
else outmux_sel_cntr <= (outmux_sel_cntr == 4'd15) ? 4'd0 : outmux_sel_cntr + 4'd1;
end
//sound data magnitude
/*
Invert the upper bits when the number is negative.
11111...(positive max)
10000...(positive min)
00000...(negative min)
01111...(negative max)
*/
wire [5:0] sound_data_magnitude = sound_data_bit_15_9[6] ? sound_data_bit_15_9[5:0] : ~sound_data_bit_15_9[5:0];
reg sound_data_sign;
reg [2:0] sound_data_shift_amount;
reg [4:0] sound_data_output_tap;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(i_CYCLE_06_22) begin
sound_data_sign <= sound_data_bit_15_9[6];
casez(sound_data_magnitude)
6'b000000: begin sound_data_output_tap <= 5'd0; sound_data_shift_amount <= 3'd1; end //small number
6'b000001: begin sound_data_output_tap <= 5'd1; sound_data_shift_amount <= 3'd2; end
6'b00001?: begin sound_data_output_tap <= 5'd2; sound_data_shift_amount <= 3'd3; end
6'b0001??: begin sound_data_output_tap <= 5'd3; sound_data_shift_amount <= 3'd4; end
6'b001???: begin sound_data_output_tap <= 5'd4; sound_data_shift_amount <= 3'd5; end
6'b01????: begin sound_data_output_tap <= 5'd5; sound_data_shift_amount <= 3'd6; end
6'b1?????: begin sound_data_output_tap <= 5'd6; sound_data_shift_amount <= 3'd7; end //large number
default: begin sound_data_output_tap <= 5'd0; sound_data_shift_amount <= 3'd1; end
endcase
end
end
reg floating_sound_data;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(outmux_sel_cntr >= 4'd1 && outmux_sel_cntr < 4'd10) floating_sound_data <= sound_data_lookaround_register[sound_data_output_tap];
else if(outmux_sel_cntr == 4'd10) floating_sound_data <= sound_data_sign;
else if(outmux_sel_cntr == 4'd11) floating_sound_data <= sound_data_shift_amount[0];
else if(outmux_sel_cntr == 4'd12) floating_sound_data <= sound_data_shift_amount[1];
else if(outmux_sel_cntr == 4'd13) floating_sound_data <= sound_data_shift_amount[2];
else floating_sound_data <= sound_data_lookaround_register[sound_data_output_tap];
o_SO <= floating_sound_data;
end
endmodule
|
module IKAOPM_timinggen #(parameter FULLY_SYNCHRONOUS = 1, parameter FAST_RESET = 0) (
//chip clock
input wire i_EMUCLK, //emulator master clock
//chip reset
input wire i_IC_n,
output wire o_MRST_n, //core internal reset
//clock endables
input wire i_phiM_PCEN_n, //phiM positive edge clock enable(negative logic)
`ifdef IKAOPM_USER_DEFINED_CLOCK_ENABLES
input wire i_phi1_PCEN_n, //phi1 positive edge clock enable
input wire i_phi1_NCEN_n, //phi1 negative edge clock enable
`endif
//phiM/2
output wire o_phi1, //phi1 output
output wire o_phi1_PCEN_n, //positive edge clock enable for emulation
output wire o_phi1_NCEN_n, //negative edge clock enable for emulation
//SH1 and 2
output reg o_SH1,
output reg o_SH2,
//timings
output reg o_CYCLE_01,
output reg o_CYCLE_31,
output reg o_CYCLE_12_28,
output reg o_CYCLE_05_21,
output reg o_CYCLE_BYTE,
output reg o_CYCLE_05,
output reg o_CYCLE_10,
output reg o_CYCLE_03,
output reg o_CYCLE_00_16,
output reg o_CYCLE_01_TO_16,
output reg o_CYCLE_04_12_20_28,
output reg o_CYCLE_12,
output reg o_CYCLE_15_31,
output reg o_CYCLE_29,
output reg o_CYCLE_06_22
);
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1ncen_n = o_phi1_NCEN_n;
wire mrst_n = o_MRST_n;
///////////////////////////////////////////////////////////
////// Reset generator
////
reg ic_n_negedge = 1'b1; //IC_n negedge detector
reg synced_mrst_n = 1'b0; //synchronized master reset
wire phi1_init;
generate
if(FAST_RESET == 0) begin : FAST_RESET_0_clock_and_global_rst
assign o_MRST_n = synced_mrst_n;
assign phi1_init = ic_n_negedge;
end
else begin : FAST_RESET_1_clock_and_global_rst
assign o_MRST_n = synced_mrst_n & i_IC_n;
assign phi1_init = ic_n_negedge | ~i_IC_n;
end
endgenerate
generate
if(FULLY_SYNCHRONOUS == 0) begin : FULLY_SYNCHRONOUS_0_reset_syncchain
//2 stage SR for synchronization
reg [1:0] ic_n_internal = 2'b00;
always @(posedge i_EMUCLK) if(!i_phiM_PCEN_n) begin
ic_n_internal[0] <= i_IC_n;
ic_n_internal[1] <= ic_n_internal[0]; //shift
end
//ICn falling edge detector for phi1 phase initialization
always @(posedge i_EMUCLK) if(!i_phiM_PCEN_n) begin
ic_n_negedge <= ~ic_n_internal[0] & ic_n_internal[1];
end
//internal master reset
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
synced_mrst_n <= ic_n_internal[0];
end
end
else begin : FULLY_SYNCHRONOUS_1_reset_syncchain
//add two stage SR
//4 stage SR for synchronization
reg [3:0] ic_n_internal = 4'b0000;
always @(posedge i_EMUCLK) if(!i_phiM_PCEN_n) begin
ic_n_internal[0] <= i_IC_n;
ic_n_internal[3:1] <= ic_n_internal[2:0]; //shift
end
//ICn falling edge detector for phi1 phase initialization
always @(posedge i_EMUCLK) if(!i_phiM_PCEN_n) begin
ic_n_negedge <= ~ic_n_internal[2] & ic_n_internal[3];
end
//internal master reset
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
synced_mrst_n <= ic_n_internal[2];
end
end
endgenerate
///////////////////////////////////////////////////////////
////// phi1 and clock enables generator
////
/*
CLOCKING INFORMATION(ORIGINAL CHIP)
phiM _______|¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|
ICn ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|___________________________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
ICn neg ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
ICn pos ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
IC _________________________________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|__________________________________________________
IC neg det _________________________________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|________________________________________________________
phi1 ¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|________
(FPGA)
EMUCLK ¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|¯|_|
phiM cen ¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯¯¯¯|___|¯¯¯¯¯¯¯¯
phiM _______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|_______|¯¯¯¯¯¯¯|
phi1p ¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|________
phi1n _______|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______________________________________________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_______________|¯¯¯¯¯¯¯¯
*/
`ifdef IKAOPM_USER_DEFINED_CLOCK_ENABLES
reg phi1;
always @(posedge i_EMUCLK) begin
case({i_phi1_PCEN_n, i_phi1_NCEN_n})
2'b00: phi1 <= phi1;
2'b01: phi1 <= 1'b1;
2'b10: phi1 <= 1'b0;
2'b11: phi1 <= phi1;
endcase
end
//phi1 output(for reference)
assign o_phi1 = phi1;
generate
if(FAST_RESET == 0) begin : FAST_RESET_0_cenout
//phi1 cen(internal)
assign o_phi1_PCEN_n = i_phi1_PCEN_n;
assign o_phi1_NCEN_n = i_phi1_NCEN_n;
end
else begin : FAST_RESET_1_cenout
//phi1 cen(internal)
assign o_phi1_PCEN_n = i_phi1_PCEN_n & i_IC_n;
assign o_phi1_NCEN_n = i_phi1_NCEN_n & i_IC_n;
end
endgenerate
`else
//actual phi1 output is phi1p(positive), and the inverted phi1 is phi1n(negative)
reg phi1p, phi1n;
generate
if(FAST_RESET == 0) begin : FAST_RESET_0_phi1gen
always @(posedge i_EMUCLK) if(!i_phiM_PCEN_n) begin
if(phi1_init) begin phi1p <= 1'b1; phi1n <= 1'b1; end //reset
else begin phi1p <= ~phi1p; phi1n <= phi1p; end //toggle
end
end
else begin : FAST_RESET_1_phi1gen
always @(posedge i_EMUCLK) if(!(i_phiM_PCEN_n & i_IC_n)) begin
if(phi1_init) begin phi1p <= 1'b1; phi1n <= 1'b1; end //reset
else begin phi1p <= ~phi1p; phi1n <= phi1p; end //toggle
end
end
endgenerate
//phi1 output(for reference)
assign o_phi1 = phi1p;
generate
if(FAST_RESET == 0) begin : FAST_RESET_0_cenout
//phi1 cen(internal)
assign o_phi1_PCEN_n = phi1p | i_phiM_PCEN_n; //ORed signal
assign o_phi1_NCEN_n = phi1n | i_phiM_PCEN_n;
end
else begin : FAST_RESET_1_cenout
//phi1 cen(internal)
assign o_phi1_PCEN_n = (phi1p | i_phiM_PCEN_n) & i_IC_n; //ORed signal
assign o_phi1_NCEN_n = (phi1n | i_phiM_PCEN_n) & i_IC_n;
end
endgenerate
`endif
///////////////////////////////////////////////////////////
////// Timing Generator
////
//
// counter
//
reg [4:0] timinggen_cntr = 5'h0;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(!mrst_n) begin
timinggen_cntr <= 5'h0;
end
else begin
if(timinggen_cntr == 5'h1F) timinggen_cntr <= 5'h0;
else timinggen_cntr <= timinggen_cntr + 5'h1;
end
end
//
// decoder
//
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
//REG
o_CYCLE_01 <= timinggen_cntr == 5'd0;
o_CYCLE_31 <= timinggen_cntr == 5'd30;
//LFO
o_CYCLE_12_28 <= (timinggen_cntr == 5'd11) | (timinggen_cntr == 5'd27);
o_CYCLE_05_21 <= (timinggen_cntr == 5'd4) | (timinggen_cntr == 5'd20);
o_CYCLE_BYTE <= (timinggen_cntr[3:1] == 3'b111) |
(timinggen_cntr[3:1] == 3'b010) |
(timinggen_cntr[3:2] == 2'b00);
//PG
o_CYCLE_05 <= timinggen_cntr == 5'd4;
o_CYCLE_10 <= timinggen_cntr == 5'd9;
//EG
o_CYCLE_03 <= timinggen_cntr == 5'd2;
o_CYCLE_00_16 <= (timinggen_cntr == 5'd31) | (timinggen_cntr == 5'd15);
o_CYCLE_01_TO_16 <= ~timinggen_cntr[4];
//OP
o_CYCLE_04_12_20_28 <= (timinggen_cntr == 5'd3) | (timinggen_cntr == 5'd11) | (timinggen_cntr == 5'd19) | (timinggen_cntr == 5'd27);
//ACC
o_CYCLE_29 <= timinggen_cntr == 5'd28;
o_CYCLE_06_22 <= (timinggen_cntr == 5'd05) | (timinggen_cntr == 5'd21);
//NOISE
o_CYCLE_12 <= timinggen_cntr == 5'd11;
o_CYCLE_15_31 <= (timinggen_cntr == 5'd14) | (timinggen_cntr == 5'd30);
end
///////////////////////////////////////////////////////////
////// SH1 / SH2
////
//sh1/sh2
wire sh1 = timinggen_cntr[4:3] == 2'b01; //01XXX
wire sh2 = timinggen_cntr[4:3] == 2'b11; //11XXX
reg [4:0] sh1_sr, sh2_sr;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
//sh1/2 shift register
sh1_sr[0] <= sh1;
sh2_sr[0] <= sh2;
sh1_sr[4:1] <= sh1_sr[3:0];
sh2_sr[4:1] <= sh2_sr[3:0];
//sh1/2 output
o_SH1 <= sh1_sr[4] & mrst_n;
o_SH2 <= sh2_sr[4] & mrst_n;
end
endmodule
|
module IKAOPM_pg #(parameter USE_BRAM_FOR_PHASEREG = 0) (
//master clock
input wire i_EMUCLK, //emulator master clock
//core internal reset
input wire i_MRST_n,
//internal clock
input wire i_phi1_PCEN_n, //positive edge clock enable for emulation
input wire i_phi1_NCEN_n, //negative edge clock enable for emulation
//timings
input wire i_CYCLE_05, //ch6 c2 phase piso sr parallel load
input wire i_CYCLE_10,
//register data
input wire [6:0] i_KC, //Key Code
input wire [5:0] i_KF, //Key Fraction
input wire [2:0] i_PMS, //Pulse Modulation Sensitivity
input wire [1:0] i_DT2, //Detune 2
input wire [2:0] i_DT1, //Detune 1
input wire [3:0] i_MUL,
input wire i_TEST_D3, //test register
//Vibrato
input wire [7:0] i_LFP,
//send signals to other modules
input wire i_PG_PHASE_RST, //phase reset request signal from PG
output wire [4:0] o_EG_PDELTA_SHIFT_AMOUNT, //send shift amount to EG
output wire [9:0] o_OP_PHASEDATA, //send phase data to OP
output wire o_REG_PHASE_CH6_C2 //send Ch6, Carrier2 phase data to REG serially
);
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1ncen_n = i_phi1_NCEN_n;
wire mrst_n = i_MRST_n;
///////////////////////////////////////////////////////////
////// Cycle 0: PMS decoding, ex-LFP conversion
////
// DESCRIPTION
//The original chip decodes PMS value in this step(we don't need to do it)
//and does extended LFP conversion with few adders.
//
// combinational part
//
//ex-lfp conversion
wire [2:0] cyc0c_ex_lfp_weight0 = (i_PMS == 3'd7) ? i_LFP[6:4] : {1'b0, i_LFP[6:5]};
wire [2:0] cyc0c_ex_lfp_weight1 = (i_PMS == 3'd7) ? {2'b00, i_LFP[6]} : 3'b000;
wire cyc0c_ex_lfp_weight2 = (i_PMS == 3'd7) ? ((i_LFP[6] & i_LFP[5]) | (i_LFP[5] & i_LFP[4])) :
(i_PMS == 3'd6) ? (i_LFP[6] & i_LFP[5]) : 1'b0;
wire [3:0] cyc0c_ex_lfp_weightsum = cyc0c_ex_lfp_weight0 + cyc0c_ex_lfp_weight1 + cyc0c_ex_lfp_weight2;
//
// register part
//
reg [2:0] cyc0r_pms_level;
reg [7:0] cyc0r_ex_lfp;
reg cyc0r_ex_lfp_sign;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc0r_pms_level <= i_PMS;
if(i_PMS == 3'd7) cyc0r_ex_lfp <= {cyc0c_ex_lfp_weightsum, i_LFP[3:0]};
else cyc0r_ex_lfp <= {cyc0c_ex_lfp_weightsum[2:0], i_LFP[4:0]};
//lfp_sign becomes 1 when PMS > 0 and LFP sign is negative to convert lfp_ex to 2's complement
cyc0r_ex_lfp_sign <= (i_PMS > 3'd0) & i_LFP[7];
end
///////////////////////////////////////////////////////////
////// Cycle 1: Pitch value calculation
////
// DESCRIPTION
//The original chip decodes PMS value in this step(we don't need to do it)
//and does extended LFP conversion with few adders.
//
// combinational part
//
reg [12:0] cyc1c_lfp_deviance;
always @(*) begin
case(cyc0r_pms_level)
3'd0: cyc1c_lfp_deviance = 13'b0;
3'd1: cyc1c_lfp_deviance = {11'b0, cyc0r_ex_lfp[6:5] };
3'd2: cyc1c_lfp_deviance = {10'b0, cyc0r_ex_lfp[6:4] };
3'd3: cyc1c_lfp_deviance = {9'b0, cyc0r_ex_lfp[6:3] };
3'd4: cyc1c_lfp_deviance = {8'b0, cyc0r_ex_lfp[6:2] };
3'd5: cyc1c_lfp_deviance = {7'b0, cyc0r_ex_lfp[6:1] };
3'd6: cyc1c_lfp_deviance = {4'b0, cyc0r_ex_lfp[7:0], 1'b0};
3'd7: cyc1c_lfp_deviance = {3'b0, cyc0r_ex_lfp[7:0], 2'b0};
endcase
end
wire [6:0] cyc1c_frac_adder = i_KF + (cyc1c_lfp_deviance[5:0] ^ {6{cyc0r_ex_lfp_sign}}) + cyc0r_ex_lfp_sign;
wire [7:0] cyc1c_int_adder = i_KC + (cyc1c_lfp_deviance[12:6] ^ {7{cyc0r_ex_lfp_sign}}) + cyc1c_frac_adder[6];
wire [2:0] cyc1c_notegroup_adder = i_KC[1:0] + (cyc1c_lfp_deviance[7:6] ^ {2{cyc0r_ex_lfp_sign}}) + cyc1c_frac_adder[6];
//wire [12:0] cyc1c_modded_raw_pitchval = (cyc0r_ex_lfp_sign == 1'b0) ? {i_KC, i_KF} + cyc1c_lfp_deviance : {i_KC, i_KF} + ~cyc1c_lfp_deviance + 13'd1;
//
// register part
//
reg [12:0] cyc1r_modded_pitchval; //add or subtract LFP value from KC, KF
reg cyc1r_modded_pitchval_ovfl;
reg cyc1r_notegroup_nopitchmod; //this flag set when no "LFP" addend is given to a "note group" range(note group: 012/456/89A/CDE)
reg cyc1r_notegroup_ovfl; //note group overflow, e.g. 6(3'b1_10) + 2(3'b0_10)
reg cyc1r_lfp_sign;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc1r_modded_pitchval <= {cyc1c_int_adder[6:0], cyc1c_frac_adder[5:0]};
cyc1r_modded_pitchval_ovfl <= cyc1c_int_adder[7];
cyc1r_notegroup_nopitchmod <= (cyc1c_lfp_deviance[7:6] ^ {2{cyc0r_ex_lfp_sign}}) == 2'b00;
cyc1r_notegroup_ovfl <= cyc1c_notegroup_adder[2];
//bypass
cyc1r_lfp_sign <= cyc0r_ex_lfp_sign;
end
///////////////////////////////////////////////////////////
////// Cycle 2: Notegroup rearrange
////
// DESCRIPTION
//The pitch value modulated by the LFP value can cause notegroup violation.
//Modify the integer part of this pitch value if it is out of the note group range.
//Notegroup (note group: 012/456/89A/CDE)
//
// combinational part
//
//wire cyc2c_int_adder_add1 = ((cyc1r_modded_pitchval[7:6] == 2'd3) | cyc1r_notegroup_ovfl) & ~cyc1r_lfp_sign;
//wire cyc2c_int_adder_sub1 = ~(cyc1r_notegroup_nopitchmod | cyc1r_notegroup_ovfl | ~cyc1r_lfp_sign);
//wire [7:0] cyc2c_int_adder = cyc1r_modded_pitchval[12:6] + {7{cyc2c_int_adder_sub1}} + cyc2c_int_adder_add1;
reg [7:0] cyc2c_int_adder;
always @(*) begin
case({(cyc1r_modded_pitchval[7:6] == 2'd3), cyc1r_notegroup_nopitchmod, cyc1r_notegroup_ovfl, cyc1r_lfp_sign})
//valid notegroup value
4'b0_0_0_0: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] ; //
4'b0_0_0_1: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] + 7'h7F; //
4'b0_0_1_0: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] + 7'h01; //
4'b0_0_1_1: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] ; //
4'b0_1_0_0: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] ; //
4'b0_1_0_1: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] ; //
4'b0_1_1_0: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] + 7'h01; //
4'b0_1_1_1: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] ; //
//invalid notegroup value
4'b1_0_0_0: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] + 7'h01; //
4'b1_0_0_1: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] + 7'h7F; //
4'b1_0_1_0: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] + 7'h01; //
4'b1_0_1_1: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] ; //
4'b1_1_0_0: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] + 7'h01; //
4'b1_1_0_1: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] ; //
4'b1_1_1_0: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] + 7'h01; //
4'b1_1_1_1: cyc2c_int_adder = cyc1r_modded_pitchval[12:6] ; //
endcase
end
//
// register part
//
reg [12:0] cyc2r_rearranged_pitchval;
reg cyc2r_rearranged_pitchval_ovfl;
reg cyc2r_modded_pitchval_ovfl;
reg cyc2r_int_sub1;
reg cyc2r_lfp_sign;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc2r_rearranged_pitchval <= {cyc2c_int_adder[6:0], cyc1r_modded_pitchval[5:0]};
cyc2r_rearranged_pitchval_ovfl <= cyc2c_int_adder[7];
cyc2r_int_sub1 <= ~(cyc1r_notegroup_nopitchmod | cyc1r_notegroup_ovfl | ~cyc1r_lfp_sign);
cyc2r_modded_pitchval_ovfl <= cyc1r_modded_pitchval_ovfl;
cyc2r_lfp_sign <= cyc1r_lfp_sign;
end
`ifdef IKAOPM_DEBUG
wire [13:0] debug_cyc1c_lfp_deviance = (cyc0r_ex_lfp_sign == 1'b1) ? (~cyc1c_lfp_deviance + 7'h1) : cyc1c_lfp_deviance;
wire debug_cyc1r_notrgroup_violation = cyc1r_modded_pitchval[7:6] == 2'd3;
wire debug_cyc2r_notrgroup_violation = cyc2r_rearranged_pitchval[7:6] == 2'd3;
`endif
///////////////////////////////////////////////////////////
////// Cycle 3: Overflow control
////
// DESCRIPTION
//Controls the rearranged pitch values to be saturated.
//
// register part
//
reg [12:0] cyc3r_saturated_pitchval;
reg [1:0] cyc3r_dt2; //just delays, the original chip decodes DT2 input here, we don't have to do.
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
casez({cyc2r_lfp_sign, cyc2r_modded_pitchval_ovfl, cyc2r_int_sub1, cyc2r_rearranged_pitchval_ovfl})
//lfp = positive
4'b0000: cyc3r_saturated_pitchval <= cyc2r_rearranged_pitchval;
4'b00?1: cyc3r_saturated_pitchval <= 13'b111_1110_111111; //max
4'b01?0: cyc3r_saturated_pitchval <= 13'b111_1110_111111;
4'b01?1: cyc3r_saturated_pitchval <= 13'b111_1110_111111;
4'b0010: cyc3r_saturated_pitchval <= 13'b000_0000_000000; //will never happen
//lfp = negative
4'b1000: cyc3r_saturated_pitchval <= 13'b000_0000_000000; //min
4'b1001: cyc3r_saturated_pitchval <= 13'b000_0000_000000;
4'b1010: cyc3r_saturated_pitchval <= 13'b000_0000_000000;
4'b1011: cyc3r_saturated_pitchval <= 13'b000_0000_000000;
4'b1100: cyc3r_saturated_pitchval <= cyc2r_rearranged_pitchval;
4'b1101: cyc3r_saturated_pitchval <= cyc2r_rearranged_pitchval;
4'b1110: cyc3r_saturated_pitchval <= 13'b000_0000_000000;
4'b1111: cyc3r_saturated_pitchval <= cyc2r_rearranged_pitchval;
endcase
cyc3r_dt2 <= i_DT2;
end
///////////////////////////////////////////////////////////
////// Cycle 4: apply DT2 to fractional part
////
// DESCRIPTION
//Apply DT2 to fractional part of the pitch value
//fixed point, fractional part is 6 bits. 0.015625 step value
//
// register part
//
reg [6:0] cyc4r_frac_detuned_pitchval; //carry + 6bit value
reg [6:0] cyc4r_int_pitchval;
reg [1:0] cyc4r_dt2;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
case(cyc3r_dt2)
2'd0: cyc4r_frac_detuned_pitchval <= cyc3r_saturated_pitchval[5:0] + 6'd0 + 1'd0;
2'd1: cyc4r_frac_detuned_pitchval <= cyc3r_saturated_pitchval[5:0] + 6'd0 + 1'd0;
2'd2: cyc4r_frac_detuned_pitchval <= cyc3r_saturated_pitchval[5:0] + 6'd52 + 1'd0; //fractional part +0.8125
2'd3: cyc4r_frac_detuned_pitchval <= cyc3r_saturated_pitchval[5:0] + 6'd32 + 1'd0; //fractional part +0.5
endcase
cyc4r_int_pitchval <= cyc3r_saturated_pitchval[12:6];
cyc4r_dt2 <= cyc3r_dt2;
end
///////////////////////////////////////////////////////////
////// Cycle 5: apply DT2 to integer part
////
// DESCRIPTION
//Apply DT2 to integer part of the pitch value
//
// register part
//
reg [5:0] cyc5r_frac_detuned_pitchval; //no carry here
reg [7:0] cyc5r_int_detuned_pitchval; //carry + 7bit value
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
casez({cyc4r_dt2, cyc4r_frac_detuned_pitchval[6], cyc4r_int_pitchval[1:0]})
//dt2 = 0
5'b00_0_00: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd0;
5'b00_0_01: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd0;
5'b00_0_10: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd0;
5'b00_0_11: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd0;
5'b00_1_00: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd0 + 7'd1;
5'b00_1_01: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd0 + 7'd1;
5'b00_1_10: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd0 + 7'd2;
5'b00_1_11: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd0 + 7'd2;
// |---base value---| + dt2 + carry(avoids notegroup violation)
//dt2 = 1
5'b01_0_00: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd8;
5'b01_0_01: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd8;
5'b01_0_10: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd8;
5'b01_0_11: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd8;
5'b01_1_00: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd8 + 7'd1;
5'b01_1_01: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd8 + 7'd1;
5'b01_1_10: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd8 + 7'd2;
5'b01_1_11: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd8 + 7'd2;
//dt2 = 2
5'b10_0_00: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd9;
5'b10_0_01: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd9;
5'b10_0_10: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd9 + 7'd1;
5'b10_0_11: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd9 + 7'd1;
5'b10_1_00: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd9 + 7'd1;
5'b10_1_01: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd9 + 7'd2;
5'b10_1_10: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd9 + 7'd2;
5'b10_1_11: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd9 + 7'd2;
//dt2 = 3
5'b11_0_00: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd12;
5'b11_0_01: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd12;
5'b11_0_10: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd12;
5'b11_0_11: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd12;
5'b11_1_00: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd12 + 7'd1;
5'b11_1_01: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd12 + 7'd1;
5'b11_1_10: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd12 + 7'd2;
5'b11_1_11: cyc5r_int_detuned_pitchval <= cyc4r_int_pitchval + 7'd12 + 7'd2;
endcase
cyc5r_frac_detuned_pitchval <= cyc4r_frac_detuned_pitchval[5:0]; //discard carry
end
///////////////////////////////////////////////////////////
////// Cycle 6: Overflow control, Keycode to F-num 1
////
// DESCRIPTION
//Controls the final pitch values to be saturated.
//
// combinational part
//
wire [12:0] cyc6c_final_pitchval = (cyc5r_int_detuned_pitchval[7] == 1'b1) ? 13'b111_1110_111111 : {cyc5r_int_detuned_pitchval[6:0], cyc5r_frac_detuned_pitchval};
// DESCRIPTION
//This ROM has absolute phase increment value(pdelta) and
//fine tuning value for small phase changes. Now we get the values
//from the conversion table.
//
// register part
//
reg [4:0] cyc6r_pdelta_shift_amount;
wire [11:0] cyc6r_pdelta_base;
wire [3:0] cyc6r_pdelta_increment_multiplicand;
reg [3:0] cyc6r_pdelta_increment_multiplier;
wire cyc6r_pdelta_calcmode;
pg_submdl_fnumrom u_cyc6r_fnumrom (
.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_ADDR(cyc6c_final_pitchval[9:4]),
.o_DATA({cyc6r_pdelta_base, cyc6r_pdelta_increment_multiplicand[0], cyc6r_pdelta_increment_multiplicand[3:1], cyc6r_pdelta_calcmode})
//The original chip's output bit order is scrambled!
);
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc6r_pdelta_shift_amount <= cyc6c_final_pitchval[12:8];
cyc6r_pdelta_increment_multiplier <= cyc6c_final_pitchval[3:0];
end
///////////////////////////////////////////////////////////
////// Cycle 7: Keycode to F-num 2
////
// DESCRIPTION
//Now we have to generate the value to adjust the pdelta base value.
//YM2151 decompresses the ROM output we got in the previous step.
//
//in calcmode == 0, we can write the weird expression like this:
//if(multiply[3:2] == 2'b11) and (increment[0] == 1'b0), then +4
//if(multiply[3] == 1'b1), then +1
//if(multiply[1] == 1'b1), then +8
//if(multuply[0] == 1'b1), then +2
//
// register part
//
reg [4:0] cyc7r_pdelta_shift_amount;
reg [11:0] cyc7r_pdelta_base;
reg [6:0] cyc7r_multiplied_increment;
assign o_EG_PDELTA_SHIFT_AMOUNT = cyc7r_pdelta_shift_amount;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc7r_pdelta_shift_amount <= cyc6r_pdelta_shift_amount;
cyc7r_pdelta_base <= cyc6r_pdelta_base;
if(cyc6r_pdelta_calcmode) begin
cyc7r_multiplied_increment <= ({{1'b1, cyc6r_pdelta_increment_multiplicand} >> 0} & {5{cyc6r_pdelta_increment_multiplier[3]}}) +
({{1'b1, cyc6r_pdelta_increment_multiplicand} >> 1} & {5{cyc6r_pdelta_increment_multiplier[2]}}) +
({{1'b1, cyc6r_pdelta_increment_multiplicand} >> 2} & {5{cyc6r_pdelta_increment_multiplier[1]}}) +
({{1'b1, cyc6r_pdelta_increment_multiplicand} >> 3} & {5{cyc6r_pdelta_increment_multiplier[0]}});
end
else begin
cyc7r_multiplied_increment <= ({{1'b1, cyc6r_pdelta_increment_multiplicand[3:1], 1'b1} >> 0} & {5{cyc6r_pdelta_increment_multiplier[3]}}) +
({{1'b1, cyc6r_pdelta_increment_multiplicand[3:1], 1'b1} >> 1} & {5{cyc6r_pdelta_increment_multiplier[2]}}) +
({{1'b1, cyc6r_pdelta_increment_multiplicand[3:1], 1'b1} >> 3} & {5{cyc6r_pdelta_increment_multiplier[0]}}) +
(5'd4 & {5{&{cyc6r_pdelta_increment_multiplier[3:2], ~cyc6r_pdelta_increment_multiplicand[0]}}}) +
(5'd1 & {5{cyc6r_pdelta_increment_multiplier[3]}}) +
(5'd8 & {5{cyc6r_pdelta_increment_multiplier[1]}}) +
(5'd2 & {5{cyc6r_pdelta_increment_multiplier[0]}});
end
end
///////////////////////////////////////////////////////////
////// Cycle 8: Keycode to F-num 3, DT1/MUL latch
////
// DESCRIPTION
//This is the third step of F-num conversion.
//Discard the LSB of "cyc7r_multiplied_increment" first.
//Add them to the base next.
//
// register part
//
reg [4:0] cyc8r_pdelta_shift_amount;
reg [11:0] cyc8r_pdelta_base;
reg [2:0] cyc8r_dt1;
reg [3:0] cyc8r_mul;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc8r_pdelta_shift_amount <= cyc7r_pdelta_shift_amount;
cyc8r_pdelta_base <= cyc7r_pdelta_base + {6'b0, cyc7r_multiplied_increment[6:1]};
cyc8r_dt1 <= i_DT1;
cyc8r_mul <= i_MUL;
end
///////////////////////////////////////////////////////////
////// Cycle 9: Keycode to F-num 4, DT1 decode
////
// DESCRIPTION
//This is the last step of F-num conversion. Shift the pdelta
//value using the shift amount[4:3].
//Calculate the intensity of detuning amount. Decode the base
//detuning value from DT1 parameter.
//
// combinational part
//
//intensity shifts the base value
reg [4:0] cyc9c_dt1_intensity; //possible intensity value: from 1 to 19
always @(*) begin
case(cyc8r_dt1[1:0])
2'd0: cyc9c_dt1_intensity = {1'b0, cyc8r_pdelta_shift_amount[4:2]} + 4'd0 + 1'd1; //always +1, confirmed 2023-07-06
2'd1: cyc9c_dt1_intensity = {1'b0, cyc8r_pdelta_shift_amount[4:2]} + 4'd8 + 1'd1;
2'd2: cyc9c_dt1_intensity = {1'b0, cyc8r_pdelta_shift_amount[4:2]} + 4'd10 + 1'd1;
2'd3: cyc9c_dt1_intensity = {1'b0, cyc8r_pdelta_shift_amount[4:2]} + 4'd11 + 1'd1;
endcase
end
//generate the base value(PLA), confirmed 2023-07-06
wire [1:0] cyc9c_dt1_base_sel = (cyc8r_pdelta_shift_amount >= 5'd28) ? 2'd0 : cyc8r_pdelta_shift_amount[1:0]; //confirmed 2023-07-06
reg [4:0] cyc9c_dt1_base;
always @(*) begin
case({cyc9c_dt1_intensity[0], cyc9c_dt1_base_sel})
//dt1 intensity is even
3'b0_00: cyc9c_dt1_base = 5'b10000; //1, 0
3'b0_01: cyc9c_dt1_base = 5'b10001; //1, 1
3'b0_10: cyc9c_dt1_base = 5'b10011; //1, 3
3'b0_11: cyc9c_dt1_base = 5'b10100; //1, 4
//dt1 intensity is odd
3'b1_00: cyc9c_dt1_base = 5'b10110; //1, 6
3'b1_01: cyc9c_dt1_base = 5'b11000; //1, 8
3'b1_10: cyc9c_dt1_base = 5'b11011; //1, 11
3'b1_11: cyc9c_dt1_base = 5'b11101; //1, 13
endcase
end
//
// register part
//
wire [19:0] cyc40r_phase_sr_out; //get previous phase from the cycle 40, SR last step(21)
reg [19:0] cyc9r_previous_phase;
reg [16:0] cyc9r_shifted_pdelta;
reg [16:0] cyc9r_pdelta_detuning_value;
reg [3:0] cyc9r_mul;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
case(cyc8r_pdelta_shift_amount[4:2])
3'd0: cyc9r_shifted_pdelta <= {7'b0000000, cyc8r_pdelta_base[11:2]}; //>>4
3'd1: cyc9r_shifted_pdelta <= {6'b000000, cyc8r_pdelta_base[11:1] }; //>>3
3'd2: cyc9r_shifted_pdelta <= {5'b00000, cyc8r_pdelta_base }; //>>2
3'd3: cyc9r_shifted_pdelta <= {4'b0000, cyc8r_pdelta_base, 1'b0 }; //>>1
3'd4: cyc9r_shifted_pdelta <= {3'b000, cyc8r_pdelta_base, 2'b00 }; //zero
3'd5: cyc9r_shifted_pdelta <= {2'b00, cyc8r_pdelta_base, 3'b000 }; //<<1
3'd6: cyc9r_shifted_pdelta <= {1'b0, cyc8r_pdelta_base, 4'b0000 }; //<<2
3'd7: cyc9r_shifted_pdelta <= { cyc8r_pdelta_base, 5'b00000 }; //<<3
endcase
case(cyc9c_dt1_intensity[4:1])
// DT1 is ? |-------- positive --------| |------------- negative -----------| intensity
4'b0101: cyc9r_pdelta_detuning_value <= (cyc8r_dt1[2] == 1'b0) ? {16'd0, cyc9c_dt1_base[4]} : ~{16'd0, cyc9c_dt1_base[4]} + 1'd1; //10, 11
4'b0110: cyc9r_pdelta_detuning_value <= (cyc8r_dt1[2] == 1'b0) ? {15'd0, cyc9c_dt1_base[4:3]} : ~{15'd0, cyc9c_dt1_base[4:3]} + 1'd1; //12, 13
4'b0111: cyc9r_pdelta_detuning_value <= (cyc8r_dt1[2] == 1'b0) ? {14'd0, cyc9c_dt1_base[4:2]} : ~{14'd0, cyc9c_dt1_base[4:2]} + 1'd1; //14, 15
4'b1000: cyc9r_pdelta_detuning_value <= (cyc8r_dt1[2] == 1'b0) ? {13'd0, cyc9c_dt1_base[4:1]} : ~{13'd0, cyc9c_dt1_base[4:1]} + 1'd1; //16, 17
4'b1001: cyc9r_pdelta_detuning_value <= (cyc8r_dt1[2] == 1'b0) ? {12'd0, cyc9c_dt1_base} : ~{12'd0, cyc9c_dt1_base} + 1'd1; //18, 19
default: cyc9r_pdelta_detuning_value <= 17'd0; //1 to 9
endcase
cyc9r_mul <= cyc8r_mul;
cyc9r_previous_phase <= mrst_n ? cyc40r_phase_sr_out : 20'd0; //force reset added
end
///////////////////////////////////////////////////////////
////// Cycle 10: apply DT1
////
// DESCRIPTION
//Sum shifted pdelta and detuning value.
//YM2151 adds low bits in this step, but we don't have to do it.
//Add everything within one cycle.
//
// register part
//
reg [19:0] cyc10r_previous_phase;
reg [16:0] cyc10r_detuned_pdelta; //ignore carry
reg [3:0] cyc10r_mul;
reg cyc10r_phase_rst;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc10r_detuned_pdelta <= cyc9r_shifted_pdelta + cyc9r_pdelta_detuning_value;
cyc10r_mul <= cyc9r_mul;
cyc10r_previous_phase <= cyc9r_previous_phase;
cyc10r_phase_rst <= i_PG_PHASE_RST;
end
///////////////////////////////////////////////////////////
////// Cycle 11: delay
////
// DESCRIPTION
//YM2151 adds high bits in this step.
//Just latch multiplier. The original chip decodes mul value
//here to feed some control signal for booth multiplier.
//
// register part
//
reg [19:0] cyc11r_previous_phase;
reg [16:0] cyc11r_detuned_pdelta;
reg [3:0] cyc11r_mul;
reg cyc11r_phase_rst;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc11r_detuned_pdelta <= cyc10r_detuned_pdelta;
cyc11r_mul <= cyc10r_mul;
cyc11r_previous_phase <= cyc10r_previous_phase;
cyc11r_phase_rst <= cyc10r_phase_rst;
end
///////////////////////////////////////////////////////////
////// Cycle 12: apply mul
////
//
// register part
//
reg [19:0] cyc12r_previous_phase;
reg [19:0] cyc12r_multiplied_pdelta; //131071*15 = 1_1101_1111_1111_1111_0001, max 21 bits, but discard MSB anyway
reg cyc12r_phase_rst;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(cyc11r_mul == 4'b0) cyc12r_multiplied_pdelta <= {4'b0000, cyc11r_detuned_pdelta[16:1]}; // divide by 2
else begin
cyc12r_multiplied_pdelta <= cyc11r_detuned_pdelta * cyc11r_mul;
end
cyc12r_previous_phase <= cyc11r_previous_phase;
cyc12r_phase_rst <= cyc11r_phase_rst;
end
///////////////////////////////////////////////////////////
////// Cycle 13: delay
////
//
// register part
//
reg [19:0] cyc13r_previous_phase;
reg [19:0] cyc13r_multiplied_pdelta; //ignore carry
reg cyc13r_phase_rst;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc13r_multiplied_pdelta <= cyc12r_multiplied_pdelta[19:0];
cyc13r_previous_phase <= cyc12r_previous_phase;
cyc13r_phase_rst <= cyc12r_phase_rst;
end
///////////////////////////////////////////////////////////
////// Cycle 14: reset phase
////
//
// register part
//
reg [19:0] cyc14r_previous_phase;
reg [19:0] cyc14r_final_pdelta;
reg cyc14r_phase_rst;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc14r_final_pdelta <= (cyc13r_phase_rst) ? 20'd0 : cyc13r_multiplied_pdelta;
cyc14r_previous_phase <= cyc13r_previous_phase;
cyc14r_phase_rst <= cyc13r_phase_rst;
end
///////////////////////////////////////////////////////////
////// Cycle 15: delay
////
//
// register part
//
reg [19:0] cyc15r_previous_phase;
reg [19:0] cyc15r_final_pdelta;
reg cyc15r_phase_rst;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc15r_final_pdelta <= cyc14r_final_pdelta;
cyc15r_previous_phase <= cyc14r_previous_phase;
cyc15r_phase_rst <= cyc14r_phase_rst;
end
///////////////////////////////////////////////////////////
////// Cycle 16: delay, reset previous phase
////
//
// register part
//
reg [19:0] cyc16r_final_pdelta;
reg [19:0] cyc16r_previous_phase;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc16r_final_pdelta <= cyc15r_final_pdelta;
cyc16r_previous_phase <= (cyc15r_phase_rst | i_TEST_D3) ? 20'd0 : cyc15r_previous_phase;
end
///////////////////////////////////////////////////////////
////// Cycle 17: sum previous phase and pdelta
////
// DESCRIPTION
//YM2151 adds low bits in this step. We will sum entire bits.
//
// register part
//
reg [19:0] cyc17r_current_phase; //ignore carry
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc17r_current_phase <= cyc16r_previous_phase + cyc16r_final_pdelta;
end
///////////////////////////////////////////////////////////
////// Cycle 18: delay
////
// DESCRIPTION
//YM2151 adds high bits in this step.
//
// register part
//
reg [19:0] cyc18r_current_phase;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc18r_current_phase <= mrst_n ? cyc17r_current_phase : 20'd0; //force reset added
end
///////////////////////////////////////////////////////////
////// Cycle 19-40: delay shift register
////
// DESCRIPTION
//10-bit processing chain above and 22-bit length shift register
//will store all 32 phases.
//
// register part
//
generate
if(USE_BRAM_FOR_PHASEREG == 0) begin: phasesr_mode_sr
primitive_sr #(.WIDTH(20), .LENGTH(22), .TAP(22)) u_cyc19r_cyc40r_phase_sr
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(cyc18r_current_phase), .o_Q_TAP(), .o_Q_LAST(cyc40r_phase_sr_out));
end
else begin: phasesr_mode_bram
primitive_sr_bram #(.WIDTH(20), .LENGTH(32), .TAP(22)) u_cyc19r_cyc40r_phase_sr
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(i_CYCLE_10 | ~mrst_n), .i_WR(1'b1), .i_D(cyc18r_current_phase), .o_Q_TAP(cyc40r_phase_sr_out));
end
endgenerate
//last stage
assign o_OP_PHASEDATA = cyc40r_phase_sr_out[19:10];
///////////////////////////////////////////////////////////
////// Phase serialization(send to test reg)
////
reg [8:0] phase_ch6_c2;
assign o_REG_PHASE_CH6_C2 = phase_ch6_c2[0];
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(i_CYCLE_05) phase_ch6_c2 <= cyc15r_previous_phase[8:0];
else begin
phase_ch6_c2[7:0] <= phase_ch6_c2[8:1];
phase_ch6_c2[8] <= 1'b0;
end
end
///////////////////////////////////////////////////////////
////// STATIC STORAGE FOR DEBUG
////
`ifdef IKAOPM_DEBUG
reg [4:0] sim_pg_static_storage_addr_cntr = 5'd0;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(i_CYCLE_10) sim_pg_static_storage_addr_cntr <= 5'd0;
else sim_pg_static_storage_addr_cntr <= sim_pg_static_storage_addr_cntr == 5'd31 ? 5'd0 : sim_pg_static_storage_addr_cntr + 5'd1;
end
reg [19:0] sim_pg_static_storage[0:31];
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
sim_pg_static_storage[sim_pg_static_storage_addr_cntr] <= mrst_n ? cyc18r_current_phase : 20'd0;
end
`endif
endmodule
|
module pg_submdl_fnumrom (
//master clock
input wire i_EMUCLK, //emulator master clock
//clock enable
input wire i_CEN_n, //positive edge clock enable for emulation
input wire [5:0] i_ADDR,
output reg [16:0] o_DATA
);
always @(posedge i_EMUCLK) if(!i_CEN_n) begin
case(i_ADDR)
6'h00: o_DATA <= 17'b010100_010011_1001_1;
6'h01: o_DATA <= 17'b010100_100110_1001_1;
6'h02: o_DATA <= 17'b010100_111001_1001_1;
6'h03: o_DATA <= 17'b010101_001100_0010_1;
6'h04: o_DATA <= 17'b010101_100000_0010_1;
6'h05: o_DATA <= 17'b010101_110100_0010_1;
6'h06: o_DATA <= 17'b010110_001000_1010_1;
6'h07: o_DATA <= 17'b010110_011101_0010_1;
6'h08: o_DATA <= 17'b010110_110010_1010_1;
6'h09: o_DATA <= 17'b010111_000111_1010_1;
6'h0A: o_DATA <= 17'b010111_011101_0011_1;
6'h0B: o_DATA <= 17'b010111_110011_0011_1;
6'h0C: o_DATA <= 17'b000000_000000_0000_0;
6'h0D: o_DATA <= 17'b000000_000000_0000_0;
6'h0E: o_DATA <= 17'b000000_000000_0000_0;
6'h0F: o_DATA <= 17'b000000_000000_0000_0;
6'h10: o_DATA <= 17'b011000_001001_0011_1;
6'h11: o_DATA <= 17'b011000_011111_0011_1;
6'h12: o_DATA <= 17'b011000_110110_1011_1;
6'h13: o_DATA <= 17'b011001_001101_1011_1;
6'h14: o_DATA <= 17'b011001_100101_1011_1;
6'h15: o_DATA <= 17'b011001_111100_0100_1;
6'h16: o_DATA <= 17'b011010_010101_0100_1;
6'h17: o_DATA <= 17'b011010_101101_0100_1;
6'h18: o_DATA <= 17'b011011_000110_1100_1;
6'h19: o_DATA <= 17'b011011_011111_1100_1;
6'h1A: o_DATA <= 17'b011011_111001_0101_1;
6'h1B: o_DATA <= 17'b011100_010011_0101_1;
6'h1C: o_DATA <= 17'b000000_000000_0000_0;
6'h1D: o_DATA <= 17'b000000_000000_0000_0;
6'h1E: o_DATA <= 17'b000000_000000_0000_0;
6'h1F: o_DATA <= 17'b000000_000000_0000_0;
6'h20: o_DATA <= 17'b011100_101101_0101_1;
6'h21: o_DATA <= 17'b011101_001000_1101_1;
6'h22: o_DATA <= 17'b011101_100011_1101_1;
6'h23: o_DATA <= 17'b011101_111110_0110_1;
6'h24: o_DATA <= 17'b011110_011010_0110_1;
6'h25: o_DATA <= 17'b011110_110111_0110_1;
6'h26: o_DATA <= 17'b011111_010011_1110_1;
6'h27: o_DATA <= 17'b011111_110000_0111_1;
6'h28: o_DATA <= 17'b100000_001110_0111_1;
6'h29: o_DATA <= 17'b100000_101100_0111_1;
6'h2A: o_DATA <= 17'b100001_001010_1111_1;
6'h2B: o_DATA <= 17'b100001_101001_1111_1;
6'h2C: o_DATA <= 17'b000000_000000_0000_0;
6'h2D: o_DATA <= 17'b000000_000000_0000_0;
6'h2E: o_DATA <= 17'b000000_000000_0000_0;
6'h2F: o_DATA <= 17'b000000_000000_0000_0;
6'h30: o_DATA <= 17'b100010_001001_1111_1;
6'h31: o_DATA <= 17'b100010_101000_1111_0;
6'h32: o_DATA <= 17'b100011_001001_1111_0;
6'h33: o_DATA <= 17'b100011_101001_1111_0;
6'h34: o_DATA <= 17'b100100_001011_1111_0;
6'h35: o_DATA <= 17'b100100_101100_1111_0;
6'h36: o_DATA <= 17'b100101_001110_0111_0;
6'h37: o_DATA <= 17'b100101_110001_0111_0;
6'h38: o_DATA <= 17'b100110_010100_0111_0;
6'h39: o_DATA <= 17'b100110_111000_0111_0;
6'h3A: o_DATA <= 17'b100111_011100_0111_0;
6'h3B: o_DATA <= 17'b101000_000001_0111_0;
6'h3C: o_DATA <= 17'b000000_000000_0000_0;
6'h3D: o_DATA <= 17'b000000_000000_0000_0;
6'h3E: o_DATA <= 17'b000000_000000_0000_0;
6'h3F: o_DATA <= 17'b000000_000000_0000_0;
endcase
end
endmodule
|
module IKAOPM_reg #(parameter USE_BRAM_FOR_D32REG = 0, parameter FULLY_SYNCHRONOUS = 1) (
//master clock
input wire i_EMUCLK, //emulator master clock
//core internal reset
input wire i_MRST_n,
//internal clock
input wire i_phi1_PCEN_n, //positive edge clock enable for emulation
input wire i_phi1_NCEN_n, //negative edge clock enable for emulation
//timings
input wire i_CYCLE_01,
input wire i_CYCLE_31,
//control/address
input wire i_CS_n,
input wire i_RD_n,
input wire i_WR_n,
input wire i_A0,
//bus data io
input wire [7:0] i_D,
output wire [7:0] o_D,
output wire o_D_OE, //output driver enable
//timer input
input wire i_TIMERA_OVFL,
input wire i_TIMERA_FLAG,
input wire i_TIMERB_FLAG,
//register output
output reg [7:0] o_TEST, //0x01 TEST register
output reg o_CT1,
output reg o_CT2,
output reg o_NE, //0x0F[7] Noise Enable
output reg [4:0] o_NFRQ, //0x0F[4:0] Noise Frequency
output reg [7:0] o_CLKA1, //0x10 Timer A D[9:2]
output reg [1:0] o_CLKA2, //0x11 Timer A D[1:0]
output reg [7:0] o_CLKB, //0x12 Timer B
output wire o_TIMERA_FRST, //0x14 Timer Control
output wire o_TIMERB_FRST, // |
output reg o_TIMERA_RUN, // |
output reg o_TIMERB_RUN, // |
output reg o_TIMERA_IRQ_EN,// |
output reg o_TIMERB_IRQ_EN,// |
output reg [7:0] o_LFRQ, //0x18 LFO frequency
output reg [6:0] o_PMD, //0x19[6:0] D[7] == 1
output reg [6:0] o_AMD, //0x19[6:0] D[7] == 0
output reg [1:0] o_W, //0x1B[1:0] Waveform type
output wire o_LFRQ_UPDATE,
//PG
output wire [6:0] o_KC,
output wire [5:0] o_KF,
output wire [2:0] o_PMS,
output wire [1:0] o_DT2,
output wire [2:0] o_DT1,
output wire [3:0] o_MUL,
//EG
output wire o_KON,
output wire [1:0] o_KS,
output wire [4:0] o_AR,
output wire [4:0] o_D1R,
output wire [4:0] o_D2R,
output wire [3:0] o_RR,
output wire [3:0] o_D1L,
output wire [6:0] o_TL,
output wire [1:0] o_AMS,
//OP
output wire [2:0] o_ALG,
output wire [2:0] o_FL,
//ACC
output wire [1:0] o_RL,
//input data for LSI test via CT pin
input wire i_REG_LFO_CLK,
//input data for LSI test via bus registers
input wire i_REG_PHASE_CH6_C2,
input wire i_REG_ATTENLEVEL_CH8_C2,
input wire [13:0] i_REG_OPDATA
);
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1pcen_n = i_phi1_PCEN_n;
wire phi1ncen_n = i_phi1_NCEN_n;
wire mrst_n = i_MRST_n;
///////////////////////////////////////////////////////////
////// Cycle number
////
//additional cycle bits
reg cycle_02;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cycle_02 <= i_CYCLE_01;
end
///////////////////////////////////////////////////////////
////// Bus/control data inlatch and synchronizer
////
//3.58MHz phiM and 1.79MHz phi1 would be too slow to catch up
//bus transaction speed. So the chip "latch" the input first.
//3-stage DFF chain will synchronize the data then.
//latch outputs
wire [7:0] dbus_inlatch_temp;
wire dreg_rq_inlatch, areg_rq_inlatch;
//Synchronizer DFF
reg dreg_rq_synced0, dreg_rq_synced1, dreg_rq_synced2;
reg areg_rq_synced0, areg_rq_synced1, areg_rq_synced2;
wire data_ld = dreg_rq_synced2;
wire addr_ld = areg_rq_synced2;
always @(posedge i_EMUCLK) begin
if(!phi1ncen_n) begin
if(!mrst_n) begin
dreg_rq_synced0 <= 1'b0;
dreg_rq_synced2 <= 1'b0;
areg_rq_synced0 <= 1'b0;
areg_rq_synced2 <= 1'b0;
end
else begin
//data load
dreg_rq_synced0 <= dreg_rq_inlatch;
dreg_rq_synced2 <= dreg_rq_synced1;
//address load
areg_rq_synced0 <= areg_rq_inlatch;
areg_rq_synced2 <= areg_rq_synced1;
end
end
if(!phi1pcen_n) begin
if(!mrst_n) begin
dreg_rq_synced1 <= 1'b0;
areg_rq_synced1 <= 1'b0;
end
else begin
//data load
dreg_rq_synced1 <= dreg_rq_synced0;
//address load
areg_rq_synced1 <= areg_rq_synced0;
end
end
end
//Stable data bus value; without this, a data value will overwrite a address value on a fast write cycle(6502@8MHz).
//The actual YM2151 is slow, so when the CPU writes a new value, it takes a significant amount of time for the old value
//to change(<20 ns). But an FPGA is fast. So the value has already changed before the address register samples the value.
reg [7:0] dbus_inlatch;
always @(posedge i_EMUCLK) begin
if(!phi1ncen_n) begin
if(!i_MRST_n) begin
dbus_inlatch <= 8'h00;
end
else begin
if(areg_rq_synced1 | dreg_rq_synced1) dbus_inlatch <= dbus_inlatch_temp;
end
end
end
generate
if(FULLY_SYNCHRONOUS == 0) begin : FULLY_SYNCHRONOUS_0_busctrl
wire dbus_inlatch_temp_en = ~|{i_CS_n, i_WR_n};
wire dreg_req_inlatch_set = ~(|{i_CS_n, i_WR_n, ~i_A0, ~mrst_n} | dreg_rq_synced1);
wire dreg_req_inlatch_rst = dreg_rq_synced1 | ~mrst_n;
wire areg_req_inlatch_set = ~(|{i_CS_n, i_WR_n, i_A0, ~mrst_n} | areg_rq_synced1);
wire areg_req_inlatch_rst = areg_rq_synced1 | ~mrst_n;
//D latch
primitive_dlatch #(.WIDTH(8)) u_dbus_inlatch_temp (
.i_EN(dbus_inlatch_temp_en), .i_D(i_D), .o_Q(dbus_inlatch_temp)
);
//SR latch
primitive_srlatch u_dreg_req_inlatch (
.i_S(dreg_req_inlatch_set), .i_R(dreg_req_inlatch_rst), .o_Q(dreg_rq_inlatch)
);
primitive_srlatch u_areg_req_inlatch (
.i_S(areg_req_inlatch_set), .i_R(areg_req_inlatch_rst), .o_Q(areg_rq_inlatch)
);
end
else begin : FULLY_SYNCHRONOUS_1_busctrl
reg [7:0] din_syncchain[0:1];
reg [1:0] cs_n_syncchain, rd_n_syncchain, wr_n_syncchain, a0_syncchain;
always @(posedge i_EMUCLK) begin
din_syncchain[0] <= i_D;
din_syncchain[1] <= din_syncchain[0];
cs_n_syncchain[0] <= i_CS_n;
cs_n_syncchain[1] <= cs_n_syncchain[0];
wr_n_syncchain[0] <= i_WR_n;
wr_n_syncchain[1] <= wr_n_syncchain[0];
a0_syncchain[0] <= i_A0;
a0_syncchain[1] <= a0_syncchain[0];
end
//make alias signals
wire cs_n = cs_n_syncchain[1];
wire wr_n = wr_n_syncchain[1];
wire a0 = a0_syncchain[1];
wire [7:0] din = din_syncchain[1];
wire dbus_inlatch_temp_en = ~|{cs_n, wr_n};
wire dreg_req_inlatch_set = ~(|{cs_n, wr_n, ~a0, ~mrst_n} | dreg_rq_synced1);
wire dreg_req_inlatch_rst = dreg_rq_synced1 | ~mrst_n;
wire areg_req_inlatch_set = ~(|{cs_n, wr_n, a0, ~mrst_n} | areg_rq_synced1);
wire areg_req_inlatch_rst = areg_rq_synced1 | ~mrst_n;
//D latch
primitive_syncdlatch #(.WIDTH(8)) u_dbus_inlatch_temp (
.i_EMUCLK(i_EMUCLK), .i_RST_n(i_MRST_n),
.i_EN(dbus_inlatch_temp_en), .i_D(din), .o_Q(dbus_inlatch_temp)
);
//SR latch
primitive_syncsrlatch u_dreg_req_inlatch (
.i_EMUCLK(i_EMUCLK), .i_RST_n(i_MRST_n),
.i_S(dreg_req_inlatch_set), .i_R(dreg_req_inlatch_rst), .o_Q(dreg_rq_inlatch)
);
primitive_syncsrlatch u_areg_req_inlatch (
.i_EMUCLK(i_EMUCLK), .i_RST_n(i_MRST_n),
.i_S(areg_req_inlatch_set), .i_R(areg_req_inlatch_rst), .o_Q(areg_rq_inlatch)
);
end
endgenerate
///////////////////////////////////////////////////////////
////// Loreg decoder
////
wire reg10_en, reg11_en, reg12_en, reg14_en; //timer related
wire reg01_en; //test register
wire reg0f_en; //noise generator
wire reg19_en; //vibrato
wire reg18_en; //LFO
wire reg1b_en; //GPO
wire reg08_en; //KON register
assign o_LFRQ_UPDATE = reg18_en; //LFO frequency update flag;
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h10)) u_reg10 (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg10_en)
);
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h11)) u_reg11 (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg11_en)
);
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h12)) u_reg12 (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg12_en)
);
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h14)) u_reg14 (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg14_en)
);
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h01)) u_reg01 (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg01_en)
);
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h0f)) u_reg0f (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg0f_en)
);
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h19)) u_reg19 (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg19_en)
);
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h18)) u_reg18 (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg18_en)
);
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h1B)) u_reg1b (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg1b_en)
);
reg_submdl_loreg_decoder #(.TARGET_ADDR(8'h08)) u_reg08 (
.i_EMUCLK(i_EMUCLK), .i_phi1_NCEN_n(phi1ncen_n),
.i_ADDR(dbus_inlatch), .i_ADDR_LD(addr_ld), .i_DATA_LD(data_ld), .o_REG_LD(reg08_en)
);
///////////////////////////////////////////////////////////
////// Hireg temp register, flags, decoder
////
//
// TEMPORARY ADDRESS REGISTER FOR HIREG
//
//hireg temporary address register load enable
wire hireg_addrreg_en = (addr_ld & (dbus_inlatch[7:5] != 3'b000)); //not 000X_XXXX
//hireg "address" temporary register with async reset
reg [7:0] hireg_addr;
always @(posedge i_EMUCLK or negedge mrst_n) begin
if(!mrst_n) begin
hireg_addr <= 8'hFF;
end
else begin
if(!phi1pcen_n) begin
if(hireg_addrreg_en) hireg_addr <= dbus_inlatch;
end
end
end
//hireg address valid flag, reset when the address input is loreg
reg hireg_addr_valid;
always @(posedge i_EMUCLK) begin
if(!phi1ncen_n) begin
hireg_addr_valid <= hireg_addrreg_en | (hireg_addr_valid & ~addr_ld);
end
end
//
// TEMPORARY DATA REGISTER FOR HIREG
//
//hireg temporary data register load enable
wire hireg_datareg_en = data_ld & hireg_addr_valid;
//hireg "data" temporary register with async reset
reg [7:0] hireg_data;
always @(posedge i_EMUCLK or negedge mrst_n) begin
if(!mrst_n) begin
hireg_data <= 8'hFF;
end
else begin
if(!phi1ncen_n) begin
if(hireg_datareg_en) hireg_data <= dbus_inlatch;
end
end
end
//hireg data valid flag, reset when the data input is loreg
reg hireg_data_valid;
always @(posedge i_EMUCLK) begin
if(!phi1pcen_n) begin
hireg_data_valid <= hireg_datareg_en | (hireg_data_valid & ~addr_ld);
end
end
//
// HIREG ADDRESS COUNTER
//
wire [4:0] hireg_addrcntr;
primitive_counter #(.WIDTH(5)) u_hireg_addrcntr (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(1'b1), .i_LD(1'b0), .i_RST(i_CYCLE_31 | ~mrst_n),
.i_D(5'd0), .o_Q(hireg_addrcntr), .o_CO()
);
//
// DECODER
//
reg reg38_3f_en; //PMS[6:4]/AMS[1:0]
reg reg30_37_en; //KF[7:2]
reg reg28_2f_en; //KC[6:0]
reg reg20_27_en; //RL[7:6]/FL[5:3]/CONNECT(algorithm)[2:0]
reg rege0_ff_en; //D1L[7:4]/RR[3:0]
reg regc0_df_en; //DT2[7:6]/D2R[4:0]
reg rega0_bf_en; //AMS-EN[7]/D1R[4:0]
reg reg80_9f_en; //KS[7:6]/AR[4:0]
reg reg60_7f_en; //TL[6:0]
reg reg40_5f_en; //DT1[6:4]/MUL[3:0]
always @(posedge i_EMUCLK) begin
if(!phi1ncen_n) begin
reg38_3f_en <= (hireg_addr[7:3] == 5'b00111) & (hireg_addr[2:0] == hireg_addrcntr[2:0]) & hireg_data_valid;
reg30_37_en <= (hireg_addr[7:3] == 5'b00110) & (hireg_addr[2:0] == hireg_addrcntr[2:0]) & hireg_data_valid;
reg28_2f_en <= (hireg_addr[7:3] == 5'b00101) & (hireg_addr[2:0] == hireg_addrcntr[2:0]) & hireg_data_valid;
reg20_27_en <= (hireg_addr[7:3] == 5'b00100) & (hireg_addr[2:0] == hireg_addrcntr[2:0]) & hireg_data_valid;
rege0_ff_en <= (hireg_addr[7:5] == 3'b111) & (hireg_addr[4:0] == hireg_addrcntr) & hireg_data_valid;
regc0_df_en <= (hireg_addr[7:5] == 3'b110) & (hireg_addr[4:0] == hireg_addrcntr) & hireg_data_valid;
rega0_bf_en <= (hireg_addr[7:5] == 3'b101) & (hireg_addr[4:0] == hireg_addrcntr) & hireg_data_valid;
reg80_9f_en <= (hireg_addr[7:5] == 3'b100) & (hireg_addr[4:0] == hireg_addrcntr) & hireg_data_valid;
reg60_7f_en <= (hireg_addr[7:5] == 3'b011) & (hireg_addr[4:0] == hireg_addrcntr) & hireg_data_valid;
reg40_5f_en <= (hireg_addr[7:5] == 3'b010) & (hireg_addr[4:0] == hireg_addrcntr) & hireg_data_valid;
end
end
///////////////////////////////////////////////////////////
////// Low registers
////
//
// GENERAL STATIC REGISTERS
//
//CT reg output
reg [1:0] ct_reg; //define CT reg
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
o_CT1 <= o_TEST[3] ? i_REG_LFO_CLK : ct_reg[0]; //LSI test purpose
o_CT2 <= ct_reg[1];
end
//reg for KON
reg csm_reg;
reg [6:0] kon_temp_reg;
//timer flag reset
assign o_TIMERA_FRST = (reg14_en & dbus_inlatch[4]) | ~mrst_n;
assign o_TIMERB_FRST = (reg14_en & dbus_inlatch[5]) | ~mrst_n;
always @(posedge i_EMUCLK) begin
if(!phi1pcen_n) begin //positive edge!!
if(!mrst_n) begin
o_TEST <= 8'h0;
ct_reg <= 2'b00;
o_NE <= 1'b0;
o_NFRQ <= 5'h00;
o_CLKA1 <= 8'h0;
o_CLKA2 <= 2'h0;
o_CLKB <= 8'h0;
o_TIMERA_RUN <= 1'b0;
o_TIMERB_RUN <= 1'b0;
o_TIMERA_IRQ_EN <= 1'b0;
o_TIMERB_IRQ_EN <= 1'b0;
o_LFRQ <= 8'h00;
o_PMD <= 7'h00;
o_AMD <= 7'h00;
o_W <= 2'd0;
csm_reg <= 1'b0;
kon_temp_reg <= 7'b0000_000;
end
else begin
o_TEST <= reg01_en ? dbus_inlatch : o_TEST;
ct_reg <= reg1b_en ? dbus_inlatch[7:6] : ct_reg;
o_NE <= reg0f_en ? dbus_inlatch[7] : o_NE;
o_NFRQ <= reg0f_en ? dbus_inlatch[4:0] : o_NFRQ;
o_CLKA1 <= reg10_en ? dbus_inlatch : o_CLKA1;
o_CLKA2 <= reg11_en ? dbus_inlatch[1:0] : o_CLKA2;
o_CLKB <= reg12_en ? dbus_inlatch : o_CLKB;
o_TIMERA_RUN <= reg14_en ? dbus_inlatch[0] : o_TIMERA_RUN;
o_TIMERB_RUN <= reg14_en ? dbus_inlatch[1] : o_TIMERB_RUN;
o_TIMERA_IRQ_EN <= reg14_en ? dbus_inlatch[2] : o_TIMERA_IRQ_EN;
o_TIMERB_IRQ_EN <= reg14_en ? dbus_inlatch[3] : o_TIMERB_IRQ_EN;
o_LFRQ <= reg18_en ? dbus_inlatch : o_LFRQ;
o_PMD <= reg19_en ? (dbus_inlatch[7] == 1'b1) ? dbus_inlatch[6:0] : o_PMD :
o_PMD;
o_AMD <= reg19_en ? (dbus_inlatch[7] == 1'b0) ? dbus_inlatch[6:0] : o_AMD :
o_AMD;
o_W <= reg1b_en ? dbus_inlatch[1:0] : o_W;
csm_reg <= reg14_en ? dbus_inlatch[7] : csm_reg;
kon_temp_reg <= reg08_en ? dbus_inlatch[6:0] : kon_temp_reg;
end
end
end
//
// DYNAMIC REGISTERS FOR KON
//
reg ch_equal, force_kon;
always @(posedge i_EMUCLK) begin
if(!phi1ncen_n) begin
ch_equal <= hireg_addrcntr == {2'b00, kon_temp_reg[2:0]}; //channel number
if(!mrst_n) force_kon <= 1'b0;
else begin if(cycle_02) force_kon <= i_TIMERA_OVFL & csm_reg; end
end
end
/*
define 8-bit, 4-line, total 32-stage shift register(8*4)
Data flows from LSB to MSB. The LSB of each line has a multiplexer
to choose data to be written in the LSB register.
When ch_equal is activated, new data from temporary kon reg is loaded.
If not, it gets data from the MSB of the previous "line"
*/
reg kon_m1, kon_m2, kon_c1, kon_c2;
reg [7:0] kon_sr_0_7, kon_sr_8_15, kon_sr_16_23, kon_sr_24_31;
always @(posedge i_EMUCLK) begin
if(!phi1ncen_n) begin
kon_m1 <= kon_temp_reg[3]; kon_m2 <= kon_temp_reg[5];
kon_c1 <= kon_temp_reg[4]; kon_c2 <= kon_temp_reg[6];
//line 1
kon_sr_0_7[0] <= ch_equal ? kon_m1 : (kon_sr_24_31[7] & mrst_n);
kon_sr_0_7[7:1] <= kon_sr_0_7[6:0];
//line 2
kon_sr_8_15[0] <= ch_equal ? kon_c2 : kon_sr_0_7[7];
kon_sr_8_15[7:1] <= kon_sr_8_15[6:0];
//line 3
kon_sr_16_23[0] <= ch_equal ? kon_c1 : kon_sr_8_15[7];
kon_sr_16_23[7:1] <= kon_sr_16_23[6:0];
//line 4
kon_sr_24_31[0] <= ch_equal ? kon_m2 : kon_sr_16_23[7];
kon_sr_24_31[7:1] <= kon_sr_24_31[6:0];
end
end
assign o_KON = kon_sr_24_31[5] | force_kon;
///////////////////////////////////////////////////////////
////// High registers
////
//
// SR8 REGISTERS
//
/*
8-stage sr for the data below:
Address 38_3f : PMS[6:4] AMS[1:0]
Address 30_37 : KF[7:2]
Address 28_2f : KC[6:0]
Address 20_27 : RL[7:6] FL[5:3] CONNECT(algorithm)[2:0]
*/
//define in/out port
wire [2:0] pms_out; //phase modulation sensitivity
wire [1:0] ams_out; //amplitude modulation sensitivity
wire [5:0] kf_out; //key fraction
wire [6:0] kc_out; //key code
wire [2:0] fl_out; //feedback level
wire [2:0] alg_out; //algorithm type
wire [1:0] rl_out; //right/left channel enable
wire [2:0] pms_in = !mrst_n ? 3'd0 : reg38_3f_en ? hireg_data[6:4] : pms_out;
wire [1:0] ams_in = !mrst_n ? 2'd0 : reg38_3f_en ? hireg_data[1:0] : ams_out;
wire [5:0] kf_in = !mrst_n ? 6'd0 : reg30_37_en ? hireg_data[7:2] : kf_out;
wire [6:0] kc_in = !mrst_n ? 7'd0 : reg28_2f_en ? hireg_data[6:0] : kc_out;
wire [2:0] fl_in = !mrst_n ? 3'd0 : reg20_27_en ? hireg_data[5:3] : fl_out;
wire [2:0] alg_in = !mrst_n ? 3'd0 : reg20_27_en ? hireg_data[2:0] : alg_out;
wire [1:0] rl_in = !mrst_n ? 2'b00 : reg20_27_en ? hireg_data[7:6] : rl_out;
primitive_sr #(.WIDTH(3), .LENGTH(8), .TAP(0)) u_pms_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(pms_in), .o_Q_TAP(o_PMS), .o_Q_LAST(pms_out));
primitive_sr #(.WIDTH(2), .LENGTH(8), .TAP(8)) u_ams_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(ams_in), .o_Q_TAP(), .o_Q_LAST(ams_out));
primitive_sr #(.WIDTH(6), .LENGTH(8), .TAP(1)) u_kf_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(kf_in), .o_Q_TAP(o_KF), .o_Q_LAST(kf_out));
primitive_sr #(.WIDTH(7), .LENGTH(8), .TAP(1)) u_kc_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(kc_in), .o_Q_TAP(o_KC), .o_Q_LAST(kc_out));
primitive_sr #(.WIDTH(3), .LENGTH(8), .TAP(7)) u_fl_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(fl_in), .o_Q_TAP(o_FL), .o_Q_LAST(fl_out));
primitive_sr #(.WIDTH(3), .LENGTH(8), .TAP(4)) u_alg_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(alg_in), .o_Q_TAP(o_ALG), .o_Q_LAST(alg_out));
primitive_sr #(.WIDTH(2), .LENGTH(8), .TAP(5)) u_rl_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(rl_in), .o_Q_TAP(o_RL), .o_Q_LAST(rl_out));
//
// SR32 REGISTERS
//
/*
32-stage sr for the data below:
Address e0_ff : D1L[7:4] RR[3:0]
Address c0_df : DT2[7:6] D2R[4:0]
Address a0_bf : AMS-EN[7] D1R[4:0]
Address 80_9f : KS[7:6] AR[4:0]
Address 60_7f : TL[6:0]
Address 40_5f : DT1[6:4] MUL[3:0]
*/
//define in/out port
wire [1:0] dt2_out; //detune2
wire [2:0] dt1_out; //detune1
wire [3:0] mul_out; //phase multuply
wire [4:0] ar_out; //attack rate
wire [4:0] d2r_out; //second decay rate
wire [4:0] d1r_out; //first decay rate
wire [3:0] rr_out; //release rate
wire [3:0] d1l_out; //first decay level
wire amen_out; //amplitude modulation enable
wire [1:0] ks_out; //key scale
wire [6:0] tl_out; //total level
generate
if(USE_BRAM_FOR_D32REG == 0) begin: d32reg_mode_sr
wire [1:0] dt2_in = !mrst_n ? 2'd0 : regc0_df_en ? hireg_data[7:6] : dt2_out;
wire [2:0] dt1_in = !mrst_n ? 3'd0 : reg40_5f_en ? hireg_data[6:4] : dt1_out;
wire [3:0] mul_in = !mrst_n ? 4'd0 : reg40_5f_en ? hireg_data[3:0] : mul_out;
wire [4:0] ar_in = !mrst_n ? 5'd0 : reg80_9f_en ? hireg_data[4:0] : ar_out;
wire [4:0] d1r_in = !mrst_n ? 5'd0 : rega0_bf_en ? hireg_data[4:0] : d1r_out;
wire [4:0] d2r_in = !mrst_n ? 5'd0 : regc0_df_en ? hireg_data[4:0] : d2r_out;
wire [3:0] rr_in = !mrst_n ? 4'd0 : rege0_ff_en ? hireg_data[3:0] : rr_out;
wire [3:0] d1l_in = !mrst_n ? 4'd0 : rege0_ff_en ? hireg_data[7:4] : d1l_out;
wire amen_in = !mrst_n ? 1'b0 : rega0_bf_en ? hireg_data[7] : amen_out;
wire [1:0] ks_in = !mrst_n ? 2'd0 : reg80_9f_en ? hireg_data[7:6] : ks_out;
wire [6:0] tl_in = !mrst_n ? 7'd0 : reg60_7f_en ? hireg_data[6:0] : tl_out;
primitive_sr #(.WIDTH(2), .LENGTH(32), .TAP(27)) u_dt2_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(dt2_in), .o_Q_TAP(o_DT2), .o_Q_LAST(dt2_out));
primitive_sr #(.WIDTH(3), .LENGTH(32), .TAP(32)) u_dt1_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(dt1_in), .o_Q_TAP(o_DT1), .o_Q_LAST(dt1_out));
primitive_sr #(.WIDTH(4), .LENGTH(32), .TAP(32)) u_mul_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(mul_in), .o_Q_TAP(o_MUL), .o_Q_LAST(mul_out));
primitive_sr #(.WIDTH(5), .LENGTH(32), .TAP(32)) u_ar_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(ar_in), .o_Q_TAP(o_AR), .o_Q_LAST(ar_out));
primitive_sr #(.WIDTH(5), .LENGTH(32), .TAP(32)) u_d1r_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(d1r_in), .o_Q_TAP(o_D1R), .o_Q_LAST(d1r_out));
primitive_sr #(.WIDTH(5), .LENGTH(32), .TAP(32)) u_d2r_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(d2r_in), .o_Q_TAP(o_D2R), .o_Q_LAST(d2r_out));
primitive_sr #(.WIDTH(4), .LENGTH(32), .TAP(32)) u_rr_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(rr_in), .o_Q_TAP(o_RR), .o_Q_LAST(rr_out));
primitive_sr #(.WIDTH(4), .LENGTH(32), .TAP(32)) u_d1l_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(d1l_in), .o_Q_TAP(o_D1L), .o_Q_LAST(d1l_out));
primitive_sr #(.WIDTH(1), .LENGTH(32), .TAP(32)) u_amen_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(amen_in), .o_Q_TAP(), .o_Q_LAST(amen_out));
primitive_sr #(.WIDTH(2), .LENGTH(32), .TAP(32)) u_ks_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(ks_in), .o_Q_TAP(o_KS), .o_Q_LAST(ks_out));
primitive_sr #(.WIDTH(7), .LENGTH(32), .TAP(32)) u_tl_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(tl_in), .o_Q_TAP(o_TL), .o_Q_LAST(tl_out));
assign o_AMS = ams_out & {2{amen_out}};
end
else begin: d32reg_mode_bram
wire [1:0] dt2_in = !mrst_n ? 2'd0 : regc0_df_en ? hireg_data[7:6] : dt2_out;
wire [2:0] dt1_in = !mrst_n ? 3'd0 : hireg_data[6:4];
wire [3:0] mul_in = !mrst_n ? 4'd0 : hireg_data[3:0];
wire [4:0] ar_in = !mrst_n ? 5'd0 : hireg_data[4:0];
wire [4:0] d1r_in = !mrst_n ? 5'd0 : hireg_data[4:0];
wire [4:0] d2r_in = !mrst_n ? 5'd0 : hireg_data[4:0];
wire [3:0] rr_in = !mrst_n ? 4'd0 : hireg_data[3:0];
wire [3:0] d1l_in = !mrst_n ? 4'd0 : hireg_data[7:4];
wire amen_in = !mrst_n ? 1'b0 : hireg_data[7] ;
wire [1:0] ks_in = !mrst_n ? 2'd0 : hireg_data[7:6];
wire [6:0] tl_in = !mrst_n ? 7'd0 : hireg_data[6:0];
wire d32reg_cntr_rst = i_CYCLE_31 | ~mrst_n;
primitive_sr #(.WIDTH(2), .LENGTH(32), .TAP(27)) u_dt2_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(dt2_in), .o_Q_TAP(o_DT2), .o_Q_LAST(dt2_out));
primitive_sr_bram #(.WIDTH(3), .LENGTH(32), .TAP(32)) u_dt1_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(reg40_5f_en), .i_D(dt1_in), .o_Q_TAP(o_DT1));
primitive_sr_bram #(.WIDTH(4), .LENGTH(32), .TAP(32)) u_mul_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(reg40_5f_en), .i_D(mul_in), .o_Q_TAP(o_MUL));
primitive_sr_bram #(.WIDTH(5), .LENGTH(32), .TAP(32)) u_ar_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(reg80_9f_en), .i_D(ar_in), .o_Q_TAP(o_AR));
primitive_sr_bram #(.WIDTH(5), .LENGTH(32), .TAP(32)) u_d1r_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(rega0_bf_en), .i_D(d1r_in), .o_Q_TAP(o_D1R));
primitive_sr_bram #(.WIDTH(5), .LENGTH(32), .TAP(32)) u_d2r_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(regc0_df_en), .i_D(d2r_in), .o_Q_TAP(o_D2R));
primitive_sr_bram #(.WIDTH(4), .LENGTH(32), .TAP(32)) u_rr_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(rege0_ff_en), .i_D(rr_in), .o_Q_TAP(o_RR));
primitive_sr_bram #(.WIDTH(4), .LENGTH(32), .TAP(32)) u_d1l_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(rege0_ff_en), .i_D(d1l_in), .o_Q_TAP(o_D1L));
primitive_sr_bram #(.WIDTH(1), .LENGTH(32), .TAP(32)) u_amen_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(rega0_bf_en), .i_D(amen_in), .o_Q_TAP(amen_out));
primitive_sr_bram #(.WIDTH(2), .LENGTH(32), .TAP(32)) u_ks_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(reg80_9f_en), .i_D(ks_in), .o_Q_TAP(o_KS));
primitive_sr_bram #(.WIDTH(7), .LENGTH(32), .TAP(32)) u_tl_reg
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_CNTRRST(d32reg_cntr_rst), .i_WR(reg60_7f_en), .i_D(tl_in), .o_Q_TAP(o_TL));
assign o_AMS = ams_out & {2{amen_out}};
end
endgenerate
///////////////////////////////////////////////////////////
////// Write busy flag timer
////
//write busy timer
reg busycntr_cnt;
wire busycntr_ovfl;
primitive_counter #(.WIDTH(5)) u_busycntr (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(busycntr_cnt), .i_LD(1'b0), .i_RST(~mrst_n),
.i_D(5'd0), .o_Q(), .o_CO(busycntr_ovfl)
);
//write busy flag
reg write_busy;
always @(posedge i_EMUCLK) begin
if(!phi1pcen_n) write_busy <= (write_busy & ~(~mrst_n | busycntr_ovfl)) | data_ld;
if(!phi1ncen_n) busycntr_cnt <= write_busy;
end
///////////////////////////////////////////////////////////
////// Read-only register multiplexer
////
wire [7:0] internal_data = o_TEST[7] ? {i_REG_PHASE_CH6_C2, i_REG_ATTENLEVEL_CH8_C2, i_REG_OPDATA[13:8]} : i_REG_OPDATA[7:0];
assign o_D = o_TEST[6] ? internal_data : {write_busy, 5'b00000, i_TIMERB_FLAG, i_TIMERA_FLAG};
assign o_D_OE = ~|{~mrst_n, ~i_A0, i_RD_n, i_CS_n};
endmodule
|
module reg_submdl_loreg_decoder #(parameter TARGET_ADDR = 8'h00 ) (
//master clock
input wire i_EMUCLK, //emulator master clock
//internal clock
input wire i_phi1_NCEN_n, //negative edge clock enable for emulation
//address to be decoded
input wire [7:0] i_ADDR,
input wire i_ADDR_LD,
input wire i_DATA_LD,
output wire o_REG_LD
);
reg loreg_addr_valid;
always @(posedge i_EMUCLK) begin
if(!i_phi1_NCEN_n) begin
loreg_addr_valid <= ((TARGET_ADDR == i_ADDR) & i_ADDR_LD) | (loreg_addr_valid & ~i_ADDR_LD);
end
end
assign o_REG_LD = loreg_addr_valid & i_DATA_LD;
endmodule
|
module IKAOPM_eg (
//master clock
input wire i_EMUCLK, //emulator master clock
//core internal reset
input wire i_MRST_n,
//internal clock
input wire i_phi1_PCEN_n, //positive edge clock enable for emulation
input wire i_phi1_NCEN_n, //negative edge clock enable for emulation
//timings
input wire i_CYCLE_03,
input wire i_CYCLE_31,
input wire i_CYCLE_00_16,
input wire i_CYCLE_01_TO_16,
//register data
input wire i_KON, //key on
input wire [1:0] i_KS, //key scale
input wire [4:0] i_AR, //attack rate
input wire [4:0] i_D1R, //first decay rate
input wire [4:0] i_D2R, //second decay rate
input wire [3:0] i_RR, //release rate
input wire [3:0] i_D1L, //first decay level
input wire [6:0] i_TL, //total level
input wire [1:0] i_AMS, //amplitude modulation sensitivity
input wire [7:0] i_LFA, //amplitude modulation from LFO
input wire i_TEST_D0, //test register
input wire i_TEST_D5,
//input data
input wire [4:0] i_EG_PDELTA_SHIFT_AMOUNT,
//output data
output wire o_PG_PHASE_RST,
output wire [9:0] o_OP_ATTENLEVEL, //envelope level
output wire o_NOISE_ATTENLEVEL, //envelope level(for noise module)
output wire o_REG_ATTENLEVEL_CH8_C2 //noise envelope level
);
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1pcen_n = i_phi1_PCEN_n;
wire phi1ncen_n = i_phi1_NCEN_n;
wire mrst_n = i_MRST_n;
///////////////////////////////////////////////////////////
////// Cycle number
////
//additional cycle bits
reg cycle_01_17;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cycle_01_17 <= i_CYCLE_00_16;
end
///////////////////////////////////////////////////////////
////// Third sample flag
////
reg samplecntr_rst;
wire [1:0] samplecntr_q;
reg third_sample;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
samplecntr_rst <= samplecntr_q[1];
third_sample <= samplecntr_q[1] | i_TEST_D0;
end
primitive_counter #(.WIDTH(2)) u_samplecntr (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(i_CYCLE_31), .i_LD(1'b0), .i_RST((samplecntr_rst & i_CYCLE_31) | ~mrst_n),
.i_D(2'd0), .o_Q(samplecntr_q), .o_CO()
);
///////////////////////////////////////////////////////////
////// Attenuation rate generator
////
/*
YM2151 uses serial counter and shift register to get the rate below
timecntr = X_0000_00000_00000 = 0
timecntr = X_1000_00000_00000 = 14
timecntr = X_X100_00000_00000 = 13
timecntr = X_XX10_00000_00000 = 12
...
timecntr = X_XXXX_XXXXX_XXX10 = 2
timecntr = X_XXXX_XXXXX_XXXX1 = 1
I used parallel 4-bit counter instead of the shift register to save
FPGA resources.
*/
reg mrst_z;
reg [1:0] timecntr_adder;
reg [14:0] timecntr_sr; //this sr can hold 15-bit integer
reg onebit_det, mrst_dlyd;
reg [3:0] conseczerobitcntr;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
//adder
timecntr_adder <= mrst_n ? (((third_sample & i_CYCLE_01_TO_16) & (cycle_01_17 | timecntr_adder[1])) + timecntr_sr[0]) :
2'd0;
//sr
timecntr_sr[14] <= timecntr_adder[0];
timecntr_sr[13:0] <= timecntr_sr[14:1];
//consecutive zero bits counter
mrst_z <= ~mrst_n; //delay master reset, to synchronize the reset timing with timecntr_adder register
if(mrst_z | cycle_01_17) begin
onebit_det <= 1'b0;
conseczerobitcntr <= 4'd1; //start from 1
end
else begin
if(!onebit_det) begin
if(timecntr_adder[0]) begin
onebit_det <= 1'b1;
conseczerobitcntr <= conseczerobitcntr;
end
else begin
onebit_det <= 1'b0;
conseczerobitcntr <= (conseczerobitcntr == 4'd14) ? 4'd0 : conseczerobitcntr + 4'd1; //max 14
end
end
end
end
`ifdef IKAOPM_DEBUG
reg [15:0] debug_timecntr;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(cycle_01_17) debug_timecntr <= {timecntr_adder[0], timecntr_sr}; //timecounter parallel output
end
`endif
reg [1:0] envcntr;
reg [3:0] attenrate;
always @(posedge i_EMUCLK) if(!phi1pcen_n) begin //positive edge!!!!
if(third_sample & ~i_CYCLE_01_TO_16 & cycle_01_17) begin
envcntr <= timecntr_sr[2:1];
attenrate <= conseczerobitcntr;
end
end
///////////////////////////////////////////////////////////
////// Previous KON shift register
////
/*
Note that the cycle numbers below are "elapsed" cycle,
NOT the master cycle counter value
previous KON data
|----------(32 stages)---------|
i_KON(cyc5) -> (cyc6 - cyc9) -+> (cyc10 - cyc37) -> (cyc6 - cyc9) -> -o|¯¯¯¯\
| | AND )---
+------------------------------------> --|____/
positive edge detector
*/
//These shift registers holds KON values from previous 32 cycles
reg [3:0] cyc6r_cyc9r_kon_current_dlyline; //outer process delay compensation(4 cycles)
reg [27:0] cyc10r_cyc37r_kon_previous; //previous KON values
reg [3:0] cyc6r_cyc9r_kon_previous; //delayed concurrently with the current kon delay line
wire cyc9r_kon_current = cyc6r_cyc9r_kon_current_dlyline[3]; //current kon value
wire cyc9r_kon_detected = ~cyc6r_cyc9r_kon_previous[3] & cyc9r_kon_current; //prev=0, curr=1, new kon detected
assign o_PG_PHASE_RST = cyc9r_kon_detected;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc6r_cyc9r_kon_current_dlyline[0] <= i_KON;
cyc6r_cyc9r_kon_current_dlyline[3:1] <= cyc6r_cyc9r_kon_current_dlyline[2:0];
cyc10r_cyc37r_kon_previous[0] <= cyc6r_cyc9r_kon_current_dlyline[3];
cyc10r_cyc37r_kon_previous[27:1] <= cyc10r_cyc37r_kon_previous[26:0];
cyc6r_cyc9r_kon_previous[0] <= cyc10r_cyc37r_kon_previous[27];
cyc6r_cyc9r_kon_previous[3:1] <= cyc6r_cyc9r_kon_previous[2:0];
end
///////////////////////////////////////////////////////////
////// Cycle 6 to 37: Envelope state machine
////
/*
Note that the cycle numbers below are "elapsed" cycle,
NOT the master cycle counter value
Envelope state machine holds the states of 32 operators
(state update)
|
V
(cyc6 - cyc9) -> (cyc10 - cyc37) (loop to cyc 6, total 32 stages)
*/
localparam ATTACK = 2'd0;
localparam FIRST_DECAY = 2'd1;
localparam SECOND_DECAY = 2'd2;
localparam RELEASE = 2'd3;
//
// combinational part
//
//flags and prev state for FSM, get the values from the last step of the attenuation level SR
wire cyc10c_first_decay_end;
wire cyc10c_prevatten_min;
wire cyc10c_prevatten_max;
//
// register part
//
//total 32 stages to store states of all operators
reg [1:0] cyc6r_cyc9r_envstate_previous[0:3]; //4 stages
reg [1:0] cyc10r_envstate_current; //1 stage
wire [1:0] cyc37r_envstate_previous; //27 stages
wire [1:0] cyc9r_envstate_previous = cyc6r_cyc9r_envstate_previous[3];
//sr4
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
//if kon detected, make previous envstate ATTACK
cyc6r_cyc9r_envstate_previous[0] <= (~cyc10r_cyc37r_kon_previous[27] & i_KON) ? ATTACK : cyc37r_envstate_previous;
cyc6r_cyc9r_envstate_previous[1] <= cyc6r_cyc9r_envstate_previous[0];
cyc6r_cyc9r_envstate_previous[2] <= cyc6r_cyc9r_envstate_previous[1];
cyc6r_cyc9r_envstate_previous[3] <= cyc6r_cyc9r_envstate_previous[2];
end
//sr27 first stage
primitive_sr #(.WIDTH(2), .LENGTH(27), .TAP(27)) u_cyc11r_cyc37r_envstate_sr
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(cyc10r_envstate_current), .o_Q_TAP(), .o_Q_LAST(cyc37r_envstate_previous));
//state machine
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(!mrst_n) begin
cyc10r_envstate_current <= RELEASE;
end
else begin
if(cyc9r_kon_detected) begin
cyc10r_envstate_current <= ATTACK; //start attack
end
else begin
if(cyc9r_kon_current) begin
case(cyc9r_envstate_previous)
//current state 0: attack
2'd0: begin
if(cyc10c_prevatten_min) begin
cyc10r_envstate_current <= FIRST_DECAY; //start first decay
end
else begin
cyc10r_envstate_current <= ATTACK; //hold state
end
end
//current state 1: first decay
2'd1: begin
if(cyc10c_prevatten_max) begin
cyc10r_envstate_current <= RELEASE; //start release
end
else begin
if(cyc10c_first_decay_end) begin
cyc10r_envstate_current <= SECOND_DECAY; //start second decay
end
else begin
cyc10r_envstate_current <= FIRST_DECAY; //hold state
end
end
end
//current state 2: second decay
2'd2: begin
if(cyc10c_prevatten_max) begin
cyc10r_envstate_current <= RELEASE; //start release
end
else begin
cyc10r_envstate_current <= SECOND_DECAY; //hold state
end
end
//current state 3: release
2'd3: begin
cyc10r_envstate_current <= RELEASE; //hold state
end
endcase
end
else begin
cyc10r_envstate_current <= RELEASE; //key off -> start release
end
end
end
end
///////////////////////////////////////////////////////////
////// Attenuation level preprocessing
////// Cycle 8: EG param/KS latch
////
//
// combinational part
//
reg [4:0] cyc8c_egparam;
always @(*) begin
if(!mrst_n) begin
cyc8c_egparam = 5'd31;
end
else begin
case(cyc6r_cyc9r_envstate_previous[1])
ATTACK: cyc8c_egparam = i_AR;
FIRST_DECAY: cyc8c_egparam = i_D1R;
SECOND_DECAY: cyc8c_egparam = i_D2R;
RELEASE: cyc8c_egparam = {i_RR, 1'b1};
endcase
end
end
//
// register part
//
reg [4:0] cyc8r_egparam;
reg cyc8r_egparam_zero;
reg [3:0] cyc8r_d1l;
reg [4:0] cyc8r_keyscale;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc8r_egparam <= cyc8c_egparam;
cyc8r_egparam_zero <= cyc8c_egparam == 5'd0;
cyc8r_d1l <= i_D1L;
case(i_KS)
2'd0: cyc8r_keyscale <= (cyc8c_egparam == 5'd0) ? 5'd0 : {3'b000, i_EG_PDELTA_SHIFT_AMOUNT[4:3]};
2'd1: cyc8r_keyscale <= {2'b00, i_EG_PDELTA_SHIFT_AMOUNT[4:2]};
2'd2: cyc8r_keyscale <= {1'b0, i_EG_PDELTA_SHIFT_AMOUNT[4:1]};
2'd3: cyc8r_keyscale <= i_EG_PDELTA_SHIFT_AMOUNT;
endcase
end
///////////////////////////////////////////////////////////
////// Attenuation level preprocessing
////// Cycle 9: apply KS
////
//
// combinational part
//
wire [6:0] cyc9c_egparam_scaled_adder = {cyc8r_egparam, 1'b0} + {1'b0, cyc8r_keyscale};
wire [9:0] cyc40r_attenlevel_previous; //feedback from the last stage of the SR
//
// register part
//
reg cyc9r_egparam_zero;
reg [5:0] cyc9r_egparam_scaled;
reg cyc9r_egparam_scaled_fullrate;
reg [3:0] cyc9r_d1l;
reg cyc9r_third_sample;
reg [1:0] cyc9r_envcntr;
reg [3:0] cyc9r_attenrate;
reg [9:0] cyc9r_attenlevel_previous;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc9r_egparam_zero <= cyc8r_egparam_zero;
cyc9r_egparam_scaled <= cyc9c_egparam_scaled_adder[6] ? 6'd63 : cyc9c_egparam_scaled_adder[5:0]; //saturation
cyc9r_egparam_scaled_fullrate <= cyc9c_egparam_scaled_adder[5:1] == 5'b11111; //eg parameter max
cyc9r_d1l <= cyc8r_d1l;
cyc9r_third_sample <= third_sample;
cyc9r_envcntr <= envcntr;
cyc9r_attenrate <= attenrate;
cyc9r_attenlevel_previous <= cyc40r_attenlevel_previous;
end
///////////////////////////////////////////////////////////
////// Attenuation level preprocessing
////// Cycle 10: make attenuation level delta weight
////
/*
HOW ATTENUATION RATE GENERATOR WORKS:
See "Attenuation rate generator" section. Attenrate value is determined
from the counter value like below:
timecntr = X_0000_00000_00000 = 0
timecntr = X_1000_00000_00000 = 14
timecntr = X_X100_00000_00000 = 13
timecntr = X_XX10_00000_00000 = 12
...
timecntr = X_XXXX_XXXXX_XXX10 = 2
timecntr = X_XXXX_XXXXX_XXXX1 = 1
An attenuation rate of 1 will occur most often, 14 or 0 will occur
least often. Attenuation rate * 4 (2-bit left shift) is added to
the "egparam_scaled" to get the final value.
Therefore, the quadrupled values that should be added to
"egparam_scaled" are:
least often <---- ----> most often
0, 56, 52, 48, 44, 40, 36, 32, 28, 24, 20, 16, 12, 8, 4
If the "egparam_scaled" is NOT 11XXXX, there are three conditions
that can change the envelope value:
1. egparam_scaled != from 6'd48 to 6'd63
egparam_scaled != 6'd0
egparam_rateapplied == from 6'd48 to 6'd51
2. egparam_scaled != from 6'd48 to 6'd63
egparam_rateapplied == 6'd54 or 6'd55
3. egparam_scaled != from 6'd48 to 6'd63
egparam_rateapplied == 6'd57 or 6'd59
These three conditions can be compressed like this:
egparam_scaled != from 6'd48 to 6'd63
egparam_scaled != 6'd0
egparam_rateapplied == 48, 49, 50, 51, 54, 55, 57, 59
Therefore, if "egparam scaled" is 1, this value can change the envelope
level when the rate is "48"
if "egparam_scaled" is 2, this value can change the envelope level when
the rate is "48" or "52"
if 3, the value-changable rate is "48" or "52" or "59"
if 4, the value-changable rate is "44"
The rate "44" appears more often than the sum of the frequency of
occurrence of "48", "52", "59". So, egparam_scaled = 4 can change the
envelope level often, than 1, 2, 3. If the envelope level changes frequently,
the difference between the envelope level of the current sample and the next
sample becomes larger.
INTENSITY AND ENVELOPE DELTA WEIGHT:
*/
//
// combinational part
//
reg cyc10c_envdeltaweight_intensity; //0 = weak, 1 = strong
always @(*) begin
case({cyc9r_egparam_scaled[1:0], cyc9r_envcntr})
4'b00_00: cyc10c_envdeltaweight_intensity = 1'b0;
4'b00_01: cyc10c_envdeltaweight_intensity = 1'b0;
4'b00_10: cyc10c_envdeltaweight_intensity = 1'b0;
4'b00_11: cyc10c_envdeltaweight_intensity = 1'b0;
4'b01_00: cyc10c_envdeltaweight_intensity = 1'b1;
4'b01_01: cyc10c_envdeltaweight_intensity = 1'b0;
4'b01_10: cyc10c_envdeltaweight_intensity = 1'b0;
4'b01_11: cyc10c_envdeltaweight_intensity = 1'b0;
4'b10_00: cyc10c_envdeltaweight_intensity = 1'b1;
4'b10_01: cyc10c_envdeltaweight_intensity = 1'b0;
4'b10_10: cyc10c_envdeltaweight_intensity = 1'b1;
4'b10_11: cyc10c_envdeltaweight_intensity = 1'b0;
4'b11_00: cyc10c_envdeltaweight_intensity = 1'b1;
4'b11_01: cyc10c_envdeltaweight_intensity = 1'b1;
4'b11_10: cyc10c_envdeltaweight_intensity = 1'b1;
4'b11_11: cyc10c_envdeltaweight_intensity = 1'b0;
endcase
end
wire [5:0] cyc10c_egparam_rateapplied = cyc9r_egparam_scaled + {cyc9r_attenrate, 2'b00}; //discard carry
//first decay end, compare cyc9r_attenlevel_previous[9:4] with {(cyc9r_d1l == 4'd15), cyc9r_d1l, 1'b0} <- idk why
assign cyc10c_first_decay_end = cyc9r_attenlevel_previous[9:4] == {(cyc9r_d1l == 4'd15), cyc9r_d1l, 1'b0}; //==? {(cyc9r_d1l == 4'd15), cyc9r_d1l, 1'b0, 4'bXXXX};
//attenuation level is min(loud)
assign cyc10c_prevatten_min = cyc9r_attenlevel_previous == 10'd0;
//attenuation level is around max(quiet), get cyc9r_attenlevel_previous[9:4] only. [3:0] don't care
assign cyc10c_prevatten_max = cyc9r_attenlevel_previous >= 10'd1008; //==? 10'b11_1111_xxxx;
//
// register part
//
//envelope delta weight
reg [3:0] cyc10r_envdeltaweight; //lv4, lv3, lv2, lv1
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
//only works every third sample
if(cyc9r_third_sample) begin
//if egparam_scaled == 1111XX
if (cyc9r_egparam_scaled[5:2] == 4'b1111) cyc10r_envdeltaweight <= cyc10c_envdeltaweight_intensity ? 4'b1000 : 4'b1000;
//if egparam_scaled == 1110XX
else if(cyc9r_egparam_scaled[5:2] == 4'b1110) cyc10r_envdeltaweight <= cyc10c_envdeltaweight_intensity ? 4'b1000 : 4'b0100;
//if egparam_scaled == 1101XX
else if(cyc9r_egparam_scaled[5:2] == 4'b1101) cyc10r_envdeltaweight <= cyc10c_envdeltaweight_intensity ? 4'b0100 : 4'b0010;
//if egparam_scaled == 1100XX
else if(cyc9r_egparam_scaled[5:2] == 4'b1100) cyc10r_envdeltaweight <= cyc10c_envdeltaweight_intensity ? 4'b0010 : 4'b0001;
//else, not 11XXXX
else begin
if(cyc9r_egparam_zero) begin
cyc10r_envdeltaweight <= 4'b0000;
end
else begin
if(cyc9r_egparam_scaled != 6'd0 &
|{cyc10c_egparam_rateapplied == 6'd59, cyc10c_egparam_rateapplied == 6'd57,
cyc10c_egparam_rateapplied == 6'd55, cyc10c_egparam_rateapplied == 6'd54,
cyc10c_egparam_rateapplied == 6'd51, cyc10c_egparam_rateapplied == 6'd50,
cyc10c_egparam_rateapplied == 6'd49, cyc10c_egparam_rateapplied == 6'd48}) begin
cyc10r_envdeltaweight <= 4'b0001;
end
else begin
cyc10r_envdeltaweight <= 4'b0000;
end
end
end
end
else begin
cyc10r_envdeltaweight <= 4'b0000;
end
end
//misc flags for envelope generator feedback
reg cyc10r_atten_inc; //attenuation level decrement mode(for decay and release)
reg cyc10r_atten_dec; //attenuation level increment mode(for attack)
reg cyc10r_fix_prevatten_max; //force previous attenuation level max(quiet)
reg cyc10r_enable_prevatten; //previous attenuation level enable(disable = 0)
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(!mrst_n) begin
cyc10r_atten_inc <= 1'b0;
cyc10r_atten_dec <= 1'b0;
end
else begin
cyc10r_atten_inc <= ( cyc9r_envstate_previous == FIRST_DECAY &
~cyc9r_kon_detected &
~cyc10c_first_decay_end &
~cyc10c_prevatten_max ) |
((cyc9r_envstate_previous == SECOND_DECAY | cyc9r_envstate_previous == RELEASE) &
~cyc9r_kon_detected &
~cyc10c_prevatten_max );
cyc10r_atten_dec <= ( cyc9r_envstate_previous == ATTACK &
cyc9r_kon_current &
~cyc10c_prevatten_min &
~cyc9r_egparam_scaled_fullrate );
end
cyc10r_fix_prevatten_max <= ( cyc9r_envstate_previous != ATTACK ) & ~cyc9r_kon_detected & cyc10c_prevatten_max;
cyc10r_enable_prevatten <= (~cyc9r_kon_detected &
cyc9r_egparam_scaled_fullrate) |
~cyc9r_egparam_scaled_fullrate;
end
reg [9:0] cyc10r_attenlevel_previous;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc10r_attenlevel_previous <= cyc9r_attenlevel_previous;
end
///////////////////////////////////////////////////////////
////// Cycle 11 to 40: Attenuation level SR storage
////
/*
Note that the cycle numbers below are "elapsed" cycle,
NOT the master cycle counter value
start from cycle 11, this shift register stores all envelopes of 32 operators
<---------(30 stages)----------->
cyc6 -> cyc7 -> cyc8 -> cyc9 -> cyc10 -+> cyc11 -> cyc12 -> (cyc13 - cyc40) --> attenuation value output from cycle 40
| |
+---------------------------------------------+
V |
cyc9 -> cyc10 -+
<--(2 stages)-->
*/
//
// cycle 11: latch weighted delta
//
reg [9:0] cyc11r_attenlevel_previous_gated; //loud: 10'd0, quiet: 10'd1023
reg [9:0] cyc11r_attenlevel_weighted_delta;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(cyc10r_fix_prevatten_max | ~mrst_n) cyc11r_attenlevel_previous_gated <= 10'd1023;
else begin
if(cyc10r_enable_prevatten) cyc11r_attenlevel_previous_gated <= cyc10r_attenlevel_previous;
else cyc11r_attenlevel_previous_gated <= 10'd0;
end
case({cyc10r_atten_dec, cyc10r_atten_inc})
//off, no change
2'b00: cyc11r_attenlevel_weighted_delta <= 10'd0;
//attenuation level increment: quieter
2'b01: cyc11r_attenlevel_weighted_delta <= {6'b000000, cyc10r_envdeltaweight};
//attenuation level decrement: louder
2'b10: begin
case(cyc10r_envdeltaweight)
4'b0001: cyc11r_attenlevel_weighted_delta <= {4'b1111, ~cyc10r_attenlevel_previous[9:5], ~cyc10r_attenlevel_previous[3]};
4'b0010: cyc11r_attenlevel_weighted_delta <= {3'b111, ~cyc10r_attenlevel_previous[9:5], ~cyc10r_attenlevel_previous[3], ~cyc10r_attenlevel_previous[1]};
4'b0100: cyc11r_attenlevel_weighted_delta <= {2'b11, ~cyc10r_attenlevel_previous[9:5], ~cyc10r_attenlevel_previous[3], {2{~cyc10r_attenlevel_previous[2]}}};
4'b1000: cyc11r_attenlevel_weighted_delta <= {1'b1, ~cyc10r_attenlevel_previous[9:5], {4{~cyc10r_attenlevel_previous[4]}}};
default: cyc11r_attenlevel_weighted_delta <= 10'd0;
endcase
end
//invalid, will not happen
2'b11: cyc11r_attenlevel_weighted_delta <= 10'd1023;
endcase
end
//
// cycle 12: add delta
//
reg [9:0] cyc12r_attenlevel_current;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc12r_attenlevel_current <= cyc11r_attenlevel_previous_gated + cyc11r_attenlevel_weighted_delta; //discard carry
end
//
// cycle from 13 to 40: shift register storage
//
//total 32 stages to store all levels, SR 28 stages and the remaining 4 stages from cyc9r to cyc12r
primitive_sr #(.WIDTH(10), .LENGTH(28), .TAP(28)) u_cyc13r_cyc40r_attenlevel_sr
(.i_EMUCLK(i_EMUCLK), .i_CEN_n(phi1ncen_n), .i_D(cyc12r_attenlevel_current), .o_Q_TAP(), .o_Q_LAST(cyc40r_attenlevel_previous));
///////////////////////////////////////////////////////////
////// Attenuation level postprocessing
////// Cycle 40: shift LFA
////
//
// register part
//
reg [9:0] cyc40r_lfa_shifted;
reg cyc40r_force_no_atten;
reg [6:0] cyc40r_tl;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
case(i_AMS)
2'd0: cyc40r_lfa_shifted <= {10'd0};
2'd1: cyc40r_lfa_shifted <= {2'b00, i_LFA};
2'd2: cyc40r_lfa_shifted <= {1'b0, i_LFA, 1'b0};
2'd3: cyc40r_lfa_shifted <= {i_LFA, 2'b00};
endcase
cyc40r_force_no_atten <= i_TEST_D5;
cyc40r_tl <= i_TL;
end
///////////////////////////////////////////////////////////
////// Attenuation level postprocessing
////// Cycle 41: apply LFA/underflow handling
////
//
// combinational part
//
wire [10:0] cyc41c_attenlevel_mod_adder = cyc40r_attenlevel_previous + cyc40r_lfa_shifted;
//
// register part
//
reg [9:0] cyc41r_attenlevel_mod;
reg cyc41r_force_no_atten;
reg [6:0] cyc41r_tl;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc41r_attenlevel_mod <= cyc41c_attenlevel_mod_adder[10] ? 10'd1023 : cyc41c_attenlevel_mod_adder[9:0]; //attenlevel saturation
cyc41r_force_no_atten <= cyc40r_force_no_atten;
cyc41r_tl <= cyc40r_tl;
end
///////////////////////////////////////////////////////////
////// Attenuation level postprocessing
////// Cycle 42: apply TL/underflow handling
////
//
// combinational part
//
wire [10:0] cyc42c_attenlevel_tl_adder = cyc41r_attenlevel_mod + {cyc41r_tl, 3'b000}; //multiply by 8
//
// register part
//
reg [9:0] cyc42r_attenlevel_tl;
reg cyc42r_force_no_atten;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc42r_attenlevel_tl <= cyc42c_attenlevel_tl_adder[10] ? 10'd1023 : cyc42c_attenlevel_tl_adder[9:0]; //attenlevel saturation
cyc42r_force_no_atten <= cyc41r_force_no_atten;
end
///////////////////////////////////////////////////////////
////// Attenuation level postprocessing
////// Cycle 43: apply test bit
////
reg [9:0] cyc43r_attenlevel_final;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
cyc43r_attenlevel_final <= cyc42r_force_no_atten ? 10'd0 : cyc42r_attenlevel_tl; //force attenlevel min(loud)
end
//final value
assign o_OP_ATTENLEVEL = cyc43r_attenlevel_final;
///////////////////////////////////////////////////////////
////// Attenuation level serialization
////
reg [9:0] noise_attenlevel;
assign o_NOISE_ATTENLEVEL = noise_attenlevel[9];
assign o_REG_ATTENLEVEL_CH8_C2 = noise_attenlevel[9];
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(i_CYCLE_03) noise_attenlevel <= cyc43r_attenlevel_final;
else begin
noise_attenlevel[9:1] <= noise_attenlevel[8:0];
noise_attenlevel[0] <= 1'b1;
end
end
///////////////////////////////////////////////////////////
////// STATIC STORAGE FOR DEBUG
////
`ifdef IKAOPM_DEBUG
reg [4:0] sim_attenlevel_static_storage_addr_cntr = 5'd0;
reg [4:0] sim_envstate_static_storage_addr_cntr = 5'd0;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
if(i_CYCLE_03) sim_attenlevel_static_storage_addr_cntr <= 5'd0;
else sim_attenlevel_static_storage_addr_cntr <= sim_attenlevel_static_storage_addr_cntr == 5'd31 ? 5'd0 : sim_attenlevel_static_storage_addr_cntr + 5'd1;
if(i_CYCLE_03) sim_envstate_static_storage_addr_cntr <= 5'd1;
else sim_envstate_static_storage_addr_cntr <= sim_envstate_static_storage_addr_cntr == 5'd31 ? 5'd0 : sim_envstate_static_storage_addr_cntr + 5'd1;
end
reg [9:0] sim_attenlevel_static_storage[0:31];
reg [1:0] sim_envstate_static_storage[0:31];
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
sim_attenlevel_static_storage[sim_attenlevel_static_storage_addr_cntr] <= mrst_n ? ~cyc43r_attenlevel_final : 10'd0;
sim_envstate_static_storage[sim_envstate_static_storage_addr_cntr] <= mrst_n ? cyc10r_envstate_current : 2'd3;
end
`endif
endmodule
|
module IKAOPM_noise (
//master clock
input wire i_EMUCLK, //emulator master clock
//core internal reset
input wire i_MRST_n,
//internal clock
input wire i_phi1_PCEN_n, //positive edge clock enable for emulation
input wire i_phi1_NCEN_n, //negative edge clock enable for emulation
//timings
input wire i_CYCLE_12,
input wire i_CYCLE_15_31,
//register data
input wire [4:0] i_NFRQ,
//noise attenuation level input for muting(atten max detection)
input wire i_NOISE_ATTENLEVEL,
//output data
output wire [13:0] o_ACC_NOISE,
output wire o_LFO_NOISE
);
///////////////////////////////////////////////////////////
////// Clock and reset
////
wire phi1pcen_n = i_phi1_PCEN_n;
wire phi1ncen_n = i_phi1_NCEN_n;
wire mrst_n = i_MRST_n;
///////////////////////////////////////////////////////////
////// Noise frequency tick generator
////
wire [4:0] noise_freqgen_value;
reg noise_update, noise_update_z;
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
noise_update <= (noise_freqgen_value == ~i_NFRQ);
noise_update_z <= noise_update;
end
primitive_counter #(.WIDTH(5)) u_noise_freqgen (
.i_EMUCLK(i_EMUCLK), .i_PCEN_n(phi1pcen_n), .i_NCEN_n(phi1ncen_n),
.i_CNT(i_CYCLE_15_31), .i_LD(1'b0), .i_RST(~mrst_n | (noise_update & i_CYCLE_15_31)),
.i_D(5'd0), .o_Q(noise_freqgen_value), .o_CO()
);
///////////////////////////////////////////////////////////
////// LFSR
////
reg [15:0] noise_lfsr;
reg xor_flag;
wire xor_fdbk = (xor_flag ^ noise_lfsr[2]) | (noise_lfsr == 16'h0000 && xor_flag == 1'b0);
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
noise_lfsr[15] <= !mrst_n ? 1'b0 :
noise_update_z ? xor_fdbk : noise_lfsr[0];
noise_lfsr[14:0] <= noise_lfsr[15:1];
xor_flag <= !mrst_n ? noise_lfsr[0] :
noise_update_z ? noise_lfsr[0] : xor_flag;
end
wire noise_serial = noise_lfsr[1];
assign o_LFO_NOISE = noise_serial;
///////////////////////////////////////////////////////////
////// Noise muting detection
////
reg is_attenlevel_max; //zero detected = attenlevel is not max
always @(posedge i_EMUCLK) if(!phi1ncen_n) begin
is_attenlevel_max <= i_CYCLE_12 ? 1'b1 : (i_NOISE_ATTENLEVEL & is_attenlevel_max);
end
///////////////////////////////////////////////////////////
////// Noise SIPO
////
reg noise_sign_z, noise_sign_zz;
reg [8:0] noise_sipo_sr;
//flags
reg noise_mute;
reg noise_sign;
reg noise_redundant_bit;
reg [8:0] noise_parallel;
always @(posedge i_EMUCLK) begin
if(!phi1ncen_n) begin
noise_sign_z <= noise_sign;
noise_sign_zz <= noise_sign_z;
noise_sipo_sr[0] <= noise_sign_zz ^ ~i_NOISE_ATTENLEVEL;
noise_sipo_sr[8:1] <= noise_sipo_sr[7:0];
end
if(!phi1pcen_n) begin
if(i_CYCLE_12) begin
noise_mute <= is_attenlevel_max; //latch mute flag
noise_sign <= noise_serial; //latch new sign bit
noise_redundant_bit <= noise_sign_z; //latch redundant bits: previous sign bit
noise_parallel <= noise_sipo_sr; //latch parallel output, discard MSB(really)
end
end
end
///////////////////////////////////////////////////////////
////// Make output
////
assign o_ACC_NOISE = noise_mute ? 14'd0 : {{2{noise_redundant_bit}},
noise_parallel,
{3{noise_redundant_bit}}};
endmodule
|
module bv_axi_slave_mem (
clk_core,
rst_x,
// AXI
// write channel
i_awid,
i_awaddr,
i_awlen,
i_awsize,
i_awburst,
i_awlock,
i_awcache,
i_awprot,
i_awvalid,
o_awready,
i_wid,
i_wdata,
i_wstrb,
i_wlast,
i_wvalid,
o_wready,
o_bid,
i_bresp,
o_bvalid,
i_bready,
// read channel
i_arid,
i_araddr,
i_arlen,
i_arsize,
i_arburst,
i_arlock,
i_arcache,
i_arprot,
i_arvalid,
o_arready,
o_rid,
o_rdata,
o_rresp,
o_rlast,
o_rvalid,
i_rready
);
//////////////////////////////////
// parameter definition
//////////////////////////////////
`include "polyphony_axi_def.v"
input clk_core;
input rst_x;
// AXI
// write channel
input [P_AXI_M_AWID-1:0] i_awid;
input [P_AXI_M_AWADDR-1:0] i_awaddr;
input [P_AXI_M_AWLEN-1:0] i_awlen;
input [P_AXI_M_AWSIZE-1:0] i_awsize;
input [P_AXI_M_AWBURST-1:0] i_awburst;
input [P_AXI_M_AWLOCK-1:0] i_awlock;
input [P_AXI_M_AWCACHE-1:0] i_awcache;
input [P_AXI_M_AWPROT-1:0] i_awprot;
input i_awvalid;
output o_awready;
input [P_AXI_M_WID-1:0] i_wid;
input [P_AXI_M_WDATA-1:0] i_wdata;
input [P_AXI_M_WSTRB-1:0] i_wstrb;
input i_wlast;
input i_wvalid;
output o_wready;
output [P_AXI_M_BID-1:0] o_bid;
input [P_AXI_M_BRESP-1:0] i_bresp;
output o_bvalid;
input i_bready;
// read channel
input [P_AXI_M_ARID-1:0] i_arid;
input [P_AXI_M_ARADDR-1:0] i_araddr;
input [P_AXI_M_ARLEN-1:0] i_arlen;
input [P_AXI_M_ARSIZE-1:0] i_arsize;
input [P_AXI_M_ARBURST-1:0] i_arburst;
input [P_AXI_M_ARLOCK-1:0] i_arlock;
input [P_AXI_M_ARCACHE-1:0] i_arcache;
input [P_AXI_M_ARPROT-1:0] i_arprot;
input i_arvalid;
output o_arready;
output [P_AXI_M_RID-1:0] o_rid;
output [P_AXI_M_RDATA-1:0] o_rdata;
output [P_AXI_M_RRESP-1:0] o_rresp;
output o_rlast;
output o_rvalid;
input i_rready;
localparam P_MEM_SIZE='d24;
localparam P_W_IDLE = 0;
localparam P_W_WRITE = 1;
localparam P_W_WAIT = 2;
localparam P_B_IDLE = 0;
localparam P_B_OUT = 1;
localparam P_R_IDLE = 0;
localparam P_R_WAIT = 1;
localparam P_R_OUT = 2;
//////////////////////////////////
// reg
//////////////////////////////////
reg [P_AXI_M_WDATA-1:0] r_mem[(1<<P_MEM_SIZE)-1:0];
reg [3:0] r_w_state;
reg [P_AXI_M_AWLEN-1:0] r_wlen;
reg [3:0] r_r_state;
reg [P_AXI_M_ARLEN-1:0] r_rlen;
reg [3:0] r_b_state;
reg [P_AXI_M_AWADDR-1-P_IB_DATA_WIDTH_POW2:0] r_waddr;
reg [P_AXI_M_ARADDR-1-P_IB_DATA_WIDTH_POW2:0] r_raddr;
`ifdef RANDOM_RVALID
reg r_rand_rvalid;
`endif
//////////////////////////////////
// wire
//////////////////////////////////
wire [P_AXI_M_AWADDR-1-P_IB_DATA_WIDTH_POW2:0] w_waddr;
wire [P_AXI_M_ARADDR-1-P_IB_DATA_WIDTH_POW2:0] w_raddr;
wire w_write;
wire w_end;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_waddr = i_awaddr[P_AXI_M_AWADDR-1:P_IB_DATA_WIDTH_POW2];
assign w_raddr = i_araddr[P_AXI_M_ARADDR-1:P_IB_DATA_WIDTH_POW2];
`ifdef RANDOM_RVALID
assign o_awready = (r_w_state == P_W_IDLE) & r_rand_rvalid;
assign o_wready = (r_w_state == P_W_WRITE) & r_rand_rvalid;
`else
assign o_awready = (r_w_state == P_W_IDLE);
assign o_wready = (r_w_state == P_W_WRITE);
`endif
assign o_bid = 0;
assign o_bresp = 0;
assign o_bvalid = (r_b_state == P_B_OUT);
assign w_write = (r_w_state == P_W_WRITE) & i_wvalid;
assign w_end = (r_w_state == P_W_WRITE) & (r_wlen == 0) & i_wvalid;
assign o_arready = (r_r_state == P_R_IDLE);
assign o_rid = 0;
assign o_rdata = r_mem[r_raddr[P_MEM_SIZE-1:0]];
wire [63:0] w_tmp;
assign w_tmp = r_mem[r_raddr[P_MEM_SIZE-1:0]];
assign o_rresp = 0;
assign o_rlast = (r_rlen == 0);
`ifdef RANDOM_RVALID
assign o_rvalid = (r_r_state == P_R_OUT) & r_rand_rvalid;
`else
assign o_rvalid = (r_r_state == P_R_OUT);
`endif
task memory_clear;
integer i;
begin
for (i=0;i<1<<P_MEM_SIZE;i=i+1) r_mem[i] = {P_AXI_M_WDATA{1'b1}};
end
endtask
task memory_clear_random;
integer i;
begin
for (i=0;i<1<<P_MEM_SIZE;i=i+1) r_mem[i] = {$random,$random};
end
endtask
//////////////////////////////////
// always
//////////////////////////////////
genvar gi;
generate for (gi=0;gi<P_AXI_M_WDATA/8;gi=gi+1) begin
always @(posedge clk_core) begin
if (w_write) begin
if (i_wstrb[gi]) r_mem[r_waddr[P_MEM_SIZE-1:0]][(gi+1)*8-1:gi*8] = i_wdata[(gi+1)*8-1:gi*8];
// $display("write %d %x %x %x %x %x",gi,{r_waddr,3'b0},r_waddr,i_axi_mw.wdata[(gi+1)*8-1:gi*8],i_axi_mw.wdata,r_mem[r_waddr[P_MEM_SIZE-1:0]][(gi+1)*8-1:gi*8]);
end
end
end
endgenerate
wire w_awvalid;
assign w_awvalid = i_awvalid;
wire w_wvalid;
assign w_wvalid = i_wvalid;
wire w_wlast;
assign w_wlast = i_wlast;
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_w_state <= P_W_IDLE;
end else begin
case (r_w_state)
P_W_IDLE: begin
`ifdef RANDOM_RVALID
if (i_awvalid & r_rand_rvalid) begin
`else
if (i_awvalid) begin
`endif
r_wlen <= i_awlen;
//r_waddr <= i_axi_mw.awaddr[P_AXI_M_AWADDR-1:2];
r_waddr <= w_waddr;
r_w_state <= P_W_WRITE;
end
end
P_W_WRITE: begin
`ifdef RANDOM_RVALID
if (i_wvalid & r_rand_rvalid) begin
`else
if (i_wvalid) begin
`endif
r_waddr <= r_waddr + 1;
r_wlen <= r_wlen - 1;
if (r_wlen == 0) r_w_state <= P_W_IDLE;
end else r_w_state <= P_W_WRITE;
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_b_state <= P_B_IDLE;
end else begin
case (r_b_state)
P_B_IDLE: begin
if (w_end) r_b_state <= P_B_OUT;
end
P_B_OUT: begin
if (i_bready) r_b_state <= P_B_IDLE;
end
endcase
end
end
`ifdef RANDOM_RVALID
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_rand_rvalid <= 1'b1;
end else begin
r_rand_rvalid <= $random;
end
end
`endif
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_r_state <= P_R_IDLE;
end else begin
case (r_r_state)
P_R_IDLE: begin
if (i_arvalid) begin
r_rlen <= i_arlen;
//r_raddr <= i_axi_mr.araddr[P_AXI_M_ARADDR-1:2];
r_raddr <= w_raddr;
r_r_state <= P_R_WAIT;
end
end
P_R_WAIT: begin
r_r_state <= P_R_OUT;
end
P_R_OUT: begin
`ifdef RANDOM_RVALID
if (i_rready & r_rand_rvalid) begin
`else
if (i_rready) begin
`endif
r_raddr <= r_raddr + 1;
r_rlen <= r_rlen - 1;
if (r_rlen == 0) r_r_state <= P_R_IDLE;
end
end
endcase
end
end
endmodule
|
module bv_axi_master (
// System
clk_core,
rst_x,
// AXI
o_awaddr,
o_awlen,
o_awsize,
o_awburst,
o_awvalid,
i_awready,
o_wdata,
o_wstrb,
o_wlast,
o_wvalid,
i_wready,
i_bresp,
i_bvalid,
o_bready,
o_araddr,
o_arlen,
o_arsize,
o_arburst,
o_arvalid,
i_arready,
i_rdata,
i_rresp,
i_rlast,
i_rvalid,
o_rready
);
parameter AXI_DATA_WIDTH = 32;
parameter AXI_BE_WIDTH = 4;
input clk_core;
input rst_x;
output [31:0] o_awaddr;
output [3:0] o_awlen;
output [2:0] o_awsize;
output [1:0] o_awburst;
output o_awvalid;
input i_awready;
output [AXI_DATA_WIDTH-1:0] o_wdata;
output [AXI_BE_WIDTH-1:0] o_wstrb;
output o_wlast;
output o_wvalid;
input i_wready;
input [1:0] i_bresp;
input i_bvalid;
output o_bready;
output [31:0] o_araddr;
output [3:0] o_arlen;
output [2:0] o_arsize;
output [1:0] o_arburst;
output o_arvalid;
input i_arready;
input [AXI_DATA_WIDTH-1:0] i_rdata;
input [1:0] i_rresp;
input i_rlast;
input i_rvalid;
output o_rready;
assign o_awsize = (AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
assign o_awburst = 2'b01;
assign o_arsize = (AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
assign o_arburst = 2'b01;
reg [31:0] o_awaddr;
reg [3:0] o_awlen;
reg o_awvalid;
reg [AXI_DATA_WIDTH-1:0] o_wdata;
reg [AXI_BE_WIDTH-1:0] o_wstrb;
reg o_wlast;
reg o_wvalid;
reg o_bready;
reg [31:0] o_araddr;
reg [3:0] o_arlen;
reg o_arvalid;
reg o_rready;
initial begin
o_awaddr = 0;
o_awlen = 0;
o_awvalid = 0;
o_wdata = 0;
o_wstrb = 0;
o_wlast = 0;
o_wvalid = 0;
o_bready = 0;
o_araddr = 0;
o_arlen = 0;
o_arvalid = 0;
o_rready = 0;
end
task axi_single_write;
input [31:0] i_adr;
input [AXI_BE_WIDTH-1:0] i_be;
input [AXI_DATA_WIDTH-1:0] i_dat;
begin
@(posedge clk_core) #1;
o_awaddr = i_adr;
o_awlen = 4'd0;
o_awvalid = 1;
o_wdata = i_dat;
o_wstrb = i_be;
o_wlast = 0;
o_wvalid = 0;
o_bready = 0;
while(!i_awready) @(posedge clk_core) #1;
@(posedge clk_core) #1;
o_awvalid = 0;
o_wlast = 1;
o_wvalid = 1;
o_bready = 1;
while(!i_wready) @(posedge clk_core) #1;
@(posedge clk_core) #1;
o_wvalid = 0;
o_wlast = 0;
o_wvalid = 0;
while(!i_bvalid) @(posedge clk_core);
@(posedge clk_core) #1;
o_bready = 0;
@(posedge clk_core) #1;
end
endtask
task axi_single_read;
input [31:0] i_adr;
output [AXI_DATA_WIDTH-1:0] o_dat;
begin
@(posedge clk_core) #1;
o_arvalid = 1;
o_araddr = i_adr;
o_arlen = 4'd0;
while(!i_arready) @(posedge clk_core) #1;
@(posedge clk_core) #1;
o_arvalid = 0;
@(posedge clk_core) #1;
while(!i_rvalid) @(posedge clk_core) #1;
o_dat = i_rdata;
o_rready = 1;
@(posedge clk_core) #1;
o_rready = 0;
@(posedge clk_core) #1;
end
endtask
endmodule
|
module fm_axi_m (
clk_core,
rst_x,
i_vtx_int,
// AXI Master configuration
i_conf_arcache_m,
i_conf_aruser_m,
i_conf_awcache_m,
i_conf_awuser_m,
// Local Memory Range
i_brg_req,
i_brg_adrs,
i_brg_id,
i_brg_rw,
i_brg_len,
o_brg_ack,
i_brg_wdvalid,
i_brg_be,
i_brg_wdata,
o_brg_wack,
o_brg_rdvalid,
o_brg_rid,
o_brg_rdata,
o_brg_rlast,
o_init_done,
// AXI write port
o_awid_m,
o_awaddr_m,
o_awlen_m,
o_awsize_m,
o_awburst_m,
o_awlock_m,
o_awcache_m,
o_awuser_m,
o_awprot_m,
o_awvalid_m,
i_awready_m,
o_wid_m,
o_wdata_m,
o_wstrb_m,
o_wlast_m,
o_wvalid_m,
i_wready_m,
i_bid_m,
i_bresp_m,
i_bvalid_m,
o_bready_m,
// AXI read port
o_arid_m,
o_araddr_m,
o_arlen_m,
o_arsize_m,
o_arburst_m,
o_arlock_m,
o_arcache_m,
o_aruser_m,
o_arprot_m,
o_arvalid_m,
i_arready_m,
i_rid_m,
i_rdata_m,
i_rresp_m,
i_rlast_m,
i_rvalid_m,
o_rready_m
`ifdef USE_AXI_MONITOR
// result out
,
i_stop_trigger,
// awvalid
o_bukets_no_wait_aw,
o_bukets_0_aw,
o_bukets_1_aw,
o_bukets_2_aw,
o_bukets_3_aw,
o_bukets_more_aw,
o_max_count_aw,
o_min_count_aw,
o_bukets_len_0_aw,
o_bukets_len_1_aw,
o_bukets_len_2_aw,
o_bukets_len_3_aw,
o_total_bytes_w,
o_cont_w,
o_discont_w,
o_bukets_nrdy_0_w,
o_bukets_nrdy_1_w,
o_bukets_nrdy_2_w,
o_bukets_nrdy_3_w,
// arvalid
o_bukets_no_wait_ar,
o_bukets_0_ar,
o_bukets_1_ar,
o_bukets_2_ar,
o_bukets_3_ar,
o_bukets_more_ar,
o_max_count_ar,
o_min_count_ar,
o_bukets_len_0_ar,
o_bukets_len_1_ar,
o_bukets_len_2_ar,
o_bukets_len_3_ar,
o_cont_ar,
o_discont_ar,
// wdata
o_bukets_no_wait_b,
o_bukets_0_b,
o_bukets_1_b,
o_bukets_2_b,
o_bukets_3_b,
o_bukets_more_b,
o_num_of_cmd_b,
o_num_of_b,
// rdata
o_bukets_no_wait_r,
o_bukets_0_r,
o_bukets_1_r,
o_bukets_2_r,
o_bukets_3_r,
o_bukets_more_r,
o_total_bytes_r,
o_rd_cont,
o_rd_discont,
o_bukets_nrdy_0_r,
o_bukets_nrdy_1_r,
o_bukets_nrdy_2_r,
o_bukets_nrdy_3_r
`endif
);
`include "polyphony_axi_def.v"
//////////////////////////////////
// I/O port definition
//////////////////////////////////
// system
input clk_core;
input rst_x;
// debug
input i_vtx_int;
// AXI Master configuration
input [3:0] i_conf_arcache_m;
input [4:0] i_conf_aruser_m;
input [3:0] i_conf_awcache_m;
input [4:0] i_conf_awuser_m;
// Bridge Interface
input i_brg_req;
input [P_IB_ADDR_WIDTH-1:0]
i_brg_adrs;
input i_brg_rw;
input [1:0] i_brg_id;
input [P_IB_LEN_WIDTH-1:0]
i_brg_len;
output o_brg_ack;
input i_brg_wdvalid;
input [P_IB_BE_WIDTH-1:0]
i_brg_be;
input [P_IB_DATA_WIDTH-1:0]
i_brg_wdata;
output o_brg_wack;
output o_brg_rdvalid;
output [1:0] o_brg_rid;
output [P_IB_DATA_WIDTH-1:0]
o_brg_rdata;
output o_brg_rlast;
output o_init_done;
// AXI Master
// write port
output [P_AXI_M_AWID-1:0] o_awid_m;
output [P_AXI_M_AWADDR-1:0] o_awaddr_m;
output [P_AXI_M_AWLEN-1:0] o_awlen_m;
output [P_AXI_M_AWSIZE-1:0] o_awsize_m;
output [P_AXI_M_AWBURST-1:0] o_awburst_m;
output [P_AXI_M_AWLOCK-1:0] o_awlock_m;
output [P_AXI_M_AWCACHE-1:0] o_awcache_m;
output [P_AXI_M_AWUSER-1:0] o_awuser_m;
output [P_AXI_M_AWPROT-1:0] o_awprot_m;
output o_awvalid_m;
input i_awready_m;
output [P_AXI_M_WID-1:0] o_wid_m;
output [P_AXI_M_WDATA-1:0] o_wdata_m;
output [P_AXI_M_WSTRB-1:0] o_wstrb_m;
output o_wlast_m;
output o_wvalid_m;
input i_wready_m;
input [P_AXI_M_BID-1:0] i_bid_m;
input [P_AXI_M_BRESP-1:0] i_bresp_m;
input i_bvalid_m;
output o_bready_m;
// read port
output [P_AXI_M_ARID-1:0] o_arid_m;
output [P_AXI_M_ARADDR-1:0] o_araddr_m;
output [P_AXI_M_ARLEN-1:0] o_arlen_m;
output [P_AXI_M_ARSIZE-1:0] o_arsize_m;
output [P_AXI_M_ARBURST-1:0] o_arburst_m;
output [P_AXI_M_ARLOCK-1:0] o_arlock_m;
output [P_AXI_M_ARCACHE-1:0] o_arcache_m;
output [P_AXI_M_ARUSER-1:0] o_aruser_m;
output [P_AXI_M_ARPROT-1:0] o_arprot_m;
output o_arvalid_m;
input i_arready_m;
// read response
input [P_AXI_M_RID-1:0] i_rid_m;
input [P_AXI_M_RDATA-1:0] i_rdata_m;
input [P_AXI_M_RRESP-1:0] i_rresp_m;
input i_rlast_m;
input i_rvalid_m;
output o_rready_m;
`ifdef USE_AXI_MONITOR
localparam P_BUCKET_SIZE = 'd32;
input i_stop_trigger;
// awvalid
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_0_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_1_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_2_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_3_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_more_aw;
output [P_BUCKET_SIZE-1:0] o_max_count_aw;
output [P_BUCKET_SIZE-1:0] o_min_count_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_len_0_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_len_1_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_len_2_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_len_3_aw;
output [P_BUCKET_SIZE-1:0] o_total_bytes_w;
output [P_BUCKET_SIZE-1:0] o_cont_w;
output [P_BUCKET_SIZE-1:0] o_discont_w;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_0_w;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_1_w;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_2_w;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_3_w;
// arvalid
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_0_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_1_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_2_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_3_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_more_ar;
output [P_BUCKET_SIZE-1:0] o_max_count_ar;
output [P_BUCKET_SIZE-1:0] o_min_count_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_len_0_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_len_1_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_len_2_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_len_3_ar;
output [P_BUCKET_SIZE-1:0] o_cont_ar;
output [P_BUCKET_SIZE-1:0] o_discont_ar;
// wdata
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait_b;
output [P_BUCKET_SIZE-1:0] o_bukets_0_b;
output [P_BUCKET_SIZE-1:0] o_bukets_1_b;
output [P_BUCKET_SIZE-1:0] o_bukets_2_b;
output [P_BUCKET_SIZE-1:0] o_bukets_3_b;
output [P_BUCKET_SIZE-1:0] o_bukets_more_b;
output [P_BUCKET_SIZE-1:0] o_num_of_cmd_b;
output [P_BUCKET_SIZE-1:0] o_num_of_b;
// rdata
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait_r;
output [P_BUCKET_SIZE-1:0] o_bukets_0_r;
output [P_BUCKET_SIZE-1:0] o_bukets_1_r;
output [P_BUCKET_SIZE-1:0] o_bukets_2_r;
output [P_BUCKET_SIZE-1:0] o_bukets_3_r;
output [P_BUCKET_SIZE-1:0] o_bukets_more_r;
output [P_BUCKET_SIZE-1:0] o_total_bytes_r;
output [P_BUCKET_SIZE-1:0] o_rd_cont;
output [P_BUCKET_SIZE-1:0] o_rd_discont;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_0_r;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_1_r;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_2_r;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_3_r;
`endif
//////////////////////////////////
// parameter definition
//////////////////////////////////
localparam P_IDLE = 1'b0;
localparam P_WPROC = 1'b1;
//////////////////////////////////
// reg
//////////////////////////////////
reg r_brg_rdvalid;
reg r_brg_rlast;
reg [1:0] r_brg_rid;
reg [P_IB_DATA_WIDTH-1:0] r_brg_rdata;
reg [P_AXI_M_AWLEN-1:0] r_awlen;
reg [1:0] r_brg_wid;
reg r_wstate;
//////////////////////////////////
// wire
//////////////////////////////////
// command/data interface
wire [P_IB_LEN_WIDTH+P_IB_ADDR_WIDTH+2+1-1:0]
w_fifo_cin;
wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
w_fifo_din;
wire [P_IB_LEN_WIDTH+P_IB_ADDR_WIDTH+2+1-1:0]
w_fifo_cout;
wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
w_fifo_dout;
wire w_cfifo_ack;
wire w_dfifo_ack;
wire w_brg_req;
wire [P_IB_ADDR_WIDTH-1:0]
w_brg_adrs;
wire w_brg_rw;
wire [1:0] w_brg_id;
wire [1:0] w_brg_wid;
wire [P_IB_LEN_WIDTH-1:0]
w_brg_len;
wire [P_IB_BE_WIDTH-1:0]
w_brg_be;
wire [P_IB_DATA_WIDTH-1:0]
w_brg_wdata;
wire w_brg_wdvalid;
wire w_wr_full;
wire w_wr_hit;
wire w_wr_empty;
wire w_wc_ack;
wire w_wdd_last_data;
wire w_arready_m_raw;
wire w_awready_m;
wire w_is_idle;
wire w_is_wproc;
wire [P_IB_DATA_WIDTH+P_IB_BE_WIDTH-1:0]
w_fifo_dout_f;
wire w_ren_f;
wire w_full_f;
wire w_empty_f;
wire w_write_command;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_write_command = w_brg_req & w_brg_rw;
assign {w_brg_be,w_brg_wdata} = w_fifo_dout_f;
assign w_is_idle = (r_wstate == P_IDLE);
assign w_is_wproc = (r_wstate == P_WPROC);
assign o_init_done = 1'b1;
assign w_wc_ack = o_awvalid_m & i_awready_m;
assign w_wdd_last_data = o_wlast_m;
// assign w_cfifo_ack = (w_brg_rw) ? i_awready_m : i_arready_m;
// arready should be masked if RAW condition
assign w_arready_m_raw = (w_wr_empty) ? i_arready_m :
i_arready_m & (!w_wr_hit);
assign w_awready_m = (w_wr_full) ? 1'b0 : i_awready_m;
assign w_cfifo_ack = (r_wstate == P_WPROC) ? 1'b0:
(!w_brg_req) ? 1'b1:
(w_brg_rw) ? w_awready_m : w_arready_m_raw;
assign w_fifo_cin = {i_brg_id,i_brg_rw,i_brg_adrs,i_brg_len};
assign w_fifo_din = {i_brg_be,i_brg_wdata};
assign {w_brg_id,w_brg_rw,w_brg_adrs,w_brg_len} = w_fifo_cout;
assign w_ren_f = (w_empty_f) ? 1'b1:
(w_is_wproc & i_wready_m);
// AXI write
assign o_awid_m = {{(P_AXI_M_AWID-2){1'b0}},w_brg_id};
assign o_awaddr_m = {w_brg_adrs,{P_IB_DATA_WIDTH_POW2{1'b0}}};
assign o_awlen_m = w_brg_len-1'b1;
`ifdef PP_BUSWIDTH_64
assign o_awsize_m = 'd3;
`else
assign o_awsize_m = 'd2;
`endif
assign o_awburst_m = 'd1;
assign o_awlock_m = 'd0; // normal access
assign o_awcache_m = i_conf_awcache_m; // non-cachable
assign o_awuser_m = i_conf_awuser_m;
assign o_awprot_m = 'd0;
assign o_awvalid_m = (w_wr_full| w_is_wproc) ? 1'b0 :
w_brg_req & w_brg_rw;
assign w_brg_wid = (o_awvalid_m) ? w_brg_id : r_brg_wid;
assign o_wid_m = {{(P_AXI_M_WID-2){1'b0}},w_brg_wid};
assign o_wdata_m = w_brg_wdata;
assign o_wstrb_m = w_brg_be;
assign o_wlast_m = (r_awlen == 'd1);
assign o_wvalid_m = w_is_wproc & (!w_empty_f);
assign o_bready_m = !w_wr_full;
// AXI read
assign o_arid_m = {{(P_AXI_M_ARID-2){1'b0}},w_brg_id};
assign o_araddr_m = {w_brg_adrs,{P_IB_DATA_WIDTH_POW2{1'b0}}};
assign o_arlen_m = w_brg_len-1'b1;
`ifdef PP_BUSWIDTH_64
assign o_arsize_m = 'd3;
`else
assign o_arsize_m = 'd2;
`endif
assign o_arburst_m = 'd1;
assign o_arlock_m = 'd0; // normal access
assign o_arcache_m = i_conf_arcache_m; // non-cachable
assign o_aruser_m = i_conf_aruser_m;
assign o_arprot_m = 'd0;
assign o_arvalid_m = (w_is_wproc) ? 1'b0:
(w_wr_empty) ? w_brg_req & (!w_brg_rw) :
w_brg_req & (!w_brg_rw) & (!w_wr_hit);
assign o_rready_m = 1'b1;
// read response
assign o_brg_rdvalid = r_brg_rdvalid;
assign o_brg_rid = r_brg_rid;
assign o_brg_rdata = r_brg_rdata;
assign o_brg_rlast = r_brg_rlast;
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_wstate <= P_IDLE;
r_awlen <= 'd0;
end else begin
case (r_wstate)
P_IDLE: begin
if (w_write_command & w_cfifo_ack ) begin
r_awlen <= w_brg_len;
r_wstate <= P_WPROC;
end
end
P_WPROC: begin
if (!w_empty_f & i_wready_m) begin
r_awlen <= r_awlen - 1'b1; // data accept only
if (w_wdd_last_data) r_wstate <= P_IDLE;
end
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_brg_rdvalid <= 1'b0;
end else begin
r_brg_rdvalid <= i_rvalid_m;
end
end
always @(posedge clk_core) begin
r_brg_rid <= i_rid_m[1:0];
r_brg_rdata <= i_rdata_m;
r_brg_rlast <= i_rlast_m;
end
always @(posedge clk_core) begin
if (w_wc_ack) begin
r_brg_wid <= w_brg_id;
end
end
//////////////////////////////////
// module instance
//////////////////////////////////
// command interface
fm_cmn_cinterface #(P_IB_LEN_WIDTH+P_IB_ADDR_WIDTH+2+1) u_cinterface (
.clk_core(clk_core),
.rst_x(rst_x),
// bus side port
.i_bstr(i_brg_req),
.i_bdata(w_fifo_cin),
.o_back(o_brg_ack),
// internal port
.o_istr(w_brg_req),
.o_idata(w_fifo_cout),
.i_iack(w_cfifo_ack)
);
// data interface
fm_cmn_dinterface #(P_IB_DATA_WIDTH+P_IB_BE_WIDTH) u_dinterface (
.clk_core(clk_core),
.rst_x(rst_x),
// bus side port
.i_bstr(i_brg_wdvalid),
.i_bdata(w_fifo_din),
.o_back(o_brg_wack),
// internal port
.o_istr(w_brg_wdvalid),
.o_idata(w_fifo_dout),
.i_iack(!w_full_f)
);
// write data fifo
fm_fifo #(P_IB_DATA_WIDTH+P_IB_BE_WIDTH,1) u_wd_fifo (
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(w_brg_wdvalid),
.i_dt(w_fifo_dout),
.o_full(w_full_f),
.i_renable(w_ren_f),
.o_dt(w_fifo_dout_f),
.o_empty(w_empty_f),
.o_dnum()
);
/*
assign w_wr_full = 0;
assign w_wr_empty = 1;
assign w_wr_hit = 0;
*/
// write response fifo
fm_raw_fifo #(P_IB_ADDR_WIDTH) u_raw_fifo (
.clk_core(clk_core),
.rst_x(rst_x),
.i_check_address(i_brg_adrs),
.o_hit(w_wr_hit),
.i_wstrobe(w_wc_ack),
.i_dt(i_brg_adrs),
.o_full(w_wr_full),
.i_renable(i_bvalid_m),
.o_dt(),
.o_empty(w_wr_empty),
.o_dnum()
);
///////////////////////////////////////////////////////////
// debug signals
reg [15:0] r_in_rcmd;
reg [15:0] r_in_wcmd;
reg [15:0] r_in_wd;
reg [15:0] r_axi_rcmd;
reg [15:0] r_axi_wcmd;
reg [15:0] r_axi_wd;
reg [15:0] r_axi_wd_last;
reg [15:0] r_axi_rd;
reg [15:0] r_axi_rd_last;
reg [15:0] r_axi_bcmd;
// id check
wire [1:0] w_last_rid;
wire w_rd_id;
wire w_diff;
assign w_rd_id = r_brg_rlast & r_brg_rdvalid;
assign w_diff = r_brg_rdvalid & w_last_rid != r_brg_rid;
fm_fifo #(2,8) u_id (
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(i_brg_req & (!i_brg_rw)),
.i_dt(i_brg_id),
.o_full(),
.i_renable(w_rd_id),
.o_dt(w_last_rid),
.o_empty(),
.o_dnum()
);
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_in_rcmd <= 'd0;
r_in_wcmd <= 'd0;
r_in_wd <= 'd0;
end else begin
if (i_brg_req & (!i_brg_rw)) r_in_rcmd <= r_in_rcmd + 1'b1;
if (i_brg_req & i_brg_rw) r_in_wcmd <= r_in_wcmd + 1'b1;
if (i_brg_wdvalid) r_in_wd <= r_in_wd + 1'b1;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_axi_rcmd <= 'd0;
r_axi_wcmd <= 'd0;
r_axi_wd <= 'd0;
r_axi_wd_last <= 'd0;
r_axi_bcmd <= 'd0;
end else begin
if (o_arvalid_m & i_arready_m) r_axi_rcmd <= r_axi_rcmd + 1'b1;
if (o_awvalid_m & i_awready_m) r_axi_wcmd <= r_axi_wcmd + 1'b1;
if (o_wvalid_m & i_wready_m) r_axi_wd <= r_axi_wd + 1'b1;
if (o_wvalid_m & i_wready_m & o_wlast_m) r_axi_wd_last <= r_axi_wd_last + 1'b1;
if (i_bvalid_m & o_bready_m) r_axi_bcmd <= r_axi_bcmd + 1'b1;
if (i_rvalid_m & o_rready_m) r_axi_rd <= r_axi_rd + 1'b1;
if (i_rvalid_m & o_rready_m & i_rlast_m) r_axi_rd_last <= r_axi_rd_last + 1'b1;
end
end
`ifdef USE_AXI_MONITOR
fm_axi_monitor u_axi_monitor (
.clk_core(clk_core),
.rst_x(rst_x),
.i_stop_trigger(i_stop_trigger),
// AXI write port
.i_awid_m(o_awid_m),
.i_awaddr_m(o_awaddr_m),
.i_awlen_m(o_awlen_m),
.i_awsize_m(o_awsize_m),
.i_awburst_m(o_awburst_m),
.i_awlock_m(o_awlock_m),
.i_awcache_m(o_awcache_m),
.i_awuser_m(o_awuser_m),
.i_awprot_m(o_awprot_m),
.i_awvalid_m(o_awvalid_m),
.i_awready_m(i_awready_m),
.i_wid_m(o_wid_m),
.i_wdata_m(o_wdata_m),
.i_wstrb_m(o_wstrb_m),
.i_wlast_m(o_wlast_m),
.i_wvalid_m(o_wvalid_m),
.i_wready_m(i_wready_m),
.i_bid_m(i_bid_m),
.i_bresp_m(i_bresp_m),
.i_bvalid_m(i_bvalid_m),
.i_bready_m(o_bready_m),
// AXI read port
.i_arid_m(o_arid_m),
.i_araddr_m(o_araddr_m),
.i_arlen_m(o_arlen_m),
.i_arsize_m(o_arsize_m),
.i_arburst_m(o_arburst_m),
.i_arlock_m(o_arlock_m),
.i_arcache_m(o_arcache_m),
.i_aruser_m(o_aruser_m),
.i_arprot_m(o_arprot_m),
.i_arvalid_m(o_arvalid_m),
.i_arready_m(i_arready_m),
.i_rid_m(i_rid_m),
.i_rdata_m(i_rdata_m),
.i_rresp_m(i_rresp_m),
.i_rlast_m(i_rlast_m),
.i_rvalid_m(i_rvalid_m),
.i_rready_m(o_rready_m),
// result out
// awvalid
.o_bukets_no_wait_aw(o_bukets_no_wait_aw),
.o_bukets_0_aw(o_bukets_0_aw),
.o_bukets_1_aw(o_bukets_1_aw),
.o_bukets_2_aw(o_bukets_2_aw),
.o_bukets_3_aw(o_bukets_3_aw),
.o_bukets_more_aw(o_bukets_more_aw),
.o_max_count_aw(o_max_count_aw),
.o_min_count_aw(o_min_count_aw),
.o_bukets_len_0_aw(o_bukets_len_0_aw),
.o_bukets_len_1_aw(o_bukets_len_1_aw),
.o_bukets_len_2_aw(o_bukets_len_2_aw),
.o_bukets_len_3_aw(o_bukets_len_3_aw),
.o_total_bytes_w(o_total_bytes_w),
.o_cont_w(o_cont_w),
.o_discont_w(o_discont_w),
// arvalid
.o_bukets_no_wait_ar(o_bukets_no_wait_ar),
.o_bukets_0_ar(o_bukets_0_ar),
.o_bukets_1_ar(o_bukets_1_ar),
.o_bukets_2_ar(o_bukets_2_ar),
.o_bukets_3_ar(o_bukets_3_ar),
.o_bukets_more_ar(o_bukets_more_ar),
.o_max_count_ar(o_max_count_ar),
.o_min_count_ar(o_min_count_ar),
.o_bukets_len_0_ar(o_bukets_len_0_ar),
.o_bukets_len_1_ar(o_bukets_len_1_ar),
.o_bukets_len_2_ar(o_bukets_len_2_ar),
.o_bukets_len_3_ar(o_bukets_len_3_ar),
.o_cont_ar(o_cont_ar),
.o_discont_ar(o_discont_ar),
.o_bukets_nrdy_0_w(o_bukets_nrdy_0_w),
.o_bukets_nrdy_1_w(o_bukets_nrdy_1_w),
.o_bukets_nrdy_2_w(o_bukets_nrdy_2_w),
.o_bukets_nrdy_3_w(o_bukets_nrdy_3_w),
// wdata
.o_bukets_no_wait_b(o_bukets_no_wait_b),
.o_bukets_0_b(o_bukets_0_b),
.o_bukets_1_b(o_bukets_1_b),
.o_bukets_2_b(o_bukets_2_b),
.o_bukets_3_b(o_bukets_3_b),
.o_bukets_more_b(o_bukets_more_b),
.o_num_of_cmd_b(o_num_of_cmd_b),
.o_num_of_b(o_num_of_b),
// rdata
.o_bukets_no_wait_r(o_bukets_no_wait_r),
.o_bukets_0_r(o_bukets_0_r),
.o_bukets_1_r(o_bukets_1_r),
.o_bukets_2_r(o_bukets_2_r),
.o_bukets_3_r(o_bukets_3_r),
.o_bukets_more_r(o_bukets_more_r),
.o_total_bytes_r(o_total_bytes_r),
.o_rd_cont(o_rd_cont),
.o_rd_discont(o_rd_discont),
.o_bukets_nrdy_0_r(o_bukets_nrdy_0_r),
.o_bukets_nrdy_1_r(o_bukets_nrdy_1_r),
.o_bukets_nrdy_2_r(o_bukets_nrdy_2_r),
.o_bukets_nrdy_3_r(o_bukets_nrdy_3_r)
);
`endif
//////////////////////////////////////////////////////////
/*
wire [35:0] CONTROL0;
wire [192:0] TRIG0;
wire [436:0] DATA;
chipscope_icon_v1_06_a_0 u_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_v1_05_a_0 u_chipscope (
.CONTROL(CONTROL0),
.CLK(clk_core),
.TRIG0(TRIG0),
.DATA(DATA)
);
assign DATA[0] = i_brg_req;
assign DATA[30:1] = i_brg_adrs[29:0];
assign DATA[31] = i_brg_rw;
assign DATA[37:32] = i_brg_len[5:0];
assign DATA[38] = o_brg_ack;
assign DATA[39] = i_brg_wdvalid;
assign DATA[43:40] = i_brg_be[3:0];
assign DATA[75:44] = i_brg_wdata[31:0];
assign DATA[76] = o_brg_wack;
assign DATA[77] = o_brg_rdvalid;
assign DATA[109:78] = o_brg_rdata[31:0];
// write port
assign DATA[113:110] = o_awid_m[3:0];
assign DATA[145:114] = o_awaddr_m[31:0];
assign DATA[150:146] = o_awlen_m[4:0];
assign DATA[151] = o_awvalid_m;
assign DATA[152] = i_awready_m;
assign DATA[156:153] = o_wid_m[3:0];
assign DATA[188:157] = o_wdata_m[31:0];
assign DATA[192:189] = o_wstrb_m[3:0];
assign DATA[193] = o_wlast_m;
assign DATA[194] = o_wvalid_m;
assign DATA[195] = i_wready_m;
assign DATA[199:196] = i_bid_m[3:0];
assign DATA[201:200] = i_bresp_m[1:0];
assign DATA[202] = i_bvalid_m;
assign DATA[203] = o_bready_m;
// read port
assign DATA[207:204] = o_arid_m[3:0];
assign DATA[239:208] = o_araddr_m[31:0];
assign DATA[244:240] = o_arlen_m[4:0];
assign DATA[245] = o_arvalid_m;
assign DATA[246] = i_arready_m;
// read response
assign DATA[250:247] = i_rid_m[3:0];
assign DATA[282:251] = i_rdata_m[31:0];
assign DATA[284:283] = i_rresp_m[1:0];
assign DATA[285] = i_rlast_m;
assign DATA[286] = i_rvalid_m;
assign DATA[287] = o_rready_m;
assign DATA[303:288] = r_in_rcmd[15:0];
assign DATA[319:304] = r_in_wcmd[15:0];
assign DATA[335:320] = r_in_wd[15:0];
assign DATA[351:336] = r_axi_rcmd[15:0];
assign DATA[367:352] = r_axi_wcmd[15:0];
assign DATA[383:368] = r_axi_wd[15:0];
assign DATA[399:384] = r_axi_bcmd[15:0];
assign DATA[415:400] = r_axi_wd_last[15:0];
assign DATA[431:416] = r_axi_rd_last[15:0];
assign DATA[433:432] = r_brg_rid;
assign DATA[435:434] = w_last_rid;
assign DATA[436] = w_diff;
assign TRIG0[0] = i_brg_req;
assign TRIG0[30:1] = i_brg_adrs[29:0];
assign TRIG0[31] = i_brg_rw;
assign TRIG0[37:32] = i_brg_len[5:0];
assign TRIG0[38] = o_brg_ack;
assign TRIG0[39] = i_brg_wdvalid;
assign TRIG0[43:40] = i_brg_be[3:0];
assign TRIG0[75:44] = i_brg_wdata[31:0];
assign TRIG0[76] = o_brg_wack;
assign TRIG0[77] = o_brg_rdvalid;
assign TRIG0[109:78] = o_brg_rdata[31:0];
// write port
assign TRIG0[113:110] = o_awid_m[3:0];
assign TRIG0[118:114] = o_awlen_m[4:0];
assign TRIG0[119] = o_awvalid_m;
assign TRIG0[120] = i_awready_m;
assign TRIG0[124:121] = o_wid_m[3:0];
assign TRIG0[128:125] = o_wstrb_m[3:0];
assign TRIG0[129] = o_wlast_m;
assign TRIG0[130] = o_wvalid_m;
assign TRIG0[131] = i_wready_m;
assign TRIG0[135:132] = i_bid_m[3:0];
assign TRIG0[137:136] = i_bresp_m[1:0];
assign TRIG0[138] = i_bvalid_m;
assign TRIG0[139] = o_bready_m;
// read port
assign TRIG0[143:140] = o_arid_m[3:0];
assign TRIG0[175:144] = o_araddr_m[31:0];
assign TRIG0[180:176] = o_arlen_m[4:0];
assign TRIG0[181] = o_arvalid_m;
assign TRIG0[182] = i_arready_m;
// read response
assign TRIG0[186:183] = i_rid_m[3:0];
assign TRIG0[188:187] = i_rresp_m[1:0];
assign TRIG0[189] = i_rlast_m;
assign TRIG0[190] = i_rvalid_m;
assign TRIG0[191] = o_rready_m;
assign TRIG0[192] = w_diff;
*/
endmodule
|
module fm_axi_monitor_r (
clk_core,
rst_x,
i_clear,
i_arvalid,
i_arready,
i_arlen,
i_rresp,
i_rlast,
i_rvalid,
i_rready,
// result out
o_set_no_wait,
o_set_bukets,
o_set_no_more,
o_timer,
o_bukets_no_wait,
o_bukets_0,
o_bukets_1,
o_bukets_2,
o_bukets_3,
o_bukets_more,
o_rvalid_invalid_cycles,
o_state,
o_len,
o_total_bytes,
o_rd_cont,
o_rd_discont,
o_bukets_nrdy_0,
o_bukets_nrdy_1,
o_bukets_nrdy_2,
o_bukets_nrdy_3
);
`include "polyphony_axi_def.v"
localparam P_TIMER_WIDTH = 'd12;
localparam P_IDLE = 1'b0;
localparam P_RUN = 1'b1;
localparam P_NUM_OF_BUCKETS = 'd4;
localparam P_BUCKET_RANGE = 'd8;
localparam P_BUCKET_RANGE_NRDY = 'd4;
localparam P_BUCKET_SIZE = 'd32;
localparam P_COUNTER_SIZE = 'd32;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
input i_clear;
// read port
input [P_AXI_M_ARLEN-1:0] i_arlen;
input i_arvalid;
input i_arready;
// read response
input [P_AXI_M_RRESP-1:0] i_rresp;
input i_rlast;
input i_rvalid;
input i_rready;
// result out
output o_set_no_wait;
output [P_NUM_OF_BUCKETS-1:0] o_set_bukets;
output o_set_no_more;
output [P_TIMER_WIDTH-1:0] o_timer;
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait;
output [P_BUCKET_SIZE-1:0] o_bukets_0;
output [P_BUCKET_SIZE-1:0] o_bukets_1;
output [P_BUCKET_SIZE-1:0] o_bukets_2;
output [P_BUCKET_SIZE-1:0] o_bukets_3;
output [P_BUCKET_SIZE-1:0] o_bukets_more;
output [P_BUCKET_SIZE-1:0] o_rvalid_invalid_cycles;
output o_state;
output [P_AXI_M_ARLEN-1:0] o_len;
output [31:0] o_total_bytes;
output [P_BUCKET_SIZE-1:0] o_rd_cont;
output [P_BUCKET_SIZE-1:0] o_rd_discont;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_0;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_1;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_2;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_3;
//////////////////////////////////
// reg
//////////////////////////////////
reg [P_TIMER_WIDTH-1:0] r_timer;
reg r_state;
reg [P_AXI_M_ARLEN-1:0] r_len;
reg [P_BUCKET_SIZE-1:0] r_bukets[P_NUM_OF_BUCKETS-1:0];
reg [P_BUCKET_SIZE-1:0] r_bukets_no_wait;
reg [P_BUCKET_SIZE-1:0] r_bukets_more;
reg [P_BUCKET_SIZE-1:0] r_rvalid_invalid_cycles;
reg [31:0] r_total_bytes;
reg [P_BUCKET_SIZE-1:0] r_rd_cont;
reg [P_BUCKET_SIZE-1:0] r_rd_discont;
reg r_rvalid_invalid_flag;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy[P_NUM_OF_BUCKETS-1:0];
reg [15:0] r_nrdy_counter;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_more;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_fifo_empty;
wire w_fifo_ren;
wire w_set_first;
wire [P_AXI_M_ARLEN-1:0] w_len;
wire [P_TIMER_WIDTH-1:0] w_timer;
wire w_start;
wire w_clear_len;
wire w_stop;
wire [P_AXI_M_ARLEN-1:0] w_len_inc;
wire w_inc;
wire [P_NUM_OF_BUCKETS-1:0]
w_set;
wire w_set_no_wait;
wire w_set_more;
wire [P_TIMER_WIDTH-1:0] w_timer_diff;
wire [P_NUM_OF_BUCKETS-1:0]
w_set_nrdy;
wire w_set_nrdy_more;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_start = !w_fifo_empty & i_rvalid;
assign w_clear_len = ((r_state == P_RUN)&w_stop&i_rvalid);
assign w_len_inc = r_len + 1'b1;
assign w_inc = i_rvalid & i_rready;
assign w_fifo_ren = ((r_state == P_IDLE) & (w_len == 'd0)) |
(w_inc & (w_len == r_len)) ;
assign w_stop = w_inc & (w_len == r_len) ;
// assign w_stop = w_inc i_rlast;
assign w_set_first = w_inc & (r_len == 'd0);
assign w_set_no_wait = w_set_first &
(w_timer_diff == 'd0);
assign w_set_more = (P_BUCKET_RANGE*P_NUM_OF_BUCKETS <= w_timer_diff) &
w_set_first & !w_fifo_empty;
assign w_timer_diff = (r_timer > w_timer) ? {1'b0,r_timer} - {1'b0,w_timer} :
{1'b1,r_timer} - {1'b0,w_timer};
assign o_bukets_no_wait = r_bukets_no_wait;
assign o_bukets_0 = r_bukets[0];
assign o_bukets_1 = r_bukets[1];
assign o_bukets_2 = r_bukets[2];
assign o_bukets_3 = r_bukets[3];
assign o_bukets_more = r_bukets_more;
assign o_set_no_wait = w_set_no_wait;
assign o_set_bukets = w_set;
assign o_set_no_more = w_set_more;
assign o_timer = w_timer_diff;
assign o_rvalid_invalid_cycles = r_rvalid_invalid_cycles;
assign o_state = r_state;
assign o_len = r_len;
// assign o_total_bytes = r_total_bytes;
assign o_total_bytes = r_bukets_nrdy_more;
assign o_rd_cont = r_rd_cont;
assign o_rd_discont = r_rd_discont;
assign o_bukets_nrdy_0 = r_bukets_nrdy[0];
assign o_bukets_nrdy_1 = r_bukets_nrdy[1];
assign o_bukets_nrdy_2 = r_bukets_nrdy[2];
assign o_bukets_nrdy_3 = r_bukets_nrdy[3];
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (w_start) begin
if (w_len == 'd0) r_state <= P_IDLE;
else r_state <= P_RUN;
end
end
P_RUN: begin
if (w_stop|i_clear) begin
r_state <= P_IDLE;
end
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_len <= 'd0;
end else begin
if (i_clear) r_len <= 'd0;
else begin
if (w_clear_len) begin
r_len <= 'd0;
end else begin
if (w_inc) r_len <= w_len_inc;
end
end
end
end
genvar gi;
generate for (gi=0;gi<P_NUM_OF_BUCKETS;gi=gi+1)begin
assign w_set[gi] = ((P_BUCKET_RANGE*gi <= w_timer_diff) &
(w_timer_diff < P_BUCKET_RANGE*(gi+1))) &
w_set_first & !w_fifo_empty;
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets[gi] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) r_bukets[gi] <= {P_BUCKET_SIZE{1'b0}};
else if (w_set[gi]) r_bukets[gi] <= r_bukets[gi] + 1'b1;
end
end
end
endgenerate
// read wait
genvar gj;
generate for (gj=0;gj<P_NUM_OF_BUCKETS;gj=gj+1)begin
assign w_set_nrdy[gj] = ((P_BUCKET_RANGE_NRDY*gj <= r_nrdy_counter) &
(r_nrdy_counter < P_BUCKET_RANGE_NRDY*(gj+1))) &
w_fifo_ren & !w_fifo_empty;
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_nrdy[gj] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) r_bukets_nrdy[gj] <= {P_BUCKET_SIZE{1'b0}};
else
if (w_set_nrdy[gj]) r_bukets_nrdy[gj] <= r_bukets_nrdy[gj] + 1'b1;
end
end
end
endgenerate
assign w_set_nrdy_more = (P_BUCKET_RANGE*P_NUM_OF_BUCKETS <= r_nrdy_counter) &
(i_rvalid & i_rready & i_rlast);
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_nrdy_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets_nrdy_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set_nrdy_more) r_bukets_nrdy_more <= r_bukets_nrdy_more + 1'b1;
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_nrdy_counter<= 'd0;
end else begin
if (i_clear) r_nrdy_counter<= 'd0;
else
if (w_fifo_ren) r_nrdy_counter <= 'd0;
else if (!i_rvalid & (r_state == P_RUN)) r_nrdy_counter <= r_nrdy_counter + 1'b1;
end
end
// rvalid invalid cycles
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_rvalid_invalid_cycles <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_rvalid_invalid_cycles <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (r_state == P_RUN) begin
if ((r_len != 'd0) & (!i_rvalid))
r_rvalid_invalid_cycles <= r_rvalid_invalid_cycles + 1'b1;
end
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_rvalid_invalid_flag <= 1'b0;
end else begin
if (i_clear) begin
r_rvalid_invalid_flag <= 1'b0;
end else begin
if (r_state == P_IDLE) begin
r_rvalid_invalid_flag <= 1'b0;
end else
if (r_state == P_RUN) begin
if ((r_len != 'd0) & (!i_rvalid))
r_rvalid_invalid_flag <= 1'b1;
end
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_rd_cont <= 'd0;
r_rd_discont <= 'd0;
end else begin
if (i_clear) begin
r_rd_cont <= 'd0;
r_rd_discont <= 'd0;
end else begin
if (r_state == P_IDLE) begin
if (w_start & (w_len == 'd0)) r_rd_cont <= r_rd_cont + 1'b1;
end else
if (r_state == P_RUN) begin
if (w_stop) begin
if (~r_rvalid_invalid_flag) r_rd_cont <= r_rd_cont + 1'b1;
if (r_rvalid_invalid_flag) r_rd_discont <= r_rd_discont + 1'b1;
end
end
end
end
end
// special case
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_no_wait <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) r_bukets_no_wait <= {P_BUCKET_SIZE{1'b0}};
else
if (w_set_no_wait) r_bukets_no_wait <= r_bukets_no_wait + 1'b1;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) r_bukets_more <= {P_BUCKET_SIZE{1'b0}};
else
if (w_set_more) r_bukets_more <= r_bukets_more + 1'b1;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_timer <= 'd0;
end else begin
if (i_clear) r_timer <= 'd0;
else
r_timer <= r_timer + 1'b1;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_total_bytes <= 'd0;
end else begin
if (i_clear) r_total_bytes <= 'd0;
else
if (w_inc) r_total_bytes <= r_total_bytes + 1'b1;
end
end
fm_fifo #(.P_WIDTH(P_AXI_M_ARLEN+P_TIMER_WIDTH),
.P_RANGE(4),
.P_CLEAR("TRUE")) u_fifo (
.clk_core(clk_core),
.rst_x(rst_x|i_clear),
.i_wstrobe(i_arvalid & i_arready),
.i_dt({r_timer,i_arlen}),
.o_full(),
.i_renable(w_fifo_ren),
.o_dt({w_timer,w_len}),
.o_empty(w_fifo_empty),
.o_dnum()
);
endmodule
|
module fm_axi_monitor_b (
clk_core,
rst_x,
i_clear,
i_wvalid, // wvalid & wlast
i_wready,
i_bid,
i_bresp,
i_bvalid,
i_bready,
// result out
o_set_no_wait,
o_set_bukets,
o_set_no_more,
o_counter,
o_bukets_no_wait,
o_bukets_0,
o_bukets_1,
o_bukets_2,
o_bukets_3,
o_bukets_more,
o_num_of_cmd,
o_num_of_b
);
`include "polyphony_axi_def.v"
localparam P_TIMER_WIDTH = 'd16;
localparam P_IDLE = 1'b0;
localparam P_RUN = 1'b1;
localparam P_NUM_OF_BUCKETS = 'd4;
localparam P_BUCKET_RANGE = 'd4;
localparam P_BUCKET_SIZE = 'd32;
localparam P_COUNTER_SIZE = 'd32;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
input i_clear;
// read port
input i_wvalid;
input i_wready;
// read response
input [P_AXI_M_BID-1:0] i_bid;
input [P_AXI_M_BRESP-1:0] i_bresp;
input i_bvalid;
input i_bready;
// result out
output o_set_no_wait;
output [P_NUM_OF_BUCKETS-1:0] o_set_bukets;
output o_set_no_more;
output [P_COUNTER_SIZE-1:0] o_counter;
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait;
output [P_BUCKET_SIZE-1:0] o_bukets_0;
output [P_BUCKET_SIZE-1:0] o_bukets_1;
output [P_BUCKET_SIZE-1:0] o_bukets_2;
output [P_BUCKET_SIZE-1:0] o_bukets_3;
output [P_BUCKET_SIZE-1:0] o_bukets_more;
output [P_BUCKET_SIZE-1:0] o_num_of_cmd;
output [P_BUCKET_SIZE-1:0] o_num_of_b;
//////////////////////////////////
// reg
//////////////////////////////////
reg [P_TIMER_WIDTH-1:0] r_timer;
reg r_state;
reg [P_BUCKET_SIZE-1:0] r_bukets[P_NUM_OF_BUCKETS-1:0];
reg [P_BUCKET_SIZE-1:0] r_bukets_no_wait;
reg [P_BUCKET_SIZE-1:0] r_bukets_more;
reg [P_BUCKET_SIZE-1:0] r_num_of_cmd;
reg [P_BUCKET_SIZE-1:0] r_num_of_b;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_fifo_empty;
wire w_fifo_ren;
wire w_set_first;
wire [P_TIMER_WIDTH-1:0] w_timer;
wire w_start;
wire w_clear_len;
wire w_stop;
wire [P_AXI_M_ARLEN-1:0] w_len_inc;
wire w_inc;
wire [P_NUM_OF_BUCKETS-1:0]
w_set;
wire w_set_no_wait;
wire w_set_more;
wire [P_TIMER_WIDTH-1:0] w_timer_diff;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_start = i_wvalid & i_wready;
assign w_clear_len = w_start & (r_state == P_IDLE);
assign w_inc = (r_state == P_RUN) & i_bvalid & i_bready;
assign w_fifo_ren = w_inc ;
assign w_stop = w_inc;
assign w_set_first = w_inc;
assign w_set_no_wait = (r_state == P_IDLE) & w_start &
(w_timer_diff == 'd0);
assign w_set_more = (P_BUCKET_RANGE*P_NUM_OF_BUCKETS <= w_timer_diff) &
w_set_first & !w_fifo_empty;
assign w_timer_diff = (r_timer > w_timer) ? {1'b0,r_timer} - {1'b0,w_timer} :
{1'b1,r_timer} - {1'b0,w_timer};
assign o_bukets_no_wait = r_bukets_no_wait;
assign o_bukets_0 = r_bukets[0];
assign o_bukets_1 = r_bukets[1];
assign o_bukets_2 = r_bukets[2];
assign o_bukets_3 = r_bukets[3];
assign o_bukets_more = r_bukets_more;
assign o_set_no_wait = w_set_no_wait;
assign o_set_bukets = w_set;
assign o_set_no_more = w_set_more;
assign o_counter = w_timer_diff;
assign o_num_of_cmd = r_num_of_cmd;
assign o_num_of_b = r_num_of_b;
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (w_start) begin
r_state <= P_RUN;
end
end
P_RUN: begin
if (w_stop| i_clear) begin
r_state <= P_IDLE;
end
end
endcase
end
end
genvar gi;
generate for (gi=0;gi<P_NUM_OF_BUCKETS;gi=gi+1)begin
assign w_set[gi] = ((P_BUCKET_RANGE*gi <= w_timer_diff) &
(w_timer_diff < P_BUCKET_RANGE*(gi+1))) &
w_set_first & !w_fifo_empty;
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets[gi] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) r_bukets[gi] <= {P_BUCKET_SIZE{1'b0}};
else
if (w_set[gi]) r_bukets[gi] <= r_bukets[gi] + 1'b1;
end
end
end
endgenerate
// special case
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_no_wait <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) r_bukets_no_wait <= {P_BUCKET_SIZE{1'b0}};
else
if (w_set_no_wait) r_bukets_no_wait <= r_bukets_no_wait + 1'b1;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) r_bukets_more <= {P_BUCKET_SIZE{1'b0}};
else
if (w_set_more) r_bukets_more <= r_bukets_more + 1'b1;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_timer <= 'd0;
end else begin
if (i_clear) r_timer <= 'd0;
else r_timer <= r_timer + 1'b1;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_num_of_cmd <= 'd0;
r_num_of_b <= 'd0;
end else begin
if (i_clear) begin
r_num_of_cmd <= 'd0;
r_num_of_b <= 'd0;
end else begin
if (i_wvalid&i_wready) r_num_of_cmd <= r_num_of_cmd + 1'b1;
if (i_bvalid&i_bready) r_num_of_b <= r_num_of_b + 1'b1;
end
end
end
fm_fifo #(.P_WIDTH(P_TIMER_WIDTH),
.P_RANGE(4),
.P_CLEAR("TRUE")) u_fifo (
.clk_core(clk_core),
.rst_x(rst_x | i_clear),
.i_wstrobe(i_wvalid & i_wready),
.i_dt(r_timer),
.o_full(),
.i_renable(w_fifo_ren),
.o_dt(w_timer),
.o_empty(w_fifo_empty),
.o_dnum()
);
endmodule
|
module fm_axi_monitor (
clk_core,
rst_x,
i_stop_trigger,
// AXI write port
i_awid_m,
i_awaddr_m,
i_awlen_m,
i_awsize_m,
i_awburst_m,
i_awlock_m,
i_awcache_m,
i_awuser_m,
i_awprot_m,
i_awvalid_m,
i_awready_m,
i_wid_m,
i_wdata_m,
i_wstrb_m,
i_wlast_m,
i_wvalid_m,
i_wready_m,
i_bid_m,
i_bresp_m,
i_bvalid_m,
i_bready_m,
// AXI read port
i_arid_m,
i_araddr_m,
i_arlen_m,
i_arsize_m,
i_arburst_m,
i_arlock_m,
i_arcache_m,
i_aruser_m,
i_arprot_m,
i_arvalid_m,
i_arready_m,
i_rid_m,
i_rdata_m,
i_rresp_m,
i_rlast_m,
i_rvalid_m,
i_rready_m,
// result out
// awvalid
o_bukets_no_wait_aw,
o_bukets_0_aw,
o_bukets_1_aw,
o_bukets_2_aw,
o_bukets_3_aw,
o_bukets_more_aw,
o_max_count_aw,
o_min_count_aw,
o_bukets_len_0_aw,
o_bukets_len_1_aw,
o_bukets_len_2_aw,
o_bukets_len_3_aw,
o_total_bytes_w,
o_cont_w,
o_discont_w,
o_bukets_nrdy_0_w,
o_bukets_nrdy_1_w,
o_bukets_nrdy_2_w,
o_bukets_nrdy_3_w,
// arvalid
o_bukets_no_wait_ar,
o_bukets_0_ar,
o_bukets_1_ar,
o_bukets_2_ar,
o_bukets_3_ar,
o_bukets_more_ar,
o_max_count_ar,
o_min_count_ar,
o_bukets_len_0_ar,
o_bukets_len_1_ar,
o_bukets_len_2_ar,
o_bukets_len_3_ar,
o_cont_ar,
o_discont_ar,
// wdata
o_bukets_no_wait_b,
o_bukets_0_b,
o_bukets_1_b,
o_bukets_2_b,
o_bukets_3_b,
o_bukets_more_b,
o_num_of_cmd_b,
o_num_of_b,
// rdata
o_bukets_no_wait_r,
o_bukets_0_r,
o_bukets_1_r,
o_bukets_2_r,
o_bukets_3_r,
o_bukets_more_r,
o_total_bytes_r,
o_rd_cont,
o_rd_discont,
o_bukets_nrdy_0_r,
o_bukets_nrdy_1_r,
o_bukets_nrdy_2_r,
o_bukets_nrdy_3_r
);
`include "polyphony_axi_def.v"
localparam P_BUCKET_SIZE = 'd32;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
// system
input clk_core;
input rst_x;
input i_stop_trigger;
// AXI Master
// write port
input [P_AXI_M_AWID-1:0] i_awid_m;
/* (* mark_debug = "true" *)*/ input [P_AXI_M_AWADDR-1:0] i_awaddr_m;
input [P_AXI_M_AWLEN-1:0] i_awlen_m;
input [P_AXI_M_AWSIZE-1:0] i_awsize_m;
input [P_AXI_M_AWBURST-1:0] i_awburst_m;
input [P_AXI_M_AWLOCK-1:0] i_awlock_m;
input [P_AXI_M_AWCACHE-1:0] i_awcache_m;
input [P_AXI_M_AWUSER-1:0] i_awuser_m;
input [P_AXI_M_AWPROT-1:0] i_awprot_m;
input i_awvalid_m;
input i_awready_m;
input [P_AXI_M_WID-1:0] i_wid_m;
input [P_AXI_M_WDATA-1:0] i_wdata_m;
input [P_AXI_M_WSTRB-1:0] i_wstrb_m;
input i_wlast_m;
input i_wvalid_m;
input i_wready_m;
input [P_AXI_M_BID-1:0] i_bid_m;
input [P_AXI_M_BRESP-1:0] i_bresp_m;
input i_bvalid_m;
input i_bready_m;
// read port
input [P_AXI_M_ARID-1:0] i_arid_m;
input [P_AXI_M_ARADDR-1:0] i_araddr_m;
input [P_AXI_M_ARLEN-1:0] i_arlen_m;
input [P_AXI_M_ARSIZE-1:0] i_arsize_m;
input [P_AXI_M_ARBURST-1:0] i_arburst_m;
input [P_AXI_M_ARLOCK-1:0] i_arlock_m;
input [P_AXI_M_ARCACHE-1:0] i_arcache_m;
input [P_AXI_M_ARUSER-1:0] i_aruser_m;
input [P_AXI_M_ARPROT-1:0] i_arprot_m;
input i_arvalid_m;
input i_arready_m;
// read response
input [P_AXI_M_RID-1:0] i_rid_m;
input [P_AXI_M_RDATA-1:0] i_rdata_m;
input [P_AXI_M_RRESP-1:0] i_rresp_m;
input i_rlast_m;
input i_rvalid_m;
input i_rready_m;
// result out
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_0_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_1_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_2_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_3_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_more_aw;
output [P_BUCKET_SIZE-1:0] o_max_count_aw;
output [P_BUCKET_SIZE-1:0] o_min_count_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_len_0_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_len_1_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_len_2_aw;
output [P_BUCKET_SIZE-1:0] o_bukets_len_3_aw;
output [P_BUCKET_SIZE-1:0] o_total_bytes_w;
output [P_BUCKET_SIZE-1:0] o_cont_w;
output [P_BUCKET_SIZE-1:0] o_discont_w;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_0_w;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_1_w;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_2_w;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_3_w;
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_0_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_1_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_2_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_3_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_more_ar;
output [P_BUCKET_SIZE-1:0] o_max_count_ar;
output [P_BUCKET_SIZE-1:0] o_min_count_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_len_0_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_len_1_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_len_2_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_len_3_ar;
output [P_BUCKET_SIZE-1:0] o_cont_ar;
output [P_BUCKET_SIZE-1:0] o_discont_ar;
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait_b;
output [P_BUCKET_SIZE-1:0] o_bukets_0_b;
output [P_BUCKET_SIZE-1:0] o_bukets_1_b;
output [P_BUCKET_SIZE-1:0] o_bukets_2_b;
output [P_BUCKET_SIZE-1:0] o_bukets_3_b;
output [P_BUCKET_SIZE-1:0] o_bukets_more_b;
output [P_BUCKET_SIZE-1:0] o_num_of_cmd_b;
output [P_BUCKET_SIZE-1:0] o_num_of_b;
// rdata
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait_r;
output [P_BUCKET_SIZE-1:0] o_bukets_0_r;
output [P_BUCKET_SIZE-1:0] o_bukets_1_r;
output [P_BUCKET_SIZE-1:0] o_bukets_2_r;
output [P_BUCKET_SIZE-1:0] o_bukets_3_r;
output [P_BUCKET_SIZE-1:0] o_bukets_more_r;
output [P_BUCKET_SIZE-1:0] o_total_bytes_r;
output [P_BUCKET_SIZE-1:0] o_rd_cont;
output [P_BUCKET_SIZE-1:0] o_rd_discont;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_0_r;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_1_r;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_2_r;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_3_r;
//////////
reg [P_BUCKET_SIZE-1:0] r_bukets_no_wait_aw;
reg [P_BUCKET_SIZE-1:0] r_bukets_0_aw;
reg [P_BUCKET_SIZE-1:0] r_bukets_1_aw;
reg [P_BUCKET_SIZE-1:0] r_bukets_2_aw;
reg [P_BUCKET_SIZE-1:0] r_bukets_3_aw;
reg [P_BUCKET_SIZE-1:0] r_bukets_more_aw;
reg [P_BUCKET_SIZE-1:0] r_max_count_aw;
reg [P_BUCKET_SIZE-1:0] r_min_count_aw;
reg [P_BUCKET_SIZE-1:0] r_bukets_len_0_aw;
reg [P_BUCKET_SIZE-1:0] r_bukets_len_1_aw;
reg [P_BUCKET_SIZE-1:0] r_bukets_len_2_aw;
reg [P_BUCKET_SIZE-1:0] r_bukets_len_3_aw;
reg [P_BUCKET_SIZE-1:0] r_total_bytes_w;
reg [P_BUCKET_SIZE-1:0] r_cont_w;
reg [P_BUCKET_SIZE-1:0] r_discont_w;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_0_w;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_1_w;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_2_w;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_3_w;
reg [P_BUCKET_SIZE-1:0] r_bukets_no_wait_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_0_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_1_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_2_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_3_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_more_ar;
reg [P_BUCKET_SIZE-1:0] r_max_count_ar;
reg [P_BUCKET_SIZE-1:0] r_min_count_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_len_0_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_len_1_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_len_2_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_len_3_ar;
reg [P_BUCKET_SIZE-1:0] r_cont_ar;
reg [P_BUCKET_SIZE-1:0] r_discont_ar;
reg [P_BUCKET_SIZE-1:0] r_bukets_no_wait_b;
reg [P_BUCKET_SIZE-1:0] r_bukets_0_b;
reg [P_BUCKET_SIZE-1:0] r_bukets_1_b;
reg [P_BUCKET_SIZE-1:0] r_bukets_2_b;
reg [P_BUCKET_SIZE-1:0] r_bukets_3_b;
reg [P_BUCKET_SIZE-1:0] r_bukets_more_b;
reg [P_BUCKET_SIZE-1:0] r_num_of_cmd_b;
reg [P_BUCKET_SIZE-1:0] r_num_of_b;
// rdata
reg [P_BUCKET_SIZE-1:0] r_bukets_no_wait_r;
reg [P_BUCKET_SIZE-1:0] r_bukets_0_r;
reg [P_BUCKET_SIZE-1:0] r_bukets_1_r;
reg [P_BUCKET_SIZE-1:0] r_bukets_2_r;
reg [P_BUCKET_SIZE-1:0] r_bukets_3_r;
reg [P_BUCKET_SIZE-1:0] r_bukets_more_r;
reg [P_BUCKET_SIZE-1:0] r_total_bytes_r;
reg [P_BUCKET_SIZE-1:0] r_rd_cont;
reg [P_BUCKET_SIZE-1:0] r_rd_discont;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_0_r;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_1_r;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_2_r;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_3_r;
//
wire [P_BUCKET_SIZE-1:0] w_bukets_no_wait_aw;
wire [P_BUCKET_SIZE-1:0] w_bukets_0_aw;
wire [P_BUCKET_SIZE-1:0] w_bukets_1_aw;
wire [P_BUCKET_SIZE-1:0] w_bukets_2_aw;
wire [P_BUCKET_SIZE-1:0] w_bukets_3_aw;
wire [P_BUCKET_SIZE-1:0] w_bukets_more_aw;
wire [P_BUCKET_SIZE-1:0] w_max_count_aw;
wire [P_BUCKET_SIZE-1:0] w_min_count_aw;
wire [P_BUCKET_SIZE-1:0] w_bukets_len_0_aw;
wire [P_BUCKET_SIZE-1:0] w_bukets_len_1_aw;
wire [P_BUCKET_SIZE-1:0] w_bukets_len_2_aw;
wire [P_BUCKET_SIZE-1:0] w_bukets_len_3_aw;
wire [P_BUCKET_SIZE-1:0] w_total_bytes_w;
wire [P_BUCKET_SIZE-1:0] w_cont_w;
wire [P_BUCKET_SIZE-1:0] w_discont_w;
wire [P_BUCKET_SIZE-1:0] w_bukets_nrdy_0_w;
wire [P_BUCKET_SIZE-1:0] w_bukets_nrdy_1_w;
wire [P_BUCKET_SIZE-1:0] w_bukets_nrdy_2_w;
wire [P_BUCKET_SIZE-1:0] w_bukets_nrdy_3_w;
wire [P_BUCKET_SIZE-1:0] w_bukets_no_wait_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_0_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_1_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_2_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_3_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_more_ar;
wire [P_BUCKET_SIZE-1:0] w_max_count_ar;
wire [P_BUCKET_SIZE-1:0] w_min_count_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_len_0_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_len_1_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_len_2_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_len_3_ar;
wire [P_BUCKET_SIZE-1:0] w_cont_ar;
wire [P_BUCKET_SIZE-1:0] w_discont_ar;
wire [P_BUCKET_SIZE-1:0] w_bukets_no_wait_b;
wire [P_BUCKET_SIZE-1:0] w_bukets_0_b;
wire [P_BUCKET_SIZE-1:0] w_bukets_1_b;
wire [P_BUCKET_SIZE-1:0] w_bukets_2_b;
wire [P_BUCKET_SIZE-1:0] w_bukets_3_b;
wire [P_BUCKET_SIZE-1:0] w_bukets_more_b;
wire [P_BUCKET_SIZE-1:0] w_num_of_cmd_b;
wire [P_BUCKET_SIZE-1:0] w_num_of_b;
// rdata
wire [P_BUCKET_SIZE-1:0] w_bukets_no_wait_r;
wire [P_BUCKET_SIZE-1:0] w_bukets_0_r;
wire [P_BUCKET_SIZE-1:0] w_bukets_1_r;
wire [P_BUCKET_SIZE-1:0] w_bukets_2_r;
wire [P_BUCKET_SIZE-1:0] w_bukets_3_r;
wire [P_BUCKET_SIZE-1:0] w_bukets_more_r;
wire [P_BUCKET_SIZE-1:0] w_total_bytes_r;
wire [P_BUCKET_SIZE-1:0] w_rd_cont;
wire [P_BUCKET_SIZE-1:0] w_rd_discont;
wire [P_BUCKET_SIZE-1:0] w_bukets_nrdy_0_r;
wire [P_BUCKET_SIZE-1:0] w_bukets_nrdy_1_r;
wire [P_BUCKET_SIZE-1:0] w_bukets_nrdy_2_r;
wire [P_BUCKET_SIZE-1:0] w_bukets_nrdy_3_r;
assign o_bukets_no_wait_aw = r_bukets_no_wait_aw;
assign o_bukets_0_aw = r_bukets_0_aw;
assign o_bukets_1_aw = r_bukets_1_aw;
assign o_bukets_2_aw = r_bukets_2_aw;
assign o_bukets_3_aw = r_bukets_3_aw;
assign o_bukets_more_aw = r_bukets_more_aw;
assign o_max_count_aw = r_max_count_aw;
assign o_min_count_aw = r_min_count_aw;
assign o_bukets_len_0_aw = r_bukets_len_0_aw;
assign o_bukets_len_1_aw = r_bukets_len_1_aw;
assign o_bukets_len_2_aw = r_bukets_len_2_aw;
assign o_bukets_len_3_aw = r_bukets_len_3_aw;
assign o_total_bytes_w = r_total_bytes_w;
assign o_cont_w = r_cont_w;
assign o_discont_w = r_discont_w;
assign o_bukets_nrdy_0_w = r_bukets_nrdy_0_w;
assign o_bukets_nrdy_1_w = r_bukets_nrdy_1_w;
assign o_bukets_nrdy_2_w = r_bukets_nrdy_2_w;
assign o_bukets_nrdy_3_w = r_bukets_nrdy_3_w;
assign o_bukets_no_wait_ar = r_bukets_no_wait_ar;
assign o_bukets_0_ar = r_bukets_0_ar;
assign o_bukets_1_ar = r_bukets_1_ar;
assign o_bukets_2_ar = r_bukets_2_ar;
assign o_bukets_3_ar = r_bukets_3_ar;
assign o_bukets_more_ar = r_bukets_more_ar;
assign o_max_count_ar = r_max_count_ar;
assign o_min_count_ar = r_min_count_ar;
assign o_bukets_len_0_ar = r_bukets_len_0_ar;
assign o_bukets_len_1_ar = r_bukets_len_1_ar;
assign o_bukets_len_2_ar = r_bukets_len_2_ar;
assign o_bukets_len_3_ar = r_bukets_len_3_ar;
assign o_cont_ar = r_cont_ar;
assign o_discont_ar = r_discont_ar;
assign o_bukets_no_wait_b = r_bukets_no_wait_b;
assign o_bukets_0_b = r_bukets_0_b;
assign o_bukets_1_b = r_bukets_1_b;
assign o_bukets_2_b = r_bukets_2_b;
assign o_bukets_3_b = r_bukets_3_b;
assign o_bukets_more_b = r_bukets_more_b;
assign o_num_of_cmd_b = r_num_of_cmd_b;
assign o_num_of_b = r_num_of_b;
// rdata
assign o_bukets_no_wait_r = r_bukets_no_wait_r;
assign o_bukets_0_r = r_bukets_0_r;
assign o_bukets_1_r = r_bukets_1_r;
assign o_bukets_2_r = r_bukets_2_r;
assign o_bukets_3_r = r_bukets_3_r;
assign o_bukets_more_r = r_bukets_more_r;
assign o_total_bytes_r = r_total_bytes_r;
assign o_rd_cont = r_rd_cont;
assign o_rd_discont = r_rd_discont;
assign o_bukets_nrdy_0_r = r_bukets_nrdy_0_r;
assign o_bukets_nrdy_1_r = r_bukets_nrdy_1_r;
assign o_bukets_nrdy_2_r = r_bukets_nrdy_2_r;
assign o_bukets_nrdy_3_r = r_bukets_nrdy_3_r;
always @(posedge clk_core) begin
if (!i_stop_trigger) begin
r_bukets_no_wait_aw <= w_bukets_no_wait_aw;
r_bukets_0_aw <= w_bukets_0_aw;
r_bukets_1_aw <= w_bukets_1_aw;
r_bukets_2_aw <= w_bukets_2_aw;
r_bukets_3_aw <= w_bukets_3_aw;
r_bukets_more_aw <= w_bukets_more_aw;
r_max_count_aw <= w_max_count_aw;
r_min_count_aw <= w_min_count_aw;
r_bukets_len_0_aw <= w_bukets_len_0_aw;
r_bukets_len_1_aw <= w_bukets_len_1_aw;
r_bukets_len_2_aw <= w_bukets_len_2_aw;
r_bukets_len_3_aw <= w_bukets_len_3_aw;
r_total_bytes_w <= w_total_bytes_w;
r_cont_w <= w_cont_w;
r_discont_w <= w_discont_w;
r_bukets_nrdy_0_w <= w_bukets_nrdy_0_w;
r_bukets_nrdy_1_w <= w_bukets_nrdy_1_w;
r_bukets_nrdy_2_w <= w_bukets_nrdy_2_w;
r_bukets_nrdy_3_w <= w_bukets_nrdy_3_w;
r_bukets_no_wait_ar <= w_bukets_no_wait_ar;
r_bukets_0_ar <= w_bukets_0_ar;
r_bukets_1_ar <= w_bukets_1_ar;
r_bukets_2_ar <= w_bukets_2_ar;
r_bukets_3_ar <= w_bukets_3_ar;
r_bukets_more_ar <= w_bukets_more_ar;
r_max_count_ar <= w_max_count_ar;
r_min_count_ar <= w_min_count_ar;
r_bukets_len_0_ar <= w_bukets_len_0_ar;
r_bukets_len_1_ar <= w_bukets_len_1_ar;
r_bukets_len_2_ar <= w_bukets_len_2_ar;
r_bukets_len_3_ar <= w_bukets_len_3_ar;
r_cont_ar <= w_cont_ar;
r_discont_ar <= w_discont_ar;
r_bukets_no_wait_b <= w_bukets_no_wait_b;
r_bukets_0_b <= w_bukets_0_b;
r_bukets_1_b <= w_bukets_1_b;
r_bukets_2_b <= w_bukets_2_b;
r_bukets_3_b <= w_bukets_3_b;
r_bukets_more_b <= w_bukets_more_b;
r_num_of_cmd_b <= w_num_of_cmd_b;
r_num_of_b <= w_num_of_b;
// rdata
r_bukets_no_wait_r <= w_bukets_no_wait_r;
r_bukets_0_r <= w_bukets_0_r;
r_bukets_1_r <= w_bukets_1_r;
r_bukets_2_r <= w_bukets_2_r;
r_bukets_3_r <= w_bukets_3_r;
r_bukets_more_r <= w_bukets_more_r;
r_total_bytes_r <= w_total_bytes_r;
r_rd_cont <= w_rd_cont;
r_rd_discont <= w_rd_discont;
r_bukets_nrdy_0_r <= w_bukets_nrdy_0_r;
r_bukets_nrdy_1_r <= w_bukets_nrdy_1_r;
r_bukets_nrdy_2_r <= w_bukets_nrdy_2_r;
r_bukets_nrdy_3_r <= w_bukets_nrdy_3_r;
end
end
//////////////////////////////////
// module instance
//////////////////////////////////
// awvalid - awready
fm_axi_monitor_vw u_mon_awvalid (
.clk_core(clk_core),
.rst_x(rst_x),
.i_start(i_awvalid_m),
.i_clear(1'b0),
.i_stop(i_awready_m),
.i_alen(i_awlen_m),
.i_wvalid(i_wvalid_m),
.i_wlast(i_wlast_m),
.i_wready(i_wready_m),
// result out
.o_set_no_wait(),
.o_set_bukets(),
.o_set_no_more(),
.o_counter(),
.o_bukets_no_wait(w_bukets_no_wait_aw), // awvalid no wait
.o_bukets_0(w_bukets_0_aw), // awvarid accept range
.o_bukets_1(w_bukets_1_aw),
.o_bukets_2(w_bukets_2_aw),
.o_bukets_3(w_bukets_3_aw),
.o_bukets_more(w_bukets_more_aw),
.o_max_count(w_max_count_aw), // max accept cycle
.o_min_count(w_min_count_aw), // min accept cycle
.o_bukets_len_0(w_bukets_len_0_aw),
.o_bukets_len_1(w_bukets_len_1_aw),
.o_bukets_len_2(w_bukets_len_2_aw),
.o_bukets_len_3(w_bukets_len_3_aw),
.o_total_bytes(w_total_bytes_w),
.o_bukets_nrdy_0(w_bukets_nrdy_0_w),
.o_bukets_nrdy_1(w_bukets_nrdy_1_w),
.o_bukets_nrdy_2(w_bukets_nrdy_2_w),
.o_bukets_nrdy_3(w_bukets_nrdy_3_w),
.o_wr_cont(w_cont_w),
.o_wr_discont(w_discont_w)
);
// arvalid - arready
fm_axi_monitor_vr u_mon_arvalid (
.clk_core(clk_core),
.rst_x(rst_x),
.i_start(i_arvalid_m),
.i_clear(1'b0),
.i_stop(i_arready_m),
.i_alen(i_arlen_m),
// result out
.o_set_no_wait(),
.o_set_bukets(),
.o_set_no_more(),
.o_counter(),
.o_bukets_no_wait(w_bukets_no_wait_ar),
.o_bukets_0(w_bukets_0_ar),
.o_bukets_1(w_bukets_1_ar),
.o_bukets_2(w_bukets_2_ar),
.o_bukets_3(w_bukets_3_ar),
.o_bukets_more(w_bukets_more_ar),
.o_max_count(w_max_count_ar), // max accept cycle
.o_min_count(w_min_count_ar), // min accept cycle
.o_bukets_len_0(w_bukets_len_0_ar),
.o_bukets_len_1(w_bukets_len_1_ar),
.o_bukets_len_2(w_bukets_len_2_ar),
.o_bukets_len_3(w_bukets_len_3_ar)
);
// wvalid & wlast & wready - bvalid & bready
fm_axi_monitor_b u_mon_bvalid (
.clk_core(clk_core),
.rst_x(rst_x),
.i_clear(1'b0),
.i_wvalid(i_wvalid_m & i_wlast_m),
.i_wready(i_wready_m),
.i_bid(i_bid_m),
.i_bresp(i_bresp_m),
.i_bvalid(i_bvalid_m),
.i_bready(i_bready_m),
// result out
.o_set_no_wait(),
.o_set_bukets(),
.o_set_no_more(),
.o_counter(),
.o_bukets_no_wait(w_bukets_no_wait_b),
.o_bukets_0(w_bukets_0_b),
.o_bukets_1(w_bukets_1_b),
.o_bukets_2(w_bukets_2_b),
.o_bukets_3(w_bukets_3_b),
.o_bukets_more(w_bukets_more_b),
.o_num_of_cmd(w_num_of_cmd_b),
.o_num_of_b(w_num_of_b)
);
// arvalid&arready - rvalid & rready
fm_axi_monitor_r u_mon_read (
.clk_core(clk_core),
.rst_x(rst_x),
.i_clear(1'b0),
.i_arvalid(i_arvalid_m),
.i_arready(i_arready_m),
.i_arlen(i_arlen_m),
.i_rresp(i_rresp_m),
.i_rlast(i_rlast_m),
.i_rvalid(i_rvalid_m),
.i_rready(i_rready_m),
// result out
.o_set_no_wait(),
.o_set_bukets(),
.o_set_no_more(),
.o_timer(),
.o_bukets_no_wait(w_bukets_no_wait_r),
.o_bukets_0(w_bukets_0_r),
.o_bukets_1(w_bukets_1_r),
.o_bukets_2(w_bukets_2_r),
.o_bukets_3(w_bukets_3_r),
.o_bukets_more(w_bukets_more_r),
.o_rvalid_invalid_cycles(),
.o_state(),
.o_len(),
.o_total_bytes(w_total_bytes_r),
.o_rd_cont(w_rd_cont),
.o_rd_discont(w_rd_discont),
.o_bukets_nrdy_0(w_bukets_nrdy_0_r),
.o_bukets_nrdy_1(w_bukets_nrdy_1_r),
.o_bukets_nrdy_2(w_bukets_nrdy_2_r),
.o_bukets_nrdy_3(w_bukets_nrdy_3_r)
);
`ifdef RTL_DEBUG
`else
/*
wire [35:0] CONTROL0;
wire [95:0] TRIG0;
wire [549:0] DATA;
chipscope_icon_v1_06_a_0 u_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_v1_05_a_0 u_chipscope (
.CONTROL(CONTROL0),
.CLK(clk_core),
.TRIG0(TRIG0),
.DATA(DATA)
);
assign DATA[15:0] = o_bukets_no_wait_w[15:0];
assign DATA[31:16] = o_bukets_0_w[15:0];
assign DATA[47:32] = o_bukets_1_w[15:0];
assign DATA[63:48] = o_bukets_2_w[15:0];
assign DATA[79:64] = o_bukets_3_w[15:0];
assign DATA[95:80] = o_bukets_more_w[15:0];
assign DATA[111:96] = o_bukets_no_wait_r[15:0];
assign DATA[127:112] = o_bukets_0_r[15:0];
assign DATA[143:128] = o_bukets_1_r[15:0];
assign DATA[159:144] = o_bukets_2_r[15:0];
assign DATA[175:160] = o_bukets_3_r[15:0];
assign DATA[191:176] = o_bukets_more_r[15:0];
assign DATA[207:192] = o_bukets_no_wait_b[15:0];
assign DATA[223:208] = o_bukets_0_b[15:0];
assign DATA[239:224] = o_bukets_1_b[15:0];
assign DATA[255:240] = o_bukets_2_b[15:0];
assign DATA[271:256] = o_bukets_3_b[15:0];
assign DATA[287:272] = o_bukets_more_b[15:0];
assign DATA[303:288] = o_bukets_no_wait_rr[15:0];
assign DATA[319:304] = o_bukets_0_rr[15:0];
assign DATA[335:320] = o_bukets_1_rr[15:0];
assign DATA[351:336] = o_bukets_2_rr[15:0];
assign DATA[367:352] = o_bukets_3_rr[15:0];
assign DATA[383:368] = o_bukets_more_rr[15:0];
assign DATA[384] = w_set_no_wait_w;
assign DATA[388:385] = w_set_bukets_w[3:0];
assign DATA[389] = w_set_no_more_w;
assign DATA[405:390] = w_counter_w[15:0];
assign DATA[406] = w_set_no_wait_r;
assign DATA[410:407] = w_set_bukets_r[3:0];
assign DATA[411] = w_set_no_more_r;
assign DATA[427:412] = w_counter_r[15:0];
assign DATA[428] = w_set_no_wait_b;
assign DATA[432:429] = w_set_bukets_b[3:0];
assign DATA[433] = w_set_no_more_b;
assign DATA[449:434] = w_counter_b[15:0];
assign DATA[450] = w_set_no_wait_rr;
assign DATA[454:451] = w_set_bukets_rr[3:0];
assign DATA[455] = w_set_no_more_rr;
assign DATA[467:456] = w_timer_rr[11:0];
assign DATA[483:468] = w_num_of_cmd_w[15:0];
assign DATA[499:484] = w_num_of_b[15:0];
assign DATA[500] = i_awvalid_m;
assign DATA[501] = i_awready_m;
assign DATA[502] = i_wlast_m;
assign DATA[503] = i_wvalid_m;
assign DATA[504] = i_wready_m;
assign DATA[505] = i_bvalid_m;
assign DATA[506] = i_bready_m;
assign DATA[507] = i_arvalid_m;
assign DATA[508] = i_arready_m;
assign DATA[509] = i_rvalid_m;
assign DATA[510] = i_rready_m;
assign DATA[526:511] = r_wvalid_no_wready_cnt[15:0];
assign DATA[542:527] = w_rvalid_invalid_cycles[15:0];
assign DATA[543] = i_rlast_m;
assign DATA[544] = w_state;
assign DATA[549:545] = w_len;
assign TRIG0[0] = i_awvalid_m;
assign TRIG0[1] = i_awready_m;
assign TRIG0[2] = i_wlast_m;
assign TRIG0[3] = i_wvalid_m;
assign TRIG0[4] = i_wready_m;
assign TRIG0[5] = i_bvalid_m;
assign TRIG0[6] = i_bready_m;
assign TRIG0[7] = i_arvalid_m;
assign TRIG0[8] = i_arready_m;
assign TRIG0[9] = i_rvalid_m;
assign TRIG0[10] = i_rready_m;
assign TRIG0[11] = w_set_no_wait_w;
assign TRIG0[15:12] = w_set_bukets_w[3:0];
assign TRIG0[16] = w_set_no_more_w;
assign TRIG0[32:17] = w_counter_w[15:0];
assign TRIG0[33] = w_set_no_wait_r;
assign TRIG0[37:34] = w_set_bukets_r[3:0];
assign TRIG0[38] = w_set_no_more_r;
assign TRIG0[54:39] = w_counter_r[15:0];
assign TRIG0[55] = w_set_no_wait_b;
assign TRIG0[59:56] = w_set_bukets_b[3:0];
assign TRIG0[60] = w_set_no_more_b;
assign TRIG0[76:61] = w_counter_b[15:0];
assign TRIG0[77] = w_set_no_wait_rr;
assign TRIG0[81:78] = w_set_bukets_rr[3:0];
assign TRIG0[82] = w_set_no_more_rr;
assign TRIG0[94:83] = w_timer_rr[11:0];
assign TRIG0[95] = i_stop_trigger;
*/
`endif
endmodule
|
module fm_raw_fifo (
clk_core,
rst_x,
i_check_address,
o_hit,
i_wstrobe,
i_dt,
o_full,
i_renable,
o_dt,
o_empty,
o_dnum
);
// set default parameters
parameter WIDTH = 32;
parameter RANGEE = 4;
localparam DEPTH = 1 << RANGEE;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core; // system clock
input rst_x; // system reset
input [WIDTH-1:0] i_check_address;
output o_hit;
input i_wstrobe; // write strobe
input [WIDTH-1:0] i_dt; // write data
output o_full; // write data full
input i_renable; // read enable
output [WIDTH-1:0] o_dt; // read data
output o_empty; // read data empty
output [RANGEE:0] o_dnum; // written data number
/////////////////////////
// Register definition
/////////////////////////
reg [RANGEE-1:0] rs_write_counter;
reg [RANGEE-1:0] rs_read_counter;
// data registers
reg [WIDTH-1:0] rs_data_buffer[0:DEPTH-1];
reg [DEPTH-1:0] rs_valid;
/////////////////////////
// wire definition
/////////////////////////
wire o_full;
wire o_empty;
wire [WIDTH-1:0] o_dt;
wire [1:0] w_status;
wire w_we;
wire w_re;
// address compare
wire [DEPTH-1:0] w_hit;
/////////////////////////
// assign statement
/////////////////////////
assign o_full = (&rs_valid);
assign o_empty = ~(|rs_valid);
assign o_dt = rs_data_buffer[rs_read_counter];
assign o_dnum = 'd0;
assign w_we = !o_full & i_wstrobe;
assign w_re = i_renable & !o_empty;
assign w_status = {w_re,w_we};
assign o_hit = |w_hit;
////////////////////////
// always statement
///////////////////////
genvar i;
generate for (i=0;i<DEPTH;i=i+1) begin : gen_loop
assign w_hit[i] = rs_valid[i] ? (i_check_address == rs_data_buffer[i]) : 1'b0;
end
endgenerate
// write side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_write_counter <= 'd0;
end else begin
if (w_we) begin
rs_write_counter <= rs_write_counter + 1'b1;
end
end
end
always @(posedge clk_core) begin
if (w_we) begin
rs_data_buffer[rs_write_counter] <= i_dt;
end
end
// read side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_read_counter <= 'd0;
end else begin
if (w_re) begin
rs_read_counter <= rs_read_counter + 1'b1;
end
end
end
// data valid
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_valid <= {DEPTH{1'b0}};
end else begin
case (w_status)
2'b01: rs_valid[rs_write_counter] <= 1'b1; // write
2'b10: rs_valid[rs_read_counter] <= 1'b0; // read
2'b11: begin
rs_valid[rs_write_counter] <= 1'b1; // write
rs_valid[rs_read_counter] <= 1'b0; // read
end
default: rs_valid <= rs_valid; // nothing to do
endcase
end
end
endmodule
|
module fm_axi_monitor_vr (
clk_core,
rst_x,
i_start,
i_clear,
i_stop,
i_alen,
// result out
o_set_no_wait,
o_set_bukets,
o_set_no_more,
o_counter,
o_bukets_no_wait,
o_bukets_0,
o_bukets_1,
o_bukets_2,
o_bukets_3,
o_bukets_more,
o_max_count,
o_min_count,
o_bukets_len_0,
o_bukets_len_1,
o_bukets_len_2,
o_bukets_len_3
);
`include "polyphony_axi_def.v"
//////////////////////////////////
// parameter definition
//////////////////////////////////
localparam P_NUM_OF_BUCKETS = 'd4;
localparam P_BUCKET_RANGE = 'd1;
localparam P_BUCKET_SIZE = 'd32;
localparam P_COUNTER_SIZE = 'd32;
localparam P_IDLE = 1'b0;
localparam P_RUN = 1'b1;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
input i_start;
input i_clear;
input i_stop;
input [P_AXI_M_ARLEN-1:0] i_alen;
// result out
output o_set_no_wait;
output [P_NUM_OF_BUCKETS-1:0] o_set_bukets;
output o_set_no_more;
output [P_COUNTER_SIZE-1:0] o_counter;
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait;
output [P_BUCKET_SIZE-1:0] o_bukets_0;
output [P_BUCKET_SIZE-1:0] o_bukets_1;
output [P_BUCKET_SIZE-1:0] o_bukets_2;
output [P_BUCKET_SIZE-1:0] o_bukets_3;
output [P_BUCKET_SIZE-1:0] o_bukets_more;
output [P_COUNTER_SIZE-1:0] o_max_count;
output [P_COUNTER_SIZE-1:0] o_min_count;
output [P_BUCKET_SIZE-1:0] o_bukets_len_0;
output [P_BUCKET_SIZE-1:0] o_bukets_len_1;
output [P_BUCKET_SIZE-1:0] o_bukets_len_2;
output [P_BUCKET_SIZE-1:0] o_bukets_len_3;
//////////////////////////////////
// reg
//////////////////////////////////
reg [P_BUCKET_SIZE-1:0] r_bukets[P_NUM_OF_BUCKETS-1:0];
reg [P_BUCKET_SIZE-1:0] r_bukets_len[P_NUM_OF_BUCKETS-1:0];
reg [P_BUCKET_SIZE-1:0] r_bukets_no_wait;
reg [P_BUCKET_SIZE-1:0] r_bukets_more;
reg [P_COUNTER_SIZE-1:0] r_counter;
reg r_state;
reg [P_COUNTER_SIZE-1:0] r_max_count;
reg [P_COUNTER_SIZE-1:0] r_min_count;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_inc;
wire [P_NUM_OF_BUCKETS-1:0]
w_set;
wire [P_NUM_OF_BUCKETS-1:0]
w_set_len;
wire w_set_no_wait;
wire w_set_more;
wire w_start;
wire [P_COUNTER_SIZE-1:0] w_counter_inc;
wire w_set_max_min;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_inc = (r_state == P_RUN);
assign w_set_no_wait = (r_state == P_IDLE) & i_start & i_stop;
assign w_set_more = (P_BUCKET_RANGE*P_NUM_OF_BUCKETS <= w_counter_inc) &
((r_state == P_RUN) & i_stop);
assign w_start = (r_state == P_IDLE) & i_start & (!i_stop);
assign w_counter_inc = (r_state == P_IDLE) ? 'd0 : r_counter + 1'b1;
assign w_set_max_min = w_set_no_wait | ((r_state == P_RUN) & i_stop);
assign o_bukets_no_wait = r_bukets_no_wait;
assign o_bukets_0 = r_bukets[0];
assign o_bukets_1 = r_bukets[1];
assign o_bukets_2 = r_bukets[2];
assign o_bukets_3 = r_bukets[3];
assign o_bukets_more = r_bukets_more;
assign o_set_no_wait = w_set_no_wait;
assign o_set_bukets = w_set;
assign o_set_no_more = w_set_more;
assign o_counter = r_counter;
assign o_max_count = r_max_count;
assign o_min_count = r_min_count;
assign o_bukets_len_0 = r_bukets_len[0];
assign o_bukets_len_1 = r_bukets_len[1];
assign o_bukets_len_2 = r_bukets_len[2];
assign o_bukets_len_3 = r_bukets_len[3];
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (i_start) begin
if (!i_stop) r_state <= P_RUN;
end
end
P_RUN: begin
if (i_stop|i_clear) begin
r_state <= P_IDLE;
end
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_counter <= {P_COUNTER_SIZE{1'b0}};
end else begin
if (w_start|i_clear) begin
r_counter <= {P_COUNTER_SIZE{1'b0}};
end else begin
if (w_inc) r_counter <= w_counter_inc;
end
end
end
genvar gi;
generate for (gi=0;gi<P_NUM_OF_BUCKETS;gi=gi+1)begin
assign w_set[gi] = ((P_BUCKET_RANGE*gi <= w_counter_inc) &
(w_counter_inc < P_BUCKET_RANGE*(gi+1))) &
(((r_state == P_IDLE) & i_start & i_stop) |
((r_state == P_RUN) & i_stop));
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets[gi] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets[gi] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set[gi]) r_bukets[gi] <= r_bukets[gi] + 1'b1;
end
end
end
end
endgenerate
// special case
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_no_wait <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets_no_wait <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set_no_wait) r_bukets_no_wait <= r_bukets_no_wait + 1'b1;
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set_more) r_bukets_more <= r_bukets_more + 1'b1;
end
end
end
// max min
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_max_count <= {P_COUNTER_SIZE{1'b0}};
r_min_count <= {P_COUNTER_SIZE{1'b1}};
end else begin
if (i_clear) begin
r_max_count <= {P_COUNTER_SIZE{1'b0}};
r_min_count <= {P_COUNTER_SIZE{1'b1}};
end else begin
if ( w_set_max_min) begin
if (!w_set_no_wait)
if (w_counter_inc > r_max_count) r_max_count <= w_counter_inc;
if (w_set_no_wait) r_min_count <= 'd0;
else if (w_counter_inc < r_min_count) r_min_count <= w_counter_inc;
end
end
end
end
genvar gj;
generate for (gj=0;gj<P_NUM_OF_BUCKETS;gj=gj+1)begin
assign w_set_len[gj] = ((P_BUCKET_RANGE*gj <= i_alen) &
(i_alen < P_BUCKET_RANGE*(gj+1))) &
(((r_state == P_IDLE) & i_start & i_stop) |
((r_state == P_RUN) & i_stop));
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_len[gj] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets_len[gj] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set_len[gj]) r_bukets_len [gj] <= r_bukets_len[gj] + 1'b1;
end
end
end
end
endgenerate
endmodule
|
module fm_axi_monitor_vw (
clk_core,
rst_x,
i_start,
i_clear,
i_stop,
i_alen,
i_wvalid,
i_wlast,
i_wready,
// result out
o_set_no_wait,
o_set_bukets,
o_set_no_more,
o_counter,
o_bukets_no_wait,
o_bukets_0,
o_bukets_1,
o_bukets_2,
o_bukets_3,
o_bukets_more,
o_max_count,
o_min_count,
o_bukets_len_0,
o_bukets_len_1,
o_bukets_len_2,
o_bukets_len_3,
o_total_bytes,
o_bukets_nrdy_0,
o_bukets_nrdy_1,
o_bukets_nrdy_2,
o_bukets_nrdy_3,
o_wr_cont,
o_wr_discont
);
`include "polyphony_axi_def.v"
//////////////////////////////////
// parameter definition
//////////////////////////////////
localparam P_NUM_OF_BUCKETS = 'd4;
localparam P_BUCKET_RANGE = 'd1;
localparam P_BUCKET_SIZE = 'd32;
localparam P_COUNTER_SIZE = 'd32;
localparam P_IDLE = 1'b0;
localparam P_RUN = 1'b1;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
input i_start;
input i_clear;
input i_stop;
input [P_AXI_M_ARLEN-1:0] i_alen;
input i_wvalid;
input i_wlast;
input i_wready;
// result out
output o_set_no_wait;
output [P_NUM_OF_BUCKETS-1:0] o_set_bukets;
output o_set_no_more;
output [P_COUNTER_SIZE-1:0] o_counter;
output [P_BUCKET_SIZE-1:0] o_bukets_no_wait;
output [P_BUCKET_SIZE-1:0] o_bukets_0;
output [P_BUCKET_SIZE-1:0] o_bukets_1;
output [P_BUCKET_SIZE-1:0] o_bukets_2;
output [P_BUCKET_SIZE-1:0] o_bukets_3;
output [P_BUCKET_SIZE-1:0] o_bukets_more;
output [P_COUNTER_SIZE-1:0] o_max_count;
output [P_COUNTER_SIZE-1:0] o_min_count;
output [P_BUCKET_SIZE-1:0] o_bukets_len_0;
output [P_BUCKET_SIZE-1:0] o_bukets_len_1;
output [P_BUCKET_SIZE-1:0] o_bukets_len_2;
output [P_BUCKET_SIZE-1:0] o_bukets_len_3;
output [P_BUCKET_SIZE-1:0] o_total_bytes;
output [P_BUCKET_SIZE-1:0] o_wr_cont;
output [P_BUCKET_SIZE-1:0] o_wr_discont;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_0;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_1;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_2;
output [P_BUCKET_SIZE-1:0] o_bukets_nrdy_3;
//////////////////////////////////
// reg
//////////////////////////////////
reg [P_BUCKET_SIZE-1:0] r_bukets[P_NUM_OF_BUCKETS-1:0];
reg [P_BUCKET_SIZE-1:0] r_bukets_len[P_NUM_OF_BUCKETS-1:0];
reg [P_BUCKET_SIZE-1:0] r_bukets_no_wait;
reg [P_BUCKET_SIZE-1:0] r_bukets_more;
reg [P_COUNTER_SIZE-1:0] r_counter;
reg [P_COUNTER_SIZE-1:0] r_nrdy_counter;
reg r_state;
reg [P_COUNTER_SIZE-1:0] r_max_count;
reg [P_COUNTER_SIZE-1:0] r_min_count;
reg r_disc_flag;
reg [P_BUCKET_SIZE-1:0] r_wr_cont;
reg [P_BUCKET_SIZE-1:0] r_wr_discont;
reg [P_BUCKET_SIZE-1:0] r_total_bytes;
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy[P_NUM_OF_BUCKETS-1:0];
reg [P_BUCKET_SIZE-1:0] r_bukets_nrdy_more;
// wire
//////////////////////////////////
wire w_inc;
wire [P_NUM_OF_BUCKETS-1:0]
w_set;
wire [P_NUM_OF_BUCKETS-1:0]
w_set_len;
wire [P_NUM_OF_BUCKETS-1:0]
w_set_nrdy;
wire w_set_no_wait;
wire w_set_more;
wire w_start;
wire [P_COUNTER_SIZE-1:0] w_counter_inc;
wire w_set_nrdy_more;
wire w_set_max_min;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_inc = (r_state == P_RUN);
assign w_set_no_wait = (r_state == P_IDLE) & i_start & i_stop;
assign w_set_more = (P_BUCKET_RANGE*P_NUM_OF_BUCKETS <= w_counter_inc) &
((r_state == P_RUN) & i_stop);
assign w_start = (r_state == P_IDLE) & i_start & (!i_stop);
assign w_counter_inc = (r_state == P_IDLE) ? 'd0 : r_counter + 1'b1;
assign w_set_max_min = w_set_no_wait | ((r_state == P_RUN) & i_stop);
assign o_bukets_no_wait = r_bukets_no_wait;
assign o_bukets_0 = r_bukets[0];
assign o_bukets_1 = r_bukets[1];
assign o_bukets_2 = r_bukets[2];
assign o_bukets_3 = r_bukets[3];
assign o_bukets_more = r_bukets_more;
assign o_set_no_wait = w_set_no_wait;
assign o_set_bukets = w_set;
assign o_set_no_more = w_set_more;
assign o_counter = r_counter;
assign o_max_count = r_max_count;
assign o_min_count = r_min_count;
assign o_bukets_len_0 = r_bukets_len[0];
assign o_bukets_len_1 = r_bukets_len[1];
assign o_bukets_len_2 = r_bukets_len[2];
assign o_bukets_len_3 = r_bukets_len[3];
assign o_wr_cont = r_wr_cont;
assign o_wr_discont = r_wr_discont;
// assign o_total_bytes = r_total_bytes;
assign o_total_bytes = r_bukets_nrdy_more;
assign o_bukets_nrdy_0 = r_bukets_nrdy[0];
assign o_bukets_nrdy_1 = r_bukets_nrdy[1];
assign o_bukets_nrdy_2 = r_bukets_nrdy[2];
assign o_bukets_nrdy_3 = r_bukets_nrdy[3];
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (i_start) begin
if (!i_stop) r_state <= P_RUN;
end
end
P_RUN: begin
if (i_stop|i_clear) begin
r_state <= P_IDLE;
end
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_counter <= {P_COUNTER_SIZE{1'b0}};
end else begin
if (w_start) begin
r_counter <= {P_COUNTER_SIZE{1'b0}};;
end else begin
if (w_inc) r_counter <= w_counter_inc;
end
end
end
genvar gi;
generate for (gi=0;gi<P_NUM_OF_BUCKETS;gi=gi+1)begin
assign w_set[gi] = ((P_BUCKET_RANGE*gi <= w_counter_inc) &
(w_counter_inc < P_BUCKET_RANGE*(gi+1))) &
(((r_state == P_IDLE) & i_start & i_stop) |
((r_state == P_RUN) & i_stop));
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets[gi] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets[gi] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set[gi]) r_bukets[gi] <= r_bukets[gi] + 1'b1;
end
end
end
end
endgenerate
// special case
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_no_wait <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets_no_wait <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set_no_wait) r_bukets_no_wait <= r_bukets_no_wait + 1'b1;
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set_more) r_bukets_more <= r_bukets_more + 1'b1;
end
end
end
// max min
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_max_count <= {P_COUNTER_SIZE{1'b0}};
r_min_count <= {P_COUNTER_SIZE{1'b1}};
end else begin
if (i_clear) begin
r_max_count <= {P_COUNTER_SIZE{1'b0}};
r_min_count <= {P_COUNTER_SIZE{1'b1}};
end else begin
if ( w_set_max_min) begin
if (!w_set_no_wait)
if (w_counter_inc > r_max_count) r_max_count <= w_counter_inc;
if (w_set_no_wait) r_min_count <= 'd0;
else if (w_counter_inc < r_min_count) r_min_count <= w_counter_inc;
end
end
end
end
genvar gj;
generate for (gj=0;gj<P_NUM_OF_BUCKETS;gj=gj+1)begin
assign w_set_len[gj] = ((P_BUCKET_RANGE*gj <= i_alen) &
(i_alen < P_BUCKET_RANGE*(gj+1))) &
(((r_state == P_IDLE) & i_start & i_stop) |
((r_state == P_RUN) & i_stop));
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_len[gj] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets_len[gj] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set_len[gj]) r_bukets_len [gj] <= r_bukets_len[gj] + 1'b1;
end
end
end
end
endgenerate
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_nrdy_counter <= 1'd0;
end else begin
if (i_clear)
r_nrdy_counter <= 1'd0;
else if (i_wvalid & i_wready & i_wlast)
r_nrdy_counter <= 1'd0;
else if (i_wvalid & !i_wready)
r_nrdy_counter <= r_nrdy_counter + 1'b1;
end
end
genvar gk;
generate for (gk=0;gk<P_NUM_OF_BUCKETS;gk=gk+1)begin
assign w_set_nrdy[gk] = ((P_BUCKET_RANGE*gk <= r_nrdy_counter) &
(r_nrdy_counter < P_BUCKET_RANGE*(gk+1))) &
(i_wvalid & i_wready & i_wlast);
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_nrdy[gk] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets_nrdy[gk] <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set_nrdy[gk]) r_bukets_nrdy[gk] <= r_bukets_nrdy[gk] + 1'b1;
end
end
end
end
endgenerate
assign w_set_nrdy_more = (P_BUCKET_RANGE*P_NUM_OF_BUCKETS <= r_nrdy_counter) &
(i_wvalid & i_wready & i_wlast);
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bukets_nrdy_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (i_clear) begin
r_bukets_nrdy_more <= {P_BUCKET_SIZE{1'b0}};
end else begin
if (w_set_nrdy_more) r_bukets_nrdy_more <= r_bukets_nrdy_more + 1'b1;
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_disc_flag <= 1'b0;
end else begin
if (i_clear)
r_disc_flag <= 1'b0;
else if (i_wvalid & i_wready & i_wlast) begin
r_disc_flag <= 1'b0;
end else begin
// awvalid is already accepted
if (i_wvalid & !i_start & !i_wready ) r_disc_flag <= 1'b1;
end
end
end // always @ (posedge clk_core or negedge rst_x)
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_wr_cont <= 'd0;
r_wr_discont <= 'd0;
end else begin
if (i_clear) begin
r_wr_cont <= 'd0;
r_wr_discont <= 'd0;
end else
if (i_wvalid & i_wready & i_wlast) begin
if (r_disc_flag) r_wr_discont <= r_wr_discont + 1'b1;
else r_wr_cont <= r_wr_cont + 1'b1;
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_total_bytes <= 'd0;
end else begin
if (i_clear)
r_total_bytes <= 'd0;
else if (i_wvalid&i_wready) r_total_bytes <= r_total_bytes + 1'b1;
end
end
endmodule
|
module fm_cmn_cinterface (
clk_core,
rst_x,
// bus side port
i_bstr,
i_bdata,
o_back,
// internal port
o_istr,
o_idata,
i_iack
);
parameter P_WIDTH = 8;
////////////////////////////
// I/O definitions
////////////////////////////
input i_bstr; // input strobe
input [P_WIDTH-1:0]
i_bdata; // input data
output o_back; // output acknowledge
output o_istr; // output strobe
output [P_WIDTH-1:0]
o_idata; // output data
input i_iack; // input acknowledge
input clk_core; // system clock
input rst_x; // system reset
/////////////////////////
// register definition
/////////////////////////
// input register
reg r_bstr;
reg [P_WIDTH-1:0]
r_bdata;
reg r_back;
/////////////////////////
// wire definition
/////////////////////////
wire w_empty;
/////////////////////////
// assign statement
/////////////////////////
assign o_istr = !w_empty;
assign o_back = r_back;
/////////////////////////
// always statement
/////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bstr <= 1'b0;
end else begin
r_bstr <= i_bstr;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_back <= 1'b0;
end else begin
r_back <= i_iack;
end
end
always @(posedge clk_core) begin
r_bdata <= i_bdata;
end
/////////////////////////
// module instanciation
/////////////////////////
// input data fifo
fm_cmn_ififo #(P_WIDTH) u_ififo (
//fm_cmn_bififo #(P_WIDTH,3) fifo (
// .o_dnum(),
.i_wstrobe(r_bstr),
.i_dt(r_bdata),
.o_full(),
.i_renable(i_iack),
.o_dt(o_idata),
.o_empty(w_empty),
.clk_core(clk_core),
.rst_x(rst_x)
);
endmodule
|
module fm_cmn_if_ff_out (
clk_core,
rst_x,
// local interface
i_req,
i_wr,
i_adrs,
i_len,
o_ack,
i_strw,
i_be,
i_dbw,
o_ackw,
o_strr,
o_dbr,
// F/F interface
o_req,
o_wr,
o_adrs,
o_len,
i_ack,
o_strw,
o_be,
o_dbw,
i_ackw,
i_strr,
i_dbr
);
//////////////////////////////////
// parameter
//////////////////////////////////
parameter P_ADRS_WIDTH = 'd22;
parameter P_DATA_WIDTH = 'd32;
parameter P_BLEN_WIDTH = 'd6;
parameter P_BE_WIDTH = P_DATA_WIDTH/8;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
// local interface
input i_req;
input i_wr;
input [P_ADRS_WIDTH-1:0]
i_adrs;
input [P_BLEN_WIDTH-1:0]
i_len;
output o_ack;
input i_strw;
input [P_BE_WIDTH-1:0]
i_be;
input [P_DATA_WIDTH-1:0]
i_dbw;
output o_ackw;
output o_strr;
output [P_DATA_WIDTH-1:0]
o_dbr;
// F/F-ed interface
output o_req;
output o_wr;
output [P_ADRS_WIDTH-1:0]
o_adrs;
output [P_BLEN_WIDTH-1:0]
o_len;
input i_ack;
output o_strw;
output [P_BE_WIDTH-1:0]
o_be;
output [P_DATA_WIDTH-1:0]
o_dbw;
input i_ackw;
input i_strr;
input [P_DATA_WIDTH-1:0]
i_dbr;
//////////////////////////////////
// reg
//////////////////////////////////
reg r_req;
reg r_wr;
reg [P_ADRS_WIDTH-1:0]
r_adrs;
reg [P_BLEN_WIDTH-1:0]
r_len;
reg r_ack;
reg r_strw;
reg [P_BE_WIDTH-1:0]
r_be;
reg [P_DATA_WIDTH-1:0]
r_dbw;
reg r_ackw;
// reg [P_DATA_WIDTH-1:0]
// r_dbr;
// reg r_strr;
//////////////////////////////////
// wire
//////////////////////////////////
//////////////////////////////////
// assign
//////////////////////////////////
assign o_req = r_req;
assign o_wr = r_wr;
assign o_adrs = r_adrs;
assign o_len = r_len;
assign o_strw = r_strw;
assign o_be = r_be;
assign o_dbw = r_dbw;
assign o_ack = (i_req & i_wr) ? (r_ack & r_ackw) : r_ack;
assign o_ackw = (i_req & i_wr) ? (r_ack & r_ackw) : r_ackw;
assign o_dbr = i_dbr;
assign o_strr = i_strr;
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_req <= 1'b0;
r_wr <= 1'b0;
r_strw <= 1'b0;
end else begin
r_req <= (o_ack) ? i_req : 1'b0;
r_wr <= i_wr;
r_strw <= (o_ackw & i_strw);
end
end
always @(posedge clk_core) begin
r_adrs <= i_adrs;
r_len <= i_len;
r_be <= i_be;
r_dbw <= i_dbw;
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_ack <= 1'b0;
r_ackw <= 1'b0;
end else begin
r_ack <= i_ack;
r_ackw <= i_ackw;
end
end
endmodule
|
module fm_cmn_dram_01 (
clk,
we,
a,
dpra,
di,
spo,
dpo
);
//////////////////////////////////
// parameter
//////////////////////////////////
parameter P_WIDTH = 32;
parameter P_RANGE = 2;
parameter P_DEPTH = 1 << P_RANGE;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk;
input we;
input [P_RANGE-1:0] a;
input [P_RANGE-1:0] dpra;
input [P_WIDTH-1:0] di;
output [P_WIDTH-1:0] spo;
output [P_WIDTH-1:0] dpo;
//////////////////////////////////
// reg
//////////////////////////////////
reg [P_WIDTH-1:0] ram [P_DEPTH-1:0];
reg [P_WIDTH-1:0] spo;
reg [P_WIDTH-1:0] dpo;
//////////////////////////////////
// always
//////////////////////////////////
// port A: write-first
always @(posedge clk) begin
if (we) begin
ram[a] <= di;
spo <= di;
end else begin
spo <= ram[a];
end
end
// port B: read-first
always @(posedge clk) begin
dpo <= ram[dpra];
end
endmodule
|
module fm_rd_split (
clk_core,
rst_x,
i_req,
i_adrs,
i_len,
o_ack,
// dram if
o_req,
o_adrs,
o_len,
i_ack
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
parameter P_IDLE = 'd0;
parameter P_SECOND = 'd1;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
input i_req;
input [P_IB_ADDR_WIDTH-1:0]
i_adrs;
input [P_IB_LEN_WIDTH-1:0]
i_len; // 32 burst x 10
output o_ack;
// dram if
output o_req;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs;
output [P_IB_LEN_WIDTH-1:0]
o_len; // 16 burst x 10
input i_ack;
//////////////////////////////////
// reg
//////////////////////////////////
reg r_state;
reg [P_IB_LEN_WIDTH-1:0]
r_len;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_a;
wire w_size;
wire [P_IB_LEN_WIDTH-1:0]
w_len; // 16 burst x 10
//////////////////////////////////
// assign
//////////////////////////////////
assign w_len = i_len - 5'h10;
assign o_req = i_req;
assign o_len = ((r_state == P_IDLE)&w_size) ? 'd16 :
((r_state == P_SECOND)&w_size) ? w_len :
i_len;
assign o_ack = ((r_state == P_SECOND) & i_ack) |
((r_state == P_IDLE) & !w_size & i_ack);
assign w_a = (r_state == P_SECOND);
assign o_adrs = {i_adrs[P_IB_ADDR_WIDTH-1:5],w_a,4'b0};
assign w_size = (i_len > 5'h10);
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (i_req & i_ack) begin
if (w_size) r_state <= P_SECOND;
end
end
P_SECOND: begin
if (i_ack) r_state <= P_IDLE;
end
endcase
end
end
endmodule
|
module fm_cmn_bififo (
clk_core,
rst_x,
i_wstrobe,
i_dt,
o_full,
i_renable,
o_dt,
o_empty,
o_dnum
);
// set default parameters
parameter P_WIDTH = 32;
parameter P_RANGE = 8;
parameter P_DEPTH = 1 << P_RANGE;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core; // system clock
input rst_x; // system reset
input i_wstrobe; // write strobe
input [P_WIDTH-1:0] i_dt; // write data
output o_full; // write data full
input i_renable; // read enable
output [P_WIDTH-1:0] o_dt; // read data
output o_empty; // read data empty
output [P_RANGE:0] o_dnum; // written data number
/////////////////////////
// Register definition
/////////////////////////
reg [P_RANGE-1:0] r_write_counter;
reg [P_RANGE-1:0] r_read_counter;
reg [P_RANGE:0] r_status;
reg r_sel;
/////////////////////////
// wire definition
/////////////////////////
wire o_full;
wire o_empty;
wire [P_WIDTH-1:0] o_dt;
wire [P_WIDTH-1:0] w_dto;
wire [P_WIDTH-1:0] w_dto_th;
wire [1:0] w_status;
wire w_we;
wire w_re;
wire [P_RANGE-1:0] w_read_counter_inc;
wire [P_RANGE-1:0] w_read_counter;
/////////////////////////
// assign statement
/////////////////////////
assign o_full = (r_status == P_DEPTH);
assign o_empty = (r_status == 0);
assign o_dnum = r_status;
assign o_dt = (o_empty) ? 'd0 :
(r_sel) ? w_dto_th : w_dto;
assign w_read_counter_inc = r_read_counter + 1'b1;
assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
assign w_we = !o_full & i_wstrobe;
assign w_re = i_renable & !o_empty;
assign w_status = {w_re,w_we};
////////////////////////
// always statement
///////////////////////
// write side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_write_counter <= 'd0;
end else begin
if (w_we) begin
r_write_counter <= r_write_counter + 1'b1;
end
end
end
// read side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_read_counter <= 'd0;
end else begin
if (w_re) begin
r_read_counter <= r_read_counter + 1'b1;
end
end
end
// ram output select
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_sel <= 1'b0;
end else begin
r_sel <= (r_write_counter == w_read_counter) ? 1'b1 : 1'b0;
end
end
// status counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_status <= 'd0;
end else begin
case (w_status)
2'b01: r_status <= r_status + 1'b1; // write
2'b10: r_status <= r_status - 1'b1; // read
default: r_status <= r_status; // nothing to do
endcase
end
end
///////////////////
// module instance
///////////////////
fm_cmn_bram_01 #(P_WIDTH, P_RANGE) bram_00 (
.clk(clk_core),
.we(w_we),
.a(r_write_counter),
.dpra(w_read_counter),
.di(i_dt),
.spo(w_dto_th),
.dpo(w_dto)
);
endmodule
|
module fm_cmn_ififo (
clk_core,
rst_x,
i_wstrobe,
i_dt,
o_full,
i_renable,
o_dt,
o_empty
);
// set default parameters
parameter WIDTH = 32;
////////////////////////////
// I/O definitions
////////////////////////////
input i_wstrobe; // write strobe
input [WIDTH-1:0] i_dt; // write data
output o_full; // write data full
input i_renable; // read enable
output [WIDTH-1:0] o_dt; // read data
output o_empty; // read data empty
input clk_core; // system clock
input rst_x; // system reset
/////////////////////////
// Register definitions
/////////////////////////
reg [2:0] rs_write_counter;
reg [2:0] rs_read_counter;
// data registers
reg [WIDTH-1:0] rs_data_buffer[0:4]; // only 5 data
reg [2:0] rs_status;
/////////////////////////
// wire definitions
/////////////////////////
wire o_full;
wire o_empty;
wire [WIDTH-1:0] o_dt;
wire [1:0] w_status;
wire w_we;
wire w_re;
//wire [2:0] w_next_write_counter;
//wire [2:0] w_next_read_counter;
reg [2:0] w_next_write_counter; // 2004/11/19
reg [2:0] w_next_read_counter; // 2004/11/19
/////////////////////////
// assign statements
/////////////////////////
assign o_full = (rs_status == 5);
assign o_empty = (rs_status == 0);
assign o_dt = rs_data_buffer[rs_read_counter];
assign w_we = !o_full & i_wstrobe;
assign w_re = i_renable & !o_empty;
assign w_status = {w_re,w_we};
//assign w_next_write_counter = (rs_write_counter == 3'd4) ? 3'd0 :
// rs_write_counter +1'b1;
// 2004/11/19
always @(*) begin
if (rs_write_counter == 3'd4) w_next_write_counter = 3'd0;
else w_next_write_counter = rs_write_counter +1'b1;
end
//assign w_next_read_counter = (rs_read_counter == 3'd4) ? 3'd0 :
// rs_read_counter +1'b1;
// 2004/11/19
always @(*) begin
if (rs_read_counter == 3'd4) w_next_read_counter = 3'd0;
else w_next_read_counter = rs_read_counter +1'b1;
end
////////////////////////
// Behaviour
///////////////////////
// write side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_write_counter <= 'd0;
end else begin
if (w_we) begin
rs_write_counter <= w_next_write_counter;
end
end
end
integer i;
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
for (i = 0; i < 5; i = i + 1) begin
rs_data_buffer[i] <= 0;
end
end else begin
if (w_we) begin
rs_data_buffer[rs_write_counter] <= i_dt;
end
end
end
// read side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_read_counter <= 'd0;
end else begin
if (w_re) begin
rs_read_counter <= w_next_read_counter;
end
end
end
// status counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_status <= 'd0;
end else begin
case (w_status)
2'b01: rs_status <= rs_status + 1'b1; // write
2'b10: rs_status <= rs_status - 1'b1; // read
default: rs_status <= rs_status; // nothing to do
endcase
end
end
endmodule
|
module fm_cmn_bram_02 (
clka,
clkb,
wea,
addra,
addrb,
dia,
doa,
dob
);
//////////////////////////////////
// parameter
//////////////////////////////////
parameter P_WIDTH = 32;
parameter P_RANGE = 2;
parameter P_DEPTH = 1 << P_RANGE;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clka;
input clkb;
input wea;
input [P_RANGE-1:0] addra;
input [P_RANGE-1:0] addrb;
input [P_WIDTH-1:0] dia;
output [P_WIDTH-1:0] doa;
output [P_WIDTH-1:0] dob;
//////////////////////////////////
// reg
//////////////////////////////////
reg [P_WIDTH-1:0] ram [P_DEPTH-1:0];
reg [P_WIDTH-1:0] doa;
reg [P_WIDTH-1:0] dob;
//////////////////////////////////
// always
//////////////////////////////////
// port A: write-first
always @(posedge clka) begin
if (wea) begin
ram[addra] <= dia;
doa <= dia;
end else begin
doa <= ram[addra];
end
end
// port B: read-first
always @(posedge clkb) begin
dob <= ram[addrb];
end
endmodule
|
module fm_cmn_bram_00 (
clk,
we,
a,
dpra,
di,
spo,
dpo
);
//////////////////////////////////
// parameter
//////////////////////////////////
parameter P_WIDTH = 32;
parameter P_RANGE = 2;
parameter P_DEPTH = 1 << P_RANGE;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk;
input we;
input [P_RANGE-1:0] a;
input [P_RANGE-1:0] dpra;
input [P_WIDTH-1:0] di;
output [P_WIDTH-1:0] spo;
output [P_WIDTH-1:0] dpo;
//////////////////////////////////
// reg
//////////////////////////////////
reg [P_WIDTH-1:0] ram [P_DEPTH-1:0];
reg [P_RANGE-1:0] read_a;
reg [P_RANGE-1:0] read_dpra;
//////////////////////////////////
// assign
//////////////////////////////////
assign spo = ram[read_a];
assign dpo = ram[read_dpra];
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk) begin
if (we) ram[a] <= di;
read_a <= a;
read_dpra <= dpra;
end
endmodule
|
module fm_cmn_fifo (
clk_core,
rst_x,
i_wstrobe,
i_dt,
o_full,
i_renable,
o_dt,
o_empty,
o_dnum
);
// set default parameters
parameter WIDTH = 32;
parameter RANGEE = 2;
parameter DEPTH = 1 << RANGEE;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core; // system clock
input rst_x; // system reset
input i_wstrobe; // write strobe
input [WIDTH-1:0] i_dt; // write data
output o_full; // write data full
input i_renable; // read enable
output [WIDTH-1:0] o_dt; // read data
output o_empty; // read data empty
output [RANGEE:0] o_dnum; // written data number
/////////////////////////
// Register definition
/////////////////////////
reg [RANGEE-1:0] rs_write_counter;
reg [RANGEE-1:0] rs_read_counter;
// data registers
reg [WIDTH-1:0] rs_data_buffer[0:DEPTH-1];
reg [RANGEE:0] rs_status;
/////////////////////////
// wire definition
/////////////////////////
wire o_full;
wire o_empty;
wire [WIDTH-1:0] o_dt;
wire [1:0] w_status;
wire w_we;
wire w_re;
/////////////////////////
// assign statement
/////////////////////////
assign o_full = (rs_status == DEPTH);
assign o_empty = (rs_status == 0);
assign o_dt = rs_data_buffer[rs_read_counter];
assign o_dnum = rs_status;
assign w_we = !o_full & i_wstrobe;
assign w_re = i_renable & !o_empty;
assign w_status = {w_re,w_we};
////////////////////////
// always statement
///////////////////////
// write side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_write_counter <= 'd0;
end else begin
if (w_we) begin
rs_write_counter <= rs_write_counter + 1'b1;
end
end
end
always @(posedge clk_core) begin
if (w_we) begin
rs_data_buffer[rs_write_counter] <= i_dt;
end
end
// read side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_read_counter <= 'd0;
end else begin
if (w_re) begin
rs_read_counter <= rs_read_counter + 1'b1;
end
end
end
// status counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_status <= 'd0;
end else begin
case (w_status)
2'b01: rs_status <= rs_status + 1'b1; // write
2'b10: rs_status <= rs_status - 1'b1; // read
default: rs_status <= rs_status; // nothing to do
endcase
end
end
endmodule
|
module fm_fifo (
clk_core,
rst_x,
i_wstrobe,
i_dt,
o_full,
i_renable,
o_dt,
o_empty,
o_dnum
);
// set default parameters
parameter P_WIDTH = 32;
parameter P_RANGE = 2;
parameter P_DEPTH = 1 << P_RANGE;
parameter P_CLEAR = "FALSE";
////////////////////////////
// I/O definition
////////////////////////////
input clk_core; // system clock
input rst_x; // system reset
input i_wstrobe; // write strobe
input [P_WIDTH-1:0] i_dt; // write data
output o_full; // write data full
input i_renable; // read enable
output [P_WIDTH-1:0] o_dt; // read data
output o_empty; // read data empty
output [P_RANGE:0] o_dnum; // written data number
/////////////////////////
// Register definition
/////////////////////////
reg [P_RANGE-1:0] rs_write_counter;
reg [P_RANGE-1:0] rs_read_counter;
// data registers
reg [P_WIDTH-1:0] rs_data_buffer[0:P_DEPTH-1];
reg [P_RANGE:0] rs_status;
/////////////////////////
// wire definition
/////////////////////////
wire o_full;
wire o_empty;
wire [P_WIDTH-1:0] o_dt;
wire [1:0] w_status;
wire w_we;
wire w_re;
/////////////////////////
// assign statement
/////////////////////////
assign o_full = (rs_status == P_DEPTH);
assign o_empty = (rs_status == 0);
assign o_dt = rs_data_buffer[rs_read_counter];
assign o_dnum = rs_status;
assign w_we = !o_full & i_wstrobe;
assign w_re = i_renable & !o_empty;
assign w_status = {w_re,w_we};
////////////////////////
// always statement
///////////////////////
// write side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_write_counter <= 'd0;
end else begin
if (w_we) begin
rs_write_counter <= rs_write_counter + 1'b1;
end
end
end
generate
if (P_CLEAR == "TRUE") begin
integer i;
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
for(i=0;i<P_DEPTH;i=i+1) rs_data_buffer[i] <= 'd0;
end else begin
if (w_we) begin
rs_data_buffer[rs_write_counter] <= i_dt;
end
end
end
end else begin
always @(posedge clk_core) begin
if (w_we) begin
rs_data_buffer[rs_write_counter] <= i_dt;
end
end
end
endgenerate
// read side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_read_counter <= 'd0;
end else begin
if (w_re) begin
rs_read_counter <= rs_read_counter + 1'b1;
end
end
end
// status counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
rs_status <= 'd0;
end else begin
case (w_status)
2'b01: rs_status <= rs_status + 1'b1; // write
2'b10: rs_status <= rs_status - 1'b1; // read
default: rs_status <= rs_status; // nothing to do
endcase
end
end
endmodule
|
module fm_3d_ru_span_fragment (
clk_core,
rst_x,
// setup module interface
i_valid,
i_aa_mode,
i_kind,
i_initial_val,
i_step_val,
i_delta_a,
i_end_flag,
i_y,
i_end_x,
o_busy,
// idle state indicator
o_idle,
// control registers
i_param0_en,
i_param1_en,
i_param0_size,
i_param0_kind,
i_param1_size,
i_param1_kind,
// pixel unit bus
o_valid_pu,
i_busy_pu,
o_aa_mode,
o_x,
o_y,
o_z,
o_cr,
o_cg,
o_cb,
o_ca,
// texture unit bus
o_valid_tu,
i_busy_tu,
o_tu,
o_tv
);
////////////////////////////
// parameter
////////////////////////////
parameter P_IDLE = 3'h0;
parameter P_INITIAL_SETUP = 3'h1;
parameter P_UPDATE_AA = 3'h2;
parameter P_WAIT_AA = 3'h3;
parameter P_GEN_FRAGMENT = 3'h4;
parameter P_OUT = 3'h5;
parameter P_PU_IDLE = 2'h0;
parameter P_PU_OUT = 2'h1;
parameter P_PU_WAIT = 2'h2;
parameter P_TU_IDLE = 2'h0;
parameter P_TU_OUT = 2'h1;
parameter P_TU_WAIT = 2'h2;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// setup module interface
input i_valid;
input i_aa_mode;
input [3:0] i_kind;
input [21:0] i_initial_val;
input [21:0] i_step_val;
input [21:0] i_delta_a;
input [8:0] i_y;
input i_end_flag;
input [20:0] i_end_x;
output o_busy;
// idle state indicator
output o_idle;
// control registers
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
input [1:0] i_param0_kind;
input [1:0] i_param1_kind;
// pixel unit bus
output o_valid_pu;
input i_busy_pu;
output o_aa_mode;
output [9:0] o_x;
output [8:0] o_y;
output [15:0] o_z;
output [7:0] o_cr;
output [7:0] o_cg;
output [7:0] o_cb;
output [7:0] o_ca;
// texture unit bus
output o_valid_tu;
input i_busy_tu;
output [21:0] o_tu;
output [21:0] o_tv;
////////////////////////////
// reg
////////////////////////////
reg [2:0] r_state;
reg [1:0] r_state_pu;
reg [1:0] r_state_tu;
reg [8:0] r_y;
reg [20:0] r_end_x;
reg r_aa_mode;
////////////////////////////
// wire
////////////////////////////
wire w_valid;
wire w_finish_setup;
wire w_start_update;
wire w_finish_update;
wire w_finish_fragment;
wire w_aa_mode;
// internal connection
wire w_update_valid;
wire [3:0] w_update_kind;
wire w_update_end_flag;
wire [21:0] w_update_val;
wire [21:0] w_update_frag;
wire [9:0] w_update_x;
wire [15:0] w_update_z;
wire [7:0] w_update_color;
wire [20:0] w_cur_x;
wire [20:0] w_cur_z;
wire [20:0] w_cur_iw;
wire [20:0] w_cur_param00;
wire [20:0] w_cur_param01;
wire [20:0] w_cur_param02;
wire [20:0] w_cur_param03;
wire [20:0] w_cur_param10;
wire [20:0] w_cur_param11;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_cur_param12;
wire [20:0] w_cur_param13;
`endif
wire w_param0_is_color0;
wire w_param1_is_color0;
wire w_param0_is_texture0;
wire w_param1_is_texture0;
wire w_go_out_pu;
wire w_set_color0;
wire w_set_color1;
wire w_set_no_color;
wire w_go_out_tu;
wire w_set_texture0;
wire w_set_texture1;
wire w_go_idle_pu;
wire w_go_idle_tu;
wire w_go_idle;
wire w_end_x;
////////////////////////////
// assign
////////////////////////////
assign o_busy = !((r_state == P_IDLE)|(r_state == P_INITIAL_SETUP));
assign w_start_update = ((r_state == P_INITIAL_SETUP) & w_finish_setup ) |
(r_state == P_WAIT_AA) |
((r_state == P_OUT) & w_go_idle & !w_end_x);
assign w_finish_setup = i_valid & i_end_flag & !o_busy;
assign w_valid = i_valid & ((r_state == P_IDLE)|(r_state == P_INITIAL_SETUP));
assign w_param0_is_color0 = (i_param0_en & (i_param0_kind == `ATTR_COLOR0));
assign w_param1_is_color0 = (i_param1_en & (i_param1_kind == `ATTR_COLOR0));
assign w_param0_is_texture0 = (i_param0_en & (i_param0_kind == `ATTR_TEXTURE0));
assign w_param1_is_texture0 = (i_param1_en & (i_param1_kind == `ATTR_TEXTURE0));
assign w_set_color0 = w_param0_is_color0 &
(((w_update_kind == `FPARAM_P02)&(i_param0_size == 2'd2))
|(w_update_kind == `FPARAM_P03));
assign w_set_color1 = w_param1_is_color0 &
(((w_update_kind == `FPARAM_P12)&(i_param1_size == 2'd2))
|(w_update_kind == `FPARAM_P13));
assign w_set_no_color = !w_param0_is_color0 & !w_param1_is_color0 &
(w_update_kind == `FPARAM_Z);
assign w_go_out_pu = !w_aa_mode & w_update_valid & (w_set_color0 | w_set_color1 | w_set_no_color);
assign w_set_texture0 = w_param0_is_texture0 & (w_update_kind == `FPARAM_P01);
assign w_set_texture1 = w_param1_is_texture0 & (w_update_kind == `FPARAM_P11);
assign w_go_out_tu = !w_aa_mode & w_update_valid & (w_set_texture0 | w_set_texture1);
assign w_go_idle_pu = (w_param0_is_texture0|w_param1_is_texture0) ?
((r_state_pu == P_PU_WAIT) & (r_state_tu == P_TU_WAIT)) :
(r_state_pu == P_PU_WAIT);
assign w_go_idle_tu = ((r_state_pu == P_PU_WAIT) & (r_state_tu == P_TU_WAIT));
assign w_go_idle = (w_go_idle_tu | w_go_idle_pu);
assign w_finish_fragment = w_finish_update;
assign w_end_x = (w_cur_x >= r_end_x);
assign w_aa_mode = (r_state == P_UPDATE_AA)|
((r_state == P_INITIAL_SETUP) & w_finish_setup &i_aa_mode);
assign o_y = r_y;
assign o_valid_pu = (r_state_pu == P_PU_OUT);
assign o_valid_tu = (r_state_tu == P_TU_OUT);
assign o_idle = (r_state == P_IDLE);
assign o_aa_mode = r_aa_mode;
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (i_valid) r_state <= P_INITIAL_SETUP;
end
P_INITIAL_SETUP: begin
if (w_finish_setup) begin
if (i_aa_mode) r_state <= P_UPDATE_AA;
else r_state <= P_GEN_FRAGMENT;
end
end
P_UPDATE_AA: begin
if (w_finish_update) r_state <= P_WAIT_AA;
end
P_WAIT_AA: begin
r_state <= P_GEN_FRAGMENT;
end
P_GEN_FRAGMENT: begin
if (w_finish_fragment) r_state <= P_OUT;
end
P_OUT: begin
if (w_go_idle) begin
if (w_end_x) r_state <= P_IDLE;
else r_state <= P_GEN_FRAGMENT;
end
end
endcase
end
end
// pixel unit output state
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state_pu <= P_PU_IDLE;
end else begin
case (r_state_pu)
P_PU_IDLE: begin
if (w_go_out_pu) r_state_pu <= P_PU_OUT;
end
P_PU_OUT: begin
if (!i_busy_pu) r_state_pu <= P_PU_WAIT;
end
P_PU_WAIT: begin
if (w_go_idle_pu) r_state_pu <= P_PU_IDLE;
end
endcase
end
end
// texture unit output state
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state_tu <= P_TU_IDLE;
end else begin
case (r_state_tu)
P_TU_IDLE: begin
if (w_go_out_tu) r_state_tu <= P_TU_OUT;
end
P_TU_OUT: begin
if (!i_busy_tu) r_state_tu <= P_TU_WAIT;
end
P_TU_WAIT: begin
if (w_go_idle_tu) r_state_tu <= P_TU_IDLE;
end
endcase
end
end
always @(posedge clk_core) begin
if (w_finish_setup) begin
r_y <= i_y;
r_end_x <= i_end_x;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_aa_mode <= 1'b0;
end else begin
if (w_valid) r_aa_mode <= i_aa_mode;
end
end
////////////////////////////
// module instance
////////////////////////////
fm_3d_ru_span_update span_update (
.clk_core(clk_core),
.rst_x(rst_x),
// parameter input
.i_start(w_start_update),
.i_aa_mode(w_aa_mode),
.i_delta_a(i_delta_a),
.o_finish(w_finish_update),
// generated steps
.i_valid_step(w_valid),
.i_step_kind(i_kind),
.i_step_val(i_step_val),
// control registers
.i_param0_en(i_param0_en),
.i_param1_en(i_param1_en),
.i_param0_size(i_param0_size),
.i_param1_size(i_param1_size),
// current values
.i_cur_x(w_cur_x),
.i_cur_z(w_cur_z),
.i_cur_iw(w_cur_iw),
.i_cur_param00(w_cur_param00),
.i_cur_param01(w_cur_param01),
.i_cur_param02(w_cur_param02),
.i_cur_param03(w_cur_param03),
.i_cur_param10(w_cur_param10),
.i_cur_param11(w_cur_param11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_cur_param12(w_cur_param12),
.i_cur_param13(w_cur_param13),
`endif
// new value
.o_update_valid(w_update_valid),
.o_update_kind(w_update_kind),
.o_update_end_flag(w_update_end_flag),
.o_update_val(w_update_val),
.o_update_frag(w_update_frag),
.o_update_x(w_update_x),
.o_update_z(w_update_z),
.o_update_color(w_update_color)
);
fm_3d_ru_span_reg span_reg (
.clk_core(clk_core),
// parameter setup
.i_initial_valid(w_valid),
.i_initial_kind(i_kind),
.i_initial_val(i_initial_val),
// parameter update
.i_update_valid(w_update_valid),
.i_update_kind(w_update_kind),
.i_update_end_flag(w_update_end_flag),
.i_update_val(w_update_val),
.i_update_frag(w_update_frag),
.i_update_x(w_update_x),
.i_update_z(w_update_z),
.i_update_color(w_update_color),
// control registers
.i_param0_en(i_param0_en),
.i_param1_en(i_param1_en),
.i_param0_size(i_param0_size),
.i_param1_size(i_param1_size),
.i_param0_kind(i_param0_kind),
.i_param1_kind(i_param1_kind),
// current values
.o_cur_x(w_cur_x),
.o_cur_z(w_cur_z),
.o_cur_iw(w_cur_iw),
.o_cur_param00(w_cur_param00),
.o_cur_param01(w_cur_param01),
.o_cur_param02(w_cur_param02),
.o_cur_param03(w_cur_param03),
.o_cur_param10(w_cur_param10),
.o_cur_param11(w_cur_param11),
`ifdef VTX_PARAM1_REDUCE
`else
.o_cur_param12(w_cur_param12),
.o_cur_param13(w_cur_param13),
`endif
// parameter output
.o_x(o_x),
.o_z(o_z),
.o_cr(o_cr),
.o_cg(o_cg),
.o_cb(o_cb),
.o_ca(o_ca),
.o_tu(o_tu),
.o_tv(o_tv)
);
endmodule
|
module fm_3d_ru_span (
clk_core,
rst_x,
// span parameters
i_valid,
i_aa_mode,
i_x_l,
i_y_l,
i_z_l,
i_iw_l,
i_param00_l,
i_param01_l,
i_param02_l,
i_param03_l,
i_param10_l,
i_param11_l,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_l,
i_param13_l,
`endif
i_x_r,
i_y_r,
i_z_r,
i_iw_r,
i_param00_r,
i_param01_r,
i_param02_r,
i_param03_r,
i_param10_r,
i_param11_r,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_r,
i_param13_r,
`endif
o_ack,
// control registers
i_param0_en,
i_param1_en,
i_param0_size,
i_param1_size,
i_param0_kind,
i_param1_kind,
// idle state indicator
o_idle,
// pixel unit bus
o_valid_pu,
i_busy_pu,
o_aa_mode,
o_x,
o_y,
o_z,
o_cr,
o_cg,
o_cb,
o_ca,
// texture unit bus
o_valid_tu,
i_busy_tu,
o_tu,
o_tv
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// span parameters
input i_valid;
input i_aa_mode;
input [20:0] i_x_l;
input [8:0] i_y_l;
input [20:0] i_z_l;
input [20:0] i_iw_l;
input [20:0] i_param00_l;
input [20:0] i_param01_l;
input [20:0] i_param02_l;
input [20:0] i_param03_l;
input [20:0] i_param10_l;
input [20:0] i_param11_l;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_l;
input [20:0] i_param13_l;
`endif
input [20:0] i_x_r;
input [8:0] i_y_r;
input [20:0] i_z_r;
input [20:0] i_iw_r;
input [20:0] i_param00_r;
input [20:0] i_param01_r;
input [20:0] i_param02_r;
input [20:0] i_param03_r;
input [20:0] i_param10_r;
input [20:0] i_param11_r;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_r;
input [20:0] i_param13_r;
`endif
output o_ack;
// control registers
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
input [1:0] i_param0_kind;
input [1:0] i_param1_kind;
// idle state indicator
output o_idle;
// pixel unit bus
output o_valid_pu;
input i_busy_pu;
output o_aa_mode;
output [9:0] o_x;
output [8:0] o_y;
output [15:0] o_z;
output [7:0] o_cr;
output [7:0] o_cg;
output [7:0] o_cb;
output [7:0] o_ca;
// texture unit bus
output o_valid_tu;
input i_busy_tu;
output [21:0] o_tu;
output [21:0] o_tv;
////////////////////////////
// wire
////////////////////////////
wire w_valid;
wire w_aa_mode;
wire [3:0] w_kind;
wire [21:0] w_initial_val;
wire [21:0] w_step_val;
wire [21:0] w_delta_a;
wire [8:0] w_y;
wire w_end_flag;
wire [20:0] w_end_x;
wire w_busy;
wire w_idle_setup;
wire w_idle_fragment;
////////////////////////////
// assign
////////////////////////////
assign o_idle = w_idle_setup & w_idle_fragment;
////////////////////////////
// module instance
////////////////////////////
// setup module
fm_3d_ru_span_setup span_setup(
.clk_core(clk_core),
.rst_x(rst_x),
// span parameters
.i_valid(i_valid),
.i_aa_mode(i_aa_mode),
.i_x_l(i_x_l),
.i_y_l(i_y_l),
.i_z_l(i_z_l),
.i_iw_l(i_iw_l),
.i_param00_l(i_param00_l),
.i_param01_l(i_param01_l),
.i_param02_l(i_param02_l),
.i_param03_l(i_param03_l),
.i_param10_l(i_param10_l),
.i_param11_l(i_param11_l),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_l(i_param12_l),
.i_param13_l(i_param13_l),
`endif
.i_x_r(i_x_r),
.i_y_r(i_y_r),
.i_z_r(i_z_r),
.i_iw_r(i_iw_r),
.i_param00_r(i_param00_r),
.i_param01_r(i_param01_r),
.i_param02_r(i_param02_r),
.i_param03_r(i_param03_r),
.i_param10_r(i_param10_r),
.i_param11_r(i_param11_r),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_r(i_param12_r),
.i_param13_r(i_param13_r),
`endif
.o_ack(o_ack),
// control registers
.i_param0_en(i_param0_en),
.i_param1_en(i_param1_en),
.i_param0_size(i_param0_size),
.i_param1_size(i_param1_size),
// idle state indicator
.o_idle(w_idle_setup),
// update module interface
.o_valid(w_valid),
.o_aa_mode(w_aa_mode),
.o_kind(w_kind), // y will be int, and last kind
.o_initial_val(w_initial_val),
.o_step_val(w_step_val),
.o_delta_a(w_delta_a),
.o_y(w_y),
.o_end_flag(w_end_flag),
.o_end_x(w_end_x),
.i_busy(w_busy)
);
// fragment generation (x -loop)
fm_3d_ru_span_fragment span_fragment(
.clk_core(clk_core),
.rst_x(rst_x),
// setup module interface
.i_valid(w_valid),
.i_aa_mode(w_aa_mode),
.i_kind(w_kind),
.i_initial_val(w_initial_val),
.i_step_val(w_step_val),
.i_delta_a(w_delta_a),
.i_y(w_y),
.i_end_flag(w_end_flag),
.i_end_x(w_end_x),
.o_busy(w_busy),
// control registers
.i_param0_en(i_param0_en),
.i_param1_en(i_param1_en),
.i_param0_size(i_param0_size),
.i_param1_size(i_param1_size),
.i_param0_kind(i_param0_kind),
.i_param1_kind(i_param1_kind),
// idle state indicator
.o_idle(w_idle_fragment),
// pixel unit bus
.o_valid_pu(o_valid_pu),
.i_busy_pu(i_busy_pu),
.o_aa_mode(o_aa_mode),
.o_x(o_x),
.o_y(o_y),
.o_z(o_z),
.o_cr(o_cr),
.o_cg(o_cg),
.o_cb(o_cb),
.o_ca(o_ca),
// texture unit bus
.o_valid_tu(o_valid_tu),
.i_busy_tu(i_busy_tu),
.o_tu(o_tu),
.o_tv(o_tv)
);
endmodule
|
module fm_3d (
clk_core,
rst_x,
// debug
o_idle,
o_ff,
o_fe,
// configuration
i_color_mode,
// system bus
i_req_s,
i_wr_s,
i_adrs_s,
o_ack_s,
i_len_s,
i_be_s,
i_dbw_s,
o_strr_s,
o_dbr_s,
// vertex dma bus
o_vtx_int,
o_req_dma,
o_adrs_dma,
o_len_dma,
i_ack_dma,
i_strr_dma,
i_dbr_dma,
// memory bus
o_req_m,
o_wr_m,
o_adrs_m,
i_ack_m,
o_len_m,
o_be_m,
o_strw_m,
o_dbw_m,
i_ackw_m,
i_strr_m,
i_dbr_m
);
`include "polyphony_params.v"
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// debug
output o_idle;
output [15:0] o_ff;
output [4:0] o_fe;
// configuration
input [1:0] i_color_mode;
// system bus
input i_req_s;
input i_wr_s;
input [21:0] i_adrs_s;
output o_ack_s;
input [5:0] i_len_s;
input [3:0] i_be_s;
input [31:0] i_dbw_s;
output o_strr_s;
output [31:0] o_dbr_s;
// vertex dma bus
output o_vtx_int;
output o_req_dma;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs_dma;
output [P_IB_LEN_WIDTH-1:0]
o_len_dma;
input i_ack_dma;
input i_strr_dma;
input [P_IB_DATA_WIDTH-1:0]
i_dbr_dma;
// memory bus
output o_req_m;
output o_wr_m;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs_m;
input i_ack_m;
output [P_IB_LEN_WIDTH-1:0]
o_len_m;
output [P_IB_BE_WIDTH-1:0]
o_be_m;
output o_strw_m;
output [P_IB_DATA_WIDTH-1:0]
o_dbw_m;
input i_ackw_m;
input i_strr_m;
input [P_IB_DATA_WIDTH-1:0]
i_dbr_m;
////////////////////////////
// wire
////////////////////////////
wire w_valid;
wire w_ml;
wire [20:0] w_vtx0_x;
wire [20:0] w_vtx0_y;
wire [20:0] w_vtx0_z;
wire [20:0] w_vtx0_iw;
wire [20:0] w_vtx0_p00;
wire [20:0] w_vtx0_p01;
wire [20:0] w_vtx0_p02;
wire [20:0] w_vtx0_p03;
wire [20:0] w_vtx0_p10;
wire [20:0] w_vtx0_p11;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_vtx0_p12;
wire [20:0] w_vtx0_p13;
`endif
wire [20:0] w_vtx1_x;
wire [20:0] w_vtx1_y;
wire [20:0] w_vtx1_z;
wire [20:0] w_vtx1_iw;
wire [20:0] w_vtx1_p00;
wire [20:0] w_vtx1_p01;
wire [20:0] w_vtx1_p02;
wire [20:0] w_vtx1_p03;
wire [20:0] w_vtx1_p10;
wire [20:0] w_vtx1_p11;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_vtx1_p12;
wire [20:0] w_vtx1_p13;
`endif
wire [20:0] w_vtx2_x;
wire [20:0] w_vtx2_y;
wire [20:0] w_vtx2_z;
wire [20:0] w_vtx2_iw;
wire [20:0] w_vtx2_p00;
wire [20:0] w_vtx2_p01;
wire [20:0] w_vtx2_p02;
wire [20:0] w_vtx2_p03;
wire [20:0] w_vtx2_p10;
wire [20:0] w_vtx2_p11;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_vtx2_p12;
wire [20:0] w_vtx2_p13;
`endif
wire w_aa_en;
wire w_attr0_en;
wire [1:0] w_attr0_size;
wire [1:0] w_attr0_kind;
wire w_attr1_en;
wire [1:0] w_attr1_size;
wire [1:0] w_attr1_kind;
wire w_tex_enable;
wire [2:0] w_tex_format;
wire [11:0] w_tex_offset;
wire [21:0] w_tex_width_m1_f;
wire [21:0] w_tex_height_m1_f;
wire [11:0] w_tex_width_ui;
wire w_tex_blend_enable;
wire w_depth_test_en;
wire [2:0] w_depth_func;
wire w_color_blend_en;
wire [2:0] w_color_blend_eq;
wire [3:0] w_color_blend_sf;
wire [3:0] w_color_blend_df;
wire [3:0] w_color_mask;
wire [11:0]
w_color_offset;
wire [11:0]
w_color_ms_offset;
wire [11:0]
w_depth_offset;
wire [11:0]
w_depth_ms_offset;
wire w_screen_flip;
wire w_ag_mode;
wire w_cache_init;
wire w_cache_flush;
wire w_flush_done;
wire w_ack;
wire w_idle_ru;
wire w_idle_tu;
wire w_idle_pu;
// ru - pu
wire w_valid_rp;
wire w_aa_mode;
wire [9:0] w_x;
wire [8:0] w_y;
wire [15:0] w_z;
wire [7:0] w_cr;
wire [7:0] w_cg;
wire [7:0] w_cb;
wire [7:0] w_ca;
wire w_busy_pr;
// ru - tu
wire w_valid_rt;
wire [21:0] w_tu_rt;
wire [21:0] w_tv_rt;
wire w_busy_tr;
// tu - pu
wire w_valid_tp;
wire [7:0] w_tr_tp;
wire [7:0] w_tg_tp;
wire [7:0] w_tb_tp;
wire [7:0] w_ta_tp;
wire w_busy_pt;
// memory unit
// texture unit
wire w_req_tu;
wire [P_IB_ADDR_WIDTH-1:0]
w_adrs_tu;
wire w_ack_tu;
wire [P_IB_LEN_WIDTH-1:0]
w_len_tu;
wire w_strr_tu;
wire [P_IB_DATA_WIDTH-1:0]
w_dbr_tu;
// color
wire w_req_cb;
wire w_wr_cb;
wire [P_IB_ADDR_WIDTH-1:0]
w_adrs_cb;
wire w_ack_cb;
wire [P_IB_LEN_WIDTH-1:0]
w_len_cb;
wire [P_IB_BE_WIDTH-1:0]
w_be_cb;
wire w_strw_cb;
wire [P_IB_DATA_WIDTH-1:0]
w_dbw_cb;
wire w_ackw_cb;
wire w_strr_cb;
wire [P_IB_DATA_WIDTH-1:0]
w_dbr_cb;
// depth
wire w_req_db;
wire w_wr_db;
wire [P_IB_ADDR_WIDTH-1:0]
w_adrs_db;
wire w_ack_db;
wire [P_IB_LEN_WIDTH-1:0]
w_len_db;
wire [P_IB_BE_WIDTH-1:0]
w_be_db;
wire w_strw_db;
wire [P_IB_DATA_WIDTH-1:0]
w_dbw_db;
wire w_ackw_db;
wire w_strr_db;
wire [P_IB_DATA_WIDTH-1:0]
w_dbr_db;
////////////////////////////
// module instance
////////////////////////////
// control unit
fm_3d_cu u_3d_cu (
.clk_core(clk_core),
.rst_x(rst_x),
// system bus
.i_req(i_req_s),
.i_wr(i_wr_s),
.i_adrs(i_adrs_s),
.o_ack(o_ack_s),
.i_len(i_len_s),
.i_be(i_be_s),
.i_dbw(i_dbw_s),
.o_strr(o_strr_s),
.o_dbr(o_dbr_s),
// triangle data
.o_valid(w_valid),
.o_ml(w_ml),
.o_vtx0_x(w_vtx0_x),
.o_vtx0_y(w_vtx0_y),
.o_vtx0_z(w_vtx0_z),
.o_vtx0_iw(w_vtx0_iw),
.o_vtx0_p00(w_vtx0_p00),
.o_vtx0_p01(w_vtx0_p01),
.o_vtx0_p02(w_vtx0_p02),
.o_vtx0_p03(w_vtx0_p03),
.o_vtx0_p10(w_vtx0_p10),
.o_vtx0_p11(w_vtx0_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.o_vtx0_p12(w_vtx0_p12),
.o_vtx0_p13(w_vtx0_p13),
`endif
.o_vtx1_x(w_vtx1_x),
.o_vtx1_y(w_vtx1_y),
.o_vtx1_z(w_vtx1_z),
.o_vtx1_iw(w_vtx1_iw),
.o_vtx1_p00(w_vtx1_p00),
.o_vtx1_p01(w_vtx1_p01),
.o_vtx1_p02(w_vtx1_p02),
.o_vtx1_p03(w_vtx1_p03),
.o_vtx1_p10(w_vtx1_p10),
.o_vtx1_p11(w_vtx1_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.o_vtx1_p12(w_vtx1_p12),
.o_vtx1_p13(w_vtx1_p13),
`endif
.o_vtx2_x(w_vtx2_x),
.o_vtx2_y(w_vtx2_y),
.o_vtx2_z(w_vtx2_z),
.o_vtx2_iw(w_vtx2_iw),
.o_vtx2_p00(w_vtx2_p00),
.o_vtx2_p01(w_vtx2_p01),
.o_vtx2_p02(w_vtx2_p02),
.o_vtx2_p03(w_vtx2_p03),
.o_vtx2_p10(w_vtx2_p10),
.o_vtx2_p11(w_vtx2_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.o_vtx2_p12(w_vtx2_p12),
.o_vtx2_p13(w_vtx2_p13),
`endif
.i_ack(w_ack),
// configuration registers
.o_aa_en(w_aa_en),
.o_attr0_en(w_attr0_en),
.o_attr0_kind(w_attr0_kind),
.o_attr0_size(w_attr0_size),
.o_attr1_en(w_attr1_en),
.o_attr1_kind(w_attr1_kind),
.o_attr1_size(w_attr1_size),
.o_tex_enable(w_tex_enable),
.o_tex_format(w_tex_format),
.o_tex_offset(w_tex_offset),
.o_tex_width_m1_f(w_tex_width_m1_f),
.o_tex_height_m1_f(w_tex_height_m1_f),
.o_tex_width_ui(w_tex_width_ui),
.o_tex_blend_enable(w_tex_blend_enable),
.o_color_offset(w_color_offset),
.o_color_ms_offset(w_color_ms_offset),
.o_depth_offset(w_depth_offset),
.o_depth_ms_offset(w_depth_ms_offset),
.o_depth_test_en(w_depth_test_en),
.o_depth_mask(),
.o_depth_func(w_depth_func),
.o_color_blend_en(w_color_blend_en),
.o_color_blend_eq(w_color_blend_eq),
.o_color_blend_sf(w_color_blend_sf),
.o_color_blend_df(w_color_blend_df),
.o_color_mask(w_color_mask),
.o_screen_flip(w_screen_flip),
.o_ag_mode(w_ag_mode),
.o_cache_init(w_cache_init),
.o_cache_flush(w_cache_flush),
.i_flush_done(w_flush_done),
// idle state indicator
.i_idle_ru(w_idle_ru),
.i_idle_tu(w_idle_tu),
.i_idle_pu(w_idle_pu),
// to system configuration
.o_vtx_int(o_vtx_int),
// dma access
.o_req_dma(o_req_dma),
.o_adrs_dma(o_adrs_dma),
.o_len_dma(o_len_dma),
.i_ack_dma(i_ack_dma),
.i_strr_dma(i_strr_dma),
.i_dbr_dma(i_dbr_dma),
// debug
.o_idle(o_idle),
.o_ff(o_ff),
.o_fe(o_fe)
);
// rasterizer unit
fm_3d_ru u_3d_ru (
.clk_core(clk_core),
.rst_x(rst_x),
// triangle data
.i_valid(w_valid),
.o_ack(w_ack),
.i_ml(w_ml),
.i_vtx0_x(w_vtx0_x),
.i_vtx0_y(w_vtx0_y),
.i_vtx0_z(w_vtx0_z),
.i_vtx0_iw(w_vtx0_iw),
.i_vtx0_p00(w_vtx0_p00),
.i_vtx0_p01(w_vtx0_p01),
.i_vtx0_p02(w_vtx0_p02),
.i_vtx0_p03(w_vtx0_p03),
.i_vtx0_p10(w_vtx0_p10),
.i_vtx0_p11(w_vtx0_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx0_p12(w_vtx0_p12),
.i_vtx0_p13(w_vtx0_p13),
`endif
.i_vtx1_x(w_vtx1_x),
.i_vtx1_y(w_vtx1_y),
.i_vtx1_z(w_vtx1_z),
.i_vtx1_iw(w_vtx1_iw),
.i_vtx1_p00(w_vtx1_p00),
.i_vtx1_p01(w_vtx1_p01),
.i_vtx1_p02(w_vtx1_p02),
.i_vtx1_p03(w_vtx1_p03),
.i_vtx1_p10(w_vtx1_p10),
.i_vtx1_p11(w_vtx1_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx1_p12(w_vtx1_p12),
.i_vtx1_p13(w_vtx1_p13),
`endif
.i_vtx2_x(w_vtx2_x),
.i_vtx2_y(w_vtx2_y),
.i_vtx2_z(w_vtx2_z),
.i_vtx2_iw(w_vtx2_iw),
.i_vtx2_p00(w_vtx2_p00),
.i_vtx2_p01(w_vtx2_p01),
.i_vtx2_p02(w_vtx2_p02),
.i_vtx2_p03(w_vtx2_p03),
.i_vtx2_p10(w_vtx2_p10),
.i_vtx2_p11(w_vtx2_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx2_p12(w_vtx2_p12),
.i_vtx2_p13(w_vtx2_p13),
`endif
// control registers
.i_aa_en(w_aa_en),
.i_attr0_en(w_attr0_en),
.i_attr0_size(w_attr0_size),
.i_attr0_kind(w_attr0_kind),
.i_attr1_en(w_attr1_en),
.i_attr1_size(w_attr1_size),
.i_attr1_kind(w_attr1_kind),
.o_idle(w_idle_ru),
// pixel unit bus
.o_valid_pu(w_valid_rp),
.i_busy_pu(w_busy_pr),
.o_aa_mode(w_aa_mode),
.o_x(w_x),
.o_y(w_y),
.o_z(w_z),
.o_cr(w_cr),
.o_cg(w_cg),
.o_cb(w_cb),
.o_ca(w_ca),
// texture unit bus
.o_valid_tu(w_valid_rt),
.i_busy_tu(w_busy_tr),
.o_tu(w_tu_rt),
.o_tv(w_tv_rt)
);
// texture unit
fm_3d_tu u_3d_tu (
.clk_core(clk_core),
.rst_x(rst_x),
// register configuration
.i_tex_enable(w_tex_enable),
.i_tex_format(w_tex_format),
.i_tex_offset(w_tex_offset),
.i_tex_width_m1_f(w_tex_width_m1_f),
.i_tex_height_m1_f(w_tex_height_m1_f),
.i_tex_width_ui(w_tex_width_ui),
.o_idle(w_idle_tu),
// rasterizer bus
.i_valid(w_valid_rt),
.i_tu(w_tu_rt),
.i_tv(w_tv_rt),
.o_busy(w_busy_tr),
// pixel unit bus
.o_valid(w_valid_tp),
.o_tr(w_tr_tp),
.o_tg(w_tg_tp),
.o_tb(w_tb_tp),
.o_ta(w_ta_tp),
.i_busy(w_busy_pt),
// memory bus
.o_req(w_req_tu),
.o_adrs(w_adrs_tu),
.i_ack(w_ack_tu),
.o_len(w_len_tu),
.i_strr(w_strr_tu),
.i_dbr(w_dbr_tu)
);
// pixel unit
fm_3d_pu pu (
.clk_core(clk_core),
.rst_x(rst_x),
// register configuration
.i_tex_enable(w_tex_enable),
.i_tex_blend_enable(w_tex_blend_enable),
.i_color_offset(w_color_offset),
.i_color_ms_offset(w_color_ms_offset),
.i_depth_offset(w_depth_offset),
.i_depth_ms_offset(w_depth_ms_offset),
.i_depth_test_en(w_depth_test_en),
.i_depth_func(w_depth_func),
.i_color_blend_en(w_color_blend_en),
.i_color_blend_eq(w_color_blend_eq),
.i_color_blend_sf(w_color_blend_sf),
.i_color_blend_df(w_color_blend_df),
.i_color_mask(w_color_mask),
.i_color_mode(i_color_mode),
.i_screen_flip(w_screen_flip),
.i_ag_mode(w_ag_mode),
.o_idle(w_idle_pu),
// rasterizer unit
.i_valid_ru(w_valid_rp),
.i_aa_mode(w_aa_mode),
.i_x(w_x),
.i_y(w_y),
.i_z(w_z),
.i_cr(w_cr),
.i_cg(w_cg),
.i_cb(w_cb),
.i_ca(w_ca),
.o_busy_ru(w_busy_pr),
// texture unit
.i_valid_tu(w_valid_tp),
.i_tr(w_tr_tp),
.i_tg(w_tg_tp),
.i_tb(w_tb_tp),
.i_ta(w_ta_tp),
.o_busy_tu(w_busy_pt),
// color
.o_req_cb(w_req_cb),
.o_wr_cb(w_wr_cb),
.o_adrs_cb(w_adrs_cb),
.i_ack_cb(w_ack_cb),
.o_len_cb(w_len_cb),
.o_be_cb(w_be_cb),
.o_strw_cb(w_strw_cb),
.o_dbw_cb(w_dbw_cb),
.i_ackw_cb(w_ackw_cb),
.i_strr_cb(w_strr_cb),
.i_dbr_cb(w_dbr_cb),
// depth
.o_req_db(w_req_db),
.o_wr_db(w_wr_db),
.o_adrs_db(w_adrs_db),
.i_ack_db(w_ack_db),
.o_len_db(w_len_db),
.o_be_db(w_be_db),
.o_strw_db(w_strw_db),
.o_dbw_db(w_dbw_db),
.i_ackw_db(w_ackw_db),
.i_strr_db(w_strr_db),
.i_dbr_db(w_dbr_db)
);
// memory unit
fm_3d_mu u_3d_mu (
.clk_core(clk_core),
.rst_x(rst_x),
// configuration
.i_cache_init(w_cache_init),
.i_cache_flush(w_cache_flush),
.o_flush_done(w_flush_done),
// texture unit
.i_req_tu(w_req_tu),
.i_adrs_tu(w_adrs_tu),
.o_ack_tu(w_ack_tu),
.i_len_tu(w_len_tu),
.o_strr_tu(w_strr_tu),
.o_dbr_tu(w_dbr_tu),
// color
.i_req_cb(w_req_cb),
.i_wr_cb(w_wr_cb),
.i_adrs_cb(w_adrs_cb),
.o_ack_cb(w_ack_cb),
.i_len_cb(w_len_cb),
.i_be_cb(w_be_cb),
.i_strw_cb(w_strw_cb),
.i_dbw_cb(w_dbw_cb),
.o_ackw_cb(w_ackw_cb),
.o_strr_cb(w_strr_cb),
.o_dbr_cb(w_dbr_cb),
// depth
.i_req_db(w_req_db),
.i_wr_db(w_wr_db),
.i_adrs_db(w_adrs_db),
.o_ack_db(w_ack_db),
.i_len_db(w_len_db),
.i_be_db(w_be_db),
.i_strw_db(w_strw_db),
.i_dbw_db(w_dbw_db),
.o_ackw_db(w_ackw_db),
.o_strr_db(w_strr_db),
.o_dbr_db(w_dbr_db),
// system memory interconnect
.o_req_m(o_req_m),
.o_wr_m(o_wr_m),
.o_adrs_m(o_adrs_m),
.i_ack_m(i_ack_m),
.o_len_m(o_len_m),
.o_be_m(o_be_m),
.o_strw_m(o_strw_m),
.o_dbw_m(o_dbw_m),
.i_ackw_m(i_ackw_m),
.i_strr_m(i_strr_m),
.i_dbr_m(i_dbr_m)
);
endmodule
|
module fm_3d_vtx_dma (
clk_core,
rst_x,
// system port
i_dma_start,
o_dma_end,
i_vtx_top_address,
i_total_size,
i_num_of_tris,
i_num_of_elements,
i_attr0_en,
i_attr0_size,
i_attr1_en,
i_attr1_size,
// register control
o_render_start,
i_render_ack,
i_render_idle,
o_req_dma,
o_adrs_dma,
o_dbw_dma,
// memory port
o_req,
o_adrs,
o_len,
i_ack,
i_strr,
i_dbr,
// debug port
o_error,
i_idle_ru,
i_idle_tu,
i_idle_pu,
o_ff,
o_fe
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
// dma read state
parameter P_DMA_IDLE = 3'h0;
parameter P_DMA_IN = 3'h1;
parameter P_DMA_NEXT = 3'h2;
parameter P_DMA_END = 3'h3;
parameter P_DMA_WAIT_EMPTY = 3'h4;
// vertex set state
parameter P_VS_X = 4'h0;
parameter P_VS_Y = 4'h1;
parameter P_VS_Z = 4'h2;
parameter P_VS_IW = 4'h3;
parameter P_VS_P00 = 4'h4;
parameter P_VS_P01 = 4'h5;
parameter P_VS_P02 = 4'h6;
parameter P_VS_P03 = 4'h7;
parameter P_VS_P10 = 4'h8;
parameter P_VS_P11 = 4'h9;
parameter P_VS_P12 = 4'ha;
parameter P_VS_P13 = 4'hb;
parameter P_TRI_V0 = 2'h0;
parameter P_TRI_V1 = 2'h1;
parameter P_TRI_V2 = 2'h2;
parameter P_TRI_OUTPUT = 2'h3;
parameter P_REG_IDLE = 2'h0;
parameter P_REG_WAIT = 2'h1;
parameter P_REG_OUT = 2'h2;
//////////////////////////////////
// I/O port definition
//////////////////////////////////
input clk_core;
input rst_x;
// system port
input i_dma_start;
output o_dma_end;
input [15:0] i_vtx_top_address;
input [20:0] i_total_size;
input [15:0] i_num_of_tris;
input [4:0] i_num_of_elements;
input i_attr0_en;
input [1:0] i_attr0_size;
input i_attr1_en;
input [1:0] i_attr1_size;
// register control
output o_render_start;
input i_render_ack;
input i_render_idle;
output o_req_dma;
output [21:0] o_adrs_dma;
output [31:0] o_dbw_dma;
// memory port
output o_req;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs;
output [P_IB_LEN_WIDTH-1:0]
o_len;
input i_ack;
input i_strr;
input [P_IB_DATA_WIDTH-1:0]
i_dbr;
// debug port
output [1:0] o_error;
output [15:0] o_ff;
output [4:0] o_fe;
input i_idle_ru;
input i_idle_tu;
input i_idle_pu;
//////////////////////////////////
// reg
//////////////////////////////////
reg [2:0] r_dma_state;
reg [15:0] r_cnt_h;
reg [4:0] r_cnt_l;
reg [1:0] r_tri_state;
reg [3:0] r_vtx_state;
reg [15:0] r_num_of_tris;
reg [1:0] r_reg_state;
reg [5:0] r_reg_adrs;
reg r_vtx_injection_end;
reg [6:0] r_current_req_size;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_cnt_l_init;
wire [5:0] w_max_burst;
wire w_cnt_h_init;
wire w_cnt_h_inc;
wire w_dma_end;
wire w_32burst_accepted;
wire w_has_fifo_space;
wire [6:0] w_fifo_num;
wire w_vtx_injection_end;
wire w_vtx_injection_end_pre;
wire w_size_init;
wire w_size_inc;
wire w_fifo_ren;
wire w_fifo_empty;
wire w_fifo_full;
wire w_next_vtx;
wire w_state_init;
wire w_register_mode;
wire w_set_reg_adrs;
wire w_req_vtx;
wire w_req_reg;
wire w_reg_cmd;
wire [15:0] w_adrs16;
wire w_data_out;
`ifdef PP_BUSWIDTH_64
wire w_discard_l32;
`endif
//////////////////////////////////
// assign
//////////////////////////////////
assign w_data_out = !w_fifo_empty & w_fifo_ren;
assign o_req = (r_dma_state == P_DMA_IN);
// bit
// i_vtx_top_address[31:16]
// r_cnt_h[21:6]
assign w_adrs16 = r_cnt_h + {i_vtx_top_address[6:2],11'b0};
// 9 16 5
`ifdef PP_BUSWIDTH_64
assign o_adrs = {i_vtx_top_address[15:7], w_adrs16, 4'h0};
assign w_discard_l32 = f_discard(r_cnt_h, i_total_size);
assign o_len = f_len64(w_max_burst);
`else
assign o_adrs = {i_vtx_top_address[15:7], w_adrs16, 5'h0};
assign o_len = w_max_burst;
`endif
assign w_cnt_l_init = (r_dma_state == P_DMA_IDLE) & i_dma_start;
assign w_cnt_h_init = w_cnt_l_init;
assign w_cnt_h_inc = w_32burst_accepted;
assign w_max_burst = f_len(r_cnt_h, i_total_size);
assign w_32burst_accepted = (o_req & i_ack);
// assign w_has_fifo_space = (w_fifo_num <= 7'd32);
assign w_has_fifo_space = (r_current_req_size <= 7'd32);
assign w_dma_end = (r_dma_state == P_DMA_NEXT) &
(i_total_size == {r_cnt_h, r_cnt_l});
assign w_vtx_injection_end_pre = // w_fifo_empty &
(r_tri_state == P_TRI_OUTPUT) &
(r_num_of_tris == i_num_of_tris) &
i_render_ack;
assign w_vtx_injection_end = w_vtx_injection_end_pre | r_vtx_injection_end;
assign o_dma_end = (r_dma_state == P_DMA_END) & w_vtx_injection_end;
assign w_next_vtx = !w_fifo_empty &
(
((r_vtx_state == P_VS_IW)&!i_attr0_en&!i_attr1_en) |
((r_vtx_state == P_VS_P01)&(i_attr0_size == 2'd1)&!i_attr1_en) |
((r_vtx_state == P_VS_P02)&(i_attr0_size == 2'd2)&!i_attr1_en) |
((r_vtx_state == P_VS_P03)&!i_attr1_en) |
((r_vtx_state == P_VS_P11)&(i_attr1_size == 2'd1)) |
((r_vtx_state == P_VS_P12)&(i_attr1_size == 2'd2)) |
(r_vtx_state == P_VS_P13));
assign w_state_init = (r_tri_state == P_TRI_OUTPUT) & i_render_ack;
assign o_req_dma = w_req_vtx | w_req_reg;
assign w_req_vtx = !w_fifo_empty & (r_tri_state != P_TRI_OUTPUT) & !w_register_mode;
assign w_req_reg = !w_fifo_empty & (r_reg_state == P_REG_OUT);
assign o_adrs_dma = (r_reg_state == P_REG_OUT) ? {12'b0, 4'b10 ,r_reg_adrs,2'b00} :
f_vtx_adrs_enc(r_tri_state, r_vtx_state);
assign o_render_start = (r_tri_state == P_TRI_OUTPUT);
assign w_size_init = (r_dma_state == P_DMA_IDLE);
assign w_size_inc = (r_tri_state == P_TRI_OUTPUT) & i_render_ack;
assign w_fifo_ren = !((r_tri_state == P_TRI_OUTPUT)| (r_reg_state == P_REG_WAIT));
assign w_reg_cmd = (o_dbw_dma[31:16] == 16'h7F88);
assign w_set_reg_adrs = w_reg_cmd&!w_fifo_empty&(r_tri_state != P_TRI_OUTPUT);
assign w_register_mode = !((r_reg_state == P_REG_IDLE) & !w_set_reg_adrs);
// debug port
//assign o_ff = w_fifo_full;
//assign o_fe = w_fifo_empty;
assign o_ff = r_num_of_tris;
assign o_fe = {w_vtx_injection_end,w_vtx_injection_end_pre,r_dma_state};
assign o_error[0] = w_fifo_full & i_strr;
assign o_error[1] = w_fifo_ren & w_fifo_empty;
//////////////////////////////////
// always
//////////////////////////////////
// fifo full detection
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_current_req_size <= 'd0;
end else begin
if (w_32burst_accepted) begin
if (w_data_out) begin
r_current_req_size <= r_current_req_size + w_max_burst - 1'b1;
end else begin
r_current_req_size <= r_current_req_size + w_max_burst;
end
end else if (w_data_out) begin
r_current_req_size <= r_current_req_size - 1'b1;
end
end
end
// vertex read state from system memory
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_dma_state <= P_DMA_IDLE;
end else begin
case (r_dma_state)
P_DMA_IDLE : begin
if (i_dma_start) begin
r_dma_state <= P_DMA_IN;
end
end
P_DMA_IN : begin
if (w_32burst_accepted) r_dma_state <= P_DMA_NEXT;
end
P_DMA_NEXT : begin
if (w_dma_end) begin
r_dma_state <= P_DMA_END;
end else begin
if (w_has_fifo_space) r_dma_state <= P_DMA_IN;
end
end
P_DMA_END : begin
if (w_vtx_injection_end) r_dma_state <= P_DMA_WAIT_EMPTY;
end
P_DMA_WAIT_EMPTY: begin // remained register configurations
if (w_fifo_empty) r_dma_state <= P_DMA_IDLE;
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_cnt_l <= 5'd0;
end else begin
if (w_cnt_l_init) r_cnt_l <= 5'd0;
else if (w_32burst_accepted) r_cnt_l <= w_max_burst[4:0];
end
end
// upper 16-bit counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_cnt_h <= 16'd0;
end else begin
if (w_cnt_h_init) r_cnt_h <= 16'd0;
else if (w_32burst_accepted) r_cnt_h <= r_cnt_h + w_max_burst[5];
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_num_of_tris <= 16'd1;
end else begin
if (w_size_init) r_num_of_tris <= 16'h1;
else if (w_size_inc) r_num_of_tris <= r_num_of_tris + 1'b1;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_vtx_state <= P_VS_X;
end else begin
if (w_state_init) begin
r_vtx_state <= P_VS_X;
end else begin
case (r_vtx_state)
P_VS_X: begin
if (w_req_vtx)r_vtx_state <= P_VS_Y;
end
P_VS_Y: begin
if (!w_fifo_empty) r_vtx_state <= P_VS_Z;
end
P_VS_Z: begin
if (!w_fifo_empty) r_vtx_state <= P_VS_IW;
end
P_VS_IW: begin
if (!w_fifo_empty) begin
if (i_attr0_en) begin
r_vtx_state <= P_VS_P00;
end else if (i_attr1_en) begin
r_vtx_state <= P_VS_P10;
end else begin
r_vtx_state <= P_VS_X;
end
end
end
P_VS_P00: begin
if (!w_fifo_empty) begin
r_vtx_state <= P_VS_P01;
end
end
P_VS_P01: begin
if (!w_fifo_empty) begin
if (i_attr0_size == 2'd1) begin
if (i_attr1_en) r_vtx_state <= P_VS_P10;
else r_vtx_state <= P_VS_X;
end else begin
r_vtx_state <= P_VS_P02;
end
end
end
P_VS_P02: begin
if (!w_fifo_empty) begin
if (i_attr0_size == 2'd2) begin
if (i_attr1_en) r_vtx_state <= P_VS_P10;
else r_vtx_state <= P_VS_X;
end else begin
r_vtx_state <= P_VS_P03;
end
end
end
P_VS_P03: begin
if (!w_fifo_empty) begin
if (i_attr1_en) r_vtx_state <= P_VS_P10;
else r_vtx_state <= P_VS_X;
end
end
P_VS_P10: begin
if (!w_fifo_empty) begin
r_vtx_state <= P_VS_P11;
end
end
P_VS_P11: begin
if (!w_fifo_empty) begin
if (i_attr1_size == 2'd1) begin
r_vtx_state <= P_VS_X;
end else begin
r_vtx_state <= P_VS_P12;
end
end
end
P_VS_P12: begin
if (!w_fifo_empty) begin
if (i_attr0_size == 2'd2) begin
r_vtx_state <= P_VS_X;
end else begin
r_vtx_state <= P_VS_P13;
end
end
end
P_VS_P13: begin
if (!w_fifo_empty) begin
r_vtx_state <= P_VS_X;
end
end
endcase
end
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_tri_state <= P_TRI_V0;
end else begin
case (r_tri_state)
P_TRI_V0: begin
if (w_next_vtx) r_tri_state <= P_TRI_V1;
end
P_TRI_V1: begin
if (w_next_vtx) r_tri_state <= P_TRI_V2;
end
P_TRI_V2: begin
if (w_next_vtx) r_tri_state <= P_TRI_OUTPUT;
end
P_TRI_OUTPUT: begin
if (i_render_ack) r_tri_state <= P_TRI_V0;
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_reg_state <= P_REG_IDLE;
end else begin
case (r_reg_state)
P_REG_IDLE: begin
if (w_set_reg_adrs) r_reg_state <= P_REG_WAIT;
end
P_REG_WAIT: begin
if (i_render_idle) r_reg_state <= P_REG_OUT;
end
P_REG_OUT: begin
if (!w_fifo_empty) r_reg_state <= P_REG_IDLE;
end
endcase
end
end
always @(posedge clk_core) begin
if (w_set_reg_adrs) r_reg_adrs <= o_dbw_dma[7:2]; // 32bits address
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_vtx_injection_end <= 1'b0;
end else begin
if (w_size_init) r_vtx_injection_end <= 1'b0;
else if (w_vtx_injection_end_pre) r_vtx_injection_end <= 1'b1;
end
end
//////////////////////////////////
// function
//////////////////////////////////
function [5:0] f_len;
input [15:0] cnt_h;
input [20:0] total_size;
reg cmp;
reg [4:0] next_len;
begin
cmp = (cnt_h == total_size[20:5]); // check length > 32
next_len = {1'b0,total_size[4:0]};
if (cmp) f_len = next_len;
else f_len = 6'd32;
end
endfunction
`ifdef PP_BUSWIDTH_64
function [5:0] f_len64;
input [5:0] len32; // 23bit burst size
begin
if (len32[0]) f_len64 = {1'b0,len32[5:1]} + len32[0];
else f_len64 = {1'b0,len32[5:1]};
end
endfunction
`endif // `ifdef PP_BUSWIDTH_64
function f_discard;
input [15:0] cnt_h;
input [20:0] total_size;
reg cmp;
begin
cmp = (cnt_h == total_size[20:5]); // check length > 32
if (cmp) f_discard = total_size[0];
else f_discard = 1'b0;
end
endfunction
function [21:0] f_vtx_adrs_enc;
input [1:0] tri_state;
input [3:0] vtx_state;
reg [5:0] adrs;
begin
case (tri_state)
P_TRI_V0: begin
case (vtx_state)
P_VS_X: adrs = (`VTX0_X >> 2);
P_VS_Y: adrs = (`VTX0_Y >> 2);
P_VS_Z: adrs = (`VTX0_Z >> 2);
P_VS_IW: adrs = (`VTX0_IW >> 2);
P_VS_P00: adrs = (`VTX0_P00 >> 2);
P_VS_P01: adrs = (`VTX0_P01 >> 2);
P_VS_P02: adrs = (`VTX0_P02 >> 2);
P_VS_P03: adrs = (`VTX0_P03 >> 2);
P_VS_P10: adrs = (`VTX0_P10 >> 2);
P_VS_P11: adrs = (`VTX0_P11 >> 2);
`ifdef VTX_PARAM1_REDUCE
`else
P_VS_P12: adrs = (`VTX0_P12 >> 2);
P_VS_P13: adrs = (`VTX0_P13 >> 2);
`endif
default: adrs = 6'b0;
endcase
end
P_TRI_V1: begin
case (vtx_state)
P_VS_X: adrs = (`VTX1_X >> 2);
P_VS_Y: adrs = (`VTX1_Y >> 2);
P_VS_Z: adrs = (`VTX1_Z >> 2);
P_VS_IW: adrs = (`VTX1_IW >> 2);
P_VS_P00: adrs = (`VTX1_P00 >> 2);
P_VS_P01: adrs = (`VTX1_P01 >> 2);
P_VS_P02: adrs = (`VTX1_P02 >> 2);
P_VS_P03: adrs = (`VTX1_P03 >> 2);
P_VS_P10: adrs = (`VTX1_P10 >> 2);
P_VS_P11: adrs = (`VTX1_P11 >> 2);
`ifdef VTX_PARAM1_REDUCE
`else
P_VS_P12: adrs = (`VTX1_P12 >> 2);
P_VS_P13: adrs = (`VTX1_P13 >> 2);
`endif
default: adrs = 6'b0;
endcase
end
P_TRI_V2: begin
case (vtx_state)
P_VS_X: adrs = (`VTX2_X >> 2);
P_VS_Y: adrs = (`VTX2_Y >> 2);
P_VS_Z: adrs = (`VTX2_Z >> 2);
P_VS_IW: adrs = (`VTX2_IW >> 2);
P_VS_P00: adrs = (`VTX2_P00 >> 2);
P_VS_P01: adrs = (`VTX2_P01 >> 2);
P_VS_P02: adrs = (`VTX2_P02 >> 2);
P_VS_P03: adrs = (`VTX2_P03 >> 2);
P_VS_P10: adrs = (`VTX2_P10 >> 2);
P_VS_P11: adrs = (`VTX2_P11 >> 2);
`ifdef VTX_PARAM1_REDUCE
`else
P_VS_P12: adrs = (`VTX2_P12 >> 2);
P_VS_P13: adrs = (`VTX2_P13 >> 2);
`endif
default: adrs = 6'b0;
endcase
end
default: adrs = 6'b0;
endcase
f_vtx_adrs_enc = {12'b0,4'b11,adrs,2'b00};
end
endfunction
//////////////////////////////////
// module instance
//////////////////////////////////
`ifdef PP_BUSWIDTH_64
fm_3d_vtx_fifo #(5) u_fifo ( // 32 words
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(i_strr),
.i_dt(i_dbr),
.o_full(w_fifo_full),
.i_renable(w_fifo_ren),
.o_dt(o_dbw_dma),
.o_empty(w_fifo_empty),
.o_dnum(w_fifo_num),
// 32bit discard flag
.i_req(w_32burst_accepted),
.i_len(o_len),
.i_discard(w_discard_l32)
);
`else
fm_cmn_bfifo #(P_IB_DATA_WIDTH ,6) u_fifo ( // 64 words
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(i_strr),
.i_dt(i_dbr),
.o_full(w_fifo_full),
.i_renable(w_fifo_ren),
.o_dt(o_dbw_dma),
.o_empty(w_fifo_empty),
.o_dnum(w_fifo_num)
);
`endif
// debug code
`ifdef RTL_DEBUG
`else
/*
ila_0 ila_pp (
.clk(clk_core),
.probe0(i_dma_start),
.probe1(i_vtx_top_address[15:0]),
.probe2(i_total_size[20:0]),
.probe3(i_num_of_tris[15:0]),
.probe4(o_req),
.probe5(o_adrs[28:0]),
.probe6(i_strr),
.probe7(i_dbr[63:0])
);
*/
/*
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
chipscope_icon_v1_06_a_0 u_icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_ila_v1_05_a_0 u_chipscope (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(clk_core), // IN
.TRIG0(TRIG0) // IN BUS [255:0]
// .DATA(DATA)
);
assign TRIG0[0] = i_dma_start;
assign TRIG0[1] = o_dma_end;
assign TRIG0[17:2] = r_num_of_tris[15:0];
assign TRIG0[22:18] = i_num_of_elements[4:0];
assign TRIG0[23] = o_render_start;
assign TRIG0[24] = i_render_ack;
assign TRIG0[25] = i_render_idle;
assign TRIG0[26] = o_req;
assign TRIG0[56:27] = {1'b0,o_adrs[28:0]};
assign TRIG0[62:57] = o_len[5:0];
assign TRIG0[63] = i_ack;
assign TRIG0[64] = i_strr;
assign TRIG0[128:65] = i_dbr[63:0];
assign TRIG0[131:129] = r_dma_state[2:0];
assign TRIG0[133:132] = r_tri_state[1:0];
assign TRIG0[137:134] = r_vtx_state[3:0];
assign TRIG0[138] = r_vtx_injection_end;
assign TRIG0[139] = w_vtx_injection_end;
assign TRIG0[140] = w_vtx_injection_end_pre;
assign TRIG0[141] = w_fifo_full;
assign TRIG0[142] = w_fifo_ren;
assign TRIG0[174:143] = o_dbw_dma[31:0];
assign TRIG0[175] = w_fifo_empty;
assign TRIG0[176] = w_32burst_accepted;
assign TRIG0[182:177] = o_len[5:0];
assign TRIG0[183] = w_discard_l32;
assign TRIG0[184] = i_idle_ru;
assign TRIG0[185] = i_idle_tu;
assign TRIG0[186] = i_idle_pu;
assign TRIG0[202:187] = i_vtx_top_address[15:0];
assign TRIG0[223:203] = i_total_size[20:0];
assign TRIG0[239:224] = i_num_of_tris[15:0];
*/
`endif
endmodule
|
module fm_3d_fcnv (
i_f32,
o_f22
);
////////////////////////////
// I/O definition
////////////////////////////
input [31:0] i_f32;
output [21:0] o_f22;
////////////////////////////
// assign
////////////////////////////
assign o_f22 = f_f32_to_f22(i_f32);
////////////////////////////
// function
////////////////////////////
function [21:0] f_f32_to_f22;
input [31:0] f32;
reg s;
reg [7:0] e8;
reg [8:0] e8d; // width sign bit
reg [4:0] e5;
reg [23:0] m23;
reg [14:0] m15;
reg carry;
reg zf;
begin
s = f32[31];
e8 = f32[30:23];
zf = (e8 == 8'h00);
m23 = f32[22:0];
{carry,m15} = m23[22:8] + m23[7];
e8d = e8 - 112 + carry; // -127+15 + carry
if (zf|e8d[8]) begin
e5 = 5'h0;
end else begin
e5 = e8d[4:0];
end
f_f32_to_f22 = {s,e5,!(zf|e8d[8]),m15};
end
endfunction
endmodule
|
module fm_3d_mu (
clk_core,
rst_x,
// system configuration
i_cache_init,
i_cache_flush,
o_flush_done,
// texture unit
i_req_tu,
i_adrs_tu,
o_ack_tu,
i_len_tu,
o_strr_tu,
o_dbr_tu,
// color
i_req_cb,
i_wr_cb,
i_adrs_cb,
o_ack_cb,
i_len_cb,
i_be_cb,
i_strw_cb,
i_dbw_cb,
o_ackw_cb,
o_strr_cb,
o_dbr_cb,
// depth
i_req_db,
i_wr_db,
i_adrs_db,
o_ack_db,
i_len_db,
i_be_db,
i_strw_db,
i_dbw_db,
o_ackw_db,
o_strr_db,
o_dbr_db,
// system memory interconnect
o_req_m,
o_wr_m,
o_adrs_m,
i_ack_m,
o_len_m,
o_be_m,
o_strw_m,
o_dbw_m,
i_ackw_m,
i_strr_m,
i_dbr_m
);
`include "polyphony_params.v"
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// system configuration
input i_cache_init;
input i_cache_flush;
output o_flush_done;
// texture unit
input i_req_tu;
input [P_IB_ADDR_WIDTH-1:0]
i_adrs_tu;
output o_ack_tu;
input [P_IB_LEN_WIDTH-1:0]
i_len_tu;
output o_strr_tu;
output [P_IB_DATA_WIDTH-1:0]
o_dbr_tu;
// color
input i_req_cb;
input i_wr_cb;
input [P_IB_ADDR_WIDTH-1:0]
i_adrs_cb;
output o_ack_cb;
input [P_IB_LEN_WIDTH-1:0]
i_len_cb;
input [P_IB_BE_WIDTH-1:0]
i_be_cb;
input i_strw_cb;
input [P_IB_DATA_WIDTH-1:0]
i_dbw_cb;
output o_ackw_cb;
output o_strr_cb;
output [P_IB_DATA_WIDTH-1:0]
o_dbr_cb;
// depth
input i_req_db;
input i_wr_db;
input [P_IB_ADDR_WIDTH-1:0]
i_adrs_db;
output o_ack_db;
input [P_IB_LEN_WIDTH-1:0]
i_len_db;
input [P_IB_BE_WIDTH-1:0]
i_be_db;
input i_strw_db;
input [P_IB_DATA_WIDTH-1:0]
i_dbw_db;
output o_ackw_db;
output o_strr_db;
output [P_IB_DATA_WIDTH-1:0]
o_dbr_db;
// system memory interconnect
output o_req_m;
output o_wr_m;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs_m;
input i_ack_m;
output [P_IB_LEN_WIDTH-1:0]
o_len_m;
output [P_IB_BE_WIDTH-1:0]
o_be_m;
output o_strw_m;
output [P_IB_DATA_WIDTH-1:0]
o_dbw_m;
input i_ackw_m;
input i_strr_m;
input [P_IB_DATA_WIDTH-1:0]
i_dbr_m;
//////////////////////////////////
// wire
//////////////////////////////////
// port0 command/data fifo (write/read)
wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1-1:0]
w_fifo_cin0;
wire [P_IB_BE_WIDTH+P_IB_DATA_WIDTH-1:0]
w_fifo_din0; // write data bus + be
wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1-1:0]
w_fifo_cout0;
wire [P_IB_BE_WIDTH+P_IB_DATA_WIDTH-1:0]
w_fifo_dout0;
wire w_cfifo_ack0;
wire w_dfifo_ack0;
// port1 command/data fifo (read/write)
wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1-1:0]
w_fifo_cin1;
wire [P_IB_BE_WIDTH+P_IB_DATA_WIDTH-1:0]
w_fifo_din1; // write data bus + be
wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1-1:0]
w_fifo_cout1;
wire [P_IB_BE_WIDTH+P_IB_DATA_WIDTH-1:0]
w_fifo_dout1;
wire w_cfifo_ack1;
wire w_dfifo_ack1;
// port2 command/data fifo (read only)
wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH-1:0]
w_fifo_cin2;
wire [P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH-1:0]
w_fifo_cout2;
wire w_cfifo_ack2;
// port 0
wire w_req0;
wire w_we0;
wire [P_IB_ADDR_WIDTH-1:0]
w_add0;
wire [P_IB_LEN_WIDTH-1:0]
w_len0;
wire [P_IB_BE_WIDTH-1:0]
w_be0;
wire w_cack0;
wire w_strw0;
wire [P_IB_DATA_WIDTH-1:0]
w_dbw0;
wire w_wdata_read_end0;
wire w_wdata_ack0;
wire w_strr0;
wire [P_IB_DATA_WIDTH-1:0]
w_dbr0;
// port 1
wire w_req1;
wire w_we1;
wire [P_IB_ADDR_WIDTH-1:0]
w_add1;
wire [P_IB_LEN_WIDTH-1:0]
w_len1;
wire [P_IB_BE_WIDTH-1:0]
w_be1;
wire w_cack1;
wire w_strw1;
wire [P_IB_DATA_WIDTH-1:0]
w_dbw1;
wire w_wdata_read_end1;
wire w_wdata_ack1;
wire w_strr1;
wire [P_IB_DATA_WIDTH-1:0]
w_dbr1;
// port 2
wire w_req2;
wire [P_IB_ADDR_WIDTH-1:0]
w_add2;
wire [P_IB_LEN_WIDTH-1:0]
w_len2;
wire w_cack2;
// color
wire w_req_cb;
wire w_wr_cb;
wire [P_IB_ADDR_WIDTH-1:0]
w_adrs_cb;
wire w_ack_cb;
wire [P_IB_LEN_WIDTH-1:0]
w_len_cb;
wire [P_IB_BE_WIDTH-1:0]
w_be_cb;
wire w_strw_cb;
wire [P_IB_DATA_WIDTH-1:0]
w_dbw_cb;
wire w_ackw_cb;
wire w_strr_cb;
wire [P_IB_DATA_WIDTH-1:0]
w_dbr_cb;
// depth
wire w_req_db;
wire w_wr_db;
wire [P_IB_ADDR_WIDTH-1:0]
w_adrs_db;
wire w_ack_db;
wire [P_IB_LEN_WIDTH-1:0]
w_len_db;
wire [P_IB_BE_WIDTH-1:0]
w_be_db;
wire w_strw_db;
wire [P_IB_DATA_WIDTH-1:0]
w_dbw_db;
wire w_ackw_db;
wire w_strr_db;
wire [P_IB_DATA_WIDTH-1:0]
w_dbr_db;
// texture
wire w_req_tu;
wire [P_IB_ADDR_WIDTH-1:0]
w_adrs_tu;
wire w_ack_tu;
wire [P_IB_LEN_WIDTH-1:0]
w_len_tu;
wire w_strr_tu;
wire [P_IB_DATA_WIDTH-1:0]
w_dbr_tu;
//////////////////////////////////
// assign
//////////////////////////////////
`ifdef USE_CACHE_MODULE
`else
assign o_flush_done = 1'b1;
assign w_req_cb = i_req_cb;
assign w_wr_cb = i_wr_cb;
assign w_adrs_cb = i_adrs_cb;
assign o_ack_cb = w_ack_cb;
assign w_len_cb = i_len_cb;
assign w_be_cb = i_be_cb;
assign w_strw_cb = i_strw_cb;
assign w_dbw_cb = i_dbw_cb;
assign o_ackw_cb = w_ackw_cb;
assign o_strr_cb = w_strr_cb;
assign o_dbr_cb = w_dbr_cb;
// depth
assign w_req_db = i_req_db;
assign w_wr_db = i_wr_db;
assign w_adrs_db = i_adrs_db;
assign o_ack_db = w_ack_db;
assign w_len_db = i_len_db;
assign w_be_db = i_be_db;
assign w_strw_db = i_strw_db;
assign w_dbw_db = i_dbw_db;
assign o_ackw_db = w_ackw_db;
assign o_strr_db = w_strr_db;
assign o_dbr_db = w_dbr_db;
// texture
assign w_req_tu = i_req_tu;
assign w_adrs_tu = i_adrs_tu;
assign o_ack_tu = w_ack_tu;
assign w_len_tu = i_len_tu;
assign o_strr_tu = w_strr_tu;
assign o_dbr_tu = w_dbr_tu;
`endif
// port0 (color r/w)
assign w_fifo_cin0 = {w_wr_cb,w_adrs_cb,w_len_cb};
assign w_fifo_din0 = {w_be_cb,w_dbw_cb};
assign {w_we0,w_add0,w_len0} = w_fifo_cout0;
assign {w_be0,w_dbw0} = w_fifo_dout0;
// port1 (depth r/w)
assign w_fifo_cin1 = {w_wr_db,w_adrs_db,w_len_db};
assign w_fifo_din1 = {w_be_db,w_dbw_db};
assign {w_we1,w_add1,w_len1} = w_fifo_cout1;
assign {w_be1,w_dbw1} = w_fifo_dout1;
// port2 (rexture r0)
assign w_fifo_cin2 = {w_adrs_tu,w_len_tu};
assign {w_add2,w_len2} = w_fifo_cout2;
////////////////////////////
// module instance
////////////////////////////
// port 0
fm_3d_mu_cif #(P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1) mu_cif0 (
.clk_core(clk_core),
.rst_x(rst_x),
// bus side port
.i_bstr(w_req_cb),
.i_bdata(w_fifo_cin0),
.o_back(w_ack_cb),
// internal port
.o_istr(w_req0),
.o_idata(w_fifo_cout0),
.i_iack(w_cfifo_ack0)
);
fm_3d_mu_dif #(P_IB_BE_WIDTH+P_IB_DATA_WIDTH) mu_dif0 (
.clk_core(clk_core),
.rst_x(rst_x),
// bus side port
.i_bstr(w_strw_cb),
.i_bdata(w_fifo_din0),
.o_back(w_ackw_cb),
// internal port
.o_istr(w_strw0),
.o_idata(w_fifo_dout0),
.i_iack(w_dfifo_ack0)
);
a_port_unit a_port_unit0 (
.clk_core(clk_core),
.rst_x(rst_x),
// port side
.i_req(w_req0),
.i_we(w_we0),
.i_len(w_len0),
.o_ack(w_cfifo_ack0),
.i_strw(w_strw0),
.o_ackw(w_dfifo_ack0),
.o_strr(w_strr_cb),
.o_dbr(w_dbr_cb),
// internal
.i_cack(w_cack0),
.o_wdata_read_end(w_wdata_read_end0),
.i_wdata_ack(w_wdata_ack0),
.i_strr(w_strr0),
.i_dbr(w_dbr0)
);
// port1
fm_3d_mu_cif #(P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH+1) mu_cif1 (
.clk_core(clk_core),
.rst_x(rst_x),
// bus side port
.i_bstr(w_req_db),
.i_bdata(w_fifo_cin1),
.o_back(w_ack_db),
// internal port
.o_istr(w_req1),
.o_idata(w_fifo_cout1),
.i_iack(w_cfifo_ack1)
);
fm_3d_mu_dif #(P_IB_BE_WIDTH+P_IB_DATA_WIDTH) mu_dif1 (
.clk_core(clk_core),
.rst_x(rst_x),
// bus side port
.i_bstr(w_strw_db),
.i_bdata(w_fifo_din1),
.o_back(w_ackw_db),
// internal port
.o_istr(w_strw1),
.o_idata(w_fifo_dout1),
.i_iack(w_dfifo_ack1)
);
a_port_unit a_port_unit1 (
.clk_core(clk_core),
.rst_x(rst_x),
// port side
.i_req(w_req1),
.i_we(w_we1),
.i_len(w_len1),
.o_ack(w_cfifo_ack1),
.i_strw(w_strw1),
.o_ackw(w_dfifo_ack1),
.o_strr(w_strr_db),
.o_dbr(w_dbr_db),
// internal
.i_cack(w_cack1),
.o_wdata_read_end(w_wdata_read_end1),
.i_wdata_ack(w_wdata_ack1),
.i_strr(w_strr1),
.i_dbr(w_dbr1)
);
// port2
fm_3d_mu_cif #(P_IB_ADDR_WIDTH+P_IB_LEN_WIDTH) mu_cif2 (
.clk_core(clk_core),
.rst_x(rst_x),
// bus side port
.i_bstr(w_req_tu),
.i_bdata(w_fifo_cin2),
.o_back(w_ack_tu),
// internal port
.o_istr(w_req2),
.o_idata(w_fifo_cout2),
.i_iack(w_cfifo_ack2)
);
assign w_cfifo_ack2 = (w_req2) ? w_cack2 : 1'b1;
fm_3d_mu_priority mu_priority (
.clk_core(clk_core),
.rst_x(rst_x),
// port0 side Read/Write
.i_req0(w_req0),
.i_we0(w_we0),
.i_add0(w_add0),
.i_len0(w_len0),
.i_be0(w_be0),
.o_cack0(w_cack0),
.i_strw0(w_strw0),
.i_dbw0(w_dbw0),
.i_wdata_read_end0(w_wdata_read_end0),
.o_wdata_ack0(w_wdata_ack0),
.o_strr0(w_strr0),
.o_dbr0(w_dbr0),
// port1 side Read/Write
.i_req1(w_req1),
.i_we1(w_we1),
.i_add1(w_add1),
.i_len1(w_len1),
.i_be1(w_be1),
.o_cack1(w_cack1),
.i_strw1(w_strw1),
.i_dbw1(w_dbw1),
.i_wdata_read_end1(w_wdata_read_end1),
.o_wdata_ack1(w_wdata_ack1),
.o_strr1(w_strr1),
.o_dbr1(w_dbr1),
// port2 side Read Only
.i_req2(w_req2),
.i_add2(w_add2),
.i_len2(w_len2),
.o_cack2(w_cack2),
.o_strr2(w_strr_tu),
.o_dbr2(w_dbr_tu),
// to system arbiter
.o_breq(o_req_m),
.o_bwe(o_wr_m),
.o_badd(o_adrs_m),
.o_blen(o_len_m),
.i_back(i_ack_m),
.o_bstrw(o_strw_m),
.o_bbe(o_be_m),
.o_bdbw(o_dbw_m),
.i_backw(i_ackw_m),
.i_bstrr(i_strr_m),
.i_bdbr(i_dbr_m)
);
`ifdef USE_CACHE_MODULE
fm_3d_mu_cache mu_cache_color (
.clk_core(clk_core),
.rst_x(rst_x),
// system configuration
.i_cache_init(i_cache_init),
.i_cache_flush(i_cache_flush),
.o_flush_done(o_flush_done),
// cache in
.i_req_ci(i_req_cb),
.i_wr_ci(i_wr_cb),
.i_adrs_ci(i_adrs_cb),
.o_ack_ci(o_ack_cb),
.i_len_ci(i_len_cb),
.i_be_ci(i_be_cb),
.i_strw_ci(i_strw_cb),
.i_dbw_ci(i_dbw_cb),
.o_ackw_ci(o_ackw_cb),
.o_strr_ci(o_strr_cb),
.o_dbr_ci(o_dbr_cb),
// cache out
.o_req_co(w_req_cb),
.o_wr_co(w_wr_cb),
.o_adrs_co(w_adrs_cb),
.i_ack_co(w_ack_cb),
.o_len_co(w_len_cb),
.o_be_co(w_be_cb),
.o_strw_co(w_strw_cb),
.o_dbw_co(w_dbw_cb),
.i_ackw_co(w_ackw_cb),
.i_strr_co(w_strr_cb),
.i_dbr_co(w_dbr_cb)
);
fm_3d_mu_cache mu_cache_depth (
.clk_core(clk_core),
.rst_x(rst_x),
// system configuration
.i_cache_init(i_cache_init),
.i_cache_flush(1'b0),
.o_flush_done(),
// cache in
.i_req_ci(i_req_db),
.i_wr_ci(i_wr_db),
.i_adrs_ci(i_adrs_db),
.o_ack_ci(o_ack_db),
.i_len_ci(i_len_db),
.i_be_ci(i_be_db),
.i_strw_ci(i_strw_db),
.i_dbw_ci(i_dbw_db),
.o_ackw_ci(o_ackw_db),
.o_strr_ci(o_strr_db),
.o_dbr_ci(o_dbr_db),
// cache out
.o_req_co(w_req_db),
.o_wr_co(w_wr_db),
.o_adrs_co(w_adrs_db),
.i_ack_co(w_ack_db),
.o_len_co(w_len_db),
.o_be_co(w_be_db),
.o_strw_co(w_strw_db),
.o_dbw_co(w_dbw_db),
.i_ackw_co(w_ackw_db),
.i_strr_co(w_strr_db),
.i_dbr_co(w_dbr_db)
);
fm_3d_mu_cache_ro mu_cache_tex (
.clk_core(clk_core),
.rst_x(rst_x),
// system configuration
.i_cache_init(i_cache_init),
// cache in
.i_req_ci(i_req_tu),
.i_adrs_ci(i_adrs_tu),
.o_ack_ci(o_ack_tu),
.i_len_ci(i_len_tu),
.o_strr_ci(o_strr_tu),
.o_dbr_ci(o_dbr_tu),
// cache out
.o_req_co(w_req_tu),
.o_adrs_co(w_adrs_tu),
.i_ack_co(w_ack_tu),
.o_len_co(w_len_tu),
.i_strr_co(w_strr_tu),
.i_dbr_co(w_dbr_tu)
);
`endif
endmodule
|
module fm_3d_mu_cache_ctrl_ro (
clk_core,
rst_x,
// system configuration
i_cache_init,
// cache in
i_req_ci,
i_adrs_ci,
o_ack_ci,
i_len_ci,
o_strr_ci,
o_dbr_ci,
// cache tag
o_tw_valid,
o_cmp_adrs_pre,
o_cmp_adrs,
o_tag_clear,
i_hit,
i_entry,
i_tag_adrs,
//cache memory
o_we_cm,
o_adrs_cm,
o_be_cm,
o_dt_cm,
i_dt_cm,
// external memory access
o_req_co,
o_adrs_co,
i_ack_co,
o_len_co,
i_strr_co,
i_dbr_co
);
`include "polyphony_params.v"
////////////////////////////
// Localparam definition
////////////////////////////
localparam P_MAIN_IDLE = 3'd0;
localparam P_MAIN_TAG_CHECK = 3'd1;
localparam P_MAIN_CACHE_READ0 = 3'd2;
localparam P_MAIN_CACHE_READ1 = 3'd3;
localparam P_MAIN_CACHE_READ2 = 3'd4;
localparam P_MAIN_EXT_READ = 3'd5;
// external memory access
localparam P_EXT_IDLE = 2'd0;
localparam P_EXT_RREQ = 2'd1;
localparam P_EXT_RDATA = 2'd2;
localparam P_MAX_BURST_LEN = 1 << P_IB_CACHE_LINE_WIDTH;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// system configuration
input i_cache_init;
// cache in
input i_req_ci;
input [P_IB_ADDR_WIDTH-1:0]
i_adrs_ci;
output o_ack_ci;
input [P_IB_LEN_WIDTH-1:0]
i_len_ci;
output o_strr_ci;
output [P_IB_DATA_WIDTH-1:0]
o_dbr_ci;
// cache tag
output o_tw_valid;
output [P_IB_ADDR_WIDTH-1:0]
o_cmp_adrs_pre;
output [P_IB_ADDR_WIDTH-1:0]
o_cmp_adrs;
output o_tag_clear;
input i_hit;
input [P_IB_CACHE_ENTRY_WIDTH-1:0]
i_entry; // 32 entries
input [P_IB_TAG_ADDR_WIDTH-1:0]
i_tag_adrs;
//cache memory
output o_we_cm;
output [P_IB_CACHE_ENTRY_WIDTH+P_IB_CACHE_LINE_WIDTH-1:0]
o_adrs_cm;
output [P_IB_BE_WIDTH-1:0]
o_be_cm;
output [P_IB_DATA_WIDTH-1:0]
o_dt_cm;
input [P_IB_DATA_WIDTH-1:0]
i_dt_cm;
// cache out
output o_req_co;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs_co;
input i_ack_co;
output [P_IB_LEN_WIDTH-1:0]
o_len_co;
input i_strr_co;
input [P_IB_DATA_WIDTH-1:0]
i_dbr_co;
//////////////////////////////////
// reg
//////////////////////////////////
reg [2:0] r_state;
reg [1:0] r_ext_state;
// save access address
reg r_len_ci;
reg [P_IB_ADDR_WIDTH-1:0]
r_adrs_ci;
reg [P_IB_CACHE_ENTRY_WIDTH-1:0]
r_entry; // 32 entries
reg [P_IB_TAG_ADDR_WIDTH-1:0]
r_tag_adrs;
reg [P_IB_CACHE_ENTRY_WIDTH+P_IB_CACHE_LINE_WIDTH-1:0]
r_adrs_cm;
reg [P_IB_LEN_WIDTH-1:0]
r_data_cnt;
//////////////////////////////////
// wire
//////////////////////////////////
wire [P_IB_CACHE_ENTRY_WIDTH+P_IB_CACHE_LINE_WIDTH-1:0]
w_adrs_cm_next;
wire w_save_adrs;
wire w_ext_rstart;
wire w_burst_read_end;
wire w_cnt_clear;
wire w_cnt_inc;
wire w_ext_read_end;
wire w_cache_adrs_init;
wire w_cache_adrs_inc;
wire w_set_entry;
wire w_ext_read_partial_end;
wire [P_IB_CACHE_LINE_WIDTH-1:0]
w_adrs_ci_p1;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_adrs_cm_next = r_adrs_cm +1'b1;
assign w_save_adrs = (r_state == P_MAIN_IDLE) & i_req_ci;
assign o_cmp_adrs_pre = i_adrs_ci;
assign o_cmp_adrs = r_adrs_ci;
assign w_cnt_clear = w_ext_rstart;
assign w_cnt_inc = i_strr_co;
assign w_cache_adrs_init = w_cnt_clear;
assign w_cache_adrs_inc = w_cnt_inc;
assign w_ext_read_end = (r_ext_state == P_EXT_RDATA)&w_burst_read_end;
assign w_set_entry = (r_state == P_MAIN_TAG_CHECK);
assign o_tw_valid = (r_state == P_MAIN_TAG_CHECK);
assign o_ack_ci = (r_state == P_MAIN_IDLE);
assign o_strr_ci = (r_state == P_MAIN_CACHE_READ1) |
(r_state == P_MAIN_CACHE_READ2) |
((r_state == P_MAIN_EXT_READ)& w_ext_read_partial_end);
assign o_dbr_ci = ((r_state == P_MAIN_CACHE_READ1) |
(r_state == P_MAIN_CACHE_READ2)) ? i_dt_cm : i_dbr_co;
assign o_tag_clear = i_cache_init;
assign o_we_cm = ((r_state == P_MAIN_EXT_READ)&i_strr_co);
// assign o_adrs_cm =
// (r_state == P_MAIN_CACHE_READ0) ? {r_entry,r_adrs_ci[3:0]}:
// (r_state == P_MAIN_CACHE_READ1) ? {r_entry,r_adrs_ci[3:0]+ 1'b1}:
// r_adrs_cm;
assign w_adrs_ci_p1 = r_adrs_ci[P_IB_CACHE_LINE_WIDTH-1:0]+ 1'b1;
assign o_adrs_cm = (r_state == P_MAIN_TAG_CHECK) ? {i_entry,r_adrs_ci[P_IB_CACHE_LINE_WIDTH-1:0]}: // pre address for read
(r_state == P_MAIN_CACHE_READ0) ? {r_entry,r_adrs_ci[P_IB_CACHE_LINE_WIDTH-1:0]}:
(r_state == P_MAIN_CACHE_READ1) ? {r_entry,w_adrs_ci_p1}:
r_adrs_cm;
assign o_be_cm = {P_IB_BE_WIDTH{1'b1}};
assign o_dt_cm = i_dbr_co;
assign w_ext_rstart = ((r_state == P_MAIN_TAG_CHECK) & !i_hit);
assign w_burst_read_end = (r_data_cnt == (P_MAX_BURST_LEN-1)) & i_strr_co;
// external memory access
assign o_req_co = (r_ext_state == P_EXT_RREQ);
assign o_adrs_co = {r_adrs_ci[P_IB_ADDR_WIDTH-1:P_IB_CACHE_LINE_WIDTH],
{P_IB_CACHE_LINE_WIDTH{1'b0}}};
assign o_len_co = 6'h10;
assign w_ext_read_partial_end = ((r_data_cnt == r_adrs_ci[P_IB_CACHE_LINE_WIDTH-1:0])|
(r_data_cnt == w_adrs_ci_p1) & r_len_ci) & i_strr_co; // 2010/2/21
//////////////////////////////////
// always
//////////////////////////////////
// main state
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_MAIN_IDLE;
end else begin
case(r_state)
P_MAIN_IDLE: begin
if (i_req_ci) r_state <= P_MAIN_TAG_CHECK;
end
P_MAIN_TAG_CHECK: begin
if (i_hit) begin
// cache hit
r_state <= P_MAIN_CACHE_READ1;
end else begin
// cache miss hit
r_state <= P_MAIN_EXT_READ;
end
end
P_MAIN_CACHE_READ0: begin
r_state <= P_MAIN_CACHE_READ1;
end
P_MAIN_CACHE_READ1: begin
if (r_len_ci) r_state <= P_MAIN_CACHE_READ2;
else r_state <= P_MAIN_IDLE;
end
P_MAIN_CACHE_READ2: begin
r_state <= P_MAIN_IDLE;
end
P_MAIN_EXT_READ: begin
// read until getting all read data
if (w_ext_read_end) begin
r_state <= P_MAIN_IDLE; // read data is returned on-the-fly
//r_state <= P_MAIN_CACHE_READ0;
end
end
endcase
end
end
// external memory access
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_ext_state <= P_EXT_IDLE;
end else begin
case(r_ext_state)
P_EXT_IDLE: begin
if (w_ext_rstart) r_ext_state <= P_EXT_RREQ;
end
P_EXT_RREQ: begin
if (i_ack_co) r_ext_state <= P_EXT_RDATA;
end
P_EXT_RDATA: begin
if (w_burst_read_end) r_ext_state <= P_EXT_IDLE;
end
endcase
end
end
// read data counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_data_cnt <= {P_IB_LEN_WIDTH{1'b0}};
end else begin
if (w_cnt_clear) r_data_cnt <= {P_IB_LEN_WIDTH{1'b0}};
else if (w_cnt_inc) r_data_cnt <= r_data_cnt + 1'b1;
end
end
always @(posedge clk_core) begin
if (w_set_entry) begin
r_entry <= i_entry;
r_tag_adrs <= i_tag_adrs;
end
end
always @(posedge clk_core) begin
if (w_cache_adrs_init) r_adrs_cm <= {i_entry,{P_IB_CACHE_LINE_WIDTH{1'b0}}};
else if (w_cache_adrs_inc) r_adrs_cm <= w_adrs_cm_next;
end
always @(posedge clk_core) begin
if (w_save_adrs) begin
r_adrs_ci <= i_adrs_ci;
r_len_ci <= i_len_ci[1];
end
end
endmodule
|
module fm_3d_f22_to_z (
i_a,
o_b
);
///////////////////////////////////////////
// port definition
///////////////////////////////////////////
input [21:0] i_a; // input s1, e5, f1.15
output [15:0] o_b; // unsigned integer
///////////////////////////////////////////
// wire definition
///////////////////////////////////////////
// intermidiate wire
wire [4:0] w_exp;
wire [15:0] w_fraction;
///////////////////////////////////////////
// assign statement
///////////////////////////////////////////
assign w_exp = i_a[20:16];
assign w_fraction = i_a[15:0];
assign o_b = f_ftoi(w_exp, w_fraction);
///////////////////////////////////////////
// function statement
///////////////////////////////////////////
function [15:0] f_ftoi;
input [4:0] exp;
input [15:0] frac;
begin
if (&exp[4:3]) begin // over value
f_ftoi = 16'hffff;
end else begin
case (exp[4:0])
5'h7: f_ftoi = {15'b0,frac[15]}; // bias 0
5'h8: f_ftoi = {14'b0,frac[15:14]};
5'h9: f_ftoi = {13'b0,frac[15:13]};
5'ha: f_ftoi = {12'b0,frac[15:12]};
5'hb: f_ftoi = {11'b0,frac[15:11]};
5'hc: f_ftoi = {10'b0,frac[15:10]};
5'hd: f_ftoi = {9'b0,frac[15:9]};
5'he: f_ftoi = {8'b0,frac[15:8]};
5'hf: f_ftoi = {7'b0,frac[15:7]};
5'h10: f_ftoi = {6'b0,frac[15:6]};
5'h11: f_ftoi = {5'b0,frac[15:5]};
5'h12: f_ftoi = {4'b0,frac[15:4]};
5'h13: f_ftoi = {3'b0,frac[15:3]};
5'h14: f_ftoi = {2'b0,frac[15:2]};
5'h15: f_ftoi = {1'b0,frac[15:1]};
5'h16: f_ftoi = frac[15:0];
5'h17: f_ftoi = 16'hffff;
default: f_ftoi = 16'h0;
endcase
end
end
endfunction
endmodule
|
module fm_3d_color_blend (
clk_core,
rst_x,
// register configuration
i_color_mode,
i_color_blend_en,
i_color_blend_eq,
i_color_blend_sr,
i_color_blend_sd,
// source input
i_src_valid,
i_sr,
i_sg,
i_sb,
i_sa,
// destination input
i_dst_valid,
i_dst,
// blend out
o_valid,
o_fr,
o_fg,
o_fb,
o_fa
);
////////////////////////////
// Parameter definition
////////////////////////////
// main state
parameter P_IDLE = 3'd0;
parameter P_GEN_SRC = 3'd1;
parameter P_WAIT_DST = 3'd2;
parameter P_GEN_DST = 3'd3;
parameter P_EQ = 3'd4;
parameter P_OUT = 3'd5;
// sub state
parameter P_CR = 2'd0;
parameter P_CG = 2'd1;
parameter P_CB = 2'd2;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// register configuration
input [1:0] i_color_mode;
input i_color_blend_en;
input [2:0] i_color_blend_eq;
input [3:0] i_color_blend_sr;
input [3:0] i_color_blend_sd;
// source input
input i_src_valid;
input [7:0] i_sr;
input [7:0] i_sg;
input [7:0] i_sb;
input [7:0] i_sa;
// destination input
input i_dst_valid;
input [15:0] i_dst;
// blend out
output o_valid;
output [7:0] o_fr;
output [7:0] o_fg;
output [7:0] o_fb;
output [7:0] o_fa;
////////////////////////////
// reg
////////////////////////////
reg [2:0] r_state;
reg [1:0] r_sub_state;
reg [7:0] r_sr; // src or result
reg [7:0] r_sg;
reg [7:0] r_sb;
reg [7:0] r_dr; // src or result
reg [7:0] r_dg;
reg [7:0] r_db;
reg [15:0] r_dst;
reg r_dst_ready;
reg [7:0] r_isr;
reg [7:0] r_isg;
reg [7:0] r_isb;
reg [7:0] r_isa;
////////////////////////////
// wire
////////////////////////////
wire w_set_sr;
wire w_set_sg;
wire w_set_sb;
wire w_set_dr;
wire w_set_dg;
wire w_set_db;
wire [7:0] w_ia;
wire [7:0] w_a_cr;
wire [7:0] w_a_cg;
wire [7:0] w_a_cb;
wire [7:0] w_b_cr;
wire [7:0] w_b_cg;
wire [7:0] w_b_cb;
wire [7:0] w_a;
wire [7:0] w_b;
wire [7:0] w_c;
wire [7:0] w_dr;
wire [7:0] w_dg;
wire [7:0] w_db;
wire [8:0] w_fr;
wire [8:0] w_fg;
wire [8:0] w_fb;
wire [7:0] w_ffr;
wire [7:0] w_ffg;
wire [7:0] w_ffb;
wire w_start;
wire w_sub_start;
wire w_ready_clear;
wire w_ready_set;
wire w_finish_src;
wire w_finish_dst;
////////////////////////////
// assign
////////////////////////////
assign o_valid = (r_state == P_OUT);
assign w_dr = f_get_color_r(r_dst,i_color_mode);
assign w_dg = f_get_color_g(r_dst,i_color_mode);
assign w_db = f_get_color_b(r_dst,i_color_mode);
assign w_ia = ~r_isa;
assign w_a_cr = (r_state == P_GEN_SRC) ? r_isr : w_dr;
assign w_a_cg = (r_state == P_GEN_SRC) ? r_isg : w_dg;
assign w_a_cb = (r_state == P_GEN_SRC) ? r_isb : w_db;
assign w_b_cr = (r_state == P_GEN_SRC) ? r_isa : w_ia;
assign w_b_cg = (r_state == P_GEN_SRC) ? r_isa : w_ia;
assign w_b_cb = (r_state == P_GEN_SRC) ? r_isa : w_ia;
assign w_a = (r_sub_state == P_CG) ? w_a_cg:
(r_sub_state == P_CB) ? w_a_cb:
w_a_cr;
assign w_b = (r_sub_state == P_CG) ? w_b_cg:
(r_sub_state == P_CB) ? w_b_cb:
w_b_cr;
assign w_set_sr = (r_state == P_GEN_SRC) & (r_sub_state == P_CR);
assign w_set_sg = (r_state == P_GEN_SRC) & (r_sub_state == P_CG);
assign w_set_sb = (r_state == P_GEN_SRC) & (r_sub_state == P_CB);
assign w_set_dr = (r_state == P_GEN_DST) & (r_sub_state == P_CR);
assign w_set_dg = (r_state == P_GEN_DST) & (r_sub_state == P_CG);
assign w_set_db = (r_state == P_GEN_DST) & (r_sub_state == P_CB);
assign w_finish_src = w_set_sb;
assign w_finish_dst = w_set_db;
assign w_fr = r_sr + r_dr;
assign w_fg = r_sg + r_dg;
assign w_fb = r_sb + r_db;
assign w_ffr = {8{w_fr[8]}} | w_fr[7:0];
assign w_ffg = {8{w_fg[8]}} | w_fg[7:0];
assign w_ffb = {8{w_fb[8]}} | w_fb[7:0];
assign o_fr = w_ffr;
assign o_fg = w_ffg;
assign o_fb = w_ffb;
assign o_fa = i_sa;
assign w_start = i_color_blend_en & i_src_valid;
assign w_sub_start = ((r_state == P_GEN_SRC) & (r_sub_state == P_CR)) |
((r_state == P_GEN_DST) & (r_sub_state == P_CR));
assign w_ready_clear = (r_state == P_OUT);
assign w_ready_set = i_dst_valid;
////////////////////////////
// always
////////////////////////////
// main sequence
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE:begin
if (w_start) r_state <= P_GEN_SRC;
end
P_GEN_SRC:begin
if (w_finish_src) begin
if (r_dst_ready) r_state <= P_GEN_DST;
else r_state <= P_WAIT_DST;
end
end
P_WAIT_DST:begin
if (r_dst_ready) r_state <= P_GEN_DST;
end
P_GEN_DST:begin
if (w_finish_dst) begin
r_state <= P_EQ;
end
end
P_EQ:begin
r_state <= P_OUT;
end
P_OUT:begin
r_state <= P_IDLE;
end
endcase
end
end
// main sequence
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_sub_state <= P_CR;
end else begin
case (r_sub_state)
P_CR:begin
if (w_sub_start) r_sub_state <= P_CG;
end
P_CG:begin
r_sub_state <= P_CB;
end
P_CB:begin
r_sub_state <= P_CR;
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_dst_ready <= 1'b0;
end else begin
if (w_ready_clear) r_dst_ready <= 1'b0;
else if (w_ready_set) r_dst_ready <= 1'b1;
end
end
always @(posedge clk_core) begin
if (i_dst_valid) r_dst <= i_dst;
end
always @(posedge clk_core) begin
r_isr <= i_sr;
r_isg <= i_sg;
r_isb <= i_sb;
r_isa <= i_sa;
end
always @(posedge clk_core) begin
if (w_set_sr) r_sr <= w_c;
if (w_set_sg) r_sg <= w_c;
if (w_set_sb) r_sb <= w_c;
if (w_set_dr) r_dr <= w_c;
if (w_set_dg) r_dg <= w_c;
if (w_set_db) r_db <= w_c;
end
////////////////////////////
// function
////////////////////////////
function [7:0] f_get_color_r;
input [15:0] dbr;
input [2:0] mode;
begin
case (mode)
2'b00 : begin
// R5G6B5
f_get_color_r = {dbr[15:11],dbr[15:13]};
end
2'b01 : begin
// R5G5B5A1
f_get_color_r = {dbr[15:11],dbr[15:13]};
end
2'b10 : begin
// R4G4B4A4
f_get_color_r = {dbr[15:12],dbr[15:12]};
end
default : begin
f_get_color_r = {dbr[15:12],dbr[15:12]};
end
endcase
end
endfunction
function [7:0] f_get_color_g;
input [15:0] dbr;
input [2:0] mode;
begin
case (mode)
2'b00 : begin
// R5G6B5
f_get_color_g = {dbr[10:5],dbr[10:9]};
end
2'b01 : begin
// R5G5B5A1
f_get_color_g = {dbr[10:6],dbr[10:8]};
end
2'b10 : begin
// R4G4B4A4
f_get_color_g = {dbr[11:8],dbr[11:8]};
end
default : begin
f_get_color_g = {dbr[11:8],dbr[11:8]};
end
endcase
end
endfunction
function [7:0] f_get_color_b;
input [15:0] dbr;
input [2:0] mode;
begin
case (mode)
2'b00 : begin
// R5G6B5
f_get_color_b = {dbr[4:0],dbr[4:2]};
end
2'b01 : begin
// R5G5B5A1
f_get_color_b = {dbr[5:1],dbr[5:3]};
end
2'b10 : begin
// R4G4B4A4
f_get_color_b = {dbr[7:4],dbr[7:4]};
end
default : begin
f_get_color_b = {dbr[7:4],dbr[7:4]};
end
endcase
end
endfunction
////////////////////////////
// module instance
////////////////////////////
fm_3d_imul8 imul8 (
.i_a(w_a),
.i_b(w_b),
.o_c(w_c)
);
endmodule
|
module fm_3d_ru_span_step_core (
clk_core,
rst_x,
i_en,
i_valid,
i_kind,
i_end_flag,
i_start_p,
i_end_p,
i_delta_t,
o_valid,
o_kind,
o_end_flag,
o_start_p,
o_step_p
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
input i_en;
input i_valid;
input [3:0] i_kind;
input i_end_flag;
input [21:0] i_start_p;
input [21:0] i_end_p;
input [21:0] i_delta_t;
output o_valid;
output [3:0] o_kind;
output o_end_flag;
output [21:0] o_start_p;
output [21:0] o_step_p;
////////////////////////////
// wire
////////////////////////////
wire [21:0] w_end_p;
wire [21:0] w_start_p;
wire [21:0] w_delta_p;
////////////////////////////
// assign
////////////////////////////
////////////////////////////
// module instance
////////////////////////////
// adder (end_p - start_p)
fm_3d_fadd fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_a(i_end_p),
.i_b(i_start_p),
.i_adsb(1'b1),
.o_c(w_delta_p)
);
// delta_p * delta_t (not necessary to add delay to delta_t, t is static)
fm_3d_fmul mul_delta_tp (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_delta_p),
.i_b(i_delta_t),
.o_c(o_step_p)
);
// delay adjust for o_start_p
fm_3d_delay #(22,6) delay_p (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_start_p),
.o_data(o_start_p)
);
// delay adjust for valid
fm_3d_delay #(1,6) delay_valid (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_valid),
.o_data(o_valid)
);
fm_3d_delay #(1,6) delay_end_flag (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_end_flag),
.o_data(o_end_flag)
);
fm_3d_delay #(4,6) delay_kind (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_kind),
.o_data(o_kind)
);
endmodule
|
module fm_3d_ru_span_delta (
clk_core,
rst_x,
// span parameters
i_start,
o_finish,
i_x_l,
i_x_r,
// generated parameters
o_delta_t,
o_delta_a
);
////////////////////////////
// parameter
////////////////////////////
parameter P_SETUP0 = 3'h0;
parameter P_SETUP1 = 3'h1;
parameter P_SETUP2 = 3'h2;
parameter P_SETUP3 = 3'h3;
parameter P_SETUP4 = 3'h4;
parameter P_SETUP5 = 3'h5;
parameter P_SETUP6 = 3'h6;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// span parameters
input i_start;
output o_finish;
input [20:0] i_x_l;
input [20:0] i_x_r;
// generated parameters
output [21:0] o_delta_t;
output [21:0] o_delta_a;
////////////////////////////
// reg
////////////////////////////
reg [2:0] r_state;
reg [21:0] r_delta_t;
reg r_is_delta_x_zero;
////////////////////////////
// wire
////////////////////////////
wire [21:0] w_adder_out;
wire [21:0] w_recip_out;
wire w_set_delta_t;
wire w_set_dx_zero;
wire [21:0] w_05;
wire [21:0] w_00;
wire w_is_zero;
////////////////////////////
// assign
////////////////////////////
assign w_05 = 22'he8000;
assign w_00 = 22'h00000;
assign w_set_dx_zero = (r_state == P_SETUP3);
assign w_is_zero = (w_adder_out == w_00); // compare delta_x and zero
assign w_set_delta_t = (r_state == P_SETUP5);
// port connection
assign o_delta_t = r_delta_t;
assign o_delta_a = (r_is_delta_x_zero) ? w_00 : w_05;
assign o_finish = (r_state == P_SETUP6);
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_SETUP0;
end else begin
case (r_state)
P_SETUP0: if (i_start) r_state <= P_SETUP1;
P_SETUP1: r_state <= P_SETUP2;
P_SETUP2: r_state <= P_SETUP3;
P_SETUP3: r_state <= P_SETUP4;
P_SETUP4: r_state <= P_SETUP5;
P_SETUP5: r_state <= P_SETUP6;
P_SETUP6: r_state <= P_SETUP0; // delta_t register store cycle
endcase
end
end
always @(posedge clk_core) begin
if (w_set_delta_t) r_delta_t <= w_recip_out;
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_is_delta_x_zero <= 1'b0;
end else begin
if (w_set_dx_zero) r_is_delta_x_zero <= w_is_zero;
end
end
////////////////////////////
// module instance
////////////////////////////
// adder
fm_3d_fadd fadd (
.clk_core(clk_core),
.i_en(1'b1),
.i_a({1'b0,i_x_r}),
.i_b({1'b0,i_x_l}),
.i_adsb(1'b1),
.o_c(w_adder_out)
);
// 1/x
fm_3d_frcp frcp (
.clk_core(clk_core),
.i_en(1'b1),
.i_a(w_adder_out),
.o_c(w_recip_out)
);
endmodule
|
module fm_3d_vtx_fifo (
clk_core,
rst_x,
i_wstrobe,
i_dt,
o_full,
i_renable,
o_dt,
o_empty,
o_dnum, // 32bit data size
// 32bit discard flag
i_req,
i_len,
i_discard
);
// set default parameters
parameter P_RANGE = 8;
parameter P_DEPTH = 1 << P_RANGE;
`include "polyphony_params.v"
localparam P_IN_WIDTH = 64;
localparam P_OUT_WIDTH = 32;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core; // system clock
input rst_x; // system reset
input i_wstrobe; // write strobe
input [P_IN_WIDTH-1:0] i_dt; // write data
output o_full; // write data full
input i_renable; // read enable
output [P_OUT_WIDTH-1:0] o_dt; // read data
output o_empty; // read data empty
output [P_RANGE:0] o_dnum; // written data number
// 32bit discard flag
input i_req;
input [P_IB_LEN_WIDTH-1:0] i_len;
input i_discard;
/////////////////////////
// Register definition
/////////////////////////
reg [P_RANGE-1:0] r_write_counter;
reg [P_RANGE-1:0] r_read_counter;
reg [P_RANGE:0] r_status;
reg r_sel;
// read data counter
reg [P_IB_LEN_WIDTH-1:0] r_read_cnt;
reg r_read_lsb;
/////////////////////////
// wire definition
/////////////////////////
wire o_full;
wire [P_OUT_WIDTH-1:0] o_dt;
wire [P_IN_WIDTH-1:0] w_dto;
wire [P_IN_WIDTH-1:0] w_dto_th;
wire [1:0] w_status;
wire w_we;
wire w_re;
wire [P_RANGE-1:0] w_read_counter_inc;
wire [P_RANGE-1:0] w_read_counter;
wire w_discard_full;
wire w_discard_ren;
wire [P_IB_LEN_WIDTH:0] w_discard_dt;
wire w_discard_empty;
wire [4:0] w_discard_dnum;
wire w_read_end;
wire [P_IB_LEN_WIDTH-1:0] w_discard_len;
wire w_discard_flag;
wire w_ren64;
wire [63:0] w_dt64;
/////////////////////////
// assign statement
/////////////////////////
assign {w_discard_flag,w_discard_len} = w_discard_dt;
assign w_ren64 = (r_read_lsb & w_re) | w_discard_ren;
assign w_discard_ren = (r_read_cnt == w_discard_len) & w_re &
((!r_read_lsb & w_discard_flag) | (r_read_lsb & !w_discard_flag));
assign w_read_end = w_discard_ren;
assign o_full = (r_status == P_DEPTH) | w_discard_full;
assign o_empty = (r_status == 0);
assign o_dnum = {r_status,1'b0}; // x2
assign w_dt64 = (r_sel) ? w_dto_th : w_dto;
assign o_dt = (r_read_lsb) ? w_dt64[63:32] : w_dt64[31:0];
assign w_read_counter_inc = r_read_counter + 1'b1;
assign w_read_counter = (w_ren64) ? w_read_counter_inc : r_read_counter;
assign w_we = !o_full & i_wstrobe;
assign w_re = i_renable & !o_empty;
assign w_status = {w_ren64,w_we};
////////////////////////
// always statement
///////////////////////
// write side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_write_counter <= 'd0;
end else begin
if (w_we) begin
r_write_counter <= r_write_counter + 1'b1;
end
end
end
// read side
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_read_counter <= 'd0;
end else begin
if (w_ren64) begin
r_read_counter <= w_read_counter_inc;
end
end
end
// ram output select
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_sel <= 1'b0;
end else begin
r_sel <= (r_write_counter == w_read_counter) ? 1'b1 : 1'b0;
end
end
// status counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_status <= 'd0;
end else begin
case (w_status)
2'b01: r_status <= r_status + 1'b1; // write
2'b10: r_status <= r_status - 1'b1; // read
default: r_status <= r_status; // nothing to do
endcase
end
end
// read data counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_read_lsb <= 1'b0;
end else begin
if (w_read_end)r_read_lsb <= 1'b0;
else if (w_re) r_read_lsb <= ~r_read_lsb;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_read_cnt <= 1;
end else begin
if (w_read_end) begin
r_read_cnt <= 1;
end else if (w_ren64) begin
r_read_cnt <= r_read_cnt + 1'b1;
end
end
end
///////////////////
// module instance
///////////////////
fm_cmn_bram_01 #(P_IN_WIDTH, P_RANGE) bram_00 (
.clk(clk_core),
.we(w_we),
.a(r_write_counter),
.dpra(w_read_counter),
.di(i_dt),
.spo(w_dto_th),
.dpo(w_dto)
);
// discard fifo
fm_fifo #((P_IB_LEN_WIDTH+1),4) u_discard_fifo (
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(i_req),
.i_dt({i_discard,i_len}),
.o_full(w_discard_full),
.i_renable(w_discard_ren),
.o_dt(w_discard_dt),
.o_empty(w_discard_empty),
.o_dnum(w_discard_dnum)
);
endmodule
|
module fm_3d_delay_r (
clk_core,
rst_x,
i_en,
i_data,
o_data
);
////////////////////////////
// parameter
////////////////////////////
parameter P_WIDTH = 8;
parameter P_NUM_DELAY = 8;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
input i_en;
input [P_WIDTH-1:0] i_data;
output [P_WIDTH-1:0] o_data;
////////////////////////////
// reg
////////////////////////////
reg [P_WIDTH-1:0] r_delay[0:P_NUM_DELAY-1];
////////////////////////////
// assign
////////////////////////////
// in/out port connection
assign o_data = r_delay[P_NUM_DELAY-1];
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core) begin
if (i_en) r_delay[0] <= i_data;
end
// delay register connection
integer i;
always @(posedge clk_core or negedge rst_x) begin
if (!rst_x) begin
if ( P_NUM_DELAY > 1 ) begin
for ( i = 1; i < P_NUM_DELAY; i = i + 1) begin
r_delay[i] <= 0;
end
end
end else begin
if ( P_NUM_DELAY > 1 ) begin
for ( i = 1; i < P_NUM_DELAY; i = i + 1) begin
if (i_en) r_delay[i] <= r_delay[i-1];
end
end
end
end
endmodule
|
module fm_3d_cu_bselect (
clk_core,
rst_x,
// system bus
i_req_sys,
i_wr_sys,
i_adrs_sys,
o_ack_sys,
i_be_sys,
i_dbw_sys,
o_strr_sys,
o_dbr_sys,
// DMA bus
i_req_dma,
i_adrs_dma,
i_dbw_dma,
// internal bus side
o_req,
o_wr,
o_adrs,
i_ack,
o_be,
o_dbw,
i_strr,
i_dbr
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// system bus
input i_req_sys;
input i_wr_sys;
input [21:0] i_adrs_sys;
output o_ack_sys;
input [3:0] i_be_sys;
input [31:0] i_dbw_sys;
output o_strr_sys;
output [31:0] o_dbr_sys;
// DMA bus
input i_req_dma;
input [21:0] i_adrs_dma;
input [31:0] i_dbw_dma;
// internal bus side
output o_req;
output o_wr;
output [21:0] o_adrs;
input i_ack;
output [3:0] o_be;
output [31:0] o_dbw;
input i_strr;
input [31:0] i_dbr;
/////////////////////////
// register definition
/////////////////////////
reg r_req_sys;
reg r_wr_sys;
reg [21:0] r_adrs_sys;
reg [3:0] r_be_sys;
reg [31:0] r_dbw_sys;
// DMA bus
reg r_req_dma;
reg [21:0] r_adrs_dma;
reg [31:0] r_dbw_dma;
/////////////////////////
// wire definition
/////////////////////////
wire w_ack;
/////////////////////////
// assign statement
/////////////////////////
assign o_req = r_req_sys | r_req_dma;
assign o_wr = (r_req_dma) ? 1'b1 : r_wr_sys;
assign o_adrs = (r_req_dma) ? r_adrs_dma : r_adrs_sys;
assign o_be = (r_req_dma) ? 4'hf : r_be_sys;
assign o_dbw = (r_req_dma) ? r_dbw_dma : r_dbw_sys;
assign o_strr_sys = i_strr;
assign o_dbr_sys = i_dbr;
assign w_ack = (r_req_dma) ? 1'b0 : i_ack;
assign o_ack_sys = w_ack;
/////////////////////////
// always statement
/////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_req_sys <= 1'b0;
r_req_dma <= 1'b0;
end else begin
if (w_ack) r_req_sys <= 1'b0;
else r_req_sys <= i_req_sys;
r_req_dma <= i_req_dma;
end
end
always @(posedge clk_core) begin
r_wr_sys <= i_wr_sys;
r_adrs_sys <= i_adrs_sys;
r_be_sys <= i_be_sys;
r_dbw_sys <= i_dbw_sys;
r_adrs_dma <= i_adrs_dma;
r_dbw_dma <= i_dbw_dma;
end
endmodule
|
module fm_3d_tu_etc_rom (
clk_core,
i_a,
o_c
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input [4:0] i_a; // table 3bits, index 2bits
output [8:0] o_c;
////////////////////////////
// reg
////////////////////////////
reg [8:0] r_c;
////////////////////////////
// assign
////////////////////////////
assign o_c = r_c;
///////////////////////////////////////////
// always statement
///////////////////////////////////////////
always @(posedge clk_core) begin
case (i_a)
5'b000_00: r_c <= 9'h002; // table0, index0 = 2
5'b000_01: r_c <= 9'h008; // table0, index1 = 8
5'b000_10: r_c <= 9'h1fe; // table0, index2 = -2
5'b000_11: r_c <= 9'h1f8; // table0, index3 = -8
5'b001_00: r_c <= 9'h005; // table1, index0 = 5
5'b001_01: r_c <= 9'h011; // table1, index1 = 17
5'b001_10: r_c <= 9'h1fb; // table1, index2 = -5
5'b001_11: r_c <= 9'h1ef; // table1, index3 = -17
5'b010_00: r_c <= 9'h009; // table2, index0 = 9
5'b010_01: r_c <= 9'h01d; // table2, index1 = 29
5'b010_10: r_c <= 9'h1f7; // table2, index2 = -9
5'b010_11: r_c <= 9'h1e3; // table2, index3 = -29
5'b011_00: r_c <= 9'h00d; // table3, index0 = 13
5'b011_01: r_c <= 9'h02a; // table3, index1 = 42
5'b011_10: r_c <= 9'h1f3; // table3, index2 = -13
5'b011_11: r_c <= 9'h1d6; // table3, index3 = -42
5'b100_00: r_c <= 9'h012; // table4, index0 = 18
5'b100_01: r_c <= 9'h03c; // table4, index1 = 60
5'b100_10: r_c <= 9'h1ee; // table4, index2 = -18
5'b100_11: r_c <= 9'h1c4; // table4, index3 = -60
5'b101_00: r_c <= 9'h018; // table5, index0 = 24
5'b101_01: r_c <= 9'h050; // table5, index1 = 80
5'b101_10: r_c <= 9'h1e8; // table5, index2 = -24
5'b101_11: r_c <= 9'h1b0; // table5, index3 = -80
5'b110_00: r_c <= 9'h021; // table6, index0 = 33
5'b110_01: r_c <= 9'h06a; // table6, index1 = 106
5'b110_10: r_c <= 9'h1df; // table6, index2 = -33
5'b110_11: r_c <= 9'h196; // table6, index3 = -106
5'b111_00: r_c <= 9'h02f; // table7, index0 = 47
5'b111_01: r_c <= 9'h0b7; // table7, index1 = 183
5'b111_10: r_c <= 9'h1d1; // table7, index2 = -47
5'b111_11: r_c <= 9'h149; // table7, index3 = -183
default: r_c <= 9'h000;
endcase
end
endmodule
|
module fm_3d_ru_outline_setup (
clk_core,
rst_x,
// control registers
i_aa_en,
// triangle data
i_valid,
o_ack,
i_vtx0_x,
i_vtx0_y,
i_vtx1_x,
i_vtx1_y,
i_vtx2_x,
i_vtx2_y,
// parameter out
o_valid,
o_is_first,
o_is_second,
o_aa_mode,
// idle state indicator
o_idle,
// edge0
o_start_x_e0,
o_start_x_05_e0,
o_start_y_e0,
o_end_y_e0,
o_delta_e0,
o_delta_t_e0,
o_delta_a_e0,
// edge1
o_start_x_e1,
o_start_x_05_e1,
o_start_y_e1,
o_end_y_e1,
o_delta_e1,
o_delta_t_e1,
o_delta_a_e1,
// edge2
o_start_x_e2,
o_start_x_05_e2,
o_start_y_e2,
o_end_y_e2,
o_delta_e2,
o_delta_t_e2,
o_delta_a_e2,
i_ack
);
////////////////////////////
// parameter
////////////////////////////
parameter P_IDLE = 3'd0;
parameter P_EDGE0 = 3'd1;
parameter P_EDGE1 = 3'd2;
parameter P_EDGE2 = 3'd3;
parameter P_PROC = 3'd4;
parameter P_PROC_AA = 3'd5;
parameter P_ACK = 3'd6;
// sub state
parameter P_SUB0 = 4'd0;
parameter P_SUB1 = 4'd1;
parameter P_SUB2 = 4'd2;
parameter P_SUB3 = 4'd3;
parameter P_SUB4 = 4'd4;
parameter P_SUB5 = 4'd5;
parameter P_SUB6 = 4'd6;
parameter P_SUB7 = 4'd7;
parameter P_SUB8 = 4'd8;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// control registers
input i_aa_en;
// triangle data
input i_valid;
output o_ack;
input [20:0] i_vtx0_x; // x,y = positice in viewport
input [20:0] i_vtx0_y;
input [20:0] i_vtx1_x;
input [20:0] i_vtx1_y;
input [20:0] i_vtx2_x;
input [20:0] i_vtx2_y;
// parameter out
output o_is_first;
output o_is_second;
output o_valid;
output o_aa_mode;
// idle state indicator
output o_idle;
// edge0
output [20:0] o_start_x_e0;
output [20:0] o_start_x_05_e0;
output [20:0] o_start_y_e0;
output [20:0] o_end_y_e0;
output [21:0] o_delta_e0;
output [21:0] o_delta_t_e0;
output [21:0] o_delta_a_e0;
// edge1
output [20:0] o_start_x_e1;
output [20:0] o_start_x_05_e1;
output [20:0] o_start_y_e1;
output [20:0] o_end_y_e1;
output [21:0] o_delta_e1;
output [21:0] o_delta_t_e1;
output [21:0] o_delta_a_e1;
// edge2
output [20:0] o_start_x_e2;
output [20:0] o_start_x_05_e2;
output [20:0] o_start_y_e2;
output [20:0] o_end_y_e2;
output [21:0] o_delta_e2;
output [21:0] o_delta_t_e2;
output [21:0] o_delta_a_e2;
input i_ack;
////////////////////////////
// reg
////////////////////////////
reg [2:0] r_state;
reg [3:0] r_sub_state;
reg [20:0] r_delta_y;
reg [21:0] r_delta_e0;
reg [21:0] r_delta_e1;
reg [21:0] r_delta_e2;
reg [21:0] r_delta_t_e0;
reg [21:0] r_delta_t_e1;
reg [21:0] r_delta_t_e2;
reg [20:0] r_end_y_e0;
reg [20:0] r_end_y_e1;
reg [20:0] r_end_y_e2;
reg r_is_delta_y_zero_e0;
reg r_is_delta_y_zero_e1;
reg r_is_delta_y_zero_e2;
reg [20:0] r_start_x_05_vtx1;
reg [20:0] r_start_x_05_vtx2;
////////////////////////////
// wire
////////////////////////////
wire [21:0] w_adder_in_a;
wire [21:0] w_adder_in_b;
wire [21:0] w_adder_out;
wire [20:0] w_adder_out_clamped;
wire [21:0] w_recip_out;
wire [21:0] w_mul_out;
wire w_set_delta_y;
wire w_set_delta_e0;
wire w_set_delta_e1;
wire w_set_delta_e2;
wire w_set_delta_t_e0;
wire w_set_delta_t_e1;
wire w_set_delta_t_e2;
wire w_set_end_y_e0;
wire w_set_end_y_e1;
wire w_set_end_y_e2;
wire w_sub_start;
wire [21:0] w_in_a_e0;
wire [21:0] w_in_b_e0;
wire [21:0] w_in_a_e1;
wire [21:0] w_in_b_e1;
wire [21:0] w_in_a_e2;
wire [21:0] w_in_b_e2;
wire [21:0] w_10;
wire [21:0] w_05;
wire [21:0] w_00;
wire w_is_zero;
wire w_set_dy_zero_e0;
wire w_set_dy_zero_e1;
wire w_set_dy_zero_e2;
wire w_set_x_05_vtx1;
wire w_set_x_05_vtx2;
wire w_adsb;
wire w_cancel;
wire w_y_one_line;
wire w_y_two_line;
wire w_only_aa;
////////////////////////////
// assign
////////////////////////////
assign w_10 = 22'hf8000;
assign w_05 = 22'he8000;
assign w_00 = 22'h00000;
assign o_is_first = (i_vtx2_y != i_vtx1_y); // bottom != middle
assign o_is_second = (i_vtx1_y != i_vtx0_y); // midle != top
assign w_is_zero = (w_adder_out == w_00); // compare delta_y and zero
assign w_in_a_e0 = (r_sub_state == P_SUB0) ? {1'b0,i_vtx0_y} :
(r_sub_state == P_SUB2) ? {1'b0,i_vtx0_x} :
{1'b0,i_vtx0_y};
assign w_in_b_e0 = (r_sub_state == P_SUB0) ? {1'b0,i_vtx2_y} :
(r_sub_state == P_SUB2) ? {1'b0,i_vtx2_x} :
w_10;
assign w_in_a_e1 = (r_sub_state == P_SUB0) ? {1'b0,i_vtx1_y} :
(r_sub_state == P_SUB2) ? {1'b0,i_vtx1_x} :
(r_sub_state == P_SUB3) ? w_05 :
{1'b0,i_vtx1_y};
assign w_in_b_e1 = (r_sub_state == P_SUB0) ? {1'b0,i_vtx2_y} :
(r_sub_state == P_SUB2) ? {1'b0,i_vtx2_x} :
(r_sub_state == P_SUB3) ? {1'b0,i_vtx2_x} :
w_10;
assign w_in_a_e2 = (r_sub_state == P_SUB0) ? {1'b0,i_vtx0_y} :
(r_sub_state == P_SUB2) ? {1'b0,i_vtx0_x} :
(r_sub_state == P_SUB3) ? w_05 :
{1'b0,i_vtx0_y};
assign w_in_b_e2 = (r_sub_state == P_SUB0) ? {1'b0,i_vtx1_y} :
(r_sub_state == P_SUB2) ? {1'b0,i_vtx1_x} :
(r_sub_state == P_SUB3) ? {1'b0,i_vtx1_x} :
w_10;
assign w_adder_in_a = (r_state == P_EDGE0) ? w_in_a_e0 : // top - bottom
(r_state == P_EDGE1) ? w_in_a_e1 : // middle - bottom
w_in_a_e2 ; // top- middle
assign w_adder_in_b = (r_state == P_EDGE0) ? w_in_b_e0 : // top - bottom
(r_state == P_EDGE1) ? w_in_b_e1 : // middle - bottom
w_in_b_e2 ; // top- middle
assign w_set_delta_y = (r_state == P_EDGE0) & (r_sub_state == P_SUB3);
assign w_set_delta_t_e0 = (r_state == P_EDGE0) & (r_sub_state == P_SUB5);
assign w_set_delta_t_e1 = (r_state == P_EDGE1) & (r_sub_state == P_SUB5);
assign w_set_delta_t_e2 = (r_state == P_EDGE2) & (r_sub_state == P_SUB5);
assign w_set_delta_e0 = (r_state == P_EDGE0) & (r_sub_state == P_SUB8);
assign w_set_delta_e1 = (r_state == P_EDGE1) & (r_sub_state == P_SUB8);
assign w_set_delta_e2 = (r_state == P_EDGE2) & (r_sub_state == P_SUB8);
assign w_set_end_y_e0 = (r_state == P_EDGE0) & (r_sub_state == P_SUB4);
assign w_set_end_y_e1 = (r_state == P_EDGE1) & (r_sub_state == P_SUB4);
assign w_set_end_y_e2 = (r_state == P_EDGE2) & (r_sub_state == P_SUB4);
assign w_set_dy_zero_e0 = (r_state == P_EDGE0) & (r_sub_state == P_SUB3);
assign w_set_dy_zero_e1 = (r_state == P_EDGE1) & (r_sub_state == P_SUB3);
assign w_set_dy_zero_e2 = (r_state == P_EDGE2) & (r_sub_state == P_SUB3);
assign w_set_x_05_vtx2 = (r_state == P_EDGE1) & (r_sub_state == P_SUB6);
assign w_set_x_05_vtx1 = (r_state == P_EDGE2) & (r_sub_state == P_SUB6);
assign w_sub_start = (r_state == P_EDGE0) |
(r_state == P_EDGE1) |
(r_state == P_EDGE2) ;
assign w_adder_out_clamped = w_adder_out[21] ? 21'h0: w_adder_out[20:0];
assign w_adsb = !(r_sub_state == P_SUB3);
assign w_y_one_line = (r_delta_y == w_00[20:0]);
assign w_y_two_line = (r_delta_y == w_10[20:0]);
assign w_cancel = w_y_one_line | (w_y_two_line & o_is_first & !i_aa_en);
assign w_only_aa = (w_y_two_line & o_is_first & i_aa_en);
// output port
assign o_ack = (r_state == P_ACK) |
((r_state == P_EDGE0)&w_set_delta_e0&w_cancel);
assign o_delta_e0 = r_delta_e0;
assign o_delta_e1 = r_delta_e1;
assign o_delta_e2 = r_delta_e2;
assign o_delta_t_e0 = r_delta_t_e0;
assign o_delta_t_e1 = r_delta_t_e1;
assign o_delta_t_e2 = r_delta_t_e2;
assign o_start_x_e0 = i_vtx2_x;
assign o_start_x_05_e0 = r_start_x_05_vtx2;
assign o_start_y_e0 = i_vtx2_y;
assign o_end_y_e0 = r_end_y_e0;
assign o_start_x_e1 = i_vtx2_x;
assign o_start_x_05_e1 = r_start_x_05_vtx2;
assign o_start_y_e1 = i_vtx2_y;
assign o_end_y_e1 = r_end_y_e1;
assign o_start_x_e2 = i_vtx1_x;
assign o_start_x_05_e2 = r_start_x_05_vtx1;
assign o_start_y_e2 = i_vtx1_y;
assign o_end_y_e2 = r_end_y_e2;
assign o_delta_a_e0 = (r_is_delta_y_zero_e0) ? w_00 : w_05;
assign o_delta_a_e1 = (r_is_delta_y_zero_e1) ? w_00 : w_05;
assign o_delta_a_e2 = (r_is_delta_y_zero_e2) ? w_00 : w_05;
assign o_valid = (r_state == P_PROC) | (r_state == P_PROC_AA);
assign o_aa_mode = (r_state == P_PROC_AA);
assign o_idle = (r_state == P_IDLE);
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (i_valid) r_state <= P_EDGE0;
end
P_EDGE0: begin
if (w_set_delta_e0) begin
if (w_cancel) r_state <= P_IDLE;
else r_state <= P_EDGE1;
end
end
P_EDGE1: begin
if (w_set_delta_e1) r_state <= P_EDGE2;
end
P_EDGE2: begin
if (w_set_delta_e2) begin
if (w_only_aa) r_state <= P_PROC_AA;
else r_state <= P_PROC;
end
end
P_PROC: begin
if (i_ack) begin
if (i_aa_en) r_state <= P_PROC_AA;
else r_state <= P_ACK;
end
end
P_PROC_AA: begin
if (i_ack) r_state <= P_ACK;
end
P_ACK: begin
r_state <= P_IDLE;
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_sub_state <= P_SUB0;
end else begin
case (r_sub_state)
P_SUB0: if (w_sub_start) r_sub_state <= P_SUB1;
P_SUB1: r_sub_state <= P_SUB2;
P_SUB2: r_sub_state <= P_SUB3;
P_SUB3: r_sub_state <= P_SUB4;
P_SUB4: r_sub_state <= P_SUB5;
P_SUB5: r_sub_state <= P_SUB6;
P_SUB6: r_sub_state <= P_SUB7;
P_SUB7: r_sub_state <= P_SUB8;
P_SUB8: r_sub_state <= P_SUB0;
endcase
end
end
always @(posedge clk_core) begin
if (w_set_delta_e0) r_delta_e0 <= w_mul_out;
if (w_set_delta_e1) r_delta_e1 <= w_mul_out;
if (w_set_delta_e2) r_delta_e2 <= w_mul_out;
if (w_set_delta_t_e0) r_delta_t_e0 <= w_recip_out;
if (w_set_delta_t_e1) r_delta_t_e1 <= w_recip_out;
if (w_set_delta_t_e2) r_delta_t_e2 <= w_recip_out;
if (w_set_end_y_e0) r_end_y_e0 <= w_adder_out_clamped[20:0];
if (w_set_end_y_e1) r_end_y_e1 <= w_adder_out_clamped[20:0];
if (w_set_end_y_e2) r_end_y_e2 <= w_adder_out_clamped[20:0];
if (w_set_dy_zero_e0) r_is_delta_y_zero_e0 <= w_is_zero;
if (w_set_dy_zero_e1) r_is_delta_y_zero_e1 <= w_is_zero;
if (w_set_dy_zero_e2) r_is_delta_y_zero_e2 <= w_is_zero;
if (w_set_x_05_vtx1) r_start_x_05_vtx1 <= w_adder_out[20:0];
if (w_set_x_05_vtx2) r_start_x_05_vtx2 <= w_adder_out[20:0];
if (w_set_delta_y) r_delta_y <= w_adder_out[20:0];
end
////////////////////////////
// module instance
////////////////////////////
// adder in: out: recip in: out mul in: result
// 0. ey-sy
// 1. ey-1.0
// 2. ex-sx
// 3. ex+0.5 delta_y delta_y ey-sy
// 4. ey-2.0 ey-1.0 ey-1.0
// 5. delta_x 1/delta_y delta_x*delta_t delta_t(1/delta_y)
// 6. ex+0.5
// 7. ey-2.0
// 8. delta
// fadd, latency = 3
fm_3d_fadd fadd (
.clk_core(clk_core),
.i_en(1'b1),
.i_a(w_adder_in_a),
.i_b(w_adder_in_b),
.i_adsb(w_adsb),
.o_c(w_adder_out)
);
// frcp, latency = 2
fm_3d_frcp frcp (
.clk_core(clk_core),
.i_en(1'b1),
.i_a(w_adder_out),
.o_c(w_recip_out)
);
// fmul, latency = 3
fm_3d_fmul fmul (
.clk_core(clk_core),
.i_en(1'b1),
.i_a(w_adder_out),
.i_b(w_recip_out),
.o_c(w_mul_out)
);
endmodule
|
module fm_3d_fmul (
clk_core,
i_en,
i_a,
i_b,
o_c
);
///////////////////////////////////////////
// port definition
///////////////////////////////////////////
input clk_core;
input i_en;
input [21:0] i_a;
input [21:0] i_b;
output [21:0] o_c;
///////////////////////////////////////////
// register
///////////////////////////////////////////
reg [21:0] r_c;
reg r_sign_1z;
reg r_sign_2z;
reg [17:0] r_cf_tmp;
reg [4:0] r_ce_tmp_1z;
reg [4:0] r_ce_tmp_2z;
reg [16:0] r_cf_tmp2;
///////////////////////////////////////////
// wire definition
///////////////////////////////////////////
// input data separation
wire w_a_sign;
wire [15:0] w_a_fraction;
wire [4:0] w_a_exp;
wire w_b_sign;
wire [15:0] w_b_fraction;
wire [4:0] w_b_exp;
// intermidiate wire
wire [5:0] w_adder_out; // result of exp addition
wire w_sign;
wire [31:0] w_cf_tmp; // multplyer out 1.15 * 1.15 = 2.30
wire [16:0] w_cf_tmp2; // multplyer out (rounded) 2.15
wire [4:0] w_ce_tmp; // temporary exp out
wire [21:0] w_c;
///////////////////////////////////////////
// stage0
///////////////////////////////////////////
// separate input and add implied fraction msb
assign w_a_sign = i_a[21];
assign w_a_exp = i_a[20:16];
assign w_a_fraction = i_a[15:0];
assign w_b_sign = i_b[21];
assign w_b_exp = i_b[20:16];
assign w_b_fraction = i_b[15:0];
// exponent calculation
// (ea + eb - bias)
wire [5:0] w_exp_add;
assign w_exp_add = w_a_exp + w_b_exp;
assign w_adder_out = w_exp_add - 4'hf;
assign w_ce_tmp = (w_exp_add < 5'hf) ? 5'h00 :
(w_adder_out[5]) ? 5'h1f :
w_adder_out[4:0];
assign w_sign = w_a_sign ^ w_b_sign;
// fraction multiplyer
assign w_cf_tmp = w_a_fraction * w_b_fraction;
///////////////////////////////////////////
// stage1
///////////////////////////////////////////
always @(posedge clk_core) begin
if (i_en) begin
r_sign_1z <= w_sign;
r_cf_tmp <= w_cf_tmp[31:14];
r_ce_tmp_1z <= w_ce_tmp;
end
end
// round
//assign w_cf_tmp2 = w_cf_tmp[14] ? w_cf_tmp[31:15] + 1'b1 :
// w_cf_tmp[31:15];
wire [16:0] w_rounded;
assign w_rounded = r_cf_tmp[17:1] + 1'b1;
assign w_cf_tmp2 = r_cf_tmp[0] ? w_rounded : // 2.15
r_cf_tmp[17:1];
///////////////////////////////////////////
// stage2
///////////////////////////////////////////
always @(posedge clk_core) begin
if (i_en) begin
r_sign_2z <= r_sign_1z;
r_ce_tmp_2z <= r_ce_tmp_1z;
r_cf_tmp2 <= w_cf_tmp2;
end
end
// normalize
fm_3d_norm norm (
.i_s(r_sign_2z),
.i_e(r_ce_tmp_2z),
.i_f(r_cf_tmp2),
.o_b(w_c)
);
///////////////////////////////////////////
// stage3
///////////////////////////////////////////
// final register
always @(posedge clk_core) begin
if (i_en) r_c <= w_c;
end
// output port connection
assign o_c = r_c;
endmodule
|
module fm_3d_mu_priority (
clk_core,
rst_x,
// port0 side Read/Write
i_req0,
i_we0,
i_add0,
i_len0,
i_be0,
o_cack0,
i_strw0,
i_dbw0,
i_wdata_read_end0,
o_wdata_ack0,
o_strr0,
o_dbr0,
// port1 side Read/Write
i_req1,
i_we1,
i_add1,
i_len1,
i_be1,
o_cack1,
i_strw1,
i_dbw1,
i_wdata_read_end1,
o_wdata_ack1,
o_strr1,
o_dbr1,
// port2 side Read Only
i_req2,
i_add2,
i_len2,
o_cack2,
o_strr2,
o_dbr2,
// output to bus bridge
o_breq,
o_bwe,
o_badd,
o_blen,
i_back,
o_bstrw,
o_bbe,
o_bdbw,
i_backw,
i_bstrr,
i_bdbr
);
`include "polyphony_params.v"
////////////////////////////
// Localparam definition
////////////////////////////
localparam P_SIDLE = 1'b0;
localparam P_SDIN = 1'b1;
////////////////////////////
// I/O definition
////////////////////////////
// port 0
input i_req0; // command request
input i_we0; // write/read flag
input [P_IB_ADDR_WIDTH-1:0]
i_add0; // address
input [P_IB_LEN_WIDTH-1:0]
i_len0; // burst length
input [P_IB_BE_WIDTH-1:0]
i_be0; // byte enable
output o_cack0; // command acknowledge
input i_strw0; // write data strobe
input [P_IB_DATA_WIDTH-1:0]
i_dbw0; // write data
input i_wdata_read_end0;
// write data end flag
output o_wdata_ack0; // write data acknowledge
output o_strr0; // read data strobe
output [P_IB_DATA_WIDTH-1:0]
o_dbr0; // read data
// port 1
input i_req1; // command request
input i_we1; // write/read flag
input [P_IB_ADDR_WIDTH-1:0]
i_add1; // address
input [P_IB_LEN_WIDTH-1:0]
i_len1; // burst length
input [P_IB_BE_WIDTH-1:0]
i_be1; // byte enable
output o_cack1; // command acknowledge
input i_strw1; // write data strobe
input [P_IB_DATA_WIDTH-1:0]
i_dbw1; // write data
input i_wdata_read_end1;
// write data end flag
output o_wdata_ack1; // write data acknowledge
output o_strr1; // read data strobe
output [P_IB_DATA_WIDTH-1:0]
o_dbr1; // read data
// port 2
input i_req2; // command request
input [P_IB_ADDR_WIDTH-1:0]
i_add2; // address
input [P_IB_LEN_WIDTH-1:0]
i_len2; // burst length
output o_cack2; // command acknowledge
output o_strr2; // read data strobe
output [P_IB_DATA_WIDTH-1:0]
o_dbr2; // read data
// output to bus bridge or
// memory bus arbiter far
output o_breq; // command request
output o_bwe; // write/read flag
output [P_IB_ADDR_WIDTH-1:0]
o_badd; // address
output [P_IB_LEN_WIDTH-1:0]
o_blen; // burst length
output [P_IB_BE_WIDTH-1:0]
o_bbe; // byte enable
input i_back; // command acknowledge
output o_bstrw; // write data strobe
output [P_IB_DATA_WIDTH-1:0]
o_bdbw; // write data
input i_backw; // write data acknowledge
input i_bstrr; // read data strobe
input [P_IB_DATA_WIDTH-1:0]
i_bdbr; // read data
input clk_core; // system clock
input rst_x; // system reset
/////////////////////////
// register definition
/////////////////////////
reg r_breq;
reg r_bwe;
reg [P_IB_ADDR_WIDTH-1:0]
r_badd;
reg [P_IB_LEN_WIDTH-1:0]
r_blen;
reg [P_IB_BE_WIDTH-1:0]
r_bbe;
reg r_back;
reg r_bstrw;
reg [P_IB_DATA_WIDTH-1:0]
r_bdbw;
reg r_backw;
reg r_bstrr;
reg [P_IB_DATA_WIDTH-1:0]
r_bdbr;
// current priority
reg [1:0] r_current_priority; // 0 - 2
// read data counter
reg [P_IB_LEN_WIDTH-1:0]
r_read_cnt;
// write data state machine
reg r_wstate;
// read data final out
reg r_strr2;
reg [P_IB_DATA_WIDTH-1:0]
r_dbr2;
/////////////////////////
// wire definition
/////////////////////////
// current port
wire w_req;
wire w_we;
wire [P_IB_ADDR_WIDTH-1:0]
w_add;
wire [P_IB_LEN_WIDTH-1:0]
w_len;
wire [P_IB_BE_WIDTH-1:0]
w_be;
wire w_strw;
wire [P_IB_DATA_WIDTH-1:0]
w_dbw;
wire w_wdata_read_end;
wire w_wdata_read;
wire w_write_burst;
wire w_wdata_idle;
wire w_rfifo_ok;
// masked back
wire w_back;
// bridge port
wire w_breq;
wire w_bstrw;
wire [2:0] w_sreq;
wire [1:0] w_decide_port;
wire w_wstate_idle;
wire w_wstate_din;
// fifo port
wire w_fifo_full;
wire [2+P_IB_LEN_WIDTH-1:0]
w_fifo_din;
wire [2+P_IB_LEN_WIDTH-1:0]
w_fifo_dout;
wire w_fifo_write;
wire [P_IB_LEN_WIDTH-1:0]
w_current_read_len;
wire [1:0] w_current_read_pr;
wire w_read_end;
wire w_set_priority;
wire [1:0] w_wdata_port;
// read data final out
wire w_strr2;
wire [P_IB_DATA_WIDTH-1:0]
w_dbr2;
/////////////////////////
// assign statement
/////////////////////////
// masked back
assign w_back = r_back;
assign w_sreq = {i_req2,i_req1,i_req0};
assign w_decide_port = f_decide_port(w_sreq,r_current_priority);
assign w_wstate_idle = (r_wstate == P_SIDLE);
assign w_wstate_din = (r_wstate == P_SDIN);
assign w_wdata_idle = (w_we) ? r_backw & w_wstate_idle : w_wstate_idle;
assign w_wdata_port = (w_wstate_idle) ? w_decide_port : r_current_priority;
assign w_wdata_read = w_wstate_din | (w_req & w_we & w_back);
assign w_rfifo_ok = (!w_we) ? !w_fifo_full : 1'b1;
// command end cycle flag
assign w_set_priority = w_req & w_back & w_wdata_idle;
// port0
assign o_cack0 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd0);
assign o_wdata_ack0 = r_backw & w_wdata_read & (w_wdata_port == 2'd0);
assign o_strr0 = r_bstrr & (w_current_read_pr == 2'd0);
assign o_dbr0 = r_bdbr;
// port1
assign o_cack1 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd1);
assign o_wdata_ack1 = r_backw & w_wdata_read & (w_wdata_port == 2'd1);
assign o_strr1 = r_bstrr & (w_current_read_pr == 3'd1);
assign o_dbr1 = r_bdbr;
// port2
assign o_cack2 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd2);
assign w_strr2 = r_bstrr & (w_current_read_pr == 2'd2);
assign w_dbr2 = r_bdbr;
assign o_strr2 = r_strr2;
assign o_dbr2 = r_dbr2;
// current port
assign w_req = (w_decide_port == 3'd0) ? i_req0 :
(w_decide_port == 3'd1) ? i_req1 : i_req2;
assign w_we = (w_decide_port == 3'd0) ? i_we0 :
(w_decide_port == 3'd1) ? i_we1 : 1'b0;
assign w_add = (w_decide_port == 3'd0) ? i_add0 :
(w_decide_port == 3'd1) ? i_add1 :i_add2;
assign w_len = (w_decide_port == 3'd0) ? i_len0 :
(w_decide_port == 3'd1) ? i_len1 : i_len2;
assign w_be = (w_wdata_port == 3'd0) ? i_be0 :
(w_wdata_port == 3'd1) ? i_be1 : 8'h00;
assign w_dbw = (w_wdata_port == 3'd0) ? i_dbw0 :
(w_wdata_port == 3'd1) ? i_dbw1 : 32'h0000_0000;
assign w_strw = (w_wdata_port == 3'd0) ? i_strw0 :
(w_wdata_port == 3'd1) ? i_strw1 : 1'b0;
assign w_wdata_read_end = (w_wdata_port == 2'd0) ? (i_wdata_read_end0 & r_backw) :
(w_wdata_port == 2'd1) ? (i_wdata_read_end1 & r_backw) : 1'b0;
assign w_write_burst = w_req & w_we & (w_len != 1) & w_back & r_backw;
// bridge port
assign w_breq = w_req & w_back & w_wdata_idle & w_rfifo_ok;
assign w_bstrw = w_strw & w_wdata_read & r_backw;
// bridge port output connection
assign o_breq = r_breq;
assign o_bwe = r_bwe;
assign o_badd = r_badd;
assign o_blen = r_blen;
assign o_bstrw = r_bstrw;
assign o_bbe = r_bbe;
assign o_bdbw = r_bdbw;
// fifo port
assign w_fifo_din = {w_decide_port,w_len};
assign w_fifo_write = w_req & w_back & !w_we & w_set_priority;
assign {w_current_read_pr,w_current_read_len} = w_fifo_dout;
assign w_read_end = (r_read_cnt == w_current_read_len) & r_bstrr;
/////////////////////////
// function statement
/////////////////////////
function [1:0] f_decide_port;
input [2:0] req;
input [1:0] cp;
begin
case (req)
3'b000: begin
// no request
f_decide_port = cp;
end
3'b001: begin
// only port0 request
f_decide_port = 2'd0;
end
3'b010: begin
// only port1 request
f_decide_port = 2'b1;
end
3'b011: begin
// simultaneous request port 1 & 0
case (cp)
2'b00 : f_decide_port = 2'd1;
default : f_decide_port = 2'd0;
endcase
end
3'b100: begin
// only port2 request
f_decide_port = 2'd2;
end
3'b101: begin
// simultaneous request port 2 & 0
case (cp)
2'b00,
2'b01 : f_decide_port = 2'd2;
default : f_decide_port = 2'd0;
endcase
end
3'b110: begin
// simultaneous request port 2 & 1
case (cp)
2'b01 : f_decide_port = 2'd2;
default : f_decide_port = 2'd1;
endcase
end
3'b111: begin
// simultaneous request port 2 & 1 & 0
case (cp)
2'b00 : f_decide_port = 2'd1;
2'b01 : f_decide_port = 2'd2;
default : f_decide_port = 2'd0;
endcase
end
default : f_decide_port = 2'd0;
endcase
// test : port2 always has top priority
if (req[2]) f_decide_port = 2'd2;
end
endfunction
/////////////////////////
// always statement
/////////////////////////
// write data state machine
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_wstate <= P_SIDLE;
end else begin
case (r_wstate)
P_SIDLE : // Idle
begin
if (w_write_burst) begin
r_wstate <= P_SDIN;
end
end
P_SDIN : // Getting write data & be
begin
if (w_wdata_read_end) begin
r_wstate <= P_SIDLE;
end
end
default : r_wstate <= r_wstate;
endcase
end
end
// current priority
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_current_priority <= 2'd1; // lowest priority port number
end else begin
if (w_set_priority) begin
r_current_priority <= w_decide_port;
end
end
end
// read data counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_read_cnt <= 1;
end else begin
if (w_read_end) begin
r_read_cnt <= 1;
end else if (r_bstrr) begin
r_read_cnt <= r_read_cnt + 1'b1;
end
end
end
// bus bridge (or memory arbiter far) port
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_breq <= 1'b0;
end else begin
r_breq <= w_breq;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bstrw <= 1'b0;
end else begin
r_bstrw <= w_bstrw;
end
end
always @(posedge clk_core) begin
r_bwe <= w_we;
r_badd <= w_add;
r_blen <= w_len;
r_bbe <= w_be;
r_bdbw <= w_dbw;
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bstrr <= 1'b0;
end else begin
r_bstrr <= i_bstrr;
end
end
always @(posedge clk_core) begin
r_bdbr <= i_bdbr;
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_back <= 1'b0;
r_backw <= 1'b0;
end else begin
r_back <= i_back;
r_backw <= i_backw;
end
end
// read data strobe & outout (Read Only Port)
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_strr2 <= 1'b0;
end else begin
r_strr2 <= w_strr2;
end
end
always @(posedge clk_core) begin
r_dbr2 <= w_dbr2;
end
/////////////////////////
// module instantiation
/////////////////////////
// read data priority fifo
// contain port number + burst length
fm_cmn_bfifo #(2+P_IB_LEN_WIDTH,7) fifo (
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(w_fifo_write),
.i_dt(w_fifo_din),
.o_full(w_fifo_full),
.i_renable(w_read_end),
.o_dt(w_fifo_dout),
.o_empty(),
.o_dnum()
);
endmodule
|
module fm_3d_ru_span_update_core (
clk_core,
rst_x,
i_en,
i_valid,
i_kind,
i_end_flag,
i_cur_p,
i_step_p,
i_delta_a,
i_aa_mode,
o_valid,
o_kind,
o_end_flag,
o_cur_p,
o_frag_p,
o_x,
o_z,
o_color
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
input i_en;
input i_valid;
input [3:0] i_kind;
input i_end_flag;
input [21:0] i_cur_p;
input [21:0] i_step_p;
input [21:0] i_delta_a;
input i_aa_mode;
output o_valid;
output [3:0] o_kind;
output o_end_flag;
output [21:0] o_cur_p;
output [21:0] o_frag_p;
output [9:0] o_x;
output [15:0] o_z;
output [7:0] o_color;
////////////////////////////
// reg
////////////////////////////
reg [21:0] r_cw;
////////////////////////////
// wire
////////////////////////////
wire [21:0] w_cw;
wire [21:0] w_recip_out;
wire w_kind_iw;
wire w_kind_x;
wire w_set_cw;
wire [21:0] w_mul_in_a;
wire [21:0] w_mul_in_b;
wire [21:0] w_10;
wire [21:0] w_mul_out;
wire [21:0] w_fadd_in_a;
wire [21:0] w_fadd_in_b;
wire [21:0] w_step_3d;
wire [21:0] w_cur_3d;
wire w_valid_3d;
wire w_end_flag_3d;
wire [3:0] w_kind_3d;
wire [15:0] w_ix;
wire [15:0] w_iz;
wire [7:0] w_color;
////////////////////////////
// assign
////////////////////////////
assign w_kind_iw = (i_kind == `FPARAM_IW);
assign w_kind_x = (i_kind == `FPARAM_X);
assign w_cw = (w_kind_iw) ? w_recip_out : r_cw;
assign w_mul_in_b = (i_aa_mode) ? i_delta_a :
(w_kind_x|w_kind_iw) ? w_10:
w_cw;
assign w_mul_in_a = (i_aa_mode) ? i_step_p : i_cur_p;
assign w_10 = {1'b0, 5'h0f, 16'h8000};
assign w_fadd_in_a = (i_aa_mode) ? w_mul_out : w_cur_3d;
assign w_fadd_in_b = (i_aa_mode) ? w_cur_3d : w_step_3d;
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core) begin
if (w_set_cw) r_cw <= w_recip_out;
end
////////////////////////////
// module instance
////////////////////////////
// cw = 1/iw (only for iw)
fm_3d_frcp frcp (
.clk_core(clk_core),
.i_en(i_en),
.i_a(i_cur_p),
.o_c(w_recip_out)
);
// delay adjust for cw register
fm_3d_delay #(1,2) delay_iw (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_kind_iw),
.o_data(w_set_cw)
);
////////////////////////////////
// stage0-2
///////////////////////////////
// current value * cw;
fm_3d_fmul mul_delta (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_mul_in_a),
.i_b(w_mul_in_b),
.o_c(w_mul_out)
);
// fmul delay adjust
fm_3d_delay #(1,3) delay_valid_fmul (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_valid),
.o_data(w_valid_3d)
);
fm_3d_delay #(1,3) delay_end_flag_fmul (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_end_flag),
.o_data(w_end_flag_3d)
);
fm_3d_delay #(4,3) delay_kind_fmul (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_kind),
.o_data(w_kind_3d)
);
fm_3d_delay #(22,3) delay_step_fmul (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_step_p),
.o_data(w_step_3d)
);
fm_3d_delay #(22,3) delay_cur_fmul (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_cur_p),
.o_data(w_cur_3d)
);
////////////////////////////////
// stage3-5
///////////////////////////////
// adder (end_p - start_p)
fm_3d_fadd fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_fadd_in_a),
.i_b(w_fadd_in_b),
.i_adsb(1'b0),
.o_c(o_cur_p)
);
// delay adjust for fragment
fm_3d_delay #(22,3) delay_frag_fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_mul_out),
.o_data(o_frag_p)
);
// delay adjust for valid
fm_3d_delay #(1,3) delay_valid_fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_valid_3d),
.o_data(o_valid)
);
fm_3d_delay #(1,3) delay_end_flag_fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_end_flag_3d),
.o_data(o_end_flag)
);
fm_3d_delay #(4,3) delay_kind_fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_kind_3d),
.o_data(o_kind)
);
// ftoi for x
fm_3d_f22_to_ui ftoi_x (
.i_a(w_mul_out),
.o_b(w_ix)
);
fm_3d_delay #(10,3) delay_x_fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_ix[9:0]),
.o_data(o_x)
);
// ftoi for z
fm_3d_f22_to_z ftoi_z (
.i_a(w_mul_out),
.o_b(w_iz)
);
fm_3d_delay #(16,3) delay_z_fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_iz),
.o_data(o_z)
);
// ftoc
fm_3d_f22_to_i8_2 ftoc (
.i_a(w_mul_out),
.o_b(w_color)
);
fm_3d_delay #(8,3) delay_col_fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_color),
.o_data(o_color)
);
endmodule
|
module fm_3d_f22_to_ui_b (
i_a,
o_b
);
///////////////////////////////////////////
// port definition
///////////////////////////////////////////
input [21:0] i_a; // input s1, e5, f1.15
output [15:0] o_b; // unsigned integer
///////////////////////////////////////////
// wire definition
///////////////////////////////////////////
// intermidiate wire
wire [4:0] w_exp;
wire [15:0] w_fraction;
///////////////////////////////////////////
// assign statement
///////////////////////////////////////////
assign w_exp = i_a[20:16];
assign w_fraction = i_a[15:0];
assign o_b = f_ftoi(w_exp, w_fraction);
///////////////////////////////////////////
// function statement
///////////////////////////////////////////
function [15:0] f_ftoi;
input [4:0] exp;
input [15:0] frac;
begin
case (exp)
5'd19: f_ftoi = {15'b0,frac[15]}; // bias 0
5'd20: f_ftoi = {14'b0,frac[15:14]};
5'd21: f_ftoi = {13'b0,frac[15:13]};
5'd22: f_ftoi = {12'b0,frac[15:12]};
5'd23: f_ftoi = {11'b0,frac[15:11]};
5'd24: f_ftoi = {10'b0,frac[15:10]};
5'd25: f_ftoi = {9'b0,frac[15:9]};
5'd26: f_ftoi = {8'b0,frac[15:8]};
5'd27: f_ftoi = {7'b0,frac[15:7]};
5'd28: f_ftoi = {6'b0,frac[15:6]};
5'd29: f_ftoi = {5'b0,frac[15:5]};
5'd30: f_ftoi = {4'b0,frac[15:4]};
5'd31: f_ftoi = {3'b0,frac[15:3]};
default: f_ftoi = 16'h0;
endcase
end
endfunction
endmodule
|
module fm_3d_ru_span_update (
clk_core,
rst_x,
// parameter input
i_start,
i_aa_mode,
i_delta_a,
o_finish,
// generated steps
i_valid_step,
i_step_kind,
i_step_val,
// control registers
i_param0_en,
i_param1_en,
i_param0_size,
i_param1_size,
// current values
i_cur_x,
i_cur_z,
i_cur_iw,
i_cur_param00,
i_cur_param01,
i_cur_param02,
i_cur_param03,
i_cur_param10,
i_cur_param11,
`ifdef VTX_PARAM1_REDUCE
`else
i_cur_param12,
i_cur_param13,
`endif
// new value
o_update_valid,
o_update_kind,
o_update_end_flag,
o_update_val,
o_update_frag,
o_update_x,
o_update_z,
o_update_color
);
////////////////////////////
// parameter
////////////////////////////
parameter P_UPDATE_IW = 4'h0;
parameter P_UPDATE_X = 4'h1;
parameter P_UPDATE_Z = 4'h2;
parameter P_UPDATE_P00 = 4'h3;
parameter P_UPDATE_P01 = 4'h4;
parameter P_UPDATE_P02 = 4'h5;
parameter P_UPDATE_P03 = 4'h6;
parameter P_UPDATE_P10 = 4'h7;
parameter P_UPDATE_P11 = 4'h8;
parameter P_UPDATE_P12 = 4'h9;
parameter P_UPDATE_P13 = 4'ha;
parameter P_UPDATE_WAIT = 4'hb;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// outline parameter input
input i_start;
output o_finish;
input i_aa_mode;
input [21:0] i_delta_a;
// generated steps
input i_valid_step;
input [3:0] i_step_kind;
input [21:0] i_step_val;
// control registers
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
// current values
input [20:0] i_cur_x;
input [20:0] i_cur_z;
input [20:0] i_cur_iw;
input [20:0] i_cur_param00;
input [20:0] i_cur_param01;
input [20:0] i_cur_param02;
input [20:0] i_cur_param03;
input [20:0] i_cur_param10;
input [20:0] i_cur_param11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_cur_param12;
input [20:0] i_cur_param13;
`endif
// new value
output o_update_valid;
output [3:0] o_update_kind;
output o_update_end_flag;
output [21:0] o_update_val;
output [21:0] o_update_frag;
output [9:0] o_update_x;
output [15:0] o_update_z;
output [7:0] o_update_color;
////////////////////////////
// reg
////////////////////////////
reg [3:0] r_state;
reg [21:0] r_step_z;
reg [21:0] r_step_iw;
reg [21:0] r_step_param00;
reg [21:0] r_step_param01;
reg [21:0] r_step_param02;
reg [21:0] r_step_param03;
reg [21:0] r_step_param10;
reg [21:0] r_step_param11;
`ifdef VTX_PARAM1_REDUCE
`else
reg [21:0] r_step_param12;
reg [21:0] r_step_param13;
`endif
////////////////////////////
// wire
////////////////////////////
wire w_valid;
wire w_end_flag;
wire w_end_flag_z;
wire w_end_flag_p00;
wire w_end_flag_p01;
wire w_end_flag_p02;
wire w_end_flag_p03;
wire w_end_flag_p10;
wire w_end_flag_p11;
`ifdef VTX_PARAM1_REDUCE
`else
wire w_end_flag_p12;
wire w_end_flag_p13;
`endif
wire [20:0] w_cur_val;
wire [21:0] w_cur_step;
wire [21:0] w_10;
wire [3:0] w_kind;
////////////////////////////
// assign
////////////////////////////
assign w_10 = {1'b0, 5'h0f, 16'h8000};
assign w_valid = (r_state != P_UPDATE_WAIT) &
((r_state != P_UPDATE_IW) |((r_state == P_UPDATE_IW)&i_start));
assign w_end_flag_z = (r_state == P_UPDATE_Z) & !i_param0_en & !i_param1_en;
assign w_end_flag_p00 = (r_state == P_UPDATE_P00) &
(i_param0_en & (i_param0_size == 2'd0)) &
!i_param1_en;
assign w_end_flag_p01 = (r_state == P_UPDATE_P01) &
(i_param0_size == 2'd1) & !i_param1_en;
assign w_end_flag_p02 = (r_state == P_UPDATE_P02) &
(i_param0_size == 2'd2) & !i_param1_en;
assign w_end_flag_p03 = (r_state == P_UPDATE_P03) & !i_param1_en;
assign w_end_flag_p10 = (r_state == P_UPDATE_P10) & (i_param1_size == 2'd0);
assign w_end_flag_p11 = (r_state == P_UPDATE_P11) & (i_param1_size == 2'd1);
`ifdef VTX_PARAM1_REDUCE
`else
assign w_end_flag_p12 = (r_state == P_UPDATE_P11) & (i_param1_size == 2'd2);
assign w_end_flag_p13 = (r_state == P_UPDATE_P11);
`endif
`ifdef VTX_PARAM1_REDUCE
assign w_end_flag = w_end_flag_z |
w_end_flag_p00 | w_end_flag_p01 | w_end_flag_p02 | w_end_flag_p03|
w_end_flag_p10 | w_end_flag_p11;
`else
assign w_end_flag = w_end_flag_z |
w_end_flag_p00 | w_end_flag_p01 | w_end_flag_p02 | w_end_flag_p03|
w_end_flag_p10 | w_end_flag_p11 | w_end_flag_p12 | w_end_flag_p03;
`endif
`ifdef VTX_PARAM1_REDUCE
assign w_cur_val =
(r_state == P_UPDATE_IW) ? i_cur_iw :
(r_state == P_UPDATE_X) ? i_cur_x :
(r_state == P_UPDATE_Z) ? i_cur_z :
(r_state == P_UPDATE_P00) ? i_cur_param00 :
(r_state == P_UPDATE_P01) ? i_cur_param01 :
(r_state == P_UPDATE_P02) ? i_cur_param02 :
(r_state == P_UPDATE_P03) ? i_cur_param03 :
(r_state == P_UPDATE_P10) ? i_cur_param10 :
i_cur_param11 ;
assign w_cur_step =
(r_state == P_UPDATE_IW) ? r_step_iw :
(r_state == P_UPDATE_X) ? w_10 :
(r_state == P_UPDATE_Z) ? r_step_z :
(r_state == P_UPDATE_P00) ? r_step_param00 :
(r_state == P_UPDATE_P01) ? r_step_param01 :
(r_state == P_UPDATE_P02) ? r_step_param02 :
(r_state == P_UPDATE_P03) ? r_step_param03 :
(r_state == P_UPDATE_P10) ? r_step_param10 :
r_step_param11 ;
assign w_kind =
(r_state == P_UPDATE_IW) ? `FPARAM_IW :
(r_state == P_UPDATE_X) ? `FPARAM_X :
(r_state == P_UPDATE_Z) ? `FPARAM_Z :
(r_state == P_UPDATE_P00) ? `FPARAM_P00 :
(r_state == P_UPDATE_P01) ? `FPARAM_P01 :
(r_state == P_UPDATE_P02) ? `FPARAM_P02 :
(r_state == P_UPDATE_P03) ? `FPARAM_P03 :
(r_state == P_UPDATE_P10) ? `FPARAM_P10 :
`FPARAM_P11 ;
`else
assign w_cur_val =
(r_state == P_UPDATE_IW) ? i_cur_iw :
(r_state == P_UPDATE_X) ? i_cur_x :
(r_state == P_UPDATE_Z) ? i_cur_z :
(r_state == P_UPDATE_P00) ? i_cur_param00 :
(r_state == P_UPDATE_P01) ? i_cur_param01 :
(r_state == P_UPDATE_P02) ? i_cur_param02 :
(r_state == P_UPDATE_P03) ? i_cur_param03 :
(r_state == P_UPDATE_P10) ? i_cur_param10 :
(r_state == P_UPDATE_P11) ? i_cur_param11 :
(r_state == P_UPDATE_P12) ? i_cur_param12 :
i_cur_param13;
assign w_cur_step =
(r_state == P_UPDATE_IW) ? r_step_iw :
(r_state == P_UPDATE_X) ? w_10 :
(r_state == P_UPDATE_Z) ? r_step_z :
(r_state == P_UPDATE_P00) ? r_step_param00 :
(r_state == P_UPDATE_P01) ? r_step_param01 :
(r_state == P_UPDATE_P02) ? r_step_param02 :
(r_state == P_UPDATE_P03) ? r_step_param03 :
(r_state == P_UPDATE_P10) ? r_step_param10 :
(r_state == P_UPDATE_P11) ? r_step_param11 :
(r_state == P_UPDATE_P12) ? r_step_param12 :
r_step_param13;
assign w_kind =
(r_state == P_UPDATE_IW) ? `FPARAM_IW :
(r_state == P_UPDATE_X) ? `FPARAM_X :
(r_state == P_UPDATE_Z) ? `FPARAM_Z :
(r_state == P_UPDATE_P00) ? `FPARAM_P00 :
(r_state == P_UPDATE_P01) ? `FPARAM_P01 :
(r_state == P_UPDATE_P02) ? `FPARAM_P02 :
(r_state == P_UPDATE_P03) ? `FPARAM_P03 :
(r_state == P_UPDATE_P10) ? `FPARAM_P10 :
(r_state == P_UPDATE_P11) ? `FPARAM_P11 :
(r_state == P_UPDATE_P12) ? `FPARAM_P12 :
`FPARAM_P13;
`endif
assign o_finish = o_update_end_flag & (r_state == P_UPDATE_WAIT);
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_UPDATE_IW;
end else begin
case (r_state)
P_UPDATE_IW: begin
if (i_start) begin
if (i_aa_mode) r_state <= P_UPDATE_Z;
else r_state <= P_UPDATE_X;
end
end
P_UPDATE_X: begin
r_state <= P_UPDATE_Z;
end
P_UPDATE_Z: begin
if (i_param0_en) r_state <= P_UPDATE_P00;
else if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end
P_UPDATE_P00: begin
if (i_param0_size == 2'd0) begin
if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P01;
end
end
P_UPDATE_P01: begin
if (i_param0_size == 2'd1) begin
if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P02;
end
end
P_UPDATE_P02: begin
if (i_param0_size == 2'd2) begin
if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P03;
end
end
P_UPDATE_P03: begin
if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end
P_UPDATE_P10: begin
if (i_param1_size == 2'd0) begin
r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P11;
end
end
P_UPDATE_P11: begin
if (i_param1_size == 2'd1) begin
r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P12;
end
end
P_UPDATE_P12: begin
if (i_param1_size == 2'd2) begin
r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P13;
end
end
P_UPDATE_P13: begin
r_state <= P_UPDATE_WAIT;
end
P_UPDATE_WAIT: begin
if (o_update_end_flag) r_state <= P_UPDATE_IW;
end
endcase
end
end
always @(posedge clk_core) begin
if (i_valid_step) begin
if (i_step_kind == `FPARAM_Z) r_step_z <= i_step_val;
if (i_step_kind == `FPARAM_IW) r_step_iw <= i_step_val;
if (i_step_kind == `FPARAM_P00) r_step_param00 <= i_step_val;
if (i_step_kind == `FPARAM_P01) r_step_param01 <= i_step_val;
if (i_step_kind == `FPARAM_P02) r_step_param02 <= i_step_val;
if (i_step_kind == `FPARAM_P03) r_step_param03 <= i_step_val;
if (i_step_kind == `FPARAM_P10) r_step_param10 <= i_step_val;
if (i_step_kind == `FPARAM_P11) r_step_param11 <= i_step_val;
`ifdef VTX_PARAM1_REDUCE
`else
if (i_step_kind == `FPARAM_P12) r_step_param12 <= i_step_val;
if (i_step_kind == `FPARAM_P13) r_step_param13 <= i_step_val;
`endif
end
end
////////////////////////////
// module instance
////////////////////////////
fm_3d_ru_span_update_core span_update_core (
.clk_core(clk_core),
.rst_x(rst_x),
.i_en(1'b1),
.i_valid(w_valid),
.i_kind(w_kind),
.i_end_flag(w_end_flag),
.i_cur_p({1'b0,w_cur_val}),
.i_step_p(w_cur_step),
.i_delta_a(i_delta_a),
.i_aa_mode(i_aa_mode),
.o_valid(o_update_valid),
.o_kind(o_update_kind),
.o_end_flag(o_update_end_flag),
.o_cur_p(o_update_val),
.o_frag_p(o_update_frag),
.o_x(o_update_x),
.o_z(o_update_z),
.o_color(o_update_color)
);
endmodule
|
module fm_3d_f22_floor (
i_a,
o_b
);
///////////////////////////////////////////
// port definition
///////////////////////////////////////////
input [20:0] i_a; // input e5, f1.15
output [20:0] o_b;
///////////////////////////////////////////
// wire definition
///////////////////////////////////////////
// intermidiate wire
wire [4:0] w_exp;
wire [15:0] w_fraction;
wire [15:0] w_fraction_out;
///////////////////////////////////////////
// assign statement
///////////////////////////////////////////
assign w_exp = i_a[20:16];
assign w_fraction = i_a[15:0];
assign o_b = {w_exp, w_fraction_out};
assign w_fraction_out = f_floor(w_exp, w_fraction);
///////////////////////////////////////////
// function statement
///////////////////////////////////////////
function [15:0] f_floor;
input [4:0] exp;
input [15:0] frac;
begin
case (exp[4:0])
5'hf: f_floor = {frac[15],15'h0};
5'h10: f_floor = {frac[15:14],14'h0};
5'h11: f_floor = {frac[15:13],13'h0};
5'h12: f_floor = {frac[15:12],12'h0};
5'h13: f_floor = {frac[15:11],11'h0};
5'h14: f_floor = {frac[15:10],10'h0};
5'h15: f_floor = {frac[15:9],9'h0};
5'h16: f_floor = {frac[15:8],8'h0};
5'h17: f_floor = {frac[15:7],7'h0};
5'h18: f_floor = {frac[15:6],6'h0};
5'h19: f_floor = {frac[15:5],5'h0};
5'h1a: f_floor = {frac[15:4],4'h0};
5'h1b: f_floor = {frac[15:3],3'h0};
5'h1c: f_floor = {frac[15:2],2'h0};
5'h1d: f_floor = {frac[15:1],1'h0};
5'h1e: f_floor = frac[15:0];
default: f_floor = 16'h0;
endcase
end
endfunction
endmodule
|
module fm_3d_ru_span_reg (
clk_core,
// parameter setup
i_initial_valid,
i_initial_kind,
i_initial_val,
// parameter update
i_update_valid,
i_update_kind,
i_update_end_flag,
i_update_val,
i_update_frag,
i_update_x,
i_update_z,
i_update_color,
// control registers
i_param0_en,
i_param1_en,
i_param0_size,
i_param1_size,
i_param0_kind,
i_param1_kind,
// current parameter output
o_cur_x,
o_cur_z,
o_cur_iw,
o_cur_param00,
o_cur_param01,
o_cur_param02,
o_cur_param03,
o_cur_param10,
o_cur_param11,
`ifdef VTX_PARAM1_REDUCE
`else
o_cur_param12,
o_cur_param13,
`endif
// parameter output
o_x,
o_z,
o_cr,
o_cg,
o_cb,
o_ca,
o_tu,
o_tv
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
// parameter setup
input i_initial_valid;
input [3:0] i_initial_kind;
input [21:0] i_initial_val;
// parameter update
input i_update_valid;
input [3:0] i_update_kind;
input i_update_end_flag;
input [21:0] i_update_val;
input [21:0] i_update_frag;
input [9:0] i_update_x;
input [15:0] i_update_z;
input [7:0] i_update_color;
// control registers
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
input [1:0] i_param0_kind;
input [1:0] i_param1_kind;
// current parameter output
output [20:0] o_cur_x;
output [20:0] o_cur_z;
output [20:0] o_cur_iw;
output [20:0] o_cur_param00;
output [20:0] o_cur_param01;
output [20:0] o_cur_param02;
output [20:0] o_cur_param03;
output [20:0] o_cur_param10;
output [20:0] o_cur_param11;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_cur_param12;
output [20:0] o_cur_param13;
`endif
// parameter output
output [9:0] o_x;
output [15:0] o_z;
output [7:0] o_cr;
output [7:0] o_cg;
output [7:0] o_cb;
output [7:0] o_ca;
output [21:0] o_tu;
output [21:0] o_tv;
////////////////////////////
// reg
////////////////////////////
reg [20:0] r_x;
reg [20:0] r_z;
reg [20:0] r_iw;
reg [20:0] r_param00;
reg [20:0] r_param01;
reg [20:0] r_param02;
reg [20:0] r_param03;
reg [20:0] r_param10;
reg [20:0] r_param11;
`ifdef VTX_PARAM1_REDUCE
`else
reg [20:0] r_param12;
reg [20:0] r_param13;
`endif
// output registers
reg [9:0] r_fx;
reg [15:0] r_fz;
reg [7:0] r_cr;
reg [7:0] r_cg;
reg [7:0] r_cb;
reg [7:0] r_ca;
reg [21:0] r_tu;
reg [21:0] r_tv;
////////////////////////////
// wire
////////////////////////////
wire w_set_initial_x;
wire w_set_initial_z;
wire w_set_initial_iw;
wire w_set_initial_param00;
wire w_set_initial_param01;
wire w_set_initial_param02;
wire w_set_initial_param03;
wire w_set_initial_param10;
wire w_set_initial_param11;
`ifdef VTX_PARAM1_REDUCE
`else
wire w_set_initial_param12;
wire w_set_initial_param13;
`endif
wire w_set_update_x;
wire w_set_update_z;
wire w_set_update_iw;
wire w_set_update_param00;
wire w_set_update_param01;
wire w_set_update_param02;
wire w_set_update_param03;
wire w_set_update_param10;
wire w_set_update_param11;
`ifdef VTX_PARAM1_REDUCE
`else
wire w_set_update_param12;
wire w_set_update_param13;
`endif
wire w_set_x;
wire w_set_z;
wire w_set_cr;
wire w_set_cg;
wire w_set_cb;
wire w_set_ca;
wire w_set_tu;
wire w_set_tv;
////////////////////////////
// assign
////////////////////////////
assign w_set_initial_x = i_initial_valid & (i_initial_kind == `FPARAM_X);
assign w_set_initial_z = i_initial_valid & (i_initial_kind == `FPARAM_Z);
assign w_set_initial_iw = i_initial_valid &
(i_initial_kind == `FPARAM_IW);
assign w_set_initial_param00 = i_initial_valid &
(i_initial_kind == `FPARAM_P00);
assign w_set_initial_param01 = i_initial_valid &
(i_initial_kind == `FPARAM_P01);
assign w_set_initial_param02 = i_initial_valid &
(i_initial_kind == `FPARAM_P02);
assign w_set_initial_param03 = i_initial_valid &
(i_initial_kind == `FPARAM_P03);
assign w_set_initial_param10 = i_initial_valid &
(i_initial_kind == `FPARAM_P10);
assign w_set_initial_param11 = i_initial_valid &
(i_initial_kind == `FPARAM_P11);
`ifdef VTX_PARAM1_REDUCE
`else
assign w_set_initial_param12 = i_initial_valid &
(i_initial_kind == `FPARAM_P12);
assign w_set_initial_param13 = i_initial_valid &
(i_initial_kind == `FPARAM_P13);
`endif
assign w_set_update_x = i_update_valid & (i_update_kind == `FPARAM_X);
assign w_set_update_z = i_update_valid & (i_update_kind == `FPARAM_Z);
assign w_set_update_iw = i_update_valid &
(i_update_kind == `FPARAM_IW);
assign w_set_update_param00 = i_update_valid &
(i_update_kind == `FPARAM_P00);
assign w_set_update_param01 = i_update_valid &
(i_update_kind == `FPARAM_P01);
assign w_set_update_param02 = i_update_valid &
(i_update_kind == `FPARAM_P02);
assign w_set_update_param03 = i_update_valid &
(i_update_kind == `FPARAM_P03);
assign w_set_update_param10 = i_update_valid &
(i_update_kind == `FPARAM_P10);
assign w_set_update_param11 = i_update_valid &
(i_update_kind == `FPARAM_P11);
`ifdef VTX_PARAM1_REDUCE
`else
assign w_set_update_param12 = i_update_valid &
(i_update_kind == `FPARAM_P12);
assign w_set_update_param13 = i_update_valid &
(i_update_kind == `FPARAM_P13);
`endif
assign w_set_x = w_set_update_x;
assign w_set_z = w_set_update_z;
assign w_set_cr = (i_param0_kind == `ATTR_COLOR0) ? w_set_update_param00 :
w_set_update_param10;
assign w_set_cg = (i_param0_kind == `ATTR_COLOR0) ? w_set_update_param01 :
w_set_update_param11;
`ifdef VTX_PARAM1_REDUCE
assign w_set_cb = w_set_update_param02;
assign w_set_ca = w_set_update_param03;
`else
assign w_set_cb = (i_param0_kind == `ATTR_COLOR0) ? w_set_update_param02 :
w_set_update_param12;
assign w_set_ca = (i_param0_kind == `ATTR_COLOR0) ? w_set_update_param03 :
w_set_update_param13;
`endif
assign w_set_tu = (i_param1_kind == `ATTR_TEXTURE0) ? w_set_update_param10 :
w_set_update_param00;
assign w_set_tv = (i_param1_kind == `ATTR_TEXTURE0) ? w_set_update_param11 :
w_set_update_param01;
assign o_cur_x = r_x;
assign o_cur_z = r_z;
assign o_cur_iw = r_iw;
assign o_cur_param00 = r_param00;
assign o_cur_param01 = r_param01;
assign o_cur_param02 = r_param02;
assign o_cur_param03 = r_param03;
assign o_cur_param10 = r_param10;
assign o_cur_param11 = r_param11;
`ifdef VTX_PARAM1_REDUCE
`else
assign o_cur_param12 = r_param12;
assign o_cur_param13 = r_param13;
`endif
assign o_x = r_fx;
assign o_z = r_fz;
assign o_cr = r_cr;
assign o_cg = r_cg;
assign o_cb = r_cb;
assign o_ca = r_ca;
assign o_tu = r_tu;
assign o_tv = r_tv;
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core) begin
if (w_set_update_x) r_x <= i_update_val[20:0];
else if (w_set_initial_x) r_x <= i_initial_val[20:0];
if (w_set_update_z) r_z <= i_update_val[20:0];
else if (w_set_initial_z) r_z <= i_initial_val[20:0];
if (w_set_update_iw) r_iw <= i_update_val[20:0];
else if (w_set_initial_iw) r_iw <= i_initial_val[20:0];
if (w_set_update_param00) r_param00 <= i_update_val[20:0];
else if (w_set_initial_param00) r_param00 <= i_initial_val[20:0];
if (w_set_update_param01) r_param01 <= i_update_val[20:0];
else if (w_set_initial_param01) r_param01 <= i_initial_val[20:0];
if (w_set_update_param02) r_param02 <= i_update_val[20:0];
else if (w_set_initial_param02) r_param02 <= i_initial_val[20:0];
if (w_set_update_param03) r_param03 <= i_update_val[20:0];
else if (w_set_initial_param03) r_param03 <= i_initial_val[20:0];
if (w_set_update_param10) r_param10 <= i_update_val[20:0];
else if (w_set_initial_param10) r_param10 <= i_initial_val[20:0];
if (w_set_update_param11) r_param11 <= i_update_val[20:0];
else if (w_set_initial_param11) r_param11 <= i_initial_val[20:0];
`ifdef VTX_PARAM1_REDUCE
`else
if (w_set_update_param12) r_param12 <= i_update_val[20:0];
else if (w_set_initial_param12) r_param12 <= i_initial_val[20:0];
if (w_set_update_param13) r_param13 <= i_update_val[20:0];
else if (w_set_initial_param13) r_param13 <= i_initial_val[20:0];
`endif
end
// output registers
always @(posedge clk_core) begin
if (w_set_x) r_fx <= i_update_x;
if (w_set_z) r_fz <= i_update_z;
if (w_set_cr) r_cr <= i_update_color;
if (w_set_cg) r_cg <= i_update_color;
if (w_set_cb) r_cb <= i_update_color;
if (w_set_ca) r_ca <= i_update_color;
if (w_set_tu) r_tu <= i_update_frag;
if (w_set_tv) r_tv <= i_update_frag;
end
endmodule
|
module fm_3d_ru_outline_step (
clk_core,
rst_x,
// outline parameter input
i_start,
o_finish,
i_delta_t,
// vertex parameters
i_start_x,
i_start_y,
i_delta_x,
i_z_s,
i_iw_s,
i_param00_s,
i_param01_s,
i_param02_s,
i_param03_s,
i_param10_s,
i_param11_s,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_s,
i_param13_s,
`endif
i_z_e,
i_iw_e,
i_param00_e,
i_param01_e,
i_param02_e,
i_param03_e,
i_param10_e,
i_param11_e,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_e,
i_param13_e,
`endif
// control registers
i_param0_en,
i_param1_en,
i_param0_size,
i_param1_size,
// output
o_valid,
o_param_kind,
o_initial_val,
o_step_val
);
////////////////////////////
// parameter
////////////////////////////
parameter P_SETUP_X = 4'h0;
parameter P_SETUP_Y = 4'h1;
parameter P_SETUP_IW = 4'h2;
parameter P_SETUP_Z = 4'h3;
parameter P_SETUP_P00 = 4'h4;
parameter P_SETUP_P01 = 4'h5;
parameter P_SETUP_P02 = 4'h6;
parameter P_SETUP_P03 = 4'h7;
parameter P_SETUP_P10 = 4'h8;
parameter P_SETUP_P11 = 4'h9;
parameter P_SETUP_P12 = 4'ha;
parameter P_SETUP_P13 = 4'hb;
parameter P_SETUP_WAIT = 4'hc;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// outline parameter input
input i_start;
output o_finish;
input [21:0] i_delta_t;
// vertex parameters
input [20:0] i_start_x;
input [20:0] i_start_y;
input [21:0] i_delta_x;
input [20:0] i_z_s;
input [20:0] i_iw_s;
input [20:0] i_param00_s;
input [20:0] i_param01_s;
input [20:0] i_param02_s;
input [20:0] i_param03_s;
input [20:0] i_param10_s;
input [20:0] i_param11_s;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_s;
input [20:0] i_param13_s;
`endif
input [20:0] i_z_e;
input [20:0] i_iw_e;
input [20:0] i_param00_e;
input [20:0] i_param01_e;
input [20:0] i_param02_e;
input [20:0] i_param03_e;
input [20:0] i_param10_e;
input [20:0] i_param11_e;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_e;
input [20:0] i_param13_e;
`endif
// control registers
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
// output
output o_valid;
output [3:0] o_param_kind;
output [21:0] o_initial_val;
output [21:0] o_step_val;
////////////////////////////
// reg
////////////////////////////
reg [3:0] r_state;
////////////////////////////
// wire
////////////////////////////
wire [20:0] w_end_p;
wire [20:0] w_start_p;
wire w_apply_iw;
wire w_valid;
wire w_end_flag;
wire w_end_flag_z;
wire w_end_flag_p00;
wire w_end_flag_p01;
wire w_end_flag_p02;
wire w_end_flag_p03;
wire w_end_flag_p10;
wire w_end_flag_p11;
wire w_end_flag_p12;
wire [3:0] w_param_kind;
wire [21:0] w_10;
wire w_valid_core;
wire [3:0] w_param_kind_core;
wire [20:0] w_initial_val_core;
wire [21:0] w_step_val_core;
////////////////////////////
// assign
////////////////////////////
assign w_10 = {1'b0, 5'h0f, 16'h8000};
assign w_valid = (r_state != P_SETUP_WAIT) &
(r_state != P_SETUP_X) & (r_state != P_SETUP_Y);
assign w_apply_iw = (r_state != P_SETUP_IW);
assign w_end_flag_z = (r_state == P_SETUP_Z) & !i_param0_en & !i_param1_en;
assign w_end_flag_p00 = (r_state == P_SETUP_P00) &
(i_param0_en & (i_param0_size == 2'd0)) &
!i_param1_en;
assign w_end_flag_p01 = (r_state == P_SETUP_P01) &
(i_param0_size == 2'd1) & !i_param1_en;
assign w_end_flag_p02 = (r_state == P_SETUP_P02) &
(i_param0_size == 2'd2) & !i_param1_en;
assign w_end_flag_p03 = (r_state == P_SETUP_P03) & !i_param1_en;
assign w_end_flag_p10 = (r_state == P_SETUP_P10) & (i_param1_size == 2'd0);
assign w_end_flag_p11 = (r_state == P_SETUP_P11) & (i_param1_size == 2'd1);
assign w_end_flag_p12 = (r_state == P_SETUP_P11) & (i_param1_size == 2'd2);
assign w_end_flag = w_end_flag_z |
w_end_flag_p00 | w_end_flag_p01 | w_end_flag_p02 | w_end_flag_p03|
w_end_flag_p10 | w_end_flag_p11 | w_end_flag_p12 | w_end_flag_p03;
`ifdef VTX_PARAM1_REDUCE
assign w_start_p = (r_state == P_SETUP_IW) ? i_iw_s :
(r_state == P_SETUP_Z) ? i_z_s :
(r_state == P_SETUP_P00) ? i_param00_s :
(r_state == P_SETUP_P01) ? i_param01_s :
(r_state == P_SETUP_P02) ? i_param02_s :
(r_state == P_SETUP_P03) ? i_param03_s :
(r_state == P_SETUP_P10) ? i_param10_s :
i_param11_s ;
assign w_end_p = (r_state == P_SETUP_IW) ? i_iw_e :
(r_state == P_SETUP_Z) ? i_z_e :
(r_state == P_SETUP_P00) ? i_param00_e :
(r_state == P_SETUP_P01) ? i_param01_e :
(r_state == P_SETUP_P02) ? i_param02_e :
(r_state == P_SETUP_P03) ? i_param03_e :
(r_state == P_SETUP_P10) ? i_param10_e :
i_param11_e ;
`else
assign w_start_p = (r_state == P_SETUP_IW) ? i_iw_s :
(r_state == P_SETUP_Z) ? i_z_s :
(r_state == P_SETUP_P00) ? i_param00_s :
(r_state == P_SETUP_P01) ? i_param01_s :
(r_state == P_SETUP_P02) ? i_param02_s :
(r_state == P_SETUP_P03) ? i_param03_s :
(r_state == P_SETUP_P10) ? i_param10_s :
(r_state == P_SETUP_P11) ? i_param11_s :
(r_state == P_SETUP_P12) ? i_param12_s :
i_param13_s;
assign w_end_p = (r_state == P_SETUP_IW) ? i_iw_e :
(r_state == P_SETUP_Z) ? i_z_e :
(r_state == P_SETUP_P00) ? i_param00_e :
(r_state == P_SETUP_P01) ? i_param01_e :
(r_state == P_SETUP_P02) ? i_param02_e :
(r_state == P_SETUP_P03) ? i_param03_e :
(r_state == P_SETUP_P10) ? i_param10_e :
(r_state == P_SETUP_P11) ? i_param11_e :
(r_state == P_SETUP_P12) ? i_param12_e :
i_param13_e;
`endif
assign w_param_kind = (r_state == P_SETUP_IW) ? `FPARAM_IW :
(r_state == P_SETUP_Z) ? `FPARAM_Z :
(r_state == P_SETUP_P00) ? `FPARAM_P00 :
(r_state == P_SETUP_P01) ? `FPARAM_P01 :
(r_state == P_SETUP_P02) ? `FPARAM_P02 :
(r_state == P_SETUP_P03) ? `FPARAM_P03 :
(r_state == P_SETUP_P10) ? `FPARAM_P10 :
(r_state == P_SETUP_P11) ? `FPARAM_P11 :
(r_state == P_SETUP_P12) ? `FPARAM_P12 :
`FPARAM_P13;
assign o_valid = w_valid_core | (r_state == P_SETUP_Y) |
((r_state == P_SETUP_X)&i_start);
assign o_param_kind = (r_state == P_SETUP_X) ? `FPARAM_X :
(r_state == P_SETUP_Y) ? `FPARAM_Y :
w_param_kind_core;
assign o_initial_val = (r_state == P_SETUP_X) ? i_start_x:
(r_state == P_SETUP_Y) ? i_start_y:
w_initial_val_core;
assign o_step_val = (r_state == P_SETUP_X) ? i_delta_x :
(r_state == P_SETUP_Y) ? w_10 :
w_step_val_core;
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_SETUP_X;
end else begin
case (r_state)
P_SETUP_X: begin
if (i_start) r_state <= P_SETUP_Y;
end
P_SETUP_Y: begin
r_state <= P_SETUP_IW;
end
P_SETUP_IW: begin
r_state <= P_SETUP_Z;
end
P_SETUP_Z: begin
if (i_param0_en) r_state <= P_SETUP_P00;
else if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end
P_SETUP_P00: begin
if (i_param0_size == 2'd0) begin
if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P01;
end
end
P_SETUP_P01: begin
if (i_param0_size == 2'd1) begin
if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P02;
end
end
P_SETUP_P02: begin
if (i_param0_size == 2'd2) begin
if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P03;
end
end
P_SETUP_P03: begin
if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end
P_SETUP_P10: begin
if (i_param1_size == 2'd0) begin
r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P11;
end
end
P_SETUP_P11: begin
if (i_param1_size == 2'd1) begin
r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P12;
end
end
P_SETUP_P12: begin
if (i_param1_size == 2'd2) begin
r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P13;
end
end
P_SETUP_P13: begin
r_state <= P_SETUP_WAIT;
end
P_SETUP_WAIT: begin
if (o_finish) r_state <= P_SETUP_X;
end
endcase
end
end
////////////////////////////
// module instance
////////////////////////////
fm_3d_ru_outline_step_core outline_step_core (
.clk_core(clk_core),
.i_en(1'b1),
.i_valid(w_valid),
.i_kind(w_param_kind),
.i_end_flag(w_end_flag),
.i_start_p(w_start_p),
.i_end_p(w_end_p),
.i_start_iw(i_iw_s),
.i_end_iw(i_iw_e),
.i_delta_t(i_delta_t),
.i_apply_iw(w_apply_iw),
.o_valid(w_valid_core),
.o_kind(w_param_kind_core),
.o_end_flag(o_finish),
.o_start_p(w_initial_val_core),
.o_step_p(w_step_val_core)
);
endmodule
|
module fm_3d_f22_to_i8_2 (
i_a,
o_b
);
///////////////////////////////////////////
// port definition
///////////////////////////////////////////
input [21:0] i_a; // input s1, e5, f1.15
output [7:0] o_b; // unsigned integer
///////////////////////////////////////////
// wire definition
///////////////////////////////////////////
// intermidiate wire
wire w_sign;
wire [4:0] w_exp;
wire [15:0] w_fraction;
///////////////////////////////////////////
// assign statement
///////////////////////////////////////////
assign w_sign = i_a[21];
assign w_exp = i_a[20:16];
assign w_fraction = i_a[15:0];
assign o_b = f_ftoi(w_exp, w_fraction);
///////////////////////////////////////////
// function statement
///////////////////////////////////////////
function [7:0] f_ftoi;
input [4:0] exp;
input [15:0] frac;
begin
case (exp)
5'd15: f_ftoi = {7'b0,frac[15]};
5'd16: f_ftoi = {6'b0,frac[15:14]};
5'd17: f_ftoi = {5'b0,frac[15:13]};
5'd18: f_ftoi = {4'b0,frac[15:12]};
5'd19: f_ftoi = {3'b0,frac[15:11]};
5'd20: f_ftoi = {2'b0,frac[15:10]};
5'd21: f_ftoi = {1'b0,frac[15:9]};
5'd22: f_ftoi = frac[15:8];
5'd23: f_ftoi = 8'd255; // overflow
default: f_ftoi = 8'h0; // including zero
endcase
end
endfunction
endmodule
|
module fm_3d_ru_outline_edge_core (
clk_core,
rst_x,
// idle state indicator
o_idle,
// outline parameters
i_valid,
i_has_bottom,
i_start_x,
i_start_x_05,
i_start_y,
i_end_y,
i_delta_x,
i_delta_t,
i_delta_a,
o_ack,
// vertex parameters
i_z_s,
i_iw_s,
i_param00_s,
i_param01_s,
i_param02_s,
i_param03_s,
i_param10_s,
i_param11_s,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_s,
i_param13_s,
`endif
i_z_e,
i_iw_e,
i_param00_e,
i_param01_e,
i_param02_e,
i_param03_e,
i_param10_e,
i_param11_e,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_e,
i_param13_e,
`endif
// control registers
i_aa_mode,
i_param0_en,
i_param1_en,
i_param0_size,
i_param1_size,
// output
o_valid,
i_busy,
o_x,
o_y,
o_z,
o_iw,
o_param00,
o_param01,
o_param02,
o_param03,
o_param10,
o_param11
`ifdef VTX_PARAM1_REDUCE
`else
,o_param12,
o_param13
`endif
);
////////////////////////////
// parameter
////////////////////////////
parameter P_IDLE = 3'h0;
parameter P_SETUP = 3'h1;
parameter P_SKIP_BOTTOM = 3'h2;
parameter P_SETUP_AA = 3'h3;
parameter P_WAIT_AA = 3'h4;
parameter P_OUTPUT = 3'h5;
parameter P_UPDATE = 3'h6;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// idle state indicator
output o_idle;
// outline parameters
input i_valid;
input i_has_bottom;
input [20:0] i_start_x;
input [20:0] i_start_x_05;
input [20:0] i_start_y;
input [20:0] i_end_y;
input [21:0] i_delta_x;
input [21:0] i_delta_t;
input [21:0] i_delta_a;
output o_ack; // empty flag
// vertex parameters
input [20:0] i_z_s;
input [20:0] i_iw_s;
input [20:0] i_param00_s;
input [20:0] i_param01_s;
input [20:0] i_param02_s;
input [20:0] i_param03_s;
input [20:0] i_param10_s;
input [20:0] i_param11_s;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_s;
input [20:0] i_param13_s;
`endif
input [20:0] i_z_e;
input [20:0] i_iw_e;
input [20:0] i_param00_e;
input [20:0] i_param01_e;
input [20:0] i_param02_e;
input [20:0] i_param03_e;
input [20:0] i_param10_e;
input [20:0] i_param11_e;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_e;
input [20:0] i_param13_e;
`endif
// control registers
input i_aa_mode;
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
// output
output o_valid;
input i_busy;
output [20:0] o_x;
output [8:0] o_y;
output [20:0] o_z;
output [20:0] o_iw;
output [20:0] o_param00;
output [20:0] o_param01;
output [20:0] o_param02;
output [20:0] o_param03;
output [20:0] o_param10;
output [20:0] o_param11;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_param12;
output [20:0] o_param13;
`endif
////////////////////////////
// reg
////////////////////////////
reg [2:0] r_state;
////////////////////////////
// wire
////////////////////////////
wire [20:0] w_start_x;
wire w_start_step;
wire w_finish_step;
wire w_initial_valid;
wire [3:0] w_initial_kind;
wire [21:0] w_initial_val;
wire [21:0] w_initial_step;
wire w_start_update;
wire w_finish_update;
wire w_update_valid;
wire [3:0] w_update_kind;
wire [21:0] w_update_edge_val;
wire w_aa_mode;
wire w_edge_end;
wire [20:0] w_edge_y;
////////////////////////////
// assign
////////////////////////////
assign w_aa_mode = (r_state == P_SETUP_AA)|(r_state == P_WAIT_AA);
assign w_start_x = (i_aa_mode) ? i_start_x : i_start_x_05;
assign w_edge_end = (w_edge_y >= i_end_y);
assign w_start_step = (r_state == P_IDLE) & i_valid;
assign w_start_update = (r_state == P_SETUP_AA) |
((r_state == P_SETUP) & w_finish_step & !i_aa_mode & !i_has_bottom & !w_edge_end) |
((r_state == P_OUTPUT) & !i_busy&!w_edge_end);
// port connection
assign o_valid = (r_state == P_OUTPUT);
assign o_ack = ((r_state == P_OUTPUT)& !i_busy&w_edge_end) |
((r_state == P_SETUP)&w_finish_step&!i_has_bottom&w_edge_end&!i_aa_mode);
assign o_idle = (r_state == P_IDLE);
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (i_valid) r_state <= P_SETUP;
end
P_SETUP: begin // gen setps
if (w_finish_step) begin
if (i_aa_mode) begin
r_state <= P_SETUP_AA;
end else if (!i_has_bottom) begin
if (w_edge_end) r_state <= P_IDLE;
else r_state <= P_SKIP_BOTTOM;
end else begin
r_state <= P_OUTPUT;
end
end
end
P_SKIP_BOTTOM: begin
if (w_finish_update) begin
if (i_aa_mode) r_state <= P_SETUP_AA;
else r_state <= P_OUTPUT;
end
end
P_SETUP_AA: begin // additional setup for aa
r_state <= P_WAIT_AA;
end
P_WAIT_AA: begin
if (w_finish_update) r_state <= P_OUTPUT;
end
P_OUTPUT: begin
if (!i_busy) begin
if (w_edge_end) r_state <= P_IDLE;
else r_state <= P_UPDATE;
end
end
P_UPDATE: begin
if (w_finish_update) r_state <= P_OUTPUT;
end
endcase
end
end
////////////////////////////
// module instance
////////////////////////////
fm_3d_ru_outline_step outline_step (
.clk_core(clk_core),
.rst_x(rst_x),
// outline parameter input
.i_start(w_start_step),
.o_finish(w_finish_step),
.i_delta_t(i_delta_t),
// vertex parameters
.i_start_x(w_start_x),
.i_start_y(i_start_y),
.i_delta_x(i_delta_x),
.i_z_s(i_z_s),
.i_iw_s(i_iw_s),
.i_param00_s(i_param00_s),
.i_param01_s(i_param01_s),
.i_param02_s(i_param02_s),
.i_param03_s(i_param03_s),
.i_param10_s(i_param10_s),
.i_param11_s(i_param11_s),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_s(i_param12_s),
.i_param13_s(i_param13_s),
`endif
.i_z_e(i_z_e),
.i_iw_e(i_iw_e),
.i_param00_e(i_param00_e),
.i_param01_e(i_param01_e),
.i_param02_e(i_param02_e),
.i_param03_e(i_param03_e),
.i_param10_e(i_param10_e),
.i_param11_e(i_param11_e),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_e(i_param12_e),
.i_param13_e(i_param13_e),
`endif
// control registers
.i_param0_en(i_param0_en),
.i_param1_en(i_param1_en),
.i_param0_size(i_param0_size),
.i_param1_size(i_param1_size),
// output
.o_valid(w_initial_valid),
.o_param_kind(w_initial_kind),
.o_initial_val(w_initial_val),
.o_step_val(w_initial_step)
);
fm_3d_ru_outline_update outline_update (
.clk_core(clk_core),
.rst_x(rst_x),
// parameter input
.i_start(w_start_update),
.i_aa_mode(w_aa_mode),
.i_delta_a(i_delta_a),
.o_finish(w_finish_update),
// generated steps
.i_valid_step(w_initial_valid),
.i_step_kind(w_initial_kind),
.i_step_val(w_initial_step),
.i_initial_val(w_initial_val),
// control registers
.i_param0_en(i_param0_en),
.i_param1_en(i_param1_en),
.i_param0_size(i_param0_size),
.i_param1_size(i_param1_size),
// new value
.o_new_valid(w_update_valid),
.o_new_kind(w_update_kind),
.o_new_edge_val(w_update_edge_val)
);
fm_3d_ru_outline_reg outline_reg (
.clk_core(clk_core),
// parameter init
.i_coord_valid(w_start_step),
.i_start_x(w_start_x),
.i_start_y(i_start_y),
.i_init_valid(w_initial_valid),
.i_init_kind(w_initial_kind),
.i_init_val(w_initial_val[20:0]),
// parameter update
.i_update_valid(w_update_valid),
.i_update_kind(w_update_kind),
.i_update_edge_val(w_update_edge_val),
// parameter out
.o_edge_x(o_x),
.o_edge_y(o_y),
.o_edge_y_float(w_edge_y),
.o_edge_z(o_z),
.o_edge_iw(o_iw),
.o_edge_param00(o_param00),
.o_edge_param01(o_param01),
.o_edge_param02(o_param02),
.o_edge_param03(o_param03),
.o_edge_param10(o_param10),
.o_edge_param11(o_param11)
`ifdef VTX_PARAM1_REDUCE
`else
,.o_edge_param12(o_param12),
.o_edge_param13(o_param13)
`endif
);
endmodule
|
module fm_3d_mu_cache_tag (
clk_core,
rst_x,
i_tw_valid,
i_adrs_pre, // for timing improvement
i_adrs,
i_tag_clear,
o_hit,
o_need_wb,
o_entry,
o_tag_adrs
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
//parameter P_ADRS_WIDTH = 26; // 21.5.4
parameter P_ADRS_WIDTH = P_IB_TAG_ADDR_WIDTH+P_IB_CACHE_ENTRY_WIDTH;
parameter P_ENTRY_RANGE = P_IB_CACHE_ENTRY_WIDTH;
parameter P_ENTRY_DEPTH = 1 << P_ENTRY_RANGE;
parameter P_TAG_RANGE = P_ADRS_WIDTH - P_ENTRY_RANGE;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
input i_tw_valid;
input [P_ADRS_WIDTH-1:0]
i_adrs_pre;
input [P_ADRS_WIDTH-1:0]
i_adrs;
input i_tag_clear;
output o_hit;
output o_need_wb;
output [P_ENTRY_RANGE-1:0]
o_entry;
output [P_TAG_RANGE-1:0]
o_tag_adrs;
//////////////////////////////////
// wire
//////////////////////////////////
wire w_tag_update;
wire [P_ENTRY_RANGE-1:0]
w_update_number_pre;
wire [P_ENTRY_RANGE-1:0]
w_update_number;
wire w_cmp;
wire w_valid;
wire [P_ADRS_WIDTH-P_ENTRY_RANGE-1:0]
w_tag_adrs;
wire [P_ADRS_WIDTH-P_ENTRY_RANGE-1:0]
w_new_adrs;
//////////////////////////////////
// reg
//////////////////////////////////
reg [P_ENTRY_DEPTH-1:0] r_valids;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_update_number_pre = i_adrs_pre[P_ENTRY_RANGE-1:0];
assign w_update_number = i_adrs[P_ENTRY_RANGE-1:0];
assign w_new_adrs = i_adrs[P_ADRS_WIDTH-1:P_ENTRY_RANGE];
assign w_cmp = (w_tag_adrs == w_new_adrs);
assign w_valid = r_valids[w_update_number];
assign o_hit = (w_valid) ? w_cmp : 1'b0 ;
assign w_tag_update = !o_hit & i_tw_valid;
assign o_need_wb = w_valid;
assign o_entry = w_update_number;
assign o_tag_adrs = w_tag_adrs;
//////////////////////////////////
// always
//////////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
// tag initial clear
r_valids <= {P_ENTRY_DEPTH{1'b0}};
end else begin
if (i_tag_clear) begin
r_valids <= {P_ENTRY_DEPTH{1'b0}};
end
if (w_tag_update) begin
r_valids[w_update_number] <= 1'b1;
end
end
end
////////////////////////////
// module instance
////////////////////////////
// not including valid bit
fm_cmn_bram_01 #((P_ADRS_WIDTH-P_ENTRY_RANGE),P_ENTRY_RANGE) tag_bram (
.clk(clk_core),
.we(w_tag_update),
.a(w_update_number),
.dpra(w_update_number_pre), // check address
.di(w_new_adrs),
.spo(),
.dpo(w_tag_adrs)
);
endmodule
|
module fm_3d_mu_cache (
clk_core,
rst_x,
// system configuration
i_cache_init,
i_cache_flush,
o_flush_done,
// cache in
i_req_ci,
i_wr_ci,
i_adrs_ci,
o_ack_ci,
i_len_ci,
i_be_ci,
i_strw_ci,
i_dbw_ci,
o_ackw_ci,
o_strr_ci,
o_dbr_ci,
// cache out
o_req_co,
o_wr_co,
o_adrs_co,
i_ack_co,
o_len_co,
o_be_co,
o_strw_co,
o_dbw_co,
i_ackw_co,
i_strr_co,
i_dbr_co
);
`include "polyphony_params.v"
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// system configueration
input i_cache_init;
input i_cache_flush;
output o_flush_done;
// cache in
input i_req_ci;
input i_wr_ci;
input [P_IB_ADDR_WIDTH-1:0]
i_adrs_ci;
output o_ack_ci;
input [P_IB_LEN_WIDTH-1:0]
i_len_ci;
input [P_IB_BE_WIDTH-1:0]
i_be_ci;
input i_strw_ci;
input [P_IB_DATA_WIDTH-1:0]
i_dbw_ci;
output o_ackw_ci;
output o_strr_ci;
output [P_IB_DATA_WIDTH-1:0]
o_dbr_ci;
// cache out
output o_req_co;
output o_wr_co;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs_co;
input i_ack_co;
output [P_IB_LEN_WIDTH-1:0]
o_len_co;
output [P_IB_BE_WIDTH-1:0]
o_be_co;
output o_strw_co;
output [P_IB_DATA_WIDTH-1:0]
o_dbw_co;
input i_ackw_co;
input i_strr_co;
input [P_IB_DATA_WIDTH-1:0]
i_dbr_co;
//////////////////////////////////
// wire
//////////////////////////////////
// tag - ctrl
wire w_tw_valid;
wire [P_IB_ADDR_WIDTH-1:0]
w_cmp_adrs;
wire [P_IB_ADDR_WIDTH-1:0]
w_cmp_adrs_pre;
wire w_tag_clear;
wire w_hit;
wire w_need_wb;
wire [P_IB_CACHE_ENTRY_WIDTH-1:0]
w_entry; // 32 entries
wire [P_IB_TAG_ADDR_WIDTH-1:0]
w_tag_adrs;
// cache memory - ctrl
wire w_we_cm;
wire [P_IB_CACHE_LINE_WIDTH+P_IB_CACHE_ENTRY_WIDTH-1:0]
w_adrs_cm;
wire [P_IB_CACHE_LINE_WIDTH+P_IB_CACHE_ENTRY_WIDTH-1:0]
w_adrs_pre_cm;
wire [P_IB_BE_WIDTH-1:0]
w_be_cm;
wire [P_IB_DATA_WIDTH-1:0]
w_dto_cm;
wire [P_IB_DATA_WIDTH-1:0]
w_dti_cm;
wire [P_IB_DATA_WIDTH-1:0]
w_dti_pre_cm;
////////////////////////////
// module instance
////////////////////////////
fm_3d_mu_cache_tag cache_tag (
.clk_core(clk_core),
.rst_x(rst_x),
.i_tw_valid(w_tw_valid),
.i_adrs_pre(w_cmp_adrs_pre[P_IB_ADDR_WIDTH-1:P_IB_CACHE_LINE_WIDTH]),
.i_adrs(w_cmp_adrs[P_IB_ADDR_WIDTH-1:P_IB_CACHE_LINE_WIDTH]),
.i_tag_clear(w_tag_clear),
.o_hit(w_hit),
.o_need_wb(w_need_wb),
.o_entry(w_entry),
.o_tag_adrs(w_tag_adrs)
);
fm_3d_mu_cache_mem cache_mem (
.clk_core(clk_core),
.i_we(w_we_cm),
.i_adrs(w_adrs_cm),
.i_adrs_pre(w_adrs_pre_cm),
.i_be(w_be_cm),
.i_dt(w_dto_cm),
.o_dt(w_dti_cm),
.o_dt_pre(w_dti_pre_cm)
);
fm_3d_mu_cache_ctrl cache_ctrl (
.clk_core(clk_core),
.rst_x(rst_x),
// system configuration
.i_cache_init(i_cache_init),
.i_cache_flush(i_cache_flush),
.o_flush_done(o_flush_done),
// cache in
.i_req_ci(i_req_ci),
.i_wr_ci(i_wr_ci),
.i_adrs_ci(i_adrs_ci),
.o_ack_ci(o_ack_ci),
.i_len_ci(i_len_ci),
.i_be_ci(i_be_ci),
.i_strw_ci(i_strw_ci),
.i_dbw_ci(i_dbw_ci),
.o_ackw_ci(o_ackw_ci),
.o_strr_ci(o_strr_ci),
.o_dbr_ci(o_dbr_ci),
// cache tag
.o_tw_valid(w_tw_valid),
.o_cmp_adrs_pre(w_cmp_adrs_pre),
.o_cmp_adrs(w_cmp_adrs),
.o_tag_clear(w_tag_clear),
.i_hit(w_hit),
.i_need_wb(w_need_wb),
.i_entry(w_entry),
.i_tag_adrs(w_tag_adrs),
//cache memory
.o_we_cm(w_we_cm),
.o_adrs_cm(w_adrs_cm),
.o_adrs_pre_cm(w_adrs_pre_cm),
.o_be_cm(w_be_cm),
.o_dt_cm(w_dto_cm),
.i_dt_cm(w_dti_cm),
.i_dt_pre_cm(w_dti_pre_cm),
// external memory access
.o_req_co(o_req_co),
.o_wr_co(o_wr_co),
.o_adrs_co(o_adrs_co),
.i_ack_co(i_ack_co),
.o_len_co(o_len_co),
.o_be_co(o_be_co),
.o_strw_co(o_strw_co),
.o_dbw_co(o_dbw_co),
.i_ackw_co(i_ackw_co),
.i_strr_co(i_strr_co),
.i_dbr_co(i_dbr_co)
);
endmodule
|
module fm_3d_ru_outline_reg (
clk_core,
// parameter init
i_coord_valid,
i_start_x,
i_start_y,
i_init_valid,
i_init_kind,
i_init_val,
// parameter update
i_update_valid,
i_update_kind,
i_update_edge_val,
// parameter output
o_edge_x,
o_edge_y,
o_edge_y_float,
o_edge_z,
o_edge_iw,
o_edge_param00,
o_edge_param01,
o_edge_param02,
o_edge_param03,
o_edge_param10,
o_edge_param11
`ifdef VTX_PARAM1_REDUCE
`else
,o_edge_param12,
o_edge_param13
`endif
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
// x,y init
input i_coord_valid;
input [20:0] i_start_x;
input [20:0] i_start_y;
input i_init_valid;
input [3:0] i_init_kind;
input [20:0] i_init_val;
// parameter update
input i_update_valid;
input [3:0] i_update_kind;
input [21:0] i_update_edge_val;
// parameter output
output [20:0] o_edge_x; //round
output [20:0] o_edge_y_float; // for end check
output [8:0] o_edge_y; // int
output [20:0] o_edge_z;
output [20:0] o_edge_iw;
output [20:0] o_edge_param00;
output [20:0] o_edge_param01;
output [20:0] o_edge_param02;
output [20:0] o_edge_param03;
output [20:0] o_edge_param10;
output [20:0] o_edge_param11;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_edge_param12;
output [20:0] o_edge_param13;
`endif
////////////////////////////
// reg
////////////////////////////
reg [20:0] r_edge_x;
reg [20:0] r_edge_y;
reg [20:0] r_edge_z;
reg [20:0] r_edge_iw;
reg [20:0] r_edge_param00;
reg [20:0] r_edge_param01;
reg [20:0] r_edge_param02;
reg [20:0] r_edge_param03;
reg [20:0] r_edge_param10;
reg [20:0] r_edge_param11;
`ifdef VTX_PARAM1_REDUCE
`else
reg [20:0] r_edge_param12;
reg [20:0] r_edge_param13;
`endif
////////////////////////////
// wire
////////////////////////////
wire w_set_init_z;
wire w_set_init_iw;
wire w_set_init_param00;
wire w_set_init_param01;
wire w_set_init_param02;
wire w_set_init_param03;
wire w_set_init_param10;
wire w_set_init_param11;
`ifdef VTX_PARAM1_REDUCE
`else
wire w_set_init_param12;
wire w_set_init_param13;
`endif
wire w_set_update_x;
wire w_set_update_y;
wire w_set_update_z;
wire w_set_update_iw;
wire w_set_update_param00;
wire w_set_update_param01;
wire w_set_update_param02;
wire w_set_update_param03;
wire w_set_update_param10;
wire w_set_update_param11;
`ifdef VTX_PARAM1_REDUCE
`else
wire w_set_update_param12;
wire w_set_update_param13;
`endif
wire [21:0] w_round_x;
wire [20:0] w_floor_x;
wire [15:0] w_iy;
////////////////////////////
// assign
////////////////////////////
assign w_set_update_x = i_update_valid & (i_update_kind == `FPARAM_X);
assign w_set_update_y = i_update_valid & (i_update_kind == `FPARAM_Y);
assign w_set_update_z = i_update_valid & (i_update_kind == `FPARAM_Z);
assign w_set_update_iw = i_update_valid &
(i_update_kind == `FPARAM_IW);
assign w_set_update_param00 = i_update_valid &
(i_update_kind == `FPARAM_P00);
assign w_set_update_param01 = i_update_valid &
(i_update_kind == `FPARAM_P01);
assign w_set_update_param02 = i_update_valid &
(i_update_kind == `FPARAM_P02);
assign w_set_update_param03 = i_update_valid &
(i_update_kind == `FPARAM_P03);
assign w_set_update_param10 = i_update_valid &
(i_update_kind == `FPARAM_P10);
assign w_set_update_param11 = i_update_valid &
(i_update_kind == `FPARAM_P11);
`ifdef VTX_PARAM1_REDUCE
`else
assign w_set_update_param12 = i_update_valid &
(i_update_kind == `FPARAM_P12);
assign w_set_update_param13 = i_update_valid &
(i_update_kind == `FPARAM_P13);
`endif
assign w_set_init_z = i_init_valid & (i_init_kind == `FPARAM_Z);
assign w_set_init_iw = i_init_valid &
(i_init_kind == `FPARAM_IW);
assign w_set_init_param00 = i_init_valid &
(i_init_kind == `FPARAM_P00);
assign w_set_init_param01 = i_init_valid &
(i_init_kind == `FPARAM_P01);
assign w_set_init_param02 = i_init_valid &
(i_init_kind == `FPARAM_P02);
assign w_set_init_param03 = i_init_valid &
(i_init_kind == `FPARAM_P03);
assign w_set_init_param10 = i_init_valid &
(i_init_kind == `FPARAM_P10);
assign w_set_init_param11 = i_init_valid &
(i_init_kind == `FPARAM_P11);
`ifdef VTX_PARAM1_REDUCE
`else
assign w_set_init_param12 = i_init_valid &
(i_init_kind == `FPARAM_P12);
assign w_set_init_param13 = i_init_valid &
(i_init_kind == `FPARAM_P13);
`endif
assign o_edge_x = w_floor_x;
assign o_edge_y = w_iy[8:0];
assign o_edge_y_float = r_edge_y;
assign o_edge_z = r_edge_z;
assign o_edge_iw = r_edge_iw;
assign o_edge_param00 = r_edge_param00;
assign o_edge_param01 = r_edge_param01;
assign o_edge_param02 = r_edge_param02;
assign o_edge_param03 = r_edge_param03;
assign o_edge_param10 = r_edge_param10;
assign o_edge_param11 = r_edge_param11;
`ifdef VTX_PARAM1_REDUCE
`else
assign o_edge_param12 = r_edge_param12;
assign o_edge_param13 = r_edge_param13;
`endif
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core) begin
if (w_set_update_x) r_edge_x <= i_update_edge_val[20:0];
else if (i_coord_valid) r_edge_x <= i_start_x;
if (w_set_update_y) r_edge_y <= i_update_edge_val[20:0];
else if (i_coord_valid) r_edge_y <= i_start_y;
if (w_set_update_z) r_edge_z <= i_update_edge_val[20:0];
else if (w_set_init_z) r_edge_z <= i_init_val[20:0];
if (w_set_update_iw) r_edge_iw <= i_update_edge_val[20:0];
else if (w_set_init_iw) r_edge_iw <= i_init_val[20:0];
if (w_set_update_param00) r_edge_param00 <= i_update_edge_val[20:0];
else if (w_set_init_param00) r_edge_param00 <= i_init_val[20:0];
if (w_set_update_param01) r_edge_param01 <= i_update_edge_val[20:0];
else if (w_set_init_param01) r_edge_param01 <= i_init_val[20:0];
if (w_set_update_param02) r_edge_param02 <= i_update_edge_val[20:0];
else if (w_set_init_param02) r_edge_param02 <= i_init_val[20:0];
if (w_set_update_param03) r_edge_param03 <= i_update_edge_val[20:0];
else if (w_set_init_param03) r_edge_param03 <= i_init_val[20:0];
if (w_set_update_param10) r_edge_param10 <= i_update_edge_val[20:0];
else if (w_set_init_param10) r_edge_param10 <= i_init_val[20:0];
if (w_set_update_param11) r_edge_param11 <= i_update_edge_val[20:0];
else if (w_set_init_param11) r_edge_param11 <= i_init_val[20:0];
`ifdef VTX_PARAM1_REDUCE
`else
if (w_set_update_param12) r_edge_param12 <= i_update_edge_val[20:0];
else if (w_set_init_param12) r_edge_param12 <= i_init_val[20:0];
if (w_set_update_param13) r_edge_param13 <= i_update_edge_val[20:0];
else if (w_set_init_param13) r_edge_param13 <= i_init_val[20:0];
`endif
end
////////////////////////////
// module instance
////////////////////////////
fm_3d_f22_floor f22_floor (
.i_a(r_edge_x),
.o_b(w_floor_x)
);
// ftoi for y
fm_3d_f22_to_ui ftoi_y (
.i_a({1'b0,r_edge_y}),
.o_b(w_iy)
);
endmodule
|
module fm_3d_fadd (
clk_core,
i_en,
i_a,
i_b,
i_adsb,
o_c
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input i_en;
input [21:0] i_a; // input A
input [21:0] i_b; // input B
input i_adsb; // 0 : A + B, 1 : A - B
output [21:0] o_c; // result
///////////////////////////////////////////
// register definition
///////////////////////////////////////////
reg [21:0] r_c; // result
reg r_sign_1z;
reg [4:0] r_exp_1z;
reg r_sign_2z;
reg [4:0] r_exp_2z;
reg [16:0] r_mats;
///////////////////////////////////////////
// wire
///////////////////////////////////////////
// input data separation
wire w_a_sign;
wire [15:0] w_a_fraction;
wire [4:0] w_a_exp;
wire w_b_sign;
wire [15:0] w_b_fraction;
wire [4:0] w_b_exp;
// intermidiate wire
wire w_mag_frac; // mag of fraction
wire w_mag_exp; // mag of exponent
wire [4:0] w_amb; // exp a - b
wire [4:0] w_bma; // exp b - a
wire [4:0] w_ex0; // larger exp - smaller exp
wire [4:0] w_exp_l; //
wire w_mag; // mag of A/B
wire [15:0] w_f0; // larger fraction
wire [15:0] w_f1_sa; // smaller fraction
wire [15:0] w_f1_sb; // smaller fraction
wire [15:0] w_f1t; // smaller fraction
wire w_sign; // sign bit
wire w_sub; // subtract frag
wire [16:0] w_mats; // result of ADD/SUB + carry
// finale result
wire [21:0] w_c;
///////////////////////////////////////////
// assign
///////////////////////////////////////////
// separate input
assign w_a_sign = i_a[21];
assign w_a_exp = i_a[20:16];
assign w_a_fraction = i_a[15:0];
assign w_b_sign = i_b[21];
assign w_b_exp = i_b[20:16];
assign w_b_fraction = i_b[15:0];
// output port
assign o_c = r_c;
////////////////////////////////////
// stage 0
///////////////////////////////////
assign w_mag_frac = (w_a_fraction <= w_b_fraction );
assign w_mag_exp = (w_a_exp <= w_b_exp );
assign w_exp_l = (w_mag_exp) ? w_b_exp : w_a_exp;
assign w_amb = w_a_exp - w_b_exp;
assign w_bma = w_b_exp - w_a_exp;
// larger exp - smaller exp
assign w_ex0 = (w_mag_exp) ? w_bma : w_amb;
assign w_mag = (w_ex0 == 4'b0) ? w_mag_frac : w_mag_exp;
// select larger/smaller fraction
assign w_f0 = (!w_mag) ? w_a_fraction : w_b_fraction;
// assign w_f1 = (!w_mag) ? w_b_fraction : w_a_fraction;
// A >= B : MAG = 0
// ADD : SUB :
// a + b a - b
// a - b a + b
// -a + b -a - b
// -a - b -a + b
// SGN = sign of a
//
// A < B : MAG = 1
// ADD : SUB :
// a + b a - b *
// a - b a + b *
// -a + b -a - b *
// -a - b -a + b *
// (sign of b) (sign of ~b)
// if (adsb ==1 ) then b is sign, else not b is sign
assign w_sign = ( w_mag == 1'b0) ? w_a_sign : (i_adsb ^ w_b_sign);
// adsb = 0(add) : a + -b or b + -a ( sub)
// adsb = 1(sub) : -a - -b or b - a
assign w_sub = ((w_a_sign ^ w_b_sign) & !i_adsb) |
(!(w_a_sign ^ w_b_sign) & i_adsb) ;
assign w_f1_sa = w_a_fraction >> w_ex0;
assign w_f1_sb = w_b_fraction >> w_ex0;
assign w_f1t = (w_mag) ? w_f1_sa : w_f1_sb;
////////////////////////////////////
// stage 1
///////////////////////////////////
reg r_sub;
reg [15:0] r_f0;
reg [15:0] r_f1t;
always @(posedge clk_core) begin
if (i_en) begin
r_sign_1z <= w_sign;
r_exp_1z <= w_exp_l;
r_sub <= w_sub;
r_f0 <= w_f0;
r_f1t <= w_f1t;
end
end
///////////////////////////////////////////
// stage 2
///////////////////////////////////////////
assign w_mats = (!r_sub) ? (r_f0 + r_f1t) : (r_f0 - r_f1t);
always @(posedge clk_core) begin
if (i_en) begin
r_sign_2z <= r_sign_1z;
r_exp_2z <= r_exp_1z;
r_mats <= w_mats;
end
end
///////////////////////////////////////////
// stage 3
///////////////////////////////////////////
// normalize
fm_3d_norm norm (
.i_s(r_sign_2z),
.i_e(r_exp_2z),
.i_f(r_mats),
.o_b(w_c)
);
always @(posedge clk_core) begin
if (i_en) r_c <= w_c;
end
endmodule
|
module fm_3d_ru_span_step (
clk_core,
rst_x,
// span parameter input
i_start,
o_finish,
i_delta_t,
// vertex parameters
i_x_l,
i_z_l,
i_iw_l,
i_param00_l,
i_param01_l,
i_param02_l,
i_param03_l,
i_param10_l,
i_param11_l,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_l,
i_param13_l,
`endif
i_z_r,
i_iw_r,
i_param00_r,
i_param01_r,
i_param02_r,
i_param03_r,
i_param10_r,
i_param11_r,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_r,
i_param13_r,
`endif
// control registers
i_param0_en,
i_param1_en,
i_param0_size,
i_param1_size,
// output
o_valid,
o_param_kind,
o_initial_val,
o_step_val,
o_end_flag,
i_busy
);
////////////////////////////
// parameter
////////////////////////////
parameter P_SETUP_IW = 4'h0;
parameter P_SETUP_X = 4'h1;
parameter P_SETUP_Z = 4'h2;
parameter P_SETUP_P00 = 4'h3;
parameter P_SETUP_P01 = 4'h4;
parameter P_SETUP_P02 = 4'h5;
parameter P_SETUP_P03 = 4'h6;
parameter P_SETUP_P10 = 4'h7;
parameter P_SETUP_P11 = 4'h8;
parameter P_SETUP_P12 = 4'h9;
parameter P_SETUP_P13 = 4'ha;
parameter P_SETUP_WAIT = 4'hb;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// outline parameter input
input i_start;
output o_finish;
input [21:0] i_delta_t;
// vertex parameters
input [20:0] i_x_l;
input [20:0] i_z_l;
input [20:0] i_iw_l;
input [20:0] i_param00_l;
input [20:0] i_param01_l;
input [20:0] i_param02_l;
input [20:0] i_param03_l;
input [20:0] i_param10_l;
input [20:0] i_param11_l;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_l;
input [20:0] i_param13_l;
`endif
input [20:0] i_z_r;
input [20:0] i_iw_r;
input [20:0] i_param00_r;
input [20:0] i_param01_r;
input [20:0] i_param02_r;
input [20:0] i_param03_r;
input [20:0] i_param10_r;
input [20:0] i_param11_r;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_r;
input [20:0] i_param13_r;
`endif
// control registers
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
// output
output o_valid;
output [3:0] o_param_kind;
output [21:0] o_initial_val;
output [21:0] o_step_val;
output o_end_flag;
input i_busy;
////////////////////////////
// reg
////////////////////////////
reg [3:0] r_state;
////////////////////////////
// wire
////////////////////////////
wire [20:0] w_end_p;
wire [20:0] w_start_p;
wire w_valid;
wire w_end_flag;
wire w_end_flag_z;
wire w_end_flag_p00;
wire w_end_flag_p01;
wire w_end_flag_p02;
wire w_end_flag_p03;
wire w_end_flag_p10;
wire w_end_flag_p11;
`ifdef VTX_PARAM1_REDUCE
`else
wire w_end_flag_p12;
wire w_end_flag_p13;
`endif
wire [3:0] w_param_kind;
wire w_finish;
wire w_busy;
////////////////////////////
// assign
////////////////////////////
assign w_busy = o_valid & i_busy;
assign o_finish = w_finish & !i_busy;
assign o_end_flag = w_finish;
assign w_valid= (r_state != P_SETUP_WAIT) &
((r_state != P_SETUP_IW) | ((r_state == P_SETUP_IW)&i_start));
assign w_end_flag_z = (r_state == P_SETUP_Z) & !i_param0_en & !i_param1_en;
assign w_end_flag_p00 = (r_state == P_SETUP_P00) &
(i_param0_en & (i_param0_size == 2'd0)) &
!i_param1_en;
assign w_end_flag_p01 = (r_state == P_SETUP_P01) &
(i_param0_size == 2'd1) & !i_param1_en;
assign w_end_flag_p02 = (r_state == P_SETUP_P02) &
(i_param0_size == 2'd2) & !i_param1_en;
assign w_end_flag_p03 = (r_state == P_SETUP_P03) & !i_param1_en;
assign w_end_flag_p10 = (r_state == P_SETUP_P10) & (i_param1_size == 2'd0);
assign w_end_flag_p11 = (r_state == P_SETUP_P11) & (i_param1_size == 2'd1);
`ifdef VTX_PARAM1_REDUCE
`else
assign w_end_flag_p12 = (r_state == P_SETUP_P11) & (i_param1_size == 2'd2);
assign w_end_flag_p13 = (r_state == P_SETUP_P11);
`endif
`ifdef VTX_PARAM1_REDUCE
assign w_end_flag = w_end_flag_z |
w_end_flag_p00 | w_end_flag_p01 | w_end_flag_p02 | w_end_flag_p03|
w_end_flag_p10 | w_end_flag_p11;
`else
assign w_end_flag = w_end_flag_z |
w_end_flag_p00 | w_end_flag_p01 | w_end_flag_p02 | w_end_flag_p03|
w_end_flag_p10 | w_end_flag_p11 | w_end_flag_p12 | w_end_flag_p03;
`endif
`ifdef VTX_PARAM1_REDUCE
assign w_start_p = (r_state == P_SETUP_IW) ? i_iw_l :
(r_state == P_SETUP_X) ? i_x_l :
(r_state == P_SETUP_Z) ? i_z_l :
(r_state == P_SETUP_P00) ? i_param00_l :
(r_state == P_SETUP_P01) ? i_param01_l :
(r_state == P_SETUP_P02) ? i_param02_l :
(r_state == P_SETUP_P03) ? i_param03_l :
(r_state == P_SETUP_P10) ? i_param10_l :
i_param11_l ;
assign w_end_p = (r_state == P_SETUP_IW) ? i_iw_r :
(r_state == P_SETUP_Z) ? i_z_r :
(r_state == P_SETUP_P00) ? i_param00_r :
(r_state == P_SETUP_P01) ? i_param01_r :
(r_state == P_SETUP_P02) ? i_param02_r :
(r_state == P_SETUP_P03) ? i_param03_r :
(r_state == P_SETUP_P10) ? i_param10_r :
i_param11_r ;
assign w_param_kind = (r_state == P_SETUP_IW) ? `FPARAM_IW :
(r_state == P_SETUP_X) ? `FPARAM_X :
(r_state == P_SETUP_Z) ? `FPARAM_Z :
(r_state == P_SETUP_P00) ? `FPARAM_P00 :
(r_state == P_SETUP_P01) ? `FPARAM_P01 :
(r_state == P_SETUP_P02) ? `FPARAM_P02 :
(r_state == P_SETUP_P03) ? `FPARAM_P03 :
(r_state == P_SETUP_P10) ? `FPARAM_P10 :
`FPARAM_P11 ;
`else
assign w_start_p = (r_state == P_SETUP_IW) ? i_iw_l :
(r_state == P_SETUP_X) ? i_x_l :
(r_state == P_SETUP_Z) ? i_z_l :
(r_state == P_SETUP_P00) ? i_param00_l :
(r_state == P_SETUP_P01) ? i_param01_l :
(r_state == P_SETUP_P02) ? i_param02_l :
(r_state == P_SETUP_P03) ? i_param03_l :
(r_state == P_SETUP_P10) ? i_param10_l :
(r_state == P_SETUP_P11) ? i_param11_l :
(r_state == P_SETUP_P12) ? i_param12_l :
i_param13_l;
assign w_end_p = (r_state == P_SETUP_IW) ? i_iw_r :
(r_state == P_SETUP_Z) ? i_z_r :
(r_state == P_SETUP_P00) ? i_param00_r :
(r_state == P_SETUP_P01) ? i_param01_r :
(r_state == P_SETUP_P02) ? i_param02_r :
(r_state == P_SETUP_P03) ? i_param03_r :
(r_state == P_SETUP_P10) ? i_param10_r :
(r_state == P_SETUP_P11) ? i_param11_r :
(r_state == P_SETUP_P12) ? i_param12_r :
i_param13_r;
assign w_param_kind = (r_state == P_SETUP_IW) ? `FPARAM_IW :
(r_state == P_SETUP_X) ? `FPARAM_X :
(r_state == P_SETUP_Z) ? `FPARAM_Z :
(r_state == P_SETUP_P00) ? `FPARAM_P00 :
(r_state == P_SETUP_P01) ? `FPARAM_P01 :
(r_state == P_SETUP_P02) ? `FPARAM_P02 :
(r_state == P_SETUP_P03) ? `FPARAM_P03 :
(r_state == P_SETUP_P10) ? `FPARAM_P10 :
(r_state == P_SETUP_P11) ? `FPARAM_P11 :
(r_state == P_SETUP_P12) ? `FPARAM_P12 :
`FPARAM_P13;
`endif
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_SETUP_IW;
end else begin
if (!w_busy) begin
case (r_state)
P_SETUP_IW: begin
if (i_start) r_state <= P_SETUP_X;
end
P_SETUP_X: begin
r_state <= P_SETUP_Z;
end
P_SETUP_Z: begin
if (i_param0_en) r_state <= P_SETUP_P00;
else if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end
P_SETUP_P00: begin
if (i_param0_size == 2'd0) begin
if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P01;
end
end
P_SETUP_P01: begin
if (i_param0_size == 2'd1) begin
if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P02;
end
end
P_SETUP_P02: begin
if (i_param0_size == 2'd2) begin
if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P03;
end
end
P_SETUP_P03: begin
if (i_param1_en) r_state <= P_SETUP_P10;
else r_state <= P_SETUP_WAIT;
end
P_SETUP_P10: begin
if (i_param1_size == 2'd0) begin
r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P11;
end
end
P_SETUP_P11: begin
if (i_param1_size == 2'd1) begin
r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P12;
end
end
P_SETUP_P12: begin
if (i_param1_size == 2'd2) begin
r_state <= P_SETUP_WAIT;
end else begin
r_state <= P_SETUP_P13;
end
end
P_SETUP_P13: begin
r_state <= P_SETUP_WAIT;
end
P_SETUP_WAIT: begin
if (o_finish) r_state <= P_SETUP_IW;
end
endcase
end
end
end
////////////////////////////
// module instance
////////////////////////////
fm_3d_ru_span_step_core span_step_core (
.clk_core(clk_core),
.rst_x(rst_x),
.i_en(!w_busy),
.i_valid(w_valid),
.i_kind(w_param_kind),
.i_end_flag(w_end_flag),
.i_start_p({1'b0,w_start_p}),
.i_end_p({1'b0,w_end_p}),
.i_delta_t(i_delta_t),
.o_valid(o_valid),
.o_kind(o_param_kind),
.o_end_flag(w_finish),
.o_start_p(o_initial_val),
.o_step_p(o_step_val)
);
endmodule
|
module fm_3d_ru_outline_update_core (
clk_core,
i_en,
i_valid,
i_kind,
i_end_flag,
i_cur_p,
i_initial_p,
i_step_p,
i_delta_a,
i_aa_mode,
o_valid,
o_kind,
o_end_flag,
o_initial_p,
o_step_p,
o_cur_p,
o_cur_edge_p
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input i_en;
input i_valid;
input [3:0] i_kind;
input i_end_flag;
input [21:0] i_cur_p;
input [20:0] i_initial_p;
input [21:0] i_step_p;
input [21:0] i_delta_a;
input i_aa_mode;
output o_valid;
output [3:0] o_kind;
output o_end_flag;
output [20:0] o_initial_p;
output [21:0] o_step_p;
output [21:0] o_cur_p;
output [21:0] o_cur_edge_p;
////////////////////////////
// wire
////////////////////////////
wire [21:0] w_cur_p;
wire [21:0] w_cur_pp;
wire [20:0] w_initial_p;
wire [21:0] w_adder_out;
wire [21:0] w_mul_out;
wire [21:0] w_adder_in_a;
wire [21:0] w_adder_in_aa;
wire [21:0] w_adder_in_bb;
////////////////////////////
// assign
////////////////////////////
assign w_adder_in_a = (i_aa_mode) ? w_mul_out : w_adder_out;
assign w_adder_in_aa = (i_aa_mode) ? w_mul_out : i_step_p;
assign w_adder_in_bb = (i_aa_mode) ? w_cur_p : i_cur_p;
assign o_cur_p = (i_aa_mode) ? w_adder_out : w_cur_pp;
////////////////////////////
// module instance
////////////////////////////
// step * delta
fm_3d_fmul mul_delta (
.clk_core(clk_core),
.i_en(i_en),
.i_a(i_step_p),
.i_b(i_delta_a),
.o_c(w_mul_out)
);
// step + delta
fm_3d_fadd fadd_cs (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_adder_in_aa),
.i_b(w_adder_in_bb),
.i_adsb(1'b0),
.o_c(w_adder_out)
);
// fmul/fadd delay adjust
fm_3d_delay #(22,3) delay_cur_p (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_cur_p),
.o_data(w_cur_p)
);
fm_3d_delay #(21,3) delay_initial_p (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_initial_p),
.o_data(w_initial_p)
);
fm_3d_delay #(1,6) delay_valid (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_valid),
.o_data(o_valid)
);
fm_3d_delay #(1,6) delay_end_flag (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_end_flag),
.o_data(o_end_flag)
);
fm_3d_delay #(4,6) delay_kind (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_kind),
.o_data(o_kind)
);
// adder (initialp + step*cur)
fm_3d_fadd fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_adder_in_a),
.i_b({1'b0,w_initial_p}),
.i_adsb(1'b0),
.o_c(o_cur_edge_p)
);
fm_3d_delay #(22,3) delay_cp (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_adder_out),
.o_data(w_cur_pp)
);
fm_3d_delay #(21,3) delay_initial_pp (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_initial_p),
.o_data(o_initial_p)
);
fm_3d_delay #(22,6) delay_step_pp (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_step_p),
.o_data(o_step_p)
);
endmodule
|
module fm_3d_f22_to_i8 (
clk_core,
i_en,
i_a,
o_b
);
///////////////////////////////////////////
// port definition
///////////////////////////////////////////
input clk_core;
input i_en;
input [21:0] i_a; // input s1, e5, f1.15
output [7:0] o_b; // unsigned integer
///////////////////////////////////////////
// wire definition
///////////////////////////////////////////
// intermidiate wire
wire w_sign;
wire [4:0] w_exp;
wire [15:0] w_fraction;
wire [21:0] w_255;
wire [21:0] w_c;
///////////////////////////////////////////
// assign statement
///////////////////////////////////////////
assign w_255 = 22'h16ff00;
assign w_sign = w_c[21];
assign w_exp = w_c[20:16];
assign w_fraction = w_c[15:0];
assign o_b = f_ftoi(w_exp, w_fraction);
///////////////////////////////////////////
// module instance
///////////////////////////////////////////
fm_3d_fmul u_fmul_255 (
.clk_core(clk_core),
.i_en(i_en),
.i_a(i_a),
.i_b(w_255),
.o_c(w_c)
);
///////////////////////////////////////////
// function statement
///////////////////////////////////////////
function [7:0] f_ftoi;
input [4:0] exp;
input [15:0] frac;
begin
case (exp)
5'd15: f_ftoi = {7'b0,frac[15]};
5'd16: f_ftoi = {6'b0,frac[15:14]};
5'd17: f_ftoi = {5'b0,frac[15:14]};
5'd18: f_ftoi = {4'b0,frac[15:12]};
5'd19: f_ftoi = {3'b0,frac[15:11]};
5'd20: f_ftoi = {2'b0,frac[15:10]};
5'd21: f_ftoi = {1'b0,frac[15:9]};
5'd22: f_ftoi = frac[15:8];
5'd23: f_ftoi = 8'd255; // overflow
default: f_ftoi = 8'h0; // including zero
endcase
end
endfunction
endmodule
|
module fm_3d_mu_cif (
clk_core,
rst_x,
// bus side port
i_bstr,
i_bdata,
o_back,
// internal port
o_istr,
o_idata,
i_iack
);
parameter P_WIDTH = 30;
////////////////////////////
// I/O definitions
////////////////////////////
input i_bstr; // input strobe
input [P_WIDTH-1:0]
i_bdata; // input data
output o_back; // output acknowledge
output o_istr; // output strobe
output [P_WIDTH-1:0]
o_idata; // output data
input i_iack; // input acknowledge
input clk_core; // system clock
input rst_x; // system reset
/////////////////////////
// register definition
/////////////////////////
// input register
reg r_bstr;
reg [P_WIDTH-1:0]
r_bdata;
/////////////////////////
// wire definition
/////////////////////////
/////////////////////////
// assign statement
/////////////////////////
assign o_istr = r_bstr;
assign o_idata = r_bdata;
assign o_back = i_iack;
/////////////////////////
// always statement
/////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_bstr <= 1'b0;
end else begin
if (i_iack) r_bstr <= i_bstr;
end
end
always @(posedge clk_core) begin
if (i_iack) r_bdata <= i_bdata;
end
endmodule
|
module fm_3d_ru_span_setup (
clk_core,
rst_x,
// span parameters
i_valid,
i_aa_mode,
i_x_l,
i_y_l,
i_z_l,
i_iw_l,
i_param00_l,
i_param01_l,
i_param02_l,
i_param03_l,
i_param10_l,
i_param11_l,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_l,
i_param13_l,
`endif
i_x_r,
i_y_r,
i_z_r,
i_iw_r,
i_param00_r,
i_param01_r,
i_param02_r,
i_param03_r,
i_param10_r,
i_param11_r,
`ifdef VTX_PARAM1_REDUCE
`else
i_param12_r,
i_param13_r,
`endif
o_ack,
// control registers
i_param0_en,
i_param1_en,
i_param0_size,
i_param1_size,
// idle state indicator
o_idle,
// update module interface
o_valid,
o_aa_mode,
o_kind,
o_initial_val,
o_step_val,
o_delta_a,
o_y,
o_end_flag,
o_end_x,
i_busy
);
////////////////////////////
// parameter
////////////////////////////
parameter P_IDLE = 2'h0;
parameter P_GEN_DELTA = 2'h1;
parameter P_GEN_STEP = 2'h2;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// span parameters
input i_valid;
input i_aa_mode;
input [20:0] i_x_l;
input [8:0] i_y_l;
input [20:0] i_z_l;
input [20:0] i_iw_l;
input [20:0] i_param00_l;
input [20:0] i_param01_l;
input [20:0] i_param02_l;
input [20:0] i_param03_l;
input [20:0] i_param10_l;
input [20:0] i_param11_l;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_l;
input [20:0] i_param13_l;
`endif
input [20:0] i_x_r;
input [8:0] i_y_r;
input [20:0] i_z_r;
input [20:0] i_iw_r;
input [20:0] i_param00_r;
input [20:0] i_param01_r;
input [20:0] i_param02_r;
input [20:0] i_param03_r;
input [20:0] i_param10_r;
input [20:0] i_param11_r;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_param12_r;
input [20:0] i_param13_r;
`endif
output o_ack;
// control registers
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
// idle state indicator
output o_idle;
// update module interface
output o_valid;
output o_aa_mode;
output [3:0] o_kind;
output [21:0] o_initial_val;
output [21:0] o_step_val;
output [21:0] o_delta_a;
output [8:0] o_y;
output o_end_flag;
output [20:0] o_end_x;
input i_busy;
////////////////////////////
// reg
////////////////////////////
reg [1:0] r_state;
reg r_aa_mode;
////////////////////////////
// wire
////////////////////////////
wire w_start_delta;
wire w_start_step;
wire w_finish_delta;
wire w_finish_step;
wire [21:0] w_delta_t;
////////////////////////////
// assign
////////////////////////////
assign w_start_delta = (r_state == P_IDLE) & i_valid;
assign w_start_step = (r_state == P_GEN_DELTA) & w_finish_delta;
assign o_y = i_y_l;
assign o_end_x = i_x_r;
assign o_ack = w_finish_step & (r_state == P_GEN_STEP);
assign o_idle = (r_state == P_IDLE);
assign o_aa_mode = r_aa_mode;
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (i_valid) r_state <= P_GEN_DELTA;
end
P_GEN_DELTA: begin // gen setps
if (w_finish_delta) r_state <= P_GEN_STEP;
end
P_GEN_STEP: begin
if (w_finish_step) r_state <= P_IDLE;
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_aa_mode <= 1'b0;
end else begin
if (w_start_delta) r_aa_mode <= i_aa_mode;
end
end
////////////////////////////
// module instance
////////////////////////////
fm_3d_ru_span_delta span_delta (
.clk_core(clk_core),
.rst_x(rst_x),
// span parameters
.i_start(w_start_delta),
.o_finish(w_finish_delta),
.i_x_l(i_x_l),
.i_x_r(i_x_r),
// generated parameters
.o_delta_t(w_delta_t),
.o_delta_a(o_delta_a)
);
fm_3d_ru_span_step span_step (
.clk_core(clk_core),
.rst_x(rst_x),
// span parameter input
.i_start(w_start_step),
.o_finish(w_finish_step),
.i_delta_t(w_delta_t),
// vertex parameters
.i_x_l(i_x_l),
.i_z_l(i_z_l),
.i_iw_l(i_iw_l),
.i_param00_l(i_param00_l),
.i_param01_l(i_param01_l),
.i_param02_l(i_param02_l),
.i_param03_l(i_param03_l),
.i_param10_l(i_param10_l),
.i_param11_l(i_param11_l),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_l(i_param12_l),
.i_param13_l(i_param13_l),
`endif
.i_z_r(i_z_r),
.i_iw_r(i_iw_r),
.i_param00_r(i_param00_r),
.i_param01_r(i_param01_r),
.i_param02_r(i_param02_r),
.i_param03_r(i_param03_r),
.i_param10_r(i_param10_r),
.i_param11_r(i_param11_r),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_r(i_param12_r),
.i_param13_r(i_param13_r),
`endif
// control registers
.i_param0_en(i_param0_en),
.i_param1_en(i_param1_en),
.i_param0_size(i_param0_size),
.i_param1_size(i_param1_size),
// output
.o_valid(o_valid),
.o_param_kind(o_kind),
.o_initial_val(o_initial_val),
.o_step_val(o_step_val),
.o_end_flag(o_end_flag),
.i_busy(i_busy)
);
endmodule
|
module fm_3d_frcp_rom (
clk_core,
i_a,
o_c
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input [6:0] i_a;
output [31:0] o_c;
////////////////////////////
// reg
////////////////////////////
(*rom_style="distributed" *) reg [31:0] r_c;
////////////////////////////
// assign
////////////////////////////
assign o_c = r_c;
///////////////////////////////////////////
// always statement
///////////////////////////////////////////
always @(posedge clk_core) begin
(* parallel_case *) case (i_a)
7'd0: r_c <= 32'h800001fc;
7'd1: r_c <= 32'h7f0101f4;
7'd2: r_c <= 32'h7e0701ec;
7'd3: r_c <= 32'h7d1101e5;
7'd4: r_c <= 32'h7c1f01dd;
7'd5: r_c <= 32'h7b3001d6;
7'd6: r_c <= 32'h7a4401cf;
7'd7: r_c <= 32'h795c01c8;
7'd8: r_c <= 32'h787801c2;
7'd9: r_c <= 32'h779701bb;
7'd10: r_c <= 32'h76b901b5;
7'd11: r_c <= 32'h75de01af;
7'd12: r_c <= 32'h750701a8;
7'd13: r_c <= 32'h743201a2;
7'd14: r_c <= 32'h7361019d;
7'd15: r_c <= 32'h72920197;
7'd16: r_c <= 32'h71c70191;
7'd17: r_c <= 32'h70fe018c;
7'd18: r_c <= 32'h70380186;
7'd19: r_c <= 32'h6f740181;
7'd20: r_c <= 32'h6eb3017c;
7'd21: r_c <= 32'h6df50177;
7'd22: r_c <= 32'h6d3a0172;
7'd23: r_c <= 32'h6c80016d;
7'd24: r_c <= 32'h6bca0168;
7'd25: r_c <= 32'h6b150164;
7'd26: r_c <= 32'h6a63015f;
7'd27: r_c <= 32'h69b4015a;
7'd28: r_c <= 32'h69060156;
7'd29: r_c <= 32'h685b0152;
7'd30: r_c <= 32'h67b2014d;
7'd31: r_c <= 32'h670b0149;
7'd32: r_c <= 32'h66660145;
7'd33: r_c <= 32'h65c30141;
7'd34: r_c <= 32'h6522013d;
7'd35: r_c <= 32'h64830139;
7'd36: r_c <= 32'h63e70136;
7'd37: r_c <= 32'h634c0132;
7'd38: r_c <= 32'h62b2012e;
7'd39: r_c <= 32'h621b012a;
7'd40: r_c <= 32'h61860127;
7'd41: r_c <= 32'h60f20123;
7'd42: r_c <= 32'h60600120;
7'd43: r_c <= 32'h5fd0011d;
7'd44: r_c <= 32'h5f410119;
7'd45: r_c <= 32'h5eb40116;
7'd46: r_c <= 32'h5e290113;
7'd47: r_c <= 32'h5d9f0110;
7'd48: r_c <= 32'h5d17010d;
7'd49: r_c <= 32'h5c90010a;
7'd50: r_c <= 32'h5c0b0107;
7'd51: r_c <= 32'h5b870104;
7'd52: r_c <= 32'h5b050101;
7'd53: r_c <= 32'h5a8400fe;
7'd54: r_c <= 32'h5a0500fb;
7'd55: r_c <= 32'h598700f9;
7'd56: r_c <= 32'h590b00f6;
7'd57: r_c <= 32'h588f00f3;
7'd58: r_c <= 32'h581600f1;
7'd59: r_c <= 32'h579d00ee;
7'd60: r_c <= 32'h572600ec;
7'd61: r_c <= 32'h56b000e9;
7'd62: r_c <= 32'h563b00e7;
7'd63: r_c <= 32'h55c700e4;
7'd64: r_c <= 32'h555500e2;
7'd65: r_c <= 32'h54e400e0;
7'd66: r_c <= 32'h547400dd;
7'd67: r_c <= 32'h540500db;
7'd68: r_c <= 32'h539700d9;
7'd69: r_c <= 32'h532a00d7;
7'd70: r_c <= 32'h52bf00d4;
7'd71: r_c <= 32'h525400d2;
7'd72: r_c <= 32'h51eb00d0;
7'd73: r_c <= 32'h518300ce;
7'd74: r_c <= 32'h511b00cc;
7'd75: r_c <= 32'h50b500ca;
7'd76: r_c <= 32'h505000c8;
7'd77: r_c <= 32'h4fec00c6;
7'd78: r_c <= 32'h4f8800c4;
7'd79: r_c <= 32'h4f2600c2;
7'd80: r_c <= 32'h4ec400c0;
7'd81: r_c <= 32'h4e6400bf;
7'd82: r_c <= 32'h4e0400bd;
7'd83: r_c <= 32'h4da600bb;
7'd84: r_c <= 32'h4d4800b9;
7'd85: r_c <= 32'h4ceb00b8;
7'd86: r_c <= 32'h4c8f00b6;
7'd87: r_c <= 32'h4c3400b4;
7'd88: r_c <= 32'h4bda00b2;
7'd89: r_c <= 32'h4b8000b1;
7'd90: r_c <= 32'h4b2700af;
7'd91: r_c <= 32'h4ad000ae;
7'd92: r_c <= 32'h4a7900ac;
7'd93: r_c <= 32'h4a2200aa;
7'd94: r_c <= 32'h49cd00a9;
7'd95: r_c <= 32'h497800a7;
7'd96: r_c <= 32'h492400a6;
7'd97: r_c <= 32'h48d100a4;
7'd98: r_c <= 32'h487e00a3;
7'd99: r_c <= 32'h482d00a2;
7'd100: r_c <= 32'h47dc00a0;
7'd101: r_c <= 32'h478b009f;
7'd102: r_c <= 32'h473c009d;
7'd103: r_c <= 32'h46ed009c;
7'd104: r_c <= 32'h469e009b;
7'd105: r_c <= 32'h46510099;
7'd106: r_c <= 32'h46040098;
7'd107: r_c <= 32'h45b80097;
7'd108: r_c <= 32'h456c0095;
7'd109: r_c <= 32'h45210094;
7'd110: r_c <= 32'h44d70093;
7'd111: r_c <= 32'h448d0092;
7'd112: r_c <= 32'h44440091;
7'd113: r_c <= 32'h43fb008f;
7'd114: r_c <= 32'h43b3008e;
7'd115: r_c <= 32'h436c008d;
7'd116: r_c <= 32'h4325008c;
7'd117: r_c <= 32'h42df008b;
7'd118: r_c <= 32'h429a008a;
7'd119: r_c <= 32'h42540088;
7'd120: r_c <= 32'h42100087;
7'd121: r_c <= 32'h41cc0086;
7'd122: r_c <= 32'h41890085;
7'd123: r_c <= 32'h41460084;
7'd124: r_c <= 32'h41040083;
7'd125: r_c <= 32'h40c20082;
7'd126: r_c <= 32'h40810081;
7'd127: r_c <= 32'h40400080;
default: r_c <= 32'h0;
endcase
end
endmodule
|
module fm_3d_tu_etc (
clk_core,
i_u_sub,
i_v_sub,
i_code_l32,
i_code_u32,
o_r,
o_g,
o_b
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input [1:0] i_u_sub;
input [1:0] i_v_sub;
input [31:0] i_code_l32;
input [31:0] i_code_u32;
output [7:0] o_r;
output [7:0] o_g;
output [7:0] o_b;
////////////////////////////
// reg
////////////////////////////
reg [7:0] r_cr_1z;
reg [7:0] r_cg_1z;
reg [7:0] r_cb_1z;
////////////////////////////
// wire
////////////////////////////
wire [1:0] w_idx0;
wire [1:0] w_idx1;
wire [1:0] w_idx2;
wire [1:0] w_idx3;
wire [1:0] w_idx4;
wire [1:0] w_idx5;
wire [1:0] w_idx6;
wire [1:0] w_idx7;
wire [1:0] w_idx8;
wire [1:0] w_idx9;
wire [1:0] w_idx10;
wire [1:0] w_idx11;
wire [1:0] w_idx12;
wire [1:0] w_idx13;
wire [1:0] w_idx14;
wire [1:0] w_idx15;
wire w_flip_bit;
wire w_diff_bit;
wire [2:0] w_tc1;
wire [2:0] w_tc2;
wire [3:0] w_r1_4bits;
wire [3:0] w_r2_4bits;
wire [3:0] w_g1_4bits;
wire [3:0] w_g2_4bits;
wire [3:0] w_b1_4bits;
wire [3:0] w_b2_4bits;
wire [4:0] w_r1_5bits;
wire [4:0] w_r2_5bits;
wire [2:0] w_r2_delta;
wire [4:0] w_g1_5bits;
wire [4:0] w_g2_5bits;
wire [2:0] w_g2_delta;
wire [4:0] w_b1_5bits;
wire [4:0] w_b2_5bits;
wire [2:0] w_b2_delta;
wire [7:0] w_r1_8bits;
wire [7:0] w_r2_8bits;
wire [7:0] w_g1_8bits;
wire [7:0] w_g2_8bits;
wire [7:0] w_b1_8bits;
wire [7:0] w_b2_8bits;
wire [3:0] w_idx;
wire [1:0] w_tbl_idx;
wire [7:0] w_r;
wire [7:0] w_g;
wire [7:0] w_b;
wire [4:0] w_rom_adrs;
wire [8:0] w_rom_out;
wire [8:0] w_cr_t;
wire [8:0] w_cg_t;
wire [8:0] w_cb_t;
wire w_select1;
////////////////////////////
// assign
////////////////////////////
// pixel index
assign w_idx0 = {i_code_l32[16],i_code_l32[0]};
assign w_idx1 = {i_code_l32[17],i_code_l32[1]};
assign w_idx2 = {i_code_l32[18],i_code_l32[2]};
assign w_idx3 = {i_code_l32[19],i_code_l32[3]};
assign w_idx4 = {i_code_l32[20],i_code_l32[4]};
assign w_idx5 = {i_code_l32[21],i_code_l32[5]};
assign w_idx6 = {i_code_l32[22],i_code_l32[6]};
assign w_idx7 = {i_code_l32[23],i_code_l32[7]};
assign w_idx8 = {i_code_l32[24],i_code_l32[8]};
assign w_idx9 = {i_code_l32[25],i_code_l32[9]};
assign w_idx10 = {i_code_l32[26],i_code_l32[10]};
assign w_idx11 = {i_code_l32[27],i_code_l32[11]};
assign w_idx12 = {i_code_l32[28],i_code_l32[12]};
assign w_idx13 = {i_code_l32[29],i_code_l32[13]};
assign w_idx14 = {i_code_l32[30],i_code_l32[14]};
assign w_idx15 = {i_code_l32[31],i_code_l32[15]};
assign w_flip_bit = i_code_u32[0];
assign w_diff_bit = i_code_u32[1];
assign w_tc2 = i_code_u32[4:2];
assign w_tc1 = i_code_u32[7:5];
// color 4:4:4
assign w_b2_4bits = i_code_u32[11:8];
assign w_b1_4bits = i_code_u32[15:12];
assign w_g2_4bits = i_code_u32[19:16];
assign w_g1_4bits = i_code_u32[23:20];
assign w_r2_4bits = i_code_u32[27:24];
assign w_r1_4bits = i_code_u32[31:28];
// color 5:5:5
assign w_b2_delta = i_code_u32[10:8];
assign w_b1_5bits = i_code_u32[15:11];
assign w_b2_5bits = f_apply_diff_b(w_b1_5bits,w_b2_delta);
assign w_g2_delta = i_code_u32[18:16];
assign w_g1_5bits = i_code_u32[23:19];
assign w_g2_5bits = f_apply_diff_g(w_g1_5bits,w_g2_delta);
assign w_r2_delta = i_code_u32[26:24];
assign w_r1_5bits = i_code_u32[31:27];
assign w_r2_5bits = f_apply_diff_r(w_r1_5bits,w_r2_delta);
assign w_r1_8bits = (w_diff_bit) ? {w_r1_5bits,w_r1_5bits[4:2]} :
{w_r1_4bits,w_r1_4bits};
assign w_r2_8bits = (w_diff_bit) ? {w_r2_5bits,w_r2_5bits[4:2]} :
{w_r2_4bits,w_r2_4bits};
assign w_g1_8bits = (w_diff_bit) ? {w_g1_5bits,w_g1_5bits[4:2]} :
{w_g1_4bits,w_g1_4bits};
assign w_g2_8bits = (w_diff_bit) ? {w_g2_5bits,w_g2_5bits[4:2]} :
{w_g2_4bits,w_g2_4bits};
assign w_b1_8bits = (w_diff_bit) ? {w_b1_5bits,w_b1_5bits[4:2]} :
{w_b1_4bits,w_b1_4bits};
assign w_b2_8bits = (w_diff_bit) ? {w_b2_5bits,w_b2_5bits[4:2]} :
{w_b2_4bits,w_b2_4bits};
assign w_idx = {i_u_sub,i_v_sub};
assign w_tbl_idx = (w_idx == 4'd0) ? w_idx0 :
(w_idx == 4'd1) ? w_idx1 :
(w_idx == 4'd2) ? w_idx2 :
(w_idx == 4'd3) ? w_idx3 :
(w_idx == 4'd4) ? w_idx4 :
(w_idx == 4'd5) ? w_idx5 :
(w_idx == 4'd6) ? w_idx6 :
(w_idx == 4'd7) ? w_idx7 :
(w_idx == 4'd8) ? w_idx8 :
(w_idx == 4'd9) ? w_idx9 :
(w_idx == 4'd10) ? w_idx10 :
(w_idx == 4'd11) ? w_idx11 :
(w_idx == 4'd12) ? w_idx12 :
(w_idx == 4'd13) ? w_idx13 :
(w_idx == 4'd14) ? w_idx14 :
w_idx15;
assign w_select1 = (w_flip_bit & !i_v_sub[1]) |
(!w_flip_bit & !i_u_sub[1]);
assign w_rom_adrs = (w_select1) ? {w_tc1,w_tbl_idx} : {w_tc2,w_tbl_idx};
assign w_r = (w_select1) ? w_r1_8bits : w_r2_8bits;
assign w_g = (w_select1) ? w_g1_8bits : w_g2_8bits;
assign w_b = (w_select1) ? w_b1_8bits : w_b2_8bits;
assign w_cr_t = {1'b0,r_cr_1z} + w_rom_out;
assign o_r = (!w_cr_t[8]) ? w_cr_t[7:0] :
(w_rom_out[8]) ? 8'h00: 8'hff;
assign w_cg_t = {1'b0,r_cg_1z} + w_rom_out;
assign o_g = (!w_cg_t[8]) ? w_cg_t[7:0] :
(w_rom_out[8]) ? 8'h00: 8'hff;
assign w_cb_t = {1'b0,r_cb_1z} + w_rom_out;
assign o_b = (!w_cb_t[8]) ? w_cb_t[7:0] :
(w_rom_out[8]) ? 8'h00: 8'hff;
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core) begin
r_cr_1z <= w_r;
r_cg_1z <= w_g;
r_cb_1z <= w_b;
end
////////////////////////////
// function
////////////////////////////
function [4:0] f_apply_diff_r;
input [4:0] c1;
input [2:0] diff;
reg [5:0] tmp;
begin
tmp = c1 + {diff[2],diff[2],diff}; // sign extension
if (tmp[5]) begin
// over-flow
f_apply_diff_r = (diff[2]) ? tmp[4:0] : 5'h1f;
end else begin
// under-flow
f_apply_diff_r = (diff[2]) ? 5'h00: tmp[4:0];
end
end
endfunction
function [4:0] f_apply_diff_g;
input [4:0] c1;
input [2:0] diff;
reg [5:0] tmp;
begin
tmp = c1 + {diff[2],diff[2],diff}; // sign extension
if (tmp[5]) begin
// over-flow
f_apply_diff_g = (diff[2]) ? tmp[4:0] : 5'h1f;
end else begin
// under-flow
f_apply_diff_g = (diff[2]) ? 5'h00: tmp[4:0];
end
end
endfunction
function [4:0] f_apply_diff_b;
input [4:0] c1;
input [2:0] diff;
reg [5:0] tmp;
begin
tmp = c1 + {diff[2],diff[2],diff}; // sign extension
if (tmp[5]) begin
// over-flow
f_apply_diff_b = (diff[2]) ? tmp[4:0] : 5'h1f;
end else begin
// under-flow
f_apply_diff_b = (diff[2]) ? 5'h00: tmp[4:0];
end
end
endfunction
////////////////////////////
// module instance
////////////////////////////
fm_3d_tu_etc_rom tu_etc_rom (
.clk_core(clk_core),
.i_a(w_rom_adrs),
.o_c(w_rom_out)
);
endmodule
|
module fm_3d_ru_outline_edge_ctrl (
clk_core,
rst_x,
// outline parameters
i_valid,
i_ml,
i_is_first,
i_is_second,
// idle state indicator
o_idle,
// edge0
i_start_x_e0,
i_start_x_05_e0,
i_start_y_e0,
i_end_y_e0,
i_delta_e0,
i_delta_t_e0,
i_delta_a_e0,
// edge1
i_start_x_e1,
i_start_x_05_e1,
i_start_y_e1,
i_end_y_e1,
i_delta_e1,
i_delta_t_e1,
i_delta_a_e1,
// edge2
i_start_x_e2,
i_start_x_05_e2,
i_start_y_e2,
i_end_y_e2,
i_delta_e2,
i_delta_t_e2,
i_delta_a_e2,
o_ack,
// triangle data
i_vtx0_z,
i_vtx0_iw,
i_vtx0_p00,
i_vtx0_p01,
i_vtx0_p02,
i_vtx0_p03,
i_vtx0_p10,
i_vtx0_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx0_p12,
i_vtx0_p13,
`endif
i_vtx1_z,
i_vtx1_iw,
i_vtx1_p00,
i_vtx1_p01,
i_vtx1_p02,
i_vtx1_p03,
i_vtx1_p10,
i_vtx1_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx1_p12,
i_vtx1_p13,
`endif
i_vtx2_z,
i_vtx2_iw,
i_vtx2_p00,
i_vtx2_p01,
i_vtx2_p02,
i_vtx2_p03,
i_vtx2_p10,
i_vtx2_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx2_p12,
i_vtx2_p13,
`endif
// control flag
o_has_bottom,
// left edge data out
o_valid_l,
o_start_x_l,
o_start_x_05_l,
o_start_y_l,
o_end_y_l,
o_delta_l,
o_delta_t_l,
o_delta_a_l,
i_ack_l,
// left vertex parameters
o_z_s_l,
o_iw_s_l,
o_p00_s_l,
o_p01_s_l,
o_p02_s_l,
o_p03_s_l,
o_p10_s_l,
o_p11_s_l,
`ifdef VTX_PARAM1_REDUCE
`else
o_p12_s_l,
o_p13_s_l,
`endif
o_z_e_l,
o_iw_e_l,
o_p00_e_l,
o_p01_e_l,
o_p02_e_l,
o_p03_e_l,
o_p10_e_l,
o_p11_e_l,
`ifdef VTX_PARAM1_REDUCE
`else
o_p12_e_l,
o_p13_e_l,
`endif
// right edge data out
o_valid_r,
o_start_x_r,
o_start_x_05_r,
o_start_y_r,
o_end_y_r,
o_delta_r,
o_delta_t_r,
o_delta_a_r,
i_ack_r,
// right vertex parameters
o_z_s_r,
o_iw_s_r,
o_p00_s_r,
o_p01_s_r,
o_p02_s_r,
o_p03_s_r,
o_p10_s_r,
o_p11_s_r,
`ifdef VTX_PARAM1_REDUCE
`else
o_p12_s_r,
o_p13_s_r,
`endif
o_z_e_r,
o_iw_e_r,
o_p00_e_r,
o_p01_e_r,
o_p02_e_r,
o_p03_e_r,
o_p10_e_r,
o_p11_e_r
`ifdef VTX_PARAM1_REDUCE
`else
,o_p12_e_r,
o_p13_e_r
`endif
);
////////////////////////////
// parameter
////////////////////////////
parameter P_IDLE = 2'b00;
parameter P_FIRST_TRI = 2'b01;
parameter P_SECOND_TRI = 2'b10;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// outline parameters
input i_valid;
input i_ml;
input i_is_first;
input i_is_second;
// idle state indicator
output o_idle;
// edge0
input [20:0] i_start_x_e0;
input [20:0] i_start_x_05_e0;
input [20:0] i_start_y_e0;
input [20:0] i_end_y_e0;
input [21:0] i_delta_e0;
input [21:0] i_delta_t_e0;
input [21:0] i_delta_a_e0;
// edge1
input [20:0] i_start_x_e1;
input [20:0] i_start_x_05_e1;
input [20:0] i_start_y_e1;
input [20:0] i_end_y_e1;
input [21:0] i_delta_e1;
input [21:0] i_delta_t_e1;
input [21:0] i_delta_a_e1;
// edge2
input [20:0] i_start_x_e2;
input [20:0] i_start_x_05_e2;
input [20:0] i_start_y_e2;
input [20:0] i_end_y_e2;
input [21:0] i_delta_e2;
input [21:0] i_delta_t_e2;
input [21:0] i_delta_a_e2;
output o_ack;
// triangle data
input [20:0] i_vtx0_z;
input [20:0] i_vtx0_iw;
input [20:0] i_vtx0_p00;
input [20:0] i_vtx0_p01;
input [20:0] i_vtx0_p02;
input [20:0] i_vtx0_p03;
input [20:0] i_vtx0_p10;
input [20:0] i_vtx0_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx0_p12;
input [20:0] i_vtx0_p13;
`endif
input [20:0] i_vtx1_z;
input [20:0] i_vtx1_iw;
input [20:0] i_vtx1_p00;
input [20:0] i_vtx1_p01;
input [20:0] i_vtx1_p02;
input [20:0] i_vtx1_p03;
input [20:0] i_vtx1_p10;
input [20:0] i_vtx1_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx1_p12;
input [20:0] i_vtx1_p13;
`endif
input [20:0] i_vtx2_z;
input [20:0] i_vtx2_iw;
input [20:0] i_vtx2_p00;
input [20:0] i_vtx2_p01;
input [20:0] i_vtx2_p02;
input [20:0] i_vtx2_p03;
input [20:0] i_vtx2_p10;
input [20:0] i_vtx2_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx2_p12;
input [20:0] i_vtx2_p13;
`endif
// control flag
output o_has_bottom;
// left edge data out
output o_valid_l;
output [20:0] o_start_x_l;
output [20:0] o_start_x_05_l;
output [20:0] o_start_y_l;
output [20:0] o_end_y_l;
output [21:0] o_delta_l;
output [21:0] o_delta_t_l;
output [21:0] o_delta_a_l;
input i_ack_l;
// left vertex parameters
output [20:0] o_z_s_l;
output [20:0] o_iw_s_l;
output [20:0] o_p00_s_l;
output [20:0] o_p01_s_l;
output [20:0] o_p02_s_l;
output [20:0] o_p03_s_l;
output [20:0] o_p10_s_l;
output [20:0] o_p11_s_l;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_p12_s_l;
output [20:0] o_p13_s_l;
`endif
output [20:0] o_z_e_l;
output [20:0] o_iw_e_l;
output [20:0] o_p00_e_l;
output [20:0] o_p01_e_l;
output [20:0] o_p02_e_l;
output [20:0] o_p03_e_l;
output [20:0] o_p10_e_l;
output [20:0] o_p11_e_l;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_p12_e_l;
output [20:0] o_p13_e_l;
`endif
// right edge data out
output o_valid_r;
output [20:0] o_start_x_r;
output [20:0] o_start_x_05_r;
output [20:0] o_start_y_r;
output [20:0] o_end_y_r;
output [21:0] o_delta_r;
output [21:0] o_delta_t_r;
output [21:0] o_delta_a_r;
input i_ack_r;
// righr vertex parameters
output [20:0] o_z_s_r;
output [20:0] o_iw_s_r;
output [20:0] o_p00_s_r;
output [20:0] o_p01_s_r;
output [20:0] o_p02_s_r;
output [20:0] o_p03_s_r;
output [20:0] o_p10_s_r;
output [20:0] o_p11_s_r;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_p12_s_r;
output [20:0] o_p13_s_r;
`endif
output [20:0] o_z_e_r;
output [20:0] o_iw_e_r;
output [20:0] o_p00_e_r;
output [20:0] o_p01_e_r;
output [20:0] o_p02_e_r;
output [20:0] o_p03_e_r;
output [20:0] o_p10_e_r;
output [20:0] o_p11_e_r;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_p12_e_r;
output [20:0] o_p13_e_r;
`endif
////////////////////////////
// reg
////////////////////////////
reg [1:0] r_state;
////////////////////////////
// wire
////////////////////////////
wire [20:0] w_start_x_fs;
wire [20:0] w_start_x_05_fs;
wire [20:0] w_start_y_fs;
wire [20:0] w_end_y_fs;
wire [21:0] w_delta_fs;
wire [21:0] w_delta_t_fs;
wire [21:0] w_delta_a_fs;
wire [20:0] w_z_s_fs;
wire [20:0] w_iw_s_fs;
wire [20:0] w_p00_s_fs;
wire [20:0] w_p01_s_fs;
wire [20:0] w_p02_s_fs;
wire [20:0] w_p03_s_fs;
wire [20:0] w_p10_s_fs;
wire [20:0] w_p11_s_fs;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_p12_s_fs;
wire [20:0] w_p13_s_fs;
`endif
wire [20:0] w_z_e_fs;
wire [20:0] w_iw_e_fs;
wire [20:0] w_p00_e_fs;
wire [20:0] w_p01_e_fs;
wire [20:0] w_p02_e_fs;
wire [20:0] w_p03_e_fs;
wire [20:0] w_p10_e_fs;
wire [20:0] w_p11_e_fs;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_p12_e_fs;
wire [20:0] w_p13_e_fs;
`endif
////////////////////////////
// assign
////////////////////////////
// first/second selection
assign w_start_x_fs = (r_state == P_FIRST_TRI) ? i_start_x_e1 : i_start_x_e2;
assign w_start_x_05_fs = (r_state == P_FIRST_TRI) ? i_start_x_05_e1 : i_start_x_05_e2;
assign w_start_y_fs = (r_state == P_FIRST_TRI) ? i_start_y_e1 : i_start_y_e2;
assign w_end_y_fs = (r_state == P_FIRST_TRI) ? i_end_y_e1 : i_end_y_e2;
assign w_delta_fs = (r_state == P_FIRST_TRI) ? i_delta_e1 : i_delta_e2;
assign w_delta_t_fs = (r_state == P_FIRST_TRI) ? i_delta_t_e1 : i_delta_t_e2;
assign w_delta_a_fs = (r_state == P_FIRST_TRI) ? i_delta_a_e1 : i_delta_a_e2;
assign w_z_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_z : i_vtx1_z;
assign w_iw_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_iw : i_vtx1_iw;
assign w_p00_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_p00 : i_vtx1_p00;
assign w_p01_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_p01 : i_vtx1_p01;
assign w_p02_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_p02 : i_vtx1_p02;
assign w_p03_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_p03 : i_vtx1_p03;
assign w_p10_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_p10 : i_vtx1_p10;
assign w_p11_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_p11 : i_vtx1_p11;
`ifdef VTX_PARAM1_REDUCE
`else
assign w_p12_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_p12 : i_vtx1_p12;
assign w_p13_s_fs = (r_state == P_FIRST_TRI) ? i_vtx2_p13 : i_vtx1_p13;
`endif
assign w_z_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_z : i_vtx0_z;
assign w_iw_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_iw : i_vtx0_iw;
assign w_p00_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_p00 : i_vtx0_p00;
assign w_p01_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_p01 : i_vtx0_p01;
assign w_p02_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_p02 : i_vtx0_p02;
assign w_p03_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_p03 : i_vtx0_p03;
assign w_p10_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_p10 : i_vtx0_p10;
assign w_p11_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_p11 : i_vtx0_p11;
`ifdef VTX_PARAM1_REDUCE
`else
assign w_p12_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_p12 : i_vtx0_p12;
assign w_p13_e_fs = (r_state == P_FIRST_TRI) ? i_vtx1_p13 : i_vtx0_p13;
`endif
// left edge data out
assign o_valid_l = (r_state != P_IDLE);
assign o_start_x_l = (!i_ml) ? i_start_x_e0 : w_start_x_fs;
assign o_start_x_05_l = (!i_ml) ? i_start_x_05_e0 : w_start_x_05_fs;
assign o_start_y_l = (!i_ml) ? i_start_y_e0 : w_start_y_fs;
assign o_end_y_l = (!i_ml) ? i_end_y_e0 : w_end_y_fs;
assign o_delta_l = (!i_ml) ? i_delta_e0 : w_delta_fs;
assign o_delta_t_l = (!i_ml) ? i_delta_t_e0 : w_delta_t_fs;
assign o_delta_a_l = (!i_ml) ? i_delta_a_e0 : w_delta_a_fs;
// right edge data out
assign o_valid_r = (r_state != P_IDLE);
assign o_start_x_r = (i_ml) ? i_start_x_e0 : w_start_x_fs;
assign o_start_x_05_r = (i_ml) ? i_start_x_05_e0 : w_start_x_05_fs;
assign o_start_y_r = (i_ml) ? i_start_y_e0 : w_start_y_fs;
assign o_end_y_r = (i_ml) ? i_end_y_e0 : w_end_y_fs;
assign o_delta_r = (i_ml) ? i_delta_e0 : w_delta_fs;
assign o_delta_t_r = (i_ml) ? i_delta_t_e0 : w_delta_t_fs;
assign o_delta_a_r = (i_ml) ? i_delta_a_e0 : w_delta_a_fs;
// left vertex parameters
assign o_z_s_l = (!i_ml) ? i_vtx2_z : w_z_s_fs;
assign o_iw_s_l = (!i_ml) ? i_vtx2_iw : w_iw_s_fs;
assign o_p00_s_l = (!i_ml) ? i_vtx2_p00 : w_p00_s_fs;
assign o_p01_s_l = (!i_ml) ? i_vtx2_p01 : w_p01_s_fs;
assign o_p02_s_l = (!i_ml) ? i_vtx2_p02 : w_p02_s_fs;
assign o_p03_s_l = (!i_ml) ? i_vtx2_p03 : w_p03_s_fs;
assign o_p10_s_l = (!i_ml) ? i_vtx2_p10 : w_p10_s_fs;
assign o_p11_s_l = (!i_ml) ? i_vtx2_p11 : w_p11_s_fs;
`ifdef VTX_PARAM1_REDUCE
`else
assign o_p12_s_l = (!i_ml) ? i_vtx2_p12 : w_p12_s_fs;
assign o_p13_s_l = (!i_ml) ? i_vtx2_p13 : w_p13_s_fs;
`endif
assign o_z_e_l = (!i_ml) ? i_vtx0_z : w_z_e_fs;
assign o_iw_e_l = (!i_ml) ? i_vtx0_iw : w_iw_e_fs;
assign o_p00_e_l = (!i_ml) ? i_vtx0_p00 : w_p00_e_fs;
assign o_p01_e_l = (!i_ml) ? i_vtx0_p01 : w_p01_e_fs;
assign o_p02_e_l = (!i_ml) ? i_vtx0_p02 : w_p02_e_fs;
assign o_p03_e_l = (!i_ml) ? i_vtx0_p03 : w_p03_e_fs;
assign o_p10_e_l = (!i_ml) ? i_vtx0_p10 : w_p10_e_fs;
assign o_p11_e_l = (!i_ml) ? i_vtx0_p11 : w_p11_e_fs;
`ifdef VTX_PARAM1_REDUCE
`else
assign o_p12_e_l = (!i_ml) ? i_vtx0_p12 : w_p12_e_fs;
assign o_p13_e_l = (!i_ml) ? i_vtx0_p13 : w_p13_e_fs;
`endif
// right vertex parameters
assign o_z_s_r = (i_ml) ? i_vtx2_z : w_z_s_fs;
assign o_iw_s_r = (i_ml) ? i_vtx2_iw : w_iw_s_fs;
assign o_p00_s_r = (i_ml) ? i_vtx2_p00 : w_p00_s_fs;
assign o_p01_s_r = (i_ml) ? i_vtx2_p01 : w_p01_s_fs;
assign o_p02_s_r = (i_ml) ? i_vtx2_p02 : w_p02_s_fs;
assign o_p03_s_r = (i_ml) ? i_vtx2_p03 : w_p03_s_fs;
assign o_p10_s_r = (i_ml) ? i_vtx2_p10 : w_p10_s_fs;
assign o_p11_s_r = (i_ml) ? i_vtx2_p11 : w_p11_s_fs;
`ifdef VTX_PARAM1_REDUCE
`else
assign o_p12_s_r = (i_ml) ? i_vtx2_p12 : w_p12_s_fs;
assign o_p13_s_r = (i_ml) ? i_vtx2_p13 : w_p13_s_fs;
`endif
assign o_z_e_r = (i_ml) ? i_vtx0_z : w_z_e_fs;
assign o_iw_e_r = (i_ml) ? i_vtx0_iw : w_iw_e_fs;
assign o_p00_e_r = (i_ml) ? i_vtx0_p00 : w_p00_e_fs;
assign o_p01_e_r = (i_ml) ? i_vtx0_p01 : w_p01_e_fs;
assign o_p02_e_r = (i_ml) ? i_vtx0_p02 : w_p02_e_fs;
assign o_p03_e_r = (i_ml) ? i_vtx0_p03 : w_p03_e_fs;
assign o_p10_e_r = (i_ml) ? i_vtx0_p10 : w_p10_e_fs;
assign o_p11_e_r = (i_ml) ? i_vtx0_p11 : w_p11_e_fs;
`ifdef VTX_PARAM1_REDUCE
`else
assign o_p12_e_r = (i_ml) ? i_vtx0_p12 : w_p12_e_fs;
assign o_p13_e_r = (i_ml) ? i_vtx0_p13 : w_p13_e_fs;
`endif
assign o_ack = ((r_state == P_FIRST_TRI)&!i_is_second & i_ack_l) |
((r_state == P_SECOND_TRI)& i_ack_l);
assign o_has_bottom = (r_state == P_SECOND_TRI);
assign o_idle = (r_state == P_IDLE);
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (i_valid) begin
if (i_is_first) r_state <= P_FIRST_TRI;
else r_state <= P_SECOND_TRI;
end
end
P_FIRST_TRI: begin
if (i_ack_r|i_ack_l) begin
if (i_is_second) r_state <= P_SECOND_TRI;
else r_state <= P_IDLE;
end
end
P_SECOND_TRI: begin
if (i_ack_r|i_ack_l) r_state <= P_IDLE;
end
endcase
end
end
endmodule
|
module fm_3d_ru_outline_update (
clk_core,
rst_x,
// parameter input
i_start,
i_aa_mode,
i_delta_a,
o_finish,
// generated steps
i_valid_step,
i_step_kind,
i_step_val,
i_initial_val,
// control registers
i_param0_en,
i_param1_en,
i_param0_size,
i_param1_size,
// new value
o_new_valid,
o_new_kind,
o_new_edge_val
);
////////////////////////////
// parameter
////////////////////////////
parameter P_UPDATE_Y = 4'h0;
parameter P_UPDATE_X = 4'h1;
parameter P_UPDATE_IW = 4'h2;
parameter P_UPDATE_Z = 4'h3;
parameter P_UPDATE_P00 = 4'h4;
parameter P_UPDATE_P01 = 4'h5;
parameter P_UPDATE_P02 = 4'h6;
parameter P_UPDATE_P03 = 4'h7;
parameter P_UPDATE_P10 = 4'h8;
parameter P_UPDATE_P11 = 4'h9;
parameter P_UPDATE_P12 = 4'ha;
parameter P_UPDATE_P13 = 4'hb;
parameter P_UPDATE_WAIT = 4'hc;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// outline parameter input
input i_start;
output o_finish;
input i_aa_mode;
input [21:0] i_delta_a;
// generated steps
input i_valid_step;
input [3:0] i_step_kind;
input [21:0] i_step_val;
input [21:0] i_initial_val;
// control registers
input i_param0_en;
input i_param1_en;
input [1:0] i_param0_size;
input [1:0] i_param1_size;
// new value
output o_new_valid;
output [3:0] o_new_kind;
output [21:0] o_new_edge_val;
////////////////////////////
// reg
////////////////////////////
reg [3:0] r_state;
reg [3:0] r_kind_1z;
reg r_valid_1z;
reg r_end_flag_1z;
////////////////////////////
// wire
////////////////////////////
wire w_valid;
wire w_valid_normal;
wire w_valid_aa;
wire w_end_flag;
wire w_end_flag_z;
wire w_end_flag_p00;
wire w_end_flag_p01;
wire w_end_flag_p02;
wire w_end_flag_p03;
wire w_end_flag_p10;
wire w_end_flag_p11;
wire w_end_flag_p12;
wire w_end_flag_p13;
wire [21:0] w_cur_val;
wire [20:0] w_initial_val;
wire [21:0] w_cur_step;
wire [21:0] w_10;
wire [3:0] w_kind;
wire [21:0] w_new_val;
wire w_ram_we;
wire [3:0] w_ram_in_adrs;
wire [3:0] w_ram_out_adrs;
wire [64:0] w_ram_in;
wire [64:0] w_ram_out;
wire [21:0] w_cur_val_ri;
wire [20:0] w_initial_val_ri;
wire [21:0] w_cur_step_ri;
wire [20:0] w_initial_val_out;
wire [21:0] w_step_val_out;
////////////////////////////
// assign
////////////////////////////
assign w_10 = {1'b0, 5'h0f, 16'h8000};
assign w_valid_normal = (r_state != P_UPDATE_WAIT)&
((r_state != P_UPDATE_Y) | ((r_state == P_UPDATE_Y)&i_start));
assign w_valid_aa = (r_state != P_UPDATE_WAIT)& (r_state != P_UPDATE_Y);
assign w_valid = (i_aa_mode) ? w_valid_aa : w_valid_normal;
assign w_end_flag_z = (r_state == P_UPDATE_Z) & !i_param0_en & !i_param1_en;
assign w_end_flag_p00 = (r_state == P_UPDATE_P00) &
(i_param0_en & (i_param0_size == 2'd0)) &
!i_param1_en;
assign w_end_flag_p01 = (r_state == P_UPDATE_P01) &
(i_param0_size == 2'd1) & !i_param1_en;
assign w_end_flag_p02 = (r_state == P_UPDATE_P02) &
(i_param0_size == 2'd2) & !i_param1_en;
assign w_end_flag_p03 = (r_state == P_UPDATE_P03) & !i_param1_en;
assign w_end_flag_p10 = (r_state == P_UPDATE_P10) & (i_param1_size == 2'd0);
assign w_end_flag_p11 = (r_state == P_UPDATE_P11) & (i_param1_size == 2'd1);
assign w_end_flag_p12 = (r_state == P_UPDATE_P11) & (i_param1_size == 2'd2);
assign w_end_flag_p13 = (r_state == P_UPDATE_P11);
assign w_end_flag = w_end_flag_z |
w_end_flag_p00 | w_end_flag_p01 | w_end_flag_p02 | w_end_flag_p03|
w_end_flag_p10 | w_end_flag_p11 | w_end_flag_p12 | w_end_flag_p03;
assign w_kind = (r_state == P_UPDATE_Y) ? `FPARAM_Y :
(r_state == P_UPDATE_X) ? `FPARAM_X :
(r_state == P_UPDATE_IW) ? `FPARAM_IW :
(r_state == P_UPDATE_Z) ? `FPARAM_Z :
(r_state == P_UPDATE_P00) ? `FPARAM_P00 :
(r_state == P_UPDATE_P01) ? `FPARAM_P01 :
(r_state == P_UPDATE_P02) ? `FPARAM_P02 :
(r_state == P_UPDATE_P03) ? `FPARAM_P03 :
(r_state == P_UPDATE_P10) ? `FPARAM_P10 :
(r_state == P_UPDATE_P11) ? `FPARAM_P11 :
(r_state == P_UPDATE_P12) ? `FPARAM_P12 :
`FPARAM_P13;
assign w_ram_in_adrs = (i_valid_step) ? i_step_kind : o_new_kind;
assign w_ram_we = o_new_valid | i_valid_step;
assign w_cur_val_ri = (i_valid_step) ? 22'h0 : w_new_val;
assign w_initial_val_ri = (i_valid_step) ? i_initial_val : w_initial_val_out;
assign w_cur_step_ri = (i_valid_step) ? i_step_val : w_step_val_out;
assign w_ram_in = {w_initial_val_ri, w_cur_val_ri, w_cur_step_ri};
assign w_ram_out_adrs = w_kind;
assign {w_initial_val,w_cur_val,w_cur_step} = w_ram_out;
////////////////////////////
// always
////////////////////////////
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_UPDATE_Y;
end else begin
case (r_state)
P_UPDATE_Y: begin
if (i_start) r_state <= P_UPDATE_X;
end
P_UPDATE_X: begin
r_state <= P_UPDATE_IW;
end
P_UPDATE_IW: begin
r_state <= P_UPDATE_Z;
end
P_UPDATE_Z: begin
if (i_param0_en) r_state <= P_UPDATE_P00;
else if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end
P_UPDATE_P00: begin
if (i_param0_size == 2'd0) begin
if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P01;
end
end
P_UPDATE_P01: begin
if (i_param0_size == 2'd1) begin
if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P02;
end
end
P_UPDATE_P02: begin
if (i_param0_size == 2'd2) begin
if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P03;
end
end
P_UPDATE_P03: begin
if (i_param1_en) r_state <= P_UPDATE_P10;
else r_state <= P_UPDATE_WAIT;
end
P_UPDATE_P10: begin
if (i_param1_size == 2'd0) begin
r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P11;
end
end
P_UPDATE_P11: begin
if (i_param1_size == 2'd1) begin
r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P12;
end
end
P_UPDATE_P12: begin
if (i_param1_size == 2'd2) begin
r_state <= P_UPDATE_WAIT;
end else begin
r_state <= P_UPDATE_P13;
end
end
P_UPDATE_P13: begin
r_state <= P_UPDATE_WAIT;
end
P_UPDATE_WAIT: begin
if (o_finish) r_state <= P_UPDATE_Y;
end
endcase
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_valid_1z <= 1'b0;
r_kind_1z <= 4'h0;
r_end_flag_1z <= 1'b0;
end else begin
r_valid_1z <= w_valid;
r_kind_1z <= w_kind;
r_end_flag_1z <= w_end_flag;
end
end
////////////////////////////
// module instance
////////////////////////////
fm_3d_ru_outline_update_core outline_update_core (
.clk_core(clk_core),
.i_en(1'b1),
.i_valid(r_valid_1z),
.i_kind(r_kind_1z),
.i_end_flag(r_end_flag_1z),
.i_cur_p(w_cur_val),
.i_initial_p(w_initial_val),
.i_step_p(w_cur_step),
.i_delta_a(i_delta_a),
.i_aa_mode(i_aa_mode),
.o_valid(o_new_valid),
.o_end_flag(o_finish),
.o_kind(o_new_kind),
.o_initial_p(w_initial_val_out),
.o_step_p(w_step_val_out),
.o_cur_p(w_new_val),
.o_cur_edge_p(o_new_edge_val)
);
`ifdef USE_OUTLINE_RRAM
fm_cmn_bram_01 #(65,4) param_bram (
`else
fm_cmn_dram_01 #(65,4,12) param_dram (
`endif
.clk(clk_core),
.we(w_ram_we),
.a(w_ram_in_adrs),
.dpra(w_ram_out_adrs),
.di(w_ram_in),
.spo(),
.dpo(w_ram_out)
);
endmodule
|
module fm_3d_mu_cache_ro (
clk_core,
rst_x,
// system configuration
i_cache_init,
// cache in
i_req_ci,
i_adrs_ci,
o_ack_ci,
i_len_ci,
o_strr_ci,
o_dbr_ci,
// cache out
o_req_co,
o_adrs_co,
i_ack_co,
o_len_co,
i_strr_co,
i_dbr_co
);
`include "polyphony_params.v"
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// system configueration
input i_cache_init;
// cache in
input i_req_ci;
input [P_IB_ADDR_WIDTH-1:0]
i_adrs_ci;
output o_ack_ci;
input [P_IB_LEN_WIDTH-1:0]
i_len_ci;
output o_strr_ci;
output [P_IB_DATA_WIDTH-1:0]
o_dbr_ci;
// cache out
output o_req_co;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs_co;
input i_ack_co;
output [P_IB_LEN_WIDTH-1:0]
o_len_co;
input i_strr_co;
input [P_IB_DATA_WIDTH-1:0]
i_dbr_co;
//////////////////////////////////
// wire
//////////////////////////////////
// tag - ctrl
wire w_tw_valid;
wire [P_IB_ADDR_WIDTH-1:0]
w_cmp_adrs;
wire [P_IB_ADDR_WIDTH-1:0]
w_cmp_adrs_pre;
wire w_tag_clear;
wire w_hit;
wire [P_IB_CACHE_ENTRY_WIDTH-1:0]
w_entry; // 32 entries
wire [P_IB_TAG_ADDR_WIDTH-1:0]
w_tag_adrs;
// cache memory - ctrl
wire w_we_cm;
wire [P_IB_CACHE_LINE_WIDTH+P_IB_CACHE_ENTRY_WIDTH-1:0]
w_adrs_cm;
wire [P_IB_CACHE_LINE_WIDTH+P_IB_CACHE_ENTRY_WIDTH-1:0]
w_adrs_pre_cm;
wire [P_IB_BE_WIDTH-1:0]
w_be_cm;
wire [P_IB_DATA_WIDTH-1:0]
w_dto_cm;
wire [P_IB_DATA_WIDTH-1:0]
w_dti_cm;
wire [P_IB_DATA_WIDTH-1:0]
w_dti_pre_cm;
////////////////////////////
// module instance
////////////////////////////
fm_3d_mu_cache_tag cache_tag (
.clk_core(clk_core),
.rst_x(rst_x),
.i_tw_valid(w_tw_valid),
.i_adrs_pre(w_cmp_adrs_pre[P_IB_ADDR_WIDTH-1:P_IB_CACHE_LINE_WIDTH]),
.i_adrs(w_cmp_adrs[P_IB_ADDR_WIDTH-1:P_IB_CACHE_LINE_WIDTH]),
.i_tag_clear(w_tag_clear),
.o_hit(w_hit),
.o_need_wb(),
.o_entry(w_entry),
.o_tag_adrs(w_tag_adrs)
);
fm_3d_mu_cache_mem cache_mem (
.clk_core(clk_core),
.i_we(w_we_cm),
.i_adrs(w_adrs_cm),
.i_adrs_pre(w_adrs_cm),
.i_be(w_be_cm),
.i_dt(w_dto_cm),
.o_dt(w_dti_cm),
.o_dt_pre()
);
fm_3d_mu_cache_ctrl_ro cache_ctrl (
.clk_core(clk_core),
.rst_x(rst_x),
// system configuration
.i_cache_init(i_cache_init),
// cache in
.i_req_ci(i_req_ci),
.i_adrs_ci(i_adrs_ci),
.o_ack_ci(o_ack_ci),
.i_len_ci(i_len_ci),
.o_strr_ci(o_strr_ci),
.o_dbr_ci(o_dbr_ci),
// cache tag
.o_tw_valid(w_tw_valid),
.o_cmp_adrs_pre(w_cmp_adrs_pre),
.o_cmp_adrs(w_cmp_adrs),
.o_tag_clear(w_tag_clear),
.i_hit(w_hit),
.i_entry(w_entry),
.i_tag_adrs(w_tag_adrs),
//cache memory
.o_we_cm(w_we_cm),
.o_adrs_cm(w_adrs_cm),
.o_be_cm(w_be_cm),
.o_dt_cm(w_dto_cm),
.i_dt_cm(w_dti_cm),
// external memory access
.o_req_co(o_req_co),
.o_adrs_co(o_adrs_co),
.i_ack_co(i_ack_co),
.o_len_co(o_len_co),
.i_strr_co(i_strr_co),
.i_dbr_co(i_dbr_co)
);
endmodule
|
module fm_3d_interp (
clk_core,
i_en,
i_a,
i_b,
i_t,
o_c
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input i_en;
input [21:0] i_a;
input [21:0] i_b;
input [21:0] i_t;
output [21:0] o_c; // result
///////////////////////////////////////////
// wire
///////////////////////////////////////////
wire [21:0] w_b_a_3z;
wire [21:0] w_a_3z;
wire [21:0] w_t_3z;
wire [21:0] w_abt_6z;
wire [21:0] w_a_6z;
////////////////////////////
// module instance
////////////////////////////
// stage1-3
// ib-ia
fm_3d_fadd fadd_b_a (
.clk_core(clk_core),
.i_en(i_en),
.i_a(i_b),
.i_b(i_a),
.i_adsb(1'b1),
.o_c(w_b_a_3z)
);
fm_3d_delay #(22,3) delay_a (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_a),
.o_data(w_a_3z)
);
fm_3d_delay #(22,3) delay_t (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_t),
.o_data(w_t_3z)
);
// stage 4-6
// (i_b-i_a)*t
fm_3d_fmul fmul_t (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_b_a_3z),
.i_b(w_t_3z),
.o_c(w_abt_6z)
);
fm_3d_delay #(22,3) delay_a_2 (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_a_3z),
.o_data(w_a_6z)
);
// stage 6-9
// i_a + (i_b-i_a) *t
fm_3d_fadd fadd_ab (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_a_6z),
.i_b(w_abt_6z),
.i_adsb(1'b0),
.o_c(o_c)
);
endmodule
|
module fm_3d_mu_cache_ctrl (
clk_core,
rst_x,
// system configuration
i_cache_init,
i_cache_flush,
o_flush_done,
// cache in
i_req_ci,
i_wr_ci,
i_adrs_ci,
o_ack_ci,
i_len_ci,
i_be_ci,
i_strw_ci,
i_dbw_ci,
o_ackw_ci,
o_strr_ci,
o_dbr_ci,
// cache tag
o_tw_valid,
o_cmp_adrs_pre,
o_cmp_adrs,
o_tag_clear,
i_hit,
i_need_wb,
i_entry,
i_tag_adrs,
//cache memory
o_we_cm,
o_adrs_cm,
o_adrs_pre_cm,
o_be_cm,
o_dt_cm,
i_dt_cm,
i_dt_pre_cm,
// external memory access
o_req_co,
o_wr_co,
o_adrs_co,
i_ack_co,
o_len_co,
o_be_co,
o_strw_co,
o_dbw_co,
i_ackw_co,
i_strr_co,
i_dbr_co
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
localparam P_MAIN_IDLE = 4'd0;
localparam P_MAIN_TAG_CHECK = 4'd1;
localparam P_MAIN_CACHE_WRITE = 4'd2;
localparam P_MAIN_CACHE_READ0 = 4'd3;
localparam P_MAIN_CACHE_READ1 = 4'd4;
localparam P_MAIN_CACHE_READ2 = 4'd5;
localparam P_MAIN_EXT_WRITE0 = 4'd6;
localparam P_MAIN_EXT_WRITE1 = 4'd7;
localparam P_MAIN_EXT_READ = 4'd8;
localparam P_MAIN_FLUSH = 4'd9;
localparam P_MAIN_FLUSH_TAG_REQ = 4'd10;
localparam P_MAIN_FLUSH_TAG_CHECK = 4'd11;
localparam P_MAIN_FLUSH_WRITE = 4'd12;
// external memory access
localparam P_EXT_IDLE = 3'd0;
localparam P_EXT_WPRE = 3'd1;
localparam P_EXT_WREQ = 3'd2;
localparam P_EXT_RREQ = 3'd3;
localparam P_EXT_WDATA = 3'd4;
localparam P_EXT_RDATA = 3'd5;
localparam P_MAX_BURST_LEN = 1 << P_IB_CACHE_LINE_WIDTH;
localparam P_MAX_FLUSH_ADRS = 1 << P_IB_CACHE_ENTRY_WIDTH;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// system configuration
input i_cache_init;
input i_cache_flush;
output o_flush_done;
// cache in
input i_req_ci;
input i_wr_ci;
input [P_IB_ADDR_WIDTH-1:0]
i_adrs_ci;
output o_ack_ci;
input [P_IB_LEN_WIDTH-1:0]
i_len_ci;
input [P_IB_BE_WIDTH-1:0]
i_be_ci;
input i_strw_ci;
input [P_IB_DATA_WIDTH-1:0]
i_dbw_ci;
output o_ackw_ci;
output o_strr_ci;
output [P_IB_DATA_WIDTH-1:0]
o_dbr_ci;
// cache tag
output o_tw_valid;
output [P_IB_ADDR_WIDTH-1:0]
o_cmp_adrs_pre;
output [P_IB_ADDR_WIDTH-1:0]
o_cmp_adrs;
output o_tag_clear;
input i_hit;
input i_need_wb;
input [P_IB_CACHE_ENTRY_WIDTH-1:0]
i_entry; // 32 entries
input [P_IB_TAG_ADDR_WIDTH-1:0]
i_tag_adrs;
//cache memory
output o_we_cm;
output [P_IB_CACHE_ENTRY_WIDTH+P_IB_CACHE_LINE_WIDTH-1:0]
o_adrs_cm;
output [P_IB_CACHE_ENTRY_WIDTH+P_IB_CACHE_LINE_WIDTH-1:0]
o_adrs_pre_cm;
output [P_IB_BE_WIDTH-1:0]
o_be_cm;
output [P_IB_DATA_WIDTH-1:0]
o_dt_cm;
input [P_IB_DATA_WIDTH-1:0]
i_dt_cm;
input [P_IB_DATA_WIDTH-1:0]
i_dt_pre_cm;
// cache out
output o_req_co;
output o_wr_co;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs_co;
input i_ack_co;
output [P_IB_LEN_WIDTH-1:0]
o_len_co;
output [P_IB_BE_WIDTH-1:0]
o_be_co;
output o_strw_co;
output [P_IB_DATA_WIDTH-1:0]
o_dbw_co;
input i_ackw_co;
input i_strr_co;
input [P_IB_DATA_WIDTH-1:0]
i_dbr_co;
//////////////////////////////////
// reg
//////////////////////////////////
reg [3:0] r_state;
reg [2:0] r_ext_state;
// save access address
reg r_wr_ci;
reg r_len_ci;
reg [P_IB_ADDR_WIDTH-1:0]
r_adrs_ci;
reg [P_IB_BE_WIDTH-1:0]
r_be_ci;
reg [P_IB_DATA_WIDTH-1:0]
r_dbw_ci;
reg [P_IB_CACHE_ENTRY_WIDTH-1:0]
r_entry; // 32 entries
reg [P_IB_CACHE_ENTRY_WIDTH-1:0]
r_flush_adrs;
reg [P_IB_TAG_ADDR_WIDTH-1:0]
r_tag_adrs;
reg [P_IB_CACHE_ENTRY_WIDTH+P_IB_CACHE_LINE_WIDTH-1:0]
r_adrs_cm;
reg [P_IB_LEN_WIDTH-1:0]
r_data_cnt;
reg r_ackw_1z;
//////////////////////////////////
// wire
//////////////////////////////////
wire [P_IB_CACHE_ENTRY_WIDTH+P_IB_CACHE_LINE_WIDTH-1:0]
w_adrs_cm_next;
wire w_save_adrs;
wire w_save_wdata;
wire w_ext_wstart;
wire w_ext_rstart;
wire w_burst_write_end;
wire w_burst_read_end;
wire w_cnt_clear;
wire w_cnt_inc;
wire w_ext_read_end;
wire w_ext_write_end;
wire w_cache_adrs_init;
wire w_cache_adrs_inc;
wire w_set_entry;
wire w_need_write_back;
wire w_flush_init;
wire w_flush_inc;
wire w_flush_end;
wire w_cnt_inc_write;
wire w_ackw_rise;
wire w_ext_read_partial_end;
wire [P_IB_CACHE_LINE_WIDTH-1:0]
w_adrs_ci_p1;
//////////////////////////////////
// assign
//////////////////////////////////
assign w_adrs_cm_next = r_adrs_cm +1'b1;
assign o_flush_done = ((r_state == P_MAIN_FLUSH_TAG_CHECK)&!w_need_write_back&w_flush_end) |
((r_state == P_MAIN_FLUSH_WRITE)&w_ext_write_end&w_flush_end);
assign w_save_adrs = (r_state == P_MAIN_IDLE) & i_req_ci;
assign w_save_wdata = w_save_adrs & i_wr_ci;
assign o_cmp_adrs_pre = (r_state == P_MAIN_FLUSH_TAG_REQ) ? {{P_IB_TAG_ADDR_WIDTH{1'b0}},
r_flush_adrs,
{P_IB_CACHE_LINE_WIDTH{1'b0}}} :
(r_state == P_MAIN_FLUSH_TAG_CHECK) ? {{P_IB_TAG_ADDR_WIDTH{1'b0}},
r_flush_adrs,
{P_IB_CACHE_LINE_WIDTH{1'b0}}} :
i_adrs_ci;
assign o_cmp_adrs = (r_state == P_MAIN_FLUSH_TAG_REQ) ? {{P_IB_TAG_ADDR_WIDTH{1'b0}},
r_flush_adrs,
{P_IB_CACHE_LINE_WIDTH{1'b0}}} :
(r_state == P_MAIN_FLUSH_TAG_CHECK) ? {{P_IB_TAG_ADDR_WIDTH{1'b0}},
r_flush_adrs,
{P_IB_CACHE_LINE_WIDTH{1'b0}}} :
r_adrs_ci;
assign w_cnt_clear = w_ext_rstart | w_ext_wstart;
assign w_cnt_inc = (r_ext_state == P_EXT_RDATA) ? i_strr_co : w_cnt_inc_write;
assign w_cnt_inc_write = (r_ext_state ==P_EXT_WREQ) ? (i_ackw_co & i_ack_co) :
(r_ext_state ==P_EXT_WDATA) ? i_ackw_co : 1'b0;
assign w_cache_adrs_init = w_cnt_clear;
assign w_cache_adrs_inc = w_cnt_inc;
assign w_ext_read_end = (r_ext_state == P_EXT_RDATA)&w_burst_read_end;
assign w_ext_write_end = (r_ext_state == P_EXT_WDATA)&w_burst_write_end;
assign w_set_entry = (r_state == P_MAIN_TAG_CHECK)|
(r_state == P_MAIN_FLUSH_TAG_CHECK);
assign o_tw_valid = (r_state == P_MAIN_TAG_CHECK);
assign o_ack_ci = (r_state == P_MAIN_IDLE);
assign o_ackw_ci = o_ack_ci;
assign o_strr_ci = (r_state == P_MAIN_CACHE_READ1) |
(r_state == P_MAIN_CACHE_READ2) |
((r_state == P_MAIN_EXT_READ)& w_ext_read_partial_end);
assign o_dbr_ci = ((r_state == P_MAIN_CACHE_READ1) |
(r_state == P_MAIN_CACHE_READ2)) ? i_dt_cm : i_dbr_co;
assign o_tag_clear = i_cache_init;
assign o_we_cm = (r_state == P_MAIN_CACHE_WRITE) |
((r_state == P_MAIN_EXT_READ)&i_strr_co);
// assign o_adrs_cm = (r_state == P_MAIN_CACHE_WRITE) ? {r_entry,r_adrs_ci[3:0]}:
// (r_state == P_MAIN_CACHE_READ0) ? {r_entry,r_adrs_ci[3:0]}:
// (r_state == P_MAIN_CACHE_READ1) ? {r_entry,r_adrs_ci[3:0]+ 1'b1}:
// r_adrs_cm;
assign w_adrs_ci_p1 = r_adrs_ci[P_IB_CACHE_LINE_WIDTH-1:0]+ 1'b1;
assign o_adrs_cm = (r_state == P_MAIN_TAG_CHECK) ? {i_entry,r_adrs_ci[P_IB_CACHE_LINE_WIDTH-1:0]}: // pre address for read
(r_state == P_MAIN_CACHE_WRITE) ? {r_entry,r_adrs_ci[P_IB_CACHE_LINE_WIDTH-1:0]}:
(r_state == P_MAIN_CACHE_READ0) ? {r_entry,r_adrs_ci[P_IB_CACHE_LINE_WIDTH-1:0]}:
(r_state == P_MAIN_CACHE_READ1) ? {r_entry,w_adrs_ci_p1}:
r_adrs_cm;
assign o_adrs_pre_cm = w_adrs_cm_next;
assign o_be_cm = (r_state == P_MAIN_EXT_READ) ?
{P_IB_BE_WIDTH{1'b1}} :
r_be_ci;
assign o_dt_cm = (r_state == P_MAIN_EXT_READ) ? i_dbr_co : r_dbw_ci;
assign w_ext_rstart = ((r_state == P_MAIN_TAG_CHECK) & !i_hit & !w_need_write_back) |
(r_state == P_MAIN_EXT_WRITE1);
assign w_ext_wstart = ((r_state == P_MAIN_TAG_CHECK) & !i_hit & w_need_write_back) |
((r_state == P_MAIN_FLUSH_TAG_CHECK) & w_need_write_back);
assign w_need_write_back = i_need_wb;
assign w_burst_write_end = (r_data_cnt == (P_MAX_BURST_LEN-1)) & i_ackw_co;
assign w_burst_read_end = (r_data_cnt == (P_MAX_BURST_LEN-1)) & i_strr_co;
assign w_flush_init = (r_state == P_MAIN_FLUSH);
assign w_flush_inc = ((r_state == P_MAIN_FLUSH_TAG_CHECK) & !w_need_write_back) |
((r_state == P_MAIN_FLUSH_WRITE) & w_ext_write_end);
assign w_flush_end = (r_flush_adrs == (P_MAX_FLUSH_ADRS-1));
// external memory access
assign o_req_co = (r_ext_state == P_EXT_WREQ) | (r_ext_state == P_EXT_RREQ);
assign o_wr_co = (r_ext_state == P_EXT_WREQ);
// 21 . 5. 4
assign o_adrs_co = (r_ext_state == P_EXT_WREQ) ? {r_tag_adrs,r_entry,{P_IB_CACHE_LINE_WIDTH{1'b0}}} : // flush
{r_adrs_ci[P_IB_ADDR_WIDTH-1:P_IB_CACHE_LINE_WIDTH],
{P_IB_CACHE_LINE_WIDTH{1'b0}}};
assign o_len_co = 6'h10;
assign o_be_co = {P_IB_BE_WIDTH{1'b1}};
assign o_strw_co = (r_ext_state == P_EXT_WREQ) | (r_ext_state == P_EXT_WDATA);
assign o_dbw_co = ((r_ext_state == P_EXT_WREQ)| w_ackw_rise) ? i_dt_cm :
i_dt_pre_cm;
assign w_ackw_rise = i_ackw_co & !r_ackw_1z;
//assign w_ext_read_partial_end = ((r_data_cnt == r_adrs_ci[3:0])|
// (r_data_cnt == w_adrs_ci_p1)) & i_strr_co & !r_wr_ci;
assign w_ext_read_partial_end = (r_data_cnt == r_adrs_ci[P_IB_CACHE_LINE_WIDTH-1:0]) & i_strr_co & !r_wr_ci;
//////////////////////////////////
// always
//////////////////////////////////
// main state
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_MAIN_IDLE;
end else begin
case(r_state)
P_MAIN_IDLE: begin
if (i_cache_flush) r_state <= P_MAIN_FLUSH;
else if (i_req_ci) r_state <= P_MAIN_TAG_CHECK;
end
P_MAIN_TAG_CHECK: begin
if (i_hit) begin
// cache hit
if (r_wr_ci) r_state <= P_MAIN_CACHE_WRITE;
else r_state <= P_MAIN_CACHE_READ1; // CACHE_READ0 is only used in cache miss
end else begin
// cache miss hit
if (w_need_write_back) begin
r_state <= P_MAIN_EXT_WRITE0;
end else begin
r_state <= P_MAIN_EXT_READ;
end
end
end
P_MAIN_CACHE_WRITE: begin
r_state <= P_MAIN_IDLE;
end
P_MAIN_CACHE_READ0: begin // pre address state
r_state <= P_MAIN_CACHE_READ1;
end
P_MAIN_CACHE_READ1: begin
if (r_len_ci) r_state <= P_MAIN_CACHE_READ2;
else r_state <= P_MAIN_IDLE;
end
P_MAIN_CACHE_READ2: begin
r_state <= P_MAIN_IDLE;
end
P_MAIN_EXT_WRITE0: begin
if (w_ext_write_end) r_state <= P_MAIN_EXT_WRITE1;
end
P_MAIN_EXT_WRITE1: begin
r_state <= P_MAIN_EXT_READ;
end
P_MAIN_EXT_READ: begin
// read until getting all read data
if (w_ext_read_end) begin
if (r_wr_ci) r_state <= P_MAIN_CACHE_WRITE;
else r_state <= P_MAIN_IDLE; // read data is returned on-the-fly
//else r_state <= P_MAIN_CACHE_READ0;
end
end
P_MAIN_FLUSH: begin
r_state <= P_MAIN_FLUSH_TAG_REQ;
end
P_MAIN_FLUSH_TAG_REQ: begin
r_state <= P_MAIN_FLUSH_TAG_CHECK;
end
P_MAIN_FLUSH_TAG_CHECK: begin
if (w_need_write_back) r_state <= P_MAIN_FLUSH_WRITE;
else if (w_flush_end) r_state <= P_MAIN_IDLE;
else r_state <= P_MAIN_FLUSH_TAG_REQ;
end
P_MAIN_FLUSH_WRITE: begin
if (w_ext_write_end) begin
if (w_flush_end) r_state <= P_MAIN_IDLE;
else r_state <= P_MAIN_FLUSH_TAG_REQ;
end
end
endcase
end
end
// external memory access
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_ext_state <= P_EXT_IDLE;
end else begin
case(r_ext_state)
P_EXT_IDLE: begin
if (w_ext_wstart) r_ext_state <= P_EXT_WPRE;
else if (w_ext_rstart) r_ext_state <= P_EXT_RREQ;
end
P_EXT_WPRE: begin
r_ext_state <= P_EXT_WREQ;
end
P_EXT_WREQ: begin
if (i_ack_co & i_ackw_co) r_ext_state <= P_EXT_WDATA;
end
P_EXT_RREQ: begin
if (i_ack_co) r_ext_state <= P_EXT_RDATA;
end
P_EXT_WDATA: begin
if (w_burst_write_end) r_ext_state <= P_EXT_IDLE;
end
P_EXT_RDATA: begin
if (w_burst_read_end) r_ext_state <= P_EXT_IDLE;
end
endcase
end
end
// write/read data counter
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_data_cnt <= {P_IB_LEN_WIDTH{1'b0}};
end else begin
if (w_cnt_clear) r_data_cnt <= {P_IB_LEN_WIDTH{1'b0}};
else if (w_cnt_inc) r_data_cnt <= r_data_cnt + 1'b1;
end
end
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_ackw_1z <= 1'b0;
end else begin
r_ackw_1z <= i_ackw_co;
end
end
always @(posedge clk_core) begin
if (w_set_entry) begin
r_entry <= i_entry;
r_tag_adrs <= i_tag_adrs;
end
end
always @(posedge clk_core) begin
if (w_cache_adrs_init) r_adrs_cm <= {i_entry,{P_IB_CACHE_LINE_WIDTH{1'b0}}};
else if (w_cache_adrs_inc) r_adrs_cm <= w_adrs_cm_next;
end
always @(posedge clk_core) begin
if (w_flush_init) r_flush_adrs <= {P_IB_CACHE_ENTRY_WIDTH{1'b0}};
else if (w_flush_inc) r_flush_adrs <= r_flush_adrs + 1'b1;
end
always @(posedge clk_core) begin
if (w_save_adrs) begin
r_wr_ci <= i_wr_ci;
r_adrs_ci <= i_adrs_ci;
r_len_ci <= i_len_ci[1];
end
end
always @(posedge clk_core) begin
if (w_save_wdata) begin
r_be_ci <= i_be_ci;
r_dbw_ci <= i_dbw_ci;
end
end
endmodule
|
module fm_3d_ru (
clk_core,
rst_x,
// triangle data
i_valid,
o_ack,
i_ml,
i_vtx0_x,
i_vtx0_y,
i_vtx0_z,
i_vtx0_iw,
i_vtx0_p00,
i_vtx0_p01,
i_vtx0_p02,
i_vtx0_p03,
i_vtx0_p10,
i_vtx0_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx0_p12,
i_vtx0_p13,
`endif
i_vtx1_x,
i_vtx1_y,
i_vtx1_z,
i_vtx1_iw,
i_vtx1_p00,
i_vtx1_p01,
i_vtx1_p02,
i_vtx1_p03,
i_vtx1_p10,
i_vtx1_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx1_p12,
i_vtx1_p13,
`endif
i_vtx2_x,
i_vtx2_y,
i_vtx2_z,
i_vtx2_iw,
i_vtx2_p00,
i_vtx2_p01,
i_vtx2_p02,
i_vtx2_p03,
i_vtx2_p10,
i_vtx2_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx2_p12,
i_vtx2_p13,
`endif
// control registers
i_aa_en,
i_attr0_en,
i_attr0_size,
i_attr0_kind,
i_attr1_en,
i_attr1_size,
i_attr1_kind,
o_idle,
// pixel unit bus
o_valid_pu,
i_busy_pu,
o_aa_mode,
o_x,
o_y,
o_z,
o_cr,
o_cg,
o_cb,
o_ca,
// texture unit bus
o_valid_tu,
i_busy_tu,
o_tu,
o_tv
);
////////////////////////////
// Parameter definition
////////////////////////////
////////////////////////////
// I/O definition
////////////////////////////
////////////////////////////
input clk_core;
input rst_x;
// triangle data
input i_valid;
output o_ack;
input i_ml;
input [20:0] i_vtx0_x; // 0.5.16
input [20:0] i_vtx0_y;
input [20:0] i_vtx0_z;
input [20:0] i_vtx0_iw;
input [20:0] i_vtx0_p00;
input [20:0] i_vtx0_p01;
input [20:0] i_vtx0_p02;
input [20:0] i_vtx0_p03;
input [20:0] i_vtx0_p10;
input [20:0] i_vtx0_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx0_p12;
input [20:0] i_vtx0_p13;
`endif
input [20:0] i_vtx1_x;
input [20:0] i_vtx1_y;
input [20:0] i_vtx1_z;
input [20:0] i_vtx1_iw;
input [20:0] i_vtx1_p00;
input [20:0] i_vtx1_p01;
input [20:0] i_vtx1_p02;
input [20:0] i_vtx1_p03;
input [20:0] i_vtx1_p10;
input [20:0] i_vtx1_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx1_p12;
input [20:0] i_vtx1_p13;
`endif
input [20:0] i_vtx2_x;
input [20:0] i_vtx2_y;
input [20:0] i_vtx2_z;
input [20:0] i_vtx2_iw;
input [20:0] i_vtx2_p00;
input [20:0] i_vtx2_p01;
input [20:0] i_vtx2_p02;
input [20:0] i_vtx2_p03;
input [20:0] i_vtx2_p10;
input [20:0] i_vtx2_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx2_p12;
input [20:0] i_vtx2_p13;
`endif
// control registers
input i_aa_en;
input i_attr0_en;
input [1:0] i_attr0_size;
input [1:0] i_attr0_kind;
input i_attr1_en;
input [1:0] i_attr1_size;
input [1:0] i_attr1_kind;
output o_idle;
// pixel unit bus
output o_valid_pu;
input i_busy_pu;
output o_aa_mode;
output [9:0] o_x;
output [8:0] o_y;
output [15:0] o_z;
output [7:0] o_cr;
output [7:0] o_cg;
output [7:0] o_cb;
output [7:0] o_ca;
// texture unit bus
output o_valid_tu;
input i_busy_tu;
output [21:0] o_tu;
output [21:0] o_tv;
/////////////////////////
// register definition
/////////////////////////
/////////////////////////
// wire
/////////////////////////
wire w_valid;
wire w_aa_mode;
wire [20:0] w_x_l;
wire [8:0] w_y_l;
wire [20:0] w_z_l;
wire [20:0] w_iw_l;
wire [20:0] w_param00_l;
wire [20:0] w_param01_l;
wire [20:0] w_param02_l;
wire [20:0] w_param03_l;
wire [20:0] w_param10_l;
wire [20:0] w_param11_l;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_param12_l;
wire [20:0] w_param13_l;
`endif
wire [20:0] w_x_r;
wire [8:0] w_y_r;
wire [20:0] w_z_r;
wire [20:0] w_iw_r;
wire [20:0] w_param00_r;
wire [20:0] w_param01_r;
wire [20:0] w_param02_r;
wire [20:0] w_param03_r;
wire [20:0] w_param10_r;
wire [20:0] w_param11_r;
`ifdef VTX_PARAM1_REDUCE
`else
wire [20:0] w_param12_r;
wire [20:0] w_param13_r;
`endif
wire w_ack;
wire w_idle_outline;
wire w_idle_span;
////////////////////////////
// assign
////////////////////////////
assign o_idle = w_idle_outline & w_idle_span;
/////////////////////////
// module instance
/////////////////////////
// outline
fm_3d_ru_outline outline (
.clk_core(clk_core),
.rst_x(rst_x),
// triangle data
.i_valid(i_valid),
.i_ml(i_ml),
.o_ack(o_ack),
.i_vtx0_x(i_vtx0_x),
.i_vtx0_y(i_vtx0_y),
.i_vtx0_z(i_vtx0_z),
.i_vtx0_iw(i_vtx0_iw),
.i_vtx0_p00(i_vtx0_p00),
.i_vtx0_p01(i_vtx0_p01),
.i_vtx0_p02(i_vtx0_p02),
.i_vtx0_p03(i_vtx0_p03),
.i_vtx0_p10(i_vtx0_p10),
.i_vtx0_p11(i_vtx0_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx0_p12(i_vtx0_p12),
.i_vtx0_p13(i_vtx0_p13),
`endif
.i_vtx1_x(i_vtx1_x),
.i_vtx1_y(i_vtx1_y),
.i_vtx1_z(i_vtx1_z),
.i_vtx1_iw(i_vtx1_iw),
.i_vtx1_p00(i_vtx1_p00),
.i_vtx1_p01(i_vtx1_p01),
.i_vtx1_p02(i_vtx1_p02),
.i_vtx1_p03(i_vtx1_p03),
.i_vtx1_p10(i_vtx1_p10),
.i_vtx1_p11(i_vtx1_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx1_p12(i_vtx1_p12),
.i_vtx1_p13(i_vtx1_p13),
`endif
.i_vtx2_x(i_vtx2_x),
.i_vtx2_y(i_vtx2_y),
.i_vtx2_z(i_vtx2_z),
.i_vtx2_iw(i_vtx2_iw),
.i_vtx2_p00(i_vtx2_p00),
.i_vtx2_p01(i_vtx2_p01),
.i_vtx2_p02(i_vtx2_p02),
.i_vtx2_p03(i_vtx2_p03),
.i_vtx2_p10(i_vtx2_p10),
.i_vtx2_p11(i_vtx2_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx2_p12(i_vtx2_p12),
.i_vtx2_p13(i_vtx2_p13),
`endif
// control registers
.i_aa_en(i_aa_en),
.i_attr0_en(i_attr0_en),
.i_attr0_size(i_attr0_size),
.i_attr0_kind(i_attr0_kind),
.i_attr1_en(i_attr1_en),
.i_attr1_size(i_attr1_size),
.i_attr1_kind(i_attr1_kind),
.o_idle(w_idle_outline),
// edge data
.o_valid(w_valid),
.o_aa_mode(w_aa_mode),
.i_ack(w_ack),
// edge data left
.o_x_l(w_x_l),
.o_y_l(w_y_l),
.o_z_l(w_z_l),
.o_iw_l(w_iw_l),
.o_param00_l(w_param00_l),
.o_param01_l(w_param01_l),
.o_param02_l(w_param02_l),
.o_param03_l(w_param03_l),
.o_param10_l(w_param10_l),
.o_param11_l(w_param11_l),
`ifdef VTX_PARAM1_REDUCE
`else
.o_param12_l(w_param12_l),
.o_param13_l(w_param13_l),
`endif
// edge data right
.o_x_r(w_x_r),
.o_y_r(w_y_r),
.o_z_r(w_z_r),
.o_iw_r(w_iw_r),
.o_param00_r(w_param00_r),
.o_param01_r(w_param01_r),
.o_param02_r(w_param02_r),
.o_param03_r(w_param03_r),
.o_param10_r(w_param10_r),
.o_param11_r(w_param11_r)
`ifdef VTX_PARAM1_REDUCE
`else
,.o_param12_r(w_param12_r),
.o_param13_r(w_param13_r)
`endif
);
// span
fm_3d_ru_span span (
.clk_core(clk_core),
.rst_x(rst_x),
// span parameters
.i_valid(w_valid),
.i_aa_mode(w_aa_mode),
.i_x_l(w_x_l),
.i_y_l(w_y_l),
.i_z_l(w_z_l),
.i_iw_l(w_iw_l),
.i_param00_l(w_param00_l),
.i_param01_l(w_param01_l),
.i_param02_l(w_param02_l),
.i_param03_l(w_param03_l),
.i_param10_l(w_param10_l),
.i_param11_l(w_param11_l),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_l(w_param12_l),
.i_param13_l(w_param13_l),
`endif
.i_x_r(w_x_r),
.i_y_r(w_y_r),
.i_z_r(w_z_r),
.i_iw_r(w_iw_r),
.i_param00_r(w_param00_r),
.i_param01_r(w_param01_r),
.i_param02_r(w_param02_r),
.i_param03_r(w_param03_r),
.i_param10_r(w_param10_r),
.i_param11_r(w_param11_r),
`ifdef VTX_PARAM1_REDUCE
`else
.i_param12_r(w_param12_r),
.i_param13_r(w_param13_r),
`endif
.o_ack(w_ack),
// control registers
.i_param0_en(i_attr0_en),
.i_param1_en(i_attr1_en),
.i_param0_size(i_attr0_size),
.i_param1_size(i_attr1_size),
.i_param0_kind(i_attr0_kind),
.i_param1_kind(i_attr1_kind),
// idle state indicator
.o_idle(w_idle_span),
// pixel unit bus
.o_valid_pu(o_valid_pu),
.i_busy_pu(i_busy_pu),
.o_aa_mode(o_aa_mode),
.o_x(o_x),
.o_y(o_y),
.o_z(o_z),
.o_cr(o_cr),
.o_cg(o_cg),
.o_cb(o_cb),
.o_ca(o_ca),
// texture unit bus
.o_valid_tu(o_valid_tu),
.i_busy_tu(i_busy_tu),
.o_tu(o_tu),
.o_tv(o_tv)
);
// debug
`ifdef RTL_DEBUG
reg [31:0] r_cnt_pu;
reg [31:0] r_cnt_tu;
initial begin
r_cnt_pu = 0;
r_cnt_tu = 0;
end
always @(posedge clk_core) begin
if (o_valid_tu & !i_busy_tu) r_cnt_tu = r_cnt_tu + 1;
if (o_valid_pu & !i_busy_pu) r_cnt_pu = r_cnt_pu + 1;
end
`endif
endmodule
|
module fm_3d_interp_e (
clk_core,
rst_x,
i_en,
i_wf,
i_a,
i_iwa,
i_b,
i_iwb,
i_t,
i_w,
o_c
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
input i_en;
input i_wf;
input [21:0] i_a;
input [21:0] i_iwa;
input [21:0] i_b;
input [21:0] i_iwb;
input [21:0] i_t;
input [21:0] i_w;
output [21:0] o_c; // result
///////////////////////////////////////////
// wire
///////////////////////////////////////////
wire [21:0] w_aiw;
wire [21:0] w_biw;
wire [21:0] w_aiw_s;
wire [21:0] w_biw_s;
wire [21:0] w_td;
wire [21:0] w_td_s;
wire [21:0] w_wd;
wire [21:0] w_wdd;
////////////////////////////
// assign
////////////////////////////
assign w_aiw_s = (i_wf) ? w_aiw : i_a;
assign w_biw_s = (i_wf) ? w_biw : i_b;
assign w_td_s = (i_wf) ? w_td : i_t;
////////////////////////////
// module instance
////////////////////////////
// stage1-3
fm_3d_fmul mul_aiw (
.clk_core(clk_core),
.i_en(i_en),
.i_a(i_a),
.i_b(i_iwa),
.o_c(w_aiw)
);
fm_3d_fmul mul_biw (
.clk_core(clk_core),
.i_en(i_en),
.i_a(i_b),
.i_b(i_iwb),
.o_c(w_biw)
);
fm_3d_delay #(22,3) delay_t (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_t),
.o_data(w_td)
);
fm_3d_delay #(22,2) delay_w (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_w),
.o_data(w_wd)
);
// stage4-12 (interpolate)
fm_3d_interp interp (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_aiw_s),
.i_b(w_biw_s),
.i_t(w_td_s),
.o_c(o_c)
);
endmodule
|
module fm_3d_tex_blend (
clk_core,
rst_x,
// ru interface
i_valid_ru,
i_aa_mode,
i_x,
i_y,
i_z,
i_cr,
i_cg,
i_cb,
i_ca,
o_busy_ru,
// texture unit
i_valid_tu,
i_tr,
i_tg,
i_tb,
i_ta,
o_busy_tu,
// configurations
i_tex_enable,
i_tex_blend_enable,
// blend out
o_valid,
o_aa_mode,
o_x,
o_y,
o_z,
o_br,
o_bg,
o_bb,
o_ba,
i_busy
);
////////////////////////////
// Parameter definition
////////////////////////////
// main state
parameter P_IDLE = 2'd0;
parameter P_WAIT_TEX = 2'd1;
parameter P_BLEND = 2'd2;
parameter P_OUT = 2'd3;
// sub state
parameter P_CR = 2'd0;
parameter P_CG = 2'd1;
parameter P_CB = 2'd2;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// ru interface
input i_valid_ru;
input i_aa_mode;
input [9:0] i_x;
input [8:0] i_y;
input [15:0] i_z;
input [7:0] i_cr;
input [7:0] i_cg;
input [7:0] i_cb;
input [7:0] i_ca;
output o_busy_ru;
// texture unit
input i_valid_tu;
input [7:0] i_tr;
input [7:0] i_tg;
input [7:0] i_tb;
input [7:0] i_ta;
output o_busy_tu;
// configurations
input i_tex_enable;
input i_tex_blend_enable;
// blend out
output o_valid;
output o_aa_mode;
output [9:0] o_x;
output [8:0] o_y;
output [15:0] o_z;
output [7:0] o_br;
output [7:0] o_bg;
output [7:0] o_bb;
output [7:0] o_ba;
input i_busy;
////////////////////////////
// reg
////////////////////////////
reg [1:0] r_state;
reg [1:0] r_sub_state;
reg [7:0] r_cr;
reg [7:0] r_cg;
reg [7:0] r_cb;
reg [7:0] r_ca;
reg [7:0] r_tr;
reg [7:0] r_tg;
reg [7:0] r_tb;
reg [7:0] r_br;
reg [7:0] r_bg;
reg [7:0] r_bb;
reg r_aa_mode;
reg [9:0] r_x;
reg [8:0] r_y;
reg [15:0] r_z;
////////////////////////////
// wire
////////////////////////////
wire w_out_c;
wire w_out_t;
wire w_set_ru;
wire w_set_tu;
wire w_set_br;
wire w_set_bg;
wire w_set_bb;
wire [7:0] w_a;
wire [7:0] w_b;
wire [7:0] w_c;
wire w_sub_start;
wire w_finish;
wire [1:0] w_valid;
////////////////////////////
// assign
////////////////////////////
assign w_valid = {i_valid_tu, i_valid_ru};
assign o_busy_ru = (r_state != P_IDLE);
assign o_busy_tu = !((r_state == P_IDLE) | (r_state == P_WAIT_TEX));
assign w_out_c = (!i_tex_enable & !i_tex_blend_enable);
assign w_out_t = (i_tex_enable & !i_tex_blend_enable);
assign o_valid = (r_state == P_OUT);
assign w_a = (r_sub_state == P_CG) ? r_cg:
(r_sub_state == P_CB) ? r_cb:
r_cr;
assign w_b = (r_sub_state == P_CG) ? r_tg:
(r_sub_state == P_CB) ? r_tb:
r_tr;
assign w_set_ru = i_valid_ru & (r_state == P_IDLE);
assign w_set_tu = i_valid_tu & ((r_state == P_IDLE) | (r_state == P_WAIT_TEX));
assign w_set_br = (r_state == P_BLEND) & (r_sub_state == P_CR);
assign w_set_bg = (r_state == P_BLEND) & (r_sub_state == P_CG);
assign w_set_bb = (r_state == P_BLEND) & (r_sub_state == P_CB);
assign w_finish = w_set_bb;
assign o_br = (w_out_c) ? r_cr :
(w_out_t) ? r_tr :
r_br;
assign o_bg = (w_out_c) ? r_cg :
(w_out_t) ? r_tg :
r_bg;
assign o_bb = (w_out_c) ? r_cb :
(w_out_t) ? r_tb :
r_bb;
assign o_ba = r_ca;
assign o_aa_mode = r_aa_mode;
assign o_x = r_x;
assign o_y = r_y;
assign o_z = r_z;
assign w_sub_start = ((r_state == P_BLEND) & (r_sub_state == P_CR));
////////////////////////////
// always
////////////////////////////
// main sequence
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE:begin
case (w_valid)
2'b01: begin // ru valid
if (w_out_c) r_state <= P_OUT;
else r_state <= P_WAIT_TEX;
end
2'b11: begin // ru & tu valid
if (w_out_t) r_state <= P_OUT;
else r_state <= P_BLEND;
end
endcase
end
P_WAIT_TEX:begin
if (i_valid_tu) begin
if (w_out_t) r_state <= P_OUT;
else r_state <= P_BLEND;
end
end
P_BLEND:begin
if (w_finish) begin
r_state <= P_OUT;
end
end
P_OUT:begin
if (!i_busy) r_state <= P_IDLE;
end
endcase
end
end
// sub sequence
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_sub_state <= P_CR;
end else begin
case (r_sub_state)
P_CR:begin
if (w_sub_start) r_sub_state <= P_CG;
end
P_CG:begin
r_sub_state <= P_CB;
end
P_CB:begin
r_sub_state <= P_CR;
end
endcase
end
end
always @(posedge clk_core) begin
if (w_set_ru) begin
r_cr <= i_cr;
r_cg <= i_cg;
r_cb <= i_cb;
r_ca <= i_ca;
r_aa_mode <= i_aa_mode;
r_x <= i_x;
r_y <= i_y;
r_z <= i_z;
end
end
always @(posedge clk_core) begin
if (w_set_tu) begin
r_tr <= i_tr;
r_tg <= i_tg;
r_tb <= i_tb;
end
end
always @(posedge clk_core) begin
if (w_set_br) r_br <= w_c;
if (w_set_bg) r_bg <= w_c;
if (w_set_bb) r_bb <= w_c;
end
////////////////////////////
// module instance
////////////////////////////
fm_3d_imul8 imul8 (
.i_a(w_a),
.i_b(w_b),
.o_c(w_c)
);
endmodule
|
module fm_3d_tu (
clk_core,
rst_x,
// register configuration
i_tex_enable,
i_tex_format,
i_tex_offset,
i_tex_width_m1_f, // texture width -1
i_tex_height_m1_f, // texture height -1
i_tex_width_ui,
o_idle,
// rasterizer bus
i_valid,
i_tu,
i_tv,
o_busy,
// pixel unit bus
o_valid,
o_tr,
o_tg,
o_tb,
o_ta,
i_busy,
// memory bus
o_req,
o_adrs,
i_ack,
o_len,
i_strr,
i_dbr
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
// main state
parameter P_IDLE = 3'd0;
parameter P_ADRS_GEN = 3'd1;
parameter P_REQ = 3'd2;
parameter P_WAIT_RDATA0 = 3'd3;
parameter P_WAIT_RDATA1 = 3'd4;
parameter P_ETC0 = 3'd5;
parameter P_ETC1 = 3'd6;
parameter P_OUT = 3'd7;
// address generation state
parameter P_AGEN_IDLE = 3'd0;
parameter P_AGEN_WAIT = 3'd1;
parameter P_AGEN_FMUL_U = 3'd2;
parameter P_AGEN_FMUL_V = 3'd3;
parameter P_AGEN_SET = 3'd4;
// texture format
parameter P_R5G6B5 = 3'd0;
parameter P_R5G5B5A1 = 3'd1;
parameter P_R4G4B4A4 = 3'd2;
parameter P_R8G8B8A8 = 3'd3;
parameter P_ETC = 3'd4;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// register configuration
input i_tex_enable;
input [2:0] i_tex_format;
input [11:0]
i_tex_offset;
input [21:0] i_tex_width_m1_f;
input [21:0] i_tex_height_m1_f;
input [11:0] i_tex_width_ui;
output o_idle;
// rasterizer bus
input i_valid;
input [21:0] i_tu;
input [21:0] i_tv;
output o_busy;
// pixel unit bus
output o_valid;
output [7:0] o_tr;
output [7:0] o_tg;
output [7:0] o_tb;
output [7:0] o_ta;
input i_busy;
// memory bus
output o_req;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs;
input i_ack;
output [P_IB_LEN_WIDTH-1:0] o_len;
input i_strr;
input [P_IB_DATA_WIDTH-1:0] i_dbr;
////////////////////////////
// reg
////////////////////////////
reg [2:0] r_state;
reg [2:0] r_agen_state;
reg [P_IB_ADDR_WIDTH-1:0]
r_adrs;
`ifdef PP_BUSWIDTH_64
reg [1:0] r_adrs_lsb0;
`else
reg r_adrs_lsb0;
`endif
reg [1:0] r_u_sub;
reg [1:0] r_v_sub;
reg [7:0] r_tr;
reg [7:0] r_tg;
reg [7:0] r_tb;
reg [7:0] r_ta;
reg [P_IB_DATA_WIDTH-1:0] r_dbr;
reg [21:0] r_tv;
reg [15:0] r_tu_ui;
////////////////////////////
// wire
////////////////////////////
wire [18:0] w_mul_tmp;
wire [18:0] w_mul_tmp_a;
wire [P_IB_ADDR_WIDTH-1:0]
w_linear_address;
wire w_set_address;
wire w_agen_start;
wire w_agen_proc_end;
wire w_set_color;
wire [21:0] w_fmul_a;
wire [21:0] w_fmul_b;
wire [21:0] w_tuv_f;
wire [15:0] w_tuv_ui;
wire w_set_tu_ui;
wire [7:0] w_tr_etc;
wire [7:0] w_tg_etc;
wire [7:0] w_tb_etc;
wire w_set_rd;
////////////////////////////
// assign
////////////////////////////
assign o_idle = (r_state == P_IDLE);
assign o_busy = (r_state != P_IDLE);
assign w_mul_tmp = (i_tex_format == P_ETC) ? w_tuv_ui[9:2] * i_tex_width_ui[9:2]:
w_tuv_ui[9:0] * i_tex_width_ui[9:0];
assign w_mul_tmp_a = (i_tex_format == P_ETC) ? w_mul_tmp + r_tu_ui[9:2]: // 15bits +8bits
w_mul_tmp + r_tu_ui[9:0]; //19bits+10bits
assign w_linear_address = (i_tex_format == P_R8G8B8A8) ? {i_tex_offset,w_mul_tmp_a[17:0]} :
(i_tex_format == P_ETC) ? {i_tex_offset,w_mul_tmp_a[16:0],1'b0} :
{i_tex_offset,w_mul_tmp_a[18:1]};
assign w_set_address = (r_agen_state == P_AGEN_SET);
assign w_set_rd = (r_state == P_WAIT_RDATA0) & i_strr;
assign w_agen_start = (r_state == P_IDLE) & i_valid;
assign w_agen_proc_end = (r_agen_state == P_AGEN_SET);
assign w_fmul_a = (r_agen_state == P_AGEN_IDLE) ? i_tu : r_tv;
assign w_fmul_b = (r_agen_state == P_AGEN_IDLE) ? i_tex_width_m1_f : i_tex_height_m1_f;
assign w_set_tu_ui = (r_agen_state == P_AGEN_FMUL_V);
assign o_req = (r_state == P_REQ);
assign o_adrs = r_adrs;
`ifdef PP_BUSWIDTH_64
assign o_len = 6'd1;
`else
assign o_len = (i_tex_format == P_ETC) ? 6'd2: 6'd1;
`endif
assign w_set_color = (i_tex_format == P_ETC) ? (r_state == P_ETC0) : i_strr;
assign o_tr = r_tr;
assign o_tg = r_tg;
assign o_tb = r_tb;
assign o_ta = r_ta;
assign o_valid = (r_state == P_OUT);
////////////////////////////
// always
////////////////////////////
// main sequence
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE:begin
if (i_valid) r_state <= P_ADRS_GEN;
end
P_ADRS_GEN:begin
if (w_agen_proc_end) r_state <= P_REQ;
end
P_REQ:begin
if (i_ack) r_state <= P_WAIT_RDATA0;
end
P_WAIT_RDATA0:begin
if (i_strr) begin
`ifdef PP_BUSWIDTH_64
if (i_tex_format == P_ETC) r_state <= P_ETC0;
else r_state <= P_OUT;
`else
if (i_tex_format == P_ETC) r_state <= P_WAIT_RDATA1;
else r_state <= P_OUT;
`endif
end
end
P_WAIT_RDATA1:begin
if (i_strr) r_state <= P_ETC0;
end
P_ETC0:begin
r_state <= P_OUT;
end
//P_ETC1:begin
// r_state <= P_OUT;
//end
P_OUT:begin
if (!i_busy) r_state <= P_IDLE;
end
endcase
end
end
// address generation sequence
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_agen_state <= P_AGEN_IDLE;
end else begin
case (r_agen_state)
P_AGEN_IDLE: begin
if (w_agen_start) r_agen_state <= P_AGEN_WAIT;
end
P_AGEN_WAIT: begin
r_agen_state <= P_AGEN_FMUL_U;
end
P_AGEN_FMUL_U: begin
r_agen_state <= P_AGEN_FMUL_V;
end
P_AGEN_FMUL_V: begin
r_agen_state <= P_AGEN_SET;
end
P_AGEN_SET: begin
r_agen_state <= P_AGEN_IDLE;
end
endcase
end
end
always @(posedge clk_core) begin
if (w_agen_start) r_tv <= i_tv;
end
always @(posedge clk_core) begin
if (w_set_tu_ui) r_tu_ui <= w_tuv_ui;
end
always @(posedge clk_core) begin
if (w_set_address) begin
`ifdef PP_BUSWIDTH_64
r_adrs <= w_linear_address[P_IB_ADDR_WIDTH-1:1];
r_adrs_lsb0 <= w_mul_tmp_a[1:0];
`else
r_adrs <= w_linear_address;
r_adrs_lsb0 <= w_mul_tmp_a[0];
`endif
r_u_sub <= r_tu_ui[1:0];
r_v_sub <= w_tuv_ui[1:0];
end
end
always @(posedge clk_core) begin
if (w_set_rd) begin
r_dbr <= i_dbr;
end
end
always @(posedge clk_core) begin
if (w_set_color) begin
r_tr <= (i_tex_format == P_ETC) ? w_tr_etc :
f_set_color_r(i_dbr, r_adrs_lsb0,i_tex_format);
r_tg <= (i_tex_format == P_ETC) ? w_tg_etc :
f_set_color_g(i_dbr, r_adrs_lsb0,i_tex_format);
r_tb <= (i_tex_format == P_ETC) ? w_tb_etc :
f_set_color_b(i_dbr, r_adrs_lsb0,i_tex_format);
r_ta <= (i_tex_format == P_ETC) ? 8'hff :
f_set_color_a(i_dbr, r_adrs_lsb0,i_tex_format);
end
end
////////////////////////////
// function
////////////////////////////
function [7:0] f_set_color_r;
input [P_IB_DATA_WIDTH-1:0] dbr;
`ifdef PP_BUSWIDTH_64
input [1:0] adr_lsb;
`else
input adr_lsb;
`endif
input [2:0] mode;
reg [15:0] sdbr;
begin
`ifdef PP_BUSWIDTH_64
sdbr = (adr_lsb == 'd1) ? dbr[31:16] :
(adr_lsb == 'd2) ? dbr[47:32] :
(adr_lsb == 'd3) ? dbr[63:48] :
dbr[15:0];
`else
sdbr = (adr_lsb) ? dbr[31:16] : dbr[15:0];
`endif
case (mode)
P_R8G8B8A8 : begin
// R8G8B8A8
f_set_color_r = dbr[31:24];
end
P_R5G5B5A1 : begin
// R5G5B5A1
f_set_color_r = {sdbr[15:11],sdbr[15:13]};
end
P_R5G6B5 : begin
// R5G6B5
f_set_color_r = {sdbr[15:11],sdbr[15:13]};
end
P_R4G4B4A4 : begin
// R4G4B4A4
f_set_color_r = {sdbr[15:12],sdbr[15:12]};
end
default : begin
f_set_color_r = dbr[31:24];
end
endcase
end
endfunction
function [7:0] f_set_color_g;
input [P_IB_DATA_WIDTH-1:0] dbr;
`ifdef PP_BUSWIDTH_64
input [1:0] adr_lsb;
`else
input adr_lsb;
`endif
input [2:0] mode;
reg [15:0] sdbr;
begin
`ifdef PP_BUSWIDTH_64
sdbr = (adr_lsb == 'd1) ? dbr[31:16] :
(adr_lsb == 'd2) ? dbr[47:32] :
(adr_lsb == 'd3) ? dbr[63:48] :
dbr[15:0];
`else
sdbr = (adr_lsb) ? dbr[31:16] : dbr[15:0];
`endif
case (mode)
P_R8G8B8A8 : begin
// R8G8B8A8
f_set_color_g = dbr[23:16];
end
P_R5G5B5A1 : begin
// R5G5B5A1
f_set_color_g = {sdbr[10:6],sdbr[10:8]};
end
P_R5G6B5 : begin
// R5G6B5
f_set_color_g = {sdbr[10:5],sdbr[10:9]};
end
P_R4G4B4A4 : begin
// R4G4B4A4
f_set_color_g = {sdbr[11:8],sdbr[11:8]};
end
default : begin
f_set_color_g = dbr[23:16];
end
endcase
end
endfunction
function [7:0] f_set_color_b;
input [P_IB_DATA_WIDTH-1:0] dbr;
`ifdef PP_BUSWIDTH_64
input [1:0] adr_lsb;
`else
input adr_lsb;
`endif
input [2:0] mode;
reg [15:0] sdbr;
begin
`ifdef PP_BUSWIDTH_64
sdbr = (adr_lsb == 'd1) ? dbr[31:16] :
(adr_lsb == 'd2) ? dbr[47:32] :
(adr_lsb == 'd3) ? dbr[63:48] :
dbr[15:0];
`else
sdbr = (adr_lsb) ? dbr[31:16] : dbr[15:0];
`endif
case (mode)
P_R8G8B8A8 : begin
// R8G8B8A8
f_set_color_b = dbr[15:8];
end
P_R5G5B5A1 : begin
// R5G5B5A1
f_set_color_b = {sdbr[5:1],sdbr[5:3]};
end
P_R5G6B5 : begin
// R5G6B5
f_set_color_b = {sdbr[4:0],sdbr[4:2]};
end
P_R4G4B4A4 : begin
// R4G4B4A4
f_set_color_b = {sdbr[7:4],sdbr[7:4]};
end
default : begin
f_set_color_b = dbr[15:8];
end
endcase
end
endfunction
function [7:0] f_set_color_a;
input [P_IB_DATA_WIDTH-1:0] dbr;
`ifdef PP_BUSWIDTH_64
input [1:0] adr_lsb;
`else
input adr_lsb;
`endif
input [2:0] mode;
reg [15:0] sdbr;
begin
`ifdef PP_BUSWIDTH_64
sdbr = (adr_lsb == 'd1) ? dbr[31:16] :
(adr_lsb == 'd2) ? dbr[47:32] :
(adr_lsb == 'd3) ? dbr[63:48] :
dbr[15:0];
`else
sdbr = (adr_lsb) ? dbr[31:16] : dbr[15:0];
`endif
case (mode)
P_R8G8B8A8 : begin
// R8G8B8A8
f_set_color_a = dbr[7:0];
end
P_R5G5B5A1 : begin
// R5G5B5A1
f_set_color_a = {8{sdbr[0]}};
end
P_R4G4B4A4 : begin
// R4G4B4A4
f_set_color_a = {sdbr[3:0],sdbr[3:0]};
end
default : begin
f_set_color_a = 8'hff;
end
endcase
end
endfunction
////////////////////////////
// module instance
////////////////////////////
// ETC decoder
fm_3d_tu_etc tu_etc (
.clk_core(clk_core),
.i_u_sub(r_u_sub),
.i_v_sub(r_v_sub),
`ifdef PP_BUSWIDTH_64
.i_code_l32(i_dbr[63:32]),
.i_code_u32(i_dbr[31:0]),
`else
.i_code_l32(i_dbr),
.i_code_u32(r_dbr),
`endif
.o_r(w_tr_etc),
.o_g(w_tg_etc),
.o_b(w_tb_etc)
);
// tu/tv
fm_3d_fmul fmul_tuv (
.clk_core(clk_core),
.i_en(1'b1),
.i_a(w_fmul_a),
.i_b(w_fmul_b),
.o_c(w_tuv_f)
);
fm_3d_f22_to_ui_b ftoui_tuv (
.i_a(w_tuv_f),
.o_b(w_tuv_ui)
);
endmodule
|
module fm_3d_mu_cache_mem (
clk_core,
i_we,
i_adrs,
i_adrs_pre,
i_be,
i_dt,
o_dt,
o_dt_pre
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
parameter P_RANGE = P_IB_CACHE_ENTRY_WIDTH+P_IB_CACHE_LINE_WIDTH;
parameter P_DEPTH = 1 << P_RANGE;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input i_we;
input [P_RANGE-1:0]
i_adrs;
input [P_RANGE-1:0]
i_adrs_pre;
input [P_IB_DATA_WIDTH/8-1:0]
i_be;
input [P_IB_DATA_WIDTH-1:0]
i_dt;
output [P_IB_DATA_WIDTH-1:0]
o_dt;
output [P_IB_DATA_WIDTH-1:0]
o_dt_pre;
//////////////////////////////////
// wire
//////////////////////////////////
wire [P_IB_BE_WIDTH/2-1:0]
w_we;
//////////////////////////////////
// assign
//////////////////////////////////
////////////////////////////
// module instance
////////////////////////////
genvar gi;
// per 16-bit byte enable
generate for (gi=0;gi < P_IB_BE_WIDTH/2;gi=gi+1) begin
assign w_we[gi] = i_we & (|i_be[gi*2+1:gi*2]);
fm_cmn_bram_01 #(16, P_RANGE) bram (
.clk(clk_core),
.we(w_we[gi]),
.a(i_adrs),
.dpra(i_adrs_pre),
.di(i_dt[(gi+1)*16-1:gi*16]),
.spo(o_dt[(gi+1)*16-1:gi*16]),
.dpo(o_dt_pre[(gi+1)*16-1:gi*16])
);
end
endgenerate
endmodule
|
module fm_3d_f22_to_ui (
i_a,
o_b
);
///////////////////////////////////////////
// port definition
///////////////////////////////////////////
input [21:0] i_a; // input s1, e5, f1.15
output [15:0] o_b; // unsigned integer
///////////////////////////////////////////
// wire definition
///////////////////////////////////////////
// intermidiate wire
wire [4:0] w_exp;
wire [15:0] w_fraction;
///////////////////////////////////////////
// assign statement
///////////////////////////////////////////
assign w_exp = i_a[20:16];
assign w_fraction = i_a[15:0];
assign o_b = f_ftoi(w_exp, w_fraction);
///////////////////////////////////////////
// function statement
///////////////////////////////////////////
function [15:0] f_ftoi;
input [4:0] exp;
input [15:0] frac;
reg [5:0] ee;
begin
ee = exp - 4'd15; // remove bias
if (ee[5]) begin
f_ftoi = 16'h0;
end else begin
case (ee[4:0])
5'd0: f_ftoi = {15'b0,frac[15]}; // bias 0
5'd1: f_ftoi = {14'b0,frac[15:14]};
5'd2: f_ftoi = {13'b0,frac[15:13]};
5'd3: f_ftoi = {12'b0,frac[15:12]};
5'd4: f_ftoi = {11'b0,frac[15:11]};
5'd5: f_ftoi = {10'b0,frac[15:10]};
5'd6: f_ftoi = {9'b0,frac[15:9]};
5'd7: f_ftoi = {8'b0,frac[15:8]};
5'd8: f_ftoi = {7'b0,frac[15:7]};
5'd9: f_ftoi = {6'b0,frac[15:6]};
5'd10: f_ftoi = {5'b0,frac[15:5]};
5'd11: f_ftoi = {4'b0,frac[15:4]};
5'd12: f_ftoi = {3'b0,frac[15:3]};
5'd13: f_ftoi = {2'b0,frac[15:2]};
5'd14: f_ftoi = {1'b0,frac[15:1]};
5'd15: f_ftoi = frac[15:0];
default: f_ftoi = 16'h0;
endcase
end
end
endfunction
endmodule
|
module fm_3d_ru_outline (
clk_core,
rst_x,
// triangle data
i_valid,
i_ml,
o_ack,
i_vtx0_x,
i_vtx0_y,
i_vtx0_z,
i_vtx0_iw,
i_vtx0_p00,
i_vtx0_p01,
i_vtx0_p02,
i_vtx0_p03,
i_vtx0_p10,
i_vtx0_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx0_p12,
i_vtx0_p13,
`endif
i_vtx1_x,
i_vtx1_y,
i_vtx1_z,
i_vtx1_iw,
i_vtx1_p00,
i_vtx1_p01,
i_vtx1_p02,
i_vtx1_p03,
i_vtx1_p10,
i_vtx1_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx1_p12,
i_vtx1_p13,
`endif
i_vtx2_x,
i_vtx2_y,
i_vtx2_z,
i_vtx2_iw,
i_vtx2_p00,
i_vtx2_p01,
i_vtx2_p02,
i_vtx2_p03,
i_vtx2_p10,
i_vtx2_p11,
`ifdef VTX_PARAM1_REDUCE
`else
i_vtx2_p12,
i_vtx2_p13,
`endif
// control registers
i_aa_en,
i_attr0_en,
i_attr0_size,
i_attr0_kind,
i_attr1_en,
i_attr1_size,
i_attr1_kind,
o_idle,
// edge data
o_valid,
o_aa_mode,
i_ack,
// edge data left
o_x_l,
o_y_l,
o_z_l,
o_iw_l,
o_param00_l,
o_param01_l,
o_param02_l,
o_param03_l,
o_param10_l,
o_param11_l,
`ifdef VTX_PARAM1_REDUCE
`else
o_param12_l,
o_param13_l,
`endif
// edge data right
o_x_r,
o_y_r,
o_z_r,
o_iw_r,
o_param00_r,
o_param01_r,
o_param02_r,
o_param03_r,
o_param10_r,
o_param11_r
`ifdef VTX_PARAM1_REDUCE
`else
,o_param12_r,
o_param13_r
`endif
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// triangle data
input i_valid;
input i_ml;
output o_ack;
input [20:0] i_vtx0_x;
input [20:0] i_vtx0_y;
input [20:0] i_vtx0_z;
input [20:0] i_vtx0_iw;
input [20:0] i_vtx0_p00;
input [20:0] i_vtx0_p01;
input [20:0] i_vtx0_p02;
input [20:0] i_vtx0_p03;
input [20:0] i_vtx0_p10;
input [20:0] i_vtx0_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx0_p12;
input [20:0] i_vtx0_p13;
`endif
input [20:0] i_vtx1_x;
input [20:0] i_vtx1_y;
input [20:0] i_vtx1_z;
input [20:0] i_vtx1_iw;
input [20:0] i_vtx1_p00;
input [20:0] i_vtx1_p01;
input [20:0] i_vtx1_p02;
input [20:0] i_vtx1_p03;
input [20:0] i_vtx1_p10;
input [20:0] i_vtx1_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx1_p12;
input [20:0] i_vtx1_p13;
`endif
input [20:0] i_vtx2_x;
input [20:0] i_vtx2_y;
input [20:0] i_vtx2_z;
input [20:0] i_vtx2_iw;
input [20:0] i_vtx2_p00;
input [20:0] i_vtx2_p01;
input [20:0] i_vtx2_p02;
input [20:0] i_vtx2_p03;
input [20:0] i_vtx2_p10;
input [20:0] i_vtx2_p11;
`ifdef VTX_PARAM1_REDUCE
`else
input [20:0] i_vtx2_p12;
input [20:0] i_vtx2_p13;
`endif
// control registers
input i_aa_en;
input i_attr0_en;
input [1:0] i_attr0_size;
input [1:0] i_attr0_kind;
input i_attr1_en;
input [1:0] i_attr1_size;
input [1:0] i_attr1_kind;
output o_idle;
// edge data
output o_valid;
output o_aa_mode;
input i_ack;
// edge data left
output [20:0] o_x_l;
output [8:0] o_y_l;
output [20:0] o_z_l;
output [20:0] o_iw_l;
output [20:0] o_param00_l;
output [20:0] o_param01_l;
output [20:0] o_param02_l;
output [20:0] o_param03_l;
output [20:0] o_param10_l;
output [20:0] o_param11_l;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_param12_l;
output [20:0] o_param13_l;
`endif
// edge data right
output [20:0] o_x_r;
output [8:0] o_y_r;
output [20:0] o_z_r;
output [20:0] o_iw_r;
output [20:0] o_param00_r;
output [20:0] o_param01_r;
output [20:0] o_param02_r;
output [20:0] o_param03_r;
output [20:0] o_param10_r;
output [20:0] o_param11_r;
`ifdef VTX_PARAM1_REDUCE
`else
output [20:0] o_param12_r;
output [20:0] o_param13_r;
`endif
////////////////////////////
// wire
////////////////////////////
// outline parameters
wire w_is_first;
wire w_is_second;
wire w_valid;
wire w_aa_mode;
// edge0
wire [20:0] w_start_x_e0;
wire [20:0] w_start_x_05_e0;
wire [20:0] w_start_y_e0;
wire [20:0] w_end_y_e0;
wire [21:0] w_delta_e0;
wire [21:0] w_delta_t_e0;
wire [21:0] w_delta_a_e0;
// edge1
wire [20:0] w_start_x_e1;
wire [20:0] w_start_x_05_e1;
wire [20:0] w_start_y_e1;
wire [20:0] w_end_y_e1;
wire [21:0] w_delta_e1;
wire [21:0] w_delta_t_e1;
wire [21:0] w_delta_a_e1;
// edge2
wire [20:0] w_start_x_e2;
wire [20:0] w_start_x_05_e2;
wire [20:0] w_start_y_e2;
wire [20:0] w_end_y_e2;
wire [21:0] w_delta_e2;
wire [21:0] w_delta_t_e2;
wire [21:0] w_delta_a_e2;
wire w_ack;
wire w_valid_l;
wire w_valid_r;
wire w_idle_setup;
wire w_idle_edge;
////////////////////////////
// assign
////////////////////////////
assign o_valid = w_valid_l & w_valid_r;
assign o_idle = w_idle_setup & w_idle_edge;
assign o_aa_mode = w_aa_mode;
////////////////////////////
// module instance
////////////////////////////
fm_3d_ru_outline_setup outline_setup (
.clk_core(clk_core),
.rst_x(rst_x),
// control registers
.i_aa_en(i_aa_en),
// triangle data
.i_valid(i_valid),
.o_ack(o_ack),
.i_vtx0_x(i_vtx0_x),
.i_vtx0_y(i_vtx0_y),
.i_vtx1_x(i_vtx1_x),
.i_vtx1_y(i_vtx1_y),
.i_vtx2_x(i_vtx2_x),
.i_vtx2_y(i_vtx2_y),
// parameter out
.o_valid(w_valid),
.o_is_first(w_is_first),
.o_is_second(w_is_second),
.o_aa_mode(w_aa_mode),
// idle state indicator
.o_idle(w_idle_setup),
// edge0
.o_start_x_e0(w_start_x_e0),
.o_start_x_05_e0(w_start_x_05_e0),
.o_start_y_e0(w_start_y_e0),
.o_end_y_e0(w_end_y_e0),
.o_delta_e0(w_delta_e0),
.o_delta_t_e0(w_delta_t_e0),
.o_delta_a_e0(w_delta_a_e0),
// edge1
.o_start_x_e1(w_start_x_e1),
.o_start_x_05_e1(w_start_x_05_e1),
.o_start_y_e1(w_start_y_e1),
.o_end_y_e1(w_end_y_e1),
.o_delta_e1(w_delta_e1),
.o_delta_t_e1(w_delta_t_e1),
.o_delta_a_e1(w_delta_a_e1),
// edge2
.o_start_x_e2(w_start_x_e2),
.o_start_x_05_e2(w_start_x_05_e2),
.o_start_y_e2(w_start_y_e2),
.o_end_y_e2(w_end_y_e2),
.o_delta_e2(w_delta_e2),
.o_delta_t_e2(w_delta_t_e2),
.o_delta_a_e2(w_delta_a_e2),
.i_ack(w_ack)
);
fm_3d_ru_outline_edge outline_edge (
.clk_core(clk_core),
.rst_x(rst_x),
// outline parameters
.i_ml(i_ml),
.i_is_first(w_is_first),
.i_is_second(w_is_second),
.i_valid(w_valid),
.i_aa_mode(w_aa_mode),
// idle state indicator
.o_idle(w_idle_edge),
// edge0
.i_start_x_e0(w_start_x_e0),
.i_start_x_05_e0(w_start_x_05_e0),
.i_start_y_e0(w_start_y_e0),
.i_end_y_e0(w_end_y_e0),
.i_delta_e0(w_delta_e0),
.i_delta_t_e0(w_delta_t_e0),
.i_delta_a_e0(w_delta_a_e0),
// edge1
.i_start_x_e1(w_start_x_e1),
.i_start_x_05_e1(w_start_x_05_e1),
.i_start_y_e1(w_start_y_e1),
.i_end_y_e1(w_end_y_e1),
.i_delta_e1(w_delta_e1),
.i_delta_t_e1(w_delta_t_e1),
.i_delta_a_e1(w_delta_a_e1),
// edge2
.i_start_x_e2(w_start_x_e2),
.i_start_x_05_e2(w_start_x_05_e2),
.i_start_y_e2(w_start_y_e2),
.i_end_y_e2(w_end_y_e2),
.i_delta_e2(w_delta_e2),
.i_delta_t_e2(w_delta_t_e2),
.i_delta_a_e2(w_delta_a_e2),
.o_ack(w_ack),
// triangle data
.i_vtx0_z(i_vtx0_z),
.i_vtx0_iw(i_vtx0_iw),
.i_vtx0_p00(i_vtx0_p00),
.i_vtx0_p01(i_vtx0_p01),
.i_vtx0_p02(i_vtx0_p02),
.i_vtx0_p03(i_vtx0_p03),
.i_vtx0_p10(i_vtx0_p10),
.i_vtx0_p11(i_vtx0_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx0_p12(i_vtx0_p12),
.i_vtx0_p13(i_vtx0_p13),
`endif
.i_vtx1_z(i_vtx1_z),
.i_vtx1_iw(i_vtx1_iw),
.i_vtx1_p00(i_vtx1_p00),
.i_vtx1_p01(i_vtx1_p01),
.i_vtx1_p02(i_vtx1_p02),
.i_vtx1_p03(i_vtx1_p03),
.i_vtx1_p10(i_vtx1_p10),
.i_vtx1_p11(i_vtx1_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx1_p12(i_vtx1_p12),
.i_vtx1_p13(i_vtx1_p13),
`endif
.i_vtx2_z(i_vtx2_z),
.i_vtx2_iw(i_vtx2_iw),
.i_vtx2_p00(i_vtx2_p00),
.i_vtx2_p01(i_vtx2_p01),
.i_vtx2_p02(i_vtx2_p02),
.i_vtx2_p03(i_vtx2_p03),
.i_vtx2_p10(i_vtx2_p10),
.i_vtx2_p11(i_vtx2_p11),
`ifdef VTX_PARAM1_REDUCE
`else
.i_vtx2_p12(i_vtx2_p12),
.i_vtx2_p13(i_vtx2_p13),
`endif
// control registers
.i_param0_en(i_attr0_en),
.i_param1_en(i_attr1_en),
.i_param0_size(i_attr0_size),
.i_param1_size(i_attr1_size),
// output left
.o_valid_l(w_valid_l),
.i_busy_l(!i_ack),
.o_x_l(o_x_l),
.o_y_l(o_y_l),
.o_z_l(o_z_l),
.o_iw_l(o_iw_l),
.o_param00_l(o_param00_l),
.o_param01_l(o_param01_l),
.o_param02_l(o_param02_l),
.o_param03_l(o_param03_l),
.o_param10_l(o_param10_l),
.o_param11_l(o_param11_l),
`ifdef VTX_PARAM1_REDUCE
`else
.o_param12_l(o_param12_l),
.o_param13_l(o_param13_l),
`endif
// output right
.o_valid_r(w_valid_r),
.i_busy_r(!i_ack),
.o_x_r(o_x_r),
.o_y_r(o_y_r),
.o_z_r(o_z_r),
.o_iw_r(o_iw_r),
.o_param00_r(o_param00_r),
.o_param01_r(o_param01_r),
.o_param02_r(o_param02_r),
.o_param03_r(o_param03_r),
.o_param10_r(o_param10_r),
.o_param11_r(o_param11_r)
`ifdef VTX_PARAM1_REDUCE
`else
,.o_param12_r(o_param12_r),
.o_param13_r(o_param13_r)
`endif
);
endmodule
|
module fm_3d_ru_outline_step_core (
clk_core,
i_en,
i_valid,
i_kind,
i_end_flag,
i_start_p,
i_end_p,
i_start_iw,
i_end_iw,
i_delta_t,
i_apply_iw,
o_valid,
o_kind,
o_end_flag,
o_start_p,
o_step_p
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input i_en;
input i_valid;
input [3:0] i_kind;
input i_end_flag;
input [20:0] i_start_p;
input [20:0] i_end_p;
input [20:0] i_start_iw;
input [20:0] i_end_iw;
input [21:0] i_delta_t;
input i_apply_iw;
output o_valid;
output [3:0] o_kind;
output o_end_flag;
output [20:0] o_start_p;
output [21:0] o_step_p;
////////////////////////////
// wire
////////////////////////////
wire [21:0] w_start_iw;
wire [21:0] w_end_iw;
wire [21:0] w_end_p;
wire [21:0] w_start_p;
wire [21:0] w_delta_p;
wire [21:0] w_10;
////////////////////////////
// assign
////////////////////////////
assign w_10 = {1'b0, 5'h0f, 16'h8000};
assign w_start_iw = (i_apply_iw) ? {1'b0,i_start_iw} : w_10;
assign w_end_iw = (i_apply_iw) ? {1'b0,i_end_iw} : w_10;
////////////////////////////
// module instance
////////////////////////////
// end * iw
fm_3d_fmul mul_end (
.clk_core(clk_core),
.i_en(i_en),
.i_a({1'b0,i_end_p}),
.i_b(w_end_iw),
.o_c(w_end_p)
);
// start * iw
fm_3d_fmul mul_start (
.clk_core(clk_core),
.i_en(i_en),
.i_a({1'b0,i_start_p}),
.i_b(w_start_iw),
.o_c(w_start_p)
);
// adder (end_p - start_p)
fm_3d_fadd fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_end_p),
.i_b(w_start_p),
.i_adsb(1'b1),
.o_c(w_delta_p)
);
// delta_p * delta_t (not necessary to add delay to delta_t, t is static)
fm_3d_fmul mul_delta_tp (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_delta_p),
.i_b(i_delta_t),
.o_c(o_step_p)
);
// delay adjust for o_start_p
fm_3d_delay #(21,6) delay_p (
.clk_core(clk_core),
.i_en(i_en),
.i_data(w_start_p[20:0]),
.o_data(o_start_p)
);
// delay adjust for valid
fm_3d_delay #(1,9) delay_valid (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_valid),
.o_data(o_valid)
);
fm_3d_delay #(1,9) delay_end_flag (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_end_flag),
.o_data(o_end_flag)
);
fm_3d_delay #(4,9) delay_kind (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_kind),
.o_data(o_kind)
);
endmodule
|
module fm_3d_pu (
clk_core,
rst_x,
// register configuration
i_tex_enable,
i_tex_blend_enable,
i_color_offset,
i_color_ms_offset,
i_depth_offset,
i_depth_ms_offset,
i_depth_test_en,
i_depth_func,
i_color_blend_en,
i_color_blend_eq,
i_color_blend_sf,
i_color_blend_df,
i_color_mask,
i_color_mode,
i_screen_flip,
i_ag_mode,
o_idle,
// rasterizer unit
i_valid_ru,
i_aa_mode,
i_x,
i_y,
i_z,
i_cr,
i_cg,
i_cb,
i_ca,
o_busy_ru,
// texture unit
i_valid_tu,
i_tr,
i_tg,
i_tb,
i_ta,
o_busy_tu,
// color
o_req_cb,
o_wr_cb,
o_adrs_cb,
i_ack_cb,
o_len_cb,
o_be_cb,
o_strw_cb,
o_dbw_cb,
i_ackw_cb,
i_strr_cb,
i_dbr_cb,
// depth
o_req_db,
o_wr_db,
o_adrs_db,
i_ack_db,
o_len_db,
o_be_db,
o_strw_db,
o_dbw_db,
i_ackw_db,
i_strr_db,
i_dbr_db
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
localparam P_WIDTH = 10'd640;
localparam P_HEIGHT = 9'd480;
// main state
localparam P_IDLE = 2'd0;
localparam P_DEPTH_PROC = 2'd1;
localparam P_COLOR_PROC = 2'd2;
// depth state
localparam P_DEPTH_IDLE = 3'd0;
localparam P_DEPTH_RREQ = 3'd1;
localparam P_DEPTH_WAIT_RDATA = 3'd2;
localparam P_DEPTH_TEST = 3'd3;
localparam P_DEPTH_WREQ = 3'd4;
// color state
localparam P_COLOR_IDLE = 3'd0;
localparam P_COLOR_RREQ = 3'd1;
localparam P_COLOR_WAIT_RDATA = 3'd2;
localparam P_COLOR_BLEND = 3'd3;
localparam P_COLOR_WREQ = 3'd4;
// depth test
localparam P_DF_NEVER = 3'd2;
localparam P_DF_ALWAYS = 3'd1;
localparam P_DF_LESS = 3'd0;
localparam P_DF_LEQUAL = 3'd3;
localparam P_DF_EQUAL = 3'd4;
localparam P_DF_GREATER = 3'd5;
localparam P_DF_GEQUAL = 3'd6;
localparam P_DF_NOTEQUAL = 3'd7;
// blend equation
localparam P_BEQ_ADD = 3'd0;
localparam P_BEQ_SUB = 3'd1;
localparam P_BEQ_REV_SUB = 3'd2;
localparam P_BEQ_MIN = 3'd3;
localparam P_BEQ_MAX = 3'd4;
localparam P_BEQ_ADD_SCREEN = 3'd5;
// blend factor
localparam P_BF_ZERO = 4'd0;
localparam P_BF_ONE = 4'd1;
localparam P_BF_SRC_COLOR = 4'd2;
localparam P_BF_ONE_MINUS_SRC_COLOR = 4'd3;
localparam P_BF_DST_COLOR = 4'd4;
localparam P_BF_ONE_MINUS_DST_COLOR = 4'd5;
localparam P_BF_SRC_ALPHA = 4'd6;
localparam P_BF_ONE_MINUS_SRC_ALPHA = 4'd7;
localparam P_BF_DST_ALPHA = 4'd8;
localparam P_BF_ONE_MINUS_DST_ALPHA = 4'd9;
localparam P_BF_SRC_CONSTANT_COLOR = 4'd10;
localparam P_BF_ONE_MINUS_CONSTANT_COLOR = 4'd11;
localparam P_BF_SRC_CONSTANT_ALPHA = 4'd12;
localparam P_BF_ONE_MINUS_CONSTANT_ALPHA = 4'd13;
localparam P_BF_SRC_ALPHA_SATURATE = 4'd14;
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
// register configuration
input i_tex_enable;
input i_tex_blend_enable;
input i_depth_test_en;
input [2:0] i_depth_func;
input i_color_blend_en;
input [2:0] i_color_blend_eq;
input [3:0] i_color_blend_sf;
input [3:0] i_color_blend_df;
input [3:0] i_color_mask;
input [11:0] i_color_offset;
input [11:0] i_color_ms_offset;
input [11:0] i_depth_offset;
input [11:0] i_depth_ms_offset;
input [1:0] i_color_mode;
input i_screen_flip;
input i_ag_mode;
output o_idle;
// rasterizer unit
input i_valid_ru;
input i_aa_mode;
input [9:0] i_x;
input [8:0] i_y;
input [15:0] i_z;
input [7:0] i_cr;
input [7:0] i_cg;
input [7:0] i_cb;
input [7:0] i_ca;
output o_busy_ru;
// texture unit
input i_valid_tu;
input [7:0] i_tr;
input [7:0] i_tg;
input [7:0] i_tb;
input [7:0] i_ta;
output o_busy_tu;
// color
output o_req_cb;
output o_wr_cb;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs_cb;
input i_ack_cb;
output [P_IB_LEN_WIDTH-1:0]
o_len_cb;
output [P_IB_BE_WIDTH-1:0]
o_be_cb;
output o_strw_cb;
output [P_IB_DATA_WIDTH-1:0]
o_dbw_cb;
input i_ackw_cb;
input i_strr_cb;
input [P_IB_DATA_WIDTH-1:0]
i_dbr_cb;
// depth
output o_req_db;
output o_wr_db;
output [P_IB_ADDR_WIDTH-1:0]
o_adrs_db;
input i_ack_db;
output [P_IB_LEN_WIDTH-1:0]
o_len_db;
output [P_IB_BE_WIDTH-1:0]
o_be_db;
output o_strw_db;
output [P_IB_DATA_WIDTH-1:0]
o_dbw_db;
input i_ackw_db;
input i_strr_db;
input [P_IB_DATA_WIDTH-1:0]
i_dbr_db;
////////////////////////////
// reg
////////////////////////////
reg [1:0] r_state;
reg [2:0] r_depth_state;
reg [2:0] r_color_state;
reg [15:0] r_dst_db;
`ifdef PP_BUSWIDTH_64
reg [16:0] r_linear_adrs;
reg [1:0] r_linear_adrs_lsb;
`else
reg [17:0] r_linear_adrs;
reg r_linear_adrs_lsb;
`endif
////////////////////////////
// wire
////////////////////////////
// texture blender out
wire w_valid_tb;
wire w_aa_mode_tb;
wire [9:0] w_x_tb;
wire [8:0] w_y_tb;
wire [15:0] w_z_tb;
wire [7:0] w_cr_tb;
wire [7:0] w_cg_tb;
wire [7:0] w_cb_tb;
wire [7:0] w_ca_tb;
wire w_busy_tb;
// fifo out
wire w_aa_mode;
wire [9:0] w_x;
wire [8:0] w_y;
wire [15:0] w_z;
wire [7:0] w_cr;
wire [7:0] w_cg;
wire [7:0] w_cb;
wire [7:0] w_ca;
wire [7:0] w_sr;
wire [7:0] w_sg;
wire [7:0] w_sb;
wire [7:0] w_sa;
wire [7:0] w_br;
wire [7:0] w_bg;
wire [7:0] w_bb;
wire [7:0] w_ba;
wire [7:0] w_fr;
wire [7:0] w_fg;
wire [7:0] w_fb;
wire [7:0] w_fa;
wire [18:0] w_height_mul; // 16bit address
wire [18:0] w_linear_adrs; // 16bit address
wire w_depth_proc_end;
wire w_color_update;
wire w_color_proc_end;
wire w_depth_proc_start;
wire w_depth_update;
wire w_color_write_start;
wire [15:0] w_dst_db;
wire [15:0] w_dst_cb;
wire [15:0] w_new_cb;
wire w_set_dst_db;
wire [8:0] w_y_t;
wire [67:0] w_fifo_in;
wire [67:0] w_fifo_out;
wire w_fifo_ren;
wire w_fifo_empty;
wire w_start;
wire w_start_idle;
wire w_finish_blend;
wire [11:0] w_color_offset;
wire [11:0] w_depth_offset;
wire w_invalid_x;
wire w_discard;
////////////////////////////
// assign
////////////////////////////
assign o_idle = (r_state == P_IDLE)&w_fifo_empty;
assign w_fifo_in = {w_aa_mode_tb,w_x_tb,w_y_tb,w_z_tb,w_cr_tb,w_cg_tb,w_cb_tb,w_ca_tb};
assign {w_aa_mode,
w_x,
w_y,
w_z,
w_cr,
w_cg,
w_cb,
w_ca } = w_fifo_out;
//assign w_color_offset = (w_aa_mode) ? i_color_ms_offset : i_color_offset;
assign w_color_offset = (w_aa_mode|i_ag_mode) ? i_color_ms_offset :
i_color_offset;
//assign w_depth_offset = (w_aa_mode) ? i_depth_ms_offset : i_depth_offset;
assign w_depth_offset = (w_aa_mode|i_ag_mode) ? i_depth_ms_offset :
i_depth_offset;
assign w_sr = w_cr;
assign w_sg = w_cg;
assign w_sb = w_cb;
assign w_sa = w_ca;
assign w_y_t = (i_screen_flip) ? (9'd479 - w_y): w_y;
assign w_height_mul = w_y_t * P_WIDTH;
assign w_linear_adrs = w_height_mul + w_x; // 0 - 4afff
assign w_fifo_ren = ((r_state == P_DEPTH_PROC) & w_depth_proc_end & !w_color_update)|
((r_state == P_COLOR_PROC) & w_color_proc_end) | w_discard;
assign w_start = !w_fifo_empty & !w_invalid_x;
assign w_invalid_x = (w_x >= 10'd640);
assign w_discard = w_invalid_x & !w_fifo_empty;
assign w_start_idle = w_start & (r_state == P_IDLE);
assign w_depth_proc_start = w_start_idle & i_depth_test_en;
assign w_depth_proc_end = ((r_depth_state == P_DEPTH_TEST) & !w_depth_update)|
((r_depth_state == P_DEPTH_WREQ)&i_ack_db);
assign o_req_db = (r_depth_state == P_DEPTH_RREQ) |
(r_depth_state == P_DEPTH_WREQ);
assign o_adrs_db = {w_depth_offset, r_linear_adrs};
assign o_len_db = 6'h1;
assign o_wr_db = (r_depth_state == P_DEPTH_WREQ);
assign o_strw_db = (r_depth_state == P_DEPTH_WREQ);
`ifdef PP_BUSWIDTH_64
assign o_be_db = (r_linear_adrs_lsb == 2'd1 ) ? 8'h0c :
(r_linear_adrs_lsb == 2'd2 ) ? 8'h30 :
(r_linear_adrs_lsb == 2'd3 ) ? 8'hc0 :
8'h3;
assign o_dbw_db = {'d4{w_z}};
assign w_dst_db = (r_linear_adrs_lsb == 2'd1) ? i_dbr_db[31:16]:
(r_linear_adrs_lsb == 2'd2) ? i_dbr_db[47:32]:
(r_linear_adrs_lsb == 2'd3) ? i_dbr_db[63:48]:
i_dbr_db[15:0];
`else
assign o_be_db = (r_linear_adrs_lsb) ? 4'hc : 4'h3;
assign o_dbw_db = {w_z, w_z};
assign w_dst_db = (r_linear_adrs_lsb) ? i_dbr_db[31:16] : i_dbr_db[15:0];
`endif
assign w_set_dst_db = (r_depth_state == P_DEPTH_WAIT_RDATA) & i_strr_db;
assign w_depth_update = f_depth_test(r_dst_db,w_z, i_depth_func);
assign w_color_update = w_depth_update;
assign o_req_cb = (r_color_state == P_COLOR_RREQ) |
(r_color_state == P_COLOR_WREQ);
assign o_adrs_cb = {w_color_offset, r_linear_adrs};
assign o_len_cb = 6'h1;
assign o_wr_cb = (r_color_state == P_COLOR_WREQ);
assign o_strw_cb = (r_color_state == P_COLOR_WREQ);
`ifdef PP_BUSWIDTH_64
assign o_be_cb = (r_linear_adrs_lsb == 2'd1 ) ? 8'h0c :
(r_linear_adrs_lsb == 2'd2 ) ? 8'h30 :
(r_linear_adrs_lsb == 2'd3 ) ? 8'hc0 :
8'h3;
assign o_dbw_cb = {'d4{w_new_cb}};
assign w_dst_cb = (r_linear_adrs_lsb == 2'd1) ? i_dbr_cb[31:16]:
(r_linear_adrs_lsb == 2'd2) ? i_dbr_cb[47:32]:
(r_linear_adrs_lsb == 2'd3) ? i_dbr_cb[63:48]:
i_dbr_cb[15:0];
`else
assign o_be_cb = (r_linear_adrs_lsb) ? 4'hc : 4'h3;
assign o_dbw_cb = {w_new_cb, w_new_cb};
assign w_dst_cb = (r_linear_adrs_lsb) ? i_dbr_cb[31:16] : i_dbr_cb[15:0];
`endif
assign w_fr = (!i_color_mask[0]) ? 8'h00 :
(i_color_blend_en) ? w_br : w_sr;
assign w_fg = (!i_color_mask[1]) ? 8'h00 :
(i_color_blend_en) ? w_bg : w_sg;
assign w_fb = (!i_color_mask[2]) ? 8'h00 :
(i_color_blend_en) ? w_bb : w_sb;
assign w_fa = (!i_color_mask[3]) ? 8'h00 :
(i_color_blend_en) ? w_ba : w_sa;
assign w_new_cb = f_set_color(w_fr,w_fg,w_fb,w_fa, i_color_mode);
assign w_color_write_start = ((r_state == P_DEPTH_PROC) &
w_depth_proc_end & w_color_update) |
(w_start_idle &!i_depth_test_en) ;
assign w_color_proc_end = ((r_color_state == P_COLOR_WREQ)&i_ack_cb);
////////////////////////////
// always
////////////////////////////
// main sequence
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_state <= P_IDLE;
end else begin
case (r_state)
P_IDLE: begin
if (w_start) begin
if (i_depth_test_en) r_state <= P_DEPTH_PROC;
else r_state <= P_COLOR_PROC;
end
end
P_DEPTH_PROC: begin
if (w_depth_proc_end) begin
if (w_color_update) begin
r_state <= P_COLOR_PROC;
end else begin
r_state <= P_IDLE;
end
end
end
P_COLOR_PROC: begin
if (w_color_proc_end) r_state <= P_IDLE;
end
endcase
end
end
// depth sequence
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_depth_state <= P_DEPTH_IDLE;
end else begin
case (r_depth_state)
P_DEPTH_IDLE: begin
if (w_depth_proc_start) r_depth_state <= P_DEPTH_RREQ;
end
P_DEPTH_RREQ: begin
if (i_ack_db) r_depth_state <= P_DEPTH_WAIT_RDATA;
end
P_DEPTH_WAIT_RDATA: begin
if (i_strr_db) r_depth_state <= P_DEPTH_TEST;
end
P_DEPTH_TEST: begin
if (w_depth_update) r_depth_state <= P_DEPTH_WREQ;
else r_depth_state <= P_IDLE;
end
P_DEPTH_WREQ: begin
if (i_ack_db) r_depth_state <= P_DEPTH_IDLE;
end
endcase
end
end
// color sequence
always @(posedge clk_core or negedge rst_x) begin
if (~rst_x) begin
r_color_state <= P_COLOR_IDLE;
end else begin
case (r_color_state)
P_COLOR_IDLE: begin
if (w_color_write_start) begin
if (!i_color_blend_en) r_color_state <= P_COLOR_WREQ;
else r_color_state <= P_COLOR_RREQ;
end
end
P_COLOR_RREQ: begin
if (i_ack_cb) r_color_state <= P_COLOR_WAIT_RDATA;
end
P_COLOR_WAIT_RDATA: begin
if (i_strr_cb)r_color_state <= P_COLOR_BLEND;
end
P_COLOR_BLEND: begin
if (w_finish_blend) r_color_state <= P_COLOR_WREQ;
end
P_COLOR_WREQ: begin
if (i_ack_cb) r_color_state <= P_COLOR_IDLE;
end
endcase
end
end
always @(posedge clk_core) begin
if (w_set_dst_db) r_dst_db <= w_dst_db;
end
always @(posedge clk_core) begin
`ifdef PP_BUSWIDTH_64
r_linear_adrs <= w_linear_adrs[18:2];
r_linear_adrs_lsb <= w_linear_adrs[1:0];
`else
r_linear_adrs <= w_linear_adrs[18:1];
r_linear_adrs_lsb <= w_linear_adrs[0];
`endif
end
////////////////////////////
// function
////////////////////////////
function f_depth_test;
input [15:0] dst;
input [15:0] src;
input [2:0] func;
begin
case (func)
P_DF_NEVER: f_depth_test = 1'b0;
P_DF_ALWAYS: f_depth_test = 1'b1;
P_DF_LESS: f_depth_test = (src < dst) ? 1'b1 : 1'b0;
P_DF_LEQUAL: f_depth_test = (src <= dst) ? 1'b1 : 1'b0;
P_DF_EQUAL: f_depth_test = (src == dst) ? 1'b1 : 1'b0;
P_DF_GREATER: f_depth_test = (src > dst) ? 1'b1 : 1'b0;
P_DF_GEQUAL: f_depth_test = (src >= dst) ? 1'b1 : 1'b0;
P_DF_NOTEQUAL:f_depth_test = (src != dst) ? 1'b1 : 1'b0;
default: f_depth_test = 1'b1;
endcase
end
endfunction
function [15:0] f_set_color;
input [7:0] cr;
input [7:0] cg;
input [7:0] cb;
input [7:0] ca;
input [1:0] mode;
begin
case (mode)
2'b00 : begin
// color mode 5:6:5
f_set_color = {cr[7:3],cg[7:2],cb[7:3]};
end
2'b01 : begin
// color mode 5:5:5:1
f_set_color = {cr[7:3],cg[7:3],cb[7:3], ca[7]};
end
2'b10 : begin
// color mode 4:4:4:4
f_set_color = {cr[7:4],cg[7:4],cb[7:4], ca[7:4]};
end
default : begin
// color mode 4:4:4:4
f_set_color = {cr[7:4],cg[7:4],cb[7:4], ca[7:4]};
end
endcase
end
endfunction
////////////////////////////
// module instance
////////////////////////////
fm_cmn_bfifo #(68, 4) fifo ( // aa_mode,x,y,z,cr,cg,cb,ca
.clk_core(clk_core),
.rst_x(rst_x),
.i_wstrobe(w_valid_tb),
.i_dt(w_fifo_in),
.o_full(w_busy_tb),
.i_renable(w_fifo_ren),
.o_dt(w_fifo_out),
.o_empty(w_fifo_empty),
.o_dnum()
);
fm_3d_color_blend color_blend (
.clk_core(clk_core),
.rst_x(rst_x),
// register configuration
.i_color_mode(i_color_mode),
.i_color_blend_en(i_color_blend_en),
.i_color_blend_eq(i_color_blend_eq),
.i_color_blend_sr(i_color_blend_sf),
.i_color_blend_sd(i_color_blend_df),
// source input
.i_src_valid(w_start_idle),
.i_sr(w_sr),
.i_sg(w_sg),
.i_sb(w_sb),
.i_sa(w_sa),
// destination input
.i_dst_valid(i_strr_cb),
.i_dst(w_dst_cb),
// memory bus
.o_valid(w_finish_blend),
.o_fr(w_br),
.o_fg(w_bg),
.o_fb(w_bb),
.o_fa(w_ba)
);
fm_3d_tex_blend tex_blend (
.clk_core(clk_core),
.rst_x(rst_x),
// ru interface
.i_valid_ru(i_valid_ru),
.i_aa_mode(i_aa_mode),
.i_x(i_x),
.i_y(i_y),
.i_z(i_z),
.i_cr(i_cr),
.i_cg(i_cg),
.i_cb(i_cb),
.i_ca(i_ca),
.o_busy_ru(o_busy_ru),
// texture unit
.i_valid_tu(i_valid_tu),
.i_tr(i_tr),
.i_tg(i_tg),
.i_tb(i_tb),
.i_ta(i_ta),
.o_busy_tu(o_busy_tu),
// configurations
.i_tex_enable(i_tex_enable),
.i_tex_blend_enable(i_tex_blend_enable),
// blend out
.o_valid(w_valid_tb),
.o_aa_mode(w_aa_mode_tb),
.o_x(w_x_tb),
.o_y(w_y_tb),
.o_z(w_z_tb),
.o_br(w_cr_tb),
.o_bg(w_cg_tb),
.o_bb(w_cb_tb),
.o_ba(w_ca_tb),
.i_busy(w_busy_tb)
);
// debug
`ifdef RTL_DEBUG
reg [31:0] r_cnt_ru;
reg [31:0] r_cnt_tu;
initial begin
r_cnt_ru = 0;
r_cnt_tu = 0;
end
always @(posedge clk_core) begin
if (i_valid_tu & !o_busy_tu) r_cnt_tu = r_cnt_tu + 1;
if (i_valid_ru & !o_busy_ru) r_cnt_ru = r_cnt_ru + 1;
end
`endif
endmodule
|
module fm_3d_norm (
i_s,
i_e,
i_f,
o_b
);
///////////////////////////////////////////
// port definition
///////////////////////////////////////////
input i_s; // input s1, e5, f2.15
input [4:0] i_e; // input s1, e5, f2.15
input [16:0] i_f; // input s1, e5, f2.15
output [21:0] o_b; // normalized out
///////////////////////////////////////////
// wire definition
///////////////////////////////////////////
// intermidiate wire
wire w_carry; // fraction carry bit
wire [3:0] w_penc; // result of priority encode
wire w_c_zero; // fraction zero flag
wire w_ce_zero; // exp zero flag
wire [15:0] w_lshifted; // left shifted fraction value
wire [4:0] w_lshift_val; // left shift value
wire [15:0] w_c_fraction;
wire [15:0] w_c_frac;
wire [4:0] w_c_exp; // normalized final exp
wire w_c_sign; // final exp
wire [5:0] w_incdec_out; // result of exp incdec
///////////////////////////////////////////
// assign statement
///////////////////////////////////////////
assign w_carry = i_f[16];
// normalize
// fraction zero flag
assign w_c_zero = (i_f == 17'h0);
// fraction priority encode
// synthesis attribute priority_extract of w_penc is yes;
assign w_penc = f_prenc(i_f[15:0]);
// if w_incdec_out[5] == 1, under flow
assign w_incdec_out = f_incdec(i_e, w_penc, w_carry);
// left shift value for normalize
assign w_lshift_val = w_penc;
// left shift for nornamize
assign w_lshifted = i_f[15:0] << w_lshift_val;
// decide final fraction
assign w_c_frac = (w_carry) ? i_f[16:1] : w_lshifted;
// decide final exp
assign w_c_exp = (w_c_zero|w_incdec_out[5]) ? 5'h0 : w_incdec_out[4:0];
// exp zero flag
assign w_ce_zero = (w_c_exp == 5'h0);
// decide final sign
assign w_c_sign = i_s & !w_ce_zero;
// decide final fraction
assign w_c_fraction = (w_ce_zero) ? 16'h0 : w_c_frac;
// output port connection
assign o_b = {w_c_sign, w_c_exp, w_c_fraction};
///////////////////////////////////////////
// function statement
///////////////////////////////////////////
function [3:0] f_prenc;
input [15:0] mat;
begin
if (mat[15] == 1'b1) begin
f_prenc = 4'h0;
end else if (mat[14] == 1'b1) begin
f_prenc = 4'h1;
end else if (mat[13] == 1'b1) begin
f_prenc = 4'h2;
end else if (mat[12] == 1'b1) begin
f_prenc = 4'h3;
end else if (mat[11] == 1'b1) begin
f_prenc = 4'h4;
end else if (mat[10] == 1'b1) begin
f_prenc = 4'h5;
end else if (mat[9] == 1'b1) begin
f_prenc = 4'h6;
end else if (mat[8] == 1'b1) begin
f_prenc = 4'h7;
end else if (mat[7] == 1'b1) begin
f_prenc = 4'h8;
end else if (mat[6] == 1'b1) begin
f_prenc = 4'h9;
end else if (mat[5] == 1'b1) begin
f_prenc = 4'ha;
end else if (mat[4] == 1'b1) begin
f_prenc = 4'hb;
end else if (mat[3] == 1'b1) begin
f_prenc = 4'hc;
end else if (mat[2] == 1'b1) begin
f_prenc = 4'hd;
end else if (mat[1] == 1'b1) begin
f_prenc = 4'he;
end else begin
f_prenc = 4'hf;
end
end
endfunction
function [5:0] f_incdec;
input [4:0] a;
input [3:0] b;
input inc;
reg [5:0] r_inc;
reg [5:0] r_dec;
reg r_1f_flag;
begin
r_1f_flag = (a == 5'h1f);
r_inc = a + !r_1f_flag;
r_dec = a - b;
f_incdec = (inc) ? r_inc : r_dec;
/*
if (inc) begin
if (a == 5'h1f) f_incdec = a;
else f_incdec = a + 1'b1;
end else begin
f_incdec = a - b;
end
*/
end
endfunction
endmodule
|
module fm_3d_interp_s (
clk_core,
rst_x,
i_en,
i_a,
i_b,
i_t,
i_w,
o_c
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
input i_en;
input [21:0] i_a;
input [21:0] i_b;
input [21:0] i_t;
input [21:0] i_w;
output [21:0] o_c; // result
///////////////////////////////////////////
// wire
///////////////////////////////////////////
wire [21:0] w_wd;
wire [21:0] w_io;
////////////////////////////
// module instance
////////////////////////////
// stage1-9 (interpolate)
fm_3d_interp interp (
.clk_core(clk_core),
.i_en(i_en),
.i_a(i_a),
.i_b(i_b),
.i_t(i_t),
.o_c(w_io)
);
fm_3d_delay #(22,9) delay_wd (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_w),
.o_data(w_wd)
);
// stage 10-12
fm_3d_fmul mul_w (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_io),
.i_b(w_wd),
.o_c(o_c)
);
endmodule
|
module fm_3d_imul8 (
i_a,
i_b,
o_c
);
////////////////////////////
// I/O definition
////////////////////////////
input [7:0] i_a;
input [7:0] i_b;
output [7:0] o_c;
///////////////////////////////////////////
// wire
///////////////////////////////////////////
wire [15:0] w_m0;
wire [15:0] w_m1;
wire [8:0] w_carry;
wire [7:0] w_c;
///////////////////////////////////////////
// assign
///////////////////////////////////////////
assign w_m0 = i_a * i_b;
//assign w_m1 = w_m0 + 8'd128; // original code
assign w_m1[6:0] = w_m0[6:0];
assign w_m1[15:7] = w_m0[15:7] + 1'b1;
assign w_carry = w_m1[7:0] + w_m1[15:8];
assign w_c = w_m1[15:8] + w_carry[8];
assign o_c = w_c;
endmodule
|
module fm_3d_ru_outline_edge_update (
clk_core,
rst_x,
i_en,
i_cur_p,
i_step_p,
i_delta_a,
i_aa_mode,
o_cur_p
);
////////////////////////////
// I/O definition
////////////////////////////
input clk_core;
input rst_x;
input i_en;
input [21:0] i_cur_p;
input [21:0] i_step_p;
input [21:0] i_delta_a;
input i_aa_mode;
output [21:0] o_cur_p;
////////////////////////////
// wire
////////////////////////////
wire [21:0] w_step_p;
wire [21:0] w_cur_p;
wire [21:0] w_step_pp;
wire [21:0] w_cur_pp;
////////////////////////////
// assign
////////////////////////////
assign w_step_pp = (i_aa_mode) ? w_step_p : i_step_p;
assign w_cur_pp = (i_aa_mode) ? w_cur_p : i_cur_p;
////////////////////////////
// module instance
////////////////////////////
// step * delta
fm_3d_fmul mul_delta (
.clk_core(clk_core),
.i_en(i_en),
.i_a(i_step_p),
.i_b(i_delta_a),
.o_c(w_step_p)
);
// delay adjust for delta
fm_3d_delay #(22,3) delay_p (
.clk_core(clk_core),
.i_en(i_en),
.i_data(i_cur_p),
.o_data(w_cur_p)
);
// adder (end_p - start_p)
fm_3d_fadd fadd (
.clk_core(clk_core),
.i_en(i_en),
.i_a(w_cur_pp),
.i_b(w_step_pp),
.i_adsb(1'b0),
.o_c(o_cur_p)
);
endmodule
|
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