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module radix2_div #(
parameter DATAWIDTH = 8
)(
input wire clk,
input wire rstn,
input wire en,
input wire [DATAWIDTH-1:0] dividend,
input wire [DATAWIDTH-1:0] divisor,
output reg ready,
output reg [DATAWIDTH-1:0] quotient,
output reg [DATAWIDTH-1:0] remainder,
output reg vld_out
);
// State encoding
localparam IDLE = 2'b00,
SUB = 2'b01,
SHIFT = 2'b10,
DONE = 2'b11;
// Registers for state machine
reg [1:0] current_state, next_state;
// Extended registers for computation
reg [DATAWIDTH-1:0] dividend_e, divisor_e;
reg [DATAWIDTH-1:0] quotient_e, remainder_e;
reg [DATAWIDTH-1:0] count;
// State machine logic
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
current_state <= IDLE;
end else begin
current_state <= next_state;
end
end
// State transition and output logic
always @(*) begin
// Default assignments
ready = 1'b0;
vld_out = 1'b0;
next_state = current_state;
case (current_state)
IDLE: begin
if (en) begin
next_state = SUB;
quotient_e = 0;
dividend_e = dividend;
divisor_e = divisor << (DATAWIDTH - 1);
count = DATAWIDTH;
end else begin
ready = 1'b1;
end
end
SUB: begin
// Perform subtraction if possible
if (dividend_e >= divisor_e) begin
dividend_e = dividend_e - divisor_e;
quotient_e = (quotient_e << 1) | 1'b1;
end else begin
quotient_e = (quotient_e << 1);
end
next_state = SHIFT;
end
SHIFT: begin
if (count > 0) begin
divisor_e = divisor_e >> 1; // Shift right the divisor
count = count - 1;
next_state = SUB; // Go back to SUB to attempt another subtraction
end else begin
next_state = DONE;
end
end
DONE: begin
quotient = quotient_e;
remainder = dividend_e;
vld_out = 1'b1;
next_state = IDLE; // Return to IDLE after completion
end
endcase
end
// Asynchronous reset logic
always @(negedge rstn) begin
if (!rstn) begin
current_state <= IDLE;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend_e <= 0;
divisor_e <= 0;
quotient_e <= 0;
remainder_e <= 0;
ready <= 1'b1;
vld_out <= 1'b0;
end
end
endmodule |
module accu(
input clk, // Clock input
input rst_n, // Active-low reset
input [7:0] data_in, // 8-bit input data
input valid_in, // Input data valid signal
output reg valid_out, // Output valid signal
output reg [9:0] data_out // 10-bit accumulated output data
);
// Internal signals
reg [9:0] accu_sum; // Accumulator for the sum
reg [1:0] count; // Counter for the input data
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset logic
accu_sum <= 10'd0;
count <= 2'd0;
valid_out <= 1'b0;
data_out <= 10'd0;
end else begin
if (valid_in) begin
// When valid_in is high, accumulate the sum
if (count == 3'd3) begin
// If 4 data points have been received, output the sum
accu_sum <= accu_sum + data_in;
data_out <= accu_sum + data_in; // Include the current data_in in the sum
valid_out <= 1'b1; // Output is valid
count <= 2'd0; // Reset the counter for next cycle
accu_sum <= 10'd0; // Reset the accumulator
end else begin
// If fewer than 4 data points have been received, keep accumulating
accu_sum <= accu_sum + data_in;
count <= count + 2'd1;
valid_out <= 1'b0; // Output is not valid yet
end
end else begin
// If valid_in is low, do nothing
valid_out <= 1'b0; // Maintain output as invalid
end
end
end
endmodule |
module div_16bit(
input [15:0] A, // 16-bit dividend
input [7:0] B, // 8-bit divisor
output reg [15:0] result, // 16-bit quotient
output reg [15:0] odd // 16-bit remainder
);
// Temporary registers to hold intermediate values and shifted divisor
reg [15:0] dividend;
reg [15:0] divisor;
reg [15:0] remainder;
integer i;
always @* begin
// Initialize the values
dividend = A;
divisor = {B, 8'd0}; // Align the divisor with the higher bits of the dividend
remainder = 0;
result = 0;
// Loop to process each bit from MSB to LSB
for (i = 0; i < 16; i = i + 1) begin
// Shift remainder and bring down the next bit of the dividend
remainder = (remainder << 1) | (dividend[15] & 1'b1);
dividend = dividend << 1; // Shift the dividend
// Compare the upper bits of the dividend with the divisor
if (remainder >= divisor) begin
remainder = remainder - divisor;
result = (result << 1) | 1'b1;
end else begin
result = result << 1;
end
end
// Assign the final remainder value
odd = remainder;
end
endmodule |
module signal_generator(
input wire clk,
input wire rst_n,
output reg [4:0] wave
);
// Define state register
reg state;
// Define states for readability
localparam STATE_UP = 1'b0;
localparam STATE_DOWN = 1'b1;
// Waveform generation always block
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Synchronous reset
wave <= 5'd0;
state <= STATE_UP;
end else begin
case (state)
STATE_UP: begin
// Increment the wave
if (wave == 5'd31) begin
// Transition to STATE_DOWN if maximum is reached
state <= STATE_DOWN;
wave <= wave - 5'd1;
end else begin
// Continue incrementing
wave <= wave + 5'd1;
end
end
STATE_DOWN: begin
// Decrement the wave
if (wave == 5'd0) begin
// Transition to STATE_UP if minimum is reached
state <= STATE_UP;
wave <= wave + 5'd1;
end else begin
// Continue decrementing
wave <= wave - 5'd1;
end
end
default: begin
// In case of an undefined state, reset to known state
state <= STATE_UP;
wave <= 5'd0;
end
endcase
end
end
endmodule |
module multi_booth_8bit (
input wire clk,
input wire reset,
input wire [7:0] a,
input wire [7:0] b,
output reg [15:0] p,
output reg rdy
);
reg [7:0] multiplicand, multiplier;
reg [4:0] count; // 4 bits to count up to 8 iterations
reg [1:0] booth_code;
reg [16:0] product; // 1 extra bit for sign extension
wire [1:0] next_booth_code = {multiplier[1], multiplier[0]};
always @(posedge clk or posedge reset) begin
if (reset) begin
// Initialize registers
product <= 0;
multiplicand <= a;
multiplier <= b;
count <= 0;
rdy <= 0;
end else begin
case (next_booth_code)
2'b01: product = product + (multiplicand << count);
2'b10: product = product - (multiplicand << count);
default: product = product; // 2'b00 or 2'b11 means no operation
endcase
// Prepare for the next iteration
count = count + 1;
multiplier = multiplier >> 2; // Shift by 2 for Radix-4 Booth
// Check if multiplication is complete
if (count == 4'b1000) begin // After 8 iterations
rdy <= 1;
p <= product[15:0]; // Assign the lower 16 bits to output
end
end
end
endmodule |
module pe(
input wire clk,
input wire rst,
input wire [31:0] a,
input wire [31:0] b,
output reg [31:0] c
);
// Intermediate full width of the product to avoid overflow during accumulation
reg [63:0] product;
always @(posedge clk or posedge rst) begin
if (rst) begin
// Reset the accumulator register 'c' to 0
c <= 32'b0;
end else begin
// Perform multiplication
product <= a * b;
// Accumulate the result
c <= c + product[31:0]; // Assuming you want to accumulate the lower 32 bits of the product
end
end
endmodule |
module alu (
input [31:0] a,
input [31:0] b,
input [5:0] aluc,
output reg [31:0] r,
output zero,
output reg carry,
output negative,
output reg overflow,
output reg flag
);
// Define operation parameters
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter LUI = 6'b001111;
// Internal signals
reg [32:0] extended_result; // 32-bit result with carry
wire [31:0] b_negated;
wire set;
wire unsigned_set;
assign b_negated = ~b + 1'b1; // Two's complement for subtraction
assign set = r[31]; // Negative flag for SLT
assign unsigned_set = !r[31]; // Unsigned comparison for SLTU
assign zero = (r == 32'b0); // Zero flag
assign negative = r[31]; // Negative flag
always @(*) begin
carry = 0; // Default carry
overflow = 0; // Default overflow
flag = 0; // Default flag
case (aluc)
ADD: {carry, r} = {1'b0, a} + {1'b0, b};
ADDU: r = a + b;
SUB: {carry, r} = {1'b0, a} + {1'b0, b_negated};
SUBU: r = a - b;
AND: r = a & b;
OR: r = a | b;
XOR: r = a ^ b;
NOR: r = ~(a | b);
SLT: begin
r = set;
flag = set;
end
SLTU: begin
r = unsigned_set;
flag = unsigned_set;
end
SLL: r = b << a[4:0];
SRL: r = b >> a[4:0];
SRA: r = $signed(b) >>> a[4:0];
SLLV: r = b << (a[4:0]);
SRLV: r = b >> (a[4:0]);
SRAV: r = $signed(b) >>> (a[4:0]);
LUI: r = {b[15:0], 16'b0};
default: r = 32'bz; // High-impedance for undefined operations
endcase
// Check for overflow in signed addition and subtraction
if (aluc == ADD || aluc == SUB) begin
overflow = (a[31] && b[31] && !r[31]) || (!a[31] && !b[31] && r[31]);
end
end
endmodule |
module pulse_detect(
input wire clk,
input wire rst_n,
input wire data_in,
output reg data_out
);
// Define states for the FSM
parameter IDLE = 2'b00,
DETECT_RISE = 2'b01,
DETECT_FALL = 2'b10;
// State register
reg [1:0] state;
reg [1:0] next_state;
// Sequential block for state transition
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
// Combinational block for next state logic and output assignment
always @(*) begin
// Default assignments
next_state = state;
data_out = 1'b0;
case (state)
IDLE: begin
// If a rising edge is detected, move to DETECT_RISE state
if (data_in == 1'b1) begin
next_state = DETECT_RISE;
end
end
DETECT_RISE: begin
// If data_in is 0 after being 1, we have detected a falling edge
if (data_in == 1'b0) begin
next_state = DETECT_FALL;
end
end
DETECT_FALL: begin
// Detected a pulse, so output should be high
data_out = 1'b1;
// Look for the next pulse
next_state = IDLE;
end
default: begin
// In case of an undefined state, go back to IDLE
next_state = IDLE;
end
endcase
end
endmodule |
module synchronizer(
input wire clk_a,
input wire clk_b,
input wire arstn,
input wire brstn,
input wire [3:0] data_in,
input wire data_en,
output reg [3:0] dataout
);
// Data Register
reg [3:0] data_reg;
// Enable Data Register
reg en_data_reg;
// Enable Control Registers
reg en_clap_one;
reg en_clap_two;
// Register data_in with clk_a
always @(posedge clk_a or negedge arstn) begin
if (!arstn) begin
data_reg <= 4'b0000;
end else if (data_en) begin
data_reg <= data_in;
end
end
// Register data_en with clk_a
always @(posedge clk_a or negedge arstn) begin
if (!arstn) begin
en_data_reg <= 1'b0;
end else begin
en_data_reg <= data_en;
end
end
// Synchronize the enable signal with clk_b
always @(posedge clk_b or negedge brstn) begin
if (!brstn) begin
en_clap_one <= 1'b0;
en_clap_two <= 1'b0;
end else begin
en_clap_one <= en_data_reg;
en_clap_two <= en_clap_one;
end
end
// Output assignment
always @(posedge clk_b or negedge brstn) begin
if (!brstn) begin
dataout <= 4'b0000;
end else if (en_clap_two) begin
dataout <= data_reg;
end
end
endmodule |
module calendar(
input CLK,
input RST,
output reg [5:0] Hours,
output reg [5:0] Mins,
output reg [5:0] Secs
);
// Define the maximum values for seconds, minutes, and hours
localparam MAX_SECS = 6'd59;
localparam MAX_MINS = 6'd59;
localparam MAX_HOURS = 5'd23;
// Seconds always block
always @(posedge CLK or posedge RST) begin
if (RST) begin
Secs <= 0; // Reset seconds to 0
end else if (Secs == MAX_SECS) begin
Secs <= 0; // Reset seconds to 0 when it reaches the max value
end else begin
Secs <= Secs + 1; // Increment seconds
end
end
// Minutes always block
always @(posedge CLK or posedge RST) begin
if (RST) begin
Mins <= 0; // Reset minutes to 0
end else if (Secs == MAX_SECS) begin
if (Mins == MAX_MINS) begin
Mins <= 0; // Reset minutes to 0 when it and seconds reach the max value
end else begin
Mins <= Mins + 1; // Increment minutes
end
end
end
// Hours always block
always @(posedge CLK or posedge RST) begin
if (RST) begin
Hours <= 0; // Reset hours to 0
end else if (Mins == MAX_MINS && Secs == MAX_SECS) begin
if (Hours == MAX_HOURS) begin
Hours <= 0; // Reset hours to 0 when it, minutes, and seconds reach the max value
end else begin
Hours <= Hours + 1; // Increment hours
end
end
end
endmodule |
module traffic_light (
input clk,
input rst_n,
input pass_request,
output reg [7:0] clock,
output reg red,
output reg yellow,
output reg green
);
// State parameters
parameter idle = 2'b00,
s1_red = 2'b01,
s2_yellow = 2'b10,
s3_green = 2'b11;
// Internal counter and state
reg [7:0] cnt;
reg [1:0] state;
// Next state logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= idle;
cnt <= 8'd60; // Start with green light duration
end else begin
case (state)
idle: begin
state <= s1_red;
end
s1_red: begin
if (cnt == 0) begin
state <= s3_green;
cnt <= 8'd60; // Green light duration
end
end
s2_yellow: begin
if (cnt == 0) begin
state <= s1_red;
cnt <= 8'd10; // Red light duration
end
end
s3_green: begin
if (cnt == 0 || (cnt > 8'd10 && pass_request)) begin
state <= s2_yellow;
cnt <= 8'd5; // Yellow light duration
end
end
default: state <= idle;
endcase
end
end
// Counter logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 8'd60; // Reset to green light duration
end else if (state == s3_green && pass_request && cnt > 8'd10) begin
cnt <= 8'd10; // Shorten green if pedestrian button is pressed
end else if (cnt > 0) begin
cnt <= cnt - 1; // Decrement counter
end
end
// Output logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
red <= 1'b0;
yellow <= 1'b0;
green <= 1'b0;
end else begin
// Set outputs based on state
red <= (state == s1_red);
yellow <= (state == s2_yellow);
green <= (state == s3_green);
end
end
// Assign internal counter to output
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
clock <= 8'd0;
end else begin
clock <= cnt;
end
end
endmodule |
module fsm (
input IN,
input CLK,
input RST,
output reg MATCH
);
// Define state identifiers
parameter [2:0] S0 = 3'b000, // Start state (or state after reset)
S1 = 3'b001, // After seeing '1'
S2 = 3'b010, // After seeing '10'
S3 = 3'b011, // After seeing '100'
S4 = 3'b100, // After seeing '1001'
S5 = 3'b101; // After seeing '10011'
// State variable
reg [2:0] current_state, next_state;
// Sequential logic for state transitions
always @(posedge CLK or posedge RST) begin
if (RST)
current_state <= S0;
else
current_state <= next_state;
end
// Combinational logic for next state and MATCH output
always @(*) begin
// Default assignment
MATCH = 0;
next_state = current_state; // Stay in the current state by default
case (current_state)
S0: begin
if (IN) next_state = S1;
end
S1: begin
if (!IN) next_state = S2;
end
S2: begin
if (!IN) next_state = S3;
else next_state = S1;
end
S3: begin
if (IN) next_state = S4;
else next_state = S2;
end
S4: begin
if (IN) begin
next_state = S5;
MATCH = 1; // MATCH output is set to '1' upon reaching S5
end else begin
next_state = S2;
end
end
S5: begin
if (IN) next_state = S1;
else next_state = S2;
end
default: next_state = S0;
endcase
end
endmodule |
module width_8to16 (
input wire clk,
input wire rst_n,
input wire valid_in,
input wire [7:0] data_in,
output reg valid_out,
output reg [15:0] data_out
);
// Internal signal to hold the first 8-bit data and the flag to indicate its presence
reg [7:0] data_lock;
reg data_lock_valid;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset state: clear registers and output
data_out <= 16'b0;
valid_out <= 1'b0;
data_lock <= 8'b0;
data_lock_valid <= 1'b0;
end else begin
if (valid_in) begin
if (data_lock_valid) begin
// If we already have a valid data_lock, concatenate and output
data_out <= {data_lock, data_in};
valid_out <= 1'b1;
data_lock_valid <= 1'b0; // Reset the data_lock_valid flag
end else begin
// Store the first part of the data and wait for the next valid input
data_lock <= data_in;
data_lock_valid <= 1'b1;
valid_out <= 1'b0; // Do not assert valid_out yet
end
end else if (!data_lock_valid) begin
// If valid_in is low and we don't have a valid data_lock, keep outputs deasserted
valid_out <= 1'b0;
end
// No else condition here, if valid_in is low but data_lock_valid is true, we wait.
end
end
endmodule |
module JC_counter (
input clk,
input rst_n,
output reg [63:0] Q
);
// Johnson counter update logic on clock edge or reset
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Active-low reset to zero
Q <= 64'b0;
end else begin
// Check the least significant bit to determine increment or decrement
if (Q[0] == 1'b0) begin
// Shift left and append 1 at LSB (note: MSB comes from the inverted LSB)
Q <= {Q[62:0], ~Q[63]};
end else begin
// Shift left and append 0 at LSB (note: MSB comes from the inverted LSB)
Q <= {Q[62:0], ~Q[63]};
end
end
end
endmodule |
module adder_pipe_64bit(
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
// Define the pipeline stages registers
reg [63:0] stage0_adda, stage0_addb;
reg [63:0] stage1_adda, stage1_addb;
reg [63:0] stage2_adda, stage2_addb;
reg [64:0] stage3_sum;
// Define the enable signals for each stage
reg stage0_en, stage1_en, stage2_en, stage3_en;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset all pipeline registers and enable signals
{stage0_adda, stage0_addb, stage1_adda, stage1_addb, stage2_adda, stage2_addb, stage3_sum} <= 0;
{stage0_en, stage1_en, stage2_en, stage3_en, o_en} <= 0;
result <= 0;
end else begin
// Pipeline stage 0 (input latching)
if (i_en) begin
stage0_adda <= adda;
stage0_addb <= addb;
stage0_en <= 1'b1;
end else begin
stage0_en <= 1'b0;
end
// Pipeline stage 1 (propagation stage)
if (stage0_en) begin
stage1_adda <= stage0_adda;
stage1_addb <= stage0_addb;
stage1_en <= 1'b1;
end else begin
stage1_en <= 1'b0;
end
// Pipeline stage 2 (propagation stage)
if (stage1_en) begin
stage2_adda <= stage1_adda;
stage2_addb <= stage1_addb;
stage2_en <= 1'b1;
end else begin
stage2_en <= 1'b0;
end
// Pipeline stage 3 (addition stage)
if (stage2_en) begin
stage3_sum <= stage2_adda + stage2_addb;
stage3_en <= 1'b1;
end else begin
stage3_en <= 1'b0;
end
// Output result
if (stage3_en) begin
result <= stage3_sum;
o_en <= 1'b1;
end else begin
o_en <= 1'b0;
end
end
end
endmodule |
module right_shifter(
input wire clk,
input wire d,
output reg [7:0] q
);
// Initialize the 'q' register to 0
initial begin
q = 8'b00000000;
end
// On each rising edge of the clock, shift 'q' right and insert 'd' at MSB
always @(posedge clk) begin
q <= {d, q[7:1]};
end
endmodule |
module serial2parallel (
input wire clk,
input wire rst_n,
input wire din_serial,
input wire din_valid,
output reg [7:0] dout_parallel,
output reg dout_valid
);
// 3-bit counter to count the number of bits received
reg [2:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset the counter and output registers
cnt <= 0;
dout_parallel <= 0;
dout_valid <= 0;
end else if (din_valid) begin
// Shift in the serial data into the MSB of dout_parallel
dout_parallel <= (dout_parallel << 1) | din_serial;
// Increment the counter
cnt <= cnt + 1;
// Check if 8 bits have been received
if (cnt == 7) begin
// Set the valid output high as all 8 bits are received
dout_valid <= 1;
// Reset the counter to start for the next byte
cnt <= 0;
end else begin
// Keep the valid output low as all 8 bits are not yet received
dout_valid <= 0;
end
end else begin
// If din_valid is not high, do not shift in new data and keep dout_valid low
dout_valid <= 0;
end
end
endmodule |
module multi_16bit(
input clk,
input rst_n,
input start,
input [15:0] ain,
input [15:0] bin,
output reg [31:0] yout,
output reg done
);
reg [31:0] product; // Accumulated product
reg [15:0] multiplicand; // Register for the multiplicand
reg [15:0] multiplier; // Register for the multiplier
reg [4:0] i; // Shift count register (4 bits for 0-16 range)
reg done_r; // Internal completion flag
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Reset the registers and flags
i <= 5'b0;
multiplicand <= 16'b0;
multiplier <= 16'b0;
product <= 32'b0;
done_r <= 1'b0;
done <= 1'b0;
yout <= 32'b0;
end else begin
if (start) begin
if (i < 17) begin
if (i == 0) begin
// Load the registers
multiplicand <= ain;
multiplier <= bin;
product <= 32'b0; // Clear the product register
end else begin
// Shift and accumulate
if (multiplicand[0]) begin
product <= product + (multiplier << (i - 1));
end
multiplicand <= multiplicand >> 1; // Shift right for the next cycle
end
i <= i + 1;
end
// Set the done flag when the operation is complete
if (i == 16) begin
done_r <= 1'b1;
yout <= product; // Assign the accumulated product to the output
end else if (i == 17) begin
// Clear the done flag for the next operation
done_r <= 1'b0;
i <= 0; // Reset the shift count register for the next operation
end
end else begin
// Clear the shift count register if start is not active
i <= 0;
done_r <= 1'b0;
end
done <= done_r; // Output the done status
end
end
endmodule |
module multi_pipe_4bit #(parameter size = 4) (
input clk,
input rst_n,
input [size-1:0] mul_a,
input [size-1:0] mul_b,
output reg [(2*size)-1:0] mul_out
);
// Intermediate product registers for pipeline stages
reg [size-1:0] stage1_mul_a[size-1:0];
reg [(2*size)-1:0] stage1_product[size-1:0];
reg [(2*size)-1:0] stage2_sum;
// Calculate partial products and store them in pipeline registers
integer i;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Reset all pipeline registers
for (i = 0; i < size; i = i + 1) begin
stage1_mul_a[i] <= 0;
stage1_product[i] <= 0;
end
stage2_sum <= 0;
mul_out <= 0;
end else begin
// First pipeline stage: calculate and store partial products
for (i = 0; i < size; i = i + 1) begin
stage1_mul_a[i] <= mul_a;
if (mul_b[i]) begin
stage1_product[i] <= mul_a << i;
end else begin
stage1_product[i] <= 0;
end
end
// Second pipeline stage: sum the partial products
stage2_sum <= stage1_product[0];
for (i = 1; i < size; i = i + 1) begin
stage2_sum <= stage2_sum + stage1_product[i];
end
// Update the output register with the final product
mul_out <= stage2_sum;
end
end
endmodule |
module freq_div(
input CLK_in, // Input clock signal at 100MHz
input RST, // Reset signal (active high)
output reg CLK_50, // Output clock signal at 50MHz
output reg CLK_10, // Output clock signal at 10MHz
output reg CLK_1 // Output clock signal at 1MHz
);
// Counter for the 10MHz clock
reg [3:0] cnt_10 = 0; // 5 stages (0-4), toggles at 5
// Counter for the 1MHz clock
reg [5:0] cnt_100 = 0; // 50 stages (0-49), toggles at 50
// Frequency division for 50MHz
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_50 <= 0;
end else begin
CLK_50 <= ~CLK_50; // Toggles each clock cycle (50MHz)
end
end
// Frequency division for 10MHz
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
cnt_10 <= 0;
CLK_10 <= 0;
end else begin
if (cnt_10 == 4) begin
cnt_10 <= 0;
CLK_10 <= ~CLK_10; // Toggle the output clock
end else begin
cnt_10 <= cnt_10 + 1;
end
end
end
// Frequency division for 1MHz
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
cnt_100 <= 0;
CLK_1 <= 0;
end else begin
if (cnt_100 == 49) begin
cnt_100 <= 0;
CLK_1 <= ~CLK_1; // Toggle the output clock
end else begin
cnt_100 <= cnt_100 + 1;
end
end
end
endmodule |
module counter_12 (
input wire rst_n, // Active low reset
input wire clk, // Clock signal
input wire valid_count, // Enable counting
output reg [3:0] out // 4-bit count value
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Reset the counter to 0 when reset is active
out <= 4'b0000;
end else if (valid_count) begin
// Only count when valid_count is high
if (out == 4'd11) begin
// Wrap around the counter after reaching 4'd11
out <= 4'b0000;
end else begin
// Increment the counter
out <= out + 1;
end
end
// When valid_count is low, do nothing (counter is paused)
end
endmodule |
module edge_detect (
input clk,
input rst_n,
input a,
output reg rise,
output reg down
);
// Register to hold the previous value of 'a'
reg a_prev;
// Detect edges on the positive clock edge and when reset is not asserted
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// On reset, clear the rise and down signals and the stored previous value of 'a'
rise <= 0;
down <= 0;
a_prev <= 0;
end else begin
// On each clock edge, update the rise and down signals based on the current and previous values of 'a'
rise <= (a_prev == 0) && (a == 1); // Set 'rise' if 'a' was 0 and is now 1
down <= (a_prev == 1) && (a == 0); // Set 'down' if 'a' was 1 and is now 0
a_prev <= a; // Store the current value of 'a' for the next comparison
end
end
endmodule |
module RAM #(
parameter WIDTH = 6,
parameter DEPTH = 8
)(
input clk,
input rst_n,
input write_en,
input [DEPTH-1:0] write_addr,
input [WIDTH-1:0] write_data,
input read_en,
input [DEPTH-1:0] read_addr,
output reg [WIDTH-1:0] read_data
);
// Declare the RAM array
reg [WIDTH-1:0] RAM [2**DEPTH-1:0];
// Initialize the RAM array values to 0 on reset
integer i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < 2**DEPTH; i = i + 1) begin
RAM[i] <= 6'b000000;
end
end
else if (write_en) begin
// Write operation
RAM[write_addr] <= write_data;
end
end
// Read operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
read_data <= 6'b000000;
end
else if (read_en) begin
read_data <= RAM[read_addr];
end
else begin
read_data <= 6'b000000; // Optionally clear read_data if not enabled
end
end
endmodule |
module adder_8bit (
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
// Wire declarations for the carry bits between full adders
wire [6:0] carry;
// Instantiate the full adder for each bit
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(carry[0])
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
.cin(carry[0]),
.sum(sum[1]),
.cout(carry[1])
);
full_adder fa2 (
.a(a[2]),
.b(b[2]),
.cin(carry[1]),
.sum(sum[2]),
.cout(carry[2])
);
full_adder fa3 (
.a(a[3]),
.b(b[3]),
.cin(carry[2]),
.sum(sum[3]),
.cout(carry[3])
);
full_adder fa4 (
.a(a[4]),
.b(b[4]),
.cin(carry[3]),
.sum(sum[4]),
.cout(carry[4])
);
full_adder fa5 (
.a(a[5]),
.b(b[5]),
.cin(carry[4]),
.sum(sum[5]),
.cout(carry[5])
);
full_adder fa6 (
.a(a[6]),
.b(b[6]),
.cin(carry[5]),
.sum(sum[6]),
.cout(carry[6])
);
full_adder fa7 (
.a(a[7]),
.b(b[7]),
.cin(carry[6]),
.sum(sum[7]),
.cout(cout)
);
endmodule |
module multi_pipe_8bit (
input clk,
input rst_n,
input mul_en_in,
input [7:0] mul_a,
input [7:0] mul_b,
output mul_en_out,
output [15:0] mul_out
);
reg [15:0] pipeline [2:0]; // 3-stage pipeline for partial products sum
reg [7:0] mul_a_reg, mul_b_reg; // Input registers
reg mul_en_in_reg, mul_en_out_reg; // Enable registers
wire [15:0] partial_product [7:0]; // Array to hold partial products
// Generate partial products
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : gen_partial_products
assign partial_product[i] = mul_a_reg & {8{mul_b_reg[i]}};
end
endgenerate
// Pipeline stages logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
mul_a_reg <= 0;
mul_b_reg <= 0;
mul_en_in_reg <= 0;
mul_en_out_reg <= 0;
pipeline[0] <= 0;
pipeline[1] <= 0;
pipeline[2] <= 0;
end else begin
// Input registers update
if (mul_en_in) begin
mul_a_reg <= mul_a;
mul_b_reg <= mul_b;
end
// Enable signal pipeline update
mul_en_in_reg <= mul_en_in; // Register input enable
mul_en_out_reg <= mul_en_in_reg; // Register output enable
// First pipeline stage
pipeline[0] <= partial_product[0] + (partial_product[1] << 1);
// Second pipeline stage
pipeline[1] <= pipeline[0] + (partial_product[2] << 2) + (partial_product[3] << 3);
// Third pipeline stage, final sum
pipeline[2] <= pipeline[1] + (partial_product[4] << 4) + (partial_product[5] << 5) +
(partial_product[6] << 6) + (partial_product[7] << 7);
end
end
// Output assignment
assign mul_out = (mul_en_out_reg) ? pipeline[2] : 16'd0;
assign mul_en_out = mul_en_out_reg;
endmodule |
module parallel2serial (
input clk,
input rst_n,
input [3:0] d,
output reg valid_out,
output reg dout
);
// Internal 4-bit register to hold the input data
reg [3:0] data;
// 2-bit counter to keep track of the bit position
reg [1:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Asynchronous reset
cnt <= 2'd0;
valid_out <= 1'b0;
dout <= 1'b0;
data <= 4'd0;
end else begin
if (cnt == 2'd3) begin
// Load new data and reset counter
data <= d;
cnt <= 2'd0;
valid_out <= 1'b1; // Valid output on loading new data
end else begin
// Shift data and increment counter
data <= {data[2:0], 1'b0};
cnt <= cnt + 2'd1;
valid_out <= 1'b0;
end
// Output the MSB of the data register
dout <= data[3];
end
end
endmodule |
module radix2_div #(
parameter DATAWIDTH = 8
)(
input wire clk,
input wire rstn,
input wire en,
input wire [DATAWIDTH-1:0] dividend,
input wire [DATAWIDTH-1:0] divisor,
output reg ready,
output reg [DATAWIDTH-1:0] quotient,
output reg [DATAWIDTH-1:0] remainder,
output reg vld_out
);
// State declaration for the FSM
localparam IDLE = 2'b00,
SUB = 2'b01,
SHIFT = 2'b10,
DONE = 2'b11;
// State registers
reg [1:0] current_state, next_state;
// Data registers
reg [DATAWIDTH-1:0] dividend_e, divisor_e;
reg [DATAWIDTH-1:0] quotient_e, remainder_e;
reg [DATAWIDTH:0] count; // Extra bit for counting up to DATAWIDTH times
// FSM and calculation logic
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
current_state <= IDLE;
quotient_e <= 0;
remainder_e <= 0;
dividend_e <= 0;
divisor_e <= 0;
count <= 0;
ready <= 1'b1;
vld_out <= 1'b0;
end else begin
case (current_state)
IDLE: begin
if (en) begin
dividend_e <= dividend;
divisor_e <= divisor << (DATAWIDTH-1); // Align divisor to the leftmost part
quotient_e <= 0;
remainder_e <= 0;
count <= DATAWIDTH; // Initialize the count
ready <= 1'b0;
current_state <= SUB;
end
end
SUB: begin
// Subtract the divisor from the dividend and check if it's non-negative
if (dividend_e >= divisor_e) begin
dividend_e <= dividend_e - divisor_e;
quotient_e <= (quotient_e << 1) | 1'b1; // Set the current quotient bit to 1
end else begin
quotient_e <= quotient_e << 1; // Set the current quotient bit to 0
end
current_state <= SHIFT;
end
SHIFT: begin
if (count == 0) begin
current_state <= DONE;
end else begin
divisor_e <= divisor_e >> 1; // Shift the divisor right
count <= count - 1; // Decrement the counter
current_state <= SUB;
end
end
DONE: begin
quotient <= quotient_e;
remainder <= dividend_e;
ready <= 1'b1;
vld_out <= 1'b1;
current_state <= IDLE;
end
default: current_state <= IDLE;
endcase
end
end
// Output assignments
always @(*) begin
case (current_state)
IDLE: begin
ready = 1'b1;
vld_out = 1'b0;
end
DONE: begin
ready = 1'b0;
vld_out = 1'b1;
end
default: begin
ready = 1'b0;
vld_out = 1'b0;
end
endcase
end
endmodule |
module accu (
input clk,
input rst_n,
input [7:0] data_in,
input valid_in,
output reg valid_out,
output reg [9:0] data_out
);
reg [9:0] sum;
reg [1:0] count;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Asynchronous reset: clear the sum, count, and output signals
sum <= 10'd0;
count <= 2'd0;
valid_out <= 1'b0;
data_out <= 10'd0;
end else begin
if (valid_in) begin
// If a valid input is received, accumulate the sum and increment the count
if (count < 3) begin
sum <= sum + data_in; // Accumulate the input data
count <= count + 1'b1; // Increment the count
valid_out <= 1'b0; // Keep valid_out low as accumulation is not complete
end else begin
// If we have received four inputs, output the accumulated sum
sum <= sum + data_in; // Add the last data input to the sum
data_out <= sum + data_in; // Output the accumulated sum
valid_out <= 1'b1; // Indicate that valid_out is ready
sum <= 10'd0; // Reset the sum for the next accumulation
count <= 2'd0; // Reset the count for the next accumulation
end
end else begin
// If valid_in is not high, do not accumulate and set valid_out to 0
valid_out <= 1'b0;
end
end
end
endmodule |
module div_16bit(
input wire [15:0] A, // 16-bit dividend
input wire [7:0] B, // 8-bit divisor
output wire [15:0] result, // 16-bit quotient
output wire [15:0] odd // 16-bit remainder
);
// Intermediate wires to hold the results of each step
wire [15:0] subtract_results[7:0];
wire [7:0] compare_results;
// Initial partial dividend (most significant bits of A)
wire [7:0] partial_dividend;
assign partial_dividend = A[15:8];
// The subtraction and comparison at each step
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : div_step
// Compare and subtract
assign compare_results[i] = (partial_dividend >= B) ? 1'b1 : 1'b0;
assign subtract_results[i] = (partial_dividend >= B) ? (partial_dividend - B) : partial_dividend;
// Prepare next partial dividend for the next stage
if (i < 7) begin
assign partial_dividend = {subtract_results[i][6:0], A[7-i]};
end
end
endgenerate
// Combine the compare results to form the quotient
assign result = {compare_results, A[7:0]};
// The final remainder is the result of the last subtraction
assign odd = {subtract_results[7], A[7:0]};
endmodule |
module signal_generator (
input wire clk,
input wire rst_n,
output reg [4:0] wave
);
// State declaration
reg state;
// State definitions
localparam STATE_UP = 1'b0;
localparam STATE_DOWN = 1'b1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset condition
wave <= 5'b00000; // Initialize wave to 0
state <= STATE_UP; // Start with incrementing state
end else begin
case (state)
STATE_UP: begin
// Increment wave until it reaches 31
if (wave == 31) begin
state <= STATE_DOWN; // Change state to decrement
end else begin
wave <= wave + 1;
end
end
STATE_DOWN: begin
// Decrement wave until it reaches 0
if (wave == 0) begin
state <= STATE_UP; // Change state to increment
end else begin
wave <= wave - 1;
end
end
default: begin
// In case of an undefined state, reset to known state
state <= STATE_UP;
wave <= 5'b00000;
end
endcase
end
end
endmodule |
module multi_booth_8bit (
input wire clk,
input wire reset,
input wire [7:0] a,
input wire [7:0] b,
output reg [15:0] p,
output reg rdy
);
// Internal registers
reg [7:0] multiplicand;
reg [8:0] multiplier; // Extra bit for sign extension
reg [3:0] ctr; // 4-bit counter since we are processing 2 bits at a time
// Initialize the registers on reset
always @(posedge clk or posedge reset) begin
if (reset) begin
multiplicand <= 0;
multiplier <= {1'b0, b}; // Sign extend the multiplier
p <= 0;
ctr <= 0;
rdy <= 0;
end else begin
// Check if the multiplication process is complete
if (ctr < 4) begin
case (multiplier[1:0]) // Radix-4 Booth Encoding
2'b01: p <= p + (multiplicand << (ctr * 2));
2'b10: p <= p - (multiplicand << (ctr * 2));
default: p <= p; // No operation for 00 and 11
endcase
// Prepare for the next iteration
multiplier <= multiplier >> 2; // Consume the next 2 bits
ctr <= ctr + 1; // Increment the counter
end else begin
rdy <= 1; // Indicate that the multiplication is done
end
end
end
// Sign extension handling for negative numbers
always @(posedge clk) begin
if (ctr == 0 && !rdy) begin
multiplicand <= a[7] ? (~a + 1'b1) : a; // If negative, take 2's complement
end
end
endmodule |
module pe(
input clk,
input rst,
input [31:0] a,
input [31:0] b,
output reg [31:0] c
);
// Temporary variable to hold the product of a and b
wire [63:0] product;
// Perform the multiplication of a and b
assign product = a * b;
always @(posedge clk or posedge rst) begin
if (rst) begin
// Reset the accumulator to 0 on reset signal
c <= 32'd0;
end else begin
// Accumulate the product in the register c
c <= c + product[31:0]; // Note: Truncating the product to 32 bits
end
end
endmodule |
module alu (
input [31:0] a,
input [31:0] b,
input [5:0] aluc,
output reg [31:0] r,
output zero,
output reg carry,
output reg negative,
output reg overflow,
output reg flag
);
// Opcode parameters
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter LUI = 6'b001111;
// Internal signals
reg [31:0] res;
wire signed [31:0] signed_a = a;
wire signed [31:0] signed_b = b;
wire [31:0] b_inv;
wire [32:0] sum; // For carry and overflow detection
wire slt_set;
// Calculate zero flag
assign zero = (r == 32'b0);
// Calculate SLT set condition
assign slt_set = signed_a < signed_b;
// Extended b inversion for SUB and SUBU
assign b_inv = ~b + 1'b1;
// 33-bit sum for carry and overflow detection
assign sum = {1'b0, a} + (aluc == SUB || aluc == SUBU ? {1'b0, b_inv} : {1'b0, b}) + (aluc == SUB);
always @(*) begin
case (aluc)
ADD, ADDU: begin
res = a + b;
carry = sum[32];
overflow = (a[31] == b[31]) && (res[31] != a[31]);
end
SUB, SUBU: begin
res = a - b;
carry = !sum[32];
overflow = (a[31] != b[31]) && (res[31] != a[31]);
end
AND: res = a & b;
OR: res = a | b;
XOR: res = a ^ b;
NOR: res = ~(a | b);
SLT: begin
res = slt_set;
flag = slt_set;
end
SLTU: begin
res = a < b;
flag = a < b;
end
SLL: res = b << a[4:0];
SRL: res = b >> a[4:0];
SRA: res = signed_b >>> a[4:0];
SLLV: res = b << b[4:0];
SRLV: res = b >> b[4:0];
SRAV: res = signed_b >>> b[4:0];
LUI: res = b << 16;
default: res = 32'bz; // High-impedance for undefined operations
endcase
// Set the output register to the computed result
r = res;
// Set flags
negative = r[31];
flag = (aluc == SLT || aluc == SLTU) ? 1'b1 : 1'b0;
// Clear carry and overflow for logical operations
if (aluc[5:3] == 3'b100) begin
carry = 1'b0;
overflow = 1'b0;
end
end
endmodule |
module adder_8bit (
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
// Internal wires for carry propagation
wire carry_internal;
// Lower 8 bits addition
assign {carry_internal, sum[7:0]} = a[7:0] + b[7:0] + cin;
// Carry-out is the MSB of the 9-bit result
assign cout = carry_internal;
endmodule |
module adder_16bit (
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
// Internal wire to carry the carry-out from the lower adder to the higher adder
wire carry_internal;
// Instantiate the lower 8-bit adder
adder_8bit lower_adder (
.a(a[7:0]),
.b(b[7:0]),
.cin(Cin),
.sum(y[7:0]),
.cout(carry_internal) // Carry-out of lower adder is carry-in of higher adder
);
// Instantiate the higher 8-bit adder
adder_8bit higher_adder (
.a(a[15:8]),
.b(b[15:8]),
.cin(carry_internal), // Carry-in is the carry-out from the lower adder
.sum(y[15:8]),
.cout(Co) // Carry-out of the full 16-bit adder
);
endmodule |
module synchronizer (
input wire clk_a,
input wire clk_b,
input wire arstn,
input wire brstn,
input wire [3:0] data_in,
input wire data_en,
output reg [3:0] dataout
);
// Data register to store input data on clk_a
reg [3:0] data_reg;
always @(posedge clk_a or negedge arstn) begin
if (!arstn)
data_reg <= 4'b0000;
else if (data_en)
data_reg <= data_in;
end
// Enable data register to store input enable on clk_a
reg en_data_reg;
always @(posedge clk_a or negedge arstn) begin
if (!arstn)
en_data_reg <= 1'b0;
else
en_data_reg <= data_en;
end
// Synchronizer flip-flops for the enable signal on clk_b
reg en_clk_b_one, en_clk_b_two;
always @(posedge clk_b or negedge brstn) begin
if (!brstn) begin
en_clk_b_one <= 1'b0;
en_clk_b_two <= 1'b0;
end else begin
en_clk_b_one <= en_data_reg;
en_clk_b_two <= en_clk_b_one;
end
end
// Output assignment based on the synchronized enable signal
always @(posedge clk_b or negedge brstn) begin
if (!brstn)
dataout <= 4'b0000;
else if (en_clk_b_two)
dataout <= data_reg;
// No else condition to hold the previous value when not enabled
end
endmodule |
module asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [WIDTH-1:0] wdata,
output reg wfull,
output reg rempty,
output reg [WIDTH-1:0] rdata
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [WIDTH-1:0] rdata_reg;
reg [$clog2(DEPTH)-1:0] waddr_bin, raddr_bin;
reg [$clog2(DEPTH)-1:0] wptr, rptr;
reg [$clog2(DEPTH)-1:0] wptr_buff, rptr_buff;
reg [WIDTH-1:0] dual_port_RAM [0:DEPTH-1];
reg wenc, renc;
// Dual-port RAM instantiation
dual_port_RAM dual_port_RAM_inst (
.wclk(wclk),
.wenc(wenc),
.waddr(waddr_bin),
.wdata(wdata),
.rclk(rclk),
.renc(renc),
.raddr(raddr_bin),
.rdata(rdata_reg)
);
// Write pointer increment logic
always @(posedge wclk or negedge wrstn) begin
if (~wrstn) begin
waddr_bin <= 0;
wptr <= 0;
wptr_buff <= 0;
end else begin
if (winc) begin
waddr_bin <= waddr_bin + 1;
wptr <= wptr + 1;
wptr_buff <= wptr;
end
end
end
// Read pointer increment logic
always @(posedge rclk or negedge rrstn) begin
if (~rrstn) begin
raddr_bin <= 0;
rptr <= 0;
rptr_buff <= 0;
end else begin
if (rinc) begin
raddr_bin <= raddr_bin + 1;
rptr <= rptr + 1;
rptr_buff <= rptr;
end
end
end
// Gray code conversion for write pointer
always @(posedge wclk) begin
wenc <= winc;
waddr_bin <= wptr ^ (wptr >> 1);
end
// Gray code conversion for read pointer
always @(posedge rclk) begin
renc <= rinc;
raddr_bin <= rptr ^ (rptr >> 1);
end
// Full and empty signal generation
always @(wptr or rptr) begin
wfull = (wptr == ~{rptr[($clog2(DEPTH)-2):0], ~rptr[($clog2(DEPTH)-1)]});
rempty = (rptr == wptr);
end
// Output data assignment
always @(posedge rclk) begin
if (renc)
rdata <= rdata_reg;
end
endmodule |
module fsm (
input IN,
input CLK,
input RST,
output reg MATCH
);
reg [4:0] state;
reg [4:0] next_state;
always @(posedge CLK or posedge RST) begin
if (RST) begin
state <= 5'b00000;
MATCH <= 1'b0;
end
else begin
state <= next_state;
MATCH <= (state == 5'b10011);
end
end
always @(IN) begin
case (state)
5'b00000: next_state = (IN == 1'b1) ? 5'b00001 : 5'b00000;
5'b00001: next_state = (IN == 1'b0) ? 5'b00010 : 5'b00000;
5'b00010: next_state = (IN == 1'b0) ? 5'b00011 : 5'b00000;
5'b00011: next_state = (IN == 1'b1) ? 5'b00100 : 5'b00000;
5'b00100: next_state = (IN == 1'b1) ? 5'b10011 : 5'b00000;
default: next_state = 5'b00000;
endcase
end
endmodule |
module width_8to16 (
input clk,
input rst_n,
input valid_in,
input [7:0] data_in,
output reg valid_out,
output reg [15:0] data_out
);
reg [7:0] data_lock;
reg [15:0] data_reg;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_lock <= 8'h0;
data_reg <= 16'h0;
valid_out <= 1'b0;
data_out <= 16'h0;
end
else begin
if (valid_in) begin
data_lock <= data_in;
end
else begin
data_lock <= 8'h0;
end
if (valid_in && ~valid_out) begin
data_reg <= {data_lock, data_in};
valid_out <= 1'b1;
end
else if (valid_out) begin
data_reg <= {data_lock, data_in};
valid_out <= 1'b0;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 16'h0;
end
else begin
if (valid_out)
data_out <= data_reg;
end
end
endmodule |
module adder_pipe_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] stage1_adda, stage1_addb;
reg [63:0] stage2_adda, stage2_addb;
reg [63:0] stage3_adda, stage3_addb;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
result <= 'b0;
else if (i_en) begin
stage1_adda <= adda;
stage1_addb <= addb;
stage2_adda <= stage1_adda + stage1_addb;
stage2_addb <= stage1_adda & stage1_addb;
stage3_adda <= stage2_adda + stage2_addb;
stage3_addb <= stage2_adda & stage2_addb;
result <= {stage3_adda, stage3_addb[63]};
o_en <= 1'b1;
end else begin
o_en <= 1'b0;
end
end
endmodule |
module right_shifter (
input clk,
input d,
output reg [7:0] q
);
always @(posedge clk) begin
q <= {q[6:0], d};
end
endmodule |
module serial2parallel (
input clk,
input rst_n,
input din_serial,
input din_valid,
output reg [7:0] dout_parallel,
output reg dout_valid
);
reg [3:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
cnt <= 0;
dout_parallel <= 0;
dout_valid <= 0;
end
else begin
if (din_valid) begin
if (cnt < 7) begin
cnt <= cnt + 1;
dout_parallel <= {dout_parallel[6:0], din_serial};
dout_valid <= 0;
end
else begin
cnt <= 0;
dout_parallel <= {dout_parallel[6:0], din_serial};
dout_valid <= 1;
end
end
end
end
endmodule |
module freq_div (
input CLK_in,
input RST,
output reg CLK_50,
output reg CLK_10,
output reg CLK_1
);
reg [2:0] cnt_10;
reg [5:0] cnt_100;
always @(posedge CLK_in or negedge RST) begin
if (~RST) begin
CLK_50 <= 1'b0;
CLK_10 <= 1'b0;
CLK_1 <= 1'b0;
cnt_10 <= 3'b0;
cnt_100 <= 6'b0;
end
else begin
// CLK_50 generation
CLK_50 <= ~CLK_50;
// CLK_10 generation
if (cnt_10 == 3'b100) begin
CLK_10 <= ~CLK_10;
cnt_10 <= 3'b0;
end
else begin
cnt_10 <= cnt_10 + 1;
end
// CLK_1 generation
if (cnt_100 == 6'b110001) begin
CLK_1 <= ~CLK_1;
cnt_100 <= 6'b0;
end
else begin
cnt_100 <= cnt_100 + 1;
end
end
end
endmodule |
module counter_12 (
input rst_n,
input clk,
input valid_count,
output reg [3:0] out
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
out <= 4'b0000;
else if (valid_count) begin
if (out == 4'd11)
out <= 4'b0000;
else
out <= out + 1;
end
end
endmodule |
module edge_detect (
input clk,
input rst_n,
input a,
output reg rise,
output reg down
);
reg a_prev;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
rise <= 1'b0;
down <= 1'b0;
a_prev <= 1'b0;
end
else begin
if (a == 1'b1 && a_prev == 1'b0)
rise <= 1'b1;
else if (a == 1'b0 && a_prev == 1'b1)
down <= 1'b1;
else begin
rise <= 1'b0;
down <= 1'b0;
end
a_prev <= a;
end
end
endmodule |
module calendar (
input CLK,
input RST,
output reg [5:0] Hours,
output reg [5:0] Mins,
output reg [5:0] Secs
);
reg [5:0] next_hours, next_mins, next_secs;
always @(posedge CLK or posedge RST) begin
if (RST)
Secs <= 6'b0;
else if (Secs == 6'b111111)
Secs <= 6'b0;
else
Secs <= Secs + 1;
end
always @(posedge CLK or posedge RST) begin
if (RST)
Mins <= 6'b0;
else if (Secs == 6'b111111 && Mins == 6'b111111)
Mins <= 6'b0;
else if (Secs == 6'b111111)
Mins <= Mins + 1;
end
always @(posedge CLK or posedge RST) begin
if (RST)
Hours <= 6'b0;
else if (Secs == 6'b111111 && Mins == 6'b111111 && Hours == 6'b111111)
Hours <= 6'b0;
else if (Secs == 6'b111111 && Mins == 6'b111111)
Hours <= Hours + 1;
end
endmodule |
module RAM #(parameter WIDTH = 4, parameter DEPTH = 8)(
input clk,
input rst_n,
input write_en,
input [WIDTH-1:0] write_addr,
input [DEPTH-1:0] write_data,
input read_en,
input [WIDTH-1:0] read_addr,
output reg [DEPTH-1:0] read_data
);
reg [DEPTH-1:0] RAM [2**WIDTH-1:0];
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
for (integer i = 0; i < 2**WIDTH; i = i + 1)
RAM[i] <= 0;
end
else begin
if (write_en)
RAM[write_addr] <= write_data;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
read_data <= 0;
else begin
if (read_en)
read_data <= RAM[read_addr];
else
read_data <= 0;
end
end
endmodule |
module parallel2serial (
input clk,
input rst_n,
input [3:0] d,
output reg valid_out,
output reg dout
);
reg [2:0] cnt;
reg [3:0] data;
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
cnt <= 3'b0;
else if (cnt == 3'b11)
cnt <= 3'b0;
else
cnt <= cnt + 1;
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
data <= 4'b0;
else if (cnt == 3'b0)
data <= d;
else
data <= {data[2:0], 1'b0};
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
valid_out <= 1'b0;
else if (cnt == 3'b0)
valid_out <= 1'b1;
else
valid_out <= 1'b0;
end
always @(posedge clk) begin
if (valid_out)
dout <= data[3];
end
endmodule |
module radix2_div #(parameter DATAWIDTH = 8)(
input clk,
input rstn,
input en,
input [DATAWIDTH-1:0] dividend,
input [DATAWIDTH-1:0] divisor,
output reg ready,
output reg [DATAWIDTH-1:0] quotient,
output reg [DATAWIDTH-1:0] remainder,
output reg vld_out
);
// State enumeration
localparam IDLE = 2'b00;
localparam SUB = 2'b01;
localparam SHIFT = 2'b10;
localparam DONE = 2'b11;
// State registers
reg [1:0] current_state;
reg [1:0] next_state;
// Data registers
reg [DATAWIDTH:0] dividend_e;
reg [DATAWIDTH:0] divisor_e;
reg [DATAWIDTH:0] quotient_e;
reg [DATAWIDTH:0] remainder_e;
reg [DATAWIDTH-1:0] count;
always @(posedge clk or negedge rstn) begin
if (~rstn)
current_state <= IDLE;
else
current_state <= next_state;
end
always @(current_state, en, dividend, divisor) begin
case (current_state)
IDLE: begin
if (en)
next_state = SUB;
else
next_state = IDLE;
end
SUB: begin
next_state = SHIFT;
end
SHIFT: begin
if (count == DATAWIDTH)
next_state = DONE;
else
next_state = SUB;
end
DONE: begin
next_state = IDLE;
end
endcase
end
always @(*) begin
case (current_state)
IDLE: begin
ready = 1'b1;
vld_out = 1'b0;
end
SUB: begin
dividend_e = {dividend, 1'b0};
divisor_e = {divisor, 1'b0};
quotient_e = {quotient, 1'b0};
remainder_e = {remainder, 1'b0};
if (dividend_e >= divisor_e) begin
quotient_e = quotient_e + 1'b1;
remainder_e = dividend_e - divisor_e;
end
end
SHIFT: begin
count = count + 1'b1;
dividend_e = remainder_e;
quotient_e = {quotient_e[DATAWIDTH-2:0], 1'b0};
remainder_e = {remainder_e[DATAWIDTH-2:0], 1'b0};
end
DONE: begin
quotient = quotient_e[DATAWIDTH-1:0];
remainder = remainder_e[DATAWIDTH-1:0];
ready = 1'b0;
vld_out = 1'b1;
end
endcase
end
always @(negedge rstn) begin
if (~rstn) begin
dividend_e <= 0;
divisor_e <= 0;
quotient_e <= 0;
remainder_e <= 0;
count <= 0;
end
end
endmodule |
module signal_generator (
input clk,
input rst_n,
output reg [4:0] wave
);
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= 0;
wave <= 0;
end
else begin
case (state)
0: begin
if (wave == 31)
state <= 1;
else
wave <= wave + 1;
end
1: begin
if (wave == 0)
state <= 0;
else
wave <= wave - 1;
end
endcase
end
end
endmodule |
module multi_booth_8bit (
input clk,
input reset,
input [7:0] a,
input [7:0] b,
output reg [15:0] p,
output reg rdy
);
reg [7:0] multiplicand;
reg [7:0] multiplier;
reg [3:0] ctr;
always @(posedge clk or posedge reset) begin
if (reset) begin
multiplicand <= 8'b0;
multiplier <= 8'b0;
ctr <= 4'b0;
p <= 16'b0;
rdy <= 1'b0;
end
else begin
if (ctr < 4'b10000) begin
multiplicand <= multiplicand << 1;
if (multiplier[ctr] == 1'b1)
p <= p + multiplicand;
ctr <= ctr + 1;
end
if (ctr == 4'b10000)
rdy <= 1'b1;
end
end
endmodule |
module pe (
input clk,
input rst,
input [31:0] a,
input [31:0] b,
output reg [31:0] c
);
always @(posedge clk or posedge rst) begin
if (rst)
c <= 32'b0;
else
c <= c + (a * b);
end
endmodule |
module pulse_detect (
input clk,
input rst_n,
input data_in,
output reg data_out
);
reg [2:0] state;
reg [2:0] next_state;
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
state <= 3'b000;
else
state <= next_state;
end
always @(state, data_in) begin
case (state)
3'b000: begin
if (data_in)
next_state = 3'b001;
else
next_state = 3'b000;
end
3'b001: begin
if (data_in)
next_state = 3'b010;
else
next_state = 3'b000;
end
3'b010: begin
if (data_in)
next_state = 3'b011;
else
next_state = 3'b000;
end
3'b011: begin
if (~data_in)
next_state = 3'b100;
else
next_state = 3'b011;
end
default: next_state = 3'b000;
endcase
end
always @(state) begin
if (state == 3'b011)
data_out = 1'b1;
else
data_out = 1'b0;
end
endmodule |
module synchronizer (
input clk_a,
input clk_b,
input arstn,
input brstn,
input [3:0] data_in,
input data_en,
output reg [3:0] dataout
);
reg [3:0] data_reg;
reg en_data_reg;
reg en_clap_one, en_clap_two;
always @(posedge clk_a or negedge arstn) begin
if (~arstn) begin
data_reg <= 0;
en_data_reg <= 0;
end
else begin
data_reg <= data_in;
en_data_reg <= data_en;
end
end
always @(posedge clk_b or negedge brstn) begin
if (~brstn) begin
en_clap_one <= 0;
en_clap_two <= 0;
dataout <= 0;
end
else begin
en_clap_one <= en_data_reg;
en_clap_two <= en_clap_one;
if (en_clap_two)
dataout <= data_reg;
end
end
endmodule |
module width_8to16(
input clk,
input rst_n,
input valid_in,
input [7:0] data_in,
output valid_out,
output [15:0] data_out
);
reg [7:0] data_lock;
reg [15:0] data_out_reg;
reg flag;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_lock <= 8'b0;
data_out_reg <= 16'b0;
flag <= 1'b0;
end
else begin
if (valid_in) begin
if (!flag) begin
data_lock <= data_in;
flag <= 1'b1;
end
else begin
data_out_reg <= {data_lock, data_in};
flag <= 1'b0;
end
end
end
end
assign valid_out = flag;
assign data_out = data_out_reg;
endmodule |
module JC_counter (
input clk,
input rst_n,
output reg [63:0] Q
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
Q <= 64'b0;
end
else begin
if (Q[0] == 1'b0) begin
Q <= {Q[62:0], 1'b1};
end
else begin
Q <= {Q[62:0], 1'b0};
end
end
end
endmodule |
module adder_pipe_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] stage1_adda, stage1_addb;
reg [64:0] stage1_sum;
reg [63:0] stage2_adda, stage2_addb;
reg [64:0] stage2_sum;
reg [63:0] stage3_adda, stage3_addb;
reg [64:0] stage3_sum;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
stage1_adda <= 64'b0;
stage1_addb <= 64'b0;
stage1_sum <= 65'b0;
stage2_adda <= 64'b0;
stage2_addb <= 64'b0;
stage2_sum <= 65'b0;
stage3_adda <= 64'b0;
stage3_addb <= 64'b0;
stage3_sum <= 65'b0;
result <= 65'b0;
o_en <= 1'b0;
end
else begin
if (i_en) begin
stage1_adda <= adda;
stage1_addb <= addb;
stage1_sum <= stage1_adda + stage1_addb;
end
else begin
stage1_adda <= 64'b0;
stage1_addb <= 64'b0;
stage1_sum <= 65'b0;
end
stage2_adda <= stage1_adda;
stage2_addb <= stage1_addb;
stage2_sum <= stage1_sum;
stage3_adda <= stage2_adda;
stage3_addb <= stage2_addb;
stage3_sum <= stage2_sum;
result <= stage3_sum;
o_en <= i_en;
end
end
endmodule |
module right_shifter (
input clk,
input d,
output reg [7:0] q
);
always @(posedge clk) begin
q <= {q[6:0], d};
end
initial begin
q <= 8'b0;
end
endmodule |
module serial2parallel (
input wire clk,
input wire rst_n,
input wire din_serial,
input wire din_valid,
output reg [7:0] dout_parallel,
output reg dout_valid
);
reg [3:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
cnt <= 4'b0000;
dout_parallel <= 8'b0;
dout_valid <= 0;
end else begin
if (din_valid) begin
if (cnt < 4'b1000) begin
cnt <= cnt + 1;
dout_parallel[cnt] <= din_serial;
end else begin
dout_valid <= 1;
end
end
end
end
endmodule |
module multi_16bit (
input clk,
input rst_n,
input start,
input [15:0] ain,
input [15:0] bin,
output reg [31:0] yout,
output reg done
);
reg [3:0] i;
reg [15:0] areg;
reg [15:0] breg;
reg [31:0] yout_r;
reg done_r;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
i <= 4'b0;
yout_r <= 32'b0;
done_r <= 1'b0;
end
else begin
if (start && (i < 4'b10000)) begin
i <= i + 1;
end
else if (!start) begin
i <= 4'b0;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
areg <= 16'b0;
breg <= 16'b0;
end
else begin
if (start) begin
if (i == 4'b0) begin
areg <= ain;
breg <= bin;
end
else if ((i > 4'b0) && (i < 4'b10001)) begin
if (areg[i-1] == 1'b1) begin
yout_r <= yout_r + (breg << (i-1));
end
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
yout <= 32'b0;
done <= 1'b0;
end
else begin
yout <= yout_r;
done <= done_r;
if (i == 4'b10000) begin
done_r <= 1'b1;
end
else if (i == 4'b10001) begin
done_r <= 1'b0;
end
end
end
endmodule |
module freq_div (
input CLK_in,
input RST,
output reg CLK_50,
output reg CLK_10,
output reg CLK_1
);
reg [2:0] cnt_10;
reg [5:0] cnt_100;
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_50 <= 0;
CLK_10 <= 0;
CLK_1 <= 0;
cnt_10 <= 0;
cnt_100 <= 0;
end
else begin
// CLK_50 generation
CLK_50 <= ~CLK_50;
// CLK_10 generation
if (cnt_10 == 4) begin
CLK_10 <= ~CLK_10;
cnt_10 <= 0;
end
else begin
cnt_10 <= cnt_10 + 1;
end
// CLK_1 generation
if (cnt_100 == 49) begin
CLK_1 <= ~CLK_1;
cnt_100 <= 0;
end
else begin
cnt_100 <= cnt_100 + 1;
end
end
end
endmodule |
module calendar (
input CLK,
input RST,
output reg [5:0] Hours,
output reg [5:0] Mins,
output reg [5:0] Secs
);
always @(posedge CLK or posedge RST) begin
if (RST)
Secs <= 6'b0;
else if (Secs == 6'b111111)
Secs <= 6'b0;
else
Secs <= Secs + 1;
end
always @(posedge CLK or posedge RST) begin
if (RST)
Mins <= 6'b0;
else if (Secs == 6'b111111 && Mins == 6'b111111)
Mins <= 6'b0;
else if (Secs == 6'b111111)
Mins <= Mins + 1;
end
always @(posedge CLK or posedge RST) begin
if (RST)
Hours <= 6'b0;
else if (Secs == 6'b111111 && Mins == 6'b111111 && Hours == 6'b101111)
Hours <= 6'b0;
else if (Secs == 6'b111111 && Mins == 6'b111111)
Hours <= Hours + 1;
end
endmodule |
module adder_8bit(
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
// Define internal signals
wire [7:0] carry;
wire [7:0] sum_intermediate;
// Instantiate full adders
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : full_adder_inst
full_adder full_adder_inst(
.a(a[i]),
.b(b[i]),
.cin(i ? carry[i-1] : cin),
.sum(sum_intermediate[i]),
.cout(carry[i])
);
end
endgenerate
// Assign the outputs
assign sum = sum_intermediate;
assign cout = carry[7];
endmodule |
module full_adder(
input a,
input b,
input cin,
output sum,
output cout
);
// Implement full adder logic
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule |
module radix2_div #(
parameter DATAWIDTH = 8
)(
input wire clk,
input wire rstn,
input wire en,
input wire [DATAWIDTH-1:0] dividend,
input wire [DATAWIDTH-1:0] divisor,
output wire ready,
output wire [DATAWIDTH-1:0] quotient,
output wire [DATAWIDTH-1:0] remainder,
output wire vld_out
);
localparam LOG2_DATAWIDTH = $clog2(DATAWIDTH);
reg [LOG2_DATAWIDTH:0] current_state;
reg [LOG2_DATAWIDTH-1:0] dividend_e;
reg [LOG2_DATAWIDTH-1:0] divisor_e;
reg [LOG2_DATAWIDTH-1:0] quotient_e;
reg [LOG2_DATAWIDTH-1:0] remainder_e;
reg [LOG2_DATAWIDTH-1:0] count;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
// Reset condition
current_state <= 0;
dividend_e <= 0;
divisor_e <= 0;
quotient_e <= 0;
remainder_e <= 0;
count <= 0;
end
else begin
// State transition logic
case (current_state)
0: begin // IDLE
if (en) begin
current_state <= 1; // Transition to SUB state
dividend_e <= {dividend, {LOG2_DATAWIDTH{1'b0}}}; // Extend dividend
divisor_e <= {divisor, {LOG2_DATAWIDTH{1'b0}}}; // Extend divisor
end
end
1: begin // SUB
if (dividend_e >= divisor_e) begin
current_state <= 2; // Transition to SHIFT state
quotient_e <= quotient_e + {1'b1, {LOG2_DATAWIDTH{1'b0}}}; // Increment quotient
remainder_e <= dividend_e - divisor_e; // Calculate remainder
end
else begin
current_state <= 1; // Stay in SUB state
quotient_e <= quotient_e + {1'b0, {LOG2_DATAWIDTH{1'b0}}}; // Append 0 to quotient
remainder_e <= dividend_e; // Remainder remains the same
end
end
2: begin // SHIFT
if (count == (DATAWIDTH - 1)) begin
current_state <= 3; // Transition to DONE state
end
else begin
current_state <= 2; // Stay in SHIFT state
dividend_e <= dividend_e << 1; // Shift dividend left
count <= count + 1; // Increment count
end
end
3: begin // DONE
current_state <= 0; // Transition back to IDLE state
end
endcase
end
end
assign ready = (current_state == 0);
assign quotient = quotient_e;
assign remainder = remainder_e;
assign vld_out = (current_state == 3);
endmodule |
module accu (
input wire clk,
input wire rst_n,
input wire [7:0] data_in,
input wire valid_in,
output wire valid_out,
output wire [9:0] data_out
);
reg [9:0] accumulator;
reg [2:0] counter;
reg valid_out_reg;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
accumulator <= 10'b0;
counter <= 3'b0;
valid_out_reg <= 1'b0;
end else begin
if (valid_in) begin
accumulator <= accumulator + data_in;
counter <= counter + 1'b1;
end
if (counter == 3'b11) begin
valid_out_reg <= 1'b1;
counter <= 3'b0;
end else begin
valid_out_reg <= 1'b0;
end
end
end
assign valid_out = valid_out_reg;
assign data_out = accumulator;
endmodule |
module signal_generator (
input wire clk,
input wire rst_n,
output reg [4:0] wave
);
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= 2'b0;
wave <= 5'b0;
end
else begin
case (state)
2'b0:
begin
if (wave == 5'b11111)
state <= 2'b1;
else
wave <= wave + 1;
end
2'b1:
begin
if (wave == 5'b00000)
state <= 2'b0;
else
wave <= wave - 1;
end
endcase
end
end
endmodule |
module synchronizer (
input wire clk_a,
input wire clk_b,
input wire arstn,
input wire brstn,
input wire [3:0] data_in,
input wire data_en,
output reg [3:0] dataout
);
reg [3:0] data_reg;
reg en_data_reg;
reg en_clap_one;
reg en_clap_two;
always @(posedge clk_a or negedge arstn) begin
if (~arstn) begin
data_reg <= 4'b0000;
en_data_reg <= 1'b0;
end
else begin
data_reg <= data_in;
en_data_reg <= data_en;
end
end
always @(posedge clk_b or negedge brstn) begin
if (~brstn) begin
en_clap_one <= 1'b0;
en_clap_two <= 1'b0;
dataout <= 4'b0000;
end
else begin
en_clap_one <= en_data_reg;
en_clap_two <= en_clap_one;
if (en_clap_two)
dataout <= data_reg;
end
end
endmodule |
module asyn_fifo #
(
parameter WIDTH = 8,
parameter DEPTH = 16
)
(
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [WIDTH-1:0] wdata,
output reg wfull,
output reg rempty,
output reg [WIDTH-1:0] rdata
);
// Dual-port RAM submodule
dual_port_RAM #
(
.WIDTH(WIDTH),
.DEPTH(DEPTH)
)
ram
(
.wclk(wclk),
.wenc(winc),
.waddr(wptr[3:0]),
.wdata(wdata),
.rclk(rclk),
.renc(rinc),
.raddr(rptr[3:0]),
.rdata(rdata)
);
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
// Write pointer logic
always @(posedge wclk or negedge wrstn)
begin
if (~wrstn)
wptr <= 4'b0000;
else if (winc)
wptr <= wptr + 1;
end
// Read pointer logic
always @(posedge rclk or negedge rrstn)
begin
if (~rrstn)
rptr <= 4'b0000;
else if (rinc)
rptr <= rptr + 1;
end
// Gray code conversion for write pointer
always @*
begin
wptr_syn[0] = wptr[0];
wptr_syn[1] = wptr[0] ^ wptr[1];
wptr_syn[2] = wptr[1] ^ wptr[2];
wptr_syn[3] = wptr[2] ^ wptr[3];
end
// Gray code conversion for read pointer
always @*
begin
rptr_syn[0] = rptr[0];
rptr_syn[1] = rptr[0] ^ rptr[1];
rptr_syn[2] = rptr[1] ^ rptr[2];
rptr_syn[3] = rptr[2] ^ rptr[3];
end
// Pointer buffers
always @(posedge wclk or negedge wrstn)
begin
if (~wrstn)
wptr_buff <= 4'b0000;
else
wptr_buff <= wptr_syn;
end
always @(posedge rclk or negedge rrstn)
begin
if (~rrstn)
rptr_buff <= 4'b0000;
else
rptr_buff <= rptr_syn;
end
// Full and empty signals
always @*
begin
wfull = (wptr_syn == ~rptr_buff[3] & rptr_buff[2:0]);
rempty = (rptr_syn == wptr_buff);
end
endmodule |
module fsm (
input IN,
input CLK,
input RST,
output reg MATCH
);
reg [4:0] state;
reg [4:0] next_state;
parameter S0 = 5'b00000;
parameter S1 = 5'b00001;
parameter S2 = 5'b00010;
parameter S3 = 5'b00011;
parameter S4 = 5'b00100;
always @(posedge CLK or posedge RST) begin
if (RST) begin
state <= S0;
MATCH <= 0;
end
else begin
state <= next_state;
MATCH <= (state == S4);
end
end
always @(state or IN) begin
case (state)
S0: begin
if (IN)
next_state <= S1;
else
next_state <= S0;
end
S1: begin
if (IN)
next_state <= S1;
else
next_state <= S2;
end
S2: begin
if (IN)
next_state <= S1;
else
next_state <= S3;
end
S3: begin
if (IN)
next_state <= S4;
else
next_state <= S0;
end
S4: begin
if (IN)
next_state <= S1;
else
next_state <= S2;
end
endcase
end
endmodule |
module adder_pipe_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] stage1;
reg [63:0] stage2;
reg [63:0] stage3;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
stage1 <= 64'b0;
stage2 <= 64'b0;
stage3 <= 64'b0;
result <= 65'b0;
o_en <= 1'b0;
end else begin
if (i_en) begin
stage1 <= adda + addb;
stage2 <= stage1 + stage2[63:0];
stage3 <= stage2 + stage3[63:0];
result <= {stage3[63], stage3};
o_en <= 1'b1;
end else begin
stage1 <= 64'b0;
stage2 <= 64'b0;
stage3 <= 64'b0;
result <= 65'b0;
o_en <= 1'b0;
end
end
end
endmodule |
module right_shifter (
input wire clk,
input wire d,
output reg [7:0] q
);
always @(posedge clk) begin
q <= {d, q[7:1]};
end
initial begin
q <= 8'b0;
end
endmodule |
module multi_16bit (
input clk,
input rst_n,
input start,
input [15:0] ain,
input [15:0] bin,
output [31:0] yout,
output reg done
);
reg [3:0] i;
reg [15:0] areg;
reg [15:0] breg;
reg [31:0] yout_r;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
i <= 4'b0000;
areg <= 16'b0;
breg <= 16'b0;
yout_r <= 32'b0;
done <= 0;
end
else begin
if (start && (i < 4'b10001))
i <= i + 1;
else if (!start)
i <= 4'b0000;
if (i == 4'b10000)
done <= 1;
else if (i == 4'b10001)
done <= 0;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
areg <= 16'b0;
breg <= 16'b0;
yout_r <= 32'b0;
end
else begin
if (start) begin
if (i == 4'b0000) begin
areg <= ain;
breg <= bin;
end
else if ((i > 4'b0000) && (i < 4'b10001)) begin
if (areg[i-1])
yout_r <= yout_r + (breg << (i-1));
end
end
end
end
assign yout = yout_r;
endmodule |
module edge_detect (
input clk,
input rst_n,
input a,
output reg rise,
output reg down
);
reg a_prev;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rise <= 0;
down <= 0;
a_prev <= 0;
end
else begin
if (a && !a_prev) // Rising edge detection
rise <= 1;
else
rise <= 0;
if (!a && a_prev) // Falling edge detection
down <= 1;
else
down <= 0;
a_prev <= a;
end
end
endmodule |
module cla_16bit(
input [15:0] A,
input [15:0] B,
input C_in,
output [16:0] S,
output C_out
);
wire [16:0] P, G;
wire [16:0] C;
assign P[0] = A[0] ^ B[0];
assign G[0] = A[0] & B[0];
assign C[0] = C_in;
generate
genvar i;
for (i = 1; i < 16; i = i + 1) begin : gen
assign P[i] = A[i] ^ B[i];
assign G[i] = A[i] & B[i];
assign C[i] = G[i - 1] | (P[i - 1] & C[i - 1]);
end
endgenerate
assign S = {C[15], C};
assign C_out = G[15] | (P[15] & C[15]);
endmodule |
module adder_32bit(
input [31:0] A,
input [31:0] B,
output [31:0] S,
output C32
);
wire [16:0] C;
wire [16:0] S_intermediate;
cla_16bit cla0(.A(A[15:0]), .B(B[15:0]), .C_in(1'b0), .S(S_intermediate[15:0]), .C_out(C[0]));
cla_16bit cla1(.A(A[31:16]), .B(B[31:16]), .C_in(C[0]), .S(S_intermediate[31:16]), .C_out(C[1]));
assign S = {S_intermediate[31], S_intermediate[31:16]};
assign C32 = C[1];
endmodule |
module signal_generator (
input wire clk,
input wire rst_n,
output reg [4:0] wave
);
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= 2'b00;
wave <= 5'b0;
end else begin
case (state)
2'b00: begin
if (wave == 5'b11111)
state <= 2'b01;
else
wave <= wave + 1;
end
2'b01: begin
if (wave == 5'b00000)
state <= 2'b00;
else
wave <= wave - 1;
end
default: state <= 2'b00;
endcase
end
end
endmodule |
module multi_booth_8bit (
input clk,
input reset,
input [7:0] a,
input [7:0] b,
output reg [15:0] p,
output reg rdy
);
reg [3:0] ctr;
reg [7:0] multiplicand;
reg [7:0] multiplier;
always @(posedge clk or posedge reset) begin
if (reset) begin
ctr <= 4'b0000;
multiplicand <= 8'b0;
multiplier <= 8'b0;
p <= 16'b0;
rdy <= 0;
end
else begin
if (ctr < 4'b10000) begin
multiplicand <= multiplicand << 1;
if (multiplier[ctr] == 1)
p <= p + multiplicand;
ctr <= ctr + 1;
end
else begin
rdy <= 1;
end
end
end
always @(posedge clk) begin
if (reset)
p <= 16'b0;
end
endmodule |
module pe (
input wire clk,
input wire rst,
input wire [31:0] a,
input wire [31:0] b,
output wire [31:0] c
);
reg [31:0] c_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
// Reset condition
c_reg <= 32'd0;
end
else begin
// Multiplication and accumulation
c_reg <= c_reg + (a * b);
end
end
assign c = c_reg;
endmodule |
module adder_16bit (
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [7:0] carry;
wire [7:0] sum;
// Instantiating eight 8-bit adders
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : ADDER_INST
// Instantiating 8-bit adder
adder_8bit adder_inst (
.a(a[i*2 +: 8]), // Extracting 8-bit portion from a
.b(b[i*2 +: 8]), // Extracting 8-bit portion from b
.Cin(i ? carry[i-1] : Cin), // Using carry from previous adder or Cin for the first adder
.y(y[i*2 +: 8]), // Storing the 8-bit sum
.Co(carry[i]) // Storing the carry-out
);
end
endgenerate
// Generating carry-out for the 16-bit output
assign Co = carry[7];
endmodule |
module adder_8bit (
input [7:0] a,
input [7:0] b,
input Cin,
output [7:0] y,
output Co
);
wire [7:0] carry;
wire [7:0] sum;
// Generating sum and carry for each bit position
assign {carry[0], sum[0]} = a[0] + b[0] + Cin;
assign {carry[1], sum[1]} = a[1] + b[1] + carry[0];
assign {carry[2], sum[2]} = a[2] + b[2] + carry[1];
assign {carry[3], sum[3]} = a[3] + b[3] + carry[2];
assign {carry[4], sum[4]} = a[4] + b[4] + carry[3];
assign {carry[5], sum[5]} = a[5] + b[5] + carry[4];
assign {carry[6], sum[6]} = a[6] + b[6] + carry[5];
assign {carry[7], sum[7]} = a[7] + b[7] + carry[6];
// Storing the sum and carry-out
assign y = sum;
assign Co = carry[7];
endmodule |
module pulse_detect (
input clk,
input rst_n,
input data_in,
output reg data_out
);
reg [1:0] state;
parameter IDLE = 2'b00;
parameter DETECT = 2'b01;
parameter PULSE_END = 2'b10;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= IDLE;
data_out <= 1'b0;
end
else begin
case (state)
IDLE:
if (data_in == 1'b1)
state <= DETECT;
else
state <= IDLE;
DETECT:
if (data_in == 1'b0)
state <= PULSE_END;
else
state <= DETECT;
PULSE_END:
if (data_in == 1'b0)
state <= IDLE;
else
state <= DETECT;
endcase
if (state == PULSE_END)
data_out <= 1'b1;
else
data_out <= 1'b0;
end
end
endmodule |
module fsm (
input IN,
input CLK,
input RST,
output reg MATCH
);
reg [4:0] state;
reg [4:0] next_state;
parameter S0 = 5'b00000; // Initial state
parameter S1 = 5'b00001; // State after detecting 1
parameter S2 = 5'b00010; // State after detecting 10
parameter S3 = 5'b00011; // State after detecting 100
parameter S4 = 5'b00100; // State after detecting 1001
parameter S5 = 5'b00101; // State after detecting 10011
always @(posedge CLK or posedge RST) begin
if (RST) begin
MATCH <= 0;
state <= S0;
end
else begin
state <= next_state;
MATCH <= (state == S5);
end
end
always @(state or IN) begin
case (state)
S0: begin
if (IN)
next_state = S1;
else
next_state = S0;
end
S1: begin
if (IN)
next_state = S1;
else
next_state = S2;
end
S2: begin
if (IN)
next_state = S1;
else
next_state = S3;
end
S3: begin
if (IN)
next_state = S4;
else
next_state = S0;
end
S4: begin
if (IN)
next_state = S1;
else
next_state = S5;
end
S5: begin
if (IN)
next_state = S1;
else
next_state = S5;
end
default: next_state = S0;
endcase
end
endmodule |
module edge_detect (
input clk,
input rst_n,
input a,
output reg rise,
output reg down
);
reg a_prev;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
rise <= 0;
down <= 0;
a_prev <= 0;
end
else begin
if (a && ~a_prev)
rise <= 1;
else
rise <= 0;
if (~a && a_prev)
down <= 1;
else
down <= 0;
a_prev <= a;
end
end
endmodule |
module adder_8bit(
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
wire [7:0] carry;
wire [7:0] sum_intermediate;
// First bit-level adder
full_adder FA0(.a(a[0]), .b(b[0]), .cin(cin), .sum(sum_intermediate[0]), .cout(carry[0]));
// Intermediate bit-level adders
genvar i;
generate
for (i = 1; i < 8; i = i + 1) begin : GEN_ADDERS
full_adder FA(.a(a[i]), .b(b[i]), .cin(carry[i-1]), .sum(sum_intermediate[i]), .cout(carry[i]));
end
endgenerate
// Final bit-level adder
full_adder FA_last(.a(a[7]), .b(b[7]), .cin(carry[6]), .sum(sum[7]), .cout(cout));
assign sum[6:0] = sum_intermediate[6:0];
endmodule |
module full_adder(
input a,
input b,
input cin,
output sum,
output cout
);
assign {cout, sum} = a + b + cin;
endmodule |
module pe(
input wire clk,
input wire rst,
input wire [31:0] a,
input wire [31:0] b,
output wire [31:0] c
);
reg [31:0] c_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
c_reg <= 0;
end else begin
c_reg <= c_reg + (a * b);
end
end
assign c = c_reg;
endmodule |
module pulse_detect (
input wire clk,
input wire rst_n,
input wire data_in,
output wire data_out
);
reg [1:0] state;
reg data_out_reg;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Reset condition
state <= 2'b00;
data_out_reg <= 1'b0;
end
else begin
case (state)
2'b00: begin
if (data_in) begin
state <= 2'b01;
end
end
2'b01: begin
if (~data_in) begin
state <= 2'b10;
end
end
2'b10: begin
if (data_in) begin
state <= 2'b11;
data_out_reg <= 1'b1;
end
else begin
state <= 2'b00;
data_out_reg <= 1'b0;
end
end
2'b11: begin
if (~data_in) begin
state <= 2'b00;
data_out_reg <= 1'b0;
end
end
endcase
end
end
assign data_out = data_out_reg;
endmodule |
module fsm (
input IN,
input CLK,
input RST,
output reg MATCH
);
reg [4:0] state;
reg [4:0] next_state;
parameter S0 = 5'b00000;
parameter S1 = 5'b00001;
parameter S2 = 5'b00010;
parameter S3 = 5'b00011;
parameter S4 = 5'b00100;
parameter S5 = 5'b00101;
always @(posedge CLK or posedge RST) begin
if (RST) begin
state <= S0;
MATCH <= 1'b0;
end else begin
state <= next_state;
MATCH <= (state == S4);
end
end
always @(IN, state) begin
case (state)
S0: begin
if (IN)
next_state = S1;
else
next_state = S0;
end
S1: begin
if (IN)
next_state = S1;
else
next_state = S2;
end
S2: begin
if (IN)
next_state = S3;
else
next_state = S0;
end
S3: begin
if (IN)
next_state = S1;
else
next_state = S4;
end
S4: begin
if (IN)
next_state = S5;
else
next_state = S2;
end
S5: begin
if (IN)
next_state = S5;
else
next_state = S0;
end
default: next_state = S0;
endcase
end
endmodule |
module adder_8bit(
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
wire [7:0] carry;
wire [7:0] carry_out;
// Instantiate 8 full adders
// Connect the carry-in and carry-out signals appropriately
full_adder fa0(a[0], b[0], cin, sum[0], carry[0]);
full_adder fa1(a[1], b[1], carry[0], sum[1], carry[1]);
full_adder fa2(a[2], b[2], carry[1], sum[2], carry[2]);
full_adder fa3(a[3], b[3], carry[2], sum[3], carry[3]);
full_adder fa4(a[4], b[4], carry[3], sum[4], carry[4]);
full_adder fa5(a[5], b[5], carry[4], sum[5], carry[5]);
full_adder fa6(a[6], b[6], carry[5], sum[6], carry[6]);
full_adder fa7(a[7], b[7], carry[6], sum[7], carry_out[7]);
// Assign the carry-out of the last full adder to cout
assign cout = carry_out[7];
endmodule |
module full_adder(
input a,
input b,
input cin,
output sum,
output carry_out
);
assign {carry_out, sum} = a + b + cin;
endmodule |
module accu (
input clk,
input rst_n,
input [7:0] data_in,
input valid_in,
output reg valid_out,
output reg [9:0] data_out
);
reg [9:0] accumulator;
reg [3:0] count;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
accumulator <= 10'b0;
count <= 4'b0;
valid_out <= 1'b0;
end
else begin
if (valid_in) begin
accumulator <= accumulator + data_in;
count <= count + 1'b1;
if (count == 4'b11) begin
data_out <= accumulator;
valid_out <= 1'b1;
end
else begin
valid_out <= 1'b0;
end
end
end
end
endmodule |
module tb_RCA4;
wire [3:0] sum;
wire cout;
reg [3:0] a, b;
reg cin;
RCA4 rca4(sum[3:0], cout, a[3:0], b[3:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b|%b", a[3:0], b[3:0], cout, sum[3:0]);
end
initial
begin
a=4'b1010; b=4'b1010;
#10 a=4'b1000; b=4'b1100;
#10 a=4'b0011; b=4'b1111;
end
endmodule |
module tb_CSkipA8;
wire [7:0] sum;
wire cout;
reg [7:0] a, b;
CSkipA8 csa8(sum[7:0], cout, a[7:0], b[7:0]);
initial
begin
$display("a |b ||cout|sum ");
end
initial
begin
$monitor("%b|%b||%b |%b", a[7:0], b[7:0], cout, sum[7:0]);
end
initial
begin
a=8'b10100000; b=8'b10100000;
#10 a=8'b01011000; b=8'b11110100;
#10 a=8'b00111101; b=8'b00001111;
#10 a=8'b11001010; b=8'b11001000;
#10 a=8'b10100110; b=8'b11110100;
#10 a=8'b11110011; b=8'b11001100;
#10 a=8'b11110011; b=8'b01010111;
end
endmodule |
module tb_CSkipA16;
wire [15:0] sum;
wire cout;
reg [15:0] a, b;
CSkipA16 csa16(sum[15:0], cout, a[15:0], b[15:0]);
initial
begin
$display("a |b ||cout|sum ");
end
initial
begin
$monitor("%b|%b||%b |%b", a[15:0], b[15:0], cout, sum[15:0]);
end
initial
begin
a=16'b1010000010100000; b=16'b1010000010100000;
#10 a=16'b0101100011110100; b=16'b1111010011110100;
#10 a=16'b0000111100111101; b=16'b0000111100001111;
#10 a=16'b1100100011001010; b=16'b1100100011001010;
end
endmodule |
module tb_CSkipA32;
wire [31:0] sum;
wire cout;
reg [31:0] a, b;
reg cin;
CSkipA32 sca32(sum[31:0], cout, a[31:0], b[31:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%b|%b||%b|%b", a[31:0], b[31:0], cout, sum[31:0]);
end
initial
begin
a='b10100000101000001111111111111111; b='b10100000101111111111111111100000;
#10 a='b01011000111111111111111111110100; b='b11110100111101001111111111111111;
#10 a='b11111111111111110000111100111101; b='b00001111000011111111111111111111;
#10 a='b11011111111111111110100011001010; b='b11001111111111111111100011001010;
end
endmodule |
module tb_CSkipA64;
wire [63:0] sum;
wire cout;
reg [63:0] a, b;
reg cin;
CSkipA64 csa64(sum[63:0], cout, a[63:0], b[63:0]);
initial
begin
$display("a|b||cout|sum");
end
initial
begin
$monitor("%d|%d||%d|%d", a[63:0], b[63:0], cout, sum[63:0]);
end
initial
begin
a=64'd998; b=64'd128;
#10 a=64'd9998; b=64'd9028;
#10 a=64'd999909989998; b=64'd769028;
end
endmodule |
module FA(output sum, cout, input a, b, cin);
wire w0, w1, w2;
xor (w0, a, b);
xor (sum, w0, cin);
and (w1, w0, cin);
and (w2, a, b);
or (cout, w1, w2);
endmodule |
module RCA4(output [3:0] sum, output cout, input [3:0] a, b, input cin);
wire [3:1] c;
FA fa0(sum[0], c[1], a[0], b[0], cin);
FA fa[2:1](sum[2:1], c[3:2], a[2:1], b[2:1], c[2:1]);
FA fa31(sum[3], cout, a[3], b[3], c[3]);
endmodule |
module SkipLogic(output cin_next,
input [3:0] a, b, input cin, cout);
wire p0, p1, p2, p3, P, e;
or (p0, a[0], b[0]);
or (p1, a[1], b[1]);
or (p2, a[2], b[2]);
or (p3, a[3], b[3]);
and (P, p0, p1, p2, p3);
and (e, P, cin);
or (cin_next, e, cout);
endmodule |
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