module
stringlengths 21
82.9k
|
|---|
module ipsl_pcie_reg #(
parameter SIG_WIDTH = 8
)(
input clk,
input [SIG_WIDTH-1:0] sig,
output reg [SIG_WIDTH-1:0] sig_reg
);
always@(posedge clk)
begin
sig_reg <= sig;
end
endmodule |
module pgs_pciex4_prefetch_fifo_v1_2
#(
parameter D = 16, //should be 2^N
parameter W = 8,
parameter TYPE = "Distributed" // "Distributed" or "DRM"
)
(
input clk,
input rst_n,
input data_in_valid,
input [W-1:0] data_in,
output data_in_ready,
input data_out_ready,
output [W-1:0] data_out,
output data_out_valid
);
//===================================================================
// Type | Latency | ADDR_WIDTH | Data width
// "Distributed" | 2 | 4~10 | 1~256
// "DRM" | 3 | 9~20 | 1~1152
//===================================================================
reg fifo_vld;
reg rd_en_ff1;
reg [2:0] shift_vld;
reg [W-1:0] rd_data_ff1;
wire [W-1:0] rd_data;
wire pop;
wire wr_en;
wire rd_en;
wire empty;
wire full;
wire rst;
//
assign wr_en = data_in_valid & ~full;
assign data_in_ready = ~full;
assign rst = ~rst_n;
//
generate
if (TYPE == "Distributed") //"Distributed"
begin
localparam DEPTH = (D < 16) ? 16 : D;
assign rd_en = ~empty & (~data_out_valid | data_out_ready);
assign data_out_valid = fifo_vld;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
fifo_vld <= 1'b0;
else if (rd_en)
fifo_vld <= 1'b1;
else if (data_out_ready)
fifo_vld <= 1'b0;
end
assign data_out = rd_data_ff1;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
rd_data_ff1 <= 1'b0;
else if (rd_en)
rd_data_ff1 <= rd_data;
end
// distributed_fifo
pgs_pciex4_fifo_v1_2
#(
.DATA_WIDTH ( W ),
.ADDR_WIDTH ( log2(DEPTH) ),
.OUT_REG ( 0 )
)
pgs_pciex4_fifo
(
.clk ( clk ),
.rst_n ( rst_n ),
.wr_data ( data_in ),
.wr_en ( wr_en ),
.full ( full ),
.rd_data ( rd_data ),
.rd_en ( rd_en ),
.empty ( empty )
);
end
else //"DRM"
begin
localparam DEPTH = (D < 512) ? 512 : D;
assign rd_en = (~shift_vld[2] | data_out_ready) & ~empty;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
rd_en_ff1 <= 1'b0;
else
rd_en_ff1 <= rd_en;
end
assign pop = data_out_valid & data_out_ready;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
shift_vld <= 3'b001;
else
begin
case ({rd_en, pop})
2'b10: shift_vld <= {shift_vld[1:0], shift_vld[2]};
2'b01: shift_vld <= {shift_vld[0], shift_vld[2:1]};
endcase
end
end
// DRM FIFO
pgm_fifo_v1_2
#(
.c_RD_DATA_WIDTH ( W ),
.c_WR_DEPTH_WIDTH ( log2(DEPTH) ),
.c_WR_DATA_WIDTH ( W ),
.c_RD_DEPTH_WIDTH ( log2(DEPTH) ),
.c_OUTPUT_REG ( 0 )
)
pgm_fifo_v1_2
(
.wr_data ( data_in ),
.wr_en ( wr_en ),
.wr_clk ( clk ),
.wr_full ( full ),
.wr_rst ( rst ),
.wr_byte_en ( 8'b0 ),
.almost_full ( ),
.wr_water_level ( ),
.rd_data ( rd_data ),
.rd_en ( rd_en ),
.rd_clk ( clk ),
.rd_empty ( empty ),
.rd_rst ( rst ),
.rd_oce ( 1'b1 ),
.almost_empty ( ),
.rd_water_level ( )
);
// Depth = 2
pgs_pciex4_reg_fifo2_v1_2
#(
.W ( W )
)
pgs_pciex4_reg_fifo2
(
.clk ( clk ),
.rst_n ( rst_n ),
.data_in_valid ( rd_en_ff1 ),
.data_in ( rd_data ),
.data_in_ready ( ),
.data_out_ready ( data_out_ready ),
.data_out ( data_out ),
.data_out_valid ( data_out_valid )
);
end
endgenerate
// Log 2
function integer log2;
input integer dep;
begin
log2 = 0;
while (dep > 1)
begin
dep = dep >> 1;
log2 = log2 + 1;
end
end
endfunction
endmodule |
module ipm_distributed_sdpram_v1_2
#(
parameter ADDR_WIDTH = 6 , //address width range:4-10
parameter DATA_WIDTH = 64 , //data width range:1-256
parameter RST_TYPE = "ASYNC" , //reset type "ASYNC" "SYNC"
parameter OUT_REG = 0 , //output options :non_register(0) register(1)
parameter INIT_FILE = "NONE" , //legal value:"NONE" or "initial file name"
parameter FILE_FORMAT = "BIN" //initial data format : "BIN" or "HEX"
)
(
input wire [DATA_WIDTH-1:0] wr_data ,
input wire [ADDR_WIDTH-1:0] wr_addr ,
input wire [ADDR_WIDTH-1:0] rd_addr ,
input wire wr_clk ,
input wire rd_clk ,
input wire wr_en ,
input wire rst ,
output wire [DATA_WIDTH-1:0] rd_data
)/* synthesis syn_ramstyle = "select_ram" */;
wire asyn_rst ;
wire syn_rst ;
wire [DATA_WIDTH-1:0] q ;
reg [DATA_WIDTH-1:0] q_reg ;
reg [DATA_WIDTH-1:0] mem [2**ADDR_WIDTH-1:0];
//***********************************************************************reset*******************************************************************
assign asyn_rst = (RST_TYPE == "ASYNC") ? rst : 0;
assign syn_rst = (RST_TYPE == "SYNC" ) ? rst : 0;
//initialize sdpram
generate
integer i,j;
if (INIT_FILE != "NONE") begin
if (FILE_FORMAT == "BIN") begin
initial begin
$readmemb(INIT_FILE,mem);
end
end
else if (FILE_FORMAT == "HEX") begin
initial begin
$readmemh(INIT_FILE,mem);
end
end
end
else begin
initial begin
for (i=0;i<2**ADDR_WIDTH;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
mem[i][j] = 1'b0;
end
end
end
end
endgenerate
//write & read
generate
always @(posedge wr_clk) begin
if(wr_en)
mem[wr_addr] <= wr_data;
end
assign q = mem[rd_addr];
if (RST_TYPE == "ASYNC") begin
always@(posedge rd_clk or posedge asyn_rst)
begin
if(asyn_rst)
q_reg <= {DATA_WIDTH{1'b0}};
else
q_reg <= q;
end
end
else if (RST_TYPE == "SYNC") begin
always@(posedge rd_clk)
begin
if(syn_rst)
q_reg <= {DATA_WIDTH{1'b0}};
else
q_reg <= q;
end
end
endgenerate
assign rd_data = (OUT_REG == 1) ? q_reg : q;
endmodule |
module ipsl_pcie_dma_tlp_rcv#(
parameter DEVICE_TYPE = 3'd0 //3'd0:EP,3'd1:Legacy EP,3'd4:RC
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
//**********************************************************************
//AXIS master interface
input i_axis_master_tvld ,
output wire o_axis_master_trdy ,
input [127:0] i_axis_master_tdata ,
input [3:0] i_axis_master_tkeep ,
input i_axis_master_tlast ,
input [7:0] i_axis_master_tuser ,
output reg [2:0] o_trgt1_radm_pkt_halt ,
// input [5:0] i_radm_grant_tlp_type ,
//**********************************************************************
//to mwr write control
output reg o_mwr_wr_start ,
output wire [9:0] o_mwr_length ,
output reg [7:0] o_mwr_dwbe ,
output reg [127:0] o_mwr_data ,
output reg [3:0] o_mwr_dw_vld ,
output reg [63:0] o_mwr_addr ,
//to cpld write control
output reg o_cpld_wr_start ,
output wire [9:0] o_cpld_length ,
output reg [6:0] o_cpld_low_addr ,
output reg [11:0] o_cpld_byte_cnt ,
output reg [127:0] o_cpld_data ,
output reg [3:0] o_cpld_dw_vld ,
output reg [7:0] o_cpld_tag ,
output reg o_multicpld_flag ,
//write bar hit
output reg [1:0] o_bar_hit ,
/////////////////////
//2'b0:bar0 hit
//2'b1:bar1 hit
//2'b2:bar2 hit
//2'b3:reserved
/////////////////////
//**********************************************************************
//to tx top
//req rcv
output reg [2:0] o_mrd_tc ,
output reg [2:0] o_mrd_attr ,
output wire [9:0] o_mrd_length ,
output reg [15:0] o_mrd_id ,
output reg [7:0] o_mrd_tag ,
output reg [63:0] o_mrd_addr ,
output reg o_cpld_req_vld ,
input i_cpld_req_rdy ,
input i_cpld_tx_rdy ,
//cpld rcv
output reg o_cpld_rcv ,
//output wire [7:0] o_cpld_tag,
input i_tag_full ,
//**********************************************************************
//rst tlp cnt
output reg [63:0] o_dma_check_result ,
input i_tx_restart
//form DMA controller
//output wire [42:0] o_dbg_bus ,
//output wire [69:0] o_dbg_tlp_rcv_cnt
);
localparam IDLE = 2'd0;
localparam HEAD_RCV = 2'd1;
localparam DATA_RCV = 2'd2;
localparam MRD_32 = 8'h0;
localparam MRD_64 = 8'h20;
localparam MRDLK_32 = 8'h01;
localparam MRDLK_64 = 8'h21;
localparam MWR_32 = 8'h40;
localparam MWR_64 = 8'h60;
localparam CPLD = 8'h4A;
localparam CPLDLK = 8'h4B;
//fsm
reg [1:0] state;
reg [1:0] next_state;
//
reg eop;
wire [2:0] tlp_fmt;
wire [4:0] tlp_type;
reg [9:0] tlp_length;
wire mrd32_rcv;
wire mrd64_rcv;
wire mrd_rcv;
wire mwr32_rcv;
wire mwr64_rcv;
wire mwr_rcv;
reg mwr_data_valid;
wire cpld_rcv;
reg cpld_data_valid;
reg with_data;
wire [127:0] axis_rx_data;
reg [11:0] dma_check_cnt;
reg [5:0] data_cnt;
reg axis_master_tvld;
reg axis_master_tvld_ff;
reg [127:0] axis_master_tdata;
reg [127:0] axis_master_tdata_ff;
reg [3:0] axis_master_tkeep;
reg [3:0] axis_master_tkeep_ff;
reg axis_master_tlast;
reg axis_master_tlast_ff;
reg [7:0] axis_master_tuser;
reg [7:0] axis_master_tuser_ff;
//reg [5:0] radm_grant_tlp_type;
//reg [5:0] radm_grant_tlp_type_ff;
//axis reg_in
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
axis_master_tvld <= 1'b0;
axis_master_tdata <= 128'b0;
axis_master_tkeep <= 4'b0;
axis_master_tlast <= 1'b0;
axis_master_tuser <= 8'b0;
//radm_grant_tlp_type <= 6'b0;
end
else
begin
axis_master_tvld <= i_axis_master_tvld;
axis_master_tdata <= i_axis_master_tdata;
axis_master_tkeep <= i_axis_master_tkeep;
axis_master_tlast <= i_axis_master_tlast;
axis_master_tuser <= i_axis_master_tuser;
//radm_grant_tlp_type <= i_radm_grant_tlp_type;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
axis_master_tvld_ff <= 1'b0;
axis_master_tdata_ff <= 128'b0;
axis_master_tkeep_ff <= 4'b0;
axis_master_tlast_ff <= 1'b0;
axis_master_tuser_ff <= 8'b0;
//radm_grant_tlp_type_ff <= 6'b0;
end
else
begin
axis_master_tvld_ff <= axis_master_tvld;
axis_master_tdata_ff <= axis_master_tdata;
axis_master_tkeep_ff <= axis_master_tkeep;
axis_master_tlast_ff <= axis_master_tlast;
axis_master_tuser_ff <= axis_master_tuser;
//radm_grant_tlp_type_ff <= radm_grant_tlp_type;
end
end
assign o_axis_master_trdy = 1'b1;
//fmt,type
assign tlp_fmt = axis_master_tdata_ff[31:29];
assign tlp_type = axis_master_tdata_ff[28:24];
//recive mrd
assign mrd32_rcv = ({tlp_fmt,tlp_type} == MRD_32 || {tlp_fmt,tlp_type} == MRDLK_32) && state == HEAD_RCV;
assign mrd64_rcv = ({tlp_fmt,tlp_type} == MRD_64 || {tlp_fmt,tlp_type} == MRDLK_64) && state == HEAD_RCV;
assign mrd_rcv = mrd32_rcv || mrd64_rcv;
//recive mwr
assign mwr32_rcv = ({tlp_fmt,tlp_type} == MWR_32) && state == HEAD_RCV;
assign mwr64_rcv = ({tlp_fmt,tlp_type} == MWR_64) && state == HEAD_RCV;
assign mwr_rcv = mwr32_rcv || mwr64_rcv;
//recive cpld
assign cpld_rcv = ({tlp_fmt,tlp_type} == CPLD || {tlp_fmt,tlp_type} == CPLDLK) && state == HEAD_RCV;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
mwr_data_valid <= 1'b0;
else if(axis_master_tlast_ff)
mwr_data_valid <= 1'b0;
else if(axis_master_tvld_ff && o_axis_master_trdy && state == HEAD_RCV)
mwr_data_valid <= mwr_rcv;
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
cpld_data_valid <= 1'b0;
else if(axis_master_tlast_ff)
cpld_data_valid <= 1'b0;
else if(axis_master_tvld_ff && o_axis_master_trdy && state == HEAD_RCV)
cpld_data_valid <= cpld_rcv;
end
//tlp with payload
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
with_data <= 1'b0;
else if(axis_master_tdata[30] && axis_master_tvld && o_axis_master_trdy)
with_data <= 1'b1;
else
with_data <= 1'b0;
end
//eop
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
eop <= 1'b0;
else if(axis_master_tlast && axis_master_tvld && o_axis_master_trdy)
eop <= 1'b1;
else
eop <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
state <= IDLE;
else
state <= next_state;
end
always @(*)
begin
case(state)
IDLE:
begin
if(axis_master_tvld && o_axis_master_trdy) //start transfer
next_state = HEAD_RCV;
else
next_state = IDLE;
end
HEAD_RCV:
begin
if(with_data)
next_state = DATA_RCV;
else if(~with_data && ~(o_axis_master_trdy && axis_master_tvld)) //without data
next_state = IDLE;
else
next_state = state;
end
DATA_RCV:
begin
if(eop && o_axis_master_trdy && axis_master_tvld)//back to back transmit
next_state = HEAD_RCV;
else if(eop && ~(o_axis_master_trdy && axis_master_tvld))//transmit end
next_state = IDLE;
else
next_state = state;
end
default:
begin
next_state = IDLE;
end
endcase
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
//comon header
tlp_length <= 10'b0;
//mrd
o_mrd_tc <= 3'b0;
o_mrd_attr <= 3'b0;
o_mrd_id <= 16'b0;
o_mrd_tag <= 8'b0;
o_mrd_addr <= 64'b0;
//mwr
o_mwr_wr_start <= 1'b0;
o_mwr_dwbe <= 8'b0;
o_mwr_data <= 128'b0;
o_mwr_dw_vld <= 4'b0;
o_mwr_addr <= 64'b0;
//cpld
o_cpld_wr_start <= 1'b0;
o_cpld_low_addr <= 7'b0;
o_cpld_byte_cnt <= 12'b0;
o_cpld_data <= 128'b0;
o_cpld_dw_vld <= 4'b0;
o_cpld_tag <= 8'b0;
o_bar_hit <= 2'b0;
o_multicpld_flag <= 1'b0;
end
else
begin
case(state)
IDLE:
begin
tlp_length <= 10'b0;
//mrd
o_mrd_tc <= 3'b0;
o_mrd_attr <= 3'b0;
o_mrd_id <= 16'b0;
o_mrd_tag <= 8'b0;
o_mrd_addr <= 64'b0;
//mwr
o_mwr_wr_start <= 1'b0;
o_mwr_dwbe <= 8'b0;
o_mwr_data <= 128'b0;
o_mwr_dw_vld <= 4'b0;
o_mwr_addr <= 64'b0;
//cpld
o_cpld_wr_start <= 1'b0;
o_cpld_low_addr <= 7'b0;
o_cpld_byte_cnt <= 12'b0;
o_cpld_data <= 128'b0;
o_cpld_dw_vld <= 4'b0;
o_cpld_tag <= 8'b0;
o_bar_hit <= 2'b0;
o_multicpld_flag <= 1'b0;
end
HEAD_RCV:
begin
//length
tlp_length <= axis_master_tdata_ff[9:0];
if(mrd_rcv)
begin
o_mrd_tc <= axis_master_tdata_ff[22:20];
o_mrd_attr <= {axis_master_tdata_ff[18],axis_master_tdata_ff[13:12]};
o_mrd_id <= axis_master_tdata_ff[63:48];
o_mrd_tag <= axis_master_tdata_ff[47:40];
//address
if (mrd32_rcv)
o_mrd_addr <= {32'b0,axis_master_tdata_ff[95:66],2'b0};
else if(mrd64_rcv)
o_mrd_addr <= {axis_master_tdata_ff[95:64],axis_master_tdata_ff[127:98],2'b0};
end
else if (mwr_rcv)
begin
o_mwr_wr_start <= 1'b0;
o_mwr_dwbe <= axis_master_tdata_ff[39:32];
//address
if (mwr32_rcv)
o_mwr_addr <= {32'b0,axis_master_tdata_ff[95:66],2'b0};
else if(mwr64_rcv)
o_mwr_addr <= {axis_master_tdata_ff[95:64],axis_master_tdata_ff[127:98],2'b0};
end
else if (cpld_rcv)
begin
o_cpld_wr_start <= 1'b0;
o_cpld_byte_cnt <= axis_master_tdata_ff[41:32];
o_cpld_low_addr <= axis_master_tdata_ff[70:64];
o_cpld_tag <= axis_master_tdata_ff[79:72];
o_multicpld_flag <= ~axis_master_tuser_ff[3];
end
end
DATA_RCV:
begin
o_bar_hit <= axis_master_tuser_ff[5:4];
if(mwr_data_valid)
begin
o_mwr_wr_start <= 1'b1;
o_mwr_data <= axis_rx_data;
o_mwr_dw_vld <= axis_master_tkeep_ff;
end
else if(cpld_data_valid)
begin
o_cpld_wr_start <= 1'b1;
o_cpld_data <= axis_rx_data;
o_cpld_dw_vld <= axis_master_tkeep_ff;
end
end
default:
begin
tlp_length <= 10'b0;
//mrd
o_mrd_tc <= 3'b0;
o_mrd_attr <= 3'b0;
o_mrd_id <= 16'b0;
o_mrd_tag <= 8'b0;
o_mrd_addr <= 64'b0;
//mwr
o_mwr_wr_start <= 1'b0;
o_mwr_dwbe <= 8'b0;
o_mwr_data <= 128'b0;
o_mwr_dw_vld <= 4'b0;
o_mwr_addr <= 64'b0;
//cpld
o_cpld_wr_start <= 1'b0;
o_cpld_low_addr <= 7'b0;
o_cpld_byte_cnt <= 12'b0;
o_cpld_data <= 128'b0;
o_cpld_dw_vld <= 4'b0;
o_cpld_tag <= 8'b0;
o_bar_hit <= 2'b0;
o_multicpld_flag <= 1'b0;
end
endcase
end
end
assign o_mwr_length = tlp_length;
assign o_mrd_length = tlp_length;
assign o_cpld_length = tlp_length;
//rcv mrd:cpld req
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_cpld_req_vld <= 1'b0;
else if((state == HEAD_RCV) && mrd_rcv)
o_cpld_req_vld <= 1'b1;
else if(i_cpld_req_rdy)
o_cpld_req_vld <= 1'b0;
end
//rcv cpld:release cpld tag
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_cpld_rcv <= 1'b0;
else if((state == HEAD_RCV) && cpld_rcv && axis_master_tuser_ff[3]) //for multicpld,i_axis_master_tuser[3]:Indicates the last completion TLP
o_cpld_rcv <= 1'b1;
else
o_cpld_rcv <= 1'b0;
end
//o_trgt1_radm_pkt_halt[0]:Halt posted TLPs for VC0,MWR
//o_trgt1_radm_pkt_halt[1]:Halt non-posted TLPs for VC0,MRD
//o_trgt1_radm_pkt_halt[2]:Halt CPL TLPs for VC0,CPLD
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_trgt1_radm_pkt_halt <= 3'b0;
else
o_trgt1_radm_pkt_halt <= {1'b0,~i_cpld_tx_rdy,i_tag_full};
end
//******************************************************************debug logic*************************************************************************
//check for 128byte only
reg [2:0] tlp_data_cnt;
reg [13:0] tlp_rx_check_pass_cnt;
reg [13:0] tlp_rx_check_error_cnt;
reg [13:0] tlp_rx_sum;
reg [13:0] multcpld_cnt;
wire tlp_rx_vld;
reg check_error_flag;
//rcv tlp cnt
reg [13:0] mwr_rcv_cnt;
reg [13:0] mrd_rcv_cnt;
reg [13:0] cpld_rcv_cnt;
//wire [41:0] o_dbg_tlp_rcv_cnt;
assign tlp_rx_vld = axis_master_tvld_ff && o_axis_master_trdy;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tlp_data_cnt <= 3'b0;
else if(axis_master_tlast_ff)
tlp_data_cnt <= 3'b0;
else if(cpld_data_valid && tlp_rx_vld)
tlp_data_cnt <= tlp_data_cnt + 3'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tlp_rx_sum <= 14'b0;
else if(i_tx_restart)
tlp_rx_sum <= 14'b0;
else if(axis_master_tlast_ff && tlp_rx_vld)
tlp_rx_sum <= tlp_rx_sum + 14'b1;
end
//rcv tlp cnt
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mwr_rcv_cnt <= 14'b0;
else if(i_tx_restart)
mwr_rcv_cnt <= 14'b0;
else if(mwr_rcv)
mwr_rcv_cnt <= mwr_rcv_cnt + 14'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mrd_rcv_cnt <= 14'b0;
else if(i_tx_restart)
mrd_rcv_cnt <= 14'b0;
else if(mrd_rcv)
mrd_rcv_cnt <= mrd_rcv_cnt + 14'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cpld_rcv_cnt <= 14'b0;
else if(i_tx_restart)
cpld_rcv_cnt <= 14'b0;
else if(cpld_rcv)
cpld_rcv_cnt <= cpld_rcv_cnt + 14'b1;
end
//assign o_dbg_tlp_rcv_cnt = {
// mwr_rcv_cnt, //41:28
// mrd_rcv_cnt, //27:14
// cpld_rcv_cnt //13:0
// };
//check multicpld,i_axis_master_tuser[3]
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
multcpld_cnt <= 14'b0;
else if(i_tx_restart)
multcpld_cnt <= 14'b0;
else if(cpld_data_valid && axis_master_tlast_ff && ~axis_master_tuser_ff[3])
multcpld_cnt <= multcpld_cnt + 14'b1;
end
//******************************************************************check logic*************************************************************************
//DMA check
//note:
//1.mrd addr must equal to mwr addr
//2.addr must 4dw aligned
//3.only for DMA test
//otherwise the check logic will not work properly
generate
if (DEVICE_TYPE == 3'd4)
begin
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dma_check_cnt <= 12'b0;
else if(mwr_rcv)
dma_check_cnt <= {axis_master_tdata_ff[79:68]};
else if(mwr_data_valid)
dma_check_cnt <= dma_check_cnt + 12'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_cnt <= 6'b0;
else if(mrd_rcv)
data_cnt <= 6'd0;
else if(mwr_data_valid)
data_cnt <= data_cnt + 6'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_dma_check_result <= 64'b0;
else if(mrd_rcv)
o_dma_check_result <= 64'b0;
else if(mwr_data_valid)
o_dma_check_result[data_cnt] <= ~(dma_check_cnt == axis_rx_data[11:0]);
end
end
else
begin
always@(*)
begin
o_dma_check_result = 64'b0;
end
end
endgenerate
assign axis_rx_data = endian_convert(axis_master_tdata_ff);
//convert from little endian into big endian
function [127:0] endian_convert;
input [127:0] data_in;
begin
endian_convert[32*0+31:32*0+0] = {data_in[32*0+7:32*0+0], data_in[32*0+15:32*0+8], data_in[32*0+23:32*0+16], data_in[32*0+31:32*0+24]};
endian_convert[32*1+31:32*1+0] = {data_in[32*1+7:32*1+0], data_in[32*1+15:32*1+8], data_in[32*1+23:32*1+16], data_in[32*1+31:32*1+24]};
endian_convert[32*2+31:32*2+0] = {data_in[32*2+7:32*2+0], data_in[32*2+15:32*2+8], data_in[32*2+23:32*2+16], data_in[32*2+31:32*2+24]};
endian_convert[32*3+31:32*3+0] = {data_in[32*3+7:32*3+0], data_in[32*3+15:32*3+8], data_in[32*3+23:32*3+16], data_in[32*3+31:32*3+24]};
end
endfunction
endmodule |
module ipsl_pcie_dma_wr_ctrl #(
parameter ADDR_WIDTH = 4'd9
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
//**********************************************************************
input i_wr_start ,
input [9:0] i_length ,
input [7:0] i_dwbe ,
input [127:0] i_data ,
input [3:0] i_dw_vld ,
input [63:0] i_addr ,
input [1:0] i_bar_hit ,
//**********************************************************************
//ram write control
output reg o_wr_en ,
output reg [ADDR_WIDTH-1:0] o_wr_addr ,
output reg [127:0] o_wr_data ,
output reg [15:0] o_wr_be ,
output reg [1:0] o_wr_bar_hit
);
reg wr_start_ff;
wire rx_start;
wire first_dw;
reg first_dw_ff;
wire last_dw;
reg [9:0] length;
reg [3:0] dw_vld;
reg [7:0] dwbe;
reg [15:0] byte_en;
reg [15:0] byte_en_ff;
wire [31:0] byte_en_shift;
reg [15:0] dw_vld_shift_out;
reg [3:0] last_dw_position;
wire [15:0] last_data_be;
reg [1:0] data_position;
reg [127:0] data_ff;
reg [127:0] data_ff2;
wire [255:0] data_shift;
reg [127:0] data_shift_out;
reg [8:0] wr_dw_cnt;
reg [8:0] wr_dw_cnt_ff;
reg [63:0] wr_addr;
wire wr_start;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
wr_start_ff <= 1'b0;
else
wr_start_ff <= i_wr_start;
end
assign rx_start = i_wr_start & ~wr_start_ff;
//**********************************************************************gen byte enbale from dwbe and dw_vld***************************************************************************
assign last_dw = ~i_wr_start & wr_start_ff;
assign first_dw = rx_start;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
first_dw_ff <= 1'b0;
else
first_dw_ff <= first_dw;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
length <= 10'b0;
else if(rx_start)
length <= i_length;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dw_vld <= 4'b0;
else
dw_vld <= i_dw_vld;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dwbe <= 8'b0;
else if(rx_start)
dwbe <= i_dwbe;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
last_dw_position <= 4'b0;
else if(rx_start)
case(i_length[1:0])
2'd0: last_dw_position <= 4'b1000;
2'd1: last_dw_position <= 4'b0001;
2'd2: last_dw_position <= 4'b0010;
2'd3: last_dw_position <= 4'b0100;
default: last_dw_position <= 4'b0000;
endcase
end
assign last_data_be[4*0+3:4*0] = last_dw_position[0] ? (dwbe[7:4] & {4{dw_vld[0]}}) : {4{dw_vld[0]}};
assign last_data_be[4*1+3:4*1] = last_dw_position[1] ? (dwbe[7:4] & {4{dw_vld[1]}}) : {4{dw_vld[1]}};
assign last_data_be[4*2+3:4*2] = last_dw_position[2] ? (dwbe[7:4] & {4{dw_vld[2]}}) : {4{dw_vld[2]}};
assign last_data_be[4*3+3:4*3] = last_dw_position[3] ? (dwbe[7:4] & {4{dw_vld[3]}}) : {4{dw_vld[3]}};
//gen byte_en
always@(*)
begin
if(wr_start_ff)
begin
if(length == 10'b1)
byte_en = {12'b0,dwbe[3:0]};
else
begin
byte_en[4*0+3:4*0] = first_dw_ff ? dwbe[3:0] : (last_dw ? last_data_be[4*0+3:4*0] : {4{dw_vld[0]}});
byte_en[4*1+3:4*1] = last_dw ? last_data_be[4*1+3:4*1] : {4{dw_vld[1]}};
byte_en[4*2+3:4*2] = last_dw ? last_data_be[4*2+3:4*2] : {4{dw_vld[2]}};
byte_en[4*3+3:4*3] = last_dw ? last_data_be[4*3+3:4*3] : {4{dw_vld[3]}};
end
end
else
byte_en = 16'b0;
end
//**********************************************************************data shift***************************************************************************
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_position <= 2'b0;
else if(rx_start)
data_position <= i_addr[3:2];
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
data_ff <= 128'b0;
data_ff2 <= 128'b0;
end
else
begin
data_ff <= i_data;
data_ff2 <= data_ff;
end
end
//data shift
assign data_shift = {data_ff,data_ff2};
always@(*)
begin
case(data_position)
2'd0: data_shift_out = data_shift[32*8-1:32*4];
2'd1: data_shift_out = data_shift[32*7-1:32*3];
2'd2: data_shift_out = data_shift[32*6-1:32*2];
2'd3: data_shift_out = data_shift[32*5-1:32*1];
default: data_shift_out = 128'b0;
endcase
end
//**********************************************************************byte_en shift***************************************************************************
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
byte_en_ff <= 16'b0;
else
byte_en_ff <= byte_en;
end
//dw_vld shift
assign byte_en_shift[31:0] = {byte_en,byte_en_ff};
always@(*)
begin
case(data_position)
2'd0: dw_vld_shift_out = byte_en_shift[4*8-1:4*4];
2'd1: dw_vld_shift_out = byte_en_shift[4*7-1:4*3];
2'd2: dw_vld_shift_out = byte_en_shift[4*6-1:4*2];
2'd3: dw_vld_shift_out = byte_en_shift[4*5-1:4*1];
default: dw_vld_shift_out = 16'b0;
endcase
end
//**********************************************************************gen bar write ctrl***************************************************************************
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
wr_dw_cnt <= 9'b0;
else if(rx_start)
wr_dw_cnt <= i_length[8:0] + {7'b0,i_addr[3:2]};
else if(wr_dw_cnt > 9'd4)
wr_dw_cnt <= wr_dw_cnt -9'd4;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
wr_dw_cnt_ff <= 9'b0;
else
wr_dw_cnt_ff <= wr_dw_cnt;
end
assign wr_start = first_dw_ff;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_wr_en <= 1'b0;
else if(wr_start)
o_wr_en <= 1'b1;
else if(wr_dw_cnt_ff <= 4)
o_wr_en <= 1'b0;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
wr_addr <= 64'b0;
else if(rx_start)
wr_addr <= i_addr;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_wr_bar_hit <= 2'b0;
else if(rx_start)
o_wr_bar_hit <= i_bar_hit;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_wr_addr <= {ADDR_WIDTH{1'b0}};
else if(wr_start)
o_wr_addr <= wr_addr[ADDR_WIDTH+3:4];
else if(o_wr_en)
o_wr_addr <= o_wr_addr + {{(ADDR_WIDTH-1){1'b0}},1'b1};
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_wr_data <= 128'b0;
else
o_wr_data <= data_shift_out;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_wr_be <= 16'b0;
else
o_wr_be <= dw_vld_shift_out;
end
endmodule |
module ipsl_pcie_dma #(
parameter DEVICE_TYPE = 3'd0 , //3'd0:EP,3'd1:Legacy EP,3'd4:RC
parameter integer AXIS_SLAVE_NUM = 3 ,
parameter ADDR_WIDTH = 4'd12
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
input [7:0] i_cfg_pbus_num ,
input [4:0] i_cfg_pbus_dev_num ,
input [2:0] i_cfg_max_rd_req_size ,
input [2:0] i_cfg_max_payload_size ,
//**********************************************************************
//axis master interface
input i_axis_master_tvld ,
output wire o_axis_master_trdy ,
input [127:0] i_axis_master_tdata ,
input [3:0] i_axis_master_tkeep ,
input i_axis_master_tlast ,
input [7:0] i_axis_master_tuser ,
output wire [2:0] o_trgt1_radm_pkt_halt ,
// input [5:0] i_radm_grant_tlp_type ,
//**********************************************************************
//axis_slave0 interface
input i_axis_slave0_trdy ,
output wire o_axis_slave0_tvld ,
output wire [127:0] o_axis_slave0_tdata ,
output wire o_axis_slave0_tlast ,
output wire o_axis_slave0_tuser ,
//axis_slave1 interface
input i_axis_slave1_trdy ,
output wire o_axis_slave1_tvld ,
output wire [127:0] o_axis_slave1_tdata ,
output wire o_axis_slave1_tlast ,
output wire o_axis_slave1_tuser ,
//axis_slave2 interface
input i_axis_slave2_trdy ,
output wire o_axis_slave2_tvld ,
output wire [127:0] o_axis_slave2_tdata ,
output wire o_axis_slave2_tlast ,
output wire o_axis_slave2_tuser ,
//**********************************************************************
//credit interface
//from pcie
input i_cfg_ido_req_en ,
input i_cfg_ido_cpl_en ,
input [7:0] i_xadm_ph_cdts ,
input [11:0] i_xadm_pd_cdts ,
input [7:0] i_xadm_nph_cdts ,
input [11:0] i_xadm_npd_cdts ,
input [7:0] i_xadm_cplh_cdts ,
input [11:0] i_xadm_cpld_cdts ,
//**********************************************************************
//apb interface
input i_apb_psel ,
input [8:0] i_apb_paddr ,
input [31:0] i_apb_pwdata ,
input [3:0] i_apb_pstrb ,
input i_apb_pwrite ,
input i_apb_penable ,
output wire o_apb_prdy ,
output wire [31:0] o_apb_prdata ,
//cross_4kb_boundary
output wire o_cross_4kb_boundary
//debug
//output wire [159:0] o_dbg_bus
);
//**********************************************************************
//from rx to tx
wire [2:0] mrd_tc;
wire [2:0] mrd_attr;
wire [9:0] mrd_length;
wire [15:0] mrd_id;
wire [7:0] mrd_tag;
wire [63:0] mrd_addr;
wire cpld_req_vld;
wire cpld_req_rdy;
wire cpld_tx_rdy;
//cpld rcv
wire cpld_rcv;
wire [7:0] cpld_tag;
wire tag_full;
//from dma_controller to tx
wire user_define_header_flag;
wire user_define_data_flag;
//mwr req & ack
wire mwr32_req;
wire mwr32_req_ack;
wire mwr64_req;
wire mwr64_req_ack;
//mrd req & ack
wire mrd32_req;
wire mrd32_req_ack;
wire mrd64_req;
wire mrd64_req_ack;
//req information
wire [9:0] req_length;
wire [63:0] req_addr;
wire [31:0] req_data;
//axis_slave0 interface
wire dma_axis_slave0_trdy ;
wire dma_axis_slave0_tvld ;
wire [127:0] dma_axis_slave0_tdata;
wire dma_axis_slave0_tlast;
wire dma_axis_slave0_tuser;
//axis_slave1 interface
wire dma_axis_slave1_trdy ;
wire dma_axis_slave1_tvld ;
wire [127:0] dma_axis_slave1_tdata;
wire dma_axis_slave1_tlast;
wire dma_axis_slave1_tuser;
//axis_slave2 interface
wire dma_axis_slave2_trdy ;
wire dma_axis_slave2_tvld ;
wire [127:0] dma_axis_slave2_tdata;
wire dma_axis_slave2_tlast;
wire dma_axis_slave2_tuser;
//**********************************************************************
//bar0 rd interface
wire bar0_rd_clk_en;
wire [ADDR_WIDTH-1:0] bar0_rd_addr;
wire [127:0] bar0_rd_data;
//bar1 wr interface
wire bar1_wr_en;
wire [ADDR_WIDTH-1:0] bar1_wr_addr;
wire [127:0] bar1_wr_data;
wire [15:0] bar1_wr_byte_en;
//bar2 rd interface
wire bar2_rd_clk_en;
wire [ADDR_WIDTH-1:0] bar2_rd_addr;
wire [127:0] bar2_rd_data;
//**********************************************************************
//rst tlp cnt
wire tx_restart;
wire [63:0] dma_check_result;
//debug bus
//wire [42:0] dbg_bus_rx_ctrl;
//wire [43:0] dbg_bus_mrd_tx;
//wire [72:0] dbg_bus_mwr_tx;
//assign o_dbg_bus = {
// dbg_bus_mwr_tx, //159:87
// dbg_bus_mrd_tx, //86:43
// dbg_bus_rx_ctrl //42:0
// };
wire [7:0] cfg_pbus_num;
wire [4:0] cfg_pbus_dev_num;
wire [2:0] cfg_max_rd_req_size;
wire [2:0] cfg_max_payload_size;
ipsl_pcie_reg #(
.SIG_WIDTH (4'd8 )
)
u_cfg_pbus_num_reg
(
.clk (clk ),
.sig (i_cfg_pbus_num ),
.sig_reg (cfg_pbus_num )
);
ipsl_pcie_reg #(
.SIG_WIDTH (3'd5 )
)
u_cfg_pbus_dev_num_reg
(
.clk (clk ),
.sig (i_cfg_pbus_dev_num ),
.sig_reg (cfg_pbus_dev_num )
);
ipsl_pcie_reg #(
.SIG_WIDTH (2'd3 )
)
u_max_rd_req_size_reg
(
.clk (clk ),
.sig (i_cfg_max_rd_req_size ),
.sig_reg (cfg_max_rd_req_size )
);
ipsl_pcie_reg #(
.SIG_WIDTH (2'd3 )
)
u_max_payload_size_reg
(
.clk (clk ),
.sig (i_cfg_max_payload_size ),
.sig_reg (cfg_max_payload_size )
);
ipsl_pcie_dma_rx_top #(
.DEVICE_TYPE (DEVICE_TYPE ), //3'd0:EP,3'd1:Legacy EP,3'd4:RC
.ADDR_WIDTH (ADDR_WIDTH )
)
u_ipsl_pcie_dma_rx_top
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
.i_cfg_max_rd_req_size (cfg_max_rd_req_size ), //input [2:0]
//**********************************************************************
//axis master interface
.i_axis_master_tvld (i_axis_master_tvld ),
.o_axis_master_trdy (o_axis_master_trdy ),
.i_axis_master_tdata (i_axis_master_tdata ),
.i_axis_master_tkeep (i_axis_master_tkeep ),
.i_axis_master_tlast (i_axis_master_tlast ),
.i_axis_master_tuser (i_axis_master_tuser ),
.o_trgt1_radm_pkt_halt (o_trgt1_radm_pkt_halt ),
// .i_radm_grant_tlp_type (i_radm_grant_tlp_type ),
//**********************************************************************
//bar0 rd interface
.i_bar0_rd_clk_en (bar0_rd_clk_en ),
.i_bar0_rd_addr (bar0_rd_addr ),
.o_bar0_rd_data (bar0_rd_data ),
//bar2 rd interface
.i_bar2_rd_clk_en (bar2_rd_clk_en ),
.i_bar2_rd_addr (bar2_rd_addr ),
.o_bar2_rd_data (bar2_rd_data ),
//bar1 wr interface
.o_bar1_wr_en (bar1_wr_en ),
.o_bar1_wr_addr (bar1_wr_addr ),
.o_bar1_wr_data (bar1_wr_data ),
.o_bar1_wr_byte_en (bar1_wr_byte_en ),
//**********************************************************************
//to tx top
//req rcv
.o_mrd_tc (mrd_tc ),
.o_mrd_attr (mrd_attr ),
.o_mrd_length (mrd_length ),
.o_mrd_id (mrd_id ),
.o_mrd_tag (mrd_tag ),
.o_mrd_addr (mrd_addr ),
.o_cpld_req_vld (cpld_req_vld ),
.i_cpld_req_rdy (cpld_req_rdy ),
.i_cpld_tx_rdy (cpld_tx_rdy ),
//cpld rcv
.o_cpld_rcv (cpld_rcv ),
.o_cpld_tag (cpld_tag ),
.i_tag_full (tag_full ),
//rst tlp cnt
.o_dma_check_result (dma_check_result ),
.i_tx_restart (tx_restart )
//.o_dbg_bus_rx_ctrl (dbg_bus_rx_ctrl )
);
ipsl_pcie_dma_controller #(
.DEVICE_TYPE (DEVICE_TYPE ), //3'd0:EP,3'd1:Legacy EP,3'd4:RC
.ADDR_WIDTH (ADDR_WIDTH )
)
u_ipsl_pcie_dma_controller
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
//bar1 wr interface
.i_bar1_wr_en (bar1_wr_en ),
.i_bar1_wr_addr (bar1_wr_addr ),
.i_bar1_wr_data (bar1_wr_data ),
.i_bar1_wr_byte_en (bar1_wr_byte_en ),
//**********************************************************************
//apb interface
.i_apb_psel (i_apb_psel ),
.i_apb_paddr (i_apb_paddr ),
.i_apb_pwdata (i_apb_pwdata ),
.i_apb_pstrb (i_apb_pstrb ),
.i_apb_pwrite (i_apb_pwrite ),
.i_apb_penable (i_apb_penable ),
.o_apb_prdy (o_apb_prdy ),
.o_apb_prdata (o_apb_prdata ),
//**********************************************************************
.o_user_define_data_flag (user_define_data_flag ),
//**********************************************************************
//to tx top
//mwr req & ack
.o_mwr32_req (mwr32_req ),
.i_mwr32_req_ack (mwr32_req_ack ),
.o_mwr64_req (mwr64_req ),
.i_mwr64_req_ack (mwr64_req_ack ),
//mrd req & ack
.o_mrd32_req (mrd32_req ),
.i_mrd32_req_ack (mrd32_req_ack ),
.o_mrd64_req (mrd64_req ),
.i_mrd64_req_ack (mrd64_req_ack ),
//req information
.o_req_length (req_length ),
.o_req_addr (req_addr ),
.o_req_data (req_data ),
.o_cross_4kb_boundary (o_cross_4kb_boundary ),
//rst tlp cnt
.i_dma_check_result (dma_check_result ),
.o_tx_restart (tx_restart )
);
ipsl_pcie_dma_tx_top #(
// .DEVICE_TYPE (DEVICE_TYPE ), //3'd0:EP,3'd1:Legacy EP,3'd4:RC
.ADDR_WIDTH (ADDR_WIDTH )
)
u_ipsl_pcie_dma_tx_top
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
.i_cfg_pbus_num (cfg_pbus_num ), //input [7:0]
.i_cfg_pbus_dev_num (cfg_pbus_dev_num ), //input [4:0]
.i_cfg_max_rd_req_size (cfg_max_rd_req_size ), //input [2:0]
.i_cfg_max_payload_size (cfg_max_payload_size ), //input [2:0]
//**********************************************************************
//axis_slave0 interface
.i_axis_slave0_trdy (dma_axis_slave0_trdy ),
.o_axis_slave0_tvld (dma_axis_slave0_tvld ),
.o_axis_slave0_tdata (dma_axis_slave0_tdata ),
.o_axis_slave0_tlast (dma_axis_slave0_tlast ),
.o_axis_slave0_tuser (dma_axis_slave0_tuser ),
//axis_slave1 interface
.i_axis_slave1_trdy (dma_axis_slave1_trdy ),
.o_axis_slave1_tvld (dma_axis_slave1_tvld ),
.o_axis_slave1_tdata (dma_axis_slave1_tdata ),
.o_axis_slave1_tlast (dma_axis_slave1_tlast ),
.o_axis_slave1_tuser (dma_axis_slave1_tuser ),
//axis_slave2 interface
.i_axis_slave2_trdy (dma_axis_slave2_trdy ),
.o_axis_slave2_tvld (dma_axis_slave2_tvld ),
.o_axis_slave2_tdata (dma_axis_slave2_tdata ),
.o_axis_slave2_tlast (dma_axis_slave2_tlast ),
.o_axis_slave2_tuser (dma_axis_slave2_tuser ),
//**********************************************************************
//from dma_controller
.i_user_define_data_flag (user_define_data_flag ),
.i_mwr32_req (mwr32_req ),
.o_mwr32_req_ack (mwr32_req_ack ),
.i_mwr64_req (mwr64_req ),
.o_mwr64_req_ack (mwr64_req_ack ),
.i_mrd32_req (mrd32_req ),
.o_mrd32_req_ack (mrd32_req_ack ),
.i_mrd64_req (mrd64_req ),
.o_mrd64_req_ack (mrd64_req_ack ),
.i_req_length (req_length ),
.i_req_addr (req_addr ),
.i_req_data (req_data ),
//**********************************************************************
//bar0 rd interface
.o_bar0_rd_clk_en (bar0_rd_clk_en ),
.o_bar0_rd_addr (bar0_rd_addr ),
.i_bar0_rd_data (bar0_rd_data ),
//bar2 rd interface
.o_bar2_rd_clk_en (bar2_rd_clk_en ),
.o_bar2_rd_addr (bar2_rd_addr ),
.i_bar2_rd_data (bar2_rd_data ),
//**********************************************************************
//from rx top
//req rcv
.i_mrd_tc (mrd_tc ),
.i_mrd_attr (mrd_attr ),
.i_mrd_length (mrd_length ),
.i_mrd_id (mrd_id ),
.i_mrd_tag (mrd_tag ),
.i_mrd_addr (mrd_addr ),
.i_cpld_req_vld (cpld_req_vld ),
.o_cpld_req_rdy (cpld_req_rdy ),
.o_cpld_tx_rdy (cpld_tx_rdy ),
//cpld rcv
.i_cpld_rcv (cpld_rcv ),
.i_cpld_tag (cpld_tag ),
.o_tag_full (tag_full ),
//rst tlp cnt
.i_tx_restart (tx_restart )
//debug
//.o_dbg_bus_mrd_tx (dbg_bus_mrd_tx ),
//.o_dbg_bus_mwr_tx (dbg_bus_mwr_tx )
);
generate
if (AXIS_SLAVE_NUM == 1)
begin:axis_slave_num_1
ipsl_pcie_dma_tlp_tx_mux #(
.AXIS_SLAVE_NUM (AXIS_SLAVE_NUM )
)
u_pcie_dma_tlp_tx_mux
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
//from dma
//axis_slave0 interface
.o_dma_axis_slave0_trdy (dma_axis_slave0_trdy ),
.i_dma_axis_slave0_tvld (dma_axis_slave0_tvld ),
.i_dma_axis_slave0_tdata (dma_axis_slave0_tdata ),
.i_dma_axis_slave0_tlast (dma_axis_slave0_tlast ),
.i_dma_axis_slave0_tuser (dma_axis_slave0_tuser ),
//axis_slave1 interface
.o_dma_axis_slave1_trdy (dma_axis_slave1_trdy ),
.i_dma_axis_slave1_tvld (dma_axis_slave1_tvld ),
.i_dma_axis_slave1_tdata (dma_axis_slave1_tdata ),
.i_dma_axis_slave1_tlast (dma_axis_slave1_tlast ),
.i_dma_axis_slave1_tuser (dma_axis_slave1_tuser ),
//axis_slave2 interface
.o_dma_axis_slave2_trdy (dma_axis_slave2_trdy ),
.i_dma_axis_slave2_tvld (dma_axis_slave2_tvld ),
.i_dma_axis_slave2_tdata (dma_axis_slave2_tdata ),
.i_dma_axis_slave2_tlast (dma_axis_slave2_tlast ),
.i_dma_axis_slave2_tuser (dma_axis_slave2_tuser ),
//credit interface
//from pcie
.i_cfg_ido_req_en (i_cfg_ido_req_en ),
.i_cfg_ido_cpl_en (i_cfg_ido_cpl_en ),
.i_xadm_ph_cdts (i_xadm_ph_cdts ),
.i_xadm_pd_cdts (i_xadm_pd_cdts ),
.i_xadm_nph_cdts (i_xadm_nph_cdts ),
.i_xadm_npd_cdts (i_xadm_npd_cdts ),
.i_xadm_cplh_cdts (i_xadm_cplh_cdts ),
.i_xadm_cpld_cdts (i_xadm_cpld_cdts ),
//pcie_axis_slave0
.i_pcie_axis_slave_trdy (i_axis_slave0_trdy ),
.o_pcie_axis_slave_tvld (o_axis_slave0_tvld ),
.o_pcie_axis_slave_tdata (o_axis_slave0_tdata ),
.o_pcie_axis_slave_tlast (o_axis_slave0_tlast ),
.o_pcie_axis_slave_tuser (o_axis_slave0_tuser )
);
assign o_axis_slave1_tvld = 1'b0;
assign o_axis_slave1_tdata = 128'b0;
assign o_axis_slave1_tlast = 1'b0;
assign o_axis_slave1_tuser = 1'b0;
assign o_axis_slave2_tvld = 1'b0;
assign o_axis_slave2_tdata = 128'b0;
assign o_axis_slave2_tlast = 1'b0;
assign o_axis_slave2_tuser = 1'b0;
end
else if (AXIS_SLAVE_NUM == 2)
begin:axis_slave_num_2
ipsl_pcie_dma_tlp_tx_mux #(
.AXIS_SLAVE_NUM (AXIS_SLAVE_NUM )
)
u_pcie_dma_tlp_tx_mux
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
//from dma
//axis_slave0 interface
.o_dma_axis_slave0_trdy ( ),
.i_dma_axis_slave0_tvld (1'b0 ),
.i_dma_axis_slave0_tdata (128'b0 ),
.i_dma_axis_slave0_tlast (1'b0 ),
.i_dma_axis_slave0_tuser (1'b0 ),
//axis_slave1 interface
.o_dma_axis_slave1_trdy (dma_axis_slave1_trdy ),
.i_dma_axis_slave1_tvld (dma_axis_slave1_tvld ),
.i_dma_axis_slave1_tdata (dma_axis_slave1_tdata ),
.i_dma_axis_slave1_tlast (dma_axis_slave1_tlast ),
.i_dma_axis_slave1_tuser (dma_axis_slave1_tuser ),
//axis_slave2 interface
.o_dma_axis_slave2_trdy (dma_axis_slave2_trdy ),
.i_dma_axis_slave2_tvld (dma_axis_slave2_tvld ),
.i_dma_axis_slave2_tdata (dma_axis_slave2_tdata ),
.i_dma_axis_slave2_tlast (dma_axis_slave2_tlast ),
.i_dma_axis_slave2_tuser (dma_axis_slave2_tuser ),
//credit interface
//from pcie
.i_cfg_ido_req_en (i_cfg_ido_req_en ),
.i_cfg_ido_cpl_en (i_cfg_ido_cpl_en ),
.i_xadm_ph_cdts (i_xadm_ph_cdts ),
.i_xadm_pd_cdts (i_xadm_pd_cdts ),
.i_xadm_nph_cdts (i_xadm_nph_cdts ),
.i_xadm_npd_cdts (i_xadm_npd_cdts ),
.i_xadm_cplh_cdts (i_xadm_cplh_cdts ),
.i_xadm_cpld_cdts (i_xadm_cpld_cdts ),
//pcie_axis_slave0
.i_pcie_axis_slave_trdy (i_axis_slave1_trdy ),
.o_pcie_axis_slave_tvld (o_axis_slave1_tvld ),
.o_pcie_axis_slave_tdata (o_axis_slave1_tdata ),
.o_pcie_axis_slave_tlast (o_axis_slave1_tlast ),
.o_pcie_axis_slave_tuser (o_axis_slave1_tuser )
);
assign dma_axis_slave0_trdy = i_axis_slave0_trdy ;
assign o_axis_slave0_tvld = dma_axis_slave0_tvld ;
assign o_axis_slave0_tdata = dma_axis_slave0_tdata ;
assign o_axis_slave0_tlast = dma_axis_slave0_tlast ;
assign o_axis_slave0_tuser = dma_axis_slave0_tuser ;
assign o_axis_slave2_tvld = 1'b0;
assign o_axis_slave2_tdata = 128'b0;
assign o_axis_slave2_tlast = 1'b0;
assign o_axis_slave2_tuser = 1'b0;
end
else if (AXIS_SLAVE_NUM == 3)
begin:axis_slave_num_3
assign dma_axis_slave0_trdy = i_axis_slave0_trdy ;
assign o_axis_slave0_tvld = dma_axis_slave0_tvld ;
assign o_axis_slave0_tdata = dma_axis_slave0_tdata ;
assign o_axis_slave0_tlast = dma_axis_slave0_tlast ;
assign o_axis_slave0_tuser = dma_axis_slave0_tuser ;
assign dma_axis_slave1_trdy = i_axis_slave1_trdy ;
assign o_axis_slave1_tvld = dma_axis_slave1_tvld ;
assign o_axis_slave1_tdata = dma_axis_slave1_tdata ;
assign o_axis_slave1_tlast = dma_axis_slave1_tlast ;
assign o_axis_slave1_tuser = dma_axis_slave1_tuser ;
assign dma_axis_slave2_trdy = i_axis_slave2_trdy ;
assign o_axis_slave2_tvld = dma_axis_slave2_tvld ;
assign o_axis_slave2_tdata = dma_axis_slave2_tdata ;
assign o_axis_slave2_tlast = dma_axis_slave2_tlast ;
assign o_axis_slave2_tuser = dma_axis_slave2_tuser ;
end
endgenerate
endmodule |
module ipsl_pcie_dma_cpld_tx_ctrl (
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
input [7:0] i_cfg_pbus_num ,
input [4:0] i_cfg_pbus_dev_num ,
input [2:0] i_cfg_max_payload_size ,
//**********************************************************************
//from rx
input [2:0] i_mrd_tc ,
input [2:0] i_mrd_attr ,
input [9:0] i_mrd_length ,
input [15:0] i_mrd_id ,
input [7:0] i_mrd_tag ,
input [63:0] i_mrd_addr ,
input i_cpld_req_vld ,
output wire o_cpld_req_rdy ,
output wire o_cpld_tx_rdy ,
//**********************************************************************
//ram interface
output reg o_rd_en ,
output wire [9:0] o_rd_length ,
output wire [63:0] o_rd_addr ,
output wire o_cpld_tx_hold ,
output wire o_cpld_tlp_tx ,
input i_gen_tlp_start ,
input [127:0] i_rd_data ,
input i_last_data ,
//axis_slave interface
input i_axis_slave0_trdy ,
output reg o_axis_slave0_tvld ,
output reg [127:0] o_axis_slave0_tdata ,
output reg o_axis_slave0_tlast ,
output reg o_axis_slave0_tuser
);
localparam IDLE = 2'd0;
localparam HEADER_TX = 2'd1;
localparam DATA_TX = 2'd2;
localparam FIFO_DEEP = 7'd64; //should be 2^N real_deep = deep < 16 ? 16 : deep;
reg [9:0] cpld_length;
wire [9:0] cpld_length_tx;
reg [7:0] cpld_tag;
reg [63:0] cpld_addr;
reg [15:0] cpld_req_id;
reg [2:0] cpld_tc;
reg [2:0] cpld_attr;
reg is_first_cpl;
reg [9:0] first_cpl_offset;
wire first_cpl_offset_calcu_done;
wire rd_en;
reg [1:0] state;
reg [1:0] next_state;
//tlp_tx
wire [15:0] cpld_cpl_id;
wire [2:0] fmt;
wire [4:0] tlp_type;
wire th;
wire td;
wire [2:0] tc;
wire [2:0] attr;
wire ep;
wire [1:0] at;
wire [2:0] compl_status;
wire bcm;
wire [11:0] byte_cnt;
wire [6:0] low_addr;
wire [31:0] cpld_header_tx;
reg tx_busy;
wire tx_done;
wire data_vlad;
wire [103:0] data_in;
wire [103:0] data_out;
wire fifo_data_in;
wire fifo_data_out;
wire data_in_valid;
wire data_in_ready;
wire data_out_valid;
reg [6:0] fifo_data_cnt;
wire [9:0] max_payload_size;
assign max_payload_size = (i_cfg_max_payload_size == 3'd0) ? 10'h20 : //dw
(i_cfg_max_payload_size == 3'd1) ? 10'h40 :
(i_cfg_max_payload_size == 3'd2) ? 10'h80 :
(i_cfg_max_payload_size == 3'd3) ? 10'h100 : 10'd20;
//reg cpld_req_ff;
assign data_in = {i_mrd_tc, //103:101
i_mrd_attr, //100:98
i_mrd_length, //97:88
i_mrd_id, //87:72
i_mrd_tag, //71:64
i_mrd_addr}; //63:0
assign data_in_valid = i_cpld_req_vld;
assign o_cpld_req_rdy = data_in_ready;
//cpld_req buff
pgs_pciex4_prefetch_fifo_v1_2
#(
.D (FIFO_DEEP ), //should be 2^N
.W (104 )
)
u_cpld_req_fifo
(
.clk (clk ),
.rst_n (rst_n ),
.data_in_valid (data_in_valid ),
.data_in (data_in ),
.data_in_ready (data_in_ready ),
.data_out_ready (~tx_busy ),
.data_out (data_out ),
.data_out_valid (data_out_valid )
);
assign fifo_data_in = data_in_valid && data_in_ready ;
assign fifo_data_out = ~tx_busy && data_out_valid;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
fifo_data_cnt <= 7'b0;
else if(fifo_data_in && fifo_data_out)
fifo_data_cnt <= fifo_data_cnt;
else if(fifo_data_in)
fifo_data_cnt <= fifo_data_cnt + 7'h1;
else if(fifo_data_out)
fifo_data_cnt <= fifo_data_cnt - 7'h1;
end
//for o_trgt1_radm_pkt_halt[1] :Halt non-posted TLPs for VC0,MRD
assign o_cpld_tx_rdy = (fifo_data_cnt >= FIFO_DEEP- 7'd10 ) ? 1'b0 : 1'b1 ;
//******************************************************************get mrd information************************************************************************
// current mult-completion address equals to:
// 1. for the first completion, address equals to MRD address
// 2. for the other comoletion(if have), address from last mult-completion's address added last mult-completion's length
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cpld_addr <= 64'd0;
else if(fifo_data_out)
cpld_addr <= data_out[63:0];
else if(|cpld_length && state == HEADER_TX && !o_cpld_tx_hold)
cpld_addr <= cpld_addr + {52'b0,cpld_length_tx,2'b0};
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cpld_tag <= 8'd0;
else if(fifo_data_out)
cpld_tag <= data_out[71:64];
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cpld_req_id <= 16'd0;
else if(fifo_data_out)
cpld_req_id <= data_out[87:72];
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cpld_length <= 10'd0;
else if(fifo_data_out)
cpld_length <= data_out[97:88];
else if(state == HEADER_TX && !o_cpld_tx_hold)
cpld_length <= cpld_length - cpld_length_tx;
end
//multicpld: first completion
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
is_first_cpl <= 1'b0;
else if(tx_done)
is_first_cpl <= 1'b0;
else if(fifo_data_out)
is_first_cpl <= 1'b1;
end
//multicpld: for rcb first_completion_length = max_payload_size - first_cpl_offset
//first_cpl_offset need <= max_payload_size
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
first_cpl_offset <= 10'b0;
else if(fifo_data_out)
first_cpl_offset <= data_out[11:2];
else if (first_cpl_offset >= max_payload_size)
first_cpl_offset <= first_cpl_offset - max_payload_size;
end
assign first_cpl_offset_calcu_done = first_cpl_offset < max_payload_size;
//the true length to be transmitted
assign cpld_length_tx = (cpld_length <= max_payload_size) ? cpld_length :
(is_first_cpl && first_cpl_offset_calcu_done) ? (max_payload_size - first_cpl_offset) : max_payload_size ;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cpld_attr <= 3'd0;
else if(fifo_data_out)
cpld_attr <= data_out[100:98];
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cpld_tc <= 3'd0;
else if(fifo_data_out)
cpld_tc <= data_out[103:101];
end
//gen tx busy
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tx_busy <= 1'b0;
else if(tx_done && ~(|cpld_length))
tx_busy <= 1'b0;
else if(fifo_data_out)
tx_busy <= 1'b1;
end
//gen rd_en
assign rd_en = is_first_cpl ? ((cpld_length <= max_payload_size) ? |cpld_length : first_cpl_offset_calcu_done ) : |cpld_length;
//rd ram ctrl
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_rd_en <= 1'b0;
else if(tx_done)
o_rd_en <= 1'b0;
else if(rd_en)
o_rd_en <= 1'b1;
end
assign data_vlad = i_gen_tlp_start;
assign o_rd_length = cpld_length_tx;
assign o_rd_addr = cpld_addr;
//tlp header
//first DW
assign {fmt,tlp_type} = 8'h4a;
assign {th,td,ep,at} = 5'b0;
assign tc = cpld_tc;
assign attr = cpld_attr;
//second DW
assign cpld_cpl_id = {i_cfg_pbus_num,i_cfg_pbus_dev_num,3'b0};
assign compl_status = 3'b0;
assign bcm = 1'b0;
assign byte_cnt = {cpld_length,2'b0};
//third DW
assign low_addr = is_first_cpl ? {cpld_addr[6:2],2'b0} : 7'b0;
assign cpld_header_tx = {fmt,tlp_type,1'b0,tc,1'b0,attr[2],1'b0,th,td,ep,attr[1:0],at,cpld_length_tx};
//mwr_tx
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
state <= IDLE;
else
state <= next_state;
end
always @(*)
begin
case(state)
IDLE:
begin
if(i_gen_tlp_start && i_axis_slave0_trdy) //start transmit
next_state = HEADER_TX;
else
next_state = IDLE;
end
HEADER_TX:
begin
if(i_axis_slave0_trdy)
next_state = DATA_TX;
else
next_state = state;
end
DATA_TX:
begin
if(i_last_data && !o_cpld_tx_hold)//transmit end
next_state = IDLE;
else
next_state = state;
end
default:
begin
next_state = IDLE;
end
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
o_axis_slave0_tdata <= 128'b0;
o_axis_slave0_tvld <= 1'b0;
o_axis_slave0_tuser <= 1'b0;
o_axis_slave0_tlast <= 1'b0;
end
else if(!o_cpld_tx_hold)
begin
case(state)
IDLE:
begin
o_axis_slave0_tdata <= 128'b0;
o_axis_slave0_tvld <= 1'b0;
o_axis_slave0_tuser <= 1'b0;
o_axis_slave0_tlast <= 1'b0;
end
HEADER_TX:
begin
o_axis_slave0_tvld <= 1'b1;
o_axis_slave0_tdata <= {32'd0,cpld_req_id,cpld_tag,1'b0,low_addr,cpld_cpl_id,compl_status,bcm,byte_cnt,cpld_header_tx};
end
DATA_TX:
begin
o_axis_slave0_tvld <= data_vlad;
o_axis_slave0_tdata <= endian_convert(i_rd_data);
if(i_last_data)
o_axis_slave0_tlast <= 1'b1;
end
default:
begin
o_axis_slave0_tdata <= 128'b0;
o_axis_slave0_tvld <= 1'b0;
o_axis_slave0_tuser <= 1'b0;
o_axis_slave0_tlast <= 1'b0;
end
endcase
end
end
assign tx_done = i_axis_slave0_trdy && o_axis_slave0_tvld && o_axis_slave0_tlast;
//when i_axis_slave0_trdy down,hold all tx logic
assign o_cpld_tx_hold = ~i_axis_slave0_trdy && o_axis_slave0_tvld;
assign o_cpld_tlp_tx = state == DATA_TX;
//convert from little endian into big endian
function [127:0] endian_convert;
input [127:0] data_in;
begin
endian_convert[32*0+31:32*0+0] = {data_in[32*0+7:32*0+0], data_in[32*0+15:32*0+8], data_in[32*0+23:32*0+16], data_in[32*0+31:32*0+24]};
endian_convert[32*1+31:32*1+0] = {data_in[32*1+7:32*1+0], data_in[32*1+15:32*1+8], data_in[32*1+23:32*1+16], data_in[32*1+31:32*1+24]};
endian_convert[32*2+31:32*2+0] = {data_in[32*2+7:32*2+0], data_in[32*2+15:32*2+8], data_in[32*2+23:32*2+16], data_in[32*2+31:32*2+24]};
endian_convert[32*3+31:32*3+0] = {data_in[32*3+7:32*3+0], data_in[32*3+15:32*3+8], data_in[32*3+23:32*3+16], data_in[32*3+31:32*3+24]};
end
endfunction
endmodule |
module ipsl_pcie_dma_mrd_tx_ctrl (
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
input [7:0] i_cfg_pbus_num ,
input [4:0] i_cfg_pbus_dev_num ,
input [2:0] i_cfg_max_rd_req_size ,
//**********************************************************************
//from dma controller
input i_mrd32_req ,
output reg o_mrd32_req_ack ,
input i_mrd64_req ,
output reg o_mrd64_req_ack ,
input [9:0] i_req_length ,
input [63:0] i_req_addr ,
//**********************************************************************
input i_cpld_rcv ,
input [7:0] i_cpld_tag ,
output wire o_tag_full ,
//axis_slave interface
input i_axis_slave1_trdy ,
output reg o_axis_slave1_tvld ,
output reg [127:0] o_axis_slave1_tdata ,
output reg o_axis_slave1_tlast ,
output reg o_axis_slave1_tuser ,
//debug
input i_tx_restart
//output wire [13:0] o_dbg_bus
);
localparam IDLE = 2'd0;
localparam HEADER_TX = 2'd1;
reg [63:0] mrd_addr;
reg [9:0] mrd_length;
reg [9:0] mrd_length_ff;
wire [9:0] mrd_length_tx;
wire mrd_req_start;
reg mrd32_req_tx;
reg mrd64_req_tx;
reg [1:0] state;
reg [1:0] next_state;
wire mrd_req_rcv;
reg [63:0] cpld_tag;
//tlp_tx
wire [15:0] requester_id;
wire [2:0] fmt;
wire [4:0] tlp_type;
wire [2:0] tc;
wire [2:0] attr;
wire th;
wire td;
reg [5:0] mrd_tag;
wire ep;
wire [1:0] at;
wire [31:0] mrd_header_tx;
wire [3:0] first_dwbe;
wire [3:0] last_dwbe;
wire [7:0] dwbe;
reg tx_busy;
reg tx_mrd;
reg tx_mrd_ff;
wire mrd_req_ack;
wire mrd_tx_hold;
wire tx_done;
wire [63:0] mask_mrd_vec;
wire mrd_tx_halt;
reg tx_tag_vld;
wire [9:0] max_rd_req_size;
assign mrd_req_rcv = i_mrd32_req || i_mrd64_req;
assign mrd_req_ack = o_mrd32_req_ack || o_mrd64_req_ack;
assign mrd_req_start = mrd_req_rcv && mrd_req_ack;
assign tx_done = i_axis_slave1_trdy && o_axis_slave1_tvld && o_axis_slave1_tlast;
assign max_rd_req_size = (i_cfg_max_rd_req_size == 3'd0) ? 10'h20 :
(i_cfg_max_rd_req_size == 3'd1) ? 10'h40 :
(i_cfg_max_rd_req_size == 3'd2) ? 10'h80 :
(i_cfg_max_rd_req_size == 3'd3) ? 10'h100 : 10'd20;
//get tlp information
//length > max_rd_req_size,
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mrd_length <= 10'd0;
else if(mrd_req_start && !tx_busy)
mrd_length <= i_req_length;
else if((mrd_length > max_rd_req_size) && tx_mrd && i_axis_slave1_trdy)
mrd_length <= mrd_length - max_rd_req_size;
else if((mrd_length <= max_rd_req_size) && tx_mrd && i_axis_slave1_trdy)
mrd_length <= 10'b0;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mrd_length_ff <= 10'd0;
else if(~mrd_tx_halt)
mrd_length_ff <= mrd_length;
end
//the true length to be transmitted
assign mrd_length_tx = (mrd_length_ff > max_rd_req_size) ? max_rd_req_size : mrd_length_ff ;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mrd_addr <= 64'd0;
else if(mrd_req_start && !tx_busy)
mrd_addr <= i_req_addr;
else if(|mrd_length && tx_done)
mrd_addr <= mrd_addr + {52'b0,max_rd_req_size,2'b0};
end
//start tx mrd
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tx_mrd <= 1'b0;
else if(i_axis_slave1_trdy && tx_mrd)
tx_mrd <= 1'b0;
else if(mrd_req_start && !tx_busy && ~mrd_tx_halt) //new req rcv
tx_mrd <= 1'b1;
else if(|mrd_length && tx_done && ~mrd_tx_halt) //for length > max_rd_req_size
tx_mrd <= 1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tx_mrd_ff <= 1'b0;
else
tx_mrd_ff <= tx_mrd;
end
//tag ctrl,for 64 valid tag
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mrd_tag <= 6'b0;
else if(tx_done)
mrd_tag <= mrd_tag + 6'b1;
else if(cpld_tag == 64'b0)
mrd_tag <= 6'b0;
end
genvar i;
generate
for ( i = 0; i < 64; i = i + 1 )
begin:tag_ctrl
assign mask_mrd_vec[i] = tx_tag_vld && (mrd_tag == i) && cpld_tag[i];
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cpld_tag[i] <= 1'b0;
else if(o_axis_slave1_tvld && i_axis_slave1_trdy && (mrd_tag == i))
cpld_tag[i] <= 1'b1;
else if(i_cpld_rcv && (i_cpld_tag == i))
cpld_tag[i] <= 1'b0;
end
end
endgenerate
//
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tx_tag_vld <= 1'b0;
else if(tx_mrd && ~tx_mrd_ff)
tx_tag_vld <= 1'b1;
else if(o_axis_slave1_tvld && i_axis_slave1_trdy)
tx_tag_vld <= 1'b0;
end
//when the sent tag is not released,will halt mrd tx logic
assign mrd_tx_halt = |mask_mrd_vec;
assign o_tag_full = &cpld_tag;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mrd32_req_tx <= 1'b0;
else if(tx_done && ~(|mrd_length))
mrd32_req_tx <= 1'b0;
else if(mrd_req_start)
mrd32_req_tx <= i_mrd32_req;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
mrd64_req_tx <= 1'b0;
else if(tx_done && ~(|mrd_length))
mrd64_req_tx <= 1'b0;
else if(mrd_req_start)
mrd64_req_tx <= i_mrd64_req;
end
//tlp header
assign requester_id = {i_cfg_pbus_num,i_cfg_pbus_dev_num,3'b0};
assign {fmt,tlp_type} = mrd32_req_tx ? 8'h0
: mrd64_req_tx ? 8'h20 : 8'h00;
assign tc = 3'b0;
assign attr = 3'b0;
assign {th,td,ep,at} = 5'b0;
assign mrd_header_tx = {fmt,tlp_type,1'b0,tc,1'b0,attr[2],1'b0,th,td,ep,attr[1:0],at,mrd_length_tx};
assign first_dwbe = 4'hf;
assign last_dwbe = mrd_length_tx == 10'h1 ? 4'h0 : 4'hf;
assign dwbe = {last_dwbe,first_dwbe};
//mrd_tx
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
state <= IDLE;
else
state <= next_state;
end
always @(*)
begin
case(state)
IDLE:
begin
if(tx_mrd && i_axis_slave1_trdy && ~mrd_tx_halt) //start transmit
next_state = HEADER_TX;
else
next_state = IDLE;
end
HEADER_TX:
begin
if(mrd_tx_hold || mrd_tx_halt)
next_state = state;
else
next_state = IDLE;
end
default:
begin
next_state = IDLE;
end
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
o_axis_slave1_tdata <= 128'd0;
o_axis_slave1_tvld <= 1'b0;
o_axis_slave1_tuser <= 1'b0;
o_axis_slave1_tlast <= 1'b0;
end
else if(~mrd_tx_hold)
begin
case(state)
IDLE:
begin
o_axis_slave1_tdata <= 128'd0;
o_axis_slave1_tvld <= 1'b0;
o_axis_slave1_tuser <= 1'b0;
o_axis_slave1_tlast <= 1'b0;
end
HEADER_TX:
begin
o_axis_slave1_tvld <= ~mrd_tx_halt;
o_axis_slave1_tlast <= ~mrd_tx_halt;
if(mrd32_req_tx)
o_axis_slave1_tdata <= {{mrd_addr[31:2],2'b0},requester_id,{2'b0,mrd_tag},dwbe,mrd_header_tx};
else if(mrd64_req_tx)
o_axis_slave1_tdata <= {{mrd_addr[31:2],2'b0},mrd_addr[63:32],requester_id,{2'b0,mrd_tag},dwbe,mrd_header_tx};
end
default:
begin
o_axis_slave1_tdata <= 128'd0;
o_axis_slave1_tvld <= 1'b0;
o_axis_slave1_tuser <= 1'b0;
o_axis_slave1_tlast <= 1'b0;
end
endcase
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tx_busy <= 1'b0;
else if(~(|mrd_length) && tx_done)
tx_busy <= 1'b0;
else if(mrd_req_start)
tx_busy <= 1'b1;
end
//ack
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_mrd32_req_ack <= 1'b0;
else if(!i_mrd32_req)
o_mrd32_req_ack <= 1'b0;
else if(i_mrd32_req && !tx_busy)
o_mrd32_req_ack <= 1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_mrd64_req_ack <= 1'b0;
else if(!i_mrd64_req)
o_mrd64_req_ack <= 1'b0;
else if(i_mrd64_req && !tx_busy)
o_mrd64_req_ack <= 1'b1;
end
//when i_axis_slave1_trdy down,hold all tx logic
assign mrd_tx_hold = ~i_axis_slave1_trdy && o_axis_slave1_tvld;
//******************************************************************debug ************************************************************************
reg [13:0] tlp_tx_sum;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tlp_tx_sum <= 14'b0;
else if(i_tx_restart)
tlp_tx_sum <= 14'b0;
else if(tx_done)
tlp_tx_sum <= tlp_tx_sum + 14'b1;
end
//debug_bus
//assign o_dbg_bus = {
// tlp_tx_sum //13:0
// };
endmodule |
module ipsl_pcie_dma_rd_ctrl #(
parameter ADDR_WIDTH = 4'd9
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
//**********************************************************************
//ram interface
input i_rd_en ,
input [9:0] i_rd_length ,
input [63:0] i_rd_addr ,
input i_tx_hold ,
input i_tlp_tx ,
output wire o_rd_ram_hold ,
output wire o_gen_tlp_start ,
output wire [127:0] o_rd_data ,
output wire o_last_data ,
//ram_rd
output reg o_bar_rd_clk_en ,
output wire [ADDR_WIDTH-1:0] o_bar_rd_addr ,
input [127:0] i_bar_rd_data
);
localparam FIFO_DEEP = 8'd128; //should be 2^N real_deep = deep < 16 ? 16 : deep;
reg rd_en_ff;
wire rd_start;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [10:0] data_read_cnt;
reg [1:0] data_position;
reg [127:0] rd_data_ff;
wire [255:0] data_shift;
reg [127:0] data_shift_out;
reg [9:0] shift_data_cnt;
reg [9:0] shift_data_cnt_ff;
reg shift_data_out_valid;
reg ram_data_out_vld;
wire ram_last_data_rd ;
reg data_in_valid;
wire data_in_ready;
wire fifo_data_in;
wire fifo_data_out;
reg [7:0] fifo_data_cnt;
reg rd_ram_hold_ff;
wire data_out_ready;
wire data_out_valid;
reg [9:0] tx_data_cnt;
wire [127:0] data_out;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
rd_en_ff <= 1'b0;
else
rd_en_ff <= i_rd_en;
end
//rd ctrl start
assign rd_start = ~rd_en_ff && i_rd_en;
//total dw data need read
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_read_cnt <= 11'b0;
else if(rd_start)
data_read_cnt <= {1'b0,i_rd_length} + {9'b0,i_rd_addr[3:2]};
else if(!o_rd_ram_hold)
begin
if(data_read_cnt > 11'h4)
data_read_cnt <= data_read_cnt - 11'h4;
else if(data_read_cnt <= 11'h4)
data_read_cnt <= 11'b0;
end
end
//bar rd enable
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
o_bar_rd_clk_en <= 1'b0;
else if(rd_start)
o_bar_rd_clk_en <= 1'b1;
else if(data_read_cnt <= 11'd4)
o_bar_rd_clk_en <= 1'b0;
end
//bar rd addr
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
rd_addr <= {ADDR_WIDTH{1'b0}};
else if(rd_start)
rd_addr <= i_rd_addr[15:4];
else if(o_bar_rd_clk_en && !o_rd_ram_hold)
rd_addr <= rd_addr + {{(ADDR_WIDTH-1){1'b0}},1'b1};
end
assign o_bar_rd_addr = rd_addr;
//data_shift
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_position <= 2'b0;
else if(rd_start)
data_position <= i_rd_addr[3:2];
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
rd_data_ff <= 128'b0;
else if(!rd_ram_hold_ff)
rd_data_ff <= i_bar_rd_data;
end
assign data_shift = {i_bar_rd_data,rd_data_ff};
always@(*)
begin
case(data_position)
2'd0: data_shift_out = data_shift[32*0+127:32*0];
2'd1: data_shift_out = data_shift[32*1+127:32*1];
2'd2: data_shift_out = data_shift[32*2+127:32*2];
2'd3: data_shift_out = data_shift[32*3+127:32*3];
default : data_shift_out = 128'b0;
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
shift_data_cnt <= 10'b0;
else if(rd_start)
shift_data_cnt <= i_rd_length;
else if(!o_rd_ram_hold)
begin
if(shift_data_cnt >= 10'd4)
shift_data_cnt <= shift_data_cnt - 10'd4;
else if(shift_data_cnt < 10'd4)
shift_data_cnt <= 10'b0;
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
shift_data_cnt_ff <= 10'b0;
else
shift_data_cnt_ff <= shift_data_cnt;
end
//bar read data valid
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
ram_data_out_vld <= 1'b0;
else if(o_rd_ram_hold)
ram_data_out_vld <= 1'b0;
else
ram_data_out_vld <= o_bar_rd_clk_en;
end
//shift out data valid
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
shift_data_out_valid <= 1'b0;
else if(!o_rd_ram_hold)
begin
if(shift_data_cnt_ff > 10'b0)
shift_data_out_valid <= 1'b1;
else if(~(|shift_data_cnt_ff) && fifo_data_in)
shift_data_out_valid <= 1'b0;
end
end
//read ram last data flag
assign ram_last_data_rd = ~(|shift_data_cnt_ff) && shift_data_out_valid;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_in_valid <= 1'b0;
else if(o_rd_ram_hold || ram_last_data_rd && data_in_valid)
data_in_valid <= 1'b0;
else if(((fifo_data_cnt == FIFO_DEEP - 8'd3) && shift_data_out_valid) || ram_data_out_vld)
data_in_valid <= 1'b1;
end
pgs_pciex4_prefetch_fifo_v1_2
#(
.D (FIFO_DEEP ), //should be 2^N
.W (128 )
)
u_mwr_data_rd_fifo
(
.clk (clk ),
.rst_n (rst_n ),
.data_in_valid (data_in_valid ),
.data_in (data_shift_out ),
.data_in_ready (data_in_ready ),
.data_out_ready (data_out_ready ),
.data_out (data_out ),
.data_out_valid (data_out_valid )
);
assign fifo_data_in = data_in_valid && data_in_ready ;
assign fifo_data_out = data_out_ready && data_out_valid;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
fifo_data_cnt <= 8'b0;
else if(fifo_data_in && fifo_data_out)
fifo_data_cnt <= fifo_data_cnt;
else if(fifo_data_in)
fifo_data_cnt <= fifo_data_cnt + 8'h1;
else if(fifo_data_out)
fifo_data_cnt <= fifo_data_cnt - 8'h1;
end
assign o_rd_ram_hold = (fifo_data_cnt >= FIFO_DEEP - 8'd2) ? 1'b1 : 1'b0;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
rd_ram_hold_ff <= 1'b0;
else
rd_ram_hold_ff <= o_rd_ram_hold;
end
assign data_out_ready = i_tlp_tx && !i_tx_hold;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tx_data_cnt <= 10'b0;
else if(rd_start)
tx_data_cnt <= (i_rd_length >= 10'd4) ? i_rd_length - 10'd4 : 10'd0;
else if(fifo_data_out && |tx_data_cnt)
tx_data_cnt <= (tx_data_cnt >= 10'd4) ? tx_data_cnt - 10'd4 : 10'd0;
end
//read fifo last data flag
assign o_last_data = ~(|tx_data_cnt) && fifo_data_out;
assign o_gen_tlp_start = data_out_valid;
assign o_rd_data = data_out;
endmodule |
module ipsl_pcie_dma_rx_cpld_wr_ctrl #(
parameter ADDR_WIDTH = 4'd9
)(
input clk , //gen1:62.5MHz,gen2:125MHz
input rst_n ,
input [2:0] i_cfg_max_rd_req_size ,
//**********************************************************************
input i_cpld_wr_start ,
input [9:0] i_cpld_length ,
input [6:0] i_cpld_low_addr ,
input [11:0] i_cpld_byte_cnt ,
input [127:0] i_cpld_data ,
input [3:0] i_cpld_dw_vld ,
input [7:0] i_cpld_tag ,
input [1:0] i_bar_hit ,
input i_multicpld_flag ,
//**********************************************************************
//ram write control
output wire o_cpld_wr_en ,
output wire [ADDR_WIDTH-1:0] o_cpld_wr_addr ,
output wire [127:0] o_cpld_wr_data ,
output wire [15:0] o_cpld_wr_be ,
output wire [1:0] o_cpld_wr_bar_hit
);
reg wr_start_ff;
wire rx_start;
wire last_dw;
wire [1:0] last_dw_byte_num;
reg [3:0] first_dw_be;
reg [3:0] last_dw_be;
wire [7:0] cpld_dwbe;
wire [63:0] cpld_addr; //128byte
reg [9:0] tag_addr;
reg [9:0] tag_addr_next;
//
wire [5:0] cpld_tag_use;
reg [5:0] cpld_tag_use_ff;
reg addr_ram_wr_en;
wire [9:0] multicpld_addr;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
wr_start_ff <= 1'b0;
else
wr_start_ff <= i_cpld_wr_start;
end
assign rx_start = i_cpld_wr_start & ~wr_start_ff;
assign last_dw = ~i_cpld_wr_start & wr_start_ff;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
addr_ram_wr_en <= 1'b0;
else
addr_ram_wr_en <= rx_start;
end
//calculating dwbe from byte count and lower address
always@(*)
begin
case(i_cpld_low_addr[1:0])
2'd0: first_dw_be = 4'b1111;
2'd1: first_dw_be = 4'b1110;
2'd2: first_dw_be = 4'b1100;
2'd3: first_dw_be = 4'b1000;
default: first_dw_be = 4'hf;
endcase
end
assign last_dw_byte_num = i_cpld_byte_cnt[1:0] + i_cpld_low_addr[1:0];
always@(*)
begin
case(last_dw_byte_num)
2'd0: last_dw_be = 4'b1111;
2'd1: last_dw_be = 4'b0001;
2'd2: last_dw_be = 4'b0011;
2'd3: last_dw_be = 4'b0111;
default: last_dw_be = 4'hf;
endcase
end
assign cpld_dwbe = {last_dw_be,first_dw_be};
//************************************gen write address*************************************
assign cpld_tag_use = i_cpld_tag[5:0]; //64 tag use
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cpld_tag_use_ff <= 6'b0;
else
cpld_tag_use_ff <= cpld_tag_use; //128byte
end
//save multicpld address pointer
ipm_distributed_sdpram_v1_2
#(
.ADDR_WIDTH (6 ), //address width range:4-10
.DATA_WIDTH (10 ), //data width range:1-256
.RST_TYPE ("ASYNC" ), //reset type "ASYNC" "SYNC"
.OUT_REG (1 ), //output options :non_register(0) register(1)
.INIT_FILE ("NONE" ), //legal value:"NONE" or "initial file name"
.FILE_FORMAT("BIN" ) //initial data format : "BIN" or "HEX"
)
u_ipm_distributed_sdpram_v1_2
(
.wr_data ( tag_addr_next ),
.wr_addr ( cpld_tag_use_ff ),
.rd_addr ( cpld_tag_use ),
.wr_clk ( clk ),
.rd_clk ( clk ),
.wr_en ( addr_ram_wr_en ),
.rst ( ~rst_n ),
.rd_data ( multicpld_addr )
);
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tag_addr <= 10'b0;
else if(last_dw)
tag_addr <= multicpld_addr; //128byte
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
tag_addr_next <= 10'b0;
else if(rx_start)
tag_addr_next <= i_multicpld_flag ? tag_addr + {i_cpld_length[7:0],2'b0} : 10'b0; //128byte
end
assign cpld_addr = (i_cfg_max_rd_req_size == 3'd0) ? {51'b0,{cpld_tag_use_ff,tag_addr[6:0]}} : //128byte
(i_cfg_max_rd_req_size == 3'd1) ? {50'b0,{cpld_tag_use_ff,tag_addr[7:0]}} : //256byte
(i_cfg_max_rd_req_size == 3'd2) ? {49'b0,{cpld_tag_use_ff,tag_addr[8:0]}} : //512byte
(i_cfg_max_rd_req_size == 3'd3) ? {48'b0,{cpld_tag_use_ff,tag_addr[9:0]}} : //1024byte
{51'b0,{cpld_tag_use_ff,tag_addr[6:0]}} ;
//******************************************************************************************
ipsl_pcie_dma_wr_ctrl #(
.ADDR_WIDTH (ADDR_WIDTH )
)
ipsl_pcie_dma_cpld_wr_ctrl
(
.clk (clk ), //gen1:62.5MHz,gen2:125MHz
.rst_n (rst_n ),
//**********************************************************************
.i_wr_start (i_cpld_wr_start ),
.i_length (i_cpld_length ),
.i_dwbe (cpld_dwbe ),
.i_data (i_cpld_data ),
.i_dw_vld (i_cpld_dw_vld ),
.i_addr (cpld_addr ),
.i_bar_hit (i_bar_hit ),
//**********************************************************************
//ram write control
.o_wr_en (o_cpld_wr_en ),
.o_wr_addr (o_cpld_wr_addr ),
.o_wr_data (o_cpld_wr_data ),
.o_wr_be (o_cpld_wr_be ),
.o_wr_bar_hit (o_cpld_wr_bar_hit )
);
endmodule |
module pgm_distributed_fifo_v1_1
#(
parameter ADDR_WIDTH = 10 , // fifo depth width 4 -- 10
parameter DATA_WIDTH = 32 , // write data width 1 -- 256
parameter RST_TYPE = "ASYNC" , //reset type "ASYNC" "SYNC"
parameter OUT_REG = 0 , // output register legal value:0 or 1
parameter FIFO_TYPE = "ASYNC_FIFO" , // fifo type legal value "SYNC_FIFO" or "ASYNC_FIFO"
parameter ALMOST_FULL_NUM = 4 , // almost full number
parameter ALMOST_EMPTY_NUM = 4 // almost full number
)
(
input [DATA_WIDTH-1 : 0] wr_data , // input write data
input wr_en , // input write enable 1 active
input wr_clk , // input write clock
output full , // output write full flag 1 active
input wr_rst , // input write reset
output almost_full , // output write almost full
output [ADDR_WIDTH : 0] wr_water_level , // output write water level
output [DATA_WIDTH-1 : 0] rd_data , // output read data
input rd_en , // input read enable
input rd_clk , // input read clock
output empty , // output read empty
input rd_rst , // input read reset
output almost_empty ,
output [ADDR_WIDTH : 0] rd_water_level
);
//declare inner variables
wire [ADDR_WIDTH-1 : 0] wr_addr ;
wire [ADDR_WIDTH-1 : 0] rd_addr ;
wire wr_en_tmp ;
assign wr_en_tmp = wr_en & (~full);
//instance sdpram
pgm_distributed_sdpram_v1_1
#(
.ADDR_WIDTH(ADDR_WIDTH ) , //address width range:4-10
.DATA_WIDTH(DATA_WIDTH ) , //data width range:4-256
.RST_TYPE (RST_TYPE ) , //reset type "ASYNC_RESET" "SYNC_RESET"
.OUT_REG (OUT_REG )
) pgm_distributed_sdpram
(
.wr_data (wr_data ) ,
.wr_addr (wr_addr ) ,
.rd_addr (rd_addr ) ,
.wr_clk (wr_clk ) ,
.rd_clk (rd_clk ) ,
.wr_en (wr_en_tmp ) ,
.rst (rd_rst ) ,
.rd_data (rd_data )
);
pgm_distributed_fifo_ctr_v1_0
#(
.DEPTH (ADDR_WIDTH ), // write and read address width 4-- 10
.FIFO_TYPE (FIFO_TYPE ),
.ALMOST_FULL_NUM (ALMOST_FULL_NUM ),
.ALMOST_EMPTY_NUM (ALMOST_EMPTY_NUM)
)u_pgm_distributed_fifo_ctr_v1_0
(
.wr_clk (wr_clk ), //write clock
.w_en (wr_en ), //write enable 1 active
.wr_addr (wr_addr ), //write address
.wrst (wr_rst ), //write reset
.wfull (full ), //write full flag 1 active
.almost_full (almost_full ),
.wr_water_level (wr_water_level ),
.rd_clk (rd_clk ), //read clock
.r_en (rd_en ), //read enable 1 active
.rd_addr (rd_addr ), //read address
.rrst (rd_rst ), //read reset
.rempty (empty ), //read empty 1 active
.almost_empty (almost_empty ),
.rd_water_level (rd_water_level )
);
endmodule |
module pgr_prefetch_fifo
#(
parameter D = 16, //should be 2^N
parameter W = 8,
parameter TYPE = "Distributed" // "Distributed" or "DRM"
)
(
input clk,
input rst_n,
input data_in_valid,
input [W-1:0] data_in,
output data_in_ready,
input data_out_ready,
output [W-1:0] data_out,
output data_out_valid
);
//===================================================================
// Type | Latency | ADDR_WIDTH | Data width
// "Distributed" | 2 | 4~10 | 1~256
// "DRM" | 3 | 9~20 | 1~1152
//===================================================================
reg fifo_vld;
reg rd_en_ff1;
reg [2:0] shift_vld;
reg [W-1:0] rd_data_ff1;
wire [W-1:0] rd_data;
wire pop;
wire wr_en;
wire rd_en;
wire empty;
wire full;
wire rst;
//
assign wr_en = data_in_valid & ~full;
assign data_in_ready = ~full;
assign rst = ~rst_n;
//
localparam DEPTH = (D < 16) ? 16 : D;
assign rd_en = ~empty & data_out_ready;
assign data_out_valid = fifo_vld;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
fifo_vld <= 1'b0;
else if (rd_en)
fifo_vld <= 1'b1;
else
fifo_vld <= 1'b0;
end
assign data_out = rd_data_ff1;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
rd_data_ff1 <= 1'b0;
else if (rd_en)
rd_data_ff1 <= rd_data;
end
// distributed_fifo
pgm_distributed_fifo_v1_1
#(
.DATA_WIDTH ( W ),
.ADDR_WIDTH ( log2(DEPTH) ),
.OUT_REG ( 0 ),
.FIFO_TYPE ( "SYNC_FIFO" )
)
pgm_distributed_fifo_v1_0
(
.wr_data ( data_in ),
.wr_en ( wr_en ),
.wr_clk ( clk ),
.full ( full ),
.wr_rst ( rst ),
.almost_full ( ),
.wr_water_level ( ),
.rd_data ( rd_data ),
.rd_en ( rd_en ),
.rd_clk ( clk ),
.empty ( empty ),
.rd_rst ( rst ),
.rd_water_level ( ),
.almost_empty ( )
);
// Log 2
function integer log2;
input integer dep;
begin
log2 = 0;
while (dep > 1)
begin
dep = dep >> 1;
log2 = log2 + 1;
end
end
endfunction
endmodule |
module pgm_distributed_fifo_ctr_v1_0 #(
parameter DEPTH = 9 , // write adn read address width 4 -- 10
parameter FIFO_TYPE = "ASYNC_FIFO" , // ASYN_FIFO or SYN_FIFO
parameter ALMOST_FULL_NUM = 4 ,
parameter ALMOST_EMPTY_NUM = 4
)
(
input wire wr_clk , //write clock
input wire w_en , //write enable 1 active
output wire [DEPTH-1 : 0] wr_addr , //write address
input wire wrst , //write reset
output wire wfull , //write full flag 1 active
output wire almost_full , //output write almost full
output reg [DEPTH : 0] wr_water_level , //output write water level
input wire rd_clk , //read clock
input wire r_en , //read enable 1 active
output wire [DEPTH-1 : 0] rd_addr , //read address
input wire rrst , //read reset
output wire rempty , //read empty 1 active
output wire almost_empty , //output read almost empty
output reg [DEPTH : 0] rd_water_level //output read water level
);
//**************************************************************************************************************
//declare inner variables
//write address operation variables
reg [DEPTH : 0] wptr ; //write pointer
reg [DEPTH : 0] wrptr1 ; //1st read-domain to write-domain synchronizer
reg [DEPTH : 0] wrptr2 ; //2nd read-domain to write-domain synchronizer
reg [DEPTH : 0] wbin ; //write current binary pointer
reg [DEPTH : 0] wbnext ; //write next binary pointer
reg [DEPTH : 0] wgnext ; //write next gray pointer
reg waddr_msb ; //the MSB of waddr
wire wgnext_2ndmsb ; //the second MSB of wgnext
wire wrptr2_2ndmsb ; //the second MSB of wrptr2
//read address operation variables
reg [DEPTH : 0] rptr ; //read pointer
reg [DEPTH : 0] rwptr1 ; //1st write-domain to read-domain synchronizer
reg [DEPTH : 0] rwptr2 ; //2nd write-domain to read-domain synchronizer
reg [DEPTH : 0] rbin ; //read current binary pointer
reg [DEPTH : 0] rbnext ; //read next binary pointer
reg [DEPTH : 0] rgnext ; //read next gray pointer
reg raddr_msb ; //the MSB of raddr
reg [DEPTH : 0] wrptr2_b ; //wrptr2 into binary
reg [DEPTH : 0] rwptr2_b ; //rwptr2 into binary
//**************************************************************************************************************
reg asyn_wfull ;
reg asyn_almost_full ;
reg asyn_rempty ;
reg asyn_almost_empty ;
reg syn_wfull ;
reg syn_almost_full ;
reg syn_rempty ;
reg syn_almost_empty ;
//main code
//**************************************************************************************************************
generate
if(FIFO_TYPE == "ASYNC_FIFO")
begin:ASYN_CTRL
//write gray pointer generate
integer i;
always@(*)
begin
for(i = 0;i <= DEPTH;i = i+1 ) //gray to binary converter
wbin[i] = ^(wptr >> i);
end
always@(*)
begin
if(!wfull)
wbnext = wbin + w_en;
else
wbnext = wbin;
end
always@(*)
begin
wgnext = (wbnext >> 1) ^ wbnext; //binary to gray converter
end
always@( posedge wr_clk or posedge wrst )
begin
if(wrst)
begin
wptr <=0;
waddr_msb <=0;
end
else
begin
wptr <= wgnext;
waddr_msb <= wgnext[DEPTH] ^ wgnext[DEPTH-1];
end
end
//read domain to write domain synchronizer
always@( posedge wr_clk or posedge wrst )
begin
if(wrst)
{wrptr2,wrptr1} <= 0;
else
{wrptr2,wrptr1} <= {wrptr1,rptr};
end
always@(*)
begin
for(i = 0;i <= DEPTH;i = i+1 ) //gray to binary converter
wrptr2_b[i] = ^(wrptr2 >> i);
end
//generate fifo write full flag
assign wgnext_2ndmsb = wgnext[DEPTH] ^ wgnext[DEPTH-1];
assign wrptr2_2ndmsb = wrptr2[DEPTH] ^ wrptr2[DEPTH-1];
//**************************************************************************************************************
//read gray pointer generate
integer j;
always@(*)
begin
for(j = 0;j <= DEPTH;j = j+1 ) //gray to binary converter
rbin[j] = ^(rptr >> j);
end
always@(*)
begin
if(!rempty)
rbnext = rbin + r_en;
else
rbnext = rbin;
rgnext = (rbnext >> 1) ^ rbnext; //binary to gray converter
end
always@( posedge rd_clk or posedge rrst )
begin
if(rrst)
begin
rptr <=0;
raddr_msb <=0;
end
else
begin
rptr <= rgnext;
raddr_msb <= rgnext[DEPTH] ^ rgnext[DEPTH-1];
end
end
//read domain to write domain synchronizer
always@(posedge rd_clk or posedge rrst)
begin
if(rrst)
{rwptr2,rwptr1} <= 0;
else
{rwptr2,rwptr1} <= {rwptr1,wptr};
end
always@(*)
begin
for(i = 0;i <= DEPTH;i = i+1 ) //gray to binary converter
rwptr2_b[i] = ^(rwptr2 >> i);
end
//generate asyn_fifo write full flag
always@(posedge wr_clk or posedge wrst)
begin
if(wrst)
asyn_wfull <= 1'b0;
else
asyn_wfull <= ( (wgnext[DEPTH] != wrptr2[DEPTH]) &&
(wgnext_2ndmsb == wrptr2_2ndmsb) &&
(wgnext[DEPTH-2:0] == wrptr2[DEPTH-2:0]) );
end
//generate asyn_fifo write almost full flag
always@(posedge wr_clk or posedge wrst)
begin
if(wrst)
asyn_almost_full <= 1'b0;
else if (wbnext[DEPTH:0] < wrptr2_b[DEPTH:0])
asyn_almost_full <= ({1'b1,wbnext[DEPTH:0]} - {1'b0,wrptr2_b[DEPTH:0]} >= ALMOST_FULL_NUM );
else
asyn_almost_full <= ((wbnext[DEPTH:0] - wrptr2_b[DEPTH:0]) >= ALMOST_FULL_NUM );
end
//asyn_fifo read empty flag generate
always@(posedge rd_clk or posedge rrst)
begin
if(rrst)
asyn_rempty <= 1'b1;
else
asyn_rempty <= (rgnext == rwptr2);
end
//generate asyn_fifo read almost empty flag
always@(posedge rd_clk or posedge rrst)
begin
if(rrst)
asyn_almost_empty <= 1'b1;
else if(rwptr2_b[DEPTH:0] < rbnext[DEPTH:0])
asyn_almost_empty <= ({1'b1,rwptr2_b[DEPTH:0]} - {1'b0,rbnext[DEPTH:0]} <= ALMOST_EMPTY_NUM );
else
asyn_almost_empty <= ((rwptr2_b[DEPTH:0] - rbnext[DEPTH:0]) <= ALMOST_EMPTY_NUM );
end
end
else
begin:SYN_CTRL
//write operation
always@(*)
begin
if(!wfull)
wbnext = wptr + w_en;
else
wbnext = wptr;
end
always@(*)
begin
wgnext = wbnext; // syn fifo
end
always@( posedge wr_clk or posedge wrst )
begin
if(wrst)
begin
wptr <=0;
waddr_msb <=0;
end
else
begin
wptr <= wgnext;
waddr_msb <= wgnext[DEPTH-1];
end
end
always@(*)
begin
wrptr2 = rptr; // syn fifo
end
always@(*)
begin
wrptr2_b = rptr; // syn fifo
end
//generate fifo write full flag
assign wgnext_2ndmsb = wgnext[DEPTH-1];
assign wrptr2_2ndmsb = wrptr2[DEPTH-1];
//**************************************************************************************************************
//read operation
always@(*)
begin
if(!rempty)
rbnext = rptr + r_en;
else
rbnext = rptr;
end
always@(*)
begin
rgnext = rbnext;
end
always@( posedge rd_clk or posedge rrst )
begin
if(rrst)
begin
rptr <=0;
raddr_msb <=0;
end
else
begin
rptr <= rgnext;
raddr_msb <= rgnext[DEPTH-1];
end
end
always@(*)
begin
rwptr2 = wptr; //syn fifo
end
always@(*)
begin
rwptr2_b = wptr; //syn fifo
end
//generate syn_fifo write full flag
always@(posedge wr_clk or posedge wrst)
begin
if(wrst)
syn_wfull <= 1'b0;
else
syn_wfull <= ((wgnext[DEPTH] != rgnext[DEPTH]) &&
(wgnext[DEPTH-1:0] == rgnext[DEPTH-1:0]) );
end
//generate syn_fifo write almost full flag
always@(posedge wr_clk or posedge wrst)
begin
if(wrst)
syn_almost_full <= 1'b0;
else if (wbnext[DEPTH:0] < rbnext[DEPTH:0])
syn_almost_full <= ({1'b1,wbnext[DEPTH:0]} - {1'b0,rbnext[DEPTH:0]} >= ALMOST_FULL_NUM );
else
syn_almost_full <= ((wbnext[DEPTH:0] - rbnext[DEPTH:0]) >= ALMOST_FULL_NUM );
end
//syn_fifo read empty flag generate
always@(posedge rd_clk or posedge rrst)
begin
if(rrst)
syn_rempty <= 1'b1;
else
syn_rempty <= (rgnext == wgnext);
end
//generate syn_fifo read almost empty flag
always@(posedge rd_clk or posedge rrst)
begin
if(rrst)
syn_almost_empty <= 1'b1;
else if (wbnext[DEPTH:0] < rbnext[DEPTH:0])
syn_almost_empty <= ({1'b1,wbnext[DEPTH:0]} - {1'b0,rbnext[DEPTH:0]} <= ALMOST_EMPTY_NUM );
else
syn_almost_empty <= ((wbnext[DEPTH:0] - rbnext[DEPTH:0]) <= ALMOST_EMPTY_NUM );
end
end
endgenerate
//write flex memory address generate
assign wr_addr = {waddr_msb,wptr[DEPTH-2:0]};
//generate fifo write full flag
assign wfull = (FIFO_TYPE == "ASYNC_FIFO") ? asyn_wfull : syn_wfull;
//generate fifo write almost full flag
assign almost_full = (FIFO_TYPE == "ASYNC_FIFO") ? asyn_almost_full : syn_almost_full;
//generate write water level flag
always@(posedge wr_clk or posedge wrst)
begin
if(wrst)
wr_water_level <= 'b0;
else if (wbnext[DEPTH:0] < wrptr2_b[DEPTH:0])
wr_water_level <= ({1'b1,wbnext[DEPTH:0]} - {1'b0,wrptr2_b[DEPTH:0]});
else
wr_water_level <= ( wbnext[DEPTH:0] - wrptr2_b[DEPTH:0] );
end
//read flex memory address generate
assign rd_addr = {raddr_msb,rptr[DEPTH-2:0]};
//fifo read empty flag generate
assign rempty = (FIFO_TYPE == "ASYNC_FIFO") ? asyn_rempty : syn_rempty;
//generate fifo read almost empty flag
assign almost_empty = (FIFO_TYPE == "ASYNC_FIFO") ? asyn_almost_empty : syn_almost_empty;
//generate read water level flag
always@(posedge rd_clk or posedge rrst)
begin
if(rrst)
rd_water_level <= 'b0;
else if (rwptr2_b[DEPTH:0] < rbnext[DEPTH:0])
rd_water_level <= ({1'b1,rwptr2_b[DEPTH:0]} - {1'b0,rbnext[DEPTH:0]});
else
rd_water_level <= ( rwptr2_b[DEPTH:0] - rbnext[DEPTH:0] );
end
endmodule |
module ipsl_pcie_cfg_ctrl(
//from APB
input pclk_div2,
input apb_rst_n,
input p_sel,
input [3:0] p_strb,
input [7:0] p_addr,
input [31:0] p_wdata,
input p_ce,
input p_we,
output p_rdy,
output [31:0] p_rdata,
output pcie_cfg_ctrl_en,
//to PCIE ctrl
input axis_slave_tready,
output axis_slave_tvalid,
output axis_slave_tlast,
output axis_slave_tuser,
output [127:0] axis_slave_tdata,
output axis_master_tready,
input axis_master_tvalid,
input axis_master_tlast,
// input [7:0] axis_master_tuser,
input [3:0] axis_master_tkeep,
input [127:0] axis_master_tdata,
output [2:0] trgt1_radm_pkt_halt
//input [5:0] radm_grant_tlp_type
);
wire pcie_cfg_fmt;
wire pcie_cfg_type;
wire [7:0] pcie_cfg_tag;
wire [3:0] pcie_cfg_fbe;
wire [15:0] pcie_cfg_req_id;
wire [15:0] pcie_cfg_des_id;
wire [9:0] pcie_cfg_reg_num;
wire [31:0] pcie_cfg_tx_data;
wire tx_en;
wire pcie_cfg_cpl_rcv;
wire [2:0] pcie_cfg_cpl_status;
wire [31:0] pcie_cfg_rx_data;
ipsl_pcie_cfg_ctrl_apb u_pcie_cfg_ctrl_apb(
//apb interface
.pclk_div2 (pclk_div2 ),
.apb_rst_n (apb_rst_n ),
.p_sel (p_sel ),
.p_strb (p_strb ),
.p_addr (p_addr ),
.p_wdata (p_wdata ),
.p_ce (p_ce ),
.p_we (p_we ),
.p_rdy (p_rdy ),
.p_rdata (p_rdata ),
.pcie_cfg_ctrl_en (pcie_cfg_ctrl_en ),
//cfg ctrl
.pcie_cfg_fmt (pcie_cfg_fmt ),
.pcie_cfg_type (pcie_cfg_type ),
.pcie_cfg_tag (pcie_cfg_tag ),
.pcie_cfg_fbe (pcie_cfg_fbe ),
.pcie_cfg_req_id (pcie_cfg_req_id ),
.pcie_cfg_des_id (pcie_cfg_des_id ),
.pcie_cfg_reg_num (pcie_cfg_reg_num ),
.pcie_cfg_tx_data (pcie_cfg_tx_data ),
.tx_en (tx_en ),
.pcie_cfg_cpl_rcv (pcie_cfg_cpl_rcv ),
.pcie_cfg_cpl_status (pcie_cfg_cpl_status),
.pcie_cfg_rx_data (pcie_cfg_rx_data )
);
ipsl_pcie_cfg_trans u_pcie_cfg_trans(
.pclk_div2 (pclk_div2 ),
.apb_rst_n (apb_rst_n ),
//cfg trans
.pcie_cfg_fmt (pcie_cfg_fmt ),
.pcie_cfg_type (pcie_cfg_type ),
.pcie_cfg_tag (pcie_cfg_tag ),
.pcie_cfg_fbe (pcie_cfg_fbe ),
//.pcie_cfg_req_id (pcie_cfg_req_id ),
.pcie_cfg_des_id (pcie_cfg_des_id ),
.pcie_cfg_reg_num (pcie_cfg_reg_num ),
.pcie_cfg_tx_data (pcie_cfg_tx_data ),
.tx_en (tx_en ),
.pcie_cfg_cpl_rcv (pcie_cfg_cpl_rcv ),
.pcie_cfg_cpl_status (pcie_cfg_cpl_status),
.pcie_cfg_rx_data (pcie_cfg_rx_data ),
//pcie core
.axis_slave_tready (axis_slave_tready ),
.axis_slave_tvalid (axis_slave_tvalid ),
.axis_slave_tlast (axis_slave_tlast ),
.axis_slave_tuser (axis_slave_tuser ),
.axis_slave_tdata (axis_slave_tdata ),
.axis_master_tready (axis_master_tready ),
.axis_master_tvalid (axis_master_tvalid ),
.axis_master_tlast (axis_master_tlast ),
//.axis_master_tuser (axis_master_tuser ),
.axis_master_tkeep (axis_master_tkeep ),
.axis_master_tdata (axis_master_tdata ),
.trgt1_radm_pkt_halt (trgt1_radm_pkt_halt)
//.radm_grant_tlp_type (radm_grant_tlp_type)
);
endmodule |
module ipsl_pcie_cfg_trans(
//from pcie_cfg_core_apb
input pclk_div2,
input apb_rst_n,
input pcie_cfg_fmt,
input pcie_cfg_type,
input [7:0] pcie_cfg_tag,
input [3:0] pcie_cfg_fbe,
// input [15:0] pcie_cfg_req_id,
input [15:0] pcie_cfg_des_id,
input [9:0] pcie_cfg_reg_num,
input [31:0] pcie_cfg_tx_data,
input tx_en,
output reg pcie_cfg_cpl_rcv,
output reg [2:0] pcie_cfg_cpl_status,
output reg [31:0] pcie_cfg_rx_data,
//to pcie_core
input axis_slave_tready,
output reg axis_slave_tvalid,
output reg axis_slave_tlast,
output axis_slave_tuser,
output reg [127:0] axis_slave_tdata,
output axis_master_tready,
input axis_master_tvalid,
input axis_master_tlast,
// input [7:0] axis_master_tuser,
input [3:0] axis_master_tkeep,
input [127:0] axis_master_tdata,
output [2:0] trgt1_radm_pkt_halt
// input [5:0] radm_grant_tlp_type
);
wire [4:0] type_code; //
reg tx_en_r;
reg tx_en_2r;
wire tx_start;
reg tx_data_en;
reg tx_wait_en;
reg rx_data_en;
//-----------------------------------------------------CFG TLP TX --------------------------------------------
//tx_start indicator
always@(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n) begin
tx_en_r <= 1'b0;
tx_en_2r <= 1'b0;
end
else begin
tx_en_r <= tx_en;
tx_en_2r <= tx_en_r;
end
assign tx_start = tx_en_r && !tx_en_2r;
//--------------------------------------------axis_slave-
assign axis_slave_tuser = 1'b0; // not used in bringup test
assign type_code = pcie_cfg_type ? 5'b00101 : 5'b00100; //type1:00101 type0:00100
always@(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
axis_slave_tvalid <= 1'b0;
else if (tx_start)
axis_slave_tvalid <= 1'b1;
else if (axis_slave_tlast)
axis_slave_tvalid <= 1'b0;
always@(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n) begin
axis_slave_tlast <= 1'b0;
axis_slave_tdata <= 128'h0;
tx_wait_en <= 1'b0;
tx_data_en <= 1'b0;
end
else if (tx_start|tx_wait_en) begin
if(axis_slave_tready) begin
case(pcie_cfg_fmt)
1'b0:begin //cfg rd fmt=000
axis_slave_tlast <= 1'b1;
axis_slave_tdata <= {32'h0,
pcie_cfg_des_id,4'h0,pcie_cfg_reg_num,2'h0, //Des ID,RSVD,REG_NUM,RSVD
16'h0,pcie_cfg_tag,4'h0,pcie_cfg_fbe, //REQ ID determined bt CTRL,TAG,LBE,FBE
3'h0,type_code,8'h0,8'h0,8'h1}; //FMT,TYPE,TC,ATTR,TH,TD,EP,AT,LENGTH
tx_wait_en <= 1'b0;
end
1'b1:begin //cfg_wr fmt=010
axis_slave_tlast <= 1'b0;
axis_slave_tdata <= {32'h0,
pcie_cfg_des_id,4'h0,pcie_cfg_reg_num,2'h0, //Des ID,RSVD,REG_NUM,RSVD
16'h0,pcie_cfg_tag,4'h0,pcie_cfg_fbe, //REQ ID determined bt CTRL,TAG,LBE,FBE
3'h2,type_code,8'h0,8'h0,8'h1}; //FMT,TYPE,TC,ATTR,TH,TD,EP,AT,LENGTH
tx_wait_en <= 1'b0;
tx_data_en <= 1'b1;
end
endcase
end
else begin
tx_wait_en <= 1'b1;
end
end
else if(tx_data_en) begin
axis_slave_tlast <= 1'b1;
axis_slave_tdata <= endian_convert({96'h0,pcie_cfg_tx_data});
tx_data_en <= 1'b0;
end
else begin
axis_slave_tlast<= 1'b0;
end
//--------------------------------------------------------CFG CPL ------
wire [127:0] pcie_rx_data;
assign pcie_rx_data = endian_convert(axis_master_tdata);
assign trgt1_radm_pkt_halt = 3'b000; //APP not halt the RX channel
assign axis_master_tready = 1'b1;
always@(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n) begin
pcie_cfg_cpl_rcv <= 1'b0;
pcie_cfg_cpl_status <= 3'b0;
pcie_cfg_rx_data <= 32'h0;
rx_data_en <= 1'b0;
end
else if(axis_master_tvalid && axis_master_tready
&& axis_master_tdata[28:24]== 5'b01010 //cpl type
&& axis_master_tdata[79:72]== pcie_cfg_tag
&& !rx_data_en)begin //tag is for cfg req tag
case(axis_master_tdata[31:29])
3'b000:begin //CPL without DATA
pcie_cfg_cpl_rcv <= 1'b1;
pcie_cfg_cpl_status <= axis_master_tdata[47:45]; //cpl status field
pcie_cfg_rx_data <= 32'h0;
end
3'b010:begin //CPL with DATA
pcie_cfg_cpl_rcv <= 1'b0;
pcie_cfg_cpl_status <= axis_master_tdata[47:45]; //CPL status field
rx_data_en <= 1'b1;
end
default:begin
pcie_cfg_cpl_rcv <= 1'b0;
pcie_cfg_cpl_status <= 3'b0;
rx_data_en <= 1'b0;
end
endcase
end
else if(rx_data_en && axis_master_tlast && axis_master_tvalid && axis_master_tready) begin
pcie_cfg_cpl_rcv <= 1'b1;
pcie_cfg_rx_data <= {32{axis_master_tkeep[0]}} & axis_master_tdata[31:0];
rx_data_en <= 1'b0;
end
else begin
pcie_cfg_cpl_rcv <= 1'b0;
end
//convert from little endian into big endian
function [127:0] endian_convert;
input [127:0] data_in;
begin
endian_convert[32*0+31:32*0+0] = {data_in[32*0+7:32*0+0], data_in[32*0+15:32*0+8], data_in[32*0+23:32*0+16], data_in[32*0+31:32*0+24]};
endian_convert[32*1+31:32*1+0] = {data_in[32*1+7:32*1+0], data_in[32*1+15:32*1+8], data_in[32*1+23:32*1+16], data_in[32*1+31:32*1+24]};
endian_convert[32*2+31:32*2+0] = {data_in[32*2+7:32*2+0], data_in[32*2+15:32*2+8], data_in[32*2+23:32*2+16], data_in[32*2+31:32*2+24]};
endian_convert[32*3+31:32*3+0] = {data_in[32*3+7:32*3+0], data_in[32*3+15:32*3+8], data_in[32*3+23:32*3+16], data_in[32*3+31:32*3+24]};
end
endfunction
endmodule |
module ipsl_pcie_cfg_ctrl_apb(
//from APB
input pclk_div2,
input apb_rst_n,
input p_sel,
input [3:0] p_strb,
input [7:0] p_addr,
input [31:0] p_wdata,
input p_ce,
input p_we,
output reg p_rdy,
output reg [31:0] p_rdata,
output pcie_cfg_ctrl_en,
//to cfg_trans
output pcie_cfg_fmt,
output pcie_cfg_type,
output [7:0] pcie_cfg_tag,
output [3:0] pcie_cfg_fbe,
output [15:0] pcie_cfg_req_id,
output [15:0] pcie_cfg_des_id,
output [9:0] pcie_cfg_reg_num,
output [31:0] pcie_cfg_tx_data,
output tx_en,
input pcie_cfg_cpl_rcv,
input [2:0] pcie_cfg_cpl_status,
input [31:0] pcie_cfg_rx_data
);
localparam IDLE = 1'b0;
localparam SETUP = 1'b1;
reg state;
reg nextstate;
reg [31:0] reg0;
reg [31:0] reg1;
reg [31:0] reg2;
reg [31:0] reg3;
reg [31:0] reg4;
wire reg0_wr;
wire reg1_wr;
wire reg2_wr;
wire reg3_wr;
assign pcie_cfg_fmt = reg0[0];
assign pcie_cfg_type = reg0[1];
assign pcie_cfg_fbe = reg0[5:2];
assign pcie_cfg_tag = reg0[15:8];
assign tx_en = reg0[24];
assign pcie_cfg_req_id = reg1[15:0];
assign pcie_cfg_des_id = reg1[31:16];
assign pcie_cfg_reg_num = reg2[9:0];
assign pcie_cfg_ctrl_en = reg2[24];
assign pcie_cfg_tx_data = reg3[31:0];
//-------------------------------APB FSM------------------------------------
//---------------PHASE 1-----------
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
state <= IDLE;
else
state <= nextstate;
//---------------PHASE 2-----------
always@(*)
case (state)
IDLE:begin
if(p_sel && !p_ce)
nextstate = SETUP;
else
nextstate = IDLE;
end
SETUP: nextstate = IDLE;
default: nextstate =IDLE;
endcase
//---------------PHASE 3-----------
// p_rdy
always@(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
p_rdy <= 1'b0;
else if(state== IDLE && p_sel && !p_ce)
p_rdy <= 1'b1;
else
p_rdy <= 1'b0;
//***************APB write*********************
assign reg0_wr = p_addr ==8'h0 && p_we && p_ce && p_rdy;
assign reg1_wr = p_addr ==8'h4 && p_we && p_ce && p_rdy;
assign reg2_wr = p_addr ==8'h8 && p_we && p_ce && p_rdy;
assign reg3_wr = p_addr ==8'hc && p_we && p_ce && p_rdy;
//***************reg0 write
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg0[7:0] <= 8'h0;
else if (reg0_wr & p_strb[0])
reg0[5:0] <= p_wdata[5:0];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg0[15:8] <= 8'h0;
else if (reg0_wr & p_strb[1])
reg0[15:8] <= p_wdata[15:8];
//reg0[19:16] are W1C
always@(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg0[23:16] <= 8'h0;
else if (reg0_wr & p_strb[2])
reg0[19:16] <= reg0[19:16] & (~p_wdata[19:16]);
else if (pcie_cfg_cpl_rcv)
reg0[19:16] <= {pcie_cfg_cpl_status,1'b1};
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg0[31:24] <= 8'h0;
else if (reg0_wr & p_strb[3])
reg0[24] <= p_wdata[24];
//***************reg1 write
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg1[7:0] <= 8'h0;
else if (reg1_wr & p_strb[0])
reg1[7:0] <= p_wdata[7:0];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg1[15:8] <= 8'h0;
else if (reg1_wr & p_strb[1])
reg1[15:8] <= p_wdata[15:8];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg1[23:16] <= 8'h0;
else if (reg1_wr & p_strb[2])
reg1[23:16] <= p_wdata[23:16];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg1[31:24] <= 8'h0;
else if (reg1_wr & p_strb[3])
reg1[31:24] <= p_wdata[31:24];
//***************reg2 write
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg2[7:0] <= 8'h0;
else if (reg2_wr & p_strb[0])
reg2[7:0] <= p_wdata[7:0];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg2[15:8] <= 8'h0;
else if (reg2_wr & p_strb[1])
reg2[9:8] <= p_wdata[9:8];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg2[23:16] <= 8'h0;
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg2[31:24] <= 8'h0;
else if (reg2_wr & p_strb[3])
reg2[24] <= p_wdata[24];
//***************reg3 write
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg3[7:0] <= 8'h0;
else if (reg3_wr & p_strb[0])
reg3[7:0] <= p_wdata[7:0];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg3[15:8] <= 8'h0;
else if (reg3_wr & p_strb[1])
reg3[15:8] <= p_wdata[15:8];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg3[23:16] <= 8'h0;
else if (reg3_wr & p_strb[2])
reg3[23:16] <= p_wdata[23:16];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg3[31:24] <= 8'h0;
else if (reg3_wr & p_strb[3])
reg3[31:24] <= p_wdata[31:24];
//***************reg4 write
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg4[7:0] <= 8'h0;
else if (pcie_cfg_cpl_rcv)
reg4[7:0] <= pcie_cfg_rx_data[7:0];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg4[15:8] <= 8'h0;
else if (pcie_cfg_cpl_rcv)
reg4[15:8] <= pcie_cfg_rx_data[15:8];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg4[23:16] <= 8'h0;
else if (pcie_cfg_cpl_rcv)
reg4[23:16] <= pcie_cfg_rx_data[23:16];
always @(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
reg4[31:24] <= 8'h0;
else if (pcie_cfg_cpl_rcv)
reg4[31:24] <= pcie_cfg_rx_data[31:24];
//***************APB read***************************************
always@(posedge pclk_div2 or negedge apb_rst_n)
if(!apb_rst_n)
p_rdata <= 32'h0;
else if (state == IDLE && p_sel && !p_ce && !p_we) begin
case(p_addr)
8'h0: p_rdata <= reg0;
8'h4: p_rdata <= reg1;
8'h8: p_rdata <= reg2;
8'hc: p_rdata <= reg3;
8'h10: p_rdata <= reg4;
default: p_rdata <= 32'h0;
endcase
end
else
p_rdata <= 32'h0;
endmodule |
module ipsl_pcie_dma_ram
(
wr_data , //input write data
wr_addr , //input write address
wr_en , //input write enable
wr_clk , //input write clock
wr_rst , //input write reset
wr_byte_en , //input write reset
rd_data , //output read data
rd_addr , //input read address
rd_clk , //input read clock
rd_clk_en , //input read clock enable
rd_rst //input read reset
);
localparam POWER_OPT = 0 ; // @IPC bool
localparam RESET_TYPE = "ASYNC" ; // @IPC enum Sync_Internally,SYNC,ASYNC
localparam SAMEWIDTH_EN = 1 ; // @IPC bool
localparam WR_BYTE_EN = 1 ; // @IPC bool
localparam BYTE_SIZE = 8 ; // @IPC enum 8,9
localparam WR_ADDR_WIDTH = 12 ; // @IPC int 9,20
localparam WR_DATA_WIDTH = 128 ; // @IPC int 1,1152
localparam BE_WIDTH = 16 ; // @IPC int 2,128
localparam WR_CLK_EN = 0 ; // @IPC bool
localparam WR_ADDR_STROBE_EN = 0 ; // @IPC bool
localparam RD_ADDR_WIDTH = 12 ; // @IPC int 9,20
localparam RD_DATA_WIDTH = 128 ; // @IPC int 1,1152
localparam RD_BE_WIDTH = 16 ; // @IPC int 1,128
localparam RD_CLK_EN = 1 ; // @IPC bool
localparam RD_ADDR_STROBE_EN = 0 ; // @IPC bool
localparam OUTPUT_REG = 0 ; // @IPC bool
localparam RD_OCE_EN = 0 ; // @IPC bool
localparam RD_CLK_OR_POL_INV = 0 ; // @IPC bool
localparam INIT_EN = 1 ; // @IPC bool
localparam INIT_FILE = "F:/01_svn/platform_ip/system_ip/ipsl_pcie/ipsl_pcie_source/src/example_design/rtl/ipsl_pcie_dma_ram/rc_ram_init.dat" ; // @IPC string
localparam INIT_FORMAT = "HEX" ; // @IPC enum BIN,HEX
localparam RESET_TYPE_CTRL = (RESET_TYPE == "ASYNC") ? "ASYNC_RESET" :
(RESET_TYPE == "SYNC") ? "SYNC_RESET" : "ASYNC_RESET_SYNC_RELEASE";
localparam DEVICE_NAME = "PGL50H";
localparam WR_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? 10 : WR_DATA_WIDTH;
localparam RD_DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? 10 : RD_DATA_WIDTH;
localparam SIM_DEVICE = ((DEVICE_NAME == "PGL22G") || (DEVICE_NAME == "PGL22GS")) ? "PGL22G" : "LOGOS";
input [WR_DATA_WIDTH-1:0] wr_data ; //input write data [WR_DATA_WIDTH-1:0]
input [WR_ADDR_WIDTH-1:0] wr_addr ; //input write address [WR_ADDR_WIDTH-1:0]
input wr_en ; //input write enable
input wr_clk ; //input write clock
input wr_rst ; //input write reset
input [BE_WIDTH-1:0] wr_byte_en ; //input write reset
output [RD_DATA_WIDTH-1:0] rd_data ; //output read data [C_RD_DATA_WIDTH-1:0]
input [RD_ADDR_WIDTH-1:0] rd_addr ; //input read address [RD_ADDR_WIDTH-1:0]
input rd_clk ; //input read clock
input rd_clk_en ; //input read clock enable
input rd_rst ; //input read reset
wire [WR_DATA_WIDTH-1:0] wr_data ; //input write data [WR_DATA_WIDTH-1:0]
wire [WR_ADDR_WIDTH-1:0] wr_addr ; //input write address [WR_ADDR_WIDTH-1:0]
wire wr_en ; //input write enable
wire wr_clk ; //input write clock
wire wr_clk_en ; //input write clock enable
wire wr_rst ; //input write reset
wire [BE_WIDTH-1:0] wr_byte_en ; //input write reset
wire wr_addr_strobe ; //input write address string
wire [RD_DATA_WIDTH-1:0] rd_data ; //output read data [C_RD_DATA_WIDTH-1:0]
wire [RD_ADDR_WIDTH-1:0] rd_addr ; //input read address [RD_ADDR_WIDTH-1:0]
wire rd_clk ; //input read clock
wire rd_clk_en ; //input read clock enable
wire rd_rst ; //input read reset
wire rd_oce ; //input read output register enable
wire rd_addr_strobe ; //input read address string
wire [BE_WIDTH-1:0] wr_byte_en_mux ;
wire rd_oce_mux ;
wire wr_clk_en_mux ;
wire rd_clk_en_mux ;
wire wr_addr_strobe_mux ;
wire rd_addr_strobe_mux ;
wire [WR_DATA_WIDTH_WRAP-1 : 0] wr_data_wrap;
wire [RD_DATA_WIDTH_WRAP-1 : 0] rd_data_wrap;
assign wr_byte_en_mux = (WR_BYTE_EN == 1) ? wr_byte_en : -1 ;
assign rd_oce_mux = (RD_OCE_EN == 1) ? rd_oce :
(OUTPUT_REG == 1) ? 1'b1 : 1'b0 ;
assign wr_clk_en_mux = (WR_CLK_EN == 1) ? wr_clk_en : 1'b1 ;
assign rd_clk_en_mux = (RD_CLK_EN == 1) ? rd_clk_en : 1'b1 ;
assign wr_addr_strobe_mux = (WR_ADDR_STROBE_EN ==1) ? wr_addr_strobe : 1'b0 ;
assign rd_addr_strobe_mux = (RD_ADDR_STROBE_EN ==1) ? rd_addr_strobe : 1'b0 ;
assign wr_data_wrap = ((DEVICE_NAME == "PGT30G") && (WR_DATA_WIDTH <= 9)) ? {{(WR_DATA_WIDTH_WRAP - WR_DATA_WIDTH){1'b0}},wr_data} : wr_data;
assign rd_data = ((DEVICE_NAME == "PGT30G") && (RD_DATA_WIDTH <= 9)) ? rd_data_wrap[RD_DATA_WIDTH-1 : 0] : rd_data_wrap;
//ipml_sdpram IP instance
ipml_sdpram_v1_5_ipsl_pcie_dma_ram
#(
.c_SIM_DEVICE (SIM_DEVICE ),
.c_WR_ADDR_WIDTH (WR_ADDR_WIDTH ),
.c_WR_DATA_WIDTH (WR_DATA_WIDTH_WRAP ),
.c_RD_ADDR_WIDTH (RD_ADDR_WIDTH ),
.c_RD_DATA_WIDTH (RD_DATA_WIDTH_WRAP ),
.c_OUTPUT_REG (OUTPUT_REG ),
.c_RD_OCE_EN (RD_OCE_EN ),
.c_WR_ADDR_STROBE_EN (WR_ADDR_STROBE_EN ),
.c_RD_ADDR_STROBE_EN (RD_ADDR_STROBE_EN ),
.c_WR_CLK_EN (WR_CLK_EN ),
.c_RD_CLK_EN (RD_CLK_EN ),
.c_RD_CLK_OR_POL_INV (RD_CLK_OR_POL_INV ),
.c_RESET_TYPE (RESET_TYPE_CTRL ),
.c_POWER_OPT (POWER_OPT ),
.c_INIT_FILE ("NONE" ),
.c_INIT_FORMAT (INIT_FORMAT ),
.c_WR_BYTE_EN (WR_BYTE_EN ),
.c_BE_WIDTH (BE_WIDTH )
) U_ipml_sdpram_ipsl_pcie_dma_ram
(
.wr_data (wr_data_wrap ),//input write data
.wr_addr (wr_addr ),//input write address
.wr_en (wr_en ),//input write enable
.wr_clk (wr_clk ),//input write clock
.wr_clk_en (wr_clk_en_mux ),//input write clock enable
.wr_rst (wr_rst ),//input write reset
.wr_byte_en (wr_byte_en_mux ),//input write byte enable
.wr_addr_strobe (wr_addr_strobe_mux ),//input write address strobe
.rd_data (rd_data_wrap ),//output read data
.rd_addr (rd_addr ),//input read address
.rd_clk (rd_clk ),//input read clock
.rd_clk_en (rd_clk_en_mux ),//input read clock enable
.rd_rst (rd_rst ),//input read reset
.rd_oce (rd_oce_mux ),//input read output register enable
.rd_addr_strobe (rd_addr_strobe_mux ) //input read address strobe
);
endmodule |
module pgs_pciex4_fifo_v1_2 #(
parameter ADDR_WIDTH = 10 , // fifo depth width 4 -- 10
parameter DATA_WIDTH = 32 , // write data width 1 -- 256
parameter OUT_REG = 0
)
(
input clk , // input write clock
input rst_n , // input write reset
input [DATA_WIDTH-1 : 0] wr_data , // input write data
input wr_en , // input write enable 1 active
output full , // output write full flag 1 active
output [DATA_WIDTH-1 : 0] rd_data , // output read data
input rd_en , // input read enable
output empty // output read empty
);
wire [ADDR_WIDTH-1 : 0] wr_addr ;
wire [ADDR_WIDTH-1 : 0] rd_addr ;
wire wr_en_tmp ;
wire rd_en_tmp ;
assign wr_en_tmp = wr_en & (~full);
assign rd_en_tmp = rd_en & (~empty);
//instance sdpram
ipm_distributed_sdpram_v1_2_distributed_fifo
#(
.ADDR_WIDTH(ADDR_WIDTH ) , //address width range:4-10
.DATA_WIDTH(DATA_WIDTH ) , //data width range:4-256
.RST_TYPE ("ASYNC" ) , //reset type "ASYNC_RESET" "SYNC_RESET"
.OUT_REG (OUT_REG )
) ipm_distributed_sdpram_distributed_fifo
(
.wr_data (wr_data ) ,
.wr_addr (wr_addr ) ,
.rd_addr (rd_addr ) ,
.wr_clk (clk ) ,
.rd_clk (clk ) ,
.wr_en (wr_en_tmp ) ,
.rst (~rst_n ) ,
.rd_data (rd_data )
);
pgs_pciex4_fifo_ctrl
#(
.ADDR_WIDTH (ADDR_WIDTH )
) pgs_pciex4_fifo_ctrl
(
.clk (clk ), //write clock
.w_en (wr_en_tmp ), //write enable 1 active
.wr_addr (wr_addr ), //write address //write reset
.wfull (full ), //write full flag 1 active
.r_en (rd_en_tmp ), //read enable 1 active
.rd_addr (rd_addr ), //read address
.rst_n (rst_n ), //read reset
.rempty (empty ) //read empty 1 active
);
endmodule //pgs_pciex4_fifo |
module pgs_pciex4_fifo_ctrl #(
parameter ADDR_WIDTH = 9
)
( input clk ,
input rst_n ,
input w_en ,
output reg [ADDR_WIDTH-1 : 0] wr_addr ,
output reg wfull ,
input r_en ,
output reg [ADDR_WIDTH-1 : 0] rd_addr ,
output reg rempty
);
reg [ADDR_WIDTH-1 : 0] fifo_cnt;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
fifo_cnt <= {ADDR_WIDTH{1'b0}};
else
case({w_en, r_en})
2'b10: fifo_cnt <= fifo_cnt + {{(ADDR_WIDTH-1){1'b0}}, 1'b1};
2'b01: fifo_cnt <= fifo_cnt - {{(ADDR_WIDTH-1){1'b0}}, 1'b1};
endcase
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
wr_addr <= {ADDR_WIDTH{1'b0}};
else if(w_en)
wr_addr <= wr_addr + {{(ADDR_WIDTH-1){1'b0}}, 1'b1};
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
rd_addr <= {ADDR_WIDTH{1'b0}};
else if(r_en)
rd_addr <= rd_addr + {{(ADDR_WIDTH-1){1'b0}}, 1'b1};
end
//FIFO full
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
wfull <= 1'b0;
else if ( (fifo_cnt == {{(ADDR_WIDTH-1){1'b1}}, 1'b0}) & w_en & ~r_en )
wfull <= 1'b1;
else if (~w_en & r_en)
wfull <= 1'b0;
end
//FIFO empty
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
rempty <= 1'b1;
else if ( (fifo_cnt == {{(ADDR_WIDTH-1){1'b0}}, 1'b1}) & ~w_en & r_en )
rempty <= 1'b1;
else if (w_en & ~r_en)
rempty <= 1'b0;
end
endmodule |
module ipml_pcie_hsst_x2_top (
input i_p_refckn_1 ,
input i_p_refckp_1 ,
input i_p_tx_lane_pd_0 ,
input i_p_tx_lane_pd_1 ,
input i_p_lane_pd_0 ,
input i_p_lane_pd_1 ,
input i_p_lane_rst_0 ,
input i_p_lane_rst_1 ,
input i_p_rx_lane_pd_0 ,
input i_p_rx_lane_pd_1 ,
output o_p_clk2core_tx_0 ,
input i_p_tx0_clk_fr_core ,
input i_p_tx1_clk_fr_core ,
input i_p_tx0_clk2_fr_core ,
input i_p_tx1_clk2_fr_core ,
output o_p_clk2core_rx_0 ,
input i_p_rx0_clk_fr_core ,
input i_p_rx1_clk_fr_core ,
input i_p_rx0_clk2_fr_core ,
input i_p_rx1_clk2_fr_core ,
input i_p_pll_rst_0 ,
input i_p_tx_pma_rst_0 ,
input i_p_tx_pma_rst_1 ,
input i_p_pcs_tx_rst_0 ,
input i_p_pcs_tx_rst_1 ,
input i_p_rx_pma_rst_0 ,
input i_p_rx_pma_rst_1 ,
input i_p_pcs_rx_rst_0 ,
input i_p_pcs_rx_rst_1 ,
input i_p_pcs_cb_rst_0 ,
input i_p_pcs_cb_rst_1 ,
input [2:0] i_p_lx_margin_ctl_0 ,
input [2:0] i_p_lx_margin_ctl_1 ,
input i_p_lx_swing_ctl_0 ,
input i_p_lx_swing_ctl_1 ,
input [1:0] i_p_lx_deemp_ctl_0 ,
input [1:0] i_p_lx_deemp_ctl_1 ,
input i_p_lane_sync_0 ,
input i_p_lane_sync_en_0 ,
input i_p_rate_change_tclk_on_0 ,
input [1:0] i_p_tx_ckdiv_0 ,
input [1:0] i_p_tx_ckdiv_1 ,
input [1:0] i_p_lx_rx_ckdiv_0 ,
input [1:0] i_p_lx_rx_ckdiv_1 ,
input [1:0] i_p_lx_elecidle_en_0 ,
input [1:0] i_p_lx_elecidle_en_1 ,
output o_p_pll_lock_0 ,
output o_p_rx_sigdet_sta_0 ,
output o_p_rx_sigdet_sta_1 ,
output o_p_lx_cdr_align_0 ,
output o_p_lx_cdr_align_1 ,
input i_p_lx_rxdct_en_0 ,
input i_p_lx_rxdct_en_1 ,
output o_p_lx_rxdct_out_0 ,
output o_p_lx_rxdct_out_1 ,
output o_p_pcs_lsm_synced_0 ,
output o_p_pcs_lsm_synced_1 ,
input i_p_pcs_nearend_loop_0 ,
input i_p_pcs_farend_loop_0 ,
input i_p_pma_nearend_ploop_0 ,
input i_p_pma_nearend_sloop_0 ,
input i_p_pma_farend_ploop_0 ,
input i_p_pcs_nearend_loop_1 ,
input i_p_pcs_farend_loop_1 ,
input i_p_pma_nearend_ploop_1 ,
input i_p_pma_nearend_sloop_1 ,
input i_p_pma_farend_ploop_1 ,
input i_p_rx_polarity_invert_0 ,
input i_p_rx_polarity_invert_1 ,
input i_p_tx_beacon_en_0 ,
input i_p_tx_beacon_en_1 ,
input i_p_cfg_clk ,
input i_p_cfg_rst ,
input i_p_cfg_psel ,
input i_p_cfg_enable ,
input i_p_cfg_write ,
input [15:0] i_p_cfg_addr ,
input [7:0] i_p_cfg_wdata ,
output [7:0] o_p_cfg_rdata ,
output o_p_cfg_int ,
output o_p_cfg_ready ,
input i_p_l0rxn ,
input i_p_l0rxp ,
input i_p_l1rxn ,
input i_p_l1rxp ,
output o_p_l0txn ,
output o_p_l0txp ,
output o_p_l1txn ,
output o_p_l1txp ,
input [31:0] i_txd_0 ,
input [3:0] i_tdispsel_0 ,
input [3:0] i_tdispctrl_0 ,
input [3:0] i_txk_0 ,
input [31:0] i_txd_1 ,
input [3:0] i_tdispsel_1 ,
input [3:0] i_tdispctrl_1 ,
input [3:0] i_txk_1 ,
output [2:0] o_rxstatus_0 ,
output [31:0] o_rxd_0 ,
output [3:0] o_rdisper_0 ,
output [3:0] o_rdecer_0 ,
output [3:0] o_rxk_0 ,
output [2:0] o_rxstatus_1 ,
output [31:0] o_rxd_1 ,
output [3:0] o_rdisper_1 ,
output [3:0] o_rdecer_1 ,
output [3:0] o_rxk_1 ,
input i_p_pllpowerdown_0
);
// ********************* UI parameters *********************
//-- wire INNER RESET & HSST ---//
wire P_PLL_READY_0 ; // input wire
wire P_PLL_READY_1 ; // input wire
wire P_RX_SIGDET_STATUS_0 ; // input wire
wire P_RX_SIGDET_STATUS_1 ; // input wire
wire P_RX_SIGDET_STATUS_2 ; // input wire
wire P_RX_SIGDET_STATUS_3 ; // input wire
wire P_LX_CDR_ALIGN_0 ; // input wire
wire P_LX_CDR_ALIGN_1 ; // input wire
wire P_LX_CDR_ALIGN_2 ; // input wire
wire P_LX_CDR_ALIGN_3 ; // input wire
wire P_PLLPOWERDOWN_0 ; // output wire
wire P_PLLPOWERDOWN_1 ; // output wire
wire P_PLL_RST_0 ; // output wire
wire P_PLL_RST_1 ; // output wire
wire P_LANE_SYNC_0 ; // output wire
wire P_LANE_SYNC_1 ; // output wire
wire P_LANE_SYNC_EN_0 ; // output wire
wire P_LANE_SYNC_EN_1 ; // output wire
wire P_RATE_CHANGE_TCLK_ON_0 ; // output wire
wire P_RATE_CHANGE_TCLK_ON_1 ; // output wire
wire P_TX_LANE_PD_0 ; // output wire
wire P_TX_LANE_PD_1 ; // output wire
wire P_TX_LANE_PD_2 ; // output wire
wire P_TX_LANE_PD_3 ; // output wire
wire [2 : 0] P_TX_RATE_0 ; // output wire [2 : 0]
wire [2 : 0] P_TX_RATE_1 ; // output wire [2 : 0]
wire [2 : 0] P_TX_RATE_2 ; // output wire [2 : 0]
wire [2 : 0] P_TX_RATE_3 ; // output wire [2 : 0]
wire P_TX_PMA_RST_0 ; // output wire
wire P_TX_PMA_RST_1 ; // output wire
wire P_TX_PMA_RST_2 ; // output wire
wire P_TX_PMA_RST_3 ; // output wire
wire P_PCS_TX_RST_0 ; // output wire
wire P_PCS_TX_RST_1 ; // output wire
wire P_PCS_TX_RST_2 ; // output wire
wire P_PCS_TX_RST_3 ; // output wire
wire P_RX_PMA_RST_0 ; // output wire
wire P_RX_PMA_RST_1 ; // output wire
wire P_RX_PMA_RST_2 ; // output wire
wire P_RX_PMA_RST_3 ; // output wire
wire P_LANE_PD_0 ; // output wire
wire P_LANE_PD_1 ; // output wire
wire P_LANE_PD_2 ; // output wire
wire P_LANE_PD_3 ; // output wire
wire P_LANE_RST_0 ; // output wire
wire P_LANE_RST_1 ; // output wire
wire P_LANE_RST_2 ; // output wire
wire P_LANE_RST_3 ; // output wire
wire P_RX_LANE_PD_0 ; // output wire
wire P_RX_LANE_PD_1 ; // output wire
wire P_RX_LANE_PD_2 ; // output wire
wire P_RX_LANE_PD_3 ; // output wire
wire P_PCS_RX_RST_0 ; // output wire
wire P_PCS_RX_RST_1 ; // output wire
wire P_PCS_RX_RST_2 ; // output wire
wire P_PCS_RX_RST_3 ; // output wire
wire [2 : 0] P_RX_RATE_0 ; // output wire [2 : 0]
wire [2 : 0] P_RX_RATE_1 ; // output wire [2 : 0]
wire [2 : 0] P_RX_RATE_2 ; // output wire [2 : 0]
wire [2 : 0] P_RX_RATE_3 ; // output wire [2 : 0]
wire P_PCS_CB_RST_0 ; // output wire
wire P_PCS_CB_RST_1 ; // output wire
wire P_PCS_CB_RST_2 ; // output wire
wire P_PCS_CB_RST_3 ; // output wire
wire i_force_rxfsm_det_0 ; // input wire
wire i_force_rxfsm_det_1 ; // input wire
wire i_force_rxfsm_det_2 ; // input wire
wire i_force_rxfsm_det_3 ; // input wire
wire i_force_rxfsm_cdr_0 ; // input wire
wire i_force_rxfsm_cdr_1 ; // input wire
wire i_force_rxfsm_cdr_2 ; // input wire
wire i_force_rxfsm_cdr_3 ; // input wire
wire i_force_rxfsm_lsm_0 ; // input wire
wire i_force_rxfsm_lsm_1 ; // input wire
wire i_force_rxfsm_lsm_2 ; // input wire
wire i_force_rxfsm_lsm_3 ; // input wire
wire [3:0] P_TCLK2FABRIC ; // output wire
wire [3:0] P_RCLK2FABRIC ; // output wire
wire [3:0] P_PCS_WORD_ALIGN_EN ; // input wire
wire [3:0] P_RX_POLARITY_INVERT ; // input wire
wire [3:0] P_PCS_MCB_EXT_EN ; // input wire
wire [3:0] P_PCS_LSM_SYNCED ; // output wire
wire [3:0] P_PCS_RX_MCB_STATUS ; // output wire
wire [3:0] P_PCS_NEAREND_LOOP ; // input wire
wire [3:0] P_PCS_FAREND_LOOP ; // input wire
wire [3:0] P_PMA_NEAREND_PLOOP ; // input wire
wire [3:0] P_PMA_NEAREND_SLOOP ; // input wire
wire [3:0] P_PMA_FAREND_PLOOP ; // input wire
wire i_free_clk = 1'b0;
wire i_pll_rst_0 = 1'b0;
wire i_pll_rst_1 = 1'b0;
wire i_wtchdg_clr_0 = 1'b0;
wire i_wtchdg_clr_1 = 1'b0;
wire i_lane_pd_0 = 1'b0;
wire i_lane_pd_1 = 1'b0;
wire i_lane_pd_2 = 1'b0;
wire i_lane_pd_3 = 1'b0;
wire i_txlane_rst_0 = 1'b0;
wire i_txlane_rst_1 = 1'b0;
wire i_txlane_rst_2 = 1'b0;
wire i_txlane_rst_3 = 1'b0;
wire i_rxlane_rst_0 = 1'b0;
wire i_rxlane_rst_1 = 1'b0;
wire i_rxlane_rst_2 = 1'b0;
wire i_rxlane_rst_3 = 1'b0;
wire i_tx_rate_chng_0 = 1'b0;
wire i_tx_rate_chng_1 = 1'b0;
wire i_tx_rate_chng_2 = 1'b0;
wire i_tx_rate_chng_3 = 1'b0;
wire [1:0] i_txckdiv_0 = 3 ;
wire [1:0] i_txckdiv_1 = 3 ;
wire [1:0] i_txckdiv_2 = 1 ;
wire [1:0] i_txckdiv_3 = 1 ;
wire i_rx_rate_chng_0 = 1'b0;
wire i_rx_rate_chng_1 = 1'b0;
wire i_rx_rate_chng_2 = 1'b0;
wire i_rx_rate_chng_3 = 1'b0;
wire [1:0] i_rxckdiv_0 = 3 ;
wire [1:0] i_rxckdiv_1 = 3 ;
wire [1:0] i_rxckdiv_2 = 1 ;
wire [1:0] i_rxckdiv_3 = 1 ;
wire i_pcs_cb_rst_0 = 1'b0;
wire i_hsst_fifo_clr_0 = 1'b0;
assign i_force_rxfsm_det_0 = 1'b0;
assign i_force_rxfsm_cdr_0 = 1'b0;
assign i_force_rxfsm_lsm_0 = 1'b0;
wire i_pcs_cb_rst_1 = 1'b0;
wire i_hsst_fifo_clr_1 = 1'b0;
assign i_force_rxfsm_det_1 = 1'b0;
assign i_force_rxfsm_cdr_1 = 1'b0;
assign i_force_rxfsm_lsm_1 = 1'b0;
wire i_pcs_cb_rst_2 = 1'b0;
wire i_hsst_fifo_clr_2 = 1'b0;
assign i_force_rxfsm_det_2 = 1'b0;
assign i_force_rxfsm_cdr_2 = 1'b0;
assign i_force_rxfsm_lsm_2 = 1'b0;
wire i_pcs_cb_rst_3 = 1'b0;
wire i_hsst_fifo_clr_3 = 1'b0;
assign i_force_rxfsm_det_3 = 1'b0;
assign i_force_rxfsm_cdr_3 = 1'b0;
assign i_force_rxfsm_lsm_3 = 1'b0;
wire [1:0] o_wtchdg_st_0 ;
wire [1:0] o_wtchdg_st_1 ;
wire o_pll_done_0 ;
wire o_pll_done_1 ;
wire o_txlane_done_0 ;
wire o_txlane_done_1 ;
wire o_txlane_done_2 ;
wire o_txlane_done_3 ;
wire o_tx_ckdiv_done_0 ;
wire o_tx_ckdiv_done_1 ;
wire o_tx_ckdiv_done_2 ;
wire o_tx_ckdiv_done_3 ;
wire o_rxlane_done_0 ;
wire o_rxlane_done_1 ;
wire o_rxlane_done_2 ;
wire o_rxlane_done_3 ;
wire o_rx_ckdiv_done_0 ;
wire o_rx_ckdiv_done_1 ;
wire o_rx_ckdiv_done_2 ;
wire o_rx_ckdiv_done_3 ;
wire i_p_pllpowerdown_1 = 1'b1;
wire i_p_tx_lane_pd_2 = 1'b1;
wire i_p_tx_lane_pd_3 = 1'b1;
wire i_p_lane_pd_2 = 1'b1;
wire i_p_lane_pd_3 = 1'b1;
wire i_p_lane_rst_2 = 1'b0;
wire i_p_lane_rst_3 = 1'b0;
wire i_p_rx_lane_pd_2 = 1'b1;
wire i_p_rx_lane_pd_3 = 1'b1;
assign o_p_clk2core_tx_0 = P_TCLK2FABRIC[0];
wire i_p_tx2_clk_fr_core = 1'b0;
wire i_p_tx3_clk_fr_core = 1'b0;
wire i_p_tx2_clk2_fr_core = 1'b0;
wire i_p_tx3_clk2_fr_core = 1'b0;
wire i_pll_lock_tx_0 = 1'b1;
wire i_pll_lock_tx_1 = 1'b1;
wire i_pll_lock_tx_2 = 1'b1;
wire i_pll_lock_tx_3 = 1'b1;
assign o_p_clk2core_rx_0 = P_RCLK2FABRIC[0];
wire i_p_rx2_clk_fr_core = 1'b0;
wire i_p_rx3_clk_fr_core = 1'b0;
wire i_p_rx2_clk2_fr_core = 1'b0;
wire i_p_rx3_clk2_fr_core = 1'b0;
wire i_pll_lock_rx_0 = 1'b1;
wire i_pll_lock_rx_1 = 1'b1;
wire i_pll_lock_rx_2 = 1'b1;
wire i_pll_lock_rx_3 = 1'b1;
wire o_p_refck2core_0 ;
wire o_p_refck2core_1 ;
wire i_p_pll_rst_1 = 1'b1;
wire i_p_tx_pma_rst_2 = 1'b1;
wire i_p_tx_pma_rst_3 = 1'b1;
wire i_p_pcs_tx_rst_2 = 1'b1;
wire i_p_pcs_tx_rst_3 = 1'b1;
wire i_p_rx_pma_rst_2 = 1'b1;
wire i_p_rx_pma_rst_3 = 1'b1;
wire i_p_pcs_rx_rst_2 = 1'b1;
wire i_p_pcs_rx_rst_3 = 1'b1;
wire i_p_pcs_cb_rst_2 = 1'b0;
wire i_p_pcs_cb_rst_3 = 1'b0;
wire [2:0] i_p_lx_margin_ctl_2 = 3'b0;
wire [2:0] i_p_lx_margin_ctl_3 = 3'b0;
wire i_p_lx_swing_ctl_2 = 1'b0;
wire i_p_lx_swing_ctl_3 = 1'b0;
wire [1:0] i_p_lx_deemp_ctl_2 = 2'b0;
wire [1:0] i_p_lx_deemp_ctl_3 = 2'b0;
wire i_p_rx_highz_0 =1'b0;
wire i_p_rx_highz_1 =1'b0;
wire i_p_rx_highz_2 =1'b0;
wire i_p_rx_highz_3 =1'b0;
wire i_p_lane_sync_1 =1'b0;
wire i_p_lane_sync_en_1 =1'b0;
wire i_p_rate_change_tclk_on_1 =1'b1;
wire [1:0] i_p_tx_ckdiv_2 = 1 ;
wire [1:0] i_p_tx_ckdiv_3 = 1 ;
wire [1:0] i_p_lx_rx_ckdiv_2 = 1 ;
wire [1:0] i_p_lx_rx_ckdiv_3 = 1 ;
wire [1:0] i_p_lx_elecidle_en_2 = 2'b0;
wire [1:0] i_p_lx_elecidle_en_3 = 2'b0;
assign o_p_pll_lock_0 = P_PLL_READY_0;
assign o_p_rx_sigdet_sta_0 = P_RX_SIGDET_STATUS_0;
assign o_p_rx_sigdet_sta_1 = P_RX_SIGDET_STATUS_1;
assign o_p_lx_cdr_align_0 = P_LX_CDR_ALIGN_0;
assign o_p_lx_cdr_align_1 = P_LX_CDR_ALIGN_1;
wire [1:0] o_p_lx_oob_sta_0 ;
wire [1:0] o_p_lx_oob_sta_1 ;
wire [1:0] o_p_lx_oob_sta_2 ;
wire [1:0] o_p_lx_oob_sta_3 ;
wire i_p_lx_rxdct_en_2 = 1'b0;
wire i_p_lx_rxdct_en_3 = 1'b0;
wire o_p_lx_rxdct_out_2 ;
wire o_p_lx_rxdct_out_3 ;
wire i_p_rxgear_slip_0 = 1'b0;
wire i_p_rxgear_slip_1 = 1'b0;
wire i_p_rxgear_slip_2 = 1'b0;
wire i_p_rxgear_slip_3 = 1'b0;
assign P_PCS_WORD_ALIGN_EN[0] = 1'b0;
assign P_PCS_WORD_ALIGN_EN[1] = 1'b0;
assign P_PCS_WORD_ALIGN_EN[2] = 1'b0;
assign P_PCS_WORD_ALIGN_EN[3] = 1'b0;
assign P_PCS_MCB_EXT_EN[0] = 1'b0;
assign P_PCS_MCB_EXT_EN[1] = 1'b0;
assign P_PCS_MCB_EXT_EN[2] = 1'b0;
assign P_PCS_MCB_EXT_EN[3] = 1'b0;
assign o_p_pcs_lsm_synced_0 = P_PCS_LSM_SYNCED[0];
assign o_p_pcs_lsm_synced_1 = P_PCS_LSM_SYNCED[1];
assign P_PCS_NEAREND_LOOP[0] = i_p_pcs_nearend_loop_0;
assign P_PCS_FAREND_LOOP[0] = i_p_pcs_farend_loop_0;
assign P_PMA_NEAREND_PLOOP[0] = i_p_pma_nearend_ploop_0;
assign P_PMA_NEAREND_SLOOP[0] = i_p_pma_nearend_sloop_0;
assign P_PMA_FAREND_PLOOP[0] = i_p_pma_farend_ploop_0;
assign P_PCS_NEAREND_LOOP[1] = i_p_pcs_nearend_loop_1;
assign P_PCS_FAREND_LOOP[1] = i_p_pcs_farend_loop_1;
assign P_PMA_NEAREND_PLOOP[1] = i_p_pma_nearend_ploop_1;
assign P_PMA_NEAREND_SLOOP[1] = i_p_pma_nearend_sloop_1;
assign P_PMA_FAREND_PLOOP[1] = i_p_pma_farend_ploop_1;
assign P_PCS_NEAREND_LOOP[2] = 1'b0;
assign P_PCS_FAREND_LOOP[2] = 1'b0;
assign P_PMA_NEAREND_PLOOP[2] = 1'b0;
assign P_PMA_NEAREND_SLOOP[2] = 1'b0;
assign P_PMA_FAREND_PLOOP[2] = 1'b0;
assign P_PCS_NEAREND_LOOP[3] = 1'b0;
assign P_PCS_FAREND_LOOP[3] = 1'b0;
assign P_PMA_NEAREND_PLOOP[3] = 1'b0;
assign P_PMA_NEAREND_SLOOP[3] = 1'b0;
assign P_PMA_FAREND_PLOOP[3] = 1'b0;
assign P_RX_POLARITY_INVERT[0] = i_p_rx_polarity_invert_0;
assign P_RX_POLARITY_INVERT[1] = i_p_rx_polarity_invert_1;
assign P_RX_POLARITY_INVERT[2] = 1'b0;
assign P_RX_POLARITY_INVERT[3] = 1'b0;
wire i_p_tx_beacon_en_2 = 1'b0;
wire i_p_tx_beacon_en_3 = 1'b0;
wire [45:0] i_p_tdata_0 = {i_p_lx_elecidle_en_0,
i_txk_0[3],i_tdispctrl_0[3],i_tdispsel_0[3],i_txd_0[31:24],
i_txk_0[2],i_tdispctrl_0[2],i_tdispsel_0[2],i_txd_0[23:16],
i_txk_0[1],i_tdispctrl_0[1],i_tdispsel_0[1],i_txd_0[15:8],
i_txk_0[0],i_tdispctrl_0[0],i_tdispsel_0[0],i_txd_0[7:0]};
wire [45:0] i_p_tdata_1 = {i_p_lx_elecidle_en_1,
i_txk_1[3],i_tdispctrl_1[3],i_tdispsel_1[3],i_txd_1[31:24],
i_txk_1[2],i_tdispctrl_1[2],i_tdispsel_1[2],i_txd_1[23:16],
i_txk_1[1],i_tdispctrl_1[1],i_tdispsel_1[1],i_txd_1[15:8],
i_txk_1[0],i_tdispctrl_1[0],i_tdispsel_1[0],i_txd_1[7:0]};
wire [45:0] i_p_tdata_2 = 46'b0;
wire [45:0] i_p_tdata_3 = 46'b0;
wire [46:0] o_p_rdata_0 ;
assign o_rxstatus_0 = o_p_rdata_0[46:44];
assign o_rxd_0 = {o_p_rdata_0[40:33],o_p_rdata_0[29:22],o_p_rdata_0[18:11],o_p_rdata_0[7:0]};
assign o_rdisper_0 = {o_p_rdata_0[41],o_p_rdata_0[30],o_p_rdata_0[19],o_p_rdata_0[8]};
assign o_rdecer_0 = {o_p_rdata_0[42],o_p_rdata_0[31],o_p_rdata_0[20],o_p_rdata_0[9]};
assign o_rxk_0 = {o_p_rdata_0[43],o_p_rdata_0[32],o_p_rdata_0[21],o_p_rdata_0[10]};
wire [46:0] o_p_rdata_1 ;
assign o_rxstatus_1 = o_p_rdata_1[46:44];
assign o_rxd_1 = {o_p_rdata_1[40:33],o_p_rdata_1[29:22],o_p_rdata_1[18:11],o_p_rdata_1[7:0]};
assign o_rdisper_1 = {o_p_rdata_1[41],o_p_rdata_1[30],o_p_rdata_1[19],o_p_rdata_1[8]};
assign o_rdecer_1 = {o_p_rdata_1[42],o_p_rdata_1[31],o_p_rdata_1[20],o_p_rdata_1[9]};
assign o_rxk_1 = {o_p_rdata_1[43],o_p_rdata_1[32],o_p_rdata_1[21],o_p_rdata_1[10]};
wire [46:0] o_p_rdata_2 ;
wire [46:0] o_p_rdata_3 ;
ipml_hsst_rst_v1_1#(
.INNER_RST_EN ("FALSE" ), //TRUE: HSST Reset Auto Control, FALSE: HSST Reset Control by User
.FREE_CLOCK_FREQ (100.0 ), //Unit is MHz, free clock freq from GUI Freq: 0~200MHz
.CH0_TX_ENABLE ("TRUE" ), //TRUE:lane0 TX Reset Logic used, FALSE: lane0 TX Reset Logic remove
.CH1_TX_ENABLE ("TRUE" ), //TRUE:lane1 TX Reset Logic used, FALSE: lane1 TX Reset Logic remove
.CH2_TX_ENABLE ("FALSE" ), //TRUE:lane2 TX Reset Logic used, FALSE: lane2 TX Reset Logic remove
.CH3_TX_ENABLE ("FALSE" ), //TRUE:lane3 TX Reset Logic used, FALSE: lane3 TX Reset Logic remove
.CH0_RX_ENABLE ("TRUE" ), //TRUE:lane0 RX Reset Logic used, FALSE: lane0 RX Reset Logic remove
.CH1_RX_ENABLE ("TRUE" ), //TRUE:lane1 RX Reset Logic used, FALSE: lane1 RX Reset Logic remove
.CH2_RX_ENABLE ("FALSE" ), //TRUE:lane2 RX Reset Logic used, FALSE: lane2 RX Reset Logic remove
.CH3_RX_ENABLE ("FALSE" ), //TRUE:lane3 RX Reset Logic used, FALSE: lane3 RX Reset Logic remove
.CH0_MULT_LANE_MODE (2 ), //Lane0 --> 1: Singel Lane 2:Two Lane 4:Four Lane
.CH1_MULT_LANE_MODE (2 ), //Lane1 --> 1: Singel Lane 2:Two Lane 4:Four Lane
.CH2_MULT_LANE_MODE (1 ), //Lane2 --> 1: Singel Lane 2:Two Lane 4:Four Lane
.CH3_MULT_LANE_MODE (1 ), //Lane3 --> 1: Singel Lane 2:Two Lane 4:Four Lane
.CH0_RXPCS_ALIGN_TIMER (65535 ), //Word Alignment Wait time, when match the RXPMA will be Reset
.CH1_RXPCS_ALIGN_TIMER (65535 ), //Word Alignment Wait time, when match the RXPMA will be Reset
.CH2_RXPCS_ALIGN_TIMER (65535 ), //Word Alignment Wait time, when match the RXPMA will be Reset
.CH3_RXPCS_ALIGN_TIMER (65535 ), //Word Alignment Wait time, when match the RXPMA will be Reset
.PCS_CH0_BYPASS_WORD_ALIGN ("FALSE" ), //TRUE: Lane0 Bypass Word Alignment or OUTSIDE Mode, FALSE: Lane0 No Bypass Word Alignment
.PCS_CH1_BYPASS_WORD_ALIGN ("FALSE" ), //TRUE: Lane1 Bypass Word Alignment or OUTSIDE Mode, FALSE: Lane1 No Bypass Word Alignment
.PCS_CH2_BYPASS_WORD_ALIGN ("TRUE" ), //TRUE: Lane2 Bypass Word Alignment or OUTSIDE Mode, FALSE: Lane0 No Bypass Word Alignment
.PCS_CH3_BYPASS_WORD_ALIGN ("TRUE" ), //TRUE: Lane3 Bypass Word Alignment or OUTSIDE Mode, FALSE: Lane0 No Bypass Word Alignment
.PCS_CH0_BYPASS_BONDING ("TRUE" ), //TRUE: Lane0 Bypass Channel Bonding, FALSE: Lane0 No Bypass Channel Bonding
.PCS_CH1_BYPASS_BONDING ("TRUE" ), //TRUE: Lane1 Bypass Channel Bonding, FALSE: Lane1 No Bypass Channel Bonding
.PCS_CH2_BYPASS_BONDING ("TRUE" ), //TRUE: Lane2 Bypass Channel Bonding, FALSE: Lane2 No Bypass Channel Bonding
.PCS_CH3_BYPASS_BONDING ("TRUE" ), //TRUE: Lane3 Bypass Channel Bonding, FALSE: Lane3 No Bypass Channel Bonding
.PCS_CH0_BYPASS_CTC ("FALSE" ), //TRUE: Lane0 Bypass CTC, FALSE: Lane0 No Bypass CTC
.PCS_CH1_BYPASS_CTC ("FALSE" ), //TRUE: Lane1 Bypass CTC, FALSE: Lane1 No Bypass CTC
.PCS_CH2_BYPASS_CTC ("TRUE" ), //TRUE: Lane2 Bypass CTC, FALSE: Lane2 No Bypass CTC
.PCS_CH3_BYPASS_CTC ("TRUE" ), //TRUE: Lane3 Bypass CTC, FALSE: Lane3 No Bypass CTC
.P_LX_TX_CKDIV_0 (3 ), //TX initial clock division value
.P_LX_TX_CKDIV_1 (3 ), //TX initial clock division value
.P_LX_TX_CKDIV_2 (1 ), //TX initial clock division value
.P_LX_TX_CKDIV_3 (1 ), //TX initial clock division value
.LX_RX_CKDIV_0 (3 ), //RX initial clock division value
.LX_RX_CKDIV_1 (3 ), //RX initial clock division value
.LX_RX_CKDIV_2 (1 ), //RX initial clock division value
.LX_RX_CKDIV_3 (1 ), //RX initial clock division value
.CH0_TX_PLL_SEL (0 ), //Lane0 --> 1:PLL1 0:PLL0
.CH1_TX_PLL_SEL (0 ), //Lane1 --> 1:PLL1 0:PLL0
.CH2_TX_PLL_SEL (0 ), //Lane2 --> 1:PLL1 0:PLL0
.CH3_TX_PLL_SEL (0 ), //Lane3 --> 1:PLL1 0:PLL0
.CH0_RX_PLL_SEL (0 ), //Lane0 --> 1:PLL1 0:PLL0
.CH1_RX_PLL_SEL (0 ), //Lane1 --> 1:PLL1 0:PLL0
.CH2_RX_PLL_SEL (0 ), //Lane2 --> 1:PLL1 0:PLL0
.CH3_RX_PLL_SEL (0 ), //Lane3 --> 1:PLL1 0:PLL0
.PLL_NUBER (1 ), //1 or 2
.PCS_TX_CLK_EXPLL_USE_CH0 ("TRUE" ), //
.PCS_TX_CLK_EXPLL_USE_CH1 ("TRUE" ), //
.PCS_TX_CLK_EXPLL_USE_CH2 ("TRUE" ), //
.PCS_TX_CLK_EXPLL_USE_CH3 ("TRUE" ), //
.PCS_RX_CLK_EXPLL_USE_CH0 ("TRUE" ), //
.PCS_RX_CLK_EXPLL_USE_CH1 ("TRUE" ), //
.PCS_RX_CLK_EXPLL_USE_CH2 ("FALSE" ), //
.PCS_RX_CLK_EXPLL_USE_CH3 ("FALSE" ) //
) U_IPML_HSST_RST (
//BOTH NEED
.i_pll_lock_tx_0 (i_pll_lock_tx_0 ), // input wire
.i_pll_lock_tx_1 (i_pll_lock_tx_1 ), // input wire
.i_pll_lock_tx_2 (i_pll_lock_tx_2 ), // input wire
.i_pll_lock_tx_3 (i_pll_lock_tx_3 ), // input wire
.i_pll_lock_rx_0 (i_pll_lock_rx_0 ), // input wire
.i_pll_lock_rx_1 (i_pll_lock_rx_1 ), // input wire
.i_pll_lock_rx_2 (i_pll_lock_rx_2 ), // input wire
.i_pll_lock_rx_3 (i_pll_lock_rx_3 ), // input wire
//--- User Side ---
//INNER_RST_EN is TRUE
.i_free_clk (i_free_clk ), // input wire
.i_pll_rst_0 (i_pll_rst_0 ), // input wire
.i_pll_rst_1 (i_pll_rst_1 ), // input wire
.i_wtchdg_clr_0 (i_wtchdg_clr_0 ), // input wire
.i_wtchdg_clr_1 (i_wtchdg_clr_1 ), // input wire
.i_lane_pd_0 (i_lane_pd_0 ), // input wire
.i_lane_pd_1 (i_lane_pd_1 ), // input wire
.i_lane_pd_2 (i_lane_pd_2 ), // input wire
.i_lane_pd_3 (i_lane_pd_3 ), // input wire
.i_txlane_rst_0 (i_txlane_rst_0 ), // input wire
.i_txlane_rst_1 (i_txlane_rst_1 ), // input wire
.i_txlane_rst_2 (i_txlane_rst_2 ), // input wire
.i_txlane_rst_3 (i_txlane_rst_3 ), // input wire
.i_rxlane_rst_0 (i_rxlane_rst_0 ), // input wire
.i_rxlane_rst_1 (i_rxlane_rst_1 ), // input wire
.i_rxlane_rst_2 (i_rxlane_rst_2 ), // input wire
.i_rxlane_rst_3 (i_rxlane_rst_3 ), // input wire
.i_tx_rate_chng_0 (i_tx_rate_chng_0 ), // input wire
.i_tx_rate_chng_1 (i_tx_rate_chng_1 ), // input wire
.i_tx_rate_chng_2 (i_tx_rate_chng_2 ), // input wire
.i_tx_rate_chng_3 (i_tx_rate_chng_3 ), // input wire
.i_rx_rate_chng_0 (i_rx_rate_chng_0 ), // input wire
.i_rx_rate_chng_1 (i_rx_rate_chng_1 ), // input wire
.i_rx_rate_chng_2 (i_rx_rate_chng_2 ), // input wire
.i_rx_rate_chng_3 (i_rx_rate_chng_3 ), // input wire
.i_txckdiv_0 (i_txckdiv_0 ), // input wire [1 : 0]
.i_txckdiv_1 (i_txckdiv_1 ), // input wire [1 : 0]
.i_txckdiv_2 (i_txckdiv_2 ), // input wire [1 : 0]
.i_txckdiv_3 (i_txckdiv_3 ), // input wire [1 : 0]
.i_rxckdiv_0 (i_rxckdiv_0 ), // input wire [1 : 0]
.i_rxckdiv_1 (i_rxckdiv_1 ), // input wire [1 : 0]
.i_rxckdiv_2 (i_rxckdiv_2 ), // input wire [1 : 0]
.i_rxckdiv_3 (i_rxckdiv_3 ), // input wire [1 : 0]
.i_pcs_cb_rst_0 (i_pcs_cb_rst_0 ), // input wire
.i_pcs_cb_rst_1 (i_pcs_cb_rst_1 ), // input wire
.i_pcs_cb_rst_2 (i_pcs_cb_rst_2 ), // input wire
.i_pcs_cb_rst_3 (i_pcs_cb_rst_3 ), // input wire
.i_hsst_fifo_clr_0 (i_hsst_fifo_clr_0 ), // input wire
.i_hsst_fifo_clr_1 (i_hsst_fifo_clr_1 ), // input wire
.i_hsst_fifo_clr_2 (i_hsst_fifo_clr_2 ), // input wire
.i_hsst_fifo_clr_3 (i_hsst_fifo_clr_3 ), // input wire
.i_force_rxfsm_det_0 (i_force_rxfsm_det_0 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_lsm_0 (i_force_rxfsm_lsm_0 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_cdr_0 (i_force_rxfsm_cdr_0 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_det_1 (i_force_rxfsm_det_1 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_lsm_1 (i_force_rxfsm_lsm_1 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_cdr_1 (i_force_rxfsm_cdr_1 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_det_2 (i_force_rxfsm_det_2 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_lsm_2 (i_force_rxfsm_lsm_2 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_cdr_2 (i_force_rxfsm_cdr_2 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_det_3 (i_force_rxfsm_det_3 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_lsm_3 (i_force_rxfsm_lsm_3 ), // input wire Debug signal for loopback mode
.i_force_rxfsm_cdr_3 (i_force_rxfsm_cdr_3 ), // input wire Debug signal for loopback mode
.o_wtchdg_st_0 (o_wtchdg_st_0 ), // output wire [1 : 0]
.o_wtchdg_st_1 (o_wtchdg_st_1 ), // output wire [1 : 0]
.o_pll_done_0 (o_pll_done_0 ), // output wire
.o_pll_done_1 (o_pll_done_1 ), // output wire
.o_txlane_done_0 (o_txlane_done_0 ), // output wire
.o_txlane_done_1 (o_txlane_done_1 ), // output wire
.o_txlane_done_2 (o_txlane_done_2 ), // output wire
.o_txlane_done_3 (o_txlane_done_3 ), // output wire
.o_tx_ckdiv_done_0 (o_tx_ckdiv_done_0 ), // output wire
.o_tx_ckdiv_done_1 (o_tx_ckdiv_done_1 ), // output wire
.o_tx_ckdiv_done_2 (o_tx_ckdiv_done_2 ), // output wire
.o_tx_ckdiv_done_3 (o_tx_ckdiv_done_3 ), // output wire
.o_rxlane_done_0 (o_rxlane_done_0 ), // output wire
.o_rxlane_done_1 (o_rxlane_done_1 ), // output wire
.o_rxlane_done_2 (o_rxlane_done_2 ), // output wire
.o_rxlane_done_3 (o_rxlane_done_3 ), // output wire
.o_rx_ckdiv_done_0 (o_rx_ckdiv_done_0 ), // output wire
.o_rx_ckdiv_done_1 (o_rx_ckdiv_done_1 ), // output wire
.o_rx_ckdiv_done_2 (o_rx_ckdiv_done_2 ), // output wire
.o_rx_ckdiv_done_3 (o_rx_ckdiv_done_3 ), // output wire
//INNER_RST_EN is FALSE
.i_f_pllpowerdown_0 (i_p_pllpowerdown_0 ), // input wire
.i_f_pllpowerdown_1 (i_p_pllpowerdown_1 ), // input wire
.i_f_pll_rst_0 (i_p_pll_rst_0 ), // input wire
.i_f_pll_rst_1 (i_p_pll_rst_1 ), // input wire
.i_f_lane_sync_0 (i_p_lane_sync_0 ), // input wire
.i_f_lane_sync_1 (i_p_lane_sync_1 ), // input wire
.i_f_lane_sync_en_0 (i_p_lane_sync_en_0 ), // input wire
.i_f_lane_sync_en_1 (i_p_lane_sync_en_1 ), // input wire
.i_f_rate_change_tclk_on_0 (i_p_rate_change_tclk_on_0 ), // input wire
.i_f_rate_change_tclk_on_1 (i_p_rate_change_tclk_on_1 ), // input wire
.i_f_tx_lane_pd_0 (i_p_tx_lane_pd_0 ), // input wire
.i_f_tx_lane_pd_1 (i_p_tx_lane_pd_1 ), // input wire
.i_f_tx_lane_pd_2 (i_p_tx_lane_pd_2 ), // input wire
.i_f_tx_lane_pd_3 (i_p_tx_lane_pd_3 ), // input wire
.i_f_tx_pma_rst_0 (i_p_tx_pma_rst_0 ), // input wire
.i_f_tx_pma_rst_1 (i_p_tx_pma_rst_1 ), // input wire
.i_f_tx_pma_rst_2 (i_p_tx_pma_rst_2 ), // input wire
.i_f_tx_pma_rst_3 (i_p_tx_pma_rst_3 ), // input wire
.i_f_tx_ckdiv_0 (i_p_tx_ckdiv_0 ), // input wire [1 : 0]
.i_f_tx_ckdiv_1 (i_p_tx_ckdiv_1 ), // input wire [1 : 0]
.i_f_tx_ckdiv_2 (i_p_tx_ckdiv_2 ), // input wire [1 : 0]
.i_f_tx_ckdiv_3 (i_p_tx_ckdiv_3 ), // input wire [1 : 0]
.i_f_pcs_tx_rst_0 (i_p_pcs_tx_rst_0 ), // input wire
.i_f_pcs_tx_rst_1 (i_p_pcs_tx_rst_1 ), // input wire
.i_f_pcs_tx_rst_2 (i_p_pcs_tx_rst_2 ), // input wire
.i_f_pcs_tx_rst_3 (i_p_pcs_tx_rst_3 ), // input wire
.i_f_lane_pd_0 (i_p_lane_pd_0 ), // input wire
.i_f_lane_pd_1 (i_p_lane_pd_1 ), // input wire
.i_f_lane_pd_2 (i_p_lane_pd_2 ), // input wire
.i_f_lane_pd_3 (i_p_lane_pd_3 ), // input wire
.i_f_lane_rst_0 (i_p_lane_rst_0 ), // input wire
.i_f_lane_rst_1 (i_p_lane_rst_1 ), // input wire
.i_f_lane_rst_2 (i_p_lane_rst_2 ), // input wire
.i_f_lane_rst_3 (i_p_lane_rst_3 ), // input wire
.i_f_rx_lane_pd_0 (i_p_rx_lane_pd_0 ), // input wire
.i_f_rx_lane_pd_1 (i_p_rx_lane_pd_1 ), // input wire
.i_f_rx_lane_pd_2 (i_p_rx_lane_pd_2 ), // input wire
.i_f_rx_lane_pd_3 (i_p_rx_lane_pd_3 ), // input wire
.i_f_rx_pma_rst_0 (i_p_rx_pma_rst_0 ), // input wire
.i_f_rx_pma_rst_1 (i_p_rx_pma_rst_1 ), // input wire
.i_f_rx_pma_rst_2 (i_p_rx_pma_rst_2 ), // input wire
.i_f_rx_pma_rst_3 (i_p_rx_pma_rst_3 ), // input wire
.i_f_pcs_rx_rst_0 (i_p_pcs_rx_rst_0 ), // input wire
.i_f_pcs_rx_rst_1 (i_p_pcs_rx_rst_1 ), // input wire
.i_f_pcs_rx_rst_2 (i_p_pcs_rx_rst_2 ), // input wire
.i_f_pcs_rx_rst_3 (i_p_pcs_rx_rst_3 ), // input wire
.i_f_lx_rx_ckdiv_0 (i_p_lx_rx_ckdiv_0 ), // input wire [1 : 0]
.i_f_lx_rx_ckdiv_1 (i_p_lx_rx_ckdiv_1 ), // input wire [1 : 0]
.i_f_lx_rx_ckdiv_2 (i_p_lx_rx_ckdiv_2 ), // input wire [1 : 0]
.i_f_lx_rx_ckdiv_3 (i_p_lx_rx_ckdiv_3 ), // input wire [1 : 0]
.i_f_pcs_cb_rst_0 (i_p_pcs_cb_rst_0 ), // input wire
.i_f_pcs_cb_rst_1 (i_p_pcs_cb_rst_1 ), // input wire
.i_f_pcs_cb_rst_2 (i_p_pcs_cb_rst_2 ), // input wire
.i_f_pcs_cb_rst_3 (i_p_pcs_cb_rst_3 ), // input wire
//--- Hsst Side ---
.P_PLL_READY_0 (P_PLL_READY_0 ), // input wire
.P_PLL_READY_1 (P_PLL_READY_1 ), // input wire
.P_RX_SIGDET_STATUS_0 (P_RX_SIGDET_STATUS_0 ), // input wire
.P_RX_SIGDET_STATUS_1 (P_RX_SIGDET_STATUS_1 ), // input wire
.P_RX_SIGDET_STATUS_2 (P_RX_SIGDET_STATUS_2 ), // input wire
.P_RX_SIGDET_STATUS_3 (P_RX_SIGDET_STATUS_3 ), // input wire
.P_RX_READY_0 (P_LX_CDR_ALIGN_0 ), // input wire
.P_RX_READY_1 (P_LX_CDR_ALIGN_1 ), // input wire
.P_RX_READY_2 (P_LX_CDR_ALIGN_2 ), // input wire
.P_RX_READY_3 (P_LX_CDR_ALIGN_3 ), // input wire
.P_PCS_LSM_SYNCED_0 (P_PCS_LSM_SYNCED[0] ), // input wire
.P_PCS_LSM_SYNCED_1 (P_PCS_LSM_SYNCED[1] ), // input wire
.P_PCS_LSM_SYNCED_2 (P_PCS_LSM_SYNCED[2] ), // input wire
.P_PCS_LSM_SYNCED_3 (P_PCS_LSM_SYNCED[3] ), // input wire
.P_PCS_RX_MCB_STATUS_0 (P_PCS_RX_MCB_STATUS[0] ), // input wire
.P_PCS_RX_MCB_STATUS_1 (P_PCS_RX_MCB_STATUS[1] ), // input wire
.P_PCS_RX_MCB_STATUS_2 (P_PCS_RX_MCB_STATUS[2] ), // input wire
.P_PCS_RX_MCB_STATUS_3 (P_PCS_RX_MCB_STATUS[3] ), // input wire
.P_PLLPOWERDOWN_0 (P_PLLPOWERDOWN_0 ), // output wire
.P_PLLPOWERDOWN_1 (P_PLLPOWERDOWN_1 ), // output wire
.P_PLL_RST_0 (P_PLL_RST_0 ), // output wire
.P_PLL_RST_1 (P_PLL_RST_1 ), // output wire
.P_LANE_SYNC_0 (P_LANE_SYNC_0 ), // output wire
.P_LANE_SYNC_1 (P_LANE_SYNC_1 ), // output wire
.P_LANE_SYNC_EN_0 (P_LANE_SYNC_EN_0 ), // output wire
.P_LANE_SYNC_EN_1 (P_LANE_SYNC_EN_1 ), // output wire
.P_RATE_CHANGE_TCLK_ON_0 (P_RATE_CHANGE_TCLK_ON_0 ), // output wire
.P_RATE_CHANGE_TCLK_ON_1 (P_RATE_CHANGE_TCLK_ON_1 ), // output wire
.P_TX_LANE_PD_0 (P_TX_LANE_PD_0 ), // output wire
.P_TX_LANE_PD_1 (P_TX_LANE_PD_1 ), // output wire
.P_TX_LANE_PD_2 (P_TX_LANE_PD_2 ), // output wire
.P_TX_LANE_PD_3 (P_TX_LANE_PD_3 ), // output wire
.P_TX_RATE_0 (P_TX_RATE_0 ), // output wire [2 : 0]
.P_TX_RATE_1 (P_TX_RATE_1 ), // output wire [2 : 0]
.P_TX_RATE_2 (P_TX_RATE_2 ), // output wire [2 : 0]
.P_TX_RATE_3 (P_TX_RATE_3 ), // output wire [2 : 0]
.P_TX_PMA_RST_0 (P_TX_PMA_RST_0 ), // output wire
.P_TX_PMA_RST_1 (P_TX_PMA_RST_1 ), // output wire
.P_TX_PMA_RST_2 (P_TX_PMA_RST_2 ), // output wire
.P_TX_PMA_RST_3 (P_TX_PMA_RST_3 ), // output wire
.P_PCS_TX_RST_0 (P_PCS_TX_RST_0 ), // output wire
.P_PCS_TX_RST_1 (P_PCS_TX_RST_1 ), // output wire
.P_PCS_TX_RST_2 (P_PCS_TX_RST_2 ), // output wire
.P_PCS_TX_RST_3 (P_PCS_TX_RST_3 ), // output wire
.P_RX_PMA_RST_0 (P_RX_PMA_RST_0 ), // output wire
.P_RX_PMA_RST_1 (P_RX_PMA_RST_1 ), // output wire
.P_RX_PMA_RST_2 (P_RX_PMA_RST_2 ), // output wire
.P_RX_PMA_RST_3 (P_RX_PMA_RST_3 ), // output wire
.P_LANE_PD_0 (P_LANE_PD_0 ), // output wire
.P_LANE_PD_1 (P_LANE_PD_1 ), // output wire
.P_LANE_PD_2 (P_LANE_PD_2 ), // output wire
.P_LANE_PD_3 (P_LANE_PD_3 ), // output wire
.P_LANE_RST_0 (P_LANE_RST_0 ), // output wire
.P_LANE_RST_1 (P_LANE_RST_1 ), // output wire
.P_LANE_RST_2 (P_LANE_RST_2 ), // output wire
.P_LANE_RST_3 (P_LANE_RST_3 ), // output wire
.P_RX_LANE_PD_0 (P_RX_LANE_PD_0 ), // output wire
.P_RX_LANE_PD_1 (P_RX_LANE_PD_1 ), // output wire
.P_RX_LANE_PD_2 (P_RX_LANE_PD_2 ), // output wire
.P_RX_LANE_PD_3 (P_RX_LANE_PD_3 ), // output wire
.P_PCS_RX_RST_0 (P_PCS_RX_RST_0 ), // output wire
.P_PCS_RX_RST_1 (P_PCS_RX_RST_1 ), // output wire
.P_PCS_RX_RST_2 (P_PCS_RX_RST_2 ), // output wire
.P_PCS_RX_RST_3 (P_PCS_RX_RST_3 ), // output wire
.P_RX_RATE_0 (P_RX_RATE_0 ), // output wire [2 : 0]
.P_RX_RATE_1 (P_RX_RATE_1 ), // output wire [2 : 0]
.P_RX_RATE_2 (P_RX_RATE_2 ), // output wire [2 : 0]
.P_RX_RATE_3 (P_RX_RATE_3 ), // output wire [2 : 0]
.P_PCS_CB_RST_0 (P_PCS_CB_RST_0 ), // output wire
.P_PCS_CB_RST_1 (P_PCS_CB_RST_1 ), // output wire
.P_PCS_CB_RST_2 (P_PCS_CB_RST_2 ), // output wire
.P_PCS_CB_RST_3 (P_PCS_CB_RST_3 ) // output wire
);
ipml_pcie_hsst_x2_wrapper_v1_3e U_GTP_HSST_WRAPPER (
//APB
.P_CFG_CLK (i_p_cfg_clk ), // input
.P_CFG_RST (i_p_cfg_rst ), // input
.P_CFG_PSEL (i_p_cfg_psel ), // input
.P_CFG_ENABLE (i_p_cfg_enable ), // input
.P_CFG_WRITE (i_p_cfg_write ), // input
.P_CFG_ADDR (i_p_cfg_addr ), // input [15:0]
.P_CFG_WDATA (i_p_cfg_wdata ), // input [7:0]
.P_CFG_RDATA (o_p_cfg_rdata ), // output [7:0]
.P_CFG_INT (o_p_cfg_int ), // output
.P_CFG_READY (o_p_cfg_ready ), // output
//PLL Common
.P_HSST_RST (1'b0 ), // input to be done
//PLL0
.P_PLLPOWERDOWN_0 (P_PLLPOWERDOWN_0 ), // input
.P_PLL_RST_0 (P_PLL_RST_0 ), // input
.P_LANE_SYNC_0 (P_LANE_SYNC_0 ), // input
.P_LANE_SYNC_EN_0 (P_LANE_SYNC_EN_0 ), // input to be done
.P_RATE_CHANGE_TCLK_ON_0 (P_RATE_CHANGE_TCLK_ON_0 ), // input
.P_PLL_REF_CLK_0 (1'b0 ), // input
.P_REFCK2CORE_0 (o_p_refck2core_0 ), // output
.P_PLL_READY_0 (P_PLL_READY_0 ), // output
//PLL1
.P_PLLPOWERDOWN_1 (P_PLLPOWERDOWN_1 ), // input
.P_PLL_RST_1 (P_PLL_RST_1 ), // input
.P_LANE_SYNC_1 (P_LANE_SYNC_1 ), // input
.P_LANE_SYNC_EN_1 (P_LANE_SYNC_EN_1 ), // input to be done
.P_RATE_CHANGE_TCLK_ON_1 (P_RATE_CHANGE_TCLK_ON_1 ), // input
.P_PLL_REF_CLK_1 (1'b0 ), // input
.P_REFCK2CORE_1 (o_p_refck2core_1 ), // output
.P_PLL_READY_1 (P_PLL_READY_1 ), // output
.P_REFCLKN_1 (i_p_refckn_1 ), // input
.P_REFCLKP_1 (i_p_refckp_1 ), // input
.P_TCLK2FABRIC (P_TCLK2FABRIC ), // output
.P_RCLK2FABRIC (P_RCLK2FABRIC ), // output
.P_PCS_WORD_ALIGN_EN (P_PCS_WORD_ALIGN_EN ), // input
.P_RX_POLARITY_INVERT (P_RX_POLARITY_INVERT ), // input
.P_PCS_MCB_EXT_EN (P_PCS_MCB_EXT_EN ), // input
.P_PCS_NEAREND_LOOP (P_PCS_NEAREND_LOOP ), // input
.P_PCS_FAREND_LOOP (P_PCS_FAREND_LOOP ), // input
.P_PMA_NEAREND_PLOOP (P_PMA_NEAREND_PLOOP ), // input
.P_PMA_NEAREND_SLOOP (P_PMA_NEAREND_SLOOP ), // input
.P_PMA_FAREND_PLOOP (P_PMA_FAREND_PLOOP ), // input
.P_PCS_LSM_SYNCED (P_PCS_LSM_SYNCED ), // output
.P_PCS_RX_MCB_STATUS (P_PCS_RX_MCB_STATUS ), // output
.P_TX_PMA_RST_0 (P_TX_PMA_RST_0 ), // input
.P_TX_LANE_PD_0 (P_TX_LANE_PD_0 ), // input
.P_LANE_PD_0 (P_LANE_PD_0 ), // input
.P_LANE_RST_0 (P_LANE_RST_0 ), // input
.P_RX_LANE_PD_0 (P_RX_LANE_PD_0 ), // input
.P_TX0_CLK_FR_CORE (i_p_tx0_clk_fr_core ), // input
.P_TX0_CLK2_FR_CORE (i_p_tx0_clk2_fr_core ), // input
.P_RX0_CLK_FR_CORE (i_p_rx0_clk_fr_core ), // input
.P_RX0_CLK2_FR_CORE (i_p_rx0_clk2_fr_core ), // input
.P_RX_PMA_RST_0 (P_RX_PMA_RST_0 ), // input
.P_PCS_TX_RST_0 (P_PCS_TX_RST_0 ), // input
.P_PCS_RX_RST_0 (P_PCS_RX_RST_0 ), // input
.P_PCS_CB_RST_0 (P_PCS_CB_RST_0 ), // input
.P_TX_MARGIN_0 (i_p_lx_margin_ctl_0 ), // input [2:0]
.P_TX_SWING_0 (i_p_lx_swing_ctl_0 ), // input
.P_TX_DEEMP_0 (i_p_lx_deemp_ctl_0 ), // input [1:0]
.P_RX_HIGHZ_0 (i_p_rx_highz_0 ), // input
.P_TX_BEACON_EN_0 (i_p_tx_beacon_en_0 ), // input
.P_RXGEAR_SLIP_0 (i_p_rxgear_slip_0 ), // input
.P_TX_RATE_0 (P_TX_RATE_0 ), // input [2:0]
.P_RX_RATE_0 (P_RX_RATE_0 ), // input [2:0]
.P_RX_SIGDET_STATUS_0 (P_RX_SIGDET_STATUS_0 ), // output
.P_RX_READY_0 (P_LX_CDR_ALIGN_0 ), // output
.P_RX_SATA_COMINIT_0 (o_p_lx_oob_sta_0[0] ), // output
.P_RX_SATA_COMWAKE_0 (o_p_lx_oob_sta_0[1] ), // output
.P_TX_RXDET_REQ_0 (i_p_lx_rxdct_en_0 ), // input
.P_TX_RXDET_STATUS_0 (o_p_lx_rxdct_out_0 ), // output
.P_TDATA_0 (i_p_tdata_0 ), // input [45:0]
.P_RDATA_0 (o_p_rdata_0 ), // output [46:0]
.P_TX_SDN0 (o_p_l0txn ), // output
.P_TX_SDP0 (o_p_l0txp ), // output
.P_RX_SDN0 (i_p_l0rxn ),
.P_RX_SDP0 (i_p_l0rxp ),
.P_TX_PMA_RST_1 (P_TX_PMA_RST_1 ), // input
.P_TX_LANE_PD_1 (P_TX_LANE_PD_1 ), // input
.P_LANE_PD_1 (P_LANE_PD_1 ), // input
.P_LANE_RST_1 (P_LANE_RST_1 ), // input
.P_RX_LANE_PD_1 (P_RX_LANE_PD_1 ), // input
.P_TX1_CLK_FR_CORE (i_p_tx1_clk_fr_core ), // input
.P_TX1_CLK2_FR_CORE (i_p_tx1_clk2_fr_core ), // input
.P_RX1_CLK_FR_CORE (i_p_rx1_clk_fr_core ), // input
.P_RX1_CLK2_FR_CORE (i_p_rx1_clk2_fr_core ), // input
.P_RX_PMA_RST_1 (P_RX_PMA_RST_1 ), // input
.P_PCS_TX_RST_1 (P_PCS_TX_RST_1 ), // input
.P_PCS_RX_RST_1 (P_PCS_RX_RST_1 ), // input
.P_PCS_CB_RST_1 (P_PCS_CB_RST_1 ), // input
.P_TX_MARGIN_1 (i_p_lx_margin_ctl_1 ), // input [2:1]
.P_TX_SWING_1 (i_p_lx_swing_ctl_1 ), // input
.P_TX_DEEMP_1 (i_p_lx_deemp_ctl_1 ), // input [1:1]
.P_RX_HIGHZ_1 (i_p_rx_highz_1 ), // input
.P_TX_BEACON_EN_1 (i_p_tx_beacon_en_1 ), // input
.P_RXGEAR_SLIP_1 (i_p_rxgear_slip_1 ), // input
.P_TX_RATE_1 (P_TX_RATE_1 ), // input [2:1]
.P_RX_RATE_1 (P_RX_RATE_1 ), // input [2:1]
.P_RX_SIGDET_STATUS_1 (P_RX_SIGDET_STATUS_1 ), // output
.P_RX_READY_1 (P_LX_CDR_ALIGN_1 ), // output
.P_RX_SATA_COMINIT_1 (o_p_lx_oob_sta_1[0] ), // output
.P_RX_SATA_COMWAKE_1 (o_p_lx_oob_sta_1[1] ), // output
.P_TX_RXDET_REQ_1 (i_p_lx_rxdct_en_1 ), // input
.P_TX_RXDET_STATUS_1 (o_p_lx_rxdct_out_1 ), // output
.P_TDATA_1 (i_p_tdata_1 ), // input [45:1]
.P_RDATA_1 (o_p_rdata_1 ), // output [46:1]
.P_TX_SDN1 (o_p_l1txn ), // output
.P_TX_SDP1 (o_p_l1txp ), // output
.P_RX_SDN1 (i_p_l1rxn ),
.P_RX_SDP1 (i_p_l1rxp ),
.P_TX_PMA_RST_2 (P_TX_PMA_RST_2 ), // input
.P_TX_LANE_PD_2 (P_TX_LANE_PD_2 ), // input
.P_LANE_PD_2 (P_LANE_PD_2 ), // input
.P_LANE_RST_2 (P_LANE_RST_2 ), // input
.P_RX_LANE_PD_2 (P_RX_LANE_PD_2 ), // input
.P_TX2_CLK_FR_CORE (i_p_tx2_clk_fr_core ), // input
.P_TX2_CLK2_FR_CORE (i_p_tx2_clk2_fr_core ), // input
.P_RX2_CLK_FR_CORE (i_p_rx2_clk_fr_core ), // input
.P_RX2_CLK2_FR_CORE (i_p_rx2_clk2_fr_core ), // input
.P_RX_PMA_RST_2 (P_RX_PMA_RST_2 ), // input
.P_PCS_TX_RST_2 (P_PCS_TX_RST_2 ), // input
.P_PCS_RX_RST_2 (P_PCS_RX_RST_2 ), // input
.P_PCS_CB_RST_2 (P_PCS_CB_RST_2 ), // input
.P_TX_MARGIN_2 (i_p_lx_margin_ctl_2 ), // input [2:2]
.P_TX_SWING_2 (i_p_lx_swing_ctl_2 ), // input
.P_TX_DEEMP_2 (i_p_lx_deemp_ctl_2 ), // input [1:2]
.P_RX_HIGHZ_2 (i_p_rx_highz_2 ), // input
.P_TX_BEACON_EN_2 (i_p_tx_beacon_en_2 ), // input
.P_RXGEAR_SLIP_2 (i_p_rxgear_slip_2 ), // input
.P_TX_RATE_2 (P_TX_RATE_2 ), // input [2:2]
.P_RX_RATE_2 (P_RX_RATE_2 ), // input [2:2]
.P_RX_SIGDET_STATUS_2 (P_RX_SIGDET_STATUS_2 ), // output
.P_RX_READY_2 (P_LX_CDR_ALIGN_2 ), // output
.P_RX_SATA_COMINIT_2 (o_p_lx_oob_sta_2[0] ), // output
.P_RX_SATA_COMWAKE_2 (o_p_lx_oob_sta_2[1] ), // output
.P_TX_RXDET_REQ_2 (i_p_lx_rxdct_en_2 ), // input
.P_TX_RXDET_STATUS_2 (o_p_lx_rxdct_out_2 ), // output
.P_TDATA_2 (i_p_tdata_2 ), // input [45:2]
.P_RDATA_2 (o_p_rdata_2 ), // output [46:2]
.P_TX_SDN2 (o_p_l2txn ), // output
.P_TX_SDP2 (o_p_l2txp ), // output
.P_TX_PMA_RST_3 (P_TX_PMA_RST_3 ), // input
.P_TX_LANE_PD_3 (P_TX_LANE_PD_3 ), // input
.P_LANE_PD_3 (P_LANE_PD_3 ), // input
.P_LANE_RST_3 (P_LANE_RST_3 ), // input
.P_RX_LANE_PD_3 (P_RX_LANE_PD_3 ), // input
.P_TX3_CLK_FR_CORE (i_p_tx3_clk_fr_core ), // input
.P_TX3_CLK2_FR_CORE (i_p_tx3_clk2_fr_core ), // input
.P_RX3_CLK_FR_CORE (i_p_rx3_clk_fr_core ), // input
.P_RX3_CLK2_FR_CORE (i_p_rx3_clk2_fr_core ), // input
.P_RX_PMA_RST_3 (P_RX_PMA_RST_3 ), // input
.P_PCS_TX_RST_3 (P_PCS_TX_RST_3 ), // input
.P_PCS_RX_RST_3 (P_PCS_RX_RST_3 ), // input
.P_PCS_CB_RST_3 (P_PCS_CB_RST_3 ), // input
.P_TX_MARGIN_3 (i_p_lx_margin_ctl_3 ), // input [2:3]
.P_TX_SWING_3 (i_p_lx_swing_ctl_3 ), // input
.P_TX_DEEMP_3 (i_p_lx_deemp_ctl_3 ), // input [1:3]
.P_RX_HIGHZ_3 (i_p_rx_highz_3 ), // input
.P_TX_BEACON_EN_3 (i_p_tx_beacon_en_3 ), // input
.P_RXGEAR_SLIP_3 (i_p_rxgear_slip_3 ), // input
.P_TX_RATE_3 (P_TX_RATE_3 ), // input [2:3]
.P_RX_RATE_3 (P_RX_RATE_3 ), // input [2:3]
.P_RX_SIGDET_STATUS_3 (P_RX_SIGDET_STATUS_3 ), // output
.P_RX_READY_3 (P_LX_CDR_ALIGN_3 ), // output
.P_RX_SATA_COMINIT_3 (o_p_lx_oob_sta_3[0] ), // output
.P_RX_SATA_COMWAKE_3 (o_p_lx_oob_sta_3[1] ), // output
.P_TX_RXDET_REQ_3 (i_p_lx_rxdct_en_3 ), // input
.P_TX_RXDET_STATUS_3 (o_p_lx_rxdct_out_3 ), // output
.P_TDATA_3 (i_p_tdata_3 ), // input [45:3]
.P_RDATA_3 (o_p_rdata_3 ), // output [46:3]
.P_TX_SDN3 (o_p_l3txn ), // output
.P_TX_SDP3 (o_p_l3txp ) // output
);
endmodule |
module hsstl_rst4mcrsw_v1_0 #(
parameter LINK_X1_WIDTH = 0, //1 = x4
parameter FORCE_LANE_REV = 0 //1 = Lane Reversal
)(
input wire clk,
input wire ext_rst_n,
input wire txpll_soft_rst_n,
// input wire txlane_soft_rst_n,
input wire [3:0] rxlane_soft_rst_n,
input wire wtchdg_clr,
input wire ltssm_in_recovery,
input wire rate, // 0 = 2.5GT/s; 1 = 5.0GT/s
input wire [1:0] link_num, // 0 = x4, 2=x2, 1=x1
input wire link_num_flag,
input wire P_PLL_LOCK,
input wire P_LX_ALOS_STA_0,
input wire P_LX_ALOS_STA_1,
input wire P_LX_ALOS_STA_2,
input wire P_LX_ALOS_STA_3,
input wire P_LX_CDR_ALIGN_0,
input wire P_LX_CDR_ALIGN_1,
input wire P_LX_CDR_ALIGN_2,
input wire P_LX_CDR_ALIGN_3,
input wire [3:0] P_PCS_LSM_SYNCED,
output wire [3:0] tx_fsm,
output wire s_P_PLL_LOCK_deb,
output wire pll_lock_wtchdg_rst_n,
output wire [3:0] P_PMA_LANE_PD,
output wire [3:0] P_PMA_LANE_RST,
output wire P_HSST_RST,
output wire P_PLLPOWERDOWN_0,
output wire P_PLLPOWERDOWN_1,
output wire P_PLL_RST_0,
output wire P_PLL_RST_1,
output wire [3:0] P_PMA_TX_PD,
output wire P_RATE_CHG_TXPCLK_ON_0,
output wire P_RATE_CHG_TXPCLK_ON_1,
output wire P_LANE_SYNC_0,
output wire P_LANE_SYNC_EN_0,
output wire P_LANE_SYNC_1,
output wire [2:0] P_PMA_TX_RATE_0,
output wire [2:0] P_PMA_TX_RATE_1,
output wire [2:0] P_PMA_TX_RATE_2,
output wire [2:0] P_PMA_TX_RATE_3,
output wire P_PMA_TX_RST_0,
output wire P_PMA_TX_RST_1,
output wire P_PMA_TX_RST_2,
output wire P_PMA_TX_RST_3,
output wire P_PCS_TX_RST_0,
output wire P_PCS_TX_RST_1,
output wire P_PCS_TX_RST_2,
output wire P_PCS_TX_RST_3,
output wire tx_rst_done,
output wire [3:0] rx_main_fsm,
output wire [3:0] rx_init_fsm0,
output wire [3:0] rx_init_fsm1,
output wire [3:0] rx_init_fsm2,
output wire [3:0] rx_init_fsm3,
output wire [3:0] s_PCS_LSM_SYNCED,
output wire [3:0] s_LX_ALOS_STA_deb,
output wire [3:0] s_LX_CDR_ALIGN_deb,
output wire [3:0] init_done,
output wire [3:0] P_PMA_RX_PD,
output wire P_PMA_RX_RST_0,
output wire P_PMA_RX_RST_1,
output wire P_PMA_RX_RST_2,
output wire P_PMA_RX_RST_3,
output wire P_PCS_RX_RST_0,
output wire P_PCS_RX_RST_1,
output wire P_PCS_RX_RST_2,
output wire P_PCS_RX_RST_3,
output wire [2:0] P_LX_RX_RATE_0,
output wire [2:0] P_LX_RX_RATE_1,
output wire [2:0] P_LX_RX_RATE_2,
output wire [2:0] P_LX_RX_RATE_3,
output wire [3:0] P_TX_PD_CLKPATH,
output wire [3:0] P_TX_PD_PISO,
output wire [3:0] P_TX_PD_DRIVER,
output wire [3:0] P_PCS_CB_RST,
output wire rate_done,
output wire [3:0] hsst_ch_ready,
input mac_clk_req_n,
output phy_clk_req_n
);
localparam RST_CNTR_WIDTH = 16;
`ifdef IPSL_PCIE_SPEEDUP_SIM
localparam RST_CNTR_VALUE = 16'h000C;
`else
localparam RST_CNTR_VALUE = 16'hC000;
`endif
wire rst_n;
wire s_rate;
wire s_ltssm_in_recovery;
// rst_n cross sync and debounce
hsst_rst_cross_sync_v1_0 #(.RST_CNTR_WIDTH(RST_CNTR_WIDTH), .RST_CNTR_VALUE(RST_CNTR_VALUE))
ext_rstn_debounce (.clk(clk), .rstn_in(ext_rst_n), .rstn_out(ext_rst_n_sync));
ipsl_pcie_sync_v1_0 mac_clk_req_n_sync (.clk(clk), .rst_n(ext_rst_n_sync), .sig_async(mac_clk_req_n), .sig_synced(mac_clk_req_n_s));
assign phy_clk_req_n = mac_clk_req_n_s; //assume that ref clk source can be controlled directly
assign rst_n = ext_rst_n_sync & (~ mac_clk_req_n_s);
//******************************************************************************************************************************************
ipsl_pcie_sync_v1_0 rate_multi_sw_sync (.clk(clk), .rst_n(rst_n), .sig_async(rate), .sig_synced(s_rate));
ipsl_pcie_sync_v1_0 st_recvr_multi_sw_sync (.clk(clk), .rst_n(rst_n), .sig_async(ltssm_in_recovery), .sig_synced(s_ltssm_in_recovery));
hsstl_rst4mcrsw_tx_v1_0 hsst_tx_rst_mcrsw(
.clk (clk ),
.rst_n (rst_n ),
.txpll_soft_rst_n (txpll_soft_rst_n ),
// .txlane_soft_rst_n (txlane_soft_rst_n ),
.wtchdg_clr (wtchdg_clr ),
.P_PLL_LOCK (P_PLL_LOCK ),
// .ltssm_in_recovery (s_ltssm_in_recovery ),
.rate (s_rate ),
.tx_fsm (tx_fsm ),
.s_P_PLL_LOCK_deb (s_P_PLL_LOCK_deb ),
.pll_lock_wtchdg_rst_n (pll_lock_wtchdg_rst_n),
.P_PMA_LANE_PD (P_PMA_LANE_PD ),
.P_PMA_LANE_RST (P_PMA_LANE_RST ),
.P_HSST_RST (P_HSST_RST ),
.P_PLLPOWERDOWN_0 (P_PLLPOWERDOWN_0 ),
.P_PLLPOWERDOWN_1 (P_PLLPOWERDOWN_1 ),
.P_PLL_RST_0 (P_PLL_RST_0 ),
.P_PLL_RST_1 (P_PLL_RST_1 ),
.P_PMA_TX_PD (P_PMA_TX_PD ),
.P_RATE_CHG_TXPCLK_ON_0 (P_RATE_CHG_TXPCLK_ON_0),
.P_RATE_CHG_TXPCLK_ON_1 (P_RATE_CHG_TXPCLK_ON_1),
.P_LANE_SYNC_0 (P_LANE_SYNC_0 ),
.P_LANE_SYNC_EN_0 (P_LANE_SYNC_EN_0 ),
.P_LANE_SYNC_1 (P_LANE_SYNC_1 ),
.P_PMA_TX_RATE_0 (P_PMA_TX_RATE_0 ),
.P_PMA_TX_RATE_1 (P_PMA_TX_RATE_1 ),
.P_PMA_TX_RATE_2 (P_PMA_TX_RATE_2 ),
.P_PMA_TX_RATE_3 (P_PMA_TX_RATE_3 ),
.P_PMA_TX_RST_0 (P_PMA_TX_RST_0 ),
.P_PMA_TX_RST_1 (P_PMA_TX_RST_1 ),
.P_PMA_TX_RST_2 (P_PMA_TX_RST_2 ),
.P_PMA_TX_RST_3 (P_PMA_TX_RST_3 ),
.P_PCS_TX_RST_0 (P_PCS_TX_RST_0 ),
.P_PCS_TX_RST_1 (P_PCS_TX_RST_1 ),
.P_PCS_TX_RST_2 (P_PCS_TX_RST_2 ),
.P_PCS_TX_RST_3 (P_PCS_TX_RST_3 ),
.P_TX_PD_CLKPATH (P_TX_PD_CLKPATH ),
.P_TX_PD_PISO (P_TX_PD_PISO ),
.P_TX_PD_DRIVER (P_TX_PD_DRIVER ),
.tx_rst_done (tx_rst_done )
);
hsstl_rst4mcrsw_rx_v1_0 #(
.LINK_X1_WIDTH (LINK_X1_WIDTH ),
.FORCE_LANE_REV (FORCE_LANE_REV )
) hsst_rx_rst_mcrsw (
.clk (clk ),
.rst_n (rst_n ),
.rxlane_soft_rst_n (rxlane_soft_rst_n ),
.tx_rst_done (tx_rst_done ),
.P_LX_ALOS_STA_0 (P_LX_ALOS_STA_0 ),
.P_LX_ALOS_STA_1 (P_LX_ALOS_STA_1 ),
.P_LX_ALOS_STA_2 (P_LX_ALOS_STA_2 ),
.P_LX_ALOS_STA_3 (P_LX_ALOS_STA_3 ),
.P_LX_CDR_ALIGN_0 (P_LX_CDR_ALIGN_0 ),
.P_LX_CDR_ALIGN_1 (P_LX_CDR_ALIGN_1 ),
.P_LX_CDR_ALIGN_2 (P_LX_CDR_ALIGN_2 ),
.P_LX_CDR_ALIGN_3 (P_LX_CDR_ALIGN_3 ),
.P_PCS_LSM_SYNCED (P_PCS_LSM_SYNCED ),
.ltssm_in_recovery (s_ltssm_in_recovery ),
.rate (s_rate ),
.link_num (link_num ),
.link_num_flag (link_num_flag ),
.rx_main_fsm (rx_main_fsm ),
.rx_init_fsm0 (rx_init_fsm0 ),
.rx_init_fsm1 (rx_init_fsm1 ),
.rx_init_fsm2 (rx_init_fsm2 ),
.rx_init_fsm3 (rx_init_fsm3 ),
.s_PCS_LSM_SYNCED (s_PCS_LSM_SYNCED ),
.s_LX_ALOS_STA_deb (s_LX_ALOS_STA_deb ),
.s_LX_CDR_ALIGN_deb (s_LX_CDR_ALIGN_deb ),
.init_done (init_done ),
.P_PMA_RX_PD (P_PMA_RX_PD ),
.P_PMA_RX_RST_0 (P_PMA_RX_RST_0 ),
.P_PMA_RX_RST_1 (P_PMA_RX_RST_1 ),
.P_PMA_RX_RST_2 (P_PMA_RX_RST_2 ),
.P_PMA_RX_RST_3 (P_PMA_RX_RST_3 ),
.P_PCS_RX_RST_0 (P_PCS_RX_RST_0 ),
.P_PCS_RX_RST_1 (P_PCS_RX_RST_1 ),
.P_PCS_RX_RST_2 (P_PCS_RX_RST_2 ),
.P_PCS_RX_RST_3 (P_PCS_RX_RST_3 ),
.P_LX_RX_RATE_0 (P_LX_RX_RATE_0 ),
.P_LX_RX_RATE_1 (P_LX_RX_RATE_1 ),
.P_LX_RX_RATE_2 (P_LX_RX_RATE_2 ),
.P_LX_RX_RATE_3 (P_LX_RX_RATE_3 ),
.P_PCS_CB_RST (P_PCS_CB_RST ),
.rate_done (rate_done ),
.hsst_ch_ready (hsst_ch_ready )
);
endmodule |
module hsstl_rst4mcrsw_rx_v1_0 #(
parameter LINK_X1_WIDTH = 0, // 1 = x4
parameter FORCE_LANE_REV = 0 //1 = Lane Reversal
)(
input wire clk,
input wire rst_n,
input wire [3:0] rxlane_soft_rst_n,
input wire tx_rst_done,
input wire [1:0] link_num,
input wire link_num_flag,
input wire P_LX_ALOS_STA_0,
input wire P_LX_ALOS_STA_1,
input wire P_LX_ALOS_STA_2,
input wire P_LX_ALOS_STA_3,
input wire P_LX_CDR_ALIGN_0,
input wire P_LX_CDR_ALIGN_1,
input wire P_LX_CDR_ALIGN_2,
input wire P_LX_CDR_ALIGN_3,
input wire [3:0] P_PCS_LSM_SYNCED,
input wire ltssm_in_recovery,
input wire rate, // 0 = 2.5GT/s; 1 = 5.0GT/s
output wire [3:0] rx_main_fsm,
output wire [3:0] rx_init_fsm0,
output wire [3:0] rx_init_fsm1,
output wire [3:0] rx_init_fsm2,
output wire [3:0] rx_init_fsm3,
output wire [3:0] s_PCS_LSM_SYNCED,
output wire [3:0] s_LX_ALOS_STA_deb,
output wire [3:0] s_LX_CDR_ALIGN_deb,
output wire [3:0] init_done,
output wire [3:0] P_PMA_RX_PD,
output wire P_PMA_RX_RST_0,
output wire P_PMA_RX_RST_1,
output wire P_PMA_RX_RST_2,
output wire P_PMA_RX_RST_3,
output wire P_PCS_RX_RST_0,
output wire P_PCS_RX_RST_1,
output wire P_PCS_RX_RST_2,
output wire P_PCS_RX_RST_3,
output wire [2:0] P_LX_RX_RATE_0,
output wire [2:0] P_LX_RX_RATE_1,
output wire [2:0] P_LX_RX_RATE_2,
output wire [2:0] P_LX_RX_RATE_3,
output wire [3:0] P_PCS_CB_RST,
output wire rate_done,
output wire [3:0] hsst_ch_ready
);
localparam LOSS_DEB_RISE_CNTR_WIDTH = 12;
localparam LOSS_DEB_RISE_CNTR_VALUE = 4;
localparam CDR_ALIGN_DEB_RISE_CNTR_WIDTH = 12;
localparam CDR_ALIGN_DEB_RISE_CNTR_VALUE = 2048;
localparam WORD_ALIGN_DEB_RISE_CNTR_WIDTH = 11;
localparam WORD_ALIGN_DEB_RISE_CNTR_VALUE = 1024;
wire [3:0] P_LX_ALOS_STA ;
wire [3:0] P_LX_CDR_ALIGN ;
wire [3:0] s_LX_ALOS_STA ;
wire [3:0] s_LX_CDR_ALIGN ;
wire main_rst_align ;
wire rx_rate_change_rst ;
wire [3:0] rx_init_fsm_buf [3:0] ;
wire P_PMA_RX_PD_m ;
wire [3:0] P_PMA_RX_RST ;
wire [3:0] P_PCS_RX_RST ;
wire [2:0] P_LX_RX_RATE ;
reg [1:0] link_num_synced ;
reg link_num_flag_synced_d;
wire [3:0] main_done ;
wire main_pll_loss_rst;
wire P_RX_LANE_POWERUP;
wire [3:0] P_RX_PMA_RSTN ;
wire [3:0] P_PCS_RX_RSTN ;
wire [3:0] P_PCS_CB_RSTN ;
wire [1:0] P_LX_RX_CKDIV;
wire [3:0] P_PCS_CB_RST_I;
wire P_LX_RX_CKDIV_DYNSEL;
wire cur_rate;
// Link Number sync
ipsl_pcie_sync_v1_0 link_num_sync (.clk(clk), .rst_n(rst_n), .sig_async(link_num_flag), .sig_synced(link_num_flag_synced));
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
link_num_flag_synced_d <= 1'b0;
link_num_synced <= 2'd0;
end
else begin
link_num_flag_synced_d <= link_num_flag_synced;
if (link_num_flag_synced_d ^ link_num_flag_synced)
link_num_synced <= link_num;
end
// Lane Reversal
assign P_LX_ALOS_STA = {P_LX_ALOS_STA_3, P_LX_ALOS_STA_2, P_LX_ALOS_STA_1, P_LX_ALOS_STA_0};
assign P_LX_CDR_ALIGN = {P_LX_CDR_ALIGN_3, P_LX_CDR_ALIGN_2, P_LX_CDR_ALIGN_1, P_LX_CDR_ALIGN_0};
// Initial part
assign rx_init_fsm0 = rx_init_fsm_buf[0];
assign rx_init_fsm1 = rx_init_fsm_buf[1];
assign rx_init_fsm2 = rx_init_fsm_buf[2];
assign rx_init_fsm3 = rx_init_fsm_buf[3];
generate
genvar i;
for(i=0;i<4;i=i+1)begin
hsstl_rst4mcrsw_rx_init_v1_0 hsst_rst4mcrsw_rx_init(
.clk (clk ),
.rst_n (rst_n ),
.rxlane_soft_rst_n (rxlane_soft_rst_n[i] ),
.ltssm_in_recovery (ltssm_in_recovery ),
.P_LX_ALOS_STA (P_LX_ALOS_STA[i] ),
.P_LX_CDR_ALIGN (P_LX_CDR_ALIGN[i] ),
.P_PCS_LSM_SYNCED (P_PCS_LSM_SYNCED[i] ),
.main_rst_align (main_rst_align ),
.main_pll_loss_rst (main_pll_loss_rst ),
.cur_rate (cur_rate),
.rx_init_fsm (rx_init_fsm_buf[i] ),
.s_LX_ALOS_STA (s_LX_ALOS_STA[i] ),
.s_LX_CDR_ALIGN (s_LX_CDR_ALIGN[i] ),
.s_PCS_LSM_SYNCED (s_PCS_LSM_SYNCED[i] ),
.s_LX_ALOS_STA_deb (s_LX_ALOS_STA_deb[i] ),
.s_LX_CDR_ALIGN_deb (s_LX_CDR_ALIGN_deb[i] ),
// .P_PMA_RX_PD (P_PMA_RX_PD_m ),
// .P_PMA_RX_RST (P_PMA_RX_RST[i] ),
.P_RX_PLL_RSTN (), //NC
// .P_PCS_RX_RST (P_PCS_RX_RST[i] ),
.P_RX_LANE_POWERUP (P_RX_LANE_POWERUP ),
.P_RX_PMA_RSTN (P_RX_PMA_RSTN[i] ),
.P_PCS_RX_RSTN (P_PCS_RX_RSTN[i] ),
.P_PCS_CB_RSTN (P_PCS_CB_RSTN[i] ),
.init_done (init_done[i] )
);
end
endgenerate
assign P_PMA_RX_PD_m = ~P_RX_LANE_POWERUP;
assign P_PMA_RX_RST = ~P_RX_PMA_RSTN | {4{P_LX_RX_CKDIV_DYNSEL}};
assign P_PCS_RX_RST = ~P_PCS_RX_RSTN;
assign P_PCS_CB_RST_I = ~P_PCS_CB_RSTN;
// Main part
hsstl_rst4mcrsw_rx_rst_fsm_v1_0 #(
.FORCE_LANE_REV (FORCE_LANE_REV )
)rx_rst_fsm_multi_sw_lane(
.clk (clk ),
.rst_n (rst_n ),
.tx_rst_done (tx_rst_done ),
// .link_num (link_num_synced ),
.ltssm_in_recovery (ltssm_in_recovery ),
.rate (rate ),
.init_done (init_done ),
.rx_main_fsm (rx_main_fsm ),
.main_rst_align (main_rst_align ),
.main_pll_loss_rst (main_pll_loss_rst ),
.loss_of_signal (s_LX_ALOS_STA),
// .P_PMA_RX_PD (P_PMA_RX_PD_m ),
// .P_LX_RX_RATE (P_LX_RX_RATE ),
.P_RX_LANE_POWERUP (P_RX_LANE_POWERUP ),
.P_LX_RX_CKDIV (P_LX_RX_CKDIV ),
.P_LX_RX_CKDIV_DYNSEL (P_LX_RX_CKDIV_DYNSEL), //NC
.rate_done (rate_done ),
.main_done (main_done )
);
assign P_LX_RX_RATE = (P_LX_RX_CKDIV == 2'd0) ? 3'd3 : 3'd2;
assign cur_rate = (P_LX_RX_CKDIV == 2'd0);
wire [3:0] mask_bits = (link_num_synced == 1) ? 4'b1110 : ((link_num_synced == 2) ? 4'b1100 : 4'b0000);
assign P_PMA_RX_PD = {4{P_PMA_RX_PD_m}} | mask_bits;
assign P_PMA_RX_RST_0 = P_PMA_RX_RST[0];
assign P_PMA_RX_RST_1 = P_PMA_RX_RST[1];
assign P_PMA_RX_RST_2 = P_PMA_RX_RST[2] ;
assign P_PMA_RX_RST_3 = P_PMA_RX_RST[3];
assign P_PCS_RX_RST_0 = ((|main_done) | (|s_LX_CDR_ALIGN[3:1] & s_LX_ALOS_STA[0])) ? &P_PCS_RX_RST :P_PCS_RX_RST[0];
assign P_PCS_RX_RST_1 = ((|main_done) | (|s_LX_CDR_ALIGN[3:2] & s_LX_ALOS_STA[1])) ? &P_PCS_RX_RST[3:1] : P_PCS_RX_RST[1];
assign P_PCS_RX_RST_2 = ((|main_done) | (|s_LX_CDR_ALIGN[3] & s_LX_ALOS_STA[2]))? &P_PCS_RX_RST[3:2] : P_PCS_RX_RST[2] ;
assign P_PCS_RX_RST_3 = P_PCS_RX_RST[3];
assign P_PCS_CB_RST[0] = ((|main_done) | (|s_LX_CDR_ALIGN[3:1] & s_LX_ALOS_STA[0])) ? &P_PCS_CB_RST_I :P_PCS_CB_RST_I[0];
assign P_PCS_CB_RST[1] = ((|main_done) | (|s_LX_CDR_ALIGN[3:2] & s_LX_ALOS_STA[1])) ? &P_PCS_CB_RST_I[3:1] : P_PCS_CB_RST_I[1];
assign P_PCS_CB_RST[2] = ((|main_done) | (|s_LX_CDR_ALIGN[3] & s_LX_ALOS_STA[2]))? &P_PCS_CB_RST_I[3:2] : P_PCS_CB_RST_I[2] ;
assign P_PCS_CB_RST[3] = P_PCS_CB_RST_I[3];
assign P_LX_RX_RATE_0 = P_LX_RX_RATE;
assign P_LX_RX_RATE_1 = P_LX_RX_RATE;
assign P_LX_RX_RATE_2 = P_LX_RX_RATE;
assign P_LX_RX_RATE_3 = P_LX_RX_RATE;
assign hsst_ch_ready = main_done ;
endmodule |
module hsstl_phy_mac_rdata_proc #(
parameter EN_CONTI_SKP_REPLACE = 1'b0
)(
input pclk,
input rst_n,
input [46:0] P_RDATA,
input rx_det_done,
input lx_rxdct_out_d,
output reg [31:0] phy_mac_rxdata,
output reg [3:0] phy_mac_rxdatak,
output reg [2:0] phy_mac_rxstatus
);
wire ctc_underflow;
localparam K30_7 = 8'hFE;
localparam K28_0 = 8'h1C;
localparam K28_5 = 8'hBC;
always @(posedge pclk or negedge rst_n)
begin
if (!rst_n)
phy_mac_rxstatus <= 3'b0;
else if (rx_det_done)
phy_mac_rxstatus <= {1'b0, {2{lx_rxdct_out_d}}};
else begin
//*******************************************************************************************
if (P_RDATA[9] | P_RDATA[20] | P_RDATA[31] | P_RDATA[42])
phy_mac_rxstatus[2:0] <= 3'b100; //decode error
// else if (P_RDATA[8] | P_RDATA[19] | P_RDATA[30] | P_RDATA[41])
// phy_mac_rxstatus[2:0] <= 3'b111; //disparity error
// else if (P_RDATA[46:44] == 3'b011) //continuous skip del
// phy_mac_rxstatus[2:0] <= 3'b010;
else if ((P_RDATA[46:44] == 3'b100) | (P_RDATA[46:44] == 3'b101)) //bridge / CTC over flow
phy_mac_rxstatus[2:0] <= 3'b101; //CTC buffer overflow
else if ((P_RDATA[46:44] == 3'b110) | (P_RDATA[46:44] == 3'b111)) //bridge under flow
phy_mac_rxstatus[2:0] <= 3'b110; //CTC buffer underflow
else if (P_RDATA[8] | P_RDATA[19] | P_RDATA[30] | P_RDATA[41])
phy_mac_rxstatus[2:0] <= 3'b111; //disparity error
else
phy_mac_rxstatus[2:0] <= P_RDATA[46:44];
end
end
assign ctc_underflow = (P_RDATA[46:44] == 3'b111) | (P_RDATA[46:44] == 3'b110);
assign cond1_for_conti_skp_del = ~ (P_RDATA[9] | P_RDATA[20] | P_RDATA[31] | P_RDATA[42] | P_RDATA[8] | P_RDATA[19] | P_RDATA[30] | P_RDATA[41]); //no decoder/disparity errs
assign cond2_for_conti_skp_del = (P_RDATA[46:44] == 3'b011) & (EN_CONTI_SKP_REPLACE == 1'b1);
assign cond3_for_conti_skp_del = ({P_RDATA[10], P_RDATA[7:0] } == {1'b1, K28_5}) &
({P_RDATA[21], P_RDATA[18:11]} == {1'b1, K28_0}) &
({P_RDATA[32], P_RDATA[29:22]} == {1'b1, K28_0}) &
({P_RDATA[43], P_RDATA[40:33]} == {1'b1, K28_5});
assign all_match_conti_skp_del = cond1_for_conti_skp_del & cond2_for_conti_skp_del & cond3_for_conti_skp_del;
always@(posedge pclk or negedge rst_n)
begin
if(!rst_n)
begin
phy_mac_rxdatak[3 :0 ] <= 4'b0;
phy_mac_rxdata[31 :0 ] <= 32'b0;
end
else
begin
{phy_mac_rxdatak[3], phy_mac_rxdata[31:24]} <= ( ctc_underflow | P_RDATA[42]) ? {1'b1, K30_7} : (all_match_conti_skp_del ? {1'b1, K28_0} : {P_RDATA[43], P_RDATA[40:33]});
{phy_mac_rxdatak[2], phy_mac_rxdata[23:16]} <= ( ctc_underflow | P_RDATA[31]) ? {1'b1, K30_7} : (all_match_conti_skp_del ? {1'b1, K28_5} : {P_RDATA[32], P_RDATA[29:22]});
{phy_mac_rxdatak[1], phy_mac_rxdata[15:8] } <= ( ctc_underflow | P_RDATA[20]) ? {1'b1, K30_7} : {P_RDATA[21], P_RDATA[18:11]};
{phy_mac_rxdatak[0], phy_mac_rxdata[7:0] } <= ( ctc_underflow | P_RDATA[9] ) ? {1'b1, K30_7} : {P_RDATA[10], P_RDATA[7:0] };
end
end
endmodule |
module hsst_rst_wtchdg_v1_0 #(
parameter ACTIVE_HIGH = 0, // 0 : active@low, 1 : active@high
parameter WTCHDG_CNTR1_WIDTH = 10, //(2**(WTCHDG_CNTR1_WIDTH-1)) = 512
parameter WTCHDG_CNTR2_WIDTH = 10 //watchdog time = (2**(WTCHDG_CNTR2_WIDTH-1))*(2**(WTCHDG_CNTR1_WIDTH-1)) = 256k;
//watchdog reset length = (2**(WTCHDG_CNTR1_WIDTH-1))
)(
input wire clk,
input wire rst_n,
input wire wtchdg_clr,
input wire wtchdg_in,
output reg wtchdg_rst_n
);
wire wtchdg_in_mux;
reg [WTCHDG_CNTR1_WIDTH-1:0] cnt_1;
reg [WTCHDG_CNTR2_WIDTH-1:0] cnt_2;
assign wtchdg_in_mux = (ACTIVE_HIGH == 1'b1) ? ~wtchdg_in : wtchdg_in;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
cnt_1 <= {WTCHDG_CNTR1_WIDTH{1'b0}};
end
else if(cnt_1[WTCHDG_CNTR1_WIDTH-1] | wtchdg_in_mux | wtchdg_clr)
begin
cnt_1 <= {WTCHDG_CNTR1_WIDTH{1'b0}};
end
else
begin
cnt_1 <= cnt_1 + { {(WTCHDG_CNTR1_WIDTH-1){1'b0}}, 1'b1};
end
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
cnt_2 <= {WTCHDG_CNTR2_WIDTH{1'b0}};
end
else if(wtchdg_clr | wtchdg_in_mux | (cnt_2[WTCHDG_CNTR2_WIDTH-1] & cnt_2[0]) )
begin
cnt_2 <= {WTCHDG_CNTR2_WIDTH{1'b0}};
end
else if(cnt_1[WTCHDG_CNTR1_WIDTH-1])
begin
cnt_2 <= cnt_2 + { {(WTCHDG_CNTR2_WIDTH-1){1'b0}}, 1'b1};
end
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
wtchdg_rst_n <= 1'b1;
end
else if(cnt_2[WTCHDG_CNTR2_WIDTH-1])
begin
wtchdg_rst_n <= 1'b0;
end
else
begin
wtchdg_rst_n <= 1'b1;
end
end
endmodule |
module hsst_rst_cross_sync_v1_0 #(
parameter RST_CNTR_WIDTH = 16,
parameter RST_CNTR_VALUE = 16'hC000
)(
// Reset and Clock
input clk,
input rstn_in,
output reg rstn_out
);
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
reg rs1;
reg rs2;
wire rstn_inner;
reg [3:0] rstn_inner_d;
reg rstn_sync;
reg [RST_CNTR_WIDTH-1:0] cnt_rst;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
always@(posedge clk or negedge rstn_in)
begin
if(!rstn_in)
begin
rs1<=0;
rs2<=0;
end
else
begin
rs1<=1;
rs2<=rs1;
end
end
assign rstn_inner = rs2;
`ifdef IPSL_PCIE_SPEEDUP_SIM
initial begin
rstn_inner_d = 4'hf; //CLM reg default value is 1
rstn_sync = 1'b1;
cnt_rst = {RST_CNTR_WIDTH{1'b1}};
rstn_out = 1'b1;
end
`endif
always @(posedge clk or negedge rstn_inner)
begin
if (!rstn_inner) begin
rstn_inner_d <= 4'h0; //CLM reg default value is 1
rstn_sync <= 1'b0;
cnt_rst <= {RST_CNTR_WIDTH{1'b1}};
rstn_out <= 1'b0;
end
else begin
rstn_inner_d <= {rstn_inner_d[2:0], rstn_inner};
if (rstn_inner_d[3:2] == 2'd0)
rstn_sync <= 1'b0;
else
rstn_sync <= 1'b1;
if (~rstn_sync) begin
cnt_rst <= {RST_CNTR_WIDTH{1'b1}};
rstn_out <= 1'b0;
end
else if (cnt_rst == RST_CNTR_VALUE)
rstn_out <= 1'b1;
else begin
rstn_out <= 1'b0;
cnt_rst <= cnt_rst + {{(RST_CNTR_WIDTH-1){1'b0}}, 1'b1};
end
end
end
endmodule |
module hsstl_rst4mcrsw_rx_init_v1_0(
input wire clk,
input wire rst_n,
input wire rxlane_soft_rst_n,
input wire ltssm_in_recovery,
input wire P_LX_ALOS_STA,
input wire P_LX_CDR_ALIGN,
input wire P_PCS_LSM_SYNCED,
input wire main_rst_align,
input wire main_pll_loss_rst,
input wire cur_rate,
output wire [3:0] rx_init_fsm,
output wire s_LX_ALOS_STA,
output wire s_LX_CDR_ALIGN,
output wire s_PCS_LSM_SYNCED,
output wire s_LX_ALOS_STA_deb,
output wire s_LX_CDR_ALIGN_deb,
input wire P_RX_LANE_POWERUP,
output wire P_RX_PMA_RSTN,
output wire P_RX_PLL_RSTN,
output wire P_PCS_RX_RSTN,
output wire P_PCS_CB_RSTN,
output wire init_done
);
localparam LOSS_DEB_RISE_CNTR_WIDTH = 12;
localparam LOSS_DEB_RISE_CNTR_VALUE = 4;
localparam CDR_ALIGN_DEB_RISE_CNTR_WIDTH = 12;
localparam CDR_ALIGN_DEB_RISE_CNTR_VALUE = 2048;
wire rx_rst_n ;
assign rx_rst_n = rst_n & rxlane_soft_rst_n;
// ALOS, CDR_ALIGN, PCS_LSM_SYNCED sync per lane
ipsl_pcie_sync_v1_0 loss_signal_multi_sw_sync (.clk(clk), .rst_n(rx_rst_n), .sig_async(P_LX_ALOS_STA), .sig_synced(s_LX_ALOS_STA));
ipsl_pcie_sync_v1_0 cdr_align_multi_sw_sync (.clk(clk), .rst_n(rx_rst_n), .sig_async(P_LX_CDR_ALIGN), .sig_synced(s_LX_CDR_ALIGN));
ipsl_pcie_sync_v1_0 word_align_multi_sw_sync (.clk(clk), .rst_n(rx_rst_n), .sig_async(P_PCS_LSM_SYNCED), .sig_synced(s_PCS_LSM_SYNCED));
// ALOS, CDR_ALIGN debounce per lane
hsst_rst_debounce_v1_0 #(.RISE_CNTR_WIDTH(LOSS_DEB_RISE_CNTR_WIDTH), .RISE_CNTR_VALUE(LOSS_DEB_RISE_CNTR_VALUE), .ACTIVE_HIGH(1))
loss_signal_multi_sw_deb(.clk(clk), .rst_n(rx_rst_n), .signal_b(s_LX_ALOS_STA), .signal_deb(s_LX_ALOS_STA_deb));
hsst_rst_debounce_v1_0 #(.RISE_CNTR_WIDTH(CDR_ALIGN_DEB_RISE_CNTR_WIDTH), .RISE_CNTR_VALUE(CDR_ALIGN_DEB_RISE_CNTR_VALUE))
cdr_align_multi_sw_deb (.clk(clk), .rst_n(rx_rst_n), .signal_b(s_LX_CDR_ALIGN), .signal_deb(s_LX_CDR_ALIGN_deb));
// RX Reset FSM
hsstl_rst4mcrsw_rx_rst_initfsm_v1_0 rx_rst_initfsm_multi_sw_lane(
.clk (clk ),
.rst_n (rx_rst_n ),
.P_RX_LANE_POWERUP (P_RX_LANE_POWERUP ),
.main_rst_align (main_rst_align ),
.main_pll_loss_rst (main_pll_loss_rst ),
.loss_signal (s_LX_ALOS_STA ),
.cdr_align (s_LX_CDR_ALIGN ),
.word_align (s_PCS_LSM_SYNCED ),
.cur_rate (cur_rate ),
.rx_init_fsm (rx_init_fsm ),
.P_RX_PMA_RSTN (P_RX_PMA_RSTN ),
.P_RX_PLL_RSTN (P_RX_PLL_RSTN ),
.P_PCS_RX_RSTN (P_PCS_RX_RSTN ),
.P_PCS_CB_RSTN (P_PCS_CB_RSTN ),
.init_done (init_done )
);
endmodule |
module hsstl_rst4mcrsw_tx_rst_fsm_v1_1(
input wire clk,
input wire rst_n,
input wire pll_rst_n,
input wire pll_ready,
input wire clk_remove,
input wire rate,
output reg [3:0] hsst_fsm,
output reg P_PMA_LANE_PD, //for each lane
output reg P_PMA_LANE_RST, //for each lane
output reg P_HSST_RST,
output reg P_PLLPOWERDOWN,
output reg P_PLL_RST,
output reg P_PMA_TX_PD,
output reg P_PMA_TX_RST,
output reg P_RATE_CHG_TXPCLK_ON,
output reg P_LANE_SYNC_EN,
output reg P_LANE_SYNC,
output reg [2:0] P_PMA_TX_RATE,
output reg P_PCS_TX_RST,
output reg P_TX_PD_CLKPATH,
output reg P_TX_PD_PISO,
output reg P_TX_PD_DRIVER,
output reg tx_rst_done
);
localparam CNTR_WIDTH = 12 ;
localparam PLL_PWRDONE_CNTR_VALUE = 4*1023;
localparam PLL_RST_CNTR_VALUE = 4*256;
localparam PMA_TX_RST_CNTR_VALUE = 64;
localparam BONDING_RST_RELEASE_VALUE = 128;
localparam BONDING_SYNC_EN_POS_VALUE = BONDING_RST_RELEASE_VALUE + 64;
localparam BONDING_SYNC_POS_VALUE = BONDING_SYNC_EN_POS_VALUE + 64;
localparam BONDING_SYNC_NEG_VALUE = BONDING_SYNC_POS_VALUE + 16;
localparam BONDING_SYNC_EN_NEG_VALUE = BONDING_SYNC_NEG_VALUE + 64;
localparam TX_PCS_RST_CNTR_VALUE = 16;
localparam RATE_SYNC_EN_POS_VALUE = 0;
localparam RATE_RCHANGE_NEG_VALUE = RATE_SYNC_EN_POS_VALUE + 56;
localparam RATE_RST_POS_VALUE = RATE_RCHANGE_NEG_VALUE + 30;
localparam RATE_UPPDATE_RATE_CNT_VALUE = RATE_RST_POS_VALUE + 8;
localparam RATE_SYNC_NEG_VALUE = RATE_UPPDATE_RATE_CNT_VALUE + 8;
localparam RATE_RST_NEG_VALUE = RATE_SYNC_NEG_VALUE + 8;
localparam RATE_RCHANGE_POS_VALUE = RATE_RST_NEG_VALUE + 30;
localparam RATE_SYNC_EN_NEG_VALUE = RATE_RCHANGE_POS_VALUE + 48;
localparam HSST_IDLE = 4'd0;
localparam PMA_PD_UP = 4'd1;
localparam PMA_PLL_RST = 4'd2;
localparam PMA_PLL_LOCK = 4'd3;
localparam PMA_TX_RST = 4'd4;
localparam PMA_BONDING = 4'd5;
localparam TX_PCS_RST = 4'd6;
localparam TX_RST_DONE = 4'd7;
localparam TX_RATE_ONLY = 4'd8;
reg [CNTR_WIDTH-1 : 0] cntr;
reg [1:0] rate_ff;
reg rate_chng;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
rate_ff <= 2'd0;
rate_chng <= 1'b0;
end
else
begin
rate_ff[0] <= rate;
rate_ff[1] <= rate_ff[0];
rate_chng <= ^rate_ff;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
hsst_fsm <= HSST_IDLE;
cntr <= {CNTR_WIDTH{1'b0}};
P_PMA_LANE_PD <= 1'b1; //powerdown
P_PMA_LANE_RST <= 1'b1; //in reset
P_HSST_RST <= 1'b1; //in reset
P_PLLPOWERDOWN <= 1'b1;
P_PLL_RST <= 1'b1;
P_PMA_TX_PD <= 1'b1;
P_PMA_TX_RST <= 1'b1;
P_RATE_CHG_TXPCLK_ON <= 1'b1;
P_TX_PD_CLKPATH <= 1'b1;
P_TX_PD_DRIVER <= 1'b1;
P_LANE_SYNC <= 1'b0;
P_LANE_SYNC_EN <= 1'b0;
P_PMA_TX_RATE <= 3'd2; //010, half rate
P_PCS_TX_RST <= 1'b1;
P_TX_PD_PISO <= 1'b1;
tx_rst_done <= 1'b0;
end
else
begin
case (hsst_fsm)
HSST_IDLE :
begin
P_PMA_LANE_PD <= 1'b1;
P_PMA_LANE_RST <= 1'b1;
P_HSST_RST <= 1'b1; //reset
P_PLLPOWERDOWN <= 1'b1; //power down
P_PLL_RST <= 1'b1; //reset
P_PMA_TX_PD <= 1'b1;
P_PMA_TX_RST <= 1'b1;
P_RATE_CHG_TXPCLK_ON <= 1'b1;
P_LANE_SYNC <= 1'b0;
P_LANE_SYNC_EN <= 1'b0;
P_PMA_TX_RATE <= 3'd2; //010, half rate
P_PCS_TX_RST <= 1'b1; //reset
tx_rst_done <= 1'b0;
if (cntr == PLL_PWRDONE_CNTR_VALUE) begin //>40us
hsst_fsm <= PMA_PD_UP;
cntr <= {CNTR_WIDTH{1'b0}};
end
else
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},1'b1};
end
PMA_PD_UP :
begin
P_PLLPOWERDOWN <= 1'b0; //power power up
if (cntr == PLL_RST_CNTR_VALUE) //>1us
begin
hsst_fsm <= PMA_PLL_RST;
cntr <= {CNTR_WIDTH{1'b0}};
end
else
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},1'b1};
end
PMA_PLL_RST :
begin
P_HSST_RST <= 1'b0; //release reset
//----------------------------------------------------
//default setting for signals
P_PMA_LANE_PD <= 1'b1;
P_PMA_LANE_RST <= 1'b1;
P_PLL_RST <= 1'b1; //reset
P_PMA_TX_PD <= 1'b1;
P_PMA_TX_RST <= 1'b1;
P_RATE_CHG_TXPCLK_ON <= 1'b1;
P_LANE_SYNC <= 1'b0;
P_LANE_SYNC_EN <= 1'b0;
P_PMA_TX_RATE <= rate ? 3'd3 : 3'd2;
P_PCS_TX_RST <= 1'b1; //reset
tx_rst_done <= 1'b0;
hsst_fsm <= PMA_PLL_LOCK;
end
PMA_PLL_LOCK :
begin
P_PLL_RST <= 1'b0; //release pll reset
if (pll_ready)
begin
if(cntr == PMA_TX_RST_CNTR_VALUE)
begin
hsst_fsm <= PMA_TX_RST;
cntr <= {CNTR_WIDTH{1'b0}};
end
else
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},1'b1};
end
else
hsst_fsm <= PMA_PLL_LOCK;
end
PMA_TX_RST:
begin
P_TX_PD_CLKPATH <= 1'b0;
if(cntr == PMA_TX_RST_CNTR_VALUE)
begin
P_PMA_TX_RST <= 1'b0;
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},1'b1};
end
else if(cntr == PMA_TX_RST_CNTR_VALUE*2)
begin
P_TX_PD_PISO <= 1'b0;
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},1'b1};
end
else if(cntr == PMA_TX_RST_CNTR_VALUE*3)
begin
P_TX_PD_DRIVER <= 1'b0;
cntr <= {CNTR_WIDTH{1'b0}};
hsst_fsm <= PMA_BONDING;
end
else
begin
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},1'b1};
hsst_fsm <= PMA_TX_RST;
end
end
PMA_BONDING :
begin
// releae power down
P_PMA_LANE_PD <= 1'b0;
P_PMA_TX_PD <= 1'b0;
if ((~pll_ready) | (~pll_rst_n))
begin
hsst_fsm <= PMA_PLL_RST;
cntr <= {CNTR_WIDTH{1'b0}};
end
else if (cntr == BONDING_SYNC_EN_NEG_VALUE)
begin
hsst_fsm <= TX_PCS_RST;
cntr <= {CNTR_WIDTH{1'b0}};
end
else
begin
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},1'b1};
end
if (cntr == BONDING_RST_RELEASE_VALUE) begin //>1us
P_PMA_LANE_RST <= 1'b0;
// P_PMA_TX_RST <= 1'b0;
end
else if (cntr == BONDING_SYNC_EN_POS_VALUE) //>500us
P_LANE_SYNC_EN <= 1'b1;
else if (cntr == BONDING_SYNC_POS_VALUE) //>500us
P_LANE_SYNC <= 1'b1;
else if (cntr == BONDING_SYNC_NEG_VALUE)
P_LANE_SYNC <= 1'b0;
else if (cntr == BONDING_SYNC_EN_NEG_VALUE) begin
P_LANE_SYNC_EN <= 1'b0;
end
end
TX_PCS_RST :
begin
if ((~pll_ready) | (~pll_rst_n))
begin
hsst_fsm <= PMA_PLL_RST;
cntr <= {CNTR_WIDTH{1'b0}};
end
else if (cntr == TX_PCS_RST_CNTR_VALUE)
begin
hsst_fsm <= TX_RST_DONE;
cntr <= {CNTR_WIDTH{1'b0}};
end
else
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},1'b1};
end
TX_RST_DONE :
begin
P_PCS_TX_RST <= 1'b0;
tx_rst_done <= 1'b1;
if (clk_remove)
hsst_fsm <= HSST_IDLE;
else if ((~pll_ready) | (~pll_rst_n))
begin
hsst_fsm <= PMA_PLL_RST;
cntr <= {CNTR_WIDTH{1'b0}};
end
else if (rate_chng)
hsst_fsm <= TX_RATE_ONLY;
else
hsst_fsm <= TX_RST_DONE;
end
TX_RATE_ONLY :
begin
if ((~pll_ready) | (~pll_rst_n)) begin
hsst_fsm <= PMA_PLL_RST;
cntr <= {CNTR_WIDTH{1'b0}};
end
else if (cntr == RATE_SYNC_EN_NEG_VALUE)
begin
hsst_fsm <= TX_RST_DONE;
cntr <= {CNTR_WIDTH{1'b0}};
end
else
begin
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},1'b1};
end
if (cntr == RATE_SYNC_EN_POS_VALUE)
P_LANE_SYNC_EN <= 1'b1;
else if (cntr == RATE_RCHANGE_NEG_VALUE)
P_RATE_CHG_TXPCLK_ON <= 1'b0;
else if (cntr == RATE_RST_POS_VALUE) begin
P_PMA_TX_RST <= 1'b1;
P_LANE_SYNC <= 1'b1;
end
else if (cntr == RATE_UPPDATE_RATE_CNT_VALUE)
P_PMA_TX_RATE <= rate ? 3'd3 : 3'd2;
else if (cntr == RATE_SYNC_NEG_VALUE)
P_LANE_SYNC <= 1'b0;
else if (cntr == RATE_RST_NEG_VALUE)
P_PMA_TX_RST <= 1'b0;
else if (cntr == RATE_RCHANGE_POS_VALUE) begin
P_PCS_TX_RST <= 1'b1;
P_RATE_CHG_TXPCLK_ON <= 1'b1;
end
else if (cntr == RATE_SYNC_EN_NEG_VALUE)
P_LANE_SYNC_EN <= 1'b0;
end
default :
begin
hsst_fsm <= HSST_IDLE;
end
endcase
end
end
endmodule |
module hsstl_rst4mcrsw_tx_v1_0(
input wire clk,
input wire rst_n,
input wire txpll_soft_rst_n,
// input wire txlane_soft_rst_n,
input wire wtchdg_clr,
input wire P_PLL_LOCK,
// input wire ltssm_in_recovery,
input wire rate, // 0 = 2.5GT/s; 1 = 5.0GT/s
output wire [3:0] tx_fsm,
output wire s_P_PLL_LOCK_deb,
output wire pll_lock_wtchdg_rst_n,
output wire [3:0] P_PMA_LANE_PD,
output wire [3:0] P_PMA_LANE_RST,
output wire P_HSST_RST,
output wire P_PLLPOWERDOWN_0,
output wire P_PLLPOWERDOWN_1,
output wire P_PLL_RST_0,
output wire P_PLL_RST_1,
output wire [3:0] P_PMA_TX_PD,
output wire P_RATE_CHG_TXPCLK_ON_0,
output wire P_RATE_CHG_TXPCLK_ON_1,
output wire P_LANE_SYNC_0,
output wire P_LANE_SYNC_EN_0,
output wire P_LANE_SYNC_1,
output wire [2:0] P_PMA_TX_RATE_0,
output wire [2:0] P_PMA_TX_RATE_1,
output wire [2:0] P_PMA_TX_RATE_2,
output wire [2:0] P_PMA_TX_RATE_3,
output wire P_PMA_TX_RST_0,
output wire P_PMA_TX_RST_1,
output wire P_PMA_TX_RST_2,
output wire P_PMA_TX_RST_3,
output wire P_PCS_TX_RST_0,
output wire P_PCS_TX_RST_1,
output wire P_PCS_TX_RST_2,
output wire P_PCS_TX_RST_3,
output wire [3:0] P_TX_PD_CLKPATH,
output wire [3:0] P_TX_PD_PISO,
output wire [3:0] P_TX_PD_DRIVER,
output wire tx_rst_done
);
localparam PLL_LOCK_RISE_CNTR_WIDTH = 12 ;
localparam PLL_LOCK_RISE_CNTR_VALUE = 2048;
localparam PLL_LOCK_WTCHDG_CNTR1_WIDTH = 10 ;
localparam PLL_LOCK_WTCHDG_CNTR2_WIDTH = 10 ;
wire P_TX_PD_CLKPATH0;
wire P_TX_PD_PISO0;
wire P_TX_PD_DRIVER0;
wire s_P_PLL_LOCK;
wire tx_rst_fsm_rst_n;
assign tx_rst_fsm_rst_n = rst_n & pll_lock_wtchdg_rst_n;
ipsl_pcie_sync_v1_0 pll_lock_multi_sw_sync (.clk(clk), .rst_n(rst_n), .sig_async(P_PLL_LOCK), .sig_synced(s_P_PLL_LOCK));
hsst_rst_debounce_v1_0 #(.RISE_CNTR_WIDTH(PLL_LOCK_RISE_CNTR_WIDTH), .RISE_CNTR_VALUE(PLL_LOCK_RISE_CNTR_VALUE))
pll_lock_multi_sw_deb (.clk(clk), .rst_n(rst_n), .signal_b(s_P_PLL_LOCK), .signal_deb(s_P_PLL_LOCK_deb));
hsst_rst_wtchdg_v1_0 #(.WTCHDG_CNTR1_WIDTH(PLL_LOCK_WTCHDG_CNTR1_WIDTH), .WTCHDG_CNTR2_WIDTH(PLL_LOCK_WTCHDG_CNTR2_WIDTH))
pll_lock_multi_sw_wtchdg (.clk(clk), .rst_n(rst_n), .wtchdg_clr(wtchdg_clr), .wtchdg_in(s_P_PLL_LOCK), .wtchdg_rst_n(pll_lock_wtchdg_rst_n));
hsstl_rst4mcrsw_tx_rst_fsm_v1_1 tx_rst_fsm_multi_sw_lane(
.clk (clk ),
.rst_n (tx_rst_fsm_rst_n ),
.pll_rst_n (txpll_soft_rst_n ),
//.lane_rst_n (txlane_soft_rst_n ),
.pll_ready (s_P_PLL_LOCK_deb ),
//.ltssm_in_recovery (ltssm_in_recovery ),
.clk_remove (1'b0),
.rate (rate ),
.hsst_fsm (tx_fsm ),
.P_PMA_LANE_PD (P_PMA_LANE_PD_0 ),
.P_PMA_LANE_RST (P_PMA_LANE_RST_0 ),
.P_HSST_RST (P_HSST_RST ),
.P_PLLPOWERDOWN (P_PLLPOWERDOWN_0 ),
.P_PLL_RST (P_PLL_RST_0 ),
.P_PMA_TX_PD (P_PMA_TX_PD_0 ),
.P_PMA_TX_RST (P_PMA_TX_RST_0 ),
.P_RATE_CHG_TXPCLK_ON (P_RATE_CHG_TXPCLK_ON_0 ),
.P_LANE_SYNC (P_LANE_SYNC_0 ),
.P_LANE_SYNC_EN (P_LANE_SYNC_EN_0),
.P_PMA_TX_RATE (P_PMA_TX_RATE_0 ),
.P_TX_PD_CLKPATH (P_TX_PD_CLKPATH0 ),
.P_TX_PD_PISO (P_TX_PD_PISO0 ),
.P_TX_PD_DRIVER (P_TX_PD_DRIVER0 ),
.P_PCS_TX_RST (P_PCS_TX_RST_0 ),
.tx_rst_done (tx_rst_done )
);
assign P_PLLPOWERDOWN_1 = P_PLLPOWERDOWN_0;//1'b1; //pll1 powerdown
assign P_PLL_RST_1 = P_PLL_RST_0;//1'b1; //pll1 in reset
assign P_RATE_CHG_TXPCLK_ON_1 = 1'b1;
assign P_LANE_SYNC_1 = 1'b0;
assign P_PMA_TX_RATE_1 = P_PMA_TX_RATE_0;
assign P_PMA_TX_RATE_2 = P_PMA_TX_RATE_0;
assign P_PMA_TX_RATE_3 = P_PMA_TX_RATE_0;
assign P_PMA_TX_RST_1 = P_PMA_TX_RST_0;
assign P_PMA_TX_RST_2 = P_PMA_TX_RST_0;
assign P_PMA_TX_RST_3 = P_PMA_TX_RST_0;
assign P_PMA_LANE_PD = {4{P_PMA_LANE_PD_0}};
assign P_PMA_LANE_RST = {4{P_PMA_LANE_RST_0}};
assign P_PMA_TX_PD = {4{P_PMA_TX_PD_0}};
assign P_PCS_TX_RST_1 = P_PCS_TX_RST_0;
assign P_PCS_TX_RST_2 = P_PCS_TX_RST_0;
assign P_PCS_TX_RST_3 = P_PCS_TX_RST_0;
assign P_TX_PD_CLKPATH = {4{P_TX_PD_CLKPATH0}};
assign P_TX_PD_PISO = {4{P_TX_PD_PISO0}};
assign P_TX_PD_DRIVER = {4{P_TX_PD_DRIVER0}};
endmodule |
module hsstl_rst4mcrsw_rx_rst_initfsm_v1_0(
input wire clk,
input wire rst_n,
input wire P_RX_LANE_POWERUP,
input wire main_rst_align,
input wire main_pll_loss_rst,
input wire loss_signal,
input wire cdr_align,
input wire word_align,
input wire cur_rate, //added on 20180927, to fix issue (XA-65) about EIOS data receive during link down
output reg [3:0] rx_init_fsm,
output reg P_RX_PMA_RSTN,
output reg P_RX_PLL_RSTN,
output reg P_PCS_RX_RSTN,
output reg P_PCS_CB_RSTN,
output reg init_done
);
localparam CNTR_WIDTH = 17;
localparam INIT_ALIGN_WAIT_TIMR_WIDTH = 8;
localparam RX_PMA_CNTR_VALUE = 150;//1.28us
localparam RX_PLL_CNTR_VALUE = 1000;//10us@100Mhz
localparam RX_PCS_CNTR_VALUE = 64;
localparam WORD_ALIGN_WAITCNTR_VALUE = 16*2;
localparam CDR_ALIGN_WAITCNTR_VALUE = 18*2;
localparam ALOS_WAITCNTR_VALUE = 20*2;
localparam RX_INIT_START = 4'd0;
localparam RX_INIT_PMA_RST = 4'd1;
localparam RX_INIT_LOSS_DOWN = 4'd2;
localparam RX_INIT_PLL_RST = 4'd3;
localparam RX_INIT_CDR_LOCK = 4'd4;
localparam RX_INIT_PCS_RST = 4'd5;
localparam RX_INIT_WORD_ALIGN = 4'd6;
localparam RX_INIT_ALIGN_WAIT = 4'd7;
localparam RX_INIT_DONE = 4'd8;
localparam RX_REALIGN_PCS_BOND = 4'd9;
reg [CNTR_WIDTH-1 : 0] init_cntr;
reg [INIT_ALIGN_WAIT_TIMR_WIDTH-1 : 0] init_align_wait_timr;
reg init_realign;
reg word_align_d;
wire word_align_pos;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
word_align_d <= 1'b0;
else
word_align_d <= word_align;
end
assign word_align_pos = word_align & ~word_align_d;
// INIT SM
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
init_cntr <= {CNTR_WIDTH{1'b0}};
rx_init_fsm <= RX_INIT_START;
P_RX_PMA_RSTN <= 1'b0;
P_RX_PLL_RSTN <= 1'b0;
P_PCS_RX_RSTN <= 1'b0;
P_PCS_CB_RSTN <= 1'b0;
init_align_wait_timr <= {INIT_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
init_realign <= 1'b0;
init_done <= 1'b0;
end
else
begin
case (rx_init_fsm)
RX_INIT_START :
begin
init_cntr <= {CNTR_WIDTH{1'b0}};
P_RX_PMA_RSTN <= 1'b0;
P_RX_PLL_RSTN <= 1'b0;
P_PCS_RX_RSTN <= 1'b0;
P_PCS_CB_RSTN <= 1'b0;
init_realign <= 1'b0;
init_done <= 1'b0;
if (P_RX_LANE_POWERUP)
rx_init_fsm <= RX_INIT_PMA_RST;
else
rx_init_fsm <= RX_INIT_START;
end
RX_INIT_PMA_RST :
begin
P_RX_PMA_RSTN <= 1'b0;
P_RX_PLL_RSTN <= 1'b0;
P_PCS_RX_RSTN <= 1'b0;
P_PCS_CB_RSTN <= 1'b0;
init_realign <= 1'b0;
init_done <= 1'b0;
if (init_cntr == RX_PMA_CNTR_VALUE)
begin
rx_init_fsm <= RX_INIT_LOSS_DOWN;
P_RX_PMA_RSTN <= 1'b1;
init_cntr <= {CNTR_WIDTH{1'b0}};
end
else
begin
rx_init_fsm <= RX_INIT_PMA_RST;
P_RX_PMA_RSTN <= 1'b0;
init_cntr <= init_cntr + {{CNTR_WIDTH-1{1'b0}}, 1'b1};
end
end
RX_INIT_LOSS_DOWN :
begin
P_RX_PLL_RSTN <= 1'b0;
P_PCS_RX_RSTN <= 1'b0;
init_done <= 1'b0;
P_PCS_CB_RSTN <= 1'b0;
if (~loss_signal)
rx_init_fsm <= RX_INIT_CDR_LOCK;
else
rx_init_fsm <= RX_INIT_LOSS_DOWN;
end
RX_INIT_CDR_LOCK :
begin
if (loss_signal)
rx_init_fsm <= RX_INIT_LOSS_DOWN ;
else if (cdr_align)
rx_init_fsm <= RX_INIT_PCS_RST;
else
rx_init_fsm <= RX_INIT_CDR_LOCK;
end
RX_INIT_PCS_RST :
begin
// P_PCS_RX_RSTN <= 1'b0;
init_done <= 1'b0;
init_align_wait_timr <= {INIT_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
if (loss_signal)
begin
rx_init_fsm <= RX_INIT_LOSS_DOWN;
init_cntr <= {CNTR_WIDTH{1'b0}};
end
else if (~cdr_align)
begin
rx_init_fsm <= RX_INIT_PLL_RST;
init_cntr <= {CNTR_WIDTH{1'b0}};
end
else //if (init_cntr == RX_PCS_CNTR_VALUE)
begin
if (init_realign)
rx_init_fsm <= RX_INIT_WORD_ALIGN;
else
rx_init_fsm <= RX_INIT_ALIGN_WAIT;
P_PCS_RX_RSTN <= 1'b1;
P_PCS_CB_RSTN <= 1'b1;
init_cntr <= {CNTR_WIDTH{1'b0}};
end
//else
//begin
// rx_init_fsm <= RX_INIT_PCS_RST;
// P_PCS_RX_RSTN <= 1'b0;
// init_cntr <= init_cntr + {{CNTR_WIDTH-1{1'b0}}, 1'b1};
//end
end
RX_INIT_WORD_ALIGN :
begin
init_realign <= 1'b0;
if (~cdr_align | loss_signal)
init_align_wait_timr <= {INIT_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
else if (&init_align_wait_timr)
init_align_wait_timr <= init_align_wait_timr;
else
init_align_wait_timr <= init_align_wait_timr + {{INIT_ALIGN_WAIT_TIMR_WIDTH-1{1'b0}}, 1'b1};
if (loss_signal)
rx_init_fsm <= RX_INIT_LOSS_DOWN;
else if (~cdr_align)
rx_init_fsm <= RX_INIT_PLL_RST;
else if (&init_align_wait_timr & (~word_align))
begin
rx_init_fsm <= RX_INIT_START;
init_done <= 1'b0;
end
else if (word_align)
begin
rx_init_fsm <= RX_INIT_DONE;
init_done <= 1'b1;
init_cntr <= {CNTR_WIDTH{1'b0}};
end
else
rx_init_fsm <= RX_INIT_WORD_ALIGN;
end
RX_INIT_ALIGN_WAIT :
begin
if (~cdr_align | loss_signal)
init_align_wait_timr <= {INIT_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
else if (&init_align_wait_timr)
init_align_wait_timr <= init_align_wait_timr;
else
init_align_wait_timr <= init_align_wait_timr + {{INIT_ALIGN_WAIT_TIMR_WIDTH-1{1'b0}}, 1'b1};
if (loss_signal)
rx_init_fsm <= RX_INIT_LOSS_DOWN;
else if (~cdr_align)
rx_init_fsm <= RX_INIT_PLL_RST;
else if (&init_align_wait_timr & (~word_align))
begin
rx_init_fsm <= RX_INIT_PLL_RST;
init_realign <= 1'b1;
init_done <= 1'b0;
init_align_wait_timr <= {INIT_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
end
else if (word_align)
begin
rx_init_fsm <= RX_INIT_DONE;
init_done <= 1'b1;
init_cntr <= {CNTR_WIDTH{1'b0}};
end
else
rx_init_fsm <= RX_INIT_ALIGN_WAIT;
end
RX_INIT_DONE :
begin
// init_cntr <= {CNTR_WIDTH{1'b0}};
if (~word_align)
begin
rx_init_fsm <= RX_INIT_PCS_RST;
init_cntr <= {CNTR_WIDTH{1'b0}};
end
//else if (main_pll_loss_rst)
// begin
// rx_init_fsm <= RX_INIT_LOSS_DOWN;
// P_RX_PLL_RSTN <= 1'b0;
// P_PCS_RX_RSTN <= 1'b0;
// P_PCS_CB_RSTN <= 1'b0;
// init_done <= 1'b0;
// end
else if (main_rst_align)
begin
rx_init_fsm <= RX_REALIGN_PCS_BOND;
// P_PCS_RX_RSTN <= 1'b0;
P_PCS_CB_RSTN <= 1'b0;
init_done <= 1'b0;
end
else
rx_init_fsm <= RX_INIT_DONE;
end
RX_REALIGN_PCS_BOND :
begin
P_PCS_CB_RSTN <= 1'b1;
if(word_align_pos)
begin
init_done <= 1'b1;
rx_init_fsm <= RX_INIT_DONE;
end
else
begin
init_done <= 1'b0;
rx_init_fsm <= RX_REALIGN_PCS_BOND;
end
end
default:
begin
init_cntr <= {CNTR_WIDTH{1'b0}};
rx_init_fsm <= RX_INIT_START;
P_RX_PMA_RSTN <= 1'b0;
P_RX_PLL_RSTN <= 1'b0;
P_PCS_RX_RSTN <= 1'b0;
P_PCS_CB_RSTN <= 1'b0;
init_align_wait_timr <= {INIT_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
init_realign <= 1'b0;
init_done <= 1'b0;
end
endcase
end
end
endmodule |
module hsst_rst_debounce_v1_0 #(
parameter RISE_CNTR_WIDTH = 12,
parameter RISE_CNTR_VALUE = 12'd2048,
parameter ACTIVE_HIGH = 1'b0 // 0 : active@low, 1 : active@high
)(
input wire clk,
input wire rst_n,
input wire signal_b,
output wire signal_deb
);
wire signal_b_mux;
reg signal_b_ff;
reg signal_b_neg;
reg signal_deb_pre;
reg [RISE_CNTR_WIDTH-1:0] rise_cnt;
assign signal_b_mux = (ACTIVE_HIGH == 1'b1) ? ~signal_b : signal_b;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
signal_b_ff <= 1'b0;
signal_b_neg <= 1'b0;
end
else
begin
signal_b_ff <= signal_b_mux;
signal_b_neg <= ~signal_b_mux & signal_b_ff;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
rise_cnt <= {RISE_CNTR_WIDTH{1'b0}};
else if (signal_b_neg)
rise_cnt <= {RISE_CNTR_WIDTH{1'b0}};
else if (rise_cnt == RISE_CNTR_VALUE)
rise_cnt <= rise_cnt;
else if (signal_b_mux)
rise_cnt <= rise_cnt + {{RISE_CNTR_WIDTH-1{1'b0}}, 1'b1};
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
signal_deb_pre <= 1'b0;
else if (signal_b_neg)
signal_deb_pre <= 1'b0;
else if (rise_cnt == RISE_CNTR_VALUE)
signal_deb_pre <= 1'b1;
end
assign signal_deb = (ACTIVE_HIGH == 1'b1) ? ~signal_deb_pre : signal_deb_pre;
endmodule |
module hsstl_rst4mcrsw_rx_rst_fsm_v1_0 #(
parameter FORCE_LANE_REV = 0 //1 = Lane Reversal
)(
input wire clk,
input wire rst_n,
input wire [3:0] loss_of_signal,
input wire tx_rst_done,
input wire ltssm_in_recovery,
input wire rate,
input wire [3:0] init_done,
output reg [3:0] rx_main_fsm,
output reg main_rst_align,
output reg main_pll_loss_rst,
output reg P_RX_LANE_POWERUP,
output reg P_LX_RX_CKDIV_DYNSEL,
output reg [1:0] P_LX_RX_CKDIV,
output reg rate_done,
output reg [3:0] main_done
);
localparam PMA_RX_PD_CNT_VALUE = 4095;
localparam CNTR_WIDTH = 16;
localparam MAIN_ALIGN_WAIT_TIMR_WIDTH = 10;
`ifdef IPSL_PCIE_SPEEDUP_SIM
localparam RX_CKDIV_DYNSEL_SW_CNTR_NEG_VALUE = 4*512;
`else
localparam RX_CKDIV_DYNSEL_SW_CNTR_NEG_VALUE = 64*512;
`endif
`ifdef IPSL_PCIE_SPEEDUP_SIM
localparam RX_CKDIV_DYNSEL_SPEED_DONE = 3*512;
`else
localparam RX_CKDIV_DYNSEL_SPEED_DONE = 16*512;
`endif
localparam RX_CKDIV_SW_CNTR_VALUE = 4*260;
localparam RX_MAIN_IDLE = 4'd0 ;
localparam RX_MAIN_INIT = 4'd1 ;
localparam RX_MAIN_INIT_WAIT = 4'd2 ;
localparam RX_MAIN_ALIGN_RST = 4'd3 ;
localparam RX_MAIN_ALIGN_WAIT = 4'd4 ;
localparam RX_MAIN_ALIGN_WAIT2 = 4'd5 ;
localparam RX_MAIN_RST_DONE = 4'd6 ;
localparam RX_MAIN_RECOVERY = 4'd7 ;
localparam RX_MAIN_CKDIV = 4'd8 ;
reg rate_chng;
reg [1:0] rate_ff;
wire all_lane_rst_done;
wire mstr_init_done;
reg [CNTR_WIDTH-1 : 0] main_cntr;
reg [MAIN_ALIGN_WAIT_TIMR_WIDTH-1 : 0] main_align_wait_timr;
reg rate_done_r;
reg rate_done_r_d;
wire [2:0] active_lane_num ;
assign mstr_init_done = (FORCE_LANE_REV ==1) ? init_done[3] : init_done[0];
assign all_lane_rst_done = &(loss_of_signal | init_done) & ~(&loss_of_signal);
assign active_lane_num =init_done[3] + init_done[2] + init_done[1] + init_done[0];
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
rate_ff <= 2'd0;
rate_chng <= 1'b0;
end
else
begin
rate_ff[0] <= rate;
rate_ff[1] <= rate_ff[0];
rate_chng <= (rate_ff[1] == P_LX_RX_CKDIV[0]) ;
end
end
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
rate_done_r_d <= 1'b0;
rate_done <= 1'b0;
end
else begin
rate_done_r_d <= rate_done_r;
rate_done <= rate_done_r_d | rate_done_r;
end
end
// MAIN SM
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
main_cntr <= {CNTR_WIDTH{1'b0}};
rx_main_fsm <= RX_MAIN_IDLE;
P_RX_LANE_POWERUP <= 1'b0;
P_LX_RX_CKDIV_DYNSEL <= 1'b0;
P_LX_RX_CKDIV <= 2'b01;
rate_done_r <= 1'b0;
main_done <= 4'd0;
main_rst_align <= 1'b0;
main_pll_loss_rst <= 1'b0;
main_align_wait_timr <= {MAIN_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
end
else
begin
case (rx_main_fsm)
RX_MAIN_IDLE :
begin
if (tx_rst_done)
if(main_cntr == PMA_RX_PD_CNT_VALUE)
begin
rx_main_fsm <= RX_MAIN_INIT;
main_cntr <= {CNTR_WIDTH{1'b0}};
end
else
begin
rx_main_fsm <= RX_MAIN_IDLE;
main_cntr <= main_cntr + {{CNTR_WIDTH-1{1'b0}}, 1'b1};
end
else
rx_main_fsm <= RX_MAIN_IDLE;
// main_cntr <= {CNTR_WIDTH{1'b0}};
P_RX_LANE_POWERUP <= 1'b0;
P_LX_RX_CKDIV_DYNSEL <= 1'b0;
P_LX_RX_CKDIV <= rate ? 2'b00: 2'b01 ;
rate_done_r <= 1'b0;
main_done <= 4'd0;
main_rst_align <= 1'b0;
main_pll_loss_rst <= 1'b0;
main_align_wait_timr <= {MAIN_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
end
RX_MAIN_INIT :
begin
P_RX_LANE_POWERUP <= 1'b1;
main_pll_loss_rst <= 1'b0;
main_align_wait_timr <= {MAIN_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
main_done <= 4'd0;
if(rate_chng )
rx_main_fsm <= RX_MAIN_CKDIV;
else if (~main_pll_loss_rst & |init_done)
rx_main_fsm <= RX_MAIN_INIT_WAIT;
else
rx_main_fsm <= RX_MAIN_INIT;
end
RX_MAIN_INIT_WAIT :
begin
main_done <= 4'd0;
if(rate_chng )
rx_main_fsm <= RX_MAIN_CKDIV;
else
begin
if (&main_align_wait_timr)
main_align_wait_timr <= main_align_wait_timr;
else
main_align_wait_timr <= main_align_wait_timr + {{MAIN_ALIGN_WAIT_TIMR_WIDTH-1{1'b0}}, 1'b1};
if (&main_align_wait_timr | all_lane_rst_done )
begin
if (active_lane_num[1] | active_lane_num[2] )
rx_main_fsm <= RX_MAIN_ALIGN_RST;
else if (active_lane_num[0])
begin
rx_main_fsm <= RX_MAIN_RST_DONE;
main_done <= (FORCE_LANE_REV == 1) ? 4'h8 : 4'h1;
end
else
begin
rx_main_fsm <= RX_MAIN_INIT;
main_done <= 4'd0;
end
end
else
rx_main_fsm <= RX_MAIN_INIT_WAIT;
end
end
RX_MAIN_ALIGN_RST :
begin
if(rate_chng )
rx_main_fsm <= RX_MAIN_CKDIV;
else
begin
main_rst_align <= 1'b1;
main_align_wait_timr <= {MAIN_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
rx_main_fsm <= RX_MAIN_ALIGN_WAIT2;
end
end
RX_MAIN_ALIGN_WAIT2 :
begin
main_rst_align <= 1'b0;
if(rate_chng )
rx_main_fsm <= RX_MAIN_CKDIV;
else if (~main_rst_align & |init_done)
rx_main_fsm <= RX_MAIN_ALIGN_WAIT;
else
rx_main_fsm <= RX_MAIN_ALIGN_WAIT2;
end
RX_MAIN_ALIGN_WAIT :
begin
if(rate_chng )
rx_main_fsm <= RX_MAIN_CKDIV;
else
begin
if (&main_align_wait_timr[6:0])
main_align_wait_timr <= main_align_wait_timr;
else
main_align_wait_timr <= main_align_wait_timr + {{MAIN_ALIGN_WAIT_TIMR_WIDTH-1{1'b0}}, 1'b1};
if (&main_align_wait_timr[6:0] | all_lane_rst_done)
begin
if (active_lane_num[2])
begin
rx_main_fsm <= RX_MAIN_RST_DONE;
main_done <= 4'hf;
end
else if (active_lane_num[1])
begin
rx_main_fsm <= RX_MAIN_RST_DONE;
main_done <= 4'h3;
end
else if (active_lane_num[0])
begin
rx_main_fsm <= RX_MAIN_RST_DONE;
main_done <= 4'h1;
end
else
begin
rx_main_fsm <= RX_MAIN_INIT;
main_done <= 4'd0;
end
end
else
rx_main_fsm <= RX_MAIN_ALIGN_WAIT;
end
end
RX_MAIN_RST_DONE :
begin
if (ltssm_in_recovery)
rx_main_fsm <= RX_MAIN_RECOVERY;
else if(rate_chng)
rx_main_fsm <= RX_MAIN_CKDIV;
else if(&main_done & (active_lane_num[1])) // down cfg linkwidth: x4 -> x2 if lane 3 inactive
main_done <= 4'h3;
else if(&main_done[1:0] & active_lane_num[0] & ~active_lane_num[1] & ~active_lane_num[2]) // down cfg linkwidth: x4 -> x1 or x2 -> x1 if lane 1 inactive
main_done <= 4'h1;
else if(((main_done == 4'h1) & (active_lane_num[2] | active_lane_num[1]) ) | ((main_done == 4'h3) & (active_lane_num[2]) )| (init_done == 4'h0)) //up cfg linkwidth : rst pcs
rx_main_fsm <= RX_MAIN_INIT;
else
rx_main_fsm <= RX_MAIN_RST_DONE;
end
RX_MAIN_RECOVERY :
begin
if (rate_chng)
begin
rx_main_fsm <= RX_MAIN_CKDIV;
main_cntr <= {CNTR_WIDTH{1'b0}};
end
else if (~ltssm_in_recovery)
rx_main_fsm <= RX_MAIN_RST_DONE;
else if(&main_done & (active_lane_num[1])) // down cfg linkwidth: x4 -> x2 if lane 3 inactive
main_done <= 4'h3;
else if(&main_done[1:0] & active_lane_num[0] & ~active_lane_num[1] & ~active_lane_num[2]) // down cfg linkwidth: x4 -> x1 or x2 -> x1 if lane 1 inactive
main_done <= 4'h1;
else if(((main_done == 4'h1) & (active_lane_num[2] | active_lane_num[1]) ) | ((main_done == 4'h3) & (active_lane_num[2]) )| (init_done == 4'h0)) //up cfg linkwidth : rst pcs
rx_main_fsm <= RX_MAIN_INIT;
else
rx_main_fsm <= RX_MAIN_RECOVERY;
end
RX_MAIN_CKDIV :
begin
main_done <= 4'd0;
if (main_cntr == RX_CKDIV_DYNSEL_SW_CNTR_NEG_VALUE)
begin
main_pll_loss_rst <= 1'b1;
rx_main_fsm <= RX_MAIN_INIT;
main_cntr <= {CNTR_WIDTH{1'b0}};
P_LX_RX_CKDIV_DYNSEL <= 1'b0;
end
else if (main_cntr == RX_CKDIV_DYNSEL_SPEED_DONE)
begin
rate_done_r <= 1'b1;
rx_main_fsm <= RX_MAIN_CKDIV;
main_cntr <= main_cntr + {{CNTR_WIDTH-1{1'b0}}, 1'b1};
end
else if (main_cntr == RX_CKDIV_SW_CNTR_VALUE)
begin
rx_main_fsm <= RX_MAIN_CKDIV;
main_cntr <= main_cntr + {{CNTR_WIDTH-1{1'b0}}, 1'b1};
if (rate)
P_LX_RX_CKDIV <= 2'd0;
else
P_LX_RX_CKDIV <= 2'd1;
end
else
begin
rate_done_r <= 1'b0;
rx_main_fsm <= RX_MAIN_CKDIV;
main_cntr <= main_cntr + {{CNTR_WIDTH-1{1'b0}}, 1'b1};
P_LX_RX_CKDIV_DYNSEL <= 1'b1;
end
end
default :
begin
main_cntr <= {CNTR_WIDTH{1'b0}};
rx_main_fsm <= RX_MAIN_IDLE;
P_RX_LANE_POWERUP <= 1'b0;
P_LX_RX_CKDIV_DYNSEL <= 1'b0;
P_LX_RX_CKDIV <= 2'b01;
main_rst_align <= 1'b0;
main_pll_loss_rst <= 1'b0;
main_align_wait_timr <= {MAIN_ALIGN_WAIT_TIMR_WIDTH{1'b0}};
end
endcase
end
end
endmodule |
module ipsl_pcie_retryd_ram
(
addr ,
wr_data ,
rd_data ,
wr_en ,
clk ,
rst
);
localparam POWER_OPT = 0 ; // @IPC bool
localparam WRITE_MODE = "NORMAL_WRITE"; // @IPC enum NORMAL_WRITE,TRANSPARENT_WRITE,READ_BEFORE_WRITE
localparam WR_BYTE_EN = 0 ; // @IPC bool
localparam BYTE_SIZE = 8 ; // @IPC enum 8,9
localparam ADDR_WIDTH = 11 ; // @IPC int 9,20
localparam DATA_WIDTH = 72 ; // @IPC int 1,1152
localparam BE_WIDTH = 4 ; // @IPC int 2,128
localparam CLK_EN = 0 ; // @IPC bool
localparam ADDR_STROBE_EN = 0 ; // @IPC bool
localparam RD_OCE_EN = 0 ; // @IPC bool
localparam OUTPUT_REG = 1 ; // @IPC bool
localparam CLK_OR_POL_INV = 0 ; // @IPC bool
localparam RESET_TYPE = "ASYNC" ; // @IPC enum Sync_Internally,SYNC,ASYNC
localparam INIT_EN = 1 ; // @IPC bool
localparam INIT_FILE = "F:/01_svn/platform_ip/system_ip/ipsl_pcie/ipsl_pcie_source/src/rtl/ipsl_pcie_ext_ram/ipsl_pcie_retryd_ram/adc_retry.dat" ; // @IPC string
localparam INIT_FORMAT = "BIN" ; // @IPC enum BIN,HEX
localparam RESET_TYPE_SEL = (RESET_TYPE == "ASYNC") ? "ASYNC_RESET" :
(RESET_TYPE == "SYNC") ? "SYNC_RESET" : "ASYNC_RESET_SYNC_RELEASE";
localparam DEVICE_NAME = "PGL25G";
localparam DATA_WIDTH_WRAP = ((DEVICE_NAME == "PGT30G") && (DATA_WIDTH <= 9)) ? 10 : DATA_WIDTH;
localparam SIM_DEVICE = ((DEVICE_NAME == "PGL22G") || (DEVICE_NAME == "PGL22GS")) ? "PGL22G" : "LOGOS";
input [ADDR_WIDTH-1 : 0] addr ;
input [DATA_WIDTH-1 : 0] wr_data ;
output [DATA_WIDTH-1 : 0] rd_data ;
input wr_en ;
input clk ;
input rst ;
wire [ADDR_WIDTH-1 : 0] addr ;
wire [DATA_WIDTH-1 : 0] wr_data ;
wire [DATA_WIDTH-1 : 0] rd_data ;
wire wr_en ;
wire clk ;
wire clk_en ;
wire addr_strobe ;
wire rst ;
wire [BE_WIDTH-1 : 0] wr_byte_en ;
wire rd_oce ;
wire [BE_WIDTH-1 : 0] wr_byte_en_mux ;
wire rd_oce_mux ;
wire clk_en_mux ;
wire addr_strobe_mux ;
wire [DATA_WIDTH_WRAP-1 : 0] wr_data_wrap;
wire [DATA_WIDTH_WRAP-1 : 0] rd_data_wrap;
assign wr_byte_en_mux = (WR_BYTE_EN == 1) ? wr_byte_en : -1 ;
assign rd_oce_mux = (RD_OCE_EN == 1) ? rd_oce :
(OUTPUT_REG == 1) ? 1'b1 : 1'B0 ;
assign clk_en_mux = (CLK_EN == 1) ? clk_en : 1'b1 ;
assign addr_strobe_mux = (ADDR_STROBE_EN == 1) ? addr_strobe : 1'b0 ;
assign wr_data_wrap = ((DEVICE_NAME == "PGT30G") && (DATA_WIDTH <= 9)) ? {{(DATA_WIDTH_WRAP - DATA_WIDTH){1'b0}},wr_data} : wr_data;
assign rd_data = ((DEVICE_NAME == "PGT30G") && (DATA_WIDTH <= 9)) ? rd_data_wrap[DATA_WIDTH-1 : 0] : rd_data_wrap;
//ipml_sdpram IP instance
ipml_spram_v1_4_ipsl_pcie_retryd_ram
#(
.c_SIM_DEVICE (SIM_DEVICE ),
.c_ADDR_WIDTH (ADDR_WIDTH ),//write address width legal value:9~20
.c_DATA_WIDTH (DATA_WIDTH_WRAP ),//write data width legal value:1~1152
.c_OUTPUT_REG (OUTPUT_REG ),//output register legal value:0 or 1
.c_RD_OCE_EN (RD_OCE_EN ),
.c_CLK_EN (CLK_EN ),
.c_ADDR_STROBE_EN (ADDR_STROBE_EN ),
.c_RESET_TYPE (RESET_TYPE_SEL ),//legal valve "ASYNC_RESET_SYNC_RELEASE" "SYNC_RESET" "ASYNC_RESET"
.c_POWER_OPT (POWER_OPT ),//0 :normal mode 1:low power mode legal value:0 or 1
.c_CLK_OR_POL_INV (CLK_OR_POL_INV ),//clk polarity invert for output register legal value 1 or 0
.c_INIT_FILE ("NONE" ),//legal value:"NONE" or "initial file name"
.c_INIT_FORMAT (INIT_FORMAT ),//initial data format legal valve: "bin" or "hex"
.c_WR_BYTE_EN (WR_BYTE_EN ),//byte write enable legal value: 0 or 1
.c_BE_WIDTH (BE_WIDTH ),//byte width legal value: 1~128
.c_WRITE_MODE (WRITE_MODE ) //"NORMAL_WRITE"; // TRANSPARENT_WRITE READ_BEFORE_WRITE
) U_ipml_spram_ipsl_pcie_retryd_ram
(
.addr ( addr ),
.wr_data ( wr_data_wrap ),
.rd_data ( rd_data_wrap ),
.wr_en ( wr_en ),
.clk ( clk ),
.clk_en ( clk_en_mux ),
.addr_strobe ( addr_strobe_mux ),
.rst ( rst ),
.wr_byte_en ( wr_byte_en_mux ),
.rd_oce ( rd_oce_mux )
);
endmodule |
module ipml_spram_v1_4_ipsl_pcie_retryd_ram
#(
parameter c_SIM_DEVICE = "LOGOS" ,
parameter c_ADDR_WIDTH = 10 , //write address width legal value:9~20
parameter c_DATA_WIDTH = 32 , //write data width legal value:1~1152
parameter c_OUTPUT_REG = 0 , //output register legal value:0 or 1
parameter c_RD_OCE_EN = 0 ,
parameter c_CLK_EN = 0 ,
parameter c_ADDR_STROBE_EN = 0 ,
parameter c_RESET_TYPE = "ASYNC_RESET" , //legal valve "ASYNC_RESET_SYNC_RELEASE" "SYNC_RESET" "ASYNC_RESET"
parameter c_POWER_OPT = 0 , //0 :normal mode 1:low power mode legal value:0 or 1
parameter c_CLK_OR_POL_INV = 0 , //clk polarity invert for output register legal value 1 or 0
parameter c_INIT_FILE = "NONE" , //legal value:"NONE" or "initial file name"
parameter c_INIT_FORMAT = "BIN" , //initial data format legal valve: "bin" or "hex"
parameter c_WR_BYTE_EN = 0 , //byte write enable legal value: 0 or 1
parameter c_BE_WIDTH = 8 , //byte width legal value: 1~128
parameter c_RAM_MODE = "SINGLE_PORT" ,
parameter c_WRITE_MODE = "NORMAL_WRITE" //"NORMAL_WRITE"; // TRANSPARENT_WRITE READ_BEFORE_WRITE
)
(
input wire [c_ADDR_WIDTH-1 : 0] addr ,
input wire [c_DATA_WIDTH-1 : 0] wr_data ,
output wire [c_DATA_WIDTH-1 : 0] rd_data ,
input wire wr_en ,
input wire clk ,
input wire clk_en ,
input wire addr_strobe ,
input wire rst ,
input wire [c_BE_WIDTH-1 : 0] wr_byte_en ,
input wire rd_oce
);
//*************************************************************************************************************************************************************
localparam INIT_EN = 1 ; // @IPC bool
localparam MODE_9K = 0 ; // @IPC bool
localparam MODE_18K = 1 ; // @IPC bool
`include "ipsl_pcie_retryd_ram_init_param.v"
//********************************************************************************************************************************************************************
//declare localparam
//L_DATA_WIDTH is the parameter value of DATA_WIDTH_A and DATA_WIDTH_B in a instance DRM ,define witch type DRM to instance in noraml mode
//********************************************************************************************************************************************************************
localparam c_WR_BYTE_WIDTH = c_WR_BYTE_EN ? c_DATA_WIDTH/(c_BE_WIDTH==0 ? 1 : c_BE_WIDTH) : (c_DATA_WIDTH%9 ==0 ? 9 : (c_DATA_WIDTH%8 ==0) ? 8 : 9 );
localparam N_DATA_WIDTH = c_ADDR_WIDTH <= 9 ? ( (c_DATA_WIDTH%9 == 0) ? ( (c_ADDR_STROBE_EN == 1) ? 18 : 36 ) :
(c_DATA_WIDTH%8 == 0) ? ( (c_ADDR_STROBE_EN == 1) ? 16 : 32 ) :
( (c_ADDR_STROBE_EN == 1) ? 18 : 36 ) ): //cascade with 512*36 type DRM
c_ADDR_WIDTH == 10 ? ( (c_DATA_WIDTH%9 == 0) ? 18 :
(c_DATA_WIDTH%8 == 0) ? 16 :
18 ): //cascade with 1k*18 type DRM
c_ADDR_WIDTH == 11 ? ( (c_DATA_WIDTH%9 == 0) ? 9 :
(c_DATA_WIDTH%8 == 0) ? 8 :
9 ): //cascade with 2k*9 type DRM
c_ADDR_WIDTH == 12 ? 4: //cascade with 4k*4 type DRM
c_ADDR_WIDTH == 13 ? 2: //cascade with 8k*2 type DRM
1; //cascade with 16k*1 type DRM
localparam L_DATA_WIDTH = c_DATA_WIDTH == 1 ? 1: //cascade with 16k*1 type DRM
c_DATA_WIDTH == 2 ? 2: //cascade with 8k*2 type DRM
c_DATA_WIDTH <= 4 ? 4: //cascade with 2k*8 type DRM
c_DATA_WIDTH <= 8 ? 8: //cascade with 2k*9 type DRM
c_DATA_WIDTH == 9 ? 9: //cascade with 4k*4 type DRM
c_DATA_WIDTH <= 16 ? 16: //cascade with 1k*16 type DRM
c_DATA_WIDTH <= 18 ? 18: //cascade with 1k*18 type DRM
((c_DATA_WIDTH%9 == 0) ? ( (c_ADDR_STROBE_EN == 1) ? 18 : 36 ):
(c_DATA_WIDTH%8 == 0) ? ( (c_ADDR_STROBE_EN == 1) ? 16 : 32 ):
( (c_ADDR_STROBE_EN == 1) ? 18 : 36 ) ); //cascade with 512*36 type DRM
//********************************************************************************************************************************************************************
//BYTE ENABLE parameter
//byte_enable && WIDTH_RATIO = 1
localparam N_BYTE_DATA_WIDTH = (c_ADDR_WIDTH <= 8) ? (c_WR_BYTE_WIDTH == 8 ? ( (c_ADDR_STROBE_EN == 1) ? 16 : 32 ) :
( (c_ADDR_STROBE_EN == 1) ? 18 : 36 ) ) :
(c_WR_BYTE_WIDTH == 8 ? 16 : 18);
localparam L_BYTE_DATA_WIDTH = (c_WR_BYTE_WIDTH == 8) ? (c_DATA_WIDTH <= 16 ? 16 :
( (c_ADDR_STROBE_EN == 1) ? 16 : 32 ) ) :
(c_DATA_WIDTH <= 18 ? 18 :
( (c_ADDR_STROBE_EN == 1) ? 18 : 36 ) );
//DRM_DATA_WIDTH is the port parameter of DRM
localparam DRM_DATA_WIDTH = (c_POWER_OPT == 1) ? (c_WR_BYTE_EN ==1 ? L_BYTE_DATA_WIDTH : L_DATA_WIDTH):
(c_WR_BYTE_EN ==1 ? N_BYTE_DATA_WIDTH : N_DATA_WIDTH);
localparam DATA_LOOP_NUM = (c_DATA_WIDTH%DRM_DATA_WIDTH == 0) ? (c_DATA_WIDTH/DRM_DATA_WIDTH):(c_DATA_WIDTH/DRM_DATA_WIDTH + 1);
localparam Q_DATA_WIDTH = (DRM_DATA_WIDTH == 36) ? 18 : (DRM_DATA_WIDTH == 32) ? 16 : DRM_DATA_WIDTH;
//DRM_ADDR_WIDTH is the ADDR_WIDTH of INSTANCE DRM primitives
localparam DRM_ADDR_WIDTH = DRM_DATA_WIDTH == 1 ? 14:
DRM_DATA_WIDTH == 2 ? 13:
DRM_DATA_WIDTH == 4 ? 12:
DRM_DATA_WIDTH == 8 ? 11:
DRM_DATA_WIDTH == 9 ? 11:
DRM_DATA_WIDTH == 16 ? 10:
DRM_DATA_WIDTH == 18 ? 10:
DRM_DATA_WIDTH == 32 ? 9:
9;
localparam ADDR_WIDTH = c_ADDR_WIDTH > DRM_ADDR_WIDTH ? c_ADDR_WIDTH : DRM_ADDR_WIDTH;
//CS_ADDR_WIDTH is the CS address width to choose the DRM18K CS_ADDR_WIDTH= [ extra-addres + cs[2]+csp[1]+cs[0] ]
localparam CS_ADDR_WIDTH = ADDR_WIDTH - DRM_ADDR_WIDTH;
//ADDR_LOOP_NUM difine how many loops to cascade the c_ADDR_WIDTH
localparam ADDR_LOOP_NUM = 2**CS_ADDR_WIDTH;
//CAS_DATA_WIDTH is the cascaded data width
localparam CAS_DATA_WIDTH = DRM_DATA_WIDTH*DATA_LOOP_NUM;
localparam Q_CAS_DATA_WIDTH = Q_DATA_WIDTH*DATA_LOOP_NUM;
localparam WR_BYTE_WIDTH = c_WR_BYTE_EN == 1 ? c_WR_BYTE_WIDTH :
( (DRM_DATA_WIDTH >=8 || DRM_DATA_WIDTH >=9 ) ? ((c_DATA_WIDTH%9 == 0) ? 9 : 8 ) : 1 );
//MASK_NUM the mask base value
localparam MASK_NUM = ( DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH == 32 ) ? (ADDR_LOOP_NUM > 4 ? 2 : 4 ):
( ADDR_LOOP_NUM >8 ) ? (( DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH == 32 ) ? 2 : 4) : 8;
localparam c_RST_TYPE = (c_RESET_TYPE == "SYNC_RESET") ? "SYNC" : ((c_RESET_TYPE == "ASYNC_RESET") ? "ASYNC" : "ASYNC_SYNC_RELEASE");
//parameter check
initial begin
if(c_ADDR_WIDTH>20 || c_ADDR_WIDTH<8 ) begin
$display("IPSpecCheck: 01030300 ipml_flex_spram parameter setting error !!!: c_ADDR_WIDTH must between 8-20")/* PANGO PAP_CRITICAL_WARNING */;
//$finish;
end
else if( c_DATA_WIDTH>1152 || c_DATA_WIDTH<1 ) begin
$display("IPSpecCheck: 01030301 ipml_flex_spram parameter setting error !!!: c_DATA_WIDTH must between 1-1152")/* PANGO PAP_CRITICAL_WARNING */;
//$finish;
end
else if(c_OUTPUT_REG!=1 && c_OUTPUT_REG!=0 ) begin
$display("IPSpecCheck: 01030303 ipml_flex_spram parameter setting error !!!: c_OUTPUT_REG must be 0 or 1")/* PANGO PAP_ERROR */;
$finish;
end
else if ( c_RD_OCE_EN!=0 && c_RD_OCE_EN!=1 ) begin
$display("IPSpecCheck: 01030304 ipml_flex_spram parameter setting error !!!: c_RD_OCE_EN must be 0 or 1")/* PANGO PAP_ERROR */;
$finish;
end
else if ( c_CLK_OR_POL_INV!=0 && c_CLK_OR_POL_INV!=1 ) begin
$display("IPSpecCheck: 01030305 ipml_flex_spram parameter setting error !!!: c_CLK_OR_POL_INV must be 0 or 1")/* PANGO PAP_ERROR */;
$finish;
end
else if ( c_RD_OCE_EN==1 && c_OUTPUT_REG==0 ) begin
$display("IPSpecCheck: 01030306 ipml_flex_spram parameter setting error !!!: c_OUTPUT_REG must be 1 when c_RD_OCE_EN is 1")/* PANGO PAP_ERROR */;
$finish;
end
else if ( c_CLK_OR_POL_INV==1 && c_OUTPUT_REG==0 ) begin
$display("IPSpecCheck: 01030307 ipml_flex_spram parameter setting error !!!: c_OUTPUT_REG must be 1 when c_CLK_OR_POL_INV is 1")/* PANGO PAP_ERROR */;
$finish;
end
else if ( c_CLK_EN!=0 && c_CLK_EN!=1 ) begin
$display("IPSpecCheck: 01030308 ipml_flex_spram parameter setting error !!!: c_CLK_EN must be 0 or 1")/* PANGO PAP_ERROR */;
$finish;
end
else if ( c_ADDR_STROBE_EN!=0 && c_ADDR_STROBE_EN!=1 ) begin
$display("IPSpecCheck: 01030309 ipml_flex_spram parameter setting error !!!: c_ADDR_STROBE_EN must be 0 or 1")/* PANGO PAP_ERROR */;
$finish;
end
else if ( c_SIM_DEVICE=="PGL22G" && (c_CLK_EN==1 && c_ADDR_STROBE_EN==1) ) begin
$display("IPSpecCheck: 01030310 ipml_flex_spram parameter setting error !!!: Clock Enable and Address Strobe only works individually when using PGL22G")/* PANGO PAP_ERROR */;
$finish;
end
else if(c_RST_TYPE!="ASYNC" && c_RST_TYPE!="SYNC" && c_RST_TYPE!="ASYNC_SYNC_RELEASE") begin
$display("IPSpecCheck: 01030011 ipml_flex_spram parameter setting error !!!: c_RESET_TYPE must be ASYNC or SYNC or ASYNC_SYNC_RELEASE")/* PANGO PAP_ERROR */;
$finish;
end
else if(c_POWER_OPT!=1 && c_POWER_OPT!=0 ) begin
$display("IPSpecCheck: 01030312 ipml_flex_spram parameter setting error !!!: c_POWER_OPT must be 0 or 1")/* PANGO PAP_ERROR */;
$finish;
end
else if(c_INIT_FORMAT!="BIN" && c_INIT_FORMAT!="HEX" ) begin
$display("IPSpecCheck: 01030313 ipml_flex_spram parameter setting error !!!: c_INIT_FORMAT must be bin or hex ")/* PANGO PAP_ERROR */;
$finish;
end
else if(c_WR_BYTE_EN!=0 && c_WR_BYTE_EN!=1 ) begin
$display("IPSpecCheck: 01030314 ipml_flex_spram parameter setting error !!!: c_WR_BYTE_EN must be 0 or 1")/* PANGO PAP_ERROR */;
$finish;
end
else if(c_WR_BYTE_EN==1) begin
if(c_WR_BYTE_WIDTH!=8 && c_WR_BYTE_WIDTH!=9 ) begin
$display("IPSpecCheck: 01030315 ipml_flex_spram parameter setting error !!!: c_WR_BYTE_WIDTH must be 8 or 9")/* PANGO PAP_ERROR */;
$finish;
end
if( (c_DATA_WIDTH%8)!=0 && (c_DATA_WIDTH%9)!=0 ) begin
$display("IPSpecCheck: 01030316 ipml_flex_spram parameter setting error !!!: c_DATA_WIDTH must be 8*N or 9*N")/* PANGO PAP_ERROR */;
$finish;
end
end
else if(c_WRITE_MODE!="NORMAL_WRITE" && c_WRITE_MODE!="TRANSPARENT_WRITE" && c_WRITE_MODE!="READ_BEFORE_WRITE") begin
$display("IPSpecCheck: 01030317 ipml_flex_spram parameter setting error !!!: c_WRITE_MODE must be NORMAL_WRITE or TRANSPARENT_WRITE or READ_BEFORE_WRITE")/* PANGO PAP_ERROR */;
$finish;
end
// else if ( (c_POWER_OPT==0 && c_ADDR_WIDTH<=9 && c_WRITE_MODE!="NORMAL_WRITE") || (c_POWER_OPT==1 && c_DATA_WIDTH>=16 && c_WRITE_MODE!="NORMAL_WRITE") ) begin
// $display("IPSpecCheck: 01030318 ipml_flex_spram parameter setting error !!!: Only works in NORMAL_WRITE when c_POWER_OPT==0 and c_ADDR_WIDTH<=9 or c_POWER_OPT==1 and c_DATA_WIDTH>=16")/* PANGO PAP_ERROR */;
// $finish;
// end
else if ( c_WR_BYTE_EN==1 && c_ADDR_STROBE_EN==1 ) begin
$display("IPSpecCheck: 01030319 ipml_flex_spram parameter setting error !!!: When Byte Write, disable Address Strobe")/* PANGO PAP_ERROR */;
$finish;
end
end
//main code
//********************************************************************************************************************************************************
//inner variables
wire [CAS_DATA_WIDTH-1:0] wr_data_bus ;
reg [Q_CAS_DATA_WIDTH-1:0] da_data_bus ; //the data bus of data_cascaded instance DRM
wire [Q_CAS_DATA_WIDTH*ADDR_LOOP_NUM-1:0] qa_data_bus ; //the total data width of instance DRM
wire [ADDR_WIDTH-1:0] addr_bus ;
reg [DATA_LOOP_NUM*14-1:0] drm_addr ; //write address to all instance DRM
reg cs_bit0 ; //write cs[0] to all instance DRM
reg [ADDR_LOOP_NUM-1:0] cs_bit1_bus ; //write cs[1] to all instance DRM
reg [ADDR_LOOP_NUM-1:0] cs_bit2_bus ; //write cs[2] bus to every data_cascaded DRM-block
reg cs_bit0_ff ;
reg [ADDR_LOOP_NUM-1:0] cs_bit1_bus_ff;
reg [ADDR_LOOP_NUM-1:0] cs_bit2_bus_ff;
wire cs_bit0_m ;
wire [ADDR_LOOP_NUM-1:0] cs_bit1_bus_m ;
wire [ADDR_LOOP_NUM-1:0] cs_bit2_bus_m ;
wire wr_en_b ;
wire clk_en_b ;
reg [CAS_DATA_WIDTH*ADDR_LOOP_NUM-1:0] rd_data_bus ;
reg [Q_CAS_DATA_WIDTH-1:0] db_data_bus ; //the data bus of data_cascaded instance DRM
wire [Q_CAS_DATA_WIDTH*ADDR_LOOP_NUM-1:0] qb_data_bus ; //the total data width of instance DRM
reg [DATA_LOOP_NUM*14-1:0] drm_b_addr ;
reg csb_bit0 ; //write cs[0] to all instance DRM
reg [ADDR_LOOP_NUM-1:0] csb_bit1_bus ; //write cs[1] to all instance DRM
reg [ADDR_LOOP_NUM-1:0] csb_bit2_bus ; //write cs[2] bus to every data_cascaded DRM-block
wire csb_bit0_m ;
wire [ADDR_LOOP_NUM-1:0] csb_bit1_bus_m ;
wire [ADDR_LOOP_NUM-1:0] csb_bit2_bus_m ;
wire [ADDR_LOOP_NUM-1:0] cs2_ctrl ;
//byte enable
wire [CAS_DATA_WIDTH/WR_BYTE_WIDTH-1 : 0] wr_byte_en_bus;
//********************************************************************************************************************************************************
//write data mux
assign wr_data_bus[CAS_DATA_WIDTH-1:0] = {{(CAS_DATA_WIDTH-c_DATA_WIDTH){1'b0}},wr_data[c_DATA_WIDTH-1:0]};
assign addr_bus[ADDR_WIDTH-1:0] = {{(ADDR_WIDTH-c_ADDR_WIDTH){1'b0}},addr[c_ADDR_WIDTH-1:0]};
//drive wr_byte_en_bus
assign wr_byte_en_bus = (c_WR_BYTE_EN == 0) ? -1 : {{(CAS_DATA_WIDTH/WR_BYTE_WIDTH-c_DATA_WIDTH/WR_BYTE_WIDTH){1'b0}},wr_byte_en[c_BE_WIDTH-1:0]};
//generate drm_addr connect to the instance DRM directly ,based on DRM_DATA_WIDTH
integer gen_wa;
always@(*) begin
for(gen_wa=0;gen_wa < DATA_LOOP_NUM;gen_wa = gen_wa +1 ) begin
case(DRM_DATA_WIDTH)
1 : begin
drm_addr[gen_wa*14 +: 14] = addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0];
drm_b_addr[gen_wa*14 +: 14] = addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0];
end
2 : begin
drm_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],1'b0};
drm_b_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],1'b0};
end
4 : begin
drm_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],2'b00};
drm_b_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],2'b00};
end
8,9 : begin
drm_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],3'b000};
drm_b_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],3'b000};
end
16,18 : begin
drm_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],2'b00,wr_byte_en_bus[gen_wa*2 +: 2]};
drm_b_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],4'b0000};
end
32,36 : begin
if ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE"))
begin
drm_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],3'b000,wr_byte_en_bus[gen_wa*4 +: 2]};
drm_b_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],3'b100,wr_byte_en_bus[gen_wa*4+2 +: 2]};
end
else
begin
drm_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],1'b0,wr_byte_en_bus[gen_wa*4 +: 4]};
drm_b_addr[gen_wa*14 +: 14] = {addr_bus[(ADDR_WIDTH-CS_ADDR_WIDTH-1):0],1'b0,wr_byte_en_bus[gen_wa*4 +: 4]};
end
end
endcase
end
end
localparam CS_ADDR_3_LSB = (CS_ADDR_WIDTH >= 3) ? (ADDR_WIDTH-CS_ADDR_WIDTH+1) : (ADDR_WIDTH-2); //avoid reveral index of wr_addr_bus
localparam CS_ADDR_4_LSB = (CS_ADDR_WIDTH >= 4) ? (ADDR_WIDTH-1-CS_ADDR_WIDTH+3) : (ADDR_WIDTH-2); //avoid reveral index of wr_addr_bus
//generate CS control signal
integer gen_m;
always@(*) begin
for(gen_m=0;gen_m<ADDR_LOOP_NUM;gen_m=gen_m+1) begin
if(DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH == 32) begin
if(CS_ADDR_WIDTH == 0) begin
cs_bit0 = 0;
cs_bit1_bus[gen_m] = 0;
if ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE"))
cs_bit2_bus[gen_m] = 1'b1;
else
cs_bit2_bus[gen_m] = 1'b0;
end
else if(CS_ADDR_WIDTH == 1) begin
cs_bit0 = addr_bus[ADDR_WIDTH-CS_ADDR_WIDTH];
cs_bit1_bus[gen_m] = 0;
if ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE"))
cs_bit2_bus[gen_m] = 1'b1;
else
cs_bit2_bus[gen_m] = 1'b0;
end
else if(CS_ADDR_WIDTH == 2) begin
cs_bit0 = addr_bus[ADDR_WIDTH-CS_ADDR_WIDTH];
cs_bit1_bus[gen_m] = addr_bus[ADDR_WIDTH-1];
if ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE"))
cs_bit2_bus[gen_m] = 1'b1;
else
cs_bit2_bus[gen_m] = 1'b0;
end
else if(CS_ADDR_WIDTH >= 3) begin
cs_bit0 = addr_bus[ADDR_WIDTH-CS_ADDR_WIDTH];
cs_bit1_bus[gen_m] = (addr_bus[(ADDR_WIDTH-1):CS_ADDR_3_LSB] == (gen_m/2)) ? 0:1;
if ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE"))
cs_bit2_bus[gen_m] = 1'b1;
else
cs_bit2_bus[gen_m] = 1'b0;
end
end
else begin
if(CS_ADDR_WIDTH == 0) begin
cs_bit0 = 0;
cs_bit1_bus[gen_m] = 0;
cs_bit2_bus[gen_m] = 0;
end
else if(CS_ADDR_WIDTH == 1) begin
cs_bit0 = addr_bus[ADDR_WIDTH-CS_ADDR_WIDTH];
cs_bit1_bus[gen_m] = 0;
cs_bit2_bus[gen_m] = 0;
end
else if(CS_ADDR_WIDTH == 2) begin
cs_bit0 = addr_bus[ADDR_WIDTH-2];
cs_bit1_bus[gen_m] = addr_bus[ADDR_WIDTH-1];
cs_bit2_bus[gen_m] = 0;
end
else if(CS_ADDR_WIDTH == 3) begin
cs_bit0 = addr_bus[ADDR_WIDTH-3];
cs_bit1_bus[gen_m] = addr_bus[ADDR_WIDTH-2];
cs_bit2_bus[gen_m] = addr_bus[ADDR_WIDTH-1];
end
else if(CS_ADDR_WIDTH >= 4) begin
cs_bit0 = addr_bus[ADDR_WIDTH-CS_ADDR_WIDTH];
cs_bit1_bus[gen_m] = addr_bus[ADDR_WIDTH-CS_ADDR_WIDTH+1];
cs_bit2_bus[gen_m] = (addr_bus[(ADDR_WIDTH-1):CS_ADDR_4_LSB] == (gen_m/4)) ? 0 : 1;
end
end
end
end
//B port CS
always@(*) begin
if(DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH == 32)
csb_bit0 = cs_bit0 ;
else
csb_bit0 = 0;
end
always@(*) begin
if(DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH == 32)
csb_bit1_bus = cs_bit1_bus ;
else
csb_bit1_bus = 'b0;
end
always@(*) begin
if(DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH == 32) begin
if ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE"))
csb_bit2_bus = cs_bit2_bus;
else
csb_bit2_bus = cs_bit2_bus & (~wr_en) ;
end
else
csb_bit2_bus = 'b0;
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
cs_bit0_ff <= 0;
cs_bit1_bus_ff <= 0;
cs_bit2_bus_ff <= 0;
end
else if(~addr_strobe) begin
cs_bit0_ff <= cs_bit0;
cs_bit1_bus_ff <= cs_bit1_bus;
cs_bit2_bus_ff <= cs_bit2_bus;
end
end
assign cs_bit0_m = (c_SIM_DEVICE == "PGL22G") ? (addr_strobe ? cs_bit0_ff : cs_bit0 ) : cs_bit0;
assign cs_bit1_bus_m = (c_SIM_DEVICE == "PGL22G") ? (addr_strobe ? cs_bit1_bus_ff : cs_bit1_bus) : cs_bit1_bus;
assign cs_bit2_bus_m = (c_SIM_DEVICE == "PGL22G") ? (addr_strobe ? cs_bit2_bus_ff : cs_bit2_bus) : cs_bit2_bus;
assign csb_bit0_m = cs_bit0_m;
assign csb_bit1_bus_m = cs_bit1_bus_m;
assign csb_bit2_bus_m = cs_bit2_bus_m;
wire [18*DATA_LOOP_NUM*ADDR_LOOP_NUM-1:0] QA_bus;
wire [18*DATA_LOOP_NUM*ADDR_LOOP_NUM-1:0] QB_bus;
wire [18*DATA_LOOP_NUM-1:0] DA_bus;
wire [18*DATA_LOOP_NUM-1:0] DB_bus;
integer drm_d_i;
always@(*) begin
for (drm_d_i = 0; drm_d_i <DATA_LOOP_NUM; drm_d_i = drm_d_i+1) begin
db_data_bus[drm_d_i*Q_DATA_WIDTH +:Q_DATA_WIDTH] = 'b0;
da_data_bus[drm_d_i*Q_DATA_WIDTH +:Q_DATA_WIDTH] = 'b0;
if(DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH == 32)
{db_data_bus[drm_d_i*Q_DATA_WIDTH +:Q_DATA_WIDTH] ,da_data_bus[drm_d_i*Q_DATA_WIDTH +:Q_DATA_WIDTH]} = wr_data_bus[drm_d_i*DRM_DATA_WIDTH +:DRM_DATA_WIDTH];
else begin
da_data_bus[drm_d_i*Q_DATA_WIDTH +:Q_DATA_WIDTH] = wr_data_bus[drm_d_i*DRM_DATA_WIDTH +:DRM_DATA_WIDTH];
db_data_bus[drm_d_i*Q_DATA_WIDTH +:Q_DATA_WIDTH] = 'b0;
end
end
end
localparam RAM_MODE_SEL = (c_RAM_MODE == "ROM") ? "ROM"
: ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE")) ? "TRUE_DUAL_PORT" : "SINGLE_PORT";
localparam DRM_DATA_WIDTH_SEL = (c_RAM_MODE == "ROM") ? DRM_DATA_WIDTH
: ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE")) ? (DRM_DATA_WIDTH/2) : DRM_DATA_WIDTH;
//generate constructs: ADDR_LOOP to cascade request address and DATA LOOP to cascade request data
genvar gen_i,gen_j;
generate
for(gen_j=0;gen_j<ADDR_LOOP_NUM;gen_j=gen_j+1) begin:ADDR_LOOP
for(gen_i=0;gen_i<DATA_LOOP_NUM;gen_i=gen_i+1) begin:DATA_LOOP
localparam [2:0] CSA_MASK = ( DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH == 32 ) ? (gen_j%MASK_NUM & 3'b011) : (gen_j%MASK_NUM);
localparam [2:0] CSB_MASK = ( DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH == 32 ) ? (gen_j%MASK_NUM & 3'b011) : (gen_j%MASK_NUM);
localparam [2:0] CSA_MASK_SEL = ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE")) ? (3'b100 | gen_j%MASK_NUM) : CSA_MASK;
localparam [2:0] CSB_MASK_SEL = ((DRM_DATA_WIDTH > 18) && (c_WRITE_MODE != "NORMAL_WRITE")) ? (3'b100 | gen_j%MASK_NUM) : CSB_MASK;
//write data
if( Q_DATA_WIDTH == 16 ) begin
assign qa_data_bus[gen_i*Q_DATA_WIDTH+gen_j*Q_CAS_DATA_WIDTH +:Q_DATA_WIDTH] = {QA_bus[(gen_i*18+gen_j*18*DATA_LOOP_NUM+9) +:8],QA_bus[(gen_i*18+gen_j*18*DATA_LOOP_NUM) +:8]};
assign {DA_bus[(gen_i*18+9) +:8 ],DA_bus[gen_i*18 +:8]} = da_data_bus[gen_i*Q_DATA_WIDTH +:Q_DATA_WIDTH];
end
else begin
assign qa_data_bus[gen_i*Q_DATA_WIDTH+gen_j*Q_CAS_DATA_WIDTH +:Q_DATA_WIDTH] = QA_bus[(gen_i*18+gen_j*18*DATA_LOOP_NUM) +:Q_DATA_WIDTH];
assign DA_bus[gen_i*18 +:Q_DATA_WIDTH] = da_data_bus[gen_i*Q_DATA_WIDTH +:Q_DATA_WIDTH];
end
if( Q_DATA_WIDTH == 16 ) begin
assign qb_data_bus[gen_i*Q_DATA_WIDTH+gen_j*Q_CAS_DATA_WIDTH +:Q_DATA_WIDTH] = {QB_bus[(gen_i*18+gen_j*18*DATA_LOOP_NUM+9) +:8],QB_bus[(gen_i*18+gen_j*18*DATA_LOOP_NUM) +:8]};
assign {DB_bus[(gen_i*18+9) +:8],DB_bus[gen_i*18 +:8]} = db_data_bus[gen_i*Q_DATA_WIDTH +:Q_DATA_WIDTH];
end
else begin
assign qb_data_bus[gen_i*Q_DATA_WIDTH+gen_j*Q_CAS_DATA_WIDTH +:Q_DATA_WIDTH] = QB_bus[(gen_i*18+gen_j*18*DATA_LOOP_NUM) +:Q_DATA_WIDTH];
assign DB_bus[gen_i*18 +:Q_DATA_WIDTH] = db_data_bus[gen_i*Q_DATA_WIDTH +:Q_DATA_WIDTH];
end
assign wr_en_b = (DRM_DATA_WIDTH <= 18) ? 1'b0 : (c_WRITE_MODE == "NORMAL_WRITE") ? 1'b0 : wr_en;
assign clk_en_b = (DRM_DATA_WIDTH <= 18) ? 1'b0 : (c_WRITE_MODE == "NORMAL_WRITE") ? ~wr_en & clk_en : clk_en;
GTP_DRM18K # (
.INIT_00 (INIT_00[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_01 (INIT_01[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_02 (INIT_02[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_03 (INIT_03[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_04 (INIT_04[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_05 (INIT_05[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_06 (INIT_06[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_07 (INIT_07[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_08 (INIT_08[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_09 (INIT_09[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_0A (INIT_0A[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_0B (INIT_0B[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_0C (INIT_0C[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_0D (INIT_0D[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_0E (INIT_0E[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_0F (INIT_0F[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_10 (INIT_10[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_11 (INIT_11[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_12 (INIT_12[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_13 (INIT_13[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_14 (INIT_14[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_15 (INIT_15[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_16 (INIT_16[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_17 (INIT_17[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_18 (INIT_18[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_19 (INIT_19[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_1A (INIT_1A[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_1B (INIT_1B[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_1C (INIT_1C[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_1D (INIT_1D[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_1E (INIT_1E[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_1F (INIT_1F[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_20 (INIT_20[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_21 (INIT_21[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_22 (INIT_22[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_23 (INIT_23[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_24 (INIT_24[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_25 (INIT_25[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_26 (INIT_26[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_27 (INIT_27[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_28 (INIT_28[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_29 (INIT_29[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_2A (INIT_2A[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_2B (INIT_2B[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_2C (INIT_2C[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_2D (INIT_2D[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_2E (INIT_2E[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_2F (INIT_2F[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_30 (INIT_30[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_31 (INIT_31[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_32 (INIT_32[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_33 (INIT_33[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_34 (INIT_34[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_35 (INIT_35[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_36 (INIT_36[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_37 (INIT_37[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_38 (INIT_38[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_39 (INIT_39[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_3A (INIT_3A[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_3B (INIT_3B[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_3C (INIT_3C[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_3D (INIT_3D[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_3E (INIT_3E[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.INIT_3F (INIT_3F[(gen_j * DATA_LOOP_NUM + gen_i)*288 +: 288]),
.GRS_EN ( "FALSE" ),
.SIM_DEVICE ( c_SIM_DEVICE ),
.CSA_MASK ( CSA_MASK_SEL ),
.CSB_MASK ( CSB_MASK_SEL ),
.DATA_WIDTH_A ( DRM_DATA_WIDTH_SEL ), // 1 2 4 8 16 9 18
.DATA_WIDTH_B ( DRM_DATA_WIDTH_SEL ), // 1 2 4 8 16 9 18
.WRITE_MODE_A ( c_WRITE_MODE ),
.WRITE_MODE_B ( c_WRITE_MODE ),
.DOA_REG ( c_OUTPUT_REG ),
.DOB_REG ( c_OUTPUT_REG ),
.DOA_REG_CLKINV ( c_CLK_OR_POL_INV ),
.DOB_REG_CLKINV ( c_CLK_OR_POL_INV ),
.RST_TYPE ( c_RST_TYPE ), // ASYNC_RESET_SYNC_RELEASE SYNC_RESET
.RAM_MODE ( RAM_MODE_SEL ), // TRUE_DUAL_PORT
.INIT_FILE ( c_INIT_FILE ),
.BLOCK_X ( gen_i ),
.BLOCK_Y ( gen_j ),
.RAM_ADDR_WIDTH ( ADDR_WIDTH ),
.RAM_DATA_WIDTH ( CAS_DATA_WIDTH ),
.INIT_FORMAT ( c_INIT_FORMAT ) //binary or hex
) U_GTP_DRM18K (
.DOA(QA_bus[(gen_i*18+gen_j*18*DATA_LOOP_NUM) +:18]),
.ADDRA(drm_addr[gen_i*14 +: 14]), //wr_addr[13:0]
.ADDRA_HOLD(addr_strobe),
.DIA(DA_bus[gen_i*18 +:18]),
.CSA({cs_bit2_bus_m[gen_j],cs_bit1_bus_m[gen_j],cs_bit0_m}),
.WEA(wr_en),
.CLKA(clk),
.CEA(clk_en),
.ORCEA(rd_oce),
.RSTA(rst),
.DOB(QB_bus[(gen_i*18+gen_j*18*DATA_LOOP_NUM) +:18]),
.ADDRB(drm_b_addr[gen_i*14 +: 14]), //rd_addr[13:0]
.ADDRB_HOLD(addr_strobe),
.DIB(DB_bus[gen_i*18 +:18]),
.CSB({csb_bit2_bus_m[gen_j],csb_bit1_bus_m[gen_j],csb_bit0_m}),
.WEB(wr_en_b),
.CLKB(clk),
.CEB(clk_en_b),
.ORCEB(rd_oce),
.RSTB(rst)
);
//rd_data_bus
always@(*)
begin
if(DRM_DATA_WIDTH == 36 || DRM_DATA_WIDTH ==32)
rd_data_bus[gen_i*DRM_DATA_WIDTH+gen_j*CAS_DATA_WIDTH +:DRM_DATA_WIDTH] = {qb_data_bus[gen_i*Q_DATA_WIDTH+gen_j*Q_CAS_DATA_WIDTH +:Q_DATA_WIDTH] ,qa_data_bus[gen_i*Q_DATA_WIDTH+gen_j*Q_CAS_DATA_WIDTH +:Q_DATA_WIDTH]};
else
rd_data_bus[gen_i*DRM_DATA_WIDTH+gen_j*CAS_DATA_WIDTH +:DRM_DATA_WIDTH] = qa_data_bus[gen_i*Q_DATA_WIDTH+gen_j*Q_CAS_DATA_WIDTH +:Q_DATA_WIDTH];
end
end
end
endgenerate
//rd_data: extra mux combination logic
localparam ADDR_SEL_LSB = (CS_ADDR_WIDTH > 0) ? (ADDR_WIDTH - CS_ADDR_WIDTH) : (ADDR_WIDTH - 1);
wire [CS_ADDR_WIDTH-1:0] addr_bus_rd_sel;
reg [CS_ADDR_WIDTH-1:0] addr_bus_rd_ce;
reg [CS_ADDR_WIDTH-1:0] addr_bus_rd_ce_ff;
wire [CS_ADDR_WIDTH-1:0] addr_bus_rd_ce_mux;
reg [CS_ADDR_WIDTH-1:0] addr_bus_rd_oce;
reg [CS_ADDR_WIDTH-1:0] addr_bus_rd_invt;
reg [CAS_DATA_WIDTH-1:0] rd_full_data;
reg wr_en_ff;
//CE
always @(posedge clk or posedge rst)
begin
if (rst)
addr_bus_rd_ce <= 0;
else if (~addr_strobe & clk_en)
addr_bus_rd_ce <= addr_bus[ADDR_WIDTH-1:ADDR_SEL_LSB];
end
always @(posedge clk or posedge rst)
begin
if (rst)
wr_en_ff <= 1'b0;
else if (clk_en)
wr_en_ff <= wr_en;
end
always @(posedge clk or posedge rst)
begin
if (rst)
addr_bus_rd_ce_ff <= 0;
else if (~wr_en_ff)
addr_bus_rd_ce_ff <= addr_bus_rd_ce;
end
assign addr_bus_rd_ce_mux = (c_WRITE_MODE != "NORMAL_WRITE") ? addr_bus_rd_ce : wr_en_ff ? addr_bus_rd_ce_ff : addr_bus_rd_ce;
//OCE
always @(posedge clk or posedge rst)
begin
if (rst)
addr_bus_rd_oce <= 0;
else if (rd_oce)
addr_bus_rd_oce <= addr_bus_rd_ce_mux;
end
//INVT
always @(negedge clk or posedge rst)
begin
if (rst)
addr_bus_rd_invt <= 0;
else if (rd_oce)
addr_bus_rd_invt <= addr_bus_rd_ce_mux;
end
assign addr_bus_rd_sel = (c_CLK_OR_POL_INV == 1) ? addr_bus_rd_invt : (c_OUTPUT_REG == 1) ? addr_bus_rd_oce : addr_bus_rd_ce_mux;
integer n;
always@(*)
begin
rd_full_data = 0;
if(ADDR_LOOP_NUM>1) begin
for(n=0;n<ADDR_LOOP_NUM;n=n+1) begin
if(addr_bus_rd_sel == n)
rd_full_data = rd_data_bus[n*CAS_DATA_WIDTH +: CAS_DATA_WIDTH];
end
end
else begin
rd_full_data = rd_data_bus;
end
end
assign rd_data = rd_full_data[c_DATA_WIDTH-1:0];
endmodule |
module ipml_hsst_rxlane_rst_fsm_v1_1#(
parameter FREE_CLOCK_FREQ = 100 , //unit is MHz, free clock freq from GUI
parameter CH_MULT_LANE_MODE = 1 , //1: 1lane 2:2lane 4:4lane
parameter CH_RXPCS_ALIGN_TIMER = 10000 , //maximum is 65535
parameter CH_BYPASS_WORD_ALIGN = "FALSE" , //TRUE: Lane Bypass Word Alignment, FALSE: Lane No Bypass Word Alignment
parameter CH_BYPASS_BONDING = "FALSE" , //TRUE: Lane Bypass Channel Bonding, FALSE: Lane No Bypass Channel Bonding
parameter CH_BYPASS_CTC = "FALSE" , //TRUE: Lane Bypass CTC, FALSE: Lane No Bypass CTC
parameter LX_RX_CKDIV = 0 ,
parameter PCS_RX_CLK_EXPLL_USE = "FALSE"
)(
// Reset and Clock
input wire clk ,
input wire rst_n ,
// HSST Reset Control Signal
input wire fifo_clr_en ,
input wire i_rx_rate_chng ,
input wire [2:0] i_rxckdiv ,
input wire sigdet ,
input wire cdr_align ,
input wire word_align ,
input wire bonding ,
input wire i_pll_lock_rx ,
input wire i_pcs_cb_rst ,
output reg P_RX_LANE_PD ,
output reg P_RX_PMA_RST ,
output reg P_PCS_RX_RST ,
output reg [2:0] P_RX_RATE ,
output wire P_PCS_CB_RST ,
output reg o_rxckdiv_done ,
output reg o_rxlane_done ,
output reg fifoclr_sig
);
//RX Lane Power Up
`ifdef IPML_HSST_SPEEDUP_SIM
localparam integer RX_PD_CNTR_VALUE = 2*((1*FREE_CLOCK_FREQ)); //add 50 percent margin
localparam integer RX_PCS_CNTR_VALUE = 2*((1*FREE_CLOCK_FREQ)); //add 50 percent margin
`else
localparam integer RX_PD_CNTR_VALUE = 2*((40*FREE_CLOCK_FREQ)); //add 50 percent margin
localparam integer RX_PCS_CNTR_VALUE = 2*((10*FREE_CLOCK_FREQ)); //add 50 percent margin
`endif
localparam integer RX_CDR_WAIT_CNTR_VALUE = 224*FREE_CLOCK_FREQ+2048;// max time : (16*8191/600)+2+2048 cycle
localparam integer RX_PMA_CNTR_VALUE = 2*((1*FREE_CLOCK_FREQ)); //add 50 percent margin
localparam integer RX_RST_DONE_DLY_CNTR_VALUE = 32;//add for rxlane_done is active but fabric clock is none by wenbin at @2019.9.26
//RX Lane Rate Change
localparam integer RX_RATE_CHANGE_PMA_R_CNTR_VALUE = 2*((0.05*FREE_CLOCK_FREQ)); //add 50 percent margin
localparam integer RX_RATE_CHANGE_PMA_F_CNTR_VALUE = 2*((0.1*FREE_CLOCK_FREQ)); //add 50 percent margin
//Counter Width
localparam CNTR_WIDTH0 = 13 ;
localparam CNTR_WIDTH1 = 8 ;
localparam CNTR_WIDTH2 = 15 ;
localparam CNTR_WIDTH3 = 11 ;
localparam CNTR_WIDTH4 = 6 ;
localparam CNTR_WIDTH5 = 5 ;
localparam CNTR_WIDTH6 = log2(CH_RXPCS_ALIGN_TIMER);
//RX Lane FSM Status
localparam RX_LANE_IDLE = 4'd0;
localparam RX_LANE_RXPD = 4'd1;
localparam RX_LANE_PMA_RST = 4'd2;
localparam RX_LANE_SIGNAL_WAIT = 4'd3;
localparam RX_LANE_CDR_WAIT = 4'd4;
localparam RX_LANE_PCS_RST = 4'd5;
localparam RX_LANE_ALIGN_WAIT = 4'd6;
localparam RX_LANE_BONDING_WAIT = 4'd7;
localparam RX_LANE_DONE = 4'd8;
localparam RX_LANE_CB_RST = 4'd9;
localparam RX_CKDIV_ONLY = 4'd10;
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
reg [CNTR_WIDTH0-1 : 0] cntr0 ;
reg [CNTR_WIDTH1-1 : 0] cntr1 ;
reg [CNTR_WIDTH2-1 : 0] cntr2 ;
reg [CNTR_WIDTH3-1 : 0] cntr3 ;
reg [CNTR_WIDTH4-1 : 0] cntr4 ;
reg [CNTR_WIDTH5-1 : 0] cntr5 ;
reg [CNTR_WIDTH6-1 : 0] cntr6 ;
reg [3 : 0] rxlane_rst_fsm ;
reg [3 : 0] next_state ;
reg [1 : 0] i_rx_rate_chng_ff ;
reg i_rx_rate_chng_posedge ;
wire rxlane_word_align_en ;
wire rxlane_bonding_en ;
wire rxlane_mult_en ;
wire expll_lock_rx ;
reg [2 : 0] i_rxckdiv_ff ;
reg [2 : 0] rxckdiv ;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
assign rxlane_word_align_en = (CH_BYPASS_WORD_ALIGN=="FALSE") ? 1'b1 : 1'b0;
assign rxlane_bonding_en = (CH_BYPASS_BONDING=="FALSE") ? 1'b1 : 1'b0;
assign rxlane_mult_en = (CH_MULT_LANE_MODE==2 || CH_MULT_LANE_MODE==4) ? 1'b1 : 1'b0;
assign expll_lock_rx = (PCS_RX_CLK_EXPLL_USE=="FALSE") ? 1'b1 : i_pll_lock_rx;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
i_rx_rate_chng_ff <= 2'b00;
else
i_rx_rate_chng_ff <= {i_rx_rate_chng_ff[0],i_rx_rate_chng};
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
i_rxckdiv_ff <= 3'b000;
else
i_rxckdiv_ff <= i_rxckdiv;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
i_rx_rate_chng_posedge <= 1'b0;
else if (rxlane_rst_fsm == RX_CKDIV_ONLY)
i_rx_rate_chng_posedge <= 1'b0;
else if (i_rx_rate_chng_ff[0] & (!i_rx_rate_chng_ff[1]))
i_rx_rate_chng_posedge <= 1'b1;
else ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
rxckdiv <= 3'b000;
else if (!i_rx_rate_chng_posedge && i_rx_rate_chng_ff[0] && (!i_rx_rate_chng_ff[1]) && rxlane_rst_fsm != RX_CKDIV_ONLY)
rxckdiv <= i_rxckdiv_ff;
else ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rxlane_rst_fsm <= RX_LANE_IDLE ;
end
else begin
rxlane_rst_fsm <= next_state ;
end
end
always @(*)
begin
case(rxlane_rst_fsm)
RX_LANE_IDLE :
next_state = RX_LANE_RXPD ;
RX_LANE_RXPD :
begin
if(cntr0 == RX_PD_CNTR_VALUE)
next_state = RX_LANE_PMA_RST ;
else
next_state = RX_LANE_RXPD ;
end
RX_LANE_PMA_RST :
begin
if(cntr1 == RX_PMA_CNTR_VALUE)
next_state = RX_LANE_SIGNAL_WAIT ;
else
next_state = RX_LANE_PMA_RST ;
end
RX_LANE_SIGNAL_WAIT :
begin
if(i_rx_rate_chng_posedge)
next_state = RX_CKDIV_ONLY ;
else if (sigdet)
next_state = RX_LANE_CDR_WAIT ;
else
next_state = RX_LANE_SIGNAL_WAIT ;
end
RX_LANE_CDR_WAIT :
begin
if(!sigdet || cntr2 == RX_CDR_WAIT_CNTR_VALUE)
next_state = RX_LANE_PMA_RST ;
else if (i_rx_rate_chng_posedge)
next_state = RX_CKDIV_ONLY ;
else if (cdr_align && expll_lock_rx )
next_state = RX_LANE_PCS_RST ;
else
next_state = RX_LANE_CDR_WAIT ;
end
RX_LANE_PCS_RST :
begin
if(!sigdet || !cdr_align)
next_state = RX_LANE_PMA_RST ;
else if (i_rx_rate_chng_posedge)
next_state = RX_CKDIV_ONLY ;
else if (cntr3 == RX_PCS_CNTR_VALUE )
if (rxlane_word_align_en)
next_state = RX_LANE_ALIGN_WAIT ;
else
next_state = RX_LANE_DONE ;
else
next_state = RX_LANE_PCS_RST ;
end
RX_LANE_ALIGN_WAIT :
begin
if(!sigdet || !cdr_align)
next_state = RX_LANE_PMA_RST ;
else if (i_rx_rate_chng_posedge)
next_state = RX_CKDIV_ONLY ;
else if (!word_align)
if(cntr6 == CH_RXPCS_ALIGN_TIMER)
next_state = RX_LANE_PMA_RST ;
else
next_state = RX_LANE_ALIGN_WAIT ;
else
next_state = RX_LANE_BONDING_WAIT ;
end
RX_LANE_BONDING_WAIT:
begin
if(!sigdet || !cdr_align)
next_state = RX_LANE_PMA_RST ;
else if (i_rx_rate_chng_posedge)
next_state = RX_CKDIV_ONLY ;
else if (i_pcs_cb_rst && rxlane_bonding_en)
next_state = RX_LANE_CB_RST ;
else if (bonding || !rxlane_bonding_en)
next_state = RX_LANE_DONE ;
else
next_state = RX_LANE_BONDING_WAIT ;
end
RX_LANE_DONE :
begin
if(!sigdet || !cdr_align)
next_state = RX_LANE_PMA_RST ;
else if (i_rx_rate_chng_posedge)
next_state = RX_CKDIV_ONLY ;
else if (fifo_clr_en && rxlane_mult_en)
next_state = RX_LANE_PCS_RST ;
else if (i_pcs_cb_rst)
next_state = RX_LANE_CB_RST ;
else
next_state = RX_LANE_DONE ;
end
RX_LANE_CB_RST :
begin
if(!sigdet || !cdr_align)
next_state = RX_LANE_PMA_RST ;
else if (i_rx_rate_chng_posedge)
next_state = RX_CKDIV_ONLY ;
else if(!i_pcs_cb_rst)
next_state = RX_LANE_BONDING_WAIT ;
else
next_state = RX_LANE_CB_RST ;
end
RX_CKDIV_ONLY :
begin
if(cntr5 == RX_RATE_CHANGE_PMA_F_CNTR_VALUE)
next_state = RX_LANE_SIGNAL_WAIT ;
else
next_state = RX_CKDIV_ONLY ;
end
default :
begin
next_state = RX_LANE_IDLE ;
end
endcase
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cntr0 <= {CNTR_WIDTH0{1'b0}};
cntr1 <= {CNTR_WIDTH1{1'b0}};
cntr2 <= {CNTR_WIDTH2{1'b0}};
cntr3 <= {CNTR_WIDTH3{1'b0}};
cntr4 <= {CNTR_WIDTH4{1'b0}};
cntr5 <= {CNTR_WIDTH5{1'b0}};
cntr6 <= {CNTR_WIDTH6{1'b0}};
P_RX_LANE_PD <= 1'b1;
P_RX_PMA_RST <= 1'b1;
P_PCS_RX_RST <= 1'b1;
P_RX_RATE <= LX_RX_CKDIV;
o_rxckdiv_done <= 1'b0;
o_rxlane_done <= 1'b0;
fifoclr_sig <= 1'b0 ;
end
else
begin
case (rxlane_rst_fsm)
RX_LANE_IDLE :
begin
cntr0 <= {CNTR_WIDTH0{1'b0}};
cntr1 <= {CNTR_WIDTH1{1'b0}};
cntr2 <= {CNTR_WIDTH2{1'b0}};
cntr3 <= {CNTR_WIDTH3{1'b0}};
cntr4 <= {CNTR_WIDTH4{1'b0}};
cntr5 <= {CNTR_WIDTH5{1'b0}};
cntr6 <= {CNTR_WIDTH6{1'b0}};
P_RX_LANE_PD <= 1'b1;
P_RX_PMA_RST <= 1'b1;
P_PCS_RX_RST <= 1'b1;
P_RX_RATE <= LX_RX_CKDIV;
o_rxckdiv_done <= 1'b0;
o_rxlane_done <= 1'b0;
fifoclr_sig <= 1'b0;
end
RX_LANE_RXPD :
begin
if(cntr0 == RX_PD_CNTR_VALUE)
begin
cntr0 <= {CNTR_WIDTH0{1'b0}} ;
P_RX_LANE_PD <= 1'b0 ;
end
else
begin
cntr0 <= cntr0 + {{CNTR_WIDTH0-1{1'b0}},{1'b1}} ;
end
end
RX_LANE_PMA_RST :
begin
if(cntr1 == RX_PMA_CNTR_VALUE)
begin
cntr1 <= {CNTR_WIDTH1{1'b0}} ;
P_RX_PMA_RST <= 1'b0 ;
end
else
begin
cntr1 <= cntr1 + {{CNTR_WIDTH1-1{1'b0}},{1'b1}} ;
P_RX_PMA_RST <= 1'b1 ;
P_PCS_RX_RST <= 1'b1 ;
o_rxlane_done <= 1'b0 ;
fifoclr_sig <= 1'b0 ;
end
end
RX_LANE_SIGNAL_WAIT :
begin
fifoclr_sig <= 1'b0 ;
end
RX_LANE_CDR_WAIT :
begin
if(!sigdet || cntr2 == RX_CDR_WAIT_CNTR_VALUE || i_rx_rate_chng_posedge || (cdr_align && expll_lock_rx))
begin
cntr2 <= {CNTR_WIDTH2{1'b0}} ;
end
else
begin
cntr2 <= cntr2 + {{CNTR_WIDTH2-1{1'b0}},{1'b1}} ;
end
end
RX_LANE_PCS_RST :
begin
if(!sigdet || !cdr_align || i_rx_rate_chng_posedge || cntr3 == RX_PCS_CNTR_VALUE)
begin
cntr3 <= {CNTR_WIDTH3{1'b0}} ;
end
else if (cntr3 >= RX_PCS_CNTR_VALUE - 1)
begin
P_PCS_RX_RST <= 1'b0 ;
cntr3 <= cntr3 + {{CNTR_WIDTH3-1{1'b0}},{1'b1}} ;
end
else
begin
cntr3 <= cntr3 + {{CNTR_WIDTH3-1{1'b0}},{1'b1}} ;
P_PCS_RX_RST <= 1'b1 ;
o_rxlane_done <= 1'b0 ;
end
end
RX_LANE_ALIGN_WAIT :
begin
if(word_align || cntr6 == CH_RXPCS_ALIGN_TIMER)
begin
cntr6 <= {CNTR_WIDTH6{1'b0}} ;
end
else
begin
cntr6 <= cntr6 + {{CNTR_WIDTH6-1{1'b0}},{1'b1}} ;
end
end
RX_LANE_BONDING_WAIT :
begin
end
RX_LANE_DONE :
begin
if(!sigdet || !cdr_align || i_rx_rate_chng_posedge || (fifo_clr_en && rxlane_mult_en) || i_pcs_cb_rst) begin
cntr4 <= {CNTR_WIDTH4{1'b0}} ;
end
else if(cntr4 == RX_RST_DONE_DLY_CNTR_VALUE) begin
o_rxlane_done <= 1'b1 ;
end
else begin
cntr4 <= cntr4 + {{CNTR_WIDTH4-1{1'b0}},{1'b1}} ;
fifoclr_sig <= 1'b1 ;
end
end
RX_LANE_CB_RST :
begin
o_rxlane_done <= 1'b0 ;
end
RX_CKDIV_ONLY :
begin
if(cntr5 == RX_RATE_CHANGE_PMA_F_CNTR_VALUE)
begin
cntr5 <= {CNTR_WIDTH5{1'b0}} ;
P_RX_PMA_RST <= 1'b0 ;
o_rxckdiv_done <= 1'b1 ;
end
else
begin
o_rxlane_done <= 1'b0 ;
o_rxckdiv_done <= 1'b0 ;
P_PCS_RX_RST <= 1'b1 ;
P_RX_PMA_RST <= 1'b1 ;
cntr5 <= cntr5 + {{CNTR_WIDTH5-1{1'b0}},{1'b1}} ;
if(cntr5 == RX_RATE_CHANGE_PMA_R_CNTR_VALUE)
P_RX_RATE <= rxckdiv ;
else ;
end
end
default :
begin
cntr0 <= {CNTR_WIDTH0{1'b0}} ;
cntr1 <= {CNTR_WIDTH1{1'b0}} ;
cntr2 <= {CNTR_WIDTH2{1'b0}} ;
cntr3 <= {CNTR_WIDTH3{1'b0}} ;
cntr4 <= {CNTR_WIDTH4{1'b0}} ;
cntr5 <= {CNTR_WIDTH5{1'b0}} ;
cntr6 <= {CNTR_WIDTH6{1'b0}} ;
P_RX_LANE_PD <= 1'b1;
P_RX_PMA_RST <= 1'b1;
P_PCS_RX_RST <= 1'b1;
P_RX_RATE <= LX_RX_CKDIV;
o_rxckdiv_done <= 1'b0;
o_rxlane_done <= 1'b0;
fifoclr_sig <= 1'b0;
end
endcase
end
end
assign P_PCS_CB_RST = i_pcs_cb_rst ;
function integer log2 (input integer x);
integer i;
begin
i = 1;
while (2**i < x)
begin
i = i + 1;
end
log2 = i;
end
endfunction
endmodule |
module ipml_hsst_rst_pll_v1_0#(
parameter FREE_CLOCK_FREQ = 100 ,//Unit is MHz, free clock freq from GUI Freq: 0~200MHz
parameter PLL_NUBER = 1
)(
//User Side
input wire clk ,
input wire i_pll_rst_0 ,
input wire i_pll_rst_1 ,
input wire P_PLL_READY_0 ,
input wire P_PLL_READY_1 ,
input wire i_wtchdg_clr_0 ,
input wire i_wtchdg_clr_1 ,
output wire [1 : 0] o_wtchdg_st_0 ,
output wire [1 : 0] o_wtchdg_st_1 ,
output wire o_pll_done_0 ,
output wire o_pll_done_1 ,
output wire P_PLLPOWERDOWN_0 ,
output wire P_PLLPOWERDOWN_1 ,
output wire P_PLL_RST_0 ,
output wire P_PLL_RST_1
);
localparam PLL_LOCK_RISE_CNTR_WIDTH = 12 ;
localparam PLL_LOCK_RISE_CNTR_VALUE = 2048;
localparam PLL_LOCK_WTCHDG_CNTR1_WIDTH = 10 ;
localparam PLL_LOCK_WTCHDG_CNTR2_WIDTH = 10 ;
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
wire pll_lock_0 ;
wire wtchdg_rstn_0 ;
wire pll_rstn_0 ;
wire s_pll_rstn_0 ;
wire s_pll_ready_0 ;
wire i_pll_rstn_0 ;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
assign i_pll_rstn_0 = ~i_pll_rst_0 ;
//Sync signal
ipml_hsst_rst_sync_v1_0 pll0_rstn_sync (.clk(clk), .rst_n(i_pll_rstn_0), .sig_async(1'b1), .sig_synced(s_pll_rstn_0));
ipml_hsst_rst_sync_v1_0 pll0_lock_sync (.clk(clk), .rst_n(s_pll_rstn_0), .sig_async(P_PLL_READY_0), .sig_synced(s_pll_ready_0));
//Debounce
ipml_hsst_rst_debounce_v1_0 #(.RISE_CNTR_WIDTH(PLL_LOCK_RISE_CNTR_WIDTH), .RISE_CNTR_VALUE(PLL_LOCK_RISE_CNTR_VALUE))
pll0_lock_deb (.clk(clk), .rst_n(s_pll_rstn_0), .signal_b(s_pll_ready_0), .signal_deb(pll_lock_0));
ipml_hsst_rst_wtchdg_v1_0 #(.WTCHDG_CNTR1_WIDTH(PLL_LOCK_WTCHDG_CNTR1_WIDTH), .WTCHDG_CNTR2_WIDTH(PLL_LOCK_WTCHDG_CNTR2_WIDTH))
pll0_lock_wtchdg (.clk(clk), .rst_n(s_pll_rstn_0), .wtchdg_clr(i_wtchdg_clr_0), .wtchdg_in(s_pll_ready_0), .wtchdg_rst_n(wtchdg_rstn_0), .wtchdg_st(o_wtchdg_st_0));
assign pll_rstn_0 = wtchdg_rstn_0 && s_pll_rstn_0 ;
//----- Instance pll Rst Fsm Module -----------
ipml_hsst_pll_rst_fsm_v1_0#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ )
) pll_rst_fsm_0 (
.clk (clk ),
.rst_n (pll_rstn_0 ),
.pll_lock (pll_lock_0 ),
.P_PLLPOWERDOWN (P_PLLPOWERDOWN_0 ),
.P_PLL_RST (P_PLL_RST_0 ),
.o_pll_done (o_pll_done_0 )
);
generate
if(PLL_NUBER == 2) begin : PLL_FSM_2_GENERATE
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
wire pll_lock_1 ;
wire wtchdg_rstn_1 ;
wire pll_rstn_1 ;
wire s_pll_rstn_1 ;
wire s_pll_ready_1 ;
wire i_pll_rstn_1 ;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
assign i_pll_rstn_1 = ~i_pll_rst_1 ;
//Sync signal
ipml_hsst_rst_sync_v1_0 pll1_rstn_sync (.clk(clk), .rst_n(i_pll_rstn_1), .sig_async(1'b1), .sig_synced(s_pll_rstn_1));
ipml_hsst_rst_sync_v1_0 pll1_lock_sync (.clk(clk), .rst_n(s_pll_rstn_1), .sig_async(P_PLL_READY_1), .sig_synced(s_pll_ready_1));
//Debounce
ipml_hsst_rst_debounce_v1_0 #(.RISE_CNTR_WIDTH(PLL_LOCK_RISE_CNTR_WIDTH), .RISE_CNTR_VALUE(PLL_LOCK_RISE_CNTR_VALUE))
pll1_lock_deb (.clk(clk), .rst_n(s_pll_rstn_1), .signal_b(s_pll_ready_1), .signal_deb(pll_lock_1));
ipml_hsst_rst_wtchdg_v1_0 #(.WTCHDG_CNTR1_WIDTH(PLL_LOCK_WTCHDG_CNTR1_WIDTH), .WTCHDG_CNTR2_WIDTH(PLL_LOCK_WTCHDG_CNTR2_WIDTH))
pll1_lock_wtchdg (.clk(clk), .rst_n(s_pll_rstn_1), .wtchdg_clr(i_wtchdg_clr_1), .wtchdg_in(s_pll_ready_1), .wtchdg_rst_n(wtchdg_rstn_1), .wtchdg_st(o_wtchdg_st_1));
assign pll_rstn_1 = wtchdg_rstn_1 && s_pll_rstn_1 ;
//----- Instance pll Rst Fsm Module -----------
ipml_hsst_pll_rst_fsm_v1_0#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ )
) pll_rst_fsm_1 (
.clk (clk ),
.rst_n (pll_rstn_1 ),
.pll_lock (pll_lock_1 ),
.P_PLLPOWERDOWN (P_PLLPOWERDOWN_1 ),
.P_PLL_RST (P_PLL_RST_1 ),
.o_pll_done (o_pll_done_1 )
);
end
else begin : PLL_FSM_2_NO_GENERATE
assign o_wtchdg_st_1 = 2'b0;
assign o_pll_done_1 = 1'b0;
assign P_PLLPOWERDOWN_1 = 1'b1;
assign P_PLL_RST_1 = 1'b1;
end
endgenerate
endmodule |
module ipml_hsst_rst_rx_v1_1#(
parameter FREE_CLOCK_FREQ = 100 , //unit is MHz, free clock freq from GUI
parameter CH0_RX_ENABLE = "TRUE" , //TRUE:lane0 RX Reset Logic used, FALSE: lane0 RX Reset Logic remove
parameter CH1_RX_ENABLE = "TRUE" , //TRUE:lane1 RX Reset Logic used, FALSE: lane1 RX Reset Logic remove
parameter CH2_RX_ENABLE = "TRUE" , //TRUE:lane2 RX Reset Logic used, FALSE: lane2 RX Reset Logic remove
parameter CH3_RX_ENABLE = "TRUE" , //TRUE:lane3 RX Reset Logic used, FALSE: lane3 RX Reset Logic remove
parameter CH0_MULT_LANE_MODE = 1 , //Lane0 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH1_MULT_LANE_MODE = 1 , //Lane1 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH2_MULT_LANE_MODE = 1 , //Lane2 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH3_MULT_LANE_MODE = 1 , //Lane3 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH0_RXPCS_ALIGN_TIMER = 10000 , //Word Alignment Wait time, when match the RXPMA will be Reset
parameter CH1_RXPCS_ALIGN_TIMER = 10000 , //Word Alignment Wait time, when match the RXPMA will be Reset
parameter CH2_RXPCS_ALIGN_TIMER = 10000 , //Word Alignment Wait time, when match the RXPMA will be Reset
parameter CH3_RXPCS_ALIGN_TIMER = 10000 , //Word Alignment Wait time, when match the RXPMA will be Reset
parameter PCS_CH0_BYPASS_WORD_ALIGN = "FALSE" , //TRUE: Lane0 Bypass Word Alignment, FALSE: Lane0 No Bypass Word Alignment
parameter PCS_CH1_BYPASS_WORD_ALIGN = "FALSE" , //TRUE: Lane1 Bypass Word Alignment, FALSE: Lane1 No Bypass Word Alignment
parameter PCS_CH2_BYPASS_WORD_ALIGN = "FALSE" , //TRUE: Lane2 Bypass Word Alignment, FALSE: Lane0 No Bypass Word Alignment
parameter PCS_CH3_BYPASS_WORD_ALIGN = "FALSE" , //TRUE: Lane3 Bypass Word Alignment, FALSE: Lane0 No Bypass Word Alignment
parameter PCS_CH0_BYPASS_BONDING = "FALSE" , //TRUE: Lane0 Bypass Channel Bonding, FALSE: Lane0 No Bypass Channel Bonding
parameter PCS_CH1_BYPASS_BONDING = "FALSE" , //TRUE: Lane1 Bypass Channel Bonding, FALSE: Lane1 No Bypass Channel Bonding
parameter PCS_CH2_BYPASS_BONDING = "FALSE" , //TRUE: Lane2 Bypass Channel Bonding, FALSE: Lane2 No Bypass Channel Bonding
parameter PCS_CH3_BYPASS_BONDING = "FALSE" , //TRUE: Lane3 Bypass Channel Bonding, FALSE: Lane3 No Bypass Channel Bonding
parameter PCS_CH0_BYPASS_CTC = "FALSE" , //TRUE: Lane0 Bypass CTC, FALSE: Lane0 No Bypass CTC
parameter PCS_CH1_BYPASS_CTC = "FALSE" , //TRUE: Lane1 Bypass CTC, FALSE: Lane1 No Bypass CTC
parameter PCS_CH2_BYPASS_CTC = "FALSE" , //TRUE: Lane2 Bypass CTC, FALSE: Lane2 No Bypass CTC
parameter PCS_CH3_BYPASS_CTC = "FALSE" , //TRUE: Lane3 Bypass CTC, FALSE: Lane3 No Bypass CTC
parameter LX_RX_CKDIV_0 = 0 ,
parameter LX_RX_CKDIV_1 = 0 ,
parameter LX_RX_CKDIV_2 = 0 ,
parameter LX_RX_CKDIV_3 = 0 ,
parameter CH0_RX_PLL_SEL = 0 ,//Lane0 --> 1:PLL1 0:PLL0
parameter CH1_RX_PLL_SEL = 0 ,//Lane1 --> 1:PLL1 0:PLL0
parameter CH2_RX_PLL_SEL = 0 ,//Lane2 --> 1:PLL1 0:PLL0
parameter CH3_RX_PLL_SEL = 0 ,//Lane3 --> 1:PLL1 0:PLL0
parameter PCS_RX_CLK_EXPLL_USE_CH0 = "FALSE" ,
parameter PCS_RX_CLK_EXPLL_USE_CH1 = "FALSE" ,
parameter PCS_RX_CLK_EXPLL_USE_CH2 = "FALSE" ,
parameter PCS_RX_CLK_EXPLL_USE_CH3 = "FALSE"
)(
// Reset and Clock
input wire clk ,
input wire i_hsst_fifo_clr_0 ,
input wire i_hsst_fifo_clr_1 ,
input wire i_hsst_fifo_clr_2 ,
input wire i_hsst_fifo_clr_3 ,
// HSST Reset Control Signal
input wire P_LANE_RST_0 ,
input wire P_LANE_RST_1 ,
input wire P_LANE_RST_2 ,
input wire P_LANE_RST_3 ,
input wire i_rxlane_rst_0 ,
input wire i_rxlane_rst_1 ,
input wire i_rxlane_rst_2 ,
input wire i_rxlane_rst_3 ,
input wire i_rx_rate_chng_0 ,
input wire i_rx_rate_chng_1 ,
input wire i_rx_rate_chng_2 ,
input wire i_rx_rate_chng_3 ,
input wire [2:0] i_rxckdiv_0 ,
input wire [2:0] i_rxckdiv_1 ,
input wire [2:0] i_rxckdiv_2 ,
input wire [2:0] i_rxckdiv_3 ,
input wire i_pcs_cb_rst_0 ,
input wire i_pcs_cb_rst_1 ,
input wire i_pcs_cb_rst_2 ,
input wire i_pcs_cb_rst_3 ,
input wire i_force_rxfsm_det_0 ,//Debug signal for loopback mode
input wire i_force_rxfsm_det_1 ,//Debug signal for loopback mode
input wire i_force_rxfsm_det_2 ,//Debug signal for loopback mode
input wire i_force_rxfsm_det_3 ,//Debug signal for loopback mode
input wire i_force_rxfsm_lsm_0 ,//Debug signal for loopback mode
input wire i_force_rxfsm_lsm_1 ,//Debug signal for loopback mode
input wire i_force_rxfsm_lsm_2 ,//Debug signal for loopback mode
input wire i_force_rxfsm_lsm_3 ,//Debug signal for loopback mode
input wire i_force_rxfsm_cdr_0 ,//Debug signal for loopback mode
input wire i_force_rxfsm_cdr_1 ,//Debug signal for loopback mode
input wire i_force_rxfsm_cdr_2 ,//Debug signal for loopback mode
input wire i_force_rxfsm_cdr_3 ,//Debug signal for loopback mode
input wire i_pll_lock_rx_0 ,
input wire i_pll_lock_rx_1 ,
input wire i_pll_lock_rx_2 ,
input wire i_pll_lock_rx_3 ,
input wire P_RX_SIGDET_STATUS_0 ,
input wire P_RX_SIGDET_STATUS_1 ,
input wire P_RX_SIGDET_STATUS_2 ,
input wire P_RX_SIGDET_STATUS_3 ,
input wire P_RX_READY_0 ,
input wire P_RX_READY_1 ,
input wire P_RX_READY_2 ,
input wire P_RX_READY_3 ,
input wire P_PCS_LSM_SYNCED_0 ,
input wire P_PCS_LSM_SYNCED_1 ,
input wire P_PCS_LSM_SYNCED_2 ,
input wire P_PCS_LSM_SYNCED_3 ,
input wire P_PCS_RX_MCB_STATUS_0 ,
input wire P_PCS_RX_MCB_STATUS_1 ,
input wire P_PCS_RX_MCB_STATUS_2 ,
input wire P_PCS_RX_MCB_STATUS_3 ,
output wire P_PCS_CB_RST_0 ,
output wire P_PCS_CB_RST_1 ,
output wire P_PCS_CB_RST_2 ,
output wire P_PCS_CB_RST_3 ,
output wire P_RX_LANE_PD_0 ,
output wire P_RX_LANE_PD_1 ,
output wire P_RX_LANE_PD_2 ,
output wire P_RX_LANE_PD_3 ,
output wire P_RX_PMA_RST_0 ,
output wire P_RX_PMA_RST_1 ,
output wire P_RX_PMA_RST_2 ,
output wire P_RX_PMA_RST_3 ,
output wire P_PCS_RX_RST_0 ,
output wire P_PCS_RX_RST_1 ,
output wire P_PCS_RX_RST_2 ,
output wire P_PCS_RX_RST_3 ,
output wire [2 : 0] P_RX_RATE_0 ,
output wire [2 : 0] P_RX_RATE_1 ,
output wire [2 : 0] P_RX_RATE_2 ,
output wire [2 : 0] P_RX_RATE_3 ,
output wire o_rxlane_done_0 ,
output wire o_rxlane_done_1 ,
output wire o_rxlane_done_2 ,
output wire o_rxlane_done_3 ,
output wire o_rxckdiv_done_0 ,
output wire o_rxckdiv_done_1 ,
output wire o_rxckdiv_done_2 ,
output wire o_rxckdiv_done_3
);
localparam SIGDET_DEB_RISE_CNTR_WIDTH = 12;
localparam SIGDET_DEB_RISE_CNTR_VALUE = 4;
localparam CDR_ALIGN_DEB_RISE_CNTR_WIDTH = 12;
`ifdef IPML_HSST_SPEEDUP_SIM
localparam CDR_ALIGN_DEB_RISE_CNTR_VALUE = 20;
localparam PLL_LOCK_RISE_CNTR_VALUE = 20;
`else
localparam CDR_ALIGN_DEB_RISE_CNTR_VALUE = 2048;
localparam PLL_LOCK_RISE_CNTR_VALUE = 2048;
`endif
localparam PLL_LOCK_RISE_CNTR_WIDTH = 12 ;
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
wire [4-1 :0] i_rxlane_rstn ;
wire [4-1 :0] i_rx_rate_chng ;
wire [4*3-1 :0] i_rxckdiv ;
wire [4-1 :0] i_pll_lock_rx ;
wire [4-1 :0] P_LX_SIGDET_STA ;
wire [4-1 :0] P_LX_CDR_ALIGN ;
wire [4-1 :0] P_PCS_LSM_SYNCED ;
wire [4-1 :0] P_PCS_RX_MCB_STATUS ;
wire [4-1 :0] s_rxlane_rstn ;
wire [4-1 :0] p_rxlane_rstn ;
wire [4-1 :0] s_LX_SIGDET_STA ;
wire [4-1 :0] s_LX_SIGDET_STA_deb ;
wire [4-1 :0] s_LX_CDR_ALIGN ;
wire [4-1 :0] s_LX_CDR_ALIGN_deb ;
wire [4-1 :0] s_PCS_LSM_SYNCED ;
wire [4-1 :0] s_P_PCS_RX_MCB_STATUS ;
wire [4-1 :0] fifo_clr_en ;
wire [4-1 :0] rxlane_done ;
wire [4-1 :0] fifoclr_sig ;
wire [4-1 :0] p_force_rxfsm_det ;
wire [4-1 :0] p_force_rxfsm_lsm ;
wire [4-1 :0] p_force_rxfsm_cdr ;
wire [4-1 :0] p_pcs_cb_rst ;
wire [4-1 :0] sigdet ;
wire [4-1 :0] cdr_align ;
wire [4-1 :0] word_align ;
wire [4-1 :0] bonding ;
wire [4-1 :0] s_pll_lock_rx ;
wire [4-1 :0] s_pll_lock_rx_deb ;
wire fifoclr_sig_0 ;
wire fifoclr_sig_1 ;
wire fifoclr_sig_2 ;
wire fifoclr_sig_3 ;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
generate
if(CH0_MULT_LANE_MODE==4) begin:FOUR_LANE_MODE
assign i_rxlane_rstn = {4{~i_rxlane_rst_0 }};
assign i_rx_rate_chng = {4{i_rx_rate_chng_0}};
assign i_rxckdiv = {4{i_rxckdiv_0 }};
assign i_pll_lock_rx = {4{i_pll_lock_rx_0}};
assign p_pcs_cb_rst = {4{i_pcs_cb_rst_0}};
assign p_force_rxfsm_det= {4{i_force_rxfsm_det_0}};
assign p_force_rxfsm_lsm= {4{i_force_rxfsm_lsm_0}};
assign p_force_rxfsm_cdr= {4{i_force_rxfsm_cdr_0}};
end
else if(CH0_MULT_LANE_MODE==2 && CH2_MULT_LANE_MODE==2) begin: TWO_LANE_MODE
assign i_rxlane_rstn = {{2{~i_rxlane_rst_2 }},{2{~i_rxlane_rst_0 }}};
assign i_rx_rate_chng = {{2{i_rx_rate_chng_2}},{2{i_rx_rate_chng_0}}};
assign i_rxckdiv = {{2{i_rxckdiv_2 }},{2{i_rxckdiv_0 }}};
assign i_pll_lock_rx = {{2{i_pll_lock_rx_2}},{2{i_pll_lock_rx_0}}};
assign p_pcs_cb_rst = {{2{i_pcs_cb_rst_2}},{2{i_pcs_cb_rst_0}}};
assign p_force_rxfsm_det = {{2{i_force_rxfsm_det_2}},{2{i_force_rxfsm_det_0}}};
assign p_force_rxfsm_lsm = {{2{i_force_rxfsm_lsm_2}},{2{i_force_rxfsm_lsm_0}}};
assign p_force_rxfsm_cdr = {{2{i_force_rxfsm_cdr_2}},{2{i_force_rxfsm_cdr_0}}};
end
else if(CH0_MULT_LANE_MODE==2) begin:TWO_LANE_MODE0
assign i_rxlane_rstn = {~i_rxlane_rst_3 ,~i_rxlane_rst_2 ,{2{~i_rxlane_rst_0 }}};
assign i_rx_rate_chng = {i_rx_rate_chng_3,i_rx_rate_chng_2,{2{i_rx_rate_chng_0}}};
assign i_rxckdiv = {i_rxckdiv_3 ,i_rxckdiv_2 ,{2{i_rxckdiv_0 }}};
assign i_pll_lock_rx = {i_pll_lock_rx_3,i_pll_lock_rx_2,{2{i_pll_lock_rx_0}}};
assign p_pcs_cb_rst = {i_pcs_cb_rst_3,i_pcs_cb_rst_2,{2{i_pcs_cb_rst_0}}};
assign p_force_rxfsm_det = {i_force_rxfsm_det_3,i_force_rxfsm_det_2,{2{i_force_rxfsm_det_0}}};
assign p_force_rxfsm_lsm = {i_force_rxfsm_lsm_3,i_force_rxfsm_lsm_2,{2{i_force_rxfsm_lsm_0}}};
assign p_force_rxfsm_cdr = {i_force_rxfsm_cdr_3,i_force_rxfsm_cdr_2,{2{i_force_rxfsm_cdr_0}}};
end
else if(CH2_MULT_LANE_MODE==2) begin:TWO_LANE_MODE1
assign i_rxlane_rstn = {{2{~i_rxlane_rst_2 }},~i_rxlane_rst_1 ,~i_rxlane_rst_0 };
assign i_rx_rate_chng = {{2{i_rx_rate_chng_2}},i_rx_rate_chng_1,i_rx_rate_chng_0};
assign i_rxckdiv = {{2{i_rxckdiv_2 }},i_rxckdiv_1 ,i_rxckdiv_0 };
assign i_pll_lock_rx = {{2{i_pll_lock_rx_2}},i_pll_lock_rx_1,i_pll_lock_rx_0};
assign p_pcs_cb_rst = {{2{i_pcs_cb_rst_2}},i_pcs_cb_rst_1,i_pcs_cb_rst_0};
assign p_force_rxfsm_det = {{2{i_force_rxfsm_det_2}},i_force_rxfsm_det_1,i_force_rxfsm_det_0};
assign p_force_rxfsm_lsm = {{2{i_force_rxfsm_lsm_2}},i_force_rxfsm_lsm_1,i_force_rxfsm_lsm_0};
assign p_force_rxfsm_cdr = {{2{i_force_rxfsm_cdr_2}},i_force_rxfsm_cdr_1,i_force_rxfsm_cdr_0};
end
else begin:ONE_LANE_MODE
assign i_rxlane_rstn = {~i_rxlane_rst_3 ,~i_rxlane_rst_2 ,~i_rxlane_rst_1 ,~i_rxlane_rst_0 };
assign i_rx_rate_chng = {i_rx_rate_chng_3,i_rx_rate_chng_2,i_rx_rate_chng_1,i_rx_rate_chng_0};
assign i_rxckdiv = {i_rxckdiv_3 ,i_rxckdiv_2 ,i_rxckdiv_1 ,i_rxckdiv_0 };
assign i_pll_lock_rx = {i_pll_lock_rx_3,i_pll_lock_rx_2,i_pll_lock_rx_1,i_pll_lock_rx_0};
assign p_pcs_cb_rst = {i_pcs_cb_rst_3,i_pcs_cb_rst_2,i_pcs_cb_rst_1,i_pcs_cb_rst_0};
assign p_force_rxfsm_det = {i_force_rxfsm_det_3,i_force_rxfsm_det_2,i_force_rxfsm_det_1,i_force_rxfsm_det_0};
assign p_force_rxfsm_lsm = {i_force_rxfsm_lsm_3,i_force_rxfsm_lsm_2,i_force_rxfsm_lsm_1,i_force_rxfsm_lsm_0};
assign p_force_rxfsm_cdr = {i_force_rxfsm_cdr_3,i_force_rxfsm_cdr_2,i_force_rxfsm_cdr_1,i_force_rxfsm_cdr_0};
end
endgenerate
assign P_LX_SIGDET_STA = {P_RX_SIGDET_STATUS_3 , P_RX_SIGDET_STATUS_2 , P_RX_SIGDET_STATUS_1 , P_RX_SIGDET_STATUS_0 };
assign P_LX_CDR_ALIGN = {P_RX_READY_3, P_RX_READY_2, P_RX_READY_1, P_RX_READY_0 };
assign P_PCS_LSM_SYNCED = {P_PCS_LSM_SYNCED_3 , P_PCS_LSM_SYNCED_2 , P_PCS_LSM_SYNCED_1 , P_PCS_LSM_SYNCED_0 };
assign P_PCS_RX_MCB_STATUS = {P_PCS_RX_MCB_STATUS_3 , P_PCS_RX_MCB_STATUS_2 , P_PCS_RX_MCB_STATUS_1 , P_PCS_RX_MCB_STATUS_0 };
genvar i;
generate
for(i=0; i<4; i=i+1) begin:SYNC_RXLANE
//Sync Reset signal
ipml_hsst_rst_sync_v1_0 rxlane_rstn_sync (.clk(clk), .rst_n(i_rxlane_rstn[i]), .sig_async(1'b1), .sig_synced(s_rxlane_rstn[i]));
// ALOS, CDR_ALIGN, PCS_LSM_SYNCED sync per lane
ipml_hsst_rst_sync_v1_0 i_pll_lock_sync (.clk(clk), .rst_n(p_rxlane_rstn[i]), .sig_async(i_pll_lock_rx[i]), .sig_synced(s_pll_lock_rx[i]));
ipml_hsst_rst_sync_v1_0 sigdet_sync (.clk(clk), .rst_n(p_rxlane_rstn[i]), .sig_async(P_LX_SIGDET_STA[i]), .sig_synced(s_LX_SIGDET_STA[i]));
ipml_hsst_rst_sync_v1_0 cdr_align_sync (.clk(clk), .rst_n(p_rxlane_rstn[i]), .sig_async(P_LX_CDR_ALIGN[i]), .sig_synced(s_LX_CDR_ALIGN[i]));
ipml_hsst_rst_sync_v1_0 word_align_sync (.clk(clk), .rst_n(p_rxlane_rstn[i]), .sig_async(P_PCS_LSM_SYNCED[i]), .sig_synced(s_PCS_LSM_SYNCED[i]));
ipml_hsst_rst_sync_v1_0 bonding_sync (.clk(clk), .rst_n(p_rxlane_rstn[i]), .sig_async(P_PCS_RX_MCB_STATUS[i]), .sig_synced(s_P_PCS_RX_MCB_STATUS[i]));
// ALOS, CDR_ALIGN debounce per lane
ipml_hsst_rst_debounce_v1_0 #(.RISE_CNTR_WIDTH(SIGDET_DEB_RISE_CNTR_WIDTH), .RISE_CNTR_VALUE(SIGDET_DEB_RISE_CNTR_VALUE))
sigdet_deb(.clk(clk), .rst_n(p_rxlane_rstn[i]), .signal_b(s_LX_SIGDET_STA[i]), .signal_deb(s_LX_SIGDET_STA_deb[i]));
ipml_hsst_rst_debounce_v1_0 #(.RISE_CNTR_WIDTH(CDR_ALIGN_DEB_RISE_CNTR_WIDTH), .RISE_CNTR_VALUE(CDR_ALIGN_DEB_RISE_CNTR_VALUE))
cdr_align_deb (.clk(clk), .rst_n(p_rxlane_rstn[i]), .signal_b(s_LX_CDR_ALIGN[i]), .signal_deb(s_LX_CDR_ALIGN_deb[i]));
ipml_hsst_rst_debounce_v1_0 #(.RISE_CNTR_WIDTH(PLL_LOCK_RISE_CNTR_WIDTH), .RISE_CNTR_VALUE(PLL_LOCK_RISE_CNTR_VALUE))
i_pll_lock_deb (.clk(clk), .rst_n(p_rxlane_rstn[i]), .signal_b(s_pll_lock_rx[i]), .signal_deb(s_pll_lock_rx_deb[i]));
end
endgenerate
assign p_rxlane_rstn = {~P_LANE_RST_3,~P_LANE_RST_2,~P_LANE_RST_1,~P_LANE_RST_0} & s_rxlane_rstn;
assign sigdet = s_LX_SIGDET_STA_deb | p_force_rxfsm_det;
assign cdr_align = s_LX_CDR_ALIGN_deb | p_force_rxfsm_cdr;
assign word_align = s_PCS_LSM_SYNCED | p_force_rxfsm_lsm;
assign bonding = s_P_PCS_RX_MCB_STATUS | p_force_rxfsm_lsm;
//Lane 0
generate
if(CH0_RX_ENABLE=="TRUE") begin:RXLANE0_ENABLE
ipml_hsst_rxlane_rst_fsm_v1_1#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.CH_MULT_LANE_MODE (CH0_MULT_LANE_MODE ),
.CH_RXPCS_ALIGN_TIMER (CH0_RXPCS_ALIGN_TIMER ),
.CH_BYPASS_WORD_ALIGN (PCS_CH0_BYPASS_WORD_ALIGN ),
.CH_BYPASS_BONDING (PCS_CH0_BYPASS_BONDING ),
.CH_BYPASS_CTC (PCS_CH0_BYPASS_CTC ),
.LX_RX_CKDIV (LX_RX_CKDIV_0 ),
.PCS_RX_CLK_EXPLL_USE (PCS_RX_CLK_EXPLL_USE_CH0 )
) rxlane_fsm0 (
.clk (clk ),
.rst_n (p_rxlane_rstn [0] ),
.fifo_clr_en (fifo_clr_en [0] ),
.i_rx_rate_chng (i_rx_rate_chng [0] ),
.i_rxckdiv (i_rxckdiv [2:0] ),
.sigdet (sigdet [0] ),
.cdr_align (cdr_align [0] ),
.word_align (word_align [0] ),
.bonding (bonding [0] ),
.i_pcs_cb_rst (p_pcs_cb_rst [0] ),
.i_pll_lock_rx (s_pll_lock_rx_deb [0] ),
.P_RX_LANE_PD (P_RX_LANE_PD_0 ),
.P_RX_PMA_RST (P_RX_PMA_RST_0 ),
.P_PCS_RX_RST (P_PCS_RX_RST_0 ),
.P_RX_RATE (P_RX_RATE_0 ),
.P_PCS_CB_RST (P_PCS_CB_RST_0 ),
.o_rxckdiv_done (o_rxckdiv_done_0 ),
.o_rxlane_done (o_rxlane_done_0 ),
.fifoclr_sig (fifoclr_sig_0 )
);
end
else begin:RXLANE0_DISABLE
assign P_RX_LANE_PD_0 = 1'b1;
assign P_RX_PMA_RST_0 = 1'b1;
assign P_PCS_RX_RST_0 = 1'b1;
assign P_RX_RATE_0 = 3'b0;
assign P_PCS_CB_RST_0 = 1'b0;
assign o_rxckdiv_done_0 = 1'b0;
assign o_rxlane_done_0 = 1'b0;
end
endgenerate
//Lane 1
generate
if(CH1_RX_ENABLE=="TRUE") begin:RXLANE1_ENABLE
ipml_hsst_rxlane_rst_fsm_v1_1#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.CH_MULT_LANE_MODE (CH1_MULT_LANE_MODE ),
.CH_RXPCS_ALIGN_TIMER (CH1_RXPCS_ALIGN_TIMER ),
.CH_BYPASS_WORD_ALIGN (PCS_CH1_BYPASS_WORD_ALIGN ),
.CH_BYPASS_BONDING (PCS_CH1_BYPASS_BONDING ),
.CH_BYPASS_CTC (PCS_CH1_BYPASS_CTC ),
.LX_RX_CKDIV (LX_RX_CKDIV_1 ),
.PCS_RX_CLK_EXPLL_USE (PCS_RX_CLK_EXPLL_USE_CH1 )
) rxlane_fsm1 (
.clk (clk ),
.rst_n (p_rxlane_rstn [1] ),
.fifo_clr_en (fifo_clr_en [1] ),
.i_rx_rate_chng (i_rx_rate_chng [1] ),
.i_rxckdiv (i_rxckdiv [5:3] ),
.sigdet (sigdet [1] ),
.cdr_align (cdr_align [1] ),
.word_align (word_align [1] ),
.bonding (bonding [1] ),
.i_pcs_cb_rst (p_pcs_cb_rst [1] ),
.i_pll_lock_rx (s_pll_lock_rx_deb [1] ),
.P_RX_LANE_PD (P_RX_LANE_PD_1 ),
.P_RX_PMA_RST (P_RX_PMA_RST_1 ),
.P_PCS_RX_RST (P_PCS_RX_RST_1 ),
.P_RX_RATE (P_RX_RATE_1 ),
.P_PCS_CB_RST (P_PCS_CB_RST_1 ),
.o_rxckdiv_done (o_rxckdiv_done_1 ),
.o_rxlane_done (o_rxlane_done_1 ),
.fifoclr_sig (fifoclr_sig_1 )
);
end
else begin:RXLANE1_DISABLE
assign P_RX_LANE_PD_1 = 1'b1;
assign P_RX_PMA_RST_1 = 1'b1;
assign P_PCS_RX_RST_1 = 1'b1;
assign P_RX_RATE_1 = 3'b0;
assign P_PCS_CB_RST_1 = 1'b0;
assign o_rxckdiv_done_1 = 1'b0;
assign o_rxlane_done_1 = 1'b0;
end
endgenerate
//Lane 2
generate
if(CH2_RX_ENABLE=="TRUE") begin:RXLANE2_ENABLE
ipml_hsst_rxlane_rst_fsm_v1_1#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.CH_MULT_LANE_MODE (CH2_MULT_LANE_MODE ),
.CH_RXPCS_ALIGN_TIMER (CH2_RXPCS_ALIGN_TIMER ),
.CH_BYPASS_WORD_ALIGN (PCS_CH2_BYPASS_WORD_ALIGN ),
.CH_BYPASS_BONDING (PCS_CH2_BYPASS_BONDING ),
.CH_BYPASS_CTC (PCS_CH2_BYPASS_CTC ),
.LX_RX_CKDIV (LX_RX_CKDIV_2 ),
.PCS_RX_CLK_EXPLL_USE (PCS_RX_CLK_EXPLL_USE_CH2 )
) rxlane_fsm2 (
.clk (clk ),
.rst_n (p_rxlane_rstn [2] ),
.fifo_clr_en (fifo_clr_en [2] ),
.i_rx_rate_chng (i_rx_rate_chng [2] ),
.i_rxckdiv (i_rxckdiv [8:6] ),
.sigdet (sigdet [2] ),
.cdr_align (cdr_align [2] ),
.word_align (word_align [2] ),
.bonding (bonding [2] ),
.i_pcs_cb_rst (p_pcs_cb_rst [2] ),
.i_pll_lock_rx (s_pll_lock_rx_deb [2] ),
.P_RX_LANE_PD (P_RX_LANE_PD_2 ),
.P_RX_PMA_RST (P_RX_PMA_RST_2 ),
.P_PCS_RX_RST (P_PCS_RX_RST_2 ),
.P_RX_RATE (P_RX_RATE_2 ),
.P_PCS_CB_RST (P_PCS_CB_RST_2 ),
.o_rxckdiv_done (o_rxckdiv_done_2 ),
.o_rxlane_done (o_rxlane_done_2 ),
.fifoclr_sig (fifoclr_sig_2 )
);
end
else begin:RXLANE2_DISABLE
assign P_RX_LANE_PD_2 = 1'b1;
assign P_RX_PMA_RST_2 = 1'b1;
assign P_PCS_RX_RST_2 = 1'b1;
assign P_RX_RATE_2 = 3'b0;
assign P_PCS_CB_RST_2 = 1'b0;
assign o_rxckdiv_done_2 = 1'b0;
assign o_rxlane_done_2 = 1'b0;
end
endgenerate
//Lane 3
generate
if(CH3_RX_ENABLE=="TRUE") begin:RXLANE3_ENABLE
ipml_hsst_rxlane_rst_fsm_v1_1#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.CH_MULT_LANE_MODE (CH3_MULT_LANE_MODE ),
.CH_RXPCS_ALIGN_TIMER (CH3_RXPCS_ALIGN_TIMER ),
.CH_BYPASS_WORD_ALIGN (PCS_CH3_BYPASS_WORD_ALIGN ),
.CH_BYPASS_BONDING (PCS_CH3_BYPASS_BONDING ),
.CH_BYPASS_CTC (PCS_CH3_BYPASS_CTC ),
.LX_RX_CKDIV (LX_RX_CKDIV_3 ),
.PCS_RX_CLK_EXPLL_USE (PCS_RX_CLK_EXPLL_USE_CH3 )
) rxlane_fsm3 (
.clk (clk ),
.rst_n (p_rxlane_rstn [3] ),
.fifo_clr_en (fifo_clr_en [3] ),
.i_rx_rate_chng (i_rx_rate_chng [3] ),
.i_rxckdiv (i_rxckdiv [11:9] ),
.sigdet (sigdet [3] ),
.cdr_align (cdr_align [3] ),
.word_align (word_align [3] ),
.bonding (bonding [3] ),
.i_pcs_cb_rst (p_pcs_cb_rst [3] ),
.i_pll_lock_rx (s_pll_lock_rx_deb [3] ),
.P_RX_LANE_PD (P_RX_LANE_PD_3 ),
.P_RX_PMA_RST (P_RX_PMA_RST_3 ),
.P_PCS_RX_RST (P_PCS_RX_RST_3 ),
.P_RX_RATE (P_RX_RATE_3 ),
.P_PCS_CB_RST (P_PCS_CB_RST_3 ),
.o_rxckdiv_done (o_rxckdiv_done_3 ),
.o_rxlane_done (o_rxlane_done_3 ),
.fifoclr_sig (fifoclr_sig_3 )
);
end
else begin:RXLANE3_DISABLE
assign P_RX_LANE_PD_3 = 1'b1;
assign P_RX_PMA_RST_3 = 1'b1;
assign P_PCS_RX_RST_3 = 1'b1;
assign P_RX_RATE_3 = 3'b0;
assign P_PCS_CB_RST_3 = 1'b0;
assign o_rxckdiv_done_3 = 1'b0;
assign o_rxlane_done_3 = 1'b0;
end
endgenerate
assign fifoclr_sig = {fifoclr_sig_3,fifoclr_sig_2,fifoclr_sig_1,fifoclr_sig_0};
ipml_hsst_fifo_clr_v1_0#(
.CH0_RX_ENABLE (CH0_RX_ENABLE ), //TRUE:lane0 RX Reset Logic used, FALSE: lane0 RX Reset Logic remove
.CH1_RX_ENABLE (CH1_RX_ENABLE ), //TRUE:lane1 RX Reset Logic used, FALSE: lane1 RX Reset Logic remove
.CH2_RX_ENABLE (CH2_RX_ENABLE ), //TRUE:lane2 RX Reset Logic used, FALSE: lane2 RX Reset Logic remove
.CH3_RX_ENABLE (CH3_RX_ENABLE ), //TRUE:lane3 RX Reset Logic used, FALSE: lane3 RX Reset Logic remove
.CH0_MULT_LANE_MODE (CH0_MULT_LANE_MODE ), //Lane0 --> 1: Singel Lane 2:Two Lane 4:Four Lane
.CH1_MULT_LANE_MODE (CH1_MULT_LANE_MODE ), //Lane1 --> 1: Singel Lane 2:Two Lane 4:Four Lane
.CH2_MULT_LANE_MODE (CH2_MULT_LANE_MODE ), //Lane2 --> 1: Singel Lane 2:Two Lane 4:Four Lane
.CH3_MULT_LANE_MODE (CH3_MULT_LANE_MODE ), //Lane3 --> 1: Singel Lane 2:Two Lane 4:Four Lane
.PCS_CH0_BYPASS_BONDING (PCS_CH0_BYPASS_BONDING ), //TRUE: Lane0 Bypass Channel Bonding, FALSE: Lane0 No Bypass Channel Bonding
.PCS_CH1_BYPASS_BONDING (PCS_CH1_BYPASS_BONDING ), //TRUE: Lane1 Bypass Channel Bonding, FALSE: Lane1 No Bypass Channel Bonding
.PCS_CH2_BYPASS_BONDING (PCS_CH2_BYPASS_BONDING ), //TRUE: Lane2 Bypass Channel Bonding, FALSE: Lane2 No Bypass Channel Bonding
.PCS_CH3_BYPASS_BONDING (PCS_CH3_BYPASS_BONDING ) //TRUE: Lane3 Bypass Channel Bonding, FALSE: Lane3 No Bypass Channel Bonding
) fifo_clr (
.clk (clk ),
.rst_n (p_rxlane_rstn ),
.i_hsst_fifo_clr_0 (i_hsst_fifo_clr_0 ),
.i_hsst_fifo_clr_1 (i_hsst_fifo_clr_1 ),
.i_hsst_fifo_clr_2 (i_hsst_fifo_clr_2 ),
.i_hsst_fifo_clr_3 (i_hsst_fifo_clr_3 ),
.cdr_align (s_LX_CDR_ALIGN_deb ),
.rxlane_done (fifoclr_sig ),
.fifo_clr_en (fifo_clr_en )
);
endmodule |
module ipml_hsst_rst_tx_v1_0#(
parameter FREE_CLOCK_FREQ = 100 , //Unit is MHz, free clock freq from GUI Freq: 0~200MHz
parameter CH0_TX_ENABLE = "TRUE" , //TRUE:lane0 TX Reset Logic used, FALSE: lane0 TX Reset Logic remove
parameter CH1_TX_ENABLE = "TRUE" , //TRUE:lane1 TX Reset Logic used, FALSE: lane1 TX Reset Logic remove
parameter CH2_TX_ENABLE = "TRUE" , //TRUE:lane2 TX Reset Logic used, FALSE: lane2 TX Reset Logic remove
parameter CH3_TX_ENABLE = "TRUE" , //TRUE:lane3 TX Reset Logic used, FALSE: lane3 TX Reset Logic remove
parameter CH0_MULT_LANE_MODE = 1 , //Lane0 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH1_MULT_LANE_MODE = 1 , //Lane1 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH2_MULT_LANE_MODE = 1 , //Lane2 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH3_MULT_LANE_MODE = 1 , //Lane3 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter P_LX_TX_CKDIV_0 = 0 ,
parameter P_LX_TX_CKDIV_1 = 0 ,
parameter P_LX_TX_CKDIV_2 = 0 ,
parameter P_LX_TX_CKDIV_3 = 0 ,
parameter CH0_TX_PLL_SEL = 0 ,//Lane0 --> 1:PLL1 0:PLL0
parameter CH1_TX_PLL_SEL = 0 ,//Lane1 --> 1:PLL1 0:PLL0
parameter CH2_TX_PLL_SEL = 0 ,//Lane2 --> 1:PLL1 0:PLL0
parameter CH3_TX_PLL_SEL = 0 ,//Lane3 --> 1:PLL1 0:PLL0
parameter PCS_TX_CLK_EXPLL_USE_CH0 = "FALSE" ,//TRUE: Fabric PLL USE
parameter PCS_TX_CLK_EXPLL_USE_CH1 = "FALSE" ,
parameter PCS_TX_CLK_EXPLL_USE_CH2 = "FALSE" ,
parameter PCS_TX_CLK_EXPLL_USE_CH3 = "FALSE"
)(
//User Side
input wire clk ,
input wire i_txlane_rst_0 ,
input wire i_txlane_rst_1 ,
input wire i_txlane_rst_2 ,
input wire i_txlane_rst_3 ,
input wire i_pll_done_0 ,
input wire i_pll_done_1 ,
input wire P_LANE_RST_0 ,
input wire P_LANE_RST_1 ,
input wire P_LANE_RST_2 ,
input wire P_LANE_RST_3 ,
input wire i_tx_rate_chng_0 ,
input wire i_tx_rate_chng_1 ,
input wire i_tx_rate_chng_2 ,
input wire i_tx_rate_chng_3 ,
input wire i_pll_lock_tx_0 ,
input wire i_pll_lock_tx_1 ,
input wire i_pll_lock_tx_2 ,
input wire i_pll_lock_tx_3 ,
input wire [2 : 0] i_txckdiv_0 ,
input wire [2 : 0] i_txckdiv_1 ,
input wire [2 : 0] i_txckdiv_2 ,
input wire [2 : 0] i_txckdiv_3 ,
output wire o_txlane_done_0 ,
output wire o_txlane_done_1 ,
output wire o_txlane_done_2 ,
output wire o_txlane_done_3 ,
output wire o_txckdiv_done_0 ,
output wire o_txckdiv_done_1 ,
output wire o_txckdiv_done_2 ,
output wire o_txckdiv_done_3 ,
output wire P_TX_LANE_PD_0 ,
output wire P_TX_LANE_PD_1 ,
output wire P_TX_LANE_PD_2 ,
output wire P_TX_LANE_PD_3 ,
output wire [2 : 0] P_TX_RATE_0 ,
output wire [2 : 0] P_TX_RATE_1 ,
output wire [2 : 0] P_TX_RATE_2 ,
output wire [2 : 0] P_TX_RATE_3 ,
output wire P_TX_PMA_RST_0 ,
output wire P_TX_PMA_RST_1 ,
output wire P_TX_PMA_RST_2 ,
output wire P_TX_PMA_RST_3 ,
output wire P_PCS_TX_RST_0 ,
output wire P_PCS_TX_RST_1 ,
output wire P_PCS_TX_RST_2 ,
output wire P_PCS_TX_RST_3 ,
output reg P_LANE_SYNC_0 ,
output reg P_LANE_SYNC_1 ,
output reg P_LANE_SYNC_EN_0 ,
output reg P_LANE_SYNC_EN_1 ,
output reg P_RATE_CHANGE_TCLK_ON_0 ,
output reg P_RATE_CHANGE_TCLK_ON_1
);
localparam PLL_LOCK_RISE_CNTR_WIDTH = 12 ;
`ifdef IPML_HSST_SPEEDUP_SIM
localparam PLL_LOCK_RISE_CNTR_VALUE = 20 ;
`else
localparam PLL_LOCK_RISE_CNTR_VALUE = 2048;
`endif
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
wire [4-1 :0] i_tx_rate_chng ;
wire [4-1 :0] i_txlane_rstn ;
wire [4-1 :0] i_pll_lock_tx ;
wire [4*3-1 :0] l_txckdiv ;
wire [4-1 :0] s_txlane_rstn ;
wire [4-1 :0] l_tx_lane_rstn ;
wire [4-1 :0] s_pll_lock_tx ;
wire [4-1 :0] s_pll_lock_tx_deb ;
wire [4-1 :0] l_pll_lock_tx_deb ;
wire pll0_sync_ch2 ;
wire pll0_sync_ch3 ;
wire pll0_sync_en_ch2 ;
wire pll0_sync_en_ch3 ;
wire pll1_sync_ch2 ;
wire pll1_sync_ch3 ;
wire pll1_sync_en_ch2 ;
wire pll1_sync_en_ch3 ;
wire pll0_rate_change_ch2;
wire pll0_rate_change_ch3;
wire pll1_rate_change_ch2;
wire pll1_rate_change_ch3;
wire LANE_SYNC_0 ;
wire LANE_SYNC_1 ;
wire LANE_SYNC_EN_0 ;
wire LANE_SYNC_EN_1 ;
wire RATE_CHANGE_TCLK_ON_0 ;
wire RATE_CHANGE_TCLK_ON_1 ;
//txfsm output
wire [4-1 :0] o_tx_lane_pd ;
wire [4-1 :0] o_lane_sync ;
wire [4-1 :0] o_lane_sync_en ;
wire [4-1 :0] o_rate_change_on ;
wire [4*3-1 :0] o_tx_ckdiv ;
wire [4-1 :0] o_tx_pma_rst ;
wire [4-1 :0] o_pcs_tx_rst ;
wire [4-1 :0] p_txlane_done ;
wire [4-1 :0] p_txckdiv_done ;
//tx output
wire [4-1 :0] p_tx_lane_pd ;
wire [4-1 :0] p_lane_sync ;
wire [4-1 :0] p_lane_sync_en ;
wire [4-1 :0] p_rate_change_on ;
wire [4*3-1 :0] p_tx_ckdiv ;
wire [4-1 :0] p_tx_pma_rst ;
wire [4-1 :0] p_pcs_tx_rst ;
wire [4-1 :0] o_txlane_done ;
wire [4-1 :0] o_txckdiv_done ;
//for rst sync
reg lane_sync_0_ff ;
reg lane_sync_1_ff ;
reg lane_sync_en_0_ff ;
reg lane_sync_en_1_ff ;
reg rate_change_tclk_on_0_ff ;
reg rate_change_tclk_on_1_ff ;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
//signal generate
assign i_txlane_rstn = {~i_txlane_rst_3,~i_txlane_rst_2,~i_txlane_rst_1,~i_txlane_rst_0};
assign i_pll_lock_tx = {i_pll_lock_tx_3,i_pll_lock_tx_2,i_pll_lock_tx_1,i_pll_lock_tx_0};
//Sync signal and Debounce signal
genvar i;
generate
for(i=0; i<4; i=i+1) begin:SYNC_TXLANE
ipml_hsst_rst_sync_v1_0 txlane_rstn_sync (.clk(clk), .rst_n(i_txlane_rstn[i]), .sig_async(1'b1), .sig_synced(s_txlane_rstn[i]));
ipml_hsst_rst_sync_v1_0 i_pll_lock_rstn_sync (.clk(clk), .rst_n(l_tx_lane_rstn[i]), .sig_async(i_pll_lock_tx[i]), .sig_synced(s_pll_lock_tx[i]));
ipml_hsst_rst_debounce_v1_0 #(.RISE_CNTR_WIDTH(PLL_LOCK_RISE_CNTR_WIDTH), .RISE_CNTR_VALUE(PLL_LOCK_RISE_CNTR_VALUE))
pll_lock_deb (.clk(clk), .rst_n(l_tx_lane_rstn[i]), .signal_b(s_pll_lock_tx[i]), .signal_deb(s_pll_lock_tx_deb[i]));
end
endgenerate
//----- Instance Txlane Rst Fsm Module -----------
//Lane0
generate
if(CH0_TX_ENABLE=="TRUE") begin : TXLANE0_ENABLE //Lane is Enable
ipml_hsst_txlane_rst_fsm_v1_0#(
.LANE_BONDING (CH0_MULT_LANE_MODE ),
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.P_LX_TX_CKDIV (P_LX_TX_CKDIV_0 ),
.PCS_TX_CLK_EXPLL_USE_CH (PCS_TX_CLK_EXPLL_USE_CH0 )
) txlane_rst_fsm0 (
.clk (clk ),
.rst_n (l_tx_lane_rstn [0 ] ),
.i_tx_rate_chng (i_tx_rate_chng [0 ] ),
.i_txckdiv (l_txckdiv [0*3 +:3] ),
.i_pll_lock_tx (l_pll_lock_tx_deb [0 ] ),
.P_TX_LANE_PD (o_tx_lane_pd [0 ] ),
.P_TX_RATE (o_tx_ckdiv [0*3 +:3] ),
.P_TX_PMA_RST (o_tx_pma_rst [0 ] ),
.P_PCS_TX_RST (o_pcs_tx_rst [0 ] ),
.o_txlane_done (p_txlane_done [0 ] ),
.o_txckdiv_done (p_txckdiv_done [0 ] ),
.lane_sync (o_lane_sync [0 ] ),
.lane_sync_en (o_lane_sync_en [0 ] ),
.rate_change_on (o_rate_change_on [0 ] )
);
end
else begin : TXLANE0_DISABLE //Lane is disable
assign o_tx_lane_pd [0] = 1'b1;
assign o_lane_sync [0] = 1'b0;
assign o_lane_sync_en [0] = 1'b0;
assign o_rate_change_on [0] = 1'b1;
assign o_tx_ckdiv [0*3 +:3] = 3'b0;
assign o_tx_pma_rst [0] = 1'b1;
assign o_pcs_tx_rst [0] = 1'b1;
assign p_txlane_done [0] = 1'b0;
assign p_txckdiv_done [0] = 1'b0;
end
endgenerate
//Lane1
generate
if((CH1_TX_ENABLE=="TRUE") && (CH1_MULT_LANE_MODE == 1)) begin : TXLANE1_ENABLE //Lane is Enable and no bonding
ipml_hsst_txlane_rst_fsm_v1_0#(
.LANE_BONDING (CH1_MULT_LANE_MODE ),
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.P_LX_TX_CKDIV (P_LX_TX_CKDIV_1 ),
.PCS_TX_CLK_EXPLL_USE_CH (PCS_TX_CLK_EXPLL_USE_CH1 )
) txlane_rst_fsm1 (
.clk (clk ),
.rst_n (l_tx_lane_rstn [1 ] ),
.i_tx_rate_chng (i_tx_rate_chng [1 ] ),
.i_txckdiv (l_txckdiv [1*3 +:3] ),
.i_pll_lock_tx (l_pll_lock_tx_deb [1 ] ),
.P_TX_LANE_PD (o_tx_lane_pd [1 ] ),
.P_TX_RATE (o_tx_ckdiv [1*3 +:3] ),
.P_TX_PMA_RST (o_tx_pma_rst [1 ] ),
.P_PCS_TX_RST (o_pcs_tx_rst [1 ] ),
.o_txlane_done (p_txlane_done [1 ] ),
.o_txckdiv_done (p_txckdiv_done [1 ] ),
.lane_sync (o_lane_sync [1 ] ),
.lane_sync_en (o_lane_sync_en [1 ] ),
.rate_change_on (o_rate_change_on [1 ] )
);
end
else begin : TXLANE1_DISABLE //Lane is disable or use Lane0 fsm
assign o_tx_lane_pd [1] = 1'b1;
assign o_lane_sync [1] = 1'b0;
assign o_lane_sync_en [1] = 1'b0;
assign o_rate_change_on [1] = 1'b1;
assign o_tx_ckdiv [1*3 +:3] = 3'b0;
assign o_tx_pma_rst [1] = 1'b1;
assign o_pcs_tx_rst [1] = 1'b1;
assign p_txlane_done [1] = 1'b0;
assign p_txckdiv_done [1] = 1'b0;
end
endgenerate
//Lane2
generate
if((CH2_TX_ENABLE=="TRUE") && (CH0_MULT_LANE_MODE != 4 )) begin : TXLANE2_ENABLE //Lane is Enable and no 4LANE bonding
ipml_hsst_txlane_rst_fsm_v1_0#(
.LANE_BONDING (CH2_MULT_LANE_MODE ),
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.P_LX_TX_CKDIV (P_LX_TX_CKDIV_2 ),
.PCS_TX_CLK_EXPLL_USE_CH (PCS_TX_CLK_EXPLL_USE_CH2 )
) txlane_rst_fsm2 (
.clk (clk ),
.rst_n (l_tx_lane_rstn [2 ] ),
.i_tx_rate_chng (i_tx_rate_chng [2 ] ),
.i_txckdiv (l_txckdiv [2*3 +:3] ),
.i_pll_lock_tx (l_pll_lock_tx_deb [2 ] ),
.P_TX_LANE_PD (o_tx_lane_pd [2 ] ),
.P_TX_RATE (o_tx_ckdiv [2*3 +:3] ),
.P_TX_PMA_RST (o_tx_pma_rst [2 ] ),
.P_PCS_TX_RST (o_pcs_tx_rst [2 ] ),
.o_txlane_done (p_txlane_done [2 ] ),
.o_txckdiv_done (p_txckdiv_done [2 ] ),
.lane_sync (o_lane_sync [2 ] ),
.lane_sync_en (o_lane_sync_en [2 ] ),
.rate_change_on (o_rate_change_on [2 ] )
);
end
else begin : TXLANE2_DISABLE //Lane is disable or use Lane0 fsm
assign o_tx_lane_pd [2] = 1'b1;
assign o_lane_sync [2] = 1'b0;
assign o_lane_sync_en [2] = 1'b0;
assign o_rate_change_on [2] = 1'b1;
assign o_tx_ckdiv [2*3+:3] = 3'b0;
assign o_tx_pma_rst [2] = 1'b1;
assign o_pcs_tx_rst [2] = 1'b1;
assign p_txlane_done [2] = 1'b0;
assign p_txckdiv_done [2] = 1'b0;
end
endgenerate
//Lane3
generate
if((CH3_TX_ENABLE=="TRUE") && (CH3_MULT_LANE_MODE == 1)) begin : TXLANE3_ENABLE //Lane is Enable and no bonding
ipml_hsst_txlane_rst_fsm_v1_0#(
.LANE_BONDING (CH3_MULT_LANE_MODE ),
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.P_LX_TX_CKDIV (P_LX_TX_CKDIV_3 ),
.PCS_TX_CLK_EXPLL_USE_CH (PCS_TX_CLK_EXPLL_USE_CH3 )
) txlane_rst_fsm3 (
.clk (clk ),
.rst_n (l_tx_lane_rstn [3 ] ),
.i_tx_rate_chng (i_tx_rate_chng [3 ] ),
.i_txckdiv (l_txckdiv [3*3 +:3] ),
.i_pll_lock_tx (l_pll_lock_tx_deb [3 ] ),
.P_TX_LANE_PD (o_tx_lane_pd [3 ] ),
.P_TX_RATE (o_tx_ckdiv [3*3 +:3] ),
.P_TX_PMA_RST (o_tx_pma_rst [3 ] ),
.P_PCS_TX_RST (o_pcs_tx_rst [3 ] ),
.o_txlane_done (p_txlane_done [3 ] ),
.o_txckdiv_done (p_txckdiv_done [3 ] ),
.lane_sync (o_lane_sync [3 ] ),
.lane_sync_en (o_lane_sync_en [3 ] ),
.rate_change_on (o_rate_change_on [3 ] )
);
end
else begin : TXLANE3_DISABLE //Lane is disable
assign o_tx_lane_pd [3] = 1'b1;
assign o_lane_sync [3] = 1'b0;
assign o_lane_sync_en [3] = 1'b0;
assign o_rate_change_on [3] = 1'b1;
assign o_tx_ckdiv [3*3+:3] = 3'b0;
assign o_tx_pma_rst [3] = 1'b1;
assign o_pcs_tx_rst [3] = 1'b1;
assign p_txlane_done [3] = 1'b0;
assign p_txckdiv_done [3] = 1'b0;
end
endgenerate
generate
if(CH0_MULT_LANE_MODE==4) begin:FOUR_LANE_MODE
//From USER
assign l_tx_lane_rstn = {3'b0,~P_LANE_RST_0 & s_txlane_rstn[0]}; //From lane0 control signal
assign i_tx_rate_chng = {3'b0,i_tx_rate_chng_0};
assign l_txckdiv = {9'b0,i_txckdiv_0};
assign l_pll_lock_tx_deb = {3'b0,s_pll_lock_tx_deb[0]};
//To HSST
assign p_tx_lane_pd = {4{o_tx_lane_pd [0]}};
assign p_lane_sync = {4{o_lane_sync [0]}};
assign p_lane_sync_en = {4{o_lane_sync_en [0]}};
assign p_rate_change_on = {4{o_rate_change_on [0]}};
assign p_tx_ckdiv = {4{o_tx_ckdiv [2:0]}};
assign p_tx_pma_rst = {4{o_tx_pma_rst [0]}};
assign p_pcs_tx_rst = {4{o_pcs_tx_rst [0]}};
assign o_txlane_done = {4{p_txlane_done [0]}};
assign o_txckdiv_done = {4{p_txckdiv_done [0]}};
end
else if(CH0_MULT_LANE_MODE==2 && CH2_MULT_LANE_MODE==2) begin: TWO_LANE_MODE
//From USER
assign l_tx_lane_rstn = {1'b0,~P_LANE_RST_2 & s_txlane_rstn[2],1'b0,~P_LANE_RST_0 & s_txlane_rstn[0]};
assign i_tx_rate_chng = {1'b0,i_tx_rate_chng_2,1'b0,i_tx_rate_chng_0};
assign l_txckdiv = {3'b0,i_txckdiv_2,3'b0,i_txckdiv_0};
assign l_pll_lock_tx_deb = {1'b0,s_pll_lock_tx_deb[2],1'b0,s_pll_lock_tx_deb[0]};
//To HSST
assign p_tx_lane_pd = {{2{o_tx_lane_pd [2]}},{2{o_tx_lane_pd [0]}}};
assign p_lane_sync = {{2{o_lane_sync [2]}},{2{o_lane_sync [0]}}};
assign p_lane_sync_en = {{2{o_lane_sync_en [2]}},{2{o_lane_sync_en [0]}}};
assign p_rate_change_on = {{2{o_rate_change_on [2]}},{2{o_rate_change_on [0]}}};
assign p_tx_ckdiv = {{2{o_tx_ckdiv [8:6]}},{2{o_tx_ckdiv [2:0]}}};
assign p_tx_pma_rst = {{2{o_tx_pma_rst [2]}},{2{o_tx_pma_rst [0]}}};
assign p_pcs_tx_rst = {{2{o_pcs_tx_rst [2]}},{2{o_pcs_tx_rst [0]}}};
assign o_txlane_done = {{2{p_txlane_done [2]}},{2{p_txlane_done [0]}}};
assign o_txckdiv_done = {{2{p_txckdiv_done [2]}},{2{p_txckdiv_done [0]}}};
end
else if(CH0_MULT_LANE_MODE==2) begin:TWO_LANE_MODE0
//From USER
assign l_tx_lane_rstn = {~P_LANE_RST_3 & s_txlane_rstn[3],~P_LANE_RST_2 & s_txlane_rstn[2],1'b0,~P_LANE_RST_0 & s_txlane_rstn[0]};
assign i_tx_rate_chng = {i_tx_rate_chng_3,i_tx_rate_chng_2,1'b0,i_tx_rate_chng_0};
assign l_txckdiv = {i_txckdiv_3,i_txckdiv_2,3'b0,i_txckdiv_0};
assign l_pll_lock_tx_deb = {s_pll_lock_tx_deb[3],s_pll_lock_tx_deb[2],1'b0,s_pll_lock_tx_deb[0]};
//To HSST
assign p_tx_lane_pd = {o_tx_lane_pd [3],o_tx_lane_pd [2],{2{o_tx_lane_pd [0]}}};
assign p_lane_sync = {o_lane_sync [3],o_lane_sync [2],{2{o_lane_sync [0]}}};
assign p_lane_sync_en = {o_lane_sync_en [3],o_lane_sync_en [2],{2{o_lane_sync_en [0]}}};
assign p_rate_change_on = {o_rate_change_on [3],o_rate_change_on [2],{2{o_rate_change_on [0]}}};
assign p_tx_ckdiv = {o_tx_ckdiv [11:9],o_tx_ckdiv [8:6],{2{o_tx_ckdiv [2:0]}}};
assign p_tx_pma_rst = {o_tx_pma_rst [3],o_tx_pma_rst [2],{2{o_tx_pma_rst [0]}}};
assign p_pcs_tx_rst = {o_pcs_tx_rst [3],o_pcs_tx_rst [2],{2{o_pcs_tx_rst [0]}}};
assign o_txlane_done = {p_txlane_done [3],p_txlane_done [2],{2{p_txlane_done [0]}}};
assign o_txckdiv_done = {p_txckdiv_done [3],p_txckdiv_done [2],{2{p_txckdiv_done [0]}}};
end
else if(CH2_MULT_LANE_MODE==2) begin:TWO_LANE_MODE1
//From USER
assign l_tx_lane_rstn = {1'b0,~P_LANE_RST_2 & s_txlane_rstn[2],~P_LANE_RST_1 & s_txlane_rstn[1],~P_LANE_RST_0 & s_txlane_rstn[0]};
assign i_tx_rate_chng = {1'b0,i_tx_rate_chng_2,i_tx_rate_chng_1,i_tx_rate_chng_0};
assign l_txckdiv = {3'b0,i_txckdiv_2,i_txckdiv_1,i_txckdiv_0};
assign l_pll_lock_tx_deb = {1'b0,s_pll_lock_tx_deb[2],s_pll_lock_tx_deb[1],s_pll_lock_tx_deb[0]};
//To HSST
assign p_tx_lane_pd = {{2{o_tx_lane_pd [2]}},o_tx_lane_pd [1],o_tx_lane_pd [0]};
assign p_lane_sync = {{2{o_lane_sync [2]}},o_lane_sync [1],o_lane_sync [0]};
assign p_lane_sync_en = {{2{o_lane_sync_en [2]}},o_lane_sync_en [1],o_lane_sync_en [0]};
assign p_rate_change_on = {{2{o_rate_change_on [2]}},o_rate_change_on [1],o_rate_change_on [0]};
assign p_tx_ckdiv = {{2{o_tx_ckdiv [8:6]}},o_tx_ckdiv [5:3],o_tx_ckdiv [2:0]};
assign p_tx_pma_rst = {{2{o_tx_pma_rst [2]}},o_tx_pma_rst [1],o_tx_pma_rst [0]};
assign p_pcs_tx_rst = {{2{o_pcs_tx_rst [2]}},o_pcs_tx_rst [1],o_pcs_tx_rst [0]};
assign o_txlane_done = {{2{p_txlane_done [2]}},p_txlane_done [1],p_txlane_done [0]};
assign o_txckdiv_done = {{2{p_txckdiv_done [2]}},p_txckdiv_done [1],p_txckdiv_done [0]};
end
else begin:ONE_LANE_MODE
//From USER
assign l_tx_lane_rstn = {~P_LANE_RST_3 & s_txlane_rstn[3],~P_LANE_RST_2 & s_txlane_rstn[2],~P_LANE_RST_1 & s_txlane_rstn[1],~P_LANE_RST_0 & s_txlane_rstn[0]};
assign i_tx_rate_chng = {i_tx_rate_chng_3,i_tx_rate_chng_2,i_tx_rate_chng_1,i_tx_rate_chng_0};
assign l_txckdiv = {i_txckdiv_3,i_txckdiv_2,i_txckdiv_1,i_txckdiv_0};
assign l_pll_lock_tx_deb = {s_pll_lock_tx_deb[3],s_pll_lock_tx_deb[2],s_pll_lock_tx_deb[1],s_pll_lock_tx_deb[0]};
//To HSST
assign p_tx_lane_pd = {o_tx_lane_pd [3],o_tx_lane_pd [2],o_tx_lane_pd [1],o_tx_lane_pd [0]};
assign p_lane_sync = {o_lane_sync [3],o_lane_sync [2],o_lane_sync [1],o_lane_sync [0]};
assign p_lane_sync_en = {o_lane_sync_en [3],o_lane_sync_en [2],o_lane_sync_en [1],o_lane_sync_en [0]};
assign p_rate_change_on = {o_rate_change_on [3],o_rate_change_on [2],o_rate_change_on [1],o_rate_change_on [0]};
assign p_tx_ckdiv = {o_tx_ckdiv [11:9],o_tx_ckdiv [8:6],o_tx_ckdiv [5:3],o_tx_ckdiv [2:0]};
assign p_tx_pma_rst = {o_tx_pma_rst [3],o_tx_pma_rst [2],o_tx_pma_rst [1],o_tx_pma_rst [0]};
assign p_pcs_tx_rst = {o_pcs_tx_rst [3],o_pcs_tx_rst [2],o_pcs_tx_rst [1],o_pcs_tx_rst [0]};
assign o_txlane_done = {p_txlane_done [3],p_txlane_done [2],p_txlane_done [1],p_txlane_done [0]};
assign o_txckdiv_done = {p_txckdiv_done [3],p_txckdiv_done [2],p_txckdiv_done [1],p_txckdiv_done [0]};
end
endgenerate
assign o_txlane_done_0 = o_txlane_done[0];
assign o_txlane_done_1 = o_txlane_done[1];
assign o_txlane_done_2 = o_txlane_done[2];
assign o_txlane_done_3 = o_txlane_done[3];
assign o_txckdiv_done_0 = o_txckdiv_done[0];
assign o_txckdiv_done_1 = o_txckdiv_done[1];
assign o_txckdiv_done_2 = o_txckdiv_done[2];
assign o_txckdiv_done_3 = o_txckdiv_done[3];
assign P_TX_LANE_PD_0 = p_tx_lane_pd [0];
assign P_TX_LANE_PD_1 = p_tx_lane_pd [1];
assign P_TX_LANE_PD_2 = p_tx_lane_pd [2];
assign P_TX_LANE_PD_3 = p_tx_lane_pd [3];
assign P_TX_RATE_0 = p_tx_ckdiv [2:0];
assign P_TX_RATE_1 = p_tx_ckdiv [5:3];
assign P_TX_RATE_2 = p_tx_ckdiv [8:6];
assign P_TX_RATE_3 = p_tx_ckdiv [11:9];
assign P_TX_PMA_RST_0 = p_tx_pma_rst [0];
assign P_TX_PMA_RST_1 = p_tx_pma_rst [1];
assign P_TX_PMA_RST_2 = p_tx_pma_rst [2];
assign P_TX_PMA_RST_3 = p_tx_pma_rst [3];
assign P_PCS_TX_RST_0 = p_pcs_tx_rst [0];
assign P_PCS_TX_RST_1 = p_pcs_tx_rst [1];
assign P_PCS_TX_RST_2 = p_pcs_tx_rst [2];
assign P_PCS_TX_RST_3 = p_pcs_tx_rst [3];
//PLL SYNC && RATE_CHANGE generate
assign pll0_sync_ch2 = (CH2_TX_PLL_SEL == 0) ? p_lane_sync[2] : 1'b0 ;
assign pll0_sync_ch3 = (CH3_TX_PLL_SEL == 0) ? p_lane_sync[3] : 1'b0 ;
assign pll1_sync_ch2 = (CH2_TX_PLL_SEL == 0) ? 1'b0 : p_lane_sync[2] ;
assign pll1_sync_ch3 = (CH3_TX_PLL_SEL == 0) ? 1'b0 : p_lane_sync[3] ;
assign LANE_SYNC_0 = p_lane_sync[0] || p_lane_sync[1] || pll0_sync_ch2 || pll0_sync_ch3 ;
assign LANE_SYNC_1 = pll1_sync_ch2 || pll1_sync_ch3 ;
assign pll0_sync_en_ch2 = (CH2_TX_PLL_SEL == 0) ? p_lane_sync_en[2] : 1'b0 ;
assign pll0_sync_en_ch3 = (CH3_TX_PLL_SEL == 0) ? p_lane_sync_en[3] : 1'b0 ;
assign pll1_sync_en_ch2 = (CH2_TX_PLL_SEL == 0) ? 1'b0 : p_lane_sync_en[2] ;
assign pll1_sync_en_ch3 = (CH3_TX_PLL_SEL == 0) ? 1'b0 : p_lane_sync_en[3] ;
assign LANE_SYNC_EN_0 = p_lane_sync_en[0] || p_lane_sync_en[1] || pll0_sync_en_ch2 || pll0_sync_en_ch3 ;
assign LANE_SYNC_EN_1 = pll1_sync_en_ch2 || pll1_sync_en_ch3 ;
assign pll0_rate_change_ch2 = (CH2_TX_PLL_SEL == 0) ? p_rate_change_on[2] : 1'b1 ;
assign pll0_rate_change_ch3 = (CH3_TX_PLL_SEL == 0) ? p_rate_change_on[3] : 1'b1 ;
assign pll1_rate_change_ch2 = (CH2_TX_PLL_SEL == 0) ? 1'b1 : p_rate_change_on[2] ;
assign pll1_rate_change_ch3 = (CH3_TX_PLL_SEL == 0) ? 1'b1 : p_rate_change_on[3] ;
assign RATE_CHANGE_TCLK_ON_0 = p_rate_change_on[0] && p_rate_change_on[1] && pll0_rate_change_ch2 && pll0_rate_change_ch3 ;
assign RATE_CHANGE_TCLK_ON_1 = pll1_rate_change_ch2 && pll1_rate_change_ch3 ;
always @ (posedge clk or negedge i_pll_done_0) begin
if(!i_pll_done_0)
lane_sync_0_ff <= 1'b0 ;
else
lane_sync_0_ff <= LANE_SYNC_0 ;
end
always @ (posedge clk or negedge i_pll_done_0) begin
if(!i_pll_done_0)
P_LANE_SYNC_0 <= 1'b0 ;
else
P_LANE_SYNC_0 <= lane_sync_0_ff;
end
always @ (posedge clk or negedge i_pll_done_0) begin
if(!i_pll_done_0)
lane_sync_en_0_ff <= 1'b0 ;
else
lane_sync_en_0_ff <= LANE_SYNC_EN_0;
end
always @ (posedge clk or negedge i_pll_done_0) begin
if(!i_pll_done_0)
P_LANE_SYNC_EN_0 <= 1'b0 ;
else
P_LANE_SYNC_EN_0 <= lane_sync_en_0_ff;
end
always @ (posedge clk or negedge i_pll_done_0) begin
if(!i_pll_done_0)
rate_change_tclk_on_0_ff <= 1'b0 ;
else
rate_change_tclk_on_0_ff <= RATE_CHANGE_TCLK_ON_0;
end
always @ (posedge clk or negedge i_pll_done_0) begin
if(!i_pll_done_0)
P_RATE_CHANGE_TCLK_ON_0 <= 1'b0 ;
else
P_RATE_CHANGE_TCLK_ON_0 <= rate_change_tclk_on_0_ff;
end
always @ (posedge clk or negedge i_pll_done_1) begin
if(!i_pll_done_1)
lane_sync_1_ff <= 1'b0 ;
else
lane_sync_1_ff <= LANE_SYNC_1 ;
end
always @ (posedge clk or negedge i_pll_done_1) begin
if(!i_pll_done_1)
P_LANE_SYNC_1 <= 1'b0 ;
else
P_LANE_SYNC_1 <= lane_sync_1_ff;
end
always @ (posedge clk or negedge i_pll_done_1) begin
if(!i_pll_done_1)
lane_sync_en_1_ff <= 1'b0 ;
else
lane_sync_en_1_ff <= LANE_SYNC_EN_1;
end
always @ (posedge clk or negedge i_pll_done_1) begin
if(!i_pll_done_1)
P_LANE_SYNC_EN_1 <= 1'b0 ;
else
P_LANE_SYNC_EN_1 <= lane_sync_en_1_ff;
end
always @ (posedge clk or negedge i_pll_done_1) begin
if(!i_pll_done_1)
rate_change_tclk_on_1_ff <= 1'b0 ;
else
rate_change_tclk_on_1_ff <= RATE_CHANGE_TCLK_ON_1;
end
always @ (posedge clk or negedge i_pll_done_1) begin
if(!i_pll_done_1)
P_RATE_CHANGE_TCLK_ON_1 <= 1'b0 ;
else
P_RATE_CHANGE_TCLK_ON_1 <= rate_change_tclk_on_1_ff;
end
endmodule |
module ipml_hsst_txlane_rst_fsm_v1_0#(
parameter LANE_BONDING = 1 , //enable bonding : 2 or 4 , disable bonding : 1
parameter FREE_CLOCK_FREQ = 100, //unit is MHz, free clock freq from GUI
parameter P_LX_TX_CKDIV = 0 , //initial params
parameter PCS_TX_CLK_EXPLL_USE_CH = "FALSE"
)(
// Reset and Clock
input wire clk ,
input wire rst_n ,
// HSST Reset Control Signal
input wire i_tx_rate_chng ,
input wire [2:0] i_txckdiv ,
input wire i_pll_lock_tx ,
output reg P_TX_LANE_PD ,
output reg [2:0] P_TX_RATE ,
output reg P_TX_PMA_RST ,
output reg P_PCS_TX_RST ,
output reg o_txlane_done ,
output reg lane_sync ,
output reg lane_sync_en ,
output reg rate_change_on ,
output reg o_txckdiv_done
);
localparam CNTR0_WIDTH = 14;
localparam CNTR1_WIDTH = 8;
localparam CNTR2_WIDTH = 8;
localparam CNTR3_WIDTH = 8;
//TX Lane Power Up
`ifdef IPML_HSST_SPEEDUP_SIM
localparam integer TX_PMA_RST_CNTR_VALUE = 2*(2*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_LANE_PD_CNTR_VALUE = 2*(1*FREE_CLOCK_FREQ);//add 50 percent margin
`else
localparam integer TX_PMA_RST_CNTR_VALUE = 2*(41*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_LANE_PD_CNTR_VALUE = 2*(40*FREE_CLOCK_FREQ);//add 50 percent margin
`endif
localparam integer TX_PCS_RST_CNTR_VALUE = 2*(0.5*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_RST_DONE_DLY_CNTR_VALUE = 32;//add for txlane_done is active but fabric clock is none by wenbin at @2019.9.26
//TX LANE SYNC
localparam integer TX_LANE_SYNC_CNTR_R_VALUE = 2*(0.5*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_LANE_SYNC_CNTR_F_VALUE = 2*(0.6*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_LANE_SYNC_EN_CNTR_F_VALUE = 2*(1.1*FREE_CLOCK_FREQ);//add 50 percent margin
//TX Lane Rate Change
localparam integer TX_RATE_CHANGE_ON_CNTR_F_VALUE = 2*(0.1*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_RATE_CHANGE_SYNC_CNTR_R_VALUE = 2*(0.5*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_RATE_CNTR_VALUE = 2*(0.55*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_RATE_CHANGE_SYNC_CNTR_F_VALUE = 2*(0.6*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_RATE_CHANGE_PMA_CNTR_F_VALUE = 2*(0.65*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer TX_RATE_CHANGE_ON_CNTR_R_VALUE = 2*(1.1*FREE_CLOCK_FREQ);//add 50 percent margin
//TX Lane FSM Status
localparam TX_LANE_IDLE = 3'd0;
localparam TX_LANE_PMA = 3'd1;
localparam TX_LANE_SYNC = 3'd2;
localparam TX_LANE_PCS = 3'd3;
localparam TX_DONE = 3'd4;
localparam TX_CKDIV_ONLY = 3'd5;
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
reg [CNTR0_WIDTH-1: 0] cntr0 ;
reg [CNTR1_WIDTH-1: 0] cntr1 ;
reg [CNTR2_WIDTH-1: 0] cntr2 ;
reg [CNTR3_WIDTH-1: 0] cntr3 ;
reg [2 : 0] txlane_rst_fsm ;
reg [2 : 0] next_state ;
reg [1 : 0] i_tx_rate_chng_ff ;
reg i_tx_rate_chng_posedge ;
reg [2 : 0] i_txckdiv_ff ;
reg [2 : 0] txckdiv ;
wire expll_lock_tx ;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
assign expll_lock_tx = (PCS_TX_CLK_EXPLL_USE_CH == "FALSE") ? 1'b1 : i_pll_lock_tx ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
i_tx_rate_chng_ff <= 2'b0;
else
i_tx_rate_chng_ff <= {i_tx_rate_chng_ff[0],i_tx_rate_chng};
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
i_tx_rate_chng_posedge <= 1'b0;
else if (txlane_rst_fsm == TX_CKDIV_ONLY)
i_tx_rate_chng_posedge <= 1'b0;
else if (i_tx_rate_chng_ff[0] & (!i_tx_rate_chng_ff[1]))
i_tx_rate_chng_posedge <= 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
i_txckdiv_ff <= 3'b000;
else
i_txckdiv_ff <= i_txckdiv;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
txckdiv <= 3'b000;
else if (!i_tx_rate_chng_posedge && i_tx_rate_chng_ff[0] && (!i_tx_rate_chng_ff[1]) && txlane_rst_fsm != TX_CKDIV_ONLY)
txckdiv <= i_txckdiv_ff;
else ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
txlane_rst_fsm <= TX_LANE_IDLE ;
end
else begin
txlane_rst_fsm <= next_state ;
end
end
always@(*) begin
case(txlane_rst_fsm)
TX_LANE_IDLE :
next_state = TX_LANE_PMA ;
TX_LANE_PMA :
begin
if(cntr0 == TX_PMA_RST_CNTR_VALUE)
begin
if(LANE_BONDING != 1)
next_state = TX_LANE_SYNC ;
else if (expll_lock_tx)
next_state = TX_LANE_PCS ;
else
next_state = TX_LANE_PMA ;
end
else
next_state = TX_LANE_PMA ;
end
TX_LANE_SYNC :
begin
if(expll_lock_tx && (cntr1 == TX_LANE_SYNC_EN_CNTR_F_VALUE))
next_state = TX_LANE_PCS ;
else
next_state = TX_LANE_SYNC ;
end
TX_LANE_PCS :
begin
if(cntr2 == (TX_PCS_RST_CNTR_VALUE + TX_RST_DONE_DLY_CNTR_VALUE))
next_state = TX_DONE ;
else
next_state = TX_LANE_PCS ;
end
TX_DONE :
begin
if(i_tx_rate_chng_posedge)
next_state = TX_CKDIV_ONLY ;
else
next_state = TX_DONE ;
end
TX_CKDIV_ONLY :
begin
if(cntr3 == TX_RATE_CHANGE_ON_CNTR_R_VALUE)
next_state = TX_LANE_PCS ;
else
next_state = TX_CKDIV_ONLY ;
end
default :
begin
next_state = TX_LANE_IDLE ;
end
endcase
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cntr0 <= {CNTR0_WIDTH{1'b0}};
cntr1 <= {CNTR1_WIDTH{1'b0}};
cntr2 <= {CNTR2_WIDTH{1'b0}};
cntr3 <= {CNTR3_WIDTH{1'b0}};
P_TX_LANE_PD <= 1'b1;
P_TX_PMA_RST <= 1'b1;
lane_sync <= 1'b0;
lane_sync_en <= 1'b0;
rate_change_on <= 1'b1;
P_TX_RATE <= P_LX_TX_CKDIV;
P_PCS_TX_RST <= 1'b1;
o_txlane_done <= 1'b0;
o_txckdiv_done <= 1'b0;
end
else
begin
case(txlane_rst_fsm)
TX_LANE_IDLE :
begin
cntr0 <= {CNTR0_WIDTH{1'b0}};
cntr1 <= {CNTR1_WIDTH{1'b0}};
cntr2 <= {CNTR2_WIDTH{1'b0}};
cntr3 <= {CNTR3_WIDTH{1'b0}};
P_TX_LANE_PD <= 1'b1;
P_TX_PMA_RST <= 1'b1;
lane_sync <= 1'b0;
lane_sync_en <= 1'b0;
rate_change_on <= 1'b1;
P_TX_RATE <= P_LX_TX_CKDIV;
P_PCS_TX_RST <= 1'b1;
o_txlane_done <= 1'b0;
o_txckdiv_done <= 1'b0;
end
TX_LANE_PMA :
begin
if(cntr0 == TX_PMA_RST_CNTR_VALUE)
begin
P_TX_PMA_RST <= 1'b0 ;
if((LANE_BONDING != 1) || expll_lock_tx)
cntr0 <= {CNTR0_WIDTH{1'b0}};
else
cntr0 <= cntr0 ;
end
else
begin
cntr0 <= cntr0 + {{CNTR0_WIDTH-1{1'b0}},{1'b1}};
if(cntr0 == TX_LANE_PD_CNTR_VALUE)
P_TX_LANE_PD <= 1'b0 ;
else
P_TX_LANE_PD <= P_TX_LANE_PD;
end
end
TX_LANE_SYNC :
begin
if(cntr1 == TX_LANE_SYNC_EN_CNTR_F_VALUE)
begin
lane_sync_en <= 1'b0 ;
lane_sync <= 1'b0 ;
if(expll_lock_tx)
cntr1 <= {CNTR1_WIDTH{1'b0}};
else
cntr1 <= cntr1 ;
end
else
begin
lane_sync_en <= 1'b1 ;
cntr1 <= cntr1 + {{CNTR1_WIDTH-1{1'b0}},{1'b1}};
if(cntr1 == TX_LANE_SYNC_CNTR_F_VALUE)
lane_sync <= 1'b0 ;
else if (cntr1 == TX_LANE_SYNC_CNTR_R_VALUE)
lane_sync <= 1'b1 ;
else
lane_sync <= lane_sync ;
end
end
TX_LANE_PCS :
begin
if(cntr2 == (TX_PCS_RST_CNTR_VALUE + TX_RST_DONE_DLY_CNTR_VALUE))
cntr2 <= {CNTR2_WIDTH{1'b0}};
else
begin
cntr2 <= cntr2 + {{CNTR2_WIDTH-1{1'b0}},{1'b1}};
if(cntr2 == TX_PCS_RST_CNTR_VALUE)
P_PCS_TX_RST <= 1'b0 ;
else
P_PCS_TX_RST <= P_PCS_TX_RST ;
end
end
TX_DONE :
begin
o_txlane_done <= 1'b1 ;
end
TX_CKDIV_ONLY :
begin
if(cntr3 == TX_RATE_CHANGE_ON_CNTR_R_VALUE)
begin
cntr3 <= {CNTR3_WIDTH{1'b0}};
lane_sync_en <= 1'b0 ;
o_txckdiv_done <= 1'b1 ;
rate_change_on <= 1'b1 ;
end
else
begin
cntr3 <= cntr3 + {{CNTR3_WIDTH-1{1'b0}},{1'b1}};
o_txckdiv_done <= 1'b0 ;
o_txlane_done <= 1'b0 ;
P_PCS_TX_RST <= 1'b1 ;
lane_sync_en <= 1'b1 ;
if(cntr3 == TX_RATE_CHANGE_PMA_CNTR_F_VALUE)
P_TX_PMA_RST <= 1'b0 ;
else if (cntr3 == TX_RATE_CHANGE_SYNC_CNTR_F_VALUE)
lane_sync <= 1'b0 ;
else if (cntr3 == TX_RATE_CNTR_VALUE)
P_TX_RATE <= txckdiv ;
else if (cntr3 == TX_RATE_CHANGE_SYNC_CNTR_R_VALUE)
begin
P_TX_PMA_RST <= 1'b1 ;
lane_sync <= 1'b1 ;
end
else if (cntr3 == TX_RATE_CHANGE_ON_CNTR_F_VALUE)
rate_change_on <= 1'b0 ;
end
end
default :
begin
cntr0 <= {CNTR0_WIDTH{1'b0}};
cntr1 <= {CNTR1_WIDTH{1'b0}};
cntr2 <= {CNTR2_WIDTH{1'b0}};
cntr3 <= {CNTR3_WIDTH{1'b0}};
P_TX_LANE_PD <= 1'b1;
P_TX_PMA_RST <= 1'b1;
lane_sync <= 1'b0;
lane_sync_en <= 1'b0;
rate_change_on <= 1'b1;
P_TX_RATE <= P_LX_TX_CKDIV;
P_PCS_TX_RST <= 1'b1;
o_txlane_done <= 1'b0;
o_txckdiv_done <= 1'b0;
end
endcase
end
end
endmodule |
module ipml_hsst_rst_v1_1#(
parameter INNER_RST_EN = "TRUE" , //TRUE: HSST Reset Auto Control, FALSE: HSST Reset Control by User
parameter FREE_CLOCK_FREQ = 100 , //Unit is MHz, free clock freq from GUI Freq: 0~200MHz
parameter CH0_TX_ENABLE = "TRUE" , //TRUE:lane0 TX Reset Logic used, FALSE: lane0 TX Reset Logic remove
parameter CH1_TX_ENABLE = "TRUE" , //TRUE:lane1 TX Reset Logic used, FALSE: lane1 TX Reset Logic remove
parameter CH2_TX_ENABLE = "TRUE" , //TRUE:lane2 TX Reset Logic used, FALSE: lane2 TX Reset Logic remove
parameter CH3_TX_ENABLE = "TRUE" , //TRUE:lane3 TX Reset Logic used, FALSE: lane3 TX Reset Logic remove
parameter CH0_RX_ENABLE = "TRUE" , //TRUE:lane0 RX Reset Logic used, FALSE: lane0 RX Reset Logic remove
parameter CH1_RX_ENABLE = "TRUE" , //TRUE:lane1 RX Reset Logic used, FALSE: lane1 RX Reset Logic remove
parameter CH2_RX_ENABLE = "TRUE" , //TRUE:lane2 RX Reset Logic used, FALSE: lane2 RX Reset Logic remove
parameter CH3_RX_ENABLE = "TRUE" , //TRUE:lane3 RX Reset Logic used, FALSE: lane3 RX Reset Logic remove
parameter CH0_MULT_LANE_MODE = 1 , //Lane0 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH1_MULT_LANE_MODE = 1 , //Lane1 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH2_MULT_LANE_MODE = 1 , //Lane2 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH3_MULT_LANE_MODE = 1 , //Lane3 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH0_RXPCS_ALIGN_TIMER = 10000 , //Word Alignment Wait time, when match the RXPMA will be Reset
parameter CH1_RXPCS_ALIGN_TIMER = 10000 , //Word Alignment Wait time, when match the RXPMA will be Reset
parameter CH2_RXPCS_ALIGN_TIMER = 10000 , //Word Alignment Wait time, when match the RXPMA will be Reset
parameter CH3_RXPCS_ALIGN_TIMER = 10000 , //Word Alignment Wait time, when match the RXPMA will be Reset
parameter PCS_CH0_BYPASS_WORD_ALIGN = "FALSE" , //TRUE: Lane0 Bypass Word Alignment, FALSE: Lane0 No Bypass Word Alignment
parameter PCS_CH1_BYPASS_WORD_ALIGN = "FALSE" , //TRUE: Lane1 Bypass Word Alignment, FALSE: Lane1 No Bypass Word Alignment
parameter PCS_CH2_BYPASS_WORD_ALIGN = "FALSE" , //TRUE: Lane2 Bypass Word Alignment, FALSE: Lane2 No Bypass Word Alignment
parameter PCS_CH3_BYPASS_WORD_ALIGN = "FALSE" , //TRUE: Lane3 Bypass Word Alignment, FALSE: Lane3 No Bypass Word Alignment
parameter PCS_CH0_BYPASS_BONDING = "FALSE" , //TRUE: Lane0 Bypass Channel Bonding, FALSE: Lane0 No Bypass Channel Bonding
parameter PCS_CH1_BYPASS_BONDING = "FALSE" , //TRUE: Lane1 Bypass Channel Bonding, FALSE: Lane1 No Bypass Channel Bonding
parameter PCS_CH2_BYPASS_BONDING = "FALSE" , //TRUE: Lane2 Bypass Channel Bonding, FALSE: Lane2 No Bypass Channel Bonding
parameter PCS_CH3_BYPASS_BONDING = "FALSE" , //TRUE: Lane3 Bypass Channel Bonding, FALSE: Lane3 No Bypass Channel Bonding
parameter PCS_CH0_BYPASS_CTC = "TRUE" , //TRUE: Lane0 Bypass CTC, FALSE: Lane0 No Bypass CTC
parameter PCS_CH1_BYPASS_CTC = "TRUE" , //TRUE: Lane1 Bypass CTC, FALSE: Lane1 No Bypass CTC
parameter PCS_CH2_BYPASS_CTC = "TRUE" , //TRUE: Lane2 Bypass CTC, FALSE: Lane2 No Bypass CTC
parameter PCS_CH3_BYPASS_CTC = "TRUE" , //TRUE: Lane3 Bypass CTC, FALSE: Lane3 No Bypass CTC
parameter P_LX_TX_CKDIV_0 = 0 , //TX initial clock division value
parameter P_LX_TX_CKDIV_1 = 0 , //TX initial clock division value
parameter P_LX_TX_CKDIV_2 = 0 , //TX initial clock division value
parameter P_LX_TX_CKDIV_3 = 0 , //TX initial clock division value
parameter LX_RX_CKDIV_0 = 0 , //RX initial clock division value
parameter LX_RX_CKDIV_1 = 0 , //RX initial clock division value
parameter LX_RX_CKDIV_2 = 0 , //RX initial clock division value
parameter LX_RX_CKDIV_3 = 0 , //RX initial clock division value
parameter CH0_TX_PLL_SEL = 0 ,//Lane0 --> 1:PLL1 0:PLL0
parameter CH1_TX_PLL_SEL = 0 ,//Lane1 --> 1:PLL1 0:PLL0
parameter CH2_TX_PLL_SEL = 0 ,//Lane2 --> 1:PLL1 0:PLL0
parameter CH3_TX_PLL_SEL = 0 ,//Lane3 --> 1:PLL1 0:PLL0
parameter CH0_RX_PLL_SEL = 0 ,//Lane0 --> 1:PLL1 0:PLL0
parameter CH1_RX_PLL_SEL = 0 ,//Lane1 --> 1:PLL1 0:PLL0
parameter CH2_RX_PLL_SEL = 0 ,//Lane2 --> 1:PLL1 0:PLL0
parameter CH3_RX_PLL_SEL = 0 ,//Lane3 --> 1:PLL1 0:PLL0
parameter PLL_NUBER = 1 ,
parameter PCS_TX_CLK_EXPLL_USE_CH0 = "FALSE" ,//TRUE: Fabric PLL USE
parameter PCS_TX_CLK_EXPLL_USE_CH1 = "FALSE" ,
parameter PCS_TX_CLK_EXPLL_USE_CH2 = "FALSE" ,
parameter PCS_TX_CLK_EXPLL_USE_CH3 = "FALSE" ,
parameter PCS_RX_CLK_EXPLL_USE_CH0 = "FALSE" ,
parameter PCS_RX_CLK_EXPLL_USE_CH1 = "FALSE" ,
parameter PCS_RX_CLK_EXPLL_USE_CH2 = "FALSE" ,
parameter PCS_RX_CLK_EXPLL_USE_CH3 = "FALSE"
)(
//BOTH NEED
input wire i_pll_lock_tx_0 ,
input wire i_pll_lock_tx_1 ,
input wire i_pll_lock_tx_2 ,
input wire i_pll_lock_tx_3 ,
input wire i_pll_lock_rx_0 ,
input wire i_pll_lock_rx_1 ,
input wire i_pll_lock_rx_2 ,
input wire i_pll_lock_rx_3 ,
//--- User Side ---
//INNER_RST_EN is TRUE
input wire i_free_clk ,
input wire i_pll_rst_0 ,
input wire i_pll_rst_1 ,
input wire i_wtchdg_clr_0 ,
input wire i_wtchdg_clr_1 ,
input wire i_lane_pd_0 ,
input wire i_lane_pd_1 ,
input wire i_lane_pd_2 ,
input wire i_lane_pd_3 ,
input wire i_txlane_rst_0 ,
input wire i_txlane_rst_1 ,
input wire i_txlane_rst_2 ,
input wire i_txlane_rst_3 ,
input wire i_rxlane_rst_0 ,
input wire i_rxlane_rst_1 ,
input wire i_rxlane_rst_2 ,
input wire i_rxlane_rst_3 ,
input wire i_tx_rate_chng_0 ,
input wire i_tx_rate_chng_1 ,
input wire i_tx_rate_chng_2 ,
input wire i_tx_rate_chng_3 ,
input wire i_rx_rate_chng_0 ,
input wire i_rx_rate_chng_1 ,
input wire i_rx_rate_chng_2 ,
input wire i_rx_rate_chng_3 ,
input wire [1 : 0] i_txckdiv_0 ,
input wire [1 : 0] i_txckdiv_1 ,
input wire [1 : 0] i_txckdiv_2 ,
input wire [1 : 0] i_txckdiv_3 ,
input wire [1 : 0] i_rxckdiv_0 ,
input wire [1 : 0] i_rxckdiv_1 ,
input wire [1 : 0] i_rxckdiv_2 ,
input wire [1 : 0] i_rxckdiv_3 ,
input wire i_pcs_cb_rst_0 ,
input wire i_pcs_cb_rst_1 ,
input wire i_pcs_cb_rst_2 ,
input wire i_pcs_cb_rst_3 ,
input wire i_hsst_fifo_clr_0 ,
input wire i_hsst_fifo_clr_1 ,
input wire i_hsst_fifo_clr_2 ,
input wire i_hsst_fifo_clr_3 ,
input wire i_force_rxfsm_det_0 ,//Debug signal for loopback mode
input wire i_force_rxfsm_det_1 ,//Debug signal for loopback mode
input wire i_force_rxfsm_det_2 ,//Debug signal for loopback mode
input wire i_force_rxfsm_det_3 ,//Debug signal for loopback mode
input wire i_force_rxfsm_lsm_0 ,//Debug signal for loopback mode
input wire i_force_rxfsm_lsm_1 ,//Debug signal for loopback mode
input wire i_force_rxfsm_lsm_2 ,//Debug signal for loopback mode
input wire i_force_rxfsm_lsm_3 ,//Debug signal for loopback mode
input wire i_force_rxfsm_cdr_0 ,//Debug signal for loopback mode
input wire i_force_rxfsm_cdr_1 ,//Debug signal for loopback mode
input wire i_force_rxfsm_cdr_2 ,//Debug signal for loopback mode
input wire i_force_rxfsm_cdr_3 ,//Debug signal for loopback mode
output wire [1 : 0] o_wtchdg_st_0 ,
output wire [1 : 0] o_wtchdg_st_1 ,
output wire o_pll_done_0 ,
output wire o_pll_done_1 ,
output wire o_txlane_done_0 ,
output wire o_txlane_done_1 ,
output wire o_txlane_done_2 ,
output wire o_txlane_done_3 ,
output wire o_tx_ckdiv_done_0 ,
output wire o_tx_ckdiv_done_1 ,
output wire o_tx_ckdiv_done_2 ,
output wire o_tx_ckdiv_done_3 ,
output wire o_rxlane_done_0 ,
output wire o_rxlane_done_1 ,
output wire o_rxlane_done_2 ,
output wire o_rxlane_done_3 ,
output wire o_rx_ckdiv_done_0 ,
output wire o_rx_ckdiv_done_1 ,
output wire o_rx_ckdiv_done_2 ,
output wire o_rx_ckdiv_done_3 ,
//INNER_RST_EN is FALSE
input wire i_f_pllpowerdown_0 ,
input wire i_f_pllpowerdown_1 ,
input wire i_f_pll_rst_0 ,
input wire i_f_pll_rst_1 ,
input wire i_f_lane_sync_0 ,
input wire i_f_lane_sync_1 ,
input wire i_f_lane_sync_en_0 ,
input wire i_f_lane_sync_en_1 ,
input wire i_f_rate_change_tclk_on_0 ,
input wire i_f_rate_change_tclk_on_1 ,
input wire i_f_tx_lane_pd_0 ,
input wire i_f_tx_lane_pd_1 ,
input wire i_f_tx_lane_pd_2 ,
input wire i_f_tx_lane_pd_3 ,
input wire i_f_tx_pma_rst_0 ,
input wire i_f_tx_pma_rst_1 ,
input wire i_f_tx_pma_rst_2 ,
input wire i_f_tx_pma_rst_3 ,
input wire [1 : 0] i_f_tx_ckdiv_0 ,
input wire [1 : 0] i_f_tx_ckdiv_1 ,
input wire [1 : 0] i_f_tx_ckdiv_2 ,
input wire [1 : 0] i_f_tx_ckdiv_3 ,
input wire i_f_pcs_tx_rst_0 ,
input wire i_f_pcs_tx_rst_1 ,
input wire i_f_pcs_tx_rst_2 ,
input wire i_f_pcs_tx_rst_3 ,
input wire i_f_lane_pd_0 ,
input wire i_f_lane_pd_1 ,
input wire i_f_lane_pd_2 ,
input wire i_f_lane_pd_3 ,
input wire i_f_lane_rst_0 ,
input wire i_f_lane_rst_1 ,
input wire i_f_lane_rst_2 ,
input wire i_f_lane_rst_3 ,
input wire i_f_rx_lane_pd_0 ,
input wire i_f_rx_lane_pd_1 ,
input wire i_f_rx_lane_pd_2 ,
input wire i_f_rx_lane_pd_3 ,
input wire i_f_rx_pma_rst_0 ,
input wire i_f_rx_pma_rst_1 ,
input wire i_f_rx_pma_rst_2 ,
input wire i_f_rx_pma_rst_3 ,
input wire i_f_pcs_rx_rst_0 ,
input wire i_f_pcs_rx_rst_1 ,
input wire i_f_pcs_rx_rst_2 ,
input wire i_f_pcs_rx_rst_3 ,
input wire [1 : 0] i_f_lx_rx_ckdiv_0 ,
input wire [1 : 0] i_f_lx_rx_ckdiv_1 ,
input wire [1 : 0] i_f_lx_rx_ckdiv_2 ,
input wire [1 : 0] i_f_lx_rx_ckdiv_3 ,
input wire i_f_pcs_cb_rst_0 ,
input wire i_f_pcs_cb_rst_1 ,
input wire i_f_pcs_cb_rst_2 ,
input wire i_f_pcs_cb_rst_3 ,
//--- Hsst Side ---
input wire P_PLL_READY_0 ,
input wire P_PLL_READY_1 ,
input wire P_RX_SIGDET_STATUS_0 ,
input wire P_RX_SIGDET_STATUS_1 ,
input wire P_RX_SIGDET_STATUS_2 ,
input wire P_RX_SIGDET_STATUS_3 ,
input wire P_RX_READY_0 ,
input wire P_RX_READY_1 ,
input wire P_RX_READY_2 ,
input wire P_RX_READY_3 ,
input wire P_PCS_LSM_SYNCED_0 ,
input wire P_PCS_LSM_SYNCED_1 ,
input wire P_PCS_LSM_SYNCED_2 ,
input wire P_PCS_LSM_SYNCED_3 ,
input wire P_PCS_RX_MCB_STATUS_0 ,
input wire P_PCS_RX_MCB_STATUS_1 ,
input wire P_PCS_RX_MCB_STATUS_2 ,
input wire P_PCS_RX_MCB_STATUS_3 ,
output wire P_PLLPOWERDOWN_0 ,
output wire P_PLLPOWERDOWN_1 ,
output wire P_PLL_RST_0 ,
output wire P_PLL_RST_1 ,
output wire P_LANE_SYNC_0 ,
output wire P_LANE_SYNC_1 ,
output wire P_LANE_SYNC_EN_0 ,
output wire P_LANE_SYNC_EN_1 ,
output wire P_RATE_CHANGE_TCLK_ON_0 ,
output wire P_RATE_CHANGE_TCLK_ON_1 ,
output wire P_TX_LANE_PD_0 ,
output wire P_TX_LANE_PD_1 ,
output wire P_TX_LANE_PD_2 ,
output wire P_TX_LANE_PD_3 ,
output wire [2 : 0] P_TX_RATE_0 ,
output wire [2 : 0] P_TX_RATE_1 ,
output wire [2 : 0] P_TX_RATE_2 ,
output wire [2 : 0] P_TX_RATE_3 ,
output wire P_TX_PMA_RST_0 ,
output wire P_TX_PMA_RST_1 ,
output wire P_TX_PMA_RST_2 ,
output wire P_TX_PMA_RST_3 ,
output wire P_PCS_TX_RST_0 ,
output wire P_PCS_TX_RST_1 ,
output wire P_PCS_TX_RST_2 ,
output wire P_PCS_TX_RST_3 ,
output wire P_RX_PMA_RST_0 ,
output wire P_RX_PMA_RST_1 ,
output wire P_RX_PMA_RST_2 ,
output wire P_RX_PMA_RST_3 ,
output wire P_LANE_PD_0 ,
output wire P_LANE_PD_1 ,
output wire P_LANE_PD_2 ,
output wire P_LANE_PD_3 ,
output wire P_LANE_RST_0 ,
output wire P_LANE_RST_1 ,
output wire P_LANE_RST_2 ,
output wire P_LANE_RST_3 ,
output wire P_RX_LANE_PD_0 ,
output wire P_RX_LANE_PD_1 ,
output wire P_RX_LANE_PD_2 ,
output wire P_RX_LANE_PD_3 ,
output wire P_PCS_RX_RST_0 ,
output wire P_PCS_RX_RST_1 ,
output wire P_PCS_RX_RST_2 ,
output wire P_PCS_RX_RST_3 ,
output wire [2 : 0] P_RX_RATE_0 ,
output wire [2 : 0] P_RX_RATE_1 ,
output wire [2 : 0] P_RX_RATE_2 ,
output wire [2 : 0] P_RX_RATE_3 ,
output wire P_PCS_CB_RST_0 ,
output wire P_PCS_CB_RST_1 ,
output wire P_PCS_CB_RST_2 ,
output wire P_PCS_CB_RST_3
);
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
//CTC Enable, TX/RX Reused Same Rate Change Port
wire p_rx_rate_chng_0;
wire p_rx_rate_chng_1;
wire p_rx_rate_chng_2;
wire p_rx_rate_chng_3;
wire [2:0] p_rxckdiv_0;
wire [2:0] p_rxckdiv_1;
wire [2:0] p_rxckdiv_2;
wire [2:0] p_rxckdiv_3;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
assign p_rx_rate_chng_0 = (CH0_TX_ENABLE=="TRUE" && PCS_CH0_BYPASS_CTC=="FALSE") ? i_tx_rate_chng_0 : i_rx_rate_chng_0;
assign p_rx_rate_chng_1 = (CH1_TX_ENABLE=="TRUE" && PCS_CH1_BYPASS_CTC=="FALSE") ? i_tx_rate_chng_1 : i_rx_rate_chng_1;
assign p_rx_rate_chng_2 = (CH2_TX_ENABLE=="TRUE" && PCS_CH2_BYPASS_CTC=="FALSE") ? i_tx_rate_chng_2 : i_rx_rate_chng_2;
assign p_rx_rate_chng_3 = (CH3_TX_ENABLE=="TRUE" && PCS_CH3_BYPASS_CTC=="FALSE") ? i_tx_rate_chng_3 : i_rx_rate_chng_3;
assign p_rxckdiv_0 = (CH0_TX_ENABLE=="TRUE" && PCS_CH0_BYPASS_CTC=="FALSE") ? {1'b0,i_txckdiv_0} : {1'b0,i_rxckdiv_0};
assign p_rxckdiv_1 = (CH1_TX_ENABLE=="TRUE" && PCS_CH1_BYPASS_CTC=="FALSE") ? {1'b0,i_txckdiv_1} : {1'b0,i_rxckdiv_1};
assign p_rxckdiv_2 = (CH2_TX_ENABLE=="TRUE" && PCS_CH2_BYPASS_CTC=="FALSE") ? {1'b0,i_txckdiv_2} : {1'b0,i_rxckdiv_2};
assign p_rxckdiv_3 = (CH3_TX_ENABLE=="TRUE" && PCS_CH3_BYPASS_CTC=="FALSE") ? {1'b0,i_txckdiv_3} : {1'b0,i_rxckdiv_3};
generate
if(INNER_RST_EN=="TRUE") begin : AUTO_MODE
ipml_hsst_rst_pll_v1_0#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.PLL_NUBER (PLL_NUBER )
) ipml_hsst_rst_pll (
.clk (i_free_clk ),//I
.i_pll_rst_0 (i_pll_rst_0 ),//I
.i_pll_rst_1 (i_pll_rst_1 ),//I
.P_PLL_READY_0 (P_PLL_READY_0 ),//I
.P_PLL_READY_1 (P_PLL_READY_1 ),//I
.i_wtchdg_clr_0 (i_wtchdg_clr_0 ),//I
.i_wtchdg_clr_1 (i_wtchdg_clr_1 ),//I
.o_wtchdg_st_0 (o_wtchdg_st_0 ),//O
.o_wtchdg_st_1 (o_wtchdg_st_1 ),//O
.o_pll_done_0 (o_pll_done_0 ),//O
.o_pll_done_1 (o_pll_done_1 ),//O
.P_PLLPOWERDOWN_0 (P_PLLPOWERDOWN_0 ),//O
.P_PLLPOWERDOWN_1 (P_PLLPOWERDOWN_1 ),//O
.P_PLL_RST_0 (P_PLL_RST_0 ),//O
.P_PLL_RST_1 (P_PLL_RST_1 )//O
);
ipml_hsst_lane_powerup_v1_0#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.CH0_TX_ENABLE (CH0_TX_ENABLE ),
.CH1_TX_ENABLE (CH1_TX_ENABLE ),
.CH2_TX_ENABLE (CH2_TX_ENABLE ),
.CH3_TX_ENABLE (CH3_TX_ENABLE ),
.CH0_RX_ENABLE (CH0_RX_ENABLE ),
.CH1_RX_ENABLE (CH1_RX_ENABLE ),
.CH2_RX_ENABLE (CH2_RX_ENABLE ),
.CH3_RX_ENABLE (CH3_RX_ENABLE ),
.CH0_MULT_LANE_MODE (CH0_MULT_LANE_MODE ),
.CH1_MULT_LANE_MODE (CH1_MULT_LANE_MODE ),
.CH2_MULT_LANE_MODE (CH2_MULT_LANE_MODE ),
.CH3_MULT_LANE_MODE (CH3_MULT_LANE_MODE ),
.CH0_TX_PLL_SEL (CH0_TX_PLL_SEL ),
.CH1_TX_PLL_SEL (CH1_TX_PLL_SEL ),
.CH2_TX_PLL_SEL (CH2_TX_PLL_SEL ),
.CH3_TX_PLL_SEL (CH3_TX_PLL_SEL ),
.CH0_RX_PLL_SEL (CH0_RX_PLL_SEL ),
.CH1_RX_PLL_SEL (CH1_RX_PLL_SEL ),
.CH2_RX_PLL_SEL (CH2_RX_PLL_SEL ),
.CH3_RX_PLL_SEL (CH3_RX_PLL_SEL )
) ipml_hsst_lane_powerup (
.clk (i_free_clk ),//I
.i_lane_pd_0 (i_lane_pd_0 ),//I
.i_lane_pd_1 (i_lane_pd_1 ),//I
.i_lane_pd_2 (i_lane_pd_2 ),//I
.i_lane_pd_3 (i_lane_pd_3 ),//I
.o_pll_done_0 (o_pll_done_0 ),//I
.o_pll_done_1 (o_pll_done_1 ),//I
.P_LANE_PD_0 (P_LANE_PD_0 ),//O
.P_LANE_PD_1 (P_LANE_PD_1 ),//O
.P_LANE_PD_2 (P_LANE_PD_2 ),//O
.P_LANE_PD_3 (P_LANE_PD_3 ),//O
.P_LANE_RST_0 (P_LANE_RST_0 ),//O
.P_LANE_RST_1 (P_LANE_RST_1 ),//O
.P_LANE_RST_2 (P_LANE_RST_2 ),//O
.P_LANE_RST_3 (P_LANE_RST_3 ) //O
);
ipml_hsst_rst_tx_v1_0#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.CH0_TX_ENABLE (CH0_TX_ENABLE ),
.CH1_TX_ENABLE (CH1_TX_ENABLE ),
.CH2_TX_ENABLE (CH2_TX_ENABLE ),
.CH3_TX_ENABLE (CH3_TX_ENABLE ),
.CH0_MULT_LANE_MODE (CH0_MULT_LANE_MODE ),
.CH1_MULT_LANE_MODE (CH1_MULT_LANE_MODE ),
.CH2_MULT_LANE_MODE (CH2_MULT_LANE_MODE ),
.CH3_MULT_LANE_MODE (CH3_MULT_LANE_MODE ),
.P_LX_TX_CKDIV_0 (P_LX_TX_CKDIV_0 ),
.P_LX_TX_CKDIV_1 (P_LX_TX_CKDIV_1 ),
.P_LX_TX_CKDIV_2 (P_LX_TX_CKDIV_2 ),
.P_LX_TX_CKDIV_3 (P_LX_TX_CKDIV_3 ),
.CH0_TX_PLL_SEL (CH0_TX_PLL_SEL ),
.CH1_TX_PLL_SEL (CH1_TX_PLL_SEL ),
.CH2_TX_PLL_SEL (CH2_TX_PLL_SEL ),
.CH3_TX_PLL_SEL (CH3_TX_PLL_SEL ),
.PCS_TX_CLK_EXPLL_USE_CH0 (PCS_TX_CLK_EXPLL_USE_CH0 ),
.PCS_TX_CLK_EXPLL_USE_CH1 (PCS_TX_CLK_EXPLL_USE_CH1 ),
.PCS_TX_CLK_EXPLL_USE_CH2 (PCS_TX_CLK_EXPLL_USE_CH2 ),
.PCS_TX_CLK_EXPLL_USE_CH3 (PCS_TX_CLK_EXPLL_USE_CH3 )
) ipml_hsst_rst_tx (
.clk (i_free_clk ),//I
.i_txlane_rst_0 (i_txlane_rst_0 ),//I
.i_txlane_rst_1 (i_txlane_rst_1 ),//I
.i_txlane_rst_2 (i_txlane_rst_2 ),//I
.i_txlane_rst_3 (i_txlane_rst_3 ),//I
.i_pll_done_0 (o_pll_done_0 ),//I
.i_pll_done_1 (o_pll_done_1 ),//I
.P_LANE_RST_0 (P_LANE_RST_0 ),//I
.P_LANE_RST_1 (P_LANE_RST_1 ),//I
.P_LANE_RST_2 (P_LANE_RST_2 ),//I
.P_LANE_RST_3 (P_LANE_RST_3 ),//I
.i_tx_rate_chng_0 (i_tx_rate_chng_0 ),//I
.i_tx_rate_chng_1 (i_tx_rate_chng_1 ),//I
.i_tx_rate_chng_2 (i_tx_rate_chng_2 ),//I
.i_tx_rate_chng_3 (i_tx_rate_chng_3 ),//I
.i_pll_lock_tx_0 (i_pll_lock_tx_0 ),//I
.i_pll_lock_tx_1 (i_pll_lock_tx_1 ),//I
.i_pll_lock_tx_2 (i_pll_lock_tx_2 ),//I
.i_pll_lock_tx_3 (i_pll_lock_tx_3 ),//I
.i_txckdiv_0 ({1'b0,i_txckdiv_0} ),//I
.i_txckdiv_1 ({1'b0,i_txckdiv_1} ),//I
.i_txckdiv_2 ({1'b0,i_txckdiv_2} ),//I
.i_txckdiv_3 ({1'b0,i_txckdiv_3} ),//I
.o_txlane_done_0 (o_txlane_done_0 ),//O
.o_txlane_done_1 (o_txlane_done_1 ),//O
.o_txlane_done_2 (o_txlane_done_2 ),//O
.o_txlane_done_3 (o_txlane_done_3 ),//O
.o_txckdiv_done_0 (o_tx_ckdiv_done_0 ),//O
.o_txckdiv_done_1 (o_tx_ckdiv_done_1 ),//O
.o_txckdiv_done_2 (o_tx_ckdiv_done_2 ),//O
.o_txckdiv_done_3 (o_tx_ckdiv_done_3 ),//O
.P_TX_LANE_PD_0 (P_TX_LANE_PD_0 ),//O
.P_TX_LANE_PD_1 (P_TX_LANE_PD_1 ),//O
.P_TX_LANE_PD_2 (P_TX_LANE_PD_2 ),//O
.P_TX_LANE_PD_3 (P_TX_LANE_PD_3 ),//O
.P_TX_RATE_0 (P_TX_RATE_0 ),//O
.P_TX_RATE_1 (P_TX_RATE_1 ),//O
.P_TX_RATE_2 (P_TX_RATE_2 ),//O
.P_TX_RATE_3 (P_TX_RATE_3 ),//O
.P_TX_PMA_RST_0 (P_TX_PMA_RST_0 ),//O
.P_TX_PMA_RST_1 (P_TX_PMA_RST_1 ),//O
.P_TX_PMA_RST_2 (P_TX_PMA_RST_2 ),//O
.P_TX_PMA_RST_3 (P_TX_PMA_RST_3 ),//O
.P_PCS_TX_RST_0 (P_PCS_TX_RST_0 ),//O
.P_PCS_TX_RST_1 (P_PCS_TX_RST_1 ),//O
.P_PCS_TX_RST_2 (P_PCS_TX_RST_2 ),//O
.P_PCS_TX_RST_3 (P_PCS_TX_RST_3 ),//O
.P_LANE_SYNC_0 (P_LANE_SYNC_0 ),//O
.P_LANE_SYNC_1 (P_LANE_SYNC_1 ),//O
.P_LANE_SYNC_EN_0 (P_LANE_SYNC_EN_0 ),//O
.P_LANE_SYNC_EN_1 (P_LANE_SYNC_EN_1 ),//O
.P_RATE_CHANGE_TCLK_ON_0 (P_RATE_CHANGE_TCLK_ON_0 ),//O
.P_RATE_CHANGE_TCLK_ON_1 (P_RATE_CHANGE_TCLK_ON_1 )//O
);
ipml_hsst_rst_rx_v1_1#(
.FREE_CLOCK_FREQ (FREE_CLOCK_FREQ ),
.CH0_RX_ENABLE (CH0_RX_ENABLE ),
.CH1_RX_ENABLE (CH1_RX_ENABLE ),
.CH2_RX_ENABLE (CH2_RX_ENABLE ),
.CH3_RX_ENABLE (CH3_RX_ENABLE ),
.CH0_MULT_LANE_MODE (CH0_MULT_LANE_MODE ),
.CH1_MULT_LANE_MODE (CH1_MULT_LANE_MODE ),
.CH2_MULT_LANE_MODE (CH2_MULT_LANE_MODE ),
.CH3_MULT_LANE_MODE (CH3_MULT_LANE_MODE ),
.CH0_RXPCS_ALIGN_TIMER (CH0_RXPCS_ALIGN_TIMER ),
.CH1_RXPCS_ALIGN_TIMER (CH1_RXPCS_ALIGN_TIMER ),
.CH2_RXPCS_ALIGN_TIMER (CH2_RXPCS_ALIGN_TIMER ),
.CH3_RXPCS_ALIGN_TIMER (CH3_RXPCS_ALIGN_TIMER ),
.PCS_CH0_BYPASS_WORD_ALIGN (PCS_CH0_BYPASS_WORD_ALIGN ),
.PCS_CH1_BYPASS_WORD_ALIGN (PCS_CH1_BYPASS_WORD_ALIGN ),
.PCS_CH2_BYPASS_WORD_ALIGN (PCS_CH2_BYPASS_WORD_ALIGN ),
.PCS_CH3_BYPASS_WORD_ALIGN (PCS_CH3_BYPASS_WORD_ALIGN ),
.PCS_CH0_BYPASS_BONDING (PCS_CH0_BYPASS_BONDING ),
.PCS_CH1_BYPASS_BONDING (PCS_CH1_BYPASS_BONDING ),
.PCS_CH2_BYPASS_BONDING (PCS_CH2_BYPASS_BONDING ),
.PCS_CH3_BYPASS_BONDING (PCS_CH3_BYPASS_BONDING ),
.PCS_CH0_BYPASS_CTC (PCS_CH0_BYPASS_CTC ),
.PCS_CH1_BYPASS_CTC (PCS_CH1_BYPASS_CTC ),
.PCS_CH2_BYPASS_CTC (PCS_CH2_BYPASS_CTC ),
.PCS_CH3_BYPASS_CTC (PCS_CH3_BYPASS_CTC ),
.LX_RX_CKDIV_0 (LX_RX_CKDIV_0 ),
.LX_RX_CKDIV_1 (LX_RX_CKDIV_1 ),
.LX_RX_CKDIV_2 (LX_RX_CKDIV_2 ),
.LX_RX_CKDIV_3 (LX_RX_CKDIV_3 ),
.CH0_RX_PLL_SEL (CH0_RX_PLL_SEL ),
.CH1_RX_PLL_SEL (CH1_RX_PLL_SEL ),
.CH2_RX_PLL_SEL (CH2_RX_PLL_SEL ),
.CH3_RX_PLL_SEL (CH3_RX_PLL_SEL ),
.PCS_RX_CLK_EXPLL_USE_CH0 (PCS_RX_CLK_EXPLL_USE_CH0 ),
.PCS_RX_CLK_EXPLL_USE_CH1 (PCS_RX_CLK_EXPLL_USE_CH1 ),
.PCS_RX_CLK_EXPLL_USE_CH2 (PCS_RX_CLK_EXPLL_USE_CH2 ),
.PCS_RX_CLK_EXPLL_USE_CH3 (PCS_RX_CLK_EXPLL_USE_CH3 )
) ipml_hsst_rst_rx (
.clk (i_free_clk ),//I
.i_hsst_fifo_clr_0 (i_hsst_fifo_clr_0 ),//I
.i_hsst_fifo_clr_1 (i_hsst_fifo_clr_1 ),//I
.i_hsst_fifo_clr_2 (i_hsst_fifo_clr_2 ),//I
.i_hsst_fifo_clr_3 (i_hsst_fifo_clr_3 ),//I
.P_LANE_RST_0 (P_LANE_RST_0 ),//I
.P_LANE_RST_1 (P_LANE_RST_1 ),//I
.P_LANE_RST_2 (P_LANE_RST_2 ),//I
.P_LANE_RST_3 (P_LANE_RST_3 ),//I
.i_rxlane_rst_0 (i_rxlane_rst_0 ),//I
.i_rxlane_rst_1 (i_rxlane_rst_1 ),//I
.i_rxlane_rst_2 (i_rxlane_rst_2 ),//I
.i_rxlane_rst_3 (i_rxlane_rst_3 ),//I
.i_rx_rate_chng_0 (p_rx_rate_chng_0 ),//I
.i_rx_rate_chng_1 (p_rx_rate_chng_1 ),//I
.i_rx_rate_chng_2 (p_rx_rate_chng_2 ),//I
.i_rx_rate_chng_3 (p_rx_rate_chng_3 ),//I
.i_rxckdiv_0 (p_rxckdiv_0 ),//I
.i_rxckdiv_1 (p_rxckdiv_1 ),//I
.i_rxckdiv_2 (p_rxckdiv_2 ),//I
.i_rxckdiv_3 (p_rxckdiv_3 ),//I
.i_force_rxfsm_det_0 (i_force_rxfsm_det_0 ),//I
.i_force_rxfsm_det_1 (i_force_rxfsm_det_1 ),//I
.i_force_rxfsm_det_2 (i_force_rxfsm_det_2 ),//I
.i_force_rxfsm_det_3 (i_force_rxfsm_det_3 ),//I
.i_force_rxfsm_lsm_0 (i_force_rxfsm_lsm_0 ),//I
.i_force_rxfsm_lsm_1 (i_force_rxfsm_lsm_1 ),//I
.i_force_rxfsm_lsm_2 (i_force_rxfsm_lsm_2 ),//I
.i_force_rxfsm_lsm_3 (i_force_rxfsm_lsm_3 ),//I
.i_force_rxfsm_cdr_0 (i_force_rxfsm_cdr_0 ),//I
.i_force_rxfsm_cdr_1 (i_force_rxfsm_cdr_1 ),//I
.i_force_rxfsm_cdr_2 (i_force_rxfsm_cdr_2 ),//I
.i_force_rxfsm_cdr_3 (i_force_rxfsm_cdr_3 ),//I
.i_pcs_cb_rst_0 (i_pcs_cb_rst_0 ),//I
.i_pcs_cb_rst_1 (i_pcs_cb_rst_1 ),//I
.i_pcs_cb_rst_2 (i_pcs_cb_rst_2 ),//I
.i_pcs_cb_rst_3 (i_pcs_cb_rst_3 ),//I
.i_pll_lock_rx_0 (i_pll_lock_rx_0 ),//I
.i_pll_lock_rx_1 (i_pll_lock_rx_1 ),//I
.i_pll_lock_rx_2 (i_pll_lock_rx_2 ),//I
.i_pll_lock_rx_3 (i_pll_lock_rx_3 ),//I
.P_RX_SIGDET_STATUS_0 (P_RX_SIGDET_STATUS_0 ),//I
.P_RX_SIGDET_STATUS_1 (P_RX_SIGDET_STATUS_1 ),//I
.P_RX_SIGDET_STATUS_2 (P_RX_SIGDET_STATUS_2 ),//I
.P_RX_SIGDET_STATUS_3 (P_RX_SIGDET_STATUS_3 ),//I
.P_RX_READY_0 (P_RX_READY_0 ),//I
.P_RX_READY_1 (P_RX_READY_1 ),//I
.P_RX_READY_2 (P_RX_READY_2 ),//I
.P_RX_READY_3 (P_RX_READY_3 ),//I
.P_PCS_LSM_SYNCED_0 (P_PCS_LSM_SYNCED_0 ),//I
.P_PCS_LSM_SYNCED_1 (P_PCS_LSM_SYNCED_1 ),//I
.P_PCS_LSM_SYNCED_2 (P_PCS_LSM_SYNCED_2 ),//I
.P_PCS_LSM_SYNCED_3 (P_PCS_LSM_SYNCED_3 ),//I
.P_PCS_RX_MCB_STATUS_0 (P_PCS_RX_MCB_STATUS_0 ),//I
.P_PCS_RX_MCB_STATUS_1 (P_PCS_RX_MCB_STATUS_1 ),//I
.P_PCS_RX_MCB_STATUS_2 (P_PCS_RX_MCB_STATUS_2 ),//I
.P_PCS_RX_MCB_STATUS_3 (P_PCS_RX_MCB_STATUS_3 ),//I
.P_RX_LANE_PD_0 (P_RX_LANE_PD_0 ),//O
.P_RX_LANE_PD_1 (P_RX_LANE_PD_1 ),//O
.P_RX_LANE_PD_2 (P_RX_LANE_PD_2 ),//O
.P_RX_LANE_PD_3 (P_RX_LANE_PD_3 ),//O
.P_RX_PMA_RST_0 (P_RX_PMA_RST_0 ),//O
.P_RX_PMA_RST_1 (P_RX_PMA_RST_1 ),//O
.P_RX_PMA_RST_2 (P_RX_PMA_RST_2 ),//O
.P_RX_PMA_RST_3 (P_RX_PMA_RST_3 ),//O
.P_PCS_RX_RST_0 (P_PCS_RX_RST_0 ),//O
.P_PCS_RX_RST_1 (P_PCS_RX_RST_1 ),//O
.P_PCS_RX_RST_2 (P_PCS_RX_RST_2 ),//O
.P_PCS_RX_RST_3 (P_PCS_RX_RST_3 ),//O
.P_RX_RATE_0 (P_RX_RATE_0 ),//O
.P_RX_RATE_1 (P_RX_RATE_1 ),//O
.P_RX_RATE_2 (P_RX_RATE_2 ),//O
.P_RX_RATE_3 (P_RX_RATE_3 ),//O
.P_PCS_CB_RST_0 (P_PCS_CB_RST_0 ),//O
.P_PCS_CB_RST_1 (P_PCS_CB_RST_1 ),//O
.P_PCS_CB_RST_2 (P_PCS_CB_RST_2 ),//O
.P_PCS_CB_RST_3 (P_PCS_CB_RST_3 ),//O
.o_rxlane_done_0 (o_rxlane_done_0 ),//O
.o_rxlane_done_1 (o_rxlane_done_1 ),//O
.o_rxlane_done_2 (o_rxlane_done_2 ),//O
.o_rxlane_done_3 (o_rxlane_done_3 ),//O
.o_rxckdiv_done_0 (o_rx_ckdiv_done_0 ),//O
.o_rxckdiv_done_1 (o_rx_ckdiv_done_1 ),//O
.o_rxckdiv_done_2 (o_rx_ckdiv_done_2 ),//O
.o_rxckdiv_done_3 (o_rx_ckdiv_done_3 )//O
);
end
else begin : USER_MODE
assign o_wtchdg_st_0 = 2'b0 ;
assign o_wtchdg_st_1 = 2'b0 ;
assign o_pll_done_0 = 1'b0 ;
assign o_pll_done_1 = 1'b0 ;
assign o_txlane_done_0 = 1'b0 ;
assign o_txlane_done_1 = 1'b0 ;
assign o_txlane_done_2 = 1'b0 ;
assign o_txlane_done_3 = 1'b0 ;
assign o_tx_ckdiv_done_0 = 1'b0 ;
assign o_tx_ckdiv_done_1 = 1'b0 ;
assign o_tx_ckdiv_done_2 = 1'b0 ;
assign o_tx_ckdiv_done_3 = 1'b0 ;
assign o_rxlane_done_0 = 1'b0 ;
assign o_rxlane_done_1 = 1'b0 ;
assign o_rxlane_done_2 = 1'b0 ;
assign o_rxlane_done_3 = 1'b0 ;
assign o_rx_ckdiv_done_0 = 1'b0 ;
assign o_rx_ckdiv_done_1 = 1'b0 ;
assign o_rx_ckdiv_done_2 = 1'b0 ;
assign o_rx_ckdiv_done_3 = 1'b0 ;
//Direct To HSST
assign P_PLLPOWERDOWN_0 = i_f_pllpowerdown_0 ;
assign P_PLLPOWERDOWN_1 = i_f_pllpowerdown_1 ;
assign P_PLL_RST_0 = i_f_pll_rst_0 ;
assign P_PLL_RST_1 = i_f_pll_rst_1 ;
assign P_LANE_SYNC_0 = i_f_lane_sync_0 ;
assign P_LANE_SYNC_1 = i_f_lane_sync_1 ;
assign P_LANE_SYNC_EN_0 = i_f_lane_sync_en_0 ;
assign P_LANE_SYNC_EN_1 = i_f_lane_sync_en_1 ;
assign P_RATE_CHANGE_TCLK_ON_0 = i_f_rate_change_tclk_on_0 ;
assign P_RATE_CHANGE_TCLK_ON_1 = i_f_rate_change_tclk_on_1 ;
assign P_TX_LANE_PD_0 = i_f_tx_lane_pd_0 ;
assign P_TX_LANE_PD_1 = i_f_tx_lane_pd_1 ;
assign P_TX_LANE_PD_2 = i_f_tx_lane_pd_2 ;
assign P_TX_LANE_PD_3 = i_f_tx_lane_pd_3 ;
assign P_TX_RATE_0 = {1'b0,i_f_tx_ckdiv_0} ;
assign P_TX_RATE_1 = {1'b0,i_f_tx_ckdiv_1} ;
assign P_TX_RATE_2 = {1'b0,i_f_tx_ckdiv_2} ;
assign P_TX_RATE_3 = {1'b0,i_f_tx_ckdiv_3} ;
assign P_TX_PMA_RST_0 = i_f_tx_pma_rst_0 ;
assign P_TX_PMA_RST_1 = i_f_tx_pma_rst_1 ;
assign P_TX_PMA_RST_2 = i_f_tx_pma_rst_2 ;
assign P_TX_PMA_RST_3 = i_f_tx_pma_rst_3 ;
assign P_PCS_TX_RST_0 = i_f_pcs_tx_rst_0 ;
assign P_PCS_TX_RST_1 = i_f_pcs_tx_rst_1 ;
assign P_PCS_TX_RST_2 = i_f_pcs_tx_rst_2 ;
assign P_PCS_TX_RST_3 = i_f_pcs_tx_rst_3 ;
assign P_LANE_PD_0 = i_f_lane_pd_0 ;
assign P_LANE_PD_1 = i_f_lane_pd_1 ;
assign P_LANE_PD_2 = i_f_lane_pd_2 ;
assign P_LANE_PD_3 = i_f_lane_pd_3 ;
assign P_LANE_RST_0 = i_f_lane_rst_0 ;
assign P_LANE_RST_1 = i_f_lane_rst_1 ;
assign P_LANE_RST_2 = i_f_lane_rst_2 ;
assign P_LANE_RST_3 = i_f_lane_rst_3 ;
assign P_RX_LANE_PD_0 = i_f_rx_lane_pd_0 ;
assign P_RX_LANE_PD_1 = i_f_rx_lane_pd_1 ;
assign P_RX_LANE_PD_2 = i_f_rx_lane_pd_2 ;
assign P_RX_LANE_PD_3 = i_f_rx_lane_pd_3 ;
assign P_RX_PMA_RST_0 = i_f_rx_pma_rst_0 ;
assign P_RX_PMA_RST_1 = i_f_rx_pma_rst_1 ;
assign P_RX_PMA_RST_2 = i_f_rx_pma_rst_2 ;
assign P_RX_PMA_RST_3 = i_f_rx_pma_rst_3 ;
assign P_PCS_RX_RST_0 = i_f_pcs_rx_rst_0 ;
assign P_PCS_RX_RST_1 = i_f_pcs_rx_rst_1 ;
assign P_PCS_RX_RST_2 = i_f_pcs_rx_rst_2 ;
assign P_PCS_RX_RST_3 = i_f_pcs_rx_rst_3 ;
assign P_RX_RATE_0 = {1'b0,i_f_lx_rx_ckdiv_0} ;
assign P_RX_RATE_1 = {1'b0,i_f_lx_rx_ckdiv_1} ;
assign P_RX_RATE_2 = {1'b0,i_f_lx_rx_ckdiv_2} ;
assign P_RX_RATE_3 = {1'b0,i_f_lx_rx_ckdiv_3} ;
assign P_PCS_CB_RST_0 = i_f_pcs_cb_rst_0 ;
assign P_PCS_CB_RST_1 = i_f_pcs_cb_rst_1 ;
assign P_PCS_CB_RST_2 = i_f_pcs_cb_rst_2 ;
assign P_PCS_CB_RST_3 = i_f_pcs_cb_rst_3 ;
end
endgenerate
endmodule |
module ipml_hsst_pll_rst_fsm_v1_0#(
parameter FREE_CLOCK_FREQ = 100 //unit is MHz, free clock freq from GUI
)(
// Reset and Clock
input wire clk ,
input wire rst_n ,
// HSST Reset Control Signal
input wire pll_lock ,
output reg P_PLLPOWERDOWN,
output reg P_PLL_RST ,
output reg o_pll_done
);
localparam CNTR_WIDTH = 14;
`ifdef IPML_HSST_SPEEDUP_SIM
localparam integer PLL_PD_CNTR_VALUE = 2*(1*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer PLL_RST_F_CNTR_VALUE = 2*(2*FREE_CLOCK_FREQ);//add 50 percent margin
`else
localparam integer PLL_PD_CNTR_VALUE = 2*(40*FREE_CLOCK_FREQ);//add 50 percent margin
localparam integer PLL_RST_F_CNTR_VALUE = 2*(41*FREE_CLOCK_FREQ);//add 50 percent margin
`endif
localparam PLL_IDLE = 2'd0;
localparam PLL_RST = 2'd1;
localparam PLL_DONE = 2'd2;
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
reg [CNTR_WIDTH-1 : 0] cntr ;
reg [1 : 0] pll_fsm ;
reg [1 : 0] next_state ;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
pll_fsm <= PLL_IDLE ;
end
else begin
pll_fsm <= next_state ;
end
end
always @ (*) begin
case(pll_fsm)
PLL_IDLE : begin
next_state = PLL_RST ;
end
PLL_RST : begin
if((cntr == PLL_RST_F_CNTR_VALUE) && pll_lock ) begin
next_state = PLL_DONE ;
end
else begin
next_state = PLL_RST ;
end
end
PLL_DONE : begin
next_state = PLL_DONE ;
end
default : begin
next_state = PLL_IDLE ;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cntr <= {CNTR_WIDTH{1'b0}} ;
P_PLLPOWERDOWN <= 1'b1 ;
P_PLL_RST <= 1'b1 ;
o_pll_done <= 1'b0 ;
end
else begin
case(pll_fsm)
PLL_IDLE : begin
P_PLLPOWERDOWN <= 1'b1 ;
P_PLL_RST <= 1'b1 ;
o_pll_done <= 1'b0 ;
end
PLL_RST : begin
if(cntr == PLL_RST_F_CNTR_VALUE) begin
P_PLL_RST <= 1'b0 ;
if(pll_lock) begin
cntr <= {CNTR_WIDTH{1'b0}} ;
end
end
else begin
cntr <= cntr + {{CNTR_WIDTH-1{1'b0}},{1'b1}} ;
if(cntr == PLL_PD_CNTR_VALUE) begin
P_PLLPOWERDOWN <= 1'b0 ;
end
end
end
PLL_DONE : begin
o_pll_done <= 1'b1 ;
end
default : begin
cntr <= {CNTR_WIDTH{1'b0}} ;
P_PLLPOWERDOWN <= 1'b1 ;
P_PLL_RST <= 1'b1 ;
o_pll_done <= 1'b0 ;
end
endcase
end
end
endmodule |
module ipml_hsst_rst_wtchdg_v1_0 #(
parameter ACTIVE_HIGH = 0, // 0 : active@low, 1 : active@high
parameter WTCHDG_CNTR1_WIDTH = 10, //(2**(WTCHDG_CNTR1_WIDTH-1)) = 512
parameter WTCHDG_CNTR2_WIDTH = 10 //watchdog time = (2**(WTCHDG_CNTR2_WIDTH-1))*(2**(WTCHDG_CNTR1_WIDTH-1)) = 256k;
//watchdog reset length = (2**(WTCHDG_CNTR1_WIDTH-1))
)(
input wire clk,
input wire rst_n,
input wire wtchdg_clr,
input wire wtchdg_in,
output reg wtchdg_rst_n,
output reg [1 :0] wtchdg_st
);
wire wtchdg_in_mux;
reg [WTCHDG_CNTR1_WIDTH-1:0] cnt_1;
reg [WTCHDG_CNTR2_WIDTH-1:0] cnt_2;
assign wtchdg_in_mux = (ACTIVE_HIGH == 1'b1) ? ~wtchdg_in : wtchdg_in;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
cnt_1 <= {WTCHDG_CNTR1_WIDTH{1'b0}};
end
else if(cnt_1[WTCHDG_CNTR1_WIDTH-1] | wtchdg_in_mux | wtchdg_clr)
begin
cnt_1 <= {WTCHDG_CNTR1_WIDTH{1'b0}};
end
else
begin
cnt_1 <= cnt_1 + { {(WTCHDG_CNTR1_WIDTH-1){1'b0}}, 1'b1};
end
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
cnt_2 <= {WTCHDG_CNTR2_WIDTH{1'b0}};
end
else if(wtchdg_clr | wtchdg_in_mux | (cnt_2[WTCHDG_CNTR2_WIDTH-1] & cnt_2[0]) )
begin
cnt_2 <= {WTCHDG_CNTR2_WIDTH{1'b0}};
end
else if(cnt_1[WTCHDG_CNTR1_WIDTH-1])
begin
cnt_2 <= cnt_2 + { {(WTCHDG_CNTR2_WIDTH-1){1'b0}}, 1'b1};
end
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
wtchdg_rst_n <= 1'b1;
end
else if(cnt_2[WTCHDG_CNTR2_WIDTH-1])
begin
wtchdg_rst_n <= 1'b0;
end
else
begin
wtchdg_rst_n <= 1'b1;
end
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
wtchdg_st <= 2'b0;
else if(wtchdg_in_mux | wtchdg_clr)
wtchdg_st <= 2'b0; //Waiting
else if(cnt_2[WTCHDG_CNTR2_WIDTH-1])
wtchdg_st <= 2'b10;//Alarming
else
wtchdg_st <= 2'b01;//Counting
end
endmodule |
module ipml_hsst_rst_sync_v1_0
(
input clk,
input rst_n,
input sig_async,
output reg sig_synced
);
//
reg sig_async_ff;
//single bit
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
sig_async_ff <= 1'b0;
else
sig_async_ff <= sig_async;
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
sig_synced <= 1'b0;
else
sig_synced <= sig_async_ff;
end
endmodule |
module ipml_hsst_fifo_clr_v1_0#(
parameter CH0_RX_ENABLE = "TRUE" , //TRUE:lane0 RX Reset Logic used, FALSE: lane0 RX Reset Logic remove
parameter CH1_RX_ENABLE = "TRUE" , //TRUE:lane1 RX Reset Logic used, FALSE: lane1 RX Reset Logic remove
parameter CH2_RX_ENABLE = "TRUE" , //TRUE:lane2 RX Reset Logic used, FALSE: lane2 RX Reset Logic remove
parameter CH3_RX_ENABLE = "TRUE" , //TRUE:lane3 RX Reset Logic used, FALSE: lane3 RX Reset Logic remove
parameter CH0_MULT_LANE_MODE = 1 , //Lane0 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH1_MULT_LANE_MODE = 1 , //Lane1 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH2_MULT_LANE_MODE = 1 , //Lane2 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH3_MULT_LANE_MODE = 1 , //Lane3 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter PCS_CH0_BYPASS_BONDING = "FALSE" , //TRUE: Lane0 Bypass Channel Bonding, FALSE: Lane0 No Bypass Channel Bonding
parameter PCS_CH1_BYPASS_BONDING = "FALSE" , //TRUE: Lane1 Bypass Channel Bonding, FALSE: Lane1 No Bypass Channel Bonding
parameter PCS_CH2_BYPASS_BONDING = "FALSE" , //TRUE: Lane2 Bypass Channel Bonding, FALSE: Lane2 No Bypass Channel Bonding
parameter PCS_CH3_BYPASS_BONDING = "FALSE" //TRUE: Lane3 Bypass Channel Bonding, FALSE: Lane3 No Bypass Channel Bonding
)(
// Reset and Clock
input wire clk ,
input wire [3 : 0] rst_n ,
input wire i_hsst_fifo_clr_0 ,
input wire i_hsst_fifo_clr_1 ,
input wire i_hsst_fifo_clr_2 ,
input wire i_hsst_fifo_clr_3 ,
// HSST Reset Control Signal
input wire [3 : 0] cdr_align ,
input wire [3 : 0] rxlane_done ,
output wire [3 : 0] fifo_clr_en
);
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
reg [3 : 0] cdr_align_lock ;
wire [3 : 0] cdr_align_vld ;
reg [3 : 0] cdr_align_vld_ff1 ;
wire [3 : 0] cdr_align_vld_pos ;
wire [3 : 0] i_hsst_fifo_clr ;
wire rxlane0_rstn ;
wire rxlane2_rstn ;
reg [3 : 0] tx_fifo_clr_en ;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
assign rxlane0_rstn = rst_n[0];//master lane0 reset port when lane0 is bonding
assign rxlane2_rstn = rst_n[2];//master lane2 reset port when lane2 is bonding
assign cdr_align_vld[0] = (CH0_RX_ENABLE=="TRUE") ? cdr_align[0]: 1'b0;
assign cdr_align_vld[1] = (CH1_RX_ENABLE=="TRUE") ? cdr_align[1]: 1'b0;
assign cdr_align_vld[2] = (CH2_RX_ENABLE=="TRUE") ? cdr_align[2]: 1'b0;
assign cdr_align_vld[3] = (CH3_RX_ENABLE=="TRUE") ? cdr_align[3]: 1'b0;
assign i_hsst_fifo_clr = {i_hsst_fifo_clr_3,i_hsst_fifo_clr_2,i_hsst_fifo_clr_1,i_hsst_fifo_clr_0};
assign cdr_align_vld_pos = cdr_align_vld & (~cdr_align_vld_ff1);
genvar i;
generate
for(i=0; i<4; i=i+1) begin : CDR_LOCK
always @ (posedge clk or negedge rst_n[i]) begin
if(!rst_n[i])
cdr_align_vld_ff1[i] <= 4'b0;
else
cdr_align_vld_ff1[i] <= cdr_align_vld[i];
end
always @ (posedge clk or negedge rst_n[i]) begin
if(!rst_n[i])
cdr_align_lock[i] <= 1'b0;
else if(fifo_clr_en[i]==1'b1)
cdr_align_lock[i] <= 1'b0;
else if(cdr_align_vld_pos[i]==1'b1)
cdr_align_lock[i] <= 1'b1;
else ;
end
end
endgenerate
generate
if(CH0_MULT_LANE_MODE==4) begin: FOUR_LANE_MODE
//generate clr enable
always @ (posedge clk or negedge rxlane0_rstn) begin
if(!rxlane0_rstn)
tx_fifo_clr_en <= 4'b0;
else if(PCS_CH0_BYPASS_BONDING=="TRUE")
tx_fifo_clr_en <= i_hsst_fifo_clr;
else if((|cdr_align_lock) && (&rxlane_done))
tx_fifo_clr_en <= 4'b1111;
else
tx_fifo_clr_en <= 4'b0;
end
assign fifo_clr_en = tx_fifo_clr_en;
end
else if(CH0_MULT_LANE_MODE==2 && CH2_MULT_LANE_MODE==2) begin:TWO_LANE_MODE
//generate clr enable
always @ (posedge clk or negedge rxlane0_rstn) begin
if(!rxlane0_rstn)
tx_fifo_clr_en[1:0] <= 2'b0;
else if(PCS_CH0_BYPASS_BONDING=="TRUE")
tx_fifo_clr_en[1:0] <= i_hsst_fifo_clr[1:0];
else if((|cdr_align_lock[1:0]) && (&rxlane_done[1:0]))
tx_fifo_clr_en[1:0] <= 2'b11;
else
tx_fifo_clr_en[1:0] <= 2'b0;
end
//generate clr enable
always @ (posedge clk or negedge rxlane2_rstn) begin
if(!rxlane2_rstn)
tx_fifo_clr_en[3:2] <= 2'b0;
else if(PCS_CH2_BYPASS_BONDING=="TRUE")
tx_fifo_clr_en[3:2] <= i_hsst_fifo_clr[3:2];
else if((|cdr_align_lock[3:2]) && (&rxlane_done[3:2]))
tx_fifo_clr_en[3:2] <= 2'b11;
else
tx_fifo_clr_en[3:2] <= 2'b0;
end
assign fifo_clr_en = tx_fifo_clr_en;
end
else if(CH0_MULT_LANE_MODE==2) begin:TWO_LANE_MODE0
//generate clr enable
always @ (posedge clk or negedge rxlane0_rstn) begin
if(!rxlane0_rstn)
tx_fifo_clr_en <= 4'b0000;
else if(PCS_CH0_BYPASS_BONDING=="TRUE")
tx_fifo_clr_en <= {2'b00,i_hsst_fifo_clr[1:0]};
else if((|cdr_align_lock[1:0]) && (&rxlane_done[1:0]))
tx_fifo_clr_en <= 4'b0011;
else
tx_fifo_clr_en <= 4'b0000;
end
assign fifo_clr_en = tx_fifo_clr_en;
end
else if(CH2_MULT_LANE_MODE==2) begin:TWO_LANE_MODE1
//generate clr enable
always @ (posedge clk or negedge rxlane2_rstn) begin
if(!rxlane2_rstn)
tx_fifo_clr_en <= 4'b0000;
else if(PCS_CH2_BYPASS_BONDING=="TRUE")
tx_fifo_clr_en <= {i_hsst_fifo_clr[3:2],2'b00};
else if((|cdr_align_lock[3:2]) && (&rxlane_done[3:2]))
tx_fifo_clr_en <= 4'b1100;
else
tx_fifo_clr_en <= 4'b0000;
end
assign fifo_clr_en = tx_fifo_clr_en;
end
else begin : ONE_LANE_MODE
assign fifo_clr_en = 4'b0;
end
endgenerate
endmodule |
module ipml_hsst_lane_powerup_v1_0#(
parameter FREE_CLOCK_FREQ = 100 , //Unit is MHz, free clock freq from GUI Freq: 0~200MHz
parameter CH0_TX_ENABLE = "TRUE" , //TRUE:lane0 TX Reset Logic used, FALSE: lane0 TX Reset Logic remove
parameter CH1_TX_ENABLE = "TRUE" , //TRUE:lane1 TX Reset Logic used, FALSE: lane1 TX Reset Logic remove
parameter CH2_TX_ENABLE = "TRUE" , //TRUE:lane2 TX Reset Logic used, FALSE: lane2 TX Reset Logic remove
parameter CH3_TX_ENABLE = "TRUE" , //TRUE:lane3 TX Reset Logic used, FALSE: lane3 TX Reset Logic remove
parameter CH0_RX_ENABLE = "TRUE" , //TRUE:lane0 RX Reset Logic used, FALSE: lane0 RX Reset Logic remove
parameter CH1_RX_ENABLE = "TRUE" , //TRUE:lane1 RX Reset Logic used, FALSE: lane1 RX Reset Logic remove
parameter CH2_RX_ENABLE = "TRUE" , //TRUE:lane2 RX Reset Logic used, FALSE: lane2 RX Reset Logic remove
parameter CH3_RX_ENABLE = "TRUE" , //TRUE:lane3 RX Reset Logic used, FALSE: lane3 RX Reset Logic remove
parameter CH0_MULT_LANE_MODE = 1 , //Lane0 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH1_MULT_LANE_MODE = 1 , //Lane1 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH2_MULT_LANE_MODE = 1 , //Lane2 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH3_MULT_LANE_MODE = 1 , //Lane3 --> 1: Singel Lane 2:Two Lane 4:Four Lane
parameter CH0_TX_PLL_SEL = 0 ,//Lane0 --> 1:PLL1 0:PLL0
parameter CH1_TX_PLL_SEL = 0 ,//Lane1 --> 1:PLL1 0:PLL0
parameter CH2_TX_PLL_SEL = 0 ,//Lane2 --> 1:PLL1 0:PLL0
parameter CH3_TX_PLL_SEL = 0 ,//Lane3 --> 1:PLL1 0:PLL0
parameter CH0_RX_PLL_SEL = 0 ,//Lane0 --> 1:PLL1 0:PLL0
parameter CH1_RX_PLL_SEL = 0 ,//Lane1 --> 1:PLL1 0:PLL0
parameter CH2_RX_PLL_SEL = 0 ,//Lane2 --> 1:PLL1 0:PLL0
parameter CH3_RX_PLL_SEL = 0 //Lane3 --> 1:PLL1 0:PLL0
)(
// Reset and Clock
input wire clk ,
input wire i_lane_pd_0 ,
input wire i_lane_pd_1 ,
input wire i_lane_pd_2 ,
input wire i_lane_pd_3 ,
input wire o_pll_done_0 ,
input wire o_pll_done_1 ,
output wire P_LANE_PD_0 ,
output wire P_LANE_PD_1 ,
output wire P_LANE_PD_2 ,
output wire P_LANE_PD_3 ,
output wire P_LANE_RST_0 ,
output wire P_LANE_RST_1 ,
output wire P_LANE_RST_2 ,
output wire P_LANE_RST_3
);
`ifdef IPML_HSST_SPEEDUP_SIM
localparam integer LANE_PD_CNTR_VALUE = 2*((1*FREE_CLOCK_FREQ)); //add 50 percent margin
localparam integer LANE_RST_CNTR_VALUE = 2*((2*FREE_CLOCK_FREQ)); //add 50 percent margin
`else
localparam integer LANE_PD_CNTR_VALUE = 2*((40*FREE_CLOCK_FREQ)); //add 50 percent margin
localparam integer LANE_RST_CNTR_VALUE = 2*((41*FREE_CLOCK_FREQ)); //add 50 percent margin
`endif
//Counter Width
localparam CNTR_WIDTH = 14 ;
//****************************************************************************//
// Internal Signal //
//****************************************************************************//
wire [4-1 :0] o_lane_pd ;
wire [4-1 :0] o_lane_rst ;
wire [4-1 :0] p_lane_pd ;
wire [4-1 :0] p_lane_rst ;
//****************************************************************************//
// Sequential and Logic //
//****************************************************************************//
//----- Instance Lane Powerup Logic Module -----------
//Lane0
generate
if(CH0_TX_ENABLE=="TRUE" || CH0_RX_ENABLE=="TRUE") begin : LANE0_ENABLE //Lane is Enable
//signal
wire i_lane_pd_n_0 ;
wire s_lane_pd_n_0 ;
wire lane_pd_n_0 ;
reg o_lane_pd_0 ;
reg o_lane_rst_0 ;
reg [CNTR_WIDTH-1 : 0] cntr0 ;
//logic
assign i_lane_pd_n_0 = ~i_lane_pd_0 ;
ipml_hsst_rst_sync_v1_0 lane_pd_n_0_sync (.clk(clk), .rst_n(i_lane_pd_n_0), .sig_async(1'b1), .sig_synced(s_lane_pd_n_0));
assign lane_pd_n_0 = s_lane_pd_n_0 && o_pll_done_0 ;
always @(posedge clk or negedge lane_pd_n_0)
begin
if(!lane_pd_n_0)
cntr0 <= {CNTR_WIDTH{1'b0}} ;
else if (cntr0 == LANE_RST_CNTR_VALUE)
cntr0 <= cntr0 ;
else
cntr0 <= cntr0 + {{CNTR_WIDTH-1{1'b0}},{1'b1}} ;
end
always @(posedge clk or negedge lane_pd_n_0)
begin
if(!lane_pd_n_0)
o_lane_pd_0 <= 1'b1 ;
else if (cntr0 == LANE_PD_CNTR_VALUE)
o_lane_pd_0 <= 1'b0 ;
else
o_lane_pd_0 <= o_lane_pd_0 ;
end
always @(posedge clk or negedge lane_pd_n_0)
begin
if(!lane_pd_n_0)
o_lane_rst_0 <= 1'b1 ;
else if (cntr0 == LANE_RST_CNTR_VALUE)
o_lane_rst_0 <= 1'b0 ;
else
o_lane_rst_0 <= o_lane_rst_0 ;
end
assign o_lane_pd [0] = o_lane_pd_0 ;
assign o_lane_rst[0] = o_lane_rst_0 ;
end
else begin : LANE0_DISABLE //Lane is disable
assign o_lane_pd [0] = 1'b1 ;
assign o_lane_rst[0] = 1'b1 ;
end
endgenerate
//Lane1
generate
if((CH1_TX_ENABLE=="TRUE" || CH1_RX_ENABLE=="TRUE") && (CH1_MULT_LANE_MODE == 1)) begin : LANE1_ENABLE //Lane is Enable
//signal
wire i_lane_pd_n_1 ;
wire s_lane_pd_n_1 ;
wire lane_pd_n_1 ;
reg o_lane_pd_1 ;
reg o_lane_rst_1 ;
reg [CNTR_WIDTH-1 : 0] cntr1 ;
//logic
assign i_lane_pd_n_1 = ~i_lane_pd_1 ;
ipml_hsst_rst_sync_v1_0 lane_pd_n_1_sync (.clk(clk), .rst_n(i_lane_pd_n_1), .sig_async(1'b1), .sig_synced(s_lane_pd_n_1));
assign lane_pd_n_1 = s_lane_pd_n_1 && o_pll_done_0 ;
always @(posedge clk or negedge lane_pd_n_1)
begin
if(!lane_pd_n_1)
cntr1 <= {CNTR_WIDTH{1'b0}} ;
else if (cntr1 == LANE_RST_CNTR_VALUE)
cntr1 <= cntr1 ;
else
cntr1 <= cntr1 + {{CNTR_WIDTH-1{1'b0}},{1'b1}} ;
end
always @(posedge clk or negedge lane_pd_n_1)
begin
if(!lane_pd_n_1)
o_lane_pd_1 <= 1'b1 ;
else if (cntr1 == LANE_PD_CNTR_VALUE)
o_lane_pd_1 <= 1'b0 ;
else
o_lane_pd_1 <= o_lane_pd_1 ;
end
always @(posedge clk or negedge lane_pd_n_1)
begin
if(!lane_pd_n_1)
o_lane_rst_1 <= 1'b1 ;
else if (cntr1 == LANE_RST_CNTR_VALUE)
o_lane_rst_1 <= 1'b0 ;
else
o_lane_rst_1 <= o_lane_rst_1 ;
end
assign o_lane_pd [1] = o_lane_pd_1 ;
assign o_lane_rst[1] = o_lane_rst_1 ;
end
else begin : LANE1_DISABLE //Lane is disable
assign o_lane_pd [1] = 1'b1 ;
assign o_lane_rst[1] = 1'b1 ;
end
endgenerate
//Lane2
generate
if((CH2_TX_ENABLE=="TRUE" || CH2_RX_ENABLE=="TRUE") && (CH2_MULT_LANE_MODE != 4)) begin : LANE2_ENABLE //Lane is Enable
//signal
wire i_lane_pd_n_2 ;
wire s_lane_pd_n_2 ;
wire lane_pd_n_2 ;
wire pll_done_2 ;
reg o_lane_pd_2 ;
reg o_lane_rst_2 ;
reg [CNTR_WIDTH-1 : 0] cntr2 ;
//logic
assign i_lane_pd_n_2 = ~i_lane_pd_2 ;
ipml_hsst_rst_sync_v1_0 lane_pd_n_2_sync (.clk(clk), .rst_n(i_lane_pd_n_2), .sig_async(1'b1), .sig_synced(s_lane_pd_n_2));
assign pll_done_2 = (CH2_TX_ENABLE=="TRUE") ? ((CH2_TX_PLL_SEL==0) ? o_pll_done_0 : o_pll_done_1) :
((CH2_RX_PLL_SEL==0) ? o_pll_done_0 : o_pll_done_1) ;
assign lane_pd_n_2 = s_lane_pd_n_2 && pll_done_2 ;
always @(posedge clk or negedge lane_pd_n_2)
begin
if(!lane_pd_n_2)
cntr2 <= {CNTR_WIDTH{1'b0}} ;
else if (cntr2 == LANE_RST_CNTR_VALUE)
cntr2 <= cntr2 ;
else
cntr2 <= cntr2 + {{CNTR_WIDTH-1{1'b0}},{1'b1}} ;
end
always @(posedge clk or negedge lane_pd_n_2)
begin
if(!lane_pd_n_2)
o_lane_pd_2 <= 1'b1 ;
else if (cntr2 == LANE_PD_CNTR_VALUE)
o_lane_pd_2 <= 1'b0 ;
else
o_lane_pd_2 <= o_lane_pd_2 ;
end
always @(posedge clk or negedge lane_pd_n_2)
begin
if(!lane_pd_n_2)
o_lane_rst_2 <= 1'b1 ;
else if (cntr2 == LANE_RST_CNTR_VALUE)
o_lane_rst_2 <= 1'b0 ;
else
o_lane_rst_2 <= o_lane_rst_2 ;
end
assign o_lane_pd [2] = o_lane_pd_2 ;
assign o_lane_rst[2] = o_lane_rst_2 ;
end
else begin : LANE2_DISABLE //Lane is disable
assign o_lane_pd [2] = 1'b1 ;
assign o_lane_rst[2] = 1'b1 ;
end
endgenerate
//Lane3
generate
if((CH3_TX_ENABLE=="TRUE" || CH3_RX_ENABLE=="TRUE") && (CH3_MULT_LANE_MODE == 1)) begin : LANE3_ENABLE //Lane is Enable
//signal
wire i_lane_pd_n_3 ;
wire s_lane_pd_n_3 ;
wire lane_pd_n_3 ;
wire pll_done_3 ;
reg o_lane_pd_3 ;
reg o_lane_rst_3 ;
reg [CNTR_WIDTH-1 : 0] cntr3 ;
//logic
assign i_lane_pd_n_3 = ~i_lane_pd_3 ;
ipml_hsst_rst_sync_v1_0 lane_pd_n_3_sync (.clk(clk), .rst_n(i_lane_pd_n_3), .sig_async(1'b1), .sig_synced(s_lane_pd_n_3));
assign pll_done_3 = (CH3_TX_ENABLE=="TRUE") ? ((CH3_TX_PLL_SEL==0) ? o_pll_done_0 : o_pll_done_1) :
((CH3_RX_PLL_SEL==0) ? o_pll_done_0 : o_pll_done_1) ;
assign lane_pd_n_3 = s_lane_pd_n_3 && pll_done_3 ;
always @(posedge clk or negedge lane_pd_n_3)
begin
if(!lane_pd_n_3)
cntr3 <= {CNTR_WIDTH{1'b0}} ;
else if (cntr3 == LANE_RST_CNTR_VALUE)
cntr3 <= cntr3 ;
else
cntr3 <= cntr3 + {{CNTR_WIDTH-1{1'b0}},{1'b1}} ;
end
always @(posedge clk or negedge lane_pd_n_3)
begin
if(!lane_pd_n_3)
o_lane_pd_3 <= 1'b1 ;
else if (cntr3 == LANE_PD_CNTR_VALUE)
o_lane_pd_3 <= 1'b0 ;
else
o_lane_pd_3 <= o_lane_pd_3 ;
end
always @(posedge clk or negedge lane_pd_n_3)
begin
if(!lane_pd_n_3)
o_lane_rst_3 <= 1'b1 ;
else if (cntr3 == LANE_RST_CNTR_VALUE)
o_lane_rst_3 <= 1'b0 ;
else
o_lane_rst_3 <= o_lane_rst_3 ;
end
assign o_lane_pd [3] = o_lane_pd_3 ;
assign o_lane_rst[3] = o_lane_rst_3 ;
end
else begin : LANE3_DISABLE //Lane is disable
assign o_lane_pd [3] = 1'b1 ;
assign o_lane_rst[3] = 1'b1 ;
end
endgenerate
generate
if(CH0_MULT_LANE_MODE==4) begin:FOUR_LANE_MODE
//To HSST
assign p_lane_pd = {4{o_lane_pd [0]}};
assign p_lane_rst = {4{o_lane_rst [0]}};
end
else if(CH0_MULT_LANE_MODE==2 && CH2_MULT_LANE_MODE==2) begin: TWO_LANE_MODE
//To HSST
assign p_lane_pd = {{2{o_lane_pd [2]}},{2{o_lane_pd [0]}}};
assign p_lane_rst = {{2{o_lane_rst [2]}},{2{o_lane_rst [0]}}};
end
else if(CH0_MULT_LANE_MODE==2) begin:TWO_LANE_MODE0
//To HSST
assign p_lane_pd = {o_lane_pd [3],o_lane_pd [2],{2{o_lane_pd [0]}}};
assign p_lane_rst = {o_lane_rst [3],o_lane_rst [2],{2{o_lane_rst [0]}}};
end
else if(CH2_MULT_LANE_MODE==2) begin:TWO_LANE_MODE1
//To HSST
assign p_lane_pd = {{2{o_lane_pd [2]}},o_lane_pd [1],o_lane_pd [0]};
assign p_lane_rst = {{2{o_lane_rst [2]}},o_lane_rst [1],o_lane_rst [0]};
end
else begin:ONE_LANE_MODE
//To HSST
assign p_lane_pd = {o_lane_pd [3],o_lane_pd [2],o_lane_pd [1],o_lane_pd [0]};
assign p_lane_rst = {o_lane_rst [3],o_lane_rst [2],o_lane_rst [1],o_lane_rst [0]};
end
endgenerate
assign P_LANE_PD_0 = p_lane_pd[0] ;
assign P_LANE_PD_1 = p_lane_pd[1] ;
assign P_LANE_PD_2 = p_lane_pd[2] ;
assign P_LANE_PD_3 = p_lane_pd[3] ;
assign P_LANE_RST_0 = p_lane_rst[0];
assign P_LANE_RST_1 = p_lane_rst[1];
assign P_LANE_RST_2 = p_lane_rst[2];
assign P_LANE_RST_3 = p_lane_rst[3];
endmodule |
module ipml_fifo_ctrl_v1_3 #(
parameter c_WR_DEPTH_WIDTH = 9 , // write address width 9 -- 20
parameter c_RD_DEPTH_WIDTH = 9 , // read address width 9 -- 20
parameter c_FIFO_TYPE = "ASYN" , // ASYN or SYN
parameter c_ALMOST_FULL_NUM = 508 ,
parameter c_ALMOST_EMPTY_NUM = 4
)
(
input wire wclk , //write clock
input wire w_en , //write enable 1 active
output wire [c_WR_DEPTH_WIDTH-1 : 0] waddr , //write address
input wire wrst , //write reset
output wire wfull , //write full flag 1 active
output wire almost_full , //output write almost full
output reg [c_WR_DEPTH_WIDTH : 0] wr_water_level , //output write water level
input wire rclk , //read clock
input wire r_en , //read enable 1 active
output wire [c_RD_DEPTH_WIDTH-1 : 0] raddr , //read address
input wire rrst , //read reset
output wire rempty , //read empty 1 active
output reg [c_RD_DEPTH_WIDTH : 0] rd_water_level , //output read water level
output wire almost_empty //output read almost empty
);
//**************************************************************************************************************
//declare inner variables
//write address operation variables
reg [c_WR_DEPTH_WIDTH : 0] wptr ; //write pointer
reg [c_RD_DEPTH_WIDTH : 0] wrptr1 ; //1st read-domain to write-domain synchronizer
reg [c_RD_DEPTH_WIDTH : 0] wrptr2 ; //2nd read-domain to write-domain synchronizer
reg [c_WR_DEPTH_WIDTH : 0] wbin ; //write current binary pointer
reg [c_WR_DEPTH_WIDTH : 0] wbnext ; //write next binary pointer
reg [c_WR_DEPTH_WIDTH : 0] wgnext ; //wriet next gray pointer
reg waddr_msb ; //the MSB of waddr
//wire wgnext_2ndmsb ; //the second MSB of wgnext
//wire wrptr2_2ndmsb ; //the second MSB of wrptr2
//read address operation variables
reg [c_RD_DEPTH_WIDTH : 0] rptr ; //read pointer
reg [c_WR_DEPTH_WIDTH : 0] rwptr1 ; //1st write-domain to read-domain synchronizer
reg [c_WR_DEPTH_WIDTH : 0] rwptr2 ; //2nd write-domain to read-domain synchronizer
reg [c_RD_DEPTH_WIDTH : 0] rbin ; //read current binary pointer
reg [c_RD_DEPTH_WIDTH : 0] rbnext ; //read next binary pointer
reg [c_RD_DEPTH_WIDTH : 0] rgnext ; //read next gray pointer
reg raddr_msb ; //the MSB of raddr
reg [c_RD_DEPTH_WIDTH : 0] wrptr2_b ; //wrptr2 into binary
reg [c_WR_DEPTH_WIDTH : 0] rwptr2_b ; //rwptr2 into binary
reg asyn_wfull ;
reg asyn_almost_full ;
reg asyn_rempty ;
reg asyn_almost_empty ;
reg syn_wfull ;
reg syn_almost_full ;
reg syn_rempty ;
reg syn_almost_empty ;
wire [c_WR_DEPTH_WIDTH:0] wwptr;
wire [c_WR_DEPTH_WIDTH:0] wrptr;
wire [c_RD_DEPTH_WIDTH:0] rwptr;
wire [c_RD_DEPTH_WIDTH:0] rrptr;
//main code
//**************************************************************************************************************
generate
if(c_FIFO_TYPE == "ASYN")
begin:ASYN_CTRL
//write gray pointer generate
always@(*)
begin
if(!wfull)
wbnext = wbin + w_en;
else
wbnext = wbin;
end
always@(*)
begin
wgnext = (wbnext >> 1) ^ wbnext; //binary to gray converter
end
always@( posedge wclk or posedge wrst )
begin
if(wrst)
begin
wptr <=0;
waddr_msb <=0;
wbin <=0;
end
else
begin
wptr <= wgnext;
wbin <= wbnext;
waddr_msb <= wgnext[c_WR_DEPTH_WIDTH] ^ wgnext[c_WR_DEPTH_WIDTH-1];
end
end
//read domain to write domain synchronizer
always@(posedge wclk or posedge wrst)
begin
if(wrst)
{wrptr2,wrptr1} <= 0;
else
{wrptr2,wrptr1} <= {wrptr1,rptr};
end
integer i;
always@(*)
begin
for(i = 0;i <= c_RD_DEPTH_WIDTH;i = i+1 ) //gray to binary converter
wrptr2_b[i] = ^(wrptr2 >> i);
end
// //generate fifo write full flag
// assign wgnext_2ndmsb = wgnext[c_WR_DEPTH_WIDTH] ^ wgnext[c_WR_DEPTH_WIDTH-1];
// assign wrptr2_2ndmsb = wrptr2[c_WR_DEPTH_WIDTH] ^ wrptr2[c_WR_DEPTH_WIDTH-1];
//**************************************************************************************************************
//read gray pointer generate
always@(*)
begin
if(!rempty)
rbnext = rbin + r_en;
else
rbnext = rbin;
rgnext = (rbnext >> 1) ^ rbnext; //binary to gray converter
end
always@( posedge rclk or posedge rrst )
begin
if(rrst)
begin
rptr <=0;
raddr_msb <=0;
rbin <=0;
end
else
begin
rptr <= rgnext;
rbin <= rbnext;
raddr_msb <= rgnext[c_RD_DEPTH_WIDTH] ^ rgnext[c_RD_DEPTH_WIDTH-1];
end
end
//read domain to write domain synchronizer
always@(posedge rclk or posedge rrst)
begin
if(rrst)
{rwptr2,rwptr1} <= 0;
else
{rwptr2,rwptr1} <= {rwptr1,wptr};
end
always@(*)
begin
for(i = 0;i <= c_WR_DEPTH_WIDTH;i = i+1 ) //gray to binary converter
rwptr2_b[i] = ^(rwptr2 >> i);
end
if(c_WR_DEPTH_WIDTH > c_RD_DEPTH_WIDTH)
begin
assign wwptr = wbnext;
assign wrptr = {wrptr2_b,{(c_WR_DEPTH_WIDTH-c_RD_DEPTH_WIDTH){1'b0}}};
assign rwptr = rwptr2_b[c_WR_DEPTH_WIDTH:c_WR_DEPTH_WIDTH-c_RD_DEPTH_WIDTH];
assign rrptr = rbnext;
end
else
begin
assign wwptr = wbnext;
assign wrptr = wrptr2_b[c_RD_DEPTH_WIDTH:c_RD_DEPTH_WIDTH-c_WR_DEPTH_WIDTH];
assign rwptr = {rwptr2_b,{(c_RD_DEPTH_WIDTH-c_WR_DEPTH_WIDTH){1'b0}}};
assign rrptr = rbnext;
end
//generate async_fifo write full flag
always@(posedge wclk or posedge wrst)
begin
if(wrst)
asyn_wfull <= 1'b0;
else
asyn_wfull <= ((wwptr[c_WR_DEPTH_WIDTH] != wrptr[c_WR_DEPTH_WIDTH])
&& (wwptr[c_WR_DEPTH_WIDTH-1:0] == wrptr[c_WR_DEPTH_WIDTH-1:0]));
end
//generate async_fifo read empty flag generate
always@(posedge rclk or posedge rrst)
begin
if(rrst)
asyn_rempty <= 1'b1;
else
asyn_rempty <= (rrptr == rwptr);
end
end
else
begin:SYN_CTRL
//write operation
always@(*)
begin
if(!wfull)
wbnext = wptr + w_en;
else
wbnext = wptr;
end
always@(*)
begin
wgnext = wbnext; // syn fifo
end
always@( posedge wclk or posedge wrst )
begin
if(wrst)
begin
wptr <=0;
waddr_msb <=0;
wbin <=0;
end
else
begin
wptr <= wgnext;
wbin <= wbnext;
waddr_msb <= wgnext[c_WR_DEPTH_WIDTH-1];
end
end
always@(*)
begin
wrptr2 = rptr; // syn fifo
end
always@(*)
begin
wrptr2_b = rptr; // syn fifo
end
// //generate fifo write full flag
// assign wgnext_2ndmsb = wgnext[c_WR_DEPTH_WIDTH-1];
// assign wrptr2_2ndmsb = wrptr2[c_WR_DEPTH_WIDTH-1];
//**************************************************************************************************************
//read operation
always@(*)
begin
if(!rempty)
rbnext = rptr + r_en;
else
rbnext = rptr;
end
always@(*)
begin
rgnext = rbnext;
end
always@( posedge rclk or posedge rrst )
begin
if(rrst)
begin
rptr <=0;
raddr_msb <=0;
rbin <=0;
end
else
begin
rptr <= rgnext;
rbin <= rbnext;
raddr_msb <= rgnext[c_RD_DEPTH_WIDTH-1];
end
end
always@(*)
begin
rwptr2 = wptr; //syn fifo
end
always@(*)
begin
rwptr2_b = wptr; //syn fifo
end
//generate sync_fifo write full flag
if(c_WR_DEPTH_WIDTH > c_RD_DEPTH_WIDTH)
begin
assign wwptr = wbnext;
assign wrptr = {rbnext,{(c_WR_DEPTH_WIDTH-c_RD_DEPTH_WIDTH){1'b0}}};
assign rwptr = wbnext[c_WR_DEPTH_WIDTH:c_WR_DEPTH_WIDTH-c_RD_DEPTH_WIDTH];
assign rrptr = rbnext;
end
else
begin
assign wwptr = wbnext;
assign wrptr = rbnext[c_RD_DEPTH_WIDTH:c_RD_DEPTH_WIDTH-c_WR_DEPTH_WIDTH];
assign rwptr = {wbnext,{(c_RD_DEPTH_WIDTH-c_WR_DEPTH_WIDTH){1'b0}}};
assign rrptr = rbnext;
end
always@(posedge wclk or posedge wrst)
begin
if(wrst)
syn_wfull <= 1'b0;
else
syn_wfull <= ((wwptr[c_WR_DEPTH_WIDTH] != wrptr[c_WR_DEPTH_WIDTH])
&& (wwptr[c_WR_DEPTH_WIDTH-1:0] == wrptr[c_WR_DEPTH_WIDTH-1:0]));
end
//generate sync_fifo read empty flag generate
always@(posedge rclk or posedge rrst)
begin
if(rrst)
syn_rempty <= 1'b1;
else
syn_rempty <= (rwptr == rrptr);
end
end
endgenerate
//write flex memory address generate
assign waddr = wbin[c_WR_DEPTH_WIDTH-1:0];
//generate fifo write full flag
assign wfull = (c_FIFO_TYPE == "ASYN") ? asyn_wfull : syn_wfull;
//generate fifo write almost full flag
assign almost_full = (wr_water_level >= c_ALMOST_FULL_NUM) ? 1'b1:1'b0;
//generate write water level flag
always@(posedge wclk or posedge wrst)
begin
if(wrst)
wr_water_level <= 'b0;
else
wr_water_level <= ( wwptr[c_WR_DEPTH_WIDTH]==0 && wrptr[c_WR_DEPTH_WIDTH]==0 ) ? (wwptr[c_WR_DEPTH_WIDTH-1:0] - wrptr[c_WR_DEPTH_WIDTH-1:0]) :
( wwptr[c_WR_DEPTH_WIDTH]==0 && wrptr[c_WR_DEPTH_WIDTH]==1 ) ? ({1'b1,wwptr[c_WR_DEPTH_WIDTH-1:0]} - wrptr[c_WR_DEPTH_WIDTH-1:0] ):
( wwptr[c_WR_DEPTH_WIDTH]==1 && wrptr[c_WR_DEPTH_WIDTH]==0 ) ? (wwptr[c_WR_DEPTH_WIDTH :0] - wrptr[c_WR_DEPTH_WIDTH-1:0]) :
( wwptr[c_WR_DEPTH_WIDTH-1:0] - wrptr[c_WR_DEPTH_WIDTH-1:0]) ;
end
//read flex memory address generate
assign raddr = rbin[c_RD_DEPTH_WIDTH-1:0];
//fifo read empty flag generate
assign rempty = (c_FIFO_TYPE == "ASYN") ? asyn_rempty : syn_rempty;
//generate fifo read almost empty flag
assign almost_empty = (rd_water_level<= c_ALMOST_EMPTY_NUM) ? 1'b1:1'b0;
//generate read water level flag
always@(posedge rclk or posedge rrst)
begin
if(rrst)
rd_water_level <= 'b0;
else
rd_water_level <= ( rwptr[c_RD_DEPTH_WIDTH]==0 && rrptr[c_RD_DEPTH_WIDTH]==0 ) ? (rwptr[c_RD_DEPTH_WIDTH-1:0] - rrptr[c_RD_DEPTH_WIDTH-1:0]) :
( rwptr[c_RD_DEPTH_WIDTH]==0 && rrptr[c_RD_DEPTH_WIDTH]==1 ) ? ({1'b1,rwptr[c_RD_DEPTH_WIDTH-1:0]} - rrptr[c_RD_DEPTH_WIDTH-1:0] ):
( rwptr[c_RD_DEPTH_WIDTH]==1 && rrptr[c_RD_DEPTH_WIDTH]==0 ) ? (rwptr[c_RD_DEPTH_WIDTH :0] - rrptr[c_RD_DEPTH_WIDTH-1:0]) :
( rwptr[c_RD_DEPTH_WIDTH-1:0] - rrptr[c_RD_DEPTH_WIDTH-1:0]);
end
endmodule |
module ipml_reg_fifo_v1_0
#(
parameter W = 8
)
(
input clk,
input rst_n,
input data_in_valid,
input [W-1:0] data_in,
output data_in_ready,
input data_out_ready,
output [W-1:0] data_out,
output data_out_valid
);
//
reg [W-1:0] data_0;
reg [W-1:0] data_1;
reg wptr;
reg rptr;
reg data_valid_0;
reg data_valid_1;
wire fifo_read;
wire fifo_write;
// handshake
assign fifo_write = data_in_ready & data_in_valid;
assign fifo_read = data_out_valid & data_out_ready;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
wptr <= 1'b0;
else if (fifo_write)
wptr <= ~wptr;
end
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
rptr <= 1'b0;
else if (fifo_read)
rptr <= ~rptr;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_0 <= {W{1'b0}};
else if (fifo_write & ~wptr)
data_0 <= data_in;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_1 <= {W{1'b0}};
else if (fifo_write & wptr)
data_1 <= data_in;
end
// valid
assign data_out_valid = data_valid_0 | data_valid_1;
assign data_in_ready = ~data_valid_0 | ~data_valid_1;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_valid_0 <= 1'b0;
else if (fifo_write & ~wptr)
data_valid_0 <= 1'b1;
else if (fifo_read & ~rptr)
data_valid_0 <= 1'b0;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
data_valid_1 <= 1'b0;
else if (fifo_write & wptr)
data_valid_1 <= 1'b1;
else if (fifo_read & rptr)
data_valid_1 <= 1'b0;
end
//
assign data_out = ({W{rptr}} & data_1) | ({W{~rptr}} & data_0);
endmodule |
module ipml_fifo_v1_6_hdmi_pcie_fifo
#(
parameter c_SIM_DEVICE = "LOGOS" ,
parameter c_WR_DEPTH_WIDTH = 10 , // fifo depth width 9 -- 20 legal value:9~20
parameter c_WR_DATA_WIDTH = 32 , // write data width 1 -- 1152 1)c_WR_BYTE_EN =0 legal value:1~1152 2)c_WR_BYTE_EN=1 legal value:2^N or 9*2^N
parameter c_RD_DEPTH_WIDTH = 10 , // read address width 9 -- 20 legal value:1~20
parameter c_RD_DATA_WIDTH = 32 , // read data width 1 -- 1152 1)c_WR_BYTE_EN =0 legal value:1~1152 2)c_WR_BYTE_EN=1 legal value:2^N or 9*2^N
parameter c_OUTPUT_REG = 0 , // output register legal value:0 or 1
parameter c_RD_OCE_EN = 0 ,
parameter c_RESET_TYPE = "ASYNC_RESET" , // reset type legal valve "ASYNC_RESET_SYNC_RELEASE" "SYNC_RESET" "ASYNC_RESET"
parameter c_POWER_OPT = 0 , // 0 :normal mode 1:low power mode legal value:0 or 1
parameter c_RD_CLK_OR_POL_INV = 0 , // clk polarity invert for output register legal value: 0 or 1
parameter c_WR_BYTE_EN = 0 , // byte write enable legal value: 0 or 1
parameter c_BE_WIDTH = 8 , // byte width legal value: 1~128
parameter c_FIFO_TYPE = "SYN" , // fifo type legal value "SYN" or "ASYN"
parameter c_ALMOST_FULL_NUM = 508 , // almost full number
parameter c_ALMOST_EMPTY_NUM = 4 // almost full number
)
(
input wire [c_WR_DATA_WIDTH-1 : 0] wr_data , // input write data
input wire wr_en , // input write enable 1 active
input wire wr_clk , // input write clock
output wire wr_full , // input write full flag 1 active
input wire wr_rst , // input write reset
input wire [c_BE_WIDTH-1 : 0] wr_byte_en , // input write byte enable
output wire almost_full , // output write almost full
output wire [c_WR_DEPTH_WIDTH : 0] wr_water_level , // output write water level
output wire [c_RD_DATA_WIDTH-1 : 0] rd_data , // output read data
input wire rd_en , // input read enable
input wire rd_clk , // input read clock
output wire rd_empty , // output read empty
input wire rd_rst , // input read reset
input wire rd_oce , // output read output register enable
output wire almost_empty , // output read water level
output wire [c_RD_DEPTH_WIDTH : 0] rd_water_level
);
//**************************************************************************************************************
//declare inner variables
wire [c_WR_DEPTH_WIDTH-1 : 0] wr_addr;
wire [c_RD_DEPTH_WIDTH-1 : 0] rd_addr;
//**************************************************************************************************************
//instance ipml_flex_sdpram
ipml_sdpram_v1_6_hdmi_pcie_fifo
#(
.c_SIM_DEVICE (c_SIM_DEVICE),
.c_WR_ADDR_WIDTH (c_WR_DEPTH_WIDTH), //write address width
.c_WR_DATA_WIDTH (c_WR_DATA_WIDTH), //write data width
.c_RD_ADDR_WIDTH (c_RD_DEPTH_WIDTH), //read address width
.c_RD_DATA_WIDTH (c_RD_DATA_WIDTH), //read data width
.c_OUTPUT_REG (c_OUTPUT_REG), //output register
.c_RD_OCE_EN (c_RD_OCE_EN),
.c_WR_ADDR_STROBE_EN (0),
.c_RD_ADDR_STROBE_EN (0),
.c_WR_CLK_EN (1),
.c_RD_CLK_EN (1),
.c_RESET_TYPE (c_RESET_TYPE), //ASYNC_RESET_SYNC_RELEASE SYNC_RESET
.c_POWER_OPT (c_POWER_OPT), //0 :normal mode 1:low power mode
.c_RD_CLK_OR_POL_INV(c_RD_CLK_OR_POL_INV), //clk polarity invert for output register
.c_INIT_FILE ("NONE"), //false NONE or initial file name
.c_INIT_FORMAT ("BIN"), //bin or hex
.c_WR_BYTE_EN (c_WR_BYTE_EN), //false
.c_BE_WIDTH (c_BE_WIDTH)
) U_ipml_sdpram (
.wr_data (wr_data), //input write data [c_WR_DATA_WIDTH-1:0]
.wr_addr (wr_addr), //input write address [c_WR_DEPTH_WIDTH-1:0]
.wr_en (wr_en), //input write enable
.wr_clk (wr_clk), //input write clock
.wr_clk_en (1'b1), //input write clock enable
.wr_rst (wr_rst), //input write reset
.wr_byte_en (wr_byte_en),//"false"
.wr_addr_strobe (1'b0),
.rd_data (rd_data), //output read data [C_RD_DATA_WIDTH-1:0]
.rd_addr (rd_addr), //output read address [c_RD_DEPTH_WIDTH-1:0]
.rd_clk (rd_clk), //output read clock
.rd_clk_en (rd_en), //output read clock enable
.rd_rst (rd_rst), //output read reset
.rd_oce (rd_oce), //output read output register enable
.rd_addr_strobe (1'b0)
);
ipml_fifo_ctrl_v1_3
#(
.c_WR_DEPTH_WIDTH (c_WR_DEPTH_WIDTH),// write address width 8-- 20
.c_RD_DEPTH_WIDTH (c_RD_DEPTH_WIDTH),// read address width 8 -- 20
.c_FIFO_TYPE (c_FIFO_TYPE),
.c_ALMOST_FULL_NUM (c_ALMOST_FULL_NUM),
.c_ALMOST_EMPTY_NUM (c_ALMOST_EMPTY_NUM)
)
U_ipml_fifo_ctrl
(
.wclk (wr_clk), //write clock
.w_en (wr_en), //write enable 1 active
.waddr (wr_addr), //write address
.wrst (wr_rst), //write reset
.wfull (wr_full), //write full flag 1 active
.almost_full (almost_full),
.wr_water_level(wr_water_level),
.rclk (rd_clk), //read clock
.r_en (rd_en), //read enable 1 active
.raddr (rd_addr), //read address
.rrst (rd_rst), //read reset
.rempty (rd_empty), //read empty 1 active
.almost_empty (almost_empty),
.rd_water_level(rd_water_level)
);
endmodule |
module ipml_prefetch_fifo_v1_6_hdmi_pcie_fifo
#(
parameter c_SIM_DEVICE = "LOGOS" ,
parameter c_WR_DEPTH_WIDTH = 10 , // fifo depth width 9 -- 20 legal value:9~20
parameter c_WR_DATA_WIDTH = 32 , // write data width 1 -- 1152 1)c_WR_BYTE_EN =0 legal value:1~1152 2)c_WR_BYTE_EN=1 legal value:2^N or 9*2^N
parameter c_RD_DEPTH_WIDTH = 10 , // read address width 9 -- 20 legal value:1~20
parameter c_RD_DATA_WIDTH = 32 , // read data width 1 -- 1152 1)c_WR_BYTE_EN =0 legal value:1~1152 2)c_WR_BYTE_EN=1 legal value:2^N or 9*2^N
parameter c_RESET_TYPE = "ASYNC_RESET" , // reset type legal valve "ASYNC_RESET_SYNC_RELEASE" "SYNC_RESET" "ASYNC_RESET"
parameter c_POWER_OPT = 0 , // 0 :normal mode 1:low power mode legal value:0 or 1
parameter c_FIFO_TYPE = "SYN" // fifo type legal value "SYN" or "ASYN"
)
(
input wire [c_WR_DATA_WIDTH-1 : 0] wr_data , // input write data
input wire wr_en , // input write enable 1 active
output wire wr_vld ,
input wire wr_clk , // input write clock
input wire wr_rst , // input write reset
output wire [c_RD_DATA_WIDTH-1 : 0] rd_data , // output read data
input wire rd_en , // input read enable
output wire rd_vld ,
input wire rd_clk , // input read clock
input wire rd_rst // input read reset
);
//**************************************************************************************************************
//declare inner variables
wire [c_WR_DEPTH_WIDTH-1 : 0] wr_addr;
wire [c_RD_DEPTH_WIDTH-1 : 0] rd_addr;
wire wr_en_mux ;
wire rd_en_mux ;
reg rd_en_ff;
wire rd_vld_pre;
reg [2:0] shift_vld;
wire rd_en_pre;
reg rd_en_pre_ff1;
wire [c_RD_DATA_WIDTH-1 : 0] rd_data_org;
wire pop;
//**************************************************************************************************************
//instance ipml_flex_sdpram
ipml_sdpram_v1_6_hdmi_pcie_fifo
#(
.c_SIM_DEVICE (c_SIM_DEVICE),
.c_WR_ADDR_WIDTH (c_WR_DEPTH_WIDTH), //write address width
.c_WR_DATA_WIDTH (c_WR_DATA_WIDTH), //write data width
.c_RD_ADDR_WIDTH (c_RD_DEPTH_WIDTH), //read address width
.c_RD_DATA_WIDTH (c_RD_DATA_WIDTH), //read data width
.c_OUTPUT_REG (0), //output register
.c_RD_OCE_EN (0),
.c_WR_ADDR_STROBE_EN (0),
.c_RD_ADDR_STROBE_EN (0),
.c_WR_CLK_EN (1),
.c_RD_CLK_EN (1),
.c_RESET_TYPE (c_RESET_TYPE), //ASYNC_RESET_SYNC_RELEASE SYNC_RESET
.c_POWER_OPT (c_POWER_OPT), //0 :normal mode 1:low power mode
.c_RD_CLK_OR_POL_INV(0), //clk polarity invert for output register
.c_INIT_FILE ("NONE"), //false NONE or initial file name
.c_INIT_FORMAT ("BIN"), //bin or hex
.c_WR_BYTE_EN (0), //false
.c_BE_WIDTH (8)
)
U_ipml_sdpram
(
.wr_data (wr_data), //input write data [c_WR_DATA_WIDTH-1:0]
.wr_addr (wr_addr), //input write address [c_WR_DEPTH_WIDTH-1:0]
.wr_en (wr_en_mux), //input write enable
.wr_clk (wr_clk), //input write clock
.wr_clk_en (1'b1), //input write clock enable
.wr_rst (wr_rst), //input write reset
.wr_byte_en (-1), //"false"
.wr_addr_strobe (1'b0),
.rd_data (rd_data_org), //output read data [C_RD_DATA_WIDTH-1:0]
.rd_addr (rd_addr), //output read address [c_RD_DEPTH_WIDTH-1:0]
.rd_clk (rd_clk), //output read clock
.rd_clk_en (rd_en_mux), //output read clock enable
.rd_rst (rd_rst), //output read reset
.rd_oce (1'b0), //output read output register enable
.rd_addr_strobe (1'b0)
);
ipml_fifo_ctrl_v1_3
#(
.c_WR_DEPTH_WIDTH (c_WR_DEPTH_WIDTH), // write address width 8-- 20
.c_RD_DEPTH_WIDTH (c_RD_DEPTH_WIDTH), // read address width 8 -- 20
.c_FIFO_TYPE (c_FIFO_TYPE)
) U_ipml_fifo_ctrl(
.wclk (wr_clk), //write clock
.w_en (wr_en_mux), //write enable 1 active
.waddr (wr_addr), //write address
.wrst (wr_rst), //write reset
.wfull (wr_full), //write full flag 1 active
.almost_full (almost_full),
.wr_water_level(wr_water_level),
.rclk (rd_clk), //read clock
.r_en (rd_en_mux), //read enable 1 active
.raddr (rd_addr), //read address
.rrst (rd_rst), //read reset
.rempty (rd_empty), //read empty 1 active
.almost_empty (almost_empty),
.rd_water_level(rd_water_level)
);
assign wr_vld = ~wr_full;
assign rd_vld = rd_vld_pre;
assign wr_en_mux = wr_en & wr_vld;
assign rd_en_mux = rd_en_pre;
always@(posedge rd_clk or posedge rd_rst)
begin
if (rd_rst)
rd_en_ff <= 1'b0;
else
rd_en_ff <= ~rd_empty & rd_en;
end
assign rd_en_pre = (~shift_vld[2] | rd_en) & ~rd_empty;
always@(posedge rd_clk or posedge rd_rst)
begin
if (rd_rst)
rd_en_pre_ff1 <= 1'b0;
else
rd_en_pre_ff1 <= rd_en_pre;
end
assign pop = rd_vld & rd_en;
always@(posedge rd_clk or posedge rd_rst)
begin
if (rd_rst)
shift_vld <= 3'b001;
else
begin
case ({rd_en_pre, pop})
2'b10 : shift_vld <= {shift_vld[1:0], shift_vld[2]};
2'b01 : shift_vld <= {shift_vld[0], shift_vld[2:1]};
default: shift_vld <= 3'b000;
endcase
end
end
// Depth = 2
ipml_reg_fifo_v1_0
#(
.W ( c_RD_DATA_WIDTH )
)
ipml_reg_fifo
(
.clk ( rd_clk ),
.rst_n ( ~rd_rst ),
.data_in_valid ( rd_en_pre_ff1 ),
.data_in ( rd_data_org ),
.data_in_ready ( ),
.data_out_ready ( rd_en ),
.data_out ( rd_data ),
.data_out_valid ( rd_vld_pre )
);
endmodule |
module XOR2_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg A, B;
wire Y_gate, Y_data, Y_beh;
integer i;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg YEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
xor2_gate UUT_xor2_gate(
.a(A), .b(B),
.y(Y_gate)
);
// UNIT UNDER TEST (dataflow)
xor2_dataflow UUT_xor2_dataflow(
.a(A), .b(B),
.y(Y_data)
);
// UNIT UNDER TEST (behavioral)
xor2_behavioral UUT_xor2_behavioral(
.a(A), .b(B),
.y(Y_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("xor2_tb.vcd");
$dumpvars(0, XOR2_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("xor2_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, A, B, YEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | A | B | Y | Y | Y |");
$display(" --------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, B, Y_gate, Y_data, Y_beh);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, A, B, YEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY TEST VECTORS ON POS EDGE TICK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, B, Y_gate, Y_data, Y_beh);
// CHECK EACH VECTOR RESULT
if (Y_gate !== YEXPECTED) begin
$display("***ERROR (gate) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_data !== YEXPECTED) begin
$display("***ERROR (dataflow) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_beh !== YEXPECTED) begin
$display("***ERROR (behavioral) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module xor2_gate(
input a, b, // 2-Input
output y); // Output
// GATE PRIMITIVE
xor (y, a, b);
endmodule |
module xor2_dataflow(
input a, b, // 2-Input
output y); // Output
// CONTINUOUS ASSIGNMENT STATEMENT
assign y = a ^ b;
endmodule |
module xor2_behavioral(
input a, b, // 2-Input
output reg y); // Output
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(a or b) begin
y <= a ^ b;
end
endmodule |
module not1_gate(
input a, // 2-Input
output y); // Output
// GATE PRIMITIVE
not (y, a);
endmodule |
module not1_dataflow(
input a, // 2-Input
output y); // Output
// CONTINUOUS ASSIGNMENT STATEMENT
assign y = ~a;
endmodule |
module not1_behavioral(
input a, // 2-Input
output reg y); // Output
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(a) begin
y <= ~a;
end
endmodule |
module NOT1_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg A;
wire Y_gate, Y_data, Y_beh;
integer i;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg YEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
not1_gate UUT_not1_gate(
.a(A),
.y(Y_gate)
);
// UNIT UNDER TEST (dataflow)
not1_dataflow UUT_not1_dataflow(
.a(A),
.y(Y_data)
);
// UNIT UNDER TEST (behavioral)
not1_behavioral UUT_not1_behavioral(
.a(A),
.y(Y_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("not1_tb.vcd");
$dumpvars(0, NOT1_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("not1_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b", COMMENT, A, YEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | A | Y | Y | Y |");
$display(" ----------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, Y_gate, Y_data, Y_beh);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b", COMMENT, A, YEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY TEST VECTORS ON POS EDGE TICK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, Y_gate, Y_data, Y_beh);
// CHECK EACH VECTOR RESULT
if (Y_gate !== YEXPECTED) begin
$display("***ERROR (gate) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_data !== YEXPECTED) begin
$display("***ERROR (dataflow) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_beh !== YEXPECTED) begin
$display("***ERROR (behavioral) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module and2_gate(
input a, b, // 2-Input
output y); // Output
// GATE PRIMITIVE
and (y, a, b);
endmodule |
module nor2_gate(
input a, b, // 2-Input
output y); // Output
// GATE PRIMITIVE
nor (y, a, b);
endmodule |
module NOR2_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg A, B;
wire Y_gate, Y_data, Y_beh;
integer i;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg YEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
nor2_gate UUT_nor2_gate(
.a(A), .b(B),
.y(Y_gate)
);
// UNIT UNDER TEST (dataflow)
nor2_dataflow UUT_nor2_dataflow(
.a(A), .b(B),
.y(Y_data)
);
// UNIT UNDER TEST (behavioral)
nor2_behavioral UUT_nor2_behavioral(
.a(A), .b(B),
.y(Y_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("nor2_tb.vcd");
$dumpvars(0, NOR2_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("nor2_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, A, B, YEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | A | B | Y | Y | Y |");
$display(" --------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, B, Y_gate, Y_data, Y_beh);
end
// APPLY TEST VECTORS ON POS EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, A, B, YEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON NEG EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY TEST VECTORS ON POS EDGE TICK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, B, Y_gate, Y_data, Y_beh);
// CHECK EACH VECTOR RESULT
if (Y_gate !== YEXPECTED) begin
$display("***ERROR (gate) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_data !== YEXPECTED) begin
$display("***ERROR (dataflow) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_beh !== YEXPECTED) begin
$display("***ERROR (behavioral) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module or2_gate(
input a, b, // 2-Input
output y); // Output
// GATE PRIMITIVE
or (y, a, b);
endmodule |
module nand4_gate(
input a, b, c, d, // 4-Input
output y); // Output
// GATE PRIMITIVE
nand (y, a, b, c, d);
endmodule |
module nand4_dataflow(
input a, b, c, d, // 4-Input
output y); // Output
// CONTINUOUS ASSIGNMENT STATEMENT
assign y = ~(a & b & c & d);
endmodule |
module nand4_behavioral(
input a, b, c, d, // 4-Input
output reg y); // Output
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(a or b or c or d) begin
y <= ~(a & b & c & d);
end
endmodule |
module NAND4_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg A, B, C, D;
wire Y_gate, Y_data, Y_beh;
integer i;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg YEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
nand4_gate UUT_nand4_gate(
.a(A), .b(B), .c(C), .d(D),
.y(Y_gate)
);
// UNIT UNDER TEST (dataflow)
nand4_dataflow UUT_nand4_dataflow(
.a(A), .b(B), .c(C), .d(D),
.y(Y_data)
);
// UNIT UNDER TEST (behavioral)
nand4_behavioral UUT_nand4_behavioral(
.a(A), .b(B), .c(C), .d(D),
.y(Y_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("nand4_tb.vcd");
$dumpvars(0, NAND4_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("nand4_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b", COMMENT, A, B, C, D, YEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | A | B | C | D | Y | Y | Y |");
$display(" ----------------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, B, C, D, Y_gate, Y_data, Y_beh);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b", COMMENT, A, B, C, D, YEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY TEST VECTORS ON POS EDGE TICK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, B, C, D, Y_gate, Y_data, Y_beh);
// CHECK EACH VECTOR RESULT
if (Y_gate !== YEXPECTED) begin
$display("***ERROR (gate) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_data !== YEXPECTED) begin
$display("***ERROR (dataflow) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
if (Y_beh !== YEXPECTED) begin
$display("***ERROR (behavioral) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module SR_LATCH_TB ();
// INPUT PROBES
reg S, R;
// OUTPUT PROBES
wire Q_gate, QBAR_gate;
wire Q_data, QBAR_data;
wire Q_beh, QBAR_beh;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
sr_latch_gate UUT_sr_latch_gate(
.s(S), .r(R),
.q(Q_gate), .qbar(QBAR_gate)
);
// UNIT UNDER TEST (dataflow)
sr_latch_dataflow UUT_sr_latch_dataflow(
.s(S), .r(R),
.q(Q_data), .qbar(QBAR_data)
);
// UNIT UNDER TEST (behavioral)
sr_latch_behavioral UUT_sr_latch_behavioral(
.s(S), .r(R),
.q(Q_beh), .qbar(QBAR_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("sr_latch_tb.vcd");
$dumpvars(0, SR_LATCH_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("sr_latch_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, S, R, QEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | S | R | Q | Q | Q |");
$display(" --------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, S, R, Q_gate, Q_data, Q_beh);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, S, R, QEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, S, R, Q_gate, Q_data, Q_beh);
// CHECK EACH VECTOR RESULT
if (Q_gate !== QEXPECTED) begin
$display("***ERROR (gate) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
if (Q_data !== QEXPECTED) begin
$display("***ERROR (dataflow) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
if (Q_beh !== QEXPECTED) begin
$display("***ERROR (behavioral) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module sr_latch_gate (
input s, // Inputs
input r, //
output q, // Output
output qbar); //
// NAND1
nand (q, s, qbar);
// NAND2
nand (qbar, r, q);
endmodule |
module sr_latch_dataflow (
input s, // Inputs
input r, //
output q, // Output
output qbar); //
// NAND1
assign q = ~(s & qbar);
// NAND2
assign qbar = ~(r & q);
endmodule |
module sr_latch_behavioral (
input s, // Inputs
input r, //
output reg q, // Output
output qbar); //
always @(*) begin
case({s,r})
2'b0_0 : q <= 1'bx;
2'b0_1 : q <= 1'b1;
2'b1_0 : q <= 1'b0;
2'b1_1 : q <= q;
endcase
end
endmodule |
module D_FLIP_FLOP_POS_EDGE_SYNC_EN_TB ();
// INPUT PROBES
reg EN;
reg D;
// OUTPUT PROBES
wire Q_beh, QBAR_beh;
// FOR TESTING
reg CLK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
d_flip_flop_pos_edge_sync_en_behavioral UUT_d_flip_flop_pos_edge_sync_en_behavioral(
.clk(CLK),
.en(EN),
.d(D),
.q(Q_beh), .qbar(QBAR_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("d_flip_flop_pos_edge_sync_en_tb.vcd");
$dumpvars(0, D_FLIP_FLOP_POS_EDGE_SYNC_EN_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("d_flip_flop_pos_edge_sync_en_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, EN, D, QEXPECTED);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | EN | D | Q |");
$display(" ---------------------------");
// $monitor("%4d %10s | %8d | %d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, EN, D, Q_beh);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, EN, D, QEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, EN, D, Q_beh);
// CHECK EACH VECTOR RESULT
if (Q_beh !== QEXPECTED) begin
$display("***ERROR (behavioral) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module d_flip_flop_pos_edge_sync_en_behavioral (
input clk, // Clock
input en, // Enable
input d, // Data
output reg q, // Output
output qbar); //
assign qbar = ~q;
// D FLIP-FLOP WITH SYNC ENABLE
always @ (posedge clk) begin
if (en) begin
q <= d;
end else begin
q <= q;
end
end
endmodule |
module jk_flip_flop_gate (
input clk, // Clock
input j, // Inputs
input k, //
output q, // Output
output qbar); //
// INTERNAL WIRES
wire s, r;
// NAND3
nand (s, j, clk, qbar);
// NAND4
nand (r, k, clk, q);
// SR- LATCH -------------------------------------
// NAND1
nand (q, s, qbar);
// NAND2
nand (qbar, r, q);
endmodule |
module jk_flip_flop_dataflow (
input clk, // Clock
input j, // Inputs
input k, //
output q, // Output
output qbar); //
// INTERNAL WIRES
wire s, r;
// NAND3
assign s = ~(j & clk & qbar);
// NAND4
assign r = ~(k & clk & q);
// SR- LATCH -------------------------------------
// NAND1
assign q = ~(s & qbar);
// NAND2
assign qbar = ~(r & q);
endmodule |
module jk_flip_flop_behavioral (
input clk, // Clock
input j, // Inputs
input k, //
output reg q, // Output
output qbar); //
// INTERNAL WIRES
assign qbar = ~q;
always @(posedge clk) begin
case({j,k})
2'b0_0 : q <= q;
2'b0_1 : q <= 1'b0;
2'b1_0 : q <= 1'b1;
2'b1_1 : q <= ~q;
endcase
end
endmodule |
module JK_FLIP_FLOP_POS_EDGE_SYNC_CLEAR_TB ();
// INPUT PROBES
reg CLRBAR;
reg J, K;
// OUTPUT PROBES
wire Q_beh, QBAR_beh;
// FOR TESTING
reg CLK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
jk_flip_flop_pos_edge_sync_clear_behavioral UUT_jk_flip_flop_pos_edge_sync_clear_behavioral(
.clk(CLK),
.clrbar(CLRBAR),
.j(J), .k(K),
.q(Q_beh), .qbar(QBAR_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("jk_flip_flop_pos_edge_sync_clear_tb.vcd");
$dumpvars(0, JK_FLIP_FLOP_POS_EDGE_SYNC_CLEAR_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("jk_flip_flop_pos_edge_sync_clear_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b", COMMENT, CLRBAR, J, K, QEXPECTED);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | CLRBAR | J | K | Q |");
$display(" -----------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, CLRBAR, J, K, Q_beh);
// INIT - PUT OUTPUT IN KNOWN STATE
// TO AVOID THE RACE CONDITION
// NOTE: The beh model will still have X
//#5
//force Q_beh = 1'b0;
//force QBAR_beh = 1'b1;
//#26
//release Q_beh;
//release QBAR_beh;
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b", COMMENT, CLRBAR, J, K, QEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT FOR OUTPUT TO SETTLE
#12;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, CLRBAR, J, K, Q_beh);
// CHECK EACH VECTOR RESULT
if (Q_beh !== QEXPECTED) begin
$display("***ERROR (behavioral) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module jk_flip_flop_pos_edge_sync_clear_behavioral (
input clk, // Clock
input clrbar, // Clear
input j, // Inputs
input k, //
output reg q, // Output
output qbar //
);
parameter NOCHANGE = 2'b0_0,
RESET = 2'b0_1,
SET = 2'b1_0,
TOGGLE = 2'b1_1;
assign qbar = ~q;
// JK FLIP-FLOP WITH SYNC CLEAR
always @ (posedge clk) begin
if (~clrbar) begin
q <= 1'b0;
end else begin
case({j,k})
NOCHANGE : q <= q;
RESET : q <= 1'b0;
SET : q <= 1'b1;
TOGGLE : q <= ~q;
endcase
end
end
endmodule |
module JK_FLIP_FLOP_PULSE_TRIGGERED_TB ();
// INPUT PROBES
reg J, K;
// OUTPUT PROBES
wire Q_gate, QBAR_gate;
wire Q_data, QBAR_data;
wire Q_beh, QBAR_beh;
// FOR TESTING
reg CLK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
jk_flip_flop_pulse_triggered_gate UUT_jk_flip_flop_pulse_triggered_gate(
.clk(CLK),
.j(J), .k(K),
.q(Q_gate), .qbar(QBAR_gate)
);
// UNIT UNDER TEST (dataflow)
jk_flip_flop_pulse_triggered_dataflow UUT_jk_flip_flop_pulse_triggered_dataflow(
.clk(CLK),
.j(J), .k(K),
.q(Q_data), .qbar(QBAR_data)
);
// UNIT UNDER TEST (behavioral)
jk_flip_flop_pulse_triggered_behavioral UUT_jk_flip_flop_pulse_triggered_behavioral(
.clk(CLK),
.j(J), .k(K),
.q(Q_beh), .qbar(QBAR_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("jk_flip_flop_pulse_triggered_tb.vcd");
$dumpvars(0, JK_FLIP_FLOP_PULSE_TRIGGERED_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("jk_flip_flop_pulse_triggered_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, J, K, QEXPECTED);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | J | K | Q | Q | Q |");
$display(" --------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, J, K, Q_gate, Q_data, Q_beh);
// INIT - PUT OUTPUT IN KNOWN STATE
// TO AVOID THE RACE CONDITION
// NOTE: The beh model will still have X
#5
force Q_gate = 1'b0;
force QBAR_gate = 1'b1;
force Q_data = 1'b0;
force QBAR_data = 1'b1;
force Q_beh = 1'b0;
force QBAR_beh = 1'b1;
#26
release Q_gate;
release QBAR_gate;
release Q_data;
release QBAR_data;
release Q_beh;
release QBAR_beh;
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, J, K, QEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT FOR OUTPUT TO SETTLE
#12;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, J, K, Q_gate, Q_data, Q_beh);
// CHECK EACH VECTOR RESULT
if (Q_gate !== QEXPECTED) begin
$display("***ERROR (gate) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
if (Q_data !== QEXPECTED) begin
$display("***ERROR (dataflow) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
if (Q_beh !== QEXPECTED) begin
$display("***ERROR (behavioral) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module jk_flip_flop_pulse_triggered_gate (
input clk, // Clock
input j, // Inputs
input k, //
output q, // Output
output qbar); //
// INTERNAL WIRES
wire clk2;
wire s1, r1;
wire s2, r2;
wire q1, q1bar;
// JK FLIP FLOP 1 -----------------------------------
// NAND7
nand (s1, j, clk, qbar);
// NAND8
nand (r1, k, clk, q);
// SR- LATCH -------------------------------------
// NAND6
nand (q1, s1, q1bar);
// NAND6
nand (q1bar, r1, q1);
// JK FLIP FLOP 2 -----------------------------------
// NAND3
nand (s2, q1, clk2);
// NAND4
nand (r2, q1bar, clk2);
// SR- LATCH -------------------------------------
// NAND1
nand (q, s2, qbar);
// NAND2
nand (qbar, r2, q);
// CLOCK -------------------------------------------
not (clk2, clk);
endmodule |
module jk_flip_flop_pulse_triggered_dataflow (
input clk, // Clock
input j, // Inputs
input k, //
output q, // Output
output qbar); //
// JK FLIP FLOP 1 -----------------------------------
// NAND7
assign s1 = ~(j & clk & qbar);
// NAND8
assign r1 = ~(k & clk & q);
// SR- LATCH -------------------------------------
// NAND6
assign q1 = ~(s1 & q1bar);
// NAND6
assign q1bar = ~(r1 & q1);
// JK FLIP FLOP 2 -----------------------------------
// NAND3
assign s2 = ~(q1 & clk2);
// NAND4
assign r2 = ~(q1bar & clk2);
// SR- LATCH -------------------------------------
// NAND1
assign q = ~(s2 & qbar);
// NAND2
assign qbar = ~(r2 & q);
// CLOCK -------------------------------------------
assign clk2 = ~(clk);
endmodule |
module sr_flip_flop_gate (
input clk, // Clock
input s, // Inputs
input r, //
output q, // Output
output qbar); //
// INTERNAL WIRES
wire s1, r1;
// NAND3
nand (s1, s, clk);
// NAND4
nand (r1, r, clk);
// SR- LATCH -------------------------------------
// NAND1
nand (q, s1, qbar);
// NAND2
nand (qbar, r1, q);
endmodule |
module sr_flip_flop_dataflow (
input clk, // Clock
input s, // Inputs
input r, //
output q, // Output
output qbar); //
// INTERNAL WIRES
wire s1, r1;
// NAND3
assign s1 = ~(s & clk);
// NAND4
assign r1 = ~(r & clk);
// SR- LATCH -------------------------------------
// NAND1
assign q = ~(s1 & qbar);
// NAND2
assign qbar = ~(r1 & q);
endmodule |
module sr_flip_flop_behavioral (
input clk, // Clock
input s, // Inputs
input r, //
output reg q, // Output
output qbar); //
// INTERNAL WIRES
assign qbar = ~q;
always @(posedge clk) begin
case({s,r})
2'b0_0 : q <= q;
2'b0_1 : q <= 1'b0;
2'b1_0 : q <= 1'b1;
2'b1_1 : q <= 1'bx;
endcase
end
endmodule |
module d_flip_flop_gate (
input clk, // Clock
input d, // Inputs
output q, // Output
output qbar); //
// INTERNAL WIRES
wire s, r;
wire s1, r1;
assign s = d;
// NOT1
not (r, s);
// SR FLIP-FLOP ---------------------------------
// NAND3
nand (s1, s, clk);
// NAND4
nand (r1, r, clk);
// SR-LATCH -------------------------------------
// NAND1
nand (q, s1, qbar);
// NAND2
nand (qbar, r1, q);
endmodule |
module d_flip_flop_dataflow (
input clk, // Clock
input d, // Inputs
output q, // Output
output qbar); //
assign s = d;
assign r = ~d;
// SR FLIP-FLOP ---------------------------------
// INTERNAL WIRES
wire s1, r1;
// NAND3
assign s1 = ~(s & clk);
// NAND4
assign r1 = ~(r & clk);
// SR- LATCH -------------------------------------
// NAND1
assign q = ~(s1 & qbar);
// NAND2
assign qbar = ~(r1 & q);
endmodule |
module d_flip_flop_behavioral (
input clk, // Clock
input d, // Inputs
output reg q, // Output
output qbar); //
parameter DATA0 = 1'b0,
DATA1 = 1'b1;
// INTERNAL WIRES
assign qbar = ~q;
always @(posedge clk) begin
case({d})
DATA0 : q <= 1'b0;
DATA1 : q <= 1'b1;
endcase
end
endmodule |
module T_FLIP_FLOP_TB ();
// INPUT PROBES
reg T;
// OUTPUT PROBES
wire Q_gate, QBAR_gate;
wire Q_data, QBAR_data;
wire Q_beh, QBAR_beh;
// FOR TESTING
reg CLK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
t_flip_flop_gate UUT_t_flip_flop_gate(
.clk(CLK),
.t(T),
.q(Q_gate), .qbar(QBAR_gate)
);
// UNIT UNDER TEST (dataflow)
// t_flip_flop_dataflow UUT_t_flip_flop_dataflow(
// .clk(CLK),
// .t(T),
// .q(Q_data), .qbar(QBAR_data)
// );
// UNIT UNDER TEST (behavioral)
t_flip_flop_behavioral UUT_t_flip_flop_behavioral(
.clk(CLK),
.t(T),
.q(Q_beh), .qbar(QBAR_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("t_flip_flop_tb.vcd");
$dumpvars(0, T_FLIP_FLOP_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("t_flip_flop_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, T, QEXPECTED);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | T | Q | Q | Q |");
$display(" ----------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, T, Q_gate, Q_data, Q_beh);
// INIT - PUT OUTPUT IN KNOWN STATE
// TO AVOID THE RACE CONDITION
// NOTE: The beh model will still have X
#1
force Q_gate = 1'b0;
force QBAR_gate = 1'b1;
// force Q_data = 1'b0;
// force QBAR_data = 1'b1;
force Q_beh = 1'b0;
force QBAR_beh = 1'b1;
#10
release Q_gate;
release QBAR_gate;
// release Q_data;
// release QBAR_data;
release Q_beh;
release QBAR_beh;
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b", COMMENT, T, QEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, T, Q_gate, Q_data, Q_beh);
// CHECK EACH VECTOR RESULT
if (Q_gate !== QEXPECTED) begin
$display("***ERROR (gate) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
// if (Q_data !== QEXPECTED) begin
// $display("***ERROR (dataflow) - Expected Q = %b", QEXPECTED);
// ERRORS = ERRORS + 1;
// end
if (Q_beh !== QEXPECTED) begin
$display("***ERROR (behavioral) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module t_flip_flop_gate (
input clk, // Clock
input t, // Inputs
output q, // Output
output qbar); //
// INTERNAL WIRES
wire j, k;
wire s, r;
assign j = t;
assign k = t;
// JK FLIP-FLOP -----------------------------------
// NAND3
nand (s, j, clk, qbar);
// NAND4
nand (r, k, clk, q);
// SR- LATCH -------------------------------------
// NAND1
nand (q, s, qbar);
// NAND2
nand (qbar, r, q);
endmodule |
module t_flip_flop_dataflow (
input clk, // Clock
input t, // Inputs
output q, // Output
output qbar); //
// INTERNAL WIRES
wire s, r;
// JK FLIP-FLOP -----------------------------------
// NAND3
assign s = ~(t & clk & qbar);
// NAND4
assign r = ~(t & clk & q);
// SR- LATCH -------------------------------------
// NAND1
assign q = ~(s & qbar);
// NAND2
assign qbar = ~(r & q);
endmodule |
module t_flip_flop_behavioral (
input clk, // Clock
input t, // Inputs
output reg q, // Output
output qbar); //
parameter HOLD = 1'b0,
TOGGLE = 1'b1;
// INTERNAL WIRES
assign qbar = ~q;
always @(posedge clk) begin
case({t})
HOLD : q <= q;
TOGGLE : q <= ~q;
endcase
end
endmodule |
module D_FLIP_FLOP_PULSE_TRIGGERED_TB ();
// INPUT PROBES
reg D;
// OUTPUT PROBES
wire Q_gate, QBAR_gate;
wire Q_data, QBAR_data;
wire Q_beh, QBAR_beh;
// FOR TESTING
reg CLK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
d_flip_flop_pulse_triggered_gate UUT_d_flip_flop_pulse_triggered_gate(
.clk(CLK),
.d(D),
.q(Q_gate), .qbar(QBAR_gate)
);
// UNIT UNDER TEST (dataflow)
d_flip_flop_pulse_triggered_dataflow UUT_d_flip_flop_pulse_triggered_dataflow(
.clk(CLK),
.d(D),
.q(Q_data), .qbar(QBAR_data)
);
// UNIT UNDER TEST (behavioral)
d_flip_flop_pulse_triggered_behavioral UUT_d_flip_flop_pulse_triggered_behavioral(
.clk(CLK),
.d(D),
.q(Q_beh), .qbar(QBAR_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("d_flip_flop_pulse_triggered_tb.vcd");
$dumpvars(0, D_FLIP_FLOP_PULSE_TRIGGERED_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("d_flip_flop_pulse_triggered_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b", COMMENT, D, QEXPECTED);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | S | Q | Q | Q |");
$display(" ----------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, D, Q_gate, Q_data, Q_beh);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b", COMMENT, D, QEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, D, Q_gate, Q_data, Q_beh);
// CHECK EACH VECTOR RESULT
if (Q_gate !== QEXPECTED) begin
$display("***ERROR (gate) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
if (Q_data !== QEXPECTED) begin
$display("***ERROR (dataflow) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
if (Q_beh !== QEXPECTED) begin
$display("***ERROR (behavioral) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module d_flip_flop_pulse_triggered_gate (
input clk, // Clock
input d, // Inputs
output q, // Output
output qbar); //
// INTERNAL WIRES
wire clk1;
//NOT 3
not (clk1, clk);
// D-FLIP FLOP (BOSS)
// INTERNAL WIRES
wire s1, r1;
wire s2, r2;
assign s1 = d;
// NOT2
not (r1, s1);
// SR FLIP-FLOP ---------------------------------
// NAND7
nand (s2, s1, clk1);
// NAND8
nand (r2, r1, clk1);
// SR-LATCH -------------------------------------
// NAND5
nand (q1, s2, q1bar);
// NAND6
nand (q1bar, r2, q1);
// D-FLIP FLOP (WORKER)
// INTERNAL WIRES
wire s3, r3;
wire s4, r4;
assign s3 = q1;
// NOT1
not (r3, s3);
// SR FLIP-FLOP ---------------------------------
// NAND3
nand (s4, s3, clk1);
// NAND4
nand (r4, r3, clk1);
// SR-LATCH -------------------------------------
// NAND1
nand (q, s4, qbar);
// NAND2
nand (qbar, r4, q);
endmodule |
module d_flip_flop_pulse_triggered_dataflow (
input clk, // Clock
input d, // Inputs
output q, // Output
output qbar); //
// INTERNAL WIRES
wire clk1;
// NOT3
assign clk1 = ~clk;
// D-FLIP FLOP (BOSS)
// INTERNAL WIRES
wire s1, r1;
wire s2, r2;
assign s1 = d;
// NOT2
assign r1 = ~s1;
// SR FLIP-FLOP ---------------------------------
// NAND7
assign s2 = ~(s1 & clk1);
// NAND8
assign r2 = ~(r1 & clk1);
// SR-LATCH -------------------------------------
// NAND5
assign q1 = ~( s2 & q1bar);
// NAND6
assign q1bar = ~(r2 & q1);
// D-FLIP FLOP (WORKER)
// INTERNAL WIRES
wire s3, r3;
wire s4, r4;
assign s3 = q1;
// NOT1
assign r3 = ~s3;
// SR FLIP-FLOP ---------------------------------
// NAND3
assign s4 = ~(s3 & clk1);
// NAND4
assign r4 = ~(r3 & clk1);
// SR-LATCH -------------------------------------
// NAND1
assign q = ~(s4 & qbar);
// NAND2
assign qbar = ~(r4 & q);
endmodule |
module jeff_74x151_behavioral(
input d0, // DATA IN
input d1, //
input d2, //
input d3, //
input d4, //
input d5, //
input d6, //
input d7, //
input a, // SELECT
input b, //
input c, //
input en, // ENABLE
output reg y, // DATA OUT
output w // INVERTED OUTPUT
);
assign w = ~y;
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ ( * ) begin
if (en) begin
case({c,b,a})
3'b000 : y <= d0;
3'b001 : y <= d1;
3'b010 : y <= d2;
3'b011 : y <= d3;
3'b100 : y <= d4;
3'b101 : y <= d5;
3'b110 : y <= d6;
3'b111 : y <= d7;
endcase
end else begin
y <= 1'b1;
end
end
endmodule |
module JEFF_74x151_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [7:0] D;
reg [2:0] SEL;
reg EN;
wire Y;
wire W;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg YEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
jeff_74x151_behavioral UUT_jeff_74x151_behavioral(
.d0(D[0]), .d1(D[1]), .d2(D[2]), .d3(D[3]), .d4(D[4]), .d5(D[5]), .d6(D[6]), .d7(D[7]),
.a(SEL[0]), .b(SEL[1]), .c(SEL[2]),
.en(EN),
.y(Y), .w(W)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("jeff_74x151_tb.vcd");
$dumpvars(0, JEFF_74x151_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("jeff_74x151_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b", COMMENT, EN, SEL, D, YEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | EN | SEL | D | Y |");
$display(" --------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, EN, SEL, D, Y);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b", COMMENT, EN, SEL, D, YEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE TICK
$display("%4d %10s | %8d | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, EN, SEL, D, Y);
// CHECK EACH VECTOR RESULT
if (Y !== YEXPECTED) begin
$display("***ERROR (behavioral) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module DEMUX_4x1_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg Y;
reg [1:0] SEL;
wire A, B, C, D;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg AEXP, BEXP, CEXP, DEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
demux_1x4_behavioral UUT_demux_1x4_behavioral(
.y(Y),
.sel(SEL),
.a(A), .b(B), .c(C), .d(D)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("demux_1x4_tb.vcd");
$dumpvars(0, DEMUX_4x1_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("demux_1x4_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b", COMMENT, SEL, Y, AEXP, BEXP, CEXP, DEXP);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | SEL | Y | A | B | C | D |");
$display(" --------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, SEL, Y, A, B, C, D);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b", COMMENT, SEL, Y, AEXP, BEXP, CEXP, DEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE TICK
$display("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, SEL, Y, A, B, C, D);
// CHECK EACH VECTOR RESULT
if ((A !== AEXP) | (B !== BEXP) | (C !== CEXP) | (D !== DEXP)) begin
$display("***ERROR (behavioral) - Expected A=%b, B=%b, C=%b, D=%b", AEXP, BEXP, CEXP, DEXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module demux_1x4_behavioral(
input y, // 1 Input
input [1:0] sel, // Select
output reg a, b, c, d); // 4 Outputs
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ ( * ) begin
case(sel)
2'b00 : begin
a <= y; b <= 0; c <= 0; d <= 0;
end
2'b01 : begin
a <= 0; b <= y; c <= 0; d <= 0;
end
2'b10 : begin
a <= 0; b <= 0; c <= y; d <= 0;
end
2'b11 : begin
a <= 0; b <= 0; c <= 0; d <= y;
end
endcase
end
endmodule |
module JEFF_74x157_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [3:0] A, B;
reg S;
reg EN;
wire [3:0] Y;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg [3:0] YEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
jeff_74x157_behavioral UUT_jeff_74x157_behavioral(
.a(A), .b(B),
.s(S),
.en(EN),
.y(Y)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("jeff_74x157_tb.vcd");
$dumpvars(0, JEFF_74x157_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("jeff_74x157_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b", COMMENT, EN, S, A, B, YEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | EN | S | A | B | Y |");
$display(" ------------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, EN, S, A, B, Y);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b", COMMENT, EN, S, A, B, YEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE TICK
$display("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, EN, S, A, B, Y);
// CHECK EACH VECTOR RESULT
if (Y !== YEXPECTED) begin
$display("***ERROR (behavioral) - Expected Y = %b", YEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module jeff_74x157_behavioral(
input [3:0] a, // INPUT DATA A
input [3:0] b, // INPUT DATA B
input s, // SELECT
input en, // ENABLE
output reg [3:0] y // OUTPUT DATA
);
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ ( * ) begin
if (~en) begin
y <= 4'h0;
end else begin
case(s)
1'b0 : y <= a;
1'b1 : y <= b;
endcase
end
end
endmodule |
module MUX_TO_DEMUX_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg A1, B1, C1, D1;
reg [1:0] SEL1;
reg [1:0] SEL2;
wire A2, B2, C2, D2;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg A2EXP, B2EXP, C2EXP, D2EXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
mux_to_demux_structural UUT_mux_to_demux_structural(
.a1(A1), .b1(B1), .c1(C1), .d1(D1),
.sel1(SEL1),
.sel2(SEL2),
.a2(A2), .b2(B2), .c2(C2), .d2(D2)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("mux_to_demux_tb.vcd");
$dumpvars(0, MUX_TO_DEMUX_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("mux_to_demux_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b %b %b %b", COMMENT, SEL1, SEL2, A1, B1, C1, D1, A2EXP, B2EXP, C2EXP, D2EXP);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | SEL1 | SEL2 | A1 | B1 | C1 | D1 | A2 | B2 | C2 | D2 |");
$display(" ------------------------------------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, SEL1, SEL2, A1, B1, C1, D1, A2, B2, C2, D2);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b %b %b %b", COMMENT, SEL1, SEL2, A1, B1, C1, D1, A2EXP, B2EXP, C2EXP, D2EXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE TICK
$display("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, SEL1, SEL2, A1, B1, C1, D1, A2, B2, C2, D2);
// CHECK EACH VECTOR RESULT
if ((A2 !== A2EXP) | (B2 !== B2EXP) | (D2 !== D2EXP) | (D2 != D2EXP)) begin
$display("***ERROR (behavioral) - Expected A=%b, B=%b, C=%b, D=%b", A2EXP, B2EXP, C2EXP, D2EXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module mux_to_demux_structural(
input a1, b1, c1, d1, // 4 Inputs
input [1:0] sel1, // Select
input [1:0] sel2, // Select
output a2, b2, c2, d2); // 4 Outputs
wire y;
// 4x1 MULTIPLEXER
mux_4x1_behavioral MUX_4X1 (
.a(a1), .b(b1), .c(c1), .d(d1),
.sel(sel1),
.y(y)
);
// 1x4 DEMULTIPLEXER
demux_1x4_behavioral DEMUX_1X4 (
.y(y),
.sel(sel2),
.a(a2), .b(b2), .c(c2), .d(d2)
);
endmodule |
module mux_4x1_behavioral(
input a, b, c, d, // 4 Inputs
input [1:0] sel, // Select
output reg y); // 1 Output
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ ( * ) begin
case(sel)
2'b00 : y <= a;
2'b01 : y <= b;
2'b10 : y <= c;
2'b11 : y <= d;
endcase
end
endmodule |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.