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module local_bus(
clk,
reset,
cs_n,//local bus;
rd_wr,//only write,no read;
ack_n,
data,
data_out,
ale,
port0_select,
port1_select,
port2_select,
port3_select,
port1_check,
port2_check
);
input clk;
input reset;
input cs_n;
input rd_wr;
output ack_n;
input [31:0]data;//;
output [31:0]data_out;
input ale;
output port0_select;
output port1_select;
output port2_select;
output port3_select;
output [31:0]port1_check;
output [31:0]port2_check;
reg [31:0]data_out;
wire [31:0]data;
reg ack_n;
reg [27:0]local_bus_address_reg;
///////////////////UM register//////////////////////
reg [31:0]test0;
reg [31:0]test1;
reg [31:0]test2;
reg [31:0]test3;
reg [31:0]test4;
reg [31:0]test5;
reg port0_select;
reg port1_select;
reg port2_select;
reg port3_select;
reg [31:0]port1_check;
reg [31:0]port2_check;
///////////////////end of UM register//////////////////////
reg [2:0]current_state;
parameter idle=3'b0,
wait_ale0=3'b001,//wait the ale change to 0;
juedge_um=3'b010,
um_register=3'b011,
wait_wrreg_cs=3'b100,
wait_rdreg_cs=3'b101,
cancel_ack=3'b0110,
cancel_command=3'b111;
always@(posedge clk or negedge reset)
if(!reset)
begin
ack_n<=1'b1;
test0<=32'd20110704;
test1<=32'd20110704;
test2<=32'd20110704;
test3<=32'd20110704;
test4<=32'd20110704;
test5<=32'd20110704;
port0_select<=1'b0;
port1_select<=1'b0;
port2_select<=1'b0;
port3_select<=1'b0;
port1_check <=32'h4;//????64
port2_check <=32'h4;//????64
current_state <=idle;
end
else
begin
case(current_state)
idle:
begin
if(ale==1'b1)//address locked signal is coming;
begin
current_state<=wait_ale0;
end
else
current_state<=idle;
end//end idle;
wait_ale0://wait ale==1'b0;
begin
if(ale==1'b0)
begin
case(data[31:28])////
4'b0001://um RAM and registers;
begin
local_bus_address_reg<=data[27:0];//data[27:26]:00-register;01-RAM;////
current_state<=juedge_um;
end
default:
begin
current_state<=idle;
end
endcase//end case;
end
else
begin
//data_in_reg<=data_in;/////
current_state<=wait_ale0;
end
end//end wait ale==1'b0;
juedge_um:
begin
case(local_bus_address_reg[27:26])
2'b00:
begin
current_state<=um_register;//UM register;
end
default:
begin
current_state<=idle;
end
endcase
end//juedge_um;
um_register:
begin
if(rd_wr==1'b0)//write;
begin
current_state<=wait_wrreg_cs;
end
else
begin
current_state<=wait_rdreg_cs;
end
end//um_register;
wait_wrreg_cs:
begin
if(cs_n==1'b0)//ok
begin
case(local_bus_address_reg[7:0])
8'h00:
begin
test0<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h01:
begin
test1<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h02:
begin
test2<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h03:
begin
test3<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h04:
begin
test4<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h05:
begin
test5<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h06:
begin
port0_select<=data[0];
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h07:
begin
port1_select<=data[0];
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h08:
begin
port2_select<=data[0];
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h09:
begin
port3_select<=data[0];
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h0a:
begin
port1_check<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h0b:
begin
port2_check<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
default:
current_state<=idle;
endcase
end
else
begin
current_state<=wait_wrreg_cs;
end
end//wait_wr_cs;
wait_rdreg_cs:
begin
if(cs_n==1'b0)//ok
begin
case(local_bus_address_reg[7:0])
8'h00:
begin
data_out<=test0;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h01:
begin
data_out<=test1;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h02:
begin
data_out<=test2;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h03:
begin
data_out<=test3;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h04:
begin
data_out<=test4;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h05:
begin
data_out<=test5;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h06:
begin
data_out<=port0_select;
data_out[31:1]<=31'b0;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h07:
begin
data_out[0]<=port1_select;
data_out[31:1]<=31'b0;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h08:
begin
data_out<=port2_select;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h09:
begin
data_out<=port3_select;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h0a:
begin
data_out<=port1_check;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h0b:
begin
data_out<=port2_check;
ack_n<=1'b1;
current_state<=cancel_ack;
end
default:
current_state<=idle;
endcase
end
else
begin
current_state<=wait_rdreg_cs;
end
end//wait_rd_cs;
cancel_ack:
begin
local_bus_address_reg<=28'b0;
ack_n<=1'b0;
current_state<=cancel_command;
end//cancel_ack;
cancel_command:
begin
if(cs_n==1'b1)
begin
ack_n<=1'b1;
current_state<=idle;
end
else
begin
current_state<=cancel_command;
end
end//cancel_command;
default:
begin
current_state<=idle;
end
endcase
end
endmodule |
module manage_tx(
clk,
reset_n,
// ack_fifo_wrclk,
ack_pkt, //[35:34]01:±íʾÊý¾ÝµÚÒ»ÅÄ 11:±íʾÊý¾ÝÖмäÅÄ 10:±íʾÊý¾Ý×îºóÒ»ÅÄ [33:32]:ÓÐЧ×Ö½ÚÊý [31:0]:±¨ÎÄ
ack_wr,
ack_afull,
//FPGA·µ»Ø¸ø¹ÜÀí½Ó¿ÚµÄ±¨ÎÄÓÐЧ±ê־λ;Õâ¸öFIFO·Ç¿Õ±íʾ±¨ÎÄFIFOÖÐÖÁÉÙÓÐÒ»¸öÍêÕûµÄ±¨ÎÄÁË
ack_valid_wr,
ack_valid_afull,
pass_pkt,
pass_pkt_wrreq,
pass_pkt_usedw,
pass_valid_wrreq,
pass_valid,
tx_pkt,
tx_pkt_wrreq,
tx_pkt_valid,
tx_pkt_valid_wrreq,
tx_pkt_usedw
);
input clk;
input reset_n;
// ack_fifo_wrclk,
input [35:0]ack_pkt; //[35:34]01:±íʾÊý¾ÝµÚÒ»ÅÄ 11:±íʾÊý¾ÝÖмäÅÄ 10:±íʾÊý¾Ý×îºóÒ»ÅÄ [33:32]:ÓÐЧ×Ö½ÚÊý [31:0]:±¨ÎÄ
input ack_wr;
output ack_afull;
//FPGA·µ»Ø¸ø¹ÜÀí½Ó¿ÚµÄ±¨ÎÄÓÐЧ±ê־λ;Õâ¸öFIFO·Ç¿Õ±íʾ±¨ÎÄFIFOÖÐÖÁÉÙÓÐÒ»¸öÍêÕûµÄ±¨ÎÄÁË
input ack_valid_wr;
output ack_valid_afull;
input[138:0]pass_pkt;
input pass_pkt_wrreq;
output [7:0]pass_pkt_usedw;
input pass_valid_wrreq;
input pass_valid;
output [138:0]tx_pkt;
output tx_pkt_wrreq;
output tx_pkt_valid;
output tx_pkt_valid_wrreq;
input [7:0] tx_pkt_usedw;
///////////////////////////////////
reg [138:0]tx_pkt;
reg tx_pkt_wrreq;
reg tx_pkt_valid;
reg tx_pkt_valid_wrreq;
reg [3:0]state;
parameter idle_s = 4'h0,
ack_head0_s = 4'h1,
ack_head1_s = 4'h2,
ack_head2_s = 4'h3,
ack_head3_s = 4'h4,
ack_mid0_s = 4'h5,
ack_mid1_s = 4'h6,
ack_mid2_s = 4'h7,
ack_mid3_s = 4'h8,
pass_data_s = 4'h9,
drop_s = 4'ha,
wait_s = 4'hb;
always@(posedge clk or negedge reset_n)
begin
if(~reset_n)begin
tx_pkt_wrreq <= 1'b0;
tx_pkt_valid_wrreq <= 1'b0;
pass_pkt_rdreq <= 1'b0;
pass_valid_rdreq <= 1'b0;
ack_rdreq <= 1'b0;
ack_valid_rdreq <= 1'b0;
state <= idle_s;
end
else begin
case(state)
idle_s:begin
tx_pkt_wrreq <= 1'b0;
tx_pkt_valid_wrreq <= 1'b0;
pass_pkt_rdreq <= 1'b0;
pass_valid_rdreq <= 1'b0;
ack_rdreq <= 1'b0;
ack_valid_rdreq <= 1'b0;
if(tx_pkt_usedw <= 8'd161)begin
if(ack_valid_empty == 1'b0)begin
ack_rdreq <= 1'b1;
ack_valid_rdreq <= 1'b1;
state <= ack_head0_s;
end
else if(pass_valid_empty == 1'b0)begin
if(pass_valid_q==1'b0)begin//drop
pass_pkt_rdreq <= 1'b1;
pass_valid_rdreq <= 1'b1;
state <= drop_s;
end
else begin
pass_pkt_rdreq <= 1'b1;
pass_valid_rdreq <= 1'b1;
state <= pass_data_s;
end
end
else begin
state <= idle_s;
end
end
else begin
state <= idle_s;
end
end
ack_head0_s:begin
ack_rdreq <= 1'b1;
ack_valid_rdreq <= 1'b0;
tx_pkt[138:136] <= 3'b101;
tx_pkt[135:128] <= 8'hf0;
tx_pkt[127:96] <= ack_rdata[31:0];
state <= ack_head1_s;
end
ack_head1_s:begin
tx_pkt[95:64] <= ack_rdata[31:0];
state <= ack_head2_s;
end
ack_head2_s:begin
tx_pkt[63:32] <= ack_rdata[31:0];
state <= ack_head3_s;
end
ack_head3_s:begin
tx_pkt[31:0] <= ack_rdata[31:0];
tx_pkt_wrreq <= 1'b1;
state <= ack_mid0_s;
end
ack_mid0_s:begin
tx_pkt_wrreq <= 1'b0;
if(ack_rdata[35:34]==2'b10)begin//tail
ack_rdreq <= 1'b0;
tx_pkt[138:136] <= 3'b110;
tx_pkt[135:128] <= 8'h30;
tx_pkt[127:96] <= ack_rdata[31:0];
tx_pkt_wrreq <= 1'b1;
tx_pkt_valid_wrreq <= 1'b1;
tx_pkt_valid <= 1'b1;
state <= wait_s;
end
else begin
tx_pkt[127:96] <= ack_rdata[31:0];
state <= ack_mid1_s;
end
end
ack_mid1_s:begin
if(ack_rdata[35:34]==2'b10)begin//tail
ack_rdreq <= 1'b0;
tx_pkt[138:136] <= 3'b110;
tx_pkt[135:128] <= 8'h70;
tx_pkt[95:64] <= ack_rdata[31:0];
tx_pkt_wrreq <= 1'b1;
tx_pkt_valid_wrreq <= 1'b1;
tx_pkt_valid <= 1'b1;
state <= wait_s;
end
else begin
tx_pkt[95:64] <= ack_rdata[31:0];
state <= ack_mid2_s;
end
end
ack_mid2_s:begin
if(ack_rdata[35:34]==2'b10)begin//tail
ack_rdreq <= 1'b0;
tx_pkt[138:136] <= 3'b110;
tx_pkt[135:128] <= 8'hb0;
tx_pkt[63:32] <= ack_rdata[31:0];
tx_pkt_wrreq <= 1'b1;
tx_pkt_valid_wrreq <= 1'b1;
tx_pkt_valid <= 1'b1;
state <= wait_s;
end
else begin
tx_pkt[63:32] <= ack_rdata[31:0];
state <= ack_mid3_s;
end
end
ack_mid3_s:begin
if(ack_rdata[35:34]==2'b10)begin//tail
ack_rdreq <= 1'b0;
tx_pkt[138:136] <= 3'b110;
tx_pkt[135:128] <= 8'hf0;
tx_pkt[31:0] <= ack_rdata[31:0];
tx_pkt_wrreq <= 1'b1;
tx_pkt_valid_wrreq <= 1'b1;
tx_pkt_valid <= 1'b1;
state <= wait_s;
end
else begin
tx_pkt[138:136] <= 3'b100;
tx_pkt[135:128] <= 8'hf0;
tx_pkt[31:0] <= ack_rdata[31:0];
tx_pkt_wrreq <= 1'b1;
tx_pkt_valid_wrreq <= 1'b0;
ack_rdreq <= 1'b1;
state <= ack_mid0_s;
end
end
pass_data_s:begin
pass_valid_rdreq <= 1'b0;
tx_pkt <= pass_pkt_q;
tx_pkt_wrreq <= 1'b1;
if(pass_pkt_q[138:136] == 3'b110)begin
tx_pkt_valid_wrreq <= 1'b1;
tx_pkt_valid <= 1'b1;
pass_pkt_rdreq <= 1'b0;
state <= wait_s;
end
else begin
pass_pkt_rdreq <= 1'b1;
state <= pass_data_s;
end
end
drop_s:begin
pass_valid_rdreq <= 1'b0;
if(pass_pkt_q[138:136] == 3'b110)begin
pass_pkt_rdreq <= 1'b0;
state <= wait_s;
end
else begin
pass_pkt_rdreq <= 1'b1;
state <= drop_s;
end
end
wait_s:begin
tx_pkt_wrreq <= 1'b0;
tx_pkt_valid_wrreq <= 1'b0;
pass_pkt_rdreq <= 1'b0;
pass_valid_rdreq <= 1'b0;
ack_rdreq <= 1'b0;
ack_valid_rdreq <= 1'b0;
state <= idle_s;
end
endcase
end
end
reg pass_pkt_rdreq;
wire [138:0]pass_pkt_q;
wire [7:0] pass_pkt_usedw;
fifo_256_139 fifo_256_139_manage_tx(
.aclr(!reset_n),
.clock(clk),
.data(pass_pkt),
.rdreq(pass_pkt_rdreq),
.wrreq(pass_pkt_wrreq),
.q(pass_pkt_q),
.usedw(pass_pkt_usedw)
);
reg pass_valid_rdreq;
wire pass_valid_q;
wire pass_valid_empty;
fifo_64_1 fifo_64_1_manage_tx(
.aclr(!reset_n),
.clock(clk),
.data(pass_valid),
.rdreq(pass_valid_rdreq),
.wrreq(pass_valid_wrreq),
.empty(pass_valid_empty),
.q(pass_valid_q)
);
//ÏìÓ¦±¨ÎÄ ±¨ÎÄFIFO
wire [9:0] wrusedw_ack;
reg ack_rdreq;
wire [35:0] ack_rdata;
tx_fifo ack_fifo (
.aclr(!reset_n),
.data(ack_pkt),
.rdclk(clk),
.rdreq(ack_rdreq),
.wrclk(clk),
.wrreq(ack_wr),
.q(ack_rdata),
.rdempty(),
.wrusedw(wrusedw_ack));
assign ack_afull = (wrusedw_ack > 10'd640)?1'b1:1'b0;//ÒѾ·ÅÁË2564¸ö×Ö½Ú£¬»¹ÄÜ·Å1532¸ö×Ö½Ú
wire [7:0] wrusedw_valid_ack;
reg ack_valid_rdreq;
wire ack_valid_rdata;
wire ack_valid_empty;
tx_valid_fifo ack_valid_fifo(//FPGA·µ»ØµÄ±¨ÎĿ϶¨ÓÐЧ¡£ÒòΪÎÞ·¨ÅжÏ×Ô¼ºÉú³ÉµÄ±¨ÎÄ´íÎó¡£
.aclr(!reset_n),
.data(1'b1),
.rdclk(clk),
.rdreq(ack_valid_rdreq),
.wrclk(clk),
.wrreq(ack_valid_wr),
.q(ack_valid_rdata),
.rdempty(ack_valid_empty),
.wrusedw(wrusedw_valid_ack));
assign ack_valid_afull = (wrusedw_valid_ack > 8'd250)?1'b1:1'b0;
endmodule |
module tx_valid_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [7:0] sub_wire1;
wire [0:0] sub_wire2;
wire rdempty = sub_wire0;
wire [7:0] wrusedw = sub_wire1[7:0];
wire [0:0] q = sub_wire2[0:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
module ddr2_ctrl_input(
sys_rst_n,
ddr2_clk,
local_init_done,
local_ready,
local_address,
local_read_req,
local_write_req,
local_wdata,
local_be,
local_size,
local_burstbegin,
um2ddr_wrclk,
um2ddr_wrreq,
um2ddr_data,
um2ddr_ready,
um2ddr_command_wrreq,
um2ddr_command,
rd_ddr2_size,
rd_ddr2_size_wrreq,
read_permit
);
input sys_rst_n;
input ddr2_clk;
input local_ready;
input local_init_done;
output[25:0] local_address;
output local_write_req;
output local_read_req;
output local_burstbegin;
output[31:0] local_wdata;
output[3:0] local_be;
output[3:0] local_size;
input um2ddr_wrclk;
input um2ddr_wrreq;
input [127:0] um2ddr_data;
output um2ddr_ready;
input um2ddr_command_wrreq;
input [33:0] um2ddr_command;
output[6:0] rd_ddr2_size;
output rd_ddr2_size_wrreq;
input read_permit;
/////////////////////////////////////
reg[25:0] local_address;
reg local_write_req;
reg local_read_req;
reg local_burstbegin;
reg[31:0] local_wdata;
reg[3:0] local_be;
reg[3:0] local_size;
wire um2ddr_ready;
reg[6:0] rd_ddr2_size;
reg rd_ddr2_size_wrreq;
reg[95:0] um2ddr_reg;
///////////////////////////////////
reg [6:0] pkt_len;
reg [1:0] shift;
reg [25:0] op_addr;
reg [2:0] state;
///////////////////////////////////
assign um2ddr_ready = ~(um2ddr_afull | um2ddr_command_afull); //changed by mxl from & to |;
///////////////////////////////////
parameter idle_s = 3'h0,
wr_start_s = 3'h1,
wr_mid_fs = 3'h2,
wr_mid_sd = 3'h3,
wr_end_s = 3'h4,
rd_start_s = 3'h5,
rd_s = 3'h6,
wait_s = 3'h7;
always@(posedge ddr2_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)begin
local_write_req <= 1'b0;
local_read_req <= 1'b0;
local_burstbegin <= 1'b0;
rd_ddr2_size_wrreq <= 1'b0;
um2ddr_command_rdreq <= 1'b0;
um2ddr_rdreq <= 1'b0;
um2ddr_reg <= 96'b0;
shift <= 2'b0;
state <= idle_s;
end
else begin
case(state)
idle_s:begin
if(um2ddr_command_empty)begin
local_write_req <= 1'b0;
local_read_req <= 1'b0;
local_burstbegin <= 1'b0;
rd_ddr2_size_wrreq <= 1'b0;
um2ddr_command_rdreq <= 1'b0;
state <= idle_s;
end
else begin
op_addr <= um2ddr_command_rdata[25:0];
pkt_len <= um2ddr_command_rdata[32:26];
um2ddr_command_rdreq <= 1'b1;
local_address <= um2ddr_command_rdata[25:0];
if(um2ddr_command_rdata[33])begin//read ddr2
pkt_len <= um2ddr_command_rdata[32:26]<<2;
state <= rd_start_s;
end
else begin//write ddr2
um2ddr_rdreq <= 1'b1;
//local_wdata <= um2ddr_rdata;
state <= wr_start_s;
end
end
end
wr_start_s:begin
um2ddr_command_rdreq <= 1'b0;
um2ddr_rdreq <= 1'b0;
if(local_ready&local_init_done)begin
local_write_req <= 1'b1;
local_burstbegin <= 1'b1;
local_be <= 4'hf;
local_size <= 4'h4;
pkt_len <= pkt_len - 1'b1;
local_address <= op_addr ;
// um2ddr_rdreq <= 1'b1;
local_wdata <= um2ddr_rdata[127:96];
um2ddr_reg <= um2ddr_rdata[95:0];
state <= wr_mid_fs;
end
else begin
local_write_req <= 1'b0;
state <= wr_start_s;
end
end
wr_mid_fs:
begin
if(local_ready&local_init_done)
begin
local_write_req <= 1'b1;
local_burstbegin <= 1'b0;
um2ddr_rdreq <= 1'b0;
local_be <= 4'hf;
local_wdata <= um2ddr_reg[95:64];
state <= wr_mid_sd;
end
else
begin
//local_write_req <= 1'b0;
local_burstbegin <= 1'b0;
um2ddr_rdreq <= 1'b0;
state <= wr_mid_fs;
end
end
wr_mid_sd:
begin
if(local_ready&local_init_done)
begin
local_write_req <= 1'b1;
um2ddr_rdreq <= 1'b0;
local_be <= 4'hf;
local_wdata <= um2ddr_reg[63:32];
state <= wr_end_s;
end
else
begin
// local_write_req <= 1'b0;
state <= wr_mid_sd;
end
end
wr_end_s:
begin
if(local_ready&local_init_done)
begin
local_write_req <= 1'b1;
um2ddr_rdreq <= 1'b0;
local_be <= 4'hf;
local_wdata <= um2ddr_reg[31:0];
op_addr <= op_addr + 4'h4;
if(pkt_len == 7'h0)
begin
state <= idle_s;
end
else
begin
um2ddr_rdreq <= 1'b1;
state <= wr_start_s;
end
end
else
begin
state <= wr_end_s;
end
end
rd_start_s:begin
um2ddr_command_rdreq <= 1'b0;
if(read_permit==1'b0)begin
state <= rd_start_s;
end
else begin
rd_ddr2_size <= pkt_len;
rd_ddr2_size_wrreq <= 1'b1;
state <= rd_s;
end
end
rd_s:begin
rd_ddr2_size_wrreq <= 1'b0;
if(local_ready&&local_init_done)
begin
local_read_req <= 1'b1;
local_burstbegin <= 1'b1;
local_be <= 4'hf;
local_address <= op_addr;
if(pkt_len > 7'h8)
begin
local_size <= 4'h4;
pkt_len <= pkt_len - 4'h4;
op_addr <= op_addr + 4'h4;
state <= wait_s;
end
else begin
local_size <= pkt_len[3:0];
//op_addr <= op_addr + pkt_len[3:0];
//local_read_req <= 1'b0;
//local_burstbegin <= 1'b0;
state <= idle_s;
end
end
else begin
local_read_req <= 1'b0;
state <= rd_s;
end
end
wait_s:begin
local_read_req <= 1'b0;
state <= rd_s;
end
default:begin
local_write_req <= 1'b0;
local_read_req <= 1'b0;
local_burstbegin <= 1'b0;
rd_ddr2_size_wrreq <= 1'b0;
um2ddr_command_rdreq <= 1'b0;
um2ddr_rdreq <= 1'b0;
state <= idle_s;
end
endcase
end
end
wire [9:0] um2ddr_wrusedw;
reg um2ddr_rdreq;
wire [127:0] um2ddr_rdata;
wire um2ddr_empty;
um2ddr_fifo um2ddr_fifo (
.aclr(!sys_rst_n),
.data(um2ddr_data),
.rdclk(ddr2_clk),
.rdreq(um2ddr_rdreq),
.wrclk(um2ddr_wrclk),
.wrreq(um2ddr_wrreq),
.q(um2ddr_rdata),
.rdempty(um2ddr_empty),
.wrusedw(um2ddr_wrusedw));
wire um2ddr_afull;
assign um2ddr_afull = (um2ddr_wrusedw > 9'd127)?1'b1:1'b0;
wire [7:0] um2ddr_command_wrusedw;
reg um2ddr_command_rdreq;
wire [33:0] um2ddr_command_rdata;
wire um2ddr_command_empty;
um2ddr_command_fifo um2ddr_command_fifo (
.aclr(!sys_rst_n),
.data(um2ddr_command),
.rdclk(ddr2_clk),
.rdreq(um2ddr_command_rdreq),
.wrclk(um2ddr_wrclk),
.wrreq(um2ddr_command_wrreq),
.q(um2ddr_command_rdata),
.rdempty(um2ddr_command_empty),
.wrusedw(um2ddr_command_wrusedw));
wire um2ddr_command_afull;
assign um2ddr_command_afull = (um2ddr_command_wrusedw > 8'hfa)?1'b1:1'b0;
endmodule |
module ddr2_ctrl_output(
sys_rst_n,
ddr2_clk,
local_rdata,
local_rdata_valid,
ddr2um_rdclk,
ddr2um_rdreq,
ddr2um_rdata,
ddr2um_valid_rdreq,
ddr2um_valid_rdata,
ddr2um_valid_empty,
rd_ddr2_size,
rd_ddr2_size_wrreq,
read_permit
);
input sys_rst_n;
input ddr2_clk;
input [31:0] local_rdata;
input local_rdata_valid;
input ddr2um_rdclk;
input ddr2um_rdreq;
output[127:0] ddr2um_rdata;
input ddr2um_valid_rdreq;
output[6:0] ddr2um_valid_rdata;
output ddr2um_valid_empty;
input[6:0] rd_ddr2_size;
input rd_ddr2_size_wrreq;
output read_permit;
/////////////////////////////////////
wire[127:0] ddr2um_rdata;
wire[6:0] ddr2um_valid_rdata;
wire read_permit;
reg [9:0]write_depth_cnt;
reg [2:0] current_state;
parameter idle =3'h0,
rd_2s =3'h1,
rd_3s =3'h2,
wr_1p =3'h3;
always@(posedge ddr2_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)begin
ddr2um_wrreq <= 1'b0;
write_depth_cnt <= 10'b0;
current_state <= idle;
end
else begin
case(current_state)
idle:begin
if(local_rdata_valid)
begin
ddr2um_data[127:96] <= local_rdata;
current_state <= rd_2s;
ddr2um_wrreq <= 1'b0;
if(ddr2um_valid_wrreq == 1'b1)
begin
write_depth_cnt <= write_depth_cnt + 1'b1 - (ddr2um_valid_data<<2);
end
else
begin
write_depth_cnt <= write_depth_cnt + 4'h1;
end
end
else
begin
ddr2um_wrreq <= 1'b0;
//current_state <= wr_1p;
if(ddr2um_valid_wrreq == 1'b1)
begin
write_depth_cnt <= write_depth_cnt - (ddr2um_valid_data<<2);
end
else
begin
write_depth_cnt <= write_depth_cnt;
end
current_state <= idle;
end
end
rd_2s:begin
if(local_rdata_valid)
begin
ddr2um_data[95:64] <= local_rdata;
current_state <= rd_3s;
write_depth_cnt <= write_depth_cnt + 4'h1;
//ddr2um_wrreq <= 1'b1;
end
else
begin
current_state <= rd_2s;
end
end
rd_3s:begin
if(local_rdata_valid)
begin
ddr2um_data[63:32] <= local_rdata;
current_state <= wr_1p;
write_depth_cnt <= write_depth_cnt + 4'h1;
//ddr2um_wrreq <= 1'b1;
end
else
begin
current_state <= rd_3s;
end
end
wr_1p:begin
if(local_rdata_valid)
begin
ddr2um_data[31:0] <= local_rdata;
ddr2um_wrreq <= 1'b1;
current_state <= idle;
if(ddr2um_valid_wrreq == 1'b1)
begin
write_depth_cnt <= write_depth_cnt + 1'b1 - (ddr2um_valid_data<<2);
end
else
begin
write_depth_cnt <= write_depth_cnt + 4'h1;
end
end
else
begin
ddr2um_wrreq <= 1'b0;
//current_state <= wr_1p;
if(ddr2um_valid_wrreq == 1'b1)
begin
write_depth_cnt <= write_depth_cnt - (ddr2um_valid_data<<2);
end
else
begin
write_depth_cnt <= write_depth_cnt;
end
end
end
default:
begin
ddr2um_wrreq <= 1'b0;
write_depth_cnt <= 10'b1;
current_state <= idle;
end
endcase
end
end
reg state;
parameter idle_s = 1'b0,
stop_read_s = 1'b1;
always@(posedge ddr2_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)begin
rd_ddr2_size_rdreq <= 1'b0;
ddr2um_valid_wrreq <= 1'b0;
state <= idle_s;
end
else begin
case(state)
idle_s:begin
if(write_depth_cnt!=10'b0)begin
if(write_depth_cnt>=rd_ddr2_size_rdata)begin
ddr2um_valid_wrreq <= 1'b1;
ddr2um_valid_data <= rd_ddr2_size_rdata>>2;
rd_ddr2_size_rdreq <= 1'b1;
state <= stop_read_s;
end
else begin
ddr2um_valid_wrreq <= 1'b0;
rd_ddr2_size_rdreq <= 1'b0;
state <= idle_s;
end
end
else begin
ddr2um_valid_wrreq <= 1'b0;
rd_ddr2_size_rdreq <= 1'b0;
state <= idle_s;
end
end
stop_read_s:begin
rd_ddr2_size_rdreq <= 1'b0;
ddr2um_valid_wrreq <= 1'b0;
state <= idle_s;
end
default:begin
rd_ddr2_size_rdreq <= 1'b0;
ddr2um_valid_wrreq <= 1'b0;
state <= idle_s;
end
endcase
end
end
wire [3:0] rd_ddr2_size_wrusedw;
reg rd_ddr2_size_rdreq;
wire [6:0] rd_ddr2_size_rdata;
wire rd_ddr2_size_empty;
wire [3:0] rd_ddr2_size_rdusedw;
ddr2um_valid_fifo rd_ddr2_size_fifo (
.aclr(!sys_rst_n),
.data(rd_ddr2_size),
.rdclk(ddr2_clk),
.rdreq(rd_ddr2_size_rdreq),
.wrclk(ddr2_clk),
.wrreq(rd_ddr2_size_wrreq),
.q(rd_ddr2_size_rdata),
.rdempty(rd_ddr2_size_empty),
.wrusedw(rd_ddr2_size_wrusedw));
// .rdusedw(rd_ddr2_size_rdusedw)
//assign rd_ddr2_size_afull = (rd_ddr2_size_wrusedw > 8'hfa)?1'b1:1'b0;
wire [9:0] ddr2um_wrusedw;
reg ddr2um_wrreq;
reg [127:0] ddr2um_data;
//wire ddr2um_empty;
ddr2um_fifo ddr2um_fifo (
.aclr(!sys_rst_n),
.data(ddr2um_data),
.rdclk(ddr2um_rdclk),
.rdreq(ddr2um_rdreq),
.wrclk(ddr2_clk),
.wrreq(ddr2um_wrreq),
.q(ddr2um_rdata),
.rdempty(),
.wrusedw(ddr2um_wrusedw));
//assign ddr2um_afull = (ddr2um_wrusedw > 9'd127)?1'b1:1'b0;
wire [3:0] ddr2um_valid_wrusedw;
reg ddr2um_valid_wrreq;
reg [6:0] ddr2um_valid_data;
wire ddr2um_valid_empty;
ddr2um_valid_fifo ddr2um_valid_fifo (
.aclr(!sys_rst_n),
.data(ddr2um_valid_data),
.rdclk(ddr2um_rdclk),
.rdreq(ddr2um_valid_rdreq),
.wrclk(ddr2_clk),
.wrreq(ddr2um_valid_wrreq),
.q(ddr2um_valid_rdata),
.rdempty(ddr2um_valid_empty),
.wrusedw(ddr2um_valid_wrusedw));
//assign ddr2um_valid_afull = (ddr2um_valid_wrusedw > 8'hfa)?1'b1:1'b0;
assign read_permit = ((rd_ddr2_size_wrusedw + ddr2um_valid_wrusedw)<= 4'h6)? 1'b1 : 1'b0;
endmodule |
module um2ddr_command_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [33:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [33:0] q;
output rdempty;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [33:0] sub_wire0;
wire sub_wire1;
wire [7:0] sub_wire2;
wire [33:0] q = sub_wire0[33:0];
wire rdempty = sub_wire1;
wire [7:0] wrusedw = sub_wire2[7:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrusedw (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 34,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
module ddr2_interface2um(
fpga_resetn, //system reset,active low
sysclk_100m, //system clk=100MHz LVCOMS
ddr2_ck, //DDR2 System Clock Pos
ddr2_ck_n, //DDR2 System Clock Neg
//Address
ddr2_addr, //only addresses (12:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
ddr2_bank_addr, //only addresses (1:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
ddr2_ras_n, //Row address select
ddr2_cas_n, //Column address select
ddr2_we_n, //Write enable
//command and control
ddr2_cs_n, //Chip Select
ddr2_cke, //Clock Enable
ddr2_odt, //On-die termination enable
//Data Bus
ddr2_dq, //Data
ddr2_dqs, //Strobe Pos
ddr2_dqs_n, //Strobe Neg
ddr2_dm, //Byte write mask
um2ddr_wrclk,
um2ddr_wrreq,
um2ddr_data,
um2ddr_ready,
um2ddr_command_wrreq,
um2ddr_command,
ddr2um_rdclk,
ddr2um_rdreq,
ddr2um_rdata,
ddr2um_valid_rdreq,
ddr2um_valid_rdata,
ddr2um_valid_empty
);
input sysclk_100m; //system clk=100MHz LVCOMS
input fpga_resetn; //system reset,active low
//////ddr2 interface/////////////////
inout ddr2_ck; //DDR2 System Clock Pos
inout ddr2_ck_n; //DDR2 System Clock Neg
//Address
output [15:0] ddr2_addr; //only addresses (12:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
output [2:0] ddr2_bank_addr;
//only addresses (1:0) are currently used for 512Mb(32Mb*16) DDR2 SDRAM
output ddr2_ras_n; //Row address select
output ddr2_cas_n; //Column address select
output ddr2_we_n; //Write enable
//command and control
output ddr2_cs_n; //Chip Select
output ddr2_cke; //Clock Enable
output ddr2_odt; //On-die termination enable
//Data Bus
inout [15:0] ddr2_dq; //Data
inout [1:0] ddr2_dqs; //Strobe Pos
inout [1:0] ddr2_dqs_n; //Strobe Neg
inout [1:0] ddr2_dm; //Byte write mask
///um interface //////////////
input um2ddr_wrclk;
input um2ddr_wrreq;
input [127:0] um2ddr_data;
output um2ddr_ready;
input um2ddr_command_wrreq;
input [33:0] um2ddr_command;
input ddr2um_rdclk;
input ddr2um_rdreq;
output[127:0] ddr2um_rdata;
input ddr2um_valid_rdreq;
output[6:0] ddr2um_valid_rdata;
output ddr2um_valid_empty;
wire local_ready;
wire [31:0] local_rdata;
wire local_rdata_valid;
wire local_init_done;
wire[23:0] local_address;
wire local_write_req;
wire local_read_req;
wire local_burstbegin;
wire[31:0] local_wdata;
wire[3:0] local_be;
wire[3:0] local_size;
wire phy_clk;
assign ddr2_addr[15:13] = 3'b0;
assign ddr2_bank_addr[2] = 1'b0;
ddr2 ddr2_ctrl_hp_inst
(
.pll_ref_clk(sysclk_100m) , // input pll_ref_clk_sig
.global_reset_n(fpga_resetn) , // input global_reset_n_sig
.soft_reset_n(fpga_resetn) , // input soft_reset_n_sig
.local_address(local_address) , // input [25:0] local_address_sig //by cyj
.local_write_req(local_write_req) , // input local_write_req_sig
.local_wdata_req() , // output local_wdata_req_sig
.local_wdata(local_wdata) , // input [127:0] Write data in fourth
.local_read_req(local_read_req) , // input local_read_req_sig
.local_be(local_be) , // input [15:0] local_be_sig
.local_size(local_size) , // input [1:0] local_size_sig //only 1bits
.local_ready(local_ready) , // output local_ready_sig
.local_rdata(local_rdata) , // output [127:0] local_rdata_sig output 256bits data by cyj
.local_rdata_valid(local_rdata_valid) , // output local_rdata_valid_sig
.local_init_done(local_init_done) , // output local_init_done_sig -- Not used
.local_burstbegin(local_burstbegin),
.reset_request_n() , // output reset_request_n_sig -- Not used
.mem_odt(ddr2_odt) , // output [0:0] mem_odt_sig
.mem_cs_n(ddr2_cs_n) , // output [0:0] mem_cs_n_sig
.mem_cke(ddr2_cke) , // output [0:0] mem_cke_sig
.mem_addr(ddr2_addr[12:0]) , // output [13:0] mem_addr_sig
.mem_ba(ddr2_bank_addr[1:0]) , // output [1:0] mem_ba_sig //by cyj 3 signals
.mem_ras_n(ddr2_ras_n) , // output mem_ras_n_sig
.mem_cas_n(ddr2_cas_n) , // output mem_cas_n_sig
.mem_we_n(ddr2_we_n) , // output mem_we_n_sig
.mem_dm(ddr2_dm) , // output [7:0] mem_dm_sig
.local_refresh_ack() , // output local_refresh_ack_sig -- Not used
.reset_phy_clk_n() , // output reset_phy_clk_n_sig -- Not used
.dll_reference_clk() , // output dll_reference_clk_sig -- Not used
.dqs_delay_ctrl_export() , // output [5:0] dqs_delay_ctrl_export_sig -- Not used
.local_powerdn_ack(), //by cyj
.phy_clk(phy_clk) , // output phy_clk_sig
.aux_full_rate_clk() , // output aux_full_rate_clk_sig -- Not used
.aux_half_rate_clk() , // output aux_half_rate_clk_sig -- Not used
.mem_clk(ddr2_ck) , // inout [1:0] mem_clk_sig
.mem_clk_n(ddr2_ck_n) , // inout [1:0] mem_clk_n_sig
.mem_dq(ddr2_dq) , // inout [63:0] mem_dq_sig
.mem_dqs(ddr2_dqs), // inout [7:0] mem_dqs_sig
.mem_dqsn(ddr2_dqs_n) //by cyj
);
ddr2_ctrl ddr2_ctrl(
.sys_rst_n(fpga_resetn),
.ddr2_clk(phy_clk),
.local_init_done(local_init_done),
.local_ready(local_ready),
.local_address(local_address),
.local_read_req(local_read_req),
.local_write_req(local_write_req),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.local_burstbegin(local_burstbegin),
.um2ddr_wrclk(um2ddr_wrclk),
.um2ddr_wrreq(um2ddr_wrreq),
.um2ddr_data(um2ddr_data),
.um2ddr_ready(um2ddr_ready),
.um2ddr_command_wrreq(um2ddr_command_wrreq),
.um2ddr_command(um2ddr_command),
.ddr2um_rdclk(ddr2um_rdclk),
.ddr2um_rdreq(ddr2um_rdreq),
.ddr2um_rdata(ddr2um_rdata),
.ddr2um_valid_rdreq(ddr2um_valid_rdreq),
.ddr2um_valid_rdata(ddr2um_valid_rdata),
.ddr2um_valid_empty(ddr2um_valid_empty)
);
endmodule |
module ddr2_ctrl(
sys_rst_n,
ddr2_clk,
local_init_done,
local_ready,
local_address,
local_read_req,
local_write_req,
local_wdata,
local_be,
local_size,
local_rdata,
local_rdata_valid,
local_burstbegin,
um2ddr_wrclk,
um2ddr_wrreq,
um2ddr_data,
um2ddr_ready,
um2ddr_command_wrreq,
um2ddr_command,
ddr2um_rdclk,
ddr2um_rdreq,
ddr2um_rdata,
ddr2um_valid_rdreq,
ddr2um_valid_rdata,
ddr2um_valid_empty
);
input sys_rst_n;
input ddr2_clk;
input local_ready;
input [31:0] local_rdata;
input local_rdata_valid;
input local_init_done;
output[25:0] local_address;
output local_write_req;
output local_read_req;
output local_burstbegin;
output[31:0] local_wdata;
output[3:0] local_be;
output[3:0] local_size;
input um2ddr_wrclk;
input um2ddr_wrreq;
input [127:0] um2ddr_data;
output um2ddr_ready;
input um2ddr_command_wrreq;
input [33:0] um2ddr_command;
input ddr2um_rdclk;
input ddr2um_rdreq;
output[127:0] ddr2um_rdata;
input ddr2um_valid_rdreq;
output[6:0] ddr2um_valid_rdata;
output ddr2um_valid_empty;
ddr2_ctrl_input ddr2_ctrl_input(
.sys_rst_n(sys_rst_n),
.ddr2_clk(ddr2_clk),
.local_init_done(local_init_done),
.local_ready(local_ready),
.local_address(local_address),
.local_read_req(local_read_req),
.local_write_req(local_write_req),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.local_burstbegin(local_burstbegin),
.um2ddr_wrclk(um2ddr_wrclk),
.um2ddr_wrreq(um2ddr_wrreq),
.um2ddr_data(um2ddr_data),
.um2ddr_ready(um2ddr_ready),
.um2ddr_command_wrreq(um2ddr_command_wrreq),
.um2ddr_command(um2ddr_command),
.rd_ddr2_size(rd_ddr2_size),
.rd_ddr2_size_wrreq(rd_ddr2_size_wrreq),
.read_permit(read_permit)
);
wire[6:0] rd_ddr2_size;
wire rd_ddr2_size_wrreq;
wire read_permit;
ddr2_ctrl_output ddr2_ctrl_output(
.sys_rst_n(sys_rst_n),
.ddr2_clk(ddr2_clk),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.ddr2um_rdclk(ddr2um_rdclk),
.ddr2um_rdreq(ddr2um_rdreq),
.ddr2um_rdata(ddr2um_rdata),
.ddr2um_valid_rdreq(ddr2um_valid_rdreq),
.ddr2um_valid_rdata(ddr2um_valid_rdata),
.ddr2um_valid_empty(ddr2um_valid_empty),
.rd_ddr2_size(rd_ddr2_size),
.rd_ddr2_size_wrreq(rd_ddr2_size_wrreq),
.read_permit(read_permit)
);
endmodule |
module mdio_mdc(
input reset,
input clk,
//-----------------------------------mdio 接口---------------------------------
output mdc,//输出给外部芯片的时钟
inout mdio,
//--------------用户给出的操作指令组---------------------
input req_enb,//使能信号，类似于片选信号
input [1:0] req_op, //本次请求的操作模式 2'b10为读，2'b01有效为写
input [4:0] phy_addr,//phy芯片选择
input [4:0] reg_addr,//phy芯片中的寄存器选择
input [15:0] data_phy,
//--------------给用户的当前忙闲信号---------------------
output work_flag,//1:正在工作状态 0：处于闲置状态
//-----------------------------------
output reg [15:0] data_sta,
output sta_enb
);
wire turn_z_flag;//器件时序图中标注的在读请求操作中，当处于Turn around状态下应该为高阻态
assign turn_z_flag = ((state==TA_STATE)&&(op_flag == 1'b0));
wire z_flag;//mdio的控制信号，该信号有效时，mdio输出高阻态（即不驱动）,可参考器件手册中的时序图
//根据时序图，总共有3种情况下应该给外部器件MDIO接口输出高阻z
//1.在IDLE状态时一直处于高阻态
//2.在器件时序图中标注的在读请求操作中，当处于Turn around状态下的发送第一个bit应该为高阻态
//3.当处于读请求操作时（这个时候MDIO应该是外部器件的输出通道，因此本逻辑应该将其置为高阻，以防冲突）
assign z_flag = ( (!work_flag) || turn_z_flag || rd_data_flag ) ? 1'b1 : 1'b0;
//---------------MDIO信号处理部分---------------------------
assign mdc = clk;
assign mdio = (z_flag) ? 1'bz : mdio_out;
wire mdio_in;
assign mdio_in = mdio;
//==========================================
reg [2:0] state;
reg [4:0] count_bit;
parameter IDLE_STATE=3'd0,
PRE_STATE=3'd1,
ST_STATE=3'd2,
OP_STATE=3'd3,
PHYAD_STATE=3'd4,
REGAD_STATE=3'd5,
TA_STATE=3'd6,
DATA_STATE=3'd7;
//------------------状态机跳转部分----------------------
wire state_jump_flag;//状态机跳转条件，由于条件仅两条，因此放在外面写
wire req_coming_flag;//IDLE状态时，在req_enb信号有效时跳转
wire count_over_flag;//其他状态时在计步器count_bit为0时跳转
assign req_coming_flag = (state == IDLE_STATE) && (req_enb == 1);
assign count_over_flag = (state != IDLE_STATE) && (count_bit==0);
assign state_jump_flag = req_coming_flag || count_over_flag;
always @(posedge clk or negedge reset) begin
if(!reset) begin
count_bit<=0;
state<=IDLE_STATE;
end
else begin
if(count_bit!= 5'd0) begin//必须放在下个if语句之前，以防count_bit <= count_bit；语句将下个count_bit赋值语句覆盖，从而始终为0
count_bit <= count_bit-5'd1;
end
else begin
count_bit <= count_bit;
end
if(state_jump_flag == 1'b1) begin
case(state)
IDLE_STATE: begin
count_bit<=5'd7;
state<=PRE_STATE;
end
PRE_STATE: begin
count_bit<=5'd1;
state<=ST_STATE;
end
ST_STATE: begin
count_bit<=5'd1;
state<=OP_STATE;
end
OP_STATE: begin
count_bit<=5'd4;
state<=PHYAD_STATE;
end
PHYAD_STATE: begin
count_bit<=5'd4;
state<=REGAD_STATE;
end
REGAD_STATE: begin
count_bit<=5'd1;
state<=TA_STATE;
end
TA_STATE: begin
count_bit<=5'd15;
state<=DATA_STATE;
end
DATA_STATE: begin
count_bit<=5'd0;
state<=IDLE_STATE;
end
default: begin
count_bit<=5'd0;
state<=IDLE_STATE;
end
endcase
end
else begin
state <= state;
end
end
end
//---------------寄存一拍后模块正式使用的操作指令组--------------------
//preamble| start of frame | Option| PHY addr | REG addr | Turn around | Data
// 8bit | 2bit | 2bit | 5bit | 5bit | 2bit | 16bit
//preamble 并不是必须的，如果有要求可以删去（文档中有描述）
//------------------将用户输入的操作指令寄存一拍，以便对指令进行解析------------------------
reg [39:0] shift_reg;
reg op_flag;//寄存op模式，以便后续处理的判断，0：read 1：wr
wire mdio_out;//每次输出shift_reg寄存器在左移中被移出的最高位
assign mdio_out = shift_reg[39];
assign work_flag = (state != IDLE_STATE);
always @(posedge clk or negedge reset) begin
if(!reset) begin
op_flag <= 1'b0;
shift_reg <= 40'b0;
end
else begin
if(req_coming_flag == 1'b1) begin //用户指令到达,即IDLE状态时，在req_enb信号有效，存储用户发送的指令
op_flag <= req_op[0];
shift_reg <= {8'hff,2'b01,req_op,phy_addr,reg_addr,2'b10,data_phy};
end
else if(work_flag) begin//处于非IDLE_STATE的工作状态，开始移位工作模式
op_flag <= op_flag;
shift_reg <= {shift_reg[38:0],1'b0};
end
else begin//处于IDLE_STATE,但是req_enb并没有来
op_flag <= 1'b0;
shift_reg <= 40'b0;
end
end
end
//--------------------------------------------------------读操作时读出的数据以及数据指示信号----------------------------------------------------
wire rd_data_flag;//正在读数据阶段
reg rd_data_flag_r;
assign rd_data_flag = (state==DATA_STATE) && (op_flag== 1'b0);
always @(posedge clk or negedge reset) begin
if(!reset) begin
rd_data_flag_r <= 1'b0;
end
else begin
rd_data_flag_r <= rd_data_flag;
end
end
assign sta_enb = (~rd_data_flag) & rd_data_flag_r;
always @(posedge clk or negedge reset) begin
if(!reset) begin
data_sta<=16'd0;
end
else begin
if(rd_data_flag == 1'b1) begin//正在读数据阶段
data_sta<={data_sta[14:0],mdio_in};
end
else begin
data_sta<=data_sta;
end
end
end
endmodule |
module top_mido(
input reset,
input clk,
//-----------------------------------mdio ½Ó¿Ú---------------------------------
output mdc,//Êä³ö¸øÍⲿоƬµÄʱÖÓ
inout mdio,
output [3:0] port_link
);
/************Ä£¿éÁ¬½ÓÇø**************/
wire req_enb;//ʹÄÜÐźţ¬ÀàËÆÓÚƬѡÐźÅ
wire [1:0] req_op; //±¾´ÎÇëÇóµÄ²Ù×÷ģʽ [1]ÓÐЧΪ¶Á£¬[0]ÓÐЧΪд
wire [4:0] phy_addr;//phyоƬѡÔñ
wire [4:0] reg_addr;//phyоƬÖеļĴæÆ÷Ñ¡Ôñ
wire [15:0] data_phy;
//--------------¸øÓû§µÄµ±Ç°Ã¦ÏÐÐźÅ---------------------
wire work_flag;//1:ÕýÔÚ¹¤×÷״̬ 0£º´¦ÓÚÏÐÖÃ״̬
//-----------------------------------
wire [15:0] data_sta;
wire sta_enb;
mdio_mdc mdio_mdc(
.reset(reset),
.clk(clk),
//-----------------------------------mdio ½Ó¿Ú---------------------------------
.mdc(mdc),//Êä³ö¸øÍⲿоƬµÄʱÖÓ
.mdio(mdio),
//--------------Óû§¸ø³öµÄ²Ù×÷Ö¸Áî×é---------------------
.req_enb(req_enb),//ʹÄÜÐźţ¬ÀàËÆÓÚƬѡÐźÅ
.req_op(req_op), //±¾´ÎÇëÇóµÄ²Ù×÷ģʽ [1]ÓÐЧΪ¶Á£¬[0]ÓÐЧΪд
.phy_addr(phy_addr),//phyоƬѡÔñ
.reg_addr(reg_addr),//phyоƬÖеļĴæÆ÷Ñ¡Ôñ
.data_phy(data_phy),
//--------------¸øÓû§µÄµ±Ç°Ã¦ÏÐÐźÅ---------------------
.work_flag(work_flag),//1:ÕýÔÚ¹¤×÷״̬ 0£º´¦ÓÚÏÐÖÃ״̬
//-----------------------------------
.data_sta(data_sta),
.sta_enb(sta_enb)
);
reg_access reg_access (
.clk(clk),
.data_sta(data_sta),
.phy_addr(phy_addr),
.port_link(port_link),
.reg_addr(reg_addr),
.req_enb(req_enb),
.req_op(req_op),
.reset(reset),
.sta_enb(sta_enb),
.work_bit(work_flag)
);
endmodule |
module reg_access (
input clk,
input reset,
input work_bit,
//给出的操作指令
output reg req_enb,
output reg [1:0] req_op,
output reg [4:0]phy_addr,
output reg [4:0]reg_addr,
output reg [3:0]port_link,
input [15:0]data_sta,
input sta_enb
);
reg [31:0]cnt;
reg [4:0]state;
reg timer;
parameter idle =4'd0,
read_port0=4'h1,
send_data0=4'h2,
read_port1=4'd3,
key_data1 =4'd4,
send_data1=4'd5,
read_port2=4'd6,
key_data2 =4'd7,
send_data2=4'd8,
read_port3=4'd9,
key_data3 =4'hA,
send_data3=4'hB;
//
always@(posedge clk,negedge reset)begin//生成计数信息
if(!reset)begin
cnt<=32'b0;
timer<=1'b0;
end
else if(cnt<32'd1250000)begin
cnt<=cnt+1'b1;
timer<=1'b0;
end
else begin
cnt<=32'b0;
timer<=1'b1;
end
end
always@(posedge clk,negedge reset)begin
if(!reset)begin
req_enb<=1'b0;
req_op<=2'b10;
phy_addr<=5'b0;
port_link<=4'b0;
state<=idle;
end
else begin//每0.1s完整读一次四个电口link信息
case(state)
idle: if(timer==1'b1&&work_bit==1'b0)begin//计数0.1s
state<=read_port0;
end
else begin
state<=idle;//判断是否处于空闲状态，不是继续等待
end
//
read_port0: begin//读0号端口的link信息
req_enb<=1'b1;//
req_op<=2'b10;//读操作
phy_addr<=5'd0;//0号端口地址
reg_addr<=5'd1;//读phy芯片里面的一号寄存器
if(work_bit==1'b1)begin//判断是否处于空闲状态
req_enb<=1'b0;
state<=send_data0;
end
else begin
state<=read_port0;
end
end
//
send_data0: begin//写link信息,给输出端口
if(sta_enb==1'b1)begin//读数据
port_link[0]<=data_sta[2];
req_enb<=1'b0;
state<=read_port1;
end
else begin
state<=send_data0;
end
end
//
read_port1: if(work_bit==1'b0)begin//读1号端口的link信息
req_enb<=1'b1;
req_op<=2'b10;
phy_addr<=5'd1;
reg_addr<=5'd1;//读phy芯片里面的一号寄存器
state<=key_data1;
end
else begin
state<=read_port1;
end
//
key_data1: if(work_bit==1'b1)begin//判断是否处于空闲状态
req_enb<=1'b0;
state<=send_data1;
end
else begin
state<=key_data1;
end
//
send_data1: begin//写link信息,给输出端口
if(sta_enb==1'b1)begin//读数据
port_link[1]<=data_sta[2];
req_enb<=1'b0;
state<=read_port2;
end
else begin
state<=send_data1;
end
end
//
read_port2: if(work_bit==1'b0)begin//读2号端口的link信息
req_enb<=1'b1;
req_op<=2'b10;
phy_addr<=5'd2;
reg_addr<=5'd1;//读phy芯片里面的一号寄存器
state<=key_data2;
end
else begin
state<=read_port2;
end
//
key_data2: if(work_bit==1'b1)begin//判断是否处于空闲状态
req_enb<=1'b0;
state<=send_data2;
end
else begin
state<=key_data2;
end
//
send_data2: begin//写link信息,给输出端口
if(sta_enb==1'b1)begin//读数据
port_link[2]<=data_sta[2];
req_enb<=1'b0;
state<=read_port3;
end
else begin
state<=send_data2;
end
end
//
read_port3: begin
if(work_bit==1'b0)begin//读3号端口的link信息
req_enb<=1'b1;
req_op<=2'b10;
phy_addr<=5'd3;
reg_addr<=5'd1;//读phy芯片里面的一号寄存器
state<=key_data3;
end
else begin
state<=read_port3;
end
end
//
key_data3: if(work_bit==1'b1)begin//判断是否处于空闲状态
req_enb<=1'b0;
state<=send_data3;
end
else begin
state<=key_data3;
end
//
send_data3: if(sta_enb==1'b1)begin//读数据
port_link[3]<=data_sta[2];
req_enb<=1'b0;
state<=idle;
end
else begin
state<=send_data3;
end
default: state<=idle;
endcase
end
end
endmodule |
module buf_manage(
input clk,
input reset,
//cut pkt
input pkt_metadata_cut_out_valid,
input [359:0] pkt_metadata_cut_out,
input [138:0] pkt_cut_data,
input pkt_cut_data_valid,
output [7:0] pkt_cut_data_usedw,
input [10:0] ram_rd_addr,
input ram_rd,
output [138:0] ram_data_q,
input [3:0] pkt_out_recycle_addr,
input pkt_out_recycle_addr_wr,
//no cut pkt
input pkt_metadata_nocut_out_valid,
input [359:0] pkt_metadata_nocut_out,
input [138:0] pkt_nocut_data,
input pkt_nocut_data_valid,
output [7:0] pkt_nocut_data_usedw,
input [10:0] nocut_pkt_ram_rd_addr,
input nocut_pkt_ram_rd,
output [138:0] nocut_pkt_ram_data_q,
input [3:0] nocutpkt_out_recycle_addr,
input nocutpkt_out_recycle_addr_wr,
//result
output [4:0] pkt_addr, //[4] == cutpkt 0 nocut pkt
output pkt_addr_wr,
output [63:0] metadata_data,
output metadata_data_wr,
output p2k_valid,
output [7:0] p2k_ingress,
output [127:0] p2k_rloc_src,
output [127:0] p2k_eid_dst,
output [71:0] p2k_metadata
);
wire [3:0] aging_recycle_addr;
wire aging_recycle_addr_wr;
wire buf_addr_wr;
wire [3:0] buf_addr;
wire [339:0] pkt_metadata_nocut;
wire pkt_metadata_nocut_valid;
wire [339:0] pkt_metadata_out;
wire pkt_metadata_out_valid;
wire nocutbuf_addr_wr;
wire [3:0] nocutbuf_addr;
pkt_recomb pkt_recomb(
.clk (clk),
.reset (reset),
.pkt_metadata_cut_out_valid (pkt_metadata_cut_out_valid),
.pkt_metadata_cut_out (pkt_metadata_cut_out),
.pkt_cut_data (pkt_cut_data),
.pkt_cut_data_valid (pkt_cut_data_valid),
.pkt_cut_data_usedw (pkt_cut_data_usedw),
.buf_addr_wr (buf_addr_wr),
.buf_addr (buf_addr),
.aging_recycle_addr (aging_recycle_addr),
.aging_recycle_addr_wr (aging_recycle_addr_wr),
.pkt_metadata_out (pkt_metadata_out), //[339:336]==pkt_addr,[335:0]
.pkt_metadata_out_valid (pkt_metadata_out_valid),
.ram_rd_addr (ram_rd_addr),
.ram_rd (ram_rd),
.ram_data_q (ram_data_q));
buf_add_manage cutpkt_buf_add_manage(
.clk (clk),
.reset (reset),
.aging_recycle_addr (aging_recycle_addr),
.aging_recycle_addr_wr (aging_recycle_addr_wr),
.pkt_out_recycle_addr (pkt_out_recycle_addr),
.pkt_out_recycle_addr_wr (pkt_out_recycle_addr_wr),
.buf_addr_wr (buf_addr_wr),
.buf_addr (buf_addr));
pkt_mux pkt_mux(
.clk (clk),
.reset (reset),
.pkt_metadata_nocut (pkt_metadata_nocut),
.pkt_metadata_nocut_valid (pkt_metadata_nocut_valid),
.pkt_metadata_out (pkt_metadata_out), //[349:336]==pkt_addr,[335:0]
.pkt_metadata_out_valid (pkt_metadata_out_valid),
.pkt_addr (pkt_addr),
.pkt_addr_wr (pkt_addr_wr),
.metadata_data (metadata_data),
.metadata_data_wr (metadata_data_wr),
.p2k_valid (p2k_valid),
.p2k_ingress (p2k_ingress),
.p2k_rloc_src (p2k_rloc_src),
.p2k_eid_dst (p2k_eid_dst),
.p2k_metadata (p2k_metadata));
pkt_in_buf pkt_in_buf(
.clk (clk),
.reset (reset),
.pkt_metadata_nocut_out_valid (pkt_metadata_nocut_out_valid),
.pkt_metadata_nocut_out (pkt_metadata_nocut_out),
.pkt_nocut_data (pkt_nocut_data),
.pkt_nocut_data_valid (pkt_nocut_data_valid),
.pkt_nocut_data_usedw (pkt_nocut_data_usedw),
.buf_addr_wr (nocutbuf_addr_wr),
.buf_addr (nocutbuf_addr),
.pkt_metadata_nocut (pkt_metadata_nocut),
.pkt_metadata_nocut_valid (pkt_metadata_nocut_valid),
.nocut_pkt_ram_rd_addr (nocut_pkt_ram_rd_addr),
.nocut_pkt_ram_rd (nocut_pkt_ram_rd),
.nocut_pkt_ram_data_q (nocut_pkt_ram_data_q));
buf_add_manage nocutpkt_buf_add_manage(
.clk (clk),
.reset (reset),
.aging_recycle_addr (4'b0),
.aging_recycle_addr_wr (1'b0),
.pkt_out_recycle_addr (nocutpkt_out_recycle_addr),
.pkt_out_recycle_addr_wr (nocutpkt_out_recycle_addr_wr),
.buf_addr_wr (nocutbuf_addr_wr),
.buf_addr (nocutbuf_addr));
endmodule |
module buf_add_manage(
input clk,
input reset,
input [3:0] aging_recycle_addr,
input aging_recycle_addr_wr,
input [3:0] pkt_out_recycle_addr,
input pkt_out_recycle_addr_wr,
output reg buf_addr_wr,
output reg [3:0] buf_addr
);
reg [3:0] count;
wire aging_recycle_addr_empty,pkt_out_recycle_addr_empty;
wire [3:0] aging_recycle_addr_q,pkt_out_recycle_addr_q;
reg aging_recycle_addr_rd,pkt_out_recycle_addr_rd;
reg [2:0] current_state;
parameter idle_s = 3'd0,
idle_s1 = 3'd1,
trans_s = 3'd2,
trans_s1 = 3'd3,
initial_s = 3'd4;
always @ (posedge clk or negedge reset)
if(!reset) begin
aging_recycle_addr_rd <= 1'b0;
pkt_out_recycle_addr_rd <= 1'b0;
buf_addr_wr <= 1'b0;
buf_addr <= 4'b0;
count <= 4'b0;
current_state <= initial_s;
end
else begin
case(current_state)
initial_s: begin
if(count ==4'hf) begin
buf_addr_wr <= 1'b1;
buf_addr <= count;
current_state <= idle_s;
end
else begin
buf_addr_wr <= 1'b1;
buf_addr <= count;
count <= count + 1'b1;
current_state <= initial_s;
end
end
idle_s: begin
buf_addr_wr <= 1'b0;
if(aging_recycle_addr_empty == 1'b1) begin
current_state <= idle_s1;
end
else begin
aging_recycle_addr_rd <= 1'b1;
current_state <= trans_s;
end
end
idle_s1: begin
buf_addr_wr <= 1'b0;
if(pkt_out_recycle_addr_empty == 1'b1) begin
current_state <= idle_s;
end
else begin
pkt_out_recycle_addr_rd <= 1'b1;
current_state <= trans_s1;
end
end
trans_s: begin
buf_addr_wr <= 1'b1;
aging_recycle_addr_rd <= 1'b0;
buf_addr <= aging_recycle_addr_q;
current_state <= idle_s1;
end
trans_s1: begin
buf_addr_wr <= 1'b1;
pkt_out_recycle_addr_rd <= 1'b0;
buf_addr <= pkt_out_recycle_addr_q;
current_state <= idle_s;
end
endcase
end
fifo_4_16 fifo_aging_recycle_addr (
.aclr (!reset),
.clock (clk),
.data (aging_recycle_addr),
.rdreq (aging_recycle_addr_rd),
.wrreq (aging_recycle_addr_wr),
.empty (aging_recycle_addr_empty),
.q (aging_recycle_addr_q));
fifo_4_16 fifo_pkt_out_recycle_addr (
.aclr (!reset),
.clock (clk),
.data (pkt_out_recycle_addr),
.rdreq (pkt_out_recycle_addr_rd),
.wrreq (pkt_out_recycle_addr_wr),
.empty (pkt_out_recycle_addr_empty),
.q (pkt_out_recycle_addr_q));
endmodule |
module search_engine(
clk,
reset,
key_valid,
key,
bv_valid,
bv,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out
);
input clk;
input reset;
input key_valid;
input [26:0]key;
output bv_valid;
output[35:0]bv;
input localbus_cs_n;
input localbus_rd_wr;
input[31:0] localbus_data;
input localbus_ale;
output localbus_ack_n;
output[31:0] localbus_data_out;
reg localbus_ack_n;
reg [31:0] localbus_data_out;
wire bv_valid;
wire[35:0] bv;
reg set_valid_1,set_valid_2,set_valid_3;
reg read_valid_1,read_valid_2,read_valid_3;
//reg [8:0] read_addr_1,read_addr_2,read_addr_3;
wire data_out_valid_1,data_out_valid_2,data_out_valid_3;
wire[35:0] data_out_1,data_out_2,data_out_3;
wire[35:0] bv_1,bv_2,bv_3;
wire stage_enable_1,stage_enable_2,stage_enable_3;
//---state----//
reg [3:0] set_state;
parameter idle = 4'd0,
ram_set = 4'd1,
ram_read = 4'd2,
wait_read = 4'd3,
wait_back = 4'd4;
//--------------reg--------------//
//--search--//
//--set--//
reg [31:0] localbus_addr;
reg [44:0] set_data;//addr_9+36;
reg [12:0] set_data_1;//addr_9+localbus[31]_vald+localbus[2:0]; 1st;
reg [35:0] data_out;
reg [8:0] read_addr;
//-----------------------search_state-----------------//
//-----------------------set_state---------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
set_valid_1 <= 1'b0;set_valid_2 <= 1'b0;set_valid_3 <= 1'b0;
read_valid_1<= 1'b0;read_valid_2<= 1'b0;read_valid_3<= 1'b0;
localbus_addr <= 32'b0;
data_out <= 36'd0;
set_data <= 45'b0;
set_data_1 <= 13'b0;
read_addr <= 9'b0;
localbus_data_out <= 32'b0;
localbus_ack_n <= 1'b1;
end
else
begin
case(set_state)
idle:
begin
if(localbus_ale == 1'b1)
begin
localbus_addr <= localbus_data;
if(localbus_rd_wr == 1'b0)
begin
set_state <= ram_set;
end
else
begin
set_state <= ram_read;
end
end
end
ram_set:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'd0: set_data_1 <= {localbus_addr[11:3],localbus_data[31],localbus_data[2:0]};//????zq0825
1'd1:
begin
set_data <= {set_data_1,localbus_data};
case(localbus_addr[13:12])
3'd0: set_valid_1 <= 1'b1;
3'd1: set_valid_2 <= 1'b1;
3'd2: set_valid_3 <= 1'b1;
3'd3: set_valid_3 <= 1'b0;
endcase
end
endcase
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
ram_read:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'b0:
begin
read_addr <= localbus_addr[11:3];
case(localbus_addr[13:12])
3'd0: read_valid_1 <= 1'b1;
3'd1: read_valid_2 <= 1'b1;
3'd2: read_valid_3 <= 1'b1;
3'd3: read_valid_3 <= 1'b1;
endcase
end
1'b1: localbus_data_out <= data_out[31:0];
endcase
if(localbus_addr[0] == 1'b0)
begin
set_state <= wait_read;
end
else
begin
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
end
wait_read:
begin
read_valid_1 <= 1'b0;read_valid_2 <= 1'b0;read_valid_3 <= 1'b0;
if((data_out_valid_1 == 1'b1) || (data_out_valid_2 == 1'b1) || (data_out_valid_3 == 1'b1))
begin
case({data_out_valid_1,data_out_valid_2,data_out_valid_3})
3'd4:
begin
data_out <= data_out_1;
localbus_data_out <= {data_out_1[35],28'b0,data_out_1[34:32]};
end
3'd2:
begin
data_out <= data_out_2;
localbus_data_out <= {data_out_2[35],28'b0,data_out_2[34:32]};
end
3'd1:
begin
data_out <= data_out_3;
localbus_data_out <= {data_out_3[35],28'b0,data_out_3[34:32]};
end
default:
begin
data_out <= 36'b0;
localbus_data_out <= 32'b0;
end
endcase
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
end
wait_back:
begin
set_valid_1 <= 1'b0;set_valid_2 <= 1'b0;set_valid_3 <= 1'b0;
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
set_state <= idle;
end
end
default:
begin
set_state <= idle;
end
endcase
end
end
//-----------------stage_1------------------//
lookup_9bit stage_1_1(
.clk(clk),
.reset(reset),
.set_valid(set_valid_1),
.set_data(set_data),
.read_valid(read_valid_1),
.read_addr(read_addr),
.data_out_valid(data_out_valid_1),
.data_out(data_out_1),
.key_valid(key_valid),
.key(key[26:18]),
//.bv_valid(),
.bv(bv_1),
.stage_enable(stage_enable_1)
);
//--stage_1_2--//
lookup_9bit stage_1_2(
.clk(clk),
.reset(reset),
.set_valid(set_valid_2),
.set_data(set_data),
.read_valid(read_valid_2),
.read_addr(read_addr),
.data_out_valid(data_out_valid_2),
.data_out(data_out_2),
.key_valid(key_valid),
.key(key[17:9]),
//.bv_valid(),
.bv(bv_2),
.stage_enable()
);
//--stage_1_3--//
lookup_9bit stage_1_3(
.clk(clk),
.reset(reset),
.set_valid(set_valid_3),
.set_data(set_data),
.read_valid(read_valid_3),
.read_addr(read_addr),
.data_out_valid(data_out_valid_3),
.data_out(data_out_3),
.key_valid(key_valid),
.key(key[8:0]),
//.bv_valid(),
.bv(bv_3),
.stage_enable()
);
//--stage_2--//
hold1clk stage_2(
.clk(clk),
.reset(reset),
.stage_enable_in(stage_enable_1),
.stage_enable_out(stage_enable_2)
);
//--stage_3--//
bv_and stage_3(
.clk(clk),
.reset(reset),
.stage_enable_in(stage_enable_2),
.stage_enable_out(stage_enable_3),
.bv_1(bv_1),
.bv_2(bv_2),
.bv_3(bv_3),
.bv_valid(bv_valid),
.bv(bv)
);
endmodule |
module lookup(
clk,
reset,
p2k_valid,
p2k_ingress,
p2k_rloc_src,
p2k_eid_dst,
p2k_metadata,
mode,
xtr_id,
action2parser_en,
transmit2action_en,
pkt_buffer_label_valid_in,
pkt_buffer_label_in,
pkt_head_valid_in,
pkt_head_in,
fragment_valid,
fragment_pkt_buffer_label,
outrule_valid,
outrule,
pkt_buffer_label_valid_out,
pkt_buffer_label_out,
pkt_head_valid_out,
pkt_head_out,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out
);
input clk;
input reset;
input p2k_valid;
input [7:0] p2k_ingress;
input [127:0] p2k_rloc_src;
input [127:0] p2k_eid_dst;
input [71:0] p2k_metadata;
input mode;
input [7:0] xtr_id;
output action2parser_en;
input transmit2action_en;
input pkt_buffer_label_valid_in;
input [31:0] pkt_buffer_label_in;
input pkt_head_valid_in;
input [138:0] pkt_head_in;
output fragment_valid;
output [31:0] fragment_pkt_buffer_label;
output outrule_valid;
output [15:0] outrule;
output pkt_buffer_label_valid_out;
output [31:0] pkt_buffer_label_out;
output pkt_head_valid_out;
output [138:0] pkt_head_out;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output localbus_ack_n;
output [31:0] localbus_data_out;
wire fragment_valid;
wire [31:0] fragment_pkt_buffer_label;
wire action2parser_en;
wire outrule_valid;
wire [15:0] outrule;
wire pkt_buffer_label_valid_out;
wire [31:0] pkt_buffer_label_out;
wire pkt_head_valid_out;
wire [138:0] pkt_head_out;
wire localbus_ack_n;
wire [31:0] localbus_data_out;
wire k2m_metadata_valid;
wire [107:0] k2m_metadata;
wire action_valid;
wire [15:0] action;
wire action_data_valid;
wire [351:0] action_data;
key_gen key_gen(
.clk(clk),
.reset(reset),
.p2k_valid(p2k_valid),
.p2k_ingress(p2k_ingress),
.p2k_rloc_src(p2k_rloc_src),
.p2k_eid_dst(p2k_eid_dst),
.p2k_metadata(p2k_metadata[71:64]),
.mode(mode),
.k2m_metadata_valid(k2m_metadata_valid),
.k2m_metadata(k2m_metadata)
);
match match(
.clk(clk),
.reset(reset),
.metadata_valid(k2m_metadata_valid),
.metadata(k2m_metadata),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale),
.localbus_ack_n(localbus_ack_n),
.localbus_data_out(localbus_data_out),
.action_valid(action_valid),
.action(action),
.action_data_valid(action_data_valid),
.action_data(action_data)
);
endmodule |
module lookup_rule(
clk,
reset,
bv_valid_1,
bv_1,
bv_valid_2,
bv_2,
bv_valid_3,
bv_3,
bv_valid_4,
bv_4,
action_valid,
action,
action_data_valid,
action_data,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out
);
input clk;
input reset;
input bv_valid_1;
input [35:0] bv_1;
input bv_valid_2;
input [35:0] bv_2;
input bv_valid_3;
input [35:0] bv_3;
input bv_valid_4;
input [35:0] bv_4;
output action_valid;
output[15:0] action;
output action_data_valid;
output[351:0] action_data;//rloc_src,rloc_dst,mac_dst,mac_src;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output localbus_ack_n;
output [31:0] localbus_data_out;
reg action_valid;
reg [15:0] action;
reg action_data_valid;
reg [351:0] action_data;
reg localbus_ack_n;
reg [31:0] localbus_data_out;
//--reg--//
reg [31:0] localbus_addr;
reg [35:0] bv;
reg [17:0] bv_18;
reg [8:0] bv_9;
reg [4:0] bv_5;
//--------ram-----------//
//---rule_ram---//
reg [5:0] address_a,address_b;
reg wren_b;
reg rden_a,rden_b;
reg [31:0] data_b;
wire [31:0] q_a,q_b;
//---xtr_info_ram---//
reg [5:0] xtr_info_addr_a;
reg [5:0] xtr_info_addr_b;
reg xtr_info_wren_b;
reg xtr_info_rden_a;
reg xtr_info_rden_b;
reg [351:0] xtr_info_data_b;
wire [351:0] xtr_info_q_a;
wire [351:0] xtr_info_q_b;
reg [351:0] xtr_info_action_data;
//----------state------//
reg [3:0] set_state;
reg flag;
reg hold1clk_in_1;
wire hold1clk_out_1,hold1clk_out_2,hold1clk_out_3,hold1clk_out_4,hold1clk_out_5,
hold1clk_out_6,hold1clk_out_7,hold1clk_out_8,hold1clk_out_9;
reg[6:0] addr1,addr2,addr3;
reg [15:0] action_1_r,action_2_r,action_3_r;//pipeline:deliver_action;
reg [5:0] index;
parameter idle = 4'd0,
ram_set_action = 4'd1,
read_ram_action = 4'd2,
wait_1_action = 4'd3,
wait_2_action = 4'd4,
ram_read_action = 4'd5,
ram_set_action_data = 4'd6,
ram_read_action_data = 4'd7,
wait_1_action_data = 4'd8,
wait_2_action_data = 4'd9,
read_ram_action_data = 4'd10,
wait_back = 4'd11;
//---------------------------state-------------------//
//--------------bv_&----//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
flag <= 1'b0;
end
else
begin
if(bv_valid_1 == 1'b1)
begin
flag <= 1'b1;
bv <= bv_1 & bv_2 & bv_3 &bv_4;
end
else flag <= 1'b0;
end
end
//--------------stage_1_bv_18----//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
hold1clk_in_1 <= 1'b0;
addr1 <= 7'b0;
end
else
begin
if(flag == 1'b1)
begin
hold1clk_in_1 <= 1'b1;
if((bv[35]==1'b1) && (bv[34:0] != 35'b0))
begin
if(bv[34:17] == 18'b0)
begin
bv_18 <= bv[17:0];
addr1 <= {1'b1,6'd17};
end
else
begin
bv_18 <= bv[34:17];
addr1 <= {1'b1,6'b0};
end
end
else
begin
bv_18 <= 18'b0;
addr1 <= 7'b0;
end
end
else
begin
hold1clk_in_1 <= 1'b0;
end
end
end
//--------------stage_2_bv_9----//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
addr2 <=7'b0;
bv_9 <= 9'b0;
end
else
begin
if(hold1clk_out_1 == 1'b1)
begin
if(addr1[6]==1'b1)
if(bv_18[17:9]== 9'b0)
begin
bv_9 <= bv_18[8:0];
addr2 <= addr1 + 7'd9;
end
else
begin
bv_9 <= bv_18[17:9];
addr2 <= addr1;
end
else addr2 <= 7'b0;
end
end
end
//--------------stage_3_bv_5----//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
addr3 <= 7'b0;
bv_5 <= 5'b0;
end
else
begin
if(hold1clk_out_2 == 1'b1)
begin
if(addr2[6]==1'b1)
if(bv_9[8:4]== 5'b0)
begin
bv_5 <= bv_9[4:0];
addr3 <= addr2 + 7'd4;
end
else
begin
bv_5 <= bv_9[8:4];
addr3 <= addr2;
end
else addr3 <= 7'b0;
end
end
end
//--------------stage_4_read_rule----//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
rden_a <= 1'b0;
end
else
begin
if(hold1clk_out_3 == 1'b1)
begin
rden_a <= 1'b1;
if(addr3[6]==1'b0) address_a <= 6'b0;
else
begin
if(bv_5[4]) address_a <= addr3[5:0] + 6'd1;
else if(bv_5[3]) address_a <= addr3[5:0] + 6'd2;
else if(bv_5[2]) address_a <= addr3[5:0] + 6'd3;
else if(bv_5[1]) address_a <= addr3[5:0] + 6'd4;
else if(bv_5[0]) address_a <= addr3[5:0] + 6'd5;
else address_a <= 6'b0;
end
end
else rden_a <= 1'b0;
end
end
//--------------lookup_rule_output----//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
action_valid <= 1'b0;
action <= 16'b0;
end
else
begin
if(hold1clk_out_6 == 1'b1)
begin
action_valid <= 1'b1;
action <= q_a[15:0];
index <= q_a[21:16];
end
else action_valid <= 1'b0;
end
end
//-----------read_action_data_ram----------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
action_1_r <= 16'b0;
end
else
begin
if(action_valid == 1'b1)
begin
action_1_r <= action;
xtr_info_addr_a <= index;
xtr_info_rden_a <= 1'b1;
end
else
begin
xtr_info_rden_a <= 1'b0;
end
end
end
//---action_deliver_2----//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
action_2_r <= 16'b0;
end
else
begin
action_2_r <= action_1_r;
end
end
//---action_deliver_3----//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
action_3_r <= 16'b0;
end
else
begin
action_3_r <= action_2_r;
end
end
//------------action_data-----------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
action_data_valid <= 1'b0;
action_data <= 352'b0;
end
else
begin
if(hold1clk_out_9 == 1'b1)
begin
action_data_valid <= 1'b1;
action_data <= xtr_info_q_a;
end
else
begin
action_data_valid <= 1'b0;
end
end
end
//-------set_state-------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
wren_b <= 1'b0;
rden_b <= 1'b0;
xtr_info_wren_b <= 1'b0;
xtr_info_rden_b <= 1'b0;
xtr_info_data_b <= 352'b0;
xtr_info_action_data <= 352'b0;
localbus_data_out <= 32'b0;
localbus_ack_n <= 1'b1;
localbus_addr <= 32'b0;
data_b <= 32'b0;
xtr_info_addr_b <= 6'b0;
address_b <= 6'b0;
end
else
begin
case(set_state)
idle:
begin
if(localbus_ale == 1'b1)
begin
localbus_addr <= localbus_data;
if(localbus_data[12] == 1'b0)
begin
if(localbus_rd_wr == 1'b0)
begin
set_state <= ram_set_action;
end
else
begin
set_state <= ram_read_action;
end
end
else
begin
if(localbus_rd_wr == 1'b0)
begin
set_state <= ram_set_action_data;
end
else
begin
set_state <= ram_read_action_data;
end
end
end
else set_state <= idle;
end
ram_set_action:
begin
if(localbus_cs_n == 1'b0)
begin
wren_b <= 1'b1;
address_b <= localbus_addr[5:0];
data_b <= localbus_data;
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
end
ram_read_action:
begin
if(localbus_cs_n == 1'b0)
begin
rden_b <= 1'b1;
address_b <= localbus_addr[5:0];
set_state <= wait_1_action;
end
end
wait_1_action:
begin
rden_b <= 1'b0;
set_state <= wait_2_action;
end
wait_2_action:
begin
set_state <= read_ram_action;
end
read_ram_action:
begin
localbus_data_out <= q_b;
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
ram_set_action_data:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[3:0])
4'd0: xtr_info_data_b[351:320] <= localbus_data;
4'd1: xtr_info_data_b[319:288] <= localbus_data;
4'd2: xtr_info_data_b[287:256] <= localbus_data;
4'd3: xtr_info_data_b[255:224] <= localbus_data;
4'd4: xtr_info_data_b[223:192] <= localbus_data;
4'd5: xtr_info_data_b[191:160] <= localbus_data;
4'd6: xtr_info_data_b[159:128] <= localbus_data;
4'd7: xtr_info_data_b[127:96] <= localbus_data;
4'd8: xtr_info_data_b[95:64] <= localbus_data;
4'd9: xtr_info_data_b[63:32] <= localbus_data;
4'd10:
begin
xtr_info_data_b[31:0] <= localbus_data;
xtr_info_addr_b <= localbus_addr[9:4];
xtr_info_wren_b <= 1'b1;
end
default: xtr_info_data_b[31:0] <= localbus_data;
endcase
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
else set_state <= ram_set_action_data;
end
ram_read_action_data:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[3:0])
4'd0:
begin
set_state <= wait_1_action_data;
xtr_info_addr_b <= localbus_addr[9:4];
xtr_info_rden_b <= 1'b1;
end
4'd1:
begin
localbus_data_out <= xtr_info_action_data[319:288];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
4'd2:
begin
localbus_data_out <= xtr_info_action_data[287:256];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
4'd3:
begin
localbus_data_out <= xtr_info_action_data[255:224];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
4'd4:
begin
localbus_data_out <= xtr_info_action_data[223:192];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
4'd5:
begin
localbus_data_out <= xtr_info_action_data[191:160];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
4'd6:
begin
localbus_data_out <= xtr_info_action_data[159:128];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
4'd7:
begin
localbus_data_out <= xtr_info_action_data[127:96];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
4'd8:
begin
localbus_data_out <= xtr_info_action_data[95:64];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
4'd9:
begin
localbus_data_out <= xtr_info_action_data[63:32];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
4'd10:
begin
localbus_data_out <= xtr_info_action_data[31:0];
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
endcase
end
else set_state <= ram_read_action_data;
end
wait_1_action_data:
begin
xtr_info_rden_b <= 1'b0;
set_state <= wait_2_action_data;
end
wait_2_action_data:
begin
set_state <= read_ram_action_data;
end
read_ram_action_data:
begin
localbus_ack_n <= 1'b0;
localbus_data_out <= xtr_info_q_b[351:320];
xtr_info_action_data <= xtr_info_q_b;
set_state <= wait_back;
end
wait_back:
begin
wren_b <= 1'b0;
xtr_info_wren_b <= 1'b0;
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
set_state <= idle;
end
else set_state <= wait_back;
end
default:
begin
set_state <= idle;
end
endcase
end
end
ram_32_64 rule_ram(
.address_a(address_a),
.address_b(address_b),
.clock(clk),
.data_a(32'b0),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b(q_b)
);
ram_352_64 xtr_info_ram(
.address_a(xtr_info_addr_a),
.address_b(xtr_info_addr_b),
.clock(clk),
.data_a(352'b0),
.data_b(xtr_info_data_b),
.rden_a(xtr_info_rden_a),
.rden_b(xtr_info_rden_b),
.wren_a(1'b0),
.wren_b(xtr_info_wren_b),
.q_a(xtr_info_q_a),
.q_b(xtr_info_q_b)
);
//--stage_2--//
hold1clk h1c_1(
.clk(clk),
.reset(reset),
.stage_enable_in(flag),
.stage_enable_out(hold1clk_out_1)
);
//--stage_3--//
hold1clk h1c_2(
.clk(clk),
.reset(reset),
.stage_enable_in(hold1clk_out_1),
.stage_enable_out(hold1clk_out_2)
);
//--stage_4--//
hold1clk h1c_3(
.clk(clk),
.reset(reset),
.stage_enable_in(hold1clk_out_2),
.stage_enable_out(hold1clk_out_3)
);
//--stage_5--//
hold1clk h1c_4(
.clk(clk),
.reset(reset),
.stage_enable_in(hold1clk_out_3),
.stage_enable_out(hold1clk_out_4)
);
//--stage_6--//
hold1clk h1c_5(
.clk(clk),
.reset(reset),
.stage_enable_in(hold1clk_out_4),
.stage_enable_out(hold1clk_out_5)
);
//--stage_7--//
hold1clk h1c_6(
.clk(clk),
.reset(reset),
.stage_enable_in(hold1clk_out_5),
.stage_enable_out(hold1clk_out_6)
);
//--stage_8--//
hold1clk h1c_7(
.clk(clk),
.reset(reset),
.stage_enable_in(action_valid),
.stage_enable_out(hold1clk_out_7)
);
//--stage_9--//
hold1clk h1c_8(
.clk(clk),
.reset(reset),
.stage_enable_in(hold1clk_out_7),
.stage_enable_out(hold1clk_out_8)
);
//--stage_10--//
hold1clk h1c_9(
.clk(clk),
.reset(reset),
.stage_enable_in(hold1clk_out_8),
.stage_enable_out(hold1clk_out_9)
);
endmodule |
module bv_and(
clk,
reset,
stage_enable_in,
stage_enable_out,
bv_1,
bv_2,
bv_3,
bv_valid,
bv
);
input clk;
input reset;
input stage_enable_in;
output stage_enable_out;
input [35:0] bv_1;
input [35:0] bv_2;
input [35:0] bv_3;
output bv_valid;
output [35:0] bv;
reg bv_valid;
reg [35:0] bv;
reg stage_enable_out;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
stage_enable_out <= 1'b0;
bv_valid <= 1'b0;
bv <= 36'b0;
end
else
begin
if(stage_enable_in == 1'b1)
begin
bv <= bv_1 & bv_2 & bv_3;
bv_valid <= 1'b1;
end
else bv_valid <= 1'b0;
end
end
endmodule |
module match(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
metadata_valid,
metadata,
action_valid,
action,
action_data_valid,
action_data
);
input clk;
input reset;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output localbus_ack_n;
output [31:0] localbus_data_out;
input metadata_valid;
input [107:0] metadata;
output action_valid;
output[15:0] action;
output action_data_valid;
output[351:0] action_data;
wire action_valid;
wire [15:0] action;
wire action_data_valid;
wire [351:0] action_data;
reg localbus_ack_n;
reg [31:0] localbus_data_out;
//---//
wire search_1_bv_valid,search_2_bv_valid,search_3_bv_valid,search_4_bv_valid;
wire [35:0] search_1_bv,search_2_bv,search_3_bv,search_4_bv;
//--reg--//
//reg localbus_cs_n_1,localbus_cs_n_2,localbus_cs_n_3,localbus_cs_n_4,localbus_cs_n_5;
reg localbus_ale_1,localbus_ale_2,localbus_ale_3,localbus_ale_4,localbus_ale_5;
wire localbus_ack_n_1,localbus_ack_n_2,localbus_ack_n_3,localbus_ack_n_4,localbus_ack_n_5;
wire [31:0] localbus_data_out_1,localbus_data_out_2,localbus_data_out_3,localbus_data_out_4,localbus_data_out_5;
//--state--//
reg [3:0] set_state;
parameter idle = 4'd0,
set_wait = 4'd1,
wait_back = 4'd3;
//---------------------------set_state--------------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
localbus_data_out <= 32'b0;
localbus_ale_1 <= 1'b0;
localbus_ale_2 <= 1'b0;
localbus_ale_3 <= 1'b0;
localbus_ale_4 <= 1'b0;
localbus_ale_5 <= 1'b0;
localbus_ack_n <= 1'b1;
end
else
begin
case(set_state)
idle:
begin
if((localbus_ale == 1'b1) && (localbus_data[23] == 1'b0))
begin
case(localbus_data[19:16])
4'd0: localbus_ale_1 <= localbus_ale;
4'd1: localbus_ale_2 <= localbus_ale;
4'd2: localbus_ale_3 <= localbus_ale;
4'd3: localbus_ale_4 <= localbus_ale;
4'd4: localbus_ale_5 <= localbus_ale;
default: localbus_ale_5 <= localbus_ale;
endcase
set_state <= set_wait;
end
end
set_wait:
begin
localbus_ale_1 <= 1'b0;localbus_ale_2 <= 1'b0;localbus_ale_3 <= 1'b0;
localbus_ale_4 <= 1'b0;localbus_ale_5 <= 1'b0;
if((localbus_ack_n_1 == 1'b0) || (localbus_ack_n_2 == 1'b0) ||(localbus_ack_n_3 == 1'b0) ||
(localbus_ack_n_4 == 1'b0) ||(localbus_ack_n_5 == 1'b0))
begin
localbus_ack_n <= 1'b0;
set_state <= wait_back;
case({localbus_ack_n_1,localbus_ack_n_2,localbus_ack_n_3,
localbus_ack_n_4,localbus_ack_n_5})
5'b01111: localbus_data_out <= localbus_data_out_1;
5'b10111: localbus_data_out <= localbus_data_out_2;
5'b11011: localbus_data_out <= localbus_data_out_3;
5'b11101: localbus_data_out <= localbus_data_out_4;
5'b11110: localbus_data_out <= localbus_data_out_5;
default:
begin
localbus_data_out <= localbus_data_out_5;
end
endcase
end
end
wait_back:
begin
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
set_state <= idle;
end
end
default:
begin
set_state <= idle;
end
endcase
end
end
//---search_engine_1---//
search_engine search_engine_1(
.clk(clk),
.reset(reset),
.key_valid(metadata_valid),
.key(metadata[107:81]),
.bv_valid(search_1_bv_valid),
.bv(search_1_bv),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_1),
.localbus_ack_n(localbus_ack_n_1),
.localbus_data_out(localbus_data_out_1)
);
//---search_engine_2---//
search_engine search_engine_2(
.clk(clk),
.reset(reset),
.key_valid(metadata_valid),
.key(metadata[80:54]),
.bv_valid(search_2_bv_valid),
.bv(search_2_bv),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_2),
.localbus_ack_n(localbus_ack_n_2),
.localbus_data_out(localbus_data_out_2)
);
//---search_engine_3---//
search_engine search_engine_3(
.clk(clk),
.reset(reset),
.key_valid(metadata_valid),
.key(metadata[53:27]),
.bv_valid(search_3_bv_valid),
.bv(search_3_bv),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_3),
.localbus_ack_n(localbus_ack_n_3),
.localbus_data_out(localbus_data_out_3)
);
//---search_engine_4---//
search_engine search_engine_4(
.clk(clk),
.reset(reset),
.key_valid(metadata_valid),
.key(metadata[26:0]),
.bv_valid(search_4_bv_valid),
.bv(search_4_bv),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_4),
.localbus_ack_n(localbus_ack_n_4),
.localbus_data_out(localbus_data_out_4)
);
//----lookup_rule---//
lookup_rule lk_rule(
.clk(clk),
.reset(reset),
.bv_valid_1(search_1_bv_valid),
.bv_1(search_1_bv),
.bv_valid_2(search_2_bv_valid),
.bv_2(search_2_bv),
.bv_valid_3(search_3_bv_valid),
.bv_3(search_3_bv),
.bv_valid_4(search_4_bv_valid),
.bv_4(search_4_bv),
.action_valid(action_valid),
.action(action),
.action_data_valid(action_data_valid),
.action_data(action_data),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_5),
.localbus_ack_n(localbus_ack_n_5),
.localbus_data_out(localbus_data_out_5)
);
endmodule |
module lookup_9bit(
clk,
reset,
set_valid,
set_data,
read_valid,
read_addr,
data_out_valid,
data_out,
key_valid,
key,
//bv_valid,
bv,
stage_enable
);
input clk;
input reset;
input set_valid;
input [44:0] set_data;
input read_valid;
input [8:0] read_addr;
output data_out_valid;
output[35:0] data_out;
input key_valid;
input [8:0] key;
//output bv_valid;
output[35:0] bv;
output stage_enable;
reg data_out_valid;
reg [35:0] data_out;
//reg bv_valid;
wire [35:0] bv;
reg stage_enable;
//--reg--//
//----ram---//a:lookup; b:set;
reg [8:0] address_b;
reg rden_b;
reg wren_b;
reg [35:0] data_b;
wire [35:0] q_b;
//-------state----//
reg [3:0] set_state;
parameter idle = 4'd0,
read_wait_1 = 4'd1,
read_wait_2 = 4'd2,
read_ram = 4'd3;
//-----------------------state--------------------------//
//------search-----//
//--input--//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
stage_enable <= 1'b0;
end
else
begin
if(key_valid == 1'b1)
begin
stage_enable <= 1'b1;
end
else stage_enable <= 1'b0;
end
end
//---set---//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
data_out <= 36'b0;
data_out_valid <= 1'b0;
address_b <= 9'b0;
rden_b <= 1'b0;
data_b <= 36'b0;
end
else
begin
case(set_state)
idle:
begin
data_out_valid <= 1'b0;
if(set_valid == 1'b1)
begin
set_state <= idle;
wren_b <= 1'b1;
address_b <= set_data[44:36];
data_b <= set_data[35:0];
end
else if(read_valid == 1'b1)
begin
set_state <= read_wait_1;
wren_b <= 1'b0;
rden_b <= 1'b1;
address_b <= read_addr;
end
else
begin
wren_b <= 1'b0;
end
end
read_wait_1:
begin
rden_b <= 1'b0;
set_state <= read_wait_2;
end
read_wait_2:
begin
set_state <= read_ram;
end
read_ram:
begin
data_out_valid <= 1'b1;
data_out <= q_b;
set_state <= idle;
end
default:
begin
set_state <= idle;
end
endcase
end
end
ram_36_512 ram_1(
.address_a(key),
.address_b(address_b),
.clock(clk),
.data_a(36'b0),
.data_b(data_b),
.rden_a(key_valid),
.rden_b(rden_b),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(bv),
.q_b(q_b)
);
endmodule |
module altera_tse_pcs_pma_gige /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
gmii_tx_d,
gmii_tx_en,
gmii_tx_err,
gxb_cal_blk_clk,
gxb_pwrdn_in,
mii_tx_d,
mii_tx_en,
mii_tx_err,
read,
reconfig_clk,
reconfig_togxb,
ref_clk,
reset,
reset_rx_clk,
reset_tx_clk,
rxp,
write,
writedata,
// outputs:
gmii_rx_d,
gmii_rx_dv,
gmii_rx_err,
hd_ena,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
mii_col,
mii_crs,
mii_rx_d,
mii_rx_dv,
mii_rx_err,
pcs_pwrdn_out,
readdata,
reconfig_fromgxb,
rx_clk,
set_10,
set_100,
set_1000,
tx_clk,
rx_clkena,
tx_clkena,
txp,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter PHY_IDENTIFIER = 32'h 00000000; // PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation.
// Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O.
parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter ENABLE_ALT_RECONFIG = 0; // Option to expose the alt_reconfig ports
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [7:0] gmii_rx_d;
output gmii_rx_dv;
output gmii_rx_err;
output hd_ena;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output mii_col;
output mii_crs;
output [3:0] mii_rx_d;
output mii_rx_dv;
output mii_rx_err;
output pcs_pwrdn_out;
output [15:0] readdata;
output [16:0] reconfig_fromgxb;
output rx_clk;
output set_10;
output set_100;
output set_1000;
output tx_clk;
output rx_clkena;
output tx_clkena;
output txp;
output waitrequest;
input [4:0] address;
input clk;
input [7:0] gmii_tx_d;
input gmii_tx_en;
input gmii_tx_err;
input gxb_pwrdn_in;
input gxb_cal_blk_clk;
input [3:0] mii_tx_d;
input mii_tx_en;
input mii_tx_err;
input read;
input reconfig_clk;
input [3:0] reconfig_togxb;
input ref_clk;
input reset;
input reset_rx_clk;
input reset_tx_clk;
input rxp;
input write;
input [15:0] writedata;
wire PCS_rx_reset;
wire PCS_tx_reset;
wire PCS_reset;
wire gige_pma_reset;
wire [7:0] gmii_rx_d;
wire gmii_rx_dv;
wire gmii_rx_err;
wire hd_ena;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire mii_col;
wire mii_crs;
wire [3:0] mii_rx_d;
wire mii_rx_dv;
wire mii_rx_err;
wire pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire [15:0] readdata;
wire rx_char_err_gx;
wire rx_clk;
wire rx_disp_err;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire set_10;
wire set_100;
wire set_1000;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire waitrequest;
wire sd_loopback;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
reg pma_digital_rst0;
reg pma_digital_rst1;
reg pma_digital_rst2;
wire [16:0] reconfig_fromgxb;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
always @(posedge clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1)
begin
pma_digital_rst0 <= reset_rx_clk;
pma_digital_rst1 <= reset_rx_clk;
pma_digital_rst2 <= reset_rx_clk;
end
else
begin
pma_digital_rst0 <= reset_rx_clk;
pma_digital_rst1 <= pma_digital_rst0;
pma_digital_rst2 <= pma_digital_rst1;
end
end
// Assign the digital reset of the PMA to the PCS logic
// --------------------------------------------------------
assign PCS_rx_reset = pma_digital_rst2;
assign PCS_tx_reset = reset_tx_clk | pma_digital_rst2;
assign PCS_reset = reset | pma_digital_rst2;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_1000_base_x_strx_gx altera_tse_top_1000_base_x_strx_gx_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.gmii_rx_d (gmii_rx_d),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_err (gmii_rx_err),
.gmii_tx_d (gmii_tx_d),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_err (gmii_tx_err),
.hd_ena (hd_ena),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rx_d (mii_rx_d),
.mii_rx_dv (mii_rx_dv),
.mii_rx_err (mii_rx_err),
.mii_tx_d (mii_tx_d),
.mii_tx_en (mii_tx_en),
.mii_tx_err (mii_tx_err),
.powerdown (pcs_pwrdn_out_sig),
.reg_addr (address),
.reg_busy (waitrequest),
.reg_clk (clk),
.reg_data_in (writedata),
.reg_data_out (readdata),
.reg_rd (read),
.reg_wr (write),
.reset_reg_clk (PCS_reset),
.reset_rx_clk (PCS_rx_reset),
.reset_tx_clk (PCS_tx_reset),
.rx_clk (rx_clk),
.rx_clkout (pcs_clk),
.rx_frame (pcs_rx_frame),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.set_10 (set_10),
.set_100 (set_100),
.set_1000 (set_1000),
.tx_clk (tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.tx_clkout (pcs_clk),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar)
);
defparam
altera_tse_top_1000_base_x_strx_gx_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_top_1000_base_x_strx_gx_inst.DEV_VERSION = DEV_VERSION,
altera_tse_top_1000_base_x_strx_gx_inst.ENABLE_SGMII = ENABLE_SGMII;
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1)
begin
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
assign pcs_pwrdn_out = 1'b0;
end
endgenerate
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(pcs_clk),
.reset(PCS_rx_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar),
.rx_datain (rxp),
.rx_dataout (rx_frame),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err),
.rx_errdetect (rx_char_err_gx),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_runlengthviolation),
.rx_seriallpbken (sd_loopback),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (pcs_clk),
.tx_ctrlenable (tx_kchar),
.tx_datain (tx_frame),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY;
endmodule |
module altera_tse_mac_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
clk, // Avalon slave - clock
read, // Avalon slave - read
write, // Avalon slave - write
address, // Avalon slave - address
writedata, // Avalon slave - writedata
readdata, // Avalon slave - readdata
waitrequest, // Avalon slave - waitrequest
reset, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
reset_ff_rx_clk,
reset_ff_tx_clk,
ff_rx_clk, // AtlanticII source - clk
ff_rx_data, // AtlanticII source - data
ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_rx_sop, // AtlanticII source - startofpacket
ff_rx_eop, // AtlanticII source - endofpacket
rx_err, // AtlanticII source - error
rx_err_stat, // AtlanticII source - component_specific_signal(eop)
rx_frm_type, // AtlanticII source - component_specific_signal(data)
ff_rx_rdy, // AtlanticII source - ready
ff_rx_dval, // AtlanticII source - valid
ff_rx_dsav, // Will not exists in SoPC Model (leave unconnected)
ff_tx_clk, // AtlanticII sink - clk
ff_tx_data, // AtlanticII sink - data
ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_tx_sop, // AtlanticII sink - startofpacket
ff_tx_eop, // AtlanticII sink - endofpacket
ff_tx_err, // AtlanticII sink - error
ff_tx_wren, // AtlanticII sink - valid
ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
ff_tx_rdy, // AtlanticII sink - ready
ff_tx_septy, // Will not exists in SoPC Model (leave unconnected)
tx_ff_uflow, // Will not exists in SoPC Model (leave unconnected)
ff_rx_a_full,
ff_rx_a_empty,
ff_tx_a_full,
ff_tx_a_empty,
xoff_gen,
xon_gen,
magic_sleep_n,
magic_wakeup,
mdc,
mdio_in,
mdio_out,
mdio_oen,
tbi_rx_clk,
tbi_tx_clk,
tbi_rx_d,
tbi_tx_d,
sd_loopback,
powerdown,
led_col,
led_an,
led_char_err,
led_disp_err,
led_crs,
led_link
);
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // ALTERA Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input clk; // 25MHz Host Interface Clock
input read; // Register Read Strobe
input write; // Register Write Strobe
input [7:0] address; // Register Address
input [31:0] writedata; // Write Data for Host Bus
output [31:0] readdata; // Read Data to Host Bus
output waitrequest; // Interface Busy
input reset; // Asynchronous Reset
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
input ff_rx_clk; // Transmit Local Clock
output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
output [1:0] ff_rx_mod; // Data Modulo
output ff_rx_sop; // Start of Packet
output ff_rx_eop; // End of Packet
output [5:0] rx_err; // Errored Packet Indication
output [17:0] rx_err_stat; // Packet Length and Status Word
output [3:0] rx_frm_type; // Unicast Frame Indication
input ff_rx_rdy; // PHY Application Ready
output ff_rx_dval; // Data Valid Strobe
output ff_rx_dsav; // Data Available
input ff_tx_clk; // Transmit Local Clock
input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
input [1:0] ff_tx_mod; // Data Modulo
input ff_tx_sop; // Start of Packet
input ff_tx_eop; // End of Packet
input ff_tx_err; // Errored Packet
input ff_tx_wren; // Write Enable
input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
output ff_tx_rdy; // FIFO Ready
output ff_tx_septy; // FIFO has space for at least one section
output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
output ff_rx_a_full; // Receive FIFO Almost Full
output ff_rx_a_empty; // Receive FIFO Almost Empty
output ff_tx_a_full; // Transmit FIFO Almost Full
output ff_tx_a_empty; // Transmit FIFO Almost Empty
input xoff_gen; // Xoff Pause frame generate
input xon_gen; // Xon Pause frame generate
input magic_sleep_n; // Enable Sleep Mode
output magic_wakeup; // Wake Up Request
output mdc; // 2.5MHz Inteface
input mdio_in; // MDIO Input
output mdio_out; // MDIO Output
output mdio_oen; // MDIO Output Enable
input tbi_rx_clk; // 125MHz Recoved Clock
input tbi_tx_clk; // 125MHz Transmit Clock
input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
output [9:0] tbi_tx_d; // Transmit TBI Interface
output sd_loopback; // SERDES Loopback Enable
output powerdown; // Powerdown Enable
output led_crs; // Carrier Sense
output led_link; // Valid Link
output led_col; // Collision Indication
output led_an; // Auto-Negotiation Status
output led_char_err; // Character Error
output led_disp_err; // Disparity Error
wire [31:0] reg_data_out;
wire reg_busy;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire ff_rx_dval;
wire ff_rx_dsav;
wire ff_tx_rdy;
wire ff_tx_septy;
wire tx_ff_uflow;
wire magic_wakeup;
wire ff_rx_a_full;
wire ff_rx_a_empty;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire mdc;
wire mdio_out;
wire mdio_oen;
wire [9:0] tbi_tx_d;
wire sd_loopback;
wire powerdown;
wire led_crs;
wire led_link;
wire led_col;
wire led_an;
wire led_char_err;
wire led_disp_err;
wire rx_clk;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire [7:0] gm_rx_d; // GMII Receive Data
wire gm_rx_dv; // GMII Receive Frame Enable
wire gm_rx_err; // GMII Receive Frame Error
wire [7:0] gm_tx_d; // GMII Transmit Data
wire gm_tx_en; // GMII Transmit Frame Enable
wire gm_tx_err; // GMII Transmit Frame Error
wire [3:0] m_rx_d; // MII Receive Data
wire m_rx_dv; // MII Receive Frame Enable
wire m_rx_err; // MII Receive Drame Error
wire [3:0] m_tx_d; // MII Transmit Data
wire m_tx_en; // MII Transmit Frame Enable
wire m_tx_err; // MII Transmit Frame Error
wire m_rx_crs; // Carrier Sense
wire m_rx_col; // Collition
wire set_1000; // Gigabit Mode Enable
wire set_10; // 10Mbps Mode Enable
wire pcs_en;
wire [31:0]readdata_mac;
wire waitrequest_mac;
wire [31:0]readdata_pcs;
wire waitrequest_pcs;
wire write_pcs;
wire read_pcs;
wire write_mac;
wire read_mac;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
// Reset Lines
// -----------
wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
// This is done because the PCS address space is from 0x80 to 0x9F
// ---------------------------------------------------------------
assign pcs_en = address[7] & !address[6] & !address[5];
assign write_pcs = pcs_en? write : 1'b0;
assign read_pcs = pcs_en? read : 1'b0;
assign write_mac = pcs_en? 1'b0 : write;
assign read_mac = pcs_en? 1'b0 : read;
assign readdata = pcs_en? readdata_pcs : readdata_mac;
assign waitrequest = pcs_en? waitrequest_pcs : waitrequest_mac;
assign readdata_pcs[31:16] = {16{1'b0}};
// Programmable Reset Options
// --------------------------
generate if (USE_SYNC_RESET == 1)
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_rx_clk : !reset_rx_clk ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_tx_clk : !reset_tx_clk ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_rx_clk : !reset_ff_rx_clk ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_tx_clk : !reset_ff_tx_clk ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
else
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
endgenerate
// --------------------------
altera_tse_top_gen_host top_gen_host_inst(
.reset_ff_rx_clk(reset_ff_rx_clk_int),
.reset_ff_tx_clk(reset_ff_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.gm_rx_dv(gm_rx_dv),
.gm_rx_d(gm_rx_d),
.gm_rx_err(gm_rx_err),
.m_rx_en(m_rx_dv),
.m_rx_d(m_rx_d),
.m_rx_err(m_rx_err),
.m_rx_col(m_rx_col),
.m_rx_crs(m_rx_crs),
.set_1000(set_1000),
.set_10(set_10),
.ff_rx_clk(ff_rx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_tx_clk(ff_tx_clk),
.ff_tx_wren(ff_tx_wren),
.ff_tx_data(ff_tx_data),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_crc_fwd(ff_tx_crc_fwd),
.reg_clk(clk),
.reg_addr(address),
.reg_data_in(writedata),
.reg_rd(read_mac),
.reg_wr(write_mac),
.mdio_in(mdio_in),
.gm_tx_en(gm_tx_en),
.gm_tx_d(gm_tx_d),
.gm_tx_err(gm_tx_err),
.m_tx_en(m_tx_en),
.m_tx_d(m_tx_d),
.m_tx_err(m_tx_err),
.eth_mode(),
.ena_10(),
.ff_rx_dval(ff_rx_dval),
.ff_rx_data(ff_rx_data),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.ff_rx_eop(ff_rx_eop),
.ff_rx_dsav(ff_rx_dsav),
.rx_err(rx_err),
.rx_err_stat(rx_err_stat),
.rx_frm_type(rx_frm_type),
.ff_tx_rdy(ff_tx_rdy),
.ff_tx_septy(ff_tx_septy),
.tx_ff_uflow(tx_ff_uflow),
.rx_a_full(ff_rx_a_full),
.rx_a_empty(ff_rx_a_empty),
.tx_a_full(ff_tx_a_full),
.tx_a_empty(ff_tx_a_empty),
.xoff_gen(xoff_gen),
.xon_gen(xon_gen),
.reg_data_out(readdata_mac),
.reg_busy(waitrequest_mac),
.reg_sleepN(magic_sleep_n),
.reg_wakeup(magic_wakeup),
.mdc(mdc),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen));
defparam
top_gen_host_inst.EG_FIFO = EG_FIFO,
top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
top_gen_host_inst.CORE_VERSION = CORE_VERSION,
top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
top_gen_host_inst.EG_ADDR = EG_ADDR,
top_gen_host_inst.ENA_HASH = ENA_HASH,
top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
top_gen_host_inst.ING_FIFO = ING_FIFO,
top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE,
top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE,
top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE,
top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE,
top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE,
top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
top_gen_host_inst.ING_ADDR = ING_ADDR,
top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
top_gen_host_inst.CUST_VERSION = CUST_VERSION,
top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
top_gen_host_inst.INSERT_TA = INSERT_TA,
top_gen_host_inst.RAM_TYPE = RAM_TYPE,
top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
altera_tse_top_1000_base_x top_1000_base_x_inst(
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.gmii_rx_dv(gm_rx_dv),
.gmii_rx_d(gm_rx_d),
.gmii_rx_err(gm_rx_err),
.gmii_tx_en(gm_tx_en),
.gmii_tx_d(gm_tx_d),
.gmii_tx_err(gm_tx_err),
.mii_rx_dv(m_rx_dv),
.mii_rx_d(m_rx_d),
.mii_rx_err(m_rx_err),
.mii_tx_en(m_tx_en),
.mii_tx_d(m_tx_d),
.mii_tx_err(m_tx_err),
.mii_col(m_rx_col),
.mii_crs(m_rx_crs),
.tbi_rx_clk(tbi_rx_clk),
.tbi_tx_clk(tbi_tx_clk),
.tbi_rx_d(tbi_rx_d),
.tbi_tx_d(tbi_tx_d),
.sd_loopback(sd_loopback),
.reg_clk(clk),
.reg_rd(read_pcs),
.reg_wr(write_pcs),
.reg_addr(address[4:0]),
.reg_data_in(writedata[15:0]),
.reg_data_out(readdata_pcs[15:0]),
.reg_busy(waitrequest_pcs),
.powerdown(powerdown),
.set_10(set_10),
.set_100(),
.set_1000(set_1000),
.hd_ena(),
.led_col(led_col),
.led_an(led_an),
.led_char_err(led_char_err),
.led_disp_err(led_disp_err),
.led_crs(led_crs),
.led_link(led_link));
defparam
top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule |
module altera_tse_mac_pcs_pma_gige /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
gxb_cal_blk_clk,
gxb_pwrdn_in,
magic_sleep_n,
mdio_in,
read,
reconfig_clk,
reconfig_togxb,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
pcs_pwrdn_out,
readdata,
reconfig_fromgxb,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output pcs_pwrdn_out;
output [31: 0] readdata;
output [16:0] reconfig_fromgxb;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input gxb_cal_blk_clk;
input gxb_pwrdn_in;
input magic_sleep_n;
input mdio_in;
input read;
input reconfig_clk;
input [3:0] reconfig_togxb;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
wire MAC_PCS_reset;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire gige_pma_reset;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire rx_char_err_gx;
wire rx_disp_err;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire sd_loopback;
wire tx_ff_uflow;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire waitrequest;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_carrierdetected;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
reg pma_digital_rst0;
reg pma_digital_rst1;
reg pma_digital_rst2;
wire [16:0] reconfig_fromgxb;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
always @(posedge clk or posedge reset)
begin
if (reset == 1)
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= reset;
pma_digital_rst2 <= reset;
end
else
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= pma_digital_rst0;
pma_digital_rst2 <= pma_digital_rst1;
end
end
// Assign the digital reset of the PMA to the MAC_PCS logic
// --------------------------------------------------------
assign MAC_PCS_reset = pma_digital_rst2;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_strx_gx_ena altera_tse_mac_pcs_pma_strx_gx_ena_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (MAC_PCS_reset),
.rx_clkout (pcs_clk),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frame (pcs_rx_frame),
.rx_frm_type (rx_frm_type),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.tx_clkout (pcs_clk),
.tx_ff_uflow (tx_ff_uflow),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1)
begin
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
assign pcs_pwrdn_out = 1'b0;
end
endgenerate
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(pcs_clk),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar),
.rx_datain (rxp),
.rx_dataout (rx_frame),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err),
.rx_errdetect (rx_char_err_gx),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_runlengthviolation),
.rx_seriallpbken (sd_loopback),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (pcs_clk),
.tx_ctrlenable (tx_kchar),
.tx_datain (tx_frame),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY;
endmodule |
module altera_tse_pma_lvds_rx (
rx_in,
rx_inclock,
rx_reset,
rx_divfwdclk,
rx_out,
rx_outclock);
input [0:0] rx_in;
input rx_inclock;
input [0:0] rx_reset;
output [0:0] rx_divfwdclk;
output [9:0] rx_out;
output rx_outclock;
wire [0:0] sub_wire0;
wire [9:0] sub_wire1;
wire sub_wire2;
wire [0:0] rx_divfwdclk = sub_wire0[0:0];
wire [9:0] rx_out = sub_wire1[9:0];
wire rx_outclock = sub_wire2;
altlvds_rx altlvds_rx_component (
.rx_inclock (rx_inclock),
.rx_reset (rx_reset),
.rx_in (rx_in),
.rx_divfwdclk (sub_wire0),
.rx_out (sub_wire1),
.rx_outclock (sub_wire2),
.pll_areset (1'b0),
.rx_cda_max (),
.rx_cda_reset (1'b0),
.rx_channel_data_align (1'b0),
.rx_coreclk (1'b1),
.rx_data_align (1'b0),
.rx_deskew (1'b0),
.rx_dpa_locked (),
.rx_dpll_enable (1'b1),
.rx_dpll_hold (1'b0),
.rx_dpll_reset (1'b0),
.rx_enable (1'b1),
.rx_fifo_reset (1'b0),
.rx_locked (),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_syncclock (1'b0));
defparam
altlvds_rx_component.common_rx_tx_pll = "ON",
altlvds_rx_component.deserialization_factor = 10,
altlvds_rx_component.enable_dpa_mode = "ON",
altlvds_rx_component.enable_soft_cdr_mode = "ON",
altlvds_rx_component.implement_in_les = "OFF",
altlvds_rx_component.inclock_period = 8000,
altlvds_rx_component.input_data_rate = 1250,
altlvds_rx_component.intended_device_family = "Stratix III",
altlvds_rx_component.lpm_type = "altlvds_rx",
altlvds_rx_component.number_of_channels = 1,
altlvds_rx_component.outclock_resource = "AUTO",
altlvds_rx_component.registered_output = "ON",
altlvds_rx_component.use_external_pll = "OFF",
altlvds_rx_component.enable_dpa_align_to_rising_edge_only = "OFF",
altlvds_rx_component.enable_dpa_initial_phase_selection = "OFF";
endmodule |
module altera_tse_rgmii_out4 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [3:0] datain_h;
input [3:0] datain_l;
input outclock;
output [3:0] dataout;
wire [3:0] sub_wire0;
wire [3:0] dataout = sub_wire0[3:0];
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (datain_h),
.aclr (aclr),
.datain_l (datain_l),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Stratix II",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 4;
endmodule |
module altera_tse_rgmii_in1 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input datain;
input inclock;
output dataout_h;
output dataout_l;
wire [0:0] sub_wire0;
wire [0:0] sub_wire2;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout_h = sub_wire1;
wire [0:0] sub_wire3 = sub_wire2[0:0];
wire dataout_l = sub_wire3;
wire sub_wire4 = datain;
wire sub_wire5 = sub_wire4;
altddio_in altddio_in_component (
.datain (sub_wire5),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire2),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 1;
endmodule |
module altera_tse_pcs_pma /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
gmii_tx_d,
gmii_tx_en,
gmii_tx_err,
gxb_cal_blk_clk,
gxb_pwrdn_in,
mii_tx_d,
mii_tx_en,
mii_tx_err,
read,
ref_clk,
reset,
reset_rx_clk,
reset_tx_clk,
rxp,
write,
writedata,
// outputs:
gmii_rx_d,
gmii_rx_dv,
gmii_rx_err,
hd_ena,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
mii_col,
mii_crs,
mii_rx_d,
mii_rx_dv,
mii_rx_err,
pcs_pwrdn_out,
readdata,
rx_clk,
rx_clkena,
tx_clkena,
set_10,
set_100,
set_1000,
tx_clk,
txp,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter PHY_IDENTIFIER = 32'h 00000000; // PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b1; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [7:0] gmii_rx_d;
output gmii_rx_dv;
output gmii_rx_err;
output hd_ena;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output mii_col;
output mii_crs;
output [3:0] mii_rx_d;
output mii_rx_dv;
output mii_rx_err;
output pcs_pwrdn_out;
output [15:0] readdata;
output rx_clk;
output set_10;
output set_100;
output set_1000;
output tx_clk;
output rx_clkena;
output tx_clkena;
output txp;
output waitrequest;
input [4:0] address;
input clk;
input [7:0] gmii_tx_d;
input gmii_tx_en;
input gmii_tx_err;
input gxb_pwrdn_in;
input gxb_cal_blk_clk;
input [3:0] mii_tx_d;
input mii_tx_en;
input mii_tx_err;
input read;
input ref_clk;
input reset;
input reset_rx_clk;
input reset_tx_clk;
input rxp;
input write;
input [15:0] writedata;
wire PCS_rx_reset;
wire PCS_tx_reset;
wire PCS_reset;
wire [7:0] gmii_rx_d;
wire gmii_rx_dv;
wire gmii_rx_err;
wire hd_ena;
wire led_an;
wire led_char_err;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire mii_col;
wire mii_crs;
wire [3:0] mii_rx_d;
wire mii_rx_dv;
wire mii_rx_err;
wire [15:0] readdata;
wire rx_clk;
wire set_10;
wire set_100;
wire set_1000;
wire tbi_rx_clk;
wire [9:0] tbi_rx_d;
wire [9:0] tbi_tx_d;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire txp;
wire waitrequest;
wire sd_loopback;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire [9:0] tbi_rx_d_lvds;
reg pma_digital_rst0;
reg pma_digital_rst1;
reg pma_digital_rst2;
reg [9:0] tbi_rx_d_flip;
reg [9:0] tbi_tx_d_flip;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
always @(posedge clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1)
begin
pma_digital_rst0 <= reset_rx_clk;
pma_digital_rst1 <= reset_rx_clk;
pma_digital_rst2 <= reset_rx_clk;
end
else
begin
pma_digital_rst0 <= reset_rx_clk;
pma_digital_rst1 <= pma_digital_rst0;
pma_digital_rst2 <= pma_digital_rst1;
end
end
// Assign the digital reset of the PMA to the PCS logic
// --------------------------------------------------------
assign PCS_rx_reset = pma_digital_rst2;
assign PCS_tx_reset = reset_tx_clk | pma_digital_rst2;
assign PCS_reset = reset | pma_digital_rst2;
// Instantiation of the PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_1000_base_x altera_tse_top_1000_base_x_inst
(
.gmii_rx_d (gmii_rx_d),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_err (gmii_rx_err),
.gmii_tx_d (gmii_tx_d),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_err (gmii_tx_err),
.hd_ena (hd_ena),
.led_an (led_an),
.led_char_err (led_char_err),
.led_col (led_col),
.led_crs (led_crs),
.led_disp_err (led_disp_err),
.led_link (led_link),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rx_d (mii_rx_d),
.mii_rx_dv (mii_rx_dv),
.mii_rx_err (mii_rx_err),
.mii_tx_d (mii_tx_d),
.mii_tx_en (mii_tx_en),
.mii_tx_err (mii_tx_err),
.reg_addr (address),
.reg_busy (waitrequest),
.reg_clk (clk),
.reg_data_in (writedata),
.reg_data_out (readdata),
.reg_rd (read),
.reg_wr (write),
.reset_reg_clk (PCS_reset),
.reset_rx_clk (PCS_rx_reset),
.reset_tx_clk (PCS_tx_reset),
.rx_clk (rx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.set_10 (set_10),
.set_100 (set_100),
.set_1000 (set_1000),
.sd_loopback(sd_loopback),
.powerdown(pcs_pwrdn_out_sig),
.tbi_rx_clk (tbi_rx_clk),
.tbi_rx_d (tbi_rx_d),
.tbi_tx_clk (tbi_tx_clk),
.tbi_tx_d (tbi_tx_d),
.tx_clk (tx_clk)
);
defparam
altera_tse_top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
altera_tse_top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1)
begin
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
assign pcs_pwrdn_out = 1'b0;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the Alt2gxb block as the PMA for Stratix II GX devices
// -----------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0)
begin
altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.rx_analogreset (reset_rx_clk),
.rx_clkout (tbi_rx_clk),
.rx_cruclk (ref_clk),
.rx_datain (rxp),
.rx_dataout (tbi_rx_d),
.rx_digitalreset (pma_digital_rst2),
.rx_patterndetect (),
.rx_seriallpbken (sd_loopback),
.tx_clkout (tbi_tx_clk),
.tx_datain (tbi_tx_d),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2)
);
end
endgenerate
// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
// ----------------------------------------------------------------
generate if (DEVICE_FAMILY == "ARRIAGX")
begin
altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.rx_analogreset (reset_rx_clk),
.rx_clkout (tbi_rx_clk),
.rx_cruclk (ref_clk),
.rx_datain (rxp),
.rx_dataout (tbi_rx_d),
.rx_digitalreset (pma_digital_rst2),
.rx_patterndetect (),
.rx_seriallpbken (sd_loopback),
.tx_clkout (tbi_tx_clk),
.tx_datain (tbi_tx_d),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2)
);
end
endgenerate
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1)
begin
assign tbi_tx_clk = ref_clk;
assign tbi_rx_d = tbi_rx_d_flip;
always @(posedge tbi_rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1)
tbi_rx_d_flip <= 0;
else
begin
tbi_rx_d_flip[0] <= tbi_rx_d_lvds[9];
tbi_rx_d_flip[1] <= tbi_rx_d_lvds[8];
tbi_rx_d_flip[2] <= tbi_rx_d_lvds[7];
tbi_rx_d_flip[3] <= tbi_rx_d_lvds[6];
tbi_rx_d_flip[4] <= tbi_rx_d_lvds[5];
tbi_rx_d_flip[5] <= tbi_rx_d_lvds[4];
tbi_rx_d_flip[6] <= tbi_rx_d_lvds[3];
tbi_rx_d_flip[7] <= tbi_rx_d_lvds[2];
tbi_rx_d_flip[8] <= tbi_rx_d_lvds[1];
tbi_rx_d_flip[9] <= tbi_rx_d_lvds[0];
end
end
always @(posedge ref_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1)
tbi_tx_d_flip <= 0;
else
begin
tbi_tx_d_flip[0] <= tbi_tx_d[9];
tbi_tx_d_flip[1] <= tbi_tx_d[8];
tbi_tx_d_flip[2] <= tbi_tx_d[7];
tbi_tx_d_flip[3] <= tbi_tx_d[6];
tbi_tx_d_flip[4] <= tbi_tx_d[5];
tbi_tx_d_flip[5] <= tbi_tx_d[4];
tbi_tx_d_flip[6] <= tbi_tx_d[3];
tbi_tx_d_flip[7] <= tbi_tx_d[2];
tbi_tx_d_flip[8] <= tbi_tx_d[1];
tbi_tx_d_flip[9] <= tbi_tx_d[0];
end
end
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx
(
.rx_divfwdclk (tbi_rx_clk),
.rx_in (rxp),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds),
.rx_outclock (),
.rx_reset (reset_rx_clk)
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx
(
.tx_in (tbi_tx_d_flip),
.tx_inclock (ref_clk),
.tx_out (txp)
);
end
endgenerate
endmodule |
module altera_tse_rgmii_out1 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input datain_h;
input datain_l;
input outclock;
output dataout;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout = sub_wire1;
wire sub_wire2 = datain_h;
wire sub_wire3 = sub_wire2;
wire sub_wire4 = datain_l;
wire sub_wire5 = sub_wire4;
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (sub_wire3),
.aclr (aclr),
.datain_l (sub_wire5),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Stratix II",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 1;
endmodule |
module altera_tse_alt4gxb_gige (
cal_blk_clk,
fixedclk,
fixedclk_fast,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
reconfig_fromgxb,
rx_clkout,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout)/* synthesis synthesis_clearbox = 1 */;
input cal_blk_clk;
input fixedclk;
input [5:0] fixedclk_fast;
input [0:0] gxb_powerdown;
input pll_inclk;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] rx_seriallpbken;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [16:0] reconfig_fromgxb;
output rx_clkout;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_patterndetect;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
endmodule |
module altera_tse_gxb_gige_inst (
cal_blk_clk,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_rlv,
rx_syncstatus,
tx_clkout,
tx_dataout,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp
);
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter STARTING_CHANNEL_NUMBER = 0;
parameter ENABLE_ALT_RECONFIG = 0;
input cal_blk_clk;
input gxb_powerdown;
input pll_inclk;
input reconfig_clk;
input [3:0] reconfig_togxb;
input rx_analogreset;
input rx_cruclk;
input rx_datain;
input rx_digitalreset;
input rx_seriallpbken;
input tx_ctrlenable;
input [7:0] tx_datain;
input tx_digitalreset;
output [16:0] reconfig_fromgxb;
output rx_ctrldetect;
output [7:0] rx_dataout;
output rx_disperr;
output rx_errdetect;
output rx_patterndetect;
output rx_rlv;
output rx_syncstatus;
output tx_clkout;
output tx_dataout;
output rx_rmfifodatadeleted;
output rx_rmfifodatainserted;
output rx_runningdisp;
wire [16:0] reconfig_fromgxb;
wire [2:0] reconfig_togxb_alt2gxb;
wire reconfig_fromgxb_alt2gxb;
wire wire_reconfig_clk;
wire [3:0] wire_reconfig_togxb;
(* altera_attribute = "-name MESSAGE_DISABLE 10036" *)
wire [16:0] wire_reconfig_fromgxb;
generate if (ENABLE_ALT_RECONFIG == 0)
begin
assign wire_reconfig_clk = 1'b0;
assign wire_reconfig_togxb = 4'b0010;
assign reconfig_fromgxb = {17{1'b0}};
end
else
begin
assign wire_reconfig_clk = reconfig_clk;
assign wire_reconfig_togxb = reconfig_togxb;
assign reconfig_fromgxb = wire_reconfig_fromgxb;
end
endgenerate
generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX")
begin
altera_tse_alt2gxb_gige the_altera_tse_alt2gxb_gige
(
.cal_blk_clk (cal_blk_clk),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(reconfig_togxb_alt2gxb),
.reconfig_fromgxb(reconfig_fromgxb_alt2gxb),
.rx_analogreset (rx_analogreset),
.rx_cruclk (rx_cruclk),
.rx_ctrldetect (rx_ctrldetect),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_seriallpbken (rx_seriallpbken),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_alt2gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER,
the_altera_tse_alt2gxb_gige.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG;
assign reconfig_togxb_alt2gxb = wire_reconfig_togxb[2:0];
assign wire_reconfig_fromgxb = {{16{1'b0}}, reconfig_fromgxb_alt2gxb};
end
endgenerate
generate if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGX")
begin
altera_tse_alt4gxb_gige the_altera_tse_alt4gxb_gige
(
.cal_blk_clk (cal_blk_clk),
.fixedclk(wire_reconfig_clk),
.fixedclk_fast(1'b0),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(wire_reconfig_togxb),
.reconfig_fromgxb(wire_reconfig_fromgxb),
.rx_analogreset (rx_analogreset),
.rx_cruclk (rx_cruclk),
.rx_ctrldetect (rx_ctrldetect),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_seriallpbken (rx_seriallpbken),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_alt4gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER;
end
endgenerate
generate if ( DEVICE_FAMILY == "CYCLONEIVGX")
begin
altera_tse_altgx_civgx_gige the_altera_tse_alt_gx_civgx
(
.cal_blk_clk (cal_blk_clk),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(wire_reconfig_togxb),
.rx_analogreset (rx_analogreset),
.rx_ctrldetect (rx_ctrldetect),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.reconfig_fromgxb(wire_reconfig_fromgxb[4:0]),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_alt_gx_civgx.starting_channel_number = STARTING_CHANNEL_NUMBER;
end
endgenerate
endmodule |
module altera_tse_alt2gxb_gige (
cal_blk_clk,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout);
input cal_blk_clk;
input [0:0] gxb_powerdown;
input pll_inclk;
input reconfig_clk;
input [2:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] rx_seriallpbken;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] reconfig_fromgxb;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_patterndetect;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
// Please this parameter and the section that use it when this module is regenerated
parameter ENABLE_ALT_RECONFIG = 1;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [0:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire [0:0] sub_wire8;
wire [0:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [7:0] sub_wire12;
wire [0:0] rx_disperr = sub_wire0[0:0];
wire [0:0] rx_rlv = sub_wire1[0:0];
wire [0:0] rx_patterndetect = sub_wire2[0:0];
wire [0:0] rx_ctrldetect = sub_wire3[0:0];
wire [0:0] rx_errdetect = sub_wire4[0:0];
wire [0:0] rx_rmfifodatadeleted = sub_wire5[0:0];
wire [0:0] rx_runningdisp = sub_wire6[0:0];
wire [0:0] tx_dataout = sub_wire7[0:0];
wire [0:0] rx_rmfifodatainserted = sub_wire8[0:0];
wire [0:0] rx_syncstatus = sub_wire9[0:0];
wire [0:0] tx_clkout = sub_wire10[0:0];
wire [0:0] reconfig_fromgxb = sub_wire11[0:0];
wire [7:0] rx_dataout = sub_wire12[7:0];
alt2gxb alt2gxb_component (
.pll_inclk (pll_inclk),
.gxb_powerdown (gxb_powerdown),
.tx_datain (tx_datain),
.rx_cruclk (rx_cruclk),
.cal_blk_clk (cal_blk_clk),
.reconfig_clk (reconfig_clk),
.rx_seriallpbken (rx_seriallpbken),
.rx_datain (rx_datain),
.reconfig_togxb (reconfig_togxb),
.tx_ctrlenable (tx_ctrlenable),
.rx_analogreset (rx_analogreset),
.rx_digitalreset (rx_digitalreset),
.tx_digitalreset (tx_digitalreset),
.rx_disperr (sub_wire0),
.rx_rlv (sub_wire1),
.rx_patterndetect (sub_wire2),
.rx_ctrldetect (sub_wire3),
.rx_errdetect (sub_wire4),
.rx_rmfifodatadeleted (sub_wire5),
.rx_runningdisp (sub_wire6),
.tx_dataout (sub_wire7),
.rx_rmfifodatainserted (sub_wire8),
.rx_syncstatus (sub_wire9),
.tx_clkout (sub_wire10),
.reconfig_fromgxb (sub_wire11),
.rx_dataout (sub_wire12)
// synopsys translate_off
,
.aeq_fromgxb (),
.aeq_togxb (),
.cal_blk_calibrationstatus (),
.cal_blk_powerdown (),
.coreclkout (),
.debug_rx_phase_comp_fifo_error (),
.debug_tx_phase_comp_fifo_error (),
.fixedclk (),
.gxb_enable (),
.pipe8b10binvpolarity (),
.pipedatavalid (),
.pipeelecidle (),
.pipephydonestatus (),
.pipestatus (),
.pll_inclk_alt (),
.pll_inclk_rx_cruclk (),
.pll_locked (),
.pll_locked_alt (),
.powerdn (),
.reconfig_fromgxb_oe (),
.rx_a1a2size (),
.rx_a1a2sizeout (),
.rx_a1detect (),
.rx_a2detect (),
.rx_bistdone (),
.rx_bisterr (),
.rx_bitslip (),
.rx_byteorderalignstatus (),
.rx_channelaligned (),
.rx_clkout (),
.rx_coreclk (),
.rx_cruclk_alt (),
.rx_dataoutfull (),
.rx_enabyteord (),
.rx_enapatternalign (),
.rx_freqlocked (),
.rx_invpolarity (),
.rx_k1detect (),
.rx_k2detect (),
.rx_locktodata (),
.rx_locktorefclk (),
.rx_phfifooverflow (),
.rx_phfifordenable (),
.rx_phfiforeset (),
.rx_phfifounderflow (),
.rx_phfifowrdisable (),
.rx_pll_locked (),
.rx_powerdown (),
.rx_recovclkout (),
.rx_revbitorderwa (),
.rx_revbyteorderwa (),
.rx_rmfifoalmostempty (),
.rx_rmfifoalmostfull (),
.rx_rmfifoempty (),
.rx_rmfifofull (),
.rx_rmfifordena (),
.rx_rmfiforeset (),
.rx_rmfifowrena (),
.rx_signaldetect (),
.tx_coreclk (),
.tx_datainfull (),
.tx_detectrxloop (),
.tx_dispval (),
.tx_forcedisp (),
.tx_forcedispcompliance (),
.tx_forceelecidle (),
.tx_invpolarity (),
.tx_phfifooverflow (),
.tx_phfiforeset (),
.tx_phfifounderflow (),
.tx_revparallellpbken ()
// synopsys translate_on
);
defparam
alt2gxb_component.starting_channel_number = starting_channel_number,
alt2gxb_component.cmu_pll_inclock_period = 8000,
alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
alt2gxb_component.digitalreset_port_width = 1,
alt2gxb_component.en_local_clk_div_ctrl = "true",
alt2gxb_component.equalizer_ctrl_a_setting = 0,
alt2gxb_component.equalizer_ctrl_b_setting = 0,
alt2gxb_component.equalizer_ctrl_c_setting = 0,
alt2gxb_component.equalizer_ctrl_d_setting = 0,
alt2gxb_component.equalizer_ctrl_v_setting = 0,
alt2gxb_component.equalizer_dcgain_setting = 0,
alt2gxb_component.gen_reconfig_pll = "false",
alt2gxb_component.intended_device_family = "Stratix II GX",
alt2gxb_component.loopback_mode = "slb",
alt2gxb_component.lpm_type = "alt2gxb",
alt2gxb_component.number_of_channels = 1,
alt2gxb_component.operation_mode = "duplex",
alt2gxb_component.pll_legal_multiplier_list = "disable_4_5_mult_above_3125",
alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
alt2gxb_component.protocol = "gige",
alt2gxb_component.receiver_termination = "oct_100_ohms",
alt2gxb_component.reconfig_dprio_mode = ENABLE_ALT_RECONFIG,
alt2gxb_component.reverse_loopback_mode = "none",
alt2gxb_component.rx_8b_10b_compatibility_mode = "true",
alt2gxb_component.rx_8b_10b_mode = "normal",
alt2gxb_component.rx_align_pattern = "0101111100",
alt2gxb_component.rx_align_pattern_length = 10,
alt2gxb_component.rx_allow_align_polarity_inversion = "false",
alt2gxb_component.rx_allow_pipe_polarity_inversion = "false",
alt2gxb_component.rx_bandwidth_mode = 1,
alt2gxb_component.rx_bitslip_enable = "false",
alt2gxb_component.rx_byte_ordering_mode = "none",
alt2gxb_component.rx_channel_width = 8,
alt2gxb_component.rx_common_mode = "0.9v",
alt2gxb_component.rx_cru_inclock_period = 8000,
alt2gxb_component.rx_cru_pre_divide_by = 1,
alt2gxb_component.rx_datapath_protocol = "basic",
alt2gxb_component.rx_data_rate = 1250,
alt2gxb_component.rx_data_rate_remainder = 0,
alt2gxb_component.rx_disable_auto_idle_insertion = "true",
alt2gxb_component.rx_enable_bit_reversal = "false",
alt2gxb_component.rx_enable_lock_to_data_sig = "false",
alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
alt2gxb_component.rx_enable_self_test_mode = "false",
alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
alt2gxb_component.rx_force_signal_detect = "true",
alt2gxb_component.rx_ppmselect = 32,
alt2gxb_component.rx_rate_match_back_to_back = "true",
alt2gxb_component.rx_rate_match_fifo_mode = "normal",
alt2gxb_component.rx_rate_match_ordered_set_based = "true",
alt2gxb_component.rx_rate_match_pattern1 = "10100010010101111100",
alt2gxb_component.rx_rate_match_pattern2 = "10101011011010000011",
alt2gxb_component.rx_rate_match_pattern_size = 20,
alt2gxb_component.rx_rate_match_skip_set_based = "true",
alt2gxb_component.rx_run_length = 5,
alt2gxb_component.rx_run_length_enable = "true",
alt2gxb_component.rx_signal_detect_threshold = 2,
alt2gxb_component.rx_use_align_state_machine = "true",
alt2gxb_component.rx_use_clkout = "false",
alt2gxb_component.rx_use_coreclk = "false",
alt2gxb_component.rx_use_cruclk = "true",
alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
alt2gxb_component.rx_use_deskew_fifo = "false",
alt2gxb_component.rx_use_double_data_mode = "false",
alt2gxb_component.rx_use_rate_match_pattern1_only = "false",
alt2gxb_component.transmitter_termination = "oct_100_ohms",
alt2gxb_component.tx_8b_10b_compatibility_mode = "true",
alt2gxb_component.tx_8b_10b_mode = "normal",
alt2gxb_component.tx_allow_polarity_inversion = "false",
alt2gxb_component.tx_analog_power = "1.5v",
alt2gxb_component.tx_channel_width = 8,
alt2gxb_component.tx_common_mode = "0.6v",
alt2gxb_component.tx_data_rate = 1250,
alt2gxb_component.tx_data_rate_remainder = 0,
alt2gxb_component.tx_enable_bit_reversal = "false",
alt2gxb_component.tx_enable_idle_selection = "true",
alt2gxb_component.tx_enable_self_test_mode = "false",
alt2gxb_component.tx_refclk_divide_by = 1,
alt2gxb_component.tx_transmit_protocol = "basic",
alt2gxb_component.tx_use_coreclk = "false",
alt2gxb_component.tx_use_double_data_mode = "false",
alt2gxb_component.tx_use_serializer_double_data_mode = "false",
alt2gxb_component.use_calibration_block = "true",
alt2gxb_component.vod_ctrl_setting = 3;
endmodule |
module altera_tse_pma_lvds_tx (
tx_in,
tx_inclock,
tx_out);
input [9:0] tx_in;
input tx_inclock;
output [0:0] tx_out;
wire [0:0] sub_wire0;
wire [0:0] tx_out = sub_wire0[0:0];
altlvds_tx altlvds_tx_component (
.tx_in (tx_in),
.tx_inclock (tx_inclock),
.tx_out (sub_wire0),
.pll_areset (1'b0),
.sync_inclock (1'b0),
.tx_coreclock (),
.tx_enable (1'b1),
.tx_locked (),
.tx_outclock (),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
defparam
altlvds_tx_component.common_rx_tx_pll = "ON",
altlvds_tx_component.deserialization_factor = 10,
altlvds_tx_component.implement_in_les = "OFF",
altlvds_tx_component.inclock_data_alignment = "UNUSED",
altlvds_tx_component.inclock_period = 8000,
altlvds_tx_component.inclock_phase_shift = 0,
altlvds_tx_component.intended_device_family = "Stratix III",
altlvds_tx_component.lpm_type = "altlvds_tx",
altlvds_tx_component.number_of_channels = 1,
altlvds_tx_component.outclock_resource = "AUTO",
altlvds_tx_component.output_data_rate = 1250,
altlvds_tx_component.registered_input = "TX_CLKIN",
altlvds_tx_component.use_external_pll = "OFF";
endmodule |
module altera_tse_rgmii_module ( // new ports to cater for mii with RGMII interface are added
// inputs
rgmii_in,
speed,
//data
gm_tx_d,
m_tx_d,
//control
gm_tx_en,
m_tx_en,
gm_tx_err,
m_tx_err,
reset_rx_clk,
reset_tx_clk,
rx_clk,
rx_control,
tx_clk,
// outputs:
rgmii_out,
gm_rx_d,
m_rx_d,
gm_rx_dv,
m_rx_en,
gm_rx_err,
m_rx_err,
m_rx_col,
m_rx_crs,
tx_control
)
;
output [ 3: 0] rgmii_out;
output [ 7: 0] gm_rx_d;
output [ 3: 0] m_rx_d;
output gm_rx_dv;
output m_rx_en;
output gm_rx_err;
output m_rx_err;
output m_rx_col;
output m_rx_crs;
output tx_control;
input [ 3: 0] rgmii_in;
input speed;
input [ 7: 0] gm_tx_d;
input [ 3: 0] m_tx_d;
input gm_tx_en;
input m_tx_en;
input gm_tx_err;
input m_tx_err;
input reset_rx_clk;
input reset_tx_clk;
input rx_clk;
input rx_control;
input tx_clk;
wire [ 3: 0] rgmii_out;
wire [ 7: 0] gm_rx_d;
wire gm_rx_dv;
wire m_rx_en;
wire gm_rx_err;
wire m_rx_err;
reg m_rx_col;
reg m_rx_crs;
reg rx_dv;
reg rx_err;
wire tx_control;
//wire tx_err;
reg [ 7: 0] rgmii_out_4_wire;
reg rgmii_out_1_wire_inp1;
reg rgmii_out_1_wire_inp2;
wire [ 7:0 ] rgmii_in_4_wire;
reg [ 7:0 ] rgmii_in_4_reg;
reg [ 7:0 ] rgmii_in_4_temp_reg;
wire [ 1:0 ] rgmii_in_1_wire;
reg [ 1:0 ] rgmii_in_1_temp_reg;
reg m_tx_en_reg1;
reg m_tx_en_reg2;
reg m_tx_en_reg3;
reg m_tx_en_reg4;
assign gm_rx_d = rgmii_in_4_reg;
assign m_rx_d = rgmii_in_4_reg[3:0]; // mii is only 4 bits, data are duplicated so we only take one nibble
altera_tse_rgmii_in4 the_rgmii_in4
(
.aclr (reset_rx_clk), //INPUT
.datain (rgmii_in), //INPUT
.dataout_h (rgmii_in_4_wire[7 : 4]), //OUTPUT
.dataout_l (rgmii_in_4_wire[3 : 0]), //OUTPUT
.inclock (rx_clk) //OUTPUT
);
altera_tse_rgmii_in1 the_rgmii_in1
(
.aclr (reset_rx_clk), //INPUT
.datain (rx_control), //INPUT
.dataout_h (rgmii_in_1_wire[1]), //INPUT rx_err
.dataout_l (rgmii_in_1_wire[0]), //OUTPUT rx_dv
.inclock (rx_clk) //OUTPUT
);
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_temp_reg <= {8{1'b0}};
rgmii_in_1_temp_reg <= {2{1'b0}};
end
else begin
rgmii_in_4_temp_reg <= rgmii_in_4_wire;
rgmii_in_1_temp_reg <= rgmii_in_1_wire;
end
end
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_reg <= {8{1'b0}};
rx_err <= 1'b0;
rx_dv <= 1'b0;
end
else begin
rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
rx_err <= rgmii_in_1_wire[0];
rx_dv <= rgmii_in_1_temp_reg[1];
end
end
always @(rx_dv or rx_err or rgmii_in_4_reg)
begin
m_rx_crs = 1'b0;
if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
begin
m_rx_crs = 1'b1; // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
end
end
always @(posedge tx_clk or posedge reset_tx_clk)
begin
if(reset_tx_clk == 1'b1)
begin
m_tx_en_reg1 <= 1'b0;
m_tx_en_reg2 <= 1'b0;
m_tx_en_reg3 <= 1'b0;
m_tx_en_reg4 <= 1'b0;
end
else
begin
m_tx_en_reg1 <= m_tx_en;
m_tx_en_reg2 <= m_tx_en_reg1;
m_tx_en_reg3 <= m_tx_en_reg2;
m_tx_en_reg4 <= m_tx_en_reg3;
end
end
always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
begin
m_rx_col = 1'b0;
if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
begin
m_rx_col = 1'b1;
end
end
assign gm_rx_err = rx_err ^ rx_dv;
assign gm_rx_dv = rx_dv;
assign m_rx_err = rx_err ^ rx_dv;
assign m_rx_en = rx_dv;
// mux for Out 4
always @(*)
begin
case (speed)
1'b1: rgmii_out_4_wire = gm_tx_d;
1'b0: rgmii_out_4_wire = {m_tx_d,m_tx_d};
endcase
end
// mux for Out 1
always @(*)
begin
case (speed)
1'b1:
begin
rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
end
1'b0:
begin
rgmii_out_1_wire_inp1 = m_tx_en;
rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
end
endcase
end
altera_tse_rgmii_out4 the_rgmii_out4
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_4_wire[3 : 0]), //INPUT
.datain_l (rgmii_out_4_wire[7 : 4]), //INPUT
.dataout (rgmii_out), //INPUT
.outclock (tx_clk) //OUTPUT
);
//assign tx_err = gm_tx_en ^ gm_tx_err;
altera_tse_rgmii_out1 the_rgmii_out1
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_1_wire_inp1), //INPUT
.datain_l (rgmii_out_1_wire_inp2), //INPUT
.dataout (tx_control), //INPUT
.outclock (tx_clk) //OUTPUT
);
endmodule |
module altera_tse_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
reg_clk, // Avalon slave - clock
reg_rd, // Avalon slave - read
reg_wr, // Avalon slave - write
reg_addr, // Avalon slave - address
reg_data_in, // Avalon slave - writedata
reg_data_out, // Avalon slave - readdata
reg_busy, // Avalon slave - waitrequest
reset_reg_clk, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
rx_clk,
tx_clk,
rx_clkena,
tx_clkena,
gmii_rx_dv,
gmii_rx_d,
gmii_rx_err,
gmii_tx_en,
gmii_tx_d,
gmii_tx_err,
mii_rx_dv,
mii_rx_d,
mii_rx_err,
mii_tx_en,
mii_tx_d,
mii_tx_err,
mii_col,
mii_crs,
tbi_rx_clk,
tbi_tx_clk,
tbi_rx_d,
tbi_tx_d,
sd_loopback,
powerdown,
set_10,
set_100,
set_1000,
hd_ena,
led_col,
led_an,
led_char_err,
led_disp_err,
led_crs,
led_link);
parameter PHY_IDENTIFIER = 32'h 00000000 ;
parameter DEV_VERSION = 16'h 0001 ;
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_reg_clk; // Asynchronous Reset - clk Domain
output rx_clk; // MAC Receive clock
output tx_clk; // MAC Transmit clock
output rx_clkena; // MAC Receive Clock Enable
output tx_clkena; // MAC Transmit Clock Enable
output gmii_rx_dv; // GMII Receive Enable
output [7:0] gmii_rx_d; // GMII Receive Data
output gmii_rx_err; // GMII Receive Error
input gmii_tx_en; // GMII Transmit Enable
input [7:0] gmii_tx_d; // GMII Transmit Data
input gmii_tx_err; // GMII Transmit Error
output mii_rx_dv; // MII Receive Enable
output [3:0] mii_rx_d; // MII Receive Data
output mii_rx_err; // MII Receive Error
input mii_tx_en; // MII Transmit Enable
input [3:0] mii_tx_d; // MII Transmit Data
input mii_tx_err; // MII Transmit Error
output mii_col; // MII Collision
output mii_crs; // MII Carrier Sense
input tbi_rx_clk; // 125MHz Recoved Clock
input tbi_tx_clk; // 125MHz Transmit Clock
input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
output [9:0] tbi_tx_d; // Transmit TBI Interface
output sd_loopback; // SERDES Loopback Enable
output powerdown; // Powerdown Enable
input reg_clk; // Register Interface Clock
input reg_rd; // Register Read Enable
input reg_wr; // Register Write Enable
input [4:0] reg_addr; // Register Address
input [15:0] reg_data_in; // Register Input Data
output [15:0] reg_data_out; // Register Output Data
output reg_busy; // Access Busy
output led_crs; // Carrier Sense
output led_link; // Valid Link
output hd_ena; // Half-Duplex Enable
output led_col; // Collision Indication
output led_an; // Auto-Negotiation Status
output led_char_err; // Character Error
output led_disp_err; // Disparity Error
output set_10; // 10Mbps Link Indication
output set_100; // 100Mbps Link Indication
output set_1000; // Gigabit Link Indication
wire rx_clk;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire gmii_rx_dv;
wire [7:0] gmii_rx_d;
wire gmii_rx_err;
wire mii_rx_dv;
wire [3:0] mii_rx_d;
wire mii_rx_err;
wire mii_col;
wire mii_crs;
wire [9:0] tbi_tx_d;
wire sd_loopback;
wire powerdown;
wire [15:0] reg_data_out;
wire reg_busy;
wire led_crs;
wire led_link;
wire hd_ena;
wire led_col;
wire led_an;
wire led_char_err;
wire led_disp_err;
wire set_10;
wire set_100;
wire set_1000;
altera_tse_top_1000_base_x top_1000_base_x_inst(
.reset_rx_clk(reset_rx_clk),
.reset_tx_clk(reset_tx_clk),
.reset_reg_clk(reset_reg_clk),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_d(gmii_rx_d),
.gmii_rx_err(gmii_rx_err),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_d(gmii_tx_d),
.gmii_tx_err(gmii_tx_err),
.mii_rx_dv(mii_rx_dv),
.mii_rx_d(mii_rx_d),
.mii_rx_err(mii_rx_err),
.mii_tx_en(mii_tx_en),
.mii_tx_d(mii_tx_d),
.mii_tx_err(mii_tx_err),
.mii_col(mii_col),
.mii_crs(mii_crs),
.tbi_rx_clk(tbi_rx_clk),
.tbi_tx_clk(tbi_tx_clk),
.tbi_rx_d(tbi_rx_d),
.tbi_tx_d(tbi_tx_d),
.sd_loopback(sd_loopback),
.reg_clk(reg_clk),
.reg_rd(reg_rd),
.reg_wr(reg_wr),
.reg_addr(reg_addr),
.reg_data_in(reg_data_in),
.reg_data_out(reg_data_out),
.reg_busy(reg_busy),
.powerdown(powerdown),
.set_10(set_10),
.set_100(set_100),
.set_1000(set_1000),
.hd_ena(hd_ena),
.led_col(led_col),
.led_an(led_an),
.led_char_err(led_char_err),
.led_disp_err(led_disp_err),
.led_crs(led_crs),
.led_link(led_link));
defparam
top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule |
module altera_tse_mac_pcs_pma /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */ (
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
gxb_cal_blk_clk,
gxb_pwrdn_in,
magic_sleep_n,
mdio_in,
read,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
pcs_pwrdn_out,
readdata,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b1; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 ? LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output pcs_pwrdn_out;
output [31: 0] readdata;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input gxb_cal_blk_clk;
input gxb_pwrdn_in;
input magic_sleep_n;
input mdio_in;
input read;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
wire MAC_PCS_reset;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire led_an;
wire led_char_err;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire [5:0] rx_err;
wire [17: 0] rx_err_stat;
wire [3:0] rx_frm_type;
wire sd_loopback;
wire tbi_rx_clk;
wire [9:0] tbi_rx_d;
wire tbi_tx_clk;
wire [9:0] tbi_tx_d;
wire tx_ff_uflow;
wire txp;
wire waitrequest;
wire [9:0] tbi_rx_d_lvds;
reg pma_digital_rst0;
reg pma_digital_rst1;
reg pma_digital_rst2;
reg [9:0] tbi_rx_d_flip;
reg [9:0] tbi_tx_d_flip;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
always @(posedge clk or posedge reset)
begin
if (reset == 1)
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= reset;
pma_digital_rst2 <= reset;
end
else
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= pma_digital_rst0;
pma_digital_rst2 <= pma_digital_rst1;
end
end
// Assign the digital reset of the PMA to the MAC_PCS logic
// --------------------------------------------------------
assign MAC_PCS_reset = pma_digital_rst2;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_ena altera_tse_mac_pcs_pma_ena_inst
(
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err),
.led_col (led_col),
.led_crs (led_crs),
.led_disp_err (led_disp_err),
.led_link (led_link),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (MAC_PCS_reset),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frm_type (rx_frm_type),
.sd_loopback (sd_loopback),
.tbi_rx_clk (tbi_rx_clk),
.tbi_rx_d (tbi_rx_d),
.tbi_tx_clk (tbi_tx_clk),
.tbi_tx_d (tbi_tx_d),
.tx_ff_uflow (tx_ff_uflow),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1)
begin
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the Alt2gxb block as the PMA for devices other than ArriaGX
// ----------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0)
begin
altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.rx_analogreset (reset),
.rx_clkout (tbi_rx_clk),
.rx_cruclk (ref_clk),
.rx_datain (rxp),
.rx_dataout (tbi_rx_d),
.rx_digitalreset (pma_digital_rst2),
.rx_patterndetect (),
.rx_seriallpbken (sd_loopback),
.tx_clkout (tbi_tx_clk),
.tx_datain (tbi_tx_d),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2)
);
end
endgenerate
// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
// ----------------------------------------------------------------
generate if (DEVICE_FAMILY == "ARRIAGX")
begin
altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.rx_analogreset (reset),
.rx_clkout (tbi_rx_clk),
.rx_cruclk (ref_clk),
.rx_datain (rxp),
.rx_dataout (tbi_rx_d),
.rx_digitalreset (pma_digital_rst2),
.rx_patterndetect (),
.rx_seriallpbken (sd_loopback),
.tx_clkout (tbi_tx_clk),
.tx_datain (tbi_tx_d),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2)
);
end
endgenerate
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1)
begin
assign tbi_tx_clk = ref_clk;
assign tbi_rx_d = tbi_rx_d_flip;
always @(posedge tbi_rx_clk or posedge reset)
begin
if (reset == 1)
tbi_rx_d_flip <= 0;
else
begin
tbi_rx_d_flip[0] <= tbi_rx_d_lvds[9];
tbi_rx_d_flip[1] <= tbi_rx_d_lvds[8];
tbi_rx_d_flip[2] <= tbi_rx_d_lvds[7];
tbi_rx_d_flip[3] <= tbi_rx_d_lvds[6];
tbi_rx_d_flip[4] <= tbi_rx_d_lvds[5];
tbi_rx_d_flip[5] <= tbi_rx_d_lvds[4];
tbi_rx_d_flip[6] <= tbi_rx_d_lvds[3];
tbi_rx_d_flip[7] <= tbi_rx_d_lvds[2];
tbi_rx_d_flip[8] <= tbi_rx_d_lvds[1];
tbi_rx_d_flip[9] <= tbi_rx_d_lvds[0];
end
end
always @(posedge ref_clk or posedge reset)
begin
if (reset == 1)
tbi_tx_d_flip <= 0;
else
begin
tbi_tx_d_flip[0] <= tbi_tx_d[9];
tbi_tx_d_flip[1] <= tbi_tx_d[8];
tbi_tx_d_flip[2] <= tbi_tx_d[7];
tbi_tx_d_flip[3] <= tbi_tx_d[6];
tbi_tx_d_flip[4] <= tbi_tx_d[5];
tbi_tx_d_flip[5] <= tbi_tx_d[4];
tbi_tx_d_flip[6] <= tbi_tx_d[3];
tbi_tx_d_flip[7] <= tbi_tx_d[2];
tbi_tx_d_flip[8] <= tbi_tx_d[1];
tbi_tx_d_flip[9] <= tbi_tx_d[0];
end
end
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx
(
.rx_divfwdclk (tbi_rx_clk),
.rx_in (rxp),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds),
.rx_outclock (),
.rx_reset (reset)
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx
(
.tx_in (tbi_tx_d_flip),
.tx_inclock (ref_clk),
.tx_out (txp)
);
end
endgenerate
endmodule |
module altera_tse_rgmii_in4 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input [3:0] datain;
input inclock;
output [3:0] dataout_h;
output [3:0] dataout_l;
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] dataout_h = sub_wire0[3:0];
wire [3:0] dataout_l = sub_wire1[3:0];
altddio_in altddio_in_component (
.datain (datain),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire1),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 4;
endmodule |
module altera_tse_gxb_aligned_rxsync (
input clk,
input reset,
input [7:0] alt_dataout,
input alt_sync,
input alt_disperr,
input alt_ctrldetect,
input alt_errdetect,
input alt_rmfifodatadeleted,
input alt_rmfifodatainserted,
input alt_runlengthviolation,
input alt_patterndetect,
input alt_runningdisp,
output reg [7:0] altpcs_dataout,
output altpcs_sync,
output reg altpcs_disperr,
output reg altpcs_ctrldetect,
output reg altpcs_errdetect,
output reg altpcs_rmfifodatadeleted,
output reg altpcs_rmfifodatainserted,
output reg altpcs_carrierdetect) ;
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
//-------------------------------------------------------------------------------
// intermediate wires
//reg altpcs_dataout
// pipelined 1
reg [7:0] alt_dataout_reg1;
reg alt_sync_reg1;
reg alt_sync_reg2;
reg alt_disperr_reg1;
reg alt_ctrldetect_reg1;
reg alt_errdetect_reg1;
reg alt_rmfifodatadeleted_reg1;
reg alt_rmfifodatainserted_reg1;
reg alt_patterndetect_reg1;
reg alt_runningdisp_reg1;
reg alt_runlengthviolation_latched;
//-------------------------------------------------------------------------------
always @(posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
// pipelined 1
alt_dataout_reg1 <= 8'h0;
alt_sync_reg1 <= 1'b0;
alt_disperr_reg1 <= 1'b0;
alt_ctrldetect_reg1 <= 1'b0;
alt_errdetect_reg1 <= 1'b0;
alt_rmfifodatadeleted_reg1 <= 1'b0;
alt_rmfifodatainserted_reg1 <= 1'b0;
alt_patterndetect_reg1 <= 1'b0;
alt_runningdisp_reg1 <= 1'b0;
end
else
begin
// pipelined 1
alt_dataout_reg1 <= alt_dataout;
alt_sync_reg1 <= alt_sync;
alt_disperr_reg1 <= alt_disperr;
alt_ctrldetect_reg1 <= alt_ctrldetect;
alt_errdetect_reg1 <= alt_errdetect;
alt_rmfifodatadeleted_reg1 <= alt_rmfifodatadeleted;
alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;
alt_patterndetect_reg1 <= alt_patterndetect;
alt_runningdisp_reg1 <= alt_runningdisp;
end
end
generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX")
begin
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
end
else
begin
if (alt_sync == 1'b1 )
begin
altpcs_dataout <= alt_dataout_reg1;
altpcs_disperr <= alt_disperr_reg1;
altpcs_ctrldetect <= alt_ctrldetect_reg1;
altpcs_errdetect <= alt_errdetect_reg1;
altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
end
else
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
end
end
end
assign altpcs_sync = alt_sync_reg1;
end
else if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "CYCLONEIVGX" || DEVICE_FAMILY == "HARDCOPYIV")
begin
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
alt_sync_reg2 <= 1'b0;
end
else
begin
altpcs_dataout <= alt_dataout_reg1;
altpcs_disperr <= alt_disperr_reg1;
altpcs_ctrldetect <= alt_ctrldetect_reg1;
altpcs_errdetect <= alt_errdetect_reg1;
altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
alt_sync_reg2 <= alt_sync_reg1 ;
end
end
assign altpcs_sync = alt_sync_reg2;
end
endgenerate
//latched runlength violation assertion for "carrier_detect" signal generation block
//reset the latch value after carrier_detect goes de-asserted
// always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)
// begin
// if (altpcs_carrierdetect == 1'b0)
// begin
// alt_runlengthviolation_latched <= 1'b0;
// end
// else
// begin
// if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)
// begin
// alt_runlengthviolation_latched <= 1'b1;
// end
// end
// end
// always @ (posedge reset or posedge clk)
// begin
// if (reset == 1'b1)
// begin
// alt_runlengthviolation_latched_reg <= 1'b0;
// end
// else
// begin
// alt_runlengthviolation_latched_reg <= alt_runlengthviolation_latched;
// end
// end
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
alt_runlengthviolation_latched <= 1'b0;
end
else
begin
if ((altpcs_carrierdetect == 1'b0) | (alt_sync == 1'b0))
begin
alt_runlengthviolation_latched <= 1'b0;
end
else
begin
if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))
begin
alt_runlengthviolation_latched <= 1'b1;
end
end
end
end
// carrier_detect signal generation
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_carrierdetect <= 1'b1;
end
else
begin
if ( (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
& alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b1
& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0 )) ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b1
& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 )) ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
& alt_runningdisp_reg1 == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )
)
begin
altpcs_carrierdetect <= 1'b0;
end
else
begin
altpcs_carrierdetect <= 1'b1;
end
end
end
endmodule |
module altera_tse_mac /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
clk, // Avalon slave - clock
read, // Avalon slave - read
write, // Avalon slave - write
address, // Avalon slave - address
writedata, // Avalon slave - writedata
readdata, // Avalon slave - readdata
waitrequest, // Avalon slave - waitrequest
reset, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
reset_ff_rx_clk,
reset_ff_tx_clk,
ff_rx_clk, // AtlanticII source - clk
ff_rx_data, // AtlanticII source - data
ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_rx_sop, // AtlanticII source - startofpacket
ff_rx_eop, // AtlanticII source - endofpacket
rx_err, // AtlanticII source - error
rx_err_stat, // AtlanticII source - component_specific_signal(eop)
rx_frm_type, // AtlanticII source - component_specific_signal(data)
ff_rx_rdy, // AtlanticII source - ready
ff_rx_dval, // AtlanticII source - valid
ff_rx_dsav, // AtlanticII source - component_specific_signal(data)
ff_tx_clk, // AtlanticII sink - clk
ff_tx_data, // AtlanticII sink - data
ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_tx_sop, // AtlanticII sink - startofpacket
ff_tx_eop, // AtlanticII sink - endofpacket
ff_tx_err, // AtlanticII sink - error
ff_tx_wren, // AtlanticII sink - valid
ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
ff_tx_rdy, // AtlanticII sink - ready
ff_tx_septy, // AtlanticII source - component_specific_signal(data)
tx_ff_uflow, // AtlanticII source - component_specific_signal(data)
ff_rx_a_full,
ff_rx_a_empty,
ff_tx_a_full,
ff_tx_a_empty,
xoff_gen,
xon_gen,
magic_sleep_n,
magic_wakeup,
rx_clk,
tx_clk,
gm_rx_d,
gm_rx_dv,
gm_rx_err,
gm_tx_d,
gm_tx_en,
gm_tx_err,
m_rx_d,
m_rx_en,
m_rx_err,
m_tx_d,
m_tx_en,
m_tx_err,
m_rx_crs,
m_rx_col,
eth_mode,
ena_10,
set_10,
set_1000,
mdc,
mdio_in,
mdio_out,
mdio_oen,
tx_control,
rx_control,
rgmii_in,
rgmii_out
);
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // ALTERA Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input clk; // 25MHz Host Interface Clock
input read; // Register Read Strobe
input write; // Register Write Strobe
input [7:0] address; // Register Address
input [31:0] writedata; // Write Data for Host Bus
output [31:0] readdata; // Read Data to Host Bus
output waitrequest; // Interface Busy
input reset; // Asynchronous Reset
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
input ff_rx_clk; // Transmit Local Clock
output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
output [1:0] ff_rx_mod; // Data Modulo
output ff_rx_sop; // Start of Packet
output ff_rx_eop; // End of Packet
output [5:0] rx_err; // Errored Packet Indication
output [17:0] rx_err_stat; // Packet Length and Status Word
output [3:0] rx_frm_type; // Unicast Frame Indication
input ff_rx_rdy; // PHY Application Ready
output ff_rx_dval; // Data Valid Strobe
output ff_rx_dsav; // Data Available
input ff_tx_clk; // Transmit Local Clock
input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
input [1:0] ff_tx_mod; // Data Modulo
input ff_tx_sop; // Start of Packet
input ff_tx_eop; // End of Packet
input ff_tx_err; // Errored Packet
input ff_tx_wren; // Write Enable
input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
output ff_tx_rdy; // FIFO Ready
output ff_tx_septy; // FIFO has space for at least one section
output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
output ff_rx_a_full; // Receive FIFO Almost Full
output ff_rx_a_empty; // Receive FIFO Almost Empty
output ff_tx_a_full; // Transmit FIFO Almost Full
output ff_tx_a_empty; // Transmit FIFO Almost Empty
input xoff_gen; // Xoff Pause frame generate
input xon_gen; // Xon Pause frame generate
input magic_sleep_n; // Enable Sleep Mode
output magic_wakeup; // Wake Up Request
input rx_clk; // Receive Clock
input tx_clk; // Transmit Clock
input [7:0] gm_rx_d; // GMII Receive Data
input gm_rx_dv; // GMII Receive Frame Enable
input gm_rx_err; // GMII Receive Frame Error
output [7:0] gm_tx_d; // GMII Transmit Data
output gm_tx_en; // GMII Transmit Frame Enable
output gm_tx_err; // GMII Transmit Frame Error
input [3:0] m_rx_d; // MII Receive Data
input m_rx_en; // MII Receive Frame Enable
input m_rx_err; // MII Receive Drame Error
output [3:0] m_tx_d; // MII Transmit Data
output m_tx_en; // MII Transmit Frame Enable
output m_tx_err; // MII Transmit Frame Error
input m_rx_crs; // Carrier Sense
input m_rx_col; // Collition
output eth_mode; // Ethernet Mode
output ena_10; // Enable 10Mbps Mode
input set_1000; // Gigabit Mode Enable
input set_10; // 10Mbps Mode Enable
output mdc; // 2.5MHz Inteface
input mdio_in; // MDIO Input
output mdio_out; // MDIO Output
output mdio_oen; // MDIO Output Enable
output tx_control;
output [3:0] rgmii_out;
input [3:0] rgmii_in;
input rx_control;
wire [31:0] reg_data_out;
wire reg_busy;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire ff_rx_dval;
wire ff_rx_dsav;
wire ff_tx_rdy;
wire ff_tx_septy;
wire tx_ff_uflow;
wire magic_wakeup;
wire ff_rx_a_full;
wire ff_rx_a_empty;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire [7:0] gm_tx_d;
wire gm_tx_en;
wire gm_tx_err;
wire [3:0] m_tx_d;
wire m_tx_en;
wire m_tx_err;
wire eth_mode;
wire ena_10;
wire mdc;
wire mdio_out;
wire mdio_oen;
wire tx_control;
wire [3:0] rgmii_out;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
// Reset Lines
// -----------
wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
// Programmable Reset Options
// --------------------------
generate if (USE_SYNC_RESET == 1)
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_rx_clk : !reset_rx_clk ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_tx_clk : !reset_tx_clk ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_rx_clk : !reset_ff_rx_clk ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset_ff_tx_clk : !reset_ff_tx_clk ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
else
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
endgenerate
// --------------------------
altera_tse_top_gen_host top_gen_host_inst(
.reset_ff_rx_clk(reset_ff_rx_clk_int),
.reset_ff_tx_clk(reset_ff_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(1'b1),
.tx_clkena(1'b1),
.gm_rx_dv(gm_rx_dv),
.gm_rx_d(gm_rx_d),
.gm_rx_err(gm_rx_err),
.m_rx_en(m_rx_en),
.m_rx_d(m_rx_d),
.m_rx_err(m_rx_err),
.m_rx_col(m_rx_col),
.m_rx_crs(m_rx_crs),
.set_1000(set_1000),
.set_10(set_10),
.ff_rx_clk(ff_rx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_tx_clk(ff_tx_clk),
.ff_tx_wren(ff_tx_wren),
.ff_tx_data(ff_tx_data),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_crc_fwd(ff_tx_crc_fwd),
.reg_clk(clk),
.reg_addr(address),
.reg_data_in(writedata),
.reg_rd(read),
.reg_wr(write),
.mdio_in(mdio_in),
.gm_tx_en(gm_tx_en),
.gm_tx_d(gm_tx_d),
.gm_tx_err(gm_tx_err),
.m_tx_en(m_tx_en),
.m_tx_d(m_tx_d),
.m_tx_err(m_tx_err),
.eth_mode(eth_mode),
.ena_10(ena_10),
.ff_rx_dval(ff_rx_dval),
.ff_rx_data(ff_rx_data),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.ff_rx_eop(ff_rx_eop),
.ff_rx_dsav(ff_rx_dsav),
.rx_err(rx_err),
.rx_err_stat(rx_err_stat),
.rx_frm_type(rx_frm_type),
.ff_tx_rdy(ff_tx_rdy),
.ff_tx_septy(ff_tx_septy),
.tx_ff_uflow(tx_ff_uflow),
.rx_a_full(ff_rx_a_full),
.rx_a_empty(ff_rx_a_empty),
.tx_a_full(ff_tx_a_full),
.tx_a_empty(ff_tx_a_empty),
.xoff_gen(xoff_gen),
.xon_gen(xon_gen),
.reg_data_out(readdata),
.reg_busy(waitrequest),
.reg_sleepN(magic_sleep_n),
.reg_wakeup(magic_wakeup),
.mdc(mdc),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen),
.tx_control(tx_control),
.rgmii_out(rgmii_out),
.rgmii_in(rgmii_in),
.rx_control(rx_control));
defparam
top_gen_host_inst.EG_FIFO = EG_FIFO,
top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
top_gen_host_inst.CORE_VERSION = CORE_VERSION,
top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
top_gen_host_inst.EG_ADDR = EG_ADDR,
top_gen_host_inst.ENA_HASH = ENA_HASH,
top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
top_gen_host_inst.ING_FIFO = ING_FIFO,
top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE, //1,
top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE, //1,
top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE, //1,
top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE, //1,
top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE, //0,
top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
top_gen_host_inst.ING_ADDR = ING_ADDR,
top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
top_gen_host_inst.CUST_VERSION = CUST_VERSION,
top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
top_gen_host_inst.INSERT_TA = INSERT_TA,
top_gen_host_inst.RAM_TYPE = RAM_TYPE,
top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
endmodule |
module system_pll (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire6),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 5,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 8000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=system_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 7;
endmodule |
module pkt_insert(
clk,
//wr_clk,
reset,
in0_pkt_wrreq,
in0_pkt,
in0_pkt_usedw,
in0_valid_wrreq,
in0_valid,
out2_pkt_wrreq,
out2_pkt,
out2_pkt_usedw,
out2_valid_wrreq,
out2_valid,
insert_N,
timer
);
input clk;
//input wr_clk;
input reset;
input in0_pkt_wrreq;//port0 input pkt;
input [138:0]in0_pkt;
output [7:0]in0_pkt_usedw;
input in0_valid_wrreq;
input in0_valid;
output out2_pkt_wrreq;//output to port2;
output [138:0]out2_pkt;
input [7:0]out2_pkt_usedw;
output out2_valid_wrreq;
output out2_valid;
input [31:0]insert_N;//insert n;
input [31:0]timer;//TS;
reg out2_pkt_wrreq;
reg [138:0]out2_pkt;
reg out2_valid_wrreq;
reg out2_valid;
reg [31:0]counter;//N:10 in 1;
reg [15:0]pkt_id;//ID;
reg [138:0]data_reg;//ip data storage;
reg [138:0]nonip_data_reg;//non ip data storage;
reg flag;
reg [31:0]insert_N_r;
reg [3:0]current_state;
parameter idle=4'b0,
pkt_identify=4'b0001,
append_pkt_id=4'b0010,
ip_transmit=4'b0011,
over_4B=4'b0100,
append_ref_pkt=4'b0101,
ref_pkt_second=4'b0110,
ref_pkt_third=4'b0111,
ref_pkt_forth=4'b1000,
discard=4'b1001,
nonip_transmit=4'b1010,
nonip_over_4B=4'b1011;
always@(posedge clk or negedge reset)
if(!reset)
begin
out2_pkt_wrreq<=1'b0;
out2_valid_wrreq<=1'b0;
in0_pkt_rdreq<=1'b0;
in0_valid_rdreq<=1'b0;
counter<=31'b0;
pkt_id<=16'b0;
data_reg<=139'b0;
flag <= 1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
out2_pkt_wrreq<=1'b0;
out2_valid_wrreq<=1'b0;
if(flag==1'b0)begin
insert_N_r <= insert_N;
flag <= 1'b1;
end
else begin
flag <= flag;
insert_N_r <= insert_N_r;
end
if(out2_pkt_usedw<=8'd161)//port2 output fifo can save a max pkt;
begin
if(in0_valid_empty==1'b0)
begin
if(in0_valid_q==1'b1)//the pkt is valid;
begin
in0_pkt_rdreq<=1'b1;
in0_valid_rdreq<=1'b1;
counter<=counter+1'b1;
pkt_id<=pkt_id+1'b1;
current_state<=pkt_identify;
end
else//invalid pkt;
begin
in0_pkt_rdreq<=1'b1;
in0_valid_rdreq<=1'b1;
current_state<=discard;
end
end
else//empty;
begin
current_state<=idle;
end
end
else
begin
current_state<=idle;
end//end usedw else;
end//end idle;
pkt_identify:
begin
in0_valid_rdreq<=1'b0;
in0_pkt_rdreq<=1'b1;
if(in0_pkt_q[31:16]==16'h0800)//IP pkt;
begin
out2_pkt_wrreq<=1'b0;
data_reg<=in0_pkt_q;
data_reg[15:0]<=16'h0001;//experimet pkt;
current_state<=append_pkt_id;
end
else//non IP pkt;
begin
out2_pkt_wrreq<=1'b0;
nonip_data_reg<=in0_pkt_q;
//out2_pkt<=in0_pkt_q;
current_state<=nonip_transmit;
end
end//end pkt_identify;
nonip_transmit:
begin
in0_pkt_rdreq<=1'b1;
if(in0_pkt_q[138:136]==3'b110)//tail;
begin
in0_pkt_rdreq<=1'b0;
nonip_data_reg<=in0_pkt_q;
if(in0_pkt_q[135:132]>4'b0011)//>4B;
begin
out2_pkt_wrreq<=1'b1;
out2_pkt<=nonip_data_reg;
current_state<=nonip_over_4B;
end
else if(in0_pkt_q[135:132]==4'b0011)//==4B;
begin
out2_pkt_wrreq<=1'b1;
out2_pkt<=nonip_data_reg;
out2_pkt[138:136]<=3'b110;//tail;
out2_pkt[135:132]<=4'b1111;
out2_valid_wrreq<=1'b1;
out2_valid<=1'b1;
if(counter==insert_N_r)//
current_state<=append_ref_pkt;
else
current_state<=idle;
end
else
begin
out2_pkt_wrreq<=1'b1;
out2_pkt<=nonip_data_reg;
out2_pkt[138:136]<=3'b110;
out2_pkt[135:132]<=4'b1111-(4'b0011-in0_pkt_q[135:132]);
out2_valid_wrreq<=1'b1;
out2_valid<=1'b1;
if(counter==insert_N_r)//
current_state<=append_ref_pkt;
else
current_state<=idle;
end
end
else//middle;
begin
out2_pkt_wrreq<=1'b1;
nonip_data_reg<=in0_pkt_q;
out2_pkt<=nonip_data_reg;
current_state<=nonip_transmit;
end
end//end nonip_transmit;
append_pkt_id:
begin
out2_pkt_wrreq<=1'b1;
out2_pkt<=data_reg;
in0_pkt_rdreq<=1'b1;
data_reg<=in0_pkt_q;
data_reg[47:16]<=timer;//TS;
data_reg[15:0]<=pkt_id;//ID;
current_state<=ip_transmit;
end//end append_pkt_id;
ip_transmit:
begin
if(in0_pkt_q[138:136]==3'b110)//tail;
begin
in0_pkt_rdreq<=1'b0;
data_reg<=in0_pkt_q;
if(in0_pkt_q[135:132]>4'b0011)//>4B;
begin
out2_pkt_wrreq<=1'b1;
out2_pkt<=data_reg;
current_state<=over_4B;
end
else if(in0_pkt_q[135:132]==4'b0011)//==4B;
begin
out2_pkt_wrreq<=1'b1;
out2_pkt<=data_reg;
out2_pkt[138:136]<=3'b110;//tail;
out2_pkt[135:132]<=4'b1111;
out2_valid_wrreq<=1'b1;
out2_valid<=1'b1;
if(counter==insert_N_r)//
current_state<=append_ref_pkt;
else
current_state<=idle;
end
else
begin
out2_pkt_wrreq<=1'b1;
out2_pkt<=data_reg;
out2_pkt[138:136]<=3'b110;
out2_pkt[135:132]<=4'b1111-(4'b0011-in0_pkt_q[135:132]);
out2_valid_wrreq<=1'b1;
out2_valid<=1'b1;
if(counter==insert_N_r)//
current_state<=append_ref_pkt;
else
current_state<=idle;
end
end
else//third and last middle;
begin
out2_pkt_wrreq<=1'b1;
out2_pkt<=data_reg;
in0_pkt_rdreq<=1'b1;
data_reg<=in0_pkt_q;
current_state<=ip_transmit;
end
end//end ip_transmit;
over_4B:
begin
out2_valid_wrreq<=1'b1;
out2_valid<=1'b1;
out2_pkt_wrreq<=1'b1;
out2_pkt<=data_reg;
out2_pkt[135:132]<=data_reg[135:132]-4'b0100;
if(counter==insert_N_r)//
current_state<=append_ref_pkt;
else
current_state<=idle;
end//end over_4B;
nonip_over_4B:
begin
out2_valid_wrreq<=1'b1;
out2_valid<=1'b1;
out2_pkt_wrreq<=1'b1;
out2_pkt<=nonip_data_reg;
out2_pkt[135:132]<=nonip_data_reg[135:132]-4'b0100;
if(counter==insert_N_r)//
current_state<=append_ref_pkt;
else
current_state<=idle;
end//end nonip_over_4B;
append_ref_pkt:
begin
out2_valid_wrreq<=1'b0;
out2_pkt_wrreq<=1'b1;//the first data of ref pkt;
out2_pkt[138:136]<=3'b101;//header;
out2_pkt[135:132]<=4'b1111;//valid byte;
out2_pkt[131:128]<=4'b0;
out2_pkt[127:80]<=48'h112233445566;//DMAC;
out2_pkt[79:32]<=48'h665544332211;//SMAC;
out2_pkt[31:16]<=16'h0800;//DMAC;
out2_pkt[15:0]<=16'h02;//ref identify;
pkt_id<=pkt_id+1'b1;
counter<=32'b0;
current_state<=ref_pkt_second;
end//end append_ref_pkt;
ref_pkt_second:
begin
out2_pkt_wrreq<=1'b1;//the second data of ref pkt;
out2_pkt[138:136]<=3'b100;//middle;
out2_pkt[135:132]<=4'b1111;//valid byte;
out2_pkt[131:128]<=4'b0;
out2_pkt[127:112]<=16'h02e;//ip length;
out2_pkt[111:96]<=pkt_id;//;ID
out2_pkt[95:80]<=16'h0;//skew;
out2_pkt[79:72]<=8'd125;//TTL;
out2_pkt[71:64]<=8'd253;//PROtocol;
out2_pkt[63:48]<=16'b0;//checksum;
out2_pkt[47:16]<=timer;//TS;
out2_pkt[15:0]<=pkt_id;//ID,unused;
current_state<=ref_pkt_third;
end//end ref_pkt_second;
ref_pkt_third:
begin
out2_pkt_wrreq<=1'b1;//the third data of ref pkt;
out2_pkt[138:136]<=3'b100;//middle;
out2_pkt[135:132]<=4'b1111;//valid byte;
out2_pkt[131:128]<=4'b0;
out2_pkt[127:110]<=16'd02;//ref identify;
out2_pkt[111:0]<=112'b0;
current_state<=ref_pkt_forth;
end//end ref_pkt_third;
ref_pkt_forth:
begin
out2_pkt_wrreq<=1'b1;//the forth and last data of ref pkt;
out2_pkt[138:136]<=3'b110;//tail;
out2_pkt[135:132]<=4'hb;//valid byte;
out2_pkt[131:128]<=4'b0;
out2_pkt[127:0]<=128'b0;
out2_valid_wrreq<=1'b1;
out2_valid<=1'b1;
flag <= 1'b0;
current_state<=idle;
end//end ref_pkt_forth;
discard:
begin
in0_pkt_rdreq<=1'b1;
in0_valid_rdreq<=1'b0;
if(in0_pkt_q[138:136]==3'b110)//tail;
begin
in0_pkt_rdreq<=1'b0;
current_state<=idle;
end
else if(in0_pkt_q[138:136]==3'b111)//tail;
begin
in0_pkt_rdreq<=1'b0;
current_state<=idle;
end
else
begin
current_state<=discard;
end
end
default:
begin
current_state<=idle;
end//end default;
endcase
end//end reset else;
reg in0_pkt_rdreq;
wire [138:0]in0_pkt_q;
wire [7:0]in0_pkt_usedw;
fifo_256_139 fifo_256_1394(
.aclr(!reset),
.clock(clk),
.data(in0_pkt),
.rdreq(in0_pkt_rdreq),
.wrreq(in0_pkt_wrreq),
.q(in0_pkt_q),
.usedw(in0_pkt_usedw)
);
reg in0_valid_rdreq;
wire in0_valid_q;
wire in0_valid_empty;
fifo_64_1 fifo_64_14(
.aclr(!reset),
.clock(clk),
.data(in0_valid),
.rdreq(in0_valid_rdreq),
.wrreq(in0_valid_wrreq),
.empty(in0_valid_empty),
.q(in0_valid_q)
);
endmodule |
module pass_through(
clk,
reset,
in_pkt_wrreq,
in_pkt,
in_pkt_usedw,
in_valid_wrreq,
in_valid,
out_pkt_wrreq,
out_pkt,
out_pkt_usedw,
out_valid_wrreq,
out_valid
);
input clk;
input reset;
input in_pkt_wrreq;
input [138:0]in_pkt;
output [7:0]in_pkt_usedw;
input in_valid_wrreq;
input in_valid;
output out_pkt_wrreq;
output [138:0]out_pkt;
input [7:0]out_pkt_usedw;
output out_valid_wrreq;
output out_valid;
reg out_pkt_wrreq;
reg [138:0]out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg [1:0]current_state;
parameter idle=2'b0,
transmit=2'b01,
discard=2'b10;
always@(posedge clk or negedge reset)
if(!reset)
begin
in_pkt_rdreq<=1'b0;
in_valid_rdreq<=1'b0;
out_pkt_wrreq<=1'b0;
out_valid_wrreq<=1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
out_pkt_wrreq<=1'b0;
out_valid_wrreq<=1'b0;
if(out_pkt_usedw<8'd161)
begin
if(!in_valid_empty)
begin
if(in_valid_q==1'b1)
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=transmit;
end
else
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=discard;
end
end
else
begin
current_state<=idle;
end
end
else
begin
current_state<=idle;
end
end//end idle;
transmit:
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b0;
if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
out_valid_wrreq<=1'b1;
out_valid<=1'b1;
current_state<=idle;
end
else
begin
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
end//end transmit;
discard:
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b0;
if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else
begin
current_state<=discard;
end
end//end discard;
default:
begin
end//end defult;
endcase
end
reg in_pkt_rdreq;
wire [138:0]in_pkt_q;
wire [7:0]in_pkt_usedw;
fifo_256_139 fifo_256_1393(
.aclr(!reset),
.clock(clk),
.data(in_pkt),
.rdreq(in_pkt_rdreq),
.wrreq(in_pkt_wrreq),
.q(in_pkt_q),
.usedw(in_pkt_usedw)
);
reg in_valid_rdreq;
wire in_valid_q;
wire in_valid_empty;
fifo_64_1 fifo_64_13(
.aclr(!reset),
.clock(clk),
.data(in_valid),
.rdreq(in_valid_rdreq),
.wrreq(in_valid_wrreq),
.empty(in_valid_empty),
.q(in_valid_q)
);
endmodule |
module info_gather(
clk,
reset,
in4_pkt_wrreq,
in4_pkt,
in4_pkt_usedw,
in4_valid_wrreq,
in4_valid,
out1_pkt_wrreq,
out1_pkt,
out1_pkt_usedw,
out1_valid_wrreq,
out1_valid,
info_pkt_wrreq,
info_pkt,
info_pkt_usedw,
info_valid_wrreq,
info_valid,
timer
);
input clk;
input reset;
input in4_pkt_wrreq;
input [138:0]in4_pkt;
output [7:0]in4_pkt_usedw;
input in4_valid_wrreq;
input in4_valid;
output out1_pkt_wrreq;
output [138:0]out1_pkt;
input [7:0]out1_pkt_usedw;
output out1_valid_wrreq;
output out1_valid;
output info_pkt_wrreq;
output [138:0]info_pkt;
input [7:0]info_pkt_usedw;
output info_valid_wrreq;
output info_valid;
input [31:0]timer;
reg out1_pkt_wrreq;
reg [138:0]out1_pkt;
reg out1_valid_wrreq;
reg out1_valid;
reg info_pkt_wrreq;
reg [138:0]info_pkt;
reg info_valid_wrreq;
reg info_valid;
reg flag;//the FSM is starting;1:reset,first pre-ref-pkt should be wrote;
reg flag_exper;//the info pkt have exper pkt;>64B;0:no;1:yes;
reg [138:0]expre_dada_reg;//
reg [138:0]nonip_data_reg;//
reg [138:0]pre_ref_pkt_reg;//the refpkt is the next pre refpkt;
reg [7:0] counter_ref;
reg [4:0]current_state;
parameter idle=5'b0,
exper_collect=5'b0001,
exper_collect1=5'b0010,
transmit=5'b0011,
ref_collect=5'b0100,
ref_collect1=5'b0101,
add_pre_ref=5'b0110,
pass_throgh=5'b0111,
discard=5'b1000,
expre_over_4B=5'b1001,
nonip_over_4B=5'b1010,
add_exper_mac=5'b1011,
add_ref_mac=5'b1100,
add_pre_mac2=5'b1101,
exper_collect2=5'b1110,
pass_add_exper_mac1=5'b01111,
pass_add_exper_mac2=5'b10000,
pass_add_exper_mac3=5'b10001;
always@(posedge clk or negedge reset)
if(!reset)
begin
in4_pkt_rdreq<=1'b0;
in4_valid_rdreq<=1'b0;
out1_pkt_wrreq<=1'b0;
out1_valid_wrreq<=1'b0;
info_pkt_wrreq<=1'b0;
info_valid_wrreq<=1'b0;
flag<=1'b1;
flag_exper<=1'b0;
expre_dada_reg<=139'b0;
nonip_data_reg<=139'b0;
counter_ref <= 8'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
info_pkt_wrreq<=1'b0;
info_pkt<=139'b0;
info_valid_wrreq<=1'b0;
out1_pkt_wrreq<=1'b0;//to port2 output fifo;
out1_valid_wrreq<=1'b0;
in4_pkt_rdreq<=1'b0;
if(!in4_valid_empty)//not empty;
begin
if(in4_valid_q==1'b1)//valid pkt;
begin
if((in4_pkt_q[31:16]==16'h0800)&&(in4_pkt_q[15:0]==16'd01)&&(counter_ref < 8'd80))//experiment flow;
begin
if(info_pkt_usedw<8'd161)//info fifo can save a max pkt;
begin
if(flag==1'b1)
begin
info_pkt_wrreq<=1'b1;
counter_ref <= counter_ref +1'b1;
info_pkt[138:136]<=3'b101;//MAC header;
info_pkt[135:132]<=4'b1111;//valid byte;
info_pkt[131:128]<=4'b0;
info_pkt[127:80]<=48'h998877665544;//DMAC;
info_pkt[79:32]<=48'h445566778899;//SMAC;
current_state<=add_exper_mac;
end
else
current_state<=add_exper_mac;
end
else
begin
current_state<=idle;
end
end
else if((in4_pkt_q[31:16]==16'h0800)&&(in4_pkt_q[15:0]==16'd01)&&(counter_ref >= 8'd80))//experiment flow to pass;
begin
if(info_pkt_usedw<8'd161)//info fifo can save a max pkt;
begin
in4_pkt_rdreq<=1'b1;
in4_valid_rdreq<=1'b1;
current_state<=pass_add_exper_mac1;
end
else
begin
current_state<=idle;
end
end
else if((in4_pkt_q[31:16]==16'h0800)&&(in4_pkt_q[15:0]==16'd02))//ref pkt flow;
begin
if(info_pkt_usedw<8'd161)//info fifo can save a max pkt;
begin
if(flag==1'b1)
begin
info_pkt_wrreq<=1'b1;
counter_ref <= counter_ref +1'b1;
info_pkt[138:136]<=3'b101;//MAC header;
info_pkt[135:132]<=4'b1111;//valid byte;
info_pkt[131:128]<=4'b0;
info_pkt[127:80]<=48'h998877665544;//DMAC;
info_pkt[79:32]<=48'h445566778899;//SMAC;
current_state<=add_ref_mac;
end
else
begin
current_state<=add_ref_mac;
end
end
else
begin
current_state<=idle;
end
end
else//pass through;
begin
in4_pkt_rdreq<=1'b1;
in4_valid_rdreq<=1'b1;
current_state<=pass_throgh;
end
end
else//error pkt;
begin
in4_pkt_rdreq<=1'b1;
in4_valid_rdreq<=1'b1;
current_state<=discard;
end
end
else//empty;
begin
current_state<=idle;
end
end//end idle;
add_exper_mac:
begin
in4_pkt_rdreq<=1'b1;
in4_valid_rdreq<=1'b1;
flag_exper<=1'b1;
if(flag==1'b1)//add pre ref pkt after the reset;
begin
info_pkt_wrreq<=1'b1;
info_pkt[138:136]<=3'b100;//middle;
info_pkt[135:132]<=4'b1111;//valid byte;
info_pkt[131:128]<=4'b0;
info_pkt[95:64]<=32'hffffffff;//the received TS;
flag<=1'b0;
counter_ref <= counter_ref +1'b1;
current_state<=exper_collect;
end
else
begin
current_state<=exper_collect;
end
end//end add_exper_mac;
add_ref_mac:
begin
in4_pkt_rdreq<=1'b1;
in4_valid_rdreq<=1'b1;
if(flag==1'b1)
begin
info_pkt_wrreq<=1'b1;
info_pkt[138:136]<=3'b100;//middle;
info_pkt[135:132]<=4'b1111;//valid byte;
info_pkt[131:128]<=4'b0;
info_pkt[95:64]<=32'hffffffff;//the received TS;
flag<=1'b0;
counter_ref <= counter_ref +1'b1;
current_state<=ref_collect;
end
else
begin
current_state<=ref_collect;
end
end//end add_exper_mac;
exper_collect:
begin
in4_pkt_rdreq<=1'b1;
in4_valid_rdreq<=1'b0;
info_pkt_wrreq<=1'b0;
info_pkt[138:136]<=3'b100;//middle;
info_pkt[135:132]<=4'b1111;//valid byte;
info_pkt[131:128]<=4'b0;
info_pkt[127:112]<=in4_pkt_q[15:0];//the received exper pkt,01;firt 101;
info_pkt[95:64]<=timer;
out1_pkt_wrreq<=1'b0;//to port2 output fifo;
expre_dada_reg<=in4_pkt_q;
expre_dada_reg[15:0]<=16'h4500;//revert;
current_state<=exper_collect1;
end//end exper_collect;
exper_collect1:
begin
in4_pkt_rdreq<=1'b1;
info_pkt_wrreq<=1'b0;
info_pkt[111:96]<=in4_pkt_q[15:0];//pkt ID;
if(in4_pkt_q[47:16]<info_pkt[95:64])//timer is normal;
info_pkt[63:32]<=info_pkt[95:64]-in4_pkt_q[47:16];//delay;
else//over flow;
info_pkt[63:32]<=32'hffffffff-in4_pkt_q[47:16]+info_pkt[95:64];//delay;
info_pkt[31:16]<=in4_pkt_q[127:112];//length;
out1_pkt_wrreq<=1'b1;//to port2 output fifo;
out1_pkt<=expre_dada_reg;
expre_dada_reg<=in4_pkt_q;
expre_dada_reg[15:0]<=16'h0102;//DIP,high 2 byte;
expre_dada_reg[47:16]<=32'h01020304;//SIP;
current_state<=exper_collect2;
end//end exper_collect1;
exper_collect2://udp d_port;
begin
in4_pkt_rdreq<=1'b1;
info_pkt_wrreq<=1'b1;
info_pkt[15:0]<=in4_pkt_q[95:80];//udp dport;
out1_pkt_wrreq<=1'b1;
out1_pkt<=expre_dada_reg;
expre_dada_reg<=in4_pkt_q;
counter_ref <= counter_ref +1'b1;
current_state<=transmit;
end//end exper_collect2;
transmit:
begin
info_pkt_wrreq<=1'b0;
in4_pkt_rdreq<=1'b1;
if(in4_pkt_q[138:136]==3'b110)//tail;
begin
in4_pkt_rdreq<=1'b0;
if(in4_pkt_q[135:132]>4'b0011)//>4B;
begin
out1_pkt_wrreq<=1'b1;
out1_pkt<=expre_dada_reg;
expre_dada_reg<=in4_pkt_q;
current_state<=expre_over_4B;
end
else if(in4_pkt_q[135:132]==4'b0011)//==4B;
begin
out1_pkt_wrreq<=1'b1;
out1_pkt<=expre_dada_reg;
out1_pkt[138:136]<=3'b110;//tail;
out1_pkt[135:132]<=4'b1111;
out1_valid_wrreq<=1'b1;
out1_valid<=1'b1;
current_state<=idle;
end
else
begin
out1_pkt_wrreq<=1'b1;
out1_pkt<=expre_dada_reg;
out1_pkt[138:136]<=3'b110;
out1_pkt[135:132]<=4'b1111-(4'b0011-in4_pkt_q[135:132]);
out1_valid_wrreq<=1'b1;
out1_valid<=1'b1;
current_state<=idle;
end
end
else
begin
out1_pkt_wrreq<=1'b1;//to port2 output fifo;
out1_pkt<=expre_dada_reg;
expre_dada_reg<=in4_pkt_q;
current_state<=transmit;
end
end//end transmit;
ref_collect:
begin
info_pkt_wrreq<=1'b0;
in4_pkt_rdreq<=1'b1;
info_pkt[138:136]<=3'b110;//tail;
info_pkt[135:132]<=4'b1111;//valid byte;
info_pkt[131:128]<=4'b0;
info_pkt[127:112]<=in4_pkt_q[15:0];//02:ref pkt;
info_pkt[95:64]<=timer;//receive TS;
current_state<=ref_collect1;
end//end ref_collect;
ref_collect1:
begin
info_pkt_wrreq<=1'b1;
counter_ref <= 8'b0;
in4_pkt_rdreq<=1'b1;
info_pkt[111:96]<=in4_pkt_q[111:96];//pkt ID;
if(in4_pkt_q[47:16]<info_pkt[95:64])//timer is normal;
info_pkt[63:32]<=info_pkt[95:64]-in4_pkt_q[47:16];//delay;
else//over flow;
info_pkt[63:32]<=32'hffffffff-in4_pkt_q[47:16]+info_pkt[95:64];//delay;
info_pkt[31:16]<=16'd64;
if(flag_exper==1'b1)//judge the abstract pkt if or not only contain pre-ref and last-ref;
begin
info_valid_wrreq<=1'b1;
info_valid<=1'b1;
end
else
begin
info_valid_wrreq<=1'b1;
info_valid<=1'b0;
end
current_state<=add_pre_mac2;
end//end ref_collect1;
add_pre_mac2://add MAC;
begin
info_valid_wrreq<=1'b0;
info_pkt_wrreq<=1'b1;
counter_ref <= counter_ref +1'b1;
in4_pkt_rdreq<=1'b1;
info_pkt[138:136]<=3'b101;//MAC header;
info_pkt[135:132]<=4'b1111;//valid byte;
info_pkt[131:128]<=4'b0;
info_pkt[127:80]<=48'h998877665544;//DMAC;
info_pkt[79:32]<=48'h445566778899;//SMAC;
pre_ref_pkt_reg<=info_pkt;
current_state<=add_pre_ref;
end//end add_pre_mac2;
add_pre_ref:
begin
info_pkt_wrreq<=1'b1;
counter_ref <= counter_ref +1'b1;
in4_pkt_rdreq<=1'b0;
info_valid_wrreq<=1'b0;
info_pkt<=pre_ref_pkt_reg;
info_pkt[138:136]<=3'b100;
flag_exper<=1'b0;
current_state<=idle;
end//end add_pre_ref;
pass_throgh:
begin
in4_pkt_rdreq<=1'b1;
in4_valid_rdreq<=1'b0;
if(in4_pkt_q[138:136]==3'b101)//header;
begin
out1_pkt_wrreq<=1'b0;
nonip_data_reg<=in4_pkt_q;
end
else if(in4_pkt_q[138:136]==3'b110)//tail;
begin
in4_pkt_rdreq<=1'b0;
if(in4_pkt_q[135:132]>4'b0011)//>4B;
begin
out1_pkt_wrreq<=1'b1;
out1_pkt<=nonip_data_reg;
nonip_data_reg<=in4_pkt_q;
current_state<=nonip_over_4B;
end
else if(in4_pkt_q[135:132]==4'b0011)//==4B;
begin
out1_pkt_wrreq<=1'b1;
out1_pkt<=nonip_data_reg;
out1_pkt[138:136]<=3'b110;//tail;
out1_pkt[135:132]<=4'b1111;
out1_valid_wrreq<=1'b1;
out1_valid<=1'b1;
current_state<=idle;
end
else
begin
out1_pkt_wrreq<=1'b1;
out1_pkt<=nonip_data_reg;
out1_pkt[138:136]<=3'b110;
out1_pkt[135:132]<=4'b1111-(4'b0011-in4_pkt_q[135:132]);
out1_valid_wrreq<=1'b1;
out1_valid<=1'b1;
current_state<=idle;
end
end
else
begin
out1_pkt_wrreq<=1'b1;
out1_pkt<=nonip_data_reg;
nonip_data_reg<=in4_pkt_q;
current_state<=pass_throgh;
end
end//end pass_throgh;
discard:
begin
info_pkt_wrreq<=1'b0;
if(in4_pkt_q[138:136]==3'b110)//tail;
begin
in4_pkt_rdreq<=1'b0;
current_state<=idle;
end
else if(in4_pkt_q[138:136]==3'b111)//only one clock data;
begin
in4_pkt_rdreq<=1'b0;
current_state<=idle;
end
else
begin
in4_pkt_rdreq<=1'b1;
current_state<=discard;
end
end//end discard;
expre_over_4B:
begin
out1_valid_wrreq<=1'b1;
out1_valid<=1'b1;
out1_pkt_wrreq<=1'b1;
out1_pkt<=expre_dada_reg;
out1_pkt[135:132]<=expre_dada_reg[135:132]-4'b0100;
current_state<=idle;
end//end expre_over_4B;
nonip_over_4B:
begin
out1_valid_wrreq<=1'b1;
out1_valid<=1'b1;
out1_pkt_wrreq<=1'b1;
out1_pkt<=nonip_data_reg;
out1_pkt[135:132]<=nonip_data_reg[135:132]-4'b0100;
current_state<=idle;
end//end expre_over_4B;
pass_add_exper_mac1:
begin
in4_pkt_rdreq<=1'b1;
in4_valid_rdreq<=1'b0;
out1_pkt_wrreq<=1'b0;//to port2 output fifo;
expre_dada_reg<=in4_pkt_q;
expre_dada_reg[15:0]<=16'h4500;//revert;
current_state<=pass_add_exper_mac2;
end
pass_add_exper_mac2:
begin
in4_pkt_rdreq<=1'b1;
in4_valid_rdreq<=1'b0;
out1_pkt_wrreq<=1'b1;//to port2 output fifo;
out1_pkt<=expre_dada_reg;
expre_dada_reg<=in4_pkt_q;
expre_dada_reg[15:0]<=16'h0102;//DIP,high 2 byte;
expre_dada_reg[47:16]<=32'h01020304;//SIP;
current_state<=pass_add_exper_mac3;
end
pass_add_exper_mac3:
begin
in4_pkt_rdreq<=1'b1;
out1_pkt_wrreq<=1'b1;
out1_pkt<=expre_dada_reg;
expre_dada_reg<=in4_pkt_q;
// counter_ref <= counter_ref +1'b1;
current_state<=transmit;
end
default:
begin
current_state<=idle;
end
endcase
end//end reset else;
reg in4_pkt_rdreq;
wire [138:0]in4_pkt_q;
wire [7:0]in4_pkt_usedw;
fifo_256_139 fifo_256_1392(
.aclr(!reset),
.clock(clk),
.data(in4_pkt),
.rdreq(in4_pkt_rdreq),
.wrreq(in4_pkt_wrreq),
.q(in4_pkt_q),
.usedw(in4_pkt_usedw)
);
reg in4_valid_rdreq;
wire in4_valid_q;
wire in4_valid_empty;
fifo_64_1 fifo_64_12(
.aclr(!reset),
.clock(clk),
.data(in4_valid),
.rdreq(in4_valid_rdreq),
.wrreq(in4_valid_wrreq),
.empty(in4_valid_empty),
.q(in4_valid_q)
);
endmodule |
module ts_gen(
clk,
reset,
timer
);
input clk;
input reset;
output [31:0]timer;
reg [31:0]timer;
always@(posedge clk or negedge reset)
if(!reset)
begin
timer<=32'b0;
end
else
begin
timer<=timer+1'b1;
end
endmodule |
module tx_crc_gen(
clk,
reset,
out2_pkt_wrreq,
out2_pkt,
out2_pkt_usedw,
out2_valid_wrreq,
out2_valid,
out2fifo_pkt_wrreq,
out2fifo_pkt,
out2fifo_pkt_usedw,
out2fifo_valid_wrreq,
out2fifo_valid
);
input clk;
input reset;
input out2_pkt_wrreq;//output to port2;
input [138:0]out2_pkt;
output [8:0]out2_pkt_usedw;
input out2_valid_wrreq;
input out2_valid;
output out2fifo_pkt_wrreq;//output to port2;
output [138:0]out2fifo_pkt;
input [7:0]out2fifo_pkt_usedw;
output out2fifo_valid_wrreq;
output out2fifo_valid;
reg out2fifo_pkt_wrreq;//output to port2;
reg [138:0]out2fifo_pkt;
wire [7:0]out2fifo_pkt_usedw;
reg out2fifo_valid_wrreq;
reg out2fifo_valid;
reg [31:0]checksum_reg;//storage crc checksum;
reg [3:0]current_state;
parameter idle=4'b0,
transmit=4'b0001,
wait_checksum=4'b0010,
last1=4'b0011,
last2=4'b0100,
last3=4'b0101,
last4=4'b0110,
discard=4'b0111;
always@(posedge clk or negedge reset)
if(!reset)
begin
out2fifo_pkt_wrreq<=1'b0;
out2fifo_valid_wrreq<=1'b0;
out2_pkt_rdreq<=1'b0;
out2_valid_rdreq<=1'b0;
crc_data_valid<=1'b0;
crc_empty<=4'b0;
end_of_pkt<=1'b0;
start_of_pkt<=1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
out2fifo_pkt_wrreq<=1'b0;
out2fifo_valid_wrreq<=1'b0;
if(out2fifo_pkt_usedw<8'd161)//output fifo can save a max pkt;
begin
if(!out2_valid_empty)//not empty;
begin
if(out2_valid_q==1'b1)//valid pkt;
begin
out2_pkt_rdreq<=1'b1;
out2_valid_rdreq<=1'b1;
current_state<=transmit;
end
else
begin
out2_pkt_rdreq<=1'b1;
out2_valid_rdreq<=1'b1;
current_state<=discard;
end
end
else//empty;
begin
current_state<=idle;
end
end
else//can not save a max pkt;
begin
current_state<=idle;
end
end//end idle;
transmit:
begin
out2_valid_rdreq<=1'b0;
out2_pkt_rdreq<=1'b1;
if(out2_pkt_q[138:136]==3'b101)//header;
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt<=out2_pkt_q;
crc_data_valid<=1'b1;
crc_data<=out2_pkt_q[127:0];
start_of_pkt<=1'b1;
current_state<=transmit;
end
else if(out2_pkt_q[138:136]==3'b110)//tail;
begin
crc_data_valid<=1'b1;
crc_data<=out2_pkt_q[127:0];
end_of_pkt<=1'b1;
crc_empty<=4'b1111-out2_pkt_q[135:132];
out2fifo_pkt_wrreq<=1'b0;
out2fifo_pkt<=out2_pkt_q;
out2_pkt_rdreq<=1'b0;
current_state<=wait_checksum;
end
else
begin
start_of_pkt<=1'b0;
crc_data_valid<=1'b1;
crc_data<=out2_pkt_q[127:0];
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt<=out2_pkt_q;
current_state<=transmit;
end
end//end transmit;
wait_checksum:
begin
crc_data_valid<=1'b0;
end_of_pkt<=1'b0;
crc_empty<=4'b0;
if(crc_checksum_valid==1'b1)//checksum is coming;
begin
checksum_reg<=crc_checksum;
case(out2fifo_pkt[135:132])
4'b0000:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:120],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{11{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b0001:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:112],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{10{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b0010:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:104],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{9{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b0011:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:96],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{8{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b0100:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:88],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{7{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b0101:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:80],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{6{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b0110:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:72],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{5{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b0111:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:64],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{4{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b1000:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:56],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{3{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b1001:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:48],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{2{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b1010:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:40],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24],{1{8'b0}}};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b1011:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:32],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16],crc_checksum[31:24]};
out2fifo_pkt[135:132]<=out2fifo_pkt[135:132]+4'b0100;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end
4'b1100:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:24],crc_checksum[7:0],crc_checksum[15:8],crc_checksum[23:16]};
out2fifo_pkt[135:132]<=4'b1111;
out2fifo_pkt[138:136]<=3'b100;
current_state<=last1;
end
4'b1101:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:16],crc_checksum[7:0],crc_checksum[15:8]};
out2fifo_pkt[135:132]<=4'b1111;
out2fifo_pkt[138:136]<=3'b100;
current_state<=last2;
end
4'b1110:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:0]<={out2fifo_pkt[127:8],crc_checksum[7:0]};
out2fifo_pkt[135:132]<=4'b1111;
out2fifo_pkt[138:136]<=3'b100;
current_state<=last3;
end
default:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt<=out2fifo_pkt;
out2fifo_pkt[135:132]<=4'b1111;
out2fifo_pkt[138:136]<=3'b100;
current_state<=last4;
end
endcase
end
else
begin
current_state<=wait_checksum;
end
end//end wait_checksum;
last1:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:120]<=checksum_reg[31:24];
out2fifo_pkt[135:132]<=4'b0;
out2fifo_pkt[138:136]<=3'b110;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end//end last1;
last2:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:112]<={checksum_reg[23:16],checksum_reg[31:24]};
out2fifo_pkt[135:132]<=4'b0001;
out2fifo_pkt[138:136]<=3'b110;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end//end last2;
last3:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:104]<={checksum_reg[15:8],checksum_reg[23:16],checksum_reg[31:24]};
out2fifo_pkt[135:132]<=4'b0010;
out2fifo_pkt[138:136]<=3'b110;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end//end last3;
last4:
begin
out2fifo_pkt_wrreq<=1'b1;
out2fifo_pkt[127:96]<={checksum_reg[7:0],checksum_reg[15:8],checksum_reg[23:16],checksum_reg[31:24]};
out2fifo_pkt[135:132]<=4'b0011;
out2fifo_pkt[138:136]<=3'b110;
out2fifo_valid_wrreq<=1'b1;
out2fifo_valid<=1'b1;
current_state<=idle;
end//end last4;
discard:
begin
out2_pkt_rdreq<=1'b1;
out2_valid_rdreq<=1'b0;
if(out2_pkt_q[138:136]==3'b110)//tail;
begin
out2_pkt_rdreq<=1'b0;
current_state<=idle;
end
else
begin
current_state<=discard;
end
end//end last4;
default:
begin
current_state<=idle;
end//end default;
endcase
end//end reset else;
wire [8:0]out2_pkt_usedw;
reg out2_pkt_rdreq;
wire [138:0]out2_pkt_q;
fifo_512_139 fifo_512_1390(
.aclr(!reset),
.clock(clk),
.data(out2_pkt),
.rdreq(out2_pkt_rdreq),
.wrreq(out2_pkt_wrreq),
.q(out2_pkt_q),
.usedw(out2_pkt_usedw)
);
reg out2_valid_rdreq;
wire out2_valid_empty;
wire out2_valid_q;
fifo_128_1 fifo_128_10(
.aclr(!reset),
.clock(clk),
.data(out2_valid),
.rdreq(out2_valid_rdreq),
.wrreq(out2_valid_wrreq),
.empty(out2_valid_empty),
.q(out2_valid_q)
);
reg [127:0]crc_data;
reg crc_data_valid;
reg [3:0]crc_empty;
reg end_of_pkt;
reg start_of_pkt;
wire [31:0]crc_checksum;
wire crc_checksum_valid;
crc_gen crc_gen0(
.clk(clk),
.data(crc_data),
.datavalid(crc_data_valid),
.empty(crc_empty),
.endofpacket(end_of_pkt),
.reset_n(reset),
.startofpacket(start_of_pkt),
.checksum(crc_checksum),
.crcvalid(crc_checksum_valid)
);
endmodule |
module nmac_crc_check(
clk,
wr_clk,
reset,
in_pkt_wrreq,
in_pkt,
in_pkt_usedw,
in_valid_wrreq,
in_valid,
port_error,
out_pkt_wrreq,
out_pkt,
out_pkt_usedw,
out_valid_wrreq,
out_valid
);
input clk;
input wr_clk;
input reset;
input in_pkt_wrreq;
input [138:0]in_pkt;
output [7:0]in_pkt_usedw;
input in_valid_wrreq;
input in_valid;
output port_error;
output out_pkt_wrreq;
output [138:0]out_pkt;
input [7:0]out_pkt_usedw;
output out_valid_wrreq;
output out_valid;
reg out_pkt_wrreq;
reg [138:0]out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg port_error;
reg [2:0]current_state;
parameter idle=3'b0,
transmit=3'b001,
wait_crcbad=3'b010,
discard=3'b011;
always@(posedge clk or negedge reset)
if(!reset)
begin
crc_data_valid<=1'b0;
crc_empty<=4'b0;
start_of_pkt<=1'b0;
end_of_pkt<=1'b0;
in_pkt_rdreq<=1'b0;
in_valid_rdreq<=1'b0;
out_pkt_wrreq<=1'b0;
out_valid_wrreq<=1'b0;
port_error <= 1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
out_valid_wrreq<=1'b0;
port_error <= 1'b0;
if(out_pkt_usedw<8'd161)
begin
if(!in_valid_empty)
begin
if(in_valid_q==1'b1)
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=transmit;
end
else
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=discard;
end
end
else
begin
current_state<=idle;
end
end
else
begin
current_state<=idle;
end
end//end idle;
transmit:
begin
in_valid_rdreq<=1'b0;
if(in_pkt_q[138:136]==3'b101)//header;
begin
in_pkt_rdreq<=1'b1;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
start_of_pkt<=1'b1;
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
else if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
end_of_pkt<=1'b1;
crc_empty<=4'b1111-in_pkt_q[135:132];
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=wait_crcbad;
end
else//middle;
begin
in_pkt_rdreq<=1'b1;
start_of_pkt<=1'b0;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
end//end transmit;
wait_crcbad:
begin
end_of_pkt<=1'b0;
crc_empty<=4'b0;
crc_data_valid<=1'b0;
out_pkt_wrreq<=1'b0;
if(crc_bad_valid==1'b1)
begin
if(crc_bad==1'b1)//error;
begin
out_valid_wrreq<=1'b1;
out_valid<=1'b0;
port_error <= 1'b1;
end
else
begin
out_valid_wrreq<=1'b1;
out_valid<=1'b1;
end
current_state<=idle;
end
else
begin
current_state<=wait_crcbad;
end
end//end wait_crcbad;
discard:
begin
in_valid_rdreq<=1'b0;
in_pkt_rdreq<=1'b1;
if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else if(in_pkt_q[138:136]==3'b111)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else
begin
current_state<=discard;
end
end//end discard;
default:
begin
current_state<=idle;
end
endcase
end
reg [127:0]crc_data;
reg crc_data_valid;
reg [3:0]crc_empty;
reg start_of_pkt;
reg end_of_pkt;
wire crc_bad_valid;
wire crc_bad;
check_ip check_ip0(
.clk(clk),
.data(crc_data),
.datavalid(crc_data_valid),
.empty(crc_empty),
.endofpacket(end_of_pkt),
.reset_n(reset),
.startofpacket(start_of_pkt),
.crcbad(crc_bad),
.crcvalid(crc_bad_valid)
);
reg in_pkt_rdreq;
wire [138:0]in_pkt_q;
wire [7:0]in_pkt_usedw;
asy_256_139 asy_256_1391(
.aclr(!reset),
.data(in_pkt),
.rdclk(clk),
.rdreq(in_pkt_rdreq),
.wrclk(wr_clk),
.wrreq(in_pkt_wrreq),
.q(in_pkt_q),
.wrusedw(in_pkt_usedw)
);
reg in_valid_rdreq;
wire in_valid_q;
wire in_valid_empty;
asy_64_1 asy_64_11(
.aclr(!reset),
.data(in_valid),
.rdclk(clk),
.rdreq(in_valid_rdreq),
.wrclk(wr_clk),
.wrreq(in_valid_wrreq),
.q(in_valid_q),
.rdempty(in_valid_empty)
);
endmodule |
module act_led(
clk,
reset,
gmii_rxen,
gmii_txen,
r_act_sfp);
input clk;
input reset;
input gmii_rxen;
input gmii_txen;
output r_act_sfp;
reg [23:0] count_led;
reg r_act_sfp;
reg [1:0]current_state;
parameter idle=2'b0,
first =2'b01,
second=2'b10;
always@(posedge clk or negedge reset)
if(!reset)
begin
count_led <= 24'b0;
r_act_sfp <= 1'b1;
current_state <= idle;
end
else
begin
case(current_state)
idle:
begin
count_led <= 24'b0;
if((gmii_rxen == 1'b1)||(gmii_txen == 1'b1))
begin
r_act_sfp <= 1'b0;
current_state <= first;
end
else
begin
r_act_sfp <= 1'b1;
current_state <= idle;
end
end
first:
begin
count_led <= count_led+1'b1;
if(count_led[23] == 1'b1)
begin
r_act_sfp <= 1'b1;
count_led <= 24'b0;
current_state <= second;
end
else
begin
current_state <= first;
end
end
second:
begin
if(count_led[23] == 1'b1)
begin
current_state <= idle;
end
else
begin
count_led <= count_led+1'b1;
current_state <= second;
end
end
default:
begin
current_state <= idle;
end
endcase
end
endmodule |
module sfp_rx_tx_1000(
clk,
sfp_clk,
reset,
gmii_rx_clk,
gmii_tx_clk,
sfp_rxp,
sfp_txp,
l_link_sfp,
r_act_sfp,
crc_data_valid,//rx data fifo
crc_data,
pkt_usedw,
pkt_valid_wrreq,
pkt_valid,
crc_gen_to_txfifo_wrreq,//tx fifo;
crc_gen_to_txfifo_data,
txfifo_data_usedw,
pkt_output_valid_wrreq,
pkt_output_valid,
port_receive,
port_discard,
port_send,
port_pream
);
input clk;
input sfp_clk;
input reset;
output gmii_rx_clk;
output gmii_tx_clk;
input sfp_rxp;
output sfp_txp;
output l_link_sfp;
output r_act_sfp;
output crc_data_valid;//to data fifo(crc check module);
output [138:0] crc_data;
input [7:0]pkt_usedw;
output pkt_valid_wrreq;//a full pkt,to flag fifo;
output pkt_valid;
input crc_gen_to_txfifo_wrreq;//data to txfifo;
input [138:0]crc_gen_to_txfifo_data;
output [7:0]txfifo_data_usedw;//data fifo usedw;
input pkt_output_valid_wrreq;//flag to flagfifo;
input pkt_output_valid;
output port_receive;
output port_discard;
output port_send;
output port_pream;
wire [7:0]gmii_txd;
wire gmii_txen;
wire gmii_txer;
wire [7:0]gmii_rxd;
wire gmii_rxen;
wire gmii_rxer;
wire gmii_rx_clk;//gmii rx clk;
wire gmii_tx_clk;//gmii tx clk;
wire crc_data_valid;//to data fifo(crc check module);
wire [138:0] crc_data;
wire pkt_valid_wrreq;//a full pkt,to flag fifo;
wire pkt_valid;
wire [7:0]txfifo_data_usedw;
wire port_receive;
wire port_discard;
wire port_send;
wire port_pream;
gmii_139_1000 gmii_139(
.clk(gmii_rx_clk),
.reset(reset),
.gmii_rxd(gmii_rxd),
.gmii_rxdv(gmii_rxen),
.gmii_rxer(gmii_rxer),
.crc_data_valid(crc_data_valid),
.crc_data(crc_data),
.pkt_usedw(pkt_usedw),
.pkt_valid_wrreq(pkt_valid_wrreq),
.pkt_valid(pkt_valid),
.port_receive(port_receive),
.port_discard(port_discard),
.port_pream(port_pream)
);
tx139_gmii_1000 tx139_gmii(
.clk(clk),//system clk;
.reset(reset),
.gmii_txclk(gmii_tx_clk),
.crc_gen_to_txfifo_wrreq(crc_gen_to_txfifo_wrreq),
.crc_gen_to_txfifo_data(crc_gen_to_txfifo_data),
.pkt_output_valid_wrreq(pkt_output_valid_wrreq),
.pkt_output_valid(pkt_output_valid),
.gmii_txd(gmii_txd),
.gmii_txen(gmii_txen),
.gmii_txer(gmii_txer),
.txfifo_data_usedw(txfifo_data_usedw),//output_data_usedw0;
.port_send(port_send)
);
wire l_link_sfp0;
wire l_link_sfp;
assign l_link_sfp = ~l_link_sfp0;
sfp2gmii sfp2gmii(
.gmii_rx_d(gmii_rxd),
.gmii_rx_dv(gmii_rxen),
.gmii_rx_err(gmii_rxer),
.tx_clk(gmii_tx_clk),
.rx_clk(gmii_rx_clk),
.readdata(),
.waitrequest(),
.txp(sfp_txp),
.reconfig_fromgxb(),
.led_an(),
.led_disp_err(),
.led_char_err(),
.led_link(l_link_sfp0),
.gmii_tx_d(gmii_txd),
.gmii_tx_en(gmii_txen),
.gmii_tx_err(gmii_txer),
.reset_tx_clk(~reset),
.reset_rx_clk(~reset),
.address(5'b0),
.read(1'b0),
.writedata(16'b0),
.write(1'b0),
.clk(clk),
.reset(~reset),
.rxp(sfp_rxp),
.ref_clk(sfp_clk),
.reconfig_clk(1'b0),
.reconfig_togxb(3'b010),
.gxb_cal_blk_clk(sfp_clk)
);
act_led act_led(
.clk(clk),
.reset(reset),
.gmii_rxen(gmii_rxen),
.gmii_txen(gmii_txen),
.r_act_sfp(r_act_sfp)
);
endmodule |
module action(
input clk,
input reset,
input [7:0] xtr_id,
//act
input action_valid,
input [15:0] action,
input action_data_valid,
input [351:0] action_data,
//pkt addr
input [4:0] pkt_addr, //[4] == 1:cutpkt 0:nocut pkt
input pkt_addr_wr,
input [63:0] metadata_data,
input metadata_data_wr,
// cut pkt addr recycle
output reg [3:0] pkt_out_recycle_addr,
output reg pkt_out_recycle_addr_wr,
//nopktcut pkt addr recycle
output reg [3:0] nocutpkt_out_recycle_addr,
output reg nocutpkt_out_recycle_addr_wr,
//no cut ram READ
output reg [10:0] nocut_pkt_ram_rd_addr,
output reg nocut_pkt_ram_rd,
input [138:0] nocut_pkt_ram_data_q,
//cut pkt RAM READ
output reg [10:0] ram_rd_addr,
output reg ram_rd,
input [138:0] ram_data_q,
//rule out
output reg rule_wr,
output reg [19:0] rule, // [19] lisp pkt capsulate flag [18:8] length [7:0] out port;
//pkt out
output reg pkt_out_valid,
output reg [138:0] pkt_out,
input [7:0] pkt_out_usedw
);
wire [15:0] action_q;
reg action_rdreq;
wire action_empty;
wire [351:0] action_data_q;
reg action_data_rdreq;
wire action_data_empty;
wire [4:0] pkt_addr_q;
wire pkt_addr_empty;
reg pkt_addr_rdreq;
wire [63:0] metadata_data_q;
wire metadata_data_empty;
reg metadata_data_rdreq;
reg [15:0] action_q_r;
reg [351:0] action_data_q_r;
reg [63:0] metadata_data_q_r;
reg [10:0] length_r;
reg flag_head;
reg [7:0] count_id;
reg [3:0] current_state;
parameter idle_s = 4'd0,
action_s = 4'd1,
capsulate_lisp_h1_s = 4'd2,
capsulate_lisp_h2_s = 4'd3,
capsulate_lisp_h3_s = 4'd4,
capsulate_lisp_h4_s = 4'd5,
capsulate_lisp_h5_s = 4'd6,
discard_s = 4'd7,
wait_read1_s = 4'd8,
wait_read2_s = 4'd9,
//wait_read3_s = 4'd10,
wait_read4_s = 4'd11,
tran_b_s = 4'd12;
always @ (posedge clk or negedge reset)
if(!reset) begin
action_rdreq <= 1'b0;
action_data_rdreq <= 1'b0;
pkt_addr_rdreq <= 1'b0;
pkt_out_recycle_addr_wr <= 1'b0;
pkt_out_recycle_addr <= 4'b0;
nocutpkt_out_recycle_addr_wr <= 1'b0;
nocutpkt_out_recycle_addr <= 4'b0;
nocut_pkt_ram_rd_addr <= 11'b0;
nocut_pkt_ram_rd <= 1'b0;
ram_rd_addr <= 11'b0;
ram_rd <= 1'b0;
rule_wr <= 1'b0;
rule <= 20'b0;
pkt_out_valid <= 1'b0;
pkt_out <= 139'b0;
action_data_q_r <= 352'b0;
action_q_r <= 16'b0;
metadata_data_q_r <= 64'b0;
flag_head <= 1'b0;
length_r <= 11'b0;
metadata_data_rdreq <= 1'b0;
count_id <= 8'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
action_rdreq <= 1'b0;
action_data_rdreq <= 1'b0;
pkt_addr_rdreq <= 1'b0;
pkt_out_recycle_addr_wr <= 1'b0;
pkt_out_recycle_addr <= 4'b0;
nocutpkt_out_recycle_addr_wr <= 1'b0;
nocutpkt_out_recycle_addr <= 4'b0;
nocut_pkt_ram_rd_addr <= 11'b0;
nocut_pkt_ram_rd <= 1'b0;
ram_rd_addr <= 11'b0;
ram_rd <= 1'b0;
rule_wr <= 1'b0;
rule <= 20'b0;
pkt_out_valid <= 1'b0;
flag_head <= 1'b0;
pkt_out <= 139'b0;
length_r <= 11'b0;
if((action_empty == 1'b0)&&(action_data_empty == 1'b0)) begin
action_rdreq <= 1'b1;
action_data_rdreq <= 1'b1;
metadata_data_rdreq <= 1'b1;
action_data_q_r <= action_data_q;
action_q_r <= action_q;
metadata_data_q_r <= metadata_data_q;
current_state <= action_s;
end
else begin
current_state <= idle_s;
end
end
action_s: begin
action_rdreq <= 1'b0;
action_data_rdreq <= 1'b0;
metadata_data_rdreq <= 1'b0;
if(action_q_r[7:0] == 8'b0) begin//discard
pkt_addr_rdreq <= 1'b1;
current_state <= discard_s;
end
else begin
if(action_q_r[15] == 1'b1) begin////capsulate action_data;
if(pkt_out_usedw[7] == 1'b1) begin
current_state <= action_s;
end
else begin
current_state <= capsulate_lisp_h1_s;
end
end
else begin //dedecapsulate ceng-die-wang;
if(pkt_out_usedw[7] == 1'b1) begin
current_state <= action_s;
end
else begin
if(pkt_addr_q[4] == 1'b1) begin
ram_rd_addr <= {pkt_addr_q[3:0],7'b0};
ram_rd <= 1'b1;
end
else begin
nocut_pkt_ram_rd_addr <= {pkt_addr_q[3:0],7'b0};
nocut_pkt_ram_rd <= 1'b1;
end
current_state <= wait_read1_s;
end
end
end
end
capsulate_lisp_h1_s: begin
pkt_out <= {3'b101,4'hf,4'b0,action_data_q_r[95:0],16'h86dd,metadata_data_q_r[63:48]};
pkt_out_valid <= 1'b1;
current_state <= capsulate_lisp_h2_s;
end
capsulate_lisp_h2_s: begin
pkt_out <= {3'b100,4'hf,4'b0,metadata_data_q_r[47:32],16'd1104,8'd17,metadata_data_q_r[7:0],action_data_q_r[351:272]};
pkt_out_valid <= 1'b1;
current_state <= capsulate_lisp_h3_s;
end
capsulate_lisp_h3_s: begin
pkt_out_valid <= 1'b1;
pkt_out <= {3'b100,4'hf,4'b0,action_data_q_r[271:144]};
if(pkt_addr_q[4] == 1'b1) begin
ram_rd_addr <= {pkt_addr_q[3:0],7'b0};
ram_rd <= 1'b1;
end
else begin
nocut_pkt_ram_rd_addr <= {pkt_addr_q[3:0],7'b0};
nocut_pkt_ram_rd <= 1'b1;
end
current_state <= capsulate_lisp_h4_s;
end
capsulate_lisp_h4_s: begin
pkt_out <= {3'b100,4'hf,4'b0,action_data_q_r[143:96],16'd4344,16'd4341,16'd1024,32'b0};
pkt_out_valid <= 1'b1;
if(pkt_addr_q[4] == 1'b1) begin
ram_rd_addr <= ram_rd_addr + 1'b1;
ram_rd <= 1'b1;
end
else begin
nocut_pkt_ram_rd_addr <= nocut_pkt_ram_rd_addr + 1'b1;
nocut_pkt_ram_rd <= 1'b1;
end
current_state <= capsulate_lisp_h5_s;
end
capsulate_lisp_h5_s :begin
pkt_out <= {3'b100,4'hf,4'b0,48'b0,8'd0,xtr_id,count_id,8'd0,48'b0};
pkt_out_valid <= 1'b1;
count_id <= count_id + 1'b1;
current_state <= tran_b_s;
length_r <= 11'b0;
if(pkt_addr_q[4] == 1'b1) begin
ram_rd_addr <= ram_rd_addr + 1'b1;
ram_rd <= 1'b1;
end
else begin
nocut_pkt_ram_rd_addr <= nocut_pkt_ram_rd_addr + 1'b1;
nocut_pkt_ram_rd <= 1'b1;
end
end
tran_b_s: begin
//length_r <= length_r +11'd16;
if(pkt_addr_q[4] == 1'b1) begin
if(ram_data_q[138:136] == 3'b110) begin
ram_rd <= 1'b0;
pkt_out <= {3'b110,ram_data_q[135:0]};
pkt_out_valid <= 1'b1;
pkt_addr_rdreq <= 1'b1;
pkt_out_recycle_addr <= pkt_addr_q[3:0];
pkt_out_recycle_addr_wr <= 1'b1;
rule_wr <= 1'b1;
rule[19] <= 1'b1;
rule[18:8] <= length_r + ram_data_q[135:131] +11'd1;
rule[7:0] <= action_q_r[7:0];
current_state <= idle_s;
end
else begin
ram_rd_addr <= ram_rd_addr + 1'b1;
ram_rd <= 1'b1;
length_r <= length_r +11'd16;
pkt_out <= {3'b100,ram_data_q[135:0]};
pkt_out_valid <= 1'b1;
current_state <= tran_b_s;
end
end
else begin
if(nocut_pkt_ram_data_q[138:136] == 3'b110) begin
nocut_pkt_ram_rd <= 1'b0;
pkt_out <= {3'b110,nocut_pkt_ram_data_q[135:0]};
pkt_out_valid <= 1'b1;
pkt_addr_rdreq <= 1'b1;
nocutpkt_out_recycle_addr_wr <= 1'b1;
nocutpkt_out_recycle_addr <= pkt_addr_q[3:0];
rule_wr <= 1'b1;
rule[19] <= 1'b1;
rule[18:8] <= length_r + nocut_pkt_ram_data_q[135:131] +11'd1;
rule[7:0] <= action_q_r[7:0];
current_state <= idle_s;
end
else begin
nocut_pkt_ram_rd_addr <= nocut_pkt_ram_rd_addr + 1'b1;
nocut_pkt_ram_rd <= 1'b1;
length_r <= length_r +11'd16;
pkt_out <= {3'b100,nocut_pkt_ram_data_q[135:0]};
pkt_out_valid <= 1'b1;
current_state <= tran_b_s;
end
end
end
wait_read1_s: begin
flag_head <= 1'b1;
if(pkt_addr_q[4] == 1'b1) begin
ram_rd_addr <= {pkt_addr_q[3:0],7'b0} + 1'b1;
ram_rd <= 1'b1;
end
else begin
nocut_pkt_ram_rd_addr <= {pkt_addr_q[3:0],7'b0} + 1'b1;
nocut_pkt_ram_rd <= 1'b1;
end
current_state <= wait_read4_s;
end
/*wait_read3_s: begin
flag_head <= 1'b1;
if(pkt_addr_q[4] == 1'b1) begin
ram_rd_addr <= ram_rd_addr + 1'b1;
ram_rd <= 1'b1;
end
else begin
nocut_pkt_ram_rd_addr <= nocut_pkt_ram_rd_addr + 1'b1;
nocut_pkt_ram_rd <= 1'b1;
end
current_state <= wait_read4_s;
end*/
wait_read4_s: begin
flag_head <= 1'b1;
if(pkt_addr_q[4] == 1'b1) begin
ram_rd_addr <= ram_rd_addr + 1'b1;
ram_rd <= 1'b1;
end
else begin
nocut_pkt_ram_rd_addr <= nocut_pkt_ram_rd_addr + 1'b1;
nocut_pkt_ram_rd <= 1'b1;
end
current_state <= wait_read2_s;
end
wait_read2_s: begin
flag_head <= 1'b0;
if(pkt_addr_q[4] == 1'b1) begin
pkt_out_valid <= 1'b1;
if((flag_head == 1'b1)&&(action_q_r[13] == 1'b1)) begin
pkt_out <= {ram_data_q[138:128],action_data_q_r[95:0],ram_data_q[31:0]};
end
else begin
pkt_out <= ram_data_q;
end
if(ram_data_q[138:136] == 3'b110) begin
ram_rd_addr <= ram_rd_addr + 1'b1;
ram_rd <= 1'b0;
pkt_addr_rdreq <= 1'b1;
pkt_out_recycle_addr <= pkt_addr_q[3:0];
pkt_out_recycle_addr_wr <= 1'b1;
rule_wr <= 1'b1;
rule <= {1'b0,11'b0,action_q_r[7:0]};
current_state <= idle_s;
end
else begin
ram_rd_addr <= ram_rd_addr + 1'b1;
ram_rd <= 1'b1;
current_state <= wait_read2_s;
end
end
else begin
pkt_out_valid <= 1'b1;
if((flag_head == 1'b1)&&(action_q_r[13] == 1'b1)) begin
pkt_out <= {nocut_pkt_ram_data_q[138:128],action_data_q_r[95:0],nocut_pkt_ram_data_q[31:0]};
end
else begin
pkt_out <= nocut_pkt_ram_data_q;
end
if(nocut_pkt_ram_data_q[138:136] == 3'b110) begin
nocut_pkt_ram_rd_addr <= nocut_pkt_ram_rd_addr + 1'b1;
nocut_pkt_ram_rd <= 1'b0;
pkt_addr_rdreq <= 1'b1;
nocutpkt_out_recycle_addr_wr <= 1'b1;
nocutpkt_out_recycle_addr <= pkt_addr_q[3:0];
rule_wr <= 1'b1;
rule <= {1'b0,11'b0,action_q_r[7:0]};
current_state <= idle_s;
end
else begin
nocut_pkt_ram_rd_addr <= nocut_pkt_ram_rd_addr + 1'b1;
nocut_pkt_ram_rd <= 1'b1;
current_state <= wait_read2_s;
end
end
end
discard_s: begin
current_state <= idle_s;
pkt_addr_rdreq <= 1'b0;
if(pkt_addr_q[4] == 1'b1) begin
pkt_out_recycle_addr_wr <= 1'b1;
pkt_out_recycle_addr <= pkt_addr_q[3:0];
end
else begin
nocutpkt_out_recycle_addr_wr <= 1'b1;
nocutpkt_out_recycle_addr <= pkt_addr_q[3:0];
end
end
endcase
end
fifo_64_32 metadata_data_fifo(
.aclr (!reset),
.clock (clk),
.data (metadata_data),
.rdreq (metadata_data_rdreq),
.wrreq (metadata_data_wr),
.empty (metadata_data_empty),
.q (metadata_data_q));
fifo_16_32 action_fifo(
.aclr (!reset),
.clock (clk),
.data (action),
.rdreq (action_rdreq),
.wrreq (action_valid),
.empty (action_empty),
.q (action_q));
fifo_352_32 action_data_fifo(
.aclr (!reset),
.clock (clk),
.data (action_data),
.rdreq (action_data_rdreq),
.wrreq (action_data_valid),
.empty (action_data_empty),
.q (action_data_q));
fifo_5_32 pkt_addr_fifo(
.aclr (!reset),
.clock (clk),
.data (pkt_addr),
.rdreq (pkt_addr_rdreq),
.wrreq (pkt_addr_wr),
.empty (pkt_addr_empty),
.q (pkt_addr_q));
endmodule |
module transmit(
input clk,
input reset,
input mode, //1:cengdie wang 0:shi wang
input pkt_ctl_valid, //contorl
input [138:0] pkt_ctl,
output [7:0] pkt_ctl_usedw,
//rule
input rule_wr,
input [19:0] rule, // [19] lisp pkt capsulate flag [18:8] length [7:0] out port;
//pkt
input pkt_out_valid,
input [138:0] pkt_out,
output [7:0] pkt_out_usedw,
output reg um2cdp_rule_wrreq,
output reg [29:0] um2cdp_rule,
output reg um2cdp_data_valid,
output reg [138:0] um2cdp_data,
input [4:0] cdp2um_rule_usedw,
input cdp2um_tx_enable );
wire [138:0] pkt_ctl_q;
reg pkt_ctl_rdreq;
wire [138:0] pkt_out_q;
reg pkt_out_rdreq;
wire [19:0] rule_q;
reg rule_rdreq;
wire rule_empty;
reg [19:0] rule_q_r;
reg flag;
reg cut_pkt_flag;
reg [10:0] lisp_payload_r1;
reg [10:0] lisp_payload_r2;
reg [138:0] lisp_h1,lisp_h2,lisp_h3,lisp_h4,lisp_h5;
reg [6:0] count_reg;
reg [138:0] pkt_out_q_r;
reg [4:0] current_state;
parameter idle_s = 5'd0,
idle_s1 = 5'd1,
trans_ctl_s = 5'd2,
paser_rule_s = 5'd3,
trans_body_s = 5'd4,
trans_lisp_h1_s = 5'd5,
trans_lisp_h2_s = 5'd6,
trans_lisp_h3_s = 5'd7,
trans_lisp_h4_s = 5'd8,
trans_lisp_h5_s = 5'd9,
trans_lisp_body_s = 5'd10,
trans_second_lisp_h1_s = 5'd11,
trans_second_lisp_h2_5_s = 5'd12,
trans_second_lisp_body_s = 5'd13,
wait_enable_s = 5'd14,
wait_second_enable_s = 5'd15,
wait_ctl_enable_s = 5'd16;
always @ (posedge clk or negedge reset)
if(!reset) begin
um2cdp_rule_wrreq <= 1'b0;
um2cdp_rule <= 30'b0;
um2cdp_data_valid <= 1'b0;
um2cdp_data <= 1'b0;
pkt_ctl_rdreq <= 1'b0;
pkt_out_rdreq <= 1'b0;
rule_rdreq <= 1'b0;
flag <= 1'b0;
rule_q_r <= 20'b0;
lisp_payload_r1 <= 11'b0;
lisp_payload_r2 <= 11'b0;
lisp_h1 <= 139'b0;
lisp_h2 <= 139'b0;
lisp_h3 <= 139'b0;
lisp_h4 <= 139'b0;
lisp_h5 <= 139'b0;
cut_pkt_flag <= 1'b0;
count_reg <= 7'b0;
pkt_out_q_r <= 139'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
um2cdp_rule_wrreq <= 1'b0;
um2cdp_rule <= 30'b0;
um2cdp_data_valid <= 1'b0;
um2cdp_data <= 1'b0;
pkt_ctl_rdreq <= 1'b0;
pkt_out_rdreq <= 1'b0;
rule_rdreq <= 1'b0;
if(rule_empty == 1'b1) begin
current_state <= idle_s1;
end
else begin
if(cdp2um_rule_usedw[4:0]<5'd30) begin
rule_rdreq <= 1'b1;
rule_q_r <= rule_q;
current_state <= paser_rule_s;
end
else begin
current_state <= idle_s;
end
end
end
idle_s1: begin
um2cdp_rule_wrreq <= 1'b0;
um2cdp_rule <= 30'b0;
um2cdp_data_valid <= 1'b0;
um2cdp_data <= 1'b0;
pkt_ctl_rdreq <= 1'b0;
pkt_out_rdreq <= 1'b0;
rule_rdreq <= 1'b0;
if(pkt_ctl_usedw[7:0] == 8'b0) begin
current_state <= idle_s;
end
else begin
if(cdp2um_rule_usedw[4:0]<5'd29) begin
//pkt_ctl_rdreq <= 1'b1;
flag <= 1'b1;
current_state <= wait_ctl_enable_s;
end
else begin
current_state <= idle_s1;
end
end
end
wait_ctl_enable_s: begin
if(cdp2um_tx_enable == 1'b1) begin
pkt_ctl_rdreq <= 1'b1;
current_state <= trans_ctl_s;
end
else begin
current_state <= wait_ctl_enable_s;
end
end
paser_rule_s: begin
rule_rdreq <= 1'b0;
if(rule_q_r[19] == 1'b0) begin
pkt_out_rdreq <= 1'b0;
flag <= 1'b1;
um2cdp_rule_wrreq <= 1'b1;
um2cdp_rule <= {22'b0,rule_q_r[7:0]};
current_state <= wait_enable_s;
end
else begin
um2cdp_rule_wrreq <= 1'b1;
um2cdp_rule <= {22'b0,rule_q_r[7:0]};
if(rule_q_r[18:8] >11'd1300) begin
cut_pkt_flag <= 1'b1;
lisp_payload_r1 <= 11'd1024 + 11'd26;
lisp_payload_r2 <= rule_q_r[17:8] + 11'd26;
pkt_out_rdreq <= 1'b1;
pkt_out_q_r <= pkt_out_q;
current_state <= trans_lisp_h1_s;
end
else begin
cut_pkt_flag <= 1'b0;
lisp_payload_r1 <= rule_q_r[18:8] + 11'd26;
pkt_out_rdreq <= 1'b1;
pkt_out_q_r <= pkt_out_q;
current_state <= trans_lisp_h1_s;
end
end
end
wait_enable_s: begin
um2cdp_rule_wrreq <= 1'b0;
if(cdp2um_tx_enable == 1'b1) begin
pkt_out_rdreq <= 1'b1;
current_state <= trans_body_s;
end
else begin
current_state <= wait_enable_s;
end
end
trans_lisp_h1_s: begin
um2cdp_rule_wrreq <= 1'b0;
pkt_out_rdreq <= 1'b0;
if(cdp2um_tx_enable == 1'b1) begin
lisp_h1 <= pkt_out_q_r;
um2cdp_data_valid <= 1'b1;
pkt_out_rdreq <= 1'b1;
um2cdp_data <= pkt_out_q_r;
current_state <= trans_lisp_h2_s;
end
else begin
current_state <= trans_lisp_h1_s;
end
end
trans_lisp_h2_s: begin
lisp_h2 <= {pkt_out_q[138:112],5'b0,lisp_payload_r2[10:0],pkt_out_q[95:0]};
um2cdp_data_valid <= 1'b1;
um2cdp_data <= {pkt_out_q[138:112],5'b0,lisp_payload_r1[10:0],pkt_out_q[95:0]};
current_state <= trans_lisp_h3_s;
end
trans_lisp_h3_s: begin
lisp_h3 <= pkt_out_q;
um2cdp_data_valid <= 1'b1;
um2cdp_data <= pkt_out_q;
current_state <= trans_lisp_h4_s;
end
trans_lisp_h4_s: begin
lisp_h4 <= pkt_out_q;
um2cdp_data_valid <= 1'b1;
um2cdp_data <= pkt_out_q;
current_state <= trans_lisp_h5_s;
end
trans_lisp_h5_s: begin
lisp_h5 <= {pkt_out_q[138:80],8'd1,pkt_out_q[71:56],8'd1,48'b0};
um2cdp_data_valid <= 1'b1;
um2cdp_data <= {pkt_out_q[138:80],7'd0,cut_pkt_flag,pkt_out_q[71:56],8'd0,48'b0};
count_reg <= 7'd0;
pkt_out_rdreq <= 1'b1;//zq
current_state <= trans_lisp_body_s;
end
trans_lisp_body_s: begin
if(cut_pkt_flag == 1'b1) begin
if(count_reg == 7'd63) begin
pkt_out_rdreq <= 1'b0;
um2cdp_data_valid <= 1'b1;
um2cdp_rule_wrreq <= 1'b1;
um2cdp_rule <= {22'b0,rule_q_r[7:0]};
um2cdp_data <= {3'b110,pkt_out_q[135:0]};
current_state <= wait_second_enable_s;
end
else begin
um2cdp_data_valid <= 1'b1;
um2cdp_data <= pkt_out_q;
count_reg <= count_reg + 1'b1;
current_state <= trans_lisp_body_s;
end
end
else begin
if(pkt_out_q[138:136] == 3'b110) begin
pkt_out_rdreq <= 1'b0;
um2cdp_data_valid <= 1'b1;
um2cdp_data <= pkt_out_q;
//um2cdp_rule_wrreq <= 1'b1;
//um2cdp_rule <= {22'b0,rule_q_r[7:0]};
current_state <= idle_s1;
end
else begin
um2cdp_data_valid <= 1'b1;
um2cdp_data <= pkt_out_q;
current_state <= trans_lisp_body_s;
end
end
end
wait_second_enable_s: begin
um2cdp_data_valid <= 1'b0;
um2cdp_rule_wrreq <= 1'b0;
if(cdp2um_tx_enable == 1'b1) begin
pkt_out_rdreq <= 1'b0;
current_state <= trans_second_lisp_h1_s;
end
else begin
current_state <= wait_second_enable_s;
end
end
trans_second_lisp_h1_s: begin
um2cdp_data_valid <= 1'b1;
count_reg <= 7'd0;
um2cdp_data <= lisp_h1;
current_state <= trans_second_lisp_h2_5_s;
end
trans_second_lisp_h2_5_s: begin
count_reg <= count_reg + 1'b1;
case(count_reg[1:0])
3'd0: begin
um2cdp_data <= lisp_h2;
current_state <= trans_second_lisp_h2_5_s;
end
3'd1: begin
um2cdp_data <= lisp_h3;
current_state <= trans_second_lisp_h2_5_s;
end
3'd2: begin
um2cdp_data <= lisp_h4;
current_state <= trans_second_lisp_h2_5_s;
end
3'd3: begin
um2cdp_data <= lisp_h5;
pkt_out_rdreq <= 1'b1;
current_state <= trans_second_lisp_body_s;
end
endcase
end
trans_second_lisp_body_s: begin
if(pkt_out_q[138:136] ==3'b110) begin
um2cdp_data_valid <= 1'b1;
pkt_out_rdreq <= 1'b0;
cut_pkt_flag <= 1'b0;
um2cdp_data <={3'b110,pkt_out_q[135:0]};
//um2cdp_rule_wrreq <= 1'b1;
//um2cdp_rule <= {22'b0,rule_q_r[7:0]};
current_state <= idle_s1;
end
else begin
um2cdp_data_valid <= 1'b1;
um2cdp_data <=pkt_out_q[138:0];
current_state <= trans_second_lisp_body_s;
end
end
trans_body_s: begin
flag <= 1'b0;
if(pkt_out_q[138:136] == 3'b110) begin
um2cdp_data_valid <= 1'b1;
pkt_out_rdreq <= 1'b0;
um2cdp_data <={3'b110,pkt_out_q[135:0]};
current_state <= idle_s1;
end
else begin
current_state <= trans_body_s;
if(flag == 1'b1) begin
um2cdp_data_valid <= 1'b1;
um2cdp_data <={3'b101,pkt_out_q[135:0]};
end
else begin
um2cdp_data_valid <= 1'b1;
um2cdp_data <={3'b100,pkt_out_q[135:0]};
end
end
end
trans_ctl_s: begin
flag <= 1'b0;
if(pkt_ctl_q[138:136] == 3'b110) begin
um2cdp_data_valid <= 1'b1;
pkt_ctl_rdreq <= 1'b0;
um2cdp_data <={3'b110,pkt_ctl_q[135:0]};
//um2cdp_rule_wrreq <= 1'b1;
//um2cdp_rule <= {22'b0,8'h1};
current_state <= idle_s;
end
else begin
current_state <= trans_ctl_s;
if(flag == 1'b1) begin
um2cdp_data_valid <= 1'b1;
um2cdp_data <={3'b101,pkt_ctl_q[135:0]};
end
else begin
um2cdp_data_valid <= 1'b1;
um2cdp_data <={3'b100,pkt_ctl_q[135:0]};
end
end
end
endcase
end
fifo_20_64 rule_fifo(
.aclr (!reset),
.clock (clk),
.data (rule),
.rdreq (rule_rdreq),
.wrreq (rule_wr),
.empty (rule_empty),
.q (rule_q));
fifo_139_256 pkt_out_fifo(
.aclr (!reset),
.clock (clk),
.data (pkt_out),
.rdreq (pkt_out_rdreq),
.wrreq (pkt_out_valid),
.q (pkt_out_q),
.usedw (pkt_out_usedw));
fifo_139_256 pkt_ctl_fifo(
.aclr (!reset),
.clock (clk),
.data (pkt_ctl),
.rdreq (pkt_ctl_rdreq),
.wrreq (pkt_ctl_valid&(!mode)),
.q (pkt_ctl_q),
.usedw (pkt_ctl_usedw));
endmodule |
module ddio_in_4 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input [3:0] datain;
input inclock;
output [3:0] dataout_h;
output [3:0] dataout_l;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] dataout_h = sub_wire0[3:0];
wire [3:0] dataout_l = sub_wire1[3:0];
altddio_in altddio_in_component (
.datain (datain),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire1),
.aset (1'b0),
.inclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
altddio_in_component.intended_device_family = "Arria II GX",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 4;
endmodule |
module rule_32_30_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [29:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [29:0] q;
output [4:0] usedw;
wire [4:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [29:0] sub_wire3;
wire [4:0] usedw = sub_wire0[4:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [29:0] q = sub_wire3[29:0];
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 30,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module output_ctrl(
clk,
reset,
input2output_wrreq,//to input2output fifo;
input2output_data,
input2output_usedw,
um2cdp_rule, //rule, from user module;
//added by guotengfei 20120322, to CDP rule_fifo;
um2cdp_rule_wrreq,
cdp2um_rule_usedw,
cdp2um_tx_enable, //data ,from user module;
um2cdp_data_valid,
um2cdp_data,
pkt_valid_wrreq,//flag fifo,to crc gen;
pkt_valid,//[18:0],[18:17]:10-valid pkt and normal forward(depend on data[131:128]);
//11-valid pkt and copy;
//0x-invalid pkt and discard;
//[16:0]:if this pkt need copy([18:17]=2'b11),every bit is one rgmii output interface;
pkt_data_wrreq,//data fifo;
pkt_data,
pkt_data_usedw
);
input clk;
input reset;
input input2output_wrreq;
input [138:0]input2output_data;
output [7:0]input2output_usedw;
input [29:0]um2cdp_rule;
output cdp2um_tx_enable;
input um2cdp_data_valid;
input [138:0]um2cdp_data;
output pkt_valid_wrreq;
output [18:0]pkt_valid;
output pkt_data_wrreq;
output [138:0]pkt_data;
input [7:0]pkt_data_usedw;
//added by guotengfei
input um2cdp_rule_wrreq;
output [4:0]cdp2um_rule_usedw;
reg pkt_valid_wrreq;
reg [18:0]pkt_valid;
reg pkt_data_wrreq;
reg [138:0]pkt_data;
reg cdp2um_tx_enable;
//added by guotengfei
wire [4:0]cdp2um_rule_usedw;
reg um2cdp_rule_rdreq;
wire [29:0]um2cdp_rule_q;
reg input2output_rdreq;
wire [138:0]input2output_q;
wire [7:0]input2output_usedw;
wire um2cdp_rule_empty,um2cdp_rule_full;
reg [3:0]output_port_reg;//storage the output port number;
reg [7:0]cutter;//the cut number;
reg [7:0]counter;//cut number counter;
reg flag;//indicate the data come from where,user module or input2output fifo;
reg [2:0]current_state;
parameter idle=3'b0,
wait_rule=3'b001,
discard=3'b011,
copy=3'b010,
cut=3'b101;
always@(posedge clk or negedge reset)
if(!reset)
begin
input2output_rdreq<=1'b0;
cdp2um_tx_enable<=1'b0;
pkt_valid_wrreq<=1'b0;
pkt_data_wrreq<=1'b0;
counter<=8'b0;
cutter<=8'b0;
um2cdp_rule_rdreq <= 1'b0;//added
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
pkt_data_wrreq<=1'b0;
pkt_valid_wrreq<=1'b0;
input2output_rdreq<=1'b0;
um2cdp_rule_rdreq <= 1'b0; //added
if(pkt_data_usedw<8'd161)//data fifo can storage a full pkt,so need a rule;
begin
current_state<=wait_rule;
end
else //data fifo can't storage a full pkt;
begin
current_state<=idle;
end
end//end idle;
wait_rule:
begin
if(um2cdp_rule_empty != 1'b1)//the rule is coming;
begin
um2cdp_rule_rdreq <= 1'b1; //added
if(um2cdp_rule_q[29]==1'b0)//the data comes from user module; //modified by gtf changing um2cdp_rule to um2cdp_rule
begin
flag<=1'b0;
cdp2um_tx_enable<=1'b1;
end
else//the data comes from input2output fifo;
begin
flag<=1'b1;
input2output_rdreq<=1'b1;
end
case(um2cdp_rule_q[28:25])//the control command;
4'b0000://direct output;
begin
if(um2cdp_rule_q[0]==1'b1)//bp0:0000;
output_port_reg<=4'b0;
else if(um2cdp_rule_q[1]==1'b1)//bp1:0001;
output_port_reg<=4'd1;
else if(um2cdp_rule_q[2]==1'b1)//bp2:0010;
output_port_reg<=4'd2;
else if(um2cdp_rule_q[3]==1'b1)//bp3:0011;
output_port_reg<=4'd3;
else if(um2cdp_rule_q[4]==1'b1)//
output_port_reg<=4'd4;
else if(um2cdp_rule_q[5]==1'b1)//
output_port_reg<=4'd5;
else if(um2cdp_rule_q[6]==1'b1)//
output_port_reg<=4'd6;
else if(um2cdp_rule_q[7]==1'b1)//
output_port_reg<=4'd7;
else if(um2cdp_rule_q[8]==1'b1)//fp0;
output_port_reg<=4'd8;
else if(um2cdp_rule_q[9]==1'b1)//
output_port_reg<=4'd9;
else if(um2cdp_rule_q[10]==1'b1)//
output_port_reg<=4'd10;
else if(um2cdp_rule_q[11]==1'b1)//
output_port_reg<=4'd11;
else if(um2cdp_rule_q[12]==1'b1)//
output_port_reg<=4'd12;
else if(um2cdp_rule_q[13]==1'b1)//
output_port_reg<=4'd13;
else if(um2cdp_rule_q[14]==1'b1)//
output_port_reg<=4'd14;
else if(um2cdp_rule_q[15]==1'b1)//
output_port_reg<=4'd15;
else//the 17 100M interface;
output_port_reg<=4'd0;
pkt_valid[16:0]<=um2cdp_rule_q[16:0];
current_state<=copy;
end
4'b0001://discard the pkt;
begin
current_state<=discard;
end
/* 4'b0010://send to main control;
begin
current_state<=idle;//unused;
end*/
/*
4'b0011://copy;
begin
pkt_valid[16:0]<=um2cdp_rule_q[16:0];//the output port;
pkt_valid[18:17]<=2'b11;
current_state<=copy;
end*/
4'b0010://cut the pkt;
begin
if(um2cdp_rule_q[0]==1'b1)//bp0:0000;
output_port_reg<=4'b0;
else if(um2cdp_rule_q[1]==1'b1)//bp1:0001;
output_port_reg<=4'd1;
else if(um2cdp_rule_q[2]==1'b1)//bp2:0010;
output_port_reg<=4'd2;
else if(um2cdp_rule_q[3]==1'b1)//bp3:0011;
output_port_reg<=4'd3;
else if(um2cdp_rule_q[4]==1'b1)//
output_port_reg<=4'd4;
else if(um2cdp_rule_q[5]==1'b1)//
output_port_reg<=4'd5;
else if(um2cdp_rule_q[6]==1'b1)//
output_port_reg<=4'd6;
else if(um2cdp_rule_q[7]==1'b1)//
output_port_reg<=4'd7;
else if(um2cdp_rule_q[8]==1'b1)//fp0;
output_port_reg<=4'd8;
else if(um2cdp_rule_q[9]==1'b1)//
output_port_reg<=4'd9;
else if(um2cdp_rule_q[10]==1'b1)//
output_port_reg<=4'd10;
else if(um2cdp_rule_q[11]==1'b1)//
output_port_reg<=4'd11;
else if(um2cdp_rule_q[12]==1'b1)//
output_port_reg<=4'd12;
else if(um2cdp_rule_q[13]==1'b1)//
output_port_reg<=4'd13;
else if(um2cdp_rule_q[14]==1'b1)//
output_port_reg<=4'd14;
else if(um2cdp_rule_q[15]==1'b1)//
output_port_reg<=4'd15;
else//the 17 100M interface;
output_port_reg<=4'd0;
/*if(um2cdp_rule_q[24:17]==8'b0)//discard;
begin
current_state<=discard;
end
else if(um2cdp_rule_q[24:17]==8'hff)//normal output;
begin
pkt_valid[16:0]<=um2cdp_rule_q[16:0];
current_state<=normal_output;
end
else
begin*/
cutter<=um2cdp_rule_q[24:17];
pkt_valid[16:0]<=um2cdp_rule_q[16:0];
current_state<=cut;
// end
end
default://discard?
begin
current_state<=discard;
end
endcase
end
else//the rule is not coming;
begin
current_state<=wait_rule;
end
end//end wait_state;
discard:
begin
pkt_data_wrreq<=1'b0;
pkt_valid_wrreq<=1'b0;
um2cdp_rule_rdreq <= 1'b0;
if(flag==1'b0)//the data come from user module;
begin
if(um2cdp_data_valid==1'b1)//the data is coming;
begin
cdp2um_tx_enable<=1'b0;
if(um2cdp_data[138:136]==3'b110)//tail;
begin
current_state<=idle;
end
else
begin
current_state<=discard;
end
end
else
begin
current_state<=discard;
end
end
else//the data come from input2output fifo;
begin
if(input2output_q[138:136]==3'b110)//tail;
begin
input2output_rdreq<=1'b0;
current_state<=idle;
end
else
begin
input2output_rdreq<=1'b1;
current_state<=discard;
end
end
end//end discard;
copy:
begin
um2cdp_rule_rdreq <= 1'b0;
if(flag==1'b0)//the data from user module;
begin
if(um2cdp_data_valid==1'b1)//the data is coming;
begin
cdp2um_tx_enable<=1'b0;
if(um2cdp_data[138:136]==3'b110)//tail;
begin
pkt_data_wrreq<=1'b1;
pkt_data<=um2cdp_data;
pkt_valid_wrreq<=1'b1;
pkt_valid[18:17]<=2'b11;
current_state<=idle;
end
else//middle;
begin
pkt_data_wrreq<=1'b1;
pkt_data<=um2cdp_data;
current_state<=copy;
end
end
else
begin
current_state<=copy;
end
end
else//the data from input2output fifo;
begin
if(input2output_q[138:136]==3'b101)//header;
begin
pkt_data_wrreq<=1'b1;
pkt_data<=input2output_q;
input2output_rdreq<=1'b1;
current_state<=copy; //header?middle????????????
end
else if(input2output_q[138:136]==3'b110)//tail;
begin
pkt_data_wrreq<=1'b1;
pkt_data<=input2output_q;
pkt_valid_wrreq<=1'b1;
pkt_valid[18:17]<=2'b11;
input2output_rdreq<=1'b0;
current_state<=idle;
end
else// middle;
begin
pkt_data_wrreq<=1'b1;
pkt_data<=input2output_q;
input2output_rdreq<=1'b1;
current_state<=copy;
end
end
end//end copy;
cut:
begin
um2cdp_rule_rdreq <= 1'b0;
if(flag==1'b0)//the data from user module;
begin
if(um2cdp_data_valid==1'b1)//the data is coming;
begin
cdp2um_tx_enable<=1'b0;
if(counter==cutter+2'b11)//equal the need number;
begin
pkt_data_wrreq<=1'b1;
pkt_data<=um2cdp_data;
pkt_data[138:136]<=3'b110;
pkt_data[135:132]<=4'b1111;
pkt_valid_wrreq<=1'b1;
pkt_valid[18:17]<=2'b10;
//pkt_valid[16:0]<=17'b0;
counter<=8'b0;
cutter<=8'b0;
current_state<=discard;
end
else//
begin
if(um2cdp_data[138:136]==3'b101)//head;
begin
counter<=counter+1'b1;
pkt_data_wrreq<=1'b1;
pkt_data<=um2cdp_data;
pkt_data[131:128]<=output_port_reg;
current_state<=cut;
end
else
begin
counter<=counter+1'b1;
pkt_data_wrreq<=1'b1;
pkt_data<=um2cdp_data;
current_state<=cut;
end
end
end
else
begin
current_state<=cut;
end
end
else//the data from input2output fifo;
begin
if(counter==cutter+2'b11)
begin
pkt_data_wrreq<=1'b1;
pkt_data<=input2output_q;
pkt_data[138:136]<=3'b110;
pkt_valid_wrreq<=1'b1;
pkt_valid[18:17]<=2'b10;
//pkt_valid[16:0]<=17'b0;
counter<=8'b0;
cutter<=8'b0;
input2output_rdreq<=1'b1;
current_state<=discard;
end
else
begin
if(input2output_q[138:136]==3'b101)//head;
begin
counter<=counter+1'b1;
pkt_data_wrreq<=1'b1;
pkt_data<=input2output_q;
pkt_data[131:128]<=output_port_reg;
input2output_rdreq<=1'b1;
current_state<=cut;
end
else
begin
counter<=counter+1'b1;
pkt_data_wrreq<=1'b1;
pkt_data<=input2output_q;
input2output_rdreq<=1'b1;
current_state<=cut;
end
end
end
end//end cut;
default:
begin
current_state<=idle;
end
endcase//endcase;
end
input2output_128_139 input2output_128_139(
.aclr(!reset),
.clock(clk),
.data(input2output_data),
.rdreq(input2output_rdreq),
//.wrreq(1'b0),
.wrreq(input2output_wrreq), //changed by litao, 20120320
.q(input2output_q),
.usedw(input2output_usedw)
);
//added by guotengfei 20120322
rule_32_30_fifo rule_32_30(
.aclr(!reset),
.clock(clk),
.data(um2cdp_rule),
.rdreq(um2cdp_rule_rdreq),
.wrreq(um2cdp_rule_wrreq),
.q(um2cdp_rule_q),
.usedw(cdp2um_rule_usedw),
.empty(um2cdp_rule_empty),
.full(um2cdp_rule_full)
);
endmodule |
module check_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
output [6:0] rdusedw;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [0:0] sub_wire2;
wire [6:0] sub_wire3;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [0:0] q = sub_wire2[0:0];
wire [6:0] rdusedw = sub_wire3[6:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2),
.rdusedw (sub_wire3)
// synopsys translate_off
,
.rdfull (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
module tx139_gmii_1000(
clk,
reset,
gmii_txclk,
crc_gen_to_txfifo_wrreq,
crc_gen_to_txfifo_data,
pkt_output_valid_wrreq,
pkt_output_valid,
gmii_txd,
gmii_txen,
gmii_txer,
txfifo_data_usedw,//output_data_usedw0;
port_send
);
input clk;//system clk;
input reset;
input gmii_txclk;
input crc_gen_to_txfifo_wrreq;//data to txfifo;
input [138:0]crc_gen_to_txfifo_data;
input pkt_output_valid_wrreq;//flag to flagfifo;
input pkt_output_valid;
output [7:0]gmii_txd;//1 btye gmii data;
output gmii_txen;
output gmii_txer;
output [7:0]txfifo_data_usedw;//data fifo usedw;
output port_send;
reg port_send;
reg [7:0]gmii_txd;
reg gmii_txen;
reg gmii_txer;
reg [138:0]data_reg;//storage data,so can split it to 16 bytes;
reg [3:0]preamble_counter;//preamble counter,1000M:7 '55',1 'd5';100M:15 '5', 1'd'
reg [3:0]counter;//the 12 clock latency between tow pkt;
wire [5:0] txfifo_flag_rdusedw; //added by litao,
reg txfifo_flag_rdreq;
wire txfifo_flag;
wire empty;
wire [7:0]txfifo_data_usedw;
reg txfifo_data_rdreq;
wire [138:0]txfifo_data;
reg [5:0]current_state;
parameter
idle=6'h0,
preamble=6'h01,
byte1=6'h02,
byte2=6'h03,
byte3=6'h04,
byte4=6'h05,
byte5=6'h06,
byte6=6'h07,
byte7=6'h08,
byte8=6'h09,
byte9=6'h0a,
byte10=6'h0b,
byte11=6'h0c,
byte12=6'h0d,
byte13=6'h0e,
byte14=6'h0f,
byte15=6'h10,
byte16=6'h11,
discard=6'h12;
always@(posedge gmii_txclk or negedge reset)
if(!reset)
begin
txfifo_data_rdreq<=1'b0;
txfifo_flag_rdreq<=1'b0;
gmii_txen<=1'b0;
gmii_txer<=1'b0;
preamble_counter<=4'b0;
port_send<=1'b0;
counter<=4'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
txfifo_data_rdreq<=1'b0;
txfifo_flag_rdreq<=1'b0;
gmii_txen<=1'b0;
gmii_txer<=1'b0;
preamble_counter<=4'b0;
if(counter==4'd11)begin
if((!empty)&&(txfifo_data_usedw!=1'b0))//flag fifo no empty; //added by litao
begin
counter<=4'b0;
if(txfifo_flag==1'b1)//data fifo have a valid pkt;
begin
txfifo_flag_rdreq<=1'b1;
if(txfifo_data[138:136]==3'b101)//head;
begin
port_send<=1'b1;
txfifo_data_rdreq<=1'b1;
data_reg<=txfifo_data;
current_state<=preamble;
end
else//if the first is not head ,so discard it;
begin
current_state<=discard;
end
end
else//data fifo have a invalid pkt;
begin
txfifo_flag_rdreq<=1'b1;
current_state<=discard;
end
end
else//data fifo empty;
begin
current_state<=idle;
end
end//end counter;
else
begin
counter<=counter+1'b1;
current_state<=idle;
end
end//end idle;
byte1:
begin
txfifo_flag_rdreq<=1'b0;
txfifo_data_rdreq<=1'b0;
if(data_reg[138:136]==3'b101)//head;
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[127:120];
current_state<=byte2;
end
else if(data_reg[138:136]==3'b110)//tail;
begin
if(data_reg[135:132]==4'b0)//only one valid byte;
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[127:120];
current_state<=idle;
end
else//more than one byte;
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[127:120];
current_state<=byte2;
end
end
else//middle;
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[127:120];
current_state<=byte2;
end
end//end byte1;
byte2:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[119:112];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b0001)//two valid byte;
current_state<=idle;
else//>2 valid byte;
current_state<=byte3;
else
current_state<=byte3;
end//byte2;
byte3:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[111:104];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b0010)//3 valid byte;
current_state<=idle;
else//>3 valid byte;
current_state<=byte4;
else
current_state<=byte4;
end//byte3;
byte4:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[103:96];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b0011)//4 valid byte;
current_state<=idle;
else//>4 valid byte;
current_state<=byte5;
else
current_state<=byte5;
end//byte4;
byte5:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[95:88];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b0100)//5 valid byte;
current_state<=idle;
else//>5 valid byte;
current_state<=byte6;
else
current_state<=byte6;
end//byte5;
byte6:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[87:80];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b0101)//6 valid byte;
current_state<=idle;
else//>6 valid byte;
current_state<=byte7;
else
current_state<=byte7;
end//byte6;
byte7:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[79:72];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b0110)//7 valid byte;
current_state<=idle;
else//>7 valid byte;
current_state<=byte8;
else
current_state<=byte8;
end//byte7;
byte8:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[71:64];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b0111)//8 valid byte;
current_state<=idle;
else//>8 valid byte;
current_state<=byte9;
else
current_state<=byte9;
end//byte8;
byte9:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[63:56];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b1000)//9 valid byte;
current_state<=idle;
else//>9 valid byte;
current_state<=byte10;
else
current_state<=byte10;
end//byte9;
byte10:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[55:48];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b1001)//10 valid byte;
current_state<=idle;
else//>10 valid byte;
current_state<=byte11;
else
current_state<=byte11;
end//byte10;
byte11:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[47:40];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b1010)//11 valid byte;
current_state<=idle;
else//>11 valid byte;
current_state<=byte12;
else
current_state<=byte12;
end//byte11;
byte12:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[39:32];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b1011)//12 valid byte;
current_state<=idle;
else//>12 valid byte;
current_state<=byte13;
else
current_state<=byte13;
end//byte12;
byte13:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[31:24];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b1100)//13 valid byte;
current_state<=idle;
else//>13 valid byte;
current_state<=byte14;
else
current_state<=byte14;
end//byte13;
byte14:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[23:16];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b1101)//14 valid byte;
current_state<=idle;
else//>14 valid byte;
current_state<=byte15;
else
current_state<=byte15;
end//byte14;
byte15:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[15:8];
if(data_reg[138:136]==3'b110)//tail;
if(data_reg[135:132]==4'b1110)//15 valid byte;
current_state<=idle;
else//>15 valid byte;
current_state<=byte16;
else
current_state<=byte16;
end//byte15;
byte16:
begin
gmii_txen<=1'b1;
gmii_txd<=data_reg[7:0];
if(data_reg[138:136]==3'b110)//tail;
current_state<=idle;
else
begin
txfifo_data_rdreq<=1'b1;
data_reg<=txfifo_data;
current_state<=byte1;
end
end//byte16;
discard:
begin
txfifo_flag_rdreq <= 1'b0; //modified by litao, 20120321
txfifo_data_rdreq<=1'b1;
if(txfifo_data[138:136]==3'b110)
begin
txfifo_data_rdreq<=1'b0;
current_state<=idle;
end
else
current_state<=discard;
end//end discard;
preamble:
begin
txfifo_flag_rdreq<=1'b0;
txfifo_data_rdreq<=1'b0;
port_send<=1'b0;
if(preamble_counter<4'b0111)//7 '55';
begin
gmii_txen<=1'b1;
gmii_txd<=8'h55;
preamble_counter<=preamble_counter+1'b1;
current_state<=preamble;
end
else//'d5';
begin
gmii_txen<=1'b1;
gmii_txd<=8'hd5;
preamble_counter <= 4'b0;
current_state<=byte1;
end
end//end preamble;
default:
begin
current_state<=idle;
end//end default;
endcase
end//end else;
asyn_256_139 asyn_256_139(
.aclr(!reset),
.wrclk(clk),
.wrreq(crc_gen_to_txfifo_wrreq),
.data(crc_gen_to_txfifo_data),
.rdclk(gmii_txclk),
.rdreq(txfifo_data_rdreq),
.q(txfifo_data),
.wrusedw(txfifo_data_usedw)
);
asyn_64_1 asyn_64_1(
.aclr(!reset),
.wrclk(clk),
.wrreq(pkt_output_valid_wrreq),
.data(pkt_output_valid),
.rdclk(gmii_txclk),
.rdreq(txfifo_flag_rdreq),
.q(txfifo_flag),
.rdempty(empty),
.rdusedw(txfifo_flag_rdusedw) //added by litao
);
endmodule |
module check_100_1000(
rgmii_rx_clk,//Íø¿Úrgmii_rx_clk 25MHzʱÍø¿ÚËÙÂÊΪ100M¡¢125MHzʱÍø¿ÚËÙÂÊΪ1000M
sys_clk,//ÓÃ125MµÄ±¾°åʱÖÓ
sys_rst_n,
SPEED_IS_100_1000//1£º100M 0:1000M
);
input rgmii_rx_clk;
input sys_clk;
input sys_rst_n;
output SPEED_IS_100_1000;
reg SPEED_IS_100_1000;
reg [6:0]timer;
reg rst_fifo;
reg wrreq;
reg [1:0]state;
parameter idle_s = 2'b00,
wait_s = 2'b01,
rst_fifo_s = 2'b10;
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(sys_rst_n==1'b0)begin
SPEED_IS_100_1000 <= 1'b0;//ĬÈÏΪ1000M
timer <= 7'b0;
state <= idle_s;
end
else case(state)
idle_s:begin
if(timer[3]==1'b1)begin
wrreq <= 1'b1;
timer <= 7'b0;
state <= wait_s;
end
else begin
timer <= timer + 1'b1;
state <= idle_s;
end
end
wait_s:begin
if(timer[6]==1'b1)begin
if(rdusedw <= 7'd40)begin
SPEED_IS_100_1000 <= 1'b1;//100M
end
else begin
SPEED_IS_100_1000 <= 1'b0;//1000M
end
timer <= 7'b0;
wrreq <= 1'b0;
state <= rst_fifo_s;
end
else begin
timer <= timer + 1'b1;
state <= wait_s;
end
end
rst_fifo_s:begin
if(timer[6]==1'b1)begin
rst_fifo <= 1'b0;
timer <= 7'b0;
state <= idle_s;
end
else begin
rst_fifo <= 1'b1;
timer <= timer + 1'b1;
state <= rst_fifo_s;
end
end
default:begin
SPEED_IS_100_1000 <= 1'b0;//ĬÈÏΪ1000M
timer <= 7'b0;
state <= idle_s;
end
endcase
end
wire [6:0]rdusedw;
check_fifo check_fifo(
.aclr(rst_fifo|(~sys_rst_n)),
.data(1'b1),
.rdclk(sys_clk),
.rdreq(1'b0),
.wrclk(rgmii_rx_clk),
.wrreq(wrreq),
.q(),
.rdempty(),
.rdusedw(rdusedw),
.wrfull());
endmodule |
module level2_256_139 (
aclr,
clock,
data,
rdreq,
wrreq,
q,
usedw);
input aclr;
input clock;
input [138:0] data;
input rdreq;
input wrreq;
output [138:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire [138:0] sub_wire1;
wire [7:0] usedw = sub_wire0[7:0];
wire [138:0] q = sub_wire1[138:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.q (sub_wire1)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.empty (),
.full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 139,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module rgmii_gmii
(
reset_n,
// RGMII Interface
rgmii_txd,
rgmii_tx_ctl,
rgmii_tx_clk,
rgmii_rxd,
rgmii_rx_ctl,
rgmii_rx_clk,
// GMII Interface
GTX_CLK,
GMII_TXD_FROM_CORE,
GMII_TX_EN_FROM_CORE,
GMII_TX_ER_FROM_CORE,
// GRX_CLK,
GMII_RXD_TO_CORE,
GMII_RX_DV_TO_CORE,
GMII_RX_ER_TO_CORE,
clk_tx,
SPEED_IS_10_100
);
input SPEED_IS_10_100;
// Port declarations
input reset_n;
input GTX_CLK;
input clk_tx;
// RGMII Interface
output [3:0] rgmii_txd;
output rgmii_tx_ctl;
output rgmii_tx_clk;
input [3:0] rgmii_rxd;
input rgmii_rx_ctl;
input rgmii_rx_clk;
// GMII Interface8
input [7:0] GMII_TXD_FROM_CORE;
input GMII_TX_EN_FROM_CORE;
input GMII_TX_ER_FROM_CORE;
output [7:0] GMII_RXD_TO_CORE;
output GMII_RX_DV_TO_CORE;
output GMII_RX_ER_TO_CORE;
reg [3:0] rgmii_txd_rising;
reg [3:0] rgmii_txd_falling;
reg rgmii_tx_ctl_rising;
reg rgmii_tx_ctl_falling;
reg [7:0] GMII_RXD_TO_CORE;
reg GMII_RX_DV_TO_CORE;
reg GMII_RX_ER_TO_CORE;
wire [3:0] rgmii_rxd_rising;
wire [3:0] rgmii_rxd_falling;
wire rgmii_rx_ctl_rising;
wire rgmii_rx_ctl_falling;
wire rgmii_tx_clk;
ddio_out ddio_out_data(
.aclr(!reset_n),
.datain_h(rgmii_txd_rising),
.datain_l(rgmii_txd_falling),
.outclock(GTX_CLK),
.dataout(rgmii_txd));
ddio_out_1 ddio_out_ctl(
.aclr(!reset_n),
.datain_h(rgmii_tx_ctl_rising),
.datain_l(rgmii_tx_ctl_falling),
.outclock(GTX_CLK),
.dataout(rgmii_tx_ctl));
ddio_out_1 ddio_out_clk(
.aclr(!reset_n),
.datain_h(1'b1),
.datain_l(1'b0),
.outclock(clk_tx),
.dataout(rgmii_tx_clk));
ddio_in_4 ddio_in_data(
.aclr(!reset_n),
.datain(rgmii_rxd),
.inclock(rgmii_rx_clk),
.dataout_h(rgmii_rxd_rising),
.dataout_l(rgmii_rxd_falling));
ddio_in_1 ddio_in_ctl(
.aclr(!reset_n),
.datain(rgmii_rx_ctl),
.inclock(rgmii_rx_clk),
.dataout_h(rgmii_rx_ctl_rising),
.dataout_l(rgmii_rx_ctl_falling));
//·¢ËÍ¡£GMII½Ó¿Úת»»³ÉRGMII½Ó¿Ú¡£SPEED_IS_10_100Ϊ1 ±íʾMII °ÙÕ×£» Ϊ0±íʾRGMII ǧÕ×
always@(posedge GTX_CLK or negedge reset_n)
begin
if(!reset_n)
begin
rgmii_txd_rising <= 4'b0;
rgmii_txd_falling <= 4'b0;
rgmii_tx_ctl_rising <= 1'b0;
rgmii_tx_ctl_falling <= 1'b0;
end
else
begin
rgmii_txd_rising <= GMII_TXD_FROM_CORE[3:0];
rgmii_tx_ctl_rising <= GMII_TX_EN_FROM_CORE;
rgmii_tx_ctl_falling <= GMII_TX_EN_FROM_CORE ^ GMII_TX_ER_FROM_CORE;
if(SPEED_IS_10_100)//100M
rgmii_txd_falling <= GMII_TXD_FROM_CORE[3:0];
else//1000M
rgmii_txd_falling <= GMII_TXD_FROM_CORE[7:4];
end
end
reg [3:0] rgmii_rxd_rising_r;
reg rgmii_rx_ctl_rising_r;
//½ÓÊÕ¡£RGMII½Ó¿Úת»»³ÉGMII½Ó¿Ú
always@(posedge rgmii_rx_clk or negedge reset_n )
begin
if(!reset_n)
begin
GMII_RXD_TO_CORE <= 8'b0;
GMII_RX_DV_TO_CORE <= 1'b0;
GMII_RX_ER_TO_CORE <= 1'b0;
rgmii_rxd_rising_r <= 4'b0;
rgmii_rx_ctl_rising_r <= 1'b0;
end
else
begin
GMII_RX_DV_TO_CORE <= rgmii_rx_ctl_rising_r;
GMII_RX_ER_TO_CORE <= rgmii_rx_ctl_rising_r ^ rgmii_rx_ctl_falling;
GMII_RXD_TO_CORE[7:4] <= rgmii_rxd_falling;
GMII_RXD_TO_CORE[3:0] <= rgmii_rxd_rising_r;
rgmii_rxd_rising_r <= rgmii_rxd_rising;
rgmii_rx_ctl_rising_r <= rgmii_rx_ctl_rising;
end
end
endmodule |
module ddio_out_1 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input datain_h;
input datain_l;
input outclock;
output dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout = sub_wire1;
wire sub_wire2 = datain_h;
wire sub_wire3 = sub_wire2;
wire sub_wire4 = datain_l;
wire sub_wire5 = sub_wire4;
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (sub_wire3),
.aclr (aclr),
.datain_l (sub_wire5),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Arria II GX",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 1;
endmodule |
module ddio_in_1 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input datain;
input inclock;
output dataout_h;
output dataout_l;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] sub_wire2;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout_h = sub_wire1;
wire [0:0] sub_wire3 = sub_wire2[0:0];
wire dataout_l = sub_wire3;
wire sub_wire4 = datain;
wire sub_wire5 = sub_wire4;
altddio_in altddio_in_component (
.datain (sub_wire5),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire2),
.aset (1'b0),
.inclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
altddio_in_component.intended_device_family = "Arria II GX",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 1;
endmodule |
module rule_32_30 (
aclr,
clock,
data,
rdreq,
wrreq,
q,
usedw);
input aclr;
input clock;
input [29:0] data;
input rdreq;
input wrreq;
output [29:0] q;
output [4:0] usedw;
wire [4:0] sub_wire0;
wire [29:0] sub_wire1;
wire [4:0] usedw = sub_wire0[4:0];
wire [29:0] q = sub_wire1[29:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.usedw (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.empty (),
.full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 30,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module rx_tx_1000(
clk_125m_core,
clk_25m_core,
clk_25m_tx,//100M RGMII TX CLK
clk_125m_tx,//1000M RGMII TX CLK
reset,
rgmii_txd,
rgmii_tx_ctl,
rgmii_tx_clk,
rgmii_rxd,
rgmii_rx_ctl,
rgmii_rx_clk,
crc_data_valid,//rx data fifo
crc_data,
pkt_usedw,
pkt_valid_wrreq,
pkt_valid,
crc_gen_to_txfifo_wrreq,//tx fifo;
crc_gen_to_txfifo_data,
txfifo_data_usedw,
pkt_output_valid_wrreq,
pkt_output_valid,
port_receive,
port_discard,
port_send,
port_pream
);
input clk_125m_core;
input clk_25m_core;
input clk_25m_tx;
input clk_125m_tx;
input reset;
output [3:0]rgmii_txd;
output rgmii_tx_ctl;
output rgmii_tx_clk;
input [3:0]rgmii_rxd;
input rgmii_rx_ctl;
input rgmii_rx_clk;
output crc_data_valid;//to data fifo(crc check module);
output [138:0] crc_data;
input [7:0]pkt_usedw;
output pkt_valid_wrreq;//a full pkt,to flag fifo;
output pkt_valid;
input crc_gen_to_txfifo_wrreq;//data to txfifo;
input [138:0]crc_gen_to_txfifo_data;
output [7:0]txfifo_data_usedw;//data fifo usedw;
input pkt_output_valid_wrreq;//flag to flagfifo;
input pkt_output_valid;
output port_receive;
output port_discard;
output port_send;
output port_pream;
wire [3:0]rgmii_txd;
wire rgmii_tx_ctl;
wire rgmii_tx_clk;
wire [7:0]gmii_txd;
wire gmii_txen;
wire gmii_txer;
//wire gmii_txclk;//gmii input clk;
wire [7:0]gmii_rxd;
wire gmii_rxen;
wire gmii_rxer;
wire gmii_rx_clk;//gmii output clk;
wire crc_data_valid;//to data fifo(crc check module);
wire [138:0] crc_data;
wire pkt_valid_wrreq;//a full pkt,to flag fifo;
wire pkt_valid;
wire [7:0]txfifo_data_usedw;
wire port_receive;
wire port_discard;
wire port_send;
//wire SPEED_IS_100_1000;
wire port_pream;
gmii_139_1000 gmii_139(
.clk(rgmii_rx_clk),
.reset(reset),
.gmii_rxd(gmii_rxd),
.gmii_rxdv(gmii_rxen),
.gmii_rxer(gmii_rxer),
.crc_data_valid(crc_data_valid),
.crc_data(crc_data),
.pkt_usedw(pkt_usedw),
.pkt_valid_wrreq(pkt_valid_wrreq),
.pkt_valid(pkt_valid),
.port_receive(port_receive),
.port_discard(port_discard),
.port_pream(port_pream)
);
rgmii_gmii rgmii_gmii(
.reset_n(reset),
// RGMII Interface
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.rgmii_tx_clk(rgmii_tx_clk),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.rgmii_rx_clk(rgmii_rx_clk),
// GMII Interface
.GTX_CLK(clk_125m_core),
.GMII_TXD_FROM_CORE(gmii_txd),
.GMII_TX_EN_FROM_CORE(gmii_txen),
.GMII_TX_ER_FROM_CORE(gmii_txer),
// .GRX_CLK(gmii_rx_clk),
.GMII_RXD_TO_CORE(gmii_rxd),
.GMII_RX_DV_TO_CORE(gmii_rxen),
.GMII_RX_ER_TO_CORE(gmii_rxer),
.clk_tx(clk_125m_tx),
.SPEED_IS_10_100(1'b0)//1£º100M 0:1000M
);
tx139_gmii_1000 tx139_gmii(
.clk(clk_125m_core),//system clk;
.reset(reset),
.gmii_txclk(clk_125m_core),
.crc_gen_to_txfifo_wrreq(crc_gen_to_txfifo_wrreq),
.crc_gen_to_txfifo_data(crc_gen_to_txfifo_data),
.pkt_output_valid_wrreq(pkt_output_valid_wrreq),
.pkt_output_valid(pkt_output_valid),
.gmii_txd(gmii_txd),
.gmii_txen(gmii_txen),
.gmii_txer(gmii_txer),
.txfifo_data_usedw(txfifo_data_usedw),//output_data_usedw0;
.port_send(port_send)
);
endmodule |
module level2_64_19 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [18:0] data;
input rdreq;
input wrreq;
output empty;
output [18:0] q;
wire sub_wire0;
wire [18:0] sub_wire1;
wire empty = sub_wire0;
wire [18:0] q = sub_wire1[18:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.empty (sub_wire0),
.q (sub_wire1)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 19,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module ddio_out (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [3:0] datain_h;
input [3:0] datain_l;
input outclock;
output [3:0] dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] dataout = sub_wire0[3:0];
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (datain_h),
.aclr (aclr),
.datain_l (datain_l),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Arria II GX",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 4;
endmodule |
module input_ctrl(
clk,
reset,
crc_check_wrreq,//data fifo;
crc_check_data,
crc_usedw,
crc_result_wrreq,//crc check fifo;
crc_result,
um2cdp_tx_enable,//to user module;
cdp2um_data_valid,
cdp2um_data,
input2output_wrreq,//to output control module;
input2output_data,
input2output_usedw,
um2cdp_path
);
input clk;
input reset;
input crc_check_wrreq;
input [138:0]crc_check_data;
output [7:0]crc_usedw;
input crc_result_wrreq;
input crc_result;
input um2cdp_tx_enable;
output cdp2um_data_valid;
output [138:0]cdp2um_data;
output input2output_wrreq;
output [138:0]input2output_data;
input [7:0]input2output_usedw;
input um2cdp_path; //added by mxl_ccz_lq_0423 to define the direction of packets(to CDP itself or to UM);
wire [7:0]crc_usedw;
reg cdp2um_data_valid;
reg [138:0]cdp2um_data;
reg input2output_wrreq;
reg [138:0]input2output_data;
reg [138:0]data_reg;//storage the data,judge the last 4 byte,discard the crc;
reg level2_fifo_rdreq;
wire [138:0]level2_fifo_q;
reg flag_fifo_rdreq;
wire flag_fifo_q;
wire flag_fifo_empty;
reg [1:0]current_state;
parameter idle=2'b0,
transmit=2'b01,
discard=2'b10,
over_4byte=2'b11;
always@(posedge clk or negedge reset)
if(!reset)
begin
level2_fifo_rdreq<=1'b0;
flag_fifo_rdreq<=1'b0;
cdp2um_data_valid<=1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
flag_fifo_rdreq<=1'b0;
level2_fifo_rdreq<=1'b0;
cdp2um_data_valid<=1'b0;
input2output_wrreq<=1'b0;
if(um2cdp_tx_enable)//user module needs data;
begin
if((um2cdp_path == 1'b1 && input2output_usedw<8'd161) || um2cdp_path == 1'b0)//input_output_fifo can storage a full pkt or the packets are sent to UM;
begin
if(!flag_fifo_empty)//flag fifo is not empty;
begin
if(flag_fifo_q==1'b1)//the data is valid;
begin
flag_fifo_rdreq<=1'b1;
level2_fifo_rdreq<=1'b1;
//cdp2um_data_valid<=1'b1;
//cdp2um_data<=level2_fifo_q;
//input2output_wrreq<=1'b1;
//input2output_data<=level2_fifo_q;
current_state<=transmit;
end
else//the data is invalid,so discard;
begin
flag_fifo_rdreq<=1'b1;
level2_fifo_rdreq<=1'b1;
current_state<=discard;
end
end
else
begin
current_state<=idle;
end
end
else//can't storage a full pkt;
begin
current_state<=idle;
end
end
else//
begin
current_state<=idle;
end
end//end idle;
transmit:
begin
flag_fifo_rdreq<=1'b0;
level2_fifo_rdreq<=1'b0;
cdp2um_data_valid<=1'b0;
input2output_wrreq<=1'b0;
data_reg<=level2_fifo_q;
if(level2_fifo_q[138:136]==3'b101)//header;
begin
level2_fifo_rdreq<=1'b1;
cdp2um_data_valid<=1'b0;
cdp2um_data<=data_reg;
input2output_wrreq<=1'b0;
input2output_data<=data_reg;
current_state<=transmit;
end
else if(level2_fifo_q[138:136]==3'b110)//tail;
begin
level2_fifo_rdreq<=1'b0;
if(level2_fifo_q[135:132]>4'b0011)//the last word have >4bytes valid data;
begin
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
current_state<=over_4byte;
end
else if(level2_fifo_q[135:132]==4'b0011)
begin
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
cdp2um_data[138:136]<=3'b110;
cdp2um_data[135:132]<=4'b1111;
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
input2output_data[138:136]<=3'b110;
input2output_data[135:132]<=4'b1111;
current_state<=idle;
end
else
begin
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
cdp2um_data[138:136]<=3'b110;
cdp2um_data[135:132]<=4'b1111-(4'b0011-level2_fifo_q[135:132]);
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
input2output_data[138:136]<=3'b110;
input2output_data[135:132]<=4'b1111-(4'b0011-level2_fifo_q[135:132]);
current_state<=idle;
end
end
else//middle;
begin
level2_fifo_rdreq<=1'b1;
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
current_state<=transmit;
end
end//end transmit;
discard:
begin
flag_fifo_rdreq<=1'b0;
level2_fifo_rdreq<=1'b0;
if(level2_fifo_q[138:136]==3'b110)//tail;
begin
//level2_fifo_rdreq<=1'b1;
current_state<=idle;
end
else//middle;
begin
level2_fifo_rdreq<=1'b1;
current_state<=discard;
end
end
over_4byte:
begin
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
cdp2um_data[135:132]<=data_reg[135:132]-4'b0100;
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
input2output_data[135:132]<=data_reg[135:132]-4'b0100;
current_state<=idle;
end
default:
begin
current_state<=idle;
end
endcase//endcase;
end
level2_256_139 level2_256_139(//level2 data fifo;
.aclr(!reset),
.clock(clk),
.data(crc_check_data),
.rdreq(level2_fifo_rdreq),
.wrreq(crc_check_wrreq),
.q(level2_fifo_q),
.usedw(crc_usedw)
);
rx_64_1 rx_64_1(//crc check result fifo;
.aclr(!reset),
.clock(clk),
.data(crc_result),
.rdreq(flag_fifo_rdreq),
.wrreq(crc_result_wrreq),
.empty(flag_fifo_empty),
.q(flag_fifo_q)
);
endmodule |
module pkt_input_ctrl(
clk,
reset,
cdp2um_tx_enable,
cdp2um_data_valid,
cdp2um_data,
pkt_input_ctrl_wrreq,
pkt_input_ctrl_data,
pkt_input_ctrl_usedw,
pkt_input_ctrl_valid_wrreq,
pkt_input_ctrl_valid
);
input clk;
input reset;
input pkt_input_ctrl_wrreq;
input [138:0] pkt_input_ctrl_data;
output [7:0] pkt_input_ctrl_usedw;
input pkt_input_ctrl_valid_wrreq;
input pkt_input_ctrl_valid;
input cdp2um_tx_enable;
output cdp2um_data_valid;
output [138:0] cdp2um_data;
reg [138:0] cdp2um_data;
reg cdp2um_data_valid;
reg [2:0] state;
parameter idle=3'b000,
transmit=3'b001,
tail=3'b010;
always@(posedge clk or negedge reset)
if(!reset)
begin
cdp2um_data_valid<=1'b0;
state<=idle;
end
else
begin
case(state)
idle:
begin
if(cdp2um_tx_enable)
begin
if((!pkt_input_ctrl_valid_empty)&&(pkt_input_ctrl_valid_q==1'b1))
begin
pkt_input_ctrl_valid_rdreq<=1'b1;
pkt_input_ctrl_rdreq<=1'b1;
state<=transmit;
end
else
begin
state<=idle;
end
end
else
begin
state<=idle;
end
end
transmit:
begin
pkt_input_ctrl_valid_rdreq<=1'b0;
pkt_input_ctrl_rdreq<=1'b0;
if(pkt_input_ctrl_q[138:136]==3'b110)//tail
begin
pkt_input_ctrl_rdreq<=1'b0;
cdp2um_data_valid<=1'b1;
cdp2um_data<=pkt_input_ctrl_q;
state<=tail;
end
else
begin
pkt_input_ctrl_rdreq<=1'b1;
cdp2um_data_valid<=1'b1;
cdp2um_data<=pkt_input_ctrl_q;
state<=transmit;
end
end
tail:
begin
pkt_input_ctrl_rdreq<=1'b0;
cdp2um_data_valid<=1'b0;
state<=idle;
end
default:
begin
cdp2um_data_valid<=1'b0;
state<=idle;
end
endcase
end
reg pkt_input_ctrl_rdreq;
wire [138:0]pkt_input_ctrl_q;
wire [7:0]pkt_input_ctrl_usedw;
reg pkt_input_ctrl_valid_rdreq;
wire pkt_input_ctrl_valid_q;
wire pkt_input_ctrl_valid_empty;
fifo_256_139 pkt_input_ctrl_fifo(
.aclr(!reset),
.clock(clk),
.data(pkt_input_ctrl_data),
.rdreq(pkt_input_ctrl_rdreq),
.wrreq(pkt_input_ctrl_wrreq),
.q(pkt_input_ctrl_q),
.usedw(pkt_input_ctrl_usedw)
);
fifo_64_1 pkt_input_ctrl_valid_fifo(
.aclr(!reset),
.clock(clk),
.data(pkt_input_ctrl_valid),
.rdreq(pkt_input_ctrl_valid_rdreq),
.wrreq(pkt_input_ctrl_valid_wrreq),
.empty(pkt_input_ctrl_valid_empty),
.q(pkt_input_ctrl_valid_q)
);
endmodule |
module ram_32_64 (
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b);
input [5:0] address_a;
input [5:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.data_b (data_b),
.rden_a (rden_a),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.rden_b (rden_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus ());
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Arria II GX",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 64,
altsyncram_component.numwords_b = 64,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule |
module fifo_4_16 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [3:0] data;
input rdreq;
input wrreq;
output empty;
output [3:0] q;
wire sub_wire0;
wire [3:0] sub_wire1;
wire empty = sub_wire0;
wire [3:0] q = sub_wire1[3:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 4,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_16_32 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output empty;
output [15:0] q;
wire sub_wire0;
wire [15:0] sub_wire1;
wire empty = sub_wire0;
wire [15:0] q = sub_wire1[15:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_64_32 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [63:0] data;
input rdreq;
input wrreq;
output empty;
output [63:0] q;
wire sub_wire0;
wire [63:0] sub_wire1;
wire empty = sub_wire0;
wire [63:0] q = sub_wire1[63:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 64,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_139_256 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [138:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [138:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [138:0] sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [138:0] q = sub_wire3[138:0];
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 139,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_20_64 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [19:0] data;
input rdreq;
input wrreq;
output empty;
output [19:0] q;
wire sub_wire0;
wire [19:0] sub_wire1;
wire empty = sub_wire0;
wire [19:0] q = sub_wire1[19:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 20,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_360_64 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [359:0] data;
input rdreq;
input wrreq;
output empty;
output [359:0] q;
wire sub_wire0;
wire [359:0] sub_wire1;
wire empty = sub_wire0;
wire [359:0] q = sub_wire1[359:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 360,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module asy_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [138:0] sub_wire0;
wire [7:0] sub_wire1;
wire [138:0] q = sub_wire0[138:0];
wire [7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.wrusedw (sub_wire1),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 139,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
module fifo_64_1 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [0:0] data;
input rdreq;
input wrreq;
output empty;
output [0:0] q;
wire sub_wire0;
wire [0:0] sub_wire1;
wire empty = sub_wire0;
wire [0:0] q = sub_wire1[0:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 1,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module asy_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire sub_wire1;
wire [0:0] q = sub_wire0[0:0];
wire rdempty = sub_wire1;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 64,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 6,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
module fifo_360_16 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [359:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [359:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [359:0] sub_wire3;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [359:0] q = sub_wire3[359:0];
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 360,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module rx_64_1 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [0:0] data;
input rdreq;
input wrreq;
output empty;
output [0:0] q;
wire sub_wire0;
wire [0:0] sub_wire1;
wire empty = sub_wire0;
wire [0:0] q = sub_wire1[0:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.empty (sub_wire0),
.q (sub_wire1)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 1,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_340_16 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [339:0] data;
input rdreq;
input wrreq;
output empty;
output [339:0] q;
wire sub_wire0;
wire [339:0] sub_wire1;
wire empty = sub_wire0;
wire [339:0] q = sub_wire1[339:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 340,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module key_gen(
clk,
reset,
p2k_valid,
p2k_ingress,
p2k_rloc_src,
p2k_eid_dst,
p2k_metadata,
mode, //1 ceng die wang ;
k2m_metadata_valid,
k2m_metadata
);
input clk;
input reset;
input p2k_valid;
input [7:0] p2k_ingress;
input [127:0] p2k_rloc_src;
input [127:0] p2k_eid_dst;
input [7:0] p2k_metadata;//useless
input mode;
output k2m_metadata_valid;
output [107:0] k2m_metadata;
reg k2m_metadata_valid;
reg [107:0] k2m_metadata;
//reg [127:0] rloc_src;
//reg [127:0] eid_dst;
//--state--//
//reg [3:0] key_state;
//-------------------key_gen_state-------------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
k2m_metadata_valid <= 1'b0;
k2m_metadata <= 108'b0;
end
else
begin
if(p2k_valid == 1'b1)
begin
if(mode == 1'b1)//ceng die wang
begin
if(p2k_ingress == 8'b0) k2m_metadata <= {mode,p2k_ingress,p2k_rloc_src[17:0],81'b0};
else k2m_metadata <= {mode,p2k_ingress,18'b0,81'b0};
k2m_metadata_valid <= 1'b1;
end
else//shi wang
begin
k2m_metadata_valid <= 1'b1;
k2m_metadata <= {mode,p2k_ingress,p2k_eid_dst[127:56],56'b0};
end
end
else k2m_metadata_valid <= 1'b0;
end
end
endmodule |
module ddr2_mem_model_ram_module (
// inputs:
data,
rdaddress,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
parameter ARRAY_DEPTH = 2048;
output [ 31: 0] q;
input [ 31: 0] data;
input [ 23: 0] rdaddress;
input [ 23: 0] wraddress;
input wrclock;
input wren;
wire [ 31: 0] aq;
reg [ 56: 0] mem_array [2047: 0];
wire [ 31: 0] q;
assign aq = mem_array[0][31:0];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [ 32 - 1: 0] out;
integer i;
reg found_valid_data;
reg data_written;
initial
begin
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
mem_array[i][0] <= 1'b0;
data_written <= 1'b0;
end
always @(rdaddress)
begin
found_valid_data <= 1'b0;
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
begin
if (rdaddress == mem_array[i][57 - 1:57 - 24] && mem_array[i][0])
begin
out = mem_array[i][57 - 24 - 1:57 - 24 - 32];
found_valid_data = 1'b1;
end
end
if (!found_valid_data)
out = 32'dX;
end
always @(posedge wrclock)
if (wren)
begin
data_written <= 1'b0;
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
begin
if (wraddress == mem_array[i][57 - 1:57 - 24] && !data_written)
begin
mem_array[i][57 - 24 - 1:57 - 24 - 32] <= data;
mem_array[i][0] <= 1'b1;
data_written = 1'b1;
end
else if (!mem_array[i][0] && !data_written)
begin
mem_array[i] <= {wraddress,data,1'b1};
data_written = 1'b1;
end
end
if (!data_written)
begin
$write($time);
$write(" --- Data could not be written, increase array depth or use full memory model --- ");
$stop;
end
end
assign q = out;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule |
module ddr2_mem_model (
// inputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
// outputs:
global_reset_n,
mem_dq,
mem_dqs,
mem_dqs_n
)
;
output global_reset_n;
inout [ 15: 0] mem_dq;
inout [ 1: 0] mem_dqs;
inout [ 1: 0] mem_dqs_n;
input [ 12: 0] mem_addr;
input [ 1: 0] mem_ba;
input mem_cas_n;
input mem_cke;
input mem_clk;
input mem_clk_n;
input mem_cs_n;
input [ 1: 0] mem_dm;
input mem_odt;
input mem_ras_n;
input mem_we_n;
wire [ 23: 0] CODE;
wire [ 12: 0] a;
reg [ 3: 0] additive_latency;
wire [ 8: 0] addr_col;
wire [ 1: 0] ba;
reg [ 2: 0] burstlength;
reg burstmode;
wire cas_n;
wire cke;
wire clk;
wire [ 2: 0] cmd_code;
wire cs_n;
wire [ 1: 0] current_row;
wire [ 1: 0] dm;
reg [ 3: 0] dm_captured;
reg [ 31: 0] dq_captured;
wire [ 15: 0] dq_temp;
wire dq_valid;
wire [ 1: 0] dqs_n_temp;
wire [ 1: 0] dqs_temp;
wire dqs_valid;
reg dqs_valid_temp;
reg [ 15: 0] first_half_dq;
wire global_reset_n;
wire [ 31: 0] mem_bytes;
wire [ 15: 0] mem_dq;
wire [ 1: 0] mem_dqs;
wire [ 1: 0] mem_dqs_n;
reg [ 12: 0] open_rows [ 3: 0];
wire ras_n;
reg [ 23: 0] rd_addr_pipe_0;
reg [ 23: 0] rd_addr_pipe_1;
reg [ 23: 0] rd_addr_pipe_10;
reg [ 23: 0] rd_addr_pipe_11;
reg [ 23: 0] rd_addr_pipe_12;
reg [ 23: 0] rd_addr_pipe_13;
reg [ 23: 0] rd_addr_pipe_14;
reg [ 23: 0] rd_addr_pipe_15;
reg [ 23: 0] rd_addr_pipe_16;
reg [ 23: 0] rd_addr_pipe_17;
reg [ 23: 0] rd_addr_pipe_18;
reg [ 23: 0] rd_addr_pipe_19;
reg [ 23: 0] rd_addr_pipe_2;
reg [ 23: 0] rd_addr_pipe_20;
reg [ 23: 0] rd_addr_pipe_21;
reg [ 23: 0] rd_addr_pipe_3;
reg [ 23: 0] rd_addr_pipe_4;
reg [ 23: 0] rd_addr_pipe_5;
reg [ 23: 0] rd_addr_pipe_6;
reg [ 23: 0] rd_addr_pipe_7;
reg [ 23: 0] rd_addr_pipe_8;
reg [ 23: 0] rd_addr_pipe_9;
reg [ 23: 0] rd_burst_counter;
reg [ 25: 0] rd_valid_pipe;
wire [ 23: 0] read_addr_delayed;
reg read_cmd;
reg read_cmd_echo;
wire [ 31: 0] read_data;
wire [ 15: 0] read_dq;
reg [ 4: 0] read_latency;
wire read_valid;
reg read_valid_r;
reg read_valid_r2;
reg read_valid_r3;
reg read_valid_r4;
reg reset_n;
wire [ 23: 0] rmw_address;
reg [ 31: 0] rmw_temp;
reg [ 15: 0] second_half_dq;
reg [ 3: 0] tcl;
wire [ 23: 0] txt_code;
wire we_n;
wire [ 23: 0] wr_addr_delayed;
reg [ 23: 0] wr_addr_delayed_r;
reg [ 23: 0] wr_addr_pipe_0;
reg [ 23: 0] wr_addr_pipe_1;
reg [ 23: 0] wr_addr_pipe_10;
reg [ 23: 0] wr_addr_pipe_11;
reg [ 23: 0] wr_addr_pipe_12;
reg [ 23: 0] wr_addr_pipe_13;
reg [ 23: 0] wr_addr_pipe_14;
reg [ 23: 0] wr_addr_pipe_15;
reg [ 23: 0] wr_addr_pipe_16;
reg [ 23: 0] wr_addr_pipe_17;
reg [ 23: 0] wr_addr_pipe_18;
reg [ 23: 0] wr_addr_pipe_2;
reg [ 23: 0] wr_addr_pipe_3;
reg [ 23: 0] wr_addr_pipe_4;
reg [ 23: 0] wr_addr_pipe_5;
reg [ 23: 0] wr_addr_pipe_6;
reg [ 23: 0] wr_addr_pipe_7;
reg [ 23: 0] wr_addr_pipe_8;
reg [ 23: 0] wr_addr_pipe_9;
reg [ 23: 0] wr_burst_counter;
reg [ 25: 0] wr_valid_pipe;
reg [ 25: 0] write_burst_length_pipe;
reg write_cmd;
reg write_cmd_echo;
reg [ 4: 0] write_latency;
wire write_to_ram;
reg write_to_ram_r;
wire write_valid;
reg write_valid_r;
reg write_valid_r2;
reg write_valid_r3;
initial
begin
$write("\n");
$write("**********************************************************************\n");
$write("This testbench includes a generated Altera memory model:\n");
$write("'ddr2_mem_model.v', to simulate accesses to the DDR2 SDRAM memory.\n");
$write(" \n");
$write("**********************************************************************\n");
end
//Synchronous write when (CODE == 24'h205752 (write))
ddr2_mem_model_ram_module ddr2_mem_model_ram
(
.data (rmw_temp),
.q (read_data),
.rdaddress (rmw_address),
.wraddress (wr_addr_delayed_r),
.wrclock (clk),
.wren (write_to_ram_r)
);
assign clk = mem_clk;
assign dm = mem_dm;
assign cke = mem_cke;
assign cs_n = mem_cs_n;
assign ras_n = mem_ras_n;
assign cas_n = mem_cas_n;
assign we_n = mem_we_n;
assign ba = mem_ba;
assign a = mem_addr;
//generate a fake reset inside the memory model
assign global_reset_n = reset_n;
initial
begin
reset_n <= 0;
#100 reset_n <= 1;
end
assign cmd_code = (&cs_n) ? 3'b111 : {ras_n, cas_n, we_n};
assign CODE = (&cs_n) ? 24'h494e48 : txt_code;
assign addr_col = a[9 : 1];
assign current_row = {ba};
// Decode commands into their actions
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
write_cmd_echo <= 0;
read_cmd_echo <= 0;
end
else // No Activity if the clock is
if (cke)
begin
// Checks whether to echo read cmd
if (read_cmd_echo && !read_cmd)
begin
read_cmd <= 1'b1;
read_cmd_echo <= 1'b0;
end
else // This is a read command
if (cmd_code == 3'b101)
begin
read_cmd <= 1'b1;
read_cmd_echo <= 1'b1;
end
else
read_cmd <= 1'b0;
// Checks whether to echo write cmd
if (write_cmd_echo && !write_cmd)
begin
write_cmd <= 1'b1;
write_cmd_echo <= 1'b0;
end
else // This is a write command
if (cmd_code == 3'b100)
begin
write_cmd <= 1'b1;
write_cmd_echo <= 1'b1;
write_burst_length_pipe[0] <= a[0];
end
else
write_cmd <= 1'b0;
// This is an activate - store the chip/row/bank address in the same order as the DDR controller
if (cmd_code == 3'b011)
open_rows[current_row] <= a;
end
end
// Pipes are flushed here
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_addr_pipe_1 <= 0;
wr_addr_pipe_2 <= 0;
wr_addr_pipe_3 <= 0;
wr_addr_pipe_4 <= 0;
wr_addr_pipe_5 <= 0;
wr_addr_pipe_6 <= 0;
wr_addr_pipe_7 <= 0;
wr_addr_pipe_8 <= 0;
wr_addr_pipe_9 <= 0;
wr_addr_pipe_10 <= 0;
wr_addr_pipe_11 <= 0;
wr_addr_pipe_12 <= 0;
wr_addr_pipe_13 <= 0;
wr_addr_pipe_14 <= 0;
wr_addr_pipe_15 <= 0;
wr_addr_pipe_16 <= 0;
wr_addr_pipe_17 <= 0;
wr_addr_pipe_18 <= 0;
rd_addr_pipe_1 <= 0;
rd_addr_pipe_2 <= 0;
rd_addr_pipe_3 <= 0;
rd_addr_pipe_4 <= 0;
rd_addr_pipe_5 <= 0;
rd_addr_pipe_6 <= 0;
rd_addr_pipe_7 <= 0;
rd_addr_pipe_8 <= 0;
rd_addr_pipe_9 <= 0;
rd_addr_pipe_10 <= 0;
rd_addr_pipe_11 <= 0;
rd_addr_pipe_12 <= 0;
rd_addr_pipe_13 <= 0;
rd_addr_pipe_14 <= 0;
rd_addr_pipe_15 <= 0;
rd_addr_pipe_16 <= 0;
rd_addr_pipe_17 <= 0;
rd_addr_pipe_18 <= 0;
rd_addr_pipe_19 <= 0;
rd_addr_pipe_20 <= 0;
rd_addr_pipe_21 <= 0;
end
else // No Activity if the clock is
if (cke)
begin
rd_addr_pipe_21 <= rd_addr_pipe_20;
rd_addr_pipe_20 <= rd_addr_pipe_19;
rd_addr_pipe_19 <= rd_addr_pipe_18;
rd_addr_pipe_18 <= rd_addr_pipe_17;
rd_addr_pipe_17 <= rd_addr_pipe_16;
rd_addr_pipe_16 <= rd_addr_pipe_15;
rd_addr_pipe_15 <= rd_addr_pipe_14;
rd_addr_pipe_14 <= rd_addr_pipe_13;
rd_addr_pipe_13 <= rd_addr_pipe_12;
rd_addr_pipe_12 <= rd_addr_pipe_11;
rd_addr_pipe_11 <= rd_addr_pipe_10;
rd_addr_pipe_10 <= rd_addr_pipe_9;
rd_addr_pipe_9 <= rd_addr_pipe_8;
rd_addr_pipe_8 <= rd_addr_pipe_7;
rd_addr_pipe_7 <= rd_addr_pipe_6;
rd_addr_pipe_6 <= rd_addr_pipe_5;
rd_addr_pipe_5 <= rd_addr_pipe_4;
rd_addr_pipe_4 <= rd_addr_pipe_3;
rd_addr_pipe_3 <= rd_addr_pipe_2;
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_valid_pipe[25 : 1] <= rd_valid_pipe[24 : 0];
rd_valid_pipe[0] <= cmd_code == 3'b101;
wr_addr_pipe_18 <= wr_addr_pipe_17;
wr_addr_pipe_17 <= wr_addr_pipe_16;
wr_addr_pipe_16 <= wr_addr_pipe_15;
wr_addr_pipe_15 <= wr_addr_pipe_14;
wr_addr_pipe_14 <= wr_addr_pipe_13;
wr_addr_pipe_13 <= wr_addr_pipe_12;
wr_addr_pipe_12 <= wr_addr_pipe_11;
wr_addr_pipe_11 <= wr_addr_pipe_10;
wr_addr_pipe_10 <= wr_addr_pipe_9;
wr_addr_pipe_9 <= wr_addr_pipe_8;
wr_addr_pipe_8 <= wr_addr_pipe_7;
wr_addr_pipe_7 <= wr_addr_pipe_6;
wr_addr_pipe_6 <= wr_addr_pipe_5;
wr_addr_pipe_5 <= wr_addr_pipe_4;
wr_addr_pipe_4 <= wr_addr_pipe_3;
wr_addr_pipe_3 <= wr_addr_pipe_2;
wr_addr_pipe_2 <= wr_addr_pipe_1;
wr_addr_pipe_1 <= wr_addr_pipe_0;
wr_valid_pipe[25 : 1] <= wr_valid_pipe[24 : 0];
wr_valid_pipe[0] <= cmd_code == 3'b100;
wr_addr_delayed_r <= wr_addr_delayed;
write_burst_length_pipe[25 : 1] <= write_burst_length_pipe[24 : 0];
end
end
// Decode CAS Latency from bits a[6:4]
always @(posedge clk)
begin
// No Activity if the clock is disabled
if (cke)
//Load mode register - set CAS latency, burst mode and length
if (cmd_code == 3'b000 && ba == 2'b00)
begin
burstmode <= a[3];
burstlength <= a[2 : 0] << 1;
//CAS Latency = 3.0
if (a[6 : 4] == 3'b011)
tcl <= 4'b0010;
else //CAS Latency = 4.0
if (a[6 : 4] == 3'b100)
tcl <= 4'b0011;
else //CAS Latency = 5.0
if (a[6 : 4] == 3'b101)
tcl <= 4'b0100;
else //CAS Latency = 6.0
if (a[6 : 4] == 3'b110)
tcl <= 4'b0101;
else
tcl <= 4'b0110;
end
else //Get additive latency
if (cmd_code == 3'b000 && ba == 2'b01)
additive_latency <= {1'b0,a[5 : 3]};
end
//Calculate actual write and read latency
always @(additive_latency or tcl)
begin
read_latency = tcl + additive_latency;
write_latency = tcl + additive_latency;
end
// Burst support - make the wr_addr & rd_addr keep counting
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_addr_pipe_0 <= 0;
rd_addr_pipe_0 <= 0;
end
else
begin
// Reset write address otherwise if the first write is partial it breaks!
if (cmd_code == 3'b000 && ba == 2'b00)
begin
wr_addr_pipe_0 <= 0;
wr_burst_counter <= 0;
end
else if (cmd_code == 3'b100)
begin
wr_addr_pipe_0 <= {ba,open_rows[current_row],addr_col};
wr_burst_counter[23 : 2] <= {ba,open_rows[current_row],addr_col[8 : 2]};
wr_burst_counter[1 : 0] <= addr_col[1 : 0] + 1;
end
else if (write_cmd || write_to_ram || write_cmd_echo)
begin
wr_addr_pipe_0 <= wr_burst_counter;
wr_burst_counter[1 : 0] <= wr_burst_counter[1 : 0] + 1;
end
else
wr_addr_pipe_0 <= 0;
// Reset read address otherwise if the first write is partial it breaks!
if (cmd_code == 3'b000 && ba == 2'b00)
rd_addr_pipe_0 <= 0;
else if (cmd_code == 3'b101)
begin
rd_addr_pipe_0 <= {ba,open_rows[current_row],addr_col};
rd_burst_counter[23 : 2] <= {ba,open_rows[current_row],addr_col[8 : 2]};
rd_burst_counter[1 : 0] <= addr_col[1 : 0] + 1;
end
else if (read_cmd || dq_valid || read_valid || read_cmd_echo)
begin
rd_addr_pipe_0 <= rd_burst_counter;
rd_burst_counter[1 : 0] <= rd_burst_counter[1 : 0] + 1;
end
else
rd_addr_pipe_0 <= 0;
end
end
// read data transition from single to double clock rate
always @(posedge clk)
begin
first_half_dq <= read_data[31 : 16];
second_half_dq <= read_data[15 : 0];
end
assign read_dq = clk ? second_half_dq : first_half_dq;
assign dq_temp = dq_valid ? read_dq : {16{1'bz}};
assign dqs_temp = dqs_valid ? {2{clk}} : {2{1'bz}};
assign dqs_n_temp = dqs_valid ? {2{~clk}} : {2{1'bz}};
assign mem_dqs = dqs_temp;
assign mem_dq = dq_temp;
assign mem_dqs_n = dqs_n_temp;
//Pipelining registers for burst counting
always @(posedge clk)
begin
write_valid_r <= write_valid;
read_valid_r <= read_valid;
write_valid_r2 <= write_valid_r;
write_valid_r3 <= write_valid_r2;
write_to_ram_r <= write_to_ram;
read_valid_r2 <= read_valid_r;
read_valid_r3 <= read_valid_r2;
read_valid_r4 <= read_valid_r3;
end
assign write_to_ram = burstlength[1] ? write_valid || write_valid_r || write_valid_r2 || write_valid_r3 : write_valid || write_valid_r;
assign dq_valid = burstlength[1] ? read_valid_r || read_valid_r2 || read_valid_r3 || read_valid_r4 : read_valid_r || read_valid_r2;
assign dqs_valid = dq_valid || dqs_valid_temp;
//
always @(negedge clk)
begin
dqs_valid_temp <= read_valid;
end
//capture first half of write data with rising edge of DQS, for simulation use only 1 DQS pin
always @(posedge mem_dqs[0])
begin
#0.1 dq_captured[15 : 0] <= mem_dq[15 : 0];
#0.1 dm_captured[1 : 0] <= mem_dm[1 : 0];
end
//capture second half of write data with falling edge of DQS, for simulation use only 1 DQS pin
always @(negedge mem_dqs[0])
begin
#0.1 dq_captured[31 : 16] <= mem_dq[15 : 0];
#0.1 dm_captured[3 : 2] <= mem_dm[1 : 0];
end
//Support for incomplete writes, do a read-modify-write with mem_bytes and the write data
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[7 : 0] <= dm_captured[0] ? mem_bytes[7 : 0] : dq_captured[7 : 0];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[15 : 8] <= dm_captured[1] ? mem_bytes[15 : 8] : dq_captured[15 : 8];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[23 : 16] <= dm_captured[2] ? mem_bytes[23 : 16] : dq_captured[23 : 16];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[31 : 24] <= dm_captured[3] ? mem_bytes[31 : 24] : dq_captured[31 : 24];
end
//DDR2 has variable write latency too, so use write_latency to select which pipeline stage drives valid
assign write_valid = (write_latency == 0)? wr_valid_pipe[0] :
(write_latency == 1)? wr_valid_pipe[1] :
(write_latency == 2)? wr_valid_pipe[2] :
(write_latency == 3)? wr_valid_pipe[3] :
(write_latency == 4)? wr_valid_pipe[4] :
(write_latency == 5)? wr_valid_pipe[5] :
(write_latency == 6)? wr_valid_pipe[6] :
(write_latency == 7)? wr_valid_pipe[7] :
(write_latency == 8)? wr_valid_pipe[8] :
(write_latency == 9)? wr_valid_pipe[9] :
(write_latency == 10)? wr_valid_pipe[10] :
(write_latency == 11)? wr_valid_pipe[11] :
(write_latency == 12)? wr_valid_pipe[12] :
(write_latency == 13)? wr_valid_pipe[13] :
(write_latency == 14)? wr_valid_pipe[14] :
(write_latency == 15)? wr_valid_pipe[15] :
(write_latency == 16)? wr_valid_pipe[16] :
(write_latency == 17)? wr_valid_pipe[17] :
wr_valid_pipe[18];
//DDR2 has variable write latency too, so use write_latency to select which pipeline stage drives addr
assign wr_addr_delayed = (write_latency == 0)? wr_addr_pipe_0 :
(write_latency == 1)? wr_addr_pipe_1 :
(write_latency == 2)? wr_addr_pipe_2 :
(write_latency == 3)? wr_addr_pipe_3 :
(write_latency == 4)? wr_addr_pipe_4 :
(write_latency == 5)? wr_addr_pipe_5 :
(write_latency == 6)? wr_addr_pipe_6 :
(write_latency == 7)? wr_addr_pipe_7 :
(write_latency == 8)? wr_addr_pipe_8 :
(write_latency == 9)? wr_addr_pipe_9 :
(write_latency == 10)? wr_addr_pipe_10 :
(write_latency == 11)? wr_addr_pipe_11 :
(write_latency == 12)? wr_addr_pipe_12 :
(write_latency == 13)? wr_addr_pipe_13 :
(write_latency == 14)? wr_addr_pipe_14 :
(write_latency == 15)? wr_addr_pipe_15 :
(write_latency == 16)? wr_addr_pipe_16 :
(write_latency == 17)? wr_addr_pipe_17 :
wr_addr_pipe_18;
assign mem_bytes = (rmw_address == wr_addr_delayed_r && write_to_ram_r) ? rmw_temp : read_data;
assign rmw_address = (write_to_ram) ? wr_addr_delayed : read_addr_delayed;
//use read_latency to select which pipeline stage drives addr
assign read_addr_delayed = (read_latency == 0)? rd_addr_pipe_0 :
(read_latency == 1)? rd_addr_pipe_1 :
(read_latency == 2)? rd_addr_pipe_2 :
(read_latency == 3)? rd_addr_pipe_3 :
(read_latency == 4)? rd_addr_pipe_4 :
(read_latency == 5)? rd_addr_pipe_5 :
(read_latency == 6)? rd_addr_pipe_6 :
(read_latency == 7)? rd_addr_pipe_7 :
(read_latency == 8)? rd_addr_pipe_8 :
(read_latency == 9)? rd_addr_pipe_9 :
(read_latency == 10)? rd_addr_pipe_10 :
(read_latency == 11)? rd_addr_pipe_11 :
(read_latency == 12)? rd_addr_pipe_12 :
(read_latency == 13)? rd_addr_pipe_13 :
(read_latency == 14)? rd_addr_pipe_14 :
(read_latency == 15)? rd_addr_pipe_15 :
(read_latency == 16)? rd_addr_pipe_16 :
(read_latency == 17)? rd_addr_pipe_17 :
(read_latency == 18)? rd_addr_pipe_18 :
(read_latency == 19)? rd_addr_pipe_19 :
(read_latency == 20)? rd_addr_pipe_20 :
rd_addr_pipe_21;
//use read_latency to select which pipeline stage drives valid
assign read_valid = (read_latency == 0)? rd_valid_pipe[0] :
(read_latency == 1)? rd_valid_pipe[1] :
(read_latency == 2)? rd_valid_pipe[2] :
(read_latency == 3)? rd_valid_pipe[3] :
(read_latency == 4)? rd_valid_pipe[4] :
(read_latency == 5)? rd_valid_pipe[5] :
(read_latency == 6)? rd_valid_pipe[6] :
(read_latency == 7)? rd_valid_pipe[7] :
(read_latency == 8)? rd_valid_pipe[8] :
(read_latency == 9)? rd_valid_pipe[9] :
(read_latency == 10)? rd_valid_pipe[10] :
(read_latency == 11)? rd_valid_pipe[11] :
(read_latency == 12)? rd_valid_pipe[12] :
(read_latency == 13)? rd_valid_pipe[13] :
(read_latency == 14)? rd_valid_pipe[14] :
(read_latency == 15)? rd_valid_pipe[15] :
(read_latency == 16)? rd_valid_pipe[16] :
(read_latency == 17)? rd_valid_pipe[17] :
(read_latency == 18)? rd_valid_pipe[18] :
(read_latency == 19)? rd_valid_pipe[19] :
(read_latency == 20)? rd_valid_pipe[20] :
rd_valid_pipe[21];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule |
module ddr2_full_mem_model_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 31: 0] q;
input [ 31: 0] data;
input [ 23: 0] rdaddress;
input rdclken;
input [ 23: 0] wraddress;
input wrclock;
input wren;
reg [ 31: 0] mem_array [16777215: 0];
wire [ 31: 0] q;
reg [ 23: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "UNUSED",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 32,
// lpm_ram_dp_component.lpm_widthad = 24,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule |
module nmp_cb08(
FPGA_SYS_CLK,//125.00MHz
R_SGMII_REFCLK,//125.00MHz
FPGA_RESET_L,//SYS RESET
//LED test
SFP_ACTIVE_LED,
SFP_LINK_LED,
SGMII1_RX,
SGMII1_TX,
SGMII0_RX,
SGMII0_TX,
//I2C port
I2C_CLK,
I2C_SDA,
//PCIE_L interface
pcie_l_rx, //PCML14 //PCIe Receive Data-req's OCT
pcie_l_tx, //PCML14 //PCIe Transmit Data
pcie_l_refclk //HCSL //PCIe Clock- Terminate on MB//100MHz
);
input FPGA_SYS_CLK;
input R_SGMII_REFCLK;
input FPGA_RESET_L;
//LED test
output [7:0] SFP_ACTIVE_LED;
output [7:0] SFP_LINK_LED;
input [3:0] SGMII1_RX;
output [3:0] SGMII1_TX;
input [3:0] SGMII0_RX;
output [3:0] SGMII0_TX;
//I2C port
output I2C_CLK;
inout [3:0] I2C_SDA;
//PCI-Express--------------------------//25 pins //--------------------------
input [7:0] pcie_l_rx; //PCML14 //PCIe Receive Data-req's OCT
output [7:0] pcie_l_tx; //PCML14 //PCIe Transmit Data
input pcie_l_refclk; //HCSL //PCIe Clock- Terminate on MB
reg [7:0]SFP_ACTIVE_LED_REG;
reg [7:0]SFP_LINK_LED_REG;
assign SFP_ACTIVE_LED=SFP_ACTIVE_LED_REG;
assign SFP_LINK_LED=SFP_LINK_LED_REG;
wire app_clk;
wire card0_clk;
wire card1_clk;
wire ammc_clk;
wire reconfig_clk;
wire ue_refclk;
wire ue1_clk;
wire spi_refclk;
/***************************************************************/
reg [15:0] reset_count;
reg cnt_reset;
/***************************************************************/
CLK_MANAGE CLK_MANAGE(
//--------------------------------input clk_ Manage Module-------------------------
.CLK_FPGA_REFCK (FPGA_SYS_CLK),//125M
//--------------------------------genarate clk_ Manage Module-------------------------
.app_clk (app_clk),//125M user clk
.reconfig_clk (reconfig_clk),//ctrl reconfig clk 40M
.spi_refclk (spi_refclk)
);
//*****************************************************************************/
wire slot0_port0_out_mux_pkt_wr;
wire [133:0] slot0_port0_out_mux_pkt;
wire slot0_port0_in_mux_pkt_almostfull;
wire slot0_port0_out_mux_pkt_valid_wr;
wire slot0_port0_out_mux_pkt_valid;
//******************************************************************************/
wire [7:0] slot0_port0_address;
wire slot0_port0_write;
wire slot0_port0_read;
wire [31:0] slot0_port0_writedata;
wire [31:0] slot0_port0_readdata;
wire slot0_port0_waitrequest;
wire [7:0] slot0_port1_address;
wire slot0_port1_write;
wire slot0_port1_read;
wire [31:0] slot0_port1_writedata;
wire [31:0] slot0_port1_readdata;
wire slot0_port1_waitrequest;
wire [7:0] slot0_port2_address;
wire slot0_port2_write;
wire slot0_port2_read;
wire [31:0] slot0_port2_writedata;
wire [31:0] slot0_port2_readdata;
wire slot0_port2_waitrequest;
wire [7:0] slot0_port3_address;
wire slot0_port3_write;
wire slot0_port3_read;
wire [31:0] slot0_port3_writedata;
wire [31:0] slot0_port3_readdata;
wire slot0_port3_waitrequest;
wire [7:0] slot0_port4_address;
wire slot0_port4_write;
wire slot0_port4_read;
wire [31:0] slot0_port4_writedata;
wire [31:0] slot0_port4_readdata;
wire slot0_port4_waitrequest;
wire [7:0] slot1_port0_address;
wire slot1_port0_write;
wire slot1_port0_read;
wire [31:0] slot1_port0_writedata;
wire [31:0] slot1_port0_readdata;
wire slot1_port0_waitrequest;
wire [7:0] slot1_port1_address;
wire slot1_port1_write;
wire slot1_port1_read;
wire [31:0] slot1_port1_writedata;
wire [31:0] slot1_port1_readdata;
wire slot1_port1_waitrequest;
wire [7:0] slot1_port2_address;
wire slot1_port2_write;
wire slot1_port2_read;
wire [31:0] slot1_port2_writedata;
wire [31:0] slot1_port2_readdata;
wire slot1_port2_waitrequest;
wire [7:0] slot1_port3_address;
wire slot1_port3_write;
wire slot1_port3_read;
wire [31:0] slot1_port3_writedata;
wire [31:0] slot1_port3_readdata;
wire slot1_port3_waitrequest;
wire [7:0] slot1_port4_address;
wire slot1_port4_write;
wire slot1_port4_read;
wire [31:0] slot1_port4_writedata;
wire [31:0] slot1_port4_readdata;
wire slot1_port4_waitrequest;
wire in_egress_pkt_wr;
wire [133:0] in_egress_pkt;
wire out_egress_pkt_almostfull;
wire in_egress_pkt_valid_wr;
wire in_egress_pkt_valid;
UM UM(
.clk(app_clk),
.rst_n(reset_rn),
.sys_max_cpuid(sys_ctl_reg[5:0]),
//cdp
.cdp2um_data_wr(if_to_um_pkt_wr),
.cdp2um_data(if_to_um_pkt),
.cdp2um_valid_wr(if_to_um_pkt_valid_wr),
.cdp2um_valid(if_to_um_pkt_valid),
.um2cdp_alf(if_to_um_pkt_almful),
.um2cdp_data_wr(um_to_if_pkt_wr),
.um2cdp_data(um_to_if_pkt),
.um2cdp_valid_wr(um_to_if_pkt_valid_wr),
.um2cdp_valid(um_to_if_pkt_valid),
.cdp2um_alf(um_to_if_pkt_almful),
//npe
.npe2um_data_wr(npe_to_um_pkt_wr),
.npe2um_data(npe_to_um_pkt),
.npe2um_valid_wr(npe_to_um_pkt_valid_wr),
.npe2um_valid(npe_to_um_pkt_valid),
.um2npe_alf(npe_to_um_pkt_almful),
.um2npe_data_wr(um_to_npe_pkt_wr),
.um2npe_data(um_to_npe_pkt),
.um2npe_valid_wr(um_to_npe_pkt_valid_wr),
.um2npe_valid(um_to_npe_pkt_valid),
.npe2um_alf(um_to_npe_pkt_almful),
//localbus
.localbus_cs_n(cs_n),
.localbus_rd_wr(rd_wr),
.localbus_data(data),
.localbus_ale(ale),
.localbus_ack_n(ack_n_um),
.localbus_data_out(rdata_um));
wire ale;
wire cs_n;
wire rd_wr;
wire [31:0] data;
wire ack_n_um;
wire [31:0] rdata_um;
wire [64:0] command;
wire command_wr;
wire [31:0] data_out;
loacal_sw loacal_sw(
.clk (app_clk),
.reset (reset_rn),
.command (command),
.command_wr (command_wr),
.data_out (data_out),
.ale (ale),
.cs_n (cs_n),
.rd_wr (rd_wr),
.data (data),
.ack_n_um (ack_n_um),
.rdata_um (rdata_um));
wire [133:0] if_to_um_pkt;
wire if_to_um_pkt_wr;
wire if_to_um_pkt_valid;
wire if_to_um_pkt_valid_wr;
wire if_to_um_pkt_almful;
wire [133:0] um_to_if_pkt;
wire um_to_if_pkt_wr;
wire um_to_if_pkt_valid;
wire um_to_if_pkt_valid_wr;
wire um_to_if_pkt_almful;
wire [133:0] npe_to_um_pkt;
wire npe_to_um_pkt_wr;
wire npe_to_um_pkt_valid;
wire npe_to_um_pkt_valid_wr;
wire npe_to_um_pkt_almful;
wire [133:0] um_to_npe_pkt;
wire um_to_npe_pkt_wr;
wire um_to_npe_pkt_valid;
wire um_to_npe_pkt_valid_wr;
wire um_to_npe_pkt_almful;
IPE_IF IPE_IF(
.clk (app_clk),
.ammc_clk (app_clk),
.card0_clk (app_clk),
.card1_clk (app_clk),
.card0_refclk (R_SGMII_REFCLK),
.card1_refclk (R_SGMII_REFCLK),
.ue1_clk (app_clk),
.reconfig_clk (reconfig_clk),
.reset (reset_rn),
//.reset (cnt_reset),
.line0_xaui_rxdat (SGMII0_RX),
.line0_xaui_txdat (SGMII0_TX),
.line1_xaui_rxdat (SGMII1_RX),
.line1_xaui_txdat (SGMII1_TX),
//egress
.in_egress_pkt_wr (um_to_if_pkt_wr),
.in_egress_pkt (um_to_if_pkt),
.out_egress_pkt_almostfull (um_to_if_pkt_almful),
.in_egress_pkt_valid_wr (um_to_if_pkt_valid_wr),
.in_egress_pkt_valid (um_to_if_pkt_valid),
//ingress
.out_ingress_pkt_wr (if_to_um_pkt_wr),
.out_ingress_pkt (if_to_um_pkt),
.in_ingress_pkt_almostfull (if_to_um_pkt_almful),
.out_ingress_valid_wr (if_to_um_pkt_valid_wr),
.out_ingress_valid (if_to_um_pkt_valid),
.slot0_port0_address (slot0_port0_address),
.slot0_port0_write (slot0_port0_write),
.slot0_port0_read (slot0_port0_read),
.slot0_port0_writedata (slot0_port0_writedata),
.slot0_port0_readdata (slot0_port0_readdata),
.slot0_port0_waitrequest (slot0_port0_waitrequest),
.slot0_port1_address (slot0_port1_address),
.slot0_port1_write (slot0_port1_write),
.slot0_port1_read (slot0_port1_read),
.slot0_port1_writedata (slot0_port1_writedata),
.slot0_port1_readdata (slot0_port1_readdata),
.slot0_port1_waitrequest (slot0_port1_waitrequest),
.slot0_port2_address (slot0_port2_address),
.slot0_port2_write (slot0_port2_write),
.slot0_port2_read (slot0_port2_read),
.slot0_port2_writedata (slot0_port2_writedata),
.slot0_port2_readdata (slot0_port2_readdata),
.slot0_port2_waitrequest (slot0_port2_waitrequest),
.slot0_port3_address (slot0_port3_address),
.slot0_port3_write (slot0_port3_write),
.slot0_port3_read (slot0_port3_read),
.slot0_port3_writedata (slot0_port3_writedata),
.slot0_port3_readdata (slot0_port3_readdata),
.slot0_port3_waitrequest (slot0_port3_waitrequest),
.slot0_port4_address (slot0_port4_address),
.slot0_port4_write (slot0_port4_write),
.slot0_port4_read (slot0_port4_read),
.slot0_port4_writedata (slot0_port4_writedata),
.slot0_port4_readdata (slot0_port4_readdata),
.slot0_port4_waitrequest (slot0_port4_waitrequest),
.slot1_port0_address (slot1_port0_address),
.slot1_port0_write (slot1_port0_write),
.slot1_port0_read (slot1_port0_read),
.slot1_port0_writedata (slot1_port0_writedata),
.slot1_port0_readdata (slot1_port0_readdata),
.slot1_port0_waitrequest (slot1_port0_waitrequest),
.slot1_port1_address (slot1_port1_address),
.slot1_port1_write (slot1_port1_write),
.slot1_port1_read (slot1_port1_read),
.slot1_port1_writedata (slot1_port1_writedata),
.slot1_port1_readdata (slot1_port1_readdata),
.slot1_port1_waitrequest (slot1_port1_waitrequest),
.slot1_port2_address (slot1_port2_address),
.slot1_port2_write (slot1_port2_write),
.slot1_port2_read (slot1_port2_read),
.slot1_port2_writedata (slot1_port2_writedata),
.slot1_port2_readdata (slot1_port2_readdata),
.slot1_port2_waitrequest (slot1_port2_waitrequest),
.slot1_port3_address (slot1_port3_address),
.slot1_port3_write (slot1_port3_write),
.slot1_port3_read (slot1_port3_read),
.slot1_port3_writedata (slot1_port3_writedata),
.slot1_port3_readdata (slot1_port3_readdata),
.slot1_port3_waitrequest (slot1_port3_waitrequest),
.slot1_port4_address (slot1_port4_address),
.slot1_port4_write (slot1_port4_write),
.slot1_port4_read (slot1_port4_read),
.slot1_port4_writedata (slot1_port4_writedata),
.slot1_port4_readdata (slot1_port4_readdata),
.slot1_port4_waitrequest (slot1_port4_waitrequest),
//port count
.slot0_port0_pkt_receive_add (slot0_port0_pkt_receive_add),
.slot0_port0_pkt_discard_add (slot0_port0_pkt_discard_add),
.slot0_port0_pkt_send_add (slot0_port0_pkt_send_add),
.slot0_port1_pkt_receive_add (slot0_port1_pkt_receive_add),
.slot0_port1_pkt_discard_add (slot0_port1_pkt_discard_add),
.slot0_port1_pkt_send_add (slot0_port1_pkt_send_add),
.slot0_port2_pkt_receive_add (slot0_port2_pkt_receive_add),
.slot0_port2_pkt_discard_add (slot0_port2_pkt_discard_add),
.slot0_port2_pkt_send_add (slot0_port2_pkt_send_add),
.slot0_port3_pkt_receive_add (slot0_port3_pkt_receive_add),
.slot0_port3_pkt_discard_add (slot0_port3_pkt_discard_add),
.slot0_port3_pkt_send_add (slot0_port3_pkt_send_add),
.slot0_port4_pkt_receive_add (slot0_port4_pkt_receive_add),
.slot0_port4_pkt_discard_add (slot0_port4_pkt_discard_add),
.slot0_port4_pkt_send_add (slot0_port4_pkt_send_add),
.slot1_port0_pkt_receive_add (slot1_port0_pkt_receive_add),
.slot1_port0_pkt_discard_add (slot1_port0_pkt_discard_add),
.slot1_port0_pkt_send_add (slot1_port0_pkt_send_add),
.slot1_port1_pkt_receive_add (slot1_port1_pkt_receive_add),
.slot1_port1_pkt_discard_add (slot1_port1_pkt_discard_add),
.slot1_port1_pkt_send_add (slot1_port1_pkt_send_add),
.slot1_port2_pkt_receive_add (slot1_port2_pkt_receive_add),
.slot1_port2_pkt_discard_add (slot1_port2_pkt_discard_add),
.slot1_port2_pkt_send_add (slot1_port2_pkt_send_add),
.slot1_port3_pkt_receive_add (slot1_port3_pkt_receive_add),
.slot1_port3_pkt_discard_add (slot1_port3_pkt_discard_add),
.slot1_port3_pkt_send_add (slot1_port3_pkt_send_add),
.slot1_port4_pkt_receive_add (slot1_port4_pkt_receive_add),
.slot1_port4_pkt_discard_add (slot1_port4_pkt_discard_add),
.slot1_port4_pkt_send_add (slot1_port4_pkt_send_add),
//mux count
.mux0_receive_pkt_add (mux0_receive_pkt_add),
.mux0_discard_error_pkt_add (mux0_discard_error_pkt_add),
.mux1_receive_pkt_add (mux1_receive_pkt_add),
.mux1_discard_error_pkt_add (mux1_discard_error_pkt_add),
//dmux count
.dmux0_receive_pkt_add (dmux0_receive_pkt_add),
.dmux0_discard_error_pkt_add (dmux0_discard_error_pkt_add),
.dmux0_send_port0_pkt_add (dmux0_send_port0_pkt_add),
.dmux0_send_port1_pkt_add (dmux0_send_port1_pkt_add),
.dmux0_send_port2_pkt_add (dmux0_send_port2_pkt_add),
.dmux0_send_port3_pkt_add (dmux0_send_port3_pkt_add),
.dmux0_send_port4_pkt_add (dmux0_send_port4_pkt_add),
.dmux1_receive_pkt_add (dmux1_receive_pkt_add),
.dmux1_discard_error_pkt_add (dmux1_discard_error_pkt_add),
.dmux1_send_port0_pkt_add (dmux1_send_port0_pkt_add),
.dmux1_send_port1_pkt_add (dmux1_send_port1_pkt_add),
.dmux1_send_port2_pkt_add (dmux1_send_port2_pkt_add),
.dmux1_send_port3_pkt_add (dmux1_send_port3_pkt_add),
.dmux1_send_port4_pkt_add (dmux1_send_port4_pkt_add),
//input ctl count
.inputctl_receive_pkt_add (inputctl_receive_pkt_add),
.output_receive_pkt_add (output_receive_pkt_add),
.output_discard_error_pkt_add (output_discard_error_pkt_add),
.output_send_slot0_pkt_add (output_send_slot0_pkt_add),
.output_send_slot1_pkt_add (output_send_slot1_pkt_add));
wire in_pcietx_pkt_wr;
wire [133:0] in_pcietx_pkt;
wire out_pcietx_pkt_almostfull;
wire in_pcietx_pkt_valid_wr;
wire in_pcietx_pkt_valid;
wire in_pcietx_des_wr;
wire [63:0] in_pcietx_des;
wire in_dispather_valid;
wire in_dispather_valid_wr;
wire [133:0] in_dispather_pkt;
wire in_dispather_pkt_wr;
wire out_dispather_pkt_almostfull;
wire [41:0] in_fpga_base_addr;
wire in_fpga_base_addr_wr;
wire [31:0] in_fpga_virhead;
NPE_DMA NPE_DMA(
.clk (app_clk),
.wrclk (pcie_clk),
.reset (reset_rn),
//----------------------------------From Software---------------------------------
.in_fpga_channel_num (sys_ctl_reg[5:0]),//RDMA will initial pkt chain by channel_num
.in_fpga_virhead (in_fpga_virhead),//vir addr head(),put in the front of vir addr body to form a vir addr
.in_fpga_base_addr (in_fpga_base_addr),
.in_fpga_base_addr_wr (in_fpga_base_addr_wr),
.in_fpga_endian_flag (sys_ctl_reg[14]),
//----------------------------------From PCIE RX---------------------------------
.out_pcierx_rdpkt_wr (in_tdma_rdpkt_wr),
.out_pcierx_rdpkt (in_tdma_rdpkt),
.in_pcierx_rdpkt_usedw (out_tdma_rdpkt_usedw),
.out_pcierx_pkt_wr (in_rdma_pkt_wr),
.out_pcierx_pkt (in_rdma_pkt),
.in_pcierx_pkt_almostfull (out_rdma_pkt_almostfull),
.out_pcierx_valid_wr (in_rdma_valid_wr),
.out_pcierx_valid (in_rdma_valid),//valid will be sent after a pkt have send completed
//----------------------------------From PCIE TX---------------------------------
.in_pcietx_des (in_pcietx_des),
.in_pcietx_des_wr (in_pcietx_des_wr),
.in_pcietx_pkt (in_pcietx_pkt),
.in_pcietx_pkt_wr (in_pcietx_pkt_wr),
.out_pcietx_pkt_almostfull (out_pcietx_pkt_almostfull),
.in_pcietx_valid (in_pcietx_pkt_valid),
.in_pcietx_valid_wr (in_pcietx_pkt_valid_wr),
//----------------------------------From dispather---------------------------------
.in_dispather_valid (in_dispather_valid),
.in_dispather_valid_wr (in_dispather_valid_wr),
.in_dispather_pkt (in_dispather_pkt),
.in_dispather_pkt_wr (in_dispather_pkt_wr),
.out_dispather_pkt_almostfull (out_dispather_pkt_almostfull),
.out_egress_pkt (in_tdma_pkt),
.out_egress_pkt_wr (in_tdma_pkt_wr),
.in_egress_pkt_almostfull (out_tdma_pkt_almostfull),
.out_egress_valid (in_tdma_valid),
.out_egress_valid_wr (in_tdma_valid_wr),
//---------------------------------- To COUNT---------------------------------
.cpuid_process_desc_add (cpuid_process_desc_add),//201312241134
.cpuid_receive_pkt_add (cpuid_receive_pkt_add),//201312241134
.cpuid_softaddr_add (cpuid_softaddr_add),//201403101619
.tdma_receive_pcietx_desc_add (tdma_receive_pcietx_desc_add),
.tdma_receive_generate_desc_add (tdma_receive_generate_desc_add),
.tdma_discard_desc_add (tdma_discard_desc_add),
.tdma_discard_overload_add (tdma_discard_overload_add),
.tdma_recycle_index_add (tdma_recycle_index_add),
.rdma_receive_pkt_add (rdma_receive_pkt_add),
.rdma_receive_addr_add (rdma_receive_addr_add)
);
wire reset_rn;
wire [3:0] lane_act;
wire pcie_clk;
wire [133:0] in_tdma_rdpkt;
wire in_tdma_rdpkt_wr;
wire [10:0] out_tdma_rdpkt_usedw;
wire [133:0] in_rdma_pkt;
wire in_rdma_pkt_wr;
wire out_rdma_pkt_almostfull;
wire in_rdma_valid;
wire in_rdma_valid_wr;
NPE_PCIE NPE_PCIE(
.npor (FPGA_RESET_L),
.reset_rn (reset_rn),
.reset_reg (reset_reg),
.pld_clk (pcie_clk),
.app_clk (app_clk),
.refclk (pcie_l_refclk),
.rx_in (pcie_l_rx),
.lane_act (lane_act),
.tx_out (pcie_l_tx),
.tag_sent (sys_ctl_reg[11:6]),
.rdpkt_limit (rdpkt_limit),
.in_rdma_pkt (in_rdma_pkt),
.in_rdma_pkt_wr (in_rdma_pkt_wr),
.in_rdma_valid_wr (in_rdma_valid_wr),
.in_rdma_valid (in_rdma_valid),
.out_rdma_pkt_almostfull (out_rdma_pkt_almostfull),
.in_tdma_rdpkt (in_tdma_rdpkt),
.in_tdma_rdpkt_wr (in_tdma_rdpkt_wr),
.out_tdma_rdpkt_usedw (out_tdma_rdpkt_usedw),
.out_tdma_des_wr (in_pcietx_des_wr),
.out_tdma_des (in_pcietx_des),
.localbus_out (localbus_out),//lxj1011
.localbus_out_wr (localbus_out_wr),//lxj1011
.localbus_in (localbus_in),//lxj1011
.localbus_in_wr (localbus_in_wr),//lxj1011
.out_tdma_pkt_wr (in_pcietx_pkt_wr),
.out_tdma_pkt (in_pcietx_pkt),
.in_tdma_pkt_almostfull (out_pcietx_pkt_almostfull),
.out_tdma_valid (in_pcietx_pkt_valid),
.out_tdma_valid_wr (in_pcietx_pkt_valid_wr),
.pcierx_receive_pktrdrequest_add (pcierx_receive_pktrdrequest_add),
.pcierx_receive_memrequest_add (pcierx_receive_memrequest_add),
.pcietx_receive_memrequest_add (pcietx_receive_memrequest_add),
.pcietx_receive_completion_pkt_add (pcietx_receive_completion_pkt_add),
.pcietx_storage_pkt_add (pcietx_storage_pkt_add),
.pcietx_sent_pkt_add (pcietx_sent_pkt_add),
.pcietx_receive_zeroindex_add (pcietx_receive_zeroindex_add),
.pcie_test (pcietx_test)
);
wire pcietx_receive_zeroindex_add;
wire pcietx_test;
wire in_inputctrl_pkt_wr;
wire [133:0] in_inputctrl_pkt;
wire out_inputctrl_pkt_almostfull;
wire in_inputctrl_valid_wr;
wire in_inputctrl_valid;
wire [133:0] in_tdma_pkt;
wire in_tdma_pkt_wr;
wire out_tdma_pkt_almostfull;
wire in_tdma_valid;
wire in_tdma_valid_wr;
IPE_PPS IPE_PPS(
.clk (app_clk),
.reset (reset_rn),
//.reset (cnt_reset),
.in_fpgaac_channel_num (sys_ctl_reg[5:0]),
.in_fpgaac_cpuid_cs (sys_ctl_reg[15]),
.cpuid_valid (32'hFFFFFFFF),
.out_rdma_pkt_wr (in_dispather_pkt_wr),
.out_rdma_pkt (in_dispather_pkt),
.out_rdma_valid_wr (in_dispather_valid_wr),
.out_rdma_valid (in_dispather_valid),
.in_rdma_pkt_almostfull (out_dispather_pkt_almostfull),
.in_tdma_pkt_wr (in_tdma_pkt_wr),
.in_tdma_pkt (in_tdma_pkt),
.in_tdma_valid_wr (in_tdma_valid_wr),
.in_tdma_valid (in_tdma_valid),
.out_tdma_pkt_almostfull (out_tdma_pkt_almostfull),
.in_inputctrl_pkt_wr (um_to_npe_pkt_wr),
.in_inputctrl_pkt (um_to_npe_pkt),
.in_inputctrl_valid_wr (um_to_npe_pkt_valid_wr),
.in_inputctrl_valid (um_to_npe_pkt_valid),
.out_inputctrl_pkt_almostfull (um_to_npe_pkt_almful),
.out_outputctrl_pkt_wr (npe_to_um_pkt_wr),
.out_outputctrl_pkt (npe_to_um_pkt),
.out_outputctrl_valid_wr (npe_to_um_pkt_valid_wr),
.out_outputctrl_valid (npe_to_um_pkt_valid),
.in_outputctrl_pkt_almostfull (npe_to_um_pkt_almful)
/*
.in_inputctrl_pkt_wr (),
.in_inputctrl_pkt (),
.in_inputctrl_valid_wr (),
.in_inputctrl_valid (),
.out_inputctrl_pkt_almostfull (),
.out_outputctrl_pkt_wr (um_to_npe_pkt_wr),
.out_outputctrl_pkt (um_to_npe_pkt),
.out_outputctrl_valid_wr (um_to_npe_pkt_valid_wr),
.out_outputctrl_valid (um_to_npe_pkt_valid),
.in_outputctrl_pkt_almostfull (um_to_npe_pkt_almful)
*/
);
wire reset_reg;
wire in_ramwr_iace_rd_wr;
wire [127:0] in_ramwr_iace_data;
wire [20:0] in_ramwr_iace_addr;
wire [127:0] out_ramwr_iace_rd_data;
wire in_ramwr_iace_cs_n;
wire out_ramwr_iace_rd_ack_n;
wire [92:0] localbus_out;//lxj1011
wire localbus_out_wr;//lxj1011
wire [92:0] localbus_in;//lxj1011
wire localbus_in_wr;//lxj1011
wire [15:0] sys_ctl_reg;
wire [31:0] cpuid_valid;
//MAC
wire slot0_port0_pkt_receive_add;
wire slot0_port0_pkt_discard_add;
wire slot0_port0_pkt_send_add;
wire slot0_port1_pkt_receive_add;
wire slot0_port1_pkt_discard_add;
wire slot0_port1_pkt_send_add;
wire slot0_port2_pkt_receive_add;
wire slot0_port2_pkt_discard_add;
wire slot0_port2_pkt_send_add;
wire slot0_port3_pkt_receive_add;
wire slot0_port3_pkt_discard_add;
wire slot0_port3_pkt_send_add;
wire slot0_port4_pkt_receive_add;
wire slot0_port4_pkt_discard_add;
wire slot0_port4_pkt_send_add;
wire slot1_port0_pkt_receive_add;
wire slot1_port0_pkt_discard_add;
wire slot1_port0_pkt_send_add;
wire slot1_port1_pkt_receive_add;
wire slot1_port1_pkt_discard_add;
wire slot1_port1_pkt_send_add;
wire slot1_port2_pkt_receive_add;
wire slot1_port2_pkt_discard_add;
wire slot1_port2_pkt_send_add;
wire slot1_port3_pkt_receive_add;
wire slot1_port3_pkt_discard_add;
wire slot1_port3_pkt_send_add;
wire slot1_port4_pkt_receive_add;
wire slot1_port4_pkt_discard_add;
wire slot1_port4_pkt_send_add;
//SYS clock field
wire [31:0] cpuid_process_desc_add;//201312241134
wire [31:0] cpuid_receive_pkt_add;//201312241134
wire [31:0] cpuid_softaddr_add;//201403101619
wire tdma_receive_pcietx_desc_add;
wire tdma_receive_generate_desc_add;
wire tdma_discard_desc_add;
wire tdma_discard_overload_add;
wire tdma_recycle_index_add;
wire rdma_receive_pkt_add;
wire rdma_receive_addr_add;
wire mux0_receive_pkt_add;
wire mux0_discard_error_pkt_add;
wire mux1_receive_pkt_add;
wire mux1_discard_error_pkt_add;
wire dmux0_receive_pkt_add;
wire dmux0_discard_error_pkt_add;
wire dmux0_send_port0_pkt_add;
wire dmux0_send_port1_pkt_add;
wire dmux0_send_port2_pkt_add;
wire dmux0_send_port3_pkt_add;
wire dmux0_send_port4_pkt_add;
wire dmux1_receive_pkt_add;
wire dmux1_discard_error_pkt_add;
wire dmux1_send_port0_pkt_add;
wire dmux1_send_port1_pkt_add;
wire dmux1_send_port2_pkt_add;
wire dmux1_send_port3_pkt_add;
wire dmux1_send_port4_pkt_add;
wire inputctl_receive_pkt_add;
wire output_receive_pkt_add;
wire output_discard_error_pkt_add;
wire output_send_slot0_pkt_add;
wire output_send_slot1_pkt_add;
//pcie clock field
wire pcierx_receive_pktrdrequest_add;
wire pcierx_receive_memrequest_add;
wire pcietx_receive_memrequest_add;
wire pcietx_receive_completion_pkt_add;
wire pcietx_storage_pkt_add;
wire pcietx_sent_pkt_add;
wire [31:0] card_inf;
wire [31:0] rdpkt_limit;
//assign card_inf[3:0] = CARD2_ID[3:0];
//assign card_inf[7:4] = CARD1_ID[3:0];
//assign card_inf[31:8] ={4'h2,4'h0,4'h2,4'h3,4'h0,4'h0};//31:28
//assign card_inf[31:8] ={4'h1,4'h0,4'h2,4'h3,4'h1,4'h1};//31:28
assign card_inf[31:8] ={4'h3,4'h0,4'h2,4'h3,4'h1,4'h2};//31:28
NPE_CAB NPE_CAB(
.pcie_clk (pcie_clk),
.reset (reset_rn),
//.reset (cnt_reset),
.app_clk (app_clk),
.localbus_in (localbus_in),
.localbus_in_wr (localbus_in_wr),
.clk_mac (app_clk),//there is a problem!!
.localbus_out (localbus_out),
.localbus_out_wr (localbus_out_wr),
//FPGA CTL
.reset_reg (reset_reg),
.sys_ctl_reg (sys_ctl_reg),
.cpuid_valid (cpuid_valid),
.dma_addr (in_fpga_base_addr),
.dma_addr_wr (in_fpga_base_addr_wr),
.virhead_reg (in_fpga_virhead),
.card_inf (card_inf),
.rdpkt_limit (rdpkt_limit),
.command (command),
.command_wr (command_wr),
.data_out (data_out),
.cab2burner_clk (I2C_CLK),//add the I2C clock
.cab2burner_data (I2C_SDA),//add the I2C data
//spi
.spi_refclk (spi_refclk),
.slot0_spi_miso (),
.slot0_spi_mosi (),
.slot0_spi_clk (),
.slot0_spi_cs_n (),
.slot1_spi_miso (),
.slot1_spi_mosi (),
.slot1_spi_clk (),
.slot1_spi_cs_n (),
//MAC clock field
.slot0_port0_pkt_receive_add (slot0_port0_pkt_receive_add),
.slot0_port0_pkt_discard_add (slot0_port0_pkt_discard_add),
.slot0_port0_pkt_send_add (slot0_port0_pkt_send_add),
.slot0_port1_pkt_receive_add (slot0_port1_pkt_receive_add),
.slot0_port1_pkt_discard_add (slot0_port1_pkt_discard_add),
.slot0_port1_pkt_send_add (slot0_port1_pkt_send_add),
.slot0_port2_pkt_receive_add (slot0_port2_pkt_receive_add),
.slot0_port2_pkt_discard_add (slot0_port2_pkt_discard_add),
.slot0_port2_pkt_send_add (slot0_port2_pkt_send_add),
.slot0_port3_pkt_receive_add (slot0_port3_pkt_receive_add),
.slot0_port3_pkt_discard_add (slot0_port3_pkt_discard_add),
.slot0_port3_pkt_send_add (slot0_port3_pkt_send_add),
.slot0_port4_pkt_receive_add (slot0_port4_pkt_receive_add),
.slot0_port4_pkt_discard_add (slot0_port4_pkt_discard_add),
.slot0_port4_pkt_send_add (slot0_port4_pkt_send_add),
.slot1_port0_pkt_receive_add (slot1_port0_pkt_receive_add),
.slot1_port0_pkt_discard_add (slot1_port0_pkt_discard_add),
.slot1_port0_pkt_send_add (slot1_port0_pkt_send_add),
.slot1_port1_pkt_receive_add (slot1_port1_pkt_receive_add),
.slot1_port1_pkt_discard_add (slot1_port1_pkt_discard_add),
.slot1_port1_pkt_send_add (slot1_port1_pkt_send_add),
.slot1_port2_pkt_receive_add (slot1_port2_pkt_receive_add),
.slot1_port2_pkt_discard_add (slot1_port2_pkt_discard_add),
.slot1_port2_pkt_send_add (slot1_port2_pkt_send_add),
.slot1_port3_pkt_receive_add (slot1_port3_pkt_receive_add),
.slot1_port3_pkt_discard_add (slot1_port3_pkt_discard_add),
.slot1_port3_pkt_send_add (slot1_port3_pkt_send_add),
.slot1_port4_pkt_receive_add (slot1_port4_pkt_receive_add),
.slot1_port4_pkt_discard_add (slot1_port4_pkt_discard_add),
.slot1_port4_pkt_send_add (slot1_port4_pkt_send_add),
//SYS clock field
.cpuid_process_desc_add (cpuid_process_desc_add),//201312241134
.cpuid_receive_pkt_add (cpuid_receive_pkt_add),//201312241134
.cpuid_softaddr_add (cpuid_softaddr_add),//201403101619
.tdma_receive_pcietx_desc_add (tdma_receive_pcietx_desc_add),
.tdma_receive_generate_desc_add (tdma_receive_generate_desc_add),
.tdma_discard_desc_add (tdma_discard_desc_add),
.tdma_discard_overload_add (tdma_discard_overload_add),
.tdma_recycle_index_add (tdma_recycle_index_add),
.rdma_receive_pkt_add (rdma_receive_pkt_add),
.rdma_receive_addr_add (rdma_receive_addr_add),
.mux0_receive_pkt_add (mux0_receive_pkt_add),
.mux0_discard_error_pkt_add (mux0_discard_error_pkt_add),
.mux1_receive_pkt_add (mux1_receive_pkt_add),
.mux1_discard_error_pkt_add (mux1_discard_error_pkt_add),
.dmux0_receive_pkt_add (dmux0_receive_pkt_add),
.dmux0_discard_error_pkt_add (dmux0_discard_error_pkt_add),
.dmux0_send_port0_pkt_add (dmux0_send_port0_pkt_add),
.dmux0_send_port1_pkt_add (dmux0_send_port1_pkt_add),
.dmux0_send_port2_pkt_add (dmux0_send_port2_pkt_add),
.dmux0_send_port3_pkt_add (dmux0_send_port3_pkt_add),
.dmux0_send_port4_pkt_add (dmux0_send_port4_pkt_add),
.dmux1_receive_pkt_add (dmux1_receive_pkt_add),
.dmux1_discard_error_pkt_add (dmux1_discard_error_pkt_add),
.dmux1_send_port0_pkt_add (dmux1_send_port0_pkt_add),
.dmux1_send_port1_pkt_add (dmux1_send_port1_pkt_add),
.dmux1_send_port2_pkt_add (dmux1_send_port2_pkt_add),
.dmux1_send_port3_pkt_add (dmux1_send_port3_pkt_add),
.dmux1_send_port4_pkt_add (dmux1_send_port4_pkt_add),
.inputctl_receive_pkt_add (inputctl_receive_pkt_add),
.output_receive_pkt_add (output_receive_pkt_add),
.output_discard_error_pkt_add (output_discard_error_pkt_add),
.output_send_slot0_pkt_add (output_send_slot0_pkt_add),
.output_send_slot1_pkt_add (output_send_slot1_pkt_add),
//pcie clock field
.pcierx_receive_pktrdrequest_add (pcierx_receive_pktrdrequest_add),
.pcierx_receive_memrequest_add (pcierx_receive_memrequest_add),
.pcietx_receive_memrequest_add (pcietx_receive_memrequest_add),
.pcietx_receive_completion_pkt_add (pcietx_receive_completion_pkt_add),
.pcietx_storage_pkt_add (pcietx_storage_pkt_add),
.pcietx_sent_pkt_add (pcietx_sent_pkt_add),
.pcietx_receive_zeroindex_add (pcietx_receive_zeroindex_add),
.pcietx_test (pcietx_test),
//avalon-MM
.ammc_clk (app_clk),
.address0 (slot0_port0_address),
.write0 (slot0_port0_write),
.read0 (slot0_port0_read),
.writedata0 (slot0_port0_writedata),
.readdata0 (slot0_port0_readdata),
.waitrequest0 (slot0_port0_waitrequest),
.address1 (slot0_port1_address),
.write1 (slot0_port1_write),
.read1 (slot0_port1_read),
.writedata1 (slot0_port1_writedata),
.readdata1 (slot0_port1_readdata),
.waitrequest1 (slot0_port1_waitrequest),
.address2 (slot0_port2_address),
.write2 (slot0_port2_write),
.read2 (slot0_port2_read),
.writedata2 (slot0_port2_writedata),
.readdata2 (slot0_port2_readdata),
.waitrequest2 (slot0_port2_waitrequest),
.address3 (slot0_port3_address),
.write3 (slot0_port3_write),
.read3 (slot0_port3_read),
.writedata3 (slot0_port3_writedata),
.readdata3 (slot0_port3_readdata),
.waitrequest3 (slot0_port3_waitrequest),
.address4 (slot0_port4_address),
.write4 (slot0_port4_write),
.read4 (slot0_port4_read),
.writedata4 (slot0_port4_writedata),
.readdata4 (slot0_port4_readdata),
.waitrequest4 (slot0_port4_waitrequest),
.address5 (slot1_port0_address),
.write5 (slot1_port0_write),
.read5 (slot1_port0_read),
.writedata5 (slot1_port0_writedata),
.readdata5 (slot1_port0_readdata),
.waitrequest5 (slot1_port0_waitrequest),
.address6 (slot1_port1_address),
.write6 (slot1_port1_write),
.read6 (slot1_port1_read),
.writedata6 (slot1_port1_writedata),
.readdata6 (slot1_port1_readdata),
.waitrequest6 (slot1_port1_waitrequest),
.address7 (slot1_port2_address),
.write7 (slot1_port2_write),
.read7 (slot1_port2_read),
.writedata7 (slot1_port2_writedata),
.readdata7 (slot1_port2_readdata),
.waitrequest7 (slot1_port2_waitrequest),
.address8 (slot1_port3_address),
.write8 (slot1_port3_write),
.read8 (slot1_port3_read),
.writedata8 (slot1_port3_writedata),
.readdata8 (slot1_port3_readdata),
.waitrequest8 (slot1_port3_waitrequest),
.address9 (slot1_port4_address),
.write9 (slot1_port4_write),
.read9 (slot1_port4_read),
.writedata9 (slot1_port4_writedata),
.readdata9 (slot1_port4_readdata),
.waitrequest9 (slot1_port4_waitrequest)
);
//*****************************************//
always@(posedge app_clk or negedge FPGA_RESET_L) begin
if(!FPGA_RESET_L)begin
reset_count<=0;
cnt_reset<=1'b0;
SFP_ACTIVE_LED_REG<=8'b11111111;
SFP_LINK_LED_REG<=8'b11111111;
end
else begin
if(reset_count==65535)begin
cnt_reset<=1'b1;
SFP_ACTIVE_LED_REG<=8'b00000000;
SFP_LINK_LED_REG<=8'b00000000;
end
else begin
reset_count<=reset_count+1'b1;
cnt_reset<=1'b0;
end
end
end
//*****************************************//
endmodule |
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module asyn_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module rule_32_30 (
aclr,
clock,
data,
rdreq,
wrreq,
q,
usedw);
input aclr;
input clock;
input [29:0] data;
input rdreq;
input wrreq;
output [29:0] q;
output [4:0] usedw;
endmodule |
module CLK_MANAGE(
//--------------------------------input clk_ Manage Module-------------------------
input FPGA_GMII_REFCLK,//125M
input PCIE_REFCK,//100M
input CLK_FPGA_REFCK,//125M
//--------------------------------genarate clk_ Manage Module-------------------------
output app_clk,
output reconfig_clk,
output spi_refclk);
card1_pll card1_pll(//genarate clk for right side of port_ip core
.inclk0 (CLK_FPGA_REFCK),//156.25M
.c0 (app_clk),//125M
.c2 (reconfig_clk),
.c3 (spi_refclk),
.locked ()
);
endmodule |
module loacal_sw(
input clk,
input reset,
output reg [31:0] data_out,
input [64:0] command,
input command_wr,
output reg ale,
output reg cs_n,
output reg rd_wr,
output reg [31:0] data,
input ack_n_um,
input [31:0] rdata_um
);
reg command_rd;
reg [64:0] command_q_r;
wire [64:0] command_q;
wire command_wr_empty;
reg [7:0] count;
reg [2:0] current_state;
localparam
idle_s = 'd1,
ale_s = 'd2,
cs_s = 'd3,
wait_ack_s = 'd4,
wait_addr_s = 'd5,
wait_addr_s1 = 'd6;
always @(posedge clk or negedge reset)
if(!reset) begin
ale <= 1'b0;
cs_n <= 1'b1;
rd_wr <= 1'b1;
data <= 32'b0;
command_rd <= 1'b0;
command_q_r <= 65'b0;
data_out <= 32'b0;
count <= 8'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
ale <= 1'b0;
cs_n <= 1'b1;
rd_wr <= 1'b1;
count <= 8'b0;
command_rd <= 1'b0;
if(command_wr_empty == 1'b1) begin
current_state <= idle_s;
end
else begin
command_rd <= 1'b1;
command_q_r <= command_q;
data <= command_q[63:32];
rd_wr <= command_q[64]; //0:wr 1:read
current_state <= ale_s;
end
end
ale_s : begin
ale <= 1'b1;
command_rd <= 1'b0;
current_state <= cs_s;
end
cs_s: begin
ale <= 1'b0;
//cs_n <= 1'b0;
//data <= command_q_r[31:0];
current_state <= wait_addr_s;
end
wait_addr_s:begin
current_state <= wait_addr_s1;
end
wait_addr_s1: begin
data <= command_q_r[31:0];
cs_n <= 1'b0;
current_state <= wait_ack_s;
end
wait_ack_s: begin
if(ack_n_um == 1'b0) begin
cs_n <= 1'b0;
data_out <= rdata_um;
current_state <= idle_s;
end
else begin
count <= count + 1'b1;
if(count[7:4] == 4'b1111) begin
current_state <= idle_s;
end
else begin
current_state <= wait_ack_s;
end
end
end
endcase
end
fifo_65_256 command_fifo(//crc check result fifo;
.aclr(!reset),
.clock(clk),
.data(command),
.rdreq(command_rd),
.wrreq(command_wr),
.empty(command_wr_empty),
.q(command_q)
);
endmodule |
module user_mgmt_slave(
input clk,
input rst_n,
//from localbus master
input localbus_cs_n,
input localbus_rd_wr,//0 write 1:read
input [31:0] localbus_data,
input localbus_ale,
output localbus_ack_n,
output [31:0] localbus_data_out,
//to bv lookup
output cfg2lookup_cs_n,
output cfg2lookup_rd_wr,
output [31:0] cfg2lookup_data,
output cfg2lookup_ale,
input lookup2cfg_ack_n,
input [31:0] lookup2cfg_data_out,
//to rule mgmt
output reg cfg2rule_cs,//high active
input rule2cfg_ack,//high active ,handshake with cfg2rule_cs
output cfg2rule_rw,//0:read 1:write
output reg [15:0] cfg2rule_addr,
output [31:0] cfg2rule_wdata,
input [31:0] rule2cfg_rdata
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
reg [1:0] ram_state;
reg [31:0] addr_latch;//latch the address when local_ale assert
//***************************************************
// Address Allocate
//***************************************************
assign localbus_ack_n = lookup2cfg_ack_n && (~rule2cfg_ack);
assign localbus_data_out = (rule2cfg_ack == 1'b1) ? rule2cfg_rdata : lookup2cfg_data_out;
//*******************
// Lookup Allocate
//*******************
always @(posedge clk) begin
if(localbus_ale == 1'b1) begin
addr_latch <= cfg2lookup_data;
end
else begin
addr_latch <= addr_latch;
end
end
//tell lzn add address space judge logic in his module
assign cfg2lookup_cs_n = (addr_latch[31:20] == 12'd0) ? localbus_cs_n : 1'b1;
assign cfg2lookup_rd_wr = localbus_rd_wr;
assign cfg2lookup_data = localbus_data;
assign cfg2lookup_ale = (cfg2lookup_data[31:20] == 12'd0) ? localbus_ale : 1'b0;
//*******************
// Ram Allocate
//*******************
assign cfg2rule_rw = ~localbus_rd_wr;
assign cfg2rule_wdata = localbus_data;
localparam IDLE_S = 2'd0,
SEND_S = 2'd1,
RELEASE_S = 2'd2;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
cfg2rule_cs <= 1'b0;
ram_state <= IDLE_S;
end
else begin
case(ram_state)
IDLE_S: begin
cfg2rule_cs <= 1'b0;
if(localbus_ale == 1'b1) begin
if(localbus_data[31:20] == 12'd1) begin//ram address space
cfg2rule_addr <= localbus_data[15:0];
ram_state <= SEND_S;
end
else begin
ram_state <= IDLE_S;
end
end
else begin
ram_state <= IDLE_S;
end
end
SEND_S: begin//wait cfg data
if(localbus_cs_n == 1'b0) begin
cfg2rule_cs <= 1'b1;
ram_state <= RELEASE_S;
end
else begin
cfg2rule_cs <= 1'b0;
ram_state <= SEND_S;
end
end
RELEASE_S: begin//wait localbus cs&ack handshake over
if(localbus_cs_n == 1'b0) begin
cfg2rule_cs <= 1'b1;
ram_state <= RELEASE_S;
end
else begin
cfg2rule_cs <= 1'b0;
ram_state <= IDLE_S;
end
end
default: begin
cfg2rule_cs <= 1'b0;
ram_state <= IDLE_S;
end
endcase
end
end
endmodule |
module UM(
input clk,
input rst_n,
input [5:0] sys_max_cpuid,
//cdp
input cdp2um_data_wr,
input [133:0] cdp2um_data,
input cdp2um_valid_wr,
input cdp2um_valid,
output um2cdp_alf,
output um2cdp_data_wr,
output [133:0] um2cdp_data,
output um2cdp_valid_wr,
output um2cdp_valid,
input cdp2um_alf,
//npe
input npe2um_data_wr,
input [133:0] npe2um_data,
input npe2um_valid_wr,
input npe2um_valid,
output um2npe_alf,
output um2npe_data_wr,
output [133:0] um2npe_data,
output um2npe_valid_wr,
output um2npe_valid,
input npe2um_alf,
//localbus
input localbus_cs_n,
input localbus_rd_wr,
input [31:0] localbus_data,
input localbus_ale,
output localbus_ack_n,
output [31:0] localbus_data_out
);
wire slave2lookup_cs_n;
wire slave2lookup_rd_wr;
wire [31:0] slave2lookup_data;
wire slave2lookup_ale;
wire lookup2slave_ack_n;
wire [31:0] lookup2slave_data_out;
//to rule mgmt
wire slave2rule_cs;//high active
wire rule2slave_ack;//high active ;handshake with slave2rule_cs
wire slave2rule_rw;//0:read 1:write
wire [15:0] slave2rule_addr;
wire [31:0] slave2rule_wdata;
wire [31:0]rule2slave_rdata;
wire parser2lookup_key_wr;
wire [287:0] parser2lookup_key;
wire parser2exe_data_wr;
wire [133:0] parser2exe_data;
wire exe2parser_alf;
wire lookup2rule_index_wr;
wire [5:0] lookup2rule_index;
wire rule2exe_data_wr;//index read return valid
wire [31:0] rule2exe_data;
wire exe2disp_direction_req;
wire exe2disp_direction;//0:up cpu 1: down port
wire exe2disp_data_wr;
wire [133:0] exe2disp_data;
wire exe2disp_valid_wr;
wire exe2disp_valid;
wire disp2exe_alf;
wire disp2usermux_data_wr;
wire [133:0] disp2usermux_data;
wire disp2usermux_valid_wr;
wire disp2usermux_valid;
wire usermux2disp_alf;
user_mgmt_slave user_mgmt_slave(
.clk(clk),
.rst_n(rst_n),
//from localbus master
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),//0 write 1:read
.localbus_data(localbus_data),
.localbus_ale(localbus_ale),
.localbus_ack_n(localbus_ack_n),
.localbus_data_out(localbus_data_out),
//to bv lookup
.cfg2lookup_cs_n(slave2lookup_cs_n),
.cfg2lookup_rd_wr(slave2lookup_rd_wr),
.cfg2lookup_data(slave2lookup_data),
.cfg2lookup_ale(slave2lookup_ale),
.lookup2cfg_ack_n(lookup2slave_ack_n),
.lookup2cfg_data_out(lookup2slave_data_out),
//to rule mgmt
.cfg2rule_cs(slave2rule_cs),//high active
.rule2cfg_ack(rule2slave_ack),//high active,handshake with cfg2rule_cs
.cfg2rule_rw(slave2rule_rw),//0:read 1:write
.cfg2rule_addr(slave2rule_addr),
.cfg2rule_wdata(slave2rule_wdata),
.rule2cfg_rdata(rule2slave_rdata)
);
parser parser(
.clk(clk),
.rst_n(rst_n),
//input pkt from port
.port2parser_data_wr(cdp2um_data_wr),
.port2parser_data(cdp2um_data),
.port2parser_valid_wr(cdp2um_valid_wr),
.port2parser_valid(cdp2um_valid),
.parser2port_alf(um2cdp_alf),
//parse key which transmit to lookup
.parser2lookup_key_wr(parser2lookup_key_wr),
.parser2lookup_key(parser2lookup_key),
//transport to next module
.parser2next_data_wr(parser2exe_data_wr),
.parser2next_data(parser2exe_data),
.next2parser_alf(exe2parser_alf)
);
lookup BV_Search_engine(
.clk(clk),
.reset(rst_n),//low active
.localbus_cs_n(slave2lookup_cs_n),
.localbus_rd_wr(slave2lookup_rd_wr),//0 write 1:read
.localbus_data(slave2lookup_data),
.localbus_ale(slave2lookup_ale),
.localbus_ack_n(lookup2slave_ack_n),
.localbus_data_out(lookup2slave_data_out),
.metadata_valid(parser2lookup_key_wr),
.metadata(parser2lookup_key),
.countid_valid(lookup2rule_index_wr),
.countid(lookup2rule_index)//6bit width?
);
rule_access rule_access(
.clk(clk),
.rst_n(rst_n),
//lookup rule read index
.lookup2rule_index_wr(lookup2rule_index_wr),
.lookup2rule_index({10'b0,lookup2rule_index}),//16bit width
.rule2lookup_data_wr(rule2exe_data_wr),//index read return valid
.rule2lookup_data(rule2exe_data),
//user cfg require
.cfg2rule_cs(slave2rule_cs),//high active
.rule2cfg_ack(rule2slave_ack),//high active,handshake with cfg2rule_cs
.cfg2rule_rw(slave2rule_rw),//0:read 1:write
.cfg2rule_addr(slave2rule_addr),
.cfg2rule_wdata(slave2rule_wdata),
.rule2cfg_rdata(rule2slave_rdata)
);
executer executer(
.clk(clk),
.rst_n(rst_n),
.sys_max_cpuid(sys_max_cpuid),
//pkt waiting for rule
.parser2exe_data_wr(parser2exe_data_wr),
.parser2exe_data(parser2exe_data),
.exe2parser_alf(exe2parser_alf),
//rule from lookup engine(BV_search_engine)
.lookup2exe_rule_wr(rule2exe_data_wr),
.lookup2exe_rule(rule2exe_data),
//execute's tranmit direction request
.exe2disp_direction_req(exe2disp_direction_req),
.exe2disp_direction(exe2disp_direction),//0:up cpu 1: down port
//transmit to next module(dispatch)
.exe2disp_data_wr(exe2disp_data_wr),
.exe2disp_data(exe2disp_data),
.exe2disp_valid_wr(exe2disp_valid_wr),
.exe2disp_valid(exe2disp_valid),
.disp2exe_alf(disp2exe_alf)
);
dispatch dispatch(
.clk(clk),
.rst_n(rst_n),
//execute module's pkt waiting for transmit
.exe2disp_data_wr(exe2disp_data_wr),
.exe2disp_data(exe2disp_data),
.exe2disp_valid_wr(exe2disp_valid_wr),
.exe2disp_valid(exe2disp_valid),
.disp2exe_alf(disp2exe_alf),
//execute's tranmit direction request
.exe2disp_direction_req(exe2disp_direction_req),
.exe2disp_direction(exe2disp_direction),//0:up cpu 1: down port
//transmit to up cpu
.disp2up_data_wr(um2npe_data_wr),
.disp2up_data(um2npe_data),
.disp2up_valid_wr(um2npe_valid_wr),
.disp2up_valid(um2npe_valid),
.up2disp_alf(npe2um_alf),
//transmit to down port
.disp2down_data_wr(disp2usermux_data_wr),
.disp2down_data(disp2usermux_data),
.disp2down_valid_wr(disp2usermux_valid_wr),
.disp2down_valid(disp2usermux_valid),
.down2disp_alf(usermux2disp_alf)
);
user_mux user_mux(
.clk(clk),
.rst_n(rst_n),
//lookup pkt waiting for transmit
.disp2usermux_data_wr(disp2usermux_data_wr),
.disp2usermux_data(disp2usermux_data),
.disp2usermux_valid_wr(disp2usermux_valid_wr),
.disp2usermux_valid(disp2usermux_valid),
.usermux2disp_alf(usermux2disp_alf),
//up cpu pkt waiting for transmit
.up2usermux_data_wr(npe2um_data_wr),
.up2usermux_data(npe2um_data),
.up2usermux_valid_wr(npe2um_valid_wr),
.up2usermux_valid(npe2um_valid),
.usermux2up_alf(um2npe_alf),
//transmit to down port
.usermux2down_data_wr(um2cdp_data_wr),
.usermux2down_data(um2cdp_data),
.usermux2down_valid_wr(um2cdp_valid_wr),
.usermux2down_valid(um2cdp_valid),
.down2usermux_alf(cdp2um_alf)
);
endmodule |
module executer(
input clk,
input rst_n,
input [5:0] sys_max_cpuid,
//pkt waiting for rule
input parser2exe_data_wr,
input [133:0] parser2exe_data,
output exe2parser_alf,
//rule from lookup engine(BV_search_engine)
input lookup2exe_rule_wr,
input [31:0] lookup2exe_rule,
//execute's tranmit direction request
output exe2disp_direction_req,
output exe2disp_direction,//0:up cpu 1: down port
//transmit to next module(dispatch)
output reg exe2disp_data_wr,
output reg [133:0] exe2disp_data,
output reg exe2disp_valid_wr,
output exe2disp_valid,
input disp2exe_alf
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
reg exe_dfifo_rd;
wire [133:0] exe_dfifo_rdata;
wire [7:0] exe_dfifo_usedw;
reg rule_fifo_rd;
reg rule_fifo_rd_dly;
wire [31:0] rule_fifo_rdata;
wire rule_fifo_empty;
reg [5:0] polling_cpuid;//polling cpuid if rule ctrl is trans to CPU with polling thread id
reg [1:0] exe_state;
//***************************************************
// Stream Judge
//***************************************************
assign exe2disp_valid = exe2disp_valid_wr;
assign exe2parser_alf = exe_dfifo_usedw[7];
assign exe2disp_direction_req = (rule_fifo_empty == 1'b0);
//when rule fifo have data(at least a rule),and not a discard rule
//so the rule fifo must be a showahead mode
assign exe2disp_direction = (rule_fifo_rdata[31:28] == 4'd3) ? 1'b1 : 1'b0;
////0:up cpu 1: down port ,don't care discard,because exe2disp_direction_req will
//be invalid if rule_fifo_rdata[31:28] is discard rule
localparam IDLE_S = 2'd0,
METADATA_S = 2'd1,
TRANS_S = 2'd2,
DISCARD_S = 2'd3;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
exe_dfifo_rd <= 1'b0;
rule_fifo_rd <= 1'b0;
exe2disp_data_wr <= 1'b0;
exe2disp_valid_wr <= 1'b0;
polling_cpuid <= 6'b0;
exe_state <= IDLE_S;
end
else begin
case(exe_state)
IDLE_S: begin
exe2disp_data_wr <= 1'b0;
exe2disp_valid_wr <= 1'b0;
if((rule_fifo_empty == 1'b0) && (disp2exe_alf == 1'b0)) begin
//have a rule & next module can receive pkt
exe_dfifo_rd <= 1'b1;
rule_fifo_rd <= 1'b1;
exe_state <= METADATA_S;
end
else begin
exe_dfifo_rd <= 1'b0;
rule_fifo_rd <= 1'b0;
exe_state <= IDLE_S;
end
end
METADATA_S: begin
rule_fifo_rd <= 1'b0;
case(rule_fifo_rdata[31:28])
4'd1: begin//1 trans to CPU with thread id assignd by user
exe2disp_data_wr <= 1'b1;
exe2disp_data[133:56] <= exe_dfifo_rdata[133:56];
exe2disp_data[55:47] <= {1'b0,rule_fifo_rdata[7:0]};
exe2disp_data[46:0] <= exe_dfifo_rdata[46:0];
exe_state <= TRANS_S;
end
4'd2: begin//2 trans to CPU with polling thread id
exe2disp_data_wr <= 1'b1;
exe2disp_data[133:56] <= exe_dfifo_rdata[133:56];
exe2disp_data[55:47] <= {3'b0,polling_cpuid};
exe2disp_data[46:0] <= exe_dfifo_rdata[46:0];
if((polling_cpuid+6'b1) < sys_max_cpuid) begin
//if use sys_max_cpuid -1,maybe underflow
polling_cpuid <= polling_cpuid + 6'd1;
end
else begin
polling_cpuid <= 6'b0;
end
exe_state <= TRANS_S;
end
4'd3: begin//3 trans to port
exe2disp_data_wr <= 1'b1;
//modify by lxj 20161011 start
exe2disp_data[133:113] <= exe_dfifo_rdata[133:113];
exe2disp_data[109:74] <= exe_dfifo_rdata[109:74];
if(rule_fifo_rdata[7:4] == 4'b0) begin//slot0
exe2disp_data[112:110] <= 3'b0;
exe2disp_data[73:64] <= {6'b0,rule_fifo_rdata[3:0]};
end
else begin//slot1
exe2disp_data[112:110] <= 3'b1;
exe2disp_data[73:64] <= {6'b0,rule_fifo_rdata[7:4]};
end
//modify by lxj 20161011 end
//exe2disp_data[73:64] <= {2'b0,rule_fifo_rdata[7:0]};
exe2disp_data[63:0] <= exe_dfifo_rdata[63:0];
exe_state <= TRANS_S;
end
default: begin//discard
exe2disp_data_wr <= 1'b0;
exe_state <= DISCARD_S;
end
endcase
end
TRANS_S: begin
exe2disp_data_wr <= 1'b1;
exe2disp_data <= exe_dfifo_rdata;
if(exe_dfifo_rdata[133:132] == 2'b10) begin//end of pkt
exe_dfifo_rd <= 1'b0;
exe2disp_valid_wr <= 1'b1;
exe_state <= IDLE_S;
end
else begin
exe_dfifo_rd <= 1'b1;
exe2disp_valid_wr <= 1'b0;
exe_state <= TRANS_S;
end
end
DISCARD_S: begin
rule_fifo_rd <= 1'b0;
exe2disp_data_wr <= 1'b0;
if(exe_dfifo_rdata[133:132] == 2'b10) begin//end of pkt
exe_dfifo_rd <= 1'b0;
exe_state <= IDLE_S;
end
else begin
exe_dfifo_rd <= 1'b1;
exe_state <= DISCARD_S;
end
end
default: begin
exe_dfifo_rd <= 1'b0;
rule_fifo_rd <= 1'b0;
exe2disp_data_wr <= 1'b0;
exe2disp_valid_wr <= 1'b0;
polling_cpuid <= 6'b0;
exe_state <= IDLE_S;
end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
rule_fifo_rd_dly <= 1'b0;
end
else begin
rule_fifo_rd_dly <= rule_fifo_rd;
end
end
//***************************************************
// Other IP Instance
//***************************************************
//likely fifo/ram/async block....
//should be instantiated below here
fifo_256_134 exe_dfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(parser2exe_data_wr),
.data(parser2exe_data),
.rdreq(exe_dfifo_rd),
.q(exe_dfifo_rdata),
.usedw(exe_dfifo_usedw)
);
rulefifo_64_32 rule_fifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(lookup2exe_rule_wr),
.data(lookup2exe_rule),
.rdreq(rule_fifo_rd_dly),
.q(rule_fifo_rdata),
.empty(rule_fifo_empty)
);
endmodule |
module dispatch(
input clk,
input rst_n,
//execute module's pkt waiting for transmit
input exe2disp_data_wr,
input [133:0] exe2disp_data,
input exe2disp_valid_wr,
input exe2disp_valid,
output reg disp2exe_alf,
//execute's tranmit direction request
input exe2disp_direction_req,
input exe2disp_direction,//0:up cpu 1: down port
//transmit to up cpu
output reg disp2up_data_wr,
output [133:0] disp2up_data,
output reg disp2up_valid_wr,
output disp2up_valid,
input up2disp_alf,
//transmit to down port
output reg disp2down_data_wr,
output [133:0] disp2down_data,
output reg disp2down_valid_wr,
output disp2down_valid,
input down2disp_alf
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
reg [133:0] data_buff;
//only 1 stream path would be select at a time,so no need 2 set data registers
reg [1:0] disp_state;
//***************************************************
// Transmit Judge
//***************************************************
assign disp2up_data = data_buff;
assign disp2down_data = data_buff;
assign disp2up_valid = disp2up_valid_wr;
assign disp2down_valid = disp2down_valid_wr;
//receive controll ,ctrl by disp2exe_alf
//if set to 1,execute must not send pkt to dispatch
always @ * begin
if(exe2disp_direction_req == 1'b1) begin
if(exe2disp_direction == 1'b0) begin//request send to up cpu
disp2exe_alf = up2disp_alf;
end
else begin//request send to down port
disp2exe_alf = down2disp_alf;
end
end
else begin
disp2exe_alf = 1'b1;//don't permit execute send pkt
end
end
//pkt data transmit
localparam IDLE_S = 2'd0,
TRANS_UP_S = 2'd1,
TRANS_DOWN_S = 2'd2;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
disp2up_data_wr <= 1'b0;
disp2up_valid_wr <= 1'b0;
disp2down_data_wr <= 1'b0;
disp2down_valid_wr <= 1'b0;
disp_state <= IDLE_S;
end
else begin
case(disp_state)
IDLE_S: begin
if(exe2disp_data_wr == 1'b1) begin//trans start
data_buff <= exe2disp_data;
if(exe2disp_direction == 1'b0) begin//request send to up cpu
disp2up_data_wr <= exe2disp_data_wr;
disp2up_valid_wr <= exe2disp_valid_wr;
disp2down_data_wr <= 1'b0;
disp2down_valid_wr <= 1'b0;
disp_state <= TRANS_UP_S;
end
else begin//request send to down port
disp2up_data_wr <= 1'b0;
disp2up_valid_wr <= 1'b0;
disp2down_data_wr <= exe2disp_data_wr;
disp2down_valid_wr <= exe2disp_valid_wr;
disp_state <= TRANS_DOWN_S;
end
end
else begin
disp2up_data_wr <= 1'b0;
disp2up_valid_wr <= 1'b0;
disp2down_data_wr <= 1'b0;
disp2down_valid_wr <= 1'b0;
disp_state <= IDLE_S;
end
end
TRANS_UP_S: begin
data_buff <= exe2disp_data;
disp2up_data_wr <= exe2disp_data_wr;
disp2up_valid_wr <= exe2disp_valid_wr;
if(exe2disp_valid_wr == 1'b1) begin//trans end
disp_state <= IDLE_S;
end
else begin
disp_state <= TRANS_UP_S;
end
end
TRANS_DOWN_S: begin
data_buff <= exe2disp_data;
disp2down_data_wr <= exe2disp_data_wr;
disp2down_valid_wr <= exe2disp_valid_wr;
if(exe2disp_valid_wr == 1'b1) begin//trans end
disp_state <= IDLE_S;
end
else begin
disp_state <= TRANS_DOWN_S;
end
end
default: begin
disp2up_data_wr <= 1'b0;
disp2up_valid_wr <= 1'b0;
disp2down_data_wr <= 1'b0;
disp2down_valid_wr <= 1'b0;
disp_state <= IDLE_S;
end
endcase
end
end
endmodule |
module parser(
input clk,
input rst_n,
//input pkt from port
input port2parser_data_wr,
input [133:0] port2parser_data,
input port2parser_valid_wr,
input port2parser_valid,
output parser2port_alf,
//parse key which transmit to lookup
output reg parser2lookup_key_wr,
output [287:0] parser2lookup_key,
//transport to next module
output parser2next_data_wr,
output [133:0] parser2next_data,
input next2parser_alf
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
reg [7:0] pkt_step_count,pkt_step_count_inc;
reg [7:0] INPORT;
reg [47:0] DMAC;
reg [47:0] SMAC;
reg [15:0] ETH_TYPE;
reg [7:0] IP_PROTO;
reg [31:0] SIP;
reg [31:0] DIP;
reg [15:0] SPORT;
reg [15:0] DPORT;
wire is_ipv4;
wire is_tcp;
wire is_udp;
//***************************************************
// Retransmit Pkt
//***************************************************
assign parser2next_data_wr = port2parser_data_wr;
assign parser2next_data = port2parser_data;
assign parser2port_alf = next2parser_alf;
//***************************************************
// Pkt Step Count
//***************************************************
//count the pkt cycle step for locate parse procotol field
//compare with pkt_step_count, pkt_step count_inc always change advance 1 cycle
always @* begin
if(port2parser_data_wr == 1'b1) begin//a pkt is receiving
if(port2parser_data[133:132] == 2'b01) begin//pkt head
pkt_step_count_inc = 8'b0;
end
else begin
pkt_step_count_inc = pkt_step_count + 8'd1;
end
end
else begin
pkt_step_count_inc = pkt_step_count;
end
end
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
pkt_step_count <= 8'b0;
end
else begin
pkt_step_count <= pkt_step_count_inc;
end
end
//***************************************************
// Key Field Parse
//***************************************************
//------INPORT/DMAC/SMAC/ETH_TYPE Field Parse----------
always @(posedge clk) begin
if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd0)) begin
INPORT <= {5'b0,port2parser_data[110],port2parser_data[59:58]};//slot id + inport number
end
else begin
INPORT <= INPORT;
end
end
//------DMAC/SMAC/ETH_TYPE Field Parse----------
always @(posedge clk) begin
if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd2)) begin//eth head
DMAC <= port2parser_data[127:80];
SMAC <= port2parser_data[79:32];
ETH_TYPE <= port2parser_data[31:16];
end
else begin
DMAC <= DMAC;
SMAC <= SMAC;
ETH_TYPE <= ETH_TYPE;
end
end
assign is_ipv4 = (ETH_TYPE == 16'h0800);
//------IP_PROTO/SIP/DIP Field Parse----------
always @(posedge clk) begin
if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd3)) begin
//second pkt line, ip head
IP_PROTO <= port2parser_data[71:64];
SIP <= port2parser_data[47:16];
DIP[31:16] <= port2parser_data[15:0];
end
else if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd4)) begin
//third pkt line, destination ip last 4 byte
DIP[15:0] <= port2parser_data[127:112];//parse DIP's last 4 byte
end
else begin
IP_PROTO <= IP_PROTO;
SIP <= SIP;
DIP <= DIP;
end
end
assign is_tcp = (is_ipv4) && (IP_PROTO == 16'h6);
assign is_udp = (is_ipv4) && (IP_PROTO == 16'h11);
//------SPORT/DPORT Field Parse----------
always @(posedge clk) begin
if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd4)) begin
SPORT <= port2parser_data[111:96];
DPORT <= port2parser_data[95:80];
end
else begin
SPORT <= SPORT;
DPORT <= DPORT;
end
end
//***************************************************
// Key Field Wrapper
//***************************************************
assign parser2lookup_key[287:240] = SMAC;
assign parser2lookup_key[239:192] = DMAC;
assign parser2lookup_key[191:176] = ETH_TYPE;
assign parser2lookup_key[175:144] = (is_ipv4) ? SIP : 32'hffff_ffff;
assign parser2lookup_key[143:112] = (is_ipv4) ? DIP : 32'hffff_ffff;
assign parser2lookup_key[111:104] = (is_ipv4) ? IP_PROTO : 8'hff;
assign parser2lookup_key[103:88] = (is_tcp || is_udp) ? SPORT : 16'hffff;
assign parser2lookup_key[87:72] = (is_tcp || is_udp) ? DPORT : 16'hffff;
assign parser2lookup_key[71:64] = INPORT;
assign parser2lookup_key[63:0] = 64'hffff_ffff_ffff_ffff;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
parser2lookup_key_wr <= 1'b0;
end
else begin
if(port2parser_valid_wr == 1'b1) begin
//send key at last cycle of pkt
parser2lookup_key_wr <= 1'b1;
end
else begin
parser2lookup_key_wr <= 1'b0;
end
end
end
endmodule |
module rule_access(
input clk,
input rst_n,
//lookup rule read index
input lookup2rule_index_wr,
input [15:0] lookup2rule_index,
output rule2lookup_data_wr,//index read return valid
output [31:0] rule2lookup_data,
//user cfg require
input cfg2rule_cs,//high active
output rule2cfg_ack,//high active ,handshake with cfg2rule_cs
input cfg2rule_rw,//0:read 1:write
input [15:0] cfg2rule_addr,
input [31:0] cfg2rule_wdata,
output [31:0] rule2cfg_rdata
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
reg index_fifo_rd;
wire [15:0] index_fifo_rdata;
wire index_fifo_empty;
wire rule_ram_wr;
wire rule_ram_rd;
wire [7:0] rule_ram_waddr;
reg [7:0] rule_ram_raddr;
wire [31:0] rule_ram_wdata;
wire [31:0] rule_ram_rdata;
reg lookup_ram_rd,cfg_ram_rd;
reg cfg2rule_rack;
wire cfg2rule_wack;
wire sync_cfg2rule_cs;
wire cfg_read_req,cfg_write_req;
//***************************************************
// Rule Access Judge
//***************************************************
sync_sig #(2)sync_cfgcs(
//sync the cfg2rule_cs signal from cfg_clk to clk
.clk(clk),
.rst_n(rst_n),
.in_sig(cfg2rule_cs),
.out_sig(sync_cfg2rule_cs)
);
assign cfg_read_req = (sync_cfg2rule_cs == 1'b1) && (cfg2rule_rw == 1'b0);
assign cfg_write_req = (sync_cfg2rule_cs == 1'b1) && (cfg2rule_rw == 1'b1);
assign rule2cfg_ack = cfg2rule_rack || cfg2rule_wack;
//*******************
// Write Access
//*******************
assign rule_ram_waddr = cfg2rule_addr[7:0];
assign rule_ram_wdata = cfg2rule_wdata;
reg cfg_write_req_dly;
always @(posedge clk) begin
cfg_write_req_dly <= cfg_write_req;
end
assign rule_ram_wr = cfg_write_req && (~cfg_write_req_dly);
//just use cfg_write_req's posedge as rule_ram_wr
assign cfg2rule_wack = cfg_write_req;
//*******************
// Read Access
//*******************
assign rule2cfg_rdata = rule_ram_rdata;
assign rule2lookup_data = rule_ram_rdata;
assign rule_ram_rd = lookup_ram_rd || cfg_ram_rd;
reg [1:0] lookup_read_dly;
always @(posedge clk) begin
lookup_read_dly[0] <= lookup_ram_rd;
lookup_read_dly[1] <= lookup_read_dly[0];
end
//ram read return have 2 cycle delay
assign rule2lookup_data_wr = lookup_read_dly[1];
reg [1:0] cfg_read_dly;
wire cfg_read_valid;
always @(posedge clk) begin
cfg_read_dly[0] <= cfg_ram_rd;
cfg_read_dly[1] <= cfg_read_dly[0];
end
//ram read return have 2 cycle delay
assign cfg_read_valid = cfg_read_dly[1];
reg [1:0] read_state;
localparam R_IDLE_S = 2'd0,
R_LOOKUP_S = 2'd1,
R_CFGWAIT_S = 2'd2,
R_HANDSHAKE_S = 2'd3;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
lookup_ram_rd <= 1'b0;
cfg_ram_rd <= 1'b0;
cfg2rule_rack <= 1'b0;
index_fifo_rd <= 1'b0;
read_state <= R_IDLE_S;
end
else begin
case(read_state)
R_IDLE_S: begin
lookup_ram_rd <= 1'b0;
cfg_ram_rd <= 1'b0;
cfg2rule_rack <= 1'b0;
index_fifo_rd <= 1'b0;
if(cfg_read_req == 1'b1) begin//cfg read grant first
cfg_ram_rd <= 1'b1;
rule_ram_raddr <= cfg2rule_addr[7:0];
read_state <= R_CFGWAIT_S;
end
else if(index_fifo_empty == 1'b0) begin//lookup read require
index_fifo_rd <= 1'b1;
read_state <= R_LOOKUP_S;
end
else begin
read_state <= R_IDLE_S;
end
end
R_LOOKUP_S: begin
index_fifo_rd <= 1'b0;
lookup_ram_rd <= 1'b1;
rule_ram_raddr <= index_fifo_rdata[7:0];
read_state <= R_IDLE_S;
end
R_CFGWAIT_S: begin
cfg_ram_rd <= 1'b0;
if(cfg_read_valid == 1'b1) begin
cfg2rule_rack <= 1'b1;
read_state <= R_HANDSHAKE_S;
end
else begin
cfg2rule_rack <= 1'b0;
read_state <= R_CFGWAIT_S;
end
end
R_HANDSHAKE_S: begin
if(cfg_read_req == 1'b1) begin//cfg req is holding
cfg2rule_rack <= 1'b1;
read_state <= R_HANDSHAKE_S;
end
else begin//cfg req is release
cfg2rule_rack <= 1'b0;
read_state <= R_IDLE_S;
end
end
default: begin
lookup_ram_rd <= 1'b0;
cfg_ram_rd <= 1'b0;
cfg2rule_rack <= 1'b0;
index_fifo_rd <= 1'b0;
read_state <= R_IDLE_S;
end
endcase
end
end
//***************************************************
// Other IP Instance
//***************************************************
//likely fifo/ram/async block....
//should be instantiated below here
fifo_64_16 index_fifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(lookup2rule_index_wr),
.data(lookup2rule_index),
.rdreq(index_fifo_rd),
.q(index_fifo_rdata),
.empty(index_fifo_empty)
);
ram_32_256 rule_ram(
.aclr(~rst_n),
.clock(clk),
.wraddress(rule_ram_waddr),
.rdaddress(rule_ram_raddr),
.data(rule_ram_wdata),
.rden(rule_ram_rd),
.wren(rule_ram_wr),
.q(rule_ram_rdata)
);
endmodule |
module sync_sig(
input clk,
input rst_n,
input in_sig,
output out_sig
);
parameter SHIFT_WIDTH = 2;
reg[SHIFT_WIDTH-1:0] sig_dly;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
sig_dly <= {SHIFT_WIDTH{1'b0}};
end
else begin//Sync signal
sig_dly[0] <= in_sig;
sig_dly[SHIFT_WIDTH-1:1] <= sig_dly[SHIFT_WIDTH-2:0];
end
end
assign out_sig = &sig_dly;
endmodule |
module user_mux(
input clk,
input rst_n,
//lookup pkt waiting for transmit
input disp2usermux_data_wr,
input [133:0] disp2usermux_data,
input disp2usermux_valid_wr,
input disp2usermux_valid,
output usermux2disp_alf,
//up cpu pkt waiting for transmit
input up2usermux_data_wr,
input [133:0] up2usermux_data,
input up2usermux_valid_wr,
input up2usermux_valid,
output usermux2up_alf,
//transmit to down port
output reg usermux2down_data_wr,
output reg [133:0] usermux2down_data,
output reg usermux2down_valid_wr,
output usermux2down_valid,
input down2usermux_alf
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
reg up_dfifo_rd;
wire [133:0] up_dfifo_rdata;
wire [7:0] up_dfifo_usedw;
reg up_vfifo_rd;
wire up_vfifo_rdata;
wire up_vfifo_empty;
reg disp_dfifo_rd;
wire [133:0] disp_dfifo_rdata;
wire [7:0] disp_dfifo_usedw;
reg disp_vfifo_rd;
wire disp_vfifo_rdata;
wire disp_vfifo_empty;
reg last_select;//which direction last pkt select
// 0:send up cpu's pkt 1: send dispute's pkt
reg grant_bit;//current pkt direction selecct
reg has_pkt;
reg [1:0] usermux_state;
//***************************************************
// Stream Judge
//***************************************************
always @ * begin
case({disp_vfifo_empty,up_vfifo_empty})
2'b00: begin has_pkt = 1'b1; grant_bit = ~last_select; end//both direction have pkt,so select different with last
2'b01: begin has_pkt = 1'b1; grant_bit = 1'b1; end//just dispcute have pkt need to sending
2'b10: begin has_pkt = 1'b1; grant_bit = 1'b0; end//just up cpu have pkt need to sending
2'b11: begin has_pkt = 1'b0; grant_bit = last_select; end//both no pkt,hold last select
endcase
end
//***************************************************
// Stream Judge
//***************************************************
assign usermux2disp_alf = disp_dfifo_usedw[7];
assign usermux2up_alf = up_dfifo_usedw[7];
assign usermux2down_valid = usermux2down_valid_wr;
localparam IDLE_S = 2'd0,
SEND_EXE_S = 2'd1,
SEND_UP_S = 2'd2;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
last_select <= 1'b0;
usermux2down_data_wr <= 1'b0;
usermux2down_valid_wr <= 1'b0;
up_dfifo_rd <= 1'b0;
up_vfifo_rd <= 1'b0;
disp_dfifo_rd <= 1'b0;
disp_vfifo_rd <= 1'b0;
usermux_state <= IDLE_S;
end
else begin
case(usermux_state)
IDLE_S: begin
usermux2down_data_wr <= 1'b0;
usermux2down_valid_wr <= 1'b0;
if((down2usermux_alf == 1'b0) && (has_pkt == 1'b1)) begin
//there is at least a pkt ,& next module can receive a pkt
last_select <= grant_bit;
if(grant_bit == 1'b0) begin//send up cpu's pkt
up_dfifo_rd <= 1'b1;
up_vfifo_rd <= 1'b1;
disp_dfifo_rd <= 1'b0;
disp_vfifo_rd <= 1'b0;
usermux_state <= SEND_UP_S;
end
else begin
up_dfifo_rd <= 1'b0;
up_vfifo_rd <= 1'b0;
disp_dfifo_rd <= 1'b1;
disp_vfifo_rd <= 1'b1;
usermux_state <= SEND_EXE_S;
end
end
else begin
up_dfifo_rd <= 1'b0;
up_vfifo_rd <= 1'b0;
disp_dfifo_rd <= 1'b0;
disp_vfifo_rd <= 1'b0;
usermux_state <= IDLE_S;
end
end
SEND_UP_S:begin
up_vfifo_rd <= 1'b0;
usermux2down_data_wr <= 1'b1;
usermux2down_data <= up_dfifo_rdata;
if(up_dfifo_rdata[133:132] == 2'b10)begin//end of pkt
up_dfifo_rd <= 1'b0;
usermux2down_valid_wr <= 1'b1;
usermux_state <= IDLE_S;
end
else begin
up_dfifo_rd <= 1'b1;
usermux2down_valid_wr <= 1'b0;
usermux_state <= SEND_UP_S;
end
end
SEND_EXE_S:begin
disp_vfifo_rd <= 1'b0;
usermux2down_data_wr <= 1'b1;
usermux2down_data <= disp_dfifo_rdata;
if(disp_dfifo_rdata[133:132] == 2'b10)begin//end of pkt
disp_dfifo_rd <= 1'b0;
usermux2down_valid_wr <= 1'b1;
usermux_state <= IDLE_S;
end
else begin
disp_dfifo_rd <= 1'b1;
usermux2down_valid_wr <= 1'b0;
usermux_state <= SEND_EXE_S;
end
end
default: begin
last_select <= 1'b0;
usermux2down_data_wr <= 1'b0;
usermux2down_valid_wr <= 1'b0;
up_dfifo_rd <= 1'b0;
up_vfifo_rd <= 1'b0;
disp_dfifo_rd <= 1'b0;
disp_vfifo_rd <= 1'b0;
usermux_state <= IDLE_S;
end
endcase
end
end
//***************************************************
// Other IP Instance
//***************************************************
//likely fifo/ram/async block....
//should be instantiated below here
fifo_256_134 up_dfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(up2usermux_data_wr),
.data(up2usermux_data),
.rdreq(up_dfifo_rd),
.q(up_dfifo_rdata),
.usedw(up_dfifo_usedw)
);
fifo_64_1 up_vfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(up2usermux_valid_wr),
.data(up2usermux_valid),
.rdreq(up_vfifo_rd),
.q(up_vfifo_rdata),
.empty(up_vfifo_empty)
);
fifo_256_134 disp_dfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(disp2usermux_data_wr),
.data(disp2usermux_data),
.rdreq(disp_dfifo_rd),
.q(disp_dfifo_rdata),
.usedw(disp_dfifo_usedw)
);
fifo_64_1 disp_vfifo(
.aclr(~rst_n),
.clock(clk),
.wrreq(disp2usermux_valid_wr),
.data(disp2usermux_valid),
.rdreq(disp_vfifo_rd),
.q(disp_vfifo_rdata),
.empty(disp_vfifo_empty)
);
endmodule |
module asyn_128_93 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [92:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [92:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [92:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [92:0] q = sub_wire0[92:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 93,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule |
module ram_128_134 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input aclr;
input clock;
input [133:0] data;
input [6:0] rdaddress;
input rden;
input [6:0] wraddress;
input wren;
output [133:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire [133:0] q = sub_wire0[133:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({134{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 134,
altsyncram_component.width_b = 134,
altsyncram_component.width_byteena_a = 1;
endmodule |
module fifo_128_49 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [48:0] data;
input rdreq;
input wrreq;
output empty;
output [48:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [48:0] sub_wire1;
wire [7:0] sub_wire2;
wire empty = sub_wire0;
wire [48:0] q = sub_wire1[48:0];
wire [7:0] usedw = sub_wire2[7:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.usedw (sub_wire2),
.almost_empty (),
.almost_full (),
.full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 49,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_256_134 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [133:0] data;
input rdreq;
input wrreq;
output empty;
output [133:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [133:0] sub_wire1;
wire [7:0] sub_wire2;
wire empty = sub_wire0;
wire [133:0] q = sub_wire1[133:0];
wire [7:0] usedw = sub_wire2[7:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.usedw (sub_wire2),
.almost_empty (),
.almost_full (),
.full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 134,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module asyn_1024_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrusedw);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output rdempty;
output [10:0] rdusedw;
output [10:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire sub_wire1;
wire [10:0] sub_wire2;
wire [10:0] sub_wire3;
wire [133:0] q = sub_wire0[133:0];
wire rdempty = sub_wire1;
wire [10:0] rdusedw = sub_wire2[10:0];
wire [10:0] wrusedw = sub_wire3[10:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.wrusedw (sub_wire3),
.rdfull (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 2048,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 134,
dcfifo_component.lpm_widthu = 11,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule |
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