module
stringlengths 21
82.9k
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module ROM32X1(O, A0, A1, A2, A3, A4); // synthesis syn_black_box syn_resources="luts=2"
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 10;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg ea_int;
reg [4:0] addr01;
reg [7:0] data1, data2, data3;
wire ea;
wire [15:0] addr_rst;
wire [7:0] int_data0, int_data1, int_data2, int_data3, int_data4, int_data5, int_data6, int_data7, int_data8, int_data9, int_data10, int_data11, int_data12, int_data13, int_data14, int_data15, int_data16, int_data17, int_data18, int_data19, int_data20, int_data21, int_data22, int_data23, int_data24, int_data25, int_data26, int_data27, int_data28, int_data29, int_data30, int_data31;
assign ea = | addr[15:INT_ROM_WID];
assign addr_rst = rst ? 16'h0000 : addr;
rom0 rom_0 (.a(addr01), .o(int_data0));
rom1 rom_1 (.a(addr01), .o(int_data1));
rom2 rom_2 (.a(addr_rst[9:5]), .o(int_data2));
rom3 rom_3 (.a(addr_rst[9:5]), .o(int_data3));
rom4 rom_4 (.a(addr_rst[9:5]), .o(int_data4));
rom5 rom_5 (.a(addr_rst[9:5]), .o(int_data5));
rom6 rom_6 (.a(addr_rst[9:5]), .o(int_data6));
rom7 rom_7 (.a(addr_rst[9:5]), .o(int_data7));
rom8 rom_8 (.a(addr_rst[9:5]), .o(int_data8));
rom9 rom_9 (.a(addr_rst[9:5]), .o(int_data9));
rom10 rom_10 (.a(addr_rst[9:5]), .o(int_data10));
rom11 rom_11 (.a(addr_rst[9:5]), .o(int_data11));
rom12 rom_12 (.a(addr_rst[9:5]), .o(int_data12));
rom13 rom_13 (.a(addr_rst[9:5]), .o(int_data13));
rom14 rom_14 (.a(addr_rst[9:5]), .o(int_data14));
rom15 rom_15 (.a(addr_rst[9:5]), .o(int_data15));
rom16 rom_16 (.a(addr_rst[9:5]), .o(int_data16));
rom17 rom_17 (.a(addr_rst[9:5]), .o(int_data17));
rom18 rom_18 (.a(addr_rst[9:5]), .o(int_data18));
rom19 rom_19 (.a(addr_rst[9:5]), .o(int_data19));
rom20 rom_20 (.a(addr_rst[9:5]), .o(int_data20));
rom21 rom_21 (.a(addr_rst[9:5]), .o(int_data21));
rom22 rom_22 (.a(addr_rst[9:5]), .o(int_data22));
rom23 rom_23 (.a(addr_rst[9:5]), .o(int_data23));
rom24 rom_24 (.a(addr_rst[9:5]), .o(int_data24));
rom25 rom_25 (.a(addr_rst[9:5]), .o(int_data25));
rom26 rom_26 (.a(addr_rst[9:5]), .o(int_data26));
rom27 rom_27 (.a(addr_rst[9:5]), .o(int_data27));
rom28 rom_28 (.a(addr_rst[9:5]), .o(int_data28));
rom29 rom_29 (.a(addr_rst[9:5]), .o(int_data29));
rom30 rom_30 (.a(addr_rst[9:5]), .o(int_data30));
rom31 rom_31 (.a(addr_rst[9:5]), .o(int_data31));
always @(addr_rst)
begin
if (addr_rst[1])
addr01= addr_rst[9:5]+ 5'h1;
else
addr01= addr_rst[9:5];
end
//
// always read tree bits in row
always @(posedge clk)
begin
case(addr[4:0])
5'd0: begin
data1 <= #1 int_data0;
data2 <= #1 int_data1;
data3 <= #1 int_data2;
end
5'd1: begin
data1 <= #1 int_data1;
data2 <= #1 int_data2;
data3 <= #1 int_data3;
end
5'd2: begin
data1 <= #1 int_data2;
data2 <= #1 int_data3;
data3 <= #1 int_data4;
end
5'd3: begin
data1 <= #1 int_data3;
data2 <= #1 int_data4;
data3 <= #1 int_data5;
end
5'd4: begin
data1 <= #1 int_data4;
data2 <= #1 int_data5;
data3 <= #1 int_data6;
end
5'd5: begin
data1 <= #1 int_data5;
data2 <= #1 int_data6;
data3 <= #1 int_data7;
end
5'd6: begin
data1 <= #1 int_data6;
data2 <= #1 int_data7;
data3 <= #1 int_data8;
end
5'd7: begin
data1 <= #1 int_data7;
data2 <= #1 int_data8;
data3 <= #1 int_data9;
end
5'd8: begin
data1 <= #1 int_data8;
data2 <= #1 int_data9;
data3 <= #1 int_data10;
end
5'd9: begin
data1 <= #1 int_data9;
data2 <= #1 int_data10;
data3 <= #1 int_data11;
end
5'd10: begin
data1 <= #1 int_data10;
data2 <= #1 int_data11;
data3 <= #1 int_data12;
end
5'd11: begin
data1 <= #1 int_data11;
data2 <= #1 int_data12;
data3 <= #1 int_data13;
end
5'd12: begin
data1 <= #1 int_data12;
data2 <= #1 int_data13;
data3 <= #1 int_data14;
end
5'd13: begin
data1 <= #1 int_data13;
data2 <= #1 int_data14;
data3 <= #1 int_data15;
end
5'd14: begin
data1 <= #1 int_data14;
data2 <= #1 int_data15;
data3 <= #1 int_data16;
end
5'd15: begin
data1 <= #1 int_data15;
data2 <= #1 int_data16;
data3 <= #1 int_data17;
end
5'd16: begin
data1 <= #1 int_data16;
data2 <= #1 int_data17;
data3 <= #1 int_data18;
end
5'd17: begin
data1 <= #1 int_data17;
data2 <= #1 int_data18;
data3 <= #1 int_data19;
end
5'd18: begin
data1 <= #1 int_data18;
data2 <= #1 int_data19;
data3 <= #1 int_data20;
end
5'd19: begin
data1 <= #1 int_data19;
data2 <= #1 int_data20;
data3 <= #1 int_data21;
end
5'd20: begin
data1 <= #1 int_data20;
data2 <= #1 int_data21;
data3 <= #1 int_data22;
end
5'd21: begin
data1 <= #1 int_data21;
data2 <= #1 int_data22;
data3 <= #1 int_data23;
end
5'd22: begin
data1 <= #1 int_data22;
data2 <= #1 int_data23;
data3 <= #1 int_data24;
end
5'd23: begin
data1 <= #1 int_data23;
data2 <= #1 int_data24;
data3 <= #1 int_data25;
end
5'd24: begin
data1 <= #1 int_data24;
data2 <= #1 int_data25;
data3 <= #1 int_data26;
end
5'd25: begin
data1 <= #1 int_data25;
data2 <= #1 int_data26;
data3 <= #1 int_data27;
end
5'd26: begin
data1 <= #1 int_data26;
data2 <= #1 int_data27;
data3 <= #1 int_data28;
end
5'd27: begin
data1 <= #1 int_data27;
data2 <= #1 int_data28;
data3 <= #1 int_data29;
end
5'd28: begin
data1 <= #1 int_data28;
data2 <= #1 int_data29;
data3 <= #1 int_data30;
end
5'd29: begin
data1 <= #1 int_data29;
data2 <= #1 int_data30;
data3 <= #1 int_data31;
end
5'd30: begin
data1 <= #1 int_data30;
data2 <= #1 int_data31;
data3 <= #1 int_data0;
end
5'd31: begin
data1 <= #1 int_data31;
data2 <= #1 int_data0;
data3 <= #1 int_data1;
end
default: begin
data1 <= #1 8'h00;
data2 <= #1 8'h00;
data3 <= #1 8'h00;
end
endcase
end
always @(posedge clk or posedge rst)
if (rst)
ea_int <= #1 1'b1;
else ea_int <= #1 !ea;
endmodule |
module rom0 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00092dd0" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00143111" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000008d8" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00178438" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000203c4" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000880c0" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0008a0c0" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00032bc0" */;
endmodule |
module rom1 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00160931" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e0294" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00193938" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00180010" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00032148" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f1564" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f1d60" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000021f0" */;
endmodule |
module rom2 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0015a771" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0017b405" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c2601" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00040170" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002ff1" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f0e4d" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f2ec8" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00008d35" */;
endmodule |
module rom3 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00070d2c" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00012083" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00070f30" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00150014" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00128d75" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0017af31" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00078f70" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000224" */;
endmodule |
module rom4 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c12f0" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00031218" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f10c0" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d1020" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0010bf2c" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00179048" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00071d44" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00003f60" */;
endmodule |
module rom5 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001402a8" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0008309e" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00100224" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00081c08" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00101274" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00141278" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004126e" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000052e8" */;
endmodule |
module rom6 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001a7348" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00043c5e" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00042090" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f6b10" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0012624a" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001c6582" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c7084" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0003dbfc" */;
endmodule |
module rom7 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000007de" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000041e8" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d3662" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0008001c" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00039ef6" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001fee62" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fae62" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000039f4" */;
endmodule |
module rom8 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0012e844" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00022100" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00180014" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00190972" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000b616" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001fd99c" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001b469c" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002f02" */;
endmodule |
module rom9 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001a6068" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00124138" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e2048" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00120000" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00052c86" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f6808" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e7826" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002924" */;
endmodule |
module rom10 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c6b8a" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e4d10" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e1caa" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00162300" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000b9fa" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e5fda" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e5dca" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000be68" */;
endmodule |
module rom11 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001c3f3e" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00041601" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00052830" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0015002e" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000a899" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001ca8d1" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001cbcd0" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0001168e" */;
endmodule |
module rom12 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00020014" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002824c" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001b1500" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00080310" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0011bd18" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001dc32a" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00196920" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00027e14" */;
endmodule |
module rom13 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0010050a" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0010520c" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00150422" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00151cbc" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000082" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001d409a" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0015409a" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000024c" */;
endmodule |
module rom14 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004224a" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001c1b0e" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c0050" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c3a32" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001103d8" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001dbff0" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001c1e70" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000b86e" */;
endmodule |
module rom15 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00082ffa" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0014242a" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c0946" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0014048e" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000adc82" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000ec9c6" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000cd9e4" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00006166" */;
endmodule |
module rom16 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e8002" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0005a410" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c1622" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00092200" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002cbf2" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000ee75e" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c4fce" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00012d60" */;
endmodule |
module rom17 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000545a" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000a746c" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00010122" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000022" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00034150" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b4010" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00095524" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000034c2" */;
endmodule |
module rom18 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e698a" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00026342" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c5d0e" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00052942" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002fcce" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000bea7a" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000968e8" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00009cca" */;
endmodule |
module rom19 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0001ae6a" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c0031" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00020e22" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000484a8" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b1ffb" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b9ef7" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00088a86" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000108" */;
endmodule |
module rom20 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00060870" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001158" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00022024" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00042816" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002eeec" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0006b4fc" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004e630" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00004a12" */;
endmodule |
module rom21 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00095118" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00027910" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f250c" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d0900" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000242bc" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00064548" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004506a" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000114b0" */;
endmodule |
module rom22 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002091a" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000a2190" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00071002" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c8e18" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0003d34a" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0007ea46" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00054246" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00009908" */;
endmodule |
module rom23 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000cb8cc" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00080d84" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d25e8" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b81a8" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000223ee" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fb7fc" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000db572" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000d02" */;
endmodule |
module rom24 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fe720" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c0830" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004812c" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00020a2a" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0003066c" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f8f28" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c9368" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000069e0" */;
endmodule |
module rom25 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00063490" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002820" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00007498" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00080042" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00082332" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e5136" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00065316" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001d10" */;
endmodule |
module rom26 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00011a54" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00033a0c" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00040740" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00058834" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000869ba" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000eca2e" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00065f20" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00019690" */;
endmodule |
module rom27 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b040a" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00030091" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0008d40e" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00004008" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00099577" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fc77b" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0003c74a" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001548" */;
endmodule |
module rom28 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000da040" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00053290" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002bb40" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000880a" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00080ca8" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fac4e" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00078ddc" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000057a" */;
endmodule |
module rom29 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00078b24" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000de308" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f880c" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d8414" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00083156" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f8040" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00079240" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000043da" */;
endmodule |
module rom30 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00042152" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00030f00" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0007c756" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00050120" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000b1e" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0007dd5a" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0007d53a" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001728" */;
endmodule |
module rom31 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e0408" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001140" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e20a0" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e1200" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00004c18" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000475ac" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000450b4" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000038f2" */;
endmodule |
module oc8051_sfr (rst, clk,
adr0, adr1, dat0,
dat1, dat2, bit_in,
des_acc,
we, wr_bit,
bit_out,
wr_sfr, acc,
ram_wr_sel, ram_rd_sel,
sp, sp_w,
bank_sel,
desAc, desOv,
srcAc, cy,
psw_set, rmw,
comp_sel,
comp_wait,
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
p0_out,
p0_in,
`endif
`ifdef OC8051_PORT1
p1_out,
p1_in,
`endif
`ifdef OC8051_PORT2
p2_out,
p2_in,
`endif
`ifdef OC8051_PORT3
p3_out,
p3_in,
`endif
`endif
`ifdef OC8051_UART
rxd, txd,
`endif
int_ack, intr,
int0, int1,
int_src,
reti,
`ifdef OC8051_TC01
t0, t1,
`endif
`ifdef OC8051_TC2
t2, t2ex,
`endif
dptr_hi, dptr_lo,
wait_data);
input rst, // reset - pin
clk, // clock - pin
we, // write enable
bit_in,
desAc,
desOv,
rmw;
input int_ack,
int0,
int1,
reti,
wr_bit;
input [1:0] psw_set,
wr_sfr,
comp_sel;
input [2:0] ram_rd_sel,
ram_wr_sel;
input [7:0] adr0, //address 0 input
adr1, //address 1 input
des_acc,
dat1, //data 1 input (des1)
dat2; //data 2 input (des2)
output bit_out,
intr,
srcAc,
cy,
wait_data,
comp_wait;
output [1:0] bank_sel;
output [7:0] dat0, //data output
int_src,
dptr_hi,
dptr_lo,
acc;
output [7:0] sp,
sp_w;
// ports
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
input [7:0] p0_in;
output [7:0] p0_out;
wire [7:0] p0_data;
`endif
`ifdef OC8051_PORT1
input [7:0] p1_in;
output [7:0] p1_out;
wire [7:0] p1_data;
`endif
`ifdef OC8051_PORT2
input [7:0] p2_in;
output [7:0] p2_out;
wire [7:0] p2_data;
`endif
`ifdef OC8051_PORT3
input [7:0] p3_in;
output [7:0] p3_out;
wire [7:0] p3_data;
`endif
`endif
// serial interface
`ifdef OC8051_UART
input rxd;
output txd;
`endif
// timer/counter 0,1
`ifdef OC8051_TC01
input t0, t1;
`endif
// timer/counter 2
`ifdef OC8051_TC2
input t2, t2ex;
`endif
reg bit_out,
wait_data;
reg [7:0] dat0,
adr0_r;
reg wr_bit_r;
reg [2:0] ram_wr_sel_r;
wire p,
uart_int,
tf0,
tf1,
tr0,
tr1,
rclk,
tclk,
brate2,
tc2_int;
wire [7:0] b_reg,
psw,
`ifdef OC8051_TC2
// t/c 2
t2con,
tl2,
th2,
rcap2l,
rcap2h,
`endif
`ifdef OC8051_TC01
// t/c 0,1
tmod,
tl0,
th0,
tl1,
th1,
`endif
// serial interface
`ifdef OC8051_UART
scon,
pcon,
sbuf,
`endif
//interrupt control
ie,
tcon,
ip;
reg pres_ow;
reg [3:0] prescaler;
assign cy = psw[7];
assign srcAc = psw [6];
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(des_acc),
.data2_in(dat2),
.wr(we),
.wr_bit(wr_bit_r),
.wr_sfr(wr_sfr),
.wr_addr(adr1),
.data_out(acc),
.p(p));
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(des_acc),
.wr(we),
.wr_bit(wr_bit_r),
.wr_addr(adr1),
.data_out(b_reg));
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk),
.rst(rst),
.ram_rd_sel(ram_rd_sel),
.ram_wr_sel(ram_wr_sel),
.wr_addr(adr1),
.wr(we),
.wr_bit(wr_bit_r),
.data_in(dat1),
.sp_out(sp),
.sp_w(sp_w));
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk),
.rst(rst),
.addr(adr1),
.data_in(des_acc),
.data2_in(dat2),
.wr(we),
.wr_bit(wr_bit_r),
.data_hi(dptr_hi),
.data_lo(dptr_lo),
.wr_sfr(wr_sfr));
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk),
.rst(rst),
.wr_addr(adr1),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.data_out(psw),
.p(p),
.cy_in(bit_in),
.ac_in(desAc),
.ov_in(desOv),
.set(psw_set),
.bank_sel(bank_sel));
//
// ports
// P0, P1, P2, P3
`ifdef OC8051_PORTS
oc8051_ports oc8051_ports1(.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.wr_addr(adr1),
`ifdef OC8051_PORT0
.p0_out(p0_out),
.p0_in(p0_in),
.p0_data(p0_data),
`endif
`ifdef OC8051_PORT1
.p1_out(p1_out),
.p1_in(p1_in),
.p1_data(p1_data),
`endif
`ifdef OC8051_PORT2
.p2_out(p2_out),
.p2_in(p2_in),
.p2_data(p2_data),
`endif
`ifdef OC8051_PORT3
.p3_out(p3_out),
.p3_in(p3_in),
.p3_data(p3_data),
`endif
.rmw(rmw));
`endif
//
// serial interface
// SCON, SBUF
`ifdef OC8051_UART
oc8051_uart oc8051_uatr1 (.clk(clk),
.rst(rst),
.bit_in(bit_in),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.wr_addr(adr1),
.rxd(rxd),
.txd(txd),
// interrupt
.intr(uart_int),
// baud rate sources
.brate2(brate2),
.t1_ow(tf1),
.pres_ow(pres_ow),
.rclk(rclk),
.tclk(tclk),
//registers
.scon(scon),
.pcon(pcon),
.sbuf(sbuf));
`else
assign uart_int = 1'b0;
`endif
//
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk),
.rst(rst),
.wr_addr(adr1),
.bit_in(bit_in),
.ack(int_ack),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.tf0(tf0),
.tf1(tf1),
.t2_int(tc2_int),
.tr0(tr0),
.tr1(tr1),
.ie0(int0),
.ie1(int1),
.uart_int(uart_int),
.reti(reti),
.intr(intr),
.int_vec(int_src),
.ie(ie),
.tcon(tcon),
.ip(ip));
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
`ifdef OC8051_TC01
oc8051_tc oc8051_tc1(.clk(clk),
.rst(rst),
.wr_addr(adr1),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.ie0(int0),
.ie1(int1),
.tr0(tr0),
.tr1(tr1),
.t0(t0),
.t1(t1),
.tf0(tf0),
.tf1(tf1),
.pres_ow(pres_ow),
.tmod(tmod),
.tl0(tl0),
.th0(th0),
.tl1(tl1),
.th1(th1));
`else
assign tf0 = 1'b0;
assign tf1 = 1'b0;
`endif
//
// timer/counter 2
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
`ifdef OC8051_TC2
oc8051_tc2 oc8051_tc21(.clk(clk),
.rst(rst),
.wr_addr(adr1),
.data_in(dat1),
.wr(we),
.wr_bit(wr_bit_r),
.bit_in(bit_in),
.t2(t2),
.t2ex(t2ex),
.rclk(rclk),
.tclk(tclk),
.brate2(brate2),
.tc2_int(tc2_int),
.pres_ow(pres_ow),
.t2con(t2con),
.tl2(tl2),
.th2(th2),
.rcap2l(rcap2l),
.rcap2h(rcap2h));
`else
assign tc2_int = 1'b0;
assign rclk = 1'b0;
assign tclk = 1'b0;
assign brate2 = 1'b0;
`endif
always @(posedge clk or posedge rst)
if (rst) begin
adr0_r <= #1 8'h00;
ram_wr_sel_r <= #1 3'b000;
wr_bit_r <= #1 1'b0;
// wait_data <= #1 1'b0;
end else begin
adr0_r <= #1 adr0;
ram_wr_sel_r <= #1 ram_wr_sel;
wr_bit_r <= #1 wr_bit;
end
assign comp_wait = !(
((comp_sel==`OC8051_CSS_AZ) &
((wr_sfr==`OC8051_WRS_ACC1) |
(wr_sfr==`OC8051_WRS_ACC2) |
((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r) |
((adr1[7:3]==`OC8051_SFR_B_ACC) & we & wr_bit_r))) |
((comp_sel==`OC8051_CSS_CY) &
((|psw_set) |
((adr1==`OC8051_SFR_PSW) & we & !wr_bit_r) |
((adr1[7:3]==`OC8051_SFR_B_PSW) & we & wr_bit_r))) |
((comp_sel==`OC8051_CSS_BIT) &
((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
((adr1==adr0) & adr1[7] & we & !wr_bit_r)));
//
//set output in case of address (byte)
always @(posedge clk or posedge rst)
begin
if (rst) begin
dat0 <= #1 8'h00;
wait_data <= #1 1'b0;
end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
dat0 <= #1 des_acc;
wait_data <= #1 1'b0;
end else if (
(
((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
// ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
(adr1[7] & (adr1==adr0) & we & !wr_bit_r) | //write and read same address
(adr1[7] & (adr1[7:3]==adr0[7:3]) & (~&adr0[2:0]) & we & wr_bit_r) //write bit addressable to read address
) & !wait_data) begin
wait_data <= #1 1'b1;
end else if ((
((|psw_set) & (adr0==`OC8051_SFR_PSW)) |
((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
) & !wait_data) begin
wait_data <= #1 1'b1;
end else begin
case (adr0) /* synopsys full_case parallel_case */
`OC8051_SFR_ACC: dat0 <= #1 acc;
`OC8051_SFR_PSW: dat0 <= #1 psw;
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
`OC8051_SFR_P0: dat0 <= #1 p0_data;
`endif
`ifdef OC8051_PORT1
`OC8051_SFR_P1: dat0 <= #1 p1_data;
`endif
`ifdef OC8051_PORT2
`OC8051_SFR_P2: dat0 <= #1 p2_data;
`endif
`ifdef OC8051_PORT3
`OC8051_SFR_P3: dat0 <= #1 p3_data;
`endif
`endif
`OC8051_SFR_SP: dat0 <= #1 sp;
`OC8051_SFR_B: dat0 <= #1 b_reg;
`OC8051_SFR_DPTR_HI: dat0 <= #1 dptr_hi;
`OC8051_SFR_DPTR_LO: dat0 <= #1 dptr_lo;
`ifdef OC8051_UART
`OC8051_SFR_SCON: dat0 <= #1 scon;
`OC8051_SFR_SBUF: dat0 <= #1 sbuf;
`OC8051_SFR_PCON: dat0 <= #1 pcon;
`endif
`ifdef OC8051_TC01
`OC8051_SFR_TH0: dat0 <= #1 th0;
`OC8051_SFR_TH1: dat0 <= #1 th1;
`OC8051_SFR_TL0: dat0 <= #1 tl0;
`OC8051_SFR_TL1: dat0 <= #1 tl1;
`OC8051_SFR_TMOD: dat0 <= #1 tmod;
`endif
`OC8051_SFR_IP: dat0 <= #1 ip;
`OC8051_SFR_IE: dat0 <= #1 ie;
`OC8051_SFR_TCON: dat0 <= #1 tcon;
`ifdef OC8051_TC2
`OC8051_SFR_RCAP2H: dat0 <= #1 rcap2h;
`OC8051_SFR_RCAP2L: dat0 <= #1 rcap2l;
`OC8051_SFR_TH2: dat0 <= #1 th2;
`OC8051_SFR_TL2: dat0 <= #1 tl2;
`OC8051_SFR_T2CON: dat0 <= #1 t2con;
`endif
// default: dat0 <= #1 8'h00;
endcase
wait_data <= #1 1'b0;
end
end
//
//set output in case of address (bit)
always @(posedge clk or posedge rst)
begin
if (rst)
bit_out <= #1 1'h0;
else if (
((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) //write to acc
)
bit_out <= #1 dat1[adr0[2:0]];
else if ((adr1==adr0) & we & wr_bit_r)
bit_out <= #1 bit_in;
else
case (adr0[7:3]) /* synopsys full_case parallel_case */
`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
`OC8051_SFR_B_P0: bit_out <= #1 p0_data[adr0[2:0]];
`endif
`ifdef OC8051_PORT1
`OC8051_SFR_B_P1: bit_out <= #1 p1_data[adr0[2:0]];
`endif
`ifdef OC8051_PORT2
`OC8051_SFR_B_P2: bit_out <= #1 p2_data[adr0[2:0]];
`endif
`ifdef OC8051_PORT3
`OC8051_SFR_B_P3: bit_out <= #1 p3_data[adr0[2:0]];
`endif
`endif
`OC8051_SFR_B_B: bit_out <= #1 b_reg[adr0[2:0]];
`OC8051_SFR_B_IP: bit_out <= #1 ip[adr0[2:0]];
`OC8051_SFR_B_IE: bit_out <= #1 ie[adr0[2:0]];
`OC8051_SFR_B_TCON: bit_out <= #1 tcon[adr0[2:0]];
`ifdef OC8051_UART
`OC8051_SFR_B_SCON: bit_out <= #1 scon[adr0[2:0]];
`endif
`ifdef OC8051_TC2
`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
`endif
// default: bit_out <= #1 1'b0;
endcase
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
prescaler <= #1 4'h0;
pres_ow <= #1 1'b0;
end else if (prescaler==4'b1011) begin
prescaler <= #1 4'h0;
pres_ow <= #1 1'b1;
end else begin
prescaler <= #1 prescaler + 4'h1;
pres_ow <= #1 1'b0;
end
end
endmodule |
module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in,
des1, des2, des_acc, desCy, desAc, desOv, sub_result);
//
// op_code (in) operation code [oc8051_decoder.alu_op -r]
// src1 (in) first operand [oc8051_alu_src1_sel.des]
// src2 (in) second operand [oc8051_alu_src2_sel.des]
// src3 (in) third operand [oc8051_alu_src3_sel.des]
// srcCy (in) carry input [oc8051_cy_select.data_out]
// srcAc (in) auxiliary carry input [oc8051_psw.data_out[6] ]
// bit_in (in) bit input, used for logic operatins on bits [oc8051_ram_sel.bit_out]
// des1 (out)
// des2 (out)
// desCy (out) carry output [oc8051_ram_top.bit_data_in, oc8051_acc.bit_in, oc8051_b_register.bit_in, oc8051_psw.cy_in, oc8051_ports.bit_in]
// desAc (out) auxiliary carry output [oc8051_psw.ac_in]
// desOv (out) Overflow output [oc8051_psw.ov_in]
//
input srcCy, srcAc, bit_in, clk, rst;
input [3:0] op_code;
input [7:0] src1, src2, src3;
output desCy, desAc, desOv;
output [7:0] des1, des2, des_acc, sub_result;
reg desCy, desAc, desOv;
reg [7:0] des1, des2, des_acc;
//
//add
//
wire [4:0] add1, add2, add3, add4;
wire [3:0] add5, add6, add7, add8;
wire [1:0] add9, adda, addb, addc;
//
//sub
//
wire [4:0] sub1, sub2, sub3, sub4;
wire [3:0] sub5, sub6, sub7, sub8;
wire [1:0] sub9, suba, subb, subc;
wire [7:0] sub_result;
//
//mul
//
wire [7:0] mulsrc1, mulsrc2;
wire mulOv;
reg enable_mul;
//
//div
//
wire [7:0] divsrc1,divsrc2;
wire divOv;
reg enable_div;
//
//da
//
reg da_tmp, da_tmp1;
//reg [8:0] da1;
//
// inc
//
wire [15:0] inc, dec;
oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));
oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));
/* Add */
assign add1 = {1'b0,src1[3:0]};
assign add2 = {1'b0,src2[3:0]};
assign add3 = {3'b000,srcCy};
assign add4 = add1+add2+add3;
assign add5 = {1'b0,src1[6:4]};
assign add6 = {1'b0,src2[6:4]};
assign add7 = {1'b0,1'b0,1'b0,add4[4]};
assign add8 = add5+add6+add7;
assign add9 = {1'b0,src1[7]};
assign adda = {1'b0,src2[7]};
assign addb = {1'b0,add8[3]};
assign addc = add9+adda+addb;
/* Sub */
assign sub1 = {1'b1,src1[3:0]};
assign sub2 = {1'b0,src2[3:0]};
assign sub3 = {1'b0,1'b0,1'b0,srcCy};
assign sub4 = sub1-sub2-sub3;
assign sub5 = {1'b1,src1[6:4]};
assign sub6 = {1'b0,src2[6:4]};
assign sub7 = {1'b0,1'b0,1'b0, !sub4[4]};
assign sub8 = sub5-sub6-sub7;
assign sub9 = {1'b1,src1[7]};
assign suba = {1'b0,src2[7]};
assign subb = {1'b0,!sub8[3]};
assign subc = sub9-suba-subb;
assign sub_result = {subc[0],sub8[2:0],sub4[3:0]};
/* inc */
assign inc = {src2, src1} + {15'h0, 1'b1};
assign dec = {src2, src1} - {15'h0, 1'b1};
always @(op_code or src1 or src2 or srcCy or srcAc or bit_in or src3 or mulsrc1
or mulsrc2 or mulOv or divsrc1 or divsrc2 or divOv or addc or add8 or add4
or sub4 or sub8 or subc or da_tmp or inc or dec or sub_result)
begin
case (op_code) /* synopsys full_case parallel_case */
//operation add
`OC8051_ALU_ADD: begin
des_acc = {addc[0],add8[2:0],add4[3:0]};
des1 = src1;
des2 = src3+ {7'b0, addc[1]};
desCy = addc[1];
desAc = add4[4];
desOv = addc[1] ^ add8[3];
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation subtract
`OC8051_ALU_SUB: begin
des_acc = sub_result;
// des1 = sub_result;
des1 = 8'h00;
des2 = 8'h00;
desCy = !subc[1];
desAc = !sub4[4];
desOv = !subc[1] ^ !sub8[3];
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation multiply
`OC8051_ALU_MUL: begin
des_acc = mulsrc1;
des1 = src1;
des2 = mulsrc2;
desOv = mulOv;
desCy = 1'b0;
desAc = 1'b0;
enable_mul = 1'b1;
enable_div = 1'b0;
end
//operation divide
`OC8051_ALU_DIV: begin
des_acc = divsrc1;
des1 = src1;
des2 = divsrc2;
desOv = divOv;
desAc = 1'b0;
desCy = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b1;
end
//operation decimal adjustment
`OC8051_ALU_DA: begin
if (srcAc==1'b1 | src1[3:0]>4'b1001) {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]}+ 5'b00110;
else {da_tmp, des_acc[3:0]} = {1'b0, src1[3:0]};
if (srcCy | da_tmp | src1[7:4]>4'b1001)
{da_tmp1, des_acc[7:4]} = {srcCy, src1[7:4]}+ 5'b00110 + {4'b0, da_tmp};
else {da_tmp1, des_acc[7:4]} = {srcCy, src1[7:4]} + {4'b0, da_tmp};
desCy = da_tmp | da_tmp1;
des1 = src1;
des2 = 8'h00;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation not
// bit operation not
`OC8051_ALU_NOT: begin
des_acc = ~src1;
des1 = ~src1;
des2 = 8'h00;
desCy = !srcCy;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation and
//bit operation and
`OC8051_ALU_AND: begin
des_acc = src1 & src2;
des1 = src1 & src2;
des2 = 8'h00;
desCy = srcCy & bit_in;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation xor
// bit operation xor
`OC8051_ALU_XOR: begin
des_acc = src1 ^ src2;
des1 = src1 ^ src2;
des2 = 8'h00;
desCy = srcCy ^ bit_in;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation or
// bit operation or
`OC8051_ALU_OR: begin
des_acc = src1 | src2;
des1 = src1 | src2;
des2 = 8'h00;
desCy = srcCy | bit_in;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate left
// bit operation cy= cy or (not ram)
`OC8051_ALU_RL: begin
des_acc = {src1[6:0], src1[7]};
des1 = src1 ;
des2 = 8'h00;
desCy = srcCy | !bit_in;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate left with carry and swap nibbles
`OC8051_ALU_RLC: begin
des_acc = {src1[6:0], srcCy};
des1 = src1 ;
des2 = {src1[3:0], src1[7:4]};
desCy = src1[7];
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate right
`OC8051_ALU_RR: begin
des_acc = {src1[0], src1[7:1]};
des1 = src1 ;
des2 = 8'h00;
desCy = srcCy & !bit_in;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation rotate right with carry
`OC8051_ALU_RRC: begin
des_acc = {srcCy, src1[7:1]};
des1 = src1 ;
des2 = 8'h00;
desCy = src1[0];
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation pcs Add
`OC8051_ALU_INC: begin
if (srcCy) begin
des_acc = dec[7:0];
des1 = dec[7:0];
des2 = dec[15:8];
end else begin
des_acc = inc[7:0];
des1 = inc[7:0];
des2 = inc[15:8];
end
desCy = 1'b0;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
//operation exchange
//if carry = 0 exchange low order digit
`OC8051_ALU_XCH: begin
if (srcCy)
begin
des_acc = src2;
des1 = src2;
des2 = src1;
end else begin
des_acc = {src1[7:4],src2[3:0]};
des1 = {src1[7:4],src2[3:0]};
des2 = {src2[7:4],src1[3:0]};
end
desCy = 1'b0;
desAc = 1'b0;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
`OC8051_ALU_NOP: begin
des_acc = src1;
des1 = src1;
des2 = src2;
desCy = srcCy;
desAc = srcAc;
desOv = 1'b0;
enable_mul = 1'b0;
enable_div = 1'b0;
end
endcase
end
endmodule |
module oc8051_top (wb_rst_i, wb_clk_i,
//interface to instruction rom
wbi_adr_o,
wbi_dat_i,
wbi_stb_o,
wbi_ack_i,
wbi_cyc_o,
wbi_err_i,
//interface to data ram
wbd_dat_i,
wbd_dat_o,
wbd_adr_o,
wbd_we_o,
wbd_ack_i,
wbd_stb_o,
wbd_cyc_o,
wbd_err_i,
// interrupt interface
int0_i,
int1_i,
// port interface
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
p0_i,
p0_o,
`endif
`ifdef OC8051_PORT1
p1_i,
p1_o,
`endif
`ifdef OC8051_PORT2
p2_i,
p2_o,
`endif
`ifdef OC8051_PORT3
p3_i,
p3_o,
`endif
`endif
// serial interface
`ifdef OC8051_UART
rxd_i, txd_o,
`endif
// counter interface
`ifdef OC8051_TC01
t0_i, t1_i,
`endif
`ifdef OC8051_TC2
t2_i, t2ex_i,
`endif
// BIST
`ifdef OC8051_BIST
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en,
`endif
// external access (active low)
ea_in
);
input wb_rst_i, // reset input
wb_clk_i, // clock input
int0_i, // interrupt 0
int1_i, // interrupt 1
ea_in, // external access
wbd_ack_i, // data acknowalge
wbi_ack_i, // instruction acknowlage
wbd_err_i, // data error
wbi_err_i; // instruction error
input [7:0] wbd_dat_i; // ram data input
input [31:0] wbi_dat_i; // rom data input
output wbd_we_o, // data write enable
wbd_stb_o, // data strobe
wbd_cyc_o, // data cycle
wbi_stb_o, // instruction strobe
wbi_cyc_o; // instruction cycle
output [7:0] wbd_dat_o; // data output
output [15:0] wbd_adr_o, // data address
wbi_adr_o; // instruction address
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
input [7:0] p0_i; // port 0 input
output [7:0] p0_o; // port 0 output
`endif
`ifdef OC8051_PORT1
input [7:0] p1_i; // port 1 input
output [7:0] p1_o; // port 1 output
`endif
`ifdef OC8051_PORT2
input [7:0] p2_i; // port 2 input
output [7:0] p2_o; // port 2 output
`endif
`ifdef OC8051_PORT3
input [7:0] p3_i; // port 3 input
output [7:0] p3_o; // port 3 output
`endif
`endif
`ifdef OC8051_UART
input rxd_i; // receive
output txd_o; // transnmit
`endif
`ifdef OC8051_TC01
input t0_i, // counter 0 input
t1_i; // counter 1 input
`endif
`ifdef OC8051_TC2
input t2_i, // counter 2 input
t2ex_i; //
`endif
`ifdef OC8051_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
wire scanb_soi;
`endif
wire [7:0] dptr_hi,
dptr_lo,
ri,
data_out,
op1,
op2,
op3,
acc,
p0_out,
p1_out,
p2_out,
p3_out,
sp,
sp_w;
wire [31:0] idat_onchip;
wire [15:0] pc;
assign wbd_cyc_o = wbd_stb_o;
wire src_sel3;
wire [1:0] wr_sfr,
src_sel2;
wire [2:0] ram_rd_sel, // ram read
ram_wr_sel, // ram write
src_sel1;
wire [7:0] ram_data,
ram_out, //data from ram
sfr_out,
wr_dat,
wr_addr, //ram write addres
rd_addr; //data ram read addres
wire sfr_bit;
wire [1:0] cy_sel, //carry select; from decoder to cy_selct1
bank_sel;
wire rom_addr_sel, //rom addres select; alu or pc
rmw,
ea_int;
wire reti,
intr,
int_ack,
istb;
wire [7:0] int_src;
wire mem_wait;
wire [2:0] mem_act;
wire [3:0] alu_op; //alu operation (from decoder)
wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)
wire [7:0] src1, //alu sources 1
src2, //alu sources 2
src3, //alu sources 3
des_acc,
des1, //alu destination 1
des2; //alu destinations 2
wire desCy, //carry out
desAc,
desOv, //overflow
alu_cy,
wr, //write to data ram
wr_o;
wire rd, //read program rom
pc_wr;
wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)
wire [7:0] op1_n, //from memory_interface to decoder
op2_n,
op3_n;
wire [1:0] comp_sel; //select source1 and source2 to compare
wire eq, //result (from comp1 to decoder)
srcAc,
cy,
rd_ind,
wr_ind,
comp_wait;
wire [2:0] op1_cur;
wire bit_addr, //bit addresable instruction
bit_data, //bit data from ram to ram_select
bit_out, //bit data from ram_select to alu and cy_select
bit_addr_o,
wait_data;
//
// cpu to cache/wb_interface
wire iack_i,
istb_o,
icyc_o;
wire [31:0] idat_i;
wire [15:0] iadr_o;
//
// decoder
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),
.rst(wb_rst_i),
.op_in(op1_n),
.op1_c(op1_cur),
.ram_rd_sel_o(ram_rd_sel),
.ram_wr_sel_o(ram_wr_sel),
.bit_addr(bit_addr),
.src_sel1(src_sel1),
.src_sel2(src_sel2),
.src_sel3(src_sel3),
.alu_op_o(alu_op),
.psw_set(psw_set),
.cy_sel(cy_sel),
.wr_o(wr),
.pc_wr(pc_wr),
.pc_sel(pc_wr_sel),
.comp_sel(comp_sel),
.eq(eq),
.wr_sfr_o(wr_sfr),
.rd(rd),
.rmw(rmw),
.istb(istb),
.mem_act(mem_act),
.mem_wait(mem_wait),
.wait_data(wait_data));
wire [7:0] sub_result;
//
//alu
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
.clk(wb_clk_i),
.op_code(alu_op),
.src1(src1),
.src2(src2),
.src3(src3),
.srcCy(alu_cy),
.srcAc(srcAc),
.des_acc(des_acc),
.sub_result(sub_result),
.des1(des1),
.des2(des2),
.desCy(desCy),
.desAc(desAc),
.desOv(desOv),
.bit_in(bit_out));
//
//data ram
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),
.rst(wb_rst_i),
.rd_addr(rd_addr),
.rd_data(ram_data),
.wr_addr(wr_addr),
.bit_addr(bit_addr_o),
.wr_data(wr_dat),
.wr(wr_o && (!wr_addr[7] || wr_ind)),
.bit_data_in(desCy),
.bit_data_out(bit_data)
`ifdef OC8051_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_soi),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
`endif
);
//
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
.rst(wb_rst_i),
.rd(rd),
.sel1(src_sel1),
.sel2(src_sel2),
.sel3(src_sel3),
.acc(acc),
.ram(ram_out),
.pc(pc),
.dptr({dptr_hi, dptr_lo}),
.op1(op1_n),
.op2(op2_n),
.op3(op3_n),
.src1(src1),
.src2(src2),
.src3(src3));
//
//
oc8051_comp oc8051_comp1(.sel(comp_sel),
.eq(eq),
.b_in(bit_out),
.cy(cy),
.acc(acc),
.des(sub_result)
);
//
//program rom
`ifdef OC8051_ROM
oc8051_rom oc8051_rom1(.rst(wb_rst_i),
.clk(wb_clk_i),
.ea_int(ea_int),
.addr(iadr_o),
.data_o(idat_onchip)
);
`else
assign ea_int = 1'b0;
assign idat_onchip = 32'h0;
`ifdef OC8051_SIMULATION
initial
begin
$display("\t * ");
$display("\t * Internal rom disabled!!!");
$display("\t * ");
end
`endif
`endif
//
//
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
.cy_in(cy),
.data_in(bit_out),
.data_out(alu_cy));
//
//
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),
.rst(wb_rst_i),
.wr_addr(wr_addr),
.data_in(wr_dat),
.wr(wr_o),
.wr_bit(bit_addr_o),
.ri_out(ri),
.sel(op1_cur[0]),
.bank(bank_sel));
assign icyc_o = istb_o;
//
//
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),
.rst(wb_rst_i),
// internal ram
.wr_i(wr),
.wr_o(wr_o),
.wr_bit_i(bit_addr),
.wr_bit_o(bit_addr_o),
.wr_dat(wr_dat),
.des_acc(des_acc),
.des1(des1),
.des2(des2),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.wr_ind(wr_ind),
.bit_in(bit_data),
.in_ram(ram_data),
.sfr(sfr_out),
.sfr_bit(sfr_bit),
.bit_out(bit_out),
.iram_out(ram_out),
// external instrauction rom
.iack_i(iack_i),
.iadr_o(iadr_o),
.idat_i(idat_i),
.istb_o(istb_o),
// internal instruction rom
.idat_onchip(idat_onchip),
// data memory
.dadr_o(wbd_adr_o),
.ddat_o(wbd_dat_o),
.dwe_o(wbd_we_o),
.dstb_o(wbd_stb_o),
.ddat_i(wbd_dat_i),
.dack_i(wbd_ack_i),
// from decoder
.rd_sel(ram_rd_sel),
.wr_sel(ram_wr_sel),
.rn({bank_sel, op1_cur}),
.rd_ind(rd_ind),
.rd(rd),
.mem_act(mem_act),
.mem_wait(mem_wait),
// external access
.ea(ea_in),
.ea_int(ea_int),
// instructions outputs to cpu
.op1_out(op1_n),
.op2_out(op2_n),
.op3_out(op3_n),
// interrupt interface
.intr(intr),
.int_v(int_src),
.int_ack(int_ack),
.istb(istb),
.reti(reti),
//pc
.pc_wr_sel(pc_wr_sel),
.pc_wr(pc_wr & comp_wait),
.pc(pc),
// sfr's
.sp_w(sp_w),
.dptr({dptr_hi, dptr_lo}),
.ri(ri),
.acc(acc),
.sp(sp)
);
//
//
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i),
.clk(wb_clk_i),
.adr0(rd_addr[7:0]),
.adr1(wr_addr[7:0]),
.dat0(sfr_out),
.dat1(wr_dat),
.dat2(des2),
.des_acc(des_acc),
.we(wr_o && !wr_ind),
.bit_in(desCy),
.bit_out(sfr_bit),
.wr_bit(bit_addr_o),
.ram_rd_sel(ram_rd_sel),
.ram_wr_sel(ram_wr_sel),
.wr_sfr(wr_sfr),
.comp_sel(comp_sel),
.comp_wait(comp_wait),
// acc
.acc(acc),
// sp
.sp(sp),
.sp_w(sp_w),
// psw
.bank_sel(bank_sel),
.desAc(desAc),
.desOv(desOv),
.psw_set(psw_set),
.srcAc(srcAc),
.cy(cy),
// ports
.rmw(rmw),
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
.p0_out(p0_o),
.p0_in(p0_i),
`endif
`ifdef OC8051_PORT1
.p1_out(p1_o),
.p1_in(p1_i),
`endif
`ifdef OC8051_PORT2
.p2_out(p2_o),
.p2_in(p2_i),
`endif
`ifdef OC8051_PORT3
.p3_out(p3_o),
.p3_in(p3_i),
`endif
`endif
// uart
`ifdef OC8051_UART
.rxd(rxd_i), .txd(txd_o),
`endif
// int
.int_ack(int_ack),
.intr(intr),
.int0(int0_i),
.int1(int1_i),
.reti(reti),
.int_src(int_src),
// t/c 0,1
`ifdef OC8051_TC01
.t0(t0_i),
.t1(t1_i),
`endif
// t/c 2
`ifdef OC8051_TC2
.t2(t2_i),
.t2ex(t2ex_i),
`endif
// dptr
.dptr_hi(dptr_hi),
.dptr_lo(dptr_lo),
.wait_data(wait_data)
);
`ifdef OC8051_CACHE
oc8051_icache oc8051_icache1(.rst(wb_rst_i), .clk(wb_clk_i),
// cpu
.adr_i(iadr_o),
.dat_o(idat_i),
.stb_i(istb_o),
.ack_o(iack_i),
.cyc_i(icyc_o),
// pins
.dat_i(wbi_dat_i),
.stb_o(wbi_stb_o),
.adr_o(wbi_adr_o),
.ack_i(wbi_ack_i),
.cyc_o(wbi_cyc_o)
`ifdef OC8051_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_si),
.scanb_so(scanb_soi),
.scanb_en(scanb_en)
`endif
);
defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
`ifdef OC8051_SIMULATION
initial
begin
#1
$display("\t * ");
$display("\t * External rom interface: cache");
$display("\t * ");
end
`endif
//
// no cache
//
`else
`ifdef OC8051_BIST
assign scanb_soi=scanb_si;
`endif
`ifdef OC8051_WB
oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
// cpu
.adr_i(iadr_o),
.dat_o(idat_i),
.stb_i(istb_o),
.ack_o(iack_i),
.cyc_i(icyc_o),
// external rom
.dat_i(wbi_dat_i),
.stb_o(wbi_stb_o),
.adr_o(wbi_adr_o),
.ack_i(wbi_ack_i),
.cyc_o(wbi_cyc_o));
`ifdef OC8051_SIMULATION
initial
begin
#1
$display("\t * ");
$display("\t * External rom interface: WB interface");
$display("\t * ");
end
`endif
`else
assign wbi_adr_o = iadr_o ;
assign idat_i = wbi_dat_i ;
assign wbi_stb_o = 1'b1 ;
assign iack_i = wbi_ack_i ;
assign wbi_cyc_o = 1'b1 ;
`ifdef OC8051_SIMULATION
initial
begin
#1
$display("\t * ");
$display("\t * External rom interface: Pipelined interface");
$display("\t * ");
end
`endif
`endif
`endif
endmodule |
module oc8051_tc (clk, rst,
data_in,
wr_addr,
wr, wr_bit,
ie0, ie1,
tr0, tr1,
t0, t1,
tf0, tf1,
pres_ow,
//registers
tmod, tl0, th0, tl1, th1);
input [7:0] wr_addr,
data_in;
input clk,
rst,
wr,
wr_bit,
ie0,
ie1,
tr0,
tr1,
t0,
t1,
pres_ow;
output [7:0] tmod,
tl0,
th0,
tl1,
th1;
output tf0,
tf1;
reg [7:0] tmod, tl0, th0, tl1, th1;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
wire tc0_add, tc1_add;
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & ((!tmod[2] & pres_ow) | (tmod[2] & !t0 & t0_buff)));
assign tc1_add = (tr1 & (!tmod[7] | !ie1) & ((!tmod[6] & pres_ow) | (tmod[6] & !t1 & t1_buff)));
assign tf1= tf1_0 | tf1_1;
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tmod <=#1 `OC8051_RST_TMOD;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
tmod <= #1 data_in;
end
//
// TIMER COUNTER 0
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tl0 <=#1 `OC8051_RST_TL0;
th0 <=#1 `OC8051_RST_TH0;
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
tl0 <= #1 data_in;
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
th0 <= #1 data_in;
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end else begin
case (tmod[1:0]) /* synopsys full_case parallel_case */
`OC8051_MODE0: begin // mode 0
tf1_0 <= #1 1'b0;
if (tc0_add)
{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
end
`OC8051_MODE1: begin // mode 1
tf1_0 <= #1 1'b0;
if (tc0_add)
{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
end
`OC8051_MODE2: begin // mode 2
tf1_0 <= #1 1'b0;
if (tc0_add) begin
if (tl0 == 8'b1111_1111) begin
tf0 <=#1 1'b1;
tl0 <=#1 th0;
end
else begin
tl0 <=#1 tl0 + 8'h1;
tf0 <= #1 1'b0;
end
end
end
`OC8051_MODE3: begin // mode 3
if (tc0_add)
{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
if (tr1 & pres_ow)
{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
end
/* default:begin
tf0 <= #1 1'b0;
tf1_0 <= #1 1'b0;
end*/
endcase
end
end
//
// TIMER COUNTER 1
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tl1 <=#1 `OC8051_RST_TL1;
th1 <=#1 `OC8051_RST_TH1;
tf1_1 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
tl1 <= #1 data_in;
tf1_1 <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
th1 <= #1 data_in;
tf1_1 <= #1 1'b0;
end else begin
case (tmod[5:4]) /* synopsys full_case parallel_case */
`OC8051_MODE0: begin // mode 0
if (tc1_add)
{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
end
`OC8051_MODE1: begin // mode 1
if (tc1_add)
{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
end
`OC8051_MODE2: begin // mode 2
if (tc1_add) begin
if (tl1 == 8'b1111_1111) begin
tf1_1 <=#1 1'b1;
tl1 <=#1 th1;
end
else begin
tl1 <=#1 tl1 + 8'h1;
tf1_1 <= #1 1'b0;
end
end
end
/* default:begin
tf1_1 <= #1 1'b0;
end*/
endcase
end
end
always @(posedge clk or posedge rst)
if (rst) begin
t0_buff <= #1 1'b0;
t1_buff <= #1 1'b0;
end else begin
t0_buff <= #1 t0;
t1_buff <= #1 t1;
end
endmodule |
module oc8051_ram_64x32_dual_bist (
clk,
rst,
adr0,
dat0_o,
en0,
adr1,
dat1_i,
dat1_o,
en1,
wr1
`ifdef OC8051_BIST
,
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en
`endif
);
parameter ADR_WIDTH = 6;
input clk,
wr1,
rst,
en0,
en1;
input [7:0] dat1_i;
input [ADR_WIDTH-1:0] adr0,
adr1;
output [7:0] dat0_o,
dat1_o;
reg [7:0] rd_data;
`ifdef OC8051_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
`endif
`ifdef OC8051_RAM_XILINX
xilinx_ram_dp xilinx_ram(
// read port
.CLKA(clk),
.RSTA(rst),
.ENA(en0),
.ADDRA(adr0),
.DIA(32'h00),
.WEA(1'b0),
.DOA(dat0_o),
// write port
.CLKB(clk),
.RSTB(rst),
.ENB(en1),
.ADDRB(adr1),
.DIB(dat1_i),
.WEB(wr1),
.DOB(dat1_o)
);
defparam
xilinx_ram.dwidth = 32,
xilinx_ram.awidth = ADR_WIDTH;
`else
`ifdef OC8051_RAM_VIRTUALSILICON
`else
`ifdef OC8051_RAM_GENERIC
generic_dpram #(ADR_WIDTH, 32) oc8051_ram1(
.rclk ( clk ),
.rrst ( rst ),
.rce ( en0 ),
.oe ( 1'b1 ),
.raddr ( adr0 ),
.do ( dat0_o ),
.wclk ( clk ),
.wrst ( rst ),
.wce ( en1 ),
.we ( wr1 ),
.waddr ( adr1 ),
.di ( dat1_i )
);
`else
reg [31:0] dat1_o,
dat0_o;
//
// buffer
reg [31:0] buff [0:(1<<ADR_WIDTH) -1];
always @(posedge clk or posedge rst)
begin
if (rst)
dat1_o <= #1 32'h0;
else if (wr1) begin
buff[adr1] <= #1 dat1_i;
dat1_o <= #1 dat1_i;
end else
dat1_o <= #1 buff[adr1];
end
always @(posedge clk or posedge rst)
begin
if (rst)
dat0_o <= #1 32'h0;
else if ((adr0==adr1) & wr1)
dat0_o <= #1 dat1_i;
else
dat0_o <= #1 buff[adr0];
end
`endif //OC8051_RAM_GENERIC
`endif //OC8051_RAM_VIRTUALSILICON
`endif //OC8051_RAM_XILINX
endmodule |
module oc8051_dptr(clk, rst, addr, data_in, data2_in, wr, wr_sfr, wr_bit, data_hi, data_lo);
//
// clk (in) clock
// rst (in) reset
// addr (in) write address input [oc8051_ram_wr_sel.out]
// data_in (in) destination 1 from alu [oc8051_alu.des1]
// data2_in (in) destination 2 from alu [oc8051_alu.des2]
// wr (in) write to ram [oc8051_decoder.wr -r]
// wd2 (in) write from destination 2 [oc8051_decoder.ram_wr_sel -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// data_hi (out) output (high bits) [oc8051_alu_src3_sel.dptr, oc8051_ext_addr_sel.dptr_hi, oc8051_ram_sel.dptr_hi]
// data_lo (out) output (low bits) [oc8051_ext_addr_sel.dptr_lo]
//
input clk, rst, wr, wr_bit;
input [1:0] wr_sfr;
input [7:0] addr, data_in, data2_in;
output [7:0] data_hi, data_lo;
reg [7:0] data_hi, data_lo;
always @(posedge clk or posedge rst)
begin
if (rst) begin
data_hi <= #1 `OC8051_RST_DPH;
data_lo <= #1 `OC8051_RST_DPL;
end else if (wr_sfr==`OC8051_WRS_DPTR) begin
//
//write from destination 2 and 1
data_hi <= #1 data2_in;
data_lo <= #1 data_in;
end else if ((addr==`OC8051_SFR_DPTR_HI) & (wr) & !(wr_bit))
//
//case of writing to dptr
data_hi <= #1 data_in;
else if ((addr==`OC8051_SFR_DPTR_LO) & (wr) & !(wr_bit))
data_lo <= #1 data_in;
end
endmodule |
module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);
input clk, rst, wr, wr_bit;
input [2:0] ram_rd_sel, ram_wr_sel;
input [7:0] data_in, wr_addr;
output [7:0] sp_out, sp_w;
reg [7:0] sp_out, sp_w;
reg pop;
wire write;
wire [7:0] sp_t;
reg [7:0] sp;
assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
assign sp_t= write ? data_in : sp;
always @(posedge clk or posedge rst)
begin
if (rst)
sp <= #1 `OC8051_RST_SP;
else if (write)
sp <= #1 data_in;
else
sp <= #1 sp_out;
end
always @(sp or ram_wr_sel)
begin
//
// push
if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
else sp_w = sp;
end
always @(sp_t or ram_wr_sel or pop or write)
begin
//
// push
if (write) sp_out = sp_t;
else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
else sp_out = sp_t - {7'b0, pop};
end
always @(posedge clk or posedge rst)
begin
if (rst)
pop <= #1 1'b0;
else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
else pop <= #1 1'b0;
end
endmodule |
module oc8051_int (clk, rst,
wr_addr,
data_in, bit_in,
wr, wr_bit,
//timer interrupts
tf0, tf1, t2_int,
tr0, tr1,
//external interrupts
ie0, ie1,
//uart interrupts
uart_int,
//to cpu
intr, reti, int_vec, ack,
//registers
ie, tcon, ip);
input [7:0] wr_addr, data_in;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
output tr0, tr1, intr;
output [7:0] int_vec,
ie,
tcon,
ip;
reg [7:0] ip, ie, int_vec;
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0;
//
// isrc processing interrupt sources
// int_dept
wire [2:0] isrc_cur;
reg [2:0] isrc [1:0];
reg [1:0] int_dept;
wire [1:0] int_dept_1;
reg int_proc;
reg [1:0] int_lev [1:0];
wire cur_lev;
assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
assign int_dept_1 = int_dept - 2'b01;
assign cur_lev = int_lev[int_dept_1];
//
// contains witch level of interrupts is running
//reg [1:0] int_levl, int_levl_w;
//
// int_ln waiting interrupts on level n
// ip_ln interrupts on level n
// int_src interrupt sources
wire [5:0] int_l0, int_l1;
wire [5:0] ip_l0, ip_l1;
wire [5:0] int_src;
wire il0, il1;
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
//
//interrupt priority
assign ip_l0 = ~ip[5:0];
assign ip_l1 = ip[5:0];
assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
//
// waiting interrupts
assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
assign il0 = |int_l0;
assign il1 = |int_l1;
//
// TCON
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
//
// IP
always @(posedge clk or posedge rst)
begin
if (rst) begin
ip <=#1 `OC8051_RST_IP;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
ip <= #1 data_in;
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
ip[wr_addr[2:0]] <= #1 bit_in;
end
//
// IE
always @(posedge clk or posedge rst)
begin
if (rst) begin
ie <=#1 `OC8051_RST_IE;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
ie <= #1 data_in;
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
ie[wr_addr[2:0]] <= #1 bit_in;
end
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tcon_s <=#1 4'b0000;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
case (wr_addr[2:0]) /* synopsys full_case parallel_case */
3'b000: tcon_s[0] <= #1 bit_in;
3'b010: tcon_s[1] <= #1 bit_in;
3'b100: tcon_s[2] <= #1 bit_in;
3'b110: tcon_s[3] <= #1 bit_in;
endcase
end
end
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tcon_tf1 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_tf1 <= #1 data_in[7];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
tcon_tf1 <= #1 bit_in;
end else if (!(tf1_buff) & (tf1)) begin
tcon_tf1 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
tcon_tf1 <= #1 1'b0;
end
end
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tcon_tf0 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_tf0 <= #1 data_in[5];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
tcon_tf0 <= #1 bit_in;
end else if (!(tf0_buff) & (tf0)) begin
tcon_tf0 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
tcon_tf0 <= #1 1'b0;
end
end
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tcon_ie0 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_ie0 <= #1 data_in[1];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
tcon_ie0 <= #1 bit_in;
end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
tcon_ie0 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
tcon_ie0 <= #1 1'b0;
end else if (!(tcon_s[0]) & (ie0)) begin
tcon_ie0 <= #1 1'b0;
end
end
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tcon_ie1 <=#1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
tcon_ie1 <= #1 data_in[3];
end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
tcon_ie1 <= #1 bit_in;
end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
tcon_ie1 <= #1 1'b1;
end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
tcon_ie1 <= #1 1'b0;
end else if (!(tcon_s[1]) & (ie1)) begin
tcon_ie1 <= #1 1'b0;
end
end
//
// interrupt processing
always @(posedge clk or posedge rst)
begin
if (rst) begin
int_vec <= #1 8'h00;
int_dept <= #1 2'b0;
isrc[0] <= #1 3'h0;
isrc[1] <= #1 3'h0;
int_proc <= #1 1'b0;
int_lev[0] <= #1 1'b0;
int_lev[1] <= #1 1'b0;
end else if (reti & int_proc) begin // return from interrupt
if (int_dept==2'b01)
int_proc <= #1 1'b0;
int_dept <= #1 int_dept - 2'b01;
end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin // interrupt on level 1
int_proc <= #1 1'b1;
int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
int_dept <= #1 int_dept + 2'b01;
if (int_l1[0]) begin
int_vec <= #1 `OC8051_INT_X0;
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
end else if (int_l1[1]) begin
int_vec <= #1 `OC8051_INT_T0;
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
end else if (int_l1[2]) begin
int_vec <= #1 `OC8051_INT_X1;
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
end else if (int_l1[3]) begin
int_vec <= #1 `OC8051_INT_T1;
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
end else if (int_l1[4]) begin
int_vec <= #1 `OC8051_INT_UART;
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
end else if (int_l1[5]) begin
int_vec <= #1 `OC8051_INT_T2;
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
end
end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0
int_proc <= #1 1'b1;
int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
int_dept <= #1 2'b01;
if (int_l0[0]) begin
int_vec <= #1 `OC8051_INT_X0;
isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
end else if (int_l0[1]) begin
int_vec <= #1 `OC8051_INT_T0;
isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
end else if (int_l0[2]) begin
int_vec <= #1 `OC8051_INT_X1;
isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
end else if (int_l0[3]) begin
int_vec <= #1 `OC8051_INT_T1;
isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
end else if (int_l0[4]) begin
int_vec <= #1 `OC8051_INT_UART;
isrc[int_dept] <= #1 `OC8051_ISRC_UART;
end else if (int_l0[5]) begin
int_vec <= #1 `OC8051_INT_T2;
isrc[int_dept] <= #1 `OC8051_ISRC_T2;
end
end else begin
int_vec <= #1 8'h00;
end
end
always @(posedge clk or posedge rst)
if (rst) begin
tf0_buff <= #1 1'b0;
tf1_buff <= #1 1'b0;
ie0_buff <= #1 1'b0;
ie1_buff <= #1 1'b0;
end else begin
tf0_buff <= #1 tf0;
tf1_buff <= #1 tf1;
ie0_buff <= #1 ie0;
ie1_buff <= #1 ie1;
end
endmodule |
module oc8051_multiply (clk, rst, enable, src1, src2, des1, des2, desOv);
//
// this module is part of alu
// clk (in)
// rst (in)
// enable (in)
// src1 (in) first operand
// src2 (in) second operand
// des1 (out) first result
// des2 (out) second result
// desOv (out) Overflow output
//
input clk, rst, enable;
input [7:0] src1, src2;
output desOv;
output [7:0] des1, des2;
// wires
wire [15:0] mul_result1, mul_result, shifted;
// real registers
reg [1:0] cycle;
reg [15:0] tmp_mul;
assign mul_result1 = src1 * (cycle == 2'h0 ? src2[7:6]
: cycle == 2'h1 ? src2[5:4]
: cycle == 2'h2 ? src2[3:2]
: src2[1:0]);
assign shifted = (cycle == 2'h0 ? 16'h0 : {tmp_mul[13:0], 2'b00});
assign mul_result = mul_result1 + shifted;
assign des1 = mul_result[15:8];
assign des2 = mul_result[7:0];
assign desOv = | des1;
always @(posedge clk or posedge rst)
begin
if (rst) begin
cycle <= #1 2'b0;
tmp_mul <= #1 16'b0;
end else begin
if (enable) cycle <= #1 cycle + 2'b1;
tmp_mul <= #1 mul_result;
end
end
endmodule |
module oc8051_cache_ram (clk, rst, addr0, data0, addr1, data1_i, data1_o, wr1);
//
// this module is part of oc8051_icache
// it's tehnology dependent
//
// clk (in) clock
// addr0 (in) addres port 0
// data0 (out) data output port 0
// addr1 (in) address port 1
// data1_i (in) data input port 1
// data1_o (out) data output port 1
// wr1 (in) write port 1
//
parameter ADR_WIDTH = 7; // cache address wihth
parameter CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
input clk, wr1, rst;
input [ADR_WIDTH-1:0] addr0, addr1;
input [31:0] data1_i;
output [31:0] data0, data1_o;
`ifdef OC8051_XILINX_RAM
RAMB4_S8_S8 ram1(.DOA(data0[7:0]), .DOB(data1_o[7:0]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[7:0]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
RAMB4_S8_S8 ram2(.DOA(data0[15:8]), .DOB(data1_o[15:8]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[15:8]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
RAMB4_S8_S8 ram3(.DOA(data0[23:16]), .DOB(data1_o[23:16]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[23:16]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
RAMB4_S8_S8 ram4(.DOA(data0[31:24]), .DOB(data1_o[31:24]), .ADDRA({2'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
.RSTA(rst), .ADDRB({2'b0, addr1}), .DIB(data1_i[31:24]), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
`else
reg [31:0] data0, data1_o;
//
// buffer
reg [31:0] buff [0:CACHE_RAM];
//
// port 1
//
always @(posedge clk or posedge rst)
begin
if (rst)
data1_o <= #1 32'h0;
else if (wr1) begin
buff[addr1] <= #1 data1_i;
data1_o <= #1 data1_i;
end else
data1_o <= #1 buff[addr1];
end
//
// port 0
//
always @(posedge clk or posedge rst)
begin
if (rst)
data0 <= #1 32'h0;
else if ((addr0==addr1) & wr1)
data0 <= #1 data1_i;
else
data0 <= #1 buff[addr0];
end
`endif
endmodule |
module oc8051_cy_select (cy_sel, cy_in, data_in, data_out);
//
// cy_sel (in) carry select, from decoder (see defines.v) [oc8051_decoder.cy_sel -r]
// cy_in (in) carry input [oc8051_psw.data_out[7] ]
// data_in (in) ram data input [oc8051_ram_sel.bit_out]
// data_out (out) data output [oc8051_alu.srcCy]
//
input [1:0] cy_sel;
input cy_in, data_in;
output data_out;
reg data_out;
always @(cy_sel or cy_in or data_in)
begin
case (cy_sel) /* synopsys full_case parallel_case */
`OC8051_CY_0: data_out = 1'b0;
`OC8051_CY_PSW: data_out = cy_in;
`OC8051_CY_RAM: data_out = data_in;
`OC8051_CY_1: data_out = 1'b1;
endcase
end
endmodule |
module oc8051_psw (clk, rst, wr_addr, data_in, wr, wr_bit, data_out, p,
cy_in, ac_in, ov_in, set, bank_sel);
//
// clk (in) clock
// rst (in) reset
// addr (in) write address [oc8051_ram_wr_sel.out]
// data_in (in) data input [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// p (in) parity [oc8051_acc.p]
// cy_in (in) input bit data [oc8051_alu.desCy]
// ac_in (in) auxiliary carry input [oc8051_alu.desAc]
// ov_in (in) overflov input [oc8051_alu.desOv]
// set (in) set psw (write to caryy, carry and overflov or carry, owerflov and ac) [oc8051_decoder.psw_set -r]
//
input clk, rst, wr, p, cy_in, ac_in, ov_in, wr_bit;
input [1:0] set;
input [7:0] wr_addr, data_in;
output [1:0] bank_sel;
output [7:0] data_out;
reg [7:1] data;
wire wr_psw;
assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
assign data_out = {data[7:1], p};
//
//case writing to psw
always @(posedge clk or posedge rst)
begin
if (rst)
data <= #1 `OC8051_RST_PSW;
//
// write to psw (byte addressable)
else begin
if (wr & (wr_bit==1'b0) & (wr_addr==`OC8051_SFR_PSW))
data[7:1] <= #1 data_in[7:1];
//
// write to psw (bit addressable)
else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))
data[wr_addr[2:0]] <= #1 cy_in;
else begin
case (set) /* synopsys full_case parallel_case */
`OC8051_PS_CY: begin
//
//write carry
data[7] <= #1 cy_in;
end
`OC8051_PS_OV: begin
//
//write carry and overflov
data[7] <= #1 cy_in;
data[2] <= #1 ov_in;
end
`OC8051_PS_AC:begin
//
//write carry, overflov and ac
data[7] <= #1 cy_in;
data[6] <= #1 ac_in;
data[2] <= #1 ov_in;
end
endcase
end
end
end
endmodule |
module oc8051_uart (rst, clk,
bit_in, data_in,
wr_addr,
wr, wr_bit,
rxd, txd,
intr,
brate2, t1_ow, pres_ow,
rclk, tclk,
//registers
scon, pcon, sbuf);
input rst,
clk,
bit_in,
wr,
rxd,
wr_bit,
t1_ow,
brate2,
pres_ow,
rclk,
tclk;
input [7:0] data_in,
wr_addr;
output txd,
intr;
output [7:0] scon,
pcon,
sbuf;
reg t1_ow_buf;
//
reg [7:0] scon, pcon;
reg txd,
trans,
receive,
tx_done,
rx_done,
rxd_r,
shift_tr,
shift_re;
reg [1:0] rx_sam;
reg [3:0] tr_count,
re_count;
reg [7:0] sbuf_rxd;
reg [11:0] sbuf_rxd_tmp;
reg [10:0] sbuf_txd;
assign sbuf = sbuf_rxd;
assign intr = scon[1] | scon [0];
//
//serial port control register
//
wire ren, tb8, rb8, ri;
assign ren = scon[4];
assign tb8 = scon[3];
assign rb8 = scon[2];
assign ri = scon[0];
always @(posedge clk or posedge rst)
begin
if (rst)
scon <= #1 `OC8051_RST_SCON;
else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
scon <= #1 data_in;
else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
scon[wr_addr[2:0]] <= #1 bit_in;
else if (tx_done)
scon[1] <= #1 1'b1;
else if (!rx_done) begin
if (scon[7:6]==2'b00) begin
scon[0] <= #1 1'b1;
end else if ((sbuf_rxd_tmp[11]) | !(scon[5])) begin
scon[0] <= #1 1'b1;
scon[2] <= #1 sbuf_rxd_tmp[11];
end else
scon[2] <= #1 sbuf_rxd_tmp[11];
end
end
//
//power control register
//
wire smod;
assign smod = pcon[7];
always @(posedge clk or posedge rst)
begin
if (rst)
begin
pcon <= #1 `OC8051_RST_PCON;
end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
pcon <= #1 data_in;
end
//
//serial port buffer (transmit)
//
wire wr_sbuf;
assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
always @(posedge clk or posedge rst)
begin
if (rst) begin
txd <= #1 1'b1;
tr_count <= #1 4'd0;
trans <= #1 1'b0;
sbuf_txd <= #1 11'h00;
tx_done <= #1 1'b0;
//
// start transmiting
//
end else if (wr_sbuf) begin
case (scon[7:6]) /* synopsys parallel_case */
2'b00: begin // mode 0
sbuf_txd <= #1 {3'b001, data_in};
end
2'b01: begin // mode 1
sbuf_txd <= #1 {2'b01, data_in, 1'b0};
end
default: begin // mode 2 and mode 3
sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0};
end
endcase
trans <= #1 1'b1;
tr_count <= #1 4'd0;
tx_done <= #1 1'b0;
//
// transmiting
//
end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0
begin
if (~|sbuf_txd[10:1]) begin
trans <= #1 1'b0;
tx_done <= #1 1'b1;
end else begin
{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
tx_done <= #1 1'b0;
end
end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3
tr_count <= #1 tr_count + 4'd1;
if (~|tr_count) begin
if (~|sbuf_txd[10:0]) begin
trans <= #1 1'b0;
tx_done <= #1 1'b1;
txd <= #1 1'b1;
end else begin
{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
tx_done <= #1 1'b0;
end
end
end else if (!trans) begin
txd <= #1 1'b1;
tx_done <= #1 1'b0;
end
end
//
//
reg sc_clk_tr, smod_clk_tr;
always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or tclk)
begin
if (scon[7:6]==8'b10) begin //mode 2
sc_clk_tr = 1'b1;
end else if (tclk) begin //
sc_clk_tr = brate2;
end else begin //
sc_clk_tr = !t1_ow_buf & t1_ow;
end
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
smod_clk_tr <= #1 1'b0;
shift_tr <= #1 1'b0;
end else if (sc_clk_tr) begin
if (smod) begin
shift_tr <= #1 1'b1;
end else begin
shift_tr <= #1 smod_clk_tr;
smod_clk_tr <= #1 !smod_clk_tr;
end
end else begin
shift_tr <= #1 1'b0;
end
end
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
re_count <= #1 4'd0;
receive <= #1 1'b0;
sbuf_rxd <= #1 8'h00;
sbuf_rxd_tmp <= #1 12'd0;
rx_done <= #1 1'b1;
rxd_r <= #1 1'b1;
rx_sam <= #1 2'b00;
end else if (!rx_done) begin
receive <= #1 1'b0;
rx_done <= #1 1'b1;
sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};
end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
re_count <= #1 re_count + 4'd1;
case (re_count) /* synopsys full_case parallel_case */
4'h7: rx_sam[0] <= #1 rxd;
4'h8: rx_sam[1] <= #1 rxd;
4'h9: begin
{sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};
end
endcase
//
//start receiving
//
end else if (scon[7:6]==2'b00) begin //start mode 0
rx_done <= #1 1'b1;
if (ren && !ri && !receive) begin
receive <= #1 1'b1;
sbuf_rxd_tmp <= #1 10'h0ff;
end
end else if (ren & shift_re) begin
rxd_r <= #1 rxd;
rx_done <= #1 1'b1;
re_count <= #1 4'h0;
receive <= #1 (rxd_r & !rxd);
sbuf_rxd_tmp <= #1 10'h1ff;
end else if (!ren) begin
rxd_r <= #1 rxd;
end else
rx_done <= #1 1'b1;
end
//
//
reg sc_clk_re, smod_clk_re;
always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or rclk)
begin
if (scon[7:6]==8'b10) begin //mode 2
sc_clk_re = 1'b1;
end else if (rclk) begin //
sc_clk_re = brate2;
end else begin //
sc_clk_re = !t1_ow_buf & t1_ow;
end
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
smod_clk_re <= #1 1'b0;
shift_re <= #1 1'b0;
end else if (sc_clk_re) begin
if (smod) begin
shift_re <= #1 1'b1;
end else begin
shift_re <= #1 smod_clk_re;
smod_clk_re <= #1 !smod_clk_re;
end
end else begin
shift_re <= #1 1'b0;
end
end
//
//
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
t1_ow_buf <= #1 1'b0;
end else begin
t1_ow_buf <= #1 t1_ow;
end
end
endmodule |
module oc8051_alu_src_sel (clk, rst, rd, sel1, sel2, sel3,
acc, ram, pc, dptr,
op1, op2, op3,
src1, src2, src3);
input clk, rst, rd, sel3;
input [1:0] sel2;
input [2:0] sel1;
input [7:0] acc, ram;
input [15:0] dptr;
input [15:0] pc;
input [7:0] op1, op2, op3;
output [7:0] src1, src2, src3;
reg [7:0] src1, src2, src3;
reg [7:0] op1_r, op2_r, op3_r;
///////
//
// src1
//
///////
always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram)
begin
case (sel1) /* synopsys full_case parallel_case */
`OC8051_AS1_RAM: src1 = ram;
`OC8051_AS1_ACC: src1 = acc;
`OC8051_AS1_OP1: src1 = op1_r;
`OC8051_AS1_OP2: src1 = op2_r;
`OC8051_AS1_OP3: src1 = op3_r;
`OC8051_AS1_PCH: src1 = pc[15:8];
`OC8051_AS1_PCL: src1 = pc[7:0];
// default: src1 = 8'h00;
endcase
end
///////
//
// src2
//
///////
always @(sel2 or op2_r or acc or ram or op1_r)
begin
case (sel2) /* synopsys full_case parallel_case */
`OC8051_AS2_ACC: src2= acc;
`OC8051_AS2_ZERO: src2= 8'h00;
`OC8051_AS2_RAM: src2= ram;
`OC8051_AS2_OP2: src2= op2_r;
// default: src2= 8'h00;
endcase
end
///////
//
// src3
//
///////
always @(sel3 or pc[15:8] or dptr[15:8] or op1_r)
begin
case (sel3) /* synopsys full_case parallel_case */
`OC8051_AS3_DP: src3= dptr[15:8];
`OC8051_AS3_PC: src3= pc[15:8];
// default: src3= 16'h0;
endcase
end
always @(posedge clk or posedge rst)
if (rst) begin
op1_r <= #1 8'h00;
op2_r <= #1 8'h00;
op3_r <= #1 8'h00;
end else begin
op1_r <= #1 op1;
op2_r <= #1 op2;
op3_r <= #1 op3;
end
endmodule |
module oc8051_acc (clk, rst,
bit_in, data_in, data2_in,
data_out,
wr, wr_bit, wr_addr,
p, wr_sfr);
input clk, rst, wr, wr_bit, bit_in;
input [1:0] wr_sfr;
input [7:0] wr_addr, data_in, data2_in;
output p;
output [7:0] data_out;
reg [7:0] data_out;
reg [7:0] acc;
wire wr_acc, wr2_acc, wr_bit_acc;
//
//calculates parity
assign p = ^acc;
assign wr_acc = (wr_sfr==`OC8051_WRS_ACC1) | (wr & !wr_bit & (wr_addr==`OC8051_SFR_ACC));
assign wr2_acc = (wr_sfr==`OC8051_WRS_ACC2);
assign wr_bit_acc = (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_ACC));
//
//writing to acc
always @(wr_sfr or data2_in or wr2_acc or wr_acc or wr_bit_acc or wr_addr[2:0] or data_in or bit_in or data_out)
begin
if (wr2_acc)
acc = data2_in;
else if (wr_acc)
acc = data_in;
else if (wr_bit_acc)
case (wr_addr[2:0]) /* synopsys full_case parallel_case */
3'b000: acc = {data_out[7:1], bit_in};
3'b001: acc = {data_out[7:2], bit_in, data_out[0]};
3'b010: acc = {data_out[7:3], bit_in, data_out[1:0]};
3'b011: acc = {data_out[7:4], bit_in, data_out[2:0]};
3'b100: acc = {data_out[7:5], bit_in, data_out[3:0]};
3'b101: acc = {data_out[7:6], bit_in, data_out[4:0]};
3'b110: acc = {data_out[7], bit_in, data_out[5:0]};
3'b111: acc = {bit_in, data_out[6:0]};
endcase
else
acc = data_out;
end
always @(posedge clk or posedge rst)
begin
if (rst)
data_out <= #1 `OC8051_RST_ACC;
else
data_out <= #1 acc;
end
`ifdef OC8051_SIMULATION
always @(data_out)
if (data_out===8'hxx) begin
$display("time ",$time, " faulire: invalid write to ACC (oc8051_acc)");
#22
$finish;
end
`endif
endmodule |
module oc8051_icache (rst, clk,
adr_i, dat_o, stb_i, ack_o, cyc_i,
adr_o, dat_i, stb_o, ack_i, cyc_o
`ifdef OC8051_BIST
,
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en
`endif
);
//
// rst (in) reset - pin
// clk (in) clock - pini
input rst, clk;
//
// interface to oc8051 cpu
//
// adr_i (in) address
// dat_o (out) data output
// stb_i (in) strobe
// ack_o (out) acknowledge
// cyc_i (in) cycle
input stb_i,
cyc_i;
input [15:0] adr_i;
output ack_o;
output [31:0] dat_o;
reg [31:0] dat_o;
//
// interface to instruction rom
//
// adr_o (out) address
// dat_i (in) data input
// stb_o (out) strobe
// ack_i (in) acknowledge
// cyc_o (out) cycle
input ack_i;
input [31:0] dat_i;
output stb_o,
cyc_o;
output [15:0] adr_o;
reg stb_o,
cyc_o;
`ifdef OC8051_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
`endif
parameter ADR_WIDTH = 6; // cache address wihth
parameter LINE_WIDTH = 2; // line address width (2 => 4x32)
parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width
parameter BL_NUM = 15; // number of blocks (2^BL_WIDTH-1)
parameter CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
//
// internal buffers adn wires
//
// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache
reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
// valid[x]=1 if block x is valid;
reg [BL_NUM:0] valid;
// con0, con2 contain temporal control information of current address and corrent address+2
// part of con_buf memory
reg [13-ADR_WIDTH:0] con0, con2;
//current upper address,
reg [13-ADR_WIDTH:0] cadr0, cadr2;
reg stb_b;
// byte_select in 32 bit line (adr_i[1:0])
reg [1:0] byte_sel;
// read cycle
reg [LINE_WIDTH-1:0] cyc;
// data input from cache ram
reg [31:0] data1_i;
// temporaly data from ram
reg [15:0] tmp_data1;
reg wr1, wr1_t, stb_it;
////////////////
reg vaild_h, vaild_l;
wire [31:0] data0, data1_o;
wire cy, cy1;
wire [BL_WIDTH-1:0] adr_i2;
wire hit, hit_l, hit_h;
wire [ADR_WIDTH-1:0] adr_r, addr1;
reg [ADR_WIDTH-1:0] adr_w;
reg [15:0] mis_adr;
wire [15:0] data1;
wire [LINE_WIDTH-1:0] adr_r1;
assign cy = &adr_i[LINE_WIDTH+1:1];
assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;
assign hit_l = (con0==cadr0) & vaild_l;
assign hit_h = (con2==cadr2) & vaild_h;
assign hit = hit_l && hit_h;
assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];
assign addr1 = wr1 ? adr_w : adr_r;
assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;
assign ack_o = hit && stb_it;
assign data1 = wr1_t ? tmp_data1 : data1_o[15:0];
assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};
oc8051_ram_64x32_dual_bist oc8051_cache_ram(
.clk ( clk ),
.rst ( rst ),
.adr0 ( adr_i[ADR_WIDTH+1:2] ),
.dat0_o ( data0 ),
.en0 ( 1'b1 ),
.adr1 ( addr1 ),
.dat1_o ( data1_o ),
.dat1_i ( data1_i ),
.en1 ( 1'b1 ),
.wr1 ( wr1 )
`ifdef OC8051_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_soi),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
`endif
);
defparam oc8051_cache_ram.ADR_WIDTH = ADR_WIDTH;
always @(stb_b or data0 or data1 or byte_sel)
begin
if (stb_b) begin
case (byte_sel) /* synopsys full_case parallel_case */
2'b00 : dat_o = data0;
2'b01 : dat_o = {data1[7:0], data0[31:8]};
2'b10 : dat_o = {data1[15:0], data0[31:16]};
2'b11 : dat_o = {8'h00, data1, data0[31:24]};
endcase
end else begin
dat_o = 32'h0;
end
end
always @(posedge clk or posedge rst)
begin
if (rst)
begin
con0 <= #1 9'h0;
con2 <= #1 9'h0;
vaild_h <= #1 1'b0;
vaild_l <= #1 1'b0;
end
else
begin
con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
con2 <= #1 {con_buf[adr_i2]};
vaild_l <= #1 valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]];
vaild_h <= #1 valid[adr_i2];
end
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
cadr0 <= #1 8'h00;
cadr2 <= #1 8'h00;
end else begin
cadr0 <= #1 adr_i[15:ADR_WIDTH+2];
cadr2 <= #1 adr_i[15:ADR_WIDTH+2]+ cy1;
end
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
stb_b <= #1 1'b0;
byte_sel <= #1 2'b00;
end else begin
stb_b <= #1 stb_i;
byte_sel <= #1 adr_i[1:0];
end
end
always @(posedge clk or posedge rst)
begin
if (rst)
begin
cyc <= #1 2'b00;
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
data1_i<= #1 32'h0;
wr1 <= #1 1'b0;
adr_w <= #1 6'h0;
valid <= #1 16'h0;
end
else if (stb_b && !hit && !stb_o && !wr1)
begin
cyc <= #1 2'b00;
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
data1_i <= #1 32'h0;
wr1 <= #1 1'b0;
end
else if (stb_o && ack_i)
begin
data1_i<= #1 dat_i; ///??
wr1 <= #1 1'b1;
adr_w <= #1 adr_o[ADR_WIDTH+1:2];
if (&cyc)
begin
cyc <= #1 2'b00;
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
end
else
begin
cyc <= #1 cyc + 1'b1;
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b0;
end
end
else
wr1 <= #1 1'b0;
end
//rih
always @(posedge clk)
if ( ~(stb_b && !hit && !stb_o && !wr1) & (stb_o && ack_i && cyc) )
con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
always @(posedge clk or posedge rst)
begin
if (rst)
mis_adr <= #1 1'b0;
else if (!hit_l)
mis_adr <= #1 adr_i;
else if (!hit_h)
mis_adr <= #1 adr_i+'d2;
end
always @(posedge clk or posedge rst)
begin
if (rst)
tmp_data1 <= #1 1'b0;
else if (!hit_h && wr1 && (cyc==adr_r1))
// tmp_data1 <= #1 dat_i[31:16]; //???
tmp_data1 <= #1 dat_i[15:0]; //???
else if (!hit_l && hit_h && wr1)
// tmp_data1 <= #1 data1_o[31:16];
tmp_data1 <= #1 data1_o[15:0]; //??
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
wr1_t <= #1 1'b0;
stb_it <= #1 1'b0;
end else begin
wr1_t <= #1 wr1;
stb_it <= #1 stb_i;
end
end
endmodule |
module oc8051_ram_top (clk,
rst,
rd_addr,
rd_data,
wr_addr,
bit_addr,
wr_data,
wr,
bit_data_in,
bit_data_out
`ifdef OC8051_BIST
,
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en
`endif
);
// on-chip ram-size (2**ram_aw bytes)
parameter ram_aw = 8; // default 256 bytes
//
// clk (in) clock
// rd_addr (in) read addres [oc8051_ram_rd_sel.out]
// rd_data (out) read data [oc8051_ram_sel.in_ram]
// wr_addr (in) write addres [oc8051_ram_wr_sel.out]
// bit_addr (in) bit addresable instruction [oc8051_decoder.bit_addr -r]
// wr_data (in) write data [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// bit_data_in (in) bit data input [oc8051_alu.desCy]
// bit_data_out (out) bit data output [oc8051_ram_sel.bit_in]
//
input clk, wr, bit_addr, bit_data_in, rst;
input [7:0] wr_data;
input [7:0] rd_addr, wr_addr;
output bit_data_out;
output [7:0] rd_data;
`ifdef OC8051_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
`endif
// rd_addr_m read address modified
// wr_addr_m write address modified
// wr_data_m write data modified
reg [7:0] wr_data_m;
reg [7:0] rd_addr_m, wr_addr_m;
wire rd_en;
reg bit_addr_r,
rd_en_r;
reg [7:0] wr_data_r;
wire [7:0] rd_data_m;
reg [2:0] bit_select;
assign bit_data_out = rd_data[bit_select];
assign rd_data = rd_en_r ? wr_data_r: rd_data_m;
assign rd_en = (rd_addr_m == wr_addr_m) & wr;
oc8051_ram_256x8_two_bist oc8051_idata(
.clk ( clk ),
.rst ( rst ),
.rd_addr ( rd_addr_m ),
.rd_data ( rd_data_m ),
.rd_en ( !rd_en ),
.wr_addr ( wr_addr_m ),
.wr_data ( wr_data_m ),
.wr_en ( 1'b1 ),
.wr ( wr )
`ifdef OC8051_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
`endif
);
always @(posedge clk or posedge rst)
if (rst) begin
bit_addr_r <= #1 1'b0;
bit_select <= #1 3'b0;
end else begin
bit_addr_r <= #1 bit_addr;
bit_select <= #1 rd_addr[2:0];
end
always @(posedge clk or posedge rst)
if (rst) begin
rd_en_r <= #1 1'b0;
wr_data_r <= #1 8'h0;
end else begin
rd_en_r <= #1 rd_en;
wr_data_r <= #1 wr_data_m;
end
always @(rd_addr or bit_addr)
casex ( {bit_addr, rd_addr[7]} ) // synopsys full_case parallel_case
2'b0?: rd_addr_m = rd_addr;
2'b10: rd_addr_m = {4'b0010, rd_addr[6:3]};
2'b11: rd_addr_m = {1'b1, rd_addr[6:3], 3'b000};
endcase
always @(wr_addr or bit_addr_r)
casex ( {bit_addr_r, wr_addr[7]} ) // synopsys full_case parallel_case
2'b0?: wr_addr_m = wr_addr;
2'b10: wr_addr_m = {8'h00, 4'b0010, wr_addr[6:3]};
2'b11: wr_addr_m = {8'h00, 1'b1, wr_addr[6:3], 3'b000};
endcase
always @(rd_data or bit_select or bit_data_in or wr_data or bit_addr_r)
casex ( {bit_addr_r, bit_select} ) // synopsys full_case parallel_case
4'b0_???: wr_data_m = wr_data;
4'b1_000: wr_data_m = {rd_data[7:1], bit_data_in};
4'b1_001: wr_data_m = {rd_data[7:2], bit_data_in, rd_data[0]};
4'b1_010: wr_data_m = {rd_data[7:3], bit_data_in, rd_data[1:0]};
4'b1_011: wr_data_m = {rd_data[7:4], bit_data_in, rd_data[2:0]};
4'b1_100: wr_data_m = {rd_data[7:5], bit_data_in, rd_data[3:0]};
4'b1_101: wr_data_m = {rd_data[7:6], bit_data_in, rd_data[4:0]};
4'b1_110: wr_data_m = {rd_data[7], bit_data_in, rd_data[5:0]};
4'b1_111: wr_data_m = {bit_data_in, rd_data[6:0]};
endcase
endmodule |
module oc8051_tc2 (clk, rst,
wr_addr,
data_in, bit_in,
wr, wr_bit,
t2, t2ex,
rclk, tclk,
brate2, tc2_int,
pres_ow,
//registers
t2con, tl2, th2, rcap2l, rcap2h);
input [7:0] wr_addr,
data_in;
input clk,
rst,
wr,
wr_bit,
t2,
t2ex,
bit_in,
pres_ow; //prescalre owerflov
output [7:0] t2con,
tl2,
th2,
rcap2l,
rcap2h;
output tc2_int,
rclk,
tclk,
brate2;
reg brate2;
reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;
reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;
wire run;
//
// t2con
wire tf2, exf2, exen2, tr2, ct2, cprl2;
assign tc2_int = tf2 | exf2;
assign tf2 = t2con[7];
assign exf2 = t2con[6];
assign rclk = t2con[5];
assign tclk = t2con[4];
assign exen2 = t2con[3];
assign tr2 = t2con[2];
assign ct2 = t2con[1];
assign cprl2 = t2con[0];
always @(posedge clk or posedge rst)
begin
if (rst) begin
t2con <= #1 `OC8051_RST_T2CON;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
t2con <= #1 data_in;
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
t2con[wr_addr[2:0]] <= #1 bit_in;
end else if (tf2_set) begin
t2con[7] <= #1 1'b1;
end else if (exen2 & neg_trans) begin
t2con[6] <= #1 1'b1;
end
end
//
//th2, tl2
assign run = tr2 & ((!ct2 & pres_ow) | (ct2 & tc2_event));
always @(posedge clk or posedge rst)
begin
if (rst) begin
//
// reset
//
tl2 <= #1 `OC8051_RST_TL2;
th2 <= #1 `OC8051_RST_TH2;
brate2 <= #1 1'b0;
tf2_set <= #1 1'b0;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
//
// write to timer 2 high
//
th2 <= #1 data_in;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
//
// write to timer 2 low
//
tl2 <= #1 data_in;
end else if (!(rclk | tclk) & !cprl2 & exen2 & neg_trans) begin
//
// avto reload mode, exen2=1, 0-1 transition on t2ex pin
//
th2 <= #1 rcap2h;
tl2 <= #1 rcap2l;
tf2_set <= #1 1'b0;
end else if (run) begin
if (rclk | tclk) begin
//
// boud rate generator mode
//
if (&{th2, tl2}) begin
th2 <= #1 rcap2h;
tl2 <= #1 rcap2l;
brate2 <= #1 1'b1;
end else begin
{brate2, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
end
tf2_set <= #1 1'b0;
end else if (cprl2) begin
//
// capture mode
//
{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
end else begin
//
// auto reload mode
//
if (&{th2, tl2}) begin
th2 <= #1 rcap2h;
tl2 <= #1 rcap2l;
tf2_set <= #1 1'b1;
end else begin
{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
end
end
end else tf2_set <= #1 1'b0;
end
//
// rcap2l, rcap2h
always @(posedge clk or posedge rst)
begin
if (rst) begin
rcap2l <= #1 `OC8051_RST_RCAP2L;
rcap2h <= #1 `OC8051_RST_RCAP2H;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
rcap2h <= #1 data_in;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
rcap2l <= #1 data_in;
end else if (!(rclk | tclk) & exen2 & cprl2 & neg_trans) begin
rcap2l <= #1 tl2;
rcap2h <= #1 th2;
end
end
//
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
neg_trans <= #1 1'b0;
t2ex_r <= #1 1'b0;
end else if (t2ex) begin
neg_trans <= #1 1'b0;
t2ex_r <= #1 1'b1;
end else if (t2ex_r) begin
neg_trans <= #1 1'b1;
t2ex_r <= #1 1'b0;
end else begin
neg_trans <= #1 1'b0;
t2ex_r <= #1 t2ex_r;
end
end
//
//
always @(posedge clk or posedge rst)
begin
if (rst) begin
tc2_event <= #1 1'b0;
t2_r <= #1 1'b0;
end else if (t2) begin
tc2_event <= #1 1'b0;
t2_r <= #1 1'b1;
end else if (!t2 & t2_r) begin
tc2_event <= #1 1'b1;
t2_r <= #1 1'b0;
end else begin
tc2_event <= #1 1'b0;
end
end
endmodule |
module oc8051_b_register (clk, rst, bit_in, data_in, wr, wr_bit,
wr_addr, data_out);
input clk, rst, wr, wr_bit, bit_in;
input [7:0] wr_addr, data_in;
output [7:0] data_out;
reg [7:0] data_out;
//
//writing to b
//must check if write high and correct address
always @(posedge clk or posedge rst)
begin
if (rst)
data_out <= #1 `OC8051_RST_B;
else if (wr) begin
if (!wr_bit) begin
if (wr_addr==`OC8051_SFR_B)
data_out <= #1 data_in;
end else begin
if (wr_addr[7:3]==`OC8051_SFR_B_B)
data_out[wr_addr[2:0]] <= #1 bit_in;
end
end
end
endmodule |
module oc8051_divide (clk, rst, enable, src1, src2, des1, des2, desOv);
//
// this module is part of alu
// clk (in)
// rst (in)
// enable (in) starts divison
// src1 (in) first operand
// src2 (in) second operand
// des1 (out) first result
// des2 (out) second result
// desOv (out) Overflow output
//
input clk, rst, enable;
input [7:0] src1, src2;
output desOv;
output [7:0] des1, des2;
// wires
wire desOv;
wire div0, div1;
wire [7:0] rem0, rem1, rem2;
wire [8:0] sub0, sub1;
wire [15:0] cmp0, cmp1;
wire [7:0] div_out, rem_out;
// real registers
reg [1:0] cycle;
reg [5:0] tmp_div;
reg [7:0] tmp_rem;
// The main logic
assign cmp1 = src2 << ({2'h3 - cycle, 1'b0} + 3'h1);
assign cmp0 = src2 << ({2'h3 - cycle, 1'b0} + 3'h0);
assign rem2 = cycle != 0 ? tmp_rem : src1;
assign sub1 = {1'b0, rem2} - {1'b0, cmp1[7:0]};
assign div1 = |cmp1[15:8] ? 1'b0 : !sub1[8];
assign rem1 = div1 ? sub1[7:0] : rem2[7:0];
assign sub0 = {1'b0, rem1} - {1'b0, cmp0[7:0]};
assign div0 = |cmp0[15:8] ? 1'b0 : !sub0[8];
assign rem0 = div0 ? sub0[7:0] : rem1[7:0];
//
// in clock cycle 0 we first calculate two MSB bits, ...
// till finally in clock cycle 3 we calculate two LSB bits
assign div_out = {tmp_div, div1, div0};
assign rem_out = rem0;
assign desOv = src2 == 8'h0;
//
// divider works in four clock cycles -- 0, 1, 2 and 3
always @(posedge clk or posedge rst)
begin
if (rst) begin
cycle <= #1 2'b0;
tmp_div <= #1 6'h0;
tmp_rem <= #1 8'h0;
end else begin
if (enable) cycle <= #1 cycle + 2'b1;
tmp_div <= #1 div_out[5:0];
tmp_rem <= #1 rem_out;
end
end
//
// assign outputs
assign des1 = rem_out;
assign des2 = div_out;
endmodule |
module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
//
input clk, // clock
rst, // reset
wr, // write
sel, // select register
wr_bit; // write bit addressable
input [1:0] bank; // select register bank
input [7:0] data_in; // data input
input [7:0] wr_addr; // write address
output [7:0] ri_out;
//reg [7:0] buff [31:0];
reg wr_bit_r;
reg [7:0] buff [0:7];
//
//write to buffer
always @(posedge clk or posedge rst)
begin
if (rst) begin
buff[3'b000] <= #1 8'h00;
buff[3'b001] <= #1 8'h00;
buff[3'b010] <= #1 8'h00;
buff[3'b011] <= #1 8'h00;
buff[3'b100] <= #1 8'h00;
buff[3'b101] <= #1 8'h00;
buff[3'b110] <= #1 8'h00;
buff[3'b111] <= #1 8'h00;
end else begin
if ((wr) & !(wr_bit_r)) begin
case (wr_addr) /* synopsys full_case parallel_case */
8'h00: buff[3'b000] <= #1 data_in;
8'h01: buff[3'b001] <= #1 data_in;
8'h08: buff[3'b010] <= #1 data_in;
8'h09: buff[3'b011] <= #1 data_in;
8'h10: buff[3'b100] <= #1 data_in;
8'h11: buff[3'b101] <= #1 data_in;
8'h18: buff[3'b110] <= #1 data_in;
8'h19: buff[3'b111] <= #1 data_in;
endcase
end
end
end
//
//read from buffer
assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
data_in : buff[{bank, sel}];
always @(posedge clk or posedge rst)
if (rst) begin
wr_bit_r <= #1 1'b0;
end else begin
wr_bit_r <= #1 wr_bit;
end
endmodule |
module oc8051_comp (sel, b_in, cy, acc, des, /*comp_wait, */eq);
//
// sel (in) select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
// b_in (in) bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
// cy (in) carry flag [oc8051_psw.data_out[7] ]
// acc (in) accumulator [oc8051_acc.data_out]
// ram (in) input from ram [oc8051_ram_sel.out_data]
// op2 (in) immediate data [oc8051_op_select.op2_out -r]
// des (in) destination from alu [oc8051_alu.des1 -r]
// eq (out) if (src1 == src2) eq = 1 [oc8051_decoder.eq]
//
input [1:0] sel;
input b_in, cy/*, comp_wait*/;
input [7:0] acc, des;
output eq;
reg eq_r;
assign eq = eq_r;// & comp_wait;
always @(sel or b_in or cy or acc or des)
begin
case (sel) /* synopsys full_case parallel_case */
`OC8051_CSS_AZ : eq_r = (acc == 8'h00);
`OC8051_CSS_DES : eq_r = (des == 8'h00);
`OC8051_CSS_CY : eq_r = cy;
`OC8051_CSS_BIT : eq_r = b_in;
endcase
end
endmodule |
module oc8051_wb_iinterface(rst, clk,
adr_i, dat_o, cyc_i, stb_i, ack_o,
adr_o, dat_i, cyc_o, stb_o, ack_i
);
//
// rst (in) reset - pin
// clk (in) clock - pini
input rst, clk;
//
// interface to oc8051 cpu
//
// adr_i (in) address
// dat_o (out) data output
// stb_i (in) strobe
// ack_o (out) acknowledge
// cyc_i (in) cycle
input stb_i,
cyc_i;
input [15:0] adr_i;
output ack_o;
output [31:0] dat_o;
//
// interface to instruction rom
//
// adr_o (out) address
// dat_i (in) data input
// stb_o (out) strobe
// ack_i (in) acknowledge
// cyc_o (out) cycle
input ack_i;
input [31:0] dat_i;
output stb_o,
cyc_o;
output [15:0] adr_o;
//
// internal bufers and wires
//
reg [15:0] adr_o;
reg stb_o;
assign ack_o = ack_i;
assign dat_o = dat_i;
//assign stb_o = stb_i || ack_i;
assign cyc_o = stb_o;
//assign adr_o = ack_i ? adr : adr_i;
always @(posedge clk or posedge rst)
if (rst) begin
stb_o <= #1 1'b0;
adr_o <= #1 16'h0000;
end else if (ack_i) begin
stb_o <= #1 stb_i;
adr_o <= #1 adr_i;
end else if (!stb_o & stb_i) begin
stb_o <= #1 1'b1;
adr_o <= #1 adr_i;
end
endmodule |
module oc8051_ram_256x8_two_bist (
clk,
rst,
rd_addr,
rd_data,
rd_en,
wr_addr,
wr_data,
wr_en,
wr
`ifdef OC8051_BIST
,
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en
`endif
);
input clk,
wr,
rst,
rd_en,
wr_en;
input [7:0] wr_data;
input [7:0] rd_addr,
wr_addr;
output [7:0] rd_data;
`ifdef OC8051_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
`endif
`ifdef OC8051_RAM_XILINX
xilinx_ram_dp xilinx_ram(
// read port
.CLKA(clk),
.RSTA(rst),
.ENA(rd_en),
.ADDRA(rd_addr),
.DIA(8'h00),
.WEA(1'b0),
.DOA(rd_data),
// write port
.CLKB(clk),
.RSTB(rst),
.ENB(wr_en),
.ADDRB(wr_addr),
.DIB(wr_data),
.WEB(wr),
.DOB()
);
defparam
xilinx_ram.dwidth = 8,
xilinx_ram.awidth = 8;
`else
`ifdef OC8051_RAM_VIRTUALSILICON
`else
`ifdef OC8051_RAM_GENERIC
generic_dpram #(8, 8) oc8051_ram1(
.rclk ( clk ),
.rrst ( rst ),
.rce ( rd_en ),
.oe ( 1'b1 ),
.raddr ( rd_addr ),
.do ( rd_data ),
.wclk ( clk ),
.wrst ( rst ),
.wce ( wr_en ),
.we ( wr ),
.waddr ( wr_addr ),
.di ( wr_data )
);
`else
reg [7:0] rd_data;
//
// buffer
reg [7:0] buff [0:256];
//
// writing to ram
always @(posedge clk)
begin
if (wr)
buff[wr_addr] <= #1 wr_data;
end
//
// reading from ram
always @(posedge clk or posedge rst)
begin
if (rst)
rd_data <= #1 8'h0;
else if ((wr_addr==rd_addr) & wr & rd_en)
rd_data <= #1 wr_data;
else if (rd_en)
rd_data <= #1 buff[rd_addr];
end
`endif //OC8051_RAM_GENERIC
`endif //OC8051_RAM_VIRTUALSILICON
`endif //OC8051_RAM_XILINX
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 7;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h02;
buff [16'h00_01] = 8'h00;
buff [16'h00_02] = 8'h2E;
buff [16'h00_03] = 8'h7D;
buff [16'h00_04] = 8'hAA;
buff [16'h00_05] = 8'hE4;
buff [16'h00_06] = 8'hFC;
buff [16'h00_07] = 8'h74;
buff [16'h00_08] = 8'h01;
buff [16'h00_09] = 8'h7E;
buff [16'h00_0a] = 8'h00;
buff [16'h00_0b] = 8'hA8;
buff [16'h00_0c] = 8'h04;
buff [16'h00_0d] = 8'h08;
buff [16'h00_0e] = 8'h80;
buff [16'h00_0f] = 8'h05;
buff [16'h00_10] = 8'hC3;
buff [16'h00_11] = 8'h33;
buff [16'h00_12] = 8'hCE;
buff [16'h00_13] = 8'h33;
buff [16'h00_14] = 8'hCE;
buff [16'h00_15] = 8'hD8;
buff [16'h00_16] = 8'hF9;
buff [16'h00_17] = 8'hFF;
buff [16'h00_18] = 8'hED;
buff [16'h00_19] = 8'hFB;
buff [16'h00_1a] = 8'hE4;
buff [16'h00_1b] = 8'hEF;
buff [16'h00_1c] = 8'h5B;
buff [16'h00_1d] = 8'h60;
buff [16'h00_1e] = 8'h04;
buff [16'h00_1f] = 8'h7F;
buff [16'h00_20] = 8'h01;
buff [16'h00_21] = 8'h80;
buff [16'h00_22] = 8'h02;
buff [16'h00_23] = 8'h7F;
buff [16'h00_24] = 8'h00;
buff [16'h00_25] = 8'h8F;
buff [16'h00_26] = 8'h80;
buff [16'h00_27] = 8'h0C;
buff [16'h00_28] = 8'hBC;
buff [16'h00_29] = 8'h08;
buff [16'h00_2a] = 8'hDC;
buff [16'h00_2b] = 8'h80;
buff [16'h00_2c] = 8'hFE;
buff [16'h00_2d] = 8'h22;
buff [16'h00_2e] = 8'h78;
buff [16'h00_2f] = 8'h7F;
buff [16'h00_30] = 8'hE4;
buff [16'h00_31] = 8'hF6;
buff [16'h00_32] = 8'hD8;
buff [16'h00_33] = 8'hFD;
buff [16'h00_34] = 8'h75;
buff [16'h00_35] = 8'h81;
buff [16'h00_36] = 8'h07;
buff [16'h00_37] = 8'h02;
buff [16'h00_38] = 8'h00;
buff [16'h00_39] = 8'h03;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 10;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h02;
buff [16'h00_01] = 8'h00;
buff [16'h00_02] = 8'hCA;
buff [16'h00_03] = 8'h8B;
buff [16'h00_04] = 8'h12;
buff [16'h00_05] = 8'h8A;
buff [16'h00_06] = 8'h13;
buff [16'h00_07] = 8'h89;
buff [16'h00_08] = 8'h14;
buff [16'h00_09] = 8'h8D;
buff [16'h00_0a] = 8'h15;
buff [16'h00_0b] = 8'hE4;
buff [16'h00_0c] = 8'hFF;
buff [16'h00_0d] = 8'hEF;
buff [16'h00_0e] = 8'hC3;
buff [16'h00_0f] = 8'h95;
buff [16'h00_10] = 8'h15;
buff [16'h00_11] = 8'h50;
buff [16'h00_12] = 8'h46;
buff [16'h00_13] = 8'hAE;
buff [16'h00_14] = 8'h07;
buff [16'h00_15] = 8'hEE;
buff [16'h00_16] = 8'hC3;
buff [16'h00_17] = 8'h95;
buff [16'h00_18] = 8'h15;
buff [16'h00_19] = 8'h50;
buff [16'h00_1a] = 8'h3B;
buff [16'h00_1b] = 8'hAB;
buff [16'h00_1c] = 8'h12;
buff [16'h00_1d] = 8'hAA;
buff [16'h00_1e] = 8'h13;
buff [16'h00_1f] = 8'hA9;
buff [16'h00_20] = 8'h14;
buff [16'h00_21] = 8'h8E;
buff [16'h00_22] = 8'h82;
buff [16'h00_23] = 8'h75;
buff [16'h00_24] = 8'h83;
buff [16'h00_25] = 8'h00;
buff [16'h00_26] = 8'h12;
buff [16'h00_27] = 8'h01;
buff [16'h00_28] = 8'hCF;
buff [16'h00_29] = 8'hFD;
buff [16'h00_2a] = 8'h8F;
buff [16'h00_2b] = 8'h82;
buff [16'h00_2c] = 8'h75;
buff [16'h00_2d] = 8'h83;
buff [16'h00_2e] = 8'h00;
buff [16'h00_2f] = 8'h12;
buff [16'h00_30] = 8'h01;
buff [16'h00_31] = 8'hCF;
buff [16'h00_32] = 8'hFC;
buff [16'h00_33] = 8'hD3;
buff [16'h00_34] = 8'h9D;
buff [16'h00_35] = 8'h40;
buff [16'h00_36] = 8'h1C;
buff [16'h00_37] = 8'h8C;
buff [16'h00_38] = 8'h16;
buff [16'h00_39] = 8'h8E;
buff [16'h00_3a] = 8'h82;
buff [16'h00_3b] = 8'h75;
buff [16'h00_3c] = 8'h83;
buff [16'h00_3d] = 8'h00;
buff [16'h00_3e] = 8'h12;
buff [16'h00_3f] = 8'h01;
buff [16'h00_40] = 8'hCF;
buff [16'h00_41] = 8'h8F;
buff [16'h00_42] = 8'h82;
buff [16'h00_43] = 8'h75;
buff [16'h00_44] = 8'h83;
buff [16'h00_45] = 8'h00;
buff [16'h00_46] = 8'h12;
buff [16'h00_47] = 8'h01;
buff [16'h00_48] = 8'hFC;
buff [16'h00_49] = 8'h8E;
buff [16'h00_4a] = 8'h82;
buff [16'h00_4b] = 8'h75;
buff [16'h00_4c] = 8'h83;
buff [16'h00_4d] = 8'h00;
buff [16'h00_4e] = 8'hE5;
buff [16'h00_4f] = 8'h16;
buff [16'h00_50] = 8'h12;
buff [16'h00_51] = 8'h01;
buff [16'h00_52] = 8'hFC;
buff [16'h00_53] = 8'h0E;
buff [16'h00_54] = 8'h80;
buff [16'h00_55] = 8'hBF;
buff [16'h00_56] = 8'h0F;
buff [16'h00_57] = 8'h80;
buff [16'h00_58] = 8'hB4;
buff [16'h00_59] = 8'hE4;
buff [16'h00_5a] = 8'hF5;
buff [16'h00_5b] = 8'h80;
buff [16'h00_5c] = 8'h22;
buff [16'h00_5d] = 8'h8B;
buff [16'h00_5e] = 8'h12;
buff [16'h00_5f] = 8'h8A;
buff [16'h00_60] = 8'h13;
buff [16'h00_61] = 8'h89;
buff [16'h00_62] = 8'h14;
buff [16'h00_63] = 8'h8D;
buff [16'h00_64] = 8'h15;
buff [16'h00_65] = 8'hE4;
buff [16'h00_66] = 8'hF5;
buff [16'h00_67] = 8'h16;
buff [16'h00_68] = 8'hAD;
buff [16'h00_69] = 8'h16;
buff [16'h00_6a] = 8'hED;
buff [16'h00_6b] = 8'h33;
buff [16'h00_6c] = 8'h95;
buff [16'h00_6d] = 8'hE0;
buff [16'h00_6e] = 8'hFC;
buff [16'h00_6f] = 8'hC3;
buff [16'h00_70] = 8'hED;
buff [16'h00_71] = 8'h95;
buff [16'h00_72] = 8'h15;
buff [16'h00_73] = 8'h74;
buff [16'h00_74] = 8'h80;
buff [16'h00_75] = 8'hF8;
buff [16'h00_76] = 8'h6C;
buff [16'h00_77] = 8'h98;
buff [16'h00_78] = 8'h50;
buff [16'h00_79] = 8'h19;
buff [16'h00_7a] = 8'hAB;
buff [16'h00_7b] = 8'h12;
buff [16'h00_7c] = 8'hAA;
buff [16'h00_7d] = 8'h13;
buff [16'h00_7e] = 8'hA9;
buff [16'h00_7f] = 8'h14;
buff [16'h00_80] = 8'hAF;
buff [16'h00_81] = 8'h16;
buff [16'h00_82] = 8'hEF;
buff [16'h00_83] = 8'h33;
buff [16'h00_84] = 8'h95;
buff [16'h00_85] = 8'hE0;
buff [16'h00_86] = 8'h8F;
buff [16'h00_87] = 8'h82;
buff [16'h00_88] = 8'hF5;
buff [16'h00_89] = 8'h83;
buff [16'h00_8a] = 8'h12;
buff [16'h00_8b] = 8'h01;
buff [16'h00_8c] = 8'hCF;
buff [16'h00_8d] = 8'hF5;
buff [16'h00_8e] = 8'h80;
buff [16'h00_8f] = 8'h05;
buff [16'h00_90] = 8'h16;
buff [16'h00_91] = 8'h80;
buff [16'h00_92] = 8'hD5;
buff [16'h00_93] = 8'h22;
buff [16'h00_94] = 8'h78;
buff [16'h00_95] = 8'h08;
buff [16'h00_96] = 8'h7C;
buff [16'h00_97] = 8'h00;
buff [16'h00_98] = 8'h7D;
buff [16'h00_99] = 8'h00;
buff [16'h00_9a] = 8'h7B;
buff [16'h00_9b] = 8'hFF;
buff [16'h00_9c] = 8'h7A;
buff [16'h00_9d] = 8'h00;
buff [16'h00_9e] = 8'h79;
buff [16'h00_9f] = 8'hC0;
buff [16'h00_a0] = 8'h7E;
buff [16'h00_a1] = 8'h00;
buff [16'h00_a2] = 8'h7F;
buff [16'h00_a3] = 8'h0A;
buff [16'h00_a4] = 8'h12;
buff [16'h00_a5] = 8'h01;
buff [16'h00_a6] = 8'hA6;
buff [16'h00_a7] = 8'h7B;
buff [16'h00_a8] = 8'h00;
buff [16'h00_a9] = 8'h7A;
buff [16'h00_aa] = 8'h00;
buff [16'h00_ab] = 8'h79;
buff [16'h00_ac] = 8'h08;
buff [16'h00_ad] = 8'h7D;
buff [16'h00_ae] = 8'h0A;
buff [16'h00_af] = 8'h12;
buff [16'h00_b0] = 8'h00;
buff [16'h00_b1] = 8'h03;
buff [16'h00_b2] = 8'h7B;
buff [16'h00_b3] = 8'h00;
buff [16'h00_b4] = 8'h7A;
buff [16'h00_b5] = 8'h00;
buff [16'h00_b6] = 8'h79;
buff [16'h00_b7] = 8'h08;
buff [16'h00_b8] = 8'h7D;
buff [16'h00_b9] = 8'h0A;
buff [16'h00_ba] = 8'h12;
buff [16'h00_bb] = 8'h00;
buff [16'h00_bc] = 8'h5D;
buff [16'h00_bd] = 8'h80;
buff [16'h00_be] = 8'hFE;
buff [16'h00_bf] = 8'h22;
buff [16'h00_c0] = 8'h13;
buff [16'h00_c1] = 8'h12;
buff [16'h00_c2] = 8'h11;
buff [16'h00_c3] = 8'h10;
buff [16'h00_c4] = 8'h0F;
buff [16'h00_c5] = 8'h0E;
buff [16'h00_c6] = 8'h0D;
buff [16'h00_c7] = 8'h0C;
buff [16'h00_c8] = 8'h0B;
buff [16'h00_c9] = 8'h0A;
buff [16'h00_ca] = 8'h78;
buff [16'h00_cb] = 8'h7F;
buff [16'h00_cc] = 8'hE4;
buff [16'h00_cd] = 8'hF6;
buff [16'h00_ce] = 8'hD8;
buff [16'h00_cf] = 8'hFD;
buff [16'h00_d0] = 8'h75;
buff [16'h00_d1] = 8'h81;
buff [16'h00_d2] = 8'h16;
buff [16'h00_d3] = 8'h02;
buff [16'h00_d4] = 8'h00;
buff [16'h00_d5] = 8'h94;
buff [16'h00_d6] = 8'hE7;
buff [16'h00_d7] = 8'h09;
buff [16'h00_d8] = 8'hF6;
buff [16'h00_d9] = 8'h08;
buff [16'h00_da] = 8'hDF;
buff [16'h00_db] = 8'hFA;
buff [16'h00_dc] = 8'h80;
buff [16'h00_dd] = 8'h46;
buff [16'h00_de] = 8'hE7;
buff [16'h00_df] = 8'h09;
buff [16'h00_e0] = 8'hF2;
buff [16'h00_e1] = 8'h08;
buff [16'h00_e2] = 8'hDF;
buff [16'h00_e3] = 8'hFA;
buff [16'h00_e4] = 8'h80;
buff [16'h00_e5] = 8'h3E;
buff [16'h00_e6] = 8'h88;
buff [16'h00_e7] = 8'h82;
buff [16'h00_e8] = 8'h8C;
buff [16'h00_e9] = 8'h83;
buff [16'h00_ea] = 8'hE7;
buff [16'h00_eb] = 8'h09;
buff [16'h00_ec] = 8'hF0;
buff [16'h00_ed] = 8'hA3;
buff [16'h00_ee] = 8'hDF;
buff [16'h00_ef] = 8'hFA;
buff [16'h00_f0] = 8'h80;
buff [16'h00_f1] = 8'h32;
buff [16'h00_f2] = 8'hE3;
buff [16'h00_f3] = 8'h09;
buff [16'h00_f4] = 8'hF6;
buff [16'h00_f5] = 8'h08;
buff [16'h00_f6] = 8'hDF;
buff [16'h00_f7] = 8'hFA;
buff [16'h00_f8] = 8'h80;
buff [16'h00_f9] = 8'h78;
buff [16'h00_fa] = 8'hE3;
buff [16'h00_fb] = 8'h09;
buff [16'h00_fc] = 8'hF2;
buff [16'h00_fd] = 8'h08;
buff [16'h00_fe] = 8'hDF;
buff [16'h00_ff] = 8'hFA;
buff [16'h01_00] = 8'h80;
buff [16'h01_01] = 8'h70;
buff [16'h01_02] = 8'h88;
buff [16'h01_03] = 8'h82;
buff [16'h01_04] = 8'h8C;
buff [16'h01_05] = 8'h83;
buff [16'h01_06] = 8'hE3;
buff [16'h01_07] = 8'h09;
buff [16'h01_08] = 8'hF0;
buff [16'h01_09] = 8'hA3;
buff [16'h01_0a] = 8'hDF;
buff [16'h01_0b] = 8'hFA;
buff [16'h01_0c] = 8'h80;
buff [16'h01_0d] = 8'h64;
buff [16'h01_0e] = 8'h89;
buff [16'h01_0f] = 8'h82;
buff [16'h01_10] = 8'h8A;
buff [16'h01_11] = 8'h83;
buff [16'h01_12] = 8'hE0;
buff [16'h01_13] = 8'hA3;
buff [16'h01_14] = 8'hF6;
buff [16'h01_15] = 8'h08;
buff [16'h01_16] = 8'hDF;
buff [16'h01_17] = 8'hFA;
buff [16'h01_18] = 8'h80;
buff [16'h01_19] = 8'h58;
buff [16'h01_1a] = 8'h89;
buff [16'h01_1b] = 8'h82;
buff [16'h01_1c] = 8'h8A;
buff [16'h01_1d] = 8'h83;
buff [16'h01_1e] = 8'hE0;
buff [16'h01_1f] = 8'hA3;
buff [16'h01_20] = 8'hF2;
buff [16'h01_21] = 8'h08;
buff [16'h01_22] = 8'hDF;
buff [16'h01_23] = 8'hFA;
buff [16'h01_24] = 8'h80;
buff [16'h01_25] = 8'h4C;
buff [16'h01_26] = 8'h80;
buff [16'h01_27] = 8'hD2;
buff [16'h01_28] = 8'h80;
buff [16'h01_29] = 8'hFA;
buff [16'h01_2a] = 8'h80;
buff [16'h01_2b] = 8'hC6;
buff [16'h01_2c] = 8'h80;
buff [16'h01_2d] = 8'hD4;
buff [16'h01_2e] = 8'h80;
buff [16'h01_2f] = 8'h69;
buff [16'h01_30] = 8'h80;
buff [16'h01_31] = 8'hF2;
buff [16'h01_32] = 8'h80;
buff [16'h01_33] = 8'h33;
buff [16'h01_34] = 8'h80;
buff [16'h01_35] = 8'h10;
buff [16'h01_36] = 8'h80;
buff [16'h01_37] = 8'hA6;
buff [16'h01_38] = 8'h80;
buff [16'h01_39] = 8'hEA;
buff [16'h01_3a] = 8'h80;
buff [16'h01_3b] = 8'h9A;
buff [16'h01_3c] = 8'h80;
buff [16'h01_3d] = 8'hA8;
buff [16'h01_3e] = 8'h80;
buff [16'h01_3f] = 8'hDA;
buff [16'h01_40] = 8'h80;
buff [16'h01_41] = 8'hE2;
buff [16'h01_42] = 8'h80;
buff [16'h01_43] = 8'hCA;
buff [16'h01_44] = 8'h80;
buff [16'h01_45] = 8'h33;
buff [16'h01_46] = 8'h89;
buff [16'h01_47] = 8'h82;
buff [16'h01_48] = 8'h8A;
buff [16'h01_49] = 8'h83;
buff [16'h01_4a] = 8'hEC;
buff [16'h01_4b] = 8'hFA;
buff [16'h01_4c] = 8'hE4;
buff [16'h01_4d] = 8'h93;
buff [16'h01_4e] = 8'hA3;
buff [16'h01_4f] = 8'hC8;
buff [16'h01_50] = 8'hC5;
buff [16'h01_51] = 8'h82;
buff [16'h01_52] = 8'hC8;
buff [16'h01_53] = 8'hCC;
buff [16'h01_54] = 8'hC5;
buff [16'h01_55] = 8'h83;
buff [16'h01_56] = 8'hCC;
buff [16'h01_57] = 8'hF0;
buff [16'h01_58] = 8'hA3;
buff [16'h01_59] = 8'hC8;
buff [16'h01_5a] = 8'hC5;
buff [16'h01_5b] = 8'h82;
buff [16'h01_5c] = 8'hC8;
buff [16'h01_5d] = 8'hCC;
buff [16'h01_5e] = 8'hC5;
buff [16'h01_5f] = 8'h83;
buff [16'h01_60] = 8'hCC;
buff [16'h01_61] = 8'hDF;
buff [16'h01_62] = 8'hE9;
buff [16'h01_63] = 8'hDE;
buff [16'h01_64] = 8'hE7;
buff [16'h01_65] = 8'h80;
buff [16'h01_66] = 8'h0D;
buff [16'h01_67] = 8'h89;
buff [16'h01_68] = 8'h82;
buff [16'h01_69] = 8'h8A;
buff [16'h01_6a] = 8'h83;
buff [16'h01_6b] = 8'hE4;
buff [16'h01_6c] = 8'h93;
buff [16'h01_6d] = 8'hA3;
buff [16'h01_6e] = 8'hF6;
buff [16'h01_6f] = 8'h08;
buff [16'h01_70] = 8'hDF;
buff [16'h01_71] = 8'hF9;
buff [16'h01_72] = 8'hEC;
buff [16'h01_73] = 8'hFA;
buff [16'h01_74] = 8'hA9;
buff [16'h01_75] = 8'hF0;
buff [16'h01_76] = 8'hED;
buff [16'h01_77] = 8'hFB;
buff [16'h01_78] = 8'h22;
buff [16'h01_79] = 8'h89;
buff [16'h01_7a] = 8'h82;
buff [16'h01_7b] = 8'h8A;
buff [16'h01_7c] = 8'h83;
buff [16'h01_7d] = 8'hEC;
buff [16'h01_7e] = 8'hFA;
buff [16'h01_7f] = 8'hE0;
buff [16'h01_80] = 8'hA3;
buff [16'h01_81] = 8'hC8;
buff [16'h01_82] = 8'hC5;
buff [16'h01_83] = 8'h82;
buff [16'h01_84] = 8'hC8;
buff [16'h01_85] = 8'hCC;
buff [16'h01_86] = 8'hC5;
buff [16'h01_87] = 8'h83;
buff [16'h01_88] = 8'hCC;
buff [16'h01_89] = 8'hF0;
buff [16'h01_8a] = 8'hA3;
buff [16'h01_8b] = 8'hC8;
buff [16'h01_8c] = 8'hC5;
buff [16'h01_8d] = 8'h82;
buff [16'h01_8e] = 8'hC8;
buff [16'h01_8f] = 8'hCC;
buff [16'h01_90] = 8'hC5;
buff [16'h01_91] = 8'h83;
buff [16'h01_92] = 8'hCC;
buff [16'h01_93] = 8'hDF;
buff [16'h01_94] = 8'hEA;
buff [16'h01_95] = 8'hDE;
buff [16'h01_96] = 8'hE8;
buff [16'h01_97] = 8'h80;
buff [16'h01_98] = 8'hDB;
buff [16'h01_99] = 8'h89;
buff [16'h01_9a] = 8'h82;
buff [16'h01_9b] = 8'h8A;
buff [16'h01_9c] = 8'h83;
buff [16'h01_9d] = 8'hE4;
buff [16'h01_9e] = 8'h93;
buff [16'h01_9f] = 8'hA3;
buff [16'h01_a0] = 8'hF2;
buff [16'h01_a1] = 8'h08;
buff [16'h01_a2] = 8'hDF;
buff [16'h01_a3] = 8'hF9;
buff [16'h01_a4] = 8'h80;
buff [16'h01_a5] = 8'hCC;
buff [16'h01_a6] = 8'h88;
buff [16'h01_a7] = 8'hF0;
buff [16'h01_a8] = 8'hED;
buff [16'h01_a9] = 8'h24;
buff [16'h01_aa] = 8'h02;
buff [16'h01_ab] = 8'hB4;
buff [16'h01_ac] = 8'h04;
buff [16'h01_ad] = 8'h00;
buff [16'h01_ae] = 8'h50;
buff [16'h01_af] = 8'hC2;
buff [16'h01_b0] = 8'hF5;
buff [16'h01_b1] = 8'h82;
buff [16'h01_b2] = 8'hEB;
buff [16'h01_b3] = 8'h24;
buff [16'h01_b4] = 8'h02;
buff [16'h01_b5] = 8'hB4;
buff [16'h01_b6] = 8'h04;
buff [16'h01_b7] = 8'h00;
buff [16'h01_b8] = 8'h50;
buff [16'h01_b9] = 8'hB8;
buff [16'h01_ba] = 8'h23;
buff [16'h01_bb] = 8'h23;
buff [16'h01_bc] = 8'h45;
buff [16'h01_bd] = 8'h82;
buff [16'h01_be] = 8'hF5;
buff [16'h01_bf] = 8'h82;
buff [16'h01_c0] = 8'hEF;
buff [16'h01_c1] = 8'h4E;
buff [16'h01_c2] = 8'h60;
buff [16'h01_c3] = 8'hAE;
buff [16'h01_c4] = 8'hEF;
buff [16'h01_c5] = 8'h60;
buff [16'h01_c6] = 8'h01;
buff [16'h01_c7] = 8'h0E;
buff [16'h01_c8] = 8'hE5;
buff [16'h01_c9] = 8'h82;
buff [16'h01_ca] = 8'h23;
buff [16'h01_cb] = 8'h90;
buff [16'h01_cc] = 8'h01;
buff [16'h01_cd] = 8'h26;
buff [16'h01_ce] = 8'h73;
buff [16'h01_cf] = 8'hBB;
buff [16'h01_d0] = 8'h01;
buff [16'h01_d1] = 8'h0C;
buff [16'h01_d2] = 8'hE5;
buff [16'h01_d3] = 8'h82;
buff [16'h01_d4] = 8'h29;
buff [16'h01_d5] = 8'hF5;
buff [16'h01_d6] = 8'h82;
buff [16'h01_d7] = 8'hE5;
buff [16'h01_d8] = 8'h83;
buff [16'h01_d9] = 8'h3A;
buff [16'h01_da] = 8'hF5;
buff [16'h01_db] = 8'h83;
buff [16'h01_dc] = 8'hE0;
buff [16'h01_dd] = 8'h22;
buff [16'h01_de] = 8'h50;
buff [16'h01_df] = 8'h06;
buff [16'h01_e0] = 8'hE9;
buff [16'h01_e1] = 8'h25;
buff [16'h01_e2] = 8'h82;
buff [16'h01_e3] = 8'hF8;
buff [16'h01_e4] = 8'hE6;
buff [16'h01_e5] = 8'h22;
buff [16'h01_e6] = 8'hBB;
buff [16'h01_e7] = 8'hFE;
buff [16'h01_e8] = 8'h06;
buff [16'h01_e9] = 8'hE9;
buff [16'h01_ea] = 8'h25;
buff [16'h01_eb] = 8'h82;
buff [16'h01_ec] = 8'hF8;
buff [16'h01_ed] = 8'hE2;
buff [16'h01_ee] = 8'h22;
buff [16'h01_ef] = 8'hE5;
buff [16'h01_f0] = 8'h82;
buff [16'h01_f1] = 8'h29;
buff [16'h01_f2] = 8'hF5;
buff [16'h01_f3] = 8'h82;
buff [16'h01_f4] = 8'hE5;
buff [16'h01_f5] = 8'h83;
buff [16'h01_f6] = 8'h3A;
buff [16'h01_f7] = 8'hF5;
buff [16'h01_f8] = 8'h83;
buff [16'h01_f9] = 8'hE4;
buff [16'h01_fa] = 8'h93;
buff [16'h01_fb] = 8'h22;
buff [16'h01_fc] = 8'hF8;
buff [16'h01_fd] = 8'hBB;
buff [16'h01_fe] = 8'h01;
buff [16'h01_ff] = 8'h0D;
buff [16'h02_00] = 8'hE5;
buff [16'h02_01] = 8'h82;
buff [16'h02_02] = 8'h29;
buff [16'h02_03] = 8'hF5;
buff [16'h02_04] = 8'h82;
buff [16'h02_05] = 8'hE5;
buff [16'h02_06] = 8'h83;
buff [16'h02_07] = 8'h3A;
buff [16'h02_08] = 8'hF5;
buff [16'h02_09] = 8'h83;
buff [16'h02_0a] = 8'hE8;
buff [16'h02_0b] = 8'hF0;
buff [16'h02_0c] = 8'h22;
buff [16'h02_0d] = 8'h50;
buff [16'h02_0e] = 8'h06;
buff [16'h02_0f] = 8'hE9;
buff [16'h02_10] = 8'h25;
buff [16'h02_11] = 8'h82;
buff [16'h02_12] = 8'hC8;
buff [16'h02_13] = 8'hF6;
buff [16'h02_14] = 8'h22;
buff [16'h02_15] = 8'hBB;
buff [16'h02_16] = 8'hFE;
buff [16'h02_17] = 8'h05;
buff [16'h02_18] = 8'hE9;
buff [16'h02_19] = 8'h25;
buff [16'h02_1a] = 8'h82;
buff [16'h02_1b] = 8'hC8;
buff [16'h02_1c] = 8'hF2;
buff [16'h02_1d] = 8'h22;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 7;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h02;
buff [16'h00_01] = 8'h00;
buff [16'h00_02] = 8'h25;
buff [16'h00_03] = 8'h7F;
buff [16'h00_04] = 8'h2F;
buff [16'h00_05] = 8'h7E;
buff [16'h00_06] = 8'h0B;
buff [16'h00_07] = 8'hEF;
buff [16'h00_08] = 8'h6E;
buff [16'h00_09] = 8'h60;
buff [16'h00_0a] = 8'h15;
buff [16'h00_0b] = 8'hEF;
buff [16'h00_0c] = 8'hD3;
buff [16'h00_0d] = 8'h9E;
buff [16'h00_0e] = 8'h40;
buff [16'h00_0f] = 8'h08;
buff [16'h00_10] = 8'hC3;
buff [16'h00_11] = 8'hEF;
buff [16'h00_12] = 8'h9E;
buff [16'h00_13] = 8'hFF;
buff [16'h00_14] = 8'hF5;
buff [16'h00_15] = 8'h80;
buff [16'h00_16] = 8'h80;
buff [16'h00_17] = 8'hEF;
buff [16'h00_18] = 8'hC3;
buff [16'h00_19] = 8'hEE;
buff [16'h00_1a] = 8'h9F;
buff [16'h00_1b] = 8'hFE;
buff [16'h00_1c] = 8'hF5;
buff [16'h00_1d] = 8'h90;
buff [16'h00_1e] = 8'h80;
buff [16'h00_1f] = 8'hE7;
buff [16'h00_20] = 8'h8F;
buff [16'h00_21] = 8'hA0;
buff [16'h00_22] = 8'h80;
buff [16'h00_23] = 8'hFE;
buff [16'h00_24] = 8'h22;
buff [16'h00_25] = 8'h78;
buff [16'h00_26] = 8'h7F;
buff [16'h00_27] = 8'hE4;
buff [16'h00_28] = 8'hF6;
buff [16'h00_29] = 8'hD8;
buff [16'h00_2a] = 8'hFD;
buff [16'h00_2b] = 8'h75;
buff [16'h00_2c] = 8'h81;
buff [16'h00_2d] = 8'h07;
buff [16'h00_2e] = 8'h02;
buff [16'h00_2f] = 8'h00;
buff [16'h00_30] = 8'h03;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 7;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h7D;
buff [16'h00_01] = 8'hA1;
buff [16'h00_02] = 8'h7C;
buff [16'h00_03] = 8'h54;
buff [16'h00_04] = 8'h79;
buff [16'h00_05] = 8'h01;
buff [16'h00_06] = 8'h78;
buff [16'h00_07] = 8'h70;
buff [16'h00_08] = 8'h12;
buff [16'h00_09] = 8'h00;
buff [16'h00_0a] = 8'h13;
buff [16'h00_0b] = 8'h8D;
buff [16'h00_0c] = 8'h80;
buff [16'h00_0d] = 8'h8C;
buff [16'h00_0e] = 8'h80;
buff [16'h00_0f] = 8'h89;
buff [16'h00_10] = 8'h80;
buff [16'h00_11] = 8'h88;
buff [16'h00_12] = 8'h80;
buff [16'h00_13] = 8'hE4;
buff [16'h00_14] = 8'hFA;
buff [16'h00_15] = 8'hFB;
buff [16'h00_16] = 8'h75;
buff [16'h00_17] = 8'hF0;
buff [16'h00_18] = 8'h01;
buff [16'h00_19] = 8'hE9;
buff [16'h00_1a] = 8'h48;
buff [16'h00_1b] = 8'h60;
buff [16'h00_1c] = 8'h53;
buff [16'h00_1d] = 8'hED;
buff [16'h00_1e] = 8'h4C;
buff [16'h00_1f] = 8'h70;
buff [16'h00_20] = 8'h04;
buff [16'h00_21] = 8'hFF;
buff [16'h00_22] = 8'hFE;
buff [16'h00_23] = 8'h01;
buff [16'h00_24] = 8'h6E;
buff [16'h00_25] = 8'hE9;
buff [16'h00_26] = 8'h33;
buff [16'h00_27] = 8'h40;
buff [16'h00_28] = 8'h16;
buff [16'h00_29] = 8'hC3;
buff [16'h00_2a] = 8'hED;
buff [16'h00_2b] = 8'h99;
buff [16'h00_2c] = 8'h40;
buff [16'h00_2d] = 8'h11;
buff [16'h00_2e] = 8'h70;
buff [16'h00_2f] = 8'h04;
buff [16'h00_30] = 8'hEC;
buff [16'h00_31] = 8'h98;
buff [16'h00_32] = 8'h40;
buff [16'h00_33] = 8'h0B;
buff [16'h00_34] = 8'hC3;
buff [16'h00_35] = 8'hE8;
buff [16'h00_36] = 8'h33;
buff [16'h00_37] = 8'hF8;
buff [16'h00_38] = 8'hE9;
buff [16'h00_39] = 8'h33;
buff [16'h00_3a] = 8'hF9;
buff [16'h00_3b] = 8'h05;
buff [16'h00_3c] = 8'hF0;
buff [16'h00_3d] = 8'h80;
buff [16'h00_3e] = 8'hE6;
buff [16'h00_3f] = 8'hC3;
buff [16'h00_40] = 8'hED;
buff [16'h00_41] = 8'h99;
buff [16'h00_42] = 8'h40;
buff [16'h00_43] = 8'h11;
buff [16'h00_44] = 8'h70;
buff [16'h00_45] = 8'h04;
buff [16'h00_46] = 8'hEC;
buff [16'h00_47] = 8'h98;
buff [16'h00_48] = 8'h40;
buff [16'h00_49] = 8'h0B;
buff [16'h00_4a] = 8'hEC;
buff [16'h00_4b] = 8'hC3;
buff [16'h00_4c] = 8'h98;
buff [16'h00_4d] = 8'hFC;
buff [16'h00_4e] = 8'hED;
buff [16'h00_4f] = 8'h99;
buff [16'h00_50] = 8'hFD;
buff [16'h00_51] = 8'hC3;
buff [16'h00_52] = 8'hB3;
buff [16'h00_53] = 8'h80;
buff [16'h00_54] = 8'h01;
buff [16'h00_55] = 8'hC3;
buff [16'h00_56] = 8'hEA;
buff [16'h00_57] = 8'h33;
buff [16'h00_58] = 8'hFA;
buff [16'h00_59] = 8'hEB;
buff [16'h00_5a] = 8'h33;
buff [16'h00_5b] = 8'hFB;
buff [16'h00_5c] = 8'hC3;
buff [16'h00_5d] = 8'hE9;
buff [16'h00_5e] = 8'h13;
buff [16'h00_5f] = 8'hF9;
buff [16'h00_60] = 8'hE8;
buff [16'h00_61] = 8'h13;
buff [16'h00_62] = 8'hF8;
buff [16'h00_63] = 8'hD5;
buff [16'h00_64] = 8'hF0;
buff [16'h00_65] = 8'hD9;
buff [16'h00_66] = 8'hED;
buff [16'h00_67] = 8'hFF;
buff [16'h00_68] = 8'hEC;
buff [16'h00_69] = 8'hFE;
buff [16'h00_6a] = 8'hEB;
buff [16'h00_6b] = 8'hFD;
buff [16'h00_6c] = 8'hEA;
buff [16'h00_6d] = 8'hFC;
buff [16'h00_6e] = 8'hC3;
buff [16'h00_6f] = 8'h22;
buff [16'h00_70] = 8'hC3;
buff [16'h00_71] = 8'hB3;
buff [16'h00_72] = 8'h22;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 9;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h02;
buff [16'h00_01] = 8'h00;
buff [16'h00_02] = 8'hC2;
buff [16'h00_03] = 8'h8B;
buff [16'h00_04] = 8'h12;
buff [16'h00_05] = 8'h8A;
buff [16'h00_06] = 8'h13;
buff [16'h00_07] = 8'h89;
buff [16'h00_08] = 8'h14;
buff [16'h00_09] = 8'h8D;
buff [16'h00_0a] = 8'h15;
buff [16'h00_0b] = 8'h74;
buff [16'h00_0c] = 8'h01;
buff [16'h00_0d] = 8'h12;
buff [16'h00_0e] = 8'h00;
buff [16'h00_0f] = 8'hFB;
buff [16'h00_10] = 8'hAB;
buff [16'h00_11] = 8'h12;
buff [16'h00_12] = 8'hAA;
buff [16'h00_13] = 8'h13;
buff [16'h00_14] = 8'hA9;
buff [16'h00_15] = 8'h14;
buff [16'h00_16] = 8'hF5;
buff [16'h00_17] = 8'h82;
buff [16'h00_18] = 8'h75;
buff [16'h00_19] = 8'h83;
buff [16'h00_1a] = 8'h00;
buff [16'h00_1b] = 8'h12;
buff [16'h00_1c] = 8'h01;
buff [16'h00_1d] = 8'h0D;
buff [16'h00_1e] = 8'h75;
buff [16'h00_1f] = 8'h16;
buff [16'h00_20] = 8'h02;
buff [16'h00_21] = 8'hAD;
buff [16'h00_22] = 8'h16;
buff [16'h00_23] = 8'hED;
buff [16'h00_24] = 8'h33;
buff [16'h00_25] = 8'h95;
buff [16'h00_26] = 8'hE0;
buff [16'h00_27] = 8'hFC;
buff [16'h00_28] = 8'hC3;
buff [16'h00_29] = 8'hED;
buff [16'h00_2a] = 8'h95;
buff [16'h00_2b] = 8'h15;
buff [16'h00_2c] = 8'h74;
buff [16'h00_2d] = 8'h80;
buff [16'h00_2e] = 8'hF8;
buff [16'h00_2f] = 8'h6C;
buff [16'h00_30] = 8'h98;
buff [16'h00_31] = 8'h50;
buff [16'h00_32] = 8'h3E;
buff [16'h00_33] = 8'hAF;
buff [16'h00_34] = 8'h16;
buff [16'h00_35] = 8'hEF;
buff [16'h00_36] = 8'h33;
buff [16'h00_37] = 8'h95;
buff [16'h00_38] = 8'hE0;
buff [16'h00_39] = 8'hFE;
buff [16'h00_3a] = 8'hEF;
buff [16'h00_3b] = 8'h24;
buff [16'h00_3c] = 8'hFE;
buff [16'h00_3d] = 8'hFD;
buff [16'h00_3e] = 8'hEE;
buff [16'h00_3f] = 8'h34;
buff [16'h00_40] = 8'hFF;
buff [16'h00_41] = 8'hAB;
buff [16'h00_42] = 8'h12;
buff [16'h00_43] = 8'hAA;
buff [16'h00_44] = 8'h13;
buff [16'h00_45] = 8'hA9;
buff [16'h00_46] = 8'h14;
buff [16'h00_47] = 8'h8D;
buff [16'h00_48] = 8'h82;
buff [16'h00_49] = 8'hF5;
buff [16'h00_4a] = 8'h83;
buff [16'h00_4b] = 8'h12;
buff [16'h00_4c] = 8'h00;
buff [16'h00_4d] = 8'hCE;
buff [16'h00_4e] = 8'hFD;
buff [16'h00_4f] = 8'hEF;
buff [16'h00_50] = 8'h24;
buff [16'h00_51] = 8'hFF;
buff [16'h00_52] = 8'hFF;
buff [16'h00_53] = 8'hEE;
buff [16'h00_54] = 8'h34;
buff [16'h00_55] = 8'hFF;
buff [16'h00_56] = 8'h8F;
buff [16'h00_57] = 8'h82;
buff [16'h00_58] = 8'hF5;
buff [16'h00_59] = 8'h83;
buff [16'h00_5a] = 8'h12;
buff [16'h00_5b] = 8'h00;
buff [16'h00_5c] = 8'hCE;
buff [16'h00_5d] = 8'h2D;
buff [16'h00_5e] = 8'hFF;
buff [16'h00_5f] = 8'hE5;
buff [16'h00_60] = 8'h16;
buff [16'h00_61] = 8'hFD;
buff [16'h00_62] = 8'h33;
buff [16'h00_63] = 8'h95;
buff [16'h00_64] = 8'hE0;
buff [16'h00_65] = 8'h8D;
buff [16'h00_66] = 8'h82;
buff [16'h00_67] = 8'hF5;
buff [16'h00_68] = 8'h83;
buff [16'h00_69] = 8'hEF;
buff [16'h00_6a] = 8'h12;
buff [16'h00_6b] = 8'h01;
buff [16'h00_6c] = 8'h0D;
buff [16'h00_6d] = 8'h05;
buff [16'h00_6e] = 8'h16;
buff [16'h00_6f] = 8'h80;
buff [16'h00_70] = 8'hB0;
buff [16'h00_71] = 8'h22;
buff [16'h00_72] = 8'h8B;
buff [16'h00_73] = 8'h12;
buff [16'h00_74] = 8'h8A;
buff [16'h00_75] = 8'h13;
buff [16'h00_76] = 8'h89;
buff [16'h00_77] = 8'h14;
buff [16'h00_78] = 8'h8D;
buff [16'h00_79] = 8'h15;
buff [16'h00_7a] = 8'hE4;
buff [16'h00_7b] = 8'hF5;
buff [16'h00_7c] = 8'h16;
buff [16'h00_7d] = 8'hAD;
buff [16'h00_7e] = 8'h16;
buff [16'h00_7f] = 8'hED;
buff [16'h00_80] = 8'h33;
buff [16'h00_81] = 8'h95;
buff [16'h00_82] = 8'hE0;
buff [16'h00_83] = 8'hFC;
buff [16'h00_84] = 8'hC3;
buff [16'h00_85] = 8'hED;
buff [16'h00_86] = 8'h95;
buff [16'h00_87] = 8'h15;
buff [16'h00_88] = 8'h74;
buff [16'h00_89] = 8'h80;
buff [16'h00_8a] = 8'hF8;
buff [16'h00_8b] = 8'h6C;
buff [16'h00_8c] = 8'h98;
buff [16'h00_8d] = 8'h50;
buff [16'h00_8e] = 8'h19;
buff [16'h00_8f] = 8'hAB;
buff [16'h00_90] = 8'h12;
buff [16'h00_91] = 8'hAA;
buff [16'h00_92] = 8'h13;
buff [16'h00_93] = 8'hA9;
buff [16'h00_94] = 8'h14;
buff [16'h00_95] = 8'hAF;
buff [16'h00_96] = 8'h16;
buff [16'h00_97] = 8'hEF;
buff [16'h00_98] = 8'h33;
buff [16'h00_99] = 8'h95;
buff [16'h00_9a] = 8'hE0;
buff [16'h00_9b] = 8'h8F;
buff [16'h00_9c] = 8'h82;
buff [16'h00_9d] = 8'hF5;
buff [16'h00_9e] = 8'h83;
buff [16'h00_9f] = 8'h12;
buff [16'h00_a0] = 8'h00;
buff [16'h00_a1] = 8'hCE;
buff [16'h00_a2] = 8'hF5;
buff [16'h00_a3] = 8'h80;
buff [16'h00_a4] = 8'h05;
buff [16'h00_a5] = 8'h16;
buff [16'h00_a6] = 8'h80;
buff [16'h00_a7] = 8'hD5;
buff [16'h00_a8] = 8'h22;
buff [16'h00_a9] = 8'h7B;
buff [16'h00_aa] = 8'h00;
buff [16'h00_ab] = 8'h7A;
buff [16'h00_ac] = 8'h00;
buff [16'h00_ad] = 8'h79;
buff [16'h00_ae] = 8'h08;
buff [16'h00_af] = 8'h7D;
buff [16'h00_b0] = 8'h0A;
buff [16'h00_b1] = 8'h12;
buff [16'h00_b2] = 8'h00;
buff [16'h00_b3] = 8'h03;
buff [16'h00_b4] = 8'h7B;
buff [16'h00_b5] = 8'h00;
buff [16'h00_b6] = 8'h7A;
buff [16'h00_b7] = 8'h00;
buff [16'h00_b8] = 8'h79;
buff [16'h00_b9] = 8'h08;
buff [16'h00_ba] = 8'h7D;
buff [16'h00_bb] = 8'h0A;
buff [16'h00_bc] = 8'h12;
buff [16'h00_bd] = 8'h00;
buff [16'h00_be] = 8'h72;
buff [16'h00_bf] = 8'h80;
buff [16'h00_c0] = 8'hFE;
buff [16'h00_c1] = 8'h22;
buff [16'h00_c2] = 8'h78;
buff [16'h00_c3] = 8'h7F;
buff [16'h00_c4] = 8'hE4;
buff [16'h00_c5] = 8'hF6;
buff [16'h00_c6] = 8'hD8;
buff [16'h00_c7] = 8'hFD;
buff [16'h00_c8] = 8'h75;
buff [16'h00_c9] = 8'h81;
buff [16'h00_ca] = 8'h16;
buff [16'h00_cb] = 8'h02;
buff [16'h00_cc] = 8'h00;
buff [16'h00_cd] = 8'hA9;
buff [16'h00_ce] = 8'hBB;
buff [16'h00_cf] = 8'h01;
buff [16'h00_d0] = 8'h0C;
buff [16'h00_d1] = 8'hE5;
buff [16'h00_d2] = 8'h82;
buff [16'h00_d3] = 8'h29;
buff [16'h00_d4] = 8'hF5;
buff [16'h00_d5] = 8'h82;
buff [16'h00_d6] = 8'hE5;
buff [16'h00_d7] = 8'h83;
buff [16'h00_d8] = 8'h3A;
buff [16'h00_d9] = 8'hF5;
buff [16'h00_da] = 8'h83;
buff [16'h00_db] = 8'hE0;
buff [16'h00_dc] = 8'h22;
buff [16'h00_dd] = 8'h50;
buff [16'h00_de] = 8'h06;
buff [16'h00_df] = 8'hE9;
buff [16'h00_e0] = 8'h25;
buff [16'h00_e1] = 8'h82;
buff [16'h00_e2] = 8'hF8;
buff [16'h00_e3] = 8'hE6;
buff [16'h00_e4] = 8'h22;
buff [16'h00_e5] = 8'hBB;
buff [16'h00_e6] = 8'hFE;
buff [16'h00_e7] = 8'h06;
buff [16'h00_e8] = 8'hE9;
buff [16'h00_e9] = 8'h25;
buff [16'h00_ea] = 8'h82;
buff [16'h00_eb] = 8'hF8;
buff [16'h00_ec] = 8'hE2;
buff [16'h00_ed] = 8'h22;
buff [16'h00_ee] = 8'hE5;
buff [16'h00_ef] = 8'h82;
buff [16'h00_f0] = 8'h29;
buff [16'h00_f1] = 8'hF5;
buff [16'h00_f2] = 8'h82;
buff [16'h00_f3] = 8'hE5;
buff [16'h00_f4] = 8'h83;
buff [16'h00_f5] = 8'h3A;
buff [16'h00_f6] = 8'hF5;
buff [16'h00_f7] = 8'h83;
buff [16'h00_f8] = 8'hE4;
buff [16'h00_f9] = 8'h93;
buff [16'h00_fa] = 8'h22;
buff [16'h00_fb] = 8'hBB;
buff [16'h00_fc] = 8'h01;
buff [16'h00_fd] = 8'h06;
buff [16'h00_fe] = 8'h89;
buff [16'h00_ff] = 8'h82;
buff [16'h01_00] = 8'h8A;
buff [16'h01_01] = 8'h83;
buff [16'h01_02] = 8'hF0;
buff [16'h01_03] = 8'h22;
buff [16'h01_04] = 8'h50;
buff [16'h01_05] = 8'h02;
buff [16'h01_06] = 8'hF7;
buff [16'h01_07] = 8'h22;
buff [16'h01_08] = 8'hBB;
buff [16'h01_09] = 8'hFE;
buff [16'h01_0a] = 8'h01;
buff [16'h01_0b] = 8'hF3;
buff [16'h01_0c] = 8'h22;
buff [16'h01_0d] = 8'hF8;
buff [16'h01_0e] = 8'hBB;
buff [16'h01_0f] = 8'h01;
buff [16'h01_10] = 8'h0D;
buff [16'h01_11] = 8'hE5;
buff [16'h01_12] = 8'h82;
buff [16'h01_13] = 8'h29;
buff [16'h01_14] = 8'hF5;
buff [16'h01_15] = 8'h82;
buff [16'h01_16] = 8'hE5;
buff [16'h01_17] = 8'h83;
buff [16'h01_18] = 8'h3A;
buff [16'h01_19] = 8'hF5;
buff [16'h01_1a] = 8'h83;
buff [16'h01_1b] = 8'hE8;
buff [16'h01_1c] = 8'hF0;
buff [16'h01_1d] = 8'h22;
buff [16'h01_1e] = 8'h50;
buff [16'h01_1f] = 8'h06;
buff [16'h01_20] = 8'hE9;
buff [16'h01_21] = 8'h25;
buff [16'h01_22] = 8'h82;
buff [16'h01_23] = 8'hC8;
buff [16'h01_24] = 8'hF6;
buff [16'h01_25] = 8'h22;
buff [16'h01_26] = 8'hBB;
buff [16'h01_27] = 8'hFE;
buff [16'h01_28] = 8'h05;
buff [16'h01_29] = 8'hE9;
buff [16'h01_2a] = 8'h25;
buff [16'h01_2b] = 8'h82;
buff [16'h01_2c] = 8'hC8;
buff [16'h01_2d] = 8'hF2;
buff [16'h01_2e] = 8'h22;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 7;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h02;
buff [16'h00_01] = 8'h00;
buff [16'h00_02] = 8'h35;
buff [16'h00_03] = 8'h90;
buff [16'h00_04] = 8'h00;
buff [16'h00_05] = 8'h00;
buff [16'h00_06] = 8'h74;
buff [16'h00_07] = 8'h01;
buff [16'h00_08] = 8'hF0;
buff [16'h00_09] = 8'hFF;
buff [16'h00_0a] = 8'h7E;
buff [16'h00_0b] = 8'h00;
buff [16'h00_0c] = 8'h74;
buff [16'h00_0d] = 8'hFF;
buff [16'h00_0e] = 8'h2F;
buff [16'h00_0f] = 8'hF5;
buff [16'h00_10] = 8'h82;
buff [16'h00_11] = 8'hEE;
buff [16'h00_12] = 8'h34;
buff [16'h00_13] = 8'hFF;
buff [16'h00_14] = 8'hF5;
buff [16'h00_15] = 8'h83;
buff [16'h00_16] = 8'hE0;
buff [16'h00_17] = 8'h04;
buff [16'h00_18] = 8'hFD;
buff [16'h00_19] = 8'h74;
buff [16'h00_1a] = 8'h00;
buff [16'h00_1b] = 8'h2F;
buff [16'h00_1c] = 8'hF5;
buff [16'h00_1d] = 8'h82;
buff [16'h00_1e] = 8'hEE;
buff [16'h00_1f] = 8'h34;
buff [16'h00_20] = 8'h00;
buff [16'h00_21] = 8'hF5;
buff [16'h00_22] = 8'h83;
buff [16'h00_23] = 8'hED;
buff [16'h00_24] = 8'hF0;
buff [16'h00_25] = 8'h0F;
buff [16'h00_26] = 8'hBF;
buff [16'h00_27] = 8'h00;
buff [16'h00_28] = 8'h01;
buff [16'h00_29] = 8'h0E;
buff [16'h00_2a] = 8'hE4;
buff [16'h00_2b] = 8'hB5;
buff [16'h00_2c] = 8'h07;
buff [16'h00_2d] = 8'hDE;
buff [16'h00_2e] = 8'hEE;
buff [16'h00_2f] = 8'hB4;
buff [16'h00_30] = 8'h08;
buff [16'h00_31] = 8'hDA;
buff [16'h00_32] = 8'h80;
buff [16'h00_33] = 8'hFE;
buff [16'h00_34] = 8'h22;
buff [16'h00_35] = 8'h78;
buff [16'h00_36] = 8'h7F;
buff [16'h00_37] = 8'hE4;
buff [16'h00_38] = 8'hF6;
buff [16'h00_39] = 8'hD8;
buff [16'h00_3a] = 8'hFD;
buff [16'h00_3b] = 8'h75;
buff [16'h00_3c] = 8'h81;
buff [16'h00_3d] = 8'h07;
buff [16'h00_3e] = 8'h02;
buff [16'h00_3f] = 8'h00;
buff [16'h00_40] = 8'h03;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 7;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h02;
buff [16'h00_01] = 8'h00;
buff [16'h00_02] = 8'h5E;
buff [16'h00_03] = 8'h8F;
buff [16'h00_04] = 8'h0F;
buff [16'h00_05] = 8'h8E;
buff [16'h00_06] = 8'h0E;
buff [16'h00_07] = 8'h8D;
buff [16'h00_08] = 8'h0D;
buff [16'h00_09] = 8'h8C;
buff [16'h00_0a] = 8'h0C;
buff [16'h00_0b] = 8'h22;
buff [16'h00_0c] = 8'h75;
buff [16'h00_0d] = 8'h0B;
buff [16'h00_0e] = 8'h67;
buff [16'h00_0f] = 8'h75;
buff [16'h00_10] = 8'h0A;
buff [16'h00_11] = 8'h45;
buff [16'h00_12] = 8'h75;
buff [16'h00_13] = 8'h09;
buff [16'h00_14] = 8'h23;
buff [16'h00_15] = 8'h75;
buff [16'h00_16] = 8'h08;
buff [16'h00_17] = 8'h01;
buff [16'h00_18] = 8'hAF;
buff [16'h00_19] = 8'h0B;
buff [16'h00_1a] = 8'hAE;
buff [16'h00_1b] = 8'h0A;
buff [16'h00_1c] = 8'hAD;
buff [16'h00_1d] = 8'h09;
buff [16'h00_1e] = 8'hAC;
buff [16'h00_1f] = 8'h08;
buff [16'h00_20] = 8'h78;
buff [16'h00_21] = 8'h18;
buff [16'h00_22] = 8'h12;
buff [16'h00_23] = 8'h00;
buff [16'h00_24] = 8'h6A;
buff [16'h00_25] = 8'h12;
buff [16'h00_26] = 8'h00;
buff [16'h00_27] = 8'h03;
buff [16'h00_28] = 8'h8F;
buff [16'h00_29] = 8'h80;
buff [16'h00_2a] = 8'hAF;
buff [16'h00_2b] = 8'h0B;
buff [16'h00_2c] = 8'hAE;
buff [16'h00_2d] = 8'h0A;
buff [16'h00_2e] = 8'hAD;
buff [16'h00_2f] = 8'h09;
buff [16'h00_30] = 8'hAC;
buff [16'h00_31] = 8'h08;
buff [16'h00_32] = 8'h78;
buff [16'h00_33] = 8'h10;
buff [16'h00_34] = 8'h12;
buff [16'h00_35] = 8'h00;
buff [16'h00_36] = 8'h6A;
buff [16'h00_37] = 8'h12;
buff [16'h00_38] = 8'h00;
buff [16'h00_39] = 8'h03;
buff [16'h00_3a] = 8'h8F;
buff [16'h00_3b] = 8'h90;
buff [16'h00_3c] = 8'hAF;
buff [16'h00_3d] = 8'h0B;
buff [16'h00_3e] = 8'hAE;
buff [16'h00_3f] = 8'h0A;
buff [16'h00_40] = 8'hAD;
buff [16'h00_41] = 8'h09;
buff [16'h00_42] = 8'hAC;
buff [16'h00_43] = 8'h08;
buff [16'h00_44] = 8'h78;
buff [16'h00_45] = 8'h08;
buff [16'h00_46] = 8'h12;
buff [16'h00_47] = 8'h00;
buff [16'h00_48] = 8'h6A;
buff [16'h00_49] = 8'h12;
buff [16'h00_4a] = 8'h00;
buff [16'h00_4b] = 8'h03;
buff [16'h00_4c] = 8'h8F;
buff [16'h00_4d] = 8'hA0;
buff [16'h00_4e] = 8'hAF;
buff [16'h00_4f] = 8'h0B;
buff [16'h00_50] = 8'hAE;
buff [16'h00_51] = 8'h0A;
buff [16'h00_52] = 8'hAD;
buff [16'h00_53] = 8'h09;
buff [16'h00_54] = 8'hAC;
buff [16'h00_55] = 8'h08;
buff [16'h00_56] = 8'h12;
buff [16'h00_57] = 8'h00;
buff [16'h00_58] = 8'h03;
buff [16'h00_59] = 8'h8F;
buff [16'h00_5a] = 8'h80;
buff [16'h00_5b] = 8'h80;
buff [16'h00_5c] = 8'hFE;
buff [16'h00_5d] = 8'h22;
buff [16'h00_5e] = 8'h78;
buff [16'h00_5f] = 8'h7F;
buff [16'h00_60] = 8'hE4;
buff [16'h00_61] = 8'hF6;
buff [16'h00_62] = 8'hD8;
buff [16'h00_63] = 8'hFD;
buff [16'h00_64] = 8'h75;
buff [16'h00_65] = 8'h81;
buff [16'h00_66] = 8'h0F;
buff [16'h00_67] = 8'h02;
buff [16'h00_68] = 8'h00;
buff [16'h00_69] = 8'h0C;
buff [16'h00_6a] = 8'hE8;
buff [16'h00_6b] = 8'h60;
buff [16'h00_6c] = 8'h0F;
buff [16'h00_6d] = 8'hEC;
buff [16'h00_6e] = 8'hC3;
buff [16'h00_6f] = 8'h13;
buff [16'h00_70] = 8'hFC;
buff [16'h00_71] = 8'hED;
buff [16'h00_72] = 8'h13;
buff [16'h00_73] = 8'hFD;
buff [16'h00_74] = 8'hEE;
buff [16'h00_75] = 8'h13;
buff [16'h00_76] = 8'hFE;
buff [16'h00_77] = 8'hEF;
buff [16'h00_78] = 8'h13;
buff [16'h00_79] = 8'hFF;
buff [16'h00_7a] = 8'hD8;
buff [16'h00_7b] = 8'hF1;
buff [16'h00_7c] = 8'h22;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 8;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h02;
buff [16'h00_01] = 8'h00;
buff [16'h00_02] = 8'h5B;
buff [16'h00_03] = 8'h75;
buff [16'h00_04] = 8'h08;
buff [16'h00_05] = 8'h00;
buff [16'h00_06] = 8'h75;
buff [16'h00_07] = 8'h09;
buff [16'h00_08] = 8'h86;
buff [16'h00_09] = 8'h7B;
buff [16'h00_0a] = 8'h01;
buff [16'h00_0b] = 8'h7A;
buff [16'h00_0c] = 8'h00;
buff [16'h00_0d] = 8'hE4;
buff [16'h00_0e] = 8'hFF;
buff [16'h00_0f] = 8'hFE;
buff [16'h00_10] = 8'h0B;
buff [16'h00_11] = 8'hBB;
buff [16'h00_12] = 8'h00;
buff [16'h00_13] = 8'h01;
buff [16'h00_14] = 8'h0A;
buff [16'h00_15] = 8'h0F;
buff [16'h00_16] = 8'hBF;
buff [16'h00_17] = 8'h00;
buff [16'h00_18] = 8'h01;
buff [16'h00_19] = 8'h0E;
buff [16'h00_1a] = 8'hEF;
buff [16'h00_1b] = 8'h64;
buff [16'h00_1c] = 8'h0C;
buff [16'h00_1d] = 8'h4E;
buff [16'h00_1e] = 8'h70;
buff [16'h00_1f] = 8'hF0;
buff [16'h00_20] = 8'hAC;
buff [16'h00_21] = 8'h02;
buff [16'h00_22] = 8'hAD;
buff [16'h00_23] = 8'h03;
buff [16'h00_24] = 8'hAE;
buff [16'h00_25] = 8'h08;
buff [16'h00_26] = 8'hAF;
buff [16'h00_27] = 8'h09;
buff [16'h00_28] = 8'h12;
buff [16'h00_29] = 8'h00;
buff [16'h00_2a] = 8'h7B;
buff [16'h00_2b] = 8'h8E;
buff [16'h00_2c] = 8'h0A;
buff [16'h00_2d] = 8'h8F;
buff [16'h00_2e] = 8'h0B;
buff [16'h00_2f] = 8'hAC;
buff [16'h00_30] = 8'h02;
buff [16'h00_31] = 8'hAD;
buff [16'h00_32] = 8'h03;
buff [16'h00_33] = 8'hAE;
buff [16'h00_34] = 8'h08;
buff [16'h00_35] = 8'hAF;
buff [16'h00_36] = 8'h09;
buff [16'h00_37] = 8'h12;
buff [16'h00_38] = 8'h00;
buff [16'h00_39] = 8'h7B;
buff [16'h00_3a] = 8'h8C;
buff [16'h00_3b] = 8'h0C;
buff [16'h00_3c] = 8'h8D;
buff [16'h00_3d] = 8'h0D;
buff [16'h00_3e] = 8'hAC;
buff [16'h00_3f] = 8'h02;
buff [16'h00_40] = 8'hAD;
buff [16'h00_41] = 8'h03;
buff [16'h00_42] = 8'hAE;
buff [16'h00_43] = 8'h0A;
buff [16'h00_44] = 8'hAF;
buff [16'h00_45] = 8'h0B;
buff [16'h00_46] = 8'h12;
buff [16'h00_47] = 8'h00;
buff [16'h00_48] = 8'h67;
buff [16'h00_49] = 8'hE5;
buff [16'h00_4a] = 8'h0D;
buff [16'h00_4b] = 8'h2F;
buff [16'h00_4c] = 8'hFF;
buff [16'h00_4d] = 8'hE5;
buff [16'h00_4e] = 8'h0C;
buff [16'h00_4f] = 8'h3E;
buff [16'h00_50] = 8'h85;
buff [16'h00_51] = 8'h0B;
buff [16'h00_52] = 8'h80;
buff [16'h00_53] = 8'h85;
buff [16'h00_54] = 8'h0D;
buff [16'h00_55] = 8'h80;
buff [16'h00_56] = 8'h8F;
buff [16'h00_57] = 8'h80;
buff [16'h00_58] = 8'h80;
buff [16'h00_59] = 8'hFE;
buff [16'h00_5a] = 8'h22;
buff [16'h00_5b] = 8'h78;
buff [16'h00_5c] = 8'h7F;
buff [16'h00_5d] = 8'hE4;
buff [16'h00_5e] = 8'hF6;
buff [16'h00_5f] = 8'hD8;
buff [16'h00_60] = 8'hFD;
buff [16'h00_61] = 8'h75;
buff [16'h00_62] = 8'h81;
buff [16'h00_63] = 8'h0D;
buff [16'h00_64] = 8'h02;
buff [16'h00_65] = 8'h00;
buff [16'h00_66] = 8'h03;
buff [16'h00_67] = 8'hEF;
buff [16'h00_68] = 8'hF8;
buff [16'h00_69] = 8'h8D;
buff [16'h00_6a] = 8'hF0;
buff [16'h00_6b] = 8'hA4;
buff [16'h00_6c] = 8'hFF;
buff [16'h00_6d] = 8'hED;
buff [16'h00_6e] = 8'hC5;
buff [16'h00_6f] = 8'hF0;
buff [16'h00_70] = 8'hCE;
buff [16'h00_71] = 8'hA4;
buff [16'h00_72] = 8'h2E;
buff [16'h00_73] = 8'hFE;
buff [16'h00_74] = 8'hEC;
buff [16'h00_75] = 8'h88;
buff [16'h00_76] = 8'hF0;
buff [16'h00_77] = 8'hA4;
buff [16'h00_78] = 8'h2E;
buff [16'h00_79] = 8'hFE;
buff [16'h00_7a] = 8'h22;
buff [16'h00_7b] = 8'hBC;
buff [16'h00_7c] = 8'h00;
buff [16'h00_7d] = 8'h0B;
buff [16'h00_7e] = 8'hBE;
buff [16'h00_7f] = 8'h00;
buff [16'h00_80] = 8'h29;
buff [16'h00_81] = 8'hEF;
buff [16'h00_82] = 8'h8D;
buff [16'h00_83] = 8'hF0;
buff [16'h00_84] = 8'h84;
buff [16'h00_85] = 8'hFF;
buff [16'h00_86] = 8'hAD;
buff [16'h00_87] = 8'hF0;
buff [16'h00_88] = 8'h22;
buff [16'h00_89] = 8'hE4;
buff [16'h00_8a] = 8'hCC;
buff [16'h00_8b] = 8'hF8;
buff [16'h00_8c] = 8'h75;
buff [16'h00_8d] = 8'hF0;
buff [16'h00_8e] = 8'h08;
buff [16'h00_8f] = 8'hEF;
buff [16'h00_90] = 8'h2F;
buff [16'h00_91] = 8'hFF;
buff [16'h00_92] = 8'hEE;
buff [16'h00_93] = 8'h33;
buff [16'h00_94] = 8'hFE;
buff [16'h00_95] = 8'hEC;
buff [16'h00_96] = 8'h33;
buff [16'h00_97] = 8'hFC;
buff [16'h00_98] = 8'hEE;
buff [16'h00_99] = 8'h9D;
buff [16'h00_9a] = 8'hEC;
buff [16'h00_9b] = 8'h98;
buff [16'h00_9c] = 8'h40;
buff [16'h00_9d] = 8'h05;
buff [16'h00_9e] = 8'hFC;
buff [16'h00_9f] = 8'hEE;
buff [16'h00_a0] = 8'h9D;
buff [16'h00_a1] = 8'hFE;
buff [16'h00_a2] = 8'h0F;
buff [16'h00_a3] = 8'hD5;
buff [16'h00_a4] = 8'hF0;
buff [16'h00_a5] = 8'hE9;
buff [16'h00_a6] = 8'hE4;
buff [16'h00_a7] = 8'hCE;
buff [16'h00_a8] = 8'hFD;
buff [16'h00_a9] = 8'h22;
buff [16'h00_aa] = 8'hED;
buff [16'h00_ab] = 8'hF8;
buff [16'h00_ac] = 8'hF5;
buff [16'h00_ad] = 8'hF0;
buff [16'h00_ae] = 8'hEE;
buff [16'h00_af] = 8'h84;
buff [16'h00_b0] = 8'h20;
buff [16'h00_b1] = 8'hD2;
buff [16'h00_b2] = 8'h1C;
buff [16'h00_b3] = 8'hFE;
buff [16'h00_b4] = 8'hAD;
buff [16'h00_b5] = 8'hF0;
buff [16'h00_b6] = 8'h75;
buff [16'h00_b7] = 8'hF0;
buff [16'h00_b8] = 8'h08;
buff [16'h00_b9] = 8'hEF;
buff [16'h00_ba] = 8'h2F;
buff [16'h00_bb] = 8'hFF;
buff [16'h00_bc] = 8'hED;
buff [16'h00_bd] = 8'h33;
buff [16'h00_be] = 8'hFD;
buff [16'h00_bf] = 8'h40;
buff [16'h00_c0] = 8'h07;
buff [16'h00_c1] = 8'h98;
buff [16'h00_c2] = 8'h50;
buff [16'h00_c3] = 8'h06;
buff [16'h00_c4] = 8'hD5;
buff [16'h00_c5] = 8'hF0;
buff [16'h00_c6] = 8'hF2;
buff [16'h00_c7] = 8'h22;
buff [16'h00_c8] = 8'hC3;
buff [16'h00_c9] = 8'h98;
buff [16'h00_ca] = 8'hFD;
buff [16'h00_cb] = 8'h0F;
buff [16'h00_cc] = 8'hD5;
buff [16'h00_cd] = 8'hF0;
buff [16'h00_ce] = 8'hEA;
buff [16'h00_cf] = 8'h22;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 7;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h75;
buff [16'h00_01] = 8'h20;
buff [16'h00_02] = 8'h00;
buff [16'h00_03] = 8'hD2;
buff [16'h00_04] = 8'h02;
buff [16'h00_05] = 8'h12;
buff [16'h00_06] = 8'h00;
buff [16'h00_07] = 8'h0E;
buff [16'h00_08] = 8'h85;
buff [16'h00_09] = 8'h20;
buff [16'h00_0a] = 8'h80;
buff [16'h00_0b] = 8'h02;
buff [16'h00_0c] = 8'h00;
buff [16'h00_0d] = 8'h12;
buff [16'h00_0e] = 8'h75;
buff [16'h00_0f] = 8'h80;
buff [16'h00_10] = 8'h0A;
buff [16'h00_11] = 8'h22;
buff [16'h00_12] = 8'h00;
buff [16'h00_13] = 8'h00;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 10;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h01;
buff [16'h00_01] = 8'h3F;
buff [16'h00_02] = 8'h00;
buff [16'h00_03] = 8'h32;
buff [16'h00_04] = 8'h00;
buff [16'h00_05] = 8'h00;
buff [16'h00_06] = 8'h00;
buff [16'h00_07] = 8'h00;
buff [16'h00_08] = 8'h00;
buff [16'h00_09] = 8'h00;
buff [16'h00_0a] = 8'h00;
buff [16'h00_0b] = 8'hD2;
buff [16'h00_0c] = 8'hB1;
buff [16'h00_0d] = 8'hC2;
buff [16'h00_0e] = 8'hB1;
buff [16'h00_0f] = 8'h32;
buff [16'h00_10] = 8'h00;
buff [16'h00_11] = 8'h00;
buff [16'h00_12] = 8'h00;
buff [16'h00_13] = 8'h32;
buff [16'h00_14] = 8'h00;
buff [16'h00_15] = 8'h00;
buff [16'h00_16] = 8'h00;
buff [16'h00_17] = 8'h00;
buff [16'h00_18] = 8'h00;
buff [16'h00_19] = 8'h00;
buff [16'h00_1a] = 8'h00;
buff [16'h00_1b] = 8'h32;
buff [16'h00_1c] = 8'h00;
buff [16'h00_1d] = 8'h00;
buff [16'h00_1e] = 8'h00;
buff [16'h00_1f] = 8'h00;
buff [16'h00_20] = 8'h00;
buff [16'h00_21] = 8'h00;
buff [16'h00_22] = 8'h00;
buff [16'h00_23] = 8'hC2;
buff [16'h00_24] = 8'h98;
buff [16'h00_25] = 8'hC2;
buff [16'h00_26] = 8'h99;
buff [16'h00_27] = 8'h75;
buff [16'h00_28] = 8'hF0;
buff [16'h00_29] = 8'h01;
buff [16'h00_2a] = 8'h32;
buff [16'h00_2b] = 8'hE5;
buff [16'h00_2c] = 8'hF0;
buff [16'h00_2d] = 8'h60;
buff [16'h00_2e] = 8'hFC;
buff [16'h00_2f] = 8'h22;
buff [16'h00_30] = 8'hE3;
buff [16'h00_31] = 8'h9A;
buff [16'h00_32] = 8'h70;
buff [16'h00_33] = 8'h5C;
buff [16'h00_34] = 8'hA2;
buff [16'h00_35] = 8'hB0;
buff [16'h00_36] = 8'h50;
buff [16'h00_37] = 8'h58;
buff [16'h00_38] = 8'h22;
buff [16'h00_39] = 8'hE5;
buff [16'h00_3a] = 8'h99;
buff [16'h00_3b] = 8'h9B;
buff [16'h00_3c] = 8'h70;
buff [16'h00_3d] = 8'h52;
buff [16'h00_3e] = 8'h22;
buff [16'h00_3f] = 8'hE4;
buff [16'h00_40] = 8'hF5;
buff [16'h00_41] = 8'h7F;
buff [16'h00_42] = 8'hC2;
buff [16'h00_43] = 8'hB7;
buff [16'h00_44] = 8'hC2;
buff [16'h00_45] = 8'hB0;
buff [16'h00_46] = 8'h75;
buff [16'h00_47] = 8'hA8;
buff [16'h00_48] = 8'h90;
buff [16'h00_49] = 8'h78;
buff [16'h00_4a] = 8'h98;
buff [16'h00_4b] = 8'h79;
buff [16'h00_4c] = 8'h99;
buff [16'h00_4d] = 8'h75;
buff [16'h00_4e] = 8'h82;
buff [16'h00_4f] = 8'h87;
buff [16'h00_50] = 8'h75;
buff [16'h00_51] = 8'h83;
buff [16'h00_52] = 8'h00;
buff [16'h00_53] = 8'h75;
buff [16'h00_54] = 8'h98;
buff [16'h00_55] = 8'h00;
buff [16'h00_56] = 8'h75;
buff [16'h00_57] = 8'hF0;
buff [16'h00_58] = 8'h00;
buff [16'h00_59] = 8'h74;
buff [16'h00_5a] = 8'h10;
buff [16'h00_5b] = 8'h7A;
buff [16'h00_5c] = 8'h6C;
buff [16'h00_5d] = 8'hF2;
buff [16'h00_5e] = 8'h8A;
buff [16'h00_5f] = 8'h99;
buff [16'h00_60] = 8'h11;
buff [16'h00_61] = 8'h2B;
buff [16'h00_62] = 8'h11;
buff [16'h00_63] = 8'h30;
buff [16'h00_64] = 8'hA2;
buff [16'h00_65] = 8'hB0;
buff [16'h00_66] = 8'h50;
buff [16'h00_67] = 8'h28;
buff [16'h00_68] = 8'hC3;
buff [16'h00_69] = 8'h74;
buff [16'h00_6a] = 8'h00;
buff [16'h00_6b] = 8'hF2;
buff [16'h00_6c] = 8'h75;
buff [16'h00_6d] = 8'h7F;
buff [16'h00_6e] = 8'h01;
buff [16'h00_6f] = 8'h00;
buff [16'h00_70] = 8'h00;
buff [16'h00_71] = 8'hA2;
buff [16'h00_72] = 8'hB0;
buff [16'h00_73] = 8'h40;
buff [16'h00_74] = 8'h1B;
buff [16'h00_75] = 8'h75;
buff [16'h00_76] = 8'h7F;
buff [16'h00_77] = 8'h02;
buff [16'h00_78] = 8'h75;
buff [16'h00_79] = 8'hF0;
buff [16'h00_7a] = 8'h00;
buff [16'h00_7b] = 8'h74;
buff [16'h00_7c] = 8'hD3;
buff [16'h00_7d] = 8'hFB;
buff [16'h00_7e] = 8'hF3;
buff [16'h00_7f] = 8'h75;
buff [16'h00_80] = 8'h98;
buff [16'h00_81] = 8'h10;
buff [16'h00_82] = 8'h11;
buff [16'h00_83] = 8'h2B;
buff [16'h00_84] = 8'h11;
buff [16'h00_85] = 8'h39;
buff [16'h00_86] = 8'hA2;
buff [16'h00_87] = 8'hB0;
buff [16'h00_88] = 8'h50;
buff [16'h00_89] = 8'h06;
buff [16'h00_8a] = 8'hC3;
buff [16'h00_8b] = 8'h75;
buff [16'h00_8c] = 8'h80;
buff [16'h00_8d] = 8'h00;
buff [16'h00_8e] = 8'h01;
buff [16'h00_8f] = 8'h96;
buff [16'h00_90] = 8'h85;
buff [16'h00_91] = 8'h7F;
buff [16'h00_92] = 8'hA0;
buff [16'h00_93] = 8'h00;
buff [16'h00_94] = 8'h01;
buff [16'h00_95] = 8'h93;
buff [16'h00_96] = 8'h75;
buff [16'h00_97] = 8'hF0;
buff [16'h00_98] = 8'h00;
buff [16'h00_99] = 8'h75;
buff [16'h00_9a] = 8'hA8;
buff [16'h00_9b] = 8'h92;
buff [16'h00_9c] = 8'h75;
buff [16'h00_9d] = 8'h7F;
buff [16'h00_9e] = 8'h03;
buff [16'h00_9f] = 8'hC2;
buff [16'h00_a0] = 8'hB1;
buff [16'h00_a1] = 8'h74;
buff [16'h00_a2] = 8'h50;
buff [16'h00_a3] = 8'hF2;
buff [16'h00_a4] = 8'h75;
buff [16'h00_a5] = 8'h98;
buff [16'h00_a6] = 8'h40;
buff [16'h00_a7] = 8'h75;
buff [16'h00_a8] = 8'h8C;
buff [16'h00_a9] = 8'hEC;
buff [16'h00_aa] = 8'h75;
buff [16'h00_ab] = 8'h8A;
buff [16'h00_ac] = 8'hEC;
buff [16'h00_ad] = 8'h75;
buff [16'h00_ae] = 8'h8D;
buff [16'h00_af] = 8'hEC;
buff [16'h00_b0] = 8'h75;
buff [16'h00_b1] = 8'h8B;
buff [16'h00_b2] = 8'hEC;
buff [16'h00_b3] = 8'h75;
buff [16'h00_b4] = 8'h89;
buff [16'h00_b5] = 8'h22;
buff [16'h00_b6] = 8'hD2;
buff [16'h00_b7] = 8'h8C;
buff [16'h00_b8] = 8'hD2;
buff [16'h00_b9] = 8'h8E;
buff [16'h00_ba] = 8'h7A;
buff [16'h00_bb] = 8'h95;
buff [16'h00_bc] = 8'h8A;
buff [16'h00_bd] = 8'h99;
buff [16'h00_be] = 8'h11;
buff [16'h00_bf] = 8'h2B;
buff [16'h00_c0] = 8'hC2;
buff [16'h00_c1] = 8'h8C;
buff [16'h00_c2] = 8'hC2;
buff [16'h00_c3] = 8'h8E;
buff [16'h00_c4] = 8'h11;
buff [16'h00_c5] = 8'h30;
buff [16'h00_c6] = 8'h75;
buff [16'h00_c7] = 8'h7F;
buff [16'h00_c8] = 8'h04;
buff [16'h00_c9] = 8'h75;
buff [16'h00_ca] = 8'hF0;
buff [16'h00_cb] = 8'h00;
buff [16'h00_cc] = 8'h74;
buff [16'h00_cd] = 8'h40;
buff [16'h00_ce] = 8'hF2;
buff [16'h00_cf] = 8'h75;
buff [16'h00_d0] = 8'h98;
buff [16'h00_d1] = 8'h50;
buff [16'h00_d2] = 8'h74;
buff [16'h00_d3] = 8'hA2;
buff [16'h00_d4] = 8'hFB;
buff [16'h00_d5] = 8'hD2;
buff [16'h00_d6] = 8'h8C;
buff [16'h00_d7] = 8'hD2;
buff [16'h00_d8] = 8'h8E;
buff [16'h00_d9] = 8'hF7;
buff [16'h00_da] = 8'h11;
buff [16'h00_db] = 8'h2B;
buff [16'h00_dc] = 8'hC2;
buff [16'h00_dd] = 8'h8C;
buff [16'h00_de] = 8'hC2;
buff [16'h00_df] = 8'h8E;
buff [16'h00_e0] = 8'h11;
buff [16'h00_e1] = 8'h39;
buff [16'h00_e2] = 8'h75;
buff [16'h00_e3] = 8'h7F;
buff [16'h00_e4] = 8'h05;
buff [16'h00_e5] = 8'hA2;
buff [16'h00_e6] = 8'h9A;
buff [16'h00_e7] = 8'h50;
buff [16'h00_e8] = 8'hA7;
buff [16'h00_e9] = 8'h75;
buff [16'h00_ea] = 8'hF0;
buff [16'h00_eb] = 8'h00;
buff [16'h00_ec] = 8'h75;
buff [16'h00_ed] = 8'hA8;
buff [16'h00_ee] = 8'h82;
buff [16'h00_ef] = 8'h75;
buff [16'h00_f0] = 8'h7F;
buff [16'h00_f1] = 8'h06;
buff [16'h00_f2] = 8'h74;
buff [16'h00_f3] = 8'h50;
buff [16'h00_f4] = 8'hF2;
buff [16'h00_f5] = 8'h75;
buff [16'h00_f6] = 8'h98;
buff [16'h00_f7] = 8'h50;
buff [16'h00_f8] = 8'hD2;
buff [16'h00_f9] = 8'h8C;
buff [16'h00_fa] = 8'hD2;
buff [16'h00_fb] = 8'h8E;
buff [16'h00_fc] = 8'h7A;
buff [16'h00_fd] = 8'h97;
buff [16'h00_fe] = 8'h8A;
buff [16'h00_ff] = 8'h99;
buff [16'h01_00] = 8'h74;
buff [16'h01_01] = 8'hD5;
buff [16'h01_02] = 8'hFB;
buff [16'h01_03] = 8'hF3;
buff [16'h01_04] = 8'hA2;
buff [16'h01_05] = 8'h99;
buff [16'h01_06] = 8'h50;
buff [16'h01_07] = 8'hFC;
buff [16'h01_08] = 8'hA2;
buff [16'h01_09] = 8'h98;
buff [16'h01_0a] = 8'h50;
buff [16'h01_0b] = 8'hF8;
buff [16'h01_0c] = 8'hC2;
buff [16'h01_0d] = 8'h8C;
buff [16'h01_0e] = 8'hC2;
buff [16'h01_0f] = 8'h8E;
buff [16'h01_10] = 8'h11;
buff [16'h01_11] = 8'h30;
buff [16'h01_12] = 8'h75;
buff [16'h01_13] = 8'h7F;
buff [16'h01_14] = 8'h07;
buff [16'h01_15] = 8'h11;
buff [16'h01_16] = 8'h39;
buff [16'h01_17] = 8'hC2;
buff [16'h01_18] = 8'h99;
buff [16'h01_19] = 8'hC2;
buff [16'h01_1a] = 8'h98;
buff [16'h01_1b] = 8'h75;
buff [16'h01_1c] = 8'h80;
buff [16'h01_1d] = 8'h01;
buff [16'h01_1e] = 8'h75;
buff [16'h01_1f] = 8'hF0;
buff [16'h01_20] = 8'h00;
buff [16'h01_21] = 8'h75;
buff [16'h01_22] = 8'hA8;
buff [16'h01_23] = 8'h90;
buff [16'h01_24] = 8'h75;
buff [16'h01_25] = 8'h7F;
buff [16'h01_26] = 8'h08;
buff [16'h01_27] = 8'h74;
buff [16'h01_28] = 8'h90;
buff [16'h01_29] = 8'hF2;
buff [16'h01_2a] = 8'h75;
buff [16'h01_2b] = 8'h98;
buff [16'h01_2c] = 8'h80;
buff [16'h01_2d] = 8'h7A;
buff [16'h01_2e] = 8'h95;
buff [16'h01_2f] = 8'h8A;
buff [16'h01_30] = 8'h99;
buff [16'h01_31] = 8'h11;
buff [16'h01_32] = 8'h2B;
buff [16'h01_33] = 8'h11;
buff [16'h01_34] = 8'h30;
buff [16'h01_35] = 8'h75;
buff [16'h01_36] = 8'h7F;
buff [16'h01_37] = 8'h09;
buff [16'h01_38] = 8'h75;
buff [16'h01_39] = 8'hF0;
buff [16'h01_3a] = 8'h00;
buff [16'h01_3b] = 8'h74;
buff [16'h01_3c] = 8'h88;
buff [16'h01_3d] = 8'hF2;
buff [16'h01_3e] = 8'h75;
buff [16'h01_3f] = 8'h98;
buff [16'h01_40] = 8'h90;
buff [16'h01_41] = 8'h74;
buff [16'h01_42] = 8'hA2;
buff [16'h01_43] = 8'hFB;
buff [16'h01_44] = 8'hF7;
buff [16'h01_45] = 8'h11;
buff [16'h01_46] = 8'h2B;
buff [16'h01_47] = 8'h11;
buff [16'h01_48] = 8'h39;
buff [16'h01_49] = 8'h75;
buff [16'h01_4a] = 8'h7F;
buff [16'h01_4b] = 8'h0A;
buff [16'h01_4c] = 8'hA2;
buff [16'h01_4d] = 8'h9A;
buff [16'h01_4e] = 8'h50;
buff [16'h01_4f] = 8'h52;
buff [16'h01_50] = 8'h75;
buff [16'h01_51] = 8'h7F;
buff [16'h01_52] = 8'h0B;
buff [16'h01_53] = 8'h75;
buff [16'h01_54] = 8'hF0;
buff [16'h01_55] = 8'h00;
buff [16'h01_56] = 8'h74;
buff [16'h01_57] = 8'h80;
buff [16'h01_58] = 8'hF2;
buff [16'h01_59] = 8'h75;
buff [16'h01_5a] = 8'h98;
buff [16'h01_5b] = 8'hB0;
buff [16'h01_5c] = 8'h74;
buff [16'h01_5d] = 8'hA2;
buff [16'h01_5e] = 8'hFB;
buff [16'h01_5f] = 8'hF7;
buff [16'h01_60] = 8'h00;
buff [16'h01_61] = 8'hA2;
buff [16'h01_62] = 8'h98;
buff [16'h01_63] = 8'h50;
buff [16'h01_64] = 8'hFB;
buff [16'h01_65] = 8'h11;
buff [16'h01_66] = 8'h39;
buff [16'h01_67] = 8'h75;
buff [16'h01_68] = 8'h7F;
buff [16'h01_69] = 8'h0C;
buff [16'h01_6a] = 8'hE5;
buff [16'h01_6b] = 8'hF0;
buff [16'h01_6c] = 8'h60;
buff [16'h01_6d] = 8'h34;
buff [16'h01_6e] = 8'h75;
buff [16'h01_6f] = 8'hF0;
buff [16'h01_70] = 8'h00;
buff [16'h01_71] = 8'h75;
buff [16'h01_72] = 8'hA8;
buff [16'h01_73] = 8'h00;
buff [16'h01_74] = 8'h75;
buff [16'h01_75] = 8'h7F;
buff [16'h01_76] = 8'h0D;
buff [16'h01_77] = 8'h74;
buff [16'h01_78] = 8'h90;
buff [16'h01_79] = 8'hF2;
buff [16'h01_7a] = 8'h74;
buff [16'h01_7b] = 8'h80;
buff [16'h01_7c] = 8'hF0;
buff [16'h01_7d] = 8'hF5;
buff [16'h01_7e] = 8'h87;
buff [16'h01_7f] = 8'h75;
buff [16'h01_80] = 8'h98;
buff [16'h01_81] = 8'h5A;
buff [16'h01_82] = 8'h7A;
buff [16'h01_83] = 8'h97;
buff [16'h01_84] = 8'h8A;
buff [16'h01_85] = 8'h99;
buff [16'h01_86] = 8'h74;
buff [16'h01_87] = 8'hD5;
buff [16'h01_88] = 8'hFB;
buff [16'h01_89] = 8'hF3;
buff [16'h01_8a] = 8'hA2;
buff [16'h01_8b] = 8'h99;
buff [16'h01_8c] = 8'h50;
buff [16'h01_8d] = 8'hFC;
buff [16'h01_8e] = 8'hA2;
buff [16'h01_8f] = 8'h98;
buff [16'h01_90] = 8'h50;
buff [16'h01_91] = 8'hF8;
buff [16'h01_92] = 8'h11;
buff [16'h01_93] = 8'h30;
buff [16'h01_94] = 8'h75;
buff [16'h01_95] = 8'h7F;
buff [16'h01_96] = 8'h0E;
buff [16'h01_97] = 8'h11;
buff [16'h01_98] = 8'h39;
buff [16'h01_99] = 8'hC2;
buff [16'h01_9a] = 8'h99;
buff [16'h01_9b] = 8'hC2;
buff [16'h01_9c] = 8'h98;
buff [16'h01_9d] = 8'h75;
buff [16'h01_9e] = 8'h80;
buff [16'h01_9f] = 8'h02;
buff [16'h01_a0] = 8'h21;
buff [16'h01_a1] = 8'hA5;
buff [16'h01_a2] = 8'h02;
buff [16'h01_a3] = 8'h00;
buff [16'h01_a4] = 8'h90;
buff [16'h01_a5] = 8'h75;
buff [16'h01_a6] = 8'hF0;
buff [16'h01_a7] = 8'h00;
buff [16'h01_a8] = 8'h75;
buff [16'h01_a9] = 8'hA8;
buff [16'h01_aa] = 8'h92;
buff [16'h01_ab] = 8'h75;
buff [16'h01_ac] = 8'h7F;
buff [16'h01_ad] = 8'h0F;
buff [16'h01_ae] = 8'h74;
buff [16'h01_af] = 8'hD0;
buff [16'h01_b0] = 8'hF2;
buff [16'h01_b1] = 8'h75;
buff [16'h01_b2] = 8'h98;
buff [16'h01_b3] = 8'hC0;
buff [16'h01_b4] = 8'h7A;
buff [16'h01_b5] = 8'h95;
buff [16'h01_b6] = 8'hD2;
buff [16'h01_b7] = 8'h8C;
buff [16'h01_b8] = 8'hD2;
buff [16'h01_b9] = 8'h8E;
buff [16'h01_ba] = 8'h8A;
buff [16'h01_bb] = 8'h99;
buff [16'h01_bc] = 8'h11;
buff [16'h01_bd] = 8'h2B;
buff [16'h01_be] = 8'hC2;
buff [16'h01_bf] = 8'h8C;
buff [16'h01_c0] = 8'hC2;
buff [16'h01_c1] = 8'h8E;
buff [16'h01_c2] = 8'h11;
buff [16'h01_c3] = 8'h30;
buff [16'h01_c4] = 8'h75;
buff [16'h01_c5] = 8'h7F;
buff [16'h01_c6] = 8'h10;
buff [16'h01_c7] = 8'h75;
buff [16'h01_c8] = 8'hF0;
buff [16'h01_c9] = 8'h00;
buff [16'h01_ca] = 8'h74;
buff [16'h01_cb] = 8'hC0;
buff [16'h01_cc] = 8'hF2;
buff [16'h01_cd] = 8'h75;
buff [16'h01_ce] = 8'h98;
buff [16'h01_cf] = 8'hD4;
buff [16'h01_d0] = 8'h74;
buff [16'h01_d1] = 8'hA2;
buff [16'h01_d2] = 8'hFB;
buff [16'h01_d3] = 8'hF7;
buff [16'h01_d4] = 8'hD2;
buff [16'h01_d5] = 8'h8C;
buff [16'h01_d6] = 8'hD2;
buff [16'h01_d7] = 8'h8E;
buff [16'h01_d8] = 8'h11;
buff [16'h01_d9] = 8'h2B;
buff [16'h01_da] = 8'hC2;
buff [16'h01_db] = 8'h8C;
buff [16'h01_dc] = 8'hC2;
buff [16'h01_dd] = 8'h8E;
buff [16'h01_de] = 8'h11;
buff [16'h01_df] = 8'h39;
buff [16'h01_e0] = 8'h75;
buff [16'h01_e1] = 8'h7F;
buff [16'h01_e2] = 8'h11;
buff [16'h01_e3] = 8'hA2;
buff [16'h01_e4] = 8'h9A;
buff [16'h01_e5] = 8'h40;
buff [16'h01_e6] = 8'hBB;
buff [16'h01_e7] = 8'h75;
buff [16'h01_e8] = 8'hF0;
buff [16'h01_e9] = 8'h00;
buff [16'h01_ea] = 8'h75;
buff [16'h01_eb] = 8'hA8;
buff [16'h01_ec] = 8'h92;
buff [16'h01_ed] = 8'h75;
buff [16'h01_ee] = 8'h7F;
buff [16'h01_ef] = 8'h12;
buff [16'h01_f0] = 8'h74;
buff [16'h01_f1] = 8'hD0;
buff [16'h01_f2] = 8'hF2;
buff [16'h01_f3] = 8'h75;
buff [16'h01_f4] = 8'h98;
buff [16'h01_f5] = 8'hF8;
buff [16'h01_f6] = 8'h7A;
buff [16'h01_f7] = 8'h97;
buff [16'h01_f8] = 8'hD2;
buff [16'h01_f9] = 8'h8C;
buff [16'h01_fa] = 8'hD2;
buff [16'h01_fb] = 8'h8E;
buff [16'h01_fc] = 8'h8A;
buff [16'h01_fd] = 8'h99;
buff [16'h01_fe] = 8'h74;
buff [16'h01_ff] = 8'hD5;
buff [16'h02_00] = 8'hFB;
buff [16'h02_01] = 8'hF3;
buff [16'h02_02] = 8'hA2;
buff [16'h02_03] = 8'h99;
buff [16'h02_04] = 8'h50;
buff [16'h02_05] = 8'hFC;
buff [16'h02_06] = 8'hA2;
buff [16'h02_07] = 8'h98;
buff [16'h02_08] = 8'h50;
buff [16'h02_09] = 8'hF8;
buff [16'h02_0a] = 8'hC2;
buff [16'h02_0b] = 8'h8C;
buff [16'h02_0c] = 8'hC2;
buff [16'h02_0d] = 8'h8E;
buff [16'h02_0e] = 8'h11;
buff [16'h02_0f] = 8'h30;
buff [16'h02_10] = 8'h75;
buff [16'h02_11] = 8'h7F;
buff [16'h02_12] = 8'h13;
buff [16'h02_13] = 8'h11;
buff [16'h02_14] = 8'h39;
buff [16'h02_15] = 8'hC2;
buff [16'h02_16] = 8'h99;
buff [16'h02_17] = 8'hC2;
buff [16'h02_18] = 8'h98;
buff [16'h02_19] = 8'h75;
buff [16'h02_1a] = 8'h7F;
buff [16'h02_1b] = 8'h14;
buff [16'h02_1c] = 8'hA2;
buff [16'h02_1d] = 8'h9A;
buff [16'h02_1e] = 8'h40;
buff [16'h02_1f] = 8'h82;
buff [16'h02_20] = 8'hE2;
buff [16'h02_21] = 8'h94;
buff [16'h02_22] = 8'hD7;
buff [16'h02_23] = 8'h75;
buff [16'h02_24] = 8'h80;
buff [16'h02_25] = 8'h03;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 7;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h85;
buff [16'h00_01] = 8'hD0;
buff [16'h00_02] = 8'h90;
buff [16'h00_03] = 8'h00;
buff [16'h00_04] = 8'h00;
buff [16'h00_05] = 8'h01;
buff [16'h00_06] = 8'h03;
buff [16'h00_07] = 8'hE4;
buff [16'h00_08] = 8'hF8;
buff [16'h00_09] = 8'h7C;
buff [16'h00_0a] = 8'h40;
buff [16'h00_0b] = 8'h75;
buff [16'h00_0c] = 8'hD0;
buff [16'h00_0d] = 8'h08;
buff [16'h00_0e] = 8'h78;
buff [16'h00_0f] = 8'h01;
buff [16'h00_10] = 8'h7C;
buff [16'h00_11] = 8'h41;
buff [16'h00_12] = 8'h75;
buff [16'h00_13] = 8'hD0;
buff [16'h00_14] = 8'h10;
buff [16'h00_15] = 8'h78;
buff [16'h00_16] = 8'h02;
buff [16'h00_17] = 8'h7C;
buff [16'h00_18] = 8'h42;
buff [16'h00_19] = 8'h75;
buff [16'h00_1a] = 8'hD0;
buff [16'h00_1b] = 8'h18;
buff [16'h00_1c] = 8'h78;
buff [16'h00_1d] = 8'h03;
buff [16'h00_1e] = 8'h7C;
buff [16'h00_1f] = 8'h43;
buff [16'h00_20] = 8'h75;
buff [16'h00_21] = 8'h80;
buff [16'h00_22] = 8'h00;
buff [16'h00_23] = 8'h75;
buff [16'h00_24] = 8'hD0;
buff [16'h00_25] = 8'h10;
buff [16'h00_26] = 8'hE8;
buff [16'h00_27] = 8'h94;
buff [16'h00_28] = 8'h02;
buff [16'h00_29] = 8'h70;
buff [16'h00_2a] = 8'hD5;
buff [16'h00_2b] = 8'hEC;
buff [16'h00_2c] = 8'h94;
buff [16'h00_2d] = 8'h42;
buff [16'h00_2e] = 8'h70;
buff [16'h00_2f] = 8'hD0;
buff [16'h00_30] = 8'h75;
buff [16'h00_31] = 8'h80;
buff [16'h00_32] = 8'h01;
buff [16'h00_33] = 8'h75;
buff [16'h00_34] = 8'hD0;
buff [16'h00_35] = 8'h08;
buff [16'h00_36] = 8'hE8;
buff [16'h00_37] = 8'h94;
buff [16'h00_38] = 8'h01;
buff [16'h00_39] = 8'h70;
buff [16'h00_3a] = 8'hC5;
buff [16'h00_3b] = 8'hEC;
buff [16'h00_3c] = 8'h94;
buff [16'h00_3d] = 8'h41;
buff [16'h00_3e] = 8'h70;
buff [16'h00_3f] = 8'hC0;
buff [16'h00_40] = 8'h75;
buff [16'h00_41] = 8'h80;
buff [16'h00_42] = 8'h02;
buff [16'h00_43] = 8'h75;
buff [16'h00_44] = 8'hD0;
buff [16'h00_45] = 8'h18;
buff [16'h00_46] = 8'hE8;
buff [16'h00_47] = 8'h94;
buff [16'h00_48] = 8'h03;
buff [16'h00_49] = 8'h70;
buff [16'h00_4a] = 8'hB5;
buff [16'h00_4b] = 8'hEC;
buff [16'h00_4c] = 8'h94;
buff [16'h00_4d] = 8'h43;
buff [16'h00_4e] = 8'h70;
buff [16'h00_4f] = 8'hB0;
buff [16'h00_50] = 8'h75;
buff [16'h00_51] = 8'h80;
buff [16'h00_52] = 8'h03;
buff [16'h00_53] = 8'h75;
buff [16'h00_54] = 8'hD0;
buff [16'h00_55] = 8'h10;
buff [16'h00_56] = 8'hE8;
buff [16'h00_57] = 8'h70;
buff [16'h00_58] = 8'hA7;
buff [16'h00_59] = 8'hEC;
buff [16'h00_5a] = 8'h94;
buff [16'h00_5b] = 8'h04;
buff [16'h00_5c] = 8'h70;
buff [16'h00_5d] = 8'hA2;
buff [16'h00_5e] = 8'h75;
buff [16'h00_5f] = 8'h80;
buff [16'h00_60] = 8'h04;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 7;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h02;
buff [16'h00_01] = 8'h00;
buff [16'h00_02] = 8'h19;
buff [16'h00_03] = 8'h7F;
buff [16'h00_04] = 8'h40;
buff [16'h00_05] = 8'h7E;
buff [16'h00_06] = 8'hFC;
buff [16'h00_07] = 8'hAD;
buff [16'h00_08] = 8'h07;
buff [16'h00_09] = 8'h8D;
buff [16'h00_0a] = 8'h80;
buff [16'h00_0b] = 8'h0F;
buff [16'h00_0c] = 8'hBF;
buff [16'h00_0d] = 8'h00;
buff [16'h00_0e] = 8'h01;
buff [16'h00_0f] = 8'h0E;
buff [16'h00_10] = 8'hBE;
buff [16'h00_11] = 8'hFC;
buff [16'h00_12] = 8'hF4;
buff [16'h00_13] = 8'hBF;
buff [16'h00_14] = 8'h4A;
buff [16'h00_15] = 8'hF1;
buff [16'h00_16] = 8'h80;
buff [16'h00_17] = 8'hFE;
buff [16'h00_18] = 8'h22;
buff [16'h00_19] = 8'h78;
buff [16'h00_1a] = 8'h7F;
buff [16'h00_1b] = 8'hE4;
buff [16'h00_1c] = 8'hF6;
buff [16'h00_1d] = 8'hD8;
buff [16'h00_1e] = 8'hFD;
buff [16'h00_1f] = 8'h75;
buff [16'h00_20] = 8'h81;
buff [16'h00_21] = 8'h07;
buff [16'h00_22] = 8'h02;
buff [16'h00_23] = 8'h00;
buff [16'h00_24] = 8'h03;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 10;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h01;
buff [16'h00_01] = 8'h4B;
buff [16'h00_02] = 8'h00;
buff [16'h00_03] = 8'h32;
buff [16'h00_04] = 8'h00;
buff [16'h00_05] = 8'h00;
buff [16'h00_06] = 8'h00;
buff [16'h00_07] = 8'h00;
buff [16'h00_08] = 8'h00;
buff [16'h00_09] = 8'h00;
buff [16'h00_0a] = 8'h00;
buff [16'h00_0b] = 8'h08;
buff [16'h00_0c] = 8'h32;
buff [16'h00_0d] = 8'h00;
buff [16'h00_0e] = 8'h00;
buff [16'h00_0f] = 8'h00;
buff [16'h00_10] = 8'h00;
buff [16'h00_11] = 8'h00;
buff [16'h00_12] = 8'h00;
buff [16'h00_13] = 8'h32;
buff [16'h00_14] = 8'h00;
buff [16'h00_15] = 8'h00;
buff [16'h00_16] = 8'h00;
buff [16'h00_17] = 8'h00;
buff [16'h00_18] = 8'h00;
buff [16'h00_19] = 8'h00;
buff [16'h00_1a] = 8'h00;
buff [16'h00_1b] = 8'h09;
buff [16'h00_1c] = 8'h32;
buff [16'h00_1d] = 8'h00;
buff [16'h00_1e] = 8'h00;
buff [16'h00_1f] = 8'h00;
buff [16'h00_20] = 8'h00;
buff [16'h00_21] = 8'h00;
buff [16'h00_22] = 8'h00;
buff [16'h00_23] = 8'h32;
buff [16'h00_24] = 8'hE5;
buff [16'h00_25] = 8'h8C;
buff [16'h00_26] = 8'h9B;
buff [16'h00_27] = 8'h70;
buff [16'h00_28] = 8'h1D;
buff [16'h00_29] = 8'h0A;
buff [16'h00_2a] = 8'hE5;
buff [16'h00_2b] = 8'h8A;
buff [16'h00_2c] = 8'h9C;
buff [16'h00_2d] = 8'h70;
buff [16'h00_2e] = 8'h17;
buff [16'h00_2f] = 8'h0A;
buff [16'h00_30] = 8'hE8;
buff [16'h00_31] = 8'h9D;
buff [16'h00_32] = 8'h70;
buff [16'h00_33] = 8'h12;
buff [16'h00_34] = 8'h22;
buff [16'h00_35] = 8'hE5;
buff [16'h00_36] = 8'h8D;
buff [16'h00_37] = 8'h9B;
buff [16'h00_38] = 8'h70;
buff [16'h00_39] = 8'h0C;
buff [16'h00_3a] = 8'h0A;
buff [16'h00_3b] = 8'hE5;
buff [16'h00_3c] = 8'h8B;
buff [16'h00_3d] = 8'h9C;
buff [16'h00_3e] = 8'h70;
buff [16'h00_3f] = 8'h06;
buff [16'h00_40] = 8'h0A;
buff [16'h00_41] = 8'hE9;
buff [16'h00_42] = 8'h9D;
buff [16'h00_43] = 8'h70;
buff [16'h00_44] = 8'h01;
buff [16'h00_45] = 8'h22;
buff [16'h00_46] = 8'h8A;
buff [16'h00_47] = 8'h80;
buff [16'h00_48] = 8'h00;
buff [16'h00_49] = 8'h01;
buff [16'h00_4a] = 8'h46;
buff [16'h00_4b] = 8'hE4;
buff [16'h00_4c] = 8'hF8;
buff [16'h00_4d] = 8'hF9;
buff [16'h00_4e] = 8'h75;
buff [16'h00_4f] = 8'hA8;
buff [16'h00_50] = 8'h8A;
buff [16'h00_51] = 8'hC3;
buff [16'h00_52] = 8'h75;
buff [16'h00_53] = 8'h89;
buff [16'h00_54] = 8'h00;
buff [16'h00_55] = 8'h75;
buff [16'h00_56] = 8'h8C;
buff [16'h00_57] = 8'h00;
buff [16'h00_58] = 8'h75;
buff [16'h00_59] = 8'h8A;
buff [16'h00_5a] = 8'h00;
buff [16'h00_5b] = 8'h75;
buff [16'h00_5c] = 8'h88;
buff [16'h00_5d] = 8'h10;
buff [16'h00_5e] = 8'h00;
buff [16'h00_5f] = 8'h00;
buff [16'h00_60] = 8'h00;
buff [16'h00_61] = 8'hC2;
buff [16'h00_62] = 8'h8C;
buff [16'h00_63] = 8'h7A;
buff [16'h00_64] = 8'h10;
buff [16'h00_65] = 8'h7B;
buff [16'h00_66] = 8'h00;
buff [16'h00_67] = 8'h7C;
buff [16'h00_68] = 8'h04;
buff [16'h00_69] = 8'h7D;
buff [16'h00_6a] = 8'h00;
buff [16'h00_6b] = 8'h11;
buff [16'h00_6c] = 8'h24;
buff [16'h00_6d] = 8'h75;
buff [16'h00_6e] = 8'h8A;
buff [16'h00_6f] = 8'h1C;
buff [16'h00_70] = 8'hD2;
buff [16'h00_71] = 8'h8C;
buff [16'h00_72] = 8'h00;
buff [16'h00_73] = 8'h00;
buff [16'h00_74] = 8'h00;
buff [16'h00_75] = 8'h00;
buff [16'h00_76] = 8'hC2;
buff [16'h00_77] = 8'h8C;
buff [16'h00_78] = 8'h7A;
buff [16'h00_79] = 8'h20;
buff [16'h00_7a] = 8'h7B;
buff [16'h00_7b] = 8'h01;
buff [16'h00_7c] = 8'h7C;
buff [16'h00_7d] = 8'h01;
buff [16'h00_7e] = 8'h7D;
buff [16'h00_7f] = 8'h00;
buff [16'h00_80] = 8'h11;
buff [16'h00_81] = 8'h24;
buff [16'h00_82] = 8'h75;
buff [16'h00_83] = 8'h8A;
buff [16'h00_84] = 8'h1C;
buff [16'h00_85] = 8'h75;
buff [16'h00_86] = 8'h8C;
buff [16'h00_87] = 8'hFF;
buff [16'h00_88] = 8'hD2;
buff [16'h00_89] = 8'h8C;
buff [16'h00_8a] = 8'h00;
buff [16'h00_8b] = 8'h00;
buff [16'h00_8c] = 8'h00;
buff [16'h00_8d] = 8'h00;
buff [16'h00_8e] = 8'h00;
buff [16'h00_8f] = 8'hC2;
buff [16'h00_90] = 8'h8C;
buff [16'h00_91] = 8'h7A;
buff [16'h00_92] = 8'h30;
buff [16'h00_93] = 8'h7B;
buff [16'h00_94] = 8'h00;
buff [16'h00_95] = 8'h7C;
buff [16'h00_96] = 8'h02;
buff [16'h00_97] = 8'h7D;
buff [16'h00_98] = 8'h01;
buff [16'h00_99] = 8'h11;
buff [16'h00_9a] = 8'h24;
buff [16'h00_9b] = 8'h75;
buff [16'h00_9c] = 8'h89;
buff [16'h00_9d] = 8'h01;
buff [16'h00_9e] = 8'h75;
buff [16'h00_9f] = 8'h8C;
buff [16'h00_a0] = 8'h00;
buff [16'h00_a1] = 8'h75;
buff [16'h00_a2] = 8'h8A;
buff [16'h00_a3] = 8'h00;
buff [16'h00_a4] = 8'hD2;
buff [16'h00_a5] = 8'h8C;
buff [16'h00_a6] = 8'h00;
buff [16'h00_a7] = 8'h00;
buff [16'h00_a8] = 8'h00;
buff [16'h00_a9] = 8'hC2;
buff [16'h00_aa] = 8'h8C;
buff [16'h00_ab] = 8'h7A;
buff [16'h00_ac] = 8'h40;
buff [16'h00_ad] = 8'h7B;
buff [16'h00_ae] = 8'h00;
buff [16'h00_af] = 8'h7C;
buff [16'h00_b0] = 8'h04;
buff [16'h00_b1] = 8'h7D;
buff [16'h00_b2] = 8'h01;
buff [16'h00_b3] = 8'h11;
buff [16'h00_b4] = 8'h24;
buff [16'h00_b5] = 8'h75;
buff [16'h00_b6] = 8'h8A;
buff [16'h00_b7] = 8'hFC;
buff [16'h00_b8] = 8'hD2;
buff [16'h00_b9] = 8'h8C;
buff [16'h00_ba] = 8'h00;
buff [16'h00_bb] = 8'h00;
buff [16'h00_bc] = 8'h00;
buff [16'h00_bd] = 8'h00;
buff [16'h00_be] = 8'hC2;
buff [16'h00_bf] = 8'h8C;
buff [16'h00_c0] = 8'h7A;
buff [16'h00_c1] = 8'h50;
buff [16'h00_c2] = 8'h7B;
buff [16'h00_c3] = 8'h01;
buff [16'h00_c4] = 8'h7C;
buff [16'h00_c5] = 8'h01;
buff [16'h00_c6] = 8'h7D;
buff [16'h00_c7] = 8'h01;
buff [16'h00_c8] = 8'h11;
buff [16'h00_c9] = 8'h24;
buff [16'h00_ca] = 8'h75;
buff [16'h00_cb] = 8'h8A;
buff [16'h00_cc] = 8'hFC;
buff [16'h00_cd] = 8'h75;
buff [16'h00_ce] = 8'h8C;
buff [16'h00_cf] = 8'hFF;
buff [16'h00_d0] = 8'hD2;
buff [16'h00_d1] = 8'h8C;
buff [16'h00_d2] = 8'h00;
buff [16'h00_d3] = 8'h00;
buff [16'h00_d4] = 8'h00;
buff [16'h00_d5] = 8'h00;
buff [16'h00_d6] = 8'h00;
buff [16'h00_d7] = 8'hC2;
buff [16'h00_d8] = 8'h8C;
buff [16'h00_d9] = 8'h7A;
buff [16'h00_da] = 8'h60;
buff [16'h00_db] = 8'h7B;
buff [16'h00_dc] = 8'h00;
buff [16'h00_dd] = 8'h7C;
buff [16'h00_de] = 8'h02;
buff [16'h00_df] = 8'h7D;
buff [16'h00_e0] = 8'h02;
buff [16'h00_e1] = 8'h11;
buff [16'h00_e2] = 8'h24;
buff [16'h00_e3] = 8'h75;
buff [16'h00_e4] = 8'h89;
buff [16'h00_e5] = 8'h02;
buff [16'h00_e6] = 8'h75;
buff [16'h00_e7] = 8'h8C;
buff [16'h00_e8] = 8'h00;
buff [16'h00_e9] = 8'h75;
buff [16'h00_ea] = 8'h8A;
buff [16'h00_eb] = 8'h05;
buff [16'h00_ec] = 8'hD2;
buff [16'h00_ed] = 8'h8C;
buff [16'h00_ee] = 8'h00;
buff [16'h00_ef] = 8'h00;
buff [16'h00_f0] = 8'h00;
buff [16'h00_f1] = 8'hC2;
buff [16'h00_f2] = 8'h8C;
buff [16'h00_f3] = 8'h7A;
buff [16'h00_f4] = 8'h70;
buff [16'h00_f5] = 8'h7B;
buff [16'h00_f6] = 8'h00;
buff [16'h00_f7] = 8'h7C;
buff [16'h00_f8] = 8'h09;
buff [16'h00_f9] = 8'h7D;
buff [16'h00_fa] = 8'h02;
buff [16'h00_fb] = 8'h11;
buff [16'h00_fc] = 8'h24;
buff [16'h00_fd] = 8'h75;
buff [16'h00_fe] = 8'h8A;
buff [16'h00_ff] = 8'hFC;
buff [16'h01_00] = 8'h75;
buff [16'h01_01] = 8'h8C;
buff [16'h01_02] = 8'h50;
buff [16'h01_03] = 8'hD2;
buff [16'h01_04] = 8'h8C;
buff [16'h01_05] = 8'h00;
buff [16'h01_06] = 8'h00;
buff [16'h01_07] = 8'h00;
buff [16'h01_08] = 8'h00;
buff [16'h01_09] = 8'hC2;
buff [16'h01_0a] = 8'h8C;
buff [16'h01_0b] = 8'h7A;
buff [16'h01_0c] = 8'h80;
buff [16'h01_0d] = 8'h7B;
buff [16'h01_0e] = 8'h50;
buff [16'h01_0f] = 8'h7C;
buff [16'h01_10] = 8'h51;
buff [16'h01_11] = 8'h7D;
buff [16'h01_12] = 8'h03;
buff [16'h01_13] = 8'h11;
buff [16'h01_14] = 8'h24;
buff [16'h01_15] = 8'h75;
buff [16'h01_16] = 8'h89;
buff [16'h01_17] = 8'h03;
buff [16'h01_18] = 8'h75;
buff [16'h01_19] = 8'h8C;
buff [16'h01_1a] = 8'h00;
buff [16'h01_1b] = 8'h75;
buff [16'h01_1c] = 8'h8A;
buff [16'h01_1d] = 8'h00;
buff [16'h01_1e] = 8'hD2;
buff [16'h01_1f] = 8'h8C;
buff [16'h01_20] = 8'h00;
buff [16'h01_21] = 8'h00;
buff [16'h01_22] = 8'h00;
buff [16'h01_23] = 8'hC2;
buff [16'h01_24] = 8'h8C;
buff [16'h01_25] = 8'h7A;
buff [16'h01_26] = 8'h90;
buff [16'h01_27] = 8'h7B;
buff [16'h01_28] = 8'h00;
buff [16'h01_29] = 8'h7C;
buff [16'h01_2a] = 8'h04;
buff [16'h01_2b] = 8'h7D;
buff [16'h01_2c] = 8'h03;
buff [16'h01_2d] = 8'h11;
buff [16'h01_2e] = 8'h24;
buff [16'h01_2f] = 8'h75;
buff [16'h01_30] = 8'h8A;
buff [16'h01_31] = 8'hFC;
buff [16'h01_32] = 8'h75;
buff [16'h01_33] = 8'h8C;
buff [16'h01_34] = 8'h00;
buff [16'h01_35] = 8'hD2;
buff [16'h01_36] = 8'h8C;
buff [16'h01_37] = 8'h00;
buff [16'h01_38] = 8'h00;
buff [16'h01_39] = 8'h00;
buff [16'h01_3a] = 8'h00;
buff [16'h01_3b] = 8'h00;
buff [16'h01_3c] = 8'hC2;
buff [16'h01_3d] = 8'h8C;
buff [16'h01_3e] = 8'h7A;
buff [16'h01_3f] = 8'hA0;
buff [16'h01_40] = 8'h7B;
buff [16'h01_41] = 8'h00;
buff [16'h01_42] = 8'h7C;
buff [16'h01_43] = 8'h02;
buff [16'h01_44] = 8'h7D;
buff [16'h01_45] = 8'h04;
buff [16'h01_46] = 8'h11;
buff [16'h01_47] = 8'h24;
buff [16'h01_48] = 8'h75;
buff [16'h01_49] = 8'h8A;
buff [16'h01_4a] = 8'h00;
buff [16'h01_4b] = 8'h75;
buff [16'h01_4c] = 8'h8C;
buff [16'h01_4d] = 8'h00;
buff [16'h01_4e] = 8'hD2;
buff [16'h01_4f] = 8'h8E;
buff [16'h01_50] = 8'h00;
buff [16'h01_51] = 8'h00;
buff [16'h01_52] = 8'h00;
buff [16'h01_53] = 8'hC2;
buff [16'h01_54] = 8'h8E;
buff [16'h01_55] = 8'h7A;
buff [16'h01_56] = 8'hB0;
buff [16'h01_57] = 8'h7B;
buff [16'h01_58] = 8'h04;
buff [16'h01_59] = 8'h7C;
buff [16'h01_5a] = 8'h00;
buff [16'h01_5b] = 8'h7D;
buff [16'h01_5c] = 8'h04;
buff [16'h01_5d] = 8'h11;
buff [16'h01_5e] = 8'h24;
buff [16'h01_5f] = 8'h75;
buff [16'h01_60] = 8'h8A;
buff [16'h01_61] = 8'h00;
buff [16'h01_62] = 8'h75;
buff [16'h01_63] = 8'h8C;
buff [16'h01_64] = 8'hFC;
buff [16'h01_65] = 8'hD2;
buff [16'h01_66] = 8'h8E;
buff [16'h01_67] = 8'h00;
buff [16'h01_68] = 8'h00;
buff [16'h01_69] = 8'h00;
buff [16'h01_6a] = 8'h00;
buff [16'h01_6b] = 8'h00;
buff [16'h01_6c] = 8'hC2;
buff [16'h01_6d] = 8'h8E;
buff [16'h01_6e] = 8'h7A;
buff [16'h01_6f] = 8'hC0;
buff [16'h01_70] = 8'h7B;
buff [16'h01_71] = 8'h02;
buff [16'h01_72] = 8'h7C;
buff [16'h01_73] = 8'h00;
buff [16'h01_74] = 8'h7D;
buff [16'h01_75] = 8'h01;
buff [16'h01_76] = 8'hA8;
buff [16'h01_77] = 8'h01;
buff [16'h01_78] = 8'h11;
buff [16'h01_79] = 8'h24;
buff [16'h01_7a] = 8'h75;
buff [16'h01_7b] = 8'h80;
buff [16'h01_7c] = 8'h01;
buff [16'h01_7d] = 8'h79;
buff [16'h01_7e] = 8'h00;
buff [16'h01_7f] = 8'h75;
buff [16'h01_80] = 8'h89;
buff [16'h01_81] = 8'h00;
buff [16'h01_82] = 8'h75;
buff [16'h01_83] = 8'h8D;
buff [16'h01_84] = 8'h00;
buff [16'h01_85] = 8'h75;
buff [16'h01_86] = 8'h8B;
buff [16'h01_87] = 8'h00;
buff [16'h01_88] = 8'h75;
buff [16'h01_89] = 8'h88;
buff [16'h01_8a] = 8'h40;
buff [16'h01_8b] = 8'h00;
buff [16'h01_8c] = 8'h00;
buff [16'h01_8d] = 8'h00;
buff [16'h01_8e] = 8'hC2;
buff [16'h01_8f] = 8'h8E;
buff [16'h01_90] = 8'h7A;
buff [16'h01_91] = 8'h18;
buff [16'h01_92] = 8'h7B;
buff [16'h01_93] = 8'h00;
buff [16'h01_94] = 8'h7C;
buff [16'h01_95] = 8'h04;
buff [16'h01_96] = 8'h7D;
buff [16'h01_97] = 8'h00;
buff [16'h01_98] = 8'h11;
buff [16'h01_99] = 8'h35;
buff [16'h01_9a] = 8'h75;
buff [16'h01_9b] = 8'h8B;
buff [16'h01_9c] = 8'h1C;
buff [16'h01_9d] = 8'hD2;
buff [16'h01_9e] = 8'h8E;
buff [16'h01_9f] = 8'h00;
buff [16'h01_a0] = 8'h00;
buff [16'h01_a1] = 8'h00;
buff [16'h01_a2] = 8'h00;
buff [16'h01_a3] = 8'hC2;
buff [16'h01_a4] = 8'h8E;
buff [16'h01_a5] = 8'h7A;
buff [16'h01_a6] = 8'h28;
buff [16'h01_a7] = 8'h7B;
buff [16'h01_a8] = 8'h01;
buff [16'h01_a9] = 8'h7C;
buff [16'h01_aa] = 8'h01;
buff [16'h01_ab] = 8'h7D;
buff [16'h01_ac] = 8'h00;
buff [16'h01_ad] = 8'h11;
buff [16'h01_ae] = 8'h35;
buff [16'h01_af] = 8'h75;
buff [16'h01_b0] = 8'h8B;
buff [16'h01_b1] = 8'h1C;
buff [16'h01_b2] = 8'h75;
buff [16'h01_b3] = 8'h8D;
buff [16'h01_b4] = 8'hFF;
buff [16'h01_b5] = 8'hD2;
buff [16'h01_b6] = 8'h8E;
buff [16'h01_b7] = 8'h00;
buff [16'h01_b8] = 8'h00;
buff [16'h01_b9] = 8'h00;
buff [16'h01_ba] = 8'h00;
buff [16'h01_bb] = 8'h00;
buff [16'h01_bc] = 8'hC2;
buff [16'h01_bd] = 8'h8E;
buff [16'h01_be] = 8'h7A;
buff [16'h01_bf] = 8'h38;
buff [16'h01_c0] = 8'h7B;
buff [16'h01_c1] = 8'h00;
buff [16'h01_c2] = 8'h7C;
buff [16'h01_c3] = 8'h02;
buff [16'h01_c4] = 8'h7D;
buff [16'h01_c5] = 8'h01;
buff [16'h01_c6] = 8'h11;
buff [16'h01_c7] = 8'h35;
buff [16'h01_c8] = 8'h75;
buff [16'h01_c9] = 8'h89;
buff [16'h01_ca] = 8'h10;
buff [16'h01_cb] = 8'h75;
buff [16'h01_cc] = 8'h8D;
buff [16'h01_cd] = 8'h00;
buff [16'h01_ce] = 8'h75;
buff [16'h01_cf] = 8'h8B;
buff [16'h01_d0] = 8'h00;
buff [16'h01_d1] = 8'hD2;
buff [16'h01_d2] = 8'h8E;
buff [16'h01_d3] = 8'h00;
buff [16'h01_d4] = 8'h00;
buff [16'h01_d5] = 8'h00;
buff [16'h01_d6] = 8'hC2;
buff [16'h01_d7] = 8'h8E;
buff [16'h01_d8] = 8'h7A;
buff [16'h01_d9] = 8'h48;
buff [16'h01_da] = 8'h7B;
buff [16'h01_db] = 8'h00;
buff [16'h01_dc] = 8'h7C;
buff [16'h01_dd] = 8'h04;
buff [16'h01_de] = 8'h7D;
buff [16'h01_df] = 8'h01;
buff [16'h01_e0] = 8'h11;
buff [16'h01_e1] = 8'h35;
buff [16'h01_e2] = 8'h75;
buff [16'h01_e3] = 8'h8B;
buff [16'h01_e4] = 8'hFC;
buff [16'h01_e5] = 8'hD2;
buff [16'h01_e6] = 8'h8E;
buff [16'h01_e7] = 8'h00;
buff [16'h01_e8] = 8'h00;
buff [16'h01_e9] = 8'h00;
buff [16'h01_ea] = 8'h00;
buff [16'h01_eb] = 8'hC2;
buff [16'h01_ec] = 8'h8E;
buff [16'h01_ed] = 8'h7A;
buff [16'h01_ee] = 8'h58;
buff [16'h01_ef] = 8'h7B;
buff [16'h01_f0] = 8'h01;
buff [16'h01_f1] = 8'h7C;
buff [16'h01_f2] = 8'h01;
buff [16'h01_f3] = 8'h7D;
buff [16'h01_f4] = 8'h01;
buff [16'h01_f5] = 8'h11;
buff [16'h01_f6] = 8'h35;
buff [16'h01_f7] = 8'h75;
buff [16'h01_f8] = 8'h8B;
buff [16'h01_f9] = 8'hFC;
buff [16'h01_fa] = 8'h75;
buff [16'h01_fb] = 8'h8D;
buff [16'h01_fc] = 8'hFF;
buff [16'h01_fd] = 8'hD2;
buff [16'h01_fe] = 8'h8E;
buff [16'h01_ff] = 8'h00;
buff [16'h02_00] = 8'h00;
buff [16'h02_01] = 8'h00;
buff [16'h02_02] = 8'h00;
buff [16'h02_03] = 8'h00;
buff [16'h02_04] = 8'hC2;
buff [16'h02_05] = 8'h8E;
buff [16'h02_06] = 8'h7A;
buff [16'h02_07] = 8'h68;
buff [16'h02_08] = 8'h7B;
buff [16'h02_09] = 8'h00;
buff [16'h02_0a] = 8'h7C;
buff [16'h02_0b] = 8'h02;
buff [16'h02_0c] = 8'h7D;
buff [16'h02_0d] = 8'h02;
buff [16'h02_0e] = 8'h11;
buff [16'h02_0f] = 8'h35;
buff [16'h02_10] = 8'h75;
buff [16'h02_11] = 8'h89;
buff [16'h02_12] = 8'h20;
buff [16'h02_13] = 8'h75;
buff [16'h02_14] = 8'h8D;
buff [16'h02_15] = 8'h00;
buff [16'h02_16] = 8'h75;
buff [16'h02_17] = 8'h8B;
buff [16'h02_18] = 8'h05;
buff [16'h02_19] = 8'hD2;
buff [16'h02_1a] = 8'h8E;
buff [16'h02_1b] = 8'h00;
buff [16'h02_1c] = 8'h00;
buff [16'h02_1d] = 8'h00;
buff [16'h02_1e] = 8'hC2;
buff [16'h02_1f] = 8'h8E;
buff [16'h02_20] = 8'h7A;
buff [16'h02_21] = 8'h78;
buff [16'h02_22] = 8'h7B;
buff [16'h02_23] = 8'h00;
buff [16'h02_24] = 8'h7C;
buff [16'h02_25] = 8'h09;
buff [16'h02_26] = 8'h7D;
buff [16'h02_27] = 8'h02;
buff [16'h02_28] = 8'h11;
buff [16'h02_29] = 8'h35;
buff [16'h02_2a] = 8'h75;
buff [16'h02_2b] = 8'h8B;
buff [16'h02_2c] = 8'hFC;
buff [16'h02_2d] = 8'h75;
buff [16'h02_2e] = 8'h8D;
buff [16'h02_2f] = 8'h50;
buff [16'h02_30] = 8'hD2;
buff [16'h02_31] = 8'h8E;
buff [16'h02_32] = 8'h00;
buff [16'h02_33] = 8'h00;
buff [16'h02_34] = 8'h00;
buff [16'h02_35] = 8'h00;
buff [16'h02_36] = 8'hC2;
buff [16'h02_37] = 8'h8E;
buff [16'h02_38] = 8'h7A;
buff [16'h02_39] = 8'h88;
buff [16'h02_3a] = 8'h7B;
buff [16'h02_3b] = 8'h50;
buff [16'h02_3c] = 8'h7C;
buff [16'h02_3d] = 8'h51;
buff [16'h02_3e] = 8'h7D;
buff [16'h02_3f] = 8'h03;
buff [16'h02_40] = 8'h11;
buff [16'h02_41] = 8'h35;
buff [16'h02_42] = 8'h75;
buff [16'h02_43] = 8'h89;
buff [16'h02_44] = 8'h30;
buff [16'h02_45] = 8'h75;
buff [16'h02_46] = 8'h8D;
buff [16'h02_47] = 8'h00;
buff [16'h02_48] = 8'h75;
buff [16'h02_49] = 8'h8B;
buff [16'h02_4a] = 8'h00;
buff [16'h02_4b] = 8'hD2;
buff [16'h02_4c] = 8'h8E;
buff [16'h02_4d] = 8'h00;
buff [16'h02_4e] = 8'h00;
buff [16'h02_4f] = 8'h00;
buff [16'h02_50] = 8'hC2;
buff [16'h02_51] = 8'h8E;
buff [16'h02_52] = 8'h7A;
buff [16'h02_53] = 8'h98;
buff [16'h02_54] = 8'h7B;
buff [16'h02_55] = 8'h00;
buff [16'h02_56] = 8'h7C;
buff [16'h02_57] = 8'h00;
buff [16'h02_58] = 8'h7D;
buff [16'h02_59] = 8'h03;
buff [16'h02_5a] = 8'h11;
buff [16'h02_5b] = 8'h35;
buff [16'h02_5c] = 8'h75;
buff [16'h02_5d] = 8'h8B;
buff [16'h02_5e] = 8'hFC;
buff [16'h02_5f] = 8'h75;
buff [16'h02_60] = 8'h8D;
buff [16'h02_61] = 8'hFF;
buff [16'h02_62] = 8'hD2;
buff [16'h02_63] = 8'h8E;
buff [16'h02_64] = 8'h00;
buff [16'h02_65] = 8'h00;
buff [16'h02_66] = 8'h00;
buff [16'h02_67] = 8'h00;
buff [16'h02_68] = 8'h00;
buff [16'h02_69] = 8'hC2;
buff [16'h02_6a] = 8'h8E;
buff [16'h02_6b] = 8'h7A;
buff [16'h02_6c] = 8'hA8;
buff [16'h02_6d] = 8'h7B;
buff [16'h02_6e] = 8'hFF;
buff [16'h02_6f] = 8'h7C;
buff [16'h02_70] = 8'hFC;
buff [16'h02_71] = 8'h7D;
buff [16'h02_72] = 8'h03;
buff [16'h02_73] = 8'h11;
buff [16'h02_74] = 8'h35;
buff [16'h02_75] = 8'h75;
buff [16'h02_76] = 8'h80;
buff [16'h02_77] = 8'h02;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
parameter INT_ROM_WID= 8;
input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;
wire ea;
assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;
initial
begin
for (i=0; i<65536; i=i+1)
buff [i] = 8'h00;
#2
buff [16'h00_00] = 8'h02;
buff [16'h00_01] = 8'h00;
buff [16'h00_02] = 8'hD6;
buff [16'h00_03] = 8'h32;
buff [16'h00_04] = 8'h00;
buff [16'h00_05] = 8'h00;
buff [16'h00_06] = 8'h00;
buff [16'h00_07] = 8'h00;
buff [16'h00_08] = 8'h00;
buff [16'h00_09] = 8'h00;
buff [16'h00_0a] = 8'h00;
buff [16'h00_0b] = 8'h32;
buff [16'h00_0c] = 8'h00;
buff [16'h00_0d] = 8'h00;
buff [16'h00_0e] = 8'h00;
buff [16'h00_0f] = 8'h00;
buff [16'h00_10] = 8'h00;
buff [16'h00_11] = 8'h00;
buff [16'h00_12] = 8'h00;
buff [16'h00_13] = 8'h32;
buff [16'h00_14] = 8'h00;
buff [16'h00_15] = 8'h00;
buff [16'h00_16] = 8'h00;
buff [16'h00_17] = 8'h00;
buff [16'h00_18] = 8'h00;
buff [16'h00_19] = 8'h00;
buff [16'h00_1a] = 8'h00;
buff [16'h00_1b] = 8'h32;
buff [16'h00_1c] = 8'h00;
buff [16'h00_1d] = 8'h00;
buff [16'h00_1e] = 8'h00;
buff [16'h00_1f] = 8'h00;
buff [16'h00_20] = 8'h00;
buff [16'h00_21] = 8'h00;
buff [16'h00_22] = 8'h00;
buff [16'h00_23] = 8'h32;
buff [16'h00_24] = 8'h00;
buff [16'h00_25] = 8'h00;
buff [16'h00_26] = 8'h00;
buff [16'h00_27] = 8'h00;
buff [16'h00_28] = 8'h00;
buff [16'h00_29] = 8'h00;
buff [16'h00_2a] = 8'h00;
buff [16'h00_2b] = 8'h32;
buff [16'h00_2c] = 8'h00;
buff [16'h00_2d] = 8'h00;
buff [16'h00_2e] = 8'h00;
buff [16'h00_2f] = 8'h00;
buff [16'h00_30] = 8'h00;
buff [16'h00_31] = 8'h00;
buff [16'h00_32] = 8'h00;
buff [16'h00_33] = 8'h12;
buff [16'h00_34] = 8'h00;
buff [16'h00_35] = 8'h38;
buff [16'h00_36] = 8'h80;
buff [16'h00_37] = 8'hFE;
buff [16'h00_38] = 8'h90;
buff [16'h00_39] = 8'h00;
buff [16'h00_3a] = 8'hFF;
buff [16'h00_3b] = 8'h74;
buff [16'h00_3c] = 8'hFF;
buff [16'h00_3d] = 8'hF0;
buff [16'h00_3e] = 8'h7A;
buff [16'h00_3f] = 8'h01;
buff [16'h00_40] = 8'h7B;
buff [16'h00_41] = 8'h00;
buff [16'h00_42] = 8'hC3;
buff [16'h00_43] = 8'hEA;
buff [16'h00_44] = 8'h94;
buff [16'h00_45] = 8'h0A;
buff [16'h00_46] = 8'hEB;
buff [16'h00_47] = 8'h94;
buff [16'h00_48] = 8'h00;
buff [16'h00_49] = 8'h40;
buff [16'h00_4a] = 8'h03;
buff [16'h00_4b] = 8'h02;
buff [16'h00_4c] = 8'h00;
buff [16'h00_4d] = 8'hCC;
buff [16'h00_4e] = 8'h8A;
buff [16'h00_4f] = 8'h05;
buff [16'h00_50] = 8'h7C;
buff [16'h00_51] = 8'h00;
buff [16'h00_52] = 8'h7E;
buff [16'h00_53] = 8'h01;
buff [16'h00_54] = 8'h7F;
buff [16'h00_55] = 8'h00;
buff [16'h00_56] = 8'hC3;
buff [16'h00_57] = 8'hEE;
buff [16'h00_58] = 8'h94;
buff [16'h00_59] = 8'h00;
buff [16'h00_5a] = 8'hEF;
buff [16'h00_5b] = 8'h94;
buff [16'h00_5c] = 8'h01;
buff [16'h00_5d] = 8'hE4;
buff [16'h00_5e] = 8'h33;
buff [16'h00_5f] = 8'hF8;
buff [16'h00_60] = 8'h60;
buff [16'h00_61] = 8'h43;
buff [16'h00_62] = 8'hEE;
buff [16'h00_63] = 8'h2C;
buff [16'h00_64] = 8'hF5;
buff [16'h00_65] = 8'h30;
buff [16'h00_66] = 8'hEF;
buff [16'h00_67] = 8'h3D;
buff [16'h00_68] = 8'hF5;
buff [16'h00_69] = 8'h31;
buff [16'h00_6a] = 8'hE5;
buff [16'h00_6b] = 8'h30;
buff [16'h00_6c] = 8'h24;
buff [16'h00_6d] = 8'h00;
buff [16'h00_6e] = 8'hF5;
buff [16'h00_6f] = 8'h32;
buff [16'h00_70] = 8'hE5;
buff [16'h00_71] = 8'h31;
buff [16'h00_72] = 8'h34;
buff [16'h00_73] = 8'h00;
buff [16'h00_74] = 8'hF5;
buff [16'h00_75] = 8'h33;
buff [16'h00_76] = 8'hE5;
buff [16'h00_77] = 8'h30;
buff [16'h00_78] = 8'h24;
buff [16'h00_79] = 8'hFF;
buff [16'h00_7a] = 8'hF5;
buff [16'h00_7b] = 8'h34;
buff [16'h00_7c] = 8'hE5;
buff [16'h00_7d] = 8'h31;
buff [16'h00_7e] = 8'h34;
buff [16'h00_7f] = 8'hFF;
buff [16'h00_80] = 8'hF5;
buff [16'h00_81] = 8'h35;
buff [16'h00_82] = 8'hE5;
buff [16'h00_83] = 8'h34;
buff [16'h00_84] = 8'h24;
buff [16'h00_85] = 8'h00;
buff [16'h00_86] = 8'hF5;
buff [16'h00_87] = 8'h82;
buff [16'h00_88] = 8'hE5;
buff [16'h00_89] = 8'h35;
buff [16'h00_8a] = 8'h34;
buff [16'h00_8b] = 8'h00;
buff [16'h00_8c] = 8'hF5;
buff [16'h00_8d] = 8'h83;
buff [16'h00_8e] = 8'hE0;
buff [16'h00_8f] = 8'hF9;
buff [16'h00_90] = 8'h24;
buff [16'h00_91] = 8'h01;
buff [16'h00_92] = 8'hF5;
buff [16'h00_93] = 8'h36;
buff [16'h00_94] = 8'h85;
buff [16'h00_95] = 8'h32;
buff [16'h00_96] = 8'h82;
buff [16'h00_97] = 8'h85;
buff [16'h00_98] = 8'h33;
buff [16'h00_99] = 8'h83;
buff [16'h00_9a] = 8'hE5;
buff [16'h00_9b] = 8'h36;
buff [16'h00_9c] = 8'hF0;
buff [16'h00_9d] = 8'h0E;
buff [16'h00_9e] = 8'hBE;
buff [16'h00_9f] = 8'h00;
buff [16'h00_a0] = 8'hB5;
buff [16'h00_a1] = 8'h0F;
buff [16'h00_a2] = 8'h02;
buff [16'h00_a3] = 8'h00;
buff [16'h00_a4] = 8'h56;
buff [16'h00_a5] = 8'h74;
buff [16'h00_a6] = 8'hFF;
buff [16'h00_a7] = 8'h2C;
buff [16'h00_a8] = 8'hFC;
buff [16'h00_a9] = 8'hE4;
buff [16'h00_aa] = 8'h3D;
buff [16'h00_ab] = 8'hFD;
buff [16'h00_ac] = 8'hEC;
buff [16'h00_ad] = 8'h24;
buff [16'h00_ae] = 8'h00;
buff [16'h00_af] = 8'hF5;
buff [16'h00_b0] = 8'h82;
buff [16'h00_b1] = 8'hED;
buff [16'h00_b2] = 8'h34;
buff [16'h00_b3] = 8'h00;
buff [16'h00_b4] = 8'hF5;
buff [16'h00_b5] = 8'h83;
buff [16'h00_b6] = 8'hE0;
buff [16'h00_b7] = 8'hFC;
buff [16'h00_b8] = 8'h7D;
buff [16'h00_b9] = 8'h00;
buff [16'h00_ba] = 8'hBC;
buff [16'h00_bb] = 8'hFF;
buff [16'h00_bc] = 8'h05;
buff [16'h00_bd] = 8'hBD;
buff [16'h00_be] = 8'h00;
buff [16'h00_bf] = 8'h02;
buff [16'h00_c0] = 8'h80;
buff [16'h00_c1] = 8'h02;
buff [16'h00_c2] = 8'h8A;
buff [16'h00_c3] = 8'h90;
buff [16'h00_c4] = 8'h0A;
buff [16'h00_c5] = 8'hBA;
buff [16'h00_c6] = 8'h00;
buff [16'h00_c7] = 8'h01;
buff [16'h00_c8] = 8'h0B;
buff [16'h00_c9] = 8'h02;
buff [16'h00_ca] = 8'h00;
buff [16'h00_cb] = 8'h42;
buff [16'h00_cc] = 8'h75;
buff [16'h00_cd] = 8'h80;
buff [16'h00_ce] = 8'h01;
buff [16'h00_cf] = 8'h80;
buff [16'h00_d0] = 8'hFE;
buff [16'h00_d1] = 8'h22;
buff [16'h00_d2] = 8'h75;
buff [16'h00_d3] = 8'h82;
buff [16'h00_d4] = 8'h00;
buff [16'h00_d5] = 8'h22;
buff [16'h00_d6] = 8'h75;
buff [16'h00_d7] = 8'h81;
buff [16'h00_d8] = 8'h07;
buff [16'h00_d9] = 8'h12;
buff [16'h00_da] = 8'h00;
buff [16'h00_db] = 8'hD2;
buff [16'h00_dc] = 8'hE5;
buff [16'h00_dd] = 8'h82;
buff [16'h00_de] = 8'h60;
buff [16'h00_df] = 8'h03;
buff [16'h00_e0] = 8'h02;
buff [16'h00_e1] = 8'h00;
buff [16'h00_e2] = 8'h33;
buff [16'h00_e3] = 8'h02;
buff [16'h00_e4] = 8'h00;
buff [16'h00_e5] = 8'h33;
end
always @(posedge clk)
begin
data1 <= #1 buff [addr];
data2 <= #1 buff [addr+1];
data3 <= #1 buff [addr+2];
end
endmodule |
module oc8051_fpga_tb;
reg rst, clk, int1, int2, int3;
wire sw1, sw2, sw3, sw4, int_act;
wire [7:0] p0_out, p1_out, p2_out, p3_out, data_out;
wire [13:0] dispout;
wire [15:0] ext_addr;
oc8051_fpga_top oc8051_fpga_top1(.clk(clk), .rst(rst), .int1(int1), .int2(int2), .int3(int3), .sw1(sw1), .sw2(sw2), .sw3(sw3), .sw4(sw4),
.int_act(int_act), .dispout(dispout), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out), .data_out(data_out),
.ext_addr(ext_addr));
initial begin
clk= 1'b0;
rst= 1'b0;
int1= 1'b1;
int2= 1'b1;
int3= 1'b1;
#22
rst = 1'b1;
#1000
int2= 1'b0;
#100
int2= 1'b1;
#40000
int3= 1'b0;
#100
int3= 1'b1;
#40000
rst = 1'b0;
#20
$finish;
end
always clk = #5 ~clk;
initial $dumpvars;
//initial $monitor("time ",$time," rst ",rst, " int1 ", int1, " int2 ", int2, " int3 ", int3, " sw1 ", sw1, " sw2 ", sw2, " sw3 ", sw3, " sw4 ", sw4, " int act ", int_act, " p0_out %h", p0_out);
initial $monitor("time ",$time," rst ",rst, " int1 ", int1, " int2 ", int2, " int3 ", int3, " int act ", int_act, " p0_out %h", p0_out);
endmodule |
module oc8051_xram (clk, rst, wr, addr, data_in, data_out, ack, stb);
//
// external data ram for simulation. part of oc8051_tb
// it's tehnology dependent
//
// clk (in) clock
// addr (in) addres
// data_in (out) data input
// data_out (in) data output
// wr (in) write
// ack (out) acknowlage
// stb (in) strobe
//
parameter DELAY=1;
input clk, wr, stb, rst;
input [7:0] data_in;
input [15:0] addr;
output [7:0] data_out;
output ack;
reg ackw, ackr;
reg [7:0] data_out;
reg [2:0] cnt;
//
// buffer
reg [7:0] buff [65535:0]; //64kb
//reg [7:0] buff [8388607:0]; //8Mb
assign ack = ackw || ackr;
//
// writing to ram
always @(posedge clk or posedge rst)
begin
if (rst)
ackw <= #1 1'b0;
else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
buff[addr] <= #1 data_in;
ackw <= #1 1'b1;
end else ackw <= #1 1'b0;
end
always @(posedge clk or posedge rst)
if (rst)
ackr <= #1 1'b0;
else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
data_out <= #1 buff[addr];
ackr <= #1 1'b1;
end else begin
ackr <= #1 1'b0;
data_out <= #1 8'h00;
end
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= #1 DELAY;
else if (cnt==3'b000)
cnt <= #1 DELAY;
else if (stb)
cnt <= #1 cnt - 3'b001;
else cnt <= #1 DELAY;
end
endmodule |
module oc8051_serial (clk, rst, rxd, txd);
parameter FREQ = 25000;
parameter BRATE = 9.6;
parameter DELAY = FREQ/BRATE;
input clk,
rst,
rxd;
output txd;
reg txd,
transmit;
reg txd_start;
reg [8:0] txd_data;
reg [15:0] count;
reg [8:0] txd_buf;
reg [63:0] wait_t;
reg [7:0] buff [0:65535];
reg receive;
reg [7:0] rxd_buf;
reg [63:0] wait_r;
reg [7:0] tmp;
reg receive_r;
reg rxd_r;
initial
begin
$readmemh("../../../serial.txt", buff);
end
/*
always @(posedge clk or posedge rst)
if (rst) begin
count <= #1 16'h0;
end else begin
count <= #1 count + 16'h1;
$display (" serial h: %h d: %d count: %h", buff[count], buff[count], count);
end
*/
always @(posedge clk or posedge rst)
if (rst) begin
wait_t <= #1 64'h0;
txd_buf <= #1 9'h1ff;
txd <= #1 1'b1;
transmit <= #1 1'b0;
end else if (txd_start) begin
transmit <= #1 1'b1;
txd_buf <= #1 {txd_data, 1'b0};
end else if ((wait_t >= DELAY) & transmit) begin
wait_t <= #1 64'h0;
{txd_buf, txd} <= #1 {1'b1, txd_buf};
transmit <= #1 ~&{txd_buf, txd};
end else begin
wait_t <= #1 wait_t + 64'h1;
end
always @(posedge clk or posedge rst)
if (rst) begin
wait_r <= #1 64'h0;
rxd_buf <= #1 8'hff;
rxd_r <= #1 1'b0;
receive <= #1 1'b0;
end else if (rxd_r & !rxd & !receive) begin
wait_r <= #1 DELAY / 2;
rxd_r <= #1 1'b0;
receive <= #1 1'b1;
rxd_buf <= #1 8'hff;
end else if ((wait_r >= DELAY) & receive) begin
wait_r <= #1 64'h0;
{rxd_buf, receive} <= #1 {rxd, rxd_buf};
end else if (receive) begin
wait_r <= #1 wait_r + 64'h1;
end else begin
rxd_r <= #1 rxd;
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
receive_r <= #1 1'b0;
txd_start <= #1 1'b0;
txd_data <= #1 8'h0;
tmp <= #1 8'h0;
end else if (!receive & receive_r) begin
receive_r <= #1 1'b0;
if ((tmp==8'h3f) && (rxd_buf==8'h20)) begin
txd_start <= #1 1'b1;
txd_data <= #1 8'h33;
end else if (rxd_buf==8'h33) begin
txd_start <= #1 1'b1;
txd_data <= #1 8'h36;
end else if (rxd_buf==8'h36) begin
txd_start <= #1 1'b1;
txd_data <= #1 8'h0a;
end
tmp <= #1 rxd_buf;
$display (" receive: %s , %h", rxd_buf, rxd_buf);
end else begin
txd_start <= #1 1'b0;
receive_r <= #1 receive;
end
end
endmodule |
module oc8051_xrom (rst, clk, addr, data, stb_i, cyc_i, ack_o);
parameter DELAY=5;
input rst, clk, stb_i, cyc_i;
input [15:0] addr;
output ack_o;
output [31:0] data;
reg ack_o;
reg [31:0] data;
reg [7:0] buff [0:65535];
//reg [7:0] buff [8388607:0];
reg [2:0] cnt;
integer i;
initial
begin
// for (i=0; i<65536; i=i+1)
// buff [i] = 8'h00;
$readmemh("../../../bench/in/oc8051_xrom.in", buff);
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
data <= #1 31'h0;
ack_o <= #1 1'b0;
end else if (stb_i && ((DELAY==3'b000) || (cnt==3'b000))) begin
data <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
ack_o <= #1 1'b1;
end else
ack_o <= #1 1'b0;
end
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= #1 DELAY;
else if (cnt == 3'b000)
cnt <= #1 DELAY;
else if (stb_i)
cnt <= #1 cnt - 3'b001;
else cnt <= #1 DELAY;
end
endmodule |
module oc8051_tb;
//parameter FREQ = 20000; // frequency in kHz
parameter FREQ = 12000; // frequency in kHz
parameter DELAY = 500000/FREQ;
reg rst, clk;
reg [7:0] p0_in, p1_in, p2_in;
wire [15:0] ext_addr, iadr_o;
wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i;
wire ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o, t2, t2ex;
wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
wire wbi_err_i, wbd_err_i;
`ifdef OC8051_XILINX_RAMB
reg [31:0] idat_i;
`else
wire [31:0] idat_i;
`endif
///
/// buffer for test vectors
///
//
// buffer
reg [23:0] buff [0:255];
reg ea [0:1];
integer num;
assign wbd_err_i = 1'b0;
assign wbi_err_i = 1'b0;
//
// oc8051 controller
//
oc8051_top oc8051_top_1(.wb_rst_i(rst), .wb_clk_i(clk),
.int0_i(int0), .int1_i(int1),
.wbd_dat_i(data_in), .wbd_we_o(write), .wbd_dat_o(data_out),
.wbd_adr_o(ext_addr), .wbd_err_i(wbd_err_i),
.wbd_ack_i(ack_i), .wbd_stb_o(stb_o), .wbd_cyc_o(cyc_o),
.wbi_adr_o(iadr_o), .wbi_stb_o(istb_o), .wbi_ack_i(iack_i),
.wbi_cyc_o(icyc_o), .wbi_dat_i(idat_i), .wbi_err_i(wbi_err_i),
`ifdef OC8051_PORTS
`ifdef OC8051_PORT0
.p0_i(p0_in),
.p0_o(p0_out),
`endif
`ifdef OC8051_PORT1
.p1_i(p1_in),
.p1_o(p1_out),
`endif
`ifdef OC8051_PORT2
.p2_i(p2_in),
.p2_o(p2_out),
`endif
`ifdef OC8051_PORT3
.p3_i(p3_in),
.p3_o(p3_out),
`endif
`endif
`ifdef OC8051_UART
.rxd_i(rxd), .txd_o(txd),
`endif
`ifdef OC8051_TC01
.t0_i(t0), .t1_i(t1),
`endif
`ifdef OC8051_TC2
.t2_i(t2), .t2ex_i(t2ex),
`endif
.ea_in(ea[0]));
//
// external data ram
//
oc8051_xram oc8051_xram1 (.clk(clk), .rst(rst), .wr(write_xram), .addr(ext_addr), .data_in(data_out), .data_out(data_out_xram), .ack(ack_xram), .stb(stb_o));
defparam oc8051_xram1.DELAY = 2;
`ifdef OC8051_SERIAL
//
// test programs with serial interface
//
oc8051_serial oc8051_serial1(.clk(clk), .rst(rst), .rxd(txd), .txd(rxd));
defparam oc8051_serial1.FREQ = FREQ;
//defparam oc8051_serial1.BRATE = 9.6;
defparam oc8051_serial1.BRATE = 4.8;
`else
//
// external uart
//
oc8051_uart_test oc8051_uart_test1(.clk(clk), .rst(rst), .addr(ext_addr[7:0]), .wr(write_uart),
.wr_bit(p3_out[0]), .data_in(data_out), .data_out(data_out_uart), .bit_out(bit_out), .rxd(txd),
.txd(rxd), .ow(p3_out[1]), .intr(int_uart), .stb(stb_o), .ack(ack_uart));
`endif
`ifdef OC8051_XILINX_RAMB
`include "oc8051_rom_values.v"
//
// exteranl program rom
//
//
// rom 0
//
wire [11:0] adr0, adr1;
wire [15:0] dat0, dat1;
assign adr0 = iadr_o[13:2] + {11'h0, iadr_o[1]};
assign adr1 = iadr_o[13:2];
rom_8kx16_top rom_8kx16_top_0
(
// WISHBONE slave
.wb_clk_i(clk),
.wb_rst_i(rst),
.wb_dat_i(16'h0),
.wb_dat_o(dat0),
.wb_adr_i(adr0),
.wb_sel_i(2'b11),
.wb_we_i(1'b0),
.wb_cyc_i(icyc_o),
.wb_stb_i(istb_o),
.wb_ack_o(iack_i),
.wb_err_o(wbi_err_i)
);
rom_8kx16_top rom_8kx16_top_1
(
// WISHBONE slave
.wb_clk_i(clk),
.wb_rst_i(rst),
.wb_dat_i(16'h0),
.wb_dat_o(dat1),
.wb_adr_i(adr1),
.wb_sel_i(2'b11),
.wb_we_i(1'b0),
.wb_cyc_i(icyc_o),
.wb_stb_i(istb_o),
.wb_ack_o(iack_i),
.wb_err_o(wbi_err_i)
);
defparam rom_8kx16_top_0.awidth = 12;
defparam rom_8kx16_top_1.awidth = 12;
always @(iadr_o[1:0] or dat0 or dat1)
begin
case (iadr_o[1:0])
2'b00: idat_i = {8'h0, dat1[7:0], dat0};
2'b01: idat_i = {8'h0, dat1, dat0[15:8]};
2'b10: idat_i = {8'h0, dat0[7:0], dat1};
default: idat_i = {8'h0, dat0, dat1[15:8]};
endcase
end
`else
oc8051_xrom oc8051_xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idat_i),
.stb_i(istb_o), .cyc_i(icyc_o), .ack_o(iack_i));
defparam oc8051_xrom1.DELAY = 0;
`endif
//
//
//
assign write_xram = p3_out[7] & write;
assign write_uart = !p3_out[7] & write;
assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
assign ack_i = p3_out[7] ? ack_xram : ack_uart;
assign p3_in = {6'h0, bit_out, int_uart};
assign t0 = p3_out[5];
assign t1 = p3_out[6];
assign int0 = p3_out[3];
assign int1 = p3_out[4];
assign t2 = p3_out[5];
assign t2ex = p3_out[2];
initial begin
rst= 1'b1;
p0_in = 8'h00;
p1_in = 8'h00;
p2_in = 8'h00;
#220
rst = 1'b0;
#80000000
$display("time ",$time, "\n faulire: end of time\n \n");
$display("");
$finish;
end
initial
begin
clk = 0;
forever #DELAY clk <= ~clk;
end
always @(ext_addr or write or stb_o or data_out)
begin
if ((ext_addr==16'h0010) & write & stb_o) begin
if (data_out==8'h7f) begin
$display("");
$display("time ",$time, " Passed");
$display("");
$finish;
end else begin
$display("");
$display("time ",$time," Error: %h", data_out);
$display("");
$finish;
end
end
end
initial
$readmemb("../oc8051_ea.in", ea);
endmodule |
module PLL (CLKI, RST, CLKOP, LOCK)/* synthesis NGD_DRC_MASK=1 */;
input wire CLKI;
input wire RST;
output wire CLKOP;
output wire LOCK;
wire CLKOP_t;
wire scuba_vlo;
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
defparam PLLInst_0.MRST_ENA = "DISABLED" ;
defparam PLLInst_0.PLLRST_ENA = "ENABLED" ;
defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
defparam PLLInst_0.CLKOS_FPHASE = 0 ;
defparam PLLInst_0.CLKOS_CPHASE = 0 ;
defparam PLLInst_0.CLKOP_FPHASE = 0 ;
defparam PLLInst_0.CLKOP_CPHASE = 14 ;
defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
defparam PLLInst_0.FRACN_DIV = 0 ;
defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
defparam PLLInst_0.CLKOS3_DIV = 1 ;
defparam PLLInst_0.CLKOS2_DIV = 1 ;
defparam PLLInst_0.CLKOS_DIV = 1 ;
defparam PLLInst_0.CLKOP_DIV = 15 ;
defparam PLLInst_0.CLKFB_DIV = 3 ;
defparam PLLInst_0.CLKI_DIV = 1 ;
defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
.PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
.LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
.RST(RST), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
.ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo),
.ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo),
.PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
.PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
.PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
.PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
.PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(),
.LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(), .PLLACK(),
.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
.PLLDATO2(), .PLLDATO1(), .PLLDATO0())
/* synthesis FREQUENCY_PIN_CLKOP="36.000000" */
/* synthesis FREQUENCY_PIN_CLKI="12.000000" */
/* synthesis ICP_CURRENT="8" */
/* synthesis LPF_RESISTOR="8" */;
assign CLKOP = CLKOP_t;
// exemplar begin
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 36.000000
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 12.000000
// exemplar attribute PLLInst_0 ICP_CURRENT 8
// exemplar attribute PLLInst_0 LPF_RESISTOR 8
// exemplar end
endmodule |
module PLL (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire7;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [2:2] sub_wire6 = sub_wire3[2:2];
wire [1:1] sub_wire5 = sub_wire3[1:1];
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire c1 = sub_wire5;
wire c2 = sub_wire6;
wire locked = sub_wire7;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire7),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 8,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 6,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 83333,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=PLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule |
module PLL (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module PulseRain_RV2T_MCU (
//=====================================================================
// clock and reset
//=====================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=====================================================================
// Interface Onchip Debugger
//=====================================================================
//== input wire run1_pause0,
input wire ocd_read_enable,
input wire ocd_write_enable,
input wire [`MEM_ADDR_BITS - 1 : 0] ocd_rw_addr,
input wire [`XLEN - 1 : 0] ocd_write_word,
output wire ocd_mem_enable_out,
output wire [`XLEN - 1 : 0] ocd_mem_word_out,
input wire [`REG_ADDR_BITS - 1 : 0] ocd_reg_read_addr,
input wire ocd_reg_we,
input wire [`REG_ADDR_BITS - 1 : 0] ocd_reg_write_addr,
input wire [`XLEN - 1 : 0] ocd_reg_write_data,
//=====================================================================
// UART
//=====================================================================
output wire TXD,
//=====================================================================
// Interface for init/start
//=====================================================================
input wire start,
input wire [`PC_BITWIDTH - 1 : 0] start_address,
output wire processor_paused,
output wire [`XLEN - 1 : 0] peek_pc,
output wire [`XLEN - 1 : 0] peek_ir,
output wire [`XLEN_BYTES - 1 : 0] peek_mem_write_en,
output wire [`XLEN - 1 : 0] peek_mem_write_data,
output wire [`MEM_ADDR_BITS - 1 : 0] peek_mem_addr
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire [`MEM_ADDR_BITS - 1 : 0] mem_addr;
reg [`MEM_ADDR_BITS - 1 : 0] mem_addr_d1;
wire [`XLEN_BYTES - 1 : 0] mem_write_en;
wire [`XLEN - 1 : 0] mem_write_data;
wire [`XLEN - 1 : 0] mem_read_data;
wire [15 : 0] dout_high;
wire [15 : 0] dout_low;
wire start_TX;
wire [7 : 0] tx_data;
wire tx_active;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// processor core
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
PulseRain_RV2T_core PulseRain_RV2T_core_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.ocd_read_enable (ocd_read_enable),
.ocd_write_enable (ocd_write_enable),
.ocd_rw_addr (ocd_rw_addr),
.ocd_write_word (ocd_write_word),
.ocd_mem_enable_out (ocd_mem_enable_out),
.ocd_mem_word_out (ocd_mem_word_out),
.ocd_reg_read_addr (ocd_reg_read_addr),
.ocd_reg_we (ocd_reg_we),
.ocd_reg_write_addr (ocd_reg_write_addr),
.ocd_reg_write_data (ocd_reg_write_data),
.start_TX (start_TX),
.tx_data (tx_data),
.tx_active (tx_active),
.start (start),
.start_address (start_address),
.peek_pc (peek_pc),
.peek_ir (peek_ir),
.mem_addr (mem_addr),
.mem_write_en (mem_write_en),
.mem_write_data (mem_write_data),
.mem_read_data (mem_read_data),
.processor_paused (processor_paused));
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// memory
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
single_port_ram #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_high_i (
.addr (mem_addr),
.din (mem_write_data [31 : 16]),
.write_en (mem_write_en[3 : 2]),
.clk (clk),
.dout (dout_high));
single_port_ram #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_low_i (
.addr (mem_addr),
.din (mem_write_data [15 : 0]),
.write_en (mem_write_en[1 : 0]),
.clk (clk),
.dout (dout_low));
/*
single_port_ram_sim_high #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_high_i (
.addr (mem_addr),
.din (mem_write_data [31 : 16]),
.write_en (mem_write_en[3 : 2]),
.clk (clk),
.dout (dout_high));
single_port_ram_sim_low #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_low_i (
.addr (mem_addr),
.din (mem_write_data [15 : 0]),
.write_en (mem_write_en[1 : 0]),
.clk (clk),
.dout (dout_low));
*/
// assign mem_read_data = {(`UART_TX_ADDR == {mem_addr_d1 [`MEM_ADDR_BITS - 1 : 0], 2'b00}) ? tx_active : dout_high[15], dout_high [14 : 0], dout_low};
assign mem_read_data = {dout_high, dout_low};
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
mem_addr_d1 <= 0;
end else begin
mem_addr_d1 <= mem_addr;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// peripherals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
/* verilator lint_off WIDTH */
UART_TX #(.STABLE_TIME(`UART_STABLE_COUNT), .BAUD_PERIOD_BITS(`UART_TX_BAUD_PERIOD_BITS)) UART_TX_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.start_TX (start_TX),
.baud_rate_period_m1 (`UART_TX_BAUD_PERIOD - 1),
//.baud_rate_period_m1 ((`UART_TX_BAUD_PERIOD - 1)),
.SBUF_in (tx_data),
.tx_active (tx_active),
.TXD (TXD));
assign peek_mem_write_en = mem_write_en;
assign peek_mem_write_data = mem_write_data;
assign peek_mem_addr = mem_addr;
endmodule |
module single_port_ram_8bit #(parameter ADDR_WIDTH = 14) (
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [7 : 0] din,
input wire write_en,
input wire clk,
output wire [7 : 0] dout
);
reg [ADDR_WIDTH - 1 : 0] addr_reg;
reg [7:0] mem [0 : (2**ADDR_WIDTH) - 1] /* synthesis syn_ramstyle="lsram" */ ;
assign dout = mem[addr_reg];
always@(posedge clk) begin
addr_reg <= addr;
if(write_en) begin
mem[addr] <= din;
end
end
endmodule |
module single_port_ram #(parameter ADDR_WIDTH = 14, DATA_WIDTH = 16) (
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [DATA_WIDTH - 1 : 0] din,
input wire [DATA_WIDTH / 8 - 1 : 0] write_en,
input wire clk,
output wire [DATA_WIDTH - 1 : 0] dout
);
wire [DATA_WIDTH - 1 : 0] dout_1st;
wire [DATA_WIDTH - 1 : 0] dout_2nd;
reg [ADDR_WIDTH - 1 : 0] addr_reg;
always @(posedge clk) begin
addr_reg <= addr;
end
genvar i;
generate
if (`MEM_SIZE_IN_BYTES == (48 * 1024)) begin: gen_if_proc
for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) begin : gen_for_proc1
single_port_ram_8bit #(.ADDR_WIDTH (ADDR_WIDTH - 1)) ram_8bit_1st (
.addr (addr[ADDR_WIDTH - 2 : 0]),
.din (din [(i + 1) * 8 - 1 : i * 8]),
.write_en (write_en[i] & (~addr[ADDR_WIDTH - 1])),
.clk (clk),
.dout (dout_1st [(i + 1) * 8 - 1 : i * 8]));
end
for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) begin : gen_for_proc2
single_port_ram_8bit #(.ADDR_WIDTH (ADDR_WIDTH - 2)) ram_8bit_2nd (
.addr (addr[ADDR_WIDTH - 3 : 0]),
.din (din [(i + 1) * 8 - 1 : i * 8]),
.write_en (write_en[i] & (addr[ADDR_WIDTH - 1])),
.clk (clk),
.dout (dout_2nd [(i + 1) * 8 - 1 : i * 8]));
end
assign dout = addr_reg [ADDR_WIDTH - 1] ? dout_2nd : dout_1st;
end else begin
for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) begin : gen_for_proc
single_port_ram_8bit #(.ADDR_WIDTH (ADDR_WIDTH)) ram_8bit (
.addr (addr),
.din (din [(i + 1) * 8 - 1 : i * 8]),
.write_en (write_en[i]),
.clk (clk),
.dout (dout [(i + 1) * 8 - 1 : i * 8]));
end
end
endgenerate
endmodule |
module dual_port_ram #(parameter ADDR_WIDTH = 5, DATA_WIDTH = 32) (
input wire [ADDR_WIDTH - 1 : 0] waddr,
input wire [ADDR_WIDTH - 1 : 0] raddr,
input wire [DATA_WIDTH - 1 : 0] din,
input wire write_en,
input wire clk,
output wire [DATA_WIDTH - 1 : 0] dout
);
reg [ADDR_WIDTH - 1 : 0] raddr_reg;
reg [DATA_WIDTH - 1 : 0] mem [0 : (2**ADDR_WIDTH) - 1] /* synthesis syn_ramstyle="uram" */;
assign dout = mem[raddr_reg] ;
always @(posedge clk) begin
raddr_reg <= raddr;
end
always@ (posedge clk) begin
if (write_en) begin
mem[waddr] <= din;
end
end
endmodule |
module SP256K (
input wire [13:0] AD,
input wire [15:0] DI,
input wire [3:0] MASKWE,
input wire WE,
input wire CS,
input wire CK,
input wire STDBY,
input wire SLEEP,
input wire PWROFF_N,
output wire [15:0] DO
);
wire [13 : 0] addr;
wire [15 : 0] din;
wire [1 : 0] write_en;
wire clk;
reg [15 : 0] dout;
assign clk = CK;
assign DO = dout;
assign addr = AD;
assign din = DI;
assign write_en = {WE & MASKWE [2], WE & MASKWE [0]};
reg [15 : 0] mem [(1<<14)-1:0];
genvar i;
generate
for (i = 0; i < 2; i = i + 1) begin : gen_proc
always @(posedge clk) begin
if (write_en[i]) begin
mem[(addr)][8 * (i + 1) - 1 : 8 * i] <= din[8 * (i + 1) - 1 : 8 * i];
end
end
end
endgenerate
always @(posedge clk) begin
dout <= mem[addr];
end
endmodule |
module single_port_ram_lattice #(parameter ADDR_WIDTH = 14, DATA_WIDTH = 16) (
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [DATA_WIDTH - 1 : 0] din,
input wire [DATA_WIDTH / 8 - 1 : 0] write_en,
input wire clk,
output wire [DATA_WIDTH - 1 : 0] dout
);
single_port_ram_lattice_16Kx16 one_blk (
.addr (addr),
.din (din),
.write_en (write_en),
.clk (clk),
.dout (dout));
endmodule |
module single_port_ram #(parameter ADDR_WIDTH = 14, DATA_WIDTH = 16) (
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [DATA_WIDTH - 1 : 0] din,
input wire [DATA_WIDTH / 8 - 1 : 0] write_en,
input wire clk,
output wire [DATA_WIDTH - 1 : 0] dout
);
single_port_ram_lattice #(.ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH)) single_port_ram_lattice_i (
.addr (addr),
.din (din),
.write_en (write_en),
.clk (clk),
.dout (dout));
endmodule |
module dual_port_ram #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
input wire [ADDR_WIDTH - 1 : 0] waddr,
input wire [ADDR_WIDTH - 1 : 0] raddr,
input wire [DATA_WIDTH - 1 : 0] din,
input wire write_en,
input wire clk,
output wire [DATA_WIDTH - 1 : 0] dout
);
dual_port_ram_lattice #(.ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH)) dual_port_ram_lattice_i (
.waddr (waddr),
.raddr (raddr),
.din (din),
.write_en (write_en),
.wclk (clk),
.rclk (clk),
.dout (dout) );
endmodule |
module single_port_ram_lattice_16Kx16 (
input wire [13 : 0] addr,
input wire [15 : 0] din,
input wire [1 : 0] write_en,
input wire clk,
output wire [15 : 0] dout
);
SP256K spram_i (
.AD (addr), // I
.DI (din), // I
.MASKWE ({write_en[1], write_en[1], write_en[0], write_en[0]}), // I
.WE (|write_en), // I
.CS (1'b1), // I
.CK (clk), // I
.STDBY (1'b0), // I
.SLEEP (1'b0), // I
.PWROFF_N (1'b1), // I
.DO (dout) // O
);
endmodule |
module dual_port_ram_lattice #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
input wire [ADDR_WIDTH - 1 : 0] waddr,
input wire [ADDR_WIDTH - 1 : 0] raddr,
input wire [DATA_WIDTH - 1 : 0] din,
input wire write_en,
input wire wclk,
input wire rclk,
output reg [DATA_WIDTH - 1 : 0] dout
);
reg [DATA_WIDTH - 1 : 0] mem [(1<<ADDR_WIDTH)-1:0];
always @(posedge wclk) begin// Write memory.
if (write_en) begin
mem[waddr] <= din; // Using write address bus.
end
end
always @(posedge rclk) begin // Read memory.
dout <= mem[raddr]; // Using read address bus.
end
endmodule |
module single_port_ram #(parameter ADDR_WIDTH = 12, DATA_WIDTH = 16) (
input wire clk,
input wire [ADDR_WIDTH - 1 : 0] addr,
input wire [DATA_WIDTH - 1 : 0] din,
input wire [DATA_WIDTH / 8 - 1 : 0] write_en,
output reg [DATA_WIDTH - 1 : 0] dout
);
reg [7 : 0] mem_hi [(1<<ADDR_WIDTH)-1:0];
reg [7 : 0] mem_low [(1<<ADDR_WIDTH)-1:0];
always @(posedge clk) begin
if (write_en[0]) begin
mem_low[addr] <= din[7 : 0];
end
if (write_en[1]) begin
mem_hi[addr] <= din[15 : 8];
end
end
always @(posedge clk) begin
dout <= {mem_hi[addr], mem_low[addr]};
end
endmodule |
module UART_TX #(parameter STABLE_TIME = `UART_STABLE_COUNT, BAUD_PERIOD_BITS= $clog2(`UART_TX_BAUD_PERIOD)) (
//=======================================================================
// clock / reset
//=======================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=======================================================================
// host interface
//=======================================================================
input wire start_TX,
input wire [BAUD_PERIOD_BITS - 1 : 0] baud_rate_period_m1,
input wire [7 : 0] SBUF_in,
//=======================================================================
// device interface
//=======================================================================
output wire tx_active,
output wire TXD
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg [$clog2(STABLE_TIME + 1) - 1 : 0] stable_counter;
reg [BAUD_PERIOD_BITS - 1 : 0] baud_rate_counter;
reg baud_rate_pulse;
reg [BAUD_PERIOD_BITS - 1 : 0] counter;
reg ctl_reset_stable_counter;
reg ctl_save_counter;
reg [$clog2 (8 + 4) - 1 : 0] data_counter;
reg ctl_reset_data_counter;
reg ctl_inc_data_counter;
reg [8 + 2 : 0] tx_data;
reg ctl_load_tx_data;
reg ctl_shift_tx_data;
reg ctl_set_TI;
reg ctl_counter_reset;
reg tx_start_flag;
reg ctl_set_tx_start_flag;
reg ctl_clear_tx_start_flag;
reg ctl_tx_idle;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// baud_rate_pulse
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : baud_rate_counter_proc
if (!reset_n) begin
baud_rate_counter <= 0;
end else if (sync_reset) begin
baud_rate_counter <= 0;
end else if (baud_rate_counter == baud_rate_period_m1) begin
baud_rate_counter <= 0;
end else begin
baud_rate_counter <= baud_rate_counter + 1;
end
end
always @(posedge clk, negedge reset_n) begin : baud_rate_pulse_proc
if (!reset_n) begin
baud_rate_pulse <= 0;
end else if (baud_rate_counter == 1) begin
baud_rate_pulse <= 1'b1;
end else begin
baud_rate_pulse <= 0;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// tx_data
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : tx_data_proc
if (!reset_n) begin
tx_data <= 0;
end else if (ctl_load_tx_data) begin
tx_data <= {1'b1, SBUF_in, 2'b01};
end else if (ctl_shift_tx_data) begin
tx_data <= {1'b1, tx_data [10 : 1]};
end
end
assign TXD = tx_data [0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// counter
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : counter_proc
if (!reset_n) begin
counter <= 0;
end else if (sync_reset | ctl_counter_reset) begin
counter <= 0;
end else if (baud_rate_pulse) begin
counter <= 0;
end else begin
counter <= counter + 1;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// data_counter
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : data_counter_proc
if (!reset_n) begin
data_counter <= 0;
end else if (ctl_reset_data_counter) begin
data_counter <= 0;
end else if (ctl_inc_data_counter) begin
data_counter <= data_counter + 1;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// stable_counter
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : stable_counter_proc
if (!reset_n) begin
stable_counter <= 0;
end else if (ctl_reset_stable_counter) begin
stable_counter <= 0;
end else begin
stable_counter <= stable_counter + 1;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// tx_start_flag
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : tx_start_flag_proc
if (!reset_n) begin
tx_start_flag <= 0;
end else if (ctl_clear_tx_start_flag) begin
tx_start_flag <= 0;
end else if (ctl_set_tx_start_flag) begin
tx_start_flag <= 1'b1;
end
end
assign tx_active = ~ctl_tx_idle;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam S_IDLE = 0, S_TX_START = 1, S_TX_DATA = 2, S_TX_WAIT = 3, S_TX_WAIT2 =4;
reg [4 : 0] current_state = 0, next_state;
// Declare states
always @(posedge clk, negedge reset_n) begin : state_machine_reg
if (!reset_n) begin
current_state <= 0;
end else if (sync_reset) begin
current_state <= 0;
end else begin
current_state <= next_state;
end
end
// FSM main body
always @(*) begin : state_machine_comb
next_state = 0;
ctl_reset_stable_counter = 0;
ctl_save_counter = 0;
ctl_reset_data_counter = 0;
ctl_inc_data_counter = 0;
ctl_load_tx_data = 0;
ctl_shift_tx_data = 0;
ctl_set_TI = 0;
ctl_counter_reset = 0;
ctl_set_tx_start_flag = 0;
ctl_clear_tx_start_flag = 0;
ctl_tx_idle = 0;
case (1'b1) // synthesis parallel_case
current_state[S_IDLE]: begin
ctl_load_tx_data = 1'b1;
ctl_reset_data_counter = 1'b1;
ctl_counter_reset = 1'b1;
ctl_clear_tx_start_flag = 1'b1;
ctl_tx_idle = 1'b1;
if (start_TX) begin
next_state [S_TX_START] = 1'b1;
end else begin
next_state [S_IDLE] = 1'b1;
end
end
current_state [S_TX_START] : begin
ctl_reset_data_counter = 1'b1;
if (baud_rate_pulse) begin
if (tx_start_flag) begin
ctl_shift_tx_data = 1'b1;
next_state [S_TX_DATA] = 1'b1;
end else begin
ctl_set_tx_start_flag = 1'b1;
next_state [S_TX_START] = 1'b1;
end
end else begin
next_state [S_TX_START] = 1'b1;
end
end
current_state [S_TX_DATA] : begin
if (data_counter == (8 + 3)) begin
ctl_set_TI = 1'b1;
next_state [S_IDLE] = 1;
end else if (baud_rate_pulse) begin
ctl_shift_tx_data = 1'b1;
ctl_inc_data_counter = 1'b1;
next_state [S_TX_DATA] = 1;
end else begin
next_state [S_TX_DATA] = 1;
end
end
current_state [S_TX_WAIT] : begin
ctl_load_tx_data = 1'b1;
if (baud_rate_pulse) begin
next_state [S_TX_WAIT2] = 1;
end else begin
next_state [S_TX_WAIT] = 1;
end
end
current_state [S_TX_WAIT2] : begin
if (baud_rate_pulse) begin
ctl_set_TI = 1'b1;
next_state [S_IDLE] = 1;
end else begin
ctl_load_tx_data = 1'b1;
next_state [S_TX_WAIT2] = 1;
end
end
default: begin
next_state[S_IDLE] = 1'b1;
end
endcase
end
endmodule |
module RV2T_reg_file (
//=======================================================================
// clock / reset
//=======================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=======================================================================
// register read / write
//=======================================================================
input wire read_enable,
input wire [`REG_ADDR_BITS - 1 : 0] read_rs1_addr,
input wire [`REG_ADDR_BITS - 1 : 0] read_rs2_addr,
output reg read_en_out,
output wire [`XLEN - 1 : 0] read_rs1_data_out,
output wire [`XLEN - 1 : 0] read_rs2_data_out,
input wire write_enable,
input wire [`REG_ADDR_BITS - 1 : 0] write_addr,
input wire [`XLEN - 1 : 0] write_data_in
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire [`XLEN - 1 : 0] read_rs1_data_out_i;
wire [`XLEN - 1 : 0] read_rs2_data_out_i;
reg write_enable_d1;
reg [`XLEN - 1 : 0] write_data_in_d1;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// datapath
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
dual_port_ram #(.ADDR_WIDTH (`REG_ADDR_BITS), .DATA_WIDTH (`XLEN)) single_clk_ram_rs1 (
.waddr (write_addr),
.raddr (read_rs1_addr),
.din (write_data_in),
.write_en (write_enable),
.clk (clk),
.dout (read_rs1_data_out_i) );
dual_port_ram #(.ADDR_WIDTH (`REG_ADDR_BITS), .DATA_WIDTH (`XLEN)) single_clk_ram_rs2 (
.waddr (write_addr),
.raddr (read_rs2_addr),
.din (write_data_in),
.write_en (write_enable),
.clk (clk),
.dout (read_rs2_data_out_i) );
assign read_rs1_data_out = (|read_rs1_addr) ? (((write_enable_d1 == 1'b1) && (read_rs1_addr == write_addr)) ? write_data_in_d1 : read_rs1_data_out_i) : 0;
assign read_rs2_data_out = (|read_rs2_addr) ? (((write_enable_d1 == 1'b1) && (read_rs2_addr == write_addr)) ? write_data_in_d1 : read_rs2_data_out_i) : 0;
always @(posedge clk, negedge reset_n) begin : output_proc
if (!reset_n) begin
read_en_out <= 0;
write_enable_d1 <= 0;
write_data_in_d1 <= 0;
end else begin
read_en_out <= read_enable;
write_enable_d1 <= write_enable;
write_data_in_d1 <= write_data_in;
end
end
endmodule |
module RV2T_controller (
//=====================================================================
// clock and reset
//=====================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=====================================================================
// interface for PC init
//=====================================================================
input wire start,
input wire [`PC_BITWIDTH - 1 : 0] start_addr,
//=====================================================================
// interface for instruction fetch
//=====================================================================
output reg fetch_init,
output reg [`PC_BITWIDTH - 1 : 0] fetch_start_addr,
output wire fetch_next,
//=====================================================================
// JARL / BRANCH
//=====================================================================
input wire branch_active,
input wire [`PC_BITWIDTH - 1 : 0] branch_addr,
//=====================================================================
// LOAD / STORE
//=====================================================================
input wire decode_ctl_LOAD,
input wire decode_ctl_STORE,
input wire decode_ctl_MISC_MEM,
input wire decode_ctl_MUL_DIV_FUNCT3,
input wire decode_ctl_WFI,
input wire mul_div_active,
input wire mul_div_done,
input wire load_active,
input wire [`XLEN - 1 : 0] data_to_store,
input wire [`XLEN - 1 : 0] mem_access_addr,
input wire unaligned_write,
input wire store_done,
input wire load_done,
//=====================================================================
// MRET
//=====================================================================
input wire mret_active,
//=====================================================================
// interface for execution unit
//=====================================================================
output wire exe_enable,
output wire data_access_enable,
//=====================================================================
// exception
//=====================================================================
input wire [`PC_BITWIDTH - 1 : 0] PC_in,
input wire [`XLEN - 1 : 0] mtvec_in,
input wire [`XLEN - 1 : 0] mepc_in,
input wire exception_storage_page_fault,
input wire exception_ecall,
input wire exception_ebreak,
input wire exception_alignment,
input wire timer_triggered,
input wire exception_illegal_instruction,
output reg is_interrupt,
output reg [`EXCEPTION_CODE_BITS - 1 : 0] exception_code,
output reg activate_exception,
output reg [`PC_BITWIDTH - 1 : 0] exception_PC,
output reg [`PC_BITWIDTH - 1 : 0] exception_addr,
output wire paused
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg ctl_pc_init;
reg ctl_fetch_enable;
reg ctl_exe_enable;
reg ctl_data_access_enable;
reg ctl_fetch_init_branch;
reg ctl_fetch_init_exception;
reg ctl_fetch_init_mret_active;
reg ctl_disable_data_access;
reg ctl_disable_data_access_reg;
reg ctl_clear_exception;
reg ctl_activate_exception;
reg ctl_instruction_addr_misalign_exception;
reg ctl_load_active;
reg ctl_store_active;
reg ctl_fetch_exe_active;
reg ctl_paused;
reg ctl_set_interrupt_active;
reg ctl_set_interrupt_active_reg;
reg load_active_reg;
reg store_active_reg;
reg first_exe;
reg [`XLEN - 1 : 0] mem_access_addr_d1;
wire exception_active;
wire exception_active_reg;
reg exception_storage_page_fault_reg;
reg exception_ecall_reg;
reg exception_ebreak_reg;
reg exception_instruction_addr_misalign_reg;
reg exception_alignment_reg;
reg exception_illegal_instruction_reg;
reg interrupt_active;
reg decode_ctl_WFI_d1;
reg ecall_active;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// data path
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
assign exception_active =
exception_storage_page_fault | exception_ecall | exception_ebreak |
ctl_instruction_addr_misalign_exception | exception_alignment | exception_illegal_instruction;
assign exception_active_reg =
exception_storage_page_fault_reg | exception_ecall_reg | exception_ebreak_reg |
exception_instruction_addr_misalign_reg | exception_alignment_reg | exception_illegal_instruction_reg;
always @(posedge clk, negedge reset_n) begin : fetch_proc
if (!reset_n) begin
fetch_init <= 0;
fetch_start_addr <= 0;
ctl_disable_data_access_reg <= 0;
exception_storage_page_fault_reg <= 0;
exception_ecall_reg <= 0;
exception_ebreak_reg <= 0;
exception_instruction_addr_misalign_reg <= 0;
exception_code <= 0;
activate_exception <= 0;
exception_PC <= 0;
exception_addr <= 0;
load_active_reg <= 0;
store_active_reg <= 0;
exception_alignment_reg <= 0;
interrupt_active <= 0;
mem_access_addr_d1 <= 0;
ctl_set_interrupt_active_reg <= 0;
decode_ctl_WFI_d1 <= 0;
is_interrupt <= 0;
ecall_active <= 0;
end else begin
decode_ctl_WFI_d1 <= decode_ctl_WFI;
activate_exception <= ctl_activate_exception;
mem_access_addr_d1 <= mem_access_addr;
if (data_access_enable) begin
if (decode_ctl_WFI_d1) begin
exception_PC <= PC_in + 4;
end else begin
exception_PC <= PC_in;
end
if (exception_alignment) begin // store exception
exception_addr <= mem_access_addr;
end else begin
case (1'b1) // synthesis parallel_case
branch_active : begin
exception_addr <= {branch_addr[`PC_BITWIDTH - 1 : 1], 1'b0};
end
default : begin
exception_addr <= PC_in;
end
endcase
end
end else if (exception_alignment) begin // load exception
exception_addr <= mem_access_addr_d1;
end
if (ctl_set_interrupt_active) begin
interrupt_active <= 1'b1;
end else if (!timer_triggered) begin
interrupt_active <= 0;
end
ctl_set_interrupt_active_reg <= ctl_set_interrupt_active;
if (ctl_clear_exception) begin
exception_storage_page_fault_reg <= 0;
end else if (exception_storage_page_fault) begin
exception_storage_page_fault_reg <= 1'b1;
end
if (ctl_clear_exception) begin
exception_ecall_reg <= 0;
end else if (exception_ecall) begin
exception_ecall_reg <= 1'b1;
end
if (ctl_clear_exception) begin
exception_ebreak_reg <= 0;
end else if (exception_ebreak) begin
exception_ebreak_reg <= 1'b1;
end
if (ctl_clear_exception) begin
exception_instruction_addr_misalign_reg <= 0;
end else if (ctl_instruction_addr_misalign_exception) begin
exception_instruction_addr_misalign_reg <= 1'b1;
end
if (ctl_clear_exception) begin
exception_alignment_reg <= 0;
end else if (exception_alignment) begin
exception_alignment_reg <= 1'b1;
end
if (ctl_clear_exception) begin
exception_illegal_instruction_reg <= 0;
end else if (exception_illegal_instruction) begin
exception_illegal_instruction_reg <= 1'b1;
end
if (ctl_fetch_exe_active) begin
load_active_reg <= 0;
end else if (ctl_load_active) begin
load_active_reg <= 1'b1;
end
if (ctl_fetch_exe_active) begin
store_active_reg <= 0;
end else if (ctl_store_active) begin
store_active_reg <= 1'b1;
end
if (exception_ecall) begin
ecall_active <= 1'b1;
end else if (mret_active) begin
ecall_active <= 1'b0;
end
if (ctl_set_interrupt_active_reg) begin
exception_code <= `INTERRUPT_MACHINE_TIMER;
is_interrupt <= 1'b1;
end else begin
is_interrupt <= 0;
case (1'b1) // synthesis parallel_case
exception_storage_page_fault_reg : begin
exception_code <= `EXCEPTION_STORE_PAGE_FAULT;
end
exception_ecall_reg : begin
exception_code <= `EXCEPTION_ENV_CALL_FROM_M_MODE;
end
exception_ebreak_reg : begin
exception_code <= `EXCEPTION_BREAKPOINT;
end
exception_instruction_addr_misalign_reg : begin
exception_code <= `EXCEPTION_INSTRUCTION_ADDR_MISALIGN;
end
exception_illegal_instruction_reg : begin
exception_code <= `EXCEPTION_ILLEGAL_INSTRUCTION;
end
exception_alignment_reg : begin
if (load_active_reg) begin
exception_code <= `EXCEPTION_LOAD_ADDR_MISALIGN;
end else begin
exception_code <= `EXCEPTION_STORE_ADDR_MISALIGN;
end
end
default : begin
end
endcase
end
fetch_init <= ctl_pc_init | ctl_fetch_init_branch | ctl_fetch_init_exception | ctl_fetch_init_mret_active;
ctl_disable_data_access_reg <= ctl_disable_data_access;
case (1'b1) // synthesis parallel_case
ctl_pc_init : begin
fetch_start_addr <= {start_addr [`PC_BITWIDTH - 1 : 1], 1'b0};
end
ctl_fetch_init_branch : begin
fetch_start_addr <= {branch_addr [`PC_BITWIDTH - 1 : 1], 1'b0};
end
ctl_fetch_init_mret_active : begin
fetch_start_addr <= mepc_in;
end
ctl_fetch_init_exception : begin
if (mtvec_in [1 : 0] == 2'b00) begin
fetch_start_addr <= mtvec_in;
end else begin
fetch_start_addr <= {mtvec_in [`XLEN - 1 : 2], 2'b00} + {{(30 - `EXCEPTION_CODE_BITS){1'b0}}, exception_code, 2'b00};
end
end
default : begin
end
endcase
end
end
assign fetch_next = ctl_fetch_enable;
assign exe_enable = ctl_exe_enable;
assign data_access_enable = ctl_data_access_enable;
always @(posedge clk, negedge reset_n) begin : first_exe_proc
if (!reset_n) begin
first_exe <= 0;
end else if (fetch_init) begin
first_exe <= 0;
end else if (exe_enable) begin
first_exe <= 1'b1;
end
end
assign paused = ctl_paused;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam S_INIT = 0, S_INIT_WAIT1 = 1, S_FETCH = 2,
S_DECODE = 3, S_FETCH_EXE = 4, S_DECODE_DATA = 5,
S_STORE = 6, S_STORE_WAIT = 7, S_LOAD = 8, S_LOAD_WAIT = 9,
S_EXCEPTION = 10, S_EXCEPTION_REINIT = 11, S_MUL_DIV = 12,
S_WFI = 13, S_WFI_WAIT = 14;
reg [14 : 0] current_state, next_state;
// Declare states
always @(posedge clk, negedge reset_n) begin : state_machine_reg
if (!reset_n) begin
current_state <= 0;
end else if (sync_reset) begin
current_state <= 0;
end else begin
current_state <= next_state;
end
end
// FSM main body
always @(*) begin : state_machine_comb
next_state = 0;
ctl_pc_init = 0;
ctl_fetch_enable = 0;
ctl_exe_enable = 0;
ctl_data_access_enable = 0;
ctl_disable_data_access = 0;
ctl_fetch_init_branch = 0;
ctl_fetch_init_mret_active = 0;
ctl_clear_exception = 0;
ctl_activate_exception = 0;
ctl_fetch_init_exception = 0;
ctl_instruction_addr_misalign_exception = 0;
ctl_load_active = 0;
ctl_store_active = 0;
ctl_fetch_exe_active = 0;
ctl_paused = 0;
ctl_set_interrupt_active = 0;
case (1'b1) // synthesis parallel_case
current_state[S_INIT]: begin
ctl_paused = 1'b1;
if (start) begin
ctl_pc_init = 1'b1;
next_state [S_INIT_WAIT1] = 1'b1;
end else begin
next_state [S_INIT] = 1'b1;
end
end
current_state[S_INIT_WAIT1]: begin
next_state [S_FETCH] = 1'b1;
end
current_state [S_FETCH] : begin
next_state [S_DECODE] = 1'b1;
end
current_state [S_DECODE] : begin
ctl_fetch_enable = 1;
next_state [S_FETCH_EXE] = 1'b1;
end
current_state [S_FETCH_EXE] : begin
ctl_fetch_exe_active = 1'b1;
ctl_data_access_enable = first_exe & (~ctl_disable_data_access_reg);
ctl_fetch_init_branch = branch_active & (~(branch_addr[1]));
ctl_fetch_init_mret_active = mret_active;
if (timer_triggered & (~interrupt_active) & (~ecall_active)) begin
ctl_set_interrupt_active = 1'b1;
next_state [S_EXCEPTION] = 1'b1;
end else if (branch_active & branch_addr[1]) begin
ctl_instruction_addr_misalign_exception = 1'b1;
next_state [S_EXCEPTION] = 1'b1;
end else if ((exception_active | exception_active_reg) & data_access_enable) begin
next_state [S_EXCEPTION] = 1'b1;
end else if (branch_active | mret_active) begin
next_state [S_INIT_WAIT1] = 1'b1;
end else begin
next_state [S_DECODE_DATA] = 1'b1;
end
end
current_state [S_DECODE_DATA] : begin
ctl_exe_enable = 1'b1;
if (decode_ctl_WFI) begin
next_state [S_WFI] = 1'b1;
end
//else if (decode_ctl_STORE) begin
// next_state [S_STORE] = 1'b1;
//end
else if (decode_ctl_LOAD) begin
next_state [S_LOAD] = 1'b1;
end else if (decode_ctl_MUL_DIV_FUNCT3) begin
next_state [S_MUL_DIV] = 1'b1;
end
else begin
ctl_fetch_enable = 1'b1;
next_state [S_FETCH_EXE] = 1'b1;
end
end
current_state [S_WFI] : begin
ctl_data_access_enable = 1'b1;
next_state [S_WFI_WAIT] = 1'b1;
end
current_state [S_WFI_WAIT] : begin
if (timer_triggered & (~interrupt_active)) begin
ctl_set_interrupt_active = 1'b1;
next_state [S_EXCEPTION] = 1'b1;
end else begin
next_state [S_WFI_WAIT] = 1'b1;
end
end
current_state [S_STORE] : begin
ctl_data_access_enable = 1'b1;
ctl_store_active = 1'b1;
next_state [S_STORE_WAIT] = 1'b1;
end
current_state [S_STORE_WAIT] : begin
if (exception_alignment) begin
next_state [S_EXCEPTION] = 1'b1;
end else if (store_done) begin
ctl_fetch_enable = 1'b1;
ctl_disable_data_access = 1'b1;
next_state [S_FETCH_EXE] = 1'b1;
end else begin
next_state [S_STORE_WAIT] = 1'b1;
end
end
current_state [S_LOAD] : begin
ctl_data_access_enable = 1'b1;
ctl_load_active = 1'b1;
next_state [S_LOAD_WAIT] = 1'b1;
end
current_state [S_LOAD_WAIT] : begin
if (exception_alignment) begin
next_state [S_EXCEPTION] = 1'b1;
end else if (load_done) begin
ctl_fetch_enable = 1'b1;
ctl_disable_data_access = 1'b1;
next_state [S_FETCH_EXE] = 1'b1;
end else begin
next_state [S_LOAD_WAIT] = 1'b1;
end
end
current_state [S_EXCEPTION] : begin
ctl_activate_exception = 1'b1;
next_state [S_EXCEPTION_REINIT] = 1'b1;
end
current_state [S_EXCEPTION_REINIT] : begin
ctl_fetch_init_exception = 1'b1;
ctl_clear_exception = 1'b1;
next_state [S_INIT_WAIT1] = 1'b1;
end
current_state [S_MUL_DIV] : begin
if (!mul_div_done) begin
next_state [S_MUL_DIV] = 1'b1;
end else begin
ctl_fetch_enable = 1'b1;
ctl_disable_data_access = 1'b1;
next_state [S_FETCH_EXE] = 1'b1;
end
end
default: begin
next_state[S_INIT] = 1'b1;
end
endcase
end
endmodule |
module RV2T_memory (
//=======================================================================
// clock / reset
//=======================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=======================================================================
// ocd
//=======================================================================
input wire ocd_read_enable,
input wire ocd_write_enable,
input wire [`MEM_ADDR_BITS - 1 : 0] ocd_rw_addr,
input wire [`XLEN - 1 : 0] ocd_write_word,
//=======================================================================
// instruction fetch
//=======================================================================
input wire code_read_enable,
input wire [`MEM_ADDR_BITS - 1 : 0] code_read_addr,
//=======================================================================
// data read / write
//=======================================================================
input wire data_read_enable,
input wire [`XLEN_BYTES - 1 : 0] data_write_enable,
input wire [`MEM_ADDR_BITS - 1 : 0] data_rw_addr,
input wire [`XLEN - 1 : 0] data_write_word,
//=======================================================================
// output
//=======================================================================
output reg enable_out,
output wire [`XLEN - 1 : 0] word_out,
output wire [`MEM_ADDR_BITS - 1 : 0] mem_addr,
output wire [`XLEN_BYTES - 1 : 0] mem_write_en,
output wire [`XLEN - 1 : 0] mem_write_data,
input wire [`XLEN - 1 : 0] mem_read_data
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg [`MEM_ADDR_BITS - 1 : 0] addr;
wire [`XLEN - 1 : 0] din;
wire [`XLEN_BYTES - 1 : 0] write_en;
wire [15 : 0] dout_high;
wire [15 : 0] dout_low;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// memory
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
assign write_en = {(`XLEN_BYTES){ocd_write_enable}} | data_write_enable;
always @(*) begin : addr_proc
if (ocd_read_enable | ocd_write_enable) begin
addr = ocd_rw_addr;
end else if (code_read_enable) begin
addr = code_read_addr;
end else begin
addr = data_rw_addr;
end
end
assign din = ocd_write_enable ? ocd_write_word : data_write_word;
/*single_port_ram_sim_high #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) single_port_ram_sim_high_i (
.addr (addr),
.din (din [31 : 16]),
.write_en (write_en[3 : 2]),
.clk (clk),
.dout (dout_high));
single_port_ram_sim_low #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) single_port_ram_sim_low_i (
.addr (addr),
.din (din [15 : 0]),
.write_en (write_en[1 : 0]),
.clk (clk),
.dout (dout_low));
*/
/*
single_port_ram_lattice #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_high_i (
.addr (addr),
.din (din [31 : 16]),
.write_en (write_en[3 : 2]),
.clk (clk),
.dout (dout_high));
single_port_ram_lattice #(.ADDR_WIDTH (`MEM_ADDR_BITS), .DATA_WIDTH (16) ) ram_low_i (
.addr (addr),
.din (din [15 : 0]),
.write_en (write_en[1 : 0]),
.clk (clk),
.dout (dout_low));
*/
// assign word_out = {dout_high, dout_low};
assign word_out = mem_read_data;
always @(posedge clk, negedge reset_n) begin : output_proc
if (!reset_n) begin
enable_out <= 0;
end else begin
enable_out <= ocd_read_enable | code_read_enable | data_read_enable;
end
end
assign mem_addr = addr;
assign mem_write_en = write_en;
assign mem_write_data = din;
endmodule |
module RV2T_CSR (
//=======================================================================
// clock / reset
//=======================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=======================================================================
// from pipeline
//=======================================================================
input wire exe_enable,
//=======================================================================
// register read / write
//=======================================================================
input wire read_enable,
input wire [`CSR_ADDR_BITS - 1 : 0] read_addr,
output wire read_en_out,
output wire [`XLEN - 1 : 0] read_data_out,
input wire write_enable,
input wire [`CSR_ADDR_BITS - 1 : 0] write_addr,
input wire [`XLEN - 1 : 0] write_data_in,
//=======================================================================
// interrupt
//=======================================================================
input wire timer_triggered,
//=======================================================================
// exception
//=======================================================================
input wire activate_exception,
input wire is_interrupt,
input wire [`EXCEPTION_CODE_BITS - 1 : 0] exception_code,
input wire [`PC_BITWIDTH - 1 : 0] exception_PC,
input wire [`PC_BITWIDTH - 1 : 0] exception_addr,
output reg exception_illegal_instruction,
output wire [`XLEN - 1 : 0] mtvec_out,
output wire [`XLEN - 1 : 0] mepc_out,
output wire mtie_out,
output wire mie_out,
output wire mtip_out
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg [`XLEN - 1 : 0] mtvec = 0;
reg [`XLEN - 1 : 0] mscratch = 0;
reg [`XLEN - 1 : 0] mepc = 0;
reg [`XLEN - 1 : 0] mtval = 0;
reg [`XLEN - 1 : 0] mcause = 0;
reg read_en_out_i;
reg [`XLEN - 1 : 0] read_data_out_i;
reg [`XLEN * 2 - 1 : 0] mcycle_i;
reg [`XLEN - 1 : 0] mcycleh;
reg [`XLEN * 2 - 1 : 0] minstret_i;
reg [`XLEN - 1 : 0] minstreth;
reg mie_mtie;
reg mstatus_mpie;
reg mstatus_mie;
reg timer_triggered_d1;
reg mtip;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// datapath
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
assign read_en_out = read_en_out_i;
assign read_data_out = read_data_out_i;
assign mtvec_out = mtvec;
assign mepc_out = mepc;
assign mtie_out = mie_mtie;
assign mie_out = mstatus_mie;
assign mtip_out = mtip;
always @(posedge clk, negedge reset_n) begin : output_proc
if (!reset_n) begin
read_en_out_i <= 0;
read_data_out_i <= 0;
mtvec <= 0;
mscratch <= 0;
mepc <= 0;
mtval <= 0;
mcause <= 0;
exception_illegal_instruction <= 0;
if (`SMALL_CSR_SET == 0) begin
mcycle_i <= 0;
mcycleh <= 0;
minstret_i <= 0;
minstreth <= 0;
end
mie_mtie <= 0;
mstatus_mpie <= 0;
mstatus_mie <= 0;
timer_triggered_d1 <= 0;
mtip <= 0;
end else begin
timer_triggered_d1 <= timer_triggered;
read_en_out_i <= read_enable;
exception_illegal_instruction <= 0;
if (`SMALL_CSR_SET == 0) begin
mcycle_i <= mcycle_i + 1;
if (exe_enable) begin
minstret_i <= minstret_i + 1;
end
end
if ((~timer_triggered_d1) & timer_triggered) begin
mtip <= 1'b1;
end else if (!timer_triggered) begin
mtip <= 0;
end
if (activate_exception) begin
mcause <= {is_interrupt, 27'd0, exception_code};
mepc <= exception_PC;
mtval <= exception_addr;
mstatus_mpie <= mstatus_mie;
end else if (read_enable) begin
case (read_addr) // synthesis parallel_case
`CSR_MVENDORID : begin
if (`SMALL_CSR_SET == 0) begin
read_data_out_i <= `PULSERAIN_JEDEC_VENDOR_ID;
end
end
`CSR_MARCHID : begin
if (`SMALL_CSR_SET == 0) begin
read_data_out_i <= `PULSERAIN_RV2T_ARCH_ID;
end
end
`CSR_MIMPID : begin
if (`SMALL_CSR_SET == 0) begin
read_data_out_i <= `PULSERAIN_RV2T_IMPLEMENT_ID;
end
end
`CSR_HARTID : begin
if (`SMALL_CSR_SET == 0) begin
read_data_out_i <= `PULSERAIN_RV2T_HART_ID;
end
end
`CSR_MISA : begin
if (`SMALL_CSR_SET == 0) begin
read_data_out_i <= `PULSERAIN_RV2T_ISA;
end
end
`CSR_MTVEC : begin
read_data_out_i <= mtvec;
end
`CSR_MSCRATCH : begin
read_data_out_i <= mscratch;
end
`CSR_MEPC : begin
read_data_out_i <= mepc;
end
`CSR_MTVAL : begin
read_data_out_i <= mtval;
end
`CSR_MSTATUS : begin
read_data_out_i <= {19'd0, 2'b11, 2'b00, 1'b0, mstatus_mpie, 1'b0, 1'b0, 1'b0, mstatus_mie, 3'd0};
end
`CSR_MCAUSE : begin
read_data_out_i <= mcause;
end
`CSR_MCYCLE : begin
if (`SMALL_CSR_SET == 0) begin
mcycleh <= mcycle_i [`XLEN * 2 - 1 : `XLEN];
read_data_out_i <= mcycle_i [`XLEN - 1 : 0];
end
end
`CSR_MCYCLEH : begin
if (`SMALL_CSR_SET == 0) begin
read_data_out_i <= mcycleh;
end
end
`CSR_MINSTRET : begin
if (`SMALL_CSR_SET == 0) begin
minstreth <= minstret_i [`XLEN * 2 - 1 : `XLEN];
read_data_out_i <= minstret_i [`XLEN - 1 : 0];
end
end
`CSR_MINSTRETH : begin
if (`SMALL_CSR_SET == 0) begin
read_data_out_i <= minstreth;
end
end
`CSR_MIP : begin
read_data_out_i <= {20'd0, 4'd0, mtip, 3'd0, 4'd0};
end
`CSR_MIE :begin
read_data_out_i <= {24'd0, mie_mtie, 7'd0};
end
default : begin
exception_illegal_instruction <= 1'b1;
end
endcase
end else if (write_enable) begin
case (write_addr) // synthesis parallel_case
`CSR_MSTATUS : begin
mstatus_mie <= write_data_in[3];
mstatus_mpie <= write_data_in[7];
end
`CSR_MTVEC : begin
mtvec <= write_data_in;
end
`CSR_MSCRATCH : begin
mscratch <= write_data_in;
end
`CSR_MEPC : begin
mepc <= write_data_in;
end
`CSR_MTVAL : begin
mtval <= write_data_in;
end
`CSR_MCAUSE : begin
mcause <= write_data_in;
end
`CSR_MISA : begin
// do nothing
end
`CSR_MIE : begin
mie_mtie <= write_data_in[7];
end
`CSR_MIP : begin
mtip <= write_data_in[7];
end
default : begin
exception_illegal_instruction <= 1'b1;
end
endcase
end
end
end
endmodule |
module RV2T_mm_reg (
//=======================================================================
// clock / reset
//=======================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=======================================================================
// data read / write
//=======================================================================
input wire data_read_enable,
input wire data_write_enable,
input wire [`MM_REG_ADDR_BITS - 1 : 0] data_rw_addr,
input wire [`XLEN - 1 : 0] data_write_word,
//=======================================================================
// UART
//=======================================================================
output wire start_TX,
output wire [7 : 0] tx_data,
input wire tx_active,
//=======================================================================
// output
//=======================================================================
output reg enable_out,
output wire [`XLEN - 1 : 0] word_out,
output wire timer_triggered
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire load_mtimecmp_low;
wire load_mtimecmp_high;
wire [`XLEN - 1 : 0] machine_timer_data_out;
reg [`MM_REG_ADDR_BITS - 1 : 0] data_rw_addr_d1;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Input
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
assign load_mtimecmp_low = (data_write_enable & (data_rw_addr == `MTIMECMP_LOW_ADDR)) ? 1'b1 : 1'b0;
assign load_mtimecmp_high = (data_write_enable & (data_rw_addr == `MTIMECMP_HIGH_ADDR)) ? 1'b1 : 1'b0;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Output
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
enable_out <= 0;
data_rw_addr_d1 <= 0;
end else begin
enable_out <= data_read_enable | data_write_enable;
data_rw_addr_d1 <= data_rw_addr;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// machine timer
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
RV2T_machine_timer RV2T_machine_timer_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.load_mtimecmp_low (load_mtimecmp_low),
.load_mtimecmp_high (load_mtimecmp_high),
.mtimecmp_write_data (data_write_word),
.timer_triggered (timer_triggered),
.reg_read_addr (data_rw_addr [1 : 0]),
.reg_read_data (machine_timer_data_out));
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// UART
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
assign start_TX = ((`UART_TX_ADDR == data_rw_addr) && data_write_enable) ? 1'b1 : 1'b0;
assign tx_data = data_write_word [7 : 0];
assign word_out = (data_rw_addr_d1 == `UART_TX_ADDR) ? {tx_active, 31'd0} : machine_timer_data_out;
endmodule |
module RV2T_instruction_decode (
//=====================================================================
// clock and reset
//=====================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=====================================================================
// interface from the controller
//=====================================================================
input wire decode_enable,
//=====================================================================
// interface for the instruction fetch
//=====================================================================
input wire enable_in,
input wire [`XLEN - 1 : 0] IR_in,
input wire [`PC_BITWIDTH - 1 : 0] PC_in,
//=====================================================================
// interface for register read
//=====================================================================
output wire [`REG_ADDR_BITS - 1 : 0] rs1,
output wire [`REG_ADDR_BITS - 1 : 0] rs2,
//=====================================================================
// interface for CSR read
//=====================================================================
output wire [`CSR_BITS - 1 : 0] csr,
output reg csr_read_enable,
//=====================================================================
// interface for next stage
//=====================================================================
output reg [`XLEN - 1 : 2] IR_out,
output reg [`PC_BITWIDTH - 1 : 0] PC_out,
output reg ctl_load_X_from_rs1,
output reg ctl_load_Y_from_rs2,
output reg ctl_load_Y_from_imm_12,
output reg ctl_load_Y_from_store_offset_12,
output reg ctl_save_to_rd,
output reg ctl_ALU_FUNCT3,
output reg ctl_MUL_DIV_FUNCT3,
output reg ctl_LUI,
output reg ctl_AUIPC,
output reg ctl_JAL,
output reg ctl_JALR,
output reg ctl_BRANCH,
output reg ctl_LOAD,
output reg ctl_STORE,
output reg ctl_SYSTEM,
output reg ctl_CSR,
output reg ctl_CSR_write,
output reg ctl_MISC_MEM,
output reg ctl_MRET,
output reg ctl_WFI,
output reg exception_illegal_instruction
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire [`REG_ADDR_BITS - 1 : 0] rs1_32;
wire [`REG_ADDR_BITS - 1 : 0] rs2_32;
wire [`REG_ADDR_BITS - 1 : 0] rd;
wire [2 : 0] funct3;
wire [11 : 0] funct12;
reg illegal;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// data path
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//---------------------------------------------------------------------
// register read
//---------------------------------------------------------------------
assign rs1_32 = IR_in [19 : 15];
assign rs2_32 = IR_in [24 : 20];
assign rd = IR_in [11 : 7];
assign rs1 = rs1_32;
assign rs2 = rs2_32;
//---------------------------------------------------------------------
// function fields
//---------------------------------------------------------------------
assign funct3 = IR_in [14 : 12];
assign funct12 = IR_in [31 : 20];
//---------------------------------------------------------------------
// CSR read
//---------------------------------------------------------------------
assign csr = IR_in [31 : 20];
always @(*) begin : csr_read_enable_proc
csr_read_enable = ctl_CSR;
end
//---------------------------------------------------------------------
// output
//---------------------------------------------------------------------
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
IR_out <= 0;
PC_out <= 0;
illegal <= 0;
end else begin
IR_out <= IR_in[`XLEN - 1 : 2];
PC_out <= PC_in;
if (|IR_in == 1'b0 || &IR_in == 1'b1)
illegal <= 1'b1;
else
illegal <= 1'b0;
end
end
//---------------------------------------------------------------------
// instruction decode
//---------------------------------------------------------------------
always @(*) begin : decode_proc
ctl_load_X_from_rs1 = 0;
ctl_load_Y_from_rs2 = 0;
ctl_load_Y_from_imm_12 = 0;
ctl_save_to_rd = 0;
ctl_ALU_FUNCT3 = 0;
ctl_MUL_DIV_FUNCT3 = 0;
ctl_LUI = 0;
ctl_AUIPC = 0;
ctl_JAL = 0;
ctl_JALR = 0;
ctl_BRANCH = 0;
ctl_LOAD = 0;
ctl_STORE = 0;
ctl_SYSTEM = 0;
ctl_CSR = 0;
ctl_CSR_write = 0;
ctl_MISC_MEM = 0;
ctl_MRET = 0;
ctl_WFI = 0;
exception_illegal_instruction = illegal;
case (IR_out [6 : 2]) // synthesis parallel_case
`CMD_OP_IMM : begin
ctl_load_X_from_rs1 = 1'b1;
ctl_load_Y_from_imm_12 = 1'b1;
ctl_save_to_rd = 1'b1;
ctl_ALU_FUNCT3 = 1'b1;
end
`CMD_OP : begin
ctl_load_X_from_rs1 = 1'b1;
ctl_load_Y_from_rs2 = 1'b1;
ctl_save_to_rd = 1'b1;
ctl_ALU_FUNCT3 = ~IR_out[25];
ctl_MUL_DIV_FUNCT3 = IR_out[25];
end
`CMD_LUI : begin
ctl_LUI = 1'b1;
ctl_save_to_rd = 1'b1;
end
`CMD_AUIPC : begin
ctl_AUIPC = 1'b1;
ctl_save_to_rd = 1'b1;
end
`CMD_JAL : begin
ctl_JAL = 1'b1;
ctl_save_to_rd = 1'b1;
end
`CMD_JALR : begin
ctl_JALR = 1'b1;
ctl_save_to_rd = 1'b1;
ctl_load_X_from_rs1 = 1'b1;
end
`CMD_BRANCH : begin
ctl_BRANCH = 1'b1;
ctl_load_X_from_rs1 = 1'b1;
ctl_load_Y_from_rs2 = 1'b1;
end
`CMD_LOAD : begin
ctl_LOAD = 1'b1;
ctl_load_X_from_rs1 = 1'b1;
// ctl_save_to_rd = 1'b1;
end
`CMD_STORE : begin
ctl_STORE = 1'b1;
ctl_load_X_from_rs1 = 1'b1;
ctl_load_Y_from_rs2 = 1'b1;
end
`CMD_SYSTEM : begin
ctl_SYSTEM = 1'b1;
if ((funct12 [4 : 0] == 5'b00010) && (funct3 == 3'b000)) begin
ctl_MRET = 1'b1;
end else if ((funct12 [4 : 0] == 5'b00101) && (funct3 == 3'b000)) begin
ctl_WFI = 1'b1;
end else begin
// If rd=x0, then the instruction shall not read the CSR and shall
// not cause any of the side-effects that might occur on a CSR read.
ctl_CSR = |funct3;
end
ctl_save_to_rd = ctl_CSR;
ctl_CSR_write = |rs1;
ctl_load_X_from_rs1 = 1'b1;
end
`CMD_MISC_MEM : begin
// only handle FENCE.I as we don't have data cache
if (IR_out[14:12] == 3'b001)
ctl_MISC_MEM = 1'b1;
end
default : begin
exception_illegal_instruction = 1'b1;
end
endcase
end
endmodule |
module RV2T_machine_timer (
//=======================================================================
// clock / reset
//=======================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=======================================================================
// control
//=======================================================================
input wire load_mtimecmp_low,
input wire load_mtimecmp_high,
input wire [`XLEN - 1 : 0] mtimecmp_write_data,
output reg timer_triggered,
input wire [1 : 0] reg_read_addr,
output reg [`XLEN - 1 : 0] reg_read_data
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg [`MTIME_CYCLE_PERIOD_BITS - 1 : 0] mtime_cycle_counter;
reg mtime_cycle_pulse;
reg [`XLEN * (2 - `SMALL_MACHINE_TIMER) - 1 : 0] mtime;
reg [`XLEN * (2 - `SMALL_MACHINE_TIMER) - 1 : 0] mtimecmp;
reg [`XLEN - 1 : 0] mtime_high;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// mtime_cycle_counter
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
/* verilator lint_off WIDTH */
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
mtime_cycle_counter <= 0;
mtime_cycle_pulse <= 0;
end else if (mtime_cycle_counter != (`MTIME_CYCLE_PERIOD - 1)) begin
mtime_cycle_counter <= mtime_cycle_counter + 1;
mtime_cycle_pulse <= 0;
end else begin
mtime_cycle_counter <= 0;
mtime_cycle_pulse <= 1'b1;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// mtime
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
generate
if (`SMALL_MACHINE_TIMER) begin
always @(posedge clk, negedge reset_n) begin : mtime_proc
if (!reset_n) begin
mtime <= 0;
end else begin
mtime <= mtime + 1;
end
end
end else begin
always @(posedge clk, negedge reset_n) begin : mtime_proc
if (!reset_n) begin
mtime <= 0;
end else if (mtime_cycle_pulse) begin
mtime <= mtime + 1;
end
end
end
endgenerate
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// mtimecmp
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
generate
if (`SMALL_MACHINE_TIMER) begin
always @(posedge clk, negedge reset_n) begin : mtimecmp_proc
if (!reset_n) begin
mtimecmp <= 0;
end else if (load_mtimecmp_low) begin
mtimecmp [`XLEN - 1 : 0] <= mtimecmp_write_data;
end
end
end else begin
always @(posedge clk, negedge reset_n) begin : mtimecmp_proc
if (!reset_n) begin
mtimecmp <= 0;
end else if (load_mtimecmp_low) begin
mtimecmp [`XLEN - 1 : 0] <= mtimecmp_write_data;
end else if (load_mtimecmp_high) begin
mtimecmp [`XLEN * 2 - 1 : `XLEN] <= mtimecmp_write_data;
end
end
end
endgenerate
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// timer trigger
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : timer_triggered_proc
if (!reset_n) begin
timer_triggered <= 0;
end else if (load_mtimecmp_low | load_mtimecmp_high) begin
timer_triggered <= 0;
end else if (mtime >= mtimecmp) begin
timer_triggered <= 1'b1;
end
end
generate
if (`SMALL_MACHINE_TIMER) begin
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
reg_read_data <= 0;
end else begin
case (reg_read_addr)
2'b01 : begin
reg_read_data <= 0;
end
2'b10 : begin
reg_read_data <= mtimecmp;
end
2'b11 : begin
reg_read_data <= 0;
end
default : begin
reg_read_data <= mtime;
end
endcase
end
end
end else begin
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
reg_read_data <= 0;
mtime_high <= 0;
end else begin
case (reg_read_addr)
2'b01 : begin
reg_read_data <= mtime_high;
end
2'b10 : begin
reg_read_data <= mtimecmp [`XLEN - 1 : 0];
end
2'b11 : begin
reg_read_data <= mtimecmp [`XLEN * 2 - 1 : `XLEN];
end
default : begin
reg_read_data <= mtime [`XLEN - 1 : 0];
mtime_high <= mtime [`XLEN * 2 - 1 : `XLEN];
end
endcase
end
end
end
endgenerate
endmodule |
module RV2T_execution_unit (
//=====================================================================
// clock and reset
//=====================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=====================================================================
// interface from the controller
//=====================================================================
input wire exe_enable,
//=====================================================================
// interface for the instruction decode
//=====================================================================
input wire enable_in,
input wire [`XLEN - 1 : 2] IR_in,
input wire [`PC_BITWIDTH - 1 : 0] PC_in,
input wire [`CSR_BITS - 1 : 0] csr_addr_in,
input wire ctl_load_Y_from_imm_12,
input wire ctl_save_to_rd,
input wire ctl_LUI,
input wire ctl_AUIPC,
input wire ctl_JAL,
input wire ctl_JALR,
input wire ctl_BRANCH,
input wire ctl_LOAD,
input wire ctl_STORE,
input wire ctl_SYSTEM,
input wire ctl_CSR,
input wire ctl_CSR_write,
input wire ctl_MISC_MEM,
input wire ctl_MRET,
input wire ctl_MUL_DIV_FUNCT3,
//=====================================================================
// interface for the register file
//=====================================================================
input wire signed [`XLEN - 1 : 0] rs1_in,
input wire signed [`XLEN - 1 : 0] rs2_in,
//=====================================================================
// interface for the CSR
//=====================================================================
input wire [`XLEN - 1 : 0] csr_in,
//=====================================================================
// output
//=====================================================================
output reg enable_out,
output reg [`REG_ADDR_BITS - 1 : 0] rd_addr_out,
output reg [`XLEN - 1 : 2] IR_out,
output reg [`PC_BITWIDTH - 1 : 0] PC_out,
output wire branch_active,
output wire [`PC_BITWIDTH - 1 : 0] branch_addr,
output reg [`XLEN - 1 : 0] csr_new_value,
output wire [`XLEN - 1 : 0] csr_old_value,
output reg reg_ctl_save_to_rd,
output reg [`XLEN - 1 : 0] data_out,
output reg load_active,
output reg store_active,
output wire [2 : 0] width_load_store,
output wire [`XLEN - 1 : 0] data_to_store,
output wire [`XLEN - 1 : 0] mem_access_addr,
output wire mem_access_unaligned,
output reg reg_ctl_CSR,
output reg reg_ctl_CSR_write,
output reg [`CSR_BITS - 1 : 0] csr_addr_out,
output reg ecall_active,
output reg ebreak_active,
output reg mret_active,
output wire mul_div_active,
output reg mul_div_done
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg signed [`XLEN - 1 : 0] X;
reg signed [`XLEN - 1 : 0] Y;
wire [`XLEN - 1 : 0] X_unsigned;
wire [`XLEN - 1 : 0] Y_unsigned;
wire [2 : 0] funct3_in;
wire [2 : 0] funct3;
reg [2 : 0] funct3_mul_div;
wire [2 : 0] width; // load/store width, only support up to 32 bits at this moment
wire [4 : 0] opcode;
wire signed [`XLEN - 1 : 0] I_immediate;
wire signed [`XLEN - 1 : 0] S_immediate;
wire signed [`XLEN - 1 : 0] B_immediate;
wire signed [`XLEN - 1 : 0] U_immediate;
wire signed [`XLEN - 1 : 0] J_immediate;
wire [4 : 0] shamt;
wire SRL0_SRA1;
wire ADD0_SUB1;
reg [`XLEN - 1 : 0] AUIPC_out;
reg signed [`XLEN - 1 : 0] ALU_out;
wire [4 : 0] csr_uimm;
wire [`XLEN - 1: 0] csr_uimm_ext;
reg reg_ctl_LUI;
reg reg_ctl_AUIPC;
reg reg_ctl_SYSTEM;
reg reg_ctl_JAL;
reg reg_ctl_JALR;
reg reg_ctl_BRANCH;
reg reg_ctl_MUL_DIV_FUNCT3;
reg branch_active_i;
reg [`PC_BITWIDTH - 1 : 0] branch_addr_i;
reg jalr_active;
wire [`PC_BITWIDTH - 1 : 0] jalr_addr;
reg jal_active;
reg [`PC_BITWIDTH - 1 : 0] jal_addr;
reg ecall_active_i;
reg ebreak_active_i;
reg exe_enable_d1;
wire mul_div_enable_out;
wire [63 : 0] Z;
wire [31 : 0] Q;
wire [31 : 0] R;
wire overflow_flag;
wire x_mul_div_signed0_unsigned1;
wire y_mul_div_signed0_unsigned1;
wire mul_div_enable;
reg [31 : 0] mul_div_out_reg;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// data path
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//---------------------------------------------------------------------
// immediate number
//---------------------------------------------------------------------
assign I_immediate = {{21{IR_in[31]}},IR_in[30:25], IR_in[24:21], IR_in[20]};
assign S_immediate = {{21{IR_in[31]}},IR_in[30:25], IR_in[11:8], IR_in[7]};
assign B_immediate = {{20{IR_in[31]}},IR_in[7], IR_in[30:25], IR_in[11:8], 1'b0};
assign U_immediate = {IR_in[31],IR_in[30:20], IR_in[19:12], {12{1'b0}}};
assign J_immediate = {{12{IR_in[31]}},IR_in[19:12], IR_in[20], IR_in[30:25], IR_in[24:21], 1'b0};
assign shamt = Y [4 : 0];
//---------------------------------------------------------------------
// funct3
//---------------------------------------------------------------------
assign funct3_in = IR_in [14 : 12];
assign opcode = IR_in [6 : 2];
assign funct3 = IR_in [14 : 12];
assign SRL0_SRA1 = IR_in [30];
assign ADD0_SUB1 = opcode[3] ? IR_in [30] : 1'b0; // distinguish between addi/add/sub
assign width = funct3 [2 : 0];
assign csr_uimm = IR_in [19 : 15];
assign csr_uimm_ext = {27'd0, csr_uimm};
//---------------------------------------------------------------------
// X/Y register
//---------------------------------------------------------------------
assign X_unsigned = $unsigned(X);
assign Y_unsigned = $unsigned(Y);
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
X <= 0;
Y <= 0;
PC_out <= 0;
IR_out <= 0;
reg_ctl_LUI <= 0;
reg_ctl_AUIPC <= 0;
reg_ctl_JAL <= 0;
reg_ctl_JALR <= 0;
reg_ctl_BRANCH <= 0;
reg_ctl_SYSTEM <= 0;
mret_active <= 0;
exe_enable_d1 <= 0;
mul_div_done <= 0;
end else begin
X <= rs1_in;
Y <= ctl_load_Y_from_imm_12 ? I_immediate : rs2_in;
PC_out <= PC_in;
IR_out <= IR_in;
exe_enable_d1 <= exe_enable;
mul_div_done <= (`ENABLE_HW_MUL_DIV) ? mul_div_enable_out : 1'b0;
if (exe_enable) begin
reg_ctl_LUI <= ctl_LUI;
reg_ctl_AUIPC <= ctl_AUIPC;
reg_ctl_JAL <= ctl_JAL | ctl_MISC_MEM;
reg_ctl_JALR <= ctl_JALR;
reg_ctl_BRANCH <= ctl_BRANCH;
reg_ctl_SYSTEM <= ctl_SYSTEM;
reg_ctl_MUL_DIV_FUNCT3 <= ctl_MUL_DIV_FUNCT3;
ecall_active <= ecall_active_i & ctl_SYSTEM;
ebreak_active <= ebreak_active_i & ctl_SYSTEM;
mret_active <= ctl_MRET & ctl_SYSTEM;
end else begin
reg_ctl_LUI <= 0;
reg_ctl_AUIPC <= 0;
reg_ctl_JAL <= 0;
reg_ctl_JALR <= 0;
reg_ctl_BRANCH <= 0;
reg_ctl_SYSTEM <= 0;
reg_ctl_MUL_DIV_FUNCT3 <= 0;
ecall_active <= 0;
ebreak_active <= 0;
mret_active <= 0;
end
end
end
//assign X = rs1_in;
//assign Y = ctl_load_Y_from_imm_12 ? {{20{I_immediate_12[11]}}, I_immediate_12} : rs2_in;
wire slt_result = (X < Y) ? 1'd1 : 1'b0;
wire sltu_result = (X_unsigned < Y_unsigned) ? 1'd1 : 1'd0;
wire[`XLEN - 1:0] xor_result = X ^ Y;
//---------------------------------------------------------------------
// ALU
//---------------------------------------------------------------------
always @(*) begin : alu_proc
case (funct3) // synopsys full_case parallel_case
`ALU_ADD_SUB : begin
ALU_out = (ADD0_SUB1) ? (X - Y) : (X + Y);
end
`ALU_SLL : begin
ALU_out = X << shamt;
end
`ALU_SLT : begin
ALU_out = {{31{1'b0}}, slt_result};
end
`ALU_SLTU : begin
ALU_out = {{31{1'b0}}, sltu_result};
end
`ALU_XOR : begin
ALU_out = xor_result;
end
`ALU_SRL_SRA : begin
ALU_out = (SRL0_SRA1) ? (X >>> shamt) : (X >> shamt);
end
`ALU_OR : begin
ALU_out = X | Y;
end
`ALU_AND : begin
ALU_out = X & Y;
end
default : begin
ALU_out = 0;
end
endcase
end
//---------------------------------------------------------------------
// LUI / AUIPC
//---------------------------------------------------------------------
always @(posedge clk, negedge reset_n) begin : lui_auipc_proc
if (!reset_n) begin
AUIPC_out <= 0;
end else if (exe_enable) begin
AUIPC_out <= U_immediate + PC_in;
end
end
//---------------------------------------------------------------------
// BRANCH
//---------------------------------------------------------------------
always @(*) begin : branch_proc
case (funct3) // synopsys full_case parallel_case
`BRANCH_BEQ : begin
branch_active_i = ~|xor_result;
end
`BRANCH_BNE : begin
branch_active_i = |xor_result;
end
`BRANCH_BLT : begin
branch_active_i = slt_result;
end
`BRANCH_BGE : begin
branch_active_i = ~slt_result;
end
`BRANCH_BLTU : begin
branch_active_i = sltu_result;
end
`BRANCH_BGEU : begin
branch_active_i = ~sltu_result;
end
default : begin
branch_active_i = 0;
end
endcase
end
always @(posedge clk, negedge reset_n) begin : branch_addr_proc
if (!reset_n) begin
branch_addr_i <= 0;
end else if (exe_enable) begin
branch_addr_i <= PC_in + B_immediate;
end
end
assign branch_active = (reg_ctl_BRANCH & branch_active_i) | (jal_active | jalr_active);
assign branch_addr = jalr_active ? jalr_addr : (jal_active?jal_addr:branch_addr_i);
//---------------------------------------------------------------------
// JALR
//---------------------------------------------------------------------
always @(posedge clk, negedge reset_n) begin : jalr_active_proc
if (!reset_n) begin
jalr_active <= 0;
end else if (exe_enable) begin
jalr_active <= ctl_JALR;
end else begin
jalr_active <= 0;
end
end
assign jalr_addr = (X + I_immediate) & {{(`XLEN - 1){1'b1}}, 1'b0};
//---------------------------------------------------------------------
// JAL
//---------------------------------------------------------------------
always @(posedge clk, negedge reset_n) begin : jal_active_proc
if (!reset_n) begin
jal_active <= 0;
jal_addr <= 0;
end else if (exe_enable) begin
jal_active <= ctl_JAL | ctl_MISC_MEM;
if (ctl_MISC_MEM) begin
jal_addr <= PC_in + 4;
end else begin
jal_addr <= PC_in + J_immediate;
end
end else begin
jal_active <= 0;
end
end
//---------------------------------------------------------------------
// CSR
//---------------------------------------------------------------------
always @(*) begin
case (funct3) // synopsys full_case parallel_case
`SYSTEM_CSRRW : begin
csr_new_value = X;
end
`SYSTEM_CSRRS : begin
csr_new_value = csr_in | X;
end
`SYSTEM_CSRRC : begin
csr_new_value = csr_in & (~X);
end
`SYSTEM_CSRRWI : begin
csr_new_value = csr_uimm_ext;
end
`SYSTEM_CSRRSI : begin
csr_new_value = csr_in | csr_uimm_ext;
end
`SYSTEM_CSRRCI : begin
csr_new_value = csr_in & (~csr_uimm_ext);
end
default : begin
csr_new_value = 0;
end
endcase
end
assign csr_old_value = csr_in;
always @(*) begin : ecall_ebreak_proc
if (funct3 == `SYSTEM_ECALL_EBREAK) begin
ecall_active_i = ~(|(IR_in [31 : 20]));
ebreak_active_i = (~(|(IR_in [31 : 21]))) & IR_in[20];
end else begin
ecall_active_i = 0;
ebreak_active_i = 0;
end
end
always @(posedge clk, negedge reset_n) begin : reg_ctl_CSR_proc
if (!reset_n) begin
reg_ctl_CSR <= 0;
reg_ctl_CSR_write <= 0;
csr_addr_out <= 0;
end else if (exe_enable) begin
reg_ctl_CSR <= ctl_CSR;
if ((funct3_in == `SYSTEM_CSRRW) || (funct3_in == `SYSTEM_CSRRWI)) begin
reg_ctl_CSR_write <= ctl_CSR;
end else begin
reg_ctl_CSR_write <= ctl_CSR_write;
end
csr_addr_out <= csr_addr_in;
end
end
//---------------------------------------------------------------------
// mul / div
//---------------------------------------------------------------------
generate
assign x_mul_div_signed0_unsigned1 = funct3 == `RV32M_MUL || funct3 == `RV32M_MULHU ||
funct3 == `RV32M_DIVU || funct3 == `RV32M_REMU;
assign y_mul_div_signed0_unsigned1 = funct3 == `RV32M_MUL || funct3 == `RV32M_MULHSU || funct3 == `RV32M_MULHU ||
funct3 == `RV32M_DIVU || funct3 == `RV32M_REMU;
assign mul_div_enable = exe_enable_d1 & reg_ctl_MUL_DIV_FUNCT3;
assign mul_div_active = reg_ctl_MUL_DIV_FUNCT3;
assign Q = Z[63 : 32];
assign R = Z[31 : 0];
if (`ENABLE_HW_MUL_DIV) begin
mul_div_32 mul_div_32_i (
.clk (clk),
.reset_n (reset_n),
.enable_in (mul_div_enable),
.x (X),
.y (Y),
.mul0_div1 (funct3[2]),
.x_signed0_unsigned1 (x_mul_div_signed0_unsigned1),
.y_signed0_unsigned1 (y_mul_div_signed0_unsigned1),
.enable_out (mul_div_enable_out),
.z (Z),
.ov (overflow_flag) );
always @(posedge clk, negedge reset_n) begin : mul_div_proc
if (!reset_n) begin
funct3_mul_div <= 0;
end else if (mul_div_enable) begin
funct3_mul_div <= funct3;
end
end
always @(*) begin : mul_div_reg_proc
case (funct3_mul_div) // synopsys full_case parallel_case
`RV32M_MUL : begin
mul_div_out_reg = Z [31 : 0];
end
`RV32M_MULH, `RV32M_MULHSU, `RV32M_MULHU : begin
mul_div_out_reg = Z [63 : 32];
end
`RV32M_DIVU : begin
mul_div_out_reg = Q;
end
`RV32M_REM, `RV32M_REMU : begin
mul_div_out_reg = R;
end
default : begin
if (overflow_flag) begin
mul_div_out_reg = 32'hFFFFFFFF;
end else begin
mul_div_out_reg = Q;
end
end
endcase
end
end
endgenerate
//---------------------------------------------------------------------
// data_out
//---------------------------------------------------------------------
always @(*) begin : data_out_proc
case (1'b1) // synopsys parallel_case
reg_ctl_LUI : begin
data_out = U_immediate;
end
reg_ctl_AUIPC : begin
data_out = AUIPC_out;
end
reg_ctl_JAL | reg_ctl_JALR : begin
data_out = PC_out + 4;
end
mul_div_done : begin
data_out = mul_div_out_reg;
end
default : begin
data_out = ALU_out;
end
endcase
end
//---------------------------------------------------------------------
// enable_out
//---------------------------------------------------------------------
always @(posedge clk, negedge reset_n) begin : output_proc
if (!reset_n) begin
rd_addr_out <= 0;
reg_ctl_save_to_rd <= 0;
load_active <= 0;
store_active <= 0;
end else if (exe_enable) begin
rd_addr_out <= IR_in [11 : 7];
reg_ctl_save_to_rd <= ctl_save_to_rd;
load_active <= ctl_LOAD;
store_active <= ctl_STORE;
end
end
assign data_to_store = Y;
assign mem_access_addr = ({32{ctl_STORE}} & (X + {{20{IR_out [31]}}, IR_out [31 : 25], IR_out [11 : 7]})) |
({32{ctl_LOAD}} & (X + {{20{IR_out[31]}}, IR_out[31 : 20]}));
assign mem_access_unaligned = (width == `WIDTH_32) ? (mem_access_addr[0] | mem_access_addr[1]) : ( (width == `WIDTH_16) || (width == `WIDTH_16U) ? mem_access_addr[0] : 0 );
assign width_load_store = width;
endmodule |
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