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module ct_ifu_sfp_entry(
cp0_ifu_icg_en,
cp0_ifu_nsfe,
cp0_yy_clk_en,
cpurst_b,
entry_bar_pc_updt_bit,
entry_bar_pc_v,
entry_clk_en_x,
entry_cnt_updt_bit,
entry_cnt_v,
entry_hi_pc_v,
entry_sf_pc_updt_bit,
entry_sf_pc_v,
entry_type_x,
entry_write_data,
entry_write_en_x,
forever_cpuclk,
pad_yy_icg_scan_en,
rtu_ifu_chgflw_vld,
sfp_vl_pred_en
);
// &Ports; @23
input cp0_ifu_icg_en;
input cp0_ifu_nsfe;
input cp0_yy_clk_en;
input cpurst_b;
input entry_bar_pc_updt_bit;
input entry_clk_en_x;
input entry_cnt_updt_bit;
input entry_sf_pc_updt_bit;
input [24:0] entry_write_data;
input entry_write_en_x;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input rtu_ifu_chgflw_vld;
input sfp_vl_pred_en;
output [11:0] entry_bar_pc_v;
output [1 :0] entry_cnt_v;
output [7 :0] entry_hi_pc_v;
output [11:0] entry_sf_pc_v;
output entry_type_x;
// &Regs; @24
reg [11:0] entry_bar_pc_v;
reg [1 :0] entry_cnt_pre;
reg [1 :0] entry_cnt_v;
reg [7 :0] entry_hi_pc_v;
reg entry_miss_state;
reg [11:0] entry_sf_pc_v;
reg entry_type_x;
// &Wires; @25
wire [1 :0] cnt_add;
wire [1 :0] cnt_sub;
wire cp0_ifu_icg_en;
wire cp0_ifu_nsfe;
wire cp0_yy_clk_en;
wire cpurst_b;
wire entry_bar_pc_updt_bit;
wire entry_bar_pc_updt_en;
wire entry_clk_en_x;
wire entry_cnt_updt_bit;
wire entry_cnt_updt_en;
wire entry_sf_pc_updt_bit;
wire entry_sf_pc_updt_en;
wire [24:0] entry_write_data;
wire entry_write_en_x;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire rtu_ifu_chgflw_vld;
wire sfp_entry_clk;
wire sfp_entry_clk_en;
wire sfp_vl_pred_en;
//==========================================================
// Entry Valid Signal
//==========================================================
//----------------------Gate Clock--------------------------
// &Instance("gated_clk_cell","x_sfp_entry_clk"); @31
gated_clk_cell x_sfp_entry_clk (
.clk_in (forever_cpuclk ),
.clk_out (sfp_entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (sfp_entry_clk_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @32
// .clk_out (sfp_entry_clk),//Out Clock @33
// .external_en (1'b0), @34
// .global_en (cp0_yy_clk_en), @35
// .local_en (sfp_entry_clk_en),//Local Condition @36
// .module_en (cp0_ifu_icg_en) @37
// ); @38
assign sfp_entry_clk_en = entry_clk_en_x
&& (cp0_ifu_nsfe || sfp_vl_pred_en);
assign entry_sf_pc_updt_en = entry_sf_pc_updt_bit
&& entry_write_en_x
&& (cp0_ifu_nsfe || sfp_vl_pred_en);
always @(posedge sfp_entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
entry_hi_pc_v[7:0] <= 8'b0;
entry_sf_pc_v[11:0] <= 12'b0;
entry_type_x <= 1'b0;
end
else if(entry_sf_pc_updt_en)
begin
entry_hi_pc_v[7:0] <= entry_write_data[23:16];
entry_sf_pc_v[11:0] <= entry_write_data[15:4];
entry_type_x <= entry_write_data[24];
end
else
begin
entry_hi_pc_v[7:0] <= entry_hi_pc_v[7:0];
entry_sf_pc_v[11:0] <= entry_sf_pc_v[11:0];
entry_type_x <= entry_type_x;
end
end
always @ (posedge sfp_entry_clk or negedge cpurst_b)
begin
if (~cpurst_b)
entry_miss_state <= 1'b0;
else if (entry_sf_pc_updt_en)
begin
if(entry_write_data[24] && entry_write_data[1])
entry_miss_state <= 1'b1;
else
entry_miss_state <= 1'b0;
end
else
entry_miss_state <= entry_miss_state;
end
assign entry_bar_pc_updt_en = entry_bar_pc_updt_bit
&& entry_write_en_x
&& (cp0_ifu_nsfe || sfp_vl_pred_en);
always @(posedge sfp_entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
entry_bar_pc_v[11:0] <= 12'b0;
else if(entry_bar_pc_updt_en)
entry_bar_pc_v[11:0] <= entry_write_data[15:4];
else
entry_bar_pc_v[11:0] <= entry_bar_pc_v[11:0];
end
// &CombBeg; @100
always @( entry_write_data[3:0]
or cnt_sub[1:0]
or entry_cnt_v[1:0]
or entry_write_data[24]
or cnt_add[1:0]
or entry_miss_state
or rtu_ifu_chgflw_vld)
begin
case(entry_write_data[3:0])
4'b1000: entry_cnt_pre[1:0] = 2'b00;
4'b0100: entry_cnt_pre[1:0] = (entry_write_data[24] && entry_cnt_v[1:0] == 2'b01)
? 2'b00
: cnt_add[1:0];
4'b0010: entry_cnt_pre[1:0] = 2'b01;
4'b0001: entry_cnt_pre[1:0] = (entry_miss_state && rtu_ifu_chgflw_vld)
? cnt_add[1:0]
: cnt_sub[1:0];
default: entry_cnt_pre[1:0] = 2'b0;
endcase
// &CombEnd; @112
end
assign cnt_add[1:0] = (entry_cnt_v[1:0] == 2'b11)
? 2'b11
: entry_cnt_v[1:0] + 2'b01;
assign cnt_sub[1:0] = (entry_cnt_v[1:0] == 2'b00)
? 2'b00
: entry_cnt_v[1:0] - 2'b01;
assign entry_cnt_updt_en = entry_cnt_updt_bit
&& entry_write_en_x
&& (cp0_ifu_nsfe || sfp_vl_pred_en);
always @(posedge sfp_entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
entry_cnt_v[1:0] <= 2'b0;
else if(entry_cnt_updt_en)
entry_cnt_v[1:0] <= entry_cnt_pre[1:0];
else
entry_cnt_v[1:0] <= entry_cnt_v[1:0];
end
// &Force("output","entry_hi_pc_v"); @136
// &Force("output","entry_sf_pc_v"); @137
// &Force("output","entry_bar_pc_v"); @138
// &Force("output","entry_cnt_v"); @139
// &Force("output", "entry_type_x"); @140
// &ModuleEnd; @142
endmodule |
module ct_ifu_icache_if(
cp0_ifu_icache_en,
cp0_ifu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
hpcp_ifu_cnt_en,
icache_if_ifctrl_inst_data0,
icache_if_ifctrl_inst_data1,
icache_if_ifctrl_tag_data0,
icache_if_ifctrl_tag_data1,
icache_if_ifdp_fifo,
icache_if_ifdp_inst_data0,
icache_if_ifdp_inst_data1,
icache_if_ifdp_precode0,
icache_if_ifdp_precode1,
icache_if_ifdp_tag_data0,
icache_if_ifdp_tag_data1,
icache_if_ipb_tag_data0,
icache_if_ipb_tag_data1,
ifctrl_icache_if_index,
ifctrl_icache_if_inv_fifo,
ifctrl_icache_if_inv_on,
ifctrl_icache_if_read_req_data0,
ifctrl_icache_if_read_req_data1,
ifctrl_icache_if_read_req_index,
ifctrl_icache_if_read_req_tag,
ifctrl_icache_if_reset_req,
ifctrl_icache_if_tag_req,
ifctrl_icache_if_tag_wen,
ifu_hpcp_icache_access,
ifu_hpcp_icache_miss,
ifu_hpcp_icache_miss_pre,
ipb_icache_if_index,
ipb_icache_if_req,
ipb_icache_if_req_for_gateclk,
l1_refill_icache_if_fifo,
l1_refill_icache_if_first,
l1_refill_icache_if_index,
l1_refill_icache_if_inst_data,
l1_refill_icache_if_last,
l1_refill_icache_if_pre_code,
l1_refill_icache_if_ptag,
l1_refill_icache_if_wr,
pad_yy_icg_scan_en,
pcgen_icache_if_chgflw,
pcgen_icache_if_chgflw_bank0,
pcgen_icache_if_chgflw_bank1,
pcgen_icache_if_chgflw_bank2,
pcgen_icache_if_chgflw_bank3,
pcgen_icache_if_chgflw_short,
pcgen_icache_if_gateclk_en,
pcgen_icache_if_index,
pcgen_icache_if_seq_data_req,
pcgen_icache_if_seq_data_req_short,
pcgen_icache_if_seq_tag_req,
pcgen_icache_if_way_pred
);
// &Ports; @23
input cp0_ifu_icache_en;
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input hpcp_ifu_cnt_en;
input [38 :0] ifctrl_icache_if_index;
input ifctrl_icache_if_inv_fifo;
input ifctrl_icache_if_inv_on;
input ifctrl_icache_if_read_req_data0;
input ifctrl_icache_if_read_req_data1;
input [38 :0] ifctrl_icache_if_read_req_index;
input ifctrl_icache_if_read_req_tag;
input ifctrl_icache_if_reset_req;
input ifctrl_icache_if_tag_req;
input [2 :0] ifctrl_icache_if_tag_wen;
input ifu_hpcp_icache_miss_pre;
input [33 :0] ipb_icache_if_index;
input ipb_icache_if_req;
input ipb_icache_if_req_for_gateclk;
input l1_refill_icache_if_fifo;
input l1_refill_icache_if_first;
input [38 :0] l1_refill_icache_if_index;
input [127:0] l1_refill_icache_if_inst_data;
input l1_refill_icache_if_last;
input [31 :0] l1_refill_icache_if_pre_code;
input [27 :0] l1_refill_icache_if_ptag;
input l1_refill_icache_if_wr;
input pad_yy_icg_scan_en;
input pcgen_icache_if_chgflw;
input pcgen_icache_if_chgflw_bank0;
input pcgen_icache_if_chgflw_bank1;
input pcgen_icache_if_chgflw_bank2;
input pcgen_icache_if_chgflw_bank3;
input pcgen_icache_if_chgflw_short;
input pcgen_icache_if_gateclk_en;
input [15 :0] pcgen_icache_if_index;
input pcgen_icache_if_seq_data_req;
input pcgen_icache_if_seq_data_req_short;
input pcgen_icache_if_seq_tag_req;
input [1 :0] pcgen_icache_if_way_pred;
output [127:0] icache_if_ifctrl_inst_data0;
output [127:0] icache_if_ifctrl_inst_data1;
output [28 :0] icache_if_ifctrl_tag_data0;
output [28 :0] icache_if_ifctrl_tag_data1;
output icache_if_ifdp_fifo;
output [127:0] icache_if_ifdp_inst_data0;
output [127:0] icache_if_ifdp_inst_data1;
output [31 :0] icache_if_ifdp_precode0;
output [31 :0] icache_if_ifdp_precode1;
output [28 :0] icache_if_ifdp_tag_data0;
output [28 :0] icache_if_ifdp_tag_data1;
output [28 :0] icache_if_ipb_tag_data0;
output [28 :0] icache_if_ipb_tag_data1;
output ifu_hpcp_icache_access;
output ifu_hpcp_icache_miss;
// &Regs; @24
reg [15 :0] icache_index_higher;
reg ifu_hpcp_icache_access_reg;
reg ifu_hpcp_icache_miss_reg;
reg [2 :0] ifu_icache_tag_wen;
// &Wires; @25
wire cp0_ifu_icache_en;
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire fifo_bit;
wire forever_cpuclk;
wire hpcp_clk;
wire hpcp_clk_en;
wire hpcp_ifu_cnt_en;
wire [127:0] icache_if_ifctrl_inst_data0;
wire [127:0] icache_if_ifctrl_inst_data1;
wire [28 :0] icache_if_ifctrl_tag_data0;
wire [28 :0] icache_if_ifctrl_tag_data1;
wire icache_if_ifdp_fifo;
wire [127:0] icache_if_ifdp_inst_data0;
wire [127:0] icache_if_ifdp_inst_data1;
wire [31 :0] icache_if_ifdp_precode0;
wire [31 :0] icache_if_ifdp_precode1;
wire [28 :0] icache_if_ifdp_tag_data0;
wire [28 :0] icache_if_ifdp_tag_data1;
wire [28 :0] icache_if_ipb_tag_data0;
wire [28 :0] icache_if_ipb_tag_data1;
wire [127:0] icache_ifu_data_array0_dout;
wire [127:0] icache_ifu_data_array1_dout;
wire [31 :0] icache_ifu_predecd_array0_dout;
wire [31 :0] icache_ifu_predecd_array1_dout;
wire [58 :0] icache_ifu_tag_dout;
wire [3 :0] icache_index_sel;
wire icache_read_req;
wire icache_req_higher;
wire icache_reset_inv;
wire [1 :0] icache_way_pred;
wire [38 :0] ifctrl_icache_if_index;
wire ifctrl_icache_if_inv_fifo;
wire ifctrl_icache_if_inv_on;
wire ifctrl_icache_if_read_req_data0;
wire ifctrl_icache_if_read_req_data1;
wire [38 :0] ifctrl_icache_if_read_req_index;
wire ifctrl_icache_if_read_req_tag;
wire ifctrl_icache_if_reset_req;
wire ifctrl_icache_if_tag_req;
wire [2 :0] ifctrl_icache_if_tag_wen;
wire ifu_hpcp_icache_access;
wire ifu_hpcp_icache_access_pre;
wire ifu_hpcp_icache_miss;
wire ifu_hpcp_icache_miss_pre;
wire ifu_icache_data_array0_bank0_cen_b;
wire ifu_icache_data_array0_bank0_clk_en;
wire ifu_icache_data_array0_bank1_cen_b;
wire ifu_icache_data_array0_bank1_clk_en;
wire ifu_icache_data_array0_bank2_cen_b;
wire ifu_icache_data_array0_bank2_clk_en;
wire ifu_icache_data_array0_bank3_cen_b;
wire ifu_icache_data_array0_bank3_clk_en;
wire [127:0] ifu_icache_data_array0_din;
wire ifu_icache_data_array0_wen_b;
wire ifu_icache_data_array1_bank0_cen_b;
wire ifu_icache_data_array1_bank0_clk_en;
wire ifu_icache_data_array1_bank1_cen_b;
wire ifu_icache_data_array1_bank1_clk_en;
wire ifu_icache_data_array1_bank2_cen_b;
wire ifu_icache_data_array1_bank2_clk_en;
wire ifu_icache_data_array1_bank3_cen_b;
wire ifu_icache_data_array1_bank3_clk_en;
wire [127:0] ifu_icache_data_array1_din;
wire ifu_icache_data_array1_wen_b;
wire [15 :0] ifu_icache_index;
wire ifu_icache_predecd_array0_cen_b;
wire ifu_icache_predecd_array0_clk_en;
wire [31 :0] ifu_icache_predecd_array0_din;
wire ifu_icache_predecd_array0_wen_b;
wire ifu_icache_predecd_array1_cen_b;
wire ifu_icache_predecd_array1_clk_en;
wire [31 :0] ifu_icache_predecd_array1_din;
wire ifu_icache_predecd_array1_wen_b;
wire ifu_icache_tag_cen_b;
wire ifu_icache_tag_clk_en;
wire [58 :0] ifu_icache_tag_din;
wire [33 :0] ipb_icache_if_index;
wire ipb_icache_if_req;
wire ipb_icache_if_req_for_gateclk;
wire l1_refill_icache_if_fifo;
wire l1_refill_icache_if_first;
wire [38 :0] l1_refill_icache_if_index;
wire [127:0] l1_refill_icache_if_inst_data;
wire l1_refill_icache_if_last;
wire [31 :0] l1_refill_icache_if_pre_code;
wire [27 :0] l1_refill_icache_if_ptag;
wire l1_refill_icache_if_wr;
wire pad_yy_icg_scan_en;
wire pcgen_icache_if_chgflw;
wire pcgen_icache_if_chgflw_bank0;
wire pcgen_icache_if_chgflw_bank1;
wire pcgen_icache_if_chgflw_bank2;
wire pcgen_icache_if_chgflw_bank3;
wire pcgen_icache_if_chgflw_short;
wire pcgen_icache_if_gateclk_en;
wire [15 :0] pcgen_icache_if_index;
wire pcgen_icache_if_seq_data_req;
wire pcgen_icache_if_seq_data_req_short;
wire pcgen_icache_if_seq_tag_req;
wire [1 :0] pcgen_icache_if_way_pred;
wire tag_fifo_din;
wire [27 :0] tag_pc_din;
wire tag_valid_din;
parameter PC_WIDTH = 40;
// &Force("bus","ifctrl_icache_if_index",38,0); @28
// &Force("bus","ifctrl_icache_if_read_req_index",38,0); @29
// &Force("bus","l1_refill_icache_if_index",38,0); @30
// &Force("bus","ipb_icache_if_index",33,0); @31
//==========================================================
// Chip Enable to Cache Tag Array
//==========================================================
//ICache Tag Array is Enable When:
// 1.Write Enable
// a.Icache Invalid Write
// b.Refill SM Data first || Data last
// 2.Read Enable
// a.Icache Invalid Read
// b.Change Flow && (!Way_pred[1:0] == 2'b00)
// c.Sequence Read && Data first
// d.Vector SM Read
// e.Prefetch Read
assign ifu_icache_tag_cen_b = !(l1_refill_icache_if_wr &&
(l1_refill_icache_if_first ||
l1_refill_icache_if_last) &&
cp0_ifu_icache_en
) &&
!(ifctrl_icache_if_tag_req
) &&
!(pcgen_icache_if_chgflw &&
(pcgen_icache_if_way_pred[1:0] != 2'b00) &&
cp0_ifu_icache_en
) &&
!(pcgen_icache_if_seq_tag_req && //Seq && !Stall
cp0_ifu_icache_en
) &&
!(ipb_icache_if_req &&
cp0_ifu_icache_en
) &&
!ifctrl_icache_if_read_req_tag;
//Gate Clk Enable Signal for Memory Gate Clk
assign ifu_icache_tag_clk_en = ifctrl_icache_if_tag_req ||
ifctrl_icache_if_read_req_tag ||
cp0_ifu_icache_en &&
(
l1_refill_icache_if_wr ||
pcgen_icache_if_gateclk_en ||
ipb_icache_if_req_for_gateclk
);
//==========================================================
// Write Enable to Icache Tag Array
//==========================================================
//ICache Tag Array is Written When:
// 1.Icache is being Invalidated
// 2.Icache is being Refilled
// a.first cycle data : clear valid bit && fifo bit not change
// b.last cycle data : Set valid bit && fifo bit change
//FIFO bit wen
// &CombBeg; @83
always @( ifctrl_icache_if_tag_wen[2]
or ifctrl_icache_if_inv_on
or l1_refill_icache_if_wr
or l1_refill_icache_if_last)
begin
if(ifctrl_icache_if_inv_on)
ifu_icache_tag_wen[2] = ifctrl_icache_if_tag_wen[2];
else if(l1_refill_icache_if_wr && l1_refill_icache_if_last)
ifu_icache_tag_wen[2] = 1'b0;
else
ifu_icache_tag_wen[2] = 1'b1;
// &CombEnd; @90
end
// &CombBeg; @92
always @( ifctrl_icache_if_inv_on
or ifctrl_icache_if_tag_wen[1:0]
or l1_refill_icache_if_wr
or l1_refill_icache_if_first
or l1_refill_icache_if_last
or fifo_bit)
begin
if(ifctrl_icache_if_inv_on)
ifu_icache_tag_wen[1:0] = ifctrl_icache_if_tag_wen[1:0];
else if(l1_refill_icache_if_wr &&
(l1_refill_icache_if_first || l1_refill_icache_if_last))
ifu_icache_tag_wen[1:0] = {!fifo_bit, fifo_bit};
else
ifu_icache_tag_wen[1:0] = 2'b11;
// &CombEnd; @104
end
assign fifo_bit = l1_refill_icache_if_fifo;
//==========================================================
// Write Data to Icache Tag Array
//==========================================================
//Data Write to ICache Tag Array:
// 1. 1bit FIFO bit * 1
// 2. 1bit Valid bit * 2
// 3. 20bit Tag Data * 2
assign tag_fifo_din = (ifctrl_icache_if_inv_on)
? ifctrl_icache_if_inv_fifo
: !fifo_bit;
//Only When refill last, Valid Bit will Be 1
assign tag_valid_din = l1_refill_icache_if_last;
assign tag_pc_din[27:0] = (ifctrl_icache_if_inv_on || l1_refill_icache_if_first)
? 28'b0
: l1_refill_icache_if_ptag[27:0];
assign ifu_icache_tag_din[58:0] = {tag_fifo_din,
tag_valid_din, tag_pc_din[27:0],
tag_valid_din, tag_pc_din[27:0]
};
//==========================================================
// Chip Enable to Icache Data Array
//==========================================================
//Icache Data Array in Enable When:
// 1.Write Enable
// a.Refill data Valid
// 2.Read Enable
// a.Change Flow && way_pred
// b.Sequence without Stall && way_pred
// c.Vector SM Read
//assign icache_way_pred[1:0] = (l1_refill_icache_if_wr || vector_icache_if_req)
assign icache_way_pred[1:0] = (l1_refill_icache_if_wr)
? 2'b11
: pcgen_icache_if_way_pred[1:0];
assign icache_reset_inv = ifctrl_icache_if_reset_req;
assign ifu_icache_data_array0_bank0_cen_b = (
!(l1_refill_icache_if_wr && !fifo_bit
) &&
!(pcgen_icache_if_chgflw_bank0
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[0])
) &&
!ifctrl_icache_if_read_req_data0 &&
!icache_reset_inv;
assign ifu_icache_data_array0_bank1_cen_b = (
!(l1_refill_icache_if_wr && !fifo_bit
) &&
!(pcgen_icache_if_chgflw_bank1
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[0])
) &&
!ifctrl_icache_if_read_req_data0 &&
!icache_reset_inv;
assign ifu_icache_data_array0_bank2_cen_b = (
!(l1_refill_icache_if_wr && !fifo_bit
) &&
!(pcgen_icache_if_chgflw_bank2
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[0])
) &&
!ifctrl_icache_if_read_req_data0 &&
!icache_reset_inv;
assign ifu_icache_data_array0_bank3_cen_b = (
!(l1_refill_icache_if_wr && !fifo_bit
) &&
!(pcgen_icache_if_chgflw_bank3
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[0])
) &&
!ifctrl_icache_if_read_req_data0 &&
!icache_reset_inv;
assign ifu_icache_data_array1_bank0_cen_b = (
!(l1_refill_icache_if_wr && fifo_bit
) &&
!(pcgen_icache_if_chgflw_bank0
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[1])
) &&
!ifctrl_icache_if_read_req_data1 &&
!icache_reset_inv;
assign ifu_icache_data_array1_bank1_cen_b = (
!(l1_refill_icache_if_wr && fifo_bit
) &&
!(pcgen_icache_if_chgflw_bank1
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[1])
) &&
!ifctrl_icache_if_read_req_data1 &&
!icache_reset_inv;
assign ifu_icache_data_array1_bank2_cen_b = (
!(l1_refill_icache_if_wr && fifo_bit
) &&
!(pcgen_icache_if_chgflw_bank2
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[1])
) &&
!ifctrl_icache_if_read_req_data1 &&
!icache_reset_inv;
assign ifu_icache_data_array1_bank3_cen_b = (
!(l1_refill_icache_if_wr && fifo_bit
) &&
!(pcgen_icache_if_chgflw_bank3
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[1])
) &&
!ifctrl_icache_if_read_req_data1 &&
!icache_reset_inv;
//Gate Clk Enable Signal for Memory Gate Clk
assign ifu_icache_data_array0_bank0_clk_en = (
l1_refill_icache_if_wr && !fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
ifctrl_icache_if_read_req_data0 ||
icache_reset_inv;
assign ifu_icache_data_array0_bank1_clk_en = (
l1_refill_icache_if_wr && !fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
ifctrl_icache_if_read_req_data0 ||
icache_reset_inv;
assign ifu_icache_data_array0_bank2_clk_en = (
l1_refill_icache_if_wr && !fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
ifctrl_icache_if_read_req_data0 ||
icache_reset_inv;
assign ifu_icache_data_array0_bank3_clk_en = (
l1_refill_icache_if_wr && !fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
ifctrl_icache_if_read_req_data0 ||
icache_reset_inv;
assign ifu_icache_data_array1_bank0_clk_en = (
l1_refill_icache_if_wr && fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
ifctrl_icache_if_read_req_data1 ||
icache_reset_inv;
assign ifu_icache_data_array1_bank1_clk_en = (
l1_refill_icache_if_wr && fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
ifctrl_icache_if_read_req_data1 ||
icache_reset_inv;
assign ifu_icache_data_array1_bank2_clk_en = (
l1_refill_icache_if_wr && fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
ifctrl_icache_if_read_req_data1 ||
icache_reset_inv;
assign ifu_icache_data_array1_bank3_clk_en = (
l1_refill_icache_if_wr && fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
ifctrl_icache_if_read_req_data1 ||
icache_reset_inv;
//==========================================================
// Write Enable to Icache Data Array
//==========================================================
//Icache Data Array is written when:
// 1.Refill data Valid
assign ifu_icache_data_array0_wen_b = !(l1_refill_icache_if_wr && !fifo_bit
) &&
!icache_reset_inv;
assign ifu_icache_data_array1_wen_b = !(l1_refill_icache_if_wr && fifo_bit
) &&
!icache_reset_inv;
//==========================================================
// Write Data to Icache Data Array
//==========================================================
assign ifu_icache_data_array0_din[127:0] = (icache_reset_inv) ? 128'b0 : l1_refill_icache_if_inst_data[127:0];
assign ifu_icache_data_array1_din[127:0] = (icache_reset_inv) ? 128'b0 : l1_refill_icache_if_inst_data[127:0];
//==========================================================
// Chip Enable to Icache Predecode Array
//==========================================================
assign ifu_icache_predecd_array0_cen_b = ( !(l1_refill_icache_if_wr && !fifo_bit
) &&
!(pcgen_icache_if_chgflw
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[0])
) &&
!icache_reset_inv;
assign ifu_icache_predecd_array1_cen_b = ( !(l1_refill_icache_if_wr && fifo_bit
) &&
!(pcgen_icache_if_chgflw
) &&
!(pcgen_icache_if_seq_data_req
)
|| !(cp0_ifu_icache_en && icache_way_pred[1])
) &&
!icache_reset_inv;
//Gate Clk Enable Signal for Memory Gate Clk
assign ifu_icache_predecd_array0_clk_en = (
l1_refill_icache_if_wr && !fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
icache_reset_inv;
assign ifu_icache_predecd_array1_clk_en = (
l1_refill_icache_if_wr && fifo_bit ||
pcgen_icache_if_chgflw_short ||
pcgen_icache_if_seq_data_req_short
) &&
cp0_ifu_icache_en ||
icache_reset_inv;
//==========================================================
// Write Enable to Icache Predecode Array
//==========================================================
//Icache Predecode Array is written when:
// 1.Refill data Valid
assign ifu_icache_predecd_array0_wen_b = !(l1_refill_icache_if_wr && !fifo_bit) &&
!icache_reset_inv;
assign ifu_icache_predecd_array1_wen_b = !(l1_refill_icache_if_wr && fifo_bit) &&
!icache_reset_inv;
//==========================================================
// Write Data to Icache Predecode Array
//==========================================================
assign ifu_icache_predecd_array0_din[31:0] = (icache_reset_inv) ? 32'b0 : l1_refill_icache_if_pre_code[31:0];
assign ifu_icache_predecd_array1_din[31:0] = (icache_reset_inv) ? 32'b0 : l1_refill_icache_if_pre_code[31:0];
//==========================================================
// Index to Icache
//==========================================================
//Index to Icache Tag Array
// 1.INV Index
// 2.Vector Index
// 3.Refill Index
// 4.Ipb Index
// ipb index request will only be valid when
// a.rifill state machine in REQ state && biu_refill_grnt
// b.biu_refill_grnt doesnot arrive witn change flow at the same time
// 5.PCgen Index
//Using & | logic to save timing
//for four condition will not set at the same time
assign ifu_icache_index[15:0] = (icache_req_higher)
? icache_index_higher[15:0]
: pcgen_icache_if_index[15:0];
assign icache_req_higher = ifctrl_icache_if_tag_req ||
ifctrl_icache_if_reset_req ||
// vector_icache_if_req ||
l1_refill_icache_if_wr ||
ipb_icache_if_req ||
ifctrl_icache_if_read_req_data0 ||
ifctrl_icache_if_read_req_data1 ||
ifctrl_icache_if_read_req_tag;
//Icache read can from
//1. icache read data/tag request
//2. icache refill write request
//3. ipb read request(for tag compare)
//4. icache read tag request for inv va/pa
assign icache_read_req = ifctrl_icache_if_read_req_data0 ||
ifctrl_icache_if_read_req_data1 ||
ifctrl_icache_if_read_req_tag;
assign icache_index_sel[3:0] = {ifctrl_icache_if_tag_req || ifctrl_icache_if_reset_req,
l1_refill_icache_if_wr,
ipb_icache_if_req,
icache_read_req};
// &CombBeg; @429
always @( l1_refill_icache_if_index[15:0]
or icache_index_sel[3:0]
or ifctrl_icache_if_read_req_index[15:0]
or ipb_icache_if_index[10:0]
or ifctrl_icache_if_index[15:0])
begin
case(icache_index_sel[3:0])
4'b1000: icache_index_higher[15:0] = ifctrl_icache_if_index[15:0];
4'b0100: icache_index_higher[15:0] = l1_refill_icache_if_index[15:0];
4'b0010: icache_index_higher[15:0] = {ipb_icache_if_index[10:0],5'b0};
4'b0001: icache_index_higher[15:0] = ifctrl_icache_if_read_req_index[15:0];
default: icache_index_higher[15:0] = {16{1'bx}};
endcase
// &CombEnd; @437
end
//==========================================================
// Icache Tag Array Output Data
//==========================================================
assign icache_if_ifdp_tag_data0[28:0] = icache_ifu_tag_dout[28:0];
assign icache_if_ifdp_tag_data1[28:0] = icache_ifu_tag_dout[57:29];
assign icache_if_ifdp_fifo = icache_ifu_tag_dout[58];
assign icache_if_ifctrl_tag_data0[28:0] = icache_ifu_tag_dout[28:0];
assign icache_if_ifctrl_tag_data1[28:0] = icache_ifu_tag_dout[57:29];
assign icache_if_ifctrl_inst_data0[127:0] = icache_ifu_data_array0_dout[127: 0];
assign icache_if_ifctrl_inst_data1[127:0] = icache_ifu_data_array1_dout[127: 0];
//==========================================================
// Icache Data Array Output Data
//==========================================================
assign icache_if_ifdp_precode0[31:0] = icache_ifu_predecd_array0_dout[31:0];
assign icache_if_ifdp_inst_data0[127:0] = icache_ifu_data_array0_dout[127:0];
assign icache_if_ifdp_precode1[31:0] = icache_ifu_predecd_array1_dout[31:0];
assign icache_if_ifdp_inst_data1[127:0] = icache_ifu_data_array1_dout[127:0];
//==========================================================
// Interactive with Vector
//==========================================================
//assign icache_if_vector_data0_dout[127:0] = icache_ifu_data_array0_dout[127:0];
//assign icache_if_vector_data1_dout[127:0] = icache_ifu_data_array1_dout[127:0];
//assign icache_if_vector_tag0_dout[28:0] = icache_ifu_tag_dout[28: 0];
//assign icache_if_vector_tag1_dout[28:0] = icache_ifu_tag_dout[57:29];
//==========================================================
// Interactive with Ipb
//==========================================================
assign icache_if_ipb_tag_data0[28:0] = icache_ifu_tag_dout[28: 0];
assign icache_if_ipb_tag_data1[28:0] = icache_ifu_tag_dout[57:29];
//==========================================================
// Interactive with PMU
//==========================================================
assign ifu_hpcp_icache_access_pre = (pcgen_icache_if_seq_data_req || pcgen_icache_if_chgflw)&& cp0_ifu_icache_en;
// ifu_hpcp_icache_miss_pre
// &Instance("gated_clk_cell","x_hpcp_clk"); @522
gated_clk_cell x_hpcp_clk (
.clk_in (forever_cpuclk ),
.clk_out (hpcp_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (hpcp_clk_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @523
// .clk_out (hpcp_clk),//Out Clock @524
// .external_en (1'b0), @525
// .global_en (cp0_yy_clk_en), @526
// .local_en (hpcp_clk_en),//Local Condition @527
// .module_en (cp0_ifu_icg_en) @528
// ); @529
assign hpcp_clk_en = cp0_ifu_icache_en && hpcp_ifu_cnt_en;
always @(posedge hpcp_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
ifu_hpcp_icache_access_reg <= 1'b0;
ifu_hpcp_icache_miss_reg <= 1'b0;
end
else if(cp0_ifu_icache_en && hpcp_ifu_cnt_en)
begin
ifu_hpcp_icache_access_reg <= ifu_hpcp_icache_access_pre;
ifu_hpcp_icache_miss_reg <= ifu_hpcp_icache_miss_pre;
end
else
begin
ifu_hpcp_icache_access_reg <= ifu_hpcp_icache_access_reg;
ifu_hpcp_icache_miss_reg <= ifu_hpcp_icache_miss_reg;
end
end
assign ifu_hpcp_icache_access = ifu_hpcp_icache_access_reg;
assign ifu_hpcp_icache_miss = ifu_hpcp_icache_miss_reg;
//==========================================================
// Memory Connect -- Tag Array
//==========================================================
// &Instance("ct_ifu_icache_tag_array", "x_ct_ifu_icache_tag_array"); @558
ct_ifu_icache_tag_array x_ct_ifu_icache_tag_array (
.cp0_ifu_icg_en (cp0_ifu_icg_en ),
.forever_cpuclk (forever_cpuclk ),
.icache_ifu_tag_dout (icache_ifu_tag_dout ),
.ifu_icache_index (ifu_icache_index ),
.ifu_icache_tag_cen_b (ifu_icache_tag_cen_b ),
.ifu_icache_tag_clk_en (ifu_icache_tag_clk_en),
.ifu_icache_tag_din (ifu_icache_tag_din ),
.ifu_icache_tag_wen (ifu_icache_tag_wen ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_ifu_icache_data_array0", "x_ct_ifu_icache_data_array0"); @559
ct_ifu_icache_data_array0 x_ct_ifu_icache_data_array0 (
.cp0_ifu_icg_en (cp0_ifu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.forever_cpuclk (forever_cpuclk ),
.icache_ifu_data_array0_dout (icache_ifu_data_array0_dout ),
.ifu_icache_data_array0_bank0_cen_b (ifu_icache_data_array0_bank0_cen_b ),
.ifu_icache_data_array0_bank0_clk_en (ifu_icache_data_array0_bank0_clk_en),
.ifu_icache_data_array0_bank1_cen_b (ifu_icache_data_array0_bank1_cen_b ),
.ifu_icache_data_array0_bank1_clk_en (ifu_icache_data_array0_bank1_clk_en),
.ifu_icache_data_array0_bank2_cen_b (ifu_icache_data_array0_bank2_cen_b ),
.ifu_icache_data_array0_bank2_clk_en (ifu_icache_data_array0_bank2_clk_en),
.ifu_icache_data_array0_bank3_cen_b (ifu_icache_data_array0_bank3_cen_b ),
.ifu_icache_data_array0_bank3_clk_en (ifu_icache_data_array0_bank3_clk_en),
.ifu_icache_data_array0_din (ifu_icache_data_array0_din ),
.ifu_icache_data_array0_wen_b (ifu_icache_data_array0_wen_b ),
.ifu_icache_index (ifu_icache_index ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_ifu_icache_data_array1", "x_ct_ifu_icache_data_array1"); @560
ct_ifu_icache_data_array1 x_ct_ifu_icache_data_array1 (
.cp0_ifu_icg_en (cp0_ifu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.forever_cpuclk (forever_cpuclk ),
.icache_ifu_data_array1_dout (icache_ifu_data_array1_dout ),
.ifu_icache_data_array1_bank0_cen_b (ifu_icache_data_array1_bank0_cen_b ),
.ifu_icache_data_array1_bank0_clk_en (ifu_icache_data_array1_bank0_clk_en),
.ifu_icache_data_array1_bank1_cen_b (ifu_icache_data_array1_bank1_cen_b ),
.ifu_icache_data_array1_bank1_clk_en (ifu_icache_data_array1_bank1_clk_en),
.ifu_icache_data_array1_bank2_cen_b (ifu_icache_data_array1_bank2_cen_b ),
.ifu_icache_data_array1_bank2_clk_en (ifu_icache_data_array1_bank2_clk_en),
.ifu_icache_data_array1_bank3_cen_b (ifu_icache_data_array1_bank3_cen_b ),
.ifu_icache_data_array1_bank3_clk_en (ifu_icache_data_array1_bank3_clk_en),
.ifu_icache_data_array1_din (ifu_icache_data_array1_din ),
.ifu_icache_data_array1_wen_b (ifu_icache_data_array1_wen_b ),
.ifu_icache_index (ifu_icache_index ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_ifu_icache_predecd_array0","x_ct_ifu_icache_predecd_array0"); @561
ct_ifu_icache_predecd_array0 x_ct_ifu_icache_predecd_array0 (
.cp0_ifu_icg_en (cp0_ifu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.forever_cpuclk (forever_cpuclk ),
.icache_ifu_predecd_array0_dout (icache_ifu_predecd_array0_dout ),
.ifu_icache_data_array0_wen_b (ifu_icache_data_array0_wen_b ),
.ifu_icache_index (ifu_icache_index ),
.ifu_icache_predecd_array0_cen_b (ifu_icache_predecd_array0_cen_b ),
.ifu_icache_predecd_array0_clk_en (ifu_icache_predecd_array0_clk_en),
.ifu_icache_predecd_array0_din (ifu_icache_predecd_array0_din ),
.ifu_icache_predecd_array0_wen_b (ifu_icache_predecd_array0_wen_b ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_ifu_icache_predecd_array1","x_ct_ifu_icache_predecd_array1"); @562
ct_ifu_icache_predecd_array1 x_ct_ifu_icache_predecd_array1 (
.cp0_ifu_icg_en (cp0_ifu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.forever_cpuclk (forever_cpuclk ),
.icache_ifu_predecd_array1_dout (icache_ifu_predecd_array1_dout ),
.ifu_icache_data_array1_wen_b (ifu_icache_data_array1_wen_b ),
.ifu_icache_index (ifu_icache_index ),
.ifu_icache_predecd_array1_cen_b (ifu_icache_predecd_array1_cen_b ),
.ifu_icache_predecd_array1_clk_en (ifu_icache_predecd_array1_clk_en),
.ifu_icache_predecd_array1_din (ifu_icache_predecd_array1_din ),
.ifu_icache_predecd_array1_wen_b (ifu_icache_predecd_array1_wen_b ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &ModuleEnd; @564
endmodule |
module ct_ifu_l0_btb_entry(
cp0_ifu_btb_en,
cp0_ifu_icg_en,
cp0_ifu_l0btb_en,
cp0_yy_clk_en,
cpurst_b,
entry_cnt,
entry_inv,
entry_ras,
entry_tag,
entry_target,
entry_update,
entry_update_cnt,
entry_update_data,
entry_update_ras,
entry_update_vld,
entry_vld,
entry_way_pred,
entry_wen,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @23
input cp0_ifu_btb_en;
input cp0_ifu_icg_en;
input cp0_ifu_l0btb_en;
input cp0_yy_clk_en;
input cpurst_b;
input entry_inv;
input entry_update;
input entry_update_cnt;
input [36:0] entry_update_data;
input entry_update_ras;
input entry_update_vld;
input [3 :0] entry_wen;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output entry_cnt;
output entry_ras;
output [14:0] entry_tag;
output [19:0] entry_target;
output entry_vld;
output [1 :0] entry_way_pred;
// &Regs; @24
reg entry_cnt;
reg entry_ras;
reg [14:0] entry_tag;
reg [19:0] entry_target;
reg entry_vld;
reg [1 :0] entry_way_pred;
// &Wires; @25
wire cp0_ifu_btb_en;
wire cp0_ifu_icg_en;
wire cp0_ifu_l0btb_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire entry_clk;
wire entry_clk_en;
wire entry_inv;
wire entry_update;
wire entry_update_cnt;
wire [36:0] entry_update_data;
wire entry_update_en;
wire entry_update_ras;
wire entry_update_vld;
wire [3 :0] entry_wen;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
// &Instance("gated_clk_cell", "x_l0_btb_entry_gatedclk"); @27
gated_clk_cell x_l0_btb_entry_gatedclk (
.clk_in (forever_cpuclk ),
.clk_out (entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (entry_clk_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @28
// .external_en (1'b0 ), @29
// .global_en (cp0_yy_clk_en ), @30
// .module_en (cp0_ifu_icg_en), @31
// .local_en (entry_clk_en ), @32
// .clk_out (entry_clk ) @33
// ); @34
assign entry_clk_en = entry_update_en;
assign entry_update_en = entry_update
&& cp0_ifu_btb_en
&& cp0_ifu_l0btb_en;
//=========================================================
// contents of one L0 BTB entry
//=========================================================
// +-----------+-----------+---------------+--------------+
// | entry_vld | tag[10:0] | way_pred[1:0] | target[19:0] |
// +-----------+-----------+---------------+--------------+
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
entry_vld <= 1'b0;
else if(entry_inv)
entry_vld <= 1'b0;
else if(entry_wen[3] && entry_update_en)
entry_vld <= entry_update_vld;
else
entry_vld <= entry_vld;
end
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
entry_cnt <= 1'b0;
else if(entry_inv)
entry_cnt <= 1'b0;
else if(entry_wen[2] && entry_update_en)
entry_cnt <= entry_update_cnt;
else
entry_cnt <= entry_cnt;
end
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
entry_ras <= 1'b0;
else if(entry_inv)
entry_ras <= 1'b0;
else if(entry_wen[1] && entry_update_en)
entry_ras <= entry_update_ras;
else
entry_ras <= entry_ras;
end
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
entry_tag[14:0] <= 15'b0;
entry_way_pred[1:0] <= 2'b0;
entry_target[19:0] <= 20'b0;
end
else if(entry_inv)
begin
entry_tag[14:0] <= 15'b0;
entry_way_pred[1:0] <= 2'b0;
entry_target[19:0] <= 20'b0;
end
else if(entry_wen[0] && entry_update_en)
begin
entry_tag[14:0] <= entry_update_data[36:22];
entry_way_pred[1:0] <= entry_update_data[21:20];
entry_target[19:0] <= entry_update_data[19:0];
end
else
begin
entry_tag[14:0] <= entry_tag[14:0];
entry_way_pred[1:0] <= entry_way_pred[1:0];
entry_target[19:0] <= entry_target[19:0];
end
end
// &Force("output","entry_vld"); @111
// &Force("output","entry_cnt"); @112
// &Force("output","entry_ras"); @113
// &Force("output","entry_tag"); @114
// &Force("output","entry_way_pred"); @115
// &Force("output","entry_target"); @116
// &ModuleEnd; @118
endmodule |
module ct_ifu_btb(
addrgen_btb_index,
addrgen_btb_tag,
addrgen_btb_target_pc,
addrgen_btb_update_vld,
btb_ifctrl_inv_done,
btb_ifctrl_inv_on,
btb_ifdp_way0_pred,
btb_ifdp_way0_tag,
btb_ifdp_way0_target,
btb_ifdp_way0_vld,
btb_ifdp_way1_pred,
btb_ifdp_way1_tag,
btb_ifdp_way1_target,
btb_ifdp_way1_vld,
btb_ifdp_way2_pred,
btb_ifdp_way2_tag,
btb_ifdp_way2_target,
btb_ifdp_way2_vld,
btb_ifdp_way3_pred,
btb_ifdp_way3_tag,
btb_ifdp_way3_target,
btb_ifdp_way3_vld,
cp0_ifu_btb_en,
cp0_ifu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
ibdp_btb_miss,
ifctrl_btb_inv,
ipctrl_btb_chgflw_vld,
ipctrl_btb_way_pred,
ipctrl_btb_way_pred_error,
ipdp_btb_index_pc,
ipdp_btb_target_pc,
pad_yy_icg_scan_en,
pcgen_btb_chgflw,
pcgen_btb_chgflw_higher_than_addrgen,
pcgen_btb_chgflw_higher_than_if,
pcgen_btb_chgflw_higher_than_ip,
pcgen_btb_chgflw_short,
pcgen_btb_index,
pcgen_btb_stall,
pcgen_btb_stall_short
);
// &Ports; @23
input [9 :0] addrgen_btb_index;
input [9 :0] addrgen_btb_tag;
input [19:0] addrgen_btb_target_pc;
input addrgen_btb_update_vld;
input cp0_ifu_btb_en;
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input ibdp_btb_miss;
input ifctrl_btb_inv;
input ipctrl_btb_chgflw_vld;
input [1 :0] ipctrl_btb_way_pred;
input ipctrl_btb_way_pred_error;
input [38:0] ipdp_btb_index_pc;
input [19:0] ipdp_btb_target_pc;
input pad_yy_icg_scan_en;
input pcgen_btb_chgflw;
input pcgen_btb_chgflw_higher_than_addrgen;
input pcgen_btb_chgflw_higher_than_if;
input pcgen_btb_chgflw_higher_than_ip;
input pcgen_btb_chgflw_short;
input [9 :0] pcgen_btb_index;
input pcgen_btb_stall;
input pcgen_btb_stall_short;
output btb_ifctrl_inv_done;
output btb_ifctrl_inv_on;
output [1 :0] btb_ifdp_way0_pred;
output [9 :0] btb_ifdp_way0_tag;
output [19:0] btb_ifdp_way0_target;
output btb_ifdp_way0_vld;
output [1 :0] btb_ifdp_way1_pred;
output [9 :0] btb_ifdp_way1_tag;
output [19:0] btb_ifdp_way1_target;
output btb_ifdp_way1_vld;
output [1 :0] btb_ifdp_way2_pred;
output [9 :0] btb_ifdp_way2_tag;
output [19:0] btb_ifdp_way2_target;
output btb_ifdp_way2_vld;
output [1 :0] btb_ifdp_way3_pred;
output [9 :0] btb_ifdp_way3_tag;
output [19:0] btb_ifdp_way3_target;
output btb_ifdp_way3_vld;
// &Regs; @24
reg after_addrgen_btb_chgflw_first;
reg after_addrgen_btb_chgflw_second;
reg [87:0] btb_data_dout_reg;
reg [3 :0] btb_data_wen;
reg [9 :0] btb_index;
reg [9 :0] btb_index_flop;
reg [38:0] btb_index_pc_record;
reg btb_inv_on_reg;
reg [9 :0] btb_inval_cnt;
reg btb_rd_flop;
reg [43:0] btb_tag_dout_reg;
reg [3 :0] btb_tag_wen;
reg [19:0] btb_target_pc_record;
reg [9 :0] refill_buf_index;
reg [9 :0] refill_buf_tag;
reg [19:0] refill_buf_target_pc;
reg refill_buf_valid;
reg [1 :0] refill_buf_way_pred;
// &Wires; @25
wire [9 :0] addrgen_btb_index;
wire [9 :0] addrgen_btb_tag;
wire [19:0] addrgen_btb_target_pc;
wire addrgen_btb_update_vld;
wire [9 :0] btb_buf_tag_data;
wire [19:0] btb_buf_target_pc;
wire btb_buf_valid;
wire [1 :0] btb_buf_way_pred;
wire btb_data_cen_b;
wire btb_data_clk_en;
wire [43:0] btb_data_din;
wire [87:0] btb_data_dout;
wire btb_data_rd;
wire btb_dout_flop_clk;
wire btb_dout_flop_clk_en;
wire btb_ifctrl_inv_done;
wire btb_ifctrl_inv_on;
wire [1 :0] btb_ifdp_way0_pred;
wire [9 :0] btb_ifdp_way0_tag;
wire [19:0] btb_ifdp_way0_target;
wire btb_ifdp_way0_vld;
wire [1 :0] btb_ifdp_way1_pred;
wire [9 :0] btb_ifdp_way1_tag;
wire [19:0] btb_ifdp_way1_target;
wire btb_ifdp_way1_vld;
wire [1 :0] btb_ifdp_way2_pred;
wire [9 :0] btb_ifdp_way2_tag;
wire [19:0] btb_ifdp_way2_target;
wire btb_ifdp_way2_vld;
wire [1 :0] btb_ifdp_way3_pred;
wire [9 :0] btb_ifdp_way3_tag;
wire [19:0] btb_ifdp_way3_target;
wire btb_ifdp_way3_vld;
wire btb_inv_reg_upd_clk;
wire btb_inv_reg_upd_clk_en;
wire [9 :0] btb_mem_way0_tag_data;
wire [19:0] btb_mem_way0_target_pc;
wire btb_mem_way0_valid;
wire [1 :0] btb_mem_way0_way_pred;
wire [9 :0] btb_mem_way1_tag_data;
wire [19:0] btb_mem_way1_target_pc;
wire btb_mem_way1_valid;
wire [1 :0] btb_mem_way1_way_pred;
wire [9 :0] btb_mem_way2_tag_data;
wire [19:0] btb_mem_way2_target_pc;
wire btb_mem_way2_valid;
wire [1 :0] btb_mem_way2_way_pred;
wire [9 :0] btb_mem_way3_tag_data;
wire [19:0] btb_mem_way3_target_pc;
wire btb_mem_way3_valid;
wire [1 :0] btb_mem_way3_way_pred;
wire btb_miss_way_pred_rd;
wire btb_tag_cen_b;
wire btb_tag_clk_en;
wire [21:0] btb_tag_din;
wire [43:0] btb_tag_dout;
wire btb_tag_rd;
wire btb_tag_rd_gateclk_en;
wire chgflw_higher_than_addrgen;
wire chgflw_higher_than_if;
wire chgflw_higher_than_ip;
wire cp0_ifu_btb_en;
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire forever_cpuclk;
wire ibdp_btb_miss;
wire ifctrl_btb_inv;
wire index_pc_record_clk;
wire index_pc_record_clk_en;
wire ip_way_mispred;
wire ipctrl_btb_chgflw_vld;
wire [1 :0] ipctrl_btb_way_pred;
wire ipctrl_btb_way_pred_error;
wire [38:0] ipdp_btb_index_pc;
wire [19:0] ipdp_btb_target_pc;
wire pad_yy_icg_scan_en;
wire pcgen_btb_chgflw;
wire pcgen_btb_chgflw_higher_than_addrgen;
wire pcgen_btb_chgflw_higher_than_if;
wire pcgen_btb_chgflw_higher_than_ip;
wire pcgen_btb_chgflw_short;
wire [9 :0] pcgen_btb_index;
wire pcgen_btb_stall;
wire pcgen_btb_stall_short;
wire pcgen_stall;
wire refill_buf_updt_clk;
wire refill_buf_updt_clk_en;
wire refill_buf_updt_vld;
wire [3 :0] refill_buf_wen;
wire tag_vld_din;
// &Force("bus","addrgen_btb_tag",9,0); @27
parameter PC_WIDTH = 40;
//==========================================================
// BTB Tag Array
//==========================================================
//|--------|-----------|--------|-----------|
//| Valid1 | Tag1[9:0] | Valid0 | Tag0[9:0] |
//|--------|-----------|--------|-----------|
//
//Tag[9:0] = {vpc[19:13],vpc[2:0]};
//==========================================================
// Chip Enable to BTB Tag array
//==========================================================
//BTB tag array is enable when:
//1.write enable
// a.BTB is on inv
// b.BTB updated by refill buffer && cp0_btb_en
//2.read enable
// a.Change flow except ip_way_pred_reissue && cp0_btb_en
// note:way_pred_reissue & ibdp_btb_miss
// need not to read btb again and
// use this cycle update refill buffer to btb
// b.Sequence Read && !pc_stall && cp0_btb_en
//INV > Write enable > Read enable
assign btb_tag_cen_b = !btb_inv_on_reg &&
!(cp0_ifu_btb_en && refill_buf_updt_vld) &&
!btb_tag_rd;
assign btb_tag_rd = cp0_ifu_btb_en &&
(
(pcgen_btb_chgflw &&
!ipctrl_btb_way_pred_error &&
!ibdp_btb_miss) ||
(!pcgen_btb_chgflw &&
!pcgen_btb_stall)
);
assign btb_tag_rd_gateclk_en = cp0_ifu_btb_en &&
(pcgen_btb_chgflw_short ||
!pcgen_btb_stall_short);
//Gate Clk for Memory
assign btb_tag_clk_en = btb_inv_on_reg ||
cp0_ifu_btb_en &&
(
pcgen_btb_chgflw_short ||
!pcgen_btb_stall_short ||
ibdp_btb_miss
);
//==========================================================
// Write Enable to BTB Tag array
//==========================================================
//1.BTB is on INV
// wen[1:0] = 2'b00, 2 way write
//2.BTB update by refill buffer
// wen[1:0] = refill buffer wen[1:0]
// = {!(pc[3]^pc[2]), pc[3]^pc[2]}
// &CombBeg; @82
always @( btb_inv_on_reg
or refill_buf_wen[3:0]
or cp0_ifu_btb_en
or refill_buf_updt_vld)
begin
if(btb_inv_on_reg)
btb_tag_wen[3:0] = 4'b00;
else if(cp0_ifu_btb_en && refill_buf_updt_vld)
btb_tag_wen[3:0] = refill_buf_wen[3:0];
else
btb_tag_wen[3:0] = 4'b1111;
// &CombEnd; @89
end
assign refill_buf_wen[3:0] = {~(refill_buf_tag[2:1]== 2'b11),
~(refill_buf_tag[2:1]== 2'b10),
~(refill_buf_tag[2:1]== 2'b01),
~(refill_buf_tag[2:1]== 2'b00)};
//==========================================================
// Write Data to BTB Tag array
//==========================================================
//1.BTB is on INV
// valid = 0; tag = 0;
//2.BTB update by refill buffer
// valid = 1; tag = refill_buffer_tag
assign tag_vld_din = refill_buf_updt_vld ? 1'b1 : 1'b0;
//BTB_1024 tag should be the value of right shifting one bit of BTB_2048
assign btb_tag_din[21:0] = {tag_vld_din, refill_buf_tag[9:0],
tag_vld_din, refill_buf_tag[9:0]};
//==========================================================
// BTB Data Array
//==========================================================
//|-----------|------------|-----------|------------|
//| way1[1:0] | Tar1[19:0] | way0[1:0] | Tar0[19:0] |
//|-----------|------------|-----------|------------|
//==========================================================
// Chip Enable to BTB Data array
//==========================================================
//BTB Data array is enable when :
//1.write enable
// a.BTB updated by refill buffer && cp0_btb_en
//2.read enable
// a.Change flow except ip_way_pred_reissue && cp0_btb_en
// b.Sequence Read && !pc_stall && cp0_btb_en
assign btb_data_cen_b = !(cp0_ifu_btb_en && refill_buf_updt_vld) &&
!btb_data_rd;
assign btb_data_rd = cp0_ifu_btb_en &&
(
(pcgen_btb_chgflw &&
!ipctrl_btb_way_pred_error &&
!ibdp_btb_miss) ||
(!pcgen_btb_chgflw &&
!pcgen_btb_stall)
);
//Gate Clk for Memory
assign btb_data_clk_en = cp0_ifu_btb_en &&
(
ibdp_btb_miss ||
//ipctrl_btb_way_pred_error || //covered by chgflw
pcgen_btb_chgflw_short ||
!pcgen_btb_stall_short
);
//==========================================================
// Write Enable to BTB Data array
//==========================================================
//1.BTB update by refill buffer
// wen[1:0] = refill buffer wen[1:0]
// = {!(pc32[3]^pc[2]), pc32[3]^pc[2]}
// &CombBeg; @155
always @( refill_buf_wen[3:0]
or cp0_ifu_btb_en
or refill_buf_updt_vld)
begin
if(cp0_ifu_btb_en && refill_buf_updt_vld)
btb_data_wen[3:0] = refill_buf_wen[3:0];
else
btb_data_wen[3:0] = 4'b1111;
// &CombEnd; @160
end
//==========================================================
// Write Data to BTB Data array
//==========================================================
//BTB Only record the low 20 bits of target PC
assign btb_data_din[43:0] = {refill_buf_way_pred[1:0], refill_buf_target_pc[19:0],
refill_buf_way_pred[1:0], refill_buf_target_pc[19:0]};
//==========================================================
// Index to BTB
//==========================================================
//Index to BTB
//1.BTB on INV
// index = btb_inval_cnt
//2.Refill Buffer Update
// index = refill_buf_index
//3.other
// index = pcgen_pc
// &CombBeg; @179
always @( btb_inval_cnt[9:0]
or btb_inv_on_reg
or refill_buf_index[9:0]
or pcgen_btb_index[9:0]
or refill_buf_updt_vld)
begin
if(btb_inv_on_reg)
btb_index[9:0] = btb_inval_cnt[9:0];
else if(refill_buf_updt_vld)
btb_index[9:0] = refill_buf_index[9:0];
else
btb_index[9:0] = pcgen_btb_index[9:0];
// &CombEnd; @186
end
//==========================================================
// Index PC Record for way pred mistake update
//==========================================================
//when in IP stage, BTB change flow happens
//record ip_vpc to btb_index_pc_record[PC_WIDTH-2:0]
//when in IP stage, way predict mistake happens
//take btb_index_pc_record[30:0] as index pc,
//and write it to the refill buffer
//we also record target PC in the same way
// &Instance("gated_clk_cell","x_index_pc_record_clk"); @197
gated_clk_cell x_index_pc_record_clk (
.clk_in (forever_cpuclk ),
.clk_out (index_pc_record_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (index_pc_record_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @198
// .clk_out (index_pc_record_clk),//Out Clock @199
// .external_en (1'b0), @200
// .global_en (cp0_yy_clk_en), @201
// .local_en (index_pc_record_clk_en),//Local Condition @202
// .module_en (cp0_ifu_icg_en) @203
// ); @204
assign index_pc_record_clk_en = btb_inv_on_reg || ipctrl_btb_chgflw_vld;
always @(posedge index_pc_record_clk or negedge cpurst_b)
begin
if(!cpurst_b)
btb_index_pc_record[PC_WIDTH-2:0] <= {PC_WIDTH-1{1'b0}};
else if(btb_inv_on_reg)
btb_index_pc_record[PC_WIDTH-2:0] <= {PC_WIDTH-1{1'b0}};
else if(ipctrl_btb_chgflw_vld)
btb_index_pc_record[PC_WIDTH-2:0] <= ipdp_btb_index_pc[PC_WIDTH-2:0];//IP Stage VPC
else
btb_index_pc_record[PC_WIDTH-2:0] <= btb_index_pc_record[PC_WIDTH-2:0];
end
always @(posedge index_pc_record_clk or negedge cpurst_b)
begin
if(!cpurst_b)
btb_target_pc_record[19:0] <= 20'b0;
else if(btb_inv_on_reg)
btb_target_pc_record[19:0] <= 20'b0;
else if(ipctrl_btb_chgflw_vld)
btb_target_pc_record[19:0] <= ipdp_btb_target_pc[19:0];//IP Stage target PC
else
btb_target_pc_record[19:0] <= btb_target_pc_record[19:0];
end
//==========================================================
// Tag Array Data Output
//==========================================================
//In case of writing change the output data of memory dout
//Every time read data out(rd flop valid), restore data to reg
//------------------Read Flop Signal------------------------
always @(posedge btb_dout_flop_clk or negedge cpurst_b)
begin
if(!cpurst_b)
btb_rd_flop <= 1'b0;
else if(btb_inv_on_reg)
btb_rd_flop <= 1'b0;
else if(btb_tag_rd)
btb_rd_flop <= 1'b1;
else
btb_rd_flop <= 1'b0;
end
//---------------------Gate Clock---------------------------
// &Instance("gated_clk_cell","x_btb_dout_flop_clk"); @251
gated_clk_cell x_btb_dout_flop_clk (
.clk_in (forever_cpuclk ),
.clk_out (btb_dout_flop_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (btb_dout_flop_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @252
// .clk_out (btb_dout_flop_clk),//Out Clock @253
// .external_en (1'b0), @254
// .global_en (cp0_yy_clk_en), @255
// .local_en (btb_dout_flop_clk_en),//Local Condition @256
// .module_en (cp0_ifu_icg_en) @257
// ); @258
assign btb_dout_flop_clk_en = btb_inv_on_reg ||
btb_rd_flop ||
btb_tag_rd_gateclk_en;
//--------------------Dout restore reg----------------------
//When ip_way_mispred, cancel the update of btb_tag_dout_reg
//Maintain the Value of btb_tag_dout_reg as the result of
//Reissue BTB Read
always @(posedge btb_dout_flop_clk or negedge cpurst_b)
begin
if(!cpurst_b)
btb_tag_dout_reg[43:0] <= 44'b0;
else if(btb_inv_on_reg)
btb_tag_dout_reg[43:0] <= 44'b0;
else if(btb_rd_flop && !ip_way_mispred)
btb_tag_dout_reg[43:0] <= btb_tag_dout[43:0];
else
btb_tag_dout_reg[43:0] <= btb_tag_dout_reg[43:0];
end
//For timing consider
//Not logic and !chgflw_higher_than_ip;
assign ip_way_mispred = ipctrl_btb_way_pred_error;
always @(posedge btb_dout_flop_clk or negedge cpurst_b)
begin
if(!cpurst_b)
btb_data_dout_reg[87:0] <= 88'b0;
else if(btb_inv_on_reg)
btb_data_dout_reg[87:0] <= 88'b0;
else if(btb_rd_flop && !ip_way_mispred)
btb_data_dout_reg[87:0] <= btb_data_dout[87:0];
else
btb_data_dout_reg[87:0] <= btb_data_dout_reg[87:0];
end
//BTB Result
//Selected from memory dout & store reg
assign btb_mem_way3_valid = (btb_rd_flop && !ip_way_mispred)
? btb_tag_dout[43]
: btb_tag_dout_reg[43];
assign btb_mem_way2_valid = (btb_rd_flop && !ip_way_mispred)
? btb_tag_dout[32]
: btb_tag_dout_reg[32];
assign btb_mem_way1_valid = (btb_rd_flop && !ip_way_mispred)
? btb_tag_dout[21]
: btb_tag_dout_reg[21];
assign btb_mem_way0_valid = (btb_rd_flop && !ip_way_mispred)
? btb_tag_dout[10]
: btb_tag_dout_reg[10];
assign btb_mem_way3_tag_data[9:0] = (btb_rd_flop && !ip_way_mispred)
? btb_tag_dout[42:33]
: btb_tag_dout_reg[42:33];
assign btb_mem_way2_tag_data[9:0] = (btb_rd_flop && !ip_way_mispred)
? btb_tag_dout[31:22]
: btb_tag_dout_reg[31:22];
assign btb_mem_way1_tag_data[9:0] = (btb_rd_flop && !ip_way_mispred)
? btb_tag_dout[20:11]
: btb_tag_dout_reg[20:11];
assign btb_mem_way0_tag_data[9:0] = (btb_rd_flop && !ip_way_mispred)
? btb_tag_dout[9:0]
: btb_tag_dout_reg[9:0];
assign btb_mem_way3_way_pred[1:0] = (btb_rd_flop && !ip_way_mispred)
? btb_data_dout[87:86]
: btb_data_dout_reg[87:86];
assign btb_mem_way2_way_pred[1:0] = (btb_rd_flop && !ip_way_mispred)
? btb_data_dout[65:64]
: btb_data_dout_reg[65:64];
assign btb_mem_way1_way_pred[1:0] = (btb_rd_flop && !ip_way_mispred)
? btb_data_dout[43:42]
: btb_data_dout_reg[43:42];
assign btb_mem_way0_way_pred[1:0] = (btb_rd_flop && !ip_way_mispred)
? btb_data_dout[21:20]
: btb_data_dout_reg[21:20];
assign btb_mem_way3_target_pc[19:0] = (btb_rd_flop && !ip_way_mispred)
? btb_data_dout[85:66]
: btb_data_dout_reg[85:66];
assign btb_mem_way2_target_pc[19:0] = (btb_rd_flop && !ip_way_mispred)
? btb_data_dout[63:44]
: btb_data_dout_reg[63:44];
assign btb_mem_way1_target_pc[19:0] = (btb_rd_flop && !ip_way_mispred)
? btb_data_dout[41:22]
: btb_data_dout_reg[41:22];
assign btb_mem_way0_target_pc[19:0] = (btb_rd_flop && !ip_way_mispred)
? btb_data_dout[19:0]
: btb_data_dout_reg[19:0];
always @(posedge forever_cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
btb_index_flop[9:0] <= 10'b0;
else
btb_index_flop[9:0] <= btb_index[9:0];
end
assign btb_buf_valid = (btb_index_flop[9:0] == refill_buf_index[9:0]) && refill_buf_updt_vld;
assign btb_buf_tag_data[9:0] = refill_buf_tag[9:0];
assign btb_buf_way_pred[1:0] = refill_buf_way_pred[1:0];
assign btb_buf_target_pc[19:0] = refill_buf_target_pc[19:0];
//BTB data to ifdp
//Select Result from memory dout or BTB Refill Buffer
assign btb_ifdp_way0_target[19:0] = (btb_mem_way0_valid)
? btb_mem_way0_target_pc[19:0]
: btb_buf_target_pc[19:0];
assign btb_ifdp_way0_pred[1:0] = (btb_mem_way0_valid)
? btb_mem_way0_way_pred[1:0]
: btb_buf_way_pred[1:0];
assign btb_ifdp_way0_tag[9:0] = (btb_mem_way0_valid)
? btb_mem_way0_tag_data[9:0]
: btb_buf_tag_data[9:0];
assign btb_ifdp_way0_vld = (btb_mem_way0_valid || btb_buf_valid) &&
cp0_ifu_btb_en;
assign btb_ifdp_way1_target[19:0] = btb_mem_way1_target_pc[19:0];
assign btb_ifdp_way1_pred[1:0] = btb_mem_way1_way_pred[1:0];
assign btb_ifdp_way1_tag[9:0] = btb_mem_way1_tag_data[9:0];
assign btb_ifdp_way1_vld = btb_mem_way1_valid && cp0_ifu_btb_en;
assign btb_ifdp_way2_target[19:0] = btb_mem_way2_target_pc[19:0];
assign btb_ifdp_way2_pred[1:0] = btb_mem_way2_way_pred[1:0];
assign btb_ifdp_way2_tag[9:0] = btb_mem_way2_tag_data[9:0];
assign btb_ifdp_way2_vld = btb_mem_way2_valid && cp0_ifu_btb_en;
assign btb_ifdp_way3_target[19:0] = btb_mem_way3_target_pc[19:0];
assign btb_ifdp_way3_pred[1:0] = btb_mem_way3_way_pred[1:0];
assign btb_ifdp_way3_tag[9:0] = btb_mem_way3_tag_data[9:0];
assign btb_ifdp_way3_vld = btb_mem_way3_valid && cp0_ifu_btb_en;
//==========================================================
// INV of BTB
//==========================================================
// &Instance("gated_clk_cell","x_btb_inv_reg_upd_clk"); @389
gated_clk_cell x_btb_inv_reg_upd_clk (
.clk_in (forever_cpuclk ),
.clk_out (btb_inv_reg_upd_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (btb_inv_reg_upd_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @390
// .clk_out (btb_inv_reg_upd_clk),//Out Clock @391
// .external_en (1'b0), @392
// .global_en (cp0_yy_clk_en), @393
// .local_en (btb_inv_reg_upd_clk_en),//Local Condition @394
// .module_en (cp0_ifu_icg_en) @395
// ); @396
assign btb_inv_reg_upd_clk_en = btb_inv_on_reg || ifctrl_btb_inv;
//------------------The Index of Inv------------------------
parameter INV_CNT_VAL = 10'b0111111111;
always @(posedge btb_inv_reg_upd_clk or negedge cpurst_b)
begin
if(!cpurst_b)
btb_inval_cnt[9:0] <= 10'b0;
else if(btb_inv_on_reg)
btb_inval_cnt[9:0] <= btb_inval_cnt[9:0] - 10'b1;
else if(ifctrl_btb_inv)
//csky vperl_off
btb_inval_cnt[9:0] <= INV_CNT_VAL;
//csky vperl_on
else
btb_inval_cnt[9:0] <= btb_inval_cnt[9:0];
end
//-------------------Inv Status Reg-------------------------
always @(posedge btb_inv_reg_upd_clk or negedge cpurst_b)
begin
if(!cpurst_b)
btb_inv_on_reg <= 1'b0;
else if(!(|btb_inval_cnt[9:0]) && btb_inv_on_reg)
btb_inv_on_reg <= 1'b0;
else if(ifctrl_btb_inv)
btb_inv_on_reg <= 1'b1;
else
btb_inv_on_reg <= btb_inv_on_reg;
end
assign btb_ifctrl_inv_done = !btb_inv_on_reg;
assign btb_ifctrl_inv_on = btb_inv_on_reg;
//==========================================================
// BTB Refill Buffer
//==========================================================
//CK860 BTB has a refill buffer,
//which hold the info to be updated into BTB
//The reason why use refill buffer is that
//BTB hold icache way predict info,
//while pre info can not be get at the same time with target PC
//Thus we use refill buffer hold the update info
//for last BTB Miss or Way Mispredict
//And update it to BTB when BTB Miss or Way Mispredict next time
//Refill Hold Info as following:
// 1.index[9:0]
// 2.target_pc[19:0]
// 3.tag_pc[20:0]
// 4.way_pred[1:0]
// 5.refill_buf_vld
// &Instance("gated_clk_cell","x_refill_buf_updt_clk"); @453
gated_clk_cell x_refill_buf_updt_clk (
.clk_in (forever_cpuclk ),
.clk_out (refill_buf_updt_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (refill_buf_updt_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @454
// .clk_out (refill_buf_updt_clk),//Out Clock @455
// .external_en (1'b0), @456
// .global_en (cp0_yy_clk_en), @457
// .local_en (refill_buf_updt_clk_en),//Local Condition @458
// .module_en (cp0_ifu_icg_en) @459
// ); @460
assign refill_buf_updt_clk_en = btb_inv_on_reg ||
addrgen_btb_update_vld ||
ipctrl_btb_way_pred_error ||
ibdp_btb_miss ||
after_addrgen_btb_chgflw_first ||
after_addrgen_btb_chgflw_second;
//------------------refill buf index------------------------
always @(posedge refill_buf_updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
refill_buf_index[9:0] <= 10'b0;
else if(btb_inv_on_reg)
refill_buf_index[9:0] <= 10'b0;
else if(addrgen_btb_update_vld && !chgflw_higher_than_addrgen)
refill_buf_index[9:0] <= addrgen_btb_index[9:0];//IB next cycle VPC
else if(ipctrl_btb_way_pred_error && !chgflw_higher_than_ip)
refill_buf_index[9:0] <= btb_index_pc_record[12:3];
else
refill_buf_index[9:0] <= refill_buf_index[9:0];
end
//------------------refill buf target_pc--------------------
always @(posedge refill_buf_updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
refill_buf_target_pc[19:0] <= 20'b0;
else if(btb_inv_on_reg)
refill_buf_target_pc[19:0] <= 20'b0;
else if(addrgen_btb_update_vld && !chgflw_higher_than_addrgen)
refill_buf_target_pc[19:0] <= addrgen_btb_target_pc[19:0];
else if(ipctrl_btb_way_pred_error && !chgflw_higher_than_ip)
refill_buf_target_pc[19:0] <= btb_target_pc_record[19:0];
else
refill_buf_target_pc[19:0] <= refill_buf_target_pc[19:0];
end
//------------------refill buf tag_pc-----------------------
always @(posedge refill_buf_updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
refill_buf_tag[9:0] <= 10'b0;
else if(btb_inv_on_reg)
refill_buf_tag[9:0] <= 10'b0;
else if(addrgen_btb_update_vld && !chgflw_higher_than_addrgen)
refill_buf_tag[9:0] <= addrgen_btb_tag[9:0];
else if(ipctrl_btb_way_pred_error && !chgflw_higher_than_ip)
refill_buf_tag[9:0] <= {btb_index_pc_record[19:13],btb_index_pc_record[2:0]};
else
refill_buf_tag[9:0] <= refill_buf_tag[9:0];
end
//------------------refill buf way_pred---------------------
always @(posedge refill_buf_updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
refill_buf_way_pred[1:0] <= 2'b11;
else if(btb_inv_on_reg)
refill_buf_way_pred[1:0] <= 2'b11;
else if(btb_miss_way_pred_rd)//addrgen chgflw after 2 cycle
refill_buf_way_pred[1:0] <= ipctrl_btb_way_pred[1:0];
else if(ipctrl_btb_way_pred_error && !chgflw_higher_than_ip)
refill_buf_way_pred[1:0] <= ipctrl_btb_way_pred[1:0];//IP use fifo bit form way_pred
else
refill_buf_way_pred[1:0] <= refill_buf_way_pred[1:0];
end
//------------------refill buf valid------------------------
always @(posedge refill_buf_updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
refill_buf_valid <= 1'b0;
else if(btb_inv_on_reg)
refill_buf_valid <= 1'b0;
else if(btb_miss_way_pred_rd)//addrgen chgflw after 2 cycle
refill_buf_valid <= 1'b1;
else if(ipctrl_btb_way_pred_error && !chgflw_higher_than_ip)
refill_buf_valid <= 1'b1;
else if(ibdp_btb_miss && !chgflw_higher_than_ip ||
addrgen_btb_update_vld)
refill_buf_valid <= 1'b0;
else
refill_buf_valid <= refill_buf_valid;
end
assign refill_buf_updt_vld = (ibdp_btb_miss ||
ipctrl_btb_way_pred_error) &&
!chgflw_higher_than_ip &&
refill_buf_valid;
//when addrgen give BTB target PC
//2 cycle later will IP stage get icache way pred info
always @(posedge refill_buf_updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
after_addrgen_btb_chgflw_first <= 1'b0;
else if(btb_inv_on_reg)
after_addrgen_btb_chgflw_first <= 1'b0;
else if(addrgen_btb_update_vld && !chgflw_higher_than_addrgen)
after_addrgen_btb_chgflw_first <= 1'b1;
else
after_addrgen_btb_chgflw_first <= 1'b0;
end
always @(posedge refill_buf_updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
after_addrgen_btb_chgflw_second <= 1'b0;
else if(btb_inv_on_reg)
after_addrgen_btb_chgflw_second <= 1'b0;
else if(after_addrgen_btb_chgflw_first && !chgflw_higher_than_if && !pcgen_stall)
after_addrgen_btb_chgflw_second <= 1'b1;
else
after_addrgen_btb_chgflw_second <= 1'b0;
end
assign btb_miss_way_pred_rd = after_addrgen_btb_chgflw_second;
//-----------------pcgen trans signal-----------------------
assign chgflw_higher_than_ip = pcgen_btb_chgflw_higher_than_ip;
assign chgflw_higher_than_addrgen = pcgen_btb_chgflw_higher_than_addrgen;
assign chgflw_higher_than_if = pcgen_btb_chgflw_higher_than_if;
assign pcgen_stall = pcgen_btb_stall;
//==========================================================
// Interface with Memory
//==========================================================
// &Instance("ct_ifu_btb_tag_array", "x_ct_ifu_btb_tag_array"); @588
ct_ifu_btb_tag_array x_ct_ifu_btb_tag_array (
.btb_index (btb_index ),
.btb_tag_cen_b (btb_tag_cen_b ),
.btb_tag_clk_en (btb_tag_clk_en ),
.btb_tag_din (btb_tag_din ),
.btb_tag_dout (btb_tag_dout ),
.btb_tag_wen (btb_tag_wen ),
.cp0_ifu_icg_en (cp0_ifu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Instance("ct_ifu_btb_data_array", "x_ct_ifu_btb_data_array"); @589
ct_ifu_btb_data_array x_ct_ifu_btb_data_array (
.btb_data_cen_b (btb_data_cen_b ),
.btb_data_clk_en (btb_data_clk_en ),
.btb_data_din (btb_data_din ),
.btb_data_dout (btb_data_dout ),
.btb_data_wen (btb_data_wen ),
.btb_index (btb_index ),
.cp0_ifu_icg_en (cp0_ifu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &ModuleEnd; @591
endmodule |
module ct_ifu_btb_tag_array(
btb_index,
btb_tag_cen_b,
btb_tag_clk_en,
btb_tag_din,
btb_tag_dout,
btb_tag_wen,
cp0_ifu_icg_en,
cp0_yy_clk_en,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @23
input [9 :0] btb_index;
input btb_tag_cen_b;
input btb_tag_clk_en;
input [21:0] btb_tag_din;
input [3 :0] btb_tag_wen;
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output [43:0] btb_tag_dout;
// &Regs; @24
// &Wires; @25
wire [9 :0] btb_index;
wire [21:0] btb_tag_bwen_bank0;
wire [21:0] btb_tag_bwen_bank1;
wire btb_tag_cen_b;
wire btb_tag_clk;
wire btb_tag_clk_en;
wire [21:0] btb_tag_din;
wire [43:0] btb_tag_dout;
wire btb_tag_en;
wire btb_tag_gwen_bank0;
wire btb_tag_gwen_bank1;
wire [3 :0] btb_tag_wen;
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
//Gate Clk
// &Instance("gated_clk_cell", "x_btb_tag_clk"); @28
gated_clk_cell x_btb_tag_clk (
.clk_in (forever_cpuclk ),
.clk_out (btb_tag_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (btb_tag_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in(forever_cpuclk), @29
// .external_en(1'b0), @30
// .global_en(cp0_yy_clk_en), @31
// .module_en(cp0_ifu_icg_en), @32
// .local_en(btb_tag_en), @33
// .clk_out(btb_tag_clk) @34
// ); @35
assign btb_tag_en = btb_tag_clk_en;
//Instance Logic
// &Force("bus","btb_index",9,0); @40
//Support Bit Write
assign btb_tag_bwen_bank0[21:0] = {{11{btb_tag_wen[1]}}, {11{btb_tag_wen[0]}}};
assign btb_tag_bwen_bank1[21:0] = {{11{btb_tag_wen[3]}}, {11{btb_tag_wen[2]}}};
assign btb_tag_gwen_bank0 = btb_tag_wen[1] && btb_tag_wen[0];
assign btb_tag_gwen_bank1 = btb_tag_wen[3] && btb_tag_wen[2];
//Icache Size define
// &Instance("ct_spsram_1024x22", "x_ct_spsram_1024x22_bank0"); @50
// &Connect( @51
// .CLK (btb_tag_clk ), @52
// .Q (btb_tag_dout[21:0] ), @53
// .CEN (btb_tag_cen_b ), @54
// .WEN (btb_tag_bwen_bank0 ), @55
// .D (btb_tag_din ), @56
// .A (btb_index[9:0] ), @57
// .GWEN (btb_tag_gwen_bank0 ) @58
// ); @59
// &Instance("ct_spsram_1024x22", "x_ct_spsram_1024x22_bank1"); @61
// &Connect( @62
// .CLK (btb_tag_clk ), @63
// .Q (btb_tag_dout[43:22] ), @64
// .CEN (btb_tag_cen_b ), @65
// .WEN (btb_tag_bwen_bank1 ), @66
// .D (btb_tag_din ), @67
// .A (btb_index[9:0] ), @68
// .GWEN (btb_tag_gwen_bank1 ) @69
// ); @70
// &Instance("ct_spsram_512x22", "x_ct_spsram_512x22_bank0"); @75
ct_spsram_512x22 x_ct_spsram_512x22_bank0 (
.A (btb_index[8:0] ),
.CEN (btb_tag_cen_b ),
.CLK (btb_tag_clk ),
.D (btb_tag_din ),
.GWEN (btb_tag_gwen_bank0),
.Q (btb_tag_dout[21:0]),
.WEN (btb_tag_bwen_bank0)
);
// &Connect( @76
// .CLK (btb_tag_clk ), @77
// .Q (btb_tag_dout[21:0] ), @78
// .CEN (btb_tag_cen_b ), @79
// .WEN (btb_tag_bwen_bank0 ), @80
// .D (btb_tag_din ), @81
// .A (btb_index[8:0] ), @82
// .GWEN (btb_tag_gwen_bank0 ) @83
// ); @84
// &Instance("ct_spsram_512x22", "x_ct_spsram_512x22_bank1"); @86
ct_spsram_512x22 x_ct_spsram_512x22_bank1 (
.A (btb_index[8:0] ),
.CEN (btb_tag_cen_b ),
.CLK (btb_tag_clk ),
.D (btb_tag_din ),
.GWEN (btb_tag_gwen_bank1 ),
.Q (btb_tag_dout[43:22]),
.WEN (btb_tag_bwen_bank1 )
);
// &Connect( @87
// .CLK (btb_tag_clk ), @88
// .Q (btb_tag_dout[43:22] ), @89
// .CEN (btb_tag_cen_b ), @90
// .WEN (btb_tag_bwen_bank1 ), @91
// .D (btb_tag_din ), @92
// .A (btb_index[8:0] ), @93
// .GWEN (btb_tag_gwen_bank1 ) @94
// ); @95
// &ModuleEnd; @101
endmodule |
module ct_ifu_debug(
cpurst_b,
forever_cpuclk,
had_rtu_xx_jdbreq,
ibctrl_debug_buf_stall,
ibctrl_debug_bypass_inst_vld,
ibctrl_debug_fifo_full_stall,
ibctrl_debug_fifo_stall,
ibctrl_debug_ib_expt_vld,
ibctrl_debug_ib_ip_stall,
ibctrl_debug_ib_vld,
ibctrl_debug_ibuf_empty,
ibctrl_debug_ibuf_full,
ibctrl_debug_ibuf_inst_vld,
ibctrl_debug_ind_btb_stall,
ibctrl_debug_lbuf_inst_vld,
ibctrl_debug_mispred_stall,
ibdp_debug_inst0_vld,
ibdp_debug_inst1_vld,
ibdp_debug_inst2_vld,
ibdp_debug_mmu_deny_vld,
ifctrl_debug_if_pc_vld,
ifctrl_debug_if_stall,
ifctrl_debug_if_vld,
ifctrl_debug_inv_st,
ifctrl_debug_lsu_all_inv,
ifctrl_debug_lsu_line_inv,
ifctrl_debug_mmu_pavld,
ifctrl_debug_way_pred_stall,
ifdp_debug_acc_err_vld,
ifdp_debug_mmu_expt_vld,
ifu_had_debug_info,
ifu_had_reset_on,
ipb_debug_req_cur_st,
ipb_debug_wb_cur_st,
ipctrl_debug_bry_missigned_stall,
ipctrl_debug_h0_vld,
ipctrl_debug_ip_expt_vld,
ipctrl_debug_ip_if_stall,
ipctrl_debug_ip_vld,
ipctrl_debug_miss_under_refill_stall,
l0_btb_debug_cur_state,
l1_refill_debug_refill_st,
lbuf_debug_st,
pcgen_debug_chgflw,
pcgen_debug_pcbus,
rtu_ifu_xx_dbgon,
vector_debug_cur_st,
vector_debug_reset_on,
vfdsu_ifu_debug_ex2_wait,
vfdsu_ifu_debug_idle,
vfdsu_ifu_debug_pipe_busy
);
// &Ports; @23
input cpurst_b;
input forever_cpuclk;
input had_rtu_xx_jdbreq;
input ibctrl_debug_buf_stall;
input ibctrl_debug_bypass_inst_vld;
input ibctrl_debug_fifo_full_stall;
input ibctrl_debug_fifo_stall;
input ibctrl_debug_ib_expt_vld;
input ibctrl_debug_ib_ip_stall;
input ibctrl_debug_ib_vld;
input ibctrl_debug_ibuf_empty;
input ibctrl_debug_ibuf_full;
input ibctrl_debug_ibuf_inst_vld;
input ibctrl_debug_ind_btb_stall;
input ibctrl_debug_lbuf_inst_vld;
input ibctrl_debug_mispred_stall;
input ibdp_debug_inst0_vld;
input ibdp_debug_inst1_vld;
input ibdp_debug_inst2_vld;
input ibdp_debug_mmu_deny_vld;
input ifctrl_debug_if_pc_vld;
input ifctrl_debug_if_stall;
input ifctrl_debug_if_vld;
input [3 :0] ifctrl_debug_inv_st;
input ifctrl_debug_lsu_all_inv;
input ifctrl_debug_lsu_line_inv;
input ifctrl_debug_mmu_pavld;
input ifctrl_debug_way_pred_stall;
input ifdp_debug_acc_err_vld;
input ifdp_debug_mmu_expt_vld;
input [3 :0] ipb_debug_req_cur_st;
input [2 :0] ipb_debug_wb_cur_st;
input ipctrl_debug_bry_missigned_stall;
input ipctrl_debug_h0_vld;
input ipctrl_debug_ip_expt_vld;
input ipctrl_debug_ip_if_stall;
input ipctrl_debug_ip_vld;
input ipctrl_debug_miss_under_refill_stall;
input [1 :0] l0_btb_debug_cur_state;
input [3 :0] l1_refill_debug_refill_st;
input [5 :0] lbuf_debug_st;
input pcgen_debug_chgflw;
input [13:0] pcgen_debug_pcbus;
input rtu_ifu_xx_dbgon;
input [9 :0] vector_debug_cur_st;
input vector_debug_reset_on;
input vfdsu_ifu_debug_ex2_wait;
input vfdsu_ifu_debug_idle;
input vfdsu_ifu_debug_pipe_busy;
output [82:0] ifu_had_debug_info;
output ifu_had_reset_on;
// &Regs; @24
reg [82:0] ifu_had_debug_info;
// &Wires; @25
wire bry_missigned_stall;
wire buf_stall;
wire bypass_inst_vld;
wire chgflw;
wire cpurst_b;
wire dbg_ack_info;
wire fifo_full_stall;
wire fifo_stall;
wire forever_cpuclk;
wire [82:0] had_debug_info;
wire had_rtu_xx_jdbreq;
wire ib_expt_vld;
wire ib_ip_stall;
wire ib_mmu_deny_vld;
wire ib_vld;
wire ibctrl_debug_buf_stall;
wire ibctrl_debug_bypass_inst_vld;
wire ibctrl_debug_fifo_full_stall;
wire ibctrl_debug_fifo_stall;
wire ibctrl_debug_ib_expt_vld;
wire ibctrl_debug_ib_ip_stall;
wire ibctrl_debug_ib_vld;
wire ibctrl_debug_ibuf_empty;
wire ibctrl_debug_ibuf_full;
wire ibctrl_debug_ibuf_inst_vld;
wire ibctrl_debug_ind_btb_stall;
wire ibctrl_debug_lbuf_inst_vld;
wire ibctrl_debug_mispred_stall;
wire ibdp_debug_inst0_vld;
wire ibdp_debug_inst1_vld;
wire ibdp_debug_inst2_vld;
wire ibdp_debug_mmu_deny_vld;
wire ibuf_empty;
wire ibuf_full;
wire ibuf_inst_vld;
wire if_acc_err_vld;
wire if_mmu_expt_vld;
wire if_pc_vld;
wire if_self_stall;
wire if_vld;
wire ifctrl_debug_if_pc_vld;
wire ifctrl_debug_if_stall;
wire ifctrl_debug_if_vld;
wire [3 :0] ifctrl_debug_inv_st;
wire ifctrl_debug_lsu_all_inv;
wire ifctrl_debug_lsu_line_inv;
wire ifctrl_debug_mmu_pavld;
wire ifctrl_debug_way_pred_stall;
wire ifdp_debug_acc_err_vld;
wire ifdp_debug_mmu_expt_vld;
wire ifu_had_reset_on;
wire ind_btb_stall;
wire inst0_vld;
wire inst1_vld;
wire inst2_vld;
wire [3 :0] inv_cur_st;
wire ip_expt_vld;
wire ip_h0_vld;
wire ip_if_stall;
wire ip_vld;
wire [3 :0] ipb_debug_req_cur_st;
wire [2 :0] ipb_debug_wb_cur_st;
wire ipctrl_debug_bry_missigned_stall;
wire ipctrl_debug_h0_vld;
wire ipctrl_debug_ip_expt_vld;
wire ipctrl_debug_ip_if_stall;
wire ipctrl_debug_ip_vld;
wire ipctrl_debug_miss_under_refill_stall;
wire [1 :0] l0_btb_cur_state;
wire [1 :0] l0_btb_debug_cur_state;
wire [3 :0] l1_refill_debug_refill_st;
wire [5 :0] lbuf_cur_state;
wire [5 :0] lbuf_debug_st;
wire lbuf_inst_vld;
wire lsu_ifu_all_inv;
wire lsu_ifu_line_inv;
wire mispred_stall;
wire miss_under_refill_stall;
wire mmu_ifu_pa_vld;
wire [13:0] pc_bus;
wire pcgen_debug_chgflw;
wire [13:0] pcgen_debug_pcbus;
wire [3 :0] pref_req_cur_st;
wire [2 :0] pref_wb_cur_st;
wire [3 :0] refill_cur_state;
wire rtu_ifu_xx_dbgon;
wire [9 :0] vector_cur_st;
wire [9 :0] vector_debug_cur_st;
wire vector_debug_reset_on;
wire vfdsu_ex2_wait;
wire vfdsu_idle;
wire vfdsu_ifu_debug_ex2_wait;
wire vfdsu_ifu_debug_idle;
wire vfdsu_ifu_debug_pipe_busy;
wire vfdsu_pipe_busy;
wire way_pred_stall;
//83-69-pc_bus
assign pc_bus[13:0] = pcgen_debug_pcbus[13:0];
//68-ib_ip_stall
assign ib_ip_stall = ibctrl_debug_ib_ip_stall;
//67-ip_if_stall
assign ip_if_stall = ipctrl_debug_ip_if_stall;
//66-if_self_stall
assign if_self_stall = ifctrl_debug_if_stall;
//65-mispred_stall
assign mispred_stall = ibctrl_debug_mispred_stall;
//64-buf_stall
assign buf_stall = ibctrl_debug_buf_stall;
//63-fifo_stall
assign fifo_stall = ibctrl_debug_fifo_stall;
//62-fifo_full_stall
assign fifo_full_stall = ibctrl_debug_fifo_full_stall;
//61-ind_btb_stall
assign ind_btb_stall = ibctrl_debug_ind_btb_stall;
//60-bry_missigned_stall
assign bry_missigned_stall = ipctrl_debug_bry_missigned_stall;
//59-miss_under_refill_stall
assign miss_under_refill_stall = ipctrl_debug_miss_under_refill_stall;
//58-if_pc_vld
assign if_pc_vld = ifctrl_debug_if_pc_vld;
//57-way_pred_stall
assign way_pred_stall = ifctrl_debug_way_pred_stall;
//56-if_mmu_expt_vld
assign if_mmu_expt_vld = ifdp_debug_mmu_expt_vld;
//55-if_acc_err_vld
assign if_acc_err_vld = ifdp_debug_acc_err_vld;
//54-ib_mmu_deny_vld
assign ib_mmu_deny_vld = ibdp_debug_mmu_deny_vld;
//53-ip_expt_vld
assign ip_expt_vld = ipctrl_debug_ip_expt_vld;
//52-ib_expt_vld
assign ib_expt_vld = ibctrl_debug_ib_expt_vld;
//51-ibuf_full
assign ibuf_full = ibctrl_debug_ibuf_full;
//50-ibuf_empty
assign ibuf_empty = ibctrl_debug_ibuf_empty;
//49-ibuf_inst_vld
assign ibuf_inst_vld = ibctrl_debug_ibuf_inst_vld;
//48-lbuf_inst_vld
assign lbuf_inst_vld = ibctrl_debug_lbuf_inst_vld;
//47-bypass_inst_vld
assign bypass_inst_vld = ibctrl_debug_bypass_inst_vld;
//46-inst0_vld
assign inst0_vld = ibdp_debug_inst0_vld;
//45-inst1_vld
assign inst1_vld = ibdp_debug_inst1_vld;
//44-inst2_vld
assign inst2_vld = ibdp_debug_inst2_vld;
//43-if_vld
assign if_vld = ifctrl_debug_if_vld;
//42-ip_vld
assign ip_vld = ipctrl_debug_ip_vld;
//41-ib_vld
assign ib_vld = ibctrl_debug_ib_vld;
//40-ip_h0_vld
assign ip_h0_vld = ipctrl_debug_h0_vld;
//39-mmu_ifu_pa_vld
assign mmu_ifu_pa_vld = ifctrl_debug_mmu_pavld;
//38-lsu_ifu_all_inv
assign lsu_ifu_all_inv = ifctrl_debug_lsu_all_inv;
//37-lsu_ifu_line_inv
assign lsu_ifu_line_inv = ifctrl_debug_lsu_line_inv;
//36-chgflw
assign chgflw = pcgen_debug_chgflw;
//35-34-l0_btb_cur_state
assign l0_btb_cur_state[1:0] = l0_btb_debug_cur_state[1:0];
//33-28-lbuf_cur_state
assign lbuf_cur_state[5:0] = lbuf_debug_st[5:0];
//27-24-refill_cur_state
assign refill_cur_state[3:0] = l1_refill_debug_refill_st[3:0];
//23-20-pref_req_cur_st
assign pref_req_cur_st[3:0] = ipb_debug_req_cur_st[3:0];
//19-17-pref_wb_cur_st
assign pref_wb_cur_st[2:0] = ipb_debug_wb_cur_st[2:0];
//16-13-inv_cur_st
assign inv_cur_st[3:0] = ifctrl_debug_inv_st[3:0];
//12-3-vector_cur_st
assign vector_cur_st[9:0] = vector_debug_cur_st[9:0];
//2-vfdsu_pipe_busy
assign vfdsu_pipe_busy = vfdsu_ifu_debug_pipe_busy;
//1-vfdsu_ex2_wait
assign vfdsu_ex2_wait = vfdsu_ifu_debug_ex2_wait;
//0-vfdsu_idle
assign vfdsu_idle = vfdsu_ifu_debug_idle;
//Merge
assign had_debug_info[82:0] = {pc_bus[13:0],
ib_ip_stall,
ip_if_stall,
if_self_stall,
mispred_stall,
buf_stall,
fifo_stall,
fifo_full_stall,
ind_btb_stall,
bry_missigned_stall,
miss_under_refill_stall,
if_pc_vld,
way_pred_stall,
if_mmu_expt_vld,
if_acc_err_vld,
ib_mmu_deny_vld,
ip_expt_vld,
ib_expt_vld,
ibuf_full,
ibuf_empty,
ibuf_inst_vld,
lbuf_inst_vld,
bypass_inst_vld,
inst0_vld,
inst1_vld,
inst2_vld,
if_vld,
ip_vld,
ib_vld,
ip_h0_vld,
mmu_ifu_pa_vld,
lsu_ifu_all_inv,
lsu_ifu_line_inv,
chgflw,
l0_btb_cur_state[1:0],
lbuf_cur_state[5:0],
refill_cur_state[3:0],
pref_req_cur_st[3:0],
pref_wb_cur_st[2:0],
inv_cur_st[3:0],
vector_cur_st[9:0],
vfdsu_pipe_busy,
vfdsu_ex2_wait,
vfdsu_idle};
//flop data for timing
assign dbg_ack_info = had_rtu_xx_jdbreq
&& !rtu_ifu_xx_dbgon;
always @(posedge forever_cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
ifu_had_debug_info[82:0] <= 83'b0;
else if(dbg_ack_info)
ifu_had_debug_info[82:0] <= had_debug_info[82:0];
else
ifu_had_debug_info[82:0] <= ifu_had_debug_info[82:0];
end
// &Force("output","ifu_had_debug_info"); @181
assign ifu_had_reset_on = vector_debug_reset_on;
// &ModuleEnd; @184
endmodule |
module ct_ifu_lbuf_entry(
cp0_ifu_icg_en,
cp0_yy_clk_en,
cpurst_b,
entry_32_start_x,
entry_back_br_x,
entry_bkpta_x,
entry_bkptb_x,
entry_create_32_start_x,
entry_create_back_br_x,
entry_create_bkpta_x,
entry_create_bkptb_x,
entry_create_clk_en_x,
entry_create_fence_x,
entry_create_front_br_x,
entry_create_inst_data_v,
entry_create_split0_type_v,
entry_create_split1_type_v,
entry_create_vl_v,
entry_create_vlmul_v,
entry_create_vsetvli_x,
entry_create_vsew_v,
entry_create_x,
entry_fence_x,
entry_front_br_x,
entry_inst_data_v,
entry_split0_type_v,
entry_split1_type_v,
entry_vl_v,
entry_vld_x,
entry_vlmul_v,
entry_vsetvli_x,
entry_vsew_v,
fill_state_enter,
forever_cpuclk,
lbuf_flush,
pad_yy_icg_scan_en
);
// &Ports; @23
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input entry_create_32_start_x;
input entry_create_back_br_x;
input entry_create_bkpta_x;
input entry_create_bkptb_x;
input entry_create_clk_en_x;
input entry_create_fence_x;
input entry_create_front_br_x;
input [15:0] entry_create_inst_data_v;
input [2 :0] entry_create_split0_type_v;
input [2 :0] entry_create_split1_type_v;
input [7 :0] entry_create_vl_v;
input [1 :0] entry_create_vlmul_v;
input entry_create_vsetvli_x;
input [2 :0] entry_create_vsew_v;
input entry_create_x;
input fill_state_enter;
input forever_cpuclk;
input lbuf_flush;
input pad_yy_icg_scan_en;
output entry_32_start_x;
output entry_back_br_x;
output entry_bkpta_x;
output entry_bkptb_x;
output entry_fence_x;
output entry_front_br_x;
output [15:0] entry_inst_data_v;
output [2 :0] entry_split0_type_v;
output [2 :0] entry_split1_type_v;
output [7 :0] entry_vl_v;
output entry_vld_x;
output [1 :0] entry_vlmul_v;
output entry_vsetvli_x;
output [2 :0] entry_vsew_v;
// &Regs; @24
reg entry_32_start_x;
reg entry_back_br_x;
reg entry_bkpta_x;
reg entry_bkptb_x;
reg entry_fence_x;
reg entry_front_br_x;
reg [15:0] entry_inst_data_v;
reg [2 :0] entry_split0_type_v;
reg [2 :0] entry_split1_type_v;
reg [7 :0] entry_vl_v;
reg entry_vld_x;
reg [1 :0] entry_vlmul_v;
reg entry_vsetvli_x;
reg [2 :0] entry_vsew_v;
// &Wires; @25
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire entry_create_32_start_x;
wire entry_create_back_br_x;
wire entry_create_bkpta_x;
wire entry_create_bkptb_x;
wire entry_create_clk_en_x;
wire entry_create_fence_x;
wire entry_create_front_br_x;
wire [15:0] entry_create_inst_data_v;
wire [2 :0] entry_create_split0_type_v;
wire [2 :0] entry_create_split1_type_v;
wire [7 :0] entry_create_vl_v;
wire [1 :0] entry_create_vlmul_v;
wire entry_create_vsetvli_x;
wire [2 :0] entry_create_vsew_v;
wire entry_create_x;
wire fill_state_enter;
wire forever_cpuclk;
wire lbuf_entry_update_clk;
wire lbuf_entry_update_clk_en;
wire lbuf_flush;
wire lbuf_vld_update_clk;
wire lbuf_vld_update_clk_en;
wire pad_yy_icg_scan_en;
//==========================================================
//Loop Buffer Entry Fields Description:
//+-----+----------+---------+----------+------+--------+--------+-------+
//| vld | front_br | back_br | 32_start | inst | split1 | split0 | fence |
//+-----+----------+---------+----------+------+--------+--------+-------+
//==========================================================
//vld means entry valid
//inst[15:0] means the half word inst data
//front_br means the half is front branch 0
//back_br means the half is back branch 0
//32_start means this half is the start of inst
//split1 decode infor
//split0 decode infor
//fence decode infor
//==========================================================
// Entry Valid Signal
//==========================================================
// &Instance("gated_clk_cell","x_lbuf_vld_update_clk"); @46
gated_clk_cell x_lbuf_vld_update_clk (
.clk_in (forever_cpuclk ),
.clk_out (lbuf_vld_update_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lbuf_vld_update_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @47
// .clk_out (lbuf_vld_update_clk),//Out Clock @48
// .external_en (1'b0), @49
// .global_en (cp0_yy_clk_en), @50
// .local_en (lbuf_vld_update_clk_en),//Local Condition @51
// .module_en (cp0_ifu_icg_en) @52
// ); @53
assign lbuf_vld_update_clk_en = entry_create_clk_en_x ||
entry_vld_x;
always @(posedge lbuf_vld_update_clk or negedge cpurst_b)
begin
if(!cpurst_b)
entry_vld_x <= 1'b0;
else if(lbuf_flush)
entry_vld_x <= 1'b0;
else if(fill_state_enter)
entry_vld_x <= 1'b0;
else if(entry_create_x)
entry_vld_x <= 1'b1;
else
entry_vld_x <= entry_vld_x;
end
//==========================================================
// Entry Data Signal
//==========================================================
//----------------------Gate Clock--------------------------
// &Instance("gated_clk_cell","x_lbuf_entry_update_clk"); @74
gated_clk_cell x_lbuf_entry_update_clk (
.clk_in (forever_cpuclk ),
.clk_out (lbuf_entry_update_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lbuf_entry_update_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @75
// .clk_out (lbuf_entry_update_clk),//Out Clock @76
// .external_en (1'b0), @77
// .global_en (cp0_yy_clk_en), @78
// .local_en (lbuf_entry_update_clk_en),//Local Condition @79
// .module_en (cp0_ifu_icg_en) @80
// ); @81
assign lbuf_entry_update_clk_en = entry_create_clk_en_x;
//--------------------Register Update-----------------------
//_x _v for instance entry convinent
always @(posedge lbuf_entry_update_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
entry_inst_data_v[15:0] <= 16'b0;
entry_split0_type_v[2:0] <= 3'b0;
entry_split1_type_v[2:0] <= 3'b0;
entry_vlmul_v[1:0] <= 2'b0;
entry_vsew_v[2:0] <= 3'b0;
entry_vl_v[7:0] <= 8'b0;
entry_front_br_x <= 1'b0;
entry_back_br_x <= 1'b0;
entry_fence_x <= 1'b0;
entry_bkpta_x <= 1'b0;
entry_bkptb_x <= 1'b0;
entry_32_start_x <= 1'b0;
entry_vsetvli_x <= 1'b0;
end
else if(entry_create_x)
begin
entry_inst_data_v[15:0] <= entry_create_inst_data_v[15:0];
entry_split0_type_v[2:0] <= entry_create_split0_type_v[2:0];
entry_split1_type_v[2:0] <= entry_create_split1_type_v[2:0];
entry_vlmul_v[1:0] <= entry_create_vlmul_v[1:0];
entry_vsew_v[2:0] <= entry_create_vsew_v[2:0];
entry_vl_v[7:0] <= entry_create_vl_v[7:0];
entry_front_br_x <= entry_create_front_br_x;
entry_back_br_x <= entry_create_back_br_x;
entry_fence_x <= entry_create_fence_x;
entry_bkpta_x <= entry_create_bkpta_x;
entry_bkptb_x <= entry_create_bkptb_x;
entry_32_start_x <= entry_create_32_start_x;
entry_vsetvli_x <= entry_create_vsetvli_x;
end
else
begin
entry_inst_data_v[15:0] <= entry_inst_data_v[15:0];
entry_split0_type_v[2:0] <= entry_split0_type_v[2:0];
entry_split1_type_v[2:0] <= entry_split1_type_v[2:0];
entry_vlmul_v[1:0] <= entry_vlmul_v[1:0];
entry_vsew_v[2:0] <= entry_vsew_v[2:0];
entry_vl_v[7:0] <= entry_vl_v[7:0];
entry_front_br_x <= entry_front_br_x;
entry_back_br_x <= entry_back_br_x;
entry_fence_x <= entry_fence_x;
entry_bkpta_x <= entry_bkpta_x;
entry_bkptb_x <= entry_bkptb_x;
entry_32_start_x <= entry_32_start_x;
entry_vsetvli_x <= entry_vsetvli_x;
end
end
// &Force("output","entry_inst_data_v"); @155
// &Force("output","entry_split0_type_v"); @156
// &Force("output","entry_split1_type_v"); @157
// &Force("output","entry_vlmul_v"); @158
// &Force("output","entry_vsew_v"); @159
// &Force("output","entry_vl_v"); @160
// &Force("output","entry_front_br_x"); @161
// &Force("output","entry_back_br_x"); @162
// &Force("output","entry_fence_x"); @163
// &Force("output","entry_bkpta_x"); @164
// &Force("output","entry_bkptb_x"); @165
// &Force("output","entry_vsetvli_x"); @166
// &Force("output","entry_32_start_x"); @167
// &Force("output","entry_vld_x"); @168
// &ModuleEnd; @170
endmodule |
module ct_ifu_vector(
cp0_ifu_icg_en,
cp0_ifu_rst_inv_done,
cp0_ifu_rvbr,
cp0_ifu_vbr,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
ifu_cp0_rst_inv_req,
ifu_xx_sync_reset,
pad_yy_icg_scan_en,
rtu_ifu_xx_dbgon,
rtu_ifu_xx_expt_vec,
rtu_ifu_xx_expt_vld,
vector_debug_cur_st,
vector_debug_reset_on,
vector_ifctrl_reset_on,
vector_ifctrl_sm_on,
vector_ifctrl_sm_start,
vector_pcgen_pc,
vector_pcgen_pcload,
vector_pcgen_reset_on
);
// &Ports; @23
input cp0_ifu_icg_en;
input cp0_ifu_rst_inv_done;
input [39:0] cp0_ifu_rvbr;
input [39:0] cp0_ifu_vbr;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input rtu_ifu_xx_dbgon;
input [5 :0] rtu_ifu_xx_expt_vec;
input rtu_ifu_xx_expt_vld;
output ifu_cp0_rst_inv_req;
output ifu_xx_sync_reset;
output [9 :0] vector_debug_cur_st;
output vector_debug_reset_on;
output vector_ifctrl_reset_on;
output vector_ifctrl_sm_on;
output vector_ifctrl_sm_start;
output [38:0] vector_pcgen_pc;
output vector_pcgen_pcload;
output vector_pcgen_reset_on;
// &Regs; @24
reg [38:0] nonvec_pc;
reg [9 :0] vec_cur_state;
reg [9 :0] vec_next_state;
reg vector_rst_inv_ff;
// &Wires; @25
wire cp0_ifu_icg_en;
wire cp0_ifu_rst_inv_done;
wire [39:0] cp0_ifu_rvbr;
wire [39:0] cp0_ifu_vbr;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [1 :0] expt_mode;
wire [38:0] expt_virtual_pc;
wire forever_cpuclk;
wire ifu_cp0_rst_inv_req;
wire ifu_xx_sync_reset;
wire int_vld;
wire pad_yy_icg_scan_en;
wire pc_load;
wire reset_expt;
wire [38:0] reset_virtual_pc;
wire rtu_ifu_xx_dbgon;
wire [5 :0] rtu_ifu_xx_expt_vec;
wire rtu_ifu_xx_expt_vld;
wire vec_sm_clk;
wire vec_sm_clk_en;
wire [9 :0] vector_debug_cur_st;
wire vector_debug_reset_on;
wire vector_ifctrl_reset_on;
wire vector_ifctrl_sm_on;
wire vector_ifctrl_sm_start;
wire vector_pc_update_clk;
wire vector_pc_update_clk_en;
wire [38:0] vector_pcgen_pc;
wire vector_pcgen_pcload;
wire vector_pcgen_reset_on;
wire vector_reset_on;
wire vector_sm_on;
wire [38:0] virtual_pc;
parameter PC_WIDTH = 40;
// &Force("bus","cp0_ifu_rvbr",39,0); @28
//==========================================================
// Vector State Machine
//==========================================================
//-----------------parameter definition---------------------
parameter IDLE = 10'b0000000001;
//parameter PHYADD = 10'b0000000010;
//parameter WAIT1 = 10'b0000000100;
//parameter CACHE = 10'b0000001000;
//parameter CMP = 10'b0000010000;
//parameter WAIT2 = 10'b0000100000;
//parameter MISS = 10'b0001000000;
//parameter EXP = 10'b0010000000;
parameter RESET = 10'b0100000000;
parameter PCLOAD = 10'b1000000000;
//---------------------Gate Clock---------------------------
// &Instance("gated_clk_cell","x_vec_sm_clk"); @46
gated_clk_cell x_vec_sm_clk (
.clk_in (forever_cpuclk ),
.clk_out (vec_sm_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (vec_sm_clk_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @47
// .clk_out (vec_sm_clk),//Out Clock @48
// .external_en (1'b0), @49
// .global_en (cp0_yy_clk_en), @50
// .local_en (vec_sm_clk_en),//Local Condition @51
// .module_en (cp0_ifu_icg_en) @52
// ); @53
assign vec_sm_clk_en = rtu_ifu_xx_expt_vld ||
(vec_cur_state[9:0] != IDLE);
//---------------------FSM of Vector------------------------
//State Description:
//IDLE : Wait for rtu expt signal & send physical address req
//RESET : One cycle to form reset logic
//PHYADD : Wait for mmu information ready
//WAIT1 : Wait Refill not on and send read req
// support hit under miss
//CACHE : The cycle after icache read
//CMP : compare and judge if cache hit request
//WAIT2 : wait Refill on IDLE state and send vec miss refill req out
// WAIT1 refill not on do not means on IDLE state
//MISS : icache miss and wait data from refill
//EXP : Deal with expt occur on vec sm on
//PCLOAD : Deal with non-vec expt
//!cpurst_b should be treated as expt
//when !cpurst_b , vec_cur_state turn to PHYADD
always @(posedge vec_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vec_cur_state[9:0] <= RESET;
else if(rtu_ifu_xx_dbgon)
vec_cur_state[9:0] <= IDLE;
else
vec_cur_state[9:0] <= vec_next_state[9:0];
end
// &CombBeg; @84
always @( vec_cur_state[9:0]
or cp0_ifu_rst_inv_done
or rtu_ifu_xx_expt_vld)
begin
case(vec_cur_state[9:0])
IDLE : if(rtu_ifu_xx_expt_vld)
vec_next_state[9:0] = PCLOAD;
else
vec_next_state[9:0] = IDLE;
RESET : if(cp0_ifu_rst_inv_done)
vec_next_state[9:0] = IDLE;
else
vec_next_state[9:0] = RESET;
PCLOAD : vec_next_state[9:0] = IDLE;
default : vec_next_state[9:0] = IDLE;
endcase
// &CombEnd; @97
end
//-------------------Control Signal-------------------------
always @(posedge vec_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
vector_rst_inv_ff <= 1'b0;
end
else begin
vector_rst_inv_ff <= vec_cur_state[8];
end
end
assign ifu_xx_sync_reset = vec_cur_state[8];
assign ifu_cp0_rst_inv_req = vec_cur_state[8] && !vector_rst_inv_ff;
assign vector_reset_on = vec_cur_state[8];
assign vector_sm_on = !(vec_cur_state[0]); //IDLE
assign pc_load = (!rtu_ifu_xx_dbgon) &&
(
(vec_cur_state[8]) && //RESET
cp0_ifu_rst_inv_done ||
(vec_cur_state[9]) //PCLOAD
);
//==========================================================
// Virtual PC
//==========================================================
//supprt multi_core different rst vbr
//rvbr is 20 bit and the following 2 bit of it must be 2'b00
// &Force("bus","cp0_ifu_vbr",39,0); @126
assign reset_expt = (rtu_ifu_xx_expt_vec[4:0] == 5'b0);
assign expt_mode[1:0] = cp0_ifu_vbr[1:0];
assign int_vld = rtu_ifu_xx_expt_vec[5];
assign expt_virtual_pc[PC_WIDTH-2:0] = (expt_mode[0] && int_vld)
? ( {cp0_ifu_vbr[PC_WIDTH-1:2],1'b0}
+ {33'b0,rtu_ifu_xx_expt_vec[4:0],1'b0})
: {cp0_ifu_vbr[PC_WIDTH-1:2],1'b0};
assign reset_virtual_pc[PC_WIDTH-2:0] = cp0_ifu_rvbr[PC_WIDTH-1:1];
assign virtual_pc[PC_WIDTH-2:0] = (reset_expt)
? reset_virtual_pc[PC_WIDTH-2:0]
: expt_virtual_pc[PC_WIDTH-2:0];
always @(posedge vector_pc_update_clk or negedge cpurst_b)
begin
if(!cpurst_b)
nonvec_pc[PC_WIDTH-2:0] <= {PC_WIDTH-1{1'b0}};
else if(rtu_ifu_xx_expt_vld || reset_expt)
nonvec_pc[PC_WIDTH-2:0] <= virtual_pc[PC_WIDTH-2:0];
else
nonvec_pc[PC_WIDTH-2:0] <= nonvec_pc[PC_WIDTH-2:0];
end
//Gate Clk
// &Instance("gated_clk_cell","x_vector_pc_update_clk"); @151
gated_clk_cell x_vector_pc_update_clk (
.clk_in (forever_cpuclk ),
.clk_out (vector_pc_update_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (vector_pc_update_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @152
// .clk_out (vector_pc_update_clk),//Out Clock @153
// .external_en (1'b0), @154
// .global_en (cp0_yy_clk_en), @155
// .local_en (vector_pc_update_clk_en),//Local Condition @156
// .module_en (cp0_ifu_icg_en) @157
// ); @158
assign vector_pc_update_clk_en = rtu_ifu_xx_expt_vld
|| reset_expt && vec_cur_state[8];
//==========================================================
// Interface to PC Generator
//==========================================================
assign vector_pcgen_pcload = pc_load;
assign vector_pcgen_reset_on = vector_reset_on;
assign vector_pcgen_pc[PC_WIDTH-2:0] = nonvec_pc[PC_WIDTH-2:0];
//==========================================================
// Interface to ifctrl
//==========================================================
assign vector_ifctrl_sm_on = vector_sm_on;
assign vector_ifctrl_reset_on = vector_reset_on;
//when vector is on RESET mode,we can not stop icache inv operation,
//or it will cause deadlock for vector state is waiting invalid complete
//but vector state stop icache invalid operation
assign vector_ifctrl_sm_start = vector_sm_on && !vec_cur_state[8] ||
rtu_ifu_xx_expt_vld;
//Debug Infor
assign vector_debug_cur_st[9:0] = vec_cur_state[9:0];
assign vector_debug_reset_on = vector_reset_on;
// &ModuleEnd; @185
endmodule |
module ct_ifu_ibctrl(
addrgen_ibctrl_cancel,
cp0_ifu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
ibctrl_debug_buf_stall,
ibctrl_debug_bypass_inst_vld,
ibctrl_debug_fifo_full_stall,
ibctrl_debug_fifo_stall,
ibctrl_debug_ib_expt_vld,
ibctrl_debug_ib_ip_stall,
ibctrl_debug_ib_vld,
ibctrl_debug_ibuf_empty,
ibctrl_debug_ibuf_full,
ibctrl_debug_ibuf_inst_vld,
ibctrl_debug_ind_btb_stall,
ibctrl_debug_lbuf_inst_vld,
ibctrl_debug_mispred_stall,
ibctrl_ibdp_buf_stall,
ibctrl_ibdp_bypass_inst_vld,
ibctrl_ibdp_cancel,
ibctrl_ibdp_chgflw,
ibctrl_ibdp_fifo_full_stall,
ibctrl_ibdp_fifo_stall,
ibctrl_ibdp_ibuf_inst_vld,
ibctrl_ibdp_if_chgflw_vld,
ibctrl_ibdp_ind_btb_rd_stall,
ibctrl_ibdp_ip_chgflw_vld,
ibctrl_ibdp_l0_btb_hit,
ibctrl_ibdp_l0_btb_mispred,
ibctrl_ibdp_l0_btb_miss,
ibctrl_ibdp_l0_btb_wait,
ibctrl_ibdp_lbuf_inst_vld,
ibctrl_ibdp_mispred_stall,
ibctrl_ibdp_self_stall,
ibctrl_ibuf_bypass_not_select,
ibctrl_ibuf_create_vld,
ibctrl_ibuf_data_vld,
ibctrl_ibuf_flush,
ibctrl_ibuf_merge_vld,
ibctrl_ibuf_retire_vld,
ibctrl_ind_btb_check_vld,
ibctrl_ind_btb_fifo_stall,
ibctrl_ind_btb_path,
ibctrl_ipctrl_low_power_stall,
ibctrl_ipctrl_stall,
ibctrl_ipdp_chgflw_vl,
ibctrl_ipdp_chgflw_vlmul,
ibctrl_ipdp_chgflw_vsew,
ibctrl_ipdp_pcload,
ibctrl_lbuf_bju_mispred,
ibctrl_lbuf_create_vld,
ibctrl_lbuf_flush,
ibctrl_lbuf_retire_vld,
ibctrl_pcfifo_if_create_vld,
ibctrl_pcfifo_if_ind_btb_miss,
ibctrl_pcfifo_if_ind_target_pc,
ibctrl_pcfifo_if_ras_target_pc,
ibctrl_pcfifo_if_ras_vld,
ibctrl_pcgen_ip_stall,
ibctrl_pcgen_pc,
ibctrl_pcgen_pcload,
ibctrl_pcgen_pcload_vld,
ibctrl_pcgen_way_pred,
ibctrl_ras_inst_pcall,
ibctrl_ras_pcall_vld,
ibctrl_ras_pcall_vld_for_gateclk,
ibctrl_ras_preturn_vld,
ibctrl_ras_preturn_vld_for_gateclk,
ibdp_ibctrl_chgflw_vl,
ibdp_ibctrl_chgflw_vlmul,
ibdp_ibctrl_chgflw_vsew,
ibdp_ibctrl_default_pc,
ibdp_ibctrl_hn_ind_br,
ibdp_ibctrl_hn_pcall,
ibdp_ibctrl_hn_preturn,
ibdp_ibctrl_l0_btb_mispred_pc,
ibdp_ibctrl_ras_chgflw_mask,
ibdp_ibctrl_ras_mistaken,
ibdp_ibctrl_ras_pc,
ibdp_ibctrl_vpc,
ibuf_ibctrl_empty,
ibuf_ibctrl_stall,
idu_ifu_id_bypass_stall,
idu_ifu_id_stall,
ifu_idu_ib_pipedown_gateclk,
ind_btb_ibctrl_dout,
ind_btb_ibctrl_priv_mode,
ipctrl_ibctrl_expt_vld,
ipctrl_ibctrl_if_chgflw_vld,
ipctrl_ibctrl_ip_chgflw_vld,
ipctrl_ibctrl_l0_btb_hit,
ipctrl_ibctrl_l0_btb_mispred,
ipctrl_ibctrl_l0_btb_miss,
ipctrl_ibctrl_l0_btb_st_wait,
ipctrl_ibctrl_vld,
ipdp_ibdp_vl_reg,
ipdp_ibdp_vlmul_reg,
ipdp_ibdp_vsew_reg,
iu_ifu_chgflw_vld,
iu_ifu_mispred_stall,
iu_ifu_pcfifo_full,
lbuf_ibctrl_active_idle_flush,
lbuf_ibctrl_chgflw_pc,
lbuf_ibctrl_chgflw_pred,
lbuf_ibctrl_chgflw_vl,
lbuf_ibctrl_chgflw_vld,
lbuf_ibctrl_chgflw_vlmul,
lbuf_ibctrl_chgflw_vsew,
lbuf_ibctrl_lbuf_active,
lbuf_ibctrl_stall,
pad_yy_icg_scan_en,
pcfifo_if_ibctrl_more_than_two,
pcgen_ibctrl_bju_chgflw,
pcgen_ibctrl_cancel,
pcgen_ibctrl_ibuf_flush,
pcgen_ibctrl_lbuf_flush
);
// &Ports; @23
input addrgen_ibctrl_cancel;
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input [7 :0] ibdp_ibctrl_chgflw_vl;
input [1 :0] ibdp_ibctrl_chgflw_vlmul;
input [2 :0] ibdp_ibctrl_chgflw_vsew;
input [38:0] ibdp_ibctrl_default_pc;
input [7 :0] ibdp_ibctrl_hn_ind_br;
input [7 :0] ibdp_ibctrl_hn_pcall;
input [7 :0] ibdp_ibctrl_hn_preturn;
input [38:0] ibdp_ibctrl_l0_btb_mispred_pc;
input ibdp_ibctrl_ras_chgflw_mask;
input ibdp_ibctrl_ras_mistaken;
input [38:0] ibdp_ibctrl_ras_pc;
input [38:0] ibdp_ibctrl_vpc;
input ibuf_ibctrl_empty;
input ibuf_ibctrl_stall;
input idu_ifu_id_bypass_stall;
input idu_ifu_id_stall;
input [22:0] ind_btb_ibctrl_dout;
input [1 :0] ind_btb_ibctrl_priv_mode;
input ipctrl_ibctrl_expt_vld;
input ipctrl_ibctrl_if_chgflw_vld;
input ipctrl_ibctrl_ip_chgflw_vld;
input ipctrl_ibctrl_l0_btb_hit;
input ipctrl_ibctrl_l0_btb_mispred;
input ipctrl_ibctrl_l0_btb_miss;
input ipctrl_ibctrl_l0_btb_st_wait;
input ipctrl_ibctrl_vld;
input [7 :0] ipdp_ibdp_vl_reg;
input [1 :0] ipdp_ibdp_vlmul_reg;
input [2 :0] ipdp_ibdp_vsew_reg;
input iu_ifu_chgflw_vld;
input iu_ifu_mispred_stall;
input iu_ifu_pcfifo_full;
input lbuf_ibctrl_active_idle_flush;
input [38:0] lbuf_ibctrl_chgflw_pc;
input [1 :0] lbuf_ibctrl_chgflw_pred;
input [7 :0] lbuf_ibctrl_chgflw_vl;
input lbuf_ibctrl_chgflw_vld;
input [1 :0] lbuf_ibctrl_chgflw_vlmul;
input [2 :0] lbuf_ibctrl_chgflw_vsew;
input lbuf_ibctrl_lbuf_active;
input lbuf_ibctrl_stall;
input pad_yy_icg_scan_en;
input pcfifo_if_ibctrl_more_than_two;
input pcgen_ibctrl_bju_chgflw;
input pcgen_ibctrl_cancel;
input pcgen_ibctrl_ibuf_flush;
input pcgen_ibctrl_lbuf_flush;
output ibctrl_debug_buf_stall;
output ibctrl_debug_bypass_inst_vld;
output ibctrl_debug_fifo_full_stall;
output ibctrl_debug_fifo_stall;
output ibctrl_debug_ib_expt_vld;
output ibctrl_debug_ib_ip_stall;
output ibctrl_debug_ib_vld;
output ibctrl_debug_ibuf_empty;
output ibctrl_debug_ibuf_full;
output ibctrl_debug_ibuf_inst_vld;
output ibctrl_debug_ind_btb_stall;
output ibctrl_debug_lbuf_inst_vld;
output ibctrl_debug_mispred_stall;
output ibctrl_ibdp_buf_stall;
output ibctrl_ibdp_bypass_inst_vld;
output ibctrl_ibdp_cancel;
output ibctrl_ibdp_chgflw;
output ibctrl_ibdp_fifo_full_stall;
output ibctrl_ibdp_fifo_stall;
output ibctrl_ibdp_ibuf_inst_vld;
output ibctrl_ibdp_if_chgflw_vld;
output ibctrl_ibdp_ind_btb_rd_stall;
output ibctrl_ibdp_ip_chgflw_vld;
output ibctrl_ibdp_l0_btb_hit;
output ibctrl_ibdp_l0_btb_mispred;
output ibctrl_ibdp_l0_btb_miss;
output ibctrl_ibdp_l0_btb_wait;
output ibctrl_ibdp_lbuf_inst_vld;
output ibctrl_ibdp_mispred_stall;
output ibctrl_ibdp_self_stall;
output ibctrl_ibuf_bypass_not_select;
output ibctrl_ibuf_create_vld;
output ibctrl_ibuf_data_vld;
output ibctrl_ibuf_flush;
output ibctrl_ibuf_merge_vld;
output ibctrl_ibuf_retire_vld;
output ibctrl_ind_btb_check_vld;
output ibctrl_ind_btb_fifo_stall;
output [7 :0] ibctrl_ind_btb_path;
output ibctrl_ipctrl_low_power_stall;
output ibctrl_ipctrl_stall;
output [7 :0] ibctrl_ipdp_chgflw_vl;
output [1 :0] ibctrl_ipdp_chgflw_vlmul;
output [2 :0] ibctrl_ipdp_chgflw_vsew;
output ibctrl_ipdp_pcload;
output ibctrl_lbuf_bju_mispred;
output ibctrl_lbuf_create_vld;
output ibctrl_lbuf_flush;
output ibctrl_lbuf_retire_vld;
output ibctrl_pcfifo_if_create_vld;
output ibctrl_pcfifo_if_ind_btb_miss;
output [38:0] ibctrl_pcfifo_if_ind_target_pc;
output [38:0] ibctrl_pcfifo_if_ras_target_pc;
output ibctrl_pcfifo_if_ras_vld;
output ibctrl_pcgen_ip_stall;
output [38:0] ibctrl_pcgen_pc;
output ibctrl_pcgen_pcload;
output ibctrl_pcgen_pcload_vld;
output [1 :0] ibctrl_pcgen_way_pred;
output ibctrl_ras_inst_pcall;
output ibctrl_ras_pcall_vld;
output ibctrl_ras_pcall_vld_for_gateclk;
output ibctrl_ras_preturn_vld;
output ibctrl_ras_preturn_vld_for_gateclk;
output ifu_idu_ib_pipedown_gateclk;
// &Regs; @24
reg [38:0] chgflw_pc;
reg [7 :0] chgflw_vl;
reg [1 :0] chgflw_vlmul;
reg [2 :0] chgflw_vsew;
reg ind_btb_rd_state;
reg [1 :0] way_pred;
// &Wires; @25
wire addrgen_ibctrl_cancel;
wire buf_create_vld;
wire buf_stall;
wire bypass_inst_vld;
wire chgflw_vld;
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire fifo_create_vld;
wire fifo_full_stall;
wire fifo_stall;
wire forever_cpuclk;
wire [7 :0] hn_ind_br;
wire [7 :0] hn_mispred_stall;
wire [7 :0] hn_pcall;
wire [7 :0] hn_preturn;
wire ib_addr_cancel;
wire ib_cancel;
wire ib_chgflw_self_stall;
wire ib_data_vld;
wire ib_expt_low_power_stall;
wire ib_expt_vld;
wire [38:0] ib_vpc;
wire ibctrl_debug_buf_stall;
wire ibctrl_debug_bypass_inst_vld;
wire ibctrl_debug_fifo_full_stall;
wire ibctrl_debug_fifo_stall;
wire ibctrl_debug_ib_expt_vld;
wire ibctrl_debug_ib_ip_stall;
wire ibctrl_debug_ib_vld;
wire ibctrl_debug_ibuf_empty;
wire ibctrl_debug_ibuf_full;
wire ibctrl_debug_ibuf_inst_vld;
wire ibctrl_debug_ind_btb_stall;
wire ibctrl_debug_lbuf_inst_vld;
wire ibctrl_debug_mispred_stall;
wire ibctrl_ibdp_buf_stall;
wire ibctrl_ibdp_bypass_inst_vld;
wire ibctrl_ibdp_cancel;
wire ibctrl_ibdp_chgflw;
wire ibctrl_ibdp_fifo_full_stall;
wire ibctrl_ibdp_fifo_stall;
wire ibctrl_ibdp_ibuf_inst_vld;
wire ibctrl_ibdp_if_chgflw_vld;
wire ibctrl_ibdp_ind_btb_rd_stall;
wire ibctrl_ibdp_ip_chgflw_vld;
wire ibctrl_ibdp_l0_btb_hit;
wire ibctrl_ibdp_l0_btb_mispred;
wire ibctrl_ibdp_l0_btb_miss;
wire ibctrl_ibdp_l0_btb_wait;
wire ibctrl_ibdp_lbuf_inst_vld;
wire ibctrl_ibdp_mispred_stall;
wire ibctrl_ibdp_self_stall;
wire ibctrl_ibuf_bypass_not_select;
wire ibctrl_ibuf_create_vld;
wire ibctrl_ibuf_data_vld;
wire ibctrl_ibuf_flush;
wire ibctrl_ibuf_merge_vld;
wire ibctrl_ibuf_retire_vld;
wire ibctrl_ind_btb_check_vld;
wire ibctrl_ind_btb_fifo_stall;
wire [7 :0] ibctrl_ind_btb_path;
wire ibctrl_ipctrl_low_power_stall;
wire ibctrl_ipctrl_stall;
wire [7 :0] ibctrl_ipdp_chgflw_vl;
wire [1 :0] ibctrl_ipdp_chgflw_vlmul;
wire [2 :0] ibctrl_ipdp_chgflw_vsew;
wire ibctrl_ipdp_pcload;
wire ibctrl_lbuf_bju_mispred;
wire ibctrl_lbuf_create_vld;
wire ibctrl_lbuf_flush;
wire ibctrl_lbuf_retire_vld;
wire ibctrl_pcfifo_if_create_vld;
wire ibctrl_pcfifo_if_ind_btb_miss;
wire [38:0] ibctrl_pcfifo_if_ind_target_pc;
wire [38:0] ibctrl_pcfifo_if_ras_target_pc;
wire ibctrl_pcfifo_if_ras_vld;
wire ibctrl_pcgen_ip_stall;
wire [38:0] ibctrl_pcgen_pc;
wire ibctrl_pcgen_pcload;
wire ibctrl_pcgen_pcload_vld;
wire [1 :0] ibctrl_pcgen_way_pred;
wire ibctrl_ras_inst_pcall;
wire ibctrl_ras_pcall_vld;
wire ibctrl_ras_pcall_vld_for_gateclk;
wire ibctrl_ras_preturn_vld;
wire ibctrl_ras_preturn_vld_for_gateclk;
wire [7 :0] ibdp_ibctrl_chgflw_vl;
wire [1 :0] ibdp_ibctrl_chgflw_vlmul;
wire [2 :0] ibdp_ibctrl_chgflw_vsew;
wire [38:0] ibdp_ibctrl_default_pc;
wire [7 :0] ibdp_ibctrl_hn_ind_br;
wire [7 :0] ibdp_ibctrl_hn_pcall;
wire [7 :0] ibdp_ibctrl_hn_preturn;
wire [38:0] ibdp_ibctrl_l0_btb_mispred_pc;
wire ibdp_ibctrl_ras_chgflw_mask;
wire ibdp_ibctrl_ras_mistaken;
wire [38:0] ibdp_ibctrl_ras_pc;
wire [38:0] ibdp_ibctrl_vpc;
wire ibuf_create_vld;
wire ibuf_empty;
wire ibuf_ibctrl_empty;
wire ibuf_ibctrl_stall;
wire ibuf_inst_vld;
wire ibuf_retire_vld;
wire idu_ifu_id_bypass_stall;
wire idu_ifu_id_stall;
wire idu_stall;
wire ifu_idu_ib_pipedown_gateclk;
wire [22:0] ind_btb_ibctrl_dout;
wire [1 :0] ind_btb_ibctrl_priv_mode;
wire ind_btb_rd_stall;
wire ind_btb_rd_state_clk;
wire ind_btb_rd_state_clk_en;
wire ind_btb_rd_vld;
wire [38:0] ind_chgflw_pc;
wire ind_chgflw_vld;
wire [1 :0] ind_way_pred;
wire ipctrl_ibctrl_expt_vld;
wire ipctrl_ibctrl_if_chgflw_vld;
wire ipctrl_ibctrl_ip_chgflw_vld;
wire ipctrl_ibctrl_l0_btb_hit;
wire ipctrl_ibctrl_l0_btb_mispred;
wire ipctrl_ibctrl_l0_btb_miss;
wire ipctrl_ibctrl_l0_btb_st_wait;
wire ipctrl_ibctrl_vld;
wire [7 :0] ipdp_ibdp_vl_reg;
wire [1 :0] ipdp_ibdp_vlmul_reg;
wire [2 :0] ipdp_ibdp_vsew_reg;
wire iu_ifu_chgflw_vld;
wire iu_ifu_mispred_stall;
wire iu_ifu_pcfifo_full;
wire l0_btb_ras_mistaken;
wire lbuf_active;
wire [38:0] lbuf_chgflw_pc;
wire [1 :0] lbuf_chgflw_pred;
wire [7 :0] lbuf_chgflw_vl;
wire lbuf_chgflw_vld;
wire [1 :0] lbuf_chgflw_vlmul;
wire [2 :0] lbuf_chgflw_vsew;
wire lbuf_create_vld;
wire lbuf_ibctrl_active_idle_flush;
wire [38:0] lbuf_ibctrl_chgflw_pc;
wire [1 :0] lbuf_ibctrl_chgflw_pred;
wire [7 :0] lbuf_ibctrl_chgflw_vl;
wire lbuf_ibctrl_chgflw_vld;
wire [1 :0] lbuf_ibctrl_chgflw_vlmul;
wire [2 :0] lbuf_ibctrl_chgflw_vsew;
wire lbuf_ibctrl_lbuf_active;
wire lbuf_ibctrl_stall;
wire lbuf_inst_vld;
wire lbuf_retire_vld;
wire merge_inst_vld;
wire mispred_stall;
wire pad_yy_icg_scan_en;
wire pcfifo_create_vld;
wire pcfifo_if_ibctrl_more_than_two;
wire pcfifo_stall;
wire pcgen_ibctrl_bju_chgflw;
wire pcgen_ibctrl_cancel;
wire pcgen_ibctrl_ibuf_flush;
wire pcgen_ibctrl_lbuf_flush;
wire ras_chgflw_mask;
wire [38:0] ras_chgflw_pc;
wire ras_chgflw_vld;
wire [1 :0] ras_way_pred;
parameter PC_WIDTH = 40;
//==========================================================
// IB Stage Change Flow
//==========================================================
//------------------ib stage chgflw pc----------------------
// 1.ras chgflw pc
// 2.ind_btb chgflw pc
// 3.lbuf chgflw pc
assign ibctrl_pcgen_pc[PC_WIDTH-2:0] = chgflw_pc[PC_WIDTH-2:0];
assign ibctrl_pcgen_way_pred[1:0] = way_pred[1:0];
// &CombBeg; @38
always @( ras_chgflw_vld
or ras_chgflw_pc[38:0]
or lbuf_chgflw_pc[38:0]
or lbuf_chgflw_vld
or ind_chgflw_vld
or ind_chgflw_pc[38:0]
or ibdp_ibctrl_l0_btb_mispred_pc[38:0])
begin
if(lbuf_chgflw_vld)
chgflw_pc[PC_WIDTH-2:0] = lbuf_chgflw_pc[PC_WIDTH-2:0];
else if(ras_chgflw_vld)
chgflw_pc[PC_WIDTH-2:0] = ras_chgflw_pc[PC_WIDTH-2:0];
else if(ind_chgflw_vld)
chgflw_pc[PC_WIDTH-2:0] = ind_chgflw_pc[PC_WIDTH-2:0];
else
chgflw_pc[PC_WIDTH-2:0] = ibdp_ibctrl_l0_btb_mispred_pc[PC_WIDTH-2:0];
// &CombEnd; @47
end
// &CombBeg; @49
always @( ras_chgflw_vld
or lbuf_chgflw_vld
or lbuf_chgflw_pred[1:0]
or ind_chgflw_vld
or ind_way_pred[1:0]
or ras_way_pred[1:0])
begin
if(lbuf_chgflw_vld)
way_pred[1:0] = lbuf_chgflw_pred[1:0];
else if(ras_chgflw_vld)
way_pred[1:0] = ras_way_pred[1:0];
else if(ind_chgflw_vld)
way_pred[1:0] = ind_way_pred[1:0];
else
way_pred[1:0] = 2'b11;
// &CombEnd; @58
end
// &CombBeg; @61
always @( ras_chgflw_vld
or lbuf_chgflw_vld
or ipdp_ibdp_vlmul_reg[1:0]
or ind_chgflw_vld
or lbuf_chgflw_vlmul[1:0]
or ibdp_ibctrl_chgflw_vlmul[1:0])
begin
if(lbuf_chgflw_vld)
chgflw_vlmul[1:0] = lbuf_chgflw_vlmul[1:0];
else if(ras_chgflw_vld || ind_chgflw_vld)
chgflw_vlmul[1:0] = ibdp_ibctrl_chgflw_vlmul[1:0];
else
chgflw_vlmul[1:0] = ipdp_ibdp_vlmul_reg[1:0];
// &CombEnd; @68
end
// &CombBeg; @70
always @( ras_chgflw_vld
or ibdp_ibctrl_chgflw_vsew[2:0]
or lbuf_chgflw_vld
or lbuf_chgflw_vsew[2:0]
or ind_chgflw_vld
or ipdp_ibdp_vsew_reg[2:0])
begin
if(lbuf_chgflw_vld)
chgflw_vsew[2:0] = lbuf_chgflw_vsew[2:0];
else if(ras_chgflw_vld || ind_chgflw_vld)
chgflw_vsew[2:0] = ibdp_ibctrl_chgflw_vsew[2:0];
else
chgflw_vsew[2:0] = ipdp_ibdp_vsew_reg[2:0];
// &CombEnd; @77
end
// &CombBeg; @80
always @( ibdp_ibctrl_chgflw_vl[7:0]
or lbuf_chgflw_vl[7:0]
or ras_chgflw_vld
or lbuf_chgflw_vld
or ind_chgflw_vld
or ipdp_ibdp_vl_reg[7:0])
begin
if(lbuf_chgflw_vld)
chgflw_vl[7:0] = lbuf_chgflw_vl[7:0];
else if(ras_chgflw_vld || ind_chgflw_vld)
chgflw_vl[7:0] = ibdp_ibctrl_chgflw_vl[7:0];
else
chgflw_vl[7:0] = ipdp_ibdp_vl_reg[7:0];
// &CombEnd; @87
end
assign lbuf_chgflw_vld = lbuf_ibctrl_chgflw_vld;
assign lbuf_chgflw_pc[PC_WIDTH-2:0] = lbuf_ibctrl_chgflw_pc[PC_WIDTH-2:0];
assign lbuf_chgflw_pred[1:0] = lbuf_ibctrl_chgflw_pred[1:0];
assign lbuf_chgflw_vlmul[1:0] = lbuf_ibctrl_chgflw_vlmul[1:0];
assign lbuf_chgflw_vsew[2:0] = lbuf_ibctrl_chgflw_vsew[2:0];
assign lbuf_chgflw_vl[7:0] = lbuf_ibctrl_chgflw_vl[7:0];
assign ind_chgflw_vld = ib_data_vld && (|hn_ind_br[7:0]) && ind_btb_rd_state;
//if IBP not valid or not define
//take next 128 PC as predict PC
assign ind_btb_rd_vld = ind_btb_ibctrl_dout[22]
&& (ind_btb_ibctrl_dout[21:20] == ind_btb_ibctrl_priv_mode[1:0]);
assign ind_chgflw_pc[PC_WIDTH-2:0] = (ind_btb_rd_vld)
? {ib_vpc[PC_WIDTH-2:20], ind_btb_ibctrl_dout[19:0]}
: ibdp_ibctrl_default_pc[PC_WIDTH-2:0]; //Ind BTB Miss
assign ind_way_pred[1:0] = (ind_btb_rd_vld)
? 2'b11
: 2'b00; //Ind BTB Miss
//if RAS not valid
//take next 128 PC as predict PC
assign ras_chgflw_vld = ib_data_vld && (|hn_preturn[7:0]);
assign ras_chgflw_mask = ibdp_ibctrl_ras_chgflw_mask;
assign ras_chgflw_pc[PC_WIDTH-2:0] = ibdp_ibctrl_ras_pc[PC_WIDTH-2:0];
assign ras_way_pred[1:0] = 2'b11;
assign hn_ind_br[7:0] = ibdp_ibctrl_hn_ind_br[7:0] & {8{~ib_expt_vld}};
assign hn_pcall[7:0] = ibdp_ibctrl_hn_pcall[7:0] & {8{~ib_expt_vld}};
assign hn_preturn[7:0] = ibdp_ibctrl_hn_preturn[7:0] & {8{~ib_expt_vld}};
assign ib_vpc[PC_WIDTH-2:0] = ibdp_ibctrl_vpc[PC_WIDTH-2:0];
//--------------------ib stage chgflw valid-----------------
// 1.rsa chgflw valid ||
// 2.ind branch chgflw valid ||
// 3.lbuf chgflw valid
// 4.!ib_self_chgflw_cancel
assign ibctrl_pcgen_pcload = chgflw_vld;
assign ibctrl_pcgen_pcload_vld = chgflw_vld
&& !ib_chgflw_self_stall;
assign ibctrl_ibdp_chgflw = chgflw_vld;
assign chgflw_vld = (
ras_chgflw_vld && !ras_chgflw_mask ||
ind_chgflw_vld ||
lbuf_chgflw_vld ||
l0_btb_ras_mistaken
) &&
!ib_expt_vld;//in case of data = 'bx
assign ib_data_vld = ipctrl_ibctrl_vld;
assign ib_expt_vld = ipctrl_ibctrl_expt_vld;
//ib_chgflw_self_stall
// 1.ibuf full or lbuf special state stall
// 2.more than 2 pc_oper/load inst stall
// 3.pcfifo full stall
// 4.iu mispredict valid & ifu fetch indbr/ras inst stall
// 5.ind_btb result not valid will satll one cycle
//For 2, fifo_stall & 5, ind_btb_rd_stall:
//if it not caccel ib_chgflw
//next cycle pipeline will stall until ib chgflw happen
//ib change flow will cancel previous ib chgflw
//Thus we need not use fifo stall cancel ib chgflw
assign ib_chgflw_self_stall = buf_stall ||
fifo_full_stall ||
mispred_stall;
assign ibctrl_ibdp_mispred_stall = mispred_stall;
assign ibctrl_ibdp_fifo_stall = fifo_stall;
assign ibctrl_ibdp_buf_stall = buf_stall;
assign ibctrl_ibdp_fifo_full_stall = fifo_full_stall;
assign ibctrl_ibdp_ind_btb_rd_stall = ind_btb_rd_stall;
//==========================================================
// IB Stage Stall
//==========================================================
//---------------------Take Notice--------------------------
//idu_ifu_id_bypass_stall > idu_stall > iu_ifu_mispred_stall
//Which can be used to simplify logic
//ibctrl_ipctrl_stall
assign ibctrl_ipctrl_stall = mispred_stall ||
buf_stall ||
fifo_full_stall ||
fifo_stall ||
ind_btb_rd_stall;
// &Force("output","ibctrl_ipctrl_stall"); @177
assign ibctrl_pcgen_ip_stall = ibctrl_ipctrl_stall;
//ibctrl_ipctrl_low_power_stall
//For when low power req, cancel ip refill set to avoid deadlock
//In case of IDU does not access inst and IFU ibuf full
//Which condition IFU should not let ip_refill set
//Otherwise ip_refill will not let ifu_no_op set
assign ibctrl_ipctrl_low_power_stall = mispred_stall ||
buf_stall ||
//ibuf_ibctrl_stall && ib_data_vld ||
fifo_full_stall ||
ib_expt_low_power_stall;
//fifo_stall ||
//ind_btb_rd_stall;
//-----------------------buf_stall--------------------------
//buf_stall valid when
// 1.ibuf full or lbuf special state/full
// 2.ip_ib_vld
assign buf_stall = (
ib_data_vld &&
ibuf_ibctrl_stall //ibuf_full
) ||
lbuf_ibctrl_stall; //lbuf front_branch/cache state
//--------------------fifo_full_stall----------------------
//lbuf active state, pcfifo will also be full
//Thus lbuf active should be treated as ib_data_vld
assign fifo_full_stall = iu_ifu_pcfifo_full &&
(ib_data_vld ||
lbuf_active);
//----------------------mispred_stall----------------------
//mispred_stall valid when
// 1.iu mispred stall valid(from next cycle of mispred)
// 2.ifu ib stage fetch ras/ind_br inst
// 3.in case of IND_BTB or RAS predict Mistake
//mispred stall used for maintain ras & ind_btb right
//if iu_ifu_mispred_stall signal need ifu generate
//when iu_mispred, mispred_state_reg <= 1
//when rtu_retire_mispred, mispred_state_reg <= 0
assign mispred_stall = iu_ifu_mispred_stall &&
ib_data_vld &&
!ib_expt_vld &&
(
(
|hn_pcall[7:0] ||
|hn_preturn[7:0] ||
|hn_ind_br[7:0]
)
);
//-----------------------idu_stall--------------------------
//idu_stall means idu_ifu_id_stall
//which stop inst trans from ifu to idu
assign idu_stall = idu_ifu_id_stall;
//----------------------fifo_stall--------------------------
//fifo_stall get may use 7-8 Gate,
//which will make ib_chgflw_vld timing worse
//Considering ib chgflw not use fifo_stall
//And correct it by cancel IF stage
//fifo_stall valid when
// 1.pcfifo more than two inst
// 2.ip_ib_valid
assign fifo_stall = ib_data_vld && pcfifo_stall;
assign pcfifo_stall = pcfifo_if_ibctrl_more_than_two && !ib_expt_vld;
//------------------ind_btb_rd_stall-----------------------
//ind_btb_rd_stall happens at the moment
//ib stage fetch ind_btb inst && ind_btb jmp state = 0
//Because ind_btb is rd in IB Stage,
//whose result will not be got cur cycle
//Thus we use ind_btb_rd_stall to stall one cycle
//and wait ind_btb result
always @(posedge ind_btb_rd_state_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ind_btb_rd_state <= 1'b0;
else if(ib_cancel || ib_addr_cancel)
ind_btb_rd_state <= 1'b0;
else if(ind_btb_rd_stall)
ind_btb_rd_state <= 1'b1; //ind_btb read
else if(ind_btb_rd_state && chgflw_vld && !fifo_stall && !fifo_full_stall)
ind_btb_rd_state <= 1'b0; //ind_jmp success
else
ind_btb_rd_state <= ind_btb_rd_state;
end
//Gate Clk
// &Instance("gated_clk_cell","x_ind_btb_rd_state_clk"); @267
gated_clk_cell x_ind_btb_rd_state_clk (
.clk_in (forever_cpuclk ),
.clk_out (ind_btb_rd_state_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ind_btb_rd_state_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @268
// .clk_out (ind_btb_rd_state_clk),//Out Clock @269
// .external_en (1'b0), @270
// .global_en (cp0_yy_clk_en), @271
// .local_en (ind_btb_rd_state_clk_en),//Local Condition @272
// .module_en (cp0_ifu_icg_en) @273
// ); @274
assign ind_btb_rd_state_clk_en = ib_cancel ||
ib_addr_cancel ||
ind_btb_rd_state ||
ind_btb_rd_stall;
assign ind_btb_rd_stall = !ind_btb_rd_state &&
ib_data_vld &&
!ib_expt_vld &&
(|hn_ind_br[7:0]);
//------------------expt low power stall-----------------------
//when IB expt valid and ib pc doesn't cross 4K,IP refill will
//be masked
assign ib_expt_low_power_stall = ipctrl_ibctrl_expt_vld
&& ipctrl_ibctrl_vld
&& !(&ib_vpc[10:3]);
//==========================================================
// IB Stage Cancel
//==========================================================
//----------------------ib_cancel---------------------------
//ib_cancel means higher priority unit chgflw
//which should cancel ib stage operation:
// 1.cancel ibuf/lbuf write in
// 2.cancel pcfifo/ldfifo write in
// 3.cancel ibuf inst send to idu
// 4.cancel lbuf inst send to idu
// 5.cancel bypass inst send to idu
assign ib_cancel = pcgen_ibctrl_cancel;
//-------------------ib_addr_cancel-----------------------
//ib_addr_cancel means addrgen cancel signal send to ib stage
//when should cancel ib stage operation:
// 1.cancel ibuf/lbuf write in
// 2.cancel pcfifo/ldfifo write in
// 3.allow ibuf inst send to idu
// 4.allow lbuf inst send to idu
// 5.cancel bypass inst send to idu
assign ib_addr_cancel = addrgen_ibctrl_cancel;
//==========================================================
// IB Stage Valid
//==========================================================
//---------------------ib_ins_vld---------------------------
//ib_inst_vld means inst send to idu valid
//IU chgflw or RTU full inst valid will be maintain by IDU
//lbuf_inst_vld
assign lbuf_inst_vld = lbuf_active &&
!fifo_full_stall &&
//!ib_inst_cancel &&
!mispred_stall;
//ibuf_inst_vld
assign ibuf_inst_vld = !ibuf_empty &&
!lbuf_active &&
//!ib_inst_cancel &&
!mispred_stall;
//bypass_inst_vld
//When iu_ifu_mispred_stall = 1
// idu_ifu_id_bypass_stall always be 1
assign bypass_inst_vld = ib_data_vld &&
ibuf_empty &&
!lbuf_active &&
!buf_stall &&
!fifo_stall &&
!fifo_full_stall &&
!mispred_stall &&
!ib_addr_cancel &&
!ind_btb_rd_stall;
//!ib_inst_cancel &&
// !idu_ifu_id_bypass_stall;
//assign ib_inst_cancel = pcgen_ibctrl_inst_cancel;
//Gate_clk_en for idu use
assign merge_inst_vld = ib_data_vld &&
!ib_expt_vld &&
!ibuf_empty &&
!lbuf_active &&
!buf_stall &&
!fifo_stall &&
!fifo_full_stall &&
!mispred_stall &&
!ib_addr_cancel &&
!ind_btb_rd_stall &&
!idu_stall &&
//!ib_inst_cancel &&
!idu_ifu_id_bypass_stall;
assign ifu_idu_ib_pipedown_gateclk = lbuf_inst_vld ||
ibuf_inst_vld ||
bypass_inst_vld;
// had_ifu_ir_vld;
assign lbuf_active = lbuf_ibctrl_lbuf_active;
assign ibuf_empty = ibuf_ibctrl_empty;
assign ibctrl_ibdp_lbuf_inst_vld = lbuf_inst_vld;
assign ibctrl_ibdp_ibuf_inst_vld = ibuf_inst_vld;
assign ibctrl_ibdp_bypass_inst_vld = bypass_inst_vld;
assign ibctrl_ibdp_cancel = ib_addr_cancel ||
ib_cancel;
assign ibctrl_ibdp_self_stall = buf_stall ||
fifo_full_stall ||
fifo_stall ||
mispred_stall;
assign ibctrl_ibdp_if_chgflw_vld = ipctrl_ibctrl_if_chgflw_vld;
assign ibctrl_ibdp_ip_chgflw_vld = ipctrl_ibctrl_ip_chgflw_vld;
//==========================================================
// ibuf control signal
//==========================================================
assign ibctrl_ibuf_flush = pcgen_ibctrl_ibuf_flush;
assign ibctrl_ibuf_merge_vld = merge_inst_vld;
assign ibctrl_ibuf_create_vld = ibuf_create_vld;
assign ibctrl_ibuf_retire_vld = ibuf_retire_vld;
assign ibctrl_ibuf_data_vld = ib_data_vld;
//When can not send inst to IDU
//Not select bypass way
assign ibctrl_ibuf_bypass_not_select = idu_ifu_id_bypass_stall;
//create_vld when
// 1.ib_data_vld
// 2.!cancel
// 3.!self_stall
assign buf_create_vld = ib_data_vld &&
//!ib_cancel &&
!ib_addr_cancel &&
!(pcfifo_stall) && //fifo_stall
!(iu_ifu_mispred_stall && (|hn_mispred_stall[7:0])) && //mispred_stall
! iu_ifu_pcfifo_full && //fifo_full_stall
!(!ind_btb_rd_state && (|hn_ind_br[7:0])); //ind_btb_rd_stall
assign ibuf_create_vld = buf_create_vld &&
!lbuf_active &&
!(ibuf_ibctrl_stall || lbuf_ibctrl_stall);
assign hn_mispred_stall[7:0] = (hn_pcall[7:0] | hn_preturn[7:0] | hn_ind_br[7:0]);
//retire_vld
//When iu_ifu_mispred_stall = 1
//idu_stall always be 1
assign ibuf_retire_vld = !ibuf_empty &&
//!lbuf_active && //lbuf_active, ibuf must be empty
!mispred_stall &&
!idu_stall;
//==========================================================
// lbuf control signal
//==========================================================
assign ibctrl_lbuf_flush = pcgen_ibctrl_lbuf_flush ||
lbuf_ibctrl_active_idle_flush;
assign ibctrl_lbuf_bju_mispred = pcgen_ibctrl_bju_chgflw;
assign ibctrl_lbuf_create_vld = lbuf_create_vld;
assign ibctrl_lbuf_retire_vld = lbuf_retire_vld;
//create_vld when
// 1.ib_data_vld
// 2.!cancel
// 3.!self_stall
assign lbuf_create_vld = buf_create_vld &&
!iu_ifu_chgflw_vld &&
!ibuf_ibctrl_stall;
//retire_vld
assign lbuf_retire_vld = lbuf_active &&
!fifo_full_stall &&
//!iu_ifu_mispred_stall &&
!idu_stall;
//==========================================================
// pcfifo control signal
//==========================================================
//pcfifo full will be maintained by iu
assign fifo_create_vld = ib_data_vld &&
!ib_cancel &&
!ib_expt_vld &&
!ib_addr_cancel &&
!mispred_stall &&
//!pcfifo_full_stall &&
!ind_btb_rd_stall &&
!buf_stall;
assign pcfifo_create_vld = fifo_create_vld;
assign ibctrl_pcfifo_if_create_vld = pcfifo_create_vld;
assign ibctrl_pcfifo_if_ras_vld = ras_chgflw_vld;
assign ibctrl_pcfifo_if_ras_target_pc[PC_WIDTH-2:0] = ras_chgflw_pc[PC_WIDTH-2:0];
assign ibctrl_pcfifo_if_ind_target_pc[PC_WIDTH-2:0] = ind_chgflw_pc[PC_WIDTH-2:0];
assign ibctrl_pcfifo_if_ind_btb_miss = ~ind_btb_rd_vld;
//==========================================================
// IND_BTB Signal
//==========================================================
assign ibctrl_ind_btb_check_vld = ind_chgflw_vld &&
!ib_chgflw_self_stall &&
!fifo_stall;
assign ibctrl_ind_btb_path[7:0] = ind_chgflw_pc[10:3];
assign ibctrl_ind_btb_fifo_stall = fifo_stall ||
fifo_full_stall;
//==========================================================
// IP Stage Signal
//==========================================================
assign ibctrl_ipdp_pcload = chgflw_vld
&& !ib_chgflw_self_stall
&& !lbuf_active;
assign ibctrl_ipdp_chgflw_vlmul[1:0] = chgflw_vlmul[1:0];
assign ibctrl_ipdp_chgflw_vsew[2:0] = chgflw_vsew[2:0];
assign ibctrl_ipdp_chgflw_vl[7:0] = chgflw_vl[7:0];
//==========================================================
// L0 BTB Signal
//==========================================================
assign l0_btb_ras_mistaken = ibdp_ibctrl_ras_mistaken;
//interface with ibdp
assign ibctrl_ibdp_l0_btb_hit = ipctrl_ibctrl_l0_btb_hit;
assign ibctrl_ibdp_l0_btb_miss = ipctrl_ibctrl_l0_btb_miss;
assign ibctrl_ibdp_l0_btb_mispred = ipctrl_ibctrl_l0_btb_mispred;
assign ibctrl_ibdp_l0_btb_wait = ipctrl_ibctrl_l0_btb_st_wait;
//==========================================================
// RAS Signal
//==========================================================
assign ibctrl_ras_inst_pcall = (|hn_pcall[7:0]) &&
ib_data_vld &&
!ib_expt_vld;
assign ibctrl_ras_pcall_vld = (|hn_pcall[7:0]) &&
ib_data_vld &&
!ib_expt_vld &&
!ib_chgflw_self_stall &&
!fifo_stall &&
!ind_btb_rd_stall;
assign ibctrl_ras_preturn_vld = (|hn_preturn[7:0]) &&
ib_data_vld &&
!ib_expt_vld &&
!ib_chgflw_self_stall &&
!fifo_stall &&
!ind_btb_rd_stall;
assign ibctrl_ras_pcall_vld_for_gateclk = (|hn_pcall[7:0]) &&
ib_data_vld &&
!ib_expt_vld &&
!ib_chgflw_self_stall &&
!ind_btb_rd_stall;
assign ibctrl_ras_preturn_vld_for_gateclk = (|hn_preturn[7:0]) &&
ib_data_vld &&
!ib_expt_vld &&
!ib_chgflw_self_stall &&
!ind_btb_rd_stall;
// &Force("output","ibctrl_ras_preturn_vld"); @539
//Debug_infor
assign ibctrl_debug_ib_ip_stall = ibctrl_ipctrl_stall;
assign ibctrl_debug_mispred_stall = mispred_stall;
assign ibctrl_debug_buf_stall = buf_stall;
assign ibctrl_debug_fifo_stall = fifo_stall;
assign ibctrl_debug_fifo_full_stall = fifo_full_stall;
assign ibctrl_debug_ind_btb_stall = ind_btb_rd_stall;
assign ibctrl_debug_ib_expt_vld = ib_expt_vld;
assign ibctrl_debug_ibuf_full = ibuf_ibctrl_stall;
assign ibctrl_debug_ibuf_empty = ibuf_ibctrl_empty;
assign ibctrl_debug_ibuf_inst_vld = ibuf_inst_vld;
assign ibctrl_debug_lbuf_inst_vld = lbuf_inst_vld;
assign ibctrl_debug_bypass_inst_vld = bypass_inst_vld;
assign ibctrl_debug_ib_vld = ib_data_vld;
// &ModuleEnd; @556
endmodule |
module ct_ifu_ind_btb(
bht_ind_btb_rtu_ghr,
bht_ind_btb_vghr,
cp0_ifu_icg_en,
cp0_ifu_ind_btb_en,
cp0_yy_clk_en,
cp0_yy_priv_mode,
cpurst_b,
forever_cpuclk,
ibctrl_ind_btb_check_vld,
ibctrl_ind_btb_fifo_stall,
ibctrl_ind_btb_path,
ifctrl_ind_btb_inv,
ind_btb_ibctrl_dout,
ind_btb_ibctrl_priv_mode,
ind_btb_ifctrl_inv_done,
ind_btb_ifctrl_inv_on,
ipctrl_ind_btb_con_br_vld,
ipdp_ind_btb_jmp_detect,
pad_yy_icg_scan_en,
rtu_ifu_flush,
rtu_ifu_retire0_chk_idx,
rtu_ifu_retire0_jmp,
rtu_ifu_retire0_jmp_mispred,
rtu_ifu_retire0_mispred,
rtu_ifu_retire0_next_pc,
rtu_ifu_retire1_chk_idx,
rtu_ifu_retire1_jmp,
rtu_ifu_retire2_chk_idx,
rtu_ifu_retire2_jmp
);
// &Ports; @23
input [7 :0] bht_ind_btb_rtu_ghr;
input [7 :0] bht_ind_btb_vghr;
input cp0_ifu_icg_en;
input cp0_ifu_ind_btb_en;
input cp0_yy_clk_en;
input [1 :0] cp0_yy_priv_mode;
input cpurst_b;
input forever_cpuclk;
input ibctrl_ind_btb_check_vld;
input ibctrl_ind_btb_fifo_stall;
input [7 :0] ibctrl_ind_btb_path;
input ifctrl_ind_btb_inv;
input ipctrl_ind_btb_con_br_vld;
input ipdp_ind_btb_jmp_detect;
input pad_yy_icg_scan_en;
input rtu_ifu_flush;
input [7 :0] rtu_ifu_retire0_chk_idx;
input rtu_ifu_retire0_jmp;
input rtu_ifu_retire0_jmp_mispred;
input rtu_ifu_retire0_mispred;
input [38:0] rtu_ifu_retire0_next_pc;
input [7 :0] rtu_ifu_retire1_chk_idx;
input rtu_ifu_retire1_jmp;
input [7 :0] rtu_ifu_retire2_chk_idx;
input rtu_ifu_retire2_jmp;
output [22:0] ind_btb_ibctrl_dout;
output [1 :0] ind_btb_ibctrl_priv_mode;
output ind_btb_ifctrl_inv_done;
output ind_btb_ifctrl_inv_on;
// &Regs; @24
reg after_path_reg_rtu_updt;
reg [22:0] ind_btb_dout_reg;
reg [7 :0] ind_btb_index;
reg [7 :0] ind_btb_inv_cnt;
reg ind_btb_inv_on_reg;
reg ind_btb_rd_flop;
reg [7 :0] path_reg_0;
reg [7 :0] path_reg_1;
reg [7 :0] path_reg_2;
reg [7 :0] path_reg_3;
reg [1 :0] priv_mode_reg;
reg [7 :0] rtu_path_reg_0;
reg [7 :0] rtu_path_reg_0_pre;
reg [7 :0] rtu_path_reg_1;
reg [7 :0] rtu_path_reg_1_pre;
reg [7 :0] rtu_path_reg_2;
reg [7 :0] rtu_path_reg_2_pre;
reg [7 :0] rtu_path_reg_3;
reg [7 :0] rtu_path_reg_3_pre;
// &Wires; @25
wire after_path_reg_rtu_updt_rd;
wire [7 :0] bht_ind_btb_rtu_ghr;
wire [7 :0] bht_ind_btb_vghr;
wire cp0_ifu_icg_en;
wire cp0_ifu_ind_btb_en;
wire cp0_yy_clk_en;
wire [1 :0] cp0_yy_priv_mode;
wire cpurst_b;
wire dout_update_clk;
wire dout_update_clk_en;
wire forever_cpuclk;
wire ib_stage_path_update_rd;
wire ibctrl_ind_btb_check_vld;
wire ibctrl_ind_btb_fifo_stall;
wire [7 :0] ibctrl_ind_btb_path;
wire ifctrl_ind_btb_inv;
wire ind_btb_cen_b;
wire ind_btb_clk_en;
wire [22:0] ind_btb_data_in;
wire [22:0] ind_btb_dout;
wire [22:0] ind_btb_ibctrl_dout;
wire [1 :0] ind_btb_ibctrl_priv_mode;
wire ind_btb_ifctrl_inv_done;
wire ind_btb_ifctrl_inv_on;
wire ind_btb_inv_reg_upd_clk;
wire ind_btb_inv_reg_upd_clk_en;
wire ind_btb_invalidate;
wire ind_btb_rd;
wire [7 :0] ind_btb_rd_index;
wire ind_btb_wen_b;
wire [7 :0] ind_btb_wr_index;
wire ip_stage_vghr_update_rd;
wire ipctrl_ind_btb_con_br_vld;
wire ipdp_ind_btb_jmp_detect;
wire pad_yy_icg_scan_en;
wire [7 :0] path_reg_0_pre;
wire [7 :0] path_reg_1_pre;
wire [7 :0] path_reg_2_pre;
wire [7 :0] path_reg_3_pre;
wire path_reg_rtu_updt;
wire path_reg_rtu_updt_rd;
wire path_reg_updt_clk;
wire path_reg_updt_clk_en;
wire [7 :0] rtu_ghr;
wire rtu_ifu_flush;
wire [7 :0] rtu_ifu_retire0_chk_idx;
wire rtu_ifu_retire0_jmp;
wire rtu_ifu_retire0_jmp_mispred;
wire rtu_ifu_retire0_mispred;
wire [38:0] rtu_ifu_retire0_next_pc;
wire [7 :0] rtu_ifu_retire1_chk_idx;
wire rtu_ifu_retire1_jmp;
wire [7 :0] rtu_ifu_retire2_chk_idx;
wire rtu_ifu_retire2_jmp;
wire rtu_ind_btb_update_vld;
wire rtu_jmp_check_vld;
wire [19:0] rtu_jmp_target_pc;
wire rtu_path_reg_updt_clk;
wire rtu_path_reg_updt_clk_en;
wire updt_clk;
wire updt_clk_en;
wire [7 :0] vghr_reg;
//==========================================================
// Chip Enable to Ind_BTB
//==========================================================
//Ind_BTB is enabled when :
//1.write enable
// a.Ind_BTB Invalid
// b.Ind_BTB Update by RTU
// When RTU ckeck any ind_btb inst, rtu_ind_btb_mispred
// It will update ind BTB memory data
//2.read enable
// a.After RTU_Ind_BTB_recover --> Update PATH Infor
// 1).RTU IFU Flush
// 2).RTU retire any mispredict inst
// b.BJU Change Flow --> Update VGHR
// BJU check any mispredict inst will update VGHR
// Need not to read ind btb, beacuse from IU check Mispred
// inst, until RTU retire Mispred inst, if IFU fetch ind btb
// inst, it will stall inst fetch
// c.IB Stage check Ind_BTB Inst --> Update PATH Infor
// d.IP Stage check Con_br Inst --> Update VGHR
assign ind_btb_cen_b = !ind_btb_inv_on_reg &&
!(cp0_ifu_ind_btb_en &&
(
rtu_ind_btb_update_vld ||
path_reg_rtu_updt_rd ||
after_path_reg_rtu_updt_rd ||
ib_stage_path_update_rd ||
ip_stage_vghr_update_rd
)
);
//Clk Enable Signal for Memory Gate Clk
assign ind_btb_clk_en = ind_btb_inv_on_reg ||
cp0_ifu_ind_btb_en &&
(
rtu_ind_btb_update_vld ||
ipdp_ind_btb_jmp_detect
);
//----------------------read signal-------------------------
//Only When ip stage detect JMP inst will read ind_btb
assign rtu_ind_btb_update_vld = rtu_ifu_retire0_jmp_mispred;
assign ib_stage_path_update_rd = ipdp_ind_btb_jmp_detect ||
ibctrl_ind_btb_check_vld;
assign ip_stage_vghr_update_rd = ipctrl_ind_btb_con_br_vld &&
ipdp_ind_btb_jmp_detect;
assign path_reg_rtu_updt_rd = path_reg_rtu_updt &&
ipdp_ind_btb_jmp_detect;
//-------------after_path_reg_rtu_updt_rd-------------------
// &Instance("gated_clk_cell","x_updt_clk"); @77
gated_clk_cell x_updt_clk (
.clk_in (forever_cpuclk ),
.clk_out (updt_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (updt_clk_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @78
// .clk_out (updt_clk),//Out Clock @79
// .external_en (1'b0), @80
// .global_en (cp0_yy_clk_en), @81
// .local_en (updt_clk_en),//Local Condition @82
// .module_en (cp0_ifu_icg_en) @83
// ); @84
assign updt_clk_en = ind_btb_inv_on_reg ||
path_reg_rtu_updt ||
after_path_reg_rtu_updt;
//path_reg_rtu_updt means rtu retire one any mispredict inst
//path_reg_rtu_updt will recover ind btb's PATH reg
always @(posedge updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
after_path_reg_rtu_updt <= 1'b0;
else if(ind_btb_inv_on_reg)
after_path_reg_rtu_updt <= 1'b0;
else if(path_reg_rtu_updt && rtu_ind_btb_update_vld)//rtu_ind_br_mispred
after_path_reg_rtu_updt <= 1'b1;
else
after_path_reg_rtu_updt <= 1'b0;
end
assign after_path_reg_rtu_updt_rd = after_path_reg_rtu_updt &&
ipdp_ind_btb_jmp_detect;
assign path_reg_rtu_updt = rtu_ifu_retire0_mispred ||
rtu_ifu_flush;
//==========================================================
// Write Enable to Ind_BTB
//==========================================================
//Ind_BTB write priority is higher than Ind_BTB read
//1.Ind_BTB Invalid
//2.Ind_BTB Update by RTU
assign ind_btb_wen_b = !ind_btb_inv_on_reg &&
!(cp0_ifu_ind_btb_en &&
rtu_ind_btb_update_vld);
//==========================================================
// Read Enable to Ind_BTB
//==========================================================
assign ind_btb_rd = cp0_ifu_ind_btb_en &&
(
path_reg_rtu_updt_rd ||
after_path_reg_rtu_updt_rd ||
ib_stage_path_update_rd ||
ip_stage_vghr_update_rd
) &&
!rtu_ind_btb_update_vld &&
!ibctrl_ind_btb_fifo_stall &&
!ind_btb_inv_on_reg;
//==========================================================
// Write Data to Ind BTB
//==========================================================
//data_in[20:0] = {vld, target[19:0]}
assign ind_btb_data_in[22:0] = (ind_btb_inv_on_reg)
? 23'b0
: {1'b1,cp0_yy_priv_mode[1:0],rtu_jmp_target_pc[19:0]};
assign rtu_jmp_target_pc[19:0] = rtu_ifu_retire0_next_pc[19:0];
// &Force("bus","rtu_ifu_retire0_next_pc",38,0); @139
//==========================================================
// Index to Ind BTB
//==========================================================
// &CombBeg; @144
always @( ind_btb_rd_index[7:0]
or ind_btb_inv_cnt[7:0]
or ind_btb_inv_on_reg
or ind_btb_wr_index[7:0]
or rtu_ind_btb_update_vld)
begin
if(ind_btb_inv_on_reg)
ind_btb_index[7:0] = ind_btb_inv_cnt[7:0];
else if(rtu_ind_btb_update_vld)
ind_btb_index[7:0] = ind_btb_wr_index[7:0];
else //if(ind_btb_read)
ind_btb_index[7:0] = ind_btb_rd_index[7:0];
// &CombEnd; @151
end
assign ind_btb_wr_index[7:0] = {
{rtu_path_reg_3[7:6] ^ rtu_ghr[7:6]},
{rtu_path_reg_2[5:4] ^ rtu_ghr[5:4]},
{rtu_path_reg_1[3:2] ^ rtu_ghr[3:2]},
{rtu_path_reg_0[1:0] ^ rtu_ghr[1:0]}
};
//For timing, use vghr_reg in stead of vghr_pre
assign ind_btb_rd_index[7:0] = {
{path_reg_3_pre[7:6] ^ vghr_reg[7:6]},
{path_reg_2_pre[5:4] ^ vghr_reg[5:4]},
{path_reg_1_pre[3:2] ^ vghr_reg[3:2]},
{path_reg_0_pre[1:0] ^ vghr_reg[1:0]}
};
assign rtu_ghr[7:0] = bht_ind_btb_rtu_ghr[7:0];
assign vghr_reg[7:0] = bht_ind_btb_vghr[7:0];
//==========================================================
// rtu_path_reg
//==========================================================
//Gate Clk
// &Instance("gated_clk_cell","x_rtu_path_reg_updt_clk"); @174
gated_clk_cell x_rtu_path_reg_updt_clk (
.clk_in (forever_cpuclk ),
.clk_out (rtu_path_reg_updt_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (rtu_path_reg_updt_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @175
// .clk_out (rtu_path_reg_updt_clk),//Out Clock @176
// .external_en (1'b0), @177
// .global_en (cp0_yy_clk_en), @178
// .local_en (rtu_path_reg_updt_clk_en),//Local Condition @179
// .module_en (cp0_ifu_icg_en) @180
// ); @181
assign rtu_path_reg_updt_clk_en = rtu_jmp_check_vld &&
cp0_ifu_ind_btb_en ||
ind_btb_inv_on_reg;
assign rtu_jmp_check_vld = rtu_ifu_retire0_jmp ||
rtu_ifu_retire1_jmp ||
rtu_ifu_retire2_jmp;
//rtu_path_reg
always @(posedge rtu_path_reg_updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
rtu_path_reg_3[7:0] <= 8'b0;
rtu_path_reg_2[7:0] <= 8'b0;
rtu_path_reg_1[7:0] <= 8'b0;
rtu_path_reg_0[7:0] <= 8'b0;
end
else if(ind_btb_inv_on_reg)
begin
rtu_path_reg_3[7:0] <= 8'b0;
rtu_path_reg_2[7:0] <= 8'b0;
rtu_path_reg_1[7:0] <= 8'b0;
rtu_path_reg_0[7:0] <= 8'b0;
end
else if(rtu_jmp_check_vld && cp0_ifu_ind_btb_en)
begin
rtu_path_reg_3[7:0] <= rtu_path_reg_3_pre[7:0];
rtu_path_reg_2[7:0] <= rtu_path_reg_2_pre[7:0];
rtu_path_reg_1[7:0] <= rtu_path_reg_1_pre[7:0];
rtu_path_reg_0[7:0] <= rtu_path_reg_0_pre[7:0];
end
else
begin
rtu_path_reg_3[7:0] <= rtu_path_reg_3[7:0];
rtu_path_reg_2[7:0] <= rtu_path_reg_2[7:0];
rtu_path_reg_1[7:0] <= rtu_path_reg_1[7:0];
rtu_path_reg_0[7:0] <= rtu_path_reg_0[7:0];
end
end
//rtu_path_reg_pre
// &CombBeg; @222
always @( rtu_ifu_retire1_chk_idx[7:0]
or rtu_ifu_retire2_chk_idx[7:0]
or rtu_path_reg_2[7:0]
or rtu_ifu_retire0_jmp
or rtu_ifu_retire0_chk_idx[7:0]
or rtu_path_reg_1[7:0]
or rtu_ifu_retire1_jmp
or rtu_path_reg_0[7:0]
or rtu_path_reg_3[7:0]
or rtu_ifu_retire2_jmp)
begin
case({rtu_ifu_retire0_jmp, rtu_ifu_retire1_jmp, rtu_ifu_retire2_jmp})
3'b000 : begin
rtu_path_reg_3_pre[7:0] = rtu_path_reg_3[7:0];
rtu_path_reg_2_pre[7:0] = rtu_path_reg_2[7:0];
rtu_path_reg_1_pre[7:0] = rtu_path_reg_1[7:0];
rtu_path_reg_0_pre[7:0] = rtu_path_reg_0[7:0];
end
3'b001 : begin
rtu_path_reg_3_pre[7:0] = rtu_path_reg_2[7:0];
rtu_path_reg_2_pre[7:0] = rtu_path_reg_1[7:0];
rtu_path_reg_1_pre[7:0] = rtu_path_reg_0[7:0];
rtu_path_reg_0_pre[7:0] = rtu_ifu_retire2_chk_idx[7:0];
end
3'b010 : begin
rtu_path_reg_3_pre[7:0] = rtu_path_reg_2[7:0];
rtu_path_reg_2_pre[7:0] = rtu_path_reg_1[7:0];
rtu_path_reg_1_pre[7:0] = rtu_path_reg_0[7:0];
rtu_path_reg_0_pre[7:0] = rtu_ifu_retire1_chk_idx[7:0];
end
3'b100 : begin
rtu_path_reg_3_pre[7:0] = rtu_path_reg_2[7:0];
rtu_path_reg_2_pre[7:0] = rtu_path_reg_1[7:0];
rtu_path_reg_1_pre[7:0] = rtu_path_reg_0[7:0];
rtu_path_reg_0_pre[7:0] = rtu_ifu_retire0_chk_idx[7:0];
end
3'b011 : begin
rtu_path_reg_3_pre[7:0] = rtu_path_reg_1[7:0];
rtu_path_reg_2_pre[7:0] = rtu_path_reg_0[7:0];
rtu_path_reg_1_pre[7:0] = rtu_ifu_retire1_chk_idx[7:0];
rtu_path_reg_0_pre[7:0] = rtu_ifu_retire2_chk_idx[7:0];
end
3'b101 : begin
rtu_path_reg_3_pre[7:0] = rtu_path_reg_1[7:0];
rtu_path_reg_2_pre[7:0] = rtu_path_reg_0[7:0];
rtu_path_reg_1_pre[7:0] = rtu_ifu_retire0_chk_idx[7:0];
rtu_path_reg_0_pre[7:0] = rtu_ifu_retire2_chk_idx[7:0];
end
3'b110 : begin
rtu_path_reg_3_pre[7:0] = rtu_path_reg_1[7:0];
rtu_path_reg_2_pre[7:0] = rtu_path_reg_0[7:0];
rtu_path_reg_1_pre[7:0] = rtu_ifu_retire0_chk_idx[7:0];
rtu_path_reg_0_pre[7:0] = rtu_ifu_retire1_chk_idx[7:0];
end
3'b111 : begin
rtu_path_reg_3_pre[7:0] = rtu_path_reg_0[7:0];
rtu_path_reg_2_pre[7:0] = rtu_ifu_retire0_chk_idx[7:0];
rtu_path_reg_1_pre[7:0] = rtu_ifu_retire1_chk_idx[7:0];
rtu_path_reg_0_pre[7:0] = rtu_ifu_retire2_chk_idx[7:0];
end
default : begin
rtu_path_reg_3_pre[7:0] = rtu_path_reg_3[7:0];
rtu_path_reg_2_pre[7:0] = rtu_path_reg_2[7:0];
rtu_path_reg_1_pre[7:0] = rtu_path_reg_1[7:0];
rtu_path_reg_0_pre[7:0] = rtu_path_reg_0[7:0];
end
endcase
// &CombEnd; @279
end
//==========================================================
// path_reg
//==========================================================
//Gate Clk
// &Instance("gated_clk_cell","x_path_reg_updt_clk"); @285
gated_clk_cell x_path_reg_updt_clk (
.clk_in (forever_cpuclk ),
.clk_out (path_reg_updt_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (path_reg_updt_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @286
// .clk_out (path_reg_updt_clk),//Out Clock @287
// .external_en (1'b0), @288
// .global_en (cp0_yy_clk_en), @289
// .local_en (path_reg_updt_clk_en),//Local Condition @290
// .module_en (cp0_ifu_icg_en) @291
// ); @292
assign path_reg_updt_clk_en = (
path_reg_rtu_updt ||
ibctrl_ind_btb_check_vld
) &&
cp0_ifu_ind_btb_en ||
ind_btb_inv_on_reg;
//path_reg
always @(posedge path_reg_updt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
path_reg_3[7:0] <= 8'b0;
path_reg_2[7:0] <= 8'b0;
path_reg_1[7:0] <= 8'b0;
path_reg_0[7:0] <= 8'b0;
end
else if(ind_btb_inv_on_reg)
begin
path_reg_3[7:0] <= 8'b0;
path_reg_2[7:0] <= 8'b0;
path_reg_1[7:0] <= 8'b0;
path_reg_0[7:0] <= 8'b0;
end
else if((path_reg_rtu_updt || ibctrl_ind_btb_check_vld) && cp0_ifu_ind_btb_en)
begin
path_reg_3[7:0] <= path_reg_3_pre[7:0];
path_reg_2[7:0] <= path_reg_2_pre[7:0];
path_reg_1[7:0] <= path_reg_1_pre[7:0];
path_reg_0[7:0] <= path_reg_0_pre[7:0];
end
else
begin
path_reg_3[7:0] <= path_reg_3[7:0];
path_reg_2[7:0] <= path_reg_2[7:0];
path_reg_1[7:0] <= path_reg_1[7:0];
path_reg_0[7:0] <= path_reg_0[7:0];
end
end
//path_reg_pre
assign path_reg_3_pre[7:0] = (path_reg_rtu_updt)
? rtu_path_reg_3_pre[7:0]
: (ibctrl_ind_btb_check_vld)
? path_reg_2[7:0]
: path_reg_3[7:0];
assign path_reg_2_pre[7:0] = (path_reg_rtu_updt)
? rtu_path_reg_2_pre[7:0]
: (ibctrl_ind_btb_check_vld)
? path_reg_1[7:0]
: path_reg_2[7:0];
assign path_reg_1_pre[7:0] = (path_reg_rtu_updt)
? rtu_path_reg_1_pre[7:0]
: (ibctrl_ind_btb_check_vld)
? path_reg_0[7:0]
: path_reg_1[7:0];
assign path_reg_0_pre[7:0] = (path_reg_rtu_updt)
? rtu_path_reg_0_pre[7:0]
: (ibctrl_ind_btb_check_vld)
? ibctrl_ind_btb_path[7:0]
: path_reg_0[7:0];
//==========================================================
// Ind BTB Data out reg
//==========================================================
//In case of memory write affect the read data of Memory Dout
//when read memory, flop one cycle, write data in dout into reg
always @(posedge forever_cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
ind_btb_rd_flop <= 1'b0;
else if(ind_btb_inv_on_reg)
ind_btb_rd_flop <= 1'b0;
else if(ind_btb_rd)
ind_btb_rd_flop <= 1'b1;
else
ind_btb_rd_flop <= 1'b0;
end
//Gate clk
// &Instance("gated_clk_cell","x_dout_update_clk"); @373
gated_clk_cell x_dout_update_clk (
.clk_in (forever_cpuclk ),
.clk_out (dout_update_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (dout_update_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @374
// .clk_out (dout_update_clk),//Out Clock @375
// .external_en (1'b0), @376
// .global_en (cp0_yy_clk_en), @377
// .local_en (dout_update_clk_en),//Local Condition @378
// .module_en (cp0_ifu_icg_en) @379
// ); @380
assign dout_update_clk_en = ind_btb_rd_flop;
//Dout Reg Update
always @(posedge dout_update_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ind_btb_dout_reg[22:0] <= 23'b0;
else if(ind_btb_rd_flop)
ind_btb_dout_reg[22:0] <= ind_btb_dout[22:0];//Memory Dout
else
ind_btb_dout_reg[22:0] <= ind_btb_dout_reg[22:0];
end
assign ind_btb_ibctrl_dout[22:0] = ind_btb_dout_reg[22:0];
//for timing consideration,when read ind btb,flop priv_mode
always @(posedge dout_update_clk or negedge cpurst_b)
begin
if(!cpurst_b)
priv_mode_reg[1:0] <= 2'b11; //reset machine mode
else if(ind_btb_rd_flop)
priv_mode_reg[1:0] <= cp0_yy_priv_mode[1:0];
else
priv_mode_reg[1:0] <= priv_mode_reg[1:0];
end
assign ind_btb_ibctrl_priv_mode[1:0] = priv_mode_reg[1:0];
//==========================================================
// Invalidation of Ind BTB
//==========================================================
//Gate Clk
// &Instance("gated_clk_cell","x_ind_btb_inv_reg_upd_clk"); @411
gated_clk_cell x_ind_btb_inv_reg_upd_clk (
.clk_in (forever_cpuclk ),
.clk_out (ind_btb_inv_reg_upd_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ind_btb_inv_reg_upd_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @412
// .clk_out (ind_btb_inv_reg_upd_clk),//Out Clock @413
// .external_en (1'b0), @414
// .global_en (cp0_yy_clk_en), @415
// .local_en (ind_btb_inv_reg_upd_clk_en),//Local Condition @416
// .module_en (cp0_ifu_icg_en) @417
// ); @418
assign ind_btb_inv_reg_upd_clk_en = ind_btb_inv_on_reg ||
ind_btb_invalidate;
//Invalidation Index
always @(posedge ind_btb_inv_reg_upd_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ind_btb_inv_cnt[7:0] <= 8'b0;
else if(ind_btb_inv_on_reg)
ind_btb_inv_cnt[7:0] <= ind_btb_inv_cnt[7:0] - 8'b1;
else if(ind_btb_invalidate)
ind_btb_inv_cnt[7:0] <= 8'b11111111;
else
ind_btb_inv_cnt[7:0] <= ind_btb_inv_cnt[7:0];
end
assign ind_btb_invalidate = ifctrl_ind_btb_inv;
//==========================================================
// Invalidating Status Register
//==========================================================
always @(posedge ind_btb_inv_reg_upd_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ind_btb_inv_on_reg <= 1'b0;
else if(!(|ind_btb_inv_cnt[7:0]) && ind_btb_inv_on_reg)
ind_btb_inv_on_reg <= 1'b0;
else if(ind_btb_invalidate)
ind_btb_inv_on_reg <= 1'b1;
else
ind_btb_inv_on_reg <= ind_btb_inv_on_reg;
end
//==========================================================
// Invalidating Finish Signal
//==========================================================
assign ind_btb_ifctrl_inv_done = !ind_btb_inv_on_reg;
assign ind_btb_ifctrl_inv_on = ind_btb_inv_on_reg;
//==========================================================
// Ind BTB Memory Instance
//==========================================================
// &Instance("ct_ifu_ind_btb_array", "x_ct_ifu_ind_btb_array"); @459
ct_ifu_ind_btb_array x_ct_ifu_ind_btb_array (
.cp0_ifu_icg_en (cp0_ifu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.forever_cpuclk (forever_cpuclk ),
.ind_btb_cen_b (ind_btb_cen_b ),
.ind_btb_clk_en (ind_btb_clk_en ),
.ind_btb_data_in (ind_btb_data_in ),
.ind_btb_dout (ind_btb_dout ),
.ind_btb_index (ind_btb_index ),
.ind_btb_wen_b (ind_btb_wen_b ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &ModuleEnd; @461
endmodule |
module ct_ifu_l1_refill(
cp0_ifu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
ifctrl_l1_refill_ins_inv,
ifctrl_l1_refill_ins_inv_dn,
ifctrl_l1_refill_inv_busy,
ifctrl_l1_refill_inv_on,
ifdp_l1_refill_bufferable,
ifdp_l1_refill_cacheable,
ifdp_l1_refill_fifo,
ifdp_l1_refill_machine_mode,
ifdp_l1_refill_secure,
ifdp_l1_refill_supv_mode,
ifdp_l1_refill_tsize,
ifu_hpcp_icache_miss_pre,
ipb_l1_refill_data_vld,
ipb_l1_refill_grnt,
ipb_l1_refill_rdata,
ipb_l1_refill_trans_err,
ipctrl_l1_refill_chk_err,
ipctrl_l1_refill_fifo,
ipctrl_l1_refill_miss_req,
ipctrl_l1_refill_ppc,
ipctrl_l1_refill_req_for_gateclk,
ipctrl_l1_refill_vpc,
l1_refill_debug_refill_st,
l1_refill_icache_if_fifo,
l1_refill_icache_if_first,
l1_refill_icache_if_index,
l1_refill_icache_if_inst_data,
l1_refill_icache_if_last,
l1_refill_icache_if_pre_code,
l1_refill_icache_if_ptag,
l1_refill_icache_if_wr,
l1_refill_ifctrl_ctc,
l1_refill_ifctrl_idle,
l1_refill_ifctrl_pc,
l1_refill_ifctrl_refill_on,
l1_refill_ifctrl_reissue,
l1_refill_ifctrl_start,
l1_refill_ifctrl_start_for_gateclk,
l1_refill_ifctrl_trans_cmplt,
l1_refill_ifdp_acc_err,
l1_refill_ifdp_inst_data,
l1_refill_ifdp_precode,
l1_refill_ifdp_refill_on,
l1_refill_ifdp_tag_data,
l1_refill_inv_wfd_back,
l1_refill_ipb_bufferable,
l1_refill_ipb_cacheable,
l1_refill_ipb_ctc_inv,
l1_refill_ipb_machine_mode,
l1_refill_ipb_ppc,
l1_refill_ipb_pre_cancel,
l1_refill_ipb_refill_on,
l1_refill_ipb_req,
l1_refill_ipb_req_for_gateclk,
l1_refill_ipb_req_pre,
l1_refill_ipb_secure,
l1_refill_ipb_supv_mode,
l1_refill_ipb_tsize,
l1_refill_ipb_vpc,
l1_refill_ipctrl_busy,
pad_yy_icg_scan_en,
pcgen_l1_refill_chgflw
);
// &Ports; @23
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input ifctrl_l1_refill_ins_inv;
input ifctrl_l1_refill_ins_inv_dn;
input ifctrl_l1_refill_inv_busy;
input ifctrl_l1_refill_inv_on;
input ifdp_l1_refill_bufferable;
input ifdp_l1_refill_cacheable;
input ifdp_l1_refill_fifo;
input ifdp_l1_refill_machine_mode;
input ifdp_l1_refill_secure;
input ifdp_l1_refill_supv_mode;
input ifdp_l1_refill_tsize;
input ipb_l1_refill_data_vld;
input ipb_l1_refill_grnt;
input [127:0] ipb_l1_refill_rdata;
input ipb_l1_refill_trans_err;
input ipctrl_l1_refill_chk_err;
input ipctrl_l1_refill_fifo;
input ipctrl_l1_refill_miss_req;
input [38 :0] ipctrl_l1_refill_ppc;
input ipctrl_l1_refill_req_for_gateclk;
input [38 :0] ipctrl_l1_refill_vpc;
input pad_yy_icg_scan_en;
input pcgen_l1_refill_chgflw;
output ifu_hpcp_icache_miss_pre;
output [3 :0] l1_refill_debug_refill_st;
output l1_refill_icache_if_fifo;
output l1_refill_icache_if_first;
output [38 :0] l1_refill_icache_if_index;
output [127:0] l1_refill_icache_if_inst_data;
output l1_refill_icache_if_last;
output [31 :0] l1_refill_icache_if_pre_code;
output [27 :0] l1_refill_icache_if_ptag;
output l1_refill_icache_if_wr;
output l1_refill_ifctrl_ctc;
output l1_refill_ifctrl_idle;
output [38 :0] l1_refill_ifctrl_pc;
output l1_refill_ifctrl_refill_on;
output l1_refill_ifctrl_reissue;
output l1_refill_ifctrl_start;
output l1_refill_ifctrl_start_for_gateclk;
output l1_refill_ifctrl_trans_cmplt;
output l1_refill_ifdp_acc_err;
output [127:0] l1_refill_ifdp_inst_data;
output [31 :0] l1_refill_ifdp_precode;
output l1_refill_ifdp_refill_on;
output [28 :0] l1_refill_ifdp_tag_data;
output l1_refill_inv_wfd_back;
output l1_refill_ipb_bufferable;
output l1_refill_ipb_cacheable;
output l1_refill_ipb_ctc_inv;
output l1_refill_ipb_machine_mode;
output [39 :0] l1_refill_ipb_ppc;
output l1_refill_ipb_pre_cancel;
output l1_refill_ipb_refill_on;
output l1_refill_ipb_req;
output l1_refill_ipb_req_for_gateclk;
output l1_refill_ipb_req_pre;
output l1_refill_ipb_secure;
output l1_refill_ipb_supv_mode;
output l1_refill_ipb_tsize;
output [39 :0] l1_refill_ipb_vpc;
output l1_refill_ipctrl_busy;
// &Regs; @24
reg bufferable;
reg cacheable;
reg inv_wfd_back;
reg l1_refill_icache_if_fifo;
reg machine_mode;
reg [38 :0] physical_pc;
reg [3 :0] refill_cur_state;
reg [3 :0] refill_next_state;
reg secure;
reg supv_mode;
reg tsize;
reg [38 :0] virtual_pc;
// &Wires; @25
wire [7 :0] byte0;
wire [7 :0] byte1;
wire [7 :0] byte10;
wire [7 :0] byte11;
wire [7 :0] byte12;
wire [7 :0] byte13;
wire [7 :0] byte14;
wire [7 :0] byte15;
wire [7 :0] byte2;
wire [7 :0] byte3;
wire [7 :0] byte4;
wire [7 :0] byte5;
wire [7 :0] byte6;
wire [7 :0] byte7;
wire [7 :0] byte8;
wire [7 :0] byte9;
wire change_flow;
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire forever_cpuclk;
wire icache_inv_busy;
wire ifctrl_l1_refill_ins_inv;
wire ifctrl_l1_refill_ins_inv_dn;
wire ifctrl_l1_refill_inv_busy;
wire ifctrl_l1_refill_inv_on;
wire ifdp_l1_refill_bufferable;
wire ifdp_l1_refill_cacheable;
wire ifdp_l1_refill_fifo;
wire ifdp_l1_refill_machine_mode;
wire ifdp_l1_refill_secure;
wire ifdp_l1_refill_supv_mode;
wire ifdp_l1_refill_tsize;
wire ifdp_tag_valid;
wire ifu_hpcp_icache_miss_pre;
wire index_inc_vld;
wire inv_wfd_back_clr;
wire inv_wfd_back_record;
wire [127:0] ipb_l1_refill_data_aft_v2trans;
wire ipb_l1_refill_data_vld;
wire ipb_l1_refill_grnt;
wire [127:0] ipb_l1_refill_rdata;
wire ipb_l1_refill_trans_err;
wire ipb_refill_data_vld;
wire ipb_refill_trans_err;
wire ipctrl_l1_refill_chk_err;
wire ipctrl_l1_refill_fifo;
wire ipctrl_l1_refill_miss_req;
wire [38 :0] ipctrl_l1_refill_ppc;
wire ipctrl_l1_refill_req_for_gateclk;
wire [38 :0] ipctrl_l1_refill_vpc;
wire l1_refill_clk;
wire l1_refill_clk_en;
wire [3 :0] l1_refill_debug_refill_st;
wire l1_refill_icache_if_first;
wire [38 :0] l1_refill_icache_if_index;
wire [127:0] l1_refill_icache_if_inst_data;
wire l1_refill_icache_if_last;
wire [31 :0] l1_refill_icache_if_pre_code;
wire [27 :0] l1_refill_icache_if_ptag;
wire l1_refill_icache_if_wr;
wire l1_refill_ifctrl_ctc;
wire l1_refill_ifctrl_idle;
wire [38 :0] l1_refill_ifctrl_pc;
wire l1_refill_ifctrl_refill_on;
wire l1_refill_ifctrl_reissue;
wire l1_refill_ifctrl_start;
wire l1_refill_ifctrl_start_for_gateclk;
wire l1_refill_ifctrl_trans_cmplt;
wire l1_refill_ifdp_acc_err;
wire [127:0] l1_refill_ifdp_inst_data;
wire [31 :0] l1_refill_ifdp_precode;
wire l1_refill_ifdp_refill_on;
wire [28 :0] l1_refill_ifdp_tag_data;
wire l1_refill_inv_wfd_back;
wire l1_refill_ipb_bufferable;
wire l1_refill_ipb_cacheable;
wire l1_refill_ipb_ctc_inv;
wire l1_refill_ipb_machine_mode;
wire [39 :0] l1_refill_ipb_ppc;
wire l1_refill_ipb_pre_cancel;
wire l1_refill_ipb_refill_on;
wire l1_refill_ipb_req;
wire l1_refill_ipb_req_for_gateclk;
wire l1_refill_ipb_req_pre;
wire l1_refill_ipb_secure;
wire l1_refill_ipb_supv_mode;
wire l1_refill_ipb_tsize;
wire [39 :0] l1_refill_ipb_vpc;
wire l1_refill_ipctrl_busy;
wire pad_yy_icg_scan_en;
wire pcgen_l1_refill_chgflw;
wire [31 :0] pre_code_info;
wire refill_grnt;
wire refill_sm_busy;
wire refill_sm_on;
wire refill_start;
wire refill_start_for_gateclk;
parameter PC_WIDTH = 40;
parameter IDLE = 4'b0000;
parameter REQ = 4'b0001;
//parameter WFG = 4'b0010;
parameter WFD1 = 4'b0100;
parameter WFD2 = 4'b0101;
parameter WFD3 = 4'b0110;
parameter WFD4 = 4'b0111;
parameter INV_WFD1 = 4'b1000;
parameter INV_WFD2 = 4'b1001;
parameter INV_WFD3 = 4'b1010;
parameter INV_WFD4 = 4'b1011;
parameter CTC_INV = 4'b0011;
//==========================================================
// Gate Clk of Icache Refill SM
//==========================================================
// &Instance("gated_clk_cell","x_l1_refill_clk"); @42
gated_clk_cell x_l1_refill_clk (
.clk_in (forever_cpuclk ),
.clk_out (l1_refill_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (l1_refill_clk_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @43
// .clk_out (l1_refill_clk),//Out Clock @44
// .external_en (1'b0), @45
// .global_en (cp0_yy_clk_en), @46
// .local_en (l1_refill_clk_en),//Local Condition @47
// .module_en (cp0_ifu_icg_en) @48
// ); @49
assign l1_refill_clk_en = refill_start_for_gateclk ||
(refill_cur_state[3:0] != IDLE);
//------------------FSM of ICache Refill--------------------
//State Description:
//IDLE : Wait for icache refill request
//REQ : Wait for biu_ifu_refill_grant or change flow
// a. grant is earlier than chgflw --> WFD1
// b. chgflw is eariier than grant --> WFG
// c. grant arrive with chgflw at the same time --> INV_WFD1
//WFG : Wait for grant signal and then go into INV_WFD1
//WFD1 : Wait for the 1st valid refill data
//WFD2 : Wait for the 2nd valid refill data
//WFD3 : Wait for the 3rd valid refill data
//WFD4 : Wait for the 4th valid refill data
//INV_WFD1 : Wait for the 1st invalid refill data
//INV_WFD2 : Wait for the 2nd invalid refill data
//INV_WFD3 : Wait for the 3rd invalid refill data
//INV_WFD4 : Wait for the 4th invalid refill data
//CTC_INV : Make CTC_INV to execute first
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
refill_cur_state[3:0] <= IDLE;
else
refill_cur_state[3:0] <= refill_next_state[3:0];
end
// &CombBeg; @79
always @( ifctrl_l1_refill_ins_inv
or refill_grnt
or ifctrl_l1_refill_ins_inv_dn
or inv_wfd_back
or refill_cur_state[3:0]
or ipb_refill_trans_err
or tsize
or change_flow
or ipb_refill_data_vld
or refill_start)
begin
case(refill_cur_state[3:0])
IDLE : if(refill_start)
refill_next_state[3:0] = REQ;
else
refill_next_state[3:0] = IDLE;
REQ : if(change_flow && !refill_grnt)
refill_next_state[3:0] = IDLE;//before grnt, set req = 0, biu will ignore this req
else if(!change_flow && refill_grnt)
refill_next_state[3:0] = WFD1;
else if(change_flow && refill_grnt)
refill_next_state[3:0] = INV_WFD1;
else if(ifctrl_l1_refill_ins_inv)
refill_next_state[3:0] = IDLE;
else
refill_next_state[3:0] = REQ;
//Because of the BIU req cancel logic
//set ifu req = 0, biu will ignore req
//WFG state does not need again
//WFG : if(refill_grnt)
// refill_next_state[3:0] = INV_WFD1;
// else
// refill_next_state[3:0] = WFG;
INV_WFD1 : if(ipb_refill_data_vld || ipb_refill_trans_err)
begin
if(tsize)
refill_next_state[3:0] = INV_WFD2;
else
refill_next_state[3:0] = IDLE;
end
else if(ifctrl_l1_refill_ins_inv)
refill_next_state[3:0] = CTC_INV;
else
refill_next_state[3:0] = INV_WFD1;
INV_WFD2 : if(ipb_refill_data_vld || ipb_refill_trans_err)
refill_next_state[3:0] = INV_WFD3;
else
refill_next_state[3:0] = INV_WFD2;
INV_WFD3 : if(ipb_refill_data_vld || ipb_refill_trans_err)
refill_next_state[3:0] = INV_WFD4;
else
refill_next_state[3:0] = INV_WFD3;
INV_WFD4 : if(ipb_refill_data_vld || ipb_refill_trans_err)
refill_next_state[3:0] = IDLE;
else
refill_next_state[3:0] = INV_WFD4;
WFD1 : if(ipb_refill_data_vld)
begin
if(tsize)
refill_next_state[3:0] = WFD2;
else
refill_next_state[3:0] = IDLE;
end
else if(ipb_refill_trans_err)
begin
if(tsize)
refill_next_state[3:0] = INV_WFD2;
else
refill_next_state[3:0] = IDLE;
end
else if(change_flow)
refill_next_state[3:0] = INV_WFD1;
else if(ifctrl_l1_refill_ins_inv)
refill_next_state[3:0] = CTC_INV;
else
refill_next_state[3:0] = WFD1;
WFD2 : if(ipb_refill_data_vld)
refill_next_state[3:0] = WFD3;
else if(ipb_refill_trans_err)
refill_next_state[3:0] = INV_WFD3;
else
refill_next_state[3:0] = WFD2;
WFD3 : if(ipb_refill_data_vld)
refill_next_state[3:0] = WFD4;
else if(ipb_refill_trans_err)
refill_next_state[3:0] = INV_WFD4;
else
refill_next_state[3:0] = WFD3;
WFD4 : if(ipb_refill_data_vld)
refill_next_state[3:0] = IDLE;
else if(ipb_refill_trans_err)
refill_next_state[3:0] = IDLE;
else
refill_next_state[3:0] = WFD4;
CTC_INV : if(ifctrl_l1_refill_ins_inv_dn && inv_wfd_back)
refill_next_state[3:0] = INV_WFD1;
// else if(ifctrl_l1_refill_ins_inv_dn)
// refill_next_state[3:0] = WFD1;
else
refill_next_state[3:0] = CTC_INV;
default : refill_next_state[3:0] = IDLE;
endcase
// &CombEnd; @171
end
//------------------Conditional Signal----------------------
assign refill_start = ipctrl_l1_refill_miss_req &&
!ifctrl_l1_refill_inv_on;
assign refill_start_for_gateclk = ipctrl_l1_refill_req_for_gateclk &&
!ifctrl_l1_refill_inv_on;
assign change_flow = pcgen_l1_refill_chgflw;
assign refill_grnt = ipb_l1_refill_grnt;
assign ipb_refill_data_vld = ipb_l1_refill_data_vld;
assign ipb_refill_trans_err = ipb_l1_refill_trans_err;
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
inv_wfd_back <= 1'b0;
else if(inv_wfd_back_clr)
inv_wfd_back <= 1'b0;
else if(inv_wfd_back_record)
inv_wfd_back <= 1'b1;
else
inv_wfd_back <= inv_wfd_back;
end
assign inv_wfd_back_clr = refill_start &&
(refill_cur_state[3:0] == IDLE);
assign inv_wfd_back_record = ifctrl_l1_refill_ins_inv &&
(refill_cur_state[3:0] == INV_WFD1 ||
refill_cur_state[3:0] == WFD1);
//==========================================================
// L1 Refill to icache if
//==========================================================
//refill inst data
//If want to use, please use // code in the following
assign l1_refill_icache_if_inst_data[127:0] = ipb_l1_refill_data_aft_v2trans[127:0];
// &Force("output","l1_refill_icache_if_inst_data"); @223
assign ipb_l1_refill_data_aft_v2trans[127:0] = {
{byte1[7:0], byte0[7:0]},
{byte3[7:0], byte2[7:0]},
{byte5[7:0], byte4[7:0]},
{byte7[7:0], byte6[7:0]},
{byte9[7:0], byte8[7:0]},
{byte11[7:0], byte10[7:0]},
{byte13[7:0], byte12[7:0]},
{byte15[7:0], byte14[7:0]}
};
assign byte15[7:0] = ipb_l1_refill_rdata[127:120];
assign byte14[7:0] = ipb_l1_refill_rdata[119:112];
assign byte13[7:0] = ipb_l1_refill_rdata[111:104];
assign byte12[7:0] = ipb_l1_refill_rdata[103: 96];
assign byte11[7:0] = ipb_l1_refill_rdata[ 95: 88];
assign byte10[7:0] = ipb_l1_refill_rdata[ 87: 80];
assign byte9[7:0] = ipb_l1_refill_rdata[ 79: 72];
assign byte8[7:0] = ipb_l1_refill_rdata[ 71: 64];
assign byte7[7:0] = ipb_l1_refill_rdata[ 63: 56];
assign byte6[7:0] = ipb_l1_refill_rdata[ 55: 48];
assign byte5[7:0] = ipb_l1_refill_rdata[ 47: 40];
assign byte4[7:0] = ipb_l1_refill_rdata[ 39: 32];
assign byte3[7:0] = ipb_l1_refill_rdata[ 31: 24];
assign byte2[7:0] = ipb_l1_refill_rdata[ 23: 16];
assign byte1[7:0] = ipb_l1_refill_rdata[ 15: 8];
assign byte0[7:0] = ipb_l1_refill_rdata[ 7: 0];
//refill tag data
assign l1_refill_icache_if_ptag[27:0] = physical_pc[PC_WIDTH-2:11];
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
physical_pc[PC_WIDTH-2:0] <= {PC_WIDTH-1{1'b0}};
else if(ipctrl_l1_refill_req_for_gateclk)
physical_pc[PC_WIDTH-2:0] <= ipctrl_l1_refill_ppc[PC_WIDTH-2:0];
else if(index_inc_vld)
physical_pc[PC_WIDTH-2:0] <= {physical_pc[PC_WIDTH-2:5],
physical_pc[ 4:3] + 2'b1,
3'b0};
else
physical_pc[PC_WIDTH-2:0] <= physical_pc[PC_WIDTH-2:0];
end
//l1_refill_icache_if_index
assign l1_refill_icache_if_index[PC_WIDTH-2:0] = virtual_pc[PC_WIDTH-2:0];
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
virtual_pc[PC_WIDTH-2:0] <= {PC_WIDTH-1{1'b0}};
else if(ipctrl_l1_refill_req_for_gateclk)
virtual_pc[PC_WIDTH-2:0] <= ipctrl_l1_refill_vpc[PC_WIDTH-2:0];
else if(index_inc_vld)
virtual_pc[PC_WIDTH-2:0] <= {virtual_pc[PC_WIDTH-2:5],
virtual_pc[4:3] + 2'b1,
3'b0};
else
virtual_pc[PC_WIDTH-2:0] <= virtual_pc[PC_WIDTH-2:0];
end
//index_inc_vld
//if ipb_refill_data_vld && tsize
//when index_inc_vld , pc[ 4:3] + 1
assign index_inc_vld = (
(refill_cur_state[3:0] == WFD1) &&
!icache_inv_busy &&
(ipb_l1_refill_trans_err ||
ipb_l1_refill_data_vld) &&
tsize
) ||
(
(refill_cur_state[3:0] == WFD2) &&
!icache_inv_busy &&
(ipb_l1_refill_trans_err ||
ipb_l1_refill_data_vld)
) ||
(
(refill_cur_state[3:0] == WFD3) &&
!icache_inv_busy &&
(ipb_l1_refill_trans_err ||
ipb_l1_refill_data_vld)
);
assign icache_inv_busy = ifctrl_l1_refill_inv_busy;
//l1_refill_icache_if_fifo
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
l1_refill_icache_if_fifo <= 1'b0;
else if(refill_start && !ipctrl_l1_refill_chk_err)
l1_refill_icache_if_fifo <= ifdp_l1_refill_fifo;
else if(refill_start && ipctrl_l1_refill_chk_err)
l1_refill_icache_if_fifo <= ipctrl_l1_refill_fifo;
else
l1_refill_icache_if_fifo <= l1_refill_icache_if_fifo;
end
// &Force("output","l1_refill_icache_if_fifo"); @322
// &Force("output","l1_refill_icache_if_chk_err"); @336
//l1_refill_icache_if_wr
assign l1_refill_icache_if_wr = refill_cur_state[2] && //WFDn
ipb_l1_refill_data_vld &&
tsize;
//l1_refill_icache_if_first
assign l1_refill_icache_if_first = (refill_cur_state[3:0] == WFD1) &&
ipb_l1_refill_data_vld &&
tsize;
//l1_refill_icache_if_last
assign l1_refill_icache_if_last = (refill_cur_state[3:0] == WFD4) &&
ipb_l1_refill_data_vld;
//==========================================================
// The Precode Information
//==========================================================
// &Instance("ct_ifu_precode", "x_ct_ifu_precode"); @371
ct_ifu_precode x_ct_ifu_precode (
.inst_data (ipb_l1_refill_data_aft_v2trans),
.pre_code (pre_code_info )
);
// &Connect( @372
// .inst_data (ipb_l1_refill_data_aft_v2trans), @373
// .pre_code (pre_code_info ) @374
// ); @375
assign l1_refill_icache_if_pre_code[31:0] = pre_code_info[31:0];
//==========================================================
// Refill State Machine on/busy Signal
//==========================================================
//refill sm on state means refill sm not accept chgflw signal
//and ifctrl should stall PC
//refill sm busy state means refill sm not allow icache refill request
assign refill_sm_on = (refill_cur_state[3:0] == REQ) ||
(refill_cur_state[3:0] == CTC_INV) ||
refill_cur_state[2]; //WFDn
assign refill_sm_busy = (refill_cur_state[3:0] != IDLE);
//==========================================================
// L1 Refill to IF Ctrl
//==========================================================
assign l1_refill_ifctrl_refill_on = refill_sm_on;
//ipb_l1_refill_trans_err should also be treated as trans_cmplt
//It will set data valid of ifctrl and not let refill_on_stall set
assign l1_refill_ifctrl_trans_cmplt = ipb_refill_data_vld ||
ipb_l1_refill_trans_err;
assign l1_refill_ifctrl_pc[PC_WIDTH-2:0] = virtual_pc[PC_WIDTH-2:0];
//L1 Refill Reissue will occur next cycle under two condition:
//(ifctrl will flop L1_Refill_Reissue and send it to pcgen)
//1.WFD4 state && ipb_refill_data_vld ||
// WFD1 state && ipb_refill_data_vld && !tsize
// which means l1 refill finish normally.
// And when l1 refill WFD4 && data_vld,
// pcgen_pc = refill_next_pc and it <not access icache>
// Thus, next cycle, reissue refill_next_pc(if_pc at that time)
// and let it access icache
//2.WFDX state && ipb_l1_refill_trans_err
// a.if if_pc hit refill pc, if_data_vld = 1 and if_stall not set
// Expt infor will send to ip stage
// Next cycle, reissue the next pc of hit pc
// Because it not access icache
// Even not reissue next pc of hit pc, it will not make mistake
// for expt will flush all following operation
// b.if if_pc not hit refill pc, if_data_vld = 0 and if_stall set
// Next cycle SM turn to INV_WFD and let inst fetch run normally
// and the if_pc is the same as previous if_pc because of stall
// Reissue it and let it access icache
//3.INV_WFDX
// Inst fetch flow has changed already,
// and the expt infor will not send to if stage
// expt infor also has no sense to if stage
assign l1_refill_ifctrl_reissue = (refill_cur_state[3:0] == WFD1) &&
ipb_refill_data_vld &&
!tsize ||
(refill_cur_state[3:0] == WFD4) &&
ipb_refill_data_vld ||
(refill_cur_state[2]) && //WFDn
ipb_l1_refill_trans_err;
//Signal send to ifctrl for low power
assign l1_refill_ifctrl_idle = (refill_cur_state[3:0] == IDLE);
assign l1_refill_ifctrl_start = refill_start;
assign l1_refill_ifctrl_ctc = (refill_cur_state[3:0] == CTC_INV);
assign l1_refill_inv_wfd_back = inv_wfd_back;
assign l1_refill_ifctrl_start_for_gateclk = refill_start_for_gateclk;
//==========================================================
// L1 Refill to IF Data Path
//==========================================================
//l1_refill_ifdp_refill_on means inform if stage
//Inst data from refill state machine not icache
assign l1_refill_ifdp_refill_on = refill_sm_on;
assign l1_refill_ifdp_inst_data[127:0] = ipb_l1_refill_data_aft_v2trans[127:0];
assign l1_refill_ifdp_precode[31:0] = pre_code_info[31:0];
assign l1_refill_ifdp_tag_data[28:0] = {ifdp_tag_valid, physical_pc[PC_WIDTH-2:11]};
assign ifdp_tag_valid = refill_cur_state[2] && //WFDn
ipb_refill_data_vld;
assign l1_refill_ifdp_acc_err = refill_cur_state[2] && //WFDn
ipb_l1_refill_trans_err;
//==========================================================
// L1 Refill to IP Stage
//==========================================================
assign l1_refill_ipctrl_busy = refill_sm_busy;
//==========================================================
// Record Transfer Size and prot
//==========================================================
//Tsize
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
tsize <= 1'b0;
// else if(vector_l1_refill_miss_req)
// tsize <= vector_l1_refill_tsize;
else if(ipctrl_l1_refill_miss_req)
tsize <= ifdp_l1_refill_tsize;
else
tsize <= tsize;
end
//Caccheable
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cacheable <= 1'b0;
else if(ipctrl_l1_refill_miss_req)
cacheable <= ifdp_l1_refill_cacheable;
else
cacheable <= cacheable;
end
//Bufferable
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
bufferable <= 1'b0;
else if(ipctrl_l1_refill_miss_req)
bufferable <= ifdp_l1_refill_bufferable;
else
bufferable <= bufferable;
end
//Supv_mode
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
supv_mode <= 1'b0;
else if(ipctrl_l1_refill_miss_req)
supv_mode <= ifdp_l1_refill_supv_mode;
else
supv_mode <= supv_mode;
end
//Machine_mode
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
machine_mode <= 1'b0;
else if(ipctrl_l1_refill_miss_req)
machine_mode <= ifdp_l1_refill_machine_mode;
else
machine_mode <= machine_mode;
end
//Secure
always @(posedge l1_refill_clk or negedge cpurst_b)
begin
if(!cpurst_b)
secure <= 1'b0;
else if(ipctrl_l1_refill_miss_req)
secure <= ifdp_l1_refill_secure;
else
secure <= secure;
end
//==========================================================
// Interface to BIU
//==========================================================
assign l1_refill_ipb_req = (refill_cur_state[3:0] == REQ);
assign l1_refill_ipb_tsize = tsize;
assign l1_refill_ipb_cacheable = cacheable;
assign l1_refill_ipb_bufferable = bufferable;
assign l1_refill_ipb_supv_mode = supv_mode;
assign l1_refill_ipb_machine_mode = machine_mode;
assign l1_refill_ipb_secure = secure;
assign l1_refill_ipb_ppc[39:0] = {physical_pc[PC_WIDTH-2:0], 1'b0};
assign l1_refill_ipb_vpc[39:0] = {virtual_pc[PC_WIDTH-2:0],1'b0};
assign l1_refill_ipb_ctc_inv = (refill_cur_state[3:0] == CTC_INV);
assign l1_refill_ipb_pre_cancel = pcgen_l1_refill_chgflw ||
ifctrl_l1_refill_inv_busy;
// vector_l1_refill_busy;
//==========================================================
// Interface to ipb
//==========================================================
assign l1_refill_ipb_refill_on = (refill_cur_state[3:0] == REQ) &&
!change_flow;
assign l1_refill_ipb_req_pre = (refill_cur_state[3:0] == IDLE) &&
refill_start_for_gateclk ||
(refill_cur_state[3:0] == REQ) &&
!change_flow && !refill_grnt &&
!ifctrl_l1_refill_ins_inv;
assign l1_refill_ipb_req_for_gateclk = (refill_cur_state[3:0] == IDLE) &&
refill_start_for_gateclk ||
(refill_cur_state[3:0] == REQ) &&
!ifctrl_l1_refill_ins_inv;
//==========================================================
// Interface to PMU
//==========================================================
assign ifu_hpcp_icache_miss_pre = (refill_cur_state[3:0] == WFD1) &&
(ipb_refill_data_vld || ipb_refill_trans_err);
//Debug Infor
assign l1_refill_debug_refill_st[3:0] = refill_cur_state[3:0];
// &ModuleEnd; @601
endmodule |
module ct_rmu_top_dummy(
apb_clk,
apbrst_b,
penable,
perr_rmr,
prdata_rmr,
pready_rmr,
psel_rmr
);
// &Ports; @3
input apb_clk;
input apbrst_b;
input penable;
input psel_rmr;
output perr_rmr;
output [31:0] prdata_rmr;
output pready_rmr;
// &Regs; @4
reg perr_rmr;
reg pready_rmr;
// &Wires; @5
wire acc_err;
wire apb_clk;
wire apbrst_b;
wire [31:0] data_out;
wire penable;
wire [31:0] prdata_rmr;
wire priv_err;
wire psel_rmr;
always @(posedge apb_clk or negedge apbrst_b)
begin
if(~apbrst_b)
pready_rmr <= 1'b0;
else if (psel_rmr & !penable)
pready_rmr <= 1'b1;
else
pready_rmr <= 1'b0;
end
always @(posedge apb_clk or negedge apbrst_b)
begin
if(~apbrst_b)
perr_rmr <= 1'b0;
else if (psel_rmr & !penable & (acc_err | priv_err))
perr_rmr <= 1'b1;
else
perr_rmr <= 1'b0;
end
assign prdata_rmr[31:0] = data_out[31:0];
assign acc_err = 1'b1;
assign priv_err = 1'b1;
assign data_out[31:0] = 32'b0;
// &ModuleEnd; @34
endmodule |
module mp_top_golden_port(
axim_clk_en,
biu_pad_araddr,
biu_pad_arburst,
biu_pad_arcache,
biu_pad_arid,
biu_pad_arlen,
biu_pad_arlock,
biu_pad_arprot,
biu_pad_arsize,
biu_pad_arvalid,
biu_pad_awaddr,
biu_pad_awburst,
biu_pad_awcache,
biu_pad_awid,
biu_pad_awlen,
biu_pad_awlock,
biu_pad_awprot,
biu_pad_awsize,
biu_pad_awvalid,
biu_pad_bready,
biu_pad_cactive,
biu_pad_csysack,
biu_pad_rready,
biu_pad_wdata,
biu_pad_wlast,
biu_pad_wstrb,
biu_pad_wvalid,
core0_pad_jdb_pm,
core0_pad_lpmd_b,
core0_pad_mstatus,
core0_pad_retire0,
core0_pad_retire0_pc,
core0_pad_retire1,
core0_pad_retire1_pc,
core0_pad_retire2,
core0_pad_retire2_pc,
core1_pad_jdb_pm,
core1_pad_lpmd_b,
core1_pad_mstatus,
core1_pad_retire0,
core1_pad_retire0_pc,
core1_pad_retire1,
core1_pad_retire1_pc,
core1_pad_retire2,
core1_pad_retire2_pc,
cpu_debug_port,
cpu_pad_l2cache_flush_done,
cpu_pad_no_op,
had_pad_jtg_tdo,
had_pad_jtg_tdo_en,
pad_biu_arready,
pad_biu_awready,
pad_biu_bid,
pad_biu_bresp,
pad_biu_bvalid,
pad_biu_csysreq,
pad_biu_rdata,
pad_biu_rid,
pad_biu_rlast,
pad_biu_rresp,
pad_biu_rvalid,
pad_biu_wready,
pad_core0_dbg_mask,
pad_core0_dbgrq_b,
pad_core0_hartid,
pad_core0_rst_b,
pad_core0_rvba,
pad_core1_dbg_mask,
pad_core1_dbgrq_b,
pad_core1_hartid,
pad_core1_rst_b,
pad_core1_rvba,
pad_cpu_apb_base,
pad_cpu_l2cache_flush_req,
pad_cpu_rst_b,
pad_cpu_sys_cnt,
pad_had_jtg_tclk,
pad_had_jtg_tdi,
pad_had_jtg_tms,
pad_had_jtg_trst_b,
pad_l2c_data_mbist_clk_ratio,
pad_l2c_tag_mbist_clk_ratio,
pad_plic_int_cfg,
pad_plic_int_vld,
pad_yy_dft_clk_rst_b,
pad_yy_icg_scan_en,
pad_yy_mbist_mode,
pad_yy_scan_enable,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
pll_cpu_clk
);
// &Ports; @3
input axim_clk_en;
input pad_biu_arready;
input pad_biu_awready;
input [7 :0] pad_biu_bid;
input [1 :0] pad_biu_bresp;
input pad_biu_bvalid;
input pad_biu_csysreq;
input [127:0] pad_biu_rdata;
input [7 :0] pad_biu_rid;
input pad_biu_rlast;
input [1 :0] pad_biu_rresp;
input pad_biu_rvalid;
input pad_biu_wready;
input pad_core0_dbg_mask;
input pad_core0_dbgrq_b;
input [2 :0] pad_core0_hartid;
input pad_core0_rst_b;
input [39 :0] pad_core0_rvba;
input pad_core1_dbg_mask;
input pad_core1_dbgrq_b;
input [2 :0] pad_core1_hartid;
input pad_core1_rst_b;
input [39 :0] pad_core1_rvba;
input [39 :0] pad_cpu_apb_base;
input pad_cpu_l2cache_flush_req;
input pad_cpu_rst_b;
input [63 :0] pad_cpu_sys_cnt;
input pad_had_jtg_tclk;
input pad_had_jtg_tdi;
input pad_had_jtg_tms;
input pad_had_jtg_trst_b;
input [2 :0] pad_l2c_data_mbist_clk_ratio;
input [2 :0] pad_l2c_tag_mbist_clk_ratio;
input [143:0] pad_plic_int_cfg;
input [143:0] pad_plic_int_vld;
input pad_yy_dft_clk_rst_b;
input pad_yy_icg_scan_en;
input pad_yy_mbist_mode;
input pad_yy_scan_enable;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
input pll_cpu_clk;
output [39 :0] biu_pad_araddr;
output [1 :0] biu_pad_arburst;
output [3 :0] biu_pad_arcache;
output [7 :0] biu_pad_arid;
output [7 :0] biu_pad_arlen;
output biu_pad_arlock;
output [2 :0] biu_pad_arprot;
output [2 :0] biu_pad_arsize;
output biu_pad_arvalid;
output [39 :0] biu_pad_awaddr;
output [1 :0] biu_pad_awburst;
output [3 :0] biu_pad_awcache;
output [7 :0] biu_pad_awid;
output [7 :0] biu_pad_awlen;
output biu_pad_awlock;
output [2 :0] biu_pad_awprot;
output [2 :0] biu_pad_awsize;
output biu_pad_awvalid;
output biu_pad_bready;
output biu_pad_cactive;
output biu_pad_csysack;
output biu_pad_rready;
output [127:0] biu_pad_wdata;
output biu_pad_wlast;
output [15 :0] biu_pad_wstrb;
output biu_pad_wvalid;
output [1 :0] core0_pad_jdb_pm;
output [1 :0] core0_pad_lpmd_b;
output [63 :0] core0_pad_mstatus;
output core0_pad_retire0;
output [39 :0] core0_pad_retire0_pc;
output core0_pad_retire1;
output [39 :0] core0_pad_retire1_pc;
output core0_pad_retire2;
output [39 :0] core0_pad_retire2_pc;
output [1 :0] core1_pad_jdb_pm;
output [1 :0] core1_pad_lpmd_b;
output [63 :0] core1_pad_mstatus;
output core1_pad_retire0;
output [39 :0] core1_pad_retire0_pc;
output core1_pad_retire1;
output [39 :0] core1_pad_retire1_pc;
output core1_pad_retire2;
output [39 :0] core1_pad_retire2_pc;
output cpu_debug_port;
output cpu_pad_l2cache_flush_done;
output cpu_pad_no_op;
output had_pad_jtg_tdo;
output had_pad_jtg_tdo_en;
// &Force("input","pll_cpu_clk"); @5
// &Force("input","axim_clk_en"); @6
// &Force("input","pad_cpu_rst_b"); @7
// &Force("input","pad_cpu_apb_base"); &Force("bus","pad_cpu_apb_base",39,0); @8
// &Force("input","pad_cpu_sys_cnt"); &Force("bus","pad_cpu_sys_cnt",63,0); @9
// &Force("input", "pad_cpu_l2cache_flush_req"); @10
// &Force("output","cpu_pad_l2cache_flush_done"); @11
//AXI master IF
// &Force("input","pad_biu_arready"); @14
// &Force("input","pad_biu_awready"); @15
// &Force("input","pad_biu_bid"); &Force("bus","pad_biu_bid",7,0); @16
// &Force("input","pad_biu_bresp"); &Force("bus","pad_biu_bresp", 1,0); @17
// &Force("input","pad_biu_bvalid"); @18
// &Force("input","pad_biu_csysreq"); @19
// &Force("input","pad_biu_rdata"); &Force("bus","pad_biu_rdata",127,0); @20
// &Force("input","pad_biu_rid"); &Force("bus","pad_biu_rid",7,0); @21
// &Force("input","pad_biu_rlast"); @22
// &Force("input","pad_biu_rvalid"); @23
// &Force("input","pad_biu_wready"); @24
// &Force("output", "biu_pad_araddr"); &Force("bus","biu_pad_araddr",39,0); @26
// &Force("output", "biu_pad_arburst"); &Force("bus","biu_pad_arburst",1,0); @27
// &Force("output", "biu_pad_arcache"); &Force("bus","biu_pad_arcache",3,0); @28
// &Force("output", "biu_pad_arid"); &Force("bus","biu_pad_arid",7,0); @29
// &Force("output", "biu_pad_arlen"); &Force("bus","biu_pad_arlen",7,0); @30
// &Force("output", "biu_pad_arlock"); @31
// &Force("output", "biu_pad_arprot"); &Force("bus","biu_pad_arprot",2,0); @32
// &Force("output", "biu_pad_arsize"); &Force("bus","biu_pad_arsize",2,0); @33
// &Force("output", "biu_pad_arvalid"); @34
// &Force("output", "biu_pad_awaddr"); &Force("bus","biu_pad_awaddr",39,0); @35
// &Force("output", "biu_pad_awburst"); &Force("bus","biu_pad_awburst",1,0); @36
// &Force("output", "biu_pad_awcache"); &Force("bus","biu_pad_awcache",3,0); @37
// &Force("output", "biu_pad_awid"); &Force("bus","biu_pad_awid",7,0); @38
// &Force("output", "biu_pad_awlen"); &Force("bus","biu_pad_awlen",7,0); @39
// &Force("output", "biu_pad_awlock"); @40
// &Force("output", "biu_pad_awprot"); &Force("bus","biu_pad_awprot",2,0); @41
// &Force("output", "biu_pad_awsize"); &Force("bus","biu_pad_awsize",2,0); @42
// &Force("output", "biu_pad_awvalid"); @43
// &Force("output", "biu_pad_bready"); @44
// &Force("output", "biu_pad_cactive"); @45
// &Force("output", "biu_pad_csysack"); @46
// &Force("output", "biu_pad_rready"); @47
// &Force("output", "biu_pad_wdata"); &Force("bus","biu_pad_wdata",127,0); @48
// &Force("output", "biu_pad_wlast"); @49
// &Force("output", "biu_pad_wstrb"); &Force("bus","biu_pad_wstrb",15,0); @50
// &Force("output", "biu_pad_wvalid"); @51
// &Force("input","pad_biu_rresp"); &Force("bus","pad_biu_rresp",3,0); @53
// &Force("input", "pad_biu_acaddr"); &Force("bus","pad_biu_acaddr",39,0); @54
// &Force("input", "pad_biu_acprot"); &Force("bus","pad_biu_acprot",2,0); @55
// &Force("input", "pad_biu_acsnoop"); &Force("bus","pad_biu_acsnoop",3,0); @56
// &Force("input", "pad_biu_acvalid"); @57
// &Force("input", "pad_biu_cdready"); @58
// &Force("input", "pad_biu_crready"); @59
// &Force("output", "biu_pad_acready"); @60
// &Force("output", "biu_pad_arbar"); &Force("bus","biu_pad_arbar",1,0); @61
// &Force("output", "biu_pad_ardomain"); &Force("bus","biu_pad_ardomain",1,0); @62
// &Force("output", "biu_pad_arsnoop"); &Force("bus","biu_pad_arsnoop",3,0); @63
// &Force("output", "biu_pad_awbar"); &Force("bus","biu_pad_awbar",1,0); @64
// &Force("output", "biu_pad_awdomain"); &Force("bus","biu_pad_awdomain",1,0); @65
// &Force("output", "biu_pad_awsnoop"); &Force("bus","biu_pad_awsnoop",2,0); @66
// &Force("output", "biu_pad_back"); @67
// &Force("output", "biu_pad_cddata"); &Force("bus","biu_pad_cddata",127,0); @68
// &Force("output", "biu_pad_cdlast"); @69
// &Force("output", "biu_pad_cdvalid"); @70
// &Force("output", "biu_pad_crresp"); &Force("bus","biu_pad_crresp",4,0); @71
// &Force("output", "biu_pad_crvalid"); @72
// &Force("output", "biu_pad_rack"); @73
// &Force("input","pad_biu_rresp"); &Force("bus","pad_biu_rresp",1,0); @75
// &Force("input", "pad_biu_acaddr"); &Force("bus","pad_biu_acaddr",39,0); @77
// &Force("input", "pad_biu_acprot"); &Force("bus","pad_biu_acprot",2,0); @78
// &Force("input", "pad_biu_acsnoop"); &Force("bus","pad_biu_acsnoop",3,0); @79
// &Force("input", "pad_biu_acvalid"); @80
// &Force("input", "pad_biu_cdready"); @81
// &Force("input", "pad_biu_crready"); @82
// &Force("output", "biu_pad_acready"); @83
// &Force("output", "biu_pad_arbar"); &Force("bus","biu_pad_arbar",1,0); @84
// &Force("output", "biu_pad_ardomain"); &Force("bus","biu_pad_ardomain",1,0); @85
// &Force("output", "biu_pad_arsnoop"); &Force("bus","biu_pad_arsnoop",3,0); @86
// &Force("output", "biu_pad_awbar"); &Force("bus","biu_pad_awbar",1,0); @87
// &Force("output", "biu_pad_awdomain"); &Force("bus","biu_pad_awdomain",1,0); @88
// &Force("output", "biu_pad_awsnoop"); &Force("bus","biu_pad_awsnoop",2,0); @89
// &Force("output", "biu_pad_back"); @90
// &Force("output", "biu_pad_cddata"); &Force("bus","biu_pad_cddata",127,0); @91
// &Force("output", "biu_pad_cdlast"); @92
// &Force("output", "biu_pad_cdvalid"); @93
// &Force("output", "biu_pad_crresp"); &Force("bus","biu_pad_crresp",4,0); @94
// &Force("output", "biu_pad_crvalid"); @95
// &Force("output", "biu_pad_rack"); @96
// &Force("input", "slvif_clk_en"); @101
// &Force("input", "pad_slvif_araddr"); &Force("bus","pad_slvif_araddr",39,0); @102
// &Force("input", "pad_slvif_arburst"); &Force("bus","pad_slvif_arburst",1,0); @103
// &Force("input", "pad_slvif_arcache"); &Force("bus","pad_slvif_arcache",3,0); @104
// &Force("input", "pad_slvif_arid"); &Force("bus","pad_slvif_arid",4,0); @105
// &Force("input", "pad_slvif_arlen"); &Force("bus","pad_slvif_arlen",7,0); @106
// &Force("input", "pad_slvif_arlock"); @107
// &Force("input", "pad_slvif_arprot"); &Force("bus","pad_slvif_arprot",2,0); @108
// &Force("input", "pad_slvif_arsize"); &Force("bus","pad_slvif_arsize",2,0); @109
// &Force("input", "pad_slvif_arvalid"); @110
// &Force("input", "pad_slvif_awaddr"); &Force("bus","pad_slvif_awaddr",39,0); @111
// &Force("input", "pad_slvif_awburst"); &Force("bus","pad_slvif_awburst",1,0); @112
// &Force("input", "pad_slvif_awcache"); &Force("bus","pad_slvif_awcache",3,0); @113
// &Force("input", "pad_slvif_awid"); &Force("bus","pad_slvif_awid",4,0); @114
// &Force("input", "pad_slvif_awlen"); &Force("bus","pad_slvif_awlen",7,0); @115
// &Force("input", "pad_slvif_awlock"); @116
// &Force("input", "pad_slvif_awprot"); &Force("bus","pad_slvif_awprot",2,0); @117
// &Force("input", "pad_slvif_awsize"); &Force("bus","pad_slvif_awsize",2,0); @118
// &Force("input", "pad_slvif_awvalid"); @119
// &Force("input", "pad_slvif_bready"); @120
// &Force("input", "pad_slvif_rready"); @121
// &Force("input", "pad_slvif_wdata"); &Force("bus","pad_slvif_wdata",127,0); @122
// &Force("input", "pad_slvif_wlast"); @123
// &Force("input", "pad_slvif_wstrb"); &Force("bus","pad_slvif_wstrb",15,0); @124
// &Force("input", "pad_slvif_wvalid"); @125
// &Force("output","slvif_pad_arready"); @127
// &Force("output","slvif_pad_awready"); @128
// &Force("output","slvif_pad_bid"); &Force("bus","slvif_pad_bid",4,0); @129
// &Force("output","slvif_pad_bresp"); &Force("bus","slvif_pad_bresp", 1,0); @130
// &Force("output","slvif_pad_bvalid"); @131
// &Force("output","slvif_pad_rdata"); &Force("bus","slvif_pad_rdata",127,0); @132
// &Force("output","slvif_pad_rid"); &Force("bus","slvif_pad_rid",4,0); @133
// &Force("output","slvif_pad_rlast"); @134
// &Force("output","slvif_pad_rresp"); &Force("bus","slvif_pad_rresp",1,0); @135
// &Force("output","slvif_pad_rvalid"); @136
// &Force("output","slvif_pad_wready"); @137
//HAD
// &Force("input", "pad_had_jtg_tclk"); @141
// &Force("input", "pad_had_jtg_trst_b"); @142
// &Force("input", "pad_had_jtg_tdi"); @143
// &Force("input", "pad_had_jtg_tms"); @144
// &Force("output", "had_pad_jtg_tdo"); @146
// &Force("output", "had_pad_jtg_tdo_en"); @147
// &Force("input", "pad_cpu_tee_dbg_disable"); &Force("bus","pad_cpu_tee_dbg_disable",7,0); @150
// &Force("input", "pad_cpu_ree_dbg_disable"); &Force("bus","pad_cpu_ree_dbg_disable",7,0); @151
//mbist
// &Force("input", "pad_yy_mbist_mode"); @155
// &Force("input", "pad_yy_dft_clk_rst_b"); @156
// &Force("input", "pad_l2c_data_mbist_clk_ratio"); &Force("bus", "pad_l2c_data_mbist_clk_ratio",2,0); @157
// &Force("input", "pad_l2c_tag_mbist_clk_ratio"); &Force("bus", "pad_l2c_tag_mbist_clk_ratio",2,0); @158
//scan
// &Force("input", "pad_yy_icg_scan_en"); @161
// &Force("input", "pad_yy_scan_mode"); @162
// &Force("input", "pad_yy_scan_enable"); @163
// &Force("input", "pad_yy_scan_rst_b"); @164
// &Force("output", "cpu_pad_no_op"); @165
// &Force("input","pad_plic_int_vld"); @168
// &Force("bus","pad_plic_int_vld",`PLIC_INT_NUM-1,0); @169
// &Force("input","pad_plic_int_cfg"); @170
// &Force("bus","pad_plic_int_cfg",`PLIC_INT_NUM-1,0); @171
// &Force("input","pad_cpu_mint_req"); @173
// &Force("bus","pad_cpu_mint_req",`HART_NUM-1,0); @174
// &Force("bus","pad_cpu_sint_req",`HART_NUM-1,0); @175
// &Force("input","pad_cpu_sint_req"); @176
// &Force("output", "cpu_debug_port"); @180
// &Force("input", "pll_core0_clk"); @185
// &Force("input", "pad_core0_async_mode"); @186
// &Force("input", "pad_core0_dbgrq_b"); @188
// &Force("input", "pad_core0_rst_b"); @191
// &Force("input", "pad_core0_rvba"); &Force("bus","pad_core0_rvba",39,0); @192
// &Force("input", "pad_core0_hartid"); &Force("bus","pad_core0_hartid",2,0); @194
// &Force("input", "pad_core0_dbg_mask"); @195
// &Force("output", "core0_pad_jdb_pm"); &Force("bus","core0_pad_jdb_pm",1,0); @196
// &Force("output", "core0_pad_lpmd_b"); &Force("bus","core0_pad_lpmd_b",1,0); @197
// &Force("output", "core0_pad_retire0"); @198
// &Force("output", "core0_pad_retire0_pc"); &Force("bus","core0_pad_retire0_pc",39,0); @199
// &Force("output", "core0_pad_retire1"); @200
// &Force("output", "core0_pad_retire1_pc"); &Force("bus","core0_pad_retire1_pc",39,0); @201
// &Force("output", "core0_pad_retire2"); @202
// &Force("output", "core0_pad_retire2_pc"); &Force("bus","core0_pad_retire2_pc",39,0); @203
// &Force("output", "core0_pad_mstatus"); &Force("bus","core0_pad_mstatus",63,0); @204
// &Force("input", "pll_core1_clk"); @209
// &Force("input", "pad_core1_async_mode"); @210
// &Force("input", "pad_core1_dbgrq_b"); @212
// &Force("input", "pad_core1_rst_b"); @215
// &Force("input", "pad_core1_rvba"); &Force("bus","pad_core1_rvba",39,0); @216
// &Force("input", "pad_core1_hartid"); &Force("bus","pad_core1_hartid",2,0); @218
// &Force("input", "pad_core1_dbg_mask"); @219
// &Force("output", "core1_pad_jdb_pm"); &Force("bus","core1_pad_jdb_pm",1,0); @220
// &Force("output", "core1_pad_lpmd_b"); &Force("bus","core1_pad_lpmd_b",1,0); @221
// &Force("output", "core1_pad_retire0"); @222
// &Force("output", "core1_pad_retire0_pc"); &Force("bus","core1_pad_retire0_pc",39,0); @223
// &Force("output", "core1_pad_retire1"); @224
// &Force("output", "core1_pad_retire1_pc"); &Force("bus","core1_pad_retire1_pc",39,0); @225
// &Force("output", "core1_pad_retire2"); @226
// &Force("output", "core1_pad_retire2_pc"); &Force("bus","core1_pad_retire2_pc",39,0); @227
// &Force("output", "core1_pad_mstatus"); &Force("bus","core1_pad_mstatus",63,0); @228
// &Force("input", "pll_core2_clk"); @233
// &Force("input", "pad_core2_async_mode"); @234
// &Force("input", "pad_core2_dbgrq_b"); @236
// &Force("input", "pad_core2_rst_b"); @239
// &Force("input", "pad_core2_rvba"); &Force("bus","pad_core2_rvba",39,0); @240
// &Force("input", "pad_core2_hartid"); &Force("bus","pad_core2_hartid",2,0); @242
// &Force("input", "pad_core2_dbg_mask"); @243
// &Force("output", "core2_pad_jdb_pm"); &Force("bus","core2_pad_jdb_pm",1,0); @244
// &Force("output", "core2_pad_lpmd_b"); &Force("bus","core2_pad_lpmd_b",1,0); @245
// &Force("output", "core2_pad_retire0"); @246
// &Force("output", "core2_pad_retire0_pc"); &Force("bus","core2_pad_retire0_pc",39,0); @247
// &Force("output", "core2_pad_retire1"); @248
// &Force("output", "core2_pad_retire1_pc"); &Force("bus","core2_pad_retire1_pc",39,0); @249
// &Force("output", "core2_pad_retire2"); @250
// &Force("output", "core2_pad_retire2_pc"); &Force("bus","core2_pad_retire2_pc",39,0); @251
// &Force("output", "core2_pad_mstatus"); &Force("bus","core2_pad_mstatus",63,0); @252
// &Force("input", "pll_core3_clk"); @257
// &Force("input", "pad_core3_async_mode"); @258
// &Force("input", "pad_core3_dbgrq_b"); @260
// &Force("input", "pad_core3_rst_b"); @263
// &Force("input", "pad_core3_rvba"); &Force("bus","pad_core3_rvba",39,0); @264
// &Force("input", "pad_core3_hartid"); &Force("bus","pad_core3_hartid",2,0); @266
// &Force("input", "pad_core3_dbg_mask"); @267
// &Force("output", "core3_pad_jdb_pm"); &Force("bus","core3_pad_jdb_pm",1,0); @268
// &Force("output", "core3_pad_lpmd_b"); &Force("bus","core3_pad_lpmd_b",1,0); @269
// &Force("output", "core3_pad_retire0"); @270
// &Force("output", "core3_pad_retire0_pc"); &Force("bus","core3_pad_retire0_pc",39,0); @271
// &Force("output", "core3_pad_retire1"); @272
// &Force("output", "core3_pad_retire1_pc"); &Force("bus","core3_pad_retire1_pc",39,0); @273
// &Force("output", "core3_pad_retire2"); @274
// &Force("output", "core3_pad_retire2_pc"); &Force("bus","core3_pad_retire2_pc",39,0); @275
// &Force("output", "core3_pad_mstatus"); &Force("bus","core3_pad_mstatus",63,0); @276
// &Force("output","core0_pad_tee_violation"); @281
// &Force("output","core0_pad_par_violation"); &Force("bus","core0_pad_par_violation",4,0); @282
// &Force("output","core0_pad_tee_mode"); &Force("bus", "core0_pad_tee_mode", 7,0); @283
// &Force("output","core1_pad_tee_violation"); @286
// &Force("output","core1_pad_par_violation"); &Force("bus","core1_pad_par_violation",4,0); @287
// &Force("output","core1_pad_tee_mode"); &Force("bus", "core1_pad_tee_mode", 7,0); @288
// &Force("output","core2_pad_tee_violation"); @291
// &Force("output","core2_pad_par_violation"); &Force("bus","core2_pad_par_violation",4,0); @292
// &Force("output","core2_pad_tee_mode"); &Force("bus", "core2_pad_tee_mode", 7,0); @293
// &Force("output","core3_pad_tee_violation"); @296
// &Force("output","core3_pad_par_violation"); &Force("bus","core3_pad_par_violation",4,0); @297
// &Force("output","core3_pad_tee_mode"); &Force("bus", "core3_pad_tee_mode", 7,0); @298
// &Force("input","pad_cpu_mem_cfg_in"); &Force("bus","pad_cpu_mem_cfg_in",`MEM_CFG_IN_WIDTH-1,0); @304
// &Force("input","pad_core0_mem_cfg_in"); &Force("bus","pad_core0_mem_cfg_in",`MEM_CFG_IN_WIDTH-1,0); @306
// &Force("input","pad_core1_mem_cfg_in"); &Force("bus","pad_core1_mem_cfg_in",`MEM_CFG_IN_WIDTH-1,0); @309
// &Force("input","pad_core2_mem_cfg_in"); &Force("bus","pad_core2_mem_cfg_in",`MEM_CFG_IN_WIDTH-1,0); @312
// &Force("input","pad_core3_mem_cfg_in"); &Force("bus","pad_core3_mem_cfg_in",`MEM_CFG_IN_WIDTH-1,0); @315
// &Force("input", "pad_cpu_sleep_in"); @320
// &Force("output", "cpu_pad_sleep_out"); @321
// &Force("input", "pad_core0_iso_en"); @323
// &Force("input", "pad_core0_sleep_in"); @324
// &Force("output", "core0_pad_sleep_out"); @325
// &Force("input", "pad_core1_iso_en"); @328
// &Force("input", "pad_core1_sleep_in"); @329
// &Force("output","core1_pad_sleep_out"); @330
// &Force("input", "pad_core2_iso_en"); @333
// &Force("input", "pad_core2_sleep_in"); @334
// &Force("output","core2_pad_sleep_out"); @335
// &Force("input", "pad_core3_iso_en"); @338
// &Force("input", "pad_core3_sleep_in"); @339
// &Force("output","core3_pad_sleep_out"); @340
//==============================================================================
// FOR_VERIFICATION
//==============================================================================
// &Force("output", "biu_pad_verf_arid"); &Force("bus","biu_pad_verf_arid",10,0); @347
// &Force("output", "biu_pad_verf_awid"); &Force("bus","biu_pad_verf_awid",10,0); @348
// &Force("output", "biu_pad_verf_wid"); &Force("bus","biu_pad_verf_wid",11,0); @349
// &Force("output", "biu_pad_verf_arsid"); &Force("bus","biu_pad_verf_arsid",6,0); @350
// &Force("output", "biu_pad_verf_awsid"); &Force("bus","biu_pad_verf_awsid",6,0); @351
// &Force("output", "biu_pad_verf_wsid"); &Force("bus","biu_pad_verf_wsid",6,0); @352
// &Force("output", "ciu_l2c_axid_bank_0"); &Force("bus","ciu_l2c_axid_bank_0",10,0); @353
// &Force("output", "ciu_l2c_axid_bank_1"); &Force("bus","ciu_l2c_axid_bank_1",10,0); @354
// &Force("output", "ciu_l2c_verf_type_bank_0"); &Force("bus","ciu_l2c_verf_type_bank_0",1,0); @355
// &Force("output", "ciu_l2c_verf_type_bank_1"); &Force("bus","ciu_l2c_verf_type_bank_1",1,0); @356
// &Force("output", "snb0_verf_sab_pop_en"); &Force("bus","snb0_verf_sab_pop_en",23,0); @357
// &Force("output", "snb1_verf_sab_pop_en"); &Force("bus","snb1_verf_sab_pop_en",23,0); @358
// &Force("output","pad_ibiu0_ac_verf_bus"); &Force("bus","pad_ibiu0_ac_verf_bus",10,0); @360
// &Force("output", "ibiu0_pad_ref_cache_awaddr"); &Force("bus","ibiu0_pad_ref_cache_awaddr",39,0); @361
// &Force("output", "ibiu0_pad_ref_cache_awsize"); &Force("bus","ibiu0_pad_ref_cache_awsize",2,0); @362
// &Force("output", "ibiu0_pad_ref_cache_awvalid"); @363
// &Force("output", "ibiu0_pad_ref_cache_wdata"); &Force("bus","ibiu0_pad_ref_cache_wdata",127,0); @364
// &Force("output", "ibiu0_pad_ref_cache_wstrb"); &Force("bus","ibiu0_pad_ref_cache_wstrb",15,0); @365
// &Force("output", "ibiu0_pad_ref_pfu_ar_sel"); @366
// &Force("output","pad_ibiu1_ac_verf_bus"); &Force("bus","pad_ibiu1_ac_verf_bus",10,0); @369
// &Force("output", "ibiu1_pad_ref_cache_awaddr"); &Force("bus","ibiu1_pad_ref_cache_awaddr",39,0); @370
// &Force("output", "ibiu1_pad_ref_cache_awsize"); &Force("bus","ibiu1_pad_ref_cache_awsize",2,0); @371
// &Force("output", "ibiu1_pad_ref_cache_awvalid"); @372
// &Force("output", "ibiu1_pad_ref_cache_wdata"); &Force("bus","ibiu1_pad_ref_cache_wdata",127,0); @373
// &Force("output", "ibiu1_pad_ref_cache_wstrb"); &Force("bus","ibiu1_pad_ref_cache_wstrb",15,0); @374
// &Force("output", "ibiu1_pad_ref_pfu_ar_sel"); @375
// &Force("output","pad_ibiu2_ac_verf_bus"); &Force("bus","pad_ibiu2_ac_verf_bus",10,0); @378
// &Force("output", "ibiu2_pad_ref_cache_awaddr"); &Force("bus","ibiu2_pad_ref_cache_awaddr",39,0); @379
// &Force("output", "ibiu2_pad_ref_cache_awsize"); &Force("bus","ibiu2_pad_ref_cache_awsize",2,0); @380
// &Force("output", "ibiu2_pad_ref_cache_awvalid"); @381
// &Force("output", "ibiu2_pad_ref_cache_wdata"); &Force("bus","ibiu2_pad_ref_cache_wdata",127,0); @382
// &Force("output", "ibiu2_pad_ref_cache_wstrb"); &Force("bus","ibiu2_pad_ref_cache_wstrb",15,0); @383
// &Force("output", "ibiu2_pad_ref_pfu_ar_sel"); @384
// &Force("output","pad_ibiu3_ac_verf_bus"); &Force("bus","pad_ibiu3_ac_verf_bus",10,0); @387
// &Force("output", "ibiu3_pad_ref_cache_awaddr"); &Force("bus","ibiu3_pad_ref_cache_awaddr",39,0); @388
// &Force("output", "ibiu3_pad_ref_cache_awsize"); &Force("bus","ibiu3_pad_ref_cache_awsize",2,0); @389
// &Force("output", "ibiu3_pad_ref_cache_awvalid"); @390
// &Force("output", "ibiu3_pad_ref_cache_wdata"); &Force("bus","ibiu3_pad_ref_cache_wdata",127,0); @391
// &Force("output", "ibiu3_pad_ref_cache_wstrb"); &Force("bus","ibiu3_pad_ref_cache_wstrb",15,0); @392
// &Force("output", "ibiu3_pad_ref_pfu_ar_sel"); @393
//for ISA
// &Force("output", "core0_pad_dispatch_info"); @402
// &Force("output", "core0_pad_dispatch0_info"); &Force("bus","core0_pad_dispatch0_info",78,0); @403
// &Force("output", "core0_pad_dispatch1_info"); &Force("bus","core0_pad_dispatch1_info",78,0); @404
// &Force("output", "core0_pad_dispatch2_info"); &Force("bus","core0_pad_dispatch2_info",78,0); @405
// &Force("output", "core0_pad_dispatch3_info"); &Force("bus","core0_pad_dispatch3_info",78,0); @406
// &Force("output", "core0_pad_flush"); @407
// &Force("output", "core0_pad_retire0_iid"); &Force("bus","core0_pad_retire0_iid",6,0); @408
// &Force("output", "core0_pad_retire1_iid"); &Force("bus","core0_pad_retire1_iid",6,0); @409
// &Force("output", "core0_pad_retire2_iid"); &Force("bus","core0_pad_retire2_iid",6,0); @410
// &Force("output", "core0_pad_wb0_vld"); @411
// &Force("output", "core0_pad_wb0_preg"); &Force("bus","core0_pad_wb0_preg",6,0); @412
// &Force("output", "core0_pad_wb0_data"); &Force("bus","core0_pad_wb0_data",63,0); @413
// &Force("output", "core0_pad_wb0_freg_vld"); @414
// &Force("output", "core0_pad_wb0_freg"); &Force("bus","core0_pad_wb0_freg",6,0); @415
// &Force("output", "core0_pad_wb0_fdata"); &Force("bus","core0_pad_wb0_fdata",63,0); @416
// &Force("output", "core0_pad_wb0_vreg_vld"); @417
// &Force("output", "core0_pad_wb0_vreg"); &Force("bus","core0_pad_wb0_vreg",6,0); @418
// &Force("output", "core0_pad_wb0_vdata"); &Force("bus","core0_pad_wb0_vdata",127,0); @419
// &Force("output", "core0_pad_wb0_ereg_vld"); @420
// &Force("output", "core0_pad_wb0_ereg"); &Force("bus","core0_pad_wb0_ereg",4,0); @421
// &Force("output", "core0_pad_wb0_edata"); &Force("bus","core0_pad_wb0_edata",5,0); @422
// &Force("output", "core0_pad_wb1_vld"); @423
// &Force("output", "core0_pad_wb1_preg"); &Force("bus","core0_pad_wb1_preg",6,0); @424
// &Force("output", "core0_pad_wb1_data"); &Force("bus","core0_pad_wb1_data",63,0); @425
// &Force("output", "core0_pad_wb1_freg_vld"); @426
// &Force("output", "core0_pad_wb1_freg"); &Force("bus","core0_pad_wb1_freg",6,0); @427
// &Force("output", "core0_pad_wb1_fdata"); &Force("bus","core0_pad_wb1_fdata",63,0); @428
// &Force("output", "core0_pad_wb1_vreg_vld"); @429
// &Force("output", "core0_pad_wb1_vreg"); &Force("bus","core0_pad_wb1_vreg",6,0); @430
// &Force("output", "core0_pad_wb1_vdata"); &Force("bus","core0_pad_wb1_vdata",127,0); @431
// &Force("output", "core0_pad_wb1_ereg_vld"); @432
// &Force("output", "core0_pad_wb1_ereg"); &Force("bus","core0_pad_wb1_ereg",4,0); @433
// &Force("output", "core0_pad_wb1_edata"); &Force("bus","core0_pad_wb1_edata",5,0); @434
// &Force("output", "core0_pad_wb2_vld"); @435
// &Force("output", "core0_pad_wb2_preg"); &Force("bus","core0_pad_wb2_preg",6,0); @436
// &Force("output", "core0_pad_wb2_data"); &Force("bus","core0_pad_wb2_data",63,0); @437
// &Force("output", "core0_pad_wb2_freg_vld"); @438
// &Force("output", "core0_pad_wb2_freg"); &Force("bus","core0_pad_wb2_freg",6,0); @439
// &Force("output", "core0_pad_wb2_fdata"); &Force("bus","core0_pad_wb2_fdata",63,0); @440
// &Force("output", "core0_pad_wb2_vreg_vld"); @441
// &Force("output", "core0_pad_wb2_vreg"); &Force("bus","core0_pad_wb2_vreg",6,0); @442
// &Force("output", "core0_pad_wb2_vdata"); &Force("bus","core0_pad_wb2_vdata",127,0); @443
// &Force("output", "core1_pad_dispatch_info"); @446
// &Force("output", "core1_pad_dispatch0_info"); &Force("bus","core1_pad_dispatch0_info",78,0); @447
// &Force("output", "core1_pad_dispatch1_info"); &Force("bus","core1_pad_dispatch1_info",78,0); @448
// &Force("output", "core1_pad_dispatch2_info"); &Force("bus","core1_pad_dispatch2_info",78,0); @449
// &Force("output", "core1_pad_dispatch3_info"); &Force("bus","core1_pad_dispatch3_info",78,0); @450
// &Force("output", "core1_pad_flush"); @451
// &Force("output", "core1_pad_retire0_iid"); &Force("bus","core1_pad_retire0_iid",6,0); @452
// &Force("output", "core1_pad_retire1_iid"); &Force("bus","core1_pad_retire1_iid",6,0); @453
// &Force("output", "core1_pad_retire2_iid"); &Force("bus","core1_pad_retire2_iid",6,0); @454
// &Force("output", "core1_pad_wb0_vld"); @455
// &Force("output", "core1_pad_wb0_preg"); &Force("bus","core1_pad_wb0_preg",6,0); @456
// &Force("output", "core1_pad_wb0_data"); &Force("bus","core1_pad_wb0_data",63,0); @457
// &Force("output", "core1_pad_wb0_freg_vld"); @458
// &Force("output", "core1_pad_wb0_freg"); &Force("bus","core1_pad_wb0_freg",6,0); @459
// &Force("output", "core1_pad_wb0_fdata"); &Force("bus","core1_pad_wb0_fdata",63,0); @460
// &Force("output", "core1_pad_wb0_vreg_vld"); @461
// &Force("output", "core1_pad_wb0_vreg"); &Force("bus","core1_pad_wb0_vreg",6,0); @462
// &Force("output", "core1_pad_wb0_vdata"); &Force("bus","core1_pad_wb0_vdata",127,0); @463
// &Force("output", "core1_pad_wb0_ereg_vld"); @464
// &Force("output", "core1_pad_wb0_ereg"); &Force("bus","core1_pad_wb0_ereg",4,0); @465
// &Force("output", "core1_pad_wb0_edata"); &Force("bus","core1_pad_wb0_edata",5,0); @466
// &Force("output", "core1_pad_wb1_vld"); @467
// &Force("output", "core1_pad_wb1_preg"); &Force("bus","core1_pad_wb1_preg",6,0); @468
// &Force("output", "core1_pad_wb1_data"); &Force("bus","core1_pad_wb1_data",63,0); @469
// &Force("output", "core1_pad_wb1_freg_vld"); @470
// &Force("output", "core1_pad_wb1_freg"); &Force("bus","core1_pad_wb1_freg",6,0); @471
// &Force("output", "core1_pad_wb1_fdata"); &Force("bus","core1_pad_wb1_fdata",63,0); @472
// &Force("output", "core1_pad_wb1_vreg_vld"); @473
// &Force("output", "core1_pad_wb1_vreg"); &Force("bus","core1_pad_wb1_vreg",6,0); @474
// &Force("output", "core1_pad_wb1_vdata"); &Force("bus","core1_pad_wb1_vdata",127,0); @475
// &Force("output", "core1_pad_wb1_ereg_vld"); @476
// &Force("output", "core1_pad_wb1_ereg"); &Force("bus","core1_pad_wb1_ereg",4,0); @477
// &Force("output", "core1_pad_wb1_edata"); &Force("bus","core1_pad_wb1_edata",5,0); @478
// &Force("output", "core1_pad_wb2_vld"); @479
// &Force("output", "core1_pad_wb2_preg"); &Force("bus","core1_pad_wb2_preg",6,0); @480
// &Force("output", "core1_pad_wb2_data"); &Force("bus","core1_pad_wb2_data",63,0); @481
// &Force("output", "core1_pad_wb2_freg_vld"); @482
// &Force("output", "core1_pad_wb2_freg"); &Force("bus","core1_pad_wb2_freg",6,0); @483
// &Force("output", "core1_pad_wb2_fdata"); &Force("bus","core1_pad_wb2_fdata",63,0); @484
// &Force("output", "core1_pad_wb2_vreg_vld"); @485
// &Force("output", "core1_pad_wb2_vreg"); &Force("bus","core1_pad_wb2_vreg",6,0); @486
// &Force("output", "core1_pad_wb2_vdata"); &Force("bus","core1_pad_wb2_vdata",127,0); @487
// &Force("output", "core2_pad_dispatch_info"); @490
// &Force("output", "core2_pad_dispatch0_info"); &Force("bus","core2_pad_dispatch0_info",78,0); @491
// &Force("output", "core2_pad_dispatch1_info"); &Force("bus","core2_pad_dispatch1_info",78,0); @492
// &Force("output", "core2_pad_dispatch2_info"); &Force("bus","core2_pad_dispatch2_info",78,0); @493
// &Force("output", "core2_pad_dispatch3_info"); &Force("bus","core2_pad_dispatch3_info",78,0); @494
// &Force("output", "core2_pad_flush"); @495
// &Force("output", "core2_pad_retire0_iid"); &Force("bus","core2_pad_retire0_iid",6,0); @496
// &Force("output", "core2_pad_retire1_iid"); &Force("bus","core2_pad_retire1_iid",6,0); @497
// &Force("output", "core2_pad_retire2_iid"); &Force("bus","core2_pad_retire2_iid",6,0); @498
// &Force("output", "core2_pad_wb0_vld"); @499
// &Force("output", "core2_pad_wb0_preg"); &Force("bus","core2_pad_wb0_preg",6,0); @500
// &Force("output", "core2_pad_wb0_data"); &Force("bus","core2_pad_wb0_data",63,0); @501
// &Force("output", "core2_pad_wb0_freg_vld"); @502
// &Force("output", "core2_pad_wb0_freg"); &Force("bus","core2_pad_wb0_freg",6,0); @503
// &Force("output", "core2_pad_wb0_fdata"); &Force("bus","core2_pad_wb0_fdata",63,0); @504
// &Force("output", "core2_pad_wb0_vreg_vld"); @505
// &Force("output", "core2_pad_wb0_vreg"); &Force("bus","core2_pad_wb0_vreg",6,0); @506
// &Force("output", "core2_pad_wb0_vdata"); &Force("bus","core2_pad_wb0_vdata",127,0); @507
// &Force("output", "core2_pad_wb0_ereg_vld"); @508
// &Force("output", "core2_pad_wb0_ereg"); &Force("bus","core2_pad_wb0_ereg",4,0); @509
// &Force("output", "core2_pad_wb0_edata"); &Force("bus","core2_pad_wb0_edata",5,0); @510
// &Force("output", "core2_pad_wb1_vld"); @511
// &Force("output", "core2_pad_wb1_preg"); &Force("bus","core2_pad_wb1_preg",6,0); @512
// &Force("output", "core2_pad_wb1_data"); &Force("bus","core2_pad_wb1_data",63,0); @513
// &Force("output", "core2_pad_wb1_freg_vld"); @514
// &Force("output", "core2_pad_wb1_freg"); &Force("bus","core2_pad_wb1_freg",6,0); @515
// &Force("output", "core2_pad_wb1_fdata"); &Force("bus","core2_pad_wb1_fdata",63,0); @516
// &Force("output", "core2_pad_wb1_vreg_vld"); @517
// &Force("output", "core2_pad_wb1_vreg"); &Force("bus","core2_pad_wb1_vreg",6,0); @518
// &Force("output", "core2_pad_wb1_vdata"); &Force("bus","core2_pad_wb1_vdata",127,0); @519
// &Force("output", "core2_pad_wb1_ereg_vld"); @520
// &Force("output", "core2_pad_wb1_ereg"); &Force("bus","core2_pad_wb1_ereg",4,0); @521
// &Force("output", "core2_pad_wb1_edata"); &Force("bus","core2_pad_wb1_edata",5,0); @522
// &Force("output", "core2_pad_wb2_vld"); @523
// &Force("output", "core2_pad_wb2_preg"); &Force("bus","core2_pad_wb2_preg",6,0); @524
// &Force("output", "core2_pad_wb2_data"); &Force("bus","core2_pad_wb2_data",63,0); @525
// &Force("output", "core2_pad_wb2_freg_vld"); @526
// &Force("output", "core2_pad_wb2_freg"); &Force("bus","core2_pad_wb2_freg",6,0); @527
// &Force("output", "core2_pad_wb2_fdata"); &Force("bus","core2_pad_wb2_fdata",63,0); @528
// &Force("output", "core2_pad_wb2_vreg_vld"); @529
// &Force("output", "core2_pad_wb2_vreg"); &Force("bus","core2_pad_wb2_vreg",6,0); @530
// &Force("output", "core2_pad_wb2_vdata"); &Force("bus","core2_pad_wb2_vdata",127,0); @531
// &Force("output", "core3_pad_dispatch_info"); @534
// &Force("output", "core3_pad_dispatch0_info"); &Force("bus","core3_pad_dispatch0_info",78,0); @535
// &Force("output", "core3_pad_dispatch1_info"); &Force("bus","core3_pad_dispatch1_info",78,0); @536
// &Force("output", "core3_pad_dispatch2_info"); &Force("bus","core3_pad_dispatch2_info",78,0); @537
// &Force("output", "core3_pad_dispatch3_info"); &Force("bus","core3_pad_dispatch3_info",78,0); @538
// &Force("output", "core3_pad_flush"); @539
// &Force("output", "core3_pad_retire0_iid"); &Force("bus","core3_pad_retire0_iid",6,0); @540
// &Force("output", "core3_pad_retire1_iid"); &Force("bus","core3_pad_retire1_iid",6,0); @541
// &Force("output", "core3_pad_retire2_iid"); &Force("bus","core3_pad_retire2_iid",6,0); @542
// &Force("output", "core3_pad_wb0_vld"); @543
// &Force("output", "core3_pad_wb0_preg"); &Force("bus","core3_pad_wb0_preg",6,0); @544
// &Force("output", "core3_pad_wb0_data"); &Force("bus","core3_pad_wb0_data",63,0); @545
// &Force("output", "core3_pad_wb0_freg_vld"); @546
// &Force("output", "core3_pad_wb0_freg"); &Force("bus","core3_pad_wb0_freg",6,0); @547
// &Force("output", "core3_pad_wb0_fdata"); &Force("bus","core3_pad_wb0_fdata",63,0); @548
// &Force("output", "core3_pad_wb0_vreg_vld"); @549
// &Force("output", "core3_pad_wb0_vreg"); &Force("bus","core3_pad_wb0_vreg",6,0); @550
// &Force("output", "core3_pad_wb0_vdata"); &Force("bus","core3_pad_wb0_vdata",127,0); @551
// &Force("output", "core3_pad_wb0_ereg_vld"); @552
// &Force("output", "core3_pad_wb0_ereg"); &Force("bus","core3_pad_wb0_ereg",4,0); @553
// &Force("output", "core3_pad_wb0_edata"); &Force("bus","core3_pad_wb0_edata",5,0); @554
// &Force("output", "core3_pad_wb1_vld"); @555
// &Force("output", "core3_pad_wb1_preg"); &Force("bus","core3_pad_wb1_preg",6,0); @556
// &Force("output", "core3_pad_wb1_data"); &Force("bus","core3_pad_wb1_data",63,0); @557
// &Force("output", "core3_pad_wb1_freg_vld"); @558
// &Force("output", "core3_pad_wb1_freg"); &Force("bus","core3_pad_wb1_freg",6,0); @559
// &Force("output", "core3_pad_wb1_fdata"); &Force("bus","core3_pad_wb1_fdata",63,0); @560
// &Force("output", "core3_pad_wb1_vreg_vld"); @561
// &Force("output", "core3_pad_wb1_vreg"); &Force("bus","core3_pad_wb1_vreg",6,0); @562
// &Force("output", "core3_pad_wb1_vdata"); &Force("bus","core3_pad_wb1_vdata",127,0); @563
// &Force("output", "core3_pad_wb1_ereg_vld"); @564
// &Force("output", "core3_pad_wb1_ereg"); &Force("bus","core3_pad_wb1_ereg",4,0); @565
// &Force("output", "core3_pad_wb1_edata"); &Force("bus","core3_pad_wb1_edata",5,0); @566
// &Force("output", "core3_pad_wb2_vld"); @567
// &Force("output", "core3_pad_wb2_preg"); &Force("bus","core3_pad_wb2_preg",6,0); @568
// &Force("output", "core3_pad_wb2_data"); &Force("bus","core3_pad_wb2_data",63,0); @569
// &Force("output", "core3_pad_wb2_freg_vld"); @570
// &Force("output", "core3_pad_wb2_freg"); &Force("bus","core3_pad_wb2_freg",6,0); @571
// &Force("output", "core3_pad_wb2_fdata"); &Force("bus","core3_pad_wb2_fdata",63,0); @572
// &Force("output", "core3_pad_wb2_vreg_vld"); @573
// &Force("output", "core3_pad_wb2_vreg"); &Force("bus","core3_pad_wb2_vreg",6,0); @574
// &Force("output", "core3_pad_wb2_vdata"); &Force("bus","core3_pad_wb2_vdata",127,0); @575
// &ModuleEnd; @578
endmodule |
module ct_sysio_top(
apb_clk_en,
axim_clk_en,
ciu_sysio_icg_en,
ciu_xx_no_op,
clint_core0_ms_int,
clint_core0_mt_int,
clint_core0_ss_int,
clint_core0_st_int,
clint_core1_ms_int,
clint_core1_mt_int,
clint_core1_ss_int,
clint_core1_st_int,
core0_pad_jdb_pm,
core0_pad_lpmd_b,
core1_pad_jdb_pm,
core1_pad_lpmd_b,
cpu_pad_l2cache_flush_done,
cpu_pad_no_op,
cpurst_b,
forever_cpuclk,
l2c_sysio_flush_done,
l2c_sysio_flush_idle,
pad_core0_dbg_mask,
pad_core0_dbgrq_b,
pad_core1_dbg_mask,
pad_core1_dbgrq_b,
pad_cpu_apb_base,
pad_cpu_l2cache_flush_req,
pad_cpu_sys_cnt,
pad_yy_icg_scan_en,
piu0_sysio_jdb_pm,
piu0_sysio_lpmd_b,
piu1_sysio_jdb_pm,
piu1_sysio_lpmd_b,
plic_core0_me_int,
plic_core0_se_int,
plic_core1_me_int,
plic_core1_se_int,
sysio_ciu_apb_base,
sysio_clint_mtime,
sysio_had_dbg_mask,
sysio_l2c_flush_req,
sysio_piu0_dbgrq_b,
sysio_piu0_me_int,
sysio_piu0_ms_int,
sysio_piu0_mt_int,
sysio_piu0_se_int,
sysio_piu0_ss_int,
sysio_piu0_st_int,
sysio_piu1_dbgrq_b,
sysio_piu1_me_int,
sysio_piu1_ms_int,
sysio_piu1_mt_int,
sysio_piu1_se_int,
sysio_piu1_ss_int,
sysio_piu1_st_int,
sysio_xx_apb_base,
sysio_xx_time
);
// &Ports; @25
input apb_clk_en;
input axim_clk_en;
input ciu_sysio_icg_en;
input ciu_xx_no_op;
input clint_core0_ms_int;
input clint_core0_mt_int;
input clint_core0_ss_int;
input clint_core0_st_int;
input clint_core1_ms_int;
input clint_core1_mt_int;
input clint_core1_ss_int;
input clint_core1_st_int;
input cpurst_b;
input forever_cpuclk;
input l2c_sysio_flush_done;
input l2c_sysio_flush_idle;
input pad_core0_dbg_mask;
input pad_core0_dbgrq_b;
input pad_core1_dbg_mask;
input pad_core1_dbgrq_b;
input [39:0] pad_cpu_apb_base;
input pad_cpu_l2cache_flush_req;
input [63:0] pad_cpu_sys_cnt;
input pad_yy_icg_scan_en;
input [1 :0] piu0_sysio_jdb_pm;
input [1 :0] piu0_sysio_lpmd_b;
input [1 :0] piu1_sysio_jdb_pm;
input [1 :0] piu1_sysio_lpmd_b;
input plic_core0_me_int;
input plic_core0_se_int;
input plic_core1_me_int;
input plic_core1_se_int;
output [1 :0] core0_pad_jdb_pm;
output [1 :0] core0_pad_lpmd_b;
output [1 :0] core1_pad_jdb_pm;
output [1 :0] core1_pad_lpmd_b;
output cpu_pad_l2cache_flush_done;
output cpu_pad_no_op;
output [39:0] sysio_ciu_apb_base;
output [63:0] sysio_clint_mtime;
output [3 :0] sysio_had_dbg_mask;
output sysio_l2c_flush_req;
output sysio_piu0_dbgrq_b;
output sysio_piu0_me_int;
output sysio_piu0_ms_int;
output sysio_piu0_mt_int;
output sysio_piu0_se_int;
output sysio_piu0_ss_int;
output sysio_piu0_st_int;
output sysio_piu1_dbgrq_b;
output sysio_piu1_me_int;
output sysio_piu1_ms_int;
output sysio_piu1_mt_int;
output sysio_piu1_se_int;
output sysio_piu1_ss_int;
output sysio_piu1_st_int;
output [39:0] sysio_xx_apb_base;
output [63:0] sysio_xx_time;
// &Regs; @26
reg [12:0] apb_base;
reg [63:0] ccvr;
reg cpu_pad_l2cache_flush_done;
reg cpu_pad_no_op;
reg sysio_l2c_flush_req;
// &Wires; @27
wire apb_clk_en;
wire axim_clk_en;
wire ciu_sysio_icg_en;
wire ciu_xx_no_op;
wire clint_core0_ms_int;
wire clint_core0_mt_int;
wire clint_core0_ss_int;
wire clint_core0_st_int;
wire clint_core1_ms_int;
wire clint_core1_mt_int;
wire clint_core1_ss_int;
wire clint_core1_st_int;
wire [1 :0] core0_pad_jdb_pm;
wire [1 :0] core0_pad_lpmd_b;
wire [1 :0] core1_pad_jdb_pm;
wire [1 :0] core1_pad_lpmd_b;
wire cpurst_b;
wire forever_cpuclk;
wire l2c_sysio_flush_done;
wire l2c_sysio_flush_idle;
wire pad_core0_dbg_mask;
wire pad_core0_dbgrq_b;
wire pad_core1_dbg_mask;
wire pad_core1_dbgrq_b;
wire [39:0] pad_cpu_apb_base;
wire pad_cpu_l2cache_flush_req;
wire [63:0] pad_cpu_sys_cnt;
wire pad_yy_icg_scan_en;
wire [1 :0] piu0_sysio_jdb_pm;
wire [1 :0] piu0_sysio_lpmd_b;
wire [1 :0] piu1_sysio_jdb_pm;
wire [1 :0] piu1_sysio_lpmd_b;
wire plic_core0_me_int;
wire plic_core0_se_int;
wire plic_core1_me_int;
wire plic_core1_se_int;
wire [39:0] sysio_ciu_apb_base;
wire [63:0] sysio_clint_mtime;
wire sysio_clk;
wire sysio_clk_en;
wire [3 :0] sysio_had_dbg_mask;
wire sysio_piu0_dbgrq_b;
wire sysio_piu0_me_int;
wire sysio_piu0_ms_int;
wire sysio_piu0_mt_int;
wire sysio_piu0_se_int;
wire sysio_piu0_ss_int;
wire sysio_piu0_st_int;
wire sysio_piu1_dbgrq_b;
wire sysio_piu1_me_int;
wire sysio_piu1_ms_int;
wire sysio_piu1_mt_int;
wire sysio_piu1_se_int;
wire sysio_piu1_ss_int;
wire sysio_piu1_st_int;
wire [39:0] sysio_xx_apb_base;
wire [63:0] sysio_xx_time;
assign sysio_clk_en = axim_clk_en;
// &Instance("gated_clk_cell", "x_ct_sysio_in_gated_clk"); @31
gated_clk_cell x_ct_sysio_in_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (sysio_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (sysio_clk_en ),
.module_en (ciu_sysio_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @32
// .external_en (1'b0 ), @33
// .global_en (1'b1 ), @34
// .module_en (ciu_sysio_icg_en), @35
// .local_en (sysio_clk_en), @36
// .clk_out (sysio_clk ) @37
// ); @38
//================================================
// debug disable
//================================================
always@(posedge sysio_clk or negedge cpurst_b)
begin
if (!cpurst_b)
sysio_l2c_flush_req <= 1'b0;
else if (axim_clk_en)
sysio_l2c_flush_req <= pad_cpu_l2cache_flush_req;
end
always@(posedge sysio_clk or negedge cpurst_b)
begin
if (!cpurst_b)
cpu_pad_l2cache_flush_done <= 1'b0;
else if (axim_clk_en)
cpu_pad_l2cache_flush_done <= l2c_sysio_flush_done;
end
//================================================
// system counter value to PTIM
//================================================
always@(posedge sysio_clk)
begin
if (axim_clk_en)
ccvr[63:0] <= pad_cpu_sys_cnt[63:0];
else
ccvr[63:0] <= ccvr[63:0];
end
assign sysio_clint_mtime[63:0] = ccvr[63:0];
// &Force("nonport","ccvr_gray"); @100
// &Instance("gated_clk_cell", "x_ct_sysio_time_gated_clk"); @107
// &Connect(.clk_in (forever_cpuclk ), @108
// .external_en (1'b0 ), @109
// .global_en (1'b1 ), @110
// .module_en (ciu_sysio_icg_en). @111
// .local_en (time_updt_en ), @112
// .clk_out (time_clk ) @113
// ); @114
assign sysio_xx_time[63:0] = ccvr[63:0];
//================================================
//apb base address
//================================================
// &Force("bus","pad_cpu_apb_base",39,0); @142
always @(posedge sysio_clk)
begin
if (axim_clk_en)
apb_base[12:0] <= pad_cpu_apb_base[39:27];
end
assign sysio_ciu_apb_base[39:0] = {apb_base[12:0], 27'b0};
assign sysio_xx_apb_base[39:0] = {apb_base[12:0], 27'b0};
//================================================
// cpu no op
//================================================
always @(posedge sysio_clk or negedge cpurst_b)
begin
if (!cpurst_b)
cpu_pad_no_op <= 1'b0;
else if (axim_clk_en)
cpu_pad_no_op <= ciu_xx_no_op && l2c_sysio_flush_idle;
end
//================================================
// cpu no op
//================================================
// &ConnRule(s/core_/core0_/); @167
// &ConnRule(s/piu_/piu0_/); @168
// &ConnRule(s/_x/[0]/); @169
// &Instance("ct_sysio_kid", "x_ct_sysio_core0"); @170
ct_sysio_kid x_ct_sysio_core0 (
.apb_clk_en (apb_clk_en ),
.axim_clk_en (axim_clk_en ),
.ciu_sysio_icg_en (ciu_sysio_icg_en ),
.clint_core_ms_int (clint_core0_ms_int ),
.clint_core_mt_int (clint_core0_mt_int ),
.clint_core_ss_int (clint_core0_ss_int ),
.clint_core_st_int (clint_core0_st_int ),
.core_pad_jdb_pm (core0_pad_jdb_pm ),
.core_pad_lpmd_b (core0_pad_lpmd_b ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_core_dbg_mask (pad_core0_dbg_mask ),
.pad_core_dbgrq_b (pad_core0_dbgrq_b ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.piu_sysio_jdb_pm (piu0_sysio_jdb_pm ),
.piu_sysio_lpmd_b (piu0_sysio_lpmd_b ),
.plic_core_me_int (plic_core0_me_int ),
.plic_core_se_int (plic_core0_se_int ),
.sysio_clk (sysio_clk ),
.sysio_had_dbg_mask_x (sysio_had_dbg_mask[0]),
.sysio_piu_dbgrq_b (sysio_piu0_dbgrq_b ),
.sysio_piu_me_int (sysio_piu0_me_int ),
.sysio_piu_ms_int (sysio_piu0_ms_int ),
.sysio_piu_mt_int (sysio_piu0_mt_int ),
.sysio_piu_se_int (sysio_piu0_se_int ),
.sysio_piu_ss_int (sysio_piu0_ss_int ),
.sysio_piu_st_int (sysio_piu0_st_int )
);
// &ConnRule(s/core_/core1_/); @173
// &ConnRule(s/piu_/piu1_/); @174
// &ConnRule(s/_x/[1]/); @175
// &Instance("ct_sysio_kid", "x_ct_sysio_core1"); @176
ct_sysio_kid x_ct_sysio_core1 (
.apb_clk_en (apb_clk_en ),
.axim_clk_en (axim_clk_en ),
.ciu_sysio_icg_en (ciu_sysio_icg_en ),
.clint_core_ms_int (clint_core1_ms_int ),
.clint_core_mt_int (clint_core1_mt_int ),
.clint_core_ss_int (clint_core1_ss_int ),
.clint_core_st_int (clint_core1_st_int ),
.core_pad_jdb_pm (core1_pad_jdb_pm ),
.core_pad_lpmd_b (core1_pad_lpmd_b ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_core_dbg_mask (pad_core1_dbg_mask ),
.pad_core_dbgrq_b (pad_core1_dbgrq_b ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.piu_sysio_jdb_pm (piu1_sysio_jdb_pm ),
.piu_sysio_lpmd_b (piu1_sysio_lpmd_b ),
.plic_core_me_int (plic_core1_me_int ),
.plic_core_se_int (plic_core1_se_int ),
.sysio_clk (sysio_clk ),
.sysio_had_dbg_mask_x (sysio_had_dbg_mask[1]),
.sysio_piu_dbgrq_b (sysio_piu1_dbgrq_b ),
.sysio_piu_me_int (sysio_piu1_me_int ),
.sysio_piu_ms_int (sysio_piu1_ms_int ),
.sysio_piu_mt_int (sysio_piu1_mt_int ),
.sysio_piu_se_int (sysio_piu1_se_int ),
.sysio_piu_ss_int (sysio_piu1_ss_int ),
.sysio_piu_st_int (sysio_piu1_st_int )
);
// &ConnRule(s/core_/core2_/); @182
// &ConnRule(s/piu_/piu2_/); @183
// &ConnRule(s/_x/[2]/); @184
// &Instance("ct_sysio_kid", "x_ct_sysio_core2"); @185
assign sysio_had_dbg_mask[2] = 1'b0;
// &ConnRule(s/core_/core3_/); @191
// &ConnRule(s/piu_/piu3_/); @192
// &ConnRule(s/_x/[3]/); @193
// &Instance("ct_sysio_kid", "x_ct_sysio_core3"); @194
assign sysio_had_dbg_mask[3] = 1'b0;
// &ModuleEnd; @199
endmodule |
module top_golden_port(
biu_pad_acready,
biu_pad_araddr,
biu_pad_arbar,
biu_pad_arburst,
biu_pad_arcache,
biu_pad_ardomain,
biu_pad_arid,
biu_pad_arlen,
biu_pad_arlock,
biu_pad_arprot,
biu_pad_arsize,
biu_pad_arsnoop,
biu_pad_aruser,
biu_pad_arvalid,
biu_pad_awaddr,
biu_pad_awbar,
biu_pad_awburst,
biu_pad_awcache,
biu_pad_awdomain,
biu_pad_awid,
biu_pad_awlen,
biu_pad_awlock,
biu_pad_awprot,
biu_pad_awsize,
biu_pad_awsnoop,
biu_pad_awunique,
biu_pad_awuser,
biu_pad_awvalid,
biu_pad_back,
biu_pad_bready,
biu_pad_cddata,
biu_pad_cderr,
biu_pad_cdlast,
biu_pad_cdvalid,
biu_pad_cnt_en,
biu_pad_crresp,
biu_pad_crvalid,
biu_pad_csr_sel,
biu_pad_csr_wdata,
biu_pad_jdb_pm,
biu_pad_lpmd_b,
biu_pad_rack,
biu_pad_rready,
biu_pad_wdata,
biu_pad_werr,
biu_pad_wlast,
biu_pad_wns,
biu_pad_wstrb,
biu_pad_wvalid,
cp0_pad_mstatus,
ir_corex_wdata,
pad_biu_acaddr,
pad_biu_acprot,
pad_biu_acsnoop,
pad_biu_acvalid,
pad_biu_arready,
pad_biu_awready,
pad_biu_bid,
pad_biu_bresp,
pad_biu_bvalid,
pad_biu_cdready,
pad_biu_crready,
pad_biu_csr_cmplt,
pad_biu_csr_rdata,
pad_biu_dbgrq_b,
pad_biu_hpcp_l2of_int,
pad_biu_me_int,
pad_biu_ms_int,
pad_biu_mt_int,
pad_biu_rdata,
pad_biu_rid,
pad_biu_rlast,
pad_biu_rresp,
pad_biu_rvalid,
pad_biu_se_int,
pad_biu_ss_int,
pad_biu_st_int,
pad_biu_wns_awready,
pad_biu_wns_wready,
pad_biu_wready,
pad_biu_ws_awready,
pad_biu_ws_wready,
pad_core_hartid,
pad_core_rst_b,
pad_core_rvba,
pad_cpu_rst_b,
pad_xx_apb_base,
pad_xx_time,
pad_yy_icg_scan_en,
pad_yy_mbist_mode,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
pll_core_clk,
rtu_cpu_no_retire,
rtu_pad_retire0,
rtu_pad_retire0_pc,
rtu_pad_retire1,
rtu_pad_retire1_pc,
rtu_pad_retire2,
rtu_pad_retire2_pc,
sm_update_dr,
sm_update_ir,
x_dbg_ack_pc,
x_enter_dbg_req_i,
x_enter_dbg_req_o,
x_exit_dbg_req_i,
x_exit_dbg_req_o,
x_had_dbg_mask,
x_regs_serial_data
);
// &Ports; @3
input [63 :0] ir_corex_wdata;
input [39 :0] pad_biu_acaddr;
input [2 :0] pad_biu_acprot;
input [3 :0] pad_biu_acsnoop;
input pad_biu_acvalid;
input pad_biu_arready;
input pad_biu_awready;
input [4 :0] pad_biu_bid;
input [1 :0] pad_biu_bresp;
input pad_biu_bvalid;
input pad_biu_cdready;
input pad_biu_crready;
input pad_biu_csr_cmplt;
input [127:0] pad_biu_csr_rdata;
input pad_biu_dbgrq_b;
input [3 :0] pad_biu_hpcp_l2of_int;
input pad_biu_me_int;
input pad_biu_ms_int;
input pad_biu_mt_int;
input [127:0] pad_biu_rdata;
input [4 :0] pad_biu_rid;
input pad_biu_rlast;
input [3 :0] pad_biu_rresp;
input pad_biu_rvalid;
input pad_biu_se_int;
input pad_biu_ss_int;
input pad_biu_st_int;
input pad_biu_wns_awready;
input pad_biu_wns_wready;
input pad_biu_wready;
input pad_biu_ws_awready;
input pad_biu_ws_wready;
input [2 :0] pad_core_hartid;
input pad_core_rst_b;
input [39 :0] pad_core_rvba;
input pad_cpu_rst_b;
input [39 :0] pad_xx_apb_base;
input [63 :0] pad_xx_time;
input pad_yy_icg_scan_en;
input pad_yy_mbist_mode;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
input pll_core_clk;
input sm_update_dr;
input sm_update_ir;
input x_enter_dbg_req_i;
input x_exit_dbg_req_i;
input x_had_dbg_mask;
output biu_pad_acready;
output [39 :0] biu_pad_araddr;
output [1 :0] biu_pad_arbar;
output [1 :0] biu_pad_arburst;
output [3 :0] biu_pad_arcache;
output [1 :0] biu_pad_ardomain;
output [4 :0] biu_pad_arid;
output [1 :0] biu_pad_arlen;
output biu_pad_arlock;
output [2 :0] biu_pad_arprot;
output [2 :0] biu_pad_arsize;
output [3 :0] biu_pad_arsnoop;
output [2 :0] biu_pad_aruser;
output biu_pad_arvalid;
output [39 :0] biu_pad_awaddr;
output [1 :0] biu_pad_awbar;
output [1 :0] biu_pad_awburst;
output [3 :0] biu_pad_awcache;
output [1 :0] biu_pad_awdomain;
output [4 :0] biu_pad_awid;
output [1 :0] biu_pad_awlen;
output biu_pad_awlock;
output [2 :0] biu_pad_awprot;
output [2 :0] biu_pad_awsize;
output [2 :0] biu_pad_awsnoop;
output biu_pad_awunique;
output biu_pad_awuser;
output biu_pad_awvalid;
output biu_pad_back;
output biu_pad_bready;
output [127:0] biu_pad_cddata;
output biu_pad_cderr;
output biu_pad_cdlast;
output biu_pad_cdvalid;
output [3 :0] biu_pad_cnt_en;
output [4 :0] biu_pad_crresp;
output biu_pad_crvalid;
output biu_pad_csr_sel;
output [79 :0] biu_pad_csr_wdata;
output biu_pad_jdb_pm;
output biu_pad_lpmd_b;
output biu_pad_rack;
output biu_pad_rready;
output [127:0] biu_pad_wdata;
output biu_pad_werr;
output biu_pad_wlast;
output biu_pad_wns;
output [15 :0] biu_pad_wstrb;
output biu_pad_wvalid;
output [63 :0] cp0_pad_mstatus;
output rtu_cpu_no_retire;
output rtu_pad_retire0;
output [39 :0] rtu_pad_retire0_pc;
output rtu_pad_retire1;
output [39 :0] rtu_pad_retire1_pc;
output rtu_pad_retire2;
output [39 :0] rtu_pad_retire2_pc;
output x_dbg_ack_pc;
output x_enter_dbg_req_o;
output x_exit_dbg_req_o;
output [63 :0] x_regs_serial_data;
parameter AXWIDTH = 71;
parameter WWIDTH = 147;
parameter CRWIDTH = 5;
parameter CDWIDTH = 130;
parameter RWIDTH = 138;
parameter ACWIDTH = 47;
parameter BWIDTH = 7;
// &Force("output", "sync_biu_pad_arvalid"); @14
// &Force("output", "sync_biu_pad_awvalid"); @15
// &Force("output", "sync_biu_pad_wvalid"); @16
// &Force("output", "sync_biu_pad_crvalid"); @17
// &Force("output", "sync_biu_pad_cdvalid"); @18
// &Force("output", "sync_biu_pad_rack"); @19
// &Force("output", "sync_biu_pad_back"); @20
// &Force("output", "sync_biu_pad_arbus"); &Force("bus", "sync_biu_pad_arbus", AXWIDTH,0); @22
// &Force("output", "sync_biu_pad_arbus"); &Force("bus", "sync_biu_pad_arbus", AXWIDTH-1,0); @24
// &Force("output", "sync_biu_pad_awbus"); &Force("bus", "sync_biu_pad_awbus", AXWIDTH-1,0); @26
// &Force("output", "sync_biu_pad_wbus"); &Force("bus", "sync_biu_pad_wbus", WWIDTH-1,0); @27
// &Force("output", "sync_biu_pad_crbus"); &Force("bus", "sync_biu_pad_crbus", CRWIDTH-1,0); @28
// &Force("output", "sync_biu_pad_cdbus"); &Force("bus", "sync_biu_pad_cdbus", CDWIDTH-1,0); @29
// &Force("input", "sync_pad_biu_rvalid"); @31
// &Force("input", "sync_pad_biu_bvalid"); @32
// &Force("input", "sync_pad_biu_acvalid"); @33
// &Force("input", "sync_pad_biu_rbus"); &Force("bus", "sync_pad_biu_rbus", RWIDTH-1,0); @34
// &Force("input", "sync_pad_biu_acbus"); &Force("bus", "sync_pad_biu_acbus", ACWIDTH-1,0); @35
// &Force("input", "sync_pad_biu_bbus"); &Force("bus", "sync_pad_biu_bbus", BWIDTH-1,0); @36
// &Force("input", "sync_pad_biu_cdready"); @38
// &Force("input", "sync_pad_biu_crready"); @39
// &Force("input", "sync_pad_biu_arready"); @40
// &Force("input", "sync_pad_biu_awready"); @41
// &Force("input", "sync_pad_biu_wready"); @42
// &Force("input", "sync_pad_biu_wns_awready"); @43
// &Force("input", "sync_pad_biu_wns_wready"); @44
// &Force("input", "sync_pad_biu_ws_awready"); @45
// &Force("input", "sync_pad_biu_ws_wready"); @46
// &Force("output", "sync_biu_pad_acready"); @47
// &Force("output", "sync_biu_pad_rready"); @48
// &Force("output", "sync_biu_pad_bready"); @49
// &Force("input", "async_pad_biu_ar_rptr_gray"); &Force("bus", "async_pad_biu_ar_rptr_gray", 2,0); @51
// &Force("output", "async_biu_pad_ar_wptr_gray"); &Force("bus", "async_biu_pad_ar_wptr_gray",2,0); @52
// &Force("output", "async_biu_pad_arbus_0"); &Force("bus", "async_biu_pad_arbus_0", AXWIDTH,0); @54
// &Force("output", "async_biu_pad_arbus_1"); &Force("bus", "async_biu_pad_arbus_1", AXWIDTH,0); @55
// &Force("output", "async_biu_pad_arbus_2"); &Force("bus", "async_biu_pad_arbus_2", AXWIDTH,0); @56
// &Force("output", "async_biu_pad_arbus_3"); &Force("bus", "async_biu_pad_arbus_3", AXWIDTH,0); @57
// &Force("output", "async_biu_pad_arbus_0"); &Force("bus", "async_biu_pad_arbus_0", AXWIDTH-1,0); @59
// &Force("output", "async_biu_pad_arbus_1"); &Force("bus", "async_biu_pad_arbus_1", AXWIDTH-1,0); @60
// &Force("output", "async_biu_pad_arbus_2"); &Force("bus", "async_biu_pad_arbus_2", AXWIDTH-1,0); @61
// &Force("output", "async_biu_pad_arbus_3"); &Force("bus", "async_biu_pad_arbus_3", AXWIDTH-1,0); @62
// &Force("input", "async_pad_biu_rbus_0"); &Force("bus", "async_pad_biu_rbus_0", RWIDTH-1,0); @64
// &Force("input", "async_pad_biu_rbus_1"); &Force("bus", "async_pad_biu_rbus_1", RWIDTH-1,0); @65
// &Force("input", "async_pad_biu_rbus_2"); &Force("bus", "async_pad_biu_rbus_2", RWIDTH-1,0); @66
// &Force("input", "async_pad_biu_rbus_3"); &Force("bus", "async_pad_biu_rbus_3", RWIDTH-1,0); @67
// &Force("input", "async_pad_biu_r_wptr_gray"); &Force("bus", "async_pad_biu_r_wptr_gray", 2,0); @68
// &Force("output", "async_biu_pad_r_rptr_gray"); &Force("bus", "async_biu_pad_r_rptr_gray", 2,0); @69
// &Force("input", "async_pad_biu_wns_aw_rptr_gray"); @71
// &Force("output", "async_biu_pad_wns_aw_wptr_gray"); @72
// &Force("output", "async_biu_pad_wns_awbus_0"); &Force("bus", "async_biu_pad_wns_awbus_0",AXWIDTH-1,0); @73
// &Force("input", "async_pad_biu_ws_aw_rptr_gray"); @75
// &Force("output", "async_biu_pad_ws_aw_wptr_gray"); @76
// &Force("output", "async_biu_pad_ws_awbus_0"); &Force("bus", "async_biu_pad_ws_awbus_0",AXWIDTH-1,0); @77
// &Force("input", "async_pad_biu_wns_w_rptr_gray"); &Force("bus", "async_pad_biu_wns_w_rptr_gray", 2,0); @79
// &Force("output", "async_biu_pad_wns_w_wptr_gray"); &Force("bus", "async_biu_pad_wns_w_wptr_gray", 2,0); @80
// &Force("output", "async_biu_pad_wns_wbus_0"); &Force("bus", "async_biu_pad_wns_wbus_0",WWIDTH-1,0); @81
// &Force("output", "async_biu_pad_wns_wbus_1"); &Force("bus", "async_biu_pad_wns_wbus_1",WWIDTH-1,0); @82
// &Force("output", "async_biu_pad_wns_wbus_2"); &Force("bus", "async_biu_pad_wns_wbus_2",WWIDTH-1,0); @83
// &Force("output", "async_biu_pad_wns_wbus_3"); &Force("bus", "async_biu_pad_wns_wbus_3",WWIDTH-1,0); @84
// &Force("input", "async_pad_biu_ws_w_rptr_gray"); &Force("bus", "async_pad_biu_ws_w_rptr_gray", 2,0); @86
// &Force("output", "async_biu_pad_ws_w_wptr_gray"); &Force("bus", "async_biu_pad_ws_w_wptr_gray", 2,0); @87
// &Force("output", "async_biu_pad_ws_wbus_0"); &Force("bus", "async_biu_pad_ws_wbus_0",WWIDTH-1,0); @88
// &Force("output", "async_biu_pad_ws_wbus_1"); &Force("bus", "async_biu_pad_ws_wbus_1",WWIDTH-1,0); @89
// &Force("output", "async_biu_pad_ws_wbus_2"); &Force("bus", "async_biu_pad_ws_wbus_2",WWIDTH-1,0); @90
// &Force("output", "async_biu_pad_ws_wbus_3"); &Force("bus", "async_biu_pad_ws_wbus_3",WWIDTH-1,0); @91
// &Force("output","async_biu_pad_b_rptr_gray"); &Force("bus", "async_biu_pad_b_rptr_gray",2,0); @93
// &Force("input", "async_pad_biu_b_wptr_gray"); &Force("bus", "async_pad_biu_b_wptr_gray",2,0) @94
// &Force("input", "async_pad_biu_bbus_0"); &Force("bus", "async_pad_biu_bbus_0",BWIDTH-1,0); @95
// &Force("input", "async_pad_biu_bbus_1"); &Force("bus", "async_pad_biu_bbus_1",BWIDTH-1,0); @96
// &Force("input", "async_pad_biu_bbus_2"); &Force("bus", "async_pad_biu_bbus_2",BWIDTH-1,0); @97
// &Force("input", "async_pad_biu_bbus_3"); &Force("bus", "async_pad_biu_bbus_3",BWIDTH-1,0); @98
// &Force("output","async_biu_pad_ac_rptr_gray"); &Force("bus", "async_biu_pad_ac_rptr_gray",2,0); @100
// &Force("input", "async_pad_biu_ac_wptr_gray"); &Force("bus", "async_pad_biu_ac_wptr_gray",2,0) @101
// &Force("input", "async_pad_biu_acbus_0"); &Force("bus", "async_pad_biu_acbus_0",ACWIDTH-1,0); @102
// &Force("input", "async_pad_biu_acbus_1"); &Force("bus", "async_pad_biu_acbus_1",ACWIDTH-1,0); @103
// &Force("input", "async_pad_biu_acbus_2"); &Force("bus", "async_pad_biu_acbus_2",ACWIDTH-1,0); @104
// &Force("input", "async_pad_biu_acbus_3"); &Force("bus", "async_pad_biu_acbus_3",ACWIDTH-1,0); @105
// &Force("input", "async_pad_biu_cr_rptr_gray"); &Force("bus", "async_pad_biu_cr_rptr_gray",2,0); @108
// &Force("output", "async_biu_pad_cr_wptr_gray"); &Force("bus", "async_biu_pad_cr_wptr_gray",2,0); @109
// &Force("output", "async_biu_pad_crbus_0"); &Force("bus", "async_biu_pad_crbus_0", CRWIDTH-1,0); @110
// &Force("output", "async_biu_pad_crbus_1"); &Force("bus", "async_biu_pad_crbus_1", CRWIDTH-1,0); @111
// &Force("output", "async_biu_pad_crbus_2"); &Force("bus", "async_biu_pad_crbus_2", CRWIDTH-1,0); @112
// &Force("output", "async_biu_pad_crbus_3"); &Force("bus", "async_biu_pad_crbus_3", CRWIDTH-1,0); @113
// &Force("input", "async_pad_biu_cd_rptr_gray"); &Force("bus", "async_pad_biu_cd_rptr_gray",2,0); @115
// &Force("output", "async_biu_pad_cd_wptr_gray"); &Force("bus", "async_biu_pad_cd_wptr_gray",2,0); @116
// &Force("output", "async_biu_pad_cdbus_0"); &Force("bus", "async_biu_pad_cdbus_0", CDWIDTH-1,0); @117
// &Force("output", "async_biu_pad_cdbus_1"); &Force("bus", "async_biu_pad_cdbus_1", CDWIDTH-1,0); @118
// &Force("output", "async_biu_pad_cdbus_2"); &Force("bus", "async_biu_pad_cdbus_2", CDWIDTH-1,0); @119
// &Force("output", "async_biu_pad_cdbus_3"); &Force("bus", "async_biu_pad_cdbus_3", CDWIDTH-1,0); @120
// &Force("input", "async_pad_biu_rack_rptr_gray"); &Force("bus", "async_pad_biu_rack_rptr_gray",2,0); @122
// &Force("output", "async_biu_pad_rack_wptr_gray"); &Force("bus", "async_biu_pad_rack_wptr_gray",2,0); @123
// &Force("input", "async_pad_biu_back_rptr_gray"); &Force("bus", "async_pad_biu_back_rptr_gray",2,0); @125
// &Force("output", "async_biu_pad_back_wptr_gray"); &Force("bus", "async_biu_pad_back_wptr_gray",2,0); @126
// &Force("output", "biu_pad_arvalid"); @128
// &Force("output", "biu_pad_araddr"); &Force("bus","biu_pad_araddr",39,0); @129
// &Force("output", "biu_pad_arburst"); &Force("bus","biu_pad_arburst",1,0); @130
// &Force("output", "biu_pad_arcache"); &Force("bus","biu_pad_arcache",3,0); @131
// &Force("output", "biu_pad_arid"); &Force("bus","biu_pad_arid",4,0); @132
// &Force("output", "biu_pad_arlen"); &Force("bus","biu_pad_arlen",1,0); @133
// &Force("output", "biu_pad_arlock"); @134
// &Force("output", "biu_pad_arprot"); &Force("bus","biu_pad_arprot",2,0); @135
// &Force("output", "biu_pad_arsize"); &Force("bus","biu_pad_arsize",2,0); @136
// &Force("output", "biu_pad_arbar"); &Force("bus","biu_pad_arbar",1,0); @137
// &Force("output", "biu_pad_ardomain"); &Force("bus","biu_pad_ardomain",1,0); @138
// &Force("output", "biu_pad_arsnoop"); &Force("bus","biu_pad_arsnoop",3,0); @139
// &Force("output", "biu_pad_aruser"); &Force("bus","biu_pad_aruser",2,0); @140
// &Force("input", "pad_biu_arready"); @141
// &Force("output", "biu_pad_ref_pfu_ar_sel"); @143
// &Force("input", "pad_biu_rvalid"); @146
// &Force("input", "pad_biu_rdata"); &Force("bus","pad_biu_rdata",127,0); @147
// &Force("input", "pad_biu_rresp"); &Force("bus","pad_biu_rresp",3,0); @148
// &Force("input", "pad_biu_rid"); &Force("bus","pad_biu_rid",4,0); @149
// &Force("input", "pad_biu_rlast"); @150
// &Force("output", "biu_pad_rready"); @151
// &Force("output", "biu_pad_awvalid"); @153
// &Force("output", "biu_pad_awaddr"); &Force("bus","biu_pad_awaddr",39,0); @154
// &Force("output", "biu_pad_awburst"); &Force("bus","biu_pad_awburst",1,0); @155
// &Force("output", "biu_pad_awcache"); &Force("bus","biu_pad_awcache",3,0); @156
// &Force("output", "biu_pad_awid"); &Force("bus","biu_pad_awid",4,0); @157
// &Force("output", "biu_pad_awlen"); &Force("bus","biu_pad_awlen",1,0); @158
// &Force("output", "biu_pad_awlock"); @159
// &Force("output", "biu_pad_awprot"); &Force("bus","biu_pad_awprot",2,0); @160
// &Force("output", "biu_pad_awsize"); &Force("bus","biu_pad_awsize",2,0); @161
// &Force("output", "biu_pad_awbar"); &Force("bus","biu_pad_awbar",1,0); @162
// &Force("output", "biu_pad_awdomain"); &Force("bus","biu_pad_awdomain",1,0); @163
// &Force("output", "biu_pad_awsnoop"); &Force("bus","biu_pad_awsnoop",2,0); @164
// &Force("output", "biu_pad_awuser"); @165
// &Force("output", "biu_pad_awunique"); @166
// &Force("input", "pad_biu_awready"); @167
// &Force("input", "pad_biu_wns_awready"); @168
// &Force("input", "pad_biu_ws_awready"); @169
// &Force("output", "biu_pad_wvalid"); @171
// &Force("output", "biu_pad_wdata"); &Force("bus","biu_pad_wdata",127,0); @172
// &Force("output", "biu_pad_wlast"); @173
// &Force("output", "biu_pad_werr"); @174
// &Force("output", "biu_pad_wns"); @175
// &Force("output", "biu_pad_wstrb"); &Force("bus","biu_pad_wstrb",15,0); @176
// &Force("input", "pad_biu_wready"); @177
// &Force("input", "pad_biu_wns_wready"); @178
// &Force("input", "pad_biu_ws_wready"); @179
// &Force("input", "pad_biu_bvalid"); @181
// &Force("input", "pad_biu_bid"); &Force("bus","pad_biu_bid",4,0); @182
// &Force("input", "pad_biu_bresp"); &Force("bus","pad_biu_bresp", 1,0); @183
// &Force("output", "biu_pad_bready"); @184
// &Force("input", "pad_biu_acvalid"); @186
// &Force("input", "pad_biu_acaddr"); &Force("bus","pad_biu_acaddr",39,0); @187
// &Force("input", "pad_biu_acprot"); &Force("bus","pad_biu_acprot",2,0); @188
// &Force("input", "pad_biu_acsnoop"); &Force("bus","pad_biu_acsnoop",3,0); @189
// &Force("output", "biu_pad_acready"); @190
// &Force("output", "biu_pad_crvalid"); @192
// &Force("output", "biu_pad_crresp"); &Force("bus","biu_pad_crresp",4,0); @193
// &Force("input", "pad_biu_crready"); @194
// &Force("output", "biu_pad_cdvalid"); @196
// &Force("output", "biu_pad_cddata"); &Force("bus","biu_pad_cddata",127,0); @197
// &Force("output", "biu_pad_cdlast"); @198
// &Force("output", "biu_pad_cderr"); @199
// &Force("input", "pad_biu_cdready"); @200
// &Force("output", "biu_pad_rack"); @202
// &Force("output", "biu_pad_back"); @203
// &Force("output", "biu_pad_csr_sel"); @206
// &Force("output", "biu_pad_csr_wdata"); &Force("bus", "biu_pad_csr_wdata", 79,0); @207
// &Force("input", "pad_biu_csr_cmplt"); @208
// &Force("input", "pad_biu_csr_rdata"); &Force("bus", "pad_biu_csr_rdata",127,0); @209
// &Force("output", "biu_pad_cnt_en"); &Force("bus", "biu_pad_cnt_en",3,0); @211
// &Force("output", "biu_pad_jdb_pm"); @212
// &Force("output", "biu_pad_lpmd_b"); @213
// &Force("input", "pad_biu_hpcp_l2of_int"); &Force("bus", "pad_biu_hpcp_l2of_int",3,0); @215
// &Force("input", "pad_biu_dbgrq_b"); @216
// &Force("input", "pad_biu_me_int"); @217
// &Force("input", "pad_biu_ms_int"); @218
// &Force("input", "pad_biu_mt_int"); @219
// &Force("input", "pad_biu_se_int"); @220
// &Force("input", "pad_biu_ss_int"); @221
// &Force("input", "pad_biu_st_int"); @222
// &Force("input", "pll_core_clk"); @224
// &Force("input", "pad_cpu_rst_b"); @225
// &Force("input", "pad_core_rst_b"); @226
// &Force("input", "pad_core_hartid"); &Force("bus", "pad_core_hartid",2,0); @227
// &Force("input", "pad_core_rvba"); &Force("bus", "pad_core_rvba",39,0); @228
// &Force("input", "pad_xx_apb_base"); &Force("bus", "pad_xx_apb_base",39,0); @229
// &Force("input", "pad_xx_time"); &Force("bus", "pad_xx_time", 63,0); @230
// &Force("input", "pad_yy_icg_scan_en"); @231
// &Force("input", "pad_yy_mbist_mode"); @232
// &Force("input", "pad_yy_scan_mode"); @233
// &Force("input", "pad_yy_scan_rst_b"); @234
// &Force("output", "rtu_pad_retire0"); @236
// &Force("output", "rtu_pad_retire0_pc"); &Force("bus", "rtu_pad_retire0_pc",39,0); @237
// &Force("output", "rtu_pad_retire1"); @238
// &Force("output", "rtu_pad_retire1_pc"); &Force("bus", "rtu_pad_retire1_pc",39,0); @239
// &Force("output", "rtu_pad_retire2"); @240
// &Force("output", "rtu_pad_retire2_pc"); &Force("bus", "rtu_pad_retire2_pc",39,0); @241
// &Force("output", "cp0_pad_mstatus"); &Force("bus","cp0_pad_mstatus",63,0); @242
//==========================================================
// HAD
//==========================================================
// &Force("input", "sm_update_dr"); @247
// &Force("input", "sm_update_ir"); @248
// &Force("input", "ir_corex_wdata"); &Force("bus", "ir_corex_wdata", 63, 0); @249
// &Force("output", "x_regs_serial_data"); &Force("bus", "x_regs_serial_data", 63, 0); @250
// &Force("input", "x_enter_dbg_req_i"); @252
// &Force("input", "x_exit_dbg_req_i"); @253
// &Force("output", "x_enter_dbg_req_o"); @254
// &Force("output", "x_exit_dbg_req_o"); @255
// &Force("output", "x_enter_dbg_req_i_ack"); @257
// &Force("output", "x_exit_dbg_req_i_ack"); @258
// &Force("input", "x_enter_dbg_req_o_ack"); @259
// &Force("input", "x_exit_dbg_req_o_ack"); @260
// &Force("output", "x_dbg_ack_pc"); @263
// &Force("input", "x_dbg_ack_pc_ack"); @265
// &Force("input", "x_had_dbg_mask"); @268
// &Force("input", "had_xx_ree_dbg_disable"); &Force("bus", "had_xx_ree_dbg_disable", 7, 0); @271
// &Force("input", "had_xx_tee_dbg_disable"); &Force("bus", "had_xx_tee_dbg_disable", 7, 0); @272
// &Force("output","biu_pad_tee_violation"); @273
// &Force("output","biu_pad_par_violation"); &Force("bus", "biu_pad_par_violation", 4, 0); @274
// &Force("input","mem_cfg_in"); &Force("bus", "mem_cfg_in",`MEM_CFG_IN_WIDTH-1,0); @278
// &Force("input", "pad_core_sleep_in"); @282
// &Force("output","core_pad_sleep_out"); @283
// &Force("input", "pad_core_async_mode"); @287
// &Force("input", "pad_biu_psel"); @291
// &Force("input", "pad_biu_pwdata"); &Force("bus", "pad_biu_pwdata",74,0); @292
// &Force("output", "biu_pad_pready"); @293
// &Force("output", "biu_pad_prdata"); &Force("bus", "biu_pad_prdata",32,0); @294
// &Force("output", "idu_pad_dispatch_info"); @298
// &Force("output", "idu_pad_dispatch0_info"); &Force("bus","idu_pad_dispatch0_info",78,0); @299
// &Force("output", "idu_pad_dispatch1_info"); &Force("bus","idu_pad_dispatch1_info",78,0); @300
// &Force("output", "idu_pad_dispatch2_info"); &Force("bus","idu_pad_dispatch2_info",78,0); @301
// &Force("output", "idu_pad_dispatch3_info"); &Force("bus","idu_pad_dispatch3_info",78,0); @302
// &Force("output", "rtu_pad_flush"); @303
// &Force("output", "rtu_pad_retire0_iid"); &Force("bus","rtu_pad_retire0_iid",6,0); @304
// &Force("output", "rtu_pad_retire1_iid"); &Force("bus","rtu_pad_retire1_iid",6,0); @305
// &Force("output", "rtu_pad_retire2_iid"); &Force("bus","rtu_pad_retire2_iid",6,0); @306
// &Force("output", "rtu_pad_wb0_vld"); @307
// &Force("output", "rtu_pad_wb0_preg"); &Force("bus","rtu_pad_wb0_preg",6,0); @308
// &Force("output", "rtu_pad_wb0_data"); &Force("bus","rtu_pad_wb0_data",63,0); @309
// &Force("output", "rtu_pad_wb0_freg_vld"); @310
// &Force("output", "rtu_pad_wb0_freg"); &Force("bus","rtu_pad_wb0_freg",6,0); @311
// &Force("output", "rtu_pad_wb0_fdata"); &Force("bus","rtu_pad_wb0_fdata",63,0); @312
// &Force("output", "rtu_pad_wb0_vreg_vld"); @313
// &Force("output", "rtu_pad_wb0_vreg"); &Force("bus","rtu_pad_wb0_vreg",6,0); @314
// &Force("output", "rtu_pad_wb0_vdata"); &Force("bus","rtu_pad_wb0_vdata",127,0); @315
// &Force("output", "rtu_pad_wb0_ereg_vld"); @316
// &Force("output", "rtu_pad_wb0_ereg"); &Force("bus","rtu_pad_wb0_ereg",4,0); @317
// &Force("output", "rtu_pad_wb0_edata"); &Force("bus","rtu_pad_wb0_edata",5,0); @318
// &Force("output", "rtu_pad_wb1_vld"); @319
// &Force("output", "rtu_pad_wb1_preg"); &Force("bus","rtu_pad_wb1_preg",6,0); @320
// &Force("output", "rtu_pad_wb1_data"); &Force("bus","rtu_pad_wb1_data",63,0); @321
// &Force("output", "rtu_pad_wb1_freg_vld"); @322
// &Force("output", "rtu_pad_wb1_freg"); &Force("bus","rtu_pad_wb1_freg",6,0); @323
// &Force("output", "rtu_pad_wb1_fdata"); &Force("bus","rtu_pad_wb1_fdata",63,0); @324
// &Force("output", "rtu_pad_wb1_vreg_vld"); @325
// &Force("output", "rtu_pad_wb1_vreg"); &Force("bus","rtu_pad_wb1_vreg",6,0); @326
// &Force("output", "rtu_pad_wb1_vdata"); &Force("bus","rtu_pad_wb1_vdata",127,0); @327
// &Force("output", "rtu_pad_wb1_ereg_vld"); @328
// &Force("output", "rtu_pad_wb1_ereg"); &Force("bus","rtu_pad_wb1_ereg",4,0); @329
// &Force("output", "rtu_pad_wb1_edata"); &Force("bus","rtu_pad_wb1_edata",5,0); @330
// &Force("output", "rtu_pad_wb2_vld"); @331
// &Force("output", "rtu_pad_wb2_preg"); &Force("bus","rtu_pad_wb2_preg",6,0); @332
// &Force("output", "rtu_pad_wb2_data"); &Force("bus","rtu_pad_wb2_data",63,0); @333
// &Force("output", "rtu_pad_wb2_freg_vld"); @334
// &Force("output", "rtu_pad_wb2_freg"); &Force("bus","rtu_pad_wb2_freg",6,0); @335
// &Force("output", "rtu_pad_wb2_fdata"); &Force("bus","rtu_pad_wb2_fdata",63,0); @336
// &Force("output", "rtu_pad_wb2_vreg_vld"); @337
// &Force("output", "rtu_pad_wb2_vreg"); &Force("bus","rtu_pad_wb2_vreg",6,0); @338
// &Force("output", "rtu_pad_wb2_vdata"); &Force("bus","rtu_pad_wb2_vdata",127,0); @339
// &Force("output", "biu_pad_ref_cache_awaddr"); &Force("bus","biu_pad_ref_cache_awaddr",39,0); @340
// &Force("output", "biu_pad_ref_cache_awsize"); &Force("bus","biu_pad_ref_cache_awsize",2,0); @341
// &Force("output", "biu_pad_ref_cache_awvalid"); @342
// &Force("output", "biu_pad_ref_cache_wdata"); &Force("bus","biu_pad_ref_cache_wdata",127,0); @343
// &Force("output", "biu_pad_ref_cache_wstrb"); &Force("bus","biu_pad_ref_cache_wstrb",15,0); @344
// &Force("output", "rtu_cpu_no_retire"); @348
// &ModuleEnd; @351
endmodule |
module ct_sysio_kid(
apb_clk_en,
axim_clk_en,
ciu_sysio_icg_en,
clint_core_ms_int,
clint_core_mt_int,
clint_core_ss_int,
clint_core_st_int,
core_pad_jdb_pm,
core_pad_lpmd_b,
cpurst_b,
forever_cpuclk,
pad_core_dbg_mask,
pad_core_dbgrq_b,
pad_yy_icg_scan_en,
piu_sysio_jdb_pm,
piu_sysio_lpmd_b,
plic_core_me_int,
plic_core_se_int,
sysio_clk,
sysio_had_dbg_mask_x,
sysio_piu_dbgrq_b,
sysio_piu_me_int,
sysio_piu_ms_int,
sysio_piu_mt_int,
sysio_piu_se_int,
sysio_piu_ss_int,
sysio_piu_st_int
);
// &Ports; @23
input apb_clk_en;
input axim_clk_en;
input ciu_sysio_icg_en;
input clint_core_ms_int;
input clint_core_mt_int;
input clint_core_ss_int;
input clint_core_st_int;
input cpurst_b;
input forever_cpuclk;
input pad_core_dbg_mask;
input pad_core_dbgrq_b;
input pad_yy_icg_scan_en;
input [1:0] piu_sysio_jdb_pm;
input [1:0] piu_sysio_lpmd_b;
input plic_core_me_int;
input plic_core_se_int;
input sysio_clk;
output [1:0] core_pad_jdb_pm;
output [1:0] core_pad_lpmd_b;
output sysio_had_dbg_mask_x;
output sysio_piu_dbgrq_b;
output sysio_piu_me_int;
output sysio_piu_ms_int;
output sysio_piu_mt_int;
output sysio_piu_se_int;
output sysio_piu_ss_int;
output sysio_piu_st_int;
// &Regs; @24
reg clint_core_ms_int_cpu;
reg clint_core_mt_int_cpu;
reg clint_core_ss_int_cpu;
reg clint_core_st_int_cpu;
reg [1:0] core_pad_jdb_pm;
reg [1:0] core_pad_lpmd_b;
reg plic_core_me_int_cpu;
reg plic_core_se_int_cpu;
reg sysio_had_dbg_mask_x;
reg sysio_piu_dbgrq_b;
// &Wires; @25
wire apb_clk_en;
wire axim_clk_en;
wire ciu_sysio_icg_en;
wire clint_core_ms_int;
wire clint_core_mt_int;
wire clint_core_ss_int;
wire clint_core_st_int;
wire cpurst_b;
wire forever_cpuclk;
wire kid_int_clk;
wire kid_int_clk_en;
wire pad_core_dbg_mask;
wire pad_core_dbgrq_b;
wire pad_yy_icg_scan_en;
wire [1:0] piu_sysio_jdb_pm;
wire [1:0] piu_sysio_lpmd_b;
wire plic_core_me_int;
wire plic_core_se_int;
wire sysio_clk;
wire sysio_piu_me_int;
wire sysio_piu_ms_int;
wire sysio_piu_mt_int;
wire sysio_piu_se_int;
wire sysio_piu_ss_int;
wire sysio_piu_st_int;
//==========================================================
//input
//==========================================================
always @(posedge sysio_clk)
begin
if (axim_clk_en)
begin
sysio_piu_dbgrq_b <= pad_core_dbgrq_b;
end
end
always @(posedge sysio_clk)
begin
if (axim_clk_en)
begin
sysio_had_dbg_mask_x <= pad_core_dbg_mask;
end
end
//==========================================================
//output
//==========================================================
always @(posedge sysio_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
core_pad_jdb_pm[1:0] <= 2'b0;
core_pad_lpmd_b[1:0] <= 2'b11;
end
else if (axim_clk_en)
begin
core_pad_jdb_pm[1:0] <= piu_sysio_jdb_pm[1:0];
core_pad_lpmd_b[1:0] <= piu_sysio_lpmd_b[1:0];
end
end
//==========================================================
//PLIC and CLINT int
//==========================================================
assign kid_int_clk_en = apb_clk_en;
// &Instance("gated_clk_cell", "x_sysio_kid_int_gated_clk"); @86
gated_clk_cell x_sysio_kid_int_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (kid_int_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (kid_int_clk_en ),
.module_en (ciu_sysio_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @87
// .external_en (1'b0 ), @88
// .global_en (1'b1 ), @89
// .module_en (ciu_sysio_icg_en). @90
// .local_en (kid_int_clk_en), @91
// .clk_out (kid_int_clk ) @92
// ); @93
always @(posedge kid_int_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
plic_core_me_int_cpu <= 1'b0;
plic_core_se_int_cpu <= 1'b0;
clint_core_ms_int_cpu <= 1'b0;
clint_core_ss_int_cpu <= 1'b0;
clint_core_mt_int_cpu <= 1'b0;
clint_core_st_int_cpu <= 1'b0;
end
else if (apb_clk_en)
begin
plic_core_me_int_cpu <= plic_core_me_int;
plic_core_se_int_cpu <= plic_core_se_int;
clint_core_ms_int_cpu <= clint_core_ms_int;
clint_core_ss_int_cpu <= clint_core_ss_int;
clint_core_mt_int_cpu <= clint_core_mt_int;
clint_core_st_int_cpu <= clint_core_st_int;
end
end
assign sysio_piu_me_int = plic_core_me_int_cpu;
assign sysio_piu_se_int = plic_core_se_int_cpu;
assign sysio_piu_ms_int = clint_core_ms_int_cpu;
assign sysio_piu_ss_int = clint_core_ss_int_cpu;
assign sysio_piu_mt_int = clint_core_mt_int_cpu;
assign sysio_piu_st_int = clint_core_st_int_cpu;
// &ModuleEnd; @124
endmodule |
module ct_ciu_bmbif_kid(
bmbif_piu0_xx_grant,
bmbif_piu1_xx_grant,
bmbif_piu2_xx_grant,
bmbif_piu3_xx_grant,
bmbif_xx_bar_req,
bmbif_xx_mid,
bmbif_xx_req_bus,
ciu_icg_en,
cpurst_b,
forever_cpuclk,
pad_yy_icg_scan_en,
piu0_bmbif_req_bus,
piu0_bmbif_xx_req,
piu1_bmbif_req_bus,
piu1_bmbif_xx_req,
piu2_bmbif_req_bus,
piu2_bmbif_xx_req,
piu3_bmbif_req_bus,
piu3_bmbif_xx_req,
xx_bmbif_bar_grant
);
// &Ports; @21
input ciu_icg_en;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [8:0] piu0_bmbif_req_bus;
input piu0_bmbif_xx_req;
input [8:0] piu1_bmbif_req_bus;
input piu1_bmbif_xx_req;
input [8:0] piu2_bmbif_req_bus;
input piu2_bmbif_xx_req;
input [8:0] piu3_bmbif_req_bus;
input piu3_bmbif_xx_req;
input xx_bmbif_bar_grant;
output bmbif_piu0_xx_grant;
output bmbif_piu1_xx_grant;
output bmbif_piu2_xx_grant;
output bmbif_piu3_xx_grant;
output bmbif_xx_bar_req;
output [2:0] bmbif_xx_mid;
output [8:0] bmbif_xx_req_bus;
// &Regs; @22
// &Wires; @23
wire bmbif_piu0_xx_grant;
wire bmbif_piu1_xx_grant;
wire bmbif_piu2_xx_grant;
wire bmbif_piu3_xx_grant;
wire bmbif_xx_bar_req;
wire bmbif_xx_clk;
wire bmbif_xx_clk_en;
wire [2:0] bmbif_xx_mid;
wire [8:0] bmbif_xx_req_bus;
wire ciu_icg_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire [8:0] piu0_bmbif_req_bus;
wire piu0_bmbif_xx_req;
wire [8:0] piu1_bmbif_req_bus;
wire piu1_bmbif_xx_req;
wire [8:0] piu2_bmbif_req_bus;
wire piu2_bmbif_xx_req;
wire [8:0] piu3_bmbif_req_bus;
wire piu3_bmbif_xx_req;
wire [3:0] xx_bar_sel;
wire [3:0] xx_bar_valid;
wire xx_bmbif_bar_grant;
wire [3:0] xx_fifo_create_bus;
wire xx_fifo_create_en;
wire [3:0] xx_fifo_pop_bus;
wire xx_fifo_pop_bus_vld;
wire xx_fifo_pop_en;
// &Force("nonport", "bmbif_xx_clk"); @25
// &Force("nonport", "xx_bar_valid"); @26
// &Force("nonport", "xx_bar_sel"); @27
// &Force("nonport", "xx_fifo_create_en"); @28
// &Force("nonport", "xx_fifo_pop_en"); @29
// &Force("nonport", "xx_fifo_create_bus"); @30
// &Force("nonport", "xx_fifo_pop_bus"); @31
// &Force("nonport", "xx_fifo_pop_bus_vld"); @32
// &Force("nonport", "xx_fifo_full"); @33
// &Force("nonport", "xx_fifo_empty"); @34
// &Force("input", "cpurst_b"); @35
assign bmbif_xx_clk_en = |xx_bar_sel[3:0];
// &Instance("gated_clk_cell", "x_bmbif_xx_prio_gated_clk"); @39
gated_clk_cell x_bmbif_xx_prio_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (bmbif_xx_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (bmbif_xx_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @40
// .external_en (1'b0), @41
// .global_en (1'b1), @42
// .module_en (ciu_icg_en ), @43
// .local_en (bmbif_xx_clk_en), @44
// .clk_out (bmbif_xx_clk)); @45
assign xx_bar_valid[3:0] ={piu3_bmbif_xx_req,
piu2_bmbif_xx_req,
piu1_bmbif_xx_req,
piu0_bmbif_xx_req};
ct_prio #(.NUM(4)) x_ct_bmbif_xx_prio(
.clk (bmbif_xx_clk ),
.rst_b (cpurst_b ),
.valid (xx_bar_valid ),
.clr (1'b1 ),
.sel (xx_bar_sel )
);
assign bmbif_piu0_xx_grant = xx_bar_sel[0];
assign bmbif_piu1_xx_grant = xx_bar_sel[1];
assign bmbif_piu2_xx_grant = xx_bar_sel[2];
assign bmbif_piu3_xx_grant = xx_bar_sel[3];
assign xx_fifo_create_en = |xx_bar_valid[3:0];
assign xx_fifo_create_bus[3:0] = xx_bar_sel[3:0];
assign xx_fifo_pop_en = xx_bmbif_bar_grant;
ct_fifo #(.WIDTH(4),.DEPTH(4),.PTR_W(2)) x_ct_bmbif_xx_fifo(
.clk (forever_cpuclk ),
.rst_b (cpurst_b ),
.fifo_create_en (xx_fifo_create_en ),
.fifo_create_en_dp (xx_fifo_create_en ),
.fifo_pop_en (xx_fifo_pop_en ),
.fifo_create_data (xx_fifo_create_bus ),
.fifo_pop_data (xx_fifo_pop_bus ),
.fifo_pop_data_vld (xx_fifo_pop_bus_vld ),
.fifo_full (xx_fifo_full ),
.fifo_empty (xx_fifo_empty ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.fifo_icg_en (ciu_icg_en)
);
assign bmbif_xx_bar_req = xx_fifo_pop_bus_vld;
assign bmbif_xx_req_bus[8:0] =
{9{xx_fifo_pop_bus[3]}} & piu3_bmbif_req_bus[8:0] |
{9{xx_fifo_pop_bus[2]}} & piu2_bmbif_req_bus[8:0] |
{9{xx_fifo_pop_bus[1]}} & piu1_bmbif_req_bus[8:0] |
{9{xx_fifo_pop_bus[0]}} & piu0_bmbif_req_bus[8:0];
assign bmbif_xx_mid[2] = 1'b0;
assign bmbif_xx_mid[1] = xx_fifo_pop_bus[3] | xx_fifo_pop_bus[2];
assign bmbif_xx_mid[0] = xx_fifo_pop_bus[3] | xx_fifo_pop_bus[1];
// &ModuleEnd; @97
endmodule |
module ct_piu_top_dummy_device(
piu_snb0_ar_bus,
piu_snb0_ar_req,
piu_snb0_aw_req,
piu_snb0_b_grant,
piu_snb0_back,
piu_snb0_r_grant,
piu_snb0_rack,
piu_snb0_wcd_req,
piu_snb1_ar_bus,
piu_snb1_ar_req,
piu_snb1_aw_req,
piu_snb1_b_grant,
piu_snb1_back,
piu_snb1_r_grant,
piu_snb1_rack,
piu_snb1_wcd_req,
piu_snbx_back_sid,
piu_snbx_rack_sid,
piu_xx_aw_bus,
piu_xx_no_op,
piu_xx_wcd_bus,
snb0_piu_ar_grant,
snb0_piu_aw_grant,
snb0_piu_bvalid,
snb0_piu_rvalid,
snb0_piu_wcd_grant,
snb0_piux_bbus,
snb0_piux_rbus,
snb1_piu_ar_grant,
snb1_piu_aw_grant,
snb1_piu_bvalid,
snb1_piu_rvalid,
snb1_piu_wcd_grant,
snb1_piux_bbus,
snb1_piux_rbus
);
// &Ports; @2
input snb0_piu_ar_grant;
input snb0_piu_aw_grant;
input snb0_piu_bvalid;
input snb0_piu_rvalid;
input snb0_piu_wcd_grant;
input [13 :0] snb0_piux_bbus;
input [534:0] snb0_piux_rbus;
input snb1_piu_ar_grant;
input snb1_piu_aw_grant;
input snb1_piu_bvalid;
input snb1_piu_rvalid;
input snb1_piu_wcd_grant;
input [13 :0] snb1_piux_bbus;
input [534:0] snb1_piux_rbus;
output [70 :0] piu_snb0_ar_bus;
output piu_snb0_ar_req;
output piu_snb0_aw_req;
output piu_snb0_b_grant;
output piu_snb0_back;
output piu_snb0_r_grant;
output piu_snb0_rack;
output piu_snb0_wcd_req;
output [70 :0] piu_snb1_ar_bus;
output piu_snb1_ar_req;
output piu_snb1_aw_req;
output piu_snb1_b_grant;
output piu_snb1_back;
output piu_snb1_r_grant;
output piu_snb1_rack;
output piu_snb1_wcd_req;
output [4 :0] piu_snbx_back_sid;
output [4 :0] piu_snbx_rack_sid;
output [70 :0] piu_xx_aw_bus;
output piu_xx_no_op;
output [534:0] piu_xx_wcd_bus;
// &Regs; @3
// &Wires; @4
wire [70 :0] piu_snb0_ar_bus;
wire piu_snb0_ar_req;
wire piu_snb0_aw_req;
wire piu_snb0_b_grant;
wire piu_snb0_back;
wire piu_snb0_r_grant;
wire piu_snb0_rack;
wire piu_snb0_wcd_req;
wire [70 :0] piu_snb1_ar_bus;
wire piu_snb1_ar_req;
wire piu_snb1_aw_req;
wire piu_snb1_b_grant;
wire piu_snb1_back;
wire piu_snb1_r_grant;
wire piu_snb1_rack;
wire piu_snb1_wcd_req;
wire [4 :0] piu_snbx_back_sid;
wire [4 :0] piu_snbx_rack_sid;
wire [70 :0] piu_xx_aw_bus;
wire piu_xx_no_op;
wire [534:0] piu_xx_wcd_bus;
parameter UPKB_WIDTH = 535;
parameter B_WIDTH = 14;
parameter ARWIDTH = 71;
parameter AWWIDTH = 71;
parameter WCD_WIDTH = 535;
// &Force("input", "snb0_piu_ar_grant"); @12
// &Force("input", "snb1_piu_ar_grant"); @13
// &Force("input", "snb0_piu_aw_grant"); @15
// &Force("input", "snb1_piu_aw_grant"); @16
// &Force("input", "snb0_piu_wcd_grant"); @17
// &Force("input", "snb1_piu_wcd_grant"); @18
// &Force("input", "snb0_piu_rvalid"); @20
// &Force("input", "snb1_piu_rvalid"); @21
// &Force("input", "snb0_piux_rbus"); &Force("bus", "snb0_piux_rbus",(UPKB_WIDTH-1),0); @22
// &Force("input", "snb1_piux_rbus"); &Force("bus", "snb1_piux_rbus",(UPKB_WIDTH-1),0); @23
// &Force("input", "snb0_piu_bvalid"); @25
// &Force("input", "snb1_piu_bvalid"); @26
// &Force("input", "snb0_piux_bbus"); &Force("bus", "snb0_piux_bbus", (B_WIDTH-1),0); @27
// &Force("input", "snb1_piux_bbus"); &Force("bus", "snb1_piux_bbus", (B_WIDTH-1),0); @28
assign piu_snb0_ar_req = 1'b0;
assign piu_snb1_ar_req = 1'b0;
assign piu_snb0_ar_bus[ARWIDTH-1:0] = {ARWIDTH{1'b0}};
assign piu_snb1_ar_bus[ARWIDTH-1:0] = {ARWIDTH{1'b0}};
assign piu_snb0_aw_req = 1'b0;
assign piu_snb1_aw_req = 1'b0;
assign piu_xx_aw_bus[AWWIDTH-1:0] = {AWWIDTH{1'b0}};
assign piu_snb0_wcd_req = 1'b0;
assign piu_snb1_wcd_req = 1'b0;
assign piu_xx_wcd_bus[WCD_WIDTH-1:0] = {WCD_WIDTH{1'b0}};
assign piu_snb0_r_grant = 1'b0;
assign piu_snb1_r_grant = 1'b0;
assign piu_snb0_b_grant = 1'b0;
assign piu_snb1_b_grant = 1'b0;
assign piu_snb0_rack = 1'b0;
assign piu_snb1_rack = 1'b0;
assign piu_snbx_rack_sid[4:0] = 5'b0;
assign piu_snb0_back = 1'b0;
assign piu_snb1_back = 1'b0;
assign piu_snbx_back_sid[4:0] = 5'b0;
assign piu_xx_no_op = 1'b1;
// &ModuleEnd; @57
endmodule |
module ct_piu_other_io_dummy(
l2cif_piu_read_data_vld,
perr_l2pmp_x,
piu_l2cif_read_data,
piu_l2cif_read_data_ecc,
piu_l2cif_read_index,
piu_l2cif_read_req,
piu_l2cif_read_tag,
piu_l2cif_read_tag_ecc,
piu_l2cif_read_way,
piu_regs_op,
piu_regs_sel,
piu_regs_wdata,
piu_xx_regs_no_op,
pready_l2pmp_x,
psel_l2pmp_x,
regs_piu_cmplt,
x_prdata_l2pmp
);
// &Ports; @2
input l2cif_piu_read_data_vld;
input psel_l2pmp_x;
input regs_piu_cmplt;
output perr_l2pmp_x;
output piu_l2cif_read_data;
output piu_l2cif_read_data_ecc;
output [20:0] piu_l2cif_read_index;
output piu_l2cif_read_req;
output piu_l2cif_read_tag;
output piu_l2cif_read_tag_ecc;
output [3 :0] piu_l2cif_read_way;
output [15:0] piu_regs_op;
output piu_regs_sel;
output [63:0] piu_regs_wdata;
output piu_xx_regs_no_op;
output pready_l2pmp_x;
output [31:0] x_prdata_l2pmp;
// &Regs; @3
// &Wires; @4
wire perr_l2pmp_x;
wire piu_l2cif_read_data;
wire piu_l2cif_read_data_ecc;
wire [20:0] piu_l2cif_read_index;
wire piu_l2cif_read_req;
wire piu_l2cif_read_tag;
wire piu_l2cif_read_tag_ecc;
wire [3 :0] piu_l2cif_read_way;
wire [15:0] piu_regs_op;
wire piu_regs_sel;
wire [63:0] piu_regs_wdata;
wire piu_xx_regs_no_op;
wire pready_l2pmp_x;
wire [31:0] x_prdata_l2pmp;
assign piu_regs_sel = 1'b0;
assign piu_regs_op[15:0] = 16'b0;
assign piu_regs_wdata[63:0] = 64'b0;
assign piu_xx_regs_no_op = 1'b1;
assign piu_l2cif_read_req = 1'b0;
assign piu_l2cif_read_tag = 1'b0;
assign piu_l2cif_read_data = 1'b0;
assign piu_l2cif_read_tag_ecc = 1'b0;
assign piu_l2cif_read_data_ecc = 1'b0;
assign piu_l2cif_read_way[3:0] = 4'b0;
assign piu_l2cif_read_index[20:0] = 21'b0;
// &Force("input", "regs_piu_cmplt"); @19
// &Force("input", "l2cif_piu_read_data_vld"); @20
assign perr_l2pmp_x = 1'b0;
assign pready_l2pmp_x = 1'b1;
assign x_prdata_l2pmp[31:0] = 32'b0;
// &Force("input", "psel_l2pmp_x"); @26
// &ModuleEnd; @28
endmodule |
module ct_ciu_regs_kid(
ciu_icg_en,
forever_cpuclk,
l2cif0_regs_read_acc_inc_x,
l2cif0_regs_read_miss_inc_x,
l2cif0_regs_write_acc_inc_x,
l2cif0_regs_write_miss_inc_x,
l2cif1_regs_read_acc_inc_x,
l2cif1_regs_read_miss_inc_x,
l2cif1_regs_write_acc_inc_x,
l2cif1_regs_write_miss_inc_x,
pad_yy_icg_scan_en,
regs_idx,
regs_l2of_wen,
regs_sel_final_x,
regs_wdata_final,
regs_wen,
smpen_x,
x_csr_value,
x_fifo_rst_b,
x_hpcp_cnt_en,
x_l2of_int
);
// &Ports; @23
input ciu_icg_en;
input forever_cpuclk;
input l2cif0_regs_read_acc_inc_x;
input l2cif0_regs_read_miss_inc_x;
input l2cif0_regs_write_acc_inc_x;
input l2cif0_regs_write_miss_inc_x;
input l2cif1_regs_read_acc_inc_x;
input l2cif1_regs_read_miss_inc_x;
input l2cif1_regs_write_acc_inc_x;
input l2cif1_regs_write_miss_inc_x;
input pad_yy_icg_scan_en;
input [3 :0] regs_idx;
input [3 :0] regs_l2of_wen;
input regs_sel_final_x;
input [63:0] regs_wdata_final;
input regs_wen;
input x_fifo_rst_b;
input [3 :0] x_hpcp_cnt_en;
output smpen_x;
output [63:0] x_csr_value;
output [3 :0] x_l2of_int;
// &Regs; @24
reg [63:0] l2_read_acc_cnt;
reg l2_read_acc_of;
reg [63:0] l2_read_miss_cnt;
reg l2_read_miss_of;
reg [63:0] l2_write_acc_cnt;
reg l2_write_acc_of;
reg [63:0] l2_write_miss_cnt;
reg l2_write_miss_of;
reg [3 :0] l2of_reg;
reg [63:0] regs_dout;
reg smpen;
// &Wires; @25
wire ciu_icg_en;
wire forever_cpuclk;
wire [64:0] l2_read_acc_adder;
wire [64:0] l2_read_miss_adder;
wire [64:0] l2_write_acc_adder;
wire [64:0] l2_write_miss_adder;
wire l2cif0_regs_read_acc_inc_x;
wire l2cif0_regs_read_miss_inc_x;
wire l2cif0_regs_write_acc_inc_x;
wire l2cif0_regs_write_miss_inc_x;
wire l2cif1_regs_read_acc_inc_x;
wire l2cif1_regs_read_miss_inc_x;
wire l2cif1_regs_write_acc_inc_x;
wire l2cif1_regs_write_miss_inc_x;
wire l2of_clk;
wire l2of_clk_en;
wire [3 :0] l2of_updt_data;
wire [63:0] l2of_value;
wire l2of_wen;
wire l2ra_clk;
wire l2ra_clk_en;
wire l2ra_of;
wire [63:0] l2ra_value;
wire l2ra_wen;
wire l2rm_clk;
wire l2rm_clk_en;
wire l2rm_of;
wire [63:0] l2rm_value;
wire l2rm_wen;
wire l2wa_clk;
wire l2wa_clk_en;
wire l2wa_of;
wire [63:0] l2wa_value;
wire l2wa_wen;
wire l2wm_clk;
wire l2wm_clk_en;
wire l2wm_of;
wire [63:0] l2wm_value;
wire l2wm_wen;
wire pad_yy_icg_scan_en;
wire [3 :0] regs_idx;
wire [3 :0] regs_l2of_wen;
wire regs_sel_final_x;
wire [63:0] regs_wdata_final;
wire regs_wen;
wire smpen_x;
wire smpr_clk;
wire smpr_clk_en;
wire [63:0] smpr_value;
wire smpr_wen;
wire [63:0] teem_value;
wire [63:0] x_csr_value;
wire x_fifo_rst_b;
wire [3 :0] x_hpcp_cnt_en;
wire [3 :0] x_l2of_int;
parameter SMPR = 4'h4;
parameter TEEM = 4'h5;
parameter L2RA = 4'h8;
parameter L2RM = 4'h9;
parameter L2WA = 4'ha;
parameter L2WM = 4'hb;
parameter L2OF = 4'hc;
//==========================================================
// REGS MUX
//==========================================================
// &CombBeg; @39
always @( l2wa_value[63:0]
or l2rm_value[63:0]
or regs_idx[3:0]
or l2of_value[63:0]
or teem_value[63:0]
or l2wm_value[63:0]
or l2ra_value[63:0]
or smpr_value[63:0])
begin
case(regs_idx[3:0])
SMPR: regs_dout[63:0] = smpr_value[63:0];
TEEM: regs_dout[63:0] = teem_value[63:0];
L2RA: regs_dout[63:0] = l2ra_value[63:0];
L2RM: regs_dout[63:0] = l2rm_value[63:0];
L2WA: regs_dout[63:0] = l2wa_value[63:0];
L2WM: regs_dout[63:0] = l2wm_value[63:0];
L2OF: regs_dout[63:0] = l2of_value[63:0];
default: regs_dout[63:0] = 64'b0;
endcase
// &CombEnd; @50
end
assign x_csr_value[63:0] = regs_dout[63:0];
//==========================================================
// CSR REGS
//==========================================================
assign smpr_wen = regs_sel_final_x & regs_wen & regs_idx[3:0] == SMPR;
assign l2ra_wen = regs_sel_final_x & regs_wen & regs_idx[3:0] == L2RA;
assign l2rm_wen = regs_sel_final_x & regs_wen & regs_idx[3:0] == L2RM;
assign l2wa_wen = regs_sel_final_x & regs_wen & regs_idx[3:0] == L2WA;
assign l2wm_wen = regs_sel_final_x & regs_wen & regs_idx[3:0] == L2WM;
assign l2of_wen = regs_sel_final_x & regs_wen & regs_idx[3:0] == L2OF;
//======================================
// SMPR
//======================================
always @(posedge smpr_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
smpen <= 1'b0;
else if (smpr_wen)
smpen <= regs_wdata_final[0];
end
assign smpr_value[63:0] = {63'b0,smpen};
assign smpen_x = smpen;
assign teem_value[63:0] = 64'b0;
//======================================
// L2RA
//======================================
always @(posedge l2ra_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
l2_read_acc_cnt[63:0] <= 64'b0;
else if (l2ra_wen)
l2_read_acc_cnt[63:0] <= regs_wdata_final[63:0];
else if (x_hpcp_cnt_en[0])
l2_read_acc_cnt[63:0] <= l2_read_acc_adder[63:0];
end
always @(posedge l2ra_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
l2_read_acc_of <= 1'b0;
else if (l2_read_acc_of)
l2_read_acc_of <= 1'b0;
else if (x_hpcp_cnt_en[0])
l2_read_acc_of <= l2_read_acc_adder[64];
end
assign l2_read_acc_adder[64:0] = {1'b0,l2_read_acc_cnt[63:0]}
+ {64'b0,l2cif0_regs_read_acc_inc_x}
+ {64'b0,l2cif1_regs_read_acc_inc_x};
assign l2ra_of = l2_read_acc_of;
assign l2ra_value[63:0] = l2_read_acc_cnt[63:0];
//======================================
// L2RM
//======================================
always @(posedge l2rm_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
l2_read_miss_cnt[63:0] <= 64'b0;
else if (l2rm_wen)
l2_read_miss_cnt[63:0] <= regs_wdata_final[63:0];
else if (x_hpcp_cnt_en[1])
l2_read_miss_cnt[63:0] <= l2_read_miss_adder[63:0];
end
always @(posedge l2rm_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
l2_read_miss_of <= 1'b0;
else if (l2_read_miss_of)
l2_read_miss_of <= 1'b0;
else if (x_hpcp_cnt_en[1])
l2_read_miss_of <= l2_read_miss_adder[64];
end
assign l2_read_miss_adder[64:0] = {1'b0,l2_read_miss_cnt[63:0]}
+ {64'b0,l2cif0_regs_read_miss_inc_x}
+ {64'b0,l2cif1_regs_read_miss_inc_x};
assign l2rm_of = l2_read_miss_of;
assign l2rm_value[63:0] = l2_read_miss_cnt[63:0];
//======================================
// L2WA
//======================================
always @(posedge l2wa_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
l2_write_acc_cnt[63:0] <= 64'b0;
else if (l2wa_wen)
l2_write_acc_cnt[63:0] <= regs_wdata_final[63:0];
else if (x_hpcp_cnt_en[2])
l2_write_acc_cnt[63:0] <= l2_write_acc_adder[63:0];
end
always @(posedge l2wa_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
l2_write_acc_of <= 1'b0;
else if (l2_write_acc_of)
l2_write_acc_of <= 1'b0;
else if (x_hpcp_cnt_en[2])
l2_write_acc_of <= l2_write_acc_adder[64];
end
assign l2_write_acc_adder[64:0] = {1'b0,l2_write_acc_cnt[63:0]}
+ {64'b0,l2cif0_regs_write_acc_inc_x}
+ {64'b0,l2cif1_regs_write_acc_inc_x};
assign l2wa_of = l2_write_acc_of;
assign l2wa_value[63:0] = l2_write_acc_cnt[63:0];
//======================================
// L2WM
//======================================
always @(posedge l2wm_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
l2_write_miss_cnt[63:0] <= 64'b0;
else if (l2wm_wen)
l2_write_miss_cnt[63:0] <= regs_wdata_final[63:0];
else if (x_hpcp_cnt_en[3])
l2_write_miss_cnt[63:0] <= l2_write_miss_adder[63:0];
end
always @(posedge l2wm_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
l2_write_miss_of <= 1'b0;
else if (l2_write_miss_of)
l2_write_miss_of <= 1'b0;
else if (x_hpcp_cnt_en[3])
l2_write_miss_of <= l2_write_miss_adder[64];
end
assign l2_write_miss_adder[64:0] = {1'b0,l2_write_miss_cnt[63:0]}
+ {64'b0,l2cif0_regs_write_miss_inc_x}
+ {64'b0,l2cif1_regs_write_miss_inc_x};
assign l2wm_of = l2_write_miss_of;
assign l2wm_value[63:0] = l2_write_miss_cnt[63:0];
//======================================
// L2OF
//======================================
always @(posedge l2of_clk or negedge x_fifo_rst_b)
begin
if (!x_fifo_rst_b)
l2of_reg[3:0] <= 4'b0;
else if (l2of_wen)
l2of_reg[3:0] <= l2of_updt_data[3:0];
else
l2of_reg[3:0] <=l2of_reg[3:0] | {l2wm_of,l2wa_of,l2rm_of,l2ra_of};
end
assign l2of_updt_data[3:0] = regs_l2of_wen[3:0] & regs_wdata_final[3:0]
| (~regs_l2of_wen[3:0]) & l2of_reg[3:0];
assign l2of_value[63:0] = {60'b0,l2of_reg[3:0]};
assign x_l2of_int[3:0] = l2of_reg[3:0];
// &Force("input","x_hpcp_cnt_en"); @247
// &Force("bus", "x_hpcp_cnt_en",3,0); @248
// &Force("input", "l2cif0_regs_read_acc_inc_x"); @249
// &Force("input", "l2cif0_regs_read_miss_inc_x"); @250
// &Force("input", "l2cif0_regs_write_acc_inc_x"); @251
// &Force("input", "l2cif0_regs_write_miss_inc_x"); @252
// &Force("input", "l2cif1_regs_read_acc_inc_x"); @253
// &Force("input", "l2cif1_regs_read_miss_inc_x"); @254
// &Force("input", "l2cif1_regs_write_acc_inc_x"); @255
// &Force("input", "l2cif1_regs_write_miss_inc_x"); @256
// &Force("output", "x_l2of_int"); @257
//==========================================================
// ICG
//==========================================================
assign smpr_clk_en = smpr_wen;
// &Instance("gated_clk_cell", "x_smpr_gated_clk"); @263
gated_clk_cell x_smpr_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (smpr_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (smpr_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @264
// .external_en (1'b0), @265
// .global_en (1'b1), @266
// .module_en (ciu_icg_en), @267
// .local_en (smpr_clk_en), @268
// .clk_out (smpr_clk)); @269
// &Instance("gated_clk_cell", "x_teem_gated_clk"); @273
// &Connect(.clk_in (forever_cpuclk), @274
// .external_en (1'b0), @275
// .global_en (1'b1), @276
// .module_en (ciu_icg_en), @277
// .local_en (teem_clk_en), @278
// .clk_out (teem_clk)); @279
assign l2ra_clk_en = l2ra_wen || x_hpcp_cnt_en[0] || l2ra_of;
// &Instance("gated_clk_cell", "x_l2ra_gated_clk"); @283
gated_clk_cell x_l2ra_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (l2ra_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2ra_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @284
// .external_en (1'b0), @285
// .global_en (1'b1), @286
// .module_en (ciu_icg_en), @287
// .local_en (l2ra_clk_en), @288
// .clk_out (l2ra_clk)); @289
assign l2rm_clk_en = l2rm_wen || x_hpcp_cnt_en[1] || l2rm_of;
// &Instance("gated_clk_cell", "x_l2rm_gated_clk"); @292
gated_clk_cell x_l2rm_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (l2rm_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2rm_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @293
// .external_en (1'b0), @294
// .global_en (1'b1), @295
// .module_en (ciu_icg_en), @296
// .local_en (l2rm_clk_en), @297
// .clk_out (l2rm_clk)); @298
assign l2wa_clk_en = l2wa_wen || x_hpcp_cnt_en[2] || l2wa_of;
// &Instance("gated_clk_cell", "x_l2wa_gated_clk"); @301
gated_clk_cell x_l2wa_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (l2wa_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2wa_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @302
// .external_en (1'b0), @303
// .global_en (1'b1), @304
// .module_en (ciu_icg_en), @305
// .local_en (l2wa_clk_en), @306
// .clk_out (l2wa_clk)); @307
assign l2wm_clk_en = l2wm_wen || x_hpcp_cnt_en[3] || l2wm_of;
// &Instance("gated_clk_cell", "x_l2wm_gated_clk"); @310
gated_clk_cell x_l2wm_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (l2wm_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2wm_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @311
// .external_en (1'b0), @312
// .global_en (1'b1), @313
// .module_en (ciu_icg_en), @314
// .local_en (l2wm_clk_en), @315
// .clk_out (l2wm_clk)); @316
assign l2of_clk_en = l2of_wen || l2ra_of || l2rm_of || l2wa_of || l2wm_of;
// &Instance("gated_clk_cell", "x_l2of_gated_clk"); @319
gated_clk_cell x_l2of_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (l2of_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2of_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @320
// .external_en (1'b0), @321
// .global_en (1'b1), @322
// .module_en (ciu_icg_en), @323
// .local_en (l2of_clk_en), @324
// .clk_out (l2of_clk)); @325
// &ModuleEnd; @327
endmodule |
module ct_ciu_bmbif(
bmbif_ctcq_bar_req,
bmbif_ctcq_mid,
bmbif_ctcq_req_bus,
bmbif_ncq_bar_req,
bmbif_ncq_mid,
bmbif_ncq_req_bus,
bmbif_piu0_ctcq_grant,
bmbif_piu0_ncq_grant,
bmbif_piu0_snb0_grant,
bmbif_piu0_snb1_grant,
bmbif_piu1_ctcq_grant,
bmbif_piu1_ncq_grant,
bmbif_piu1_snb0_grant,
bmbif_piu1_snb1_grant,
bmbif_piu2_ctcq_grant,
bmbif_piu2_ncq_grant,
bmbif_piu2_snb0_grant,
bmbif_piu2_snb1_grant,
bmbif_piu3_ctcq_grant,
bmbif_piu3_ncq_grant,
bmbif_piu3_snb0_grant,
bmbif_piu3_snb1_grant,
bmbif_snb0_bar_req,
bmbif_snb0_mid,
bmbif_snb0_req_bus,
bmbif_snb1_bar_req,
bmbif_snb1_mid,
bmbif_snb1_req_bus,
ciu_icg_en,
cpurst_b,
ctcq_bmbif_bar_grant,
forever_cpuclk,
ncq_bmbif_bar_grant,
pad_yy_icg_scan_en,
piu0_bmbif_ctcq_req,
piu0_bmbif_ncq_req,
piu0_bmbif_req_bus,
piu0_bmbif_snb0_req,
piu0_bmbif_snb1_req,
piu1_bmbif_ctcq_req,
piu1_bmbif_ncq_req,
piu1_bmbif_req_bus,
piu1_bmbif_snb0_req,
piu1_bmbif_snb1_req,
piu2_bmbif_ctcq_req,
piu2_bmbif_ncq_req,
piu2_bmbif_req_bus,
piu2_bmbif_snb0_req,
piu2_bmbif_snb1_req,
piu3_bmbif_ctcq_req,
piu3_bmbif_ncq_req,
piu3_bmbif_req_bus,
piu3_bmbif_snb0_req,
piu3_bmbif_snb1_req,
snb0_bmbif_bar_grant,
snb1_bmbif_bar_grant
);
// &Ports; @19
input ciu_icg_en;
input cpurst_b;
input ctcq_bmbif_bar_grant;
input forever_cpuclk;
input ncq_bmbif_bar_grant;
input pad_yy_icg_scan_en;
input piu0_bmbif_ctcq_req;
input piu0_bmbif_ncq_req;
input [8:0] piu0_bmbif_req_bus;
input piu0_bmbif_snb0_req;
input piu0_bmbif_snb1_req;
input piu1_bmbif_ctcq_req;
input piu1_bmbif_ncq_req;
input [8:0] piu1_bmbif_req_bus;
input piu1_bmbif_snb0_req;
input piu1_bmbif_snb1_req;
input piu2_bmbif_ctcq_req;
input piu2_bmbif_ncq_req;
input [8:0] piu2_bmbif_req_bus;
input piu2_bmbif_snb0_req;
input piu2_bmbif_snb1_req;
input piu3_bmbif_ctcq_req;
input piu3_bmbif_ncq_req;
input [8:0] piu3_bmbif_req_bus;
input piu3_bmbif_snb0_req;
input piu3_bmbif_snb1_req;
input snb0_bmbif_bar_grant;
input snb1_bmbif_bar_grant;
output bmbif_ctcq_bar_req;
output [2:0] bmbif_ctcq_mid;
output [8:0] bmbif_ctcq_req_bus;
output bmbif_ncq_bar_req;
output [2:0] bmbif_ncq_mid;
output [8:0] bmbif_ncq_req_bus;
output bmbif_piu0_ctcq_grant;
output bmbif_piu0_ncq_grant;
output bmbif_piu0_snb0_grant;
output bmbif_piu0_snb1_grant;
output bmbif_piu1_ctcq_grant;
output bmbif_piu1_ncq_grant;
output bmbif_piu1_snb0_grant;
output bmbif_piu1_snb1_grant;
output bmbif_piu2_ctcq_grant;
output bmbif_piu2_ncq_grant;
output bmbif_piu2_snb0_grant;
output bmbif_piu2_snb1_grant;
output bmbif_piu3_ctcq_grant;
output bmbif_piu3_ncq_grant;
output bmbif_piu3_snb0_grant;
output bmbif_piu3_snb1_grant;
output bmbif_snb0_bar_req;
output [2:0] bmbif_snb0_mid;
output [8:0] bmbif_snb0_req_bus;
output bmbif_snb1_bar_req;
output [2:0] bmbif_snb1_mid;
output [8:0] bmbif_snb1_req_bus;
// &Regs; @20
// &Wires; @21
wire bmbif_ctcq_bar_req;
wire [2:0] bmbif_ctcq_mid;
wire [8:0] bmbif_ctcq_req_bus;
wire bmbif_ncq_bar_req;
wire [2:0] bmbif_ncq_mid;
wire [8:0] bmbif_ncq_req_bus;
wire bmbif_piu0_ctcq_grant;
wire bmbif_piu0_ncq_grant;
wire bmbif_piu0_snb0_grant;
wire bmbif_piu0_snb1_grant;
wire bmbif_piu1_ctcq_grant;
wire bmbif_piu1_ncq_grant;
wire bmbif_piu1_snb0_grant;
wire bmbif_piu1_snb1_grant;
wire bmbif_piu2_ctcq_grant;
wire bmbif_piu2_ncq_grant;
wire bmbif_piu2_snb0_grant;
wire bmbif_piu2_snb1_grant;
wire bmbif_piu3_ctcq_grant;
wire bmbif_piu3_ncq_grant;
wire bmbif_piu3_snb0_grant;
wire bmbif_piu3_snb1_grant;
wire bmbif_snb0_bar_req;
wire [2:0] bmbif_snb0_mid;
wire [8:0] bmbif_snb0_req_bus;
wire bmbif_snb1_bar_req;
wire [2:0] bmbif_snb1_mid;
wire [8:0] bmbif_snb1_req_bus;
wire ciu_icg_en;
wire cpurst_b;
wire ctcq_bmbif_bar_grant;
wire forever_cpuclk;
wire ncq_bmbif_bar_grant;
wire pad_yy_icg_scan_en;
wire piu0_bmbif_ctcq_req;
wire piu0_bmbif_ncq_req;
wire [8:0] piu0_bmbif_req_bus;
wire piu0_bmbif_snb0_req;
wire piu0_bmbif_snb1_req;
wire piu1_bmbif_ctcq_req;
wire piu1_bmbif_ncq_req;
wire [8:0] piu1_bmbif_req_bus;
wire piu1_bmbif_snb0_req;
wire piu1_bmbif_snb1_req;
wire piu2_bmbif_ctcq_req;
wire piu2_bmbif_ncq_req;
wire [8:0] piu2_bmbif_req_bus;
wire piu2_bmbif_snb0_req;
wire piu2_bmbif_snb1_req;
wire piu3_bmbif_ctcq_req;
wire piu3_bmbif_ncq_req;
wire [8:0] piu3_bmbif_req_bus;
wire piu3_bmbif_snb0_req;
wire piu3_bmbif_snb1_req;
wire snb0_bmbif_bar_grant;
wire snb1_bmbif_bar_grant;
// &ConnRule(s/xx_/snb0_/); @23
// &Instance("ct_ciu_bmbif_kid","x_ct_ciu_bmbif_snb0"); @24
ct_ciu_bmbif_kid x_ct_ciu_bmbif_snb0 (
.bmbif_piu0_xx_grant (bmbif_piu0_snb0_grant),
.bmbif_piu1_xx_grant (bmbif_piu1_snb0_grant),
.bmbif_piu2_xx_grant (bmbif_piu2_snb0_grant),
.bmbif_piu3_xx_grant (bmbif_piu3_snb0_grant),
.bmbif_xx_bar_req (bmbif_snb0_bar_req ),
.bmbif_xx_mid (bmbif_snb0_mid ),
.bmbif_xx_req_bus (bmbif_snb0_req_bus ),
.ciu_icg_en (ciu_icg_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.piu0_bmbif_req_bus (piu0_bmbif_req_bus ),
.piu0_bmbif_xx_req (piu0_bmbif_snb0_req ),
.piu1_bmbif_req_bus (piu1_bmbif_req_bus ),
.piu1_bmbif_xx_req (piu1_bmbif_snb0_req ),
.piu2_bmbif_req_bus (piu2_bmbif_req_bus ),
.piu2_bmbif_xx_req (piu2_bmbif_snb0_req ),
.piu3_bmbif_req_bus (piu3_bmbif_req_bus ),
.piu3_bmbif_xx_req (piu3_bmbif_snb0_req ),
.xx_bmbif_bar_grant (snb0_bmbif_bar_grant )
);
// &ConnRule(s/xx_/snb1_/); @26
// &Instance("ct_ciu_bmbif_kid","x_ct_ciu_bmbif_snb1"); @27
ct_ciu_bmbif_kid x_ct_ciu_bmbif_snb1 (
.bmbif_piu0_xx_grant (bmbif_piu0_snb1_grant),
.bmbif_piu1_xx_grant (bmbif_piu1_snb1_grant),
.bmbif_piu2_xx_grant (bmbif_piu2_snb1_grant),
.bmbif_piu3_xx_grant (bmbif_piu3_snb1_grant),
.bmbif_xx_bar_req (bmbif_snb1_bar_req ),
.bmbif_xx_mid (bmbif_snb1_mid ),
.bmbif_xx_req_bus (bmbif_snb1_req_bus ),
.ciu_icg_en (ciu_icg_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.piu0_bmbif_req_bus (piu0_bmbif_req_bus ),
.piu0_bmbif_xx_req (piu0_bmbif_snb1_req ),
.piu1_bmbif_req_bus (piu1_bmbif_req_bus ),
.piu1_bmbif_xx_req (piu1_bmbif_snb1_req ),
.piu2_bmbif_req_bus (piu2_bmbif_req_bus ),
.piu2_bmbif_xx_req (piu2_bmbif_snb1_req ),
.piu3_bmbif_req_bus (piu3_bmbif_req_bus ),
.piu3_bmbif_xx_req (piu3_bmbif_snb1_req ),
.xx_bmbif_bar_grant (snb1_bmbif_bar_grant )
);
// &ConnRule(s/xx_/ncq_/); @29
// &Instance("ct_ciu_bmbif_kid","x_ct_ciu_bmbif_ncq"); @30
ct_ciu_bmbif_kid x_ct_ciu_bmbif_ncq (
.bmbif_piu0_xx_grant (bmbif_piu0_ncq_grant),
.bmbif_piu1_xx_grant (bmbif_piu1_ncq_grant),
.bmbif_piu2_xx_grant (bmbif_piu2_ncq_grant),
.bmbif_piu3_xx_grant (bmbif_piu3_ncq_grant),
.bmbif_xx_bar_req (bmbif_ncq_bar_req ),
.bmbif_xx_mid (bmbif_ncq_mid ),
.bmbif_xx_req_bus (bmbif_ncq_req_bus ),
.ciu_icg_en (ciu_icg_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.piu0_bmbif_req_bus (piu0_bmbif_req_bus ),
.piu0_bmbif_xx_req (piu0_bmbif_ncq_req ),
.piu1_bmbif_req_bus (piu1_bmbif_req_bus ),
.piu1_bmbif_xx_req (piu1_bmbif_ncq_req ),
.piu2_bmbif_req_bus (piu2_bmbif_req_bus ),
.piu2_bmbif_xx_req (piu2_bmbif_ncq_req ),
.piu3_bmbif_req_bus (piu3_bmbif_req_bus ),
.piu3_bmbif_xx_req (piu3_bmbif_ncq_req ),
.xx_bmbif_bar_grant (ncq_bmbif_bar_grant )
);
// &ConnRule(s/xx_/ctcq_/); @32
// &Instance("ct_ciu_bmbif_kid","x_ct_ciu_bmbif_ctcq"); @33
ct_ciu_bmbif_kid x_ct_ciu_bmbif_ctcq (
.bmbif_piu0_xx_grant (bmbif_piu0_ctcq_grant),
.bmbif_piu1_xx_grant (bmbif_piu1_ctcq_grant),
.bmbif_piu2_xx_grant (bmbif_piu2_ctcq_grant),
.bmbif_piu3_xx_grant (bmbif_piu3_ctcq_grant),
.bmbif_xx_bar_req (bmbif_ctcq_bar_req ),
.bmbif_xx_mid (bmbif_ctcq_mid ),
.bmbif_xx_req_bus (bmbif_ctcq_req_bus ),
.ciu_icg_en (ciu_icg_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.piu0_bmbif_req_bus (piu0_bmbif_req_bus ),
.piu0_bmbif_xx_req (piu0_bmbif_ctcq_req ),
.piu1_bmbif_req_bus (piu1_bmbif_req_bus ),
.piu1_bmbif_xx_req (piu1_bmbif_ctcq_req ),
.piu2_bmbif_req_bus (piu2_bmbif_req_bus ),
.piu2_bmbif_xx_req (piu2_bmbif_ctcq_req ),
.piu3_bmbif_req_bus (piu3_bmbif_req_bus ),
.piu3_bmbif_xx_req (piu3_bmbif_ctcq_req ),
.xx_bmbif_bar_grant (ctcq_bmbif_bar_grant )
);
// &ModuleEnd; @35
endmodule |
module ct_piu_other_io(
ciu_ibiu_csr_cmplt,
ciu_ibiu_csr_rdata,
ciu_ibiu_dbgrq_b,
ciu_ibiu_hpcp_l2of_int,
ciu_ibiu_me_int,
ciu_ibiu_ms_int,
ciu_ibiu_mt_int,
ciu_ibiu_se_int,
ciu_ibiu_ss_int,
ciu_ibiu_st_int,
ciu_icg_en,
cpurst_b,
forever_cpuclk,
ibiu_ciu_cnt_en,
ibiu_ciu_csr_sel,
ibiu_ciu_csr_wdata,
ibiu_ciu_jdb_pm,
ibiu_ciu_lpmd_b,
l2cif_piu_read_data_vld,
l2cif_piux_read_data,
pad_yy_icg_scan_en,
perr_l2pmp_x,
piu_csr_sel,
piu_l2cif_read_data,
piu_l2cif_read_data_ecc,
piu_l2cif_read_index,
piu_l2cif_read_req,
piu_l2cif_read_tag,
piu_l2cif_read_tag_ecc,
piu_l2cif_read_way,
piu_regs_hpcp_cnt_en,
piu_regs_op,
piu_regs_sel,
piu_regs_wdata,
piu_sysio_jdb_pm,
piu_sysio_lpmd_b,
piu_xx_regs_no_op,
pready_l2pmp_x,
psel_l2pmp_x,
regs_piu_cmplt,
regs_piu_hpcp_l2of_int,
regs_piux_rdata,
sysio_piu_dbgrq_b,
sysio_piu_me_int,
sysio_piu_ms_int,
sysio_piu_mt_int,
sysio_piu_se_int,
sysio_piu_ss_int,
sysio_piu_st_int,
x_prdata_l2pmp
);
// &Ports; @24
input ciu_icg_en;
input cpurst_b;
input forever_cpuclk;
input [3 :0] ibiu_ciu_cnt_en;
input ibiu_ciu_csr_sel;
input [79 :0] ibiu_ciu_csr_wdata;
input ibiu_ciu_jdb_pm;
input ibiu_ciu_lpmd_b;
input l2cif_piu_read_data_vld;
input [127:0] l2cif_piux_read_data;
input pad_yy_icg_scan_en;
input psel_l2pmp_x;
input regs_piu_cmplt;
input [3 :0] regs_piu_hpcp_l2of_int;
input [63 :0] regs_piux_rdata;
input sysio_piu_dbgrq_b;
input sysio_piu_me_int;
input sysio_piu_ms_int;
input sysio_piu_mt_int;
input sysio_piu_se_int;
input sysio_piu_ss_int;
input sysio_piu_st_int;
output ciu_ibiu_csr_cmplt;
output [127:0] ciu_ibiu_csr_rdata;
output ciu_ibiu_dbgrq_b;
output [3 :0] ciu_ibiu_hpcp_l2of_int;
output ciu_ibiu_me_int;
output ciu_ibiu_ms_int;
output ciu_ibiu_mt_int;
output ciu_ibiu_se_int;
output ciu_ibiu_ss_int;
output ciu_ibiu_st_int;
output perr_l2pmp_x;
output piu_csr_sel;
output piu_l2cif_read_data;
output piu_l2cif_read_data_ecc;
output [20 :0] piu_l2cif_read_index;
output piu_l2cif_read_req;
output piu_l2cif_read_tag;
output piu_l2cif_read_tag_ecc;
output [3 :0] piu_l2cif_read_way;
output [3 :0] piu_regs_hpcp_cnt_en;
output [15 :0] piu_regs_op;
output piu_regs_sel;
output [63 :0] piu_regs_wdata;
output [1 :0] piu_sysio_jdb_pm;
output [1 :0] piu_sysio_lpmd_b;
output piu_xx_regs_no_op;
output pready_l2pmp_x;
output [31 :0] x_prdata_l2pmp;
// &Regs; @25
// &Wires; @26
wire ciu_ibiu_csr_cmplt;
wire [127:0] ciu_ibiu_csr_rdata;
wire ciu_ibiu_dbgrq_b;
wire [3 :0] ciu_ibiu_hpcp_l2of_int;
wire ciu_ibiu_me_int;
wire ciu_ibiu_ms_int;
wire ciu_ibiu_mt_int;
wire ciu_ibiu_se_int;
wire ciu_ibiu_ss_int;
wire ciu_ibiu_st_int;
wire ciu_icg_en;
wire cpurst_b;
wire forever_cpuclk;
wire [3 :0] ibiu_ciu_cnt_en;
wire ibiu_ciu_csr_sel;
wire [79 :0] ibiu_ciu_csr_wdata;
wire ibiu_ciu_jdb_pm;
wire ibiu_ciu_lpmd_b;
wire l2cif_piu_read_data_vld;
wire [127:0] l2cif_piux_read_data;
wire pad_yy_icg_scan_en;
wire perr_l2pmp_x;
wire piu_csr_sel;
wire piu_l2cif_read_data;
wire piu_l2cif_read_data_ecc;
wire [20 :0] piu_l2cif_read_index;
wire piu_l2cif_read_req;
wire piu_l2cif_read_tag;
wire piu_l2cif_read_tag_ecc;
wire [3 :0] piu_l2cif_read_way;
wire [3 :0] piu_regs_hpcp_cnt_en;
wire [15 :0] piu_regs_op;
wire piu_regs_sel;
wire [63 :0] piu_regs_wdata;
wire [1 :0] piu_sysio_jdb_pm;
wire [1 :0] piu_sysio_lpmd_b;
wire piu_xx_regs_no_op;
wire pready_l2pmp_x;
wire psel_l2pmp_x;
wire regs_piu_cmplt;
wire [3 :0] regs_piu_hpcp_l2of_int;
wire [63 :0] regs_piux_rdata;
wire sysio_piu_dbgrq_b;
wire sysio_piu_me_int;
wire sysio_piu_ms_int;
wire sysio_piu_mt_int;
wire sysio_piu_se_int;
wire sysio_piu_ss_int;
wire sysio_piu_st_int;
wire [31 :0] x_prdata_l2pmp;
// &Instance("ct_piu_other_io_async", "x_ct_piu_other_io_async"); @29
// &Instance("ct_piu_other_io_sync", "x_ct_piu_other_io_sync"); @31
ct_piu_other_io_sync x_ct_piu_other_io_sync (
.ciu_ibiu_csr_cmplt (ciu_ibiu_csr_cmplt ),
.ciu_ibiu_csr_rdata (ciu_ibiu_csr_rdata ),
.ciu_ibiu_dbgrq_b (ciu_ibiu_dbgrq_b ),
.ciu_ibiu_hpcp_l2of_int (ciu_ibiu_hpcp_l2of_int ),
.ciu_ibiu_me_int (ciu_ibiu_me_int ),
.ciu_ibiu_ms_int (ciu_ibiu_ms_int ),
.ciu_ibiu_mt_int (ciu_ibiu_mt_int ),
.ciu_ibiu_se_int (ciu_ibiu_se_int ),
.ciu_ibiu_ss_int (ciu_ibiu_ss_int ),
.ciu_ibiu_st_int (ciu_ibiu_st_int ),
.ciu_icg_en (ciu_icg_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ibiu_ciu_cnt_en (ibiu_ciu_cnt_en ),
.ibiu_ciu_csr_sel (ibiu_ciu_csr_sel ),
.ibiu_ciu_csr_wdata (ibiu_ciu_csr_wdata ),
.ibiu_ciu_jdb_pm (ibiu_ciu_jdb_pm ),
.ibiu_ciu_lpmd_b (ibiu_ciu_lpmd_b ),
.l2cif_piu_read_data_vld (l2cif_piu_read_data_vld),
.l2cif_piux_read_data (l2cif_piux_read_data ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.perr_l2pmp_x (perr_l2pmp_x ),
.piu_csr_sel (piu_csr_sel ),
.piu_l2cif_read_data (piu_l2cif_read_data ),
.piu_l2cif_read_data_ecc (piu_l2cif_read_data_ecc),
.piu_l2cif_read_index (piu_l2cif_read_index ),
.piu_l2cif_read_req (piu_l2cif_read_req ),
.piu_l2cif_read_tag (piu_l2cif_read_tag ),
.piu_l2cif_read_tag_ecc (piu_l2cif_read_tag_ecc ),
.piu_l2cif_read_way (piu_l2cif_read_way ),
.piu_regs_hpcp_cnt_en (piu_regs_hpcp_cnt_en ),
.piu_regs_op (piu_regs_op ),
.piu_regs_sel (piu_regs_sel ),
.piu_regs_wdata (piu_regs_wdata ),
.piu_sysio_jdb_pm (piu_sysio_jdb_pm ),
.piu_sysio_lpmd_b (piu_sysio_lpmd_b ),
.piu_xx_regs_no_op (piu_xx_regs_no_op ),
.pready_l2pmp_x (pready_l2pmp_x ),
.psel_l2pmp_x (psel_l2pmp_x ),
.regs_piu_cmplt (regs_piu_cmplt ),
.regs_piu_hpcp_l2of_int (regs_piu_hpcp_l2of_int ),
.regs_piux_rdata (regs_piux_rdata ),
.sysio_piu_dbgrq_b (sysio_piu_dbgrq_b ),
.sysio_piu_me_int (sysio_piu_me_int ),
.sysio_piu_ms_int (sysio_piu_ms_int ),
.sysio_piu_mt_int (sysio_piu_mt_int ),
.sysio_piu_se_int (sysio_piu_se_int ),
.sysio_piu_ss_int (sysio_piu_ss_int ),
.sysio_piu_st_int (sysio_piu_st_int ),
.x_prdata_l2pmp (x_prdata_l2pmp )
);
// &ModuleEnd; @34
endmodule |
module ct_ciu_snb(
bmbif_snb_bar_req,
bmbif_snb_mid,
bmbif_snb_req_bus,
ciu_chr2_bar_dis,
ciu_chr2_sf_dis,
ciu_icg_en,
ciu_xx_smpen,
cpurst_b,
ebiuif_snb_acvalid,
ebiuif_snb_ar_grant,
ebiuif_snb_ar_grant_gate,
ebiuif_snb_rvalid,
ebiuif_snbx_acbus,
ebiuif_xx_entry_sel,
ebiuif_xx_rdata,
ebiuif_xx_rlast,
ebiuif_xx_rresp,
forever_cpuclk,
l2c_snb_addr_grant,
l2c_snb_cmplt,
l2c_snb_cmplt_sid,
l2c_snb_cp,
l2c_snb_data,
l2c_snb_data_grant,
l2c_snb_data_grant_gate,
l2c_snb_prf_bus,
l2c_snb_prf_req,
l2c_snb_resp,
l2c_snb_snpl2_bus,
l2c_snb_snpl2_ini_sid,
l2c_snb_snpl2_req,
pad_yy_icg_scan_en,
piu0_snb_ac_grant,
piu0_snb_ar_bus,
piu0_snb_ar_req,
piu0_snb_aw_req,
piu0_snb_b_grant,
piu0_snb_back,
piu0_snb_cr_bus,
piu0_snb_cr_req,
piu0_snb_r_grant,
piu0_snb_rack,
piu0_snb_wcd_req,
piu0_snbx_back_sid,
piu0_snbx_rack_sid,
piu0_xx_aw_bus,
piu0_xx_wcd_bus,
piu1_snb_ac_grant,
piu1_snb_ar_bus,
piu1_snb_ar_req,
piu1_snb_aw_req,
piu1_snb_b_grant,
piu1_snb_back,
piu1_snb_cr_bus,
piu1_snb_cr_req,
piu1_snb_r_grant,
piu1_snb_rack,
piu1_snb_wcd_req,
piu1_snbx_back_sid,
piu1_snbx_rack_sid,
piu1_xx_aw_bus,
piu1_xx_wcd_bus,
piu2_snb_ac_grant,
piu2_snb_ar_bus,
piu2_snb_ar_req,
piu2_snb_aw_req,
piu2_snb_b_grant,
piu2_snb_back,
piu2_snb_cr_bus,
piu2_snb_cr_req,
piu2_snb_r_grant,
piu2_snb_rack,
piu2_snb_wcd_req,
piu2_snbx_back_sid,
piu2_snbx_rack_sid,
piu2_xx_aw_bus,
piu2_xx_wcd_bus,
piu3_snb_ac_grant,
piu3_snb_ar_bus,
piu3_snb_ar_req,
piu3_snb_aw_req,
piu3_snb_b_grant,
piu3_snb_back,
piu3_snb_cr_bus,
piu3_snb_cr_req,
piu3_snb_r_grant,
piu3_snb_rack,
piu3_snb_wcd_req,
piu3_snbx_back_sid,
piu3_snbx_rack_sid,
piu3_xx_aw_bus,
piu3_xx_wcd_bus,
piu4_snb_ar_bus,
piu4_snb_ar_req,
piu4_snb_aw_req,
piu4_snb_b_grant,
piu4_snb_back,
piu4_snb_r_grant,
piu4_snb_rack,
piu4_snb_wcd_req,
piu4_snbx_back_sid,
piu4_snbx_rack_sid,
piu4_xx_aw_bus,
piu4_xx_wcd_bus,
snb1,
snb_bmbif_bar_grant,
snb_dbg_info,
snb_ebiuif_ac_grant,
snb_ebiuif_arbus,
snb_ebiuif_arvalid,
snb_l2c_addr_bus,
snb_l2c_addr_req,
snb_l2c_data_bus,
snb_l2c_data_req,
snb_l2c_hpcp_bus,
snb_l2c_prf_grant,
snb_l2c_snpl2_grant,
snb_piu0_acbus,
snb_piu0_acvalid,
snb_piu0_ar_grant,
snb_piu0_aw_grant,
snb_piu0_bar_cmplt,
snb_piu0_bvalid,
snb_piu0_cr_grant,
snb_piu0_rvalid,
snb_piu0_wcd_grant,
snb_piu1_acbus,
snb_piu1_acvalid,
snb_piu1_ar_grant,
snb_piu1_aw_grant,
snb_piu1_bar_cmplt,
snb_piu1_bvalid,
snb_piu1_cr_grant,
snb_piu1_rvalid,
snb_piu1_wcd_grant,
snb_piu2_acbus,
snb_piu2_acvalid,
snb_piu2_ar_grant,
snb_piu2_aw_grant,
snb_piu2_bar_cmplt,
snb_piu2_bvalid,
snb_piu2_cr_grant,
snb_piu2_rvalid,
snb_piu2_wcd_grant,
snb_piu3_acbus,
snb_piu3_acvalid,
snb_piu3_ar_grant,
snb_piu3_aw_grant,
snb_piu3_bar_cmplt,
snb_piu3_bvalid,
snb_piu3_cr_grant,
snb_piu3_rvalid,
snb_piu3_wcd_grant,
snb_piu4_ar_grant,
snb_piu4_aw_grant,
snb_piu4_bvalid,
snb_piu4_rvalid,
snb_piu4_wcd_grant,
snb_piux_aw_sid,
snb_piux_bbus,
snb_piux_rbus,
snb_snpext_depd_ebiu,
snb_snpext_depd_vb,
snb_vb_awbus,
snb_vb_awvalid,
snb_vb_mid,
snb_vb_vid,
snb_vb_wbus,
snb_vb_wvalid,
snb_xx_no_op,
snb_yy_snpext_index,
vb_snb_aw_grant,
vb_snb_w_grant,
vb_yy_grant_id
);
// &Ports; @19
input bmbif_snb_bar_req;
input [2 :0] bmbif_snb_mid;
input [8 :0] bmbif_snb_req_bus;
input ciu_chr2_bar_dis;
input ciu_chr2_sf_dis;
input ciu_icg_en;
input [3 :0] ciu_xx_smpen;
input cpurst_b;
input ebiuif_snb_acvalid;
input ebiuif_snb_ar_grant;
input ebiuif_snb_ar_grant_gate;
input ebiuif_snb_rvalid;
input [70 :0] ebiuif_snbx_acbus;
input [23 :0] ebiuif_xx_entry_sel;
input [127:0] ebiuif_xx_rdata;
input ebiuif_xx_rlast;
input [3 :0] ebiuif_xx_rresp;
input forever_cpuclk;
input l2c_snb_addr_grant;
input l2c_snb_cmplt;
input [4 :0] l2c_snb_cmplt_sid;
input [3 :0] l2c_snb_cp;
input [511:0] l2c_snb_data;
input l2c_snb_data_grant;
input l2c_snb_data_grant_gate;
input [70 :0] l2c_snb_prf_bus;
input l2c_snb_prf_req;
input [4 :0] l2c_snb_resp;
input [70 :0] l2c_snb_snpl2_bus;
input [4 :0] l2c_snb_snpl2_ini_sid;
input l2c_snb_snpl2_req;
input pad_yy_icg_scan_en;
input piu0_snb_ac_grant;
input [70 :0] piu0_snb_ar_bus;
input piu0_snb_ar_req;
input piu0_snb_aw_req;
input piu0_snb_b_grant;
input piu0_snb_back;
input [9 :0] piu0_snb_cr_bus;
input piu0_snb_cr_req;
input piu0_snb_r_grant;
input piu0_snb_rack;
input piu0_snb_wcd_req;
input [4 :0] piu0_snbx_back_sid;
input [4 :0] piu0_snbx_rack_sid;
input [70 :0] piu0_xx_aw_bus;
input [534:0] piu0_xx_wcd_bus;
input piu1_snb_ac_grant;
input [70 :0] piu1_snb_ar_bus;
input piu1_snb_ar_req;
input piu1_snb_aw_req;
input piu1_snb_b_grant;
input piu1_snb_back;
input [9 :0] piu1_snb_cr_bus;
input piu1_snb_cr_req;
input piu1_snb_r_grant;
input piu1_snb_rack;
input piu1_snb_wcd_req;
input [4 :0] piu1_snbx_back_sid;
input [4 :0] piu1_snbx_rack_sid;
input [70 :0] piu1_xx_aw_bus;
input [534:0] piu1_xx_wcd_bus;
input piu2_snb_ac_grant;
input [70 :0] piu2_snb_ar_bus;
input piu2_snb_ar_req;
input piu2_snb_aw_req;
input piu2_snb_b_grant;
input piu2_snb_back;
input [9 :0] piu2_snb_cr_bus;
input piu2_snb_cr_req;
input piu2_snb_r_grant;
input piu2_snb_rack;
input piu2_snb_wcd_req;
input [4 :0] piu2_snbx_back_sid;
input [4 :0] piu2_snbx_rack_sid;
input [70 :0] piu2_xx_aw_bus;
input [534:0] piu2_xx_wcd_bus;
input piu3_snb_ac_grant;
input [70 :0] piu3_snb_ar_bus;
input piu3_snb_ar_req;
input piu3_snb_aw_req;
input piu3_snb_b_grant;
input piu3_snb_back;
input [9 :0] piu3_snb_cr_bus;
input piu3_snb_cr_req;
input piu3_snb_r_grant;
input piu3_snb_rack;
input piu3_snb_wcd_req;
input [4 :0] piu3_snbx_back_sid;
input [4 :0] piu3_snbx_rack_sid;
input [70 :0] piu3_xx_aw_bus;
input [534:0] piu3_xx_wcd_bus;
input [70 :0] piu4_snb_ar_bus;
input piu4_snb_ar_req;
input piu4_snb_aw_req;
input piu4_snb_b_grant;
input piu4_snb_back;
input piu4_snb_r_grant;
input piu4_snb_rack;
input piu4_snb_wcd_req;
input [4 :0] piu4_snbx_back_sid;
input [4 :0] piu4_snbx_rack_sid;
input [70 :0] piu4_xx_aw_bus;
input [534:0] piu4_xx_wcd_bus;
input snb1;
input snb_snpext_depd_ebiu;
input snb_snpext_depd_vb;
input vb_snb_aw_grant;
input vb_snb_w_grant;
input [1 :0] vb_yy_grant_id;
output snb_bmbif_bar_grant;
output [95 :0] snb_dbg_info;
output snb_ebiuif_ac_grant;
output [68 :0] snb_ebiuif_arbus;
output snb_ebiuif_arvalid;
output [63 :0] snb_l2c_addr_bus;
output snb_l2c_addr_req;
output [511:0] snb_l2c_data_bus;
output snb_l2c_data_req;
output [2 :0] snb_l2c_hpcp_bus;
output snb_l2c_prf_grant;
output snb_l2c_snpl2_grant;
output [54 :0] snb_piu0_acbus;
output snb_piu0_acvalid;
output snb_piu0_ar_grant;
output snb_piu0_aw_grant;
output snb_piu0_bar_cmplt;
output snb_piu0_bvalid;
output snb_piu0_cr_grant;
output snb_piu0_rvalid;
output snb_piu0_wcd_grant;
output [54 :0] snb_piu1_acbus;
output snb_piu1_acvalid;
output snb_piu1_ar_grant;
output snb_piu1_aw_grant;
output snb_piu1_bar_cmplt;
output snb_piu1_bvalid;
output snb_piu1_cr_grant;
output snb_piu1_rvalid;
output snb_piu1_wcd_grant;
output [54 :0] snb_piu2_acbus;
output snb_piu2_acvalid;
output snb_piu2_ar_grant;
output snb_piu2_aw_grant;
output snb_piu2_bar_cmplt;
output snb_piu2_bvalid;
output snb_piu2_cr_grant;
output snb_piu2_rvalid;
output snb_piu2_wcd_grant;
output [54 :0] snb_piu3_acbus;
output snb_piu3_acvalid;
output snb_piu3_ar_grant;
output snb_piu3_aw_grant;
output snb_piu3_bar_cmplt;
output snb_piu3_bvalid;
output snb_piu3_cr_grant;
output snb_piu3_rvalid;
output snb_piu3_wcd_grant;
output snb_piu4_ar_grant;
output snb_piu4_aw_grant;
output snb_piu4_bvalid;
output snb_piu4_rvalid;
output snb_piu4_wcd_grant;
output [4 :0] snb_piux_aw_sid;
output [13 :0] snb_piux_bbus;
output [534:0] snb_piux_rbus;
output [67 :0] snb_vb_awbus;
output snb_vb_awvalid;
output [2 :0] snb_vb_mid;
output [1 :0] snb_vb_vid;
output [534:0] snb_vb_wbus;
output snb_vb_wvalid;
output snb_xx_no_op;
output [7 :0] snb_yy_snpext_index;
// &Regs; @20
// &Wires; @21
wire [6 :0] ar_crt_entry_index;
wire arb_sab_bresp_grant;
wire [4 :0] arb_sab_bresp_grant_sid;
wire arb_sab_l2c_cmplt;
wire [4 :0] arb_sab_l2c_cmplt_sid;
wire [3 :0] arb_sab_l2c_cp;
wire [511:0] arb_sab_l2c_data;
wire arb_sab_l2c_grant;
wire [4 :0] arb_sab_l2c_resp;
wire arb_sab_no_l2c_req;
wire arb_sab_rresp_grant;
wire [4 :0] arb_sab_rresp_grant_sid;
wire [23 :0] arb_sdb_ebiu_sel;
wire [23 :0] arb_sdb_l2c_sel;
wire [6 :0] aw_crt_entry_index;
wire bmbif_snb_bar_req;
wire [2 :0] bmbif_snb_mid;
wire [8 :0] bmbif_snb_req_bus;
wire ciu_chr2_bar_dis;
wire ciu_chr2_sf_dis;
wire ciu_icg_en;
wire [3 :0] ciu_xx_smpen;
wire cpurst_b;
wire ebiuif_snb_acvalid;
wire ebiuif_snb_ar_grant;
wire ebiuif_snb_ar_grant_gate;
wire ebiuif_snb_rvalid;
wire [70 :0] ebiuif_snbx_acbus;
wire [23 :0] ebiuif_xx_entry_sel;
wire [127:0] ebiuif_xx_rdata;
wire ebiuif_xx_rlast;
wire [3 :0] ebiuif_xx_rresp;
wire forever_cpuclk;
wire l2c_snb_addr_grant;
wire l2c_snb_cmplt;
wire [4 :0] l2c_snb_cmplt_sid;
wire [3 :0] l2c_snb_cp;
wire [511:0] l2c_snb_data;
wire l2c_snb_data_grant;
wire l2c_snb_data_grant_gate;
wire [70 :0] l2c_snb_prf_bus;
wire l2c_snb_prf_req;
wire [4 :0] l2c_snb_resp;
wire [70 :0] l2c_snb_snpl2_bus;
wire [4 :0] l2c_snb_snpl2_ini_sid;
wire l2c_snb_snpl2_req;
wire pad_yy_icg_scan_en;
wire piu0_snb_ac_grant;
wire [70 :0] piu0_snb_ar_bus;
wire piu0_snb_ar_req;
wire piu0_snb_aw_req;
wire piu0_snb_b_grant;
wire piu0_snb_back;
wire [9 :0] piu0_snb_cr_bus;
wire piu0_snb_cr_req;
wire piu0_snb_r_grant;
wire piu0_snb_rack;
wire piu0_snb_wcd_req;
wire [4 :0] piu0_snbx_back_sid;
wire [4 :0] piu0_snbx_rack_sid;
wire [70 :0] piu0_xx_aw_bus;
wire [534:0] piu0_xx_wcd_bus;
wire piu1_snb_ac_grant;
wire [70 :0] piu1_snb_ar_bus;
wire piu1_snb_ar_req;
wire piu1_snb_aw_req;
wire piu1_snb_b_grant;
wire piu1_snb_back;
wire [9 :0] piu1_snb_cr_bus;
wire piu1_snb_cr_req;
wire piu1_snb_r_grant;
wire piu1_snb_rack;
wire piu1_snb_wcd_req;
wire [4 :0] piu1_snbx_back_sid;
wire [4 :0] piu1_snbx_rack_sid;
wire [70 :0] piu1_xx_aw_bus;
wire [534:0] piu1_xx_wcd_bus;
wire piu2_snb_ac_grant;
wire [70 :0] piu2_snb_ar_bus;
wire piu2_snb_ar_req;
wire piu2_snb_aw_req;
wire piu2_snb_b_grant;
wire piu2_snb_back;
wire [9 :0] piu2_snb_cr_bus;
wire piu2_snb_cr_req;
wire piu2_snb_r_grant;
wire piu2_snb_rack;
wire piu2_snb_wcd_req;
wire [4 :0] piu2_snbx_back_sid;
wire [4 :0] piu2_snbx_rack_sid;
wire [70 :0] piu2_xx_aw_bus;
wire [534:0] piu2_xx_wcd_bus;
wire piu3_snb_ac_grant;
wire [70 :0] piu3_snb_ar_bus;
wire piu3_snb_ar_req;
wire piu3_snb_aw_req;
wire piu3_snb_b_grant;
wire piu3_snb_back;
wire [9 :0] piu3_snb_cr_bus;
wire piu3_snb_cr_req;
wire piu3_snb_r_grant;
wire piu3_snb_rack;
wire piu3_snb_wcd_req;
wire [4 :0] piu3_snbx_back_sid;
wire [4 :0] piu3_snbx_rack_sid;
wire [70 :0] piu3_xx_aw_bus;
wire [534:0] piu3_xx_wcd_bus;
wire [70 :0] piu4_snb_ar_bus;
wire piu4_snb_ar_req;
wire piu4_snb_aw_req;
wire piu4_snb_b_grant;
wire piu4_snb_back;
wire piu4_snb_r_grant;
wire piu4_snb_rack;
wire piu4_snb_wcd_req;
wire [4 :0] piu4_snbx_back_sid;
wire [4 :0] piu4_snbx_rack_sid;
wire [70 :0] piu4_xx_aw_bus;
wire [534:0] piu4_xx_wcd_bus;
wire [70 :0] sab_ar_create_bus;
wire sab_ar_create_en;
wire [2 :0] sab_ar_create_mid;
wire [15 :0] sab_ar_create_sel;
wire [4 :0] sab_ar_create_snpl2_isid;
wire [14 :0] sab_arb_bresp_bus;
wire sab_arb_bresp_req;
wire [68 :0] sab_arb_ebiu_ar_bus;
wire sab_arb_ebiu_ar_req;
wire [67 :0] sab_arb_ebiu_aw_bus;
wire [2 :0] sab_arb_ebiu_aw_mid;
wire sab_arb_ebiu_aw_req;
wire [23 :0] sab_arb_ebiu_aw_sel;
wire [63 :0] sab_arb_l2c_addr_bus;
wire [2 :0] sab_arb_l2c_hpcp_bus;
wire sab_arb_l2c_req;
wire [23 :0] sab_arb_l2c_sel;
wire [23 :0] sab_arb_rresp_ctrl;
wire sab_arb_rresp_req;
wire [70 :0] sab_aw_create_bus;
wire sab_aw_create_en;
wire [2 :0] sab_aw_create_mid;
wire [7 :0] sab_aw_create_sel;
wire [23 :0] sab_back_sel;
wire [4 :0] sab_crresp_piu0;
wire [4 :0] sab_crresp_piu1;
wire [4 :0] sab_crresp_piu2;
wire [4 :0] sab_crresp_piu3;
wire [23 :0] sab_crvld_piu0;
wire [23 :0] sab_crvld_piu1;
wire [23 :0] sab_crvld_piu2;
wire [23 :0] sab_crvld_piu3;
wire [23 :0] sab_entry_busy;
wire [127:0] sab_memr_data;
wire sab_memr_grant;
wire sab_memr_last;
wire [3 :0] sab_memr_resp;
wire [23 :0] sab_memr_sel;
wire sab_memr_vld;
wire sab_memw_aw_grant;
wire sab_memw_cmplt;
wire [23 :0] sab_memw_cmplt_sel;
wire [54 :0] sab_piu0_ac_bus;
wire sab_piu0_ac_grant;
wire sab_piu0_ac_vld;
wire [54 :0] sab_piu1_ac_bus;
wire sab_piu1_ac_grant;
wire sab_piu1_ac_vld;
wire [54 :0] sab_piu2_ac_bus;
wire sab_piu2_ac_grant;
wire sab_piu2_ac_vld;
wire [54 :0] sab_piu3_ac_bus;
wire sab_piu3_ac_grant;
wire sab_piu3_ac_vld;
wire [23 :0] sab_rack_sel;
wire [3 :0] sab_snp_bar_cmplt;
wire sab_snpext_depd_vld;
wire [3 :0] sab_wcd_create_cdsel;
wire [511:0] sab_wcd_create_data;
wire [23 :0] sab_wcd_create_en;
wire sab_wcd_create_err;
wire [15 :0] sab_wcd_create_wstrb;
wire [534:0] sdb_arb_ebiu_w_bus;
wire [511:0] sdb_arb_l2c_data_bus;
wire [511:0] sdb_arb_rresp_data;
wire snb1;
wire snb_bmbif_bar_grant;
wire [95 :0] snb_dbg_info;
wire snb_ebiuif_ac_grant;
wire [68 :0] snb_ebiuif_arbus;
wire snb_ebiuif_arvalid;
wire [63 :0] snb_l2c_addr_bus;
wire snb_l2c_addr_req;
wire [511:0] snb_l2c_data_bus;
wire snb_l2c_data_req;
wire [2 :0] snb_l2c_hpcp_bus;
wire snb_l2c_prf_grant;
wire snb_l2c_snpl2_grant;
wire [54 :0] snb_piu0_acbus;
wire snb_piu0_acvalid;
wire snb_piu0_ar_grant;
wire snb_piu0_aw_grant;
wire snb_piu0_bar_cmplt;
wire snb_piu0_bvalid;
wire snb_piu0_cr_grant;
wire snb_piu0_rvalid;
wire snb_piu0_wcd_grant;
wire [54 :0] snb_piu1_acbus;
wire snb_piu1_acvalid;
wire snb_piu1_ar_grant;
wire snb_piu1_aw_grant;
wire snb_piu1_bar_cmplt;
wire snb_piu1_bvalid;
wire snb_piu1_cr_grant;
wire snb_piu1_rvalid;
wire snb_piu1_wcd_grant;
wire [54 :0] snb_piu2_acbus;
wire snb_piu2_acvalid;
wire snb_piu2_ar_grant;
wire snb_piu2_aw_grant;
wire snb_piu2_bar_cmplt;
wire snb_piu2_bvalid;
wire snb_piu2_cr_grant;
wire snb_piu2_rvalid;
wire snb_piu2_wcd_grant;
wire [54 :0] snb_piu3_acbus;
wire snb_piu3_acvalid;
wire snb_piu3_ar_grant;
wire snb_piu3_aw_grant;
wire snb_piu3_bar_cmplt;
wire snb_piu3_bvalid;
wire snb_piu3_cr_grant;
wire snb_piu3_rvalid;
wire snb_piu3_wcd_grant;
wire snb_piu4_ar_grant;
wire snb_piu4_aw_grant;
wire snb_piu4_bvalid;
wire snb_piu4_rvalid;
wire snb_piu4_wcd_grant;
wire [4 :0] snb_piux_aw_sid;
wire [13 :0] snb_piux_bbus;
wire [534:0] snb_piux_rbus;
wire snb_snpext_depd_ebiu;
wire snb_snpext_depd_vb;
wire [67 :0] snb_vb_awbus;
wire snb_vb_awvalid;
wire [2 :0] snb_vb_mid;
wire [1 :0] snb_vb_vid;
wire [534:0] snb_vb_wbus;
wire snb_vb_wvalid;
wire snb_xx_no_op;
wire [7 :0] snb_yy_snpext_index;
wire [15 :0] snpext_cen0_raw;
wire [6 :0] snpext_index;
wire snpext_vld;
wire vb_snb_aw_grant;
wire vb_snb_w_grant;
wire [1 :0] vb_yy_grant_id;
// &Force("output","snb_bmbif_bar_grant"); @23
// &Instance("ct_ciu_snb_arb", "x_ct_ciu_snb_arb"); @24
ct_ciu_snb_arb x_ct_ciu_snb_arb (
.ar_crt_entry_index (ar_crt_entry_index ),
.arb_sab_bresp_grant (arb_sab_bresp_grant ),
.arb_sab_bresp_grant_sid (arb_sab_bresp_grant_sid ),
.arb_sab_l2c_cmplt (arb_sab_l2c_cmplt ),
.arb_sab_l2c_cmplt_sid (arb_sab_l2c_cmplt_sid ),
.arb_sab_l2c_cp (arb_sab_l2c_cp ),
.arb_sab_l2c_data (arb_sab_l2c_data ),
.arb_sab_l2c_grant (arb_sab_l2c_grant ),
.arb_sab_l2c_resp (arb_sab_l2c_resp ),
.arb_sab_no_l2c_req (arb_sab_no_l2c_req ),
.arb_sab_rresp_grant (arb_sab_rresp_grant ),
.arb_sab_rresp_grant_sid (arb_sab_rresp_grant_sid ),
.arb_sdb_ebiu_sel (arb_sdb_ebiu_sel ),
.arb_sdb_l2c_sel (arb_sdb_l2c_sel ),
.aw_crt_entry_index (aw_crt_entry_index ),
.bmbif_snb_bar_req (bmbif_snb_bar_req ),
.bmbif_snb_mid (bmbif_snb_mid ),
.bmbif_snb_req_bus (bmbif_snb_req_bus ),
.ciu_icg_en (ciu_icg_en ),
.cpurst_b (cpurst_b ),
.ebiuif_snb_acvalid (ebiuif_snb_acvalid ),
.ebiuif_snb_ar_grant (ebiuif_snb_ar_grant ),
.ebiuif_snb_ar_grant_gate (ebiuif_snb_ar_grant_gate),
.ebiuif_snb_rvalid (ebiuif_snb_rvalid ),
.ebiuif_snbx_acbus (ebiuif_snbx_acbus ),
.ebiuif_xx_entry_sel (ebiuif_xx_entry_sel ),
.ebiuif_xx_rdata (ebiuif_xx_rdata ),
.ebiuif_xx_rlast (ebiuif_xx_rlast ),
.ebiuif_xx_rresp (ebiuif_xx_rresp ),
.forever_cpuclk (forever_cpuclk ),
.l2c_snb_addr_grant (l2c_snb_addr_grant ),
.l2c_snb_cmplt (l2c_snb_cmplt ),
.l2c_snb_cmplt_sid (l2c_snb_cmplt_sid ),
.l2c_snb_cp (l2c_snb_cp ),
.l2c_snb_data (l2c_snb_data ),
.l2c_snb_data_grant (l2c_snb_data_grant ),
.l2c_snb_data_grant_gate (l2c_snb_data_grant_gate ),
.l2c_snb_prf_bus (l2c_snb_prf_bus ),
.l2c_snb_prf_req (l2c_snb_prf_req ),
.l2c_snb_resp (l2c_snb_resp ),
.l2c_snb_snpl2_bus (l2c_snb_snpl2_bus ),
.l2c_snb_snpl2_ini_sid (l2c_snb_snpl2_ini_sid ),
.l2c_snb_snpl2_req (l2c_snb_snpl2_req ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.piu0_snb_ac_grant (piu0_snb_ac_grant ),
.piu0_snb_ar_bus (piu0_snb_ar_bus ),
.piu0_snb_ar_req (piu0_snb_ar_req ),
.piu0_snb_aw_req (piu0_snb_aw_req ),
.piu0_snb_b_grant (piu0_snb_b_grant ),
.piu0_snb_back (piu0_snb_back ),
.piu0_snb_cr_bus (piu0_snb_cr_bus ),
.piu0_snb_cr_req (piu0_snb_cr_req ),
.piu0_snb_r_grant (piu0_snb_r_grant ),
.piu0_snb_rack (piu0_snb_rack ),
.piu0_snb_wcd_req (piu0_snb_wcd_req ),
.piu0_snbx_back_sid (piu0_snbx_back_sid ),
.piu0_snbx_rack_sid (piu0_snbx_rack_sid ),
.piu0_xx_aw_bus (piu0_xx_aw_bus ),
.piu0_xx_wcd_bus (piu0_xx_wcd_bus ),
.piu1_snb_ac_grant (piu1_snb_ac_grant ),
.piu1_snb_ar_bus (piu1_snb_ar_bus ),
.piu1_snb_ar_req (piu1_snb_ar_req ),
.piu1_snb_aw_req (piu1_snb_aw_req ),
.piu1_snb_b_grant (piu1_snb_b_grant ),
.piu1_snb_back (piu1_snb_back ),
.piu1_snb_cr_bus (piu1_snb_cr_bus ),
.piu1_snb_cr_req (piu1_snb_cr_req ),
.piu1_snb_r_grant (piu1_snb_r_grant ),
.piu1_snb_rack (piu1_snb_rack ),
.piu1_snb_wcd_req (piu1_snb_wcd_req ),
.piu1_snbx_back_sid (piu1_snbx_back_sid ),
.piu1_snbx_rack_sid (piu1_snbx_rack_sid ),
.piu1_xx_aw_bus (piu1_xx_aw_bus ),
.piu1_xx_wcd_bus (piu1_xx_wcd_bus ),
.piu2_snb_ac_grant (piu2_snb_ac_grant ),
.piu2_snb_ar_bus (piu2_snb_ar_bus ),
.piu2_snb_ar_req (piu2_snb_ar_req ),
.piu2_snb_aw_req (piu2_snb_aw_req ),
.piu2_snb_b_grant (piu2_snb_b_grant ),
.piu2_snb_back (piu2_snb_back ),
.piu2_snb_cr_bus (piu2_snb_cr_bus ),
.piu2_snb_cr_req (piu2_snb_cr_req ),
.piu2_snb_r_grant (piu2_snb_r_grant ),
.piu2_snb_rack (piu2_snb_rack ),
.piu2_snb_wcd_req (piu2_snb_wcd_req ),
.piu2_snbx_back_sid (piu2_snbx_back_sid ),
.piu2_snbx_rack_sid (piu2_snbx_rack_sid ),
.piu2_xx_aw_bus (piu2_xx_aw_bus ),
.piu2_xx_wcd_bus (piu2_xx_wcd_bus ),
.piu3_snb_ac_grant (piu3_snb_ac_grant ),
.piu3_snb_ar_bus (piu3_snb_ar_bus ),
.piu3_snb_ar_req (piu3_snb_ar_req ),
.piu3_snb_aw_req (piu3_snb_aw_req ),
.piu3_snb_b_grant (piu3_snb_b_grant ),
.piu3_snb_back (piu3_snb_back ),
.piu3_snb_cr_bus (piu3_snb_cr_bus ),
.piu3_snb_cr_req (piu3_snb_cr_req ),
.piu3_snb_r_grant (piu3_snb_r_grant ),
.piu3_snb_rack (piu3_snb_rack ),
.piu3_snb_wcd_req (piu3_snb_wcd_req ),
.piu3_snbx_back_sid (piu3_snbx_back_sid ),
.piu3_snbx_rack_sid (piu3_snbx_rack_sid ),
.piu3_xx_aw_bus (piu3_xx_aw_bus ),
.piu3_xx_wcd_bus (piu3_xx_wcd_bus ),
.piu4_snb_ar_bus (piu4_snb_ar_bus ),
.piu4_snb_ar_req (piu4_snb_ar_req ),
.piu4_snb_aw_req (piu4_snb_aw_req ),
.piu4_snb_b_grant (piu4_snb_b_grant ),
.piu4_snb_back (piu4_snb_back ),
.piu4_snb_r_grant (piu4_snb_r_grant ),
.piu4_snb_rack (piu4_snb_rack ),
.piu4_snb_wcd_req (piu4_snb_wcd_req ),
.piu4_snbx_back_sid (piu4_snbx_back_sid ),
.piu4_snbx_rack_sid (piu4_snbx_rack_sid ),
.piu4_xx_aw_bus (piu4_xx_aw_bus ),
.piu4_xx_wcd_bus (piu4_xx_wcd_bus ),
.sab_ar_create_bus (sab_ar_create_bus ),
.sab_ar_create_en (sab_ar_create_en ),
.sab_ar_create_mid (sab_ar_create_mid ),
.sab_ar_create_sel (sab_ar_create_sel ),
.sab_ar_create_snpl2_isid (sab_ar_create_snpl2_isid),
.sab_arb_bresp_bus (sab_arb_bresp_bus ),
.sab_arb_bresp_req (sab_arb_bresp_req ),
.sab_arb_ebiu_ar_bus (sab_arb_ebiu_ar_bus ),
.sab_arb_ebiu_ar_req (sab_arb_ebiu_ar_req ),
.sab_arb_ebiu_aw_bus (sab_arb_ebiu_aw_bus ),
.sab_arb_ebiu_aw_mid (sab_arb_ebiu_aw_mid ),
.sab_arb_ebiu_aw_req (sab_arb_ebiu_aw_req ),
.sab_arb_ebiu_aw_sel (sab_arb_ebiu_aw_sel ),
.sab_arb_l2c_addr_bus (sab_arb_l2c_addr_bus ),
.sab_arb_l2c_hpcp_bus (sab_arb_l2c_hpcp_bus ),
.sab_arb_l2c_req (sab_arb_l2c_req ),
.sab_arb_l2c_sel (sab_arb_l2c_sel ),
.sab_arb_rresp_ctrl (sab_arb_rresp_ctrl ),
.sab_arb_rresp_req (sab_arb_rresp_req ),
.sab_aw_create_bus (sab_aw_create_bus ),
.sab_aw_create_en (sab_aw_create_en ),
.sab_aw_create_mid (sab_aw_create_mid ),
.sab_aw_create_sel (sab_aw_create_sel ),
.sab_back_sel (sab_back_sel ),
.sab_crresp_piu0 (sab_crresp_piu0 ),
.sab_crresp_piu1 (sab_crresp_piu1 ),
.sab_crresp_piu2 (sab_crresp_piu2 ),
.sab_crresp_piu3 (sab_crresp_piu3 ),
.sab_crvld_piu0 (sab_crvld_piu0 ),
.sab_crvld_piu1 (sab_crvld_piu1 ),
.sab_crvld_piu2 (sab_crvld_piu2 ),
.sab_crvld_piu3 (sab_crvld_piu3 ),
.sab_entry_busy (sab_entry_busy ),
.sab_memr_data (sab_memr_data ),
.sab_memr_grant (sab_memr_grant ),
.sab_memr_last (sab_memr_last ),
.sab_memr_resp (sab_memr_resp ),
.sab_memr_sel (sab_memr_sel ),
.sab_memr_vld (sab_memr_vld ),
.sab_memw_aw_grant (sab_memw_aw_grant ),
.sab_memw_cmplt (sab_memw_cmplt ),
.sab_memw_cmplt_sel (sab_memw_cmplt_sel ),
.sab_piu0_ac_bus (sab_piu0_ac_bus ),
.sab_piu0_ac_grant (sab_piu0_ac_grant ),
.sab_piu0_ac_vld (sab_piu0_ac_vld ),
.sab_piu1_ac_bus (sab_piu1_ac_bus ),
.sab_piu1_ac_grant (sab_piu1_ac_grant ),
.sab_piu1_ac_vld (sab_piu1_ac_vld ),
.sab_piu2_ac_bus (sab_piu2_ac_bus ),
.sab_piu2_ac_grant (sab_piu2_ac_grant ),
.sab_piu2_ac_vld (sab_piu2_ac_vld ),
.sab_piu3_ac_bus (sab_piu3_ac_bus ),
.sab_piu3_ac_grant (sab_piu3_ac_grant ),
.sab_piu3_ac_vld (sab_piu3_ac_vld ),
.sab_rack_sel (sab_rack_sel ),
.sab_snp_bar_cmplt (sab_snp_bar_cmplt ),
.sab_snpext_depd_vld (sab_snpext_depd_vld ),
.sab_wcd_create_cdsel (sab_wcd_create_cdsel ),
.sab_wcd_create_data (sab_wcd_create_data ),
.sab_wcd_create_en (sab_wcd_create_en ),
.sab_wcd_create_err (sab_wcd_create_err ),
.sab_wcd_create_wstrb (sab_wcd_create_wstrb ),
.sdb_arb_ebiu_w_bus (sdb_arb_ebiu_w_bus ),
.sdb_arb_l2c_data_bus (sdb_arb_l2c_data_bus ),
.sdb_arb_rresp_data (sdb_arb_rresp_data ),
.snb1 (snb1 ),
.snb_bmbif_bar_grant (snb_bmbif_bar_grant ),
.snb_ebiuif_ac_grant (snb_ebiuif_ac_grant ),
.snb_ebiuif_arbus (snb_ebiuif_arbus ),
.snb_ebiuif_arvalid (snb_ebiuif_arvalid ),
.snb_l2c_addr_bus (snb_l2c_addr_bus ),
.snb_l2c_addr_req (snb_l2c_addr_req ),
.snb_l2c_data_bus (snb_l2c_data_bus ),
.snb_l2c_data_req (snb_l2c_data_req ),
.snb_l2c_hpcp_bus (snb_l2c_hpcp_bus ),
.snb_l2c_prf_grant (snb_l2c_prf_grant ),
.snb_l2c_snpl2_grant (snb_l2c_snpl2_grant ),
.snb_piu0_acbus (snb_piu0_acbus ),
.snb_piu0_acvalid (snb_piu0_acvalid ),
.snb_piu0_ar_grant (snb_piu0_ar_grant ),
.snb_piu0_aw_grant (snb_piu0_aw_grant ),
.snb_piu0_bar_cmplt (snb_piu0_bar_cmplt ),
.snb_piu0_bvalid (snb_piu0_bvalid ),
.snb_piu0_cr_grant (snb_piu0_cr_grant ),
.snb_piu0_rvalid (snb_piu0_rvalid ),
.snb_piu0_wcd_grant (snb_piu0_wcd_grant ),
.snb_piu1_acbus (snb_piu1_acbus ),
.snb_piu1_acvalid (snb_piu1_acvalid ),
.snb_piu1_ar_grant (snb_piu1_ar_grant ),
.snb_piu1_aw_grant (snb_piu1_aw_grant ),
.snb_piu1_bar_cmplt (snb_piu1_bar_cmplt ),
.snb_piu1_bvalid (snb_piu1_bvalid ),
.snb_piu1_cr_grant (snb_piu1_cr_grant ),
.snb_piu1_rvalid (snb_piu1_rvalid ),
.snb_piu1_wcd_grant (snb_piu1_wcd_grant ),
.snb_piu2_acbus (snb_piu2_acbus ),
.snb_piu2_acvalid (snb_piu2_acvalid ),
.snb_piu2_ar_grant (snb_piu2_ar_grant ),
.snb_piu2_aw_grant (snb_piu2_aw_grant ),
.snb_piu2_bar_cmplt (snb_piu2_bar_cmplt ),
.snb_piu2_bvalid (snb_piu2_bvalid ),
.snb_piu2_cr_grant (snb_piu2_cr_grant ),
.snb_piu2_rvalid (snb_piu2_rvalid ),
.snb_piu2_wcd_grant (snb_piu2_wcd_grant ),
.snb_piu3_acbus (snb_piu3_acbus ),
.snb_piu3_acvalid (snb_piu3_acvalid ),
.snb_piu3_ar_grant (snb_piu3_ar_grant ),
.snb_piu3_aw_grant (snb_piu3_aw_grant ),
.snb_piu3_bar_cmplt (snb_piu3_bar_cmplt ),
.snb_piu3_bvalid (snb_piu3_bvalid ),
.snb_piu3_cr_grant (snb_piu3_cr_grant ),
.snb_piu3_rvalid (snb_piu3_rvalid ),
.snb_piu3_wcd_grant (snb_piu3_wcd_grant ),
.snb_piu4_ar_grant (snb_piu4_ar_grant ),
.snb_piu4_aw_grant (snb_piu4_aw_grant ),
.snb_piu4_bvalid (snb_piu4_bvalid ),
.snb_piu4_rvalid (snb_piu4_rvalid ),
.snb_piu4_wcd_grant (snb_piu4_wcd_grant ),
.snb_piux_aw_sid (snb_piux_aw_sid ),
.snb_piux_bbus (snb_piux_bbus ),
.snb_piux_rbus (snb_piux_rbus ),
.snb_snpext_depd_ebiu (snb_snpext_depd_ebiu ),
.snb_snpext_depd_vb (snb_snpext_depd_vb ),
.snb_vb_awbus (snb_vb_awbus ),
.snb_vb_awvalid (snb_vb_awvalid ),
.snb_vb_mid (snb_vb_mid ),
.snb_vb_vid (snb_vb_vid ),
.snb_vb_wbus (snb_vb_wbus ),
.snb_vb_wvalid (snb_vb_wvalid ),
.snb_xx_no_op (snb_xx_no_op ),
.snb_yy_snpext_index (snb_yy_snpext_index ),
.snpext_cen0_raw (snpext_cen0_raw ),
.snpext_index (snpext_index ),
.snpext_vld (snpext_vld ),
.vb_snb_aw_grant (vb_snb_aw_grant ),
.vb_snb_w_grant (vb_snb_w_grant ),
.vb_yy_grant_id (vb_yy_grant_id )
);
// &Instance("ct_ciu_snb_sab", "x_ct_ciu_snb_sab"); @26
ct_ciu_snb_sab x_ct_ciu_snb_sab (
.ar_crt_entry_index (ar_crt_entry_index ),
.arb_sab_bresp_grant (arb_sab_bresp_grant ),
.arb_sab_bresp_grant_sid (arb_sab_bresp_grant_sid ),
.arb_sab_l2c_cmplt (arb_sab_l2c_cmplt ),
.arb_sab_l2c_cmplt_sid (arb_sab_l2c_cmplt_sid ),
.arb_sab_l2c_cp (arb_sab_l2c_cp ),
.arb_sab_l2c_data (arb_sab_l2c_data ),
.arb_sab_l2c_grant (arb_sab_l2c_grant ),
.arb_sab_l2c_resp (arb_sab_l2c_resp ),
.arb_sab_no_l2c_req (arb_sab_no_l2c_req ),
.arb_sab_rresp_grant (arb_sab_rresp_grant ),
.arb_sab_rresp_grant_sid (arb_sab_rresp_grant_sid ),
.arb_sdb_ebiu_sel (arb_sdb_ebiu_sel ),
.arb_sdb_l2c_sel (arb_sdb_l2c_sel ),
.aw_crt_entry_index (aw_crt_entry_index ),
.ciu_chr2_bar_dis (ciu_chr2_bar_dis ),
.ciu_chr2_sf_dis (ciu_chr2_sf_dis ),
.ciu_icg_en (ciu_icg_en ),
.ciu_xx_smpen (ciu_xx_smpen ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.sab_ar_create_bus (sab_ar_create_bus ),
.sab_ar_create_en (sab_ar_create_en ),
.sab_ar_create_mid (sab_ar_create_mid ),
.sab_ar_create_sel (sab_ar_create_sel ),
.sab_ar_create_snpl2_isid (sab_ar_create_snpl2_isid),
.sab_arb_bresp_bus (sab_arb_bresp_bus ),
.sab_arb_bresp_req (sab_arb_bresp_req ),
.sab_arb_ebiu_ar_bus (sab_arb_ebiu_ar_bus ),
.sab_arb_ebiu_ar_req (sab_arb_ebiu_ar_req ),
.sab_arb_ebiu_aw_bus (sab_arb_ebiu_aw_bus ),
.sab_arb_ebiu_aw_mid (sab_arb_ebiu_aw_mid ),
.sab_arb_ebiu_aw_req (sab_arb_ebiu_aw_req ),
.sab_arb_ebiu_aw_sel (sab_arb_ebiu_aw_sel ),
.sab_arb_l2c_addr_bus (sab_arb_l2c_addr_bus ),
.sab_arb_l2c_hpcp_bus (sab_arb_l2c_hpcp_bus ),
.sab_arb_l2c_req (sab_arb_l2c_req ),
.sab_arb_l2c_sel (sab_arb_l2c_sel ),
.sab_arb_rresp_ctrl (sab_arb_rresp_ctrl ),
.sab_arb_rresp_req (sab_arb_rresp_req ),
.sab_aw_create_bus (sab_aw_create_bus ),
.sab_aw_create_en (sab_aw_create_en ),
.sab_aw_create_mid (sab_aw_create_mid ),
.sab_aw_create_sel (sab_aw_create_sel ),
.sab_back_sel (sab_back_sel ),
.sab_crresp_piu0 (sab_crresp_piu0 ),
.sab_crresp_piu1 (sab_crresp_piu1 ),
.sab_crresp_piu2 (sab_crresp_piu2 ),
.sab_crresp_piu3 (sab_crresp_piu3 ),
.sab_crvld_piu0 (sab_crvld_piu0 ),
.sab_crvld_piu1 (sab_crvld_piu1 ),
.sab_crvld_piu2 (sab_crvld_piu2 ),
.sab_crvld_piu3 (sab_crvld_piu3 ),
.sab_entry_busy (sab_entry_busy ),
.sab_memr_data (sab_memr_data ),
.sab_memr_grant (sab_memr_grant ),
.sab_memr_last (sab_memr_last ),
.sab_memr_resp (sab_memr_resp ),
.sab_memr_sel (sab_memr_sel ),
.sab_memr_vld (sab_memr_vld ),
.sab_memw_aw_grant (sab_memw_aw_grant ),
.sab_memw_cmplt (sab_memw_cmplt ),
.sab_memw_cmplt_sel (sab_memw_cmplt_sel ),
.sab_piu0_ac_bus (sab_piu0_ac_bus ),
.sab_piu0_ac_grant (sab_piu0_ac_grant ),
.sab_piu0_ac_vld (sab_piu0_ac_vld ),
.sab_piu1_ac_bus (sab_piu1_ac_bus ),
.sab_piu1_ac_grant (sab_piu1_ac_grant ),
.sab_piu1_ac_vld (sab_piu1_ac_vld ),
.sab_piu2_ac_bus (sab_piu2_ac_bus ),
.sab_piu2_ac_grant (sab_piu2_ac_grant ),
.sab_piu2_ac_vld (sab_piu2_ac_vld ),
.sab_piu3_ac_bus (sab_piu3_ac_bus ),
.sab_piu3_ac_grant (sab_piu3_ac_grant ),
.sab_piu3_ac_vld (sab_piu3_ac_vld ),
.sab_rack_sel (sab_rack_sel ),
.sab_snp_bar_cmplt (sab_snp_bar_cmplt ),
.sab_snpext_depd_vld (sab_snpext_depd_vld ),
.sab_wcd_create_cdsel (sab_wcd_create_cdsel ),
.sab_wcd_create_data (sab_wcd_create_data ),
.sab_wcd_create_en (sab_wcd_create_en ),
.sab_wcd_create_err (sab_wcd_create_err ),
.sab_wcd_create_wstrb (sab_wcd_create_wstrb ),
.sdb_arb_ebiu_w_bus (sdb_arb_ebiu_w_bus ),
.sdb_arb_l2c_data_bus (sdb_arb_l2c_data_bus ),
.sdb_arb_rresp_data (sdb_arb_rresp_data ),
.snb1 (snb1 ),
.snb_dbg_info (snb_dbg_info ),
.snpext_cen0_raw (snpext_cen0_raw ),
.snpext_index (snpext_index ),
.snpext_vld (snpext_vld )
);
// &ModuleEnd; @29
endmodule |
module ct_ebiu_lowpower(
clk_en,
cpurst_b,
ebiu_pad_cactive,
ebiu_pad_csysack,
ebiu_read_channel_no_op,
ebiu_snoop_channel_no_op,
ebiu_write_channel_no_op,
ebiu_xx_no_op,
forever_cpuclk,
pad_ebiu_csysreq
);
// &Ports; @24
input clk_en;
input cpurst_b;
input ebiu_read_channel_no_op;
input ebiu_snoop_channel_no_op;
input ebiu_write_channel_no_op;
input forever_cpuclk;
input pad_ebiu_csysreq;
output ebiu_pad_cactive;
output ebiu_pad_csysack;
output ebiu_xx_no_op;
// &Regs; @25
reg ebiu_pad_csysack;
// &Wires; @26
wire clk_en;
wire cpurst_b;
wire ebiu_pad_cactive;
wire ebiu_read_channel_no_op;
wire ebiu_snoop_channel_no_op;
wire ebiu_write_channel_no_op;
wire ebiu_xx_no_op;
wire forever_cpuclk;
wire pad_ebiu_csysreq;
//==========================================================
// EBIU no_op
//==========================================================
assign ebiu_xx_no_op = ebiu_write_channel_no_op & ebiu_snoop_channel_no_op & ebiu_read_channel_no_op;
//==========================================================
// low power handshake with interconnect clock controller
//==========================================================
assign ebiu_pad_cactive = 1'b1;
always@(posedge forever_cpuclk or negedge cpurst_b)
begin
if(~cpurst_b)
ebiu_pad_csysack <= 1'b1;
else if(clk_en)
begin
if(~pad_ebiu_csysreq)
ebiu_pad_csysack <= 1'b0;
else
ebiu_pad_csysack <= 1'b1;
end
end
// &ModuleEnd; @52
endmodule |
module ct_ciu_regs(
ciu_apbif_had_pctrace_inv,
ciu_chr2_bar_dis,
ciu_chr2_dvm_dis,
ciu_chr2_sf_dis,
ciu_global_icg_en,
ciu_icg_en,
ciu_l2c_data_latency,
ciu_l2c_data_setup,
ciu_l2c_iprf,
ciu_l2c_rst_req,
ciu_l2c_tag_latency,
ciu_l2c_tag_setup,
ciu_l2c_tprf,
ciu_so_ostd_dis,
ciu_sysio_icg_en,
ciu_xx_smpen,
core0_fifo_rst_b,
core1_fifo_rst_b,
cpurst_b,
forever_cpuclk,
l2c_icg_en,
l2c_plic_ecc_int_vld,
l2cif0_regs_read_acc_inc,
l2cif0_regs_read_miss_inc,
l2cif0_regs_write_acc_inc,
l2cif0_regs_write_miss_inc,
l2cif1_regs_read_acc_inc,
l2cif1_regs_read_miss_inc,
l2cif1_regs_write_acc_inc,
l2cif1_regs_write_miss_inc,
pad_yy_icg_scan_en,
piu0_regs_hpcp_cnt_en,
piu0_regs_op,
piu0_regs_sel,
piu0_regs_wdata,
piu1_regs_hpcp_cnt_en,
piu1_regs_op,
piu1_regs_sel,
piu1_regs_wdata,
piu2_regs_op,
piu2_regs_sel,
piu2_regs_wdata,
piu3_regs_op,
piu3_regs_sel,
piu3_regs_wdata,
regs_apbif_icg_en,
regs_piu0_cmplt,
regs_piu0_hpcp_l2of_int,
regs_piu1_cmplt,
regs_piu1_hpcp_l2of_int,
regs_piu2_cmplt,
regs_piu3_cmplt,
regs_piux_rdata
);
// &Ports; @23
input core0_fifo_rst_b;
input core1_fifo_rst_b;
input cpurst_b;
input forever_cpuclk;
input [3 :0] l2cif0_regs_read_acc_inc;
input [3 :0] l2cif0_regs_read_miss_inc;
input [3 :0] l2cif0_regs_write_acc_inc;
input [3 :0] l2cif0_regs_write_miss_inc;
input [3 :0] l2cif1_regs_read_acc_inc;
input [3 :0] l2cif1_regs_read_miss_inc;
input [3 :0] l2cif1_regs_write_acc_inc;
input [3 :0] l2cif1_regs_write_miss_inc;
input pad_yy_icg_scan_en;
input [3 :0] piu0_regs_hpcp_cnt_en;
input [15:0] piu0_regs_op;
input piu0_regs_sel;
input [63:0] piu0_regs_wdata;
input [3 :0] piu1_regs_hpcp_cnt_en;
input [15:0] piu1_regs_op;
input piu1_regs_sel;
input [63:0] piu1_regs_wdata;
input [15:0] piu2_regs_op;
input piu2_regs_sel;
input [63:0] piu2_regs_wdata;
input [15:0] piu3_regs_op;
input piu3_regs_sel;
input [63:0] piu3_regs_wdata;
output ciu_apbif_had_pctrace_inv;
output ciu_chr2_bar_dis;
output ciu_chr2_dvm_dis;
output ciu_chr2_sf_dis;
output ciu_global_icg_en;
output ciu_icg_en;
output [2 :0] ciu_l2c_data_latency;
output ciu_l2c_data_setup;
output [1 :0] ciu_l2c_iprf;
output ciu_l2c_rst_req;
output [2 :0] ciu_l2c_tag_latency;
output ciu_l2c_tag_setup;
output ciu_l2c_tprf;
output ciu_so_ostd_dis;
output ciu_sysio_icg_en;
output [3 :0] ciu_xx_smpen;
output l2c_icg_en;
output l2c_plic_ecc_int_vld;
output regs_apbif_icg_en;
output regs_piu0_cmplt;
output [3 :0] regs_piu0_hpcp_l2of_int;
output regs_piu1_cmplt;
output [3 :0] regs_piu1_hpcp_l2of_int;
output regs_piu2_cmplt;
output regs_piu3_cmplt;
output [63:0] regs_piux_rdata;
// &Regs; @24
reg [10:0] chr2_data;
reg [2 :0] ciu_ccr2_dltncy;
reg ciu_ccr2_dsetup;
reg [1 :0] ciu_ccr2_iprf;
reg [2 :0] ciu_ccr2_tltncy;
reg ciu_ccr2_tprf;
reg ciu_ccr2_tsetup;
reg [63:0] private_csr_value;
reg [1 :0] regs_cur_state;
reg [63:0] regs_dout;
reg [1 :0] regs_next_state;
reg [11:0] regs_op;
reg [63:0] regs_rdata;
reg [3 :0] regs_sel;
reg [3 :0] regs_sel_ff;
reg [63:0] regs_wdata;
reg rvba_rst;
// &Wires; @25
wire ccr2_clk;
wire ccr2_clk_en;
wire ccr2_wen;
wire chr2_clk;
wire chr2_clk_en;
wire ciu_apbif_had_pctrace_inv;
wire [63:0] ciu_ccr2;
wire ciu_ccr2_eccen;
wire [63:0] ciu_cer2;
wire [63:0] ciu_chr2;
wire ciu_chr2_bar_dis;
wire ciu_chr2_dvm_dis;
wire ciu_chr2_sf_dis;
wire [63:0] ciu_eir2;
wire ciu_global_icg_en;
wire ciu_icg_en;
wire [2 :0] ciu_l2c_data_latency;
wire ciu_l2c_data_setup;
wire [1 :0] ciu_l2c_iprf;
wire ciu_l2c_rst_req;
wire [2 :0] ciu_l2c_tag_latency;
wire ciu_l2c_tag_setup;
wire ciu_l2c_tprf;
wire ciu_so_ostd_dis;
wire ciu_sysio_icg_en;
wire [3 :0] ciu_xx_smpen;
wire [63:0] core0_csr_value;
wire core0_fifo_rst_b;
wire [3 :0] core0_hpcp_cnt_en;
wire [3 :0] core0_l2of_int;
wire [63:0] core1_csr_value;
wire core1_fifo_rst_b;
wire [3 :0] core1_hpcp_cnt_en;
wire [3 :0] core1_l2of_int;
wire [63:0] core2_csr_value;
wire [63:0] core3_csr_value;
wire cpurst_b;
wire ctrl_clk;
wire ctrl_clk_en;
wire forever_cpuclk;
wire hint2_wen;
wire l2c_icg_en;
wire l2c_plic_ecc_int_vld;
wire [3 :0] l2cif0_regs_read_acc_inc;
wire [3 :0] l2cif0_regs_read_miss_inc;
wire [3 :0] l2cif0_regs_write_acc_inc;
wire [3 :0] l2cif0_regs_write_miss_inc;
wire [3 :0] l2cif1_regs_read_acc_inc;
wire [3 :0] l2cif1_regs_read_miss_inc;
wire [3 :0] l2cif1_regs_write_acc_inc;
wire [3 :0] l2cif1_regs_write_miss_inc;
wire pad_yy_icg_scan_en;
wire [3 :0] piu0_regs_hpcp_cnt_en;
wire [15:0] piu0_regs_op;
wire piu0_regs_sel;
wire [63:0] piu0_regs_wdata;
wire [3 :0] piu1_regs_hpcp_cnt_en;
wire [15:0] piu1_regs_op;
wire piu1_regs_sel;
wire [63:0] piu1_regs_wdata;
wire [15:0] piu2_regs_op;
wire piu2_regs_sel;
wire [63:0] piu2_regs_wdata;
wire [15:0] piu3_regs_op;
wire piu3_regs_sel;
wire [63:0] piu3_regs_wdata;
wire rdata_clk;
wire rdata_clk_en;
wire regs_apbif_icg_en;
wire regs_csrrc;
wire regs_csrrs;
wire regs_csrrw;
wire regs_cur_idle;
wire regs_cur_read;
wire regs_cur_write;
wire [3 :0] regs_idx;
wire [3 :0] regs_l2of_wen;
wire regs_piu0_cmplt;
wire [3 :0] regs_piu0_hpcp_l2of_int;
wire regs_piu1_cmplt;
wire [3 :0] regs_piu1_hpcp_l2of_int;
wire regs_piu2_cmplt;
wire regs_piu3_cmplt;
wire regs_piu_cmplt;
wire [63:0] regs_piux_rdata;
wire regs_req_vld;
wire [3 :0] regs_sel_final;
wire [3 :0] regs_sel_raw;
wire [63:0] regs_wdata_final;
wire regs_wen;
wire regs_write;
wire [3 :0] smpen;
parameter CCR2 = 4'h0;
parameter HINT2 = 4'h1;
parameter CER2 = 4'h2;
parameter EIR2 = 4'h3;
parameter SMPR = 4'h4;
parameter TEEM = 4'h5;
parameter L2RA = 4'h8;
parameter L2RM = 4'h9;
parameter L2WA = 4'ha;
parameter L2WM = 4'hb;
parameter L2OF = 4'hc;
//==============================================================================
// arbiterf of requests from multicore
//==============================================================================
parameter REG_7 = 11;
parameter REG_4 = 8;
parameter REG_3 = 7;
parameter REG_0 = 4;
parameter WT = 3;
parameter CSRRW = 2;
parameter CSRRS = 1;
parameter CSRRC = 0;
// &Force("bus", "piu0_regs_op",15,0); @51
// &Force("bus", "piu1_regs_op",15,0); @52
// &Force("bus", "piu2_regs_op",15,0); @53
// &Force("bus", "piu3_regs_op",15,0); @54
assign regs_sel_raw[3:0] = {piu3_regs_sel,piu2_regs_sel,piu1_regs_sel,piu0_regs_sel};
// &CombBeg; @58
always @( regs_sel_raw[3:0])
begin
casez(regs_sel_raw[3:0])
4'b1??? : regs_sel[3:0] = 4'b1000;
4'b01?? : regs_sel[3:0] = 4'b0100;
4'b001? : regs_sel[3:0] = 4'b0010;
4'b0001 : regs_sel[3:0] = 4'b0001;
default : regs_sel[3:0] = 4'b0000;
endcase
// &CombEnd; @66
end
always@(posedge ctrl_clk or negedge cpurst_b)
begin
if (!cpurst_b)
regs_sel_ff[3:0] <= 4'b0;
else if (regs_req_vld & regs_cur_idle)
regs_sel_ff[3:0] <= regs_sel[3:0];
end
assign regs_sel_final[3:0] = regs_cur_idle ? regs_sel[3:0] : regs_sel_ff[3:0];
// &CombBeg; @78
always @( piu2_regs_op[11:0]
or piu3_regs_op[11:0]
or piu2_regs_wdata[63:0]
or piu0_regs_op[11:0]
or piu0_regs_wdata[63:0]
or piu1_regs_op[11:0]
or piu1_regs_wdata[63:0]
or piu3_regs_wdata[63:0]
or regs_sel_final[3:0])
begin
case(regs_sel_final[3:0])
4'b0001 : begin regs_op[11:0] = piu0_regs_op[11:0]; regs_wdata[63:0] = piu0_regs_wdata[63:0]; end
4'b0010 : begin regs_op[11:0] = piu1_regs_op[11:0]; regs_wdata[63:0] = piu1_regs_wdata[63:0]; end
4'b0100 : begin regs_op[11:0] = piu2_regs_op[11:0]; regs_wdata[63:0] = piu2_regs_wdata[63:0]; end
4'b1000 : begin regs_op[11:0] = piu3_regs_op[11:0]; regs_wdata[63:0] = piu3_regs_wdata[63:0]; end
default : begin regs_op[11:0] = 12'b0; regs_wdata[63:0] = 64'b0; end
endcase
// &CombEnd; @86
end
assign regs_req_vld = |regs_sel_final[3:0];
assign regs_write = regs_op[WT];
assign regs_l2of_wen[3:0] = regs_op[REG_7:REG_4];
assign regs_idx[3:0] = regs_op[REG_3:REG_0];
assign regs_csrrw = regs_op[CSRRW];
assign regs_csrrs = regs_op[CSRRS];
assign regs_csrrc = regs_op[CSRRC];
//================================================
// REGS FSM
//================================================
parameter IDLE = 2'b00;
parameter READ = 2'b01;
parameter WRITE = 2'b10;
always@(posedge ctrl_clk or negedge cpurst_b)
begin
if (!cpurst_b)
regs_cur_state[1:0] <= IDLE;
else
regs_cur_state[1:0] <= regs_next_state[1:0];
end
// &CombBeg; @111
always @( regs_write
or regs_req_vld
or regs_cur_state)
begin
case(regs_cur_state)
IDLE: begin
if (regs_req_vld)
regs_next_state = READ;
else
regs_next_state = IDLE;
end
READ: begin
if (regs_write)
regs_next_state = WRITE;
else
regs_next_state = IDLE;
end
WRITE: begin
regs_next_state = IDLE;
end
default: regs_next_state = IDLE;
endcase
// &CombEnd; @130
end
assign regs_cur_idle = regs_cur_state == IDLE;
assign regs_cur_read = regs_cur_state == READ;
assign regs_cur_write = regs_cur_state == WRITE;
assign regs_piu_cmplt = regs_write ? regs_cur_write : regs_cur_read;
assign regs_piu0_cmplt = regs_piu_cmplt & regs_sel_final[0];
assign regs_piu1_cmplt = regs_piu_cmplt & regs_sel_final[1];
assign regs_piu2_cmplt = regs_piu_cmplt & regs_sel_final[2];
assign regs_piu3_cmplt = regs_piu_cmplt & regs_sel_final[3];
assign regs_piux_rdata[63:0] = regs_rdata[63:0];
always@(posedge rdata_clk or negedge cpurst_b)
begin
if (!cpurst_b)
regs_rdata[63:0] <= 64'b0;
else if (regs_req_vld & regs_cur_idle)
regs_rdata[63:0] <= regs_dout[63:0];
end
// &CombBeg; @151
always @( ciu_eir2[63:0]
or private_csr_value[63:0]
or regs_idx[3:0]
or ciu_chr2[63:0]
or ciu_cer2[63:0]
or ciu_ccr2[63:0])
begin
case(regs_idx[3:0])
CCR2: regs_dout[63:0] = ciu_ccr2[63:0];
HINT2: regs_dout[63:0] = ciu_chr2[63:0];
CER2: regs_dout[63:0] = ciu_cer2[63:0];
EIR2: regs_dout[63:0] = ciu_eir2[63:0];
SMPR,TEEM,L2RA,L2RM,L2WA,L2WM,L2OF:
regs_dout[63:0] = private_csr_value[63:0];
default: regs_dout[63:0] = 64'b0;
endcase
// &CombEnd; @161
end
// &CombBeg; @163
always @( core1_csr_value[63:0]
or core0_csr_value[63:0]
or core2_csr_value[63:0]
or core3_csr_value[63:0]
or regs_sel_final[3:0])
begin
case(regs_sel_final[3:0])
4'b0001 : private_csr_value[63:0] = core0_csr_value[63:0];
4'b0010 : private_csr_value[63:0] = core1_csr_value[63:0];
4'b0100 : private_csr_value[63:0] = core2_csr_value[63:0];
4'b1000 : private_csr_value[63:0] = core3_csr_value[63:0];
default : private_csr_value[63:0] = 64'b0;
endcase
// &CombEnd; @171
end
//==============================================================================
// shared CSR of L2C
//==============================================================================
assign regs_wen = regs_cur_read & regs_write;
assign ccr2_wen = regs_wen & regs_idx[3:0] == CCR2;
assign hint2_wen = regs_wen & regs_idx[3:0] == HINT2;
assign regs_wdata_final[63:0] = {64{regs_csrrw}} & regs_wdata[63:0] |
{64{regs_csrrs}} & (regs_rdata[63:0] | regs_wdata[63:0]) |
{64{regs_csrrc}} & (regs_rdata[63:0] & ~regs_wdata[63:0]);
//======================================
// CHR2
//======================================
always @(posedge chr2_clk or negedge cpurst_b)
begin
if(~cpurst_b)
chr2_data[10:0] <= 11'b0;
else if (hint2_wen)
chr2_data[10:0] <= regs_wdata_final[10:0];
end
assign ciu_chr2[63:0] = {53'b0, chr2_data[10:0]};
assign ciu_icg_en = chr2_data[1];
assign l2c_icg_en = chr2_data[6];
assign regs_apbif_icg_en = chr2_data[7];
assign ciu_sysio_icg_en = chr2_data[8];
assign ciu_global_icg_en = chr2_data[9];
assign ciu_chr2_bar_dis = chr2_data[0];
assign ciu_chr2_sf_dis = chr2_data[4];
assign ciu_chr2_dvm_dis = chr2_data[5];
assign ciu_so_ostd_dis = chr2_data[10];
// &Force("output","ciu_icg_en"); @218
//======================================
// error injection register
//======================================
assign ciu_eir2[63:0] = 64'b0;
//======================================
// CCR2
//reg content:
//| 31 |30-29|28:26| 25 |24-22 |21-20|
//|TPRF| IPRF| res |TSETUP|TLTNCY| res |
//| 19 |18-16 |15-4| 3 | 2 | 1 | 0 |
//|DSETUP|DLTNCY|res |L2E|res|ECCEN|INCL|
//INCL: L2 inclusive en
//TPRF: L2 TLB prefetch en
//IPRF: L2 Icache prefetch strength
//TSETUP: L2 TAG RAM setup
//TLTNCY: L2 TAG RAM latency
//DSETUP: L2 DATA RAM setup
//DLTNCY: L2 DATA RAM latency
//ECCEN : L2 DATA RAM ECC en
//L2E : L2 cache en
//======================================
//TPRF
always @(posedge ccr2_clk or negedge cpurst_b)
begin
if(~cpurst_b)
ciu_ccr2_tprf <= 1'b0;
else if(ccr2_wen)
ciu_ccr2_tprf <= regs_wdata_final[31];
else
ciu_ccr2_tprf <= ciu_ccr2_tprf;
end
//IPRF
always @(posedge ccr2_clk or negedge cpurst_b)
begin
if(~cpurst_b)
ciu_ccr2_iprf[1:0] <= 2'b0;
else if(ccr2_wen)
ciu_ccr2_iprf[1:0] <= regs_wdata_final[30:29];
else
ciu_ccr2_iprf[1:0] <= ciu_ccr2_iprf[1:0];
end
//TSETUP
always @(posedge ccr2_clk or negedge cpurst_b)
begin
if(~cpurst_b)
ciu_ccr2_tsetup <= 1'b0;
else if(ccr2_wen)
ciu_ccr2_tsetup <= regs_wdata_final[25];
else
ciu_ccr2_tsetup <= ciu_ccr2_tsetup;
end
//TLTNCY
always @(posedge ccr2_clk or negedge cpurst_b)
begin
if(~cpurst_b)
ciu_ccr2_tltncy[2:0] <= 3'b1;
else if(ccr2_wen)
ciu_ccr2_tltncy[2:0] <= regs_wdata_final[24:22];
else
ciu_ccr2_tltncy[2:0] <= ciu_ccr2_tltncy[2:0];
end
//DSETUP
always @(posedge ccr2_clk or negedge cpurst_b)
begin
if(~cpurst_b)
ciu_ccr2_dsetup <= 1'b0;
else if(ccr2_wen)
ciu_ccr2_dsetup <= regs_wdata_final[19];
else
ciu_ccr2_dsetup <= ciu_ccr2_dsetup;
end
//DLTNCY
always @(posedge ccr2_clk or negedge cpurst_b)
begin
if(~cpurst_b)
ciu_ccr2_dltncy[2:0] <= 3'b1;
else if(ccr2_wen)
ciu_ccr2_dltncy[2:0] <= regs_wdata_final[18:16];
else
ciu_ccr2_dltncy[2:0] <= ciu_ccr2_dltncy[2:0];
end
//ECCEN
assign ciu_ccr2_eccen = 1'b0;
assign ciu_ccr2[63:0] = {32'b0,
ciu_ccr2_tprf,
ciu_ccr2_iprf[1:0],
3'b0,
ciu_ccr2_tsetup,
ciu_ccr2_tltncy[2:0],
2'b0,
ciu_ccr2_dsetup,
ciu_ccr2_dltncy[2:0],
12'b0,
1'b1,
1'b0,
ciu_ccr2_eccen,
1'b1
};
assign ciu_l2c_iprf[1:0] = ciu_ccr2_iprf[1:0];
assign ciu_l2c_tprf = ciu_ccr2_tprf;
assign ciu_l2c_tag_latency[2:0] = ciu_ccr2_tltncy[2:0];
assign ciu_l2c_data_latency[2:0] = ciu_ccr2_dltncy[2:0];
assign ciu_l2c_tag_setup = ciu_ccr2_tsetup;
assign ciu_l2c_data_setup = ciu_ccr2_dsetup;
//======================================
// CER2
// | 31 |
// | ECC_ERR |
//======================================
assign ciu_cer2[63:0] = 64'b0;
assign l2c_plic_ecc_int_vld = 1'b0;
// &ConnRule(s/^x_/core0_/); @461
// &ConnRule(s/_x$/[0]/); @462
// &Instance("ct_ciu_regs_kid","x_ct_ciu_regs_kid_core0"); @463
ct_ciu_regs_kid x_ct_ciu_regs_kid_core0 (
.ciu_icg_en (ciu_icg_en ),
.forever_cpuclk (forever_cpuclk ),
.l2cif0_regs_read_acc_inc_x (l2cif0_regs_read_acc_inc[0] ),
.l2cif0_regs_read_miss_inc_x (l2cif0_regs_read_miss_inc[0] ),
.l2cif0_regs_write_acc_inc_x (l2cif0_regs_write_acc_inc[0] ),
.l2cif0_regs_write_miss_inc_x (l2cif0_regs_write_miss_inc[0]),
.l2cif1_regs_read_acc_inc_x (l2cif1_regs_read_acc_inc[0] ),
.l2cif1_regs_read_miss_inc_x (l2cif1_regs_read_miss_inc[0] ),
.l2cif1_regs_write_acc_inc_x (l2cif1_regs_write_acc_inc[0] ),
.l2cif1_regs_write_miss_inc_x (l2cif1_regs_write_miss_inc[0]),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.regs_idx (regs_idx ),
.regs_l2of_wen (regs_l2of_wen ),
.regs_sel_final_x (regs_sel_final[0] ),
.regs_wdata_final (regs_wdata_final ),
.regs_wen (regs_wen ),
.smpen_x (smpen[0] ),
.x_csr_value (core0_csr_value ),
.x_fifo_rst_b (core0_fifo_rst_b ),
.x_hpcp_cnt_en (core0_hpcp_cnt_en ),
.x_l2of_int (core0_l2of_int )
);
// &ConnRule(s/^x_/core1_/); @468
// &ConnRule(s/_x$/[1]/); @469
// &Instance("ct_ciu_regs_kid","x_ct_ciu_regs_kid_core1"); @471
ct_ciu_regs_kid x_ct_ciu_regs_kid_core1 (
.ciu_icg_en (ciu_icg_en ),
.forever_cpuclk (forever_cpuclk ),
.l2cif0_regs_read_acc_inc_x (l2cif0_regs_read_acc_inc[1] ),
.l2cif0_regs_read_miss_inc_x (l2cif0_regs_read_miss_inc[1] ),
.l2cif0_regs_write_acc_inc_x (l2cif0_regs_write_acc_inc[1] ),
.l2cif0_regs_write_miss_inc_x (l2cif0_regs_write_miss_inc[1]),
.l2cif1_regs_read_acc_inc_x (l2cif1_regs_read_acc_inc[1] ),
.l2cif1_regs_read_miss_inc_x (l2cif1_regs_read_miss_inc[1] ),
.l2cif1_regs_write_acc_inc_x (l2cif1_regs_write_acc_inc[1] ),
.l2cif1_regs_write_miss_inc_x (l2cif1_regs_write_miss_inc[1]),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.regs_idx (regs_idx ),
.regs_l2of_wen (regs_l2of_wen ),
.regs_sel_final_x (regs_sel_final[1] ),
.regs_wdata_final (regs_wdata_final ),
.regs_wen (regs_wen ),
.smpen_x (smpen[1] ),
.x_csr_value (core1_csr_value ),
.x_fifo_rst_b (core1_fifo_rst_b ),
.x_hpcp_cnt_en (core1_hpcp_cnt_en ),
.x_l2of_int (core1_l2of_int )
);
// &ConnRule(s/^x_/core2_/); @477
// &ConnRule(s/_x$/[2]/); @478
// &Instance("ct_ciu_regs_kid","x_ct_ciu_regs_kid_core2"); @479
assign core2_csr_value[63:0] = 64'b0;
assign smpen[2] = 1'b0;
// &ConnRule(s/^x_/core3_/); @485
// &ConnRule(s/_x$/[3]/); @486
// &Instance("ct_ciu_regs_kid","x_ct_ciu_regs_kid_core3"); @487
assign core3_csr_value[63:0] = 64'b0;
assign smpen[3] = 1'b0;
// &Force("bus", "l2cif0_regs_read_acc_inc",3,0); @538
// &Force("bus", "l2cif0_regs_read_miss_inc",3,0); @539
// &Force("bus", "l2cif0_regs_write_acc_inc",3,0); @540
// &Force("bus", "l2cif0_regs_write_miss_inc",3,0); @541
// &Force("bus", "l2cif1_regs_read_acc_inc",3,0); @542
// &Force("bus", "l2cif1_regs_read_miss_inc",3,0); @543
// &Force("bus", "l2cif1_regs_write_acc_inc",3,0); @544
// &Force("bus", "l2cif1_regs_write_miss_inc",3,0); @545
assign regs_piu0_hpcp_l2of_int[3:0] = core0_l2of_int[3:0];
assign core0_hpcp_cnt_en[3:0] = piu0_regs_hpcp_cnt_en[3:0];
assign regs_piu1_hpcp_l2of_int[3:0] = core1_l2of_int[3:0];
assign core1_hpcp_cnt_en[3:0] = piu1_regs_hpcp_cnt_en[3:0];
assign ciu_xx_smpen[3:0] = smpen[3:0];
always@(posedge forever_cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
rvba_rst <= 1'b1;
else
rvba_rst <= 1'b0;
end
assign ciu_l2c_rst_req = rvba_rst;
assign ciu_apbif_had_pctrace_inv = rvba_rst;
//==========================================================
// Gated Clk EN
//==========================================================
assign chr2_clk_en = hint2_wen;
// &Instance("gated_clk_cell", "x_chr2_gated_clk"); @583
gated_clk_cell x_chr2_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (chr2_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (chr2_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @584
// .external_en (1'b0), @585
// .global_en (1'b1), @586
// .module_en (ciu_icg_en), @587
// .local_en (chr2_clk_en), @588
// .clk_out (chr2_clk)); @589
assign ccr2_clk_en = ccr2_wen;
// &Instance("gated_clk_cell", "x_ccr2_gated_clk"); @592
gated_clk_cell x_ccr2_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ccr2_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (ccr2_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @593
// .external_en (1'b0), @594
// .global_en (1'b1), @595
// .module_en (ciu_icg_en), @596
// .local_en (ccr2_clk_en), @597
// .clk_out (ccr2_clk)); @598
// &Instance("gated_clk_cell", "x_cer2_gated_clk"); @603
// &Connect(.clk_in (forever_cpuclk), @604
// .external_en (1'b0), @605
// .global_en (1'b1), @606
// .module_en (ciu_icg_en), @607
// .local_en (cer2_clk_en), @608
// .clk_out (cer2_clk)); @609
// &Instance("gated_clk_cell", "x_eir2_gated_clk"); @614
// &Connect(.clk_in (forever_cpuclk), @615
// .external_en (1'b0), @616
// .global_en (1'b1), @617
// .module_en (ciu_icg_en), @618
// .local_en (eir2_clk_en), @619
// .clk_out (eir2_clk)); @620
assign ctrl_clk_en = regs_req_vld | !regs_cur_idle;
// &Instance("gated_clk_cell", "x_ctrl_gated_clk"); @625
gated_clk_cell x_ctrl_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ctrl_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (ctrl_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @626
// .external_en (1'b0), @627
// .global_en (1'b1), @628
// .module_en (ciu_icg_en), @629
// .local_en (ctrl_clk_en), @630
// .clk_out (ctrl_clk)); @631
assign rdata_clk_en = regs_req_vld & regs_cur_idle;
// &Instance("gated_clk_cell", "x_rdata_gated_clk"); @634
gated_clk_cell x_rdata_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (rdata_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (rdata_clk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @635
// .external_en (1'b0), @636
// .global_en (1'b1), @637
// .module_en (ciu_icg_en), @638
// .local_en (rdata_clk_en), @639
// .clk_out (rdata_clk)); @640
// &ModuleEnd; @642
endmodule |
module ct_ciu_ctcq_respq_entry(
ciu_icg_en,
cpurst_b,
forever_cpuclk,
pad_yy_icg_scan_en,
respq_create_cmplt_init,
respq_create_dvm,
respq_create_en_x,
respq_dvm_x,
respq_ebiu_resp_create_en_x,
respq_l2c_resp_create_en_x,
respq_piu0_resp_create_en_x,
respq_piu1_resp_create_en_x,
respq_piu2_resp_create_en_x,
respq_piu3_resp_create_en_x,
respq_vld_x
);
// &Ports; @23
input ciu_icg_en;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [5:0] respq_create_cmplt_init;
input respq_create_dvm;
input respq_create_en_x;
input respq_ebiu_resp_create_en_x;
input respq_l2c_resp_create_en_x;
input respq_piu0_resp_create_en_x;
input respq_piu1_resp_create_en_x;
input respq_piu2_resp_create_en_x;
input respq_piu3_resp_create_en_x;
output respq_dvm_x;
output respq_vld_x;
// &Regs; @24
reg respq_dvm;
reg respq_ebiu_cmplt;
reg respq_l2c_cmplt;
reg respq_piu0_cmplt;
reg respq_piu1_cmplt;
reg respq_piu2_cmplt;
reg respq_piu3_cmplt;
reg respq_vld;
// &Wires; @25
wire ciu_icg_en;
wire cpurst_b;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire [5:0] respq_create_cmplt_init;
wire respq_create_dvm;
wire respq_create_en;
wire respq_create_en_x;
wire respq_dvm_x;
wire respq_ebiu_resp_create_en;
wire respq_ebiu_resp_create_en_x;
wire respq_entry_clk_en;
wire respq_l2c_resp_create_en;
wire respq_l2c_resp_create_en_x;
wire respq_piu0_resp_create_en;
wire respq_piu0_resp_create_en_x;
wire respq_piu1_resp_create_en;
wire respq_piu1_resp_create_en_x;
wire respq_piu2_resp_create_en;
wire respq_piu2_resp_create_en_x;
wire respq_piu3_resp_create_en;
wire respq_piu3_resp_create_en_x;
wire respq_pop_en;
wire respq_vld_x;
wire respqentyclk;
//======================================
// CTC resp queue(respq)
//entry content:
//| vld |
//| cmplt | [4]: L2 cmplt
// [3]: cpu3 cmplt
// [2]: cpu2 cmplt
// [1]: cpu1 cmplt
// [0]: cpu0 cmplt
//======================================
assign respq_pop_en = respq_l2c_cmplt
& respq_ebiu_cmplt
& respq_piu3_cmplt
& respq_piu2_cmplt
& respq_piu1_cmplt
& respq_piu0_cmplt
& respq_vld;
always @(posedge respqentyclk or negedge cpurst_b)
begin
if(~cpurst_b)
respq_vld <= 1'b0;
else
begin
if(respq_create_en)
respq_vld <= 1'b1;
else if(respq_pop_en)
respq_vld <= 1'b0;
else
respq_vld <= respq_vld;
end
end
always @(posedge respqentyclk or negedge cpurst_b)
begin
if(~cpurst_b)
respq_l2c_cmplt <= 1'b0;
else if(respq_create_en)
respq_l2c_cmplt <= respq_create_cmplt_init[5];
else if(respq_l2c_resp_create_en)
respq_l2c_cmplt <= 1'b1;
else
respq_l2c_cmplt <= respq_l2c_cmplt;
end
always @(posedge respqentyclk or negedge cpurst_b)
begin
if(~cpurst_b)
respq_ebiu_cmplt <= 1'b0;
else if(respq_create_en)
respq_ebiu_cmplt <= respq_create_cmplt_init[4];
else if(respq_ebiu_resp_create_en)
respq_ebiu_cmplt <= 1'b1;
else
respq_ebiu_cmplt <= respq_ebiu_cmplt;
end
always @(posedge respqentyclk or negedge cpurst_b)
begin
if(~cpurst_b)
respq_piu3_cmplt <= 1'b0;
else if(respq_create_en)
respq_piu3_cmplt <= respq_create_cmplt_init[3];
else if(respq_piu3_resp_create_en)
respq_piu3_cmplt <= 1'b1;
else
respq_piu3_cmplt <= respq_piu3_cmplt;
end
always @(posedge respqentyclk or negedge cpurst_b)
begin
if(~cpurst_b)
respq_piu2_cmplt <= 1'b0;
else if(respq_create_en)
respq_piu2_cmplt <= respq_create_cmplt_init[2];
else if(respq_piu2_resp_create_en)
respq_piu2_cmplt <= 1'b1;
else
respq_piu2_cmplt <= respq_piu2_cmplt;
end
always @(posedge respqentyclk or negedge cpurst_b)
begin
if(~cpurst_b)
respq_piu1_cmplt <= 1'b0;
else if(respq_create_en)
respq_piu1_cmplt <= respq_create_cmplt_init[1];
else if(respq_piu1_resp_create_en)
respq_piu1_cmplt <= 1'b1;
else
respq_piu1_cmplt <= respq_piu1_cmplt;
end
always @(posedge respqentyclk or negedge cpurst_b)
begin
if(~cpurst_b)
respq_piu0_cmplt <= 1'b0;
else if(respq_create_en)
respq_piu0_cmplt <= respq_create_cmplt_init[0];
else if(respq_piu0_resp_create_en)
respq_piu0_cmplt <= 1'b1;
else
respq_piu0_cmplt <= respq_piu0_cmplt;
end
always @(posedge respqentyclk)
begin
if (respq_create_en)
respq_dvm <= respq_create_dvm;
else
respq_dvm <= respq_dvm;
end
//==========================================================
// Gated Clk EN
//==========================================================
assign respq_entry_clk_en = respq_create_en
|| respq_pop_en
|| respq_l2c_resp_create_en
|| respq_ebiu_resp_create_en
|| respq_piu3_resp_create_en
|| respq_piu2_resp_create_en
|| respq_piu1_resp_create_en
|| respq_piu0_resp_create_en;
// &Instance("gated_clk_cell","x_respq_entry_gated_cell"); @146
gated_clk_cell x_respq_entry_gated_cell (
.clk_in (forever_cpuclk ),
.clk_out (respqentyclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (respq_entry_clk_en),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk ), @147
// .clk_out (respqentyclk ), @148
// .external_en (1'b0 ), @149
// .global_en (1'b1 ), @150
// .local_en (respq_entry_clk_en ), @151
// .module_en (ciu_icg_en ) @152
// ); @153
//==========================================================
// input/output
//==========================================================
//input
assign respq_create_en = respq_create_en_x;
assign respq_l2c_resp_create_en = respq_l2c_resp_create_en_x;
assign respq_ebiu_resp_create_en = respq_ebiu_resp_create_en_x;
assign respq_piu3_resp_create_en = respq_piu3_resp_create_en_x;
assign respq_piu2_resp_create_en = respq_piu2_resp_create_en_x;
assign respq_piu1_resp_create_en = respq_piu1_resp_create_en_x;
assign respq_piu0_resp_create_en = respq_piu0_resp_create_en_x;
//output
assign respq_vld_x = respq_vld;
assign respq_dvm_x = respq_dvm;
// &ModuleEnd; @171
endmodule |
module ct_ciu_snb_dp_sel_16(
entry0_age_vect,
entry10_age_vect,
entry11_age_vect,
entry12_age_vect,
entry13_age_vect,
entry14_age_vect,
entry15_age_vect,
entry1_age_vect,
entry2_age_vect,
entry3_age_vect,
entry4_age_vect,
entry5_age_vect,
entry6_age_vect,
entry7_age_vect,
entry8_age_vect,
entry9_age_vect,
req_vld,
sel
);
// &Ports; @19
input [23:0] entry0_age_vect;
input [23:0] entry10_age_vect;
input [23:0] entry11_age_vect;
input [23:0] entry12_age_vect;
input [23:0] entry13_age_vect;
input [23:0] entry14_age_vect;
input [23:0] entry15_age_vect;
input [23:0] entry1_age_vect;
input [23:0] entry2_age_vect;
input [23:0] entry3_age_vect;
input [23:0] entry4_age_vect;
input [23:0] entry5_age_vect;
input [23:0] entry6_age_vect;
input [23:0] entry7_age_vect;
input [23:0] entry8_age_vect;
input [23:0] entry9_age_vect;
input [15:0] req_vld;
output [15:0] sel;
// &Regs; @20
// &Wires; @21
wire [23:0] entry0_age_vect;
wire [23:0] entry10_age_vect;
wire [23:0] entry11_age_vect;
wire [23:0] entry12_age_vect;
wire [23:0] entry13_age_vect;
wire [23:0] entry14_age_vect;
wire [23:0] entry15_age_vect;
wire [23:0] entry1_age_vect;
wire [23:0] entry2_age_vect;
wire [23:0] entry3_age_vect;
wire [23:0] entry4_age_vect;
wire [23:0] entry5_age_vect;
wire [23:0] entry6_age_vect;
wire [23:0] entry7_age_vect;
wire [23:0] entry8_age_vect;
wire [23:0] entry9_age_vect;
wire [15:0] req_vld;
wire [15:0] sel;
// &Force("bus", "entry0_age_vect",23,0); @23
// &Force("bus", "entry1_age_vect",23,0); @24
// &Force("bus", "entry2_age_vect",23,0); @25
// &Force("bus", "entry3_age_vect",23,0); @26
// &Force("bus", "entry4_age_vect",23,0); @27
// &Force("bus", "entry5_age_vect",23,0); @28
// &Force("bus", "entry6_age_vect",23,0); @29
// &Force("bus", "entry7_age_vect",23,0); @30
// &Force("bus", "entry8_age_vect",23,0); @31
// &Force("bus", "entry9_age_vect",23,0); @32
// &Force("bus", "entry10_age_vect",23,0); @33
// &Force("bus", "entry11_age_vect",23,0); @34
// &Force("bus", "entry12_age_vect",23,0); @35
// &Force("bus", "entry13_age_vect",23,0); @36
// &Force("bus", "entry14_age_vect",23,0); @37
// &Force("bus", "entry15_age_vect",23,0); @38
parameter DEPTH = 16;
assign sel[0] = req_vld[0] && !(|(req_vld[DEPTH-1:0] & entry0_age_vect[DEPTH-1:0]));
assign sel[1] = req_vld[1] && !(|(req_vld[DEPTH-1:0] & entry1_age_vect[DEPTH-1:0]));
assign sel[2] = req_vld[2] && !(|(req_vld[DEPTH-1:0] & entry2_age_vect[DEPTH-1:0]));
assign sel[3] = req_vld[3] && !(|(req_vld[DEPTH-1:0] & entry3_age_vect[DEPTH-1:0]));
assign sel[4] = req_vld[4] && !(|(req_vld[DEPTH-1:0] & entry4_age_vect[DEPTH-1:0]));
assign sel[5] = req_vld[5] && !(|(req_vld[DEPTH-1:0] & entry5_age_vect[DEPTH-1:0]));
assign sel[6] = req_vld[6] && !(|(req_vld[DEPTH-1:0] & entry6_age_vect[DEPTH-1:0]));
assign sel[7] = req_vld[7] && !(|(req_vld[DEPTH-1:0] & entry7_age_vect[DEPTH-1:0]));
assign sel[8] = req_vld[8] && !(|(req_vld[DEPTH-1:0] & entry8_age_vect[DEPTH-1:0]));
assign sel[9] = req_vld[9] && !(|(req_vld[DEPTH-1:0] & entry9_age_vect[DEPTH-1:0]));
assign sel[10] = req_vld[10] && !(|(req_vld[DEPTH-1:0] & entry10_age_vect[DEPTH-1:0]));
assign sel[11] = req_vld[11] && !(|(req_vld[DEPTH-1:0] & entry11_age_vect[DEPTH-1:0]));
assign sel[12] = req_vld[12] && !(|(req_vld[DEPTH-1:0] & entry12_age_vect[DEPTH-1:0]));
assign sel[13] = req_vld[13] && !(|(req_vld[DEPTH-1:0] & entry13_age_vect[DEPTH-1:0]));
assign sel[14] = req_vld[14] && !(|(req_vld[DEPTH-1:0] & entry14_age_vect[DEPTH-1:0]));
assign sel[15] = req_vld[15] && !(|(req_vld[DEPTH-1:0] & entry15_age_vect[DEPTH-1:0]));
// &ModuleEnd; @59
endmodule |
module ct_ciu_snb_dp_sel_8(
entry16_age_vect,
entry17_age_vect,
entry18_age_vect,
entry19_age_vect,
entry20_age_vect,
entry21_age_vect,
entry22_age_vect,
entry23_age_vect,
req_vld,
sel
);
// &Ports; @19
input [23:0] entry16_age_vect;
input [23:0] entry17_age_vect;
input [23:0] entry18_age_vect;
input [23:0] entry19_age_vect;
input [23:0] entry20_age_vect;
input [23:0] entry21_age_vect;
input [23:0] entry22_age_vect;
input [23:0] entry23_age_vect;
input [7 :0] req_vld;
output [7 :0] sel;
// &Regs; @20
// &Wires; @21
wire [23:0] entry16_age_vect;
wire [23:0] entry17_age_vect;
wire [23:0] entry18_age_vect;
wire [23:0] entry19_age_vect;
wire [23:0] entry20_age_vect;
wire [23:0] entry21_age_vect;
wire [23:0] entry22_age_vect;
wire [23:0] entry23_age_vect;
wire [7 :0] req_vld;
wire [7 :0] sel;
// &Force("bus", "entry16_age_vect", 23,0); @23
// &Force("bus", "entry17_age_vect", 23,0); @24
// &Force("bus", "entry18_age_vect", 23,0); @25
// &Force("bus", "entry19_age_vect", 23,0); @26
// &Force("bus", "entry20_age_vect", 23,0); @27
// &Force("bus", "entry21_age_vect", 23,0); @28
// &Force("bus", "entry22_age_vect", 23,0); @29
// &Force("bus", "entry23_age_vect", 23,0); @30
parameter DEPTH = 8;
assign sel[0] = req_vld[0] && !(|(req_vld[DEPTH-1:0] & entry16_age_vect[23:16]));
assign sel[1] = req_vld[1] && !(|(req_vld[DEPTH-1:0] & entry17_age_vect[23:16]));
assign sel[2] = req_vld[2] && !(|(req_vld[DEPTH-1:0] & entry18_age_vect[23:16]));
assign sel[3] = req_vld[3] && !(|(req_vld[DEPTH-1:0] & entry19_age_vect[23:16]));
assign sel[4] = req_vld[4] && !(|(req_vld[DEPTH-1:0] & entry20_age_vect[23:16]));
assign sel[5] = req_vld[5] && !(|(req_vld[DEPTH-1:0] & entry21_age_vect[23:16]));
assign sel[6] = req_vld[6] && !(|(req_vld[DEPTH-1:0] & entry22_age_vect[23:16]));
assign sel[7] = req_vld[7] && !(|(req_vld[DEPTH-1:0] & entry23_age_vect[23:16]));
// &ModuleEnd; @43
endmodule |
module ct_fifo(
clk,
rst_b,
fifo_create_en,
fifo_create_en_dp,
fifo_pop_en,
fifo_create_data,
fifo_pop_data,
fifo_pop_data_vld,
fifo_full,
fifo_empty,
pad_yy_icg_scan_en,
fifo_icg_en
);
parameter DEPTH = 2;
parameter WIDTH = 6;
parameter PTR_W = 1;
input clk;
input rst_b;
input fifo_create_en;
input fifo_create_en_dp;
input fifo_pop_en;
input [WIDTH-1:0] fifo_create_data;
input pad_yy_icg_scan_en;
input fifo_icg_en;
output [WIDTH-1:0] fifo_pop_data;
output fifo_pop_data_vld;
output fifo_full;
output fifo_empty;
wire ctrl_clk;
wire ctrl_clk_en;
wire pad_yy_icg_scan_en;
wire fifo_icg_en;
wire [DEPTH-1:0] fifo_entry_create;
wire [DEPTH-1:0] fifo_entry_create_dp;
wire [DEPTH-1:0] fifo_entry_pop;
wire fifo_empty;
wire fifo_full;
wire [DEPTH-1:0] entry_clk;
wire [DEPTH-1:0] fifo_pop_sel;
wire fifo_not_empty;
wire fifo_pop_data_vld;
wire [WIDTH-1:0] fifo_pop_data;
reg [DEPTH-1:0] fifo_entry_vld;
reg [WIDTH-1:0] fifo_entry_cont [DEPTH-1:0];
reg [DEPTH-1:0] fifo_create_ptr;
reg [PTR_W :0] fifo_pop_ptr;
assign ctrl_clk_en = fifo_create_en_dp | fifo_not_empty;
gated_clk_cell x_fifo_ctrl_gated_clk(
.clk_in (clk ),
.clk_out (ctrl_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (ctrl_clk_en ),
.module_en (fifo_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
always@(posedge ctrl_clk or negedge rst_b)
begin
if (!rst_b)
fifo_create_ptr[DEPTH-1:0] <= {{(DEPTH-1){1'b0}},1'b1};
else if (fifo_create_en)
fifo_create_ptr[DEPTH-1:0] <= {fifo_create_ptr[DEPTH-2:0],fifo_create_ptr[DEPTH-1]};
end
always@(posedge ctrl_clk or negedge rst_b)
begin
if (!rst_b)
fifo_pop_ptr[PTR_W:0] <= {(PTR_W+1){1'b0}};
else if (fifo_pop_en & (fifo_pop_ptr[PTR_W-1:0] == (DEPTH-1)))
fifo_pop_ptr[PTR_W:0] <= {(PTR_W+1){1'b0}};
else if (fifo_pop_en)
fifo_pop_ptr[PTR_W:0] <= fifo_pop_ptr[PTR_W:0] + {{PTR_W{1'b0}},1'b1};
end
assign fifo_pop_sel[DEPTH-1:0] = {{(DEPTH-1){1'b0}},1'b1} << fifo_pop_ptr[PTR_W-1:0];
assign fifo_entry_create[DEPTH-1:0] =
{DEPTH{fifo_create_en}} & fifo_create_ptr[DEPTH-1:0];
assign fifo_entry_create_dp[DEPTH-1:0] =
{DEPTH{fifo_create_en_dp}} & fifo_create_ptr[DEPTH-1:0];
assign fifo_entry_pop[DEPTH-1:0] =
{DEPTH{fifo_pop_en}} & fifo_pop_sel[DEPTH-1:0];
genvar i;
generate
for(i=0; i<DEPTH; i=i+1) begin: DFIFO_VLD_GEN
always@(posedge ctrl_clk or negedge rst_b)
begin
if (!rst_b)
fifo_entry_vld[i] <= 1'b0;
else if (fifo_entry_create[i])
fifo_entry_vld[i] <= 1'b1;
else if (fifo_entry_pop[i])
fifo_entry_vld[i] <= 1'b0;
end
end
endgenerate
generate
for(i=0; i<DEPTH; i=i+1) begin: DFIFO_GATED_CLK_GEN
gated_clk_cell x_entry_gated_clk(
.clk_in (clk ),
.clk_out (entry_clk[i] ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (fifo_entry_create_dp[i]),
.module_en (fifo_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
end
endgenerate
generate
for(i=0; i<DEPTH; i=i+1) begin: DFIFO_CONT_GEN
always@(posedge entry_clk[i] or negedge rst_b)
begin
if (!rst_b)
fifo_entry_cont[i][WIDTH-1:0] <= {WIDTH{1'b0}};
else if (fifo_entry_create_dp[i])
fifo_entry_cont[i][WIDTH-1:0] <= fifo_create_data[WIDTH-1:0];
else
fifo_entry_cont[i][WIDTH-1:0] <= fifo_entry_cont[i][WIDTH-1:0];
end
end
endgenerate
assign fifo_full = &fifo_entry_vld[DEPTH-1:0];
assign fifo_not_empty = |fifo_entry_vld[DEPTH-1:0];
assign fifo_empty = ~fifo_not_empty;
assign fifo_pop_data_vld = |fifo_entry_vld[DEPTH-1:0];
assign fifo_pop_data[WIDTH-1:0] = fifo_entry_cont[fifo_pop_ptr[PTR_W-1:0]][WIDTH-1:0];
endmodule |
module ct_ebiu_top(
ciu_icg_en,
ciu_so_ostd_dis,
ciu_top_clk,
clk_en,
cpurst_b,
ctcq_ebiu_araddr,
ctcq_ebiu_arbar,
ctcq_ebiu_arburst,
ctcq_ebiu_arcache,
ctcq_ebiu_ardomain,
ctcq_ebiu_arid,
ctcq_ebiu_arlen,
ctcq_ebiu_arlock,
ctcq_ebiu_arprot,
ctcq_ebiu_arsize,
ctcq_ebiu_arsnoop,
ctcq_ebiu_arvalid,
ctcq_ebiu_r_grant,
ebiu_ctcq_ar_grant,
ebiu_ctcq_rid,
ebiu_ctcq_rvalid,
ebiu_ebiuif_acaddr,
ebiu_ebiuif_acid,
ebiu_ebiuif_acprot,
ebiu_ebiuif_acsnoop,
ebiu_ebiuif_acvalid,
ebiu_ebiuif_ar_grant,
ebiu_ebiuif_ar_grant_gate,
ebiu_ebiuif_cd_grant,
ebiu_ebiuif_cr_grant,
ebiu_ebiuif_entry_sel,
ebiu_ebiuif_rdata,
ebiu_ebiuif_rlast,
ebiu_ebiuif_rresp,
ebiu_ebiuif_snb0_rvalid,
ebiu_ebiuif_snb1_rvalid,
ebiu_ncq_ar_grant,
ebiu_ncq_ar_grant_gate,
ebiu_ncq_aw_grant,
ebiu_ncq_aw_grant_gated,
ebiu_ncq_bid,
ebiu_ncq_bresp,
ebiu_ncq_bvalid,
ebiu_ncq_rdata,
ebiu_ncq_rid,
ebiu_ncq_rlast,
ebiu_ncq_rresp,
ebiu_ncq_rvalid,
ebiu_ncq_w_grant,
ebiu_pad_araddr,
ebiu_pad_arburst,
ebiu_pad_arcache,
ebiu_pad_arid,
ebiu_pad_arlen,
ebiu_pad_arlock,
ebiu_pad_arprot,
ebiu_pad_arsize,
ebiu_pad_arvalid,
ebiu_pad_awaddr,
ebiu_pad_awburst,
ebiu_pad_awcache,
ebiu_pad_awid,
ebiu_pad_awlen,
ebiu_pad_awlock,
ebiu_pad_awprot,
ebiu_pad_awsize,
ebiu_pad_awvalid,
ebiu_pad_back,
ebiu_pad_bready,
ebiu_pad_cactive,
ebiu_pad_csysack,
ebiu_pad_rack,
ebiu_pad_rready,
ebiu_pad_wdata,
ebiu_pad_wlast,
ebiu_pad_wstrb,
ebiu_pad_wvalid,
ebiu_piu0_no_op,
ebiu_piu1_no_op,
ebiu_piu2_no_op,
ebiu_piu3_no_op,
ebiu_vb_aw_grant,
ebiu_vb_aw_grant_gated,
ebiu_vb_bid,
ebiu_vb_bresp,
ebiu_vb_bvalid,
ebiu_vb_w_grant,
ebiu_xx_no_op,
ebiuif_ebiu_ac_grant,
ebiuif_ebiu_araddr,
ebiuif_ebiu_arbar,
ebiuif_ebiu_arburst,
ebiuif_ebiu_arcache,
ebiuif_ebiu_ardomain,
ebiuif_ebiu_arid,
ebiuif_ebiu_arlen,
ebiuif_ebiu_arlock,
ebiuif_ebiu_arprot,
ebiuif_ebiu_arsize,
ebiuif_ebiu_arsnoop,
ebiuif_ebiu_arvalid,
ebiuif_ebiu_cddata,
ebiuif_ebiu_cdlast,
ebiuif_ebiu_cdvalid,
ebiuif_ebiu_crresp,
ebiuif_ebiu_crvalid,
ebiuif_ebiu_r_grant,
ncq_ebiu_arvalid,
ncq_ebiu_awvalid,
ncq_ebiu_b_grant,
ncq_ebiu_r_grant,
ncq_ebiu_wvalid,
ncq_xx_araddr,
ncq_xx_arbar,
ncq_xx_arburst,
ncq_xx_arcache,
ncq_xx_ardomain,
ncq_xx_arid,
ncq_xx_arlen,
ncq_xx_arlock,
ncq_xx_arprot,
ncq_xx_arsize,
ncq_xx_arsnoop,
ncq_xx_aw_needissue,
ncq_xx_awaddr,
ncq_xx_awbar,
ncq_xx_awburst,
ncq_xx_awcache,
ncq_xx_awdomain,
ncq_xx_awid,
ncq_xx_awlen,
ncq_xx_awlock,
ncq_xx_awprot,
ncq_xx_awsize,
ncq_xx_awsnoop,
ncq_xx_wdata,
ncq_xx_wid,
ncq_xx_wlast,
ncq_xx_wstrb,
pad_ebiu_arready,
pad_ebiu_awready,
pad_ebiu_bid,
pad_ebiu_bresp,
pad_ebiu_bvalid,
pad_ebiu_csysreq,
pad_ebiu_rdata,
pad_ebiu_rid,
pad_ebiu_rlast,
pad_ebiu_rresp,
pad_ebiu_rvalid,
pad_ebiu_wready,
pad_yy_icg_scan_en,
snb0_snpext_depd_ebiu,
snb0_yy_snpext_index,
snb1_snpext_depd_ebiu,
snb1_yy_snpext_index,
vb_ebiu_awaddr,
vb_ebiu_awbar,
vb_ebiu_awburst,
vb_ebiu_awcache,
vb_ebiu_awdomain,
vb_ebiu_awid,
vb_ebiu_awlen,
vb_ebiu_awlock,
vb_ebiu_awprot,
vb_ebiu_awsize,
vb_ebiu_awsnoop,
vb_ebiu_awvalid,
vb_ebiu_b_grant,
vb_ebiu_mid,
vb_ebiu_wdata,
vb_ebiu_wid,
vb_ebiu_wlast,
vb_ebiu_wstrb,
vb_ebiu_wvalid
);
// &Ports; @19
input ciu_icg_en;
input ciu_so_ostd_dis;
input ciu_top_clk;
input clk_en;
input cpurst_b;
input [39 :0] ctcq_ebiu_araddr;
input [1 :0] ctcq_ebiu_arbar;
input [1 :0] ctcq_ebiu_arburst;
input [3 :0] ctcq_ebiu_arcache;
input [1 :0] ctcq_ebiu_ardomain;
input [5 :0] ctcq_ebiu_arid;
input [7 :0] ctcq_ebiu_arlen;
input ctcq_ebiu_arlock;
input [2 :0] ctcq_ebiu_arprot;
input [2 :0] ctcq_ebiu_arsize;
input [3 :0] ctcq_ebiu_arsnoop;
input ctcq_ebiu_arvalid;
input ctcq_ebiu_r_grant;
input ebiuif_ebiu_ac_grant;
input [39 :0] ebiuif_ebiu_araddr;
input [1 :0] ebiuif_ebiu_arbar;
input [1 :0] ebiuif_ebiu_arburst;
input [3 :0] ebiuif_ebiu_arcache;
input [1 :0] ebiuif_ebiu_ardomain;
input [5 :0] ebiuif_ebiu_arid;
input [7 :0] ebiuif_ebiu_arlen;
input ebiuif_ebiu_arlock;
input [2 :0] ebiuif_ebiu_arprot;
input [2 :0] ebiuif_ebiu_arsize;
input [3 :0] ebiuif_ebiu_arsnoop;
input ebiuif_ebiu_arvalid;
input [127:0] ebiuif_ebiu_cddata;
input ebiuif_ebiu_cdlast;
input ebiuif_ebiu_cdvalid;
input [4 :0] ebiuif_ebiu_crresp;
input ebiuif_ebiu_crvalid;
input ebiuif_ebiu_r_grant;
input ncq_ebiu_arvalid;
input ncq_ebiu_awvalid;
input ncq_ebiu_b_grant;
input ncq_ebiu_r_grant;
input ncq_ebiu_wvalid;
input [39 :0] ncq_xx_araddr;
input [1 :0] ncq_xx_arbar;
input [1 :0] ncq_xx_arburst;
input [3 :0] ncq_xx_arcache;
input [1 :0] ncq_xx_ardomain;
input [7 :0] ncq_xx_arid;
input [7 :0] ncq_xx_arlen;
input ncq_xx_arlock;
input [2 :0] ncq_xx_arprot;
input [2 :0] ncq_xx_arsize;
input [3 :0] ncq_xx_arsnoop;
input ncq_xx_aw_needissue;
input [39 :0] ncq_xx_awaddr;
input [1 :0] ncq_xx_awbar;
input [1 :0] ncq_xx_awburst;
input [3 :0] ncq_xx_awcache;
input [1 :0] ncq_xx_awdomain;
input [7 :0] ncq_xx_awid;
input [7 :0] ncq_xx_awlen;
input ncq_xx_awlock;
input [2 :0] ncq_xx_awprot;
input [2 :0] ncq_xx_awsize;
input [2 :0] ncq_xx_awsnoop;
input [127:0] ncq_xx_wdata;
input [7 :0] ncq_xx_wid;
input ncq_xx_wlast;
input [15 :0] ncq_xx_wstrb;
input pad_ebiu_arready;
input pad_ebiu_awready;
input [7 :0] pad_ebiu_bid;
input [1 :0] pad_ebiu_bresp;
input pad_ebiu_bvalid;
input pad_ebiu_csysreq;
input [127:0] pad_ebiu_rdata;
input [7 :0] pad_ebiu_rid;
input pad_ebiu_rlast;
input [1 :0] pad_ebiu_rresp;
input pad_ebiu_rvalid;
input pad_ebiu_wready;
input pad_yy_icg_scan_en;
input [7 :0] snb0_yy_snpext_index;
input [7 :0] snb1_yy_snpext_index;
input [39 :0] vb_ebiu_awaddr;
input [1 :0] vb_ebiu_awbar;
input [1 :0] vb_ebiu_awburst;
input [3 :0] vb_ebiu_awcache;
input [1 :0] vb_ebiu_awdomain;
input [5 :0] vb_ebiu_awid;
input [7 :0] vb_ebiu_awlen;
input vb_ebiu_awlock;
input [2 :0] vb_ebiu_awprot;
input [2 :0] vb_ebiu_awsize;
input [2 :0] vb_ebiu_awsnoop;
input vb_ebiu_awvalid;
input vb_ebiu_b_grant;
input [2 :0] vb_ebiu_mid;
input [127:0] vb_ebiu_wdata;
input [5 :0] vb_ebiu_wid;
input vb_ebiu_wlast;
input [15 :0] vb_ebiu_wstrb;
input vb_ebiu_wvalid;
output ebiu_ctcq_ar_grant;
output [5 :0] ebiu_ctcq_rid;
output ebiu_ctcq_rvalid;
output [39 :0] ebiu_ebiuif_acaddr;
output [4 :0] ebiu_ebiuif_acid;
output [2 :0] ebiu_ebiuif_acprot;
output [3 :0] ebiu_ebiuif_acsnoop;
output ebiu_ebiuif_acvalid;
output ebiu_ebiuif_ar_grant;
output ebiu_ebiuif_ar_grant_gate;
output ebiu_ebiuif_cd_grant;
output ebiu_ebiuif_cr_grant;
output [23 :0] ebiu_ebiuif_entry_sel;
output [127:0] ebiu_ebiuif_rdata;
output ebiu_ebiuif_rlast;
output [3 :0] ebiu_ebiuif_rresp;
output ebiu_ebiuif_snb0_rvalid;
output ebiu_ebiuif_snb1_rvalid;
output ebiu_ncq_ar_grant;
output ebiu_ncq_ar_grant_gate;
output ebiu_ncq_aw_grant;
output ebiu_ncq_aw_grant_gated;
output [7 :0] ebiu_ncq_bid;
output [1 :0] ebiu_ncq_bresp;
output ebiu_ncq_bvalid;
output [127:0] ebiu_ncq_rdata;
output [7 :0] ebiu_ncq_rid;
output ebiu_ncq_rlast;
output [1 :0] ebiu_ncq_rresp;
output ebiu_ncq_rvalid;
output ebiu_ncq_w_grant;
output [39 :0] ebiu_pad_araddr;
output [1 :0] ebiu_pad_arburst;
output [3 :0] ebiu_pad_arcache;
output [7 :0] ebiu_pad_arid;
output [7 :0] ebiu_pad_arlen;
output ebiu_pad_arlock;
output [2 :0] ebiu_pad_arprot;
output [2 :0] ebiu_pad_arsize;
output ebiu_pad_arvalid;
output [39 :0] ebiu_pad_awaddr;
output [1 :0] ebiu_pad_awburst;
output [3 :0] ebiu_pad_awcache;
output [7 :0] ebiu_pad_awid;
output [7 :0] ebiu_pad_awlen;
output ebiu_pad_awlock;
output [2 :0] ebiu_pad_awprot;
output [2 :0] ebiu_pad_awsize;
output ebiu_pad_awvalid;
output ebiu_pad_back;
output ebiu_pad_bready;
output ebiu_pad_cactive;
output ebiu_pad_csysack;
output ebiu_pad_rack;
output ebiu_pad_rready;
output [127:0] ebiu_pad_wdata;
output ebiu_pad_wlast;
output [15 :0] ebiu_pad_wstrb;
output ebiu_pad_wvalid;
output ebiu_piu0_no_op;
output ebiu_piu1_no_op;
output ebiu_piu2_no_op;
output ebiu_piu3_no_op;
output ebiu_vb_aw_grant;
output ebiu_vb_aw_grant_gated;
output [4 :0] ebiu_vb_bid;
output [1 :0] ebiu_vb_bresp;
output ebiu_vb_bvalid;
output ebiu_vb_w_grant;
output ebiu_xx_no_op;
output snb0_snpext_depd_ebiu;
output snb1_snpext_depd_ebiu;
// &Regs; @20
// &Wires; @21
wire [31 :0] ca_rd_addr_hit_cawt;
wire ciu_icg_en;
wire ciu_so_ostd_dis;
wire ciu_top_clk;
wire clk_en;
wire cpurst_b;
wire [39 :0] ctcq_ebiu_araddr;
wire [1 :0] ctcq_ebiu_arbar;
wire [1 :0] ctcq_ebiu_arburst;
wire [3 :0] ctcq_ebiu_arcache;
wire [1 :0] ctcq_ebiu_ardomain;
wire [5 :0] ctcq_ebiu_arid;
wire [7 :0] ctcq_ebiu_arlen;
wire ctcq_ebiu_arlock;
wire [2 :0] ctcq_ebiu_arprot;
wire [2 :0] ctcq_ebiu_arsize;
wire [3 :0] ctcq_ebiu_arsnoop;
wire ctcq_ebiu_arvalid;
wire ctcq_ebiu_r_grant;
wire ebiu_ctcq_ar_grant;
wire [5 :0] ebiu_ctcq_rid;
wire ebiu_ctcq_rvalid;
wire [39 :0] ebiu_ebiuif_acaddr;
wire [4 :0] ebiu_ebiuif_acid;
wire [2 :0] ebiu_ebiuif_acprot;
wire [3 :0] ebiu_ebiuif_acsnoop;
wire ebiu_ebiuif_acvalid;
wire ebiu_ebiuif_ar_grant;
wire ebiu_ebiuif_ar_grant_gate;
wire ebiu_ebiuif_cd_grant;
wire ebiu_ebiuif_cr_grant;
wire [23 :0] ebiu_ebiuif_entry_sel;
wire [127:0] ebiu_ebiuif_rdata;
wire ebiu_ebiuif_rlast;
wire [3 :0] ebiu_ebiuif_rresp;
wire ebiu_ebiuif_snb0_rvalid;
wire ebiu_ebiuif_snb1_rvalid;
wire ebiu_ncq_ar_grant;
wire ebiu_ncq_ar_grant_gate;
wire ebiu_ncq_aw_grant;
wire ebiu_ncq_aw_grant_gated;
wire [7 :0] ebiu_ncq_bid;
wire [1 :0] ebiu_ncq_bresp;
wire ebiu_ncq_bvalid;
wire [127:0] ebiu_ncq_rdata;
wire [7 :0] ebiu_ncq_rid;
wire ebiu_ncq_rlast;
wire [1 :0] ebiu_ncq_rresp;
wire ebiu_ncq_rvalid;
wire ebiu_ncq_w_grant;
wire [39 :0] ebiu_pad_araddr;
wire [1 :0] ebiu_pad_arburst;
wire [3 :0] ebiu_pad_arcache;
wire [7 :0] ebiu_pad_arid;
wire [7 :0] ebiu_pad_arlen;
wire ebiu_pad_arlock;
wire [2 :0] ebiu_pad_arprot;
wire [2 :0] ebiu_pad_arsize;
wire ebiu_pad_arvalid;
wire [39 :0] ebiu_pad_awaddr;
wire [1 :0] ebiu_pad_awburst;
wire [3 :0] ebiu_pad_awcache;
wire [7 :0] ebiu_pad_awid;
wire [7 :0] ebiu_pad_awlen;
wire ebiu_pad_awlock;
wire [2 :0] ebiu_pad_awprot;
wire [2 :0] ebiu_pad_awsize;
wire ebiu_pad_awvalid;
wire ebiu_pad_back;
wire ebiu_pad_bready;
wire ebiu_pad_cactive;
wire ebiu_pad_csysack;
wire ebiu_pad_rack;
wire ebiu_pad_rready;
wire [127:0] ebiu_pad_wdata;
wire ebiu_pad_wlast;
wire [15 :0] ebiu_pad_wstrb;
wire ebiu_pad_wvalid;
wire ebiu_piu0_no_op;
wire ebiu_piu1_no_op;
wire ebiu_piu2_no_op;
wire ebiu_piu3_no_op;
wire ebiu_read_channel_no_op;
wire ebiu_snoop_channel_no_op;
wire ebiu_vb_aw_grant;
wire ebiu_vb_aw_grant_gated;
wire [4 :0] ebiu_vb_bid;
wire [1 :0] ebiu_vb_bresp;
wire ebiu_vb_bvalid;
wire ebiu_vb_w_grant;
wire ebiu_write_channel_no_op;
wire ebiu_xx_no_op;
wire ebiuif_ebiu_ac_grant;
wire [39 :0] ebiuif_ebiu_araddr;
wire [1 :0] ebiuif_ebiu_arbar;
wire [1 :0] ebiuif_ebiu_arburst;
wire [3 :0] ebiuif_ebiu_arcache;
wire [1 :0] ebiuif_ebiu_ardomain;
wire [5 :0] ebiuif_ebiu_arid;
wire [7 :0] ebiuif_ebiu_arlen;
wire ebiuif_ebiu_arlock;
wire [2 :0] ebiuif_ebiu_arprot;
wire [2 :0] ebiuif_ebiu_arsize;
wire [3 :0] ebiuif_ebiu_arsnoop;
wire ebiuif_ebiu_arvalid;
wire [127:0] ebiuif_ebiu_cddata;
wire ebiuif_ebiu_cdlast;
wire ebiuif_ebiu_cdvalid;
wire [4 :0] ebiuif_ebiu_crresp;
wire ebiuif_ebiu_crvalid;
wire ebiuif_ebiu_r_grant;
wire [15 :0] nc_wo_rd_depd_ncwt;
wire ncq_ebiu_arvalid;
wire ncq_ebiu_awvalid;
wire ncq_ebiu_b_grant;
wire ncq_ebiu_r_grant;
wire ncq_ebiu_wvalid;
wire [3 :0] ncq_so_vld;
wire [39 :0] ncq_xx_araddr;
wire [1 :0] ncq_xx_arbar;
wire [1 :0] ncq_xx_arburst;
wire [3 :0] ncq_xx_arcache;
wire [1 :0] ncq_xx_ardomain;
wire [7 :0] ncq_xx_arid;
wire [7 :0] ncq_xx_arlen;
wire ncq_xx_arlock;
wire [2 :0] ncq_xx_arprot;
wire [2 :0] ncq_xx_arsize;
wire [3 :0] ncq_xx_arsnoop;
wire ncq_xx_aw_needissue;
wire [39 :0] ncq_xx_awaddr;
wire [1 :0] ncq_xx_awbar;
wire [1 :0] ncq_xx_awburst;
wire [3 :0] ncq_xx_awcache;
wire [1 :0] ncq_xx_awdomain;
wire [7 :0] ncq_xx_awid;
wire [7 :0] ncq_xx_awlen;
wire ncq_xx_awlock;
wire [2 :0] ncq_xx_awprot;
wire [2 :0] ncq_xx_awsize;
wire [2 :0] ncq_xx_awsnoop;
wire [127:0] ncq_xx_wdata;
wire [7 :0] ncq_xx_wid;
wire ncq_xx_wlast;
wire [15 :0] ncq_xx_wstrb;
wire pad_ebiu_arready;
wire pad_ebiu_awready;
wire [7 :0] pad_ebiu_bid;
wire [1 :0] pad_ebiu_bresp;
wire pad_ebiu_bvalid;
wire pad_ebiu_csysreq;
wire [127:0] pad_ebiu_rdata;
wire [7 :0] pad_ebiu_rid;
wire pad_ebiu_rlast;
wire [1 :0] pad_ebiu_rresp;
wire pad_ebiu_rvalid;
wire pad_ebiu_wready;
wire pad_yy_icg_scan_en;
wire snb0_snpext_depd_ebiu;
wire [7 :0] snb0_yy_snpext_index;
wire snb1_snpext_depd_ebiu;
wire [7 :0] snb1_yy_snpext_index;
wire [39 :0] vb_ebiu_awaddr;
wire [1 :0] vb_ebiu_awbar;
wire [1 :0] vb_ebiu_awburst;
wire [3 :0] vb_ebiu_awcache;
wire [1 :0] vb_ebiu_awdomain;
wire [5 :0] vb_ebiu_awid;
wire [7 :0] vb_ebiu_awlen;
wire vb_ebiu_awlock;
wire [2 :0] vb_ebiu_awprot;
wire [2 :0] vb_ebiu_awsize;
wire [2 :0] vb_ebiu_awsnoop;
wire vb_ebiu_awvalid;
wire vb_ebiu_b_grant;
wire [2 :0] vb_ebiu_mid;
wire [127:0] vb_ebiu_wdata;
wire [5 :0] vb_ebiu_wid;
wire vb_ebiu_wlast;
wire [15 :0] vb_ebiu_wstrb;
wire vb_ebiu_wvalid;
// &Instance("ct_ebiu_read_channel"); @23
ct_ebiu_read_channel x_ct_ebiu_read_channel (
.ca_rd_addr_hit_cawt (ca_rd_addr_hit_cawt ),
.ciu_icg_en (ciu_icg_en ),
.clk_en (clk_en ),
.cpurst_b (cpurst_b ),
.ctcq_ebiu_araddr (ctcq_ebiu_araddr ),
.ctcq_ebiu_arbar (ctcq_ebiu_arbar ),
.ctcq_ebiu_arburst (ctcq_ebiu_arburst ),
.ctcq_ebiu_arcache (ctcq_ebiu_arcache ),
.ctcq_ebiu_ardomain (ctcq_ebiu_ardomain ),
.ctcq_ebiu_arid (ctcq_ebiu_arid ),
.ctcq_ebiu_arlen (ctcq_ebiu_arlen ),
.ctcq_ebiu_arlock (ctcq_ebiu_arlock ),
.ctcq_ebiu_arprot (ctcq_ebiu_arprot ),
.ctcq_ebiu_arsize (ctcq_ebiu_arsize ),
.ctcq_ebiu_arsnoop (ctcq_ebiu_arsnoop ),
.ctcq_ebiu_arvalid (ctcq_ebiu_arvalid ),
.ctcq_ebiu_r_grant (ctcq_ebiu_r_grant ),
.ebiu_ctcq_ar_grant (ebiu_ctcq_ar_grant ),
.ebiu_ctcq_rid (ebiu_ctcq_rid ),
.ebiu_ctcq_rvalid (ebiu_ctcq_rvalid ),
.ebiu_ebiuif_ar_grant (ebiu_ebiuif_ar_grant ),
.ebiu_ebiuif_ar_grant_gate (ebiu_ebiuif_ar_grant_gate),
.ebiu_ebiuif_entry_sel (ebiu_ebiuif_entry_sel ),
.ebiu_ebiuif_rdata (ebiu_ebiuif_rdata ),
.ebiu_ebiuif_rlast (ebiu_ebiuif_rlast ),
.ebiu_ebiuif_rresp (ebiu_ebiuif_rresp ),
.ebiu_ebiuif_snb0_rvalid (ebiu_ebiuif_snb0_rvalid ),
.ebiu_ebiuif_snb1_rvalid (ebiu_ebiuif_snb1_rvalid ),
.ebiu_ncq_ar_grant (ebiu_ncq_ar_grant ),
.ebiu_ncq_ar_grant_gate (ebiu_ncq_ar_grant_gate ),
.ebiu_ncq_rdata (ebiu_ncq_rdata ),
.ebiu_ncq_rid (ebiu_ncq_rid ),
.ebiu_ncq_rlast (ebiu_ncq_rlast ),
.ebiu_ncq_rresp (ebiu_ncq_rresp ),
.ebiu_ncq_rvalid (ebiu_ncq_rvalid ),
.ebiu_pad_araddr (ebiu_pad_araddr ),
.ebiu_pad_arburst (ebiu_pad_arburst ),
.ebiu_pad_arcache (ebiu_pad_arcache ),
.ebiu_pad_arid (ebiu_pad_arid ),
.ebiu_pad_arlen (ebiu_pad_arlen ),
.ebiu_pad_arlock (ebiu_pad_arlock ),
.ebiu_pad_arprot (ebiu_pad_arprot ),
.ebiu_pad_arsize (ebiu_pad_arsize ),
.ebiu_pad_arvalid (ebiu_pad_arvalid ),
.ebiu_pad_rack (ebiu_pad_rack ),
.ebiu_pad_rready (ebiu_pad_rready ),
.ebiu_read_channel_no_op (ebiu_read_channel_no_op ),
.ebiuif_ebiu_araddr (ebiuif_ebiu_araddr ),
.ebiuif_ebiu_arbar (ebiuif_ebiu_arbar ),
.ebiuif_ebiu_arburst (ebiuif_ebiu_arburst ),
.ebiuif_ebiu_arcache (ebiuif_ebiu_arcache ),
.ebiuif_ebiu_ardomain (ebiuif_ebiu_ardomain ),
.ebiuif_ebiu_arid (ebiuif_ebiu_arid ),
.ebiuif_ebiu_arlen (ebiuif_ebiu_arlen ),
.ebiuif_ebiu_arlock (ebiuif_ebiu_arlock ),
.ebiuif_ebiu_arprot (ebiuif_ebiu_arprot ),
.ebiuif_ebiu_arsize (ebiuif_ebiu_arsize ),
.ebiuif_ebiu_arsnoop (ebiuif_ebiu_arsnoop ),
.ebiuif_ebiu_arvalid (ebiuif_ebiu_arvalid ),
.ebiuif_ebiu_r_grant (ebiuif_ebiu_r_grant ),
.forever_cpuclk (ciu_top_clk ),
.nc_wo_rd_depd_ncwt (nc_wo_rd_depd_ncwt ),
.ncq_ebiu_arvalid (ncq_ebiu_arvalid ),
.ncq_ebiu_r_grant (ncq_ebiu_r_grant ),
.ncq_so_vld (ncq_so_vld ),
.ncq_xx_araddr (ncq_xx_araddr ),
.ncq_xx_arbar (ncq_xx_arbar ),
.ncq_xx_arburst (ncq_xx_arburst ),
.ncq_xx_arcache (ncq_xx_arcache ),
.ncq_xx_ardomain (ncq_xx_ardomain ),
.ncq_xx_arid (ncq_xx_arid ),
.ncq_xx_arlen (ncq_xx_arlen ),
.ncq_xx_arlock (ncq_xx_arlock ),
.ncq_xx_arprot (ncq_xx_arprot ),
.ncq_xx_arsize (ncq_xx_arsize ),
.ncq_xx_arsnoop (ncq_xx_arsnoop ),
.pad_ebiu_arready (pad_ebiu_arready ),
.pad_ebiu_rdata (pad_ebiu_rdata ),
.pad_ebiu_rid (pad_ebiu_rid ),
.pad_ebiu_rlast (pad_ebiu_rlast ),
.pad_ebiu_rresp (pad_ebiu_rresp ),
.pad_ebiu_rvalid (pad_ebiu_rvalid ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.forever_cpuclk (ciu_top_clk)); @24
// &Instance("ct_ebiu_snoop_channel"); @26
// &Connect(.ciu_clk (forever_cpuclk)); @27
// &Connect(.forever_cpuclk (ciu_top_clk)); @28
// &Instance("ct_ebiu_snoop_channel"); @31
// &Connect(.ciu_clk (forever_cpuclk)); @32
// &Connect(.forever_cpuclk (ciu_top_clk)); @33
// &Instance("ct_ebiu_snoop_channel_dummy"); @35
ct_ebiu_snoop_channel_dummy x_ct_ebiu_snoop_channel_dummy (
.ebiu_ebiuif_acaddr (ebiu_ebiuif_acaddr ),
.ebiu_ebiuif_acid (ebiu_ebiuif_acid ),
.ebiu_ebiuif_acprot (ebiu_ebiuif_acprot ),
.ebiu_ebiuif_acsnoop (ebiu_ebiuif_acsnoop ),
.ebiu_ebiuif_acvalid (ebiu_ebiuif_acvalid ),
.ebiu_ebiuif_cd_grant (ebiu_ebiuif_cd_grant ),
.ebiu_ebiuif_cr_grant (ebiu_ebiuif_cr_grant ),
.ebiu_snoop_channel_no_op (ebiu_snoop_channel_no_op),
.ebiuif_ebiu_ac_grant (ebiuif_ebiu_ac_grant ),
.ebiuif_ebiu_cddata (ebiuif_ebiu_cddata ),
.ebiuif_ebiu_cdlast (ebiuif_ebiu_cdlast ),
.ebiuif_ebiu_cdvalid (ebiuif_ebiu_cdvalid ),
.ebiuif_ebiu_crresp (ebiuif_ebiu_crresp ),
.ebiuif_ebiu_crvalid (ebiuif_ebiu_crvalid )
);
// &Instance("ct_ebiu_write_channel"); @38
ct_ebiu_write_channel x_ct_ebiu_write_channel (
.ca_rd_addr_hit_cawt (ca_rd_addr_hit_cawt ),
.ciu_icg_en (ciu_icg_en ),
.ciu_so_ostd_dis (ciu_so_ostd_dis ),
.clk_en (clk_en ),
.cpurst_b (cpurst_b ),
.ebiu_ncq_aw_grant (ebiu_ncq_aw_grant ),
.ebiu_ncq_aw_grant_gated (ebiu_ncq_aw_grant_gated ),
.ebiu_ncq_bid (ebiu_ncq_bid ),
.ebiu_ncq_bresp (ebiu_ncq_bresp ),
.ebiu_ncq_bvalid (ebiu_ncq_bvalid ),
.ebiu_ncq_w_grant (ebiu_ncq_w_grant ),
.ebiu_pad_awaddr (ebiu_pad_awaddr ),
.ebiu_pad_awburst (ebiu_pad_awburst ),
.ebiu_pad_awcache (ebiu_pad_awcache ),
.ebiu_pad_awid (ebiu_pad_awid ),
.ebiu_pad_awlen (ebiu_pad_awlen ),
.ebiu_pad_awlock (ebiu_pad_awlock ),
.ebiu_pad_awprot (ebiu_pad_awprot ),
.ebiu_pad_awsize (ebiu_pad_awsize ),
.ebiu_pad_awvalid (ebiu_pad_awvalid ),
.ebiu_pad_back (ebiu_pad_back ),
.ebiu_pad_bready (ebiu_pad_bready ),
.ebiu_pad_wdata (ebiu_pad_wdata ),
.ebiu_pad_wlast (ebiu_pad_wlast ),
.ebiu_pad_wstrb (ebiu_pad_wstrb ),
.ebiu_pad_wvalid (ebiu_pad_wvalid ),
.ebiu_piu0_no_op (ebiu_piu0_no_op ),
.ebiu_piu1_no_op (ebiu_piu1_no_op ),
.ebiu_piu2_no_op (ebiu_piu2_no_op ),
.ebiu_piu3_no_op (ebiu_piu3_no_op ),
.ebiu_vb_aw_grant (ebiu_vb_aw_grant ),
.ebiu_vb_aw_grant_gated (ebiu_vb_aw_grant_gated ),
.ebiu_vb_bid (ebiu_vb_bid ),
.ebiu_vb_bresp (ebiu_vb_bresp ),
.ebiu_vb_bvalid (ebiu_vb_bvalid ),
.ebiu_vb_w_grant (ebiu_vb_w_grant ),
.ebiu_write_channel_no_op (ebiu_write_channel_no_op),
.ebiuif_ebiu_araddr (ebiuif_ebiu_araddr ),
.forever_cpuclk (ciu_top_clk ),
.nc_wo_rd_depd_ncwt (nc_wo_rd_depd_ncwt ),
.ncq_ebiu_awvalid (ncq_ebiu_awvalid ),
.ncq_ebiu_b_grant (ncq_ebiu_b_grant ),
.ncq_ebiu_wvalid (ncq_ebiu_wvalid ),
.ncq_so_vld (ncq_so_vld ),
.ncq_xx_araddr (ncq_xx_araddr ),
.ncq_xx_aw_needissue (ncq_xx_aw_needissue ),
.ncq_xx_awaddr (ncq_xx_awaddr ),
.ncq_xx_awbar (ncq_xx_awbar ),
.ncq_xx_awburst (ncq_xx_awburst ),
.ncq_xx_awcache (ncq_xx_awcache ),
.ncq_xx_awdomain (ncq_xx_awdomain ),
.ncq_xx_awid (ncq_xx_awid ),
.ncq_xx_awlen (ncq_xx_awlen ),
.ncq_xx_awlock (ncq_xx_awlock ),
.ncq_xx_awprot (ncq_xx_awprot ),
.ncq_xx_awsize (ncq_xx_awsize ),
.ncq_xx_awsnoop (ncq_xx_awsnoop ),
.ncq_xx_wdata (ncq_xx_wdata ),
.ncq_xx_wid (ncq_xx_wid ),
.ncq_xx_wlast (ncq_xx_wlast ),
.ncq_xx_wstrb (ncq_xx_wstrb ),
.pad_ebiu_awready (pad_ebiu_awready ),
.pad_ebiu_bid (pad_ebiu_bid ),
.pad_ebiu_bresp (pad_ebiu_bresp ),
.pad_ebiu_bvalid (pad_ebiu_bvalid ),
.pad_ebiu_wready (pad_ebiu_wready ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.snb0_snpext_depd_ebiu (snb0_snpext_depd_ebiu ),
.snb0_yy_snpext_index (snb0_yy_snpext_index ),
.snb1_snpext_depd_ebiu (snb1_snpext_depd_ebiu ),
.snb1_yy_snpext_index (snb1_yy_snpext_index ),
.vb_ebiu_awaddr (vb_ebiu_awaddr ),
.vb_ebiu_awbar (vb_ebiu_awbar ),
.vb_ebiu_awburst (vb_ebiu_awburst ),
.vb_ebiu_awcache (vb_ebiu_awcache ),
.vb_ebiu_awdomain (vb_ebiu_awdomain ),
.vb_ebiu_awid (vb_ebiu_awid ),
.vb_ebiu_awlen (vb_ebiu_awlen ),
.vb_ebiu_awlock (vb_ebiu_awlock ),
.vb_ebiu_awprot (vb_ebiu_awprot ),
.vb_ebiu_awsize (vb_ebiu_awsize ),
.vb_ebiu_awsnoop (vb_ebiu_awsnoop ),
.vb_ebiu_awvalid (vb_ebiu_awvalid ),
.vb_ebiu_b_grant (vb_ebiu_b_grant ),
.vb_ebiu_mid (vb_ebiu_mid ),
.vb_ebiu_wdata (vb_ebiu_wdata ),
.vb_ebiu_wid (vb_ebiu_wid ),
.vb_ebiu_wlast (vb_ebiu_wlast ),
.vb_ebiu_wstrb (vb_ebiu_wstrb ),
.vb_ebiu_wvalid (vb_ebiu_wvalid )
);
// &Connect(.forever_cpuclk (ciu_top_clk)); @39
// &Instance("ct_ebiu_lowpower"); @41
ct_ebiu_lowpower x_ct_ebiu_lowpower (
.clk_en (clk_en ),
.cpurst_b (cpurst_b ),
.ebiu_pad_cactive (ebiu_pad_cactive ),
.ebiu_pad_csysack (ebiu_pad_csysack ),
.ebiu_read_channel_no_op (ebiu_read_channel_no_op ),
.ebiu_snoop_channel_no_op (ebiu_snoop_channel_no_op),
.ebiu_write_channel_no_op (ebiu_write_channel_no_op),
.ebiu_xx_no_op (ebiu_xx_no_op ),
.forever_cpuclk (ciu_top_clk ),
.pad_ebiu_csysreq (pad_ebiu_csysreq )
);
// &Connect(.forever_cpuclk (ciu_top_clk)); @42
// &ModuleEnd; @83
endmodule |
module ct_ciu_ncq_gm(
ciu_icg_en,
cpurst_b,
forever_cpuclk,
gm_aw_req,
gm_ctrl_clk,
gm_set_vld_gate_x,
gm_set_vld_x,
gm_success_x,
gm_vld_x,
pad_yy_icg_scan_en,
raq_pop_bus,
waq_pop_bus,
waq_pop_en
);
// &Ports; @24
input ciu_icg_en;
input cpurst_b;
input forever_cpuclk;
input gm_aw_req;
input gm_ctrl_clk;
input gm_set_vld_gate_x;
input gm_set_vld_x;
input pad_yy_icg_scan_en;
input [73:0] raq_pop_bus;
input [73:0] waq_pop_bus;
input waq_pop_en;
output gm_success_x;
output gm_vld_x;
// &Regs; @25
reg [73:0] gm_cont;
reg gm_exclusive;
// &Wires; @26
wire ciu_icg_en;
wire cpurst_b;
wire forever_cpuclk;
wire gm_aw_req;
wire gm_clk;
wire gm_clr_vld;
wire gm_ctrl_clk;
wire gm_set_vld_gate_x;
wire gm_set_vld_x;
wire gm_success_x;
wire gm_vld_x;
wire pad_yy_icg_scan_en;
wire [73:0] raq_pop_bus;
wire [73:0] waq_pop_bus;
wire waq_pop_en;
parameter ADDRW = 40;
parameter LOCK = 10;
parameter ADDR_0 = 34;
parameter ADDRH = 73; //ADDRW -1 + ADDR_0;
parameter GMWIDTH = 74; //ADDRW + ADDR_0;
assign gm_clr_vld = gm_aw_req && waq_pop_en &&
(waq_pop_bus[ADDRH:ADDR_0] == gm_cont[ADDRH:ADDR_0]);
assign gm_success_x = gm_aw_req && waq_pop_bus[LOCK] &&
gm_exclusive &&
(gm_cont[GMWIDTH-1:0] == waq_pop_bus[GMWIDTH-1:0]);
always @(posedge gm_ctrl_clk or negedge cpurst_b)
begin
if (!cpurst_b)
gm_exclusive <= 1'b0;
else if (gm_clr_vld)
gm_exclusive <= 1'b0;
else if (gm_set_vld_x)
gm_exclusive <= 1'b1;
end
assign gm_vld_x = gm_exclusive;
always @(posedge gm_clk or negedge cpurst_b)
begin
if (!cpurst_b)
gm_cont[GMWIDTH-1:0] <= {GMWIDTH{1'b0}};
else if (gm_set_vld_x)
gm_cont[GMWIDTH-1:0] <= raq_pop_bus[GMWIDTH-1:0];
end
// &Instance("gated_clk_cell", "x_ncq_gm_gated_clk"); @62
gated_clk_cell x_ncq_gm_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (gm_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (gm_set_vld_gate_x ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @63
// .external_en (1'b0), @64
// .global_en (1'b1), @65
// .module_en (ciu_icg_en ), @66
// .local_en (gm_set_vld_gate_x), @67
// .clk_out (gm_clk)); @68
// &ModuleEnd; @70
endmodule |
module ct_piu_other_io_sync(
ciu_ibiu_csr_cmplt,
ciu_ibiu_csr_rdata,
ciu_ibiu_dbgrq_b,
ciu_ibiu_hpcp_l2of_int,
ciu_ibiu_me_int,
ciu_ibiu_ms_int,
ciu_ibiu_mt_int,
ciu_ibiu_se_int,
ciu_ibiu_ss_int,
ciu_ibiu_st_int,
ciu_icg_en,
cpurst_b,
forever_cpuclk,
ibiu_ciu_cnt_en,
ibiu_ciu_csr_sel,
ibiu_ciu_csr_wdata,
ibiu_ciu_jdb_pm,
ibiu_ciu_lpmd_b,
l2cif_piu_read_data_vld,
l2cif_piux_read_data,
pad_yy_icg_scan_en,
perr_l2pmp_x,
piu_csr_sel,
piu_l2cif_read_data,
piu_l2cif_read_data_ecc,
piu_l2cif_read_index,
piu_l2cif_read_req,
piu_l2cif_read_tag,
piu_l2cif_read_tag_ecc,
piu_l2cif_read_way,
piu_regs_hpcp_cnt_en,
piu_regs_op,
piu_regs_sel,
piu_regs_wdata,
piu_sysio_jdb_pm,
piu_sysio_lpmd_b,
piu_xx_regs_no_op,
pready_l2pmp_x,
psel_l2pmp_x,
regs_piu_cmplt,
regs_piu_hpcp_l2of_int,
regs_piux_rdata,
sysio_piu_dbgrq_b,
sysio_piu_me_int,
sysio_piu_ms_int,
sysio_piu_mt_int,
sysio_piu_se_int,
sysio_piu_ss_int,
sysio_piu_st_int,
x_prdata_l2pmp
);
// &Ports; @24
input ciu_icg_en;
input cpurst_b;
input forever_cpuclk;
input [3 :0] ibiu_ciu_cnt_en;
input ibiu_ciu_csr_sel;
input [79 :0] ibiu_ciu_csr_wdata;
input ibiu_ciu_jdb_pm;
input ibiu_ciu_lpmd_b;
input l2cif_piu_read_data_vld;
input [127:0] l2cif_piux_read_data;
input pad_yy_icg_scan_en;
input psel_l2pmp_x;
input regs_piu_cmplt;
input [3 :0] regs_piu_hpcp_l2of_int;
input [63 :0] regs_piux_rdata;
input sysio_piu_dbgrq_b;
input sysio_piu_me_int;
input sysio_piu_ms_int;
input sysio_piu_mt_int;
input sysio_piu_se_int;
input sysio_piu_ss_int;
input sysio_piu_st_int;
output ciu_ibiu_csr_cmplt;
output [127:0] ciu_ibiu_csr_rdata;
output ciu_ibiu_dbgrq_b;
output [3 :0] ciu_ibiu_hpcp_l2of_int;
output ciu_ibiu_me_int;
output ciu_ibiu_ms_int;
output ciu_ibiu_mt_int;
output ciu_ibiu_se_int;
output ciu_ibiu_ss_int;
output ciu_ibiu_st_int;
output perr_l2pmp_x;
output piu_csr_sel;
output piu_l2cif_read_data;
output piu_l2cif_read_data_ecc;
output [20 :0] piu_l2cif_read_index;
output piu_l2cif_read_req;
output piu_l2cif_read_tag;
output piu_l2cif_read_tag_ecc;
output [3 :0] piu_l2cif_read_way;
output [3 :0] piu_regs_hpcp_cnt_en;
output [15 :0] piu_regs_op;
output piu_regs_sel;
output [63 :0] piu_regs_wdata;
output [1 :0] piu_sysio_jdb_pm;
output [1 :0] piu_sysio_lpmd_b;
output piu_xx_regs_no_op;
output pready_l2pmp_x;
output [31 :0] x_prdata_l2pmp;
// &Regs; @25
reg ciu_ibiu_csr_cmplt;
reg [127:0] ciu_ibiu_csr_rdata;
reg cp0_csr_sel;
reg [79 :0] cp0_csr_wdata;
reg dbgon;
reg in_lpmd_b;
reg [3 :0] piu_regs_hpcp_cnt_en;
// &Wires; @26
wire ciu_ibiu_dbgrq_b;
wire [3 :0] ciu_ibiu_hpcp_l2of_int;
wire ciu_ibiu_me_int;
wire ciu_ibiu_ms_int;
wire ciu_ibiu_mt_int;
wire ciu_ibiu_se_int;
wire ciu_ibiu_ss_int;
wire ciu_ibiu_st_int;
wire ciu_icg_en;
wire cp0_csr_cmplt;
wire [127:0] cp0_csr_rdata;
wire cpurst_b;
wire forever_cpuclk;
wire [3 :0] ibiu_ciu_cnt_en;
wire ibiu_ciu_csr_sel;
wire [79 :0] ibiu_ciu_csr_wdata;
wire ibiu_ciu_jdb_pm;
wire ibiu_ciu_lpmd_b;
wire l2cif_piu_read_data_vld;
wire [127:0] l2cif_piux_read_data;
wire l2reg_oclk;
wire l2reg_oclk_en;
wire pad_yy_icg_scan_en;
wire perr_l2pmp_x;
wire piu_csr_sel;
wire piu_l2cif_read_data;
wire piu_l2cif_read_data_ecc;
wire [20 :0] piu_l2cif_read_index;
wire piu_l2cif_read_req;
wire piu_l2cif_read_tag;
wire piu_l2cif_read_tag_ecc;
wire [3 :0] piu_l2cif_read_way;
wire [15 :0] piu_regs_op;
wire piu_regs_sel;
wire [63 :0] piu_regs_wdata;
wire [1 :0] piu_sysio_jdb_pm;
wire [1 :0] piu_sysio_lpmd_b;
wire piu_xx_regs_no_op;
wire pready_l2pmp_x;
wire regs_piu_cmplt;
wire [3 :0] regs_piu_hpcp_l2of_int;
wire [63 :0] regs_piux_rdata;
wire sysio_piu_dbgrq_b;
wire sysio_piu_me_int;
wire sysio_piu_ms_int;
wire sysio_piu_mt_int;
wire sysio_piu_se_int;
wire sysio_piu_ss_int;
wire sysio_piu_st_int;
wire [31 :0] x_prdata_l2pmp;
// &Instance("gated_clk_cell", "x_ct_apbif_req_cpu_gated_clk"); @33
// &Connect(.clk_in (forever_cpuclk), @34
// .external_en (1'b0), @35
// .global_en (1'b1), @36
// .module_en (ciu_icg_en), @37
// .local_en (apbif_req_cpu_clk_en), @38
// .clk_out (apbif_req_cpu_clk)); @39
// &Instance("gated_clk_cell", "x_ct_apbif_in_gated_clk"); @42
// &Connect(.clk_in (forever_cpuclk), @43
// .external_en (1'b0), @44
// .global_en (1'b1), @45
// .module_en (ciu_icg_en), @46
// .local_en (apbif_iclk_en), @47
// .clk_out (apbif_iclk)); @48
// &Instance("gated_clk_cell", "x_ct_apbif_cmplt_cpu_gated_clk"); @51
// &Connect(.clk_in (forever_cpuclk), @52
// .external_en (1'b0), @53
// .global_en (1'b1), @54
// .module_en (ciu_icg_en), @55
// .local_en (apbif_cmplt_apb_clk_en), @56
// .clk_out (apbif_cmplt_apb_clk)); @57
// &Force("input", "psel_l2pmp_x"); @157
assign pready_l2pmp_x = 1'b1;
assign perr_l2pmp_x = 1'b0;
assign x_prdata_l2pmp[31:0] = 32'b0;
//==============================================================================
// L2C CSR and RAM IF
//==============================================================================
//================================================
// request from core
//================================================
parameter DCA = 79;
parameter REG_7 = 75;
parameter REG_0 = 68;
parameter WT = 67;
parameter CSRRW = 66;
parameter CSRRS = 65;
parameter CSRRC = 64;
parameter RID_3 = 31;
parameter RID_0 = 28;
parameter WAY_3 = 24;
parameter WAY_0 = 21;
parameter IDX_20 = 20;
parameter IDX_0 = 0;
always@(posedge forever_cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
cp0_csr_sel <= 1'b0;
else if (ibiu_ciu_csr_sel)
cp0_csr_sel <= 1'b1;
else if (cp0_csr_cmplt)
cp0_csr_sel <= 1'b0;
end
always@(posedge forever_cpuclk)
begin
if (ibiu_ciu_csr_sel)
cp0_csr_wdata[79:0] <= ibiu_ciu_csr_wdata[79:0];
end
//for ciu top ICG
assign piu_csr_sel = cp0_csr_sel;
assign piu_xx_regs_no_op = !cp0_csr_sel;
assign piu_regs_sel = cp0_csr_sel & !cp0_csr_wdata[DCA];
assign piu_regs_op[15:0] = cp0_csr_wdata[DCA:CSRRC];
assign piu_regs_wdata[63:0] = cp0_csr_wdata[63:0];
assign piu_l2cif_read_req = cp0_csr_sel & cp0_csr_wdata[DCA];
assign piu_l2cif_read_tag = cp0_csr_wdata[RID_3:RID_0] == 4'd4;
assign piu_l2cif_read_data = cp0_csr_wdata[RID_3:RID_0] == 4'd5;
assign piu_l2cif_read_tag_ecc = 1'b0;
assign piu_l2cif_read_data_ecc = 1'b0;
assign piu_l2cif_read_way[3:0] = cp0_csr_wdata[WAY_3:WAY_0];
assign piu_l2cif_read_index[20:0] = cp0_csr_wdata[IDX_20:IDX_0];
//================================================
// cmplt to core
//================================================
// &Force("output", "ciu_ibiu_csr_cmplt"); @223
assign cp0_csr_cmplt = l2cif_piu_read_data_vld | regs_piu_cmplt;
assign cp0_csr_rdata[127:0] = {128{l2cif_piu_read_data_vld}} & l2cif_piux_read_data[127:0] |
{128{regs_piu_cmplt}} & {64'b0,regs_piux_rdata[63:0]};
always@(posedge l2reg_oclk or negedge cpurst_b)
begin
if (!cpurst_b)
ciu_ibiu_csr_cmplt <= 1'b0;
else
ciu_ibiu_csr_cmplt <= cp0_csr_cmplt;
end
always@(posedge l2reg_oclk)
begin
if (cp0_csr_cmplt)
ciu_ibiu_csr_rdata[127:0] <= cp0_csr_rdata[127:0];
end
//================================================
// other signals from core to top
//================================================
always@(posedge forever_cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)begin
in_lpmd_b <= 1'b1;
dbgon <= 1'b0;
end
else begin
in_lpmd_b <= ibiu_ciu_lpmd_b;
dbgon <= ibiu_ciu_jdb_pm;
end
end
assign piu_sysio_jdb_pm[1:0] = dbgon
? 2'b10
: (!in_lpmd_b) ? 2'b01 : 2'b00;
assign piu_sysio_lpmd_b[1:0] = {in_lpmd_b,in_lpmd_b};
always@(posedge forever_cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
piu_regs_hpcp_cnt_en[3:0] <= 4'b0;
else
piu_regs_hpcp_cnt_en[3:0] <= ibiu_ciu_cnt_en[3:0];
end
assign ciu_ibiu_hpcp_l2of_int[3:0] = regs_piu_hpcp_l2of_int[3:0];
//================================================
// other signals from top to core
//================================================
assign ciu_ibiu_me_int = sysio_piu_me_int;
assign ciu_ibiu_mt_int = sysio_piu_mt_int;
assign ciu_ibiu_ms_int = sysio_piu_ms_int;
assign ciu_ibiu_se_int = sysio_piu_se_int;
assign ciu_ibiu_st_int = sysio_piu_st_int;
assign ciu_ibiu_ss_int = sysio_piu_ss_int;
assign ciu_ibiu_dbgrq_b = sysio_piu_dbgrq_b;
//================================================
// ICG
//================================================
assign l2reg_oclk_en = cp0_csr_cmplt | ciu_ibiu_csr_cmplt;
// &Instance("gated_clk_cell", "x_ct_l2reg_out_gated_clk"); @306
gated_clk_cell x_ct_l2reg_out_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (l2reg_oclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2reg_oclk_en ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @307
// .external_en (1'b0), @308
// .global_en (1'b1), @309
// .module_en (ciu_icg_en), @310
// .local_en (l2reg_oclk_en), @311
// .clk_out (l2reg_oclk)); @312
// &ModuleEnd; @314
endmodule |
module ct_ciu_vb_aw_entry(
ciu_icg_en,
cpurst_b,
ebiuif_vb_index,
forever_cpuclk,
l2c0_vb_wbus,
l2c0_wvalid_x,
l2c1_vb_wbus,
l2c1_wvalid_x,
pad_yy_icg_scan_en,
snb0_snpext_addr_hit_x,
snb0_vb_wbus,
snb0_wvalid_x,
snb0_yy_snpext_index,
snb1_snpext_addr_hit_x,
snb1_vb_wbus,
snb1_wvalid_x,
snb1_yy_snpext_index,
vb_aw_create_bus,
vb_aw_create_mid,
vb_aw_create_sel_x,
vb_aw_en_x,
vb_aw_req_sel_x,
vb_aw_vld_x,
vb_ctrl_clk,
vb_entryx_awbus,
vb_entryx_mid,
vb_entryx_offset,
vb_entryx_wbus,
vb_snb_addr_hit_x,
vb_w_pop_sel_x,
vb_w_vld_x
);
// &Ports; @24
input ciu_icg_en;
input cpurst_b;
input [7 :0] ebiuif_vb_index;
input forever_cpuclk;
input [534:0] l2c0_vb_wbus;
input l2c0_wvalid_x;
input [534:0] l2c1_vb_wbus;
input l2c1_wvalid_x;
input pad_yy_icg_scan_en;
input [534:0] snb0_vb_wbus;
input snb0_wvalid_x;
input [7 :0] snb0_yy_snpext_index;
input [534:0] snb1_vb_wbus;
input snb1_wvalid_x;
input [7 :0] snb1_yy_snpext_index;
input [67 :0] vb_aw_create_bus;
input [2 :0] vb_aw_create_mid;
input vb_aw_create_sel_x;
input vb_aw_req_sel_x;
input vb_ctrl_clk;
input vb_w_pop_sel_x;
output snb0_snpext_addr_hit_x;
output snb1_snpext_addr_hit_x;
output vb_aw_en_x;
output vb_aw_vld_x;
output [67 :0] vb_entryx_awbus;
output [2 :0] vb_entryx_mid;
output [1 :0] vb_entryx_offset;
output [534:0] vb_entryx_wbus;
output vb_snb_addr_hit_x;
output vb_w_vld_x;
// &Regs; @25
reg [67 :0] vb_aw_bus;
reg vb_aw_en;
reg [2 :0] vb_aw_mid;
reg vb_aw_vld;
reg [534:0] vb_w_bus;
reg vb_w_vld;
// &Wires; @26
wire ciu_icg_en;
wire cpurst_b;
wire [7 :0] ebiuif_vb_index;
wire forever_cpuclk;
wire [534:0] l2c0_vb_wbus;
wire l2c0_wvalid_x;
wire [534:0] l2c1_vb_wbus;
wire l2c1_wvalid_x;
wire pad_yy_icg_scan_en;
wire snb0_snpext_addr_hit_x;
wire [534:0] snb0_vb_wbus;
wire snb0_wvalid_x;
wire [7 :0] snb0_yy_snpext_index;
wire snb1_snpext_addr_hit_x;
wire [534:0] snb1_vb_wbus;
wire snb1_wvalid_x;
wire [7 :0] snb1_yy_snpext_index;
wire [67 :0] vb_aw_create_bus;
wire [2 :0] vb_aw_create_mid;
wire vb_aw_create_sel_x;
wire vb_aw_en_x;
wire vb_aw_req_sel_x;
wire vb_aw_vld_x;
wire vb_ctrl_clk;
wire vb_entry_awclk;
wire vb_entry_wclk;
wire [67 :0] vb_entryx_awbus;
wire [2 :0] vb_entryx_mid;
wire [1 :0] vb_entryx_offset;
wire [534:0] vb_entryx_wbus;
wire vb_snb_addr_hit_x;
wire [534:0] vb_w_create_bus;
wire vb_w_create_sel;
wire vb_w_pop_sel_x;
wire vb_w_vld_x;
//======================================
// CA Write Table CA_WT(WT)
//1. CA_WT : non-cacheable write
//entry content:
//| vld | addr
//======================================
//CA_WT vld
parameter ADDR_4 = 4;
parameter ADDR_5 = 5;
parameter ADDR_6 = 6;
parameter ADDR_13 = 13;
parameter WIDTH = 68;
parameter DWIDTH = 535;
always @(posedge vb_ctrl_clk or negedge cpurst_b)
begin
if(~cpurst_b)
vb_aw_vld <= 1'b0;
else if(vb_aw_create_sel_x)
vb_aw_vld <= 1'b1;
else if(vb_w_pop_sel_x)
vb_aw_vld <= 1'b0;
end
always @(posedge vb_ctrl_clk or negedge cpurst_b)
begin
if(~cpurst_b)
vb_aw_en <= 1'b0;
else if(vb_aw_create_sel_x)
vb_aw_en <= 1'b1;
else if(vb_aw_req_sel_x)
vb_aw_en <= 1'b0;
end
always @(posedge vb_entry_awclk or negedge cpurst_b)
begin
if(~cpurst_b)
vb_aw_bus[WIDTH-1:0] <= {WIDTH{1'b0}};
else if(vb_aw_create_sel_x)
vb_aw_bus[WIDTH-1:0] <= vb_aw_create_bus[WIDTH-1:0];
else
vb_aw_bus[WIDTH-1:0] <= vb_aw_bus[WIDTH-1:0];
end
always @(posedge vb_entry_awclk or negedge cpurst_b)
begin
if(~cpurst_b)
vb_aw_mid[2:0] <= 3'b0;
else if(vb_aw_create_sel_x)
vb_aw_mid[2:0] <= vb_aw_create_mid[2:0];
else
vb_aw_mid[2:0] <= vb_aw_mid[2:0];
end
assign vb_w_create_sel = l2c0_wvalid_x |
l2c1_wvalid_x |
snb0_wvalid_x |
snb1_wvalid_x;
always @(posedge vb_ctrl_clk or negedge cpurst_b)
begin
if(~cpurst_b)
vb_w_vld <= 1'b0;
else if(vb_w_create_sel)
vb_w_vld <= 1'b1;
else if(vb_w_pop_sel_x)
vb_w_vld <= 1'b0;
end
assign vb_w_create_bus[DWIDTH-1:0] =
{DWIDTH{l2c0_wvalid_x}} & l2c0_vb_wbus[DWIDTH-1:0] |
{DWIDTH{l2c1_wvalid_x}} & l2c1_vb_wbus[DWIDTH-1:0] |
{DWIDTH{snb0_wvalid_x}} & snb0_vb_wbus[DWIDTH-1:0] |
{DWIDTH{snb1_wvalid_x}} & snb1_vb_wbus[DWIDTH-1:0];
always @(posedge vb_entry_wclk or negedge cpurst_b)
begin
if(~cpurst_b)
vb_w_bus[DWIDTH-1:0] <= {DWIDTH{1'b0}};
else if(vb_w_create_sel)
vb_w_bus[DWIDTH-1:0] <= vb_w_create_bus[DWIDTH-1:0];
else
vb_w_bus[DWIDTH-1:0] <= vb_w_bus[DWIDTH-1:0];
end
assign vb_aw_vld_x = vb_aw_vld;
assign vb_aw_en_x = vb_aw_en;
assign vb_w_vld_x = vb_w_vld;
assign vb_entryx_offset[1:0] = vb_aw_bus[ADDR_5:ADDR_4];
assign vb_entryx_awbus[WIDTH-1:0] = vb_aw_bus[WIDTH-1:0];
assign vb_entryx_wbus[DWIDTH-1:0] = vb_w_bus[DWIDTH-1:0];
assign vb_entryx_mid[2:0] = vb_aw_mid[2:0];
assign vb_snb_addr_hit_x = vb_aw_vld && (ebiuif_vb_index[7:0] == vb_aw_bus[ADDR_13:ADDR_6]);
//assign vb_snb1_addr_hit_x = vb_aw_vld && (snb1_vb_araddr[7:0] == vb_aw_bus[ADDR_13:ADDR_6]);
assign snb0_snpext_addr_hit_x = vb_aw_vld && (snb0_yy_snpext_index[7:0] == vb_aw_bus[ADDR_13:ADDR_6]);
assign snb1_snpext_addr_hit_x = vb_aw_vld && (snb1_yy_snpext_index[7:0] == vb_aw_bus[ADDR_13:ADDR_6]);
// &Instance("gated_clk_cell", "x_vb_entry_aw_gated_clk"); @139
gated_clk_cell x_vb_entry_aw_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (vb_entry_awclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (vb_aw_create_sel_x),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @140
// .external_en (1'b0), @141
// .global_en (1'b1), @142
// .module_en (ciu_icg_en ), @143
// .local_en (vb_aw_create_sel_x), @144
// .clk_out (vb_entry_awclk)); @145
// &Instance("gated_clk_cell", "x_vb_entry_w_gated_clk"); @148
gated_clk_cell x_vb_entry_w_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (vb_entry_wclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (vb_w_create_sel ),
.module_en (ciu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @149
// .external_en (1'b0), @150
// .global_en (1'b1), @151
// .module_en (ciu_icg_en ), @152
// .local_en (vb_w_create_sel), @153
// .clk_out (vb_entry_wclk)); @154
// &ModuleEnd; @156
endmodule |
module ct_idu_dep_reg_src2_entry(
alu0_reg_fwd_vld,
alu1_reg_fwd_vld,
cp0_idu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_xx_rf_pipe0_preg_lch_vld_dupx,
ctrl_xx_rf_pipe1_preg_lch_vld_dupx,
dp_xx_rf_pipe0_dst_preg_dupx,
dp_xx_rf_pipe1_dst_preg_dupx,
forever_cpuclk,
gateclk_entry_vld,
iu_idu_div_inst_vld,
iu_idu_div_preg_dupx,
iu_idu_ex2_pipe0_wb_preg_dupx,
iu_idu_ex2_pipe0_wb_preg_vld_dupx,
iu_idu_ex2_pipe1_mult_inst_vld_dupx,
iu_idu_ex2_pipe1_preg_dupx,
iu_idu_ex2_pipe1_wb_preg_dupx,
iu_idu_ex2_pipe1_wb_preg_vld_dupx,
lsu_idu_ag_pipe3_load_inst_vld,
lsu_idu_ag_pipe3_preg_dupx,
lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx,
lsu_idu_dc_pipe3_load_inst_vld_dupx,
lsu_idu_dc_pipe3_preg_dupx,
lsu_idu_wb_pipe3_wb_preg_dupx,
lsu_idu_wb_pipe3_wb_preg_vld_dupx,
mla_reg_fwd_vld,
pad_yy_icg_scan_en,
rtu_idu_flush_fe,
rtu_idu_flush_is,
vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx,
vfpu_idu_ex1_pipe6_preg_dupx,
vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx,
vfpu_idu_ex1_pipe7_preg_dupx,
x_create_data,
x_entry_mla,
x_gateclk_idx_write_en,
x_gateclk_write_en,
x_rdy_clr,
x_read_data,
x_write_en
);
// &Ports; @27
input alu0_reg_fwd_vld;
input alu1_reg_fwd_vld;
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_xx_rf_pipe0_preg_lch_vld_dupx;
input ctrl_xx_rf_pipe1_preg_lch_vld_dupx;
input [6 :0] dp_xx_rf_pipe0_dst_preg_dupx;
input [6 :0] dp_xx_rf_pipe1_dst_preg_dupx;
input forever_cpuclk;
input gateclk_entry_vld;
input iu_idu_div_inst_vld;
input [6 :0] iu_idu_div_preg_dupx;
input [6 :0] iu_idu_ex2_pipe0_wb_preg_dupx;
input iu_idu_ex2_pipe0_wb_preg_vld_dupx;
input iu_idu_ex2_pipe1_mult_inst_vld_dupx;
input [6 :0] iu_idu_ex2_pipe1_preg_dupx;
input [6 :0] iu_idu_ex2_pipe1_wb_preg_dupx;
input iu_idu_ex2_pipe1_wb_preg_vld_dupx;
input lsu_idu_ag_pipe3_load_inst_vld;
input [6 :0] lsu_idu_ag_pipe3_preg_dupx;
input lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx;
input lsu_idu_dc_pipe3_load_inst_vld_dupx;
input [6 :0] lsu_idu_dc_pipe3_preg_dupx;
input [6 :0] lsu_idu_wb_pipe3_wb_preg_dupx;
input lsu_idu_wb_pipe3_wb_preg_vld_dupx;
input mla_reg_fwd_vld;
input pad_yy_icg_scan_en;
input rtu_idu_flush_fe;
input rtu_idu_flush_is;
input vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe6_preg_dupx;
input vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe7_preg_dupx;
input [10:0] x_create_data;
input x_entry_mla;
input x_gateclk_idx_write_en;
input x_gateclk_write_en;
input x_rdy_clr;
input x_write_en;
output [12:0] x_read_data;
// &Regs; @28
reg lsu_match;
reg mla_rdy;
reg [6 :0] preg;
reg rdy;
reg wb;
// &Wires; @29
wire alu0_data_ready;
wire alu0_issue_data_ready;
wire alu0_reg_fwd_vld;
wire alu1_data_ready;
wire alu1_issue_data_ready;
wire alu1_reg_fwd_vld;
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_xx_rf_pipe0_preg_lch_vld_dupx;
wire ctrl_xx_rf_pipe1_preg_lch_vld_dupx;
wire data_ready;
wire dep_clk;
wire dep_clk_en;
wire div_data_ready;
wire [6 :0] dp_xx_rf_pipe0_dst_preg_dupx;
wire [6 :0] dp_xx_rf_pipe1_dst_preg_dupx;
wire forever_cpuclk;
wire gateclk_entry_vld;
wire iu_idu_div_inst_vld;
wire [6 :0] iu_idu_div_preg_dupx;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg_dupx;
wire iu_idu_ex2_pipe0_wb_preg_vld_dupx;
wire iu_idu_ex2_pipe1_mult_inst_vld_dupx;
wire [6 :0] iu_idu_ex2_pipe1_preg_dupx;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg_dupx;
wire iu_idu_ex2_pipe1_wb_preg_vld_dupx;
wire load_data_ready;
wire load_issue_data_ready;
wire lsu_idu_ag_pipe3_load_inst_vld;
wire [6 :0] lsu_idu_ag_pipe3_preg_dupx;
wire lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx;
wire lsu_idu_dc_pipe3_load_inst_vld_dupx;
wire [6 :0] lsu_idu_dc_pipe3_preg_dupx;
wire [6 :0] lsu_idu_wb_pipe3_wb_preg_dupx;
wire lsu_idu_wb_pipe3_wb_preg_vld_dupx;
wire lsu_match_update;
wire mla_data_ready;
wire mla_issue_data_ready;
wire mla_rdy_update;
wire mla_reg_fwd_vld;
wire mult_data_ready;
wire pad_yy_icg_scan_en;
wire pipe0_wb;
wire pipe1_wb;
wire pipe3_wb;
wire rdy_clear;
wire rdy_update;
wire rtu_idu_flush_fe;
wire rtu_idu_flush_is;
wire vfpu0_data_ready;
wire vfpu1_data_ready;
wire vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe6_preg_dupx;
wire vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe7_preg_dupx;
wire wake_up;
wire wb_update;
wire write_back;
wire write_clk;
wire write_clk_en;
wire [10:0] x_create_data;
wire x_create_lsu_match;
wire x_create_mla_rdy;
wire [6 :0] x_create_preg;
wire x_create_rdy;
wire x_create_wb;
wire x_entry_mla;
wire x_gateclk_idx_write_en;
wire x_gateclk_write_en;
wire x_rdy_clr;
wire [12:0] x_read_data;
wire x_read_lsu_match;
wire x_read_mla_rdy;
wire [6 :0] x_read_preg;
wire x_read_rdy;
wire x_read_rdy_for_bypass;
wire x_read_rdy_for_issue;
wire x_read_wb;
wire x_write_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign dep_clk_en = x_gateclk_write_en || gateclk_entry_vld && (!rdy || !wb);
// &Instance("gated_clk_cell", "x_dep_gated_clk"); @36
gated_clk_cell x_dep_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (dep_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (dep_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @37
// .external_en (1'b0), @38
// .global_en (cp0_yy_clk_en), @39
// .module_en (cp0_idu_icg_en), @40
// .local_en (dep_clk_en), @41
// .clk_out (dep_clk)); @42
assign write_clk_en = x_gateclk_idx_write_en;
// &Instance("gated_clk_cell", "x_write_gated_clk"); @45
gated_clk_cell x_write_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (write_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (write_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @46
// .external_en (1'b0), @47
// .global_en (cp0_yy_clk_en), @48
// .module_en (cp0_idu_icg_en), @49
// .local_en (write_clk_en), @50
// .clk_out (write_clk)); @51
//==========================================================
// Create and Read Bus
//==========================================================
assign x_create_lsu_match = x_create_data[10];
assign x_create_mla_rdy = x_create_data[9];
assign x_create_preg[6:0] = x_create_data[8:2];
assign x_create_wb = x_create_data[1];
assign x_create_rdy = x_create_data[0];
assign x_read_data[12] = x_read_lsu_match;
assign x_read_data[11] = x_read_rdy_for_bypass;
assign x_read_data[10] = x_read_rdy_for_issue;
assign x_read_data[9] = x_read_mla_rdy;
assign x_read_data[8:2] = x_read_preg[6:0];
assign x_read_data[1] = x_read_wb;
assign x_read_data[0] = x_read_rdy;
//==========================================================
// Ready Bit
//==========================================================
//ready bit shows the result of source is predicted to be ready:
//1 stands for the result may be forwarded
//-------------Update value of Ready Bit--------------------
//prepare data_ready signal
assign alu0_data_ready = ctrl_xx_rf_pipe0_preg_lch_vld_dupx
&& (dp_xx_rf_pipe0_dst_preg_dupx[6:0] == preg[6:0]);
//div data ready use wb to wake up / set ready
assign alu1_data_ready = ctrl_xx_rf_pipe1_preg_lch_vld_dupx
&& (dp_xx_rf_pipe1_dst_preg_dupx[6:0] == preg[6:0]);
assign mult_data_ready = iu_idu_ex2_pipe1_mult_inst_vld_dupx
&& (iu_idu_ex2_pipe1_preg_dupx[6:0] == preg[6:0]);
assign div_data_ready = iu_idu_div_inst_vld
&& (iu_idu_div_preg_dupx[6:0] == preg[6:0]);
assign load_data_ready = lsu_idu_dc_pipe3_load_inst_vld_dupx
&& (lsu_idu_dc_pipe3_preg_dupx[6:0] == preg[6:0]);
assign vfpu0_data_ready = vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx
&& (vfpu_idu_ex1_pipe6_preg_dupx[6:0] == preg[6:0]);
assign vfpu1_data_ready = vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx
&& (vfpu_idu_ex1_pipe7_preg_dupx[6:0] == preg[6:0]);
//bypass data ready for issue
assign alu0_issue_data_ready = alu0_reg_fwd_vld;
assign alu1_issue_data_ready = alu1_reg_fwd_vld;
assign load_issue_data_ready = lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx && lsu_match;
assign data_ready = alu0_data_ready
|| alu1_data_ready
|| mult_data_ready
|| div_data_ready
|| load_data_ready
|| vfpu0_data_ready
|| vfpu1_data_ready;
//prepare wake up signal
assign wake_up = wb;
//prepare clear signal
assign rdy_clear = x_rdy_clr;
//1.if ready is already be 1, just hold 1
//2.if producer are presumed to produce the result two cycles later,
// set ready to 1
//3.if producer wake up, set ready to 1
//4.clear ready to 0
assign rdy_update = (rdy || data_ready || wake_up) && !rdy_clear;
//ready read signal
assign x_read_rdy = rdy_update;
//the following signals are for Issue Queue bypass/issue logic
assign x_read_rdy_for_issue = rdy || mla_rdy
|| alu0_issue_data_ready
|| alu1_issue_data_ready
|| load_issue_data_ready
|| mla_issue_data_ready;
assign x_read_rdy_for_bypass = rdy;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rdy <= 1'b1;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
rdy <= 1'b1;
else if(x_write_en)
rdy <= x_create_rdy;
else
rdy <= rdy_update;
end
//==========================================================
// Multiply Accumulate Ready Bit
//==========================================================
//ready bit for mla inst, ready eariler than normal ready
//-------------Update value of Ready Bit--------------------
//prepare data_ready signal
assign mla_issue_data_ready = x_entry_mla
&& mla_reg_fwd_vld;
assign mla_data_ready = mla_issue_data_ready;
//1.if ready is already be 1, just hold 1
//2.if producer are presumed to produce the result two cycles later,
// set ready to 1
//3.if producer wake up, set ready to 1
//4.clear ready to 0
assign mla_rdy_update = (mla_rdy || mla_data_ready || wake_up) && !rdy_clear;
//ready read signal
assign x_read_mla_rdy = mla_rdy_update;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mla_rdy <= 1'b1;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
mla_rdy <= 1'b1;
else if(x_write_en)
mla_rdy <= x_create_mla_rdy;
else
mla_rdy <= mla_rdy_update;
end
//==========================================================
// Write Back Valid
//==========================================================
//write back valid shows whether the result is written back
//into PRF : 1 stands for the result is in PRF
//-------------Update value of Write Back Bit---------------
//prepare write back signal
assign pipe0_wb = iu_idu_ex2_pipe0_wb_preg_vld_dupx
&& (iu_idu_ex2_pipe0_wb_preg_dupx[6:0] == preg[6:0]);
assign pipe1_wb = iu_idu_ex2_pipe1_wb_preg_vld_dupx
&& (iu_idu_ex2_pipe1_wb_preg_dupx[6:0] == preg[6:0]);
assign pipe3_wb = lsu_idu_wb_pipe3_wb_preg_vld_dupx
&& (lsu_idu_wb_pipe3_wb_preg_dupx[6:0] == preg[6:0]);
assign write_back = wb
|| pipe0_wb
|| pipe1_wb
|| pipe3_wb;
//1.if wb_vld is already be 1, just hold 1
//2.if this result is writing back to PRF, set wb to 1
assign x_read_wb = wb_update;
assign wb_update = wb || write_back;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
wb <= 1'b1;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
wb <= 1'b1;
else if(x_write_en)
wb <= x_create_wb;
else
wb <= wb_update;
end
//==========================================================
// LSU reg Match for Bypass Ready
//==========================================================
assign lsu_match_update = lsu_idu_ag_pipe3_load_inst_vld
&& (lsu_idu_ag_pipe3_preg_dupx[6:0] == preg[6:0]);
assign x_read_lsu_match = lsu_match_update;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lsu_match <= 1'b0;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
lsu_match <= 1'b0;
else if(x_write_en)
lsu_match <= x_create_lsu_match;
else
lsu_match <= lsu_match_update;
end
//==========================================================
// Preg
//==========================================================
assign x_read_preg[6:0] = preg[6:0];
always @(posedge write_clk or negedge cpurst_b)
begin
if(!cpurst_b)
preg[6:0] <= 7'b0;
else if(x_write_en)
preg[6:0] <= x_create_preg[6:0];
else
preg[6:0] <= preg[6:0];
end
// &ModuleEnd; @239
endmodule |
module ct_idu_rf_fwd_vreg(
lsu_idu_da_pipe3_fwd_vreg,
lsu_idu_da_pipe3_fwd_vreg_data,
lsu_idu_da_pipe3_fwd_vreg_vld,
lsu_idu_wb_pipe3_fwd_vreg,
lsu_idu_wb_pipe3_fwd_vreg_vld,
lsu_idu_wb_pipe3_wb_vreg_data,
vfpu_idu_ex3_pipe6_fwd_vreg,
vfpu_idu_ex3_pipe6_fwd_vreg_data,
vfpu_idu_ex3_pipe6_fwd_vreg_vld,
vfpu_idu_ex3_pipe7_fwd_vreg,
vfpu_idu_ex3_pipe7_fwd_vreg_data,
vfpu_idu_ex3_pipe7_fwd_vreg_vld,
vfpu_idu_ex4_pipe6_fwd_vreg,
vfpu_idu_ex4_pipe6_fwd_vreg_data,
vfpu_idu_ex4_pipe6_fwd_vreg_vld,
vfpu_idu_ex4_pipe7_fwd_vreg,
vfpu_idu_ex4_pipe7_fwd_vreg_data,
vfpu_idu_ex4_pipe7_fwd_vreg_vld,
vfpu_idu_ex5_pipe6_fwd_vreg,
vfpu_idu_ex5_pipe6_fwd_vreg_vld,
vfpu_idu_ex5_pipe6_wb_vreg_data,
vfpu_idu_ex5_pipe7_fwd_vreg,
vfpu_idu_ex5_pipe7_fwd_vreg_vld,
vfpu_idu_ex5_pipe7_wb_vreg_data,
x_srcv_data,
x_srcv_no_fwd,
x_srcv_reg
);
// &Ports; @27
input [6 :0] lsu_idu_da_pipe3_fwd_vreg;
input [63:0] lsu_idu_da_pipe3_fwd_vreg_data;
input lsu_idu_da_pipe3_fwd_vreg_vld;
input [6 :0] lsu_idu_wb_pipe3_fwd_vreg;
input lsu_idu_wb_pipe3_fwd_vreg_vld;
input [63:0] lsu_idu_wb_pipe3_wb_vreg_data;
input [6 :0] vfpu_idu_ex3_pipe6_fwd_vreg;
input [63:0] vfpu_idu_ex3_pipe6_fwd_vreg_data;
input vfpu_idu_ex3_pipe6_fwd_vreg_vld;
input [6 :0] vfpu_idu_ex3_pipe7_fwd_vreg;
input [63:0] vfpu_idu_ex3_pipe7_fwd_vreg_data;
input vfpu_idu_ex3_pipe7_fwd_vreg_vld;
input [6 :0] vfpu_idu_ex4_pipe6_fwd_vreg;
input [63:0] vfpu_idu_ex4_pipe6_fwd_vreg_data;
input vfpu_idu_ex4_pipe6_fwd_vreg_vld;
input [6 :0] vfpu_idu_ex4_pipe7_fwd_vreg;
input [63:0] vfpu_idu_ex4_pipe7_fwd_vreg_data;
input vfpu_idu_ex4_pipe7_fwd_vreg_vld;
input [6 :0] vfpu_idu_ex5_pipe6_fwd_vreg;
input vfpu_idu_ex5_pipe6_fwd_vreg_vld;
input [63:0] vfpu_idu_ex5_pipe6_wb_vreg_data;
input [6 :0] vfpu_idu_ex5_pipe7_fwd_vreg;
input vfpu_idu_ex5_pipe7_fwd_vreg_vld;
input [63:0] vfpu_idu_ex5_pipe7_wb_vreg_data;
input [6 :0] x_srcv_reg;
output [63:0] x_srcv_data;
output x_srcv_no_fwd;
// &Regs; @28
reg [63:0] x_srcv_data;
// &Wires; @29
wire [7 :0] fwd_srcv_sel;
wire [6 :0] lsu_idu_da_pipe3_fwd_vreg;
wire [63:0] lsu_idu_da_pipe3_fwd_vreg_data;
wire lsu_idu_da_pipe3_fwd_vreg_vld;
wire [6 :0] lsu_idu_wb_pipe3_fwd_vreg;
wire lsu_idu_wb_pipe3_fwd_vreg_vld;
wire [63:0] lsu_idu_wb_pipe3_wb_vreg_data;
wire [6 :0] vfpu_idu_ex3_pipe6_fwd_vreg;
wire [63:0] vfpu_idu_ex3_pipe6_fwd_vreg_data;
wire vfpu_idu_ex3_pipe6_fwd_vreg_vld;
wire [6 :0] vfpu_idu_ex3_pipe7_fwd_vreg;
wire [63:0] vfpu_idu_ex3_pipe7_fwd_vreg_data;
wire vfpu_idu_ex3_pipe7_fwd_vreg_vld;
wire [6 :0] vfpu_idu_ex4_pipe6_fwd_vreg;
wire [63:0] vfpu_idu_ex4_pipe6_fwd_vreg_data;
wire vfpu_idu_ex4_pipe6_fwd_vreg_vld;
wire [6 :0] vfpu_idu_ex4_pipe7_fwd_vreg;
wire [63:0] vfpu_idu_ex4_pipe7_fwd_vreg_data;
wire vfpu_idu_ex4_pipe7_fwd_vreg_vld;
wire [6 :0] vfpu_idu_ex5_pipe6_fwd_vreg;
wire vfpu_idu_ex5_pipe6_fwd_vreg_vld;
wire [63:0] vfpu_idu_ex5_pipe6_wb_vreg_data;
wire [6 :0] vfpu_idu_ex5_pipe7_fwd_vreg;
wire vfpu_idu_ex5_pipe7_fwd_vreg_vld;
wire [63:0] vfpu_idu_ex5_pipe7_wb_vreg_data;
wire x_srcv_no_fwd;
wire [6 :0] x_srcv_reg;
//==========================================================
// Vreg Forward
//==========================================================
//0: pipe6 ex3, 1: pipe6 ex4, 2: pipe6 ex5, 3: pipe7 ex3,
//4: pipe7 ex4, 5: pipe7 ex5, 6: pipe3 da 7: pipe3 wb
assign fwd_srcv_sel[0] = vfpu_idu_ex3_pipe6_fwd_vreg_vld
&& (x_srcv_reg[6:0] == vfpu_idu_ex3_pipe6_fwd_vreg[6:0]);
assign fwd_srcv_sel[1] = vfpu_idu_ex4_pipe6_fwd_vreg_vld
&& (x_srcv_reg[6:0] == vfpu_idu_ex4_pipe6_fwd_vreg[6:0]);
assign fwd_srcv_sel[2] = vfpu_idu_ex5_pipe6_fwd_vreg_vld
&& (x_srcv_reg[6:0] == vfpu_idu_ex5_pipe6_fwd_vreg[6:0]);
assign fwd_srcv_sel[3] = vfpu_idu_ex3_pipe7_fwd_vreg_vld
&& (x_srcv_reg[6:0] == vfpu_idu_ex3_pipe7_fwd_vreg[6:0]);
assign fwd_srcv_sel[4] = vfpu_idu_ex4_pipe7_fwd_vreg_vld
&& (x_srcv_reg[6:0] == vfpu_idu_ex4_pipe7_fwd_vreg[6:0]);
assign fwd_srcv_sel[5] = vfpu_idu_ex5_pipe7_fwd_vreg_vld
&& (x_srcv_reg[6:0] == vfpu_idu_ex5_pipe7_fwd_vreg[6:0]);
assign fwd_srcv_sel[6] = lsu_idu_da_pipe3_fwd_vreg_vld
&& (x_srcv_reg[6:0] == lsu_idu_da_pipe3_fwd_vreg[6:0]);
assign fwd_srcv_sel[7] = lsu_idu_wb_pipe3_fwd_vreg_vld
&& (x_srcv_reg[6:0] == lsu_idu_wb_pipe3_fwd_vreg[6:0]);
assign x_srcv_no_fwd = !(|fwd_srcv_sel[7:0]);
// &CombBeg; @56
always @( vfpu_idu_ex4_pipe7_fwd_vreg_data[63:0]
or vfpu_idu_ex5_pipe7_wb_vreg_data[63:0]
or lsu_idu_da_pipe3_fwd_vreg_data[63:0]
or vfpu_idu_ex5_pipe6_wb_vreg_data[63:0]
or fwd_srcv_sel[7:0]
or lsu_idu_wb_pipe3_wb_vreg_data[63:0]
or vfpu_idu_ex3_pipe7_fwd_vreg_data[63:0]
or vfpu_idu_ex4_pipe6_fwd_vreg_data[63:0]
or vfpu_idu_ex3_pipe6_fwd_vreg_data[63:0])
begin
case (fwd_srcv_sel[7:0])
8'b00000001: x_srcv_data[63:0] = vfpu_idu_ex3_pipe6_fwd_vreg_data[63:0];
8'b00000010: x_srcv_data[63:0] = vfpu_idu_ex4_pipe6_fwd_vreg_data[63:0];
8'b00000100: x_srcv_data[63:0] = vfpu_idu_ex5_pipe6_wb_vreg_data[63:0];
8'b00001000: x_srcv_data[63:0] = vfpu_idu_ex3_pipe7_fwd_vreg_data[63:0];
8'b00010000: x_srcv_data[63:0] = vfpu_idu_ex4_pipe7_fwd_vreg_data[63:0];
8'b00100000: x_srcv_data[63:0] = vfpu_idu_ex5_pipe7_wb_vreg_data[63:0];
8'b01000000: x_srcv_data[63:0] = lsu_idu_da_pipe3_fwd_vreg_data[63:0];
8'b10000000: x_srcv_data[63:0] = lsu_idu_wb_pipe3_wb_vreg_data[63:0];
default : x_srcv_data[63:0] = {64{1'bx}};
endcase
// &CombEnd; @68
end
// &ModuleEnd; @70
endmodule |
module ct_idu_is_aiq_lch_rdy_2(
cpurst_b,
vld,
x_create_dp_en,
x_create_entry,
x_create_lch_rdy,
x_read_lch_rdy,
y_clk,
y_create0_dp_en,
y_create0_src_match,
y_create1_dp_en,
y_create1_src_match
);
// &Ports; @25
input cpurst_b;
input vld;
input x_create_dp_en;
input [1:0] x_create_entry;
input [1:0] x_create_lch_rdy;
input y_clk;
input y_create0_dp_en;
input [1:0] y_create0_src_match;
input y_create1_dp_en;
input [1:0] y_create1_src_match;
output [1:0] x_read_lch_rdy;
// &Regs; @26
reg [1:0] lch_rdy;
reg [1:0] x_read_lch_rdy;
// &Wires; @27
wire cpurst_b;
wire lch_rdy_create0_en;
wire lch_rdy_create1_en;
wire vld;
wire x_create_dp_en;
wire [1:0] x_create_entry;
wire [1:0] x_create_lch_rdy;
wire y_clk;
wire y_create0_dp_en;
wire [1:0] y_create0_src_match;
wire y_create1_dp_en;
wire [1:0] y_create1_src_match;
parameter WIDTH = 2;
//==========================================================
// Preg Register
//==========================================================
assign lch_rdy_create0_en = y_create0_dp_en && x_create_entry[0];
assign lch_rdy_create1_en = y_create1_dp_en && x_create_entry[1];
always @(posedge y_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lch_rdy[WIDTH-1:0] <= {WIDTH{1'b0}};
else if(x_create_dp_en)
lch_rdy[WIDTH-1:0] <= x_create_lch_rdy[WIDTH-1:0];
else if(vld && lch_rdy_create0_en)
lch_rdy[WIDTH-1:0] <= y_create0_src_match[WIDTH-1:0];
else if(vld && lch_rdy_create1_en)
lch_rdy[WIDTH-1:0] <= y_create1_src_match[WIDTH-1:0];
else
lch_rdy[WIDTH-1:0] <= lch_rdy[WIDTH-1:0];
end
//==========================================================
// Read Port
//==========================================================
// &CombBeg; @54
always @( y_create0_src_match[1:0]
or lch_rdy_create1_en
or lch_rdy[1:0]
or lch_rdy_create0_en
or y_create1_src_match[1:0])
begin
case({lch_rdy_create1_en,lch_rdy_create0_en})
2'b01 : x_read_lch_rdy[WIDTH-1:0] = y_create0_src_match[WIDTH-1:0];
2'b10 : x_read_lch_rdy[WIDTH-1:0] = y_create1_src_match[WIDTH-1:0];
default: x_read_lch_rdy[WIDTH-1:0] = lch_rdy[WIDTH-1:0];
endcase
// &CombEnd; @60
end
// &ModuleEnd; @62
endmodule |
module ct_idu_is_sdiq_entry(
cp0_idu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_xx_rf_pipe0_preg_lch_vld_dupx,
ctrl_xx_rf_pipe1_preg_lch_vld_dupx,
dp_sdiq_rf_rdy_clr,
dp_sdiq_rf_staddr1_vld,
dp_sdiq_rf_staddr_rdy_clr,
dp_sdiq_rf_stdata1_vld,
dp_xx_rf_pipe0_dst_preg_dupx,
dp_xx_rf_pipe1_dst_preg_dupx,
forever_cpuclk,
iu_idu_div_inst_vld,
iu_idu_div_preg_dupx,
iu_idu_ex2_pipe0_wb_preg_dupx,
iu_idu_ex2_pipe0_wb_preg_vld_dupx,
iu_idu_ex2_pipe1_mult_inst_vld_dupx,
iu_idu_ex2_pipe1_preg_dupx,
iu_idu_ex2_pipe1_wb_preg_dupx,
iu_idu_ex2_pipe1_wb_preg_vld_dupx,
lsu_idu_ag_pipe3_load_inst_vld,
lsu_idu_ag_pipe3_preg_dupx,
lsu_idu_ag_pipe3_vload_inst_vld,
lsu_idu_ag_pipe3_vreg_dupx,
lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx,
lsu_idu_dc_pipe3_load_inst_vld_dupx,
lsu_idu_dc_pipe3_preg_dupx,
lsu_idu_dc_pipe3_vload_fwd_inst_vld,
lsu_idu_dc_pipe3_vload_inst_vld_dupx,
lsu_idu_dc_pipe3_vreg_dupx,
lsu_idu_dc_staddr1_vld,
lsu_idu_dc_staddr_unalign,
lsu_idu_ex1_sdiq_pop_vld,
lsu_idu_wb_pipe3_wb_preg_dupx,
lsu_idu_wb_pipe3_wb_preg_vld_dupx,
lsu_idu_wb_pipe3_wb_vreg_dupx,
lsu_idu_wb_pipe3_wb_vreg_vld_dupx,
pad_yy_icg_scan_en,
rtu_yy_xx_flush,
vfpu_idu_ex1_pipe6_data_vld_dupx,
vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx,
vfpu_idu_ex1_pipe6_preg_dupx,
vfpu_idu_ex1_pipe6_vreg_dupx,
vfpu_idu_ex1_pipe7_data_vld_dupx,
vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx,
vfpu_idu_ex1_pipe7_preg_dupx,
vfpu_idu_ex1_pipe7_vreg_dupx,
vfpu_idu_ex2_pipe6_data_vld_dupx,
vfpu_idu_ex2_pipe6_vreg_dupx,
vfpu_idu_ex2_pipe7_data_vld_dupx,
vfpu_idu_ex2_pipe7_vreg_dupx,
vfpu_idu_ex3_pipe6_data_vld_dupx,
vfpu_idu_ex3_pipe6_vreg_dupx,
vfpu_idu_ex3_pipe7_data_vld_dupx,
vfpu_idu_ex3_pipe7_vreg_dupx,
vfpu_idu_ex5_pipe6_wb_vreg_dupx,
vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx,
vfpu_idu_ex5_pipe7_wb_vreg_dupx,
vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx,
x_agevec,
x_alu0_reg_fwd_vld,
x_alu1_reg_fwd_vld,
x_create_agevec,
x_create_data,
x_create_dp_en,
x_create_en,
x_create_gateclk_en,
x_ex1_frz_clr,
x_issue_en,
x_pop_cur_entry,
x_pop_other_entry,
x_rdy,
x_read_data,
x_rf_frz_clr,
x_src0_preg_expand,
x_srcf_freg_expand,
x_srcv_vreg_expand,
x_staddr_rdy_set,
x_staddr_stq_create,
x_vld,
x_vld_with_frz
);
// &Ports; @28
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_xx_rf_pipe0_preg_lch_vld_dupx;
input ctrl_xx_rf_pipe1_preg_lch_vld_dupx;
input [1 :0] dp_sdiq_rf_rdy_clr;
input dp_sdiq_rf_staddr1_vld;
input dp_sdiq_rf_staddr_rdy_clr;
input dp_sdiq_rf_stdata1_vld;
input [6 :0] dp_xx_rf_pipe0_dst_preg_dupx;
input [6 :0] dp_xx_rf_pipe1_dst_preg_dupx;
input forever_cpuclk;
input iu_idu_div_inst_vld;
input [6 :0] iu_idu_div_preg_dupx;
input [6 :0] iu_idu_ex2_pipe0_wb_preg_dupx;
input iu_idu_ex2_pipe0_wb_preg_vld_dupx;
input iu_idu_ex2_pipe1_mult_inst_vld_dupx;
input [6 :0] iu_idu_ex2_pipe1_preg_dupx;
input [6 :0] iu_idu_ex2_pipe1_wb_preg_dupx;
input iu_idu_ex2_pipe1_wb_preg_vld_dupx;
input lsu_idu_ag_pipe3_load_inst_vld;
input [6 :0] lsu_idu_ag_pipe3_preg_dupx;
input lsu_idu_ag_pipe3_vload_inst_vld;
input [6 :0] lsu_idu_ag_pipe3_vreg_dupx;
input lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx;
input lsu_idu_dc_pipe3_load_inst_vld_dupx;
input [6 :0] lsu_idu_dc_pipe3_preg_dupx;
input lsu_idu_dc_pipe3_vload_fwd_inst_vld;
input lsu_idu_dc_pipe3_vload_inst_vld_dupx;
input [6 :0] lsu_idu_dc_pipe3_vreg_dupx;
input lsu_idu_dc_staddr1_vld;
input lsu_idu_dc_staddr_unalign;
input lsu_idu_ex1_sdiq_pop_vld;
input [6 :0] lsu_idu_wb_pipe3_wb_preg_dupx;
input lsu_idu_wb_pipe3_wb_preg_vld_dupx;
input [6 :0] lsu_idu_wb_pipe3_wb_vreg_dupx;
input lsu_idu_wb_pipe3_wb_vreg_vld_dupx;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
input vfpu_idu_ex1_pipe6_data_vld_dupx;
input vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe6_preg_dupx;
input [6 :0] vfpu_idu_ex1_pipe6_vreg_dupx;
input vfpu_idu_ex1_pipe7_data_vld_dupx;
input vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe7_preg_dupx;
input [6 :0] vfpu_idu_ex1_pipe7_vreg_dupx;
input vfpu_idu_ex2_pipe6_data_vld_dupx;
input [6 :0] vfpu_idu_ex2_pipe6_vreg_dupx;
input vfpu_idu_ex2_pipe7_data_vld_dupx;
input [6 :0] vfpu_idu_ex2_pipe7_vreg_dupx;
input vfpu_idu_ex3_pipe6_data_vld_dupx;
input [6 :0] vfpu_idu_ex3_pipe6_vreg_dupx;
input vfpu_idu_ex3_pipe7_data_vld_dupx;
input [6 :0] vfpu_idu_ex3_pipe7_vreg_dupx;
input [6 :0] vfpu_idu_ex5_pipe6_wb_vreg_dupx;
input vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx;
input [6 :0] vfpu_idu_ex5_pipe7_wb_vreg_dupx;
input vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx;
input x_alu0_reg_fwd_vld;
input x_alu1_reg_fwd_vld;
input [10:0] x_create_agevec;
input [26:0] x_create_data;
input x_create_dp_en;
input x_create_en;
input x_create_gateclk_en;
input x_ex1_frz_clr;
input x_issue_en;
input x_pop_cur_entry;
input [10:0] x_pop_other_entry;
input x_rf_frz_clr;
input x_staddr_rdy_set;
input x_staddr_stq_create;
output [10:0] x_agevec;
output x_rdy;
output [26:0] x_read_data;
output [95:0] x_src0_preg_expand;
output [63:0] x_srcf_freg_expand;
output [63:0] x_srcv_vreg_expand;
output x_vld;
output x_vld_with_frz;
// &Regs; @29
reg [10:0] agevec;
reg frz;
reg load;
reg src0_vld;
reg srcv0_vld;
reg staddr0_in_stq;
reg staddr0_rdy;
reg staddr1_in_stq;
reg staddr1_rdy;
reg stdata1_vld;
reg unalign;
reg vld;
// &Wires; @30
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [9 :0] create_src0_data;
wire create_src0_gateclk_en;
wire [9 :0] create_srcv0_data;
wire create_srcv0_gateclk_en;
wire ctrl_xx_rf_pipe0_preg_lch_vld_dupx;
wire ctrl_xx_rf_pipe1_preg_lch_vld_dupx;
wire [1 :0] dp_sdiq_rf_rdy_clr;
wire dp_sdiq_rf_staddr1_vld;
wire dp_sdiq_rf_staddr_rdy_clr;
wire dp_sdiq_rf_stdata1_vld;
wire [6 :0] dp_xx_rf_pipe0_dst_preg_dupx;
wire [6 :0] dp_xx_rf_pipe1_dst_preg_dupx;
wire entry_clk;
wire entry_clk_en;
wire forever_cpuclk;
wire gateclk_entry_vld;
wire iu_idu_div_inst_vld;
wire [6 :0] iu_idu_div_preg_dupx;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg_dupx;
wire iu_idu_ex2_pipe0_wb_preg_vld_dupx;
wire iu_idu_ex2_pipe1_mult_inst_vld_dupx;
wire [6 :0] iu_idu_ex2_pipe1_preg_dupx;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg_dupx;
wire iu_idu_ex2_pipe1_wb_preg_vld_dupx;
wire lsu_idu_ag_pipe3_load_inst_vld;
wire [6 :0] lsu_idu_ag_pipe3_preg_dupx;
wire lsu_idu_ag_pipe3_vload_inst_vld;
wire [6 :0] lsu_idu_ag_pipe3_vreg_dupx;
wire lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx;
wire lsu_idu_dc_pipe3_load_inst_vld_dupx;
wire [6 :0] lsu_idu_dc_pipe3_preg_dupx;
wire lsu_idu_dc_pipe3_vload_fwd_inst_vld;
wire lsu_idu_dc_pipe3_vload_inst_vld_dupx;
wire [6 :0] lsu_idu_dc_pipe3_vreg_dupx;
wire lsu_idu_dc_staddr1_vld;
wire lsu_idu_dc_staddr_unalign;
wire lsu_idu_ex1_sdiq_pop_vld;
wire [6 :0] lsu_idu_wb_pipe3_wb_preg_dupx;
wire lsu_idu_wb_pipe3_wb_preg_vld_dupx;
wire [6 :0] lsu_idu_wb_pipe3_wb_vreg_dupx;
wire lsu_idu_wb_pipe3_wb_vreg_vld_dupx;
wire pad_yy_icg_scan_en;
wire [6 :0] read_data_src0_preg;
wire [95:0] read_data_src0_preg_expand;
wire [5 :0] read_data_srcv0_vreg;
wire [63:0] read_data_srcv0_vreg_expand;
wire [11:0] read_src0_data;
wire [11:0] read_srcv0_data;
wire rtu_yy_xx_flush;
wire src0_rdy_clr;
wire src0_rdy_for_issue;
wire srcv0_rdy_clr;
wire srcv0_rdy_for_issue;
wire staddr0_rdy_clr;
wire staddr0_rdy_set;
wire staddr1_rdy_clr;
wire staddr1_rdy_set;
wire vfpu_idu_ex1_pipe6_data_vld_dupx;
wire vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe6_preg_dupx;
wire [6 :0] vfpu_idu_ex1_pipe6_vreg_dupx;
wire vfpu_idu_ex1_pipe7_data_vld_dupx;
wire vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe7_preg_dupx;
wire [6 :0] vfpu_idu_ex1_pipe7_vreg_dupx;
wire vfpu_idu_ex2_pipe6_data_vld_dupx;
wire [6 :0] vfpu_idu_ex2_pipe6_vreg_dupx;
wire vfpu_idu_ex2_pipe7_data_vld_dupx;
wire [6 :0] vfpu_idu_ex2_pipe7_vreg_dupx;
wire vfpu_idu_ex3_pipe6_data_vld_dupx;
wire [6 :0] vfpu_idu_ex3_pipe6_vreg_dupx;
wire vfpu_idu_ex3_pipe7_data_vld_dupx;
wire [6 :0] vfpu_idu_ex3_pipe7_vreg_dupx;
wire [6 :0] vfpu_idu_ex5_pipe6_wb_vreg_dupx;
wire vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx;
wire [6 :0] vfpu_idu_ex5_pipe7_wb_vreg_dupx;
wire vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx;
wire [10:0] x_agevec;
wire x_alu0_reg_fwd_vld;
wire x_alu1_reg_fwd_vld;
wire [10:0] x_create_agevec;
wire [26:0] x_create_data;
wire x_create_dp_en;
wire x_create_en;
wire x_create_gateclk_en;
wire x_ex1_frz_clr;
wire x_issue_en;
wire x_pop_cur_entry;
wire [10:0] x_pop_other_entry;
wire x_rdy;
wire [26:0] x_read_data;
wire x_rf_frz_clr;
wire [95:0] x_src0_preg_expand;
wire [63:0] x_srcf_freg_expand;
wire [63:0] x_srcv_vreg_expand;
wire x_staddr_rdy_set;
wire x_staddr_stq_create;
wire x_vld;
wire x_vld_with_frz;
//==========================================================
// Parameters
//==========================================================
//----------------------------------------------------------
// SDIQ Parameters
//----------------------------------------------------------
parameter SDIQ_WIDTH = 27;
parameter SDIQ_LOAD = 26;
parameter SDIQ_STADDR1_IN_STQ = 25;
parameter SDIQ_STADDR0_IN_STQ = 24;
parameter SDIQ_STDATA1_VLD = 23;
parameter SDIQ_UNALIGN = 22;
parameter SDIQ_SRCV0_LSU_MATCH = 21;
parameter SDIQ_SRCV0_DATA = 20;
parameter SDIQ_SRCV0_VREG = 20;
parameter SDIQ_SRCV0_WB = 13;
parameter SDIQ_SRCV0_RDY = 12;
parameter SDIQ_SRC0_LSU_MATCH = 11;
parameter SDIQ_SRC0_DATA = 10;
parameter SDIQ_SRC0_PREG = 10;
parameter SDIQ_SRC0_WB = 3;
parameter SDIQ_SRC0_RDY = 2;
parameter SDIQ_SRCV0_VLD = 1;
parameter SDIQ_SRC0_VLD = 0;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign entry_clk_en = x_create_gateclk_en || vld;
// &Instance("gated_clk_cell", "x_entry_gated_clk"); @63
gated_clk_cell x_entry_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (entry_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @64
// .external_en (1'b0), @65
// .global_en (cp0_yy_clk_en), @66
// .module_en (cp0_idu_icg_en), @67
// .local_en (entry_clk_en), @68
// .clk_out (entry_clk)); @69
//if entry is not valid, shut down dep info clock
assign gateclk_entry_vld = vld;
//==========================================================
// Create and Read Bus
//==========================================================
//force create and read bus width
// &Force("bus","x_create_data",SDIQ_WIDTH-1,0); @78
// &Force("bus","x_read_data",SDIQ_WIDTH-1,0); @79
// &Force("output","x_read_data"); @80
//==========================================================
// Entry Valid
//==========================================================
assign x_vld = vld;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vld <= 1'b0;
else if(rtu_yy_xx_flush)
vld <= 1'b0;
else if(x_create_en)
vld <= 1'b1;
else if(lsu_idu_ex1_sdiq_pop_vld && x_pop_cur_entry)
vld <= 1'b0;
else
vld <= vld;
end
//==========================================================
// Freeze
//==========================================================
assign x_vld_with_frz = vld && !frz;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
frz <= 1'b0;
else if(x_create_en)
//SDIQ cannot bypass, create in frz is always 0
frz <= 1'b0;
else if(x_rf_frz_clr || x_ex1_frz_clr)
frz <= 1'b0;
else if(x_issue_en)
frz <= 1'b1;
else
frz <= frz;
end
//==========================================================
// Age Vector
//==========================================================
assign x_agevec[10:0] = agevec[10:0];
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
agevec[10:0] <= 11'b0;
else if(x_create_en)
agevec[10:0] <= x_create_agevec[10:0];
else if(lsu_idu_ex1_sdiq_pop_vld)
agevec[10:0] <= agevec[10:0] & ~x_pop_other_entry[10:0];
else
agevec[10:0] <= agevec[10:0];
end
//==========================================================
// Instruction Information
//==========================================================
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
src0_vld <= 1'b0;
srcv0_vld <= 1'b0;
load <= 1'b0;
end
else if(x_create_dp_en) begin
src0_vld <= x_create_data[SDIQ_SRC0_VLD];
srcv0_vld <= x_create_data[SDIQ_SRCV0_VLD];
load <= x_create_data[SDIQ_LOAD];
end
else begin
src0_vld <= src0_vld;
srcv0_vld <= srcv0_vld;
load <= load;
end
end
//rename for read output
assign x_read_data[SDIQ_SRC0_VLD] = src0_vld;
assign x_read_data[SDIQ_SRCV0_VLD] = srcv0_vld;
assign x_read_data[SDIQ_LOAD] = load;
//==========================================================
// Store Address Instruction Ready
//==========================================================
//----------------------------------------------------------
// Staddr 0 Ready
//----------------------------------------------------------
assign staddr0_rdy_clr = x_rf_frz_clr
&& dp_sdiq_rf_staddr_rdy_clr
&& !dp_sdiq_rf_stdata1_vld;
assign staddr0_rdy_set = staddr0_in_stq
|| x_staddr_rdy_set
&& !dp_sdiq_rf_staddr1_vld;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
staddr0_rdy <= 1'b0;
else if(x_create_en)
staddr0_rdy <= 1'b0;
else if(staddr0_rdy_clr)
staddr0_rdy <= 1'b0;
else if(staddr0_rdy_set)
staddr0_rdy <= 1'b1;
else
staddr0_rdy <= staddr0_rdy;
end
//----------------------------------------------------------
// Staddr 1 Ready
//----------------------------------------------------------
assign staddr1_rdy_clr = x_rf_frz_clr
&& dp_sdiq_rf_staddr_rdy_clr
&& dp_sdiq_rf_stdata1_vld;
assign staddr1_rdy_set = staddr1_in_stq
|| x_staddr_rdy_set
&& dp_sdiq_rf_staddr1_vld;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
staddr1_rdy <= 1'b0;
else if(x_create_en)
staddr1_rdy <= 1'b0;
else if(staddr1_rdy_clr)
staddr1_rdy <= 1'b0;
else if(staddr1_rdy_set)
staddr1_rdy <= 1'b1;
else
staddr1_rdy <= staddr1_rdy;
end
//----------------------------------------------------------
// Staddr 0 in Store Queue
//----------------------------------------------------------
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
staddr0_in_stq <= 1'b0;
unalign <= 1'b0;
end
else if(x_create_en) begin
staddr0_in_stq <= 1'b0;
unalign <= 1'b0;
end
else if(x_staddr_stq_create && !lsu_idu_dc_staddr1_vld) begin
staddr0_in_stq <= 1'b1;
unalign <= lsu_idu_dc_staddr_unalign;
end
else begin
staddr0_in_stq <= staddr0_in_stq;
unalign <= unalign;
end
end
assign x_read_data[SDIQ_UNALIGN] = unalign || x_staddr_stq_create
&& !lsu_idu_dc_staddr1_vld
&& lsu_idu_dc_staddr_unalign;
assign x_read_data[SDIQ_STADDR0_IN_STQ] = staddr0_in_stq
|| x_staddr_stq_create
&& !lsu_idu_dc_staddr1_vld;
//----------------------------------------------------------
// Staddr 1 in Store Queue
//----------------------------------------------------------
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
staddr1_in_stq <= 1'b0;
else if(x_create_en)
staddr1_in_stq <= 1'b0;
else if(x_staddr_stq_create && lsu_idu_dc_staddr1_vld)
staddr1_in_stq <= 1'b1;
else
staddr1_in_stq <= staddr1_in_stq;
end
assign x_read_data[SDIQ_STADDR1_IN_STQ] = staddr1_in_stq
|| x_staddr_stq_create
&& lsu_idu_dc_staddr1_vld;
//==========================================================
// Store Data 1 Valid
//==========================================================
//indicate the current entry is unalign stdata inst 1
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
stdata1_vld <= 1'b0;
else if(x_create_en)
stdata1_vld <= 1'b0;
else if(x_ex1_frz_clr)
stdata1_vld <= 1'b1;
else
stdata1_vld <= stdata1_vld;
end
assign x_read_data[SDIQ_STDATA1_VLD] = stdata1_vld;
//==========================================================
// Source Dependency Information
//==========================================================
assign src0_rdy_clr = x_rf_frz_clr && dp_sdiq_rf_rdy_clr[0];
assign srcv0_rdy_clr = x_rf_frz_clr && dp_sdiq_rf_rdy_clr[1];
//SDIQ is flush by backend rtu_yy_xx_flush, not frontend or IS
//flush
//------------------------source 0--------------------------
assign create_src0_gateclk_en = x_create_gateclk_en && x_create_data[SDIQ_SRC0_VLD];
assign create_src0_data[9] = x_create_data[SDIQ_SRC0_LSU_MATCH];
assign create_src0_data[8:0] = x_create_data[SDIQ_SRC0_DATA:SDIQ_SRC0_DATA-8];
// &Instance("ct_idu_dep_reg_entry", "x_ct_idu_is_sdiq_src0_entry"); @289
ct_idu_dep_reg_entry x_ct_idu_is_sdiq_src0_entry (
.alu0_reg_fwd_vld (x_alu0_reg_fwd_vld ),
.alu1_reg_fwd_vld (x_alu1_reg_fwd_vld ),
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ctrl_xx_rf_pipe0_preg_lch_vld_dupx (ctrl_xx_rf_pipe0_preg_lch_vld_dupx ),
.ctrl_xx_rf_pipe1_preg_lch_vld_dupx (ctrl_xx_rf_pipe1_preg_lch_vld_dupx ),
.dp_xx_rf_pipe0_dst_preg_dupx (dp_xx_rf_pipe0_dst_preg_dupx ),
.dp_xx_rf_pipe1_dst_preg_dupx (dp_xx_rf_pipe1_dst_preg_dupx ),
.forever_cpuclk (forever_cpuclk ),
.gateclk_entry_vld (gateclk_entry_vld ),
.iu_idu_div_inst_vld (iu_idu_div_inst_vld ),
.iu_idu_div_preg_dupx (iu_idu_div_preg_dupx ),
.iu_idu_ex2_pipe0_wb_preg_dupx (iu_idu_ex2_pipe0_wb_preg_dupx ),
.iu_idu_ex2_pipe0_wb_preg_vld_dupx (iu_idu_ex2_pipe0_wb_preg_vld_dupx ),
.iu_idu_ex2_pipe1_mult_inst_vld_dupx (iu_idu_ex2_pipe1_mult_inst_vld_dupx ),
.iu_idu_ex2_pipe1_preg_dupx (iu_idu_ex2_pipe1_preg_dupx ),
.iu_idu_ex2_pipe1_wb_preg_dupx (iu_idu_ex2_pipe1_wb_preg_dupx ),
.iu_idu_ex2_pipe1_wb_preg_vld_dupx (iu_idu_ex2_pipe1_wb_preg_vld_dupx ),
.lsu_idu_ag_pipe3_load_inst_vld (lsu_idu_ag_pipe3_load_inst_vld ),
.lsu_idu_ag_pipe3_preg_dupx (lsu_idu_ag_pipe3_preg_dupx ),
.lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx (lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx),
.lsu_idu_dc_pipe3_load_inst_vld_dupx (lsu_idu_dc_pipe3_load_inst_vld_dupx ),
.lsu_idu_dc_pipe3_preg_dupx (lsu_idu_dc_pipe3_preg_dupx ),
.lsu_idu_wb_pipe3_wb_preg_dupx (lsu_idu_wb_pipe3_wb_preg_dupx ),
.lsu_idu_wb_pipe3_wb_preg_vld_dupx (lsu_idu_wb_pipe3_wb_preg_vld_dupx ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_idu_flush_fe (rtu_yy_xx_flush ),
.rtu_idu_flush_is (rtu_yy_xx_flush ),
.vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx (vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx ),
.vfpu_idu_ex1_pipe6_preg_dupx (vfpu_idu_ex1_pipe6_preg_dupx ),
.vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx (vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx ),
.vfpu_idu_ex1_pipe7_preg_dupx (vfpu_idu_ex1_pipe7_preg_dupx ),
.x_create_data (create_src0_data[9:0] ),
.x_gateclk_idx_write_en (create_src0_gateclk_en ),
.x_gateclk_write_en (x_create_gateclk_en ),
.x_rdy_clr (src0_rdy_clr ),
.x_read_data (read_src0_data[11:0] ),
.x_write_en (x_create_dp_en )
);
// &Connect(.gateclk_entry_vld (gateclk_entry_vld), @290
// .rtu_idu_flush_fe (rtu_yy_xx_flush), @291
// .rtu_idu_flush_is (rtu_yy_xx_flush), @292
// .alu0_reg_fwd_vld (x_alu0_reg_fwd_vld), @293
// .alu1_reg_fwd_vld (x_alu1_reg_fwd_vld), @294
// .x_write_en (x_create_dp_en), @295
// .x_gateclk_write_en (x_create_gateclk_en), @296
// .x_gateclk_idx_write_en (create_src0_gateclk_en), @297
// .x_create_data (create_src0_data[9:0]), @298
// .x_read_data (read_src0_data[11:0]), @299
// .x_rdy_clr (src0_rdy_clr) @300
// ); @301
assign x_read_data[SDIQ_SRC0_WB] = read_src0_data[1];
assign x_read_data[SDIQ_SRC0_PREG:SDIQ_SRC0_PREG-6] = read_src0_data[8:2];
assign src0_rdy_for_issue = read_src0_data[9];
assign x_read_data[SDIQ_SRC0_RDY] = 1'b0;
assign x_read_data[SDIQ_SRC0_LSU_MATCH] = 1'b0;
//-----------------------source v 0-------------------------
assign create_srcv0_gateclk_en = x_create_gateclk_en && x_create_data[SDIQ_SRCV0_VLD];
assign create_srcv0_data[9] = x_create_data[SDIQ_SRCV0_LSU_MATCH];
assign create_srcv0_data[8:0] = x_create_data[SDIQ_SRCV0_DATA:SDIQ_SRCV0_DATA-8];
// &Instance("ct_idu_dep_vreg_entry", "x_ct_idu_is_sdiq_srcv0_entry"); @312
ct_idu_dep_vreg_entry x_ct_idu_is_sdiq_srcv0_entry (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.gateclk_entry_vld (gateclk_entry_vld ),
.lsu_idu_ag_pipe3_vload_inst_vld (lsu_idu_ag_pipe3_vload_inst_vld ),
.lsu_idu_ag_pipe3_vreg_dupx (lsu_idu_ag_pipe3_vreg_dupx ),
.lsu_idu_dc_pipe3_vload_fwd_inst_vld (lsu_idu_dc_pipe3_vload_fwd_inst_vld ),
.lsu_idu_dc_pipe3_vload_inst_vld_dupx (lsu_idu_dc_pipe3_vload_inst_vld_dupx),
.lsu_idu_dc_pipe3_vreg_dupx (lsu_idu_dc_pipe3_vreg_dupx ),
.lsu_idu_wb_pipe3_wb_vreg_dupx (lsu_idu_wb_pipe3_wb_vreg_dupx ),
.lsu_idu_wb_pipe3_wb_vreg_vld_dupx (lsu_idu_wb_pipe3_wb_vreg_vld_dupx ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_idu_flush_fe (rtu_yy_xx_flush ),
.rtu_idu_flush_is (rtu_yy_xx_flush ),
.vfpu_idu_ex1_pipe6_data_vld_dupx (vfpu_idu_ex1_pipe6_data_vld_dupx ),
.vfpu_idu_ex1_pipe6_vreg_dupx (vfpu_idu_ex1_pipe6_vreg_dupx ),
.vfpu_idu_ex1_pipe7_data_vld_dupx (vfpu_idu_ex1_pipe7_data_vld_dupx ),
.vfpu_idu_ex1_pipe7_vreg_dupx (vfpu_idu_ex1_pipe7_vreg_dupx ),
.vfpu_idu_ex2_pipe6_data_vld_dupx (vfpu_idu_ex2_pipe6_data_vld_dupx ),
.vfpu_idu_ex2_pipe6_vreg_dupx (vfpu_idu_ex2_pipe6_vreg_dupx ),
.vfpu_idu_ex2_pipe7_data_vld_dupx (vfpu_idu_ex2_pipe7_data_vld_dupx ),
.vfpu_idu_ex2_pipe7_vreg_dupx (vfpu_idu_ex2_pipe7_vreg_dupx ),
.vfpu_idu_ex3_pipe6_data_vld_dupx (vfpu_idu_ex3_pipe6_data_vld_dupx ),
.vfpu_idu_ex3_pipe6_vreg_dupx (vfpu_idu_ex3_pipe6_vreg_dupx ),
.vfpu_idu_ex3_pipe7_data_vld_dupx (vfpu_idu_ex3_pipe7_data_vld_dupx ),
.vfpu_idu_ex3_pipe7_vreg_dupx (vfpu_idu_ex3_pipe7_vreg_dupx ),
.vfpu_idu_ex5_pipe6_wb_vreg_dupx (vfpu_idu_ex5_pipe6_wb_vreg_dupx ),
.vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx (vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx ),
.vfpu_idu_ex5_pipe7_wb_vreg_dupx (vfpu_idu_ex5_pipe7_wb_vreg_dupx ),
.vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx (vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx ),
.x_create_data (create_srcv0_data[9:0] ),
.x_gateclk_idx_write_en (create_srcv0_gateclk_en ),
.x_gateclk_write_en (x_create_gateclk_en ),
.x_rdy_clr (srcv0_rdy_clr ),
.x_read_data (read_srcv0_data[11:0] ),
.x_write_en (x_create_dp_en )
);
// &Connect(.gateclk_entry_vld (gateclk_entry_vld), @313
// .rtu_idu_flush_fe (rtu_yy_xx_flush), @314
// .rtu_idu_flush_is (rtu_yy_xx_flush), @315
// .x_write_en (x_create_dp_en), @316
// .x_gateclk_write_en (x_create_gateclk_en), @317
// .x_gateclk_idx_write_en (create_srcv0_gateclk_en), @318
// .x_create_data (create_srcv0_data[9:0]), @319
// .x_read_data (read_srcv0_data[11:0]), @320
// .x_rdy_clr (srcv0_rdy_clr) @321
// ); @322
assign x_read_data[SDIQ_SRCV0_WB] = read_srcv0_data[1];
assign x_read_data[SDIQ_SRCV0_VREG:SDIQ_SRCV0_VREG-6] = read_srcv0_data[8:2];
assign srcv0_rdy_for_issue = read_srcv0_data[9];
assign x_read_data[SDIQ_SRCV0_RDY] = 1'b0;
assign x_read_data[SDIQ_SRCV0_LSU_MATCH] = 1'b0;
//==========================================================
// Dealloc mask signal for src0/srcv0
//==========================================================
assign read_data_src0_preg[6:0] = x_read_data[SDIQ_SRC0_PREG:SDIQ_SRC0_PREG-6];
assign read_data_srcv0_vreg[5:0] = x_read_data[SDIQ_SRCV0_VREG-1:SDIQ_SRCV0_VREG-6];
// &ConnRule(s/^x_num/read_data_src0_preg/); @335
// &Instance("ct_rtu_expand_96","x_ct_rtu_expand_96_read_data_src0_preg"); @336
ct_rtu_expand_96 x_ct_rtu_expand_96_read_data_src0_preg (
.x_num (read_data_src0_preg ),
.x_num_expand (read_data_src0_preg_expand)
);
// &ConnRule(s/^x_num/read_data_srcv0_vreg/); @337
// &Instance("ct_rtu_expand_64","x_ct_rtu_expand_64_read_data_srcv0_vreg"); @338
ct_rtu_expand_64 x_ct_rtu_expand_64_read_data_srcv0_vreg (
.x_num (read_data_srcv0_vreg ),
.x_num_expand (read_data_srcv0_vreg_expand)
);
assign x_src0_preg_expand[95:0] = {96{vld && src0_vld}}
& read_data_src0_preg_expand[95:0];
assign x_srcv_vreg_expand[63:0] =
{64{vld && srcv0_vld && x_read_data[SDIQ_SRCV0_VREG]}} & read_data_srcv0_vreg_expand[63:0];
assign x_srcf_freg_expand[63:0] =
{64{vld && srcv0_vld && !x_read_data[SDIQ_SRCV0_VREG]}} & read_data_srcv0_vreg_expand[63:0];
//==========================================================
// Entry Ready Signal
//==========================================================
assign x_rdy = vld
&& !frz
&& src0_rdy_for_issue
&& srcv0_rdy_for_issue
&& (load
|| !stdata1_vld && staddr0_rdy
|| stdata1_vld && staddr1_rdy);
// &ModuleEnd; @358
endmodule |
module ct_idu_id_decd_special(
cp0_idu_cskyee,
cp0_idu_frm,
cp0_idu_fs,
x_fence,
x_fence_type,
x_inst,
x_split,
x_split_long_type,
x_split_potnt,
x_split_short,
x_split_short_potnt,
x_split_short_type
);
// &Ports; @26
input cp0_idu_cskyee;
input [2 :0] cp0_idu_frm;
input [1 :0] cp0_idu_fs;
input [31:0] x_inst;
output x_fence;
output [2 :0] x_fence_type;
output x_split;
output [9 :0] x_split_long_type;
output [2 :0] x_split_potnt;
output x_split_short;
output [2 :0] x_split_short_potnt;
output [6 :0] x_split_short_type;
// &Regs; @27
// &Wires; @28
wire cp0_idu_cskyee;
wire [2 :0] cp0_idu_frm;
wire [1 :0] cp0_idu_fs;
wire hfence_inst;
wire x_fence;
wire [2 :0] x_fence_type;
wire [31:0] x_inst;
wire x_split;
wire [9 :0] x_split_long_type;
wire [2 :0] x_split_potnt;
wire x_split_short;
wire [2 :0] x_split_short_potnt;
wire [6 :0] x_split_short_type;
// &Force("bus","x_inst",31,0); @31
//==========================================================
// Decode Split Short Type
//==========================================================
// &Force("output","x_split_short_type"); @35
//----------------------------------------------------------
// Instruction Split Short
//----------------------------------------------------------
assign x_split_short = |x_split_short_type[6:0];
//----------------------------------------------------------
// jal with dest
//----------------------------------------------------------
assign x_split_short_type[0] = ({x_inst[15:12], x_inst[6:0]} == 11'b1001_0000010)
&& (x_inst[11:7] != 5'd0) //c.jalr
|| (x_inst[6:0] == 7'b1101111)
&& (x_inst[11:7] != 5'd0) //jalr
|| ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111)
&& (x_inst[11:7] != 5'd0); //jalr
//----------------------------------------------------------
// FP compare and convert
//----------------------------------------------------------
assign x_split_short_type[1] = ( ({x_inst[31:27],x_inst[24:22],x_inst[6:0]} == 15'b11000_000_1010011)
|| ({x_inst[31:27],x_inst[24:22],x_inst[6:0]} == 15'b11010_000_1010011))
&& !(cp0_idu_fs[1:0] == 2'b00) //fs bit
&& !((x_inst[14:12] == 3'b101) || (x_inst[14:12] == 3'b110)) //illegal
&& !((x_inst[14:12] == 3'b111)
&& ((cp0_idu_frm[2:0] == 3'b101)
||(cp0_idu_frm[2:0] == 3'b110)
||(cp0_idu_frm[2:0] == 3'b111)));
//----------------------------------------------------------
// Indexed Load and Store
//----------------------------------------------------------
assign x_split_short_type[2] =
cp0_idu_cskyee
&& (({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00001_100_0001011) //lbib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00011_100_0001011) //lbia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00101_100_0001011) //lhib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00111_100_0001011) //lhia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01001_100_0001011) //lwib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01011_100_0001011) //lwia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01101_100_0001011) //ldib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01111_100_0001011) //ldia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10001_100_0001011) //lbuib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10011_100_0001011) //lbuia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10101_100_0001011) //lhuib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10111_100_0001011) //lhuia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11001_100_0001011) //lwuib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11011_100_0001011) //lwuia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00001_101_0001011) //sbib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00011_101_0001011) //sbia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00101_101_0001011) //shib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00111_101_0001011) //shia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01001_101_0001011) //swib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01011_101_0001011) //swia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01101_101_0001011) //sdib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01111_101_0001011));//sdia
//----------------------------------------------------------
// Indexed Load and Store
//----------------------------------------------------------
assign x_split_short_type[3] =
cp0_idu_cskyee
&& (({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11100_100_0001011) //lwd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11110_100_0001011) //lwud
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11111_100_0001011) //ldd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11100_101_0001011) //swd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11111_101_0001011));//sdd
assign x_split_short_potnt[0] = |x_split_short_type[3:0];
assign x_split_short_potnt[2:1] = 2'b0;
assign x_split_short_type[6:4] = 3'b0;
//==========================================================
// Decode Split long Type
//==========================================================
// &Force("output","x_split_long_type"); @314
//----------------------------------------------------------
// Instruction Split Long
//----------------------------------------------------------
assign x_split = |x_split_long_type[9:0];
//----------------------------------------------------------
// Atomic Load / Store / AMO
//----------------------------------------------------------
assign x_split_long_type[0] = ({x_inst[14:13],x_inst[6:0]} == 9'b01_0101111)
&& (({x_inst[31:27],x_inst[24:20]}
== 10'b00010_00000) //lr.w/d
|| (x_inst[31:27] == 5'b00011) //sc.w/d
|| (x_inst[31:27] == 5'b00000) //amoadd.w/d
|| (x_inst[31:27] == 5'b00001) //amoswap.w/d
|| (x_inst[31:27] == 5'b00100) //amoxor.w/d
|| (x_inst[31:27] == 5'b01000) //amoor.w/d
|| (x_inst[31:27] == 5'b01100) //amoand.w/d
|| (x_inst[31:27] == 5'b10000) //amomin.w/d
|| (x_inst[31:27] == 5'b10100) //amomax.w/d
|| (x_inst[31:27] == 5'b11000) //amominu.w/d
|| (x_inst[31:27] == 5'b11100)); //amomaxu.w/d
assign x_split_potnt[0] = x_split_long_type[0];
assign x_split_potnt[2:1] = 2'b0;
assign x_split_long_type[1] = 1'b0;//normal vector inst
assign x_split_long_type[2] = 1'b0;//permute inst
assign x_split_long_type[3] = 1'b0;//vfreduction inst
assign x_split_long_type[4] = 1'b0;//stride vec load store inst
assign x_split_long_type[5] = 1'b0;//index vec load store inst
assign x_split_long_type[6] = 1'b0;//vector amo
assign x_split_long_type[7] = 1'b0;//zvlsseg unit
assign x_split_long_type[8] = 1'b0;//zvlsseg stride
assign x_split_long_type[9] = 1'b0;//zvlsseg index
//==========================================================
// Decode Fence Instruction
//==========================================================
// &Force("output","x_fence_type"); @431
//----------------------------------------------------------
// Instruction Fence
//----------------------------------------------------------
assign x_fence = |x_fence_type[2:0];
//----------------------------------------------------------
// Fence.i Instruction
//----------------------------------------------------------
assign x_fence_type[0] = cp0_idu_cskyee
&& ((x_inst[31:0] == 32'h0180000b) //sync
|| (x_inst[31:0] == 32'h0190000b) //sync.s
|| (x_inst[31:0] == 32'h01a0000b) //sync.i
|| (x_inst[31:0] == 32'h01b0000b) //sync.is
|| (x_inst[31:0] == 32'h0010000b) //dcache.call
|| (x_inst[31:0] == 32'h0020000b) //dcache.iall
|| (x_inst[31:0] == 32'h0030000b));//dcache.ciall
//----------------------------------------------------------
// CP0 Instruction
//----------------------------------------------------------
assign x_fence_type[1] = (x_inst[31:0] == 32'h10200073) //sret
// || (x_inst[31:0] == 32'h00000073) //ecall
// || (x_inst[31:0] == 32'h00100073) //ebreak
|| (x_inst[31:0] == 32'h30200073) //mret
|| (x_inst[31:0] == 32'h10500073) //wfi
// || (x_inst[15:0] == 16'h9002) //c.ebreak
|| ({x_inst[14:12],x_inst[6:0]} == 10'b001_1110011) //csrrw
|| ({x_inst[14:12],x_inst[6:0]} == 10'b010_1110011) //csrrs
|| ({x_inst[14:12],x_inst[6:0]} == 10'b011_1110011) //csrrc
|| ({x_inst[14:12],x_inst[6:0]} == 10'b101_1110011) //csrwi
|| ({x_inst[14:12],x_inst[6:0]} == 10'b110_1110011) //csrsi
|| ({x_inst[14:12],x_inst[6:0]} == 10'b111_1110011); //csrci
//----------------------------------------------------------
// sfence Instruction
//----------------------------------------------------------
assign hfence_inst = 1'b0;
assign x_fence_type[2] = ({x_inst[14:12],x_inst[6:0]} == 10'b001_0001111) //fence.i
|| ({x_inst[31:25],x_inst[14:0]}
== 22'b0001001_000000001110011) //sfence.vma
|| hfence_inst;
// &ModuleEnd; @484
endmodule |
module ct_idu_rf_prf_gated_ereg(
cp0_idu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ereg_top_clk,
pad_yy_icg_scan_en,
vfpu_idu_ex5_pipe6_wb_ereg_data,
vfpu_idu_ex5_pipe7_wb_ereg_data,
x_acc_reg_dout,
x_retired_released_wb,
x_wb_vld
);
// &Ports; @28
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ereg_top_clk;
input pad_yy_icg_scan_en;
input [5:0] vfpu_idu_ex5_pipe6_wb_ereg_data;
input [5:0] vfpu_idu_ex5_pipe7_wb_ereg_data;
input x_retired_released_wb;
input [1:0] x_wb_vld;
output [5:0] x_acc_reg_dout;
// &Regs; @29
reg [5:0] reg_dout;
// &Wires; @30
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ereg_clk;
wire ereg_clk_en;
wire ereg_top_clk;
wire pad_yy_icg_scan_en;
wire [5:0] vfpu_idu_ex5_pipe6_wb_ereg_data;
wire [5:0] vfpu_idu_ex5_pipe7_wb_ereg_data;
wire [5:0] write_data;
wire write_en;
wire [5:0] x_acc_reg_dout;
wire x_retired_released_wb;
wire [1:0] x_wb_vld;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign ereg_clk_en = write_en;
// &Instance("gated_clk_cell", "x_ereg_gated_clk"); @37
gated_clk_cell x_ereg_gated_clk (
.clk_in (ereg_top_clk ),
.clk_out (ereg_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ereg_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (ereg_top_clk), @38
// .external_en (1'b0), @39
// .global_en (cp0_yy_clk_en), @40
// .module_en (cp0_idu_icg_en), @41
// .local_en (ereg_clk_en), @42
// .clk_out (ereg_clk)); @43
//==========================================================
// Write Port
//==========================================================
assign write_en = |x_wb_vld[1:0];
assign write_data[5:0] =
{6{x_wb_vld[0]}} & vfpu_idu_ex5_pipe6_wb_ereg_data[5:0]
| {6{x_wb_vld[1]}} & vfpu_idu_ex5_pipe7_wb_ereg_data[5:0];
//==========================================================
// Freg Register
//==========================================================
always @(posedge ereg_clk or negedge cpurst_b)
begin
if(!cpurst_b)
reg_dout[5:0] <= 6'b0;
else if(write_en)
reg_dout[5:0] <= write_data[5:0];
else
reg_dout[5:0] <= reg_dout[5:0];
end
//assign x_reg_dout[5:0] = reg_dout[5:0];
//==========================================================
// Accumulate Register Update Value
//==========================================================
assign x_acc_reg_dout[5:0] = {6{x_retired_released_wb}} & reg_dout[5:0];
// &ModuleEnd; @73
endmodule |
module ct_idu_rf_pipe2_decd(
pipe2_decd_func,
pipe2_decd_offset,
pipe2_decd_opcode,
pipe2_decd_src1_imm
);
// &Ports; @28
input [31:0] pipe2_decd_opcode;
output [7 :0] pipe2_decd_func;
output [20:0] pipe2_decd_offset;
output [63:0] pipe2_decd_src1_imm;
// &Regs; @29
reg [7 :0] decd_16_func;
reg [7 :0] decd_32_func;
reg [20:0] pipe2_decd_offset;
// &Wires; @30
wire [5 :0] decd_imm_sel;
wire [31:0] decd_op;
wire [7 :0] pipe2_decd_func;
wire [31:0] pipe2_decd_opcode;
wire [63:0] pipe2_decd_src1_imm;
//==========================================================
// Rename Input
//==========================================================
assign decd_op[31:0] = pipe2_decd_opcode[31:0];
//==========================================================
// Immediate
//==========================================================
//----------------------------------------------------------
// Source 1 immediate
//----------------------------------------------------------
assign pipe2_decd_src1_imm[63:0] = 64'b0;
//----------------------------------------------------------
// Offset Selection
//----------------------------------------------------------
//32 bit imm20
assign decd_imm_sel[0] = (decd_op[3:0] == 4'b1111);
//32 bit imm12
assign decd_imm_sel[1] = (decd_op[3:0] == 4'b0111);
//32 bit imm13
assign decd_imm_sel[2] = (decd_op[3:0] == 4'b0011);
//16 bit imm12
assign decd_imm_sel[3] = ({decd_op[15:14],decd_op[1:0]} == 4'b10_01);
//16 bit imm9
assign decd_imm_sel[4] = ({decd_op[15:14],decd_op[1:0]} == 4'b11_01);
//16 bit 0
assign decd_imm_sel[5] = (decd_op[1:0] == 2'b10);
//----------------------------------------------------------
// Offset immediate
//----------------------------------------------------------
// &CombBeg; @65
always @( decd_op[31:2]
or decd_imm_sel[5:0])
begin
case(decd_imm_sel[5:0])
6'h01 : pipe2_decd_offset[20:0] = {decd_op[31],decd_op[19:12],
decd_op[20], decd_op[30:21],1'b0};
6'h02 : pipe2_decd_offset[20:0] = {{9{decd_op[31]}},decd_op[31:20]};
6'h04 : pipe2_decd_offset[20:0] = {{8{decd_op[31]}},decd_op[31],
decd_op[7], decd_op[30:25],
decd_op[11:8],1'b0};
6'h08 : pipe2_decd_offset[20:0] = {{9{decd_op[12]}},decd_op[12],
decd_op[8], decd_op[10:9],
decd_op[6], decd_op[7],
decd_op[2], decd_op[11],
decd_op[5:3],1'b0};
6'h10 : pipe2_decd_offset[20:0] = {{12{decd_op[12]}},decd_op[12],
decd_op[6:5], decd_op[2],
decd_op[11:10], decd_op[4:3],1'b0};
6'h20 : pipe2_decd_offset[20:0] = 21'b0;
default: pipe2_decd_offset[20:0] = {21{1'bx}};
endcase
// &CombEnd; @84
end
//==========================================================
// Full Decoder for function and operand prepare
//==========================================================
//----------------------------------------------------------
// Rename for Output
//----------------------------------------------------------
assign pipe2_decd_func[7:0] = (decd_op[1:0] == 2'b11)
? decd_32_func[7:0]
: decd_16_func[7:0];
//----------------------------------------------------------
// 16 bit FUll Decoder
//----------------------------------------------------------
// &CombBeg; @99
always @( decd_op[6:5]
or decd_op[1:0]
or decd_op[15:10])
begin
//initialize decoded information value
casez({decd_op[15:10], decd_op[6:5], decd_op[1:0]})
//16-bits instructions decode logic
10'b101???_??01: //c.j
decd_16_func[7:0] = 8'b01_000000;
10'b110???_??01: //c.beqz
decd_16_func[7:0] = 8'b00_100000;
10'b111???_??01: //c.bnez
decd_16_func[7:0] = 8'b00_010000;
10'b1000??_??10: //c.jr
decd_16_func[7:0] = 8'b10_000000;
10'b1001??_??10: //c.jalr
decd_16_func[7:0] = 8'b10_000000;
default: //invalid instruction
decd_16_func[7:0] = 8'b0;
endcase
// &CombEnd; @116
end
//----------------------------------------------------------
// 32 bits Full Decoder
//----------------------------------------------------------
// &CombBeg; @121
always @( decd_op[6:2]
or decd_op[31:25]
or decd_op[14:12])
begin
//initialize decoded information value
casez({decd_op[31:25], decd_op[14:12], decd_op[6:2]})
//32-bits instructions decode logic
15'b??????????11011: //jal (dst_vld deal in split)
decd_32_func[7:0] = 8'b01000000;
15'b???????00011001: //jalr (dst_vld deal in split)
decd_32_func[7:0] = 8'b10000000;
15'b???????00011000: //beq
decd_32_func[7:0] = 8'b00100000;
15'b???????00111000: //bne
decd_32_func[7:0] = 8'b00_010000;
15'b???????10011000: //blt
decd_32_func[7:0] = 8'b00001000;
15'b???????10111000: //bge
decd_32_func[7:0] = 8'b00000010;
15'b???????11011000: //bltu
decd_32_func[7:0] = 8'b00000100;
15'b???????11111000: //bgeu
decd_32_func[7:0] = 8'b00000001;
default: //invalid instruction
decd_32_func[7:0] = 8'b0;
endcase
// &CombEnd; @144
end
// &ModuleEnd; @146
endmodule |
module ct_idu_id_ctrl(
cp0_idu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_dp_id_debug_id_pipedown3,
ctrl_dp_id_inst0_vld,
ctrl_dp_id_inst1_vld,
ctrl_dp_id_inst2_vld,
ctrl_dp_id_pipedown_1_inst,
ctrl_dp_id_pipedown_2_inst,
ctrl_dp_id_pipedown_3_inst,
ctrl_dp_id_stall,
ctrl_fence_id_inst_vld,
ctrl_fence_id_stall,
ctrl_id_pipedown_gateclk,
ctrl_id_pipedown_inst0_vld,
ctrl_id_pipedown_inst1_vld,
ctrl_id_pipedown_inst2_vld,
ctrl_id_pipedown_inst3_vld,
ctrl_ir_stage_stall,
ctrl_ir_stall,
ctrl_split_long_id_inst_vld,
ctrl_split_long_id_stall,
ctrl_top_id_inst0_vld,
ctrl_top_id_inst1_vld,
ctrl_top_id_inst2_vld,
dp_ctrl_id_inst0_fence,
dp_ctrl_id_inst0_normal,
dp_ctrl_id_inst0_split_long,
dp_ctrl_id_inst0_split_short,
dp_ctrl_id_inst1_fence,
dp_ctrl_id_inst1_normal,
dp_ctrl_id_inst1_split_long,
dp_ctrl_id_inst1_split_short,
dp_ctrl_id_inst2_fence,
dp_ctrl_id_inst2_normal,
dp_ctrl_id_inst2_split_long,
dp_ctrl_id_inst2_split_short,
fence_ctrl_id_stall,
fence_ctrl_inst0_vld,
fence_ctrl_inst1_vld,
fence_ctrl_inst2_vld,
forever_cpuclk,
had_idu_debug_id_inst_en,
hpcp_idu_cnt_en,
idu_had_id_inst0_vld,
idu_had_id_inst1_vld,
idu_had_id_inst2_vld,
idu_had_pipe_stall,
idu_hpcp_backend_stall,
idu_ifu_id_bypass_stall,
idu_ifu_id_stall,
ifu_idu_ib_inst0_vld,
ifu_idu_ib_inst1_vld,
ifu_idu_ib_inst2_vld,
ifu_idu_ib_pipedown_gateclk,
iu_yy_xx_cancel,
pad_yy_icg_scan_en,
rtu_idu_flush_fe,
split_long_ctrl_id_stall,
split_long_ctrl_inst_vld
);
// &Ports; @28
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_ir_stage_stall;
input ctrl_ir_stall;
input dp_ctrl_id_inst0_fence;
input dp_ctrl_id_inst0_normal;
input dp_ctrl_id_inst0_split_long;
input dp_ctrl_id_inst0_split_short;
input dp_ctrl_id_inst1_fence;
input dp_ctrl_id_inst1_normal;
input dp_ctrl_id_inst1_split_long;
input dp_ctrl_id_inst1_split_short;
input dp_ctrl_id_inst2_fence;
input dp_ctrl_id_inst2_normal;
input dp_ctrl_id_inst2_split_long;
input dp_ctrl_id_inst2_split_short;
input fence_ctrl_id_stall;
input fence_ctrl_inst0_vld;
input fence_ctrl_inst1_vld;
input fence_ctrl_inst2_vld;
input forever_cpuclk;
input had_idu_debug_id_inst_en;
input hpcp_idu_cnt_en;
input ifu_idu_ib_inst0_vld;
input ifu_idu_ib_inst1_vld;
input ifu_idu_ib_inst2_vld;
input ifu_idu_ib_pipedown_gateclk;
input iu_yy_xx_cancel;
input pad_yy_icg_scan_en;
input rtu_idu_flush_fe;
input split_long_ctrl_id_stall;
input [3:0] split_long_ctrl_inst_vld;
output ctrl_dp_id_debug_id_pipedown3;
output ctrl_dp_id_inst0_vld;
output ctrl_dp_id_inst1_vld;
output ctrl_dp_id_inst2_vld;
output ctrl_dp_id_pipedown_1_inst;
output ctrl_dp_id_pipedown_2_inst;
output ctrl_dp_id_pipedown_3_inst;
output ctrl_dp_id_stall;
output ctrl_fence_id_inst_vld;
output ctrl_fence_id_stall;
output ctrl_id_pipedown_gateclk;
output ctrl_id_pipedown_inst0_vld;
output ctrl_id_pipedown_inst1_vld;
output ctrl_id_pipedown_inst2_vld;
output ctrl_id_pipedown_inst3_vld;
output ctrl_split_long_id_inst_vld;
output ctrl_split_long_id_stall;
output ctrl_top_id_inst0_vld;
output ctrl_top_id_inst1_vld;
output ctrl_top_id_inst2_vld;
output idu_had_id_inst0_vld;
output idu_had_id_inst1_vld;
output idu_had_id_inst2_vld;
output idu_had_pipe_stall;
output idu_hpcp_backend_stall;
output idu_ifu_id_bypass_stall;
output idu_ifu_id_stall;
// &Regs; @29
reg ctrl_id_pipedown_inst1_vld;
reg ctrl_id_pipedown_inst2_vld;
reg ctrl_id_pipedown_inst3_vld;
reg debug_id_inst0_vld;
reg debug_id_inst1_vld;
reg debug_id_inst2_vld;
reg debug_id_pipedown3;
reg id_inst0_vld;
reg id_inst1_vld;
reg id_inst2_vld;
// &Wires; @30
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_dp_id_debug_id_pipedown3;
wire ctrl_dp_id_inst0_vld;
wire ctrl_dp_id_inst1_vld;
wire ctrl_dp_id_inst2_vld;
wire ctrl_dp_id_pipedown_1_inst;
wire ctrl_dp_id_pipedown_2_inst;
wire ctrl_dp_id_pipedown_3_inst;
wire ctrl_dp_id_stall;
wire ctrl_fence_id_inst_vld;
wire ctrl_fence_id_stall;
wire ctrl_ib_pipedown_inst0_vld;
wire ctrl_ib_pipedown_inst1_vld;
wire ctrl_ib_pipedown_inst2_vld;
wire ctrl_id_1_fence_inst;
wire ctrl_id_1_split_long_inst;
wire ctrl_id_bypass_stall;
wire ctrl_id_inst0_fence;
wire ctrl_id_inst0_normal;
wire ctrl_id_inst0_split_long;
wire ctrl_id_inst0_split_short;
wire ctrl_id_inst1_fence;
wire ctrl_id_inst1_normal;
wire ctrl_id_inst1_split_long;
wire ctrl_id_inst1_split_short;
wire ctrl_id_inst2_fence;
wire ctrl_id_inst2_normal;
wire ctrl_id_inst2_split_long;
wire ctrl_id_inst2_split_short;
wire ctrl_id_pipedown_1_inst;
wire ctrl_id_pipedown_2_inst;
wire ctrl_id_pipedown_3_inst;
wire ctrl_id_pipedown_3_inst_for_bypass;
wire ctrl_id_pipedown_gateclk;
wire ctrl_id_pipedown_inst0_vld;
wire ctrl_id_pipedown_stall;
wire ctrl_id_split_long_stall;
wire ctrl_id_stall;
wire ctrl_ir_stage_stall;
wire ctrl_ir_stall;
wire ctrl_split_long_id_inst_vld;
wire ctrl_split_long_id_stall;
wire ctrl_top_id_inst0_vld;
wire ctrl_top_id_inst1_vld;
wire ctrl_top_id_inst2_vld;
wire debug_id_inst_clk;
wire debug_id_inst_clk_en;
wire debug_id_inst_vld;
wire dp_ctrl_id_inst0_fence;
wire dp_ctrl_id_inst0_normal;
wire dp_ctrl_id_inst0_split_long;
wire dp_ctrl_id_inst0_split_short;
wire dp_ctrl_id_inst1_fence;
wire dp_ctrl_id_inst1_normal;
wire dp_ctrl_id_inst1_split_long;
wire dp_ctrl_id_inst1_split_short;
wire dp_ctrl_id_inst2_fence;
wire dp_ctrl_id_inst2_normal;
wire dp_ctrl_id_inst2_split_long;
wire dp_ctrl_id_inst2_split_short;
wire fence_ctrl_id_stall;
wire fence_ctrl_inst0_vld;
wire fence_ctrl_inst1_vld;
wire fence_ctrl_inst2_vld;
wire forever_cpuclk;
wire had_idu_debug_id_inst_en;
wire hpcp_idu_cnt_en;
wire id_inst_clk;
wire id_inst_clk_en;
wire idu_had_id_inst0_vld;
wire idu_had_id_inst1_vld;
wire idu_had_id_inst2_vld;
wire idu_had_pipe_stall;
wire idu_hpcp_backend_stall;
wire idu_ifu_id_bypass_stall;
wire idu_ifu_id_stall;
wire ifu_idu_ib_inst0_vld;
wire ifu_idu_ib_inst1_vld;
wire ifu_idu_ib_inst2_vld;
wire ifu_idu_ib_pipedown_gateclk;
wire iu_yy_xx_cancel;
wire pad_yy_icg_scan_en;
wire rtu_idu_flush_fe;
wire split_long_ctrl_id_stall;
wire [3:0] split_long_ctrl_inst_vld;
//==========================================================
// ID pipeline registers
//==========================================================
//----------------------------------------------------------
// IB Pipedown Instruction selection
//----------------------------------------------------------
assign ctrl_ib_pipedown_inst0_vld =
ctrl_id_pipedown_1_inst && id_inst1_vld
|| ctrl_id_pipedown_2_inst && id_inst2_vld
|| ctrl_id_pipedown_3_inst && ifu_idu_ib_inst0_vld;
assign ctrl_ib_pipedown_inst1_vld =
ctrl_id_pipedown_1_inst && id_inst2_vld
|| ctrl_id_pipedown_2_inst && 1'b0
|| ctrl_id_pipedown_3_inst && ifu_idu_ib_inst1_vld;
assign ctrl_ib_pipedown_inst2_vld =
ctrl_id_pipedown_1_inst && 1'b0
|| ctrl_id_pipedown_2_inst && 1'b0
|| ctrl_id_pipedown_3_inst && ifu_idu_ib_inst2_vld;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign id_inst_clk_en = ifu_idu_ib_pipedown_gateclk
|| id_inst0_vld
|| id_inst1_vld
|| id_inst2_vld;
// &Instance("gated_clk_cell", "x_id_inst_gated_clk"); @60
gated_clk_cell x_id_inst_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (id_inst_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (id_inst_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @61
// .external_en (1'b0), @62
// .global_en (cp0_yy_clk_en), @63
// .module_en (cp0_idu_icg_en), @64
// .local_en (id_inst_clk_en), @65
// .clk_out (id_inst_clk)); @66
//----------------------------------------------------------
// Pipeline register implement
//----------------------------------------------------------
always @(posedge id_inst_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
id_inst0_vld <= 1'b0;
id_inst1_vld <= 1'b0;
id_inst2_vld <= 1'b0;
end
else if(rtu_idu_flush_fe || iu_yy_xx_cancel) begin
id_inst0_vld <= 1'b0;
id_inst1_vld <= 1'b0;
id_inst2_vld <= 1'b0;
end
else if(!ctrl_id_pipedown_stall) begin
id_inst0_vld <= ctrl_ib_pipedown_inst0_vld;
id_inst1_vld <= ctrl_ib_pipedown_inst1_vld;
id_inst2_vld <= ctrl_ib_pipedown_inst2_vld;
end
else begin
id_inst0_vld <= id_inst0_vld;
id_inst1_vld <= id_inst1_vld;
id_inst2_vld <= id_inst2_vld;
end
end
assign ctrl_dp_id_inst0_vld = id_inst0_vld;
assign ctrl_dp_id_inst1_vld = id_inst1_vld;
assign ctrl_dp_id_inst2_vld = id_inst2_vld;
assign ctrl_id_pipedown_gateclk = id_inst0_vld;
assign ctrl_top_id_inst0_vld = id_inst0_vld;
assign ctrl_top_id_inst1_vld = id_inst1_vld;
assign ctrl_top_id_inst2_vld = id_inst2_vld;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign debug_id_inst_clk_en = debug_id_inst_vld
|| debug_id_pipedown3
|| debug_id_inst0_vld;
// &Instance("gated_clk_cell", "x_debug_id_inst_gated_clk"); @109
gated_clk_cell x_debug_id_inst_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (debug_id_inst_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (debug_id_inst_clk_en),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk), @110
// .external_en (1'b0), @111
// .global_en (cp0_yy_clk_en), @112
// .module_en (cp0_idu_icg_en), @113
// .local_en (debug_id_inst_clk_en), @114
// .clk_out (debug_id_inst_clk)); @115
//----------------------------------------------------------
// Pipeline register implement
//----------------------------------------------------------
assign debug_id_inst_vld = id_inst0_vld
&& (had_idu_debug_id_inst_en
|| hpcp_idu_cnt_en);
always @(posedge debug_id_inst_clk or negedge cpurst_b)
begin
if(!cpurst_b)
debug_id_pipedown3 <= 1'b0;
else if(debug_id_inst_vld)
debug_id_pipedown3 <= !ctrl_id_stall;
else
debug_id_pipedown3 <= 1'b0;
end
assign ctrl_dp_id_debug_id_pipedown3 = debug_id_pipedown3;
assign idu_hpcp_backend_stall = !debug_id_pipedown3;
//----------------------------------------------------------
// Pipeline register implement
//----------------------------------------------------------
always @(posedge debug_id_inst_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
debug_id_inst0_vld <= 1'b0;
debug_id_inst1_vld <= 1'b0;
debug_id_inst2_vld <= 1'b0;
end
else if(debug_id_pipedown3) begin
debug_id_inst0_vld <= id_inst0_vld;
debug_id_inst1_vld <= id_inst1_vld;
debug_id_inst2_vld <= id_inst2_vld;
end
else begin
debug_id_inst0_vld <= 1'b0;
debug_id_inst1_vld <= 1'b0;
debug_id_inst2_vld <= 1'b0;
end
end
assign idu_had_id_inst0_vld = debug_id_inst0_vld;
assign idu_had_id_inst1_vld = debug_id_inst1_vld;
assign idu_had_id_inst2_vld = debug_id_inst2_vld;
//==========================================================
// ID stage control signals
//==========================================================
//----------------------------------------------------------
// Prepare Type Signals
//----------------------------------------------------------
assign ctrl_id_inst0_fence = id_inst0_vld && dp_ctrl_id_inst0_fence;
assign ctrl_id_inst1_fence = id_inst1_vld && dp_ctrl_id_inst1_fence;
assign ctrl_id_inst2_fence = id_inst2_vld && dp_ctrl_id_inst2_fence;
assign ctrl_id_inst0_split_short = id_inst0_vld && dp_ctrl_id_inst0_split_short;
assign ctrl_id_inst1_split_short = id_inst1_vld && dp_ctrl_id_inst1_split_short;
assign ctrl_id_inst2_split_short = id_inst2_vld && dp_ctrl_id_inst2_split_short;
assign ctrl_id_inst0_split_long = id_inst0_vld && dp_ctrl_id_inst0_split_long;
assign ctrl_id_inst1_split_long = id_inst1_vld && dp_ctrl_id_inst1_split_long;
assign ctrl_id_inst2_split_long = id_inst2_vld && dp_ctrl_id_inst2_split_long;
assign ctrl_id_inst0_normal = id_inst0_vld && dp_ctrl_id_inst0_normal;
assign ctrl_id_inst1_normal = id_inst1_vld && dp_ctrl_id_inst1_normal;
assign ctrl_id_inst2_normal = id_inst2_vld && dp_ctrl_id_inst2_normal;
//----------------------------------------------------------
// Fence Instruction Valid
//----------------------------------------------------------
//fence valid only when ID inst0 is valid fence inst
assign ctrl_fence_id_inst_vld = ctrl_id_inst0_fence;
//----------------------------------------------------------
// Long Split Instruction Valid
//----------------------------------------------------------
//long split valid only when ID inst0 is valid long split inst
assign ctrl_split_long_id_inst_vld = ctrl_id_inst0_split_long;
//==========================================================
// Pipedown control signals
//==========================================================
//----------------------------------------------------------
// IR Pipedown Instruction 0 valid
//----------------------------------------------------------
assign ctrl_id_pipedown_inst0_vld =
ctrl_id_inst0_normal && id_inst0_vld
|| ctrl_id_inst0_split_short && 1'b1
|| ctrl_id_inst0_split_long && split_long_ctrl_inst_vld[0]
|| ctrl_id_inst0_fence && fence_ctrl_inst0_vld;
//----------------------------------------------------------
// IR Pipedown Instruction 1 valid
//----------------------------------------------------------
// &CombBeg; @211
always @( ctrl_id_inst1_fence
or ctrl_id_inst0_split_long
or ctrl_id_inst1_split_long
or ctrl_id_inst0_fence
or ctrl_id_inst0_split_short
or split_long_ctrl_inst_vld[1]
or id_inst1_vld
or fence_ctrl_inst1_vld
or ctrl_id_inst1_split_short
or ctrl_id_pipedown_1_inst)
begin
//consider id inst0 type
if(ctrl_id_inst0_fence)
ctrl_id_pipedown_inst1_vld = fence_ctrl_inst1_vld;
else if(ctrl_id_inst0_split_short)
ctrl_id_pipedown_inst1_vld = 1'b1;
else if(ctrl_id_inst0_split_long)
ctrl_id_pipedown_inst1_vld = split_long_ctrl_inst_vld[1];
//consider id inst1 type
else if(ctrl_id_inst1_fence)
ctrl_id_pipedown_inst1_vld = 1'b0;
else if(ctrl_id_inst1_split_long)
ctrl_id_pipedown_inst1_vld = 1'b0;
else if(ctrl_id_inst1_split_short)
ctrl_id_pipedown_inst1_vld = 1'b1;
else
ctrl_id_pipedown_inst1_vld = id_inst1_vld
&& !ctrl_id_pipedown_1_inst;
// &CombEnd; @229
end
//----------------------------------------------------------
// IR Pipedown Instruction 2 valid
//----------------------------------------------------------
// &CombBeg; @234
always @( ctrl_id_inst1_fence
or ctrl_id_inst0_split_long
or ctrl_id_inst1_split_long
or ctrl_id_pipedown_2_inst
or ctrl_id_inst0_fence
or fence_ctrl_inst2_vld
or ctrl_id_inst0_split_short
or id_inst1_vld
or id_inst2_vld
or split_long_ctrl_inst_vld[2]
or ctrl_id_inst1_split_short
or ctrl_id_inst2_split_short
or ctrl_id_inst2_fence
or ctrl_id_pipedown_1_inst
or ctrl_id_inst2_split_long)
begin
//consider id inst0 type
if(ctrl_id_inst0_fence)
ctrl_id_pipedown_inst2_vld = fence_ctrl_inst2_vld;
else if(ctrl_id_inst0_split_long)
ctrl_id_pipedown_inst2_vld = split_long_ctrl_inst_vld[2];
else if(ctrl_id_inst0_split_short && ctrl_id_inst1_split_short)
ctrl_id_pipedown_inst2_vld = 1'b1;
else if(ctrl_id_inst0_split_short)
ctrl_id_pipedown_inst2_vld = id_inst1_vld
&& !ctrl_id_pipedown_1_inst;
//consider id inst1 type
else if(ctrl_id_inst1_fence)
ctrl_id_pipedown_inst2_vld = 1'b0;
else if(ctrl_id_inst1_split_long)
ctrl_id_pipedown_inst2_vld = 1'b0;
else if(ctrl_id_inst1_split_short)
ctrl_id_pipedown_inst2_vld = 1'b1;
//consider id inst2 type
else if(ctrl_id_inst2_fence)
ctrl_id_pipedown_inst2_vld = 1'b0;
else if(ctrl_id_inst2_split_long)
ctrl_id_pipedown_inst2_vld = 1'b0;
else if(ctrl_id_inst2_split_short)
ctrl_id_pipedown_inst2_vld = 1'b1;
else
ctrl_id_pipedown_inst2_vld = id_inst2_vld
&& !ctrl_id_pipedown_1_inst
&& !ctrl_id_pipedown_2_inst;
// &CombEnd; @263
end
//----------------------------------------------------------
// IR Pipedown Instruction 3 valid
//----------------------------------------------------------
// &CombBeg; @268
always @( ctrl_id_inst1_fence
or ctrl_id_inst0_split_long
or ctrl_id_pipedown_2_inst
or ctrl_id_inst1_split_long
or ctrl_id_inst0_fence
or ctrl_id_inst0_split_short
or id_inst2_vld
or split_long_ctrl_inst_vld[3]
or ctrl_id_inst1_split_short
or ctrl_id_inst2_split_short
or ctrl_id_pipedown_1_inst)
begin
//consider id inst0 type
if(ctrl_id_inst0_fence)
ctrl_id_pipedown_inst3_vld = 1'b0;
else if(ctrl_id_inst0_split_long)
ctrl_id_pipedown_inst3_vld = split_long_ctrl_inst_vld[3];
else if(ctrl_id_inst0_split_short && ctrl_id_inst1_split_short)
ctrl_id_pipedown_inst3_vld = 1'b1;
else if(ctrl_id_inst0_split_short)
ctrl_id_pipedown_inst3_vld = id_inst2_vld
&& !ctrl_id_pipedown_1_inst
&& !ctrl_id_pipedown_2_inst;
//consider id inst1 type
else if(ctrl_id_inst1_fence)
ctrl_id_pipedown_inst3_vld = 1'b0;
else if(ctrl_id_inst1_split_long)
ctrl_id_pipedown_inst3_vld = 1'b0;
else if(ctrl_id_inst1_split_short)
ctrl_id_pipedown_inst3_vld = id_inst2_vld
&& !ctrl_id_pipedown_1_inst
&& !ctrl_id_pipedown_2_inst;
//consider id inst2 type
else
ctrl_id_pipedown_inst3_vld = ctrl_id_inst2_split_short
&& !ctrl_id_pipedown_1_inst
&& !ctrl_id_pipedown_2_inst;
// &CombEnd; @294
end
//==========================================================
// Pipedown Instruction Type
//==========================================================
//short split: split to 2 inst
//long split: (may) split to more than 2 inst
assign ctrl_id_1_fence_inst = ctrl_id_inst0_fence
|| ctrl_id_inst1_fence
|| ctrl_id_inst2_fence;
assign ctrl_id_1_split_long_inst = ctrl_id_inst0_split_long
|| ctrl_id_inst1_split_long
|| ctrl_id_inst2_split_long;
//----------------------------------------------------------
// Pipedown 1 Inst
//----------------------------------------------------------
//pipedown 1 inst when:
// inst0 can pipedown (not a stall long split, fence stall deal in id stall)
// while inst1 cannot pipedown with inst0
assign ctrl_id_pipedown_1_inst =
(ctrl_id_inst0_normal || ctrl_id_inst0_split_short)
&& (ctrl_id_inst1_fence || ctrl_id_inst1_split_long)
|| (ctrl_id_inst0_split_long && !split_long_ctrl_id_stall
|| ctrl_id_inst0_fence && !fence_ctrl_id_stall);
//----------------------------------------------------------
// Pipedown 2 Inst
//----------------------------------------------------------
//pipedown 2 inst when:
// inst0 and inst1 are normal or split short
// while inst2 cannot pipedown with inst0 and inst1
assign ctrl_id_pipedown_2_inst =
(ctrl_id_inst0_normal || ctrl_id_inst0_split_short)
&& (ctrl_id_inst1_normal || ctrl_id_inst1_split_short)
&& (ctrl_id_inst2_normal
&& ctrl_id_inst0_split_short && ctrl_id_inst1_split_short
|| ctrl_id_inst2_split_short
&& (ctrl_id_inst0_split_short || ctrl_id_inst1_split_short)
|| ctrl_id_inst2_split_long
|| ctrl_id_inst2_fence);
//----------------------------------------------------------
// Pipedown 3 Inst
//----------------------------------------------------------
//pipedown 3 inst when:
//1. no fence inst and no long split inst and no 2 or more short split inst
// (except inst0/1 are short split insts and inst 2 is normal inst)
assign ctrl_id_pipedown_3_inst =
!ctrl_id_1_fence_inst
&& !ctrl_id_1_split_long_inst
&& !(ctrl_id_inst2_split_short
&& (ctrl_id_inst0_split_short || ctrl_id_inst1_split_short))
&& !(id_inst2_vld
&& (ctrl_id_inst0_split_short && ctrl_id_inst1_split_short));
//pipedown 3 inst signal for IFU ibuf bypass with timing optimization:
//no timing optimization
assign ctrl_id_pipedown_3_inst_for_bypass = ctrl_id_pipedown_3_inst;
//----------------------------------------------------------
// ID inst Select
//----------------------------------------------------------
//rename for data path
assign ctrl_dp_id_pipedown_1_inst = ctrl_id_pipedown_1_inst;
assign ctrl_dp_id_pipedown_2_inst = ctrl_id_pipedown_2_inst;
assign ctrl_dp_id_pipedown_3_inst = ctrl_id_pipedown_3_inst;
//==========================================================
// ID stage stall
//==========================================================
//----------------------------------------------------------
// ID stage Stall Source
//----------------------------------------------------------
//if ir stage stall
assign ctrl_split_long_id_stall = ctrl_ir_stall;
assign ctrl_fence_id_stall = ctrl_ir_stall;
//split long stall
assign ctrl_id_split_long_stall = ctrl_id_inst0_split_long
&& split_long_ctrl_id_stall;
//----------------------------------------------------------
// ID stage Stall
//----------------------------------------------------------
// id stall for IFU
assign ctrl_id_stall = id_inst0_vld
&& (ctrl_ir_stall
|| !ctrl_id_pipedown_3_inst);
//bypass id stall for IFU bypass
assign ctrl_id_bypass_stall = id_inst0_vld
&& (ctrl_ir_stall
|| !ctrl_id_pipedown_3_inst_for_bypass);
//pipedown stall for ID inst valid and data path
assign ctrl_id_pipedown_stall = id_inst0_vld
&& (ctrl_ir_stall
|| fence_ctrl_id_stall
|| ctrl_id_split_long_stall);
//----------------------------------------------------------
// Output stall signals
//----------------------------------------------------------
assign ctrl_dp_id_stall = ctrl_id_pipedown_stall;
assign idu_ifu_id_stall = ctrl_id_stall;
assign idu_ifu_id_bypass_stall = ctrl_id_bypass_stall;
assign idu_had_pipe_stall = id_inst0_vld && fence_ctrl_id_stall
|| ctrl_ir_stage_stall;
// &ModuleEnd; @403
endmodule |
module ct_idu_rf_pipe1_decd(
pipe1_decd_eu_sel,
pipe1_decd_func,
pipe1_decd_imm,
pipe1_decd_mult_func,
pipe1_decd_opcode,
pipe1_decd_sel,
pipe1_decd_src1_imm
);
// &Ports; @28
input [31:0] pipe1_decd_opcode;
output [1 :0] pipe1_decd_eu_sel;
output [4 :0] pipe1_decd_func;
output [5 :0] pipe1_decd_imm;
output [7 :0] pipe1_decd_mult_func;
output [20:0] pipe1_decd_sel;
output [63:0] pipe1_decd_src1_imm;
// &Regs; @29
reg [1 :0] decd_16_eu_sel;
reg [4 :0] decd_16_func;
reg [20:0] decd_16_sel;
reg [1 :0] decd_32_eu_sel;
reg [4 :0] decd_32_func;
reg [20:0] decd_32_sel;
reg [63:0] pipe1_decd_src1_imm;
// &Wires; @30
wire [9 :0] decd_caddi4spn_imm;
wire [9 :0] decd_caddisp_imm;
wire [5 :0] decd_ext_offset;
wire [4 :0] decd_imm_sel;
wire decd_mult_mula_muls;
wire [31:0] decd_op;
wire [1 :0] pipe1_decd_eu_sel;
wire [4 :0] pipe1_decd_func;
wire [5 :0] pipe1_decd_imm;
wire [7 :0] pipe1_decd_mult_func;
wire [31:0] pipe1_decd_opcode;
wire [20:0] pipe1_decd_sel;
//==========================================================
// Rename Input
//==========================================================
assign decd_op[31:0] = pipe1_decd_opcode[31:0];
//==========================================================
// Immediate
//==========================================================
//----------------------------------------------------------
// Immediate Selection
//----------------------------------------------------------
//32 bit imm20
assign decd_imm_sel[0] = (decd_op[6:0] == 7'b0110111)
|| (decd_op[6:0] == 7'b0010111);
//32 bit imm12
assign decd_imm_sel[1] = (decd_op[1:0] == 2'b11)
&& !decd_imm_sel[0];
//16 bit imm6
assign decd_imm_sel[2] = (decd_op[1:0] != 2'b11)
&& !decd_imm_sel[3]
&& !decd_imm_sel[4];
//16 bit caddisp
assign decd_imm_sel[3] = ({decd_op[15:13],decd_op[11:7],
decd_op[1:0]} == 10'b011_00010_01);
//16 bit caddi4spn
assign decd_imm_sel[4] = ({decd_op[15:13],decd_op[1:0]}
== 5'b000_00);
//----------------------------------------------------------
// Source 1 immediate
//----------------------------------------------------------
assign decd_caddisp_imm[9:0] = {decd_op[12],decd_op[4:3],
decd_op[5], decd_op[2],
decd_op[6], 4'b0};
assign decd_caddi4spn_imm[9:0] = {decd_op[10:7],decd_op[12:11],
decd_op[5], decd_op[6],2'b0};
// &CombBeg; @71
always @( decd_op[6:2]
or decd_imm_sel[4:0]
or decd_op[31:12]
or decd_caddi4spn_imm[9:0]
or decd_caddisp_imm[9:0])
begin
case(decd_imm_sel[4:0])
5'h01 : pipe1_decd_src1_imm[63:0] = {44'b0, decd_op[31:12]};
5'h02 : pipe1_decd_src1_imm[63:0] = {{52{decd_op[31]}},decd_op[31:20]};
5'h04 : pipe1_decd_src1_imm[63:0] = {{58{decd_op[12]}},
decd_op[12],decd_op[6:2]};
5'h08 : pipe1_decd_src1_imm[63:0] = {{54{decd_caddisp_imm[9]}},
decd_caddisp_imm[9:0]};
5'h10 : pipe1_decd_src1_imm[63:0] = {54'b0, decd_caddi4spn_imm[9:0]};
default: pipe1_decd_src1_imm[63:0] = {64{1'bx}};
endcase
// &CombEnd; @82
end
//----------------------------------------------------------
// Source immediate
//----------------------------------------------------------
assign decd_ext_offset[5:0] = decd_op[31:26] - decd_op[25:20];
assign pipe1_decd_imm[5:0] = decd_op[13] ? decd_ext_offset[5:0]
: {4'b0,decd_op[26:25]};
//==========================================================
// Mult func Decoder
//==========================================================
//casez({decd_op[31:25], decd_op[14:12], decd_op[6:2]})
// 15'b0000001_000_01100:begin //mul
// 15'b0000001_001_01100:begin //mulh
// 15'b0000001_010_01100:begin //mulhsu
// 15'b0000001_011_01100:begin //mulhu
// 15'b0000001_000_01110:begin //mulw
// 15'b0010000_001_00010:begin //mula
// 15'b0010001_001_00010:begin //muls
// 15'b0010010_001_00010:begin //mulaw
// 15'b0010011_001_00010:begin //mulsw
// 15'b0010100_001_00010:begin //mulah
// 15'b0010101_001_00010:begin //mulsh
//for timing consideration, decode mult func
assign decd_mult_mula_muls = ({decd_op[27:26],decd_op[4]} == 3'b0);
assign pipe1_decd_mult_func[0] = (decd_op[13:12] != 2'b00) && decd_op[4];
assign pipe1_decd_mult_func[1] = decd_op[3] && !decd_mult_mula_muls;
assign pipe1_decd_mult_func[2] = decd_op[3] && !decd_mult_mula_muls
|| (decd_op[13:12] == 2'b11);
assign pipe1_decd_mult_func[3] = decd_op[3] && !decd_mult_mula_muls
|| decd_op[13];
assign pipe1_decd_mult_func[4] = decd_op[27];
assign pipe1_decd_mult_func[5] = !decd_op[4];
assign pipe1_decd_mult_func[6] = decd_mult_mula_muls;
assign pipe1_decd_mult_func[7] = decd_op[25] && !decd_op[4];
//==========================================================
// Full Decoder for function and operand prepare
//==========================================================
//----------------------------------------------------------
// Execution Units Define
//----------------------------------------------------------
parameter EU_WIDTH = 2;
parameter ALU = 2'b01;
parameter MULT = 2'b10;
parameter ALU_SEL = 21;
parameter NON_ALU = 21'h0;
parameter ADDER_ADD = 21'h000001;
parameter ADDER_ADDW = 21'h000002;
parameter ADDER_SUB = 21'h000004;
parameter ADDER_SUBW = 21'h000008;
parameter ADDER_SLT = 21'h000010;
parameter SHIFTER_SL = 21'h000020;
parameter SHIFTER_SR = 21'h000040;
parameter SHIFTER_SLW = 21'h000080;
parameter SHIFTER_SRW = 21'h000100;
parameter SHIFTER_EXT = 21'h000200;
parameter LOGIC_AND = 21'h000400;
parameter LOGIC_OR = 21'h000800;
parameter LOGIC_XOR = 21'h001000;
parameter LOGIC_LUI = 21'h002000;
parameter LOGIC_CLI = 21'h004000;
parameter MISC_MV = 21'h008000;
parameter MISC_TSTNBZ = 21'h010000;
parameter MISC_TST = 21'h020000;
parameter MISC_FF1 = 21'h040000;
parameter MISC_REV = 21'h080000;
parameter MISC_REVW = 21'h100000;
parameter ADDER_MAX = 21'h01;
parameter ADDER_MAXW = 21'h02;
parameter ADDER_MIN = 21'h04;
parameter ADDER_MINW = 21'h08;
parameter ADDER_ADDSL = 21'h20;
//----------------------------------------------------------
// Rename for Output
//----------------------------------------------------------
assign pipe1_decd_eu_sel[EU_WIDTH-1:0] = (decd_op[1:0] == 2'b11)
? decd_32_eu_sel[EU_WIDTH-1:0]
: decd_16_eu_sel[EU_WIDTH-1:0];
assign pipe1_decd_func[4:0] = (decd_op[1:0] == 2'b11)
? decd_32_func[4:0]
: decd_16_func[4:0];
assign pipe1_decd_sel[ALU_SEL-1:0] = (decd_op[1:0] == 2'b11)
? decd_32_sel[ALU_SEL-1:0]
: decd_16_sel[ALU_SEL-1:0];
//----------------------------------------------------------
// 16 bit FUll Decoder
//----------------------------------------------------------
// &CombBeg; @181
always @( decd_op[1:0]
or decd_op[15:5])
begin
//initialize decoded information value
casez({decd_op[15:10], decd_op[6:5], decd_op[1:0]})
//16-bits instructions decode logic
10'b000???_??00:begin //c.addi4spn
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00000;
decd_16_sel[ALU_SEL-1:0] = ADDER_ADD;
end
10'b000???_??01:begin //c.addi / c.nop
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00000;
decd_16_sel[ALU_SEL-1:0] = ADDER_ADD;
end
10'b001???_??01:begin //c.addiw
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = ADDER_ADDW;
end
10'b010???_??01:begin //c.li
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b10000;
decd_16_sel[ALU_SEL-1:0] = LOGIC_CLI;
end
10'b011???_??01:begin //c.addi16sp, c.lui
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = (decd_op[11:7] == 5'd2)
? 5'b00000 : 5'b01000;
decd_16_sel[ALU_SEL-1:0] = (decd_op[11:7] == 5'd2)
? ADDER_ADD : LOGIC_LUI;
end
10'b100?00_??01:begin //c.srli
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
10'b100?01_??01:begin //c.srai
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00011;
decd_16_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
10'b100?10_??01:begin //c.andi
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = LOGIC_AND;
end
10'b100011_0001:begin //c.sub
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00010;
decd_16_sel[ALU_SEL-1:0] = ADDER_SUB;
end
10'b100011_0101:begin //c.xor
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00100;
decd_16_sel[ALU_SEL-1:0] = LOGIC_XOR;
end
10'b100011_1001:begin //c.or
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00010;
decd_16_sel[ALU_SEL-1:0] = LOGIC_OR;
end
10'b100011_1101:begin //c.and
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = LOGIC_AND;
end
10'b100111_0001:begin //c.subw
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00011;
decd_16_sel[ALU_SEL-1:0] = ADDER_SUBW;
end
10'b100111_0101:begin //c.addw
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = ADDER_ADDW;
end
10'b000???_??10:begin //c.slli
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00000;
decd_16_sel[ALU_SEL-1:0] = SHIFTER_SL;
end
10'b1000??_??10:begin //c.mv
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00000;
decd_16_sel[ALU_SEL-1:0] = MISC_MV;
end
10'b1001??_??10:begin //c.add
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00000;
decd_16_sel[ALU_SEL-1:0] = ADDER_ADD;
end
default:begin //invalid instruction
decd_16_eu_sel[EU_WIDTH-1:0] = {EU_WIDTH{1'b0}};
decd_16_func[4:0] = 5'b0;
decd_16_sel[ALU_SEL-1:0] = NON_ALU;
end
endcase
// &CombEnd; @279
end
//----------------------------------------------------------
// 32 bits Full Decoder
//----------------------------------------------------------
// &CombBeg; @284
always @( decd_op[6:2]
or decd_op[31:25]
or decd_op[14:12])
begin
//initialize decoded information value
casez({decd_op[31:25], decd_op[14:12], decd_op[6:2]})
15'b??????????01101:begin //lui
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01000;
decd_32_sel[ALU_SEL-1:0] = LOGIC_LUI;
end
15'b???????00000100:begin //addi
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADD;
end
15'b???????01000100:begin //slti
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00110;
decd_32_sel[ALU_SEL-1:0] = ADDER_SLT;
end
15'b???????01100100:begin //sltiu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01110;
decd_32_sel[ALU_SEL-1:0] = ADDER_SLT;
end
15'b???????10000100:begin //xori
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = LOGIC_XOR;
end
15'b???????11000100:begin //ori
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = LOGIC_OR;
end
15'b???????11100100:begin //andi
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = LOGIC_AND;
end
15'b000000?00100100:begin //slli
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SL;
end
15'b000000?10100100:begin //srli
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b010000?10100100:begin //srai
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00011;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b???????00000110:begin //addiw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADDW;
end
15'b000000000100110:begin //slliw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SLW;
end
15'b000000010100110:begin //srliw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00101;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b010000010100110:begin //sraiw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00111;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b000000000001110:begin //addw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADDW;
end
15'b010000000001110:begin //subw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00011;
decd_32_sel[ALU_SEL-1:0] = ADDER_SUBW;
end
15'b000000000101110:begin //sllw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SLW;
end
15'b000000010101110:begin //srlw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00101;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b010000010101110:begin //sraw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00111;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b000000000001100:begin //add
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADD;
end
15'b010000000001100:begin //sub
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = ADDER_SUB;
end
15'b000000000101100:begin //sll
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SL;
end
15'b000000001001100:begin //slt
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00110;
decd_32_sel[ALU_SEL-1:0] = ADDER_SLT;
end
15'b010000001001100:begin //pseudo_min
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10100;
decd_32_sel[ALU_SEL-1:0] = ADDER_MIN;
end
15'b011000001001100:begin //pseudo_max
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10000;
decd_32_sel[ALU_SEL-1:0] = ADDER_MAX;
end
15'b010000001001110:begin //pseudo_minw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10101;
decd_32_sel[ALU_SEL-1:0] = ADDER_MINW;
end
15'b011000001001110:begin //pseudo_maxw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10001;
decd_32_sel[ALU_SEL-1:0] = ADDER_MAXW;
end
15'b000000001101100:begin //sltu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01110;
decd_32_sel[ALU_SEL-1:0] = ADDER_SLT;
end
15'b010000001101100:begin //pseudo_minu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b11100;
decd_32_sel[ALU_SEL-1:0] = ADDER_MIN;
end
15'b011000001101100:begin //pseudo_maxu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b11000;
decd_32_sel[ALU_SEL-1:0] = ADDER_MAX;
end
15'b010000001101110:begin //pseudo_minuw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b11101;
decd_32_sel[ALU_SEL-1:0] = ADDER_MINW;
end
15'b011000001101110:begin //pseudo_maxuw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b11001;
decd_32_sel[ALU_SEL-1:0] = ADDER_MAXW;
end
15'b000000010001100:begin //xor
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = LOGIC_XOR;
end
15'b000000010101100:begin //srl
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b010000010101100:begin //sra
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00011;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b000000011001100:begin //or
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = LOGIC_OR;
end
15'b000000011101100:begin //and
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = LOGIC_AND;
end
15'b000000100001100:begin //mul
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000100101100:begin //mulh
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000101001100:begin //mulhsu
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000101101100:begin //mulhu
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000100001110:begin //mulw
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b111101000010100:begin //fmv.h.x
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b111100000010100:begin //fmv.w.x
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b111100100010100:begin //fmv.d.x
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b00000??00100010:begin //addsl
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00111;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADDSL;
end
15'b000100?00100010:begin //srri
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10001;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b000101?00100010:begin //srriw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10101;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b100000000100010:begin //tstnbz
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = MISC_TSTNBZ;
end
15'b100000100100010:begin //rev
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01000;
decd_32_sel[ALU_SEL-1:0] = MISC_REV;
end
15'b100001000100010:begin //ff0
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00111;
decd_32_sel[ALU_SEL-1:0] = MISC_FF1;
end
15'b100001100100010:begin //ff1
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00110;
decd_32_sel[ALU_SEL-1:0] = MISC_FF1;
end
15'b100010?00100010:begin //tst
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00101;
decd_32_sel[ALU_SEL-1:0] = MISC_TST;
end
15'b100100000100010:begin //revw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01001;
decd_32_sel[ALU_SEL-1:0] = MISC_REVW;
end
15'b010000000100010:begin //mveqz
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = MISC_MV;
end
15'b010000100100010:begin //mvnez
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00011;
decd_32_sel[ALU_SEL-1:0] = MISC_MV;
end
15'b001000000100010:begin //mula
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b001000100100010:begin //muls
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b001001000100010:begin //mulaw
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b001001100100010:begin //mulsw
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b001010000100010:begin //mulah
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b001010100100010:begin //mulsh
decd_32_eu_sel[EU_WIDTH-1:0] = MULT;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b???????01000010:begin //ext
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01110;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_EXT;
end
15'b???????01100010:begin //extu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01010;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_EXT;
end
15'b010111110010101:begin //vmv.vx
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01000;
decd_32_sel[ALU_SEL-1:0] = MISC_MV;
end
15'b001101111010101:begin //vmv.s.x
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = MISC_MV;
end
default:begin //invalid instruction
decd_32_eu_sel[EU_WIDTH-1:0] = {EU_WIDTH{1'b0}};
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
endcase
// &CombEnd; @624
end
// &ModuleEnd; @626
endmodule |
module ct_idu_rf_pipe0_decd(
pipe0_decd_eu_sel,
pipe0_decd_expt_vld,
pipe0_decd_func,
pipe0_decd_imm,
pipe0_decd_opcode,
pipe0_decd_sel,
pipe0_decd_src1_imm
);
// &Ports; @28
input pipe0_decd_expt_vld;
input [31:0] pipe0_decd_opcode;
output [3 :0] pipe0_decd_eu_sel;
output [4 :0] pipe0_decd_func;
output [5 :0] pipe0_decd_imm;
output [20:0] pipe0_decd_sel;
output [63:0] pipe0_decd_src1_imm;
// &Regs; @29
reg [3 :0] decd_16_eu_sel;
reg [4 :0] decd_16_func;
reg [20:0] decd_16_sel;
reg [3 :0] decd_32_eu_sel;
reg [4 :0] decd_32_func;
reg [20:0] decd_32_sel;
reg [3 :0] pipe0_decd_eu_sel;
reg [4 :0] pipe0_decd_func;
reg [20:0] pipe0_decd_sel;
reg [63:0] pipe0_decd_src1_imm;
// &Wires; @30
wire [9 :0] decd_caddi4spn_imm;
wire [9 :0] decd_caddisp_imm;
wire decd_expt_vld;
wire [5 :0] decd_ext_offset;
wire [4 :0] decd_imm_sel;
wire [31:0] decd_op;
wire pipe0_decd_expt_vld;
wire [5 :0] pipe0_decd_imm;
wire [31:0] pipe0_decd_opcode;
//==========================================================
// Rename Input
//==========================================================
assign decd_op[31:0] = pipe0_decd_opcode[31:0];
assign decd_expt_vld = pipe0_decd_expt_vld;
//==========================================================
// Immediate
//==========================================================
//----------------------------------------------------------
// Immediate Selection
//----------------------------------------------------------
//32 bit imm20
assign decd_imm_sel[0] = (decd_op[6:0] == 7'b0110111)
|| (decd_op[6:0] == 7'b0010111);
//32 bit imm12
assign decd_imm_sel[1] = (decd_op[1:0] == 2'b11)
&& !decd_imm_sel[0];
//16 bit imm6
assign decd_imm_sel[2] = (decd_op[1:0] != 2'b11)
&& !decd_imm_sel[3]
&& !decd_imm_sel[4];
//16 bit caddisp
assign decd_imm_sel[3] = ({decd_op[15:13],decd_op[11:7],
decd_op[1:0]} == 10'b011_00010_01);
//16 bit caddi4spn
assign decd_imm_sel[4] = ({decd_op[15:13],decd_op[1:0]}
== 5'b000_00);
//----------------------------------------------------------
// Source 1 immediate
//----------------------------------------------------------
assign decd_caddisp_imm[9:0] = {decd_op[12],decd_op[4:3],
decd_op[5], decd_op[2],
decd_op[6], 4'b0};
assign decd_caddi4spn_imm[9:0] = {decd_op[10:7],decd_op[12:11],
decd_op[5], decd_op[6],2'b0};
// &CombBeg; @72
always @( decd_op[6:2]
or decd_imm_sel[4:0]
or decd_op[31:12]
or decd_caddi4spn_imm[9:0]
or decd_caddisp_imm[9:0])
begin
case(decd_imm_sel[4:0])
5'h01 : pipe0_decd_src1_imm[63:0] = {44'b0, decd_op[31:12]};
5'h02 : pipe0_decd_src1_imm[63:0] = {{52{decd_op[31]}},decd_op[31:20]};
5'h04 : pipe0_decd_src1_imm[63:0] = {{58{decd_op[12]}},
decd_op[12],decd_op[6:2]};
5'h08 : pipe0_decd_src1_imm[63:0] = {{54{decd_caddisp_imm[9]}},
decd_caddisp_imm[9:0]};
5'h10 : pipe0_decd_src1_imm[63:0] = {54'b0, decd_caddi4spn_imm[9:0]};
default: pipe0_decd_src1_imm[63:0] = {64{1'bx}};
endcase
// &CombEnd; @83
end
//----------------------------------------------------------
// Source immediate
//----------------------------------------------------------
assign decd_ext_offset[5:0] = decd_op[31:26] - decd_op[25:20];
assign pipe0_decd_imm[5:0] = decd_op[13] ? decd_ext_offset[5:0]
: {4'b0,decd_op[26:25]};
//==========================================================
// Full Decoder for function and operand prepare
//==========================================================
//----------------------------------------------------------
// Execution Units Define
//----------------------------------------------------------
parameter EU_WIDTH = 4;
parameter ALU = 4'b0001;
parameter DIV = 4'b0010;
parameter SPECIAL = 4'b0100;
parameter CP0 = 4'b1000;
parameter ALU_SEL = 21;
parameter NON_ALU = 21'h0;
parameter ADDER_ADD = 21'h000001;
parameter ADDER_ADDW = 21'h000002;
parameter ADDER_SUB = 21'h000004;
parameter ADDER_SUBW = 21'h000008;
parameter ADDER_SLT = 21'h000010;
parameter SHIFTER_SL = 21'h000020;
parameter SHIFTER_SR = 21'h000040;
parameter SHIFTER_SLW = 21'h000080;
parameter SHIFTER_SRW = 21'h000100;
parameter SHIFTER_EXT = 21'h000200;
parameter LOGIC_AND = 21'h000400;
parameter LOGIC_OR = 21'h000800;
parameter LOGIC_XOR = 21'h001000;
parameter LOGIC_LUI = 21'h002000;
parameter LOGIC_CLI = 21'h004000;
parameter MISC_MV = 21'h008000;
parameter MISC_TSTNBZ = 21'h010000;
parameter MISC_TST = 21'h020000;
parameter MISC_FF1 = 21'h040000;
parameter MISC_REV = 21'h080000;
parameter MISC_REVW = 21'h100000;
parameter ADDER_MAX = 21'h01;
parameter ADDER_MAXW = 21'h02;
parameter ADDER_MIN = 21'h04;
parameter ADDER_MINW = 21'h08;
parameter ADDER_ADDSL = 21'h20;
parameter SPECIAL_NOP = 5'b00000;
parameter SPECIAL_ECALL = 5'b00010;
parameter SPECIAL_EBREAK = 5'b00011;
parameter SPECIAL_AUIPC = 5'b00100;
parameter SPECIAL_PSEUDO_AUIPC = 5'b00101;
parameter SPECIAL_VSETVLI = 5'b00110;
parameter SPECIAL_VSETVL = 5'b00111;
//----------------------------------------------------------
// Rename for Output
//----------------------------------------------------------
// &CombBeg; @149
always @( decd_16_sel[20:0]
or decd_16_func[4:0]
or decd_expt_vld
or decd_32_sel[20:0]
or decd_32_func[4:0]
or decd_op[1:0]
or decd_16_eu_sel[3:0]
or decd_32_eu_sel[3:0])
begin
if(decd_expt_vld) begin
pipe0_decd_eu_sel[EU_WIDTH-1:0] = SPECIAL;
pipe0_decd_func[4:0] = SPECIAL_NOP;
pipe0_decd_sel[ALU_SEL-1:0] = NON_ALU;
end
else if(decd_op[1:0] == 2'b11) begin
pipe0_decd_eu_sel[EU_WIDTH-1:0] = decd_32_eu_sel[EU_WIDTH-1:0];
pipe0_decd_func[4:0] = decd_32_func[4:0];
pipe0_decd_sel[ALU_SEL-1:0] = decd_32_sel[ALU_SEL-1:0];
end
else begin
pipe0_decd_eu_sel[EU_WIDTH-1:0] = decd_16_eu_sel[EU_WIDTH-1:0];
pipe0_decd_func[4:0] = decd_16_func[4:0];
pipe0_decd_sel[ALU_SEL-1:0] = decd_16_sel[ALU_SEL-1:0];
end
// &CombEnd; @165
end
//----------------------------------------------------------
// 16 bit FUll Decoder
//----------------------------------------------------------
// &CombBeg; @170
always @( decd_op[15:0])
begin
//initialize decoded information value
casez({decd_op[15:10], decd_op[6:5], decd_op[1:0]})
//16-bits instructions decode logic
10'b000???_??00:begin //c.addi4spn
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00000;
decd_16_sel[ALU_SEL-1:0] = ADDER_ADD;
end
10'b000???_??01:begin //c.addi / c.nop
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00000;
decd_16_sel[ALU_SEL-1:0] = ADDER_ADD;
end
10'b001???_??01:begin //c.addiw
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = ADDER_ADDW;
end
10'b010???_??01:begin //c.li
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b10000;
decd_16_sel[ALU_SEL-1:0] = LOGIC_CLI;
end
10'b011???_??01:begin //c.addi16sp, c.lui
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = (decd_op[11:7] == 5'd2)
? 5'b00000 : 5'b01000;
decd_16_sel[ALU_SEL-1:0] = (decd_op[11:7] == 5'd2)
? ADDER_ADD : LOGIC_LUI;
end
10'b100?00_??01:begin //c.srli
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
10'b100?01_??01:begin //c.srai
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00011;
decd_16_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
10'b100?10_??01:begin //c.andi
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = LOGIC_AND;
end
10'b100011_0001:begin //c.sub
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00010;
decd_16_sel[ALU_SEL-1:0] = ADDER_SUB;
end
10'b100011_0101:begin //c.xor
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00100;
decd_16_sel[ALU_SEL-1:0] = LOGIC_XOR;
end
10'b100011_1001:begin //c.or
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00010;
decd_16_sel[ALU_SEL-1:0] = LOGIC_OR;
end
10'b100011_1101:begin //c.and
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = LOGIC_AND;
end
10'b100111_0001:begin //c.subw
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00011;
decd_16_sel[ALU_SEL-1:0] = ADDER_SUBW;
end
10'b100111_0101:begin //c.addw
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00001;
decd_16_sel[ALU_SEL-1:0] = ADDER_ADDW;
end
10'b000???_??10:begin //c.slli
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00000;
decd_16_sel[ALU_SEL-1:0] = SHIFTER_SL;
end
10'b1000??_??10:begin //c.mv
decd_16_eu_sel[EU_WIDTH-1:0] = ALU;
decd_16_func[4:0] = 5'b00000;
decd_16_sel[ALU_SEL-1:0] = MISC_MV;
end
10'b1001??_??10:begin //c.add //c.ebreak
decd_16_eu_sel[EU_WIDTH-1:0] = (decd_op[6:2] == 5'b0)
? SPECIAL : ALU;
decd_16_func[4:0] = (decd_op[6:2] == 5'b0)
? SPECIAL_EBREAK : 5'b00000;
decd_16_sel[ALU_SEL-1:0] = (decd_op[6:2] == 5'b0)
? NON_ALU : ADDER_ADD;
end
default:begin //invalid instruction
decd_16_eu_sel[EU_WIDTH-1:0] = {EU_WIDTH{1'b0}};
decd_16_func[4:0] = 5'b0;
decd_16_sel[ALU_SEL-1:0] = NON_ALU;
end
endcase
// &CombEnd; @271
end
//----------------------------------------------------------
// 32 bits Full Decoder
//----------------------------------------------------------
// &CombBeg; @276
always @( decd_op[6:2]
or decd_op[31:25]
or decd_op[20]
or decd_op[14:12])
begin
//initialize decoded information value
casez({decd_op[31:25], decd_op[14:12], decd_op[6:2]})
15'b??????????01101:begin //lui
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01000;
decd_32_sel[ALU_SEL-1:0] = LOGIC_LUI;
end
15'b??????????00101:begin //auipc
decd_32_eu_sel[EU_WIDTH-1:0] = SPECIAL;
decd_32_func[4:0] = SPECIAL_AUIPC;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b??????????00111:begin //pseudo auipc
decd_32_eu_sel[EU_WIDTH-1:0] = SPECIAL;
decd_32_func[4:0] = SPECIAL_PSEUDO_AUIPC;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b???????00000100:begin //addi
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADD;
end
15'b???????01000100:begin //slti
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00110;
decd_32_sel[ALU_SEL-1:0] = ADDER_SLT;
end
15'b???????01100100:begin //sltiu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01110;
decd_32_sel[ALU_SEL-1:0] = ADDER_SLT;
end
15'b???????10000100:begin //xori
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = LOGIC_XOR;
end
15'b???????11000100:begin //ori
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = LOGIC_OR;
end
15'b???????11100100:begin //andi
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = LOGIC_AND;
end
15'b000000?00100100:begin //slli
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SL;
end
15'b000000?10100100:begin //srli
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b010000?10100100:begin //srai
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00011;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b???????00000110:begin //addiw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADDW;
end
15'b000000000100110:begin //slliw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SLW;
end
15'b000000010100110:begin //srliw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00101;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b010000010100110:begin //sraiw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00111;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b000000000001110:begin //addw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADDW;
end
15'b010000000001110:begin //subw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00011;
decd_32_sel[ALU_SEL-1:0] = ADDER_SUBW;
end
15'b000000000101110:begin //sllw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SLW;
end
15'b000000010101110:begin //srlw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00101;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b010000010101110:begin //sraw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00111;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b000000000001100:begin //add
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADD;
end
15'b010000000001100:begin //sub
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = ADDER_SUB;
end
15'b000000000101100:begin //sll
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00000;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SL;
end
15'b000000001001100:begin //slt
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00110;
decd_32_sel[ALU_SEL-1:0] = ADDER_SLT;
end
15'b010000001001100:begin //pseudo_min
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10100;
decd_32_sel[ALU_SEL-1:0] = ADDER_MIN;
end
15'b011000001001100:begin //pseudo_max
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10000;
decd_32_sel[ALU_SEL-1:0] = ADDER_MAX;
end
15'b010000001001110:begin //pseudo_minw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10101;
decd_32_sel[ALU_SEL-1:0] = ADDER_MINW;
end
15'b011000001001110:begin //pseudo_maxw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10001;
decd_32_sel[ALU_SEL-1:0] = ADDER_MAXW;
end
15'b000000001101100:begin //sltu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01110;
decd_32_sel[ALU_SEL-1:0] = ADDER_SLT;
end
15'b010000001101100:begin //pseudo_minu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b11100;
decd_32_sel[ALU_SEL-1:0] = ADDER_MIN;
end
15'b011000001101100:begin //pseudo_maxu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b11000;
decd_32_sel[ALU_SEL-1:0] = ADDER_MAX;
end
15'b010000001101110:begin //pseudo_minuw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b11101;
decd_32_sel[ALU_SEL-1:0] = ADDER_MINW;
end
15'b011000001101110:begin //pseudo_maxuw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b11001;
decd_32_sel[ALU_SEL-1:0] = ADDER_MAXW;
end
15'b000000010001100:begin //xor
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = LOGIC_XOR;
end
15'b000000010101100:begin //srl
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b010000010101100:begin //sra
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00011;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b000000011001100:begin //or
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = LOGIC_OR;
end
15'b000000011101100:begin //and
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = LOGIC_AND;
end
15'b000000110001100:begin //div
decd_32_eu_sel[EU_WIDTH-1:0] = DIV;
decd_32_func[4:0] = 5'b00101;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000110101100:begin //divu
decd_32_eu_sel[EU_WIDTH-1:0] = DIV;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000111001100:begin //rem
decd_32_eu_sel[EU_WIDTH-1:0] = DIV;
decd_32_func[4:0] = 5'b01001;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000111101100:begin //remu
decd_32_eu_sel[EU_WIDTH-1:0] = DIV;
decd_32_func[4:0] = 5'b01000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000110001110:begin //divw
decd_32_eu_sel[EU_WIDTH-1:0] = DIV;
decd_32_func[4:0] = 5'b00111;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000110101110:begin //divuw
decd_32_eu_sel[EU_WIDTH-1:0] = DIV;
decd_32_func[4:0] = 5'b00110;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000111001110:begin //remw
decd_32_eu_sel[EU_WIDTH-1:0] = DIV;
decd_32_func[4:0] = 5'b01011;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000111101110:begin //remuw
decd_32_eu_sel[EU_WIDTH-1:0] = DIV;
decd_32_func[4:0] = 5'b01010;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000000000011100:begin //ecall ebreak
decd_32_eu_sel[EU_WIDTH-1:0] = SPECIAL;
decd_32_func[4:0] = (decd_op[20])
? SPECIAL_EBREAK : SPECIAL_ECALL;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b000100000011100:begin //sret wfi
//deal in fence
decd_32_eu_sel[EU_WIDTH-1:0] = CP0;
decd_32_func[4:0] = (decd_op[20])
? 5'b01001 :5'b01000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b001100000011100:begin //mret
//deal in fence
decd_32_eu_sel[EU_WIDTH-1:0] = CP0;
decd_32_func[4:0] = 5'b01010;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b???????00111100:begin //csrrw
//deal in fence
decd_32_eu_sel[EU_WIDTH-1:0] = CP0;
decd_32_func[4:0] = 5'b10000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b???????01011100:begin //csrrs
//deal in fence
decd_32_eu_sel[EU_WIDTH-1:0] = CP0;
decd_32_func[4:0] = 5'b10001;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b???????01111100:begin //csrrc
//deal in fence
decd_32_eu_sel[EU_WIDTH-1:0] = CP0;
decd_32_func[4:0] = 5'b10010;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b???????10111100:begin //csrwi
//deal in fence
decd_32_eu_sel[EU_WIDTH-1:0] = CP0;
decd_32_func[4:0] = 5'b10011;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b???????11011100:begin //csrsi
//deal in fence
decd_32_eu_sel[EU_WIDTH-1:0] = CP0;
decd_32_func[4:0] = 5'b10100;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b???????11111100:begin //csrci
//deal in fence
decd_32_eu_sel[EU_WIDTH-1:0] = CP0;
decd_32_func[4:0] = 5'b10101;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b111101000010100:begin //fmv.h.x
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10000;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b111100000010100:begin //fmv.w.x
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00001;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b111100100010100:begin //fmv.d.x
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b00000??00100010:begin //addsl
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00111;
decd_32_sel[ALU_SEL-1:0] = ADDER_ADDSL;
end
15'b000100?00100010:begin //srri
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10001;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SR;
end
15'b000101?00100010:begin //srriw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b10101;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_SRW;
end
15'b100000000100010:begin //tstnbz
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = MISC_TSTNBZ;
end
15'b100000100100010:begin //rev
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01000;
decd_32_sel[ALU_SEL-1:0] = MISC_REV;
end
15'b100001000100010:begin //ff0
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00111;
decd_32_sel[ALU_SEL-1:0] = MISC_FF1;
end
15'b100001100100010:begin //ff1
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00110;
decd_32_sel[ALU_SEL-1:0] = MISC_FF1;
end
15'b100010?00100010:begin //tst
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00101;
decd_32_sel[ALU_SEL-1:0] = MISC_TST;
end
15'b100100000100010:begin //revw
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01001;
decd_32_sel[ALU_SEL-1:0] = MISC_REVW;
end
15'b010000000100010:begin //mveqz
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00010;
decd_32_sel[ALU_SEL-1:0] = MISC_MV;
end
15'b010000100100010:begin //mvnez
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00011;
decd_32_sel[ALU_SEL-1:0] = MISC_MV;
end
15'b???????01000010:begin //ext
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01110;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_EXT;
end
15'b???????01100010:begin //extu
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01010;
decd_32_sel[ALU_SEL-1:0] = SHIFTER_EXT;
end
15'b010111110010101:begin //vmv.vx
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b01000;
decd_32_sel[ALU_SEL-1:0] = MISC_MV;
end
15'b001101111010101:begin //vmv.s.x
decd_32_eu_sel[EU_WIDTH-1:0] = ALU;
decd_32_func[4:0] = 5'b00100;
decd_32_sel[ALU_SEL-1:0] = MISC_MV;
end
15'b0??????11110101:begin //vsetvli
decd_32_eu_sel[EU_WIDTH-1:0] = SPECIAL;
decd_32_func[4:0] = SPECIAL_VSETVLI;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
15'b100000011110101:begin //vsetvl
decd_32_eu_sel[EU_WIDTH-1:0] = SPECIAL;
decd_32_func[4:0] = SPECIAL_VSETVL;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
default:begin //invalid instruction
decd_32_eu_sel[EU_WIDTH-1:0] = SPECIAL;
decd_32_func[4:0] = SPECIAL_NOP;
decd_32_sel[ALU_SEL-1:0] = NON_ALU;
end
endcase
// &CombEnd; @675
end
// &ModuleEnd; @677
endmodule |
module ct_idu_is_biq_entry(
cp0_idu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_biq_rf_pop_vld,
ctrl_xx_rf_pipe0_preg_lch_vld_dupx,
ctrl_xx_rf_pipe1_preg_lch_vld_dupx,
dp_biq_rf_rdy_clr,
dp_xx_rf_pipe0_dst_preg_dupx,
dp_xx_rf_pipe1_dst_preg_dupx,
forever_cpuclk,
iu_idu_div_inst_vld,
iu_idu_div_preg_dupx,
iu_idu_ex2_pipe0_wb_preg_dupx,
iu_idu_ex2_pipe0_wb_preg_vld_dupx,
iu_idu_ex2_pipe1_mult_inst_vld_dupx,
iu_idu_ex2_pipe1_preg_dupx,
iu_idu_ex2_pipe1_wb_preg_dupx,
iu_idu_ex2_pipe1_wb_preg_vld_dupx,
lsu_idu_ag_pipe3_load_inst_vld,
lsu_idu_ag_pipe3_preg_dupx,
lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx,
lsu_idu_dc_pipe3_load_inst_vld_dupx,
lsu_idu_dc_pipe3_preg_dupx,
lsu_idu_wb_pipe3_wb_preg_dupx,
lsu_idu_wb_pipe3_wb_preg_vld_dupx,
pad_yy_icg_scan_en,
rtu_idu_flush_fe,
rtu_idu_flush_is,
vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx,
vfpu_idu_ex1_pipe6_preg_dupx,
vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx,
vfpu_idu_ex1_pipe7_preg_dupx,
x_agevec,
x_alu0_reg_fwd_vld,
x_alu1_reg_fwd_vld,
x_create_agevec,
x_create_data,
x_create_dp_en,
x_create_en,
x_create_frz,
x_create_gateclk_en,
x_frz_clr,
x_issue_en,
x_pop_cur_entry,
x_pop_other_entry,
x_rdy,
x_read_data,
x_vld,
x_vld_with_frz
);
// &Ports; @28
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_biq_rf_pop_vld;
input ctrl_xx_rf_pipe0_preg_lch_vld_dupx;
input ctrl_xx_rf_pipe1_preg_lch_vld_dupx;
input [1 :0] dp_biq_rf_rdy_clr;
input [6 :0] dp_xx_rf_pipe0_dst_preg_dupx;
input [6 :0] dp_xx_rf_pipe1_dst_preg_dupx;
input forever_cpuclk;
input iu_idu_div_inst_vld;
input [6 :0] iu_idu_div_preg_dupx;
input [6 :0] iu_idu_ex2_pipe0_wb_preg_dupx;
input iu_idu_ex2_pipe0_wb_preg_vld_dupx;
input iu_idu_ex2_pipe1_mult_inst_vld_dupx;
input [6 :0] iu_idu_ex2_pipe1_preg_dupx;
input [6 :0] iu_idu_ex2_pipe1_wb_preg_dupx;
input iu_idu_ex2_pipe1_wb_preg_vld_dupx;
input lsu_idu_ag_pipe3_load_inst_vld;
input [6 :0] lsu_idu_ag_pipe3_preg_dupx;
input lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx;
input lsu_idu_dc_pipe3_load_inst_vld_dupx;
input [6 :0] lsu_idu_dc_pipe3_preg_dupx;
input [6 :0] lsu_idu_wb_pipe3_wb_preg_dupx;
input lsu_idu_wb_pipe3_wb_preg_vld_dupx;
input pad_yy_icg_scan_en;
input rtu_idu_flush_fe;
input rtu_idu_flush_is;
input vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe6_preg_dupx;
input vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe7_preg_dupx;
input [1 :0] x_alu0_reg_fwd_vld;
input [1 :0] x_alu1_reg_fwd_vld;
input [10:0] x_create_agevec;
input [81:0] x_create_data;
input x_create_dp_en;
input x_create_en;
input x_create_frz;
input x_create_gateclk_en;
input x_frz_clr;
input x_issue_en;
input x_pop_cur_entry;
input [10:0] x_pop_other_entry;
output [10:0] x_agevec;
output x_rdy;
output [81:0] x_read_data;
output x_vld;
output x_vld_with_frz;
// &Regs; @29
reg [10:0] agevec;
reg frz;
reg [6 :0] iid;
reg length;
reg [31:0] opcode;
reg pcall;
reg [4 :0] pid;
reg rts;
reg src0_vld;
reg src1_vld;
reg [7 :0] vl;
reg vld;
reg [1 :0] vlmul;
reg [2 :0] vsew;
// &Wires; @30
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire create_clk;
wire create_clk_en;
wire [9 :0] create_src0_data;
wire create_src0_gateclk_en;
wire [9 :0] create_src1_data;
wire create_src1_gateclk_en;
wire ctrl_biq_rf_pop_vld;
wire ctrl_xx_rf_pipe0_preg_lch_vld_dupx;
wire ctrl_xx_rf_pipe1_preg_lch_vld_dupx;
wire [1 :0] dp_biq_rf_rdy_clr;
wire [6 :0] dp_xx_rf_pipe0_dst_preg_dupx;
wire [6 :0] dp_xx_rf_pipe1_dst_preg_dupx;
wire entry_clk;
wire entry_clk_en;
wire forever_cpuclk;
wire gateclk_entry_vld;
wire iu_idu_div_inst_vld;
wire [6 :0] iu_idu_div_preg_dupx;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg_dupx;
wire iu_idu_ex2_pipe0_wb_preg_vld_dupx;
wire iu_idu_ex2_pipe1_mult_inst_vld_dupx;
wire [6 :0] iu_idu_ex2_pipe1_preg_dupx;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg_dupx;
wire iu_idu_ex2_pipe1_wb_preg_vld_dupx;
wire lsu_idu_ag_pipe3_load_inst_vld;
wire [6 :0] lsu_idu_ag_pipe3_preg_dupx;
wire lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx;
wire lsu_idu_dc_pipe3_load_inst_vld_dupx;
wire [6 :0] lsu_idu_dc_pipe3_preg_dupx;
wire [6 :0] lsu_idu_wb_pipe3_wb_preg_dupx;
wire lsu_idu_wb_pipe3_wb_preg_vld_dupx;
wire pad_yy_icg_scan_en;
wire [11:0] read_src0_data;
wire [11:0] read_src1_data;
wire rtu_idu_flush_fe;
wire rtu_idu_flush_is;
wire src0_rdy_clr;
wire src0_rdy_for_issue;
wire src1_rdy_clr;
wire src1_rdy_for_issue;
wire vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe6_preg_dupx;
wire vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe7_preg_dupx;
wire [10:0] x_agevec;
wire [1 :0] x_alu0_reg_fwd_vld;
wire [1 :0] x_alu1_reg_fwd_vld;
wire [10:0] x_create_agevec;
wire [81:0] x_create_data;
wire x_create_dp_en;
wire x_create_en;
wire x_create_frz;
wire x_create_gateclk_en;
wire x_frz_clr;
wire x_issue_en;
wire x_pop_cur_entry;
wire [10:0] x_pop_other_entry;
wire x_rdy;
wire [81:0] x_read_data;
wire x_vld;
wire x_vld_with_frz;
//==========================================================
// Parameters
//==========================================================
//----------------------------------------------------------
// BIQ Parameters
//----------------------------------------------------------
parameter BIQ_WIDTH = 82;
parameter BIQ_VL = 81;
parameter BIQ_VSEW = 73;
parameter BIQ_VLMUL = 70;
parameter BIQ_PCALL = 68;
parameter BIQ_RTS = 67;
parameter BIQ_PID = 66;
parameter BIQ_LENGTH = 61;
parameter BIQ_SRC1_LSU_MATCH = 60;
parameter BIQ_SRC1_DATA = 59;
parameter BIQ_SRC1_PREG = 59;
parameter BIQ_SRC1_WB = 52;
parameter BIQ_SRC1_RDY = 51;
parameter BIQ_SRC0_LSU_MATCH = 50;
parameter BIQ_SRC0_DATA = 49;
parameter BIQ_SRC0_PREG = 49;
parameter BIQ_SRC0_WB = 42;
parameter BIQ_SRC0_RDY = 41;
parameter BIQ_SRC1_VLD = 40;
parameter BIQ_SRC0_VLD = 39;
parameter BIQ_IID = 38;
parameter BIQ_OPCODE = 31;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign entry_clk_en = x_create_gateclk_en || vld;
// &Instance("gated_clk_cell", "x_entry_gated_clk"); @67
gated_clk_cell x_entry_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (entry_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @68
// .external_en (1'b0), @69
// .global_en (cp0_yy_clk_en), @70
// .module_en (cp0_idu_icg_en), @71
// .local_en (entry_clk_en), @72
// .clk_out (entry_clk)); @73
assign create_clk_en = x_create_gateclk_en;
// &Instance("gated_clk_cell", "x_create_gated_clk"); @76
gated_clk_cell x_create_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (create_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (create_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @77
// .external_en (1'b0), @78
// .global_en (cp0_yy_clk_en), @79
// .module_en (cp0_idu_icg_en), @80
// .local_en (create_clk_en), @81
// .clk_out (create_clk)); @82
//if entry is not valid, shut down dep info clock
assign gateclk_entry_vld = vld;
//==========================================================
// Create and Read Bus
//==========================================================
//force create and read bus width
// &Force("bus","x_create_data",BIQ_WIDTH-1,0); @91
// &Force("bus","x_read_data",BIQ_WIDTH-1,0); @92
// &Force("output","x_read_data"); @93
//==========================================================
// Entry Valid
//==========================================================
assign x_vld = vld;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vld <= 1'b0;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
vld <= 1'b0;
else if(x_create_en)
vld <= 1'b1;
else if(ctrl_biq_rf_pop_vld && x_pop_cur_entry)
vld <= 1'b0;
else
vld <= vld;
end
//==========================================================
// Freeze
//==========================================================
assign x_vld_with_frz = vld && !frz;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
frz <= 1'b0;
else if(x_create_en)
frz <= x_create_frz;
else if(x_frz_clr)
frz <= 1'b0;
else if(x_issue_en)
frz <= 1'b1;
else
frz <= frz;
end
//==========================================================
// Age Vector
//==========================================================
assign x_agevec[10:0] = agevec[10:0];
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
agevec[10:0] <= 11'b0;
else if(x_create_en)
agevec[10:0] <= x_create_agevec[10:0];
else if(ctrl_biq_rf_pop_vld)
agevec[10:0] <= agevec[10:0] & ~x_pop_other_entry[10:0];
else
agevec[10:0] <= agevec[10:0];
end
//==========================================================
// Instruction Information
//==========================================================
always @(posedge create_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
opcode[31:0] <= 32'b0;
iid[6:0] <= 7'b0;
src0_vld <= 1'b0;
src1_vld <= 1'b0;
length <= 1'b0;
rts <= 1'b0;
pcall <= 1'b0;
pid[4:0] <= 5'b0;
vlmul[1:0] <= 2'b0;
vsew[2:0] <= 3'b0;
vl[7:0] <= 8'b0;
end
else if(x_create_dp_en) begin
opcode[31:0] <= x_create_data[BIQ_OPCODE:BIQ_OPCODE-31];
iid[6:0] <= x_create_data[BIQ_IID:BIQ_IID-6];
src0_vld <= x_create_data[BIQ_SRC0_VLD];
src1_vld <= x_create_data[BIQ_SRC1_VLD];
length <= x_create_data[BIQ_LENGTH];
rts <= x_create_data[BIQ_RTS];
pcall <= x_create_data[BIQ_PCALL];
pid[4:0] <= x_create_data[BIQ_PID:BIQ_PID-4];
vlmul[1:0] <= x_create_data[BIQ_VLMUL:BIQ_VLMUL-1];
vsew[2:0] <= x_create_data[BIQ_VSEW:BIQ_VSEW-2];
vl[7:0] <= x_create_data[BIQ_VL:BIQ_VL-7];
end
else begin
opcode[31:0] <= opcode[31:0];
iid[6:0] <= iid[6:0];
src0_vld <= src0_vld;
src1_vld <= src1_vld;
length <= length;
rts <= rts;
pcall <= pcall;
pid[4:0] <= pid[4:0];
vlmul[1:0] <= vlmul[1:0];
vsew[2:0] <= vsew[2:0];
vl[7:0] <= vl[7:0];
end
end
//rename for read output
assign x_read_data[BIQ_OPCODE:BIQ_OPCODE-31] = opcode[31:0];
assign x_read_data[BIQ_IID:BIQ_IID-6] = iid[6:0];
assign x_read_data[BIQ_SRC0_VLD] = src0_vld;
assign x_read_data[BIQ_SRC1_VLD] = src1_vld;
assign x_read_data[BIQ_LENGTH] = length;
assign x_read_data[BIQ_RTS] = rts;
assign x_read_data[BIQ_PCALL] = pcall;
assign x_read_data[BIQ_PID:BIQ_PID-4] = pid[4:0];
assign x_read_data[BIQ_VLMUL:BIQ_VLMUL-1] = vlmul[1:0];
assign x_read_data[BIQ_VSEW:BIQ_VSEW-2] = vsew[2:0];
assign x_read_data[BIQ_VL:BIQ_VL-7] = vl[7:0];
//==========================================================
// Source Dependency Information
//==========================================================
assign src0_rdy_clr = x_frz_clr && dp_biq_rf_rdy_clr[0];
assign src1_rdy_clr = x_frz_clr && dp_biq_rf_rdy_clr[1];
//------------------------source 0--------------------------
assign create_src0_gateclk_en = x_create_gateclk_en && x_create_data[BIQ_SRC0_VLD];
assign create_src0_data[9] = x_create_data[BIQ_SRC0_LSU_MATCH];
assign create_src0_data[8:0] = x_create_data[BIQ_SRC0_DATA:BIQ_SRC0_DATA-8];
// &Instance("ct_idu_dep_reg_entry", "x_ct_idu_is_biq_src0_entry"); @216
ct_idu_dep_reg_entry x_ct_idu_is_biq_src0_entry (
.alu0_reg_fwd_vld (x_alu0_reg_fwd_vld[0] ),
.alu1_reg_fwd_vld (x_alu1_reg_fwd_vld[0] ),
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ctrl_xx_rf_pipe0_preg_lch_vld_dupx (ctrl_xx_rf_pipe0_preg_lch_vld_dupx ),
.ctrl_xx_rf_pipe1_preg_lch_vld_dupx (ctrl_xx_rf_pipe1_preg_lch_vld_dupx ),
.dp_xx_rf_pipe0_dst_preg_dupx (dp_xx_rf_pipe0_dst_preg_dupx ),
.dp_xx_rf_pipe1_dst_preg_dupx (dp_xx_rf_pipe1_dst_preg_dupx ),
.forever_cpuclk (forever_cpuclk ),
.gateclk_entry_vld (gateclk_entry_vld ),
.iu_idu_div_inst_vld (iu_idu_div_inst_vld ),
.iu_idu_div_preg_dupx (iu_idu_div_preg_dupx ),
.iu_idu_ex2_pipe0_wb_preg_dupx (iu_idu_ex2_pipe0_wb_preg_dupx ),
.iu_idu_ex2_pipe0_wb_preg_vld_dupx (iu_idu_ex2_pipe0_wb_preg_vld_dupx ),
.iu_idu_ex2_pipe1_mult_inst_vld_dupx (iu_idu_ex2_pipe1_mult_inst_vld_dupx ),
.iu_idu_ex2_pipe1_preg_dupx (iu_idu_ex2_pipe1_preg_dupx ),
.iu_idu_ex2_pipe1_wb_preg_dupx (iu_idu_ex2_pipe1_wb_preg_dupx ),
.iu_idu_ex2_pipe1_wb_preg_vld_dupx (iu_idu_ex2_pipe1_wb_preg_vld_dupx ),
.lsu_idu_ag_pipe3_load_inst_vld (lsu_idu_ag_pipe3_load_inst_vld ),
.lsu_idu_ag_pipe3_preg_dupx (lsu_idu_ag_pipe3_preg_dupx ),
.lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx (lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx),
.lsu_idu_dc_pipe3_load_inst_vld_dupx (lsu_idu_dc_pipe3_load_inst_vld_dupx ),
.lsu_idu_dc_pipe3_preg_dupx (lsu_idu_dc_pipe3_preg_dupx ),
.lsu_idu_wb_pipe3_wb_preg_dupx (lsu_idu_wb_pipe3_wb_preg_dupx ),
.lsu_idu_wb_pipe3_wb_preg_vld_dupx (lsu_idu_wb_pipe3_wb_preg_vld_dupx ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_idu_flush_fe (rtu_idu_flush_fe ),
.rtu_idu_flush_is (rtu_idu_flush_is ),
.vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx (vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx ),
.vfpu_idu_ex1_pipe6_preg_dupx (vfpu_idu_ex1_pipe6_preg_dupx ),
.vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx (vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx ),
.vfpu_idu_ex1_pipe7_preg_dupx (vfpu_idu_ex1_pipe7_preg_dupx ),
.x_create_data (create_src0_data[9:0] ),
.x_gateclk_idx_write_en (create_src0_gateclk_en ),
.x_gateclk_write_en (x_create_gateclk_en ),
.x_rdy_clr (src0_rdy_clr ),
.x_read_data (read_src0_data[11:0] ),
.x_write_en (x_create_dp_en )
);
// &Connect(.gateclk_entry_vld (gateclk_entry_vld), @217
// .alu0_reg_fwd_vld (x_alu0_reg_fwd_vld[0]), @218
// .alu1_reg_fwd_vld (x_alu1_reg_fwd_vld[0]), @219
// .x_write_en (x_create_dp_en), @220
// .x_gateclk_write_en (x_create_gateclk_en), @221
// .x_gateclk_idx_write_en (create_src0_gateclk_en), @222
// .x_create_data (create_src0_data[9:0]), @223
// .x_read_data (read_src0_data[11:0]), @224
// .x_rdy_clr (src0_rdy_clr) @225
// ); @226
assign x_read_data[BIQ_SRC0_WB] = read_src0_data[1];
assign x_read_data[BIQ_SRC0_PREG:BIQ_SRC0_PREG-6] = read_src0_data[8:2];
assign src0_rdy_for_issue = read_src0_data[9];
assign x_read_data[BIQ_SRC0_RDY] = 1'b0;
assign x_read_data[BIQ_SRC0_LSU_MATCH] = 1'b0;
//------------------------source 1--------------------------
assign create_src1_gateclk_en = x_create_gateclk_en && x_create_data[BIQ_SRC1_VLD];
assign create_src1_data[9] = x_create_data[BIQ_SRC1_LSU_MATCH];
assign create_src1_data[8:0] = x_create_data[BIQ_SRC1_DATA:BIQ_SRC1_DATA-8];
// &Instance("ct_idu_dep_reg_entry", "x_ct_idu_is_biq_src1_entry"); @237
ct_idu_dep_reg_entry x_ct_idu_is_biq_src1_entry (
.alu0_reg_fwd_vld (x_alu0_reg_fwd_vld[1] ),
.alu1_reg_fwd_vld (x_alu1_reg_fwd_vld[1] ),
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ctrl_xx_rf_pipe0_preg_lch_vld_dupx (ctrl_xx_rf_pipe0_preg_lch_vld_dupx ),
.ctrl_xx_rf_pipe1_preg_lch_vld_dupx (ctrl_xx_rf_pipe1_preg_lch_vld_dupx ),
.dp_xx_rf_pipe0_dst_preg_dupx (dp_xx_rf_pipe0_dst_preg_dupx ),
.dp_xx_rf_pipe1_dst_preg_dupx (dp_xx_rf_pipe1_dst_preg_dupx ),
.forever_cpuclk (forever_cpuclk ),
.gateclk_entry_vld (gateclk_entry_vld ),
.iu_idu_div_inst_vld (iu_idu_div_inst_vld ),
.iu_idu_div_preg_dupx (iu_idu_div_preg_dupx ),
.iu_idu_ex2_pipe0_wb_preg_dupx (iu_idu_ex2_pipe0_wb_preg_dupx ),
.iu_idu_ex2_pipe0_wb_preg_vld_dupx (iu_idu_ex2_pipe0_wb_preg_vld_dupx ),
.iu_idu_ex2_pipe1_mult_inst_vld_dupx (iu_idu_ex2_pipe1_mult_inst_vld_dupx ),
.iu_idu_ex2_pipe1_preg_dupx (iu_idu_ex2_pipe1_preg_dupx ),
.iu_idu_ex2_pipe1_wb_preg_dupx (iu_idu_ex2_pipe1_wb_preg_dupx ),
.iu_idu_ex2_pipe1_wb_preg_vld_dupx (iu_idu_ex2_pipe1_wb_preg_vld_dupx ),
.lsu_idu_ag_pipe3_load_inst_vld (lsu_idu_ag_pipe3_load_inst_vld ),
.lsu_idu_ag_pipe3_preg_dupx (lsu_idu_ag_pipe3_preg_dupx ),
.lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx (lsu_idu_dc_pipe3_load_fwd_inst_vld_dupx),
.lsu_idu_dc_pipe3_load_inst_vld_dupx (lsu_idu_dc_pipe3_load_inst_vld_dupx ),
.lsu_idu_dc_pipe3_preg_dupx (lsu_idu_dc_pipe3_preg_dupx ),
.lsu_idu_wb_pipe3_wb_preg_dupx (lsu_idu_wb_pipe3_wb_preg_dupx ),
.lsu_idu_wb_pipe3_wb_preg_vld_dupx (lsu_idu_wb_pipe3_wb_preg_vld_dupx ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_idu_flush_fe (rtu_idu_flush_fe ),
.rtu_idu_flush_is (rtu_idu_flush_is ),
.vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx (vfpu_idu_ex1_pipe6_mfvr_inst_vld_dupx ),
.vfpu_idu_ex1_pipe6_preg_dupx (vfpu_idu_ex1_pipe6_preg_dupx ),
.vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx (vfpu_idu_ex1_pipe7_mfvr_inst_vld_dupx ),
.vfpu_idu_ex1_pipe7_preg_dupx (vfpu_idu_ex1_pipe7_preg_dupx ),
.x_create_data (create_src1_data[9:0] ),
.x_gateclk_idx_write_en (create_src1_gateclk_en ),
.x_gateclk_write_en (x_create_gateclk_en ),
.x_rdy_clr (src1_rdy_clr ),
.x_read_data (read_src1_data[11:0] ),
.x_write_en (x_create_dp_en )
);
// &Connect(.gateclk_entry_vld (gateclk_entry_vld), @238
// .alu0_reg_fwd_vld (x_alu0_reg_fwd_vld[1]), @239
// .alu1_reg_fwd_vld (x_alu1_reg_fwd_vld[1]), @240
// .x_write_en (x_create_dp_en), @241
// .x_gateclk_write_en (x_create_gateclk_en), @242
// .x_gateclk_idx_write_en (create_src1_gateclk_en), @243
// .x_create_data (create_src1_data[9:0]), @244
// .x_read_data (read_src1_data[11:0]), @245
// .x_rdy_clr (src1_rdy_clr) @246
// ); @247
assign x_read_data[BIQ_SRC1_WB] = read_src1_data[1];
assign x_read_data[BIQ_SRC1_PREG:BIQ_SRC1_PREG-6] = read_src1_data[8:2];
assign src1_rdy_for_issue = read_src1_data[9];
assign x_read_data[BIQ_SRC1_RDY] = 1'b0;
assign x_read_data[BIQ_SRC1_LSU_MATCH] = 1'b0;
//==========================================================
// Entry Ready Signal
//==========================================================
assign x_rdy = vld
&& !frz
&& src0_rdy_for_issue
&& src1_rdy_for_issue;
// &ModuleEnd; @262
endmodule |
module ct_idu_rf_prf_eregfile(
cp0_idu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
idu_cp0_fesr_acc_updt_val,
idu_cp0_fesr_acc_updt_vld,
pad_yy_icg_scan_en,
rtu_idu_pst_ereg_retired_released_wb,
rtu_idu_retire0_inst_vld,
vfpu_idu_ex5_pipe6_wb_ereg,
vfpu_idu_ex5_pipe6_wb_ereg_data,
vfpu_idu_ex5_pipe6_wb_ereg_vld,
vfpu_idu_ex5_pipe7_wb_ereg,
vfpu_idu_ex5_pipe7_wb_ereg_data,
vfpu_idu_ex5_pipe7_wb_ereg_vld
);
// &Ports; @26
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [31:0] rtu_idu_pst_ereg_retired_released_wb;
input rtu_idu_retire0_inst_vld;
input [4 :0] vfpu_idu_ex5_pipe6_wb_ereg;
input [5 :0] vfpu_idu_ex5_pipe6_wb_ereg_data;
input vfpu_idu_ex5_pipe6_wb_ereg_vld;
input [4 :0] vfpu_idu_ex5_pipe7_wb_ereg;
input [5 :0] vfpu_idu_ex5_pipe7_wb_ereg_data;
input vfpu_idu_ex5_pipe7_wb_ereg_vld;
output [6 :0] idu_cp0_fesr_acc_updt_val;
output idu_cp0_fesr_acc_updt_vld;
// &Regs; @27
reg fesr_acc_updt_vld_ff;
reg [31:0] fesr_retired_released_wb_ff;
// &Wires; @28
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [5 :0] ereg0_acc_reg_dout;
wire ereg0_retired_released_wb;
wire [1 :0] ereg0_wb_vld;
wire [5 :0] ereg10_acc_reg_dout;
wire ereg10_retired_released_wb;
wire [1 :0] ereg10_wb_vld;
wire [5 :0] ereg11_acc_reg_dout;
wire ereg11_retired_released_wb;
wire [1 :0] ereg11_wb_vld;
wire [5 :0] ereg12_acc_reg_dout;
wire ereg12_retired_released_wb;
wire [1 :0] ereg12_wb_vld;
wire [5 :0] ereg13_acc_reg_dout;
wire ereg13_retired_released_wb;
wire [1 :0] ereg13_wb_vld;
wire [5 :0] ereg14_acc_reg_dout;
wire ereg14_retired_released_wb;
wire [1 :0] ereg14_wb_vld;
wire [5 :0] ereg15_acc_reg_dout;
wire ereg15_retired_released_wb;
wire [1 :0] ereg15_wb_vld;
wire [5 :0] ereg16_acc_reg_dout;
wire ereg16_retired_released_wb;
wire [1 :0] ereg16_wb_vld;
wire [5 :0] ereg17_acc_reg_dout;
wire ereg17_retired_released_wb;
wire [1 :0] ereg17_wb_vld;
wire [5 :0] ereg18_acc_reg_dout;
wire ereg18_retired_released_wb;
wire [1 :0] ereg18_wb_vld;
wire [5 :0] ereg19_acc_reg_dout;
wire ereg19_retired_released_wb;
wire [1 :0] ereg19_wb_vld;
wire [5 :0] ereg1_acc_reg_dout;
wire ereg1_retired_released_wb;
wire [1 :0] ereg1_wb_vld;
wire [5 :0] ereg20_acc_reg_dout;
wire ereg20_retired_released_wb;
wire [1 :0] ereg20_wb_vld;
wire [5 :0] ereg21_acc_reg_dout;
wire ereg21_retired_released_wb;
wire [1 :0] ereg21_wb_vld;
wire [5 :0] ereg22_acc_reg_dout;
wire ereg22_retired_released_wb;
wire [1 :0] ereg22_wb_vld;
wire [5 :0] ereg23_acc_reg_dout;
wire ereg23_retired_released_wb;
wire [1 :0] ereg23_wb_vld;
wire [5 :0] ereg24_acc_reg_dout;
wire ereg24_retired_released_wb;
wire [1 :0] ereg24_wb_vld;
wire [5 :0] ereg25_acc_reg_dout;
wire ereg25_retired_released_wb;
wire [1 :0] ereg25_wb_vld;
wire [5 :0] ereg26_acc_reg_dout;
wire ereg26_retired_released_wb;
wire [1 :0] ereg26_wb_vld;
wire [5 :0] ereg27_acc_reg_dout;
wire ereg27_retired_released_wb;
wire [1 :0] ereg27_wb_vld;
wire [5 :0] ereg28_acc_reg_dout;
wire ereg28_retired_released_wb;
wire [1 :0] ereg28_wb_vld;
wire [5 :0] ereg29_acc_reg_dout;
wire ereg29_retired_released_wb;
wire [1 :0] ereg29_wb_vld;
wire [5 :0] ereg2_acc_reg_dout;
wire ereg2_retired_released_wb;
wire [1 :0] ereg2_wb_vld;
wire [5 :0] ereg30_acc_reg_dout;
wire ereg30_retired_released_wb;
wire [1 :0] ereg30_wb_vld;
wire [5 :0] ereg31_acc_reg_dout;
wire ereg31_retired_released_wb;
wire [1 :0] ereg31_wb_vld;
wire [5 :0] ereg3_acc_reg_dout;
wire ereg3_retired_released_wb;
wire [1 :0] ereg3_wb_vld;
wire [5 :0] ereg4_acc_reg_dout;
wire ereg4_retired_released_wb;
wire [1 :0] ereg4_wb_vld;
wire [5 :0] ereg5_acc_reg_dout;
wire ereg5_retired_released_wb;
wire [1 :0] ereg5_wb_vld;
wire [5 :0] ereg6_acc_reg_dout;
wire ereg6_retired_released_wb;
wire [1 :0] ereg6_wb_vld;
wire [5 :0] ereg7_acc_reg_dout;
wire ereg7_retired_released_wb;
wire [1 :0] ereg7_wb_vld;
wire [5 :0] ereg8_acc_reg_dout;
wire ereg8_retired_released_wb;
wire [1 :0] ereg8_wb_vld;
wire [5 :0] ereg9_acc_reg_dout;
wire ereg9_retired_released_wb;
wire [1 :0] ereg9_wb_vld;
wire ereg_clk_en;
wire ereg_top_clk;
wire [5 :0] fesr_acc;
wire fesr_acc_clk;
wire fesr_acc_clk_en;
wire fesr_acc_updt_vld;
wire [6 :0] fesr_acc_with_fcr;
wire forever_cpuclk;
wire [6 :0] idu_cp0_fesr_acc_updt_val;
wire idu_cp0_fesr_acc_updt_vld;
wire pad_yy_icg_scan_en;
wire [31:0] pipe6_wb_vld;
wire [31:0] pipe7_wb_vld;
wire [31:0] rtu_idu_pst_ereg_retired_released_wb;
wire rtu_idu_retire0_inst_vld;
wire [4 :0] vfpu_idu_ex5_pipe6_wb_ereg;
wire [5 :0] vfpu_idu_ex5_pipe6_wb_ereg_data;
wire [31:0] vfpu_idu_ex5_pipe6_wb_ereg_expand;
wire vfpu_idu_ex5_pipe6_wb_ereg_vld;
wire [4 :0] vfpu_idu_ex5_pipe7_wb_ereg;
wire [5 :0] vfpu_idu_ex5_pipe7_wb_ereg_data;
wire [31:0] vfpu_idu_ex5_pipe7_wb_ereg_expand;
wire vfpu_idu_ex5_pipe7_wb_ereg_vld;
//==========================================================
// Top Mudule Gated Cell
//==========================================================
assign ereg_clk_en = vfpu_idu_ex5_pipe6_wb_ereg_vld
|| vfpu_idu_ex5_pipe7_wb_ereg_vld;
// &Instance("gated_clk_cell", "x_ereg_gated_clk"); @36
gated_clk_cell x_ereg_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ereg_top_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ereg_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @37
// .external_en (1'b0), @38
// .global_en (cp0_yy_clk_en), @39
// .module_en (cp0_idu_icg_en), @40
// .local_en (ereg_clk_en), @41
// .clk_out (ereg_top_clk)); @42
//==========================================================
// Instance F expt Physical Registers
//==========================================================
// &ConnRule(s/^x_/ereg0_/); @47
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg0"); @48
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg0 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg0_acc_reg_dout ),
.x_retired_released_wb (ereg0_retired_released_wb ),
.x_wb_vld (ereg0_wb_vld )
);
// &ConnRule(s/^x_/ereg1_/); @49
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg1"); @50
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg1 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg1_acc_reg_dout ),
.x_retired_released_wb (ereg1_retired_released_wb ),
.x_wb_vld (ereg1_wb_vld )
);
// &ConnRule(s/^x_/ereg2_/); @51
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg2"); @52
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg2 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg2_acc_reg_dout ),
.x_retired_released_wb (ereg2_retired_released_wb ),
.x_wb_vld (ereg2_wb_vld )
);
// &ConnRule(s/^x_/ereg3_/); @53
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg3"); @54
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg3 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg3_acc_reg_dout ),
.x_retired_released_wb (ereg3_retired_released_wb ),
.x_wb_vld (ereg3_wb_vld )
);
// &ConnRule(s/^x_/ereg4_/); @55
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg4"); @56
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg4 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg4_acc_reg_dout ),
.x_retired_released_wb (ereg4_retired_released_wb ),
.x_wb_vld (ereg4_wb_vld )
);
// &ConnRule(s/^x_/ereg5_/); @57
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg5"); @58
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg5 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg5_acc_reg_dout ),
.x_retired_released_wb (ereg5_retired_released_wb ),
.x_wb_vld (ereg5_wb_vld )
);
// &ConnRule(s/^x_/ereg6_/); @59
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg6"); @60
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg6 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg6_acc_reg_dout ),
.x_retired_released_wb (ereg6_retired_released_wb ),
.x_wb_vld (ereg6_wb_vld )
);
// &ConnRule(s/^x_/ereg7_/); @61
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg7"); @62
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg7 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg7_acc_reg_dout ),
.x_retired_released_wb (ereg7_retired_released_wb ),
.x_wb_vld (ereg7_wb_vld )
);
// &ConnRule(s/^x_/ereg8_/); @63
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg8"); @64
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg8 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg8_acc_reg_dout ),
.x_retired_released_wb (ereg8_retired_released_wb ),
.x_wb_vld (ereg8_wb_vld )
);
// &ConnRule(s/^x_/ereg9_/); @65
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg9"); @66
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg9 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg9_acc_reg_dout ),
.x_retired_released_wb (ereg9_retired_released_wb ),
.x_wb_vld (ereg9_wb_vld )
);
// &ConnRule(s/^x_/ereg10_/); @67
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg10"); @68
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg10 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg10_acc_reg_dout ),
.x_retired_released_wb (ereg10_retired_released_wb ),
.x_wb_vld (ereg10_wb_vld )
);
// &ConnRule(s/^x_/ereg11_/); @69
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg11"); @70
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg11 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg11_acc_reg_dout ),
.x_retired_released_wb (ereg11_retired_released_wb ),
.x_wb_vld (ereg11_wb_vld )
);
// &ConnRule(s/^x_/ereg12_/); @71
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg12"); @72
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg12 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg12_acc_reg_dout ),
.x_retired_released_wb (ereg12_retired_released_wb ),
.x_wb_vld (ereg12_wb_vld )
);
// &ConnRule(s/^x_/ereg13_/); @73
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg13"); @74
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg13 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg13_acc_reg_dout ),
.x_retired_released_wb (ereg13_retired_released_wb ),
.x_wb_vld (ereg13_wb_vld )
);
// &ConnRule(s/^x_/ereg14_/); @75
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg14"); @76
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg14 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg14_acc_reg_dout ),
.x_retired_released_wb (ereg14_retired_released_wb ),
.x_wb_vld (ereg14_wb_vld )
);
// &ConnRule(s/^x_/ereg15_/); @77
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg15"); @78
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg15 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg15_acc_reg_dout ),
.x_retired_released_wb (ereg15_retired_released_wb ),
.x_wb_vld (ereg15_wb_vld )
);
// &ConnRule(s/^x_/ereg16_/); @79
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg16"); @80
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg16 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg16_acc_reg_dout ),
.x_retired_released_wb (ereg16_retired_released_wb ),
.x_wb_vld (ereg16_wb_vld )
);
// &ConnRule(s/^x_/ereg17_/); @81
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg17"); @82
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg17 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg17_acc_reg_dout ),
.x_retired_released_wb (ereg17_retired_released_wb ),
.x_wb_vld (ereg17_wb_vld )
);
// &ConnRule(s/^x_/ereg18_/); @83
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg18"); @84
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg18 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg18_acc_reg_dout ),
.x_retired_released_wb (ereg18_retired_released_wb ),
.x_wb_vld (ereg18_wb_vld )
);
// &ConnRule(s/^x_/ereg19_/); @85
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg19"); @86
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg19 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg19_acc_reg_dout ),
.x_retired_released_wb (ereg19_retired_released_wb ),
.x_wb_vld (ereg19_wb_vld )
);
// &ConnRule(s/^x_/ereg20_/); @87
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg20"); @88
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg20 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg20_acc_reg_dout ),
.x_retired_released_wb (ereg20_retired_released_wb ),
.x_wb_vld (ereg20_wb_vld )
);
// &ConnRule(s/^x_/ereg21_/); @89
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg21"); @90
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg21 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg21_acc_reg_dout ),
.x_retired_released_wb (ereg21_retired_released_wb ),
.x_wb_vld (ereg21_wb_vld )
);
// &ConnRule(s/^x_/ereg22_/); @91
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg22"); @92
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg22 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg22_acc_reg_dout ),
.x_retired_released_wb (ereg22_retired_released_wb ),
.x_wb_vld (ereg22_wb_vld )
);
// &ConnRule(s/^x_/ereg23_/); @93
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg23"); @94
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg23 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg23_acc_reg_dout ),
.x_retired_released_wb (ereg23_retired_released_wb ),
.x_wb_vld (ereg23_wb_vld )
);
// &ConnRule(s/^x_/ereg24_/); @95
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg24"); @96
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg24 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg24_acc_reg_dout ),
.x_retired_released_wb (ereg24_retired_released_wb ),
.x_wb_vld (ereg24_wb_vld )
);
// &ConnRule(s/^x_/ereg25_/); @97
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg25"); @98
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg25 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg25_acc_reg_dout ),
.x_retired_released_wb (ereg25_retired_released_wb ),
.x_wb_vld (ereg25_wb_vld )
);
// &ConnRule(s/^x_/ereg26_/); @99
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg26"); @100
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg26 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg26_acc_reg_dout ),
.x_retired_released_wb (ereg26_retired_released_wb ),
.x_wb_vld (ereg26_wb_vld )
);
// &ConnRule(s/^x_/ereg27_/); @101
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg27"); @102
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg27 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg27_acc_reg_dout ),
.x_retired_released_wb (ereg27_retired_released_wb ),
.x_wb_vld (ereg27_wb_vld )
);
// &ConnRule(s/^x_/ereg28_/); @103
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg28"); @104
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg28 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg28_acc_reg_dout ),
.x_retired_released_wb (ereg28_retired_released_wb ),
.x_wb_vld (ereg28_wb_vld )
);
// &ConnRule(s/^x_/ereg29_/); @105
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg29"); @106
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg29 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg29_acc_reg_dout ),
.x_retired_released_wb (ereg29_retired_released_wb ),
.x_wb_vld (ereg29_wb_vld )
);
// &ConnRule(s/^x_/ereg30_/); @107
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg30"); @108
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg30 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg30_acc_reg_dout ),
.x_retired_released_wb (ereg30_retired_released_wb ),
.x_wb_vld (ereg30_wb_vld )
);
// &ConnRule(s/^x_/ereg31_/); @109
// &Instance("ct_idu_rf_prf_gated_ereg", "x_ct_idu_rf_prf_ereg31"); @110
ct_idu_rf_prf_gated_ereg x_ct_idu_rf_prf_ereg31 (
.cp0_idu_icg_en (cp0_idu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ereg_top_clk (ereg_top_clk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_idu_ex5_pipe6_wb_ereg_data (vfpu_idu_ex5_pipe6_wb_ereg_data),
.vfpu_idu_ex5_pipe7_wb_ereg_data (vfpu_idu_ex5_pipe7_wb_ereg_data),
.x_acc_reg_dout (ereg31_acc_reg_dout ),
.x_retired_released_wb (ereg31_retired_released_wb ),
.x_wb_vld (ereg31_wb_vld )
);
//==========================================================
// Write Port
//==========================================================
// &ConnRule(s/^x_num/vfpu_idu_ex5_pipe6_wb_ereg/); @115
// &Instance("ct_rtu_expand_32","x_ct_rtu_expand_32_vfpu_idu_ex5_pipe6_wb_ereg"); @116
ct_rtu_expand_32 x_ct_rtu_expand_32_vfpu_idu_ex5_pipe6_wb_ereg (
.x_num (vfpu_idu_ex5_pipe6_wb_ereg ),
.x_num_expand (vfpu_idu_ex5_pipe6_wb_ereg_expand)
);
// &ConnRule(s/^x_num/vfpu_idu_ex5_pipe7_wb_ereg/); @117
// &Instance("ct_rtu_expand_32","x_ct_rtu_expand_32_vfpu_idu_ex5_pipe7_wb_ereg"); @118
ct_rtu_expand_32 x_ct_rtu_expand_32_vfpu_idu_ex5_pipe7_wb_ereg (
.x_num (vfpu_idu_ex5_pipe7_wb_ereg ),
.x_num_expand (vfpu_idu_ex5_pipe7_wb_ereg_expand)
);
//3 write ports
assign pipe6_wb_vld[31:0] = {32{vfpu_idu_ex5_pipe6_wb_ereg_vld}}
& vfpu_idu_ex5_pipe6_wb_ereg_expand[31:0];
assign pipe7_wb_vld[31:0] = {32{vfpu_idu_ex5_pipe7_wb_ereg_vld}}
& vfpu_idu_ex5_pipe7_wb_ereg_expand[31:0];
assign ereg0_wb_vld[1:0] = {pipe7_wb_vld[0], pipe6_wb_vld[0]};
assign ereg1_wb_vld[1:0] = {pipe7_wb_vld[1], pipe6_wb_vld[1]};
assign ereg2_wb_vld[1:0] = {pipe7_wb_vld[2], pipe6_wb_vld[2]};
assign ereg3_wb_vld[1:0] = {pipe7_wb_vld[3], pipe6_wb_vld[3]};
assign ereg4_wb_vld[1:0] = {pipe7_wb_vld[4], pipe6_wb_vld[4]};
assign ereg5_wb_vld[1:0] = {pipe7_wb_vld[5], pipe6_wb_vld[5]};
assign ereg6_wb_vld[1:0] = {pipe7_wb_vld[6], pipe6_wb_vld[6]};
assign ereg7_wb_vld[1:0] = {pipe7_wb_vld[7], pipe6_wb_vld[7]};
assign ereg8_wb_vld[1:0] = {pipe7_wb_vld[8], pipe6_wb_vld[8]};
assign ereg9_wb_vld[1:0] = {pipe7_wb_vld[9], pipe6_wb_vld[9]};
assign ereg10_wb_vld[1:0] = {pipe7_wb_vld[10],pipe6_wb_vld[10]};
assign ereg11_wb_vld[1:0] = {pipe7_wb_vld[11],pipe6_wb_vld[11]};
assign ereg12_wb_vld[1:0] = {pipe7_wb_vld[12],pipe6_wb_vld[12]};
assign ereg13_wb_vld[1:0] = {pipe7_wb_vld[13],pipe6_wb_vld[13]};
assign ereg14_wb_vld[1:0] = {pipe7_wb_vld[14],pipe6_wb_vld[14]};
assign ereg15_wb_vld[1:0] = {pipe7_wb_vld[15],pipe6_wb_vld[15]};
assign ereg16_wb_vld[1:0] = {pipe7_wb_vld[16],pipe6_wb_vld[16]};
assign ereg17_wb_vld[1:0] = {pipe7_wb_vld[17],pipe6_wb_vld[17]};
assign ereg18_wb_vld[1:0] = {pipe7_wb_vld[18],pipe6_wb_vld[18]};
assign ereg19_wb_vld[1:0] = {pipe7_wb_vld[19],pipe6_wb_vld[19]};
assign ereg20_wb_vld[1:0] = {pipe7_wb_vld[20],pipe6_wb_vld[20]};
assign ereg21_wb_vld[1:0] = {pipe7_wb_vld[21],pipe6_wb_vld[21]};
assign ereg22_wb_vld[1:0] = {pipe7_wb_vld[22],pipe6_wb_vld[22]};
assign ereg23_wb_vld[1:0] = {pipe7_wb_vld[23],pipe6_wb_vld[23]};
assign ereg24_wb_vld[1:0] = {pipe7_wb_vld[24],pipe6_wb_vld[24]};
assign ereg25_wb_vld[1:0] = {pipe7_wb_vld[25],pipe6_wb_vld[25]};
assign ereg26_wb_vld[1:0] = {pipe7_wb_vld[26],pipe6_wb_vld[26]};
assign ereg27_wb_vld[1:0] = {pipe7_wb_vld[27],pipe6_wb_vld[27]};
assign ereg28_wb_vld[1:0] = {pipe7_wb_vld[28],pipe6_wb_vld[28]};
assign ereg29_wb_vld[1:0] = {pipe7_wb_vld[29],pipe6_wb_vld[29]};
assign ereg30_wb_vld[1:0] = {pipe7_wb_vld[30],pipe6_wb_vld[30]};
assign ereg31_wb_vld[1:0] = {pipe7_wb_vld[31],pipe6_wb_vld[31]};
//==========================================================
// Read Port
//==========================================================
////----------------------------------------------------------
//// Read Port : FESR Cur bit
////----------------------------------------------------------
//assign fesr_cur[6] = |fesr_cur[5:0];
//assign fesr_cur[5:0] =
// {6{rtu_idu_prf_f_ereg_expand[0]}} & ereg0_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[1]}} & ereg1_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[2]}} & ereg2_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[3]}} & ereg3_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[4]}} & ereg4_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[5]}} & ereg5_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[6]}} & ereg6_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[7]}} & ereg7_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[8]}} & ereg8_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[9]}} & ereg9_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[10]}} & ereg10_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[11]}} & ereg11_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[12]}} & ereg12_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[13]}} & ereg13_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[14]}} & ereg14_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[15]}} & ereg15_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[16]}} & ereg16_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[17]}} & ereg17_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[18]}} & ereg18_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[19]}} & ereg19_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[20]}} & ereg20_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[21]}} & ereg21_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[22]}} & ereg22_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[23]}} & ereg23_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[24]}} & ereg24_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[25]}} & ereg25_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[26]}} & ereg26_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[27]}} & ereg27_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[28]}} & ereg28_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[29]}} & ereg29_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[30]}} & ereg30_reg_dout[5:0]
// | {6{rtu_idu_prf_f_ereg_expand[31]}} & ereg31_reg_dout[5:0];
//
//assign idu_cp0_fesr_cur[6:0] = fesr_cur[6:0];
//----------------------------------------------------------
// Read Port : FESR Acc bit update value
//----------------------------------------------------------
assign ereg0_retired_released_wb = fesr_retired_released_wb_ff[0];
assign ereg1_retired_released_wb = fesr_retired_released_wb_ff[1];
assign ereg2_retired_released_wb = fesr_retired_released_wb_ff[2];
assign ereg3_retired_released_wb = fesr_retired_released_wb_ff[3];
assign ereg4_retired_released_wb = fesr_retired_released_wb_ff[4];
assign ereg5_retired_released_wb = fesr_retired_released_wb_ff[5];
assign ereg6_retired_released_wb = fesr_retired_released_wb_ff[6];
assign ereg7_retired_released_wb = fesr_retired_released_wb_ff[7];
assign ereg8_retired_released_wb = fesr_retired_released_wb_ff[8];
assign ereg9_retired_released_wb = fesr_retired_released_wb_ff[9];
assign ereg10_retired_released_wb = fesr_retired_released_wb_ff[10];
assign ereg11_retired_released_wb = fesr_retired_released_wb_ff[11];
assign ereg12_retired_released_wb = fesr_retired_released_wb_ff[12];
assign ereg13_retired_released_wb = fesr_retired_released_wb_ff[13];
assign ereg14_retired_released_wb = fesr_retired_released_wb_ff[14];
assign ereg15_retired_released_wb = fesr_retired_released_wb_ff[15];
assign ereg16_retired_released_wb = fesr_retired_released_wb_ff[16];
assign ereg17_retired_released_wb = fesr_retired_released_wb_ff[17];
assign ereg18_retired_released_wb = fesr_retired_released_wb_ff[18];
assign ereg19_retired_released_wb = fesr_retired_released_wb_ff[19];
assign ereg20_retired_released_wb = fesr_retired_released_wb_ff[20];
assign ereg21_retired_released_wb = fesr_retired_released_wb_ff[21];
assign ereg22_retired_released_wb = fesr_retired_released_wb_ff[22];
assign ereg23_retired_released_wb = fesr_retired_released_wb_ff[23];
assign ereg24_retired_released_wb = fesr_retired_released_wb_ff[24];
assign ereg25_retired_released_wb = fesr_retired_released_wb_ff[25];
assign ereg26_retired_released_wb = fesr_retired_released_wb_ff[26];
assign ereg27_retired_released_wb = fesr_retired_released_wb_ff[27];
assign ereg28_retired_released_wb = fesr_retired_released_wb_ff[28];
assign ereg29_retired_released_wb = fesr_retired_released_wb_ff[29];
assign ereg30_retired_released_wb = fesr_retired_released_wb_ff[30];
assign ereg31_retired_released_wb = fesr_retired_released_wb_ff[31];
assign fesr_acc[5:0] = ereg0_acc_reg_dout[5:0]
| ereg1_acc_reg_dout[5:0]
| ereg2_acc_reg_dout[5:0]
| ereg3_acc_reg_dout[5:0]
| ereg4_acc_reg_dout[5:0]
| ereg5_acc_reg_dout[5:0]
| ereg6_acc_reg_dout[5:0]
| ereg7_acc_reg_dout[5:0]
| ereg8_acc_reg_dout[5:0]
| ereg9_acc_reg_dout[5:0]
| ereg10_acc_reg_dout[5:0]
| ereg11_acc_reg_dout[5:0]
| ereg12_acc_reg_dout[5:0]
| ereg13_acc_reg_dout[5:0]
| ereg14_acc_reg_dout[5:0]
| ereg15_acc_reg_dout[5:0]
| ereg16_acc_reg_dout[5:0]
| ereg17_acc_reg_dout[5:0]
| ereg18_acc_reg_dout[5:0]
| ereg19_acc_reg_dout[5:0]
| ereg20_acc_reg_dout[5:0]
| ereg21_acc_reg_dout[5:0]
| ereg22_acc_reg_dout[5:0]
| ereg23_acc_reg_dout[5:0]
| ereg24_acc_reg_dout[5:0]
| ereg25_acc_reg_dout[5:0]
| ereg26_acc_reg_dout[5:0]
| ereg27_acc_reg_dout[5:0]
| ereg28_acc_reg_dout[5:0]
| ereg29_acc_reg_dout[5:0]
| ereg30_acc_reg_dout[5:0]
| ereg31_acc_reg_dout[5:0];
assign fesr_acc_with_fcr[4:0] = fesr_acc[4:0];
assign fesr_acc_with_fcr[5] = |fesr_acc_with_fcr[4:0];
assign fesr_acc_with_fcr[6] = fesr_acc[5];
assign idu_cp0_fesr_acc_updt_val[6:0] = fesr_acc_with_fcr[6:0];
//----------------------------------------------------------
// Update valid
//----------------------------------------------------------
assign fesr_acc_updt_vld = rtu_idu_retire0_inst_vld
|| vfpu_idu_ex5_pipe6_wb_ereg_vld
|| vfpu_idu_ex5_pipe7_wb_ereg_vld;
assign fesr_acc_clk_en = fesr_acc_updt_vld || fesr_acc_updt_vld_ff;
// &Instance("gated_clk_cell", "x_ereg_acc_gated_clk"); @284
gated_clk_cell x_ereg_acc_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (fesr_acc_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fesr_acc_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @285
// .external_en (1'b0), @286
// .global_en (cp0_yy_clk_en), @287
// .module_en (cp0_idu_icg_en), @288
// .local_en (fesr_acc_clk_en), @289
// .clk_out (fesr_acc_clk)); @290
always @(posedge fesr_acc_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
fesr_acc_updt_vld_ff <= 1'b0;
fesr_retired_released_wb_ff[31:0] <= 32'b0;
end
else if(fesr_acc_updt_vld) begin
fesr_acc_updt_vld_ff <= 1'b1;
fesr_retired_released_wb_ff[31:0] <= rtu_idu_pst_ereg_retired_released_wb[31:0];
end
else begin
fesr_acc_updt_vld_ff <= 1'b0;
fesr_retired_released_wb_ff[31:0] <= fesr_retired_released_wb_ff[31:0];
end
end
assign idu_cp0_fesr_acc_updt_vld = fesr_acc_updt_vld_ff
&& (|fesr_retired_released_wb_ff[31:0]);
// &ModuleEnd; @311
endmodule |
module ct_idu_dep_vreg_srcv2_entry(
cp0_idu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_xx_rf_pipe6_vmla_lch_vld_dupx,
ctrl_xx_rf_pipe7_vmla_lch_vld_dupx,
dp_xx_rf_pipe6_dst_vreg_dupx,
dp_xx_rf_pipe7_dst_vreg_dupx,
forever_cpuclk,
gateclk_entry_vld,
lsu_idu_ag_pipe3_vload_inst_vld,
lsu_idu_ag_pipe3_vreg_dupx,
lsu_idu_dc_pipe3_vload_fwd_inst_vld,
lsu_idu_dc_pipe3_vload_inst_vld_dupx,
lsu_idu_dc_pipe3_vreg_dupx,
lsu_idu_wb_pipe3_wb_vreg_dupx,
lsu_idu_wb_pipe3_wb_vreg_vld_dupx,
pad_yy_icg_scan_en,
rtu_idu_flush_fe,
rtu_idu_flush_is,
vfpu0_vreg_fwd_vld,
vfpu1_vreg_fwd_vld,
vfpu_idu_ex1_pipe6_data_vld_dupx,
vfpu_idu_ex1_pipe6_fmla_data_vld_dupx,
vfpu_idu_ex1_pipe6_vreg_dupx,
vfpu_idu_ex1_pipe7_data_vld_dupx,
vfpu_idu_ex1_pipe7_fmla_data_vld_dupx,
vfpu_idu_ex1_pipe7_vreg_dupx,
vfpu_idu_ex2_pipe6_data_vld_dupx,
vfpu_idu_ex2_pipe6_fmla_data_vld_dupx,
vfpu_idu_ex2_pipe6_vreg_dupx,
vfpu_idu_ex2_pipe7_data_vld_dupx,
vfpu_idu_ex2_pipe7_fmla_data_vld_dupx,
vfpu_idu_ex2_pipe7_vreg_dupx,
vfpu_idu_ex3_pipe6_data_vld_dupx,
vfpu_idu_ex3_pipe6_vreg_dupx,
vfpu_idu_ex3_pipe7_data_vld_dupx,
vfpu_idu_ex3_pipe7_vreg_dupx,
vfpu_idu_ex5_pipe6_wb_vreg_dupx,
vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx,
vfpu_idu_ex5_pipe7_wb_vreg_dupx,
vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx,
x_create_data,
x_entry_vmla,
x_gateclk_idx_write_en,
x_gateclk_write_en,
x_rdy_clr,
x_read_data,
x_write_en
);
// &Ports; @27
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_xx_rf_pipe6_vmla_lch_vld_dupx;
input ctrl_xx_rf_pipe7_vmla_lch_vld_dupx;
input [6 :0] dp_xx_rf_pipe6_dst_vreg_dupx;
input [6 :0] dp_xx_rf_pipe7_dst_vreg_dupx;
input forever_cpuclk;
input gateclk_entry_vld;
input lsu_idu_ag_pipe3_vload_inst_vld;
input [6 :0] lsu_idu_ag_pipe3_vreg_dupx;
input lsu_idu_dc_pipe3_vload_fwd_inst_vld;
input lsu_idu_dc_pipe3_vload_inst_vld_dupx;
input [6 :0] lsu_idu_dc_pipe3_vreg_dupx;
input [6 :0] lsu_idu_wb_pipe3_wb_vreg_dupx;
input lsu_idu_wb_pipe3_wb_vreg_vld_dupx;
input pad_yy_icg_scan_en;
input rtu_idu_flush_fe;
input rtu_idu_flush_is;
input vfpu0_vreg_fwd_vld;
input vfpu1_vreg_fwd_vld;
input vfpu_idu_ex1_pipe6_data_vld_dupx;
input vfpu_idu_ex1_pipe6_fmla_data_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe6_vreg_dupx;
input vfpu_idu_ex1_pipe7_data_vld_dupx;
input vfpu_idu_ex1_pipe7_fmla_data_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe7_vreg_dupx;
input vfpu_idu_ex2_pipe6_data_vld_dupx;
input vfpu_idu_ex2_pipe6_fmla_data_vld_dupx;
input [6 :0] vfpu_idu_ex2_pipe6_vreg_dupx;
input vfpu_idu_ex2_pipe7_data_vld_dupx;
input vfpu_idu_ex2_pipe7_fmla_data_vld_dupx;
input [6 :0] vfpu_idu_ex2_pipe7_vreg_dupx;
input vfpu_idu_ex3_pipe6_data_vld_dupx;
input [6 :0] vfpu_idu_ex3_pipe6_vreg_dupx;
input vfpu_idu_ex3_pipe7_data_vld_dupx;
input [6 :0] vfpu_idu_ex3_pipe7_vreg_dupx;
input [6 :0] vfpu_idu_ex5_pipe6_wb_vreg_dupx;
input vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx;
input [6 :0] vfpu_idu_ex5_pipe7_wb_vreg_dupx;
input vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx;
input [10:0] x_create_data;
input x_entry_vmla;
input x_gateclk_idx_write_en;
input x_gateclk_write_en;
input x_rdy_clr;
input x_write_en;
output [12:0] x_read_data;
// &Regs; @28
reg lsu_match;
reg mla_rdy;
reg rdy;
reg [6 :0] vreg;
reg wb;
// &Wires; @29
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_xx_rf_pipe6_vmla_lch_vld_dupx;
wire ctrl_xx_rf_pipe7_vmla_lch_vld_dupx;
wire data_ready;
wire dep_clk;
wire dep_clk_en;
wire [6 :0] dp_xx_rf_pipe6_dst_vreg_dupx;
wire [6 :0] dp_xx_rf_pipe7_dst_vreg_dupx;
wire forever_cpuclk;
wire gateclk_entry_vld;
wire load_data_ready;
wire load_issue_data_ready;
wire lsu_idu_ag_pipe3_vload_inst_vld;
wire [6 :0] lsu_idu_ag_pipe3_vreg_dupx;
wire lsu_idu_dc_pipe3_vload_fwd_inst_vld;
wire lsu_idu_dc_pipe3_vload_inst_vld_dupx;
wire [6 :0] lsu_idu_dc_pipe3_vreg_dupx;
wire [6 :0] lsu_idu_wb_pipe3_wb_vreg_dupx;
wire lsu_idu_wb_pipe3_wb_vreg_vld_dupx;
wire lsu_match_update;
wire mla_data_ready;
wire mla_rdy_update;
wire pad_yy_icg_scan_en;
wire pipe3_wb;
wire pipe6_wb;
wire pipe7_wb;
wire rdy_clear;
wire rdy_update;
wire rtu_idu_flush_fe;
wire rtu_idu_flush_is;
wire vfpu0_ex3_data_ready;
wire vfpu0_ex4_data_ready;
wire vfpu0_ex5_data_ready;
wire vfpu0_fmla_data_ready;
wire vfpu0_vdsp_fwd_data_ready;
wire vfpu0_vmla_data_ready;
wire vfpu0_vreg_fwd_vld;
wire vfpu1_ex3_data_ready;
wire vfpu1_ex4_data_ready;
wire vfpu1_ex5_data_ready;
wire vfpu1_fmla_data_ready;
wire vfpu1_vdsp_fwd_data_ready;
wire vfpu1_vmla_data_ready;
wire vfpu1_vreg_fwd_vld;
wire vfpu_idu_ex1_pipe6_data_vld_dupx;
wire vfpu_idu_ex1_pipe6_fmla_data_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe6_vreg_dupx;
wire vfpu_idu_ex1_pipe7_data_vld_dupx;
wire vfpu_idu_ex1_pipe7_fmla_data_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe7_vreg_dupx;
wire vfpu_idu_ex2_pipe6_data_vld_dupx;
wire vfpu_idu_ex2_pipe6_fmla_data_vld_dupx;
wire [6 :0] vfpu_idu_ex2_pipe6_vreg_dupx;
wire vfpu_idu_ex2_pipe7_data_vld_dupx;
wire vfpu_idu_ex2_pipe7_fmla_data_vld_dupx;
wire [6 :0] vfpu_idu_ex2_pipe7_vreg_dupx;
wire vfpu_idu_ex3_pipe6_data_vld_dupx;
wire [6 :0] vfpu_idu_ex3_pipe6_vreg_dupx;
wire vfpu_idu_ex3_pipe7_data_vld_dupx;
wire [6 :0] vfpu_idu_ex3_pipe7_vreg_dupx;
wire [6 :0] vfpu_idu_ex5_pipe6_wb_vreg_dupx;
wire vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx;
wire [6 :0] vfpu_idu_ex5_pipe7_wb_vreg_dupx;
wire vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx;
wire wake_up;
wire wb_update;
wire write_back;
wire write_clk;
wire write_clk_en;
wire [10:0] x_create_data;
wire x_create_lsu_match;
wire x_create_mla_rdy;
wire x_create_rdy;
wire [6 :0] x_create_vreg;
wire x_create_wb;
wire x_entry_vmla;
wire x_gateclk_idx_write_en;
wire x_gateclk_write_en;
wire x_rdy_clr;
wire [12:0] x_read_data;
wire x_read_lsu_match;
wire x_read_mla_rdy;
wire x_read_rdy;
wire x_read_rdy_for_bypass;
wire x_read_rdy_for_issue;
wire [6 :0] x_read_vreg;
wire x_read_wb;
wire x_write_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign dep_clk_en = x_gateclk_write_en || gateclk_entry_vld && (!rdy || !wb);
// &Instance("gated_clk_cell", "x_dep_gated_clk"); @36
gated_clk_cell x_dep_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (dep_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (dep_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @37
// .external_en (1'b0), @38
// .global_en (cp0_yy_clk_en), @39
// .module_en (cp0_idu_icg_en), @40
// .local_en (dep_clk_en), @41
// .clk_out (dep_clk)); @42
assign write_clk_en = x_gateclk_idx_write_en;
// &Instance("gated_clk_cell", "x_write_gated_clk"); @45
gated_clk_cell x_write_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (write_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (write_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @46
// .external_en (1'b0), @47
// .global_en (cp0_yy_clk_en), @48
// .module_en (cp0_idu_icg_en), @49
// .local_en (write_clk_en), @50
// .clk_out (write_clk)); @51
//==========================================================
// Create and Read Bus
//==========================================================
assign x_create_lsu_match = x_create_data[10];
assign x_create_mla_rdy = x_create_data[9];
assign x_create_vreg[6:0] = x_create_data[8:2];
assign x_create_wb = x_create_data[1];
assign x_create_rdy = x_create_data[0];
assign x_read_data[12] = x_read_lsu_match;
assign x_read_data[11] = x_read_rdy_for_bypass;
assign x_read_data[10] = x_read_rdy_for_issue;
assign x_read_data[9] = x_read_mla_rdy;
assign x_read_data[8:2] = x_read_vreg[6:0];
assign x_read_data[1] = x_read_wb;
assign x_read_data[0] = x_read_rdy;
//==========================================================
// Ready Bit
//==========================================================
//ready bit shows the result of source is predicted to be ready:
//1 stands for the result may be forwarded
//-------------Update value of Ready Bit--------------------
//prepare data_ready signal
assign vfpu0_ex3_data_ready = vfpu_idu_ex1_pipe6_data_vld_dupx
&& (vfpu_idu_ex1_pipe6_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu0_ex4_data_ready = vfpu_idu_ex2_pipe6_data_vld_dupx
&& (vfpu_idu_ex2_pipe6_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu0_ex5_data_ready = vfpu_idu_ex3_pipe6_data_vld_dupx
&& (vfpu_idu_ex3_pipe6_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu1_ex3_data_ready = vfpu_idu_ex1_pipe7_data_vld_dupx
&& (vfpu_idu_ex1_pipe7_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu1_ex4_data_ready = vfpu_idu_ex2_pipe7_data_vld_dupx
&& (vfpu_idu_ex2_pipe7_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu1_ex5_data_ready = vfpu_idu_ex3_pipe7_data_vld_dupx
&& (vfpu_idu_ex3_pipe7_vreg_dupx[6:0] == vreg[6:0]);
assign load_data_ready = lsu_idu_dc_pipe3_vload_inst_vld_dupx
&& (lsu_idu_dc_pipe3_vreg_dupx[6:0] == vreg[6:0]);
//load bypass data ready for issue
assign load_issue_data_ready = lsu_idu_dc_pipe3_vload_fwd_inst_vld && lsu_match;
assign data_ready = vfpu0_ex3_data_ready
|| vfpu0_ex4_data_ready
|| vfpu0_ex5_data_ready
|| vfpu1_ex3_data_ready
|| vfpu1_ex4_data_ready
|| vfpu1_ex5_data_ready
|| load_data_ready;
//prepare wake up signal
assign wake_up = wb;
//prepare clear signal
assign rdy_clear = x_rdy_clr;
//1.if ready is already be 1, just hold 1
//2.if producer are presumed to produce the result two cycles later,
// set ready to 1
//3.if producer wake up, set ready to 1
//4.clear ready to 0
assign rdy_update = (rdy || data_ready || wake_up) && !rdy_clear;
//ready read signal
assign x_read_rdy = rdy_update;
//the following signals are for Issue Queue bypass/issue logic
assign x_read_rdy_for_issue = rdy || mla_rdy || load_issue_data_ready
|| vfpu0_vdsp_fwd_data_ready
|| vfpu1_vdsp_fwd_data_ready;
assign x_read_rdy_for_bypass = rdy;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rdy <= 1'b1;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
rdy <= 1'b1;
else if(x_write_en)
rdy <= x_create_rdy;
else
rdy <= rdy_update;
end
//==========================================================
// LSU reg Match for Bypass Ready
//==========================================================
assign lsu_match_update = lsu_idu_ag_pipe3_vload_inst_vld
&& (lsu_idu_ag_pipe3_vreg_dupx[6:0] == vreg[6:0]);
assign x_read_lsu_match = lsu_match_update;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lsu_match <= 1'b0;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
lsu_match <= 1'b0;
else if(x_write_en)
lsu_match <= x_create_lsu_match;
else
lsu_match <= lsu_match_update;
end
//==========================================================
// Multiply Accumulate Ready Bit
//==========================================================
//ready bit for mla inst, ready eariler than normal ready
//-------------Update value of Ready Bit--------------------
//prepare data_ready signal
assign vfpu0_fmla_data_ready = x_entry_vmla
&& vfpu_idu_ex2_pipe6_fmla_data_vld_dupx
&& (vfpu_idu_ex2_pipe6_vreg_dupx[6:0] == vreg[6:0])
|| x_entry_vmla
&& vfpu_idu_ex1_pipe6_fmla_data_vld_dupx
&& (vfpu_idu_ex1_pipe6_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu1_fmla_data_ready = x_entry_vmla
&& vfpu_idu_ex2_pipe7_fmla_data_vld_dupx
&& (vfpu_idu_ex2_pipe7_vreg_dupx[6:0] == vreg[6:0])
|| x_entry_vmla
&& vfpu_idu_ex1_pipe7_fmla_data_vld_dupx
&& (vfpu_idu_ex1_pipe7_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu0_vmla_data_ready = x_entry_vmla
&& ctrl_xx_rf_pipe6_vmla_lch_vld_dupx
&& (dp_xx_rf_pipe6_dst_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu1_vmla_data_ready = x_entry_vmla
&& ctrl_xx_rf_pipe7_vmla_lch_vld_dupx
&& (dp_xx_rf_pipe7_dst_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu0_vdsp_fwd_data_ready = x_entry_vmla
&& vfpu0_vreg_fwd_vld;
assign vfpu1_vdsp_fwd_data_ready = x_entry_vmla
&& vfpu1_vreg_fwd_vld;
assign mla_data_ready = vfpu0_fmla_data_ready
|| vfpu1_fmla_data_ready
|| vfpu0_vmla_data_ready
|| vfpu1_vmla_data_ready
|| vfpu0_vdsp_fwd_data_ready
|| vfpu1_vdsp_fwd_data_ready;
//1.if ready is already be 1, just hold 1
//2.if producer are presumed to produce the result two cycles later,
// set ready to 1
//3.if producer wake up, set ready to 1
//4.clear ready to 0
assign mla_rdy_update = (mla_rdy || mla_data_ready || wake_up) && !rdy_clear;
//ready read signal
assign x_read_mla_rdy = mla_rdy_update;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mla_rdy <= 1'b1;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
mla_rdy <= 1'b1;
else if(x_write_en)
mla_rdy <= x_create_mla_rdy;
else
mla_rdy <= mla_rdy_update;
end
//==========================================================
// Write Back Valid
//==========================================================
//write back valid shows whether the result is written back
//into PRF : 1 stands for the result is in PRF
//-------------Update value of Write Back Bit---------------
//prepare write back signal
assign pipe3_wb = lsu_idu_wb_pipe3_wb_vreg_vld_dupx
&& (lsu_idu_wb_pipe3_wb_vreg_dupx[6:0] == vreg[6:0]);
assign pipe6_wb = vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx
&& (vfpu_idu_ex5_pipe6_wb_vreg_dupx[6:0] == vreg[6:0]);
assign pipe7_wb = vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx
&& (vfpu_idu_ex5_pipe7_wb_vreg_dupx[6:0] == vreg[6:0]);
assign write_back = wb
|| pipe3_wb
|| pipe6_wb
|| pipe7_wb;
//1.if wb_vld is already be 1, just hold 1
//2.if this result is writing back to PRF, set wb to 1
assign x_read_wb = wb_update;
assign wb_update = wb || write_back;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
wb <= 1'b1;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
wb <= 1'b1;
else if(x_write_en)
wb <= x_create_wb;
else
wb <= wb_update;
end
//==========================================================
// Vreg
//==========================================================
assign x_read_vreg[6:0] = vreg[6:0];
always @(posedge write_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vreg[6:0] <= 7'b0;
else if(x_write_en)
vreg[6:0] <= x_create_vreg[6:0];
else
vreg[6:0] <= vreg[6:0];
end
// &ModuleEnd; @259
endmodule |
module ct_idu_rf_pipe3_decd(
pipe3_decd_atomic,
pipe3_decd_inst_fls,
pipe3_decd_inst_ldr,
pipe3_decd_inst_size,
pipe3_decd_inst_type,
pipe3_decd_lsfifo,
pipe3_decd_off_0_extend,
pipe3_decd_offset,
pipe3_decd_offset_plus,
pipe3_decd_opcode,
pipe3_decd_shift,
pipe3_decd_sign_extend
);
// &Ports; @28
input [31:0] pipe3_decd_opcode;
output pipe3_decd_atomic;
output pipe3_decd_inst_fls;
output pipe3_decd_inst_ldr;
output [1 :0] pipe3_decd_inst_size;
output [1 :0] pipe3_decd_inst_type;
output pipe3_decd_lsfifo;
output pipe3_decd_off_0_extend;
output [11:0] pipe3_decd_offset;
output [12:0] pipe3_decd_offset_plus;
output [3 :0] pipe3_decd_shift;
output pipe3_decd_sign_extend;
// &Regs; @29
reg [3 :0] ldr_shift;
reg pipe3_decd_atomic;
reg pipe3_decd_inst_fls;
reg pipe3_decd_inst_ldr;
reg [1 :0] pipe3_decd_inst_size;
reg [1 :0] pipe3_decd_inst_type;
reg pipe3_decd_inst_vls;
reg pipe3_decd_lsfifo;
reg pipe3_decd_off_0_extend;
reg [11:0] pipe3_decd_offset;
reg [3 :0] pipe3_decd_shift;
reg pipe3_decd_sign_extend;
// &Wires; @30
wire [31:0] decd_op;
wire [12:0] pipe3_decd_offset_plus;
wire [31:0] pipe3_decd_opcode;
parameter BYTE = 2'b00,
HALF = 2'b01,
WORD = 2'b10,
DWORD = 2'b11;
//==========================================================
// Rename Input
//==========================================================
assign decd_op[31:0] = pipe3_decd_opcode[31:0];
//==========================================================
// Decode for offset shift
//==========================================================
// &CombBeg; @45
always @( decd_op[26:25])
begin
ldr_shift[3:0] = 4'b0;
case(decd_op[26:25])
2'b00:ldr_shift[0] = 1'b1;
2'b01:ldr_shift[1] = 1'b1;
2'b10:ldr_shift[2] = 1'b1;
2'b11:ldr_shift[3] = 1'b1;
default:ldr_shift[3:0] = 4'b0;
endcase
// &CombEnd; @54
end
//==========================================================
// Decode
//==========================================================
// &CombBeg; @59
always @( decd_op[31:0]
or ldr_shift[3:0])
begin
casez(decd_op[31:0])
//------------------------normal----------------------------
// ..28..24..20..16..12...8...4...0
32'b?????????????????000?????0000011: //lb
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b00;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b?????????????????001?????0000011: //lh
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b01;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b?????????????????010?????0000011: //lw
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b?????????????????100?????0000011: //lbu
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b00;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b?????????????????101?????0000011: //lhu
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b01;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b?????????????????110?????0000011: //lwu
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b?????????????????011?????0000011: //ld
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
//------------------------atomic----------------------------
// ..28..24..20..16..12...8...4...0
32'b00010??00000?????010?????0101111: //lr.w
begin
pipe3_decd_atomic = 1'b1;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b01;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b0;
end
// ..28..24..20..16..12...8...4...0
32'b00001????????????010?????0101111, //amoswap.w
32'b00000????????????010?????0101111, //amoadd .w
32'b00100????????????010?????0101111, //amoxor .w
32'b01100????????????010?????0101111, //amoand .w
32'b01000????????????010?????0101111, //amoor .w
32'b10000????????????010?????0101111, //amomin .w
32'b10100????????????010?????0101111, //amomax .w
32'b11000????????????010?????0101111, //amominu.w
32'b11100????????????010?????0101111: //amomaxu.w
begin
pipe3_decd_atomic = 1'b1;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b0;
end
// ..28..24..20..16..12...8...4...0
32'b00010??00000?????011?????0101111: //lr.d
begin
pipe3_decd_atomic = 1'b1;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b01;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b0;
end
// ..28..24..20..16..12...8...4...0
32'b00001????????????011?????0101111, //amoswap.d
32'b00000????????????011?????0101111, //amoadd .d
32'b00100????????????011?????0101111, //amoxor .d
32'b01100????????????011?????0101111, //amoand .d
32'b01000????????????011?????0101111, //amoor .d
32'b10000????????????011?????0101111, //amomin .d
32'b10100????????????011?????0101111, //amomax .d
32'b11000????????????011?????0101111, //amominu.d
32'b11100????????????011?????0101111: //amomaxu.d
begin
pipe3_decd_atomic = 1'b1;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b0;
end
//------------------------float-----------------------------
// ..28..24..20..16..12...8...4...0
32'b?????????????????001?????0000111: //flh
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b01;
pipe3_decd_inst_fls = 1'b1;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b?????????????????010?????0000111: //flw
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b1;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b?????????????????011?????0000111: //fld
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b1;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = decd_op[31:20];
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
//------------------------short-----------------------------
// ..28..24..20..16..12...8...4...0
32'b????????????????001???????????00: //c.fld
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b1;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = {4'b0,decd_op[6:5],decd_op[12:10],3'b0};
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b????????????????010???????????00: //c.lw
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = {5'b0,decd_op[5],decd_op[12:10],decd_op[6],2'b0};
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b????????????????011???????????00: //c.ld
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = {4'b0,decd_op[6:5],decd_op[12:10],3'b0};
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b????????????????001???????????10: //c.fldsp
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b1;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = {3'b0,decd_op[4:2],decd_op[12],decd_op[6:5],3'b0};
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b0;
end
// ..28..24..20..16..12...8...4...0
32'b????????????????010???????????10: //c.lwsp
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = {4'b0,decd_op[3:2],decd_op[12],decd_op[6:4],2'b0};
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b0;
end
// ..28..24..20..16..12...8...4...0
32'b????????????????011???????????10: //c.ldsp
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = {3'b0,decd_op[4:2],decd_op[12],decd_op[6:5],3'b0};
pipe3_decd_shift[3:0] = 4'b1;
pipe3_decd_inst_ldr = 1'b0;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b0;
end
// ..28..24..20..16..12...8...4...0
32'b00000????????????100?????0001011: //lrb
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b00;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b00100????????????100?????0001011: //lrh
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b01;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b01000????????????100?????0001011: //lrw
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b01100????????????100?????0001011: //lrd
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b10000????????????100?????0001011: //lrbu
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b00;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b10100????????????100?????0001011: //lrhu
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b01;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b11000????????????100?????0001011: //lrwu
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b00010????????????100?????0001011: //lurb
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b00;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b1;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b00110????????????100?????0001011: //lurh
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b01;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b1;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b01010????????????100?????0001011: //lurw
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b1;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b01110????????????100?????0001011: //lurd
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b1;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b10010????????????100?????0001011: //lurbu
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b00;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b1;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b10110????????????100?????0001011: //lurhu
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b01;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b1;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b11010????????????100?????0001011: //lurwu
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b0;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b1;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b01000????????????110?????0001011: //flrw
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b1;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b01100????????????110?????0001011: //flrd
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b1;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b0;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b01010????????????110?????0001011: //flurw
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b1;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b10;
pipe3_decd_inst_fls = 1'b1;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b1;
pipe3_decd_lsfifo = 1'b1;
end
// ..28..24..20..16..12...8...4...0
32'b01110????????????110?????0001011: //flurd
begin
pipe3_decd_atomic = 1'b0;
pipe3_decd_sign_extend = 1'b0;
pipe3_decd_inst_type[1:0] = 2'b00;
pipe3_decd_inst_size[1:0] = 2'b11;
pipe3_decd_inst_fls = 1'b1;
pipe3_decd_inst_vls = 1'b0;
pipe3_decd_offset[11:0] = 12'b0;
pipe3_decd_shift[3:0] = ldr_shift[3:0];
pipe3_decd_inst_ldr = 1'b1;
pipe3_decd_off_0_extend = 1'b1;
pipe3_decd_lsfifo = 1'b1;
end
//// ..28..24..20..16..12...8...4...0
//32'b????????????????????????????????: //template
//begin
// pipe3_decd_atomic = 1'b0;
// pipe3_decd_sign_extend = 1'b0;
// pipe3_decd_inst_type[1:0] = 2'b00;
// pipe3_decd_inst_size[1:0] = 2'b00;
// pipe3_decd_inst_fls = 1'b0;
// pipe3_decd_inst_vls = 1'b0;
// pipe3_decd_offset[11:0] = 12'b0;
// pipe3_decd_shift[3:0] = 4'b1;
// pipe3_decd_inst_ldr = 1'b0;
// pipe3_decd_off_0_extend = 1'b0;
//end
default:
begin
pipe3_decd_atomic = 1'bx;
pipe3_decd_sign_extend = 1'bx;
pipe3_decd_inst_type[1:0] = {2{1'bx}};
pipe3_decd_inst_size[1:0] = {2{1'bx}};
pipe3_decd_inst_fls = 1'bx;
pipe3_decd_inst_vls = 1'bx;
pipe3_decd_offset[11:0] = {12{1'bx}};
pipe3_decd_shift[3:0] = {4{1'bx}};
pipe3_decd_inst_ldr = 1'bx;
pipe3_decd_off_0_extend = 1'bx;
pipe3_decd_lsfifo = 1'bx;
end
endcase
// &CombEnd; @1045
end
// &Force("output","pipe3_decd_offset"); @1047
assign pipe3_decd_offset_plus[12:0] = {pipe3_decd_offset[11],pipe3_decd_offset[11:0]}
+ 13'h10;
//for vector decode
// &Force("output","pipe3_decd_inst_vls"); @1053
// &Force("output","pipe3_decd_atomic"); @1054
// &Force("output","pipe3_decd_unit_stride"); @1055
// &Force("output","pipe3_decd_inst_fof"); @1056
// &Force("output","pipe3_decd_vmask_vld"); @1057
// &CombBeg; @1082
// &CombEnd; @1092
// &CombBeg; @1098
// &CombEnd; @1106
// &CombBeg; @1115
// &CombEnd; @1123
// &CombBeg; @1129
// &CombEnd; @1143
// &CombBeg; @1145
// &CombEnd; @1165
// &Force("nonport","pipe3_decd_inst_vls"); @1167
// &ModuleEnd; @1171
endmodule |
module ct_idu_ir_decd(
x_alu_short,
x_bar,
x_bar_type,
x_csr,
x_ecall,
x_fp,
x_illegal,
x_load,
x_mfvr,
x_mtvr,
x_opcode,
x_pcall,
x_pcfifo,
x_rts,
x_store,
x_str,
x_sync,
x_type_alu,
x_type_staddr,
x_type_vload,
x_unit_stride,
x_vamo,
x_vdiv,
x_vec,
x_viq_srcv12_switch,
x_vmla_short,
x_vmla_type,
x_vmul,
x_vmul_unsplit,
x_vsetvl,
x_vsetvli,
x_vsew
);
// &Ports; @27
input x_illegal;
input [31:0] x_opcode;
input x_type_alu;
input x_type_staddr;
input x_type_vload;
input [2 :0] x_vsew;
output x_alu_short;
output x_bar;
output [3 :0] x_bar_type;
output x_csr;
output x_ecall;
output x_fp;
output x_load;
output x_mfvr;
output x_mtvr;
output x_pcall;
output x_pcfifo;
output x_rts;
output x_store;
output x_str;
output x_sync;
output x_unit_stride;
output x_vamo;
output x_vdiv;
output x_vec;
output x_viq_srcv12_switch;
output x_vmla_short;
output [2 :0] x_vmla_type;
output x_vmul;
output x_vmul_unsplit;
output x_vsetvl;
output x_vsetvli;
// &Regs; @28
// &Wires; @29
wire decd_alu_short;
wire decd_bar;
wire [3 :0] decd_bar_type;
wire decd_bar_type_sel;
wire decd_cmp_inst;
wire decd_csr;
wire decd_ecall;
wire decd_fmac_doub;
wire decd_fmac_half;
wire decd_fmac_sing;
wire decd_fp_inst;
wire decd_load;
wire decd_mfvr;
wire decd_mtvr;
wire decd_narr_vsft;
wire decd_opfvf;
wire decd_opfvv;
wire decd_opivi;
wire decd_opivv;
wire decd_opivx;
wire decd_opmvv;
wire decd_opmvx;
wire decd_pcall;
wire decd_pcfifo;
wire decd_permu;
wire decd_redu_vlgc;
wire decd_redu_vsum;
wire decd_return;
wire decd_rts;
wire decd_sca_fmac;
wire decd_sca_fmac_doub;
wire decd_sca_fmac_half;
wire decd_sca_fmac_sing;
wire decd_store;
wire decd_str;
wire decd_sub_call;
wire decd_sync;
wire decd_unit_stride;
wire decd_vamo;
wire decd_vdiv;
wire decd_vec_fmac;
wire decd_vec_fmac_doub;
wire decd_vec_fmac_half;
wire decd_vec_fmac_sing;
wire decd_vec_inst;
wire decd_vec_other;
wire decd_viq_srcv12_switch;
wire decd_vmac_norm;
wire decd_vmac_wide;
wire decd_vmla_short;
wire [2 :0] decd_vmla_type;
wire decd_vmul;
wire decd_vmul_norm;
wire decd_vmul_unsplit;
wire decd_vmul_wide;
wire decd_vsetvl;
wire decd_vsetvli;
wire x_alu_short;
wire x_bar;
wire [3 :0] x_bar_type;
wire x_csr;
wire x_ecall;
wire x_fp;
wire x_illegal;
wire x_load;
wire x_mfvr;
wire x_mtvr;
wire [31:0] x_opcode;
wire x_pcall;
wire x_pcfifo;
wire x_rts;
wire x_store;
wire x_str;
wire x_sync;
wire x_type_alu;
wire x_type_staddr;
wire x_type_vload;
wire x_unit_stride;
wire x_vamo;
wire x_vdiv;
wire x_vec;
wire x_viq_srcv12_switch;
wire x_vmla_short;
wire [2 :0] x_vmla_type;
wire x_vmul;
wire x_vmul_unsplit;
wire x_vsetvl;
wire x_vsetvli;
wire [2 :0] x_vsew;
//==========================================================
// Output Decode
//==========================================================
//CAUTION!!!
//illegal instruction keeps its opcode when pipedown from id stage
//ir decode should consider id stage illegal instruction
assign x_load = !x_illegal && decd_load;
assign x_store = !x_illegal && decd_store;
assign x_rts = !x_illegal && decd_rts;
assign x_pcall = !x_illegal && decd_pcall;
assign x_pcfifo = !x_illegal && decd_pcfifo;
assign x_bar = !x_illegal && decd_bar;
assign x_bar_type[3:0] = {4{!x_illegal}} & decd_bar_type[3:0];
assign x_vdiv = !x_illegal && decd_vdiv;
assign x_mfvr = !x_illegal && decd_mfvr;
assign x_mtvr = !x_illegal && decd_mtvr;
assign x_vmla_type[2:0] = {3{!x_illegal}} & decd_vmla_type[2:0];
assign x_str = !x_illegal && decd_str;
assign x_alu_short = !x_illegal && decd_alu_short;
assign x_vmla_short = !x_illegal && decd_vmla_short;
assign x_vmul_unsplit = !x_illegal && decd_vmul_unsplit;
assign x_vmul = !x_illegal && decd_vmul;
assign x_vsetvli = !x_illegal && decd_vsetvli;
assign x_vsetvl = !x_illegal && decd_vsetvl;
assign x_viq_srcv12_switch = !x_illegal && decd_viq_srcv12_switch;
assign x_unit_stride = !x_illegal && decd_unit_stride;
assign x_vamo = !x_illegal && decd_vamo;
assign x_vec = !x_illegal && decd_vec_inst;
assign x_fp = !x_illegal && decd_fp_inst;
assign x_csr = !x_illegal && decd_csr;
assign x_sync = !x_illegal && decd_sync;
assign x_ecall = !x_illegal && decd_ecall;
//==========================================================
// Short ALU
//==========================================================
//Long ALU do not forward data in EX1
assign decd_alu_short =
x_type_alu
&& !(({x_opcode[31:25],x_opcode[14:12],x_opcode[6:0]} == 17'b0100000_010_0110011) //pseudo_min
|| ({x_opcode[31:25],x_opcode[14:12],x_opcode[6:0]} == 17'b0110000_010_0110011) //pseudo_max
|| ({x_opcode[31:25],x_opcode[14:12],x_opcode[6:0]} == 17'b0100000_010_0111011) //pseudo_minw
|| ({x_opcode[31:25],x_opcode[14:12],x_opcode[6:0]} == 17'b0110000_010_0111011) //pseudo_maxw
|| ({x_opcode[31:25],x_opcode[14:12],x_opcode[6:0]} == 17'b0100000_011_0110011) //pseudo_minu
|| ({x_opcode[31:25],x_opcode[14:12],x_opcode[6:0]} == 17'b0110000_011_0110011) //pseudo_maxu
|| ({x_opcode[31:25],x_opcode[14:12],x_opcode[6:0]} == 17'b0100000_011_0111011) //pseudo_minuw
|| ({x_opcode[31:25],x_opcode[14:12],x_opcode[6:0]} == 17'b0110000_011_0111011) //pseudo_maxuw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00000_001_0001011)); //addsl
//==========================================================
// Load and Store
//==========================================================
//----------------------------------------------------------
// Load Instruction
//----------------------------------------------------------
//control whether inst issue to pipe3 or pipe4
assign decd_load =
({x_opcode[15:13],x_opcode[1:0]} == 5'b001_00) //c.fld
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b010_00) //c.lw
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b011_00) //c.ld
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b001_10) //c.fldsp
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b010_10) //c.lwsp
&& (x_opcode[11:7] != 5'b0)
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b011_10) //c.ldsp
&& (x_opcode[11:7] != 5'b0)
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b000_0000011) //lb
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b001_0000011) //lh
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b010_0000011) //lw
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b011_0000011) //ld
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b100_0000011) //lbu
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b101_0000011) //lhu
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b110_0000011) //lwu
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b001_0000111) //flh
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b010_0000111) //flw
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b011_0000111) //fld
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b000_0000111) //vld.b
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b101_0000111) //vld.h
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b110_0000111) //vld.w
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b111_0000111) //vld.sew
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00000_100_0001011) //lrb
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00100_100_0001011) //lrh
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01000_100_0001011) //lrw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01100_100_0001011) //lrd
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b10000_100_0001011) //lrbu
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b10100_100_0001011) //lrhu
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b11000_100_0001011) //lrwu
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00010_100_0001011) //lurb
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00110_100_0001011) //lurh
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01010_100_0001011) //lurw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01110_100_0001011) //lurd
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b10010_100_0001011) //lurbu
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b10110_100_0001011) //lurhu
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b11010_100_0001011) //lurwu
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00010_010_0101111) //lr.w
&& (x_opcode[24:20] == 5'b0)
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00010_011_0101111) //lr.d
&& (x_opcode[24:20] == 5'b0)
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01000_110_0001011) //flrw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01100_110_0001011) //flrd
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01010_110_0001011) //flurw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01110_110_0001011) //flurd
|| (x_opcode[14] ? x_type_vload : !x_type_staddr)
&& (({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00000_10_0101111) //(v)amoadd.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00001_10_0101111) //(v)amoswap.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00100_10_0101111) //(v)amoxor.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01100_10_0101111) //(v)amoand.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01000_10_0101111) //(v)amoor.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10000_10_0101111) //(v)amomin.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10100_10_0101111) //(v)amomax.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11000_10_0101111) //(v)amominu.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11100_10_0101111) //(v)amomaxu.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00000_11_0101111) //(v)amoadd.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00001_11_0101111) //(v)amoswap.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00100_11_0101111) //(v)amoxor.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01100_11_0101111) //(v)amoand.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01000_11_0101111) //(v)amoor.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10000_11_0101111) //(v)amomin.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10100_11_0101111) //(v)amomax.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11000_11_0101111) //(v)amominu.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11100_11_0101111)); //(v)amomaxu.d
//----------------------------------------------------------
// Store Instruction
//----------------------------------------------------------
//control whether inst issue to pipe3 or pipe4
assign decd_store =
({x_opcode[15:13],x_opcode[1:0]} == 5'b101_00) //c.fsd
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b110_00) //c.sw
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b111_00) //c.sd
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b101_10) //c.fsdsp
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b110_10) //c.swsp
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b111_10) //c.sdsp
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b000_0100011) //sb
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b001_0100011) //sh
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b010_0100011) //sw
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b011_0100011) //sd
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b001_0100111) //fsh
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b010_0100111) //fsw
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b011_0100111) //fsd
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b000_0100111) //vst.b
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b101_0100111) //vst.h
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b110_0100111) //vst.w
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b111_0100111) //vst.sew
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00000_101_0001011) //srb
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00100_101_0001011) //srh
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01000_101_0001011) //srw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01100_101_0001011) //srd
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00010_101_0001011) //surb
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00110_101_0001011) //surh
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01010_101_0001011) //surw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01110_101_0001011) //surd
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01000_111_0001011) //fsrw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01100_111_0001011) //fsrd
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01010_111_0001011) //fsurw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01110_111_0001011) //fsurd
// || ({x_opcode[14:12],x_opcode[6:0]} == 10'b000_0001111) //fence
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b001_0001111) //fence.i
|| ({x_opcode[31:25],x_opcode[14:0]} == 22'b0001001_000000001110011) //sfence.vma
|| ({x_opcode[31:25],x_opcode[14:0]} == 22'b0010001_000000001110011) //hfence.vvma
|| ({x_opcode[31:25],x_opcode[14:0]} == 22'b0110001_000000001110011) //hfence.gvma
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00011_010_0101111) //sc.w
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00011_011_0101111) //sc.d
|| (x_opcode[14:0] == 15'b000_00000_0001011) //cache extension instruction
|| (x_opcode[14] ? !x_type_vload : x_type_staddr)
&& (({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00000_10_0101111) //(v)amoadd.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00001_10_0101111) //(v)amoswap.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00100_10_0101111) //(v)amoxor.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01100_10_0101111) //(v)amoand.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01000_10_0101111) //(v)amoor.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10000_10_0101111) //(v)amomin.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10100_10_0101111) //(v)amomax.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11000_10_0101111) //(v)amominu.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11100_10_0101111) //(v)amomaxu.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00000_11_0101111) //(v)amoadd.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00001_11_0101111) //(v)amoswap.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00100_11_0101111) //(v)amoxor.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01100_11_0101111) //(v)amoand.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01000_11_0101111) //(v)amoor.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10000_11_0101111) //(v)amomin.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10100_11_0101111) //(v)amomax.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11000_11_0101111) //(v)amominu.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11100_11_0101111)); //(v)amomaxu.d
//----------------------------------------------------------
// Reg Offset Store Instruction
//----------------------------------------------------------
assign decd_str =
({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00000_101_0001011) //srb
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00100_101_0001011) //srh
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01000_101_0001011) //srw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01100_101_0001011) //srd
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00010_101_0001011) //surb
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00110_101_0001011) //surh
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01010_101_0001011) //surw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01110_101_0001011) //surd
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01000_111_0001011) //fsrw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01100_111_0001011) //fsrd
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01010_111_0001011) //fsurw
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b01110_111_0001011);//fsurd
//----------------------------------------------------------
// Fence lr/sc amo Instruction
//----------------------------------------------------------
assign decd_sync =
(x_opcode[31:0] == 32'h0180000b) //sync
|| (x_opcode[31:0] == 32'h0190000b) //sync.s
|| (x_opcode[31:0] == 32'h01a0000b) //sync.i
|| (x_opcode[31:0] == 32'h01b0000b) //sync.is
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b000_0001111) //fence
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b001_0001111) //fence.i
|| ({x_opcode[31:25],x_opcode[14:0]} == 22'b0001001_000000001110011) //sfence.vma
|| ({x_opcode[31:25],x_opcode[14:0]} == 22'b0010001_000000001110011) //hfence.vvma
|| ({x_opcode[31:25],x_opcode[14:0]} == 22'b0110001_000000001110011) //hfence.gvma
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00010_010_0101111) //lr.w
&& (x_opcode[24:20] == 5'b0)
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00010_011_0101111) //lr.d
&& (x_opcode[24:20] == 5'b0)
|| (x_opcode[14] ? x_type_vload : !x_type_staddr)
&& (({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00000_10_0101111) //(v)amoadd.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00001_10_0101111) //(v)amoswap.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00100_10_0101111) //(v)amoxor.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01100_10_0101111) //(v)amoand.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01000_10_0101111) //(v)amoor.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10000_10_0101111) //(v)amomin.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10100_10_0101111) //(v)amomax.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11000_10_0101111) //(v)amominu.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11100_10_0101111) //(v)amomaxu.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00000_11_0101111) //(v)amoadd.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00001_11_0101111) //(v)amoswap.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00100_11_0101111) //(v)amoxor.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01100_11_0101111) //(v)amoand.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01000_11_0101111) //(v)amoor.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10000_11_0101111) //(v)amomin.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10100_11_0101111) //(v)amomax.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11000_11_0101111) //(v)amominu.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11100_11_0101111)) //(v)amomaxu.d
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00011_010_0101111) //sc.w
|| ({x_opcode[31:27],x_opcode[14:12],x_opcode[6:0]} == 15'b00011_011_0101111) //sc.d
|| (x_opcode[14] ? !x_type_vload : x_type_staddr)
&& (({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00000_10_0101111) //(v)amoadd.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00001_10_0101111) //(v)amoswap.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00100_10_0101111) //(v)amoxor.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01100_10_0101111) //(v)amoand.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01000_10_0101111) //(v)amoor.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10000_10_0101111) //(v)amomin.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10100_10_0101111) //(v)amomax.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11000_10_0101111) //(v)amominu.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11100_10_0101111) //(v)amomaxu.w
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00000_11_0101111) //(v)amoadd.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00001_11_0101111) //(v)amoswap.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b00100_11_0101111) //(v)amoxor.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01100_11_0101111) //(v)amoand.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b01000_11_0101111) //(v)amoor.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10000_11_0101111) //(v)amomin.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b10100_11_0101111) //(v)amomax.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11000_11_0101111) //(v)amominu.d
|| ({x_opcode[31:27],x_opcode[13:12],x_opcode[6:0]} == 14'b11100_11_0101111)); //(v)amomaxu.d
//==========================================================
// BJU Information
//==========================================================
//----------------------------------------------------------
// Return Stack Related Instruction
//----------------------------------------------------------
assign decd_return =
({x_opcode[15:12], x_opcode[1:0]} == 6'b1000_10) //c.jr x1/x5
&& (x_opcode[6:2] == 5'b0)
&& ((x_opcode[11:7] == 5'd1) || (x_opcode[11:7] == 5'd5))
|| ({x_opcode[15:12], x_opcode[1:0]} == 6'b1001_10) //c.jalr x5
&& (x_opcode[11:7] == 5'd5) && (x_opcode[6:2] == 5'b0)
|| ({x_opcode[14:12], x_opcode[6:0]} == 10'b000_1100111) //jalr x1/x5
&& ((x_opcode[19:15] == 5'd1) || (x_opcode[19:15] == 5'd5))
&& (x_opcode[19:15] != x_opcode[11:7]);
assign decd_sub_call =
({x_opcode[15:12], x_opcode[1:0]} == 6'b1001_10) //c.jalr
&& (x_opcode[11:7] != 5'b0) && (x_opcode[6:2] == 5'b0)
|| (x_opcode[6:0] == 7'b1101111) //jal x1/x5
&& ((x_opcode[11:7] == 5'd1) || (x_opcode[11:7] == 5'd5))
|| ({x_opcode[14:12], x_opcode[6:0]} == 10'b000_1100111) //jalr x1/x5
&& ((x_opcode[11:7] == 5'd1) || (x_opcode[11:7] == 5'd5));
assign decd_rts = decd_return;
assign decd_pcall = decd_sub_call;
//----------------------------------------------------------
// PCFIFO Instruction
//----------------------------------------------------------
assign decd_pcfifo = ({x_opcode[15:13],x_opcode[1:0]} == 5'b101_01) //c.j
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b110_01) //c.beqz
|| ({x_opcode[15:13],x_opcode[1:0]} == 5'b111_01) //c.bnez
|| ({x_opcode[15:12],x_opcode[1:0]} == 6'b1000_10) //c.jr
&& (x_opcode[11:7] != 5'b0)
&& (x_opcode[6:2] == 5'b0)
|| ({x_opcode[15:12],x_opcode[1:0]} == 6'b1001_10) //c.jalr
&& (x_opcode[11:7] != 5'b0)
&& (x_opcode[6:2] == 5'b0)
|| (x_opcode[6:0] == 7'b1101111) //jal
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b000_1100111) //jalr
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b000_1100011) //beq
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b001_1100011) //bne
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b100_1100011) //blt
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b101_1100011) //bge
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b110_1100011) //bltu
|| ({x_opcode[14:12],x_opcode[6:0]} == 10'b111_1100011) //bgeu
|| (x_opcode[6:0] == 7'b0010111) //auipc
|| (x_opcode[6:0] == 7'b0011111); //pseudo auipc
//==========================================================
// Barrier Instruction
//==========================================================
assign decd_bar = ({x_opcode[14:12],x_opcode[6:0]} == 10'b000_0001111); //fence
//treat all bar_type as 1111 except 1010 to preven
//lsiq issue dead lock
assign decd_bar_type_sel = (x_opcode[26] || x_opcode[24])
&& !(x_opcode[27] || x_opcode[25])
&& (x_opcode[22] || x_opcode[20])
&& !(x_opcode[23] || x_opcode[21]);
assign decd_bar_type[3:0] = (decd_bar_type_sel)
? 4'b1010 : 4'b1111;
//==========================================================
// Special Instruction
//==========================================================
assign decd_csr = (x_opcode[6:0] == 7'b1110011)
&& (x_opcode[14:12] != 3'b000);
assign decd_ecall = (x_opcode[31:0] == 32'h00000073);
//==========================================================
// Vector Instruction
//==========================================================
//CAUTION!!!
//illegal instruction keeps its opcode when pipedown from id stage
//ir decode should consider id stage illegal instruction
assign decd_vec_inst = (x_opcode[6:0]==7'b1010111);
assign decd_fp_inst = (x_opcode[6:0] == 7'b1010011)
|| ({x_opcode[6:4],x_opcode[1:0]} == 5'b10011);
assign decd_opivv = (x_opcode[14:12] == 3'b000);
assign decd_opivx = (x_opcode[14:12] == 3'b100);
assign decd_opivi = (x_opcode[14:12] == 3'b011);
assign decd_opmvv = (x_opcode[14:12] == 3'b010);
assign decd_opmvx = (x_opcode[14:12] == 3'b110);
assign decd_opfvv = (x_opcode[14:12] == 3'b001);
assign decd_opfvf = (x_opcode[14:12] == 3'b101);
assign decd_vdiv = ({x_opcode[31:27],x_opcode[6:0]} == 12'b00011_1010011) //fdiv.t
|| ({x_opcode[31:27],x_opcode[6:0]} == 12'b01011_1010011) //fsqrt.t
|| (x_opcode[31:28]== 4'b1000) && //vdiv vdivu vrem vremu
(decd_opmvv || decd_opmvx) && decd_vec_inst
|| (x_opcode[31:26]== 6'b100000) && //vfdiv
(decd_opfvv || decd_opfvf) && decd_vec_inst
|| (x_opcode[31:26]== 6'b100001) && //vfrdiv
( decd_opfvf) && decd_vec_inst
|| (x_opcode[31:26]== 6'b100011) && //vfsqrt
(decd_opfvv ) && (x_opcode[19:15]==5'b00000) && decd_vec_inst;
assign decd_mfvr = ({x_opcode[31:20],x_opcode[14:12],x_opcode[6:0]} == 22'b111000000000_000_1010011) //fmv.x.w
|| ({x_opcode[31:20],x_opcode[14:12],x_opcode[6:0]} == 22'b111001000000_000_1010011) //fmv.x.h
|| ({x_opcode[31:20],x_opcode[14:12],x_opcode[6:0]} == 22'b111000000000_001_1010011) //fclass.s
|| ({x_opcode[31:20],x_opcode[14:12],x_opcode[6:0]} == 22'b111001000000_001_1010011) //fclass.h
|| ({x_opcode[31:20],x_opcode[14:12],x_opcode[6:0]} == 22'b111000100000_000_1010011) //fmv.x.d
|| ({x_opcode[31:20],x_opcode[14:12],x_opcode[6:0]} == 22'b111000100000_001_1010011) //fclass.w
|| (x_opcode[31:25] == 7'b001100_1) && (x_opcode[14:12]== 3'b010) && decd_vec_inst //vext
|| (x_opcode[31:25] == 7'b0010001) && (x_opcode[19:12]== 8'b00000_001) && decd_vec_inst //vfmv.f.s
|| (x_opcode[31:25] == 7'b1010001) && (x_opcode[14:12]==3'b010) && (x_opcode[6:0]==7'b1010011) //feq.d
|| (x_opcode[31:25] == 7'b1010001) && (x_opcode[14:12]==3'b001) && (x_opcode[6:0]==7'b1010011) //flt.d
|| (x_opcode[31:25] == 7'b1010001) && (x_opcode[14:12]==3'b000) && (x_opcode[6:0]==7'b1010011) //fle.d
|| (x_opcode[31:25] == 7'b1010000) && (x_opcode[14:12]==3'b010) && (x_opcode[6:0]==7'b1010011) //feq.s
|| (x_opcode[31:25] == 7'b1010000) && (x_opcode[14:12]==3'b001) && (x_opcode[6:0]==7'b1010011) //flt.s
|| (x_opcode[31:25] == 7'b1010000) && (x_opcode[14:12]==3'b000) && (x_opcode[6:0]==7'b1010011) //fle.s
|| (x_opcode[31:25] == 7'b1010010) && (x_opcode[14:12]==3'b010) && (x_opcode[6:0]==7'b1010011) //feq.h
|| (x_opcode[31:25] == 7'b1010010) && (x_opcode[14:12]==3'b001) && (x_opcode[6:0]==7'b1010011) //flt.h
|| (x_opcode[31:25] == 7'b1010010) && (x_opcode[14:12]==3'b000) && (x_opcode[6:0]==7'b1010011); //fle.h
assign decd_mtvr = ({x_opcode[31:20],x_opcode[14:12],x_opcode[6:0]} == 22'b111100000000_000_1010011) //fmv.w.x
|| ({x_opcode[31:20],x_opcode[14:12],x_opcode[6:0]} == 22'b111101000000_000_1010011) //fmv.h.x
|| ({x_opcode[31:20],x_opcode[14:12],x_opcode[6:0]} == 22'b111100100000_000_1010011) //fmv.d.x
|| (x_opcode[31:20]== 12'b001101_1_00000) && decd_opmvx && decd_vec_inst //vmv.s.x
|| (x_opcode[31:20]== 12'b010111_1_00000) && decd_opivx && decd_vec_inst //vmv.v.x
|| (x_opcode[31:20]== 12'b001100_1_00000) && decd_opfvf && decd_vec_inst; //vfmv.s.f
//type info for vfpu internal forward
assign decd_vmla_type[2:0] = {3{decd_vmac_norm && !(x_opcode[31:28]== 4'b1010)}} & 3'b110 //vmla_type[2]==1 is used specially for integer vmac inst
|{3{decd_vmac_wide}} & 3'b110
|{3{decd_redu_vsum}} & 3'b101
|{3{decd_vec_other}} & 3'b100
|{3{decd_fmac_half}} & 3'b011
|{3{decd_fmac_sing}} & 3'b010
|{3{decd_fmac_doub}} & 3'b001;
assign decd_redu_vsum = (x_opcode[31:27]== 5'b10011) //vwredusumu vwredusm
&& decd_opivv && decd_vec_inst
||((x_opcode[31:26]== 6'b000000) // vredsum
|| (x_opcode[31:28]== 4'b0001)) // vredminu vredmin vredmaxu vredmax
&& decd_opmvv && decd_vec_inst;
assign decd_redu_vlgc = ((x_opcode[31:26]== 6'b000001)
||(x_opcode[31:26]== 6'b000010)
||(x_opcode[31:26]== 6'b000011)) //vredand vredor vredxor
&& decd_opmvv && decd_vec_inst;
assign decd_narr_vsft = (x_opcode[31:28]== 4'b1011) //vnsrl vnsra vnclipu vnclip
&& (decd_opivv || decd_opivx || decd_opivi) && decd_vec_inst;
assign decd_cmp_inst = (x_opcode[31:29]==3'b011) //compare inst
&& (decd_opivv || decd_opivx || decd_opivi) && decd_vec_inst;
assign decd_permu = (x_opcode[31:26]==6'b001100) //vrgather
&& (decd_opivv || decd_opivx || decd_opivi) && decd_vec_inst
|| (x_opcode[31:27]==5'b00111) //vslide
&& (decd_opivx || decd_opivi || decd_opmvx) && decd_vec_inst
|| (x_opcode[31:26]==6'b010111)//vcompress
&& decd_opmvv && decd_vec_inst;
assign decd_vec_other = decd_redu_vlgc || decd_narr_vsft || decd_cmp_inst || decd_permu;
assign decd_vec_fmac = ((x_opcode[31:28] == 4'b1011) ||(x_opcode[31:28] == 4'b1111))
&& (decd_opfvv || decd_opfvf) ;
assign decd_sca_fmac = ({x_opcode[6:4],x_opcode[1:0]} == 5'b100_11);
assign decd_vec_fmac_half = (x_vsew[2:0] == 3'b001) && !(&x_opcode[31:28]);
assign decd_vec_fmac_sing = (x_vsew[2:0] == 3'b010) && !(&x_opcode[31:28]);
assign decd_vec_fmac_doub = (x_vsew[2:0] == 3'b011) && !(&x_opcode[31:28])
|| (x_vsew[2:0] == 3'b010) && (&x_opcode[31:28]);
assign decd_sca_fmac_half = (x_opcode[26:25] == 2'b10);
assign decd_sca_fmac_sing = (x_opcode[26:25] == 2'b00);
assign decd_sca_fmac_doub = (x_opcode[26:25] == 2'b01);
assign decd_fmac_half = decd_sca_fmac_half && decd_sca_fmac
|| decd_vec_fmac_half && decd_vec_fmac;
assign decd_fmac_sing = decd_sca_fmac_sing && decd_sca_fmac
|| decd_vec_fmac_sing && decd_vec_fmac;
assign decd_fmac_doub = decd_sca_fmac_doub && decd_sca_fmac
|| decd_vec_fmac_doub && decd_vec_fmac;
//vfpu back to back issue
assign decd_vmla_short = decd_redu_vsum ||decd_redu_vlgc || decd_narr_vsft
|| decd_cmp_inst || decd_permu;
//||decd_vmac_norm || decd_vmac_wide;
//pipe7 vmul_unsplit will lch fail pipe6 vmul
assign decd_vmul_unsplit = decd_vmul_norm || decd_vmac_norm;
assign decd_vmul_norm = (x_opcode[31:26]== 6'b100111) //vsmul
&& (decd_opivv || decd_opivx) && decd_vec_inst
|| (x_opcode[31:28]== 4'b1001) //vmulhu vmul vmulhsu vmulh
&& (decd_opmvv || decd_opmvx) && decd_vec_inst;
assign decd_vmac_norm =((x_opcode[31:26]== 6'b101001) // vmadd
||(x_opcode[31:26]== 6'b101011) // vnmsub
||(x_opcode[31:26]== 6'b101101) // vmacc
||(x_opcode[31:26]== 6'b101111)) // vnmsac
&& (decd_opmvv || decd_opmvx) && decd_vec_inst;
assign decd_vmul_wide =((x_opcode[31:26]== 6'b111000)
||(x_opcode[31:27]== 5'b11101)) // vwmulu vwmulsu vwmul
&& (decd_opmvv || decd_opmvx) && decd_vec_inst;
assign decd_vmac_wide = (x_opcode[31:28]== 4'b1111) //vwsmaccu vwsmacc vwsmaccsu vwsmaccus
&& (decd_opivv || decd_opivx) && decd_vec_inst
|| (x_opcode[31:28]== 4'b1111) // vwmaccu vwmacc vwmaccsu vwmaccus
&& (decd_opmvv || decd_opmvx) && decd_vec_inst;
assign decd_vmul = decd_vmul_norm || decd_vmul_wide || decd_vmac_norm || decd_vmac_wide;
assign decd_vsetvli = (x_opcode[31]== 1'b0) && (x_opcode[14:12]==3'b111) && (x_opcode[6:0]==7'b1010111);
assign decd_vsetvl = (x_opcode[31:25]== 7'b100_0000) && (x_opcode[14:12]==3'b111) && (x_opcode[6:0]==7'b1010111);
assign decd_viq_srcv12_switch = ((x_opcode[31:26]== 6'b101001)||(x_opcode[31:26]== 6'b101011)) //vmadd vmnsub
&& (decd_opmvv || decd_opmvx) && decd_vec_inst //vfmadd
|| ((x_opcode[31:28]== 4'b1010) && (decd_opfvv || decd_opfvf)) && decd_vec_inst
|| (x_opcode[31:26] == 6'b100010) && decd_opfvv && decd_vec_inst;
assign decd_unit_stride = (x_opcode[27:26]== 2'b0) && (x_opcode[31:29]== 3'b000);
assign decd_vamo = (x_opcode[6:0]== 7'b0101111) || |x_opcode[31:29]; //zvlsseg also use this signal for vmb
// &ModuleEnd; @511
endmodule |
module ct_idu_rf_prf_vregfile(
dp_prf_rf_pipe5_srcv0_vreg,
dp_prf_rf_pipe6_srcv0_vreg,
dp_prf_rf_pipe6_srcv1_vreg,
dp_prf_rf_pipe6_srcv2_vreg,
dp_prf_rf_pipe6_srcvm_vreg,
dp_prf_rf_pipe7_srcv0_vreg,
dp_prf_rf_pipe7_srcv1_vreg,
dp_prf_rf_pipe7_srcv2_vreg,
dp_prf_rf_pipe7_srcvm_vreg,
lsu_idu_wb_pipe3_wb_vreg_data,
lsu_idu_wb_pipe3_wb_vreg_expand,
lsu_idu_wb_pipe3_wb_vreg_vld,
prf_dp_rf_pipe5_srcv0_vreg_data,
prf_dp_rf_pipe6_srcv0_vreg_data,
prf_dp_rf_pipe6_srcv1_vreg_data,
prf_dp_rf_pipe6_srcv2_vreg_data,
prf_dp_rf_pipe6_srcvm_vreg_data,
prf_dp_rf_pipe7_srcv0_vreg_data,
prf_dp_rf_pipe7_srcv1_vreg_data,
prf_dp_rf_pipe7_srcv2_vreg_data,
prf_dp_rf_pipe7_srcvm_vreg_data,
vfpu_idu_ex5_pipe6_wb_vreg_data,
vfpu_idu_ex5_pipe6_wb_vreg_expand,
vfpu_idu_ex5_pipe6_wb_vreg_vld,
vfpu_idu_ex5_pipe7_wb_vreg_data,
vfpu_idu_ex5_pipe7_wb_vreg_expand,
vfpu_idu_ex5_pipe7_wb_vreg_vld
);
// &Ports; @26
input [5 :0] dp_prf_rf_pipe5_srcv0_vreg;
input [5 :0] dp_prf_rf_pipe6_srcv0_vreg;
input [5 :0] dp_prf_rf_pipe6_srcv1_vreg;
input [5 :0] dp_prf_rf_pipe6_srcv2_vreg;
input [5 :0] dp_prf_rf_pipe6_srcvm_vreg;
input [5 :0] dp_prf_rf_pipe7_srcv0_vreg;
input [5 :0] dp_prf_rf_pipe7_srcv1_vreg;
input [5 :0] dp_prf_rf_pipe7_srcv2_vreg;
input [5 :0] dp_prf_rf_pipe7_srcvm_vreg;
input [63:0] lsu_idu_wb_pipe3_wb_vreg_data;
input [63:0] lsu_idu_wb_pipe3_wb_vreg_expand;
input lsu_idu_wb_pipe3_wb_vreg_vld;
input [63:0] vfpu_idu_ex5_pipe6_wb_vreg_data;
input [63:0] vfpu_idu_ex5_pipe6_wb_vreg_expand;
input vfpu_idu_ex5_pipe6_wb_vreg_vld;
input [63:0] vfpu_idu_ex5_pipe7_wb_vreg_data;
input [63:0] vfpu_idu_ex5_pipe7_wb_vreg_expand;
input vfpu_idu_ex5_pipe7_wb_vreg_vld;
output [63:0] prf_dp_rf_pipe5_srcv0_vreg_data;
output [63:0] prf_dp_rf_pipe6_srcv0_vreg_data;
output [63:0] prf_dp_rf_pipe6_srcv1_vreg_data;
output [63:0] prf_dp_rf_pipe6_srcv2_vreg_data;
output [63:0] prf_dp_rf_pipe6_srcvm_vreg_data;
output [63:0] prf_dp_rf_pipe7_srcv0_vreg_data;
output [63:0] prf_dp_rf_pipe7_srcv1_vreg_data;
output [63:0] prf_dp_rf_pipe7_srcv2_vreg_data;
output [63:0] prf_dp_rf_pipe7_srcvm_vreg_data;
// &Regs; @27
// &Wires; @28
wire [63:0] prf_dp_rf_pipe5_srcv0_vreg_data;
wire [63:0] prf_dp_rf_pipe6_srcv0_vreg_data;
wire [63:0] prf_dp_rf_pipe6_srcv1_vreg_data;
wire [63:0] prf_dp_rf_pipe6_srcv2_vreg_data;
wire [63:0] prf_dp_rf_pipe6_srcvm_vreg_data;
wire [63:0] prf_dp_rf_pipe7_srcv0_vreg_data;
wire [63:0] prf_dp_rf_pipe7_srcv1_vreg_data;
wire [63:0] prf_dp_rf_pipe7_srcv2_vreg_data;
wire [63:0] prf_dp_rf_pipe7_srcvm_vreg_data;
// &Instance("gated_clk_cell", "x_vreg_gated_clk"); @38
// &Connect(.clk_in (forever_cpuclk), @39
// .external_en (1'b0), @40
// .global_en (cp0_yy_clk_en), @41
// .module_en (cp0_idu_icg_en), @42
// .local_en (vreg_clk_en), @43
// .clk_out (vreg_top_clk)); @44
// &ConnRule(s/^x_/vreg0_/); @49
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg0"); @50
// &ConnRule(s/^x_/vreg1_/); @51
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg1"); @52
// &ConnRule(s/^x_/vreg2_/); @53
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg2"); @54
// &ConnRule(s/^x_/vreg3_/); @55
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg3"); @56
// &ConnRule(s/^x_/vreg4_/); @57
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg4"); @58
// &ConnRule(s/^x_/vreg5_/); @59
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg5"); @60
// &ConnRule(s/^x_/vreg6_/); @61
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg6"); @62
// &ConnRule(s/^x_/vreg7_/); @63
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg7"); @64
// &ConnRule(s/^x_/vreg8_/); @65
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg8"); @66
// &ConnRule(s/^x_/vreg9_/); @67
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg9"); @68
// &ConnRule(s/^x_/vreg10_/); @69
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg10"); @70
// &ConnRule(s/^x_/vreg11_/); @71
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg11"); @72
// &ConnRule(s/^x_/vreg12_/); @73
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg12"); @74
// &ConnRule(s/^x_/vreg13_/); @75
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg13"); @76
// &ConnRule(s/^x_/vreg14_/); @77
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg14"); @78
// &ConnRule(s/^x_/vreg15_/); @79
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg15"); @80
// &ConnRule(s/^x_/vreg16_/); @81
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg16"); @82
// &ConnRule(s/^x_/vreg17_/); @83
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg17"); @84
// &ConnRule(s/^x_/vreg18_/); @85
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg18"); @86
// &ConnRule(s/^x_/vreg19_/); @87
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg19"); @88
// &ConnRule(s/^x_/vreg20_/); @89
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg20"); @90
// &ConnRule(s/^x_/vreg21_/); @91
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg21"); @92
// &ConnRule(s/^x_/vreg22_/); @93
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg22"); @94
// &ConnRule(s/^x_/vreg23_/); @95
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg23"); @96
// &ConnRule(s/^x_/vreg24_/); @97
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg24"); @98
// &ConnRule(s/^x_/vreg25_/); @99
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg25"); @100
// &ConnRule(s/^x_/vreg26_/); @101
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg26"); @102
// &ConnRule(s/^x_/vreg27_/); @103
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg27"); @104
// &ConnRule(s/^x_/vreg28_/); @105
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg28"); @106
// &ConnRule(s/^x_/vreg29_/); @107
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg29"); @108
// &ConnRule(s/^x_/vreg30_/); @109
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg30"); @110
// &ConnRule(s/^x_/vreg31_/); @111
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg31"); @112
// &ConnRule(s/^x_/vreg32_/); @113
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg32"); @114
// &ConnRule(s/^x_/vreg33_/); @115
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg33"); @116
// &ConnRule(s/^x_/vreg34_/); @117
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg34"); @118
// &ConnRule(s/^x_/vreg35_/); @119
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg35"); @120
// &ConnRule(s/^x_/vreg36_/); @121
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg36"); @122
// &ConnRule(s/^x_/vreg37_/); @123
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg37"); @124
// &ConnRule(s/^x_/vreg38_/); @125
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg38"); @126
// &ConnRule(s/^x_/vreg39_/); @127
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg39"); @128
// &ConnRule(s/^x_/vreg40_/); @129
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg40"); @130
// &ConnRule(s/^x_/vreg41_/); @131
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg41"); @132
// &ConnRule(s/^x_/vreg42_/); @133
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg42"); @134
// &ConnRule(s/^x_/vreg43_/); @135
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg43"); @136
// &ConnRule(s/^x_/vreg44_/); @137
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg44"); @138
// &ConnRule(s/^x_/vreg45_/); @139
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg45"); @140
// &ConnRule(s/^x_/vreg46_/); @141
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg46"); @142
// &ConnRule(s/^x_/vreg47_/); @143
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg47"); @144
// &ConnRule(s/^x_/vreg48_/); @145
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg48"); @146
// &ConnRule(s/^x_/vreg49_/); @147
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg49"); @148
// &ConnRule(s/^x_/vreg50_/); @149
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg50"); @150
// &ConnRule(s/^x_/vreg51_/); @151
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg51"); @152
// &ConnRule(s/^x_/vreg52_/); @153
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg52"); @154
// &ConnRule(s/^x_/vreg53_/); @155
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg53"); @156
// &ConnRule(s/^x_/vreg54_/); @157
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg54"); @158
// &ConnRule(s/^x_/vreg55_/); @159
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg55"); @160
// &ConnRule(s/^x_/vreg56_/); @161
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg56"); @162
// &ConnRule(s/^x_/vreg57_/); @163
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg57"); @164
// &ConnRule(s/^x_/vreg58_/); @165
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg58"); @166
// &ConnRule(s/^x_/vreg59_/); @167
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg59"); @168
// &ConnRule(s/^x_/vreg60_/); @169
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg60"); @170
// &ConnRule(s/^x_/vreg61_/); @171
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg61"); @172
// &ConnRule(s/^x_/vreg62_/); @173
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg62"); @174
// &ConnRule(s/^x_/vreg63_/); @175
// &Instance("ct_idu_rf_prf_gated_vreg", "x_ct_idu_rf_prf_vreg63"); @176
// &CombBeg; @260
// &CombEnd; @328
// &CombBeg; @333
// &CombEnd; @401
// &CombBeg; @406
// &CombEnd; @474
// &CombBeg; @479
// &CombEnd; @547
// &CombBeg; @552
// &CombEnd; @620
// &CombBeg; @625
// &CombEnd; @693
// &CombBeg; @698
// &CombEnd; @766
// &CombBeg; @771
// &CombEnd; @839
// &CombBeg; @844
// &CombEnd; @912
// &Force("bus","dp_prf_rf_pipe5_srcv0_vreg",5,0); @915
// &Force("bus","dp_prf_rf_pipe6_srcv0_vreg",5,0); @916
// &Force("bus","dp_prf_rf_pipe6_srcv1_vreg",5,0); @917
// &Force("bus","dp_prf_rf_pipe6_srcv2_vreg",5,0); @918
// &Force("bus","dp_prf_rf_pipe6_srcvm_vreg",5,0); @919
// &Force("bus","dp_prf_rf_pipe7_srcv0_vreg",5,0); @920
// &Force("bus","dp_prf_rf_pipe7_srcv1_vreg",5,0); @921
// &Force("bus","dp_prf_rf_pipe7_srcv2_vreg",5,0); @922
// &Force("bus","dp_prf_rf_pipe7_srcvm_vreg",5,0); @923
// &Force("bus","lsu_idu_wb_pipe3_wb_vreg_data",63,0); @924
// &Force("bus","lsu_idu_wb_pipe3_wb_vreg_expand",63,0); @925
// &Force("bus","vfpu_idu_ex5_pipe6_wb_vreg_data",63,0); @926
// &Force("bus","vfpu_idu_ex5_pipe6_wb_vreg_expand",63,0); @927
// &Force("bus","vfpu_idu_ex5_pipe7_wb_vreg_data",63,0); @928
// &Force("bus","vfpu_idu_ex5_pipe7_wb_vreg_expand",63,0); @929
// &Force("input","dp_prf_rf_pipe5_srcv0_vreg"); @931
// &Force("input","dp_prf_rf_pipe6_srcv0_vreg"); @932
// &Force("input","dp_prf_rf_pipe6_srcv1_vreg"); @933
// &Force("input","dp_prf_rf_pipe6_srcv2_vreg"); @934
// &Force("input","dp_prf_rf_pipe6_srcvm_vreg"); @935
// &Force("input","dp_prf_rf_pipe7_srcv0_vreg"); @936
// &Force("input","dp_prf_rf_pipe7_srcv1_vreg"); @937
// &Force("input","dp_prf_rf_pipe7_srcv2_vreg"); @938
// &Force("input","dp_prf_rf_pipe7_srcvm_vreg"); @939
// &Force("input","lsu_idu_wb_pipe3_wb_vreg_data"); @940
// &Force("input","lsu_idu_wb_pipe3_wb_vreg_vld"); @941
// &Force("input","lsu_idu_wb_pipe3_wb_vreg_expand"); @942
// &Force("input","vfpu_idu_ex5_pipe6_wb_vreg_data"); @943
// &Force("input","vfpu_idu_ex5_pipe6_wb_vreg_vld"); @944
// &Force("input","vfpu_idu_ex5_pipe6_wb_vreg_expand"); @945
// &Force("input","vfpu_idu_ex5_pipe7_wb_vreg_data"); @946
// &Force("input","vfpu_idu_ex5_pipe7_wb_vreg_vld"); @947
// &Force("input","vfpu_idu_ex5_pipe7_wb_vreg_expand"); @948
assign prf_dp_rf_pipe5_srcv0_vreg_data[63:0] = 64'b0;
assign prf_dp_rf_pipe6_srcv0_vreg_data[63:0] = 64'b0;
assign prf_dp_rf_pipe6_srcv1_vreg_data[63:0] = 64'b0;
assign prf_dp_rf_pipe6_srcv2_vreg_data[63:0] = 64'b0;
assign prf_dp_rf_pipe6_srcvm_vreg_data[63:0] = 64'b0;
assign prf_dp_rf_pipe7_srcv0_vreg_data[63:0] = 64'b0;
assign prf_dp_rf_pipe7_srcv1_vreg_data[63:0] = 64'b0;
assign prf_dp_rf_pipe7_srcv2_vreg_data[63:0] = 64'b0;
assign prf_dp_rf_pipe7_srcvm_vreg_data[63:0] = 64'b0;
// &ModuleEnd; @962
endmodule |
module ct_idu_ir_vrt(
dp_vrt_inst0_dst_vreg,
dp_vrt_inst0_dstv_reg,
dp_vrt_inst0_dstv_vld,
dp_vrt_inst0_srcv0_reg,
dp_vrt_inst0_srcv0_vld,
dp_vrt_inst0_srcv1_reg,
dp_vrt_inst0_srcv1_vld,
dp_vrt_inst0_srcv2_vld,
dp_vrt_inst0_srcvm_vld,
dp_vrt_inst0_vmla,
dp_vrt_inst1_dst_vreg,
dp_vrt_inst1_dstv_reg,
dp_vrt_inst1_dstv_vld,
dp_vrt_inst1_srcv0_reg,
dp_vrt_inst1_srcv0_vld,
dp_vrt_inst1_srcv1_reg,
dp_vrt_inst1_srcv1_vld,
dp_vrt_inst1_srcv2_vld,
dp_vrt_inst1_srcvm_vld,
dp_vrt_inst1_vmla,
dp_vrt_inst2_dst_vreg,
dp_vrt_inst2_dstv_reg,
dp_vrt_inst2_dstv_vld,
dp_vrt_inst2_srcv0_reg,
dp_vrt_inst2_srcv0_vld,
dp_vrt_inst2_srcv1_reg,
dp_vrt_inst2_srcv1_vld,
dp_vrt_inst2_srcv2_vld,
dp_vrt_inst2_srcvm_vld,
dp_vrt_inst2_vmla,
dp_vrt_inst3_dst_vreg,
dp_vrt_inst3_dstv_reg,
dp_vrt_inst3_dstv_vld,
dp_vrt_inst3_srcv0_reg,
dp_vrt_inst3_srcv0_vld,
dp_vrt_inst3_srcv1_reg,
dp_vrt_inst3_srcv1_vld,
dp_vrt_inst3_srcv2_vld,
dp_vrt_inst3_srcvm_vld,
dp_vrt_inst3_vmla,
rtu_idu_rt_recover_vreg,
vrt_dp_inst01_srcv2_match,
vrt_dp_inst02_srcv2_match,
vrt_dp_inst03_srcv2_match,
vrt_dp_inst0_rel_vreg,
vrt_dp_inst0_srcv0_data,
vrt_dp_inst0_srcv1_data,
vrt_dp_inst0_srcv2_data,
vrt_dp_inst0_srcvm_data,
vrt_dp_inst12_srcv2_match,
vrt_dp_inst13_srcv2_match,
vrt_dp_inst1_rel_vreg,
vrt_dp_inst1_srcv0_data,
vrt_dp_inst1_srcv1_data,
vrt_dp_inst1_srcv2_data,
vrt_dp_inst1_srcvm_data,
vrt_dp_inst23_srcv2_match,
vrt_dp_inst2_rel_vreg,
vrt_dp_inst2_srcv0_data,
vrt_dp_inst2_srcv1_data,
vrt_dp_inst2_srcv2_data,
vrt_dp_inst2_srcvm_data,
vrt_dp_inst3_rel_vreg,
vrt_dp_inst3_srcv0_data,
vrt_dp_inst3_srcv1_data,
vrt_dp_inst3_srcv2_data,
vrt_dp_inst3_srcvm_data
);
// &Ports; @26
input [5 :0] dp_vrt_inst0_dst_vreg;
input [5 :0] dp_vrt_inst0_dstv_reg;
input dp_vrt_inst0_dstv_vld;
input [5 :0] dp_vrt_inst0_srcv0_reg;
input dp_vrt_inst0_srcv0_vld;
input [5 :0] dp_vrt_inst0_srcv1_reg;
input dp_vrt_inst0_srcv1_vld;
input dp_vrt_inst0_srcv2_vld;
input dp_vrt_inst0_srcvm_vld;
input dp_vrt_inst0_vmla;
input [5 :0] dp_vrt_inst1_dst_vreg;
input [5 :0] dp_vrt_inst1_dstv_reg;
input dp_vrt_inst1_dstv_vld;
input [5 :0] dp_vrt_inst1_srcv0_reg;
input dp_vrt_inst1_srcv0_vld;
input [5 :0] dp_vrt_inst1_srcv1_reg;
input dp_vrt_inst1_srcv1_vld;
input dp_vrt_inst1_srcv2_vld;
input dp_vrt_inst1_srcvm_vld;
input dp_vrt_inst1_vmla;
input [5 :0] dp_vrt_inst2_dst_vreg;
input [5 :0] dp_vrt_inst2_dstv_reg;
input dp_vrt_inst2_dstv_vld;
input [5 :0] dp_vrt_inst2_srcv0_reg;
input dp_vrt_inst2_srcv0_vld;
input [5 :0] dp_vrt_inst2_srcv1_reg;
input dp_vrt_inst2_srcv1_vld;
input dp_vrt_inst2_srcv2_vld;
input dp_vrt_inst2_srcvm_vld;
input dp_vrt_inst2_vmla;
input [5 :0] dp_vrt_inst3_dst_vreg;
input [5 :0] dp_vrt_inst3_dstv_reg;
input dp_vrt_inst3_dstv_vld;
input [5 :0] dp_vrt_inst3_srcv0_reg;
input dp_vrt_inst3_srcv0_vld;
input [5 :0] dp_vrt_inst3_srcv1_reg;
input dp_vrt_inst3_srcv1_vld;
input dp_vrt_inst3_srcv2_vld;
input dp_vrt_inst3_srcvm_vld;
input dp_vrt_inst3_vmla;
input [191:0] rtu_idu_rt_recover_vreg;
output vrt_dp_inst01_srcv2_match;
output vrt_dp_inst02_srcv2_match;
output vrt_dp_inst03_srcv2_match;
output [6 :0] vrt_dp_inst0_rel_vreg;
output [8 :0] vrt_dp_inst0_srcv0_data;
output [8 :0] vrt_dp_inst0_srcv1_data;
output [9 :0] vrt_dp_inst0_srcv2_data;
output [8 :0] vrt_dp_inst0_srcvm_data;
output vrt_dp_inst12_srcv2_match;
output vrt_dp_inst13_srcv2_match;
output [6 :0] vrt_dp_inst1_rel_vreg;
output [8 :0] vrt_dp_inst1_srcv0_data;
output [8 :0] vrt_dp_inst1_srcv1_data;
output [9 :0] vrt_dp_inst1_srcv2_data;
output [8 :0] vrt_dp_inst1_srcvm_data;
output vrt_dp_inst23_srcv2_match;
output [6 :0] vrt_dp_inst2_rel_vreg;
output [8 :0] vrt_dp_inst2_srcv0_data;
output [8 :0] vrt_dp_inst2_srcv1_data;
output [9 :0] vrt_dp_inst2_srcv2_data;
output [8 :0] vrt_dp_inst2_srcvm_data;
output [6 :0] vrt_dp_inst3_rel_vreg;
output [8 :0] vrt_dp_inst3_srcv0_data;
output [8 :0] vrt_dp_inst3_srcv1_data;
output [9 :0] vrt_dp_inst3_srcv2_data;
output [8 :0] vrt_dp_inst3_srcvm_data;
// &Regs; @27
// &Wires; @28
wire vrt_dp_inst01_srcv2_match;
wire vrt_dp_inst02_srcv2_match;
wire vrt_dp_inst03_srcv2_match;
wire [6 :0] vrt_dp_inst0_rel_vreg;
wire [8 :0] vrt_dp_inst0_srcv0_data;
wire [8 :0] vrt_dp_inst0_srcv1_data;
wire [9 :0] vrt_dp_inst0_srcv2_data;
wire [8 :0] vrt_dp_inst0_srcvm_data;
wire vrt_dp_inst12_srcv2_match;
wire vrt_dp_inst13_srcv2_match;
wire [6 :0] vrt_dp_inst1_rel_vreg;
wire [8 :0] vrt_dp_inst1_srcv0_data;
wire [8 :0] vrt_dp_inst1_srcv1_data;
wire [9 :0] vrt_dp_inst1_srcv2_data;
wire [8 :0] vrt_dp_inst1_srcvm_data;
wire vrt_dp_inst23_srcv2_match;
wire [6 :0] vrt_dp_inst2_rel_vreg;
wire [8 :0] vrt_dp_inst2_srcv0_data;
wire [8 :0] vrt_dp_inst2_srcv1_data;
wire [9 :0] vrt_dp_inst2_srcv2_data;
wire [8 :0] vrt_dp_inst2_srcvm_data;
wire [6 :0] vrt_dp_inst3_rel_vreg;
wire [8 :0] vrt_dp_inst3_srcv0_data;
wire [8 :0] vrt_dp_inst3_srcv1_data;
wire [9 :0] vrt_dp_inst3_srcv2_data;
wire [8 :0] vrt_dp_inst3_srcvm_data;
// &Force("bus","dp_rt_dep_info",DEP_WIDTH-1,0); @57
// &Instance("gated_clk_cell", "x_vrt_gated_clk"); @73
// &Connect(.clk_in (forever_cpuclk), @74
// .external_en (1'b0), @75
// .global_en (cp0_yy_clk_en), @76
// .module_en (cp0_idu_icg_en), @77
// .local_en (vrt_clk_en), @78
// .clk_out (vrt_top_clk)); @79
// &ConnRule(s/^x_/reg_0_/); @85
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_0"); @86
// &Connect(.forever_cpuclk(vrt_top_clk)); @87
// &ConnRule(s/^x_/reg_1_/); @88
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_1"); @89
// &Connect(.forever_cpuclk(vrt_top_clk)); @90
// &ConnRule(s/^x_/reg_2_/); @91
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_2"); @92
// &Connect(.forever_cpuclk(vrt_top_clk)); @93
// &ConnRule(s/^x_/reg_3_/); @94
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_3"); @95
// &Connect(.forever_cpuclk(vrt_top_clk)); @96
// &ConnRule(s/^x_/reg_4_/); @97
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_4"); @98
// &Connect(.forever_cpuclk(vrt_top_clk)); @99
// &ConnRule(s/^x_/reg_5_/); @100
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_5"); @101
// &Connect(.forever_cpuclk(vrt_top_clk)); @102
// &ConnRule(s/^x_/reg_6_/); @103
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_6"); @104
// &Connect(.forever_cpuclk(vrt_top_clk)); @105
// &ConnRule(s/^x_/reg_7_/); @106
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_7"); @107
// &Connect(.forever_cpuclk(vrt_top_clk)); @108
// &ConnRule(s/^x_/reg_8_/); @109
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_8"); @110
// &Connect(.forever_cpuclk(vrt_top_clk)); @111
// &ConnRule(s/^x_/reg_9_/); @112
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_9"); @113
// &Connect(.forever_cpuclk(vrt_top_clk)); @114
// &ConnRule(s/^x_/reg_10_/); @115
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_10"); @116
// &Connect(.forever_cpuclk(vrt_top_clk)); @117
// &ConnRule(s/^x_/reg_11_/); @118
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_11"); @119
// &Connect(.forever_cpuclk(vrt_top_clk)); @120
// &ConnRule(s/^x_/reg_12_/); @121
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_12"); @122
// &Connect(.forever_cpuclk(vrt_top_clk)); @123
// &ConnRule(s/^x_/reg_13_/); @124
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_13"); @125
// &Connect(.forever_cpuclk(vrt_top_clk)); @126
// &ConnRule(s/^x_/reg_14_/); @127
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_14"); @128
// &Connect(.forever_cpuclk(vrt_top_clk)); @129
// &ConnRule(s/^x_/reg_15_/); @130
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_15"); @131
// &Connect(.forever_cpuclk(vrt_top_clk)); @132
// &ConnRule(s/^x_/reg_16_/); @133
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_16"); @134
// &Connect(.forever_cpuclk(vrt_top_clk)); @135
// &ConnRule(s/^x_/reg_17_/); @136
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_17"); @137
// &Connect(.forever_cpuclk(vrt_top_clk)); @138
// &ConnRule(s/^x_/reg_18_/); @139
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_18"); @140
// &Connect(.forever_cpuclk(vrt_top_clk)); @141
// &ConnRule(s/^x_/reg_19_/); @142
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_19"); @143
// &Connect(.forever_cpuclk(vrt_top_clk)); @144
// &ConnRule(s/^x_/reg_20_/); @145
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_20"); @146
// &Connect(.forever_cpuclk(vrt_top_clk)); @147
// &ConnRule(s/^x_/reg_21_/); @148
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_21"); @149
// &Connect(.forever_cpuclk(vrt_top_clk)); @150
// &ConnRule(s/^x_/reg_22_/); @151
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_22"); @152
// &Connect(.forever_cpuclk(vrt_top_clk)); @153
// &ConnRule(s/^x_/reg_23_/); @154
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_23"); @155
// &Connect(.forever_cpuclk(vrt_top_clk)); @156
// &ConnRule(s/^x_/reg_24_/); @157
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_24"); @158
// &Connect(.forever_cpuclk(vrt_top_clk)); @159
// &ConnRule(s/^x_/reg_25_/); @160
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_25"); @161
// &Connect(.forever_cpuclk(vrt_top_clk)); @162
// &ConnRule(s/^x_/reg_26_/); @163
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_26"); @164
// &Connect(.forever_cpuclk(vrt_top_clk)); @165
// &ConnRule(s/^x_/reg_27_/); @166
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_27"); @167
// &Connect(.forever_cpuclk(vrt_top_clk)); @168
// &ConnRule(s/^x_/reg_28_/); @169
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_28"); @170
// &Connect(.forever_cpuclk(vrt_top_clk)); @171
// &ConnRule(s/^x_/reg_29_/); @172
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_29"); @173
// &Connect(.forever_cpuclk(vrt_top_clk)); @174
// &ConnRule(s/^x_/reg_30_/); @175
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_30"); @176
// &Connect(.forever_cpuclk(vrt_top_clk)); @177
// &ConnRule(s/^x_/reg_31_/); @178
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_31"); @179
// &Connect(.forever_cpuclk(vrt_top_clk)); @180
// &ConnRule(s/^x_/reg_32_/); @181
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_32"); @182
// &Connect(.forever_cpuclk(vrt_top_clk)); @183
// &ConnRule(s/^x_/reg_33_/); @184
// &Instance("ct_idu_dep_vreg_srcv2_entry","x_ct_idu_ir_vrt_entry_vreg_33"); @185
// &Connect(.forever_cpuclk(vrt_top_clk)); @186
// &ConnRule(s/^x_num/dp_vrt_inst0_dstv_reg_lsb/); @314
// &Instance("ct_rtu_expand_32","x_ct_rtu_expand_32_dp_vrt_inst0_dstv_reg_lsb"); @315
// &ConnRule(s/^x_num/dp_vrt_inst1_dstv_reg_lsb/); @316
// &Instance("ct_rtu_expand_32","x_ct_rtu_expand_32_dp_vrt_inst1_dstv_reg_lsb"); @317
// &ConnRule(s/^x_num/dp_vrt_inst2_dstv_reg_lsb/); @318
// &Instance("ct_rtu_expand_32","x_ct_rtu_expand_32_dp_vrt_inst2_dstv_reg_lsb"); @319
// &ConnRule(s/^x_num/dp_vrt_inst3_dstv_reg_lsb/); @320
// &Instance("ct_rtu_expand_32","x_ct_rtu_expand_32_dp_vrt_inst3_dstv_reg_lsb"); @321
// &CombBeg; @537
// &CombEnd; @548
// &CombBeg; @549
// &CombEnd; @560
// &CombBeg; @561
// &CombEnd; @572
// &CombBeg; @573
// &CombEnd; @584
// &CombBeg; @585
// &CombEnd; @596
// &CombBeg; @597
// &CombEnd; @608
// &CombBeg; @609
// &CombEnd; @620
// &CombBeg; @621
// &CombEnd; @632
// &CombBeg; @633
// &CombEnd; @644
// &CombBeg; @645
// &CombEnd; @656
// &CombBeg; @657
// &CombEnd; @668
// &CombBeg; @669
// &CombEnd; @680
// &CombBeg; @681
// &CombEnd; @692
// &CombBeg; @693
// &CombEnd; @704
// &CombBeg; @705
// &CombEnd; @716
// &CombBeg; @717
// &CombEnd; @728
// &CombBeg; @729
// &CombEnd; @740
// &CombBeg; @741
// &CombEnd; @752
// &CombBeg; @753
// &CombEnd; @764
// &CombBeg; @765
// &CombEnd; @776
// &CombBeg; @777
// &CombEnd; @788
// &CombBeg; @789
// &CombEnd; @800
// &CombBeg; @801
// &CombEnd; @812
// &CombBeg; @813
// &CombEnd; @824
// &CombBeg; @825
// &CombEnd; @836
// &CombBeg; @837
// &CombEnd; @848
// &CombBeg; @849
// &CombEnd; @860
// &CombBeg; @861
// &CombEnd; @872
// &CombBeg; @873
// &CombEnd; @884
// &CombBeg; @885
// &CombEnd; @896
// &CombBeg; @897
// &CombEnd; @908
// &CombBeg; @909
// &CombEnd; @920
// &CombBeg; @921
// &CombEnd; @932
// &CombBeg; @933
// &CombEnd; @944
// &CombBeg; @988
// &CombEnd; @1026
// &CombBeg; @1039
// &CombEnd; @1077
// &CombBeg; @1090
// &CombEnd; @1128
// &CombBeg; @1167
// &CombEnd; @1205
// &CombBeg; @1222
// &CombEnd; @1235
// &CombBeg; @1238
// &CombEnd; @1276
// &CombBeg; @1295
// &CombEnd; @1308
// &CombBeg; @1311
// &CombEnd; @1349
// &CombBeg; @1368
// &CombEnd; @1389
// &CombBeg; @1408
// &CombEnd; @1421
// &CombBeg; @1439
// &CombEnd; @1446
// &CombBeg; @1452
// &CombEnd; @1490
// &CombBeg; @1512
// &CombEnd; @1530
// &CombBeg; @1533
// &CombEnd; @1571
// &CombBeg; @1592
// &CombEnd; @1610
// &CombBeg; @1613
// &CombEnd; @1651
// &CombBeg; @1672
// &CombEnd; @1704
// &CombBeg; @1725
// &CombEnd; @1743
// &CombBeg; @1760
// &CombEnd; @1769
// &CombBeg; @1775
// &CombEnd; @1813
// &CombBeg; @1842
// &CombEnd; @1865
// &CombBeg; @1868
// &CombEnd; @1906
// &CombBeg; @1932
// &CombEnd; @1955
// &CombBeg; @1958
// &CombEnd; @1996
// &CombBeg; @2022
// &CombEnd; @2067
// &CombBeg; @2093
// &CombEnd; @2116
// &CombBeg; @2137
// &CombEnd; @2148
// &Force("input","dp_vrt_inst0_dst_vreg"); @2151
// &Force("input","dp_vrt_inst0_dstv_reg"); @2152
// &Force("input","dp_vrt_inst0_dstv_vld"); @2153
// &Force("input","dp_vrt_inst0_srcv0_reg"); @2154
// &Force("input","dp_vrt_inst0_srcv0_vld"); @2155
// &Force("input","dp_vrt_inst0_srcv1_reg"); @2156
// &Force("input","dp_vrt_inst0_srcv1_vld"); @2157
// &Force("input","dp_vrt_inst0_srcv2_vld"); @2158
// &Force("input","dp_vrt_inst0_srcvm_vld"); @2159
// &Force("input","dp_vrt_inst0_vmla"); @2160
// &Force("input","dp_vrt_inst1_dst_vreg"); @2161
// &Force("input","dp_vrt_inst1_dstv_reg"); @2162
// &Force("input","dp_vrt_inst1_dstv_vld"); @2163
// &Force("input","dp_vrt_inst1_srcv0_reg"); @2164
// &Force("input","dp_vrt_inst1_srcv0_vld"); @2165
// &Force("input","dp_vrt_inst1_srcv1_reg"); @2166
// &Force("input","dp_vrt_inst1_srcv1_vld"); @2167
// &Force("input","dp_vrt_inst1_srcv2_vld"); @2168
// &Force("input","dp_vrt_inst1_srcvm_vld"); @2169
// &Force("input","dp_vrt_inst1_vmla"); @2170
// &Force("input","dp_vrt_inst2_dst_vreg"); @2171
// &Force("input","dp_vrt_inst2_dstv_reg"); @2172
// &Force("input","dp_vrt_inst2_dstv_vld"); @2173
// &Force("input","dp_vrt_inst2_srcv0_reg"); @2174
// &Force("input","dp_vrt_inst2_srcv0_vld"); @2175
// &Force("input","dp_vrt_inst2_srcv1_reg"); @2176
// &Force("input","dp_vrt_inst2_srcv1_vld"); @2177
// &Force("input","dp_vrt_inst2_srcv2_vld"); @2178
// &Force("input","dp_vrt_inst2_srcvm_vld"); @2179
// &Force("input","dp_vrt_inst2_vmla"); @2180
// &Force("input","dp_vrt_inst3_dst_vreg"); @2181
// &Force("input","dp_vrt_inst3_dstv_reg"); @2182
// &Force("input","dp_vrt_inst3_dstv_vld"); @2183
// &Force("input","dp_vrt_inst3_srcv0_reg"); @2184
// &Force("input","dp_vrt_inst3_srcv0_vld"); @2185
// &Force("input","dp_vrt_inst3_srcv1_reg"); @2186
// &Force("input","dp_vrt_inst3_srcv1_vld"); @2187
// &Force("input","dp_vrt_inst3_srcv2_vld"); @2188
// &Force("input","dp_vrt_inst3_srcvm_vld"); @2189
// &Force("input","dp_vrt_inst3_vmla"); @2190
// &Force("input","rtu_idu_rt_recover_vreg"); @2191
// &Force("bus","dp_vrt_inst0_dst_vreg",5,0); @2193
// &Force("bus","dp_vrt_inst0_dstv_reg",5,0); @2194
// &Force("bus","dp_vrt_inst0_srcv0_reg",5,0); @2195
// &Force("bus","dp_vrt_inst0_srcv1_reg",5,0); @2196
// &Force("bus","dp_vrt_inst1_dst_vreg",5,0); @2197
// &Force("bus","dp_vrt_inst1_dstv_reg",5,0); @2198
// &Force("bus","dp_vrt_inst1_srcv0_reg",5,0); @2199
// &Force("bus","dp_vrt_inst1_srcv1_reg",5,0); @2200
// &Force("bus","dp_vrt_inst2_dst_vreg",5,0); @2201
// &Force("bus","dp_vrt_inst2_dstv_reg",5,0); @2202
// &Force("bus","dp_vrt_inst2_srcv0_reg",5,0); @2203
// &Force("bus","dp_vrt_inst2_srcv1_reg",5,0); @2204
// &Force("bus","dp_vrt_inst3_dst_vreg",5,0); @2205
// &Force("bus","dp_vrt_inst3_dstv_reg",5,0); @2206
// &Force("bus","dp_vrt_inst3_srcv0_reg",5,0); @2207
// &Force("bus","dp_vrt_inst3_srcv1_reg",5,0); @2208
// &Force("bus","rtu_idu_rt_recover_vreg",191,0); @2209
assign vrt_dp_inst01_srcv2_match = 1'b0;
assign vrt_dp_inst02_srcv2_match = 1'b0;
assign vrt_dp_inst03_srcv2_match = 1'b0;
assign vrt_dp_inst0_rel_vreg[6:0] = 7'b0;
assign vrt_dp_inst0_srcv0_data[8:0] = 9'b100000011;
assign vrt_dp_inst0_srcv1_data[8:0] = 9'b100000011;
assign vrt_dp_inst0_srcv2_data[9:0] = 10'b1000000111;
assign vrt_dp_inst0_srcvm_data[8:0] = 9'b100000011;
assign vrt_dp_inst12_srcv2_match = 1'b0;
assign vrt_dp_inst13_srcv2_match = 1'b0;
assign vrt_dp_inst1_rel_vreg[6:0] = 7'b0;
assign vrt_dp_inst1_srcv0_data[8:0] = 9'b100000011;
assign vrt_dp_inst1_srcv1_data[8:0] = 9'b100000011;
assign vrt_dp_inst1_srcv2_data[9:0] = 10'b1000000111;
assign vrt_dp_inst1_srcvm_data[8:0] = 9'b100000011;
assign vrt_dp_inst23_srcv2_match = 1'b0;
assign vrt_dp_inst2_rel_vreg[6:0] = 7'b0;
assign vrt_dp_inst2_srcv0_data[8:0] = 9'b100000011;
assign vrt_dp_inst2_srcv1_data[8:0] = 9'b100000011;
assign vrt_dp_inst2_srcv2_data[9:0] = 10'b1000000111;
assign vrt_dp_inst2_srcvm_data[8:0] = 9'b100000011;
assign vrt_dp_inst3_rel_vreg[6:0] = 7'b0;
assign vrt_dp_inst3_srcv0_data[8:0] = 9'b100000011;
assign vrt_dp_inst3_srcv1_data[8:0] = 9'b100000011;
assign vrt_dp_inst3_srcv2_data[9:0] = 10'b1000000111;
assign vrt_dp_inst3_srcvm_data[8:0] = 9'b100000011;
// &ModuleEnd; @2240
endmodule |
module ct_idu_is_aiq_lch_rdy_1(
cpurst_b,
vld,
x_create_dp_en,
x_create_entry,
x_create_lch_rdy,
x_read_lch_rdy,
y_clk,
y_create0_dp_en,
y_create0_src_match,
y_create1_dp_en,
y_create1_src_match
);
// &Ports; @25
input cpurst_b;
input vld;
input x_create_dp_en;
input [1:0] x_create_entry;
input x_create_lch_rdy;
input y_clk;
input y_create0_dp_en;
input y_create0_src_match;
input y_create1_dp_en;
input y_create1_src_match;
output x_read_lch_rdy;
// &Regs; @26
reg lch_rdy;
reg x_read_lch_rdy;
// &Wires; @27
wire cpurst_b;
wire lch_rdy_create0_en;
wire lch_rdy_create1_en;
wire vld;
wire x_create_dp_en;
wire [1:0] x_create_entry;
wire x_create_lch_rdy;
wire y_clk;
wire y_create0_dp_en;
wire y_create0_src_match;
wire y_create1_dp_en;
wire y_create1_src_match;
//==========================================================
// Preg Register
//==========================================================
assign lch_rdy_create0_en = y_create0_dp_en && x_create_entry[0];
assign lch_rdy_create1_en = y_create1_dp_en && x_create_entry[1];
always @(posedge y_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lch_rdy <= 1'b0;
else if(x_create_dp_en)
lch_rdy <= x_create_lch_rdy;
else if(vld && lch_rdy_create0_en)
lch_rdy <= y_create0_src_match;
else if(vld && lch_rdy_create1_en)
lch_rdy <= y_create1_src_match;
else
lch_rdy <= lch_rdy;
end
//==========================================================
// Read Port
//==========================================================
// &CombBeg; @53
always @( y_create1_src_match
or lch_rdy_create1_en
or y_create0_src_match
or lch_rdy
or lch_rdy_create0_en)
begin
case({lch_rdy_create1_en,lch_rdy_create0_en})
2'b01 : x_read_lch_rdy = y_create0_src_match;
2'b10 : x_read_lch_rdy = y_create1_src_match;
default: x_read_lch_rdy = lch_rdy;
endcase
// &CombEnd; @59
end
// &ModuleEnd; @61
endmodule |
module ct_idu_rf_prf_gated_vreg(
cp0_idu_icg_en,
cp0_yy_clk_en,
lsu_idu_wb_pipe3_wb_vreg_data,
pad_yy_icg_scan_en,
vfpu_idu_ex5_pipe6_wb_vreg_data,
vfpu_idu_ex5_pipe7_wb_vreg_data,
vreg_top_clk,
x_reg_dout,
x_wb_vld
);
// &Ports; @28
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input [63:0] lsu_idu_wb_pipe3_wb_vreg_data;
input pad_yy_icg_scan_en;
input [63:0] vfpu_idu_ex5_pipe6_wb_vreg_data;
input [63:0] vfpu_idu_ex5_pipe7_wb_vreg_data;
input vreg_top_clk;
input [2 :0] x_wb_vld;
output [63:0] x_reg_dout;
// &Regs; @29
reg [63:0] reg_dout;
reg [63:0] write_data;
// &Wires; @30
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire [63:0] lsu_idu_wb_pipe3_wb_vreg_data;
wire pad_yy_icg_scan_en;
wire [63:0] vfpu_idu_ex5_pipe6_wb_vreg_data;
wire [63:0] vfpu_idu_ex5_pipe7_wb_vreg_data;
wire vreg_clk;
wire vreg_clk_en;
wire vreg_top_clk;
wire write_en;
wire [63:0] x_reg_dout;
wire [2 :0] x_wb_vld;
//parameter VEC_MSB = `VEC_WIDTH;
parameter VEC_MSB = 63;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign vreg_clk_en = write_en;
// &Instance("gated_clk_cell", "x_vreg_gated_clk"); @40
gated_clk_cell x_vreg_gated_clk (
.clk_in (vreg_top_clk ),
.clk_out (vreg_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (vreg_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (vreg_top_clk), @41
// .external_en (1'b0), @42
// .global_en (cp0_yy_clk_en), @43
// .module_en (cp0_idu_icg_en), @44
// .local_en (vreg_clk_en), @45
// .clk_out (vreg_clk)); @46
//==========================================================
// Write Port
//==========================================================
assign write_en = |x_wb_vld[2:0];
// &CombBeg; @52
always @( lsu_idu_wb_pipe3_wb_vreg_data[63:0]
or vfpu_idu_ex5_pipe7_wb_vreg_data[63:0]
or x_wb_vld[2:0]
or vfpu_idu_ex5_pipe6_wb_vreg_data[63:0])
begin
case (x_wb_vld[2:0])
3'b001 : write_data[VEC_MSB:0] = vfpu_idu_ex5_pipe6_wb_vreg_data[VEC_MSB:0];
3'b010 : write_data[VEC_MSB:0] = vfpu_idu_ex5_pipe7_wb_vreg_data[VEC_MSB:0];
3'b100 : write_data[VEC_MSB:0] = lsu_idu_wb_pipe3_wb_vreg_data[VEC_MSB:0];
default: write_data[VEC_MSB:0] = {VEC_MSB+1{1'bx}};
endcase
// &CombEnd; @59
end
//==========================================================
// Vreg Register
//==========================================================
always @(posedge vreg_clk)
begin
if(write_en)
reg_dout[VEC_MSB:0] <= write_data[VEC_MSB:0];
else
reg_dout[VEC_MSB:0] <= reg_dout[VEC_MSB:0];
end
assign x_reg_dout[VEC_MSB:0] = reg_dout[VEC_MSB:0];
// &ModuleEnd; @74
endmodule |
module ct_idu_dep_vreg_entry(
cp0_idu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
gateclk_entry_vld,
lsu_idu_ag_pipe3_vload_inst_vld,
lsu_idu_ag_pipe3_vreg_dupx,
lsu_idu_dc_pipe3_vload_fwd_inst_vld,
lsu_idu_dc_pipe3_vload_inst_vld_dupx,
lsu_idu_dc_pipe3_vreg_dupx,
lsu_idu_wb_pipe3_wb_vreg_dupx,
lsu_idu_wb_pipe3_wb_vreg_vld_dupx,
pad_yy_icg_scan_en,
rtu_idu_flush_fe,
rtu_idu_flush_is,
vfpu_idu_ex1_pipe6_data_vld_dupx,
vfpu_idu_ex1_pipe6_vreg_dupx,
vfpu_idu_ex1_pipe7_data_vld_dupx,
vfpu_idu_ex1_pipe7_vreg_dupx,
vfpu_idu_ex2_pipe6_data_vld_dupx,
vfpu_idu_ex2_pipe6_vreg_dupx,
vfpu_idu_ex2_pipe7_data_vld_dupx,
vfpu_idu_ex2_pipe7_vreg_dupx,
vfpu_idu_ex3_pipe6_data_vld_dupx,
vfpu_idu_ex3_pipe6_vreg_dupx,
vfpu_idu_ex3_pipe7_data_vld_dupx,
vfpu_idu_ex3_pipe7_vreg_dupx,
vfpu_idu_ex5_pipe6_wb_vreg_dupx,
vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx,
vfpu_idu_ex5_pipe7_wb_vreg_dupx,
vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx,
x_create_data,
x_gateclk_idx_write_en,
x_gateclk_write_en,
x_rdy_clr,
x_read_data,
x_write_en
);
// &Ports; @27
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input gateclk_entry_vld;
input lsu_idu_ag_pipe3_vload_inst_vld;
input [6 :0] lsu_idu_ag_pipe3_vreg_dupx;
input lsu_idu_dc_pipe3_vload_fwd_inst_vld;
input lsu_idu_dc_pipe3_vload_inst_vld_dupx;
input [6 :0] lsu_idu_dc_pipe3_vreg_dupx;
input [6 :0] lsu_idu_wb_pipe3_wb_vreg_dupx;
input lsu_idu_wb_pipe3_wb_vreg_vld_dupx;
input pad_yy_icg_scan_en;
input rtu_idu_flush_fe;
input rtu_idu_flush_is;
input vfpu_idu_ex1_pipe6_data_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe6_vreg_dupx;
input vfpu_idu_ex1_pipe7_data_vld_dupx;
input [6 :0] vfpu_idu_ex1_pipe7_vreg_dupx;
input vfpu_idu_ex2_pipe6_data_vld_dupx;
input [6 :0] vfpu_idu_ex2_pipe6_vreg_dupx;
input vfpu_idu_ex2_pipe7_data_vld_dupx;
input [6 :0] vfpu_idu_ex2_pipe7_vreg_dupx;
input vfpu_idu_ex3_pipe6_data_vld_dupx;
input [6 :0] vfpu_idu_ex3_pipe6_vreg_dupx;
input vfpu_idu_ex3_pipe7_data_vld_dupx;
input [6 :0] vfpu_idu_ex3_pipe7_vreg_dupx;
input [6 :0] vfpu_idu_ex5_pipe6_wb_vreg_dupx;
input vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx;
input [6 :0] vfpu_idu_ex5_pipe7_wb_vreg_dupx;
input vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx;
input [9 :0] x_create_data;
input x_gateclk_idx_write_en;
input x_gateclk_write_en;
input x_rdy_clr;
input x_write_en;
output [11:0] x_read_data;
// &Regs; @28
reg lsu_match;
reg rdy;
reg [6 :0] vreg;
reg wb;
// &Wires; @29
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire data_ready;
wire dep_clk;
wire dep_clk_en;
wire forever_cpuclk;
wire gateclk_entry_vld;
wire load_data_ready;
wire load_issue_data_ready;
wire lsu_idu_ag_pipe3_vload_inst_vld;
wire [6 :0] lsu_idu_ag_pipe3_vreg_dupx;
wire lsu_idu_dc_pipe3_vload_fwd_inst_vld;
wire lsu_idu_dc_pipe3_vload_inst_vld_dupx;
wire [6 :0] lsu_idu_dc_pipe3_vreg_dupx;
wire [6 :0] lsu_idu_wb_pipe3_wb_vreg_dupx;
wire lsu_idu_wb_pipe3_wb_vreg_vld_dupx;
wire lsu_match_update;
wire pad_yy_icg_scan_en;
wire pipe3_wb;
wire pipe6_wb;
wire pipe7_wb;
wire rdy_clear;
wire rdy_update;
wire rtu_idu_flush_fe;
wire rtu_idu_flush_is;
wire vfpu0_ex3_data_ready;
wire vfpu0_ex4_data_ready;
wire vfpu0_ex5_data_ready;
wire vfpu1_ex3_data_ready;
wire vfpu1_ex4_data_ready;
wire vfpu1_ex5_data_ready;
wire vfpu_idu_ex1_pipe6_data_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe6_vreg_dupx;
wire vfpu_idu_ex1_pipe7_data_vld_dupx;
wire [6 :0] vfpu_idu_ex1_pipe7_vreg_dupx;
wire vfpu_idu_ex2_pipe6_data_vld_dupx;
wire [6 :0] vfpu_idu_ex2_pipe6_vreg_dupx;
wire vfpu_idu_ex2_pipe7_data_vld_dupx;
wire [6 :0] vfpu_idu_ex2_pipe7_vreg_dupx;
wire vfpu_idu_ex3_pipe6_data_vld_dupx;
wire [6 :0] vfpu_idu_ex3_pipe6_vreg_dupx;
wire vfpu_idu_ex3_pipe7_data_vld_dupx;
wire [6 :0] vfpu_idu_ex3_pipe7_vreg_dupx;
wire [6 :0] vfpu_idu_ex5_pipe6_wb_vreg_dupx;
wire vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx;
wire [6 :0] vfpu_idu_ex5_pipe7_wb_vreg_dupx;
wire vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx;
wire wake_up;
wire wb_update;
wire write_back;
wire write_clk;
wire write_clk_en;
wire [9 :0] x_create_data;
wire x_create_lsu_match;
wire x_create_rdy;
wire [6 :0] x_create_vreg;
wire x_create_wb;
wire x_gateclk_idx_write_en;
wire x_gateclk_write_en;
wire x_rdy_clr;
wire [11:0] x_read_data;
wire x_read_lsu_match;
wire x_read_rdy;
wire x_read_rdy_for_bypass;
wire x_read_rdy_for_issue;
wire [6 :0] x_read_vreg;
wire x_read_wb;
wire x_write_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign dep_clk_en = x_gateclk_write_en || gateclk_entry_vld && (!rdy || !wb);
// &Instance("gated_clk_cell", "x_dep_gated_clk"); @36
gated_clk_cell x_dep_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (dep_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (dep_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @37
// .external_en (1'b0), @38
// .global_en (cp0_yy_clk_en), @39
// .module_en (cp0_idu_icg_en), @40
// .local_en (dep_clk_en), @41
// .clk_out (dep_clk)); @42
assign write_clk_en = x_gateclk_idx_write_en;
// &Instance("gated_clk_cell", "x_write_gated_clk"); @45
gated_clk_cell x_write_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (write_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (write_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @46
// .external_en (1'b0), @47
// .global_en (cp0_yy_clk_en), @48
// .module_en (cp0_idu_icg_en), @49
// .local_en (write_clk_en), @50
// .clk_out (write_clk)); @51
//==========================================================
// Create and Read Bus
//==========================================================
assign x_create_lsu_match = x_create_data[9];
assign x_create_vreg[6:0] = x_create_data[8:2];
assign x_create_wb = x_create_data[1];
assign x_create_rdy = x_create_data[0];
assign x_read_data[11] = x_read_lsu_match;
assign x_read_data[10] = x_read_rdy_for_bypass;
assign x_read_data[9] = x_read_rdy_for_issue;
assign x_read_data[8:2] = x_read_vreg[6:0];
assign x_read_data[1] = x_read_wb;
assign x_read_data[0] = x_read_rdy;
//==========================================================
// Ready Bit
//==========================================================
//ready bit shows the result of source is predicted to be ready:
//1 stands for the result may be forwarded
//-------------Update value of Ready Bit--------------------
//prepare data_ready signal
assign vfpu0_ex3_data_ready = vfpu_idu_ex1_pipe6_data_vld_dupx
&& (vfpu_idu_ex1_pipe6_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu0_ex4_data_ready = vfpu_idu_ex2_pipe6_data_vld_dupx
&& (vfpu_idu_ex2_pipe6_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu0_ex5_data_ready = vfpu_idu_ex3_pipe6_data_vld_dupx
&& (vfpu_idu_ex3_pipe6_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu1_ex3_data_ready = vfpu_idu_ex1_pipe7_data_vld_dupx
&& (vfpu_idu_ex1_pipe7_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu1_ex4_data_ready = vfpu_idu_ex2_pipe7_data_vld_dupx
&& (vfpu_idu_ex2_pipe7_vreg_dupx[6:0] == vreg[6:0]);
assign vfpu1_ex5_data_ready = vfpu_idu_ex3_pipe7_data_vld_dupx
&& (vfpu_idu_ex3_pipe7_vreg_dupx[6:0] == vreg[6:0]);
assign load_data_ready = lsu_idu_dc_pipe3_vload_inst_vld_dupx
&& (lsu_idu_dc_pipe3_vreg_dupx[6:0] == vreg[6:0]);
//load bypass data ready for issue
assign load_issue_data_ready = lsu_idu_dc_pipe3_vload_fwd_inst_vld && lsu_match;
assign data_ready = vfpu0_ex3_data_ready
|| vfpu0_ex4_data_ready
|| vfpu0_ex5_data_ready
|| vfpu1_ex3_data_ready
|| vfpu1_ex4_data_ready
|| vfpu1_ex5_data_ready
|| load_data_ready;
//prepare wake up signal
assign wake_up = wb;
//prepare clear signal
assign rdy_clear = x_rdy_clr;
//1.if ready is already be 1, just hold 1
//2.if producer are presumed to produce the result two cycles later,
// set ready to 1
//3.if producer wake up, set ready to 1
//4.clear ready to 0
assign rdy_update = (rdy || data_ready || wake_up) && !rdy_clear;
//ready read signal
assign x_read_rdy = rdy_update;
//the following signals are for Issue Queue bypass/issue logic
assign x_read_rdy_for_issue = rdy || load_issue_data_ready;
assign x_read_rdy_for_bypass = rdy;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rdy <= 1'b1;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
rdy <= 1'b1;
else if(x_write_en)
rdy <= x_create_rdy;
else
rdy <= rdy_update;
end
//==========================================================
// LSU reg Match for Bypass Ready
//==========================================================
assign lsu_match_update = lsu_idu_ag_pipe3_vload_inst_vld
&& (lsu_idu_ag_pipe3_vreg_dupx[6:0] == vreg[6:0]);
assign x_read_lsu_match = lsu_match_update;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lsu_match <= 1'b0;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
lsu_match <= 1'b0;
else if(x_write_en)
lsu_match <= x_create_lsu_match;
else
lsu_match <= lsu_match_update;
end
//==========================================================
// Write Back Valid
//==========================================================
//write back valid shows whether the result is written back
//into PRF : 1 stands for the result is in PRF
//-------------Update value of Write Back Bit---------------
//prepare write back signal
assign pipe3_wb = lsu_idu_wb_pipe3_wb_vreg_vld_dupx
&& (lsu_idu_wb_pipe3_wb_vreg_dupx[6:0] == vreg[6:0]);
assign pipe6_wb = vfpu_idu_ex5_pipe6_wb_vreg_vld_dupx
&& (vfpu_idu_ex5_pipe6_wb_vreg_dupx[6:0] == vreg[6:0]);
assign pipe7_wb = vfpu_idu_ex5_pipe7_wb_vreg_vld_dupx
&& (vfpu_idu_ex5_pipe7_wb_vreg_dupx[6:0] == vreg[6:0]);
assign write_back = wb
|| pipe3_wb
|| pipe6_wb
|| pipe7_wb;
//1.if wb_vld is already be 1, just hold 1
//2.if this result is writing back to PRF, set wb to 1
assign x_read_wb = wb_update;
assign wb_update = wb || write_back;
always @(posedge dep_clk or negedge cpurst_b)
begin
if(!cpurst_b)
wb <= 1'b1;
else if(rtu_idu_flush_fe || rtu_idu_flush_is)
wb <= 1'b1;
else if(x_write_en)
wb <= x_create_wb;
else
wb <= wb_update;
end
//==========================================================
// Vreg
//==========================================================
assign x_read_vreg[6:0] = vreg[6:0];
always @(posedge write_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vreg[6:0] <= 7'b0;
else if(x_write_en)
vreg[6:0] <= x_create_vreg[6:0];
else
vreg[6:0] <= vreg[6:0];
end
// &ModuleEnd; @198
endmodule |
module ct_idu_id_fence(
cp0_idu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_fence_id_inst_vld,
ctrl_fence_id_stall,
ctrl_fence_ir_pipe_empty,
ctrl_fence_is_pipe_empty,
dp_fence_id_bkpta_inst,
dp_fence_id_bkptb_inst,
dp_fence_id_fence_type,
dp_fence_id_inst,
dp_fence_id_pc,
dp_fence_id_vl,
dp_fence_id_vl_pred,
dp_fence_id_vlmul,
dp_fence_id_vsew,
fence_ctrl_id_stall,
fence_ctrl_inst0_vld,
fence_ctrl_inst1_vld,
fence_ctrl_inst2_vld,
fence_dp_inst0_data,
fence_dp_inst1_data,
fence_dp_inst2_data,
fence_top_cur_state,
forever_cpuclk,
idu_had_pipeline_empty,
idu_hpcp_fence_sync_vld,
idu_rtu_fence_idle,
iu_idu_div_busy,
iu_yy_xx_cancel,
pad_yy_icg_scan_en,
rtu_idu_flush_fe,
rtu_idu_pst_empty,
rtu_idu_rob_empty
);
// &Ports; @28
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_fence_id_inst_vld;
input ctrl_fence_id_stall;
input ctrl_fence_ir_pipe_empty;
input ctrl_fence_is_pipe_empty;
input dp_fence_id_bkpta_inst;
input dp_fence_id_bkptb_inst;
input [2 :0] dp_fence_id_fence_type;
input [31 :0] dp_fence_id_inst;
input [14 :0] dp_fence_id_pc;
input [7 :0] dp_fence_id_vl;
input dp_fence_id_vl_pred;
input [1 :0] dp_fence_id_vlmul;
input [2 :0] dp_fence_id_vsew;
input forever_cpuclk;
input iu_idu_div_busy;
input iu_yy_xx_cancel;
input pad_yy_icg_scan_en;
input rtu_idu_flush_fe;
input rtu_idu_pst_empty;
input rtu_idu_rob_empty;
output fence_ctrl_id_stall;
output fence_ctrl_inst0_vld;
output fence_ctrl_inst1_vld;
output fence_ctrl_inst2_vld;
output [177:0] fence_dp_inst0_data;
output [177:0] fence_dp_inst1_data;
output [177:0] fence_dp_inst2_data;
output [2 :0] fence_top_cur_state;
output idu_had_pipeline_empty;
output idu_hpcp_fence_sync_vld;
output idu_rtu_fence_idle;
// &Regs; @29
reg [2 :0] fence_cur_state;
reg [177:0] fence_dp_inst0_data;
reg [177:0] fence_dp_inst1_data;
reg [177:0] fence_dp_inst2_data;
reg [177:0] fence_inst0_cp0_data;
reg [177:0] fence_inst0_data;
reg [177:0] fence_inst0_fence_data;
reg [177:0] fence_inst0_sync_data;
reg [177:0] fence_inst1_fence_data;
reg [177:0] fence_inst2_sync_data;
reg [2 :0] fence_next_state;
// &Wires; @30
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_fence_id_inst_vld;
wire ctrl_fence_id_stall;
wire ctrl_fence_ir_pipe_empty;
wire ctrl_fence_is_pipe_empty;
wire dp_fence_id_bkpta_inst;
wire dp_fence_id_bkptb_inst;
wire [2 :0] dp_fence_id_fence_type;
wire [31 :0] dp_fence_id_inst;
wire [14 :0] dp_fence_id_pc;
wire [7 :0] dp_fence_id_vl;
wire dp_fence_id_vl_pred;
wire [1 :0] dp_fence_id_vlmul;
wire [2 :0] dp_fence_id_vsew;
wire fence_clk;
wire fence_clk_en;
wire fence_ctrl_id_stall;
wire fence_ctrl_inst0_vld;
wire fence_ctrl_inst1_vld;
wire fence_ctrl_inst2_vld;
wire [31 :0] fence_inst0_bar_opcode;
wire fence_inst0_cp0_csri;
wire fence_inst0_cp0_csrr;
wire fence_inst0_fence_fencei;
wire fence_inst0_fence_sfence_asid;
wire fence_inst0_fence_sfence_va;
wire [177:0] fence_inst1_data;
wire [177:0] fence_inst2_data;
wire [31 :0] fence_inst2_sync_opcode;
wire fence_pipedown;
wire fence_pipeline_empty;
wire fence_sm_start;
wire [2 :0] fence_top_cur_state;
wire forever_cpuclk;
wire idu_had_pipeline_empty;
wire idu_hpcp_fence_sync_vld;
wire idu_rtu_fence_idle;
wire iu_idu_div_busy;
wire iu_yy_xx_cancel;
wire pad_yy_icg_scan_en;
wire rtu_idu_flush_fe;
wire rtu_idu_pst_empty;
wire rtu_idu_rob_empty;
//==========================================================
// Parameters
//==========================================================
//----------------------------------------------------------
// IR data path parameters
//----------------------------------------------------------
parameter IR_WIDTH = 178;
parameter IR_VL_PRED = 177;
parameter IR_VL = 176;
parameter IR_VMB = 168;
parameter IR_PC = 167;
parameter IR_VSEW = 152;
parameter IR_VLMUL = 149;
parameter IR_FMLA = 147;
parameter IR_SPLIT_NUM = 146;
parameter IR_NO_SPEC = 139;
parameter IR_MLA = 138;
parameter IR_DST_X0 = 137;
parameter IR_ILLEGAL = 136;
parameter IR_SPLIT_LAST = 135;
parameter IR_VMLA = 134;
parameter IR_IID_PLUS = 133;
parameter IR_BKPTB_INST = 129;
parameter IR_BKPTA_INST = 128;
parameter IR_FMOV = 127;
parameter IR_MOV = 126;
parameter IR_EXPT = 125;
parameter IR_LENGTH = 118;
parameter IR_INTMASK = 117;
parameter IR_SPLIT = 116;
parameter IR_INST_TYPE = 115;
parameter IR_DSTV_REG = 105;
parameter IR_DSTV_VLD = 99;
parameter IR_SRCVM_VLD = 98;
parameter IR_SRCV2_VLD = 97;
parameter IR_SRCV1_REG = 96;
parameter IR_SRCV1_VLD = 90;
parameter IR_SRCV0_REG = 89;
parameter IR_SRCV0_VLD = 83;
parameter IR_DSTE_VLD = 82;
parameter IR_DSTF_REG = 81;
parameter IR_DSTF_VLD = 75;
parameter IR_SRCF2_REG = 74;
parameter IR_SRCF2_VLD = 68;
parameter IR_SRCF1_REG = 67;
parameter IR_SRCF1_VLD = 61;
parameter IR_SRCF0_REG = 60;
parameter IR_SRCF0_VLD = 54;
parameter IR_DST_REG = 53;
parameter IR_DST_VLD = 47;
parameter IR_SRC2_VLD = 46;
parameter IR_SRC1_REG = 45;
parameter IR_SRC1_VLD = 39;
parameter IR_SRC0_REG = 38;
parameter IR_SRC0_VLD = 32;
parameter IR_OPCODE = 31;
//----------------------------------------------------------
// Type parameters
//----------------------------------------------------------
parameter ALU = 10'b0000000001;
parameter BJU = 10'b0000000010;
parameter MULT = 10'b0000000100;
parameter DIV = 10'b0000001000;
parameter LSU_P5 = 10'b0000110000;
parameter LSU = 10'b0000010000;
parameter PIPE67 = 10'b0001000000;
parameter PIPE6 = 10'b0010000000;
parameter PIPE7 = 10'b0100000000;
parameter SPECIAL = 10'b1000000000;
//==========================================================
// Fence instructions
//==========================================================
parameter IDLE = 3'b000;
parameter WAIT_ISSUE = 3'b001;
parameter ISSUE = 3'b010;
parameter WAIT_CMPLT = 3'b011;
parameter POP_INST = 3'b100;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign fence_clk_en = fence_sm_start
|| (fence_cur_state[2:0] != IDLE);
// &Instance("gated_clk_cell", "x_fence_gated_clk"); @119
gated_clk_cell x_fence_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (fence_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fence_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @120
// .external_en (1'b0), @121
// .global_en (cp0_yy_clk_en), @122
// .module_en (cp0_idu_icg_en), @123
// .local_en (fence_clk_en), @124
// .clk_out (fence_clk)); @125
//----------------------------------------------------------
// control signal for fence FSM
//----------------------------------------------------------
assign fence_sm_start = ctrl_fence_id_inst_vld
&& !ctrl_fence_id_stall;
assign fence_pipeline_empty = ctrl_fence_ir_pipe_empty
&& ctrl_fence_is_pipe_empty
&& rtu_idu_rob_empty
&& !iu_idu_div_busy
&& rtu_idu_pst_empty;
assign fence_pipedown = fence_pipeline_empty;
assign idu_had_pipeline_empty = fence_pipeline_empty;
//----------------------------------------------------------
// FSM of inst fence ctrl logic
//----------------------------------------------------------
// State Description:
// IDLE : id stage instruction 0 is not fence instruction
// or the first cycle to start fence FSM
// WAIT_ISSUE : wait backend pipeline empty
// ISSUE : start to pipedown
// WAIT_CMPLT : wait this fence instruction complete
// POP_INST : pop fence inst from id stage pipeline register
always @(posedge fence_clk or negedge cpurst_b)
begin
if(!cpurst_b)
fence_cur_state[2:0] <= IDLE;
else if(rtu_idu_flush_fe)
fence_cur_state[2:0] <= IDLE;
else if(iu_yy_xx_cancel)
fence_cur_state[2:0] <= IDLE;
else
fence_cur_state[2:0] <= fence_next_state[2:0];
end
// &CombBeg; @163
always @( fence_pipeline_empty
or fence_pipedown
or fence_cur_state[2:0]
or fence_sm_start)
begin
case(fence_cur_state[2:0])
IDLE : if(fence_sm_start)
fence_next_state[2:0] = WAIT_ISSUE;
else
fence_next_state[2:0] = IDLE;
WAIT_ISSUE : if(fence_pipedown)
fence_next_state[2:0] = ISSUE;
else
fence_next_state[2:0] = WAIT_ISSUE;
ISSUE : fence_next_state[2:0] = WAIT_CMPLT;
WAIT_CMPLT : if(fence_pipeline_empty)
fence_next_state[2:0] = POP_INST;
else
fence_next_state[2:0] = WAIT_CMPLT;
POP_INST : fence_next_state[2:0] = IDLE;
default : fence_next_state[2:0] = IDLE;
endcase
// &CombEnd; @181
end
//----------------------------------------------------------
// control signals
//----------------------------------------------------------
assign fence_ctrl_id_stall = ctrl_fence_id_inst_vld
&& !fence_cur_state[2]; //POP_INST
assign fence_ctrl_inst0_vld = (fence_cur_state[2:0] == ISSUE);
assign fence_ctrl_inst1_vld = (fence_cur_state[2:0] == ISSUE)
&& dp_fence_id_fence_type[2]; //fence
assign fence_ctrl_inst2_vld = (fence_cur_state[2:0] == ISSUE)
&& dp_fence_id_fence_type[2]; //fence
assign fence_top_cur_state[2:0] = fence_cur_state[2:0];
assign idu_rtu_fence_idle = (fence_cur_state[2:0] == IDLE)
|| (fence_cur_state[2:0] != IDLE)
&& dp_fence_id_fence_type[1]
&& !(dp_fence_id_inst[31:0] == 32'h10500073); //wfi
assign idu_hpcp_fence_sync_vld = (fence_cur_state[2:0] == POP_INST)
&& (dp_fence_id_fence_type[0]
|| dp_fence_id_fence_type[2]);
//----------------------------------------------------------
// Sync Instuction: sync
//----------------------------------------------------------
// &CombBeg; @213
always @( dp_fence_id_inst[31:0])
begin
fence_inst0_sync_data[IR_WIDTH-1:0] = {IR_WIDTH{1'b0}};
if(1'b1) begin
fence_inst0_sync_data[IR_OPCODE:IR_OPCODE-31] = dp_fence_id_inst[31:0];
fence_inst0_sync_data[IR_INST_TYPE:IR_INST_TYPE-9] = LSU;
fence_inst0_sync_data[IR_LENGTH] = 1'b1;
end
// &CombEnd; @220
end
assign fence_inst2_sync_opcode[31:0] = 32'h01b0000b;
// &CombBeg; @224
always @( fence_inst2_sync_opcode[31:0])
begin
fence_inst2_sync_data[IR_WIDTH-1:0] = {IR_WIDTH{1'b0}};
if(1'b1) begin
fence_inst2_sync_data[IR_OPCODE:IR_OPCODE-31] = fence_inst2_sync_opcode[31:0];
fence_inst2_sync_data[IR_INST_TYPE:IR_INST_TYPE-9] = LSU;
fence_inst2_sync_data[IR_LENGTH] = 1'b1;
end
// &CombEnd; @231
end
//----------------------------------------------------------
// Fence Instuction: cp0
//----------------------------------------------------------
assign fence_inst0_cp0_csrr = ({dp_fence_id_inst[14:12],dp_fence_id_inst[6:0]}
== 10'b001_1110011) //csrrw
|| ({dp_fence_id_inst[14:12],dp_fence_id_inst[6:0]}
== 10'b010_1110011) //csrrs
|| ({dp_fence_id_inst[14:12],dp_fence_id_inst[6:0]}
== 10'b011_1110011); //csrrc
assign fence_inst0_cp0_csri = ({dp_fence_id_inst[14:12],dp_fence_id_inst[6:0]}
== 10'b101_1110011) //csrwi
|| ({dp_fence_id_inst[14:12],dp_fence_id_inst[6:0]}
== 10'b110_1110011) //csrsi
|| ({dp_fence_id_inst[14:12],dp_fence_id_inst[6:0]}
== 10'b111_1110011); //csrci
// &CombBeg; @250
always @( dp_fence_id_inst[31:0]
or fence_inst0_cp0_csrr
or fence_inst0_cp0_csri)
begin
fence_inst0_cp0_data[IR_WIDTH-1:0] = {IR_WIDTH{1'b0}};
if(1'b1) begin
fence_inst0_cp0_data[IR_OPCODE:IR_OPCODE-31] = dp_fence_id_inst[31:0];
fence_inst0_cp0_data[IR_INST_TYPE:IR_INST_TYPE-9] = SPECIAL;
fence_inst0_cp0_data[IR_SRC0_VLD] = fence_inst0_cp0_csrr;
fence_inst0_cp0_data[IR_SRC0_REG:IR_SRC0_REG-5] = {1'b0,dp_fence_id_inst[19:15]};
fence_inst0_cp0_data[IR_DST_VLD] = fence_inst0_cp0_csrr || fence_inst0_cp0_csri;
fence_inst0_cp0_data[IR_DST_REG:IR_DST_REG-5] = {1'b0,dp_fence_id_inst[11:7]};
fence_inst0_cp0_data[IR_LENGTH] = 1'b1;
end
// &CombEnd; @261
end
//----------------------------------------------------------
// Fence Instuction: fence
//----------------------------------------------------------
assign fence_inst0_bar_opcode[31:0] = 32'h0ff0000f; //fence
// &CombBeg; @268
always @( fence_inst0_bar_opcode[31:0])
begin
fence_inst0_fence_data[IR_WIDTH-1:0] = {IR_WIDTH{1'b0}};
if(1'b1) begin
fence_inst0_fence_data[IR_OPCODE:IR_OPCODE-31] = fence_inst0_bar_opcode[31:0];
fence_inst0_fence_data[IR_INST_TYPE:IR_INST_TYPE-9] = LSU;
fence_inst0_fence_data[IR_LENGTH] = 1'b1;
fence_inst0_fence_data[IR_SPLIT] = 1'b1;
end
// &CombEnd; @276
end
assign fence_inst0_fence_fencei = (dp_fence_id_inst[6:0] == 7'b0001111);
assign fence_inst0_fence_sfence_asid = (dp_fence_id_inst[24:20] != 5'd0)
&& !fence_inst0_fence_fencei;
assign fence_inst0_fence_sfence_va = (dp_fence_id_inst[19:15] != 5'd0)
&& !fence_inst0_fence_fencei;
// &CombBeg; @284
always @( dp_fence_id_inst[31:0]
or fence_inst0_fence_sfence_asid
or fence_inst0_fence_sfence_va)
begin
fence_inst1_fence_data[IR_WIDTH-1:0] = {IR_WIDTH{1'b0}};
if(1'b1) begin
fence_inst1_fence_data[IR_OPCODE:IR_OPCODE-31] = dp_fence_id_inst[31:0];
fence_inst1_fence_data[IR_INST_TYPE:IR_INST_TYPE-9] = fence_inst0_fence_sfence_asid
? LSU_P5 : LSU;
fence_inst1_fence_data[IR_SRC0_VLD] = fence_inst0_fence_sfence_va;
fence_inst1_fence_data[IR_SRC0_REG:IR_SRC0_REG-5] = {1'b0,dp_fence_id_inst[19:15]};
fence_inst1_fence_data[IR_SRC1_VLD] = fence_inst0_fence_sfence_asid;
fence_inst1_fence_data[IR_SRC1_REG:IR_SRC1_REG-5] = {1'b0,dp_fence_id_inst[24:20]};
fence_inst1_fence_data[IR_LENGTH] = 1'b1;
fence_inst1_fence_data[IR_SPLIT] = 1'b1;
end
// &CombEnd; @297
end
//==========================================================
// Fence Instructions Selection
//==========================================================
//----------------------------------------------------------
// MUX between fence instructions
//----------------------------------------------------------
// &CombBeg; @305
always @( fence_inst0_cp0_data[177:0]
or fence_inst0_sync_data[177:0]
or fence_inst0_fence_data[177:0]
or dp_fence_id_fence_type[2:0])
begin
case(dp_fence_id_fence_type[2:0])
3'b001 : fence_inst0_data[IR_WIDTH-1:0] = fence_inst0_sync_data[IR_WIDTH-1:0];
3'b010 : fence_inst0_data[IR_WIDTH-1:0] = fence_inst0_cp0_data[IR_WIDTH-1:0];
3'b100 : fence_inst0_data[IR_WIDTH-1:0] = fence_inst0_fence_data[IR_WIDTH-1:0];
default: fence_inst0_data[IR_WIDTH-1:0] = {IR_WIDTH{1'bx}};
endcase
// &CombEnd; @312
end
assign fence_inst1_data[IR_WIDTH-1:0] = fence_inst1_fence_data[IR_WIDTH-1:0];
assign fence_inst2_data[IR_WIDTH-1:0] = fence_inst2_sync_data[IR_WIDTH-1:0];
//fence no inst2/3
//----------------------------------------------------------
// Re-Pack into IR data path form
//----------------------------------------------------------
// &CombBeg; @322
always @( dp_fence_id_pc[14:0]
or dp_fence_id_bkpta_inst
or dp_fence_id_vl_pred
or dp_fence_id_bkptb_inst
or dp_fence_id_vl[7:0]
or dp_fence_id_vlmul[1:0]
or dp_fence_id_vsew[2:0]
or fence_inst0_data[177:0])
begin
fence_dp_inst0_data[IR_WIDTH-1:0] = fence_inst0_data[IR_WIDTH-1:0];
if(1'b1) begin
fence_dp_inst0_data[IR_DST_X0] = (fence_inst0_data[IR_DST_REG:IR_DST_REG-5]
== 6'd0);
fence_dp_inst0_data[IR_BKPTB_INST] = dp_fence_id_bkptb_inst;
fence_dp_inst0_data[IR_BKPTA_INST] = dp_fence_id_bkpta_inst;
fence_dp_inst0_data[IR_VLMUL:IR_VLMUL-1] = dp_fence_id_vlmul[1:0];
fence_dp_inst0_data[IR_VSEW:IR_VSEW-2] = dp_fence_id_vsew[2:0];
fence_dp_inst0_data[IR_VL:IR_VL-7] = dp_fence_id_vl[7:0];
fence_dp_inst0_data[IR_VL_PRED] = dp_fence_id_vl_pred;
fence_dp_inst0_data[IR_PC:IR_PC-14] = dp_fence_id_pc[14:0];
end
// &CombEnd; @335
end
// &CombBeg; @337
always @( fence_inst1_data[177:0]
or dp_fence_id_pc[14:0]
or dp_fence_id_vl_pred
or dp_fence_id_bkpta_inst
or dp_fence_id_bkptb_inst
or dp_fence_id_vlmul[1:0]
or dp_fence_id_vl[7:0]
or dp_fence_id_vsew[2:0])
begin
fence_dp_inst1_data[IR_WIDTH-1:0] = fence_inst1_data[IR_WIDTH-1:0];
if(1'b1) begin
fence_dp_inst1_data[IR_DST_X0] = (fence_inst1_data[IR_DST_REG:IR_DST_REG-5]
== 6'd0);
fence_dp_inst1_data[IR_BKPTB_INST] = dp_fence_id_bkptb_inst;
fence_dp_inst1_data[IR_BKPTA_INST] = dp_fence_id_bkpta_inst;
fence_dp_inst1_data[IR_VLMUL:IR_VLMUL-1] = dp_fence_id_vlmul[1:0];
fence_dp_inst1_data[IR_VSEW:IR_VSEW-2] = dp_fence_id_vsew[2:0];
fence_dp_inst1_data[IR_VL:IR_VL-7] = dp_fence_id_vl[7:0];
fence_dp_inst1_data[IR_VL_PRED] = dp_fence_id_vl_pred;
fence_dp_inst1_data[IR_PC:IR_PC-14] = dp_fence_id_pc[14:0];
end
// &CombEnd; @350
end
// &CombBeg; @352
always @( fence_inst2_data[177:0]
or dp_fence_id_pc[14:0]
or dp_fence_id_vl_pred
or dp_fence_id_bkpta_inst
or dp_fence_id_bkptb_inst
or dp_fence_id_vlmul[1:0]
or dp_fence_id_vl[7:0]
or dp_fence_id_vsew[2:0])
begin
fence_dp_inst2_data[IR_WIDTH-1:0] = fence_inst2_data[IR_WIDTH-1:0];
if(1'b1) begin
fence_dp_inst2_data[IR_DST_X0] = (fence_inst2_data[IR_DST_REG:IR_DST_REG-5]
== 6'd0);
fence_dp_inst2_data[IR_BKPTB_INST] = dp_fence_id_bkptb_inst;
fence_dp_inst2_data[IR_BKPTA_INST] = dp_fence_id_bkpta_inst;
fence_dp_inst2_data[IR_VLMUL:IR_VLMUL-1] = dp_fence_id_vlmul[1:0];
fence_dp_inst2_data[IR_VSEW:IR_VSEW-2] = dp_fence_id_vsew[2:0];
fence_dp_inst2_data[IR_VL:IR_VL-7] = dp_fence_id_vl[7:0];
fence_dp_inst2_data[IR_VL_PRED] = dp_fence_id_vl_pred;
fence_dp_inst2_data[IR_PC:IR_PC-14] = dp_fence_id_pc[14:0];
end
// &CombEnd; @365
end
// &ModuleEnd; @368
endmodule |
module ct_idu_rf_prf_gated_preg(
cp0_idu_icg_en,
cp0_yy_clk_en,
forever_cpuclk,
iu_idu_ex2_pipe0_wb_preg_data,
iu_idu_ex2_pipe1_wb_preg_data,
lsu_idu_wb_pipe3_wb_preg_data,
pad_yy_icg_scan_en,
x_reg_dout,
x_wb_vld
);
// &Ports; @28
input cp0_idu_icg_en;
input cp0_yy_clk_en;
input forever_cpuclk;
input [63:0] iu_idu_ex2_pipe0_wb_preg_data;
input [63:0] iu_idu_ex2_pipe1_wb_preg_data;
input [63:0] lsu_idu_wb_pipe3_wb_preg_data;
input pad_yy_icg_scan_en;
input [2 :0] x_wb_vld;
output [63:0] x_reg_dout;
// &Regs; @29
reg [63:0] reg_dout;
reg [63:0] write_data;
// &Wires; @30
wire cp0_idu_icg_en;
wire cp0_yy_clk_en;
wire forever_cpuclk;
wire [63:0] iu_idu_ex2_pipe0_wb_preg_data;
wire [63:0] iu_idu_ex2_pipe1_wb_preg_data;
wire [63:0] lsu_idu_wb_pipe3_wb_preg_data;
wire pad_yy_icg_scan_en;
wire preg_clk;
wire preg_clk_en;
wire write_en;
wire [63:0] x_reg_dout;
wire [2 :0] x_wb_vld;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign preg_clk_en = write_en;
// &Instance("gated_clk_cell", "x_preg_gated_clk"); @37
gated_clk_cell x_preg_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (preg_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (preg_clk_en ),
.module_en (cp0_idu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @38
// .external_en (1'b0), @39
// .global_en (cp0_yy_clk_en), @40
// .module_en (cp0_idu_icg_en), @41
// .local_en (preg_clk_en), @42
// .clk_out (preg_clk)); @43
//==========================================================
// Write Port
//==========================================================
assign write_en = |x_wb_vld[2:0];
// &CombBeg; @49
always @( iu_idu_ex2_pipe0_wb_preg_data[63:0]
or x_wb_vld[2:0]
or lsu_idu_wb_pipe3_wb_preg_data[63:0]
or iu_idu_ex2_pipe1_wb_preg_data[63:0])
begin
case (x_wb_vld[2:0])
3'b001 : write_data[63:0] = iu_idu_ex2_pipe0_wb_preg_data[63:0];
3'b010 : write_data[63:0] = iu_idu_ex2_pipe1_wb_preg_data[63:0];
3'b100 : write_data[63:0] = lsu_idu_wb_pipe3_wb_preg_data[63:0];
default: write_data[63:0] = {64{1'bx}};
endcase
// &CombEnd; @56
end
//==========================================================
// Preg Register
//==========================================================
always @(posedge preg_clk)
begin
if(write_en)
reg_dout[63:0] <= write_data[63:0];
else
reg_dout[63:0] <= reg_dout[63:0];
end
assign x_reg_dout[63:0] = reg_dout[63:0];
// &ModuleEnd; @91
endmodule |
module ct_idu_rf_fwd_preg(
iu_idu_ex1_pipe0_fwd_preg,
iu_idu_ex1_pipe0_fwd_preg_data,
iu_idu_ex1_pipe0_fwd_preg_vld,
iu_idu_ex1_pipe1_fwd_preg,
iu_idu_ex1_pipe1_fwd_preg_data,
iu_idu_ex1_pipe1_fwd_preg_vld,
iu_idu_ex2_pipe0_wb_preg,
iu_idu_ex2_pipe0_wb_preg_data,
iu_idu_ex2_pipe0_wb_preg_vld,
iu_idu_ex2_pipe1_wb_preg,
iu_idu_ex2_pipe1_wb_preg_data,
iu_idu_ex2_pipe1_wb_preg_vld,
lsu_idu_da_pipe3_fwd_preg,
lsu_idu_da_pipe3_fwd_preg_data,
lsu_idu_da_pipe3_fwd_preg_vld,
lsu_idu_wb_pipe3_wb_preg,
lsu_idu_wb_pipe3_wb_preg_data,
lsu_idu_wb_pipe3_wb_preg_vld,
x_src_data,
x_src_no_fwd,
x_src_reg
);
// &Ports; @27
input [6 :0] iu_idu_ex1_pipe0_fwd_preg;
input [63:0] iu_idu_ex1_pipe0_fwd_preg_data;
input iu_idu_ex1_pipe0_fwd_preg_vld;
input [6 :0] iu_idu_ex1_pipe1_fwd_preg;
input [63:0] iu_idu_ex1_pipe1_fwd_preg_data;
input iu_idu_ex1_pipe1_fwd_preg_vld;
input [6 :0] iu_idu_ex2_pipe0_wb_preg;
input [63:0] iu_idu_ex2_pipe0_wb_preg_data;
input iu_idu_ex2_pipe0_wb_preg_vld;
input [6 :0] iu_idu_ex2_pipe1_wb_preg;
input [63:0] iu_idu_ex2_pipe1_wb_preg_data;
input iu_idu_ex2_pipe1_wb_preg_vld;
input [6 :0] lsu_idu_da_pipe3_fwd_preg;
input [63:0] lsu_idu_da_pipe3_fwd_preg_data;
input lsu_idu_da_pipe3_fwd_preg_vld;
input [6 :0] lsu_idu_wb_pipe3_wb_preg;
input [63:0] lsu_idu_wb_pipe3_wb_preg_data;
input lsu_idu_wb_pipe3_wb_preg_vld;
input [6 :0] x_src_reg;
output [63:0] x_src_data;
output x_src_no_fwd;
// &Regs; @28
reg [63:0] x_src_data;
// &Wires; @29
wire [5 :0] fwd_src_sel;
wire [6 :0] iu_idu_ex1_pipe0_fwd_preg;
wire [63:0] iu_idu_ex1_pipe0_fwd_preg_data;
wire iu_idu_ex1_pipe0_fwd_preg_vld;
wire [6 :0] iu_idu_ex1_pipe1_fwd_preg;
wire [63:0] iu_idu_ex1_pipe1_fwd_preg_data;
wire iu_idu_ex1_pipe1_fwd_preg_vld;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg;
wire [63:0] iu_idu_ex2_pipe0_wb_preg_data;
wire iu_idu_ex2_pipe0_wb_preg_vld;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg;
wire [63:0] iu_idu_ex2_pipe1_wb_preg_data;
wire iu_idu_ex2_pipe1_wb_preg_vld;
wire [6 :0] lsu_idu_da_pipe3_fwd_preg;
wire [63:0] lsu_idu_da_pipe3_fwd_preg_data;
wire lsu_idu_da_pipe3_fwd_preg_vld;
wire [6 :0] lsu_idu_wb_pipe3_wb_preg;
wire [63:0] lsu_idu_wb_pipe3_wb_preg_data;
wire lsu_idu_wb_pipe3_wb_preg_vld;
wire x_src_no_fwd;
wire [6 :0] x_src_reg;
//==========================================================
// Preg Forward
//==========================================================
//0: pipe0 ex1, 1: pipe0 ex2, 2: pipe1 ex1, 3: pipe1 ex2, 4: pipe3 da, 5: pipe3 wb
assign fwd_src_sel[0] = iu_idu_ex1_pipe0_fwd_preg_vld
&& (x_src_reg[6:0] == iu_idu_ex1_pipe0_fwd_preg[6:0]);
assign fwd_src_sel[1] = iu_idu_ex2_pipe0_wb_preg_vld
&& (x_src_reg[6:0] == iu_idu_ex2_pipe0_wb_preg[6:0]);
assign fwd_src_sel[2] = iu_idu_ex1_pipe1_fwd_preg_vld
&& (x_src_reg[6:0] == iu_idu_ex1_pipe1_fwd_preg[6:0]);
assign fwd_src_sel[3] = iu_idu_ex2_pipe1_wb_preg_vld
&& (x_src_reg[6:0] == iu_idu_ex2_pipe1_wb_preg[6:0]);
assign fwd_src_sel[4] = lsu_idu_da_pipe3_fwd_preg_vld
&& (x_src_reg[6:0] == lsu_idu_da_pipe3_fwd_preg[6:0]);
assign fwd_src_sel[5] = lsu_idu_wb_pipe3_wb_preg_vld
&& (x_src_reg[6:0] == lsu_idu_wb_pipe3_wb_preg[6:0]);
assign x_src_no_fwd = !(|fwd_src_sel[5:0]);
// &CombBeg; @51
always @( iu_idu_ex1_pipe1_fwd_preg_data[63:0]
or lsu_idu_da_pipe3_fwd_preg_data[63:0]
or iu_idu_ex2_pipe0_wb_preg_data[63:0]
or iu_idu_ex1_pipe0_fwd_preg_data[63:0]
or lsu_idu_wb_pipe3_wb_preg_data[63:0]
or iu_idu_ex2_pipe1_wb_preg_data[63:0]
or fwd_src_sel[5:0])
begin
case (fwd_src_sel[5:0])
6'b000001: x_src_data[63:0] = iu_idu_ex1_pipe0_fwd_preg_data[63:0];
6'b000010: x_src_data[63:0] = iu_idu_ex2_pipe0_wb_preg_data[63:0];
6'b000100: x_src_data[63:0] = iu_idu_ex1_pipe1_fwd_preg_data[63:0];
6'b001000: x_src_data[63:0] = iu_idu_ex2_pipe1_wb_preg_data[63:0];
6'b010000: x_src_data[63:0] = lsu_idu_da_pipe3_fwd_preg_data[63:0];
6'b100000: x_src_data[63:0] = lsu_idu_wb_pipe3_wb_preg_data[63:0];
default : x_src_data[63:0] = {64{1'bx}};
endcase
// &CombEnd; @61
end
// &ModuleEnd; @64
endmodule |
module ct_vfdsu_pack(
ex4_out_expt,
ex4_out_result,
vfdsu_ex4_denorm_to_tiny_frac,
vfdsu_ex4_double,
vfdsu_ex4_dz,
vfdsu_ex4_expnt_rst,
vfdsu_ex4_frac,
vfdsu_ex4_nv,
vfdsu_ex4_nx,
vfdsu_ex4_of,
vfdsu_ex4_of_rst_lfn,
vfdsu_ex4_potnt_norm,
vfdsu_ex4_potnt_of,
vfdsu_ex4_potnt_uf,
vfdsu_ex4_qnan_f,
vfdsu_ex4_qnan_sign,
vfdsu_ex4_result_inf,
vfdsu_ex4_result_lfn,
vfdsu_ex4_result_nor,
vfdsu_ex4_result_qnan,
vfdsu_ex4_result_sign,
vfdsu_ex4_result_zero,
vfdsu_ex4_rslt_denorm,
vfdsu_ex4_single,
vfdsu_ex4_uf
);
// &Ports; @23
input vfdsu_ex4_denorm_to_tiny_frac;
input vfdsu_ex4_double;
input vfdsu_ex4_dz;
input [12:0] vfdsu_ex4_expnt_rst;
input [54:0] vfdsu_ex4_frac;
input vfdsu_ex4_nv;
input vfdsu_ex4_nx;
input vfdsu_ex4_of;
input vfdsu_ex4_of_rst_lfn;
input [1 :0] vfdsu_ex4_potnt_norm;
input vfdsu_ex4_potnt_of;
input vfdsu_ex4_potnt_uf;
input [51:0] vfdsu_ex4_qnan_f;
input vfdsu_ex4_qnan_sign;
input vfdsu_ex4_result_inf;
input vfdsu_ex4_result_lfn;
input vfdsu_ex4_result_nor;
input vfdsu_ex4_result_qnan;
input vfdsu_ex4_result_sign;
input vfdsu_ex4_result_zero;
input vfdsu_ex4_rslt_denorm;
input vfdsu_ex4_single;
input vfdsu_ex4_uf;
output [4 :0] ex4_out_expt;
output [63:0] ex4_out_result;
// &Regs; @24
reg [51:0] ex4_denorm_frac;
reg [51:0] ex4_frac_52;
reg [51:0] ex4_half_denorm_frac;
reg [63:0] ex4_out_result;
reg [51:0] ex4_single_denorm_frac;
reg [12:0] expnt_add_op1;
// &Wires; @25
wire ex4_cor_nx;
wire ex4_cor_uf;
wire ex4_denorm_potnt_norm;
wire [63:0] ex4_denorm_result;
wire [63:0] ex4_doub_lfn;
wire [63:0] ex4_doub_rst0;
wire [63:0] ex4_doub_rst_inf;
wire [63:0] ex4_doub_rst_norm;
wire [63:0] ex4_doub_rst_qnan;
wire [12:0] ex4_expnt_rst;
wire ex4_final_rst_norm;
wire [54:0] ex4_frac;
wire [63:0] ex4_half_lfn;
wire [63:0] ex4_half_rst0;
wire [63:0] ex4_half_rst_inf;
wire [63:0] ex4_half_rst_norm;
wire [63:0] ex4_half_rst_qnan;
wire ex4_of_plus;
wire [4 :0] ex4_out_expt;
wire ex4_result_inf;
wire ex4_result_lfn;
wire ex4_rslt_denorm;
wire [63:0] ex4_rst0;
wire [63:0] ex4_rst_inf;
wire [63:0] ex4_rst_lfn;
wire ex4_rst_nor;
wire [63:0] ex4_rst_norm;
wire [63:0] ex4_rst_qnan;
wire [63:0] ex4_sing_lfn;
wire [63:0] ex4_sing_rst0;
wire [63:0] ex4_sing_rst_inf;
wire [63:0] ex4_sing_rst_norm;
wire [63:0] ex4_sing_rst_qnan;
wire ex4_uf_plus;
wire vfdsu_ex4_denorm_to_tiny_frac;
wire vfdsu_ex4_double;
wire vfdsu_ex4_dz;
wire [12:0] vfdsu_ex4_expnt_rst;
wire [54:0] vfdsu_ex4_frac;
wire vfdsu_ex4_nv;
wire vfdsu_ex4_nx;
wire vfdsu_ex4_of;
wire vfdsu_ex4_of_rst_lfn;
wire [1 :0] vfdsu_ex4_potnt_norm;
wire vfdsu_ex4_potnt_of;
wire vfdsu_ex4_potnt_uf;
wire [51:0] vfdsu_ex4_qnan_f;
wire vfdsu_ex4_qnan_sign;
wire vfdsu_ex4_result_inf;
wire vfdsu_ex4_result_lfn;
wire vfdsu_ex4_result_nor;
wire vfdsu_ex4_result_qnan;
wire vfdsu_ex4_result_sign;
wire vfdsu_ex4_result_zero;
wire vfdsu_ex4_rslt_denorm;
wire vfdsu_ex4_single;
wire vfdsu_ex4_uf;
//============================EX4 STAGE=====================
assign ex4_frac[54:0] = vfdsu_ex4_frac[54:0];
//exponent adder
// &CombBeg; @30
always @( ex4_frac[54:53])
begin
casez(ex4_frac[54:53])
2'b00 : expnt_add_op1[12:0] = 13'h0fff; //the expnt sub 1
2'b01 : expnt_add_op1[12:0] = 13'h0; //the expnt stay the origi
2'b1? : expnt_add_op1[12:0] = 13'h1; // the exptn add 1
default : expnt_add_op1[12:0] = 13'b0;
endcase
// &CombEnd; @37
end
assign ex4_expnt_rst[12:0] = vfdsu_ex4_expnt_rst[12:0] +
expnt_add_op1[12:0];
//==========================Result Pack=====================
// result denormal pack
// shift to the denormal number
// &CombBeg; @45
always @( vfdsu_ex4_expnt_rst[12:0]
or ex4_frac[54:1]
or vfdsu_ex4_denorm_to_tiny_frac)
begin
case(vfdsu_ex4_expnt_rst[12:0])
13'h1: ex4_denorm_frac[51:0] = { ex4_frac[52:1]}; //-1022 1
13'h0: ex4_denorm_frac[51:0] = { ex4_frac[53:2]}; //-1023 0
13'h1fff:ex4_denorm_frac[51:0] = { ex4_frac[54:3]}; //-1024 -1
13'h1ffe:ex4_denorm_frac[51:0] = {1'b0, ex4_frac[54:4]}; //-1025 -2
13'h1ffd:ex4_denorm_frac[51:0] = {2'b0, ex4_frac[54:5]}; //-1026 -3
13'h1ffc:ex4_denorm_frac[51:0] = {3'b0, ex4_frac[54:6]}; //-1027 -4
13'h1ffb:ex4_denorm_frac[51:0] = {4'b0, ex4_frac[54:7]}; //-1028 -5
13'h1ffa:ex4_denorm_frac[51:0] = {5'b0, ex4_frac[54:8]}; //-1029 -6
13'h1ff9:ex4_denorm_frac[51:0] = {6'b0, ex4_frac[54:9]}; //-1030 -7
13'h1ff8:ex4_denorm_frac[51:0] = {7'b0, ex4_frac[54:10]}; //-1031 -8
13'h1ff7:ex4_denorm_frac[51:0] = {8'b0, ex4_frac[54:11]}; //-1032 -9
13'h1ff6:ex4_denorm_frac[51:0] = {9'b0, ex4_frac[54:12]}; //-1033 -10
13'h1ff5:ex4_denorm_frac[51:0] = {10'b0,ex4_frac[54:13]}; //-1034 -11
13'h1ff4:ex4_denorm_frac[51:0] = {11'b0,ex4_frac[54:14]}; //-1035 -12
13'h1ff3:ex4_denorm_frac[51:0] = {12'b0,ex4_frac[54:15]}; //-1036 -13
13'h1ff2:ex4_denorm_frac[51:0] = {13'b0,ex4_frac[54:16]}; // -1037
13'h1ff1:ex4_denorm_frac[51:0] = {14'b0,ex4_frac[54:17]}; //-1038
13'h1ff0:ex4_denorm_frac[51:0] = {15'b0,ex4_frac[54:18]}; //-1039
13'h1fef:ex4_denorm_frac[51:0] = {16'b0,ex4_frac[54:19]}; //-1040
13'h1fee:ex4_denorm_frac[51:0] = {17'b0,ex4_frac[54:20]}; //-1041
13'h1fed:ex4_denorm_frac[51:0] = {18'b0,ex4_frac[54:21]}; //-1042
13'h1fec:ex4_denorm_frac[51:0] = {19'b0,ex4_frac[54:22]}; //-1043
13'h1feb:ex4_denorm_frac[51:0] = {20'b0,ex4_frac[54:23]}; //-1044
13'h1fea:ex4_denorm_frac[51:0] = {21'b0,ex4_frac[54:24]}; //-1045
13'h1fe9:ex4_denorm_frac[51:0] = {22'b0,ex4_frac[54:25]}; //-1046
13'h1fe8:ex4_denorm_frac[51:0] = {23'b0,ex4_frac[54:26]}; //-1047
13'h1fe7:ex4_denorm_frac[51:0] = {24'b0,ex4_frac[54:27]}; //-1048
13'h1fe6:ex4_denorm_frac[51:0] = {25'b0,ex4_frac[54:28]}; //-1049
13'h1fe5:ex4_denorm_frac[51:0] = {26'b0,ex4_frac[54:29]}; //-1050
13'h1fe4:ex4_denorm_frac[51:0] = {27'b0,ex4_frac[54:30]}; //-1056
13'h1fe3:ex4_denorm_frac[51:0] = {28'b0,ex4_frac[54:31]}; //-1052
13'h1fe2:ex4_denorm_frac[51:0] = {29'b0,ex4_frac[54:32]}; //-1053
13'h1fe1:ex4_denorm_frac[51:0] = {30'b0,ex4_frac[54:33]}; //-1054
13'h1fe0:ex4_denorm_frac[51:0] = {31'b0,ex4_frac[54:34]}; //-1055
13'h1fdf:ex4_denorm_frac[51:0] = {32'b0,ex4_frac[54:35]}; //-1056
13'h1fde:ex4_denorm_frac[51:0] = {33'b0,ex4_frac[54:36]}; //-1057
13'h1fdd:ex4_denorm_frac[51:0] = {34'b0,ex4_frac[54:37]}; //-1058
13'h1fdc:ex4_denorm_frac[51:0] = {35'b0,ex4_frac[54:38]}; //-1059
13'h1fdb:ex4_denorm_frac[51:0] = {36'b0,ex4_frac[54:39]}; //-1060
13'h1fda:ex4_denorm_frac[51:0] = {37'b0,ex4_frac[54:40]}; //-1061
13'h1fd9:ex4_denorm_frac[51:0] = {38'b0,ex4_frac[54:41]}; //-1062
13'h1fd8:ex4_denorm_frac[51:0] = {39'b0,ex4_frac[54:42]}; //-1063
13'h1fd7:ex4_denorm_frac[51:0] = {40'b0,ex4_frac[54:43]}; //-1064
13'h1fd6:ex4_denorm_frac[51:0] = {41'b0,ex4_frac[54:44]}; //-1065
13'h1fd5:ex4_denorm_frac[51:0] = {42'b0,ex4_frac[54:45]}; //-1066
13'h1fd4:ex4_denorm_frac[51:0] = {43'b0,ex4_frac[54:46]}; //-1067
13'h1fd3:ex4_denorm_frac[51:0] = {44'b0,ex4_frac[54:47]}; //-1068
13'h1fd2:ex4_denorm_frac[51:0] = {45'b0,ex4_frac[54:48]}; //-1069
13'h1fd1:ex4_denorm_frac[51:0] = {46'b0,ex4_frac[54:49]}; //-1070
13'h1fd0:ex4_denorm_frac[51:0] = {47'b0,ex4_frac[54:50]}; //-1071
13'h1fcf:ex4_denorm_frac[51:0] = {48'b0,ex4_frac[54:51]}; //-1072
13'h1fce:ex4_denorm_frac[51:0] = {49'b0,ex4_frac[54:52]}; //-1073
13'h1fcd:ex4_denorm_frac[51:0] = {50'b0,ex4_frac[54:53]}; //-1074
default: ex4_denorm_frac[51:0] = vfdsu_ex4_denorm_to_tiny_frac ? 52'b1 : 52'b0;
endcase
// &CombEnd; @102
end
// &CombBeg; @103
always @( vfdsu_ex4_expnt_rst[12:0]
or ex4_frac[54:1]
or vfdsu_ex4_denorm_to_tiny_frac)
begin
case(vfdsu_ex4_expnt_rst[12:0])
13'h1: ex4_single_denorm_frac[51:0] = { ex4_frac[52:1]}; //-1022 1
13'h0: ex4_single_denorm_frac[51:0] = { ex4_frac[53:2]}; //-1023 0
13'h1fff:ex4_single_denorm_frac[51:0] = { ex4_frac[54:3]}; //-1024 -1
13'h1ffe:ex4_single_denorm_frac[51:0] = {1'b0, ex4_frac[54:4]}; //-1025 -2
13'h1ffd:ex4_single_denorm_frac[51:0] = {2'b0, ex4_frac[54:5]}; //-1026 -3
13'h1ffc:ex4_single_denorm_frac[51:0] = {3'b0, ex4_frac[54:6]}; //-1027 -4
13'h1ffb:ex4_single_denorm_frac[51:0] = {4'b0, ex4_frac[54:7]}; //-1028 -5
13'h1ffa:ex4_single_denorm_frac[51:0] = {5'b0, ex4_frac[54:8]}; //-1029 -6
13'h1ff9:ex4_single_denorm_frac[51:0] = {6'b0, ex4_frac[54:9]}; //-1030 -7
13'h1ff8:ex4_single_denorm_frac[51:0] = {7'b0, ex4_frac[54:10]}; //-1031 -8
13'h1ff7:ex4_single_denorm_frac[51:0] = {8'b0, ex4_frac[54:11]}; //-1032 -9
13'h1ff6:ex4_single_denorm_frac[51:0] = {9'b0, ex4_frac[54:12]}; //-1033 -10
13'h1ff5:ex4_single_denorm_frac[51:0] = {10'b0,ex4_frac[54:13]}; //-1034 -11
13'h1ff4:ex4_single_denorm_frac[51:0] = {11'b0,ex4_frac[54:14]}; //-1035 -12
13'h1ff3:ex4_single_denorm_frac[51:0] = {12'b0,ex4_frac[54:15]}; //-1036 -13
13'h1ff2:ex4_single_denorm_frac[51:0] = {13'b0,ex4_frac[54:16]}; // -1037
13'h1ff1:ex4_single_denorm_frac[51:0] = {14'b0,ex4_frac[54:17]}; //-1038
13'h1ff0:ex4_single_denorm_frac[51:0] = {15'b0,ex4_frac[54:18]}; //-1039
13'h1fef:ex4_single_denorm_frac[51:0] = {16'b0,ex4_frac[54:19]}; //-1040
13'h1fee:ex4_single_denorm_frac[51:0] = {17'b0,ex4_frac[54:20]}; //-1041
13'h1fed:ex4_single_denorm_frac[51:0] = {18'b0,ex4_frac[54:21]}; //-1042
13'h1fec:ex4_single_denorm_frac[51:0] = {19'b0,ex4_frac[54:22]}; //-1043
13'h1feb:ex4_single_denorm_frac[51:0] = {20'b0,ex4_frac[54:23]}; //-1044
13'h1fea:ex4_single_denorm_frac[51:0] = {21'b0,ex4_frac[54:24]}; //-1044
default :ex4_single_denorm_frac[51:0] = vfdsu_ex4_denorm_to_tiny_frac ?{23'b1,29'b0} : 52'b0; //-1045
endcase
// &CombEnd; @131
end
// &CombBeg; @132
always @( vfdsu_ex4_expnt_rst[12:0]
or ex4_frac[54:1]
or vfdsu_ex4_denorm_to_tiny_frac)
begin
case(vfdsu_ex4_expnt_rst[12:0])
13'h1: ex4_half_denorm_frac[51:0] = { ex4_frac[52:1]}; //-1022 1
13'h0: ex4_half_denorm_frac[51:0] = { ex4_frac[53:2]}; //-1023 0
13'h1fff:ex4_half_denorm_frac[51:0] = { ex4_frac[54:3]}; //-1024 -1
13'h1ffe:ex4_half_denorm_frac[51:0] = {1'b0, ex4_frac[54:4]}; //-1025 -2
13'h1ffd:ex4_half_denorm_frac[51:0] = {2'b0, ex4_frac[54:5]}; //-1026 -3
13'h1ffc:ex4_half_denorm_frac[51:0] = {3'b0, ex4_frac[54:6]}; //-1027 -4
13'h1ffb:ex4_half_denorm_frac[51:0] = {4'b0, ex4_frac[54:7]}; //-1028 -5
13'h1ffa:ex4_half_denorm_frac[51:0] = {5'b0, ex4_frac[54:8]}; //-1029 -6
13'h1ff9:ex4_half_denorm_frac[51:0] = {6'b0, ex4_frac[54:9]}; //-1030 -7
13'h1ff8:ex4_half_denorm_frac[51:0] = {7'b0, ex4_frac[54:10]}; //-1031 -8
13'h1ff7:ex4_half_denorm_frac[51:0] = {8'b0, ex4_frac[54:11]}; //-1032 -9
default :ex4_half_denorm_frac[51:0] = vfdsu_ex4_denorm_to_tiny_frac ?{10'b1,42'b0} : 52'b0; //-1045
endcase
// &CombEnd; @147
end
//here when denormal number round to add1, it will become normal number
assign ex4_denorm_potnt_norm = (vfdsu_ex4_potnt_norm[1] && ex4_frac[53]) ||
(vfdsu_ex4_potnt_norm[0] && ex4_frac[54]) ;
assign ex4_rslt_denorm = !vfdsu_ex4_result_qnan
&& !vfdsu_ex4_result_zero
&& (vfdsu_ex4_rslt_denorm && !ex4_denorm_potnt_norm);
assign ex4_denorm_result[63:0] = vfdsu_ex4_double ?
{vfdsu_ex4_result_sign,11'h0,ex4_denorm_frac[51:0]} :
vfdsu_ex4_single ? {32'hffffffff,vfdsu_ex4_result_sign,
8'h0,ex4_single_denorm_frac[51:29]} : {
48'hffffffffffff,vfdsu_ex4_result_sign,5'h0,
ex4_half_denorm_frac[51:42]};
assign ex4_half_lfn[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,5'h1e,{10{1'b1}}};
assign ex4_half_rst_qnan[63:0] = {48'hffffffffffff,vfdsu_ex4_qnan_sign, 5'h1f,1'b1, vfdsu_ex4_qnan_f[8:0]};
assign ex4_half_rst_inf[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,5'h1f,10'b0};
assign ex4_half_rst_norm[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,
ex4_expnt_rst[4:0],
ex4_frac_52[51:42]};
assign ex4_half_rst0[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,15'h0};
//ex4 overflow/underflow plus
assign ex4_rst_nor = vfdsu_ex4_result_nor;
assign ex4_of_plus = vfdsu_ex4_potnt_of &&
(|ex4_frac[54:53]) &&
ex4_rst_nor;
assign ex4_uf_plus = vfdsu_ex4_potnt_uf &&
(~|ex4_frac[54:53]) &&
ex4_rst_nor;
//ex4 overflow round result
assign ex4_result_lfn = (ex4_of_plus && vfdsu_ex4_of_rst_lfn) ||
vfdsu_ex4_result_lfn;
assign ex4_result_inf = (ex4_of_plus && !vfdsu_ex4_of_rst_lfn) ||
vfdsu_ex4_result_inf;
//Special Result Form
// result largest finity number
assign ex4_doub_lfn[63:0] = {vfdsu_ex4_result_sign,11'h7fe,{52{1'b1}}};
assign ex4_sing_lfn[63:0] = {32'hffffffff,vfdsu_ex4_result_sign,8'hfe,{23{1'b1}}};
// result 0
assign ex4_doub_rst0[63:0] = {vfdsu_ex4_result_sign,63'b0};
assign ex4_sing_rst0[63:0] = {32'hffffffff,vfdsu_ex4_result_sign,31'b0};
//result qNaN
// &Force("bus","vfdsu_ex4_qnan_f",51,0); @192
assign ex4_doub_rst_qnan[63:0] = { vfdsu_ex4_qnan_sign, 11'h7ff, 1'b1, vfdsu_ex4_qnan_f[50:0]};
assign ex4_sing_rst_qnan[63:0] = {32'hffffffff,vfdsu_ex4_qnan_sign, 8'hff, 1'b1, vfdsu_ex4_qnan_f[21:0]};
//result infinity
assign ex4_doub_rst_inf[63:0] = {vfdsu_ex4_result_sign,11'h7ff,52'b0};
assign ex4_sing_rst_inf[63:0] = {32'hffffffff,vfdsu_ex4_result_sign,8'hff,23'b0};
//result normal
// &CombBeg; @199
always @( ex4_frac[54:0])
begin
casez(ex4_frac[54:53])
2'b00 : ex4_frac_52[51:0] = ex4_frac[51:0];
2'b01 : ex4_frac_52[51:0] = ex4_frac[52:1];
2'b1? : ex4_frac_52[51:0] = ex4_frac[53:2];
default : ex4_frac_52[51:0] = 52'b0;
endcase
// &CombEnd; @206
end
assign ex4_doub_rst_norm[63:0] = {vfdsu_ex4_result_sign,
ex4_expnt_rst[10:0],
ex4_frac_52[51:0]};
assign ex4_sing_rst_norm[63:0] = {32'hffffffff,vfdsu_ex4_result_sign,
ex4_expnt_rst[7:0],
ex4_frac_52[51:29]};
assign ex4_rst_lfn[63:0] = (vfdsu_ex4_double) ? ex4_doub_lfn[63:0] :
vfdsu_ex4_single ? ex4_sing_lfn[63:0] : ex4_half_lfn[63:0];
assign ex4_rst0[63:0] = (vfdsu_ex4_double) ? ex4_doub_rst0[63:0] :
vfdsu_ex4_single ? ex4_sing_rst0[63:0] : ex4_half_rst0[63:0];
assign ex4_rst_qnan[63:0] = (vfdsu_ex4_double) ? ex4_doub_rst_qnan[63:0] :
vfdsu_ex4_single ? ex4_sing_rst_qnan[63:0]
: ex4_half_rst_qnan[63:0];
assign ex4_rst_norm[63:0] = (vfdsu_ex4_double) ? ex4_doub_rst_norm[63:0] :
vfdsu_ex4_single ? ex4_sing_rst_norm[63:0]
: ex4_half_rst_norm[63:0];
assign ex4_rst_inf[63:0] = (vfdsu_ex4_double) ? ex4_doub_rst_inf[63:0] :
vfdsu_ex4_single ? ex4_sing_rst_inf[63:0]
: ex4_half_rst_inf[63:0];
assign ex4_cor_uf = (vfdsu_ex4_uf && !ex4_denorm_potnt_norm || ex4_uf_plus)
&& vfdsu_ex4_nx;
assign ex4_cor_nx = vfdsu_ex4_nx
|| vfdsu_ex4_of
|| ex4_of_plus;
assign ex4_out_expt[4:0] = {
vfdsu_ex4_nv,
vfdsu_ex4_dz,
vfdsu_ex4_of | ex4_of_plus,
ex4_cor_uf,
ex4_cor_nx};
assign ex4_final_rst_norm = !vfdsu_ex4_result_qnan &&
!ex4_result_inf &&
!ex4_result_lfn &&
!vfdsu_ex4_result_zero &&
!ex4_rslt_denorm;
// &CombBeg; @249
always @( ex4_rst_norm[63:0]
or ex4_result_lfn
or vfdsu_ex4_result_qnan
or ex4_rst_qnan[63:0]
or ex4_rst0[63:0]
or ex4_rslt_denorm
or ex4_denorm_result[63:0]
or ex4_result_inf
or ex4_final_rst_norm
or ex4_rst_lfn[63:0]
or vfdsu_ex4_result_zero
or ex4_rst_inf[63:0])
begin
case({ex4_rslt_denorm,
vfdsu_ex4_result_qnan,
ex4_result_inf,
ex4_result_lfn,
vfdsu_ex4_result_zero,
ex4_final_rst_norm})
6'b100000 : ex4_out_result[63:0] = ex4_denorm_result[63:0];
6'b010000 : ex4_out_result[63:0] = ex4_rst_qnan[63:0];
6'b001000 : ex4_out_result[63:0] = ex4_rst_inf[63:0];
6'b000100 : ex4_out_result[63:0] = ex4_rst_lfn[63:0];
6'b000010 : ex4_out_result[63:0] = ex4_rst0[63:0];
6'b000001 : ex4_out_result[63:0] = ex4_rst_norm[63:0];
default : ex4_out_result[63:0] = 64'b0;
endcase
// &CombEnd; @264
end
// &ModuleEnd; @266
endmodule |
module ct_vfdsu_prepare(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ex1_div,
ex1_divisor,
ex1_double,
ex1_pipedown,
ex1_remainder,
ex1_scalar,
ex1_single,
ex1_sqrt,
ex1_src0,
ex1_src1,
ex1_static_rm,
forever_cpuclk,
pad_yy_icg_scan_en,
vfdsu_ex2_div,
vfdsu_ex2_double,
vfdsu_ex2_dz,
vfdsu_ex2_expnt_add0,
vfdsu_ex2_expnt_add1,
vfdsu_ex2_nv,
vfdsu_ex2_of_rm_lfn,
vfdsu_ex2_op0_norm,
vfdsu_ex2_op1_norm,
vfdsu_ex2_qnan_f,
vfdsu_ex2_qnan_sign,
vfdsu_ex2_result_inf,
vfdsu_ex2_result_qnan,
vfdsu_ex2_result_sign,
vfdsu_ex2_result_zero,
vfdsu_ex2_rm,
vfdsu_ex2_single,
vfdsu_ex2_sqrt,
vfdsu_ex2_srt_skip,
vfpu_yy_xx_dqnan,
vfpu_yy_xx_rm
);
// &Ports; @23
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ex1_div;
input ex1_double;
input ex1_pipedown;
input ex1_scalar;
input ex1_single;
input ex1_sqrt;
input [63:0] ex1_src0;
input [63:0] ex1_src1;
input [2 :0] ex1_static_rm;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input vfpu_yy_xx_dqnan;
input [2 :0] vfpu_yy_xx_rm;
output [52:0] ex1_divisor;
output [59:0] ex1_remainder;
output vfdsu_ex2_div;
output vfdsu_ex2_double;
output vfdsu_ex2_dz;
output [12:0] vfdsu_ex2_expnt_add0;
output [12:0] vfdsu_ex2_expnt_add1;
output vfdsu_ex2_nv;
output vfdsu_ex2_of_rm_lfn;
output vfdsu_ex2_op0_norm;
output vfdsu_ex2_op1_norm;
output [51:0] vfdsu_ex2_qnan_f;
output vfdsu_ex2_qnan_sign;
output vfdsu_ex2_result_inf;
output vfdsu_ex2_result_qnan;
output vfdsu_ex2_result_sign;
output vfdsu_ex2_result_zero;
output [2 :0] vfdsu_ex2_rm;
output vfdsu_ex2_single;
output vfdsu_ex2_sqrt;
output vfdsu_ex2_srt_skip;
// &Regs; @24
reg [12:0] ex1_expnt_adder_op1;
reg ex1_of_result_lfn;
reg [51:0] ex1_qnan_f;
reg ex1_qnan_sign;
reg vfdsu_ex2_div;
reg vfdsu_ex2_double;
reg vfdsu_ex2_dz;
reg [12:0] vfdsu_ex2_expnt_add0;
reg [12:0] vfdsu_ex2_expnt_add1;
reg vfdsu_ex2_nv;
reg vfdsu_ex2_of_rm_lfn;
reg vfdsu_ex2_op0_norm;
reg vfdsu_ex2_op1_norm;
reg [51:0] vfdsu_ex2_qnan_f;
reg vfdsu_ex2_qnan_sign;
reg vfdsu_ex2_result_inf;
reg vfdsu_ex2_result_qnan;
reg vfdsu_ex2_result_sign;
reg vfdsu_ex2_result_zero;
reg [2 :0] vfdsu_ex2_rm;
reg vfdsu_ex2_single;
reg vfdsu_ex2_sqrt;
reg vfdsu_ex2_srt_skip;
// &Wires; @25
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire div_sign;
wire ex1_div;
wire ex1_div_dz;
wire [52:0] ex1_div_noid_nor_srt_op0;
wire [52:0] ex1_div_noid_nor_srt_op1;
wire [52:0] ex1_div_nor_srt_op0;
wire [52:0] ex1_div_nor_srt_op1;
wire ex1_div_nv;
wire [12:0] ex1_div_op0_expnt;
wire [12:0] ex1_div_op1_expnt;
wire ex1_div_rst_inf;
wire ex1_div_rst_qnan;
wire ex1_div_rst_zero;
wire [52:0] ex1_div_srt_op0;
wire [52:0] ex1_div_srt_op1;
wire [52:0] ex1_divisor;
wire ex1_doub_expnt0_max;
wire ex1_doub_expnt0_zero;
wire ex1_doub_expnt1_max;
wire ex1_doub_expnt1_zero;
wire ex1_doub_frac0_all0;
wire ex1_doub_frac1_all0;
wire ex1_double;
wire ex1_dz;
wire ex1_expnt0_max;
wire ex1_expnt0_zero;
wire ex1_expnt1_max;
wire ex1_expnt1_zero;
wire [12:0] ex1_expnt_adder_op0;
wire ex1_frac0_all0;
wire ex1_frac0_msb;
wire ex1_frac1_all0;
wire ex1_frac1_msb;
wire ex1_half_expnt0_max;
wire ex1_half_expnt0_zero;
wire ex1_half_expnt1_max;
wire ex1_half_expnt1_zero;
wire ex1_half_frac0_all0;
wire ex1_half_frac1_all0;
wire ex1_nv;
wire ex1_op0_cnan;
wire [51:0] ex1_op0_f;
wire ex1_op0_id;
wire ex1_op0_id_nor;
wire ex1_op0_inf;
wire ex1_op0_is_qnan;
wire ex1_op0_is_snan;
wire ex1_op0_norm;
wire ex1_op0_qnan;
wire ex1_op0_sign;
wire ex1_op0_snan;
wire ex1_op0_tt_zero;
wire ex1_op0_zero;
wire ex1_op1_cnan;
wire [51:0] ex1_op1_f;
wire ex1_op1_id;
wire ex1_op1_id_nor;
wire ex1_op1_inf;
wire ex1_op1_is_qnan;
wire ex1_op1_is_snan;
wire ex1_op1_norm;
wire ex1_op1_qnan;
wire ex1_op1_sign;
wire ex1_op1_snan;
wire ex1_op1_tt_zero;
wire ex1_op1_zero;
wire [63:0] ex1_oper0;
wire [51:0] ex1_oper0_frac;
wire ex1_oper0_high_all1;
wire [12:0] ex1_oper0_id_expnt;
wire [51:0] ex1_oper0_id_frac;
wire [63:0] ex1_oper1;
wire [51:0] ex1_oper1_frac;
wire ex1_oper1_high_all1;
wire [12:0] ex1_oper1_id_expnt;
wire [51:0] ex1_oper1_id_frac;
wire ex1_pipe_clk;
wire ex1_pipe_clk_en;
wire ex1_pipedown;
wire [59:0] ex1_remainder;
wire ex1_result_inf;
wire ex1_result_qnan;
wire ex1_result_sign;
wire ex1_result_zero;
wire [2 :0] ex1_rm;
wire ex1_rst_default_qnan;
wire ex1_scalar;
wire ex1_sing_expnt0_max;
wire ex1_sing_expnt0_zero;
wire ex1_sing_expnt1_max;
wire ex1_sing_expnt1_zero;
wire ex1_sing_frac0_all0;
wire ex1_sing_frac1_all0;
wire ex1_single;
wire ex1_sqrt;
wire ex1_sqrt_expnt_odd;
wire ex1_sqrt_expnt_result_odd;
wire ex1_sqrt_nv;
wire [12:0] ex1_sqrt_op1_expnt;
wire ex1_sqrt_rst_inf;
wire ex1_sqrt_rst_qnan;
wire ex1_sqrt_rst_zero;
wire [52:0] ex1_sqrt_srt_op0;
wire [63:0] ex1_src0;
wire [63:0] ex1_src1;
wire ex1_srt_skip;
wire [2 :0] ex1_static_rm;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire [59:0] sqrt_remainder;
wire sqrt_sign;
wire vfpu_yy_xx_dqnan;
wire [2 :0] vfpu_yy_xx_rm;
//======================Operator prepare====================
//VECTOR_SIMD
assign ex1_oper0[63:0] = ex1_src0[63:0];
assign ex1_oper1[63:0] = ex1_src1[63:0];
//Sign bit prepare
assign ex1_op0_sign = ex1_double ? ex1_oper0[63] :
ex1_single ? ex1_oper0[31] : ex1_oper0[15];
assign ex1_op1_sign = ex1_double ? ex1_oper1[63] :
ex1_single ? ex1_oper1[31] : ex1_oper1[15];
assign div_sign = ex1_op0_sign ^ ex1_op1_sign;
assign sqrt_sign = ex1_op0_sign;
assign ex1_result_sign = (ex1_div)
? div_sign
: sqrt_sign;
//exponent max
assign ex1_doub_expnt0_max = &ex1_oper0[62:52];
assign ex1_sing_expnt0_max = &ex1_oper0[30:23];
assign ex1_doub_expnt1_max = &ex1_oper1[62:52];
assign ex1_sing_expnt1_max = &ex1_oper1[30:23];
assign ex1_half_expnt0_max = &ex1_oper0[14:10];
assign ex1_half_expnt1_max = &ex1_oper1[14:10];
assign ex1_expnt0_max = ex1_double ? ex1_doub_expnt0_max :
ex1_single ? ex1_sing_expnt0_max : ex1_half_expnt0_max;
assign ex1_expnt1_max = ex1_double ? ex1_doub_expnt1_max :
ex1_single ? ex1_sing_expnt1_max : ex1_half_expnt1_max;
//exponent zero
assign ex1_doub_expnt0_zero = ~|ex1_oper0[62:52];
assign ex1_sing_expnt0_zero = ~|ex1_oper0[30:23];
assign ex1_doub_expnt1_zero = ~|ex1_oper1[62:52];
assign ex1_sing_expnt1_zero = ~|ex1_oper1[30:23];
assign ex1_half_expnt0_zero = ~|ex1_oper0[14:10];
assign ex1_half_expnt1_zero = ~|ex1_oper1[14:10];
assign ex1_expnt0_zero = ex1_double ? ex1_doub_expnt0_zero :
ex1_single ? ex1_sing_expnt0_zero : ex1_half_expnt0_zero;
assign ex1_expnt1_zero = ex1_double ? ex1_doub_expnt1_zero :
ex1_single ? ex1_sing_expnt1_zero : ex1_half_expnt1_zero;
//fraction zero
assign ex1_doub_frac0_all0 = ~|ex1_oper0[51:0];
assign ex1_sing_frac0_all0 = ~|ex1_oper0[22:0];
assign ex1_doub_frac1_all0 = ~|ex1_oper1[51:0];
assign ex1_sing_frac1_all0 = ~|ex1_oper1[22:0];
assign ex1_half_frac0_all0 = ~|ex1_oper0[9:0];
assign ex1_half_frac1_all0 = ~|ex1_oper1[9:0];
assign ex1_frac0_all0 = ex1_double ? ex1_doub_frac0_all0 :
ex1_single ? ex1_sing_frac0_all0 : ex1_half_frac0_all0;
assign ex1_frac1_all0 = ex1_double ? ex1_doub_frac1_all0 :
ex1_single ? ex1_sing_frac1_all0 : ex1_half_frac1_all0;
assign ex1_frac0_msb = ex1_double ? ex1_oper0[51] :
ex1_single ? ex1_oper0[22] : ex1_oper0[9];
assign ex1_frac1_msb = ex1_double ? ex1_oper1[51] :
ex1_single ? ex1_oper1[22] : ex1_oper1[9];
assign ex1_oper0_high_all1 = ex1_single ? &ex1_oper0[63:32] : &ex1_oper0[63:16];
assign ex1_oper1_high_all1 = ex1_single ? &ex1_oper1[63:32] : &ex1_oper1[63:16];
//infinity number
assign ex1_op0_inf = ex1_expnt0_max &&
ex1_frac0_all0 &&
~ex1_op0_cnan;
assign ex1_op1_inf = ex1_expnt1_max &&
ex1_frac1_all0 &&
~ex1_op1_cnan;
//zero
assign ex1_op0_zero = ex1_expnt0_zero &&
ex1_frac0_all0 &&
~ex1_op0_cnan;
assign ex1_op1_zero = ex1_expnt1_zero &&
ex1_frac1_all0 &&
~ex1_op1_cnan;
//denormalize number
assign ex1_op0_id = ex1_expnt0_zero &&
~ex1_frac0_all0 &&
~ex1_op0_cnan;
assign ex1_op1_id = ex1_expnt1_zero &&
~ex1_frac1_all0 &&
~ex1_op1_cnan;
//assign ex1_op0_id_fm1 = vfpu_yy_xx_fm[1] &&
// vfpu_yy_xx_fm[0] &&
// ex1_op0_id;
//assign ex1_op1_id_fm1 = vfpu_yy_xx_fm[1] &&
// vfpu_yy_xx_fm[0] &&
// ex1_op1_id;
//assign ex1_op0_id_fm0 = vfpu_yy_xx_fm[1] &&
// !vfpu_yy_xx_fm[0] &&
// ex1_op0_id;
//assign ex1_op1_id_fm0 = vfpu_yy_xx_fm[1] &&
// !vfpu_yy_xx_fm[0] &&
// ex1_op1_id;
assign ex1_op0_id_nor = ex1_op0_id;
assign ex1_op1_id_nor = ex1_op1_id;
//cNaN
assign ex1_op0_cnan = ex1_scalar &&
!ex1_double &&
!ex1_oper0_high_all1;
assign ex1_op1_cnan = ex1_scalar &&
!ex1_double &&
!ex1_oper1_high_all1;
//sNaN
assign ex1_op0_snan = ex1_expnt0_max &&
~ex1_frac0_all0 &&
~ex1_frac0_msb &&
~ex1_op0_cnan;
assign ex1_op1_snan = ex1_expnt1_max &&
~ex1_frac1_all0 &&
~ex1_frac1_msb &&
~ex1_op1_cnan;
//qNaN
assign ex1_op0_qnan = (ex1_expnt0_max &&
ex1_frac0_msb) ||
ex1_op0_cnan;
assign ex1_op1_qnan = (ex1_expnt1_max &&
ex1_frac1_msb) ||
ex1_op1_cnan;
//=====================find first one=======================
// this is for the denormal number
// &Instance("ct_vfdsu_ff1","x_frac0_expnt"); @150
ct_vfdsu_ff1 x_frac0_expnt (
.fanc_shift_num (ex1_oper0_id_frac[51:0] ),
.frac_bin_val (ex1_oper0_id_expnt[12:0]),
.frac_num (ex1_oper0_frac[51:0] )
);
// &Connect(.frac_num(ex1_oper0_frac[51:0])); @151
// &Connect(.frac_bin_val(ex1_oper0_id_expnt[12:0])); @152
// &Connect(.fanc_shift_num(ex1_oper0_id_frac[51:0])); @153
// &Instance("ct_vfdsu_ff1","x_frac1_expnt"); @155
ct_vfdsu_ff1 x_frac1_expnt (
.fanc_shift_num (ex1_oper1_id_frac[51:0] ),
.frac_bin_val (ex1_oper1_id_expnt[12:0]),
.frac_num (ex1_oper1_frac[51:0] )
);
// &Connect(.frac_num(ex1_oper1_frac[51:0])); @156
// &Connect(.frac_bin_val(ex1_oper1_id_expnt[12:0])); @157
// &Connect(.fanc_shift_num(ex1_oper1_id_frac[51:0])); @158
assign ex1_oper0_frac[51:0] = ex1_double ? ex1_oper0[51:0] :
ex1_single ? {ex1_oper0[22:0],29'b0}
: {ex1_oper0[9:0],42'b0};
assign ex1_oper1_frac[51:0] = ex1_double ? ex1_oper1[51:0] :
ex1_single ? {ex1_oper1[22:0],29'b0}
: {ex1_oper1[9:0],42'b0};
//=====================exponent add=========================
//exponent number 0
assign ex1_div_op0_expnt[12:0] = ex1_double ? {2'b0,ex1_oper0[62:52]} :
ex1_single ? {5'b0,ex1_oper0[30:23]}
: {8'b0,ex1_oper0[14:10]};
assign ex1_expnt_adder_op0[12:0] = ex1_op0_id_nor ? ex1_oper0_id_expnt[12:0]
: ex1_div_op0_expnt[12:0];
//exponent number 1
assign ex1_div_op1_expnt[12:0] = ex1_double ? {2'b0,ex1_oper1[62:52]} :
ex1_single ? {5'b0,ex1_oper1[30:23]}
: {8'b0,ex1_oper1[14:10]};
assign ex1_sqrt_op1_expnt[12:0] = ex1_double ? {3'b0,{10{1'b1}}} : //'d1023
ex1_single ? {6'b0,{7{1'b1}}} //'d127
: {9'b0,{4{1'b1}}}; //'d15
// &CombBeg; @180
always @( ex1_oper1_id_expnt[12:0]
or ex1_div
or ex1_op1_id_nor
or ex1_sqrt_op1_expnt[12:0]
or ex1_sqrt
or ex1_div_op1_expnt[12:0])
begin
case({ex1_div,ex1_sqrt})
2'b10: ex1_expnt_adder_op1[12:0] = ex1_op1_id_nor ? ex1_oper1_id_expnt[12:0]
: ex1_div_op1_expnt[12:0];
2'b01: ex1_expnt_adder_op1[12:0] = ex1_sqrt_op1_expnt[12:0];
default: ex1_expnt_adder_op1[12:0] = 13'b0;
endcase
// &CombEnd; @187
end
//expnt0 sub expnt1
assign ex1_sqrt_expnt_result_odd = ex1_expnt_adder_op0[0] ^ ex1_expnt_adder_op1[0];
//======================EX1 expt detect=====================
//ex1_id_detect
//any opration is zero
// no input denormalize exception anymore
//
//ex1_nv_detect
//div_nv
// 1.any operation is sNaN
// 2.0/0(include DN flush to zero)
// 3.inf/inf
//sqrt_nv
// 1.any operation is sNaN
// 2.operation sign is 1 && operation is not zero/qNaN
assign ex1_nv = ex1_div && ex1_div_nv ||
ex1_sqrt && ex1_sqrt_nv;
//ex1_div_nv
assign ex1_div_nv = ex1_op0_snan ||
ex1_op1_snan ||
(ex1_op0_tt_zero && ex1_op1_tt_zero)||
(ex1_op0_inf && ex1_op1_inf);
assign ex1_op0_tt_zero = ex1_op0_zero;
assign ex1_op1_tt_zero = ex1_op1_zero;
//ex1_sqrt_nv
assign ex1_sqrt_nv = ex1_op0_snan ||
ex1_op0_sign &&
(ex1_op0_norm ||
ex1_op0_inf );
assign ex1_op0_norm = !ex1_expnt0_zero && !ex1_expnt0_max && !ex1_op0_cnan || ex1_op0_id_nor ;
assign ex1_op1_norm = !ex1_expnt1_zero && !ex1_expnt1_max && !ex1_op1_cnan || ex1_op1_id_nor;
//ex1_of_detect
//div_of
// 1.only detect id overflow case
//assign ex1_of = ex1_div && ex1_div_of;
//assign ex1_div_of = ex1_op1_id_fm1 &&
// ex1_op0_norm &&
// ex1_div_id_of;
//
////ex1_uf_detect
////div_uf
//// 1.only detect id underflow case
//assign ex1_uf = ex1_div && ex1_div_uf;
//assign ex1_div_uf = ex1_op0_id &&
// ex1_op1_norm &&
// ex1_div_id_uf;
//ex1_dz_detect
//div_dz
// 1.op0 is normal && op1 zero
assign ex1_dz = ex1_div && ex1_div_dz;
assign ex1_div_dz = ex1_op1_tt_zero && ex1_op0_norm;
//===================sqrt exponent prepare==================
//sqrt exponent prepare
//afert E sub, div E by 2
//assign ex1_sqrt_expnt_result[12:0] = {ex1_expnt_result[12],
// ex1_expnt_result[12:1]};
//ex1_sqrt_expnt_odd
//fraction will shift left by 1
assign ex1_sqrt_expnt_odd = ex1_sqrt_expnt_result_odd;
//===================special cal result=====================
//ex1 result is zero
//div_zero
// 1.op0 is zero && op1 is normal
// 2.op0 is zero/normal && op1 is inf
//sqrt_zero
// 1.op0 is zero
assign ex1_result_zero = ex1_div_rst_zero && ex1_div ||
ex1_sqrt_rst_zero && ex1_sqrt;
assign ex1_div_rst_zero = (ex1_op0_tt_zero && ex1_op1_norm ) ||
(!ex1_expnt0_max && !ex1_op0_cnan && ex1_op1_inf);
assign ex1_sqrt_rst_zero = ex1_op0_tt_zero;
//ex1 result is qNaN
//ex1_nv
//div_qnan
// 1.op0 is qnan || op1 is qnan
//sqrt_qnan
// 1.op0 is qnan
assign ex1_result_qnan = ex1_div_rst_qnan && ex1_div ||
ex1_sqrt_rst_qnan && ex1_sqrt ||
ex1_nv;
assign ex1_div_rst_qnan = ex1_op0_qnan ||
ex1_op1_qnan;
assign ex1_sqrt_rst_qnan = ex1_op0_qnan;
//ex1_rst_default_qnan
//0/0, inf/inf, sqrt negative should get default qNaN
assign ex1_rst_default_qnan = (ex1_div && ex1_op0_zero && ex1_op1_zero) ||
(ex1_div && ex1_op0_inf && ex1_op1_inf) ||
(ex1_sqrt&& ex1_op0_sign && (ex1_op0_norm || ex1_op0_inf));
//ex1 result is inf
//ex1_dz
//
//div_inf
// 1.op0 is inf && op1 is normal/zero
//sqrt_inf
// 1.op0 is inf
assign ex1_result_inf = ex1_div_rst_inf && ex1_div ||
ex1_sqrt_rst_inf && ex1_sqrt ||
ex1_dz ;
assign ex1_div_rst_inf = ex1_op0_inf && !ex1_expnt1_max && !ex1_op1_cnan;
assign ex1_sqrt_rst_inf = ex1_op0_inf && !ex1_op0_sign;
//ex1 result is lfn
//ex1_of && round result toward not inc 1
assign ex1_rm[2:0] = ((ex1_static_rm[2:0] == 3'b111)|| !ex1_scalar)
? vfpu_yy_xx_rm[2:0]
: ex1_static_rm[2:0];
//RNE : Always inc 1 because round to nearest of 1.111...11
//RTZ : Always not inc 1
//RUP : Always not inc 1 when posetive
//RDN : Always not inc 1 when negative
//RMM : Always inc 1 because round to max magnitude
// &CombBeg; @308
always @( ex1_rm[2:0]
or ex1_result_sign)
begin
case(ex1_rm[2:0])
3'b000 : ex1_of_result_lfn = 1'b0;
3'b001 : ex1_of_result_lfn = 1'b1;
3'b010 : ex1_of_result_lfn = !ex1_result_sign;
3'b011 : ex1_of_result_lfn = ex1_result_sign;
3'b100 : ex1_of_result_lfn = 1'b0;
default: ex1_of_result_lfn = 1'b0;
endcase
// &CombEnd; @317
end
//EX1 Remainder
//div : 1/8 <= x < 1/4
//sqrt : 1/16 <= x < 1/4
assign ex1_remainder[59:0] = {60{ex1_div }} & {5'b0,ex1_div_srt_op0[52:0],2'b0} |
{60{ex1_sqrt}} & sqrt_remainder[59:0];
//EX1 Divisor
//1/2 <= y < 1
assign ex1_divisor[52:0] = ex1_div_srt_op1[52:0];
//ex1_div_srt_op0
assign ex1_div_srt_op0[52:0] = ex1_div_nor_srt_op0[52:0];
//ex1_div_srt_op1
assign ex1_div_srt_op1[52:0] = ex1_div_nor_srt_op1[52:0];
//ex1_div_nor_srt_op0
assign ex1_div_noid_nor_srt_op0[52:0] = ex1_double ? {1'b1,ex1_oper0[51:0]} :
ex1_single ? {1'b1,ex1_oper0[22:0],29'b0}
: {1'b1,ex1_oper0[9:0],42'b0};
assign ex1_div_noid_nor_srt_op1[52:0] = ex1_double ? {1'b1,ex1_oper1[51:0]} :
ex1_single ? {1'b1,ex1_oper1[22:0],29'b0}
: {1'b1,ex1_oper1[9:0],42'b0};
assign ex1_div_nor_srt_op0[52:0] = ex1_op0_id_nor ? {ex1_oper0_id_frac[51:0],1'b0}
: ex1_div_noid_nor_srt_op0[52:0];
//ex1_div_nor_srt_op1
assign ex1_div_nor_srt_op1[52:0] = ex1_op1_id_nor ? {ex1_oper1_id_frac[51:0],1'b0}
: ex1_div_noid_nor_srt_op1[52:0];
//sqrt_remainder
assign sqrt_remainder[59:0] = (ex1_sqrt_expnt_odd)
? {5'b0,ex1_sqrt_srt_op0[52:0],2'b0}
: {6'b0,ex1_sqrt_srt_op0[52:0],1'b0};
//ex1_sqrt_srt_op0
assign ex1_sqrt_srt_op0[52:0] = ex1_div_srt_op0[52:0];
//Default_qnan/Standard_qnan Select
assign ex1_op0_is_snan = ex1_op0_snan;
assign ex1_op1_is_snan = ex1_op1_snan && ex1_div;
assign ex1_op0_is_qnan = ex1_op0_qnan;
assign ex1_op1_is_qnan = ex1_op1_qnan && ex1_div;
assign ex1_op0_f[51:0] = (ex1_op0_cnan) ? 52'b0: ex1_oper0[51:0];
assign ex1_op1_f[51:0] = (ex1_op1_cnan) ? 52'b0: ex1_oper1[51:0];
// &CombBeg; @359
always @( ex1_op0_is_snan
or ex1_op0_is_qnan
or ex1_op0_f[51:0]
or ex1_rst_default_qnan
or ex1_op1_f[51:0]
or vfpu_yy_xx_dqnan
or ex1_op1_is_snan
or ex1_op1_is_qnan)
begin
if(ex1_rst_default_qnan)
ex1_qnan_f[51:0] = {1'b1, 51'b0};
else if(ex1_op0_is_snan && vfpu_yy_xx_dqnan)
ex1_qnan_f[51:0] = ex1_op0_f[51:0];
else if(ex1_op1_is_snan && vfpu_yy_xx_dqnan)
ex1_qnan_f[51:0] = ex1_op1_f[51:0];
else if(ex1_op0_is_qnan && vfpu_yy_xx_dqnan)
ex1_qnan_f[51:0] = ex1_op0_f[51:0];
else if(ex1_op1_is_qnan && vfpu_yy_xx_dqnan)
ex1_qnan_f[51:0] = ex1_op1_f[51:0];
else
ex1_qnan_f[51:0] = {1'b1, 51'b0};
// &CombEnd; @372
end
// &CombBeg; @374
always @( ex1_op0_is_snan
or ex1_op0_cnan
or ex1_op0_is_qnan
or ex1_op1_sign
or ex1_op0_sign
or ex1_rst_default_qnan
or vfpu_yy_xx_dqnan
or ex1_op1_cnan
or ex1_op1_is_snan
or ex1_op1_is_qnan)
begin
if(ex1_rst_default_qnan)
ex1_qnan_sign = 1'b0;
else if(ex1_op0_is_snan && vfpu_yy_xx_dqnan)
ex1_qnan_sign = ex1_op0_sign;
else if(ex1_op1_is_snan && vfpu_yy_xx_dqnan)
ex1_qnan_sign = ex1_op1_sign;
else if(ex1_op0_is_qnan && vfpu_yy_xx_dqnan)
ex1_qnan_sign = ex1_op0_sign && !ex1_op0_cnan;
else if(ex1_op1_is_qnan && vfpu_yy_xx_dqnan)
ex1_qnan_sign = ex1_op1_sign && !ex1_op1_cnan;
else
ex1_qnan_sign = 1'b0;
// &CombEnd; @387
end
//========================Pipe to EX2=======================
//exponent register cal result
//assign ex1_srt_expnt_rst[12:0] = (ex1_sqrt)
// ? ex1_sqrt_expnt_result[12:0]
// : ex1_expnt_result[12:0];
//Special result should skip SRT logic
assign ex1_srt_skip = ex1_result_zero ||
ex1_result_qnan ||
ex1_result_inf;
//gate clk
// &Instance("gated_clk_cell","x_ex1_pipe_clk"); @400
gated_clk_cell x_ex1_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_pipe_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @401
// .clk_out (ex1_pipe_clk),//Out Clock @402
// .external_en (1'b0), @403
// .global_en (cp0_yy_clk_en), @404
// .local_en (ex1_pipe_clk_en),//Local Condition @405
// .module_en (cp0_vfpu_icg_en) @406
// ); @407
assign ex1_pipe_clk_en = ex1_pipedown;
always @(posedge ex1_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
vfdsu_ex2_result_zero <= 1'b0;
vfdsu_ex2_result_qnan <= 1'b0;
vfdsu_ex2_result_inf <= 1'b0;
vfdsu_ex2_result_sign <= 1'b0;
vfdsu_ex2_op0_norm <= 1'b0;
vfdsu_ex2_op1_norm <= 1'b0;
vfdsu_ex2_expnt_add0[12:0] <= 13'b0;
vfdsu_ex2_expnt_add1[12:0] <= 13'b0;
vfdsu_ex2_nv <= 1'b0;
vfdsu_ex2_dz <= 1'b0;
vfdsu_ex2_srt_skip <= 1'b0;
vfdsu_ex2_of_rm_lfn <= 1'b0;
vfdsu_ex2_qnan_sign <= 1'b0;
vfdsu_ex2_qnan_f[51:0] <= 52'b0;
vfdsu_ex2_rm[2:0] <= 3'b0;
vfdsu_ex2_div <= 1'b0;
vfdsu_ex2_sqrt <= 1'b0;
vfdsu_ex2_double <= 1'b0;
vfdsu_ex2_single <= 1'b0;
end
else if(ex1_pipedown)
begin
vfdsu_ex2_result_zero <= ex1_result_zero;
vfdsu_ex2_result_qnan <= ex1_result_qnan;
vfdsu_ex2_result_inf <= ex1_result_inf;
vfdsu_ex2_result_sign <= ex1_result_sign;
vfdsu_ex2_op0_norm <= ex1_op0_norm;
vfdsu_ex2_op1_norm <= ex1_op1_norm;
vfdsu_ex2_expnt_add0[12:0] <= ex1_expnt_adder_op0[12:0];
vfdsu_ex2_expnt_add1[12:0] <= ex1_expnt_adder_op1[12:0];
vfdsu_ex2_nv <= ex1_nv;
vfdsu_ex2_dz <= ex1_dz;
vfdsu_ex2_srt_skip <= ex1_srt_skip;
vfdsu_ex2_of_rm_lfn <= ex1_of_result_lfn;
vfdsu_ex2_qnan_sign <= ex1_qnan_sign;
vfdsu_ex2_qnan_f[51:0] <= ex1_qnan_f[51:0];
vfdsu_ex2_rm[2:0] <= ex1_rm[2:0];
vfdsu_ex2_div <= ex1_div;
vfdsu_ex2_sqrt <= ex1_sqrt;
vfdsu_ex2_double <= ex1_double;
vfdsu_ex2_single <= ex1_single;
end
else
begin
vfdsu_ex2_result_zero <= vfdsu_ex2_result_zero;
vfdsu_ex2_result_qnan <= vfdsu_ex2_result_qnan;
vfdsu_ex2_result_inf <= vfdsu_ex2_result_inf;
vfdsu_ex2_result_sign <= vfdsu_ex2_result_sign;
vfdsu_ex2_op0_norm <= vfdsu_ex2_op0_norm;
vfdsu_ex2_op1_norm <= vfdsu_ex2_op1_norm;
vfdsu_ex2_expnt_add0[12:0] <= vfdsu_ex2_expnt_add0[12:0];
vfdsu_ex2_expnt_add1[12:0] <= vfdsu_ex2_expnt_add1[12:0];
vfdsu_ex2_nv <= vfdsu_ex2_nv;
vfdsu_ex2_dz <= vfdsu_ex2_dz;
vfdsu_ex2_srt_skip <= vfdsu_ex2_srt_skip;
vfdsu_ex2_of_rm_lfn <= vfdsu_ex2_of_rm_lfn;
vfdsu_ex2_qnan_sign <= vfdsu_ex2_qnan_sign;
vfdsu_ex2_qnan_f[51:0] <= vfdsu_ex2_qnan_f[51:0];
vfdsu_ex2_rm[2:0] <= vfdsu_ex2_rm[2:0];
vfdsu_ex2_div <= vfdsu_ex2_div;
vfdsu_ex2_sqrt <= vfdsu_ex2_sqrt;
vfdsu_ex2_double <= vfdsu_ex2_double;
vfdsu_ex2_single <= vfdsu_ex2_single;
end
end
// &Force("output","vfdsu_ex2_op0_norm"); @480
// &Force("output","vfdsu_ex2_op1_norm"); @481
// &Force("output","vfdsu_ex2_dz"); @482
// &Force("output","vfdsu_ex2_nv"); @483
// &Force("output","vfdsu_ex2_srt_skip"); @484
// &Force("output","vfdsu_ex2_of_rm_lfn"); @485
// &Force("output","vfdsu_ex2_result_inf"); @486
// &Force("output","vfdsu_ex2_result_qnan"); @487
// &Force("output","vfdsu_ex2_result_zero"); @488
// //&Force("output","vfdsu_ex2_expnt_rst"); @489
// &Force("output","vfdsu_ex2_result_sign"); @490
// &Force("output","vfdsu_ex2_qnan_f"); @491
// &Force("output","vfdsu_ex2_qnan_sign"); @492
// &Force("output","vfdsu_ex2_rm"); @493
// &Force("output","vfdsu_ex2_div"); @494
// &Force("output","vfdsu_ex2_sqrt"); @495
// &Force("output","vfdsu_ex2_double"); @496
// &Force("output","vfdsu_ex2_single"); @497
// &Force("output","vfdsu_ex2_expnt_add0"); @498
// &Force("output","vfdsu_ex2_expnt_add1"); @499
// &ModuleEnd; @501
endmodule |
module ct_vfdsu_double(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ex1_div,
ex1_double,
ex1_pipedown,
ex1_scalar,
ex1_single,
ex1_sqrt,
ex1_src0,
ex1_src1,
ex1_static_rm,
ex2_pipedown,
ex2_srt_first_round,
ex3_pipedown,
ex4_out_expt,
ex4_out_result,
forever_cpuclk,
pad_yy_icg_scan_en,
srt_ctrl_rem_zero,
srt_ctrl_skip_srt,
srt_secd_round,
srt_sm_on,
vfpu_yy_xx_dqnan,
vfpu_yy_xx_rm
);
// &Ports; @24
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ex1_div;
input ex1_double;
input ex1_pipedown;
input ex1_scalar;
input ex1_single;
input ex1_sqrt;
input [63:0] ex1_src0;
input [63:0] ex1_src1;
input [2 :0] ex1_static_rm;
input ex2_pipedown;
input ex2_srt_first_round;
input ex3_pipedown;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input srt_secd_round;
input srt_sm_on;
input vfpu_yy_xx_dqnan;
input [2 :0] vfpu_yy_xx_rm;
output [4 :0] ex4_out_expt;
output [63:0] ex4_out_result;
output srt_ctrl_rem_zero;
output srt_ctrl_skip_srt;
// &Regs; @25
// &Wires; @26
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ex1_div;
wire [52:0] ex1_divisor;
wire ex1_double;
wire ex1_pipedown;
wire [59:0] ex1_remainder;
wire ex1_scalar;
wire ex1_single;
wire ex1_sqrt;
wire [63:0] ex1_src0;
wire [63:0] ex1_src1;
wire [2 :0] ex1_static_rm;
wire ex2_pipedown;
wire ex2_srt_first_round;
wire ex3_pipedown;
wire [4 :0] ex4_out_expt;
wire [63:0] ex4_out_result;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire srt_ctrl_rem_zero;
wire srt_ctrl_skip_srt;
wire srt_secd_round;
wire srt_sm_on;
wire [57:0] total_qt_rt_58;
wire vfdsu_ex2_div;
wire vfdsu_ex2_double;
wire vfdsu_ex2_dz;
wire [12:0] vfdsu_ex2_expnt_add0;
wire [12:0] vfdsu_ex2_expnt_add1;
wire vfdsu_ex2_nv;
wire vfdsu_ex2_of_rm_lfn;
wire vfdsu_ex2_op0_norm;
wire vfdsu_ex2_op1_norm;
wire [51:0] vfdsu_ex2_qnan_f;
wire vfdsu_ex2_qnan_sign;
wire vfdsu_ex2_result_inf;
wire vfdsu_ex2_result_qnan;
wire vfdsu_ex2_result_sign;
wire vfdsu_ex2_result_zero;
wire [2 :0] vfdsu_ex2_rm;
wire vfdsu_ex2_single;
wire vfdsu_ex2_sqrt;
wire vfdsu_ex2_srt_skip;
wire [12:0] vfdsu_ex3_doub_expnt_rst;
wire vfdsu_ex3_double;
wire vfdsu_ex3_dz;
wire [12:0] vfdsu_ex3_half_expnt_rst;
wire vfdsu_ex3_id_srt_skip;
wire vfdsu_ex3_nv;
wire vfdsu_ex3_of;
wire vfdsu_ex3_potnt_of;
wire vfdsu_ex3_potnt_uf;
wire [51:0] vfdsu_ex3_qnan_f;
wire vfdsu_ex3_qnan_sign;
wire vfdsu_ex3_rem_sign;
wire vfdsu_ex3_rem_zero;
wire [52:0] vfdsu_ex3_result_denorm_round_add_num;
wire vfdsu_ex3_result_inf;
wire vfdsu_ex3_result_lfn;
wire vfdsu_ex3_result_qnan;
wire vfdsu_ex3_result_sign;
wire vfdsu_ex3_result_zero;
wire [2 :0] vfdsu_ex3_rm;
wire vfdsu_ex3_rslt_denorm;
wire [8 :0] vfdsu_ex3_sing_expnt_rst;
wire vfdsu_ex3_single;
wire vfdsu_ex3_uf;
wire vfdsu_ex4_denorm_to_tiny_frac;
wire vfdsu_ex4_double;
wire vfdsu_ex4_dz;
wire [12:0] vfdsu_ex4_expnt_rst;
wire [54:0] vfdsu_ex4_frac;
wire vfdsu_ex4_nv;
wire vfdsu_ex4_nx;
wire vfdsu_ex4_of;
wire vfdsu_ex4_of_rst_lfn;
wire [1 :0] vfdsu_ex4_potnt_norm;
wire vfdsu_ex4_potnt_of;
wire vfdsu_ex4_potnt_uf;
wire [51:0] vfdsu_ex4_qnan_f;
wire vfdsu_ex4_qnan_sign;
wire vfdsu_ex4_result_inf;
wire vfdsu_ex4_result_lfn;
wire vfdsu_ex4_result_nor;
wire vfdsu_ex4_result_qnan;
wire vfdsu_ex4_result_sign;
wire vfdsu_ex4_result_zero;
wire vfdsu_ex4_rslt_denorm;
wire vfdsu_ex4_single;
wire vfdsu_ex4_uf;
wire vfpu_yy_xx_dqnan;
wire [2 :0] vfpu_yy_xx_rm;
// &Instance("ct_vfdsu_prepare"); @28
ct_vfdsu_prepare x_ct_vfdsu_prepare (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ex1_div (ex1_div ),
.ex1_divisor (ex1_divisor ),
.ex1_double (ex1_double ),
.ex1_pipedown (ex1_pipedown ),
.ex1_remainder (ex1_remainder ),
.ex1_scalar (ex1_scalar ),
.ex1_single (ex1_single ),
.ex1_sqrt (ex1_sqrt ),
.ex1_src0 (ex1_src0 ),
.ex1_src1 (ex1_src1 ),
.ex1_static_rm (ex1_static_rm ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfdsu_ex2_div (vfdsu_ex2_div ),
.vfdsu_ex2_double (vfdsu_ex2_double ),
.vfdsu_ex2_dz (vfdsu_ex2_dz ),
.vfdsu_ex2_expnt_add0 (vfdsu_ex2_expnt_add0 ),
.vfdsu_ex2_expnt_add1 (vfdsu_ex2_expnt_add1 ),
.vfdsu_ex2_nv (vfdsu_ex2_nv ),
.vfdsu_ex2_of_rm_lfn (vfdsu_ex2_of_rm_lfn ),
.vfdsu_ex2_op0_norm (vfdsu_ex2_op0_norm ),
.vfdsu_ex2_op1_norm (vfdsu_ex2_op1_norm ),
.vfdsu_ex2_qnan_f (vfdsu_ex2_qnan_f ),
.vfdsu_ex2_qnan_sign (vfdsu_ex2_qnan_sign ),
.vfdsu_ex2_result_inf (vfdsu_ex2_result_inf ),
.vfdsu_ex2_result_qnan (vfdsu_ex2_result_qnan),
.vfdsu_ex2_result_sign (vfdsu_ex2_result_sign),
.vfdsu_ex2_result_zero (vfdsu_ex2_result_zero),
.vfdsu_ex2_rm (vfdsu_ex2_rm ),
.vfdsu_ex2_single (vfdsu_ex2_single ),
.vfdsu_ex2_sqrt (vfdsu_ex2_sqrt ),
.vfdsu_ex2_srt_skip (vfdsu_ex2_srt_skip ),
.vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan ),
.vfpu_yy_xx_rm (vfpu_yy_xx_rm )
);
// &Instance("ct_vfdsu_srt"); @29
ct_vfdsu_srt x_ct_vfdsu_srt (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ex1_div (ex1_div ),
.ex1_divisor (ex1_divisor ),
.ex1_pipedown (ex1_pipedown ),
.ex1_remainder (ex1_remainder ),
.ex1_sqrt (ex1_sqrt ),
.ex2_pipedown (ex2_pipedown ),
.ex2_srt_first_round (ex2_srt_first_round ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.srt_ctrl_rem_zero (srt_ctrl_rem_zero ),
.srt_ctrl_skip_srt (srt_ctrl_skip_srt ),
.srt_secd_round (srt_secd_round ),
.srt_sm_on (srt_sm_on ),
.total_qt_rt_58 (total_qt_rt_58 ),
.vfdsu_ex2_div (vfdsu_ex2_div ),
.vfdsu_ex2_double (vfdsu_ex2_double ),
.vfdsu_ex2_dz (vfdsu_ex2_dz ),
.vfdsu_ex2_expnt_add0 (vfdsu_ex2_expnt_add0 ),
.vfdsu_ex2_expnt_add1 (vfdsu_ex2_expnt_add1 ),
.vfdsu_ex2_nv (vfdsu_ex2_nv ),
.vfdsu_ex2_of_rm_lfn (vfdsu_ex2_of_rm_lfn ),
.vfdsu_ex2_op0_norm (vfdsu_ex2_op0_norm ),
.vfdsu_ex2_op1_norm (vfdsu_ex2_op1_norm ),
.vfdsu_ex2_qnan_f (vfdsu_ex2_qnan_f ),
.vfdsu_ex2_qnan_sign (vfdsu_ex2_qnan_sign ),
.vfdsu_ex2_result_inf (vfdsu_ex2_result_inf ),
.vfdsu_ex2_result_qnan (vfdsu_ex2_result_qnan ),
.vfdsu_ex2_result_sign (vfdsu_ex2_result_sign ),
.vfdsu_ex2_result_zero (vfdsu_ex2_result_zero ),
.vfdsu_ex2_rm (vfdsu_ex2_rm ),
.vfdsu_ex2_single (vfdsu_ex2_single ),
.vfdsu_ex2_sqrt (vfdsu_ex2_sqrt ),
.vfdsu_ex2_srt_skip (vfdsu_ex2_srt_skip ),
.vfdsu_ex3_doub_expnt_rst (vfdsu_ex3_doub_expnt_rst ),
.vfdsu_ex3_double (vfdsu_ex3_double ),
.vfdsu_ex3_dz (vfdsu_ex3_dz ),
.vfdsu_ex3_half_expnt_rst (vfdsu_ex3_half_expnt_rst ),
.vfdsu_ex3_id_srt_skip (vfdsu_ex3_id_srt_skip ),
.vfdsu_ex3_nv (vfdsu_ex3_nv ),
.vfdsu_ex3_of (vfdsu_ex3_of ),
.vfdsu_ex3_potnt_of (vfdsu_ex3_potnt_of ),
.vfdsu_ex3_potnt_uf (vfdsu_ex3_potnt_uf ),
.vfdsu_ex3_qnan_f (vfdsu_ex3_qnan_f ),
.vfdsu_ex3_qnan_sign (vfdsu_ex3_qnan_sign ),
.vfdsu_ex3_rem_sign (vfdsu_ex3_rem_sign ),
.vfdsu_ex3_rem_zero (vfdsu_ex3_rem_zero ),
.vfdsu_ex3_result_denorm_round_add_num (vfdsu_ex3_result_denorm_round_add_num),
.vfdsu_ex3_result_inf (vfdsu_ex3_result_inf ),
.vfdsu_ex3_result_lfn (vfdsu_ex3_result_lfn ),
.vfdsu_ex3_result_qnan (vfdsu_ex3_result_qnan ),
.vfdsu_ex3_result_sign (vfdsu_ex3_result_sign ),
.vfdsu_ex3_result_zero (vfdsu_ex3_result_zero ),
.vfdsu_ex3_rm (vfdsu_ex3_rm ),
.vfdsu_ex3_rslt_denorm (vfdsu_ex3_rslt_denorm ),
.vfdsu_ex3_sing_expnt_rst (vfdsu_ex3_sing_expnt_rst ),
.vfdsu_ex3_single (vfdsu_ex3_single ),
.vfdsu_ex3_uf (vfdsu_ex3_uf )
);
// &Instance("ct_vfdsu_round"); @30
ct_vfdsu_round x_ct_vfdsu_round (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ex3_pipedown (ex3_pipedown ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.total_qt_rt_58 (total_qt_rt_58 ),
.vfdsu_ex2_of_rm_lfn (vfdsu_ex2_of_rm_lfn ),
.vfdsu_ex3_doub_expnt_rst (vfdsu_ex3_doub_expnt_rst ),
.vfdsu_ex3_double (vfdsu_ex3_double ),
.vfdsu_ex3_dz (vfdsu_ex3_dz ),
.vfdsu_ex3_half_expnt_rst (vfdsu_ex3_half_expnt_rst ),
.vfdsu_ex3_id_srt_skip (vfdsu_ex3_id_srt_skip ),
.vfdsu_ex3_nv (vfdsu_ex3_nv ),
.vfdsu_ex3_of (vfdsu_ex3_of ),
.vfdsu_ex3_potnt_of (vfdsu_ex3_potnt_of ),
.vfdsu_ex3_potnt_uf (vfdsu_ex3_potnt_uf ),
.vfdsu_ex3_qnan_f (vfdsu_ex3_qnan_f ),
.vfdsu_ex3_qnan_sign (vfdsu_ex3_qnan_sign ),
.vfdsu_ex3_rem_sign (vfdsu_ex3_rem_sign ),
.vfdsu_ex3_rem_zero (vfdsu_ex3_rem_zero ),
.vfdsu_ex3_result_denorm_round_add_num (vfdsu_ex3_result_denorm_round_add_num),
.vfdsu_ex3_result_inf (vfdsu_ex3_result_inf ),
.vfdsu_ex3_result_lfn (vfdsu_ex3_result_lfn ),
.vfdsu_ex3_result_qnan (vfdsu_ex3_result_qnan ),
.vfdsu_ex3_result_sign (vfdsu_ex3_result_sign ),
.vfdsu_ex3_result_zero (vfdsu_ex3_result_zero ),
.vfdsu_ex3_rm (vfdsu_ex3_rm ),
.vfdsu_ex3_rslt_denorm (vfdsu_ex3_rslt_denorm ),
.vfdsu_ex3_sing_expnt_rst (vfdsu_ex3_sing_expnt_rst ),
.vfdsu_ex3_single (vfdsu_ex3_single ),
.vfdsu_ex3_uf (vfdsu_ex3_uf ),
.vfdsu_ex4_denorm_to_tiny_frac (vfdsu_ex4_denorm_to_tiny_frac ),
.vfdsu_ex4_double (vfdsu_ex4_double ),
.vfdsu_ex4_dz (vfdsu_ex4_dz ),
.vfdsu_ex4_expnt_rst (vfdsu_ex4_expnt_rst ),
.vfdsu_ex4_frac (vfdsu_ex4_frac ),
.vfdsu_ex4_nv (vfdsu_ex4_nv ),
.vfdsu_ex4_nx (vfdsu_ex4_nx ),
.vfdsu_ex4_of (vfdsu_ex4_of ),
.vfdsu_ex4_of_rst_lfn (vfdsu_ex4_of_rst_lfn ),
.vfdsu_ex4_potnt_norm (vfdsu_ex4_potnt_norm ),
.vfdsu_ex4_potnt_of (vfdsu_ex4_potnt_of ),
.vfdsu_ex4_potnt_uf (vfdsu_ex4_potnt_uf ),
.vfdsu_ex4_qnan_f (vfdsu_ex4_qnan_f ),
.vfdsu_ex4_qnan_sign (vfdsu_ex4_qnan_sign ),
.vfdsu_ex4_result_inf (vfdsu_ex4_result_inf ),
.vfdsu_ex4_result_lfn (vfdsu_ex4_result_lfn ),
.vfdsu_ex4_result_nor (vfdsu_ex4_result_nor ),
.vfdsu_ex4_result_qnan (vfdsu_ex4_result_qnan ),
.vfdsu_ex4_result_sign (vfdsu_ex4_result_sign ),
.vfdsu_ex4_result_zero (vfdsu_ex4_result_zero ),
.vfdsu_ex4_rslt_denorm (vfdsu_ex4_rslt_denorm ),
.vfdsu_ex4_single (vfdsu_ex4_single ),
.vfdsu_ex4_uf (vfdsu_ex4_uf )
);
// &Instance("ct_vfdsu_pack"); @31
ct_vfdsu_pack x_ct_vfdsu_pack (
.ex4_out_expt (ex4_out_expt ),
.ex4_out_result (ex4_out_result ),
.vfdsu_ex4_denorm_to_tiny_frac (vfdsu_ex4_denorm_to_tiny_frac),
.vfdsu_ex4_double (vfdsu_ex4_double ),
.vfdsu_ex4_dz (vfdsu_ex4_dz ),
.vfdsu_ex4_expnt_rst (vfdsu_ex4_expnt_rst ),
.vfdsu_ex4_frac (vfdsu_ex4_frac ),
.vfdsu_ex4_nv (vfdsu_ex4_nv ),
.vfdsu_ex4_nx (vfdsu_ex4_nx ),
.vfdsu_ex4_of (vfdsu_ex4_of ),
.vfdsu_ex4_of_rst_lfn (vfdsu_ex4_of_rst_lfn ),
.vfdsu_ex4_potnt_norm (vfdsu_ex4_potnt_norm ),
.vfdsu_ex4_potnt_of (vfdsu_ex4_potnt_of ),
.vfdsu_ex4_potnt_uf (vfdsu_ex4_potnt_uf ),
.vfdsu_ex4_qnan_f (vfdsu_ex4_qnan_f ),
.vfdsu_ex4_qnan_sign (vfdsu_ex4_qnan_sign ),
.vfdsu_ex4_result_inf (vfdsu_ex4_result_inf ),
.vfdsu_ex4_result_lfn (vfdsu_ex4_result_lfn ),
.vfdsu_ex4_result_nor (vfdsu_ex4_result_nor ),
.vfdsu_ex4_result_qnan (vfdsu_ex4_result_qnan ),
.vfdsu_ex4_result_sign (vfdsu_ex4_result_sign ),
.vfdsu_ex4_result_zero (vfdsu_ex4_result_zero ),
.vfdsu_ex4_rslt_denorm (vfdsu_ex4_rslt_denorm ),
.vfdsu_ex4_single (vfdsu_ex4_single ),
.vfdsu_ex4_uf (vfdsu_ex4_uf )
);
// &ModuleEnd; @34
endmodule |
module ct_vfdsu_scalar_dp(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfdsu_ex1_pipex_dst_ereg,
dp_vfdsu_ex1_pipex_dst_vreg,
dp_vfdsu_ex1_pipex_iid,
dp_vfdsu_ex1_pipex_imm0,
dp_vfdsu_ex1_pipex_srcf0,
dp_vfdsu_ex1_pipex_srcf1,
ex1_data_clk,
ex1_div,
ex1_double,
ex1_pipedown,
ex1_scalar,
ex1_single,
ex1_sqrt,
ex1_src0,
ex1_src1,
ex1_static_rm,
ex2_data_clk,
ex2_pipedown,
ex3_data_clk,
ex3_pipedown,
ex4_out_expt,
ex4_out_result,
forever_cpuclk,
idu_vfpu_rf_pipex_func,
idu_vfpu_rf_pipex_gateclk_sel,
pad_yy_icg_scan_en,
pipex_dp_vfdsu_ereg,
pipex_dp_vfdsu_ereg_data,
pipex_dp_vfdsu_freg_data,
pipex_dp_vfdsu_vreg,
vfdsu_ex2_double,
vfdsu_ex2_single
);
// &Ports; @24
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [4 :0] dp_vfdsu_ex1_pipex_dst_ereg;
input [6 :0] dp_vfdsu_ex1_pipex_dst_vreg;
input [6 :0] dp_vfdsu_ex1_pipex_iid;
input [2 :0] dp_vfdsu_ex1_pipex_imm0;
input [63:0] dp_vfdsu_ex1_pipex_srcf0;
input [63:0] dp_vfdsu_ex1_pipex_srcf1;
input ex1_data_clk;
input ex1_pipedown;
input ex2_data_clk;
input ex2_pipedown;
input ex3_data_clk;
input ex3_pipedown;
input [4 :0] ex4_out_expt;
input [63:0] ex4_out_result;
input forever_cpuclk;
input [19:0] idu_vfpu_rf_pipex_func;
input idu_vfpu_rf_pipex_gateclk_sel;
input pad_yy_icg_scan_en;
output ex1_div;
output ex1_double;
output ex1_scalar;
output ex1_single;
output ex1_sqrt;
output [63:0] ex1_src0;
output [63:0] ex1_src1;
output [2 :0] ex1_static_rm;
output [4 :0] pipex_dp_vfdsu_ereg;
output [4 :0] pipex_dp_vfdsu_ereg_data;
output [63:0] pipex_dp_vfdsu_freg_data;
output [6 :0] pipex_dp_vfdsu_vreg;
output vfdsu_ex2_double;
output vfdsu_ex2_single;
// &Regs; @25
reg ex1_div;
reg ex1_double;
reg ex1_single;
reg ex1_sqrt;
reg vfdsu_ex2_div;
reg vfdsu_ex2_double;
reg [4 :0] vfdsu_ex2_dst_ereg;
reg [6 :0] vfdsu_ex2_dst_vreg;
reg [6 :0] vfdsu_ex2_iid;
reg vfdsu_ex2_single;
reg vfdsu_ex2_sqrt;
reg [4 :0] vfdsu_ex3_dst_ereg;
reg [6 :0] vfdsu_ex3_dst_vreg;
reg [6 :0] vfdsu_ex3_iid;
reg [4 :0] vfdsu_ex4_dst_ereg;
reg [6 :0] vfdsu_ex4_dst_vreg;
reg [6 :0] vfdsu_ex4_iid;
// &Wires; @26
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [4 :0] dp_vfdsu_ex1_pipex_dst_ereg;
wire [6 :0] dp_vfdsu_ex1_pipex_dst_vreg;
wire [6 :0] dp_vfdsu_ex1_pipex_iid;
wire [2 :0] dp_vfdsu_ex1_pipex_imm0;
wire [63:0] dp_vfdsu_ex1_pipex_srcf0;
wire [63:0] dp_vfdsu_ex1_pipex_srcf1;
wire ex1_data_clk;
wire ex1_pipedown;
wire ex1_scalar;
wire [63:0] ex1_src0;
wire [63:0] ex1_src1;
wire [2 :0] ex1_static_rm;
wire ex2_data_clk;
wire ex2_pipedown;
wire ex3_data_clk;
wire ex3_pipedown;
wire [4 :0] ex4_out_expt;
wire [63:0] ex4_out_result;
wire forever_cpuclk;
wire [19:0] idu_vfpu_rf_pipex_func;
wire idu_vfpu_rf_pipex_gateclk_sel;
wire pad_yy_icg_scan_en;
wire [4 :0] pipex_dp_vfdsu_ereg;
wire [4 :0] pipex_dp_vfdsu_ereg_data;
wire [63:0] pipex_dp_vfdsu_freg_data;
wire [6 :0] pipex_dp_vfdsu_vreg;
wire vfdsu_sew_clk;
wire vfdsu_sew_clk_en;
//==========================================================
// EX1 Stage Control Signal
//==========================================================
// &Force("bus","idu_vfpu_rf_pipex_func",19,0); @31
//assign func[19:0] = dp_vfdsu_ex1_pipex_func[19:0];
// &Instance("gated_clk_cell","x_vfdsu_sew_clk"); @33
gated_clk_cell x_vfdsu_sew_clk (
.clk_in (forever_cpuclk ),
.clk_out (vfdsu_sew_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (vfdsu_sew_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @34
// .clk_out (vfdsu_sew_clk),//Out Clock @35
// .external_en (1'b0), @36
// .global_en (cp0_yy_clk_en), @37
// .local_en (vfdsu_sew_clk_en),//Local Condition @38
// .module_en (cp0_vfpu_icg_en) @39
// ); @40
assign vfdsu_sew_clk_en = idu_vfpu_rf_pipex_gateclk_sel;
always @(posedge vfdsu_sew_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
ex1_div <= 1'b0;
ex1_sqrt <= 1'b0;
ex1_double <= 1'b0;
ex1_single <= 1'b0;
end
else if(idu_vfpu_rf_pipex_gateclk_sel)
begin
ex1_div <= idu_vfpu_rf_pipex_func[0];
ex1_sqrt <= idu_vfpu_rf_pipex_func[1];
ex1_double <= idu_vfpu_rf_pipex_func[16];
ex1_single <= idu_vfpu_rf_pipex_func[15];
end
end
assign ex1_scalar = 1'b1;
assign ex1_static_rm[2:0] = dp_vfdsu_ex1_pipex_imm0[2:0];
// &Force("output","ex1_div"); @61
// &Force("output","ex1_sqrt"); @62
// &Force("output","ex1_double"); @63
// &Force("output","ex1_single"); @64
assign ex1_src0[63:0] = dp_vfdsu_ex1_pipex_srcf0[63:0];
assign ex1_src1[63:0] = dp_vfdsu_ex1_pipex_srcf1[63:0];
always @(posedge ex1_data_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
vfdsu_ex2_dst_ereg[4:0] <= 5'b0;
vfdsu_ex2_dst_vreg[6:0] <= 7'b0;
vfdsu_ex2_iid[6:0] <= 7'b0;
vfdsu_ex2_double <= 1'b0;
vfdsu_ex2_single <= 1'b0;
vfdsu_ex2_div <= 1'b0;
vfdsu_ex2_sqrt <= 1'b0;
end
else if(ex1_pipedown)
begin
vfdsu_ex2_dst_ereg[4:0] <= dp_vfdsu_ex1_pipex_dst_ereg[4:0];
vfdsu_ex2_dst_vreg[6:0] <= dp_vfdsu_ex1_pipex_dst_vreg[6:0];
vfdsu_ex2_iid[6:0] <= dp_vfdsu_ex1_pipex_iid[6:0];
vfdsu_ex2_double <= ex1_double;
vfdsu_ex2_single <= ex1_single;
vfdsu_ex2_div <= ex1_div;
vfdsu_ex2_sqrt <= ex1_sqrt;
end
else
begin
vfdsu_ex2_dst_ereg[4:0] <= vfdsu_ex2_dst_ereg[4:0];
vfdsu_ex2_dst_vreg[6:0] <= vfdsu_ex2_dst_vreg[6:0];
vfdsu_ex2_iid[6:0] <= vfdsu_ex2_iid[6:0];
vfdsu_ex2_double <= vfdsu_ex2_double;
vfdsu_ex2_single <= vfdsu_ex2_single;
vfdsu_ex2_div <= vfdsu_ex2_div;
vfdsu_ex2_sqrt <= vfdsu_ex2_sqrt;
end
end
// &Force("output","vfdsu_ex2_double"); @103
// &Force("output","vfdsu_ex2_single"); @104
// //&Force("output","vfdsu_ex2_div"); @105
// //&Force("output","vfdsu_ex2_sqrt"); @106
always @(posedge ex2_data_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
vfdsu_ex3_dst_ereg[4:0] <= 5'b0;
vfdsu_ex3_dst_vreg[6:0] <= 7'b0;
vfdsu_ex3_iid[6:0] <= 7'b0;
// vfdsu_ex3_double <= 1'b0;
// vfdsu_ex3_single <= 1'b0;
// vfdsu_ex3_div <= 1'b0;
// vfdsu_ex3_sqrt <= 1'b0;
end
else if(ex2_pipedown)
begin
vfdsu_ex3_dst_ereg[4:0] <= vfdsu_ex2_dst_ereg[4:0];
vfdsu_ex3_dst_vreg[6:0] <= vfdsu_ex2_dst_vreg[6:0];
vfdsu_ex3_iid[6:0] <= vfdsu_ex2_iid[6:0];
// vfdsu_ex3_double <= vfdsu_ex2_double;
// vfdsu_ex3_single <= vfdsu_ex2_single;
// vfdsu_ex3_div <= vfdsu_ex2_div;
// vfdsu_ex3_sqrt <= vfdsu_ex2_sqrt;
end
else
begin
vfdsu_ex3_dst_ereg[4:0] <= vfdsu_ex3_dst_ereg[4:0];
vfdsu_ex3_dst_vreg[6:0] <= vfdsu_ex3_dst_vreg[6:0];
vfdsu_ex3_iid[6:0] <= vfdsu_ex3_iid[6:0];
// vfdsu_ex3_double <= vfdsu_ex3_double;
// vfdsu_ex3_single <= vfdsu_ex3_single;
// vfdsu_ex3_div <= vfdsu_ex3_div;
// vfdsu_ex3_sqrt <= vfdsu_ex3_sqrt;
end
end
// //&Force("output","vfdsu_ex3_double"); @142
// //&Force("output","vfdsu_ex3_single"); @143
always @(posedge ex3_data_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
vfdsu_ex4_dst_ereg[4:0] <= 5'b0;
vfdsu_ex4_dst_vreg[6:0] <= 7'b0;
vfdsu_ex4_iid[6:0] <= 7'b0;
// vfdsu_ex4_double <= 1'b0;
// vfdsu_ex4_single <= 1'b0;
// vfdsu_ex4_div <= 1'b0;
// vfdsu_ex4_sqrt <= 1'b0;
end
else if(ex3_pipedown)
begin
vfdsu_ex4_dst_ereg[4:0] <= vfdsu_ex3_dst_ereg[4:0];
vfdsu_ex4_dst_vreg[6:0] <= vfdsu_ex3_dst_vreg[6:0];
vfdsu_ex4_iid[6:0] <= vfdsu_ex3_iid[6:0];
// vfdsu_ex4_double <= vfdsu_ex3_double;
// vfdsu_ex4_single <= vfdsu_ex3_single;
// vfdsu_ex4_div <= vfdsu_ex3_div;
// vfdsu_ex4_sqrt <= vfdsu_ex3_sqrt;
end
else
begin
vfdsu_ex4_dst_ereg[4:0] <= vfdsu_ex4_dst_ereg[4:0];
vfdsu_ex4_dst_vreg[6:0] <= vfdsu_ex4_dst_vreg[6:0];
vfdsu_ex4_iid[6:0] <= vfdsu_ex4_iid[6:0];
// vfdsu_ex4_double <= vfdsu_ex4_double;
// vfdsu_ex4_single <= vfdsu_ex4_single;
// vfdsu_ex4_div <= vfdsu_ex4_div;
// vfdsu_ex4_sqrt <= vfdsu_ex4_sqrt;
end
end
// //&Force("output","vfdsu_ex4_double"); @178
// //&Force("output","vfdsu_ex4_single"); @179
assign pipex_dp_vfdsu_ereg_data[4:0] = ex4_out_expt[4:0];
assign pipex_dp_vfdsu_freg_data[63:0] = ex4_out_result[63:0];
assign pipex_dp_vfdsu_ereg[4:0] = vfdsu_ex4_dst_ereg[4:0];
assign pipex_dp_vfdsu_vreg[6:0] = vfdsu_ex4_dst_vreg[6:0];
// &ModuleEnd; @192
endmodule |
module ct_vfdsu_ctrl(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfdsu_ex1_pipex_sel,
dp_vfdsu_fdiv_gateclk_issue,
dp_vfdsu_idu_fdiv_issue,
ex1_data_clk,
ex1_double,
ex1_pipedown,
ex1_single,
ex2_data_clk,
ex2_pipedown,
ex2_srt_first_round,
ex3_data_clk,
ex3_pipedown,
forever_cpuclk,
pad_yy_icg_scan_en,
pipex_dp_vfdsu_inst_vld,
rtu_yy_xx_flush,
srt_ctrl_rem_zero,
srt_ctrl_skip_srt,
srt_secd_round,
srt_sm_on,
vfdsu_dp_fdiv_busy,
vfdsu_dp_inst_wb_req,
vfdsu_ex2_double,
vfdsu_ex2_single,
vfdsu_ifu_debug_ex2_wait,
vfdsu_ifu_debug_idle,
vfdsu_ifu_debug_pipe_busy
);
// &Ports; @24
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input dp_vfdsu_ex1_pipex_sel;
input dp_vfdsu_fdiv_gateclk_issue;
input dp_vfdsu_idu_fdiv_issue;
input ex1_double;
input ex1_single;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
input srt_ctrl_rem_zero;
input srt_ctrl_skip_srt;
input vfdsu_ex2_double;
input vfdsu_ex2_single;
output ex1_data_clk;
output ex1_pipedown;
output ex2_data_clk;
output ex2_pipedown;
output ex2_srt_first_round;
output ex3_data_clk;
output ex3_pipedown;
output pipex_dp_vfdsu_inst_vld;
output srt_secd_round;
output srt_sm_on;
output vfdsu_dp_fdiv_busy;
output vfdsu_dp_inst_wb_req;
output vfdsu_ifu_debug_ex2_wait;
output vfdsu_ifu_debug_idle;
output vfdsu_ifu_debug_pipe_busy;
// &Regs; @25
reg [3:0] div_cur_state;
reg [3:0] div_next_state;
reg ex2_srt_first_round;
reg ex2_srt_secd_round;
reg [4:0] srt_cnt;
reg srt_cur_state;
reg srt_nxt_state;
reg vfdsu_ex3_vld;
reg vfdsu_ex4_vld;
// &Wires; @26
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire div_sm_clk;
wire div_sm_clk_en;
wire div_st_ex2;
wire dp_vfdsu_ex1_pipex_sel;
wire dp_vfdsu_fdiv_gateclk_issue;
wire dp_vfdsu_idu_fdiv_issue;
wire ex1_data_clk;
wire ex1_data_clk_en;
wire ex1_double;
wire ex1_pipedown;
wire ex1_single;
wire ex2_data_clk;
wire ex2_data_clk_en;
wire ex2_pipe_clk;
wire ex2_pipe_clk_en;
wire ex2_pipedown;
wire ex2_srt_secd_round_pre;
wire ex3_data_clk;
wire ex3_data_clk_en;
wire ex3_pipe_clk;
wire ex3_pipe_clk_en;
wire ex3_pipedown;
wire ex4_pipedown;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire pipex_dp_vfdsu_inst_vld;
wire rtu_yy_xx_flush;
wire skip_srt;
wire [4:0] srt_cnt_ini;
wire srt_cnt_zero;
wire srt_ctrl_rem_zero;
wire srt_ctrl_skip_srt;
wire srt_last_round;
wire srt_secd_round;
wire srt_secd_round_pre;
wire srt_sm_clk;
wire srt_sm_clk_en;
wire srt_sm_on;
wire vfdsu_dp_fdiv_busy;
wire vfdsu_dp_inst_wb_req;
wire vfdsu_ex2_double;
wire vfdsu_ex2_single;
wire vfdsu_ex2_vld;
wire vfdsu_ifu_debug_ex2_wait;
wire vfdsu_ifu_debug_idle;
wire vfdsu_ifu_debug_pipe_busy;
//==========================================================
// EX1 Stage Control Signal
//==========================================================
//vfdsu ex1 pipedown signal
assign ex1_pipedown = dp_vfdsu_ex1_pipex_sel;
// &Force("output","ex1_pipedown"); @34
//==========================================================
// EX2 Stage Control Signal
//==========================================================
//state parameter
parameter SRT_IDLE = 1'b0;
parameter SRT_BUSY = 1'b1;
//gate clk
// &Instance("gated_clk_cell","x_srt_sm_clk"); @43
gated_clk_cell x_srt_sm_clk (
.clk_in (forever_cpuclk ),
.clk_out (srt_sm_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (srt_sm_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @44
// .clk_out (srt_sm_clk),//Out Clock @45
// .external_en (1'b0), @46
// .global_en (cp0_yy_clk_en), @47
// .local_en (srt_sm_clk_en),//Local Condition @48
// .module_en (cp0_vfpu_icg_en) @49
// ); @50
assign srt_sm_clk_en = srt_cur_state ||
ex1_pipedown ||
rtu_yy_xx_flush;
//state machine
always @(posedge srt_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
srt_cur_state <= SRT_IDLE;
else if(rtu_yy_xx_flush)
srt_cur_state <= SRT_IDLE;
else
srt_cur_state <= srt_nxt_state;
end
// &CombBeg; @66
always @( ex1_pipedown
or srt_last_round
or srt_cur_state)
begin
case(srt_cur_state)
SRT_IDLE : if(ex1_pipedown)
srt_nxt_state = SRT_BUSY;
else
srt_nxt_state = SRT_IDLE;
SRT_BUSY : if(srt_last_round)
srt_nxt_state = SRT_IDLE;
else
srt_nxt_state = SRT_BUSY;
default : srt_nxt_state = SRT_IDLE;
endcase
// &CombEnd; @78
end
//srt sm state
//assign srt_sm_idle = ~srt_cur_state;
assign srt_sm_on = srt_cur_state;
// &Force("output","srt_sm_on"); @83
//state machine control signal
//srt_last_round on three condition :
// 1.srt need not execute
// 2.srt rem is zero
// 3.srt cnt zero
assign srt_last_round = (skip_srt ||
srt_ctrl_rem_zero ||
srt_cnt_zero) &&
srt_sm_on;
assign skip_srt = srt_ctrl_skip_srt;
assign srt_cnt_zero = ~|srt_cnt[4:0];
//srt counter
always @(posedge srt_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
srt_cnt[4:0] <= 5'b0;
else if(rtu_yy_xx_flush)
srt_cnt[4:0] <= 5'b0;
else if(ex1_pipedown)
srt_cnt[4:0] <= srt_cnt_ini[4:0];
else if(srt_sm_on)
srt_cnt[4:0] <= srt_cnt[4:0] - 5'b1;
else
srt_cnt[4:0] <= srt_cnt[4:0];
end
//srt_cnt_ini[4:0]
//For Double, initial is 5'b11100('d28), calculate 29 round
//For Single, initial is 5'b01110('d14), calculate 15 round
assign srt_cnt_ini[4:0] = (ex1_double) ? 5'b01101 :
ex1_single ? 5'b00110
: 5'b00011;
//vfdsu ex2 pipedown signal
assign ex2_pipedown = srt_last_round && div_st_ex2;
// &Force("output","ex2_pipedown"); @157
// &Force("output","ex2_srt_first_round"); @172
always @(posedge srt_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ex2_srt_first_round <= 1'b0;
else if(rtu_yy_xx_flush)
ex2_srt_first_round <= 1'b0;
else if(ex1_pipedown)
ex2_srt_first_round <= 1'h1;
else
ex2_srt_first_round <= 1'b0;
end
// &Force("output","ex2_srt_first_round"); @195
always @(posedge srt_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ex2_srt_secd_round <= 1'b0;
else if(rtu_yy_xx_flush)
ex2_srt_secd_round <= 1'b0;
else
ex2_srt_secd_round <= {1{ex2_srt_secd_round_pre}};
end
assign srt_secd_round = ex2_srt_secd_round;
assign ex2_srt_secd_round_pre = srt_sm_on && srt_secd_round_pre;
assign srt_secd_round_pre = vfdsu_ex2_double ? srt_cnt[4:0]==5'b01101 :
vfdsu_ex2_single ? srt_cnt[4:0]==5'b00110 : srt_cnt[4:0] == 5'b00011;
//==========================================================
// EX3 Stage Control Signal
//==========================================================
//gate clk
// &Instance("gated_clk_cell","x_ex2_pipe_clk"); @217
gated_clk_cell x_ex2_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_pipe_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @218
// .clk_out (ex2_pipe_clk),//Out Clock @219
// .external_en (1'b0), @220
// .global_en (cp0_yy_clk_en), @221
// .local_en (ex2_pipe_clk_en),//Local Condition @222
// .module_en (cp0_vfpu_icg_en) @223
// ); @224
assign ex2_pipe_clk_en = vfdsu_ex2_vld ||
vfdsu_ex3_vld ||
rtu_yy_xx_flush;
assign vfdsu_ex2_vld = ex2_pipedown;
//EX2 to EX3 pipedown
always @(posedge ex2_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vfdsu_ex3_vld <= 1'b0;
else if(rtu_yy_xx_flush)
vfdsu_ex3_vld <= 1'b0;
else if(ex2_pipedown)
vfdsu_ex3_vld <= 1'b1;
else
vfdsu_ex3_vld <= 1'b0;
end
assign ex3_pipedown = vfdsu_ex3_vld;
// &Force("output","ex3_pipedown"); @242
//==========================================================
// EX4 Stage Control Signal
//==========================================================
//gate clk
// &Instance("gated_clk_cell","x_ex3_pipe_clk"); @248
gated_clk_cell x_ex3_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex3_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex3_pipe_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @249
// .clk_out (ex3_pipe_clk),//Out Clock @250
// .external_en (1'b0), @251
// .global_en (cp0_yy_clk_en), @252
// .local_en (ex3_pipe_clk_en),//Local Condition @253
// .module_en (cp0_vfpu_icg_en) @254
// ); @255
assign ex3_pipe_clk_en = ex3_pipedown ||
vfdsu_ex4_vld ||
rtu_yy_xx_flush;
//EX3 to EX4 pipedown
always @(posedge ex3_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vfdsu_ex4_vld <= 1'b0;
else if(rtu_yy_xx_flush)
vfdsu_ex4_vld <= 1'b0;
else if(ex3_pipedown)
vfdsu_ex4_vld <= 1'b1;
else
vfdsu_ex4_vld <= 1'b0;
end
assign ex4_pipedown = vfdsu_ex4_vld;
//Div Write Back State Machine
parameter IDLE = 4'b0000;
parameter RF = 4'b0100;
parameter EX1 = 4'b0101;
parameter EX2 = 4'b0110;
parameter WB_REQ = 4'b0111;
parameter WB = 4'b1000;
//GateClk
// &Instance("gated_clk_cell","x_div_sm_clk"); @284
gated_clk_cell x_div_sm_clk (
.clk_in (forever_cpuclk ),
.clk_out (div_sm_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (div_sm_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @285
// .clk_out (div_sm_clk),//Out Clock @286
// .external_en (1'b0), @287
// .global_en (cp0_yy_clk_en), @288
// .local_en (div_sm_clk_en),//Local Condition @289
// .module_en (cp0_vfpu_icg_en) @290
// ); @291
assign div_sm_clk_en = dp_vfdsu_fdiv_gateclk_issue ||
!(div_cur_state[3:0] == IDLE);
//State Trans
always @(posedge div_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
div_cur_state[3:0] <= IDLE;
else if(rtu_yy_xx_flush)
div_cur_state[3:0] <= IDLE;
else
div_cur_state[3:0] <= div_next_state[3:0];
end
// &CombBeg; @304
always @( dp_vfdsu_idu_fdiv_issue
or dp_vfdsu_ex1_pipex_sel
or ex4_pipedown
or srt_last_round
or div_cur_state[3:0])
begin
case(div_cur_state[3:0])
IDLE : if(dp_vfdsu_idu_fdiv_issue)
div_next_state[3:0] = RF;
else
div_next_state[3:0] = IDLE;
RF : div_next_state[3:0] = EX1;
EX1 : if(dp_vfdsu_ex1_pipex_sel)
div_next_state[3:0] = EX2;
else
div_next_state[3:0] = IDLE;
EX2 : if(srt_last_round)
div_next_state[3:0] = WB_REQ;
else
div_next_state[3:0] = EX2;
WB_REQ : if(ex4_pipedown)
div_next_state[3:0] = WB;
else
div_next_state[3:0] = WB_REQ;
WB : if(dp_vfdsu_idu_fdiv_issue)
div_next_state[3:0] = RF;
else
div_next_state[3:0] = IDLE;
default : div_next_state[3:0] = IDLE;
endcase
// &CombEnd; @329
end
//Control Signal
assign div_st_ex2 = (div_cur_state[3:0] == EX2);
//Div Rdy Signal
//assign vfdsu_vfpu_gateclk_en = div_cur_state[2] || div_cur_state[3] ||
// ex4_pipedown;
//Active Data with VFPU
//GateClk
// &Instance("gated_clk_cell","x_ex1_data_clk"); @340
gated_clk_cell x_ex1_data_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_data_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @341
// .clk_out (ex1_data_clk),//Out Clock @342
// .external_en (1'b0), @343
// .global_en (cp0_yy_clk_en), @344
// .local_en (ex1_data_clk_en),//Local Condition @345
// .module_en (cp0_vfpu_icg_en) @346
// ); @347
assign ex1_data_clk_en = ex1_pipedown;
// &Instance("gated_clk_cell","x_ex2_data_clk"); @350
gated_clk_cell x_ex2_data_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_data_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @351
// .clk_out (ex2_data_clk),//Out Clock @352
// .external_en (1'b0), @353
// .global_en (cp0_yy_clk_en), @354
// .local_en (ex2_data_clk_en),//Local Condition @355
// .module_en (cp0_vfpu_icg_en) @356
// ); @357
assign ex2_data_clk_en = ex2_pipedown;
// &Instance("gated_clk_cell","x_ex3_data_clk"); @360
gated_clk_cell x_ex3_data_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex3_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex3_data_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @361
// .clk_out (ex3_data_clk),//Out Clock @362
// .external_en (1'b0), @363
// .global_en (cp0_yy_clk_en), @364
// .local_en (ex3_data_clk_en),//Local Condition @365
// .module_en (cp0_vfpu_icg_en) @366
// ); @367
assign ex3_data_clk_en = ex3_pipedown;
assign pipex_dp_vfdsu_inst_vld = div_cur_state[3:0] == WB;
// this is used to apply write back port
assign vfdsu_dp_inst_wb_req = vfdsu_ex3_vld;
assign vfdsu_dp_fdiv_busy = div_cur_state[2];
//Debug infor
assign vfdsu_ifu_debug_ex2_wait = 1'b0;
assign vfdsu_ifu_debug_idle = (div_cur_state[3:0] == IDLE);
assign vfdsu_ifu_debug_pipe_busy = 1'b0;
// &ModuleEnd; @381
endmodule |
module ct_vfdsu_srt(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ex1_div,
ex1_divisor,
ex1_pipedown,
ex1_remainder,
ex1_sqrt,
ex2_pipedown,
ex2_srt_first_round,
forever_cpuclk,
pad_yy_icg_scan_en,
srt_ctrl_rem_zero,
srt_ctrl_skip_srt,
srt_secd_round,
srt_sm_on,
total_qt_rt_58,
vfdsu_ex2_div,
vfdsu_ex2_double,
vfdsu_ex2_dz,
vfdsu_ex2_expnt_add0,
vfdsu_ex2_expnt_add1,
vfdsu_ex2_nv,
vfdsu_ex2_of_rm_lfn,
vfdsu_ex2_op0_norm,
vfdsu_ex2_op1_norm,
vfdsu_ex2_qnan_f,
vfdsu_ex2_qnan_sign,
vfdsu_ex2_result_inf,
vfdsu_ex2_result_qnan,
vfdsu_ex2_result_sign,
vfdsu_ex2_result_zero,
vfdsu_ex2_rm,
vfdsu_ex2_single,
vfdsu_ex2_sqrt,
vfdsu_ex2_srt_skip,
vfdsu_ex3_doub_expnt_rst,
vfdsu_ex3_double,
vfdsu_ex3_dz,
vfdsu_ex3_half_expnt_rst,
vfdsu_ex3_id_srt_skip,
vfdsu_ex3_nv,
vfdsu_ex3_of,
vfdsu_ex3_potnt_of,
vfdsu_ex3_potnt_uf,
vfdsu_ex3_qnan_f,
vfdsu_ex3_qnan_sign,
vfdsu_ex3_rem_sign,
vfdsu_ex3_rem_zero,
vfdsu_ex3_result_denorm_round_add_num,
vfdsu_ex3_result_inf,
vfdsu_ex3_result_lfn,
vfdsu_ex3_result_qnan,
vfdsu_ex3_result_sign,
vfdsu_ex3_result_zero,
vfdsu_ex3_rm,
vfdsu_ex3_rslt_denorm,
vfdsu_ex3_sing_expnt_rst,
vfdsu_ex3_single,
vfdsu_ex3_uf
);
// &Ports; @23
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ex1_div;
input [52:0] ex1_divisor;
input ex1_pipedown;
input [59:0] ex1_remainder;
input ex1_sqrt;
input ex2_pipedown;
input ex2_srt_first_round;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input srt_secd_round;
input srt_sm_on;
input vfdsu_ex2_div;
input vfdsu_ex2_double;
input vfdsu_ex2_dz;
input [12:0] vfdsu_ex2_expnt_add0;
input [12:0] vfdsu_ex2_expnt_add1;
input vfdsu_ex2_nv;
input vfdsu_ex2_of_rm_lfn;
input vfdsu_ex2_op0_norm;
input vfdsu_ex2_op1_norm;
input [51:0] vfdsu_ex2_qnan_f;
input vfdsu_ex2_qnan_sign;
input vfdsu_ex2_result_inf;
input vfdsu_ex2_result_qnan;
input vfdsu_ex2_result_sign;
input vfdsu_ex2_result_zero;
input [2 :0] vfdsu_ex2_rm;
input vfdsu_ex2_single;
input vfdsu_ex2_sqrt;
input vfdsu_ex2_srt_skip;
output srt_ctrl_rem_zero;
output srt_ctrl_skip_srt;
output [57:0] total_qt_rt_58;
output [12:0] vfdsu_ex3_doub_expnt_rst;
output vfdsu_ex3_double;
output vfdsu_ex3_dz;
output [12:0] vfdsu_ex3_half_expnt_rst;
output vfdsu_ex3_id_srt_skip;
output vfdsu_ex3_nv;
output vfdsu_ex3_of;
output vfdsu_ex3_potnt_of;
output vfdsu_ex3_potnt_uf;
output [51:0] vfdsu_ex3_qnan_f;
output vfdsu_ex3_qnan_sign;
output vfdsu_ex3_rem_sign;
output vfdsu_ex3_rem_zero;
output [52:0] vfdsu_ex3_result_denorm_round_add_num;
output vfdsu_ex3_result_inf;
output vfdsu_ex3_result_lfn;
output vfdsu_ex3_result_qnan;
output vfdsu_ex3_result_sign;
output vfdsu_ex3_result_zero;
output [2 :0] vfdsu_ex3_rm;
output vfdsu_ex3_rslt_denorm;
output [8 :0] vfdsu_ex3_sing_expnt_rst;
output vfdsu_ex3_single;
output vfdsu_ex3_uf;
// &Regs; @24
reg [52:0] ex2_result_double_denorm_round_add_num;
reg [52:0] ex2_result_half_denorm_round_add_num;
reg [52:0] ex2_result_single_denorm_round_add_num;
reg [12:0] vfdsu_ex3_doub_expnt_rst;
reg vfdsu_ex3_double;
reg vfdsu_ex3_dz;
reg [12:0] vfdsu_ex3_half_expnt_rst;
reg vfdsu_ex3_id_srt_skip;
reg vfdsu_ex3_nv;
reg vfdsu_ex3_of;
reg vfdsu_ex3_potnt_of;
reg vfdsu_ex3_potnt_uf;
reg [51:0] vfdsu_ex3_qnan_f;
reg vfdsu_ex3_qnan_sign;
reg vfdsu_ex3_rem_sign;
reg [52:0] vfdsu_ex3_result_denorm_round_add_num;
reg vfdsu_ex3_result_inf;
reg vfdsu_ex3_result_lfn;
reg vfdsu_ex3_result_qnan;
reg vfdsu_ex3_result_sign;
reg vfdsu_ex3_result_zero;
reg [2 :0] vfdsu_ex3_rm;
reg vfdsu_ex3_rslt_denorm;
reg [8 :0] vfdsu_ex3_sing_expnt_rst;
reg vfdsu_ex3_single;
reg vfdsu_ex3_uf;
// &Wires; @25
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ex1_div;
wire [52:0] ex1_divisor;
wire ex1_pipedown;
wire [59:0] ex1_remainder;
wire ex1_sqrt;
wire ex2_div_of;
wire ex2_div_uf;
wire ex2_doub_expnt_of;
wire ex2_doub_expnt_uf;
wire ex2_doub_potnt_of;
wire ex2_doub_potnt_uf;
wire ex2_double_id_nor_srt_skip;
wire ex2_expnt_of;
wire [12:0] ex2_expnt_result;
wire ex2_expnt_uf;
wire ex2_half_expnt_of;
wire ex2_half_expnt_uf;
wire ex2_half_id_nor_srt_skip;
wire ex2_half_potnt_of;
wire ex2_half_potnt_uf;
wire ex2_id_nor_srt_skip;
wire ex2_of;
wire ex2_of_plus;
wire ex2_pipe_clk;
wire ex2_pipe_clk_en;
wire ex2_pipedown;
wire ex2_potnt_of;
wire ex2_potnt_of_pre;
wire ex2_potnt_uf;
wire ex2_potnt_uf_pre;
wire [52:0] ex2_result_denorm_round_add_num;
wire ex2_result_inf;
wire ex2_result_lfn;
wire ex2_result_qnan;
wire ex2_result_zero;
wire ex2_rslt_denorm;
wire ex2_sing_expnt_of;
wire ex2_sing_expnt_uf;
wire ex2_sing_potnt_of;
wire ex2_sing_potnt_uf;
wire ex2_single_id_nor_srt_skip;
wire [12:0] ex2_sqrt_expnt_result;
wire ex2_srt_first_round;
wire ex2_uf;
wire ex2_uf_plus;
wire forever_cpuclk;
wire [6 :0] initial_bound_sel_in;
wire [55:0] initial_divisor_in;
wire [60:0] initial_remainder_in;
wire initial_srt_en;
wire initial_srt_sel_div_in;
wire initial_srt_sel_sqrt_in;
wire pad_yy_icg_scan_en;
wire srt_ctrl_rem_zero;
wire srt_ctrl_skip_srt;
wire srt_first_round;
wire [60:0] srt_remainder;
wire [59:0] srt_remainder_out;
wire srt_remainder_sign;
wire srt_secd_round;
wire srt_sm_on;
wire [57:0] total_qt_rt;
wire [57:0] total_qt_rt_58;
wire [57:0] vdiv_qt_rt;
wire vfdsu_ex2_div;
wire vfdsu_ex2_double;
wire vfdsu_ex2_dz;
wire [12:0] vfdsu_ex2_expnt_add0;
wire [12:0] vfdsu_ex2_expnt_add1;
wire [12:0] vfdsu_ex2_expnt_rst;
wire vfdsu_ex2_nv;
wire vfdsu_ex2_of_rm_lfn;
wire vfdsu_ex2_op0_norm;
wire vfdsu_ex2_op1_norm;
wire [51:0] vfdsu_ex2_qnan_f;
wire vfdsu_ex2_qnan_sign;
wire vfdsu_ex2_result_inf;
wire vfdsu_ex2_result_qnan;
wire vfdsu_ex2_result_sign;
wire vfdsu_ex2_result_zero;
wire [2 :0] vfdsu_ex2_rm;
wire vfdsu_ex2_single;
wire vfdsu_ex2_sqrt;
wire vfdsu_ex2_srt_skip;
wire vfdsu_ex3_rem_zero;
//====================EX2 Expt info=========================
//EX1 only detect of/uf under id condition
//EX2 will deal with other condition
//When input is normal, overflow when E1-E2 > 128/1024
//here we mov the expnt result calculation into second stage
assign vfdsu_ex2_expnt_rst[12:0] = (vfdsu_ex2_sqrt)
? ex2_sqrt_expnt_result[12:0]
: ex2_expnt_result[12:0];
assign ex2_sqrt_expnt_result[12:0] = {ex2_expnt_result[12],
ex2_expnt_result[12:1]};
assign ex2_expnt_result[12:0] = vfdsu_ex2_expnt_add0[12:0] - vfdsu_ex2_expnt_add1[12:0];
assign ex2_doub_expnt_of = ~vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11]
|| (vfdsu_ex2_expnt_rst[10] &&
|vfdsu_ex2_expnt_rst[9:0]));
assign ex2_sing_expnt_of = ~vfdsu_ex2_expnt_rst[9] && (vfdsu_ex2_expnt_rst[8]
|| (vfdsu_ex2_expnt_rst[7] &&
|vfdsu_ex2_expnt_rst[6:0]));
assign ex2_half_expnt_of = ~vfdsu_ex2_expnt_rst[6] && (vfdsu_ex2_expnt_rst[5]
|| (vfdsu_ex2_expnt_rst[4] &&
|vfdsu_ex2_expnt_rst[3:0]));
assign ex2_expnt_of = vfdsu_ex2_double ? ex2_doub_expnt_of :
vfdsu_ex2_single ? ex2_sing_expnt_of
: ex2_half_expnt_of;
assign ex2_potnt_of_pre = vfdsu_ex2_double ? ex2_doub_potnt_of :
vfdsu_ex2_single ? ex2_sing_potnt_of : ex2_half_potnt_of;
assign ex2_potnt_uf_pre = vfdsu_ex2_double ? ex2_doub_potnt_uf :
vfdsu_ex2_single ? ex2_sing_potnt_uf : ex2_half_potnt_uf;
assign ex2_expnt_uf = vfdsu_ex2_double ? ex2_doub_expnt_uf :
vfdsu_ex2_single ? ex2_sing_expnt_uf : ex2_half_expnt_uf;
assign ex2_id_nor_srt_skip = vfdsu_ex2_double ? ex2_double_id_nor_srt_skip :
vfdsu_ex2_single ? ex2_single_id_nor_srt_skip
: ex2_half_id_nor_srt_skip;
assign ex2_result_denorm_round_add_num[52:0] = vfdsu_ex2_double ?
ex2_result_double_denorm_round_add_num[52:0] :
vfdsu_ex2_single ?
ex2_result_single_denorm_round_add_num[52:0] :
ex2_result_half_denorm_round_add_num[52:0];
//potential overflow when E1-E2 = 128/1024
assign ex2_doub_potnt_of = ~vfdsu_ex2_expnt_rst[12] &&
~vfdsu_ex2_expnt_rst[11] &&
vfdsu_ex2_expnt_rst[10] &&
~|vfdsu_ex2_expnt_rst[9:0];
assign ex2_sing_potnt_of = ~vfdsu_ex2_expnt_rst[9] &&
~vfdsu_ex2_expnt_rst[8] &&
vfdsu_ex2_expnt_rst[7] &&
~|vfdsu_ex2_expnt_rst[6:0];
assign ex2_half_potnt_of = ~vfdsu_ex2_expnt_rst[6] &&
~vfdsu_ex2_expnt_rst[5] &&
vfdsu_ex2_expnt_rst[4] &&
~|vfdsu_ex2_expnt_rst[3:0];
assign ex2_potnt_of = ex2_potnt_of_pre &&
vfdsu_ex2_op0_norm &&
vfdsu_ex2_op1_norm &&
vfdsu_ex2_div;
//When input is normal, underflow when E1-E2 <= -127/-1023/-15
assign ex2_doub_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hc01);
assign ex2_sing_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hf81);
assign ex2_half_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hff1);
assign ex2_half_potnt_uf = &vfdsu_ex2_expnt_rst[6:4] &&
~|vfdsu_ex2_expnt_rst[3:2] &&
vfdsu_ex2_expnt_rst[1] &&
!vfdsu_ex2_expnt_rst[0];
//potential underflow when E1-E2 = -126/-1022
assign ex2_doub_potnt_uf = &vfdsu_ex2_expnt_rst[12:10] &&
~|vfdsu_ex2_expnt_rst[9:2] &&
vfdsu_ex2_expnt_rst[1] &&
!vfdsu_ex2_expnt_rst[0];
assign ex2_sing_potnt_uf = &vfdsu_ex2_expnt_rst[9:7] &&
~|vfdsu_ex2_expnt_rst[6:2] &&
vfdsu_ex2_expnt_rst[1] &&
!vfdsu_ex2_expnt_rst[0];
assign ex2_potnt_uf = (ex2_potnt_uf_pre &&
vfdsu_ex2_op0_norm &&
vfdsu_ex2_op1_norm &&
vfdsu_ex2_div) ||
(ex2_potnt_uf_pre &&
vfdsu_ex2_op0_norm);
//========================EX2 Overflow======================
//ex2 overflow when
// 1.op0 & op1 both norm && expnt overflow
// 2.ex1_id_of
assign ex2_of = ex2_of_plus;
assign ex2_of_plus = ex2_div_of && vfdsu_ex2_div;
assign ex2_div_of = vfdsu_ex2_op0_norm &&
vfdsu_ex2_op1_norm &&
ex2_expnt_of;
//=======================EX2 Underflow======================
//ex2 underflow when
// 1.op0 & op1 both norm && expnt underflow
// 2.ex1_id_uf
// and detect when to skip the srt, here, we have further optmization
assign ex2_uf = ex2_uf_plus;
assign ex2_uf_plus = ex2_div_uf && vfdsu_ex2_div;
assign ex2_div_uf = vfdsu_ex2_op0_norm &&
vfdsu_ex2_op1_norm &&
ex2_expnt_uf;
assign ex2_double_id_nor_srt_skip = vfdsu_ex2_expnt_rst[12]
&& (vfdsu_ex2_expnt_rst[11:0]<12'hbcd);
assign ex2_single_id_nor_srt_skip = vfdsu_ex2_expnt_rst[12]
&& (vfdsu_ex2_expnt_rst[11:0]<12'hf6a);
assign ex2_half_id_nor_srt_skip = vfdsu_ex2_expnt_rst[12]
&& (vfdsu_ex2_expnt_rst[11:0]<12'hfe7);
assign ex2_rslt_denorm = ex2_uf;
//=======================EX2 skip srt iteration======================
assign srt_ctrl_skip_srt = ex2_of || ex2_id_nor_srt_skip
|| vfdsu_ex2_srt_skip;
//===============ex2 round prepare for denormal round======
// &CombBeg; @146
always @( vfdsu_ex2_expnt_rst[12:0])
begin
case(vfdsu_ex2_expnt_rst[12:0])
13'h1c02:ex2_result_double_denorm_round_add_num[52:0] = 53'h1; //-1022 1
13'h1c01:ex2_result_double_denorm_round_add_num[52:0] = 53'h2; //-1023 0
13'h1c00:ex2_result_double_denorm_round_add_num[52:0] = 53'h4; //-1024 -1
13'h1bff:ex2_result_double_denorm_round_add_num[52:0] = 53'h8; //-1025 -2
13'h1bfe:ex2_result_double_denorm_round_add_num[52:0] = 53'h10; //-1026 -3
13'h1bfd:ex2_result_double_denorm_round_add_num[52:0] = 53'h20; //-1027 -4
13'h1bfc:ex2_result_double_denorm_round_add_num[52:0] = 53'h40; //-1028 -5
13'h1bfb:ex2_result_double_denorm_round_add_num[52:0] = 53'h80; //-1029 -6
13'h1bfa:ex2_result_double_denorm_round_add_num[52:0] = 53'h100; //-1030 -7
13'h1bf9:ex2_result_double_denorm_round_add_num[52:0] = 53'h200; //-1031 -8
13'h1bf8:ex2_result_double_denorm_round_add_num[52:0] = 53'h400; //-1032 -9
13'h1bf7:ex2_result_double_denorm_round_add_num[52:0] = 53'h800; //-1033 -10
13'h1bf6:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000; //-1034 -11
13'h1bf5:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000; //-1035 -12
13'h1bf4:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000; //-1036 -13
13'h1bf3:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000; // -1037
13'h1bf2:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000;//-1038
13'h1bf1:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000;//-1039
13'h1bf0:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000; //-1040
13'h1bef:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000; //-1041
13'h1bee:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000; //-1042
13'h1bed:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000; //-1043
13'h1bec:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000; //-1044
13'h1beb:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000; //-1045
13'h1bea:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000;//-1046
13'h1be9:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000;//-1047
13'h1be8:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000; //-1048
13'h1be7:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000; //-1049
13'h1be6:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000;//-1050
13'h1be5:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000000; //-1051
13'h1be4:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000000; //-1052
13'h1be3:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000000; //-1053
13'h1be2:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000000; //-1054
13'h1be1:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000000; //-1055
13'h1be0:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000000; //-1056
13'h1bdf:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000000; //-1057
13'h1bde:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000000; //-1058
13'h1bdd:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000000; //-1059
13'h1bdc:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000000; //-1060
13'h1bdb:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000000; //-1061
13'h1bda:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000000; //-1062
13'h1bd9:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000000000; //-1063
13'h1bd8:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000000000; //-1064
13'h1bd7:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000000000; //-1065
13'h1bd6:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000000000; //-1066
13'h1bd5:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000000000; //-1067
13'h1bd4:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000000000; //-1068
13'h1bd3:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000000000; //-1069
13'h1bd2:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000000000;//-1070
13'h1bd1:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000000000; //-1071
13'h1bd0:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000000000; //-1072
13'h1bcf:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000000000; //-1073
13'h1bce:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000000000; //-1073
default: ex2_result_double_denorm_round_add_num[52:0] = 53'h0;
endcase
// &CombEnd; @203
end
// &CombBeg; @204
always @( vfdsu_ex2_expnt_rst[12:0])
begin
case(vfdsu_ex2_expnt_rst[12:0])
13'h1f82:ex2_result_single_denorm_round_add_num[52:0] = 53'h20000000; //-126 1
13'h1f81:ex2_result_single_denorm_round_add_num[52:0] = 53'h40000000; //-127 0
13'h1f80:ex2_result_single_denorm_round_add_num[52:0] = 53'h80000000; //-128 -1
13'h1f7f:ex2_result_single_denorm_round_add_num[52:0] = 53'h100000000; //-129 -2
13'h1f7e:ex2_result_single_denorm_round_add_num[52:0] = 53'h200000000; //-130 -3
13'h1f7d:ex2_result_single_denorm_round_add_num[52:0] = 53'h400000000; //-131 -4
13'h1f7c:ex2_result_single_denorm_round_add_num[52:0] = 53'h800000000; //-132 -5
13'h1f7b:ex2_result_single_denorm_round_add_num[52:0] = 53'h1000000000; //-133 -6
13'h1f7a:ex2_result_single_denorm_round_add_num[52:0] = 53'h2000000000; //-134 -7
13'h1f79:ex2_result_single_denorm_round_add_num[52:0] = 53'h4000000000; //-135 -8
13'h1f78:ex2_result_single_denorm_round_add_num[52:0] = 53'h8000000000; //-136 -9
13'h1f77:ex2_result_single_denorm_round_add_num[52:0] = 53'h10000000000; //-137 -10
13'h1f76:ex2_result_single_denorm_round_add_num[52:0] = 53'h20000000000; //-138 -11
13'h1f75:ex2_result_single_denorm_round_add_num[52:0] = 53'h40000000000; //-139 -12
13'h1f74:ex2_result_single_denorm_round_add_num[52:0] = 53'h80000000000; //-140 -13
13'h1f73:ex2_result_single_denorm_round_add_num[52:0] = 53'h100000000000; // -141 -14
13'h1f72:ex2_result_single_denorm_round_add_num[52:0] = 53'h200000000000;//-142 -15
13'h1f71:ex2_result_single_denorm_round_add_num[52:0] = 53'h400000000000;//-143 -16
13'h1f70:ex2_result_single_denorm_round_add_num[52:0] = 53'h800000000000; //-144 -17
13'h1f6f:ex2_result_single_denorm_round_add_num[52:0] = 53'h1000000000000; //-145 -18
13'h1f6e:ex2_result_single_denorm_round_add_num[52:0] = 53'h2000000000000; //-146 -19
13'h1f6d:ex2_result_single_denorm_round_add_num[52:0] = 53'h4000000000000; //-147 -20
13'h1f6c:ex2_result_single_denorm_round_add_num[52:0] = 53'h8000000000000; //-148 -21
13'h1f6b:ex2_result_single_denorm_round_add_num[52:0] = 53'h10000000000000; //-148 -22
default: ex2_result_single_denorm_round_add_num[52:0] = 53'h0; // -23
endcase
// &CombEnd; @232
end
// &CombBeg; @233
always @( vfdsu_ex2_expnt_rst[12:0])
begin
case(vfdsu_ex2_expnt_rst[12:0])
13'h1ff2:ex2_result_half_denorm_round_add_num[52:0] = 53'h40000000000; //-14 1
13'h1ff1:ex2_result_half_denorm_round_add_num[52:0] = 53'h80000000000; //-15 0
13'h1ff0:ex2_result_half_denorm_round_add_num[52:0] = 53'h100000000000; //-16 -1
13'h1fef:ex2_result_half_denorm_round_add_num[52:0] = 53'h200000000000; //-17 -2
13'h1fee:ex2_result_half_denorm_round_add_num[52:0] = 53'h400000000000; //-18 -3
13'h1fed:ex2_result_half_denorm_round_add_num[52:0] = 53'h800000000000; //-19 -4
13'h1fec:ex2_result_half_denorm_round_add_num[52:0] = 53'h1000000000000; //-20 -5
13'h1feb:ex2_result_half_denorm_round_add_num[52:0] = 53'h2000000000000; //-21 -6
13'h1fea:ex2_result_half_denorm_round_add_num[52:0] = 53'h4000000000000; //-22 -7
13'h1fe9:ex2_result_half_denorm_round_add_num[52:0] = 53'h8000000000000; //-23 -8
13'h1fe8:ex2_result_half_denorm_round_add_num[52:0] = 53'h10000000000000; //-24 -9
default: ex2_result_half_denorm_round_add_num[52:0] = 53'h0; // -23
endcase
// &CombEnd; @248
end
//===================special result========================
assign ex2_result_zero = vfdsu_ex2_result_zero;
assign ex2_result_qnan = vfdsu_ex2_result_qnan;
assign ex2_result_inf = vfdsu_ex2_result_inf ||
ex2_of_plus && !vfdsu_ex2_of_rm_lfn;
assign ex2_result_lfn =
ex2_of_plus && vfdsu_ex2_of_rm_lfn;
//====================Pipe to EX3===========================
//gate clk
// &Instance("gated_clk_cell","x_ex2_pipe_clk"); @262
gated_clk_cell x_ex2_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_pipe_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @263
// .clk_out (ex2_pipe_clk),//Out Clock @264
// .external_en (1'b0), @265
// .global_en (cp0_yy_clk_en), @266
// .local_en (ex2_pipe_clk_en),//Local Condition @267
// .module_en (cp0_vfpu_icg_en) @268
// ); @269
assign ex2_pipe_clk_en = ex2_pipedown;
always @(posedge ex2_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
vfdsu_ex3_result_zero <= 1'b0;
vfdsu_ex3_result_qnan <= 1'b0;
vfdsu_ex3_result_inf <= 1'b0;
vfdsu_ex3_result_lfn <= 1'b0;
vfdsu_ex3_of <= 1'b0;
vfdsu_ex3_uf <= 1'b0;
vfdsu_ex3_nv <= 1'b0;
vfdsu_ex3_dz <= 1'b0;
vfdsu_ex3_potnt_of <= 1'b0;
vfdsu_ex3_potnt_uf <= 1'b0;
vfdsu_ex3_rem_sign <= 1'b0;
// vfdsu_ex3_rem_zero <= 1'b0;
vfdsu_ex3_doub_expnt_rst[12:0] <= 13'b0;
vfdsu_ex3_sing_expnt_rst[8:0] <= 9'b0;
vfdsu_ex3_half_expnt_rst[12:0] <= 13'b0;
vfdsu_ex3_result_sign <= 1'b0;
vfdsu_ex3_qnan_sign <= 1'b0;
vfdsu_ex3_qnan_f[51:0] <= 52'b0;
vfdsu_ex3_rm[2:0] <= 3'b0;
vfdsu_ex3_result_denorm_round_add_num[52:0]
<= 53'b0;
vfdsu_ex3_rslt_denorm <= 1'b0;
vfdsu_ex3_id_srt_skip <= 1'b0;
vfdsu_ex3_double <= 1'b0;
vfdsu_ex3_single <= 1'b0;
end
else if(ex2_pipedown)
begin
vfdsu_ex3_result_zero <= ex2_result_zero;
vfdsu_ex3_result_qnan <= ex2_result_qnan;
vfdsu_ex3_result_inf <= ex2_result_inf;
vfdsu_ex3_result_lfn <= ex2_result_lfn;
vfdsu_ex3_of <= ex2_of;
vfdsu_ex3_uf <= ex2_uf;
vfdsu_ex3_nv <= vfdsu_ex2_nv;
vfdsu_ex3_dz <= vfdsu_ex2_dz;
vfdsu_ex3_potnt_of <= ex2_potnt_of;
vfdsu_ex3_potnt_uf <= ex2_potnt_uf;
vfdsu_ex3_rem_sign <= srt_remainder_sign;
//vfdsu_ex3_rem_zero <= srt_remainder_zero;
vfdsu_ex3_doub_expnt_rst[12:0] <= vfdsu_ex2_expnt_rst[12:0];
vfdsu_ex3_sing_expnt_rst[8:0] <= vfdsu_ex2_expnt_rst[8:0];
vfdsu_ex3_half_expnt_rst[12:0] <= vfdsu_ex2_expnt_rst[12:0];
vfdsu_ex3_result_sign <= vfdsu_ex2_result_sign;
vfdsu_ex3_qnan_sign <= vfdsu_ex2_qnan_sign;
vfdsu_ex3_qnan_f[51:0] <= vfdsu_ex2_qnan_f[51:0];
vfdsu_ex3_rm[2:0] <= vfdsu_ex2_rm[2:0];
vfdsu_ex3_result_denorm_round_add_num[52:0]
<= ex2_result_denorm_round_add_num[52:0];
vfdsu_ex3_rslt_denorm <= ex2_rslt_denorm;
vfdsu_ex3_id_srt_skip <= ex2_id_nor_srt_skip;
vfdsu_ex3_double <= vfdsu_ex2_double;
vfdsu_ex3_single <= vfdsu_ex2_single;
end
else
begin
vfdsu_ex3_result_zero <= vfdsu_ex3_result_zero;
vfdsu_ex3_result_qnan <= vfdsu_ex3_result_qnan;
vfdsu_ex3_result_inf <= vfdsu_ex3_result_inf;
vfdsu_ex3_result_lfn <= vfdsu_ex3_result_lfn;
vfdsu_ex3_of <= vfdsu_ex3_of;
vfdsu_ex3_uf <= vfdsu_ex3_uf;
vfdsu_ex3_nv <= vfdsu_ex3_nv;
vfdsu_ex3_dz <= vfdsu_ex3_dz;
vfdsu_ex3_potnt_of <= vfdsu_ex3_potnt_of;
vfdsu_ex3_potnt_uf <= vfdsu_ex3_potnt_uf;
vfdsu_ex3_rem_sign <= vfdsu_ex3_rem_sign;
//vfdsu_ex3_rem_zero <= vfdsu_ex3_rem_zero;
vfdsu_ex3_doub_expnt_rst[12:0] <= vfdsu_ex3_doub_expnt_rst[12:0];
vfdsu_ex3_sing_expnt_rst[8:0] <= vfdsu_ex3_sing_expnt_rst[8:0];
vfdsu_ex3_half_expnt_rst[12:0] <= vfdsu_ex3_half_expnt_rst[12:0];
vfdsu_ex3_result_sign <= vfdsu_ex3_result_sign;
vfdsu_ex3_qnan_sign <= vfdsu_ex3_qnan_sign;
vfdsu_ex3_qnan_f[51:0] <= vfdsu_ex3_qnan_f[51:0];
vfdsu_ex3_rm[2:0] <= vfdsu_ex3_rm[2:0];
vfdsu_ex3_result_denorm_round_add_num[52:0]
<= vfdsu_ex3_result_denorm_round_add_num[52:0];
vfdsu_ex3_rslt_denorm <= vfdsu_ex3_rslt_denorm;
vfdsu_ex3_id_srt_skip <= vfdsu_ex3_id_srt_skip;
vfdsu_ex3_double <= vfdsu_ex3_double;
vfdsu_ex3_single <= vfdsu_ex3_single;
end
end
assign vfdsu_ex3_rem_zero = ~|srt_remainder[60:0];
assign srt_ctrl_rem_zero = vfdsu_ex3_rem_zero;
// &Force("output","vfdsu_ex3_potnt_of"); @365
// &Force("output","vfdsu_ex3_potnt_uf"); @366
// &Force("output","vfdsu_ex3_rem_sign"); @367
// &Force("output","vfdsu_ex3_rem_zero"); @368
// &Force("output","vfdsu_ex3_result_zero"); @369
// &Force("output","vfdsu_ex3_result_qnan"); @370
// &Force("output","vfdsu_ex3_result_inf"); @371
// &Force("output","vfdsu_ex3_result_lfn"); @372
// &Force("output","vfdsu_ex3_dz"); @373
// &Force("output","vfdsu_ex3_nv"); @374
// &Force("output","vfdsu_ex3_of"); @375
// &Force("output","vfdsu_ex3_uf"); @376
// &Force("output","vfdsu_ex3_result_sign"); @377
// &Force("output","vfdsu_ex3_doub_expnt_rst"); @378
// &Force("output","vfdsu_ex3_sing_expnt_rst"); @379
// &Force("output","vfdsu_ex3_half_expnt_rst"); @380
// &Force("output","vfdsu_ex3_qnan_sign"); @381
// &Force("output","vfdsu_ex3_qnan_f"); @382
// &Force("output","vfdsu_ex3_rm"); @383
// &Force("output","vfdsu_ex3_result_denorm_round_add_num"); @384
// &Force("output","vfdsu_ex3_rslt_denorm"); @385
// &Force("output","vfdsu_ex3_id_srt_skip"); @386
// &Force("output","vfdsu_ex3_single"); @387
// &Force("output","vfdsu_ex3_double"); @388
//==========================================================
// SRT Remainder & Divisor for Quotient/Root Generate
//==========================================================
// &Instance("ct_vfdsu_srt_radix16_with_sqrt_for_vdsp"); @411
// &Connect(.srt_sm_on (srt_sm_on_all)); @412
// &Force("bus","ex1_remainder",59,0); @414
// &Force("bus","srt_remainder_out",69,0); @415
// &Force("nonport","srt_remainder_out"); @422
// &Force("nonport","vdiv_qt_rt"); @423
assign initial_divisor_in[55:0] = {ex1_divisor[52:0],3'b000};
assign initial_remainder_in[60:0] = {2'b00,ex1_remainder[59:1]};
assign initial_bound_sel_in[6:0] = ex1_div ? initial_divisor_in[55:49]:{7{1'b0}};
assign initial_srt_en = ex1_pipedown;
assign initial_srt_sel_div_in = ex1_div;
assign initial_srt_sel_sqrt_in = ex1_sqrt;
assign srt_first_round = ex2_srt_first_round;
// &Instance("ct_vfdsu_srt_radix16_with_sqrt"); @436
ct_vfdsu_srt_radix16_with_sqrt x_ct_vfdsu_srt_radix16_with_sqrt (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.initial_bound_sel_in (initial_bound_sel_in ),
.initial_divisor_in (initial_divisor_in ),
.initial_remainder_in (initial_remainder_in ),
.initial_srt_en (initial_srt_en ),
.initial_srt_sel_div_in (initial_srt_sel_div_in ),
.initial_srt_sel_sqrt_in (initial_srt_sel_sqrt_in),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.srt_first_round (srt_first_round ),
.srt_remainder (srt_remainder ),
.srt_remainder_out (srt_remainder_out ),
.srt_remainder_sign (srt_remainder_sign ),
.srt_secd_round (srt_secd_round ),
.srt_sm_on (srt_sm_on ),
.total_qt_rt (total_qt_rt ),
.vdiv_qt_rt (vdiv_qt_rt )
);
// &Force("bus","ex1_remainder",59,0); @438
assign total_qt_rt_58[57:0] = {total_qt_rt[57:2],2'b00};
// &ModuleEnd; @443
endmodule |
module ct_vfdsu_top(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfdsu_ex1_pipex_dst_ereg,
dp_vfdsu_ex1_pipex_dst_vreg,
dp_vfdsu_ex1_pipex_iid,
dp_vfdsu_ex1_pipex_imm0,
dp_vfdsu_ex1_pipex_sel,
dp_vfdsu_ex1_pipex_srcf0,
dp_vfdsu_ex1_pipex_srcf1,
dp_vfdsu_fdiv_gateclk_issue,
dp_vfdsu_idu_fdiv_issue,
forever_cpuclk,
idu_vfpu_rf_pipex_func,
idu_vfpu_rf_pipex_gateclk_sel,
pad_yy_icg_scan_en,
pipex_dp_vfdsu_ereg,
pipex_dp_vfdsu_ereg_data,
pipex_dp_vfdsu_freg_data,
pipex_dp_vfdsu_inst_vld,
pipex_dp_vfdsu_vreg,
rtu_yy_xx_flush,
vfdsu_dp_fdiv_busy,
vfdsu_dp_inst_wb_req,
vfdsu_ifu_debug_ex2_wait,
vfdsu_ifu_debug_idle,
vfdsu_ifu_debug_pipe_busy,
vfpu_yy_xx_dqnan,
vfpu_yy_xx_rm
);
// &Ports; @24
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [4 :0] dp_vfdsu_ex1_pipex_dst_ereg;
input [6 :0] dp_vfdsu_ex1_pipex_dst_vreg;
input [6 :0] dp_vfdsu_ex1_pipex_iid;
input [2 :0] dp_vfdsu_ex1_pipex_imm0;
input dp_vfdsu_ex1_pipex_sel;
input [63:0] dp_vfdsu_ex1_pipex_srcf0;
input [63:0] dp_vfdsu_ex1_pipex_srcf1;
input dp_vfdsu_fdiv_gateclk_issue;
input dp_vfdsu_idu_fdiv_issue;
input forever_cpuclk;
input [19:0] idu_vfpu_rf_pipex_func;
input idu_vfpu_rf_pipex_gateclk_sel;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
input vfpu_yy_xx_dqnan;
input [2 :0] vfpu_yy_xx_rm;
output [4 :0] pipex_dp_vfdsu_ereg;
output [4 :0] pipex_dp_vfdsu_ereg_data;
output [63:0] pipex_dp_vfdsu_freg_data;
output pipex_dp_vfdsu_inst_vld;
output [6 :0] pipex_dp_vfdsu_vreg;
output vfdsu_dp_fdiv_busy;
output vfdsu_dp_inst_wb_req;
output vfdsu_ifu_debug_ex2_wait;
output vfdsu_ifu_debug_idle;
output vfdsu_ifu_debug_pipe_busy;
// &Regs; @25
// &Wires; @26
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [4 :0] dp_vfdsu_ex1_pipex_dst_ereg;
wire [6 :0] dp_vfdsu_ex1_pipex_dst_vreg;
wire [6 :0] dp_vfdsu_ex1_pipex_iid;
wire [2 :0] dp_vfdsu_ex1_pipex_imm0;
wire dp_vfdsu_ex1_pipex_sel;
wire [63:0] dp_vfdsu_ex1_pipex_srcf0;
wire [63:0] dp_vfdsu_ex1_pipex_srcf1;
wire dp_vfdsu_fdiv_gateclk_issue;
wire dp_vfdsu_idu_fdiv_issue;
wire ex1_data_clk;
wire ex1_div;
wire ex1_double;
wire ex1_pipedown;
wire ex1_scalar;
wire ex1_single;
wire ex1_sqrt;
wire [63:0] ex1_src0;
wire [63:0] ex1_src1;
wire [2 :0] ex1_static_rm;
wire ex2_data_clk;
wire ex2_pipedown;
wire ex2_srt_first_round;
wire ex3_data_clk;
wire ex3_pipedown;
wire [4 :0] ex4_out_expt;
wire [63:0] ex4_out_result;
wire forever_cpuclk;
wire [19:0] idu_vfpu_rf_pipex_func;
wire idu_vfpu_rf_pipex_gateclk_sel;
wire pad_yy_icg_scan_en;
wire [4 :0] pipex_dp_vfdsu_ereg;
wire [4 :0] pipex_dp_vfdsu_ereg_data;
wire [63:0] pipex_dp_vfdsu_freg_data;
wire pipex_dp_vfdsu_inst_vld;
wire [6 :0] pipex_dp_vfdsu_vreg;
wire rtu_yy_xx_flush;
wire srt_ctrl_rem_zero;
wire srt_ctrl_skip_srt;
wire srt_secd_round;
wire srt_sm_on;
wire vfdsu_dp_fdiv_busy;
wire vfdsu_dp_inst_wb_req;
wire vfdsu_ex2_double;
wire vfdsu_ex2_single;
wire vfdsu_ifu_debug_ex2_wait;
wire vfdsu_ifu_debug_idle;
wire vfdsu_ifu_debug_pipe_busy;
wire vfpu_yy_xx_dqnan;
wire [2 :0] vfpu_yy_xx_rm;
// &Instance("ct_vfdsu_ctrl"); @28
// &Instance("ct_vfdsu_dp"); @29
// &ConnRule(s/ex4_out/set0_doub_ex4/); @30
// &ConnRule(s/srt_ctrl/set0_doub_srt_ctrl/); @31
// &ConnRule(s/vfdsu_ex2_/dp_set0_double_ex2_/); @32
// &ConnRule(s/slice_x/slice_0/); @33
// &ConnRule(s/vfdsu_ex3_/dp_set0_double_ex3_/); @34
// &ConnRule(s/vfdsu_ex4_/dp_set0_double_ex4_/); @35
// &Instance("ct_vfdsu_double","x_ct_vfdsu_double_set0"); @36
// &Connect(.ex1_src0(ex1_src0[63:0])); @37
// &Connect(.ex1_src1(ex1_src1[63:0])); @38
// &Connect(.ex1_double(set0_ex1_double)); @39
// &Connect(.srt_secd_round(srt_secd_round[0])); @40
// &Connect(.ex2_srt_first_round(ex2_srt_first_round[0])); @41
// &ConnRule(s/ex4_out/set0_half0_ex4/); @43
// &ConnRule(s/_pipedown/_half_pipedown/); @44
// &ConnRule(s/srt_ctrl/set0_half0_srt_ctrl/); @45
// &ConnRule(s/vfdsu_ex2_/dp_set0_half0_ex2_/); @46
// &ConnRule(s/vfdsu_ex3_/dp_set0_half0_ex3_/); @47
// &ConnRule(s/vfdsu_ex4_/dp_set0_half0_ex4_/); @48
// &Instance("ct_vfdsu_half","x_ct_vfdsu_half0_set0"); @49
// &Connect(.ex1_src0(ex1_src0[31:16])); @50
// &Connect(.ex1_src1(ex1_src1[31:16])); @51
// &Connect(.srt_secd_round(srt_secd_round[1])); @52
// &Connect(.ex2_srt_first_round(ex2_srt_first_round[1])); @53
// &ConnRule(s/ex4_out/set0_sing_ex4/); @56
// &ConnRule(s/_pipedown/_sing_pipedown/); @57
// &ConnRule(s/srt_ctrl/set0_sing_srt_ctrl/); @58
// &ConnRule(s/slice_x/slice_0/); @59
// &Instance("ct_vfdsu_single","x_ct_vfdsu_single_set0"); @60
// &Connect(.ex1_src0(ex1_src0[63:32])); @61
// &Connect(.ex1_src1(ex1_src1[63:32])); @62
// &Connect(.srt_secd_round(srt_secd_round[1])); @63
// &Connect(.ex2_srt_first_round(ex2_srt_first_round[1])); @64
// &ConnRule(s/ex4_out/set0_half1_ex4/); @68
// &ConnRule(s/_pipedown/_half_pipedown/); @69
// &ConnRule(s/srt_ctrl/set0_half1_srt_ctrl/); @70
// &ConnRule(s/vfdsu_ex2_/dp_set0_half1_ex2_/); @71
// &ConnRule(s/vfdsu_ex3_/dp_set0_half1_ex3_/); @72
// &ConnRule(s/vfdsu_ex4_/dp_set0_half1_ex4_/); @73
// &Instance("ct_vfdsu_half","x_ct_vfdsu_half1_set0"); @74
// &Connect(.ex1_src0(ex1_src0[63:48])); @75
// &Connect(.ex1_src1(ex1_src1[63:48])); @76
// &Connect(.srt_secd_round(srt_secd_round[1])); @77
// &Connect(.ex2_srt_first_round(ex2_srt_first_round[1])); @78
// &ConnRule(s/ex4_out/set1_doub_ex4/); @81
// &ConnRule(s/srt_ctrl/set1_doub_srt_ctrl/); @82
// &ConnRule(s/vfdsu_ex2_/dp_set1_double_ex2_/); @83
// &ConnRule(s/slice_x/slice_1/); @84
// &ConnRule(s/vfdsu_ex3_/dp_set1_double_ex3_/); @85
// &ConnRule(s/vfdsu_ex4_/dp_set1_double_ex4_/); @86
// &Instance("ct_vfdsu_double","x_ct_vfdsu_double_set1"); @87
// &Connect(.ex1_src0(ex1_src0[127:64])); @88
// &Connect(.ex1_src1(ex1_src1[127:64])); @89
// &Connect(.ex1_double(set1_ex1_double)); @90
// &Connect(.srt_secd_round(srt_secd_round[2])); @91
// &Connect(.ex2_srt_first_round(ex2_srt_first_round[2])); @92
// &ConnRule(s/ex4_out/set1_half0_ex4/); @95
// &ConnRule(s/_pipedown/_half_pipedown/); @96
// &ConnRule(s/srt_ctrl/set1_half0_srt_ctrl/); @97
// &ConnRule(s/vfdsu_ex2_/dp_set1_half0_ex2_/); @98
// &ConnRule(s/vfdsu_ex3_/dp_set1_half0_ex3_/); @99
// &ConnRule(s/vfdsu_ex4_/dp_set1_half0_ex4_/); @100
// &Instance("ct_vfdsu_half","x_ct_vfdsu_half0_set1"); @101
// &Connect(.ex1_src0(ex1_src0[95:80])); @102
// &Connect(.ex1_src1(ex1_src1[95:80])); @103
// &Connect(.srt_secd_round(srt_secd_round[3])); @104
// &Connect(.ex2_srt_first_round(ex2_srt_first_round[3])); @105
// &ConnRule(s/ex4_out/set1_sing_ex4/); @108
// &ConnRule(s/_pipedown/_sing_pipedown/); @109
// &ConnRule(s/srt_ctrl/set1_sing_srt_ctrl/); @110
// &ConnRule(s/slice_x/slice_1/); @111
// &Instance("ct_vfdsu_single","x_ct_vfdsu_single_set1"); @112
// &Connect(.ex1_src0(ex1_src0[127:96])); @113
// &Connect(.ex1_src1(ex1_src1[127:96])); @114
// &Connect(.srt_secd_round(srt_secd_round[3])); @115
// &Connect(.ex2_srt_first_round(ex2_srt_first_round[3])); @116
// &ConnRule(s/ex4_out/set1_half1_ex4/); @119
// &ConnRule(s/_pipedown/_half_pipedown/); @120
// &ConnRule(s/srt_ctrl/set1_half1_srt_ctrl/); @121
// &ConnRule(s/vfdsu_ex2_/dp_set1_half1_ex2_/); @122
// &ConnRule(s/vfdsu_ex3_/dp_set1_half1_ex3_/); @123
// &ConnRule(s/vfdsu_ex4_/dp_set1_half1_ex4_/); @124
// &Instance("ct_vfdsu_half","x_ct_vfdsu_half1_set1"); @125
// &Connect(.ex1_src0(ex1_src0[127:112])); @126
// &Connect(.ex1_src1(ex1_src1[127:112])); @127
// &Connect(.srt_secd_round(srt_secd_round[3])); @128
// &Connect(.ex2_srt_first_round(ex2_srt_first_round[3])); @129
// &Instance("ct_vfdsu_ctrl"); @132
ct_vfdsu_ctrl x_ct_vfdsu_ctrl (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfdsu_ex1_pipex_sel (dp_vfdsu_ex1_pipex_sel ),
.dp_vfdsu_fdiv_gateclk_issue (dp_vfdsu_fdiv_gateclk_issue),
.dp_vfdsu_idu_fdiv_issue (dp_vfdsu_idu_fdiv_issue ),
.ex1_data_clk (ex1_data_clk ),
.ex1_double (ex1_double ),
.ex1_pipedown (ex1_pipedown ),
.ex1_single (ex1_single ),
.ex2_data_clk (ex2_data_clk ),
.ex2_pipedown (ex2_pipedown ),
.ex2_srt_first_round (ex2_srt_first_round ),
.ex3_data_clk (ex3_data_clk ),
.ex3_pipedown (ex3_pipedown ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pipex_dp_vfdsu_inst_vld (pipex_dp_vfdsu_inst_vld ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.srt_ctrl_rem_zero (srt_ctrl_rem_zero ),
.srt_ctrl_skip_srt (srt_ctrl_skip_srt ),
.srt_secd_round (srt_secd_round ),
.srt_sm_on (srt_sm_on ),
.vfdsu_dp_fdiv_busy (vfdsu_dp_fdiv_busy ),
.vfdsu_dp_inst_wb_req (vfdsu_dp_inst_wb_req ),
.vfdsu_ex2_double (vfdsu_ex2_double ),
.vfdsu_ex2_single (vfdsu_ex2_single ),
.vfdsu_ifu_debug_ex2_wait (vfdsu_ifu_debug_ex2_wait ),
.vfdsu_ifu_debug_idle (vfdsu_ifu_debug_idle ),
.vfdsu_ifu_debug_pipe_busy (vfdsu_ifu_debug_pipe_busy )
);
// &Instance("ct_vfdsu_double"); @133
ct_vfdsu_double x_ct_vfdsu_double (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ex1_div (ex1_div ),
.ex1_double (ex1_double ),
.ex1_pipedown (ex1_pipedown ),
.ex1_scalar (ex1_scalar ),
.ex1_single (ex1_single ),
.ex1_sqrt (ex1_sqrt ),
.ex1_src0 (ex1_src0 ),
.ex1_src1 (ex1_src1 ),
.ex1_static_rm (ex1_static_rm ),
.ex2_pipedown (ex2_pipedown ),
.ex2_srt_first_round (ex2_srt_first_round),
.ex3_pipedown (ex3_pipedown ),
.ex4_out_expt (ex4_out_expt ),
.ex4_out_result (ex4_out_result ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.srt_ctrl_rem_zero (srt_ctrl_rem_zero ),
.srt_ctrl_skip_srt (srt_ctrl_skip_srt ),
.srt_secd_round (srt_secd_round ),
.srt_sm_on (srt_sm_on ),
.vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan ),
.vfpu_yy_xx_rm (vfpu_yy_xx_rm )
);
// &Instance("ct_vfdsu_scalar_dp"); @134
ct_vfdsu_scalar_dp x_ct_vfdsu_scalar_dp (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfdsu_ex1_pipex_dst_ereg (dp_vfdsu_ex1_pipex_dst_ereg ),
.dp_vfdsu_ex1_pipex_dst_vreg (dp_vfdsu_ex1_pipex_dst_vreg ),
.dp_vfdsu_ex1_pipex_iid (dp_vfdsu_ex1_pipex_iid ),
.dp_vfdsu_ex1_pipex_imm0 (dp_vfdsu_ex1_pipex_imm0 ),
.dp_vfdsu_ex1_pipex_srcf0 (dp_vfdsu_ex1_pipex_srcf0 ),
.dp_vfdsu_ex1_pipex_srcf1 (dp_vfdsu_ex1_pipex_srcf1 ),
.ex1_data_clk (ex1_data_clk ),
.ex1_div (ex1_div ),
.ex1_double (ex1_double ),
.ex1_pipedown (ex1_pipedown ),
.ex1_scalar (ex1_scalar ),
.ex1_single (ex1_single ),
.ex1_sqrt (ex1_sqrt ),
.ex1_src0 (ex1_src0 ),
.ex1_src1 (ex1_src1 ),
.ex1_static_rm (ex1_static_rm ),
.ex2_data_clk (ex2_data_clk ),
.ex2_pipedown (ex2_pipedown ),
.ex3_data_clk (ex3_data_clk ),
.ex3_pipedown (ex3_pipedown ),
.ex4_out_expt (ex4_out_expt ),
.ex4_out_result (ex4_out_result ),
.forever_cpuclk (forever_cpuclk ),
.idu_vfpu_rf_pipex_func (idu_vfpu_rf_pipex_func ),
.idu_vfpu_rf_pipex_gateclk_sel (idu_vfpu_rf_pipex_gateclk_sel),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pipex_dp_vfdsu_ereg (pipex_dp_vfdsu_ereg ),
.pipex_dp_vfdsu_ereg_data (pipex_dp_vfdsu_ereg_data ),
.pipex_dp_vfdsu_freg_data (pipex_dp_vfdsu_freg_data ),
.pipex_dp_vfdsu_vreg (pipex_dp_vfdsu_vreg ),
.vfdsu_ex2_double (vfdsu_ex2_double ),
.vfdsu_ex2_single (vfdsu_ex2_single )
);
// &ModuleEnd; @137
endmodule |
module ct_rst_top(
forever_coreclk,
fpu_rst_b,
had_rst_b,
idu_rst_b,
ifu_rst_b,
lsu_rst_b,
mmu_rst_b,
pad_core_rst_b,
pad_cpu_rst_b,
pad_yy_mbist_mode,
pad_yy_scan_mode,
pad_yy_scan_rst_b
);
// &Ports; @23
input forever_coreclk;
input pad_core_rst_b;
input pad_cpu_rst_b;
input pad_yy_mbist_mode;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
output fpu_rst_b;
output had_rst_b;
output idu_rst_b;
output ifu_rst_b;
output lsu_rst_b;
output mmu_rst_b;
// &Regs; @24
reg core_rst_ff_1st;
reg core_rst_ff_2nd;
reg core_rst_ff_3rd;
reg fpurst_b;
reg hadrst_b;
reg idurst_b;
reg ifurst_b;
reg lsurst_b;
reg mmurst_b;
// &Wires; @25
wire async_corerst_b;
wire corerst_b;
wire forever_coreclk;
wire fpu_rst_b;
wire had_rst_b;
wire idu_rst_b;
wire ifu_rst_b;
wire lsu_rst_b;
wire mmu_rst_b;
wire pad_core_rst_b;
wire pad_cpu_rst_b;
wire pad_yy_mbist_mode;
wire pad_yy_scan_mode;
wire pad_yy_scan_rst_b;
//==============================================================================
//cpu reset
//==============================================================================
assign async_corerst_b = pad_core_rst_b & pad_cpu_rst_b & !pad_yy_mbist_mode;
always @(posedge forever_coreclk or negedge async_corerst_b)
begin
if(!async_corerst_b)
begin
core_rst_ff_1st <= 1'b0;
core_rst_ff_2nd <= 1'b0;
core_rst_ff_3rd <= 1'b0;
end
else
begin
core_rst_ff_1st <= 1'b1;
core_rst_ff_2nd <= core_rst_ff_1st;
core_rst_ff_3rd <= core_rst_ff_2nd;
end
end
assign corerst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : core_rst_ff_3rd;
always @(posedge forever_coreclk or negedge corerst_b)
begin
if (!corerst_b)
ifurst_b <= 1'b0;
else
ifurst_b <= corerst_b;
end
assign ifu_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : ifurst_b;
always @(posedge forever_coreclk or negedge corerst_b)
begin
if (!corerst_b)
idurst_b <= 1'b0;
else
idurst_b <= corerst_b;
end
assign idu_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : idurst_b;
always @(posedge forever_coreclk or negedge corerst_b)
begin
if (!corerst_b)
lsurst_b <= 1'b0;
else
lsurst_b <= corerst_b;
end
assign lsu_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : lsurst_b;
always @(posedge forever_coreclk or negedge corerst_b)
begin
if (!corerst_b)
fpurst_b <= 1'b0;
else
fpurst_b <= corerst_b;
end
assign fpu_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : fpurst_b;
always @(posedge forever_coreclk or negedge corerst_b)
begin
if (!corerst_b)
mmurst_b <= 1'b0;
else
mmurst_b <= corerst_b;
end
assign mmu_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : mmurst_b;
always @(posedge forever_coreclk or negedge corerst_b)
begin
if (!corerst_b)
hadrst_b <= 1'b0;
else
hadrst_b <= corerst_b;
end
assign had_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : hadrst_b;
// &ModuleEnd; @110
endmodule |
module ct_mp_rst_top(
apbrst_b,
core0_fifo_rst_b,
core0_rst_b,
core1_fifo_rst_b,
core1_rst_b,
cpurst_b,
forever_cpuclk,
forever_jtgclk,
pad_core0_rst_b,
pad_core1_rst_b,
pad_cpu_rst_b,
pad_had_jtg_trst_b,
pad_yy_dft_clk_rst_b,
pad_yy_mbist_mode,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
phl_rst_b,
trst_b
);
// &Ports; @23
input forever_cpuclk;
input forever_jtgclk;
input pad_core0_rst_b;
input pad_core1_rst_b;
input pad_cpu_rst_b;
input pad_had_jtg_trst_b;
input pad_yy_dft_clk_rst_b;
input pad_yy_mbist_mode;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
output apbrst_b;
output core0_fifo_rst_b;
output core0_rst_b;
output core1_fifo_rst_b;
output core1_rst_b;
output cpurst_b;
output phl_rst_b;
output trst_b;
// &Regs; @24
reg core0_rst_1ff;
reg core0_rst_2ff;
reg core0_rst_3ff;
reg core1_rst_1ff;
reg core1_rst_2ff;
reg core1_rst_3ff;
reg cpurst_1ff;
reg cpurst_2ff;
reg cpurst_3ff;
reg cpurst_jtg_1ff;
reg cpurst_jtg_2ff;
reg cpurst_jtg_3ff;
reg trst_1ff;
reg trst_2ff;
reg trst_3ff;
// &Wires; @25
wire apbrst_b;
wire async_core0_rst_b;
wire async_core1_rst_b;
wire async_cpurst_b;
wire async_trst_b;
wire core0_fifo_rst_b;
wire core0_rst_b;
wire core1_fifo_rst_b;
wire core1_rst_b;
wire cpurst_b;
wire forever_cpuclk;
wire forever_jtgclk;
wire pad_core0_rst_b;
wire pad_core1_rst_b;
wire pad_cpu_rst_b;
wire pad_had_jtg_trst_b;
wire pad_yy_dft_clk_rst_b;
wire pad_yy_mbist_mode;
wire pad_yy_scan_mode;
wire pad_yy_scan_rst_b;
wire phl_rst_b;
wire trst_b;
//=============================================================================
//cpu reset
//=============================================================================
// &Force("output", "cpurst_b"); @30
assign async_cpurst_b = pad_cpu_rst_b & !pad_yy_mbist_mode;
always @(posedge forever_cpuclk or negedge async_cpurst_b)
begin
if (!async_cpurst_b)
begin
cpurst_1ff <= 1'b0;
cpurst_2ff <= 1'b0;
cpurst_3ff <= 1'b0;
end
else
begin
cpurst_1ff <= 1'b1;
cpurst_2ff <= cpurst_1ff;
cpurst_3ff <= cpurst_2ff;
end
end
assign cpurst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : cpurst_3ff;
//=============================================================================
// Core reset
//=============================================================================
assign async_core0_rst_b = pad_core0_rst_b & !pad_yy_mbist_mode;
always @(posedge forever_cpuclk or negedge async_core0_rst_b)
begin
if (!async_core0_rst_b)
begin
core0_rst_1ff <= 1'b0;
core0_rst_2ff <= 1'b0;
core0_rst_3ff <= 1'b0;
end
else
begin
core0_rst_1ff <= 1'b1;
core0_rst_2ff <= core0_rst_1ff;
core0_rst_3ff <= core0_rst_2ff;
end
end
assign core0_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : core0_rst_3ff;
assign core0_fifo_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : (core0_rst_3ff & cpurst_3ff);
assign async_core1_rst_b = pad_core1_rst_b & !pad_yy_mbist_mode;
always @(posedge forever_cpuclk or negedge async_core1_rst_b)
begin
if (!async_core1_rst_b)
begin
core1_rst_1ff <= 1'b0;
core1_rst_2ff <= 1'b0;
core1_rst_3ff <= 1'b0;
end
else
begin
core1_rst_1ff <= 1'b1;
core1_rst_2ff <= core1_rst_1ff;
core1_rst_3ff <= core1_rst_2ff;
end
end
assign core1_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : core1_rst_3ff;
assign core1_fifo_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : (core1_rst_3ff & cpurst_3ff);
//=============================================================================
// APB reset
//=============================================================================
assign apbrst_b = cpurst_b;
//=============================================================================
//reset for clkgen
//=============================================================================
assign phl_rst_b = pad_yy_scan_mode ? pad_yy_dft_clk_rst_b : cpurst_3ff;
//=============================================================================
//jtag reset
//=============================================================================
assign async_trst_b = pad_had_jtg_trst_b & !pad_yy_mbist_mode;
always @(posedge forever_jtgclk or negedge async_trst_b)
begin
if (!async_trst_b)
begin
trst_1ff <= 1'b0;
trst_2ff <= 1'b0;
trst_3ff <= 1'b0;
end
else
begin
trst_1ff <= 1'b1;
trst_2ff <= trst_1ff;
trst_3ff <= trst_2ff;
end
end
always @(posedge forever_jtgclk or negedge async_cpurst_b)
begin
if (!async_cpurst_b)
begin
cpurst_jtg_1ff <= 1'b0;
cpurst_jtg_2ff <= 1'b0;
cpurst_jtg_3ff <= 1'b0;
end
else
begin
cpurst_jtg_1ff <= 1'b1;
cpurst_jtg_2ff <= cpurst_jtg_1ff;
cpurst_jtg_3ff <= cpurst_jtg_2ff;
end
end
assign trst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : trst_3ff & cpurst_jtg_3ff;
// &ModuleEnd; @193
endmodule |
module ct_hpcp_event(
cp0_hpcp_icg_en,
cpurst_b,
eventx_clk_en,
eventx_value,
eventx_wen,
forever_cpuclk,
hpcp_wdata,
pad_yy_icg_scan_en
);
// &Ports; @23
input cp0_hpcp_icg_en;
input cpurst_b;
input eventx_clk_en;
input eventx_wen;
input forever_cpuclk;
input [63:0] hpcp_wdata;
input pad_yy_icg_scan_en;
output [63:0] eventx_value;
// &Regs; @24
reg [5 :0] value;
// &Wires @25
wire cp0_hpcp_icg_en;
wire cpurst_b;
wire eventx_clk;
wire eventx_clk_en;
wire [63:0] eventx_value;
wire eventx_wen;
wire forever_cpuclk;
wire [63:0] hpcp_wdata;
wire pad_yy_icg_scan_en;
wire value_mask;
//define total counter num
parameter HPMCNT_NUM = 42;
parameter HPMEVT_WIDTH = 6;
// &Force("bus","hpcp_wdata",63,0); @31
//==========================================================
// Instance of Gated Cell
//==========================================================
// &Instance("gated_clk_cell", "x_gated_clk"); @35
gated_clk_cell x_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (eventx_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (eventx_clk_en ),
.module_en (cp0_hpcp_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @36
// .external_en (1'b0), @37
// .global_en (1'b1), @38
// .module_en (cp0_hpcp_icg_en), @39
// .local_en (eventx_clk_en), @40
// .clk_out (eventx_clk)); @41
//==========================================================
// Implementation of counter
//==========================================================
always @(posedge eventx_clk or negedge cpurst_b)
begin
if(!cpurst_b)
value[HPMEVT_WIDTH-1:0] <= {HPMEVT_WIDTH{1'b0}};
else if(eventx_wen)
value[HPMEVT_WIDTH-1:0] <= hpcp_wdata[HPMEVT_WIDTH-1:0] & {HPMEVT_WIDTH{value_mask}} ;
else
value[HPMEVT_WIDTH-1:0] <= value[HPMEVT_WIDTH-1:0];
end
assign value_mask = (!(|hpcp_wdata[63:HPMEVT_WIDTH]))
&& (hpcp_wdata[HPMEVT_WIDTH-1:0] <= HPMCNT_NUM);
//output
assign eventx_value[63:0] = {{64-HPMEVT_WIDTH{1'b0}},value[HPMEVT_WIDTH-1:0]};
// &ModuleEnd; @62
endmodule |
module ct_hpcp_cnt(
cnt_adder,
cnt_clk_en,
cnt_en,
cnt_of,
cnt_value,
cnt_wen,
cp0_hpcp_icg_en,
cpurst_b,
forever_cpuclk,
hpcp_cnt_en,
hpcp_wdata,
pad_yy_icg_scan_en
);
// &Ports; @23
input [3 :0] cnt_adder;
input cnt_clk_en;
input cnt_en;
input cnt_wen;
input cp0_hpcp_icg_en;
input cpurst_b;
input forever_cpuclk;
input hpcp_cnt_en;
input [63:0] hpcp_wdata;
input pad_yy_icg_scan_en;
output cnt_of;
output [63:0] cnt_value;
// &Regs; @24
reg [3 :0] cnt_adder_ff;
reg cnt_en_ff;
reg cnt_overflow;
reg [63:0] counter;
// &Wires @25
wire clk_en;
wire [3 :0] cnt_adder;
wire cnt_clk;
wire cnt_clk_en;
wire cnt_en;
wire cnt_of;
wire [63:0] cnt_value;
wire cnt_wen;
wire [64:0] counter_adder;
wire cp0_hpcp_icg_en;
wire cpurst_b;
wire forever_cpuclk;
wire hpcp_cnt_en;
wire [63:0] hpcp_wdata;
wire pad_yy_icg_scan_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
// &Instance("gated_clk_cell", "x_gated_clk"); @30
gated_clk_cell x_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (cnt_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (clk_en ),
.module_en (cp0_hpcp_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @31
// .external_en (1'b0 ), @32
// .global_en (1'b1 ), @33
// .module_en (cp0_hpcp_icg_en), @34
// .local_en (clk_en ), @35
// .clk_out (cnt_clk )); @36
assign clk_en = cnt_clk_en || cnt_en_ff;
always @(posedge cnt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
cnt_en_ff <= 1'b0;
cnt_adder_ff[3:0] <= 4'b0;
end
else if(cnt_en)
begin
cnt_en_ff <= cnt_en;
cnt_adder_ff[3:0] <= cnt_adder[3:0];
end
else
begin
cnt_en_ff <= 1'b0;
cnt_adder_ff[3:0] <= cnt_adder_ff[3:0];
end
end
//==========================================================
// Implementation of counter
//==========================================================
always @(posedge cnt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
counter[63:0] <= 64'b0;
else if(cnt_wen)
counter[63:0] <= hpcp_wdata[63:0];
else if(cnt_en_ff && hpcp_cnt_en && (|cnt_adder_ff[3:0]))
counter[63:0] <= counter_adder[63:0];
else
counter[63:0] <= counter[63:0];
end
always @(posedge cnt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cnt_overflow <= 1'b0;
else if(cnt_overflow)
cnt_overflow <= 1'b0;
else if(cnt_en_ff && hpcp_cnt_en && (|cnt_adder_ff[3:0]))
cnt_overflow <= counter_adder[64];
else
cnt_overflow <= cnt_overflow;
end
assign counter_adder[64:0] = {1'b0,counter[63:0]} + {61'b0,cnt_adder_ff[3:0]};
//output
assign cnt_value[63:0] = counter[63:0];
assign cnt_of = cnt_overflow;
// &Force("input","cnt_dis"); @97
// &Force("input","cp0_yy_priv_mode"); @98
// &Force("nonport","counter_ff"); @99
// &ModuleEnd; @137
endmodule |
module ct_hpcp_cntinten_reg(
cntinten_wen_x,
cntinten_x,
cpurst_b,
hpcp_clk,
hpcp_wdata_x
);
// &Ports; @23
input cntinten_wen_x;
input cpurst_b;
input hpcp_clk;
input hpcp_wdata_x;
output cntinten_x;
// &Regs; @24
reg cntinten_x;
// &Wires @25
wire cntinten_wen_x;
wire cpurst_b;
wire hpcp_clk;
wire hpcp_wdata_x;
always @(posedge hpcp_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cntinten_x <= 1'b0;
else if(cntinten_wen_x)
cntinten_x <= hpcp_wdata_x;
else
cntinten_x <= cntinten_x;
end
// &Force("output","cntinten_x"); @37
// &ModuleEnd; @38
endmodule |
module ct_lsu_dcache_data_array(
data_din,
data_dout,
data_gateclk_en,
data_gwen_b,
data_idx,
data_sel_b,
data_wen_b,
forever_cpuclk,
pad_yy_icg_scan_en,
cp0_lsu_icg_en
);
input [31:0] data_din;
input data_gateclk_en;
input data_gwen_b;
input [10:0] data_idx;
input data_sel_b;
input [3 :0] data_wen_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input cp0_lsu_icg_en;
output [31:0] data_dout;
wire data_clk;
wire data_clk_en;
wire [31:0] data_din;
wire [31:0] data_dout;
wire data_gateclk_en;
wire data_gwen_b;
wire [10:0] data_idx;
wire data_sel_b;
wire [3 :0] data_wen_b;
wire [31:0] data_wen_b_all;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire cp0_lsu_icg_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign data_clk_en = data_gateclk_en;
// &Instance("gated_clk_cell", "x_dcache_data_gated_clk"); @100
gated_clk_cell x_dcache_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (data_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (data_clk_en ),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @101
// .external_en (1'b0 ), @102
// .global_en (1'b1 ), @103
// .module_en (cp0_lsu_icg_en ), @104
// .local_en (data_clk_en ), @105
// .clk_out (data_clk )); @106
//==========================================================
// Instance dcache array
//==========================================================
// &Force("bus","data_idx","10","0"); @112
assign data_wen_b_all[31:0] = {{8{data_wen_b[3]}},
{8{data_wen_b[2]}},
{8{data_wen_b[1]}},
{8{data_wen_b[0]}}};
//csky vperl_off
`ifdef DCACHE_32K
ct_spsram_1024x32 x_ct_spsram_1024x32 (
`ifdef MEM_CFG_IN
.mem_cfg_in (mem_cfg_in ),
`endif
.A (data_idx[9:0] ),
.CEN (data_sel_b ),
.CLK (data_clk ),
.D (data_din ),
.GWEN (data_gwen_b ),
.Q (data_dout ),
.WEN (data_wen_b_all)
);
`endif//DCACHE_32K
`ifdef DCACHE_64K
ct_spsram_2048x32 x_ct_spsram_2048x32 (
`ifdef MEM_CFG_IN
.mem_cfg_in (mem_cfg_in ),
`endif
.A (data_idx[10:0]),
.CEN (data_sel_b ),
.CLK (data_clk ),
.D (data_din ),
.GWEN (data_gwen_b ),
.Q (data_dout ),
.WEN (data_wen_b_all)
);
`endif//DCACHE_64K
//csky vperl_on
// &ModuleEnd; @192
endmodule |
module ct_lsu_dcache_info_update(
compare_dcwp_addr,
compare_dcwp_hit_idx,
compare_dcwp_sw_inst,
compare_dcwp_update_vld,
dcache_dirty_din,
dcache_dirty_gwen,
dcache_dirty_wen,
dcache_idx,
dcache_tag_din,
dcache_tag_gwen,
dcache_tag_wen,
origin_dcache_dirty,
origin_dcache_share,
origin_dcache_valid,
origin_dcache_way,
update_dcache_dirty,
update_dcache_share,
update_dcache_valid,
update_dcache_way
);
// &Ports; @24
input [39:0] compare_dcwp_addr;
input compare_dcwp_sw_inst;
input [6 :0] dcache_dirty_din;
input dcache_dirty_gwen;
input [6 :0] dcache_dirty_wen;
input [8 :0] dcache_idx;
input [51:0] dcache_tag_din;
input dcache_tag_gwen;
input [1 :0] dcache_tag_wen;
input origin_dcache_dirty;
input origin_dcache_share;
input origin_dcache_valid;
input origin_dcache_way;
output compare_dcwp_hit_idx;
output compare_dcwp_update_vld;
output update_dcache_dirty;
output update_dcache_share;
output update_dcache_valid;
output update_dcache_way;
// &Regs; @25
// &Wires; @26
wire [39:0] compare_dcwp_addr;
wire compare_dcwp_hit_dirty;
wire [2 :0] compare_dcwp_hit_dirty_din;
wire [2 :0] compare_dcwp_hit_dirty_wen;
wire compare_dcwp_hit_idx;
wire compare_dcwp_hit_sel;
wire compare_dcwp_hit_share;
wire compare_dcwp_hit_up_vld;
wire compare_dcwp_hit_valid;
wire compare_dcwp_miss_dirty;
wire [2 :0] compare_dcwp_miss_dirty_din;
wire compare_dcwp_miss_share;
wire compare_dcwp_miss_up_pre;
wire compare_dcwp_miss_up_vld;
wire compare_dcwp_miss_up_way0;
wire compare_dcwp_miss_up_way0_sel;
wire compare_dcwp_miss_up_way1;
wire compare_dcwp_miss_up_way1_sel;
wire compare_dcwp_miss_valid;
wire compare_dcwp_sw_inst;
wire compare_dcwp_sw_up_vld;
wire [25:0] compare_dcwp_tag;
wire compare_dcwp_update_vld;
wire [6 :0] dcache_dirty_din;
wire dcache_dirty_gwen;
wire [6 :0] dcache_dirty_wen;
wire [51:0] dcache_tag_din;
wire dcache_tag_gwen;
wire [1 :0] dcache_tag_wen;
wire origin_dcache_dirty;
wire origin_dcache_share;
wire origin_dcache_valid;
wire origin_dcache_way;
wire update_dcache_dirty;
wire update_dcache_dirty_new;
wire update_dcache_share;
wire update_dcache_share_new;
wire update_dcache_valid;
wire update_dcache_valid_new;
wire update_dcache_way;
wire update_dcache_way_new;
// &Force("output","compare_dcwp_hit_idx"); @28
// &Force("input","compare_dcwp_addr"); @29
// &Force("bus","compare_dcwp_addr","39","0"); @30
// &Force("input","dcache_idx"); @31
// &Force("bus","dcache_idx","8","0"); @32
//csky vperl_off
`ifdef DCACHE_32K
assign compare_dcwp_hit_idx = compare_dcwp_addr[13:6] == dcache_idx[7:0];
`endif//DCACHE_32K
`ifdef DCACHE_64K
assign compare_dcwp_hit_idx = compare_dcwp_addr[14:6] == dcache_idx[8:0];
`endif//DCACHE_64K
//csky vperl_on
//-----------------update if dcache hit---------------------
// &Force("bus","dcache_dirty_din",6,0); @45
// &Force("bus","dcache_dirty_wen",6,0); @46
assign compare_dcwp_hit_dirty_din[2:0] = origin_dcache_way
? dcache_dirty_din[5:3]
: dcache_dirty_din[2:0];
assign compare_dcwp_hit_dirty_wen[2:0] = origin_dcache_way
? dcache_dirty_wen[5:3]
: dcache_dirty_wen[2:0];
assign compare_dcwp_hit_up_vld = dcache_dirty_gwen
&& origin_dcache_valid
&& compare_dcwp_hit_idx;
assign compare_dcwp_hit_dirty = compare_dcwp_hit_dirty_wen[2]
? compare_dcwp_hit_dirty_din[2]
: origin_dcache_dirty;
assign compare_dcwp_hit_share = compare_dcwp_hit_dirty_wen[1]
? compare_dcwp_hit_dirty_din[1]
: origin_dcache_share;
assign compare_dcwp_hit_valid = compare_dcwp_hit_dirty_wen[0]
? compare_dcwp_hit_dirty_din[0]
: origin_dcache_valid;
//---------------update if dcache miss----------------------
//dcache set&way inst will not appear dcache miss update,
assign compare_dcwp_miss_up_pre = dcache_tag_gwen
&& !compare_dcwp_sw_inst
&& !origin_dcache_valid;
assign compare_dcwp_tag[25:0] = compare_dcwp_addr[39:14];
assign compare_dcwp_miss_up_way0_sel = dcache_dirty_wen[0]
&& dcache_dirty_din[0]
&& dcache_tag_wen[0]
&& (compare_dcwp_tag[25:0]
== dcache_tag_din[25:0]);
assign compare_dcwp_miss_up_way0 = compare_dcwp_miss_up_pre
&& compare_dcwp_miss_up_way0_sel
&& compare_dcwp_hit_idx;
assign compare_dcwp_miss_up_way1_sel = dcache_dirty_wen[3]
&& dcache_dirty_din[3]
&& dcache_tag_wen[1]
&& (compare_dcwp_tag[25:0]
== dcache_tag_din[51:26]);
assign compare_dcwp_miss_up_way1 = compare_dcwp_miss_up_pre
&& compare_dcwp_miss_up_way1_sel
&& compare_dcwp_hit_idx;
//if refill cacheline then the ralating dirty wen must open,
//so it will set din to the update signal.
assign compare_dcwp_miss_dirty_din[2:0] = compare_dcwp_miss_up_way1_sel
? dcache_dirty_din[5:3]
: dcache_dirty_din[2:0];
assign compare_dcwp_miss_up_vld = compare_dcwp_miss_up_way0
|| compare_dcwp_miss_up_way1;
assign compare_dcwp_miss_dirty = compare_dcwp_miss_dirty_din[2];
assign compare_dcwp_miss_share = compare_dcwp_miss_dirty_din[1];
assign compare_dcwp_miss_valid = compare_dcwp_miss_dirty_din[0];
//--------------------set&way update------------------------
//only up_vld use set&way signal, other signals reuse hit update signals
assign compare_dcwp_sw_up_vld = dcache_dirty_gwen
&& compare_dcwp_sw_inst
&& compare_dcwp_hit_idx;
//---------------------select-------------------------------
// &Force("output","compare_dcwp_update_vld"); @118
assign compare_dcwp_update_vld = compare_dcwp_hit_up_vld
|| compare_dcwp_miss_up_vld
|| compare_dcwp_sw_up_vld;
assign compare_dcwp_hit_sel = origin_dcache_valid
|| compare_dcwp_sw_inst;
assign update_dcache_dirty_new = compare_dcwp_hit_sel
? compare_dcwp_hit_dirty
: compare_dcwp_miss_dirty;
assign update_dcache_share_new = compare_dcwp_hit_sel
? compare_dcwp_hit_share
: compare_dcwp_miss_share;
assign update_dcache_valid_new = compare_dcwp_hit_sel
? compare_dcwp_hit_valid
: compare_dcwp_miss_valid;
assign update_dcache_way_new = compare_dcwp_hit_sel
? origin_dcache_way
: compare_dcwp_miss_up_way1;
//if donot need to update, choose origin value
assign update_dcache_dirty = compare_dcwp_update_vld
? update_dcache_dirty_new
: origin_dcache_dirty;
assign update_dcache_share = compare_dcwp_update_vld
? update_dcache_share_new
: origin_dcache_share;
assign update_dcache_valid = compare_dcwp_update_vld
? update_dcache_valid_new
: origin_dcache_valid;
assign update_dcache_way = compare_dcwp_update_vld
? update_dcache_way_new
: origin_dcache_way;
// &ModuleEnd; @159
endmodule |
module ct_lsu_pfu_gsdb(
cp0_lsu_icg_en,
cp0_yy_clk_en,
cp0_yy_dcache_pref_en,
cpurst_b,
forever_cpuclk,
ld_da_iid,
ld_da_pfu_act_vld,
ld_da_pfu_pf_inst_vld,
ld_da_pfu_va,
pad_yy_icg_scan_en,
pfu_gpfb_vld,
pfu_gsdb_gpfb_create_vld,
pfu_gsdb_gpfb_pop_req,
pfu_gsdb_stride,
pfu_gsdb_stride_neg,
pfu_gsdb_strideh_6to0,
pfu_pop_all_vld,
rtu_yy_xx_commit0,
rtu_yy_xx_commit0_iid,
rtu_yy_xx_commit1,
rtu_yy_xx_commit1_iid,
rtu_yy_xx_commit2,
rtu_yy_xx_commit2_iid,
rtu_yy_xx_flush
);
// &Ports; @29
input cp0_lsu_icg_en;
input cp0_yy_clk_en;
input cp0_yy_dcache_pref_en;
input cpurst_b;
input forever_cpuclk;
input [6 :0] ld_da_iid;
input ld_da_pfu_act_vld;
input ld_da_pfu_pf_inst_vld;
input [39:0] ld_da_pfu_va;
input pad_yy_icg_scan_en;
input pfu_gpfb_vld;
input pfu_pop_all_vld;
input rtu_yy_xx_commit0;
input [6 :0] rtu_yy_xx_commit0_iid;
input rtu_yy_xx_commit1;
input [6 :0] rtu_yy_xx_commit1_iid;
input rtu_yy_xx_commit2;
input [6 :0] rtu_yy_xx_commit2_iid;
input rtu_yy_xx_flush;
output pfu_gsdb_gpfb_create_vld;
output pfu_gsdb_gpfb_pop_req;
output [10:0] pfu_gsdb_stride;
output pfu_gsdb_stride_neg;
output [6 :0] pfu_gsdb_strideh_6to0;
// &Regs; @30
reg pfu_gsdb_newest_pf_inst_cmit;
reg [6 :0] pfu_gsdb_newest_pf_inst_iid;
reg pfu_gsdb_newest_pf_inst_vld;
reg [3 :0] pfu_gsdb_next_state;
reg [1 :0] pfu_gsdb_pop_confidence;
reg [3 :0] pfu_gsdb_state;
// &Wires; @31
wire confidence_add_vld;
wire confidence_max;
wire confidence_min;
wire confidence_reset;
wire confidence_sub_vld;
wire cp0_lsu_icg_en;
wire cp0_yy_clk_en;
wire cp0_yy_dcache_pref_en;
wire cpurst_b;
wire forever_cpuclk;
wire [6 :0] ld_da_iid;
wire ld_da_pfu_act_vld;
wire ld_da_pfu_pf_inst_vld;
wire [39:0] ld_da_pfu_va;
wire monitor_with_confidence;
wire pad_yy_icg_scan_en;
wire pfu_gpfb_vld;
wire pfu_gsdb_addr0_act;
wire pfu_gsdb_addr_cmp_info_vld;
wire pfu_gsdb_check_stride_success;
wire pfu_gsdb_clk;
wire pfu_gsdb_clk_en;
wire pfu_gsdb_create_dp_vld;
wire pfu_gsdb_create_gateclk_en;
wire pfu_gsdb_create_vld;
wire pfu_gsdb_gpfb_create_vld;
wire pfu_gsdb_gpfb_pop_req;
wire pfu_gsdb_newest_pf_inst_cmit_hit0;
wire pfu_gsdb_newest_pf_inst_cmit_hit1;
wire pfu_gsdb_newest_pf_inst_cmit_hit2;
wire pfu_gsdb_newest_pf_inst_cmit_set;
wire pfu_gsdb_newest_pf_inst_flush_uncmit;
wire pfu_gsdb_newest_pf_inst_iid_older_than_ld_da;
wire pfu_gsdb_newest_pf_inst_older_than_ld_da;
wire pfu_gsdb_newest_pf_inst_set;
wire pfu_gsdb_normal_stride;
wire pfu_gsdb_pf_inst_vld;
wire pfu_gsdb_pf_inst_vld_clk;
wire pfu_gsdb_pf_inst_vld_clk_en;
wire pfu_gsdb_state_is_check_stride;
wire pfu_gsdb_state_is_get_stride;
wire pfu_gsdb_state_is_monitor_stride;
wire [10:0] pfu_gsdb_stride;
wire pfu_gsdb_stride_neg;
wire [6 :0] pfu_gsdb_strideh_6to0;
wire pfu_gsdb_vld;
wire pfu_pop_all_vld;
wire rtu_yy_xx_commit0;
wire [6 :0] rtu_yy_xx_commit0_iid;
wire rtu_yy_xx_commit1;
wire [6 :0] rtu_yy_xx_commit1_iid;
wire rtu_yy_xx_commit2;
wire [6 :0] rtu_yy_xx_commit2_iid;
wire rtu_yy_xx_flush;
parameter IDLE = 4'b0000,
GET_STRIDE = 4'b1001,
CHECK_STRIDE = 4'b1010,
MONITOR_STRIDE = 4'b1100;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign pfu_gsdb_clk_en = pfu_gsdb_vld
|| pfu_gsdb_create_gateclk_en;
// &Instance("gated_clk_cell", "x_lsu_pfu_gsdb_gated_clk"); @43
gated_clk_cell x_lsu_pfu_gsdb_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (pfu_gsdb_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pfu_gsdb_clk_en ),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @44
// .external_en (1'b0 ), @45
// .global_en (cp0_yy_clk_en ), @46
// .module_en (cp0_lsu_icg_en ), @47
// .local_en (pfu_gsdb_clk_en ), @48
// .clk_out (pfu_gsdb_clk )); @49
assign pfu_gsdb_pf_inst_vld_clk_en = pfu_gsdb_pf_inst_vld;
// &Instance("gated_clk_cell", "x_lsu_pfu_gsdb_pf_inst_vld_gated_clk"); @52
gated_clk_cell x_lsu_pfu_gsdb_pf_inst_vld_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (pfu_gsdb_pf_inst_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pfu_gsdb_pf_inst_vld_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @53
// .external_en (1'b0 ), @54
// .global_en (cp0_yy_clk_en ), @55
// .module_en (cp0_lsu_icg_en ), @56
// .local_en (pfu_gsdb_pf_inst_vld_clk_en), @57
// .clk_out (pfu_gsdb_pf_inst_vld_clk)); @58
//==========================================================
// Register
//==========================================================
//+-------+
//| state |
//+-------+
always @(posedge pfu_gsdb_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_gsdb_state[3:0] <= IDLE;
else if(pfu_pop_all_vld)
pfu_gsdb_state[3:0] <= IDLE;
else
pfu_gsdb_state[3:0] <= pfu_gsdb_next_state[3:0];
end
assign pfu_gsdb_vld = pfu_gsdb_state[3];
//+----------------+
//| newest_pf_inst |
//+----------------+
always @(posedge pfu_gsdb_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_gsdb_newest_pf_inst_vld <= 1'b0;
else if(pfu_gsdb_create_dp_vld || pfu_gsdb_newest_pf_inst_flush_uncmit)
pfu_gsdb_newest_pf_inst_vld <= 1'b0;
else if(pfu_gsdb_vld && pfu_gsdb_pf_inst_vld)
pfu_gsdb_newest_pf_inst_vld <= 1'b1;
end
always @(posedge pfu_gsdb_pf_inst_vld_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_gsdb_newest_pf_inst_iid[6:0] <= 7'b0;
else if(pfu_gsdb_newest_pf_inst_set)
pfu_gsdb_newest_pf_inst_iid[6:0] <= ld_da_iid[6:0];
end
always @(posedge pfu_gsdb_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_gsdb_newest_pf_inst_cmit <= 1'b0;
else if(pfu_gsdb_newest_pf_inst_set)
pfu_gsdb_newest_pf_inst_cmit <= 1'b0;
else if(pfu_gsdb_newest_pf_inst_cmit_set)
pfu_gsdb_newest_pf_inst_cmit <= 1'b1;
end
//+-----------------------------+
//| gsdb to gpfb pop confidence |
//+-----------------------------+
always @(posedge pfu_gsdb_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_gsdb_pop_confidence[1:0] <= 2'b0;
else if(confidence_reset)
pfu_gsdb_pop_confidence[1:0] <= 2'b10;
else if(confidence_sub_vld)
pfu_gsdb_pop_confidence[1:0] <= pfu_gsdb_pop_confidence[1:0] - 2'b01;
else if(confidence_add_vld)
pfu_gsdb_pop_confidence[1:0] <= pfu_gsdb_pop_confidence[1:0] + 2'b01;
end
//==========================================================
// Instance addr cmp
//==========================================================
// &ConnRule(s/^entry_/pfu_gsdb_/); @125
// &Instance("ct_lsu_pfu_sdb_cmp","x_ct_lsu_pfu_gsdb_cmp"); @126
ct_lsu_pfu_sdb_cmp x_ct_lsu_pfu_gsdb_cmp (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.entry_addr0_act (pfu_gsdb_addr0_act ),
.entry_addr_cmp_info_vld (pfu_gsdb_addr_cmp_info_vld ),
.entry_check_stride_success (pfu_gsdb_check_stride_success),
.entry_clk (pfu_gsdb_clk ),
.entry_create_dp_vld (pfu_gsdb_create_dp_vld ),
.entry_create_gateclk_en (pfu_gsdb_create_gateclk_en ),
.entry_normal_stride (pfu_gsdb_normal_stride ),
.entry_pf_inst_vld (pfu_gsdb_pf_inst_vld ),
.entry_stride (pfu_gsdb_stride ),
.entry_stride_keep (monitor_with_confidence ),
.entry_stride_neg (pfu_gsdb_stride_neg ),
.entry_strideh_6to0 (pfu_gsdb_strideh_6to0 ),
.entry_vld (pfu_gsdb_vld ),
.forever_cpuclk (forever_cpuclk ),
.ld_da_iid (ld_da_iid ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pipe_va (ld_da_pfu_va ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush )
);
// &Connect(.pipe_va (ld_da_pfu_va ), @127
// .entry_stride_keep (monitor_with_confidence)); @128
//==========================================================
// Generate state machine
//==========================================================
// &CombBeg; @134
always @( confidence_min
or pfu_gsdb_normal_stride
or pfu_gsdb_create_vld
or pfu_gsdb_addr_cmp_info_vld
or pfu_gpfb_vld
or pfu_gsdb_state[3:0]
or pfu_gsdb_check_stride_success)
begin
pfu_gsdb_next_state[3:0] = IDLE;
case(pfu_gsdb_state[3:0])
IDLE:
if(pfu_gsdb_create_vld)
pfu_gsdb_next_state[3:0] = GET_STRIDE;
else
pfu_gsdb_next_state[3:0] = IDLE;
GET_STRIDE:
if(pfu_gsdb_addr_cmp_info_vld && pfu_gsdb_normal_stride)
pfu_gsdb_next_state[3:0] = CHECK_STRIDE;
else
pfu_gsdb_next_state[3:0] = GET_STRIDE;
CHECK_STRIDE:
if(pfu_gsdb_addr_cmp_info_vld && pfu_gsdb_check_stride_success)
pfu_gsdb_next_state[3:0] = MONITOR_STRIDE;
else if(pfu_gsdb_addr_cmp_info_vld && !pfu_gsdb_check_stride_success)
pfu_gsdb_next_state[3:0] = GET_STRIDE;
else
pfu_gsdb_next_state[3:0] = CHECK_STRIDE;
MONITOR_STRIDE:
if(pfu_gsdb_addr_cmp_info_vld
&& (!pfu_gsdb_check_stride_success
&& confidence_min
|| !pfu_gpfb_vld))
pfu_gsdb_next_state[3:0] = GET_STRIDE;
else
pfu_gsdb_next_state[3:0] = MONITOR_STRIDE;
default:
pfu_gsdb_next_state[3:0] = IDLE;
endcase
// &CombEnd; @165
end
assign pfu_gsdb_state_is_get_stride = pfu_gsdb_state[0];
assign pfu_gsdb_state_is_check_stride = pfu_gsdb_state[1];
assign pfu_gsdb_state_is_monitor_stride = pfu_gsdb_state[2];
//==========================================================
// Set ld inst
//==========================================================
assign pfu_gsdb_pf_inst_vld = pfu_gsdb_vld
&& ld_da_pfu_pf_inst_vld;
assign pfu_gsdb_addr0_act = pfu_gsdb_newest_pf_inst_older_than_ld_da
&& (!pfu_gsdb_state_is_get_stride
|| ld_da_pfu_act_vld);
//==========================================================
// Generate create gsdb signal
//==========================================================
assign pfu_gsdb_create_vld = !pfu_gsdb_vld
&& cp0_yy_dcache_pref_en;
assign pfu_gsdb_create_dp_vld = pfu_gsdb_create_vld;
assign pfu_gsdb_create_gateclk_en = pfu_gsdb_create_vld;
//==========================================================
// pop confidence ctrl
//==========================================================
assign confidence_max = (pfu_gsdb_pop_confidence[1:0] == 2'b11);
assign confidence_min = (pfu_gsdb_pop_confidence[1:0] == 2'b00);
assign confidence_reset = pfu_gsdb_state_is_check_stride
&& pfu_gsdb_addr_cmp_info_vld
&& pfu_gsdb_check_stride_success;
assign confidence_sub_vld = pfu_gsdb_state_is_monitor_stride
&& pfu_gsdb_addr_cmp_info_vld
&& !pfu_gsdb_check_stride_success
&& !confidence_min;
assign confidence_add_vld = pfu_gsdb_state_is_monitor_stride
&& pfu_gsdb_addr_cmp_info_vld
&& pfu_gsdb_check_stride_success
&& !confidence_max;
assign monitor_with_confidence = pfu_gsdb_state_is_monitor_stride
&& pfu_gpfb_vld
&& !confidence_min;
//==========================================================
// Maintain newest iid
//==========================================================
//-------------------------older----------------------------
// &Instance("ct_rtu_compare_iid","x_lsu_gsdb_newest_inst_cmp"); @212
ct_rtu_compare_iid x_lsu_gsdb_newest_inst_cmp (
.x_iid0 (pfu_gsdb_newest_pf_inst_iid[6:0] ),
.x_iid0_older (pfu_gsdb_newest_pf_inst_iid_older_than_ld_da),
.x_iid1 (ld_da_iid[6:0] )
);
// &Connect( .x_iid0 (pfu_gsdb_newest_pf_inst_iid[6:0]), @213
// .x_iid1 (ld_da_iid[6:0] ), @214
// .x_iid0_older (pfu_gsdb_newest_pf_inst_iid_older_than_ld_da)); @215
assign pfu_gsdb_newest_pf_inst_cmit_hit0 = {rtu_yy_xx_commit0,rtu_yy_xx_commit0_iid[6:0]}
== {1'b1,pfu_gsdb_newest_pf_inst_iid[6:0]};
assign pfu_gsdb_newest_pf_inst_cmit_hit1 = {rtu_yy_xx_commit1,rtu_yy_xx_commit1_iid[6:0]}
== {1'b1,pfu_gsdb_newest_pf_inst_iid[6:0]};
assign pfu_gsdb_newest_pf_inst_cmit_hit2 = {rtu_yy_xx_commit2,rtu_yy_xx_commit2_iid[6:0]}
== {1'b1,pfu_gsdb_newest_pf_inst_iid[6:0]};
assign pfu_gsdb_newest_pf_inst_cmit_set = (pfu_gsdb_newest_pf_inst_cmit_hit0
|| pfu_gsdb_newest_pf_inst_cmit_hit1
|| pfu_gsdb_newest_pf_inst_cmit_hit2)
&& pfu_gsdb_newest_pf_inst_vld;
assign pfu_gsdb_newest_pf_inst_older_than_ld_da = pfu_gsdb_newest_pf_inst_vld
&& (pfu_gsdb_newest_pf_inst_iid_older_than_ld_da
|| pfu_gsdb_newest_pf_inst_cmit);
//-------------------newest_pf_inst_set---------------------
assign pfu_gsdb_newest_pf_inst_set = pfu_gsdb_vld
&& pfu_gsdb_pf_inst_vld
&& (!pfu_gsdb_newest_pf_inst_vld
|| pfu_gsdb_newest_pf_inst_older_than_ld_da);
assign pfu_gsdb_newest_pf_inst_flush_uncmit = rtu_yy_xx_flush
&& !pfu_gsdb_newest_pf_inst_cmit;
//==========================================================
// Generate gpfb signal
//==========================================================
assign pfu_gsdb_gpfb_create_vld = pfu_gsdb_state_is_check_stride
&& pfu_gsdb_addr_cmp_info_vld
&& pfu_gsdb_check_stride_success;
assign pfu_gsdb_gpfb_pop_req = pfu_gsdb_state_is_monitor_stride
&& pfu_gsdb_addr_cmp_info_vld
&& confidence_min
&& !pfu_gsdb_check_stride_success;
// &ModuleEnd; @255
endmodule |
module ct_lsu_mcic(
biu_lsu_r_data,
biu_lsu_r_id,
biu_lsu_r_resp,
biu_lsu_r_vld,
cp0_lsu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dcache_arb_mcic_ld_grnt,
forever_cpuclk,
ld_da_dcache_hit,
ld_da_mcic_borrow_mmu_req,
ld_da_mcic_bypass_data,
ld_da_mcic_data_err,
ld_da_mcic_rb_full,
ld_da_mcic_wakeup,
lfb_mcic_wakeup,
lsu_had_mcic_data_req,
lsu_had_mcic_frz,
lsu_mmu_bus_error,
lsu_mmu_data,
lsu_mmu_data_vld,
mcic_dcache_arb_ld_data_gateclk_en,
mcic_dcache_arb_ld_data_high_idx,
mcic_dcache_arb_ld_data_low_idx,
mcic_dcache_arb_ld_data_req,
mcic_dcache_arb_ld_req,
mcic_dcache_arb_ld_tag_gateclk_en,
mcic_dcache_arb_ld_tag_idx,
mcic_dcache_arb_req_addr,
mmu_lsu_data_req,
mmu_lsu_data_req_addr,
pad_yy_icg_scan_en,
rb_mcic_ar_id,
rb_mcic_biu_req_success,
rb_mcic_ecc_err,
rb_mcic_not_full
);
// &Ports; @26
input [127:0] biu_lsu_r_data;
input [4 :0] biu_lsu_r_id;
input [3 :0] biu_lsu_r_resp;
input biu_lsu_r_vld;
input cp0_lsu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input dcache_arb_mcic_ld_grnt;
input forever_cpuclk;
input ld_da_dcache_hit;
input ld_da_mcic_borrow_mmu_req;
input [63 :0] ld_da_mcic_bypass_data;
input ld_da_mcic_data_err;
input ld_da_mcic_rb_full;
input ld_da_mcic_wakeup;
input lfb_mcic_wakeup;
input mmu_lsu_data_req;
input [39 :0] mmu_lsu_data_req_addr;
input pad_yy_icg_scan_en;
input [4 :0] rb_mcic_ar_id;
input rb_mcic_biu_req_success;
input rb_mcic_ecc_err;
input rb_mcic_not_full;
output lsu_had_mcic_data_req;
output lsu_had_mcic_frz;
output lsu_mmu_bus_error;
output [63 :0] lsu_mmu_data;
output lsu_mmu_data_vld;
output [7 :0] mcic_dcache_arb_ld_data_gateclk_en;
output [10 :0] mcic_dcache_arb_ld_data_high_idx;
output [10 :0] mcic_dcache_arb_ld_data_low_idx;
output [7 :0] mcic_dcache_arb_ld_data_req;
output mcic_dcache_arb_ld_req;
output mcic_dcache_arb_ld_tag_gateclk_en;
output [8 :0] mcic_dcache_arb_ld_tag_idx;
output [39 :0] mcic_dcache_arb_req_addr;
// &Regs; @27
reg [4 :0] mcic_ar_id;
reg mcic_ar_id_vld;
reg mcic_frz;
reg mcic_rb_full;
// &Wires; @28
wire [127:0] biu_lsu_r_data;
wire [4 :0] biu_lsu_r_id;
wire [3 :0] biu_lsu_r_resp;
wire biu_lsu_r_vld;
wire cp0_lsu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire dcache_arb_mcic_ld_grnt;
wire forever_cpuclk;
wire ld_da_dcache_hit;
wire ld_da_mcic_borrow_mmu_req;
wire [63 :0] ld_da_mcic_bypass_data;
wire ld_da_mcic_data_err;
wire ld_da_mcic_rb_full;
wire ld_da_mcic_wakeup;
wire lfb_mcic_wakeup;
wire lsu_had_mcic_data_req;
wire lsu_had_mcic_frz;
wire lsu_mmu_bus_error;
wire [63 :0] lsu_mmu_data;
wire lsu_mmu_data_vld;
wire [63 :0] mcic_bus_bypass_data;
wire [63 :0] mcic_bus_bypass_data_ori;
wire mcic_clk;
wire mcic_clk_en;
wire [63 :0] mcic_data;
wire mcic_data_vld;
wire [7 :0] mcic_dcache_arb_ld_data_gateclk_en;
wire [10 :0] mcic_dcache_arb_ld_data_high_idx;
wire [10 :0] mcic_dcache_arb_ld_data_low_idx;
wire [7 :0] mcic_dcache_arb_ld_data_req;
wire mcic_dcache_arb_ld_req;
wire mcic_dcache_arb_ld_tag_gateclk_en;
wire [8 :0] mcic_dcache_arb_ld_tag_idx;
wire [39 :0] mcic_dcache_arb_req_addr;
wire [3 :0] mcic_dcache_data_req;
wire mcic_r_bus_error;
wire mcic_r_id_hit;
wire mcic_rb_full_wakeup;
wire [39 :0] mcic_req_addr;
wire mmu_lsu_data_req;
wire [39 :0] mmu_lsu_data_req_addr;
wire pad_yy_icg_scan_en;
wire [4 :0] rb_mcic_ar_id;
wire rb_mcic_biu_req_success;
wire rb_mcic_ecc_err;
wire rb_mcic_not_full;
parameter OKAY = 2'b00,
EXOKAY = 2'b01,
SLVERR = 2'b10,
DECERR = 2'b11;
parameter BYTE = 2'b00,
HALF = 2'b01,
WORD = 2'b10;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign mcic_clk_en = mmu_lsu_data_req;
// &Instance("gated_clk_cell", "x_lsu_mcic_gated_clk"); @43
gated_clk_cell x_lsu_mcic_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (mcic_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (mcic_clk_en ),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @44
// .external_en (1'b0 ), @45
// .global_en (cp0_yy_clk_en ), @46
// .module_en (cp0_lsu_icg_en ), @47
// .local_en (mcic_clk_en ), @48
// .clk_out (mcic_clk )); @49
//==========================================================
// Register
//==========================================================
//+-----+
//| frz |
//+-----+
always @(posedge mcic_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mcic_frz <= 1'b0;
else if(mcic_rb_full_wakeup || mcic_data_vld || lfb_mcic_wakeup || ld_da_mcic_wakeup)
mcic_frz <= 1'b0;
else if(dcache_arb_mcic_ld_grnt)
mcic_frz <= 1'b1;
end
//+---------+
//| rb_full |
//+---------+
always @(posedge mcic_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mcic_rb_full <= 1'b0;
else if(mcic_rb_full_wakeup)
mcic_rb_full <= 1'b0;
else if(ld_da_mcic_rb_full)
mcic_rb_full <= 1'b1;
end
//+-----------+
//| ar_id_vld |
//+-----------+
always @(posedge mcic_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mcic_ar_id_vld <= 1'b0;
else if(mcic_data_vld)
mcic_ar_id_vld <= 1'b0;
else if(rb_mcic_biu_req_success)
mcic_ar_id_vld <= 1'b1;
end
//+-------+
//| ar_id |
//+-------+
always @(posedge mcic_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mcic_ar_id[4:0] <= 5'b0;
else if(rb_mcic_biu_req_success)
mcic_ar_id[4:0] <= rb_mcic_ar_id[4:0];
end
//==========================================================
// Dcache request
//==========================================================
assign mcic_req_addr[39:0] = mmu_lsu_data_req_addr[39:0];
//-----------dcache req-------------------------------------
// &Force("output", "mcic_dcache_arb_ld_req"); @109
assign mcic_dcache_arb_ld_req = mmu_lsu_data_req && !mcic_frz;
//-----------tag array------------------
assign mcic_dcache_arb_ld_tag_gateclk_en= mcic_dcache_arb_ld_req;
assign mcic_dcache_arb_ld_tag_idx[8:0] = mmu_lsu_data_req_addr[14:6];
//-----------data array-----------------
assign mcic_dcache_data_req[3:0] = mcic_req_addr[3]
? 4'b1100
: 4'b0011;
// &Force("output","mcic_dcache_arb_ld_data_req"); @118
assign mcic_dcache_arb_ld_data_req[7:0] = {mcic_dcache_data_req[3:0],mcic_dcache_data_req[3:0]};
assign mcic_dcache_arb_ld_data_gateclk_en[7:0]= mcic_dcache_arb_ld_data_req[7:0]
& {8{mcic_dcache_arb_ld_req}};
assign mcic_dcache_arb_ld_data_low_idx[10:0] = mcic_req_addr[14:4];
assign mcic_dcache_arb_ld_data_high_idx[10:0] = {mcic_req_addr[14:5],~mcic_req_addr[4]};
//assign mcic_dcache_arb_ld_data_wen[31:0] = 32'b0;
//-----------borrow signal----------------------------------
assign mcic_dcache_arb_req_addr[39:0] = mcic_req_addr[39:0];
//==========================================================
// Restart
//==========================================================
assign mcic_rb_full_wakeup = mcic_rb_full && rb_mcic_not_full;
//==========================================================
// Bypass data
//==========================================================
//----------------------get data----------------------------
//get data from bus
assign mcic_bus_bypass_data_ori[63:0] = mcic_req_addr[3]
? biu_lsu_r_data[127:64]
: biu_lsu_r_data[63:0];
assign mcic_bus_bypass_data[63:0] = rb_mcic_ecc_err
? 64'b0
: mcic_bus_bypass_data_ori[63:0];
//get data unsettle
assign mcic_data[63:0] = mcic_ar_id_vld
? mcic_bus_bypass_data[63:0]
: ld_da_mcic_bypass_data[63:0];
//==========================================================
// judge biu r info
//==========================================================
assign mcic_data_vld = (ld_da_mcic_borrow_mmu_req && ld_da_dcache_hit)
|| ld_da_mcic_data_err
|| mcic_r_id_hit;
assign mcic_r_id_hit = (mcic_ar_id[4:0] == biu_lsu_r_id[4:0])
&& mcic_ar_id_vld
&& biu_lsu_r_vld;
// &Force("bus","biu_lsu_r_resp",3,0); @161
assign mcic_r_bus_error = biu_lsu_r_resp[1:0] != OKAY;
//==========================================================
// Interface to mmu
//==========================================================
assign lsu_mmu_data_vld = mcic_data_vld;
assign lsu_mmu_data[63:0] = mcic_data[63:0];
assign lsu_mmu_bus_error = mcic_r_id_hit && mcic_r_bus_error;
//==========================================================
// interface to other module
//==========================================================
assign lsu_had_mcic_data_req = mmu_lsu_data_req;
assign lsu_had_mcic_frz = mcic_frz;
// &ModuleEnd; @177
endmodule |
module ct_lsu_rot_data(
data_in,
data_settle_out,
rot_sel
);
// &Ports; @24
input [127:0] data_in;
input [7 :0] rot_sel;
output [127:0] data_settle_out;
// &Regs; @25
reg [63 :0] data_settle;
// &Wires; @26
wire [63 :0] data;
wire [127:0] data_in;
wire [63 :0] data_rot0;
wire [63 :0] data_rot1;
wire [63 :0] data_rot2;
wire [63 :0] data_rot3;
wire [63 :0] data_rot4;
wire [63 :0] data_rot5;
wire [63 :0] data_rot6;
wire [63 :0] data_rot7;
wire [127:0] data_settle_out;
wire [7 :0] rot_sel;
// &CombBeg; @48
// &CombEnd; @68
assign data[63:0] = data_in[63:0]
| data_in[127:64];
assign data_rot0[63:0] = data[63:0];
assign data_rot1[63:0] = {data[7:0],data[63:8]};
assign data_rot2[63:0] = {data[15:0],data[63:16]};
assign data_rot3[63:0] = {data[23:0],data[63:24]};
assign data_rot4[63:0] = {data[31:0],data[63:32]};
assign data_rot5[63:0] = {data[39:0],data[63:40]};
assign data_rot6[63:0] = {data[47:0],data[63:48]};
assign data_rot7[63:0] = {data[55:0],data[63:56]};
// &CombBeg; @85
always @( data_rot5[63:0]
or rot_sel[7:0]
or data_rot0[63:0]
or data_rot3[63:0]
or data_rot6[63:0]
or data_rot4[63:0]
or data_rot1[63:0]
or data_rot7[63:0]
or data_rot2[63:0])
begin
case(rot_sel[7:0])
8'h01:data_settle[63:0] = data_rot0[63:0];
8'h02:data_settle[63:0] = data_rot1[63:0];
8'h04:data_settle[63:0] = data_rot2[63:0];
8'h08:data_settle[63:0] = data_rot3[63:0];
8'h10:data_settle[63:0] = data_rot4[63:0];
8'h20:data_settle[63:0] = data_rot5[63:0];
8'h40:data_settle[63:0] = data_rot6[63:0];
8'h80:data_settle[63:0] = data_rot7[63:0];
default: data_settle[63:0] = {64{1'bx}};
endcase
// &CombEnd; @97
end
assign data_settle_out[127:0] = {64'b0,data_settle[63:0]};
// &ModuleEnd; @102
endmodule |
module ct_lsu_dcache_tag_array(
forever_cpuclk,
pad_yy_icg_scan_en,
tag_din,
tag_dout,
tag_gateclk_en,
tag_gwen_b,
tag_idx,
tag_sel_b,
tag_wen_b,
cp0_lsu_icg_en
);
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [51:0] tag_din;
input tag_gateclk_en;
input tag_gwen_b;
input [8 :0] tag_idx;
input tag_sel_b;
input [1 :0] tag_wen_b;
input cp0_lsu_icg_en;
output [51:0] tag_dout;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire tag_clk;
wire tag_clk_en;
wire [51:0] tag_din;
wire [51:0] tag_dout;
wire tag_gateclk_en;
wire tag_gwen_b;
wire [8 :0] tag_idx;
wire tag_sel_b;
wire [1 :0] tag_wen_b;
wire [51:0] tag_wen_b_all;
wire cp0_lsu_icg_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign tag_clk_en = tag_gateclk_en;
// &Instance("gated_clk_cell", "x_dcache_tag_gated_clk"); @79
gated_clk_cell x_dcache_tag_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (tag_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (tag_clk_en ),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @80
// .external_en (1'b0 ), @81
// .global_en (1'b1 ), @82
// .module_en (cp0_lsu_icg_en ), @83
// .local_en (tag_clk_en ), @84
// .clk_out (tag_clk )); @85
//==========================================================
// Instance dcache array
//==========================================================
// &Force("bus","tag_idx","8","0"); @91
assign tag_wen_b_all[51:0] = {{26{tag_wen_b[1]}},
{26{tag_wen_b[0]}}};
//csky vperl_off
`ifdef DCACHE_32K
ct_spsram_256x52 x_ct_spsram_256x52 (
`ifdef MEM_CFG_IN
.mem_cfg_in (mem_cfg_in ),
`endif
.A (tag_idx[7:0] ),
.CEN (tag_sel_b ),
.CLK (tag_clk ),
.D (tag_din ),
.GWEN (tag_gwen_b ),
.Q (tag_dout ),
.WEN (tag_wen_b_all)
);
`endif//DCACHE_32K
`ifdef DCACHE_64K
ct_spsram_512x52 x_ct_spsram_512x52 (
`ifdef MEM_CFG_IN
.mem_cfg_in (mem_cfg_in ),
`endif
.A (tag_idx[8:0] ),
.CEN (tag_sel_b ),
.CLK (tag_clk ),
.D (tag_din ),
.GWEN (tag_gwen_b ),
.Q (tag_dout ),
.WEN (tag_wen_b_all)
);
`endif//DCACHE_64K
//csky vperl_on
// &ModuleEnd; @128
endmodule |
module ct_lsu_dcache_dirty_array(
dirty_din,
dirty_dout,
dirty_gateclk_en,
dirty_gwen_b,
dirty_idx,
dirty_sel_b,
dirty_wen_b,
forever_cpuclk,
pad_yy_icg_scan_en,
cp0_lsu_icg_en
);
input [6:0] dirty_din;
input dirty_gateclk_en;
input dirty_gwen_b;
input [8:0] dirty_idx;
input dirty_sel_b;
input [6:0] dirty_wen_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input cp0_lsu_icg_en;
output [6:0] dirty_dout;
wire dirty_clk;
wire dirty_clk_en;
wire [6:0] dirty_din;
wire [6:0] dirty_dout;
wire dirty_gateclk_en;
wire dirty_gwen_b;
wire [8:0] dirty_idx;
wire dirty_sel_b;
wire [6:0] dirty_wen_b;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire cp0_lsu_icg_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign dirty_clk_en = dirty_gateclk_en;
// &Instance("gated_clk_cell", "x_dcache_dirty_gated_clk"); @103
gated_clk_cell x_dcache_dirty_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (dirty_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (dirty_clk_en ),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @104
// .external_en (1'b0 ), @105
// .global_en (1'b1 ), @106
// .module_en (cp0_lsu_icg_en ), @107
// .local_en (dirty_clk_en ), @108
// .clk_out (dirty_clk )); @109
//==========================================================
// Instance dcache array
//==========================================================
// &Force("bus","dirty_idx","8","0"); @115
//csky vperl_off
`ifdef DCACHE_32K
ct_spsram_256x7 x_ct_spsram_256x7 (
`ifdef MEM_CFG_IN
.mem_cfg_in (mem_cfg_in ),
`endif
.A (dirty_idx[7:0]),
.CEN (dirty_sel_b ),
.CLK (dirty_clk ),
.D (dirty_din ),
.GWEN (dirty_gwen_b ),
.Q (dirty_dout ),
.WEN (dirty_wen_b )
);
`endif//DCACHE_32K
`ifdef DCACHE_64K
ct_spsram_512x7 x_ct_spsram_512x7 (
`ifdef MEM_CFG_IN
.mem_cfg_in (mem_cfg_in ),
`endif
.A (dirty_idx[8:0]),
.CEN (dirty_sel_b ),
.CLK (dirty_clk ),
.D (dirty_din ),
.GWEN (dirty_gwen_b ),
.Q (dirty_dout ),
.WEN (dirty_wen_b )
);
`endif//DCACHE_64K
//csky vperl_on
// &ModuleEnd; @183
endmodule |
module ct_lsu_snoop_resp(
biu_ctcq_cr_ready,
biu_lsu_cd_ready,
biu_lsu_cr_ready,
biu_lsu_cr_resp_acept,
biu_sdb_cd_ready,
biu_snq_cr_ready,
ctcq_biu_cr_resp,
ctcq_biu_cr_valid,
lsu_biu_cd_data,
lsu_biu_cd_last,
lsu_biu_cd_valid,
lsu_biu_cr_resp,
lsu_biu_cr_valid,
sdb_biu_cd_data,
sdb_biu_cd_last,
sdb_biu_cd_valid,
snq_biu_cr_resp,
snq_biu_cr_valid
);
// &Ports; @23
input biu_lsu_cd_ready;
input biu_lsu_cr_ready;
input [4 :0] ctcq_biu_cr_resp;
input ctcq_biu_cr_valid;
input [127:0] sdb_biu_cd_data;
input sdb_biu_cd_last;
input sdb_biu_cd_valid;
input [4 :0] snq_biu_cr_resp;
input snq_biu_cr_valid;
output biu_ctcq_cr_ready;
output biu_lsu_cr_resp_acept;
output biu_sdb_cd_ready;
output biu_snq_cr_ready;
output [127:0] lsu_biu_cd_data;
output lsu_biu_cd_last;
output lsu_biu_cd_valid;
output [4 :0] lsu_biu_cr_resp;
output lsu_biu_cr_valid;
// &Regs; @24
// &Wires; @25
wire biu_ctcq_cr_ready;
wire biu_lsu_cd_ready;
wire biu_lsu_cr_ready;
wire biu_lsu_cr_resp_acept;
wire biu_sdb_cd_ready;
wire biu_snq_cr_ready;
wire [4 :0] ctcq_biu_cr_resp;
wire ctcq_biu_cr_valid;
wire [127:0] lsu_biu_cd_data;
wire lsu_biu_cd_last;
wire lsu_biu_cd_valid;
wire [4 :0] lsu_biu_cr_resp;
wire lsu_biu_cr_valid;
wire [127:0] sdb_biu_cd_data;
wire sdb_biu_cd_last;
wire sdb_biu_cd_valid;
wire [4 :0] snq_biu_cr_resp;
wire snq_biu_cr_valid;
//cr channel
// &Force("output","lsu_biu_cr_valid"); @28
assign lsu_biu_cr_valid = snq_biu_cr_valid || ctcq_biu_cr_valid;
assign lsu_biu_cr_resp[4:0] = (snq_biu_cr_resp[4:0] & {5{snq_biu_cr_valid}})
| (ctcq_biu_cr_resp[4:0] & {5{ctcq_biu_cr_valid}});
assign biu_snq_cr_ready = biu_lsu_cr_ready;
assign biu_ctcq_cr_ready = biu_lsu_cr_ready;
assign biu_lsu_cr_resp_acept = lsu_biu_cr_valid && biu_lsu_cr_ready;
//cd channel
assign lsu_biu_cd_valid = sdb_biu_cd_valid;
assign lsu_biu_cd_data[127:0] = sdb_biu_cd_data[127:0];
assign lsu_biu_cd_last = sdb_biu_cd_last;
assign biu_sdb_cd_ready = biu_lsu_cd_ready;
// &ModuleEnd; @49
endmodule |
module ct_lsu_lq(
cp0_lsu_corr_dis,
cp0_lsu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
ld_dc_addr0,
ld_dc_addr1,
ld_dc_bytes_vld,
ld_dc_bytes_vld1,
ld_dc_chk_ld_addr1_vld,
ld_dc_iid,
ld_dc_inst_chk_vld,
ld_dc_lq_create1_dp_vld,
ld_dc_lq_create1_gateclk_en,
ld_dc_lq_create1_vld,
ld_dc_lq_create_dp_vld,
ld_dc_lq_create_gateclk_en,
ld_dc_lq_create_vld,
ld_dc_secd,
lq_ld_dc_full,
lq_ld_dc_inst_hit,
lq_ld_dc_less2,
lq_ld_dc_spec_fail,
lq_st_dc_spec_fail,
lsu_idu_lq_not_full,
pad_yy_icg_scan_en,
rtu_yy_xx_commit0,
rtu_yy_xx_commit0_iid,
rtu_yy_xx_commit1,
rtu_yy_xx_commit1_iid,
rtu_yy_xx_commit2,
rtu_yy_xx_commit2_iid,
rtu_yy_xx_flush,
st_dc_addr0,
st_dc_bytes_vld,
st_dc_chk_st_inst_vld,
st_dc_chk_statomic_inst_vld,
st_dc_iid
);
// &Ports; @26
input cp0_lsu_corr_dis;
input cp0_lsu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input [39:0] ld_dc_addr0;
input [39:0] ld_dc_addr1;
input [15:0] ld_dc_bytes_vld;
input [15:0] ld_dc_bytes_vld1;
input ld_dc_chk_ld_addr1_vld;
input [6 :0] ld_dc_iid;
input ld_dc_inst_chk_vld;
input ld_dc_lq_create1_dp_vld;
input ld_dc_lq_create1_gateclk_en;
input ld_dc_lq_create1_vld;
input ld_dc_lq_create_dp_vld;
input ld_dc_lq_create_gateclk_en;
input ld_dc_lq_create_vld;
input ld_dc_secd;
input pad_yy_icg_scan_en;
input rtu_yy_xx_commit0;
input [6 :0] rtu_yy_xx_commit0_iid;
input rtu_yy_xx_commit1;
input [6 :0] rtu_yy_xx_commit1_iid;
input rtu_yy_xx_commit2;
input [6 :0] rtu_yy_xx_commit2_iid;
input rtu_yy_xx_flush;
input [39:0] st_dc_addr0;
input [15:0] st_dc_bytes_vld;
input st_dc_chk_st_inst_vld;
input st_dc_chk_statomic_inst_vld;
input [6 :0] st_dc_iid;
output lq_ld_dc_full;
output lq_ld_dc_inst_hit;
output lq_ld_dc_less2;
output lq_ld_dc_spec_fail;
output lq_st_dc_spec_fail;
output lsu_idu_lq_not_full;
// &Regs; @27
reg [15:0] lq_create_ptr0;
reg [15:0] lq_create_ptr1;
// &Wires; @28
wire cp0_lsu_corr_dis;
wire cp0_lsu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire forever_cpuclk;
wire [39:0] ld_dc_addr0;
wire [39:0] ld_dc_addr1;
wire [15:0] ld_dc_bytes_vld;
wire [15:0] ld_dc_bytes_vld1;
wire ld_dc_chk_ld_addr1_vld;
wire [6 :0] ld_dc_iid;
wire ld_dc_inst_chk_vld;
wire ld_dc_lq_create1_dp_vld;
wire ld_dc_lq_create1_gateclk_en;
wire ld_dc_lq_create1_vld;
wire ld_dc_lq_create_dp_vld;
wire ld_dc_lq_create_gateclk_en;
wire ld_dc_lq_create_vld;
wire ld_dc_secd;
wire lq_clk;
wire lq_clk_en;
wire lq_create1_success;
wire lq_create_success;
wire lq_empty;
wire [15:0] lq_entry_create0_dp_vld;
wire [15:0] lq_entry_create0_vld;
wire [15:0] lq_entry_create1_dp_vld;
wire [15:0] lq_entry_create1_gateclk_en;
wire [15:0] lq_entry_create1_vld;
wire [15:0] lq_entry_create_gateclk_en;
wire [15:0] lq_entry_inst_hit;
wire [15:0] lq_entry_rar_spec_fail;
wire [15:0] lq_entry_raw_spec_fail;
wire [15:0] lq_entry_vld;
wire lq_full;
wire lq_ld_dc_full;
wire lq_ld_dc_inst_hit;
wire lq_ld_dc_less2;
wire lq_ld_dc_spec_fail;
wire lq_st_dc_spec_fail;
wire lsu_idu_lq_not_full;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_commit0;
wire [6 :0] rtu_yy_xx_commit0_iid;
wire rtu_yy_xx_commit1;
wire [6 :0] rtu_yy_xx_commit1_iid;
wire rtu_yy_xx_commit2;
wire [6 :0] rtu_yy_xx_commit2_iid;
wire rtu_yy_xx_flush;
wire [39:0] st_dc_addr0;
wire [15:0] st_dc_bytes_vld;
wire st_dc_chk_st_inst_vld;
wire st_dc_chk_statomic_inst_vld;
wire [6 :0] st_dc_iid;
parameter LQ_ENTRY = 16;
//==========================================================
// Instance of Gated Cell
//==========================================================
//if lq has entry or create lq, then this gateclk is on
//lq_clk is used for entry_vld
assign lq_clk_en = !lq_empty
|| ld_dc_lq_create_gateclk_en;
// &Instance("gated_clk_cell", "x_lsu_lq_gated_clk"); @39
gated_clk_cell x_lsu_lq_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (lq_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lq_clk_en ),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @40
// .external_en (1'b0 ), @41
// .global_en (cp0_yy_clk_en ), @42
// .module_en (cp0_lsu_icg_en ), @43
// .local_en (lq_clk_en ), @44
// .clk_out (lq_clk )); @45
//==========================================================
// Instance load queue entry
//==========================================================
// &ConnRule(s/_x$/[0]/); @51
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_0"); @52
ct_lsu_lq_entry x_ct_lsu_lq_entry_0 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[0] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[0] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[0] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[0]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[0] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[0] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[0] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[0] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[0] ),
.lq_entry_vld_x (lq_entry_vld[0] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[1]/); @54
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_1"); @55
ct_lsu_lq_entry x_ct_lsu_lq_entry_1 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[1] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[1] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[1] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[1]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[1] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[1] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[1] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[1] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[1] ),
.lq_entry_vld_x (lq_entry_vld[1] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[2]/); @57
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_2"); @58
ct_lsu_lq_entry x_ct_lsu_lq_entry_2 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[2] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[2] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[2] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[2]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[2] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[2] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[2] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[2] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[2] ),
.lq_entry_vld_x (lq_entry_vld[2] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[3]/); @60
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_3"); @61
ct_lsu_lq_entry x_ct_lsu_lq_entry_3 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[3] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[3] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[3] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[3]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[3] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[3] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[3] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[3] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[3] ),
.lq_entry_vld_x (lq_entry_vld[3] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[4]/); @63
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_4"); @64
ct_lsu_lq_entry x_ct_lsu_lq_entry_4 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[4] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[4] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[4] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[4]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[4] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[4] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[4] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[4] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[4] ),
.lq_entry_vld_x (lq_entry_vld[4] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[5]/); @66
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_5"); @67
ct_lsu_lq_entry x_ct_lsu_lq_entry_5 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[5] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[5] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[5] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[5]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[5] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[5] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[5] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[5] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[5] ),
.lq_entry_vld_x (lq_entry_vld[5] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[6]/); @69
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_6"); @70
ct_lsu_lq_entry x_ct_lsu_lq_entry_6 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[6] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[6] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[6] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[6]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[6] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[6] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[6] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[6] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[6] ),
.lq_entry_vld_x (lq_entry_vld[6] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[7]/); @72
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_7"); @73
ct_lsu_lq_entry x_ct_lsu_lq_entry_7 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[7] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[7] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[7] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[7]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[7] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[7] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[7] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[7] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[7] ),
.lq_entry_vld_x (lq_entry_vld[7] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[8]/); @75
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_8"); @76
ct_lsu_lq_entry x_ct_lsu_lq_entry_8 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[8] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[8] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[8] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[8]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[8] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[8] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[8] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[8] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[8] ),
.lq_entry_vld_x (lq_entry_vld[8] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[9]/); @78
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_9"); @79
ct_lsu_lq_entry x_ct_lsu_lq_entry_9 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[9] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[9] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[9] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[9]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[9] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[9] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[9] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[9] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[9] ),
.lq_entry_vld_x (lq_entry_vld[9] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[10]/); @81
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_10"); @82
ct_lsu_lq_entry x_ct_lsu_lq_entry_10 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[10] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[10] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[10] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[10]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[10] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[10] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[10] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[10] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[10] ),
.lq_entry_vld_x (lq_entry_vld[10] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[11]/); @84
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_11"); @85
ct_lsu_lq_entry x_ct_lsu_lq_entry_11 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[11] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[11] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[11] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[11]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[11] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[11] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[11] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[11] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[11] ),
.lq_entry_vld_x (lq_entry_vld[11] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[12]/); @87
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_12"); @88
ct_lsu_lq_entry x_ct_lsu_lq_entry_12 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[12] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[12] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[12] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[12]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[12] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[12] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[12] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[12] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[12] ),
.lq_entry_vld_x (lq_entry_vld[12] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[13]/); @90
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_13"); @91
ct_lsu_lq_entry x_ct_lsu_lq_entry_13 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[13] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[13] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[13] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[13]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[13] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[13] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[13] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[13] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[13] ),
.lq_entry_vld_x (lq_entry_vld[13] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[14]/); @93
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_14"); @94
ct_lsu_lq_entry x_ct_lsu_lq_entry_14 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[14] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[14] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[14] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[14]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[14] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[14] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[14] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[14] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[14] ),
.lq_entry_vld_x (lq_entry_vld[14] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
// &ConnRule(s/_x$/[15]/); @96
// &Instance("ct_lsu_lq_entry","x_ct_lsu_lq_entry_15"); @97
ct_lsu_lq_entry x_ct_lsu_lq_entry_15 (
.cp0_lsu_corr_dis (cp0_lsu_corr_dis ),
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_dc_addr0 (ld_dc_addr0 ),
.ld_dc_addr1 (ld_dc_addr1 ),
.ld_dc_bytes_vld (ld_dc_bytes_vld ),
.ld_dc_bytes_vld1 (ld_dc_bytes_vld1 ),
.ld_dc_chk_ld_addr1_vld (ld_dc_chk_ld_addr1_vld ),
.ld_dc_iid (ld_dc_iid ),
.ld_dc_inst_chk_vld (ld_dc_inst_chk_vld ),
.ld_dc_secd (ld_dc_secd ),
.lq_clk (lq_clk ),
.lq_entry_create0_dp_vld_x (lq_entry_create0_dp_vld[15] ),
.lq_entry_create0_vld_x (lq_entry_create0_vld[15] ),
.lq_entry_create1_dp_vld_x (lq_entry_create1_dp_vld[15] ),
.lq_entry_create1_gateclk_en_x (lq_entry_create1_gateclk_en[15]),
.lq_entry_create1_vld_x (lq_entry_create1_vld[15] ),
.lq_entry_create_gateclk_en_x (lq_entry_create_gateclk_en[15] ),
.lq_entry_inst_hit_x (lq_entry_inst_hit[15] ),
.lq_entry_rar_spec_fail_x (lq_entry_rar_spec_fail[15] ),
.lq_entry_raw_spec_fail_x (lq_entry_raw_spec_fail[15] ),
.lq_entry_vld_x (lq_entry_vld[15] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_commit0 (rtu_yy_xx_commit0 ),
.rtu_yy_xx_commit0_iid (rtu_yy_xx_commit0_iid ),
.rtu_yy_xx_commit1 (rtu_yy_xx_commit1 ),
.rtu_yy_xx_commit1_iid (rtu_yy_xx_commit1_iid ),
.rtu_yy_xx_commit2 (rtu_yy_xx_commit2 ),
.rtu_yy_xx_commit2_iid (rtu_yy_xx_commit2_iid ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.st_dc_addr0 (st_dc_addr0 ),
.st_dc_bytes_vld (st_dc_bytes_vld ),
.st_dc_chk_st_inst_vld (st_dc_chk_st_inst_vld ),
.st_dc_chk_statomic_inst_vld (st_dc_chk_statomic_inst_vld ),
.st_dc_iid (st_dc_iid )
);
//==========================================================
// Generate create pointer
//==========================================================
// &CombBeg; @101
always @( lq_entry_vld[15:0])
begin
lq_create_ptr0[LQ_ENTRY-1:0] = {LQ_ENTRY{1'b0}};
casez(lq_entry_vld[LQ_ENTRY-1:0])
16'b????_????_????_???0:lq_create_ptr0[0] = 1'b1;
16'b????_????_????_??01:lq_create_ptr0[1] = 1'b1;
16'b????_????_????_?011:lq_create_ptr0[2] = 1'b1;
16'b????_????_????_0111:lq_create_ptr0[3] = 1'b1;
16'b????_????_???0_1111:lq_create_ptr0[4] = 1'b1;
16'b????_????_??01_1111:lq_create_ptr0[5] = 1'b1;
16'b????_????_?011_1111:lq_create_ptr0[6] = 1'b1;
16'b????_????_0111_1111:lq_create_ptr0[7] = 1'b1;
16'b????_???0_1111_1111:lq_create_ptr0[8] = 1'b1;
16'b????_??01_1111_1111:lq_create_ptr0[9] = 1'b1;
16'b????_?011_1111_1111:lq_create_ptr0[10] = 1'b1;
16'b????_0111_1111_1111:lq_create_ptr0[11] = 1'b1;
16'b???0_1111_1111_1111:lq_create_ptr0[12] = 1'b1;
16'b??01_1111_1111_1111:lq_create_ptr0[13] = 1'b1;
16'b?011_1111_1111_1111:lq_create_ptr0[14] = 1'b1;
16'b0111_1111_1111_1111:lq_create_ptr0[15] = 1'b1;
default:lq_create_ptr0[LQ_ENTRY-1:0] = {LQ_ENTRY{1'b0}};
endcase
// &CombEnd; @122
end
// &CombBeg; @124
always @( lq_entry_vld[15:0])
begin
lq_create_ptr1[LQ_ENTRY-1:0] = {LQ_ENTRY{1'b0}};
casez(lq_entry_vld[LQ_ENTRY-1:0])
16'b0???_????_????_????:lq_create_ptr1[15] = 1'b1;
16'b10??_????_????_????:lq_create_ptr1[14] = 1'b1;
16'b110?_????_????_????:lq_create_ptr1[13] = 1'b1;
16'b1110_????_????_????:lq_create_ptr1[12] = 1'b1;
16'b1111_0???_????_????:lq_create_ptr1[11] = 1'b1;
16'b1111_10??_????_????:lq_create_ptr1[10] = 1'b1;
16'b1111_110?_????_????:lq_create_ptr1[9] = 1'b1;
16'b1111_1110_????_????:lq_create_ptr1[8] = 1'b1;
16'b1111_1111_0???_????:lq_create_ptr1[7] = 1'b1;
16'b1111_1111_10??_????:lq_create_ptr1[6] = 1'b1;
16'b1111_1111_110?_????:lq_create_ptr1[5] = 1'b1;
16'b1111_1111_1110_????:lq_create_ptr1[4] = 1'b1;
16'b1111_1111_1111_0???:lq_create_ptr1[3] = 1'b1;
16'b1111_1111_1111_10??:lq_create_ptr1[2] = 1'b1;
16'b1111_1111_1111_110?:lq_create_ptr1[1] = 1'b1;
16'b1111_1111_1111_1110:lq_create_ptr1[0] = 1'b1;
default:lq_create_ptr1[LQ_ENTRY-1:0] = {LQ_ENTRY{1'b0}};
endcase
// &CombEnd; @145
end
assign lq_empty = !(|lq_entry_vld[LQ_ENTRY-1:0]);
assign lq_full = &lq_entry_vld[LQ_ENTRY-1:0];
//==========================================================
// Generate create pointer
//==========================================================
assign lq_create_success = ld_dc_lq_create_vld
&& !rtu_yy_xx_flush
&& (!lq_ld_dc_less2
|| !lq_ld_dc_full && !ld_dc_lq_create1_vld);
assign lq_create1_success = lq_create_success
&& ld_dc_lq_create1_vld;
assign lq_entry_create0_vld[LQ_ENTRY-1:0] = {LQ_ENTRY{lq_create_success}}
& lq_create_ptr0[LQ_ENTRY-1:0];
assign lq_entry_create1_vld[LQ_ENTRY-1:0] = {LQ_ENTRY{lq_create1_success}}
& lq_create_ptr1[LQ_ENTRY-1:0];
assign lq_entry_create0_dp_vld[LQ_ENTRY-1:0] = {LQ_ENTRY{ld_dc_lq_create_dp_vld}}
& lq_create_ptr0[LQ_ENTRY-1:0];
assign lq_entry_create1_dp_vld[LQ_ENTRY-1:0] = {LQ_ENTRY{ld_dc_lq_create1_dp_vld}}
& lq_create_ptr1[LQ_ENTRY-1:0];
assign lq_entry_create_gateclk_en[LQ_ENTRY-1:0] = {LQ_ENTRY{ld_dc_lq_create_gateclk_en}}
& lq_create_ptr0[LQ_ENTRY-1:0];
assign lq_entry_create1_gateclk_en[LQ_ENTRY-1:0] = {LQ_ENTRY{ld_dc_lq_create1_gateclk_en}}
& lq_create_ptr1[LQ_ENTRY-1:0];
//==========================================================
// Generate interface
//==========================================================
// &Force("output", "lq_ld_dc_full"); @181
// &Force("output", "lq_ld_dc_less2"); @182
assign lq_ld_dc_full = lq_full;
assign lq_ld_dc_less2 = &(lq_create_ptr0[LQ_ENTRY-1:0] | lq_entry_vld[LQ_ENTRY-1:0]);
assign lq_ld_dc_inst_hit = |lq_entry_inst_hit[LQ_ENTRY-1:0];
assign lq_ld_dc_spec_fail = |lq_entry_rar_spec_fail[LQ_ENTRY-1:0];
assign lq_st_dc_spec_fail = |lq_entry_raw_spec_fail[LQ_ENTRY-1:0];
assign lsu_idu_lq_not_full = !lq_full;
// &ModuleEnd; @191
endmodule |
module ct_lsu_dcache_ld_tag_array(
forever_cpuclk,
pad_yy_icg_scan_en,
tag_din,
tag_dout,
tag_gateclk_en,
tag_gwen_b,
tag_idx,
tag_sel_b,
tag_wen_b,
cp0_lsu_icg_en
);
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [53:0] tag_din;
input tag_gateclk_en;
input tag_gwen_b;
input [8 :0] tag_idx;
input tag_sel_b;
input [1 :0] tag_wen_b;
input cp0_lsu_icg_en;
output [53:0] tag_dout;
wire forever_cpuclk;
wire ld_tag_clk;
wire ld_tag_clk_en;
wire pad_yy_icg_scan_en;
wire [53:0] tag_din;
wire [53:0] tag_dout;
wire tag_gateclk_en;
wire tag_gwen_b;
wire [8 :0] tag_idx;
wire tag_sel_b;
wire [1 :0] tag_wen_b;
wire [53:0] tag_wen_b_all;
wire cp0_lsu_icg_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign ld_tag_clk_en = tag_gateclk_en;
// &Instance("gated_clk_cell", "x_dcache_ld_tag_gated_clk"); @100
gated_clk_cell x_dcache_ld_tag_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ld_tag_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (ld_tag_clk_en ),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @101
// .external_en (1'b0 ), @102
// .global_en (1'b1 ), @103
// .module_en (cp0_lsu_icg_en ), @104
// .local_en (ld_tag_clk_en ), @105
// .clk_out (ld_tag_clk )); @106
//==========================================================
// Instance dcache array
//==========================================================
assign tag_wen_b_all[53:0] = {{27{tag_wen_b[1]}},
{27{tag_wen_b[0]}}};
//csky vperl_off
`ifdef DCACHE_32K
ct_spsram_256x54 x_ct_spsram_256x54 (
`ifdef MEM_CFG_IN
.mem_cfg_in (mem_cfg_in ),
`endif
.A (tag_idx[7:0] ),
.CEN (tag_sel_b ),
.CLK (ld_tag_clk ),
.D (tag_din ),
.GWEN (tag_gwen_b ),
.Q (tag_dout ),
.WEN (tag_wen_b_all)
);
`endif//DCACHE_32K
`ifdef DCACHE_64K
ct_spsram_512x54 x_ct_spsram_512x54 (
`ifdef MEM_CFG_IN
.mem_cfg_in (mem_cfg_in ),
`endif
.A (tag_idx[8:0] ),
.CEN (tag_sel_b ),
.CLK (ld_tag_clk ),
.D (tag_din ),
.GWEN (tag_gwen_b ),
.Q (tag_dout ),
.WEN (tag_wen_b_all)
);
`endif//DCACHE_64K
//csky vperl_on
endmodule |
module ct_lsu_dcache_top(
cp0_lsu_icg_en,
dcache_lsu_ld_data_bank0_dout,
dcache_lsu_ld_data_bank1_dout,
dcache_lsu_ld_data_bank2_dout,
dcache_lsu_ld_data_bank3_dout,
dcache_lsu_ld_data_bank4_dout,
dcache_lsu_ld_data_bank5_dout,
dcache_lsu_ld_data_bank6_dout,
dcache_lsu_ld_data_bank7_dout,
dcache_lsu_ld_tag_dout,
dcache_lsu_st_dirty_dout,
dcache_lsu_st_tag_dout,
forever_cpuclk,
lsu_dcache_ld_data_gateclk_en,
lsu_dcache_ld_data_gwen_b,
lsu_dcache_ld_data_high_din,
lsu_dcache_ld_data_high_idx,
lsu_dcache_ld_data_low_din,
lsu_dcache_ld_data_low_idx,
lsu_dcache_ld_data_sel_b,
lsu_dcache_ld_data_wen_b,
lsu_dcache_ld_tag_din,
lsu_dcache_ld_tag_gateclk_en,
lsu_dcache_ld_tag_gwen_b,
lsu_dcache_ld_tag_idx,
lsu_dcache_ld_tag_sel_b,
lsu_dcache_ld_tag_wen_b,
lsu_dcache_st_dirty_din,
lsu_dcache_st_dirty_gateclk_en,
lsu_dcache_st_dirty_gwen_b,
lsu_dcache_st_dirty_idx,
lsu_dcache_st_dirty_sel_b,
lsu_dcache_st_dirty_wen_b,
lsu_dcache_st_tag_din,
lsu_dcache_st_tag_gateclk_en,
lsu_dcache_st_tag_gwen_b,
lsu_dcache_st_tag_idx,
lsu_dcache_st_tag_sel_b,
lsu_dcache_st_tag_wen_b,
pad_yy_icg_scan_en
);
// &Ports; @27
input cp0_lsu_icg_en;
input forever_cpuclk;
input [7 :0] lsu_dcache_ld_data_gateclk_en;
input [7 :0] lsu_dcache_ld_data_gwen_b;
input [127:0] lsu_dcache_ld_data_high_din;
input [10 :0] lsu_dcache_ld_data_high_idx;
input [127:0] lsu_dcache_ld_data_low_din;
input [10 :0] lsu_dcache_ld_data_low_idx;
input [7 :0] lsu_dcache_ld_data_sel_b;
input [31 :0] lsu_dcache_ld_data_wen_b;
input [53 :0] lsu_dcache_ld_tag_din;
input lsu_dcache_ld_tag_gateclk_en;
input lsu_dcache_ld_tag_gwen_b;
input [8 :0] lsu_dcache_ld_tag_idx;
input lsu_dcache_ld_tag_sel_b;
input [1 :0] lsu_dcache_ld_tag_wen_b;
input [6 :0] lsu_dcache_st_dirty_din;
input lsu_dcache_st_dirty_gateclk_en;
input lsu_dcache_st_dirty_gwen_b;
input [8 :0] lsu_dcache_st_dirty_idx;
input lsu_dcache_st_dirty_sel_b;
input [6 :0] lsu_dcache_st_dirty_wen_b;
input [51 :0] lsu_dcache_st_tag_din;
input lsu_dcache_st_tag_gateclk_en;
input lsu_dcache_st_tag_gwen_b;
input [8 :0] lsu_dcache_st_tag_idx;
input lsu_dcache_st_tag_sel_b;
input [1 :0] lsu_dcache_st_tag_wen_b;
input pad_yy_icg_scan_en;
output [31 :0] dcache_lsu_ld_data_bank0_dout;
output [31 :0] dcache_lsu_ld_data_bank1_dout;
output [31 :0] dcache_lsu_ld_data_bank2_dout;
output [31 :0] dcache_lsu_ld_data_bank3_dout;
output [31 :0] dcache_lsu_ld_data_bank4_dout;
output [31 :0] dcache_lsu_ld_data_bank5_dout;
output [31 :0] dcache_lsu_ld_data_bank6_dout;
output [31 :0] dcache_lsu_ld_data_bank7_dout;
output [53 :0] dcache_lsu_ld_tag_dout;
output [6 :0] dcache_lsu_st_dirty_dout;
output [51 :0] dcache_lsu_st_tag_dout;
// &Regs; @28
// &Wires; @29
wire cp0_lsu_icg_en;
wire [31 :0] dcache_lsu_ld_data_bank0_dout;
wire [31 :0] dcache_lsu_ld_data_bank1_dout;
wire [31 :0] dcache_lsu_ld_data_bank2_dout;
wire [31 :0] dcache_lsu_ld_data_bank3_dout;
wire [31 :0] dcache_lsu_ld_data_bank4_dout;
wire [31 :0] dcache_lsu_ld_data_bank5_dout;
wire [31 :0] dcache_lsu_ld_data_bank6_dout;
wire [31 :0] dcache_lsu_ld_data_bank7_dout;
wire [53 :0] dcache_lsu_ld_tag_dout;
wire [6 :0] dcache_lsu_st_dirty_dout;
wire [51 :0] dcache_lsu_st_tag_dout;
wire forever_cpuclk;
wire [7 :0] lsu_dcache_ld_data_gateclk_en;
wire [7 :0] lsu_dcache_ld_data_gwen_b;
wire [127:0] lsu_dcache_ld_data_high_din;
wire [10 :0] lsu_dcache_ld_data_high_idx;
wire [127:0] lsu_dcache_ld_data_low_din;
wire [10 :0] lsu_dcache_ld_data_low_idx;
wire [7 :0] lsu_dcache_ld_data_sel_b;
wire [31 :0] lsu_dcache_ld_data_wen_b;
wire [53 :0] lsu_dcache_ld_tag_din;
wire lsu_dcache_ld_tag_gateclk_en;
wire lsu_dcache_ld_tag_gwen_b;
wire [8 :0] lsu_dcache_ld_tag_idx;
wire lsu_dcache_ld_tag_sel_b;
wire [1 :0] lsu_dcache_ld_tag_wen_b;
wire [6 :0] lsu_dcache_st_dirty_din;
wire lsu_dcache_st_dirty_gateclk_en;
wire lsu_dcache_st_dirty_gwen_b;
wire [8 :0] lsu_dcache_st_dirty_idx;
wire lsu_dcache_st_dirty_sel_b;
wire [6 :0] lsu_dcache_st_dirty_wen_b;
wire [51 :0] lsu_dcache_st_tag_din;
wire lsu_dcache_st_tag_gateclk_en;
wire lsu_dcache_st_tag_gwen_b;
wire [8 :0] lsu_dcache_st_tag_idx;
wire lsu_dcache_st_tag_sel_b;
wire [1 :0] lsu_dcache_st_tag_wen_b;
wire pad_yy_icg_scan_en;
//==========================================================
// Instance dcache array
//==========================================================
//---------------------tag and dirty------------------------
// &Instance("ct_lsu_dcache_ld_tag_array", "x_ct_lsu_dcache_ld_tag_array"); @35
ct_lsu_dcache_ld_tag_array x_ct_lsu_dcache_ld_tag_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.tag_din (lsu_dcache_ld_tag_din ),
.tag_dout (dcache_lsu_ld_tag_dout ),
.tag_gateclk_en (lsu_dcache_ld_tag_gateclk_en),
.tag_gwen_b (lsu_dcache_ld_tag_gwen_b ),
.tag_idx (lsu_dcache_ld_tag_idx ),
.tag_sel_b (lsu_dcache_ld_tag_sel_b ),
.tag_wen_b (lsu_dcache_ld_tag_wen_b )
);
// &Connect( @36
// .tag_gateclk_en (lsu_dcache_ld_tag_gateclk_en ), @37
// .tag_dout (dcache_lsu_ld_tag_dout ), @38
// .tag_sel_b (lsu_dcache_ld_tag_sel_b ), @39
// .tag_wen_b (lsu_dcache_ld_tag_wen_b ), @40
// .tag_din (lsu_dcache_ld_tag_din ), @41
// .tag_idx (lsu_dcache_ld_tag_idx ), @42
// .tag_gwen_b (lsu_dcache_ld_tag_gwen_b )); @43
// &Instance("ct_lsu_dcache_tag_array", "x_ct_lsu_dcache_st_tag_array"); @45
ct_lsu_dcache_tag_array x_ct_lsu_dcache_st_tag_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.tag_din (lsu_dcache_st_tag_din ),
.tag_dout (dcache_lsu_st_tag_dout ),
.tag_gateclk_en (lsu_dcache_st_tag_gateclk_en),
.tag_gwen_b (lsu_dcache_st_tag_gwen_b ),
.tag_idx (lsu_dcache_st_tag_idx ),
.tag_sel_b (lsu_dcache_st_tag_sel_b ),
.tag_wen_b (lsu_dcache_st_tag_wen_b )
);
// &Connect( @46
// .tag_gateclk_en (lsu_dcache_st_tag_gateclk_en ), @47
// .tag_dout (dcache_lsu_st_tag_dout ), @48
// .tag_sel_b (lsu_dcache_st_tag_sel_b ), @49
// .tag_wen_b (lsu_dcache_st_tag_wen_b ), @50
// .tag_din (lsu_dcache_st_tag_din ), @51
// .tag_idx (lsu_dcache_st_tag_idx ), @52
// .tag_gwen_b (lsu_dcache_st_tag_gwen_b )); @53
// &Instance("ct_lsu_dcache_dirty_array", "x_ct_lsu_dcache_st_dirty_array"); @55
ct_lsu_dcache_dirty_array x_ct_lsu_dcache_st_dirty_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.dirty_din (lsu_dcache_st_dirty_din ),
.dirty_dout (dcache_lsu_st_dirty_dout ),
.dirty_gateclk_en (lsu_dcache_st_dirty_gateclk_en),
.dirty_gwen_b (lsu_dcache_st_dirty_gwen_b ),
.dirty_idx (lsu_dcache_st_dirty_idx ),
.dirty_sel_b (lsu_dcache_st_dirty_sel_b ),
.dirty_wen_b (lsu_dcache_st_dirty_wen_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @56
// .dirty_gateclk_en (lsu_dcache_st_dirty_gateclk_en ), @57
// .dirty_dout (dcache_lsu_st_dirty_dout ), @58
// .dirty_sel_b (lsu_dcache_st_dirty_sel_b ), @59
// .dirty_wen_b (lsu_dcache_st_dirty_wen_b ), @60
// .dirty_din (lsu_dcache_st_dirty_din ), @61
// .dirty_idx (lsu_dcache_st_dirty_idx ), @62
// .dirty_gwen_b (lsu_dcache_st_dirty_gwen_b )); @63
//-------------------------data-----------------------------
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank0_array"); @67
// &Connect( @68
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[0] ), @69
// .data_dout (dcache_lsu_ld_data_bank0_dout ), @70
// .data_sel_b (lsu_dcache_ld_data_sel_b[0] ), @71
// .data_wen_b (lsu_dcache_ld_data_wen_b[3:0] ), @72
// .data_din (lsu_dcache_ld_data_low_din[38:0] ), @73
// .data_idx (lsu_dcache_ld_data_low_idx ), @74
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[0] )); @75
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank1_array"); @77
// &Connect( @78
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[1] ), @79
// .data_dout (dcache_lsu_ld_data_bank1_dout ), @80
// .data_sel_b (lsu_dcache_ld_data_sel_b[1] ), @81
// .data_wen_b (lsu_dcache_ld_data_wen_b[7:4] ), @82
// .data_din (lsu_dcache_ld_data_low_din[77:39] ), @83
// .data_idx (lsu_dcache_ld_data_low_idx ), @84
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[1] )); @85
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank2_array"); @87
// &Connect( @88
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[2] ), @89
// .data_dout (dcache_lsu_ld_data_bank2_dout ), @90
// .data_sel_b (lsu_dcache_ld_data_sel_b[2] ), @91
// .data_wen_b (lsu_dcache_ld_data_wen_b[11:8] ), @92
// .data_din (lsu_dcache_ld_data_low_din[116:78] ), @93
// .data_idx (lsu_dcache_ld_data_low_idx ), @94
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[2] )); @95
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank3_array"); @97
// &Connect( @98
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[3] ), @99
// .data_dout (dcache_lsu_ld_data_bank3_dout ), @100
// .data_sel_b (lsu_dcache_ld_data_sel_b[3] ), @101
// .data_wen_b (lsu_dcache_ld_data_wen_b[15:12] ), @102
// .data_din (lsu_dcache_ld_data_low_din[155:117] ), @103
// .data_idx (lsu_dcache_ld_data_low_idx ), @104
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[3] )); @105
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank4_array"); @107
// &Connect( @108
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[4] ), @109
// .data_dout (dcache_lsu_ld_data_bank4_dout ), @110
// .data_sel_b (lsu_dcache_ld_data_sel_b[4] ), @111
// .data_wen_b (lsu_dcache_ld_data_wen_b[19:16] ), @112
// .data_din (lsu_dcache_ld_data_high_din[38:0] ), @113
// .data_idx (lsu_dcache_ld_data_high_idx ), @114
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[4] )); @115
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank5_array"); @117
// &Connect( @118
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[5] ), @119
// .data_dout (dcache_lsu_ld_data_bank5_dout ), @120
// .data_sel_b (lsu_dcache_ld_data_sel_b[5] ), @121
// .data_wen_b (lsu_dcache_ld_data_wen_b[23:20] ), @122
// .data_din (lsu_dcache_ld_data_high_din[77:39] ), @123
// .data_idx (lsu_dcache_ld_data_high_idx ), @124
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[5] )); @125
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank6_array"); @127
// &Connect( @128
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[6] ), @129
// .data_dout (dcache_lsu_ld_data_bank6_dout ), @130
// .data_sel_b (lsu_dcache_ld_data_sel_b[6] ), @131
// .data_wen_b (lsu_dcache_ld_data_wen_b[27:24] ), @132
// .data_din (lsu_dcache_ld_data_high_din[116:78] ), @133
// .data_idx (lsu_dcache_ld_data_high_idx ), @134
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[6] )); @135
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank7_array"); @137
// &Connect( @138
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[7] ), @139
// .data_dout (dcache_lsu_ld_data_bank7_dout ), @140
// .data_sel_b (lsu_dcache_ld_data_sel_b[7] ), @141
// .data_wen_b (lsu_dcache_ld_data_wen_b[31:28] ), @142
// .data_din (lsu_dcache_ld_data_high_din[155:117]), @143
// .data_idx (lsu_dcache_ld_data_high_idx ), @144
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[7] )); @145
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank0_array"); @147
ct_lsu_dcache_data_array x_ct_lsu_dcache_ld_data_bank0_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.data_din (lsu_dcache_ld_data_low_din[31:0]),
.data_dout (dcache_lsu_ld_data_bank0_dout ),
.data_gateclk_en (lsu_dcache_ld_data_gateclk_en[0]),
.data_gwen_b (lsu_dcache_ld_data_gwen_b[0] ),
.data_idx (lsu_dcache_ld_data_low_idx ),
.data_sel_b (lsu_dcache_ld_data_sel_b[0] ),
.data_wen_b (lsu_dcache_ld_data_wen_b[3:0] ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @148
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[0] ), @149
// .data_dout (dcache_lsu_ld_data_bank0_dout ), @150
// .data_sel_b (lsu_dcache_ld_data_sel_b[0] ), @151
// .data_wen_b (lsu_dcache_ld_data_wen_b[3:0] ), @152
// .data_din (lsu_dcache_ld_data_low_din[31:0] ), @153
// .data_idx (lsu_dcache_ld_data_low_idx ), @154
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[0] )); @155
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank1_array"); @157
ct_lsu_dcache_data_array x_ct_lsu_dcache_ld_data_bank1_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.data_din (lsu_dcache_ld_data_low_din[63:32]),
.data_dout (dcache_lsu_ld_data_bank1_dout ),
.data_gateclk_en (lsu_dcache_ld_data_gateclk_en[1] ),
.data_gwen_b (lsu_dcache_ld_data_gwen_b[1] ),
.data_idx (lsu_dcache_ld_data_low_idx ),
.data_sel_b (lsu_dcache_ld_data_sel_b[1] ),
.data_wen_b (lsu_dcache_ld_data_wen_b[7:4] ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @158
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[1] ), @159
// .data_dout (dcache_lsu_ld_data_bank1_dout ), @160
// .data_sel_b (lsu_dcache_ld_data_sel_b[1] ), @161
// .data_wen_b (lsu_dcache_ld_data_wen_b[7:4] ), @162
// .data_din (lsu_dcache_ld_data_low_din[63:32] ), @163
// .data_idx (lsu_dcache_ld_data_low_idx ), @164
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[1] )); @165
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank2_array"); @167
ct_lsu_dcache_data_array x_ct_lsu_dcache_ld_data_bank2_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.data_din (lsu_dcache_ld_data_low_din[95:64]),
.data_dout (dcache_lsu_ld_data_bank2_dout ),
.data_gateclk_en (lsu_dcache_ld_data_gateclk_en[2] ),
.data_gwen_b (lsu_dcache_ld_data_gwen_b[2] ),
.data_idx (lsu_dcache_ld_data_low_idx ),
.data_sel_b (lsu_dcache_ld_data_sel_b[2] ),
.data_wen_b (lsu_dcache_ld_data_wen_b[11:8] ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @168
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[2] ), @169
// .data_dout (dcache_lsu_ld_data_bank2_dout ), @170
// .data_sel_b (lsu_dcache_ld_data_sel_b[2] ), @171
// .data_wen_b (lsu_dcache_ld_data_wen_b[11:8] ), @172
// .data_din (lsu_dcache_ld_data_low_din[95:64] ), @173
// .data_idx (lsu_dcache_ld_data_low_idx ), @174
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[2] )); @175
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank3_array"); @177
ct_lsu_dcache_data_array x_ct_lsu_dcache_ld_data_bank3_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.data_din (lsu_dcache_ld_data_low_din[127:96]),
.data_dout (dcache_lsu_ld_data_bank3_dout ),
.data_gateclk_en (lsu_dcache_ld_data_gateclk_en[3] ),
.data_gwen_b (lsu_dcache_ld_data_gwen_b[3] ),
.data_idx (lsu_dcache_ld_data_low_idx ),
.data_sel_b (lsu_dcache_ld_data_sel_b[3] ),
.data_wen_b (lsu_dcache_ld_data_wen_b[15:12] ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @178
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[3] ), @179
// .data_dout (dcache_lsu_ld_data_bank3_dout ), @180
// .data_sel_b (lsu_dcache_ld_data_sel_b[3] ), @181
// .data_wen_b (lsu_dcache_ld_data_wen_b[15:12] ), @182
// .data_din (lsu_dcache_ld_data_low_din[127:96] ), @183
// .data_idx (lsu_dcache_ld_data_low_idx ), @184
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[3] )); @185
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank4_array"); @187
ct_lsu_dcache_data_array x_ct_lsu_dcache_ld_data_bank4_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.data_din (lsu_dcache_ld_data_high_din[31:0]),
.data_dout (dcache_lsu_ld_data_bank4_dout ),
.data_gateclk_en (lsu_dcache_ld_data_gateclk_en[4] ),
.data_gwen_b (lsu_dcache_ld_data_gwen_b[4] ),
.data_idx (lsu_dcache_ld_data_high_idx ),
.data_sel_b (lsu_dcache_ld_data_sel_b[4] ),
.data_wen_b (lsu_dcache_ld_data_wen_b[19:16] ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @188
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[4] ), @189
// .data_dout (dcache_lsu_ld_data_bank4_dout ), @190
// .data_sel_b (lsu_dcache_ld_data_sel_b[4] ), @191
// .data_wen_b (lsu_dcache_ld_data_wen_b[19:16] ), @192
// .data_din (lsu_dcache_ld_data_high_din[31:0] ), @193
// .data_idx (lsu_dcache_ld_data_high_idx ), @194
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[4] )); @195
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank5_array"); @197
ct_lsu_dcache_data_array x_ct_lsu_dcache_ld_data_bank5_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.data_din (lsu_dcache_ld_data_high_din[63:32]),
.data_dout (dcache_lsu_ld_data_bank5_dout ),
.data_gateclk_en (lsu_dcache_ld_data_gateclk_en[5] ),
.data_gwen_b (lsu_dcache_ld_data_gwen_b[5] ),
.data_idx (lsu_dcache_ld_data_high_idx ),
.data_sel_b (lsu_dcache_ld_data_sel_b[5] ),
.data_wen_b (lsu_dcache_ld_data_wen_b[23:20] ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @198
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[5] ), @199
// .data_dout (dcache_lsu_ld_data_bank5_dout ), @200
// .data_sel_b (lsu_dcache_ld_data_sel_b[5] ), @201
// .data_wen_b (lsu_dcache_ld_data_wen_b[23:20] ), @202
// .data_din (lsu_dcache_ld_data_high_din[63:32] ), @203
// .data_idx (lsu_dcache_ld_data_high_idx ), @204
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[5] )); @205
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank6_array"); @207
ct_lsu_dcache_data_array x_ct_lsu_dcache_ld_data_bank6_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.data_din (lsu_dcache_ld_data_high_din[95:64]),
.data_dout (dcache_lsu_ld_data_bank6_dout ),
.data_gateclk_en (lsu_dcache_ld_data_gateclk_en[6] ),
.data_gwen_b (lsu_dcache_ld_data_gwen_b[6] ),
.data_idx (lsu_dcache_ld_data_high_idx ),
.data_sel_b (lsu_dcache_ld_data_sel_b[6] ),
.data_wen_b (lsu_dcache_ld_data_wen_b[27:24] ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @208
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[6] ), @209
// .data_dout (dcache_lsu_ld_data_bank6_dout ), @210
// .data_sel_b (lsu_dcache_ld_data_sel_b[6] ), @211
// .data_wen_b (lsu_dcache_ld_data_wen_b[27:24] ), @212
// .data_din (lsu_dcache_ld_data_high_din[95:64] ), @213
// .data_idx (lsu_dcache_ld_data_high_idx ), @214
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[6] )); @215
// &Instance("ct_lsu_dcache_data_array", "x_ct_lsu_dcache_ld_data_bank7_array"); @217
ct_lsu_dcache_data_array x_ct_lsu_dcache_ld_data_bank7_array (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.data_din (lsu_dcache_ld_data_high_din[127:96]),
.data_dout (dcache_lsu_ld_data_bank7_dout ),
.data_gateclk_en (lsu_dcache_ld_data_gateclk_en[7] ),
.data_gwen_b (lsu_dcache_ld_data_gwen_b[7] ),
.data_idx (lsu_dcache_ld_data_high_idx ),
.data_sel_b (lsu_dcache_ld_data_sel_b[7] ),
.data_wen_b (lsu_dcache_ld_data_wen_b[31:28] ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @218
// .data_gateclk_en (lsu_dcache_ld_data_gateclk_en[7] ), @219
// .data_dout (dcache_lsu_ld_data_bank7_dout ), @220
// .data_sel_b (lsu_dcache_ld_data_sel_b[7] ), @221
// .data_wen_b (lsu_dcache_ld_data_wen_b[31:28] ), @222
// .data_din (lsu_dcache_ld_data_high_din[127:96]), @223
// .data_idx (lsu_dcache_ld_data_high_idx ), @224
// .data_gwen_b (lsu_dcache_ld_data_gwen_b[7] )); @225
// &ModuleEnd; @228
endmodule |
module ct_lsu_idfifo_entry(
cpurst_b,
idfifo_clk,
idfifo_create_id,
idfifo_entry_create_vld_x,
idfifo_entry_id_v
);
// &Ports; @24
input cpurst_b;
input idfifo_clk;
input [2:0] idfifo_create_id;
input idfifo_entry_create_vld_x;
output [2:0] idfifo_entry_id_v;
// &Regs; @25
reg [2:0] idfifo_entry_id;
// &Wires; @26
wire cpurst_b;
wire idfifo_clk;
wire [2:0] idfifo_create_id;
wire idfifo_entry_create_vld;
wire idfifo_entry_create_vld_x;
wire [2:0] idfifo_entry_id_v;
//==========================================================
// Register
//==========================================================
always @(posedge idfifo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
idfifo_entry_id[2:0] <= 3'b0;
else if(idfifo_entry_create_vld)
idfifo_entry_id[2:0] <= idfifo_create_id[2:0];
end
//==========================================================
// Generate interface
//==========================================================
//------------------input-----------------------------------
assign idfifo_entry_create_vld = idfifo_entry_create_vld_x;
//------------------output----------------------------------
assign idfifo_entry_id_v[2:0] = idfifo_entry_id[2:0];
// &ModuleEnd; @47
endmodule |
module ct_lsu_idfifo_8(
cp0_lsu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
idfifo_clk_en,
idfifo_create_id,
idfifo_create_id_oh,
idfifo_create_vld,
idfifo_empty,
idfifo_pop_id_oh,
idfifo_pop_vld,
pad_yy_icg_scan_en
);
// &Ports; @26
input cp0_lsu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input idfifo_clk_en;
input [2:0] idfifo_create_id;
input [7:0] idfifo_create_id_oh;
input idfifo_create_vld;
input idfifo_pop_vld;
input pad_yy_icg_scan_en;
output idfifo_empty;
output [7:0] idfifo_pop_id_oh;
// &Regs; @27
reg [3:0] idfifo_create_ptr;
reg [7:0] idfifo_pop_id_oh;
reg [3:0] idfifo_pop_ptr;
reg [3:0] idfifo_pop_ptr_next;
// &Wires; @28
wire cp0_lsu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire forever_cpuclk;
wire idfifo_1vld;
wire idfifo_clk;
wire idfifo_clk_en;
wire [2:0] idfifo_create_id;
wire [7:0] idfifo_create_id_oh;
wire [7:0] idfifo_create_ptr_oh;
wire idfifo_create_vld;
wire idfifo_empty;
wire [7:0] idfifo_entry_create_vld;
wire [2:0] idfifo_entry_id_0;
wire [2:0] idfifo_entry_id_1;
wire [2:0] idfifo_entry_id_2;
wire [2:0] idfifo_entry_id_3;
wire [2:0] idfifo_entry_id_4;
wire [2:0] idfifo_entry_id_5;
wire [2:0] idfifo_entry_id_6;
wire [2:0] idfifo_entry_id_7;
wire idfifo_pe_clr_vld;
wire idfifo_pe_sel_create_ptr_vld;
wire [2:0] idfifo_pop_id_next;
wire [7:0] idfifo_pop_id_next_oh;
wire [7:0] idfifo_pop_ptr_next_oh;
wire idfifo_pop_vld;
wire pad_yy_icg_scan_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
// &Instance("gated_clk_cell", "x_lsu_idfifo_gated_clk"); @33
gated_clk_cell x_lsu_idfifo_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (idfifo_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (idfifo_clk_en ),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @34
// .external_en (1'b0 ), @35
// .global_en (cp0_yy_clk_en ), @36
// .module_en (cp0_lsu_icg_en ), @37
// .local_en (idfifo_clk_en ), @38
// .clk_out (idfifo_clk )); @39
//==========================================================
// Instance FIFO
//==========================================================
// &ConnRule(s/_x$/[0]/); @43
// &ConnRule(s/_v$/_0/); @44
// &Instance("ct_lsu_idfifo_entry","x_ct_lsu_idfifo_0"); @45
ct_lsu_idfifo_entry x_ct_lsu_idfifo_0 (
.cpurst_b (cpurst_b ),
.idfifo_clk (idfifo_clk ),
.idfifo_create_id (idfifo_create_id ),
.idfifo_entry_create_vld_x (idfifo_entry_create_vld[0]),
.idfifo_entry_id_v (idfifo_entry_id_0 )
);
// &ConnRule(s/_x$/[1]/); @47
// &ConnRule(s/_v$/_1/); @48
// &Instance("ct_lsu_idfifo_entry","x_ct_lsu_idfifo_1"); @49
ct_lsu_idfifo_entry x_ct_lsu_idfifo_1 (
.cpurst_b (cpurst_b ),
.idfifo_clk (idfifo_clk ),
.idfifo_create_id (idfifo_create_id ),
.idfifo_entry_create_vld_x (idfifo_entry_create_vld[1]),
.idfifo_entry_id_v (idfifo_entry_id_1 )
);
// &ConnRule(s/_x$/[2]/); @51
// &ConnRule(s/_v$/_2/); @52
// &Instance("ct_lsu_idfifo_entry","x_ct_lsu_idfifo_2"); @53
ct_lsu_idfifo_entry x_ct_lsu_idfifo_2 (
.cpurst_b (cpurst_b ),
.idfifo_clk (idfifo_clk ),
.idfifo_create_id (idfifo_create_id ),
.idfifo_entry_create_vld_x (idfifo_entry_create_vld[2]),
.idfifo_entry_id_v (idfifo_entry_id_2 )
);
// &ConnRule(s/_x$/[3]/); @55
// &ConnRule(s/_v$/_3/); @56
// &Instance("ct_lsu_idfifo_entry","x_ct_lsu_idfifo_3"); @57
ct_lsu_idfifo_entry x_ct_lsu_idfifo_3 (
.cpurst_b (cpurst_b ),
.idfifo_clk (idfifo_clk ),
.idfifo_create_id (idfifo_create_id ),
.idfifo_entry_create_vld_x (idfifo_entry_create_vld[3]),
.idfifo_entry_id_v (idfifo_entry_id_3 )
);
// &ConnRule(s/_x$/[4]/); @59
// &ConnRule(s/_v$/_4/); @60
// &Instance("ct_lsu_idfifo_entry","x_ct_lsu_idfifo_4"); @61
ct_lsu_idfifo_entry x_ct_lsu_idfifo_4 (
.cpurst_b (cpurst_b ),
.idfifo_clk (idfifo_clk ),
.idfifo_create_id (idfifo_create_id ),
.idfifo_entry_create_vld_x (idfifo_entry_create_vld[4]),
.idfifo_entry_id_v (idfifo_entry_id_4 )
);
// &ConnRule(s/_x$/[5]/); @63
// &ConnRule(s/_v$/_5/); @64
// &Instance("ct_lsu_idfifo_entry","x_ct_lsu_idfifo_5"); @65
ct_lsu_idfifo_entry x_ct_lsu_idfifo_5 (
.cpurst_b (cpurst_b ),
.idfifo_clk (idfifo_clk ),
.idfifo_create_id (idfifo_create_id ),
.idfifo_entry_create_vld_x (idfifo_entry_create_vld[5]),
.idfifo_entry_id_v (idfifo_entry_id_5 )
);
// &ConnRule(s/_x$/[6]/); @67
// &ConnRule(s/_v$/_6/); @68
// &Instance("ct_lsu_idfifo_entry","x_ct_lsu_idfifo_6"); @69
ct_lsu_idfifo_entry x_ct_lsu_idfifo_6 (
.cpurst_b (cpurst_b ),
.idfifo_clk (idfifo_clk ),
.idfifo_create_id (idfifo_create_id ),
.idfifo_entry_create_vld_x (idfifo_entry_create_vld[6]),
.idfifo_entry_id_v (idfifo_entry_id_6 )
);
// &ConnRule(s/_x$/[7]/); @71
// &ConnRule(s/_v$/_7/); @72
// &Instance("ct_lsu_idfifo_entry","x_ct_lsu_idfifo_7"); @73
ct_lsu_idfifo_entry x_ct_lsu_idfifo_7 (
.cpurst_b (cpurst_b ),
.idfifo_clk (idfifo_clk ),
.idfifo_create_id (idfifo_create_id ),
.idfifo_entry_create_vld_x (idfifo_entry_create_vld[7]),
.idfifo_entry_id_v (idfifo_entry_id_7 )
);
//==========================================================
// Register
//==========================================================
//------------------pointer---------------------------------
always @(posedge idfifo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
idfifo_create_ptr[3:0] <= 4'b0;
else if(idfifo_create_vld)
idfifo_create_ptr[3:0] <= idfifo_create_ptr[3:0] + 4'b1;
end
always @(posedge idfifo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
idfifo_pop_ptr[3:0] <= 4'b0;
idfifo_pop_ptr_next[3:0]<= 4'b1;
end
else if(idfifo_pop_vld)
begin
idfifo_pop_ptr[3:0] <= idfifo_pop_ptr_next[3:0];
idfifo_pop_ptr_next[3:0]<= idfifo_pop_ptr_next[3:0] + 4'b1;
end
end
always @(posedge idfifo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
idfifo_pop_id_oh[7:0] <= 8'b0;
else if(idfifo_pe_clr_vld)
idfifo_pop_id_oh[7:0] <= 8'b0;
else if(idfifo_pe_sel_create_ptr_vld)
idfifo_pop_id_oh[7:0] <= idfifo_create_id_oh[7:0];
else if(idfifo_pop_vld)
idfifo_pop_id_oh[7:0] <= idfifo_pop_id_next_oh[7:0];
end
//==========================================================
// Wires
//==========================================================
//------------------pop entry signal------------------------
assign idfifo_pe_clr_vld = idfifo_pop_vld
&& !idfifo_create_vld
&& idfifo_1vld;
assign idfifo_pe_sel_create_ptr_vld = idfifo_create_vld
&& (idfifo_empty
|| idfifo_1vld
&& idfifo_pop_vld);
//------------------entry signal----------------------------
assign idfifo_entry_create_vld[7:0] = idfifo_create_ptr_oh[7:0]
& {8{idfifo_create_vld}};
//------------------pointer---------------------------------
//expand to one hot code
// &Instance("ct_rtu_expand_8","x_lsu_idfifo_create_ptr_expand"); @128
ct_rtu_expand_8 x_lsu_idfifo_create_ptr_expand (
.x_num (idfifo_create_ptr[2:0] ),
.x_num_expand (idfifo_create_ptr_oh[7:0])
);
// &Connect( .x_num (idfifo_create_ptr[2:0] ), @129
// .x_num_expand (idfifo_create_ptr_oh[7:0] )); @130
// &Instance("ct_rtu_expand_8","x_lsu_idfifo_pop_ptr_next_expand"); @132
ct_rtu_expand_8 x_lsu_idfifo_pop_ptr_next_expand (
.x_num (idfifo_pop_ptr_next[2:0] ),
.x_num_expand (idfifo_pop_ptr_next_oh[7:0])
);
// &Connect( .x_num (idfifo_pop_ptr_next[2:0] ), @133
// .x_num_expand (idfifo_pop_ptr_next_oh[7:0] )); @134
//-------------------entry valid signal---------------------
// &Force("output","idfifo_empty"); @137
assign idfifo_empty = idfifo_create_ptr[3:0]
== idfifo_pop_ptr[3:0];
//only 1 entry is valid
assign idfifo_1vld = idfifo_create_ptr[3:0]
== idfifo_pop_ptr_next[3:0];
//-------------------next pop id----------------------------
assign idfifo_pop_id_next[2:0] = {3{idfifo_pop_ptr_next_oh[0]}} & idfifo_entry_id_0[2:0]
| {3{idfifo_pop_ptr_next_oh[1]}} & idfifo_entry_id_1[2:0]
| {3{idfifo_pop_ptr_next_oh[2]}} & idfifo_entry_id_2[2:0]
| {3{idfifo_pop_ptr_next_oh[3]}} & idfifo_entry_id_3[2:0]
| {3{idfifo_pop_ptr_next_oh[4]}} & idfifo_entry_id_4[2:0]
| {3{idfifo_pop_ptr_next_oh[5]}} & idfifo_entry_id_5[2:0]
| {3{idfifo_pop_ptr_next_oh[6]}} & idfifo_entry_id_6[2:0]
| {3{idfifo_pop_ptr_next_oh[7]}} & idfifo_entry_id_7[2:0];
// &Instance("ct_rtu_expand_8","x_lsu_idfifo_pop_id_next_expand"); @154
ct_rtu_expand_8 x_lsu_idfifo_pop_id_next_expand (
.x_num (idfifo_pop_id_next[2:0] ),
.x_num_expand (idfifo_pop_id_next_oh[7:0])
);
// &Connect( .x_num (idfifo_pop_id_next[2:0] ), @155
// .x_num_expand (idfifo_pop_id_next_oh[7:0] )); @156
// &ModuleEnd; @158
endmodule |
module ct_lsu_pfu_pmb_entry(
amr_wa_cancel,
cp0_lsu_icg_en,
cp0_lsu_l2_st_pref_en,
cp0_yy_clk_en,
cpurst_b,
ld_da_ldfifo_pc,
ld_da_pfu_act_dp_vld,
ld_da_pfu_evict_cnt_vld,
ld_da_pfu_pf_inst_vld,
lsu_special_clk,
pad_yy_icg_scan_en,
pfu_pmb_entry_create_dp_vld_x,
pfu_pmb_entry_create_gateclk_en_x,
pfu_pmb_entry_create_vld_x,
pfu_pmb_entry_evict_x,
pfu_pmb_entry_hit_pc_x,
pfu_pmb_entry_pc_v,
pfu_pmb_entry_ready_grnt_x,
pfu_pmb_entry_ready_x,
pfu_pmb_entry_type_ld_x,
pfu_pmb_entry_vld_x,
pfu_pop_all_part_vld,
pipe_create_pc,
pmb_timeout_cnt_val,
st_da_pc,
st_da_pfu_evict_cnt_vld,
st_da_pfu_pf_inst_vld
);
// &Ports; @27
input amr_wa_cancel;
input cp0_lsu_icg_en;
input cp0_lsu_l2_st_pref_en;
input cp0_yy_clk_en;
input cpurst_b;
input [14:0] ld_da_ldfifo_pc;
input ld_da_pfu_act_dp_vld;
input ld_da_pfu_evict_cnt_vld;
input ld_da_pfu_pf_inst_vld;
input lsu_special_clk;
input pad_yy_icg_scan_en;
input pfu_pmb_entry_create_dp_vld_x;
input pfu_pmb_entry_create_gateclk_en_x;
input pfu_pmb_entry_create_vld_x;
input pfu_pmb_entry_ready_grnt_x;
input pfu_pop_all_part_vld;
input [14:0] pipe_create_pc;
input [7 :0] pmb_timeout_cnt_val;
input [14:0] st_da_pc;
input st_da_pfu_evict_cnt_vld;
input st_da_pfu_pf_inst_vld;
output pfu_pmb_entry_evict_x;
output pfu_pmb_entry_hit_pc_x;
output [14:0] pfu_pmb_entry_pc_v;
output pfu_pmb_entry_ready_x;
output pfu_pmb_entry_type_ld_x;
output pfu_pmb_entry_vld_x;
// &Regs; @28
reg pfu_pmb_entry_cnt;
reg pfu_pmb_entry_evict;
reg [14:0] pfu_pmb_entry_pc;
reg pfu_pmb_entry_ready;
reg [7 :0] pfu_pmb_entry_timeout_cnt;
reg pfu_pmb_entry_type_ld;
reg pfu_pmb_entry_vld;
// &Wires; @29
wire amr_wa_cancel;
wire cp0_lsu_icg_en;
wire cp0_lsu_l2_st_pref_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire entry_hit_pc;
wire [14:0] ld_da_ldfifo_pc;
wire ld_da_pfu_act_dp_vld;
wire ld_da_pfu_evict_cnt_vld;
wire ld_da_pfu_pf_inst_vld;
wire lsu_special_clk;
wire pad_yy_icg_scan_en;
wire pfu_pmb_entry_all_pf_inst_clk;
wire pfu_pmb_entry_all_pf_inst_clk_en;
wire pfu_pmb_entry_clk;
wire pfu_pmb_entry_clk_en;
wire pfu_pmb_entry_create_clk;
wire pfu_pmb_entry_create_clk_en;
wire pfu_pmb_entry_create_dp_vld;
wire pfu_pmb_entry_create_dp_vld_x;
wire pfu_pmb_entry_create_gateclk_en;
wire pfu_pmb_entry_create_gateclk_en_x;
wire pfu_pmb_entry_create_vld;
wire pfu_pmb_entry_create_vld_x;
wire pfu_pmb_entry_evict_pop;
wire pfu_pmb_entry_evict_x;
wire pfu_pmb_entry_hit_pc;
wire pfu_pmb_entry_hit_pc_for_new;
wire pfu_pmb_entry_hit_pc_x;
wire [14:0] pfu_pmb_entry_pc_v;
wire pfu_pmb_entry_pop_vld;
wire pfu_pmb_entry_ready_grnt;
wire pfu_pmb_entry_ready_grnt_x;
wire pfu_pmb_entry_ready_x;
wire pfu_pmb_entry_timeout_cnt_full;
wire pfu_pmb_entry_type_ld_x;
wire pfu_pmb_entry_vld_x;
wire pfu_pop_all_part_vld;
wire pfu_pop_st_all;
wire pfu_sdb_entry_evict_clr;
wire pfu_sdb_entry_evict_set;
wire pipe_cmp_inst_vld;
wire [14:0] pipe_cmp_pc;
wire [14:0] pipe_create_pc;
wire pipe_evict_cnt_vld;
wire [7 :0] pmb_timeout_cnt_val;
wire [14:0] st_da_pc;
wire st_da_pfu_evict_cnt_vld;
wire st_da_pfu_pf_inst_vld;
parameter TIMEOUT_BW = 8;
parameter PC_LEN = 15;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign pfu_pmb_entry_clk_en = pfu_pmb_entry_vld
|| pfu_pmb_entry_create_gateclk_en;
// &Instance("gated_clk_cell", "x_lsu_pfu_pmb_entry_gated_clk"); @39
gated_clk_cell x_lsu_pfu_pmb_entry_gated_clk (
.clk_in (lsu_special_clk ),
.clk_out (pfu_pmb_entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pfu_pmb_entry_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (lsu_special_clk ), @40
// .external_en (1'b0 ), @41
// .global_en (cp0_yy_clk_en ), @42
// .module_en (cp0_lsu_icg_en ), @43
// .local_en (pfu_pmb_entry_clk_en), @44
// .clk_out (pfu_pmb_entry_clk )); @45
assign pfu_pmb_entry_create_clk_en = pfu_pmb_entry_create_gateclk_en;
// &Instance("gated_clk_cell", "x_lsu_pfu_pmb_entry_create_gated_clk"); @48
gated_clk_cell x_lsu_pfu_pmb_entry_create_gated_clk (
.clk_in (lsu_special_clk ),
.clk_out (pfu_pmb_entry_create_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pfu_pmb_entry_create_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (lsu_special_clk ), @49
// .external_en (1'b0 ), @50
// .global_en (cp0_yy_clk_en ), @51
// .module_en (cp0_lsu_icg_en ), @52
// .local_en (pfu_pmb_entry_create_clk_en), @53
// .clk_out (pfu_pmb_entry_create_clk)); @54
assign pfu_pmb_entry_all_pf_inst_clk_en = pfu_pmb_entry_vld
&& (ld_da_pfu_pf_inst_vld || st_da_pfu_pf_inst_vld)
|| pfu_pmb_entry_create_gateclk_en;
// &Instance("gated_clk_cell", "x_lsu_pfu_pmb_entry_all_pf_inst_gated_clk"); @59
gated_clk_cell x_lsu_pfu_pmb_entry_all_pf_inst_gated_clk (
.clk_in (lsu_special_clk ),
.clk_out (pfu_pmb_entry_all_pf_inst_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pfu_pmb_entry_all_pf_inst_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (lsu_special_clk ), @60
// .external_en (1'b0 ), @61
// .global_en (cp0_yy_clk_en ), @62
// .module_en (cp0_lsu_icg_en ), @63
// .local_en (pfu_pmb_entry_all_pf_inst_clk_en), @64
// .clk_out (pfu_pmb_entry_all_pf_inst_clk)); @65
//==========================================================
// Register
//==========================================================
//+-----------+
//| entry_vld |
//+-----------+
always @(posedge pfu_pmb_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_pmb_entry_vld <= 1'b0;
else if(pfu_pmb_entry_pop_vld)
pfu_pmb_entry_vld <= 1'b0;
else if(pfu_pmb_entry_create_vld)
pfu_pmb_entry_vld <= 1'b1;
end
//+----+
//| pc |
//+----+
always @(posedge pfu_pmb_entry_create_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_pmb_entry_pc[PC_LEN-1:0] <= {PC_LEN{1'b0}};
else if(pfu_pmb_entry_create_dp_vld)
pfu_pmb_entry_pc[PC_LEN-1:0] <= pipe_create_pc[PC_LEN-1:0];
end
//+----+------+
//| pref_type |
//+----+------+
always @(posedge pfu_pmb_entry_create_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_pmb_entry_type_ld <= 1'b0;
else if(pfu_pmb_entry_create_dp_vld)
pfu_pmb_entry_type_ld <= ld_da_pfu_act_dp_vld;
end
//+-----+
//| cnt |
//+-----+
always @(posedge pfu_pmb_entry_all_pf_inst_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_pmb_entry_cnt <= 1'b0;
else if(pfu_pmb_entry_create_dp_vld)
pfu_pmb_entry_cnt <= 1'b0;
else if(!pfu_pmb_entry_cnt && pfu_pmb_entry_hit_pc)
pfu_pmb_entry_cnt <= ~pfu_pmb_entry_cnt;
end
//+-------------+
//| timeout_cnt |
//+-------------+
always @(posedge pfu_pmb_entry_all_pf_inst_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_pmb_entry_timeout_cnt[TIMEOUT_BW-1:0] <= {TIMEOUT_BW{1'b0}};
else if(pfu_pmb_entry_create_dp_vld || pfu_pmb_entry_hit_pc)
pfu_pmb_entry_timeout_cnt[TIMEOUT_BW-1:0] <= {TIMEOUT_BW{1'b0}};
else if(pipe_evict_cnt_vld && !pfu_pmb_entry_timeout_cnt_full)
pfu_pmb_entry_timeout_cnt[TIMEOUT_BW-1:0] <= pfu_pmb_entry_timeout_cnt[TIMEOUT_BW-1:0]
+ {{TIMEOUT_BW-1{1'b0}},1'b1};
end
//+-------+
//| ready |
//+-------+
always @(posedge pfu_pmb_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_pmb_entry_ready <= 1'b0;
else if(pfu_pmb_entry_create_dp_vld || pfu_pmb_entry_pop_vld)
pfu_pmb_entry_ready <= 1'b0;
else if(pfu_pmb_entry_cnt && pfu_pmb_entry_hit_pc)
pfu_pmb_entry_ready <= 1'b1;
end
//+-------+
//| evict |
//+-------+
always @(posedge pfu_pmb_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
pfu_pmb_entry_evict <= 1'b0;
else if(pfu_pmb_entry_create_dp_vld || pfu_pmb_entry_pop_vld || pfu_sdb_entry_evict_clr)
pfu_pmb_entry_evict <= 1'b0;
else if(pfu_sdb_entry_evict_set)
pfu_pmb_entry_evict <= 1'b1;
end
//==========================================================
// pipe info select
//==========================================================
assign pipe_cmp_inst_vld = pfu_pmb_entry_type_ld
? ld_da_pfu_pf_inst_vld
: st_da_pfu_pf_inst_vld;
assign pipe_cmp_pc[PC_LEN-1:0] = pfu_pmb_entry_type_ld
? ld_da_ldfifo_pc[PC_LEN-1:0]
: st_da_pc[PC_LEN-1:0];
assign pipe_evict_cnt_vld = ld_da_pfu_evict_cnt_vld || st_da_pfu_evict_cnt_vld;
//==========================================================
// Caucalate hit pc signal
//==========================================================
assign entry_hit_pc = pfu_pmb_entry_vld
&& (pipe_cmp_pc[PC_LEN-1:0]
== pfu_pmb_entry_pc[PC_LEN-1:0]);
//for maintance
assign pfu_pmb_entry_hit_pc = entry_hit_pc
&& pipe_cmp_inst_vld;
//for new inst create
assign pfu_pmb_entry_hit_pc_for_new = entry_hit_pc
&& !(pfu_pmb_entry_type_ld ^ ld_da_pfu_act_dp_vld);
//==========================================================
// Set/clr evict
//==========================================================
assign pfu_pmb_entry_timeout_cnt_full = (pfu_pmb_entry_timeout_cnt[TIMEOUT_BW-1:0]
== pmb_timeout_cnt_val[TIMEOUT_BW-1:0]);
//if
assign pfu_sdb_entry_evict_set = pfu_pmb_entry_vld
&& !pfu_pmb_entry_ready
&& pipe_cmp_inst_vld
&& pfu_pmb_entry_timeout_cnt_full
&& !pfu_pmb_entry_hit_pc;
assign pfu_sdb_entry_evict_clr = pfu_pmb_entry_hit_pc;
//==========================================================
// Generate pop signal
//==========================================================
//st pref pop
assign pfu_pop_st_all = pfu_pmb_entry_vld
&& !pfu_pmb_entry_type_ld
&& (!cp0_lsu_l2_st_pref_en || amr_wa_cancel);
//for timing
//when create_vld != create_dp,and the entry is at evict state
//pop entry preventing data path from being changed incorrectly
assign pfu_pmb_entry_evict_pop = pfu_pmb_entry_vld
&& pfu_pmb_entry_evict
&& pfu_pmb_entry_create_dp_vld
&& !pfu_pmb_entry_create_vld;
assign pfu_pmb_entry_pop_vld = pfu_pmb_entry_ready_grnt
|| pfu_pmb_entry_evict_pop
|| pfu_pop_st_all
|| pfu_pop_all_part_vld;
//==========================================================
// Generate interface
//==========================================================
//------------------input-----------------------------------
//-----------create signal--------------
assign pfu_pmb_entry_create_vld = pfu_pmb_entry_create_vld_x;
assign pfu_pmb_entry_create_dp_vld = pfu_pmb_entry_create_dp_vld_x;
assign pfu_pmb_entry_create_gateclk_en = pfu_pmb_entry_create_gateclk_en_x;
//---------grnt/done signal-------------
assign pfu_pmb_entry_ready_grnt = pfu_pmb_entry_ready_grnt_x;
//------------------output----------------------------------
//-----------entry signal---------------
assign pfu_pmb_entry_vld_x = pfu_pmb_entry_vld;
assign pfu_pmb_entry_pc_v[PC_LEN-1:0] = pfu_pmb_entry_pc[PC_LEN-1:0];
assign pfu_pmb_entry_ready_x = pfu_pmb_entry_ready;
assign pfu_pmb_entry_evict_x = pfu_pmb_entry_evict;
assign pfu_pmb_entry_type_ld_x = pfu_pmb_entry_type_ld;
//-----------hit signal-----------------
assign pfu_pmb_entry_hit_pc_x = pfu_pmb_entry_hit_pc_for_new;
// &ModuleEnd; @239
endmodule |
module ct_lsu_sd_ex1(
cp0_lsu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_st_clk,
forever_cpuclk,
idu_lsu_rf_pipe5_gateclk_sel,
idu_lsu_rf_pipe5_sdiq_entry,
idu_lsu_rf_pipe5_sel,
idu_lsu_rf_pipe5_src0,
idu_lsu_rf_pipe5_srcv0_fr,
idu_lsu_rf_pipe5_srcv0_fr_vld,
idu_lsu_rf_pipe5_srcv0_vld,
idu_lsu_rf_pipe5_srcv0_vr0,
idu_lsu_rf_pipe5_srcv0_vr1,
idu_lsu_rf_pipe5_stdata1_vld,
idu_lsu_rf_pipe5_unalign,
lsu_idu_ex1_sdiq_entry,
lsu_idu_ex1_sdiq_frz_clr,
lsu_idu_ex1_sdiq_pop_vld,
pad_yy_icg_scan_en,
rtu_yy_xx_flush,
sd_ex1_data,
sd_ex1_data_bypass,
sd_ex1_inst_vld,
sd_rf_ex1_sdid,
sd_rf_inst_vld_short
);
// &Ports; @26
input cp0_lsu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_st_clk;
input forever_cpuclk;
input idu_lsu_rf_pipe5_gateclk_sel;
input [11 :0] idu_lsu_rf_pipe5_sdiq_entry;
input idu_lsu_rf_pipe5_sel;
input [63 :0] idu_lsu_rf_pipe5_src0;
input [63 :0] idu_lsu_rf_pipe5_srcv0_fr;
input idu_lsu_rf_pipe5_srcv0_fr_vld;
input idu_lsu_rf_pipe5_srcv0_vld;
input [63 :0] idu_lsu_rf_pipe5_srcv0_vr0;
input [63 :0] idu_lsu_rf_pipe5_srcv0_vr1;
input idu_lsu_rf_pipe5_stdata1_vld;
input idu_lsu_rf_pipe5_unalign;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
output [11 :0] lsu_idu_ex1_sdiq_entry;
output lsu_idu_ex1_sdiq_frz_clr;
output lsu_idu_ex1_sdiq_pop_vld;
output [63 :0] sd_ex1_data;
output [127:0] sd_ex1_data_bypass;
output sd_ex1_inst_vld;
output [3 :0] sd_rf_ex1_sdid;
output sd_rf_inst_vld_short;
// &Regs; @27
reg sd_ex1_boundary;
reg sd_ex1_inst_vld;
reg [11 :0] sd_ex1_sdid_oh;
reg sd_ex1_secd;
reg [63 :0] sd_ex1_src0_data;
reg [63 :0] sd_ex1_srcv0_fr_data;
reg sd_ex1_srcv0_fr_vld;
reg sd_ex1_srcv0_vld;
reg [63 :0] sd_ex1_srcv0_vr0_data;
reg [63 :0] sd_ex1_srcv0_vr1_data;
// &Wires; @28
wire cp0_lsu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_st_clk;
wire forever_cpuclk;
wire idu_lsu_rf_pipe5_gateclk_sel;
wire [11 :0] idu_lsu_rf_pipe5_sdiq_entry;
wire idu_lsu_rf_pipe5_sel;
wire [63 :0] idu_lsu_rf_pipe5_src0;
wire [63 :0] idu_lsu_rf_pipe5_srcv0_fr;
wire idu_lsu_rf_pipe5_srcv0_fr_vld;
wire idu_lsu_rf_pipe5_srcv0_vld;
wire [63 :0] idu_lsu_rf_pipe5_srcv0_vr0;
wire [63 :0] idu_lsu_rf_pipe5_srcv0_vr1;
wire idu_lsu_rf_pipe5_stdata1_vld;
wire idu_lsu_rf_pipe5_unalign;
wire [11 :0] lsu_idu_ex1_sdiq_entry;
wire lsu_idu_ex1_sdiq_frz_clr;
wire lsu_idu_ex1_sdiq_pop_vld;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_flush;
wire sd_ex1_clk;
wire sd_ex1_clk_en;
wire [63 :0] sd_ex1_data;
wire [63 :0] sd_ex1_data_64;
wire [127:0] sd_ex1_data_bypass;
wire sd_ex1_data_clk;
wire sd_ex1_data_clk_en;
wire sd_ex1_vdata_clk;
wire sd_ex1_vdata_clk_en;
wire sd_rf_ex1_inst_vld;
wire [3 :0] sd_rf_ex1_sdid;
wire sd_rf_inst_vld_short;
parameter LSIQ_ENTRY = 12;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign sd_ex1_clk_en = idu_lsu_rf_pipe5_gateclk_sel;
// &Instance("gated_clk_cell", "x_lsu_sd_ex1_gated_clk"); @36
gated_clk_cell x_lsu_sd_ex1_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (sd_ex1_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (sd_ex1_clk_en ),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @37
// .external_en (1'b0 ), @38
// .global_en (cp0_yy_clk_en ), @39
// .module_en (cp0_lsu_icg_en ), @40
// .local_en (sd_ex1_clk_en ), @41
// .clk_out (sd_ex1_clk )); @42
assign sd_ex1_data_clk_en = idu_lsu_rf_pipe5_gateclk_sel
&& !idu_lsu_rf_pipe5_srcv0_vld;
// &Instance("gated_clk_cell", "x_lsu_sd_ex1_data_gated_clk"); @46
gated_clk_cell x_lsu_sd_ex1_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (sd_ex1_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (sd_ex1_data_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @47
// .external_en (1'b0 ), @48
// .global_en (cp0_yy_clk_en ), @49
// .module_en (cp0_lsu_icg_en ), @50
// .local_en (sd_ex1_data_clk_en ), @51
// .clk_out (sd_ex1_data_clk )); @52
assign sd_ex1_vdata_clk_en = idu_lsu_rf_pipe5_gateclk_sel
&& idu_lsu_rf_pipe5_srcv0_vld;
// &Instance("gated_clk_cell", "x_lsu_sd_ex1_vdata_gated_clk"); @56
gated_clk_cell x_lsu_sd_ex1_vdata_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (sd_ex1_vdata_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (sd_ex1_vdata_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @57
// .external_en (1'b0 ), @58
// .global_en (cp0_yy_clk_en ), @59
// .module_en (cp0_lsu_icg_en ), @60
// .local_en (sd_ex1_vdata_clk_en ), @61
// .clk_out (sd_ex1_vdata_clk )); @62
//==========================================================
// encode sdid
//==========================================================
assign sd_rf_ex1_sdid[3:0] = {4{idu_lsu_rf_pipe5_sdiq_entry[0]}} & 4'd0
| {4{idu_lsu_rf_pipe5_sdiq_entry[1]}} & 4'd1
| {4{idu_lsu_rf_pipe5_sdiq_entry[2]}} & 4'd2
| {4{idu_lsu_rf_pipe5_sdiq_entry[3]}} & 4'd3
| {4{idu_lsu_rf_pipe5_sdiq_entry[4]}} & 4'd4
| {4{idu_lsu_rf_pipe5_sdiq_entry[5]}} & 4'd5
| {4{idu_lsu_rf_pipe5_sdiq_entry[6]}} & 4'd6
| {4{idu_lsu_rf_pipe5_sdiq_entry[7]}} & 4'd7
| {4{idu_lsu_rf_pipe5_sdiq_entry[8]}} & 4'd8
| {4{idu_lsu_rf_pipe5_sdiq_entry[9]}} & 4'd9
| {4{idu_lsu_rf_pipe5_sdiq_entry[10]}} & 4'd10
| {4{idu_lsu_rf_pipe5_sdiq_entry[11]}} & 4'd11;
//==========================================================
// Pipeline Register
//==========================================================
//------------------control part----------------------------
//+----------+
//| inst_vld |
//+----------+
assign sd_rf_inst_vld_short = idu_lsu_rf_pipe5_gateclk_sel;
assign sd_rf_ex1_inst_vld = idu_lsu_rf_pipe5_sel && !rtu_yy_xx_flush;
// &Force("output","sd_ex1_inst_vld"); @89
always @(posedge ctrl_st_clk or negedge cpurst_b)
begin
if (!cpurst_b)
sd_ex1_inst_vld <= 1'b0;
else
sd_ex1_inst_vld <= sd_rf_ex1_inst_vld;
end
//+------+------+----------+------+
//| sdid | secd | boundary | data |
//+------+------+----------+------+
always @(posedge sd_ex1_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
sd_ex1_sdid_oh[LSIQ_ENTRY-1:0] <= {LSIQ_ENTRY{1'b0}};
sd_ex1_secd <= 1'b0;
sd_ex1_boundary <= 1'b0;
sd_ex1_srcv0_vld <= 1'b0;
sd_ex1_srcv0_fr_vld <= 1'b0;
end
else if (sd_ex1_clk_en)
begin
sd_ex1_sdid_oh[LSIQ_ENTRY-1:0] <= idu_lsu_rf_pipe5_sdiq_entry[LSIQ_ENTRY-1:0];
sd_ex1_secd <= idu_lsu_rf_pipe5_stdata1_vld;
sd_ex1_boundary <= idu_lsu_rf_pipe5_unalign;
sd_ex1_srcv0_vld <= idu_lsu_rf_pipe5_srcv0_vld;
sd_ex1_srcv0_fr_vld <= idu_lsu_rf_pipe5_srcv0_fr_vld;
end
end
always @(posedge sd_ex1_data_clk or negedge cpurst_b)
begin
if (!cpurst_b)
sd_ex1_src0_data[63:0] <= 64'b0;
else if (sd_ex1_data_clk_en)
sd_ex1_src0_data[63:0] <= idu_lsu_rf_pipe5_src0[63:0];
end
always @(posedge sd_ex1_vdata_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
sd_ex1_srcv0_vr1_data[63:0] <= 64'b0;
sd_ex1_srcv0_vr0_data[63:0] <= 64'b0;
sd_ex1_srcv0_fr_data[63:0] <= 64'b0;
end
else if (sd_ex1_vdata_clk_en)
begin
sd_ex1_srcv0_vr1_data[63:0] <= idu_lsu_rf_pipe5_srcv0_vr1[63:0];
sd_ex1_srcv0_vr0_data[63:0] <= idu_lsu_rf_pipe5_srcv0_vr0[63:0];
sd_ex1_srcv0_fr_data[63:0] <= idu_lsu_rf_pipe5_srcv0_fr[63:0];
end
end
//==========================================================
// data select
//==========================================================
assign sd_ex1_data_64[63:0] = sd_ex1_srcv0_vld
? (sd_ex1_srcv0_fr_vld
? sd_ex1_srcv0_fr_data[63:0]
: sd_ex1_srcv0_vr0_data[63:0])
: sd_ex1_src0_data[63:0];
//sd_ex1_data used for sq data rot,sd_ex1_data_bypass used for ld_da data bypass
// &Force("nonport","sd_ex1_srcv0_vr1_data"); @158
assign sd_ex1_data[63:0] = sd_ex1_data_64[63:0];
assign sd_ex1_data_bypass[127:0] = {64'b0,sd_ex1_data_64[63:0]};
//==========================================================
// Generage interface to idu
//==========================================================
assign lsu_idu_ex1_sdiq_pop_vld = sd_ex1_inst_vld
&& (!sd_ex1_boundary || sd_ex1_secd);
assign lsu_idu_ex1_sdiq_frz_clr = sd_ex1_inst_vld
&& sd_ex1_boundary
&& !sd_ex1_secd;
assign lsu_idu_ex1_sdiq_entry[LSIQ_ENTRY-1:0] = sd_ex1_sdid_oh[LSIQ_ENTRY-1:0];
// &ModuleEnd; @172
endmodule |
module ct_lsu_vb_sdb_data_entry(
cp0_lsu_icg_en,
cpurst_b,
forever_cpuclk,
ld_da_data256,
ld_da_vb_borrow_vb_x,
pad_yy_icg_scan_en,
sdb_create_data_order,
sdb_create_en_x,
sdb_data_vld_x,
sdb_entry_avail_x,
sdb_entry_data_index,
sdb_entry_data_v,
sdb_inv_en_x,
sdb_vld_x,
snq_data_bypass_hit_x,
snq_vb_bypass_invalid_x,
snq_vb_bypass_readonce,
snq_vb_bypass_start_x,
vb_data_entry_addr_id_v,
vb_data_entry_biu_req_success_x,
vb_data_entry_biu_req_x,
vb_data_entry_bypass_pop_x,
vb_data_entry_create_dp_vld_x,
vb_data_entry_create_gateclk_en_x,
vb_data_entry_create_vld_x,
vb_data_entry_dirty_x,
vb_data_entry_inv_x,
vb_data_entry_lfb_create_x,
vb_data_entry_normal_pop_x,
vb_data_entry_req_success_x,
vb_data_entry_vld_x,
vb_data_entry_wd_sm_grnt_x,
vb_data_entry_wd_sm_req_x,
vb_data_entry_write_data128_v,
vb_rcl_sm_addr_id,
vb_rcl_sm_data_dcache_dirty,
vb_rcl_sm_data_set_data_done_x,
vb_rcl_sm_inv,
vb_rcl_sm_lfb_create,
vb_sdb_data_entry_vld_x,
vb_wd_sm_data_bias,
vb_wd_sm_data_pop_req_x
);
// &Ports; @28
input cp0_lsu_icg_en;
input cpurst_b;
input forever_cpuclk;
input [255:0] ld_da_data256;
input ld_da_vb_borrow_vb_x;
input pad_yy_icg_scan_en;
input [1 :0] sdb_create_data_order;
input sdb_create_en_x;
input [3 :0] sdb_entry_data_index;
input sdb_inv_en_x;
input snq_data_bypass_hit_x;
input snq_vb_bypass_invalid_x;
input snq_vb_bypass_readonce;
input snq_vb_bypass_start_x;
input vb_data_entry_biu_req_success_x;
input vb_data_entry_create_dp_vld_x;
input vb_data_entry_create_gateclk_en_x;
input vb_data_entry_create_vld_x;
input vb_data_entry_wd_sm_grnt_x;
input [1 :0] vb_rcl_sm_addr_id;
input vb_rcl_sm_data_dcache_dirty;
input vb_rcl_sm_data_set_data_done_x;
input vb_rcl_sm_inv;
input vb_rcl_sm_lfb_create;
input [3 :0] vb_wd_sm_data_bias;
input vb_wd_sm_data_pop_req_x;
output sdb_data_vld_x;
output sdb_entry_avail_x;
output [127:0] sdb_entry_data_v;
output sdb_vld_x;
output [1 :0] vb_data_entry_addr_id_v;
output vb_data_entry_biu_req_x;
output vb_data_entry_bypass_pop_x;
output vb_data_entry_dirty_x;
output vb_data_entry_inv_x;
output vb_data_entry_lfb_create_x;
output vb_data_entry_normal_pop_x;
output vb_data_entry_req_success_x;
output vb_data_entry_vld_x;
output vb_data_entry_wd_sm_req_x;
output [127:0] vb_data_entry_write_data128_v;
output vb_sdb_data_entry_vld_x;
// &Regs; @29
reg sdb_bypass_readonce;
reg [3 :0] sdb_return_order;
reg [1 :0] sdb_start_bias;
reg [1 :0] vb_data_entry_addr_id;
reg [511:0] vb_data_entry_data;
reg [1 :0] vb_data_entry_data_bias;
reg vb_data_entry_dirty;
reg vb_data_entry_inv;
reg vb_data_entry_lfb_create;
reg [3 :0] vb_data_entry_next_state;
reg [3 :0] vb_data_entry_state;
// &Wires; @30
wire cp0_lsu_icg_en;
wire cpurst_b;
wire forever_cpuclk;
wire [255:0] ld_da_data256;
wire ld_da_vb_borrow_vb;
wire ld_da_vb_borrow_vb_x;
wire pad_yy_icg_scan_en;
wire sdb_bypass_reverse;
wire [1 :0] sdb_create_data_order;
wire sdb_create_en;
wire sdb_create_en_x;
wire sdb_data_vld;
wire sdb_data_vld_x;
wire sdb_entry_avail;
wire sdb_entry_avail_x;
wire [127:0] sdb_entry_data;
wire [3 :0] sdb_entry_data_index;
wire [127:0] sdb_entry_data_v;
wire sdb_inv_en;
wire sdb_inv_en_x;
wire sdb_vld;
wire sdb_vld_x;
wire snq_data_bypass_hit;
wire snq_data_bypass_hit_x;
wire snq_vb_bypass_invalid;
wire snq_vb_bypass_invalid_x;
wire snq_vb_bypass_readonce;
wire snq_vb_bypass_start;
wire snq_vb_bypass_start_x;
wire vb_data_bypass_pop;
wire [1 :0] vb_data_entry_addr_id_v;
wire vb_data_entry_biu_req;
wire vb_data_entry_biu_req_success;
wire vb_data_entry_biu_req_success_x;
wire vb_data_entry_biu_req_x;
wire vb_data_entry_bypass_pop_x;
wire vb_data_entry_clk;
wire vb_data_entry_clk_en;
wire vb_data_entry_create_clk;
wire vb_data_entry_create_clk_en;
wire vb_data_entry_create_dp_vld;
wire vb_data_entry_create_dp_vld_x;
wire vb_data_entry_create_gateclk_en;
wire vb_data_entry_create_gateclk_en_x;
wire vb_data_entry_create_vld;
wire vb_data_entry_create_vld_x;
wire vb_data_entry_data0_clk;
wire vb_data_entry_data0_clk_en;
wire vb_data_entry_data1_clk;
wire vb_data_entry_data1_clk_en;
wire vb_data_entry_dirty_x;
wire vb_data_entry_inv_x;
wire vb_data_entry_lfb_create_x;
wire vb_data_entry_normal_pop_x;
wire vb_data_entry_pass_data0_vld;
wire vb_data_entry_pass_data1_vld;
wire vb_data_entry_pop_vld;
wire vb_data_entry_req_success;
wire vb_data_entry_req_success_x;
wire vb_data_entry_vld;
wire vb_data_entry_vld_x;
wire vb_data_entry_wd_sm_grnt;
wire vb_data_entry_wd_sm_grnt_x;
wire vb_data_entry_wd_sm_req;
wire vb_data_entry_wd_sm_req_x;
wire [127:0] vb_data_entry_write_data128;
wire [127:0] vb_data_entry_write_data128_v;
wire vb_data_normal_pop;
wire [1 :0] vb_rcl_sm_addr_id;
wire vb_rcl_sm_data_dcache_dirty;
wire vb_rcl_sm_data_set_data_done;
wire vb_rcl_sm_data_set_data_done_x;
wire vb_rcl_sm_inv;
wire vb_rcl_sm_lfb_create;
wire vb_sdb_data_entry_vld;
wire vb_sdb_data_entry_vld_x;
wire [3 :0] vb_wd_sm_data_bias;
wire vb_wd_sm_data_pop_req;
wire vb_wd_sm_data_pop_req_x;
parameter IDLE = 4'b0000,
GET_VB_DATA = 4'b1000,
REQ_WRITE_ADDR = 4'b1001,
REQ_WRITE_DATA = 4'b1010,
GRNT_WRITE_DATA = 4'b1011,
// VB_NOP = 4'b1111,
WAIT_REQ = 4'b0111,
GET_SNQ_DATA = 4'b0100,
REQ_CD_CHANNEL = 4'b0101;
//==========================================================
// Instance of Gated Cell
//==========================================================
//-----------entry gateclk--------------
//normal gateclk ,open when create || entry_vld
assign vb_data_entry_clk_en = vb_data_entry_vld
|| sdb_vld
|| sdb_create_en
|| vb_data_entry_create_gateclk_en;
// &Instance("gated_clk_cell", "x_lsu_vb_data_entry_gated_clk"); @52
gated_clk_cell x_lsu_vb_data_entry_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (vb_data_entry_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (vb_data_entry_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @53
// .external_en (1'b0 ), @54
// .global_en (1'b1 ), @55
// .module_en (cp0_lsu_icg_en ), @56
// .local_en (vb_data_entry_clk_en), @57
// .clk_out (vb_data_entry_clk )); @58
//-----------data gateclk---------------
assign vb_data_entry_create_clk_en = vb_data_entry_create_gateclk_en;
// &Instance("gated_clk_cell", "x_lsu_vb_data_entry_create_gated_clk"); @62
gated_clk_cell x_lsu_vb_data_entry_create_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (vb_data_entry_create_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (vb_data_entry_create_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @63
// .external_en (1'b0 ), @64
// .global_en (1'b1 ), @65
// .module_en (cp0_lsu_icg_en ), @66
// .local_en (vb_data_entry_create_clk_en), @67
// .clk_out (vb_data_entry_create_clk)); @68
assign vb_data_entry_data0_clk_en = vb_data_entry_pass_data0_vld;
// &Instance("gated_clk_cell", "x_lsu_vb_data_entry_data0_gated_clk"); @71
gated_clk_cell x_lsu_vb_data_entry_data0_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (vb_data_entry_data0_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (vb_data_entry_data0_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @72
// .external_en (1'b0 ), @73
// .global_en (1'b1 ), @74
// .module_en (cp0_lsu_icg_en ), @75
// .local_en (vb_data_entry_data0_clk_en), @76
// .clk_out (vb_data_entry_data0_clk)); @77
assign vb_data_entry_data1_clk_en = vb_data_entry_pass_data1_vld;
// &Instance("gated_clk_cell", "x_lsu_vb_data_entry_data1_gated_clk"); @80
gated_clk_cell x_lsu_vb_data_entry_data1_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (vb_data_entry_data1_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (vb_data_entry_data1_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @81
// .external_en (1'b0 ), @82
// .global_en (1'b1 ), @83
// .module_en (cp0_lsu_icg_en ), @84
// .local_en (vb_data_entry_data1_clk_en), @85
// .clk_out (vb_data_entry_data1_clk)); @86
//==========================================================
// Registers
//==========================================================
//+-------+
//| state |
//+-------+
always @(posedge vb_data_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
vb_data_entry_state[3:0] <= IDLE;
else
vb_data_entry_state[3:0] <= vb_data_entry_next_state[3:0];
end
assign vb_data_entry_vld = vb_data_entry_state[3];
assign vb_data_entry_biu_req = (vb_data_entry_state[3:0] == REQ_WRITE_ADDR);
assign vb_data_entry_wd_sm_req = (vb_data_entry_state[3:0] == REQ_WRITE_DATA);
//+-----------+
//| data_bias |
//+-----------+
always @(posedge vb_data_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
vb_data_entry_data_bias[1:0] <= 2'b1;
else if(vb_data_entry_create_dp_vld || sdb_create_en)
vb_data_entry_data_bias[1:0] <= 2'b1;
else if(ld_da_vb_borrow_vb)
vb_data_entry_data_bias[1:0] <= {vb_data_entry_data_bias[0],
vb_data_entry_data_bias[1]};
end
//+-------+------------+-----+---------+
//| dirty | lfb_create | inv | addr_id |
//+-------+------------+-----+---------+
//dirty is read from cache
//lfb create is read from addr entry
always @(posedge vb_data_entry_create_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
vb_data_entry_dirty <= 1'b0;
vb_data_entry_lfb_create <= 1'b0;
vb_data_entry_inv <= 1'b0;
vb_data_entry_addr_id[1:0] <= 2'b0;
end
else if(vb_data_entry_create_dp_vld)
begin
vb_data_entry_dirty <= vb_rcl_sm_data_dcache_dirty;
vb_data_entry_lfb_create <= vb_rcl_sm_lfb_create;
vb_data_entry_inv <= vb_rcl_sm_inv;
vb_data_entry_addr_id[1:0] <= vb_rcl_sm_addr_id[1:0];
end
end
//+------+
//| data |
//+------+
always @(posedge vb_data_entry_data0_clk or negedge cpurst_b)
begin
if (!cpurst_b)
vb_data_entry_data[255:0] <= 256'b0;
else if(vb_data_entry_pass_data0_vld)
vb_data_entry_data[255:0] <= ld_da_data256[255:0];
end
always @(posedge vb_data_entry_data1_clk or negedge cpurst_b)
begin
if (!cpurst_b)
vb_data_entry_data[511:256] <= 256'b0;
else if(vb_data_entry_pass_data1_vld)
vb_data_entry_data[511:256] <= ld_da_data256[255:0];
end
//for sdb return order
//+--------------+
//| return order |
//+--------------+
always @(posedge vb_data_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
sdb_start_bias[1:0] <= 2'b0;
else if(sdb_create_en || snq_vb_bypass_start)
sdb_start_bias[1:0] <= sdb_create_data_order[1:0];
end
//for readonce record
always @(posedge vb_data_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
sdb_bypass_readonce <= 1'b0;
else if(sdb_create_en)
sdb_bypass_readonce <= 1'b0;
else if(snq_vb_bypass_start)
sdb_bypass_readonce <= snq_vb_bypass_readonce;
end
//==========================================================
// Generate next state
//==========================================================
// &CombBeg; @207
always @( sdb_create_en
or vb_rcl_sm_data_set_data_done
or vb_data_entry_wd_sm_grnt
or sdb_bypass_readonce
or vb_data_entry_create_vld
or snq_vb_bypass_start
or snq_vb_bypass_invalid
or vb_data_entry_pass_data0_vld
or vb_data_entry_pop_vld
or snq_data_bypass_hit
or vb_data_entry_state[3:0]
or vb_data_entry_biu_req_success
or vb_data_entry_pass_data1_vld
or sdb_inv_en)
begin
vb_data_entry_next_state[3:0] = IDLE;
case(vb_data_entry_state[3:0])
IDLE:
if(vb_data_entry_create_vld)
vb_data_entry_next_state[3:0] = GET_VB_DATA;
else if(sdb_create_en)
vb_data_entry_next_state[3:0] = GET_SNQ_DATA;
GET_VB_DATA:
if(vb_rcl_sm_data_set_data_done)
vb_data_entry_next_state[3:0] = REQ_WRITE_ADDR;
else
vb_data_entry_next_state[3:0] = GET_VB_DATA;
REQ_WRITE_ADDR:
if(vb_data_entry_biu_req_success)
vb_data_entry_next_state[3:0] = REQ_WRITE_DATA;
else if(snq_data_bypass_hit)
vb_data_entry_next_state[3:0] = WAIT_REQ;
else
vb_data_entry_next_state[3:0] = REQ_WRITE_ADDR;
REQ_WRITE_DATA:
if(vb_data_entry_wd_sm_grnt)
vb_data_entry_next_state[3:0] = GRNT_WRITE_DATA;
else
vb_data_entry_next_state[3:0] = REQ_WRITE_DATA;
GRNT_WRITE_DATA:
if(vb_data_entry_pop_vld)
vb_data_entry_next_state[3:0] = IDLE;
else
vb_data_entry_next_state[3:0] = GRNT_WRITE_DATA;
WAIT_REQ:
if(snq_vb_bypass_start)
vb_data_entry_next_state[3:0] = REQ_CD_CHANNEL;
else if(snq_vb_bypass_invalid)
vb_data_entry_next_state[3:0] = IDLE;
else
vb_data_entry_next_state[3:0] = WAIT_REQ;
GET_SNQ_DATA:
if(vb_data_entry_pass_data0_vld || vb_data_entry_pass_data1_vld)
vb_data_entry_next_state[3:0] = REQ_CD_CHANNEL;
else
vb_data_entry_next_state[3:0] = GET_SNQ_DATA;
REQ_CD_CHANNEL:
if(sdb_inv_en & sdb_bypass_readonce)
vb_data_entry_next_state[3:0] = REQ_WRITE_ADDR;
else if(sdb_inv_en)
vb_data_entry_next_state[3:0] = IDLE;
else
vb_data_entry_next_state[3:0] = REQ_CD_CHANNEL;
default:vb_data_entry_next_state[3:0] = IDLE;
endcase
// &CombEnd; @258
end
//==========================================================
// State 1 : get data
//==========================================================
//when sdb get data,critial first
assign sdb_bypass_reverse = sdb_vld
&& sdb_start_bias[1];
assign vb_data_entry_pass_data0_vld = ld_da_vb_borrow_vb
&& (vb_data_entry_data_bias[0] ^ sdb_bypass_reverse);
assign vb_data_entry_pass_data1_vld = ld_da_vb_borrow_vb
&& (vb_data_entry_data_bias[1] ^ sdb_bypass_reverse);
//==========================================================
// State 4 : grnt write data
//==========================================================
assign vb_data_entry_pop_vld = vb_wd_sm_data_pop_req;
assign vb_data_entry_write_data128[127:0] = {128{vb_wd_sm_data_bias[0]}} & vb_data_entry_data[127:0]
| {128{vb_wd_sm_data_bias[1]}} & vb_data_entry_data[255:128]
| {128{vb_wd_sm_data_bias[2]}} & vb_data_entry_data[383:256]
| {128{vb_wd_sm_data_bias[3]}} & vb_data_entry_data[511:384];
//==========================================================
// Snoop signal
//==========================================================
assign vb_sdb_data_entry_vld = |vb_data_entry_state[3:2];
assign sdb_vld = !vb_data_entry_state[3] && vb_data_entry_state[2];
assign sdb_data_vld = (vb_data_entry_state[3:0] == REQ_CD_CHANNEL);
assign sdb_entry_avail = !vb_sdb_data_entry_vld && !vb_data_entry_create_vld;
//snoop data
// &CombBeg; @291
always @( sdb_start_bias[1:0]
or sdb_entry_data_index[3:0])
begin
case(sdb_start_bias[1:0])
2'b00: sdb_return_order[3:0] = sdb_entry_data_index[3:0];
2'b01: sdb_return_order[3:0] = {sdb_entry_data_index[2:0],sdb_entry_data_index[3]};
2'b10: sdb_return_order[3:0] = {sdb_entry_data_index[1:0],sdb_entry_data_index[3:2]};
2'b11: sdb_return_order[3:0] = {sdb_entry_data_index[0],sdb_entry_data_index[3:1]};
default:sdb_return_order[3:0] = {4{1'bx}};
endcase
// &CombEnd; @299
end
assign sdb_entry_data[127:0] = {128{sdb_return_order[0]}} & vb_data_entry_data[127:0]
| {128{sdb_return_order[1]}} & vb_data_entry_data[255:128]
| {128{sdb_return_order[2]}} & vb_data_entry_data[383:256]
| {128{sdb_return_order[3]}} & vb_data_entry_data[511:384];
//for data dep or bypass
assign vb_data_entry_req_success = (vb_data_entry_state[3:0] == REQ_WRITE_ADDR) && vb_data_entry_biu_req_success
|| (vb_data_entry_state[3:0] == REQ_WRITE_DATA)
|| (vb_data_entry_state[3:0] == GRNT_WRITE_DATA);
//bypass should pop vb addr entry
assign vb_data_bypass_pop = (vb_data_entry_state[3:0] == WAIT_REQ)
&& (snq_vb_bypass_start && !snq_vb_bypass_readonce || snq_vb_bypass_invalid);
//when req data success,should ack addr entry not bypass
assign vb_data_normal_pop = (vb_data_entry_state[3:0] == GRNT_WRITE_DATA)
&& vb_data_entry_pop_vld;
//==========================================================
// Generate interface
//==========================================================
//------------------input-----------------------------------
//-----------create signal--------------
assign vb_data_entry_create_vld = vb_data_entry_create_vld_x;
assign vb_data_entry_create_dp_vld = vb_data_entry_create_dp_vld_x;
assign vb_data_entry_create_gateclk_en = vb_data_entry_create_gateclk_en_x;
//-----------grnt signal----------------
assign vb_data_entry_biu_req_success = vb_data_entry_biu_req_success_x;
assign vb_data_entry_wd_sm_grnt = vb_data_entry_wd_sm_grnt_x;
//-----------other signal---------------
assign ld_da_vb_borrow_vb = ld_da_vb_borrow_vb_x;
assign vb_rcl_sm_data_set_data_done = vb_rcl_sm_data_set_data_done_x;
assign vb_wd_sm_data_pop_req = vb_wd_sm_data_pop_req_x;
//----------- for snq--------------
assign snq_vb_bypass_start = snq_vb_bypass_start_x;
assign snq_vb_bypass_invalid = snq_vb_bypass_invalid_x;
assign snq_data_bypass_hit = snq_data_bypass_hit_x;
assign sdb_create_en = sdb_create_en_x;
assign sdb_inv_en = sdb_inv_en_x;
//------------------output----------------------------------
//----------- entry signal--------------
assign vb_sdb_data_entry_vld_x = vb_sdb_data_entry_vld;
assign vb_data_entry_vld_x = vb_data_entry_vld;
assign vb_data_entry_dirty_x = vb_data_entry_dirty;
assign vb_data_entry_lfb_create_x = vb_data_entry_lfb_create;
assign vb_data_entry_inv_x = vb_data_entry_inv;
assign vb_data_entry_addr_id_v[1:0] = vb_data_entry_addr_id[1:0];
//-----------request--------------------
assign vb_data_entry_biu_req_x = vb_data_entry_biu_req;
assign vb_data_entry_wd_sm_req_x = vb_data_entry_wd_sm_req;
//-----------other signal---------------
assign vb_data_entry_write_data128_v[127:0] = vb_data_entry_write_data128[127:0];
assign vb_data_entry_req_success_x = vb_data_entry_req_success;
assign vb_data_entry_bypass_pop_x = vb_data_bypass_pop;
assign vb_data_entry_normal_pop_x = vb_data_normal_pop;
//----------- for snq--------------
assign sdb_vld_x = sdb_vld;
assign sdb_data_vld_x = sdb_data_vld;
assign sdb_entry_avail_x = sdb_entry_avail;
assign sdb_entry_data_v[127:0] = sdb_entry_data[127:0];
// &ModuleEnd; @368
endmodule |
module ct_lsu_vb_sdb_data(
cp0_lsu_icg_en,
cpurst_b,
forever_cpuclk,
ld_da_data256,
ld_da_vb_borrow_vb,
pad_yy_icg_scan_en,
sdb_create_data_order,
sdb_create_en,
sdb_data_vld,
sdb_entry_avail,
sdb_entry_data_0,
sdb_entry_data_1,
sdb_entry_data_2,
sdb_entry_data_index,
sdb_inv_en,
sdb_vld,
snq_data_bypass_hit,
snq_vb_bypass_invalid,
snq_vb_bypass_readonce,
snq_vb_bypass_start,
vb_data_entry_addr_id_0,
vb_data_entry_addr_id_1,
vb_data_entry_addr_id_2,
vb_data_entry_biu_req,
vb_data_entry_biu_req_success,
vb_data_entry_bypass_pop,
vb_data_entry_create_dp_vld,
vb_data_entry_create_gateclk_en,
vb_data_entry_create_vld,
vb_data_entry_dirty,
vb_data_entry_inv,
vb_data_entry_lfb_create,
vb_data_entry_normal_pop,
vb_data_entry_req_success,
vb_data_entry_vld,
vb_data_entry_wd_sm_grnt,
vb_data_entry_wd_sm_req,
vb_data_entry_write_data128_0,
vb_data_entry_write_data128_1,
vb_data_entry_write_data128_2,
vb_rcl_sm_addr_id,
vb_rcl_sm_data_dcache_dirty,
vb_rcl_sm_data_set_data_done,
vb_rcl_sm_inv,
vb_rcl_sm_lfb_create,
vb_sdb_data_entry_vld,
vb_wd_sm_data_bias,
vb_wd_sm_data_pop_req
);
// &Ports; @26
input cp0_lsu_icg_en;
input cpurst_b;
input forever_cpuclk;
input [255:0] ld_da_data256;
input [2 :0] ld_da_vb_borrow_vb;
input pad_yy_icg_scan_en;
input [1 :0] sdb_create_data_order;
input [2 :0] sdb_create_en;
input [3 :0] sdb_entry_data_index;
input [2 :0] sdb_inv_en;
input [2 :0] snq_data_bypass_hit;
input [2 :0] snq_vb_bypass_invalid;
input snq_vb_bypass_readonce;
input [2 :0] snq_vb_bypass_start;
input [2 :0] vb_data_entry_biu_req_success;
input [2 :0] vb_data_entry_create_dp_vld;
input [2 :0] vb_data_entry_create_gateclk_en;
input [2 :0] vb_data_entry_create_vld;
input [2 :0] vb_data_entry_wd_sm_grnt;
input [1 :0] vb_rcl_sm_addr_id;
input vb_rcl_sm_data_dcache_dirty;
input [2 :0] vb_rcl_sm_data_set_data_done;
input vb_rcl_sm_inv;
input vb_rcl_sm_lfb_create;
input [3 :0] vb_wd_sm_data_bias;
input [2 :0] vb_wd_sm_data_pop_req;
output [2 :0] sdb_data_vld;
output [2 :0] sdb_entry_avail;
output [127:0] sdb_entry_data_0;
output [127:0] sdb_entry_data_1;
output [127:0] sdb_entry_data_2;
output [2 :0] sdb_vld;
output [1 :0] vb_data_entry_addr_id_0;
output [1 :0] vb_data_entry_addr_id_1;
output [1 :0] vb_data_entry_addr_id_2;
output [2 :0] vb_data_entry_biu_req;
output [2 :0] vb_data_entry_bypass_pop;
output [2 :0] vb_data_entry_dirty;
output [2 :0] vb_data_entry_inv;
output [2 :0] vb_data_entry_lfb_create;
output [2 :0] vb_data_entry_normal_pop;
output [2 :0] vb_data_entry_req_success;
output [2 :0] vb_data_entry_vld;
output [2 :0] vb_data_entry_wd_sm_req;
output [127:0] vb_data_entry_write_data128_0;
output [127:0] vb_data_entry_write_data128_1;
output [127:0] vb_data_entry_write_data128_2;
output [2 :0] vb_sdb_data_entry_vld;
// &Regs; @27
// &Wires; @28
wire cp0_lsu_icg_en;
wire cpurst_b;
wire forever_cpuclk;
wire [255:0] ld_da_data256;
wire [2 :0] ld_da_vb_borrow_vb;
wire pad_yy_icg_scan_en;
wire [1 :0] sdb_create_data_order;
wire [2 :0] sdb_create_en;
wire [2 :0] sdb_data_vld;
wire [2 :0] sdb_entry_avail;
wire [127:0] sdb_entry_data_0;
wire [127:0] sdb_entry_data_1;
wire [127:0] sdb_entry_data_2;
wire [3 :0] sdb_entry_data_index;
wire [2 :0] sdb_inv_en;
wire [2 :0] sdb_vld;
wire [2 :0] snq_data_bypass_hit;
wire [2 :0] snq_vb_bypass_invalid;
wire snq_vb_bypass_readonce;
wire [2 :0] snq_vb_bypass_start;
wire [1 :0] vb_data_entry_addr_id_0;
wire [1 :0] vb_data_entry_addr_id_1;
wire [1 :0] vb_data_entry_addr_id_2;
wire [2 :0] vb_data_entry_biu_req;
wire [2 :0] vb_data_entry_biu_req_success;
wire [2 :0] vb_data_entry_bypass_pop;
wire [2 :0] vb_data_entry_create_dp_vld;
wire [2 :0] vb_data_entry_create_gateclk_en;
wire [2 :0] vb_data_entry_create_vld;
wire [2 :0] vb_data_entry_dirty;
wire [2 :0] vb_data_entry_inv;
wire [2 :0] vb_data_entry_lfb_create;
wire [2 :0] vb_data_entry_normal_pop;
wire [2 :0] vb_data_entry_req_success;
wire [2 :0] vb_data_entry_vld;
wire [2 :0] vb_data_entry_wd_sm_grnt;
wire [2 :0] vb_data_entry_wd_sm_req;
wire [127:0] vb_data_entry_write_data128_0;
wire [127:0] vb_data_entry_write_data128_1;
wire [127:0] vb_data_entry_write_data128_2;
wire [1 :0] vb_rcl_sm_addr_id;
wire vb_rcl_sm_data_dcache_dirty;
wire [2 :0] vb_rcl_sm_data_set_data_done;
wire vb_rcl_sm_inv;
wire vb_rcl_sm_lfb_create;
wire [2 :0] vb_sdb_data_entry_vld;
wire [3 :0] vb_wd_sm_data_bias;
wire [2 :0] vb_wd_sm_data_pop_req;
parameter DATA_ENTRY = 3;
//==========================================================
// Instance data entry
//==========================================================
//3 data entry(share with sdb)
// &ConnRule(s/_x$/[0]/); @36
// &ConnRule(s/_v$/_0/); @37
// &Instance("ct_lsu_vb_sdb_data_entry","x_ct_lsu_vb_sdb_data_entry_0"); @38
ct_lsu_vb_sdb_data_entry x_ct_lsu_vb_sdb_data_entry_0 (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_da_data256 (ld_da_data256 ),
.ld_da_vb_borrow_vb_x (ld_da_vb_borrow_vb[0] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.sdb_create_data_order (sdb_create_data_order ),
.sdb_create_en_x (sdb_create_en[0] ),
.sdb_data_vld_x (sdb_data_vld[0] ),
.sdb_entry_avail_x (sdb_entry_avail[0] ),
.sdb_entry_data_index (sdb_entry_data_index ),
.sdb_entry_data_v (sdb_entry_data_0 ),
.sdb_inv_en_x (sdb_inv_en[0] ),
.sdb_vld_x (sdb_vld[0] ),
.snq_data_bypass_hit_x (snq_data_bypass_hit[0] ),
.snq_vb_bypass_invalid_x (snq_vb_bypass_invalid[0] ),
.snq_vb_bypass_readonce (snq_vb_bypass_readonce ),
.snq_vb_bypass_start_x (snq_vb_bypass_start[0] ),
.vb_data_entry_addr_id_v (vb_data_entry_addr_id_0 ),
.vb_data_entry_biu_req_success_x (vb_data_entry_biu_req_success[0] ),
.vb_data_entry_biu_req_x (vb_data_entry_biu_req[0] ),
.vb_data_entry_bypass_pop_x (vb_data_entry_bypass_pop[0] ),
.vb_data_entry_create_dp_vld_x (vb_data_entry_create_dp_vld[0] ),
.vb_data_entry_create_gateclk_en_x (vb_data_entry_create_gateclk_en[0]),
.vb_data_entry_create_vld_x (vb_data_entry_create_vld[0] ),
.vb_data_entry_dirty_x (vb_data_entry_dirty[0] ),
.vb_data_entry_inv_x (vb_data_entry_inv[0] ),
.vb_data_entry_lfb_create_x (vb_data_entry_lfb_create[0] ),
.vb_data_entry_normal_pop_x (vb_data_entry_normal_pop[0] ),
.vb_data_entry_req_success_x (vb_data_entry_req_success[0] ),
.vb_data_entry_vld_x (vb_data_entry_vld[0] ),
.vb_data_entry_wd_sm_grnt_x (vb_data_entry_wd_sm_grnt[0] ),
.vb_data_entry_wd_sm_req_x (vb_data_entry_wd_sm_req[0] ),
.vb_data_entry_write_data128_v (vb_data_entry_write_data128_0 ),
.vb_rcl_sm_addr_id (vb_rcl_sm_addr_id ),
.vb_rcl_sm_data_dcache_dirty (vb_rcl_sm_data_dcache_dirty ),
.vb_rcl_sm_data_set_data_done_x (vb_rcl_sm_data_set_data_done[0] ),
.vb_rcl_sm_inv (vb_rcl_sm_inv ),
.vb_rcl_sm_lfb_create (vb_rcl_sm_lfb_create ),
.vb_sdb_data_entry_vld_x (vb_sdb_data_entry_vld[0] ),
.vb_wd_sm_data_bias (vb_wd_sm_data_bias ),
.vb_wd_sm_data_pop_req_x (vb_wd_sm_data_pop_req[0] )
);
// &ConnRule(s/_x$/[1]/); @40
// &ConnRule(s/_v$/_1/); @41
// &Instance("ct_lsu_vb_sdb_data_entry","x_ct_lsu_vb_sdb_data_entry_1"); @42
ct_lsu_vb_sdb_data_entry x_ct_lsu_vb_sdb_data_entry_1 (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_da_data256 (ld_da_data256 ),
.ld_da_vb_borrow_vb_x (ld_da_vb_borrow_vb[1] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.sdb_create_data_order (sdb_create_data_order ),
.sdb_create_en_x (sdb_create_en[1] ),
.sdb_data_vld_x (sdb_data_vld[1] ),
.sdb_entry_avail_x (sdb_entry_avail[1] ),
.sdb_entry_data_index (sdb_entry_data_index ),
.sdb_entry_data_v (sdb_entry_data_1 ),
.sdb_inv_en_x (sdb_inv_en[1] ),
.sdb_vld_x (sdb_vld[1] ),
.snq_data_bypass_hit_x (snq_data_bypass_hit[1] ),
.snq_vb_bypass_invalid_x (snq_vb_bypass_invalid[1] ),
.snq_vb_bypass_readonce (snq_vb_bypass_readonce ),
.snq_vb_bypass_start_x (snq_vb_bypass_start[1] ),
.vb_data_entry_addr_id_v (vb_data_entry_addr_id_1 ),
.vb_data_entry_biu_req_success_x (vb_data_entry_biu_req_success[1] ),
.vb_data_entry_biu_req_x (vb_data_entry_biu_req[1] ),
.vb_data_entry_bypass_pop_x (vb_data_entry_bypass_pop[1] ),
.vb_data_entry_create_dp_vld_x (vb_data_entry_create_dp_vld[1] ),
.vb_data_entry_create_gateclk_en_x (vb_data_entry_create_gateclk_en[1]),
.vb_data_entry_create_vld_x (vb_data_entry_create_vld[1] ),
.vb_data_entry_dirty_x (vb_data_entry_dirty[1] ),
.vb_data_entry_inv_x (vb_data_entry_inv[1] ),
.vb_data_entry_lfb_create_x (vb_data_entry_lfb_create[1] ),
.vb_data_entry_normal_pop_x (vb_data_entry_normal_pop[1] ),
.vb_data_entry_req_success_x (vb_data_entry_req_success[1] ),
.vb_data_entry_vld_x (vb_data_entry_vld[1] ),
.vb_data_entry_wd_sm_grnt_x (vb_data_entry_wd_sm_grnt[1] ),
.vb_data_entry_wd_sm_req_x (vb_data_entry_wd_sm_req[1] ),
.vb_data_entry_write_data128_v (vb_data_entry_write_data128_1 ),
.vb_rcl_sm_addr_id (vb_rcl_sm_addr_id ),
.vb_rcl_sm_data_dcache_dirty (vb_rcl_sm_data_dcache_dirty ),
.vb_rcl_sm_data_set_data_done_x (vb_rcl_sm_data_set_data_done[1] ),
.vb_rcl_sm_inv (vb_rcl_sm_inv ),
.vb_rcl_sm_lfb_create (vb_rcl_sm_lfb_create ),
.vb_sdb_data_entry_vld_x (vb_sdb_data_entry_vld[1] ),
.vb_wd_sm_data_bias (vb_wd_sm_data_bias ),
.vb_wd_sm_data_pop_req_x (vb_wd_sm_data_pop_req[1] )
);
// &ConnRule(s/_x$/[2]/); @44
// &ConnRule(s/_v$/_2/); @45
// &Instance("ct_lsu_vb_sdb_data_entry","x_ct_lsu_vb_sdb_data_entry_2"); @46
ct_lsu_vb_sdb_data_entry x_ct_lsu_vb_sdb_data_entry_2 (
.cp0_lsu_icg_en (cp0_lsu_icg_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ld_da_data256 (ld_da_data256 ),
.ld_da_vb_borrow_vb_x (ld_da_vb_borrow_vb[2] ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.sdb_create_data_order (sdb_create_data_order ),
.sdb_create_en_x (sdb_create_en[2] ),
.sdb_data_vld_x (sdb_data_vld[2] ),
.sdb_entry_avail_x (sdb_entry_avail[2] ),
.sdb_entry_data_index (sdb_entry_data_index ),
.sdb_entry_data_v (sdb_entry_data_2 ),
.sdb_inv_en_x (sdb_inv_en[2] ),
.sdb_vld_x (sdb_vld[2] ),
.snq_data_bypass_hit_x (snq_data_bypass_hit[2] ),
.snq_vb_bypass_invalid_x (snq_vb_bypass_invalid[2] ),
.snq_vb_bypass_readonce (snq_vb_bypass_readonce ),
.snq_vb_bypass_start_x (snq_vb_bypass_start[2] ),
.vb_data_entry_addr_id_v (vb_data_entry_addr_id_2 ),
.vb_data_entry_biu_req_success_x (vb_data_entry_biu_req_success[2] ),
.vb_data_entry_biu_req_x (vb_data_entry_biu_req[2] ),
.vb_data_entry_bypass_pop_x (vb_data_entry_bypass_pop[2] ),
.vb_data_entry_create_dp_vld_x (vb_data_entry_create_dp_vld[2] ),
.vb_data_entry_create_gateclk_en_x (vb_data_entry_create_gateclk_en[2]),
.vb_data_entry_create_vld_x (vb_data_entry_create_vld[2] ),
.vb_data_entry_dirty_x (vb_data_entry_dirty[2] ),
.vb_data_entry_inv_x (vb_data_entry_inv[2] ),
.vb_data_entry_lfb_create_x (vb_data_entry_lfb_create[2] ),
.vb_data_entry_normal_pop_x (vb_data_entry_normal_pop[2] ),
.vb_data_entry_req_success_x (vb_data_entry_req_success[2] ),
.vb_data_entry_vld_x (vb_data_entry_vld[2] ),
.vb_data_entry_wd_sm_grnt_x (vb_data_entry_wd_sm_grnt[2] ),
.vb_data_entry_wd_sm_req_x (vb_data_entry_wd_sm_req[2] ),
.vb_data_entry_write_data128_v (vb_data_entry_write_data128_2 ),
.vb_rcl_sm_addr_id (vb_rcl_sm_addr_id ),
.vb_rcl_sm_data_dcache_dirty (vb_rcl_sm_data_dcache_dirty ),
.vb_rcl_sm_data_set_data_done_x (vb_rcl_sm_data_set_data_done[2] ),
.vb_rcl_sm_inv (vb_rcl_sm_inv ),
.vb_rcl_sm_lfb_create (vb_rcl_sm_lfb_create ),
.vb_sdb_data_entry_vld_x (vb_sdb_data_entry_vld[2] ),
.vb_wd_sm_data_bias (vb_wd_sm_data_bias ),
.vb_wd_sm_data_pop_req_x (vb_wd_sm_data_pop_req[2] )
);
//==========================================================
// Interface with VB
//==========================================================
//input
//output
//==========================================================
// Interface with SNQ
//==========================================================
//input
//output
// &ModuleEnd; @62
endmodule |
module ct_lsu_lfb_data_entry(
biu_lsu_r_data,
biu_lsu_r_last,
biu_lsu_r_vld,
cp0_lsu_dcache_en,
cp0_lsu_icg_en,
cp0_yy_clk_en,
cpurst_b,
lfb_addr_entry_linefill_abort,
lfb_addr_entry_linefill_permit,
lfb_biu_id_2to0,
lfb_biu_r_id_hit,
lfb_data_entry_addr_id_v,
lfb_data_entry_addr_pop_req_v,
lfb_data_entry_create_dp_vld_x,
lfb_data_entry_create_gateclk_en_x,
lfb_data_entry_create_vld_x,
lfb_data_entry_data_v,
lfb_data_entry_dcache_share_x,
lfb_data_entry_full_x,
lfb_data_entry_last_x,
lfb_data_entry_lf_sm_req_x,
lfb_data_entry_vld_x,
lfb_data_entry_wait_surplus_x,
lfb_first_pass_ptr,
lfb_lf_sm_data_grnt_x,
lfb_lf_sm_data_pop_req_x,
lfb_r_resp_err,
lfb_r_resp_share,
lsu_special_clk,
pad_yy_icg_scan_en,
snq_lfb_bypass_chg_tag_x,
snq_lfb_bypass_invalid_x
);
// &Ports; @28
input [127:0] biu_lsu_r_data;
input biu_lsu_r_last;
input biu_lsu_r_vld;
input cp0_lsu_dcache_en;
input cp0_lsu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [7 :0] lfb_addr_entry_linefill_abort;
input [7 :0] lfb_addr_entry_linefill_permit;
input [2 :0] lfb_biu_id_2to0;
input lfb_biu_r_id_hit;
input lfb_data_entry_create_dp_vld_x;
input lfb_data_entry_create_gateclk_en_x;
input lfb_data_entry_create_vld_x;
input [3 :0] lfb_first_pass_ptr;
input lfb_lf_sm_data_grnt_x;
input lfb_lf_sm_data_pop_req_x;
input lfb_r_resp_err;
input lfb_r_resp_share;
input lsu_special_clk;
input pad_yy_icg_scan_en;
input snq_lfb_bypass_chg_tag_x;
input snq_lfb_bypass_invalid_x;
output [7 :0] lfb_data_entry_addr_id_v;
output [7 :0] lfb_data_entry_addr_pop_req_v;
output [511:0] lfb_data_entry_data_v;
output lfb_data_entry_dcache_share_x;
output lfb_data_entry_full_x;
output lfb_data_entry_last_x;
output lfb_data_entry_lf_sm_req_x;
output lfb_data_entry_vld_x;
output lfb_data_entry_wait_surplus_x;
// &Regs; @29
reg [7 :0] lfb_data_entry_addr_id;
reg [2 :0] lfb_data_entry_biu_id;
reg lfb_data_entry_bus_err;
reg [1 :0] lfb_data_entry_cnt;
reg [511:0] lfb_data_entry_data;
reg lfb_data_entry_dcache_share;
reg lfb_data_entry_last;
reg lfb_data_entry_lf_sm_req_success;
reg [3 :0] lfb_data_entry_pass_ptr;
reg lfb_data_entry_vld;
// &Wires; @30
wire [127:0] biu_lsu_r_data;
wire biu_lsu_r_last;
wire biu_lsu_r_vld;
wire cp0_lsu_dcache_en;
wire cp0_lsu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [7 :0] lfb_addr_entry_linefill_abort;
wire [7 :0] lfb_addr_entry_linefill_permit;
wire [2 :0] lfb_biu_id_2to0;
wire lfb_biu_r_id_hit;
wire lfb_data_entry_abort;
wire [7 :0] lfb_data_entry_addr_id_v;
wire [7 :0] lfb_data_entry_addr_pop_req;
wire [7 :0] lfb_data_entry_addr_pop_req_v;
wire lfb_data_entry_clk;
wire lfb_data_entry_clk_en;
wire lfb_data_entry_create_dp_vld;
wire lfb_data_entry_create_dp_vld_x;
wire lfb_data_entry_create_gateclk_en;
wire lfb_data_entry_create_gateclk_en_x;
wire lfb_data_entry_create_vld;
wire lfb_data_entry_create_vld_x;
wire lfb_data_entry_data0_clk;
wire lfb_data_entry_data0_clk_en;
wire lfb_data_entry_data1_clk;
wire lfb_data_entry_data1_clk_en;
wire lfb_data_entry_data2_clk;
wire lfb_data_entry_data2_clk_en;
wire lfb_data_entry_data3_clk;
wire lfb_data_entry_data3_clk_en;
wire lfb_data_entry_data_clk;
wire lfb_data_entry_data_clk_en;
wire [511:0] lfb_data_entry_data_v;
wire lfb_data_entry_dcache_share_x;
wire lfb_data_entry_finish_line;
wire lfb_data_entry_finish_once;
wire lfb_data_entry_full;
wire lfb_data_entry_full_x;
wire lfb_data_entry_last_x;
wire lfb_data_entry_lf_sm_req;
wire lfb_data_entry_lf_sm_req_x;
wire lfb_data_entry_linefill_abort;
wire lfb_data_entry_linefill_permit;
wire lfb_data_entry_pass_3times;
wire lfb_data_entry_pass_data0_vld;
wire lfb_data_entry_pass_data1_vld;
wire lfb_data_entry_pass_data2_vld;
wire lfb_data_entry_pass_data3_vld;
wire lfb_data_entry_pass_data_last;
wire lfb_data_entry_pass_data_vld;
wire lfb_data_entry_pop_vld;
wire lfb_data_entry_r_id_hit;
wire lfb_data_entry_vld_x;
wire lfb_data_entry_wait_surplus;
wire lfb_data_entry_wait_surplus_x;
wire [3 :0] lfb_first_pass_ptr;
wire lfb_lf_sm_data_grnt;
wire lfb_lf_sm_data_grnt_x;
wire lfb_lf_sm_data_pop_req;
wire lfb_lf_sm_data_pop_req_x;
wire lfb_r_resp_err;
wire lfb_r_resp_share;
wire lsu_special_clk;
wire pad_yy_icg_scan_en;
wire snq_lfb_bypass_chg_tag;
wire snq_lfb_bypass_chg_tag_x;
wire snq_lfb_bypass_invalid;
wire snq_lfb_bypass_invalid_x;
parameter LFB_ADDR_ENTRY = 8;
//==========================================================
// Instance of Gated Cell
//==========================================================
//-----------entry gateclk--------------
//normal gateclk ,open when create || entry_vld
assign lfb_data_entry_clk_en = lfb_data_entry_vld
|| lfb_data_entry_create_gateclk_en;
// &Instance("gated_clk_cell", "x_lsu_lfb_data_entry_gated_clk"); @41
gated_clk_cell x_lsu_lfb_data_entry_gated_clk (
.clk_in (lsu_special_clk ),
.clk_out (lfb_data_entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lfb_data_entry_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (lsu_special_clk ), @42
// .external_en (1'b0 ), @43
// .global_en (cp0_yy_clk_en ), @44
// .module_en (cp0_lsu_icg_en ), @45
// .local_en (lfb_data_entry_clk_en), @46
// .clk_out (lfb_data_entry_clk )); @47
//-----------data gateclk---------------
assign lfb_data_entry_data_clk_en = lfb_data_entry_pass_data_vld;
// &Instance("gated_clk_cell", "x_lsu_lfb_data_entry_data_gated_clk"); @51
gated_clk_cell x_lsu_lfb_data_entry_data_gated_clk (
.clk_in (lsu_special_clk ),
.clk_out (lfb_data_entry_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lfb_data_entry_data_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (lsu_special_clk ), @52
// .external_en (1'b0 ), @53
// .global_en (cp0_yy_clk_en ), @54
// .module_en (cp0_lsu_icg_en ), @55
// .local_en (lfb_data_entry_data_clk_en), @56
// .clk_out (lfb_data_entry_data_clk)); @57
assign lfb_data_entry_data0_clk_en = lfb_data_entry_pass_data0_vld;
// &Instance("gated_clk_cell", "x_lsu_lfb_data_entry_data0_gated_clk"); @60
gated_clk_cell x_lsu_lfb_data_entry_data0_gated_clk (
.clk_in (lsu_special_clk ),
.clk_out (lfb_data_entry_data0_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lfb_data_entry_data0_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (lsu_special_clk ), @61
// .external_en (1'b0 ), @62
// .global_en (cp0_yy_clk_en ), @63
// .module_en (cp0_lsu_icg_en ), @64
// .local_en (lfb_data_entry_data0_clk_en), @65
// .clk_out (lfb_data_entry_data0_clk)); @66
assign lfb_data_entry_data1_clk_en = lfb_data_entry_pass_data1_vld;
// &Instance("gated_clk_cell", "x_lsu_lfb_data_entry_data1_gated_clk"); @69
gated_clk_cell x_lsu_lfb_data_entry_data1_gated_clk (
.clk_in (lsu_special_clk ),
.clk_out (lfb_data_entry_data1_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lfb_data_entry_data1_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (lsu_special_clk ), @70
// .external_en (1'b0 ), @71
// .global_en (cp0_yy_clk_en ), @72
// .module_en (cp0_lsu_icg_en ), @73
// .local_en (lfb_data_entry_data1_clk_en), @74
// .clk_out (lfb_data_entry_data1_clk)); @75
assign lfb_data_entry_data2_clk_en = lfb_data_entry_pass_data2_vld;
// &Instance("gated_clk_cell", "x_lsu_lfb_data_entry_data2_gated_clk"); @78
gated_clk_cell x_lsu_lfb_data_entry_data2_gated_clk (
.clk_in (lsu_special_clk ),
.clk_out (lfb_data_entry_data2_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lfb_data_entry_data2_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (lsu_special_clk ), @79
// .external_en (1'b0 ), @80
// .global_en (cp0_yy_clk_en ), @81
// .module_en (cp0_lsu_icg_en ), @82
// .local_en (lfb_data_entry_data2_clk_en), @83
// .clk_out (lfb_data_entry_data2_clk)); @84
assign lfb_data_entry_data3_clk_en = lfb_data_entry_pass_data3_vld;
// &Instance("gated_clk_cell", "x_lsu_lfb_data_entry_data3_gated_clk"); @87
gated_clk_cell x_lsu_lfb_data_entry_data3_gated_clk (
.clk_in (lsu_special_clk ),
.clk_out (lfb_data_entry_data3_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lfb_data_entry_data3_clk_en),
.module_en (cp0_lsu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (lsu_special_clk ), @88
// .external_en (1'b0 ), @89
// .global_en (cp0_yy_clk_en ), @90
// .module_en (cp0_lsu_icg_en ), @91
// .local_en (lfb_data_entry_data3_clk_en), @92
// .clk_out (lfb_data_entry_data3_clk)); @93
//==========================================================
// Registers
//==========================================================
//+-----------+
//| entry_vld |
//+-----------+
always @(posedge lfb_data_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lfb_data_entry_vld <= 1'b0;
else if(lfb_data_entry_pop_vld)
lfb_data_entry_vld <= 1'b0;
else if(lfb_data_entry_create_vld)
lfb_data_entry_vld <= 1'b1;
end
//+--------------------+
//| addr_entry_id/r_id |
//+--------------------+
always @(posedge lfb_data_entry_data_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lfb_data_entry_biu_id[2:0] <= 3'b0;
else if(lfb_data_entry_create_dp_vld)
lfb_data_entry_biu_id[2:0] <= lfb_biu_id_2to0[2:0];
end
//+-------------+-----+------------+
//| cache share | cnt | bypass_ptr |
//+-------------+-----+------------+
always @(posedge lfb_data_entry_data_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
lfb_data_entry_cnt[1:0] <= 2'b0;
lfb_data_entry_last <= 1'b0;
lfb_data_entry_pass_ptr[3:0] <= 4'b1;
end
else if(lfb_data_entry_create_dp_vld)
begin
lfb_data_entry_cnt[1:0] <= 2'b0;
lfb_data_entry_last <= biu_lsu_r_last;
lfb_data_entry_pass_ptr[3:0] <= {lfb_first_pass_ptr[2:0],
lfb_first_pass_ptr[3]};
end
else if(lfb_data_entry_pass_data_vld)
begin
lfb_data_entry_cnt[1:0] <= lfb_data_entry_cnt[1:0] + 2'b1;
lfb_data_entry_last <= biu_lsu_r_last;
lfb_data_entry_pass_ptr[3:0] <= {lfb_data_entry_pass_ptr[2:0],
lfb_data_entry_pass_ptr[3]};
end
end
always @(posedge lfb_data_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
lfb_data_entry_dcache_share <= 1'b0;
end
else if(lfb_data_entry_create_dp_vld)
begin
lfb_data_entry_dcache_share <= lfb_r_resp_share;
end
else if(lfb_data_entry_pass_data_vld)
begin
lfb_data_entry_dcache_share <= lfb_r_resp_share;
end
else if(snq_lfb_bypass_chg_tag)
begin
lfb_data_entry_dcache_share <= 1'b1;
end
end
//+-----------+
//| bus error |
//+-----------+
always @(posedge lfb_data_entry_data_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lfb_data_entry_bus_err <= 1'b0;
else if(lfb_data_entry_create_dp_vld)
lfb_data_entry_bus_err <= lfb_r_resp_err;
else if(lfb_data_entry_pass_data_vld && lfb_r_resp_err)
lfb_data_entry_bus_err <= 1'b1;
end
//+------+
//| data |
//+------+
always @(posedge lfb_data_entry_data0_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lfb_data_entry_data[127:0] <= 128'b0;
else if(lfb_data_entry_pass_data0_vld)
lfb_data_entry_data[127:0] <= biu_lsu_r_data[127:0];
end
always @(posedge lfb_data_entry_data1_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lfb_data_entry_data[255:128] <= 128'b0;
else if(lfb_data_entry_pass_data1_vld)
lfb_data_entry_data[255:128] <= biu_lsu_r_data[127:0];
end
always @(posedge lfb_data_entry_data2_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lfb_data_entry_data[383:256] <= 128'b0;
else if(lfb_data_entry_pass_data2_vld)
lfb_data_entry_data[383:256] <= biu_lsu_r_data[127:0];
end
always @(posedge lfb_data_entry_data3_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lfb_data_entry_data[511:384] <= 128'b0;
else if(lfb_data_entry_pass_data3_vld)
lfb_data_entry_data[511:384] <= biu_lsu_r_data[127:0];
end
//+-------------------+
//| lf_sm_req_success |
//+-------------------+
always @(posedge lfb_data_entry_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lfb_data_entry_lf_sm_req_success <= 1'b0;
else if(lfb_data_entry_create_dp_vld)
lfb_data_entry_lf_sm_req_success <= 1'b0;
else if(lfb_lf_sm_data_grnt)
lfb_data_entry_lf_sm_req_success <= 1'b1;
end
//==========================================================
// Wires
//==========================================================
//---------------------full signal--------------------------
assign lfb_data_entry_full = lfb_data_entry_vld
&& lfb_data_entry_last;
//wait surplus means, though this entry is vld, but it hasn't received all data
assign lfb_data_entry_wait_surplus = lfb_data_entry_vld
&& !lfb_data_entry_last;
//------------------pass data signal------------------------
assign lfb_data_entry_r_id_hit = lfb_data_entry_vld
&& biu_lsu_r_vld
&& lfb_biu_r_id_hit
&& (lfb_data_entry_biu_id[2:0]
== lfb_biu_id_2to0[2:0]);
assign lfb_data_entry_pass_data_vld = lfb_data_entry_create_dp_vld
|| lfb_data_entry_r_id_hit;
assign lfb_data_entry_pass_data0_vld = lfb_data_entry_create_dp_vld
&& lfb_first_pass_ptr[0]
|| lfb_data_entry_r_id_hit
&& lfb_data_entry_pass_ptr[0];
assign lfb_data_entry_pass_data1_vld = lfb_data_entry_create_dp_vld
&& lfb_first_pass_ptr[1]
|| lfb_data_entry_r_id_hit
&& lfb_data_entry_pass_ptr[1];
assign lfb_data_entry_pass_data2_vld = lfb_data_entry_create_dp_vld
&& lfb_first_pass_ptr[2]
|| lfb_data_entry_r_id_hit
&& lfb_data_entry_pass_ptr[2];
assign lfb_data_entry_pass_data3_vld = lfb_data_entry_create_dp_vld
&& lfb_first_pass_ptr[3]
|| lfb_data_entry_r_id_hit
&& lfb_data_entry_pass_ptr[3];
//==========================================================
// Generate req/pop signal
//==========================================================
//------------------last signal---------------------------
assign lfb_data_entry_pass_3times = lfb_data_entry_vld
&& (lfb_data_entry_cnt[1:0] == 2'd2);
assign lfb_data_entry_finish_line = lfb_data_entry_vld
&& (lfb_data_entry_cnt[1:0] == 2'd3)
&& lfb_data_entry_last;
assign lfb_data_entry_finish_once = lfb_data_entry_vld
&& (lfb_data_entry_cnt[1:0] == 2'd0)
&& lfb_data_entry_last;
assign lfb_data_entry_pass_data_last = lfb_data_entry_vld
&& biu_lsu_r_last
&& lfb_data_entry_pass_data_vld;
//------------------addr entry signal-----------------------
// &CombBeg; @289
always @( lfb_data_entry_biu_id[2:0])
begin
lfb_data_entry_addr_id[LFB_ADDR_ENTRY-1:0] = {LFB_ADDR_ENTRY{1'b0}};
case(lfb_data_entry_biu_id[2:0])
3'd0:lfb_data_entry_addr_id[0] = 1'b1;
3'd1:lfb_data_entry_addr_id[1] = 1'b1;
3'd2:lfb_data_entry_addr_id[2] = 1'b1;
3'd3:lfb_data_entry_addr_id[3] = 1'b1;
3'd4:lfb_data_entry_addr_id[4] = 1'b1;
3'd5:lfb_data_entry_addr_id[5] = 1'b1;
3'd6:lfb_data_entry_addr_id[6] = 1'b1;
3'd7:lfb_data_entry_addr_id[7] = 1'b1;
default:lfb_data_entry_addr_id[LFB_ADDR_ENTRY-1:0] = {LFB_ADDR_ENTRY{1'b0}};
endcase
// &CombEnd; @302
end
assign lfb_data_entry_linefill_permit = |(lfb_data_entry_addr_id[LFB_ADDR_ENTRY-1:0]
& lfb_addr_entry_linefill_permit[LFB_ADDR_ENTRY-1:0]);
assign lfb_data_entry_linefill_abort = |(lfb_data_entry_addr_id[LFB_ADDR_ENTRY-1:0]
& lfb_addr_entry_linefill_abort[LFB_ADDR_ENTRY-1:0]);
//if addr entry/bus err/read once should abort
assign lfb_data_entry_abort = lfb_data_entry_finish_once
|| snq_lfb_bypass_invalid
|| lfb_data_entry_finish_line
&& (lfb_data_entry_linefill_abort
|| lfb_data_entry_linefill_permit
&& (lfb_data_entry_bus_err
|| !cp0_lsu_dcache_en));
assign lfb_data_entry_addr_pop_req[LFB_ADDR_ENTRY-1:0] = lfb_data_entry_addr_id[LFB_ADDR_ENTRY-1:0]
& {LFB_ADDR_ENTRY{lfb_data_entry_abort}};
//------------------lf req signal---------------------------
//if get all data already, or get last data this cycle, it will request linefill
//state machine
assign lfb_data_entry_lf_sm_req = lfb_data_entry_vld
&& !lfb_data_entry_lf_sm_req_success
&& !lfb_data_entry_bus_err
&& lfb_data_entry_linefill_permit
&& cp0_lsu_dcache_en
&& (lfb_data_entry_finish_line
|| lfb_data_entry_pass_3times
&& lfb_data_entry_pass_data_last
&& !lfb_r_resp_err);
//------------------pop signal------------------------------
assign lfb_data_entry_pop_vld = lfb_data_entry_abort
|| lfb_lf_sm_data_pop_req;
//==========================================================
// Generate interface
//==========================================================
//------------------input-----------------------------------
//-----------create signal--------------
assign lfb_data_entry_create_vld = lfb_data_entry_create_vld_x;
assign lfb_data_entry_create_dp_vld = lfb_data_entry_create_dp_vld_x;
assign lfb_data_entry_create_gateclk_en = lfb_data_entry_create_gateclk_en_x;
//-----------grnt signal----------------
assign lfb_lf_sm_data_grnt = lfb_lf_sm_data_grnt_x;
//-----------other signal---------------
assign lfb_lf_sm_data_pop_req = lfb_lf_sm_data_pop_req_x;
assign snq_lfb_bypass_invalid = snq_lfb_bypass_invalid_x;
assign snq_lfb_bypass_chg_tag = snq_lfb_bypass_chg_tag_x;
//------------------output----------------------------------
//----------- entry signal--------------
assign lfb_data_entry_vld_x = lfb_data_entry_vld;
assign lfb_data_entry_addr_id_v[LFB_ADDR_ENTRY-1:0] =
lfb_data_entry_addr_id[LFB_ADDR_ENTRY-1:0];
assign lfb_data_entry_dcache_share_x = lfb_data_entry_dcache_share;
assign lfb_data_entry_data_v[511:0] = lfb_data_entry_data[511:0];
assign lfb_data_entry_last_x = lfb_data_entry_last;
assign lfb_data_entry_wait_surplus_x = lfb_data_entry_wait_surplus;
assign lfb_data_entry_full_x = lfb_data_entry_full;
//-----------request--------------------
assign lfb_data_entry_addr_pop_req_v[LFB_ADDR_ENTRY-1:0] = lfb_data_entry_addr_pop_req[LFB_ADDR_ENTRY-1:0];
assign lfb_data_entry_lf_sm_req_x = lfb_data_entry_lf_sm_req;
// &ModuleEnd; @367
endmodule |
module ct_had_etm(
core0_enter_dbg_req_i,
core0_enter_dbg_req_o,
core0_exit_dbg_req_i,
core0_exit_dbg_req_o,
core1_enter_dbg_req_i,
core1_enter_dbg_req_o,
core1_exit_dbg_req_i,
core1_exit_dbg_req_o,
cpurst_b,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @2
input core0_enter_dbg_req_o;
input core0_exit_dbg_req_o;
input core1_enter_dbg_req_o;
input core1_exit_dbg_req_o;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output core0_enter_dbg_req_i;
output core0_exit_dbg_req_i;
output core1_enter_dbg_req_i;
output core1_exit_dbg_req_i;
// &Regs; @3
// &Wires; @4
wire core0_enter_dbg_req;
wire core0_enter_dbg_req_i;
wire core0_enter_dbg_req_o;
wire core0_enter_dbg_req_o_ff;
wire core0_event_clk_en;
wire core0_exit_dbg_req;
wire core0_exit_dbg_req_i;
wire core0_exit_dbg_req_o;
wire core0_exit_dbg_req_o_ff;
wire core0_tee;
wire core1_enter_dbg_req;
wire core1_enter_dbg_req_i;
wire core1_enter_dbg_req_o;
wire core1_enter_dbg_req_o_ff;
wire core1_event_clk_en;
wire core1_exit_dbg_req;
wire core1_exit_dbg_req_i;
wire core1_exit_dbg_req_o;
wire core1_exit_dbg_req_o_ff;
wire core1_tee;
wire core2_enter_dbg_req;
wire core2_enter_dbg_req_o_ff;
wire core2_event_clk_en;
wire core2_exit_dbg_req;
wire core2_exit_dbg_req_o_ff;
wire core2_tee;
wire core3_enter_dbg_req;
wire core3_enter_dbg_req_o_ff;
wire core3_event_clk_en;
wire core3_exit_dbg_req;
wire core3_exit_dbg_req_o_ff;
wire core3_tee;
wire cpurst_b;
wire event_clk;
wire event_clk_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
// &ConnRule(s/^x_/core0_/); @6
// &Instance("ct_had_etm_if", "x_ct_had_etm_if_core0"); @7
ct_had_etm_if x_ct_had_etm_if_core0 (
.cpurst_b (cpurst_b ),
.event_clk (event_clk ),
.x_enter_dbg_req (core0_enter_dbg_req ),
.x_enter_dbg_req_i (core0_enter_dbg_req_i ),
.x_enter_dbg_req_o (core0_enter_dbg_req_o ),
.x_enter_dbg_req_o_ff (core0_enter_dbg_req_o_ff),
.x_event_clk_en (core0_event_clk_en ),
.x_exit_dbg_req (core0_exit_dbg_req ),
.x_exit_dbg_req_i (core0_exit_dbg_req_i ),
.x_exit_dbg_req_o (core0_exit_dbg_req_o ),
.x_exit_dbg_req_o_ff (core0_exit_dbg_req_o_ff )
);
// &Force("output", "core0_enter_dbg_req_i"); @9
// &Force("output", "core0_exit_dbg_req_i"); @10
// &ConnRule(s/^x_/core1_/); @13
// &Instance("ct_had_etm_if", "x_ct_had_etm_if_core1"); @14
ct_had_etm_if x_ct_had_etm_if_core1 (
.cpurst_b (cpurst_b ),
.event_clk (event_clk ),
.x_enter_dbg_req (core1_enter_dbg_req ),
.x_enter_dbg_req_i (core1_enter_dbg_req_i ),
.x_enter_dbg_req_o (core1_enter_dbg_req_o ),
.x_enter_dbg_req_o_ff (core1_enter_dbg_req_o_ff),
.x_event_clk_en (core1_event_clk_en ),
.x_exit_dbg_req (core1_exit_dbg_req ),
.x_exit_dbg_req_i (core1_exit_dbg_req_i ),
.x_exit_dbg_req_o (core1_exit_dbg_req_o ),
.x_exit_dbg_req_o_ff (core1_exit_dbg_req_o_ff )
);
// &Force("output", "core1_enter_dbg_req_i"); @16
// &Force("output", "core1_exit_dbg_req_i"); @17
// &Force("nonport", "core1_enter_dbg_req"); @22
// &Force("nonport", "core1_exit_dbg_req"); @23
// &ConnRule(s/^x_/core2_/); @27
// &Instance("ct_had_etm_if", "x_ct_had_etm_if_core2"); @28
// &Force("output", "core2_enter_dbg_req_i"); @30
// &Force("output", "core2_exit_dbg_req_i"); @31
assign core2_enter_dbg_req_o_ff = 1'b0;
assign core2_exit_dbg_req_o_ff = 1'b0;
assign core2_event_clk_en = 1'b0;
// &Force("nonport", "core2_enter_dbg_req"); @36
// &Force("nonport", "core2_exit_dbg_req"); @37
// &ConnRule(s/^x_/core3_/); @41
// &Instance("ct_had_etm_if", "x_ct_had_etm_if_core3"); @42
// &Force("output", "core3_enter_dbg_req_i"); @44
// &Force("output", "core3_exit_dbg_req_i"); @45
assign core3_enter_dbg_req_o_ff = 1'b0;
assign core3_exit_dbg_req_o_ff = 1'b0;
assign core3_event_clk_en = 1'b0;
// &Force("nonport", "core3_enter_dbg_req"); @50
// &Force("nonport", "core3_exit_dbg_req"); @51
assign core0_tee = 1'b0;
assign core1_tee = 1'b0;
assign core2_tee = 1'b0;
assign core3_tee = 1'b0;
assign core0_enter_dbg_req =
(core1_enter_dbg_req_o_ff && (core0_tee == core1_tee) ||
core2_enter_dbg_req_o_ff && (core0_tee == core2_tee) ||
core3_enter_dbg_req_o_ff && (core0_tee == core3_tee));
assign core1_enter_dbg_req =
(core0_enter_dbg_req_o_ff && (core1_tee == core0_tee) ||
core2_enter_dbg_req_o_ff && (core1_tee == core2_tee) ||
core3_enter_dbg_req_o_ff && (core1_tee == core3_tee));
assign core2_enter_dbg_req =
(core0_enter_dbg_req_o_ff && (core2_tee == core0_tee) ||
core1_enter_dbg_req_o_ff && (core2_tee == core1_tee) ||
core3_enter_dbg_req_o_ff && (core2_tee == core3_tee));
assign core3_enter_dbg_req =
(core0_enter_dbg_req_o_ff && (core3_tee == core0_tee) ||
core1_enter_dbg_req_o_ff && (core3_tee == core1_tee) ||
core2_enter_dbg_req_o_ff && (core3_tee == core2_tee));
assign core0_exit_dbg_req =
(core1_exit_dbg_req_o_ff && (core0_tee == core1_tee) ||
core2_exit_dbg_req_o_ff && (core0_tee == core2_tee) ||
core3_exit_dbg_req_o_ff && (core0_tee == core3_tee));
assign core1_exit_dbg_req =
(core0_exit_dbg_req_o_ff && (core1_tee == core0_tee) ||
core2_exit_dbg_req_o_ff && (core1_tee == core2_tee) ||
core3_exit_dbg_req_o_ff && (core1_tee == core3_tee));
assign core2_exit_dbg_req =
(core0_exit_dbg_req_o_ff && (core2_tee == core0_tee) ||
core1_exit_dbg_req_o_ff && (core2_tee == core1_tee) ||
core3_exit_dbg_req_o_ff && (core2_tee == core3_tee));
assign core3_exit_dbg_req =
(core0_exit_dbg_req_o_ff && (core3_tee == core0_tee) ||
core1_exit_dbg_req_o_ff && (core3_tee == core1_tee) ||
core2_exit_dbg_req_o_ff && (core3_tee == core2_tee));
assign event_clk_en = core0_event_clk_en
| core1_event_clk_en
| core2_event_clk_en
| core3_event_clk_en;
// &Instance("gated_clk_cell", "x_ct_event_io_gated_clk"); @113
gated_clk_cell x_ct_event_io_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (event_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (event_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @114
// .external_en (1'b0), @115
// .global_en (1'b1), @116
// .module_en (1'b0), @117
// .local_en (event_clk_en), @118
// .clk_out (event_clk)); @119
// &ModuleEnd; @121
endmodule |
module ct_had_event(
cpuclk,
cpurst_b,
ctrl_event_dbgenter,
ctrl_event_dbgexit,
event_ctrl_enter_dbg,
event_ctrl_exit_dbg,
event_ctrl_had_clk_en,
forever_coreclk,
regs_event_enter_ie,
regs_event_enter_oe,
regs_event_exit_ie,
regs_event_exit_oe,
rtu_yy_xx_dbgon,
x_enter_dbg_req_i,
x_enter_dbg_req_o,
x_exit_dbg_req_i,
x_exit_dbg_req_o
);
// &Ports; @24
input cpuclk;
input cpurst_b;
input ctrl_event_dbgenter;
input ctrl_event_dbgexit;
input forever_coreclk;
input regs_event_enter_ie;
input regs_event_enter_oe;
input regs_event_exit_ie;
input regs_event_exit_oe;
input rtu_yy_xx_dbgon;
input x_enter_dbg_req_i;
input x_exit_dbg_req_i;
output event_ctrl_enter_dbg;
output event_ctrl_exit_dbg;
output event_ctrl_had_clk_en;
output x_enter_dbg_req_o;
output x_exit_dbg_req_o;
// &Regs; @25
reg enter_dbg_req_i;
reg enter_dbg_req_o;
reg exit_dbg_req_o;
reg x_enter_dbg_req_i_f;
reg x_enter_dbg_req_i_sync;
reg x_exit_dbg_req_i_f;
reg x_exit_dbg_req_i_sync;
// &Wires; @26
wire cpuclk;
wire cpurst_b;
wire ctrl_event_dbgenter;
wire ctrl_event_dbgexit;
wire event_ctrl_enter_dbg;
wire event_ctrl_exit_dbg;
wire event_ctrl_had_clk_en;
wire forever_coreclk;
wire regs_event_enter_ie;
wire regs_event_enter_oe;
wire regs_event_exit_ie;
wire regs_event_exit_oe;
wire rtu_yy_xx_dbgon;
wire x_enter_dbg_req_i;
wire x_enter_dbg_req_o;
wire x_enter_dbg_req_o_sync;
wire x_exit_dbg_req_i;
wire x_exit_dbg_req_o;
wire x_exit_dbg_req_o_sync;
//==========================================================
// Input Sync
//==========================================================
// &Instance("sync_level2pulse", "x_ct_sync_enter_dbg_req_i"); @32
// &Connect(.clk (forever_coreclk), @33
// .rst_b (cpurst_b), @34
// .sync_in (x_enter_dbg_req_i), @35
// .sync_out (x_enter_dbg_req_i_sync), @36
// .sync_ack (x_enter_dbg_req_i_ack) @37
// ); @38
// &Instance("sync_level2pulse", "x_ct_sync_exit_dbg_req_i"); @40
// &Connect(.clk (forever_coreclk), @41
// .rst_b (cpurst_b), @42
// .sync_in (x_exit_dbg_req_i), @43
// .sync_out (x_exit_dbg_req_i_sync), @44
// .sync_ack (x_exit_dbg_req_i_ack) @45
// ); @46
always @ (posedge forever_coreclk or negedge cpurst_b)
begin
if (~cpurst_b) begin
x_enter_dbg_req_i_f <= 1'b0;
x_enter_dbg_req_i_sync <= 1'b0;
x_exit_dbg_req_i_f <= 1'b0;
x_exit_dbg_req_i_sync <= 1'b0;
end
else begin
x_enter_dbg_req_i_f <= x_enter_dbg_req_i;
x_enter_dbg_req_i_sync <= x_enter_dbg_req_i_f;
x_exit_dbg_req_i_f <= x_exit_dbg_req_i;
x_exit_dbg_req_i_sync <= x_exit_dbg_req_i_f;
end
end
//==========================================================
// Input Ctrl
//==========================================================
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
enter_dbg_req_i <= 1'b0;
else if (x_enter_dbg_req_i_sync & regs_event_enter_ie)
enter_dbg_req_i <= 1'b1;
else if (rtu_yy_xx_dbgon)
enter_dbg_req_i <= 1'b0;
end
assign event_ctrl_enter_dbg = enter_dbg_req_i;
assign event_ctrl_exit_dbg = x_exit_dbg_req_i_sync & regs_event_exit_ie;
//assign x_event_enter_dbg_req_i = enter_dbg_req_i;
//==========================================================
// Output Ctrl
//==========================================================
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
exit_dbg_req_o <= 1'b0;
else
exit_dbg_req_o <= ctrl_event_dbgexit;
end
assign x_exit_dbg_req_o_sync = exit_dbg_req_o && regs_event_exit_oe;
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
enter_dbg_req_o <= 1'b0;
else
enter_dbg_req_o <= ctrl_event_dbgenter;
end
assign x_enter_dbg_req_o_sync = enter_dbg_req_o && regs_event_enter_oe;
//==========================================================
// Output Sync
//==========================================================
// &Force("input", "x_exit_dbg_req_o_ack"); @119
// &Force("input", "forever_coreclk"); @120
// &Force("nonport", "x_exit_dbg_req_o_ack_sync"); @121
// &Force("input", "x_enter_dbg_req_o_ack"); @141
// &Force("input", "forever_coreclk"); @142
// &Force("nonport", "x_enter_dbg_req_o_ack_sync"); @143
assign x_exit_dbg_req_o = x_exit_dbg_req_o_sync;
assign x_enter_dbg_req_o = x_enter_dbg_req_o_sync;
assign event_ctrl_had_clk_en = x_enter_dbg_req_i_sync
|| x_exit_dbg_req_i_sync;
// &ModuleEnd; @163
endmodule |
module ct_had_common_dbg_info(
ciu_had_dbg_info,
core0_dbg_ack_pc,
core1_dbg_ack_pc,
cpurst_b,
dbgfifo2_data,
dbgfifo2_read_ren,
forever_cpuclk,
l2c_had_dbg_info,
pad_yy_icg_scan_en
);
// &Ports; @25
input [292:0] ciu_had_dbg_info;
input core0_dbg_ack_pc;
input core1_dbg_ack_pc;
input cpurst_b;
input dbgfifo2_read_ren;
input forever_cpuclk;
input [43 :0] l2c_had_dbg_info;
input pad_yy_icg_scan_en;
output [63 :0] dbgfifo2_data;
// &Regs; @26
reg dbg_ack_info_f;
reg [2 :0] dbg_rptr;
reg [63 :0] dbginfo_dout;
reg [336:0] xx_dbg_info_reg;
// &Wires; @27
wire [292:0] ciu_had_dbg_info;
wire core0_dbg_ack_pc;
wire core0_dbg_ack_pc_sync;
wire core1_dbg_ack_pc;
wire core1_dbg_ack_pc_sync;
wire core2_dbg_ack_pc_sync;
wire core3_dbg_ack_pc_sync;
wire cpurst_b;
wire dbg_ack_info;
wire dbg_info_record;
wire dbg_rptr_done;
wire [63 :0] dbgfifo2_data;
wire dbgfifo2_read_ren;
wire dbginfo_clk;
wire dbginfo_clk_en;
wire forever_cpuclk;
wire had_dbg_ack_pc;
wire [43 :0] l2c_had_dbg_info;
wire pad_yy_icg_scan_en;
wire [336:0] xx_dbg_info;
wire [383:0] xx_dbg_info_reg_padding;
//==========================================================
// DBGINFO ACK
//==========================================================
// &Instance("sync_level2pulse", "x_ct_core0_dbg_ack_pc"); @33
// &Connect(.clk (forever_cpuclk), @34
// .rst_b (cpurst_b), @35
// .sync_in (core0_dbg_ack_pc), @36
// .sync_out (core0_dbg_ack_pc_sync), @37
// .sync_ack (core0_dbg_ack_pc_ack) @38
// ); @39
assign core0_dbg_ack_pc_sync = core0_dbg_ack_pc;
// &Instance("sync_level2pulse", "x_ct_core1_dbg_ack_pc"); @46
// &Connect(.clk (forever_cpuclk), @47
// .rst_b (cpurst_b), @48
// .sync_in (core1_dbg_ack_pc), @49
// .sync_out (core1_dbg_ack_pc_sync), @50
// .sync_ack (core1_dbg_ack_pc_ack) @51
// ); @52
assign core1_dbg_ack_pc_sync = core1_dbg_ack_pc;
// &Instance("sync_level2pulse", "x_ct_core2_dbg_ack_pc"); @63
// &Connect(.clk (forever_cpuclk), @64
// .rst_b (cpurst_b), @65
// .sync_in (core2_dbg_ack_pc), @66
// .sync_out (core2_dbg_ack_pc_sync), @67
// .sync_ack (core2_dbg_ack_pc_ack) @68
// ); @69
assign core2_dbg_ack_pc_sync = 1'b0;
// &Instance("sync_level2pulse", "x_ct_core3_dbg_ack_pc"); @79
// &Connect(.clk (forever_cpuclk), @80
// .rst_b (cpurst_b), @81
// .sync_in (core3_dbg_ack_pc), @82
// .sync_out (core3_dbg_ack_pc_sync), @83
// .sync_ack (core3_dbg_ack_pc_ack) @84
// ); @85
assign core3_dbg_ack_pc_sync = 1'b0;
assign had_dbg_ack_pc = core0_dbg_ack_pc_sync
| core1_dbg_ack_pc_sync
| core2_dbg_ack_pc_sync
| core3_dbg_ack_pc_sync;
parameter DBG_WIDTH = 64;
parameter DBG_RPTR_WIDTH = 3;
parameter DBG_DEPTH = 6;
//==========================================================
// DBGINFO FIFO Read
//==========================================================
//csky vperl_off
wire [DBG_WIDTH-1:0] dbginfo_reg[DBG_DEPTH-1:0];
genvar i;
generate
for (i = 0; i < DBG_DEPTH; i = i+1)
begin: DBG_FIFO
assign dbginfo_reg[i][DBG_WIDTH-1:0] = xx_dbg_info_reg_padding[DBG_WIDTH*i+:DBG_WIDTH];
end
endgenerate
//csky vperl_on
always @(posedge dbginfo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
dbginfo_dout[DBG_WIDTH-1:0] <= {DBG_WIDTH{1'b0}};
//csky vperl_off
else if (dbgfifo2_read_ren)
dbginfo_dout[DBG_WIDTH-1:0] <= dbginfo_reg[dbg_rptr[DBG_RPTR_WIDTH-1:0]][DBG_WIDTH-1:0];
//csky vperl_on
else
dbginfo_dout[DBG_WIDTH-1:0] <= dbginfo_dout[DBG_WIDTH-1:0];
end
assign dbgfifo2_data[DBG_WIDTH-1:0] = dbginfo_dout[DBG_WIDTH-1:0];
//==========================================================
// DBGINFO FIFO Write
//==========================================================
assign dbg_ack_info = had_dbg_ack_pc;
always @ (posedge dbginfo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
dbg_ack_info_f <= 1'b0;
else
dbg_ack_info_f <= dbg_ack_info;
end
assign dbg_info_record = dbg_ack_info && !dbg_ack_info_f;
parameter DBG_INFO_WIDTH = 337;
assign xx_dbg_info[DBG_INFO_WIDTH-1:0] = {
l2c_had_dbg_info[43:0],
ciu_had_dbg_info[292:0]
};
always @ (posedge dbginfo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
xx_dbg_info_reg <= {DBG_INFO_WIDTH{1'b0}};
else if (dbg_info_record)
xx_dbg_info_reg <= xx_dbg_info[DBG_INFO_WIDTH-1:0];
end
assign xx_dbg_info_reg_padding[DBG_WIDTH*DBG_DEPTH-1:0] = {
{(DBG_WIDTH*DBG_DEPTH-DBG_INFO_WIDTH){1'b0}},
xx_dbg_info_reg[DBG_INFO_WIDTH-1:0]
};
// &Force("nonport", "xx_dbg_info_reg"); @167
// &Force("nonport", "xx_dbg_info_reg_padding"); @168
//==========================================================
// DBGINFO FIFO Read Pointer
//==========================================================
always @ (posedge dbginfo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
dbg_rptr[DBG_RPTR_WIDTH-1:0] <= {DBG_RPTR_WIDTH{1'b0}};
else if (dbgfifo2_read_ren)
dbg_rptr[DBG_RPTR_WIDTH-1:0] <= {dbg_rptr[DBG_RPTR_WIDTH-1:0] + 1'b1};
else if (dbg_rptr_done)
dbg_rptr[DBG_RPTR_WIDTH-1:0] <= {DBG_RPTR_WIDTH{1'b0}};
end
assign dbg_rptr_done = dbg_rptr[DBG_RPTR_WIDTH-1:0] == DBG_DEPTH;
assign dbginfo_clk_en = dbgfifo2_read_ren
|| dbg_ack_info
|| dbg_ack_info_f
|| dbg_rptr_done;
// &Instance("gated_clk_cell", "x_dbginfo_clk"); @189
gated_clk_cell x_dbginfo_clk (
.clk_in (forever_cpuclk ),
.clk_out (dbginfo_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (dbginfo_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @190
// .external_en (1'b0), @191
// .global_en (1'b1), @192
// .module_en (1'b0), @193
// .local_en (dbginfo_clk_en), @194
// .clk_out (dbginfo_clk)); @195
// &ModuleEnd; @198
endmodule |
module ct_had_nirv_bkpt(
cpuclk,
cpurst_b,
ctrl_bkpta_en,
ctrl_bkptb_en,
nirv_bkpta,
non_irv_bkpt_vld,
regs_xx_nirven,
rtu_had_inst0_non_irv_bkpt,
rtu_had_inst1_non_irv_bkpt,
rtu_had_inst2_non_irv_bkpt,
rtu_had_xx_split_inst,
rtu_yy_xx_dbgon,
rtu_yy_xx_flush,
rtu_yy_xx_retire0_normal,
rtu_yy_xx_retire1,
rtu_yy_xx_retire2
);
// &Ports; @24
input cpuclk;
input cpurst_b;
input ctrl_bkpta_en;
input ctrl_bkptb_en;
input regs_xx_nirven;
input [3:0] rtu_had_inst0_non_irv_bkpt;
input [3:0] rtu_had_inst1_non_irv_bkpt;
input [3:0] rtu_had_inst2_non_irv_bkpt;
input rtu_had_xx_split_inst;
input rtu_yy_xx_dbgon;
input rtu_yy_xx_flush;
input rtu_yy_xx_retire0_normal;
input rtu_yy_xx_retire1;
input rtu_yy_xx_retire2;
output nirv_bkpta;
output non_irv_bkpt_vld;
// &Regs; @25
reg nirv_bkpt_pending;
reg nirv_bkpta;
reg nirv_bkpta_pending;
reg non_irv_bkpt_vld;
// &Wires; @26
wire cpuclk;
wire cpurst_b;
wire ctrl_bkpta_en;
wire ctrl_bkptb_en;
wire [3:0] inst0_non_irv_bkpt;
wire [3:0] inst1_non_irv_bkpt;
wire [3:0] inst2_non_irv_bkpt;
wire kbpt_occur;
wire nirv_bkpt_occur_raw;
wire nirv_bkpta_occur;
wire nirv_bkpta_sel;
wire nirv_bkptb_occur;
wire regs_xx_nirven;
wire [3:0] rtu_had_inst0_non_irv_bkpt;
wire [3:0] rtu_had_inst1_non_irv_bkpt;
wire [3:0] rtu_had_inst2_non_irv_bkpt;
wire rtu_had_xx_split_inst;
wire rtu_yy_xx_dbgon;
wire rtu_yy_xx_flush;
wire rtu_yy_xx_retire0_normal;
wire rtu_yy_xx_retire1;
wire rtu_yy_xx_retire2;
assign inst0_non_irv_bkpt[3:0] = rtu_had_inst0_non_irv_bkpt[3:0] & {4{rtu_yy_xx_retire0_normal}};
assign inst1_non_irv_bkpt[3:0] = rtu_had_inst1_non_irv_bkpt[3:0] & {4{rtu_yy_xx_retire1}};
assign inst2_non_irv_bkpt[3:0] = rtu_had_inst2_non_irv_bkpt[3:0] & {4{rtu_yy_xx_retire2}};
assign nirv_bkpta_occur = inst0_non_irv_bkpt[1] || inst0_non_irv_bkpt[2] ||
inst1_non_irv_bkpt[1] || inst1_non_irv_bkpt[2] ||
inst2_non_irv_bkpt[1] || inst2_non_irv_bkpt[2];
assign nirv_bkptb_occur = inst0_non_irv_bkpt[0] || inst0_non_irv_bkpt[3] ||
inst1_non_irv_bkpt[0] || inst1_non_irv_bkpt[3] ||
inst2_non_irv_bkpt[0] || inst2_non_irv_bkpt[3];
assign kbpt_occur = regs_xx_nirven &&
(nirv_bkpta_occur && ctrl_bkpta_en || nirv_bkptb_occur && ctrl_bkptb_en) ;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
nirv_bkpt_pending <= 1'b0;
else if (rtu_yy_xx_flush)
nirv_bkpt_pending <= 1'b0;
else if (kbpt_occur && rtu_had_xx_split_inst)
nirv_bkpt_pending <= 1'b1;
else if (rtu_yy_xx_dbgon)
nirv_bkpt_pending <= 1'b0;
end
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
nirv_bkpta_pending <= 1'b0;
else if (kbpt_occur && rtu_had_xx_split_inst && !nirv_bkpt_pending)
nirv_bkpta_pending <= nirv_bkpta_occur;
else if (rtu_yy_xx_dbgon)
nirv_bkpta_pending <= 1'b0;
end
assign nirv_bkpt_occur_raw = kbpt_occur && !rtu_had_xx_split_inst ||
nirv_bkpt_pending && !rtu_had_xx_split_inst && rtu_yy_xx_retire0_normal;
// &Force("output","non_irv_bkpt_vld"); @68
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
non_irv_bkpt_vld <= 1'b0;
else if (rtu_yy_xx_flush)
non_irv_bkpt_vld <= 1'b0;
else if (nirv_bkpt_occur_raw)
non_irv_bkpt_vld <= 1'b1;
else if (rtu_yy_xx_dbgon)
non_irv_bkpt_vld <= 1'b0;
end
assign nirv_bkpta_sel = nirv_bkpt_pending ? nirv_bkpta_pending : nirv_bkpta_occur;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
nirv_bkpta <= 1'b0;
else if (nirv_bkpt_occur_raw && !non_irv_bkpt_vld)
nirv_bkpta <= nirv_bkpta_sel;
else if (rtu_yy_xx_dbgon)
nirv_bkpta <= 1'b0;
end
// &ModuleEnd; @93
endmodule |
module ct_had_etm_if(
cpurst_b,
event_clk,
x_enter_dbg_req,
x_enter_dbg_req_i,
x_enter_dbg_req_o,
x_enter_dbg_req_o_ff,
x_event_clk_en,
x_exit_dbg_req,
x_exit_dbg_req_i,
x_exit_dbg_req_o,
x_exit_dbg_req_o_ff
);
// &Ports; @25
input cpurst_b;
input event_clk;
input x_enter_dbg_req;
input x_enter_dbg_req_o;
input x_exit_dbg_req;
input x_exit_dbg_req_o;
output x_enter_dbg_req_i;
output x_enter_dbg_req_o_ff;
output x_event_clk_en;
output x_exit_dbg_req_i;
output x_exit_dbg_req_o_ff;
// &Regs; @26
reg x_enter_dbg_req_i;
reg x_enter_dbg_req_o_ff;
reg x_exit_dbg_req_i;
reg x_exit_dbg_req_o_ff;
// &Wires; @27
wire cpurst_b;
wire event_clk;
wire x_enter_dbg_req;
wire x_enter_dbg_req_o;
wire x_event_clk_en;
wire x_exit_dbg_req;
wire x_exit_dbg_req_o;
//==========================================================
// Output Sync
//==========================================================
// &Instance("sync_level2pulse", "x_ct_x_enter_dbg_req_o"); @33
// &Connect(.clk (forever_cpuclk), @34
// .rst_b (cpurst_b), @35
// .sync_in (x_enter_dbg_req_o), @36
// .sync_out (x_enter_dbg_req_o_ff), @37
// .sync_ack (x_enter_dbg_req_o_ack) @38
// ); @39
// &Instance("sync_level2pulse", "x_ct_x_exit_dbg_req_o"); @41
// &Connect(.clk (forever_cpuclk), @42
// .rst_b (cpurst_b), @43
// .sync_in (x_exit_dbg_req_o), @44
// .sync_out (x_exit_dbg_req_o_ff), @45
// .sync_ack (x_exit_dbg_req_o_ack) @46
// ); @47
always @ (posedge event_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
x_enter_dbg_req_o_ff <= 1'b0;
x_exit_dbg_req_o_ff <= 1'b0;
end
else begin
x_enter_dbg_req_o_ff <= x_enter_dbg_req_o;
x_exit_dbg_req_o_ff <= x_exit_dbg_req_o;
end
end
//==========================================================
// Input Sync
//==========================================================
// &Force("input", "x_enter_dbg_req_i_ack"); @75
// &Force("input", "forever_cpuclk"); @76
// &Force("nonport", "x_enter_dbg_req_i_ack_sync"); @77
// &Force("input", "x_exit_dbg_req_i_ack"); @97
// &Force("input", "forever_cpuclk"); @98
// &Force("nonport", "x_exit_dbg_req_i_ack_sync"); @99
always @ (posedge event_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
x_enter_dbg_req_i <= 1'b0;
x_exit_dbg_req_i <= 1'b0;
end
else begin
x_enter_dbg_req_i <= x_enter_dbg_req;
x_exit_dbg_req_i <= x_exit_dbg_req;
end
end
assign x_event_clk_en = x_exit_dbg_req_o_ff | x_exit_dbg_req_o
| x_enter_dbg_req_o_ff | x_enter_dbg_req_o
| x_exit_dbg_req_i | x_exit_dbg_req
| x_enter_dbg_req_i | x_enter_dbg_req;
// &Force("output", "x_exit_dbg_req_i"); @133
// &Force("output", "x_enter_dbg_req_i"); @134
// &Force("output", "x_exit_dbg_req_o_ff"); @135
// &Force("output", "x_enter_dbg_req_o_ff"); @136
// &ModuleEnd; @139
endmodule |
module ct_had_serial(
io_serial_tdi,
ir_xx_baba_reg_sel,
ir_xx_babb_reg_sel,
ir_xx_bama_reg_sel,
ir_xx_bamb_reg_sel,
ir_xx_csr_reg_sel,
ir_xx_daddr_reg_sel,
ir_xx_dbgfifo2_reg_sel,
ir_xx_dbgfifo_reg_sel,
ir_xx_ddata_reg_sel,
ir_xx_mbca_reg_sel,
ir_xx_mbcb_reg_sel,
ir_xx_otc_reg_sel,
ir_xx_pc_reg_sel,
ir_xx_pcfifo_reg_sel,
ir_xx_pipefifo_reg_sel,
ir_xx_wbbr_reg_sel,
regs_serial_data,
serial_io_tdo,
serial_xx_data,
sm_serial_capture_dr,
sm_serial_shift_dr,
sm_serial_shift_ir,
sm_xx_write_en,
tclk,
trst_b
);
// &Ports; @24
input io_serial_tdi;
input ir_xx_baba_reg_sel;
input ir_xx_babb_reg_sel;
input ir_xx_bama_reg_sel;
input ir_xx_bamb_reg_sel;
input ir_xx_csr_reg_sel;
input ir_xx_daddr_reg_sel;
input ir_xx_dbgfifo2_reg_sel;
input ir_xx_dbgfifo_reg_sel;
input ir_xx_ddata_reg_sel;
input ir_xx_mbca_reg_sel;
input ir_xx_mbcb_reg_sel;
input ir_xx_otc_reg_sel;
input ir_xx_pc_reg_sel;
input ir_xx_pcfifo_reg_sel;
input ir_xx_pipefifo_reg_sel;
input ir_xx_wbbr_reg_sel;
input [63:0] regs_serial_data;
input sm_serial_capture_dr;
input sm_serial_shift_dr;
input sm_serial_shift_ir;
input sm_xx_write_en;
input tclk;
input trst_b;
output serial_io_tdo;
output [63:0] serial_xx_data;
// &Regs; @25
reg parity;
reg [63:0] serial_shifter;
reg [63:0] serial_shifter_pre;
reg tdo;
// &Wires; @26
wire io_serial_tdi;
wire ir_xx_baba_reg_sel;
wire ir_xx_babb_reg_sel;
wire ir_xx_bama_reg_sel;
wire ir_xx_bamb_reg_sel;
wire ir_xx_csr_reg_sel;
wire ir_xx_daddr_reg_sel;
wire ir_xx_dbgfifo2_reg_sel;
wire ir_xx_dbgfifo_reg_sel;
wire ir_xx_ddata_reg_sel;
wire ir_xx_mbca_reg_sel;
wire ir_xx_mbcb_reg_sel;
wire ir_xx_otc_reg_sel;
wire ir_xx_pc_reg_sel;
wire ir_xx_pcfifo_reg_sel;
wire ir_xx_pipefifo_reg_sel;
wire ir_xx_wbbr_reg_sel;
wire [63:0] regs_serial_data;
wire serial_io_tdo;
wire serial_shifter_16_sel;
wire serial_shifter_32_sel;
wire serial_shifter_64_sel;
wire serial_shifter_8_sel;
wire [63:0] serial_shifter_dr_pre;
wire [63:0] serial_xx_data;
wire sm_serial_capture_dr;
wire sm_serial_shift_dr;
wire sm_serial_shift_ir;
wire sm_xx_write_en;
wire tclk;
wire tdi;
wire trst_b;
//==============================================================================
// data shift in and out
// 1. how to shift IR
// 2. how to capture DR
// 3. how to shift DR in JTAG_2 interface
// 4. how to shift DR in JTAG_5 interface
//==============================================================================
assign serial_shifter_8_sel =
ir_xx_otc_reg_sel
|| ir_xx_mbca_reg_sel
|| ir_xx_mbcb_reg_sel
|| ir_xx_bama_reg_sel
|| ir_xx_bamb_reg_sel;
assign serial_shifter_16_sel =
ir_xx_csr_reg_sel;
assign serial_shifter_32_sel =
!(serial_shifter_8_sel
|| serial_shifter_16_sel
|| serial_shifter_64_sel);
assign serial_shifter_64_sel =
ir_xx_pipefifo_reg_sel
|| ir_xx_baba_reg_sel
|| ir_xx_babb_reg_sel
|| ir_xx_wbbr_reg_sel
|| ir_xx_pc_reg_sel
|| ir_xx_pcfifo_reg_sel
|| ir_xx_daddr_reg_sel
|| ir_xx_dbgfifo_reg_sel
|| ir_xx_dbgfifo2_reg_sel
|| ir_xx_ddata_reg_sel;
assign serial_shifter_dr_pre[63:0] =
{64{serial_shifter_8_sel}} & {56'b0, tdi, serial_shifter[7:1]}
| {64{serial_shifter_16_sel}} & {48'b0, tdi, serial_shifter[15:1]}
| {64{serial_shifter_32_sel}} & {32'b0, tdi, serial_shifter[31:1]}
| {64{serial_shifter_64_sel}} & {tdi,serial_shifter[63:1]};
// &CombBeg; @69
always @( serial_shifter[63:0]
or sm_serial_shift_dr
or sm_serial_capture_dr
or tdi
or serial_shifter_dr_pre[63:0]
or sm_serial_shift_ir
or regs_serial_data[63:0])
begin
serial_shifter_pre[63:0] = 64'b0;
if (sm_serial_shift_ir)
serial_shifter_pre[15:0] = {tdi, serial_shifter[15:1]};
else if (sm_serial_capture_dr)
serial_shifter_pre[63:0] = regs_serial_data[63:0];
else if (sm_serial_shift_dr)
serial_shifter_pre[63:0] = serial_shifter_dr_pre[63:0];
else
serial_shifter_pre[63:0] = serial_shifter[63:0];
// &CombEnd; @79
end
// data shift from the lowest bit
// sample tdi on the posedge of JTAG clock
always @(posedge tclk)
begin
serial_shifter[63:0] <= serial_shifter_pre[63:0];
end
// output signal, data shift in
assign serial_xx_data[63:0] = serial_shifter[63:0];
//==============================================
// calculate the parity bit when read DR
//==============================================
always @(posedge tclk)
begin
if (sm_serial_capture_dr)
parity <= 1'b1;
else if (sm_serial_shift_dr && !sm_xx_write_en)
parity <= parity ^ serial_shifter[0];
else
parity <= parity;
end
//==============================================
// set tdo on the negedge of tclk
// set tdo to logic 1 when IDLE
//==============================================
always @(negedge tclk or negedge trst_b)
begin
if (!trst_b)
tdo <= 1'b1;
else if (sm_serial_shift_dr && !sm_xx_write_en)
tdo <= serial_shifter[0];
else
tdo <= tdo;
end
//==========================================================
// jtag input and output
//==========================================================
assign tdi = io_serial_tdi;
assign serial_io_tdo = tdo;
// &ModuleEnd; @126
endmodule |
module ct_had_io(
had_pad_jtg_tdo,
had_pad_jtg_tdo_en,
io_serial_tdi,
io_sm_tap_en,
pad_had_jtg_tdi,
serial_io_tdo,
sm_io_tdo_en
);
// &Ports; @24
input pad_had_jtg_tdi;
input serial_io_tdo;
input sm_io_tdo_en;
output had_pad_jtg_tdo;
output had_pad_jtg_tdo_en;
output io_serial_tdi;
output io_sm_tap_en;
// &Regs; @25
// &Wires; @26
wire had_pad_jtg_tdo;
wire had_pad_jtg_tdo_en;
wire io_serial_tdi;
wire io_sm_tap_en;
wire pad_had_jtg_tdi;
wire serial_io_tdo;
wire sm_io_tdo_en;
//===============================================================
// JTAG_2 and JTAG_5 interface signals
//===============================================================
// | __
// pad_had_jtg_tdi ----------->|----| \
// | | |----> io_serial_tdi
// pad_had_jtg_tms_i ----------->|----|__/
// | |
// pad_had_jtag2_sel ----------->|-----+
// |
// had_pad_jtg_tdo <-----------|--+
// | |----------- serial_io_tdo
// had_pad_jtg_tms_o <-----------|--+
// |
// had_pad_jtg_tdo_en <-----------|-------------- sm_io_tdo_en
// |
// had_pad_jtg_tms_oe <-----------|-------------- sm_io_tms_oe
// |
//===============================================================
assign io_serial_tdi = pad_had_jtg_tdi;
assign had_pad_jtg_tdo = serial_io_tdo;
assign had_pad_jtg_tdo_en = sm_io_tdo_en;
assign io_sm_tap_en = 1'b1;
// &ModuleEnd; @77
endmodule |
module ct_had_private_ir(
biu_had_coreid,
cpuclk,
cpurst_b,
ctrl_xx_dbg_disable,
forever_coreclk,
ir_corex_wdata,
ir_ctrl_exit_dbg_reg,
ir_ctrl_had_clk_en,
ir_xx_baba_reg_sel,
ir_xx_babb_reg_sel,
ir_xx_bama_reg_sel,
ir_xx_bamb_reg_sel,
ir_xx_csr_reg_sel,
ir_xx_daddr_reg_sel,
ir_xx_dbgfifo_reg_sel,
ir_xx_ddata_reg_sel,
ir_xx_eventie_reg_sel,
ir_xx_eventoe_reg_sel,
ir_xx_hcr_reg_sel,
ir_xx_hsr_reg_sel,
ir_xx_id_reg_sel,
ir_xx_ir_reg_sel,
ir_xx_mbca_reg_sel,
ir_xx_mbcb_reg_sel,
ir_xx_mbir_reg_sel,
ir_xx_otc_reg_sel,
ir_xx_pc_reg_sel,
ir_xx_pcfifo_reg_sel,
ir_xx_pipefifo_reg_sel,
ir_xx_pipesel_reg_sel,
ir_xx_wbbr_reg_sel,
ir_xx_wdata,
sm_update_dr,
sm_update_ir,
x_ir_ctrl_dbgfifo_read_pulse,
x_ir_ctrl_pcfifo_read_pulse,
x_ir_ctrl_pipefifo_read_pulse,
x_ir_xx_ex,
x_ir_xx_go,
x_sm_xx_update_dr_en
);
// &Ports; @24
input [1 :0] biu_had_coreid;
input cpuclk;
input cpurst_b;
input ctrl_xx_dbg_disable;
input forever_coreclk;
input [63:0] ir_corex_wdata;
input sm_update_dr;
input sm_update_ir;
output ir_ctrl_exit_dbg_reg;
output ir_ctrl_had_clk_en;
output ir_xx_baba_reg_sel;
output ir_xx_babb_reg_sel;
output ir_xx_bama_reg_sel;
output ir_xx_bamb_reg_sel;
output ir_xx_csr_reg_sel;
output ir_xx_daddr_reg_sel;
output ir_xx_dbgfifo_reg_sel;
output ir_xx_ddata_reg_sel;
output ir_xx_eventie_reg_sel;
output ir_xx_eventoe_reg_sel;
output ir_xx_hcr_reg_sel;
output ir_xx_hsr_reg_sel;
output ir_xx_id_reg_sel;
output ir_xx_ir_reg_sel;
output ir_xx_mbca_reg_sel;
output ir_xx_mbcb_reg_sel;
output ir_xx_mbir_reg_sel;
output ir_xx_otc_reg_sel;
output ir_xx_pc_reg_sel;
output ir_xx_pcfifo_reg_sel;
output ir_xx_pipefifo_reg_sel;
output ir_xx_pipesel_reg_sel;
output ir_xx_wbbr_reg_sel;
output [63:0] ir_xx_wdata;
output x_ir_ctrl_dbgfifo_read_pulse;
output x_ir_ctrl_pcfifo_read_pulse;
output x_ir_ctrl_pipefifo_read_pulse;
output x_ir_xx_ex;
output x_ir_xx_go;
output x_sm_xx_update_dr_en;
// &Regs; @25
reg [15:0] hacr_f;
reg update_dr_ff1;
reg update_hacr_ff1;
// &Wires; @26
wire bank0_sel;
wire bank1_sel;
wire bank2_sel;
wire [1 :0] biu_had_coreid;
wire core_sel;
wire cpuclk;
wire cpurst_b;
wire ctrl_xx_dbg_disable;
wire dbgfifo_read;
wire forever_coreclk;
wire [4 :0] hacr_index;
wire hacr_rw;
wire hacr_update_en;
wire [63:0] ir_corex_wdata;
wire ir_ctrl_exit_dbg_reg;
wire ir_ctrl_had_clk_en;
wire ir_xx_baba_reg_sel;
wire ir_xx_babb_reg_sel;
wire ir_xx_bama_reg_sel;
wire ir_xx_bamb_reg_sel;
wire ir_xx_bypass_reg_sel;
wire ir_xx_csr_reg_sel;
wire ir_xx_daddr_reg_sel;
wire ir_xx_dbgfifo_reg_sel;
wire ir_xx_ddata_reg_sel;
wire ir_xx_eventie_reg_sel;
wire ir_xx_eventoe_reg_sel;
wire ir_xx_ex;
wire ir_xx_go;
wire ir_xx_hcr_reg_sel;
wire ir_xx_hsr_reg_sel;
wire ir_xx_id_reg_sel;
wire ir_xx_ir_reg_sel;
wire ir_xx_mbca_reg_sel;
wire ir_xx_mbcb_reg_sel;
wire ir_xx_mbir_reg_sel;
wire ir_xx_otc_reg_sel;
wire ir_xx_pc_reg_sel;
wire ir_xx_pcfifo_reg_sel;
wire ir_xx_pipefifo_reg_sel;
wire ir_xx_pipesel_reg_sel;
wire ir_xx_wbbr_reg_sel;
wire [63:0] ir_xx_wdata;
wire pcfifo_read;
wire pipefifo_read;
wire sm_update_dr;
wire sm_update_ir;
wire x_ir_ctrl_dbgfifo_read_pulse;
wire x_ir_ctrl_pcfifo_read_pulse;
wire x_ir_ctrl_pipefifo_read_pulse;
wire x_ir_xx_ex;
wire x_ir_xx_go;
wire x_sm_xx_update_dr_en;
wire x_update_dr_cpu;
wire x_update_dr_cpu_ack;
wire x_update_dr_cpu_raw;
wire x_update_ir_cpu;
wire x_update_ir_cpu_ack;
wire x_update_ir_cpu_raw;
//==========================================================
// DR/IR Generation
//==========================================================
// &Instance("sync_level2pulse", "x_ct_had_private_sync_ir"); @32
sync_level2pulse x_ct_had_private_sync_ir (
.clk (forever_coreclk ),
.rst_b (cpurst_b ),
.sync_ack (x_update_ir_cpu_ack),
.sync_in (sm_update_ir ),
.sync_out (x_update_ir_cpu_raw)
);
// &Connect(.clk (forever_coreclk), @33
// .rst_b (cpurst_b), @34
// .sync_in (sm_update_ir), @35
// .sync_out (x_update_ir_cpu_raw), @36
// .sync_ack (x_update_ir_cpu_ack) @37
// ); @38
assign x_update_ir_cpu = x_update_ir_cpu_raw && !ctrl_xx_dbg_disable;
// &Force("nonport", "x_update_ir_cpu_ack"); @40
// &Instance("sync_level2pulse", "x_ct_had_private_sync_dr"); @42
sync_level2pulse x_ct_had_private_sync_dr (
.clk (forever_coreclk ),
.rst_b (cpurst_b ),
.sync_ack (x_update_dr_cpu_ack),
.sync_in (sm_update_dr ),
.sync_out (x_update_dr_cpu_raw)
);
// &Connect(.clk (forever_coreclk), @43
// .rst_b (cpurst_b), @44
// .sync_in (sm_update_dr), @45
// .sync_out (x_update_dr_cpu_raw), @46
// .sync_ack (x_update_dr_cpu_ack) @47
// ); @48
assign x_update_dr_cpu = x_update_dr_cpu_raw && !ctrl_xx_dbg_disable;
// &Force("nonport", "x_update_dr_cpu_ack"); @50
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)begin
update_hacr_ff1 <= 1'b0;
update_dr_ff1 <= 1'b0;
end
else begin
update_hacr_ff1 <= x_update_ir_cpu;
update_dr_ff1 <= x_update_dr_cpu;
end
end
//==============================================================================
// Update HACR
//==============================================================================
assign hacr_update_en = x_update_ir_cpu; //|(hacr_f[15:0] ^ ir_corex_hacr[15:0]);
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
hacr_f[15:0] <= 16'h8200; // Async reset to point to HAD_ID
else if (hacr_update_en)
hacr_f[15:0] <= ir_corex_wdata[15:0];
end
//==============================================================================
// HACR commond decode
//==============================================================================
parameter ID_NUM = 5'd2;
parameter OTC_NUM = 5'd3;
parameter MBCA_NUM = 5'd4;
parameter MBCB_NUM = 5'd5;
parameter PCFIFO_NUM = 5'd6;
parameter BABA_NUM = 5'd7;
parameter BABB_NUM = 5'd8;
parameter BAMA_NUM = 5'd9;
parameter BAMB_NUM = 5'd10;
parameter BYPASS_NUM = 5'd12;
parameter HCR_NUM = 5'd13;
parameter HSR_NUM = 5'd14;
parameter WBBR_NUM = 5'd17;
parameter PSR_NUM = 5'd18;
parameter PC_NUM = 5'd19;
parameter IR_NUM = 5'd20;
parameter CSR_NUM = 5'd21;
parameter DADDR_NUM = 5'd24;
parameter DDATA_NUM = 5'd25;
assign hacr_rw = hacr_f[15];
assign ir_xx_go = hacr_f[14];
assign ir_xx_ex = hacr_f[13];
assign ir_xx_wdata[63:0] = ir_corex_wdata[63:0];
assign core_sel = (hacr_f[1:0] == biu_had_coreid[1:0]);
assign x_ir_xx_ex = ir_xx_ex && core_sel;
assign x_ir_xx_go = ir_xx_go && core_sel;
assign bank0_sel = (hacr_f[6:4] == 3'd0);
assign bank1_sel = (hacr_f[6:4] == 3'd1);
assign bank2_sel = (hacr_f[6:4] == 3'd2);
assign hacr_index[4:0] = hacr_f[12:8];
assign ir_xx_id_reg_sel = bank0_sel && (hacr_index[4:0] == ID_NUM);
assign ir_xx_otc_reg_sel = bank0_sel && (hacr_index[4:0] == OTC_NUM);
assign ir_xx_mbca_reg_sel = bank0_sel && (hacr_index[4:0] == MBCA_NUM);
assign ir_xx_mbcb_reg_sel = bank0_sel && (hacr_index[4:0] == MBCB_NUM);
assign ir_xx_pcfifo_reg_sel = bank0_sel && (hacr_index[4:0] == PCFIFO_NUM);
assign ir_xx_baba_reg_sel = bank0_sel && (hacr_index[4:0] == BABA_NUM);
assign ir_xx_babb_reg_sel = bank0_sel && (hacr_index[4:0] == BABB_NUM);
assign ir_xx_bama_reg_sel = bank0_sel && (hacr_index[4:0] == BAMA_NUM);
assign ir_xx_bamb_reg_sel = bank0_sel && (hacr_index[4:0] == BAMB_NUM);
assign ir_xx_bypass_reg_sel = bank0_sel && (hacr_index[4:0] == BYPASS_NUM);
assign ir_xx_hcr_reg_sel = bank0_sel && (hacr_index[4:0] == HCR_NUM);
assign ir_xx_hsr_reg_sel = bank0_sel && (hacr_index[4:0] == HSR_NUM);
assign ir_xx_wbbr_reg_sel = bank0_sel && (hacr_index[4:0] == WBBR_NUM);
assign ir_xx_pc_reg_sel = bank0_sel && (hacr_index[4:0] == PC_NUM);
assign ir_xx_ir_reg_sel = bank0_sel && (hacr_index[4:0] == IR_NUM);
assign ir_xx_csr_reg_sel = bank0_sel && (hacr_index[4:0] == CSR_NUM);
assign ir_xx_daddr_reg_sel = bank0_sel && (hacr_index[4:0] == DADDR_NUM);
assign ir_xx_ddata_reg_sel = bank0_sel && (hacr_index[4:0] == DDATA_NUM);
parameter MBIR_NUM = 5'd27;
assign ir_xx_mbir_reg_sel = bank1_sel && (hacr_index[4:0] == MBIR_NUM);
parameter EVENT_OE_NUM = 5'd2;
parameter EVENT_IE_NUM = 5'd3;
parameter DBGFIFO_NUM = 5'd4;
parameter PIPEFIFO_NUM = 5'd5;
parameter PIPESEL_NUM = 5'd6;
assign ir_xx_eventoe_reg_sel = bank2_sel && (hacr_index[4:0] == EVENT_OE_NUM);
assign ir_xx_eventie_reg_sel = bank2_sel && (hacr_index[4:0] == EVENT_IE_NUM);
assign ir_xx_pipefifo_reg_sel = bank2_sel && (hacr_index[4:0] == PIPEFIFO_NUM);
assign ir_xx_pipesel_reg_sel = bank2_sel && (hacr_index[4:0] == PIPESEL_NUM);
assign ir_xx_dbgfifo_reg_sel = bank2_sel && (hacr_index[4:0] == DBGFIFO_NUM);
//================================================
//
//================================================
// &Force("output", "ir_xx_ir_reg_sel"); @152
// &Force("output", "ir_xx_csr_reg_sel"); @153
// &Force("output", "ir_xx_pc_reg_sel"); @154
// &Force("output", "ir_xx_wbbr_reg_sel"); @155
// &Force("output", "ir_xx_pcfifo_reg_sel"); @156
// &Force("output", "ir_xx_pipefifo_reg_sel"); @157
// &Force("output", "ir_xx_dbgfifo_reg_sel"); @158
assign pcfifo_read = hacr_rw && ir_xx_pcfifo_reg_sel;
assign pipefifo_read = hacr_rw && ir_xx_pipefifo_reg_sel;
assign dbgfifo_read = hacr_rw && ir_xx_dbgfifo_reg_sel;
assign x_ir_ctrl_pcfifo_read_pulse = pcfifo_read && update_hacr_ff1 && core_sel;
assign x_ir_ctrl_pipefifo_read_pulse = pipefifo_read && update_hacr_ff1 && core_sel;
assign x_ir_ctrl_dbgfifo_read_pulse = dbgfifo_read && update_hacr_ff1 && core_sel;
assign x_sm_xx_update_dr_en = update_dr_ff1 & !hacr_rw & core_sel;
assign ir_ctrl_exit_dbg_reg = ir_xx_wbbr_reg_sel ||
ir_xx_pc_reg_sel ||
ir_xx_ir_reg_sel ||
ir_xx_csr_reg_sel ||
ir_xx_bypass_reg_sel;
assign ir_ctrl_had_clk_en = x_update_ir_cpu_raw
|| x_update_dr_cpu_raw;
// &ModuleEnd; @180
endmodule |
module ct_had_trace(
cpuclk,
cpurst_b,
ctrl_trace_en,
inst_bkpt_dbgreq,
ir_xx_otc_reg_sel,
ir_xx_wdata,
rtu_had_xx_split_inst,
rtu_yy_xx_dbgon,
rtu_yy_xx_retire0_normal,
trace_ctrl_req,
trace_regs_otc,
x_sm_xx_update_dr_en
);
// &Ports; @24
input cpuclk;
input cpurst_b;
input ctrl_trace_en;
input inst_bkpt_dbgreq;
input ir_xx_otc_reg_sel;
input [63:0] ir_xx_wdata;
input rtu_had_xx_split_inst;
input rtu_yy_xx_dbgon;
input rtu_yy_xx_retire0_normal;
input x_sm_xx_update_dr_en;
output trace_ctrl_req;
output [7 :0] trace_regs_otc;
// &Regs; @25
reg [7 :0] trace_counter;
// &Wires; @26
wire cpuclk;
wire cpurst_b;
wire ctrl_trace_en;
wire inst_bkpt_dbgreq;
wire ir_xx_otc_reg_sel;
wire [63:0] ir_xx_wdata;
wire rtu_had_xx_split_inst;
wire rtu_yy_xx_dbgon;
wire rtu_yy_xx_retire0_normal;
wire trace_counter_dec;
wire trace_counter_eq_0;
wire trace_ctrl_req;
wire [7 :0] trace_regs_otc;
wire trace_vld;
wire x_sm_xx_update_dr_en;
//==============================================================================
// trace valid conditions(AND):
// 1. retire normally, without exception.
// 2. not a split inst or the last of the split inst.
// 3. not in debug mode.
// 4. trace mode enable.
// The last condition is designed for low power.
// when trace mode enable, CPU will retire only one inst in a cycle.
//==============================================================================
assign trace_vld = rtu_yy_xx_retire0_normal &&
!rtu_had_xx_split_inst &&
!rtu_yy_xx_dbgon &&
ctrl_trace_en;
//==============================================================================
// trace counter decrease condition (AND):
// 1. trace valid
// 2. trace counter dosen't equal to zero.
// 3. no mbkpt occurs
//==============================================================================
assign trace_counter_eq_0 = trace_counter[7:0] == 8'b0;
assign trace_counter_dec = trace_vld && !trace_counter_eq_0 && !inst_bkpt_dbgreq;
//==============================================================================
// trace counter maintenance
//==============================================================================
// &Force("bus", "ir_xx_wdata", 63, 0); @57
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
trace_counter[7:0] <= 8'b0;
else if (x_sm_xx_update_dr_en && ir_xx_otc_reg_sel)
trace_counter[7:0] <= ir_xx_wdata[7:0];
else if (trace_counter_dec)
trace_counter[7:0] <= trace_counter[7:0] - 1'b1;
else
trace_counter[7:0] <= trace_counter[7:0];
end
//==========================================================
// trace counter to regs
//==========================================================
assign trace_regs_otc[7:0] = trace_counter[7:0];
//==========================================================
// trace debug request
//==========================================================
// trace request to HAD control path conditions (AND):
// 1. trace_vld
// 2. trace counter equals to zero.
assign trace_ctrl_req = trace_vld && trace_counter_eq_0;
// &ModuleEnd; @86
endmodule |
module ct_had_common_regs(
common_regs_data,
core0_had_dbg_mask,
core0_rst_b,
core1_had_dbg_mask,
core1_rst_b,
dbgfifo2_data,
forever_cpuclk,
ir_xx_core0_sel,
ir_xx_core1_sel,
ir_xx_core2_sel,
ir_xx_core3_sel,
ir_xx_dbgfifo2_reg_sel,
ir_xx_dms_reg_sel,
ir_xx_id_reg_sel,
ir_xx_rsr_reg_sel,
sysio_had_dbg_mask
);
// &Ports; @25
input core0_rst_b;
input core1_rst_b;
input [63:0] dbgfifo2_data;
input forever_cpuclk;
input ir_xx_core0_sel;
input ir_xx_core1_sel;
input ir_xx_core2_sel;
input ir_xx_core3_sel;
input ir_xx_dbgfifo2_reg_sel;
input ir_xx_dms_reg_sel;
input ir_xx_id_reg_sel;
input ir_xx_rsr_reg_sel;
input [3 :0] sysio_had_dbg_mask;
output [63:0] common_regs_data;
output core0_had_dbg_mask;
output core1_had_dbg_mask;
// &Regs; @26
reg core_rst0;
reg core_rst1;
// &Wires; @27
wire [63:0] common_regs_data;
wire core0_had_dbg_mask;
wire core0_rst_b;
wire core1_had_dbg_mask;
wire core1_rst_b;
wire [3 :0] core_rst;
wire core_rst2;
wire core_rst3;
wire [63:0] dbgfifo2_data;
wire [31:0] dms_data;
wire forever_cpuclk;
wire [31:0] id_reg;
wire ir_xx_dbgfifo2_reg_sel;
wire ir_xx_dms_reg_sel;
wire ir_xx_id_reg_sel;
wire ir_xx_rsr_reg_sel;
wire [31:0] rsr_data;
wire [3 :0] sysio_had_dbg_mask;
wire [3 :0] tee_mask;
parameter DATAW = 64;
//==========================================================
// RSR
//==========================================================
always @ (posedge forever_cpuclk or negedge core0_rst_b)
begin
if (!core0_rst_b)
core_rst0 <= 1'b1;
else
core_rst0 <= 1'b0;
end
always @ (posedge forever_cpuclk or negedge core1_rst_b)
begin
if (!core1_rst_b)
core_rst1 <= 1'b1;
else
core_rst1 <= 1'b0;
end
assign core_rst2 = 1'b1;
assign core_rst3 = 1'b1;
assign core_rst[3:0] = {core_rst3, core_rst2, core_rst1, core_rst0};
assign tee_mask[3:0] = 4'b0;
// &Force("input", "ir_xx_core0_sel"); @97
// &Force("input", "ir_xx_core1_sel"); @98
// &Force("input", "ir_xx_core2_sel"); @99
// &Force("input", "ir_xx_core3_sel"); @100
assign rsr_data[31:0] = {28'b0, core_rst[3:0] | tee_mask[3:0]};
//==========================================================
// HAD ID
//==========================================================
// +-------+-----+---------+----+----+-------+------+-----+-----+
// | 31:28 |27:26| 25:18 | 17 | 16 | 15:12 | 11:8 | 7:4 | 3:0 |
// +-------+-----+---------+----+----+-------+------+-----+-----+
// | | | | | | | |
// | | | | | | | +--- ID_VERSION
// | | | | | | +--------- HAD_VERSION
// | | | | | +-------------- HAD_REVISION
// | | | | +---------------------- BKPT_NUM
// | | | +----------------------------- DDC
// | | +---------------------------------- BANK1
// | +--------------------------------------- CPU Inst. Arch
// +---------------------------------------------- JTAG InterfaceType
assign id_reg[31:28] = 4'b0;
assign id_reg[27:26] = 2'b10; //CSKY V3
assign id_reg[25:20] = 6'd0; // -
assign id_reg[19] = 1'b1; //have rsr.
assign id_reg[18] = 1'b1; //hacr_reg is 16 bits
assign id_reg[17] = 1'b0; // BANK1
assign id_reg[16] = 1'b1; // DDC
assign id_reg[15:12] = 4'd2; // BKPT_NUM
//-----------------------------------------
// initial reversion
// assign id_reg[11:8] = 4'b0000;
//-----------------------------------------
// memeory breakpoint logic modify
// current instruction doesnot executing
// but goto debug mode if current maca is 0
// assign id_reg[11:8] = 4'b0001;
//-----------------------------------------
// add HCR[ASR] and cpu dead reason in HSR
//assign id_reg[11:8] = 4'b0010;
// version 2.3
// 1. add DCC handshake
// 2. add TEE support
assign id_reg[11:8] = 4'b1011;
// HAD_VER as ISA version,0000:6xx, 0001:810p, 0010: 8xx, 0011:902, 0100: 960
assign id_reg[7:4] = 4'b0100;
assign id_reg[3:0] = 4'b0011;
//==========================================================
// DMS
//==========================================================
assign dms_data[31:0] = {28'b0, sysio_had_dbg_mask[3:0] & ~tee_mask[3:0]};
assign core0_had_dbg_mask = sysio_had_dbg_mask[0];
assign core1_had_dbg_mask = sysio_had_dbg_mask[1];
//==========================================================
// MUX
//==========================================================
assign common_regs_data[DATAW-1:0] =
{DATAW{ir_xx_dbgfifo2_reg_sel}} & dbgfifo2_data[63:0]
| {DATAW{ir_xx_rsr_reg_sel}} & {{DATAW-32{1'b0}},rsr_data[31:0]}
| {DATAW{ir_xx_id_reg_sel}} & {{DATAW-32{1'b0}},id_reg[31:0]}
| {DATAW{ir_xx_dms_reg_sel}} & {{DATAW-32{1'b0}},dms_data[31:0]};
// &ModuleEnd; @177
endmodule |
module ct_had_ctrl(
biu_had_sdb_req_b,
bkpta_ctrl_data_req,
bkpta_ctrl_data_req_raw,
bkpta_ctrl_inst_req,
bkpta_ctrl_inst_req_raw,
bkpta_ctrl_xx_ack,
bkptb_ctrl_data_req,
bkptb_ctrl_data_req_raw,
bkptb_ctrl_inst_req,
bkptb_ctrl_inst_req_raw,
bkptb_ctrl_xx_ack,
cpuclk,
cpurst_b,
ctrl_bkpta_en,
ctrl_bkpta_en_raw,
ctrl_bkptb_en,
ctrl_bkptb_en_raw,
ctrl_dbgfifo_ren,
ctrl_event_dbgenter,
ctrl_event_dbgexit,
ctrl_pcfifo_ren,
ctrl_pcfifo_wen,
ctrl_pipefifo_ren,
ctrl_pipefifo_wen,
ctrl_regs_bkpta_vld,
ctrl_regs_bkptb_vld,
ctrl_regs_exit_dbg,
ctrl_regs_freeze_pcfifo,
ctrl_regs_set_sqa,
ctrl_regs_set_sqb,
ctrl_regs_update_adro,
ctrl_regs_update_dro,
ctrl_regs_update_mbo,
ctrl_regs_update_pro,
ctrl_regs_update_swo,
ctrl_regs_update_to,
ctrl_trace_en,
ctrl_xx_dbg_disable,
ddc_xx_update_ir,
event_ctrl_enter_dbg,
event_ctrl_exit_dbg,
event_ctrl_had_clk_en,
forever_coreclk,
had_cp0_xx_dbg,
had_ifu_ir_vld,
had_ifu_pcload,
had_rtu_data_bkpt_dbgreq,
had_rtu_dbg_disable,
had_rtu_dbg_req_en,
had_rtu_event_dbgreq,
had_rtu_fdb,
had_rtu_hw_dbgreq,
had_rtu_hw_dbgreq_gateclk,
had_rtu_inst_bkpt_dbgreq,
had_rtu_non_irv_bkpt_dbgreq,
had_rtu_pop1_disa,
had_rtu_trace_dbgreq,
had_rtu_trace_en,
had_rtu_xx_jdbreq,
had_rtu_xx_tme,
had_xx_clk_en,
had_yy_xx_exit_dbg,
inst_bkpt_dbgreq,
ir_ctrl_exit_dbg_reg,
ir_ctrl_had_clk_en,
ir_xx_ir_reg_sel,
nirv_bkpta,
non_irv_bkpt_vld,
regs_ctrl_adr,
regs_ctrl_dr,
regs_ctrl_fdb,
regs_ctrl_frzc,
regs_ctrl_pcfifo_frozen,
regs_ctrl_pm,
regs_ctrl_sqa,
regs_ctrl_sqb,
regs_ctrl_sqc,
regs_ctrl_tme,
regs_xx_bca,
regs_xx_bcb,
regs_xx_ddc_en,
regs_xx_nirven,
rtu_had_dbgreq_ack,
rtu_had_inst0_bkpt_inst,
rtu_yy_xx_dbgon,
rtu_yy_xx_retire0,
rtu_yy_xx_retire0_normal,
trace_ctrl_req,
x_had_dbg_mask,
x_ir_ctrl_dbgfifo_read_pulse,
x_ir_ctrl_pcfifo_read_pulse,
x_ir_ctrl_pipefifo_read_pulse,
x_ir_xx_ex,
x_ir_xx_go,
x_sm_xx_update_dr_en
);
// &Ports; @26
input biu_had_sdb_req_b;
input bkpta_ctrl_data_req;
input bkpta_ctrl_data_req_raw;
input bkpta_ctrl_inst_req;
input bkpta_ctrl_inst_req_raw;
input bkpta_ctrl_xx_ack;
input bkptb_ctrl_data_req;
input bkptb_ctrl_data_req_raw;
input bkptb_ctrl_inst_req;
input bkptb_ctrl_inst_req_raw;
input bkptb_ctrl_xx_ack;
input cpuclk;
input cpurst_b;
input ddc_xx_update_ir;
input event_ctrl_enter_dbg;
input event_ctrl_exit_dbg;
input event_ctrl_had_clk_en;
input forever_coreclk;
input ir_ctrl_exit_dbg_reg;
input ir_ctrl_had_clk_en;
input ir_xx_ir_reg_sel;
input nirv_bkpta;
input non_irv_bkpt_vld;
input regs_ctrl_adr;
input regs_ctrl_dr;
input regs_ctrl_fdb;
input regs_ctrl_frzc;
input regs_ctrl_pcfifo_frozen;
input [1:0] regs_ctrl_pm;
input regs_ctrl_sqa;
input regs_ctrl_sqb;
input [1:0] regs_ctrl_sqc;
input regs_ctrl_tme;
input [4:0] regs_xx_bca;
input [4:0] regs_xx_bcb;
input regs_xx_ddc_en;
input regs_xx_nirven;
input rtu_had_dbgreq_ack;
input rtu_had_inst0_bkpt_inst;
input rtu_yy_xx_dbgon;
input rtu_yy_xx_retire0;
input rtu_yy_xx_retire0_normal;
input trace_ctrl_req;
input x_had_dbg_mask;
input x_ir_ctrl_dbgfifo_read_pulse;
input x_ir_ctrl_pcfifo_read_pulse;
input x_ir_ctrl_pipefifo_read_pulse;
input x_ir_xx_ex;
input x_ir_xx_go;
input x_sm_xx_update_dr_en;
output ctrl_bkpta_en;
output ctrl_bkpta_en_raw;
output ctrl_bkptb_en;
output ctrl_bkptb_en_raw;
output ctrl_dbgfifo_ren;
output ctrl_event_dbgenter;
output ctrl_event_dbgexit;
output ctrl_pcfifo_ren;
output ctrl_pcfifo_wen;
output ctrl_pipefifo_ren;
output ctrl_pipefifo_wen;
output ctrl_regs_bkpta_vld;
output ctrl_regs_bkptb_vld;
output ctrl_regs_exit_dbg;
output ctrl_regs_freeze_pcfifo;
output ctrl_regs_set_sqa;
output ctrl_regs_set_sqb;
output ctrl_regs_update_adro;
output ctrl_regs_update_dro;
output ctrl_regs_update_mbo;
output ctrl_regs_update_pro;
output ctrl_regs_update_swo;
output ctrl_regs_update_to;
output ctrl_trace_en;
output ctrl_xx_dbg_disable;
output had_cp0_xx_dbg;
output had_ifu_ir_vld;
output had_ifu_pcload;
output had_rtu_data_bkpt_dbgreq;
output had_rtu_dbg_disable;
output had_rtu_dbg_req_en;
output had_rtu_event_dbgreq;
output had_rtu_fdb;
output had_rtu_hw_dbgreq;
output had_rtu_hw_dbgreq_gateclk;
output had_rtu_inst_bkpt_dbgreq;
output had_rtu_non_irv_bkpt_dbgreq;
output had_rtu_pop1_disa;
output had_rtu_trace_dbgreq;
output had_rtu_trace_en;
output had_rtu_xx_jdbreq;
output had_rtu_xx_tme;
output had_xx_clk_en;
output had_yy_xx_exit_dbg;
output inst_bkpt_dbgreq;
// &Regs; @27
reg ctrl_bkptb_en;
reg ctrl_exit_dbg;
reg ctrl_go_noex;
reg ctrl_out_dbg_disable;
reg ctrl_trace_en;
reg dr_set_req;
reg event_req;
reg had_clk_en_ff;
// &Wires; @28
wire adr_set_req;
wire async_dbg_req;
wire biu_had_sdb_req_b;
wire bkpta_ctrl_data_req;
wire bkpta_ctrl_data_req_raw;
wire bkpta_ctrl_inst_req;
wire bkpta_ctrl_inst_req_raw;
wire bkpta_ctrl_xx_ack;
wire bkptb_ctrl_data_req;
wire bkptb_ctrl_data_req_raw;
wire bkptb_ctrl_inst_req;
wire bkptb_ctrl_inst_req_raw;
wire bkptb_ctrl_xx_ack;
wire bkptb_en;
wire bkptb_sqc_en;
wire cpuclk;
wire cpurst_b;
wire ctrl_bkpta_en;
wire ctrl_bkpta_en_raw;
wire ctrl_bkptb_en_raw;
wire ctrl_dbgfifo_ren;
wire ctrl_event_dbgenter;
wire ctrl_event_dbgexit;
wire ctrl_pcfifo_ren;
wire ctrl_pcfifo_wen;
wire ctrl_pipefifo_ren;
wire ctrl_pipefifo_wen;
wire ctrl_regs_bkpta_vld;
wire ctrl_regs_bkptb_vld;
wire ctrl_regs_exit_dbg;
wire ctrl_regs_freeze_pcfifo;
wire ctrl_regs_set_sqa;
wire ctrl_regs_set_sqb;
wire ctrl_regs_update_adro;
wire ctrl_regs_update_dro;
wire ctrl_regs_update_mbo;
wire ctrl_regs_update_pro;
wire ctrl_regs_update_swo;
wire ctrl_regs_update_to;
wire ctrl_tee_dbg_disable;
wire ctrl_xx_dbg_disable;
wire data_bkpt_dbgreq;
wire ddc_inst_go;
wire ddc_xx_update_ir;
wire event_ctrl_enter_dbg;
wire event_ctrl_exit_dbg;
wire event_ctrl_had_clk_en;
wire exit_dbg;
wire exit_dbg_active;
wire forever_coreclk;
wire go_in_dbg;
wire go_noex;
wire had_clk_en;
wire had_cp0_xx_dbg;
wire had_ifu_ir_vld;
wire had_ifu_pcload;
wire had_rtu_data_bkpt_dbgreq;
wire had_rtu_dbg_disable;
wire had_rtu_dbg_req_en;
wire had_rtu_event_dbgreq;
wire had_rtu_fdb;
wire had_rtu_hw_dbgreq;
wire had_rtu_hw_dbgreq_gateclk;
wire had_rtu_inst_bkpt_dbgreq;
wire had_rtu_non_irv_bkpt_dbgreq;
wire had_rtu_pop1_disa;
wire had_rtu_trace_dbgreq;
wire had_rtu_trace_en;
wire had_rtu_xx_jdbreq;
wire had_rtu_xx_tme;
wire had_xx_clk_en;
wire had_yy_xx_exit_dbg;
wire inst_bkpt_dbgreq;
wire ir_ctrl_exit_dbg_reg;
wire ir_ctrl_had_clk_en;
wire ir_xx_ir_reg_sel;
wire mem_bkpta_data_req;
wire mem_bkpta_data_req_raw;
wire mem_bkpta_inst_req;
wire mem_bkpta_inst_req_raw;
wire mem_bkptb_data_req;
wire mem_bkptb_data_req_raw;
wire mem_bkptb_inst_req;
wire mem_bkptb_inst_req_raw;
wire nirv_bkpta;
wire non_irv_bkpt_vld;
wire regs_ctrl_adr;
wire regs_ctrl_dr;
wire regs_ctrl_fdb;
wire regs_ctrl_frzc;
wire regs_ctrl_pcfifo_frozen;
wire [1:0] regs_ctrl_pm;
wire regs_ctrl_sqa;
wire regs_ctrl_sqb;
wire [1:0] regs_ctrl_sqc;
wire regs_ctrl_tme;
wire [4:0] regs_xx_bca;
wire [4:0] regs_xx_bcb;
wire regs_xx_ddc_en;
wire regs_xx_nirven;
wire rtu_had_dbgreq_ack;
wire rtu_had_inst0_bkpt_inst;
wire rtu_yy_xx_dbgon;
wire rtu_yy_xx_retire0;
wire rtu_yy_xx_retire0_normal;
wire sdb_req;
wire trace_ctrl_req;
wire trace_req;
wire trace_sqc_en;
wire x_had_dbg_mask;
wire x_ir_ctrl_dbgfifo_read_pulse;
wire x_ir_ctrl_pcfifo_read_pulse;
wire x_ir_ctrl_pipefifo_read_pulse;
wire x_ir_xx_ex;
wire x_ir_xx_go;
wire x_sm_xx_update_dr_en;
// had control logic can be divided into four parts:
// 1. ctrl signal to had function modules
// 2. debug request to RTU
// 3. inform HSR to update corresponding status bits
// 4. exit debug mode logic
//==============================================================================
// 1. ctrl signal to had function modules
//==============================================================================
//==========================================================
// memory bkpta enable
//==========================================================
// &Force("output", "ctrl_bkpta_en"); @44
assign ctrl_bkpta_en = |regs_xx_bca[4:0];
assign ctrl_bkpta_en_raw = |regs_xx_bca[4:0];
//==========================================================
// memory bkptb enable
//==========================================================
// memory bkptb enable contains two conditions:
// 1. bcb not zero
// 2. meet SQC conditons
// i) sqc[1:0] = 2'b00: no affect
// ii) sqc[1] = 1'b1: bkptb won't be enabled until bkpta occurs
assign bkptb_en = |regs_xx_bcb[4:0];
assign bkptb_sqc_en = !regs_ctrl_sqc[1] ||
regs_ctrl_sqc[1] && rtu_yy_xx_retire0_normal &&
!inst_bkpt_dbgreq && (bkpta_ctrl_inst_req || bkpta_ctrl_data_req) ||
regs_ctrl_sqa;
// &Force("output", "ctrl_bkptb_en"); @65
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
ctrl_bkptb_en <= 1'b0;
else if (bkptb_en && bkptb_sqc_en)
ctrl_bkptb_en <= 1'b1;
else
ctrl_bkptb_en <= 1'b0;
end
assign ctrl_bkptb_en_raw = bkptb_en && bkptb_sqc_en;
//==========================================================
// trace enable
//==========================================================
// trace enable contains two conditions:
// 1. tme set
// 2. meet SQC conditions
// i) sqc[1:0] = 2'b00: no affect
// ii) sqc[0] = 1'b1: trace won't be enabled until bkptb occurs
assign trace_sqc_en = !regs_ctrl_sqc[0] ||
regs_ctrl_sqc[0] && rtu_yy_xx_retire0_normal &&
!inst_bkpt_dbgreq && (bkptb_ctrl_inst_req || bkptb_ctrl_data_req) ||
regs_ctrl_sqb;
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
ctrl_trace_en <= 1'b0;
else if (regs_ctrl_tme && trace_sqc_en)
ctrl_trace_en <= 1'b1;
else
ctrl_trace_en <= 1'b0;
end
// &Force("output","ctrl_trace_en"); @103
assign had_rtu_trace_en = ctrl_trace_en;
//==========================================================
// pcfifo enable
//==========================================================
// pcfifo write enable contains three conditions:
// 1. pcfifo not frozen
// 2. change flow inst retire normally
// 3. not in debug mode
// 4. meet the condition about
assign ctrl_pcfifo_wen = !regs_ctrl_pcfifo_frozen &&
!inst_bkpt_dbgreq &&
!rtu_yy_xx_dbgon;
// && cp0_had_pcfifo_wen;
// pcfifo read enable contains two conditions:
// 1. pcfifo not frozen
// 2. pcfifo read pulse
assign ctrl_pcfifo_ren = !regs_ctrl_pcfifo_frozen && x_ir_ctrl_pcfifo_read_pulse;
//==========================================================
// pipefifo enable
//==========================================================
assign ctrl_pipefifo_wen = !rtu_yy_xx_dbgon;
assign ctrl_pipefifo_ren = x_ir_ctrl_pipefifo_read_pulse;
assign ctrl_dbgfifo_ren = x_ir_ctrl_dbgfifo_read_pulse;
//==============================================================================
// 2. debug request to RTU
//==============================================================================
//==========================================================
// Three major kinds of debug requests are sent to RTU from HAD
// 1. had_rtu_xx_jdbreq: asynchronous debug request
// 2. had_rtu_hw_dbgreq: synchronous debug request, include DR set, sdb_req_b
// 3. had_rtu_mt_dbgreq: synchronous debug request, include memory bkpt and trace
//==========================================================
assign trace_req = trace_ctrl_req;
assign mem_bkpta_inst_req = bkpta_ctrl_inst_req && !regs_ctrl_sqc[1];
assign mem_bkpta_data_req = bkpta_ctrl_data_req && !regs_ctrl_sqc[1];
assign mem_bkptb_inst_req = bkptb_ctrl_inst_req && !regs_ctrl_sqc[0] && !regs_ctrl_frzc;
assign mem_bkptb_data_req = bkptb_ctrl_data_req && !regs_ctrl_sqc[0] && !regs_ctrl_frzc;
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
dr_set_req <= 1'b0;
else
dr_set_req <= regs_ctrl_dr;
end
assign adr_set_req = regs_ctrl_adr;
assign sdb_req = !biu_had_sdb_req_b;
// &Force("output", "had_rtu_hw_dbgreq"); @164
assign had_rtu_hw_dbgreq = (dr_set_req || sdb_req) && !rtu_yy_xx_dbgon;
assign had_rtu_hw_dbgreq_gateclk = dr_set_req || sdb_req;
// &Force("output", "had_rtu_trace_dbgreq"); @168
// &Force("output", "inst_bkpt_dbgreq"); @169
assign inst_bkpt_dbgreq = (mem_bkpta_inst_req || mem_bkptb_inst_req) && regs_ctrl_fdb &&!rtu_yy_xx_dbgon;
assign data_bkpt_dbgreq = (mem_bkpta_data_req || mem_bkptb_data_req) && regs_ctrl_fdb &&!rtu_yy_xx_dbgon;
assign had_rtu_trace_dbgreq = trace_req && !rtu_yy_xx_dbgon;
// &Force("output", "had_rtu_xx_jdbreq"); @175
assign had_rtu_xx_jdbreq = async_dbg_req;
// &Force("output", "had_rtu_event_dbgreq"); @178
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
event_req <= 1'b0;
else
event_req <= event_ctrl_enter_dbg;
end
assign had_rtu_event_dbgreq = event_req && !rtu_yy_xx_dbgon;
assign mem_bkpta_inst_req_raw = bkpta_ctrl_inst_req_raw && !regs_ctrl_sqc[1];
assign mem_bkpta_data_req_raw = bkpta_ctrl_data_req_raw && !regs_ctrl_sqc[1];
assign mem_bkptb_inst_req_raw = bkptb_ctrl_inst_req_raw && !regs_ctrl_sqc[0] && !regs_ctrl_frzc;
assign mem_bkptb_data_req_raw = bkptb_ctrl_data_req_raw && !regs_ctrl_sqc[0] && !regs_ctrl_frzc;
assign had_rtu_inst_bkpt_dbgreq = (mem_bkpta_inst_req_raw || mem_bkptb_inst_req_raw) && regs_ctrl_fdb &&!rtu_yy_xx_dbgon;
assign had_rtu_data_bkpt_dbgreq = (mem_bkpta_data_req_raw || mem_bkptb_data_req_raw) && regs_ctrl_fdb &&!rtu_yy_xx_dbgon;
assign had_rtu_non_irv_bkpt_dbgreq = non_irv_bkpt_vld && !rtu_yy_xx_dbgon;
//==========================================================
// wake up CPU from low power mode
//==========================================================
assign had_cp0_xx_dbg = (had_rtu_hw_dbgreq ||
inst_bkpt_dbgreq ||
data_bkpt_dbgreq ||
had_rtu_trace_dbgreq ||
had_rtu_xx_jdbreq ||
had_rtu_event_dbgreq ||
non_irv_bkpt_vld) && !ctrl_xx_dbg_disable;
//==========================================================
// control signal for RTU enter debug
//==========================================================
assign had_rtu_fdb = regs_ctrl_fdb;
// when trace or memory bkpt is enabled, RTU retires inst one by one
assign had_rtu_pop1_disa = regs_ctrl_tme ||
!regs_xx_nirven && (ctrl_bkpta_en || bkptb_en);
//when there may be new debug request, signal RTU to enable single retire
//mode and mask debug request if committed inst may be flushed
assign had_rtu_dbg_req_en = regs_ctrl_dr ||
regs_ctrl_adr ||
event_ctrl_enter_dbg ||
non_irv_bkpt_vld;
assign had_rtu_xx_tme = regs_ctrl_tme;
assign ctrl_event_dbgenter = rtu_had_dbgreq_ack ;
//==============================================================================
// 3. inform HSR to update corresponding status bits
//==============================================================================
// debug request has the highest proirity, all debug request will be acked.
// update adro
assign ctrl_regs_update_adro = async_dbg_req;
assign async_dbg_req = adr_set_req && !rtu_yy_xx_dbgon;
// update dro
assign ctrl_regs_update_dro = dr_set_req && !rtu_yy_xx_dbgon;
// update mbo
assign ctrl_regs_update_mbo = ((bkpta_ctrl_xx_ack ||
bkptb_ctrl_xx_ack) && regs_ctrl_fdb
|| non_irv_bkpt_vld)
&& !rtu_yy_xx_dbgon;
assign ctrl_regs_bkpta_vld = (bkpta_ctrl_xx_ack && regs_ctrl_fdb
|| non_irv_bkpt_vld && nirv_bkpta)
&& !rtu_yy_xx_dbgon;
assign ctrl_regs_bkptb_vld = (bkptb_ctrl_xx_ack && regs_ctrl_fdb
|| non_irv_bkpt_vld && !nirv_bkpta)
&& !rtu_yy_xx_dbgon;
// update swo
// if bkpt ins triggles mbkpt&soft bkpt, the mbkpt is higher than soft bkpt
// &Force("output","ctrl_regs_update_mbo"); @262
assign ctrl_regs_update_swo =rtu_had_inst0_bkpt_inst && rtu_yy_xx_retire0 &&
regs_ctrl_fdb &&
!ctrl_regs_update_mbo &&
!rtu_yy_xx_dbgon;
// update to
// if mbkpt&trace occurs at the same time, the mbkpt is higher than soft bkpt
assign ctrl_regs_update_to = trace_req && !rtu_yy_xx_dbgon && !ctrl_regs_update_mbo;
// update frzo
assign ctrl_regs_freeze_pcfifo = (bkptb_ctrl_inst_req || bkptb_ctrl_data_req) && rtu_yy_xx_retire0_normal
&& !inst_bkpt_dbgreq && regs_ctrl_frzc;
// update sqb
assign ctrl_regs_set_sqb = (bkptb_ctrl_inst_req || bkptb_ctrl_data_req) && rtu_yy_xx_retire0_normal
&& !inst_bkpt_dbgreq && regs_ctrl_sqc[0];
// update sqa
assign ctrl_regs_set_sqa =(bkpta_ctrl_inst_req || bkpta_ctrl_data_req) && rtu_yy_xx_retire0_normal
&& !inst_bkpt_dbgreq && regs_ctrl_sqc[1];
//update pro
assign ctrl_regs_update_pro = event_req && !rtu_yy_xx_dbgon;
//==============================================================================
// exit debug mode logic
//==============================================================================
//==========================================================
// exit debug mode
//==========================================================
// CPU exit debug mode when TAP is in UPDATE_DR state and bypass or cpuscr reg
// is selected
assign exit_dbg_active = x_ir_xx_ex && x_ir_xx_go
&& x_sm_xx_update_dr_en && ir_ctrl_exit_dbg_reg
&& rtu_yy_xx_dbgon;
assign exit_dbg = exit_dbg_active || event_ctrl_exit_dbg && rtu_yy_xx_dbgon;
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
ctrl_exit_dbg <= 1'b0;
else
ctrl_exit_dbg <= exit_dbg;
end
assign ctrl_regs_exit_dbg = ctrl_exit_dbg;
assign had_yy_xx_exit_dbg = ctrl_exit_dbg;
assign had_ifu_pcload = ctrl_exit_dbg;
assign ctrl_event_dbgexit = exit_dbg_active;
//==========================================================
// go in debug mode
//==========================================================
// CPU go in debug mode contains two cases:
// 1. normal debug channel
// 2. ddc channel
assign go_noex = !x_ir_xx_ex && x_ir_xx_go
&& x_sm_xx_update_dr_en && ir_xx_ir_reg_sel // this is a pulse signal
&& rtu_yy_xx_dbgon;
assign ddc_inst_go = regs_xx_ddc_en
&& ddc_xx_update_ir // this is a pulse signal
&& rtu_yy_xx_dbgon;
assign go_in_dbg = go_noex || ddc_inst_go;
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
ctrl_go_noex <= 1'b0;
else
ctrl_go_noex <= go_in_dbg;
end
assign had_ifu_ir_vld = ctrl_go_noex;
//==========================================================
// TEE Signals
//==========================================================
// &Force("input", "had_xx_tee_dbg_disable"); &Force("bus", "had_xx_tee_dbg_disable", 7, 0); @360
// &Force("input", "forever_coreclk"); @361
// &Force("nonport", "had_xx_tee_dbg_disable_sync"); @362
// &Force("input", "had_xx_ree_dbg_disable"); &Force("bus", "had_xx_ree_dbg_disable", 7, 0); @373
// &Force("input", "forever_coreclk"); @374
// &Force("nonport", "had_xx_ree_dbg_disable_sync"); @375
assign ctrl_tee_dbg_disable = 1'b0;
//==========================================================
// Debug Disable
//==========================================================
// &Force("input", "x_had_dbg_mask"); @402
// &Force("input", "forever_coreclk"); @403
// &Force("nonport", "ctrl_out_dbg_disable"); @404
always @ (posedge forever_coreclk or negedge cpurst_b)
begin
if (~cpurst_b)
ctrl_out_dbg_disable <= 1'b0;
else
ctrl_out_dbg_disable <= x_had_dbg_mask;
end
assign ctrl_xx_dbg_disable = ctrl_tee_dbg_disable || ctrl_out_dbg_disable;
// &Force("output", "ctrl_xx_dbg_disable"); @417
assign had_rtu_dbg_disable = ctrl_xx_dbg_disable;
//==========================================================
// Top ICG
//==========================================================
assign had_clk_en = ir_ctrl_had_clk_en | event_ctrl_had_clk_en;
always@(posedge forever_coreclk or negedge cpurst_b)
begin
if (!cpurst_b)
had_clk_en_ff <= 1'b0;
else if (had_clk_en)
had_clk_en_ff <= 1'b1;
else if (regs_ctrl_pm[1:0] == 2'b11)
had_clk_en_ff <= 1'b0;
end
assign had_xx_clk_en = had_clk_en | had_clk_en_ff;
// &ModuleEnd; @439
endmodule |
module ct_had_ddc_ctrl(
cpuclk,
cpurst_b,
ddc_ctrl_dp_addr_gen,
ddc_ctrl_dp_addr_sel,
ddc_ctrl_dp_data_sel,
ddc_regs_update_csr,
ddc_regs_update_wbbr,
ddc_xx_update_ir,
ir_xx_daddr_reg_sel,
ir_xx_ddata_reg_sel,
regs_xx_ddc_en,
rtu_yy_xx_retire0_normal,
x_sm_xx_update_dr_en
);
// &Ports; @24
input cpuclk;
input cpurst_b;
input ir_xx_daddr_reg_sel;
input ir_xx_ddata_reg_sel;
input regs_xx_ddc_en;
input rtu_yy_xx_retire0_normal;
input x_sm_xx_update_dr_en;
output ddc_ctrl_dp_addr_gen;
output ddc_ctrl_dp_addr_sel;
output ddc_ctrl_dp_data_sel;
output ddc_regs_update_csr;
output ddc_regs_update_wbbr;
output ddc_xx_update_ir;
// &Regs; @25
reg addr_ld_finish;
reg [3:0] cur_st;
reg [3:0] nxt_st;
// &Wires; @26
wire addr_ready;
wire cpuclk;
wire cpurst_b;
wire data_ld_finish;
wire data_ready;
wire ddc_ctrl_dp_addr_gen;
wire ddc_ctrl_dp_addr_sel;
wire ddc_ctrl_dp_data_sel;
wire ddc_ctrl_dp_stw_sel;
wire ddc_regs_update_csr;
wire ddc_regs_update_wbbr;
wire ddc_xx_update_ir;
wire ir_xx_daddr_reg_sel;
wire ir_xx_ddata_reg_sel;
wire regs_xx_ddc_en;
wire rtu_yy_xx_retire0_normal;
wire stw_inst_retire;
wire x_sm_xx_update_dr_en;
//==============================================================================
// DDC control state machine
//==============================================================================
parameter IDLE = 4'h0;
parameter ADDR_WATI = 4'h1;
parameter ADDR_LD = 4'h2;
parameter DATA_WAIT = 4'h3;
parameter DATA_LD = 4'h4;
parameter STW_WAIT = 4'h5;
parameter STW_LD = 4'h6;
parameter STW_FINISH = 4'h7;
parameter ADDR_GEN = 4'h8;
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
cur_st[3:0] <= IDLE;
else
cur_st[3:0] <= nxt_st[3:0];
end
// &CombBeg; @50
always @( addr_ld_finish
or cur_st[3:0]
or addr_ready
or regs_xx_ddc_en
or data_ready
or stw_inst_retire
or data_ld_finish)
begin
case(cur_st[3:0])
IDLE:
if (regs_xx_ddc_en)
nxt_st[3:0] = ADDR_WATI;
else
nxt_st[3:0] = IDLE;
ADDR_WATI: // wait addr be loaded into daddr
if (addr_ready)
nxt_st[3:0] = ADDR_LD;
else
nxt_st[3:0] = ADDR_WATI;
ADDR_LD: // load "mov r0, r0" to ir, ffy and wbbr
nxt_st[3:0] = DATA_WAIT;
DATA_WAIT:
if (addr_ld_finish && data_ready) // wait base prepare finish and data ready.
nxt_st[3:0] = DATA_LD;
else if (addr_ready) // re-prepare base
nxt_st[3:0] = ADDR_LD;
else if (!regs_xx_ddc_en)
nxt_st[3:0] = IDLE;
else
nxt_st[3:0] = DATA_WAIT;
DATA_LD:
nxt_st[3:0] = STW_WAIT; // load "mov r1, r1" to ir, ffy and wbbr
STW_WAIT:
if (data_ld_finish) // wait for "mov r1, r1" retire: data prepare finish
nxt_st[3:0] = STW_LD;
else
nxt_st[3:0] = STW_WAIT;
STW_LD: // load "stw r1, r0" to ir
nxt_st[3:0] = STW_FINISH;
STW_FINISH: // wait for stw finish
if (stw_inst_retire)
nxt_st[3:0] = ADDR_GEN;
else
nxt_st[3:0] = STW_FINISH;
ADDR_GEN: // increase addr and recycle
nxt_st[3:0] = ADDR_LD;
default:
nxt_st[3:0] = IDLE;
endcase
// &CombEnd; @92
end
assign addr_ready = x_sm_xx_update_dr_en && ir_xx_daddr_reg_sel;
assign data_ready = x_sm_xx_update_dr_en && ir_xx_ddata_reg_sel;
// addr load finish
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
addr_ld_finish <= 1'b0;
else if (cur_st[3:0] == DATA_WAIT) begin
if (rtu_yy_xx_retire0_normal)
addr_ld_finish <= 1'b1;
else
addr_ld_finish <= addr_ld_finish; // hold finish state
end
else
addr_ld_finish <= 1'b0;
end
// data load finish will push state machine into next state, so the state
// needn't hold
assign data_ld_finish = rtu_yy_xx_retire0_normal;
assign stw_inst_retire = rtu_yy_xx_retire0_normal;
//==========================================================
// control signal to ddc dp
//==========================================================
// &Force("output", "ddc_ctrl_dp_addr_sel"); @122
assign ddc_ctrl_dp_addr_sel = cur_st[3:0] == ADDR_LD;
// &Force("output", "ddc_ctrl_dp_data_sel"); @125
assign ddc_ctrl_dp_data_sel = cur_st[3:0] == DATA_LD;
assign ddc_ctrl_dp_stw_sel = cur_st[3:0] == STW_LD;
assign ddc_ctrl_dp_addr_gen = cur_st[3:0] == ADDR_GEN;
//==========================================================
// control signal to regs
//==========================================================
assign ddc_regs_update_wbbr = ddc_ctrl_dp_addr_sel || ddc_ctrl_dp_data_sel;
assign ddc_regs_update_csr = ddc_ctrl_dp_addr_sel ||
ddc_ctrl_dp_data_sel ||
ddc_ctrl_dp_stw_sel;
assign ddc_xx_update_ir = ddc_ctrl_dp_addr_sel ||
ddc_ctrl_dp_data_sel ||
ddc_ctrl_dp_stw_sel;
// &ModuleEnd; @146
endmodule |
module ct_had_sm(
cpurst_b,
dbgfifo2_read_ren,
forever_cpuclk,
io_sm_tap_en,
ir_sm_hacr_rw,
ir_xx_dbgfifo2_reg_sel,
pad_had_jtg_tms,
pad_yy_icg_scan_en,
sm_io_tdo_en,
sm_ir_update_hacr,
sm_serial_capture_dr,
sm_serial_shift_dr,
sm_serial_shift_ir,
sm_update_dr,
sm_update_ir,
sm_xx_write_en,
tclk,
trst_b
);
// &Ports; @23
input cpurst_b;
input forever_cpuclk;
input io_sm_tap_en;
input ir_sm_hacr_rw;
input ir_xx_dbgfifo2_reg_sel;
input pad_had_jtg_tms;
input pad_yy_icg_scan_en;
input tclk;
input trst_b;
output dbgfifo2_read_ren;
output sm_io_tdo_en;
output sm_ir_update_hacr;
output sm_serial_capture_dr;
output sm_serial_shift_dr;
output sm_serial_shift_ir;
output sm_update_dr;
output sm_update_ir;
output sm_xx_write_en;
// &Regs; @24
reg [5:0] tap5_cur_st;
reg [5:0] tap5_nxt_st;
reg tdo_en;
reg update_ir_cpu_ff1;
// &Wires; @25
wire cpurst_b;
wire dbgfifo2_read;
wire dbgfifo2_read_ren;
wire forever_cpuclk;
wire io_sm_tap_en;
wire ir_sm_hacr_rw;
wire ir_xx_dbgfifo2_reg_sel;
wire pad_had_jtg_tms;
wire pad_yy_icg_scan_en;
wire sm5_capture_dr;
wire sm5_shift_dr;
wire sm5_shift_ir;
wire sm5_update_dr;
wire sm5_update_ir;
wire sm_clk;
wire sm_clk_en;
wire sm_io_tdo_en;
wire sm_ir_update_hacr;
wire sm_ir_update_hacr_ff1;
wire sm_serial_capture_dr;
wire sm_serial_shift_dr;
wire sm_serial_shift_ir;
wire sm_update_dr;
wire sm_update_ir;
wire sm_update_ir_cpu;
wire sm_xx_write_en;
wire tclk;
wire tms_i;
wire trst_b;
assign tms_i = pad_had_jtg_tms;
//==============================================================================
// TAP5 controller state machine
//==============================================================================
parameter TAP5_RESET = 6'b000000;
parameter TAP5_IDLE = 6'b000001;
parameter TAP5_SELECT_DR_SCAN = 6'b000011;
parameter TAP5_SELECT_IR_SCAN = 6'b000010;
parameter TAP5_CAPTURE_IR = 6'b000110;
parameter TAP5_SHIFT_IR = 6'b000100;
parameter TAP5_EXIT1_IR = 6'b000101;
// parameter TAP5_UPDATE_IR = 4'b0111;
parameter TAP5_UPDATE_IR = 6'b010000; // UPDATE_IR change to 1 bit reg to sync.
parameter TAP5_CAPTURE_DR = 6'b001011;
parameter TAP5_SHIFT_DR = 6'b001010;
parameter TAP5_EXIT1_DR = 6'b001000;
// parameter TAP5_UPDATE_DR = 4'b1001;
parameter TAP5_UPDATE_DR = 6'b100000; // UPDATE_DR change to 1 bit reg to sync.
parameter TAP5_PAUSE_IR = 6'b001101;
parameter TAP5_EXIT2_IR = 6'b001111;
parameter TAP5_PAUSE_DR = 6'b001100;
parameter TAP5_EXIT2_DR = 6'b001110;
always @(posedge tclk or negedge trst_b)
begin
if (!trst_b)
tap5_cur_st[5:0] <= TAP5_RESET;
else begin
tap5_cur_st[5:0] <= tap5_nxt_st[5:0];
end
end
// &CombBeg; @60
always @( io_sm_tap_en
or tap5_cur_st[5:0]
or tms_i)
begin
case(tap5_cur_st[5:0])
TAP5_RESET:
if (io_sm_tap_en && !tms_i)
tap5_nxt_st[5:0] = TAP5_IDLE;
else
tap5_nxt_st[5:0] = TAP5_RESET;
TAP5_IDLE:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_SELECT_DR_SCAN;
else
tap5_nxt_st[5:0] = TAP5_IDLE;
TAP5_SELECT_DR_SCAN:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_SELECT_IR_SCAN;
else
tap5_nxt_st[5:0] = TAP5_CAPTURE_DR;
TAP5_SELECT_IR_SCAN:
if (!tms_i)
tap5_nxt_st[5:0] = TAP5_CAPTURE_IR;
else
tap5_nxt_st[5:0] = TAP5_RESET;
TAP5_CAPTURE_IR:
if (!tms_i)
tap5_nxt_st[5:0] = TAP5_SHIFT_IR;
else
tap5_nxt_st[5:0] = TAP5_EXIT1_IR;
TAP5_SHIFT_IR:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_EXIT1_IR;
else
tap5_nxt_st[5:0] = TAP5_SHIFT_IR;
TAP5_EXIT1_IR:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_UPDATE_IR;
else
tap5_nxt_st[5:0] = TAP5_PAUSE_IR;
TAP5_PAUSE_IR:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_EXIT2_IR;
else
tap5_nxt_st[5:0] = TAP5_PAUSE_IR;
TAP5_EXIT2_IR:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_UPDATE_IR;
else
tap5_nxt_st[5:0] = TAP5_SHIFT_IR;
TAP5_UPDATE_IR:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_SELECT_DR_SCAN;
else
tap5_nxt_st[5:0] = TAP5_IDLE;
TAP5_CAPTURE_DR:
if (!tms_i)
tap5_nxt_st[5:0] = TAP5_SHIFT_DR;
else
tap5_nxt_st[5:0] = TAP5_EXIT1_DR;
TAP5_SHIFT_DR:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_EXIT1_DR;
else
tap5_nxt_st[5:0] = TAP5_SHIFT_DR;
TAP5_EXIT1_DR:
if (!tms_i)
tap5_nxt_st[5:0] = TAP5_PAUSE_DR;
else
tap5_nxt_st[5:0] = TAP5_UPDATE_DR;
TAP5_PAUSE_DR:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_EXIT2_DR;
else
tap5_nxt_st[5:0] = TAP5_PAUSE_DR;
TAP5_EXIT2_DR:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_UPDATE_DR;
else
tap5_nxt_st[5:0] = TAP5_SHIFT_DR;
TAP5_UPDATE_DR:
if (tms_i)
tap5_nxt_st[5:0] = TAP5_SELECT_DR_SCAN;
else
tap5_nxt_st[5:0] = TAP5_IDLE;
default:
tap5_nxt_st[5:0] = TAP5_RESET;
endcase
// &CombEnd; @145
end
//=============================================
// TAP5 status
//=============================================
assign sm5_shift_ir = (tap5_cur_st[5:0] == TAP5_SHIFT_IR);
assign sm5_update_ir = tap5_cur_st[4];
assign sm5_shift_dr = (tap5_cur_st[5:0] == TAP5_SHIFT_DR);
assign sm5_update_dr = tap5_cur_st[5];
assign sm5_capture_dr = (tap5_cur_st[5:0] == TAP5_CAPTURE_DR);
//=============================================
// TDO output enable in JTAG_5 interafce
//=============================================
always @(negedge tclk or negedge trst_b)
begin
if (!trst_b)
tdo_en <= 1'b0;
else if (sm5_shift_dr && ir_sm_hacr_rw)
tdo_en <= 1'b1;
else
tdo_en <= 1'b0;
end
assign sm_io_tdo_en = tdo_en;
//==========================================================
// Interface to serial module
//==========================================================
// shift_ir, shift_dr and capture_dr are used in serial in and out and is in
// tclk domain, thus no synchronization is needed.
assign sm_serial_shift_ir = sm5_shift_ir;
assign sm_serial_shift_dr = sm5_shift_dr;
assign sm_serial_capture_dr = sm5_capture_dr;
//==========================================================
// tclk domain to cpuclk domain
// update_ir, update_dr are used in registers updating and is in cpuclk domain,
// thus synchronization is needed.
//==========================================================
assign sm_update_ir = sm5_update_ir;
assign sm_update_dr = sm5_update_dr;
// &Instance("ct_had_sync_3flop", "x_ct_had_sync_ir"); @189
ct_had_sync_3flop x_ct_had_sync_ir (
.clk1 (forever_cpuclk ),
.clk2 (tclk ),
.rst1_b (cpurst_b ),
.rst2_b (trst_b ),
.sync_in (sm_update_ir ),
.sync_out (sm_update_ir_cpu)
);
// &Connect(.clk1 (forever_cpuclk), @190
// .clk2 (tclk), @191
// .rst1_b (cpurst_b), @192
// .rst2_b (trst_b), @193
// .sync_in (sm_update_ir), @194
// .sync_out (sm_update_ir_cpu) @195
// ); @196
// &Instance("ct_had_sync", "x_ct_had_sync_dr");
// // &Connect(.clk1 (forever_cpuclk), @199
// // .clk2 (tclk), @200
// // .rst1_b (cpurst_b), @201
// // .rst2_b (trst_b), @202
// // .sync_in (sm_update_dr), @203
// // .sync_out (sm_update_dr_cpu) @204
// // ); @205
// &Force("output", "sm_update_ir"); @207
// &Force("output", "sm_update_dr"); @208
//==========================================================
// update ir
//==========================================================
assign sm_ir_update_hacr = sm_update_ir_cpu;
assign sm_ir_update_hacr_ff1 = update_ir_cpu_ff1;
always @(posedge sm_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
update_ir_cpu_ff1 <= 1'b0;
end
else begin
update_ir_cpu_ff1 <= sm_update_ir_cpu;
end
end
//==========================================================
// update dr
//==========================================================
// &Force ("output", "sm_xx_write_en"); @229
//================================
// we ignor JTAG interface type, and only use HACR[7] bit to indicate
// "read" or "write" operation.
// If we use sm2_read_vld in JTAG2 interface, this will couse PCFIFO
// cannot be read out!
//================================
assign sm_xx_write_en = !ir_sm_hacr_rw;
//assign update_dr_cpu = sm_update_dr_cpu;
assign sm_clk_en = sm_update_ir_cpu ^ update_ir_cpu_ff1;
// &Instance("gated_clk_cell", "x_had_sm_gated_clk"); @242
gated_clk_cell x_had_sm_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (sm_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (sm_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @243
// .external_en (1'b0), @244
// .global_en (1'b1), @245
// .module_en (1'b0), @246
// .local_en (sm_clk_en), @247
// .clk_out (sm_clk)); @248
assign dbgfifo2_read = ir_sm_hacr_rw && ir_xx_dbgfifo2_reg_sel;
assign dbgfifo2_read_ren = dbgfifo2_read && sm_ir_update_hacr_ff1;
// &ModuleEnd; @253
endmodule |
module ct_had_ir(
common_regs_data,
core0_regs_serial_data,
core1_regs_serial_data,
cpurst_b,
forever_cpuclk,
ir_corex_wdata,
ir_sm_hacr_rw,
ir_xx_baba_reg_sel,
ir_xx_babb_reg_sel,
ir_xx_bama_reg_sel,
ir_xx_bamb_reg_sel,
ir_xx_core0_sel,
ir_xx_core1_sel,
ir_xx_core2_sel,
ir_xx_core3_sel,
ir_xx_csr_reg_sel,
ir_xx_daddr_reg_sel,
ir_xx_dbgfifo2_reg_sel,
ir_xx_dbgfifo_reg_sel,
ir_xx_ddata_reg_sel,
ir_xx_dms_reg_sel,
ir_xx_id_reg_sel,
ir_xx_mbca_reg_sel,
ir_xx_mbcb_reg_sel,
ir_xx_otc_reg_sel,
ir_xx_pc_reg_sel,
ir_xx_pcfifo_reg_sel,
ir_xx_pipefifo_reg_sel,
ir_xx_rsr_reg_sel,
ir_xx_wbbr_reg_sel,
pad_yy_icg_scan_en,
regs_serial_data,
serial_xx_data,
sm_ir_update_hacr,
sysio_had_dbg_mask
);
// &Ports; @24
input [63:0] common_regs_data;
input [63:0] core0_regs_serial_data;
input [63:0] core1_regs_serial_data;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [63:0] serial_xx_data;
input sm_ir_update_hacr;
input [3 :0] sysio_had_dbg_mask;
output [63:0] ir_corex_wdata;
output ir_sm_hacr_rw;
output ir_xx_baba_reg_sel;
output ir_xx_babb_reg_sel;
output ir_xx_bama_reg_sel;
output ir_xx_bamb_reg_sel;
output ir_xx_core0_sel;
output ir_xx_core1_sel;
output ir_xx_core2_sel;
output ir_xx_core3_sel;
output ir_xx_csr_reg_sel;
output ir_xx_daddr_reg_sel;
output ir_xx_dbgfifo2_reg_sel;
output ir_xx_dbgfifo_reg_sel;
output ir_xx_ddata_reg_sel;
output ir_xx_dms_reg_sel;
output ir_xx_id_reg_sel;
output ir_xx_mbca_reg_sel;
output ir_xx_mbcb_reg_sel;
output ir_xx_otc_reg_sel;
output ir_xx_pc_reg_sel;
output ir_xx_pcfifo_reg_sel;
output ir_xx_pipefifo_reg_sel;
output ir_xx_rsr_reg_sel;
output ir_xx_wbbr_reg_sel;
output [63:0] regs_serial_data;
// &Regs; @25
reg [15:0] hacr_reg;
// &Wires; @26
wire bank0_sel;
wire bank2_sel;
wire bank3_sel;
wire [63:0] common_regs_data;
wire core0_dbg_disable;
wire [63:0] core0_regs_serial_data;
wire core1_dbg_disable;
wire [63:0] core1_regs_serial_data;
wire core2_dbg_disable;
wire core3_dbg_disable;
wire cpurst_b;
wire forever_cpuclk;
wire [4 :0] hacr_index;
wire ir_clk;
wire ir_common_sel;
wire ir_core0_priv_sel;
wire ir_core0_sel;
wire ir_core1_priv_sel;
wire ir_core1_sel;
wire ir_core2_priv_sel;
wire ir_core2_sel;
wire ir_core3_priv_sel;
wire ir_core3_sel;
wire [63:0] ir_corex_wdata;
wire ir_sm_hacr_rw;
wire ir_xx_baba_reg_sel;
wire ir_xx_babb_reg_sel;
wire ir_xx_bama_reg_sel;
wire ir_xx_bamb_reg_sel;
wire ir_xx_core0_sel;
wire ir_xx_core1_sel;
wire ir_xx_core2_sel;
wire ir_xx_core3_sel;
wire ir_xx_csr_reg_sel;
wire ir_xx_daddr_reg_sel;
wire ir_xx_dbgfifo2_reg_sel;
wire ir_xx_dbgfifo_reg_sel;
wire ir_xx_ddata_reg_sel;
wire ir_xx_dms_reg_sel;
wire ir_xx_id_reg_sel;
wire ir_xx_mbca_reg_sel;
wire ir_xx_mbcb_reg_sel;
wire ir_xx_otc_reg_sel;
wire ir_xx_pc_reg_sel;
wire ir_xx_pcfifo_reg_sel;
wire ir_xx_pipefifo_reg_sel;
wire ir_xx_rsr_reg_sel;
wire ir_xx_wbbr_reg_sel;
wire pad_yy_icg_scan_en;
wire [63:0] rdata_0;
wire [63:0] rdata_1;
wire [63:0] rdata_2;
wire [63:0] rdata_3;
wire [63:0] regs_core_serial_data;
wire [63:0] regs_serial_data;
wire [63:0] serial_xx_data;
wire sm_ir_update_hacr;
wire [3 :0] sysio_had_dbg_mask;
// &Instance("gated_clk_cell", "x_had_ir_gated_clk"); @28
gated_clk_cell x_had_ir_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ir_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (sm_ir_update_hacr ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @29
// .external_en (1'b0), @30
// .global_en (1'b1), @31
// .module_en (1'b0), @32
// .local_en (sm_ir_update_hacr), @33
// .clk_out (ir_clk)); @34
//==============================================================================
// Update HACR
//==============================================================================
always @(posedge ir_clk or negedge cpurst_b)
begin
if (!cpurst_b)
hacr_reg[15:0] <= 16'h8200; // Async reset to point to HAD_ID
else if (sm_ir_update_hacr)
hacr_reg[15:0] <= serial_xx_data[15:0];
else
hacr_reg[15:0] <= hacr_reg[15:0];
end
//assign ir_corex_hacr[15:0] = hacr_reg[15:0];
assign ir_corex_wdata[63:0] = serial_xx_data[63:0];
//==============================================================================
// HACR commond decode
//==============================================================================
assign ir_sm_hacr_rw = hacr_reg[15];
assign rdata_0[63:0] = core0_regs_serial_data[63:0];
assign rdata_1[63:0] = core1_regs_serial_data[63:0];
assign rdata_2[63:0] = 64'b0;
assign rdata_3[63:0] = 64'b0;
assign core0_dbg_disable = 1'b0;
assign core1_dbg_disable = 1'b0;
assign core2_dbg_disable = 1'b0;
assign core3_dbg_disable = 1'b0;
assign ir_core0_sel = (hacr_reg[1:0] == 2'b00) && !core0_dbg_disable;
assign ir_core1_sel = (hacr_reg[1:0] == 2'b01) && !core1_dbg_disable;
assign ir_core2_sel = (hacr_reg[1:0] == 2'b10) && !core2_dbg_disable;
assign ir_core3_sel = (hacr_reg[1:0] == 2'b11) && !core3_dbg_disable;
assign ir_core0_priv_sel = ir_core0_sel && !sysio_had_dbg_mask[0];
assign ir_core1_priv_sel = ir_core1_sel && !sysio_had_dbg_mask[1];
assign ir_core2_priv_sel = ir_core2_sel && !sysio_had_dbg_mask[2];
assign ir_core3_priv_sel = ir_core3_sel && !sysio_had_dbg_mask[3];
assign regs_core_serial_data[63:0] = {64{ir_core0_priv_sel}} & rdata_0[63:0] |
{64{ir_core1_priv_sel}} & rdata_1[63:0] |
{64{ir_core2_priv_sel}} & rdata_2[63:0] |
{64{ir_core3_priv_sel}} & rdata_3[63:0];
// Bank3 data is in had common top
// Now only dbgfifo2 in bank3.
// Bank3 regs should care dbg disable.
assign ir_common_sel = (bank3_sel || ir_xx_id_reg_sel)
&& (ir_core0_sel || ir_core1_sel
|| ir_core2_sel || ir_core3_sel);
assign regs_serial_data[63:0] = ir_common_sel ? common_regs_data[63:0]
: regs_core_serial_data[63:0];
assign bank0_sel = (hacr_reg[6:4] == 3'd0);
assign bank2_sel = (hacr_reg[6:4] == 3'd2);
assign bank3_sel = (hacr_reg[6:4] == 3'd3);
assign hacr_index[4:0] = hacr_reg[12:8];
parameter ID_NUM = 5'd2;
parameter OTC_NUM = 5'd3;
parameter MBCA_NUM = 5'd4;
parameter MBCB_NUM = 5'd5;
parameter PCFIFO_NUM = 5'd6;
parameter BABA_NUM = 5'd7;
parameter BABB_NUM = 5'd8;
parameter BAMA_NUM = 5'd9;
parameter BAMB_NUM = 5'd10;
parameter WBBR_NUM = 5'd17;
parameter PC_NUM = 5'd19;
parameter CSR_NUM = 5'd21;
parameter DADDR_NUM = 5'd24;
parameter DDATA_NUM = 5'd25;
assign ir_xx_id_reg_sel = bank0_sel && (hacr_index[4:0] == ID_NUM);
assign ir_xx_otc_reg_sel = bank0_sel && (hacr_index[4:0] == OTC_NUM);
assign ir_xx_mbca_reg_sel = bank0_sel && (hacr_index[4:0] == MBCA_NUM);
assign ir_xx_mbcb_reg_sel = bank0_sel && (hacr_index[4:0] == MBCB_NUM);
assign ir_xx_bama_reg_sel = bank0_sel && (hacr_index[4:0] == BAMA_NUM);
assign ir_xx_bamb_reg_sel = bank0_sel && (hacr_index[4:0] == BAMB_NUM);
assign ir_xx_csr_reg_sel = bank0_sel && (hacr_index[4:0] == CSR_NUM);
assign ir_xx_baba_reg_sel = bank0_sel && (hacr_index[4:0] == BABA_NUM);
assign ir_xx_babb_reg_sel = bank0_sel && (hacr_index[4:0] == BABB_NUM);
assign ir_xx_wbbr_reg_sel = bank0_sel && (hacr_index[4:0] == WBBR_NUM);
assign ir_xx_pc_reg_sel = bank0_sel && (hacr_index[4:0] == PC_NUM);
assign ir_xx_pcfifo_reg_sel = bank0_sel && (hacr_index[4:0] == PCFIFO_NUM);
assign ir_xx_daddr_reg_sel = bank0_sel && (hacr_index[4:0] == DADDR_NUM);
assign ir_xx_ddata_reg_sel = bank0_sel && (hacr_index[4:0] == DDATA_NUM);
parameter DBGFIFO_NUM = 5'd4;
parameter PIPEFIFO_NUM = 5'd5;
assign ir_xx_pipefifo_reg_sel = bank2_sel && (hacr_index[4:0] == PIPEFIFO_NUM);
assign ir_xx_dbgfifo_reg_sel = bank2_sel && (hacr_index[4:0] == DBGFIFO_NUM);
parameter DBGFIFO2_NUM = 5'd0;
parameter RWR_NUM = 5'd1;
parameter DMS_NUM = 5'd2;
assign ir_xx_dbgfifo2_reg_sel = bank3_sel && (hacr_index[4:0] == DBGFIFO2_NUM);
assign ir_xx_rsr_reg_sel = bank3_sel && (hacr_index[4:0] == RWR_NUM);
assign ir_xx_dms_reg_sel = bank3_sel && (hacr_index[4:0] == DMS_NUM);
// &Force("output", "ir_xx_id_reg_sel"); @179
// &Force("output", "ir_xx_dbgfifo2_reg_sel"); @180
assign ir_xx_core0_sel = ir_core0_sel;
assign ir_xx_core1_sel = ir_core1_sel;
assign ir_xx_core2_sel = ir_core2_sel;
assign ir_xx_core3_sel = ir_core3_sel;
// &ModuleEnd; @187
endmodule |
Subsets and Splits