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module NV_NVDLA_DMAIF_rdrsp (
nvdla_core_clk
,nvdla_core_rstn
,cvif_rd_rsp_pd
,cvif_rd_rsp_valid
,cvif_rd_rsp_ready
,mcif_rd_rsp_pd
,mcif_rd_rsp_valid
,mcif_rd_rsp_ready
,dmaif_rd_rsp_pd
,dmaif_rd_rsp_pvld
,dmaif_rd_rsp_prdy
);
//////////////////////////////////////////////
input nvdla_core_clk;
input nvdla_core_rstn;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $maskbw;
//: $maskbw = $mask;
//: my $dmabw = ( $dmaif + $maskbw );
//: print qq( input [${dmabw}-1:0] cvif_rd_rsp_pd; \n);
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [257-1:0] cvif_rd_rsp_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input cvif_rd_rsp_valid;
output cvif_rd_rsp_ready;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $maskbw;
//: $maskbw = $mask;
//: my $dmabw = ( $dmaif + $maskbw );
//: print qq( input [${dmabw}-1:0] mcif_rd_rsp_pd; \n);
//: print qq( output [${dmabw}-1:0] dmaif_rd_rsp_pd; \n);
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [257-1:0] mcif_rd_rsp_pd;
output [257-1:0] dmaif_rd_rsp_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input mcif_rd_rsp_valid;
output mcif_rd_rsp_ready;
output dmaif_rd_rsp_pvld;
input dmaif_rd_rsp_prdy;
//////////////////////////////////////////////
wire dma_rd_rsp_rdy;
wire dma_rd_rsp_vld;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $maskbw;
//: $maskbw = $mask;
//: my $dmabw = ( $dmaif + $maskbw );
//: print qq( wire [${dmabw}-1:0] dma_rd_rsp_pd; \n);
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [257-1:0] dma_rd_rsp_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
//////////////////////////////////////////////
///////////////////////////////////////
// pipe before mux
///////////////////////////////////////
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $maskbw;
//: $maskbw = $mask;
//: my $dmabw = ( $dmaif + $maskbw );
//: &eperl::pipe(" -wid $dmabw -is -do mcif_rd_rsp_pd_d0 -vo mcif_rd_rsp_valid_d0 -ri dma_rd_rsp_rdy -di mcif_rd_rsp_pd -vi mcif_rd_rsp_valid -ro mcif_rd_rsp_ready ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg mcif_rd_rsp_ready;
reg skid_flop_mcif_rd_rsp_ready;
reg skid_flop_mcif_rd_rsp_valid;
reg [257-1:0] skid_flop_mcif_rd_rsp_pd;
reg pipe_skid_mcif_rd_rsp_valid;
reg [257-1:0] pipe_skid_mcif_rd_rsp_pd;
// Wire
wire skid_mcif_rd_rsp_valid;
wire [257-1:0] skid_mcif_rd_rsp_pd;
wire skid_mcif_rd_rsp_ready;
wire pipe_skid_mcif_rd_rsp_ready;
wire mcif_rd_rsp_valid_d0;
wire [257-1:0] mcif_rd_rsp_pd_d0;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mcif_rd_rsp_ready <= 1'b1;
skid_flop_mcif_rd_rsp_ready <= 1'b1;
end else begin
mcif_rd_rsp_ready <= skid_mcif_rd_rsp_ready;
skid_flop_mcif_rd_rsp_ready <= skid_mcif_rd_rsp_ready;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_mcif_rd_rsp_valid <= 1'b0;
end else begin
if (skid_flop_mcif_rd_rsp_ready) begin
skid_flop_mcif_rd_rsp_valid <= mcif_rd_rsp_valid;
end
end
end
assign skid_mcif_rd_rsp_valid = (skid_flop_mcif_rd_rsp_ready) ? mcif_rd_rsp_valid : skid_flop_mcif_rd_rsp_valid;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_mcif_rd_rsp_ready & mcif_rd_rsp_valid) begin
skid_flop_mcif_rd_rsp_pd[257-1:0] <= mcif_rd_rsp_pd[257-1:0];
end
end
assign skid_mcif_rd_rsp_pd[257-1:0] = (skid_flop_mcif_rd_rsp_ready) ? mcif_rd_rsp_pd[257-1:0] : skid_flop_mcif_rd_rsp_pd[257-1:0];
// PIPE READY
assign skid_mcif_rd_rsp_ready = pipe_skid_mcif_rd_rsp_ready || !pipe_skid_mcif_rd_rsp_valid;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_mcif_rd_rsp_valid <= 1'b0;
end else begin
if (skid_mcif_rd_rsp_ready) begin
pipe_skid_mcif_rd_rsp_valid <= skid_mcif_rd_rsp_valid;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_mcif_rd_rsp_ready && skid_mcif_rd_rsp_valid) begin
pipe_skid_mcif_rd_rsp_pd[257-1:0] <= skid_mcif_rd_rsp_pd[257-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_mcif_rd_rsp_ready = dma_rd_rsp_rdy;
assign mcif_rd_rsp_valid_d0 = pipe_skid_mcif_rd_rsp_valid;
assign mcif_rd_rsp_pd_d0 = pipe_skid_mcif_rd_rsp_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire cv_dma_rd_rsp_rdy;
assign cv_dma_rd_rsp_rdy = dma_rd_rsp_rdy;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $maskbw;
//: $maskbw = $mask;
//: my $dmabw = ( $dmaif + $maskbw );
//: &eperl::pipe(" -wid $dmabw -is -do cvif_rd_rsp_pd_d0 -vo cvif_rd_rsp_valid_d0 -ri cv_dma_rd_rsp_rdy -di cvif_rd_rsp_pd -vi cvif_rd_rsp_valid -ro cvif_rd_rsp_ready ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg cvif_rd_rsp_ready;
reg skid_flop_cvif_rd_rsp_ready;
reg skid_flop_cvif_rd_rsp_valid;
reg [257-1:0] skid_flop_cvif_rd_rsp_pd;
reg pipe_skid_cvif_rd_rsp_valid;
reg [257-1:0] pipe_skid_cvif_rd_rsp_pd;
// Wire
wire skid_cvif_rd_rsp_valid;
wire [257-1:0] skid_cvif_rd_rsp_pd;
wire skid_cvif_rd_rsp_ready;
wire pipe_skid_cvif_rd_rsp_ready;
wire cvif_rd_rsp_valid_d0;
wire [257-1:0] cvif_rd_rsp_pd_d0;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cvif_rd_rsp_ready <= 1'b1;
skid_flop_cvif_rd_rsp_ready <= 1'b1;
end else begin
cvif_rd_rsp_ready <= skid_cvif_rd_rsp_ready;
skid_flop_cvif_rd_rsp_ready <= skid_cvif_rd_rsp_ready;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_cvif_rd_rsp_valid <= 1'b0;
end else begin
if (skid_flop_cvif_rd_rsp_ready) begin
skid_flop_cvif_rd_rsp_valid <= cvif_rd_rsp_valid;
end
end
end
assign skid_cvif_rd_rsp_valid = (skid_flop_cvif_rd_rsp_ready) ? cvif_rd_rsp_valid : skid_flop_cvif_rd_rsp_valid;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_cvif_rd_rsp_ready & cvif_rd_rsp_valid) begin
skid_flop_cvif_rd_rsp_pd[257-1:0] <= cvif_rd_rsp_pd[257-1:0];
end
end
assign skid_cvif_rd_rsp_pd[257-1:0] = (skid_flop_cvif_rd_rsp_ready) ? cvif_rd_rsp_pd[257-1:0] : skid_flop_cvif_rd_rsp_pd[257-1:0];
// PIPE READY
assign skid_cvif_rd_rsp_ready = pipe_skid_cvif_rd_rsp_ready || !pipe_skid_cvif_rd_rsp_valid;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_cvif_rd_rsp_valid <= 1'b0;
end else begin
if (skid_cvif_rd_rsp_ready) begin
pipe_skid_cvif_rd_rsp_valid <= skid_cvif_rd_rsp_valid;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_cvif_rd_rsp_ready && skid_cvif_rd_rsp_valid) begin
pipe_skid_cvif_rd_rsp_pd[257-1:0] <= skid_cvif_rd_rsp_pd[257-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_cvif_rd_rsp_ready = cv_dma_rd_rsp_rdy;
assign cvif_rd_rsp_valid_d0 = pipe_skid_cvif_rd_rsp_valid;
assign cvif_rd_rsp_pd_d0 = pipe_skid_cvif_rd_rsp_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
///////////////////////////////////////
//mux
///////////////////////////////////////
assign dma_rd_rsp_vld = mcif_rd_rsp_valid_d0 | cvif_rd_rsp_valid_d0;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $maskbw;
//: $maskbw = $mask;
//: my $dmabw = ( $dmaif + $maskbw );
//: print qq(
//: assign dma_rd_rsp_pd = ({${dmabw}{mcif_rd_rsp_valid_d0}} & mcif_rd_rsp_pd_d0)
//: | ({${dmabw}{cvif_rd_rsp_valid_d0}} & cvif_rd_rsp_pd_d0);
//: );
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign dma_rd_rsp_pd = ({257{mcif_rd_rsp_valid_d0}} & mcif_rd_rsp_pd_d0)
| ({257{cvif_rd_rsp_valid_d0}} & cvif_rd_rsp_pd_d0);
//| eperl: generated_end (DO NOT EDIT ABOVE)
// //: &eperl::assert(" -type never -desc 'DMAIF: mcif and cvif should never return data both' -expr 'mcif_rd_rsp_valid_d0 & cvif_rd_rsp_valid_d0' ");
///////////////////////////////////////
// pipe after mux
///////////////////////////////////////
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $maskbw;
//: $maskbw = $mask;
//: my $dmabw = ( $dmaif + $maskbw );
//: &eperl::pipe(" -wid $dmabw -is -do dmaif_rd_rsp_pd -vo dmaif_rd_rsp_pvld -ri dmaif_rd_rsp_prdy -di dma_rd_rsp_pd -vi dma_rd_rsp_vld -ro dma_rd_rsp_rdy_f ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg dma_rd_rsp_rdy_f;
reg skid_flop_dma_rd_rsp_rdy_f;
reg skid_flop_dma_rd_rsp_vld;
reg [257-1:0] skid_flop_dma_rd_rsp_pd;
reg pipe_skid_dma_rd_rsp_vld;
reg [257-1:0] pipe_skid_dma_rd_rsp_pd;
// Wire
wire skid_dma_rd_rsp_vld;
wire [257-1:0] skid_dma_rd_rsp_pd;
wire skid_dma_rd_rsp_rdy_f;
wire pipe_skid_dma_rd_rsp_rdy_f;
wire dmaif_rd_rsp_pvld;
wire [257-1:0] dmaif_rd_rsp_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
dma_rd_rsp_rdy_f <= 1'b1;
skid_flop_dma_rd_rsp_rdy_f <= 1'b1;
end else begin
dma_rd_rsp_rdy_f <= skid_dma_rd_rsp_rdy_f;
skid_flop_dma_rd_rsp_rdy_f <= skid_dma_rd_rsp_rdy_f;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_dma_rd_rsp_vld <= 1'b0;
end else begin
if (skid_flop_dma_rd_rsp_rdy_f) begin
skid_flop_dma_rd_rsp_vld <= dma_rd_rsp_vld;
end
end
end
assign skid_dma_rd_rsp_vld = (skid_flop_dma_rd_rsp_rdy_f) ? dma_rd_rsp_vld : skid_flop_dma_rd_rsp_vld;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_dma_rd_rsp_rdy_f & dma_rd_rsp_vld) begin
skid_flop_dma_rd_rsp_pd[257-1:0] <= dma_rd_rsp_pd[257-1:0];
end
end
assign skid_dma_rd_rsp_pd[257-1:0] = (skid_flop_dma_rd_rsp_rdy_f) ? dma_rd_rsp_pd[257-1:0] : skid_flop_dma_rd_rsp_pd[257-1:0];
// PIPE READY
assign skid_dma_rd_rsp_rdy_f = pipe_skid_dma_rd_rsp_rdy_f || !pipe_skid_dma_rd_rsp_vld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_dma_rd_rsp_vld <= 1'b0;
end else begin
if (skid_dma_rd_rsp_rdy_f) begin
pipe_skid_dma_rd_rsp_vld <= skid_dma_rd_rsp_vld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_dma_rd_rsp_rdy_f && skid_dma_rd_rsp_vld) begin
pipe_skid_dma_rd_rsp_pd[257-1:0] <= skid_dma_rd_rsp_pd[257-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_dma_rd_rsp_rdy_f = dmaif_rd_rsp_prdy;
assign dmaif_rd_rsp_pvld = pipe_skid_dma_rd_rsp_vld;
assign dmaif_rd_rsp_pd = pipe_skid_dma_rd_rsp_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign dma_rd_rsp_rdy = dma_rd_rsp_rdy_f;
endmodule |
module NV_NVDLA_MCIF_READ_ig (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,pwrbus_ram_pd
,reg2dp_rd_os_cnt
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print(" ,reg2dp_rd_weight_${client}\n");
//: }
//: foreach my $client (@rdma_name) {
//: print (" ,${client}2mcif_rd_cdt_lat_fifo_pop\n");
//: print (" ,${client}2mcif_rd_req_valid\n");
//: print (" ,${client}2mcif_rd_req_ready\n");
//: print (" ,${client}2mcif_rd_req_pd\n");
//:}
//| eperl: generated_beg (DO NOT EDIT BELOW)
,reg2dp_rd_weight_cdma_dat
,reg2dp_rd_weight_cdma_wt
,reg2dp_rd_weight_sdp
,reg2dp_rd_weight_sdp_b
,reg2dp_rd_weight_sdp_n
,reg2dp_rd_weight_sdp_e
,reg2dp_rd_weight_pdp
,reg2dp_rd_weight_cdp
,reg2dp_rd_weight_bdma
,cdma_dat2mcif_rd_cdt_lat_fifo_pop
,cdma_dat2mcif_rd_req_valid
,cdma_dat2mcif_rd_req_ready
,cdma_dat2mcif_rd_req_pd
,cdma_wt2mcif_rd_cdt_lat_fifo_pop
,cdma_wt2mcif_rd_req_valid
,cdma_wt2mcif_rd_req_ready
,cdma_wt2mcif_rd_req_pd
,sdp2mcif_rd_cdt_lat_fifo_pop
,sdp2mcif_rd_req_valid
,sdp2mcif_rd_req_ready
,sdp2mcif_rd_req_pd
,sdp_b2mcif_rd_cdt_lat_fifo_pop
,sdp_b2mcif_rd_req_valid
,sdp_b2mcif_rd_req_ready
,sdp_b2mcif_rd_req_pd
,sdp_n2mcif_rd_cdt_lat_fifo_pop
,sdp_n2mcif_rd_req_valid
,sdp_n2mcif_rd_req_ready
,sdp_n2mcif_rd_req_pd
,sdp_e2mcif_rd_cdt_lat_fifo_pop
,sdp_e2mcif_rd_req_valid
,sdp_e2mcif_rd_req_ready
,sdp_e2mcif_rd_req_pd
,pdp2mcif_rd_cdt_lat_fifo_pop
,pdp2mcif_rd_req_valid
,pdp2mcif_rd_req_ready
,pdp2mcif_rd_req_pd
,cdp2mcif_rd_cdt_lat_fifo_pop
,cdp2mcif_rd_req_valid
,cdp2mcif_rd_req_ready
,cdp2mcif_rd_req_pd
,bdma2mcif_rd_cdt_lat_fifo_pop
,bdma2mcif_rd_req_valid
,bdma2mcif_rd_req_ready
,bdma2mcif_rd_req_pd
//| eperl: generated_end (DO NOT EDIT ABOVE)
,eg2ig_axi_vld
,mcif2noc_axi_ar_araddr //|> o
,mcif2noc_axi_ar_arready //|< i
,mcif2noc_axi_ar_arid //|> o
,mcif2noc_axi_ar_arlen //|> o
,mcif2noc_axi_ar_arvalid //|> o
);
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
input [7:0] reg2dp_rd_os_cnt;
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print("input [7:0] reg2dp_rd_weight_${client};\n");
//: }
//: foreach my $client (@rdma_name) {
//: print ("input ${client}2mcif_rd_cdt_lat_fifo_pop;\n");
//: print ("input ${client}2mcif_rd_req_valid;\n");
//: print ("output ${client}2mcif_rd_req_ready;\n");
//: print qq(input [79 -1:0] ${client}2mcif_rd_req_pd;\n);
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [7:0] reg2dp_rd_weight_cdma_dat;
input [7:0] reg2dp_rd_weight_cdma_wt;
input [7:0] reg2dp_rd_weight_sdp;
input [7:0] reg2dp_rd_weight_sdp_b;
input [7:0] reg2dp_rd_weight_sdp_n;
input [7:0] reg2dp_rd_weight_sdp_e;
input [7:0] reg2dp_rd_weight_pdp;
input [7:0] reg2dp_rd_weight_cdp;
input [7:0] reg2dp_rd_weight_bdma;
input cdma_dat2mcif_rd_cdt_lat_fifo_pop;
input cdma_dat2mcif_rd_req_valid;
output cdma_dat2mcif_rd_req_ready;
input [79 -1:0] cdma_dat2mcif_rd_req_pd;
input cdma_wt2mcif_rd_cdt_lat_fifo_pop;
input cdma_wt2mcif_rd_req_valid;
output cdma_wt2mcif_rd_req_ready;
input [79 -1:0] cdma_wt2mcif_rd_req_pd;
input sdp2mcif_rd_cdt_lat_fifo_pop;
input sdp2mcif_rd_req_valid;
output sdp2mcif_rd_req_ready;
input [79 -1:0] sdp2mcif_rd_req_pd;
input sdp_b2mcif_rd_cdt_lat_fifo_pop;
input sdp_b2mcif_rd_req_valid;
output sdp_b2mcif_rd_req_ready;
input [79 -1:0] sdp_b2mcif_rd_req_pd;
input sdp_n2mcif_rd_cdt_lat_fifo_pop;
input sdp_n2mcif_rd_req_valid;
output sdp_n2mcif_rd_req_ready;
input [79 -1:0] sdp_n2mcif_rd_req_pd;
input sdp_e2mcif_rd_cdt_lat_fifo_pop;
input sdp_e2mcif_rd_req_valid;
output sdp_e2mcif_rd_req_ready;
input [79 -1:0] sdp_e2mcif_rd_req_pd;
input pdp2mcif_rd_cdt_lat_fifo_pop;
input pdp2mcif_rd_req_valid;
output pdp2mcif_rd_req_ready;
input [79 -1:0] pdp2mcif_rd_req_pd;
input cdp2mcif_rd_cdt_lat_fifo_pop;
input cdp2mcif_rd_req_valid;
output cdp2mcif_rd_req_ready;
input [79 -1:0] cdp2mcif_rd_req_pd;
input bdma2mcif_rd_cdt_lat_fifo_pop;
input bdma2mcif_rd_req_valid;
output bdma2mcif_rd_req_ready;
input [79 -1:0] bdma2mcif_rd_req_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
output mcif2noc_axi_ar_arvalid;
input mcif2noc_axi_ar_arready;
output [7:0] mcif2noc_axi_ar_arid;
output [3:0] mcif2noc_axi_ar_arlen;
output [64 -1:0] mcif2noc_axi_ar_araddr;
input eg2ig_axi_vld;
//:for (my $i=0;$i<9;$i++) {
//: print qq(wire [64 +10:0] bpt2arb_req${i}_pd;\n);
//: print ("wire bpt2arb_req${i}_ready;\n");
//: print ("wire bpt2arb_req${i}_valid;\n");
//:}
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [64 +10:0] bpt2arb_req0_pd;
wire bpt2arb_req0_ready;
wire bpt2arb_req0_valid;
wire [64 +10:0] bpt2arb_req1_pd;
wire bpt2arb_req1_ready;
wire bpt2arb_req1_valid;
wire [64 +10:0] bpt2arb_req2_pd;
wire bpt2arb_req2_ready;
wire bpt2arb_req2_valid;
wire [64 +10:0] bpt2arb_req3_pd;
wire bpt2arb_req3_ready;
wire bpt2arb_req3_valid;
wire [64 +10:0] bpt2arb_req4_pd;
wire bpt2arb_req4_ready;
wire bpt2arb_req4_valid;
wire [64 +10:0] bpt2arb_req5_pd;
wire bpt2arb_req5_ready;
wire bpt2arb_req5_valid;
wire [64 +10:0] bpt2arb_req6_pd;
wire bpt2arb_req6_ready;
wire bpt2arb_req6_valid;
wire [64 +10:0] bpt2arb_req7_pd;
wire bpt2arb_req7_ready;
wire bpt2arb_req7_valid;
wire [64 +10:0] bpt2arb_req8_pd;
wire bpt2arb_req8_ready;
wire bpt2arb_req8_valid;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire [64 +10:0] arb2spt_req_pd;
wire arb2spt_req_ready;
wire arb2spt_req_valid;
wire [64 +10:0] spt2cvt_req_pd;
wire spt2cvt_req_valid;
wire spt2cvt_req_ready;
//---------------------read_bpt inst--------------------------------//
//: my $i = 0;
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print("NV_NVDLA_MCIF_READ_IG_bpt u_bpt${i} (\n");
//: print (" .nvdla_core_clk(nvdla_core_clk)\n");
//: print (" ,.nvdla_core_rstn(nvdla_core_rstn)\n");
//: print (" ,.dma2bpt_cdt_lat_fifo_pop(${client}2mcif_rd_cdt_lat_fifo_pop)\n");
//: print (" ,.dma2bpt_req_valid(${client}2mcif_rd_req_valid)\n");
//: print (" ,.dma2bpt_req_ready(${client}2mcif_rd_req_ready)\n");
//: print (" ,.dma2bpt_req_pd(${client}2mcif_rd_req_pd)\n");
//: print (" ,.bpt2arb_req_valid(bpt2arb_req${i}_valid)\n");
//: print (" ,.bpt2arb_req_ready(bpt2arb_req${i}_ready)\n");
//: print (" ,.bpt2arb_req_pd(bpt2arb_req${i}_pd)\n");
//: print (" ,.tieoff_axid(`tieoff_axid_${client})\n");
//: print (" ,.tieoff_lat_fifo_depth(`tieoff_depth_${client})\n");
//: print (");\n");
//: $i++;
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
NV_NVDLA_MCIF_READ_IG_bpt u_bpt0 (
.nvdla_core_clk(nvdla_core_clk)
,.nvdla_core_rstn(nvdla_core_rstn)
,.dma2bpt_cdt_lat_fifo_pop(cdma_dat2mcif_rd_cdt_lat_fifo_pop)
,.dma2bpt_req_valid(cdma_dat2mcif_rd_req_valid)
,.dma2bpt_req_ready(cdma_dat2mcif_rd_req_ready)
,.dma2bpt_req_pd(cdma_dat2mcif_rd_req_pd)
,.bpt2arb_req_valid(bpt2arb_req0_valid)
,.bpt2arb_req_ready(bpt2arb_req0_ready)
,.bpt2arb_req_pd(bpt2arb_req0_pd)
,.tieoff_axid(`tieoff_axid_cdma_dat)
,.tieoff_lat_fifo_depth(`tieoff_depth_cdma_dat)
);
NV_NVDLA_MCIF_READ_IG_bpt u_bpt1 (
.nvdla_core_clk(nvdla_core_clk)
,.nvdla_core_rstn(nvdla_core_rstn)
,.dma2bpt_cdt_lat_fifo_pop(cdma_wt2mcif_rd_cdt_lat_fifo_pop)
,.dma2bpt_req_valid(cdma_wt2mcif_rd_req_valid)
,.dma2bpt_req_ready(cdma_wt2mcif_rd_req_ready)
,.dma2bpt_req_pd(cdma_wt2mcif_rd_req_pd)
,.bpt2arb_req_valid(bpt2arb_req1_valid)
,.bpt2arb_req_ready(bpt2arb_req1_ready)
,.bpt2arb_req_pd(bpt2arb_req1_pd)
,.tieoff_axid(`tieoff_axid_cdma_wt)
,.tieoff_lat_fifo_depth(`tieoff_depth_cdma_wt)
);
NV_NVDLA_MCIF_READ_IG_bpt u_bpt2 (
.nvdla_core_clk(nvdla_core_clk)
,.nvdla_core_rstn(nvdla_core_rstn)
,.dma2bpt_cdt_lat_fifo_pop(sdp2mcif_rd_cdt_lat_fifo_pop)
,.dma2bpt_req_valid(sdp2mcif_rd_req_valid)
,.dma2bpt_req_ready(sdp2mcif_rd_req_ready)
,.dma2bpt_req_pd(sdp2mcif_rd_req_pd)
,.bpt2arb_req_valid(bpt2arb_req2_valid)
,.bpt2arb_req_ready(bpt2arb_req2_ready)
,.bpt2arb_req_pd(bpt2arb_req2_pd)
,.tieoff_axid(`tieoff_axid_sdp)
,.tieoff_lat_fifo_depth(`tieoff_depth_sdp)
);
NV_NVDLA_MCIF_READ_IG_bpt u_bpt3 (
.nvdla_core_clk(nvdla_core_clk)
,.nvdla_core_rstn(nvdla_core_rstn)
,.dma2bpt_cdt_lat_fifo_pop(sdp_b2mcif_rd_cdt_lat_fifo_pop)
,.dma2bpt_req_valid(sdp_b2mcif_rd_req_valid)
,.dma2bpt_req_ready(sdp_b2mcif_rd_req_ready)
,.dma2bpt_req_pd(sdp_b2mcif_rd_req_pd)
,.bpt2arb_req_valid(bpt2arb_req3_valid)
,.bpt2arb_req_ready(bpt2arb_req3_ready)
,.bpt2arb_req_pd(bpt2arb_req3_pd)
,.tieoff_axid(`tieoff_axid_sdp_b)
,.tieoff_lat_fifo_depth(`tieoff_depth_sdp_b)
);
NV_NVDLA_MCIF_READ_IG_bpt u_bpt4 (
.nvdla_core_clk(nvdla_core_clk)
,.nvdla_core_rstn(nvdla_core_rstn)
,.dma2bpt_cdt_lat_fifo_pop(sdp_n2mcif_rd_cdt_lat_fifo_pop)
,.dma2bpt_req_valid(sdp_n2mcif_rd_req_valid)
,.dma2bpt_req_ready(sdp_n2mcif_rd_req_ready)
,.dma2bpt_req_pd(sdp_n2mcif_rd_req_pd)
,.bpt2arb_req_valid(bpt2arb_req4_valid)
,.bpt2arb_req_ready(bpt2arb_req4_ready)
,.bpt2arb_req_pd(bpt2arb_req4_pd)
,.tieoff_axid(`tieoff_axid_sdp_n)
,.tieoff_lat_fifo_depth(`tieoff_depth_sdp_n)
);
NV_NVDLA_MCIF_READ_IG_bpt u_bpt5 (
.nvdla_core_clk(nvdla_core_clk)
,.nvdla_core_rstn(nvdla_core_rstn)
,.dma2bpt_cdt_lat_fifo_pop(sdp_e2mcif_rd_cdt_lat_fifo_pop)
,.dma2bpt_req_valid(sdp_e2mcif_rd_req_valid)
,.dma2bpt_req_ready(sdp_e2mcif_rd_req_ready)
,.dma2bpt_req_pd(sdp_e2mcif_rd_req_pd)
,.bpt2arb_req_valid(bpt2arb_req5_valid)
,.bpt2arb_req_ready(bpt2arb_req5_ready)
,.bpt2arb_req_pd(bpt2arb_req5_pd)
,.tieoff_axid(`tieoff_axid_sdp_e)
,.tieoff_lat_fifo_depth(`tieoff_depth_sdp_e)
);
NV_NVDLA_MCIF_READ_IG_bpt u_bpt6 (
.nvdla_core_clk(nvdla_core_clk)
,.nvdla_core_rstn(nvdla_core_rstn)
,.dma2bpt_cdt_lat_fifo_pop(pdp2mcif_rd_cdt_lat_fifo_pop)
,.dma2bpt_req_valid(pdp2mcif_rd_req_valid)
,.dma2bpt_req_ready(pdp2mcif_rd_req_ready)
,.dma2bpt_req_pd(pdp2mcif_rd_req_pd)
,.bpt2arb_req_valid(bpt2arb_req6_valid)
,.bpt2arb_req_ready(bpt2arb_req6_ready)
,.bpt2arb_req_pd(bpt2arb_req6_pd)
,.tieoff_axid(`tieoff_axid_pdp)
,.tieoff_lat_fifo_depth(`tieoff_depth_pdp)
);
NV_NVDLA_MCIF_READ_IG_bpt u_bpt7 (
.nvdla_core_clk(nvdla_core_clk)
,.nvdla_core_rstn(nvdla_core_rstn)
,.dma2bpt_cdt_lat_fifo_pop(cdp2mcif_rd_cdt_lat_fifo_pop)
,.dma2bpt_req_valid(cdp2mcif_rd_req_valid)
,.dma2bpt_req_ready(cdp2mcif_rd_req_ready)
,.dma2bpt_req_pd(cdp2mcif_rd_req_pd)
,.bpt2arb_req_valid(bpt2arb_req7_valid)
,.bpt2arb_req_ready(bpt2arb_req7_ready)
,.bpt2arb_req_pd(bpt2arb_req7_pd)
,.tieoff_axid(`tieoff_axid_cdp)
,.tieoff_lat_fifo_depth(`tieoff_depth_cdp)
);
NV_NVDLA_MCIF_READ_IG_bpt u_bpt8 (
.nvdla_core_clk(nvdla_core_clk)
,.nvdla_core_rstn(nvdla_core_rstn)
,.dma2bpt_cdt_lat_fifo_pop(bdma2mcif_rd_cdt_lat_fifo_pop)
,.dma2bpt_req_valid(bdma2mcif_rd_req_valid)
,.dma2bpt_req_ready(bdma2mcif_rd_req_ready)
,.dma2bpt_req_pd(bdma2mcif_rd_req_pd)
,.bpt2arb_req_valid(bpt2arb_req8_valid)
,.bpt2arb_req_ready(bpt2arb_req8_ready)
,.bpt2arb_req_pd(bpt2arb_req8_pd)
,.tieoff_axid(`tieoff_axid_bdma)
,.tieoff_lat_fifo_depth(`tieoff_depth_bdma)
);
//| eperl: generated_end (DO NOT EDIT ABOVE)
NV_NVDLA_MCIF_READ_IG_arb u_arb (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
//: my $i = 0;
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print(" ,.reg2dp_rd_weight${i}(reg2dp_rd_weight_${client})\n");
//: $i++;
//: }
//: $i = 0;
//: foreach my $client (@rdma_name) {
//: print(" ,.bpt2arb_req${i}_valid(bpt2arb_req${i}_valid)\n");
//: print(" ,.bpt2arb_req${i}_ready(bpt2arb_req${i}_ready)\n");
//: print(" ,.bpt2arb_req${i}_pd(bpt2arb_req${i}_pd)\n");
//: $i++;
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.reg2dp_rd_weight0(reg2dp_rd_weight_cdma_dat)
,.reg2dp_rd_weight1(reg2dp_rd_weight_cdma_wt)
,.reg2dp_rd_weight2(reg2dp_rd_weight_sdp)
,.reg2dp_rd_weight3(reg2dp_rd_weight_sdp_b)
,.reg2dp_rd_weight4(reg2dp_rd_weight_sdp_n)
,.reg2dp_rd_weight5(reg2dp_rd_weight_sdp_e)
,.reg2dp_rd_weight6(reg2dp_rd_weight_pdp)
,.reg2dp_rd_weight7(reg2dp_rd_weight_cdp)
,.reg2dp_rd_weight8(reg2dp_rd_weight_bdma)
,.bpt2arb_req0_valid(bpt2arb_req0_valid)
,.bpt2arb_req0_ready(bpt2arb_req0_ready)
,.bpt2arb_req0_pd(bpt2arb_req0_pd)
,.bpt2arb_req1_valid(bpt2arb_req1_valid)
,.bpt2arb_req1_ready(bpt2arb_req1_ready)
,.bpt2arb_req1_pd(bpt2arb_req1_pd)
,.bpt2arb_req2_valid(bpt2arb_req2_valid)
,.bpt2arb_req2_ready(bpt2arb_req2_ready)
,.bpt2arb_req2_pd(bpt2arb_req2_pd)
,.bpt2arb_req3_valid(bpt2arb_req3_valid)
,.bpt2arb_req3_ready(bpt2arb_req3_ready)
,.bpt2arb_req3_pd(bpt2arb_req3_pd)
,.bpt2arb_req4_valid(bpt2arb_req4_valid)
,.bpt2arb_req4_ready(bpt2arb_req4_ready)
,.bpt2arb_req4_pd(bpt2arb_req4_pd)
,.bpt2arb_req5_valid(bpt2arb_req5_valid)
,.bpt2arb_req5_ready(bpt2arb_req5_ready)
,.bpt2arb_req5_pd(bpt2arb_req5_pd)
,.bpt2arb_req6_valid(bpt2arb_req6_valid)
,.bpt2arb_req6_ready(bpt2arb_req6_ready)
,.bpt2arb_req6_pd(bpt2arb_req6_pd)
,.bpt2arb_req7_valid(bpt2arb_req7_valid)
,.bpt2arb_req7_ready(bpt2arb_req7_ready)
,.bpt2arb_req7_pd(bpt2arb_req7_pd)
,.bpt2arb_req8_valid(bpt2arb_req8_valid)
,.bpt2arb_req8_ready(bpt2arb_req8_ready)
,.bpt2arb_req8_pd(bpt2arb_req8_pd)
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.arb2spt_req_valid (arb2spt_req_valid) //|> w
,.arb2spt_req_ready (arb2spt_req_ready) //|< w
,.arb2spt_req_pd (arb2spt_req_pd) //|> w
);
/*
NV_NVDLA_MCIF_READ_IG_spt u_spt (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.arb2spt_req_valid (arb2spt_req_valid) //|< w
,.arb2spt_req_ready (arb2spt_req_ready) //|> w
,.arb2spt_req_pd (arb2spt_req_pd) //|< w
,.spt2cvt_req_valid (spt2cvt_req_valid) //|> w
,.spt2cvt_req_ready (spt2cvt_req_ready) //|< w
,.spt2cvt_req_pd (spt2cvt_req_pd) //|> w
);
*/
NV_NVDLA_MCIF_READ_IG_cvt u_cvt (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|< i
,.eg2ig_axi_vld (eg2ig_axi_vld) //|< i
,.spt2cvt_req_valid (arb2spt_req_valid) //|< w
,.spt2cvt_req_ready (arb2spt_req_ready) //|> w
,.spt2cvt_req_pd (arb2spt_req_pd) //|< w
,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o
,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i
,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0]) //|> o
,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0]) //|> o
,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr) //|> o
);
endmodule |
module NV_NVDLA_partition_a (
cacc2sdp_ready
,csb2cacc_req_pvld
,csb2cacc_req_prdy
,csb2cacc_req_pd
,cacc2csb_resp_pd
,cacc2csb_resp_valid
,cacc2glb_done_intr_pd
,direct_reset_
,dla_reset_rstn
,global_clk_ovr_on
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: ,mac_a2accu_data${i} )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,mac_a2accu_data0
,mac_a2accu_data1
,mac_a2accu_data2
,mac_a2accu_data3
,mac_a2accu_data4
,mac_a2accu_data5
,mac_a2accu_data6
,mac_a2accu_data7
,mac_a2accu_data8
,mac_a2accu_data9
,mac_a2accu_data10
,mac_a2accu_data11
,mac_a2accu_data12
,mac_a2accu_data13
,mac_a2accu_data14
,mac_a2accu_data15
//| eperl: generated_end (DO NOT EDIT ABOVE)
,mac_a2accu_mask
,mac_a2accu_mode
,mac_a2accu_pd
,mac_a2accu_pvld
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: ,mac_b2accu_data${i} )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,mac_b2accu_data0
,mac_b2accu_data1
,mac_b2accu_data2
,mac_b2accu_data3
,mac_b2accu_data4
,mac_b2accu_data5
,mac_b2accu_data6
,mac_b2accu_data7
,mac_b2accu_data8
,mac_b2accu_data9
,mac_b2accu_data10
,mac_b2accu_data11
,mac_b2accu_data12
,mac_b2accu_data13
,mac_b2accu_data14
,mac_b2accu_data15
//| eperl: generated_end (DO NOT EDIT ABOVE)
,mac_b2accu_mask
,mac_b2accu_mode
,mac_b2accu_pd
,mac_b2accu_pvld
,nvdla_clk_ovr_on
,nvdla_core_clk
,pwrbus_ram_pd
,test_mode
,tmc2slcg_disable_clock_gating
,accu2sc_credit_size
,accu2sc_credit_vld
,cacc2sdp_pd
,cacc2sdp_valid
);
//
// NV_NVDLA_partition_a_io.v
//
input test_mode;
input direct_reset_;
input global_clk_ovr_on;
input tmc2slcg_disable_clock_gating;
output accu2sc_credit_vld; /* data valid */
output [2:0] accu2sc_credit_size;
output cacc2csb_resp_valid; /* data valid */
output [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */
output [1:0] cacc2glb_done_intr_pd;
input csb2cacc_req_pvld; /* data valid */
output csb2cacc_req_prdy; /* data return handshake */
input [62:0] csb2cacc_req_pd;
output cacc2sdp_valid; /* data valid */
input cacc2sdp_ready; /* data return handshake */
output [32*16 +2 -1:0] cacc2sdp_pd;
input mac_a2accu_pvld; /* data valid */
input [32/2 -1:0] mac_a2accu_mask;
input mac_a2accu_mode;
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: input [22 -1:0] mac_a2accu_data${i}; )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [22 -1:0] mac_a2accu_data0;
input [22 -1:0] mac_a2accu_data1;
input [22 -1:0] mac_a2accu_data2;
input [22 -1:0] mac_a2accu_data3;
input [22 -1:0] mac_a2accu_data4;
input [22 -1:0] mac_a2accu_data5;
input [22 -1:0] mac_a2accu_data6;
input [22 -1:0] mac_a2accu_data7;
input [22 -1:0] mac_a2accu_data8;
input [22 -1:0] mac_a2accu_data9;
input [22 -1:0] mac_a2accu_data10;
input [22 -1:0] mac_a2accu_data11;
input [22 -1:0] mac_a2accu_data12;
input [22 -1:0] mac_a2accu_data13;
input [22 -1:0] mac_a2accu_data14;
input [22 -1:0] mac_a2accu_data15;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input [8:0] mac_a2accu_pd;
input mac_b2accu_pvld; /* data valid */
input [32/2 -1:0] mac_b2accu_mask;
input mac_b2accu_mode;
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: input [22 -1:0] mac_b2accu_data${i}; )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [22 -1:0] mac_b2accu_data0;
input [22 -1:0] mac_b2accu_data1;
input [22 -1:0] mac_b2accu_data2;
input [22 -1:0] mac_b2accu_data3;
input [22 -1:0] mac_b2accu_data4;
input [22 -1:0] mac_b2accu_data5;
input [22 -1:0] mac_b2accu_data6;
input [22 -1:0] mac_b2accu_data7;
input [22 -1:0] mac_b2accu_data8;
input [22 -1:0] mac_b2accu_data9;
input [22 -1:0] mac_b2accu_data10;
input [22 -1:0] mac_b2accu_data11;
input [22 -1:0] mac_b2accu_data12;
input [22 -1:0] mac_b2accu_data13;
input [22 -1:0] mac_b2accu_data14;
input [22 -1:0] mac_b2accu_data15;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input [8:0] mac_b2accu_pd;
input [31:0] pwrbus_ram_pd;
//input la_r_clk;
//input larstn;
input nvdla_core_clk;
input dla_reset_rstn;
input nvdla_clk_ovr_on;
wire dla_clk_ovr_on_sync;
wire global_clk_ovr_on_sync;
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: wire [22 -1:0] mac_b2accu_data${i}; )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [22 -1:0] mac_b2accu_data0;
wire [22 -1:0] mac_b2accu_data1;
wire [22 -1:0] mac_b2accu_data2;
wire [22 -1:0] mac_b2accu_data3;
wire [22 -1:0] mac_b2accu_data4;
wire [22 -1:0] mac_b2accu_data5;
wire [22 -1:0] mac_b2accu_data6;
wire [22 -1:0] mac_b2accu_data7;
wire [22 -1:0] mac_b2accu_data8;
wire [22 -1:0] mac_b2accu_data9;
wire [22 -1:0] mac_b2accu_data10;
wire [22 -1:0] mac_b2accu_data11;
wire [22 -1:0] mac_b2accu_data12;
wire [22 -1:0] mac_b2accu_data13;
wire [22 -1:0] mac_b2accu_data14;
wire [22 -1:0] mac_b2accu_data15;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire [32/2 -1:0] mac_b2accu_mask;
wire mac_b2accu_mode;
wire [8:0] mac_b2accu_pd;
wire mac_b2accu_pvld;
wire nvdla_core_rstn;
////////////////////////////////////////////////////////////////////////
// NVDLA Partition M: Reset Syncer //
////////////////////////////////////////////////////////////////////////
NV_NVDLA_reset u_partition_a_reset (
.dla_reset_rstn (dla_reset_rstn) //|< i
,.direct_reset_ (direct_reset_) //|< i
,.test_mode (test_mode) //|< i
,.synced_rstn (nvdla_core_rstn) //|> w
,.nvdla_clk (nvdla_core_clk) //|< i
);
////////////////////////////////////////////////////////////////////////
// SLCG override
////////////////////////////////////////////////////////////////////////
NV_NVDLA_sync3d u_dla_clk_ovr_on_sync (
.clk (nvdla_core_clk) //|< i
,.sync_i (nvdla_clk_ovr_on) //|< i
,.sync_o (dla_clk_ovr_on_sync) //|> w
);
NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync (
.clk (nvdla_core_clk) //|< i
,.prst (nvdla_core_rstn) //|< w
,.sync_i (global_clk_ovr_on) //|< i
,.sync_o (global_clk_ovr_on_sync) //|> w
);
////////////////////////////////////////////////////////////////////////
// NVDLA Partition A: Convolution Accumulator //
////////////////////////////////////////////////////////////////////////
//stepheng, modify for cacc verification
NV_NVDLA_cacc u_NV_NVDLA_cacc (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.csb2cacc_req_pvld (csb2cacc_req_pvld)
,.csb2cacc_req_prdy (csb2cacc_req_prdy)
,.csb2cacc_req_pd (csb2cacc_req_pd)
,.cacc2csb_resp_valid (cacc2csb_resp_valid)
,.cacc2csb_resp_pd (cacc2csb_resp_pd)
,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd)
,.mac_a2accu_pvld (mac_a2accu_pvld) //|< i
,.mac_a2accu_mask (mac_a2accu_mask[32/2 -1:0]) //|< i
,.mac_a2accu_mode (mac_a2accu_mode) //|< i
//:for(my $i=0; $i<32/2; $i++){
//: print ",.mac_a2accu_data${i} (mac_a2accu_data${i}) \n"; #//|< i
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.mac_a2accu_data0 (mac_a2accu_data0)
,.mac_a2accu_data1 (mac_a2accu_data1)
,.mac_a2accu_data2 (mac_a2accu_data2)
,.mac_a2accu_data3 (mac_a2accu_data3)
,.mac_a2accu_data4 (mac_a2accu_data4)
,.mac_a2accu_data5 (mac_a2accu_data5)
,.mac_a2accu_data6 (mac_a2accu_data6)
,.mac_a2accu_data7 (mac_a2accu_data7)
,.mac_a2accu_data8 (mac_a2accu_data8)
,.mac_a2accu_data9 (mac_a2accu_data9)
,.mac_a2accu_data10 (mac_a2accu_data10)
,.mac_a2accu_data11 (mac_a2accu_data11)
,.mac_a2accu_data12 (mac_a2accu_data12)
,.mac_a2accu_data13 (mac_a2accu_data13)
,.mac_a2accu_data14 (mac_a2accu_data14)
,.mac_a2accu_data15 (mac_a2accu_data15)
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.mac_a2accu_pd (mac_a2accu_pd[8:0]) //|< i
,.mac_b2accu_pvld (mac_b2accu_pvld) //|< w
,.mac_b2accu_mask (mac_b2accu_mask[32/2 -1:0]) //|< w
,.mac_b2accu_mode (mac_b2accu_mode) //|< w
//:for(my $i=0; $i<32/2; $i++){
//: print ",.mac_b2accu_data${i} (mac_b2accu_data${i}) \n"; #//|< i
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.mac_b2accu_data0 (mac_b2accu_data0)
,.mac_b2accu_data1 (mac_b2accu_data1)
,.mac_b2accu_data2 (mac_b2accu_data2)
,.mac_b2accu_data3 (mac_b2accu_data3)
,.mac_b2accu_data4 (mac_b2accu_data4)
,.mac_b2accu_data5 (mac_b2accu_data5)
,.mac_b2accu_data6 (mac_b2accu_data6)
,.mac_b2accu_data7 (mac_b2accu_data7)
,.mac_b2accu_data8 (mac_b2accu_data8)
,.mac_b2accu_data9 (mac_b2accu_data9)
,.mac_b2accu_data10 (mac_b2accu_data10)
,.mac_b2accu_data11 (mac_b2accu_data11)
,.mac_b2accu_data12 (mac_b2accu_data12)
,.mac_b2accu_data13 (mac_b2accu_data13)
,.mac_b2accu_data14 (mac_b2accu_data14)
,.mac_b2accu_data15 (mac_b2accu_data15)
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.mac_b2accu_pd (mac_b2accu_pd[8:0]) //|< w
,.cacc2sdp_valid (cacc2sdp_valid)
,.cacc2sdp_ready (cacc2sdp_ready)
,.cacc2sdp_pd (cacc2sdp_pd)
,.accu2sc_credit_vld (accu2sc_credit_vld)
,.accu2sc_credit_size (accu2sc_credit_size)
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync)
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync)
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
);
////////////////////////////////////////////////////////////////////////
// NVDLA Partition A: OBS //
////////////////////////////////////////////////////////////////////////
//&Instance NV_NVDLA_A_obs;
////////////////////////////////////////////////////////////////////////
// Dangles/Contenders report //
////////////////////////////////////////////////////////////////////////
//|
//|
//|
//|
endmodule // NV_NVDLA_partition_a |
module triangle_gen(MAX10_CLK1_50, KEY, VGA_R);
input MAX10_CLK1_50;
input [1:0] KEY;
output [3:0] VGA_R;
reg [9:0] clk_div_cnt;
reg [3:0] dac_cnt;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
assign VGA_R = dac_cnt;
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
clk_div_cnt <= 10'd0;
end else begin
clk_div_cnt <= clk_div_cnt + 1'b1;
end
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
dac_cnt <= 4'd0;
end else begin
if(&clk_div_cnt)
dac_cnt <= dac_cnt + 1'b1;
end
end
endmodule |
module testbench;
parameter PERIOD = 20;
reg i_clk, i_rst_n;
wire [3:0] o_dac;
triangle_gen gen_inst(.MAX10_CLK1_50 (i_clk),
.KEY ({i_rst_n, 1'b0}),
.VGA_R (o_dac)
);
initial begin
i_clk = 0;
forever #(PERIOD/2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@(negedge i_clk) i_rst_n = 1;
repeat (100000) @(negedge i_clk);
$finish;
end
endmodule |
module counter(MAX10_CLK1_50, KEY, LEDR);
input MAX10_CLK1_50;
input [1:0] KEY;
output [9:0] LEDR;
reg [9:0] cnt;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
assign LEDR = cnt;
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
cnt <= 10'd0;
end else begin
cnt <= cnt + 1'b1;
end
end
endmodule |
module testbench;
parameter PERIOD = 20;
reg i_clk, i_rst_n;
wire [9:0] o_cnt_dat;
counter cnt_inst(.MAX10_CLK1_50(i_clk),
.KEY ({i_rst_n, 1'b0}),
.LEDR (o_cnt_dat)
);
initial begin
i_clk = 0;
forever #(PERIOD/2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@(negedge i_clk) i_rst_n = 1;
repeat (2000) @(negedge i_clk);
$finish;
end
endmodule |
module nco(MAX10_CLK1_50, KEY, SW, VGA_R);
input MAX10_CLK1_50;
input [1:0] KEY;
input [9:0] SW;
output [3:0] VGA_R;
reg [3:0] sin_table_rom[1023:0];
reg [31:0] phase;
reg [3:0] dac_data;
reg [31:0] freq_step;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
assign VGA_R = dac_data;
initial $readmemh("sin_table_4bit.hex", sin_table_rom);
always @(posedge sys_clk)
dac_data <= sin_table_rom[phase[31:22]];
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
freq_step <= 0;
end else begin
freq_step <= {14'd0, SW, 8'd0}; //for simplicity here we dont use synchronization
end
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
phase <= 0;
end else begin
phase <= phase + freq_step;
end
end
endmodule |
module testbench;
parameter PERIOD = 20;
reg i_clk, i_rst_n;
reg [9:0] i_freq_step;
wire [3:0] o_dac;
nco nco_inst(.MAX10_CLK1_50 (i_clk),
.KEY ({i_rst_n, 1'b0}),
.SW (i_freq_step),
.VGA_R (o_dac)
);
initial begin
i_clk = 0;
forever #(PERIOD/2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
i_freq_step = 10'd64;
@(negedge i_clk) i_rst_n = 1'b1;
repeat (15) begin
repeat (500000) @(negedge i_clk);
i_freq_step = i_freq_step + 50;
end
$finish;
end
endmodule |
module sin_gen(MAX10_CLK1_50, KEY, VGA_R);
input MAX10_CLK1_50;
input [1:0] KEY;
output [3:0] VGA_R;
reg [3:0] sin_table_rom[1023:0];
reg [9:0] phase;
reg [3:0] dac_data;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
assign VGA_R = dac_data;
initial $readmemh("sin_table_4bit.hex", sin_table_rom);
always @(posedge sys_clk)
dac_data <= sin_table_rom[phase];
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
phase <= 0;
end else begin
phase <= phase + 1'b1;
end
end
endmodule |
module logic_elements(SW, LEDR);
input [9:0] SW;
output [9:0] LEDR;
wire [9:0] y;
wire [9:0] x;
assign LEDR = y;
assign x = SW;
assign y[0] = ~x[0];
assign y[1] = x[0] & x[1];
assign y[2] = ~(x[0] & x[1]);
assign y[3] = x[0] | x[1];
assign y[4] = ~(x[0] | x[1]);
assign y[5] = x[0] ^ x[1];
assign y[9:6] = 4'b1010;
endmodule |
module spi_7seg_controller(MAX10_CLK1_50,
GPIO,
KEY,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input MAX10_CLK1_50;
input [35:0] GPIO;
input [1:0] KEY;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
wire spi_sck = GPIO[0];
wire spi_cs = GPIO[1];
wire spi_mosi = GPIO[2];
wire sck_rs_edg;
wire tr_cmplt;
reg [7:0] spi_dat_ff;
reg [2:0] sck_sync_ff;
reg [2:0] cs_sync_ff;
reg [1:0] mosi_sync_ff;
reg ctrl_or_data_ff; // 0 -> waiting ctrl word (address, etc)
// 1 -> waiting data word
reg spi_recv_byte_ff;
reg [2:0] cnt_ff;
reg [2:0] addr_ff;
reg [6:0] digits[5:0];
assign HEX0 = digits[0];
assign HEX1 = digits[1];
assign HEX2 = digits[2];
assign HEX3 = digits[3];
assign HEX4 = digits[4];
assign HEX5 = digits[5];
/******************************************************************************
* SPI old part *
******************************************************************************/
assign sck_rs_edg = ~sck_sync_ff[2] & sck_sync_ff[1];
assign tr_cmplt = ~cs_sync_ff[2] & cs_sync_ff[1];
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n)
sck_sync_ff <= 3'b000;
else
sck_sync_ff <= {sck_sync_ff[1:0], spi_sck};
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n)
cs_sync_ff <= 3'b111;
else
cs_sync_ff <= {cs_sync_ff[1:0], spi_cs};
end
always @(posedge sys_clk)
mosi_sync_ff <= {mosi_sync_ff[0], spi_mosi};
always @(posedge sys_clk) begin
if (sck_rs_edg)
spi_dat_ff <= {spi_dat_ff[6:0], mosi_sync_ff[1]};
end
/******************************************************************************
* SPI new part *
******************************************************************************/
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n)
cnt_ff <= 3'd0;
else if (cs_sync_ff[2])
cnt_ff <= 3'd0;
else if (sck_rs_edg)
cnt_ff <= cnt_ff + 1'b1;
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n)
spi_recv_byte_ff <= 1'b0;
else if (sck_rs_edg & (3'd7 == cnt_ff) )
spi_recv_byte_ff <= 1'b1;
else
spi_recv_byte_ff <= 1'b0;
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n)
ctrl_or_data_ff <= 1'b0;
else if (cs_sync_ff[2])
ctrl_or_data_ff <= 1'b0;
else if (spi_recv_byte_ff & ~ctrl_or_data_ff )
ctrl_or_data_ff <= 1'b1;
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n)
addr_ff <= 3'd0;
else if (cs_sync_ff[2])
addr_ff <= 3'd0;
else if (spi_recv_byte_ff & ~ctrl_or_data_ff )
addr_ff <= spi_dat_ff[2:0];
else if (spi_recv_byte_ff)
addr_ff <= addr_ff + 1'b1;
end
always @(posedge sys_clk) begin
if (spi_recv_byte_ff & ctrl_or_data_ff)
digits[addr_ff] <= spi_dat_ff[6:0];
end
endmodule |
module dec_7seg(i_dat, o_seg);
input [3:0] i_dat;
output reg [6:0] o_seg;
always @* begin
case (i_dat)
4'h0: o_seg = 7'b1000000;
4'h1: o_seg = 7'b1111001;
4'h2: o_seg = 7'b0100100;
4'h3: o_seg = 7'b0110000;
4'h4: o_seg = 7'b0011001;
4'h5: o_seg = 7'b0010010;
4'h6: o_seg = 7'b0000010;
4'h7: o_seg = 7'b1111000;
4'h8: o_seg = 7'b0000000;
4'h9: o_seg = 7'b0011000;
4'hA: o_seg = 7'b0001000;
4'hB: o_seg = 7'b0000011;
4'hC: o_seg = 7'b1000110;
4'hD: o_seg = 7'b0100001;
4'hE: o_seg = 7'b0000110;
4'hF: o_seg = 7'b0001110;
endcase
end
endmodule |
module debouncer(i_clk, i_button, o_buttton);
parameter CNT_WIDTH = 16;
input i_clk;
input i_button;
output o_buttton;
reg but_sync1_ff = 1'b0;
reg but_sync2_ff = 1'b0;
reg [CNT_WIDTH-1:0] cnt = 0;
wire cnt_full = &cnt;
reg but_state;
wire but_new_state = but_sync2_ff;
wire but_state_dif = but_state ^ but_new_state;
assign o_buttton = but_state;
always @(posedge i_clk)
but_sync1_ff <= i_button;
always @(posedge i_clk)
but_sync2_ff <= but_sync1_ff;
always @(posedge i_clk)
if (cnt_full)
but_state <= ~but_state;
always @(posedge i_clk) begin
if (but_state_dif) begin
cnt <= cnt + 1'b1;
end else begin
cnt <= 0;
end
end
endmodule |
module shift_reg (KEY, SW, LEDR);
input [1:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
wire clk = KEY[0];
wire rst_n = KEY[1];
reg [9:0] shift_reg;
assign LEDR = shift_reg;
always @(posedge clk, negedge rst_n)
if (~rst_n) begin
shift_reg <= 0;
end else begin
shift_reg <= {shift_reg[8:0], SW[0]};
end
endmodule |
module lfsr10bit(KEY, SW, LEDR);
input [1:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
reg [9:0] lfsr;
wire clk = KEY[0];
wire rst_n = KEY[1];
wire lfsr_lsb = ~(lfsr[9] ^ lfsr[6]);
assign LEDR = lfsr;
always @(posedge clk, negedge rst_n) begin
if (~rst_n) begin
lfsr <= 0;
end else begin
lfsr <= {lfsr[8:0], lfsr_lsb};
end
end
endmodule |
module simple_spi(MAX10_CLK1_50, GPIO, KEY, LEDR);
input MAX10_CLK1_50;
input [35:0] GPIO;
input [1:0] KEY;
output [9:0] LEDR;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
wire spi_sck = GPIO[0];
wire spi_cs = GPIO[1];
wire spi_mosi = GPIO[2];
wire sck_rs_edg;
wire tr_cmplt;
reg [7:0] user_reg_ff;
reg [7:0] spi_dat_ff;
reg [2:0] sck_sync_ff;
reg [2:0] cs_sync_ff;
reg [1:0] mosi_sync_ff;
assign LEDR = user_reg_ff;
assign sck_rs_edg = ~sck_sync_ff[2] & sck_sync_ff[1];
assign tr_cmplt = ~cs_sync_ff[2] & cs_sync_ff[1];
// you should obligatorily implement reset on all control lines
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) begin
sck_sync_ff <= 3'b000;
end else begin
sck_sync_ff <= {sck_sync_ff[1:0], spi_sck};
end
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) begin
cs_sync_ff <= 3'b111;
end else begin
cs_sync_ff <= {cs_sync_ff[1:0], spi_cs};
end
end
// it is not necessary implement reset on data lines
// but you can do it if you want
always @(posedge sys_clk)
mosi_sync_ff <= {mosi_sync_ff[0], spi_mosi};
always @(posedge sys_clk) begin
if (sck_rs_edg)
spi_dat_ff <= {spi_dat_ff[6:0], mosi_sync_ff[1]};
end
always @(posedge sys_clk)
if (tr_cmplt)
user_reg_ff <= spi_dat_ff;
endmodule |
module dec_7seg_tb;
parameter DELAY = 20;
reg [3:0] bin_code;
wire [6:0] segments;
dec_7seg dec_7seg_inst(.i_dat (bin_code),
.o_seg (segments)
);
integer unsigned i;
initial begin
for (i = 0; i < 16; i = i + 1) begin
bin_code = i;
#DELAY;
end
$finish;
end
endmodule |
module dec_7seg_demo (SW, HEX0);
input [9:0] SW;
output [7:0] HEX0;
dec_7seg dec_7seg_inst(.i_dat (SW[3:0]),
.o_seg (HEX0)
);
endmodule |
module counter(i_clk, i_rst_n, i_srst, i_cnt_en, o_tick, o_data);
parameter MAX_VAL = 7;
parameter WIDTH = 4;
input i_clk;
input i_rst_n;
input i_srst;
input i_cnt_en;
output [WIDTH-1:0] o_data;
output reg o_tick;
reg [WIDTH-1:0] cnt;
wire cnt_overflow = ((MAX_VAL == cnt) & i_cnt_en);
assign o_data = cnt;
always @(posedge i_clk, negedge i_rst_n) begin
if(~i_rst_n) begin
o_tick <= 1'b0;
end else begin
if (cnt_overflow)
o_tick <= 1'b1;
else
o_tick <= 1'b0;
end
end
always @(posedge i_clk, negedge i_rst_n) begin
if(~i_rst_n) begin
cnt <= 0;
end else begin
if (cnt_overflow | i_srst)
cnt <= 0;
else if (i_cnt_en)
cnt <= cnt + 1'b1;
end
end
endmodule |
module clock(MAX10_CLK1_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5);
parameter DIV_CONST = 50_000_000;
input MAX10_CLK1_50;
input [1:0] KEY;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire [3:0] sec0, sec1, min0, min1, hour0, hour1;
wire sec0_to_sec1, sec1_to_min0, min0_to_min1, min1_to_hour0, hour0_to_hour1;
wire tick_1hz;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
wire clr_hrs = (8'h24 == {hour1, hour0});
// Creating 1 Hz reference signal
counter #(.MAX_VAL(DIV_CONST-1), .WIDTH(26) ) freq_div(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_srst (1'b0),
.i_cnt_en (1'b1),
.o_data (),
.o_tick (tick_1hz)
);
// Counters for secs, mins, hours
counter #(.MAX_VAL(9), .WIDTH(4) ) sec_0(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_srst (1'b0),
.i_cnt_en (tick_1hz),
.o_data (sec0),
.o_tick (sec0_to_sec1)
);
counter #(.MAX_VAL(5), .WIDTH(4) ) sec_1(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_srst (1'b0),
.i_cnt_en (sec0_to_sec1),
.o_data(sec1),
.o_tick (sec1_to_min0)
);
counter #(.MAX_VAL(9), .WIDTH(4) ) min_0(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_srst (1'b0),
.i_cnt_en (sec1_to_min0),
.o_data(min0),
.o_tick (min0_to_min1)
);
counter #(.MAX_VAL(5), .WIDTH(4) ) min_1(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_srst (1'b0),
.i_cnt_en (min0_to_min1),
.o_data(min1),
.o_tick (min1_to_hour0)
);
counter #(.MAX_VAL(9), .WIDTH(4) ) hour_0(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_srst (clr_hrs),
.i_cnt_en (min1_to_hour0),
.o_data(hour0),
.o_tick (hour0_to_hour1)
);
counter #(.MAX_VAL(5), .WIDTH(4) ) hour_1(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_srst (clr_hrs),
.i_cnt_en (hour0_to_hour1),
.o_data(hour1),
.o_tick ()
);
// Decoding secs, mins, hours from bin to 7-seg control signals
dec_7seg dec_sec_0(.i_dat (sec0),
.o_seg (HEX0)
);
dec_7seg dec_sec_1(.i_dat (sec1),
.o_seg (HEX1)
);
dec_7seg dec_min_0(.i_dat (min0),
.o_seg (HEX2)
);
dec_7seg dec_min_1(.i_dat (min1),
.o_seg (HEX3)
);
dec_7seg dec_hour_0(.i_dat (hour0),
.o_seg (HEX4)
);
dec_7seg dec_hour_1(.i_dat (hour1),
.o_seg (HEX5)
);
endmodule |
module clock_tb;
parameter PERIOD = 20;
parameter DELAY_CYCLES = 60*60*24*10;
reg i_clk;
reg i_rst_n;
wire [6:0] hex0, hex1, hex2, hex3, hex4, hex5;
clock #(.DIV_CONST(10) ) clock_inst(.MAX10_CLK1_50 (i_clk),
.KEY ({i_rst_n, 1'b0}),
.HEX0 (hex0),
.HEX1 (hex1),
.HEX2 (hex2),
.HEX3 (hex3),
.HEX4 (hex4),
.HEX5 (hex5)
);
initial begin
i_clk = 0;
forever #(PERIOD/2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@(negedge i_clk) i_rst_n = 1'b1;
repeat (DELAY_CYCLES) @(negedge i_clk);
$finish;
end
endmodule |
module const_div(i_clk, i_rst_n, o_clk);
input i_clk;
input i_rst_n;
output o_clk;
parameter DIV_BY = 7;
localparam N = $clog2(DIV_BY);
reg [N-1:0] cnt;
wire [N-1:0] cnt_max = (DIV_BY-1);
wire sync_rst_cnt = (cnt_max== cnt);
assign o_clk = sync_rst_cnt;
always @(posedge i_clk, negedge i_rst_n) begin
if(~i_rst_n) begin
cnt <= 0;
end else begin
if (sync_rst_cnt)
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
end
endmodule |
module dec_7seg_demo (MAX10_CLK1_50, KEY, HEX0);
input MAX10_CLK1_50;
input [1:0] KEY;
output [7:0] HEX0;
parameter DIV_CONST = 50_000_000;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
wire tick_event;
reg [3:0] cnt;
dec_7seg dec_7seg_inst(.i_dat (cnt),
.o_seg (HEX0)
);
const_div #(.DIV_BY(DIV_CONST)) div_inst(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.o_clk (tick_event)
);
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) begin
cnt <= 4'd0;
end else begin
if (tick_event)
cnt <= cnt + 1'b1;
end
end
endmodule |
module dec_7seg_demo_tb;
parameter PERIOD = 20;
parameter DELAY_CYCLES = 16*50_000_000;
reg i_clk;
reg i_rst_n;
wire [6:0] o_seg;
dec_7seg_demo dec_7seg_demo_inst(.MAX10_CLK1_50 (i_clk),
.KEY ({i_rst_n, 1'b0}),
.HEX0 (o_seg)
);
initial begin
i_clk = 0;
forever #(PERIOD/2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@(negedge i_clk) i_rst_n = 1'b1;
repeat (DELAY_CYCLES) @(negedge i_clk);
$finish;
end
endmodule |
module system_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
system_pll_0002 system_pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule |
module adc_ltc2308(i_clk, // max 40Mhz
i_rst_n,
i_measure_ch,
o_measure_done,
o_measure_data,
//adc interface
ADC_CONVST,
ADC_SCK,
ADC_SDI,
ADC_SDO
);
input i_clk;
input i_rst_n;
input [2:0] i_measure_ch;
output reg o_measure_done = 1'b0;
output reg [11:0] o_measure_data;
output reg ADC_CONVST = 1'b0;
output ADC_SCK;
output reg ADC_SDI;
input ADC_SDO;
/////////////////////////////////
// Timing definition
// using 40MHz clock
// to acheive fsample = 500KHz
// ntcyc = 2us / 25ns = 80
localparam DATA_BITS_NUM = 12;
localparam CMD_BITS_NUM = 6;
localparam CH_NUM = 8;
localparam tWHCONV = 3; // CONVST High Time, min 20 ns
localparam tCONV = 64; // tCONV: type 1.3 us, MAX 1.6 us, 1600/25(assumed clk is 40mhz)=64 -> 1.3us/25ns = 52
// set 64 for suite for 1.6 us max
localparam tHCONVST = 3;
localparam tCONVST_HIGH_START = 0;
localparam tCONVST_HIGH_END = tCONVST_HIGH_START+ tWHCONV;
localparam tCONFIG_START = tCONVST_HIGH_END;
localparam tCONFIG_END = tCLK_START+ CMD_BITS_NUM - 1;
localparam tCLK_START = tCONVST_HIGH_START + tCONV;
localparam tCLK_END = tCLK_START + DATA_BITS_NUM;
localparam tDONE = tCLK_END + tHCONVST;
localparam UNI_MODE = 1'b1; //1: Unipolar, 0:Bipolar
localparam SLP_MODE = 1'b0; //1: enable sleep
localparam SD = 1'b1; //1: single-ended, 0: differential
reg clk_enable = 1'b0;
reg [15:0] tick;
reg [DATA_BITS_NUM-1:0] read_data;
reg [3:0] write_pos;
wire [CMD_BITS_NUM-1:0] config_cmd = {SD, i_measure_ch, UNI_MODE, SLP_MODE};
wire config_init = (tick == tCONFIG_START);
wire config_enable = (tick > tCLK_START && tick <= tCONFIG_END);
wire config_done = (tick > tCONFIG_END);
reg [2:0] sdi_index;
assign ADC_SCK = clk_enable & i_clk;
always @ (posedge i_clk, negedge i_rst_n) begin
if (~i_rst_n)
tick <= 0;
else if (tick < tDONE)
tick <= tick + 1;
else
tick <= 0;
end
always @ (negedge i_clk, negedge i_rst_n) begin
if (~i_rst_n)
ADC_CONVST <= 1'b0;
else
ADC_CONVST <= ( tick >= tCONVST_HIGH_START && tick < tCONVST_HIGH_END );
end
always @ (negedge i_clk, negedge i_rst_n) begin
if (~i_rst_n)
clk_enable <= 1'b0;
else if ((tick >= tCLK_START && tick < tCLK_END))
clk_enable <= 1'b1;
else
clk_enable <= 1'b0;
end
always @ (negedge i_clk, negedge i_rst_n) begin // posedge??
if (~i_rst_n) begin
read_data <= 0;
write_pos <= DATA_BITS_NUM-1;
end else if (tick == 2) begin
read_data <= 0;
write_pos <= DATA_BITS_NUM-1;
end else if (clk_enable) begin
read_data[write_pos] <= ADC_SDO;
write_pos <= write_pos - 1;
end
end
always @ (posedge i_clk, negedge i_rst_n) begin
if (~i_rst_n) begin
o_measure_done <= 1'b0;
o_measure_data <= 0;
end else if (tick == tDONE) begin
o_measure_done <= 1'b1;
o_measure_data <= read_data;
end else
o_measure_done <= 1'b0;
end
always @(negedge i_clk) begin
if (config_init) begin
ADC_SDI <= config_cmd[CMD_BITS_NUM-1];
sdi_index <= CMD_BITS_NUM-2;
end else if (config_enable) begin
ADC_SDI <= config_cmd[sdi_index];
sdi_index <= sdi_index - 1;
end else if (config_done)
ADC_SDI <= 1'b0;
end
endmodule |
module adc_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [9:0] sub_wire3;
wire [11:0] q = sub_wire0[11:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
wire [9:0] wrusedw = sub_wire3[9:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.wrusedw (sub_wire3),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty ());
defparam
dcfifo_component.add_usedw_msb_bit = "ON",
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 12,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule |
module top(CLOCK_50, KEY, LEDR, ADC_CONVST, ADC_SCLK, ADC_DIN, ADC_DOUT, GPIO_0);
input CLOCK_50;
input [1:0] KEY;
output [9:0] LEDR;
output [35:0] GPIO_0;
output ADC_CONVST;
output ADC_SCLK;
input ADC_DOUT;
output ADC_DIN;
wire pll_locked;
wire sys_rst_n = KEY[1];
wire sys_clk; // 100 MHz
wire adc_clk; // 40 MHz
wire [11:0] fifo_in_data;
wire [11:0] fifo_out_data;
wire fifo_full;
wire fifo_empty;
wire fifo_write_req;
reg fifo_read_ack = 1'b0;
reg adc_data_valid = 1'b0;
reg [11:0] adc_data;
wire adc_measure_done;
reg adc_measure_done_ff = 1'b0;
reg [7:0] tick_cnt = 8'd0;
reg [3:0] pll_locked_ff = 4'b0000;
assign LEDR[0] = pll_locked;
assign GPIO_0[11:0] = adc_data;
assign GPIO_0[12] = adc_data_valid;
assign fifo_write_req = ~adc_measure_done_ff & adc_measure_done & ~fifo_full;
system_pll sys_pll ( .refclk (CLOCK_50),
.rst (~sys_rst_n),
.outclk_0 (sys_clk),
.outclk_1 (adc_clk),
.locked (pll_locked)
);
adc_ltc2308 adc (.i_clk (adc_clk),
.i_rst_n (pll_locked_ff[3]), // posedge triggle
.i_measure_ch (3'd0),
.o_measure_done (adc_measure_done),
.o_measure_data (fifo_in_data),
// adc interface
.ADC_CONVST (ADC_CONVST),
.ADC_SCK (ADC_SCLK),
.ADC_SDI (ADC_DIN),
.ADC_SDO (ADC_DOUT)
);
adc_fifo adc_fifo_inst( .aclr(~sys_rst_n),
.data (fifo_in_data),
.rdclk (sys_clk),
.rdreq (fifo_read_ack),
.wrclk (adc_clk),
.wrreq (fifo_write_req),
.q (fifo_out_data),
.rdempty (fifo_empty),
.wrfull (fifo_full)
);
always @(posedge adc_clk, negedge sys_rst_n)
if (~sys_rst_n)
adc_measure_done_ff <= 1'b0;
else
adc_measure_done_ff <= adc_measure_done;
always @(posedge adc_clk, negedge sys_rst_n)
if (~sys_rst_n)
pll_locked_ff <= 4'b0000;
else
pll_locked_ff <= {pll_locked_ff[2:0], pll_locked};
always @(posedge sys_clk, negedge sys_rst_n)
if (~sys_rst_n) begin
tick_cnt <= 8'd0;
fifo_read_ack <= 1'b0;
adc_data <= 12'd0;
adc_data_valid <= 1'b0;
end else begin
tick_cnt <= tick_cnt + 1'b1;
fifo_read_ack <= 1'b0;
adc_data_valid <= 1'b0;
if (8'd199 == tick_cnt) begin
tick_cnt <= 8'd0;
adc_data_valid <= ~fifo_empty;
fifo_read_ack <= ~fifo_empty;
adc_data <= fifo_out_data - 12'd2048;
end
end
endmodule |
module one_hot_div(MAX10_CLK1_50, KEY, GPIO);
input MAX10_CLK1_50;
input [1:0] KEY;
output [35:0] GPIO;
parameter N = 7;
reg [N-1:0] one_hot_cnt;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
assign GPIO[0] = one_hot_cnt[0];
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
one_hot_cnt <= 1;
end else begin
one_hot_cnt <= {one_hot_cnt[N-2:0], one_hot_cnt[N-1]};
end
end
endmodule |
module testbench;
parameter PERIOD = 20;
parameter DIV_BY = 7;
reg i_clk, i_rst_n;
wire o_clk;
wire [35:0] gpio;
one_hot_div #(.N(DIV_BY)) oh_div_inst(.MAX10_CLK1_50(i_clk),
.KEY ({i_rst_n, 1'b0}),
.GPIO (gpio)
);
assign o_clk = gpio[0];
initial begin
i_clk = 0;
forever #(PERIOD/2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@(negedge i_clk) i_rst_n = 1;
repeat (20) @(negedge i_clk);
$finish;
end
endmodule |
module testbench;
parameter PERIOD = 20;
parameter DIV_BY = 7;
wire [35:0] gpio;
wire o_clk;
reg i_clk, i_rst_n;
reg [9:0] i_div_by;
integer i = 0;
prog_div prog_div_inst(.MAX10_CLK1_50(i_clk),
.KEY ({i_rst_n, 1'b0}),
.SW (i_div_by),
.GPIO (gpio)
);
assign o_clk = gpio[0];
initial begin
i_clk = 0;
forever #(PERIOD/2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
i_div_by = 0;
@(negedge i_clk) i_rst_n = 1;
repeat(10) @(negedge i_clk);
for (i=1; i<1024; i=i+1) begin
i_div_by = i;
repeat(5*i) @(negedge i_clk);
end
$finish;
end
endmodule |
module prog_div(MAX10_CLK1_50, KEY, SW, GPIO);
input MAX10_CLK1_50;
input [1:0] KEY;
input [9:0] SW;
output [35:0] GPIO;
reg [9:0] cnt_ff;
reg [9:0] div_const_ff;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
wire preload_cnt = ~|cnt_ff;
assign GPIO[0] = preload_cnt;
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
div_const_ff <= 1;
end else begin
div_const_ff <= SW; //for simplicity here we don't use synchronization
end
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
cnt_ff <= 0;
end else begin
if (preload_cnt)
cnt_ff <= div_const_ff;
else
cnt_ff <= cnt_ff - 1'b1;
end
end
endmodule |
module simple_uart_receiver(i_clk, i_rst_n, i_rx, o_dat, o_dat_vld);
input i_clk;
input i_rst_n;
input i_rx;
output reg o_dat_vld;
output [7:0] o_dat;
parameter RCONST = 1085; //230400bps for 250MHz i_clk
reg [10:0] baud_rate_cnt;
reg [3:0] bit_cnt;
reg [7:0] shift_reg;
reg [1:0] rx_sync;
reg [7:0] data_reg;
assign o_dat = data_reg;
always @(posedge i_clk)
if ( (9 == bit_cnt) && (RCONST/2 == baud_rate_cnt) ) begin
data_reg <= shift_reg;
o_dat_vld <= 1'b1;
end else begin
o_dat_vld <= 1'b0;
end
always @(posedge i_clk)
rx_sync <= {rx_sync[0], i_rx};
always @(posedge i_clk)
if( RCONST/2 == baud_rate_cnt )
shift_reg <= {rx_sync[1], shift_reg[7:1]};
always @(posedge i_clk, negedge i_rst_n)
if (~i_rst_n) begin
baud_rate_cnt <= 0;
end else begin
if ( (RCONST == baud_rate_cnt) || (10 == bit_cnt) )
baud_rate_cnt <= 0;
else
baud_rate_cnt <= baud_rate_cnt + 1'b1;
end
always @(posedge i_clk, negedge i_rst_n)
if (~i_rst_n) begin
bit_cnt <= 0;
end else begin
if ( (10 == bit_cnt) && (1'b0 == rx_sync[1]) )
bit_cnt <= 0;
else if (RCONST == baud_rate_cnt)
bit_cnt <= bit_cnt + 1'b1;
end
endmodule |
module fm_transmitter(MAX10_CLK1_50, GPIO, KEY, LEDR);
input MAX10_CLK1_50;
inout [35:0] GPIO;
input [1:0] KEY;
output [9:0] LEDR;
parameter NCO_PHASE_STEP_CARRIER = 32'h5C28_F5C2; // 90 MHz FM carrier, 250 MHz sys_clk
wire sys_rst_n = KEY[0];
wire sys_clk;
wire [7:0] uart_dat;
reg [7:0] sample;
reg [31:0] nco_phase;
reg [31:0] nco_phase_step;
wire [31:0] nco_phase_step_carrier = NCO_PHASE_STEP_CARRIER;
wire [31:0] nco_phase_step_deviation = { {(32-8-13){sample[7]}}, sample, 13'b0 };
mypll pll_inst(.inclk0 (MAX10_CLK1_50),
.c0 (sys_clk), // 250 MHz clock
.locked (LEDR[0])
);
simple_uart_receiver uart_rec(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_rx (GPIO[0]),
.o_dat (uart_dat),
.o_dat_vld ()
);
always @(posedge sys_clk)
sample <= uart_dat - 128;
always @(posedge sys_clk)
nco_phase_step <= nco_phase_step_carrier + nco_phase_step_deviation;
always @(posedge sys_clk)
nco_phase <= nco_phase + nco_phase_step;
assign GPIO[35] = nco_phase[31];
endmodule |
module mypll (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 5,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=mypll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule |
module const_div(MAX10_CLK1_50, KEY, GPIO);
input MAX10_CLK1_50;
input [1:0] KEY;
output [35:0] GPIO;
parameter DIV_BY = 7;
localparam N = $clog2(DIV_BY);
reg [N-1:0] cnt;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
wire sync_rst_cnt = (DIV_BY-1) == cnt;
assign GPIO[0] = sync_rst_cnt;
always @(posedge sys_clk, negedge sys_rst_n) begin
if(~sys_rst_n) begin
cnt <= 0;
end else begin
if (sync_rst_cnt)
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
end
endmodule |
module testbench;
parameter PERIOD = 20;
parameter DIV_BY = 7;
reg i_clk, i_rst_n;
wire o_clk;
wire [35:0] gpio;
const_div #(.DIV_BY(DIV_BY)) const_div_inst(.MAX10_CLK1_50(i_clk),
.KEY ({i_rst_n, 1'b0}),
.GPIO (gpio)
);
assign o_clk = gpio[0];
initial begin
i_clk = 0;
forever #(PERIOD/2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@(negedge i_clk) i_rst_n = 1;
repeat (30) @(negedge i_clk);
$finish;
end
endmodule |
module simple_pwm (MAX10_CLK1_50, KEY, SW, GPIO);
input MAX10_CLK1_50;
input [1:0] KEY;
input [9:0] SW;
inout [35:0] GPIO;
wire sys_clk = MAX10_CLK1_50;
reg [9:0] cnt_ff = 0;
reg [9:0] dc_ff = 0;
reg out_ff = 1'b1;
reg en_ff = 1'b1;
always @(posedge sys_clk) begin
en_ff <= KEY[0];
dc_ff <= SW;
end
always @(posedge sys_clk)
if(en_ff)
cnt_ff <= cnt_ff + 1'b1;
always @(posedge sys_clk)
out_ff <= (cnt_ff < dc_ff);
assign GPIO[0] = out_ff;
endmodule |
module audio_pcm_pwm (MAX10_CLK1_50, GPIO, KEY, LEDR);
input MAX10_CLK1_50;
inout [35:0] GPIO;
input [1:0] KEY;
output [9:0] LEDR;
wire sys_clk;
wire sys_rst_n = KEY[0];
reg pwm_out_ff;
reg [7:0] pwm_cnt_ff;
reg [7:0] pcm_sample_ff;
wire [7:0] uart_dat;
mypll pll_inst(.inclk0 (MAX10_CLK1_50),
.c0 (sys_clk), // 255 MHz clock
.locked (LEDR[0])
);
simple_uart_receiver uart_rec(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_rx (GPIO[0]),
.o_dat (uart_dat),
.o_dat_vld ()
);
always @(posedge sys_clk)
pcm_sample_ff <= uart_dat;
always @(posedge sys_clk)
pwm_cnt_ff <= pwm_cnt_ff + 1'b1;
always @(posedge sys_clk)
pwm_out_ff <= (pwm_cnt_ff < pcm_sample_ff);
assign GPIO[35] = pwm_out_ff;
endmodule |
module pwm_am_transmitter (MAX10_CLK1_50, GPIO, KEY, LEDR);
input MAX10_CLK1_50;
inout [35:0] GPIO;
input [1:0] KEY;
output [9:0] LEDR;
wire [7:0] uart_dat;
reg [9:0] pcm_sample_ff;
reg pwm_out_ff;
reg [9:0] pwm_cnt_ff;
wire sys_rst_n = KEY[0];
wire sys_clk;
mypll pll_inst(.inclk0 (MAX10_CLK1_50),
.c0 (sys_clk), // 250 MHz clock
.locked (LEDR[0])
);
simple_uart_receiver uart_rec(.i_clk (sys_clk),
.i_rst_n (sys_rst_n),
.i_rx (GPIO[0]),
.o_dat (uart_dat),
.o_dat_vld ()
);
always @(posedge sys_clk)
pcm_sample_ff <= {uart_dat, 1'b0};
always @(posedge sys_clk)
pwm_cnt_ff <= pwm_cnt_ff + 1'b1;
always @(posedge sys_clk)
pwm_out_ff <= (pwm_cnt_ff < pcm_sample_ff);
assign GPIO[35] = pwm_out_ff;
endmodule |
module pwm_control_period (i_clk, i_period, i_duty_cyle, o_pwm);
parameter PWM_WIDTH = 10;
input i_clk;
input [PWM_WIDTH-1:0] i_period; // max val for pwm counter
input [PWM_WIDTH-1:0] i_duty_cyle; // i_duty_cyle should be less or equal then i_period
output o_pwm;
reg [PWM_WIDTH-1:0] cnt_ff = 0;
reg [PWM_WIDTH-1:0] duty_cyle_ff = 0;
reg [PWM_WIDTH-1:0] period_ff = 0;
reg out_ff = 1'b0;
always @(posedge i_clk) begin
period_ff <= i_period;
duty_cyle_ff <= i_duty_cyle;
end
always @(posedge i_clk)
if(cnt_ff == period_ff)
cnt_ff <= 0;
else
cnt_ff <= cnt_ff + 1'b1;
always @(posedge i_clk)
out_ff <= (cnt_ff < duty_cyle_ff);
assign o_pwm = out_ff;
endmodule |
module testbench;
parameter PERIOD = 20;
parameter PWM_WIDTH = 10;
wire o_pwm;
reg i_clk;
reg [PWM_WIDTH-1:0] i_period; // max val for pwm counter
reg [PWM_WIDTH-1:0] i_duty_cyle; // i_duty_cyle should be less or equal then i_period
integer i = 0;
integer j = 0;
pwm_control_period #(.PWM_WIDTH(PWM_WIDTH)) pwm_inst(.i_clk (i_clk),
.i_period (i_period),
.i_duty_cyle (i_duty_cyle),
.o_pwm (o_pwm)
);
initial begin
i_clk = 0;
forever #(PERIOD/2) i_clk = ~i_clk;
end
initial begin
i_duty_cyle = 0;
i_period = 0;
repeat(10) @(negedge i_clk);
for (j=PWM_WIDTH/2; j<=PWM_WIDTH; j=j+1) begin
i_period = (1'b1<<j) - 1'b1;
@(negedge i_clk);
for (i=0; i<=i_period; i=i+1) begin
i_duty_cyle = i;
repeat (5*(i_period + 1)) @(negedge i_clk);
end
end
$finish;
end
endmodule |
module priority_encoder_DE10_Lite (SW, HEX0, LEDR);
input [9:0] SW;
output [9:0] LEDR;
output [6:0] HEX0;
wire [2:0] bin;
priority_encoder #(.ONEHOT_WIDTH(8)) enc_inst(.i_one_hot (SW[7:0]),
.o_bin (bin),
.o_active (LEDR[0])
);
dec_7seg ind_hex0(.i_dat ({1'b0, bin}),
.o_seg (HEX0)
);
endmodule |
module testbench;
parameter DELAY = 20;
reg [15:0] one_hot;
wire [3:0] bin;
wire active;
priority_encoder #(.ONEHOT_WIDTH(16)) enc_inst(.i_one_hot (one_hot),
.o_bin (bin),
.o_active (active)
);
initial begin
one_hot = 16'b0;
#DELAY;
one_hot = 16'b1;
repeat (15) begin
#DELAY;
one_hot = one_hot << 1;
end
repeat (100) begin
#DELAY;
one_hot = $random;
end
$finish;
end
endmodule |
module priority_encoder (i_one_hot, o_bin, o_active);
parameter ONEHOT_WIDTH = 16;
parameter BIN_WIDTH = $clog2(ONEHOT_WIDTH);
input [ONEHOT_WIDTH-1:0] i_one_hot;
output reg [BIN_WIDTH-1:0] o_bin;
output o_active;
integer i = 0;
assign o_active = |i_one_hot;
always @* begin
o_bin = 0;
for (i=0; i<ONEHOT_WIDTH; i=i+1)
if (i_one_hot[i])
o_bin = i;
end
endmodule |
module barrel_shifter_right (i_data, i_sa, i_st, o_data);
parameter DATA_WIDTH = 10;
parameter SA_WIDTH = $clog2(DATA_WIDTH);
input i_st; // st - shift type (0:logical 1:arithmetic)
input [DATA_WIDTH-1:0] i_data;
input [SA_WIDTH-1:0] i_sa; // sa -shift amount
output [DATA_WIDTH-1:0] o_data;
reg [DATA_WIDTH-1:0] shift_result;
always @* begin
shift_result = $signed({ (i_st & i_data[DATA_WIDTH-1]) , i_data}) >>> i_sa;
end
assign o_data = shift_result;
endmodule |
module barrel_shifter_DE10_Lite (KEY, SW, LEDR);
input [1:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
barrel_shifter_right #(.DATA_WIDTH (8)) bsr_inst(.i_data (SW[7:0]),
.i_sa ({~KEY[0], SW[9:8]}),
.i_st (KEY[1]),
.o_data (LEDR[7:0])
);
endmodule |
module testbench;
parameter DATA_WIDTH = 16;
parameter SA_WIDTH = $clog2(DATA_WIDTH);
parameter DELAY = 20;
parameter N = 10_000;
reg i_st; // st - shift type (0:logical 1:arithmetic)
reg [DATA_WIDTH-1:0] i_data;
reg [SA_WIDTH-1:0] i_sa; // sa -shift amount
wire [DATA_WIDTH-1:0] o_data;
barrel_shifter_right #(.DATA_WIDTH (DATA_WIDTH)) bsr_inst(.i_data (i_data),
.i_sa (i_sa),
.i_st (i_st),
.o_data (o_data)
);
initial begin
repeat (N) begin
i_st = $random;
i_sa = $random;
i_data = $random;
#DELAY;
end
$finish;
end
endmodule |
module testbench;
parameter DELAY = 20;
reg [7:0] one_hot;
wire [2:0] bin;
wire active;
enc8in enc_inst(.i_one_hot (one_hot),
.o_bin (bin),
.o_active (active)
);
initial begin
one_hot = 8'b0;
#DELAY;
one_hot = 8'b1;
repeat (7) begin
#DELAY;
one_hot = one_hot << 1;
end
repeat (30) begin
#DELAY;
one_hot = $random;
end
$finish;
end
endmodule |
module enc8in (i_one_hot, o_bin, o_active);
input [7:0] i_one_hot;
output reg [2:0] o_bin;
output reg o_active;
always @* begin
o_bin[0] = i_one_hot[1] | i_one_hot[3] | i_one_hot[5] | i_one_hot[7];
o_bin[1] = i_one_hot[2] | i_one_hot[3] | i_one_hot[6] | i_one_hot[7];
o_bin[2] = i_one_hot[4] | i_one_hot[5] | i_one_hot[6] | i_one_hot[7];
o_active = |i_one_hot;
end
endmodule |
module encoder_DE10_Lite (SW, HEX0, LEDR);
input [9:0] SW;
output [9:0] LEDR;
output [6:0] HEX0;
wire [2:0] bin;
enc8in enc_inst(.i_one_hot (SW[7:0]),
.o_bin (bin),
.o_active (LEDR[0])
);
dec_7seg ind_hex0(.i_dat ({1'b0, bin}),
.o_seg (HEX0)
);
endmodule |
module barrel_shifter_right (i_data, i_sa, i_st, o_data);
input i_st; // st - shift type (0:logical 1:arithmetic)
input [7:0] i_data;
input [2:0] i_sa; // sa -shift amount
output [7:0] o_data;
wire [7:0] mux0_to_mux1;
wire [7:0] mux1_to_mux2;
mux_2in1_type2 #(.WIDTH(8)) mux0(.i_dat0 (i_data),
.i_dat1 ({i_st & i_data[7], i_data[7:1]}),
.i_sel (i_sa[0]),
.o_dat (mux0_to_mux1)
);
mux_2in1_type2 #(.WIDTH(8)) mux1(.i_dat0 (mux0_to_mux1),
.i_dat1 ({ {2{i_st & mux0_to_mux1[7]}}, mux0_to_mux1[7:2]}),
.i_sel (i_sa[1]),
.o_dat (mux1_to_mux2)
);
mux_2in1_type2 #(.WIDTH(8)) mux2(.i_dat0 (mux1_to_mux2),
.i_dat1 ({ {4{i_st & mux1_to_mux2[7]}}, mux1_to_mux2[7:4]}),
.i_sel (i_sa[2]),
.o_dat (o_data)
);
endmodule |
module mux_2in1_type2 (i_dat0, i_dat1, i_sel, o_dat);
parameter WIDTH = 8;
input i_sel;
input [WIDTH-1:0] i_dat0;
input [WIDTH-1:0] i_dat1;
output reg [WIDTH-1:0] o_dat;
always @* begin
if (i_sel)
o_dat = i_dat1;
else
o_dat = i_dat0;
end
endmodule |
module testbench;
parameter DELAY = 20;
parameter N = 10_000;
reg i_st; // st - shift type (0:logical 1:arithmetic)
reg [7:0] i_data;
reg [2:0] i_sa; // sa -shift amount
wire [7:0] o_data;
barrel_shifter_right bsr_inst(.i_data (i_data),
.i_sa (i_sa),
.i_st (i_st),
.o_data (o_data)
);
initial begin
repeat (N) begin
i_st = $random;
i_sa = $random;
i_data = $random;
#DELAY;
end
$finish;
end
endmodule |
module mux_2in1_type1 (i_dat0, i_dat1, i_sel, o_dat);
parameter WIDTH = 8;
input i_sel;
input [WIDTH-1:0] i_dat0;
input [WIDTH-1:0] i_dat1;
output [WIDTH-1:0] o_dat;
assign o_dat = i_sel ? i_dat1 : i_dat0;
endmodule |
module bin8_to_bcd_DE10_Lite (SW, HEX0, HEX1, HEX2);
input [9:0] SW;
output [6:0] HEX0, HEX1, HEX2;
wire [11:0] bcd;
bin8_to_bcd bin2bcd_inst (.i_bin (SW[7:0]),
.o_bcd (bcd)
);
dec_7seg bcd0(.i_dat (bcd[3:0]),
.o_seg (HEX0)
);
dec_7seg bcd1(.i_dat (bcd[7:4]),
.o_seg (HEX1)
);
dec_7seg bcd2(.i_dat (bcd[11:8]),
.o_seg (HEX2)
);
endmodule |
module testbench;
parameter DELAY = 20;
reg [7:0] bin;
wire [11:0] bcd;
integer i;
bin8_to_bcd bin2bcd_inst (.i_bin (bin),
.o_bcd (bcd)
);
initial begin
for (i=0; i<256; i=i+1) begin
bin = i;
#DELAY;
end
$finish;
end
endmodule |
module bin8_to_bcd (i_bin, o_bcd);
input [7:0] i_bin;
output reg [11:0] o_bcd;
integer i;
always @* begin
o_bcd = 0;
for (i = 0; i < 8; i = i+1) begin
o_bcd = {o_bcd[10:0], i_bin[7-i]};
if(i < 7 && o_bcd[3:0] > 4)
o_bcd[3:0] = o_bcd[3:0] + 3;
if(i < 7 && o_bcd[7:4] > 4)
o_bcd[7:4] = o_bcd[7:4] + 3;
if(i < 7 && o_bcd[11:8] > 4)
o_bcd[11:8] = o_bcd[11:8] + 3;
end
end
endmodule |
module enc_param (i_one_hot, o_bin, o_active);
parameter ONEHOT_WIDTH = 16;
parameter BIN_WIDTH = $clog2(ONEHOT_WIDTH);
input [ONEHOT_WIDTH-1:0] i_one_hot;
output [BIN_WIDTH-1:0] o_bin;
output o_active;
genvar i,j;
assign o_active = |i_one_hot;
generate
for (j=0; j<BIN_WIDTH; j=j+1)
begin : jl
wire [ONEHOT_WIDTH-1:0] tmp_mask;
for (i=0; i<ONEHOT_WIDTH; i=i+1)
begin : il
assign tmp_mask[i] = i[j];
end
assign o_bin[j] = |(tmp_mask & i_one_hot);
end
endgenerate
endmodule |
module encoder_DE10_Lite (SW, HEX0, LEDR);
input [9:0] SW;
output [9:0] LEDR;
output [6:0] HEX0;
wire [2:0] bin;
enc_param #(.ONEHOT_WIDTH(8)) enc_inst(.i_one_hot (SW[7:0]),
.o_bin (bin),
.o_active (LEDR[0])
);
dec_7seg ind_hex0(.i_dat ({1'b0, bin}),
.o_seg (HEX0)
);
endmodule |
module testbench;
parameter DELAY = 20;
parameter DEC_OUT_NUM = 17;
reg [$clog2(DEC_OUT_NUM)-1:0] bin;
wire [DEC_OUT_NUM-1:0] one_hot;
integer i;
decoder #(.ONE_HOT_WIDTH(DEC_OUT_NUM)) dec_inst(.i_bin (bin),
.o_one_hot (one_hot)
);
initial begin
for (i=0; i<DEC_OUT_NUM; i=i+1) begin
bin = i;
#DELAY;
end
$finish;
end
endmodule |
module decoder (i_bin, o_one_hot);
parameter ONE_HOT_WIDTH = 8;
parameter BIN_WIDTH = $clog2(ONE_HOT_WIDTH);
input [BIN_WIDTH-1:0] i_bin;
output reg [ONE_HOT_WIDTH-1:0] o_one_hot;
always @* begin
o_one_hot = 0;
o_one_hot[i_bin] = 1'b1;
end
endmodule |
module decoder_DE10_Lite (SW, LEDR);
input [9:0] SW;
output [9:0] LEDR;
decoder #(.ONE_HOT_WIDTH(10)) dec_inst(.i_bin (SW[3:0]),
.o_one_hot (LEDR)
);
endmodule |
module testbench;
parameter DELAY = 20;
parameter WIDTH = 8;
reg [WIDTH-1:0] i_dat0, i_dat1, i_dat2, i_dat3, i_dat4;
reg [2:0] i_sel;
wire [WIDTH-1:0] o_dat;
integer i;
mux_5in1 #(.WIDTH(WIDTH)) mux_inst(.i_dat0 (i_dat0),
.i_dat1 (i_dat1),
.i_dat2 (i_dat2),
.i_dat3 (i_dat3),
.i_dat4 (i_dat4),
.i_sel (i_sel),
.o_dat (o_dat)
);
initial begin
for (i=0; i<8; i=i+1) begin
i_sel = i;
repeat (10) begin
i_dat0 = $random;
i_dat1 = $random;
i_dat2 = $random;
i_dat3 = $random;
i_dat4 = $random;
#DELAY;
end
end
$finish;
end
endmodule |
module mux_5in1 (i_dat0, i_dat1, i_dat2, i_dat3, i_dat4, i_sel, o_dat);
parameter WIDTH = 8;
input [2:0] i_sel;
input [WIDTH-1:0] i_dat0, i_dat1, i_dat2, i_dat3, i_dat4;
output reg [WIDTH-1:0] o_dat;
always @* begin
o_dat = 0;
case (i_sel)
3'd0: o_dat = i_dat0;
3'd1: o_dat = i_dat1;
3'd2: o_dat = i_dat2;
3'd3: o_dat = i_dat3;
3'd4: o_dat = i_dat4;
endcase
end
endmodule |
module test_bench(
);
reg rst;
reg clk;
wire [7:0] ans;
wire [6:0] seg;
wire [9:0] led;
initial
begin
clk = 1'b0;
rst = 1'b1;
#500;
rst = 1'b0;
end
always #10 clk = ~clk;
top top(
.hclk(clk),
.rst(rst),
.seg(seg),
.ans(ans),
.led(led)
);
endmodule |
module testbench();
reg clk;
reg rst;
wire[31:0] writedata,dataadr;
wire memwrite;
top dut(clk,rst,writedata,dataadr,memwrite);
initial begin
rst <= 1;
#200;
rst <= 0;
end
always begin
clk <= 1;
#10;
clk <= 0;
#10;
end
always @(negedge clk) begin
if(memwrite) begin
/* code */
if(dataadr === 84 & writedata === 7) begin
/* code */
$display("Simulation succeeded");
$stop;
end else if(dataadr !== 80) begin
/* code */
$display("Simulation Failed");
$stop;
end
end
end
endmodule |
module Rom(
input [15:0] ins,
input clk,
input reset,
output [6:0] seg,
output [7:0] ans
);
wire [31:0] InsData;
Ins_ROM Ins_Rom(.clka(clk), // input wire clka
.addra({{16{ins[15]}},ins[15:0]}), // input wire [15 : 0] addra
.douta(InsData[31:0]) // output wire [31 : 0] douta
);
display display_0(.clk(clk),.reset(reset),.s(InsData),.ans(ans),.seg(seg));
endmodule |
module seg7(
input wire [3:0]din,
output reg [6:0]dout
);
always@(*)
case(din)
5'h0:dout = 7'b000_0001;
5'h1:dout = 7'b100_1111;
5'h2:dout = 7'b001_0010;
5'h3:dout = 7'b000_0110;
5'h4:dout = 7'b100_1100;
5'h5:dout = 7'b010_0100;
5'h6:dout = 7'b010_0000;
5'h7:dout = 7'b000_1111;
5'h8:dout = 7'b000_0000;
5'h9:dout = 7'b000_0100;
5'ha:dout = 7'b000_1000;
5'hb:dout = 7'b110_0000;
5'hc:dout = 7'b011_0001;
5'hd:dout = 7'b100_0010;
5'he:dout = 7'b011_0000;
5'hf:dout = 7'b011_1000;
default:dout = 7'b111_1111;
endcase
endmodule |
module display(
input wire clk,reset,
input wire [31:0]s,
output wire [6:0]seg,
output reg [7:0]ans
);
reg [20:0]count;
reg [4:0]digit;
always@(posedge clk,posedge reset)
if(reset)
count = 0;
else
count = count + 1;
always @(posedge clk)
case(count[20:18])
0:begin
ans = 8'b11111110;
digit = s[3:0];
end
1:begin
ans = 8'b11111101;
digit = s[7:4];
end
2:begin
ans = 8'b11111011;
digit =s[11:8];
end
3:begin
ans = 8'b11110111;
digit = s[15:12];
end
4:begin
ans = 8'b11101111;
digit = s[19:16];
end
5:begin
ans = 8'b11011111;
digit = s[23:20];
end
6:begin
ans = 8'b10111111;
digit =s[27:24];
end
7:begin
ans = 8'b01111111;
digit = s[31:28];
end
endcase
seg7 U4(.din(digit),.dout(seg));
endmodule |
module adder(
input wire[31:0] a,b,
output wire[31:0] y
);
assign y = a + b;
endmodule |
module floprc #(parameter WIDTH = 8)(
input wire clk,rst,clear,
input wire[WIDTH-1:0] d,
output reg[WIDTH-1:0] q
);
always @(posedge clk,posedge rst) begin
if(rst) begin
q <= 0;
end else if (clear)begin
q <= 0;
end else begin
q <= d;
end
end
endmodule |
module mux2 #(parameter WIDTH = 8)(
input wire[WIDTH-1:0] d0,d1,
input wire s,
output wire[WIDTH-1:0] y
);
assign y = s ? d1 : d0;
endmodule |
module signext(
input wire[15:0] a,
output wire[31:0] y
);
assign y = {{16{a[15]}},a};
endmodule |
module flopenr #(parameter WIDTH = 8)(
input wire clk,rst,en,
input wire[WIDTH-1:0] d,
output reg[WIDTH-1:0] q
);
always @(posedge clk) begin
if(rst) begin
q <= 0;
end else if(en) begin
/* code */
q <= d;
end
end
endmodule |
module controller(
input wire clk,rst,
//decode stage
input wire[5:0] opD,functD,
output wire pcsrcD,branchD,equalD,jumpD,
//execute stage
input wire flushE,
output wire memtoregE,alusrcE,
output wire regdstE,regwriteE,
output wire[2:0] alucontrolE,
//mem stage
output wire memtoregM,memwriteM,
regwriteM,
//write back stage
output wire memtoregW,regwriteW
);
//decode stage
wire[1:0] aluopD;
wire memtoregD,memwriteD,alusrcD,
regdstD,regwriteD;
wire[2:0] alucontrolD;
//execute stage
wire memwriteE;
maindec md(
opD,
memtoregD,memwriteD,
branchD,alusrcD,
regdstD,regwriteD,
jumpD,
aluopD
);
aludec ad(functD,aluopD,alucontrolD);
assign pcsrcD = branchD & equalD;
//pipeline registers
floprc #(8) regE(
clk,
rst,
flushE,
{memtoregD,memwriteD,alusrcD,regdstD,regwriteD,alucontrolD},
{memtoregE,memwriteE,alusrcE,regdstE,regwriteE,alucontrolE}
);
flopr #(8) regM(
clk,rst,
{memtoregE,memwriteE,regwriteE},
{memtoregM,memwriteM,regwriteM}
);
flopr #(8) regW(
clk,rst,
{memtoregM,regwriteM},
{memtoregW,regwriteW}
);
endmodule |
module aludec(
input wire[5:0] funct,
input wire[1:0] aluop,
output reg[2:0] alucontrol
);
always @(*) begin
case (aluop)
2'b00: alucontrol <= 3'b010;//add (for lw/sw/addi)
2'b01: alucontrol <= 3'b110;//sub (for beq)
default : case (funct)
6'b100000:alucontrol <= 3'b010; //add
6'b100010:alucontrol <= 3'b110; //sub
6'b100100:alucontrol <= 3'b000; //and
6'b100101:alucontrol <= 3'b001; //or
6'b101010:alucontrol <= 3'b111; //slt
default: alucontrol <= 3'b000;
endcase
endcase
end
endmodule |
module sl2(
input wire[31:0] a,
output wire[31:0] y
);
assign y = {a[29:0],2'b00};
endmodule |
module pc #(parameter WIDTH = 8)(
input wire clk,rst,en,
input wire[WIDTH-1:0] d,
output reg[WIDTH-1:0] q
);
always @(posedge clk,posedge rst) begin
if(rst) begin
q <= 0;
end else if(en) begin
/* code */
q <= d;
end
end
endmodule |
module mux3 #(parameter WIDTH = 8)(
input wire[WIDTH-1:0] d0,d1,d2,
input wire[1:0] s,
output wire[WIDTH-1:0] y
);
assign y = (s == 2'b00) ? d0 :
(s == 2'b01) ? d1:
(s == 2'b10) ? d2: d0;
endmodule |
module eqcmp(
input wire [31:0] a,b,
output wire y
);
assign y = (a == b) ? 1 : 0;
endmodule |
module maindec(
input wire[5:0] op,
output wire memtoreg,memwrite,
output wire branch,alusrc,
output wire regdst,regwrite,
output wire jump,
output wire[1:0] aluop
);
reg[8:0] controls;
assign {regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump,aluop} = controls;
always @(*) begin
case (op)
6'b000000:controls <= 9'b110000010;//R-TYRE
6'b100011:controls <= 9'b101001000;//LW
6'b101011:controls <= 9'b001010000;//SW
6'b000100:controls <= 9'b000100001;//BEQ
6'b001000:controls <= 9'b101000000;//ADDI
6'b000010:controls <= 9'b000000100;//J
default: controls <= 9'b000000000;//illegal op
endcase
end
endmodule |
module hazard(
//fetch stage
output wire stallF,
//decode stage
input wire[4:0] rsD,rtD,
input wire branchD,
output wire forwardaD,forwardbD,
output wire stallD,
//execute stage
input wire[4:0] rsE,rtE,
input wire[4:0] writeregE,
input wire regwriteE,
input wire memtoregE,
output reg[1:0] forwardaE,forwardbE,
output wire flushE,
//mem stage
input wire[4:0] writeregM,
input wire regwriteM,
input wire memtoregM,
//write back stage
input wire[4:0] writeregW,
input wire regwriteW
);
wire lwstallD,branchstallD;
//forwarding sources to D stage (branch equality)
assign forwardaD = (rsD != 0 & rsD == writeregM & regwriteM);
assign forwardbD = (rtD != 0 & rtD == writeregM & regwriteM);
//forwarding sources to E stage (ALU)
always @(*) begin
forwardaE = 2'b00;
forwardbE = 2'b00;
if(rsE != 0) begin
/* code */
if(rsE == writeregM & regwriteM) begin
/* code */
forwardaE = 2'b10;
end else if(rsE == writeregW & regwriteW) begin
/* code */
forwardaE = 2'b01;
end
end
if(rtE != 0) begin
/* code */
if(rtE == writeregM & regwriteM) begin
/* code */
forwardbE = 2'b10;
end else if(rtE == writeregW & regwriteW) begin
/* code */
forwardbE = 2'b01;
end
end
end
//stalls
assign #1 lwstallD = memtoregE & (rtE == rsD | rtE == rtD);
assign #1 branchstallD = branchD &
(regwriteE &
(writeregE == rsD | writeregE == rtD) |
memtoregM &
(writeregM == rsD | writeregM == rtD));
assign #1 stallD = lwstallD | branchstallD;
assign #1 stallF = stallD;
//stalling D stalls all previous stages
assign #1 flushE = stallD;
//stalling D flushes next stage
// Note: not necessary to stall D stage on store
// if source comes from load;
// instead, another bypass network could
// be added from W to M
endmodule |
module mips(
input wire clk,rst,
output wire[31:0] pcF,
input wire[31:0] instrF,
output wire memwriteM,
output wire[31:0] aluoutM,writedataM,
input wire[31:0] readdataM
);
wire [5:0] opD,functD;
wire regdstE,alusrcE,pcsrcD,memtoregE,memtoregM,memtoregW,
regwriteE,regwriteM,regwriteW;
wire [2:0] alucontrolE;
wire flushE,equalD;
controller c(
clk,rst,
//decode stage
opD,functD,
pcsrcD,branchD,equalD,jumpD,
//execute stage
flushE,
memtoregE,alusrcE,
regdstE,regwriteE,
alucontrolE,
//mem stage
memtoregM,memwriteM,
regwriteM,
//write back stage
memtoregW,regwriteW
);
datapath dp(
clk,rst,
//fetch stage
pcF,
instrF,
//decode stage
pcsrcD,branchD,
jumpD,
equalD,
opD,functD,
//execute stage
memtoregE,
alusrcE,regdstE,
regwriteE,
alucontrolE,
flushE,
//mem stage
memtoregM,
regwriteM,
aluoutM,writedataM,
readdataM,
//writeback stage
memtoregW,
regwriteW
);
endmodule |
module datapath(
input wire clk,rst,
//fetch stage
output wire[31:0] pcF,
input wire[31:0] instrF,
//decode stage
input wire pcsrcD,branchD,
input wire jumpD,
output wire equalD,
output wire[5:0] opD,functD,
//execute stage
input wire memtoregE,
input wire alusrcE,regdstE,
input wire regwriteE,
input wire[2:0] alucontrolE,
output wire flushE,
//mem stage
input wire memtoregM,
input wire regwriteM,
output wire[31:0] aluoutM,writedataM,
input wire[31:0] readdataM,
//writeback stage
input wire memtoregW,
input wire regwriteW
);
//fetch stage
wire stallF;
//FD
wire [31:0] pcnextFD,pcnextbrFD,pcplus4F,pcbranchD;
//decode stage
wire [31:0] pcplus4D,instrD;
wire forwardaD,forwardbD;
wire [4:0] rsD,rtD,rdD;
wire flushD,stallD;
wire [31:0] signimmD,signimmshD;
wire [31:0] srcaD,srca2D,srcbD,srcb2D;
//execute stage
wire [1:0] forwardaE,forwardbE;
wire [4:0] rsE,rtE,rdE;
wire [4:0] writeregE;
wire [31:0] signimmE;
wire [31:0] srcaE,srca2E,srcbE,srcb2E,srcb3E;
wire [31:0] aluoutE;
//mem stage
wire [4:0] writeregM;
//writeback stage
wire [4:0] writeregW;
wire [31:0] aluoutW,readdataW,resultW;
//hazard detection
hazard h(
//fetch stage
stallF,
//decode stage
rsD,rtD,
branchD,
forwardaD,forwardbD,
stallD,
//execute stage
rsE,rtE,
writeregE,
regwriteE,
memtoregE,
forwardaE,forwardbE,
flushE,
//mem stage
writeregM,
regwriteM,
memtoregM,
//write back stage
writeregW,
regwriteW
);
//next PC logic (operates in fetch an decode)
mux2 #(32) pcbrmux(pcplus4F,pcbranchD,pcsrcD,pcnextbrFD);
mux2 #(32) pcmux(pcnextbrFD,
{pcplus4D[31:28],instrD[25:0],2'b00},
jumpD,pcnextFD);
//regfile (operates in decode and writeback)
regfile rf(clk,regwriteW,rsD,rtD,writeregW,resultW,srcaD,srcbD);
//fetch stage logic
pc #(32) pcreg(clk,rst,~stallF,pcnextFD,pcF);
adder pcadd1(pcF,32'b100,pcplus4F);
//decode stage
flopenr #(32) r1D(clk,rst,~stallD,pcplus4F,pcplus4D);
flopenrc #(32) r2D(clk,rst,~stallD,flushD,instrF,instrD);
signext se(instrD[15:0],signimmD);
sl2 immsh(signimmD,signimmshD);
adder pcadd2(pcplus4D,signimmshD,pcbranchD);
mux2 #(32) forwardamux(srcaD,aluoutM,forwardaD,srca2D);
mux2 #(32) forwardbmux(srcbD,aluoutM,forwardbD,srcb2D);
eqcmp comp(srca2D,srcb2D,equalD);
assign opD = instrD[31:26];
assign functD = instrD[5:0];
assign rsD = instrD[25:21];
assign rtD = instrD[20:16];
assign rdD = instrD[15:11];
//execute stage
floprc #(32) r1E(clk,rst,flushE,srcaD,srcaE);
floprc #(32) r2E(clk,rst,flushE,srcbD,srcbE);
floprc #(32) r3E(clk,rst,flushE,signimmD,signimmE);
floprc #(5) r4E(clk,rst,flushE,rsD,rsE);
floprc #(5) r5E(clk,rst,flushE,rtD,rtE);
floprc #(5) r6E(clk,rst,flushE,rdD,rdE);
mux3 #(32) forwardaemux(srcaE,resultW,aluoutM,forwardaE,srca2E);
mux3 #(32) forwardbemux(srcbE,resultW,aluoutM,forwardbE,srcb2E);
mux2 #(32) srcbmux(srcb2E,signimmE,alusrcE,srcb3E);
alu alu(srca2E,srcb3E,alucontrolE,aluoutE);
mux2 #(5) wrmux(rtE,rdE,regdstE,writeregE);
//mem stage
flopr #(32) r1M(clk,rst,srcb2E,writedataM);
flopr #(32) r2M(clk,rst,aluoutE,aluoutM);
flopr #(5) r3M(clk,rst,writeregE,writeregM);
//writeback stage
flopr #(32) r1W(clk,rst,aluoutM,aluoutW);
flopr #(32) r2W(clk,rst,readdataM,readdataW);
flopr #(5) r3W(clk,rst,writeregM,writeregW);
mux2 #(32) resmux(aluoutW,readdataW,memtoregW,resultW);
endmodule |
module top(
input wire clk,rst,
output wire[31:0] writedata,dataadr,
output wire memwrite
);
wire[31:0] pc,instr,readdata;
mips mips(clk,rst,pc,instr,memwrite,dataadr,writedata,readdata);
inst_mem imem(~clk,pc[7:2],instr);
data_mem dmem(~clk,memwrite,dataadr,writedata,readdata);
endmodule |
module regfile(
input wire clk,
input wire we3,
input wire[4:0] ra1,ra2,wa3,
input wire[31:0] wd3,
output wire[31:0] rd1,rd2
);
reg [31:0] rf[31:0];
always @(negedge clk) begin
if(we3) begin
rf[wa3] <= wd3;
end
end
assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule |
module flopr #(parameter WIDTH = 8)(
input wire clk,rst,
input wire[WIDTH-1:0] d,
output reg[WIDTH-1:0] q
);
always @(posedge clk,posedge rst) begin
if(rst) begin
q <= 0;
end else begin
q <= d;
end
end
endmodule |
module alu(
input wire[31:0] a,b,
input wire[2:0] op,
output reg[31:0] y,
output reg overflow,
output wire zero
);
wire[31:0] s,bout;
assign bout = op[2] ? ~b : b;
assign s = a + bout + op[2];
always @(*) begin
case (op[1:0])
2'b00: y <= a & bout;
2'b01: y <= a | bout;
2'b10: y <= s;
2'b11: y <= s[31];
default : y <= 32'b0;
endcase
end
assign zero = (y == 32'b0);
always @(*) begin
case (op[2:1])
2'b01:overflow <= a[31] & b[31] & ~s[31] |
~a[31] & ~b[31] & s[31];
2'b11:overflow <= ~a[31] & b[31] & s[31] |
a[31] & ~b[31] & ~s[31];
default : overflow <= 1'b0;
endcase
end
endmodule |
module controller(
input wire[5:0] op,funct,
input wire zero,
output wire memtoreg,memwrite,
output wire pcsrc,alusrc,
output wire regdst,regwrite,
output wire jump,
output wire[2:0] alucontrol
);
wire[1:0] aluop;
wire branch;
maindec md(op,memtoreg,memwrite,branch,alusrc,regdst,regwrite,jump,aluop);
aludec ad(funct,aluop,alucontrol);
assign pcsrc = branch & zero;
endmodule |
module mips(
input wire clk,rst,
output wire[31:0] pc,
input wire[31:0] instr,
output wire memwrite,
output wire[31:0] aluout,writedata,
input wire[31:0] readdata
);
wire memtoreg,alusrc,regdst,regwrite,jump,pcsrc,zero,overflow;
wire[2:0] alucontrol;
controller c(instr[31:26],instr[5:0],zero,memtoreg,
memwrite,pcsrc,alusrc,regdst,regwrite,jump,alucontrol);
datapath dp(clk,rst,memtoreg,pcsrc,alusrc,
regdst,regwrite,jump,alucontrol,overflow,zero,pc,instr,aluout,writedata,readdata);
endmodule |
module datapath(
input wire clk,rst,
input wire memtoreg,pcsrc,
input wire alusrc,regdst,
input wire regwrite,jump,
input wire[2:0] alucontrol,
output wire overflow,zero,
output wire[31:0] pc,
input wire[31:0] instr,
output wire[31:0] aluout,writedata,
input wire[31:0] readdata
);
wire[4:0] writereg;
wire[31:0] pcnext,pcnextbr,pcplus4,pcbranch;
wire[31:0] signimm,signimmsh;
wire[31:0] srca,srcb;
wire[31:0] result;
flopr #(32) pcreg(clk,rst,pcnext,pc);
adder pcadd1(pc,32'b100,pcplus4);
sl2 immsh(signimm,signimmsh);
adder pcadd2(pcplus4,signimmsh,pcbranch);
mux2 #(32) pcbrmux(pcplus4,pcbranch,pcsrc,pcnextbr);
mux2 #(32) pcmux(pcnextbr,{pcplus4[31:28],instr[25:0],2'b00},jump,pcnext);
regfile rf(clk,regwrite,instr[25:21],instr[20:16],writereg,result,srca,writedata);
mux2 #(5) wrmux(instr[20:16],instr[15:11],regdst,writereg);
mux2 #(32) resmux(aluout,readdata,memtoreg,result);
signext se(instr[15:0],signimm);
mux2 #(32) srcbmux(writedata,signimm,alusrc,srcb);
alu alu(srca,srcb,alucontrol,aluout,overflow,zero);
endmodule |
module calculate(
input wire [7:0] num1,
input wire [2:0] op,
output [31:0] result
);
wire [31:0] num2;
wire [31:0] Sign_extend;
assign num2 = 32'h00000001;
assign Sign_extend={{24{1'b0}},num1[7:0]};
assign result = (op == 3'b000)? Sign_extend + num2:
(op == 3'b001)? Sign_extend - num2:
(op == 3'b010)? Sign_extend & num2:
(op == 3'b011)? Sign_extend | num2:
(op == 3'b100)? ~Sign_extend: 32'h00000000;
endmodule |
module top(
input clk,
input rst,
input [2:0] op,
input [7:0] num1,
output [7:0] ans,
output [6:0] seg
);
wire [31:0] s;
calculate U1(.num1(num1),.op(op),.result(s));
display U2(.clk(clk),.reset(rst),.s(s),.ans(ans),.seg(seg));
endmodule |
module le_tb;
reg clk;
reg [31:0] le_a;
reg [31:0] le_b;
wire [0:0] le_z;
integer le_a_file;
integer le_b_file;
integer le_z_file;
integer le_a_count;
integer le_b_count;
integer le_z_count;
le le1 (clk, le_a, le_b, le_z);
initial
begin
le_z_file = $fopen("stim/le_z");
le_a_file = $fopen("stim/le_a", "r");
le_b_file = $fopen("stim/le_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(le_z_file, "%d", le_z);
#0 le_a_count = $fscanf(le_a_file, "%d\n", le_a);
#0 le_b_count = $fscanf(le_b_file, "%d\n", le_b);
end
endmodule |
module eq_tb;
reg clk;
reg [31:0] eq_a;
reg [31:0] eq_b;
wire [0:0] eq_z;
integer eq_a_file;
integer eq_b_file;
integer eq_z_file;
integer eq_a_count;
integer eq_b_count;
integer eq_z_count;
eq eq1 (clk, eq_a, eq_b, eq_z);
initial
begin
eq_z_file = $fopen("stim/eq_z");
eq_a_file = $fopen("stim/eq_a", "r");
eq_b_file = $fopen("stim/eq_b", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(eq_z_file, "%d", eq_z);
#0 eq_a_count = $fscanf(eq_a_file, "%d\n", eq_a);
#0 eq_b_count = $fscanf(eq_b_file, "%d\n", eq_b);
end
endmodule |
module neg_tb;
reg clk;
reg [31:0] neg_a;
wire [31:0] neg_z;
integer neg_a_file;
integer neg_z_file;
integer neg_a_count;
integer neg_z_count;
neg neg1 (clk, neg_a, neg_z);
initial
begin
neg_z_file = $fopen("stim/neg_z");
neg_a_file = $fopen("stim/neg_a", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(neg_z_file, "%d", neg_z);
#0 neg_a_count = $fscanf(neg_a_file, "%d\n", neg_a);
end
endmodule |
module floor_tb;
reg clk;
reg [31:0] floor_a;
wire [31:0] floor_z;
integer floor_a_file;
integer floor_z_file;
integer floor_a_count;
integer floor_z_count;
floor floor1 (clk, floor_a, floor_z);
initial
begin
floor_z_file = $fopen("stim/floor_z");
floor_a_file = $fopen("stim/floor_a", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(floor_z_file, "%d", floor_z);
#0 floor_a_count = $fscanf(floor_a_file, "%d\n", floor_a);
end
endmodule |
module nearest_tb;
reg clk;
reg [31:0] nearest_a;
wire [31:0] nearest_z;
integer nearest_a_file;
integer nearest_z_file;
integer nearest_a_count;
integer nearest_z_count;
nearest nearest1 (clk, nearest_a, nearest_z);
initial
begin
nearest_z_file = $fopen("stim/nearest_z");
nearest_a_file = $fopen("stim/nearest_a", "r");
end
initial
begin
#4480 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(nearest_z_file, "%d", nearest_z);
#0 nearest_a_count = $fscanf(nearest_a_file, "%d\n", nearest_a);
end
endmodule |
Subsets and Splits