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module oc_snap_core(
//
//Clocks&Reset
input clock_tlx ,
input clock_afu ,
input reset_snap ,
//configuration
input [3:0] cfg_backoff_timer ,
input [7:0] cfg_bdf_bus ,
input [4:0] cfg_bdf_device ,
input [2:0] cfg_bdf_function ,
input [11:0] cfg_actag_base ,
input [19:0] cfg_pasid_base ,
input [4:0] cfg_pasid_length ,
input [63:0] cfg_f1_mmio_bar0 ,
input [63:0] cfg_f1_mmio_bar0_mask ,
//AFU-TLXcommandtransmitinterface
output afu_tlx_cmd_valid ,
output [7:0] afu_tlx_cmd_opcode ,
output [11:0] afu_tlx_cmd_actag ,
output [3:0] afu_tlx_cmd_stream_id ,
output [67:0] afu_tlx_cmd_ea_or_obj ,
output [15:0] afu_tlx_cmd_afutag ,
output [1:0] afu_tlx_cmd_dl ,
output [2:0] afu_tlx_cmd_pl ,
output afu_tlx_cmd_os ,
output [63:0] afu_tlx_cmd_be ,
output [3:0] afu_tlx_cmd_flag ,
output afu_tlx_cmd_endian ,
output [15:0] afu_tlx_cmd_bdf ,
output [19:0] afu_tlx_cmd_pasid ,
output [5:0] afu_tlx_cmd_pg_size ,
output afu_tlx_cdata_valid ,
output afu_tlx_cdata_bdi ,
output [511:0] afu_tlx_cdata_bus ,
input tlx_afu_cmd_credit ,
input tlx_afu_cmd_data_credit ,
input [3:0] tlx_afu_cmd_initial_credit ,
input [5:0] tlx_afu_cmd_data_initial_credit ,
//
//TLX-AFUresponsereceiveinterface
input tlx_afu_resp_valid ,
input [7:0] tlx_afu_resp_opcode ,
input [15:0] tlx_afu_resp_afutag ,
input [3:0] tlx_afu_resp_code ,
input [1:0] tlx_afu_resp_dl ,
input [1:0] tlx_afu_resp_dp ,
output afu_tlx_resp_rd_req ,
output [2:0] afu_tlx_resp_rd_cnt ,
input tlx_afu_resp_data_valid ,
input tlx_afu_resp_data_bdi ,
input [511:0] tlx_afu_resp_data_bus ,
output afu_tlx_resp_credit ,
output [6:0] afu_tlx_resp_initial_credit ,
//
//TLX-AFUcommandreceiveinterface
input tlx_afu_cmd_valid ,
input [7:0] tlx_afu_cmd_opcode ,
input [15:0] tlx_afu_cmd_capptag ,
input [1:0] tlx_afu_cmd_dl ,
input [2:0] tlx_afu_cmd_pl ,
input [63:0] tlx_afu_cmd_be ,
input tlx_afu_cmd_end ,
input [63:0] tlx_afu_cmd_pa ,
input [3:0] tlx_afu_cmd_flag ,
input tlx_afu_cmd_os ,
output afu_tlx_cmd_credit ,
output [6:0] afu_tlx_cmd_initial_credit ,
output afu_tlx_cmd_rd_req ,
output [2:0] afu_tlx_cmd_rd_cnt ,
input tlx_afu_cmd_data_valid ,
input tlx_afu_cmd_data_bdi ,
input [511:0] tlx_afu_cmd_data_bus ,
//
//AFU-TLXresponsetransmitinterface
output afu_tlx_resp_valid ,
output [7:0] afu_tlx_resp_opcode ,
output [1:0] afu_tlx_resp_dl ,
output [15:0] afu_tlx_resp_capptag ,
output [1:0] afu_tlx_resp_dp ,
output [3:0] afu_tlx_resp_code ,
output afu_tlx_rdata_valid ,
output afu_tlx_rdata_bdi ,
output [511:0] afu_tlx_rdata_bus ,
input tlx_afu_resp_credit ,
input tlx_afu_resp_data_credit ,
input [3:0] tlx_afu_resp_initial_credit ,
input [5:0] tlx_afu_resp_data_initial_credit ,
//
//ACTIONInterface
//misc
output soft_reset_action ,
//
`ifndef ENABLE_ODMA
//MMIOtoconverteroraction
//xk_d_o:OUTXK_D_T;
output [`AXI_LITE_AW-1:0] lite_snap2conv_awaddr ,
output [2:0] lite_snap2conv_awprot ,
output lite_snap2conv_awvalid ,
output [`AXI_LITE_DW-1:0] lite_snap2conv_wdata ,
output [3:0] lite_snap2conv_wstrb ,
output lite_snap2conv_wvalid ,
output lite_snap2conv_bready ,
output [`AXI_LITE_AW-1:0] lite_snap2conv_araddr ,
output [2:0] lite_snap2conv_arprot ,
output lite_snap2conv_arvalid ,
output lite_snap2conv_rready ,
//kx_d_i:INKX_D_T;
input lite_conv2snap_awready ,
input lite_conv2snap_wready ,
input [1:0] lite_conv2snap_bresp ,
input lite_conv2snap_bvalid ,
input lite_conv2snap_arready ,
input [`AXI_LITE_DW-1:0] lite_conv2snap_rdata ,
input [1:0] lite_conv2snap_rresp ,
input lite_conv2snap_rvalid ,
//dwidth_convertororactiontobridge
//sk_d:OUTSK_D_T;
output mm_snap2conv_awready ,
output mm_snap2conv_wready ,
output [`IDW-1:0] mm_snap2conv_bid ,
output [1:0] mm_snap2conv_bresp ,
output mm_snap2conv_bvalid ,
output [`IDW-1:0] mm_snap2conv_rid ,
output [`AXI_MM_DW-1:0] mm_snap2conv_rdata ,
output [1:0] mm_snap2conv_rresp ,
output mm_snap2conv_rlast ,
output mm_snap2conv_rvalid ,
output mm_snap2conv_arready ,
output int_req_ack ,
//ks_d:INKS_D_T
input [`IDW-1:0] mm_conv2snap_awid ,
input [`AXI_MM_AW-1:0] mm_conv2snap_awaddr ,
input [7:0] mm_conv2snap_awlen ,
input [2:0] mm_conv2snap_awsize ,
input [1:0] mm_conv2snap_awburst ,
input mm_conv2snap_awlock ,
input [3:0] mm_conv2snap_awcache ,
input [2:0] mm_conv2snap_awprot ,
input [3:0] mm_conv2snap_awqos ,
input [3:0] mm_conv2snap_awregion ,
input [`AXI_AWUSER-1:0] mm_conv2snap_awuser ,
input mm_conv2snap_awvalid ,
input [`AXI_MM_DW-1:0] mm_conv2snap_wdata ,
input [(`AXI_MM_DW/8)-1:0] mm_conv2snap_wstrb ,
input mm_conv2snap_wlast ,
input mm_conv2snap_wvalid ,
input mm_conv2snap_bready ,
output[`AXI_AWUSER-1:0] mm_snap2conv_buser ,
input [`IDW-1:0] mm_conv2snap_arid ,
input [`AXI_MM_AW-1:0] mm_conv2snap_araddr ,
input [7:0] mm_conv2snap_arlen ,
input [2:0] mm_conv2snap_arsize ,
input [1:0] mm_conv2snap_arburst ,
input [`AXI_ARUSER-1:0] mm_conv2snap_aruser ,
input mm_conv2snap_arlock ,
input [3:0] mm_conv2snap_arcache ,
input [2:0] mm_conv2snap_arprot ,
input [3:0] mm_conv2snap_arqos ,
input [3:0] mm_conv2snap_arregion ,
input mm_conv2snap_arvalid ,
input mm_conv2snap_rready ,
output[`AXI_AWUSER-1:0] mm_snap2conv_ruser ,
input int_req ,
input [`INT_BITS-1:0] int_src ,
input [`CTXW-1:0] int_ctx
//Note: here is the end of port list
`else
`ifdef ENABLE_ODMA_ST_MODE
input m_axis_tready ,
output m_axis_tlast ,
output [`AXI_ST_DW - 1:0] m_axis_tdata ,
output [`AXI_ST_DW/8 - 1:0] m_axis_tkeep ,
output m_axis_tvalid ,
output [`IDW - 1:0] m_axis_tid ,
output [`AXI_ST_USER - 1:0] m_axis_tuser ,
output s_axis_tready ,
input s_axis_tlast ,
input [`AXI_ST_DW - 1:0] s_axis_tdata ,
input [`AXI_ST_DW/8 - 1:0] s_axis_tkeep ,
input s_axis_tvalid ,
input [`IDW - 1:0] s_axis_tid ,
input [`AXI_ST_USER - 1:0] s_axis_tuser ,
`else
//ODMAmode:AXI4-MMInterface
output [`AXI_MM_AW-1:0] axi_mm_awaddr ,
output [`IDW-1:0] axi_mm_awid ,
output [7:0] axi_mm_awlen ,
output [2:0] axi_mm_awsize ,
output [1:0] axi_mm_awburst ,
output [2:0] axi_mm_awprot ,
output [3:0] axi_mm_awqos ,
output [3:0] axi_mm_awregion ,
output [`AXI_AWUSER-1:0] axi_mm_awuser ,
output axi_mm_awvalid ,
output [1:0] axi_mm_awlock ,
output [3:0] axi_mm_awcache ,
input axi_mm_awready ,
output [`AXI_MM_DW-1:0] axi_mm_wdata ,
output axi_mm_wlast ,
output [`AXI_MM_DW/8-1:0] axi_mm_wstrb ,
output axi_mm_wvalid ,
output [`AXI_WUSER-1:0] axi_mm_wuser ,
input axi_mm_wready ,
input axi_mm_bvalid ,
input [1:0] axi_mm_bresp ,
input [`IDW-1:0] axi_mm_bid ,
input [`AXI_BUSER-1:0] axi_mm_buser ,
output axi_mm_bready ,
output [`AXI_MM_AW-1:0] axi_mm_araddr ,
output [1:0] axi_mm_arburst ,
output [3:0] axi_mm_arcache ,
output [`IDW-1:0] axi_mm_arid ,
output [7:0] axi_mm_arlen ,
output [1:0] axi_mm_arlock ,
output [2:0] axi_mm_arprot ,
output [3:0] axi_mm_arqos ,
input axi_mm_arready ,
output [3:0] axi_mm_arregion ,
output [2:0] axi_mm_arsize ,
output [`AXI_ARUSER-1:0] axi_mm_aruser ,
output axi_mm_arvalid ,
input [`AXI_MM_DW-1:0] axi_mm_rdata ,
input [`IDW-1:0] axi_mm_rid ,
input axi_mm_rlast ,
output axi_mm_rready ,
input [1:0] axi_mm_rresp ,
input [`AXI_RUSER-1:0] axi_mm_ruser ,
input axi_mm_rvalid ,
`endif
//
//ActionAXI-LiteslaveInterface
input a_s_axi_arvalid ,
input [`AXI_LITE_AW-1:0] a_s_axi_araddr ,
output a_s_axi_arready ,
output a_s_axi_rvalid ,
output [`AXI_LITE_DW-1:0] a_s_axi_rdata ,
output [1:0] a_s_axi_rresp ,
input a_s_axi_rready ,
input a_s_axi_awvalid ,
input [`AXI_LITE_AW-1:0] a_s_axi_awaddr ,
output a_s_axi_awready ,
input a_s_axi_wvalid ,
input [`AXI_LITE_DW-1:0] a_s_axi_wdata ,
input [`AXI_LITE_DW/8-1:0] a_s_axi_wstrb ,
output a_s_axi_wready ,
output a_s_axi_bvalid ,
output [1:0] a_s_axi_bresp ,
input a_s_axi_bready ,
//ActionAXI-LitemasterInterface
output a_m_axi_arvalid ,
output [`AXI_LITE_AW-1:0] a_m_axi_araddr ,
input a_m_axi_arready ,
input a_m_axi_rvalid ,
input [`AXI_LITE_DW-1:0] a_m_axi_rdata ,
input [1:0] a_m_axi_rresp ,
output a_m_axi_rready ,
output a_m_axi_awvalid ,
output [`AXI_LITE_AW-1:0] a_m_axi_awaddr ,
input a_m_axi_awready ,
output a_m_axi_wvalid ,
output [`AXI_LITE_DW-1:0] a_m_axi_wdata ,
output [`AXI_LITE_DW/8-1:0] a_m_axi_wstrb ,
input a_m_axi_wready ,
input a_m_axi_bvalid ,
input [1:0] a_m_axi_bresp ,
output a_m_axi_bready
`endif
) ; //end of module ports
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// wires
//------------------------------------------------------------------------------
//-----------------------------------------------------------------------------
`ifdef ENABLE_ODMA
wire [`AXI_LITE_AW-1:0] lite_mmio2odma_awaddr ;
wire [2:0] lite_mmio2odma_awprot ;
wire lite_mmio2odma_awvalid ;
wire [`AXI_LITE_DW-1:0] lite_mmio2odma_wdata ;
wire [3:0] lite_mmio2odma_wstrb ;
wire lite_mmio2odma_wvalid ;
wire lite_mmio2odma_bready ;
wire [`AXI_LITE_AW-1:0] lite_mmio2odma_araddr ;
wire [2:0] lite_mmio2odma_arprot ;
wire lite_mmio2odma_arvalid ;
wire lite_mmio2odma_rready ;
wire lite_odma2mmio_awready ;
wire lite_odma2mmio_wready ;
wire [1:0] lite_odma2mmio_bresp ;
wire lite_odma2mmio_bvalid ;
wire lite_odma2mmio_arready ;
wire [`AXI_LITE_DW-1:0] lite_odma2mmio_rdata ;
wire [1:0] lite_odma2mmio_rresp ;
wire lite_odma2mmio_rvalid ;
`endif
wire debug_cnt_clear ;
wire [63:0] debug_tlx_cnt_cmd ;
wire [63:0] debug_tlx_cnt_rsp ;
wire [63:0] debug_tlx_cnt_retry ;
wire [63:0] debug_tlx_cnt_fail ;
wire [63:0] debug_tlx_cnt_xlt_pd ;
wire [63:0] debug_tlx_cnt_xlt_done ;
wire [63:0] debug_tlx_cnt_xlt_retry ;
wire [63:0] debug_axi_cnt_cmd ;
wire [63:0] debug_axi_cnt_rsp ;
wire [63:0] debug_buf_cnt ;
wire [63:0] debug_traffic_idle ;
wire [63:0] debug_tlx_idle_lim ;
wire [63:0] debug_axi_idle_lim ;
wire [63:0] fir_fifo_overflow ;
wire [63:0] fir_tlx_interface ;
wire soft_reset_brdg_odma ;
wire brdg_odma_rst_n ;
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// SNAP CORE ENTITIES
//------------------------------------------------------------------------------
//-----------------------------------------------------------------------------
`ifndef ENABLE_ODMA
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// BRIDGE Entity
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
brdg_wrapper bridge (
//
// Clocks & Reset
.clk_tlx ( clock_tlx ) ,
.clk_afu ( clock_afu ) ,
.rst_n ( brdg_odma_rst_n ) ,
//
// CONFIGURATION
.cfg_backoff_timer ( cfg_backoff_timer ) ,
.cfg_bdf_bus ( cfg_bdf_bus ) ,
.cfg_bdf_device ( cfg_bdf_device ) ,
.cfg_bdf_function ( cfg_bdf_function ) ,
.cfg_actag_base ( cfg_actag_base ) ,
.cfg_pasid_base ( cfg_pasid_base ) ,
.cfg_pasid_length ( cfg_pasid_length ) ,
// STATUS
.debug_cnt_clear ( debug_cnt_clear ) ,
.debug_tlx_cnt_cmd ( debug_tlx_cnt_cmd ) ,
.debug_tlx_cnt_rsp ( debug_tlx_cnt_rsp ) ,
.debug_tlx_cnt_retry ( debug_tlx_cnt_retry ) ,
.debug_tlx_cnt_fail ( debug_tlx_cnt_fail ) ,
.debug_tlx_cnt_xlt_pd ( debug_tlx_cnt_xlt_pd ) ,
.debug_tlx_cnt_xlt_done ( debug_tlx_cnt_xlt_done ) ,
.debug_tlx_cnt_xlt_retry ( debug_tlx_cnt_xlt_retry ) ,
.debug_axi_cnt_cmd ( debug_axi_cnt_cmd ) ,
.debug_axi_cnt_rsp ( debug_axi_cnt_rsp ) ,
.debug_buf_cnt ( debug_buf_cnt ) ,
.debug_traffic_idle ( debug_traffic_idle ) ,
.debug_tlx_idle_lim ( debug_tlx_idle_lim ) ,
.debug_axi_idle_lim ( debug_axi_idle_lim ) ,
.fir_fifo_overflow ( fir_fifo_overflow ) ,
.fir_tlx_interface ( fir_tlx_interface ) ,
//
//
// AFU-TLX command transmit interface
.afu_tlx_cmd_valid ( afu_tlx_cmd_valid ) ,
.afu_tlx_cmd_opcode ( afu_tlx_cmd_opcode ) ,
.afu_tlx_cmd_actag ( afu_tlx_cmd_actag ) ,
.afu_tlx_cmd_stream_id ( afu_tlx_cmd_stream_id ) ,
.afu_tlx_cmd_ea_or_obj ( afu_tlx_cmd_ea_or_obj ) ,
.afu_tlx_cmd_afutag ( afu_tlx_cmd_afutag ) ,
.afu_tlx_cmd_dl ( afu_tlx_cmd_dl ) ,
.afu_tlx_cmd_pl ( afu_tlx_cmd_pl ) ,
.afu_tlx_cmd_os ( afu_tlx_cmd_os ) ,
.afu_tlx_cmd_be ( afu_tlx_cmd_be ) ,
.afu_tlx_cmd_flag ( afu_tlx_cmd_flag ) ,
.afu_tlx_cmd_endian ( afu_tlx_cmd_endian ) ,
.afu_tlx_cmd_bdf ( afu_tlx_cmd_bdf ) ,
.afu_tlx_cmd_pasid ( afu_tlx_cmd_pasid ) ,
.afu_tlx_cmd_pg_size ( afu_tlx_cmd_pg_size ) ,
.afu_tlx_cdata_valid ( afu_tlx_cdata_valid ) ,
.afu_tlx_cdata_bdi ( afu_tlx_cdata_bdi ) ,
.afu_tlx_cdata_bus ( afu_tlx_cdata_bus ) ,
.tlx_afu_cmd_credit ( tlx_afu_cmd_credit ) ,
.tlx_afu_cmd_data_credit ( tlx_afu_cmd_data_credit ) ,
.tlx_afu_cmd_initial_credit ( tlx_afu_cmd_initial_credit ) ,
.tlx_afu_cmd_data_initial_credit ( tlx_afu_cmd_data_initial_credit ) ,
//
// TLX-AFU response receive interface
.tlx_afu_resp_valid ( tlx_afu_resp_valid ) ,
.tlx_afu_resp_afutag ( tlx_afu_resp_afutag ) ,
.tlx_afu_resp_opcode ( tlx_afu_resp_opcode ) ,
.tlx_afu_resp_code ( tlx_afu_resp_code ) ,
.tlx_afu_resp_dl ( tlx_afu_resp_dl ) ,
.tlx_afu_resp_dp ( tlx_afu_resp_dp ) ,
.afu_tlx_resp_rd_req ( afu_tlx_resp_rd_req ) ,
.afu_tlx_resp_rd_cnt ( afu_tlx_resp_rd_cnt ) ,
.tlx_afu_resp_data_valid ( tlx_afu_resp_data_valid ) ,
.tlx_afu_resp_data_bus ( tlx_afu_resp_data_bus ) ,
.tlx_afu_resp_data_bdi ( tlx_afu_resp_data_bdi ) ,
.afu_tlx_resp_credit ( afu_tlx_resp_credit ) ,
.afu_tlx_resp_initial_credit ( afu_tlx_resp_initial_credit ) ,
//
// AXI write address channel
.s_axi_awid ( mm_conv2snap_awid ) ,
.s_axi_awaddr ( mm_conv2snap_awaddr ) ,
.s_axi_awlen ( mm_conv2snap_awlen ) ,
.s_axi_awvalid ( mm_conv2snap_awvalid ) ,
.s_axi_awready ( mm_snap2conv_awready ) ,
.s_axi_awsize ( mm_conv2snap_awsize ) ,
.s_axi_awburst ( mm_conv2snap_awburst ) ,
// .s_axi_awcache ( mm_conv2snap_awcache ) ,
// .s_axi_awlock ( mm_conv2snap_awlock ) ,
// .s_axi_awprot ( mm_conv2snap_awprot ) ,
// .s_axi_awqos ( mm_conv2snap_awqos ) ,
// .s_axi_awregion ( mm_conv2snap_awregion ) ,
.s_axi_awuser ( mm_conv2snap_awuser ) ,
//
// AXI write data channel
// .s_axi_wid ( mm_conv2snap_wid ) ,
.s_axi_wdata ( mm_conv2snap_wdata ) ,
.s_axi_wstrb ( mm_conv2snap_wstrb ) ,
.s_axi_wlast ( mm_conv2snap_wlast ) ,
.s_axi_wvalid ( mm_conv2snap_wvalid ) ,
.s_axi_wready ( mm_snap2conv_wready ) ,
//
// AXI write response channel
.s_axi_bready ( mm_conv2snap_bready ) ,
.s_axi_bid ( mm_snap2conv_bid ) ,
.s_axi_bresp ( mm_snap2conv_bresp ) ,
.s_axi_bvalid ( mm_snap2conv_bvalid ) ,
.s_axi_buser ( mm_snap2conv_buser ) ,
//
// AXI read address channel
.s_axi_arid ( mm_conv2snap_arid ) ,
.s_axi_araddr ( mm_conv2snap_araddr ) ,
.s_axi_arlen ( mm_conv2snap_arlen ) ,
.s_axi_arsize ( mm_conv2snap_arsize ) ,
.s_axi_arburst ( mm_conv2snap_arburst ) ,
.s_axi_aruser ( mm_conv2snap_aruser ) ,
// .s_axi_arcache ( mm_conv2snap_arcache ) ,
// .s_axi_arlock ( mm_conv2snap_arlock ) ,
// .s_axi_arprot ( mm_conv2snap_arprot ) ,
// .s_axi_arqos ( mm_conv2snap_arqos ) ,
// .s_axi_arregion ( mm_conv2snap_arregion ) ,
.s_axi_arvalid ( mm_conv2snap_arvalid ) ,
.s_axi_arready ( mm_snap2conv_arready ) ,
//
// AXI read data channel
.s_axi_rready ( mm_conv2snap_rready ) ,
.s_axi_rid ( mm_snap2conv_rid ) ,
.s_axi_rdata ( mm_snap2conv_rdata ) ,
.s_axi_rresp ( mm_snap2conv_rresp ) ,
.s_axi_rlast ( mm_snap2conv_rlast ) ,
.s_axi_rvalid ( mm_snap2conv_rvalid ) ,
.s_axi_ruser ( mm_snap2conv_ruser ) ,
//
// interrupt channel
.interrupt_ack ( int_req_ack ),
.interrupt ( int_req ),
.interrupt_src ( int_src ),
.interrupt_ctx ( int_ctx )
) ;
`else
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// ODMA Entity
//
//
// shortcut = o
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
odma_wrapper #(
.IDW(`IDW),
.CTXW(`CTXW),
.TAGW(`TAGW),
.AXI_MM_DW(`AXI_MM_DW),
.AXI_MM_AW(`AXI_MM_AW),
.AXI_ST_DW(`AXI_ST_DW),
.AXI_ST_AW(`AXI_ST_AW),
.AXI_LITE_DW(`AXI_LITE_DW),
.AXI_LITE_AW(`AXI_LITE_AW),
.AXI_MM_AWUSER(`AXI_AWUSER),
.AXI_MM_ARUSER(`AXI_ARUSER),
.AXI_MM_WUSER(`AXI_WUSER),
.AXI_MM_RUSER(`AXI_RUSER),
.AXI_MM_BUSER(`AXI_BUSER),
.AXI_ST_USER(`AXI_ST_USER)
)
odma (
//
// Clocks & Reset
.clk_tlx ( clock_tlx ) ,
.clk_afu ( clock_afu ) ,
.rst_n ( brdg_odma_rst_n ) ,
//
// CONFIGURATION
.cfg_backoff_timer ( cfg_backoff_timer ) ,
.cfg_bdf_bus ( cfg_bdf_bus ) ,
.cfg_bdf_device ( cfg_bdf_device ) ,
.cfg_bdf_function ( cfg_bdf_function ) ,
.cfg_actag_base ( cfg_actag_base ) ,
.cfg_pasid_base ( cfg_pasid_base ) ,
.cfg_pasid_length ( cfg_pasid_length ) ,
// STATUS
.debug_cnt_clear ( debug_cnt_clear ) ,
.debug_tlx_cnt_cmd ( debug_tlx_cnt_cmd ) ,
.debug_tlx_cnt_rsp ( debug_tlx_cnt_rsp ) ,
.debug_tlx_cnt_retry ( debug_tlx_cnt_retry ) ,
.debug_tlx_cnt_fail ( debug_tlx_cnt_fail ) ,
.debug_tlx_cnt_xlt_pd ( debug_tlx_cnt_xlt_pd ) ,
.debug_tlx_cnt_xlt_done ( debug_tlx_cnt_xlt_done ) ,
.debug_tlx_cnt_xlt_retry ( debug_tlx_cnt_xlt_retry ) ,
.debug_axi_cnt_cmd ( debug_axi_cnt_cmd ) ,
.debug_axi_cnt_rsp ( debug_axi_cnt_rsp ) ,
.debug_buf_cnt ( debug_buf_cnt ) ,
.debug_traffic_idle ( debug_traffic_idle ) ,
.debug_tlx_idle_lim ( debug_tlx_idle_lim ) ,
.debug_axi_idle_lim ( debug_axi_idle_lim ) ,
.fir_fifo_overflow ( fir_fifo_overflow ) ,
.fir_tlx_interface ( fir_tlx_interface ) ,
//
//
// AFU-TLX command transmit interface
.afu_tlx_cmd_valid ( afu_tlx_cmd_valid ) ,
.afu_tlx_cmd_opcode ( afu_tlx_cmd_opcode ) ,
.afu_tlx_cmd_actag ( afu_tlx_cmd_actag ) ,
.afu_tlx_cmd_stream_id ( afu_tlx_cmd_stream_id ) ,
.afu_tlx_cmd_ea_or_obj ( afu_tlx_cmd_ea_or_obj ) ,
.afu_tlx_cmd_afutag ( afu_tlx_cmd_afutag ) ,
.afu_tlx_cmd_dl ( afu_tlx_cmd_dl ) ,
.afu_tlx_cmd_pl ( afu_tlx_cmd_pl ) ,
.afu_tlx_cmd_os ( afu_tlx_cmd_os ) ,
.afu_tlx_cmd_be ( afu_tlx_cmd_be ) ,
.afu_tlx_cmd_flag ( afu_tlx_cmd_flag ) ,
.afu_tlx_cmd_endian ( afu_tlx_cmd_endian ) ,
.afu_tlx_cmd_bdf ( afu_tlx_cmd_bdf ) ,
.afu_tlx_cmd_pasid ( afu_tlx_cmd_pasid ) ,
.afu_tlx_cmd_pg_size ( afu_tlx_cmd_pg_size ) ,
.afu_tlx_cdata_valid ( afu_tlx_cdata_valid ) ,
.afu_tlx_cdata_bdi ( afu_tlx_cdata_bdi ) ,
.afu_tlx_cdata_bus ( afu_tlx_cdata_bus ) ,
.tlx_afu_cmd_credit ( tlx_afu_cmd_credit ) ,
.tlx_afu_cmd_data_credit ( tlx_afu_cmd_data_credit ) ,
.tlx_afu_cmd_initial_credit ( tlx_afu_cmd_initial_credit ) ,
.tlx_afu_cmd_data_initial_credit ( tlx_afu_cmd_data_initial_credit ) ,
//
// TLX-AFU response receive interface
.tlx_afu_resp_valid ( tlx_afu_resp_valid ) ,
.tlx_afu_resp_afutag ( tlx_afu_resp_afutag ) ,
.tlx_afu_resp_opcode ( tlx_afu_resp_opcode ) ,
.tlx_afu_resp_code ( tlx_afu_resp_code ) ,
.tlx_afu_resp_dl ( tlx_afu_resp_dl ) ,
.tlx_afu_resp_dp ( tlx_afu_resp_dp ) ,
.afu_tlx_resp_rd_req ( afu_tlx_resp_rd_req ) ,
.afu_tlx_resp_rd_cnt ( afu_tlx_resp_rd_cnt ) ,
.tlx_afu_resp_data_valid ( tlx_afu_resp_data_valid ) ,
.tlx_afu_resp_data_bus ( tlx_afu_resp_data_bus ) ,
.tlx_afu_resp_data_bdi ( tlx_afu_resp_data_bdi ) ,
.afu_tlx_resp_credit ( afu_tlx_resp_credit ) ,
.afu_tlx_resp_initial_credit ( afu_tlx_resp_initial_credit ) ,
//
`ifndef ENABLE_ODMA_ST_MODE
// AXI4-MM Interface to action
// Write Addr/Req channel
.axi_mm_awaddr ( axi_mm_awaddr ) ,
.axi_mm_awid ( axi_mm_awid ) ,
.axi_mm_awlen ( axi_mm_awlen ) ,
.axi_mm_awsize ( axi_mm_awsize ) ,
.axi_mm_awburst ( axi_mm_awburst ) ,
.axi_mm_awprot ( axi_mm_awprot ) ,
.axi_mm_awqos ( axi_mm_awqos ) ,
.axi_mm_awregion ( axi_mm_awregion ) ,
.axi_mm_awuser ( axi_mm_awuser ) ,
.axi_mm_awvalid ( axi_mm_awvalid ) ,
.axi_mm_awlock ( axi_mm_awlock ) ,
.axi_mm_awcache ( axi_mm_awcache ) ,
.axi_mm_awready ( axi_mm_awready ) ,
//
// Write Data channel
.axi_mm_wdata ( axi_mm_wdata ) ,
.axi_mm_wlast ( axi_mm_wlast ) ,
.axi_mm_wstrb ( axi_mm_wstrb ) ,
.axi_mm_wvalid ( axi_mm_wvalid ) ,
.axi_mm_wuser ( axi_mm_wuser ) ,
.axi_mm_wready ( axi_mm_wready ) ,
//
// Write Response channel
.axi_mm_bvalid ( axi_mm_bvalid ) ,
.axi_mm_bresp ( axi_mm_bresp ) ,
.axi_mm_bid ( axi_mm_bid ) ,
.axi_mm_buser ( axi_mm_buser ) ,
.axi_mm_bready ( axi_mm_bready ) ,
//
// Read Addr/Req Channel
.axi_mm_araddr ( axi_mm_araddr ) ,
.axi_mm_arburst ( axi_mm_arburst ) ,
.axi_mm_arcache ( axi_mm_arcache ) ,
.axi_mm_arid ( axi_mm_arid ) ,
.axi_mm_arlen ( axi_mm_arlen ) ,
.axi_mm_arlock ( axi_mm_arlock ) ,
.axi_mm_arprot ( axi_mm_arprot ) ,
.axi_mm_arqos ( axi_mm_arqos ) ,
.axi_mm_arready ( axi_mm_arready ) ,
.axi_mm_arregion ( axi_mm_arregion ) ,
.axi_mm_arsize ( axi_mm_arsize ) ,
.axi_mm_aruser ( axi_mm_aruser ) ,
.axi_mm_arvalid ( axi_mm_arvalid ) ,
//
// Read Data Channel
.axi_mm_rdata ( axi_mm_rdata ) ,
.axi_mm_rid ( axi_mm_rid ) ,
.axi_mm_rlast ( axi_mm_rlast ) ,
.axi_mm_rready ( axi_mm_rready ) ,
.axi_mm_rresp ( axi_mm_rresp ) ,
.axi_mm_ruser ( axi_mm_ruser ) ,
.axi_mm_rvalid ( axi_mm_rvalid ) ,
`else
.m_axis_tready ( m_axis_tready ),
.m_axis_tlast ( m_axis_tlast ),
.m_axis_tdata ( m_axis_tdata ),
.m_axis_tkeep ( m_axis_tkeep ),
.m_axis_tvalid ( m_axis_tvalid ),
.m_axis_tid ( m_axis_tid ),
.m_axis_tuser ( m_axis_tuser ),
.s_axis_tready ( s_axis_tready ),
.s_axis_tlast ( s_axis_tlast ),
.s_axis_tdata ( s_axis_tdata ),
.s_axis_tkeep ( s_axis_tkeep ),
.s_axis_tvalid ( s_axis_tvalid ),
.s_axis_tid ( s_axis_tid ),
.s_axis_tuser ( s_axis_tuser ),
`endif
//
// Host AXI-Lite slave Interface
.h_s_axi_arvalid ( lite_mmio2odma_arvalid ) ,
.h_s_axi_araddr ( lite_mmio2odma_araddr ) ,
.h_s_axi_arready ( lite_odma2mmio_arready ) ,
.h_s_axi_rvalid ( lite_odma2mmio_rvalid ) ,
.h_s_axi_rdata ( lite_odma2mmio_rdata ) ,
.h_s_axi_rresp ( lite_odma2mmio_rresp ) ,
.h_s_axi_rready ( lite_mmio2odma_rready ) ,
.h_s_axi_awvalid ( lite_mmio2odma_awvalid ) ,
.h_s_axi_awaddr ( lite_mmio2odma_awaddr ) ,
.h_s_axi_awready ( lite_odma2mmio_awready ) ,
.h_s_axi_wvalid ( lite_mmio2odma_wvalid ) ,
.h_s_axi_wdata ( lite_mmio2odma_wdata ) ,
.h_s_axi_wstrb ( lite_mmio2odma_wstrb ) ,
.h_s_axi_wready ( lite_odma2mmio_wready ) ,
.h_s_axi_bvalid ( lite_odma2mmio_bvalid ) ,
.h_s_axi_bresp ( lite_odma2mmio_bresp ) ,
.h_s_axi_bready ( lite_mmio2odma_bready ) ,
// Action AXI-Lite slave Interface
.a_s_axi_arvalid ( a_s_axi_arvalid ) ,
.a_s_axi_araddr ( a_s_axi_araddr ) ,
.a_s_axi_arready ( a_s_axi_arready ) ,
.a_s_axi_rvalid ( a_s_axi_rvalid ) ,
.a_s_axi_rdata ( a_s_axi_rdata ) ,
.a_s_axi_rresp ( a_s_axi_rresp ) ,
.a_s_axi_rready ( a_s_axi_rready ) ,
.a_s_axi_awvalid ( a_s_axi_awvalid ) ,
.a_s_axi_awaddr ( a_s_axi_awaddr ) ,
.a_s_axi_awready ( a_s_axi_awready ) ,
.a_s_axi_wvalid ( a_s_axi_wvalid ) ,
.a_s_axi_wdata ( a_s_axi_wdata ) ,
.a_s_axi_wstrb ( a_s_axi_wstrb ) ,
.a_s_axi_wready ( a_s_axi_wready ) ,
.a_s_axi_bvalid ( a_s_axi_bvalid ) ,
.a_s_axi_bresp ( a_s_axi_bresp ) ,
.a_s_axi_bready ( a_s_axi_bready ) ,
// Action AXI-Lite master Interface -------//
.a_m_axi_arvalid ( a_m_axi_arvalid ) ,
.a_m_axi_araddr ( a_m_axi_araddr ) ,
.a_m_axi_arready ( a_m_axi_arready ) ,
.a_m_axi_rvalid ( a_m_axi_rvalid ) ,
.a_m_axi_rdata ( a_m_axi_rdata ) ,
.a_m_axi_rresp ( a_m_axi_rresp ) ,
.a_m_axi_rready ( a_m_axi_rready ) ,
.a_m_axi_awvalid ( a_m_axi_awvalid ) ,
.a_m_axi_awaddr ( a_m_axi_awaddr ) ,
.a_m_axi_awready ( a_m_axi_awready ) ,
.a_m_axi_wvalid ( a_m_axi_wvalid ) ,
.a_m_axi_wdata ( a_m_axi_wdata ) ,
.a_m_axi_wstrb ( a_m_axi_wstrb ) ,
.a_m_axi_wready ( a_m_axi_wready ) ,
.a_m_axi_bvalid ( a_m_axi_bvalid ) ,
.a_m_axi_bresp ( a_m_axi_bresp ) ,
.a_m_axi_bready ( a_m_axi_bready )
) ;
`endif
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// MMIO Entity
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
mmio_wrapper mmio (
//
// Clocks & Reset
.clk_tlx ( clock_tlx ) ,
.clk_afu ( clock_afu ) ,
.rst_n ( ~reset_snap ) ,
//
// CONFIGURATION
.cfg_f1_mmio_bar0 ( cfg_f1_mmio_bar0 ) ,
.cfg_f1_mmio_bar0_mask ( cfg_f1_mmio_bar0_mask ) ,
//
// STATUS
.debug_cnt_clear ( debug_cnt_clear ) ,
.debug_tlx_cnt_cmd ( debug_tlx_cnt_cmd ) ,
.debug_tlx_cnt_rsp ( debug_tlx_cnt_rsp ) ,
.debug_tlx_cnt_retry ( debug_tlx_cnt_retry ) ,
.debug_tlx_cnt_fail ( debug_tlx_cnt_fail ) ,
.debug_tlx_cnt_xlt_pd ( debug_tlx_cnt_xlt_pd ) ,
.debug_tlx_cnt_xlt_done ( debug_tlx_cnt_xlt_done ) ,
.debug_tlx_cnt_xlt_retry ( debug_tlx_cnt_xlt_retry ) ,
.debug_axi_cnt_cmd ( debug_axi_cnt_cmd ) ,
.debug_axi_cnt_rsp ( debug_axi_cnt_rsp ) ,
.debug_buf_cnt ( debug_buf_cnt ) ,
.debug_traffic_idle ( debug_traffic_idle ) ,
.debug_tlx_idle_lim ( debug_tlx_idle_lim ) ,
.debug_axi_idle_lim ( debug_axi_idle_lim ) ,
.fir_fifo_overflow ( fir_fifo_overflow ) ,
.fir_tlx_interface ( fir_tlx_interface ) ,
//
// CONTROL
.soft_reset_brdg_odma ( soft_reset_brdg_odma ),
.soft_reset_action ( soft_reset_action ) ,
//
// TLX to AFU command
.tlx_afu_cmd_valid ( tlx_afu_cmd_valid ) ,
.tlx_afu_cmd_opcode ( tlx_afu_cmd_opcode ) ,
.tlx_afu_cmd_capptag ( tlx_afu_cmd_capptag ) ,
.tlx_afu_cmd_dl ( tlx_afu_cmd_dl ) ,
.tlx_afu_cmd_pl ( tlx_afu_cmd_pl ) ,
.tlx_afu_cmd_be ( tlx_afu_cmd_be ) ,
.tlx_afu_cmd_end ( tlx_afu_cmd_end ) ,
.tlx_afu_cmd_pa ( tlx_afu_cmd_pa ) ,
.tlx_afu_cmd_flag ( tlx_afu_cmd_flag ) ,
.tlx_afu_cmd_os ( tlx_afu_cmd_os ) ,
.afu_tlx_cmd_credit ( afu_tlx_cmd_credit ) ,
.afu_tlx_cmd_initial_credit ( afu_tlx_cmd_initial_credit ) ,
.afu_tlx_cmd_rd_req ( afu_tlx_cmd_rd_req ) ,
.afu_tlx_cmd_rd_cnt ( afu_tlx_cmd_rd_cnt ) ,
.tlx_afu_cmd_data_valid ( tlx_afu_cmd_data_valid ) ,
.tlx_afu_cmd_data_bdi ( tlx_afu_cmd_data_bdi ) ,
.tlx_afu_cmd_data_bus ( tlx_afu_cmd_data_bus ) ,
//
// AFU to TLX response
.afu_tlx_resp_valid ( afu_tlx_resp_valid ) ,
.afu_tlx_resp_opcode ( afu_tlx_resp_opcode ) ,
.afu_tlx_resp_dl ( afu_tlx_resp_dl ) ,
.afu_tlx_resp_capptag ( afu_tlx_resp_capptag ) ,
.afu_tlx_resp_dp ( afu_tlx_resp_dp ) ,
.afu_tlx_resp_code ( afu_tlx_resp_code ) ,
.afu_tlx_rdata_valid ( afu_tlx_rdata_valid ) ,
.afu_tlx_rdata_bdi ( afu_tlx_rdata_bdi ) ,
.afu_tlx_rdata_bus ( afu_tlx_rdata_bus ) ,
.tlx_afu_resp_credit ( tlx_afu_resp_credit ) ,
.tlx_afu_resp_data_credit ( tlx_afu_resp_data_credit ) ,
.tlx_afu_resp_initial_credit ( tlx_afu_resp_initial_credit ) ,
.tlx_afu_resp_data_initial_credit ( tlx_afu_resp_data_initial_credit ) ,
//
`ifndef ENABLE_ODMA
// AXI Lite write
.m_axi_awready ( lite_conv2snap_awready ) ,
.m_axi_awaddr ( lite_snap2conv_awaddr ) ,
.m_axi_awprot ( lite_snap2conv_awprot ) ,
.m_axi_awvalid ( lite_snap2conv_awvalid ) ,
.m_axi_wready ( lite_conv2snap_wready ) ,
.m_axi_wdata ( lite_snap2conv_wdata ) ,
.m_axi_wstrb ( lite_snap2conv_wstrb ) ,
.m_axi_wvalid ( lite_snap2conv_wvalid ) ,
.m_axi_bresp ( lite_conv2snap_bresp ) ,
.m_axi_bvalid ( lite_conv2snap_bvalid ) ,
.m_axi_bready ( lite_snap2conv_bready ) ,
// AXI Lite read
.m_axi_arready ( lite_conv2snap_arready ) ,
.m_axi_arvalid ( lite_snap2conv_arvalid ) ,
.m_axi_araddr ( lite_snap2conv_araddr ) ,
.m_axi_arprot ( lite_snap2conv_arprot ) ,
.m_axi_rdata ( lite_conv2snap_rdata ) ,
.m_axi_rresp ( lite_conv2snap_rresp ) ,
.m_axi_rready ( lite_snap2conv_rready ) ,
.m_axi_rvalid ( lite_conv2snap_rvalid )
`else
// AXI Lite write
.m_axi_awready ( lite_odma2mmio_awready ) ,
.m_axi_awaddr ( lite_mmio2odma_awaddr ) ,
.m_axi_awprot ( lite_mmio2odma_awprot ) ,
.m_axi_awvalid ( lite_mmio2odma_awvalid ) ,
.m_axi_wready ( lite_odma2mmio_wready ) ,
.m_axi_wdata ( lite_mmio2odma_wdata ) ,
.m_axi_wstrb ( lite_mmio2odma_wstrb ) ,
.m_axi_wvalid ( lite_mmio2odma_wvalid ) ,
.m_axi_bresp ( lite_odma2mmio_bresp ) ,
.m_axi_bvalid ( lite_odma2mmio_bvalid ) ,
.m_axi_bready ( lite_mmio2odma_bready ) ,
// AXI Lite read
.m_axi_arready ( lite_odma2mmio_arready ) ,
.m_axi_arvalid ( lite_mmio2odma_arvalid ) ,
.m_axi_araddr ( lite_mmio2odma_araddr ) ,
.m_axi_arprot ( lite_mmio2odma_arprot ) ,
.m_axi_rdata ( lite_odma2mmio_rdata ) ,
.m_axi_rresp ( lite_odma2mmio_rresp ) ,
.m_axi_rready ( lite_mmio2odma_rready ) ,
.m_axi_rvalid ( lite_odma2mmio_rvalid )
`endif
) ; // mmio_wrapper
assign brdg_odma_rst_n = ~(soft_reset_brdg_odma || reset_snap);
endmodule |
module oc_function (
// -----------------------------------
// Miscellaneous Ports
// -----------------------------------
input clock_tlx
, input clock_afu
, input reset
, input decouple
, input ocde //connected from top-level port
, output ocde_to_bsp_dcpl
// Bus number comes from CFG_SEQ
, input [7:0] cfg_bus // Extracted from config_write command
// Hardcoded configuration inputs
, input [4:0] ro_device // Passed down from *_device.v
, input [2:0] ro_function // Assigned in *_device.v for this function instantiation
// -----------------------------------
// TLX Parser -> AFU Receive Interface
// -----------------------------------
, input tlx_afu_ready // When 1, TLX is ready to receive both commands and responses from the AFU
// Command interface to AFU
, output [ 6:0] afu_tlx_cmd_initial_credit // (static) Number of cmd credits available for TLX to use in the AFU
, output afu_tlx_cmd_credit // Returns a cmd credit to the TLX
, input tlx_afu_cmd_valid // Indicates TLX has a valid cmd for AFU to process
, input [ 7:0] tlx_afu_cmd_opcode // (w/cmd_valid) Cmd Opcode
, input [ 1:0] tlx_afu_cmd_dl // (w/cmd_valid) Cmd Data Length (00=rsvd, 01=64B, 10=128B, 11=256B)
, input tlx_afu_cmd_end // (w/cmd_valid) Operand Endian-ess
, input [ 63:0] tlx_afu_cmd_pa // (w/cmd_valid) Physical Address
, input [ 3:0] tlx_afu_cmd_flag // (w/cmd_valid) Specifies atomic memory operation (unsupported)
, input tlx_afu_cmd_os // (w/cmd_valid) Ordered Segment - 1 means ordering is guaranteed (unsupported)
, input [ 15:0] tlx_afu_cmd_capptag // (w/cmd_valid) Unique operation tag from CAPP unit
, input [ 2:0] tlx_afu_cmd_pl // (w/cmd_valid) Partial Length (000=1B,001=2B,010=4B,011=8B,100=16B,101=32B,110/111=rsvd)
, input [ 63:0] tlx_afu_cmd_be // (w/cmd_valid) Byte Enable
// Response interface to AFU
, output [ 6:0] afu_tlx_resp_initial_credit // (static) Number of resp credits available for TLX to use in the AFU
, output afu_tlx_resp_credit // Returns a resp credit to the TLX
, input tlx_afu_resp_valid // Indicates TLX has a valid resp for AFU to process
, input [ 7:0] tlx_afu_resp_opcode // (w/resp_valid) Resp Opcode
, input [ 15:0] tlx_afu_resp_afutag // (w/resp_valid) Resp Tag
, input [ 3:0] tlx_afu_resp_code // (w/resp_valid) Describes the reason for a failed transaction
, input [ 5:0] tlx_afu_resp_pg_size // (w/resp_valid) Page size
, input [ 1:0] tlx_afu_resp_dl // (w/resp_valid) Resp Data Length (00=rsvd, 01=64B, 10=128B, 11=256B)
, input [ 1:0] tlx_afu_resp_dp // (w/resp_valid) Data Part, indicates the data content of the current resp packet
, input [ 23:0] tlx_afu_resp_host_tag // (w/resp_valid) Tag for data held in AFU L1 (unsupported, CAPI 4.0 feature)
, input [ 3:0] tlx_afu_resp_cache_state // (w/resp_valid) Gives cache state of cache line obtained
, input [ 17:0] tlx_afu_resp_addr_tag // (w/resp_valid) Address translation tag for use by AFU with dot-t format commands
// Command data interface to AFU
, output afu_tlx_cmd_rd_req // Command Read Request
, output [ 2:0] afu_tlx_cmd_rd_cnt // Command Read Count, number of 64B flits requested (000 is not useful)
, input tlx_afu_cmd_data_valid // Command Data Valid, when 1 valid data is present on cmd_data_bus
, input tlx_afu_cmd_data_bdi // (w/cmd_data_valid) Bad Data Indicator, when 1 data FLIT is corrupted
, input [511:0] tlx_afu_cmd_data_bus // (w/cmd_data_valid) Command Data Bus, contains the command for the AFU to process
// Response data interface to AFU
, output afu_tlx_resp_rd_req // Response Read Request
, output [ 2:0] afu_tlx_resp_rd_cnt // Response Read Count, number of 64B flits requested (000 is not useful)
, input tlx_afu_resp_data_valid // Response Valid, when 1 valid data is present on resp_data
, input tlx_afu_resp_data_bdi // (w/resp_data_valid) Bad Data Indicator, when 1 data FLIT is corrupted
, input [511:0] tlx_afu_resp_data_bus // (w/resp_data_valid) Response Data, contains data for a read request
// ------------------------------------
// AFU -> TLX Framer Transmit Interface
// ------------------------------------
// Initial credit allocation
// , input [ 2:0] tlx_afu_cmd_resp_initial_credit // Number of starting credits from TLX for both AFU->TLX cmd and resp interfaces
// , input [ 4:0] tlx_afu_data_initial_credit // Number of starting credits from TLX for both AFU->TLX cmd and resp data interfaces
, input [ 3:0] tlx_afu_cmd_initial_credit // Number of starting credits from TLX for AFU->TLX cmd interface
, input [ 3:0] tlx_afu_resp_initial_credit // Number of starting credits from TLX for AFU->TLX resp interface
, input [ 5:0] tlx_afu_cmd_data_initial_credit // Number of starting credits from TLX for both AFU->TLX cmd data interface
, input [ 5:0] tlx_afu_resp_data_initial_credit // Number of starting credits from TLX for both AFU->TLX resp data interface
// Commands from AFU
, input tlx_afu_cmd_credit
, output afu_tlx_cmd_valid
, output [ 7:0] afu_tlx_cmd_opcode
, output [ 11:0] afu_tlx_cmd_actag
, output [ 3:0] afu_tlx_cmd_stream_id
, output [ 67:0] afu_tlx_cmd_ea_or_obj
, output [ 15:0] afu_tlx_cmd_afutag
, output [ 1:0] afu_tlx_cmd_dl
, output [ 2:0] afu_tlx_cmd_pl
, output afu_tlx_cmd_os
, output [ 63:0] afu_tlx_cmd_be
, output [ 3:0] afu_tlx_cmd_flag
, output afu_tlx_cmd_endian
, output [ 15:0] afu_tlx_cmd_bdf // BDF = Concatenation of 8 bit Bus Number, 5 bit Device Number, and 3 bit Function
, output [ 19:0] afu_tlx_cmd_pasid
, output [ 5:0] afu_tlx_cmd_pg_size
// Command data from AFU
, input tlx_afu_cmd_data_credit
, output afu_tlx_cdata_valid
, output [511:0] afu_tlx_cdata_bus
, output afu_tlx_cdata_bdi // When 1, marks command data associated with AFU->host command as bad
// Responses from AFU
, input tlx_afu_resp_credit
, output afu_tlx_resp_valid
, output [ 7:0] afu_tlx_resp_opcode
, output [ 1:0] afu_tlx_resp_dl
, output [ 15:0] afu_tlx_resp_capptag
, output [ 1:0] afu_tlx_resp_dp
, output [ 3:0] afu_tlx_resp_code
// Response data from AFU
, input tlx_afu_resp_data_credit
, output afu_tlx_rdata_valid
, output [511:0] afu_tlx_rdata_bus
, output afu_tlx_rdata_bdi // When 1, marks response data associated with AFU's reply to Host->AFU cmd as bad
// -------------------------------------------------------------
// Configuration Sequencer Interface [CFG_SEQ -> CFG_Fn (n=1-7)]
// -------------------------------------------------------------
, input [2:0] cfg_function
, input [1:0] cfg_portnum
, input [11:0] cfg_addr
, input [31:0] cfg_wdata
, output [31:0] cfg_f1_rdata
, output cfg_f1_rdata_vld
, input cfg_wr_1B
, input cfg_wr_2B
, input cfg_wr_4B
, input cfg_rd
, output cfg_f1_bad_op_or_align
, output cfg_f1_addr_not_implemented
// ------------------------------------
// Other signals
// ------------------------------------
// Fence control
, output cfg_f1_octrl00_fence_afu
// TLX Configuration for the TLX port(s) connected to AFUs under this Function
, input [3:0] cfg_f0_otl0_long_backoff_timer
, input [3:0] cfg_f0_otl0_short_backoff_timer
// Error signals into MMIO capture register
, input vpd_err_unimplemented_addr
, input cfg0_cff_fifo_overflow
, input cfg1_cff_fifo_overflow
, input cfg0_rff_fifo_overflow
, input cfg1_rff_fifo_overflow
, input [127:0] cfg_errvec
, input cfg_errvec_valid
// Resync credits control
, output cfg_f1_octrl00_resync_credits
//cfg tieoff files
,input [31:0] f1_csh_expansion_rom_bar
,input [15:0] f1_csh_subsystem_id
,input [15:0] f1_csh_subsystem_vendor_id
,input [63:0] f1_csh_mmio_bar0_size
,input [63:0] f1_csh_mmio_bar1_size
,input [63:0] f1_csh_mmio_bar2_size
,input f1_csh_mmio_bar0_prefetchable
,input f1_csh_mmio_bar1_prefetchable
,input f1_csh_mmio_bar2_prefetchable
,input [4:0] f1_pasid_max_pasid_width
,input [7:0] f1_ofunc_reset_duration
,input f1_ofunc_afu_present
,input [4:0] f1_ofunc_max_afu_index
,input [7:0] f1_octrl00_reset_duration
,input [5:0] f1_octrl00_afu_control_index
,input [4:0] f1_octrl00_pasid_len_supported
,input f1_octrl00_metadata_supported
,input [11:0] f1_octrl00_actag_len_supported
`ifdef ENABLE_DDR
`ifdef AD9V3
// DDR4 SDRAM Interface
// , output [511:0] dbg_bus //Unused
, input c0_sys_clk_p
, input c0_sys_clk_n
, output [16 : 0] c0_ddr4_adr
, output [1 : 0] c0_ddr4_ba
, output [0 : 0] c0_ddr4_cke
, output [0 : 0] c0_ddr4_cs_n
, inout [8 : 0] c0_ddr4_dm_dbi_n
, inout [71 : 0] c0_ddr4_dq
, inout [8 : 0] c0_ddr4_dqs_c
, inout [8 : 0] c0_ddr4_dqs_t
, output [0 : 0] c0_ddr4_odt
, output [1 : 0] c0_ddr4_bg
, output c0_ddr4_reset_n
, output c0_ddr4_act_n
, output [0 : 0] c0_ddr4_ck_c
, output [0 : 0] c0_ddr4_ck_t
`endif
`ifdef BW250SOC
// DDR4 SDRAM Interface
// , output [511:0] dbg_bus //Unused
, input c0_sys_clk_p
, input c0_sys_clk_n
, output [16 : 0] c0_ddr4_adr
, output [1 : 0] c0_ddr4_ba
, output [0 : 0] c0_ddr4_cke
, output [0 : 0] c0_ddr4_cs_n
, inout [8 : 0] c0_ddr4_dm_dbi_n
, inout [71 : 0] c0_ddr4_dq
, inout [8 : 0] c0_ddr4_dqs_c
, inout [8 : 0] c0_ddr4_dqs_t
, output [0 : 0] c0_ddr4_odt
, output [0 : 0] c0_ddr4_bg
, output c0_ddr4_reset_n
, output c0_ddr4_act_n
, output [0 : 0] c0_ddr4_ck_c
, output [0 : 0] c0_ddr4_ck_t
`endif
`endif
`ifdef ENABLE_ETHERNET
`ifndef ENABLE_ETH_LOOP_BACK
, input gt_ref_clk_n
, input gt_ref_clk_p
, input gt_rx_gt_port_0_n
, input gt_rx_gt_port_0_p
, input gt_rx_gt_port_1_n
, input gt_rx_gt_port_1_p
, input gt_rx_gt_port_2_n
, input gt_rx_gt_port_2_p
, input gt_rx_gt_port_3_n
, input gt_rx_gt_port_3_p
, output gt_tx_gt_port_0_n
, output gt_tx_gt_port_0_p
, output gt_tx_gt_port_1_n
, output gt_tx_gt_port_1_p
, output gt_tx_gt_port_2_n
, output gt_tx_gt_port_2_p
, output gt_tx_gt_port_3_n
, output gt_tx_gt_port_3_p
`endif
`endif
`ifdef ENABLE_9H3_LED
, output user_led_a0
, output user_led_a1
, output user_led_g0
, output user_led_g1
`endif
`ifdef ENABLE_9H3_EEPROM
, inout eeprom_scl
, inout eeprom_sda
, output eeprom_wp
`endif
`ifdef ENABLE_9H3_AVR
, input avr_rx
, output avr_tx
, input avr_ck
`endif
);
// ==============================================================================================================================
// @@@ SIG: Internal signals
// ==============================================================================================================================
// Interface to AFU Descriptor table (interface is Read Only)
wire [5:0] cfg_desc_afu_index
; wire [30:0] cfg_desc_offset
; wire cfg_desc_cmd_valid
; wire [31:0] desc_cfg_data
; wire desc_cfg_data_valid
; wire desc_cfg_echo_cmd_valid
; wire [31:0] desc0_cfg_data
; wire desc0_cfg_data_valid
; wire desc0_cfg_echo_cmd_valid
// Between other modules in the file
; wire reset_afu00
; wire resync_credits_afu00
;
//Cfg tieoffs
wire [31:0] f1_ro_csh_expansion_rom_bar ;
wire [15:0] f1_ro_csh_subsystem_id ;
wire [15:0] f1_ro_csh_subsystem_vendor_id ;
wire [63:0] f1_ro_csh_mmio_bar0_size ;
wire [63:0] f1_ro_csh_mmio_bar1_size ;
wire [63:0] f1_ro_csh_mmio_bar2_size ;
wire f1_ro_csh_mmio_bar0_prefetchable ;
wire f1_ro_csh_mmio_bar1_prefetchable ;
wire f1_ro_csh_mmio_bar2_prefetchable ;
wire [4:0] f1_ro_pasid_max_pasid_width ;
wire [7:0] f1_ro_ofunc_reset_duration ;
wire f1_ro_ofunc_afu_present ;
wire [4:0] f1_ro_ofunc_max_afu_index ;
wire [7:0] f1_ro_octrl00_reset_duration ;
wire [5:0] f1_ro_octrl00_afu_control_index ;
wire [4:0] f1_ro_octrl00_pasid_len_supported ;
wire f1_ro_octrl00_metadata_supported ;
wire [11:0] f1_ro_octrl00_actag_len_supported ;
assign f1_ro_csh_expansion_rom_bar = f1_csh_expansion_rom_bar ;
assign f1_ro_csh_subsystem_id = f1_csh_subsystem_id ;
assign f1_ro_csh_subsystem_vendor_id = f1_csh_subsystem_vendor_id ;
assign f1_ro_csh_mmio_bar0_size = f1_csh_mmio_bar0_size ;
assign f1_ro_csh_mmio_bar1_size = f1_csh_mmio_bar1_size ;
assign f1_ro_csh_mmio_bar2_size = f1_csh_mmio_bar2_size ;
assign f1_ro_csh_mmio_bar0_prefetchable = f1_csh_mmio_bar0_prefetchable ;
assign f1_ro_csh_mmio_bar1_prefetchable = f1_csh_mmio_bar1_prefetchable ;
assign f1_ro_csh_mmio_bar2_prefetchable = f1_csh_mmio_bar2_prefetchable ;
assign f1_ro_pasid_max_pasid_width = f1_pasid_max_pasid_width ;
assign f1_ro_ofunc_reset_duration = f1_ofunc_reset_duration ;
assign f1_ro_ofunc_afu_present = f1_ofunc_afu_present ;
assign f1_ro_ofunc_max_afu_index = f1_ofunc_max_afu_index ;
assign f1_ro_octrl00_reset_duration = f1_octrl00_reset_duration ;
assign f1_ro_octrl00_afu_control_index = f1_octrl00_afu_control_index ;
assign f1_ro_octrl00_pasid_len_supported = f1_octrl00_pasid_len_supported;
assign f1_ro_octrl00_metadata_supported = f1_octrl00_metadata_supported ;
assign f1_ro_octrl00_actag_len_supported = f1_octrl00_actag_len_supported;
// ==============================================================================================================================
// @@@ CFG_F1: Function 1 Capability Structures (controls AFU)
// ==============================================================================================================================
// Signals from AFU
wire afu_f1_cfg_terminate_in_progress // CFG_F1 input
// Declare F1 outputs
; wire cfg_f1_csh_memory_space
; wire [63:0] cfg_f1_csh_mmio_bar0
; wire [63:0] cfg_f1_csh_mmio_bar1
; wire [63:0] cfg_f1_csh_mmio_bar2
; wire [31:0] cfg_f1_csh_expansion_ROM_bar
; wire cfg_f1_csh_expansion_ROM_enable
; wire cfg_f1_ofunc_function_reset
; wire [11:0] cfg_f1_ofunc_func_actag_base
; wire [11:0] cfg_f1_ofunc_func_actag_len_enab
; wire [5:0] cfg_f1_octrl00_afu_control_index
; wire [3:0] cfg_f1_octrl00_afu_unique
//; wire cfg_f1_octrl00_fence_afu Move to 'output'
; wire cfg_f1_octrl00_enable_afu
; wire cfg_f1_octrl00_reset_afu
; wire cfg_f1_octrl00_terminate_valid
; wire [19:0] cfg_f1_octrl00_terminate_pasid
; wire [4:0] cfg_f1_octrl00_pasid_length_enabled
; wire cfg_f1_octrl00_metadata_enabled
; wire [2:0] cfg_f1_octrl00_host_tag_run_length
; wire [19:0] cfg_f1_octrl00_pasid_base
; wire [11:0] cfg_f1_octrl00_afu_actag_len_enab
; wire [11:0] cfg_f1_octrl00_afu_actag_base
;
wire cfg_f1_reset;
assign cfg_f1_reset = (reset == 1'b1 || cfg_f1_ofunc_function_reset == 1'b1) ? 1'b1 : 1'b0; // Apply on hardware reset OR software cmd (Function Reset)
cfg_func1 cfg_f1
(
// -- Clocks & Reset
.clock ( clock_tlx ), // -- input
.reset ( cfg_f1_reset ), // -- input
.device_reset ( reset ), // -- input
// -- READ ONLY field inputs
// -- Configuration Space Header
.cfg_ro_csh_device_id ( 16'h062B ), // -- input
.cfg_ro_csh_vendor_id ( 16'h1014 ), // -- input
.cfg_ro_csh_class_code ( 24'h120000 ), // -- input
.cfg_ro_csh_revision_id ( 8'h00 ), // -- input
.cfg_ro_csh_multi_function ( 1'b1 ), // -- input
.cfg_ro_csh_mmio_bar0_size ( f1_ro_csh_mmio_bar0_size ), // -- input // -- [63:n+1]=1, [n:0]=0 to indicate MMIO region size (default 64 MB)
.cfg_ro_csh_mmio_bar1_size ( f1_ro_csh_mmio_bar1_size ), // -- input // -- [63:n+1]=1, [n:0]=0 to indicate MMIO region size (default 0 MB)
.cfg_ro_csh_mmio_bar2_size ( f1_ro_csh_mmio_bar2_size ), // -- input // -- [63:n+1]=1, [n:0]=0 to indicate MMIO region size (default 0 MB)
.cfg_ro_csh_mmio_bar0_prefetchable ( f1_ro_csh_mmio_bar0_prefetchable ), // -- input
.cfg_ro_csh_mmio_bar1_prefetchable ( f1_ro_csh_mmio_bar1_prefetchable ), // -- input
.cfg_ro_csh_mmio_bar2_prefetchable ( f1_ro_csh_mmio_bar2_prefetchable ), // -- input
.cfg_ro_csh_subsystem_id ( f1_ro_csh_subsystem_id ), // -- input
.cfg_ro_csh_subsystem_vendor_id ( f1_ro_csh_subsystem_vendor_id ), // -- input
.cfg_ro_csh_expansion_rom_bar ( f1_ro_csh_expansion_rom_bar ), // -- input // -- Only [31:11] are used
// -- PASID
.cfg_ro_pasid_max_pasid_width ( f1_ro_pasid_max_pasid_width ), // -- input // -- Default is 512 PASIDs
// -- Function
.cfg_ro_ofunc_reset_duration ( f1_ro_ofunc_reset_duration ), // -- input // -- Number of cycles Function reset is active (00=256 cycles)
.cfg_ro_ofunc_afu_present ( f1_ro_ofunc_afu_present ), // -- input // -- Func0=0, FuncN=1 (likely)
.cfg_ro_ofunc_max_afu_index ( f1_ro_ofunc_max_afu_index ), // -- input // -- Default is AFU number 0
// -- AFU 0 Control
.cfg_ro_octrl00_reset_duration ( f1_ro_octrl00_reset_duration ), // -- input // -- Number of cycles AFU reset is active (00=256 cycles)
.cfg_ro_octrl00_afu_control_index ( f1_ro_octrl00_afu_control_index ), // -- input // -- Control structure for AFU Index 0
.cfg_ro_octrl00_pasid_len_supported ( f1_ro_octrl00_pasid_len_supported ), // -- input // -- Default is 512 PASID
.cfg_ro_octrl00_metadata_supported ( f1_ro_octrl00_metadata_supported ), // -- input // -- MetaData is not supported
.cfg_ro_octrl00_actag_len_supported ( f1_ro_octrl00_actag_len_supported ), // -- input // -- Default is 32 acTags
// -- Assigned configuration values
.cfg_ro_function ( ro_function ), // -- input
// -- Functional interface
.cfg_function ( cfg_function[2:0] ), // -- input // -- Targeted Function
.cfg_portnum ( cfg_portnum[1:0] ), // -- input // -- Targeted TLX port
.cfg_addr ( cfg_addr[11:0] ), // -- input // -- Target address for the read or write access
.cfg_wdata ( cfg_wdata[31:0] ), // -- input // -- Write data into selected config reg
.cfg_rdata ( cfg_f1_rdata[31:0] ), // -- output // -- Read data from selected config reg
.cfg_rdata_vld ( cfg_f1_rdata_vld ), // -- output // -- When observed in the proper cycle, indicates if cfg_rdata has valid information
.cfg_wr_1B ( cfg_wr_1B ), // -- input // -- When 1, triggers a write operation of 1 byte (cfg_addr[1:0] selects byte)
.cfg_wr_2B ( cfg_wr_2B ), // -- input // -- When 1, triggers a write operation of 2 bytes (cfg_addr[1] selects starting byte)
.cfg_wr_4B ( cfg_wr_4B ), // -- input // -- When 1, triggers a write operation of all 4 bytes
.cfg_rd ( cfg_rd ), // -- input // -- When 1, triggers a read operation that returns all 4 bytes of data from the reg
.cfg_bad_op_or_align ( cfg_f1_bad_op_or_align ), // -- output // -- Pulsed when multiple write/read strobes are active or writes are not naturally aligned
.cfg_addr_not_implemented ( cfg_f1_addr_not_implemented ), // -- output // -- Pulsed when address provided is not implemented within the ACS space
// -- Inputs defined by active AFU logic
.cfg_octrl00_terminate_in_progress ( afu_f1_cfg_terminate_in_progress ), // -- input // -- When 1, a PASID is in the process of being terminated (set to 1 immediately after 'terminate valid')
// -- Individual fields from configuration registers
// -- CSH
.cfg_csh_memory_space ( cfg_f1_csh_memory_space ), // -- output
.cfg_csh_mmio_bar0 ( cfg_f1_csh_mmio_bar0[63:0] ), // -- output
.cfg_csh_mmio_bar1 ( cfg_f1_csh_mmio_bar1[63:0] ), // -- output // -- Unused
.cfg_csh_mmio_bar2 ( cfg_f1_csh_mmio_bar2[63:0] ), // -- output // -- Unused
.cfg_csh_expansion_ROM_bar ( cfg_f1_csh_expansion_ROM_bar[31:0] ), // -- output // -- Unused
.cfg_csh_expansion_ROM_enable ( cfg_f1_csh_expansion_ROM_enable ), // -- output // -- Unused
// -- OFUNC
.cfg_ofunc_function_reset ( cfg_f1_ofunc_function_reset ), // -- output // -- When 1, reset this Function
.cfg_ofunc_func_actag_base ( cfg_f1_ofunc_func_actag_base[11:0] ), // -- output
.cfg_ofunc_func_actag_len_enab ( cfg_f1_ofunc_func_actag_len_enab[11:0] ), // -- output
// -- OCTRL
.cfg_octrl00_afu_control_index ( cfg_f1_octrl00_afu_control_index[5:0] ), // -- output // -- AFU number that other octrl signals refer to (control 1 AFU at a time)
.cfg_octrl00_afu_unique ( cfg_f1_octrl00_afu_unique[3:0] ), // -- output // -- Each AFU can assign a use to this (OCTRL, h0C, bit [31:28])
.cfg_octrl00_fence_afu ( cfg_f1_octrl00_fence_afu ), // -- output // -- When 1, isolate the selected AFU from all other units (likely in preparation for re-configuring it)
.cfg_octrl00_enable_afu ( cfg_f1_octrl00_enable_afu ), // -- output // -- When 1, the selected AFU can initiate commands to the host
.cfg_octrl00_reset_afu ( cfg_f1_octrl00_reset_afu ), // -- output // -- When 1, reset the selected AFU
.cfg_octrl00_terminate_valid ( cfg_f1_octrl00_terminate_valid ), // -- output // -- When 1, terminate the specified PASID process
.cfg_octrl00_terminate_pasid ( cfg_f1_octrl00_terminate_pasid[19:0] ), // -- output // -- Which PASID 'terminate valid' applies to
.cfg_octrl00_pasid_length_enabled ( cfg_f1_octrl00_pasid_length_enabled[4:0] ), // -- output
.cfg_octrl00_metadata_enabled ( cfg_f1_octrl00_metadata_enabled ), // -- output
.cfg_octrl00_host_tag_run_length ( cfg_f1_octrl00_host_tag_run_length[2:0] ), // -- output
.cfg_octrl00_pasid_base ( cfg_f1_octrl00_pasid_base[19:0] ), // -- output
.cfg_octrl00_afu_actag_base ( cfg_f1_octrl00_afu_actag_base[11:0] ), // -- output
.cfg_octrl00_afu_actag_len_enab ( cfg_f1_octrl00_afu_actag_len_enab[11:0] ), // -- output
// -- Interface to AFU Descriptor table (interface is Read Only)
.cfg_desc_afu_index ( cfg_desc_afu_index[5:0] ), // -- output
.cfg_desc_offset ( cfg_desc_offset[30:0] ), // -- output
.cfg_desc_cmd_valid ( cfg_desc_cmd_valid ), // -- output
.desc_cfg_data ( desc_cfg_data[31:0] ), // -- input
.desc_cfg_data_valid ( desc_cfg_data_valid ), // -- input
.desc_cfg_echo_cmd_valid ( desc_cfg_echo_cmd_valid ) // -- input
);
// Combine Descriptor outputs before sending into Config Space
// When used with multiple descriptors representing multiple AFUs, connect the inputs thusly at the next level up:
// (into afu_config_space.v) = (out of DESC0 instance) (out of DESC1 instance) (out of other DESC instances)
assign desc_cfg_echo_cmd_valid = desc0_cfg_echo_cmd_valid ; // & desc1_cfg_echo_cmd_valid & ... ;
assign desc_cfg_data_valid = desc0_cfg_data_valid ; // | desc1_cfg_data_valid | ... ;
assign desc_cfg_data = desc0_cfg_data ; // | desc1_cfg_data | ... ;
// Resync credits control
assign cfg_f1_octrl00_resync_credits = cfg_f1_octrl00_afu_unique[0]; // Assign AFU Unique[0] as resync_credits signal
assign resync_credits_afu00 = cfg_f1_octrl00_afu_unique[0]; // Make a copy for internal use, as get Warning when an output as an input
// Set AFU reset on either: card reset OR function reset OR software reset to AFU 0
assign reset_afu00 = ( reset == 1'b1 ||
cfg_f1_reset == 1'b1 ||
(cfg_f1_octrl00_reset_afu == 1'b1 && cfg_f1_octrl00_afu_control_index == 6'b000000) ) ? 1'b1 : 1'b0;
wire afu_tlx_fatal_error; //MF currently unconnected
framework_afu fw_afu
(
// -- Clocks & Reset
.clock_tlx ( clock_tlx), // -- input
.clock_afu ( clock_afu ), // -- input
.reset ( reset_afu00 ), // -- input
.decouple ( decouple ), // -- input
.ocde ( ocde ), //connected from top-level port
.ocde_to_bsp_dcpl ( ocde_to_bsp_dcpl ),
`ifdef ENABLE_DDR
`ifdef AD9V3
// DDR4 SDRAM Interface
.c0_sys_clk_p ( c0_sys_clk_p ) ,
.c0_sys_clk_n ( c0_sys_clk_n ) ,
.c0_ddr4_adr ( c0_ddr4_adr ) ,
.c0_ddr4_ba ( c0_ddr4_ba ) ,
.c0_ddr4_cke ( c0_ddr4_cke ) ,
.c0_ddr4_cs_n ( c0_ddr4_cs_n ) ,
.c0_ddr4_dm_dbi_n ( c0_ddr4_dm_dbi_n ) ,
.c0_ddr4_dq ( c0_ddr4_dq ) ,
.c0_ddr4_dqs_c ( c0_ddr4_dqs_c ) ,
.c0_ddr4_dqs_t ( c0_ddr4_dqs_t ) ,
.c0_ddr4_odt ( c0_ddr4_odt ) ,
.c0_ddr4_bg ( c0_ddr4_bg ) ,
.c0_ddr4_reset_n ( c0_ddr4_reset_n ) ,
.c0_ddr4_act_n ( c0_ddr4_act_n ) ,
.c0_ddr4_ck_c ( c0_ddr4_ck_c ) ,
.c0_ddr4_ck_t ( c0_ddr4_ck_t ) ,
`endif
`ifdef BW250SOC
// DDR4 SDRAM Interface
.c0_sys_clk_p ( c0_sys_clk_p ) ,
.c0_sys_clk_n ( c0_sys_clk_n ) ,
.c0_ddr4_adr ( c0_ddr4_adr ) ,
.c0_ddr4_ba ( c0_ddr4_ba ) ,
.c0_ddr4_cke ( c0_ddr4_cke ) ,
.c0_ddr4_cs_n ( c0_ddr4_cs_n ) ,
.c0_ddr4_dm_dbi_n ( c0_ddr4_dm_dbi_n ) ,
.c0_ddr4_dq ( c0_ddr4_dq ) ,
.c0_ddr4_dqs_c ( c0_ddr4_dqs_c ) ,
.c0_ddr4_dqs_t ( c0_ddr4_dqs_t ) ,
.c0_ddr4_odt ( c0_ddr4_odt ) ,
.c0_ddr4_bg ( c0_ddr4_bg ) ,
.c0_ddr4_reset_n ( c0_ddr4_reset_n ) ,
.c0_ddr4_act_n ( c0_ddr4_act_n ) ,
.c0_ddr4_ck_c ( c0_ddr4_ck_c ) ,
.c0_ddr4_ck_t ( c0_ddr4_ck_t ) ,
`endif
`endif
`ifdef ENABLE_ETHERNET
`ifndef ENABLE_ETH_LOOP_BACK
.gt_ref_clk_n ( gt_ref_clk_n ),
.gt_ref_clk_p ( gt_ref_clk_p ),
.gt_rx_gt_port_0_n ( gt_rx_gt_port_0_n ),
.gt_rx_gt_port_0_p ( gt_rx_gt_port_0_p ),
.gt_rx_gt_port_1_n ( gt_rx_gt_port_1_n ),
.gt_rx_gt_port_1_p ( gt_rx_gt_port_1_p ),
.gt_rx_gt_port_2_n ( gt_rx_gt_port_2_n ),
.gt_rx_gt_port_2_p ( gt_rx_gt_port_2_p ),
.gt_rx_gt_port_3_n ( gt_rx_gt_port_3_n ),
.gt_rx_gt_port_3_p ( gt_rx_gt_port_3_p ),
.gt_tx_gt_port_0_n ( gt_tx_gt_port_0_n ),
.gt_tx_gt_port_0_p ( gt_tx_gt_port_0_p ),
.gt_tx_gt_port_1_n ( gt_tx_gt_port_1_n ),
.gt_tx_gt_port_1_p ( gt_tx_gt_port_1_p ),
.gt_tx_gt_port_2_n ( gt_tx_gt_port_2_n ),
.gt_tx_gt_port_2_p ( gt_tx_gt_port_2_p ),
.gt_tx_gt_port_3_n ( gt_tx_gt_port_3_n ),
.gt_tx_gt_port_3_p ( gt_tx_gt_port_3_p ),
`endif
`endif
`ifdef ENABLE_9H3_LED
.user_led_a0 ( user_led_a0 ),
.user_led_a1 ( user_led_a1 ),
.user_led_g0 ( user_led_g0 ),
.user_led_g1 ( user_led_g1 ),
`endif
`ifdef ENABLE_9H3_EEPROM
.eeprom_scl (eeprom_scl ),
.eeprom_sda (eeprom_sda ),
.eeprom_wp (eeprom_wp ),
`endif
`ifdef ENABLE_9H3_AVR
.avr_rx (avr_rx ),
.avr_tx (avr_tx ),
.avr_ck (avr_ck ),
`endif
// -- AFU Index
.afu_index ( 6'b000000 ), // -- input // -- This AFU is number 0
// -- TLX_AFU command receive interface
.tlx_afu_ready ( tlx_afu_ready ), // -- input
.tlx_afu_cmd_valid ( tlx_afu_cmd_valid ), // -- input
.tlx_afu_cmd_opcode ( tlx_afu_cmd_opcode[7:0] ), // -- input
.tlx_afu_cmd_capptag ( tlx_afu_cmd_capptag[15:0] ), // -- input
.tlx_afu_cmd_dl ( tlx_afu_cmd_dl[1:0] ), // -- input
.tlx_afu_cmd_pl ( tlx_afu_cmd_pl[2:0] ), // -- input
.tlx_afu_cmd_be ( tlx_afu_cmd_be[63:0] ), // -- input
.tlx_afu_cmd_end ( tlx_afu_cmd_end ), // -- input
.tlx_afu_cmd_pa ( tlx_afu_cmd_pa[63:0] ), // -- input
.tlx_afu_cmd_flag ( tlx_afu_cmd_flag[3:0] ), // -- input
.tlx_afu_cmd_os ( tlx_afu_cmd_os ), // -- input
.afu_tlx_cmd_rd_req ( afu_tlx_cmd_rd_req ), // -- output
.afu_tlx_cmd_rd_cnt ( afu_tlx_cmd_rd_cnt[2:0] ), // -- output
.tlx_afu_cmd_data_valid ( tlx_afu_cmd_data_valid ), // -- input
.tlx_afu_cmd_data_bdi ( tlx_afu_cmd_data_bdi ), // -- input
.tlx_afu_cmd_data_bus ( tlx_afu_cmd_data_bus[511:0] ), // -- input
.afu_tlx_cmd_credit ( afu_tlx_cmd_credit ), // -- output
.afu_tlx_cmd_initial_credit ( afu_tlx_cmd_initial_credit[6:0] ), // -- output
// -- AFU_TLX response transmit interface
.afu_tlx_resp_valid ( afu_tlx_resp_valid ), // -- output
.afu_tlx_resp_opcode ( afu_tlx_resp_opcode[7:0] ), // -- output
.afu_tlx_resp_dl ( afu_tlx_resp_dl[1:0] ), // -- output
.afu_tlx_resp_capptag ( afu_tlx_resp_capptag[15:0] ), // -- output
.afu_tlx_resp_dp ( afu_tlx_resp_dp[1:0] ), // -- output
.afu_tlx_resp_code ( afu_tlx_resp_code[3:0] ), // -- output
.afu_tlx_rdata_valid ( afu_tlx_rdata_valid ), // -- output
.afu_tlx_rdata_bdi ( afu_tlx_rdata_bdi ), // -- output
.afu_tlx_rdata_bus ( afu_tlx_rdata_bus[511:0] ), // -- output
.tlx_afu_resp_credit ( tlx_afu_resp_credit ), // -- input
.tlx_afu_resp_data_credit ( tlx_afu_resp_data_credit ), // -- input
// -- AFU_TLX command transmit interface
.afu_tlx_cmd_valid ( afu_tlx_cmd_valid ), // -- output
.afu_tlx_cmd_opcode ( afu_tlx_cmd_opcode[7:0] ), // -- output
.afu_tlx_cmd_actag ( afu_tlx_cmd_actag[11:0] ), // -- output
.afu_tlx_cmd_stream_id ( afu_tlx_cmd_stream_id[3:0] ), // -- output
.afu_tlx_cmd_ea_or_obj ( afu_tlx_cmd_ea_or_obj[67:0] ), // -- output
.afu_tlx_cmd_afutag ( afu_tlx_cmd_afutag[15:0] ), // -- output
.afu_tlx_cmd_dl ( afu_tlx_cmd_dl[1:0] ), // -- output
.afu_tlx_cmd_pl ( afu_tlx_cmd_pl[2:0] ), // -- output
.afu_tlx_cmd_os ( afu_tlx_cmd_os ), // -- output
.afu_tlx_cmd_be ( afu_tlx_cmd_be[63:0] ), // -- output
.afu_tlx_cmd_flag ( afu_tlx_cmd_flag[3:0] ), // -- output
.afu_tlx_cmd_endian ( afu_tlx_cmd_endian ), // -- output
.afu_tlx_cmd_bdf ( afu_tlx_cmd_bdf[15:0] ), // -- output
.afu_tlx_cmd_pasid ( afu_tlx_cmd_pasid[19:0] ), // -- output
.afu_tlx_cmd_pg_size ( afu_tlx_cmd_pg_size[5:0] ), // -- output
.afu_tlx_cdata_valid ( afu_tlx_cdata_valid ), // -- output
.afu_tlx_cdata_bdi ( afu_tlx_cdata_bdi ), // -- output
.afu_tlx_cdata_bus ( afu_tlx_cdata_bus[511:0] ), // -- output
.tlx_afu_cmd_credit ( tlx_afu_cmd_credit ), // -- input
.tlx_afu_cmd_data_credit ( tlx_afu_cmd_data_credit ), // -- input
//GFP .tlx_afu_cmd_resp_initial_credit_x ( tlx_afu_cmd_resp_initial_credit_x[4:3] ), // -- input
.tlx_afu_cmd_initial_credit_x ( 1'b0 ), // -- input
//GFP .tlx_afu_cmd_resp_initial_credit ( tlx_afu_cmd_resp_initial_credit[2:0] ), // -- input
.tlx_afu_cmd_initial_credit ( tlx_afu_cmd_initial_credit ), // -- input
.tlx_afu_resp_initial_credit ( tlx_afu_resp_initial_credit ), // -- input
//GFP .tlx_afu_data_initial_credit_x ( tlx_afu_data_initial_credit_x[6:5] ), // -- input
.tlx_afu_cmd_data_initial_credit_x ( 1'b0 ), // -- input
//GFP .tlx_afu_data_initial_credit ( tlx_afu_data_initial_credit[4:0] ), // -- input
.tlx_afu_cmd_data_initial_credit ( tlx_afu_cmd_data_initial_credit ), // -- input
.tlx_afu_resp_data_initial_credit ( tlx_afu_resp_data_initial_credit ), // -- input
// -- TLX_AFU response receive interface
.tlx_afu_resp_valid ( tlx_afu_resp_valid ), // -- input
.tlx_afu_resp_opcode ( tlx_afu_resp_opcode[7:0] ), // -- input
.tlx_afu_resp_afutag ( tlx_afu_resp_afutag[15:0] ), // -- input
.tlx_afu_resp_code ( tlx_afu_resp_code[3:0] ), // -- input
.tlx_afu_resp_dl ( tlx_afu_resp_dl[1:0] ), // -- input
.tlx_afu_resp_dp ( tlx_afu_resp_dp[1:0] ), // -- input
.tlx_afu_resp_pg_size ( tlx_afu_resp_pg_size[5:0] ), // -- input
.tlx_afu_resp_addr_tag ( tlx_afu_resp_addr_tag[17:0] ), // -- input
// -- .tlx_afu_resp_host_tag ( tlx_afu_resp_host_tag[23:0] ), // -- input // -- Reserved for CAPI 4.0
// -- .tlx_afu_resp_cache_state ( tlx_afu_resp_cache_state[3:0] ), // -- input // -- Reserved for CAPI 4.0
.afu_tlx_resp_rd_req ( afu_tlx_resp_rd_req ), // -- output
.afu_tlx_resp_rd_cnt ( afu_tlx_resp_rd_cnt[2:0] ), // -- output
.tlx_afu_resp_data_valid ( tlx_afu_resp_data_valid ), // -- input
.tlx_afu_resp_data_bdi ( tlx_afu_resp_data_bdi ), // -- input
.tlx_afu_resp_data_bus ( tlx_afu_resp_data_bus[511:0] ), // -- input
.afu_tlx_resp_credit ( afu_tlx_resp_credit ), // -- output
.afu_tlx_resp_initial_credit ( afu_tlx_resp_initial_credit[6:0] ), // -- output
.afu_tlx_fatal_error ( afu_tlx_fatal_error ), // -- output
// -- BDF Interface
.cfg_afu_bdf_bus ( cfg_bus[7:0] ), // -- input
.cfg_afu_bdf_device ( ro_device[4:0] ), // -- input
.cfg_afu_bdf_function ( ro_function[2:0] ), // -- input
// -- Configuration Space Outputs used by AFU
// -- MMIO
.cfg_csh_memory_space ( cfg_f1_csh_memory_space ), // -- input
.cfg_csh_mmio_bar0 ( cfg_f1_csh_mmio_bar0[63:0] ), // -- input
// -- 'assign_actag' generation controls
.cfg_octrl00_afu_actag_len_enab ( cfg_f1_octrl00_afu_actag_len_enab[11:0] ), // -- input
.cfg_octrl00_afu_actag_base ( cfg_f1_octrl00_afu_actag_base[11:0] ), // -- input
// -- Process termination controls
.cfg_octrl00_terminate_in_progress ( afu_f1_cfg_terminate_in_progress ), // -- output
.cfg_octrl00_terminate_valid ( cfg_f1_octrl00_terminate_valid ), // -- input
.cfg_octrl00_terminate_pasid ( cfg_f1_octrl00_terminate_pasid[19:0] ), // -- input
//-- PASID controls
.cfg_octrl00_pasid_length_enabled ( cfg_f1_octrl00_pasid_length_enabled[4:0] ), // -- input
.cfg_octrl00_pasid_base ( cfg_f1_octrl00_pasid_base[19:0] ), // -- input
// -- Interrupt generation controls
.cfg_f0_otl0_long_backoff_timer ( cfg_f0_otl0_long_backoff_timer[3:0] ), // -- input
.cfg_f0_otl0_short_backoff_timer ( cfg_f0_otl0_short_backoff_timer[3:0] ), // -- input
.cfg_octrl00_enable_afu ( cfg_f1_octrl00_enable_afu ), // -- input // -- When 1, the AFU can initiate commands to the host
// -- Interface to AFU Descriptor table (interface is Read Only
.cfg_desc_afu_index ( cfg_desc_afu_index[5:0] ), // -- input
.cfg_desc_offset ( cfg_desc_offset[30:0] ), // -- input
.cfg_desc_cmd_valid ( cfg_desc_cmd_valid ), // -- input
.desc_cfg_data ( desc0_cfg_data[31:0] ), // -- output
.desc_cfg_data_valid ( desc0_cfg_data_valid ), // -- output
.desc_cfg_echo_cmd_valid ( desc0_cfg_echo_cmd_valid ), // -- output
// -- Errors to record from CFG Sub-System, Descriptor Table, and VPD
.vpd_err_unimplemented_addr ( vpd_err_unimplemented_addr ), // -- input
.cfg0_cff_fifo_overflow ( cfg0_cff_fifo_overflow ), // -- input
// -- .cfg1_cff_fifo_overflow ( cfg1_cff_fifo_overflow ), // -- input
.cfg0_rff_fifo_overflow ( cfg0_rff_fifo_overflow ), // -- input
// -- .cfg1_rff_fifo_overflow ( cfg1_rff_fifo_overflow ), // -- input
.cfg_errvec ( cfg_errvec ), // -- input
.cfg_errvec_valid ( cfg_errvec_valid ) // -- input
);
endmodule //-- oc_cfg |
module action_multi_process # (
parameter ENGINE_NUM = 8,
parameter ACTION_ID_WIDTH = 5,
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
parameter C_S_AXI_CTRL_REG_DATA_WIDTH = 32,
parameter C_S_AXI_CTRL_REG_ADDR_WIDTH = 32,
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
parameter C_M_AXI_HOST_MEM_ID_WIDTH = 4,
parameter C_M_AXI_HOST_MEM_ADDR_WIDTH = 64,
parameter C_M_AXI_HOST_MEM_DATA_WIDTH = 512,
parameter C_M_AXI_HOST_MEM_AWUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_ARUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_WUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_RUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_BUSER_WIDTH = 1,
parameter INT_BITS = 3,
parameter CONTEXT_BITS = 8
)
(
input clk ,
input rst_n ,
//---- AXI bus interfaced with SNAP core ----
// AXI write address channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_awid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH - 1:0] m_axi_snap_awaddr ,
output [0007:0] m_axi_snap_awlen ,
output [0002:0] m_axi_snap_awsize ,
output [0001:0] m_axi_snap_awburst ,
output [0003:0] m_axi_snap_awcache ,
output [0001:0] m_axi_snap_awlock ,
output [0002:0] m_axi_snap_awprot ,
output [0003:0] m_axi_snap_awqos ,
output [0003:0] m_axi_snap_awregion ,
output [C_M_AXI_HOST_MEM_AWUSER_WIDTH - 1:0] m_axi_snap_awuser ,
output m_axi_snap_awvalid ,
input m_axi_snap_awready ,
// AXI write data channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_wid ,
output [C_M_AXI_HOST_MEM_DATA_WIDTH - 1:0] m_axi_snap_wdata ,
output [(C_M_AXI_HOST_MEM_DATA_WIDTH/8) -1:0] m_axi_snap_wstrb ,
output m_axi_snap_wlast ,
output m_axi_snap_wvalid ,
input m_axi_snap_wready ,
// AXI write response channel
output m_axi_snap_bready ,
input [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_bid ,
input [0001:0] m_axi_snap_bresp ,
input m_axi_snap_bvalid ,
// AXI read address channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_arid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH - 1:0] m_axi_snap_araddr ,
output [0007:0] m_axi_snap_arlen ,
output [0002:0] m_axi_snap_arsize ,
output [0001:0] m_axi_snap_arburst ,
output [C_M_AXI_HOST_MEM_ARUSER_WIDTH - 1:0] m_axi_snap_aruser ,
output [0002:0] m_axi_snap_arcache ,
output [0001:0] m_axi_snap_arlock ,
output [0002:0] m_axi_snap_arprot ,
output [0003:0] m_axi_snap_arqos ,
output [0008:0] m_axi_snap_arregion ,
output m_axi_snap_arvalid ,
input m_axi_snap_arready ,
// AXI ead data channel
output m_axi_snap_rready ,
input [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_rid ,
input [C_M_AXI_HOST_MEM_DATA_WIDTH - 1:0] m_axi_snap_rdata ,
input [0001:0] m_axi_snap_rresp ,
input m_axi_snap_rlast ,
input m_axi_snap_rvalid ,
//---- AXI Lite bus interfaced with SNAP core ----
// AXI write address channel
output s_axi_snap_awready ,
input [C_S_AXI_CTRL_REG_ADDR_WIDTH - 1:0] s_axi_snap_awaddr ,
input [0002:0] s_axi_snap_awprot ,
input s_axi_snap_awvalid ,
// axi write data channel
output s_axi_snap_wready ,
input [C_S_AXI_CTRL_REG_DATA_WIDTH - 1:0] s_axi_snap_wdata ,
input [(C_S_AXI_CTRL_REG_DATA_WIDTH/8) -1:0] s_axi_snap_wstrb ,
input s_axi_snap_wvalid ,
// AXI response channel
output [0001:0] s_axi_snap_bresp ,
output s_axi_snap_bvalid ,
input s_axi_snap_bready ,
// AXI read address channel
output s_axi_snap_arready ,
input s_axi_snap_arvalid ,
input [C_S_AXI_CTRL_REG_ADDR_WIDTH - 1:0] s_axi_snap_araddr ,
input [0002:0] s_axi_snap_arprot ,
// AXI read data channel
output [C_S_AXI_CTRL_REG_DATA_WIDTH - 1:0] s_axi_snap_rdata ,
output [0001:0] s_axi_snap_rresp ,
input s_axi_snap_rready ,
output s_axi_snap_rvalid ,
// Other signals
input [31:0] i_action_type ,
input [31:0] i_action_version ,
output o_interrupt ,
input i_interrupt_ack
);
reg [0000:0] app_ready;
always @(posedge clk) begin
if (rst_n == 0) begin
app_ready <= 0;
end else begin
app_ready <= 1;
end
end
multi_process_framework #(
// This is a 8 kernel framework
.ENGINE_NUM (ENGINE_NUM),
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
.C_S_AXI_CTRL_REG_DATA_WIDTH (C_S_AXI_CTRL_REG_DATA_WIDTH ),
.C_S_AXI_CTRL_REG_ADDR_WIDTH (C_S_AXI_CTRL_REG_ADDR_WIDTH ),
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
.C_M_AXI_HOST_MEM_ID_WIDTH (ACTION_ID_WIDTH ),
.C_M_AXI_HOST_MEM_ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.C_M_AXI_HOST_MEM_DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH ),
.C_M_AXI_HOST_MEM_AWUSER_WIDTH (C_M_AXI_HOST_MEM_AWUSER_WIDTH ),
.C_M_AXI_HOST_MEM_ARUSER_WIDTH (C_M_AXI_HOST_MEM_ARUSER_WIDTH ),
.C_M_AXI_HOST_MEM_WUSER_WIDTH (C_M_AXI_HOST_MEM_WUSER_WIDTH ),
.C_M_AXI_HOST_MEM_RUSER_WIDTH (C_M_AXI_HOST_MEM_RUSER_WIDTH ),
.C_M_AXI_HOST_MEM_BUSER_WIDTH (C_M_AXI_HOST_MEM_BUSER_WIDTH )
) multi_process_framework_0 (
.clk (clk ) ,
.rst_n (rst_n ) ,
.m_axi_snap_awid (m_axi_snap_awid ) ,
.m_axi_snap_awaddr (m_axi_snap_awaddr ) ,
.m_axi_snap_awlen (m_axi_snap_awlen ) ,
.m_axi_snap_awsize (m_axi_snap_awsize ) ,
.m_axi_snap_awburst (m_axi_snap_awburst ) ,
.m_axi_snap_awcache (m_axi_snap_awcache ) ,
.m_axi_snap_awlock ( ) ,
.m_axi_snap_awprot (m_axi_snap_awprot ) ,
.m_axi_snap_awqos (m_axi_snap_awqos ) ,
.m_axi_snap_awregion (m_axi_snap_awregion ) ,
.m_axi_snap_awuser (m_axi_snap_awuser) ,
.m_axi_snap_awvalid (m_axi_snap_awvalid ) ,
.m_axi_snap_awready (m_axi_snap_awready ) ,
.m_axi_snap_wid (m_axi_snap_wid ) ,
.m_axi_snap_wdata (m_axi_snap_wdata ) ,
.m_axi_snap_wstrb (m_axi_snap_wstrb ) ,
.m_axi_snap_wlast (m_axi_snap_wlast ) ,
.m_axi_snap_wvalid (m_axi_snap_wvalid ) ,
.m_axi_snap_wready (m_axi_snap_wready ) ,
.m_axi_snap_bready (m_axi_snap_bready ) ,
.m_axi_snap_bid (m_axi_snap_bid ) ,
.m_axi_snap_bresp (m_axi_snap_bresp ) ,
.m_axi_snap_bvalid (m_axi_snap_bvalid ) ,
.m_axi_snap_arid (m_axi_snap_arid ) ,
.m_axi_snap_araddr (m_axi_snap_araddr ) ,
.m_axi_snap_arlen (m_axi_snap_arlen ) ,
.m_axi_snap_arsize (m_axi_snap_arsize ) ,
.m_axi_snap_arburst (m_axi_snap_arburst ) ,
.m_axi_snap_aruser (m_axi_snap_aruser) ,
.m_axi_snap_arcache (m_axi_snap_arcache ) ,
.m_axi_snap_arlock ( ) ,
.m_axi_snap_arprot (m_axi_snap_arprot ) ,
.m_axi_snap_arqos (m_axi_snap_arqos ) ,
.m_axi_snap_arregion (m_axi_snap_arregion ) ,
.m_axi_snap_arvalid (m_axi_snap_arvalid ) ,
.m_axi_snap_arready (m_axi_snap_arready ) ,
.m_axi_snap_rready (m_axi_snap_rready ) ,
.m_axi_snap_rid (m_axi_snap_rid ) ,
.m_axi_snap_rdata (m_axi_snap_rdata ) ,
.m_axi_snap_rresp (m_axi_snap_rresp ) ,
.m_axi_snap_rlast (m_axi_snap_rlast ) ,
.m_axi_snap_rvalid (m_axi_snap_rvalid ) ,
.s_axi_snap_awready (s_axi_snap_awready ) ,
.s_axi_snap_awaddr (s_axi_snap_awaddr ) ,
.s_axi_snap_awprot (s_axi_snap_awprot ) ,
.s_axi_snap_awvalid (s_axi_snap_awvalid ) ,
.s_axi_snap_wready (s_axi_snap_wready ) ,
.s_axi_snap_wdata (s_axi_snap_wdata ) ,
.s_axi_snap_wstrb (s_axi_snap_wstrb ) ,
.s_axi_snap_wvalid (s_axi_snap_wvalid ) ,
.s_axi_snap_bresp (s_axi_snap_bresp ) ,
.s_axi_snap_bvalid (s_axi_snap_bvalid ) ,
.s_axi_snap_bready (s_axi_snap_bready ) ,
.s_axi_snap_arready (s_axi_snap_arready ) ,
.s_axi_snap_arvalid (s_axi_snap_arvalid ) ,
.s_axi_snap_araddr (s_axi_snap_araddr ) ,
.s_axi_snap_arprot (s_axi_snap_arprot ) ,
.s_axi_snap_rdata (s_axi_snap_rdata ) ,
.s_axi_snap_rresp (s_axi_snap_rresp ) ,
.s_axi_snap_rready (s_axi_snap_rready ) ,
.s_axi_snap_rvalid (s_axi_snap_rvalid ) ,
.i_app_ready (app_ready ) ,
.i_action_type (i_action_type ) ,
.i_action_version (i_action_version ) ,
.o_interrupt (o_interrupt ) ,
.i_interrupt_ack (i_interrupt_ack )
) ;
endmodule |
module mp_manager #(
parameter ID_WIDTH = 1,
parameter ARUSER_WIDTH = 9,
parameter AWUSER_WIDTH = 9,
parameter DATA_WIDTH = 1024,
parameter ADDR_WIDTH = 64
)(
input clk ,
input rst_n ,
input [087:0] process_info_i ,
input process_start_i ,
output process_ready_o ,
input dsc0_pull_i ,
output [1023:0] dsc0_data_o ,
output dsc0_ready_o ,
//---- AXI bus ----
// AXI read address channel
output [ID_WIDTH - 1:0] m_axi_arid ,
output [ADDR_WIDTH - 1:0] m_axi_araddr ,
output [007:0] m_axi_arlen ,
output [002:0] m_axi_arsize ,
output [001:0] m_axi_arburst ,
output [ARUSER_WIDTH - 1:0] m_axi_aruser ,
output [003:0] m_axi_arcache ,
output [001:0] m_axi_arlock ,
output [002:0] m_axi_arprot ,
output [003:0] m_axi_arqos ,
output [003:0] m_axi_arregion,
output reg m_axi_arvalid ,
input m_axi_arready ,
// AXI read data channel
output m_axi_rready ,
//input [ARUSER_WIDTH - 1:0] m_axi_ruser ,
input [ID_WIDTH - 1:0] m_axi_rid ,
input [DATA_WIDTH - 1:0] m_axi_rdata ,
input [001:0] m_axi_rresp ,
input m_axi_rlast ,
input m_axi_rvalid
);
reg [8:0] process_num;
reg in_read;
wire read_done;
wire read_request;
wire process_fifo_empty;
wire process_fifo_full;
wire process_fifo_valid;
wire process_fifo_pull;
wire process_fifo_push;
wire [87:0] process_fifo_out;
wire [87:0] process_fifo_in;
wire dsc_fifo_empty;
wire dsc_fifo_full;
wire dsc_fifo_valid;
wire dsc_fifo_pull;
wire dsc_fifo_push;
wire [1023:0] dsc_fifo_out;
wire [1023:0] dsc_fifo_in;
wire [5:0] dsc_fifo_cnt;
assign m_axi_arid = 0;
assign m_axi_arsize = 3'd7; // 8*2^7=1024
assign m_axi_arburst = 2'd1; // INCR mode for memory access
assign m_axi_arcache = 4'd3; // Normal Non-cacheable Bufferable
assign m_axi_arprot = 3'd0;
assign m_axi_arqos = 4'd0;
assign m_axi_arregion = 4'd0; //?
assign m_axi_arlock = 2'b00; // normal access
assign m_axi_rready = 1'b1;
process_fifo fifo_process (
.clk (clk ),
.rst (!rst_n ),
.din (process_fifo_in ),
.wr_en (process_fifo_push ),
.rd_en (process_fifo_pull ),
.dout (process_fifo_out ),
.full (process_fifo_full ),
.empty (process_fifo_empty ),
.data_count ( )
);
assign process_ready_o = !(read_done & (m_axi_rdata[1023:960] != 'd0));
assign m_axi_araddr = process_fifo_out[63:0];
assign m_axi_aruser = process_fifo_out[72:64];
assign m_axi_arlen = process_fifo_out[77:73];
assign process_fifo_pull = read_done;
assign process_fifo_push = (read_done & (m_axi_rdata[1023:960] != 'd0)) | process_start_i;
assign process_fifo_in = (read_done & (m_axi_rdata[1023:960] != 'd0)) ? {10'b0,m_axi_rdata[12:8],process_num,m_axi_rdata[1023:960]} : process_info_i;
assign read_done = m_axi_rvalid & m_axi_rlast & (m_axi_rresp == 2'b0) & (m_axi_rid == 5'b00000);
assign read_request = ((dsc_fifo_cnt + m_axi_arlen) <'d63) & !in_read;
always@(posedge clk) if(m_axi_arready & m_axi_arvalid) process_num <= m_axi_aruser;
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_read <= 1'b0;
else if(m_axi_arready & m_axi_arvalid)
in_read <= 1'b1;
else if(read_done)
in_read <= 1'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
m_axi_arvalid <= 1'b0;
else if(m_axi_arready & m_axi_arvalid)
m_axi_arvalid <= 1'b0;
else if(read_request & !process_fifo_empty)
m_axi_arvalid <= 1'b1;
descriptor_fifo fifo_descriptor (
.clk (clk ), // input clk
.rst (!rst_n ), // input rst
.din (dsc_fifo_in ), // input [511 : 0] din
.wr_en (dsc_fifo_push ), // input wr_en
.rd_en (dsc_fifo_pull ), // input rd_en
.dout (dsc_fifo_out ), // output [511 : 0] dout
.full (dsc_fifo_full ), // output full
.empty (dsc_fifo_empty ), // output empty
.data_count (dsc_fifo_cnt ) // output [4 : 0] data_count
);
assign dsc_fifo_in = {23'b0, process_num, m_axi_rdata[991:0]};
assign dsc_fifo_push = m_axi_rvalid & (m_axi_rid == 5'b00000) & (m_axi_rresp == 2'b00);
assign dsc_fifo_pull = dsc0_pull_i;
assign dsc0_data_o = dsc_fifo_out;
assign dsc0_ready_o = !dsc_fifo_empty;
endmodule |
module axi_lite_global_slave #(
parameter KERNEL_NUM = 8,
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32
)(
input clk ,
input rst_n ,
//---- AXI Lite bus----
// AXI write address channel
output reg s_axi_awready ,
input [ADDR_WIDTH - 1:0] s_axi_awaddr ,
input [02:0] s_axi_awprot ,
input s_axi_awvalid ,
// axi write data channel
output reg s_axi_wready ,
input [DATA_WIDTH - 1:0] s_axi_wdata ,
input [(DATA_WIDTH/8) - 1:0] s_axi_wstrb ,
input s_axi_wvalid ,
// AXI response channel
output [01:0] s_axi_bresp ,
output reg s_axi_bvalid ,
input s_axi_bready ,
// AXI read address channel
output reg s_axi_arready ,
input s_axi_arvalid ,
input [ADDR_WIDTH - 1:0] s_axi_araddr ,
input [02:0] s_axi_arprot ,
// AXI read data channel
output reg [DATA_WIDTH - 1:0] s_axi_rdata ,
output [01:0] s_axi_rresp ,
input s_axi_rready ,
output reg s_axi_rvalid ,
//---- local control ----
output manager_start ,
output run_mode ,
output [63:0] init_addr ,
output [63:0] completion_addr ,
output [31:0] completion_size ,
output new_job ,
output job_done ,
input job_start ,
output reg real_done ,
input [31:0] i_action_type ,
input [31:0] i_action_version ,
output reg [KERNEL_NUM-1:0] kernel_start,
input [KERNEL_NUM-1:0] kernel_complete,
output [KERNEL_NUM-1:0] kernel_complete_posedge,
output o_interrupt ,
input i_interrupt_ack
);
//---- declarations ----
// For 32bit write data.
reg [31:0] write_address;
wire[31:0] wr_mask;
wire [31:0] write_data_interrupt_control;
//wire [31:0] write_data_interrupt_mask;
wire [31:0] REG_interrupt_mask_rd;
wire [31:0] REG_interrupt_control_rd;
reg [31:0] completion_q;
reg [KERNEL_NUM-1:0] kernel_complete_prev;
reg [KERNEL_NUM-1:0] pending_completed_kernels;
reg interrupt_req_reg;
reg interrupt_wait_soft_clear;
reg [KERNEL_NUM-1:0] kernel_busy;
///////////////////////////////////////////////////
//***********************************************//
//> REGISTERS <//
//***********************************************//
// //
/**/ reg [31:0] REG_interrupt_control ; /*W1C*/
/**/ reg [31:0] REG_interrupt_mask ; /*RO*/
/**/ reg [31:0] REG_global_control ; /*RW*/
/**/ reg [31:0] REG_init_addr_hi ; /*RW*/
/**/ reg [31:0] REG_init_addr_lo ; /*RW*/
/**/ reg [31:0] REG_completion_addr_hi ; /*RW*/
/**/ reg [31:0] REG_completion_addr_lo ; /*RW*/
/**/ reg [31:0] REG_completion_size ; /*RW*/
// //
//-----------------------------------------------//
// //
///////////////////////////////////////////////////
reg [31:0] cnt0;
reg [31:0] cnt1;
reg [31:0] cnt2;
reg [31:0] cnt3;
reg [31:0] cnt4;
reg [31:0] cnt5;
reg [31:0] cnt6;
reg [31:0] cnt7;
reg job_done_r;
//---- parameters ----
// Register addresses arrangement
parameter ADDR_GLOBAL_INTR_CONTROL = 32'h30,
ADDR_GLOBAL_INTR_MASK = 32'h34,
ADDR_GLOBAL_CONTROL = 32'h38,
ADDR_INIT_ADDR_HI = 32'h3C,
ADDR_INIT_ADDR_LO = 32'h40,
ADDR_GLOBAL_DONE = 32'h44,
ADDR_KERNEL0_CNT = 32'h48,
ADDR_KERNEL1_CNT = 32'h4C,
ADDR_KERNEL2_CNT = 32'h50,
ADDR_KERNEL3_CNT = 32'h54,
ADDR_KERNEL4_CNT = 32'h58,
ADDR_KERNEL5_CNT = 32'h5C,
ADDR_KERNEL6_CNT = 32'h60,
ADDR_KERNEL7_CNT = 32'h64,
ADDR_CMPL_ADDR_HI = 32'h68,
ADDR_CMPL_ADDR_LO = 32'h6C,
ADDR_CMPL_SIZE = 32'h70,
ADDR_SNAP_ACTION_TYPE = 32'h10,
ADDR_SNAP_ACTION_VERSION = 32'h14;
/***********************************************************************
* interrupt generation *
***********************************************************************/
genvar i;
generate
for (i = 0; i < KERNEL_NUM; i = i + 1) begin:kernel_complete_posedge_gen
assign kernel_complete_posedge[i] = (kernel_complete_prev[i] == 0) & (kernel_complete[i] == 1);
end
endgenerate
//assign o_interrupt = |REG_interrupt_mask;
assign o_interrupt = interrupt_req_reg;
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
interrupt_req_reg <= 1'b0;
interrupt_wait_soft_clear <= 1'b0;
end
else begin
// Interrupt acknowledged, clear the interrupt request
if (i_interrupt_ack == 1'b1) begin
interrupt_req_reg <= 1'b0;
interrupt_wait_soft_clear <= 1'b1;
end
else if ((interrupt_wait_soft_clear == 1'b1) & (REG_interrupt_mask[KERNEL_NUM-1:0] == {KERNEL_NUM{1'b0}})) begin
interrupt_wait_soft_clear <= 1'b0;
end
else if (interrupt_wait_soft_clear == 1'b0) begin
interrupt_req_reg <= |REG_interrupt_mask;
end
else begin
interrupt_req_reg <= interrupt_req_reg;
interrupt_wait_soft_clear <= interrupt_wait_soft_clear;
end
end
always@(posedge clk or negedge rst_n)
if(~rst_n)
kernel_complete_prev <= {KERNEL_NUM{1'b1}};
else
kernel_complete_prev <= kernel_complete;
always@(posedge clk or negedge rst_n)
if(!rst_n)
job_done_r <= 1'b0;
else
job_done_r <= job_done;
always@(posedge clk or negedge rst_n)
if(!rst_n)
real_done <= 1'b0;
else if(manager_start)
real_done <= 1'b0;
else if(job_done & !job_done_r)
real_done <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt0 <= 32'b0;
else if(manager_start)
cnt0 <= 32'b0;
else if(kernel_complete_posedge[0])
cnt0 <= cnt0 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt1 <= 32'b0;
else if(manager_start)
cnt1 <= 32'b0;
else if(kernel_complete_posedge[1])
cnt1 <= cnt1 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt2 <= 32'b0;
else if(manager_start)
cnt2 <= 32'b0;
else if(kernel_complete_posedge[2])
cnt2 <= cnt2 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt3 <= 32'b0;
else if(manager_start)
cnt3 <= 32'b0;
else if(kernel_complete_posedge[3])
cnt3 <= cnt3 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt4 <= 32'b0;
else if(manager_start)
cnt4 <= 32'b0;
else if(kernel_complete_posedge[4])
cnt4 <= cnt4 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt5 <= 32'b0;
else if(manager_start)
cnt5 <= 32'b0;
else if(kernel_complete_posedge[5])
cnt5 <= cnt5 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt6 <= 32'b0;
else if(manager_start)
cnt6 <= 32'b0;
else if(kernel_complete_posedge[6])
cnt6 <= cnt6 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt7 <= 32'b0;
else if(manager_start)
cnt7 <= 32'b0;
else if(kernel_complete_posedge[7])
cnt7 <= cnt7 + 1'b1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
REG_interrupt_mask <= 32'b0;
else begin
if ((REG_interrupt_mask[KERNEL_NUM-1:0] == {KERNEL_NUM{1'b0}}) & ~(s_axi_wvalid & s_axi_wready)) begin
REG_interrupt_mask[KERNEL_NUM-1:0] <= pending_completed_kernels;
end
else if (s_axi_wvalid & s_axi_wready) begin
case(write_address)
ADDR_GLOBAL_INTR_CONTROL : begin
REG_interrupt_mask <= REG_interrupt_mask & ~write_data_interrupt_control;
end
default :;
endcase
end
else begin
REG_interrupt_mask <= REG_interrupt_mask;
end
end
always@(posedge clk or negedge rst_n)
if(~rst_n)
pending_completed_kernels <= {KERNEL_NUM{1'b0}};
else begin
pending_completed_kernels <= (pending_completed_kernels | kernel_complete_posedge) & ~REG_interrupt_mask[KERNEL_NUM-1:0];
end
/***********************************************************************
* writing registers *
***********************************************************************/
//---- write address capture ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
write_address <= 32'd0;
else if(s_axi_awvalid & s_axi_awready)
write_address <= s_axi_awaddr;
//---- write address ready ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_awready <= 1'b0;
else if(s_axi_awvalid)
s_axi_awready <= 1'b1;
else if(s_axi_wvalid & s_axi_wready)
s_axi_awready <= 1'b0;
//---- write data ready ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_wready <= 1'b0;
else if(s_axi_awvalid & s_axi_awready)
s_axi_wready <= 1'b1;
else if(s_axi_wvalid)
s_axi_wready <= 1'b0;
//---- handle write data strobe ----
assign wr_mask = {{8{s_axi_wstrb[3]}},{8{s_axi_wstrb[2]}},{8{s_axi_wstrb[1]}},{8{s_axi_wstrb[0]}}};
assign write_data_interrupt_control = {(s_axi_wdata&wr_mask)|(~wr_mask®_interrupt_control)};
//assign write_data_interrupt_mask = {(s_axi_wdata&wr_mask)|(~wr_mask®_interrupt_mask)};
//---- registers behaviour ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
REG_interrupt_control <= 32'd0;
//REG_interrupt_mask <= 32'd0;
end
else if(s_axi_wvalid & s_axi_wready)
case(write_address)
ADDR_GLOBAL_INTR_CONTROL : begin
REG_interrupt_control <= write_data_interrupt_control;
end
//ADDR_GLOBAL_INTR_MASK : REG_interrupt_mask <= write_data_interrupt_mask;
default :;
endcase
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
completion_q <= 0;
end
end
/***********************************************************************
* reading registers *
***********************************************************************/
assign REG_interrupt_control_rd = REG_interrupt_control;
assign REG_interrupt_mask_rd = REG_interrupt_mask;
//---- read registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_rdata <= 32'd0;
else if(s_axi_arvalid & s_axi_arready)
case(s_axi_araddr)
ADDR_GLOBAL_INTR_CONTROL : s_axi_rdata <= REG_interrupt_control_rd;
ADDR_GLOBAL_INTR_MASK : s_axi_rdata <= REG_interrupt_mask_rd;
ADDR_SNAP_ACTION_TYPE : s_axi_rdata <= i_action_type;
ADDR_SNAP_ACTION_VERSION : s_axi_rdata <= i_action_version;
ADDR_GLOBAL_CONTROL : s_axi_rdata <= REG_global_control;
ADDR_INIT_ADDR_HI : s_axi_rdata <= REG_init_addr_hi;
ADDR_INIT_ADDR_LO : s_axi_rdata <= REG_init_addr_lo;
ADDR_GLOBAL_DONE : s_axi_rdata <= {31'b0,real_done};
ADDR_CMPL_ADDR_HI : s_axi_rdata <= REG_completion_addr_hi;
ADDR_CMPL_ADDR_LO : s_axi_rdata <= REG_completion_addr_lo;
ADDR_CMPL_SIZE : s_axi_rdata <= REG_completion_size;
ADDR_KERNEL0_CNT : s_axi_rdata <= cnt0;
ADDR_KERNEL1_CNT : s_axi_rdata <= cnt1;
ADDR_KERNEL2_CNT : s_axi_rdata <= cnt2;
ADDR_KERNEL3_CNT : s_axi_rdata <= cnt3;
ADDR_KERNEL4_CNT : s_axi_rdata <= cnt4;
ADDR_KERNEL5_CNT : s_axi_rdata <= cnt5;
ADDR_KERNEL6_CNT : s_axi_rdata <= cnt6;
ADDR_KERNEL7_CNT : s_axi_rdata <= cnt7;
default : s_axi_rdata <= 32'h5a5aa5a5;
endcase
//---- address ready: deasserts once arvalid is seen; reasserts when current read is done ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_arready <= 1'b1;
else if(s_axi_arvalid)
s_axi_arready <= 1'b0;
else if(s_axi_rvalid & s_axi_rready)
s_axi_arready <= 1'b1;
//---- data ready: deasserts once rvalid is seen; reasserts when new address has come ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_rvalid <= 1'b0;
else if (s_axi_arvalid & s_axi_arready)
s_axi_rvalid <= 1'b1;
else if (s_axi_rready)
s_axi_rvalid <= 1'b0;
/***********************************************************************
* status reporting *
***********************************************************************/
//---- axi write response ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_bvalid <= 1'b0;
else if(s_axi_wvalid & s_axi_wready)
s_axi_bvalid <= 1'b1;
else if(s_axi_bready)
s_axi_bvalid <= 1'b0;
assign s_axi_bresp = 2'd0;
//---- axi read response ----
assign s_axi_rresp = 2'd0;
/***********************************************************************
* control *
***********************************************************************/
always@(posedge clk or negedge rst_n)
if(!rst_n)
REG_completion_size <= 32'b0;
else if(s_axi_wvalid & s_axi_wready & (write_address == ADDR_CMPL_SIZE))
REG_completion_size <= s_axi_wdata;
always@(posedge clk or negedge rst_n)
if(!rst_n)
REG_completion_addr_hi <= 32'b0;
else if(s_axi_wvalid & s_axi_wready & (write_address == ADDR_CMPL_ADDR_HI))
REG_completion_addr_hi <= s_axi_wdata;
always@(posedge clk or negedge rst_n)
if(!rst_n)
REG_completion_addr_lo <= 32'b0;
else if(s_axi_wvalid & s_axi_wready & (write_address == ADDR_CMPL_ADDR_LO))
REG_completion_addr_lo <= s_axi_wdata;
always@(posedge clk or negedge rst_n)
if(!rst_n)
REG_init_addr_lo <= 32'b0;
else if(s_axi_wvalid & s_axi_wready & (write_address == ADDR_INIT_ADDR_LO))
REG_init_addr_lo <= s_axi_wdata;
always@(posedge clk or negedge rst_n)
if(!rst_n)
REG_init_addr_hi <= 32'b0;
else if(s_axi_wvalid & s_axi_wready & (write_address == ADDR_INIT_ADDR_HI))
REG_init_addr_hi <= s_axi_wdata;
always@(posedge clk or negedge rst_n)
if(!rst_n)
REG_global_control <= 32'b0;
else if(s_axi_wvalid & s_axi_wready & (write_address == ADDR_GLOBAL_CONTROL))
REG_global_control <= s_axi_wdata;
assign manager_start = REG_global_control[0];
assign run_mode = REG_global_control[8];
assign init_addr = {REG_init_addr_hi,REG_init_addr_lo};
assign completion_addr = {REG_completion_addr_hi,REG_completion_addr_lo};
assign completion_size = REG_completion_size;
assign new_job = !(&kernel_busy);
assign job_done = !(|kernel_busy);
genvar j;
generate
for (j = 0; j < KERNEL_NUM; j = j + 1) begin:kernel_busy_gen
always@(posedge clk or negedge rst_n)
if(!rst_n)
kernel_busy[j] <= 1'b0;
else if(kernel_start[j] == 1'b1)
kernel_busy[j] <= 1'b1;
else if(kernel_complete_posedge[j] == 1'b1)
kernel_busy[j] <= 1'b0;
end
endgenerate
always@(posedge clk or negedge rst_n)
if(!rst_n)
kernel_start <= 8'b0;
else if(job_start) begin
casex(kernel_busy)
8'b0xxxxxxx: kernel_start <= 8'b10000000;
8'b10xxxxxx: kernel_start <= 8'b01000000;
8'b110xxxxx: kernel_start <= 8'b00100000;
8'b1110xxxx: kernel_start <= 8'b00010000;
8'b11110xxx: kernel_start <= 8'b00001000;
8'b111110xx: kernel_start <= 8'b00000100;
8'b1111110x: kernel_start <= 8'b00000010;
8'b11111110: kernel_start <= 8'b00000001;
default: kernel_start <= 8'b00000000;
endcase
end
else
kernel_start <= 8'b00000000;
endmodule |
module mp_scheduler #(
parameter KERNEL_NUM = 8
)(
input clk ,
input rst_n ,
//---- manager ----
output dsc0_pull_o ,
input dsc0_ready_i ,
input [1023:0] dsc0_data_i ,
//---- completion ----
input complete_ready_i,
output complete_push_o ,
output [40:0] return_data_o ,
//---- kernel ----
output reg [KERNEL_NUM-1:0] engine_start ,
output reg [1023:0] jd_payload ,
input [KERNEL_NUM-1:0] engine_done
);
//---- declarations ----
reg [KERNEL_NUM-1:0] kernel_complete_prev;
reg [KERNEL_NUM-1:0] kernel_busy;
wire [KERNEL_NUM-1:0] kernel_complete_posedge;
reg [40:0] kernel0_info; //40:32 pid 31:0 jobid
reg [40:0] kernel1_info; //40:32 pid 31:0 jobid
reg [40:0] kernel2_info; //40:32 pid 31:0 jobid
reg [40:0] kernel3_info; //40:32 pid 31:0 jobid
reg [40:0] kernel4_info; //40:32 pid 31:0 jobid
reg [40:0] kernel5_info; //40:32 pid 31:0 jobid
reg [40:0] kernel6_info; //40:32 pid 31:0 jobid
reg [40:0] kernel7_info; //40:32 pid 31:0 jobid
reg [31:0] process_cnt0[511:0];
reg [31:0] process_cnt1[511:0];
reg [40:0] completion_info;
genvar m;
generate
for (m = 0; m < 512; m = m + 1) begin: process_job_run
always@(posedge clk or negedge rst_n)
if(!rst_n)
process_cnt0[m] <= 'd0;
else if((|engine_start) & (jd_payload[40:32] == m))
process_cnt0[m] <= process_cnt0[m] + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
process_cnt1[m] <= 'd0;
else if(complete_push_o & (completion_info[40:32] == m))
process_cnt1[m] <= process_cnt1[m] + 1'b1;
end
endgenerate
genvar i;
generate
for (i = 0; i < KERNEL_NUM; i = i + 1) begin:kernel_complete_posedge_gen
assign kernel_complete_posedge[i] = (kernel_complete_prev[i] == 0) & (engine_done[i] == 1);
end
endgenerate
always@(posedge clk or negedge rst_n)
if(~rst_n)
kernel_complete_prev <= {KERNEL_NUM{1'b1}};
else
kernel_complete_prev <= engine_done;
assign dsc0_pull_o = !(&kernel_busy) & dsc0_ready_i;
assign complete_push_o = |engine_done;
assign return_data_o = completion_info;
genvar j;
generate
for (j = 0; j < KERNEL_NUM; j = j + 1) begin:kernel_busy_gen
always@(posedge clk or negedge rst_n)
if(!rst_n)
kernel_busy[j] <= 1'b0;
else if(engine_start[j] == 1'b1)
kernel_busy[j] <= 1'b1;
else if(kernel_complete_posedge[j] == 1'b1)
kernel_busy[j] <= 1'b0;
end
endgenerate
always@(posedge clk or negedge rst_n)
if(!rst_n)
engine_start <= 8'b0;
else if(dsc0_pull_o) begin
casex(kernel_busy)
8'b0xxxxxxx: engine_start <= 8'b10000000;
8'b10xxxxxx: engine_start <= 8'b01000000;
8'b110xxxxx: engine_start <= 8'b00100000;
8'b1110xxxx: engine_start <= 8'b00010000;
8'b11110xxx: engine_start <= 8'b00001000;
8'b111110xx: engine_start <= 8'b00000100;
8'b1111110x: engine_start <= 8'b00000010;
8'b11111110: engine_start <= 8'b00000001;
default: engine_start <= 8'b00000000;
endcase
end
else
engine_start <= 8'b00000000;
always@(posedge clk) if(dsc0_pull_o) jd_payload <= dsc0_data_i;
always@(posedge clk) if(engine_start[0]) kernel0_info <= {dsc0_data_i[1000:992],dsc0_data_i[63:32]};
always@(posedge clk) if(engine_start[1]) kernel1_info <= {dsc0_data_i[1000:992],dsc0_data_i[63:32]};
always@(posedge clk) if(engine_start[2]) kernel2_info <= {dsc0_data_i[1000:992],dsc0_data_i[63:32]};
always@(posedge clk) if(engine_start[3]) kernel3_info <= {dsc0_data_i[1000:992],dsc0_data_i[63:32]};
always@(posedge clk) if(engine_start[4]) kernel4_info <= {dsc0_data_i[1000:992],dsc0_data_i[63:32]};
always@(posedge clk) if(engine_start[5]) kernel5_info <= {dsc0_data_i[1000:992],dsc0_data_i[63:32]};
always@(posedge clk) if(engine_start[6]) kernel6_info <= {dsc0_data_i[1000:992],dsc0_data_i[63:32]};
always@(posedge clk) if(engine_start[7]) kernel7_info <= {dsc0_data_i[1000:992],dsc0_data_i[63:32]};
always@(*)
if(complete_push_o)
casex(engine_done & kernel_busy)
8'b1xxxxxxx: completion_info = kernel7_info;
8'b01xxxxxx: completion_info = kernel6_info;
8'b001xxxxx: completion_info = kernel5_info;
8'b0001xxxx: completion_info = kernel4_info;
8'b00001xxx: completion_info = kernel3_info;
8'b000001xx: completion_info = kernel2_info;
8'b0000001x: completion_info = kernel1_info;
default: completion_info = kernel0_info;
endcase
else
completion_info = 'd0;
endmodule |
module mp_control #(
parameter KERNEL_NUM = 8,
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32
)(
input clk ,
input rst_n ,
//---- AXI Lite bus----
// AXI write address channel
output reg s_axi_awready ,
input [ADDR_WIDTH - 1:0] s_axi_awaddr ,
input [02:0] s_axi_awprot ,
input s_axi_awvalid ,
// axi write data channel
output reg s_axi_wready ,
input [DATA_WIDTH - 1:0] s_axi_wdata ,
input [(DATA_WIDTH/8) - 1:0] s_axi_wstrb ,
input s_axi_wvalid ,
// AXI response channel
output [01:0] s_axi_bresp ,
output reg s_axi_bvalid ,
input s_axi_bready ,
// AXI read address channel
output reg s_axi_arready ,
input s_axi_arvalid ,
input [ADDR_WIDTH - 1:0] s_axi_araddr ,
input [02:0] s_axi_arprot ,
// AXI read data channel
output reg [DATA_WIDTH - 1:0] s_axi_rdata ,
output [01:0] s_axi_rresp ,
input s_axi_rready ,
output reg s_axi_rvalid ,
//---- local control ----
output [8:0] cmpl_ram_addr_o ,
output cmpl_ram_hi_o ,
output cmpl_ram_lo_o ,
output [31:0] cmpl_ram_data_o ,
output [87:0] process_info_o ,
output reg process_start_o ,
input process_ready_i ,
input [31:0] i_action_type ,
input [31:0] i_action_version
);
//---- declarations ----
// For 32bit write data.
reg [31:0] write_address;
wire [31:0] wr_mask;
reg [31:0] REG_global_control;
reg [8:0] process_id;
wire ram_read;
wire ram_write0;
wire ram_write1;
wire [8:0] ram_read_addr;
wire [8:0] ram_write_addr;
wire [63:0] ram_read_data;
wire [31:0] ram_write_data;
//---- parameters ----
// Register addresses arrangement
parameter ADDR_GLOBAL_CONTROL = 'h24,
ADDR_INIT_ADDR_LO = 'h28,
ADDR_INIT_ADDR_HI = 'h2C,
ADDR_CMPL_ADDR_LO = 'h30,
ADDR_CMPL_ADDR_HI = 'h34;
assign cmpl_ram_hi_o = s_axi_wvalid & s_axi_wready & (write_address[20:0] == ADDR_CMPL_ADDR_HI);
assign cmpl_ram_lo_o = s_axi_wvalid & s_axi_wready & (write_address[20:0] == ADDR_CMPL_ADDR_LO);
assign cmpl_ram_addr_o = write_address[30:22];
assign cmpl_ram_data_o = s_axi_wdata;
/***********************************************************************
* writing registers *
***********************************************************************/
//---- write address capture ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
write_address <= 32'd0;
else if(s_axi_awvalid & s_axi_awready)
write_address <= s_axi_awaddr;
//---- write address ready ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_awready <= 1'b0;
else if(s_axi_awvalid)
s_axi_awready <= 1'b1;
else if(s_axi_wvalid & s_axi_wready)
s_axi_awready <= 1'b0;
//---- write data ready ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_wready <= 1'b0;
else if(process_start_o & !process_ready_i)
s_axi_wready <= 1'b0;
else if(s_axi_awvalid & s_axi_awready)
s_axi_wready <= 1'b1;
else if(s_axi_wvalid)
s_axi_wready <= 1'b0;
//---- handle write data strobe ----
assign wr_mask = {{8{s_axi_wstrb[3]}},{8{s_axi_wstrb[2]}},{8{s_axi_wstrb[1]}},{8{s_axi_wstrb[0]}}};
/***********************************************************************
* reading registers *
***********************************************************************/
//---- read registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_rdata <= 32'd0;
else if(s_axi_arvalid & s_axi_arready)
case(s_axi_araddr)
// ADDR_SNAP_ACTION_TYPE : s_axi_rdata <= i_action_type;
ADDR_GLOBAL_CONTROL : s_axi_rdata <= REG_global_control;
// ADDR_INIT_ADDR_HI : s_axi_rdata <= REG_init_addr_hi;
// ADDR_INIT_ADDR_LO : s_axi_rdata <= REG_init_addr_lo;
default : s_axi_rdata <= 32'h5a5aa5a5;
endcase
//---- address ready: deasserts once arvalid is seen; reasserts when current read is done ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_arready <= 1'b1;
else if(s_axi_arvalid)
s_axi_arready <= 1'b0;
else if(s_axi_rvalid & s_axi_rready)
s_axi_arready <= 1'b1;
//---- data ready: deasserts once rvalid is seen; reasserts when new address has come ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_rvalid <= 1'b0;
else if (s_axi_arvalid & s_axi_arready)
s_axi_rvalid <= 1'b1;
else if (s_axi_rready)
s_axi_rvalid <= 1'b0;
/***********************************************************************
* status reporting *
***********************************************************************/
//---- axi write response ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_bvalid <= 1'b0;
else if(s_axi_wvalid & s_axi_wready)
s_axi_bvalid <= 1'b1;
else if(s_axi_bready)
s_axi_bvalid <= 1'b0;
assign s_axi_bresp = 2'd0;
assign s_axi_rresp = 2'd0;
/***********************************************************************
* control *
***********************************************************************/
addr_ram addr_ram_low(
.clk (clk ),
.d (ram_write_data ),
.dpra (ram_read_addr ),
.a (ram_write_addr ),
.we (ram_write1 ),
.dpo (ram_read_data[31:0] )
);
addr_ram addr_ram_high(
.clk (clk ),
.d (ram_write_data ),
.dpra (ram_read_addr ),
.a (ram_write_addr ),
.we (ram_write0 ),
.dpo (ram_read_data[63:32] )
);
always@(posedge clk or negedge rst_n)
if(!rst_n)
REG_global_control <= 32'b0;
else if(s_axi_wvalid & s_axi_wready & (write_address[20:0] == ADDR_GLOBAL_CONTROL))
REG_global_control <= s_axi_wdata;
assign ram_read = s_axi_wvalid & s_axi_wready & (write_address[20:0] == ADDR_GLOBAL_CONTROL);
assign ram_read_addr = write_address[30:22];
assign ram_write0 = s_axi_wvalid & s_axi_wready & (write_address[20:0] == ADDR_INIT_ADDR_HI);
assign ram_write1 = s_axi_wvalid & s_axi_wready & (write_address[20:0] == ADDR_INIT_ADDR_LO);
assign ram_write_addr = write_address[30:22];
assign ram_write_data = s_axi_wdata;
assign process_info_o = {7'b0,REG_global_control[15:8],process_id,ram_read_data};
always@(posedge clk) process_id <= write_address[30:22];
always@(posedge clk or negedge rst_n)
if(!rst_n)
process_start_o <= 1'b0;
else if(ram_read)
process_start_o <= 1'b1;
else if(process_ready_i)
process_start_o <= 1'b0;
endmodule |
module mp_completion #(
parameter ID_WIDTH = 1,
parameter ARUSER_WIDTH = 9,
parameter AWUSER_WIDTH = 9,
parameter DATA_WIDTH = 1024,
parameter ADDR_WIDTH = 64
)(
input clk ,
input rst_n ,
input [8:0] cmpl_ram_addr_i ,
input cmpl_ram_hi_i ,
input cmpl_ram_lo_i ,
input [31:0] cmpl_ram_data_i ,
output complete_ready_o ,
input complete_push_i ,
input [40:0] return_data_i ,
output [ID_WIDTH-1:0] m_axi_awid ,
output [ADDR_WIDTH-1:0] m_axi_awaddr ,
output [7:0] m_axi_awlen ,
output [2:0] m_axi_awsize ,
output [1:0] m_axi_awburst ,
output [3:0] m_axi_awcache ,
output m_axi_awlock ,
output [2:0] m_axi_awprot ,
output [3:0] m_axi_awqos ,
output [AWUSER_WIDTH-1:0] m_axi_awuser ,
output reg m_axi_awvalid ,
input m_axi_awready ,
output [ID_WIDTH-1:0] m_axi_wid ,
output [DATA_WIDTH-1:0] m_axi_wdata ,
output [DATA_WIDTH/8-1:0] m_axi_wstrb ,
output m_axi_wlast ,
output reg m_axi_wvalid ,
input m_axi_wready ,
output m_axi_bready ,
input [ID_WIDTH - 1:0] m_axi_bid ,
input [1:0] m_axi_bresp ,
input m_axi_bvalid
);
wire [8:0] cmpl_read_addr;
wire [63:0] cmpl_addr;
wire cmpl_fifo_pull;
wire cmpl_fifo_full;
wire cmpl_fifo_empty;
wire [3:0] cmpl_fifo_count;
wire [40:0] cmpl_fifo_out;
wire [31:0] cmpl_ram_wdata_hi;
wire cmpl_ram_wr_hi;
wire [31:0] cmpl_ram_wdata_lo;
wire cmpl_ram_wr_lo;
wire [8:0] cmpl_ram_waddr;
wire [63:0] next_cmpl_addr;
reg in_write;
reg cmpl_addr_update;
reg [40:0] cur_return_code;
always@(posedge clk) if(cmpl_fifo_pull) cur_return_code <= cmpl_fifo_out;
always@(posedge clk or negedge rst_n)
if(!rst_n)
m_axi_awvalid <= 1'b0;
else if(m_axi_wvalid)
m_axi_awvalid <= 1'b1;
else if(m_axi_awvalid & m_axi_awready)
m_axi_awvalid <= 1'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
m_axi_wvalid <= 1'b0;
else if(cmpl_fifo_pull)
m_axi_wvalid <= 1'b1;
else if(m_axi_wvalid & m_axi_wready)
m_axi_wvalid <= 1'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_write <= 1'b0;
else if(cmpl_fifo_pull)
in_write <= 1'b1;
else if(m_axi_bvalid & (m_axi_bresp == 2'b00))
in_write <= 1'b0;
assign cmpl_read_addr = cur_return_code[40:32];
assign cmpl_fifo_pull = !cmpl_fifo_empty & !in_write;
assign complete_ready_o = !cmpl_fifo_full;
assign m_axi_bready = 1'b1;
assign m_axi_wdata = {992'b0,cur_return_code[31:0]};
assign m_axi_wlast = m_axi_wvalid;
assign m_axi_wid = 'd0;
assign m_axi_wstrb = 'hffffffffffffffffffffffffffffffff;
assign m_axi_awid = 'd0;
assign m_axi_awsize = 3'd7; // 8*2^7=1024
assign m_axi_awburst = 2'd1; // INCR mode for memory access
assign m_axi_awcache = 4'd3; // Normal Non-cacheable Bufferable
assign m_axi_awprot = 3'd0;
assign m_axi_awqos = 4'd0;
assign m_axi_awlock = 2'b00; // normal access
assign m_axi_awlen = 8'd0;
assign m_axi_awuser = cur_return_code[40:32];
assign m_axi_awaddr = cmpl_addr;
completion_fifo fifo_completion (
.clk (clk ),
.rst (!rst_n ),
.din (return_data_i ),
.wr_en (complete_push_i ),
.rd_en (cmpl_fifo_pull ),
.dout (cmpl_fifo_out ),
.full (cmpl_fifo_full ),
.empty (cmpl_fifo_empty ),
.data_count (cmpl_fifo_count )
);
addr_ram cpml_ram_low(
.clk ( clk ),
.d ( cmpl_ram_wdata_lo ),
.dpra ( cmpl_read_addr ),
.a ( cmpl_ram_waddr ),
.we ( cmpl_ram_wr_lo ),
.dpo ( cmpl_addr[31:0] )
);
addr_ram cpml_ram_high(
.clk (clk ),
.d ( cmpl_ram_wdata_hi ),
.dpra ( cmpl_read_addr ),
.a ( cmpl_ram_waddr ),
.we ( cmpl_ram_wr_hi ),
.dpo ( cmpl_addr[63:32] )
);
assign cmpl_ram_wr_lo = cmpl_ram_lo_i | cmpl_addr_update & !cmpl_ram_hi_i;
assign cmpl_ram_wr_hi = cmpl_ram_hi_i | cmpl_addr_update & !cmpl_ram_lo_i;
assign cmpl_ram_wdata_lo = cmpl_ram_lo_i ? cmpl_ram_data_i : next_cmpl_addr[31:0];
assign cmpl_ram_wdata_hi = cmpl_ram_hi_i ? cmpl_ram_data_i : next_cmpl_addr[63:32];
assign next_cmpl_addr = cmpl_addr + 'd128;
assign cmpl_ram_waddr = (cmpl_ram_lo_i | cmpl_ram_hi_i) ? cmpl_ram_addr_i : cmpl_read_addr;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cmpl_addr_update <= 1'b0;
else if(m_axi_awvalid & m_axi_awready)
cmpl_addr_update <= 1'b1;
else if(cmpl_addr_update & !cmpl_ram_hi_i & !cmpl_ram_lo_i)
cmpl_addr_update <= 1'b0;
endmodule |
module action_memcopy # (
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
parameter C_S_AXI_CTRL_REG_DATA_WIDTH = 32,
parameter C_S_AXI_CTRL_REG_ADDR_WIDTH = 32,
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
parameter C_M_AXI_HOST_MEM_ID_WIDTH = 2,
parameter C_M_AXI_HOST_MEM_ADDR_WIDTH = 64,
parameter C_M_AXI_HOST_MEM_DATA_WIDTH = 1024,
parameter C_M_AXI_HOST_MEM_AWUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_ARUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_WUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_RUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_BUSER_WIDTH = 1
)
(
input clk ,
input rst_n ,
//---- AXI bus interfaced with SNAP core ----
// AXI write address channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_awid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH - 1:0] m_axi_snap_awaddr ,
output [0007:0] m_axi_snap_awlen ,
output [0002:0] m_axi_snap_awsize ,
output [0001:0] m_axi_snap_awburst ,
output [0003:0] m_axi_snap_awcache ,
output [0001:0] m_axi_snap_awlock ,
output [0002:0] m_axi_snap_awprot ,
output [0003:0] m_axi_snap_awqos ,
output [0003:0] m_axi_snap_awregion ,
output [C_M_AXI_HOST_MEM_AWUSER_WIDTH - 1:0] m_axi_snap_awuser ,
output m_axi_snap_awvalid ,
input m_axi_snap_awready ,
// AXI write data channel
output [C_M_AXI_HOST_MEM_DATA_WIDTH - 1:0] m_axi_snap_wdata ,
output [(C_M_AXI_HOST_MEM_DATA_WIDTH/8) -1:0]m_axi_snap_wstrb ,
output m_axi_snap_wlast ,
output m_axi_snap_wvalid ,
input m_axi_snap_wready ,
// AXI write response channel
output m_axi_snap_bready ,
input [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_bid ,
input [0001:0] m_axi_snap_bresp ,
input m_axi_snap_bvalid ,
// AXI read address channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_arid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH - 1:0] m_axi_snap_araddr ,
output [0007:0] m_axi_snap_arlen ,
output [0002:0] m_axi_snap_arsize ,
output [0001:0] m_axi_snap_arburst ,
output [C_M_AXI_HOST_MEM_ARUSER_WIDTH - 1:0] m_axi_snap_aruser ,
output [0003:0] m_axi_snap_arcache ,
output [0001:0] m_axi_snap_arlock ,
output [0002:0] m_axi_snap_arprot ,
output [0003:0] m_axi_snap_arqos ,
output [0008:0] m_axi_snap_arregion ,
output m_axi_snap_arvalid ,
input m_axi_snap_arready ,
// AXI ead data channel
output m_axi_snap_rready ,
input [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_rid ,
input [C_M_AXI_HOST_MEM_DATA_WIDTH - 1:0] m_axi_snap_rdata ,
input [0001:0] m_axi_snap_rresp ,
input m_axi_snap_rlast ,
input m_axi_snap_rvalid ,
input kernel_start ,
output kernel_done ,
input [1023:0] system_register
//---- AXI Lite bus interfaced with SNAP core ----
// AXI write address channel
//input [C_S_AXI_CTRL_REG_ADDR_WIDTH - 1:0] s_axi_snap_baseaddr ,
//output s_axi_snap_awready ,
//input [C_S_AXI_CTRL_REG_ADDR_WIDTH - 1:0] s_axi_snap_awaddr ,
//input [0002:0] s_axi_snap_awprot ,
//input s_axi_snap_awvalid ,
// axi write data channel
//output s_axi_snap_wready ,
//input [C_S_AXI_CTRL_REG_DATA_WIDTH - 1:0] s_axi_snap_wdata ,
//input [(C_S_AXI_CTRL_REG_DATA_WIDTH/8) -1:0]s_axi_snap_wstrb ,
//input s_axi_snap_wvalid ,
// AXI response channel
//output [0001:0] s_axi_snap_bresp ,
//output s_axi_snap_bvalid ,
//input s_axi_snap_bready ,
// AXI read address channel
//output s_axi_snap_arready ,
//input s_axi_snap_arvalid ,
//input [C_S_AXI_CTRL_REG_ADDR_WIDTH - 1:0] s_axi_snap_araddr ,
//input [0002:0] s_axi_snap_arprot ,
// AXI read data channel
//output [C_S_AXI_CTRL_REG_DATA_WIDTH - 1:0] s_axi_snap_rdata ,
//output [0001:0] s_axi_snap_rresp ,
//input s_axi_snap_rready ,
//output s_axi_snap_rvalid ,
// Other signals
//input [31:0] i_action_type ,
//input [31:0] i_action_version
);
wire engine_start_pulse ;
wire wrap_mode ;
wire [03:0] wrap_len ;
wire [63:0] source_address ;
wire [63:0] target_address ;
wire [31:0] rd_init_data ;
wire [31:0] wr_init_data ;
wire [31:0] rd_pattern ;
wire [31:0] rd_number ;
wire [31:0] wr_pattern ;
wire [31:0] wr_number ;
wire rd_done_pulse ;
wire wr_done_pulse ;
wire [1:0] rd_error ;
wire [63:0] rd_error_info ;
wire tt_arvalid ; //arvalid & arready
wire tt_rlast ; //rlast & rvalid & rready
wire tt_awvalid ; //awvalid & awready
wire tt_bvalid ; //bvalid & bready
wire [4:0] tt_arid ;
wire [4:0] tt_awid ;
wire [4:0] tt_rid ;
wire [4:0] tt_bid ;
wire [31:0] snap_context ;
reg wr_done ;
reg rd_done ;
reg kernel_start_r ;
reg [1023:0] system_register_r ;
reg engine_in_work ;
assign engine_start_pulse = kernel_start_r;
assign kernel_done = (wr_done || ((wr_number == 0) && engine_in_work)) && // wr_done
(rd_done || ((rd_number == 0) && engine_in_work)); // rd_done;
always@(posedge clk) if (kernel_start) system_register_r <= system_register;
always@(posedge clk) kernel_start_r <= kernel_start;
always@(posedge clk or negedge rst_n)
if(!rst_n)
wr_done <= 1'b0;
else if(kernel_start)
wr_done <= 1'b0;
else if(wr_done_pulse)
wr_done <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
rd_done <= 1'b0;
else if(kernel_start)
rd_done <= 1'b0;
else if(rd_done_pulse)
rd_done <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
engine_in_work <= 1'b0;
else if(kernel_start)
engine_in_work <= 1'b1;
else if(kernel_done)
engine_in_work <= 1'b0;
//---- registers hub for AXI Lite interface ----
// axi_lite_slave #(
// .DATA_WIDTH (C_S_AXI_CTRL_REG_DATA_WIDTH ),
// .ADDR_WIDTH (C_S_AXI_CTRL_REG_ADDR_WIDTH )
// ) maxi_lite_slave (
// .clk ( clk ) ,
// .rst_n ( rst_n ) ,
// .s_axi_baseaddr (s_axi_snap_baseaddr ),
// .s_axi_awready ( s_axi_snap_awready ) ,
// .s_axi_awaddr ( s_axi_snap_awaddr ) ,//32b
// .s_axi_awprot ( s_axi_snap_awprot ) ,//3b
// .s_axi_awvalid ( s_axi_snap_awvalid ) ,
// .s_axi_wready ( s_axi_snap_wready ) ,
// .s_axi_wdata ( s_axi_snap_wdata ) ,//32b
// .s_axi_wstrb ( s_axi_snap_wstrb ) ,//4b
// .s_axi_wvalid ( s_axi_snap_wvalid ) ,
// .s_axi_bresp ( s_axi_snap_bresp ) ,//2b
// .s_axi_bvalid ( s_axi_snap_bvalid ) ,
// .s_axi_bready ( s_axi_snap_bready ) ,
// .s_axi_arready ( s_axi_snap_arready ) ,
// .s_axi_arvalid ( s_axi_snap_arvalid ) ,
// .s_axi_araddr ( s_axi_snap_araddr ) ,//32b
// .s_axi_arprot ( s_axi_snap_arprot ) ,//3b
// .s_axi_rdata ( s_axi_snap_rdata ) ,//32b
// .s_axi_rresp ( s_axi_snap_rresp ) ,//2b
// .s_axi_rready ( s_axi_snap_rready ) ,
// .s_axi_rvalid ( s_axi_snap_rvalid ) ,
/*
.engine_start_pulse ( engine_start_pulse ) ,
.wrap_mode ( wrap_mode ) ,
.wrap_len ( wrap_len ) ,
.source_address ( source_address ) ,
.target_address ( target_address ) ,
.rd_init_data ( rd_init_data ) ,
.wr_init_data ( wr_init_data ) ,
.rd_pattern ( rd_pattern ) ,
.rd_number ( rd_number ) ,
.wr_pattern ( wr_pattern ) ,
.wr_number ( wr_number ) ,
.rd_done_pulse ( rd_done_pulse ) ,
.wr_done_pulse ( wr_done_pulse ) ,
.rd_error ( rd_error ) ,
.rd_error_info ( rd_error_info ) ,
.wr_error ( wr_error ) ,
.tt_arvalid ( tt_arvalid ) , //arvalid & arready
.tt_rlast ( tt_rlast ) , //rlast & rvalid & rready
.tt_awvalid ( tt_awvalid ) , //awvalid & awready
.tt_bvalid ( tt_bvalid ) , //bvalid & bready
.tt_arid ( tt_arid ) ,
.tt_awid ( tt_awid ) ,
.tt_rid ( tt_rid ) ,
.tt_bid ( tt_bid ) ,
.i_action_type ( i_action_type ) ,
.i_action_version ( i_action_version ) ,
.o_snap_context ( snap_context )
);
assign tt_arvalid = m_axi_snap_arvalid && m_axi_snap_arready;
assign tt_rlast = m_axi_snap_rvalid && m_axi_snap_rready && m_axi_snap_rlast;
assign tt_arid = m_axi_snap_arid;
assign tt_rid = m_axi_snap_rid;
assign tt_awvalid = m_axi_snap_awvalid && m_axi_snap_awready;
assign tt_bvalid = m_axi_snap_bvalid && m_axi_snap_bready;
assign tt_awid = m_axi_snap_awid;
assign tt_bid = m_axi_snap_bid;&*/
assign snap_context = system_register_r[1023:992];
assign wrap_mode = 'd0;
assign wrap_len = 'd0;
assign target_address = system_register_r[639:576];
assign source_address = system_register_r[575:512];
assign wr_number = system_register_r[511:480];
assign wr_pattern = system_register_r[479:448];
assign rd_number = system_register_r[447:416];
assign rd_pattern = system_register_r[415:384];
assign wr_init_data = system_register_r[127:96];
assign rd_init_data = system_register_r[95:64];
//---- writing channel of AXI master interface facing SNAP ----
axi_master_wr#(
.ID_WIDTH (C_M_AXI_HOST_MEM_ID_WIDTH ),
.ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH ),
.AWUSER_WIDTH (C_M_AXI_HOST_MEM_AWUSER_WIDTH ),
.ARUSER_WIDTH (C_M_AXI_HOST_MEM_ARUSER_WIDTH ),
.WUSER_WIDTH (C_M_AXI_HOST_MEM_WUSER_WIDTH ),
.RUSER_WIDTH (C_M_AXI_HOST_MEM_RUSER_WIDTH ),
.BUSER_WIDTH (C_M_AXI_HOST_MEM_BUSER_WIDTH )
) maxi_master_wr(
.clk (clk ),
.rst_n (rst_n),
.m_axi_awid (m_axi_snap_awid ),
.m_axi_awaddr (m_axi_snap_awaddr ),
.m_axi_awlen (m_axi_snap_awlen ),
.m_axi_awsize (m_axi_snap_awsize ),
.m_axi_awburst (m_axi_snap_awburst ),
.m_axi_awcache (m_axi_snap_awcache ),
.m_axi_awlock (m_axi_snap_awlock ),
.m_axi_awprot (m_axi_snap_awprot ),
.m_axi_awqos (m_axi_snap_awqos ),
.m_axi_awregion (m_axi_snap_awregion),
.m_axi_awuser (m_axi_snap_awuser ),
.m_axi_awvalid (m_axi_snap_awvalid ),
.m_axi_awready (m_axi_snap_awready ),
.m_axi_wdata (m_axi_snap_wdata ),
.m_axi_wstrb (m_axi_snap_wstrb ),
.m_axi_wlast (m_axi_snap_wlast ),
.m_axi_wvalid (m_axi_snap_wvalid ),
.m_axi_wready (m_axi_snap_wready ),
.m_axi_bready (m_axi_snap_bready ),
.m_axi_bid (m_axi_snap_bid ),
.m_axi_bresp (m_axi_snap_bresp ),
.m_axi_bvalid (m_axi_snap_bvalid ),
.engine_start_pulse (engine_start_pulse ),
.wrap_mode (wrap_mode ),
.wrap_len (wrap_len ),
.target_address (target_address ),
.wr_init_data (wr_init_data ),
.wr_pattern (wr_pattern ),
.wr_number (wr_number ),
.wr_done_pulse (wr_done_pulse ),
.wr_error (wr_error ),
.i_snap_context (snap_context )
);
//---- writing channel of AXI master interface facing SNAP ----
axi_master_rd#(
.ID_WIDTH (C_M_AXI_HOST_MEM_ID_WIDTH ),
.ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH ),
.AWUSER_WIDTH (C_M_AXI_HOST_MEM_AWUSER_WIDTH ),
.ARUSER_WIDTH (C_M_AXI_HOST_MEM_ARUSER_WIDTH ),
.WUSER_WIDTH (C_M_AXI_HOST_MEM_WUSER_WIDTH ),
.RUSER_WIDTH (C_M_AXI_HOST_MEM_RUSER_WIDTH ),
.BUSER_WIDTH (C_M_AXI_HOST_MEM_BUSER_WIDTH )
) maxi_master_rd(
.clk (clk ),
.rst_n (rst_n ),
.m_axi_arid (m_axi_snap_arid ),
.m_axi_araddr (m_axi_snap_araddr ),
.m_axi_arlen (m_axi_snap_arlen ),
.m_axi_arsize (m_axi_snap_arsize ),
.m_axi_arburst (m_axi_snap_arburst ),
.m_axi_aruser (m_axi_snap_aruser ),
.m_axi_arcache (m_axi_snap_arcache ),
.m_axi_arlock (m_axi_snap_arlock ),
.m_axi_arprot (m_axi_snap_arprot ),
.m_axi_arqos (m_axi_snap_arqos ),
.m_axi_arregion (m_axi_snap_arregion),
.m_axi_arvalid (m_axi_snap_arvalid ),
.m_axi_arready (m_axi_snap_arready ),
.m_axi_rready (m_axi_snap_rready ),
.m_axi_rid (m_axi_snap_rid ),
.m_axi_rdata (m_axi_snap_rdata ),
.m_axi_rresp (m_axi_snap_rresp ),
.m_axi_rlast (m_axi_snap_rlast ),
.m_axi_rvalid (m_axi_snap_rvalid ),
.engine_start_pulse (engine_start_pulse ),
.wrap_mode (wrap_mode ),
.wrap_len (wrap_len ),
.source_address (source_address ),
.rd_init_data (rd_init_data ),
.rd_pattern (rd_pattern ),
.rd_number (rd_number ),
.rd_done_pulse (rd_done_pulse ),
.rd_error (rd_error ),
.rd_error_info (rd_error_info ),
.i_snap_context (snap_context )
);
endmodule |
module addr_send_channel #(
parameter ID_WIDTH = 2,
parameter ADDR_WIDTH = 64,
parameter DATA_WIDTH = 512,
parameter AWUSER_WIDTH = 8,
parameter ARUSER_WIDTH = 8,
parameter WUSER_WIDTH = 1,
parameter RUSER_WIDTH = 1,
parameter BUSER_WIDTH = 1
)
(
input clk ,
input rst_n ,
//---- AXI bus ----
// AXI read address channel
output wire [063:0] axi_addr ,
output wire [007:0] axi_len ,
output wire axi_valid ,
input axi_ready ,
//---- local control ----
output wire addr_send_done ,
input engine_start ,
input wrap_mode ,
input [003:0] wrap_len ,
input [063:0] source_address ,
input [039:0] total_beat_count ,
input data_error ,
input [002:0] size ,
input [007:0] len ,
input [031:0] number
);
parameter IDLE = 6'h01;
parameter INIT = 6'h02;
parameter CLEN = 6'h04;
parameter SEND = 6'h08;
parameter CHECK = 6'h10;
parameter DONE = 6'h20;
reg [005:0] cstate;
reg [005:0] nstate;
wire all_burst_sent;
wire few_beat_remain;
wire cross_4KB_boundry;
reg [012:0] normal_addr_bias_reg;
reg [063:0] current_burst_addr;
reg [012:0] normal_addr_bias;
wire [063:0] next_4KB_boundry;
wire [063:0] next_burst_addr;
wire [063:0] next_burst_addr_incr;
reg [063:0] next_burst_addr_wrap;
reg [012:0] beat_number_in_4KB_reg;
reg [012:0] beat_number_sent_in_4KB;
reg [039:0] remain_beat_number;
reg [008:0] current_burst_len;
reg [012:0] init_beat_number_sent;
reg [012:0] beat_number_sent;
reg [012:0] beat_number_in_4KB;
wire [012:0] cross_4KB_burst_len;
wire [008:0] burst_len;
wire [008:0] actual_axi_len;
wire [008:0] len_plus_1;
assign len_plus_1 = {1'b0, len} + 1'b1;
assign addr_send_done = (cstate == DONE);
//---- Burst send state machine ----
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
cstate <= IDLE;
else
cstate <= nstate;
end
always@*
begin
case(cstate)
IDLE:
if(engine_start)
nstate = INIT;
else
nstate = IDLE;
INIT: // initilization, calculation normal addr bias, beat number in a 4KB range etc.
nstate = CLEN;
CLEN: // calculate burst length for axi interface
if(data_error)
nstate = IDLE;
else
nstate = SEND;
SEND: // calculate burst address and send axi burst
if(data_error)
nstate = IDLE;
else if(axi_ready)
nstate = CHECK;
else
nstate = SEND;
CHECK: // check if all burst has been send
if(data_error)
nstate = IDLE;
else if(all_burst_sent)
nstate = DONE;
else
nstate = CLEN;
DONE:
nstate = IDLE;
default:
nstate = IDLE;
endcase
end
//---- prepare values in IDLE and INIT state ----
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
beat_number_in_4KB_reg <= 0;
normal_addr_bias_reg <= 0;
end
else if(cstate == INIT)
begin
beat_number_in_4KB_reg <= beat_number_in_4KB;
normal_addr_bias_reg <= normal_addr_bias;
end
end
always@*
begin
case(size)
3'b010: begin beat_number_in_4KB = {2'b0,1'b1,10'b0}; normal_addr_bias = {3'b0,len_plus_1,2'b0}; end
3'b011: begin beat_number_in_4KB = {3'b0,1'b1,9'b0}; normal_addr_bias = {2'b0,len_plus_1,3'b0}; end
3'b100: begin beat_number_in_4KB = {4'b0,1'b1,8'b0}; normal_addr_bias = {1'b0,len_plus_1,4'b0}; end
3'b101: begin beat_number_in_4KB = {5'b0,1'b1,7'b0}; normal_addr_bias = {len_plus_1,5'b0}; end
3'b110: begin beat_number_in_4KB = {6'b0,1'b1,6'b0}; normal_addr_bias = {len_plus_1[6:0],6'b0}; end
3'b111: begin beat_number_in_4KB = {7'b0,1'b1,5'b0}; normal_addr_bias = {len_plus_1[5:0],7'b0}; end
default: begin beat_number_in_4KB = {7'b0,1'b1,5'b0}; normal_addr_bias = {len_plus_1[5:0],7'b0}; end
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
current_burst_addr <= 0;
remain_beat_number <= 0;
end
else if (cstate == INIT)
begin
current_burst_addr <= source_address;
remain_beat_number <= total_beat_count;
end
else if (axi_ready && (cstate == SEND))
begin
current_burst_addr <= next_burst_addr;
remain_beat_number <= remain_beat_number - {31'b0,current_burst_len};
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
current_burst_len <= 0;
else if (cstate == CLEN)
current_burst_len <= burst_len;
end
always@*
begin
case(size)
3'b010: begin init_beat_number_sent = {3'b0,source_address[11:2]}; beat_number_sent = {3'b0,current_burst_addr[11:2]}; end
3'b011: begin init_beat_number_sent = {4'b0,source_address[11:3]}; beat_number_sent = {4'b0,current_burst_addr[11:3]}; end
3'b100: begin init_beat_number_sent = {5'b0,source_address[11:4]}; beat_number_sent = {5'b0,current_burst_addr[11:4]}; end
3'b101: begin init_beat_number_sent = {6'b0,source_address[11:5]}; beat_number_sent = {6'b0,current_burst_addr[11:5]}; end
3'b110: begin init_beat_number_sent = {7'b0,source_address[11:6]}; beat_number_sent = {7'b0,current_burst_addr[11:6]}; end
3'b111: begin init_beat_number_sent = {8'b0,source_address[11:7]}; beat_number_sent = {8'b0,current_burst_addr[11:7]}; end
default: begin init_beat_number_sent = {8'b0,source_address[11:7]}; beat_number_sent = {8'b0,current_burst_addr[11:7]}; end
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
beat_number_sent_in_4KB <= 0;
else if(cstate == INIT)
beat_number_sent_in_4KB <= init_beat_number_sent;
else if(cstate == CHECK)
beat_number_sent_in_4KB <= beat_number_sent;
end
assign next_4KB_boundry = {current_burst_addr[63:12] + 52'd1, 12'd0};
assign next_burst_addr_incr = cross_4KB_boundry ? next_4KB_boundry : current_burst_addr + {51'b0,normal_addr_bias};
assign next_burst_addr = wrap_mode ? next_burst_addr_wrap : next_burst_addr_incr;
always@*
begin
case(wrap_len)
4'b0000: next_burst_addr_wrap = {source_address[63:12], next_burst_addr_incr[11:0]};
4'b0001: next_burst_addr_wrap = {source_address[63:13], next_burst_addr_incr[12:0]};
4'b0010: next_burst_addr_wrap = {source_address[63:14], next_burst_addr_incr[13:0]};
4'b0011: next_burst_addr_wrap = {source_address[63:15], next_burst_addr_incr[14:0]};
4'b0100: next_burst_addr_wrap = {source_address[63:16], next_burst_addr_incr[15:0]};
4'b0101: next_burst_addr_wrap = {source_address[63:17], next_burst_addr_incr[16:0]};
4'b0110: next_burst_addr_wrap = {source_address[63:18], next_burst_addr_incr[17:0]};
4'b0111: next_burst_addr_wrap = {source_address[63:19], next_burst_addr_incr[18:0]};
4'b1000: next_burst_addr_wrap = {source_address[63:20], next_burst_addr_incr[19:0]};
4'b1001: next_burst_addr_wrap = {source_address[63:21], next_burst_addr_incr[20:0]};
4'b1010: next_burst_addr_wrap = {source_address[63:22], next_burst_addr_incr[21:0]};
4'b1011: next_burst_addr_wrap = {source_address[63:23], next_burst_addr_incr[22:0]};
4'b1100: next_burst_addr_wrap = {source_address[63:24], next_burst_addr_incr[23:0]};
4'b1101: next_burst_addr_wrap = {source_address[63:25], next_burst_addr_incr[24:0]};
4'b1110: next_burst_addr_wrap = {source_address[63:26], next_burst_addr_incr[25:0]};
4'b1111: next_burst_addr_wrap = {source_address[63:27], next_burst_addr_incr[26:0]};
default: next_burst_addr_wrap = {source_address[63:12], next_burst_addr_incr[11:0]};
endcase
end
assign burst_len = few_beat_remain ? remain_beat_number[8:0] : (cross_4KB_boundry ? cross_4KB_burst_len[8:0] : len_plus_1);
assign cross_4KB_burst_len = beat_number_in_4KB - beat_number_sent_in_4KB;
assign all_burst_sent = (remain_beat_number == 0);
assign cross_4KB_boundry = ({4'b0,len_plus_1} > cross_4KB_burst_len);
assign few_beat_remain = (remain_beat_number < {27'b0,cross_4KB_burst_len}) && (remain_beat_number < {31'b0,len_plus_1});
assign actual_axi_len = current_burst_len - 1;
//---- generate axi output signals ----
assign axi_addr = current_burst_addr;
assign axi_len = actual_axi_len[7:0];
assign axi_valid = (cstate == SEND);
endmodule |
module axi_master_wr #(
parameter ID_WIDTH = 2,
parameter ADDR_WIDTH = 64,
parameter DATA_WIDTH = 512,
parameter AWUSER_WIDTH = 8,
parameter ARUSER_WIDTH = 8,
parameter WUSER_WIDTH = 1,
parameter RUSER_WIDTH = 1,
parameter BUSER_WIDTH = 1
)
(
input clk ,
input rst_n ,
input [031:0] i_snap_context ,
//---- AXI bus ----
// AXI write address channel
output reg [ID_WIDTH - 1:0] m_axi_awid ,
output wire [ADDR_WIDTH - 1:0] m_axi_awaddr ,
output wire [007:0] m_axi_awlen ,
output wire [002:0] m_axi_awsize ,
output wire [001:0] m_axi_awburst ,
output wire [ARUSER_WIDTH - 1:0] m_axi_awuser ,
output wire [003:0] m_axi_awcache ,
output wire [001:0] m_axi_awlock ,
output wire [002:0] m_axi_awprot ,
output wire [003:0] m_axi_awqos ,
output wire [003:0] m_axi_awregion ,
output wire m_axi_awvalid ,
input m_axi_awready ,
// AXI write data channel
output wire [DATA_WIDTH - 1:0] m_axi_wdata ,
output wire [(DATA_WIDTH/8) - 1:0] m_axi_wstrb ,
output wire m_axi_wlast ,
output wire m_axi_wvalid ,
input m_axi_wready ,
// AXI write data channel
output wire m_axi_bready ,
input [ID_WIDTH - 1:0] m_axi_bid ,
input [001:0] m_axi_bresp ,
input m_axi_bvalid ,
//---- local control ----
input engine_start_pulse,
input wrap_mode ,
input [003:0] wrap_len ,
input [063:0] target_address ,
input [031:0] wr_init_data ,
input [031:0] wr_pattern ,
input [031:0] wr_number ,
//---- local status report ----
output wire wr_done_pulse ,
output reg wr_error
);
wire [002:0] wr_size;
wire [007:0] wr_len;
wire [004:0] wr_id_num;
wire [008:0] wr_len_plus_1;
reg [039:0] total_wr_beat_count;
reg [031:0] wr_burst_cnt;
wire burst_sent;
wire wr_engine_start;
wire resp_get;
wire addr_send_done;
reg wr_wait_done;
assign wr_engine_start = engine_start_pulse && (wr_number != 0);
//---- signals for AXI advanced features ----
assign m_axi_awsize = wr_pattern[2:0]; // 2^6=512
assign m_axi_awburst = 2'd1; // INCR mode for memory access
assign m_axi_awcache = 4'd3; // Normal Non-cacheable Bufferable
assign m_axi_awuser = i_snap_context[ARUSER_WIDTH - 1:0];
assign m_axi_awprot = 3'd0;
assign m_axi_awqos = 4'd0;
assign m_axi_awregion = 4'd0; //?
assign m_axi_awlock = 2'b00; // normal access
assign m_axi_bready = 1'b1;
assign burst_sent = m_axi_awvalid && m_axi_awready;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
m_axi_awid <= 0;
else if(burst_sent && (m_axi_awid == wr_id_num))
m_axi_awid <= 0;
else if(burst_sent)
m_axi_awid <= m_axi_awid + 1;
end
assign wr_size = wr_pattern[2:0];
assign wr_len = wr_pattern[15:8];
assign wr_id_num = wr_pattern[20:16];
assign wr_len_plus_1 = {1'b0, wr_len} + 1'b1;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
total_wr_beat_count <= 0;
else if(wr_engine_start)
total_wr_beat_count <= {8'b0, wr_number} * ({31'b0, wr_len_plus_1});
end
/***********************************************************************
* write addr send channel *
***********************************************************************/
addr_send_channel mwr_addr_send (
.clk (clk ),
.rst_n (rst_n ),
.wrap_mode (wrap_mode ),
.wrap_len (wrap_len ),
.engine_start (wr_engine_start ),
.source_address (target_address ),
.size (wr_size ),
.len (wr_len ),
.number (wr_number ),
.total_beat_count (total_wr_beat_count),
.data_error (1'b0 ),
.addr_send_done (addr_send_done ),
.axi_addr (m_axi_awaddr ),
.axi_len (m_axi_awlen ),
.axi_valid (m_axi_awvalid ),
.axi_ready (m_axi_awready )
);
/***********************************************************************
* write data send channel *
***********************************************************************/
wr_data_send_channel mwr_data_send (
.clk (clk ),
.rst_n (rst_n ),
.m_axi_wdata (m_axi_wdata ),
.m_axi_wlast (m_axi_wlast ),
.m_axi_wvalid (m_axi_wvalid ),
.m_axi_wstrb (m_axi_wstrb ),
.m_axi_wready (m_axi_wready ),
.total_wr_beat_count (total_wr_beat_count),
.wr_engine_start (wr_engine_start ),
.wrap_mode (wrap_mode ),
.wrap_len (wrap_len ),
.wr_size (wr_size ),
.wr_len (wr_len ),
.wr_init_data (wr_init_data )
);
/***********************************************************************
* write response channel *
***********************************************************************/
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
wr_wait_done <= 1'b0;
else if(addr_send_done)
wr_wait_done <= 1'b1;
else if(wr_done_pulse)
wr_wait_done <= 1'b0;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
wr_burst_cnt <= 0;
else if(burst_sent && !resp_get)
wr_burst_cnt <= wr_burst_cnt + 1'b1;
else if(!burst_sent && resp_get)
wr_burst_cnt <= wr_burst_cnt - 1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
wr_error <= 1'b0;
else if(resp_get)
wr_error <= (m_axi_bresp != 0);
else if(wr_error)
wr_error <= 1'b0;
end
assign resp_get = m_axi_bvalid && m_axi_bready;
assign wr_done_pulse = wr_wait_done && (wr_burst_cnt == 0);
endmodule |
module axi_master_rd #(
parameter ID_WIDTH = 2,
parameter ADDR_WIDTH = 64,
parameter DATA_WIDTH = 512,
parameter AWUSER_WIDTH = 8,
parameter ARUSER_WIDTH = 8,
parameter WUSER_WIDTH = 1,
parameter RUSER_WIDTH = 1,
parameter BUSER_WIDTH = 1
)
(
input clk ,
input rst_n ,
input [031:0] i_snap_context ,
//---- AXI bus ----
// AXI read address channel
output reg [ID_WIDTH - 1:0] m_axi_arid ,
output wire[ADDR_WIDTH - 1:0] m_axi_araddr ,
output wire[007:0] m_axi_arlen ,
output wire[002:0] m_axi_arsize ,
output wire[001:0] m_axi_arburst ,
output wire[ARUSER_WIDTH - 1:0] m_axi_aruser ,
output wire[003:0] m_axi_arcache ,
output wire[001:0] m_axi_arlock ,
output wire[002:0] m_axi_arprot ,
output wire[003:0] m_axi_arqos ,
output wire[003:0] m_axi_arregion ,
output wire m_axi_arvalid ,
input m_axi_arready ,
// AXI read data channel
output wire m_axi_rready ,
input [ID_WIDTH - 1:0] m_axi_rid ,
input [DATA_WIDTH - 1:0] m_axi_rdata ,
input [001:0] m_axi_rresp ,
input m_axi_rlast ,
input m_axi_rvalid ,
//---- local control ----
input engine_start_pulse,
input wrap_mode ,
input [003:0] wrap_len ,
input [063:0] source_address ,
input [031:0] rd_init_data ,
input [031:0] rd_pattern ,
input [031:0] rd_number ,
//---- local status report ----
output wire rd_done_pulse ,
output wire[001:0] rd_error ,
output wire[063:0] rd_error_info
);
wire [002:0] rd_size;
wire [007:0] rd_len;
wire [004:0] rd_id_num;
wire [008:0] rd_len_plus_1;
reg [039:0] total_rd_beat_count;
wire burst_sent;
wire rd_engine_start;
wire addr_send_done;
assign rd_engine_start = engine_start_pulse && (rd_number != 0);
//---- signals for AXI advanced features ----
assign m_axi_arsize = rd_pattern[2:0]; // 2^6=512
assign m_axi_arburst = 2'd1; // INCR mode for memory access
assign m_axi_arcache = 4'd3; // Normal Non-cacheable Bufferable
assign m_axi_aruser = i_snap_context[ARUSER_WIDTH - 1:0];
assign m_axi_arprot = 3'd0;
assign m_axi_arqos = 4'd0;
assign m_axi_arregion = 4'd0; //?
assign m_axi_arlock = 2'b00; // normal access
assign burst_sent = m_axi_arvalid && m_axi_arready;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
m_axi_arid <= 0;
else if(burst_sent && (m_axi_arid == rd_id_num))
m_axi_arid <= 0;
else if(burst_sent)
m_axi_arid <= m_axi_arid + 1;
end
assign rd_size = rd_pattern[2:0];
assign rd_len = rd_pattern[15:8];
assign rd_id_num = rd_pattern[20:16];
assign rd_len_plus_1 = {1'b0, rd_len} + 1'b1;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
total_rd_beat_count <= 0;
else if(rd_engine_start)
total_rd_beat_count <= {8'b0, rd_number} * ({31'b0, rd_len_plus_1});
end
/***********************************************************************
* read burst send channel *
***********************************************************************/
addr_send_channel mrd_addr_send (
.clk (clk ),
.rst_n (rst_n ),
.engine_start (rd_engine_start ),
.wrap_mode (wrap_mode ),
.wrap_len (wrap_len ),
.source_address (source_address ),
.size (rd_size ),
.len (rd_len ),
.number (rd_number ),
.total_beat_count (total_rd_beat_count),
.data_error (1'b0 ),
.addr_send_done (addr_send_done ),
.axi_addr (m_axi_araddr ),
.axi_len (m_axi_arlen ),
.axi_valid (m_axi_arvalid ),
.axi_ready (m_axi_arready )
);
rd_result_check_channel mrd_check (
.clk (clk ),
.rst_n (rst_n ),
.m_axi_rid (m_axi_rid ),
.m_axi_rdata (m_axi_rdata ),
.m_axi_rlast (m_axi_rlast ),
.m_axi_rvalid (m_axi_rvalid ),
.m_axi_rready (m_axi_rready ),
.m_axi_rresp (m_axi_rresp ),
.total_rd_beat_count (total_rd_beat_count),
.rd_engine_start (rd_engine_start ),
.wrap_mode (wrap_mode ),
.wrap_len (wrap_len ),
.rd_id_num (rd_id_num ),
.rd_len (rd_len ),
.rd_size (rd_size ),
.rd_init_data (rd_init_data ),
.rd_done (rd_done_pulse ),
.rd_error (rd_error ),
.rd_error_info (rd_error_info )
);
endmodule |
module ram_single_port (clk, we, addr, data_in, data_out);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 5;
parameter DEPTH = 2**ADDR_WIDTH;
input clk, we;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
integer i;
initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;
always @(posedge clk) begin
addr_reg <= addr;
if (we)
ram[addr] <= data_in;
end
assign data_out = ram[addr_reg];
///// clk ___^^^___^^^___^^^___^^^___^^^___
//
// we ___^^^^^^______^^^^^^^^^^^^______
// di ___XXXXXX______YYYYYYZZZZZZ______
// addr ___AAAAAA______BBBBBBCCCCCC______
//addr_reg _________AAAAAA______BBBBBBCCCCCC
// do _________XXXXXX______YYYYYYZZZZZZ
endmodule |
module action_wrapper #(
// Parameters of Axi Master Bus Interface AXI_CARD_MEM0 ; to DDR memory
// DDR paramaters are not used but still need to stay here to match the
// above hierarchy.
parameter C_M_AXI_CARD_MEM0_ID_WIDTH = 4,
parameter C_M_AXI_CARD_MEM0_ADDR_WIDTH = 33,
parameter C_M_AXI_CARD_MEM0_DATA_WIDTH = 512,
parameter C_M_AXI_CARD_MEM0_AWUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_ARUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_WUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_RUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_BUSER_WIDTH = 1,
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
parameter C_S_AXI_CTRL_REG_DATA_WIDTH = 32,
parameter C_S_AXI_CTRL_REG_ADDR_WIDTH = 32,
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
parameter C_M_AXI_HOST_MEM_ID_WIDTH = 5,
parameter C_M_AXI_HOST_MEM_ADDR_WIDTH = 64,
parameter C_M_AXI_HOST_MEM_DATA_WIDTH = 1024,
parameter C_M_AXI_HOST_MEM_AWUSER_WIDTH = 9,
parameter C_M_AXI_HOST_MEM_ARUSER_WIDTH = 9,
parameter C_M_AXI_HOST_MEM_WUSER_WIDTH = 9,
parameter C_M_AXI_HOST_MEM_RUSER_WIDTH = 9,
parameter C_M_AXI_HOST_MEM_BUSER_WIDTH = 9,
parameter INT_BITS = 64,
parameter CONTEXT_BITS = 9
)
(
input ap_clk ,
input ap_rst_n ,
output interrupt ,
output [INT_BITS-1 : 0] interrupt_src ,
output [CONTEXT_BITS-1 : 0] interrupt_ctx ,
input interrupt_ack ,
//
// AXI Control Register Interface
input [C_S_AXI_CTRL_REG_ADDR_WIDTH-1 : 0] s_axi_ctrl_reg_araddr ,
output s_axi_ctrl_reg_arready ,
input s_axi_ctrl_reg_arvalid ,
input [C_S_AXI_CTRL_REG_ADDR_WIDTH-1 : 0] s_axi_ctrl_reg_awaddr ,
output s_axi_ctrl_reg_awready ,
input s_axi_ctrl_reg_awvalid ,
input s_axi_ctrl_reg_bready ,
output [1 : 0] s_axi_ctrl_reg_bresp ,
output s_axi_ctrl_reg_bvalid ,
output [C_S_AXI_CTRL_REG_DATA_WIDTH-1 : 0] s_axi_ctrl_reg_rdata ,
input s_axi_ctrl_reg_rready ,
output [1 : 0] s_axi_ctrl_reg_rresp ,
output s_axi_ctrl_reg_rvalid ,
input [C_S_AXI_CTRL_REG_DATA_WIDTH-1 : 0] s_axi_ctrl_reg_wdata ,
output s_axi_ctrl_reg_wready ,
input [(C_S_AXI_CTRL_REG_DATA_WIDTH/8)-1 : 0] s_axi_ctrl_reg_wstrb ,
input s_axi_ctrl_reg_wvalid ,
//
// AXI Host Memory Interface
output [C_M_AXI_HOST_MEM_ADDR_WIDTH-1 : 0] m_axi_host_mem_araddr ,
output [1 : 0] m_axi_host_mem_arburst ,
output [3 : 0] m_axi_host_mem_arcache ,
output [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0] m_axi_host_mem_arid ,
output [7 : 0] m_axi_host_mem_arlen ,
output [1 : 0] m_axi_host_mem_arlock ,
output [2 : 0] m_axi_host_mem_arprot ,
output [3 : 0] m_axi_host_mem_arqos ,
input m_axi_host_mem_arready ,
output [3 : 0] m_axi_host_mem_arregion ,
output [2 : 0] m_axi_host_mem_arsize ,
output [C_M_AXI_HOST_MEM_ARUSER_WIDTH-1 : 0] m_axi_host_mem_aruser ,
output m_axi_host_mem_arvalid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH-1 : 0] m_axi_host_mem_awaddr ,
output [1 : 0] m_axi_host_mem_awburst ,
output [3 : 0] m_axi_host_mem_awcache ,
output [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0] m_axi_host_mem_awid ,
output [7 : 0] m_axi_host_mem_awlen ,
output [1 : 0] m_axi_host_mem_awlock ,
output [2 : 0] m_axi_host_mem_awprot ,
output [3 : 0] m_axi_host_mem_awqos ,
input m_axi_host_mem_awready ,
output [3 : 0] m_axi_host_mem_awregion ,
output [2 : 0] m_axi_host_mem_awsize ,
output [C_M_AXI_HOST_MEM_AWUSER_WIDTH-1 : 0] m_axi_host_mem_awuser ,
output m_axi_host_mem_awvalid ,
input [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0] m_axi_host_mem_bid ,
output m_axi_host_mem_bready ,
input [1 : 0] m_axi_host_mem_bresp ,
input [C_M_AXI_HOST_MEM_BUSER_WIDTH-1 : 0] m_axi_host_mem_buser ,
input m_axi_host_mem_bvalid ,
input [C_M_AXI_HOST_MEM_DATA_WIDTH-1 : 0] m_axi_host_mem_rdata ,
input [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0] m_axi_host_mem_rid ,
input m_axi_host_mem_rlast ,
output m_axi_host_mem_rready ,
input [1 : 0] m_axi_host_mem_rresp ,
input [C_M_AXI_HOST_MEM_RUSER_WIDTH-1 : 0] m_axi_host_mem_ruser ,
input m_axi_host_mem_rvalid ,
output [C_M_AXI_HOST_MEM_DATA_WIDTH-1 : 0] m_axi_host_mem_wdata ,
output m_axi_host_mem_wlast ,
input m_axi_host_mem_wready ,
output [(C_M_AXI_HOST_MEM_DATA_WIDTH/8)-1 : 0] m_axi_host_mem_wstrb ,
output [C_M_AXI_HOST_MEM_WUSER_WIDTH-1 : 0] m_axi_host_mem_wuser ,
output m_axi_host_mem_wvalid
);
// Make wuser stick to 0
assign m_axi_host_mem_wuser = 0;
action_single_engine #(
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
.C_S_AXI_CTRL_REG_DATA_WIDTH (C_S_AXI_CTRL_REG_DATA_WIDTH ),
.C_S_AXI_CTRL_REG_ADDR_WIDTH (C_S_AXI_CTRL_REG_ADDR_WIDTH ),
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
.C_M_AXI_HOST_MEM_ID_WIDTH (C_M_AXI_HOST_MEM_ID_WIDTH ),
.C_M_AXI_HOST_MEM_ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.C_M_AXI_HOST_MEM_DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH ),
.C_M_AXI_HOST_MEM_AWUSER_WIDTH (C_M_AXI_HOST_MEM_AWUSER_WIDTH ),
.C_M_AXI_HOST_MEM_ARUSER_WIDTH (C_M_AXI_HOST_MEM_ARUSER_WIDTH ),
.C_M_AXI_HOST_MEM_WUSER_WIDTH (C_M_AXI_HOST_MEM_WUSER_WIDTH ),
.C_M_AXI_HOST_MEM_RUSER_WIDTH (C_M_AXI_HOST_MEM_RUSER_WIDTH ),
.C_M_AXI_HOST_MEM_BUSER_WIDTH (C_M_AXI_HOST_MEM_BUSER_WIDTH )
) action_hdl_single_engine (
.clk (ap_clk),
.rst_n (ap_rst_n),
//---- AXI bus interfaced with SNAP core ----
// AXI write address channel
.m_axi_snap_awid (m_axi_host_mem_awid),
.m_axi_snap_awaddr (m_axi_host_mem_awaddr),
.m_axi_snap_awlen (m_axi_host_mem_awlen),
.m_axi_snap_awsize (m_axi_host_mem_awsize),
.m_axi_snap_awburst (m_axi_host_mem_awburst),
.m_axi_snap_awcache (m_axi_host_mem_awcache),
.m_axi_snap_awlock (m_axi_host_mem_awlock),
.m_axi_snap_awprot (m_axi_host_mem_awprot),
.m_axi_snap_awqos (m_axi_host_mem_awqos),
.m_axi_snap_awregion (m_axi_host_mem_awregion),
.m_axi_snap_awuser (m_axi_host_mem_awuser),
.m_axi_snap_awvalid (m_axi_host_mem_awvalid),
.m_axi_snap_awready (m_axi_host_mem_awready),
// AXI write data channel
//.m_axi_snap_wid (0),
.m_axi_snap_wdata (m_axi_host_mem_wdata),
.m_axi_snap_wstrb (m_axi_host_mem_wstrb),
.m_axi_snap_wlast (m_axi_host_mem_wlast),
.m_axi_snap_wvalid (m_axi_host_mem_wvalid),
.m_axi_snap_wready (m_axi_host_mem_wready),
// AXI write response channel
.m_axi_snap_bready (m_axi_host_mem_bready),
.m_axi_snap_bid (m_axi_host_mem_bid),
.m_axi_snap_bresp (m_axi_host_mem_bresp),
.m_axi_snap_bvalid (m_axi_host_mem_bvalid),
// AXI read address channel
.m_axi_snap_arid (m_axi_host_mem_arid),
.m_axi_snap_araddr (m_axi_host_mem_araddr),
.m_axi_snap_arlen (m_axi_host_mem_arlen),
.m_axi_snap_arsize (m_axi_host_mem_arsize),
.m_axi_snap_arburst (m_axi_host_mem_arburst),
.m_axi_snap_aruser (m_axi_host_mem_aruser),
.m_axi_snap_arcache (m_axi_host_mem_arcache),
.m_axi_snap_arlock (m_axi_host_mem_arlock),
.m_axi_snap_arprot (m_axi_host_mem_arprot),
.m_axi_snap_arqos (m_axi_host_mem_arqos),
.m_axi_snap_arregion (m_axi_host_mem_arregion),
.m_axi_snap_arvalid (m_axi_host_mem_arvalid),
.m_axi_snap_arready (m_axi_host_mem_arready),
// AXI ead data channel
.m_axi_snap_rready (m_axi_host_mem_rready),
.m_axi_snap_rid (m_axi_host_mem_rid),
.m_axi_snap_rdata (m_axi_host_mem_rdata),
.m_axi_snap_rresp (m_axi_host_mem_rresp),
.m_axi_snap_rlast (m_axi_host_mem_rlast),
.m_axi_snap_rvalid (m_axi_host_mem_rvalid),
//---- AXI Lite bus interfaced with SNAP core ----
// AXI write address channel
.s_axi_snap_awready (s_axi_ctrl_reg_awready),
.s_axi_snap_awaddr (s_axi_ctrl_reg_awaddr),
.s_axi_snap_awvalid (s_axi_ctrl_reg_awvalid),
// axi write data channel
.s_axi_snap_wready (s_axi_ctrl_reg_wready),
.s_axi_snap_wdata (s_axi_ctrl_reg_wdata),
.s_axi_snap_wstrb (s_axi_ctrl_reg_wstrb),
.s_axi_snap_wvalid (s_axi_ctrl_reg_wvalid),
// AXI response channel
.s_axi_snap_bresp (s_axi_ctrl_reg_bresp),
.s_axi_snap_bvalid (s_axi_ctrl_reg_bvalid),
.s_axi_snap_bready (s_axi_ctrl_reg_bready),
// AXI read address channel
.s_axi_snap_arready (s_axi_ctrl_reg_arready),
.s_axi_snap_arvalid (s_axi_ctrl_reg_arvalid),
.s_axi_snap_araddr (s_axi_ctrl_reg_araddr),
// AXI read data channel
.s_axi_snap_rdata (s_axi_ctrl_reg_rdata),
.s_axi_snap_rresp (s_axi_ctrl_reg_rresp),
.s_axi_snap_rready (s_axi_ctrl_reg_rready),
.s_axi_snap_rvalid (s_axi_ctrl_reg_rvalid),
.i_action_type (32'h10142002), //Should match ACTION_TYPE with sw
.i_action_version (32'h00000002) //Hardware Version
);
endmodule |
module action_single_engine # (
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
parameter C_S_AXI_CTRL_REG_DATA_WIDTH = 32,
parameter C_S_AXI_CTRL_REG_ADDR_WIDTH = 32,
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
parameter C_M_AXI_HOST_MEM_ID_WIDTH = 2,
parameter C_M_AXI_HOST_MEM_ADDR_WIDTH = 64,
parameter C_M_AXI_HOST_MEM_DATA_WIDTH = 1024,
parameter C_M_AXI_HOST_MEM_AWUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_ARUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_WUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_RUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_BUSER_WIDTH = 1
)
(
input clk ,
input rst_n ,
//---- AXI bus interfaced with SNAP core ----
// AXI write address channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_awid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH - 1:0] m_axi_snap_awaddr ,
output [0007:0] m_axi_snap_awlen ,
output [0002:0] m_axi_snap_awsize ,
output [0001:0] m_axi_snap_awburst ,
output [0003:0] m_axi_snap_awcache ,
output [0001:0] m_axi_snap_awlock ,
output [0002:0] m_axi_snap_awprot ,
output [0003:0] m_axi_snap_awqos ,
output [0003:0] m_axi_snap_awregion ,
output [C_M_AXI_HOST_MEM_AWUSER_WIDTH - 1:0] m_axi_snap_awuser ,
output m_axi_snap_awvalid ,
input m_axi_snap_awready ,
// AXI write data channel
output [C_M_AXI_HOST_MEM_DATA_WIDTH - 1:0] m_axi_snap_wdata ,
output [(C_M_AXI_HOST_MEM_DATA_WIDTH/8) -1:0]m_axi_snap_wstrb ,
output m_axi_snap_wlast ,
output m_axi_snap_wvalid ,
input m_axi_snap_wready ,
// AXI write response channel
output m_axi_snap_bready ,
input [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_bid ,
input [0001:0] m_axi_snap_bresp ,
input m_axi_snap_bvalid ,
// AXI read address channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_arid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH - 1:0] m_axi_snap_araddr ,
output [0007:0] m_axi_snap_arlen ,
output [0002:0] m_axi_snap_arsize ,
output [0001:0] m_axi_snap_arburst ,
output [C_M_AXI_HOST_MEM_ARUSER_WIDTH - 1:0] m_axi_snap_aruser ,
output [0003:0] m_axi_snap_arcache ,
output [0001:0] m_axi_snap_arlock ,
output [0002:0] m_axi_snap_arprot ,
output [0003:0] m_axi_snap_arqos ,
output [0003:0] m_axi_snap_arregion ,
output m_axi_snap_arvalid ,
input m_axi_snap_arready ,
// AXI ead data channel
output m_axi_snap_rready ,
input [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_rid ,
input [C_M_AXI_HOST_MEM_DATA_WIDTH - 1:0] m_axi_snap_rdata ,
input [0001:0] m_axi_snap_rresp ,
input m_axi_snap_rlast ,
input m_axi_snap_rvalid ,
//---- AXI Lite bus interfaced with SNAP core ----
// AXI write address channel
output s_axi_snap_awready ,
input [C_S_AXI_CTRL_REG_ADDR_WIDTH - 1:0] s_axi_snap_awaddr ,
input s_axi_snap_awvalid ,
// axi write data channel
output s_axi_snap_wready ,
input [C_S_AXI_CTRL_REG_DATA_WIDTH - 1:0] s_axi_snap_wdata ,
input [(C_S_AXI_CTRL_REG_DATA_WIDTH/8) -1:0]s_axi_snap_wstrb ,
input s_axi_snap_wvalid ,
// AXI response channel
output [0001:0] s_axi_snap_bresp ,
output s_axi_snap_bvalid ,
input s_axi_snap_bready ,
// AXI read address channel
output s_axi_snap_arready ,
input s_axi_snap_arvalid ,
input [C_S_AXI_CTRL_REG_ADDR_WIDTH - 1:0] s_axi_snap_araddr ,
// AXI read data channel
output [C_S_AXI_CTRL_REG_DATA_WIDTH - 1:0] s_axi_snap_rdata ,
output [0001:0] s_axi_snap_rresp ,
input s_axi_snap_rready ,
output s_axi_snap_rvalid ,
// Other signals
input [31:0] i_action_type ,
input [31:0] i_action_version
);
wire engine_start_pulse ;
wire wrap_mode ;
wire [03:0] wrap_len ;
wire [63:0] source_address ;
wire [63:0] target_address ;
wire [31:0] rd_init_data ;
wire [31:0] wr_init_data ;
wire [31:0] rd_pattern ;
wire [31:0] rd_number ;
wire [31:0] wr_pattern ;
wire [31:0] wr_number ;
wire rd_done_pulse ;
wire wr_done_pulse ;
wire [1:0] rd_error ;
wire [63:0] rd_error_info ;
wire tt_arvalid ; //arvalid & arready
wire tt_rlast ; //rlast & rvalid & rready
wire tt_awvalid ; //awvalid & awready
wire tt_bvalid ; //bvalid & bready
wire [4:0] tt_arid ;
wire [4:0] tt_awid ;
wire [4:0] tt_rid ;
wire [4:0] tt_bid ;
wire [31:0] snap_context ;
//---- registers hub for AXI Lite interface ----
axi_lite_slave #(
.DATA_WIDTH (C_S_AXI_CTRL_REG_DATA_WIDTH ),
.ADDR_WIDTH (C_S_AXI_CTRL_REG_ADDR_WIDTH )
) maxi_lite_slave (
.clk ( clk ) ,
.rst_n ( rst_n ) ,
.s_axi_awready ( s_axi_snap_awready ) ,
.s_axi_awaddr ( s_axi_snap_awaddr ) ,//32b
.s_axi_awvalid ( s_axi_snap_awvalid ) ,
.s_axi_wready ( s_axi_snap_wready ) ,
.s_axi_wdata ( s_axi_snap_wdata ) ,//32b
.s_axi_wstrb ( s_axi_snap_wstrb ) ,//4b
.s_axi_wvalid ( s_axi_snap_wvalid ) ,
.s_axi_bresp ( s_axi_snap_bresp ) ,//2b
.s_axi_bvalid ( s_axi_snap_bvalid ) ,
.s_axi_bready ( s_axi_snap_bready ) ,
.s_axi_arready ( s_axi_snap_arready ) ,
.s_axi_arvalid ( s_axi_snap_arvalid ) ,
.s_axi_araddr ( s_axi_snap_araddr ) ,//32b
.s_axi_rdata ( s_axi_snap_rdata ) ,//32b
.s_axi_rresp ( s_axi_snap_rresp ) ,//2b
.s_axi_rready ( s_axi_snap_rready ) ,
.s_axi_rvalid ( s_axi_snap_rvalid ) ,
.engine_start_pulse ( engine_start_pulse ) ,
.wrap_mode ( wrap_mode ) ,
.wrap_len ( wrap_len ) ,
.source_address ( source_address ) ,
.target_address ( target_address ) ,
.rd_init_data ( rd_init_data ) ,
.wr_init_data ( wr_init_data ) ,
.rd_pattern ( rd_pattern ) ,
.rd_number ( rd_number ) ,
.wr_pattern ( wr_pattern ) ,
.wr_number ( wr_number ) ,
.rd_done_pulse ( rd_done_pulse ) ,
.wr_done_pulse ( wr_done_pulse ) ,
.rd_error ( rd_error ) ,
.rd_error_info ( rd_error_info ) ,
.wr_error ( wr_error ) ,
.tt_arvalid ( tt_arvalid ) , //arvalid & arready
.tt_rlast ( tt_rlast ) , //rlast & rvalid & rready
.tt_awvalid ( tt_awvalid ) , //awvalid & awready
.tt_bvalid ( tt_bvalid ) , //bvalid & bready
.tt_arid ( tt_arid ) ,
.tt_awid ( tt_awid ) ,
.tt_rid ( tt_rid ) ,
.tt_bid ( tt_bid ) ,
.i_action_type ( i_action_type ) ,
.i_action_version ( i_action_version ) ,
.o_snap_context ( snap_context )
);
assign tt_arvalid = m_axi_snap_arvalid && m_axi_snap_arready;
assign tt_rlast = m_axi_snap_rvalid && m_axi_snap_rready && m_axi_snap_rlast;
assign tt_arid = m_axi_snap_arid;
assign tt_rid = m_axi_snap_rid;
assign tt_awvalid = m_axi_snap_awvalid && m_axi_snap_awready;
assign tt_bvalid = m_axi_snap_bvalid && m_axi_snap_bready;
assign tt_awid = m_axi_snap_awid;
assign tt_bid = m_axi_snap_bid;
//---- writing channel of AXI master interface facing SNAP ----
axi_master_wr#(
.ID_WIDTH (C_M_AXI_HOST_MEM_ID_WIDTH ),
.ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH ),
.AWUSER_WIDTH (C_M_AXI_HOST_MEM_AWUSER_WIDTH ),
.ARUSER_WIDTH (C_M_AXI_HOST_MEM_ARUSER_WIDTH ),
.WUSER_WIDTH (C_M_AXI_HOST_MEM_WUSER_WIDTH ),
.RUSER_WIDTH (C_M_AXI_HOST_MEM_RUSER_WIDTH ),
.BUSER_WIDTH (C_M_AXI_HOST_MEM_BUSER_WIDTH )
) maxi_master_wr(
.clk (clk ),
.rst_n (rst_n),
.m_axi_awid (m_axi_snap_awid ),
.m_axi_awaddr (m_axi_snap_awaddr ),
.m_axi_awlen (m_axi_snap_awlen ),
.m_axi_awsize (m_axi_snap_awsize ),
.m_axi_awburst (m_axi_snap_awburst ),
.m_axi_awcache (m_axi_snap_awcache ),
.m_axi_awlock (m_axi_snap_awlock ),
.m_axi_awprot (m_axi_snap_awprot ),
.m_axi_awqos (m_axi_snap_awqos ),
.m_axi_awregion (m_axi_snap_awregion),
.m_axi_awuser (m_axi_snap_awuser ),
.m_axi_awvalid (m_axi_snap_awvalid ),
.m_axi_awready (m_axi_snap_awready ),
.m_axi_wdata (m_axi_snap_wdata ),
.m_axi_wstrb (m_axi_snap_wstrb ),
.m_axi_wlast (m_axi_snap_wlast ),
.m_axi_wvalid (m_axi_snap_wvalid ),
.m_axi_wready (m_axi_snap_wready ),
.m_axi_bready (m_axi_snap_bready ),
.m_axi_bid (m_axi_snap_bid ),
.m_axi_bresp (m_axi_snap_bresp ),
.m_axi_bvalid (m_axi_snap_bvalid ),
.engine_start_pulse (engine_start_pulse ),
.wrap_mode ( wrap_mode ) ,
.wrap_len ( wrap_len ) ,
.target_address (target_address ),
.wr_init_data (wr_init_data ),
.wr_pattern (wr_pattern ),
.wr_number (wr_number ),
.wr_done_pulse (wr_done_pulse ),
.wr_error (wr_error ),
.i_snap_context (snap_context )
);
//---- writing channel of AXI master interface facing SNAP ----
axi_master_rd#(
.ID_WIDTH (C_M_AXI_HOST_MEM_ID_WIDTH ),
.ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH ),
.AWUSER_WIDTH (C_M_AXI_HOST_MEM_AWUSER_WIDTH ),
.ARUSER_WIDTH (C_M_AXI_HOST_MEM_ARUSER_WIDTH ),
.WUSER_WIDTH (C_M_AXI_HOST_MEM_WUSER_WIDTH ),
.RUSER_WIDTH (C_M_AXI_HOST_MEM_RUSER_WIDTH ),
.BUSER_WIDTH (C_M_AXI_HOST_MEM_BUSER_WIDTH )
) maxi_master_rd(
.clk (clk ),
.rst_n (rst_n),
.m_axi_arid (m_axi_snap_arid ),
.m_axi_araddr (m_axi_snap_araddr ),
.m_axi_arlen (m_axi_snap_arlen ),
.m_axi_arsize (m_axi_snap_arsize ),
.m_axi_arburst (m_axi_snap_arburst ),
.m_axi_aruser (m_axi_snap_aruser ),
.m_axi_arcache (m_axi_snap_arcache ),
.m_axi_arlock (m_axi_snap_arlock ),
.m_axi_arprot (m_axi_snap_arprot ),
.m_axi_arqos (m_axi_snap_arqos ),
.m_axi_arregion (m_axi_snap_arregion),
.m_axi_arvalid (m_axi_snap_arvalid ),
.m_axi_arready (m_axi_snap_arready ),
.m_axi_rready (m_axi_snap_rready ),
.m_axi_rid (m_axi_snap_rid ),
.m_axi_rdata (m_axi_snap_rdata ),
.m_axi_rresp (m_axi_snap_rresp ),
.m_axi_rlast (m_axi_snap_rlast ),
.m_axi_rvalid (m_axi_snap_rvalid ),
.engine_start_pulse (engine_start_pulse ),
.wrap_mode ( wrap_mode ) ,
.wrap_len ( wrap_len ) ,
.source_address (source_address ),
.rd_init_data (rd_init_data ),
.rd_pattern (rd_pattern ),
.rd_number (rd_number ),
.rd_done_pulse (rd_done_pulse ),
.rd_error (rd_error ),
.rd_error_info (rd_error_info ),
.i_snap_context (snap_context )
);
endmodule |
module axi_lite_slave #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32
)(
input clk ,
input rst_n ,
//---- AXI Lite bus----
// AXI write address channel
output reg s_axi_awready ,
input [ADDR_WIDTH - 1:0] s_axi_awaddr ,
input s_axi_awvalid ,
// axi write data channel
output reg s_axi_wready ,
input [DATA_WIDTH - 1:0] s_axi_wdata ,
input [(DATA_WIDTH/8) - 1:0]s_axi_wstrb ,
input s_axi_wvalid ,
// AXI response channel
output [01:0] s_axi_bresp ,
output reg s_axi_bvalid ,
input s_axi_bready ,
// AXI read address channel
output reg s_axi_arready ,
input s_axi_arvalid ,
input [ADDR_WIDTH - 1:0] s_axi_araddr ,
// AXI read data channel
output reg [DATA_WIDTH - 1:0] s_axi_rdata ,
output [01:0] s_axi_rresp ,
input s_axi_rready ,
output reg s_axi_rvalid ,
//---- local control ----
output wire engine_start_pulse,
output wire wrap_mode , // 1 for wrap, 0 for incr
output wire [03:0] wrap_len ,
output [63:0] source_address ,
output [63:0] target_address ,
output [31:0] rd_init_data ,
output [31:0] wr_init_data ,
output [31:0] rd_pattern ,
output [31:0] rd_number ,
output [31:0] wr_pattern ,
output [31:0] wr_number ,
//---- local status ----
input rd_done_pulse ,
input wr_done_pulse ,
input [01:0] rd_error , //bit 0 means response error, bit 1 means data error
input [63:0] rd_error_info ,
input wr_error , //write response error
input tt_arvalid , //arvalid & arready
input tt_rlast , //rlast & rvalid & rready
input tt_awvalid , //awvalid & awready
input tt_bvalid , //bvalid & bready
input [4:0] tt_arid ,
input [4:0] tt_awid ,
input [4:0] tt_rid ,
input [4:0] tt_bid ,
//---- snap status ----
input [31:0] i_action_type ,
input [31:0] i_action_version ,
output [31:0] o_snap_context
);
//---- declarations ----
wire[31:0] REG_snap_control_rd;
wire[31:0] REG_user_status; /*RO*/
wire[31:0] regw_snap_status;
wire[31:0] regw_snap_int_enable;
wire[31:0] regw_snap_context;
wire[31:0] regw_control;
wire[31:0] regw_mode;
wire[31:0] regw_init_rdata;
wire[31:0] regw_init_wdata;
wire[31:0] regw_rd_pattern;
wire[31:0] regw_rd_number;
wire[31:0] regw_wr_pattern;
wire[31:0] regw_wr_number;
wire[63:0] regw_source_address;
wire[63:0] regw_target_address;
wire [31:0] regw_soft_reset;
reg [31:0] write_address;
wire[31:0] wr_mask;
reg [31:0] current_cycle_L;
reg [15:0] current_cycle_H;
wire soft_reset;
///////////////////////////////////////////////////
//***********************************************//
//> REGISTERS <//
//***********************************************//
// //
/**/ reg [31:0] REG_snap_control ; /**/
/**/ reg [31:0] REG_snap_int_enable ; /**/
/**/ reg [31:0] REG_snap_context ; /**/
/*-----------------------------------------------*/
/**/ reg [63:0] REG_error_info ; /*RO*/
/**/ reg [31:0] REG_user_control ; /*RW*/
/**/ reg [31:0] REG_user_mode ; /*RW*/
/**/ reg [31:0] REG_init_rdata ; /*RW*/
/**/ reg [31:0] REG_init_wdata ; /*RW*/
/**/ wire [31:0] cyc_tt_rd_cmd ; /*RO, from RAM data_out*/
/**/ wire [31:0] cyc_tt_rd_rsp ; /*RO, from RAM data_out*/
/**/ wire [31:0] cyc_tt_wr_cmd ; /*RO, from RAM data_out*/
/**/ wire [31:0] cyc_tt_wr_rsp ; /*RO, from RAM data_out*/
/**/ wire [4:0] dout_arid ; /*RO, from RAM data_out*/
/**/ wire [4:0] dout_awid ; /*RO, from RAM data_out*/
/**/ wire [4:0] dout_rid ; /*RO, from RAM data_out*/
/**/ wire [4:0] dout_bid ; /*RO, from RAM data_out*/
/**/ reg [31:0] REG_rd_pattern ; /*RW*/
/**/ reg [31:0] REG_rd_number ; /*RW*/
/**/ reg [31:0] REG_wr_pattern ; /*RW*/
/**/ reg [31:0] REG_wr_number ; /*RW*/
/**/ reg [63:0] REG_source_address ; /*RW*/
/**/ reg [63:0] REG_target_address ; /*RW*/
/**/ reg [31:0] REG_soft_reset ; /*RW*/
// //
//-----------------------------------------------//
// //
///////////////////////////////////////////////////
//---- parameters ----
// Register addresses arrangement
parameter ADDR_SNAP_CONTROL = 32'h00,
ADDR_SNAP_INT_ENABLE = 32'h04,
ADDR_SNAP_ACTION_TYPE = 32'h10,
ADDR_SNAP_ACTION_VERSION = 32'h14,
ADDR_SNAP_CONTEXT = 32'h20,
// User defined below
ADDR_USER_STATUS = 32'h30,
ADDR_USER_CONTROL = 32'h34,
ADDR_USER_MODE = 32'h38,
ADDR_INIT_RDATA = 32'h3C, //Non-zero init Read Data
ADDR_INIT_WDATA = 32'h40, //Non-zero init Write Data
//Following four Time Trace RAMs, when read the MMIO port, the RAM
//address is increased by 1 automatically
ADDR_TT_RD_CMD = 32'h44, //Time Trace RAM, when ARVALID is sent
ADDR_TT_RD_RSP = 32'h48, //Time Trace RAM, when RLAST is received
ADDR_TT_WR_CMD = 32'h4C, //Time Trace RAM, when AWVALID is sent
ADDR_TT_WR_RSP = 32'h50, //Time Trace RAM, when BVALID is received
ADDR_TT_ARID = 32'h54, //ID Trace RAM,
ADDR_TT_AWID = 32'h58, //ID Trace RAM,
ADDR_TT_RID = 32'h5C, //ID Trace RAM,
ADDR_TT_BID = 32'h60, //ID Trace RAM,
ADDR_RD_PATTERN = 32'h64, //AXI Read pattern
ADDR_RD_NUMBER = 32'h68, //how many AXI Read transactions
ADDR_WR_PATTERN = 32'h6C, //AXI Write Pattern
ADDR_WR_NUMBER = 32'h70, //how many AXI Write trasactions
ADDR_SOURCE_ADDRESS_L = 32'h74,
ADDR_SOURCE_ADDRESS_H = 32'h78,
ADDR_TARGET_ADDRESS_L = 32'h7C,
ADDR_TARGET_ADDRESS_H = 32'h80,
ADDR_ERROR_INFO_L = 32'h84,
ADDR_ERROR_INFO_H = 32'h88,
ADDR_SOFT_RESET = 32'h8C;
//---- local controlling signals assignments ----
assign rd_init_data = REG_init_rdata;
assign wr_init_data = REG_init_wdata;
assign rd_pattern = REG_rd_pattern;
assign rd_number = REG_rd_number;
assign wr_pattern = REG_wr_pattern;
assign wr_number = REG_wr_number;
assign source_address = REG_source_address;
assign target_address = REG_target_address;
assign o_snap_context = REG_snap_context;
assign soft_reset = REG_soft_reset[0];
assign wrap_mode = REG_user_mode[0];
assign wrap_len = REG_user_mode[11:8];
/***********************************************************************
* writing registers *
***********************************************************************/
//---- write address capture ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
write_address <= 32'd0;
else if(s_axi_awvalid & s_axi_awready)
write_address <= s_axi_awaddr;
//---- write address ready ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_awready <= 1'b0;
else if(s_axi_awvalid)
s_axi_awready <= 1'b1;
else if(s_axi_wvalid & s_axi_wready)
s_axi_awready <= 1'b0;
//---- write data ready ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_wready <= 1'b0;
else if(s_axi_awvalid & s_axi_awready)
s_axi_wready <= 1'b1;
else if(s_axi_wvalid)
s_axi_wready <= 1'b0;
//---- handle write data strobe ----
assign wr_mask = {{8{s_axi_wstrb[3]}},{8{s_axi_wstrb[2]}},{8{s_axi_wstrb[1]}},{8{s_axi_wstrb[0]}}};
assign regw_snap_status = {(s_axi_wdata&wr_mask)|(~wr_mask®_snap_control)};
assign regw_snap_int_enable = {(s_axi_wdata&wr_mask)|(~wr_mask®_snap_int_enable)};
assign regw_snap_context = {(s_axi_wdata&wr_mask)|(~wr_mask®_snap_context)};
assign regw_control = {(s_axi_wdata&wr_mask)|(~wr_mask®_user_control)};
assign regw_mode = {(s_axi_wdata&wr_mask)|(~wr_mask®_user_mode)};
assign regw_init_rdata = {(s_axi_wdata&wr_mask)|(~wr_mask®_init_rdata)};
assign regw_init_wdata = {(s_axi_wdata&wr_mask)|(~wr_mask®_init_wdata)};
assign regw_rd_pattern = {(s_axi_wdata&wr_mask)|(~wr_mask®_rd_pattern)};
assign regw_rd_number = {(s_axi_wdata&wr_mask)|(~wr_mask®_rd_number)};
assign regw_wr_pattern = {(s_axi_wdata&wr_mask)|(~wr_mask®_wr_pattern)};
assign regw_wr_number = {(s_axi_wdata&wr_mask)|(~wr_mask®_wr_number)};
assign regw_source_address = {(s_axi_wdata&wr_mask)|(~wr_mask®_source_address)};
assign regw_target_address = {(s_axi_wdata&wr_mask)|(~wr_mask®_target_address)};
assign regw_soft_reset = {(s_axi_wdata&wr_mask)|(~wr_mask®_soft_reset)};
//---- write registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
REG_snap_control <= 32'd0;
REG_snap_int_enable <= 32'd0;
REG_snap_context <= 32'd0;
REG_user_control <= 32'd0;
REG_user_mode <= 32'd0;
REG_init_rdata <= 32'd0;
REG_init_wdata <= 32'd0;
REG_rd_pattern <= 32'd0;
REG_rd_number <= 32'd0;
REG_wr_pattern <= 32'd0;
REG_wr_number <= 32'd0;
REG_source_address <= 64'd0;
REG_target_address <= 64'd0;
REG_soft_reset <= 32'd0;
end
else if(soft_reset)
begin
REG_snap_control <= 32'd0;
REG_snap_int_enable <= 32'd0;
REG_snap_context <= 32'd0;
REG_user_control <= 32'd0;
REG_user_mode <= 32'd0;
REG_init_rdata <= 32'd0;
REG_init_wdata <= 32'd0;
REG_rd_pattern <= 32'd0;
REG_rd_number <= 32'd0;
REG_wr_pattern <= 32'd0;
REG_wr_number <= 32'd0;
REG_source_address <= 64'd0;
REG_target_address <= 64'd0;
REG_soft_reset <= 32'd0;
end
else if(s_axi_wvalid & s_axi_wready)
case(write_address)
ADDR_SNAP_CONTROL : REG_snap_control <= regw_snap_status;
ADDR_SNAP_INT_ENABLE : REG_snap_int_enable <= regw_snap_int_enable;
ADDR_SNAP_CONTEXT : REG_snap_context <= regw_snap_context;
ADDR_USER_CONTROL : REG_user_control <= regw_control;
ADDR_USER_MODE : REG_user_mode <= regw_mode;
ADDR_INIT_RDATA : REG_init_rdata <= regw_init_rdata;
ADDR_INIT_WDATA : REG_init_wdata <= regw_init_wdata;
ADDR_RD_PATTERN : REG_rd_pattern <= regw_rd_pattern;
ADDR_RD_NUMBER : REG_rd_number <= regw_rd_number;
ADDR_WR_PATTERN : REG_wr_pattern <= regw_wr_pattern;
ADDR_WR_NUMBER : REG_wr_number <= regw_wr_number;
ADDR_SOURCE_ADDRESS_H : REG_source_address <= {regw_source_address,REG_source_address[31:00]};
ADDR_SOURCE_ADDRESS_L : REG_source_address <= {REG_source_address[63:32],regw_source_address};
ADDR_TARGET_ADDRESS_H : REG_target_address <= {regw_target_address,REG_target_address[31:00]};
ADDR_TARGET_ADDRESS_L : REG_target_address <= {REG_target_address[63:32],regw_target_address};
ADDR_SOFT_RESET : REG_soft_reset <= regw_soft_reset;
default :;
endcase
/***********************************************************************
* Control Flow *
***********************************************************************/
// The build-in snap_action_start() and snap_action_completed functions
// sets REG_snap_control bit "start" and reads bit "idle"
// The other things are managed by REG_user_control (user defined control register)
// Flow:
// ---------------------------------------------------------------------------------------------
// Software Hardware REG Hardware signal & action
// ---------------------------------------------------------------------------------------------
// snap_action_start() | |
// | SNAP_CONTROL[snap_start]=1 |
// mmio_write(USER_CONTROL[address...]) | | snap_start_pulse
// mmio_write(USER_CONTROL[pattern...]) | | Spend 4096 cycles to clear tt_RAM
// mmio_write(USER_CONTROL[number...]) | |
// wait(USER_CONTROL[engine_ready])==1 | |
// | USER_STATUS[engine_ready]=1 |
// mmio_write(USER_CONTROL[engine_start])=1 | |
// | CONTROL[engine_start]=1 |
// | | engine_start_pulse
// | | Run Read requests and Write requests
// | | .
// | | .
// | | .
// | | rd_done or wr_done or rd_error
// | USER_STATUS[rd_done/wr_done/rd_error]= 1 |
// wait(USER_STATUS) | |
// Send 4096 MMIO reads for TT ... | |
// mmio_write(USER_CONTROL[finish_dump])=1 | |
// | USER_CONTROL[finish_dump]=1 |
// | SNAP_CONTROL[snap_idle]=1 |
// snap_action_completed() | |
//
wire snap_start_pulse;
reg snap_start_q;
reg snap_idle_q;
reg engine_start_q;
reg engine_ready_q;
reg [11:0] tt_counter_q;
reg [01:0] rd_error_q;
reg wr_error_q;
reg rd_done_q;
reg wr_done_q;
wire both_done;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
snap_start_q <= 0;
engine_start_q <= 0;
end
else if(soft_reset) begin
snap_start_q <= 0;
engine_start_q <= 0;
end
else begin
snap_start_q <= REG_snap_control[0];
engine_start_q <= REG_user_control[0];
end
end
assign snap_start_pulse = REG_snap_control[0] & ~snap_start_q;
assign engine_start_pulse = REG_user_control[0] & ~engine_start_q;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
snap_idle_q <= 0;
end
else if(soft_reset) begin
snap_idle_q <= 0;
end
else if (REG_user_control[1]) begin //finish_dump
snap_idle_q <= 1;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
tt_counter_q <= 12'hFFF;
engine_ready_q <= 0;
end
else if(soft_reset) begin
tt_counter_q <= 12'hFFF;
engine_ready_q <= 0;
end
else if (REG_snap_control[0]) begin
if (tt_counter_q != 0)
tt_counter_q <= tt_counter_q - 1;
else
engine_ready_q <= 1;
end
end
always@(posedge clk or negedge rst_n)
if (~rst_n) begin
REG_error_info <= 64'd0;
end
else if(rd_error[1] && (!rd_error_q[1])) begin
REG_error_info <= rd_error_info;
end
always@(posedge clk or negedge rst_n)
if (~rst_n) begin
rd_error_q <= 0;
end
else if(soft_reset) begin
rd_error_q <= 0;
end
else if(|rd_error) begin
rd_error_q <= rd_error;
end
always@(posedge clk or negedge rst_n)
if (~rst_n) begin
wr_error_q <= 0;
end
else if(soft_reset) begin
wr_error_q <= 0;
end
else if(wr_error) begin
wr_error_q <= 1;
end
always@(posedge clk or negedge rst_n)
if (~rst_n)
rd_done_q <= 0;
else if(soft_reset)
rd_done_q <= 0;
else if (rd_done_pulse || (engine_start_pulse && (rd_number == 0)))
rd_done_q <= 1;
always@(posedge clk or negedge rst_n)
if (~rst_n)
wr_done_q <= 0;
else if(soft_reset)
wr_done_q <= 0;
else if (wr_done_pulse || (engine_start_pulse && (wr_number == 0)))
wr_done_q <= 1;
assign both_done = rd_done_q & wr_done_q;
assign REG_user_status = {current_cycle_H, 10'd0, engine_ready_q, rd_error_q, wr_error_q, rd_done_q, wr_done_q};
assign REG_snap_control_rd = {REG_snap_control[31:4], 1'b1, snap_idle_q, 1'b0, snap_start_q};
//Address: 0x000
// 31..8 RO: Reserved
// 7 RW: auto restart
// 6..4 RO: Reserved
// 3 RO: Ready (not used)
// 2 RO: Idle (in use)
// 1 RC: Done (not used)
// 0 RW: Start (in use)
/***********************************************************************
* reading registers *
***********************************************************************/
//---- read registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_rdata <= 32'd0;
else if(s_axi_arvalid & s_axi_arready)
case(s_axi_araddr)
ADDR_SNAP_CONTROL : s_axi_rdata <= REG_snap_control_rd;
ADDR_SNAP_INT_ENABLE : s_axi_rdata <= REG_snap_int_enable[31 : 0];
ADDR_SNAP_ACTION_TYPE : s_axi_rdata <= i_action_type;
ADDR_SNAP_ACTION_VERSION : s_axi_rdata <= i_action_version;
ADDR_SNAP_CONTEXT : s_axi_rdata <= REG_snap_context[31 : 0];
ADDR_USER_STATUS : s_axi_rdata <= REG_user_status;
ADDR_USER_CONTROL : s_axi_rdata <= REG_user_control;
ADDR_USER_MODE : s_axi_rdata <= REG_user_mode;
ADDR_INIT_RDATA : s_axi_rdata <= REG_init_rdata;
ADDR_INIT_WDATA : s_axi_rdata <= REG_init_wdata;
ADDR_TT_RD_CMD : s_axi_rdata <= cyc_tt_rd_cmd;
ADDR_TT_RD_RSP : s_axi_rdata <= cyc_tt_rd_rsp;
ADDR_TT_WR_CMD : s_axi_rdata <= cyc_tt_wr_cmd;
ADDR_TT_WR_RSP : s_axi_rdata <= cyc_tt_wr_rsp;
ADDR_TT_ARID : s_axi_rdata <= {27'd0, dout_arid};
ADDR_TT_AWID : s_axi_rdata <= {27'd0, dout_awid};
ADDR_TT_RID : s_axi_rdata <= {27'd0, dout_rid};
ADDR_TT_BID : s_axi_rdata <= {27'd0, dout_bid};
ADDR_RD_PATTERN : s_axi_rdata <= REG_rd_pattern;
ADDR_RD_NUMBER : s_axi_rdata <= REG_rd_number;
ADDR_WR_PATTERN : s_axi_rdata <= REG_wr_pattern;
ADDR_WR_NUMBER : s_axi_rdata <= REG_wr_number;
ADDR_SOURCE_ADDRESS_L : s_axi_rdata <= REG_source_address[31 : 0];
ADDR_SOURCE_ADDRESS_H : s_axi_rdata <= REG_source_address[63 : 32];
ADDR_TARGET_ADDRESS_L : s_axi_rdata <= REG_target_address[31 : 0];
ADDR_TARGET_ADDRESS_H : s_axi_rdata <= REG_target_address[63 : 32];
ADDR_ERROR_INFO_L : s_axi_rdata <= REG_error_info[31 : 0];
ADDR_ERROR_INFO_H : s_axi_rdata <= REG_error_info[63 : 32];
ADDR_SOFT_RESET : s_axi_rdata <= REG_soft_reset;
default : s_axi_rdata <= 32'h5a5aa5a5;
endcase
//---- address ready: deasserts once arvalid is seen; reasserts when current read is done ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_arready <= 1'b1;
else if(s_axi_arvalid)
s_axi_arready <= 1'b0;
else if(s_axi_rvalid & s_axi_rready)
s_axi_arready <= 1'b1;
//---- data ready: deasserts once rvalid is seen; reasserts when new address has come ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_rvalid <= 1'b0;
else if (s_axi_arvalid & s_axi_arready)
s_axi_rvalid <= 1'b1;
else if (s_axi_rready)
s_axi_rvalid <= 1'b0;
/***********************************************************************
* status reporting *
***********************************************************************/
//---- axi write response ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_bvalid <= 1'b0;
else if(s_axi_wvalid & s_axi_wready)
s_axi_bvalid <= 1'b1;
else if(s_axi_bready)
s_axi_bvalid <= 1'b0;
assign s_axi_bresp = 2'd0;
//---- axi read response ----
assign s_axi_rresp = 2'd0;
/***********************************************************************
* Four time trace RAMs *
***********************************************************************/
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
current_cycle_L <= 32'd0;
current_cycle_H <= 16'd0;
end
else if(soft_reset) begin
current_cycle_L <= 32'd0;
current_cycle_H <= 16'd0;
end
else if (REG_user_control[0] & ~both_done) begin //Only count after engine_start and before both_done
if (current_cycle_L == 32'hFFFFFFFF) begin
current_cycle_H <= current_cycle_H + 1;
current_cycle_L <= 32'd0;
end
else
current_cycle_L <= current_cycle_L + 1;
end
//Generate RAM address
//wr_done_pulse and rd_done_pulse are 1-cycle pulses. They are Used to reset the RAM address.
reg [11:0] tt_addr_rd_cmd;
reg [11:0] tt_addr_rd_rsp;
reg [11:0] tt_addr_wr_cmd;
reg [11:0] tt_addr_wr_rsp;
wire clear_RAM;
//We spend 4096 cycles to clear the RAMs. At this moment data_in
//(current_cycle_L) is zero.
assign clear_RAM = REG_snap_control[0] & ~engine_ready_q;
always@(posedge clk or negedge rst_n)
if(~rst_n)
tt_addr_rd_cmd <= 0;
else if(soft_reset)
tt_addr_rd_cmd <= 0;
else if(rd_done_pulse || (|rd_error))
tt_addr_rd_cmd <= 0;
else if (tt_arvalid || //Transactions write RAM, repeatedly flush the old data
clear_RAM || //Clear RAM in the beginning
((s_axi_arvalid & s_axi_arready) && (s_axi_araddr == ADDR_TT_RD_CMD))) //MMIO read tt RAM
tt_addr_rd_cmd <= tt_addr_rd_cmd + 1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
tt_addr_rd_rsp <= 0;
else if(soft_reset)
tt_addr_rd_rsp <= 0;
else if(rd_done_pulse || (|rd_error) )
tt_addr_rd_rsp <= 0;
else if (tt_rlast || //Transactions write RAM, repeatedly flush the old data
clear_RAM || //Clear RAM in the beginning
((s_axi_arvalid & s_axi_arready) && (s_axi_araddr == ADDR_TT_RD_RSP))) //MMIO read tt RAM
tt_addr_rd_rsp <= tt_addr_rd_rsp + 1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
tt_addr_wr_cmd <= 0;
else if(soft_reset)
tt_addr_wr_cmd <= 0;
else if(wr_done_pulse || wr_error)
tt_addr_wr_cmd <= 0;
else if (tt_awvalid || //Transactions write RAM, repeatedly flush the old data
clear_RAM || //Clear RAM in the beginning
((s_axi_arvalid & s_axi_arready) && (s_axi_araddr == ADDR_TT_WR_CMD))) //MMIO read tt RAM
tt_addr_wr_cmd <= tt_addr_wr_cmd + 1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
tt_addr_wr_rsp <= 0;
else if(soft_reset)
tt_addr_wr_rsp <= 0;
else if(wr_done_pulse || wr_error)
tt_addr_wr_rsp <= 0;
else if (tt_bvalid || //Transactions write RAM, repeatedly flush the old data
clear_RAM || //Clear RAM in the beginning
((s_axi_arvalid & s_axi_arready) && (s_axi_araddr == ADDR_TT_WR_RSP))) //MMIO read tt RAM
tt_addr_wr_rsp <= tt_addr_wr_rsp + 1;
ram_single_port #(.DATA_WIDTH(37), .ADDR_WIDTH(12)) RAM_tt_rd_cmd(
.clk ( clk ) ,
.we ( tt_arvalid || clear_RAM ) ,
.addr ( tt_addr_rd_cmd ) ,
.data_in ( {tt_arid,current_cycle_L} ) ,
.data_out ( {dout_arid, cyc_tt_rd_cmd} )
);
ram_single_port #(.DATA_WIDTH(37), .ADDR_WIDTH(12)) RAM_tt_rd_rsp(
.clk ( clk ) ,
.we ( tt_rlast || clear_RAM ) ,
.addr ( tt_addr_rd_rsp ) ,
.data_in ( {tt_rid,current_cycle_L} ) ,
.data_out ( {dout_rid, cyc_tt_rd_rsp} )
);
ram_single_port #(.DATA_WIDTH(37), .ADDR_WIDTH(12)) RAM_tt_wr_cmd(
.clk ( clk ) ,
.we ( tt_awvalid || clear_RAM ) ,
.addr ( tt_addr_wr_cmd ) ,
.data_in ( {tt_awid, current_cycle_L} ) ,
.data_out ( {dout_awid, cyc_tt_wr_cmd } )
);
ram_single_port #(.DATA_WIDTH(37), .ADDR_WIDTH(12)) RAM_tt_wr_rsp(
.clk ( clk ) ,
.we ( tt_bvalid || clear_RAM ) ,
.addr ( tt_addr_wr_rsp ) ,
.data_in ( {tt_bid, current_cycle_L} ) ,
.data_out ( {dout_bid, cyc_tt_wr_rsp} )
);
endmodule |
module action_wrapper #(
// Parameters of Axi Master Bus Interface AXI_CARD_MEM0 ; to DDR memory
parameter C_M_AXI_CARD_MEM0_ID_WIDTH = 5,
parameter C_M_AXI_CARD_MEM0_ADDR_WIDTH = 33,
parameter C_M_AXI_CARD_MEM0_DATA_WIDTH = 512,
parameter C_M_AXI_CARD_MEM0_AWUSER_WIDTH = 9,
parameter C_M_AXI_CARD_MEM0_ARUSER_WIDTH = 9,
parameter C_M_AXI_CARD_MEM0_WUSER_WIDTH = 9,
parameter C_M_AXI_CARD_MEM0_RUSER_WIDTH = 9,
parameter C_M_AXI_CARD_MEM0_BUSER_WIDTH = 9,
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
parameter C_S_AXI_CTRL_REG_DATA_WIDTH = 32,
parameter C_S_AXI_CTRL_REG_ADDR_WIDTH = 32,
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
parameter C_M_AXI_HOST_MEM_ID_WIDTH = `IDW,
parameter C_M_AXI_HOST_MEM_ADDR_WIDTH = 64,
parameter C_M_AXI_HOST_MEM_DATA_WIDTH = `AXI_MM_DW,
parameter C_M_AXI_HOST_MEM_AWUSER_WIDTH = `CTXW,
parameter C_M_AXI_HOST_MEM_ARUSER_WIDTH = `CTXW,
parameter C_M_AXI_HOST_MEM_WUSER_WIDTH = `CTXW,
parameter C_M_AXI_HOST_MEM_RUSER_WIDTH = `CTXW,
parameter C_M_AXI_HOST_MEM_BUSER_WIDTH = `CTXW,
// Parameters of Interrupt Interface
parameter SOURCE_BITS = 64,
parameter CONTEXT_BITS = `CTXW
)
(
input ap_clk ,
input ap_rst_n ,
output interrupt ,
output [SOURCE_BITS-1 : 0] interrupt_src ,
output [CONTEXT_BITS-1 : 0] interrupt_ctx ,
input interrupt_ack ,
// AXI Control Register Interface
input [C_S_AXI_CTRL_REG_ADDR_WIDTH-1 : 0 ] s_axi_ctrl_reg_araddr ,
output s_axi_ctrl_reg_arready ,
input s_axi_ctrl_reg_arvalid ,
input [C_S_AXI_CTRL_REG_ADDR_WIDTH-1 : 0 ] s_axi_ctrl_reg_awaddr ,
output s_axi_ctrl_reg_awready ,
input s_axi_ctrl_reg_awvalid ,
input s_axi_ctrl_reg_bready ,
output [1 : 0 ] s_axi_ctrl_reg_bresp ,
output s_axi_ctrl_reg_bvalid ,
output [C_S_AXI_CTRL_REG_DATA_WIDTH-1 : 0 ] s_axi_ctrl_reg_rdata ,
input s_axi_ctrl_reg_rready ,
output [1 : 0 ] s_axi_ctrl_reg_rresp ,
output s_axi_ctrl_reg_rvalid ,
input [C_S_AXI_CTRL_REG_DATA_WIDTH-1 : 0 ] s_axi_ctrl_reg_wdata ,
output s_axi_ctrl_reg_wready ,
input [(C_S_AXI_CTRL_REG_DATA_WIDTH/8)-1 : 0 ] s_axi_ctrl_reg_wstrb ,
input s_axi_ctrl_reg_wvalid ,
//
// AXI Host Memory Interface
output [C_M_AXI_HOST_MEM_ADDR_WIDTH-1 : 0 ] m_axi_host_mem_araddr ,
output [1 : 0 ] m_axi_host_mem_arburst ,
output [3 : 0 ] m_axi_host_mem_arcache ,
output [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0 ] m_axi_host_mem_arid ,
output [7 : 0 ] m_axi_host_mem_arlen ,
output [1 : 0 ] m_axi_host_mem_arlock ,
output [2 : 0 ] m_axi_host_mem_arprot ,
output [3 : 0 ] m_axi_host_mem_arqos ,
input m_axi_host_mem_arready ,
output [3 : 0 ] m_axi_host_mem_arregion ,
output [2 : 0 ] m_axi_host_mem_arsize ,
output [C_M_AXI_HOST_MEM_ARUSER_WIDTH-1 : 0 ] m_axi_host_mem_aruser ,
output m_axi_host_mem_arvalid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH-1 : 0 ] m_axi_host_mem_awaddr ,
output [1 : 0 ] m_axi_host_mem_awburst ,
output [3 : 0 ] m_axi_host_mem_awcache ,
output [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0 ] m_axi_host_mem_awid ,
output [7 : 0 ] m_axi_host_mem_awlen ,
output [1 : 0 ] m_axi_host_mem_awlock ,
output [2 : 0 ] m_axi_host_mem_awprot ,
output [3 : 0 ] m_axi_host_mem_awqos ,
input m_axi_host_mem_awready ,
output [3 : 0 ] m_axi_host_mem_awregion ,
output [2 : 0 ] m_axi_host_mem_awsize ,
output [C_M_AXI_HOST_MEM_AWUSER_WIDTH-1 : 0 ] m_axi_host_mem_awuser ,
output m_axi_host_mem_awvalid ,
input [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0 ] m_axi_host_mem_bid ,
output m_axi_host_mem_bready ,
input [1 : 0 ] m_axi_host_mem_bresp ,
input [C_M_AXI_HOST_MEM_BUSER_WIDTH-1 : 0 ] m_axi_host_mem_buser ,
input m_axi_host_mem_bvalid ,
input [C_M_AXI_HOST_MEM_DATA_WIDTH-1 : 0 ] m_axi_host_mem_rdata ,
input [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0 ] m_axi_host_mem_rid ,
input m_axi_host_mem_rlast ,
output m_axi_host_mem_rready ,
input [1 : 0 ] m_axi_host_mem_rresp ,
input [C_M_AXI_HOST_MEM_RUSER_WIDTH-1 : 0 ] m_axi_host_mem_ruser ,
input m_axi_host_mem_rvalid ,
output [C_M_AXI_HOST_MEM_DATA_WIDTH-1 : 0 ] m_axi_host_mem_wdata ,
output m_axi_host_mem_wlast ,
input m_axi_host_mem_wready ,
output [(C_M_AXI_HOST_MEM_DATA_WIDTH/8)-1 : 0 ] m_axi_host_mem_wstrb ,
output [C_M_AXI_HOST_MEM_WUSER_WIDTH-1 : 0 ] m_axi_host_mem_wuser ,
output m_axi_host_mem_wvalid
);
endmodule |
module action_wrapper #(
// Parameters of Axi MM Bus Interface
parameter AXI_ID_WIDTH = 5,
parameter AXI_ADDR_WIDTH = 64,
parameter AXI_DATA_WIDTH = `AXI_MM_DW,
parameter AXI_AWUSER_WIDTH = `CTXW,
parameter AXI_ARUSER_WIDTH = `CTXW,
parameter AXI_WUSER_WIDTH = `CTXW,
parameter AXI_RUSER_WIDTH = `CTXW,
parameter AXI_BUSER_WIDTH = `CTXW,
parameter AXIL_ADDR_WIDTH = 32,
parameter AXIL_DATA_WIDTH = 32,
// Parameters of Axi Stream Bus Interface
parameter AXIS_ID_WIDTH = `IDW,
parameter AXIS_DATA_WIDTH = `AXI_ST_DW,
parameter AXIS_USER_WIDTH = `CTXW,
// Parameters of Interrupt Interface
parameter SOURCE_BITS = 64,
parameter CONTEXT_BITS = `CTXW)
(
input ap_clk ,
input ap_rst_n ,
output interrupt ,
output [SOURCE_BITS-1 : 0] interrupt_src ,
output [CONTEXT_BITS-1 : 0] interrupt_ctx ,
input interrupt_ack ,
`ifndef ENABLE_ODMA_ST_MODE
//----- AXI4 read addr interface -----
input [AXI_ADDR_WIDTH-1 : 0] axi_mm_araddr,
input [1 : 0] axi_mm_arburst,
input [3 : 0] axi_mm_arcache,
input [AXI_ID_WIDTH-1 : 0] axi_mm_arid,
input [7 : 0] axi_mm_arlen,
input [1 : 0] axi_mm_arlock,
input [2 : 0] axi_mm_arprot,
input [3 : 0] axi_mm_arqos,
output axi_mm_arready,
input [3 : 0] axi_mm_arregion,
input [2 : 0] axi_mm_arsize,
input [AXI_ARUSER_WIDTH-1 : 0] axi_mm_aruser,
input axi_mm_arvalid,
//----- AXI4 read data interface -----
output [AXI_DATA_WIDTH-1 : 0 ] axi_mm_rdata,
output [AXI_ID_WIDTH-1 : 0 ] axi_mm_rid,
output axi_mm_rlast,
input axi_mm_rready,
output [1 : 0 ] axi_mm_rresp,
output [AXI_RUSER_WIDTH-1 : 0 ] axi_mm_ruser,
output axi_mm_rvalid,
//----- AXI4 write addr interface -----
input [AXI_ADDR_WIDTH-1 : 0] axi_mm_awaddr,
input [1 : 0] axi_mm_awburst,
input [3 : 0] axi_mm_awcache,
input [AXI_ID_WIDTH-1 : 0] axi_mm_awid,
input [7 : 0] axi_mm_awlen,
input [1 : 0] axi_mm_awlock,
input [2 : 0] axi_mm_awprot,
input [3 : 0] axi_mm_awqos,
output axi_mm_awready,
input [3 : 0] axi_mm_awregion,
input [2 : 0] axi_mm_awsize,
input [AXI_AWUSER_WIDTH-1 : 0] axi_mm_awuser,
input axi_mm_awvalid,
//----- AXI4 write data interface -----
input [AXI_DATA_WIDTH-1 : 0 ] axi_mm_wdata,
input [(AXI_DATA_WIDTH/8)-1 : 0 ] axi_mm_wstrb,
input axi_mm_wlast,
input [AXI_WUSER_WIDTH-1 : 0 ] axi_mm_wuser,
input axi_mm_wvalid,
output axi_mm_wready,
//----- AXI4 write resp interface -----
output axi_mm_bvalid,
output [1 : 0] axi_mm_bresp,
output [AXI_BUSER_WIDTH-1 : 0 ] axi_mm_buser,
output [AXI_ID_WIDTH-1 : 0 ] axi_mm_bid,
input axi_mm_bready,
`else
output m_axis_tready,
input m_axis_tlast,
input [`AXI_ST_DW - 1:0] m_axis_tdata,
input [`AXI_ST_DW/8 - 1:0] m_axis_tkeep,
input m_axis_tvalid,
input [`IDW - 1:0] m_axis_tid,
input [`AXI_ST_USER - 1:0] m_axis_tuser,
input s_axis_tready,
output s_axis_tlast,
output [`AXI_ST_DW - 1:0] s_axis_tdata,
output [`AXI_ST_DW/8 - 1:0] s_axis_tkeep ,
output s_axis_tvalid,
output [`IDW - 1:0] s_axis_tid,
output [`AXI_ST_USER - 1:0] s_axis_tuser,
`endif
//----- AXI lite slave interface -----
input a_s_axi_arvalid,
input [AXIL_ADDR_WIDTH-1 : 0] a_s_axi_araddr,
output a_s_axi_arready,
output a_s_axi_rvalid,
output [AXIL_DATA_WIDTH-1 : 0 ] a_s_axi_rdata,
output [1 : 0 ] a_s_axi_rresp,
input a_s_axi_rready,
input a_s_axi_awvalid,
input [AXIL_ADDR_WIDTH-1 : 0] a_s_axi_awaddr,
output a_s_axi_awready,
input a_s_axi_wvalid,
input [AXIL_DATA_WIDTH-1 : 0 ] a_s_axi_wdata,
input [(AXIL_DATA_WIDTH/8)-1 : 0 ] a_s_axi_wstrb,
output a_s_axi_wready,
output a_s_axi_bvalid,
output [1 : 0 ] a_s_axi_bresp,
input a_s_axi_bready,
//----- AXI lite master interface -----
output a_m_axi_arvalid,
output [AXIL_ADDR_WIDTH-1 : 0] a_m_axi_araddr,
input a_m_axi_arready,
input a_m_axi_rvalid,
input [AXIL_DATA_WIDTH-1 : 0 ] a_m_axi_rdata,
input [1 : 0 ] a_m_axi_rresp,
output a_m_axi_rready,
output a_m_axi_awvalid,
output [AXIL_ADDR_WIDTH-1 : 0] a_m_axi_awaddr,
input a_m_axi_awready,
output a_m_axi_wvalid,
output [AXIL_DATA_WIDTH-1 : 0 ] a_m_axi_wdata,
output [(AXIL_DATA_WIDTH/8)-1 : 0 ] a_m_axi_wstrb,
input a_m_axi_wready,
input a_m_axi_bvalid,
input [1 : 0 ] a_m_axi_bresp,
output a_m_axi_bready
);
//TODO: Send interrupt
assign interrupt_src=0;
assign interrupt=0;
assign interrupt_ctx=0;
//`ifndef ENABLE_ODMA_ST_MODE
// //odma_axi_slave is ready, codes are as follows
// odma_axi_slave axi_slave(
// /*input */ .clk ( ap_clk ),
// /*input */ .rst_n ( ap_rst_n ),
// /* AXI4 read addr interface */
// /*input [AXI_ADDR_WIDTH-1 : 0] */ .axi_araddr ( axi_mm_araddr ),
// /*input [1 : 0] */ .axi_arburst ( axi_mm_arburst ),
// /*input [3 : 0] */ .axi_arcache ( axi_mm_arcache ),
// /*input [AXI_ID_WIDTH-1 : 0] */ .axi_arid ( axi_mm_arid ),
// /*input [7 : 0] */ .axi_arlen ( axi_mm_arlen ),
// /*input [1 : 0] */ .axi_arlock ( axi_mm_arlock ),
// /*input [2 : 0] */ .axi_arprot ( axi_mm_arprot ),
// /*input [3 : 0] */ .axi_arqos ( axi_mm_arqos ),
// /*output */ .axi_arready ( axi_mm_arready ),
// /*input [3 : 0] */ .axi_arregion ( axi_mm_arregion ),
// /*input [2 : 0] */ .axi_arsize ( axi_mm_arsize ),
// /*input [AXI_ARUSER_WIDTH-1 : 0] */ .axi_aruser ( axi_mm_aruser ),
// /*input */ .axi_arvalid ( axi_mm_arvalid ),
// /* AXI4 read data interface */
// /*output [AXI_DATA_WIDTH-1 : 0 ] */ .axi_rdata ( axi_mm_rdata ),
// /*output [AXI_ID_WIDTH-1 : 0 ] */ .axi_rid ( axi_mm_rid ),
// /*output */ .axi_rlast ( axi_mm_rlast ),
// /*input */ .axi_rready ( axi_mm_rready ),
// /*output [1 : 0 ] */ .axi_rresp ( axi_mm_rresp ),
// /*output [AXI_RUSER_WIDTH-1 : 0 ] */ .axi_ruser ( axi_mm_ruser ),
// /*output reg */ .axi_rvalid ( axi_mm_rvalid ),
// /* AXI4 write addr interface */
// /*input [AXI_ADDR_WIDTH-1 : 0] */ .axi_awaddr ( axi_mm_awaddr ),
// /*input [1 : 0] */ .axi_awburst ( axi_mm_awburst ),
// /*input [3 : 0] */ .axi_awcache ( axi_mm_awcache ),
// /*input [AXI_ID_WIDTH-1 : 0] */ .axi_awid ( axi_mm_awid ),
// /*input [7 : 0] */ .axi_awlen ( axi_mm_awlen ),
// /*input [1 : 0] */ .axi_awlock ( axi_mm_awlock ),
// /*input [2 : 0] */ .axi_awprot ( axi_mm_awprot ),
// /*input [3 : 0] */ .axi_awqos ( axi_mm_awqos ),
// /*output reg */ .axi_awready ( axi_mm_awready ),
// /*input [3 : 0] */ .axi_awregion ( axi_mm_awregion ),
// /*input [2 : 0] */ .axi_awsize ( axi_mm_awsize ),
// /*input [AXI_ARUSER_WIDTH-1 : 0] */ .axi_awuser ( axi_mm_awuser ),
// /*input */ .axi_awvalid ( axi_mm_awvalid ),
// /* AXI4 write data interface */
// /*input [AXI_DATA_WIDTH-1 : 0 ] */ .axi_wdata ( axi_mm_wdata ),
// /*input [(AXI_DATA_WIDTH/8)-1 : 0 ] */ .axi_wstrb ( axi_mm_wstrb ),
// /*input */ .axi_wlast ( axi_mm_wlast ),
// /*input [AXI_WUSER_WIDTH-1 : 0 ] */ .axi_wuser ( axi_mm_wuser ),
// /*input */ .axi_wvalid ( axi_mm_wvalid ),
// /*output reg */ .axi_wready ( axi_mm_wready ),
// /* AXI4 write resp interface */
// /*output reg */ .axi_bvalid ( axi_mm_bvalid ),
// /*output [1 : 0] */ .axi_bresp ( axi_mm_bresp ),
// /*output [AXI_BUSER_WIDTH-1 : 0 ] */ .axi_buser ( axi_mm_buser ),
// /*output [AXI_ID_WIDTH-1 : 0 ] */ .axi_bid ( axi_mm_bid ),
// /*input */ .axi_bready ( axi_mm_bready )
// );
//`else
// //odma_axi_st_slave is ready, codes are as follows
// odma_axi_st_slave #(
// .AXIS_ID_WIDTH ( AXIS_ID_WIDTH ),
// .AXIS_USER_WIDTH ( AXIS_USER_WIDTH ),
// .AXIS_DATA_WIDTH ( AXIS_DATA_WIDTH )
// ) st_slave(
// .clk (ap_clk),
// .rst_n (ap_rst_n),
// .axis_tvalid (m_axis_tvalid),
// .axis_tready (m_axis_tready),
// .axis_tdata (m_axis_tdata),
// .axis_tkeep (m_axis_tkeep),
// .axis_tlast (m_axis_tlast),
// .axis_tid (m_axis_tid),
// .axis_tuser (m_axis_tuser)
// );
//
// //odma_axi_st_master is ready, codes are as follows
// odma_axi_st_master #(
// .AXIS_ID_WIDTH ( AXIS_ID_WIDTH ),
// .AXIS_USER_WIDTH ( AXIS_USER_WIDTH ),
// .AXIS_DATA_WIDTH ( AXIS_DATA_WIDTH )
// ) st_master(
// .clk (ap_clk),
// .rst_n (ap_rst_n),
// .axis_tvalid (s_axis_tvalid),
// .axis_tready (s_axis_tready),
// .axis_tdata (s_axis_tdata),
// .axis_tkeep (s_axis_tkeep),
// .axis_tlast (s_axis_tlast),
// .axis_tid (s_axis_tid),
// .axis_tuser (s_axis_tuser)
// );
//`endif
//
////odma_axi_lite_slave is ready, codes are as follows
//odma_axi_lite_slave lite_slave(
// .clk (ap_clk ),
// .aresetn (ap_rst_n ),
//
// .s_lite_arvalid(a_s_axi_arvalid),
// .s_lite_araddr (a_s_axi_araddr ),
// .s_lite_arready(a_s_axi_arready),
// .s_lite_rvalid (a_s_axi_rvalid ),
// .s_lite_rdata (a_s_axi_rdata ),
// .s_lite_rresp (a_s_axi_rresp ),
// .s_lite_rready (a_s_axi_rready ),
// .s_lite_awvalid(a_s_axi_awvalid),
// .s_lite_awaddr (a_s_axi_awaddr ),
// .s_lite_awready(a_s_axi_awready),
// .s_lite_wvalid (a_s_axi_wvalid ),
// .s_lite_wdata (a_s_axi_wdata ),
// .s_lite_wstrb (a_s_axi_wstrb ),
// .s_lite_wready (a_s_axi_wready ),
// .s_lite_bvalid (a_s_axi_bvalid ),
// .s_lite_bresp (a_s_axi_bresp ),
// .s_lite_bready (a_s_axi_bready )
//);
//
//odma_axi_lite_master lite_master(
// /*output */ .m_lite_arvalid( a_m_axi_arvalid ),
// /*output [AXIL_ADDR_WIDTH-1 : 0] */ .m_lite_araddr ( a_m_axi_araddr ),
// /*input */ .m_lite_arready( a_m_axi_arready ),
// /*input */ .m_lite_rvalid ( a_m_axi_rvalid ),
// /*input [AXIL_DATA_WIDTH-1 : 0 ] */ .m_lite_rdata ( a_m_axi_rdata ),
// /*input [1 : 0 ] */ .m_lite_rresp ( a_m_axi_rresp ),
// /*output */ .m_lite_rready ( a_m_axi_rready ),
// /*output */ .m_lite_awvalid( a_m_axi_awvalid ),
// /*output [AXIL_ADDR_WIDTH-1 : 0] */ .m_lite_awaddr ( a_m_axi_awaddr ),
// /*input */ .m_lite_awready( a_m_axi_awready ),
// /*output */ .m_lite_wvalid ( a_m_axi_wvalid ),
// /*output [AXIL_DATA_WIDTH-1 : 0 ] */ .m_lite_wdata ( a_m_axi_wdata ),
// /*output [(AXIL_DATA_WIDTH/8)-1 : 0 ]*/ .m_lite_wstrb ( a_m_axi_wstrb ),
// /*input */ .m_lite_wready ( a_m_axi_wready ),
// /*input */ .m_lite_bvalid ( a_m_axi_bvalid ),
// /*input [1 : 0 ] */ .m_lite_bresp ( a_m_axi_bresp ),
// /*output */ .m_lite_bready ( a_m_axi_bready )
//);
endmodule |
module odma_dummy_action #(
parameter DDR_AXI_ID_WIDTH = 4,
parameter DDR_AXI_ADDR_WIDTH = 33,
parameter DDR_AXI_DATA_WIDTH = 512,
parameter DDR_AXI_AWUSER_WIDTH = 1,
parameter DDR_AXI_ARUSER_WIDTH = 1,
parameter DDR_AXI_WUSER_WIDTH = 1,
parameter DDR_AXI_RUSER_WIDTH = 1,
parameter DDR_AXI_BUSER_WIDTH = 1,
parameter AXI_ID_WIDTH = 5,
parameter AXI_ADDR_WIDTH = 64,
parameter AXI_DATA_WIDTH = 1024,
parameter AXI_AWUSER_WIDTH = 9,
parameter AXI_ARUSER_WIDTH = 9,
parameter AXI_WUSER_WIDTH = 1,
parameter AXI_RUSER_WIDTH = 1,
parameter AXI_BUSER_WIDTH = 1,
parameter AXIL_ADDR_WIDTH = 32,
parameter AXIL_DATA_WIDTH = 32
)
(
input clk,
input rst_n,
// AXI SDRAM Interface
output [DDR_AXI_ADDR_WIDTH-1 : 0 ] ddr_axi_araddr,
output [1 : 0 ] ddr_axi_arburst,
output [3 : 0 ] ddr_axi_arcache,
output [DDR_AXI_ID_WIDTH-1 : 0 ] ddr_axi_arid,
output [7 : 0 ] ddr_axi_arlen,
output [1 : 0 ] ddr_axi_arlock,
output [2 : 0 ] ddr_axi_arprot,
output [3 : 0 ] ddr_axi_arqos,
input ddr_axi_arready,
output [3 : 0 ] ddr_axi_arregion,
output [2 : 0 ] ddr_axi_arsize,
output [DDR_AXI_ARUSER_WIDTH-1 : 0 ] ddr_axi_aruser,
output ddr_axi_arvalid,
output [DDR_AXI_ADDR_WIDTH-1 : 0 ] ddr_axi_awaddr,
output [1 : 0 ] ddr_axi_awburst,
output [3 : 0 ] ddr_axi_awcache,
output [DDR_AXI_ID_WIDTH-1 : 0 ] ddr_axi_awid,
output [7 : 0 ] ddr_axi_awlen,
output [1 : 0 ] ddr_axi_awlock,
output [2 : 0 ] ddr_axi_awprot,
output [3 : 0 ] ddr_axi_awqos,
input ddr_axi_awready,
output [3 : 0 ] ddr_axi_awregion,
output [2 : 0 ] ddr_axi_awsize,
output [DDR_AXI_AWUSER_WIDTH-1 : 0 ] ddr_axi_awuser,
output ddr_axi_awvalid,
input [DDR_AXI_ID_WIDTH-1 : 0 ] ddr_axi_bid,
output ddr_axi_bready,
input [1 : 0 ] ddr_axi_bresp,
input [DDR_AXI_BUSER_WIDTH-1 : 0 ] ddr_axi_buser,
input ddr_axi_bvalid,
input [DDR_AXI_DATA_WIDTH-1 : 0 ] ddr_axi_rdata,
input [DDR_AXI_ID_WIDTH-1 : 0 ] ddr_axi_rid,
input ddr_axi_rlast,
output ddr_axi_rready,
input [1 : 0 ] ddr_axi_rresp,
input [DDR_AXI_RUSER_WIDTH-1 : 0 ] ddr_axi_ruser,
input ddr_axi_rvalid,
output [DDR_AXI_DATA_WIDTH-1 : 0 ] ddr_axi_wdata,
output ddr_axi_wlast,
input ddr_axi_wready,
output [(DDR_AXI_DATA_WIDTH/8)-1 : 0 ] ddr_axi_wstrb,
output [DDR_AXI_WUSER_WIDTH-1 : 0 ] ddr_axi_wuser,
output ddr_axi_wvalid,
//----- AXI4 read addr interface -----
input [AXI_ADDR_WIDTH-1 : 0] axi_araddr,
input [1 : 0] axi_arburst,
input [3 : 0] axi_arcache,
input [AXI_ID_WIDTH-1 : 0] axi_arid,
input [7 : 0] axi_arlen,
input [1 : 0] axi_arlock,
input [2 : 0] axi_arprot,
input [3 : 0] axi_arqos,
output axi_arready,
input [3 : 0] axi_arregion,
input [2 : 0] axi_arsize,
input [AXI_ARUSER_WIDTH-1 : 0] axi_aruser,
input axi_arvalid,
//----- AXI4 read data interface -----
output [AXI_DATA_WIDTH-1 : 0 ] axi_rdata,
output [AXI_ID_WIDTH-1 : 0 ] axi_rid,
output axi_rlast,
input axi_rready,
output [1 : 0 ] axi_rresp,
output [AXI_RUSER_WIDTH-1 : 0 ] axi_ruser,
output axi_rvalid,
//----- AXI4 write addr interface -----
input [AXI_ADDR_WIDTH-1 : 0] axi_awaddr,
input [1 : 0] axi_awburst,
input [3 : 0] axi_awcache,
input [AXI_ID_WIDTH-1 : 0] axi_awid,
input [7 : 0] axi_awlen,
input [1 : 0] axi_awlock,
input [2 : 0] axi_awprot,
input [3 : 0] axi_awqos,
output axi_awready,
input [3 : 0] axi_awregion,
input [2 : 0] axi_awsize,
input [AXI_ARUSER_WIDTH-1 : 0] axi_awuser,
input axi_awvalid,
//----- AXI4 write data interface -----
input [AXI_DATA_WIDTH-1 : 0 ] axi_wdata,
input [(AXI_DATA_WIDTH/8)-1 : 0 ] axi_wstrb,
input axi_wlast,
input [AXI_WUSER_WIDTH-1 : 0 ] axi_wuser,
input axi_wvalid,
output axi_wready,
//----- AXI4 write resp interface -----
output axi_bvalid,
output [1 : 0] axi_bresp,
output [AXI_BUSER_WIDTH-1 : 0 ] axi_buser,
output [AXI_ID_WIDTH-1 : 0 ] axi_bid,
input axi_bready,
//----- AXI lite slave interface -----
input s_lite_arvalid,
input [AXIL_ADDR_WIDTH-1 : 0] s_lite_araddr,
output reg s_lite_arready,
output reg s_lite_rvalid,
output [AXIL_DATA_WIDTH-1 : 0 ] s_lite_rdata,
output [1 : 0 ] s_lite_rresp,
input s_lite_rready,
input s_lite_awvalid,
input [AXIL_ADDR_WIDTH-1 : 0] s_lite_awaddr,
output reg s_lite_awready,
input s_lite_wvalid,
input [AXIL_DATA_WIDTH-1 : 0 ] s_lite_wdata,
input [(AXIL_DATA_WIDTH/8)-1 : 0 ] s_lite_wstrb,
output reg s_lite_wready,
output reg s_lite_bvalid,
output [1 : 0 ] s_lite_bresp,
input s_lite_bready,
//----- AXI lite master interface -----
output m_lite_arvalid,
output [AXIL_ADDR_WIDTH-1 : 0] m_lite_araddr,
input m_lite_arready,
input m_lite_rvalid,
input [AXIL_DATA_WIDTH-1 : 0 ] m_lite_rdata,
input [1 : 0 ] m_lite_rresp,
output m_lite_rready,
output m_lite_awvalid,
output [AXIL_ADDR_WIDTH-1 : 0] m_lite_awaddr,
input m_lite_awready,
output m_lite_wvalid,
output [AXIL_DATA_WIDTH-1 : 0 ] m_lite_wdata,
output [(AXIL_DATA_WIDTH/8)-1 : 0 ] m_lite_wstrb,
input m_lite_wready,
input m_lite_bvalid,
input [1 : 0 ] m_lite_bresp,
output m_lite_bready
);
//------------------------------------------------------------------------------
parameter AXIL_STRB_WIDTH = AXIL_DATA_WIDTH/8;
//------------------------------------------------------------------------------
// AXI data width converter(1024b <-> 512b)
// Xilinx IP
axi_data_width_converter axi_converter (
.s_axi_aclk (clk),
.s_axi_aresetn (rst_n),
.s_axi_awid (axi_awid ),
.s_axi_awaddr (axi_awaddr[DDR_AXI_ADDR_WIDTH-1 : 0]),
.s_axi_awlen (axi_awlen ),
.s_axi_awsize (axi_awsize ),
.s_axi_awburst (axi_awburst ),
.s_axi_awlock (axi_awlock ),
.s_axi_awcache (axi_awcache ),
.s_axi_awprot (axi_awprot ),
.s_axi_awregion (axi_awregion),
.s_axi_awqos (axi_awqos ),
.s_axi_awvalid (axi_awvalid ),
.s_axi_awready (axi_awready ),
.s_axi_wdata (axi_wdata ),
.s_axi_wstrb (axi_wstrb ),
.s_axi_wlast (axi_wlast ),
.s_axi_wvalid (axi_wvalid ),
.s_axi_wready (axi_wready ),
.s_axi_bid (axi_bid ),
.s_axi_bresp (axi_bresp ),
.s_axi_bvalid (axi_bvalid ),
.s_axi_bready (axi_bready ),
.s_axi_arid (axi_arid ),
.s_axi_araddr (axi_araddr ),
.s_axi_arlen (axi_arlen ),
.s_axi_arsize (axi_arsize ),
.s_axi_arburst (axi_arburst ),
.s_axi_arlock (axi_arlock ),
.s_axi_arcache (axi_arcache ),
.s_axi_arprot (axi_arprot ),
.s_axi_arregion (axi_arregion),
.s_axi_arqos (axi_arqos ),
.s_axi_arvalid (axi_arvalid ),
.s_axi_arready (axi_arready ),
.s_axi_rid (axi_rid ),
.s_axi_rdata (axi_rdata ),
.s_axi_rresp (axi_rresp ),
.s_axi_rlast (axi_rlast ),
.s_axi_rvalid (axi_rvalid ),
.s_axi_rready (axi_rready ),
.m_axi_awaddr (ddr_axi_awaddr ),
.m_axi_awlen (ddr_axi_awlen ),
.m_axi_awsize (ddr_axi_awsize ),
.m_axi_awburst (ddr_axi_awburst ),
.m_axi_awlock (ddr_axi_awlock ),
.m_axi_awcache (ddr_axi_awcache ),
.m_axi_awprot (ddr_axi_awprot ),
.m_axi_awregion (ddr_axi_awregion),
.m_axi_awqos (ddr_axi_awqos ),
.m_axi_awvalid (ddr_axi_awvalid ),
.m_axi_awready (ddr_axi_awready ),
.m_axi_wdata (ddr_axi_wdata ),
.m_axi_wstrb (ddr_axi_wstrb ),
.m_axi_wlast (ddr_axi_wlast ),
.m_axi_wvalid (ddr_axi_wvalid ),
.m_axi_wready (ddr_axi_wready ),
.m_axi_bresp (ddr_axi_bresp ),
.m_axi_bvalid (ddr_axi_bvalid ),
.m_axi_bready (ddr_axi_bready ),
.m_axi_araddr (ddr_axi_araddr ),
.m_axi_arlen (ddr_axi_arlen ),
.m_axi_arsize (ddr_axi_arsize ),
.m_axi_arburst (ddr_axi_arburst ),
.m_axi_arlock (ddr_axi_arlock ),
.m_axi_arcache (ddr_axi_arcache ),
.m_axi_arprot (ddr_axi_arprot ),
.m_axi_arregion (ddr_axi_arregion),
.m_axi_arqos (ddr_axi_arqos ),
.m_axi_arvalid (ddr_axi_arvalid ),
.m_axi_arready (ddr_axi_arready ),
.m_axi_rdata (ddr_axi_rdata ),
.m_axi_rresp (ddr_axi_rresp ),
.m_axi_rlast (ddr_axi_rlast ),
.m_axi_rvalid (ddr_axi_rvalid ),
.m_axi_rready (ddr_axi_rready )
);
assign ddr_axi_arid = {DDR_AXI_ID_WIDTH{1'b0}};
assign ddr_axi_awid = {DDR_AXI_ID_WIDTH{1'b0}};
assign ddr_axi_aruser = {DDR_AXI_ARUSER_WIDTH{1'b0}};
assign ddr_axi_awuser = {DDR_AXI_AWUSER_WIDTH{1'b0}};
assign ddr_axi_wuser = {DDR_AXI_WUSER_WIDTH{1'b0}};
assign axi_ruser = {AXI_RUSER_WIDTH{1'b0}};
assign axi_buser = {AXI_BUSER_WIDTH{1'b0}};
// AXI lite slave
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
s_lite_arready <= 1'b1;
else if(s_lite_arvalid)
s_lite_arready <= 1'b0;
else if(s_lite_rvalid & s_lite_rready)
s_lite_arready <= 1'b1;
else
s_lite_arready <= s_lite_arready;
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
s_lite_rvalid <= 1'b0;
else if(s_lite_arvalid & s_lite_arready)
s_lite_rvalid <= 1'b1;
else if(s_lite_rready)
s_lite_rvalid <= 1'b0;
else
s_lite_rvalid <= s_lite_rvalid;
end
assign s_lite_rdata = {AXIL_DATA_WIDTH{1'b0}};
assign s_lite_rresp = 2'b0;
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
s_lite_awready <= 1'b0;
else if(s_lite_awvalid)
s_lite_awready <= 1'b1;
else if(s_lite_wvalid & s_lite_wready)
s_lite_awready <= 1'b0;
else
s_lite_awready <= s_lite_awready;
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
s_lite_wready <= 1'b0;
else if(s_lite_awvalid & s_lite_awready)
s_lite_wready <= 1'b1;
else if(s_lite_wvalid)
s_lite_wready <= 1'b0;
else
s_lite_wready <= s_lite_wready;
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
s_lite_bvalid <= 1'b0;
else if(s_lite_wvalid & s_lite_wready)
s_lite_bvalid <= 1'b1;
else if(s_lite_bready)
s_lite_bvalid <= 1'b0;
else
s_lite_bvalid <= s_lite_bvalid;
end
assign s_lite_bresp = 2'b0;
// AXI lite master
assign m_lite_arvalid = 1'b0;
assign m_lite_araddr = {AXIL_ADDR_WIDTH{1'b0}};
assign m_lite_rready = 1'b0;
assign m_lite_awvalid = 1'b0;
assign m_lite_awaddr = {AXIL_ADDR_WIDTH{1'b0}};
assign m_lite_wvalid = 1'b0;
assign m_lite_wdata = {AXIL_DATA_WIDTH{1'b0}};
assign m_lite_wstrb = {AXIL_STRB_WIDTH{1'b0}};
assign m_lite_bready = 1'b0;
endmodule |
module top(
input CLK,
output LEDR_N,
output LEDG_N,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
);
// Create reset signal 16 clocks long
reg reset = 1'b1;
reg [3:0] reset_cnt = 0;
always @(posedge CLK)
begin
reset <= (reset_cnt != 15);
reset_cnt <= reset_cnt + (reset_cnt != 15);
end
// Map 7 LEDs that exists on icebreaker board
wire [31:0] leds;
assign { LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5 } = {~leds[6:5], leds[4:0]};
nervsoc soc (
.clock(CLK),
.reset(reset),
.leds(leds)
);
endmodule |
module riscv_rv32i_insn (
input [31:0] insn,
output reg valid
);
always @* begin
valid = 0;
if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI
if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC
if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL
if (insn[6:0] == 7'b 11_001_11) begin // JALR
valid = insn[14:12] == 3'b 000;
end
if (insn[6:0] == 7'b 11_000_11) begin // BRANCH
valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011);
end
if (insn[6:0] == 7'b 00_000_11) begin // LOAD
valid = (insn[14:12] != 3'b 011) && (insn[14:12] != 3'b 110) && (insn[14:12] != 3'b 111);
end
if (insn[6:0] == 7'b 01_000_11) begin // STORE
valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010);
end
if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM
case (insn[14:12])
3'b 001: begin // SLLI
valid = insn[31:25] == 7'b 0000000;
end
3'b 101: begin // SRLI SRAI
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
default: begin
valid = 1;
end
endcase
end
if (insn[6:0] == 7'b 01_100_11) begin // OP
case (insn[14:12])
3'b 000, 3'b 101: begin // ADD SUB SRL SRA
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
default: begin
valid = insn[31:25] == 7'b 0000000;
end
endcase
end
end
endmodule |
module riscv_rv64i_insn (
input [31:0] insn,
output reg valid
);
always @* begin
valid = 0;
if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI
if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC
if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL
if (insn[6:0] == 7'b 11_001_11) begin // JALR
valid = insn[14:12] == 3'b 000;
end
if (insn[6:0] == 7'b 11_000_11) begin // BRANCH
valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011);
end
if (insn[6:0] == 7'b 00_000_11) begin // LOAD
valid = (insn[14:12] != 3'b 111);
end
if (insn[6:0] == 7'b 01_000_11) begin // STORE
valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010) || (insn[14:12] == 3'b 011);
end
if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM
case (insn[14:12])
3'b 001: begin // SLLI
valid = insn[31:26] == 6'b 000000;
end
3'b 101: begin // SRLI SRAI
valid = (insn[31:26] == 6'b 000000) || (insn[31:26] == 6'b 010000);
end
default: begin
valid = 1;
end
endcase
end
if (insn[6:0] == 7'b 01_100_11) begin // OP
case (insn[14:12])
3'b 000, 3'b 101: begin // ADD SUB SRL SRA
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
default: begin
valid = insn[31:25] == 7'b 0000000;
end
endcase
end
if (insn[6:0] == 7'b 00_110_11) begin // OP-IMM-32
case (insn[14:12])
3'b 001: begin // SLLIW
valid = insn[31:25] == 7'b 0000000;
end
3'b 101: begin // SRLIW SRAIW
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
3'b 000: begin // ADDIW
valid = 1;
end
endcase
end
if (insn[6:0] == 7'b 01_110_11) begin // OP-32
case (insn[14:12])
3'b 000, 3'b 101: begin // ADDW SUBW SRLW SRAW
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
3'b 001: begin // SLLW
valid = insn[31:25] == 7'b 0000000;
end
endcase
end
end
endmodule |
module riscv_rv64ic_insn (
input [31:0] insn,
output reg valid
);
always @* begin
valid = 0;
if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI
if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC
if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL
if (insn[6:0] == 7'b 11_001_11) begin // JALR
valid = insn[14:12] == 3'b 000;
end
if (insn[6:0] == 7'b 11_000_11) begin // BRANCH
valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011);
end
if (insn[6:0] == 7'b 00_000_11) begin // LOAD
valid = (insn[14:12] != 3'b 111);
end
if (insn[6:0] == 7'b 01_000_11) begin // STORE
valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010) || (insn[14:12] == 3'b 011);
end
if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM
case (insn[14:12])
3'b 001: begin // SLLI
valid = insn[31:26] == 6'b 000000;
end
3'b 101: begin // SRLI SRAI
valid = (insn[31:26] == 6'b 000000) || (insn[31:26] == 6'b 010000);
end
default: begin
valid = 1;
end
endcase
end
if (insn[6:0] == 7'b 01_100_11) begin // OP
case (insn[14:12])
3'b 000, 3'b 101: begin // ADD SUB SRL SRA
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
default: begin
valid = insn[31:25] == 7'b 0000000;
end
endcase
end
if (insn[6:0] == 7'b 00_110_11) begin // OP-IMM-32
case (insn[14:12])
3'b 001: begin // SLLIW
valid = insn[31:25] == 7'b 0000000;
end
3'b 101: begin // SRLIW SRAIW
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
3'b 000: begin // ADDIW
valid = 1;
end
endcase
end
if (insn[6:0] == 7'b 01_110_11) begin // OP-32
case (insn[14:12])
3'b 000, 3'b 101: begin // ADDW SUBW SRLW SRAW
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
3'b 001: begin // SLLW
valid = insn[31:25] == 7'b 0000000;
end
endcase
end
if (insn[31:16] == 16'b0 && insn[1:0] != 2'b11) begin
casez (insn[15:0])
// RVC -- Quadrant 0
16'b 000_???_???_??_???_00: valid = |insn[12:5]; // C.ADDI4SPN
16'b 010_???_???_??_???_00: valid = 1; // C.LW
16'b 011_???_???_??_???_00: valid = 1; // C.LD
16'b 110_???_???_??_???_00: valid = 1; // C.SW
16'b 111_???_???_??_???_00: valid = 1; // C.SD
// RVC -- Quadrant 1
16'b 000_?_??_???_??_???_01: valid = 1; // C.NOP, C.ADDI
16'b 001_?_??_???_??_???_01: valid = |insn[11:7]; // C.ADDIW
16'b 010_?_??_???_??_???_01: valid = 1; // C.LI
16'b 011_?_??_???_??_???_01: valid = |{insn[12], insn[6:2]}; // C.ADDI16SP, C.LUI
16'b 100_?_00_???_??_???_01: valid = 1; // C.SRLI
16'b 100_?_01_???_??_???_01: valid = 1; // C.SRAI
16'b 100_?_10_???_??_???_01: valid = 1; // C.ANDI
16'b 100_0_11_???_00_???_01: valid = 1; // C.SUB
16'b 100_0_11_???_01_???_01: valid = 1; // C.XOR
16'b 100_0_11_???_10_???_01: valid = 1; // C.OR
16'b 100_0_11_???_11_???_01: valid = 1; // C.AND
16'b 100_1_11_???_00_???_01: valid = 1; // C.SUBW
16'b 100_1_11_???_01_???_01: valid = 1; // C.ADDW
16'b 101_?_??_???_??_???_01: valid = 1; // C.J
16'b 110_?_??_???_??_???_01: valid = 1; // C.BEQZ
16'b 111_?_??_???_??_???_01: valid = 1; // C.BNEZ
// RVC -- Quadrant 2
16'b 000_?_?????_?????_10: valid = 1; // C.SLLI
16'b 010_?_?????_?????_10: valid = |insn[11:7]; // C.LWSP
16'b 011_?_?????_?????_10: valid = |insn[11:7]; // C.LDSP
16'b 100_0_?????_00000_10: valid = |insn[11:7]; // C.JR
16'b 100_0_?????_?????_10: valid = |insn[6:2]; // C.MV
16'b 100_1_00000_00000_10: valid = 0; // C.EBREAK (SYSTEM => valid=0)
16'b 100_1_?????_?????_10: valid = 1; // C.JALR, C.ADD
16'b 110_?_?????_?????_10: valid = 1; // C.SWSP
16'b 111_?_?????_?????_10: valid = 1; // C.SDSP
endcase
end
end
endmodule |
module riscv_rv32ic_insn (
input [31:0] insn,
output reg valid
);
always @* begin
valid = 0;
if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI
if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC
if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL
if (insn[6:0] == 7'b 11_001_11) begin // JALR
valid = insn[14:12] == 3'b 000;
end
if (insn[6:0] == 7'b 11_000_11) begin // BRANCH
valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011);
end
if (insn[6:0] == 7'b 00_000_11) begin // LOAD
valid = (insn[14:12] != 3'b 011) && (insn[14:12] != 3'b 110) && (insn[14:12] != 3'b 111);
end
if (insn[6:0] == 7'b 01_000_11) begin // STORE
valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010);
end
if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM
case (insn[14:12])
3'b 001: begin // SLLI
valid = insn[31:25] == 7'b 0000000;
end
3'b 101: begin // SRLI SRAI
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
default: begin
valid = 1;
end
endcase
end
if (insn[6:0] == 7'b 01_100_11) begin // OP
case (insn[14:12])
3'b 000, 3'b 101: begin // ADD SUB SRL SRA
valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);
end
default: begin
valid = insn[31:25] == 7'b 0000000;
end
endcase
end
if (insn[31:16] == 16'b0 && insn[1:0] != 2'b11) begin
casez (insn[15:0])
// RVC -- Quadrant 0
16'b 000_???_???_??_???_00: valid = |insn[12:5]; // C.ADDI4SPN
16'b 010_???_???_??_???_00: valid = 1; // C.LW
16'b 110_???_???_??_???_00: valid = 1; // C.SW
// RVC -- Quadrant 1
16'b 000_?_??_???_??_???_01: valid = 1; // C.NOP, C.ADDI
16'b 001_?_??_???_??_???_01: valid = 1; // C.JAL
16'b 010_?_??_???_??_???_01: valid = 1; // C.LI
16'b 011_?_??_???_??_???_01: valid = |{insn[12], insn[6:2]}; // C.ADDI16SP, C.LUI
16'b 100_?_00_???_??_???_01: valid = !insn[12]; // C.SRLI
16'b 100_?_01_???_??_???_01: valid = !insn[12]; // C.SRAI
16'b 100_?_10_???_??_???_01: valid = 1; // C.ANDI
16'b 100_0_11_???_00_???_01: valid = 1; // C.SUB
16'b 100_0_11_???_01_???_01: valid = 1; // C.XOR
16'b 100_0_11_???_10_???_01: valid = 1; // C.OR
16'b 100_0_11_???_11_???_01: valid = 1; // C.AND
16'b 101_?_??_???_??_???_01: valid = 1; // C.J
16'b 110_?_??_???_??_???_01: valid = 1; // C.BEQZ
16'b 111_?_??_???_??_???_01: valid = 1; // C.BNEZ
// RVC -- Quadrant 2
16'b 000_?_?????_?????_10: valid = !insn[12]; // C.SLLI
16'b 010_?_?????_?????_10: valid = |insn[11:7]; // C.LWSP
16'b 100_0_?????_00000_10: valid = |insn[11:7]; // C.JR
16'b 100_0_?????_?????_10: valid = |insn[6:2]; // C.MV
16'b 100_1_00000_00000_10: valid = 0; // C.EBREAK (SYSTEM => valid=0)
16'b 100_1_?????_?????_10: valid = 1; // C.JALR, C.ADD
16'b 110_?_?????_?????_10: valid = 1; // C.SWSP
endcase
end
end
endmodule |
module top_sapphire (
output wire my_pll_rstn,
input wire my_pll_locked,
//SOC
input wire io_systemClk,
input wire io_asyncReset,
output wire system_uart_0_io_txd,
input wire system_uart_0_io_rxd,
output wire system_i2c_0_io_sda_writeEnable,
output wire system_i2c_0_io_sda_write,
input wire system_i2c_0_io_sda_read,
output wire system_i2c_0_io_scl_writeEnable,
output wire system_i2c_0_io_scl_write,
input wire system_i2c_0_io_scl_read,
input wire [15:0]system_gpio_0_io_read,
output wire [15:0]system_gpio_0_io_write,
output wire [15:0]system_gpio_0_io_writeEnable,
output wire system_spi_0_io_sclk_write,
output wire system_spi_0_io_data_0_writeEnable,
input wire system_spi_0_io_data_0_read,
output wire system_spi_0_io_data_0_write,
output wire system_spi_0_io_data_1_writeEnable,
input wire system_spi_0_io_data_1_read,
output wire system_spi_0_io_data_1_write,
output wire system_spi_0_io_ss,
output wire system_spi_1_io_sclk_write,
output wire system_spi_1_io_data_0_writeEnable,
input wire system_spi_1_io_data_0_read,
output wire system_spi_1_io_data_0_write,
output wire system_spi_1_io_data_1_writeEnable,
input wire system_spi_1_io_data_1_read,
output wire system_spi_1_io_data_1_write,
output wire system_spi_1_io_ss,
//JTAG
input wire jtag_inst1_TCK,
input wire jtag_inst1_TDI,
output wire jtag_inst1_TDO,
input wire jtag_inst1_SEL,
input wire jtag_inst1_CAPTURE,
input wire jtag_inst1_SHIFT,
input wire jtag_inst1_UPDATE,
input wire jtag_inst1_RESET
);
/////////////////////////////////////////////////////////////////////////////
//Reset and PLL
wire mcuReset;
wire io_systemReset;
wire userInterrupt;
/////////////////////////////////////////////////////////////////////////////
//Reset and PLL
assign mcuReset = ~( io_asyncReset & my_pll_locked );
assign my_pll_rstn = 1'b1;
//I2C
assign system_i2c_0_io_sda_writeEnable = !system_i2c_0_io_sda_write;
assign system_i2c_0_io_scl_writeEnable = !system_i2c_0_io_scl_write;
sapphire0 sapphire0_inst
(
.io_systemClk (io_systemClk),
.io_asyncReset (mcuReset),
.io_systemReset (io_systemReset),
.system_uart_0_io_txd (system_uart_0_io_txd),
.system_uart_0_io_rxd (system_uart_0_io_rxd),
.system_i2c_0_io_sda_write (system_i2c_0_io_sda_write),
.system_i2c_0_io_sda_read (system_i2c_0_io_sda_read),
.system_i2c_0_io_scl_write (system_i2c_0_io_scl_write),
.system_i2c_0_io_scl_read (system_i2c_0_io_scl_read),
.system_gpio_0_io_read (system_gpio_0_io_read[15:0]),
.system_gpio_0_io_write (system_gpio_0_io_write[15:0]),
.system_gpio_0_io_writeEnable (system_gpio_0_io_writeEnable[15:0]),
.userInterruptA (userInterrupt),
.system_spi_0_io_sclk_write (system_spi_0_io_sclk_write),
.system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable),
.system_spi_0_io_data_0_read (system_spi_0_io_data_0_read),
.system_spi_0_io_data_0_write (system_spi_0_io_data_0_write),
.system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable),
.system_spi_0_io_data_1_read (system_spi_0_io_data_1_read),
.system_spi_0_io_data_1_write (system_spi_0_io_data_1_write),
.system_spi_0_io_ss (system_spi_0_io_ss),
.system_spi_1_io_sclk_write (system_spi_1_io_sclk_write),
.system_spi_1_io_data_0_writeEnable (system_spi_1_io_data_0_writeEnable),
.system_spi_1_io_data_0_read (system_spi_1_io_data_0_read),
.system_spi_1_io_data_0_write (system_spi_1_io_data_0_write),
.system_spi_1_io_data_1_writeEnable (system_spi_1_io_data_1_writeEnable),
.system_spi_1_io_data_1_read (system_spi_1_io_data_1_read),
.system_spi_1_io_data_1_write (system_spi_1_io_data_1_write),
.system_spi_1_io_ss (system_spi_1_io_ss),
.jtagCtrl_tck (jtag_inst1_TCK),
.jtagCtrl_tdi (jtag_inst1_TDI),
.jtagCtrl_tdo (jtag_inst1_TDO),
.jtagCtrl_enable (jtag_inst1_SEL),
.jtagCtrl_capture (jtag_inst1_CAPTURE),
.jtagCtrl_shift (jtag_inst1_SHIFT),
.jtagCtrl_update (jtag_inst1_UPDATE),
.jtagCtrl_reset (jtag_inst1_RESET)
);
endmodule |
module xyloni
(
input BTN1,
input BTN2_J2_7,
input [14:0] GPIO_J1_IN,
input [13:0] GPIO_J2_IN,
input [8:0] GPIO_J3_IN,
input RXD,
input SD_DI,
input SPI_MISO,
input i_sysclk,
input i_pll_locked,
output [14:0] GPIO_J1_OUT,
output [14:0] GPIO_J1_OE,
output [13:0] GPIO_J2_OUT,
output [13:0] GPIO_J2_OE,
output [8:0] GPIO_J3_OUT,
output [8:0] GPIO_J3_OE,
output LED1,
output LED2,
output LED3_J2_6,
output LED4_J2_5,
output SD_CS,
output SD_DO,
output SD_SCLK,
output SPI_MOSI,
output SPI_SCLK,
output SPI_SS,
output TXD
);
endmodule |
module tft_tester
#(
parameter MAX_HRES = 512,
parameter MAX_VRES = 1024,
parameter COLOR_PRECISION = 8,
parameter TFT_DLYC_WIDTH = 22,
parameter TFT_DLY_VAL = 2**22-1,
parameter TFT_TCHW = 2,
parameter TFT_TWRL = 2,
parameter TFT_TWRH = 2,
parameter TFT_TRDL = 4,
parameter TFT_TRDH = 4,
parameter RGB_IN_L = 2
)
(
input i_arstn,
input i_sysclk,
input i_pll_locked,
output o_pll_rstn,
input jtag_inst1_CAPTURE,
input jtag_inst1_DRCK,
input jtag_inst1_RESET,
input jtag_inst1_RUNTEST,
input jtag_inst1_SEL,
input jtag_inst1_SHIFT,
input jtag_inst1_TCK,
input jtag_inst1_TDI,
input jtag_inst1_TMS,
input jtag_inst1_UPDATE,
output jtag_inst1_TDO,
output o_srst,
output o_lcd_init_done,
output o_csx,
output o_dcx,
output o_wrx,
output o_rdx,
input [COLOR_PRECISION*3-1:0]i_d,
output [COLOR_PRECISION*3-1:0]o_d,
output [COLOR_PRECISION*3-1:0]o_oe
);
function integer log2;
input integer val;
integer i;
begin
log2 = 0;
for (i=0; 2**i<val; i=i+1)
log2 = i+1;
end
endfunction
wire w_srst;
wire w_vio_on;
wire w_vio_off;
wire [log2(MAX_HRES)-1:0]w_vio_hres;
wire [log2(MAX_VRES)-1:0]w_vio_vres;
wire [log2(MAX_HRES)-1:0]w_vio_hpix;
wire w_vio_en;
wire w_vio_mode;
wire w_vio_we;
wire w_vio_re;
wire [COLOR_PRECISION*3-1:0]w_vio_rgb;
wire [3:0]w_state;
wire [log2(MAX_HRES)-1:0]w_x;
wire [log2(MAX_VRES)-1:0]w_y;
wire w_lcd_init_done;
wire w_csx;
wire w_dcx;
wire w_wrx;
wire w_rdx;
wire [COLOR_PRECISION*3-1:0]w_d;
wire [COLOR_PRECISION*3-1:0]w_oe;
reg r_vio_we;
assign o_pll_rstn = i_arstn;
reset
#(
.IN_RST_ACTIVE ("LOW"),
.OUT_RST_ACTIVE ("HIGH"),
.CYCLE (1)
)
inst_reset
(
.i_arst (i_pll_locked),
.i_clk (i_sysclk),
.o_srst (w_srst)
);
edb_top edb_top_inst (
.bscan_CAPTURE ( jtag_inst1_CAPTURE ),
.bscan_DRCK ( jtag_inst1_DRCK ),
.bscan_RESET ( jtag_inst1_RESET ),
.bscan_RUNTEST ( jtag_inst1_RUNTEST ),
.bscan_SEL ( jtag_inst1_SEL ),
.bscan_SHIFT ( jtag_inst1_SHIFT ),
.bscan_TCK ( jtag_inst1_TCK ),
.bscan_TDI ( jtag_inst1_TDI ),
.bscan_TMS ( jtag_inst1_TMS ),
.bscan_UPDATE ( jtag_inst1_UPDATE ),
.bscan_TDO ( jtag_inst1_TDO ),
.vio0_clk ( i_sysclk ),
.vio0_on ( w_vio_on ),
.vio0_off ( w_vio_off ),
.vio0_hres ( w_vio_hres ),
.vio0_vres ( w_vio_vres ),
.vio0_hpix ( w_vio_hpix ),
.vio0_en ( w_vio_en ),
.vio0_mode ( w_vio_mode ),
.vio0_we ( w_vio_we ),
.vio0_re ( w_vio_re ),
.vio0_rgb ( w_vio_rgb ),
.vio0_next ( w_next ),
.vio0_back ( w_back ),
.vio0_interrupt ( w_interrupt ),
.vio0_state ( w_state ),
.la0_clk ( i_sysclk ),
.la0_csx ( w_csx ),
.la0_dcx ( w_dcx ),
.la0_wrx ( w_wrx ),
.la0_rdx ( w_rdx ),
.la0_o_d ( w_d ),
.la0_oe ( w_oe ),
.la0_i_d ( i_d ),
.la0_state ( w_state ),
.la0_x ( w_x ),
.la0_y ( w_y )
);
always@(posedge w_srst or posedge i_sysclk)
begin
if (w_srst)
r_vio_we <= 1'b0;
else
r_vio_we <= w_vio_we;
end
mpu_interface
#(
.HRES_WIDTH (log2(MAX_HRES)),
.VRES_WIDTH (log2(MAX_VRES)),
.DATA_WIDTH (COLOR_PRECISION*3),
.DLYC_WIDTH (TFT_DLYC_WIDTH),
.DLY_VAL (TFT_DLY_VAL),
.TCHW (TFT_TCHW),
.TWRL (TFT_TWRL),
.TWRH (TFT_TWRH),
.TRDL (TFT_TRDL),
.TRDH (TFT_TRDH),
.RGB_IN_L (RGB_IN_L)
)
inst_mpu_interface
(
.i_arst (w_srst),
.i_sysclk (i_sysclk),
.i_width (w_vio_hres),
.i_height (w_vio_vres),
.i_pixel (w_vio_hpix),
.i_on (w_vio_on),
.i_off (w_vio_off),
.i_mode (w_vio_mode),
.i_de (w_vio_we & ~r_vio_we),
.i_rgb (w_vio_rgb),
.o_ack (w_re),
.o_x (w_x),
.o_y (w_y),
.o_state (w_state),
.o_init_done(w_lcd_init_done),
.o_csx (w_csx),
.o_dcx (w_dcx),
.o_wrx (w_wrx),
.o_rdx (w_rdx),
.o_d (w_d),
.o_oe (w_oe)
);
assign o_srst = ~w_srst;
assign o_lcd_init_done = w_lcd_init_done;
assign o_csx = w_csx;
assign o_dcx = w_dcx;
assign o_wrx = w_wrx;
assign o_rdx = w_rdx;
assign o_d = w_d;
assign o_oe = w_oe;
endmodule |
module mpu_interface
#(
parameter HRES_WIDTH = 9,
parameter VRES_WIDTH = 10,
parameter DATA_WIDTH = 24,
parameter DLYC_WIDTH = 22,
parameter DLY_VAL = 1,
parameter TCHW = 2,
parameter TWRL = 4,
parameter TWRH = 4,
parameter TRDL = 4,
parameter TRDH = 4,
parameter RGB_IN_L = 2
)
(
input i_arst,
input i_sysclk,
input [HRES_WIDTH-1:0]i_width,
input [VRES_WIDTH-1:0]i_height,
input [HRES_WIDTH-1:0]i_pixel,
input i_on,
input i_off,
input i_mode,
input i_de,
input [DATA_WIDTH-1:0]i_rgb,
output o_ack,
output [3:0]o_state,
output [HRES_WIDTH-1:0]o_x,
output [VRES_WIDTH-1:0]o_y,
output o_init_done,
output o_csx,
output o_dcx,
output o_wrx,
output o_rdx,
output [DATA_WIDTH-1:0]o_d,
output [DATA_WIDTH-1:0]o_oe
);
localparam s_reset = 3'b000;
localparam s_init = 3'b001;
localparam s_delay = 3'b010;
localparam s_idle = 3'b011;
localparam s_rawwr = 3'b100;
localparam s_ramwrd = 3'b101;
localparam s_sleep = 3'b110;
wire w_nop;
wire w_sel;
wire w_cmd;
wire w_dat;
wire [5:0]w_tWRL;
wire [5:0]w_tWRH;
wire [5:0]w_tRDL;
wire [5:0]w_tRDH;
wire [DLYC_WIDTH-1:0]w_dly_val;
wire [2:0]w_rgb_in_l;
assign w_nop = `DES;
assign w_sel = `SEL;
assign w_cmd = `CMD;
assign w_dat = `DAT;
assign w_tWRL = TWRL-1'b1;
assign w_tWRH = TWRL+TWRH-1'b1;
assign w_tRDL = TRDL-1'b1;
assign w_tRDH = TRDL+TRDH-1'b1;
assign w_dly_val = DLY_VAL;
assign w_rgb_in_l = RGB_IN_L;
wire [15:0]w_reg;
wire w_dcx;
reg [2:0]r_state_1P;
reg r_init_done_1P;
reg [4:0]r_cnt_1P;
reg [DLYC_WIDTH-1:0]r_dly_1P;
reg [HRES_WIDTH-1:0]r_x_1P;
reg [VRES_WIDTH-1:0]r_y_1P;
reg [HRES_WIDTH-1:0]r_p_1P;
reg r_ack_1P;
reg r_ren_1P;
reg r_csx_1P;
reg r_dcx_1P;
reg r_wrx_1P;
reg r_rdx_1P;
reg [DATA_WIDTH-1:0]r_d_1P;
reg [DATA_WIDTH-1:0]r_oe_1P;
reg [5:0]r_cycle_1P;
reg [2:0]r_rgb_in_l_1P;
nt35510_reg
inst_nt35510_reg
(
.i_adr (r_cnt_1P),
.o_reg (w_reg),
.o_dcx (w_dcx)
);
`ifdef RTL_SIM
initial
begin
$display("Hihi mpu_interface.v");
$display("DLY_VAL = %h", w_dly_val);
$display("DLYC_WIDTH = %d", DLYC_WIDTH);
end
`endif
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_state_1P <= s_reset;
r_init_done_1P <= 1'b0;
r_cnt_1P <= {5{1'b0}};
r_dly_1P <= {DLYC_WIDTH{1'b0}};
r_x_1P <= {HRES_WIDTH{1'b0}};
r_y_1P <= {VRES_WIDTH{1'b0}};
r_x_1P <= {HRES_WIDTH{1'b0}};
r_ack_1P <= 1'b0;
r_ren_1P <= 1'b0;
r_csx_1P <= w_nop;
r_dcx_1P <= w_dat;
r_wrx_1P <= w_nop;
r_rdx_1P <= w_nop;
r_d_1P <= {8'h0, 8'h0, 8'h0};
r_oe_1P <= {DATA_WIDTH{1'b0}};
r_cycle_1P <= {6{1'b0}};
r_rgb_in_l_1P <= {3{1'b0}};
end
else
begin
r_ack_1P <= 1'b0;
r_ren_1P <= 1'b0;
case (r_state_1P)
s_reset:
begin
r_dly_1P <= r_dly_1P+1'b1;
if (r_dly_1P == w_dly_val)
begin
r_state_1P <= s_init;
r_csx_1P <= w_sel;
r_dcx_1P <= w_dcx;
r_wrx_1P <= w_sel;
r_rdx_1P <= w_nop;
r_d_1P <= {8'h0, w_reg};
r_oe_1P <= {DATA_WIDTH{1'b1}};
r_cnt_1P <= r_cnt_1P+1'b1;
`ifdef RTL_SIM
r_dly_1P <= {DLYC_WIDTH{1'b0}};
`endif
end
end
s_init:
begin
r_cycle_1P <= r_cycle_1P+1'b1;
if (r_cycle_1P == w_tWRL)
r_wrx_1P <= ~r_wrx_1P;
else if (r_cycle_1P == w_tWRH)
begin
r_wrx_1P <= ~r_wrx_1P;
r_cycle_1P <= {6{1'b0}};
r_dcx_1P <= w_dcx;
r_d_1P <= {8'h0, w_reg};
r_cnt_1P <= r_cnt_1P+1'b1;
if (r_cnt_1P == `DELAY)
begin
r_state_1P <= s_delay;
r_csx_1P <= w_nop;
r_dcx_1P <= w_dat;
r_wrx_1P <= w_nop;
r_rdx_1P <= w_nop;
r_d_1P <= {8'h0, 8'h0, 8'h0};
r_oe_1P <= {DATA_WIDTH{1'b0}};
r_cnt_1P <= r_cnt_1P;
end
else if (r_cnt_1P == `INIT_DONE)
begin
r_state_1P <= s_idle;
r_init_done_1P <= 1'b1;
r_csx_1P <= w_nop;
r_dcx_1P <= w_dat;
r_wrx_1P <= w_nop;
r_rdx_1P <= w_nop;
r_d_1P <= {8'h0, 8'h0, 8'h0};
r_oe_1P <= {DATA_WIDTH{1'b0}};
r_cnt_1P <= `SLEEP;
end
else if (r_cnt_1P == `EOF)
begin
r_state_1P <= s_sleep;
r_init_done_1P <= 1'b0;
r_csx_1P <= w_nop;
r_dcx_1P <= w_dat;
r_wrx_1P <= w_nop;
r_rdx_1P <= w_nop;
r_d_1P <= {8'h0, 8'h0, 8'h0};
r_oe_1P <= {DATA_WIDTH{1'b0}};
r_cnt_1P <= {5{1'b0}};
end
end
end
s_delay:
begin
r_dly_1P <= r_dly_1P+1'b1;
if (r_dly_1P == w_dly_val)
begin
r_state_1P <= s_init;
r_csx_1P <= w_sel;
r_dcx_1P <= w_dcx;
r_wrx_1P <= w_sel;
r_rdx_1P <= w_nop;
r_d_1P <= {8'h0, w_reg};
r_oe_1P <= {DATA_WIDTH{1'b1}};
r_cnt_1P <= r_cnt_1P+1'b1;
`ifdef RTL_SIM
r_dly_1P <= {DLYC_WIDTH{1'b0}};
`endif
end
end
s_idle:
begin
if (i_off)
begin
r_state_1P <= s_init;
r_csx_1P <= w_sel;
r_dcx_1P <= w_dcx;
r_wrx_1P <= w_sel;
r_rdx_1P <= w_nop;
r_d_1P <= {8'h0, w_reg};
r_oe_1P <= {DATA_WIDTH{1'b1}};
r_cnt_1P <= r_cnt_1P+1'b1;
end
else if (i_de)
begin
r_state_1P <= s_rawwr;
r_csx_1P <= w_sel;
r_dcx_1P <= w_cmd;
r_wrx_1P <= w_sel;
r_rdx_1P <= w_nop;
r_oe_1P <= {DATA_WIDTH{1'b1}};
if (i_mode)
begin
r_p_1P <= r_x_1P+i_pixel;
r_d_1P <= {8'h0, `RAMWRC, 8'h0};
end
else
begin
r_p_1P <= i_width;
r_d_1P <= {8'h0, `RAMWR, 8'h0};
end
end
end
s_rawwr:
begin
r_csx_1P <= w_sel;
// r_dcx_1P <= w_cmd;
r_rdx_1P <= w_nop;
r_cycle_1P <= r_cycle_1P+1'b1;
if (r_cycle_1P == w_tWRL)
begin
r_ack_1P <= 1'b1;
r_wrx_1P <= ~r_wrx_1P;
end
else if (r_cycle_1P == w_tWRH)
begin
r_dcx_1P <= w_dat;
r_cycle_1P <= {6{1'b0}};
begin
r_state_1P <= s_ramwrd;
r_wrx_1P <= ~r_wrx_1P;
r_d_1P <= i_rgb;
end
end
end
s_ramwrd:
begin
r_csx_1P <= w_sel;
r_dcx_1P <= w_dat;
r_rdx_1P <= w_nop;
r_cycle_1P <= r_cycle_1P+1'b1;
if (r_cycle_1P == w_tWRL)
begin
r_ack_1P <= 1'b1;
r_wrx_1P <= ~r_wrx_1P;
end
else if (r_cycle_1P == w_tWRH)
begin
r_wrx_1P <= ~r_wrx_1P;
r_d_1P <= i_rgb;
r_x_1P <= r_x_1P+1'b1;
r_cycle_1P <= {6{1'b0}};
if (r_x_1P == i_width)
begin
r_x_1P <= {HRES_WIDTH{1'b0}};
r_y_1P <= r_y_1P+1'b1;
if (r_y_1P == i_height)
begin
r_state_1P <= s_idle;
r_csx_1P <= w_nop;
r_wrx_1P <= w_nop;
r_d_1P <= {8'h0, 8'h0, 8'h0};
r_oe_1P <= {DATA_WIDTH{1'b0}};
r_y_1P <= {VRES_WIDTH{1'b0}};
end
end
if (i_mode && r_x_1P == r_p_1P)
begin
r_state_1P <= s_idle;
r_csx_1P <= w_nop;
r_wrx_1P <= w_nop;
r_d_1P <= {8'h0, 8'h0, 8'h0};
r_oe_1P <= {DATA_WIDTH{1'b0}};
end
end
end
s_sleep:
begin
if (i_on)
r_state_1P <= s_reset;
end
default:
begin
r_state_1P <= s_reset;
r_init_done_1P <= 1'b0;
r_cnt_1P <= {5{1'b0}};
r_dly_1P <= {DLYC_WIDTH{1'b0}};
r_x_1P <= {HRES_WIDTH{1'b0}};
r_y_1P <= {VRES_WIDTH{1'b0}};
r_ren_1P <= 1'b0;
r_csx_1P <= w_nop;
r_dcx_1P <= w_dat;
r_wrx_1P <= w_nop;
r_rdx_1P <= w_nop;
r_d_1P <= {8'h0, 8'h0, 8'h0};
r_oe_1P <= {DATA_WIDTH{1'b0}};
r_cycle_1P <= {6{1'b0}};
r_rgb_in_l_1P <= {3{1'b0}};
end
endcase
end
end
assign o_ack = r_ack_1P;
assign o_state = r_state_1P;
assign o_x = r_x_1P;
assign o_u = r_y_1P;
assign o_init_done = r_init_done_1P;
assign o_ren = r_ren_1P;
assign o_csx = r_csx_1P;
assign o_dcx = r_dcx_1P;
assign o_wrx = r_wrx_1P;
assign o_rdx = r_rdx_1P;
assign o_d = r_d_1P;
assign o_oe = r_oe_1P;
endmodule |
module line_buffer
#(
parameter COLOR_PRECISION = 8,
parameter MAX_HRES = 480,
parameter HRES_WIDTH = 9,
parameter LINE = 16,
parameter Y_XI_SUBSAMPLE = 1,
parameter Y_YI_SUBSAMPLE = 1,
parameter C_XI_SUBSAMPLE = 2,
parameter C_YI_SUBSAMPLE = 2,
parameter Y_XO_SUBSAMPLE = 1,
parameter Y_YO_SUBSAMPLE = 1,
parameter C_XO_SUBSAMPLE = 2,
parameter C_YO_SUBSAMPLE = 2,
parameter WR_ADDRESSING = "BLOCK",
parameter RD_ADDRESSING = "LINE",
parameter MCU_WIDTH = 8,
parameter MCU_HEIGHT = 8,
parameter BRAM_OUTPUT_REG = "FALSE"
)
(
input i_arst,
input i_sysclk,
input [HRES_WIDTH-1:0]i_hres,
input i_Y_we,
input i_U_we,
input i_V_we,
input [COLOR_PRECISION-1:0]i_Y_wd,
input [COLOR_PRECISION-1:0]i_U_wd,
input [COLOR_PRECISION-1:0]i_V_wd,
output o_full,
input i_re,
output [COLOR_PRECISION-1:0]o_Y_rd,
output [COLOR_PRECISION-1:0]o_U_rd,
output [COLOR_PRECISION-1:0]o_V_rd,
output o_nempty
);
function integer log2;
input integer val;
integer i;
begin
log2 = 0;
for (i=0; 2**i<val; i=i+1)
log2 = i+1;
end
endfunction
reg [log2(MAX_HRES)-1:0] r_wr_hres_x_1P;
reg [log2(MCU_WIDTH)-1:0] r_wr_mcu_x_1P;
reg [log2(LINE)-1:0] r_wr_hres_y_1P;
reg [log2(MCU_HEIGHT)-1:0] r_wr_mcu_y_1P;
reg r_wr_sample_x_cnt_1P;
reg r_wr_sample_y_cnt_1P;
reg r_full_1P;
reg [log2(MAX_HRES)-1:0] r_rd_hres_x_1P;
reg [log2(MCU_WIDTH)-1:0] r_rd_mcu_x_1P;
reg [log2(LINE)-1:0] r_rd_hres_y_1P;
reg [log2(MCU_HEIGHT)-1:0] r_rd_mcu_y_1P;
reg r_nempty_1P;
wire [log2(MAX_HRES)-1:0]w_hres;
wire [log2(LINE)+log2(MAX_HRES)-1:0]w_Y_wr_addr_1P;
wire [log2(LINE)+log2(MAX_HRES)-1:0]w_Y_rd_addr_1P;
wire [log2(LINE/C_YO_SUBSAMPLE)+log2(MAX_HRES/C_XO_SUBSAMPLE)-1:0]w_C_wr_addr_1P;
wire [log2(LINE/C_YO_SUBSAMPLE)+log2(MAX_HRES/C_XO_SUBSAMPLE)-1:0]w_C_rd_addr_1P;
wire [log2(MCU_WIDTH)-1:0]w_wr_x_mcu_end;
wire [log2(MCU_WIDTH)-1:0]w_wr_y_mcu_end;
wire w_wr_x_subsample;
wire w_wr_y_subsample;
wire [2:0]w_mcu_width_offset;
wire [2:0]w_mcu_height_offset;
wire [3:0]w_mcu_width_offset_x2;
wire [3:0]w_mcu_height_offset_x2;
assign w_hres = i_hres;
assign w_Y_wr_addr_1P = {r_wr_hres_y_1P, r_wr_hres_x_1P};
assign w_Y_rd_addr_1P = {r_rd_hres_y_1P, r_rd_hres_x_1P};
`ifdef RTL_SIM
initial
begin
$display("hihi line_buffer.v");
$display("Y_XI_SUBSAMPLE = %d", Y_XI_SUBSAMPLE);
$display("Y_YI_SUBSAMPLE = %d", Y_YI_SUBSAMPLE);
$display("C_XI_SUBSAMPLE = %d", C_XI_SUBSAMPLE);
$display("C_YI_SUBSAMPLE = %d", C_YI_SUBSAMPLE);
$display("Y_XO_SUBSAMPLE = %d", Y_XO_SUBSAMPLE);
$display("Y_YO_SUBSAMPLE = %d", Y_YO_SUBSAMPLE);
$display("C_XO_SUBSAMPLE = %d", C_XO_SUBSAMPLE);
$display("C_YO_SUBSAMPLE = %d", C_YO_SUBSAMPLE);
$display("HRES = %d", i_hres);
end
`endif
generate
begin
if (WR_ADDRESSING == "BLOCK")
begin
if (C_YI_SUBSAMPLE == 1 && C_XI_SUBSAMPLE == 1 && C_YO_SUBSAMPLE == 2 && C_XO_SUBSAMPLE == 2)
begin
assign w_C_wr_addr_1P = { r_wr_hres_y_1P[log2(MCU_HEIGHT)-1:C_YO_SUBSAMPLE-1], r_wr_hres_x_1P[log2(MAX_HRES)-1:C_XO_SUBSAMPLE-1]};
end
else if (C_YI_SUBSAMPLE == 2 && C_XI_SUBSAMPLE == 2 && C_YO_SUBSAMPLE == 2 && C_XO_SUBSAMPLE == 2)
begin
assign w_C_wr_addr_1P = { r_wr_hres_y_1P[log2(MCU_HEIGHT)-1:0],
r_wr_hres_x_1P[log2(MAX_HRES)-1:log2(MCU_WIDTH)+C_XO_SUBSAMPLE-1],
r_wr_hres_x_1P[log2(MCU_WIDTH)-1:0]};
end
end
else
assign w_C_wr_addr_1P = {r_wr_hres_y_1P[log2(LINE)-1:C_YO_SUBSAMPLE-1], r_wr_hres_x_1P[log2(MAX_HRES)-1:C_XO_SUBSAMPLE-1]};
end
endgenerate
assign w_C_rd_addr_1P = {r_rd_hres_y_1P[log2(LINE)-1:C_YO_SUBSAMPLE-1], r_rd_hres_x_1P[log2(MAX_HRES)-1:C_XO_SUBSAMPLE-1]};
assign w_wr_x_mcu_end = MCU_WIDTH-1'b1;
assign w_wr_y_mcu_end = MCU_HEIGHT-1'b1;
assign w_wr_x_subsample = C_XO_SUBSAMPLE-1'b1;
assign w_wr_y_subsample = C_YO_SUBSAMPLE-1'b1;
assign w_mcu_width_offset = MCU_WIDTH-1'b1;
assign w_mcu_height_offset = MCU_HEIGHT-1'b1;
assign w_mcu_width_offset_x2 = MCU_WIDTH*2-1'b1;
assign w_mcu_height_offset_x2 = MCU_HEIGHT*2-1'b1;
simple_dual_port_ram
#(
.DATA_WIDTH (COLOR_PRECISION),
.ADDR_WIDTH (log2(LINE/Y_YO_SUBSAMPLE)+log2(MAX_HRES/Y_XO_SUBSAMPLE)),
.OUTPUT_REG ("FALSE"),
.RAM_INIT_FILE (""),
.RAM_INIT_RADIX ("")
)
inst_line_buffer_Y
(
.wdata (i_Y_wd),
.waddr (w_Y_wr_addr_1P),
.raddr (w_Y_rd_addr_1P),
.we (i_Y_we),
.wclk (i_sysclk),
.re (1'b1),
.rclk (i_sysclk),
.rdata (o_Y_rd)
);
simple_dual_port_ram
#(
.DATA_WIDTH (COLOR_PRECISION),
.ADDR_WIDTH (log2(LINE/C_YO_SUBSAMPLE)+log2(MAX_HRES/C_XO_SUBSAMPLE)),
.OUTPUT_REG ("FALSE"),
.RAM_INIT_FILE (""),
.RAM_INIT_RADIX ("")
)
inst_line_buffer_U
(
.wdata (i_U_wd),
.waddr (w_C_wr_addr_1P),
.raddr (w_C_rd_addr_1P),
.we (i_U_we),
.wclk (i_sysclk),
.re (1'b1),
.rclk (i_sysclk),
.rdata (o_U_rd)
);
simple_dual_port_ram
#(
.DATA_WIDTH (COLOR_PRECISION),
.ADDR_WIDTH (log2(LINE/C_YO_SUBSAMPLE)+log2(MAX_HRES/C_XO_SUBSAMPLE)),
.OUTPUT_REG ("FALSE"),
.RAM_INIT_FILE (""),
.RAM_INIT_RADIX ("")
)
inst_line_buffer_V
(
.wdata (i_V_wd),
.waddr (w_C_wr_addr_1P),
.raddr (w_C_rd_addr_1P),
.we (i_V_we),
.wclk (i_sysclk),
.re (1'b1),
.rclk (i_sysclk),
.rdata (o_V_rd)
);
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_wr_hres_x_1P <= {log2(MAX_HRES){1'b0}};
r_wr_mcu_x_1P <= {log2(MCU_WIDTH){1'b0}};
r_wr_sample_x_cnt_1P <= {1{1'b0}};
r_wr_hres_y_1P <= {log2(LINE){1'b0}};
r_wr_mcu_y_1P <= {log2(MCU_HEIGHT){1'b0}};
r_wr_sample_y_cnt_1P <= {1{1'b0}};
r_full_1P <= 1'b0;
r_rd_hres_x_1P <= {log2(MAX_HRES){1'b0}};
r_rd_mcu_x_1P <= {log2(MCU_WIDTH){1'b0}};
r_rd_hres_y_1P <= {log2(LINE){1'b0}};
r_rd_mcu_y_1P <= {log2(MCU_HEIGHT){1'b0}};
r_nempty_1P <= 1'b0;
end
else
begin
if (WR_ADDRESSING == "BLOCK")
begin
if (i_Y_we)
begin
r_wr_hres_x_1P <= r_wr_hres_x_1P+1'b1;
r_wr_mcu_x_1P <= r_wr_mcu_x_1P+1'b1;
if (r_wr_mcu_x_1P == w_wr_x_mcu_end)
begin
r_wr_hres_x_1P <= r_wr_hres_x_1P-w_mcu_width_offset;
r_wr_hres_y_1P <= r_wr_hres_y_1P+1'b1;
r_wr_mcu_y_1P <= r_wr_mcu_y_1P+1'b1;
if (r_wr_mcu_y_1P == w_wr_y_mcu_end)
begin
r_wr_hres_x_1P <= r_wr_hres_x_1P+1'b1;
r_wr_hres_y_1P <= r_wr_hres_y_1P-w_mcu_height_offset;
if (C_XI_SUBSAMPLE != 1)
begin
r_wr_sample_x_cnt_1P <= r_wr_sample_x_cnt_1P+1'b1;
if (r_wr_sample_x_cnt_1P == w_wr_x_subsample)
begin
r_wr_hres_x_1P <= r_wr_hres_x_1P-w_mcu_width_offset_x2;
r_wr_hres_y_1P <= r_wr_hres_y_1P+1'b1;
r_wr_sample_x_cnt_1P <= {1{1'b0}};
if (C_YI_SUBSAMPLE != 1)
begin
r_wr_sample_y_cnt_1P <= r_wr_sample_y_cnt_1P+1'b1;
if (r_wr_sample_y_cnt_1P == w_wr_y_subsample)
begin
r_wr_hres_x_1P <= r_wr_hres_x_1P+1'b1;
r_wr_hres_y_1P <= r_wr_hres_y_1P-w_mcu_height_offset_x2;
r_wr_sample_y_cnt_1P <= {1{1'b0}};
// if (r_wr_hres_x_1P == w_hres-1'b1)
if (r_wr_hres_x_1P == w_hres)
begin
r_wr_hres_x_1P <= {log2(MAX_HRES){1'b0}};
r_wr_hres_y_1P <= r_wr_hres_y_1P+1'b1;
// T8 specific
r_full_1P <= 1'b1;
r_nempty_1P <= 1'b1;
end
end
end
// else if (r_wr_hres_x_1P == w_hres-1'b1)
else if (r_wr_hres_x_1P == w_hres)
begin
r_wr_hres_x_1P <= {log2(MAX_HRES){1'b0}};
r_wr_hres_y_1P <= r_wr_hres_y_1P+1'b1;
// T8 specific
r_full_1P <= 1'b1;
r_nempty_1P <= 1'b1;
end
end
end
// else if (r_wr_hres_x_1P == w_hres-1'b1)
else if (r_wr_hres_x_1P == w_hres)
begin
r_wr_hres_x_1P <= {log2(MAX_HRES){1'b0}};
r_wr_hres_y_1P <= r_wr_hres_y_1P+1'b1;
// T8 specific
r_full_1P <= 1'b1;
r_nempty_1P <= 1'b1;
end
end
end
end
end
else
begin
if (i_Y_we)
begin
r_wr_hres_x_1P <= r_wr_hres_x_1P+1'b1;
// if (r_wr_hres_x_1P == w_hres-1'b1)
if (r_wr_hres_x_1P == w_hres)
begin
r_wr_hres_x_1P <= {log2(MAX_HRES){1'b0}};
r_wr_hres_y_1P <= r_wr_hres_y_1P+1'b1;
if (r_wr_hres_y_1P == LINE-1'b1)
begin
r_wr_hres_y_1P <= {log2(LINE){1'b0}};
// T8 specific
r_full_1P <= 1'b1;
r_nempty_1P <= 1'b1;
end
end
end
end
if (RD_ADDRESSING == "BLOCK")
begin
if (i_re & r_nempty_1P)
begin
r_rd_hres_x_1P <= r_rd_hres_x_1P+1'b1;
r_rd_mcu_x_1P <= r_rd_mcu_x_1P+1'b1;
if (r_rd_mcu_x_1P == MCU_WIDTH-1'b1)
begin
r_rd_hres_x_1P <= r_rd_hres_x_1P-w_mcu_width_offset;
r_rd_mcu_x_1P <= {log2(MCU_WIDTH){1'b0}};
r_rd_hres_y_1P <= r_rd_hres_y_1P+1'b1;
r_rd_mcu_y_1P <= r_rd_mcu_y_1P+1'b1;
if (r_rd_mcu_y_1P == MCU_HEIGHT-1'b1)
begin
r_rd_hres_x_1P <= r_rd_hres_x_1P+1'b1;
r_rd_hres_y_1P <= r_rd_hres_y_1P-w_mcu_height_offset;
// if (r_rd_hres_x_1P == w_hres-1'b1)
if (r_rd_hres_x_1P == w_hres)
begin
r_rd_hres_x_1P <= {log2(MAX_HRES){1'b0}};
r_rd_mcu_y_1P <= {log2(MCU_HEIGHT){1'b0}};
r_rd_hres_y_1P <= r_rd_hres_y_1P+1'b1;
// T8 specific
r_full_1P <= 1'b0;
r_nempty_1P <= 1'b0;
end
end
end
end
end
else
begin
if (i_re & r_nempty_1P)
begin
r_rd_hres_x_1P <= r_rd_hres_x_1P+1'b1;
// if (r_rd_hres_x_1P == w_hres-1'b1)
if (r_rd_hres_x_1P == w_hres)
begin
r_rd_hres_x_1P <= {log2(MAX_HRES){1'b0}};
r_rd_hres_y_1P <= r_rd_hres_y_1P+1'b1;
if (r_rd_hres_y_1P == LINE-1'b1)
begin
r_rd_hres_y_1P <= {log2(LINE){1'b0}};
// T8 specific
r_full_1P <= 1'b0;
r_nempty_1P <= 1'b0;
end
end
end
end
end
end
assign o_full = r_full_1P;
assign o_nempty = r_nempty_1P;
endmodule |
module dq_idct
#(
parameter NUM_ACCUMULATOR = 3,
parameter NUM_CHANNEL = 3,
parameter AMPLITUDE_PRECISION = 16,
parameter COLOR_PRECISION = 8,
parameter ZIGZAG_MULTIPLEX = "SEQUENTIAL", // TIME
parameter YUV_COMPRESSION = 4,
parameter DQT_PRECISION = 8,
parameter DQT_BRAM_OUTPUT_REG = "TRUE",
parameter DQT_MIF = "../mif/wiki_dqt.memh",
parameter DQT_MULT_LATENCY = 0,
parameter DCT_PRECISION = 9,
// parameter DCT_BRAM_OUTPUT_REG = "FALSE",
// parameter DCT_MIF = "",
parameter DCT_MULT_LATENCY = 0,
parameter ACCU_MULT_LATENCY = 0
)
(
input i_arst,
input i_sysclk,
input i_Y_de,
input i_U_de,
input i_V_de,
input [AMPLITUDE_PRECISION-1:0]i_Y_B,
input [AMPLITUDE_PRECISION-1:0]i_U_B,
input [AMPLITUDE_PRECISION-1:0]i_V_B,
output o_Y_re,
output o_U_re,
output o_V_re,
input i_Y_lb_full,
input i_U_lb_full,
input i_V_lb_full,
output o_Y_lb_we,
output o_U_lb_we,
output o_V_lb_we,
output [COLOR_PRECISION-1:0]o_Y_lb,
output [COLOR_PRECISION-1:0]o_U_lb,
output [COLOR_PRECISION-1:0]o_V_lb
);
localparam c_Y = 0;
localparam c_U = 1;
localparam c_V = 2;
localparam s_idle = 2'b00;
localparam s_dct = 2'b01;
localparam s_flush = 2'b10;
wire [1:0]w_YUV_compression;
reg [1:0]r_DCT_state_1P;
reg r_load_1P;
reg r_done_1P;
reg [NUM_CHANNEL-1:0] r_re_1P;
reg [2:0] r_y_1P, r_x_1P;
reg [2:0] r_v_1P, r_u_1P;
reg [1:0] r_YUV_cyc_1P;
reg [NUM_CHANNEL-1:0]r_de_4P;
reg [COLOR_PRECISION-1:0]r_f_4P[0:NUM_CHANNEL-1];
wire [NUM_CHANNEL-1:0] w_de_0P;
wire [AMPLITUDE_PRECISION-1:0] w_B_0P[0:NUM_CHANNEL-1];
wire [2:0] w_lb_full_0P;
wire [DCT_PRECISION-1:0]w_dct_u_1P;
wire [DCT_PRECISION-1:0]w_dct_v_1P;
wire [DCT_PRECISION*2-1:0] w_dct_uv_2P;
wire [DQT_PRECISION-1:0] w_Q_Y_2P;
wire [DQT_PRECISION-1:0] w_Q_C_2P;
wire [DCT_PRECISION*2+DQT_PRECISION-1:0]w_dq_dct_Y_2P;
wire [DCT_PRECISION*2+DQT_PRECISION-1:0]w_dq_dct_C_2P;
wire [DCT_PRECISION*2+DQT_PRECISION-8-1:0]w_dq_dct_Y_div_2P;
wire [DCT_PRECISION*2+DQT_PRECISION-8-1:0]w_dq_dct_C_div_2P;
wire [DCT_PRECISION*2+DQT_PRECISION-8-1:0]w_dq_dct_div_2P[0:2];
wire [NUM_ACCUMULATOR-1:0]w_en_3P;
wire [COLOR_PRECISION:0]w_f_3P[NUM_CHANNEL-1:0];
wire [COLOR_PRECISION:0]w_f_sum_3P[NUM_CHANNEL-1:0];
assign w_de_0P[c_Y] = i_Y_de;
assign w_de_0P[c_U] = i_U_de;
assign w_de_0P[c_V] = i_V_de;
assign w_B_0P[c_Y] = i_Y_B;
assign w_B_0P[c_U] = i_U_B;
assign w_B_0P[c_V] = i_V_B;
assign w_lb_full_0P[c_Y] = i_Y_lb_full;
assign w_lb_full_0P[c_U] = i_U_lb_full;
assign w_lb_full_0P[c_V] = i_V_lb_full;
assign o_Y_re = r_re_1P[c_Y];
assign o_U_re = r_re_1P[c_U];
assign o_V_re = r_re_1P[c_V];
assign o_Y_lb_we = r_de_4P[c_Y];
assign o_U_lb_we = r_de_4P[c_U];
assign o_V_lb_we = r_de_4P[c_V];
assign o_Y_lb = r_f_4P[c_Y];
assign o_U_lb = r_f_4P[c_U];
assign o_V_lb = r_f_4P[c_V];
assign w_YUV_compression = YUV_COMPRESSION-1'b1;
`ifdef RTL_SIM
initial
begin
$display("Hihi dq_idct.v");
$display("YUV_COMPRESSION = %d", YUV_COMPRESSION);
end
`endif
true_dual_port_ram
#(
.DATA_WIDTH (DQT_PRECISION),
.ADDR_WIDTH (7),
.WRITE_MODE_1 ("READ_FIRST"),
.WRITE_MODE_2 ("READ_FIRST"),
.OUTPUT_REG_1 (DQT_BRAM_OUTPUT_REG),
.OUTPUT_REG_2 (DQT_BRAM_OUTPUT_REG),
.RAM_INIT_FILE (DQT_MIF),
.RAM_INIT_RADIX ("HEX")
)
inst_DQT
(
.we1 (1'b0),
.we2 (1'b0),
.clka (i_sysclk),
.clkb (i_sysclk),
.din1 ({DQT_PRECISION{1'b0}}),
.din2 ({DQT_PRECISION{1'b0}}),
.addr1 ({1'b0, r_v_1P, r_u_1P}),
.addr2 ({1'b1, r_v_1P, r_u_1P}),
.dout1 (w_Q_Y_2P),
.dout2 (w_Q_C_2P)
);
/*
true_dual_port_ram
#(
.DATA_WIDTH (DCT_PRECISION),
.ADDR_WIDTH (6),
.WRITE_MODE_1 ("READ_FIRST"),
.WRITE_MODE_2 ("READ_FIRST"),
.OUTPUT_REG_1 (DCT_BRAM_OUTPUT_REG),
.OUTPUT_REG_2 (DCT_BRAM_OUTPUT_REG),
.RAM_INIT_FILE (DCT_MIF),
.RAM_INIT_RADIX ("HEX")
)
inst_DCT
(
.we1 (1'b0),
.we2 (1'b0),
.clka (i_sysclk),
.clkb (i_sysclk),
.din1 ({8{1'b0}}),
.din2 ({8{1'b0}}),
.addr1 ({r_x_1P, r_u_1P}),
.addr2 ({r_y_1P, r_v_1P}}),
.dout1 (w_dct_x_2P),
.dout2 (w_dct_y_2P)
);
shift_reg
#(
.D_WIDTH(4*3),
.TAPE (1)
)
inst_dct_pipe
(
.i_arst (i_arst),
.i_clk (i_sysclk),
.i_d ({r_y_1P, r_x_1P, r_v_1P, r_u_1P}),
.o_q ({w_y_P, w_x_P, w_v_P, w_u_P})
);
*/
dct
inst_dct_xu
(
.i_Gxy(r_x_1P),
.i_Buv(r_u_1P),
.o_dct(w_dct_u_1P)
);
dct
inst_dct_yv
(
.i_Gxy(r_y_1P),
.i_Buv(r_v_1P),
.o_dct(w_dct_v_1P)
);
mult_a_signed_b_signed
#(
.A_WIDTH(DCT_PRECISION),
.B_WIDTH(DCT_PRECISION),
.LATENCY(1)
)
inst_mult_dct
(
.arst (i_arst),
.clk (i_sysclk),
.a (w_dct_u_1P),
.b (w_dct_v_1P),
.o (w_dct_uv_2P)
);
mult_a_signed_b_signed
#(
.A_WIDTH(DQT_PRECISION),
.B_WIDTH(DCT_PRECISION*2),
.LATENCY(0)
)
inst_mult_dq_dct_Y
(
.arst (i_arst),
.clk (i_sysclk),
.a (w_Q_Y_2P),
.b (w_dct_uv_2P),
.o (w_dq_dct_Y_2P)
);
mult_a_signed_b_signed
#(
.A_WIDTH(DQT_PRECISION),
.B_WIDTH(DCT_PRECISION*2),
.LATENCY(0)
)
inst_mult_dq_dct_C
(
.arst (i_arst),
.clk (i_sysclk),
.a (w_Q_C_2P),
.b (w_dct_uv_2P),
.o (w_dq_dct_C_2P)
);
assign w_dq_dct_Y_div_2P = w_dq_dct_Y_2P[DCT_PRECISION*2+DQT_PRECISION-1:8];
assign w_dq_dct_C_div_2P = w_dq_dct_C_2P[DCT_PRECISION*2+DQT_PRECISION-1:8];
assign w_dq_dct_div_2P[c_Y]= w_dq_dct_Y_div_2P;
assign w_dq_dct_div_2P[c_U]= w_dq_dct_C_div_2P;
assign w_dq_dct_div_2P[c_V]= w_dq_dct_C_div_2P;
genvar i;
generate
for (i=0; i<NUM_ACCUMULATOR; i=i+1)
begin
accumulator
#(
.A_IN_PRECISION (AMPLITUDE_PRECISION),
.B_IN_PRECISION (DCT_PRECISION*2+DQT_PRECISION-8),
.O_OUT_PRECISION(COLOR_PRECISION),
.MULT_LATENCY (ACCU_MULT_LATENCY)
)
inst_accumulator
(
.i_arst (i_arst),
.i_sysclk (i_sysclk),
.i_en (r_re_1P[i]),
.i_load (r_load_1P),
.i_a (w_B_0P[i]),
.i_b (w_dq_dct_div_2P[i]),
.o_en (w_en_3P[i]),
.o_O (w_f_3P[i])
);
assign w_f_sum_3P[i] = w_f_3P[i]+8'd128;
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_de_4P[i] <= 1'b0;
r_f_4P[i] <= {COLOR_PRECISION{1'b0}};
end
else
begin
r_de_4P[i] <= 1'b0;
if (r_done_1P)
begin
// r_de_4P[i] <= 1'b1;
r_de_4P[i] <= w_en_3P[i];
if (w_f_sum_3P[i][COLOR_PRECISION])
begin
if (w_f_3P[i][COLOR_PRECISION])
r_f_4P[i] <= {COLOR_PRECISION{1'b0}};
else
r_f_4P[i] <= {COLOR_PRECISION{1'b1}};
end
else
r_f_4P[i] <= w_f_sum_3P[i][COLOR_PRECISION-1:0];
end
end
end
end
endgenerate
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_DCT_state_1P <= s_idle;
r_load_1P <= 1'b0;
r_done_1P <= 1'b0;
r_re_1P <= {NUM_CHANNEL{1'b0}};
r_x_1P <= {3{1'b0}};
r_y_1P <= {3{1'b0}};
r_u_1P <= {3{1'b0}};
r_v_1P <= {3{1'b0}};
r_YUV_cyc_1P <= {2{1'b0}};
end
else
begin
r_load_1P <= 1'b0;
r_done_1P <= 1'b0;
case (r_DCT_state_1P)
s_idle:
begin
if (w_de_0P == {NUM_CHANNEL{1'b1}} && w_lb_full_0P == {3{1'b0}})
begin
r_DCT_state_1P <= s_dct;
r_load_1P <= 1'b1;
r_re_1P <= {NUM_CHANNEL{1'b1}};
r_u_1P <= r_u_1P+1'b1;
end
end
s_dct:
begin
r_u_1P <= r_u_1P+1'b1;
if (r_v_1P == {3{1'b0}} && r_u_1P == {3{1'b0}})
begin
r_load_1P <= 1'b1;
end
else if (r_u_1P == {3{1'b1}})
begin
r_v_1P <= r_v_1P+1'b1;
if (r_v_1P == {3{1'b1}})
begin
r_done_1P <= 1'b1;
r_x_1P <= r_x_1P+1'b1;
if (r_x_1P == {3{1'b1}})
begin
r_y_1P <= r_y_1P+1'b1;
if (r_y_1P == {3{1'b1}})
begin
r_DCT_state_1P <= s_flush;
end
end
end
end
end
s_flush:
begin
r_YUV_cyc_1P <= r_YUV_cyc_1P+1'b1;
if (r_YUV_cyc_1P == w_YUV_compression)
begin
r_DCT_state_1P <= s_idle;
r_re_1P <= {NUM_CHANNEL{1'b0}};
r_YUV_cyc_1P <= {2{1'b0}};
end
else
begin
r_DCT_state_1P <= s_dct;
r_load_1P <= 1'b1;
r_re_1P[c_V:c_U] <= {NUM_CHANNEL-1{1'b0}};
r_u_1P <= r_u_1P+1'b1;
end
end
default:
begin
r_DCT_state_1P <= s_idle;
r_load_1P <= 1'b0;
r_done_1P <= 1'b0;
r_re_1P <= {NUM_CHANNEL{1'b0}};
r_x_1P <= {3{1'b0}};
r_y_1P <= {3{1'b0}};
r_u_1P <= {3{1'b0}};
r_v_1P <= {3{1'b0}};
end
endcase
end
end
endmodule |
module rgb_to_cymk
#(
parameter COLOR_PRECISION = 8
)
(
input i_arst,
input i_sysclk,
input [COLOR_PRECISION-1:0]i_R,
input [COLOR_PRECISION-1:0]i_G,
input [COLOR_PRECISION-1:0]i_B,
output [COLOR_PRECISION-1:0]o_C,
output [COLOR_PRECISION-1:0]o_M,
output [COLOR_PRECISION-1:0]o_Y,
output [COLOR_PRECISION-1:0]o_K
);
reg [COLOR_PRECISION-1:0]r_R_1P, r_G_1P, r_B_1P, r_K_1P;
reg [COLOR_PRECISION-1:0]r_R_2P, r_G_2P, r_B_2P, r_K_2P;
reg [COLOR_PRECISION-1:0]r_C_3P, r_M_3P, r_Y_3P, r_K_3P;
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
end
else
begin
if (i_R > i_G)
r_K_1P <= i_R;
else
r_K_1P <= i_G;
if (r_B_1P > r_K_1P)
r_K_2P <= {COLOR_PRECISION{1'b1}} - r_B_1P;
else
r_K_2P <= {COLOR_PRECISION{1'b1}} - r_K_1P;
r_C_3P <= r_R_2P - r_K_2P;
r_M_3P <= r_G_2P - r_K_2P;
r_Y_3P <= r_B_2P - r_K_2P;
end
end
endmodule |
module jfif_parser
#(
parameter SOS_CNT_W = 4
)
(
input i_arst,
input i_sysclk,
`ifdef DBG_MODE
output [1:0]o_sos_status,
`endif
input i_byte_en,
input [7:0]i_byte,
output o_jfif_ready,
output o_jfif_eoi,
input i_sos_re,
output o_sos_start,
output [15:0]o_sos_width,
output [15:0]o_sos_height,
output o_sos_scan_en,
output o_sos_ecs_bit
);
sos_parser
#(
.CNT_W (SOS_CNT_W)
)
inst_sos_parser
(
.i_arst (i_arst),
.i_sysclk (i_sysclk),
`ifdef DBG_MODE
.o_scan_status (o_sos_status),
`endif
.i_byte_en (i_byte_en),
.i_byte (i_byte),
.o_ready (o_jfif_ready),
.o_eoi (o_jfif_eoi),
.i_re (i_sos_re),
.o_start (o_sos_start),
.o_width (o_sos_width),
.o_height (o_sos_height),
.o_scan_en (o_sos_scan_en),
.o_ecs_bit (o_sos_ecs_bit)
);
endmodule |
module subsampling
#(
parameter XI_SUBSAMPLE = 1,
parameter YI_SUBSAMPLE = 1,
parameter XO_SUBSAMPLE = 2,
parameter YO_SUBSAMPLE = 2,
parameter MCU_WIDTH = 8,
parameter MCU_HEIGHT = 8,
parameter COLOR_PRECISION = 8,
parameter REGISTER = "YES"
)
(
input i_arst,
input i_sysclk,
input i_we,
input [COLOR_PRECISION-1:0]i_color,
output o_we,
output [COLOR_PRECISION-1:0]o_color
);
function integer log2;
input integer val;
integer i;
begin
log2 = 0;
for (i=0; 2**i<val; i=i+1)
log2 = i+1;
end
endfunction
wire w_x_subsample;
wire w_y_subsample;
wire [log2(MCU_WIDTH)-1:0]w_mcu_width;
wire [log2(MCU_HEIGHT)-1:0]w_mcu_height;
reg r_x_1P;
reg r_y_1P;
reg [log2(MCU_WIDTH)-1:0]r_w_1P;
reg [log2(MCU_HEIGHT)-1:0]r_h_1P;
reg r_we_1P;
reg [COLOR_PRECISION-1:0]r_color_1P;
wire w_we_0P;
wire [COLOR_PRECISION-1:0]w_color_0P;
assign w_x_subsample = XO_SUBSAMPLE/XI_SUBSAMPLE-1'b1;
assign w_y_subsample = YO_SUBSAMPLE/YI_SUBSAMPLE-1'b1;
assign w_mcu_width = MCU_WIDTH-1'b1;
assign w_mcu_height = MCU_HEIGHT-1'b1;
assign w_we_0P = (r_y_1P == 1'b0 && r_x_1P == 1'b0)?
i_we:1'b0;
assign w_color_0P = i_color;
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_x_1P <= 1'b0;
r_y_1P <= 1'b0;
r_w_1P <= {log2(MCU_WIDTH){1'b0}};
r_h_1P <= {log2(MCU_HEIGHT){1'b0}};
r_we_1P <= 1'b0;
r_color_1P <= {COLOR_PRECISION{1'b0}};
end
else
begin
if (i_we)
begin
r_x_1P <= r_x_1P+1'b1;
r_w_1P <= r_w_1P+1'b1;
if (r_x_1P == w_x_subsample)
r_x_1P <= 1'b0;
if (r_w_1P == w_mcu_width)
begin
r_w_1P <= {log2(MCU_WIDTH){1'b0}};
r_y_1P <= r_y_1P+1'b1;
r_h_1P <= r_h_1P+1'b1;
if (r_y_1P == w_y_subsample)
r_y_1P <= 1'b0;
if (r_h_1P == w_mcu_height)
r_h_1P <= {log2(MCU_HEIGHT){1'b0}};
end
end
r_we_1P <= w_we_0P;
r_color_1P <= w_color_0P;
end
end
generate
if (REGISTER == "YES")
begin
assign o_we = r_we_1P;
assign o_color = r_color_1P;
end
else
begin
assign o_we = w_we_0P;
assign o_color = w_color_0P;
end
endgenerate
endmodule |
module jpeg_decoder
#(
parameter SOS_CNT_W = 4,
parameter AMPLITUDE_PRECISION = 16,
parameter DHT_BST_MIF = "../mif/adobe_web/adobe_web_dht_bst.memh",
parameter Y_DC_CW_MIF = "../mif/t8/adobe_web_y_dc_codeword.memb",
parameter Y_AC_CW_MIF = "../mif/adobe_web/adobe_web_y_ac_codeword.memb",
parameter Y_S1_MIF = "../mif/adobe_web/adobe_web_y_symbol1.memh",
parameter C_DC_CW_MIF = "../mif/t8/adobe_web_y_dc_codeword.memb",
parameter C_AC_CW_MIF = "../mif/adobe_web/adobe_web_c_ac_codeword.memb",
parameter C_S1_MIF = "../mif/adobe_web/adobe_web_c_symbol1.memh",
parameter Y_X_SUBSAMPLE = 1,
parameter Y_Y_SUBSAMPLE = 1,
parameter C_X_SUBSAMPLE = 2,
parameter C_Y_SUBSAMPLE = 2,
parameter NUM_MATRIX_Y = 4,
parameter NUM_MATRIX_U = 4,
parameter NUM_MATRIX_V = 4,
`ifdef RTL_SIM
parameter REF_MTX_Y = "ref_mtx_Y.txt",
parameter REF_MTX_U = "ref_mtx_U.txt",
parameter REF_MTX_V = "ref_mtx_V.txt",
`endif
parameter NUM_ACCUMULATOR = 3,
parameter NUM_CHANNEL = 3,
parameter MCU_WIDTH = 8,
parameter MCU_HEIGHT = 8,
parameter COLOR_PRECISION = 8,
parameter ZIGZAG_MULTIPLEX = "SEQUENTIAL",
parameter DQT_PRECISION = 8,
parameter DQT_BRAM_OUTPUT_REG = "FALSE",
parameter DQT_MIF = "../mif/wiki_dqt.memh",
parameter DQT_MULT_LATENCY = 0,
parameter DCT_PRECISION = 9,
// parameter DCT_BRAM_OUTPUT_REG = "FALSE",
// parameter DCT_MIF = "",
parameter DCT_MULT_LATENCY = 0,
parameter ACCU_MULT_LATENCY = 0,
parameter PX_OUT = 1,
parameter PY_OUT = 1
)
(
input i_arst,
input i_sysclk,
`ifdef DBG_MODE
output [1:0]o_sos_status,
output [2:0]o_scan_state,
`endif
input i_byte_en,
input [7:0]i_byte,
output o_jfif_ready,
output o_jfif_eoi,
output [15:0]o_width,
output [15:0]o_height,
`ifdef RTL_SIM
output [15:0]o_sim_Y_wr_mcu,
output [15:0]o_sim_U_wr_mcu,
output [15:0]o_sim_V_wr_mcu,
`endif
input i_Y_lb_full,
input i_U_lb_full,
input i_V_lb_full,
output o_Y_lb_we,
output o_U_lb_we,
output o_V_lb_we,
output [COLOR_PRECISION-1:0]o_Y_lb,
output [COLOR_PRECISION-1:0]o_U_lb,
output [COLOR_PRECISION-1:0]o_V_lb
);
localparam c_Y = 0;
localparam c_U = 1;
localparam c_V = 2;
wire w_start;
wire w_scan_en;
wire w_ecs_bit;
wire w_Y_dq_ready;
wire w_U_dq_ready;
wire w_V_dq_ready;
wire w_ed_ready;
wire w_Y_de;
wire w_U_de;
wire w_V_de;
wire [AMPLITUDE_PRECISION-1:0]w_Y_B;
wire [AMPLITUDE_PRECISION-1:0]w_U_B;
wire [AMPLITUDE_PRECISION-1:0]w_V_B;
wire w_Y_mx_full;
wire w_Y_mx_re;
wire [PY_OUT*PX_OUT*AMPLITUDE_PRECISION-1:0]w_Y_mx_md;
wire w_Y_mx_nempty;
wire w_U_mx_full;
wire w_U_mx_re;
wire [PY_OUT*PX_OUT*AMPLITUDE_PRECISION-1:0]w_U_mx_md;
wire w_U_mx_nempty;
wire w_V_mx_full;
wire w_V_mx_re;
wire [PY_OUT*PX_OUT*AMPLITUDE_PRECISION-1:0]w_V_mx_md;
wire w_V_mx_nempty;
wire w_Y_lb_full;
wire w_U_lb_full;
wire w_V_lb_full;
wire w_Y_lb_we;
wire w_U_lb_we;
wire w_V_lb_we;
wire [COLOR_PRECISION-1:0]w_Y_lb;
wire [COLOR_PRECISION-1:0]w_U_lb;
wire [COLOR_PRECISION-1:0]w_V_lb;
`ifdef RTL_SIM
initial
begin
$display("Hihi jpeg_decoder.v");
$display("Y_X_SUBSAMPLE = %d", Y_X_SUBSAMPLE);
$display("Y_Y_SUBSAMPLE = %d", Y_Y_SUBSAMPLE);
$display("C_X_SUBSAMPLE = %d", C_X_SUBSAMPLE);
$display("C_Y_SUBSAMPLE = %d", C_Y_SUBSAMPLE);
end
`endif
jfif_parser
#(
.SOS_CNT_W(SOS_CNT_W)
)
inst_jfif_parser
(
.i_arst (i_arst),
.i_sysclk (i_sysclk),
`ifdef DBG_MODE
.o_sos_status (o_sos_status),
`endif
.i_byte_en (i_byte_en),
.i_byte (i_byte),
.o_jfif_ready (o_jfif_ready),
.o_jfif_eoi (o_jfif_eoi),
.i_sos_re (w_ed_ready),
.o_sos_start (w_start),
.o_sos_width (o_width),
.o_sos_height (o_height),
.o_sos_scan_en (w_scan_en),
.o_sos_ecs_bit (w_ecs_bit)
);
entropy_decoder
#(
.AMPLITUDE_PRECISION (AMPLITUDE_PRECISION),
.MCU_SIZE (MCU_HEIGHT*MCU_WIDTH),
.YUV_COMPRESSION (C_Y_SUBSAMPLE*C_X_SUBSAMPLE),
.DHT_BST_MIF (DHT_BST_MIF),
.Y_DC_CW_MIF (Y_DC_CW_MIF),
.Y_AC_CW_MIF (Y_AC_CW_MIF),
.Y_S1_MIF (Y_S1_MIF),
.C_DC_CW_MIF (C_DC_CW_MIF),
.C_AC_CW_MIF (C_AC_CW_MIF),
.C_S1_MIF (C_S1_MIF)
)
inst_entropy_decoder
(
.i_arst (i_arst),
.i_srst (w_start),
.i_sysclk (i_sysclk),
`ifdef DBG_MODE
.o_scan_state (o_scan_state),
`endif
.i_scan_en (w_scan_en),
.i_ecs_bit (w_ecs_bit),
.i_Y_dq_ready (w_Y_dq_ready),
.i_U_dq_ready (w_U_dq_ready),
.i_V_dq_ready (w_V_dq_ready),
.o_ed_ready (w_ed_ready),
.o_Y_de (w_Y_de),
.o_U_de (w_U_de),
.o_V_de (w_V_de),
.o_Y_B (w_Y_B),
.o_U_B (w_U_B),
.o_V_B (w_V_B)
);
assign w_Y_dq_ready = ~w_Y_mx_full;
assign w_U_dq_ready = ~w_U_mx_full;
assign w_V_dq_ready = ~w_V_mx_full;
zigzag_to_matrix
#(
`ifdef RTL_SIM
.REF_MTX_FILE (REF_MTX_Y),
`endif
.DATA_W (AMPLITUDE_PRECISION),
.MCU_WIDTH (MCU_WIDTH),
.MCU_HEIGHT (MCU_HEIGHT),
.NUM_MATRIX (NUM_MATRIX_Y),
.PX_OUT (PX_OUT),
.PY_OUT (PY_OUT),
.MATRIX_TYPE ("RAM")
)
inst_zigzag_to_matrix_Y
(
.i_arst (i_arst),
.i_srst (i_arst),
.i_sysclk (i_sysclk),
.i_we (w_Y_de),
.i_data (w_Y_B),
.o_full (w_Y_mx_full),
`ifdef RTL_SIM
.o_sim_wr_mcu (o_sim_Y_wr_mcu),
`endif
.i_re (w_Y_mx_re),
.o_nempty (w_Y_mx_nempty),
.o_md (w_Y_mx_md)
);
zigzag_to_matrix
#(
`ifdef RTL_SIM
.REF_MTX_FILE (REF_MTX_U),
`endif
.DATA_W (AMPLITUDE_PRECISION),
.MCU_WIDTH (MCU_WIDTH),
.MCU_HEIGHT (MCU_HEIGHT),
.NUM_MATRIX (NUM_MATRIX_U),
.PX_OUT (PX_OUT),
.PY_OUT (PY_OUT),
.MATRIX_TYPE ("RAM")
)
inst_zigzag_to_matrix_U
(
.i_arst (i_arst),
.i_srst (i_arst),
.i_sysclk (i_sysclk),
.i_we (w_U_de),
.i_data (w_U_B),
.o_full (w_U_mx_full),
`ifdef RTL_SIM
.o_sim_wr_mcu (o_sim_U_wr_mcu),
`endif
.i_re (w_U_mx_re),
.o_nempty (w_U_mx_nempty),
.o_md (w_U_mx_md)
);
zigzag_to_matrix
#(
`ifdef RTL_SIM
.REF_MTX_FILE (REF_MTX_V),
`endif
.DATA_W (AMPLITUDE_PRECISION),
.MCU_WIDTH (MCU_WIDTH),
.MCU_HEIGHT (MCU_HEIGHT),
.NUM_MATRIX (NUM_MATRIX_V),
.PX_OUT (PX_OUT),
.PY_OUT (PY_OUT),
.MATRIX_TYPE ("RAM")
)
inst_zigzag_to_matrix_V
(
.i_arst (i_arst),
.i_srst (i_arst),
.i_sysclk (i_sysclk),
.i_we (w_V_de),
.i_data (w_V_B),
.o_full (w_V_mx_full),
`ifdef RTL_SIM
.o_sim_wr_mcu (o_sim_V_wr_mcu),
`endif
.i_re (w_V_mx_re),
.o_nempty (w_V_mx_nempty),
.o_md (w_V_mx_md)
);
dq_idct
#(
.NUM_ACCUMULATOR (NUM_ACCUMULATOR),
.NUM_CHANNEL (NUM_CHANNEL),
.AMPLITUDE_PRECISION (AMPLITUDE_PRECISION),
.COLOR_PRECISION (COLOR_PRECISION),
.ZIGZAG_MULTIPLEX (ZIGZAG_MULTIPLEX),
.YUV_COMPRESSION (C_Y_SUBSAMPLE*C_X_SUBSAMPLE),
.DQT_PRECISION (DQT_PRECISION),
.DQT_BRAM_OUTPUT_REG (DQT_BRAM_OUTPUT_REG),
.DQT_MIF (DQT_MIF),
.DQT_MULT_LATENCY (DQT_MULT_LATENCY),
.DCT_PRECISION (DCT_PRECISION),
.DCT_MULT_LATENCY (DCT_MULT_LATENCY),
.ACCU_MULT_LATENCY (ACCU_MULT_LATENCY)
)
inst_dq_idct
(
.i_arst (i_arst),
.i_sysclk (i_sysclk),
.i_Y_de (w_Y_mx_nempty),
// .i_Y_de (w_Y_mx_full),
.i_U_de (w_U_mx_nempty),
.i_V_de (w_V_mx_nempty),
.i_Y_B (w_Y_mx_md),
.i_U_B (w_U_mx_md),
.i_V_B (w_V_mx_md),
.o_Y_re (w_Y_mx_re),
.o_U_re (w_U_mx_re),
.o_V_re (w_V_mx_re),
.i_Y_lb_full (w_Y_lb_full),
.i_U_lb_full (w_U_lb_full),
.i_V_lb_full (w_V_lb_full),
.o_Y_lb_we (w_Y_lb_we),
.o_U_lb_we (w_U_lb_we),
.o_V_lb_we (w_V_lb_we),
.o_Y_lb (w_Y_lb),
.o_U_lb (w_U_lb),
.o_V_lb (w_V_lb)
);
assign w_Y_lb_full = i_Y_lb_full;
assign w_U_lb_full = i_U_lb_full;
assign w_V_lb_full = i_V_lb_full;
assign o_Y_lb_we = w_Y_lb_we;
assign o_U_lb_we = w_U_lb_we;
assign o_V_lb_we = w_V_lb_we;
assign o_Y_lb = w_Y_lb;
assign o_U_lb = w_U_lb;
assign o_V_lb = w_V_lb;
endmodule |
module runlength_shifter
#(
parameter AMPLITUDE_PRECISION = 16,
parameter MCU_SIZE = 64
)
(
input i_arst,
input i_sysclk,
input i_we,
input i_eob,
input [3:0]i_runlength,
input [AMPLITUDE_PRECISION-1:0]i_B,
output o_ready,
output [5:0]o_run_cnt,
input i_ready,
output o_de,
output [AMPLITUDE_PRECISION-1:0]o_B
);
localparam s_idle = 2'b00;
localparam s_flush = 2'b01;
localparam s_run_zero = 2'b10;
localparam s_run_eob = 2'b11;
wire [6:0]w_mcu_size;
reg [1:0]r_shift_state_1P;
reg r_ready_1P;
reg [4:0]r_len_cnt_1P;
reg [6:0]r_run_cnt_1P;
reg r_de_1P;
reg [AMPLITUDE_PRECISION-1:0]r_B_1P;
reg r_we_hold_1P;
reg r_eob_hold_1P;
reg [3:0]r_runlength_hold_1P;
reg [AMPLITUDE_PRECISION-1:0]r_B_hold_1P;
assign w_mcu_size = MCU_SIZE;
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_shift_state_1P <= s_idle;
r_ready_1P <= 1'b1;
r_len_cnt_1P <= {5{1'b0}};
r_run_cnt_1P <= {7{1'b0}};
r_de_1P <= 1'b0;
r_B_1P <= {AMPLITUDE_PRECISION{1'b0}};
r_runlength_hold_1P <= {4{1'b0}};
r_B_hold_1P <= {AMPLITUDE_PRECISION{1'b0}};
end
else
begin
case (r_shift_state_1P)
s_idle:
begin
if (i_ready)
begin
r_ready_1P <= 1'b1;
r_de_1P <= 1'b0;
if (i_eob)
begin
r_shift_state_1P <= s_run_eob;
r_ready_1P <= 1'b0;
r_de_1P <= 1'b1;
r_B_1P <= {AMPLITUDE_PRECISION{1'b0}};
r_run_cnt_1P <= r_run_cnt_1P+1'b1;
// if ((r_run_cnt_1P == {7{1'b0}}))
// begin
// r_shift_state_1P <= s_idle;
// r_ready_1P <= 1'b1;
// r_run_cnt_1P <= {7{1'b0}};
// end
// else if (r_run_cnt_1P == {1'b1, {6{1'b0}}})
// else if (r_run_cnt_1P == w_mcu_size)
if (r_run_cnt_1P == w_mcu_size)
begin
r_shift_state_1P <= s_idle;
r_ready_1P <= 1'b1;
// r_run_cnt_1P <= {7{1'b0}};
r_run_cnt_1P <= {7{1'b0}}+1'b1;
end
end
else if (i_we)
begin
if (i_runlength != 4'd0)
begin
r_shift_state_1P <= s_run_zero;
r_ready_1P <= 1'b0;
r_len_cnt_1P <= i_runlength;
r_run_cnt_1P <= r_run_cnt_1P+1'b1;
r_de_1P <= 1'b1;
r_B_1P <= {AMPLITUDE_PRECISION{1'b0}};
r_B_hold_1P <= i_B;
end
else
begin
r_run_cnt_1P <= r_run_cnt_1P+1'b1;
r_de_1P <= 1'b1;
if (r_run_cnt_1P == w_mcu_size)
// r_run_cnt_1P <= {7{1'b0}};
r_run_cnt_1P <= {7{1'b0}}+1'b1;
r_B_1P <= i_B;
end
end
end
else
begin
// TODO
if (i_we | i_eob)
begin
r_shift_state_1P <= s_flush;
r_ready_1P <= 1'b0;
r_we_hold_1P <= i_we;
r_eob_hold_1P <= i_eob;
r_runlength_hold_1P <= i_runlength;
r_B_hold_1P <= i_B;
end
/* else
begin
r_ready_1P <= 1'b0;
end*/
end
end
s_flush:
begin
if (i_ready)
begin
if (r_eob_hold_1P)
begin
r_shift_state_1P <= s_run_eob;
r_ready_1P <= 1'b0;
r_de_1P <= 1'b1;
r_B_1P <= {AMPLITUDE_PRECISION{1'b0}};
r_run_cnt_1P <= r_run_cnt_1P+1'b1;
// if (r_run_cnt_1P == {7{1'b0}})
// begin
// r_shift_state_1P <= s_idle;
// r_ready_1P <= 1'b1;
// r_run_cnt_1P <= {7{1'b0}};
// end
// else if (r_run_cnt_1P == {1'b1, {6{1'b0}}})
// else if (r_run_cnt_1P == w_mcu_size)
if (r_run_cnt_1P == w_mcu_size)
begin
r_shift_state_1P <= s_idle;
r_ready_1P <= 1'b1;
// r_run_cnt_1P <= {7{1'b0}};
r_run_cnt_1P <= {7{1'b0}}+1'b1;
end
end
else if (r_we_hold_1P)
begin
if (r_runlength_hold_1P != 5'd0)
begin
r_shift_state_1P <= s_run_zero;
r_ready_1P <= 1'b0;
r_len_cnt_1P <= r_runlength_hold_1P;
r_run_cnt_1P <= r_run_cnt_1P+1'b1;
r_de_1P <= 1'b1;
r_B_1P <= {AMPLITUDE_PRECISION{1'b0}};
r_B_hold_1P <= r_B_hold_1P;
end
else
begin
r_shift_state_1P <= s_idle;
r_ready_1P <= 1'b1;
r_run_cnt_1P <= r_run_cnt_1P+1'b1;
r_de_1P <= 1'b1;
if (r_run_cnt_1P == w_mcu_size)
// r_run_cnt_1P <= {7{1'b0}};
r_run_cnt_1P <= {7{1'b0}}+1'b1;
r_B_1P <= r_B_hold_1P;
end
end
end
end
s_run_zero:
begin
if (i_ready)
begin
r_de_1P <= 1'b1;
r_B_1P <= {AMPLITUDE_PRECISION{1'b0}};
r_len_cnt_1P <= r_len_cnt_1P-1'b1;
r_run_cnt_1P <= r_run_cnt_1P+1'b1;
if (r_len_cnt_1P == 5'd1)
begin
r_shift_state_1P <= s_idle;
r_ready_1P <= 1'b1;
r_B_1P <= r_B_hold_1P;
end
end
end
s_run_eob:
begin
if (i_ready)
begin
r_de_1P <= 1'b1;
r_B_1P <= {AMPLITUDE_PRECISION{1'b0}};
r_run_cnt_1P <= r_run_cnt_1P+1'b1;
// if ((r_run_cnt_1P == {7{1'b0}}))
// begin
// r_shift_state_1P <= s_idle;
// r_ready_1P <= 1'b1;
// r_de_1P <= 1'b0;
//// r_run_cnt_1P <= {7{1'b0}};
// end
// else if ((r_run_cnt_1P == w_mcu_size)
if (r_run_cnt_1P == w_mcu_size)
begin
r_shift_state_1P <= s_idle;
r_ready_1P <= 1'b1;
r_de_1P <= 1'b0;
r_run_cnt_1P <= {7{1'b0}};
// r_run_cnt_1P <= {7{1'b0}}+1'b1;
end
end
end
default:
begin
r_shift_state_1P <= s_idle;
r_ready_1P <= 1'b1;
r_len_cnt_1P <= {5{1'b0}};
r_run_cnt_1P <= {7{1'b0}};
r_de_1P <= 1'b0;
r_B_1P <= {AMPLITUDE_PRECISION{1'b0}};
r_runlength_hold_1P <= {4{1'b0}};
r_B_hold_1P <= {AMPLITUDE_PRECISION{1'b0}};
end
endcase
end
end
assign o_ready = r_ready_1P;
assign o_de = r_de_1P;
assign o_run_cnt = r_run_cnt_1P[5:0];
assign o_B = r_B_1P;
endmodule |
module zigzag_to_matrix
#(
`ifdef RTL_SIM
parameter DQT_00 = 1,
parameter DQT_01 = 1,
parameter DQT_02 = 1,
parameter DQT_03 = 1,
parameter DQT_04 = 1,
parameter DQT_05 = 1,
parameter DQT_06 = 1,
parameter DQT_07 = 1,
parameter DQT_10 = 1,
parameter DQT_11 = 1,
parameter DQT_12 = 1,
parameter DQT_13 = 1,
parameter DQT_14 = 1,
parameter DQT_15 = 1,
parameter DQT_16 = 1,
parameter DQT_17 = 1,
parameter DQT_20 = 1,
parameter DQT_21 = 1,
parameter DQT_22 = 1,
parameter DQT_23 = 1,
parameter DQT_24 = 1,
parameter DQT_25 = 1,
parameter DQT_26 = 1,
parameter DQT_27 = 1,
parameter DQT_30 = 1,
parameter DQT_31 = 1,
parameter DQT_32 = 1,
parameter DQT_33 = 1,
parameter DQT_34 = 1,
parameter DQT_35 = 1,
parameter DQT_36 = 1,
parameter DQT_37 = 1,
parameter DQT_40 = 1,
parameter DQT_41 = 1,
parameter DQT_42 = 1,
parameter DQT_43 = 1,
parameter DQT_44 = 1,
parameter DQT_45 = 1,
parameter DQT_46 = 1,
parameter DQT_47 = 1,
parameter DQT_50 = 1,
parameter DQT_51 = 1,
parameter DQT_52 = 1,
parameter DQT_53 = 1,
parameter DQT_54 = 1,
parameter DQT_55 = 1,
parameter DQT_56 = 1,
parameter DQT_57 = 1,
parameter DQT_60 = 1,
parameter DQT_61 = 1,
parameter DQT_62 = 1,
parameter DQT_63 = 1,
parameter DQT_64 = 1,
parameter DQT_65 = 1,
parameter DQT_66 = 1,
parameter DQT_67 = 1,
parameter DQT_70 = 1,
parameter DQT_71 = 1,
parameter DQT_72 = 1,
parameter DQT_73 = 1,
parameter DQT_74 = 1,
parameter DQT_75 = 1,
parameter DQT_76 = 1,
parameter DQT_77 = 1,
parameter REF_MTX_FILE= "ref_mtx_file.txt",
`endif
parameter DATA_W = 16,
parameter MCU_WIDTH = 8,
parameter MCU_HEIGHT = 8,
parameter NUM_MATRIX = 4,
parameter PX_OUT = 1,
parameter PY_OUT = 1,
// parameter MATRIX_TYPE = "REG" // REG/RAM
parameter MATRIX_TYPE = "RAM" // REG/RAM
)
(
input i_arst,
input i_srst,
input i_sysclk,
input i_we,
input [DATA_W-1:0]i_data,
output o_full,
`ifdef RTL_SIM
output [15:0]o_sim_wr_mcu,
`endif
input i_re,
output o_nempty,
output [PY_OUT*PX_OUT*DATA_W-1:0]o_md
);
function integer log2;
input integer val;
integer i;
begin
log2 = 0;
for (i=0; 2**i<val; i=i+1)
log2 = i+1;
end
endfunction
`ifdef RTL_SIM
genvar k;
`endif
generate
if (MATRIX_TYPE == "REG")
begin
integer a, b, c, d, e, f, g, h, i, j, k, l, m, n, z;
reg [MCU_WIDTH*DATA_W-1:0]r_matrix_1P[0:MCU_HEIGHT-1];
/*
0,0 <= 0,1 | 0,2 <= 0,3 | 0,4 <= 0,5 | 0,6 <= 0,7
7,0 <= 7,1 | 7,2 <= 7,3 | 7,4 <= 7,5 | 7,6 <= 7,7
----------------------------------------------+---------------------------------+-----------------------------------------------+------------------------------------------------------
0,1 <= 1,0 | 0,3 <= 1,2 <= 2,1 <= 3,0 | 0,5 <= 1,4 <= 2,3 <= 3,2 <= 4,1 <= 5,0 | 0,7 <= 1,6 <= 2,5 <= 3,4 <= 4,3 <= 5,2 <= 6,1 <= 7,0
2,7 <= 3,6 <= 4,5 <= 5,4 <= 6,3 <= 7,2 | 4,7 <= 5,6 <= 6,5 <= 7,4 | 6,7 <= 7,6 |
----------------------------------------------+---------------------------------+-----------------------------------------------+------------------------------------------------------
1,0 <= 2,0 | 3,0 <= 4,0 | 5,0 <= 6,0 |
1,7 <= 2,7 | 3,7 <= 4,7 | 5,7 <= 6,7 |
----------------------------------------------+---------------------------------+-----------------------------------------------+
2,0 <= 1,1 <= 0,2 | 4,0 <= 3,1 <= 2,2 <= 1,3 <= 4,0 | 6,0 <= 5,1 <= 4,2 <= 3,3 <= 2,4 <= 1,5 <= 0,6 |
7,1 <= 6,2 <= 5,3 <= 4,4 <= 3,5 <= 2,6 <= 1,7 | 7,3 <= 6,4 <= 5,5 <= 4,6 <= 3,7 | 7,5 <= 6,6 <= 5,7 |
*/
always@(posedge i_sysclk)
begin
if (i_srst)
begin
for (z=0; z<MCU_HEIGHT; z=z+1)
begin
r_matrix_1P[z] <= {MCU_WIDTH*DATA_W{1'b0}};
end
end
else
begin
if (i_we)
begin
r_matrix_1P[MCU_HEIGHT-1][(MCU_WIDTH-1)*DATA_W+:DATA_W] <= i_data;
for (b=0; b<MCU_HEIGHT; b=b+MCU_HEIGHT-1)
begin
for (a=0; a<MCU_WIDTH; a=a+2)
begin
r_matrix_1P[b][a*DATA_W+:DATA_W] <= r_matrix_1P[b][(a+1)*DATA_W+:DATA_W];
end
end
for (c=1; c<MCU_WIDTH; c=c+2)
begin
for (d=c; d>0; d=d-1)
begin
r_matrix_1P[c-d][d*DATA_W+:DATA_W] <= r_matrix_1P[c-d+1][(d-1)*DATA_W+:DATA_W];
end
end
for (e=2; e<MCU_HEIGHT; e=e+2)
begin
for (f=0; f<MCU_WIDTH-e-1; f=f+1)
begin
r_matrix_1P[e+f][(MCU_WIDTH-1-f)*DATA_W+:DATA_W] <= r_matrix_1P[e+f+1][(MCU_WIDTH-1-f-1)*DATA_W+:DATA_W];
end
end
for (h=1; h<MCU_HEIGHT-2; h=h+2)
begin
for (g=0; g<MCU_WIDTH; g=g+MCU_WIDTH-1)
begin
r_matrix_1P[h][g*DATA_W+:DATA_W] <= r_matrix_1P[h+1][g*DATA_W+:DATA_W];
end
end
for (i=2; i<MCU_HEIGHT; i=i+2)
begin
for (j=i; j>0; j=j-1)
begin
r_matrix_1P[i-j+1][(j-1)*DATA_W+:DATA_W] <= r_matrix_1P[i-j][j*DATA_W+:DATA_W];
end
end
for (k=1; k<MCU_WIDTH-1; k=k+2)
begin
for (l=0; l<MCU_HEIGHT-k-1; l=l+1)
begin
r_matrix_1P[MCU_HEIGHT-1-l][(k+l)*DATA_W+:DATA_W] <= r_matrix_1P[MCU_HEIGHT-1-l-1][(k+l+1)*DATA_W+:DATA_W];
end
end
end
else if (i_re)
begin
for (n=0; n<MCU_HEIGHT; n=n+1)
begin
r_matrix_1P[n][(MCU_WIDTH-1)*DATA_W+:DATA_W] <= r_matrix_1P[(n+1)%MCU_HEIGHT][0*DATA_W+:DATA_W];
for (m=0; m<MCU_WIDTH-1; m=m+1)
begin
r_matrix_1P[n][m*DATA_W+:DATA_W] <= r_matrix_1P[n][(m+1)*DATA_W+:DATA_W];
end
end
end
end
end
genvar x, y;
for (y=0; y<PY_OUT; y=y+1)
begin
for (x=0; x<PX_OUT; x=y+1)
begin
assign o_md[(y*MCU_WIDTH*DATA_W)+x*DATA_W+:DATA_W] = r_matrix_1P[y][x*DATA_W+:DATA_W];
end
end
`ifdef RTL_SIM
wire [DATA_W-1:0]w_row_0[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_row_1[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_row_2[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_row_3[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_row_4[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_row_5[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_row_6[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_row_7[0:MCU_WIDTH-1];
assign w_row_0[0] = r_matrix_1P[0][0*DATA_W+:DATA_W] * DQT_00;
assign w_row_0[1] = r_matrix_1P[0][1*DATA_W+:DATA_W] * DQT_01;
assign w_row_0[2] = r_matrix_1P[0][2*DATA_W+:DATA_W] * DQT_02;
assign w_row_0[3] = r_matrix_1P[0][3*DATA_W+:DATA_W] * DQT_03;
assign w_row_0[4] = r_matrix_1P[0][4*DATA_W+:DATA_W] * DQT_04;
assign w_row_0[5] = r_matrix_1P[0][5*DATA_W+:DATA_W] * DQT_05;
assign w_row_0[6] = r_matrix_1P[0][6*DATA_W+:DATA_W] * DQT_06;
assign w_row_0[7] = r_matrix_1P[0][7*DATA_W+:DATA_W] * DQT_07;
assign w_row_1[0] = r_matrix_1P[1][0*DATA_W+:DATA_W] * DQT_10;
assign w_row_1[1] = r_matrix_1P[1][1*DATA_W+:DATA_W] * DQT_11;
assign w_row_1[2] = r_matrix_1P[1][2*DATA_W+:DATA_W] * DQT_12;
assign w_row_1[3] = r_matrix_1P[1][3*DATA_W+:DATA_W] * DQT_13;
assign w_row_1[4] = r_matrix_1P[1][4*DATA_W+:DATA_W] * DQT_14;
assign w_row_1[5] = r_matrix_1P[1][5*DATA_W+:DATA_W] * DQT_15;
assign w_row_1[6] = r_matrix_1P[1][6*DATA_W+:DATA_W] * DQT_16;
assign w_row_1[7] = r_matrix_1P[1][7*DATA_W+:DATA_W] * DQT_17;
assign w_row_2[0] = r_matrix_1P[2][0*DATA_W+:DATA_W] * DQT_20;
assign w_row_2[1] = r_matrix_1P[2][1*DATA_W+:DATA_W] * DQT_21;
assign w_row_2[2] = r_matrix_1P[2][2*DATA_W+:DATA_W] * DQT_22;
assign w_row_2[3] = r_matrix_1P[2][3*DATA_W+:DATA_W] * DQT_23;
assign w_row_2[4] = r_matrix_1P[2][4*DATA_W+:DATA_W] * DQT_24;
assign w_row_2[5] = r_matrix_1P[2][5*DATA_W+:DATA_W] * DQT_25;
assign w_row_2[6] = r_matrix_1P[2][6*DATA_W+:DATA_W] * DQT_26;
assign w_row_2[7] = r_matrix_1P[2][7*DATA_W+:DATA_W] * DQT_27;
assign w_row_3[0] = r_matrix_1P[3][0*DATA_W+:DATA_W] * DQT_30;
assign w_row_3[1] = r_matrix_1P[3][1*DATA_W+:DATA_W] * DQT_31;
assign w_row_3[2] = r_matrix_1P[3][2*DATA_W+:DATA_W] * DQT_32;
assign w_row_3[3] = r_matrix_1P[3][3*DATA_W+:DATA_W] * DQT_33;
assign w_row_3[4] = r_matrix_1P[3][4*DATA_W+:DATA_W] * DQT_34;
assign w_row_3[5] = r_matrix_1P[3][5*DATA_W+:DATA_W] * DQT_35;
assign w_row_3[6] = r_matrix_1P[3][6*DATA_W+:DATA_W] * DQT_36;
assign w_row_3[7] = r_matrix_1P[3][7*DATA_W+:DATA_W] * DQT_37;
assign w_row_4[0] = r_matrix_1P[4][0*DATA_W+:DATA_W] * DQT_40;
assign w_row_4[1] = r_matrix_1P[4][1*DATA_W+:DATA_W] * DQT_41;
assign w_row_4[2] = r_matrix_1P[4][2*DATA_W+:DATA_W] * DQT_42;
assign w_row_4[3] = r_matrix_1P[4][3*DATA_W+:DATA_W] * DQT_43;
assign w_row_4[4] = r_matrix_1P[4][4*DATA_W+:DATA_W] * DQT_44;
assign w_row_4[5] = r_matrix_1P[4][5*DATA_W+:DATA_W] * DQT_45;
assign w_row_4[6] = r_matrix_1P[4][6*DATA_W+:DATA_W] * DQT_46;
assign w_row_4[7] = r_matrix_1P[4][7*DATA_W+:DATA_W] * DQT_47;
assign w_row_5[0] = r_matrix_1P[5][0*DATA_W+:DATA_W] * DQT_50;
assign w_row_5[1] = r_matrix_1P[5][1*DATA_W+:DATA_W] * DQT_51;
assign w_row_5[2] = r_matrix_1P[5][2*DATA_W+:DATA_W] * DQT_52;
assign w_row_5[3] = r_matrix_1P[5][3*DATA_W+:DATA_W] * DQT_53;
assign w_row_5[4] = r_matrix_1P[5][4*DATA_W+:DATA_W] * DQT_54;
assign w_row_5[5] = r_matrix_1P[5][5*DATA_W+:DATA_W] * DQT_55;
assign w_row_5[6] = r_matrix_1P[5][6*DATA_W+:DATA_W] * DQT_56;
assign w_row_5[7] = r_matrix_1P[5][7*DATA_W+:DATA_W] * DQT_57;
assign w_row_6[0] = r_matrix_1P[6][0*DATA_W+:DATA_W] * DQT_60;
assign w_row_6[1] = r_matrix_1P[6][1*DATA_W+:DATA_W] * DQT_61;
assign w_row_6[2] = r_matrix_1P[6][2*DATA_W+:DATA_W] * DQT_62;
assign w_row_6[3] = r_matrix_1P[6][3*DATA_W+:DATA_W] * DQT_63;
assign w_row_6[4] = r_matrix_1P[6][4*DATA_W+:DATA_W] * DQT_64;
assign w_row_6[5] = r_matrix_1P[6][5*DATA_W+:DATA_W] * DQT_65;
assign w_row_6[6] = r_matrix_1P[6][6*DATA_W+:DATA_W] * DQT_66;
assign w_row_6[7] = r_matrix_1P[6][7*DATA_W+:DATA_W] * DQT_67;
assign w_row_7[0] = r_matrix_1P[7][0*DATA_W+:DATA_W] * DQT_70;
assign w_row_7[1] = r_matrix_1P[7][1*DATA_W+:DATA_W] * DQT_71;
assign w_row_7[2] = r_matrix_1P[7][2*DATA_W+:DATA_W] * DQT_72;
assign w_row_7[3] = r_matrix_1P[7][3*DATA_W+:DATA_W] * DQT_73;
assign w_row_7[4] = r_matrix_1P[7][4*DATA_W+:DATA_W] * DQT_74;
assign w_row_7[5] = r_matrix_1P[7][5*DATA_W+:DATA_W] * DQT_75;
assign w_row_7[6] = r_matrix_1P[7][6*DATA_W+:DATA_W] * DQT_76;
assign w_row_7[7] = r_matrix_1P[7][7*DATA_W+:DATA_W] * DQT_77;
`endif
end
else
begin
localparam s_east = 2'b00;
localparam s_south = 2'b01;
localparam s_southwest = 2'b10;
localparam s_northeast = 2'b11;
localparam top = 0;
localparam bottom = MCU_HEIGHT-1;
localparam left = 0;
localparam right = MCU_WIDTH-1;
localparam ADDR_WIDTH = log2(NUM_MATRIX*MCU_HEIGHT*MCU_WIDTH);
wire [2:0]c_top;
wire [2:0]c_bottom;
wire [2:0]c_left;
wire [2:0]c_right;
assign c_top = top;
assign c_bottom= bottom;
assign c_left = left;
assign c_right = right;
reg [1:0]r_zigzag_state_1P;
reg [log2(MCU_WIDTH)-1:0]r_wr_x_1P;
reg [log2(MCU_HEIGHT)-1:0]r_wr_y_1P;
reg [log2(NUM_MATRIX)-1:0]r_wr_ptr_1P;
reg r_full_1P;
reg [log2(MCU_HEIGHT*MCU_WIDTH)-1:0]r_rd_addr_1P;
reg [log2(MCU_HEIGHT*MCU_WIDTH)-1:0]r_rd_iteration_1P;
reg [log2(NUM_MATRIX)-1:0]r_rd_ptr_1P;
reg r_nempty_1P;
`ifdef RTL_SIM
reg [log2(MCU_HEIGHT*MCU_WIDTH)-1:0]r_wr_cnt_1P;
reg [15:0]r_wr_mcu_1P;
`endif
wire [log2(MCU_HEIGHT*MCU_WIDTH)-1:0]w_rd_addr_1P;
wire [log2(NUM_MATRIX)-1:0]w_rd_ptr_1P;
simple_dual_port_ram
#(
.DATA_WIDTH (DATA_W),
.ADDR_WIDTH (ADDR_WIDTH),
.OUTPUT_REG ("FALSE"),
.RAM_INIT_FILE (""),
.RAM_INIT_RADIX ("HEX")
)
inst_simple_dual_port_ram
(
.wdata (i_data),
.waddr ({r_wr_ptr_1P, r_wr_y_1P, r_wr_x_1P}),
.raddr ({w_rd_ptr_1P, w_rd_addr_1P}),
.we (i_we),
.wclk (i_sysclk),
.re (1'b1),
.rclk (i_sysclk),
.rdata (o_md)
);
assign o_full = r_full_1P;
assign o_nempty = r_nempty_1P;
assign w_rd_ptr_1P = (i_re && r_rd_addr_1P == {6{1'b1}} && r_rd_iteration_1P == {6{1'b1}})?
r_rd_ptr_1P+1'b1:
r_rd_ptr_1P;
assign w_rd_addr_1P = (i_re)?
r_rd_addr_1P+1'b1:
r_rd_addr_1P;
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_zigzag_state_1P <= s_east;
r_wr_x_1P <= {log2(MCU_WIDTH){1'b0}};
r_wr_y_1P <= {log2(MCU_HEIGHT){1'b0}};
r_wr_ptr_1P <= {log2(NUM_MATRIX){1'b0}};
r_full_1P <= 1'b0;
r_rd_addr_1P <= {log2(MCU_HEIGHT*MCU_WIDTH){1'b0}};
r_rd_iteration_1P <= {log2(MCU_HEIGHT*MCU_WIDTH){1'b0}};
r_rd_ptr_1P <= {log2(NUM_MATRIX){1'b0}};
r_nempty_1P <= 1'b0;
`ifdef RTL_SIM
r_wr_cnt_1P <= {log2(MCU_HEIGHT*MCU_WIDTH){1'b0}};
r_wr_mcu_1P <= {16{1'b0}};
`endif
end
else
begin
if (i_we & ~r_full_1P)
begin
`ifdef RTL_SIM
r_wr_cnt_1P <= r_wr_cnt_1P+1'b1;
`endif
case (r_zigzag_state_1P)
s_east:
begin
r_wr_x_1P <= r_wr_x_1P+1'b1;
if (r_wr_y_1P == bottom)
r_zigzag_state_1P <= s_northeast;
else
r_zigzag_state_1P <= s_southwest;
end
s_south:
begin
r_wr_y_1P <= r_wr_y_1P+1'b1;
if (r_wr_x_1P == right)
r_zigzag_state_1P <= s_southwest;
else
r_zigzag_state_1P <= s_northeast;
end
s_southwest:
begin
r_wr_x_1P <= r_wr_x_1P-1'b1;
r_wr_y_1P <= r_wr_y_1P+1'b1;
if (r_wr_y_1P == bottom-1'b1)
r_zigzag_state_1P <= s_east;
else if (r_wr_x_1P == left+1'b1)
r_zigzag_state_1P <= s_south;
end
s_northeast:
begin
r_wr_x_1P <= r_wr_x_1P+1'b1;
r_wr_y_1P <= r_wr_y_1P-1'b1;
if (r_wr_y_1P == bottom && r_wr_x_1P == right)
begin
r_zigzag_state_1P <= s_east;
r_wr_x_1P <= {log2(MCU_WIDTH){1'b0}};
r_wr_y_1P <= {log2(MCU_HEIGHT){1'b0}};
r_wr_ptr_1P <= r_wr_ptr_1P+1'b1;
if (r_wr_ptr_1P+1'b1 == r_rd_ptr_1P)
r_full_1P <= 1'b1;
r_nempty_1P <= 1'b1;
`ifdef RTL_SIM
r_wr_cnt_1P <= {log2(MCU_HEIGHT*MCU_WIDTH){1'b0}};
r_wr_mcu_1P <= r_wr_mcu_1P+1'b1;
`endif
end
else if (r_wr_x_1P == right-1'b1)
r_zigzag_state_1P <= s_south;
else if (r_wr_y_1P == top+1'b1)
r_zigzag_state_1P <= s_east;
end
default:
begin
end
endcase
end
if (i_re & r_nempty_1P)
begin
r_rd_addr_1P <= w_rd_addr_1P;
if (r_rd_addr_1P == {log2(MCU_HEIGHT*MCU_WIDTH){1'b1}})
begin
r_rd_iteration_1P <= r_rd_iteration_1P+1'b1;
if (r_rd_iteration_1P == {log2(MCU_HEIGHT*MCU_WIDTH){1'b1}})
begin
r_rd_ptr_1P <= w_rd_ptr_1P;
// r_full_1P <= 1'b0;
if (r_wr_ptr_1P == w_rd_ptr_1P)
begin
r_full_1P <= 1'b0;
r_nempty_1P <= 1'b0;
end
end
end
end
end
end
`ifdef RTL_SIM
integer ref_mtx_file, status;
integer m, h, j, l;
reg [DATA_W-1:0]r_ref_mtx[0:MCU_HEIGHT*MCU_WIDTH-1];
reg [DATA_W-1:0]r_dbg_mtx[0:MCU_HEIGHT*MCU_WIDTH-1];
reg [MCU_HEIGHT*MCU_WIDTH-1:0]r_err;
wire [DATA_W-1:0]w_ref_row_0[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_ref_row_1[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_ref_row_2[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_ref_row_3[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_ref_row_4[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_ref_row_5[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_ref_row_6[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_ref_row_7[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_dbg_row_0[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_dbg_row_1[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_dbg_row_2[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_dbg_row_3[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_dbg_row_4[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_dbg_row_5[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_dbg_row_6[0:MCU_WIDTH-1];
wire [DATA_W-1:0]w_dbg_row_7[0:MCU_WIDTH-1];
wire w_err;
initial
begin
for (h=0; h<MCU_HEIGHT*MCU_WIDTH; h=h+1)
begin
r_dbg_mtx[h] <= {DATA_W{1'b0}};
r_err[h] <= 1'b0;
end
m = 0;
$display("%s", REF_MTX_FILE);
ref_mtx_file = $fopen(REF_MTX_FILE, "r");
if (ref_mtx_file != 0)
begin
while (!$feof(ref_mtx_file))
begin
@(posedge i_sysclk)
begin
if (i_we & ~r_full_1P)
begin
status = $fscanf(ref_mtx_file, "%d", r_ref_mtx[m%(MCU_HEIGHT*MCU_WIDTH)]);
m = m+1;
end
end
end
end
end
always@(posedge i_sysclk)
begin
if (i_we & ~r_full_1P)
begin
r_dbg_mtx[MCU_HEIGHT*MCU_WIDTH-1] <= i_data;
for (j=0; j<MCU_HEIGHT*MCU_WIDTH-1; j=j+1)
begin
r_dbg_mtx[j] <= r_dbg_mtx[j+1];
end
end
if ({r_wr_y_1P, r_wr_x_1P} == {(log2(MCU_HEIGHT)+log2(MCU_WIDTH)){1'b0}})
begin
for (l=0; l<MCU_HEIGHT*MCU_WIDTH; l=l+1)
begin
r_err[l] <= r_dbg_mtx[l] != r_ref_mtx[l];
end
end
end
for (k=0; k<MCU_WIDTH; k=k+1)
begin
assign w_ref_row_0[k] = r_ref_mtx[MCU_HEIGHT*0+k];
assign w_ref_row_1[k] = r_ref_mtx[MCU_HEIGHT*1+k];
assign w_ref_row_2[k] = r_ref_mtx[MCU_HEIGHT*2+k];
assign w_ref_row_3[k] = r_ref_mtx[MCU_HEIGHT*3+k];
assign w_ref_row_4[k] = r_ref_mtx[MCU_HEIGHT*4+k];
assign w_ref_row_5[k] = r_ref_mtx[MCU_HEIGHT*5+k];
assign w_ref_row_6[k] = r_ref_mtx[MCU_HEIGHT*6+k];
assign w_ref_row_7[k] = r_ref_mtx[MCU_HEIGHT*7+k];
assign w_dbg_row_0[k] = r_dbg_mtx[MCU_HEIGHT*0+k];
assign w_dbg_row_1[k] = r_dbg_mtx[MCU_HEIGHT*1+k];
assign w_dbg_row_2[k] = r_dbg_mtx[MCU_HEIGHT*2+k];
assign w_dbg_row_3[k] = r_dbg_mtx[MCU_HEIGHT*3+k];
assign w_dbg_row_4[k] = r_dbg_mtx[MCU_HEIGHT*4+k];
assign w_dbg_row_5[k] = r_dbg_mtx[MCU_HEIGHT*5+k];
assign w_dbg_row_6[k] = r_dbg_mtx[MCU_HEIGHT*6+k];
assign w_dbg_row_7[k] = r_dbg_mtx[MCU_HEIGHT*7+k];
end
assign w_err = (r_err != {(MCU_HEIGHT*MCU_WIDTH){1'b0}});
assign o_sim_wr_mcu = r_wr_mcu_1P;
`endif
end
endgenerate
endmodule |
module sos_parser
#(
parameter CNT_W = 4
)
(
input i_arst,
input i_sysclk,
`ifdef DBG_MODE
output [1:0]o_scan_status,
`endif
input i_byte_en,
input [7:0]i_byte,
output o_ready,
output o_eoi,
input i_re,
output o_start,
output [15:0]o_width,
output [15:0]o_height,
output o_scan_en,
output o_ecs_bit
);
localparam c_MRK = 8'hFF;
localparam c_PAD = 8'h00;
localparam c_SOI = 8'hD8;
localparam c_SOF0 = 8'hC0; // Basline DCT
localparam c_DHT = 8'hC4;
localparam c_DQT = 8'hDB;
localparam c_DRI = 8'hDD;
localparam c_SOS = 8'hDA;
localparam c_RST = 5'b11010; //XXX
localparam c_APP = 4'hE; //X
localparam c_COM = 8'hFE;
localparam c_EOI = 8'hD9;
/*==============================
For YUV Sequential DCT Baseline
Ls 12
Ns 3
Csj
Tdj Don't care with fixed DHT DC
Taj Don't care with fixed DHT AC
Ss 0
Se 63
Ah 0
Al 0
==============================*/
localparam s_idle = 2'b00;
localparam s_scan_res = 2'b01;
localparam s_scan_header = 2'b10;
localparam s_scan_data = 2'b11;
reg r_marker_1P;
reg [7:0]r_sr_1P;
reg [1:0]r_scan_status_1P;
reg r_ready_1P;
reg [CNT_W-1:0]r_cnt_1P;
reg r_start_1P;
reg [15:0]r_width_1P;
reg [15:0]r_height_1P;
reg r_scan_en_1P;
reg r_eoi_1P;
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_marker_1P <= 1'b0;
r_sr_1P <= {8{1'b0}};
r_scan_status_1P <= s_idle;
r_ready_1P <= 1'b1;
r_cnt_1P <= {CNT_W{1'b0}};
r_start_1P <= 1'b0;
r_width_1P <= {16{1'b0}};
r_height_1P <= {16{1'b0}};
r_scan_en_1P <= 1'b0;
r_eoi_1P <= 1'b0;
end
else
begin
r_ready_1P <= 1'b1;
r_start_1P <= 1'b0;
r_eoi_1P <= 1'b0;
// if (i_byte == 8'hFF)
// if (i_byte_en && i_byte == c_MRK)
// r_marker_1P <= 1'b1;
// else
// r_marker_1P <= 1'b0;
//
// if (i_byte_en)
// r_sr_1P <= i_byte;
case (r_scan_status_1P)
s_idle:
begin
if (i_byte_en)
begin
if (i_byte == c_MRK)
r_marker_1P <= 1'b1;
else
r_marker_1P <= 1'b0;
r_sr_1P <= i_byte;
if (r_marker_1P)
begin
if (i_byte == c_SOF0)
begin
r_scan_status_1P <= s_scan_res;
end
else if (i_byte == c_SOS)
begin
r_scan_status_1P <= s_scan_header;
r_start_1P <= 1'b1;
end
end
end
end
s_scan_res:
begin
if (i_byte_en)
begin
r_sr_1P <= i_byte;
r_cnt_1P <= r_cnt_1P+1'b1;
if (r_cnt_1P == 4'd3)
r_height_1P[15:8] <= i_byte;
else if (r_cnt_1P == 4'd4)
r_height_1P[7:0] <= i_byte;
else if (r_cnt_1P == 4'd5)
r_width_1P[15:8] <= i_byte;
else if (r_cnt_1P == 4'd6)
begin
r_width_1P[7:0] <= i_byte;
r_scan_status_1P <= s_idle;
r_cnt_1P <= {CNT_W{1'b0}};
end
end
end
s_scan_header:
begin
if (i_byte_en)
begin
r_sr_1P <= i_byte;
r_cnt_1P <= r_cnt_1P+1'b1;
if (r_cnt_1P == 4'd12)
begin
r_scan_status_1P <= s_scan_data;
r_ready_1P <= 1'b0;
r_cnt_1P <= {CNT_W{1'b0}};
r_scan_en_1P <= 1'b1;
end
end
end
s_scan_data:
begin
r_ready_1P <= 1'b0;
r_scan_en_1P <= i_byte_en;
if (i_byte_en)
begin
if (i_byte == c_MRK)
begin
r_marker_1P <= 1'b1;
if (~r_ready_1P)
r_ready_1P <= 1'b1;
if (r_cnt_1P == 4'd7)
r_scan_en_1P <= 1'b0;
end
end
if (i_re & r_scan_en_1P)
begin
r_cnt_1P <= r_cnt_1P+1'b1;
r_sr_1P <= {r_sr_1P[6:0], 1'b0};
if (r_cnt_1P == 4'd7)
begin
r_ready_1P <= 1'b1;
r_cnt_1P <= {CNT_W{1'b0}};
r_sr_1P <= i_byte;
if (r_marker_1P)
begin
if (i_byte == c_PAD)
begin
r_marker_1P <= 1'b0;
r_sr_1P <= 8'hFF;
end
else if (i_byte == c_EOI)
begin
r_scan_status_1P <= s_idle;
r_scan_en_1P <= 1'b0;
r_ready_1P <= 1'b1;
r_eoi_1P <= 1'b1;
end
end
end
end
else
begin
r_sr_1P <= r_sr_1P;
end
end
default:
begin
r_marker_1P <= 1'b0;
r_sr_1P <= {8{1'b0}};
r_scan_status_1P <= s_idle;
r_ready_1P <= 1'b1;
r_cnt_1P <= {CNT_W{1'b0}};
r_start_1P <= 1'b0;
r_scan_en_1P <= 1'b0;
r_eoi_1P <= 1'b0;
end
endcase
end
end
assign o_ready = r_ready_1P;
assign o_eoi = r_eoi_1P;
assign o_start = r_start_1P;
assign o_width = r_width_1P;
assign o_height = r_height_1P;
assign o_scan_en = r_scan_en_1P;
assign o_ecs_bit = r_sr_1P[7];
`ifdef DBG_MODE
assign o_scan_status = r_scan_status_1P;
`endif
endmodule |
module accumulator
#(
parameter A_IN_PRECISION = 16,
parameter B_IN_PRECISION = 10,
parameter O_OUT_PRECISION = 8,
parameter MULT_LATENCY = 0
)
(
input i_arst,
input i_sysclk,
input i_en,
input i_load,
input [A_IN_PRECISION-1:0]i_a,
input [B_IN_PRECISION-1:0]i_b,
output o_en,
output [O_OUT_PRECISION:0]o_O
);
wire [A_IN_PRECISION+B_IN_PRECISION-1:0]w_mult_out;
reg r_en_1P;
reg [A_IN_PRECISION+B_IN_PRECISION-8-1:0]r_adder_1P;
mult_a_signed_b_signed
#(
.A_WIDTH(A_IN_PRECISION),
.B_WIDTH(B_IN_PRECISION),
.LATENCY(MULT_LATENCY)
)
inst_mult
(
.arst (i_arst),
.clk (i_sysclk),
.a (i_a),
.b (i_b),
.o (w_mult_out)
);
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_en_1P <= 1'b0;
r_adder_1P <= {A_IN_PRECISION+B_IN_PRECISION-8{1'b0}};
end
else
begin
r_en_1P <= i_en;
if (i_en)
begin
if (i_load)
r_adder_1P <= w_mult_out[A_IN_PRECISION+B_IN_PRECISION-1:8];
else
r_adder_1P <= r_adder_1P+w_mult_out[A_IN_PRECISION+B_IN_PRECISION-1:8];
end
end
end
assign o_en = r_en_1P;
assign o_O = r_adder_1P[O_OUT_PRECISION+2:2];
endmodule |
module dct
(
input [2:0]i_Gxy,
input [2:0]i_Buv,
output [8:0]o_dct
);
wire [8:0]w_dct[0:63];
wire [8:0]w_p9807, w_p9238, w_p8314, w_p7071, w_p5555, w_p3826, w_p1950;
wire [8:0]w_n9807, w_n9238, w_n8314, w_n7071, w_n5555, w_n3826, w_n1950;
assign w_p9807 = 9'd251;
assign w_p9238 = 9'd237;
assign w_p8314 = 9'd213;
assign w_p7071 = 9'd181;
assign w_p5555 = 9'd142;
assign w_p3826 = 9'd98;
assign w_p1950 = 9'd50;
assign w_n9807 = ~w_p9807+1'b1;
assign w_n9238 = ~w_p9238+1'b1;
assign w_n8314 = ~w_p8314+1'b1;
assign w_n7071 = ~w_p7071+1'b1;
assign w_n5555 = ~w_p5555+1'b1;
assign w_n3826 = ~w_p3826+1'b1;
assign w_n1950 = ~w_p1950+1'b1;
assign w_dct[0] = w_p7071;
assign w_dct[1] = w_p9807;
assign w_dct[2] = w_p9238;
assign w_dct[3] = w_p8314;
assign w_dct[4] = w_p7071;
assign w_dct[5] = w_p5555;
assign w_dct[6] = w_p3826;
assign w_dct[7] = w_p1950;
assign w_dct[8] = w_p7071;
assign w_dct[9] = w_p8314;
assign w_dct[10] = w_p3826;
assign w_dct[11] = w_n1950;
assign w_dct[12] = w_n7071;
assign w_dct[13] = w_n9807;
assign w_dct[14] = w_n9238;
assign w_dct[15] = w_n5555;
assign w_dct[16] = w_p7071;
assign w_dct[17] = w_p5555;
assign w_dct[18] = w_n3826;
assign w_dct[19] = w_n9807;
assign w_dct[20] = w_n7071;
assign w_dct[21] = w_p1950;
assign w_dct[22] = w_p9238;
assign w_dct[23] = w_p8314;
assign w_dct[24] = w_p7071;
assign w_dct[25] = w_p1950;
assign w_dct[26] = w_n9238;
assign w_dct[27] = w_n5555;
assign w_dct[28] = w_p7071;
assign w_dct[29] = w_p8314;
assign w_dct[30] = w_n3826;
assign w_dct[31] = w_n9807;
assign w_dct[32] = w_p7071;
assign w_dct[33] = w_n1950;
assign w_dct[34] = w_n9238;
assign w_dct[35] = w_p5555;
assign w_dct[36] = w_p7071;
assign w_dct[37] = w_n8314;
assign w_dct[38] = w_n3826;
assign w_dct[39] = w_p9807;
assign w_dct[40] = w_p7071;
assign w_dct[41] = w_n5555;
assign w_dct[42] = w_n3826;
assign w_dct[43] = w_p9807;
assign w_dct[44] = w_n7071;
assign w_dct[45] = w_n1950;
assign w_dct[46] = w_p9238;
assign w_dct[47] = w_n8314;
assign w_dct[48] = w_p7071;
assign w_dct[49] = w_n8314;
assign w_dct[50] = w_p3826;
assign w_dct[51] = w_p1950;
assign w_dct[52] = w_n7071;
assign w_dct[53] = w_p9807;
assign w_dct[54] = w_n9238;
assign w_dct[55] = w_p5555;
assign w_dct[56] = w_p7071;
assign w_dct[57] = w_n9807;
assign w_dct[58] = w_p9238;
assign w_dct[59] = w_n8314;
assign w_dct[60] = w_p7071;
assign w_dct[61] = w_n5555;
assign w_dct[62] = w_p3826;
assign w_dct[63] = w_n1950;
assign o_dct = w_dct[{i_Gxy, i_Buv}];
endmodule |
module yuv_to_rgb
#(
parameter Y_PRECISION = 8,
parameter U_PRECISION = 8,
parameter V_PRECISION = 8,
parameter R_PRECISION = 8,
parameter G_PRECISION = 8,
parameter B_PRECISION = 8
)
(
input i_arst,
input i_sysclk,
input [Y_PRECISION-1:0]i_Y,
input [U_PRECISION-1:0]i_U,
input [V_PRECISION-1:0]i_V,
output [R_PRECISION-1:0]o_R,
output [G_PRECISION-1:0]o_G,
output [B_PRECISION-1:0]o_B
);
/*
Module FFs ADDs LUTs RAMs MULTs
------------------------------- --- ---- ---- ---- -----
yuv_to_rgb:yuv_to_rgb 144(27) 368(83) 48(0) 0(0) 0(0)
+inst_m00:mult(AW=9,BW=11,L=2) 28(28) 49(49) 2(2) 0(0) 0(0)
+inst_m02:mult(AW=9,BW=11,L=2) 19(19) 46(46) 3(3) 0(0) 0(0)
+inst_m11:mult(AW=9,BW=11,L=2) 18(18) 85(85) 7(7) 0(0) 0(0)
+inst_m12:mult(AW=9,BW=11,L=2) 25(25) 75(75) 9(9) 0(0) 0(0)
+inst_m21:mult(AW=9,BW=11,L=2) 27(27) 30(30) 27(27) 0(0) 0(0)
Module FFs ADDs LUTs RAMs MULTs
------------------------------- --- ---- ---- ---- -----
yuv_to_rgb:yuv_to_rgb 144(27) 368(83) 48(0) 0(0) 0(0)
+inst_m11:mult(AW=9,BW=11,L=2) 18(18) 85(85) 7(7) 0(0) 0(0)
+inst_m12:mult(AW=9,BW=11,L=2) 16(16) 58(58) 0(0) 0(0) 0(0)
+inst_m21:mult(AW=9,BW=11,L=2) 26(26) 30(30) 9(9) 0(0) 0(0)
+inst_m00:mult(AW=9,BW=11,L=2) 28(28) 49(49) 2(2) 0(0) 0(0)
+inst_m02:mult(AW=9,BW=11,L=2) 29(29) 63(63) 30(30) 0(0) 0(0)
*/
localparam c_Y = 0;
localparam c_U = 1;
localparam c_V = 2;
localparam c_R = 0;
localparam c_G = 1;
localparam c_B = 2;
localparam c_Ym_msb = Y_PRECISION+11;
localparam c_Um_msb = U_PRECISION+11;
localparam c_Vm_msb = V_PRECISION+11;
wire [10:0]w_matrix_0P[0:8];
assign w_matrix_0P[0]=11'd298;assign w_matrix_0P[1]= 11'd000; assign w_matrix_0P[2]= 11'd409;
assign w_matrix_0P[3]=11'd298;assign w_matrix_0P[4]=~(11'd100)+1'b1;assign w_matrix_0P[5]=~(11'd208)+1'b1;
assign w_matrix_0P[6]=11'd298;assign w_matrix_0P[7]= 11'd516; assign w_matrix_0P[8]= 11'd000;
wire [Y_PRECISION+11:0]w_m00, w_m10, w_m20;
wire [U_PRECISION+11:0]w_m01, w_m11, w_m21;
wire [V_PRECISION+11:0]w_m02, w_m12, w_m22;
wire [Y_PRECISION+11+1:0]w_R;
wire [U_PRECISION+11+1:0]w_G;
wire [V_PRECISION+11+1:0]w_B;
reg [Y_PRECISION:0]r_c_1P;
reg [U_PRECISION:0]r_d_1P;
reg [V_PRECISION:0]r_e_1P;
reg [Y_PRECISION+11+1-8:0]r_R_4P;
reg [U_PRECISION+11+1-8:0]r_G_4P;
reg [V_PRECISION+11+1-8:0]r_B_4P;
reg [R_PRECISION-1:0]r_R_5P;
reg [G_PRECISION-1:0]r_G_5P;
reg [B_PRECISION-1:0]r_B_5P;
reg [R_PRECISION-1:0]r_R_6P;
reg [G_PRECISION-1:0]r_G_6P;
reg [B_PRECISION-1:0]r_B_6P;
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_c_1P <= {Y_PRECISION+1{1'b0}};
r_d_1P <= {U_PRECISION+1{1'b0}};
r_e_1P <= {V_PRECISION+1{1'b0}};
end
else
begin
r_c_1P <= {1'b0, i_Y}-8'd16;
r_d_1P <= {1'b0, i_U}-8'd128;
r_e_1P <= {1'b0, i_V}-8'd128;
end
end
////////////////////////////////////////////////////////////////
//// Synthesis gets Magic
////////////////////////////////////////////////////////////////
assign w_m10 = w_m00;
mult_a_signed_b_signed
#(
.A_WIDTH(U_PRECISION+1),
.B_WIDTH(11),
.LATENCY(2)
)
inst_m11
(
.arst (i_arst),
.clk (i_sysclk),
.a (r_d_1P),
.b (w_matrix_0P[4]),
.o (w_m11)
);
mult_a_signed_b_signed
#(
.A_WIDTH(V_PRECISION+1),
.B_WIDTH(11),
.LATENCY(2)
)
inst_m12
(
.arst (i_arst),
.clk (i_sysclk),
.a (r_e_1P),
.b (w_matrix_0P[5]),
.o (w_m12)
);
////////////////////////////////////////////////////////////////
assign w_m20 = w_m00;
mult_a_signed_b_signed
#(
.A_WIDTH(U_PRECISION+1),
.B_WIDTH(11),
.LATENCY(2)
)
inst_m21
(
.arst (i_arst),
.clk (i_sysclk),
.a (r_d_1P),
.b (w_matrix_0P[7]),
.o (w_m21)
);
assign w_m22 = {V_PRECISION+12{1'b0}};
////////////////////////////////////////////////////////////////
mult_a_signed_b_signed
#(
.A_WIDTH(Y_PRECISION+1),
.B_WIDTH(11),
.LATENCY(2)
)
inst_m00
(
.arst (i_arst),
.clk (i_sysclk),
.a (r_c_1P),
.b (w_matrix_0P[0]),
.o (w_m00)
);
assign w_m01 = {U_PRECISION+12{1'b0}};
mult_a_signed_b_signed
#(
.A_WIDTH(V_PRECISION+1),
.B_WIDTH(11),
.LATENCY(2)
)
inst_m02
(
.arst (i_arst),
.clk (i_sysclk),
.a (r_e_1P),
.b (w_matrix_0P[2]),
.o (w_m02)
);
////////////////////////////////////////////////////////////////
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_R_4P <= {Y_PRECISION+11+1-8{1'b0}};
r_G_4P <= {U_PRECISION+11+1-8{1'b0}};
r_B_4P <= {V_PRECISION+11+1-8{1'b0}};
r_R_5P <= {R_PRECISION-1{1'b0}};
r_G_5P <= {G_PRECISION-1{1'b0}};
r_B_5P <= {B_PRECISION-1{1'b0}};
r_R_6P <= {R_PRECISION-1{1'b0}};
r_G_6P <= {G_PRECISION-1{1'b0}};
r_B_6P <= {B_PRECISION-1{1'b0}};
end
else
begin
r_R_4P <= w_R[Y_PRECISION+11+1:8];
r_G_4P <= w_G[U_PRECISION+11+1:8];
r_B_4P <= w_B[V_PRECISION+11+1:8];
if (r_R_4P[c_Ym_msb+1-8])
r_R_5P <= {R_PRECISION{1'b0}};
else if (r_R_4P[c_Ym_msb-8:R_PRECISION] != {(c_Ym_msb+1-8-R_PRECISION){1'b0}})
r_R_5P <= {R_PRECISION{1'b1}};
else
r_R_5P <= r_R_4P[R_PRECISION-1:0];
if (r_G_4P[c_Um_msb+1-8])
r_G_5P <= {G_PRECISION{1'b0}};
else if (r_G_4P[c_Um_msb-8:G_PRECISION] != {(c_Um_msb+1-8-G_PRECISION){1'b0}})
r_G_5P <= {G_PRECISION{1'b1}};
else
r_G_5P <= r_G_4P[G_PRECISION-1:0];
if (r_B_4P[c_Vm_msb+1-8])
r_B_5P <= {B_PRECISION{1'b0}};
else if (r_B_4P[c_Vm_msb-8:B_PRECISION] != {(c_Vm_msb+1-8-B_PRECISION){1'b0}})
r_B_5P <= {B_PRECISION{1'b1}};
else
r_B_5P <= r_B_4P[B_PRECISION-1:0];
r_R_6P <= r_R_5P;
r_G_6P <= r_G_5P;
r_B_6P <= r_B_5P;
end
end
assign w_R = {w_m00[c_Ym_msb], w_m00} + {w_m01[c_Um_msb], w_m01} + {w_m02[c_Vm_msb], w_m02} + 8'd128;
assign w_G = {w_m10[c_Ym_msb], w_m10} + {w_m11[c_Um_msb], w_m11} + {w_m12[c_Vm_msb], w_m12} + 8'd128;
assign w_B = {w_m20[c_Ym_msb], w_m20} + {w_m21[c_Um_msb], w_m21} + {w_m22[c_Vm_msb], w_m22} + 8'd128;
assign o_R = r_R_5P;
assign o_G = r_G_5P;
assign o_B = r_B_5P;
endmodule |
module spi_controller
#(
parameter SCLK_FREQ = 6'd0,
parameter ADDR_WIDTH = 24,
parameter NUM_OF_JPG = 16,
parameter START_ADDR = 'h40000,
parameter ADDR_OFFSET = 'h40000
)
(
input i_arst,
input i_sysclk,
// user button / VIO
input i_next,
input i_back,
input i_interrupt,
// jfif parser
input i_flush,
`ifdef DBG_MODE
output o_cmd_en,
output [4:0]o_cmd,
output [ADDR_WIDTH-1:0]o_spi_addr,
output o_rd_valid,
output [7:0]o_rd_byte,
output o_rd_fifo_empty,
output o_busy,
output [4:0]o_fsm_status,
output [2:0]o_spi_status,
output o_next_pe,
output o_next_ne,
output o_back_pe,
output o_back_ne,
output o_interrupt_pe,
output o_interrupt_ne,
output [3:0]o_cnt,
output [7:0]o_device_id,
`endif
input i_miso,
input i_miso_1,
output o_nss,
output o_sclk,
output o_mosi,
output o_mosi_oe,
input i_ready,
output o_byte_en,
output [7:0]o_byte
);
function integer log2;
input integer val;
integer i;
begin
log2 = 0;
for (i=0; 2**i<val; i=i+1)
log2 = i+1;
end
endfunction
localparam s_reset = 3'b000;
localparam s_read_id = 3'b001;
localparam s_idle = 3'b010;
localparam s_read = 3'b011;
localparam s_fifo_full = 3'b100;
localparam s_fifo_flush = 3'b101;
localparam c_nop = 5'd0;
localparam c_read_id = 5'd3;
localparam c_read = 5'd2;
localparam c_fast_read = 5'd20;
wire [ADDR_WIDTH-1:0]w_jpg_file_addr_map_0P[0:NUM_OF_JPG-1];
wire w_busy;
wire [7:0]w_rd_byte;
wire w_rd_valid;
wire [4:0]w_fsm_status;
wire [7:0]w_device_id;
wire w_rd_fifo_empty;
wire w_next_pe_0P;
wire w_next_ne_0P;
wire w_back_pe_0P;
wire w_back_ne_0P;
wire w_interrupt_pe_0P;
wire w_interrupt_ne_0P;
reg [2:0]r_spi_status_1P;
reg r_cmd_en_1P;
reg [4:0]r_cmd_1P;
reg r_re_1P;
reg [ADDR_WIDTH-1:0]r_spi_addr_1P;
reg [log2(NUM_OF_JPG)-1:0]r_cnt_1P;
reg r_busy_1P;
reg r_byte_en_1P;
reg r_flush_1P;
reg r_next_1P;
reg r_back_1P;
reg r_interrupt_1P;
reg [log2(NUM_OF_JPG)-1:0]r_stack_1P;
reg r_return_1P;
assign w_jpg_file_addr_map_0P[0] = START_ADDR;
//assign w_jpg_file_addr_map_0P[0] = 'h40000;
//assign w_jpg_file_addr_map_0P[0] = 'h0;
genvar i;
generate
for (i=1; i<NUM_OF_JPG; i=i+1)
begin
assign w_jpg_file_addr_map_0P[i] = w_jpg_file_addr_map_0P[i-1]+ADDR_OFFSET;
// assign w_jpg_file_addr_map_0P[i] = w_jpg_file_addr_map_0P[i-1]+'h40000;
// assign w_jpg_file_addr_map_0P[i] = w_jpg_file_addr_map_0P[i-1]+'h00200;
end
endgenerate
efx_spi_shifter
#(
.SCLK_FREQ (SCLK_FREQ),
.ADDR_WIDTH (ADDR_WIDTH)
)
inst_efx_spi_shifter
(
.nrst (~i_arst),
.clkin (i_sysclk),
.locked (1'b1),
.pll_rst (),
.spi_cmd_en (r_cmd_en_1P),
.spi_cmd (r_cmd_1P),
.spi_cmd_instr ({8{1'b0}}),
.address (r_spi_addr_1P),
.data_in ({8{1'b0}}),
.burst_data_wr ({8{1'b0}}),
.byte_cnt ({9{1'b0}}),
.w_burst_size ({8{1'b0}}),
.r_burst_size (8'd2),
.rden (r_re_1P),
.data_out (w_rd_byte),
.busy (w_busy),
.data_valid (w_rd_valid),
.jedec_id_reg (),
.manufacturing_id_reg (),
.unique_id_reg (),
.device_id_reg (w_device_id),
.spi_flash_rd_status_reg0 (),
.spi_flash_rd_status_reg1 (),
.spi_flash_rd_status_reg2 (),
.erase_en (),
.fsm_status (w_fsm_status),
.wfifo_rd (),
.page_program_done (),
.miso (i_miso),
.miso_1 (i_miso_1),
.sclk (o_sclk),
.nss (o_nss),
.mosi (o_mosi),
.mosi_oe(o_mosi_oe)
);
dual_clock_fifo_wrapper
#(
.DATA_WIDTH (8),
.ADDR_WIDTH (9),
.LATENCY (1),
.FIFO_MODE ("BYPASS"),
.RAM_INIT_FILE (""),
.COMPATIBILITY ("E"),
.OUTPUT_REG ("FALSE"),
.CHECK_FULL ("FALSE"),
.CHECK_EMPTY ("TRUE")
)
inst_dcfifo
(
.i_arst (i_arst),
.i_wclk (i_sysclk),
.i_we (w_rd_valid),
.i_wdata (w_rd_byte),
.i_rclk (i_sysclk),
.i_re ((i_ready & r_byte_en_1P) | r_flush_1P) ,
.o_full (),
.o_empty (w_rd_fifo_empty),
.o_rdata (o_byte),
.o_afull (),
.o_wcnt (),
.o_aempty (),
.o_rcnt ()
);
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_spi_status_1P <= s_reset;
r_cmd_en_1P <= 1'b0;
r_cmd_1P <= c_nop;
r_re_1P <= 1'b0;
r_spi_addr_1P <= {ADDR_WIDTH{1'b0}};
r_cnt_1P <= {log2(NUM_OF_JPG){1'b0}};
r_busy_1P <= 1'b1;
r_byte_en_1P <= 1'b0;
r_flush_1P <= 1'b0;
r_next_1P <= 1'b0;
r_back_1P <= 1'b0;
r_interrupt_1P <= 1'b0;
end
else
begin
r_busy_1P <= w_busy;
r_next_1P <= i_next;
r_back_1P <= i_back;
r_interrupt_1P <= i_interrupt;
case (r_spi_status_1P)
s_reset:
begin
if (~w_busy & r_busy_1P)
r_spi_status_1P <= s_read_id;
end
s_read_id:
begin
r_cmd_en_1P <= 1'b1;
r_cmd_1P <= c_read_id;
if (~w_busy & r_busy_1P)
begin
r_spi_status_1P <= s_read;
r_cmd_en_1P <= 1'b0;
r_cmd_1P <= c_nop;
r_spi_addr_1P <= w_jpg_file_addr_map_0P[r_cnt_1P];
end
end
s_idle:
begin
if (w_next_pe_0P)
r_cnt_1P <= r_cnt_1P+1'b1;
else if (w_back_pe_0P)
r_cnt_1P <= r_cnt_1P-1'b1;
else if (w_interrupt_pe_0P)
begin
if (r_return_1P)
begin
r_cnt_1P <= r_stack_1P;
r_return_1P <= 1'b0;
end
else
begin
r_cnt_1P <= NUM_OF_JPG-1'b1;
r_stack_1P <= r_cnt_1P;
r_return_1P <= 1'b1;
end
end
if (i_flush)
begin
r_spi_status_1P <= s_fifo_flush;
r_flush_1P <= 1'b1;
end
else if (w_next_ne_0P | w_back_ne_0P | w_interrupt_ne_0P)
begin
r_spi_status_1P <= s_read;
r_spi_addr_1P <= w_jpg_file_addr_map_0P[r_cnt_1P];
end
end
s_read:
begin
r_cmd_en_1P <= 1'b1;
r_cmd_1P <= c_fast_read;
r_re_1P <= 1'b1;
if (i_flush)
begin
r_spi_status_1P <= s_fifo_flush;
r_cmd_en_1P <= 1'b0;
r_cmd_1P <= c_nop;
r_re_1P <= 1'b0;
r_flush_1P <= 1'b1;
end
else if (~w_busy & r_busy_1P)
begin
r_spi_status_1P <= s_fifo_full;
r_cmd_en_1P <= 1'b0;
r_cmd_1P <= c_nop;
r_re_1P <= 1'b0;
r_byte_en_1P <= 1'b1;
end
end
s_fifo_full:
begin
if (i_flush)
begin
r_spi_status_1P <= s_fifo_flush;
r_flush_1P <= 1'b1;
end
else if (w_rd_fifo_empty)
begin
r_spi_status_1P <= s_read;
r_spi_addr_1P <= r_spi_addr_1P+10'd512;
r_byte_en_1P <= 1'b0;
end
end
s_fifo_flush:
begin
if (w_rd_fifo_empty)
begin
r_spi_status_1P <= s_idle;
r_flush_1P <= 1'b0;
end
end
default:
begin
r_spi_status_1P <= s_read_id;
r_cmd_en_1P <= 1'b0;
r_cmd_1P <= c_nop;
r_re_1P <= 1'b0;
r_spi_addr_1P <= {ADDR_WIDTH{1'b0}};
r_cnt_1P <= {log2(NUM_OF_JPG){1'b0}};
r_busy_1P <= 1'b0;
r_byte_en_1P <= 1'b0;
r_flush_1P <= 1'b0;
r_next_1P <= 1'b0;
r_back_1P <= 1'b0;
r_interrupt_1P <= 1'b0;
end
endcase
end
end
assign w_next_pe_0P = i_next & ~r_next_1P;
assign w_next_ne_0P = ~i_next & r_next_1P;
assign w_back_pe_0P = i_back & ~r_back_1P;
assign w_back_ne_0P = ~i_back & r_back_1P;
assign w_interrupt_pe_0P = i_interrupt & ~r_interrupt_1P;
assign w_interrupt_ne_0P = ~i_interrupt & r_interrupt_1P;
assign o_byte_en = ~w_rd_fifo_empty & r_byte_en_1P;
`ifdef DBG_MODE
assign o_cmd_en = r_cmd_en_1P;
assign o_cmd = r_cmd_1P;
assign o_spi_addr = r_spi_addr_1P;
assign o_rd_valid = w_rd_valid;
assign o_rd_byte = w_rd_byte;
assign o_rd_fifo_empty = w_rd_fifo_empty;
assign o_busy = w_busy;
assign o_fsm_status = w_fsm_status;
assign o_spi_status = r_spi_status_1P;
assign o_next_pe = w_next_pe_0P;
assign o_next_ne = w_next_ne_0P;
assign o_back_pe = w_back_pe_0P;
assign o_back_ne = w_back_ne_0P;
assign o_interrupt_pe = w_interrupt_pe_0P;
assign o_interrupt_ne = w_interrupt_ne_0P;
assign o_cnt = r_cnt_1P;
assign o_device_id = w_device_id;
`endif
endmodule |
module zigzag_to_matrix_tb();
localparam DATA_W = 8;
localparam MCU_WIDTH = 8;
localparam MCU_HEIGHT = 8;
localparam NUM_MATRIX = 4;
localparam PX_OUT = 1;
localparam PY_OUT = 1;
localparam s_idle = 1'b0;
localparam s_done = 1'b1;
reg r_srst;
reg r_sysclk;
reg r_state_1P;
reg r_we;
reg [255:0]r_ptr;
wire [DATA_W-1:0]w_data[0:MCU_HEIGHT*MCU_WIDTH-1];
wire w_full;
reg r_re;
wire [PY_OUT*PX_OUT*DATA_W-1:0]w_md;
wire w_nempty;
/*
0 0_0
1 0_1 1_0
3 2_0 1_1 0_2
6 0_3 1_2 2_1 3_0
10 4_0 3_1 2_2 1_3 0_4
15 0_5 1_4 2_3 3_2 4_1 5_0
21 6_0 5_1 4_2 3_3 2_4 1_5 0_6
28 0_7 1_6 2_5 3_4 4_3 5_2 6_1 7_0
36 7_1 6_2 5_3 4_4 3_5 2_6 1_7
43 2_7 3_6 4_5 5_4 6_3 7_2
49
*/
assign w_data[0] = 8'h0_0;
assign w_data[1] = 8'h0_1;
assign w_data[2] = 8'h1_0;
assign w_data[3] = 8'h2_0;
assign w_data[4] = 8'h1_1;
assign w_data[5] = 8'h0_2;
assign w_data[6] = 8'h0_3;
assign w_data[7] = 8'h1_2;
assign w_data[8] = 8'h2_1;
assign w_data[9] = 8'h3_0;
assign w_data[10] = 8'h4_0;
assign w_data[11] = 8'h3_1;
assign w_data[12] = 8'h2_2;
assign w_data[13] = 8'h1_3;
assign w_data[14] = 8'h0_4;
assign w_data[15] = 8'h0_5;
assign w_data[16] = 8'h1_4;
assign w_data[17] = 8'h2_3;
assign w_data[18] = 8'h3_2;
assign w_data[19] = 8'h4_1;
assign w_data[20] = 8'h5_0;
assign w_data[21] = 8'h6_0;
assign w_data[22] = 8'h5_1;
assign w_data[23] = 8'h4_2;
assign w_data[24] = 8'h3_3;
assign w_data[25] = 8'h2_4;
assign w_data[26] = 8'h1_5;
assign w_data[27] = 8'h0_6;
assign w_data[28] = 8'h0_7;
assign w_data[29] = 8'h1_6;
assign w_data[30] = 8'h2_5;
assign w_data[31] = 8'h3_4;
assign w_data[32] = 8'h4_3;
assign w_data[33] = 8'h5_2;
assign w_data[34] = 8'h6_1;
assign w_data[35] = 8'h7_0;
assign w_data[36] = 8'h7_1;
assign w_data[37] = 8'h6_2;
assign w_data[38] = 8'h5_3;
assign w_data[39] = 8'h4_4;
assign w_data[40] = 8'h3_5;
assign w_data[41] = 8'h2_6;
assign w_data[42] = 8'h1_7;
assign w_data[43] = 8'h2_7;
assign w_data[44] = 8'h3_6;
assign w_data[45] = 8'h4_5;
assign w_data[46] = 8'h5_4;
assign w_data[47] = 8'h6_3;
assign w_data[48] = 8'h7_2;
assign w_data[49] = 8'h7_3;
assign w_data[50] = 8'h6_4;
assign w_data[51] = 8'h5_5;
assign w_data[52] = 8'h4_6;
assign w_data[53] = 8'h3_7;
assign w_data[54] = 8'h4_7;
assign w_data[55] = 8'h5_6;
assign w_data[56] = 8'h6_5;
assign w_data[57] = 8'h7_4;
assign w_data[58] = 8'h7_5;
assign w_data[59] = 8'h6_6;
assign w_data[60] = 8'h5_7;
assign w_data[61] = 8'h6_7;
assign w_data[62] = 8'h7_6;
assign w_data[63] = 8'h7_7;
zigzag_to_matrix
#(
.DATA_W (DATA_W),
.MCU_WIDTH (MCU_WIDTH),
.MCU_HEIGHT (MCU_HEIGHT),
.NUM_MATRIX (NUM_MATRIX),
.PX_OUT (PX_OUT),
.PY_OUT (PY_OUT),
.MATRIX_TYPE("RAM")
)
inst_zigzag_to_matrix
(
.i_arst (r_srst),
.i_srst (r_srst),
.i_sysclk (r_sysclk),
.i_we (r_we),
.i_data (w_data[r_ptr[5:0]]),
.o_full (w_full),
.i_re (r_re),
.o_nempty (w_nempty),
.o_md (w_md)
);
initial
begin
r_srst <= 1'b1;
#10 r_srst <= 1'b0;
end
initial
begin
r_sysclk <= 1'b1;
forever
#2.5 r_sysclk <= ~r_sysclk;
end
always@(posedge r_srst or posedge r_sysclk)
begin
if (r_srst)
begin
r_state_1P <= s_idle;
r_we <= 1'b0;
r_re <= 1'b0;
r_ptr <= {8{1'b0}};
end
else
begin
case (r_state_1P)
s_idle:
begin
r_we <= 1'b1;
if (r_we)
begin
r_ptr <= r_ptr+1'b1;
if (r_ptr == {8{1'b1}}-1'b1)
r_state_1P <= s_done;
end
end
s_done:
begin
r_we <= 1'b0;
r_re <= 1'b1;
end
endcase
end
end
endmodule |
module yuv_to_rgb_tb();
localparam Y_PRECISION = 8;
localparam U_PRECISION = 8;
localparam V_PRECISION = 8;
localparam R_PRECISION = 8;
localparam G_PRECISION = 8;
localparam B_PRECISION = 8;
reg r_arst;
reg r_sysclk;
reg [Y_PRECISION-1:0]r_Y;
reg [U_PRECISION-1:0]r_U;
reg [V_PRECISION-1:0]r_V;
wire [R_PRECISION-1:0]w_R;
wire [G_PRECISION-1:0]w_G;
wire [B_PRECISION-1:0]w_B;
/*
Y U V c d e m00 m01 m02 m10 m11 m12 m20 m21 m22 R G B
0 0 0 -16 -128 -128 -4768 0 -52352 -4768 12800 26624 -4768 -66048 0 -56992 34784 -70688
-222.6 90.8 -276.1
255 255 255 239 127 127 71222 0 51943 71222 -12700 -26416 71222 65532 0 123293 32234 136882
481.6 125.9 534.6
*/
initial
begin
r_arst <= 1'b1;
r_Y <= 8'd0;
r_U <= 8'd0;
r_V <= 8'd0;
// 0 135 0
#10 r_arst <= 1'b0;
#10 r_Y <= 8'd255;
r_U <= 8'd255;
r_V <= 8'd255;
// 255 120 255
#10 r_Y <= 8'd76;
r_U <= 8'd84;
r_V <= 8'd255;
// 255 0 0
#10 r_Y <= 8'd149;
r_U <= 8'd43;
r_V <= 8'd21;
// 0 255 0
#10 r_Y <= 8'd29;
r_U <= 8'd255;
r_V <= 8'd107;
// 0 0 255
#10 r_Y <= 8'd178;
r_U <= 8'd171;
r_V <= 8'd0;
// 0 255 255
#10 r_Y <= 8'd225;
r_U <= 8'd0;
r_V <= 8'd148;
// 255 255 0
end
initial
begin
r_sysclk <= 1'b0;
forever
#5 r_sysclk <= ~r_sysclk;
end
yuv_to_rgb
#(
.Y_PRECISION(Y_PRECISION),
.U_PRECISION(U_PRECISION),
.V_PRECISION(V_PRECISION),
.R_PRECISION(R_PRECISION),
.G_PRECISION(G_PRECISION),
.B_PRECISION(B_PRECISION)
)
inst_yuv_to_rgb
(
.i_arst (r_arst),
.i_sysclk (r_sysclk),
.i_Y (r_Y),
.i_U (r_U),
.i_V (r_V),
.o_R (w_R),
.o_G (w_G),
.o_B (w_B)
);
endmodule |
module line_buffer_tb();
localparam COLOR_PRECISION = 8;
localparam MAX_HRES = 480;
localparam LINE = 16;
localparam Y_XI_SUBSAMPLE = 1;
localparam Y_YI_SUBSAMPLE = 1;
localparam C_XI_SUBSAMPLE = 2;
localparam C_YI_SUBSAMPLE = 2;
localparam Y_XO_SUBSAMPLE = 1;
localparam Y_YO_SUBSAMPLE = 1;
localparam C_XO_SUBSAMPLE = 2;
localparam C_YO_SUBSAMPLE = 2;
localparam WR_ADDRESSING = "BLOCK";
localparam RD_ADDRESSING = "LINE";
localparam MCU_WIDTH = 8;
localparam MCU_HEIGHT = 8;
localparam BRAM_OUTPUT_REG = "FALSE";
localparam s_idle = 2'b00;
localparam s_wr = 2'b01;
localparam s_rd = 2'b10;
localparam s_done = 2'b11;
reg r_arst;
reg r_sysclk;
reg [8:0]r_hres;
reg [2:0]r_we;
wire [COLOR_PRECISION-1:0]w_Y_wd[0:MCU_HEIGHT*MCU_WIDTH*4-1];
wire [COLOR_PRECISION-1:0]i_Y_wd;
wire [COLOR_PRECISION-1:0]i_U_wd;
wire [COLOR_PRECISION-1:0]i_V_wd;
reg [7:0]r_ptr;
reg [15:0]r_cycle;
wire w_full;
reg r_re;
wire [COLOR_PRECISION-1:0]w_Y_rd;
wire [COLOR_PRECISION-1:0]w_U_rd;
wire [COLOR_PRECISION-1:0]w_V_rd;
wire w_nempty;
reg [1:0]r_state_1P;
assign w_Y_wd[8* 0+0] = 8'h0_0;
assign w_Y_wd[8* 0+1] = 8'h0_1;
assign w_Y_wd[8* 0+2] = 8'h0_2;
assign w_Y_wd[8* 0+3] = 8'h0_3;
assign w_Y_wd[8* 0+4] = 8'h0_4;
assign w_Y_wd[8* 0+5] = 8'h0_5;
assign w_Y_wd[8* 0+6] = 8'h0_6;
assign w_Y_wd[8* 0+7] = 8'h0_7;
assign w_Y_wd[8* 1+0] = 8'h1_0;
assign w_Y_wd[8* 1+1] = 8'h1_1;
assign w_Y_wd[8* 1+2] = 8'h1_2;
assign w_Y_wd[8* 1+3] = 8'h1_3;
assign w_Y_wd[8* 1+4] = 8'h1_4;
assign w_Y_wd[8* 1+5] = 8'h1_5;
assign w_Y_wd[8* 1+6] = 8'h1_6;
assign w_Y_wd[8* 1+7] = 8'h1_7;
assign w_Y_wd[8* 2+0] = 8'h2_0;
assign w_Y_wd[8* 2+1] = 8'h2_1;
assign w_Y_wd[8* 2+2] = 8'h2_2;
assign w_Y_wd[8* 2+3] = 8'h2_3;
assign w_Y_wd[8* 2+4] = 8'h2_4;
assign w_Y_wd[8* 2+5] = 8'h2_5;
assign w_Y_wd[8* 2+6] = 8'h2_6;
assign w_Y_wd[8* 2+7] = 8'h2_7;
assign w_Y_wd[8* 3+0] = 8'h3_0;
assign w_Y_wd[8* 3+1] = 8'h3_1;
assign w_Y_wd[8* 3+2] = 8'h3_2;
assign w_Y_wd[8* 3+3] = 8'h3_3;
assign w_Y_wd[8* 3+4] = 8'h3_4;
assign w_Y_wd[8* 3+5] = 8'h3_5;
assign w_Y_wd[8* 3+6] = 8'h3_6;
assign w_Y_wd[8* 3+7] = 8'h3_7;
assign w_Y_wd[8* 4+0] = 8'h4_0;
assign w_Y_wd[8* 4+1] = 8'h4_1;
assign w_Y_wd[8* 4+2] = 8'h4_2;
assign w_Y_wd[8* 4+3] = 8'h4_3;
assign w_Y_wd[8* 4+4] = 8'h4_4;
assign w_Y_wd[8* 4+5] = 8'h4_5;
assign w_Y_wd[8* 4+6] = 8'h4_6;
assign w_Y_wd[8* 4+7] = 8'h4_7;
assign w_Y_wd[8* 5+0] = 8'h5_0;
assign w_Y_wd[8* 5+1] = 8'h5_1;
assign w_Y_wd[8* 5+2] = 8'h5_2;
assign w_Y_wd[8* 5+3] = 8'h5_3;
assign w_Y_wd[8* 5+4] = 8'h5_4;
assign w_Y_wd[8* 5+5] = 8'h5_5;
assign w_Y_wd[8* 5+6] = 8'h5_6;
assign w_Y_wd[8* 5+7] = 8'h5_7;
assign w_Y_wd[8* 6+0] = 8'h6_0;
assign w_Y_wd[8* 6+1] = 8'h6_1;
assign w_Y_wd[8* 6+2] = 8'h6_2;
assign w_Y_wd[8* 6+3] = 8'h6_3;
assign w_Y_wd[8* 6+4] = 8'h6_4;
assign w_Y_wd[8* 6+5] = 8'h6_5;
assign w_Y_wd[8* 6+6] = 8'h6_6;
assign w_Y_wd[8* 6+7] = 8'h6_7;
assign w_Y_wd[8* 7+0] = 8'h7_0;
assign w_Y_wd[8* 7+1] = 8'h7_1;
assign w_Y_wd[8* 7+2] = 8'h7_2;
assign w_Y_wd[8* 7+3] = 8'h7_3;
assign w_Y_wd[8* 7+4] = 8'h7_4;
assign w_Y_wd[8* 7+5] = 8'h7_5;
assign w_Y_wd[8* 7+6] = 8'h7_6;
assign w_Y_wd[8* 7+7] = 8'h7_7;
assign w_Y_wd[8* 8+0] = 8'h0_8;
assign w_Y_wd[8* 8+1] = 8'h0_9;
assign w_Y_wd[8* 8+2] = 8'h0_A;
assign w_Y_wd[8* 8+3] = 8'h0_B;
assign w_Y_wd[8* 8+4] = 8'h0_C;
assign w_Y_wd[8* 8+5] = 8'h0_D;
assign w_Y_wd[8* 8+6] = 8'h0_E;
assign w_Y_wd[8* 8+7] = 8'h0_F;
assign w_Y_wd[8* 9+0] = 8'h1_8;
assign w_Y_wd[8* 9+1] = 8'h1_9;
assign w_Y_wd[8* 9+2] = 8'h1_A;
assign w_Y_wd[8* 9+3] = 8'h1_B;
assign w_Y_wd[8* 9+4] = 8'h1_C;
assign w_Y_wd[8* 9+5] = 8'h1_D;
assign w_Y_wd[8* 9+6] = 8'h1_E;
assign w_Y_wd[8* 9+7] = 8'h1_F;
assign w_Y_wd[8*10+0] = 8'h2_8;
assign w_Y_wd[8*10+1] = 8'h2_9;
assign w_Y_wd[8*10+2] = 8'h2_A;
assign w_Y_wd[8*10+3] = 8'h2_B;
assign w_Y_wd[8*10+4] = 8'h2_C;
assign w_Y_wd[8*10+5] = 8'h2_D;
assign w_Y_wd[8*10+6] = 8'h2_E;
assign w_Y_wd[8*10+7] = 8'h2_F;
assign w_Y_wd[8*11+0] = 8'h3_8;
assign w_Y_wd[8*11+1] = 8'h3_9;
assign w_Y_wd[8*11+2] = 8'h3_A;
assign w_Y_wd[8*11+3] = 8'h3_B;
assign w_Y_wd[8*11+4] = 8'h3_C;
assign w_Y_wd[8*11+5] = 8'h3_D;
assign w_Y_wd[8*11+6] = 8'h3_E;
assign w_Y_wd[8*11+7] = 8'h3_F;
assign w_Y_wd[8*12+0] = 8'h4_8;
assign w_Y_wd[8*12+1] = 8'h4_9;
assign w_Y_wd[8*12+2] = 8'h4_A;
assign w_Y_wd[8*12+3] = 8'h4_B;
assign w_Y_wd[8*12+4] = 8'h4_C;
assign w_Y_wd[8*12+5] = 8'h4_D;
assign w_Y_wd[8*12+6] = 8'h4_E;
assign w_Y_wd[8*12+7] = 8'h4_F;
assign w_Y_wd[8*13+0] = 8'h5_8;
assign w_Y_wd[8*13+1] = 8'h5_9;
assign w_Y_wd[8*13+2] = 8'h5_A;
assign w_Y_wd[8*13+3] = 8'h5_B;
assign w_Y_wd[8*13+4] = 8'h5_C;
assign w_Y_wd[8*13+5] = 8'h5_D;
assign w_Y_wd[8*13+6] = 8'h5_E;
assign w_Y_wd[8*13+7] = 8'h5_F;
assign w_Y_wd[8*14+0] = 8'h6_8;
assign w_Y_wd[8*14+1] = 8'h6_9;
assign w_Y_wd[8*14+2] = 8'h6_A;
assign w_Y_wd[8*14+3] = 8'h6_B;
assign w_Y_wd[8*14+4] = 8'h6_C;
assign w_Y_wd[8*14+5] = 8'h6_D;
assign w_Y_wd[8*14+6] = 8'h6_E;
assign w_Y_wd[8*14+7] = 8'h6_F;
assign w_Y_wd[8*15+0] = 8'h7_8;
assign w_Y_wd[8*15+1] = 8'h7_9;
assign w_Y_wd[8*15+2] = 8'h7_A;
assign w_Y_wd[8*15+3] = 8'h7_B;
assign w_Y_wd[8*15+4] = 8'h7_C;
assign w_Y_wd[8*15+5] = 8'h7_D;
assign w_Y_wd[8*15+6] = 8'h7_E;
assign w_Y_wd[8*15+7] = 8'h7_F;
assign w_Y_wd[8*16+0] = 8'h8_0;
assign w_Y_wd[8*16+1] = 8'h8_1;
assign w_Y_wd[8*16+2] = 8'h8_2;
assign w_Y_wd[8*16+3] = 8'h8_3;
assign w_Y_wd[8*16+4] = 8'h8_4;
assign w_Y_wd[8*16+5] = 8'h8_5;
assign w_Y_wd[8*16+6] = 8'h8_6;
assign w_Y_wd[8*16+7] = 8'h8_7;
assign w_Y_wd[8*17+0] = 8'h9_0;
assign w_Y_wd[8*17+1] = 8'h9_1;
assign w_Y_wd[8*17+2] = 8'h9_2;
assign w_Y_wd[8*17+3] = 8'h9_3;
assign w_Y_wd[8*17+4] = 8'h9_4;
assign w_Y_wd[8*17+5] = 8'h9_5;
assign w_Y_wd[8*17+6] = 8'h9_6;
assign w_Y_wd[8*17+7] = 8'h9_7;
assign w_Y_wd[8*18+0] = 8'hA_0;
assign w_Y_wd[8*18+1] = 8'hA_1;
assign w_Y_wd[8*18+2] = 8'hA_2;
assign w_Y_wd[8*18+3] = 8'hA_3;
assign w_Y_wd[8*18+4] = 8'hA_4;
assign w_Y_wd[8*18+5] = 8'hA_5;
assign w_Y_wd[8*18+6] = 8'hA_6;
assign w_Y_wd[8*18+7] = 8'hA_7;
assign w_Y_wd[8*19+0] = 8'hB_0;
assign w_Y_wd[8*19+1] = 8'hB_1;
assign w_Y_wd[8*19+2] = 8'hB_2;
assign w_Y_wd[8*19+3] = 8'hB_3;
assign w_Y_wd[8*19+4] = 8'hB_4;
assign w_Y_wd[8*19+5] = 8'hB_5;
assign w_Y_wd[8*19+6] = 8'hB_6;
assign w_Y_wd[8*19+7] = 8'hB_7;
assign w_Y_wd[8*20+0] = 8'hC_0;
assign w_Y_wd[8*20+1] = 8'hC_1;
assign w_Y_wd[8*20+2] = 8'hC_2;
assign w_Y_wd[8*20+3] = 8'hC_3;
assign w_Y_wd[8*20+4] = 8'hC_4;
assign w_Y_wd[8*20+5] = 8'hC_5;
assign w_Y_wd[8*20+6] = 8'hC_6;
assign w_Y_wd[8*20+7] = 8'hC_7;
assign w_Y_wd[8*21+0] = 8'hD_0;
assign w_Y_wd[8*21+1] = 8'hD_1;
assign w_Y_wd[8*21+2] = 8'hD_2;
assign w_Y_wd[8*21+3] = 8'hD_3;
assign w_Y_wd[8*21+4] = 8'hD_4;
assign w_Y_wd[8*21+5] = 8'hD_5;
assign w_Y_wd[8*21+6] = 8'hD_6;
assign w_Y_wd[8*21+7] = 8'hD_7;
assign w_Y_wd[8*22+0] = 8'hE_0;
assign w_Y_wd[8*22+1] = 8'hE_1;
assign w_Y_wd[8*22+2] = 8'hE_2;
assign w_Y_wd[8*22+3] = 8'hE_3;
assign w_Y_wd[8*22+4] = 8'hE_4;
assign w_Y_wd[8*22+5] = 8'hE_5;
assign w_Y_wd[8*22+6] = 8'hE_6;
assign w_Y_wd[8*22+7] = 8'hE_7;
assign w_Y_wd[8*23+0] = 8'hF_0;
assign w_Y_wd[8*23+1] = 8'hF_1;
assign w_Y_wd[8*23+2] = 8'hF_2;
assign w_Y_wd[8*23+3] = 8'hF_3;
assign w_Y_wd[8*23+4] = 8'hF_4;
assign w_Y_wd[8*23+5] = 8'hF_5;
assign w_Y_wd[8*23+6] = 8'hF_6;
assign w_Y_wd[8*23+7] = 8'hF_7;
assign w_Y_wd[8*24+0] = 8'h8_8;
assign w_Y_wd[8*24+1] = 8'h8_9;
assign w_Y_wd[8*24+2] = 8'h8_A;
assign w_Y_wd[8*24+3] = 8'h8_B;
assign w_Y_wd[8*24+4] = 8'h8_C;
assign w_Y_wd[8*24+5] = 8'h8_D;
assign w_Y_wd[8*24+6] = 8'h8_E;
assign w_Y_wd[8*24+7] = 8'h8_F;
assign w_Y_wd[8*25+0] = 8'h9_8;
assign w_Y_wd[8*25+1] = 8'h9_9;
assign w_Y_wd[8*25+2] = 8'h9_A;
assign w_Y_wd[8*25+3] = 8'h9_B;
assign w_Y_wd[8*25+4] = 8'h9_C;
assign w_Y_wd[8*25+5] = 8'h9_D;
assign w_Y_wd[8*25+6] = 8'h9_E;
assign w_Y_wd[8*25+7] = 8'h9_F;
assign w_Y_wd[8*26+0] = 8'hA_8;
assign w_Y_wd[8*26+1] = 8'hA_9;
assign w_Y_wd[8*26+2] = 8'hA_A;
assign w_Y_wd[8*26+3] = 8'hA_B;
assign w_Y_wd[8*26+4] = 8'hA_C;
assign w_Y_wd[8*26+5] = 8'hA_D;
assign w_Y_wd[8*26+6] = 8'hA_E;
assign w_Y_wd[8*26+7] = 8'hA_F;
assign w_Y_wd[8*27+0] = 8'hB_8;
assign w_Y_wd[8*27+1] = 8'hB_9;
assign w_Y_wd[8*27+2] = 8'hB_A;
assign w_Y_wd[8*27+3] = 8'hB_B;
assign w_Y_wd[8*27+4] = 8'hB_C;
assign w_Y_wd[8*27+5] = 8'hB_D;
assign w_Y_wd[8*27+6] = 8'hB_E;
assign w_Y_wd[8*27+7] = 8'hB_F;
assign w_Y_wd[8*28+0] = 8'hC_8;
assign w_Y_wd[8*28+1] = 8'hC_9;
assign w_Y_wd[8*28+2] = 8'hC_A;
assign w_Y_wd[8*28+3] = 8'hC_B;
assign w_Y_wd[8*28+4] = 8'hC_C;
assign w_Y_wd[8*28+5] = 8'hC_D;
assign w_Y_wd[8*28+6] = 8'hC_E;
assign w_Y_wd[8*28+7] = 8'hC_F;
assign w_Y_wd[8*29+0] = 8'hD_8;
assign w_Y_wd[8*29+1] = 8'hD_9;
assign w_Y_wd[8*29+2] = 8'hD_A;
assign w_Y_wd[8*29+3] = 8'hD_B;
assign w_Y_wd[8*29+4] = 8'hD_C;
assign w_Y_wd[8*29+5] = 8'hD_D;
assign w_Y_wd[8*29+6] = 8'hD_E;
assign w_Y_wd[8*29+7] = 8'hD_F;
assign w_Y_wd[8*30+0] = 8'hE_8;
assign w_Y_wd[8*30+1] = 8'hE_9;
assign w_Y_wd[8*30+2] = 8'hE_A;
assign w_Y_wd[8*30+3] = 8'hE_B;
assign w_Y_wd[8*30+4] = 8'hE_C;
assign w_Y_wd[8*30+5] = 8'hE_D;
assign w_Y_wd[8*30+6] = 8'hE_E;
assign w_Y_wd[8*30+7] = 8'hE_F;
assign w_Y_wd[8*31+0] = 8'hF_8;
assign w_Y_wd[8*31+1] = 8'hF_9;
assign w_Y_wd[8*31+2] = 8'hF_A;
assign w_Y_wd[8*31+3] = 8'hF_B;
assign w_Y_wd[8*31+4] = 8'hF_C;
assign w_Y_wd[8*31+5] = 8'hF_D;
assign w_Y_wd[8*31+6] = 8'hF_E;
assign w_Y_wd[8*31+7] = 8'hF_F;
assign i_Y_wd = w_Y_wd[r_ptr];
assign i_U_wd = w_Y_wd[r_ptr];
assign i_V_wd = w_Y_wd[r_ptr];
line_buffer
#(
.COLOR_PRECISION(COLOR_PRECISION),
.MAX_HRES (MAX_HRES),
.LINE (LINE),
.WR_ADDRESSING (WR_ADDRESSING),
.RD_ADDRESSING (RD_ADDRESSING),
.MCU_WIDTH (MCU_WIDTH),
.MCU_HEIGHT (MCU_HEIGHT),
.BRAM_OUTPUT_REG(BRAM_OUTPUT_REG)
)
inst_line_buffer
(
.i_arst (r_arst),
.i_sysclk (r_sysclk),
.i_hres (r_hres),
.i_Y_we (r_we[0]),
.i_U_we (r_we[1]),
.i_V_we (r_we[2]),
.i_Y_wd (i_Y_wd),
.i_U_wd (i_U_wd),
.i_V_wd (i_V_wd),
.o_full (w_full),
.i_re (r_re),
.o_Y_rd (w_Y_rd),
.o_U_rd (w_U_rd),
.o_V_rd (w_V_rd),
.o_nempty (w_nempty)
);
initial
begin
r_arst <= 1'b1;
#5 r_arst <= 1'b0;
end
initial
begin
r_sysclk <= 1'b1;
forever
#2.5 r_sysclk <= ~r_sysclk;
end
always@(posedge r_arst or posedge r_sysclk)
begin
if (r_arst)
begin
r_state_1P <= s_idle;
r_hres <= {9{1'b0}};
r_we <= {3{1'b0}};
r_ptr <= {8{1'b0}};
r_cycle <= {16{1'b0}};
r_re <= 1'b0;
end
else
begin
case (r_state_1P)
s_idle:
begin
r_state_1P <= s_wr;
r_hres <= 9'd480-1'b1;
r_we <= {3{1'b1}};
end
s_wr:
begin
r_ptr <= r_ptr+1'b1;
if (r_ptr == MCU_HEIGHT*MCU_WIDTH-1)
begin
r_we[2:1] <= {2{1'b0}};
end
else if (r_ptr == MCU_HEIGHT*MCU_WIDTH*4-1)
begin
r_ptr <= {8{1'b0}};
r_cycle <= r_cycle+1'b1;
r_we <= {3{1'b1}};
r_re <= 1'b0;
if (r_cycle == 16'd29)
begin
r_state_1P <= s_rd;
r_cycle <= {8{1'b0}};
r_we <= {3{1'b0}};
r_re <= 1'b1;
end
end
end
s_rd:
begin
r_cycle <= r_cycle+1'b1;
if (r_ptr == 16'd480*16'd16-1'b1)
begin
r_state_1P <= s_done;
r_we <= {3{1'b0}};
r_re <= 1'b0;
end
end
s_done:
begin
end
endcase
end
end
endmodule |
module sos_parser_tb();
localparam CNT_W = 4;
integer jpeg_file;
integer temp;
reg r_arst;
reg r_sysclk;
reg r_byte_en;
reg [7:0]r_byte[0:1023];
reg [15:0]r_ptr;
wire [7:0]w_byte;
wire w_ready;
reg r_re;
wire w_start;
wire w_scan_en;
wire w_ecs_bit;
assign w_byte = r_byte[r_ptr];
sos_parser
#(
.CNT_W(CNT_W)
)
inst_sos_parser
(
.i_arst (r_arst),
.i_sysclk (r_sysclk),
.i_byte_en (r_byte_en),
.i_byte (w_byte),
.o_ready (w_ready),
.i_re (r_re),
.o_start (w_start),
.o_scan_en (w_scan_en),
.o_ecs_bit (w_ecs_bit)
);
initial
begin
jpeg_file = $fopen("test_pattern_01.jpg", "rb");
temp = $fread(r_byte, jpeg_file, 0, 1023);
$fclose(jpeg_file);
end
initial
begin
r_arst <= 1'b1;
#10 r_arst <= 1'b0;
end
initial
begin
r_sysclk <= 1'b1;
forever
#2.5 r_sysclk <= ~r_sysclk;
end
always@(posedge r_arst or posedge r_sysclk)
begin
if (r_arst)
begin
r_byte_en <= 1'b0;
r_ptr <= 'h0;
r_re <= 1'b0;
end
else
begin
r_byte_en <= 1'b1;
if (w_ready)
r_ptr <= r_ptr+1'b1;
r_re <= 1'b1;
end
end
endmodule |
module yuv_to_rgb_tb();
localparam COLOR_PRECISION = 8;
reg r_arst;
reg r_sysclk;
reg [COLOR_PRECISION-1:0]r_R;
reg [COLOR_PRECISION-1:0]r_G;
reg [COLOR_PRECISION-1:0]r_B;
wire [COLOR_PRECISION-1:0]w_C;
wire [COLOR_PRECISION-1:0]w_M;
wire [COLOR_PRECISION-1:0]w_Y;
wire [COLOR_PRECISION-1:0]w_K;
initial
begin
r_arst <= 1'b1;
r_R <= 8'd0;
r_G <= 8'd0;
r_B <= 8'd0;
#10 r_arst <= 1'b0;
#5 r_R <= 8'd255;
r_G <= 8'd255;
r_B <= 8'd255;
//
#5 r_R <= 8'd255;
r_G <= 8'd0;
r_B <= 8'd0;
//
#5 r_R <= 8'd0;
r_G <= 8'd255;
r_B <= 8'd0;
//
#5 r_R <= 8'd0;
r_G <= 8'd0;
r_B <= 8'd255;
end
initial
begin
r_sysclk <= 1'b1;
forever
#2.5 r_sysclk <= ~r_sysclk;
end
rgb_to_cmyk
#(
.COLOR_PRECISION(COLOR_PRECISION)
)
inst_rgb_to_cmyk
(
.i_arst (r_arst),
.i_sysclk (r_sysclk),
.i_R (r_R),
.i_G (r_G),
.i_B (r_B),
.o_C (w_C),
.o_M (w_M),
.o_Y (w_Y),
.o_K (w_K)
);
endmodule |
module spi_controller_tb();
localparam SCLK_FREQ = 6'd1;
localparam ADDR_WIDTH = 24;
localparam NUM_OF_JPG = 16;
localparam START_ADDR = 'h00000;
localparam ADDR_OFFSET = 'h00200;
reg r_arst;
reg r_sysclk;
reg r_next;
reg r_back;
reg r_interrupt;
reg r_flush;
wire w_WPn;
wire w_HOLDn;
wire w_miso;
wire w_DIO;
wire w_nss;
wire w_sclk;
wire w_mosi;
wire w_mosi_oe;
wire w_ready;
wire w_byte_en;
wire [7:0]w_byte;
assign w_WPn = 1'b1;
assign w_HOLDn = 1'b1;
assign w_ready = 1'b1;
spi_controller
#(
.SCLK_FREQ (SCLK_FREQ),
.ADDR_WIDTH (ADDR_WIDTH),
.NUM_OF_JPG (NUM_OF_JPG),
.START_ADDR (START_ADDR),
.ADDR_OFFSET (ADDR_OFFSET)
)
inst_spi_controller
(
.i_arst (r_arst),
.i_sysclk (r_sysclk),
.i_next (r_next),
.i_back (r_back),
.i_interrupt(r_interrupt),
.i_flush (r_flush),
.i_miso (w_miso),
.i_miso_1 (w_DIO),
.o_nss (w_nss),
.o_sclk (w_sclk),
.o_mosi (w_mosi),
.o_mosi_oe (w_mosi_oe),
.i_ready (w_ready),
.o_byte_en (w_byte_en),
.o_byte (w_byte)
);
W25Q32JV
inst_w25q32jv
(
.DIO (w_DIO),
.WPn (w_WPn),
.HOLDn (w_HOLDn),
.DO (w_miso),
.CSn (w_nss),
.CLK (w_sclk)
);
pullup(w_DIO);
pullup(w_miso);
assign w_DIO = (w_mosi_oe)?
w_mosi:1'bz;
initial
begin
r_arst <= 1'b1;
#10 r_arst <= 1'b0;
end
initial
begin
r_sysclk <= 1'b1;
forever
#2.5 r_sysclk <= ~r_sysclk;
end
always@(posedge r_arst or posedge r_sysclk)
begin
if (r_arst)
begin
r_next <= 1'b0;
r_back <= 1'b0;
r_interrupt <= 1'b0;
r_flush <= 1'b0;
end
else
begin
r_next <= 1'b0;
r_back <= 1'b0;
r_interrupt <= 1'b0;
r_flush <= 1'b0;
end
end
endmodule |
module runlength_shifter_tb();
localparam AMPLITUDE_PRECISION = 16;
reg r_arst;
reg r_sysclk;
reg r_we;
wire [19:0]w_eob;
wire [4:0]w_runlength[0:19];
wire [AMPLITUDE_PRECISION-1:0]w_B[0:19];
reg [4:0]r_ptr;
wire w_ready;
reg r_ready;
wire w_de;
wire [AMPLITUDE_PRECISION-1:0]o_B;
reg r_test_state_1P;
localparam s_test_0 = 1'b0;
localparam s_test_1 = 1'b1;
wire i_eob;
wire [4:0]i_runlength;
wire [AMPLITUDE_PRECISION-1:0]i_B;
assign i_eob = w_eob[r_ptr];
assign i_runlength = w_runlength[r_ptr];
assign i_B = w_B[r_ptr];
assign w_runlength[0] = 5'd0; assign w_eob[0] = 1'b0; assign w_B[0] = 16'h1;
assign w_runlength[1] = 5'd1; assign w_eob[1] = 1'b0; assign w_B[1] = 16'h2;
assign w_runlength[2] = 5'd0; assign w_eob[2] = 1'b0; assign w_B[2] = 16'h3;
assign w_runlength[3] = 5'd0; assign w_eob[3] = 1'b0; assign w_B[3] = 16'h4;
assign w_runlength[4] = 5'd0; assign w_eob[4] = 1'b0; assign w_B[4] = 16'h5;
assign w_runlength[5] = 5'd0; assign w_eob[5] = 1'b0; assign w_B[5] = 16'h6;
assign w_runlength[6] = 5'd0; assign w_eob[6] = 1'b0; assign w_B[6] = 16'h7;
assign w_runlength[7] = 5'd0; assign w_eob[7] = 1'b0; assign w_B[7] = 16'h8;
assign w_runlength[8] = 5'd0; assign w_eob[8] = 1'b0; assign w_B[8] = 16'h9;
assign w_runlength[9] = 5'd0; assign w_eob[9] = 1'b0; assign w_B[9] = 16'hA;
assign w_runlength[10] = 5'd0; assign w_eob[10] = 1'b0; assign w_B[10] = 16'hB;
assign w_runlength[11] = 5'd0; assign w_eob[11] = 1'b0; assign w_B[11] = 16'hC;
assign w_runlength[12] = 5'd0; assign w_eob[12] = 1'b0; assign w_B[12] = 16'hD;
assign w_runlength[13] = 5'd0; assign w_eob[13] = 1'b0; assign w_B[13] = 16'hE;
assign w_runlength[14] = 5'd0; assign w_eob[14] = 1'b0; assign w_B[14] = 16'hF;
assign w_runlength[15] = 5'd0; assign w_eob[15] = 1'b0; assign w_B[15] = 16'h10;
assign w_runlength[16] = 5'd0; assign w_eob[16] = 1'b0; assign w_B[16] = 16'h11;
assign w_runlength[17] = 5'd5; assign w_eob[17] = 1'b0; assign w_B[17] = 16'h12;
assign w_runlength[18] = 5'd0; assign w_eob[18] = 1'b0; assign w_B[18] = 16'h13;
assign w_runlength[19] = 5'd0; assign w_eob[19] = 1'b1; assign w_B[19] = 16'h14;
runlength_shifter
#(
.AMPLITUDE_PRECISION(AMPLITUDE_PRECISION)
)
inst_runlength_shifter
(
.i_arst (r_arst),
.i_sysclk (r_sysclk),
.i_we (r_we),
.i_eob (i_eob),
.i_runlength(i_runlength),
.i_B (i_B),
.o_ready (w_ready),
.i_ready (r_ready),
.o_de (w_de),
.o_B (o_B)
);
initial
begin
r_arst <= 1'b1;
#10 r_arst <= 1'b0;
end
initial
begin
r_sysclk <= 1'b1;
forever
#2.5 r_sysclk <= ~r_sysclk;
end
always@(posedge r_arst or posedge r_sysclk)
begin
if (r_arst)
begin
r_test_state_1P <= s_test_0;
r_ptr <= {5{1'b0}};
r_we <= 1'b1;
r_ready <= 1'b1;
end
else
begin
case (r_test_state_1P)
s_test_0:
begin
if (w_ready)
begin
r_ptr <= r_ptr+1'b1;
if (r_ptr == 5'd19)
begin
r_test_state_1P <= s_test_1;
r_ptr <= {5{1'b0}};
end
end
end
s_test_1:
begin
r_ready <= 1'b1;
if (w_ready)
begin
r_ready <= 1'b0;
r_ptr <= r_ptr+1'b1;
if (r_ptr == 5'd19)
begin
r_ptr <= r_ptr;
end
end
end
endcase
end
end
endmodule |
module line_buffer
#(
parameter VESA_STD = "VESA_1280X720_60FPS",
parameter Y_DEPTH = 8,
parameter U_DEPTH = 8,
parameter V_DEPTH = 8,
parameter X_LSB_CNT_WIDTH = 5,
parameter X_MSB_CNT_WIDTH = 6
)
(
input i_arst,
input i_pclk,
input i_vsync,
input i_hsync,
input i_de,
input [Y_DEPTH-1:0]i_y,
input [U_DEPTH-1:0]i_u,
input [V_DEPTH-1:0]i_v,
output o_vsync,
output o_hsync,
output o_de,
output [Y_DEPTH-1:0]o_y_11,
output [U_DEPTH-1:0]o_u_11,
output [V_DEPTH-1:0]o_v_11,
output [Y_DEPTH-1:0]o_y_00,
output [U_DEPTH-1:0]o_u_00,
output [V_DEPTH-1:0]o_v_00,
output [Y_DEPTH-1:0]o_y_01,
output [U_DEPTH-1:0]o_u_01,
output [V_DEPTH-1:0]o_v_01,
output [X_MSB_CNT_WIDTH+X_LSB_CNT_WIDTH-1:0]o_x
);
localparam HOR_SYNC_POLARITY = `HOR_SYNC_POLARITY;
localparam VER_SYNC_POLARITY = `VER_SYNC_POLARITY;
wire c_act_vs_por;
wire c_ina_vs_por;
wire c_act_hs_por;
wire c_ina_hs_por;
wire c_act_de_por;
wire c_ina_de_por;
reg r_vsync_1P;
reg r_hsync1_1P;
reg r_hsync2_1P;
reg r_de_1P;
reg [Y_DEPTH-1:0]r_y_1P;
reg [Y_DEPTH-1:0]r_u_1P;
reg [Y_DEPTH-1:0]r_v_1P;
reg [X_LSB_CNT_WIDTH-1:0]r_addr1_lsb_1P;
reg [X_MSB_CNT_WIDTH-1:0]r_addr1_msb_1P;
reg r_addr1_sel_1P;
reg [X_LSB_CNT_WIDTH-1:0]r_addr2_lsb_1P;
reg [X_MSB_CNT_WIDTH-1:0]r_addr2_msb_1P;
reg r_addr2_sel_1P;
reg r_vsync_2P;
reg r_hsync1_2P;
reg r_hsync2_2P;
reg r_de_2P;
reg [Y_DEPTH-1:0]r_y_01_2P;
reg [U_DEPTH-1:0]r_u_01_2P;
reg [V_DEPTH-1:0]r_v_01_2P;
reg [X_LSB_CNT_WIDTH-1:0]r_addr2_lsb_2P;
reg [X_MSB_CNT_WIDTH-1:0]r_addr2_msb_2P;
wire [Y_DEPTH-1:0]w_y_11_2P;
wire [U_DEPTH-1:0]w_u_11_2P;
wire [V_DEPTH-1:0]w_v_11_2P;
wire [Y_DEPTH-1:0]w_y_00_2P;
wire [U_DEPTH-1:0]w_u_00_2P;
wire [V_DEPTH-1:0]w_v_00_2P;
generate
if (HOR_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_hs_por = 1'b0;
assign c_ina_hs_por = 1'b1;
end
else
begin
assign c_act_hs_por = 1'b1;
assign c_ina_hs_por = 1'b0;
end
if (VER_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_vs_por = 1'b0;
assign c_ina_vs_por = 1'b1;
end
else
begin
assign c_act_vs_por = 1'b1;
assign c_ina_vs_por = 1'b0;
end
endgenerate
assign c_act_de_por = 1'b1;
assign c_ina_de_por = 1'b0;
true_dual_port_ram
#(
.DATA_WIDTH(Y_DEPTH),
.ADDR_WIDTH(12),
.WRITE_MODE_1("READ_FIRST"),
.WRITE_MODE_2("READ_FIRST"),
.OUTPUT_REG_1("FALSE"),
.OUTPUT_REG_2("FALSE"),
.RAM_INIT_FILE(""),
.RAM_INIT_RADIX("HEX")
)
inst_y_buffer
(
.we1(1'b1),
.clka(i_pclk),
.din1(r_y_1P),
.addr1({r_addr1_sel_1P, r_addr1_msb_1P, r_addr1_lsb_1P}),
.dout1(w_y_11_2P),
.we2(1'b0),
.clkb(i_pclk),
.din2(r_y_1P),
.addr2({r_addr2_sel_1P, r_addr2_msb_1P, r_addr2_lsb_1P}),
.dout2(w_y_00_2P)
);
/*
true_dual_port_ram
#(
.DATA_WIDTH(U_DEPTH),
.ADDR_WIDTH(11),
.WRITE_MODE_1("READ_FIRST"),
.WRITE_MODE_2("READ_FIRST"),
.OUTPUT_REG_1("FALSE"),
.OUTPUT_REG_2("FALSE"),
.RAM_INIT_FILE("")
)
inst_u_buffer
(
.we1(1'b1),
.clka(i_pclk),
.din1(r_u_1P),
.addr1({r_addr1_sel_1P, r_addr1_msb_1P, r_addr1_lsb_1P}),
.dout1(w_u_11_2P),
.we2(1'b0),
.clkb(i_pclk),
.din2(r_u_1P),
.addr2({r_addr2_sel_1P, r_addr2_msb_1P, r_addr2_lsb_1P}),
.dout2(w_u_00_2P)
);
true_dual_port_ram
#(
.DATA_WIDTH(V_DEPTH),
.ADDR_WIDTH(11),
.WRITE_MODE_1("READ_FIRST"),
.WRITE_MODE_2("READ_FIRST"),
.OUTPUT_REG_1("FALSE"),
.OUTPUT_REG_2("FALSE"),
.RAM_INIT_FILE("")
)
inst_v_buffer
(
.we1(1'b1),
.clka(i_pclk),
.din1(r_v_1P),
.addr1({r_addr1_sel_1P, r_addr1_msb_1P, r_addr1_lsb_1P}),
.dout1(w_u_11_2P),
.we2(1'b0),
.clkb(i_pclk),
.din2(r_u_1P),
.addr2({r_addr2_sel_1P, r_addr2_msb_1P, r_addr2_lsb_1P}),
.dout2(w_u_00_2P)
);
*/
assign w_u_11_2P[U_DEPTH-1] = 1'b1;
assign w_u_11_2P[U_DEPTH-2:0] = {U_DEPTH-1{1'b0}};
assign w_v_11_2P[V_DEPTH-1] = 1'b1;
assign w_v_11_2P[V_DEPTH-2:0] = {U_DEPTH-1{1'b0}};
assign w_u_00_2P[U_DEPTH-1] = 1'b1;
assign w_u_00_2P[U_DEPTH-2:0] = {U_DEPTH-1{1'b0}};
assign w_v_00_2P[V_DEPTH-1] = 1'b1;
assign w_v_00_2P[V_DEPTH-2:0] = {U_DEPTH-1{1'b0}};
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_vsync_1P <= c_ina_vs_por;
r_hsync1_1P <= c_ina_hs_por;
r_hsync2_1P <= c_ina_hs_por;
r_de_1P <= c_ina_de_por;
r_y_1P <= {Y_DEPTH{1'b0}};
r_u_1P <= {U_DEPTH{1'b0}};
r_v_1P <= {V_DEPTH{1'b0}};
r_addr1_lsb_1P <= {X_LSB_CNT_WIDTH{1'b0}};
r_addr1_msb_1P <= {X_MSB_CNT_WIDTH{1'b0}};
r_addr1_sel_1P <= 1'b0;
r_addr2_lsb_1P <= {X_LSB_CNT_WIDTH{1'b0}};
r_addr2_msb_1P <= {X_MSB_CNT_WIDTH{1'b0}};
r_addr2_sel_1P <= 1'b1;
r_vsync_2P <= c_ina_vs_por;
r_hsync1_2P <= c_ina_hs_por;
r_hsync2_2P <= c_ina_hs_por;
r_de_2P <= c_ina_de_por;
r_y_01_2P <= {Y_DEPTH{1'b0}};
r_u_01_2P <= {U_DEPTH{1'b0}};
r_v_01_2P <= {V_DEPTH{1'b0}};
end
else
begin
r_vsync_1P <= i_vsync;
r_hsync1_1P <= i_hsync;
r_hsync2_1P <= i_hsync;
r_de_1P <= i_de;
r_y_1P <= i_y;
r_u_1P <= i_u;
r_v_1P <= i_v;
r_addr1_lsb_1P <= r_addr1_lsb_1P+1'b1;
r_addr2_lsb_1P <= r_addr2_lsb_1P+1'b1;
if (r_addr1_lsb_1P == {X_LSB_CNT_WIDTH{1'b1}})
r_addr1_msb_1P <= r_addr1_msb_1P+1'b1;
if (r_addr2_lsb_1P == {X_LSB_CNT_WIDTH{1'b1}})
r_addr2_msb_1P <= r_addr2_msb_1P+1'b1;
if (r_hsync1_1P && ~r_hsync1_2P)
begin
r_addr1_lsb_1P <= {X_LSB_CNT_WIDTH{1'b0}};
r_addr1_msb_1P <= {X_MSB_CNT_WIDTH{1'b0}};
r_addr1_sel_1P <= ~r_addr1_sel_1P;
end
if (r_hsync2_1P && ~r_hsync2_2P)
begin
r_addr2_lsb_1P <= {X_LSB_CNT_WIDTH{1'b0}};
r_addr2_msb_1P <= {X_MSB_CNT_WIDTH{1'b0}};
r_addr2_sel_1P <= ~r_addr2_sel_1P;
end
r_vsync_2P <= r_vsync_1P;
r_hsync1_2P <= r_hsync1_1P;
r_hsync2_2P <= r_hsync2_1P;
r_de_2P <= r_de_1P;
r_y_01_2P <= r_y_1P;
r_u_01_2P <= r_u_1P;
r_v_01_2P <= r_v_1P;
r_addr2_lsb_2P <= r_addr2_lsb_1P;
r_addr2_msb_2P <= r_addr2_msb_1P;
end
end
assign o_vsync = r_vsync_2P;
assign o_hsync = r_hsync2_2P;
assign o_de = r_de_2P;
assign o_y_11 = w_y_11_2P;
assign o_u_11 = w_u_11_2P;
assign o_v_11 = w_v_11_2P;
assign o_y_00 = w_y_00_2P;
assign o_u_00 = w_u_00_2P;
assign o_v_00 = w_v_00_2P;
assign o_y_01 = r_y_01_2P;
assign o_u_01 = r_u_01_2P;
assign o_v_01 = r_v_01_2P;
assign o_x = {r_addr2_msb_2P, r_addr2_lsb_2P};
endmodule |
module display_fsm
#(
parameter TIMER_WIDTH = 16
)
(
input i_arst,
input i_osc,
input i_pclk,
input i_sw_n,
input i_pll_locked,
output o_srst,
output o_pll_locked,
output o_posterize_en,
output [1:0]o_display_sel
);
localparam c_idle_streaming = 3'b100;
localparam c_full_sobel = 3'b101;
localparam c_half_sobel = 3'b110;
localparam c_half_posterize = 3'b000;
localparam s_m_idle_streaming = 3'b000;
localparam s_m_full_sobel = 3'b001;
localparam s_m_half_sobel = 3'b010;
localparam s_m_half_posterize = 3'b011;
localparam s_a_idle_streaming = 3'b100;
localparam s_a_full_sobel = 3'b101;
localparam s_a_half_sobel = 3'b110;
localparam s_a_half_posterize = 3'b111;
reg [TIMER_WIDTH-1:0]r_timer_osc_1P = {TIMER_WIDTH{1'b0}};
reg r_timer_en_osc_2P = 1'b0;
reg r_timer_en_osc_3P = 1'b0;
reg r_timer_msb_osc_2P = 1'b0;
reg r_pll_locked_osc_1P = 1'b0;
reg r_pll_locked_osc_2P = 1'b0;
reg r_pll_locked_osc_3P = 1'b0;
reg r_pll_locked_osc_4P = 1'b0;
reg r_pll_locked_osc_5P = 1'b0;
reg r_srst_osc_1P = 1'b0;
reg [2:0]r_display_state_1P;
reg r_sw_n_pclk_1P;
reg r_timer_msb_pclk_1P;
reg [2:0]r_display_ctrl_pclk_1P;
reg r_timer_en_pclk_1P;
reg r_sw_n_pclk_2P;
reg r_sw_n_fe_pclk_2P;
reg r_timer_msb_pclk_2P;
reg r_timer_msb_fe_pclk_2P;
//always@(posedge i_arst or posedge i_osc)
always@(posedge i_osc)
begin
// if (i_arst)
// begin
// r_timer_osc_1P <= {TIMER_WIDTH{1'b0}};
// r_timer_en_osc_2P <= 1'b0;
// r_timer_en_osc_3P <= 1'b0;
// r_timer_msb_osc_2P <= 1'b0;
// r_pll_locked_osc_1P <= 1'b0;
// r_pll_locked_osc_2P <= 1'b0;
// r_srst_osc_1P <= 1'b0;
// end
// else
begin
r_timer_osc_1P <= r_timer_osc_1P+1'b1;
if (r_timer_en_osc_2P & ~r_timer_en_osc_3P)
r_timer_osc_1P <= {TIMER_WIDTH{1'b0}};
r_timer_en_osc_2P <= r_timer_en_pclk_1P;
r_timer_en_osc_3P <= r_timer_en_osc_2P;
r_timer_msb_osc_2P <= r_timer_osc_1P[TIMER_WIDTH-1];
if (~r_timer_osc_1P[TIMER_WIDTH-1] & r_timer_msb_osc_2P)
begin
r_pll_locked_osc_1P <= i_pll_locked;
r_pll_locked_osc_2P <= r_pll_locked_osc_1P;
r_pll_locked_osc_3P <= r_pll_locked_osc_2P;
r_pll_locked_osc_4P <= r_pll_locked_osc_3P;
r_pll_locked_osc_5P <= r_pll_locked_osc_4P;
end
r_srst_osc_1P <= 1'b0;
// if (r_pll_locked_osc_4P & ~r_pll_locked_osc_5P)
if (r_pll_locked_osc_1P & ~r_pll_locked_osc_2P)
r_srst_osc_1P <= 1'b1;
end
end
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_display_state_1P <= s_m_idle_streaming;
r_sw_n_pclk_1P <= 1'b1;
r_timer_msb_pclk_1P <= 1'b0;
r_display_ctrl_pclk_1P <= c_idle_streaming;
r_timer_en_pclk_1P <= 1'b0;
r_sw_n_pclk_2P <= 1'b1;
r_sw_n_fe_pclk_2P <= 1'b0;
r_timer_msb_pclk_2P <= 1'b0;
r_timer_msb_fe_pclk_2P <= 1'b0;
end
else
begin
r_sw_n_pclk_1P <= i_sw_n;
r_timer_msb_pclk_1P <= r_timer_osc_1P[TIMER_WIDTH-1];
r_sw_n_pclk_2P <= r_sw_n_pclk_1P;
r_timer_msb_pclk_2P <= r_timer_msb_pclk_1P;
r_sw_n_fe_pclk_2P <= ~r_sw_n_pclk_1P & r_sw_n_pclk_2P;
r_timer_msb_fe_pclk_2P <= ~r_timer_msb_pclk_1P & r_timer_msb_pclk_2P;
case (r_display_state_1P)
s_m_idle_streaming:
begin
if (r_sw_n_fe_pclk_2P)
begin
r_display_state_1P <= s_m_full_sobel;
r_display_ctrl_pclk_1P <= c_full_sobel;
end
end
s_m_full_sobel:
begin
if (r_sw_n_fe_pclk_2P)
begin
r_display_state_1P <= s_m_half_sobel;
r_display_ctrl_pclk_1P <= c_half_sobel;
end
end
s_m_half_sobel:
begin
if (r_sw_n_fe_pclk_2P)
begin
r_display_state_1P <= s_m_half_posterize;
r_display_ctrl_pclk_1P <= c_half_posterize;
end
end
s_m_half_posterize:
begin
if (r_sw_n_fe_pclk_2P)
begin
r_display_state_1P <= s_a_idle_streaming;
r_display_ctrl_pclk_1P <= c_idle_streaming;
r_timer_en_pclk_1P <= 1'b1;
end
end
s_a_idle_streaming:
begin
if (r_sw_n_fe_pclk_2P)
begin
r_display_state_1P <= s_m_idle_streaming;
r_display_ctrl_pclk_1P <= c_idle_streaming;
r_timer_en_pclk_1P <= 1'b0;
end
else if (r_timer_msb_fe_pclk_2P)
begin
r_display_state_1P <= s_a_full_sobel;
r_display_ctrl_pclk_1P <= c_full_sobel;
end
end
s_a_full_sobel:
begin
if (r_sw_n_fe_pclk_2P)
begin
r_display_state_1P <= s_m_idle_streaming;
r_display_ctrl_pclk_1P <= c_idle_streaming;
r_timer_en_pclk_1P <= 1'b0;
end
else if (r_timer_msb_fe_pclk_2P)
begin
r_display_state_1P <= s_a_half_sobel;
r_display_ctrl_pclk_1P <= c_half_sobel;
end
end
s_a_half_sobel:
begin
if (r_sw_n_fe_pclk_2P)
begin
r_display_state_1P <= s_m_idle_streaming;
r_display_ctrl_pclk_1P <= c_idle_streaming;
r_timer_en_pclk_1P <= 1'b0;
end
else if (r_timer_msb_fe_pclk_2P)
begin
r_display_state_1P <= s_a_half_posterize;
r_display_ctrl_pclk_1P <= c_half_posterize;
end
end
s_a_half_posterize:
begin
if (r_sw_n_fe_pclk_2P)
begin
r_display_state_1P <= s_m_idle_streaming;
r_display_ctrl_pclk_1P <= c_idle_streaming;
r_timer_en_pclk_1P <= 1'b0;
end
else if (r_timer_msb_fe_pclk_2P)
begin
r_display_state_1P <= s_a_idle_streaming;
r_display_ctrl_pclk_1P <= c_idle_streaming;
end
end
endcase
end
end
assign o_srst = r_srst_osc_1P;
assign o_pll_locked = r_pll_locked_osc_2P;
assign o_posterize_en = r_display_ctrl_pclk_1P[2];
assign o_display_sel = r_display_ctrl_pclk_1P[1:0];
endmodule |
module multi_n1_ext2
#(
parameter D_WIDTH = 8
)
(
input i_arst,
input i_clk,
input [D_WIDTH-1:0]i_d,
output [D_WIDTH+2-1:0]o_q
);
reg [D_WIDTH+2-1:0]r_q_1P;
wire [D_WIDTH+2-1:0]w_d_0P;
assign w_d_0P = {2'b00, i_d};
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_q_1P <= {D_WIDTH+2{1'b0}};
else
r_q_1P <= ~w_d_0P+1'b1;
end
assign o_q = r_q_1P;
endmodule |
module multi_p1_ext2
#(
parameter D_WIDTH = 8
)
(
input i_arst,
input i_clk,
input [D_WIDTH-1:0]i_d,
output [D_WIDTH+2-1:0]o_q
);
reg [D_WIDTH+2-1:0]r_q_1P;
wire [D_WIDTH+2-1:0]w_d_0P;
assign w_d_0P = {2'b00, i_d};
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_q_1P <= {D_WIDTH+2{1'b0}};
else
r_q_1P <= w_d_0P;
end
assign o_q = r_q_1P;
endmodule |
module multi_p8_ext5
#(
parameter D_WIDTH = 8
)
(
input i_arst,
input i_clk,
input [D_WIDTH-1:0]i_d,
output [D_WIDTH+5-1:0]o_q
);
reg [D_WIDTH+5-1:0]r_q_1P;
wire [D_WIDTH+5-1:0]w_d_0P;
assign w_d_0P = {2'b0, i_d, 3'b000};
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_q_1P <= {D_WIDTH+5{1'b0}};
else
r_q_1P <= w_d_0P;
end
assign o_q = r_q_1P;
endmodule |
module filter_size
#(
parameter VESA_STD = "VESA_STD",
parameter X_START = 0,
parameter Y_START = 0,
parameter X_END = 640,
parameter Y_END = 720,
parameter X_LSB_CNT_WIDTH = 4,
parameter X_MSB_CNT_WIDTH = 6,
parameter Y_LSB_CNT_WIDTH = 4,
parameter Y_MSB_CNT_WIDTH = 6
)
(
input i_arst,
input i_pclk,
input i_hsync,
output o_hsync,
output o_x_en
);
localparam HOR_SYNC_POLARITY = `HOR_SYNC_POLARITY;
localparam VER_SYNC_POLARITY = `VER_SYNC_POLARITY;
wire c_act_vs_por;
wire c_ina_vs_por;
wire c_act_hs_por;
wire c_ina_hs_por;
reg r_hsync_1P;
reg [X_LSB_CNT_WIDTH-1:0]r_x_lsb_cnt_1P;
reg [X_MSB_CNT_WIDTH-1:0]r_x_msb_cnt_1P;
reg r_x_en_1P;
reg r_x_done_1P;
reg r_hsync_posedge_1P;
//reg r_hsync_2P;
reg r_x_en_2P;
reg r_hsync_posedge_2P;
//reg r_hsync_3P;
reg r_x_en_3P;
reg r_hsync_posedge_3P;
generate
if (HOR_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_hs_por = 1'b0;
assign c_ina_hs_por = 1'b1;
end
else
begin
assign c_act_hs_por = 1'b1;
assign c_ina_hs_por = 1'b0;
end
if (VER_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_vs_por = 1'b0;
assign c_ina_vs_por = 1'b1;
end
else
begin
assign c_act_vs_por = 1'b1;
assign c_ina_vs_por = 1'b0;
end
endgenerate
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_hsync_1P <= c_ina_hs_por;
r_x_lsb_cnt_1P <= {X_LSB_CNT_WIDTH{1'b0}};
r_x_msb_cnt_1P <= {X_MSB_CNT_WIDTH{1'b0}};
r_x_en_1P <= 1'b0;
r_x_done_1P <= 1'b0;
r_hsync_posedge_1P <= 1'b0;
// r_hsync_2P <= 1'b0;
r_x_en_2P <= 1'b0;
r_hsync_posedge_2P <= 1'b0;
// r_hsync_3P <= 1'b0;
r_x_en_3P <= 1'b0;
r_hsync_posedge_3P <= 1'b0;
end
else
begin
r_hsync_1P <= i_hsync;
r_hsync_posedge_1P <= i_hsync & ~r_hsync_1P;
// r_hsync_2P <= r_hsync_1P;
r_x_en_2P <= r_x_en_1P;
r_hsync_posedge_2P <= r_hsync_posedge_1P;
// r_hsync_3P <= r_hsync_2P;
r_x_en_3P <= r_x_en_2P;
r_hsync_posedge_3P <= r_hsync_posedge_2P;
r_x_lsb_cnt_1P <= r_x_lsb_cnt_1P+1'b1;
if (r_x_lsb_cnt_1P == {X_LSB_CNT_WIDTH{1'b1}})
r_x_msb_cnt_1P <= r_x_msb_cnt_1P+1'b1;
if (r_x_en_1P)
begin
if (r_x_msb_cnt_1P[5] & r_x_msb_cnt_1P[3]) // 640
begin
r_x_en_1P <= 1'b0;
r_x_done_1P <= 1'b1;
end
end
else if (r_x_msb_cnt_1P[5:4] == 2'b01 && r_x_lsb_cnt_1P[1:0] == 3'b11) // 259
begin
r_x_lsb_cnt_1P <= {X_LSB_CNT_WIDTH{1'b0}};
// r_x_msb_cnt_1P <= {X_MSB_CNT_WIDTH{1'b0}};
// r_x_en_1P <= 1'b1;
r_x_en_1P <= ~r_x_done_1P;
end
if (i_hsync & ~r_hsync_1P)
begin
r_x_lsb_cnt_1P <= {X_LSB_CNT_WIDTH{1'b0}};
// r_x_msb_cnt_1P <= {X_MSB_CNT_WIDTH{1'b0}};
// r_x_en_1P <= 1'b0;
// r_x_done_1P <= 1'b0;
end
// if (r_hsync_2P & ~r_hsync_3P)
if (r_hsync_posedge_2P)
begin
// r_x_msb_cnt_1P <= {X_MSB_CNT_WIDTH{1'b0}};
r_x_msb_cnt_1P[X_MSB_CNT_WIDTH/2-1:0] <= {X_MSB_CNT_WIDTH/2{1'b0}};
r_x_en_1P <= 1'b0;
r_x_done_1P <= 1'b0;
end
else if (r_hsync_posedge_3P)
begin
r_x_msb_cnt_1P[X_MSB_CNT_WIDTH-1:X_MSB_CNT_WIDTH/2] <= {X_MSB_CNT_WIDTH/2{1'b0}};
end
else if (r_x_en_2P & ~r_x_en_3P)
begin
r_x_msb_cnt_1P <= {X_MSB_CNT_WIDTH{1'b0}};
// r_x_en_1P <= 1'b0;
// r_x_done_1P <= 1'b0;
end
end
end
assign o_hsync = r_hsync_1P;
assign o_x_en = r_x_en_1P;
endmodule |
module vga_controller
#(
parameter VESA_STD = "VESA_1280X720_60FPS",
parameter R_DEPTH = 6,
parameter G_DEPTH = 6,
parameter B_DEPTH = 6
)
(
input i_arst,
input i_pclk,
input i_vs,
input i_hs,
input i_de,
input [R_DEPTH-1:0]i_r,
input [G_DEPTH-1:0]i_g,
input [B_DEPTH-1:0]i_b,
output o_vga_vs,
output o_vga_hs,
output o_vga_de,
output [R_DEPTH-1:0]o_vga_r,
output [G_DEPTH-1:0]o_vga_g,
output [B_DEPTH-1:0]o_vga_b
);
localparam HOR_SYNC_POLARITY = `HOR_SYNC_POLARITY;
localparam VER_SYNC_POLARITY = `VER_SYNC_POLARITY;
wire c_act_vs_por;
wire c_ina_vs_por;
wire c_act_hs_por;
wire c_ina_hs_por;
wire c_act_de_por;
wire c_ina_de_por;
reg r_vs_1P;
reg r_hs_1P;
reg r_de_r_1P;
reg r_de_g_1P;
reg r_de_b_1P;
reg [R_DEPTH-1:0]r_r_1P;
reg [G_DEPTH-1:0]r_g_1P;
reg [B_DEPTH-1:0]r_b_1P;
reg r_vs_2P;
reg r_hs_2P;
reg r_de_2P;
reg [R_DEPTH-1:0]r_r_2P;
reg [G_DEPTH-1:0]r_g_2P;
reg [B_DEPTH-1:0]r_b_2P;
generate
if (HOR_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_hs_por = 1'b0;
assign c_ina_hs_por = 1'b1;
end
else
begin
assign c_act_hs_por = 1'b1;
assign c_ina_hs_por = 1'b0;
end
if (VER_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_vs_por = 1'b0;
assign c_ina_vs_por = 1'b1;
end
else
begin
assign c_act_vs_por = 1'b1;
assign c_ina_vs_por = 1'b0;
end
endgenerate
assign c_act_de_por = 1'b1;
assign c_ina_de_por = 1'b0;
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_vs_1P <= c_ina_vs_por;
r_hs_1P <= c_ina_hs_por;
r_de_r_1P <= c_ina_de_por;
r_de_g_1P <= c_ina_de_por;
r_de_b_1P <= c_ina_de_por;
r_r_1P <= {R_DEPTH{1'b0}};
r_g_1P <= {G_DEPTH{1'b0}};
r_b_1P <= {B_DEPTH{1'b0}};
r_vs_2P <= c_ina_vs_por;
r_hs_2P <= c_ina_hs_por;
r_de_2P <= c_ina_de_por;
r_r_2P <= {R_DEPTH{1'b0}};
r_g_2P <= {G_DEPTH{1'b0}};
r_b_2P <= {B_DEPTH{1'b0}};
end
else
begin
r_vs_1P <= i_vs;
r_hs_1P <= i_hs;
r_de_r_1P <= i_de;
r_de_g_1P <= i_de;
r_de_b_1P <= i_de;
r_r_1P <= i_r;
r_g_1P <= i_g;
r_b_1P <= i_b;
r_vs_2P <= r_vs_1P;
r_hs_2P <= r_hs_1P;
r_de_2P <= r_de_r_1P;
if (r_de_r_1P)
r_r_2P <= r_r_1P;
else
r_r_2P <= {R_DEPTH{1'b0}};
if (r_de_g_1P)
r_g_2P <= r_g_1P;
else
r_g_2P <= {G_DEPTH{1'b0}};
if (r_de_b_1P)
r_b_2P <= r_b_1P;
else
r_b_2P <= {B_DEPTH{1'b0}};
end
end
assign o_vga_vs = r_vs_2P;
assign o_vga_hs = r_hs_2P;
assign o_vga_de = r_de_2P;
assign o_vga_r = r_r_2P;
assign o_vga_g = r_g_2P;
assign o_vga_b = r_b_2P;
endmodule |
module sobel_feldman
#(
parameter Y_DEPTH = 8
)
(
input i_arst,
input i_pclk,
input [Y_DEPTH-1:0]i_pixel_11_01,
input [Y_DEPTH-1:0]i_pixel_00_01,
input [Y_DEPTH-1:0]i_pixel_01_01,
output [Y_DEPTH-1:0]o_pixel
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// x -1 0 +1 y
//
// -1 0 1 -1
// -2 0 2 0
// -1 0 1 +1
//
// -1 -2 -1 -1
// 0 0 0 0
// 1 2 1 +1
//
// PL_11_11_2P PL_11_00_1P PL_11_01_0P
// PL_00_11_2P PL_00_00_1P PL_00_01_0P
// PL_01_11_2P PL_01_00_1P PL_01_01_0P
//
// GX_11_11_3P GX_11_00_2P GX_11_01_1P
// GX_00_11_3P GX_00_00_2P GX_00_01_1P
// GX_01_11_3P GX_01_00_2P GX_01_01_1P
// 0
// GXS_11_4P GX_11_01_2P GXS_11_5P
// GXS_00_4P GX_00_01_2P GXS_00_5P GXS_00_6P GXS_00_7P
// GXS_01_4P GX_01_01_2P GXS_01_5P GXS_01_6P
//
// GY_11_11_3P GY_11_00_2P GY_11_01_1P
// GY_00_11_3P GY_00_00_2P GY_00_01_1P 0
// GY_01_11_3P GY_01_00_2P GY_01_01_1P
//
// GYS_11_4P GY_11_01_2P GYS_11_5P
// GYS_00_4P GY_00_01_2P GYS_00_5P GYS_00_6P GYS_00_7P
// GYS_01_4P GY_01_01_2P GYS_01_5P GYS_01_6P
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [Y_DEPTH-1:0]r_p_11_00_1P, r_p_11_11_2P;
reg [Y_DEPTH-1:0]r_p_00_00_1P, r_p_00_11_2P;
reg [Y_DEPTH-1:0]r_p_01_00_1P, r_p_01_11_2P;
reg [Y_DEPTH+2-1:0]r_gx_11_01_2P;
reg [Y_DEPTH+2-1:0]r_gx_00_01_2P;
reg [Y_DEPTH+2-1:0]r_gx_01_01_2P;
reg [Y_DEPTH+2-1:0]r_gxs_11_4P, r_gxs_11_5P;
reg [Y_DEPTH+2-1:0]r_gxs_00_4P, r_gxs_00_5P, r_gxs_00_6P, r_gxs_00_7P;
reg [Y_DEPTH+2-1:0]r_gxs_01_4P, r_gxs_01_5P, r_gxs_01_6P;
reg [Y_DEPTH+2-1:0]r_gy_11_01_2P;
reg [Y_DEPTH+2-1:0]r_gy_00_01_2P;
reg [Y_DEPTH+2-1:0]r_gy_01_01_2P;
reg [Y_DEPTH+2-1:0]r_gys_11_4P, r_gys_11_5P;
reg [Y_DEPTH+2-1:0]r_gys_00_4P, r_gys_00_5P, r_gys_00_6P, r_gys_00_7P;
reg [Y_DEPTH+2-1:0]r_gys_01_4P, r_gys_01_5P, r_gys_01_6P;
reg [Y_DEPTH+2-1:0]r_gxs_00_8P;
reg [Y_DEPTH+2-1:0]r_gys_00_8P;
reg [Y_DEPTH+2-1:0]r_g_9P;
reg [Y_DEPTH-1:0]r_g_10P;
wire [Y_DEPTH+2-1:0]w_gx_11_01_1P, w_gx_11_00_2P, w_gx_11_11_3P;
wire [Y_DEPTH+2-1:0]w_gx_00_01_1P, w_gx_00_00_2P, w_gx_00_11_3P;
wire [Y_DEPTH+2-1:0]w_gx_01_01_1P, w_gx_01_00_2P, w_gx_01_11_3P;
wire [Y_DEPTH+2-1:0]w_gy_11_01_1P, w_gy_11_00_2P, w_gy_11_11_3P;
wire [Y_DEPTH+2-1:0]w_gy_00_01_1P, w_gy_00_00_2P, w_gy_00_11_3P;
wire [Y_DEPTH+2-1:0]w_gy_01_01_1P, w_gy_01_00_2P, w_gy_01_11_3P;
assign w_gx_11_00_2P = {Y_DEPTH+2{1'b0}};
assign w_gx_00_00_2P = {Y_DEPTH+2{1'b0}};
assign w_gx_01_00_2P = {Y_DEPTH+2{1'b0}};
assign w_gy_00_01_1P = {Y_DEPTH+2{1'b0}};
assign w_gy_00_00_2P = {Y_DEPTH+2{1'b0}};
assign w_gy_00_11_3P = {Y_DEPTH+2{1'b0}};
////////////////////////////////////////////////////////////////
// x - 1
multi_n1_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gx_11_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_11_11_2P),
.o_q (w_gx_11_11_3P)
);
multi_n2_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gx_00_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_00_11_2P),
.o_q (w_gx_00_11_3P)
);
multi_n1_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gx_01_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_01_11_2P),
.o_q (w_gx_01_11_3P)
);
////////////////////////////////////////////////////////////////
// x + 1
multi_p1_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gx_11_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_11_01),
.o_q (w_gx_11_01_1P)
);
multi_p2_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gx_00_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_00_01),
.o_q (w_gx_00_01_1P)
);
multi_p1_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gx_01_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_01_01),
.o_q (w_gx_01_01_1P)
);
////////////////////////////////////////////////////////////////
// y - 1
multi_n1_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gy_11_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_11_11_2P),
.o_q (w_gy_11_11_3P)
);
multi_n2_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gy_11_00
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_11_00_1P),
.o_q (w_gy_11_00_2P)
);
multi_n1_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gy_11_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_11_01),
.o_q (w_gy_11_01_1P)
);
////////////////////////////////////////////////////////////////
// y + 1
multi_p1_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gy_01_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_01_11_2P),
.o_q (w_gy_01_11_3P)
);
multi_p2_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gy_01_00
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_01_00_1P),
.o_q (w_gy_01_00_2P)
);
multi_p1_ext2
#(
.D_WIDTH(Y_DEPTH)
)
inst_gy_01_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_01_01),
.o_q (w_gy_01_01_1P)
);
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_p_11_00_1P <= {Y_DEPTH{1'b0}};
r_p_11_11_2P <= {Y_DEPTH{1'b0}};
r_p_00_00_1P <= {Y_DEPTH{1'b0}};
r_p_00_11_2P <= {Y_DEPTH{1'b0}};
r_p_01_00_1P <= {Y_DEPTH{1'b0}};
r_p_01_11_2P <= {Y_DEPTH{1'b0}};
////////////////////////////////
r_gx_11_01_2P <= {Y_DEPTH+2{1'b0}};
r_gx_00_01_2P <= {Y_DEPTH+2{1'b0}};
r_gx_01_01_2P <= {Y_DEPTH+2{1'b0}};
r_gxs_11_4P <= {Y_DEPTH+2{1'b0}};
r_gxs_00_4P <= {Y_DEPTH+2{1'b0}};
r_gxs_01_4P <= {Y_DEPTH+2{1'b0}};
r_gxs_11_5P <= {Y_DEPTH+2{1'b0}};
r_gxs_00_5P <= {Y_DEPTH+2{1'b0}};
r_gxs_01_5P <= {Y_DEPTH+2{1'b0}};
r_gxs_00_6P <= {Y_DEPTH+2{1'b0}};
r_gxs_01_6P <= {Y_DEPTH+2{1'b0}};
r_gxs_00_7P <= {Y_DEPTH+2{1'b0}};
////////////////////////////////
r_gy_11_01_2P <= {Y_DEPTH+2{1'b0}};
r_gy_00_01_2P <= {Y_DEPTH+2{1'b0}};
r_gy_01_01_2P <= {Y_DEPTH+2{1'b0}};
r_gys_11_4P <= {Y_DEPTH+2{1'b0}};
r_gys_00_4P <= {Y_DEPTH+2{1'b0}};
r_gys_01_4P <= {Y_DEPTH+2{1'b0}};
r_gys_11_5P <= {Y_DEPTH+2{1'b0}};
r_gys_00_5P <= {Y_DEPTH+2{1'b0}};
r_gys_01_5P <= {Y_DEPTH+2{1'b0}};
r_gys_00_6P <= {Y_DEPTH+2{1'b0}};
r_gys_01_6P <= {Y_DEPTH+2{1'b0}};
r_gys_00_7P <= {Y_DEPTH+2{1'b0}};
////////////////////////////////
r_gxs_00_8P <= {Y_DEPTH+2{1'b0}};
r_gys_00_8P <= {Y_DEPTH+2{1'b0}};
r_g_9P <= {Y_DEPTH+2{1'b0}};
r_g_10P <= {Y_DEPTH{1'b0}};
end
else
begin
r_p_11_00_1P <= i_pixel_11_01;
r_p_00_00_1P <= i_pixel_00_01;
r_p_01_00_1P <= i_pixel_01_01;
r_p_11_11_2P <= r_p_11_00_1P;
r_p_00_11_2P <= r_p_00_00_1P;
r_p_01_11_2P <= r_p_01_00_1P;
////////////////////////////////
r_gx_11_01_2P <= w_gx_11_01_1P;
r_gx_00_01_2P <= w_gx_00_01_1P;
r_gx_01_01_2P <= w_gx_01_01_1P;
////////////////////////////////
r_gxs_11_4P <= w_gx_11_00_2P + w_gx_11_11_3P;
r_gxs_00_4P <= w_gx_00_00_2P + w_gx_00_11_3P;
r_gxs_01_4P <= w_gx_01_00_2P + w_gx_01_11_3P;
r_gxs_11_5P <= r_gxs_11_4P + r_gx_11_01_2P;
r_gxs_00_5P <= r_gxs_00_4P + r_gx_00_01_2P;
r_gxs_01_5P <= r_gxs_01_4P + r_gx_01_01_2P;
r_gxs_00_6P <= r_gxs_00_5P + r_gxs_11_5P;
r_gxs_01_6P <= r_gxs_01_5P;
r_gxs_00_7P <= r_gxs_00_6P + r_gxs_01_6P;
////////////////////////////////
r_gy_11_01_2P <= w_gy_11_01_1P;
r_gy_00_01_2P <= w_gy_00_01_1P;
r_gy_01_01_2P <= w_gy_01_01_1P;
////////////////////////////////
r_gys_11_4P <= w_gy_11_00_2P + w_gy_11_11_3P;
r_gys_00_4P <= w_gy_00_00_2P + w_gy_00_11_3P;
r_gys_01_4P <= w_gy_01_00_2P + w_gy_01_11_3P;
r_gys_11_5P <= r_gys_11_4P + r_gy_11_01_2P;
r_gys_00_5P <= r_gys_00_4P + r_gy_00_01_2P;
r_gys_01_5P <= r_gys_01_4P + r_gy_01_01_2P;
r_gys_00_6P <= r_gys_00_5P + r_gys_11_5P;
r_gys_01_6P <= r_gys_01_5P;
r_gys_00_7P <= r_gys_00_6P + r_gys_01_6P;
////////////////////////////////
if (r_gxs_00_7P[Y_DEPTH+2-1])
r_gxs_00_8P <= ~r_gxs_00_7P + 1'b1;
else
r_gxs_00_8P <= r_gxs_00_7P;
if (r_gys_00_7P[Y_DEPTH+2-1])
r_gys_00_8P <= ~r_gys_00_7P + 1'b1;
else
r_gys_00_8P <= r_gys_00_7P;
r_g_9P <= r_gxs_00_8P + r_gys_00_8P;
if (r_g_9P[Y_DEPTH+2-1] || r_g_9P[Y_DEPTH+2-2])
r_g_10P <= {Y_DEPTH{1'b0}};
else
// r_g_10P <= {Y_DEPTH{1'b1}} - r_g_9P[Y_DEPTH-1:0];
r_g_10P <= r_g_9P[Y_DEPTH-1:0];
end
end
assign o_pixel = r_g_10P;
endmodule |
module multi_n2_ext5
#(
parameter D_WIDTH = 8
)
(
input i_arst,
input i_clk,
input [D_WIDTH-1:0]i_d,
output [D_WIDTH+5-1:0]o_q
);
reg [D_WIDTH+5-1:0]r_q_1P;
wire [D_WIDTH+5-1:0]w_d_0P;
assign w_d_0P = {4'b0000, i_d, 1'b0};
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_q_1P <= {D_WIDTH+5{1'b0}};
else
r_q_1P <= ~w_d_0P+1'b1;
end
assign o_q = r_q_1P;
endmodule |
module posterize
#(
parameter VESA_STD = "VESA_1280X720_60FPS",
parameter X_START = 0,
parameter Y_START = 0,
parameter X_END = 640,
parameter Y_END = 720,
parameter Y_DEPTH = 8,
parameter U_DEPTH = 8,
parameter V_DEPTH = 8,
parameter Y_TRIM_BIT = 5,
parameter U_TRIM_BIT = 5,
parameter V_TRIM_BIT = 5,
parameter X_LSB_CNT_WIDTH = 4,
parameter X_MSB_CNT_WIDTH = 6,
parameter Y_LSB_CNT_WIDTH = 4,
parameter Y_MSB_CNT_WIDTH = 6
)
(
input i_arst,
input i_pclk,
input i_posterize_en,
input i_vsync,
input i_hsync,
input i_de,
input [Y_DEPTH-1:0]i_y,
input [U_DEPTH-1:0]i_u,
input [V_DEPTH-1:0]i_v,
output o_vsync,
output o_hsync,
output o_de,
output [Y_DEPTH-1:0]o_y,
output [U_DEPTH-1:0]o_u,
output [V_DEPTH-1:0]o_v,
output o_x_done
);
//localparam X_MSB_END = X_END/(2**X_LSB_CNT_WIDTH)-1;
localparam X_MSB_END = X_END/(2**X_LSB_CNT_WIDTH);
//wire [X_MSB_CNT_WIDTH-1:0]w_X_MSB_END;
//wire [X_LSB_CNT_WIDTH-1:0]w_X_LSB_END;
localparam HOR_SYNC_POLARITY = `HOR_SYNC_POLARITY;
localparam VER_SYNC_POLARITY = `VER_SYNC_POLARITY;
wire c_act_vs_por;
wire c_ina_vs_por;
wire c_act_hs_por;
wire c_ina_hs_por;
wire c_act_de_por;
wire c_ina_de_por;
reg [X_LSB_CNT_WIDTH-1:0]r_x_lsb_cnt_1P;
reg [X_MSB_CNT_WIDTH-1:0]r_x_msb_cnt_1P;
//reg r_x_done_1P;
//reg r_x_msb_cnt_inc_1P;
reg r_posterize_en_1P;
reg r_vsync_1P;
reg r_hsync_1P;
reg r_de_1P;
reg [Y_DEPTH-1:0]r_y_1P;
reg [U_DEPTH-1:0]r_u_1P;
reg [V_DEPTH-1:0]r_v_1P;
reg r_vsync_2P;
reg r_hsync_2P;
reg r_de_2P;
reg [Y_DEPTH-1:0]r_y_2P;
reg [U_DEPTH-1:0]r_u_2P;
reg [V_DEPTH-1:0]r_v_2P;
reg r_x_done_y_2P;
reg r_x_done_u_2P;
reg r_x_done_v_2P;
//assign w_X_MSB_END = r_x_msb_cnt_1P-X_MSB_END;
//assign w_X_LSB_END = r_x_lsb_cnt_1P-{X_LSB_CNT_WIDTH{1'b1}};
generate
if (HOR_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_hs_por = 1'b0;
assign c_ina_hs_por = 1'b1;
end
else
begin
assign c_act_hs_por = 1'b1;
assign c_ina_hs_por = 1'b0;
end
if (VER_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_vs_por = 1'b0;
assign c_ina_vs_por = 1'b1;
end
else
begin
assign c_act_vs_por = 1'b1;
assign c_ina_vs_por = 1'b0;
end
endgenerate
assign c_act_de_por = 1'b1;
assign c_ina_de_por = 1'b0;
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_x_lsb_cnt_1P <= {X_LSB_CNT_WIDTH{1'b0}};
r_x_msb_cnt_1P <= {X_MSB_CNT_WIDTH{1'b0}};
// r_x_done_1P <= 1'b0;
// r_x_msb_cnt_inc_1P <= 1'b0;
r_posterize_en_1P <= 1'b0;
r_vsync_1P <= c_ina_vs_por;
r_hsync_1P <= c_ina_hs_por;
r_de_1P <= c_ina_de_por;
r_y_1P <= {Y_DEPTH{1'b0}};
r_u_1P <= {U_DEPTH{1'b0}};
r_v_1P <= {V_DEPTH{1'b0}};
r_vsync_2P <= c_ina_vs_por;
r_hsync_2P <= c_ina_hs_por;
r_de_2P <= c_ina_de_por;
r_y_2P <= {Y_DEPTH{1'b0}};
r_u_2P <= {U_DEPTH{1'b0}};
r_v_2P <= {V_DEPTH{1'b0}};
r_x_done_y_2P <= 1'b0;
r_x_done_u_2P <= 1'b0;
r_x_done_v_2P <= 1'b0;
end
else
begin
// r_x_msb_cnt_inc_1P <= 1'b0;
r_posterize_en_1P <= i_posterize_en;
if (i_hsync == c_act_hs_por)
r_x_lsb_cnt_1P <= {X_LSB_CNT_WIDTH{1'b0}};
else if (i_de)
r_x_lsb_cnt_1P <= r_x_lsb_cnt_1P+1'b1;
/* if (r_x_msb_cnt_inc_1P)
begin
r_x_msb_cnt_1P <= r_x_msb_cnt_1P+1'b1;
if (r_x_msb_cnt_1P == X_MSB_END)
begin
// r_x_done_1P <= 1'b1;
r_x_done_y_2P <= 1'b1;
r_x_done_u_2P <= 1'b1;
r_x_done_v_2P <= 1'b1;
end
end*/
if (i_hsync == c_act_hs_por)
begin
r_x_msb_cnt_1P <= {X_MSB_CNT_WIDTH{1'b0}};
// r_x_done_1P <= 1'b0;
end
// else if (w_X_LSB_END == {X_LSB_CNT_WIDTH{1'b0}})
else if (r_x_lsb_cnt_1P == {X_LSB_CNT_WIDTH{1'b1}})
begin
// r_x_msb_cnt_inc_1P <= 1'b1;
r_x_msb_cnt_1P <= r_x_msb_cnt_1P+1'b1;
// if (w_X_MSB_END == {X_MSB_CNT_WIDTH{1'b0}})
// if (r_x_msb_cnt_1P == X_MSB_END)
// r_x_done_1P <= 1'b1;
end
if (r_hsync_1P == c_act_hs_por)
begin
// r_x_done_y_2P <= 1'b0;
// r_x_done_u_2P <= 1'b0;
// r_x_done_v_2P <= 1'b0;
r_x_done_y_2P <= r_posterize_en_1P;
r_x_done_u_2P <= r_posterize_en_1P;
r_x_done_v_2P <= r_posterize_en_1P;
end
else if (r_x_msb_cnt_1P == X_MSB_END)
begin
r_x_done_y_2P <= 1'b1;
r_x_done_u_2P <= 1'b1;
r_x_done_v_2P <= 1'b1;
// r_x_done_y_2P <= r_posterize_en_1P;
// r_x_done_u_2P <= r_posterize_en_1P;
// r_x_done_v_2P <= r_posterize_en_1P;
end
r_vsync_1P <= i_vsync;
r_hsync_1P <= i_hsync;
r_de_1P <= i_de;
// r_y_1P[Y_DEPTH-1:Y_TRIM_BIT] <= i_y[Y_DEPTH-1:Y_TRIM_BIT];
// r_u_1P[U_DEPTH-1:U_TRIM_BIT] <= i_u[U_DEPTH-1:U_TRIM_BIT];
// r_v_1P[V_DEPTH-1:V_TRIM_BIT] <= i_v[V_DEPTH-1:V_TRIM_BIT];
r_y_1P <= i_y;
r_u_1P <= i_u;
r_v_1P <= i_v;
/* if (~r_x_done_1P)
begin
r_y_1P[Y_TRIM_BIT-1:0] <= {Y_TRIM_BIT{1'b0}};
r_u_1P[U_TRIM_BIT-1:0] <= {U_TRIM_BIT{1'b0}};
r_v_1P[V_TRIM_BIT-1:0] <= {V_TRIM_BIT{1'b0}};
end
else
begin
r_y_1P[Y_TRIM_BIT-1:0] <= i_y[Y_TRIM_BIT-1:0];
r_u_1P[U_TRIM_BIT-1:0] <= i_u[U_TRIM_BIT-1:0];
r_v_1P[V_TRIM_BIT-1:0] <= i_v[V_TRIM_BIT-1:0];
end*/
r_vsync_2P <= r_vsync_1P;
r_hsync_2P <= r_hsync_1P;
r_de_2P <= r_de_1P;
r_y_2P[Y_DEPTH-1:Y_TRIM_BIT] <= r_y_1P[Y_DEPTH-1:Y_TRIM_BIT];
r_u_2P[U_DEPTH-1:U_TRIM_BIT] <= r_u_1P[U_DEPTH-1:U_TRIM_BIT];
r_v_2P[V_DEPTH-1:V_TRIM_BIT] <= r_v_1P[V_DEPTH-1:V_TRIM_BIT];
// r_x_done_y_2P <= r_x_done_1P;
// r_x_done_u_2P <= r_x_done_1P;
// r_x_done_v_2P <= r_x_done_1P;
if (~r_x_done_y_2P)
r_y_2P[Y_TRIM_BIT-1:0] <= {Y_TRIM_BIT{1'b0}};
else
r_y_2P[Y_TRIM_BIT-1:0] <= r_y_1P[Y_TRIM_BIT-1:0];
if (~r_x_done_u_2P)
r_u_2P[U_TRIM_BIT-1:0] <= {U_TRIM_BIT{1'b0}};
else
r_u_2P[U_TRIM_BIT-1:0] <= r_u_1P[U_TRIM_BIT-1:0];
if (~r_x_done_v_2P)
r_v_2P[V_TRIM_BIT-1:0] <= {V_TRIM_BIT{1'b0}};
else
r_v_2P[V_TRIM_BIT-1:0] <= r_v_1P[V_TRIM_BIT-1:0];
end
end
//assign o_vsync = r_vsync_1P;
//assign o_hsync = r_hsync_1P;
//assign o_de = r_de_1P;
//assign o_y = r_y_1P;
//assign o_u = r_u_1P;
//assign o_v = r_v_1P;
assign o_vsync = r_vsync_2P;
assign o_hsync = r_hsync_2P;
assign o_de = r_de_2P;
assign o_y = r_y_2P;
assign o_u = r_u_2P;
assign o_v = r_v_2P;
//assign o_x_done = r_x_done_1P;
assign o_x_done = r_x_done_y_2P;
endmodule |
module ov5640_interface
#(
parameter VESA_STD = "VESA_1280X720_60FPS",
parameter RED_DEPTH = 5,
parameter GREEN_DEPTH = 6,
parameter BLUE_DEPTH = 5
)
(
input i_arst_pclk_x2,
input i_arst_pclk_x1,
input i_arst_pclk_div2,
input i_ov5640_pclk,
input i_ov5640_vsync,
input i_ov5640_href,
input [7:0]i_ov5640_d,
output o_pclk_x1,
output o_pclk_div2,
output o_synced,
output o_vs,
output o_hs,
output o_de,
output [RED_DEPTH-1:0]o_r,
output [GREEN_DEPTH-1:0]o_g,
output [BLUE_DEPTH-1:0]o_b
);
reg r_pclk_x1_1P = 1'b0;
reg r_pclk_div2_1P = 1'b0;
//reg r_pclk_x1_1P = 1'b1;
//reg r_pclk_div2_1P = 1'b1;
reg r_vs_sel_2P;
reg r_de_sel_2P;
reg r_vs_sel_3P = 1'b0;
reg r_vs_sel_4P = 1'b0;
reg r_vs_sel_5P = 1'b0;
reg [1:0]r_ov5640_vsync_pclk_x1_1P;
reg [1:0]r_ov5640_vs_pclk_x1_1P;
reg [1:0]r_ov5640_href_pclk_x1_1P;
reg [1:0]r_ov5640_de_pclk_x1_1P;
reg [15:0]r_ov5640_d_pclk_x1_1P;
reg [1:0]r_ov5640_vsync_pclk_x1_2P;
reg [1:0]r_ov5640_vs_pclk_x1_2P;
reg [1:0]r_ov5640_href_pclk_x1_2P;
reg [1:0]r_ov5640_de_pclk_x1_2P;
reg [15:0]r_ov5640_d_pclk_x1_2P;
reg r_ov5640_vsync_pclk_x1_FP;
reg r_ov5640_href_pclk_x1_FP;
reg [7:0]r_ov5640_d_pclk_x1_FP;
reg [1:0]r_ov5640_vsync_pclk_x1_3P;
reg [1:0]r_ov5640_href_pclk_x1_3P;
reg [15:0]r_ov5640_d_pclk_x1_3P;
reg r_vs_pclk_x1_4P;
reg r_de_pclk_x1_4P;
reg [RED_DEPTH-1:0]r_r_pclk_x1_4P;
reg [GREEN_DEPTH-1:0]r_g_pclk_x1_4P;
reg [BLUE_DEPTH-1:0]r_b_pclk_x1_4P;
reg r_neven_odd_pclk_x1_5P;
reg r_vs_pclk_x1_5P;
reg r_de_pclk_x1_5P;
reg [RED_DEPTH-1:0]r_r_pclk_x1_5P;
reg [GREEN_DEPTH-1:0]r_g_pclk_x1_5P;
reg [BLUE_DEPTH-1:0]r_b_pclk_x1_5P;
reg r_neven_odd_pclk_x1_6P;
reg r_vs_pclk_x1_6P;
reg [2*RED_DEPTH-1:0]r_r_pclk_x1_6P;
reg [2*GREEN_DEPTH-1:0]r_g_pclk_x1_6P;
reg [2*BLUE_DEPTH-1:0]r_b_pclk_x1_6P;
reg r_vs_pclk_div2_7P;
reg r_de_pclk_div2_7P;
reg [2*RED_DEPTH-1:0]r_r_pclk_div2_7P;
reg [2*GREEN_DEPTH-1:0]r_g_pclk_div2_7P;
reg [2*BLUE_DEPTH-1:0]r_b_pclk_div2_7P;
reg r_vs_pclk_div2_8P;
reg r_de_pclk_div2_8P;
reg [2*RED_DEPTH-1:0]r_r_pclk_div2_8P;
reg [2*GREEN_DEPTH-1:0]r_g_pclk_div2_8P;
reg [2*BLUE_DEPTH-1:0]r_b_pclk_div2_8P;
reg r_vs_pclk_div2_9P;
reg r_hs_pclk_div2_9P;
reg r_de_pclk_div2_9P;
reg [2*RED_DEPTH-1:0]r_r_pclk_div2_9P;
reg [2*GREEN_DEPTH-1:0]r_g_pclk_div2_9P;
reg [2*BLUE_DEPTH-1:0]r_b_pclk_div2_9P;
reg [9:0]r_x_9P;
reg [9:0]r_y_9P;
reg r_synced_pclk_div2_9P;
reg r_de_next_pclk_div2_9P;
reg r_vs_pclk_x1_10P;
reg r_hs_pclk_x1_10P;
reg r_de_pclk_x1_10P;
reg [2*RED_DEPTH-1:0]r_r_pclk_x1_10P;
reg [2*GREEN_DEPTH-1:0]r_g_pclk_x1_10P;
reg [2*BLUE_DEPTH-1:0]r_b_pclk_x1_10P;
reg r_vs_pclk_x1_11P;
reg r_hs_pclk_x1_11P;
reg r_de_pclk_x1_11P;
reg [2*RED_DEPTH-1:0]r_r_pclk_x1_11P;
reg [2*GREEN_DEPTH-1:0]r_g_pclk_x1_11P;
reg [2*BLUE_DEPTH-1:0]r_b_pclk_x1_11P;
reg r_neven_odd_pclk_x1_12P;
reg r_de_pclk_x1_12P;
reg [RED_DEPTH-1:0]r_r_pclk_x1_12P;
reg [GREEN_DEPTH-1:0]r_g_pclk_x1_12P;
reg [BLUE_DEPTH-1:0]r_b_pclk_x1_12P;
wire [1:0]w_ov5640_vsync_pclk_x1;
wire [1:0]w_ov5640_href_pclk_x1;
wire [15:0]w_ov5640_d_pclk_x1;
wire w_de;
wire [RED_DEPTH-1:0]w_r;
wire [GREEN_DEPTH-1:0]w_g;
wire [BLUE_DEPTH-1:0]w_b;
wire c_act_vs_por;
wire c_ina_vs_por;
wire c_act_hs_por;
wire c_ina_hs_por;
wire c_act_de_por;
wire c_ina_de_por;
wire w_pclk_x1;
wire w_pclk_div2;
wire [11:0]c_cmp_hor_sync_time;
wire [11:0]c_cmp_hor_total_time;
assign w_pclk_x1 = r_pclk_x1_1P;
assign w_pclk_div2 = r_pclk_div2_1P;
assign c_cmp_hor_sync_time = `HOR_SYNC_TIME-1'b1;
assign c_cmp_hor_total_time = `HOR_TOTAL_TIME-1'b1;
generate
localparam HOR_SYNC_POLARITY = `HOR_SYNC_POLARITY;
localparam VER_SYNC_POLARITY = `VER_SYNC_POLARITY;
if (HOR_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_hs_por = 1'b0;
assign c_ina_hs_por = 1'b1;
end
else
begin
assign c_act_hs_por = 1'b1;
assign c_ina_hs_por = 1'b0;
end
if (VER_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_vs_por = 1'b0;
assign c_ina_vs_por = 1'b1;
end
else
begin
assign c_act_vs_por = 1'b1;
assign c_ina_vs_por = 1'b0;
end
endgenerate
assign c_act_de_por = 1'b1;
assign c_ina_de_por = 1'b0;
sync_ddio_group_in
#(
.DW(10),
.SYNC("RISING")
)
inst_sync_ddio_group_in
(
.arst_c_x1(i_arst_pclk_x1),
.arst_c_x2(i_arst_pclk_x2),
.c_x1(w_pclk_x1),
.c_x2(i_ov5640_pclk),
.d({i_ov5640_vsync,
i_ov5640_href,
i_ov5640_d}),
.q0({ w_ov5640_vsync_pclk_x1[0],
w_ov5640_href_pclk_x1[0],
w_ov5640_d_pclk_x1[15:8]
}),
.q1({ w_ov5640_vsync_pclk_x1[1],
w_ov5640_href_pclk_x1[1],
w_ov5640_d_pclk_x1[7:0]
})
);
always@(posedge i_ov5640_pclk)
begin
r_vs_sel_3P <= r_vs_sel_2P;
r_vs_sel_4P <= r_vs_sel_3P;
r_vs_sel_5P <= r_vs_sel_4P;
if (r_vs_sel_4P && ~r_vs_sel_5P)
r_pclk_x1_1P <= r_pclk_x1_1P;
else
r_pclk_x1_1P <= ~r_pclk_x1_1P;
end
always@(posedge w_pclk_x1)
begin
r_pclk_div2_1P <= ~r_pclk_div2_1P;
end
always@(posedge i_arst_pclk_x1 or posedge w_pclk_x1)
begin
if (i_arst_pclk_x1)
begin
r_vs_sel_2P <= 1'b0;
r_de_sel_2P <= 1'b0;
r_ov5640_vsync_pclk_x1_1P <= {2{1'b0}};
r_ov5640_vs_pclk_x1_1P <= {2{1'b0}};
r_ov5640_href_pclk_x1_1P <= {2{1'b0}};
r_ov5640_de_pclk_x1_1P <= {2{1'b0}};
r_ov5640_d_pclk_x1_1P <= {16{1'b0}};
r_ov5640_vsync_pclk_x1_2P <= {2{1'b0}};
r_ov5640_vs_pclk_x1_2P <= {2{1'b0}};
r_ov5640_href_pclk_x1_2P <= {2{1'b0}};
r_ov5640_de_pclk_x1_2P <= {2{1'b0}};
r_ov5640_d_pclk_x1_2P <= {16{1'b0}};
r_ov5640_vsync_pclk_x1_FP <= {1{1'b0}};
r_ov5640_href_pclk_x1_FP <= {1{1'b0}};
r_ov5640_d_pclk_x1_FP <= {8{1'b0}};
r_ov5640_vsync_pclk_x1_3P <= {2{1'b0}};
r_ov5640_href_pclk_x1_3P <= {2{1'b0}};
r_ov5640_d_pclk_x1_3P <= {16{1'b0}};
r_vs_pclk_x1_4P <= c_ina_vs_por;
r_de_pclk_x1_4P <= 1'b0;
r_r_pclk_x1_4P <= {RED_DEPTH{1'b0}};
r_g_pclk_x1_4P <= {GREEN_DEPTH{1'b0}};
r_b_pclk_x1_4P <= {BLUE_DEPTH{1'b0}};
r_neven_odd_pclk_x1_5P <= 1'b0;
r_vs_pclk_x1_5P <= c_ina_vs_por;
r_de_pclk_x1_5P <= 1'b0;
r_r_pclk_x1_5P <= {RED_DEPTH{1'b0}};
r_g_pclk_x1_5P <= {GREEN_DEPTH{1'b0}};
r_b_pclk_x1_5P <= {BLUE_DEPTH{1'b0}};
r_neven_odd_pclk_x1_6P <= 1'b0;
r_vs_pclk_x1_6P <= c_ina_vs_por;
r_r_pclk_x1_6P <= {RED_DEPTH{1'b0}};
r_g_pclk_x1_6P <= {GREEN_DEPTH{1'b0}};
r_b_pclk_x1_6P <= {BLUE_DEPTH{1'b0}};
end
else
begin
r_ov5640_vsync_pclk_x1_1P <= w_ov5640_vsync_pclk_x1;
r_ov5640_vs_pclk_x1_1P <= w_ov5640_vsync_pclk_x1;
r_ov5640_href_pclk_x1_1P <= w_ov5640_href_pclk_x1;
r_ov5640_de_pclk_x1_1P <= w_ov5640_href_pclk_x1;
r_ov5640_d_pclk_x1_1P <= w_ov5640_d_pclk_x1;
r_ov5640_vsync_pclk_x1_2P <= r_ov5640_vsync_pclk_x1_1P;
r_ov5640_vs_pclk_x1_2P <= r_ov5640_vsync_pclk_x1_1P;
r_ov5640_href_pclk_x1_2P <= r_ov5640_href_pclk_x1_1P;
r_ov5640_de_pclk_x1_2P <= r_ov5640_href_pclk_x1_1P;
r_ov5640_d_pclk_x1_2P <= r_ov5640_d_pclk_x1_1P;
if (r_ov5640_vs_pclk_x1_1P == 2'b10)
r_vs_sel_2P <= 1'b1;
else if (r_ov5640_vs_pclk_x1_1P == 2'b11 && r_ov5640_vs_pclk_x1_2P == 2'b00)
r_vs_sel_2P <= 1'b0;
if (r_ov5640_de_pclk_x1_1P == 2'b10)
r_de_sel_2P <= 1'b1;
else if (r_ov5640_de_pclk_x1_1P == 2'b11 && r_ov5640_de_pclk_x1_2P == 2'b00)
r_de_sel_2P <= 1'b0;
r_ov5640_vsync_pclk_x1_FP <= r_ov5640_vsync_pclk_x1_2P[1];
r_ov5640_href_pclk_x1_FP <= r_ov5640_href_pclk_x1_2P[1];
r_ov5640_d_pclk_x1_FP <= r_ov5640_d_pclk_x1_2P[15:8];
if (r_vs_sel_2P)
r_ov5640_vsync_pclk_x1_3P <= {r_ov5640_vsync_pclk_x1_2P[0], r_ov5640_vsync_pclk_x1_FP};
else
r_ov5640_vsync_pclk_x1_3P <= r_ov5640_vsync_pclk_x1_2P;
if (r_de_sel_2P)
begin
r_ov5640_href_pclk_x1_3P <= {r_ov5640_href_pclk_x1_2P[0], r_ov5640_href_pclk_x1_FP};
r_ov5640_d_pclk_x1_3P <= {r_ov5640_d_pclk_x1_2P[7:0], r_ov5640_d_pclk_x1_FP};
end
else
begin
r_ov5640_href_pclk_x1_3P <= r_ov5640_href_pclk_x1_2P;
r_ov5640_d_pclk_x1_3P <= r_ov5640_d_pclk_x1_2P;
end
r_vs_pclk_x1_4P <= 1'b0;
if (r_ov5640_vsync_pclk_x1_3P[0])
r_vs_pclk_x1_4P <= 1'b1;
r_de_pclk_x1_4P <= 1'b0;
if (r_ov5640_href_pclk_x1_3P[0])
r_de_pclk_x1_4P <= 1'b1;
r_r_pclk_x1_4P <= {RED_DEPTH{1'b0}};
r_g_pclk_x1_4P <= {GREEN_DEPTH{1'b0}};
r_b_pclk_x1_4P <= {BLUE_DEPTH{1'b0}};
// Color Bar
if (r_ov5640_href_pclk_x1_3P[1])
r_b_pclk_x1_4P <= r_ov5640_d_pclk_x1_3P[15:16-BLUE_DEPTH];
// r_b_pclk_x1_4P <= {BLUE_DEPTH{1'b0}};
if (r_ov5640_href_pclk_x1_3P[0])
r_g_pclk_x1_4P <= r_ov5640_d_pclk_x1_3P[16-BLUE_DEPTH-1:16-BLUE_DEPTH-GREEN_DEPTH];
// r_g_pclk_x1_4P <= {GREEN_DEPTH{1'b0}};
if (r_ov5640_href_pclk_x1_3P[1])
r_r_pclk_x1_4P <= r_ov5640_d_pclk_x1_3P[RED_DEPTH-1:0];
// r_r_pclk_x1_4P <= {RED_DEPTH{1'b1}};
if (~r_de_pclk_x1_4P && r_de_pclk_x1_5P)
r_neven_odd_pclk_x1_5P <= 1'b0;
else if (r_de_pclk_x1_4P)
r_neven_odd_pclk_x1_5P <= ~r_neven_odd_pclk_x1_5P;
r_vs_pclk_x1_5P <= r_vs_pclk_x1_4P;
r_de_pclk_x1_5P <= r_de_pclk_x1_4P;
r_r_pclk_x1_5P <= r_r_pclk_x1_4P;
r_g_pclk_x1_5P <= r_g_pclk_x1_4P;
r_b_pclk_x1_5P <= r_b_pclk_x1_4P;
r_neven_odd_pclk_x1_6P <= r_neven_odd_pclk_x1_5P;
r_vs_pclk_x1_6P <= r_vs_pclk_x1_5P;
if (r_de_pclk_x1_5P)
begin
if (r_neven_odd_pclk_x1_5P && ~r_neven_odd_pclk_x1_6P)
begin
r_r_pclk_x1_6P <= {r_r_pclk_x1_4P, r_r_pclk_x1_5P};
r_g_pclk_x1_6P <= {r_g_pclk_x1_4P, r_g_pclk_x1_5P};
r_b_pclk_x1_6P <= {r_b_pclk_x1_4P, r_b_pclk_x1_5P};
end
end
else
begin
r_r_pclk_x1_6P <= {RED_DEPTH*2{1'b0}};
r_g_pclk_x1_6P <= {GREEN_DEPTH*2{1'b0}};
r_b_pclk_x1_6P <= {BLUE_DEPTH*2{1'b0}};
end
end
end
always@(posedge i_arst_pclk_div2 or posedge w_pclk_div2)
begin
if (i_arst_pclk_div2)
begin
r_vs_pclk_div2_7P <= c_ina_vs_por;
r_r_pclk_div2_7P <= {2*RED_DEPTH{1'b0}};
r_g_pclk_div2_7P <= {2*GREEN_DEPTH{1'b0}};
r_b_pclk_div2_7P <= {2*BLUE_DEPTH{1'b0}};
r_vs_pclk_div2_8P <= c_ina_vs_por;
r_r_pclk_div2_8P <= {2*RED_DEPTH{1'b0}};
r_g_pclk_div2_8P <= {2*GREEN_DEPTH{1'b0}};
r_b_pclk_div2_8P <= {2*BLUE_DEPTH{1'b0}};
r_vs_pclk_div2_9P <= c_ina_vs_por;
r_hs_pclk_div2_9P <= c_ina_hs_por;
r_de_pclk_div2_9P <= c_ina_de_por;
r_r_pclk_div2_9P <= {2*RED_DEPTH{1'b0}};
r_g_pclk_div2_9P <= {2*GREEN_DEPTH{1'b0}};
r_b_pclk_div2_9P <= {2*BLUE_DEPTH{1'b0}};
r_x_9P <= {10{1'b0}};
r_y_9P <= {10{1'b0}};
r_synced_pclk_div2_9P <= 1'b0;
r_de_next_pclk_div2_9P <= c_ina_de_por;
end
else
begin
r_vs_pclk_div2_7P <= r_vs_pclk_x1_6P;
r_r_pclk_div2_7P <= r_r_pclk_x1_6P;
r_g_pclk_div2_7P <= r_g_pclk_x1_6P;
r_b_pclk_div2_7P <= r_b_pclk_x1_6P;
r_vs_pclk_div2_8P <= r_vs_pclk_div2_7P;
r_r_pclk_div2_8P <= r_r_pclk_div2_7P;
r_g_pclk_div2_8P <= r_g_pclk_div2_7P;
r_b_pclk_div2_8P <= r_b_pclk_div2_7P;
r_r_pclk_div2_9P <= r_r_pclk_div2_8P;
r_g_pclk_div2_9P <= r_g_pclk_div2_8P;
r_b_pclk_div2_9P <= r_b_pclk_div2_8P;
r_x_9P <= r_x_9P+1'b1;
if (r_x_9P-10'd19==10'h000)
r_hs_pclk_div2_9P <= c_ina_hs_por;
else if (r_x_9P-10'd22==10'h000)
r_de_pclk_div2_9P <= r_de_next_pclk_div2_9P;
else if (r_x_9P-10'd661==10'h000)
r_de_pclk_div2_9P <= c_ina_de_por;
else if (r_x_9P-10'd824==10'h000)
begin
r_hs_pclk_div2_9P <= c_act_hs_por;
r_x_9P <= {10{1'b0}};
r_y_9P <= r_y_9P+1'b1;
if (r_y_9P-10'd4 == 10'h000)
r_vs_pclk_div2_9P <= c_ina_vs_por;
else if (r_y_9P-10'd24 == 10'h000)
r_de_next_pclk_div2_9P <= c_act_de_por;
else if (r_y_9P-10'd744 == 10'h000)
r_de_next_pclk_div2_9P <= c_ina_de_por;
else if (r_y_9P-10'd749 == 10'h000)
begin
r_vs_pclk_div2_9P <= c_act_vs_por;
r_y_9P <= {10{1'b0}};
end
end
if (~r_synced_pclk_div2_9P)
begin
if (r_vs_pclk_div2_8P)
begin
r_hs_pclk_div2_9P <= c_act_hs_por;
r_x_9P <= r_x_9P+1'b1;
if (r_x_9P-10'd19==10'h000)
begin
r_hs_pclk_div2_9P <= c_ina_hs_por;
r_synced_pclk_div2_9P <= 1'b1;
end
end
else
begin
r_hs_pclk_div2_9P <= c_ina_hs_por;
r_x_9P <= {10{1'b0}};
end
end
end
end
//always@(posedge i_arst or posedge w_pclk_x1)
always@(posedge i_arst_pclk_x1 or posedge w_pclk_x1)
begin
// if (i_arst)
if (i_arst_pclk_x1)
begin
r_vs_pclk_x1_10P <= c_ina_vs_por;
r_hs_pclk_x1_10P <= c_ina_hs_por;
r_de_pclk_x1_10P <= c_ina_de_por;
r_r_pclk_x1_10P <= {2*RED_DEPTH{1'b0}};
r_g_pclk_x1_10P <= {2*GREEN_DEPTH{1'b0}};
r_b_pclk_x1_10P <= {2*BLUE_DEPTH{1'b0}};
r_vs_pclk_x1_11P <= c_ina_vs_por;
r_hs_pclk_x1_11P <= c_ina_hs_por;
r_de_pclk_x1_11P <= c_ina_de_por;
r_r_pclk_x1_11P <= {2*RED_DEPTH{1'b0}};
r_g_pclk_x1_11P <= {2*GREEN_DEPTH{1'b0}};
r_b_pclk_x1_11P <= {2*BLUE_DEPTH{1'b0}};
r_neven_odd_pclk_x1_12P <= 1'b0;
r_de_pclk_x1_12P <= c_ina_de_por;
r_r_pclk_x1_12P <= {RED_DEPTH{1'b0}};
r_g_pclk_x1_12P <= {GREEN_DEPTH{1'b0}};
r_b_pclk_x1_12P <= {BLUE_DEPTH{1'b0}};
end
else
begin
r_vs_pclk_x1_10P <= r_vs_pclk_div2_9P;
r_hs_pclk_x1_10P <= r_hs_pclk_div2_9P;
r_de_pclk_x1_10P <= r_de_pclk_div2_9P;
r_r_pclk_x1_10P <= r_r_pclk_div2_9P;
r_g_pclk_x1_10P <= r_g_pclk_div2_9P;
r_b_pclk_x1_10P <= r_b_pclk_div2_9P;
r_vs_pclk_x1_11P <= r_vs_pclk_x1_10P;
r_hs_pclk_x1_11P <= r_hs_pclk_x1_10P;
r_de_pclk_x1_11P <= r_de_pclk_x1_10P;
r_r_pclk_x1_11P <= r_r_pclk_x1_10P;
r_g_pclk_x1_11P <= r_g_pclk_x1_10P;
r_b_pclk_x1_11P <= r_b_pclk_x1_10P;
if (r_de_pclk_x1_11P)
r_neven_odd_pclk_x1_12P <= ~r_neven_odd_pclk_x1_12P;
r_de_pclk_x1_12P <= r_de_pclk_x1_11P;
if (r_neven_odd_pclk_x1_12P)
begin
r_r_pclk_x1_12P <= r_r_pclk_x1_11P[RED_DEPTH*2-1:RED_DEPTH];
r_g_pclk_x1_12P <= r_g_pclk_x1_11P[GREEN_DEPTH*2-1:GREEN_DEPTH];
r_b_pclk_x1_12P <= r_b_pclk_x1_11P[BLUE_DEPTH*2-1:BLUE_DEPTH];
end
else
begin
r_r_pclk_x1_12P <= r_r_pclk_x1_11P[RED_DEPTH-1:0];
r_g_pclk_x1_12P <= r_g_pclk_x1_11P[GREEN_DEPTH-1:0];
r_b_pclk_x1_12P <= r_b_pclk_x1_11P[BLUE_DEPTH-1:0];
end
end
end
ram_shift_reg
#(
.DATA_WIDTH(1+RED_DEPTH+GREEN_DEPTH+BLUE_DEPTH),
.LATENCY(214),
.NUM_GROUP(1)
)
inst_ram_shift_reg
(
.arst(i_arst_pclk_x1),
.clk(w_pclk_x1),
.sr_in({r_de_pclk_x1_12P, r_b_pclk_x1_12P,
r_g_pclk_x1_12P, r_r_pclk_x1_12P}),
.sr_out({w_de, w_b, w_g, w_r}),
.tg_out()
);
assign o_pclk_x1 = w_pclk_x1;
assign o_pclk_div2 = w_pclk_div2;
assign o_synced = r_synced_pclk_div2_9P;
assign o_vs = r_vs_pclk_x1_11P;
assign o_hs = r_hs_pclk_x1_11P;
assign o_de = w_de;
assign o_r = w_r;
assign o_g = w_g;
assign o_b = w_b;
endmodule |
module ov5640_config
(
input i_arst,
input i_sysclk,
input i_pll_locked,
output o_confdone,
input i_sda,
output o_sda_oe,
input i_scl,
output o_scl_oe
);
localparam DEVICE_ADDRESS = 8'h00;
localparam ADDRESSING = 7;
localparam SYSCLK_FREQ = 25;
localparam MODE = "FAST";
localparam SLAVE_ENABLE = "FALSE";
localparam s_IDLE = 2'b01;
localparam s_CONFIG = 2'b10;
localparam s_DONE = 2'b00;
reg r_m_en_1P;
reg r_m_wr_1P;
wire [7:0]w_ov5640_reg;
reg r_last_1P;
wire w_ack;
wire w_last;
wire [7:0]w_data;
reg [1:0]r_i2c_config_state_1P;
reg [9:0]r_addr_1P;
reg [1:0]r_byte_cnt_1P;
reg [8:0]r_reg_cnt_1P;
reg r_confdone_1P;
i2c_wrapper
#(
.DEVICE_ADDRESS (DEVICE_ADDRESS),
.ADDRESSING (ADDRESSING),
.SYSCLK_FREQ (SYSCLK_FREQ),
.MODE (MODE),
.SLAVE_ENABLE (SLAVE_ENABLE)
)
inst_i2c
(
.i_arst (i_arst),
.i_sysclk (i_sysclk),
.i_m_en (r_m_en_1P),
.i_m_wr (r_m_wr_1P),
.i_last (r_last_1P),
.i_addr (7'h3C),
.i_data (w_ov5640_reg),
// .o_s_en (w_s_en),
// .o_s_wr (w_s_wr),
.o_ack (w_ack),
.o_last (w_last),
.o_data (w_data),
.i_sda (i_sda),
.o_sda_oe (o_sda_oe),
.i_scl (i_scl),
.o_scl_oe (o_scl_oe)
);
ov5640_reg
inst_ov5640_reg
(
.i_addr(r_addr_1P),
.o_data(w_ov5640_reg)
);
always@(posedge i_arst or posedge i_sysclk)
begin
if (i_arst)
begin
r_i2c_config_state_1P <= s_IDLE;
r_addr_1P <= {10{1'b0}};
r_m_en_1P <= 1'b0;
r_m_wr_1P <= 1'b0;
r_last_1P <= 1'b0;
r_byte_cnt_1P <= {2{1'b0}};
r_reg_cnt_1P <= {9{1'b0}};
r_confdone_1P <= 1'b0;
end
else
begin
case (r_i2c_config_state_1P)
s_IDLE:
begin
if (i_pll_locked)
begin
r_i2c_config_state_1P <= s_CONFIG;
r_addr_1P <= {10{1'b0}};
r_m_en_1P <= 1'b1;
r_m_wr_1P <= 1'b0;
r_last_1P <= 1'b0;
r_byte_cnt_1P <= {2{1'b0}};
r_reg_cnt_1P <= {9{1'b0}};
end
end
s_CONFIG:
begin
r_m_en_1P <= 1'b1;
r_last_1P <= 1'b0;
if (w_ack)
begin
if (r_reg_cnt_1P != 9'd305)
// if (r_reg_cnt_1P != 9'd001)
begin
r_addr_1P <= r_addr_1P+1'b1;
r_byte_cnt_1P <= r_byte_cnt_1P+1'b1;
if (r_byte_cnt_1P == 2'b10)
begin
r_m_en_1P <= 1'b0;
r_last_1P <= 1'b1;
r_byte_cnt_1P <= {2{1'b0}};
r_reg_cnt_1P <= r_reg_cnt_1P+1'b1;
end
end
else
begin
r_i2c_config_state_1P <= s_DONE;
r_m_en_1P <= 1'b0;
r_confdone_1P <= 1'b1;
end
end
end
s_DONE:
begin
end
default:
begin
r_i2c_config_state_1P <= s_IDLE;
r_addr_1P <= {10{1'b0}};
r_m_en_1P <= 1'b0;
r_m_wr_1P <= 1'b0;
r_byte_cnt_1P <= {2{1'b0}};
r_reg_cnt_1P <= {9{1'b0}};
end
endcase
end
end
assign o_confdone = r_confdone_1P;
endmodule |
module sobel_filter
#(
parameter VESA_STD = "VESA_180X720_60FPS",
parameter X_START = 0,
parameter Y_START = 0,
parameter X_END = 640,
parameter Y_END = 720,
parameter Y_DEPTH = 8,
parameter X_LSB_CNT_WIDTH = 4,
parameter X_MSB_CNT_WIDTH = 6,
parameter Y_LSB_CNT_WIDTH = 4,
parameter Y_MSB_CNT_WIDTH = 6
)
(
input i_arst,
input i_pclk,
input i_vsync,
input i_hsync,
input i_de,
input [Y_DEPTH-1:0]i_y_11_01,
input [Y_DEPTH-1:0]i_y_00_01,
input [Y_DEPTH-1:0]i_y_01_01,
output o_x_en,
output o_vsync,
output o_hsync,
output o_de,
output [Y_DEPTH-1:0]o_y
);
localparam HOR_SYNC_POLARITY = `HOR_SYNC_POLARITY;
localparam VER_SYNC_POLARITY = `VER_SYNC_POLARITY;
wire c_act_vs_por;
wire c_ina_vs_por;
wire c_act_hs_por;
wire c_ina_hs_por;
wire c_act_de_por;
wire c_ina_de_por;
reg r_vsync_1P;
reg r_de_1P;
wire w_x_en_1P;
wire w_hsync_1P;
wire w_x_en_9P;
wire w_vsync_9P;
wire w_hsync_9P;
wire w_de_9P;
wire [Y_DEPTH-1:0]w_y_9P;
generate
if (HOR_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_hs_por = 1'b0;
assign c_ina_hs_por = 1'b1;
end
else
begin
assign c_act_hs_por = 1'b1;
assign c_ina_hs_por = 1'b0;
end
if (VER_SYNC_POLARITY == "NEGATIVE")
begin
assign c_act_vs_por = 1'b0;
assign c_ina_vs_por = 1'b1;
end
else
begin
assign c_act_vs_por = 1'b1;
assign c_ina_vs_por = 1'b0;
end
endgenerate
assign c_act_de_por = 1'b1;
assign c_ina_de_por = 1'b0;
sobel_feldman
//sobel_scharr
#(
.Y_DEPTH(Y_DEPTH)
)
inst_sobel_pixel
(
.i_arst (i_arst),
.i_pclk (i_pclk),
.i_pixel_11_01 (i_y_11_01),
.i_pixel_00_01 (i_y_00_01),
.i_pixel_01_01 (i_y_01_01),
.o_pixel (w_y_9P)
);
filter_size
#(
.VESA_STD (VESA_STD),
.X_START (0),
.Y_START (0),
.X_END (640),
.Y_END (720),
.X_LSB_CNT_WIDTH(4),
.X_MSB_CNT_WIDTH(6),
.Y_LSB_CNT_WIDTH(4),
.Y_MSB_CNT_WIDTH(6)
)
isnt_filter_size
(
.i_arst (i_arst),
.i_pclk (i_pclk),
.i_hsync (i_hsync),
.o_hsync (w_hsync_1P),
.o_x_en (w_x_en_1P)
);
shift_reg
#(
.D_WIDTH(4),
.TAPE(8)
)
inst_shift_reg
(
.i_arst(i_arst),
.i_clk(i_pclk),
.i_d({w_x_en_1P, r_vsync_1P, w_hsync_1P, r_de_1P}),
.o_q({w_x_en_9P, w_vsync_9P, w_hsync_9P, w_de_9P})
);
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_vsync_1P <= c_ina_vs_por;
r_de_1P <= c_ina_de_por;
end
else
begin
r_vsync_1P <= i_vsync;
r_de_1P <= i_de;
end
end
assign o_x_en = w_x_en_9P;
assign o_vsync = w_vsync_9P;
assign o_hsync = w_hsync_9P;
assign o_de = w_de_9P;
assign o_y = w_y_9P;
endmodule |
module multi_n1_ext5
#(
parameter D_WIDTH = 8
)
(
input i_arst,
input i_clk,
input [D_WIDTH-1:0]i_d,
output [D_WIDTH+5-1:0]o_q
);
reg [D_WIDTH+5-1:0]r_q_1P;
wire [D_WIDTH+5-1:0]w_d_0P;
assign w_d_0P = {5'b00000, i_d};
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_q_1P <= {D_WIDTH+5{1'b0}};
else
r_q_1P <= ~w_d_0P+1'b1;
end
assign o_q = r_q_1P;
endmodule |
module color_coding_converter
#(
parameter R_DEPTH = 5,
parameter G_DEPTH = 5,
parameter B_DEPTH = 5,
parameter Y_DEPTH = 5,
parameter U_DEPTH = 5,
parameter V_DEPTH = 5,
parameter RGB2YUV_TWOCOMP_WIDTH = 6,
parameter YUV2RGB_TWOCOMP_WIDTH = 7,
parameter Y_OFFSET = 8'd16,
// 16 for BT.601 Studio swing
// 0 for BT.601 Full swing
// 0 for JPEG YCbCr
parameter OUTPUT_REG = "TRUE",
parameter ROM_A00 = "rom_a00.mem",
parameter ROM_A01 = "rom_a01.mem",
parameter ROM_A02 = "rom_a02.mem",
parameter ROM_A10 = "rom_a10.mem",
parameter ROM_A11 = "rom_a11.mem",
parameter ROM_A12 = "rom_a12.mem",
parameter ROM_A20 = "rom_a20.mem",
parameter ROM_A21 = "rom_a21.mem",
parameter ROM_A22 = "rom_a22.mem"
)
(
input i_arst,
input i_pclk,
input i_rgb2yuv_de,
input [R_DEPTH-1:0]i_rgb2yuv_r,
input [G_DEPTH-1:0]i_rgb2yuv_g,
input [B_DEPTH-1:0]i_rgb2yuv_b,
output o_rgb2yuv_de,
output [Y_DEPTH-1:0]o_rgb2yuv_y,
output [U_DEPTH-1:0]o_rgb2yuv_u,
output [V_DEPTH-1:0]o_rgb2yuv_v,
input i_yuv2rgb_de,
input [Y_DEPTH-1:0]i_yuv2rgb_y,
input [U_DEPTH-1:0]i_yuv2rgb_u,
input [V_DEPTH-1:0]i_yuv2rgb_v,
output o_yuv2rgb_de,
output [R_DEPTH-1:0]o_yuv2rgb_r,
output [G_DEPTH-1:0]o_yuv2rgb_g,
output [B_DEPTH-1:0]o_yuv2rgb_b
);
reg r_rgb2yuv_de_P;
reg r_yuv2rgb_de_P;
reg [RGB2YUV_TWOCOMP_WIDTH-1:0]r_rom_a02_dout1_P;
reg [YUV2RGB_TWOCOMP_WIDTH-1:0]r_rom_a02_dout2_P;
reg [RGB2YUV_TWOCOMP_WIDTH-1:0]r_rom_a12_dout1_P;
reg [YUV2RGB_TWOCOMP_WIDTH-1:0]r_rom_a12_dout2_P;
reg [YUV2RGB_TWOCOMP_WIDTH-1:0]r_rom_a21_dout2_P;
reg [RGB2YUV_TWOCOMP_WIDTH-1:0]r_rom_a22_dout1_P;
reg r_rgb2yuv_de_1P;
reg [R_DEPTH-1:0]r_rgb2yuv_r_1P;
reg [G_DEPTH-1:0]r_rgb2yuv_g_1P;
reg [B_DEPTH-1:0]r_rgb2yuv_b_1P;
//reg r_rgb2yuv_we_1P;
reg r_yuv2rgb_de_1P;
reg [Y_DEPTH-1:0]r_yuv2rgb_y_1P;
reg [U_DEPTH-1:0]r_yuv2rgb_u_1P;
reg [V_DEPTH-1:0]r_yuv2rgb_v_1P;
//reg r_yuv2rgb_we_1P;
reg r_rgb2yuv_de_2P;
reg r_yuv2rgb_de_2P;
reg r_rgb2yuv_de_3P;
reg [RGB2YUV_TWOCOMP_WIDTH-1:0]r_rgb2yuv_s00_3P;
reg [RGB2YUV_TWOCOMP_WIDTH-1:0]r_rgb2yuv_s10_3P;
reg [RGB2YUV_TWOCOMP_WIDTH-1:0]r_rgb2yuv_s20_3P;
reg r_yuv2rgb_de_3P;
reg [YUV2RGB_TWOCOMP_WIDTH-1:0]r_yuv2rgb_s00_3P;
reg [YUV2RGB_TWOCOMP_WIDTH-1:0]r_yuv2rgb_s10_3P;
reg [YUV2RGB_TWOCOMP_WIDTH-1:0]r_yuv2rgb_s20_3P;
reg r_rgb2yuv_de_4P;
reg [RGB2YUV_TWOCOMP_WIDTH-1:0]r_rgb2yuv_y_4P;
reg [RGB2YUV_TWOCOMP_WIDTH-1:0]r_rgb2yuv_u_4P;
reg [RGB2YUV_TWOCOMP_WIDTH-1:0]r_rgb2yuv_v_4P;
reg r_yuv2rgb_de_4P;
reg [YUV2RGB_TWOCOMP_WIDTH-1:0]r_yuv2rgb_r_4P;
reg [YUV2RGB_TWOCOMP_WIDTH-1:0]r_yuv2rgb_g_4P;
reg [YUV2RGB_TWOCOMP_WIDTH-1:0]r_yuv2rgb_b_4P;
reg [1:0]r_yuv2rgb_r_2c_4P;
reg [1:0]r_yuv2rgb_g_2c_4P;
reg [1:0]r_yuv2rgb_b_2c_4P;
reg r_rgb2yuv_de_5P;
reg [Y_DEPTH-1:0]r_rgb2yuv_y_5P;
reg [U_DEPTH-1:0]r_rgb2yuv_u_5P;
reg [B_DEPTH-1:0]r_rgb2yuv_v_5P;
reg r_yuv2rgb_de_5P;
reg [R_DEPTH-1:0]r_yuv2rgb_r_5P;
reg [G_DEPTH-1:0]r_yuv2rgb_g_5P;
reg [B_DEPTH-1:0]r_yuv2rgb_b_5P;
/*
reg r_yuv2rgb_de_6P;
reg [R_DEPTH-1:0]r_yuv2rgb_r_6P;
reg [G_DEPTH-1:0]r_yuv2rgb_g_6P;
reg [B_DEPTH-1:0]r_yuv2rgb_b_6P;
reg r_yuv2rgb_r_c_6P;
reg r_yuv2rgb_g_c_6P;
reg r_yuv2rgb_b_c_6P;
reg r_yuv2rgb_de_7P;
reg [R_DEPTH-1:0]r_yuv2rgb_r_7P;
reg [G_DEPTH-1:0]r_yuv2rgb_g_7P;
reg [B_DEPTH-1:0]r_yuv2rgb_b_7P;
*/
////////////////////////////////
// 0.299R + 0.587G + 0.114B
// - 0.147R - 0.289G + 0.436B
// 0.615R - 0.515G - 0.100B
//
// C = Y - 16 >> 2?
// D = Y - 128 >> 16?
// E = V - 128 >> 16?
//
// 298C
//
//
// 2P 2P 3P 3P 4P
// a00 + a01 = s00 + a02 = b0
// a10 + a11 = s10 + a12 = b1
// a20 + a21 = s20 + a22 = b2
//
// c00 + c01 = t00 + c02 = d0
// 0 = overflow
// = underflow
// c10 + c11 = t10 + c12 = d1
// = overflow
// = underflow
// c20 + c22 = t20 + c21 = d2
// 0 = overflow
// = underflow
////////////////////////////////
wire [RGB2YUV_TWOCOMP_WIDTH-1:0]w_rgb2yuv_a00_2P;
wire [RGB2YUV_TWOCOMP_WIDTH-1:0]w_rgb2yuv_a01_2P;
wire [RGB2YUV_TWOCOMP_WIDTH-1:0]w_rgb2yuv_a02_3P;
wire [RGB2YUV_TWOCOMP_WIDTH-1:0]w_rgb2yuv_a10_2P;
wire [RGB2YUV_TWOCOMP_WIDTH-1:0]w_rgb2yuv_a11_2P;
wire [RGB2YUV_TWOCOMP_WIDTH-1:0]w_rgb2yuv_a12_3P;
wire [RGB2YUV_TWOCOMP_WIDTH-1:0]w_rgb2yuv_a20_2P;
wire [RGB2YUV_TWOCOMP_WIDTH-1:0]w_rgb2yuv_a21_2P;
wire [RGB2YUV_TWOCOMP_WIDTH-1:0]w_rgb2yuv_a22_3P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_yuv2rgb_a00_2P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_yuv2rgb_a01_2P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_yuv2rgb_a02_3P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_yuv2rgb_a10_2P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_yuv2rgb_a11_2P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_yuv2rgb_a12_3P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_yuv2rgb_a20_2P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_yuv2rgb_a22_2P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_yuv2rgb_a21_3P;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a00_dout1;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a01_dout1;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a02_dout1;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a10_dout1;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a11_dout1;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a12_dout1;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a20_dout1;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a21_dout1;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a22_dout1;
wire w_rgb2yuv_de;
wire w_yuv2rgb_de;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a02_dout2;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a12_dout2;
wire [YUV2RGB_TWOCOMP_WIDTH-1:0]w_rom_a21_dout2;
wire c_rgb2yuv_sel;
wire c_yuv2rgb_sel;
assign c_rgb2yuv_sel = 1'b0;
assign c_yuv2rgb_sel = 1'b1;
assign w_yuv2rgb_a01_2P = {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
assign w_yuv2rgb_a22_2P = {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
//assign w_yuv2rgb_a01_2P = 6'd0;
//assign w_yuv2rgb_a22_2P = 6'd0;
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_rgb2yuv_de_1P <= 1'b0;
r_rgb2yuv_r_1P <= {R_DEPTH{1'b0}};
r_rgb2yuv_g_1P <= {G_DEPTH{1'b0}};
r_rgb2yuv_b_1P <= {B_DEPTH{1'b0}};
// r_rgb2yuv_we_1P <= 1'b0;
r_yuv2rgb_de_1P <= 1'b0;
r_yuv2rgb_y_1P <= {Y_DEPTH{1'b0}};
r_yuv2rgb_u_1P <= {U_DEPTH{1'b0}};
r_yuv2rgb_v_1P <= {V_DEPTH{1'b0}};
// r_yuv2rgb_we_1P <= 1'b0;
r_rgb2yuv_de_2P <= 1'b0;
r_yuv2rgb_de_2P <= 1'b0;
r_rgb2yuv_de_3P <= 1'b0;
r_rgb2yuv_s00_3P <= {RGB2YUV_TWOCOMP_WIDTH{1'b0}};
r_rgb2yuv_s10_3P <= {RGB2YUV_TWOCOMP_WIDTH{1'b0}};
r_rgb2yuv_s20_3P <= {RGB2YUV_TWOCOMP_WIDTH{1'b0}};
r_yuv2rgb_de_3P <= 1'b0;
r_yuv2rgb_s00_3P <= {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
r_yuv2rgb_s10_3P <= {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
r_yuv2rgb_s20_3P <= {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
r_rgb2yuv_de_4P <= 1'b0;
r_rgb2yuv_y_4P <= {RGB2YUV_TWOCOMP_WIDTH{1'b0}};
r_rgb2yuv_u_4P <= {RGB2YUV_TWOCOMP_WIDTH{1'b0}};
r_rgb2yuv_v_4P <= {RGB2YUV_TWOCOMP_WIDTH{1'b0}};
r_yuv2rgb_de_4P <= 1'b0;
r_yuv2rgb_r_4P <= {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
r_yuv2rgb_g_4P <= {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
r_yuv2rgb_b_4P <= {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
r_yuv2rgb_r_2c_4P <= 2'b00;
r_yuv2rgb_g_2c_4P <= 2'b00;
r_yuv2rgb_b_2c_4P <= 2'b00;
r_rgb2yuv_de_5P <= 1'b0;
r_rgb2yuv_y_5P <= {Y_DEPTH{1'b0}};
r_rgb2yuv_u_5P <= {U_DEPTH{1'b0}};
r_rgb2yuv_v_5P <= {V_DEPTH{1'b0}};
r_yuv2rgb_de_5P <= 1'b0;
r_yuv2rgb_r_5P <= {R_DEPTH{1'b0}};
r_yuv2rgb_g_5P <= {G_DEPTH{1'b0}};
r_yuv2rgb_b_5P <= {B_DEPTH{1'b0}};
/*
r_yuv2rgb_de_6P <= 1'b0;
r_yuv2rgb_r_6P <= {R_DEPTH{1'b0}};
r_yuv2rgb_g_6P <= {G_DEPTH{1'b0}};
r_yuv2rgb_b_6P <= {B_DEPTH{1'b0}};
r_yuv2rgb_r_c_6P <= 1'b0;
r_yuv2rgb_g_c_6P <= 1'b0;
r_yuv2rgb_b_c_6P <= 1'b0;
r_yuv2rgb_de_7P <= 1'b0;
r_yuv2rgb_r_7P <= {R_DEPTH{1'b0}};
r_yuv2rgb_g_7P <= {G_DEPTH{1'b0}};
r_yuv2rgb_b_7P <= {B_DEPTH{1'b0}};
*/
end
else
begin
r_rgb2yuv_de_1P <= w_rgb2yuv_de;
r_yuv2rgb_de_1P <= w_yuv2rgb_de;
r_rgb2yuv_de_2P <= r_rgb2yuv_de_1P;
r_yuv2rgb_de_2P <= r_yuv2rgb_de_1P;
r_rgb2yuv_de_3P <= r_rgb2yuv_de_2P;
r_yuv2rgb_de_3P <= r_yuv2rgb_de_2P;
r_rgb2yuv_de_4P <= r_rgb2yuv_de_3P;
r_yuv2rgb_de_4P <= r_yuv2rgb_de_3P;
r_rgb2yuv_de_5P <= r_rgb2yuv_de_4P;
r_yuv2rgb_de_5P <= r_yuv2rgb_de_4P;
// r_yuv2rgb_de_6P <= r_yuv2rgb_de_5P;
// r_yuv2rgb_de_7P <= r_yuv2rgb_de_6P;
/* if (i_rgb2yuv_de)
begin
r_rgb2yuv_r_1P <= {1'b0, i_rgb2yuv_r};
r_rgb2yuv_g_1P <= {1'b0, i_rgb2yuv_g};
r_rgb2yuv_b_1P <= {1'b0, i_rgb2yuv_b};
r_rgb2yuv_we_1P <= 1'b0;
end
else
begin
r_rgb2yuv_r_1P[R_DEPTH] <= 1'b1;
r_rgb2yuv_g_1P[G_DEPTH] <= 1'b1;
r_rgb2yuv_b_1P[B_DEPTH] <= 1'b1;
r_rgb2yuv_we_1P <= 1'b1;
end*/
r_rgb2yuv_r_1P <= i_rgb2yuv_r;
r_rgb2yuv_g_1P <= i_rgb2yuv_g;
r_rgb2yuv_b_1P <= i_rgb2yuv_b;
/* if (i_yuv2rgb_de)
begin
r_yuv2rgb_y_1P <= {1'b0, i_yuv2rgb_y};
r_yuv2rgb_u_1P <= {1'b0, i_yuv2rgb_u};
r_yuv2rgb_v_1P <= {1'b0, i_yuv2rgb_v};
r_yuv2rgb_we_1P <= 1'b0;
end
else
begin
r_yuv2rgb_y_1P[Y_DEPTH] <= 1'b1;
r_yuv2rgb_u_1P[U_DEPTH] <= 1'b1;
r_yuv2rgb_v_1P[V_DEPTH] <= 1'b1;
r_yuv2rgb_we_1P <= 1'b1;
end*/
r_yuv2rgb_y_1P <= i_yuv2rgb_y;
r_yuv2rgb_u_1P <= i_yuv2rgb_u;
r_yuv2rgb_v_1P <= i_yuv2rgb_v;
r_rgb2yuv_s00_3P <= w_rgb2yuv_a00_2P + w_rgb2yuv_a01_2P;
r_rgb2yuv_s10_3P <= w_rgb2yuv_a10_2P + w_rgb2yuv_a11_2P;
r_rgb2yuv_s20_3P <= w_rgb2yuv_a20_2P + w_rgb2yuv_a21_2P;
r_yuv2rgb_s00_3P <= w_yuv2rgb_a00_2P + w_yuv2rgb_a01_2P;
r_yuv2rgb_s10_3P <= w_yuv2rgb_a10_2P + w_yuv2rgb_a11_2P;
r_yuv2rgb_s20_3P <= w_yuv2rgb_a20_2P + w_yuv2rgb_a22_2P;
r_rgb2yuv_y_4P <= r_rgb2yuv_s00_3P + w_rgb2yuv_a02_3P + Y_OFFSET;
r_rgb2yuv_u_4P <= r_rgb2yuv_s10_3P + w_rgb2yuv_a12_3P + 8'd128;
r_rgb2yuv_v_4P <= r_rgb2yuv_s20_3P + w_rgb2yuv_a22_3P + 8'd128;
r_yuv2rgb_r_4P <= r_yuv2rgb_s00_3P + w_yuv2rgb_a02_3P;
r_yuv2rgb_g_4P <= r_yuv2rgb_s10_3P + w_yuv2rgb_a12_3P;
r_yuv2rgb_b_4P <= r_yuv2rgb_s20_3P + w_yuv2rgb_a21_3P;
r_yuv2rgb_r_2c_4P <= {r_yuv2rgb_s00_3P[YUV2RGB_TWOCOMP_WIDTH-1], w_yuv2rgb_a02_3P[YUV2RGB_TWOCOMP_WIDTH-1]};
r_yuv2rgb_g_2c_4P <= {r_yuv2rgb_s10_3P[YUV2RGB_TWOCOMP_WIDTH-1], w_yuv2rgb_a12_3P[YUV2RGB_TWOCOMP_WIDTH-1]};
r_yuv2rgb_b_2c_4P <= {r_yuv2rgb_s20_3P[YUV2RGB_TWOCOMP_WIDTH-1], w_yuv2rgb_a21_3P[YUV2RGB_TWOCOMP_WIDTH-1]};
// r_rgb2yuv_y_5P <= r_rgb2yuv_y_4P[Y_DEPTH-1:0]+8'd16;
if (r_rgb2yuv_y_4P[RGB2YUV_TWOCOMP_WIDTH-1])
r_rgb2yuv_y_5P <= {Y_DEPTH{1'b1}};
else
r_rgb2yuv_y_5P <= r_rgb2yuv_y_4P[Y_DEPTH-1:0]/*+Y_OFFSET*/;
if (r_rgb2yuv_u_4P[RGB2YUV_TWOCOMP_WIDTH-1])
// r_rgb2yuv_u_5P <= {U_DEPTH{1'b0}};
r_rgb2yuv_u_5P <= {U_DEPTH{1'b1}};
else
r_rgb2yuv_u_5P <= r_rgb2yuv_u_4P[U_DEPTH-1:0]/*+8'd128*/;
if (r_rgb2yuv_v_4P[RGB2YUV_TWOCOMP_WIDTH-1])
// r_rgb2yuv_v_5P <= {V_DEPTH{1'b0}};
r_rgb2yuv_v_5P <= {V_DEPTH{1'b1}};
else
r_rgb2yuv_v_5P <= r_rgb2yuv_v_4P[V_DEPTH-1:0]/*+8'd128*/;
if (r_yuv2rgb_r_2c_4P[1] & r_yuv2rgb_r_2c_4P[0] & ~r_yuv2rgb_r_4P[YUV2RGB_TWOCOMP_WIDTH-1])
r_yuv2rgb_r_5P <= {R_DEPTH{1'b0}};
else if (~r_yuv2rgb_r_2c_4P[1] & ~r_yuv2rgb_r_2c_4P[0] & r_yuv2rgb_r_4P[YUV2RGB_TWOCOMP_WIDTH-1])
r_yuv2rgb_r_5P <= {R_DEPTH{1'b1}};
else if (r_yuv2rgb_r_4P[YUV2RGB_TWOCOMP_WIDTH-1])
r_yuv2rgb_r_5P <= {R_DEPTH{1'b0}};
else if (r_yuv2rgb_r_4P[YUV2RGB_TWOCOMP_WIDTH-2])
r_yuv2rgb_r_5P <= {R_DEPTH{1'b1}};
else
r_yuv2rgb_r_5P <= r_yuv2rgb_r_4P[R_DEPTH-1:0];
if (r_yuv2rgb_g_2c_4P[1] & r_yuv2rgb_g_2c_4P[0] & ~r_yuv2rgb_g_4P[YUV2RGB_TWOCOMP_WIDTH-1])
r_yuv2rgb_g_5P <= {G_DEPTH{1'b0}};
else if (~r_yuv2rgb_g_2c_4P[1] & ~r_yuv2rgb_g_2c_4P[0] & r_yuv2rgb_g_4P[YUV2RGB_TWOCOMP_WIDTH-1])
r_yuv2rgb_g_5P <= {G_DEPTH{1'b1}};
else if (r_yuv2rgb_g_4P[YUV2RGB_TWOCOMP_WIDTH-1])
r_yuv2rgb_g_5P <= {G_DEPTH{1'b0}};
else if (r_yuv2rgb_g_4P[YUV2RGB_TWOCOMP_WIDTH-2])
r_yuv2rgb_g_5P <= {G_DEPTH{1'b1}};
else
r_yuv2rgb_g_5P <= r_yuv2rgb_g_4P[G_DEPTH-1:0];
if (r_yuv2rgb_b_2c_4P[1] & r_yuv2rgb_b_2c_4P[0] & ~r_yuv2rgb_b_4P[YUV2RGB_TWOCOMP_WIDTH-1])
r_yuv2rgb_b_5P <= {B_DEPTH{1'b0}};
else if (~r_yuv2rgb_b_2c_4P[1] & ~r_yuv2rgb_b_2c_4P[0] & r_yuv2rgb_b_4P[YUV2RGB_TWOCOMP_WIDTH-1])
r_yuv2rgb_b_5P <= {B_DEPTH{1'b1}};
else if (r_yuv2rgb_b_4P[YUV2RGB_TWOCOMP_WIDTH-1])
r_yuv2rgb_b_5P <= {B_DEPTH{1'b0}};
else if (r_yuv2rgb_b_4P[YUV2RGB_TWOCOMP_WIDTH-2])
r_yuv2rgb_b_5P <= {B_DEPTH{1'b1}};
else
r_yuv2rgb_b_5P <= r_yuv2rgb_b_4P[B_DEPTH-1:0];
/* r_yuv2rgb_r_6P <= r_yuv2rgb_r_5P+5'd2;
r_yuv2rgb_r_c_6P <= r_yuv2rgb_r_5P[R_DEPTH-1];
r_yuv2rgb_g_6P <= r_yuv2rgb_g_5P+5'd2;
r_yuv2rgb_g_c_6P <= r_yuv2rgb_g_5P[G_DEPTH-1];
r_yuv2rgb_g_6P <= r_yuv2rgb_g_5P;
r_yuv2rgb_b_6P <= r_yuv2rgb_b_5P+5'd2;
r_yuv2rgb_b_c_6P <= r_yuv2rgb_b_5P[B_DEPTH-1];
if (~r_yuv2rgb_r_c_6P & r_yuv2rgb_r_6P[R_DEPTH-1])
r_yuv2rgb_r_7P <= {R_DEPTH{1'b1}};
else
r_yuv2rgb_r_7P <= r_yuv2rgb_r_6P;
if (~r_yuv2rgb_g_c_6P & r_yuv2rgb_g_6P[G_DEPTH-1])
r_yuv2rgb_g_7P <= {R_DEPTH{1'b1}};
else
r_yuv2rgb_g_7P <= r_yuv2rgb_g_6P;
if (~r_yuv2rgb_b_c_6P & r_yuv2rgb_b_6P[B_DEPTH-1])
r_yuv2rgb_b_7P <= {B_DEPTH{1'b1}};
else
r_yuv2rgb_b_7P <= r_yuv2rgb_b_6P;*/
end
end
true_dual_port_ram
#(
.DATA_WIDTH(YUV2RGB_TWOCOMP_WIDTH),
// .ADDR_WIDTH(1+1+YUV2RGB_TWOCOMP_WIDTH-1),
// .ADDR_WIDTH(1+1+R_DEPTH),
.ADDR_WIDTH(1+R_DEPTH),
.WRITE_MODE_1("WRITE_FIRST"),
.WRITE_MODE_2("WRITE_FIRST"),
.OUTPUT_REG_1(OUTPUT_REG),
.OUTPUT_REG_2(OUTPUT_REG),
.RAM_INIT_FILE(ROM_A00),
.RAM_INIT_RADIX("HEX")
)
inst_rom_a00
(
.clka (i_pclk),
// .we1 (r_rgb2yuv_we_1P),
// .addr1 ({r_rgb2yuv_r_1P[R_DEPTH], c_rgb2yuv_sel, r_rgb2yuv_r_1P[R_DEPTH-1:0]}),
.we1 (1'b0),
.addr1 ({c_rgb2yuv_sel, r_rgb2yuv_r_1P[R_DEPTH-1:0]}),
.din1 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout1 (w_rgb2yuv_a00_2P),
.dout1 (w_rom_a00_dout1),
.clkb (i_pclk),
// .we2 (r_yuv2rgb_we_1P),
// .addr2 ({r_yuv2rgb_y_1P[Y_DEPTH], c_yuv2rgb_sel, r_yuv2rgb_y_1P[Y_DEPTH-1:0]}),
.we2 (1'b0),
.addr2 ({c_yuv2rgb_sel, r_yuv2rgb_y_1P[Y_DEPTH-1:0]}),
.din2 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
.dout2 (w_yuv2rgb_a00_2P)
);
assign w_rgb2yuv_a00_2P = w_rom_a00_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
true_dual_port_ram
#(
.DATA_WIDTH(YUV2RGB_TWOCOMP_WIDTH),
// .ADDR_WIDTH(1+1+YUV2RGB_TWOCOMP_WIDTH-1),
// .ADDR_WIDTH(1+1+G_DEPTH),
.ADDR_WIDTH(1+G_DEPTH),
.WRITE_MODE_1("WRITE_FIRST"),
.WRITE_MODE_2("WRITE_FIRST"),
.OUTPUT_REG_1(OUTPUT_REG),
.OUTPUT_REG_2(OUTPUT_REG),
.RAM_INIT_FILE(ROM_A01),
.RAM_INIT_RADIX("HEX")
)
inst_rom_a01
(
.clka (i_pclk),
// .we1 (r_rgb2yuv_we_1P),
// .addr1 ({r_rgb2yuv_g_1P[G_DEPTH], c_rgb2yuv_sel, r_rgb2yuv_g_1P[G_DEPTH-1:0]}),
.we1 (1'b0),
.addr1 ({c_rgb2yuv_sel, r_rgb2yuv_g_1P[G_DEPTH-1:0]}),
.din1 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout1 (w_rgb2yuv_a01_2P),
.dout1 (w_rom_a01_dout1),
.clkb (i_pclk),
// .we2 (r_yuv2rgb_we_1P),
// .addr2 ({r_yuv2rgb_u_1P[U_DEPTH], c_yuv2rgb_sel, r_yuv2rgb_u_1P[U_DEPTH-1:0]}),
.we2 (1'b0),
.addr2 ({c_yuv2rgb_sel, r_yuv2rgb_u_1P[U_DEPTH-1:0]}),
.din2 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout2 (w_yuv2rgb_a01_2P),
.dout2 ()
);
assign w_rgb2yuv_a01_2P = w_rom_a01_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
true_dual_port_ram
#(
.DATA_WIDTH(YUV2RGB_TWOCOMP_WIDTH),
// .ADDR_WIDTH(1+1+YUV2RGB_TWOCOMP_WIDTH-1),
// .ADDR_WIDTH(1+1+B_DEPTH),
.ADDR_WIDTH(1+B_DEPTH),
.WRITE_MODE_1("WRITE_FIRST"),
.WRITE_MODE_2("WRITE_FIRST"),
.OUTPUT_REG_1("TRUE"),
.OUTPUT_REG_2("TRUE"),
.RAM_INIT_FILE(ROM_A02),
.RAM_INIT_RADIX("HEX")
)
inst_rom_a02
(
.clka (i_pclk),
// .we1 (r_rgb2yuv_we_1P),
// .addr1 ({r_rgb2yuv_b_1P[B_DEPTH], c_rgb2yuv_sel, r_rgb2yuv_b_1P[B_DEPTH-1:0]}),
.we1 (1'b0),
.addr1 ({c_rgb2yuv_sel, r_rgb2yuv_b_1P[B_DEPTH-1:0]}),
.din1 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout1 (w_rgb2yuv_a02_3P),
.dout1 (w_rom_a02_dout1),
.clkb (i_pclk),
// .we2 (r_yuv2rgb_we_1P),
// .addr2 ({r_yuv2rgb_v_1P[V_DEPTH], c_yuv2rgb_sel, r_yuv2rgb_v_1P[V_DEPTH-1:0]}),
.we2 (1'b0),
.addr2 ({c_yuv2rgb_sel, r_yuv2rgb_v_1P[V_DEPTH-1:0]}),
.din2 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout2 (w_yuv2rgb_a02_3P)
.dout2 (w_rom_a02_dout2)
);
generate
if (OUTPUT_REG == "TRUE")
begin
assign w_rgb2yuv_a02_3P = r_rom_a02_dout1_P;
assign w_yuv2rgb_a02_3P = r_rom_a02_dout2_P;
end
else
begin
assign w_rgb2yuv_a02_3P = w_rom_a02_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
assign w_yuv2rgb_a02_3P = w_rom_a02_dout2;
end
endgenerate
true_dual_port_ram
#(
.DATA_WIDTH(YUV2RGB_TWOCOMP_WIDTH),
// .ADDR_WIDTH(1+1+YUV2RGB_TWOCOMP_WIDTH-1),
// .ADDR_WIDTH(1+1+R_DEPTH),
.ADDR_WIDTH(1+R_DEPTH),
.WRITE_MODE_1("WRITE_FIRST"),
.WRITE_MODE_2("WRITE_FIRST"),
.OUTPUT_REG_1(OUTPUT_REG),
.OUTPUT_REG_2(OUTPUT_REG),
.RAM_INIT_FILE(ROM_A10),
.RAM_INIT_RADIX("HEX")
)
inst_rom_a10
(
.clka (i_pclk),
// .we1 (r_rgb2yuv_we_1P),
// .addr1 ({r_rgb2yuv_r_1P[R_DEPTH], c_rgb2yuv_sel, r_rgb2yuv_r_1P[R_DEPTH-1:0]}),
.we1 (1'b0),
.addr1 ({c_rgb2yuv_sel, r_rgb2yuv_r_1P[R_DEPTH-1:0]}),
.din1 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout1 (w_rgb2yuv_a10_2P),
.dout1 (w_rom_a10_dout1),
.clkb (i_pclk),
// .we2 (r_yuv2rgb_we_1P),
// .addr2 ({r_yuv2rgb_y_1P[Y_DEPTH], c_yuv2rgb_sel, r_yuv2rgb_y_1P[Y_DEPTH-1:0]}),
.we2 (1'b0),
.addr2 ({c_yuv2rgb_sel, r_yuv2rgb_y_1P[Y_DEPTH-1:0]}),
.din2 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
.dout2 (w_yuv2rgb_a10_2P)
);
assign w_rgb2yuv_a10_2P = w_rom_a10_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
true_dual_port_ram
#(
.DATA_WIDTH(YUV2RGB_TWOCOMP_WIDTH),
// .ADDR_WIDTH(1+1+YUV2RGB_TWOCOMP_WIDTH-1),
// .ADDR_WIDTH(1+1+G_DEPTH),
.ADDR_WIDTH(1+G_DEPTH),
.WRITE_MODE_1("WRITE_FIRST"),
.WRITE_MODE_2("WRITE_FIRST"),
.OUTPUT_REG_1(OUTPUT_REG),
.OUTPUT_REG_2(OUTPUT_REG),
.RAM_INIT_FILE(ROM_A11),
.RAM_INIT_RADIX("HEX")
)
inst_rom_a11
(
.clka (i_pclk),
// .we1 (r_rgb2yuv_we_1P),
// .addr1 ({r_rgb2yuv_g_1P[G_DEPTH], c_rgb2yuv_sel, r_rgb2yuv_g_1P[G_DEPTH-1:0]}),
.we1 (1'b0),
.addr1 ({c_rgb2yuv_sel, r_rgb2yuv_g_1P[G_DEPTH-1:0]}),
.din1 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout1 (w_rgb2yuv_a11_2P),
.dout1 (w_rom_a11_dout1),
.clkb (i_pclk),
// .we2 (r_yuv2rgb_we_1P),
// .addr2 ({r_yuv2rgb_u_1P[U_DEPTH], c_yuv2rgb_sel, r_yuv2rgb_u_1P[U_DEPTH-1:0]}),
.we2 (1'b0),
.addr2 ({c_yuv2rgb_sel, r_yuv2rgb_u_1P[U_DEPTH-1:0]}),
.din2 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
.dout2 (w_yuv2rgb_a11_2P)
);
assign w_rgb2yuv_a11_2P = w_rom_a11_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
true_dual_port_ram
#(
.DATA_WIDTH(YUV2RGB_TWOCOMP_WIDTH),
// .ADDR_WIDTH(1+1+YUV2RGB_TWOCOMP_WIDTH-1),
// .ADDR_WIDTH(1+1+B_DEPTH),
.ADDR_WIDTH(1+B_DEPTH),
.WRITE_MODE_1("WRITE_FIRST"),
.WRITE_MODE_2("WRITE_FIRST"),
.OUTPUT_REG_1("TRUE"),
.OUTPUT_REG_2("TRUE"),
.RAM_INIT_FILE(ROM_A12),
.RAM_INIT_RADIX("HEX")
)
inst_rom_a12
(
.clka (i_pclk),
// .we1 (r_rgb2yuv_we_1P),
// .addr1 ({r_rgb2yuv_b_1P[B_DEPTH], c_rgb2yuv_sel, r_rgb2yuv_b_1P[B_DEPTH-1:0]}),
.we1 (1'b0),
.addr1 ({c_rgb2yuv_sel, r_rgb2yuv_b_1P[B_DEPTH-1:0]}),
.din1 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout1 (w_rgb2yuv_a12_3P),
.dout1 (w_rom_a12_dout1),
.clkb (i_pclk),
// .we2 (r_yuv2rgb_we_1P),
// .addr2 ({r_yuv2rgb_v_1P[B_DEPTH], c_yuv2rgb_sel, r_yuv2rgb_v_1P[B_DEPTH-1:0]}),
.we2 (1'b0),
.addr2 ({c_yuv2rgb_sel, r_yuv2rgb_v_1P[B_DEPTH-1:0]}),
.din2 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout2 (w_yuv2rgb_a12_3P)
.dout2 (w_rom_a12_dout2)
);
generate
if (OUTPUT_REG == "TRUE")
begin
assign w_rgb2yuv_a12_3P = r_rom_a12_dout1_P;
assign w_yuv2rgb_a12_3P = r_rom_a12_dout2_P;
end
else
begin
assign w_rgb2yuv_a12_3P = w_rom_a12_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
assign w_yuv2rgb_a12_3P = w_rom_a12_dout2;
end
endgenerate
true_dual_port_ram
#(
.DATA_WIDTH(YUV2RGB_TWOCOMP_WIDTH),
// .ADDR_WIDTH(1+1+YUV2RGB_TWOCOMP_WIDTH-1),
// .ADDR_WIDTH(1+1+R_DEPTH),
.ADDR_WIDTH(1+R_DEPTH),
.WRITE_MODE_1("WRITE_FIRST"),
.WRITE_MODE_2("WRITE_FIRST"),
.OUTPUT_REG_1(OUTPUT_REG),
.OUTPUT_REG_2(OUTPUT_REG),
.RAM_INIT_FILE(ROM_A20),
.RAM_INIT_RADIX("HEX")
)
inst_rom_a20
(
.clka (i_pclk),
// .we1 (r_rgb2yuv_we_1P),
// .addr1 ({r_rgb2yuv_r_1P[R_DEPTH], c_rgb2yuv_sel, r_rgb2yuv_r_1P[R_DEPTH-1:0]}),
.we1 (1'b0),
.addr1 ({c_rgb2yuv_sel, r_rgb2yuv_r_1P[R_DEPTH-1:0]}),
.din1 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout1 (w_rgb2yuv_a20_2P),
.dout1 (w_rom_a20_dout1),
.clkb (i_pclk),
// .we2 (r_yuv2rgb_we_1P),
// .addr2 ({r_yuv2rgb_y_1P[Y_DEPTH], c_yuv2rgb_sel, r_yuv2rgb_y_1P[Y_DEPTH-1:0]}),
.we2 (1'b0),
.addr2 ({c_yuv2rgb_sel, r_yuv2rgb_y_1P[Y_DEPTH-1:0]}),
.din2 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
.dout2 (w_yuv2rgb_a20_2P)
);
assign w_rgb2yuv_a20_2P = w_rom_a20_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
true_dual_port_ram
#(
.DATA_WIDTH(YUV2RGB_TWOCOMP_WIDTH),
// .ADDR_WIDTH(1+1+YUV2RGB_TWOCOMP_WIDTH-1),
// .ADDR_WIDTH(1+1+G_DEPTH),
.ADDR_WIDTH(1+G_DEPTH),
.WRITE_MODE_1("WRITE_FIRST"),
.WRITE_MODE_2("WRITE_FIRST"),
.OUTPUT_REG_1(OUTPUT_REG),
.OUTPUT_REG_2("TRUE"),
.RAM_INIT_FILE(ROM_A21),
.RAM_INIT_RADIX("HEX")
)
inst_rom_a21
(
.clka (i_pclk),
// .we1 (r_rgb2yuv_we_1P),
// .addr1 ({r_rgb2yuv_g_1P[G_DEPTH], c_rgb2yuv_sel, r_rgb2yuv_g_1P[G_DEPTH-1:0]}),
.we1 (1'b0),
.addr1 ({c_rgb2yuv_sel, r_rgb2yuv_g_1P[G_DEPTH-1:0]}),
.din1 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout1 (w_rgb2yuv_a21_2P),
.dout1 (w_rom_a21_dout1),
.clkb (i_pclk),
// .we2 (r_yuv2rgb_we_1P),
// .addr2 ({r_yuv2rgb_u_1P[U_DEPTH], c_yuv2rgb_sel, r_yuv2rgb_u_1P[U_DEPTH-1:0]}),
.we2 (1'b0),
.addr2 ({c_yuv2rgb_sel, r_yuv2rgb_u_1P[U_DEPTH-1:0]}),
.din2 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout2 (w_yuv2rgb_a21_3P)
.dout2 (w_rom_a21_dout2)
);
assign w_rgb2yuv_a21_2P = w_rom_a21_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
generate
if (OUTPUT_REG == "TRUE")
begin
assign w_yuv2rgb_a21_3P = r_rom_a21_dout2_P;
end
else
begin
assign w_yuv2rgb_a21_3P = w_rom_a21_dout2;
end
endgenerate
true_dual_port_ram
#(
.DATA_WIDTH(YUV2RGB_TWOCOMP_WIDTH),
// .ADDR_WIDTH(1+1+YUV2RGB_TWOCOMP_WIDTH-1),
// .ADDR_WIDTH(1+1+B_DEPTH),
.ADDR_WIDTH(1+B_DEPTH),
.WRITE_MODE_1("WRITE_FIRST"),
.WRITE_MODE_2("WRITE_FIRST"),
.OUTPUT_REG_1(OUTPUT_REG),
.OUTPUT_REG_2("FALSE"),
.RAM_INIT_FILE(ROM_A22),
.RAM_INIT_RADIX("HEX")
)
inst_rom_a22
(
.clka (i_pclk),
// .we1 (r_rgb2yuv_we_1P),
// .addr1 ({r_rgb2yuv_b_1P[B_DEPTH], c_rgb2yuv_sel, r_rgb2yuv_b_1P[B_DEPTH-1:0]}),
.we1 (1'b0),
.addr1 ({c_rgb2yuv_sel, r_rgb2yuv_b_1P[B_DEPTH-1:0]}),
.din1 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout1 (w_rgb2yuv_a22_3P),
.dout1 (w_rom_a22_dout1),
.clkb (i_pclk),
// .we2 (r_yuv2rgb_we_1P),
// .addr2 ({r_yuv2rgb_v_1P[V_DEPTH], c_yuv2rgb_sel, r_yuv2rgb_v_1P[V_DEPTH-1:0]}),
.we2 (1'b0),
.addr2 ({c_yuv2rgb_sel, r_yuv2rgb_v_1P[V_DEPTH-1:0]}),
.din2 ({YUV2RGB_TWOCOMP_WIDTH{1'b0}}),
// .dout2 (w_yuv2rgb_a22_2P),
.dout2 ()
);
generate
if (OUTPUT_REG == "TRUE")
begin
assign w_rgb2yuv_a22_3P = r_rom_a22_dout1_P;
assign w_rgb2yuv_de = r_rgb2yuv_de_P;
assign w_yuv2rgb_de = r_yuv2rgb_de_P;
end
else
begin
assign w_rgb2yuv_a22_3P = w_rom_a22_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
assign w_rgb2yuv_de = i_rgb2yuv_de;
assign w_yuv2rgb_de = i_yuv2rgb_de;
end
endgenerate
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_rgb2yuv_de_P <= 1'b0;
r_yuv2rgb_de_P <= 1'b0;
r_rom_a02_dout1_P <= {RGB2YUV_TWOCOMP_WIDTH{1'b0}};
r_rom_a02_dout2_P <= {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
r_rom_a12_dout1_P <= {RGB2YUV_TWOCOMP_WIDTH{1'b0}};
r_rom_a12_dout2_P <= {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
r_rom_a21_dout2_P <= {YUV2RGB_TWOCOMP_WIDTH{1'b0}};
r_rom_a22_dout1_P <= {RGB2YUV_TWOCOMP_WIDTH{1'b0}};
end
else
begin
r_rgb2yuv_de_P <= i_rgb2yuv_de;
r_yuv2rgb_de_P <= i_yuv2rgb_de;
r_rom_a02_dout1_P <= w_rom_a02_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
r_rom_a02_dout2_P <= w_rom_a02_dout2;
r_rom_a12_dout1_P <= w_rom_a12_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
r_rom_a12_dout2_P <= w_rom_a12_dout2;
r_rom_a21_dout2_P <= w_rom_a21_dout2;
r_rom_a22_dout1_P <= w_rom_a22_dout1[RGB2YUV_TWOCOMP_WIDTH-1:0];
end
end
assign o_rgb2yuv_de = r_rgb2yuv_de_5P;
assign o_rgb2yuv_y = r_rgb2yuv_y_5P;
assign o_rgb2yuv_u = r_rgb2yuv_u_5P;
assign o_rgb2yuv_v = r_rgb2yuv_v_5P;
assign o_yuv2rgb_de = r_yuv2rgb_de_5P;
assign o_yuv2rgb_r = r_yuv2rgb_r_5P;
assign o_yuv2rgb_g = r_yuv2rgb_g_5P;
assign o_yuv2rgb_b = r_yuv2rgb_b_5P;
endmodule |
module multi_p2_ext5
#(
parameter D_WIDTH = 8
)
(
input i_arst,
input i_clk,
input [D_WIDTH-1:0]i_d,
output [D_WIDTH+5-1:0]o_q
);
reg [D_WIDTH+5-1:0]r_q_1P;
wire [D_WIDTH+5-1:0]w_d_0P;
assign w_d_0P = {4'b0, i_d, 1'b0};
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_q_1P <= {D_WIDTH+5{1'b0}};
else
r_q_1P <= w_d_0P;
end
assign o_q = r_q_1P;
endmodule |
module sobel_scharr
#(
parameter Y_DEPTH = 8
)
(
input i_arst,
input i_pclk,
input [Y_DEPTH-1:0]i_pixel_11_01,
input [Y_DEPTH-1:0]i_pixel_00_01,
input [Y_DEPTH-1:0]i_pixel_01_01,
output [Y_DEPTH-1:0]o_pixel
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// x -1 0 +1 y
//
// -1 0 1 -1
// -2 0 2 0
// -1 0 1 +1
//
// -1 -2 -1 -1
// 0 0 0 0
// 1 2 1 +1
//
// PL_11_11_2P PL_11_00_1P PL_11_01_0P
// PL_00_11_2P PL_00_00_1P PL_00_01_0P
// PL_01_11_2P PL_01_00_1P PL_01_01_0P
//
// GX_11_11_3P GX_11_00_2P GX_11_01_1P
// GX_00_11_3P GX_00_00_2P GX_00_01_1P
// GX_01_11_3P GX_01_00_2P GX_01_01_1P
// 0
// GXS_11_4P GX_11_01_2P GXS_11_5P
// GXS_00_4P GX_00_01_2P GXS_00_5P GXS_00_6P GXS_00_7P
// GXS_01_4P GX_01_01_2P GXS_01_5P GXS_01_6P
//
// GY_11_11_3P GY_11_00_2P GY_11_01_1P
// GY_00_11_3P GY_00_00_2P GY_00_01_1P 0
// GY_01_11_3P GY_01_00_2P GY_01_01_1P
//
// GYS_11_4P GY_11_01_2P GYS_11_5P
// GYS_00_4P GY_00_01_2P GYS_00_5P GYS_00_6P GYS_00_7P
// GYS_01_4P GY_01_01_2P GYS_01_5P GYS_01_6P
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [Y_DEPTH-1:0]r_p_11_00_1P, r_p_11_11_2P;
reg [Y_DEPTH-1:0]r_p_00_00_1P, r_p_00_11_2P;
reg [Y_DEPTH-1:0]r_p_01_00_1P, r_p_01_11_2P;
reg [Y_DEPTH+5-1:0]r_gx_11_01_2P;
reg [Y_DEPTH+5-1:0]r_gx_00_01_2P;
reg [Y_DEPTH+5-1:0]r_gx_01_01_2P;
reg [Y_DEPTH+5-1:0]r_gxs_11_4P, r_gxs_11_5P;
reg [Y_DEPTH+5-1:0]r_gxs_00_4P, r_gxs_00_5P, r_gxs_00_6P, r_gxs_00_7P;
reg [Y_DEPTH+5-1:0]r_gxs_01_4P, r_gxs_01_5P, r_gxs_01_6P;
reg [Y_DEPTH+5-1:0]r_gy_11_01_2P;
reg [Y_DEPTH+5-1:0]r_gy_00_01_2P;
reg [Y_DEPTH+5-1:0]r_gy_01_01_2P;
reg [Y_DEPTH+5-1:0]r_gys_11_4P, r_gys_11_5P;
reg [Y_DEPTH+5-1:0]r_gys_00_4P, r_gys_00_5P, r_gys_00_6P, r_gys_00_7P;
reg [Y_DEPTH+5-1:0]r_gys_01_4P, r_gys_01_5P, r_gys_01_6P;
reg [Y_DEPTH+5-1:0]r_gxs_00_8P;
reg [Y_DEPTH+5-1:0]r_gys_00_8P;
reg [Y_DEPTH+5-1:0]r_g_9P;
reg [Y_DEPTH-1:0]r_g_10P;
////////
wire [Y_DEPTH+5-1:0]w_xp1_11_01_1P, w_xp2_11_01_1P;
wire [Y_DEPTH+5-1:0]w_gx_11_00_2P;
wire [Y_DEPTH+5-1:0]w_xn1_11_11_3P, w_xn2_11_11_3P;
////
wire [Y_DEPTH+5-1:0]w_xp2_00_01_1P, w_xp8_00_01_1P;
wire [Y_DEPTH+5-1:0]w_gx_00_00_2P;
wire [Y_DEPTH+5-1:0]w_xn2_00_11_3P, w_xn8_00_11_3P;
////
wire [Y_DEPTH+5-1:0]w_xp1_01_01_1P, w_xp2_01_01_1P;
wire [Y_DEPTH+5-1:0]w_gx_01_00_2P;
wire [Y_DEPTH+5-1:0]w_xn1_01_11_3P, w_xn2_01_11_3P;
////////
wire [Y_DEPTH+5-1:0]w_yn1_11_01_1P, w_yn2_11_01_1P;
wire [Y_DEPTH+5-1:0]w_yn2_11_00_2P, w_yn8_11_00_2P;
wire [Y_DEPTH+5-1:0]w_yn1_11_11_3P, w_yn2_11_11_3P;
////
wire [Y_DEPTH+5-1:0]w_gy_00_11_3P, w_gy_00_00_2P, w_gy_00_01_1P;
////
wire [Y_DEPTH+5-1:0]w_yn1_01_01_1P, w_yn2_01_01_1P;
wire [Y_DEPTH+5-1:0]w_yp2_01_00_2P, w_yp8_01_00_2P;
wire [Y_DEPTH+5-1:0]w_yn1_01_11_3P, w_yn2_01_11_3P;
assign w_gx_11_00_2P = {Y_DEPTH+5{1'b0}};
assign w_gx_00_00_2P = {Y_DEPTH+5{1'b0}};
assign w_gx_01_00_2P = {Y_DEPTH+5{1'b0}};
assign w_gy_00_11_3P = {Y_DEPTH+5{1'b0}};
assign w_gy_00_00_2P = {Y_DEPTH+5{1'b0}};
assign w_gy_00_01_1P = {Y_DEPTH+5{1'b0}};
////////////////////////////////////////////////////////////////
// x - 1
multi_n1_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xn1_11_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_11_11_2P),
.o_q (w_xn1_11_11_3P)
);
multi_n2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xn2_11_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_11_11_2P),
.o_q (w_xn2_11_11_3P)
);
////
multi_n2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xn2_00_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_00_11_2P),
.o_q (w_xn2_00_11_3P)
);
multi_n8_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xn8_00_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_00_11_2P),
.o_q (w_xn8_00_11_3P)
);
////
multi_n1_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xn1_01_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_01_11_2P),
.o_q (w_xn1_01_11_3P)
);
multi_n2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xn2_01_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_01_11_2P),
.o_q (w_xn2_01_11_3P)
);
////////////////////////////////////////////////////////////////
// x + 1
multi_p1_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xp1_11_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_11_01),
.o_q (w_xp1_11_01_1P)
);
multi_p2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xp2_11_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_11_01),
.o_q (w_xp2_11_01_1P)
);
////
multi_p2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xp2_00_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_00_01),
.o_q (w_xp2_00_01_1P)
);
multi_p8_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xp8_00_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_00_01),
.o_q (w_xp8_00_01_1P)
);
////
multi_p1_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xp1_01_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_01_01),
.o_q (w_xp1_01_01_1P)
);
multi_p2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_xp2_01_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_01_01),
.o_q (w_xp2_01_01_1P)
);
////////////////////////////////////////////////////////////////
// y - 1
multi_n1_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yn1_11_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_11_01),
.o_q (w_yn1_11_01_1P)
);
multi_n2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yn2_11_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_11_01),
.o_q (w_yn2_11_01_1P)
);
////
multi_n2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yn2_11_00
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_11_00_1P),
.o_q (w_yn2_11_00_2P)
);
multi_n8_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yn8_11_00
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_11_00_1P),
.o_q (w_yn8_11_00_2P)
);
///
multi_n1_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yn1_11_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_11_11_2P),
.o_q (w_yn1_11_11_3P)
);
multi_n2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yn2_11_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_11_11_2P),
.o_q (w_yn2_11_11_3P)
);
////////////////////////////////////////////////////////////////
// y + 1
multi_p1_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yp1_01_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_01_01),
.o_q (w_yn1_01_01_1P)
);
multi_p2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yp2_01_01
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (i_pixel_01_01),
.o_q (w_yn2_01_01_1P)
);
////
multi_p2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yp2_01_00
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_01_00_1P),
.o_q (w_yp2_01_00_2P)
);
multi_p8_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yp8_01_00
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_01_00_1P),
.o_q (w_yp8_01_00_2P)
);
////
multi_p1_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yp1_01_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_01_11_2P),
.o_q (w_yn1_01_11_3P)
);
multi_p2_ext5
#(
.D_WIDTH(Y_DEPTH)
)
inst_yp2_01_11
(
.i_arst (i_arst),
.i_clk (i_pclk),
.i_d (r_p_01_11_2P),
.o_q (w_yn2_01_11_3P)
);
always@(posedge i_arst or posedge i_pclk)
begin
if (i_arst)
begin
r_p_11_00_1P <= {Y_DEPTH{1'b0}};
r_p_11_11_2P <= {Y_DEPTH{1'b0}};
r_p_00_00_1P <= {Y_DEPTH{1'b0}};
r_p_00_11_2P <= {Y_DEPTH{1'b0}};
r_p_01_00_1P <= {Y_DEPTH{1'b0}};
r_p_01_11_2P <= {Y_DEPTH{1'b0}};
////////////////////////////////
r_gx_11_01_2P <= {Y_DEPTH+4{1'b0}};
r_gx_00_01_2P <= {Y_DEPTH+4{1'b0}};
r_gx_01_01_2P <= {Y_DEPTH+4{1'b0}};
r_gxs_11_4P <= {Y_DEPTH+4{1'b0}};
r_gxs_00_4P <= {Y_DEPTH+4{1'b0}};
r_gxs_01_4P <= {Y_DEPTH+4{1'b0}};
r_gxs_11_5P <= {Y_DEPTH+4{1'b0}};
r_gxs_00_5P <= {Y_DEPTH+4{1'b0}};
r_gxs_01_5P <= {Y_DEPTH+4{1'b0}};
r_gxs_00_6P <= {Y_DEPTH+4{1'b0}};
r_gxs_01_6P <= {Y_DEPTH+4{1'b0}};
r_gxs_00_7P <= {Y_DEPTH+4{1'b0}};
////////////////////////////////
r_gy_11_01_2P <= {Y_DEPTH+4{1'b0}};
r_gy_00_01_2P <= {Y_DEPTH+4{1'b0}};
r_gy_01_01_2P <= {Y_DEPTH+4{1'b0}};
r_gys_11_4P <= {Y_DEPTH+4{1'b0}};
r_gys_00_4P <= {Y_DEPTH+4{1'b0}};
r_gys_01_4P <= {Y_DEPTH+4{1'b0}};
r_gys_11_5P <= {Y_DEPTH+4{1'b0}};
r_gys_00_5P <= {Y_DEPTH+4{1'b0}};
r_gys_01_5P <= {Y_DEPTH+4{1'b0}};
r_gys_00_6P <= {Y_DEPTH+4{1'b0}};
r_gys_01_6P <= {Y_DEPTH+4{1'b0}};
r_gys_00_7P <= {Y_DEPTH+4{1'b0}};
////////////////////////////////
r_gxs_00_8P <= {Y_DEPTH+4{1'b0}};
r_gys_00_8P <= {Y_DEPTH+4{1'b0}};
r_g_9P <= {Y_DEPTH+4{1'b0}};
r_g_10P <= {Y_DEPTH{1'b0}};
end
else
begin
r_p_11_00_1P <= i_pixel_11_01;
r_p_00_00_1P <= i_pixel_00_01;
r_p_01_00_1P <= i_pixel_01_01;
r_p_11_11_2P <= r_p_11_00_1P;
r_p_00_11_2P <= r_p_00_00_1P;
r_p_01_11_2P <= r_p_01_00_1P;
////////////////////////////////
r_gx_11_01_2P <= w_xp1_11_01_1P + w_xp2_11_01_1P;
r_gx_00_01_2P <= w_xp2_00_01_1P + w_xp8_00_01_1P;
r_gx_01_01_2P <= w_xp1_01_01_1P + w_xp2_01_01_1P;
////////////////////////////////
r_gxs_11_4P <= w_xn1_11_11_3P + w_xn2_11_11_3P;
r_gxs_00_4P <= w_xn2_00_11_3P + w_xn8_00_11_3P;
r_gxs_01_4P <= w_xn1_01_11_3P + w_xn2_01_11_3P;
r_gxs_11_5P <= r_gxs_11_4P + r_gx_11_01_2P;
r_gxs_00_5P <= r_gxs_00_4P + r_gx_00_01_2P;
r_gxs_01_5P <= r_gxs_01_4P + r_gx_01_01_2P;
r_gxs_00_6P <= r_gxs_00_5P + r_gxs_11_5P;
r_gxs_01_6P <= r_gxs_01_5P;
r_gxs_00_7P <= r_gxs_00_6P + r_gxs_01_6P;
////////////////////////////////
r_gy_11_01_2P <= w_yn1_11_01_1P + w_yn2_11_01_1P;
r_gy_00_01_2P <= w_gy_00_11_3P;
r_gy_01_01_2P <= w_yn1_01_01_1P + w_yn2_01_01_1P;
////////////////////////////////
r_gys_11_4P <= w_yn2_11_00_2P + w_yn8_11_00_2P + w_yn1_11_11_3P + w_yn2_11_11_3P;
r_gys_00_4P <= w_gy_00_00_2P + w_gy_00_01_1P;
r_gys_01_4P <= w_yp2_01_00_2P + w_yp8_01_00_2P + w_yn1_01_11_3P + w_yn2_01_11_3P;
r_gys_11_5P <= r_gys_11_4P + r_gy_11_01_2P;
r_gys_00_5P <= r_gys_00_4P + r_gy_00_01_2P;
r_gys_01_5P <= r_gys_01_4P + r_gy_01_01_2P;
r_gys_00_6P <= r_gys_00_5P + r_gys_11_5P;
r_gys_01_6P <= r_gys_01_5P;
r_gys_00_7P <= r_gys_00_6P + r_gys_01_6P;
////////////////////////////////
if (r_gxs_00_7P[Y_DEPTH+5-1])
r_gxs_00_8P <= ~r_gxs_00_7P + 1'b1;
else
r_gxs_00_8P <= r_gxs_00_7P;
if (r_gys_00_7P[Y_DEPTH+5-1])
r_gys_00_8P <= ~r_gys_00_7P + 1'b1;
else
r_gys_00_8P <= r_gys_00_7P;
r_g_9P <= r_gxs_00_8P + r_gys_00_8P;
if (r_g_9P[Y_DEPTH+5-1] || r_g_9P[Y_DEPTH+5-2])
r_g_10P <= {Y_DEPTH{1'b0}};
else
// r_g_10P <= {Y_DEPTH{1'b1}} - r_g_9P[Y_DEPTH-1:0];
r_g_10P <= r_g_9P[Y_DEPTH-1:0];
end
end
assign o_pixel = r_g_10P;
endmodule |
module sobel_scharr_tb();
localparam Y_DEPTH = 8;
reg r_arst;
reg r_pclk;
reg [Y_DEPTH-1:0]r_pixel_11_11;
reg [Y_DEPTH-1:0]r_pixel_00_11;
reg [Y_DEPTH-1:0]r_pixel_01_11;
reg [Y_DEPTH-1:0]r_pixel_11_11_1P;
reg [Y_DEPTH-1:0]r_pixel_00_11_1P;
reg [Y_DEPTH-1:0]r_pixel_01_11_1P;
wire [Y_DEPTH-1:0]w_pixel;
sobel_scharr
#(
.Y_DEPTH(Y_DEPTH)
)
inst_sobel_scharr
(
.i_arst(r_arst),
.i_pclk(r_pclk),
.i_pixel_11_11(r_pixel_11_11_1P),
.i_pixel_00_11(r_pixel_00_11_1P),
.i_pixel_01_11(r_pixel_01_11_1P),
.o_pixel(w_pixel)
);
initial
begin
r_pclk <= 1'b1;
forever
#2.5 r_pclk <= ~r_pclk;
end
initial
begin
r_arst <= 1'b1;
r_pixel_11_11 <= {Y_DEPTH{1'b0}};
r_pixel_00_11 <= {Y_DEPTH{1'b0}};
r_pixel_01_11 <= {Y_DEPTH{1'b0}};
#10 r_arst <= 1'b0;
r_pixel_11_11 <= 8'd225;
r_pixel_00_11 <= 8'd0;
r_pixel_01_11 <= 8'd76;
#5 r_pixel_11_11 <= 8'd105;
r_pixel_00_11 <= 8'd255;
r_pixel_01_11 <= 8'd149;
#5 r_pixel_11_11 <= 8'd178;
r_pixel_00_11 <= 8'd128;
r_pixel_01_11 <= 8'd29;
#5 r_pixel_11_11 <= {Y_DEPTH{1'b0}};
r_pixel_00_11 <= {Y_DEPTH{1'b0}};
r_pixel_11_11 <= {Y_DEPTH{1'b0}};
end
always@(posedge r_arst or posedge r_pclk)
begin
if (r_arst)
begin
r_pixel_11_11_1P <= {Y_DEPTH{1'b0}};
r_pixel_00_11_1P <= {Y_DEPTH{1'b0}};
r_pixel_01_11_1P <= {Y_DEPTH{1'b0}};
end
else
begin
r_pixel_11_11_1P <= r_pixel_11_11;
r_pixel_00_11_1P <= r_pixel_00_11;
r_pixel_01_11_1P <= r_pixel_01_11;
end
end
endmodule |
module sobel_feldman_tb();
localparam Y_DEPTH = 8;
reg r_arst;
reg r_pclk;
reg [Y_DEPTH-1:0]r_pixel_11_11;
reg [Y_DEPTH-1:0]r_pixel_00_11;
reg [Y_DEPTH-1:0]r_pixel_01_11;
reg [Y_DEPTH-1:0]r_pixel_11_11_1P;
reg [Y_DEPTH-1:0]r_pixel_00_11_1P;
reg [Y_DEPTH-1:0]r_pixel_01_11_1P;
wire [Y_DEPTH-1:0]w_pixel;
sobel_feldman
#(
.Y_DEPTH(Y_DEPTH)
)
inst_sobel_pixel
(
.i_arst(r_arst),
.i_pclk(r_pclk),
.i_pixel_11_11(r_pixel_11_11_1P),
.i_pixel_00_11(r_pixel_00_11_1P),
.i_pixel_01_11(r_pixel_01_11_1P),
.o_pixel(w_pixel)
);
initial
begin
r_pclk <= 1'b1;
forever
#2.5 r_pclk <= ~r_pclk;
end
initial
begin
r_arst <= 1'b1;
r_pixel_11_11 <= {Y_DEPTH{1'b0}};
r_pixel_00_11 <= {Y_DEPTH{1'b0}};
r_pixel_01_11 <= {Y_DEPTH{1'b0}};
#10 r_arst <= 1'b0;
r_pixel_11_11 <= 8'd225;
r_pixel_00_11 <= 8'd0;
r_pixel_01_11 <= 8'd76;
#5 r_pixel_11_11 <= 8'd105;
r_pixel_00_11 <= 8'd255;
r_pixel_01_11 <= 8'd149;
#5 r_pixel_11_11 <= 8'd178;
r_pixel_00_11 <= 8'd128;
r_pixel_01_11 <= 8'd29;
#5 r_pixel_11_11 <= {Y_DEPTH{1'b0}};
r_pixel_00_11 <= {Y_DEPTH{1'b0}};
r_pixel_11_11 <= {Y_DEPTH{1'b0}};
end
always@(posedge r_arst or posedge r_pclk)
begin
if (r_arst)
begin
r_pixel_11_11_1P <= {Y_DEPTH{1'b0}};
r_pixel_00_11_1P <= {Y_DEPTH{1'b0}};
r_pixel_01_11_1P <= {Y_DEPTH{1'b0}};
end
else
begin
r_pixel_11_11_1P <= r_pixel_11_11;
r_pixel_00_11_1P <= r_pixel_00_11;
r_pixel_01_11_1P <= r_pixel_01_11;
end
end
endmodule |
module top_opalSoc (
//user custom ports
//output [1:0] apb3LED,
//PLL
output my_pll_rstn,
input my_pll_locked,
//SOC
input io_systemClk,
input io_asyncReset,
output system_uart_0_io_txd,
input system_uart_0_io_rxd,
output system_i2c_0_io_sda_writeEnable,
output system_i2c_0_io_sda_write,
input system_i2c_0_io_sda_read,
output system_i2c_0_io_scl_writeEnable,
output system_i2c_0_io_scl_write,
input system_i2c_0_io_scl_read,
input [15:0] system_gpio_0_io_read,
output [15:0] system_gpio_0_io_write,
output [15:0] system_gpio_0_io_writeEnable,
output system_spi_0_io_sclk_write,
output system_spi_0_io_data_0_writeEnable,
input system_spi_0_io_data_0_read,
output system_spi_0_io_data_0_write,
output system_spi_0_io_data_1_writeEnable,
input system_spi_0_io_data_1_read,
output system_spi_0_io_data_1_write,
output system_spi_0_io_ss,
output system_spi_1_io_sclk_write,
output system_spi_1_io_data_0_writeEnable,
input system_spi_1_io_data_0_read,
output system_spi_1_io_data_0_write,
output system_spi_1_io_data_1_writeEnable,
input system_spi_1_io_data_1_read,
output system_spi_1_io_data_1_write,
output system_spi_1_io_ss,
`ifndef SOFT_TAP
input jtag_inst1_TCK,
input jtag_inst1_TDI,
output jtag_inst1_TDO,
input jtag_inst1_SEL,
input jtag_inst1_CAPTURE,
input jtag_inst1_SHIFT,
input jtag_inst1_UPDATE,
input jtag_inst1_RESET
`else
input io_jtag_tms,
input io_jtag_tdi,
output io_jtag_tdo,
input io_jtag_tck
`endif
);
/////////////////////////////////////////////////////////////////////////////
//Reset and PLL
wire mcuReset;
wire io_systemReset;
//APB Slave 0
wire [11:0] io_apbSlave_0_PADDR;
wire io_apbSlave_0_PSEL;
wire io_apbSlave_0_PENABLE;
wire io_apbSlave_0_PREADY;
wire io_apbSlave_0_PWRITE;
wire [31:0] io_apbSlave_0_PWDATA;
wire [31:0] io_apbSlave_0_PRDATA;
wire io_apbSlave_0_PSLVERROR;
//User Interupt
wire apb3Interrupt;
/////////////////////////////////////////////////////////////////////////////
//Reset and PLL
assign mcuReset = ~( io_asyncReset & my_pll_locked );
assign my_pll_rstn = 1'b1;
//I2C
assign system_i2c_0_io_sda_writeEnable = !system_i2c_0_io_sda_write;
assign system_i2c_0_io_scl_writeEnable = !system_i2c_0_io_scl_write;
//User Interrupt
assign userInterrupt = apb3Interrupt;
/////////////////////////////////////////////////////////////////////////////
//Custom APB PLUGIN
apb3_slave #(
// user parameter starts here
//
.ADDR_WIDTH (12),
.DATA_WIDTH (32),
.NUM_REG (2)
) apb_slave_0 (
// user logic starts here
.apb3LED (),
.apb3Interrupt (apb3Interrupt),
.clk (io_systemClk),
.resetn (~io_systemReset),
.PADDR (io_apbSlave_0_PADDR),
.PSEL (io_apbSlave_0_PSEL),
.PENABLE (io_apbSlave_0_PENABLE),
.PREADY (io_apbSlave_0_PREADY),
.PWRITE (io_apbSlave_0_PWRITE),
.PWDATA (io_apbSlave_0_PWDATA),
.PRDATA (io_apbSlave_0_PRDATA),
.PSLVERROR (io_apbSlave_0_PSLVERROR)
);
`ifndef SOFT_TAP
OpalSoc_t8 OpalSoc_t8_inst
(
.io_systemClk (io_systemClk),
.io_asyncReset (mcuReset),
.io_systemReset (io_systemReset),
.system_uart_0_io_txd (system_uart_0_io_txd),
.system_uart_0_io_rxd (system_uart_0_io_rxd),
.system_i2c_0_io_sda_write (system_i2c_0_io_sda_write),
.system_i2c_0_io_sda_read (system_i2c_0_io_sda_read),
.system_i2c_0_io_scl_write (system_i2c_0_io_scl_write),
.system_i2c_0_io_scl_read (system_i2c_0_io_scl_read),
.system_gpio_0_io_read (system_gpio_0_io_read[15:0]),
.system_gpio_0_io_write (system_gpio_0_io_write[15:0]),
.system_gpio_0_io_writeEnable (system_gpio_0_io_writeEnable[15:0]),
.io_apbSlave_0_PADDR (io_apbSlave_0_PADDR),
.io_apbSlave_0_PSEL (io_apbSlave_0_PSEL),
.io_apbSlave_0_PENABLE (io_apbSlave_0_PENABLE),
.io_apbSlave_0_PREADY (io_apbSlave_0_PREADY),
.io_apbSlave_0_PWRITE (io_apbSlave_0_PWRITE),
.io_apbSlave_0_PWDATA (io_apbSlave_0_PWDATA),
.io_apbSlave_0_PRDATA (io_apbSlave_0_PRDATA),
.io_apbSlave_0_PSLVERROR (io_apbSlave_0_PSLVERROR),
.userInterruptA (userInterrupt),
.system_spi_0_io_sclk_write (system_spi_0_io_sclk_write),
.system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable),
.system_spi_0_io_data_0_read (system_spi_0_io_data_0_read),
.system_spi_0_io_data_0_write (system_spi_0_io_data_0_write),
.system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable),
.system_spi_0_io_data_1_read (system_spi_0_io_data_1_read),
.system_spi_0_io_data_1_write (system_spi_0_io_data_1_write),
.system_spi_0_io_data_2_writeEnable (),
.system_spi_0_io_data_2_read (),
.system_spi_0_io_data_2_write (),
.system_spi_0_io_data_3_writeEnable (),
.system_spi_0_io_data_3_read (),
.system_spi_0_io_data_3_write (),
.system_spi_0_io_ss (system_spi_0_io_ss),
.system_spi_1_io_sclk_write (system_spi_1_io_sclk_write),
.system_spi_1_io_data_0_writeEnable (system_spi_1_io_data_0_writeEnable),
.system_spi_1_io_data_0_read (system_spi_1_io_data_0_read),
.system_spi_1_io_data_0_write (system_spi_1_io_data_0_write),
.system_spi_1_io_data_1_writeEnable (system_spi_1_io_data_1_writeEnable),
.system_spi_1_io_data_1_read (system_spi_1_io_data_1_read),
.system_spi_1_io_data_1_write (system_spi_1_io_data_1_write),
.system_spi_1_io_data_2_writeEnable (),
.system_spi_1_io_data_2_read (),
.system_spi_1_io_data_2_write (),
.system_spi_1_io_data_3_writeEnable (),
.system_spi_1_io_data_3_read (),
.system_spi_1_io_data_3_write (),
.system_spi_1_io_ss (system_spi_1_io_ss),
.jtagCtrl_tck (jtag_inst1_TCK),
.jtagCtrl_tdi (jtag_inst1_TDI),
.jtagCtrl_tdo (jtag_inst1_TDO),
.jtagCtrl_enable (jtag_inst1_SEL),
.jtagCtrl_capture (jtag_inst1_CAPTURE),
.jtagCtrl_shift (jtag_inst1_SHIFT),
.jtagCtrl_update (jtag_inst1_UPDATE),
.jtagCtrl_reset (jtag_inst1_RESET)
);
`else
OpalSoc_t8_softTap OpalSoc_t8_softTap_inst
(
.io_systemClk (io_systemClk),
.io_asyncReset (mcuReset),
.io_systemReset (io_systemReset),
.system_uart_0_io_txd (system_uart_0_io_txd),
.system_uart_0_io_rxd (system_uart_0_io_rxd),
.system_i2c_0_io_sda_write (system_i2c_0_io_sda_write),
.system_i2c_0_io_sda_read (system_i2c_0_io_sda_read),
.system_i2c_0_io_scl_write (system_i2c_0_io_scl_write),
.system_i2c_0_io_scl_read (system_i2c_0_io_scl_read),
.system_gpio_0_io_read (system_gpio_0_io_read[7:0]),
.system_gpio_0_io_write (system_gpio_0_io_write[7:0]),
.system_gpio_0_io_writeEnable (system_gpio_0_io_writeEnable[7:0]),
.io_apbSlave_0_PADDR (io_apbSlave_0_PADDR),
.io_apbSlave_0_PSEL (io_apbSlave_0_PSEL),
.io_apbSlave_0_PENABLE (io_apbSlave_0_PENABLE),
.io_apbSlave_0_PREADY (io_apbSlave_0_PREADY),
.io_apbSlave_0_PWRITE (io_apbSlave_0_PWRITE),
.io_apbSlave_0_PWDATA (io_apbSlave_0_PWDATA),
.io_apbSlave_0_PRDATA (io_apbSlave_0_PRDATA),
.io_apbSlave_0_PSLVERROR (io_apbSlave_0_PSLVERROR),
.userInterruptA (userInterrupt),
.system_spi_0_io_sclk_write (system_spi_0_io_sclk_write),
.system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable),
.system_spi_0_io_data_0_read (system_spi_0_io_data_0_read),
.system_spi_0_io_data_0_write (system_spi_0_io_data_0_write),
.system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable),
.system_spi_0_io_data_1_read (system_spi_0_io_data_1_read),
.system_spi_0_io_data_1_write (system_spi_0_io_data_1_write),
.system_spi_0_io_data_2_writeEnable (),
.system_spi_0_io_data_2_read (),
.system_spi_0_io_data_2_write (),
.system_spi_0_io_data_3_writeEnable (),
.system_spi_0_io_data_3_read (),
.system_spi_0_io_data_3_write (),
.system_spi_0_io_ss (system_spi_0_io_ss),
.io_jtag_tms (io_jtag_tms),
.io_jtag_tdi (io_jtag_tdi),
.io_jtag_tdo (io_jtag_tdo),
.io_jtag_tck (io_jtag_tck)
);
`endif
endmodule |
module apb3_slave #(
// user parameter starts here
//
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 31,
parameter NUM_REG = 4
) (
// user logic starts here
output [1:0] apb3LED,
output apb3Interrupt,
//
input clk,
input resetn,
input [ADDR_WIDTH-1:0] PADDR,
input PSEL,
input PENABLE,
output PREADY,
input PWRITE,
input [DATA_WIDTH-1:0] PWDATA,
output [DATA_WIDTH-1:0] PRDATA,
output PSLVERROR
);
///////////////////////////////////////////////////////////////////////////////
localparam [1:0] IDLE = 2'b00,
SETUP = 2'b01,
ACCESS = 2'b10;
reg [1:0] busState,
busNext;
reg [DATA_WIDTH-1:0] slaveReg [0:NUM_REG-1];
reg [DATA_WIDTH-1:0] slaveRegOut;
reg slaveReady;
wire actWrite,
actRead;
integer byteIndex;
///////////////////////////////////////////////////////////////////////////////
always@(posedge clk or negedge resetn)
begin
if(!resetn)
busState <= IDLE;
else
busState <= busNext;
end
always@(*)
begin
busNext = busState;
case(busState)
IDLE:
begin
if(PSEL && !PENABLE)
busNext = SETUP;
else
busNext = IDLE;
end
SETUP:
begin
if(PENABLE)
busNext = ACCESS;
else
busNext = IDLE;
end
ACCESS:
begin
if(PENABLE)
busNext = ACCESS;
else
busNext = IDLE;
end
default:
begin
busNext = IDLE;
end
endcase
end
assign actWrite = PWRITE & (busNext == ACCESS);
assign actRead = !PWRITE & (busNext == SETUP);
assign PSLVERROR = 1'b0; //FIXME
assign PRDATA = slaveRegOut;
assign PREADY = slaveReady;
always@ (posedge clk)
begin
slaveReady <= (busState == IDLE);
end
always@ (posedge clk or negedge resetn)
begin
if(!resetn)
for(byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1)
slaveReg[byteIndex] <= {{DATA_WIDTH}{1'b0}};
else begin
for(byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1)
if(actWrite && PADDR[3:0] == (byteIndex*4))
slaveReg[byteIndex] <= PWDATA;
else
slaveReg[byteIndex] <= slaveReg[byteIndex];
end
end
always@ (posedge clk or negedge resetn)
begin
if(!resetn)
slaveRegOut <= {{DATA_WIDTH}{1'b0}};
else begin
if(actRead)
slaveRegOut <= slaveReg[PADDR[7:2]];
else
slaveRegOut <= slaveRegOut;
end
end
//custom logic starts here
assign apb3LED = slaveReg[0][1:0];
assign apb3Interrupt = slaveReg[0][2];
//
endmodule |
module aib_adaptrxdp_map (
input wire [39:0] din,
input wire [79:0] rx_fifo_data_out, // Data from rx fifo
input wire rx_aib_transfer_clk,
input wire rx_aib_transfer_rst_n,
input wire rx_clock_fifo_rd_clk,
input wire rx_reset_fifo_rd_rst_n,
output reg [79:0] r_fifo_dout,
output reg [39:0] reg_dout
);
always @(posedge rx_clock_fifo_rd_clk or negedge rx_reset_fifo_rd_rst_n) begin
if (!rx_reset_fifo_rd_rst_n)
begin
r_fifo_dout[79:0] <= {80{1'b0}};
end
else begin
r_fifo_dout[79:0] <= rx_fifo_data_out[79:0];
end
end
always @(posedge rx_aib_transfer_clk or negedge rx_aib_transfer_rst_n) begin
if (!rx_aib_transfer_rst_n)
begin
reg_dout[39:0] <= {40{1'b0}};
end
else begin
reg_dout[39:0] <= din[39:0];
end
end
endmodule |
module aib_adapt_rxchnl(
// Outputs
output wire [77:0] data_out,
output wire [79:0] rx_fifo_data_out_sel,
output wire [39:0] reg_dout, //reg mode output
output wire align_done,
output wire rxfifo_wrclk,
// Inputs
input wire atpg_mode,
input wire rxswap_en,
input wire adapt_rstn,
input wire [39:0] din, //from io buffer
input wire [39:0] dout, //loopback data from tx to io buffer
input wire ns_fwd_clk, //loopback clock from tx
input wire fs_fwd_clk,
input wire m_rd_clk,
input wire rx_fifo_latency_adj_en,
input wire r_rx_double_read,
input wire [1:0] r_rx_fifo_mode,
input wire r_rx_lpbk,
input wire [2:0] r_rx_phcomp_rd_delay,
input wire r_rx_wa_en,
input wire r_rx_wr_adj_en,
input wire r_rx_rd_adj_en
);
wire loopback1;
wire [39:0] din_sel;
wire [79:0] r_fifo_dout, rx_fifo_data_out;
wire rxwr_rstn, rxrd_rstn, wa_error;
assign loopback1 = r_rx_lpbk;
assign din_sel[39:0] = loopback1 ? dout[39:0] :din[39:0];
assign data_out[77:0] = (r_rx_fifo_mode==2'b11) ? {38'b0,reg_dout[39:0]} :
(r_rx_fifo_mode==2'b00) ? {39'b0, r_fifo_dout[39:0]} :
{r_fifo_dout[78:40], r_fifo_dout[38:0]};
assign rx_fifo_data_out_sel[79:0] =((r_rx_fifo_mode==2'b01) & rxswap_en) ? {rx_fifo_data_out[79], rx_fifo_data_out[38:0], rx_fifo_data_out[39], rx_fifo_data_out[78:40]} : rx_fifo_data_out[79:0];
aib_adaptrxdp_map aib_adaptrxdp_map (
.din(din_sel[39:0]),
.rx_fifo_data_out(rx_fifo_data_out_sel[79:0]), // Data from rx fifo
.rx_aib_transfer_clk(rxfifo_wrclk),
.rx_aib_transfer_rst_n(rxwr_rstn),
.rx_clock_fifo_rd_clk(m_rd_clk),
.rx_reset_fifo_rd_rst_n(rxrd_rstn),
.r_fifo_dout(r_fifo_dout[79:0]),
.reg_dout(reg_dout[39:0])
);
aib_adaptrxdp_rxdp rx_datapath (
// Outputs
.rx_fifo_data_out (rx_fifo_data_out[79:0]),
.align_done (align_done),
.wa_error (wa_error),
.wa_error_cnt (),
.rx_fifo_testbus1 (),
.rx_fifo_testbus2 (),
.word_align_testbus (),
// Inputs
.din (din_sel[39:0]),
.r_rx_double_read (r_rx_double_read),
.r_rx_fifo_empty (5'b0),
.r_rx_fifo_mode (r_rx_fifo_mode[1:0]),
.r_rx_fifo_full (5'b11111),
.r_rx_fifo_pempty (5'b0),
.r_rx_fifo_pfull (5'b11111),
.r_rx_phcomp_rd_delay (r_rx_phcomp_rd_delay[2:0]),
.r_rx_stop_read (1'b1),
.r_rx_stop_write (1'b1),
.r_rx_wa_en (r_rx_wa_en),
.r_rx_wr_adj_en (r_rx_wr_adj_en),
.r_rx_rd_adj_en (r_rx_rd_adj_en),
.rx_fifo_latency_adj_en (rx_fifo_latency_adj_en),
.rx_clock_fifo_rd_clk (m_rd_clk),
.rx_reset_fifo_rd_rst_n (rxrd_rstn),
.rx_clock_fifo_wr_clk (rxfifo_wrclk),
.q1_rx_clock_fifo_wr_clk (rxfifo_wrclk),
.rx_reset_fifo_wr_rst_n (rxwr_rstn));
c3lib_mux2_ctn rxfifo_wrclk_mux (
.ck_out (rxfifo_wrclk),
.ck0 (fs_fwd_clk),
.ck1 (ns_fwd_clk),
.s0 (loopback1)
);
aib_rstnsync rxwr_rstnsync
(
.clk(rxfifo_wrclk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(rxwr_rstn) // Synchronized reset output
);
aib_rstnsync rxrd_rstnsync
(
.clk(m_rd_clk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(rxrd_rstn) // Synchronized reset output
);
endmodule |
module aib_adapttxdp_fifo
#(
parameter DWIDTH = 'd40, // FIFO Input data width
parameter AWIDTH = 'd5 // FIFO Depth (address width)
)
(
input wire wr_rst_n, // Write Domain Active low Reset
input wire wr_clk, // Write Domain Clock
input wire q1_wr_clk, // Write Domain Clock
input wire [2*DWIDTH-1:0] data_in, // Write Data In
input wire [DWIDTH-1:0] direct_data,
input wire rd_rst_n, // Read Domain Active low Reset
input wire rd_clk, // Read Domain Clock
input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold
input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold
input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold
input wire [AWIDTH-1:0] r_full, // FIFO full threshold
input wire r_double_write, // FIFO double write mode
input wire [1:0] r_fifo_mode, // FIFO Mode: Phase-comp, Register Mode
input wire [2:0] r_phcomp_rd_delay, // Programmable read and write pointer gap in phase comp mode
input wire r_wr_adj_en,
input wire r_rd_adj_en,
input wire fifo_latency_adj,
output wire [DWIDTH-1:0] aib_hssi_tx_data_out, // Read Data Out
output wire [19:0] tx_fifo_testbus1,
output wire [19:0] tx_fifo_testbus2,
output wire fifo_ready,
output wire fifo_empty, // FIFO empty
output wire fifo_pempty, // FIFO partial empty
output wire fifo_pfull, // FIFO partial full
output wire fifo_full, // FIFO full
output wire phcomp_wren, // Wr Enable to CP Bonding
output wire phcomp_rden, // Rd Enable to CP Bonding
output wire double_write_int // To CP bonding
);
//********************************************************************
// Define Parameters
//********************************************************************
localparam FIFO_DATA_DEFAULT = 40'd0;
localparam ASYNC_FIFO_AWIDTH = 4;
//********************************************************************
// Define variables
//********************************************************************
wire register_mode;
wire phcomp_mode;
wire phcomp_rden_int;
reg phcomp_wren_d0;
wire phcomp_wren_sync2;
reg phcomp_wren_sync3;
reg phcomp_wren_sync4;
reg phcomp_wren_sync5;
reg phcomp_wren_sync6;
wire [DWIDTH-1:0] fifo_out,wr_data;
reg [DWIDTH-1:0] data_out_int;
//wire phcomp_mode1x;
wire wr_en_int;
wire rd_en_int;
wire wr_empty;
wire wr_pempty;
wire wr_full;
wire wr_pfull;
wire rd_empty;
wire rd_pempty;
wire rd_full;
wire rd_pfull;
wire wr_addr_msb;
wire rd_addr_msb;
wire phcomp_wren_sync;
reg fifo_latency_adj_wr_sync_d0;
wire fifo_latency_adj_wr_sync;
wire fifo_latency_adj_wr_pulse;
reg fifo_latency_adj_rd_sync_d0;
reg fifo_latency_adj_rd_sync_d1;
wire fifo_latency_adj_rd_sync;
wire fifo_latency_adj_rd_pulse;
wire wr_en_int2;
wire rd_en_int2;
reg phcomp_wren_d1;
reg phcomp_wren_d2;
// FIFO mode decode
assign register_mode = (r_fifo_mode == 2'b11);
assign phcomp_mode = (r_fifo_mode == 2'b01) | (r_fifo_mode == 2'b00); //2'b00:1xphcomp, 2'b01:2xphcomp
assign wr_data[DWIDTH-1:0] = (r_fifo_mode == 2'b00) ? direct_data[DWIDTH-1:0] : data_in[DWIDTH-1:0];
//********************************************************************
// Instantiate the Async FIFO
//********************************************************************
aib_adapttxdp_async_fifo
#(
.DWIDTH (DWIDTH), // FIFO Input data width
.AWIDTH (ASYNC_FIFO_AWIDTH)
)
adapt_txdp_async_fifo (
.wr_rst_n (wr_rst_n), // Write Domain Active low Reset
.wr_clk (wr_clk), // Write Domain Clock
.q1_wr_clk (q1_wr_clk), // Write Domain Clock
.wr_en (wr_en_int2), // Write Data Enable
.wr_data (wr_data[DWIDTH-1:0]), // Write Data In
.wr_data2 (data_in[2*DWIDTH-1:DWIDTH]), // Write Data In
.rd_rst_n (rd_rst_n), // Read Domain Active low Reset
.rd_clk (rd_clk), // Read Domain Clock
.rd_en (rd_en_int2), // Read Data Enable
.rd_data (fifo_out), // Read Data Out
.r_pempty (r_pempty[ASYNC_FIFO_AWIDTH-1:0]), // FIFO partially empty threshold
.r_pfull (r_pfull[ASYNC_FIFO_AWIDTH-1:0]), // FIFO partially full threshold
.r_empty (r_empty[ASYNC_FIFO_AWIDTH-1:0]), // FIFO empty threshold
.r_full (r_full[ASYNC_FIFO_AWIDTH-1:0]), // FIFO full threshold
.r_stop_write (1'b0), // FIFO write option
.r_stop_read (1'b0), // FIFO read option
.r_double_write (r_double_write), // FIFO read option
.r_fifo_power_mode (2'b11),
.wr_empty (wr_empty), // FIFO Empty
.ps_wr_addr_msb (),
.ps_rd_addr_msb (),
.wr_pempty (wr_pempty), // FIFO Partial Empty
.wr_full (wr_full), // FIFO Full
.wr_pfull (wr_pfull), // FIFO Parial Full
.rd_empty (rd_empty), // FIFO Empty
.rd_pempty (rd_pempty), // FIFO Partial Empty
.rd_full (rd_full), // FIFO Full
.rd_pfull (rd_pfull), // FIFO Partial Full
.wr_addr_msb (wr_addr_msb), // Write address MSB for latency measure
.rd_addr_msb (rd_addr_msb) // Read address MSB for latency measure
);
//********************************************************************
// Instantiate latency measuring logic
//********************************************************************
//********************************************************************
// Read Write logic
//********************************************************************
assign wr_en_int = phcomp_mode & phcomp_wren; // Phase Comp Indiviual mode
assign rd_en_int = phcomp_mode & phcomp_rden_int; // Phase Comp Indiviual mode
// Output Register and Bypass Logic
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
data_out_int <= FIFO_DATA_DEFAULT;
end
//else if (register_mode == 1'b1) begin
// data_out_int <= data_in[DWIDTH-1:0];
//end
else if (phcomp_mode && ~rd_en_int2) begin
data_out_int <= FIFO_DATA_DEFAULT;
end
else begin
data_out_int <= rd_en_int2 ? fifo_out: data_out_int;
end
end
assign aib_hssi_tx_data_out = data_out_int;
//********************************************************************
// FIFO bonding logic
//********************************************************************
// Phase Comp FIFO mode Write/Read enable logic generation
// Write Enable
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
phcomp_wren_d0 <= 1'b0;
phcomp_wren_d1 <= 1'b0;
phcomp_wren_d2 <= 1'b0;
end
else begin
phcomp_wren_d0 <= 1'b1; // Indv: 1, Bonding: goes high and stays high
phcomp_wren_d1 <= phcomp_wren_d0;
phcomp_wren_d2 <= phcomp_wren_d1;
end
end
assign phcomp_wren = phcomp_wren_d2;
// phcomp_wren Synchronizer
c3lib_bitsync
#(
.SRC_DATA_FREQ_MHZ (200),
.DST_CLK_FREQ_MHZ (1000),
.DWIDTH (1),
.RESET_VAL (0)
)
bitsync2_phcomp_wren
(
.clk (rd_clk),
.rst_n (rd_rst_n),
.data_in (phcomp_wren),
.data_out (phcomp_wren_sync2)
);
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
phcomp_wren_sync3 <= 1'b0;
phcomp_wren_sync4 <= 1'b0;
phcomp_wren_sync5 <= 1'b0;
phcomp_wren_sync6 <= 1'b0;
end
else begin
phcomp_wren_sync3 <= phcomp_wren_sync2;
phcomp_wren_sync4 <= phcomp_wren_sync3;
phcomp_wren_sync5 <= phcomp_wren_sync4;
phcomp_wren_sync6 <= phcomp_wren_sync5;
end
end
// Read Enable
assign phcomp_wren_sync = (r_phcomp_rd_delay == 3'b110) ? phcomp_wren_sync6 : (r_phcomp_rd_delay == 3'b101) ? phcomp_wren_sync5 : (r_phcomp_rd_delay == 3'b100) ? phcomp_wren_sync4 : (r_phcomp_rd_delay == 3'b011) ? phcomp_wren_sync3 : phcomp_wren_sync2;
assign phcomp_rden = phcomp_wren_sync;
assign phcomp_rden_int = phcomp_rden;
// Sync to write/read clock domain
assign double_write_int = r_double_write;
assign fifo_full = wr_full;
assign fifo_pfull = wr_pfull;
assign fifo_empty = rd_empty;
assign fifo_pempty = rd_pempty;
c3lib_bitsync
#(
.SRC_DATA_FREQ_MHZ (200),
.DST_CLK_FREQ_MHZ (1000),
.DWIDTH (1),
.RESET_VAL (0)
)
bitsync2_wr_adj
(
.clk (wr_clk),
.rst_n (wr_rst_n),
.data_in (fifo_latency_adj),
.data_out (fifo_latency_adj_wr_sync)
);
c3lib_bitsync
#(
.SRC_DATA_FREQ_MHZ (200),
.DST_CLK_FREQ_MHZ (1000),
.DWIDTH (1),
.RESET_VAL (0)
)
bitsync2_rd_adj
(
.clk (rd_clk),
.rst_n (rd_rst_n),
.data_in (fifo_latency_adj),
.data_out (fifo_latency_adj_rd_sync)
);
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
fifo_latency_adj_rd_sync_d0 <= 1'b0;
fifo_latency_adj_rd_sync_d1 <= 1'b0;
end
else begin
fifo_latency_adj_rd_sync_d0 <= fifo_latency_adj_rd_sync;
fifo_latency_adj_rd_sync_d1 <= fifo_latency_adj_rd_sync_d0;
end
end
assign fifo_latency_adj_rd_pulse = r_rd_adj_en && (r_double_write ? fifo_latency_adj_rd_sync && (~fifo_latency_adj_rd_sync_d0 || ~fifo_latency_adj_rd_sync_d1) : fifo_latency_adj_rd_sync && ~fifo_latency_adj_rd_sync_d0);
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
fifo_latency_adj_wr_sync_d0 <= 1'b0;
end
else begin
fifo_latency_adj_wr_sync_d0 <= fifo_latency_adj_wr_sync;
end
end
assign fifo_latency_adj_wr_pulse = r_wr_adj_en && (fifo_latency_adj_wr_sync && ~fifo_latency_adj_wr_sync_d0);
assign wr_en_int2 = wr_en_int && ~ fifo_latency_adj_wr_pulse;
assign rd_en_int2 = rd_en_int && ~ fifo_latency_adj_rd_pulse;
// Testbus
assign tx_fifo_testbus1 = {16'd0, wr_full, wr_pfull , wr_addr_msb, wr_en_int2};
assign tx_fifo_testbus2 = {16'd0, rd_empty, rd_pempty, rd_addr_msb, rd_en_int2};
assign fifo_ready = register_mode;
endmodule |
module aib_adapttxdp_reg (
input wire tx_clock_fifo_rd_clk,
input wire tx_reset_fifo_rd_rst_n,
input wire [1:0] r_tx_fifo_mode,
input wire [39:0] data_in,
output reg [39:0] reg_dout
);
always @(posedge tx_clock_fifo_rd_clk or negedge tx_reset_fifo_rd_rst_n) begin
if (!tx_reset_fifo_rd_rst_n)
reg_dout <= {40{1'b0}};
else if (r_tx_fifo_mode[1:0] == 2'b11) begin
reg_dout[39:0] <= data_in[39:0];
end
end
endmodule |
module aib_adaptrxdp_rxdp (
input wire [40-1:0] din,
input wire rx_fifo_latency_adj_en,
input wire r_rx_double_read,
input wire [5-1:0] r_rx_fifo_empty,
input wire [1:0] r_rx_fifo_mode,
input wire [5-1:0] r_rx_fifo_full,
input wire [5-1:0] r_rx_fifo_pempty,
input wire [5-1:0] r_rx_fifo_pfull,
input wire [2:0] r_rx_phcomp_rd_delay,
input wire r_rx_stop_read,
input wire r_rx_stop_write,
input wire r_rx_wa_en,
input wire r_rx_wr_adj_en,
input wire r_rx_rd_adj_en,
input wire rx_clock_fifo_rd_clk,
input wire rx_reset_fifo_rd_rst_n,
input wire rx_clock_fifo_wr_clk,
input wire q1_rx_clock_fifo_wr_clk,
input wire rx_reset_fifo_wr_rst_n,
output wire wa_error,
output wire [3:0] wa_error_cnt,
output wire [79:0] rx_fifo_data_out,
output wire [19:0] rx_fifo_testbus1, // RX FIFO
output wire [19:0] rx_fifo_testbus2, // RX FIFO
output wire [19:0] word_align_testbus,
output wire align_done
);
localparam DWIDTH = 40;
localparam CNTWIDTH = 8;
localparam AWIDTH = 5;
wire wa_lock;
wire phcomp_rden;
wire phcomp_wren;
wire rd_clk;
wire rd_rst_n;
wire wr_clk;
wire q1_wr_clk;
wire q2_wr_clk;
wire q3_wr_clk;
wire q4_wr_clk;
wire wr_rst_n;
wire rx_rdfifo_clk;
wire rx_wrfifo_clk;
wire fifo_srst_n_rd_clk;
wire fifo_srst_n_wr_clk;
wire latency_pulse;
wire word_align_cmd;
wire fifo_pempty;
wire fifo_pfull;
wire rd_en_reg;
wire fifo_empty_int;
wire fifo_full_int;
wire r_double_read = r_rx_double_read;
wire [5-1:0] r_empty = r_rx_fifo_empty;
wire [1:0] r_fifo_mode = r_rx_fifo_mode;
wire [5-1:0] r_full = r_rx_fifo_full;
wire [5-1:0] r_pempty = r_rx_fifo_pempty;
wire [5-1:0] r_pfull = r_rx_fifo_pfull;
wire [2:0] r_phcomp_rd_delay = r_rx_phcomp_rd_delay;
wire r_stop_read = r_rx_stop_read;
wire r_stop_write = r_rx_stop_write;
wire r_wa_en = r_rx_wa_en;
wire r_wr_adj_en = r_rx_wr_adj_en;
wire r_rd_adj_en = r_rx_rd_adj_en;
assign rd_clk = rx_clock_fifo_rd_clk;
assign rx_rdfifo_clk = rx_clock_fifo_rd_clk;
assign wr_clk = rx_clock_fifo_wr_clk;
assign q1_wr_clk = q1_rx_clock_fifo_wr_clk;
assign rx_wrfifo_clk = rx_clock_fifo_wr_clk;
assign rd_rst_n = rx_reset_fifo_rd_rst_n;
assign wr_rst_n = rx_reset_fifo_wr_rst_n;
assign word_align_cmd = rd_en_reg;
assign align_done = rd_en_reg;
aib_adaptrxdp_fifo rxdp_fifo(
// Outputs
.rx_fifo_data_out (rx_fifo_data_out[2*DWIDTH-1:0]),
.rd_en_reg (rd_en_reg),
.fifo_empty (fifo_empty_int),
.fifo_pempty (fifo_pempty),
.fifo_pfull (fifo_pfull),
.fifo_full (fifo_full_int),
.wa_error (wa_error),
.wa_error_cnt (wa_error_cnt[3:0]),
.rx_fifo_testbus1 (rx_fifo_testbus1),
.rx_fifo_testbus2 (rx_fifo_testbus2),
// Inputs
.wr_rst_n (wr_rst_n),
.wr_clk (wr_clk),
.q1_wr_clk (q1_wr_clk),
.aib_hssi_rx_data_in (din[DWIDTH-1:0]),
.rd_rst_n (rd_rst_n),
.rd_clk (rd_clk),
.r_pempty (r_pempty[AWIDTH-1:0]),
.r_pfull (r_pfull[AWIDTH-1:0]),
.r_empty (r_empty[AWIDTH-1:0]),
.r_full (r_full[AWIDTH-1:0]),
.r_stop_read (r_stop_read),
.r_stop_write (r_stop_write),
.r_double_read (r_double_read),
.r_fifo_mode (r_fifo_mode[1:0]),
.r_phcomp_rd_delay (r_phcomp_rd_delay[2:0]),
.r_wa_en (r_wa_en),
.r_wr_adj_en (r_wr_adj_en),
.r_rd_adj_en (r_rd_adj_en),
.fifo_latency_adj (rx_fifo_latency_adj_en),
.wa_lock (wa_lock));
aib_adaptrxdp_word_align rxdp_word_align(
// Outputs
.wa_lock (wa_lock),
.word_align_testbus (word_align_testbus),
// Inputs
.wr_clk (wr_clk),
.wr_rst_n (wr_rst_n),
.r_wa_en (r_wa_en),
.aib_hssi_rx_data_in(din[DWIDTH-1:0]));
endmodule |
module aib_adapttxdp_txdp (
//input wire tx_elane_clk,
//input wire tx_elane_rst_n,
input wire [77:0] data_in,
input wire r_tx_double_write,
input wire [5-1:0] r_tx_fifo_empty,
input wire [1:0] r_tx_fifo_mode,
input wire [5-1:0] r_tx_fifo_full,
input wire [5-1:0] r_tx_fifo_pempty,
input wire [5-1:0] r_tx_fifo_pfull,
input wire [2:0] r_tx_phcomp_rd_delay,
input wire r_tx_stop_read,
input wire r_tx_stop_write,
input wire r_tx_wm_en,
input wire [2:0] r_tx_stretch_num_stages,
input wire r_tx_wr_adj_en,
input wire r_tx_rd_adj_en,
input wire tx_fifo_latency_adj_en,
input wire tx_clock_fifo_wr_clk,
input wire q1_tx_clock_fifo_wr_clk,
input wire tx_reset_fifo_wr_rst_n,
input wire tx_clock_fifo_rd_clk,
input wire tx_reset_fifo_rd_rst_n,
input wire rx_aib_lpbk_en, //loopback path from rxfifo output enable
input wire [79:0] rx_fifo_lpbk_data, //loopback data from rxfifo output
output wire [40-1:0] fifo_dout,
output wire fifo_empty,
output wire fifo_full,
output wire tx_fifo_ready,
output wire [19:0] tx_fifo_testbus1,
output wire [19:0] tx_fifo_testbus2
);
localparam DWIDTH = 40;
localparam CNTWIDTH = 8;
localparam AWIDTH = 5;
wire double_write;
wire double_write_int;
wire phcomp_rden;
wire phcomp_wren;
wire rd_clk;
wire rd_rst_n;
wire wr_clk;
wire q1_wr_clk;
wire wr_rst_n;
wire fifo_srst_n_rd_clk;
wire fifo_srst_n_wr_clk;
wire [79:0] wm_data;
wire [79:0] fifo_data_in;
wire [77:0] word_marker_data;
wire fifo_pempty; // To be connected to TB
wire fifo_pfull; // To be connected to TB
wire fifo_empty_int;
wire fifo_full_int;
wire compin_sel_rden;
wire compin_sel_wren;
// Add _tx to DPRIO bit name
wire r_double_write = r_tx_double_write;
wire [5-1:0] r_empty = r_tx_fifo_empty;
wire [1:0] r_fifo_mode = r_tx_fifo_mode;
wire [5-1:0] r_full = r_tx_fifo_full;
wire [5-1:0] r_pempty = r_tx_fifo_pempty;
wire [5-1:0] r_pfull = r_tx_fifo_pfull;
wire [2:0] r_phcomp_rd_delay = r_tx_phcomp_rd_delay;
wire r_stop_read = r_tx_stop_read;
wire r_stop_write = r_tx_stop_write;
wire r_wm_en = r_tx_wm_en;
wire r_wr_adj_en = r_tx_wr_adj_en;
wire r_rd_adj_en = r_tx_rd_adj_en;
//wire latency_pulse_mux1;
//wire xcvrif_latency_sel;
assign double_write = double_write_int;
assign rd_clk = tx_clock_fifo_rd_clk;
assign wr_clk = tx_clock_fifo_wr_clk;
assign q1_wr_clk = q1_tx_clock_fifo_wr_clk;
assign rd_rst_n = tx_reset_fifo_rd_rst_n;
assign wr_rst_n = tx_reset_fifo_wr_rst_n;
// Output of work-mark --> input of FIFO
assign fifo_data_in = (rx_aib_lpbk_en ) ? rx_fifo_lpbk_data[79:0] :
r_wm_en ? {1'b1, data_in[77:39], 1'b0, data_in[38:0]} : {2'b0,data_in[77:0]};
//assign wm_data = (rx_aib_lpbk_en ) ? rx_fifo_lpbk_data[79:0] : {1'b0,data_in[77:39],1'b0,data_in[38:0]};
aib_adapttxdp_fifo txdp_fifo(
// Outputs
.aib_hssi_tx_data_out (fifo_dout[DWIDTH-1:0]),
.fifo_empty (fifo_empty_int),
.fifo_pempty (fifo_pempty),
.fifo_pfull (fifo_pfull),
.fifo_full (fifo_full_int),
.phcomp_wren (phcomp_wren),
.phcomp_rden (phcomp_rden),
.double_write_int (double_write_int),
.fifo_ready (tx_fifo_ready),
.tx_fifo_testbus1 (tx_fifo_testbus1),
.tx_fifo_testbus2 (tx_fifo_testbus2),
// Inputs
.wr_rst_n (wr_rst_n),
.wr_clk (wr_clk),
.q1_wr_clk (q1_wr_clk),
.direct_data (data_in[DWIDTH-1:0]),
.data_in (fifo_data_in[2*DWIDTH-1:0]),
.rd_rst_n (rd_rst_n),
.rd_clk (rd_clk),
.r_pempty (r_pempty[AWIDTH-1:0]),
.r_pfull (r_pfull[AWIDTH-1:0]),
.r_empty (r_empty[AWIDTH-1:0]),
.r_full (r_full[AWIDTH-1:0]),
.r_double_write (r_double_write),
.r_fifo_mode (r_fifo_mode[1:0]),
.r_phcomp_rd_delay (r_phcomp_rd_delay[2:0]),
.r_wr_adj_en (r_wr_adj_en),
.r_rd_adj_en (r_rd_adj_en),
.fifo_latency_adj (tx_fifo_latency_adj_en));
// Pulse-stretch signals before being capture by osc_clk
// Flag pulse-stretch
aib_adapt_cmn_pulse_stretch
#(
.RESET_VAL (0) // Reset Value
) cmn_pulse_stretch_fifo_full
(
.clk (wr_clk),
.rst_n (wr_rst_n),
.num_stages (r_tx_stretch_num_stages),
.data_in (fifo_full_int),
.data_out (fifo_full)
);
aib_adapt_cmn_pulse_stretch
#(
.RESET_VAL (1) // Reset Value
) cmn_pulse_stretch_fifo_empty
(
.clk (rd_clk),
.rst_n (rd_rst_n),
.num_stages (r_tx_stretch_num_stages),
.data_in (fifo_empty_int),
.data_out (fifo_empty)
);
endmodule |
module aib_adaptrxdp_fifo
#(
parameter DWIDTH = 'd40, // FIFO Input data width
parameter AWIDTH = 'd5 // FIFO Depth (address width)
)
(
input wire wr_rst_n, // Write Domain Active low Reset
input wire wr_clk, // Write Domain Clock
input wire q1_wr_clk, // Write Domain Clock
input wire [DWIDTH-1:0] aib_hssi_rx_data_in, // Write Data In
input wire rd_rst_n, // Read Domain Active low Reset
input wire rd_clk, // Read Domain Clock
input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold
input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold
input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold
input wire [AWIDTH-1:0] r_full, // FIFO full threshold
input wire r_stop_read, // Disable/enable reading when FIFO is empty
input wire r_stop_write, // Disable/enable writing when FIFO is full
input wire r_double_read, // FIFO double write mode
input wire [1:0] r_fifo_mode, // FIFO Mode: Phase-comp, BaseR RM, Interlaken, Register Mode
input wire [2:0] r_phcomp_rd_delay, // Programmable read and write pointer gap in phase comp mode
input wire r_wa_en, // Word-align enable
input wire r_wr_adj_en,
input wire r_rd_adj_en,
input wire fifo_latency_adj,
input wire wa_lock,
output wire [2*DWIDTH-1:0] rx_fifo_data_out, // Read Data Out
output reg rd_en_reg, // Read data valid
output wire [19:0] rx_fifo_testbus1,
output wire [19:0] rx_fifo_testbus2,
output wire fifo_empty, // FIFO empty
output wire fifo_pempty, // FIFO partial empty
output wire fifo_pfull, // FIFO partial full
output wire fifo_full, // FIFO full
output reg wa_error, // To SR, status reg
output reg [3:0] wa_error_cnt // Go to status reg
);
//********************************************************************
// Define Parameters
//********************************************************************
localparam FIFO_DATA_DEFAULT = {1'b1, 39'd0,1'b0, 39'd0};
localparam G3_DATA_OUT_HOLD = {1'b1, 39'd0,1'b0, 39'd0}; // To be updated
localparam ASYNC_FIFO_AWIDTH = 4;
//********************************************************************
// Define variables
//********************************************************************
wire phcomp_mode;
wire phcomp_rden_int;
reg phcomp_wren_d0;
wire phcomp_wren_sync2;
reg phcomp_wren_sync3;
reg phcomp_wren_sync4;
reg phcomp_wren_sync5;
reg phcomp_wren_sync6;
wire [DWIDTH-1:0] fifo_out;
wire [DWIDTH-1:0] fifo_out_next;
wire [DWIDTH-1:0] data_in;
reg [2*DWIDTH-1:0] data_out;
wire wa_error_int;
wire double_read_int;
wire wr_en_int;
wire rd_en_int;
wire wr_empty;
wire wr_pempty;
wire wr_full;
wire wr_pfull;
wire rd_empty;
wire rd_pempty;
wire rd_full;
wire rd_pfull;
wire wr_addr_msb;
wire rd_addr_msb;
wire phcomp_wren, phcomp_wren_sync;
reg fifo_latency_adj_wr_sync_d0;
reg fifo_latency_adj_wr_sync_d1;
wire fifo_latency_adj_wr_sync;
wire fifo_latency_adj_wr_pulse;
reg fifo_latency_adj_rd_sync_d0;
wire fifo_latency_adj_rd_sync;
wire fifo_latency_adj_rd_pulse;
wire wr_en_int2;
wire rd_en_int2;
reg rd_en_int2_d0;
wire ps_rd_addr_msb;
wire ps_wr_addr_msb;
reg phcomp_wren_d1;
reg phcomp_wren_d2;
wire phcomp_rden;
// FIFO mode decode
assign phcomp_mode = (r_fifo_mode == 2'b01) | (r_fifo_mode == 2'b00);
assign data_in = aib_hssi_rx_data_in;
//********************************************************************
// Instantiate the Async FIFO
//********************************************************************
aib_adaptrxdp_async_fifo
#(
.DWIDTH (DWIDTH), // FIFO Input data width
.AWIDTH (ASYNC_FIFO_AWIDTH) // Reduce depth from 32 to 16 to save power
)
rx_datapath_async_fifo
(
.wr_rst_n (wr_rst_n), // Write Domain Active low Reset
.wr_clk (wr_clk), // Write Domain Clock
.q1_wr_clk (q1_wr_clk), // Write Domain Clock
.wr_en (wr_en_int2), // Write Data Enable
.wr_data (data_in), // Write Data In
.rd_rst_n (rd_rst_n), // Read Domain Active low Reset
.rd_clk (rd_clk), // Read Domain Clock
.rd_en (rd_en_int2), // Read Data Enable
.rd_data (fifo_out), // Read Data Out
.rd_data_next (fifo_out_next),// Read Data Out
.r_pempty (r_pempty[ASYNC_FIFO_AWIDTH-1:0]), // FIFO partially empty threshold
.r_pfull (r_pfull[ASYNC_FIFO_AWIDTH-1:0]), // FIFO partially full threshold
.r_empty (r_empty[ASYNC_FIFO_AWIDTH-1:0]), // FIFO empty threshold
.r_full (r_full[ASYNC_FIFO_AWIDTH-1:0]), // FIFO full threshold
.r_stop_write (r_stop_write), // FIFO write option
.r_stop_read (r_stop_read), // FIFO read option
.r_double_read (double_read_int), // FIFO read option
.r_fifo_power_mode (2'b11),
.wr_empty (wr_empty), // FIFO Empty
.wr_pempty (wr_pempty), // FIFO Partial Empty
.wr_full (wr_full), // FIFO Full
.wr_pfull (wr_pfull), // FIFO Parial Full
.rd_empty (rd_empty), // FIFO Empty
.rd_pempty (rd_pempty), // FIFO Partial Empty
.rd_full (rd_full), // FIFO Full
.rd_pfull (rd_pfull), // FIFO Partial Full
.wr_addr_msb (wr_addr_msb), // Write address MSB for latency measure
.rd_addr_msb (rd_addr_msb), // Read address MSB for latency measure
.ps_wr_addr_msb (ps_wr_addr_msb), // Write address MSB for latency measure
.ps_rd_addr_msb (ps_rd_addr_msb) // Read address MSB for latency measure
);
//********************************************************************
// Read Write logic
//********************************************************************
assign wr_en_int = phcomp_mode & phcomp_wren;
assign rd_en_int = phcomp_mode & phcomp_rden_int;
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
data_out <= FIFO_DATA_DEFAULT;
end
else if (phcomp_mode && ~rd_en_int2) begin
data_out <= FIFO_DATA_DEFAULT;
end
else begin
data_out <= rd_en_int2 ? {fifo_out_next, fifo_out}: data_out;
end
end
// Pipeline comb output to send to test bus
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
rd_en_int2_d0 <= 1'b0;
end
else begin
rd_en_int2_d0 <= rd_en_int2;
end
end
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
rd_en_reg <= 1'b0;
end
else begin
rd_en_reg <= rd_en_int2;
end
end
//Word-align error detect
assign wa_error_int = (data_out[39] || ~data_out[79]) && r_wa_en && rd_en_reg && (r_fifo_mode == 2'b01);
// Sample and hold wa_error
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0)
wa_error <= 1'b0;
else
wa_error <= wa_error | wa_error_int;
end
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
wa_error_cnt <= 4'b0000;
end
else if (wa_error_cnt < 4'b1111 && wa_error_int) begin
wa_error_cnt <= wa_error_cnt + 1'b1;
end
end
// Phase Comp FIFO mode Write/Read enable logic generation
// Write Enable
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
phcomp_wren_d0 <= 1'b0;
phcomp_wren_d1 <= 1'b0;
phcomp_wren_d2 <= 1'b0;
end
else begin
phcomp_wren_d0 <= (~r_wa_en || wa_lock) || phcomp_wren_d0;
phcomp_wren_d1 <= phcomp_wren_d0;
phcomp_wren_d2 <= phcomp_wren_d1;
end
end
assign phcomp_wren = phcomp_wren_d1;
// phcomp_wren Synchronizer
c3lib_bitsync
#(
.SRC_DATA_FREQ_MHZ (200),
.DST_CLK_FREQ_MHZ (1000),
.DWIDTH (1),
.RESET_VAL (0)
)
bitsync2_phcomp_wren
(
.clk (rd_clk),
.rst_n (rd_rst_n),
.data_in (phcomp_wren),
.data_out (phcomp_wren_sync2)
);
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
phcomp_wren_sync3 <= 1'b0;
phcomp_wren_sync4 <= 1'b0;
phcomp_wren_sync5 <= 1'b0;
phcomp_wren_sync6 <= 1'b0;
end
else begin
phcomp_wren_sync3 <= phcomp_wren_sync2;
phcomp_wren_sync4 <= phcomp_wren_sync3;
phcomp_wren_sync5 <= phcomp_wren_sync4;
phcomp_wren_sync6 <= phcomp_wren_sync5;
end
end
// Read Enable
assign phcomp_wren_sync = (r_phcomp_rd_delay == 3'b110) ? phcomp_wren_sync6 :
(r_phcomp_rd_delay == 3'b101) ? phcomp_wren_sync5 :
(r_phcomp_rd_delay == 3'b100) ? phcomp_wren_sync4 :
(r_phcomp_rd_delay == 3'b011) ? phcomp_wren_sync3 : phcomp_wren_sync2;
assign phcomp_rden = phcomp_wren_sync;
// Phase comp mode, FIFO read enable signal asserts when rd_val is high
assign phcomp_rden_int = phcomp_rden;
assign fifo_empty = rd_empty;
assign fifo_pempty = rd_pempty;
assign fifo_full = wr_full;
assign fifo_pfull = wr_pfull;
assign double_read_int = r_double_read;
// Latency adjust
c3lib_bitsync
#(
.SRC_DATA_FREQ_MHZ (200),
.DST_CLK_FREQ_MHZ (1000),
.DWIDTH (1),
.RESET_VAL (0)
)
bitsync2_wr_adj
(
.clk (wr_clk),
.rst_n (wr_rst_n),
.data_in (fifo_latency_adj),
.data_out (fifo_latency_adj_wr_sync)
);
c3lib_bitsync
#(
.SRC_DATA_FREQ_MHZ (200),
.DST_CLK_FREQ_MHZ (1000),
.DWIDTH (1),
.RESET_VAL (0)
)
bitsync2_rd_adj
(
.clk (rd_clk),
.rst_n (rd_rst_n),
.data_in (fifo_latency_adj),
.data_out (fifo_latency_adj_rd_sync)
);
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
fifo_latency_adj_wr_sync_d0 <= 1'b0;
fifo_latency_adj_wr_sync_d1 <= 1'b0;
end
else begin
fifo_latency_adj_wr_sync_d0 <= fifo_latency_adj_wr_sync;
fifo_latency_adj_wr_sync_d1 <= fifo_latency_adj_wr_sync_d0;
end
end
assign fifo_latency_adj_wr_pulse = r_wr_adj_en && (r_double_read ? fifo_latency_adj_wr_sync && (~fifo_latency_adj_wr_sync_d0 || ~fifo_latency_adj_wr_sync_d1) : fifo_latency_adj_wr_sync && ~fifo_latency_adj_wr_sync_d0);
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
fifo_latency_adj_rd_sync_d0 <= 1'b0;
end
else begin
fifo_latency_adj_rd_sync_d0 <= fifo_latency_adj_rd_sync;
end
end
assign fifo_latency_adj_rd_pulse = r_rd_adj_en && (fifo_latency_adj_rd_sync && ~fifo_latency_adj_rd_sync_d0);
assign wr_en_int2 = wr_en_int && ~ fifo_latency_adj_wr_pulse;
assign rd_en_int2 = rd_en_int && ~ fifo_latency_adj_rd_pulse;
assign rx_fifo_data_out[79:0] = data_out[79:0];
// Testbus
assign rx_fifo_testbus1 = {13'd0, wa_error, wr_en_int, wr_en_int2, 1'b0, phcomp_wren, fifo_full, fifo_pfull};
assign rx_fifo_testbus2 = {7'd0, rd_en_int, rd_en_int2_d0, 1'b0, rd_en_reg, wa_error, wa_error_cnt[3:0], 1'b0, 1'b0, fifo_empty, fifo_pempty};
endmodule |
module aib_adapt_txchnl(
// Outputs
output wire [39:0] dout,
output wire ns_fwd_clk,
// Inputs
input atpg_mode,
input txswap_en,
input adapt_rstn,
input m_wr_clk,
input m_ns_fwd_clk,
input [77:0] data_in,
input [79:0] rx_fifo_data_out, //loopback data from rx fifo mode
input [39:0] rx_reg_dout, //loopback data from rx reg mode
input [39:0] din, //loopback data from rx aib io
input m_rd_clk, //loopback clock for rx fifo mode
input fs_fwd_clk, //loopback clock for rx reg mode loopback
input rxfifo_wrclk, //loopback2 clock
input r_tx_double_write,
input [1:0] r_tx_fifo_mode,
input [1:0] r_tx_adapter_lpbk_mode, //tx loopback mode:00 no lpbk. 01 lpbk 2, 10 lpbk 3 reg, 11 lpbk 3 fifo
input [2:0] r_tx_phcomp_rd_delay,
input r_tx_wm_en,
input r_tx_wr_adj_en,
input r_tx_rd_adj_en,
input r_tx_fifo_latency_adj_en
);
wire fifo_empty;
wire fifo_full;
wire [39:0] reg_din, reg_dout, fifo_dout;
wire loopback2, loopback3_reg, loopback3_fifo;
wire txrd_rstn, tx_fifo_ready, txfifo_wrclk, txwr_rstn;
wire loopbk2_3reg;
wire reg_clk, regmd_rstn;
wire [77:0] data_in_sel;
assign loopback2 = (r_tx_adapter_lpbk_mode[1:0] == 2'b01);
assign loopback3_reg = (r_tx_adapter_lpbk_mode[1:0] == 2'b10);
assign loopback3_fifo = (r_tx_adapter_lpbk_mode[1:0] == 2'b11);
assign loopbk2_3reg = loopback2 | loopback3_reg;
assign dout[39:0]= loopback2 ? din[39:0] :
(r_tx_fifo_mode == 2'b11) ? reg_dout[39:0] : fifo_dout[39:0];
assign reg_din[39:0]= loopback3_reg ? rx_reg_dout[39:0] : data_in[39:0];
assign data_in_sel[77:0] = ((r_tx_fifo_mode == 2'b01) & txswap_en) ? {data_in[38:0], data_in[77:39]} : data_in[77:0];
c3lib_mux2_ctn reg_clk_mux (
.ck_out (reg_clk),
.ck0 (m_ns_fwd_clk),
.ck1 (fs_fwd_clk),
.s0 (loopback3_reg)
);
aib_rstnsync regmd_rstnsync
(
.clk(reg_clk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(regmd_rstn) // Synchronized reset output
);
aib_adapttxdp_reg txdp_reg (
// Outputs
.reg_dout (reg_dout[39:0]),
// Inputs
.tx_clock_fifo_rd_clk (reg_clk),
.tx_reset_fifo_rd_rst_n (regmd_rstn),
.r_tx_fifo_mode (r_tx_fifo_mode),
.data_in (reg_din[39:0])
);
aib_adapttxdp_txdp tx_datapath (
// Outputs
.fifo_dout (fifo_dout[39:0]),
.fifo_empty (fifo_empty),
.fifo_full (fifo_full),
.tx_fifo_ready (tx_fifo_ready),
.tx_fifo_testbus1 (),
.tx_fifo_testbus2 (),
// Inputs
.data_in (data_in_sel[77:0]),
.r_tx_double_write (r_tx_double_write),
.r_tx_fifo_empty (5'b0),
.r_tx_fifo_mode (r_tx_fifo_mode[1:0]),
.r_tx_fifo_full (5'b11111),
.r_tx_fifo_pempty (5'b0),
.r_tx_fifo_pfull (5'b11111),
.r_tx_phcomp_rd_delay (r_tx_phcomp_rd_delay[2:0]),
.r_tx_stop_read (1'b1),
.r_tx_stop_write (1'b1),
.r_tx_wm_en (r_tx_wm_en),
.r_tx_stretch_num_stages (3'b001),
.r_tx_wr_adj_en (r_tx_wr_adj_en),
.r_tx_rd_adj_en (r_tx_rd_adj_en),
.tx_fifo_latency_adj_en (r_tx_fifo_latency_adj_en),
.rx_aib_lpbk_en (loopback3_fifo),
.rx_fifo_lpbk_data (rx_fifo_data_out),
.tx_clock_fifo_wr_clk (txfifo_wrclk),
.q1_tx_clock_fifo_wr_clk (txfifo_wrclk),
.tx_reset_fifo_wr_rst_n (txwr_rstn),
.tx_clock_fifo_rd_clk (m_ns_fwd_clk),
.tx_reset_fifo_rd_rst_n (txrd_rstn)
);
c3lib_mux2_ctn txfifo_wrclk_mux (
.ck_out (txfifo_wrclk),
.ck0 (m_wr_clk),
.ck1 (m_rd_clk),
.s0 (loopback3_fifo)
);
c3lib_mux2_ctn ns_fwd_clk_mux (
.ck_out (ns_fwd_clk),
.ck0 (m_ns_fwd_clk),
.ck1 (rxfifo_wrclk),
.s0 (loopbk2_3reg)
);
aib_rstnsync txwr_rstnsync
(
.clk(txfifo_wrclk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(txwr_rstn) // Synchronized reset output
);
aib_rstnsync txrd_rstnsync
(
.clk(m_ns_fwd_clk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(txrd_rstn) // Synchronized reset output
);
endmodule |
module aib_adapttxdp_async_fifo
#(
parameter DWIDTH = 'd40, // FIFO Input data width
parameter AWIDTH = 'd4 // FIFO Depth (address width)
)
(
input wire wr_rst_n, // Write Domain Active low Reset
input wire wr_clk, // Write Domain Clock
input wire q1_wr_clk, // Write Domain Clock
input wire wr_en, // Write Data Enable
input wire [DWIDTH-1:0] wr_data, // Write Data In
input wire [DWIDTH-1:0] wr_data2, // Write Data In
input wire rd_rst_n, // Read Domain Active low Reset
input wire rd_clk, // Read Domain Clock
input wire rd_en, // Read Data Enable
input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold
input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold
input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold
input wire [AWIDTH-1:0] r_full, // FIFO full threshold
input wire r_double_write, // FIFO double write mode
input wire [1:0] r_fifo_power_mode, // FIFO double write mode, tie to "11"
input wire r_stop_read, // Disable/enable reading when FIFO is empty, tie to"0"
input wire r_stop_write, // Disable/enable writing when FIFO is full, tie to"0"
output wire [DWIDTH-1:0] rd_data, // Read Data Out
output wire wr_addr_msb, // Write address MSB
output wire rd_addr_msb, // Write address MSB
output wire ps_wr_addr_msb, // Power-saving Write address MSB
output wire ps_rd_addr_msb, // Power-saving Write address MSB
output reg wr_empty, // FIFO Empty
output reg wr_pempty, // FIFO Partial Empty
output reg wr_full, // FIFO Full
output reg wr_pfull, // FIFO Parial Full
output reg rd_empty, // FIFO Empty
output reg rd_pempty, // FIFO Partial Empty
output reg rd_full, // FIFO Full
output reg rd_pfull // FIFO Partial Full
);
//********************************************************************
// Define Parameters
//********************************************************************
localparam DEPTH = (1<<AWIDTH);
localparam PS_DEPTH = 8;
localparam PS_AWIDTH = 3;
localparam PS_DWIDTH = 20;
localparam NPS_DEPTH = 8;
localparam NPS_AWIDTH = 3;
localparam NPS_DWIDTH = 20;
//********************************************************************
// Define variables
//********************************************************************
wire [AWIDTH-1:0] rd_numdata; // Number of Data available in Read clock
wire [AWIDTH-1:0] wr_numdata; // Number of Data available in Write clock
wire wr_full_comb; // FIFO Full
wire wr_pfull_comb; // FIFO Parial Full
wire q1_wr_en;
wire [PS_DEPTH-1:0] q1_wr_ptr;
wire [PS_DEPTH-1:0] q1_rd_ptr;
wire [PS_DWIDTH-1:0] q1_wr_data;
wire [PS_DWIDTH-1:0] q1_rd_data;
wire [PS_DWIDTH-1:0] q1_wr_data2;
wire q2_wr_en;
wire [PS_DEPTH-1:0] q2_wr_ptr;
wire [PS_DEPTH-1:0] q2_rd_ptr;
wire [PS_DWIDTH-1:0] q2_wr_data;
wire [PS_DWIDTH-1:0] q2_rd_data;
wire [PS_DWIDTH-1:0] q2_wr_data2;
wire q3_wr_en;
wire [NPS_DEPTH-1:0] q3_wr_ptr;
wire [NPS_DEPTH-1:0] q3_rd_ptr;
wire [NPS_DWIDTH-1:0] q3_wr_data;
wire [NPS_DWIDTH-1:0] q3_rd_data;
wire [NPS_DWIDTH-1:0] q3_wr_data2;
wire q4_wr_en;
wire [NPS_DEPTH-1:0] q4_wr_ptr;
wire [NPS_DEPTH-1:0] q4_rd_ptr;
wire [NPS_DWIDTH-1:0] q4_wr_data;
wire [NPS_DWIDTH-1:0] q4_rd_data;
wire [NPS_DWIDTH-1:0] q4_wr_data2;
wire top_wr_en;
wire top_rd_en;
wire top_rd_empty;
wire top_wr_full;
wire [PS_DEPTH-1:0] top_wr_ptr_one_hot;
wire [PS_DEPTH-1:0] top_rd_ptr_one_hot;
wire top_wr_addr_msb;
wire top_rd_addr_msb;
wire [PS_AWIDTH-1:0] top_wr_numdata;
wire [PS_AWIDTH-1:0] top_rd_numdata;
wire [PS_AWIDTH-1:0] top_rd_ptr_bin;
wire [PS_AWIDTH-1:0] top_wr_ptr_bin;
wire full_wr_clk;
wire full_rd_clk;
wire full_wr_en;
wire full_rd_en;
wire full_rd_empty;
wire full_wr_full;
wire [DEPTH-1:0] full_wr_ptr_one_hot;
wire [DEPTH-1:0] full_rd_ptr_one_hot;
wire full_wr_addr_msb;
wire full_rd_addr_msb;
wire [AWIDTH-1:0] full_wr_numdata;
wire [AWIDTH-1:0] full_rd_numdata;
wire [AWIDTH-1:0] full_rd_ptr_bin;
wire [AWIDTH-1:0] full_wr_ptr_bin;
wire [DWIDTH-1:0] full_rd_data;
wire [DWIDTH-1:0] top_rd_data;
wire [DWIDTH-1:0] bot_rd_data;
reg [DWIDTH-1:0] mem_comb [DEPTH-1:0];
//********************************************************************
// FIFO RAM
//********************************************************************
aib_adapttxdp_fifo_ram
# (
.DWIDTH (PS_DWIDTH),
.DEPTH (PS_DEPTH))
q1_ram (
.r_double_write (r_double_write),
.r_stop_write (r_stop_write),
.wr_clk (q1_wr_clk),
.wr_rst_n (wr_rst_n),
.wr_en (q1_wr_en),
.wr_full (wr_full),
.wr_ptr (q1_wr_ptr),
.wr_data (q1_wr_data),
.wr_data2 (q1_wr_data2),
.rd_ptr (q1_rd_ptr),
.rd_data (q1_rd_data)
);
aib_adapttxdp_fifo_ram
# (
.DWIDTH (NPS_DWIDTH),
.DEPTH (PS_DEPTH))
q2_ram (
.r_double_write (r_double_write),
.r_stop_write (r_stop_write),
.wr_clk (q1_wr_clk),
.wr_rst_n (wr_rst_n),
.wr_en (q2_wr_en),
.wr_full (wr_full),
.wr_ptr (q2_wr_ptr),
.wr_data (q2_wr_data),
.wr_data2 (q2_wr_data2),
.rd_ptr (q2_rd_ptr),
.rd_data (q2_rd_data)
);
aib_adapttxdp_fifo_ram
# (
.DWIDTH (PS_DWIDTH),
.DEPTH (NPS_DEPTH))
q3_ram (
.r_double_write (r_double_write),
.r_stop_write (r_stop_write),
.wr_clk (q1_wr_clk),
.wr_rst_n (wr_rst_n),
.wr_en (q3_wr_en),
.wr_full (wr_full),
.wr_ptr (q3_wr_ptr),
.wr_data (q3_wr_data),
.wr_data2 (q3_wr_data2),
.rd_ptr (q3_rd_ptr),
.rd_data (q3_rd_data)
);
aib_adapttxdp_fifo_ram
# (
.DWIDTH (NPS_DWIDTH),
.DEPTH (NPS_DEPTH))
q4_ram (
.r_double_write (r_double_write),
.r_stop_write (r_stop_write),
.wr_clk (q1_wr_clk),
.wr_rst_n (wr_rst_n),
.wr_en (q4_wr_en),
.wr_full (wr_full),
.wr_ptr (q4_wr_ptr),
.wr_data (q4_wr_data),
.wr_data2 (q4_wr_data2),
.rd_ptr (q4_rd_ptr),
.rd_data (q4_rd_data)
);
//********************************************************************
// FIFO pointers
//********************************************************************
aib_adapttxdp_fifo_ptr
# (
.AWIDTH (AWIDTH),
.PS_AWIDTH (PS_AWIDTH),
.DEPTH (DEPTH),
.PS_DEPTH (PS_DEPTH))
full_pointers (
.wr_clk (wr_clk),
.wr_rst_n (wr_rst_n),
.rd_clk (rd_clk),
.rd_rst_n (rd_rst_n),
.wr_en (full_wr_en),
.rd_en (full_rd_en),
.rd_empty (full_rd_empty),
.wr_full (full_wr_full),
.r_stop_read (r_stop_read),
.r_stop_write (r_stop_write),
.r_double_write (r_double_write),
.r_fifo_power_mode (r_fifo_power_mode),
.wr_ptr_one_hot (full_wr_ptr_one_hot),
.rd_ptr_one_hot (full_rd_ptr_one_hot),
.rd_ptr_bin (full_rd_ptr_bin),
.wr_ptr_bin (full_wr_ptr_bin),
.wr_addr_msb (full_wr_addr_msb),
.rd_addr_msb (full_rd_addr_msb),
.ps_wr_addr_msb (ps_wr_addr_msb),
.ps_rd_addr_msb (ps_rd_addr_msb),
.wr_numdata (full_wr_numdata),
.rd_numdata (full_rd_numdata)
);
//********************************************************************
// WRITE CLOCK DOMAIN: Generate Fifo Number of Data Present
// using Write Address and Synchronized Read Address
//********************************************************************
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wr_full <= 1'b0;
wr_pfull <= 1'b0;
wr_empty <= 1'b1;
wr_pempty <= 1'b1;
end
else begin
// Generate FIFO Empty
wr_empty <= (wr_numdata <= r_empty) ? 1'b1 : 1'b0;
// Generate FIFO Almost Empty
wr_pempty <= (wr_numdata <= r_pempty) ? 1'b1 : 1'b0;
// Generate FIFO Full
wr_full <= wr_full_comb;
// Generate FIFO Almost Full
wr_pfull <= wr_pfull_comb;
end
end
assign wr_full_comb = (wr_numdata >= r_full) ? 1'b1 : 1'b0;
assign wr_pfull_comb = (wr_numdata >= r_pfull) ? 1'b1 : 1'b0;
//********************************************************************
// READ CLOCK DOMAIN: Generate Fifo Number of Data Present
// using Read Address and Synchronized Write Address
//********************************************************************
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
rd_empty <= 1'b1;
rd_pempty <= 1'b1;
rd_full <= 1'b0;
rd_pfull <= 1'b0;
end
else begin
// Generate FIFO Empty
rd_empty <= (rd_numdata <= r_empty) ? 1'b1 : 1'b0;
// Generate FIFO Almost Empty
rd_pempty <= (rd_numdata <= r_pempty) ? 1'b1 : 1'b0;
// Generate FIFO Full
rd_full <= (rd_numdata >= r_full) ? 1'b1 : 1'b0;
// Generate FIFO Almost Full
rd_pfull <= (rd_numdata >= r_pfull) ? 1'b1 : 1'b0;
end
end
//********************************************************************
// FIFO Mapping
//********************************************************************
assign q1_wr_en = wr_en;
assign q1_wr_ptr = full_wr_ptr_one_hot[PS_DEPTH-1:0];
assign q1_rd_ptr = full_rd_ptr_one_hot[PS_DEPTH-1:0];
assign q1_wr_data = wr_data[PS_DWIDTH-1:0];
assign q1_wr_data2 = wr_data2[PS_DWIDTH-1:0];
assign q2_wr_en = q1_wr_en;
assign q2_wr_ptr = q1_wr_ptr;
assign q2_rd_ptr = q1_rd_ptr;
assign q2_wr_data = wr_data[DWIDTH-1:PS_DWIDTH];
assign q2_wr_data2 = wr_data2[DWIDTH-1:PS_DWIDTH];
assign q3_wr_en = wr_en;
assign q3_wr_ptr = full_wr_ptr_one_hot[DEPTH-1:PS_DEPTH];
assign q3_rd_ptr = full_rd_ptr_one_hot[DEPTH-1:PS_DEPTH];
assign q3_wr_data = wr_data[PS_DWIDTH-1:0];
assign q3_wr_data2 = wr_data2[PS_DWIDTH-1:0];
assign q4_wr_en = q3_wr_en;
assign q4_wr_ptr = q3_wr_ptr;
assign q4_rd_ptr = q3_rd_ptr;
assign q4_wr_data = wr_data[DWIDTH-1:PS_DWIDTH];
assign q4_wr_data2 = wr_data2[DWIDTH-1:PS_DWIDTH];
assign top_wr_en = wr_en;
assign top_rd_en = rd_en;
assign top_rd_empty = rd_empty;
assign top_wr_full = wr_full;
assign full_wr_en = wr_en;
assign full_rd_en = rd_en;
assign full_rd_empty = rd_empty;
assign full_wr_full = wr_full;
assign wr_numdata = ~r_fifo_power_mode[1] ? {{AWIDTH-PS_AWIDTH{1'b0}},full_wr_numdata[PS_AWIDTH-1:0]} : full_wr_numdata;
assign rd_numdata = ~r_fifo_power_mode[1] ? {{AWIDTH-PS_AWIDTH{1'b0}},full_rd_numdata[PS_AWIDTH-1:0]} : full_rd_numdata;
assign wr_addr_msb = full_wr_addr_msb;
assign rd_addr_msb = full_rd_addr_msb;
assign top_rd_data = {q2_rd_data, q1_rd_data};
assign bot_rd_data = {q4_rd_data, q3_rd_data};
// Read data: concatenate data from multiple FIFOs
integer i, j;
always @ * begin
for (i='d0; i<= DEPTH-1; i=i+1'b1) begin
if (i<=PS_DEPTH-1)
mem_comb[i] = {q2_rd_data, q1_rd_data};
else
mem_comb[i] = {q4_rd_data, q3_rd_data};
end
end
assign full_rd_data = mem_comb[full_rd_ptr_bin];
assign rd_data = ~r_fifo_power_mode[1] ? top_rd_data : full_rd_data;
endmodule |
module aib_rstnsync
(
input wire clk, // Destination clock of reset to be synced
input wire i_rst_n, // Asynchronous reset input
input wire scan_mode, // Scan bypass for reset
output wire sync_rst_n // Synchronized reset output
);
reg first_stg_rst_n;
wire prescan_sync_rst_n;
always @(posedge clk or negedge i_rst_n)
if (!i_rst_n)
first_stg_rst_n <= 1'b0;
else
first_stg_rst_n <= 1'b1;
c3lib_bitsync
#(
.SRC_DATA_FREQ_MHZ (200),
.DST_CLK_FREQ_MHZ (1000),
.DWIDTH (1),
.RESET_VAL (0)
)
i_sync_rst_n
(
.clk (clk ),
.rst_n (i_rst_n ),
.data_in (first_stg_rst_n ),
.data_out (prescan_sync_rst_n)
);
assign sync_rst_n = scan_mode ? i_rst_n : prescan_sync_rst_n;
endmodule |
module aib_adaptrxdp_word_align
#(
parameter DWIDTH = 'd40 // FIFO Input data width
)
(
input wire wr_clk, // clock
input wire wr_rst_n, // async reset
input wire r_wa_en, // Word-align enable
input wire [DWIDTH-1:0] aib_hssi_rx_data_in, // Write Data In
output wire wa_lock, // Go to FIFO, status reg
output wire [19:0] word_align_testbus
);
reg wm_bit;
reg wm_bit_d1;
reg wm_bit_d2;
reg wm_bit_d3;
reg wm_bit_d4;
reg wm_bit_d5;
reg wa_lock_lt;
wire wa_lock_int;
//********************************************************************
// Main logic
//********************************************************************
//Word-align
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wm_bit <= 1'b0;
wm_bit_d1 <= 1'b0;
wm_bit_d2 <= 1'b0;
wm_bit_d3 <= 1'b0;
wm_bit_d4 <= 1'b0;
wm_bit_d5 <= 1'b0;
end
else begin
wm_bit <= aib_hssi_rx_data_in[39];
wm_bit_d1 <= wm_bit;
wm_bit_d2 <= wm_bit_d1;
wm_bit_d3 <= wm_bit_d2;
wm_bit_d4 <= wm_bit_d3;
wm_bit_d5 <= wm_bit_d4;
end
end
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wa_lock_lt <= 1'b0;
end
else begin
wa_lock_lt <= wa_lock_int || wa_lock_lt;
end
end
assign wa_lock_int = wm_bit && ~wm_bit_d1 && wm_bit_d2 && ~wm_bit_d3 && wm_bit_d4 && ~wm_bit_d5 || ~r_wa_en;
assign wa_lock = wa_lock_int || wa_lock_lt;
assign word_align_testbus = {13'd0, wa_lock, wm_bit, wm_bit_d1, wm_bit_d2, wm_bit_d3, wm_bit_d4, wm_bit_d5};
endmodule |
module aib_iotop_wrp ( osc_clkout, osc_clk_adpt, jtag_clksel_out, jtag_intest_out,
jtag_mode_out, jtag_rstb_en_out, jtag_rstb_out,
jtag_tx_scanen_out, jtag_weakpdn_out, jtag_weakpu_out,
oaibdftdll2core, oaibdftdll2adjch, oatpg_bsr0_scan_out,
oatpg_bsr1_scan_out, oatpg_bsr2_scan_out, oatpg_bsr3_scan_out,
oatpg_scan_out0, oatpg_scan_out1, odirectout_data_out_chain1,
ohssi_adapter_rx_pld_rst_n, odirectout_data_out_chain2,
ohssi_pld_pma_coreclkin, ohssi_pld_pma_rxpma_rstb,
ohssi_sr_clk_in,
ohssi_ssr_data_in, ohssi_ssr_load_in, ohssi_tx_data_in,
ohssi_tx_dcd_cal_done, ohssi_tx_dll_lock,
ohssi_tx_transfer_clk, ohssirx_dcc_done, ojtag_clkdr_out_chain,
ojtag_last_bs_out_chain, ojtag_rx_scan_out_chain,
por_aib_vcchssi_out, por_aib_vccl_out, aib0, aib1, aib2, aib3,
aib4, aib5, aib6, aib7, aib8, aib9, aib10, aib11, aib12, aib13,
aib14, aib15, aib16, aib17, aib18, aib19, aib20, aib21, aib22,
aib23, aib24, aib25, aib26, aib27, aib28, aib29, aib30, aib31,
aib32, aib33, aib34, aib35, aib36, aib37, aib38, aib39, aib40,
aib41, aib42, aib43, aib44, aib45, aib46, aib47, aib48, aib49,
aib50, aib51, aib52, aib53, aib54, aib55, aib56, aib57, aib58,
aib59, aib60, aib61, aib62, aib63, aib64, aib65, aib66, aib67,
aib68, aib69, aib70, aib71, aib72, aib73, aib74, aib75, aib76,
aib77, aib78, aib79, aib80, aib81, aib82, aib83, aib84, aib85,
aib86, aib87, aib88, aib89, aib90, aib91, aib92, aib93, aib94,
aib95, iaibdftcore2dll, iaibdftdll2adjch, iatpg_bsr0_scan_in,
iatpg_bsr0_scan_shift_clk, iatpg_bsr1_scan_in,
iatpg_bsr1_scan_shift_clk, iatpg_bsr2_scan_in,
iatpg_bsr2_scan_shift_clk, iatpg_bsr3_scan_in,
iatpg_bsr3_scan_shift_clk, iatpg_bsr_scan_shift_n,
iatpg_pipeline_global_en, iatpg_scan_clk_in0, iatpg_scan_clk_in1,
iatpg_scan_in0, iatpg_scan_in1, iatpg_scan_mode_n,
iatpg_scan_rst_n, iatpg_scan_shift_n,
ihssi_dcc_req,
ihssi_pld_pma_clkdiv_rx_user, ihssi_pld_pma_clkdiv_tx_user,
ihssi_pma_aib_tx_clk,
ihssi_rx_data_out, ihssi_rx_transfer_clk, ihssi_sr_clk_out,
ihssi_ssr_data_out, ihssi_ssr_load_out, ihssi_tx_dcd_cal_req,
ihssi_tx_dll_lock_req, ijtag_clkdr_in_chain,
ijtag_last_bs_in_chain, ijtag_tx_scan_in_chain,
irstb,
jtag_clksel, jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en,
jtag_tx_scanen_in, jtag_weakpdn, jtag_weakpu, osc_clkin,
por_aib_vcchssi, por_aib_vccl, r_aib_csr_ctrl_0, r_aib_csr_ctrl_1,
r_aib_csr_ctrl_2, r_aib_csr_ctrl_3, r_aib_csr_ctrl_4,
r_aib_csr_ctrl_5, r_aib_csr_ctrl_6, r_aib_csr_ctrl_7,
r_aib_csr_ctrl_8, r_aib_csr_ctrl_9, r_aib_csr_ctrl_10,
r_aib_csr_ctrl_11, r_aib_csr_ctrl_12, r_aib_csr_ctrl_13,
r_aib_csr_ctrl_14, r_aib_csr_ctrl_15, r_aib_csr_ctrl_16,
r_aib_csr_ctrl_17, r_aib_csr_ctrl_18, r_aib_csr_ctrl_19,
r_aib_csr_ctrl_20, r_aib_csr_ctrl_21, r_aib_csr_ctrl_22,
r_aib_csr_ctrl_23, r_aib_csr_ctrl_24, r_aib_csr_ctrl_25,
r_aib_csr_ctrl_26, r_aib_csr_ctrl_27, r_aib_csr_ctrl_28,
r_aib_csr_ctrl_29, r_aib_csr_ctrl_30, r_aib_csr_ctrl_31,
r_aib_csr_ctrl_32, r_aib_csr_ctrl_33, r_aib_csr_ctrl_34,
r_aib_csr_ctrl_35, r_aib_csr_ctrl_36, r_aib_csr_ctrl_37,
r_aib_csr_ctrl_38, r_aib_csr_ctrl_39, r_aib_csr_ctrl_40,
r_aib_csr_ctrl_41, r_aib_csr_ctrl_42, r_aib_csr_ctrl_43,
r_aib_csr_ctrl_44, r_aib_csr_ctrl_45, r_aib_csr_ctrl_46,
r_aib_csr_ctrl_47, r_aib_csr_ctrl_48, r_aib_csr_ctrl_49,
r_aib_csr_ctrl_50, r_aib_csr_ctrl_51, r_aib_csr_ctrl_52,
r_aib_csr_ctrl_53, r_aib_dprio_ctrl_0, r_aib_dprio_ctrl_1,
r_aib_dprio_ctrl_2, r_aib_dprio_ctrl_3, r_aib_dprio_ctrl_4
);
output osc_clkout, osc_clk_adpt, jtag_clksel_out, jtag_intest_out, jtag_mode_out,
jtag_rstb_en_out, jtag_rstb_out, jtag_tx_scanen_out,
jtag_weakpdn_out, jtag_weakpu_out, oatpg_bsr0_scan_out,
oatpg_bsr1_scan_out, oatpg_bsr2_scan_out, oatpg_bsr3_scan_out,
oatpg_scan_out0, oatpg_scan_out1, odirectout_data_out_chain1,
ohssi_adapter_rx_pld_rst_n, odirectout_data_out_chain2,
ohssi_pld_pma_coreclkin, ohssi_pld_pma_rxpma_rstb,
ohssi_sr_clk_in,
ohssi_ssr_data_in, ohssi_ssr_load_in, ohssi_tx_dcd_cal_done,
ohssi_tx_dll_lock, ohssi_tx_transfer_clk,
ohssirx_dcc_done, ojtag_clkdr_out_chain, ojtag_last_bs_out_chain,
ojtag_rx_scan_out_chain,
por_aib_vcchssi_out, por_aib_vccl_out;
inout aib0, aib1, aib2, aib3, aib4, aib5, aib6, aib7, aib8, aib9,
aib10, aib11, aib12, aib13, aib14, aib15, aib16, aib17, aib18,
aib19, aib20, aib21, aib22, aib23, aib24, aib25, aib26, aib27,
aib28, aib29, aib30, aib31, aib32, aib33, aib34, aib35, aib36,
aib37, aib38, aib39, aib40, aib41, aib42, aib43, aib44, aib45,
aib46, aib47, aib48, aib49, aib50, aib51, aib52, aib53, aib54,
aib55, aib56, aib57, aib58, aib59, aib60, aib61, aib62, aib63,
aib64, aib65, aib66, aib67, aib68, aib69, aib70, aib71, aib72,
aib73, aib74, aib75, aib76, aib77, aib78, aib79, aib80, aib81,
aib82, aib83, aib84, aib85, aib86, aib87, aib88, aib89, aib90,
aib91, aib92, aib93, aib94, aib95;
input iatpg_bsr0_scan_in, iatpg_bsr0_scan_shift_clk,
iatpg_bsr1_scan_in, iatpg_bsr1_scan_shift_clk, iatpg_bsr2_scan_in,
iatpg_bsr2_scan_shift_clk, iatpg_bsr3_scan_in,
iatpg_bsr3_scan_shift_clk, iatpg_bsr_scan_shift_n,
iatpg_pipeline_global_en, iatpg_scan_clk_in0, iatpg_scan_clk_in1,
iatpg_scan_in0, iatpg_scan_in1, iatpg_scan_mode_n,
iatpg_scan_rst_n, iatpg_scan_shift_n,
ihssi_dcc_req,
ihssi_pld_pma_clkdiv_rx_user, ihssi_pld_pma_clkdiv_tx_user,
ihssi_pma_aib_tx_clk,
ihssi_rx_transfer_clk, ihssi_sr_clk_out, ihssi_ssr_data_out,
ihssi_ssr_load_out, ihssi_tx_dcd_cal_req, ihssi_tx_dll_lock_req,
ijtag_clkdr_in_chain, ijtag_last_bs_in_chain,
ijtag_tx_scan_in_chain,
irstb,
jtag_clksel, jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en,
jtag_tx_scanen_in, jtag_weakpdn, jtag_weakpu, osc_clkin,
por_aib_vcchssi, por_aib_vccl;
output [12:0] oaibdftdll2adjch;
output [12:0] oaibdftdll2core;
output [39:0] ohssi_tx_data_in;
input [7:0] r_aib_csr_ctrl_42;
input [12:0] iaibdftdll2adjch;
input [7:0] r_aib_csr_ctrl_40;
input [7:0] r_aib_csr_ctrl_36;
input [7:0] r_aib_csr_ctrl_43;
input [7:0] r_aib_csr_ctrl_52;
input [7:0] r_aib_csr_ctrl_49;
input [7:0] r_aib_csr_ctrl_45;
input [7:0] r_aib_csr_ctrl_48;
input [7:0] r_aib_csr_ctrl_44;
input [7:0] r_aib_csr_ctrl_47;
input [39:0] ihssi_rx_data_out;
input [7:0] r_aib_csr_ctrl_34;
input [7:0] r_aib_csr_ctrl_35;
input [7:0] r_aib_dprio_ctrl_4;
input [2:1] iaibdftcore2dll;
input [7:0] r_aib_dprio_ctrl_1;
input [7:0] r_aib_dprio_ctrl_0;
input [7:0] r_aib_csr_ctrl_20;
input [7:0] r_aib_csr_ctrl_19;
input [7:0] r_aib_csr_ctrl_50;
input [7:0] r_aib_csr_ctrl_53;
input [7:0] r_aib_csr_ctrl_13;
input [7:0] r_aib_csr_ctrl_17;
input [7:0] r_aib_csr_ctrl_23;
input [7:0] r_aib_csr_ctrl_12;
input [7:0] r_aib_csr_ctrl_26;
input [7:0] r_aib_dprio_ctrl_2;
input [7:0] r_aib_csr_ctrl_29;
input [7:0] r_aib_csr_ctrl_30;
input [7:0] r_aib_csr_ctrl_24;
input [7:0] r_aib_csr_ctrl_46;
input [7:0] r_aib_csr_ctrl_39;
input [7:0] r_aib_csr_ctrl_37;
input [7:0] r_aib_csr_ctrl_38;
input [7:0] r_aib_csr_ctrl_31;
input [7:0] r_aib_csr_ctrl_18;
input [7:0] r_aib_dprio_ctrl_3;
input [7:0] r_aib_csr_ctrl_27;
input [7:0] r_aib_csr_ctrl_41;
input [7:0] r_aib_csr_ctrl_22;
input [7:0] r_aib_csr_ctrl_51;
input [7:0] r_aib_csr_ctrl_33;
input [7:0] r_aib_csr_ctrl_32;
input [7:0] r_aib_csr_ctrl_28;
input [7:0] r_aib_csr_ctrl_21;
input [7:0] r_aib_csr_ctrl_16;
input [7:0] r_aib_csr_ctrl_15;
input [7:0] r_aib_csr_ctrl_14;
input [7:0] r_aib_csr_ctrl_11;
input [7:0] r_aib_csr_ctrl_10;
input [7:0] r_aib_csr_ctrl_9;
input [7:0] r_aib_csr_ctrl_8;
input [7:0] r_aib_csr_ctrl_7;
input [7:0] r_aib_csr_ctrl_6;
input [7:0] r_aib_csr_ctrl_5;
input [7:0] r_aib_csr_ctrl_4;
input [7:0] r_aib_csr_ctrl_3;
input [7:0] r_aib_csr_ctrl_2;
input [7:0] r_aib_csr_ctrl_1;
input [7:0] r_aib_csr_ctrl_0;
input [7:0] r_aib_csr_ctrl_25;
wire NC_AIB76, NC_AIB77, NC_AIB53 ;
wire NC_AIB68, NC_AIB69, NC_AIB47;
assign aib47 = NC_AIB47;
assign aib48 = NC_AIB76;
assign aib55 = NC_AIB77;
assign aib62 = NC_AIB53;
assign aib68 = NC_AIB68;
assign aib69 = NC_AIB69;
aibcr3_top_wrp xaibcr3_top_wrp (
// Outputs
.jtag_clksel_out (jtag_clksel_out),
.jtag_intest_out (jtag_intest_out),
.jtag_mode_out (jtag_mode_out),
.jtag_rstb_en_out (jtag_rstb_en_out),
.jtag_rstb_out (jtag_rstb_out),
.jtag_tx_scanen_out (jtag_tx_scanen_out),
.jtag_weakpdn_out (jtag_weakpdn_out),
.jtag_weakpu_out (jtag_weakpu_out),
.oatpg_bsr0_scan_out(oatpg_bsr0_scan_out),
.oatpg_bsr1_scan_out(oatpg_bsr1_scan_out),
.oatpg_bsr2_scan_out(oatpg_bsr2_scan_out),
.oatpg_bsr3_scan_out(oatpg_bsr3_scan_out),
.oatpg_scan_out0 (oatpg_scan_out0),
.oatpg_scan_out1 (oatpg_scan_out1),
.odirectout_data_out_chain1(odirectout_data_out_chain1),
.odirectout_data_out_chain2(odirectout_data_out_chain2),
.ohssi_adapter_rx_pld_rst_n(ohssi_adapter_rx_pld_rst_n), //
.ohssi_adapter_tx_pld_rst_n(),
.ohssi_fsr_data_in (),
.ohssi_fsr_load_in (),
.ohssi_pcs_rx_pld_rst_n(),
.ohssi_pcs_tx_pld_rst_n(),
.ohssi_pld_pma_coreclkin(ohssi_pld_pma_coreclkin),
.ohssi_pld_pma_coreclkin_n(),
.ohssi_pld_pma_rxpma_rstb(ohssi_pld_pma_rxpma_rstb),
.ohssi_pld_pma_txdetectrx(),
.ohssi_pld_pma_txpma_rstb(),
.ohssi_pld_sclk (), //
.ohssi_sr_clk_in (ohssi_sr_clk_in),
.ohssi_ssr_data_in (ohssi_ssr_data_in),
.ohssi_ssr_load_in (ohssi_ssr_load_in),
.ohssi_tx_dcd_cal_done(ohssi_tx_dcd_cal_done),
.ohssi_tx_dll_lock (ohssi_tx_dll_lock),
.ohssi_tx_sr_clk_in (osc_clk_adpt),
.ohssi_tx_transfer_clk(ohssi_tx_transfer_clk),
.ohssirx_dcc_done (ohssirx_dcc_done),
.ojtag_clkdr_out_chain(ojtag_clkdr_out_chain),
.ojtag_last_bs_out_chain(ojtag_last_bs_out_chain),
.ojtag_rx_scan_out_chain(ojtag_rx_scan_out_chain),
.ored_idataselb_out_chain1(), //
.ored_idataselb_out_chain2(),
.ored_shift_en_out_chain1(),
.ored_shift_en_out_chain2(),
.osc_clkout (osc_clkout),
.otxen_out_chain1 (),
.otxen_out_chain2 (), //
.por_aib_vcchssi_out(por_aib_vcchssi_out),
.por_aib_vccl_out (por_aib_vccl_out),
.oaibdftdll2adjch (oaibdftdll2adjch),
.oaibdftdll2core (oaibdftdll2core),
.oshared_direct_async_out(),
.ohssi_avmm1_data_in(),
.ohssi_avmm2_data_in(), //
.ohssi_tx_data_in (ohssi_tx_data_in),
// Inouts
.aib0 (aib20),
.aib1 (aib21),
.aib2 (aib22),
.aib3 (aib23),
.aib4 (aib24),
.aib5 (aib25),
.aib6 (aib26),
.aib7 (aib27),
.aib8 (aib28),
.aib9 (aib29),
.aib10 (aib30),
.aib11 (aib31),
.aib12 (aib32),
.aib13 (aib33),
.aib14 (aib34),
.aib15 (aib35),
.aib16 (aib36),
.aib17 (aib37),
.aib18 (aib38),
.aib19 (aib39),
.aib20 (aib0),
.aib21 (aib1),
.aib22 (aib2),
.aib23 (aib3),
.aib24 (aib4),
.aib25 (aib5),
.aib26 (aib6),
.aib27 (aib7),
.aib28 (aib8),
.aib29 (aib9),
.aib30 (aib10),
.aib31 (aib11),
.aib32 (aib12),
.aib33 (aib13),
.aib34 (aib14),
.aib35 (aib15),
.aib36 (aib16),
.aib37 (aib17),
.aib38 (aib18),
.aib39 (aib19),
.aib40 (aib42),
.aib41 (aib43),
.aib42 (aib40),
.aib43 (aib41),
.aib44 (aib49),
.aib45 (aib46),
.aib46 (aib45),
.aib47 (),
.aib48 (aib58),
.aib49 (aib44),
.aib50 (aib61),
.aib51 (aib80),
.aib52 (aib81),
.aib53 (),
.aib54 (aib64),
.aib55 (aib79),
.aib56 (aib65),
.aib57 (aib87),
.aib58 (aib76),
.aib59 (aib86),
.aib60 (aib78),
.aib61 (aib50),
.aib62 (aib63),
.aib63 (aib77),
.aib64 (aib60),
.aib65 (aib56),
.aib66 (aib67),
.aib67 (aib66),
.aib68 (),
.aib69 (),
.aib70 (aib88),
.aib71 (aib89),
.aib72 (aib75),
.aib73 (aib91),
.aib74 (aib90),
.aib75 (aib72),
.aib76 (),
.aib77 (),
.aib78 (aib51),
.aib79 (aib52),
.aib80 (aib53),
.aib81 (aib54),
.aib82 (aib84),
.aib83 (aib85),
.aib84 (aib82),
.aib85 (aib83),
.aib86 (aib59),
.aib87 (aib57),
.aib88 (aib70),
.aib89 (aib71),
.aib90 (aib74),
.aib91 (aib73),
.aib92 (aib94),
.aib93 (aib95),
.aib94 (aib92),
.aib95 (aib93),
// Inputs
.iatpg_bsr0_scan_in (iatpg_bsr0_scan_in),
.iatpg_bsr0_scan_shift_clk(iatpg_bsr0_scan_shift_clk),
.iatpg_bsr1_scan_in (iatpg_bsr1_scan_in),
.iatpg_bsr1_scan_shift_clk(iatpg_bsr1_scan_shift_clk),
.iatpg_bsr2_scan_in (iatpg_bsr2_scan_in),
.iatpg_bsr2_scan_shift_clk(iatpg_bsr2_scan_shift_clk),
.iatpg_bsr3_scan_in (iatpg_bsr3_scan_in),
.iatpg_bsr3_scan_shift_clk(iatpg_bsr3_scan_shift_clk),
.iatpg_bsr_scan_shift_n(iatpg_bsr_scan_shift_n),
.iatpg_pipeline_global_en(iatpg_pipeline_global_en),
.iatpg_scan_clk_in0 (iatpg_scan_clk_in0),
.iatpg_scan_clk_in1 (iatpg_scan_clk_in1),
.iatpg_scan_in0 (iatpg_scan_in0),
.iatpg_scan_in1 (iatpg_scan_in1),
.iatpg_scan_mode_n (iatpg_scan_mode_n),
.iatpg_scan_rst_n (iatpg_scan_rst_n),
.iatpg_scan_shift_n (iatpg_scan_shift_n),
.idirectout_data_in_chain1(1'b0),
.idirectout_data_in_chain2(1'b0),
.ihssi_avmm1_data_out(1'b0),
.ihssi_avmm2_data_out(1'b0),
.ihssi_dcc_req (ihssi_dcc_req),
.ihssi_fsr_data_out (1'b0),
.ihssi_fsr_load_out (1'b0),
.ihssi_pld_8g_rxelecidle(1'b0),
.ihssi_pld_pcs_rx_clk_out(1'b0),
.ihssi_pld_pcs_tx_clk_out(1'b0),
.ihssi_pld_pma_clkdiv_rx_user(ihssi_pld_pma_clkdiv_rx_user),
.ihssi_pld_pma_clkdiv_tx_user(ihssi_pld_pma_clkdiv_tx_user),
.ihssi_pld_pma_hclk (1'b1), // output to aib61. Has to be "1" for cr3, which is rx, Wei
.ihssi_pld_pma_internal_clk1(1'b0),
.ihssi_pld_pma_internal_clk2(1'b0),
.ihssi_pld_pma_pfdmode_lock(1'b0),
.ihssi_pld_pma_rxpll_lock(1'b0),
.ihssi_pld_rx_hssi_fifo_latency_pulse(1'b0),
.ihssi_pld_tx_hssi_fifo_latency_pulse(1'b0),
.ihssi_pma_aib_tx_clk(ihssi_pma_aib_tx_clk),
.ihssi_rx_transfer_clk(ihssi_rx_transfer_clk),
.ihssi_sr_clk_out (ihssi_sr_clk_out),
.ihssi_ssr_data_out (ihssi_ssr_data_out),
.ihssi_ssr_load_out (ihssi_ssr_load_out),
.ihssi_tx_dcd_cal_req(ihssi_tx_dcd_cal_req),
.ihssi_tx_dll_lock_req(ihssi_tx_dll_lock_req),
.ijtag_clkdr_in_chain(ijtag_clkdr_in_chain),
.ijtag_last_bs_in_chain(ijtag_last_bs_in_chain),
.ijtag_tx_scan_in_chain(ijtag_tx_scan_in_chain),
.ired_idataselb_in_chain1(1'b0),
.ired_idataselb_in_chain2(1'b0),
.ired_shift_en_in_chain1(1'b0),
.ired_shift_en_in_chain2(1'b0),
.irstb (irstb),
.itxen_in_chain1 (1'b0),
.itxen_in_chain2 (1'b0),
.jtag_clksel (jtag_clksel),
.jtag_intest (jtag_intest),
.jtag_mode_in (jtag_mode_in),
.jtag_rstb (jtag_rstb),
.jtag_rstb_en (jtag_rstb_en),
.jtag_tx_scanen_in (jtag_tx_scanen_in),
.jtag_weakpdn (jtag_weakpdn),
.jtag_weakpu (jtag_weakpu),
.osc_clkin (osc_clkin),
.por_aib_vcchssi (por_aib_vcchssi),
.por_aib_vccl (por_aib_vccl),
.r_aib_csr_ctrl_42 (r_aib_csr_ctrl_42[7:0]),
.iaibdftdll2adjch (iaibdftdll2adjch[12:0]),
.r_aib_csr_ctrl_40 (r_aib_csr_ctrl_40[7:0]),
.r_aib_csr_ctrl_36 (r_aib_csr_ctrl_36[7:0]),
.r_aib_csr_ctrl_43 (r_aib_csr_ctrl_43[7:0]),
.r_aib_csr_ctrl_52 (r_aib_csr_ctrl_52[7:0]),
.r_aib_csr_ctrl_49 (r_aib_csr_ctrl_49[7:0]),
.r_aib_csr_ctrl_45 (r_aib_csr_ctrl_45[7:0]),
.r_aib_csr_ctrl_48 (r_aib_csr_ctrl_48[7:0]),
.r_aib_csr_ctrl_44 (r_aib_csr_ctrl_44[7:0]),
.r_aib_csr_ctrl_47 (r_aib_csr_ctrl_47[7:0]),
.ihssi_rx_data_out (ihssi_rx_data_out),
.r_aib_csr_ctrl_34 (r_aib_csr_ctrl_34[7:0]),
.r_aib_csr_ctrl_35 (r_aib_csr_ctrl_35[7:0]),
.r_aib_dprio_ctrl_4 (r_aib_dprio_ctrl_4[7:0]),
.iaibdftcore2dll (iaibdftcore2dll),
.r_aib_dprio_ctrl_1 (r_aib_dprio_ctrl_1[7:0]),
.r_aib_dprio_ctrl_0 (r_aib_dprio_ctrl_0[7:0]),
.r_aib_csr_ctrl_20 (r_aib_csr_ctrl_20[7:0]),
.r_aib_csr_ctrl_19 (r_aib_csr_ctrl_19[7:0]),
.r_aib_csr_ctrl_50 (r_aib_csr_ctrl_50[7:0]),
.r_aib_csr_ctrl_53 (r_aib_csr_ctrl_53[7:0]),
.r_aib_csr_ctrl_13 (r_aib_csr_ctrl_13[7:0]),
.r_aib_csr_ctrl_17 (r_aib_csr_ctrl_17[7:0]),
.r_aib_csr_ctrl_23 (r_aib_csr_ctrl_23[7:0]),
.r_aib_csr_ctrl_12 (r_aib_csr_ctrl_12[7:0]),
.r_aib_csr_ctrl_26 (r_aib_csr_ctrl_26[7:0]),
.r_aib_dprio_ctrl_2 (r_aib_dprio_ctrl_2[7:0]),
.r_aib_csr_ctrl_29 (r_aib_csr_ctrl_29[7:0]),
.r_aib_csr_ctrl_30 (r_aib_csr_ctrl_30[7:0]),
.r_aib_csr_ctrl_24 (r_aib_csr_ctrl_24[7:0]),
.r_aib_csr_ctrl_46 (r_aib_csr_ctrl_46[7:0]),
.r_aib_csr_ctrl_39 (r_aib_csr_ctrl_39[7:0]),
.r_aib_csr_ctrl_37 (r_aib_csr_ctrl_37[7:0]),
.r_aib_csr_ctrl_38 (r_aib_csr_ctrl_38[7:0]),
.ishared_direct_async_in(5'b0),
.r_aib_csr_ctrl_31 (r_aib_csr_ctrl_31[7:0]),
.r_aib_csr_ctrl_18 (r_aib_csr_ctrl_18[7:0]),
.r_aib_dprio_ctrl_3 (r_aib_dprio_ctrl_3[7:0]),
.r_aib_csr_ctrl_27 (r_aib_csr_ctrl_27[7:0]),
.r_aib_csr_ctrl_41 (r_aib_csr_ctrl_41[7:0]),
.r_aib_csr_ctrl_22 (r_aib_csr_ctrl_22[7:0]),
.r_aib_csr_ctrl_51 (r_aib_csr_ctrl_51[7:0]),
.r_aib_csr_ctrl_33 (r_aib_csr_ctrl_33[7:0]),
.r_aib_csr_ctrl_32 (r_aib_csr_ctrl_32[7:0]),
.r_aib_csr_ctrl_28 (r_aib_csr_ctrl_28[7:0]),
.r_aib_csr_ctrl_21 (r_aib_csr_ctrl_21[7:0]),
.r_aib_csr_ctrl_16 (r_aib_csr_ctrl_16[7:0]),
.r_aib_csr_ctrl_15 (r_aib_csr_ctrl_15[7:0]),
.r_aib_csr_ctrl_14 (r_aib_csr_ctrl_14[7:0]),
.r_aib_csr_ctrl_11 (r_aib_csr_ctrl_11[7:0]),
.r_aib_csr_ctrl_10 (r_aib_csr_ctrl_10[7:0]),
.r_aib_csr_ctrl_9 (r_aib_csr_ctrl_9[7:0]),
.r_aib_csr_ctrl_8 (r_aib_csr_ctrl_8[7:0]),
.r_aib_csr_ctrl_7 (r_aib_csr_ctrl_7[7:0]),
.r_aib_csr_ctrl_6 (r_aib_csr_ctrl_6[7:0]),
.r_aib_csr_ctrl_5 (r_aib_csr_ctrl_5[7:0]),
.r_aib_csr_ctrl_4 (r_aib_csr_ctrl_4[7:0]),
.r_aib_csr_ctrl_3 (r_aib_csr_ctrl_3[7:0]),
.r_aib_csr_ctrl_2 (r_aib_csr_ctrl_2[7:0]),
.r_aib_csr_ctrl_1 (r_aib_csr_ctrl_1[7:0]),
.r_aib_csr_ctrl_0 (r_aib_csr_ctrl_0[7:0]),
.r_aib_csr_ctrl_25 (r_aib_csr_ctrl_25[7:0]));
endmodule |
module aib_adaptrxdp_fifo_ram
#(
parameter DWIDTH = 'd40, // FIFO Input data width
parameter DEPTH = 'd16 // FIFO Depth
)
(
input wire r_stop_write, // Disable/enable writing when FIFO is full
input wire wr_clk, // Write Domain Clock
input wire wr_rst_n, // Write Domain Reset
input wire wr_full,
input wire wr_en, // Write Data Enable
input wire [DEPTH-1:0] wr_ptr, // Write Pointer
input wire [DWIDTH-1:0] wr_data, // Write Data In
input wire [DEPTH-1:0] rd_ptr, // Read Pointer
output reg [DWIDTH-1:0] rd_data, // Read Data
output reg [DWIDTH-1:0] rd_data2 // Read Data
);
//********************************************************************
// Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
//********************************************************************
wire [DEPTH-1:0] rd_ptr2;
integer m;
integer i, j;
// reg [DWIDTH-1:0] fifo_mem [((1<<AWIDTH)-1):0];
reg [DWIDTH-1:0] fifo_mem [DEPTH-1:0];
always @(negedge wr_rst_n or posedge wr_clk) begin
if (~wr_rst_n) begin
for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
fifo_mem[m] <= 'd0;
end
else if (wr_en && (~wr_full||~r_stop_write)) begin
for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
if (wr_ptr[m]) begin
fifo_mem[m] <= wr_data;
end
end
end
end
assign rd_ptr2 = {rd_ptr[DEPTH-2:0], rd_ptr[DEPTH-1]};
always @ *
begin: data_out
rd_data = fifo_mem[0];
for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
if (rd_ptr[i]) begin
rd_data = fifo_mem[i];
end
end
end
always @ *
begin: data_out2
rd_data2 = fifo_mem[0];
for (j='d0; j<=(DEPTH-1'b1); j=j+1'b1) begin
if (rd_ptr2[j]) begin
rd_data2 = fifo_mem[j];
end
end
end
endmodule |
module aib_top_v2s
# (
parameter TOTAL_CHNL_NUM = 24
)
(
//================================================================================================
// Reset Inteface
input i_conf_done, // AIB adaptor hard reset
input dual_mode_select, //1 is master mode, 0 is slave mode
// reset for XCVRIF
output [TOTAL_CHNL_NUM-1:0] fs_mac_rdy, // chiplet xcvr receiving path reset, the reset is controlled by remote chiplet which is FPGA in this case
//===============================================================================================
// Configuration Interface which includes two paths
// Path directly from chip programming controller
input i_cfg_avmm_clk,
input i_cfg_avmm_rst_n,
input [16:0] i_cfg_avmm_addr, // address to be programmed
input [3:0] i_cfg_avmm_byte_en, // byte enable
input i_cfg_avmm_read, // Asserted to indicate the Cfg read access
input i_cfg_avmm_write, // Asserted to indicate the Cfg write access
input [31:0] i_cfg_avmm_wdata, // data to be programmed
output o_cfg_avmm_rdatavld,// Assert to indicate data available for Cfg read access
output [31:0] o_cfg_avmm_rdata, // data returned for Cfg read access
output o_cfg_avmm_waitreq, // asserted to indicate not ready for Cfg access
//===============================================================================================
// Data Path
// Rx Path clocks/data, from master (current chiplet) to slave (FPGA)
input [TOTAL_CHNL_NUM-1:0] m_ns_fwd_clk, // Rx path clk for data receiving, may generated from xcvr pll
input [TOTAL_CHNL_NUM-1:0] m_ns_fwd_div2_clk, // Divided by 2 clock on Rx pathinput
// input [TOTAL_CHNL_NUM*65-1:0] i_chnl_ssr, // Slow shift chain path, tie to 0s if not used
// input [TOTAL_CHNL_NUM*40-1:0] i_rx_pma_data, // Directed bump rx data sync path
input [TOTAL_CHNL_NUM-1:0] m_wr_clk, //Clock for phase compensation fifo
input [TOTAL_CHNL_NUM*78-1:0] data_in, //data in for phase compensation fifo
// Tx Path clocks/data, from slave (FPGA) to master (current chiplet)
input [TOTAL_CHNL_NUM-1:0] m_ns_rcv_clk, // this clock is sent over to the other chiplet to be used for the clock as the data transmission
// output [TOTAL_CHNL_NUM*61-1:0] o_chnl_ssr, // Slow shift chain path, left unconnected if not used
output [TOTAL_CHNL_NUM-1:0] m_fs_fwd_clk, // clock used for tx data transmission
output [TOTAL_CHNL_NUM-1:0] m_fs_fwd_div2_clk, // half rate of tx data transmission clock
output [TOTAL_CHNL_NUM-1:0] m_fs_rcv_clk,
output [TOTAL_CHNL_NUM-1:0] m_fs_rcv_div2_clk,
// output [TOTAL_CHNL_NUM*40-1:0] o_tx_pma_data, // Directed bump tx data sync path
input [TOTAL_CHNL_NUM-1:0] m_rd_clk, //Clock for phase compensation fifo
output [TOTAL_CHNL_NUM*78-1:0] data_out, // data out for phase compensation fifo
//=================================================================================================
// AIB open source IP enhancement. The following ports are added to
// be compliance with AIB specification 1.1
input [TOTAL_CHNL_NUM-1:0] ns_mac_rdy, //From Mac. To indicate MAC is ready to send and receive data. use aibio49
input [TOTAL_CHNL_NUM-1:0] ns_adapter_rstn, //From Mac. To reset near adapt reset sm and far side reset sm. aibio56
output [TOTAL_CHNL_NUM*81-1:0] ms_sideband, //Status of serial shifting bit from this master chiplet to slave chiplet
output [TOTAL_CHNL_NUM*73-1:0] sl_sideband, //Status of serial shifting bit from slave chiplet to master chiplet.
output [TOTAL_CHNL_NUM-1:0] m_rxfifo_align_done, //Newly added rx data fifo alignment done signal.
output [TOTAL_CHNL_NUM-1:0] ms_tx_transfer_en,
output [TOTAL_CHNL_NUM-1:0] ms_rx_transfer_en,
output [TOTAL_CHNL_NUM-1:0] sl_tx_transfer_en,
output [TOTAL_CHNL_NUM-1:0] sl_rx_transfer_en,
input [TOTAL_CHNL_NUM-1:0] sl_tx_dcc_dll_lock_req,
input [TOTAL_CHNL_NUM-1:0] sl_rx_dcc_dll_lock_req,
//=================================================================================================
// Inout signals for AIB ubump
inout [95:0] s0_ch0_aib,
inout [95:0] s0_ch1_aib,
inout [95:0] s0_ch2_aib,
inout [95:0] s0_ch3_aib,
inout [95:0] s0_ch4_aib,
inout [95:0] s0_ch5_aib,
inout [95:0] s1_ch0_aib,
inout [95:0] s1_ch1_aib,
inout [95:0] s1_ch2_aib,
inout [95:0] s1_ch3_aib,
inout [95:0] s1_ch4_aib,
inout [95:0] s1_ch5_aib,
inout [95:0] s2_ch0_aib,
inout [95:0] s2_ch1_aib,
inout [95:0] s2_ch2_aib,
inout [95:0] s2_ch3_aib,
inout [95:0] s2_ch4_aib,
inout [95:0] s2_ch5_aib,
inout [95:0] s3_ch0_aib,
inout [95:0] s3_ch1_aib,
inout [95:0] s3_ch2_aib,
inout [95:0] s3_ch3_aib,
inout [95:0] s3_ch4_aib,
inout [95:0] s3_ch5_aib,
// inout [95:0] io_aib_aux,
// inout io_aib_aux74, //Device select pin
// inout io_aib_aux75, //Device select passive resundancy
inout device_detect,
// inout io_aib_aux85, //Power on Reset pin
// inout io_aib_aux87, //Power on reset passive redundancy pin
inout por,
// inout io_aux_bg_ext_2k, //connect to external 2k resistor, C4 bump
//======================================================================================
// Interface with AIB control block
// reset for AIB AUX
input m_power_on_reset,
output m_device_detect,
input m_device_detect_ovrd,
// from control block register file
// input [31:0] i_aibaux_ctrl_bus0, //1st set of register bits from register file
// input [31:0] i_aibaux_ctrl_bus1, //2nd set of register bits from register file
// input [31:0] i_aibaux_ctrl_bus2, //3rd set of register bits from register file
// input [9:0] i_aibaux_osc_fuse_trim, //control by Fuse/OTP from User
//
input i_osc_clk, // test clock from c4 bump, may tie low for User if not used
// output o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator, User may use this clock to connect with i_test_clk_1g
//======================================================================================
// DFT signals
input scan_clk,
input scan_enable,
// input [TOTAL_CHNL_NUM-1:0][19:0] scan_in,
// splitting scan_in because of the lvs tool issue. 7/29/2020
input [19:0] scan_in_ch0,
input [19:0] scan_in_ch1,
input [19:0] scan_in_ch2,
input [19:0] scan_in_ch3,
input [19:0] scan_in_ch4,
input [19:0] scan_in_ch5,
input [19:0] scan_in_ch6,
input [19:0] scan_in_ch7,
input [19:0] scan_in_ch8,
input [19:0] scan_in_ch9,
input [19:0] scan_in_ch10,
input [19:0] scan_in_ch11,
input [19:0] scan_in_ch12,
input [19:0] scan_in_ch13,
input [19:0] scan_in_ch14,
input [19:0] scan_in_ch15,
input [19:0] scan_in_ch16,
input [19:0] scan_in_ch17,
input [19:0] scan_in_ch18,
input [19:0] scan_in_ch19,
input [19:0] scan_in_ch20,
input [19:0] scan_in_ch21,
input [19:0] scan_in_ch22,
input [19:0] scan_in_ch23,
// output [TOTAL_CHNL_NUM-1:0][19:0] scan_out,
output [19:0] scan_out_ch0,
output [19:0] scan_out_ch1,
output [19:0] scan_out_ch2,
output [19:0] scan_out_ch3,
output [19:0] scan_out_ch4,
output [19:0] scan_out_ch5,
output [19:0] scan_out_ch6,
output [19:0] scan_out_ch7,
output [19:0] scan_out_ch8,
output [19:0] scan_out_ch9,
output [19:0] scan_out_ch10,
output [19:0] scan_out_ch11,
output [19:0] scan_out_ch12,
output [19:0] scan_out_ch13,
output [19:0] scan_out_ch14,
output [19:0] scan_out_ch15,
output [19:0] scan_out_ch16,
output [19:0] scan_out_ch17,
output [19:0] scan_out_ch18,
output [19:0] scan_out_ch19,
output [19:0] scan_out_ch20,
output [19:0] scan_out_ch21,
output [19:0] scan_out_ch22,
output [19:0] scan_out_ch23,
input i_scan_clk,
// input i_test_clk_1g, //1GHz free running direct accessed ATPG at speed clock.
// input i_test_clk_125m,//Divided down from i_test_clk_1g.
// input i_test_clk_250m,//Divided down from i_test_clk_1g.
// input i_test_clk_500m,//Divided down from i_test_clk_1g.
// input i_test_clk_62m, //Divided down from i_test_clk_1g.
//The divided down clock is for different clock domain at
//speed test.
//Channel ATPG signals from/to CODEC
// input [TOTAL_CHNL_NUM-1:0] [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] i_test_c3adapt_scan_in, //scan in hook from Codec
// input [`AIBADAPTWRAPTCB_STATIC_COMMON_RNG] i_test_c3adapt_tcb_static_common, //TCM Controls for ATPG scan test.
// i_test_scan_reset, i_test_scan_enable, i_test_scan_mode
input i_test_scan_en, //Terminate i_test_c3adapt_tcb_static_common, only pull out Scan enable
input i_test_scan_mode,
// output [TOTAL_CHNL_NUM-1:0] [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] o_test_c3adapt_scan_out, //scan out hook to Codec
//Inputs from TCB (JTAG signals)
input i_jtag_clkdr, // (from dbg_test_bscan block)Enable AIB IO boundary scan clock (clock gate control)
input i_jtag_clksel, // (from dbg_test_bscan block)Select between i_jtag_clkdr_in and functional clk
input i_jtag_intest, // (from dbg_test_bscan block)Enable in test operation
input i_jtag_mode, // (from dbg_test_bscan block)Selects between AIB BSR register or functional path
input i_jtag_rstb, // (from dbg_test_bscan block)JTAG controlleable reset the AIB IO circuitry
input i_jtag_rstb_en, // (from dbg_test_bscan block)JTAG controlleable override to reset the AIB IO circuitry
input i_jtag_tdi, // (from dbg_test_bscan block)TDI
input i_jtag_tx_scanen,// (from dbg_test_bscan block)Drives AIB IO jtag_tx_scanen_in or BSR shift control
input i_jtag_weakpdn, //(from dbg_test_bscan block)Enable AIB global pull down test.
input i_jtag_weakpu, //(from dbg_test_bscan block)Enable AIB global pull up test.
//output TCB
output o_jtag_tdo //last boundary scan chain output, TDO
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire aibaux_osc_clk; // From u_aibcr3aux_top_wrp of aibcr3aux_top_wrp.v
wire aibaux_por_vcchssi; // From u_aibcr3aux_top_wrp of aibcr3aux_top_wrp.v
wire aibaux_por_vccl; // From u_aibcr3aux_top_wrp of aibcr3aux_top_wrp.v
c3aibadapt_wrap_top_v2s u_c3aibadapt_wrap_top
(/*AUTOINST*/
// Outputs
.i_por_aib_vcchssi(aibaux_por_vcchssi),
.i_por_aib_vccl(aibaux_por_vccl),
.fs_mac_rdy (fs_mac_rdy[TOTAL_CHNL_NUM-1:0]),
.o_cfg_avmm_rdatavld (o_cfg_avmm_rdatavld),
.o_cfg_avmm_rdata (o_cfg_avmm_rdata[31:0]),
.o_cfg_avmm_waitreq (o_cfg_avmm_waitreq),
// .o_osc_clk (), // Templated
// .o_chnl_ssr (),
.m_fs_fwd_clk (m_fs_fwd_clk[TOTAL_CHNL_NUM-1:0]),
.m_fs_fwd_div2_clk (m_fs_fwd_div2_clk[TOTAL_CHNL_NUM-1:0]),
.m_fs_rcv_clk (m_fs_rcv_clk[TOTAL_CHNL_NUM-1:0]),
.m_fs_rcv_div2_clk (m_fs_rcv_div2_clk),
// .o_tx_pma_data (),
.ns_mac_rdy (ns_mac_rdy[TOTAL_CHNL_NUM-1:0]),
.ns_adapter_rstn (ns_adapter_rstn[TOTAL_CHNL_NUM-1:0]),
.m_rxfifo_align_done (m_rxfifo_align_done),
.ms_sideband (ms_sideband[TOTAL_CHNL_NUM*81-1:0]),
.sl_sideband (sl_sideband[TOTAL_CHNL_NUM*73-1:0]),
.ms_tx_transfer_en (ms_tx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.ms_rx_transfer_en (ms_rx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_tx_transfer_en (sl_tx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_rx_transfer_en (sl_rx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.ms_tx_dcc_dll_lock_req (24'h0),
.ms_rx_dcc_dll_lock_req (24'h0),
.sl_tx_dcc_dll_lock_req (sl_tx_dcc_dll_lock_req[TOTAL_CHNL_NUM-1:0]),
.sl_rx_dcc_dll_lock_req (sl_rx_dcc_dll_lock_req[TOTAL_CHNL_NUM-1:0]),
.o_test_c3adapt_scan_out (),
.o_test_c3adapttcb_jtag (), // Templated
.o_jtag_last_bs_chain_out (o_jtag_tdo), // Templated
.o_red_idataselb_out_chain1 (red_idataselb_in_chain1), // Templated
.o_red_idataselb_out_chain2 (red_idataselb_in_chain2), // Templated
.o_red_shift_en_out_chain1 (red_shift_en_in_chain1), // Templated
.o_red_shift_en_out_chain2 (red_shift_en_in_chain2), // Templated
.o_txen_out_chain1 (o_txen_out_chain1),
.o_txen_out_chain2 (o_txen_out_chain2),
.o_directout_data_chain1_out (o_directout_data_chain1_out),
.o_directout_data_chain2_out (o_directout_data_chain2_out),
.scan_clk (scan_clk),
.scan_enable (scan_enable),
// .scan_in (scan_in),
.scan_in_ch0 (scan_in_ch0),
.scan_in_ch1 (scan_in_ch1),
.scan_in_ch2 (scan_in_ch2),
.scan_in_ch3 (scan_in_ch3),
.scan_in_ch4 (scan_in_ch4),
.scan_in_ch5 (scan_in_ch5),
.scan_in_ch6 (scan_in_ch6),
.scan_in_ch7 (scan_in_ch7),
.scan_in_ch8 (scan_in_ch8),
.scan_in_ch9 (scan_in_ch9),
.scan_in_ch10 (scan_in_ch10),
.scan_in_ch11 (scan_in_ch11),
.scan_in_ch12 (scan_in_ch12),
.scan_in_ch13 (scan_in_ch13),
.scan_in_ch14 (scan_in_ch14),
.scan_in_ch15 (scan_in_ch15),
.scan_in_ch16 (scan_in_ch16),
.scan_in_ch17 (scan_in_ch17),
.scan_in_ch18 (scan_in_ch18),
.scan_in_ch19 (scan_in_ch19),
.scan_in_ch20 (scan_in_ch20),
.scan_in_ch21 (scan_in_ch21),
.scan_in_ch22 (scan_in_ch22),
.scan_in_ch23 (scan_in_ch23),
// .scan_out (scan_out),
.scan_out_ch0 (scan_out_ch0),
.scan_out_ch1 (scan_out_ch1),
.scan_out_ch2 (scan_out_ch2),
.scan_out_ch3 (scan_out_ch3),
.scan_out_ch4 (scan_out_ch4),
.scan_out_ch5 (scan_out_ch5),
.scan_out_ch6 (scan_out_ch6),
.scan_out_ch7 (scan_out_ch7),
.scan_out_ch8 (scan_out_ch8),
.scan_out_ch9 (scan_out_ch9),
.scan_out_ch10 (scan_out_ch10),
.scan_out_ch11 (scan_out_ch11),
.scan_out_ch12 (scan_out_ch12),
.scan_out_ch13 (scan_out_ch13),
.scan_out_ch14 (scan_out_ch14),
.scan_out_ch15 (scan_out_ch15),
.scan_out_ch16 (scan_out_ch16),
.scan_out_ch17 (scan_out_ch17),
.scan_out_ch18 (scan_out_ch18),
.scan_out_ch19 (scan_out_ch19),
.scan_out_ch20 (scan_out_ch20),
.scan_out_ch21 (scan_out_ch21),
.scan_out_ch22 (scan_out_ch22),
.scan_out_ch23 (scan_out_ch23),
// .o_aibdftdll2adjch (),
// Inouts
.io_aib_ch0 (s0_ch0_aib[95:0]),
.io_aib_ch1 (s0_ch1_aib[95:0]),
.io_aib_ch2 (s0_ch2_aib[95:0]),
.io_aib_ch3 (s0_ch3_aib[95:0]),
.io_aib_ch4 (s0_ch4_aib[95:0]),
.io_aib_ch5 (s0_ch5_aib[95:0]),
.io_aib_ch6 (s1_ch0_aib[95:0]),
.io_aib_ch7 (s1_ch1_aib[95:0]),
.io_aib_ch8 (s1_ch2_aib[95:0]),
.io_aib_ch9 (s1_ch3_aib[95:0]),
.io_aib_ch10 (s1_ch4_aib[95:0]),
.io_aib_ch11 (s1_ch5_aib[95:0]),
.io_aib_ch12 (s2_ch0_aib[95:0]),
.io_aib_ch13 (s2_ch1_aib[95:0]),
.io_aib_ch14 (s2_ch2_aib[95:0]),
.io_aib_ch15 (s2_ch3_aib[95:0]),
.io_aib_ch16 (s2_ch4_aib[95:0]),
.io_aib_ch17 (s2_ch5_aib[95:0]),
.io_aib_ch18 (s3_ch0_aib[95:0]),
.io_aib_ch19 (s3_ch1_aib[95:0]),
.io_aib_ch20 (s3_ch2_aib[95:0]),
.io_aib_ch21 (s3_ch3_aib[95:0]),
.io_aib_ch22 (s3_ch4_aib[95:0]),
.io_aib_ch23 (s3_ch5_aib[95:0]),
// Inputs
.conf_done (i_conf_done),
.dual_mode_select (dual_mode_select),
.i_cfg_avmm_clk (i_cfg_avmm_clk),
.i_cfg_avmm_rst_n (i_cfg_avmm_rst_n),
.i_cfg_avmm_addr (i_cfg_avmm_addr[16:0]),
.i_cfg_avmm_byte_en (i_cfg_avmm_byte_en[3:0]),
.i_cfg_avmm_read (i_cfg_avmm_read),
.i_cfg_avmm_write (i_cfg_avmm_write),
.i_cfg_avmm_wdata (i_cfg_avmm_wdata[31:0]),
.m_ns_fwd_clk (m_ns_fwd_clk[TOTAL_CHNL_NUM-1:0]),
.m_ns_fwd_div2_clk (m_ns_fwd_div2_clk[TOTAL_CHNL_NUM-1:0]),
.m_wr_clk (m_wr_clk[TOTAL_CHNL_NUM-1:0]),
.data_in (data_in[TOTAL_CHNL_NUM*78-1:0]),
.i_osc_clk (aibaux_osc_clk), // Templated
// .i_chnl_ssr ({24{65'h0}}),
// .i_rx_pma_data ({24{40'h0}}),
.m_ns_rcv_clk (m_ns_rcv_clk[TOTAL_CHNL_NUM-1:0]),
.m_rd_clk (m_rd_clk[TOTAL_CHNL_NUM-1:0]),
.data_out (data_out[TOTAL_CHNL_NUM*78-1:0]),
.i_scan_clk (i_scan_clk),
.i_test_clk_125m (1'b0),
.i_test_clk_1g (1'b0),
.i_test_clk_250m (1'b0),
.i_test_clk_500m (1'b0),
.i_test_clk_62m (1'b0),
.i_test_c3adapt_scan_in ({24{17'h0}}),
.i_test_c3adapt_tcb_static_common({58'h0, i_test_scan_en, i_test_scan_mode}),
.i_jtag_rstb_in (i_jtag_rstb), // Templated
.i_jtag_rstb_en_in (i_jtag_rstb_en), // Templated
.i_jtag_clkdr_in (i_jtag_clkdr), // Templated
.i_jtag_clksel_in (i_jtag_clksel), // Templated
.i_jtag_intest_in (i_jtag_intest), // Templated
.i_jtag_mode_in (i_jtag_mode), // Templated
.i_jtag_weakpdn_in (i_jtag_weakpdn), // Templated
.i_jtag_weakpu_in (i_jtag_weakpu), // Templated
.i_jtag_bs_scanen_in (i_jtag_tx_scanen), // Templated
.i_jtag_bs_chain_in (i_jtag_tdi) // Templated
); // Templated
aib_aux_dual aib_aux_dual
(
// AIB IO Bidirectional
.device_detect(device_detect),
.por(por),
// .device_detect_ms(ms_device_detect),
.i_osc_clk(i_osc_clk),
.m_i_por_ovrd(1'b0),
.m_i_device_detect_ovrd(m_device_detect_ovrd),
.m_o_power_on_reset(),
.m_o_device_detect(m_device_detect),
.o_por_vcchssi(aibaux_por_vcchssi),
.o_por_vccl(aibaux_por_vccl),
.osc_clkout(aibaux_osc_clk),
.m_i_power_on_reset(m_power_on_reset),
.ms_nsl(dual_mode_select)
);
endmodule // aib_top |
module aib_top_v2m
# (
parameter TOTAL_CHNL_NUM = 24
)
(
//================================================================================================
// Reset Inteface
input i_conf_done, // AIB adaptor hard reset
// reset for XCVRIF
output [TOTAL_CHNL_NUM-1:0] fs_mac_rdy, // chiplet xcvr receiving path reset, the reset is controlled by remote chiplet which is FPGA in this case
//===============================================================================================
// Configuration Interface which includes two paths
// Path directly from chip programming controller
input i_cfg_avmm_clk,
input i_cfg_avmm_rst_n,
input [16:0] i_cfg_avmm_addr, // address to be programmed
input [3:0] i_cfg_avmm_byte_en, // byte enable
input i_cfg_avmm_read, // Asserted to indicate the Cfg read access
input i_cfg_avmm_write, // Asserted to indicate the Cfg write access
input [31:0] i_cfg_avmm_wdata, // data to be programmed
output o_cfg_avmm_rdatavld,// Assert to indicate data available for Cfg read access
output [31:0] o_cfg_avmm_rdata, // data returned for Cfg read access
output o_cfg_avmm_waitreq, // asserted to indicate not ready for Cfg access
//===============================================================================================
// Data Path
// Rx Path clocks/data, from master (current chiplet) to slave (FPGA)
input [TOTAL_CHNL_NUM-1:0] m_ns_fwd_clk, // Rx path clk for data receiving, may generated from xcvr pll
input [TOTAL_CHNL_NUM-1:0] m_ns_fwd_div2_clk, // Divided by 2 clock on Rx pathinput
// input [TOTAL_CHNL_NUM*65-1:0] i_chnl_ssr, // Slow shift chain path, tie to 0s if not used
input [TOTAL_CHNL_NUM*40-1:0] data_in_reg_mode, // data out for direct register mode
input [TOTAL_CHNL_NUM-1:0] m_wr_clk, //Clock for phase compensation fifo
input [TOTAL_CHNL_NUM*78-1:0] data_in, //data in for phase compensation fifo
// Tx Path clocks/data, from slave (FPGA) to master (current chiplet)
input [TOTAL_CHNL_NUM-1:0] m_ns_rcv_clk, // this clock is sent over to the other chiplet to be used for the clock as the data transmission
// output [TOTAL_CHNL_NUM*61-1:0] o_chnl_ssr, // Slow shift chain path, left unconnected if not used
output [TOTAL_CHNL_NUM-1:0] m_fs_fwd_clk, // clock used for tx data transmission
output [TOTAL_CHNL_NUM-1:0] m_fs_fwd_div2_clk, // half rate of tx data transmission clock
output [TOTAL_CHNL_NUM*40-1:0] data_out_reg_mode, //data out during direct register mode.
input [TOTAL_CHNL_NUM-1:0] m_rd_clk, //Clock for phase compensation fifo
output [TOTAL_CHNL_NUM*78-1:0] data_out, // data out for phase compensation fifo
//=================================================================================================
// AIB open source IP enhancement. The following ports are added to
// be compliance with AIB specification 1.1
input [TOTAL_CHNL_NUM-1:0] ns_mac_rdy, //From Mac. To indicate MAC is ready to send and receive data. use aibio49
input [TOTAL_CHNL_NUM-1:0] ns_adapter_rstn, //From Mac. To reset near adapt reset sm and far side reset sm. aibio56
output [TOTAL_CHNL_NUM*81-1:0] ms_sideband, //Status of serial shifting bit from this master chiplet to slave chiplet
output [TOTAL_CHNL_NUM*73-1:0] sl_sideband, //Status of serial shifting bit from slave chiplet to master chiplet.
output [TOTAL_CHNL_NUM-1:0] ms_rx_transfer_en, //master link rx transfer enable
output [TOTAL_CHNL_NUM-1:0] ms_tx_transfer_en, //master link tx transfer enable
output [TOTAL_CHNL_NUM-1:0] sl_rx_transfer_en, //slave link rx transfer enable
output [TOTAL_CHNL_NUM-1:0] sl_tx_transfer_en, //slave link tx transfer enable
output [TOTAL_CHNL_NUM-1:0] m_rxfifo_align_done, //Newly added rx data fifo alignment done signal.
//=================================================================================================
// Inout signals for AIB ubump
inout [95:0] m0_ch0_aib,
inout [95:0] m0_ch1_aib,
inout [95:0] m0_ch2_aib,
inout [95:0] m0_ch3_aib,
inout [95:0] m0_ch4_aib,
inout [95:0] m0_ch5_aib,
inout [95:0] m1_ch0_aib,
inout [95:0] m1_ch1_aib,
inout [95:0] m1_ch2_aib,
inout [95:0] m1_ch3_aib,
inout [95:0] m1_ch4_aib,
inout [95:0] m1_ch5_aib,
inout [95:0] m2_ch0_aib,
inout [95:0] m2_ch1_aib,
inout [95:0] m2_ch2_aib,
inout [95:0] m2_ch3_aib,
inout [95:0] m2_ch4_aib,
inout [95:0] m2_ch5_aib,
inout [95:0] m3_ch0_aib,
inout [95:0] m3_ch1_aib,
inout [95:0] m3_ch2_aib,
inout [95:0] m3_ch3_aib,
inout [95:0] m3_ch4_aib,
inout [95:0] m3_ch5_aib,
// inout [95:0] io_aib_aux,
// inout io_aib_aux74,
// inout io_aib_aux75,
inout device_detect,
// inout io_aib_aux85,
// inout io_aib_aux87,
inout por,
// inout io_aux_bg_ext_2k, //connect to external 2k resistor, C4 bump
//======================================================================================
input m_por_ovrd, //test por override through c4 bump
//
input i_osc_clk, // test clock from c4 bump, may tie low for User if not used
// output o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator, User may use this clock to connect with i_test_clk_1g
//======================================================================================
// DFT signals
input i_scan_clk, //ATPG Scan shifting clock from Test Pad.
// input i_test_clk_1g, //1GHz free running direct accessed ATPG at speed clock.
// input i_test_clk_125m,//Divided down from i_test_clk_1g.
// input i_test_clk_250m,//Divided down from i_test_clk_1g.
// input i_test_clk_500m,//Divided down from i_test_clk_1g.
// input i_test_clk_62m, //Divided down from i_test_clk_1g.
//The divided down clock is for different clock domain at
//speed test.
//Channel ATPG signals from/to CODEC
// input [TOTAL_CHNL_NUM-1:0] [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] i_test_c3adapt_scan_in, //scan in hook from Codec
input i_test_scan_en, //Terminate i_test_c3adapt_tcb_static_common, only pull out Scan enable
input i_test_scan_mode,
// output [TOTAL_CHNL_NUM-1:0] [`AIBADAPTWRAPTCB_SCAN_CHAINS_RNG] o_test_c3adapt_scan_out, //scan out hook to Codec
//Inputs from TCB (JTAG signals)
input i_jtag_clkdr, // (from dbg_test_bscan block)Enable AIB IO boundary scan clock (clock gate control)
input i_jtag_clksel, // (from dbg_test_bscan block)Select between i_jtag_clkdr_in and functional clk
input i_jtag_intest, // (from dbg_test_bscan block)Enable in test operation
input i_jtag_mode, // (from dbg_test_bscan block)Selects between AIB BSR register or functional path
input i_jtag_rstb, // (from dbg_test_bscan block)JTAG controlleable reset the AIB IO circuitry
input i_jtag_rstb_en, // (from dbg_test_bscan block)JTAG controlleable override to reset the AIB IO circuitry
input i_jtag_tdi, // (from dbg_test_bscan block)TDI
input i_jtag_tx_scanen,// (from dbg_test_bscan block)Drives AIB IO jtag_tx_scanen_in or BSR shift control
input i_jtag_weakpdn, //(from dbg_test_bscan block)Enable AIB global pull down test.
input i_jtag_weakpu, //(from dbg_test_bscan block)Enable AIB global pull up test.
//output TCB
output o_jtag_tdo, //last boundary scan chain output, TDO
output m_power_on_reset // S10 POR to User, can be left unconnected for User
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire aibaux_osc_clk; // From u_aibcr3aux_top_wrp of aibcr3aux_top_wrp.v
wire aibaux_por_vcchssi; // From u_aibcr3aux_top_wrp of aibcr3aux_top_wrp.v
wire aibaux_por_vccl; // From u_aibcr3aux_top_wrp of aibcr3aux_top_wrp.v
c3aibadapt_wrap_top u_c3aibadapt_wrap_top
(/*AUTOINST*/
// Outputs
.o_rx_xcvrif_rst_n (fs_mac_rdy[TOTAL_CHNL_NUM-1:0]),
.o_cfg_avmm_rdatavld (o_cfg_avmm_rdatavld),
.o_cfg_avmm_rdata (o_cfg_avmm_rdata[31:0]),
.o_cfg_avmm_waitreq (o_cfg_avmm_waitreq),
.o_osc_clk (), // Templated
.o_chnl_ssr (),
.o_tx_transfer_clk (m_fs_fwd_clk[TOTAL_CHNL_NUM-1:0]),
.o_tx_transfer_div2_clk (m_fs_fwd_div2_clk[TOTAL_CHNL_NUM-1:0]),
.o_tx_pma_data (data_out_reg_mode),
.ns_mac_rdy (ns_mac_rdy[TOTAL_CHNL_NUM-1:0]),
.ns_adapt_rstn (ns_adapter_rstn[TOTAL_CHNL_NUM-1:0]),
.m_rxfifo_align_done (m_rxfifo_align_done[TOTAL_CHNL_NUM-1:0]),
.ms_sideband (ms_sideband[TOTAL_CHNL_NUM*81-1:0]),
.sl_sideband (sl_sideband[TOTAL_CHNL_NUM*73-1:0]),
.ms_tx_transfer_en (ms_tx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.ms_rx_transfer_en (ms_rx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_tx_transfer_en (sl_tx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.sl_rx_transfer_en (sl_rx_transfer_en[TOTAL_CHNL_NUM-1:0]),
.o_test_c3adapt_scan_out (),
.o_test_c3adapttcb_jtag (), // Templated
.o_jtag_last_bs_chain_out (o_jtag_tdo), // Templated
.o_red_idataselb_out_chain1 (red_idataselb_in_chain1), // Templated
.o_red_idataselb_out_chain2 (red_idataselb_in_chain2), // Templated
.o_red_shift_en_out_chain1 (red_shift_en_in_chain1), // Templated
.o_red_shift_en_out_chain2 (red_shift_en_in_chain2), // Templated
.o_txen_out_chain1 (o_txen_out_chain1),
.o_txen_out_chain2 (o_txen_out_chain2),
.o_directout_data_chain1_out (o_directout_data_chain1_out),
.o_directout_data_chain2_out (o_directout_data_chain2_out),
.o_aibdftdll2adjch (),
// Inouts
.io_aib_ch0 (m0_ch0_aib[95:0]),
.io_aib_ch1 (m0_ch1_aib[95:0]),
.io_aib_ch2 (m0_ch2_aib[95:0]),
.io_aib_ch3 (m0_ch3_aib[95:0]),
.io_aib_ch4 (m0_ch4_aib[95:0]),
.io_aib_ch5 (m0_ch5_aib[95:0]),
.io_aib_ch6 (m1_ch0_aib[95:0]),
.io_aib_ch7 (m1_ch1_aib[95:0]),
.io_aib_ch8 (m1_ch2_aib[95:0]),
.io_aib_ch9 (m1_ch3_aib[95:0]),
.io_aib_ch10 (m1_ch4_aib[95:0]),
.io_aib_ch11 (m1_ch5_aib[95:0]),
.io_aib_ch12 (m2_ch0_aib[95:0]),
.io_aib_ch13 (m2_ch1_aib[95:0]),
.io_aib_ch14 (m2_ch2_aib[95:0]),
.io_aib_ch15 (m2_ch3_aib[95:0]),
.io_aib_ch16 (m2_ch4_aib[95:0]),
.io_aib_ch17 (m2_ch5_aib[95:0]),
.io_aib_ch18 (m3_ch0_aib[95:0]),
.io_aib_ch19 (m3_ch1_aib[95:0]),
.io_aib_ch20 (m3_ch2_aib[95:0]),
.io_aib_ch21 (m3_ch3_aib[95:0]),
.io_aib_ch22 (m3_ch4_aib[95:0]),
.io_aib_ch23 (m3_ch5_aib[95:0]),
// Inputs
.i_adpt_hard_rst_n (i_conf_done),
.i_cfg_avmm_clk (i_cfg_avmm_clk),
.i_cfg_avmm_rst_n (i_cfg_avmm_rst_n),
.i_cfg_avmm_addr (i_cfg_avmm_addr[16:0]),
.i_cfg_avmm_byte_en (i_cfg_avmm_byte_en[3:0]),
.i_cfg_avmm_read (i_cfg_avmm_read),
.i_cfg_avmm_write (i_cfg_avmm_write),
.i_cfg_avmm_wdata (i_cfg_avmm_wdata[31:0]),
.i_rx_pma_clk (m_ns_fwd_clk[TOTAL_CHNL_NUM-1:0]),
.i_rx_pma_div2_clk (m_ns_fwd_div2_clk[TOTAL_CHNL_NUM-1:0]),
.i_rx_elane_clk (m_wr_clk[TOTAL_CHNL_NUM-1:0]),
.i_rx_elane_data (data_in[TOTAL_CHNL_NUM*78-1:0]),
.i_osc_clk (aibaux_osc_clk), // Templated
.i_chnl_ssr ({24{65'h0}}),
.i_rx_pma_data (data_in_reg_mode),
.i_tx_pma_clk (m_ns_rcv_clk[TOTAL_CHNL_NUM-1:0]),
.i_tx_elane_clk (m_rd_clk[TOTAL_CHNL_NUM-1:0]),
.o_tx_elane_data (data_out[TOTAL_CHNL_NUM*78-1:0]),
.i_scan_clk (i_scan_clk),
.i_test_clk_125m (1'b0),
.i_test_clk_1g (1'b0),
.i_test_clk_250m (1'b0),
.i_test_clk_500m (1'b0),
.i_test_clk_62m (1'b0),
.i_test_c3adapt_scan_in ({24{17'h0}}),
.i_test_c3adapt_tcb_static_common({58'h0, i_test_scan_en, i_test_scan_mode}),
.i_jtag_rstb_in (i_jtag_rstb),
.i_jtag_rstb_en_in (i_jtag_rstb_en),
.i_jtag_clkdr_in (i_jtag_clkdr),
.i_jtag_clksel_in (i_jtag_clksel),
.i_jtag_intest_in (i_jtag_intest),
.i_jtag_mode_in (i_jtag_mode),
.i_jtag_weakpdn_in (i_jtag_weakpdn),
.i_jtag_weakpu_in (i_jtag_weakpu),
.i_jtag_bs_scanen_in (i_jtag_tx_scanen),
.i_jtag_bs_chain_in (i_jtag_tdi),
.i_por_aib_vcchssi (aibaux_por_vcchssi),
.i_por_aib_vccl (aibaux_por_vccl));
assign m_power_on_reset = aibaux_por_vcchssi;
aibcr3aux_top_master aibcr3aux_top_master (
.o_por_vcchssi (aibaux_por_vcchssi),
.o_por_vccl (aibaux_por_vccl),
.osc_clkout (aibaux_osc_clk),
.device_detect (device_detect),
.por (por),
.m_por_ovrd (m_por_ovrd),
.i_osc_clk (i_osc_clk)
);
endmodule // aib_top |
module aibndaux_top_slave ( o_crdet, u_crdet, u_crdet_r, u_dn_por, u_dn_por_r, i_dn_por, i_crdet_ovrd);
output o_crdet;
inout u_crdet, u_crdet_r, u_dn_por, u_dn_por_r;
input i_dn_por, i_crdet_ovrd;
wire o_crete_detect;
assign vccl_aibndaux = 1'b1;
assign vssl_aibndaux = 1'b0;
assign o_crdet = o_crete_detect | i_crdet_ovrd;
aibndaux_aliasd aliasd2 ( .PLUS(u_dn_por), .MINUS(u_dn_por_r));
aibndaux_pasred_simple xpasred ( .crete_detect(o_crete_detect),
.iopad_crdet(u_crdet),
.vssl_aibndaux(vssl_aibndaux),
.vccl_aibndaux(vccl_aibndaux),
.iopad_dn_por(u_dn_por),
.dn_por(i_dn_por)
);
endmodule |
module aibndaux_pasred_simple ( crete_detect, iopad_crdet,
iopad_dn_por, dn_por, vccl_aibndaux, vssl_aibndaux );
output crete_detect;
inout iopad_crdet, iopad_dn_por;
input dn_por, vccl_aibndaux, vssl_aibndaux;
aibnd_buffx1_top xcrdet ( .idata1_in1_jtag_out(),
.async_dat_in1_jtag_out(), .idata0_in1_jtag_out(),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(),
.anlg_rstb(vccl_aibndaux), .pd_data_aib(),
.oclk_out(), .oclkb_out(), .odat0_out(),
.odat1_out(), .odat_async_out(crete_detect),
.pd_data_out(), .async_dat_in0(vssl_aibndaux),
.async_dat_in1(vssl_aibndaux), .iclkin_dist_in0(vssl_aibndaux),
.iclkin_dist_in1(vssl_aibndaux), .idata0_in0(vssl_aibndaux),
.idata0_in1(vssl_aibndaux), .idata1_in0(vssl_aibndaux),
.idata1_in1(vssl_aibndaux), .idataselb_in0(vssl_aibndaux),
.idataselb_in1(vssl_aibndaux), .iddren_in0(vssl_aibndaux),
.iddren_in1(vssl_aibndaux), .ilaunch_clk_in0(vssl_aibndaux),
.ilaunch_clk_in1(vssl_aibndaux), .ilpbk_dat_in0(vssl_aibndaux),
.ilpbk_dat_in1(vssl_aibndaux), .ilpbk_en_in0(vssl_aibndaux),
.ilpbk_en_in1(vssl_aibndaux), .indrv_in0({vssl_aibndaux,
vssl_aibndaux}), .indrv_in1({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in0({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in1({vssl_aibndaux, vssl_aibndaux}),
.irxen_in0({vssl_aibndaux,vssl_aibndaux,vssl_aibndaux}),
.irxen_in1({vssl_aibndaux,vssl_aibndaux,vssl_aibndaux}), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(vssl_aibndaux),
.itxen_in1(vssl_aibndaux), .oclk_in1(vssl_aibndaux),
.odat_async_aib(), .oclkb_in1(vssl_aibndaux),
.jtag_clksel(vssl_aibndaux), .odat0_in1(vssl_aibndaux),
.vssl_aibnd(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(vccl_aibndaux),
.jtag_clkdr_out(), .jtag_intest(vssl_aibndaux),
.odat1_aib(), .jtag_rx_scan_out(), .odat0_aib(),
.oclk_aib(), .last_bs_out(),
.vccl_aibnd(vccl_aibndaux), .oclkb_aib(),
.jtag_clkdr_in(vssl_aibndaux), .jtag_rstb_en(vssl_aibndaux),
.jtag_mode_in(vssl_aibndaux), .jtag_rstb(vssl_aibndaux),
.jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_crdet), .oclkn(), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vccl_aibndaux));
aibnd_buffx1_top xdn_por ( .idata1_in1_jtag_out(),
.async_dat_in1_jtag_out(), .idata0_in1_jtag_out(),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(),
.jtag_clksel(vssl_aibndaux), .vssl_aibnd(vssl_aibndaux),
.jtag_intest(vssl_aibndaux), .vccl_aibnd(vccl_aibndaux),
.jtag_rstb_en(vssl_aibndaux), .anlg_rstb(vccl_aibndaux),
.pd_data_aib(), .oclk_out(), .oclkb_out(),
.odat0_out(), .odat1_out(),
.odat_async_out(), .pd_data_out(),
.async_dat_in0(dn_por), .async_dat_in1(vssl_aibndaux),
.iclkin_dist_in0(vssl_aibndaux), .iclkin_dist_in1(vssl_aibndaux),
.idata0_in0(vssl_aibndaux), .idata0_in1(vssl_aibndaux),
.idata1_in0(vssl_aibndaux), .idata1_in1(vssl_aibndaux),
.idataselb_in0(vssl_aibndaux), .idataselb_in1(vssl_aibndaux),
.iddren_in0(vssl_aibndaux), .iddren_in1(vssl_aibndaux),
.ilaunch_clk_in0(vssl_aibndaux), .ilaunch_clk_in1(vssl_aibndaux),
.ilpbk_dat_in0(vssl_aibndaux), .ilpbk_dat_in1(vssl_aibndaux),
.ilpbk_en_in0(vssl_aibndaux), .ilpbk_en_in1(vssl_aibndaux),
.indrv_in0({vccl_aibndaux, vssl_aibndaux}),
.indrv_in1({vccl_aibndaux, vssl_aibndaux}),
.ipdrv_in0({vccl_aibndaux, vssl_aibndaux}),
.ipdrv_in1({vccl_aibndaux, vssl_aibndaux}), .irxen_in0({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .irxen_in1({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(vccl_aibndaux),
.itxen_in1(vccl_aibndaux), .oclk_in1(vssl_aibndaux),
.odat_async_aib(), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(vccl_aibndaux),
.jtag_clkdr_out(), .odat1_aib(),
.jtag_rx_scan_out(), .odat0_aib(),
.oclk_aib(), .last_bs_out(), .oclkb_aib(),
.jtag_clkdr_in(vssl_aibndaux), .jtag_mode_in(vssl_aibndaux),
.jtag_rstb(vssl_aibndaux), .jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_dn_por), .oclkn(), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vssl_aibndaux));
endmodule |
module aibndaux_aliasd ( PLUS, MINUS );
input PLUS;
output MINUS;
assign MINUS = PLUS;
endmodule |
module aibndaux_actred ( actred_chain1, actred_chain2,
jtag_rx_scan_out_01x1, jtag_rx_scan_out_01x2, last_bs_out_01x1,
last_bs_out_01x2, iopad_actred_chain1, iopad_actred_chain2,
actred_rxen_chain1, actred_rxen_chain2, actred_shiften_chain1,
actred_shiften_chain2, anlg_rstb, dig_rstb, jtag_clkdr_in1l,
jtag_clkdr_in2l, jtag_clksel, jtag_intest, jtag_mode_in,
jtag_rstb, jtag_rstb_en, jtag_tx_scan_in_01x1,
jtag_tx_scan_in_01x2, jtag_tx_scanen_in, jtag_weakpdn,
jtag_weakpu, last_bs_in_01x1, last_bs_in_01x2, vccl_aibndaux,
vssl_aibndaux );
output actred_chain1, actred_chain2, jtag_rx_scan_out_01x1,
jtag_rx_scan_out_01x2, last_bs_out_01x1, last_bs_out_01x2;
inout iopad_actred_chain1, iopad_actred_chain2;
input actred_shiften_chain1, actred_shiften_chain2, anlg_rstb,
dig_rstb, jtag_clkdr_in1l, jtag_clkdr_in2l, jtag_clksel,
jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en,
jtag_tx_scan_in_01x1, jtag_tx_scan_in_01x2, jtag_tx_scanen_in,
jtag_weakpdn, jtag_weakpu, last_bs_in_01x1, last_bs_in_01x2,
vccl_aibndaux, vssl_aibndaux;
input [2:0] actred_rxen_chain1;
input [2:0] actred_rxen_chain2;
// specify
// specparam CDS_LIBNAME = "aibndaux_lib";
// specparam CDS_CELLNAME = "aibndaux_actred";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
aibnd_buffx1_top xio_in0 ( .idata1_in1_jtag_out(net036),
.async_dat_in1_jtag_out(net035), .idata0_in1_jtag_out(net034),
.prev_io_shift_en(actred_shiften_chain1),
.jtag_clkdr_outn(net024), .jtag_clksel(jtag_clksel),
.vssl_aibnd(vssl_aibndaux), .jtag_intest(jtag_intest),
.vccl_aibnd(vccl_aibndaux), .jtag_rstb_en(jtag_rstb_en),
.anlg_rstb(anlg_rstb), .pd_data_aib(net089), .oclk_out(net072),
.oclkb_out(net073), .odat0_out(net074), .odat1_out(net075),
.odat_async_out(net026), .pd_data_out(net076),
.async_dat_in0(vssl_aibndaux), .async_dat_in1(vssl_aibndaux),
.iclkin_dist_in0(vssl_aibndaux), .iclkin_dist_in1(vssl_aibndaux),
.idata0_in0(vssl_aibndaux), .idata0_in1(vssl_aibndaux),
.idata1_in0(vssl_aibndaux), .idata1_in1(vssl_aibndaux),
.idataselb_in0(vssl_aibndaux), .idataselb_in1(vssl_aibndaux),
.iddren_in0(vssl_aibndaux), .iddren_in1(vssl_aibndaux),
.ilaunch_clk_in0(vssl_aibndaux), .ilaunch_clk_in1(vssl_aibndaux),
.ilpbk_dat_in0(vssl_aibndaux), .ilpbk_dat_in1(vssl_aibndaux),
.ilpbk_en_in0(vssl_aibndaux), .ilpbk_en_in1(vssl_aibndaux),
.indrv_in0({vssl_aibndaux, vssl_aibndaux}),
.indrv_in1({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in0({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in1({vssl_aibndaux, vssl_aibndaux}),
.irxen_in0({vssl_aibndaux, vssl_aibndaux, vssl_aibndaux}),
.irxen_in1(actred_rxen_chain1[2:0]), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(vssl_aibndaux),
.itxen_in1(vssl_aibndaux), .oclk_in1(vssl_aibndaux),
.odat_async_aib(actred_chain1), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(actred_shiften_chain1),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net023), .odat1_aib(net087),
.jtag_rx_scan_out(jtag_rx_scan_out_01x2), .odat0_aib(net086),
.oclk_aib(net084), .last_bs_out(last_bs_out_01x2),
.oclkb_aib(net085), .jtag_clkdr_in(jtag_clkdr_in2l),
.jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb),
.jtag_tx_scan_in(jtag_tx_scan_in_01x2),
.jtag_tx_scanen_in(jtag_tx_scanen_in),
.last_bs_in(last_bs_in_01x2), .iopad(iopad_actred_chain1),
.oclkn(net083), .iclkn(vssl_aibndaux), .test_weakpu(jtag_weakpu),
.test_weakpd(jtag_weakpdn));
aibnd_buffx1_top xio_in1 ( .idata1_in1_jtag_out(net031),
.async_dat_in1_jtag_out(net032), .idata0_in1_jtag_out(net033),
.prev_io_shift_en(actred_shiften_chain2),
.jtag_clkdr_outn(net022), .jtag_clksel(jtag_clksel),
.vssl_aibnd(vssl_aibndaux), .jtag_intest(jtag_intest),
.vccl_aibnd(vccl_aibndaux), .jtag_rstb_en(jtag_rstb_en),
.anlg_rstb(anlg_rstb), .pd_data_aib(net096), .oclk_out(net078),
.oclkb_out(net079), .odat0_out(net080), .odat1_out(net081),
.odat_async_out(net025), .pd_data_out(net082),
.async_dat_in0(vssl_aibndaux), .async_dat_in1(vssl_aibndaux),
.iclkin_dist_in0(vssl_aibndaux), .iclkin_dist_in1(vssl_aibndaux),
.idata0_in0(vssl_aibndaux), .idata0_in1(vssl_aibndaux),
.idata1_in0(vssl_aibndaux), .idata1_in1(vssl_aibndaux),
.idataselb_in0(vssl_aibndaux), .idataselb_in1(vssl_aibndaux),
.iddren_in0(vssl_aibndaux), .iddren_in1(vssl_aibndaux),
.ilaunch_clk_in0(vssl_aibndaux), .ilaunch_clk_in1(vssl_aibndaux),
.ilpbk_dat_in0(vssl_aibndaux), .ilpbk_dat_in1(vssl_aibndaux),
.ilpbk_en_in0(vssl_aibndaux), .ilpbk_en_in1(vssl_aibndaux),
.indrv_in0({vssl_aibndaux, vssl_aibndaux}),
.indrv_in1({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in0({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in1({vssl_aibndaux, vssl_aibndaux}),
.irxen_in0(actred_rxen_chain1[2:0]),
.irxen_in1(actred_rxen_chain2[2:0]), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(vssl_aibndaux),
.itxen_in1(vssl_aibndaux), .oclk_in1(vssl_aibndaux),
.odat_async_aib(actred_chain2), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(actred_shiften_chain2),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net021), .odat1_aib(net094),
.jtag_rx_scan_out(jtag_rx_scan_out_01x1), .odat0_aib(net093),
.oclk_aib(net091), .last_bs_out(last_bs_out_01x1),
.oclkb_aib(net092), .jtag_clkdr_in(jtag_clkdr_in1l),
.jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb),
.jtag_tx_scan_in(jtag_tx_scan_in_01x1),
.jtag_tx_scanen_in(jtag_tx_scanen_in),
.last_bs_in(last_bs_in_01x1), .iopad(iopad_actred_chain2),
.oclkn(net090), .iclkn(vssl_aibndaux), .test_weakpu(jtag_weakpu),
.test_weakpd(jtag_weakpdn));
endmodule |
module aibndaux_pasred ( crete_detect, jtr_tck, jtr_tdo, jtr_tms, iopad_crdet,
iopad_dn_por, iopad_dn_rst_n, iopad_jt_tck, iopad_jt_tdi,
iopad_jt_tms, iopad_jtr_tck, iopad_jtr_tdo, iopad_jtr_tms,
anlg_rstb, csr_iocsr_sel, csr_pred_dataselb, csr_pred_ndrv,
csr_pred_pdrv, csr_pred_rxen, csr_pred_txen, dig_rstb, dn_por,
dn_rst_n, jt_tck, jt_tdi, jt_tms, vccl_aibndaux, vssl_aibndaux );
output crete_detect, jtr_tck, jtr_tdo, jtr_tms;
inout iopad_crdet, iopad_dn_por, iopad_dn_rst_n, iopad_jt_tck,
iopad_jt_tdi, iopad_jt_tms, iopad_jtr_tck, iopad_jtr_tdo,
iopad_jtr_tms;
input anlg_rstb, csr_iocsr_sel, csr_pred_dataselb, csr_pred_txen,
dig_rstb, dn_por, dn_rst_n, jt_tck, jt_tdi, jt_tms, vccl_aibndaux,
vssl_aibndaux;
input [1:0] csr_pred_ndrv;
input [1:0] csr_pred_pdrv;
input [2:0] csr_pred_rxen;
wire jtr_tck, crete_detect, jtr_tck_int, jt_tck, jtr_tms, jtr_tms_int, jt_tms, jtr_tdo, jtr_tdo_int, jt_tdi, csr_iocsr_sel, vssl_aibndaux, csr_pred_txen_int, csr_pred_txen, vccl_aibndaux; // Conversion Sript Generated
// Buses in the design
wire [2:0] csr_pred_rxen_int;
wire [1:0] csr_pred_ndrv_int;
wire [1:0] csr_pred_pdrv_int;
// specify
// specparam CDS_LIBNAME = "aibndaux_lib";
// specparam CDS_CELLNAME = "aibndaux_pasred";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
aibnd_buffx1_top xcrdet ( .idata1_in1_jtag_out(net0282),
.async_dat_in1_jtag_out(net0266), .idata0_in1_jtag_out(net0310),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(net0203),
.anlg_rstb(vccl_aibndaux), .pd_data_aib(net087),
.oclk_out(net075), .oclkb_out(net076), .odat0_out(net077),
.odat1_out(net078), .odat_async_out(crete_detect),
.pd_data_out(net080), .async_dat_in0(vssl_aibndaux),
.async_dat_in1(vssl_aibndaux), .iclkin_dist_in0(vssl_aibndaux),
.iclkin_dist_in1(vssl_aibndaux), .idata0_in0(vssl_aibndaux),
.idata0_in1(vssl_aibndaux), .idata1_in0(vssl_aibndaux),
.idata1_in1(vssl_aibndaux), .idataselb_in0(vssl_aibndaux),
.idataselb_in1(vssl_aibndaux), .iddren_in0(vssl_aibndaux),
.iddren_in1(vssl_aibndaux), .ilaunch_clk_in0(vssl_aibndaux),
.ilaunch_clk_in1(vssl_aibndaux), .ilpbk_dat_in0(vssl_aibndaux),
.ilpbk_dat_in1(vssl_aibndaux), .ilpbk_en_in0(vssl_aibndaux),
.ilpbk_en_in1(vssl_aibndaux), .indrv_in0({vssl_aibndaux,
vssl_aibndaux}), .indrv_in1({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in0({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in1({vssl_aibndaux, vssl_aibndaux}),
.irxen_in0({vssl_aibndaux,vssl_aibndaux,vssl_aibndaux}),
.irxen_in1({vssl_aibndaux,vssl_aibndaux,vssl_aibndaux}), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(vssl_aibndaux),
.itxen_in1(vssl_aibndaux), .oclk_in1(vssl_aibndaux),
.odat_async_aib(net086), .oclkb_in1(vssl_aibndaux),
.jtag_clksel(vssl_aibndaux), .odat0_in1(vssl_aibndaux),
.vssl_aibnd(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net040), .jtag_intest(vssl_aibndaux),
.odat1_aib(net085), .jtag_rx_scan_out(net041), .odat0_aib(net084),
.oclk_aib(net082), .last_bs_out(net042),
.vccl_aibnd(vccl_aibndaux), .oclkb_aib(net083),
.jtag_clkdr_in(vssl_aibndaux), .jtag_rstb_en(vssl_aibndaux),
.jtag_mode_in(vssl_aibndaux), .jtag_rstb(vssl_aibndaux),
.jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_crdet), .oclkn(net081), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vccl_aibndaux));
aibnd_buffx1_top xtstmx2 ( .idata1_in1_jtag_out(net0285),
.async_dat_in1_jtag_out(net0102), .idata0_in1_jtag_out(net0312),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(net0271),
.jtag_clksel(vssl_aibndaux), .vssl_aibnd(vssl_aibndaux),
.jtag_intest(vssl_aibndaux), .vccl_aibnd(vccl_aibndaux),
.jtag_rstb_en(vssl_aibndaux), .anlg_rstb(anlg_rstb),
.pd_data_aib(net0255), .oclk_out(net0206), .oclkb_out(net0210),
.odat0_out(net0214), .odat1_out(net0218),
.odat_async_out(jtr_tms_int), .pd_data_out(net0222),
.async_dat_in0(vssl_aibndaux), .async_dat_in1(vssl_aibndaux),
.iclkin_dist_in0(vssl_aibndaux), .iclkin_dist_in1(vssl_aibndaux),
.idata0_in0(vssl_aibndaux), .idata0_in1(vssl_aibndaux),
.idata1_in0(vssl_aibndaux), .idata1_in1(vssl_aibndaux),
.idataselb_in0(vssl_aibndaux), .idataselb_in1(vssl_aibndaux),
.iddren_in0(vssl_aibndaux), .iddren_in1(vssl_aibndaux),
.ilaunch_clk_in0(vssl_aibndaux), .ilaunch_clk_in1(vssl_aibndaux),
.ilpbk_dat_in0(vssl_aibndaux), .ilpbk_dat_in1(vssl_aibndaux),
.ilpbk_en_in0(vssl_aibndaux), .ilpbk_en_in1(vssl_aibndaux),
.indrv_in0({vssl_aibndaux, vssl_aibndaux}),
.indrv_in1({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in0({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in1({vssl_aibndaux, vssl_aibndaux}),
.irxen_in0(csr_pred_rxen_int[2:0]),
.irxen_in1(csr_pred_rxen_int[2:0]), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(vssl_aibndaux),
.itxen_in1(vssl_aibndaux), .oclk_in1(vssl_aibndaux),
.odat_async_aib(net0251), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net043), .odat1_aib(net0247),
.jtag_rx_scan_out(net044), .odat0_aib(net0243),
.oclk_aib(net0235), .last_bs_out(net045), .oclkb_aib(net0239),
.jtag_clkdr_in(vssl_aibndaux), .jtag_mode_in(vssl_aibndaux),
.jtag_rstb(vssl_aibndaux), .jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_jtr_tms), .oclkn(net0231), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vssl_aibndaux));
aibnd_buffx1_top xjt_tms ( .idata1_in1_jtag_out(net0324),
.async_dat_in1_jtag_out(net0321), .idata0_in1_jtag_out(net094),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(net0284),
.jtag_clksel(vssl_aibndaux), .vssl_aibnd(vssl_aibndaux),
.jtag_intest(vssl_aibndaux), .vccl_aibnd(vccl_aibndaux),
.jtag_rstb_en(vssl_aibndaux), .anlg_rstb(anlg_rstb),
.pd_data_aib(net0253), .oclk_out(net0204), .oclkb_out(net0208),
.odat0_out(net0212), .odat1_out(net0216),
.odat_async_out(net0199), .pd_data_out(net0220),
.async_dat_in0(jt_tms), .async_dat_in1(vssl_aibndaux),
.iclkin_dist_in0(vssl_aibndaux), .iclkin_dist_in1(vssl_aibndaux),
.idata0_in0(vssl_aibndaux), .idata0_in1(vssl_aibndaux),
.idata1_in0(vssl_aibndaux), .idata1_in1(vssl_aibndaux),
.idataselb_in0(csr_pred_dataselb), .idataselb_in1(vssl_aibndaux),
.iddren_in0(vssl_aibndaux), .iddren_in1(vssl_aibndaux),
.ilaunch_clk_in0(vssl_aibndaux), .ilaunch_clk_in1(vssl_aibndaux),
.ilpbk_dat_in0(vssl_aibndaux), .ilpbk_dat_in1(vssl_aibndaux),
.ilpbk_en_in0(vssl_aibndaux), .ilpbk_en_in1(vssl_aibndaux),
.indrv_in0(csr_pred_ndrv_int[1:0]),
.indrv_in1(csr_pred_ndrv_int[1:0]),
.ipdrv_in0(csr_pred_pdrv_int[1:0]),
.ipdrv_in1(csr_pred_pdrv_int[1:0]), .irxen_in0({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .irxen_in1({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(csr_pred_txen_int),
.itxen_in1(csr_pred_txen_int), .oclk_in1(vssl_aibndaux),
.odat_async_aib(net0249), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net052), .odat1_aib(net0245),
.jtag_rx_scan_out(net053), .odat0_aib(net0241),
.oclk_aib(net0233), .last_bs_out(net054), .oclkb_aib(net0237),
.jtag_clkdr_in(vssl_aibndaux), .jtag_mode_in(vssl_aibndaux),
.jtag_rstb(vssl_aibndaux), .jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_jt_tms), .oclkn(net0229), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vssl_aibndaux));
aibnd_buffx1_top xjt_tdi ( .idata1_in1_jtag_out(net0275),
.async_dat_in1_jtag_out(net0311), .idata0_in1_jtag_out(net0268),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(net0277),
.jtag_clksel(vssl_aibndaux), .vssl_aibnd(vssl_aibndaux),
.jtag_intest(vssl_aibndaux), .vccl_aibnd(vccl_aibndaux),
.jtag_rstb_en(vssl_aibndaux), .anlg_rstb(anlg_rstb),
.pd_data_aib(net0101), .oclk_out(net088), .oclkb_out(net089),
.odat0_out(net090), .odat1_out(net091), .odat_async_out(net092),
.pd_data_out(net093), .async_dat_in0(jt_tdi),
.async_dat_in1(vssl_aibndaux), .iclkin_dist_in0(vssl_aibndaux),
.iclkin_dist_in1(vssl_aibndaux), .idata0_in0(vssl_aibndaux),
.idata0_in1(vssl_aibndaux), .idata1_in0(vssl_aibndaux),
.idata1_in1(vssl_aibndaux), .idataselb_in0(csr_pred_dataselb),
.idataselb_in1(vssl_aibndaux), .iddren_in0(vssl_aibndaux),
.iddren_in1(vssl_aibndaux), .ilaunch_clk_in0(vssl_aibndaux),
.ilaunch_clk_in1(vssl_aibndaux), .ilpbk_dat_in0(vssl_aibndaux),
.ilpbk_dat_in1(vssl_aibndaux), .ilpbk_en_in0(vssl_aibndaux),
.ilpbk_en_in1(vssl_aibndaux), .indrv_in0(csr_pred_ndrv_int[1:0]),
.indrv_in1(csr_pred_ndrv_int[1:0]),
.ipdrv_in0(csr_pred_pdrv_int[1:0]),
.ipdrv_in1(csr_pred_pdrv_int[1:0]), .irxen_in0({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .irxen_in1({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(csr_pred_txen_int),
.itxen_in1(csr_pred_txen_int), .oclk_in1(vssl_aibndaux),
.odat_async_aib(net0100), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net059), .odat1_aib(net099),
.jtag_rx_scan_out(net058), .odat0_aib(net098), .oclk_aib(net096),
.last_bs_out(net060), .oclkb_aib(net097),
.jtag_clkdr_in(vssl_aibndaux), .jtag_mode_in(vssl_aibndaux),
.jtag_rstb(vssl_aibndaux), .jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_jt_tdi), .oclkn(net095), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vssl_aibndaux));
aibnd_buffx1_top xjt_tck ( .idata1_in1_jtag_out(net0317),
.async_dat_in1_jtag_out(net0320), .idata0_in1_jtag_out(net0287),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(net0274),
.jtag_clksel(vssl_aibndaux), .vssl_aibnd(vssl_aibndaux),
.jtag_intest(vssl_aibndaux), .vccl_aibnd(vccl_aibndaux),
.jtag_rstb_en(vssl_aibndaux), .anlg_rstb(anlg_rstb),
.pd_data_aib(net0263), .oclk_out(net0224), .oclkb_out(net0225),
.odat0_out(net0226), .odat1_out(net0227),
.odat_async_out(net0267), .pd_data_out(net0228),
.async_dat_in0(jt_tck), .async_dat_in1(vssl_aibndaux),
.iclkin_dist_in0(vssl_aibndaux), .iclkin_dist_in1(vssl_aibndaux),
.idata0_in0(vssl_aibndaux), .idata0_in1(vssl_aibndaux),
.idata1_in0(vssl_aibndaux), .idata1_in1(vssl_aibndaux),
.idataselb_in0(csr_pred_dataselb), .idataselb_in1(vssl_aibndaux),
.iddren_in0(vssl_aibndaux), .iddren_in1(vssl_aibndaux),
.ilaunch_clk_in0(vssl_aibndaux), .ilaunch_clk_in1(vssl_aibndaux),
.ilpbk_dat_in0(vssl_aibndaux), .ilpbk_dat_in1(vssl_aibndaux),
.ilpbk_en_in0(vssl_aibndaux), .ilpbk_en_in1(vssl_aibndaux),
.indrv_in0(csr_pred_ndrv_int[1:0]),
.indrv_in1(csr_pred_ndrv_int[1:0]),
.ipdrv_in0(csr_pred_pdrv_int[1:0]),
.ipdrv_in1(csr_pred_pdrv_int[1:0]), .irxen_in0({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .irxen_in1({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(csr_pred_txen_int),
.itxen_in1(csr_pred_txen_int), .oclk_in1(vssl_aibndaux),
.odat_async_aib(net0262), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net056), .odat1_aib(net0261),
.jtag_rx_scan_out(net057), .odat0_aib(net0260),
.oclk_aib(net0258), .last_bs_out(net055), .oclkb_aib(net0259),
.jtag_clkdr_in(vssl_aibndaux), .jtag_mode_in(vssl_aibndaux),
.jtag_rstb(vssl_aibndaux), .jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_jt_tck), .oclkn(net0257), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vssl_aibndaux));
aibnd_buffx1_top xdn_por ( .idata1_in1_jtag_out(net0309),
.async_dat_in1_jtag_out(net0283), .idata0_in1_jtag_out(net0313),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(net0264),
.jtag_clksel(vssl_aibndaux), .vssl_aibnd(vssl_aibndaux),
.jtag_intest(vssl_aibndaux), .vccl_aibnd(vccl_aibndaux),
.jtag_rstb_en(vssl_aibndaux), .anlg_rstb(vccl_aibndaux),
.pd_data_aib(net0115), .oclk_out(net0103), .oclkb_out(net0104),
.odat0_out(net0105), .odat1_out(net0106),
.odat_async_out(net0107), .pd_data_out(net0108),
.async_dat_in0(dn_por), .async_dat_in1(vssl_aibndaux),
.iclkin_dist_in0(vssl_aibndaux), .iclkin_dist_in1(vssl_aibndaux),
.idata0_in0(vssl_aibndaux), .idata0_in1(vssl_aibndaux),
.idata1_in0(vssl_aibndaux), .idata1_in1(vssl_aibndaux),
.idataselb_in0(vssl_aibndaux), .idataselb_in1(vssl_aibndaux),
.iddren_in0(vssl_aibndaux), .iddren_in1(vssl_aibndaux),
.ilaunch_clk_in0(vssl_aibndaux), .ilaunch_clk_in1(vssl_aibndaux),
.ilpbk_dat_in0(vssl_aibndaux), .ilpbk_dat_in1(vssl_aibndaux),
.ilpbk_en_in0(vssl_aibndaux), .ilpbk_en_in1(vssl_aibndaux),
.indrv_in0({vccl_aibndaux, vssl_aibndaux}),
.indrv_in1({vccl_aibndaux, vssl_aibndaux}),
.ipdrv_in0({vccl_aibndaux, vssl_aibndaux}),
.ipdrv_in1({vccl_aibndaux, vssl_aibndaux}), .irxen_in0({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .irxen_in1({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(csr_pred_txen_int),
.itxen_in1(csr_pred_txen_int), .oclk_in1(vssl_aibndaux),
.odat_async_aib(net0114), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net061), .odat1_aib(net0113),
.jtag_rx_scan_out(net062), .odat0_aib(net0112),
.oclk_aib(net0110), .last_bs_out(net063), .oclkb_aib(net0111),
.jtag_clkdr_in(vssl_aibndaux), .jtag_mode_in(vssl_aibndaux),
.jtag_rstb(vssl_aibndaux), .jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_dn_por), .oclkn(net0109), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vssl_aibndaux));
aibnd_buffx1_top xdn_rst_n ( .idata1_in1_jtag_out(net0290),
.async_dat_in1_jtag_out(net0280), .idata0_in1_jtag_out(net0307),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(net0278),
.jtag_clksel(vssl_aibndaux), .vssl_aibnd(vssl_aibndaux),
.jtag_intest(vssl_aibndaux), .vccl_aibnd(vccl_aibndaux),
.jtag_rstb_en(vssl_aibndaux), .anlg_rstb(anlg_rstb),
.pd_data_aib(net0130), .oclk_out(net0442), .oclkb_out(net0416),
.odat0_out(net028), .odat1_out(net029), .odat_async_out(net0385),
.pd_data_out(net0402), .async_dat_in0(dn_rst_n),
.async_dat_in1(vssl_aibndaux), .iclkin_dist_in0(vssl_aibndaux),
.iclkin_dist_in1(vssl_aibndaux), .idata0_in0(vssl_aibndaux),
.idata0_in1(vssl_aibndaux), .idata1_in0(vssl_aibndaux),
.idata1_in1(vssl_aibndaux), .idataselb_in0(csr_pred_dataselb),
.idataselb_in1(vssl_aibndaux), .iddren_in0(vssl_aibndaux),
.iddren_in1(vssl_aibndaux), .ilaunch_clk_in0(vssl_aibndaux),
.ilaunch_clk_in1(vssl_aibndaux), .ilpbk_dat_in0(vssl_aibndaux),
.ilpbk_dat_in1(vssl_aibndaux), .ilpbk_en_in0(vssl_aibndaux),
.ilpbk_en_in1(vssl_aibndaux), .indrv_in0(csr_pred_ndrv_int[1:0]),
.indrv_in1(csr_pred_ndrv_int[1:0]),
.ipdrv_in0(csr_pred_pdrv_int[1:0]),
.ipdrv_in1(csr_pred_pdrv_int[1:0]), .irxen_in0({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .irxen_in1({vssl_aibndaux,
vccl_aibndaux, vssl_aibndaux}), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(csr_pred_txen_int),
.itxen_in1(csr_pred_txen_int), .oclk_in1(vssl_aibndaux),
.odat_async_aib(net0129), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net066), .odat1_aib(net0128),
.jtag_rx_scan_out(net065), .odat0_aib(net0127),
.oclk_aib(net0125), .last_bs_out(net064), .oclkb_aib(net0126),
.jtag_clkdr_in(vssl_aibndaux), .jtag_mode_in(vssl_aibndaux),
.jtag_rstb(vssl_aibndaux), .jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_dn_rst_n), .oclkn(net0124), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vssl_aibndaux));
aibnd_buffx1_top xtstmx0 ( .idata1_in1_jtag_out(net0304),
.async_dat_in1_jtag_out(net0323), .idata0_in1_jtag_out(net0322),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(net0276),
.jtag_clksel(vssl_aibndaux), .vssl_aibnd(vssl_aibndaux),
.jtag_intest(vssl_aibndaux), .vccl_aibnd(vccl_aibndaux),
.jtag_rstb_en(vssl_aibndaux), .anlg_rstb(anlg_rstb),
.pd_data_aib(net0254), .oclk_out(net0205), .oclkb_out(net0209),
.odat0_out(net0213), .odat1_out(net0217),
.odat_async_out(jtr_tdo_int), .pd_data_out(net0221),
.async_dat_in0(vssl_aibndaux), .async_dat_in1(vssl_aibndaux),
.iclkin_dist_in0(vssl_aibndaux), .iclkin_dist_in1(vssl_aibndaux),
.idata0_in0(vssl_aibndaux), .idata0_in1(vssl_aibndaux),
.idata1_in0(vssl_aibndaux), .idata1_in1(vssl_aibndaux),
.idataselb_in0(vssl_aibndaux), .idataselb_in1(vssl_aibndaux),
.iddren_in0(vssl_aibndaux), .iddren_in1(vssl_aibndaux),
.ilaunch_clk_in0(vssl_aibndaux), .ilaunch_clk_in1(vssl_aibndaux),
.ilpbk_dat_in0(vssl_aibndaux), .ilpbk_dat_in1(vssl_aibndaux),
.ilpbk_en_in0(vssl_aibndaux), .ilpbk_en_in1(vssl_aibndaux),
.indrv_in0({vssl_aibndaux, vssl_aibndaux}),
.indrv_in1({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in0({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in1({vssl_aibndaux, vssl_aibndaux}),
.irxen_in0(csr_pred_rxen_int[2:0]),
.irxen_in1(csr_pred_rxen_int[2:0]), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(vssl_aibndaux),
.itxen_in1(vssl_aibndaux), .oclk_in1(vssl_aibndaux),
.odat_async_aib(net0250), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net046), .odat1_aib(net0246),
.jtag_rx_scan_out(net047), .odat0_aib(net0242),
.oclk_aib(net0234), .last_bs_out(net048), .oclkb_aib(net0238),
.jtag_clkdr_in(vssl_aibndaux), .jtag_mode_in(vssl_aibndaux),
.jtag_rstb(vssl_aibndaux), .jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_jtr_tdo), .oclkn(net0230), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vssl_aibndaux));
aibnd_buffx1_top xio_oe0 ( .idata1_in1_jtag_out(net0305),
.async_dat_in1_jtag_out(net0292), .idata0_in1_jtag_out(net0318),
.prev_io_shift_en(vssl_aibndaux), .jtag_clkdr_outn(net0281),
.jtag_clksel(vssl_aibndaux), .vssl_aibnd(vssl_aibndaux),
.jtag_intest(vssl_aibndaux), .vccl_aibnd(vccl_aibndaux),
.jtag_rstb_en(vssl_aibndaux), .anlg_rstb(anlg_rstb),
.pd_data_aib(net0256), .oclk_out(net0207), .oclkb_out(net0211),
.odat0_out(net0215), .odat1_out(net0219),
.odat_async_out(jtr_tck_int), .pd_data_out(net0223),
.async_dat_in0(vssl_aibndaux), .async_dat_in1(vssl_aibndaux),
.iclkin_dist_in0(vssl_aibndaux), .iclkin_dist_in1(vssl_aibndaux),
.idata0_in0(vssl_aibndaux), .idata0_in1(vssl_aibndaux),
.idata1_in0(vssl_aibndaux), .idata1_in1(vssl_aibndaux),
.idataselb_in0(vssl_aibndaux), .idataselb_in1(vssl_aibndaux),
.iddren_in0(vssl_aibndaux), .iddren_in1(vssl_aibndaux),
.ilaunch_clk_in0(vssl_aibndaux), .ilaunch_clk_in1(vssl_aibndaux),
.ilpbk_dat_in0(vssl_aibndaux), .ilpbk_dat_in1(vssl_aibndaux),
.ilpbk_en_in0(vssl_aibndaux), .ilpbk_en_in1(vssl_aibndaux),
.indrv_in0({vssl_aibndaux, vssl_aibndaux}),
.indrv_in1({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in0({vssl_aibndaux, vssl_aibndaux}),
.ipdrv_in1({vssl_aibndaux, vssl_aibndaux}),
.irxen_in0(csr_pred_rxen_int[2:0]),
.irxen_in1(csr_pred_rxen_int[2:0]), .istrbclk_in0(vssl_aibndaux),
.istrbclk_in1(vssl_aibndaux), .itxen_in0(vssl_aibndaux),
.itxen_in1(vssl_aibndaux), .oclk_in1(vssl_aibndaux),
.odat_async_aib(net0252), .oclkb_in1(vssl_aibndaux),
.odat0_in1(vssl_aibndaux), .odat1_in1(vssl_aibndaux),
.odat_async_in1(vssl_aibndaux), .shift_en(vssl_aibndaux),
.pd_data_in1(vssl_aibndaux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net051), .odat1_aib(net0248),
.jtag_rx_scan_out(net050), .odat0_aib(net0244),
.oclk_aib(net0236), .last_bs_out(net049), .oclkb_aib(net0240),
.jtag_clkdr_in(vssl_aibndaux), .jtag_mode_in(vssl_aibndaux),
.jtag_rstb(vssl_aibndaux), .jtag_tx_scan_in(vssl_aibndaux),
.jtag_tx_scanen_in(vssl_aibndaux), .last_bs_in(vssl_aibndaux),
.iopad(iopad_jtr_tck), .oclkn(net0232), .iclkn(vssl_aibndaux),
.test_weakpu(vssl_aibndaux), .test_weakpd(vssl_aibndaux));
assign jtr_tck = crete_detect ? jtr_tck_int : jt_tck;
assign jtr_tms = crete_detect ? jtr_tms_int : jt_tms;
assign jtr_tdo = crete_detect ? jtr_tdo_int : jt_tdi;
assign csr_pred_ndrv_int[1:0] = csr_iocsr_sel ? csr_pred_ndrv[1:0] : {vccl_aibndaux, vssl_aibndaux};
assign csr_pred_pdrv_int[1:0] = csr_iocsr_sel ? csr_pred_pdrv[1:0] : {vccl_aibndaux, vssl_aibndaux};
assign csr_pred_rxen_int[2:0] = csr_iocsr_sel ? csr_pred_rxen[2:0] : vssl_aibndaux;
assign csr_pred_txen_int = csr_iocsr_sel ? csr_pred_txen : crete_detect;
endmodule |
module aib_dlycell_dll_comb_inv_1__w_sup(
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in );
endmodule |
module aib_dlycell_dll_comb_nand_1__w_sup(
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in );
endmodule |
module aib_dlycell_dll_comb_aib_dlycell_core_1__w_sup(
input wire bk1,
input wire ci_p,
input wire in_p,
output wire co_p,
output wire out_p,
inout wire VDD,
inout wire VSS
);
wire sr0_o;
wire sr1_o;
aib_dlycell_dll_comb_nand_1__w_sup XNAND_SR0 (
.in( {sr1_o,bk1} ),
.out( sr0_o ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dll_comb_nand_1__w_sup XNAND_SR1 (
.in( {sr0_o,in_p} ),
.out( sr1_o ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dll_comb_nand_1__w_sup XNAND_in (
.in( {bk1,in_p} ),
.out( co_p ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dll_comb_nand_1__w_sup XNAND_out (
.in( {sr1_o,ci_p} ),
.out( out_p ),
.VDD( VDD ),
.VSS( VSS )
);
endmodule |
module aibcr3_dlycell_dll_comb__w_sup(
input wire bk,
input wire ci_p,
input wire in_p,
output wire co_p,
output wire out_p,
inout wire VDD,
inout wire VSS
);
wire bk1;
wire bk_mid;
wire mid_in;
wire mid_out;
aib_dlycell_dll_comb_inv_1__w_sup XBKInv0 (
.in( bk ),
.out( bk_mid ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dll_comb_inv_1__w_sup XBKInv1 (
.in( bk_mid ),
.out( bk1 ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dll_comb_aib_dlycell_core_1__w_sup XCore_1 (
.bk1( bk1 ),
.ci_p( mid_out ),
.in_p( in_p ),
.co_p( mid_in ),
.out_p( out_p ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dll_comb_aib_dlycell_core_1__w_sup XCore_0 (
.bk1( bk1 ),
.ci_p( ci_p ),
.in_p( mid_in ),
.co_p( co_p ),
.out_p( mid_out ),
.VDD( VDD ),
.VSS( VSS )
);
endmodule |
module aibcr3_dlycell_dll_comb(
input wire bk,
input wire ci_p,
input wire in_p,
output wire co_p,
output wire out_p
);
wire VDD_val;
wire VSS_val;
wire out_p_int;
assign VDD_val = 1'b1;
assign VSS_val = 1'b0;
aibcr3_dlycell_dll_comb__w_sup XDUT (
.bk( bk ),
.ci_p( ci_p ),
.in_p( in_p ),
.co_p( co_p ),
.out_p( out_p_int ),
.VDD( VDD_val ),
.VSS( VSS_val )
);
// from tttt_25_0p850_0p970
assign #(20, 24) out_p = out_p_int;
endmodule |
module aib_dcc_dlyline64_inv_1__w_sup(
input wire in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~in );
endmodule |
module aib_dcc_dlyline64_nand_2__w_sup(
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 20;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in );
endmodule |
module aib_dcc_dlyline64_aib_dlycell_core_1__w_sup(
input wire bk1,
input wire ci_p,
input wire in_p,
output wire co_p,
output wire out_p,
inout wire VDD,
inout wire VSS
);
wire sr0_o;
wire sr1_o;
aib_dcc_dlyline64_nand_2__w_sup XNAND_SR0 (
.in( {sr1_o,bk1} ),
.out( sr0_o ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_nand_2__w_sup XNAND_SR1 (
.in( {sr0_o,in_p} ),
.out( sr1_o ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_nand_3__w_sup XNAND_in (
.in( {bk1,in_p} ),
.out( co_p ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_nand_3__w_sup XNAND_out (
.in( {sr1_o,ci_p} ),
.out( out_p ),
.VDD( VDD ),
.VSS( VSS )
);
endmodule |
module aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup(
input wire bk,
input wire ci_p,
input wire in_p,
output wire co_p,
output wire out_p,
inout wire VDD,
inout wire VSS
);
wire bk1;
wire bk_mid;
aib_dcc_dlyline64_inv_1__w_sup XBKInv0 (
.in( bk ),
.out( bk_mid ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_inv_1__w_sup XBKInv1 (
.in( bk_mid ),
.out( bk1 ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_core_1__w_sup XCore (
.bk1( bk1 ),
.ci_p( ci_p ),
.in_p( in_p ),
.co_p( co_p ),
.out_p( out_p ),
.VDD( VDD ),
.VSS( VSS )
);
endmodule |
module aibcr3_dcc_dlyline64__w_sup(
input wire b63,
input wire [63:0] bk,
input wire dlyin,
output wire a63,
output wire dlyout,
inout wire VDD,
inout wire VSS
);
wire NC_co;
wire NC_out;
wire NC_so;
wire [62:0] a;
wire [62:0] b;
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_63 (
.bk( bk[63] ),
.ci_p( b63 ),
.in_p( a[62] ),
.co_p( a63 ),
.out_p( b[62] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_62 (
.bk( bk[62] ),
.ci_p( b[62] ),
.in_p( a[61] ),
.co_p( a[62] ),
.out_p( b[61] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_61 (
.bk( bk[61] ),
.ci_p( b[61] ),
.in_p( a[60] ),
.co_p( a[61] ),
.out_p( b[60] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_60 (
.bk( bk[60] ),
.ci_p( b[60] ),
.in_p( a[59] ),
.co_p( a[60] ),
.out_p( b[59] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_59 (
.bk( bk[59] ),
.ci_p( b[59] ),
.in_p( a[58] ),
.co_p( a[59] ),
.out_p( b[58] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_58 (
.bk( bk[58] ),
.ci_p( b[58] ),
.in_p( a[57] ),
.co_p( a[58] ),
.out_p( b[57] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_57 (
.bk( bk[57] ),
.ci_p( b[57] ),
.in_p( a[56] ),
.co_p( a[57] ),
.out_p( b[56] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_56 (
.bk( bk[56] ),
.ci_p( b[56] ),
.in_p( a[55] ),
.co_p( a[56] ),
.out_p( b[55] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_55 (
.bk( bk[55] ),
.ci_p( b[55] ),
.in_p( a[54] ),
.co_p( a[55] ),
.out_p( b[54] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_54 (
.bk( bk[54] ),
.ci_p( b[54] ),
.in_p( a[53] ),
.co_p( a[54] ),
.out_p( b[53] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_53 (
.bk( bk[53] ),
.ci_p( b[53] ),
.in_p( a[52] ),
.co_p( a[53] ),
.out_p( b[52] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_52 (
.bk( bk[52] ),
.ci_p( b[52] ),
.in_p( a[51] ),
.co_p( a[52] ),
.out_p( b[51] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_51 (
.bk( bk[51] ),
.ci_p( b[51] ),
.in_p( a[50] ),
.co_p( a[51] ),
.out_p( b[50] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_50 (
.bk( bk[50] ),
.ci_p( b[50] ),
.in_p( a[49] ),
.co_p( a[50] ),
.out_p( b[49] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_49 (
.bk( bk[49] ),
.ci_p( b[49] ),
.in_p( a[48] ),
.co_p( a[49] ),
.out_p( b[48] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_48 (
.bk( bk[48] ),
.ci_p( b[48] ),
.in_p( a[47] ),
.co_p( a[48] ),
.out_p( b[47] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_47 (
.bk( bk[47] ),
.ci_p( b[47] ),
.in_p( a[46] ),
.co_p( a[47] ),
.out_p( b[46] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_46 (
.bk( bk[46] ),
.ci_p( b[46] ),
.in_p( a[45] ),
.co_p( a[46] ),
.out_p( b[45] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_45 (
.bk( bk[45] ),
.ci_p( b[45] ),
.in_p( a[44] ),
.co_p( a[45] ),
.out_p( b[44] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_44 (
.bk( bk[44] ),
.ci_p( b[44] ),
.in_p( a[43] ),
.co_p( a[44] ),
.out_p( b[43] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_43 (
.bk( bk[43] ),
.ci_p( b[43] ),
.in_p( a[42] ),
.co_p( a[43] ),
.out_p( b[42] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_42 (
.bk( bk[42] ),
.ci_p( b[42] ),
.in_p( a[41] ),
.co_p( a[42] ),
.out_p( b[41] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_41 (
.bk( bk[41] ),
.ci_p( b[41] ),
.in_p( a[40] ),
.co_p( a[41] ),
.out_p( b[40] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_40 (
.bk( bk[40] ),
.ci_p( b[40] ),
.in_p( a[39] ),
.co_p( a[40] ),
.out_p( b[39] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_39 (
.bk( bk[39] ),
.ci_p( b[39] ),
.in_p( a[38] ),
.co_p( a[39] ),
.out_p( b[38] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_38 (
.bk( bk[38] ),
.ci_p( b[38] ),
.in_p( a[37] ),
.co_p( a[38] ),
.out_p( b[37] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_37 (
.bk( bk[37] ),
.ci_p( b[37] ),
.in_p( a[36] ),
.co_p( a[37] ),
.out_p( b[36] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_36 (
.bk( bk[36] ),
.ci_p( b[36] ),
.in_p( a[35] ),
.co_p( a[36] ),
.out_p( b[35] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_35 (
.bk( bk[35] ),
.ci_p( b[35] ),
.in_p( a[34] ),
.co_p( a[35] ),
.out_p( b[34] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_34 (
.bk( bk[34] ),
.ci_p( b[34] ),
.in_p( a[33] ),
.co_p( a[34] ),
.out_p( b[33] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_33 (
.bk( bk[33] ),
.ci_p( b[33] ),
.in_p( a[32] ),
.co_p( a[33] ),
.out_p( b[32] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_32 (
.bk( bk[32] ),
.ci_p( b[32] ),
.in_p( a[31] ),
.co_p( a[32] ),
.out_p( b[31] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_31 (
.bk( bk[31] ),
.ci_p( b[31] ),
.in_p( a[30] ),
.co_p( a[31] ),
.out_p( b[30] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_30 (
.bk( bk[30] ),
.ci_p( b[30] ),
.in_p( a[29] ),
.co_p( a[30] ),
.out_p( b[29] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_29 (
.bk( bk[29] ),
.ci_p( b[29] ),
.in_p( a[28] ),
.co_p( a[29] ),
.out_p( b[28] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_28 (
.bk( bk[28] ),
.ci_p( b[28] ),
.in_p( a[27] ),
.co_p( a[28] ),
.out_p( b[27] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_27 (
.bk( bk[27] ),
.ci_p( b[27] ),
.in_p( a[26] ),
.co_p( a[27] ),
.out_p( b[26] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_26 (
.bk( bk[26] ),
.ci_p( b[26] ),
.in_p( a[25] ),
.co_p( a[26] ),
.out_p( b[25] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_25 (
.bk( bk[25] ),
.ci_p( b[25] ),
.in_p( a[24] ),
.co_p( a[25] ),
.out_p( b[24] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_24 (
.bk( bk[24] ),
.ci_p( b[24] ),
.in_p( a[23] ),
.co_p( a[24] ),
.out_p( b[23] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_23 (
.bk( bk[23] ),
.ci_p( b[23] ),
.in_p( a[22] ),
.co_p( a[23] ),
.out_p( b[22] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_22 (
.bk( bk[22] ),
.ci_p( b[22] ),
.in_p( a[21] ),
.co_p( a[22] ),
.out_p( b[21] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_21 (
.bk( bk[21] ),
.ci_p( b[21] ),
.in_p( a[20] ),
.co_p( a[21] ),
.out_p( b[20] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_20 (
.bk( bk[20] ),
.ci_p( b[20] ),
.in_p( a[19] ),
.co_p( a[20] ),
.out_p( b[19] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_19 (
.bk( bk[19] ),
.ci_p( b[19] ),
.in_p( a[18] ),
.co_p( a[19] ),
.out_p( b[18] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_18 (
.bk( bk[18] ),
.ci_p( b[18] ),
.in_p( a[17] ),
.co_p( a[18] ),
.out_p( b[17] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_17 (
.bk( bk[17] ),
.ci_p( b[17] ),
.in_p( a[16] ),
.co_p( a[17] ),
.out_p( b[16] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_16 (
.bk( bk[16] ),
.ci_p( b[16] ),
.in_p( a[15] ),
.co_p( a[16] ),
.out_p( b[15] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_15 (
.bk( bk[15] ),
.ci_p( b[15] ),
.in_p( a[14] ),
.co_p( a[15] ),
.out_p( b[14] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_14 (
.bk( bk[14] ),
.ci_p( b[14] ),
.in_p( a[13] ),
.co_p( a[14] ),
.out_p( b[13] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_13 (
.bk( bk[13] ),
.ci_p( b[13] ),
.in_p( a[12] ),
.co_p( a[13] ),
.out_p( b[12] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_12 (
.bk( bk[12] ),
.ci_p( b[12] ),
.in_p( a[11] ),
.co_p( a[12] ),
.out_p( b[11] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_11 (
.bk( bk[11] ),
.ci_p( b[11] ),
.in_p( a[10] ),
.co_p( a[11] ),
.out_p( b[10] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_10 (
.bk( bk[10] ),
.ci_p( b[10] ),
.in_p( a[9] ),
.co_p( a[10] ),
.out_p( b[9] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_9 (
.bk( bk[9] ),
.ci_p( b[9] ),
.in_p( a[8] ),
.co_p( a[9] ),
.out_p( b[8] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_8 (
.bk( bk[8] ),
.ci_p( b[8] ),
.in_p( a[7] ),
.co_p( a[8] ),
.out_p( b[7] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_7 (
.bk( bk[7] ),
.ci_p( b[7] ),
.in_p( a[6] ),
.co_p( a[7] ),
.out_p( b[6] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_6 (
.bk( bk[6] ),
.ci_p( b[6] ),
.in_p( a[5] ),
.co_p( a[6] ),
.out_p( b[5] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_5 (
.bk( bk[5] ),
.ci_p( b[5] ),
.in_p( a[4] ),
.co_p( a[5] ),
.out_p( b[4] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_4 (
.bk( bk[4] ),
.ci_p( b[4] ),
.in_p( a[3] ),
.co_p( a[4] ),
.out_p( b[3] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_3 (
.bk( bk[3] ),
.ci_p( b[3] ),
.in_p( a[2] ),
.co_p( a[3] ),
.out_p( b[2] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_2 (
.bk( bk[2] ),
.ci_p( b[2] ),
.in_p( a[1] ),
.co_p( a[2] ),
.out_p( b[1] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_1 (
.bk( bk[1] ),
.ci_p( b[1] ),
.in_p( a[0] ),
.co_p( a[1] ),
.out_p( b[0] ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_2__w_sup XCELL_0 (
.bk( bk[0] ),
.ci_p( b[0] ),
.in_p( dlyin ),
.co_p( a[0] ),
.out_p( dlyout ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dcc_dlyline64_aib_dlycell_no_flop_3__w_sup XDUM (
.bk( VSS ),
.ci_p( VSS ),
.in_p( VSS ),
.co_p( NC_co ),
.out_p( NC_out ),
.VDD( VDD ),
.VSS( VSS )
);
endmodule |
module aibcr3_dcc_dlyline64(
input wire b63,
input wire [63:0] bk,
input wire dlyin,
output wire a63,
output wire dlyout
);
wire VDD_val;
wire VSS_val;
assign VDD_val = 1'b1;
assign VSS_val = 1'b0;
aibcr3_dcc_dlyline64__w_sup XDUT (
.b63( b63 ),
.bk( bk ),
.dlyin( dlyin ),
.a63( a63 ),
.dlyout( dlyout ),
.VDD( VDD_val ),
.VSS( VSS_val )
);
endmodule |
Subsets and Splits