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module aib_dlycell_dcc_nand_2__w_sup(
input wire [1:0] in,
output wire out,
inout wire VDD,
inout wire VSS
);
parameter DELAY = 0;
assign #DELAY out = VSS ? 1'bx : (~VDD ? 1'b0 : ~&in );
endmodule |
module aib_dlycell_dcc_aib_dlycell_core_1__w_sup(
input wire bk1,
input wire ci_p,
input wire in_p,
output wire co_p,
output wire out_p,
inout wire VDD,
inout wire VSS
);
wire sr0_o;
wire sr1_o;
aib_dlycell_dcc_nand_2__w_sup XNAND_SR0 (
.in( {sr1_o,bk1} ),
.out( sr0_o ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dcc_nand_2__w_sup XNAND_SR1 (
.in( {sr0_o,in_p} ),
.out( sr1_o ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dcc_nand_3__w_sup XNAND_in (
.in( {bk1,in_p} ),
.out( co_p ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dcc_nand_3__w_sup XNAND_out (
.in( {sr1_o,ci_p} ),
.out( out_p ),
.VDD( VDD ),
.VSS( VSS )
);
endmodule |
module aibcr3_dlycell_dcc__w_sup(
input wire bk,
input wire ci_p,
input wire in_p,
output wire co_p,
output wire out_p,
inout wire VDD,
inout wire VSS
);
wire bk1;
wire bk_mid;
aib_dlycell_dcc_inv_1__w_sup XBKInv0 (
.in( bk ),
.out( bk_mid ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dcc_inv_1__w_sup XBKInv1 (
.in( bk_mid ),
.out( bk1 ),
.VDD( VDD ),
.VSS( VSS )
);
aib_dlycell_dcc_aib_dlycell_core_1__w_sup XCore (
.bk1( bk1 ),
.ci_p( ci_p ),
.in_p( in_p ),
.co_p( co_p ),
.out_p( out_p ),
.VDD( VDD ),
.VSS( VSS )
);
endmodule |
module aibcr3_dcc_phasedet_single (
output wire t_down,
output wire t_up,
input wire CLKA,
input wire CLKB,
input wire RSTb
);
aibcr3_dcc_phasedet phasedet (
.t_down (),
.t_up (t_up),
.CLKA (CLKA),
.CLKB (CLKB),
.RSTb (RSTb)
);
assign t_down = !t_up;
endmodule |
module aibcr3_latch (
input wire E,
input wire CDN,
input wire D,
output reg Q
);
wire latch_reset;
assign latch_reset = !CDN;
//cadence async_set_reset "latch_reset"
//synopsys async_set_reset "latch_reset"
always@(*) begin
if (latch_reset) Q <= 0;
else if (E) Q <= D;
end
endmodule |
module aibcr3_txdig ( indrv_buf, ipdrv_buf, itx_en_buf, tx_dat_out,
weak_pulldownen, weak_pullupenb, async_data, clkdr,
idat0, idat1, idataselb, iddrctrl, ilaunch_clk, ilpbk_dat,
ilpbk_en, indrv, ipadrstb, ipdrv, irstb, itx_en, rx_enb,
test_weakpd, test_weakpu, testmode_en );
output wire itx_en_buf, tx_dat_out, weak_pulldownen, weak_pullupenb;
input wire async_data, clkdr, idat0, idat1, idataselb, iddrctrl,
ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb, itx_en, rx_enb,
test_weakpd, test_weakpu, testmode_en;
output wire [1:0] indrv_buf;
output wire [1:0] ipdrv_buf;
input wire [1:0] indrv;
input wire [1:0] ipdrv;
wire mux_din;
wire net036;
wire itx_enb;
wire ff1_dout;
wire ff0_dout;
wire clk;
wire ff1_latch_dout_buf2;
wire ff0_dout_buf2;
wire async_dat_buf;
wire ipadrstb_buf;
wire weak_pulld_enb;
wire test_weakpu_buf;
wire test_weakpd_buf;
wire ff1_latch_buf1;
wire ff1_latch_dout;
wire anlg_rst_nd_out;
wire io_disable_b;
// Missing wire declarations
wire mux_out;
wire txenb_rxenb;
wire ff1_hold_buf0;
wire ff1_hold_buf1;
wire ff0_hold_buf1;
wire ff0_dout_buf1;
wire irstb_buf;
wire din0;
wire din1;
wire clkb;
wire ff1_latch_input;
assign txenb_rxenb = ~net036;
assign itx_en_buf = ~itx_enb;
assign ff1_hold_buf0 = iddrctrl ? ff1_dout : ff0_dout;
//assign mux_din = idataselb ? mux_out : async_dat_buf;
assign net036 = ~(rx_enb & itx_enb);
assign weak_pulldownen = ~(ipadrstb_buf & weak_pulld_enb);
assign weak_pullupenb = ~ (ipadrstb_buf & test_weakpu_buf);
assign itx_enb = ~(itx_en & ipadrstb);
assign weak_pulld_enb = ~(test_weakpd_buf | txenb_rxenb);
assign test_weakpu_buf = test_weakpu;
assign test_weakpd_buf = test_weakpd;
assign ipadrstb_buf = ipadrstb;
assign ipdrv_buf[1] = ipdrv[1];
assign ipdrv_buf[0] = ipdrv[0];
assign indrv_buf[1] = indrv[1];
assign indrv_buf[0] = indrv[0];
assign ff1_hold_buf1 = ff1_hold_buf0;
assign ff0_dout_buf1 = ff0_dout;
assign ff0_dout_buf2 = ff0_dout_buf1;
assign irstb_buf = irstb;
assign async_dat_buf = async_data;
assign tx_dat_out = mux_din;
assign din0 = idat0;
assign din1 = idat1;
assign clkb = ~clk;
assign clk = ilaunch_clk;
assign ff1_latch_dout_buf2 = ff1_latch_buf1;
assign ff1_latch_buf1 = ff1_latch_dout;
assign ff1_latch_input = ff1_hold_buf1;
/* replaced by latch
aibcr3_ulvt16_dffcdn_cust x29 ( ff1_latch_dout, irstb_buf,
clkb, ff1_latch_input);
*/
aibcr3_latch x29 (.Q(ff1_latch_dout), .E(clkb), .CDN(irstb_buf), .D(ff1_latch_input));
aibcr3_ulvt16_dffcdn_cust x25 ( .Q(ff1_dout), .CDN(irstb_buf), .CK(clk),
.D(din1));
aibcr3_ulvt16_dffcdn_cust x18 ( .Q(ff0_dout), .CDN(irstb_buf), .CK(clk),
.D(din0));
aibcr3_bypmux bypmux(
.out (mux_din),
.byp (idataselb),
.in1 (mux_out),
.in0 (async_dat_buf));
aibcr3_ddrmux ddrmux(
.out (mux_out),
.clk (clk),
.in0 (ff0_dout_buf2),
.in1 (ff1_latch_dout_buf2));
endmodule |
module aib_aux_dual
(
// AIB IO Bidirectional
inout wire device_detect, //Shrink aux74/75 due to limit microbump/C4 bump pin
inout wire por, //Shrink aux85/87 pin due to limit microbump/C4 bump pin
input i_osc_clk,
input m_i_por_ovrd, //Master onlhy input, it overrides the por signal. For slave, it is tied to "0"
input m_i_device_detect_ovrd, //Slave only input, it overrides the device_detect signal. For Master, it is tied to "0"
output wire m_o_power_on_reset,
output wire m_o_device_detect,
output wire o_por_vcchssi,
output wire o_por_vccl,
output wire osc_clkout,
input m_i_power_on_reset,
input ms_nsl //"1", this is a Master. "0", this is a Slave
);
wire device_detect_async_data_in = 1'b0;
wire device_detect_async_data_out;
wire device_detect_txen = 1'b0; //itxen 0: TX buffer 1: RX buffer
wire [2:0] device_detect_rxen = 3'b000; //000 is rx buffer receiving enable
wire device_detect_tx_sync_enable = 1'b0; //idataselb_in0 0: async 1: sync
wire device_detect_ddren = 1'b0; //0: SDR 1: DDR pin
wire device_detect_weakpu = 1'b0; //1: weak pull up 0: disable weak pull up
wire device_detect_weakpd = 1'b1; //1: weak pull down 0: disable weak pull down
wire por_async_data_in = m_i_power_on_reset; //Async data in
wire por_async_data_out; //Async data out
wire por_txen = 1'b1; //itxen 0: TX buffer 1: RX buffer
wire [2:0] por_rxen = 3'b010; //000 is rx buffer receiving disable
wire por_tx_sync_enable = 1'b0;
wire por_ddren = 1'b0;
wire por_weakpu = 1'b1;
wire por_weakpd = 1'b0;
assign m_o_device_detect = device_detect_async_data_out | m_i_device_detect_ovrd;
assign o_por_vcchssi = m_i_power_on_reset;
assign o_por_vccl = 1'b0;
assign osc_clkout = i_osc_clk;
wire v_hi = 1'b1;
wire v_lo = 1'b0;
aibcr3_buffx1_top xdevice_detect ( .idata1_in1_jtag_out(),
.idata0_in1_jtag_out(), .async_dat_in1_jtag_out(),
.prev_io_shift_en(v_lo), .jtag_clkdr_outn(),
.por_aib_vccl(v_lo), .por_aib_vcchssi(v_lo),
.anlg_rstb(v_hi), .pd_data_aib(), .oclk_out(),
.oclkb_out(), .odat0_out(), .odat1_out(),
.odat_async_out(), .pd_data_out(),
.async_dat_in0(device_detect_async_data_in), .async_dat_in1(v_lo),
.iclkin_dist_in0(v_lo), .iclkin_dist_in1(v_lo),
.idata0_in0(v_lo), .idata0_in1(v_lo),
.idata1_in0(v_lo), .idata1_in1(v_lo),
.idataselb_in0(device_detect_tx_sync_enable), .idataselb_in1(v_lo),
.iddren_in0(device_detect_ddren), .iddren_in1(v_lo),
.ilaunch_clk_in0(v_lo), .ilaunch_clk_in1(v_lo),
.ilpbk_dat_in0(v_lo), .ilpbk_dat_in1(v_lo),
.ilpbk_en_in0(v_lo), .ilpbk_en_in1(v_lo),
.indrv_in0({v_lo,v_lo}), .indrv_in1({v_lo,
v_lo}), .ipdrv_in0({v_lo,v_lo}),
.ipdrv_in1({v_lo, v_lo}),
.irxen_in0(device_detect_rxen),
.irxen_in1(device_detect_rxen),
.istrbclk_in0(v_lo), .istrbclk_in1(v_lo),
.itxen_in0(device_detect_txen), .itxen_in1(v_lo),
.oclk_in1(v_lo), .odat_async_aib(device_detect_async_data_out),
.oclkb_in1(v_lo), .jtag_clksel(v_lo),
.odat0_in1(v_lo), .odat1_in1(v_lo),
.odat_async_in1(v_lo), .shift_en(v_lo),
.pd_data_in1(v_lo), .dig_rstb(v_hi),
.jtag_clkdr_out(), .jtag_intest(v_lo),
.odat1_aib(), .jtag_rx_scan_out(), .odat0_aib(),
.oclk_aib(), .last_bs_out(), .oclkb_aib(),
.jtag_clkdr_in(v_lo), .jtag_rstb_en(v_lo),
.jtag_mode_in(v_lo), .jtag_rstb(v_lo),
.jtag_tx_scan_in(v_lo),
.jtag_tx_scanen_in(v_lo), .last_bs_in(v_lo),
.iopad(device_detect), .oclkn(), .iclkn(v_lo),
.test_weakpu(device_detect_weakpu), .test_weakpd(device_detect_weakpd));
aibcr3_buffx1_top xdn_por ( .idata1_in1_jtag_out(),
.idata0_in1_jtag_out(), .async_dat_in1_jtag_out(),
.prev_io_shift_en(v_lo), .jtag_clkdr_outn(),
.por_aib_vccl(v_lo), .por_aib_vcchssi(v_lo),
.jtag_clksel(v_lo), .jtag_intest(v_lo),
.jtag_rstb_en(v_lo), .anlg_rstb(v_hi),
.pd_data_aib(), .oclk_out(), .oclkb_out(),
.odat0_out(), .odat1_out(), .odat_async_out(),
.pd_data_out(), .async_dat_in0(por_async_data_in),
.async_dat_in1(v_lo), .iclkin_dist_in0(v_lo),
.iclkin_dist_in1(v_lo), .idata0_in0(v_lo),
.idata0_in1(v_lo), .idata1_in0(v_lo),
.idata1_in1(v_lo), .idataselb_in0(por_tx_sync_enable),
.idataselb_in1(v_lo), .iddren_in0(por_ddren),
.iddren_in1(v_lo), .ilaunch_clk_in0(v_lo),
.ilaunch_clk_in1(v_lo), .ilpbk_dat_in0(v_lo),
.ilpbk_dat_in1(v_lo), .ilpbk_en_in0(v_lo),
.ilpbk_en_in1(v_lo), .indrv_in0({v_lo,
v_lo}), .indrv_in1({v_lo, v_lo}),
.ipdrv_in0({v_lo, v_lo}),
.ipdrv_in1({v_lo, v_lo}),
.irxen_in0(por_rxen), .irxen_in1({v_lo,
v_lo, v_lo}), .istrbclk_in0(v_lo),
.istrbclk_in1(v_lo), .itxen_in0(por_txen),
.itxen_in1(v_lo), .oclk_in1(v_lo),
.odat_async_aib(por_async_data_out), .oclkb_in1(v_lo),
.odat0_in1(v_lo), .odat1_in1(v_lo),
.odat_async_in1(v_lo), .shift_en(v_lo),
.pd_data_in1(v_lo), .dig_rstb(v_hi),
.jtag_clkdr_out(), .odat1_aib(),
.jtag_rx_scan_out(), .odat0_aib(),
.oclk_aib(), .last_bs_out(), .oclkb_aib(),
.jtag_clkdr_in(v_lo), .jtag_mode_in(v_lo),
.jtag_rstb(v_lo), .jtag_tx_scan_in(v_lo),
.jtag_tx_scanen_in(v_lo), .last_bs_in(v_lo),
.iopad(por), .oclkn(), .iclkn(v_lo),
.test_weakpu(por_weakpu), .test_weakpd(por_weakpd));
endmodule // aib_aux_dual |
module aibcr3aux_pasred_baldwin
(
dn_por,
iopad_crdet,
iopad_dn_por,
vccl_aibcr3aux,
vssl_aibcr3aux );
output dn_por;
inout iopad_crdet,
iopad_dn_por;
input vccl_aibcr3aux,
vssl_aibcr3aux;
wire csr_iocsr_sel, vssl_aibcr3aux, vcc_aibcr3aux, csr_pred_txen_int, csr_pred_txen;
// Buses in the design
wire [1:0] csr_pred_pdrv_int;
wire [2:0] csr_pred_rxen_int;
wire [1:0] csr_pred_ndrv_int;
wire net0266;
wire net087;
wire net075;
wire net076;
wire net077;
wire net078;
wire net0276;
wire net080;
wire net086;
wire net051;
wire net085;
wire net052;
wire net084;
wire net082;
wire net050;
wire net083;
wire net081;
wire net0291;
wire net0255;
wire net0206;
wire net0210;
wire net0214;
wire net0218;
wire net0183;
wire net0222;
wire net0251;
wire net054;
wire net0247;
wire net053;
wire net0243;
wire net0235;
wire net055;
wire net0239;
wire net0231;
wire net0283;
wire net0253;
wire net0204;
wire net0208;
wire net0212;
wire net0216;
wire net0220;
wire net0249;
wire net062;
wire net0245;
wire net063;
wire net0241;
wire net0233;
wire net064;
wire net0237;
wire net0229;
wire net0282;
wire net0101;
wire net088;
wire net089;
wire net090;
wire net091;
wire net093;
wire net0100;
wire net068;
wire net099;
wire net070;
wire net098;
wire net096;
wire net069;
wire net097;
wire net095;
wire net0277;
wire net0263;
wire net0224;
wire net0225;
wire net0226;
wire net0227;
wire net0228;
wire net0262;
wire net067;
wire net0261;
wire net065;
wire net0260;
wire net0258;
wire net066;
wire net0259;
wire net0257;
wire net0285;
wire net0115;
wire net0103;
wire net0104;
wire net0105;
wire net0106;
wire net0108;
wire net0114;
wire net073;
wire net0113;
wire net071;
wire net0112;
wire net0110;
wire net072;
wire net0111;
wire net0109;
wire net0288;
wire net0130;
wire net0442;
wire net0416;
wire net028;
wire net029;
wire net0402;
wire net0129;
wire net0267;
wire net0128;
wire net0265;
wire net0127;
wire net0125;
wire net074;
wire net0126;
wire net0124;
wire net0281;
wire net0254;
wire net0205;
wire net0209;
wire net0213;
wire net0217;
wire net0184;
wire net0221;
wire net0250;
wire net056;
wire net0246;
wire net057;
wire net0242;
wire net0234;
wire net058;
wire net0238;
wire net0230;
wire net0286;
wire net0256;
wire net0207;
wire net0211;
wire net0215;
wire net0219;
wire net0185;
wire net0223;
wire net0252;
wire net061;
wire net0248;
wire net060;
wire net0244;
wire net0236;
wire net059;
wire net0240;
wire net0232;
wire net0307;
wire net0334;
wire net0336;
wire net0123;
wire net0122;
wire net0284;
wire net0314;
wire net0299;
wire net0312;
wire net0305;
wire net0320;
wire net0107;
wire net0327;
wire net0278;
wire net0333;
wire net0325;
wire net0297;
wire net0290;
wire net0102;
wire net0323;
wire net0335;
wire net0120;
wire net0121;
wire net0119;
wire net0117;
wire net0116;
wire net0118;
// specify
// specparam CDS_LIBNAME = "aibcr3aux_lib";
// specparam CDS_CELLNAME = "aibcr3aux_pasred";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
//assign csr_pred_rxen_int[2:0] = csr_iocsr_sel ? csr_pred_rxen[2:0] : vssl_aibcr3aux;
//assign csr_pred_pdrv_int[1:0] = csr_iocsr_sel ? csr_pred_pdrv[1:0] : {vcc_aibcr3aux, vssl_aibcr3aux};
//assign csr_pred_txen_int = csr_iocsr_sel ? csr_pred_txen : vcc_aibcr3aux;
//assign csr_pred_ndrv_int[1:0] = csr_iocsr_sel ? csr_pred_ndrv[1:0] : {vcc_aibcr3aux, vssl_aibcr3aux};
aibcr3_buffx1_top xporvccl ( .idata1_in1_jtag_out(net0307),
.idata0_in1_jtag_out(net0334), .async_dat_in1_jtag_out(net0336),
.prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0266),
/*.vssl(vssl_aibcr3aux),*/ /*.vccl(vccl_aibcr3aux),*/ /*.vcc(vccl_aibcr3aux),*/
.por_aib_vccl(vssl_aibcr3aux), .por_aib_vcchssi(vssl_aibcr3aux),
.anlg_rstb(vccl_aibcr3aux), .pd_data_aib(net087), .oclk_out(net075),
.oclkb_out(net076), .odat0_out(net077), .odat1_out(net078),
.odat_async_out(net0276), .pd_data_out(net080),
.async_dat_in0(vccl_aibcr3aux), .async_dat_in1(vssl_aibcr3aux),
.iclkin_dist_in0(vssl_aibcr3aux), .iclkin_dist_in1(vssl_aibcr3aux),
.idata0_in0(vssl_aibcr3aux), .idata0_in1(vssl_aibcr3aux),
.idata1_in0(vssl_aibcr3aux), .idata1_in1(vssl_aibcr3aux),
.idataselb_in0(vssl_aibcr3aux), .idataselb_in1(vssl_aibcr3aux),
.iddren_in0(vssl_aibcr3aux), .iddren_in1(vssl_aibcr3aux),
.ilaunch_clk_in0(vssl_aibcr3aux), .ilaunch_clk_in1(vssl_aibcr3aux),
.ilpbk_dat_in0(vssl_aibcr3aux), .ilpbk_dat_in1(vssl_aibcr3aux),
.ilpbk_en_in0(vssl_aibcr3aux), .ilpbk_en_in1(vssl_aibcr3aux),
.indrv_in0({vccl_aibcr3aux,vssl_aibcr3aux}), .indrv_in1({vssl_aibcr3aux,
vssl_aibcr3aux}), .ipdrv_in0({vccl_aibcr3aux,vssl_aibcr3aux}),
.ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
.irxen_in0({vssl_aibcr3aux, vccl_aibcr3aux, vssl_aibcr3aux}),
.irxen_in1({vssl_aibcr3aux, vccl_aibcr3aux, vssl_aibcr3aux}),
.istrbclk_in0(vssl_aibcr3aux), .istrbclk_in1(vssl_aibcr3aux),
.itxen_in0(vccl_aibcr3aux), .itxen_in1(vssl_aibcr3aux),
.oclk_in1(vssl_aibcr3aux), .odat_async_aib(net086),
.oclkb_in1(vssl_aibcr3aux), .jtag_clksel(vssl_aibcr3aux),
.odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
.odat_async_in1(vssl_aibcr3aux), .shift_en(vssl_aibcr3aux),
.pd_data_in1(vssl_aibcr3aux), .dig_rstb(vccl_aibcr3aux),
.jtag_clkdr_out(net051), .jtag_intest(vssl_aibcr3aux),
.odat1_aib(net085), .jtag_rx_scan_out(net052), .odat0_aib(net084),
.oclk_aib(net082), .last_bs_out(net050), .oclkb_aib(net083),
.jtag_clkdr_in(vssl_aibcr3aux), .jtag_rstb_en(vssl_aibcr3aux),
.jtag_mode_in(vssl_aibcr3aux), .jtag_rstb(vssl_aibcr3aux),
.jtag_tx_scan_in(vssl_aibcr3aux),
.jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
.iopad(iopad_crdet), .oclkn(net081), .iclkn(vssl_aibcr3aux),
.test_weakpu(vssl_aibcr3aux), .test_weakpd(vssl_aibcr3aux));
aibcr3_buffx1_top xdn_por ( .idata1_in1_jtag_out(net0325),
.idata0_in1_jtag_out(net0297), .async_dat_in1_jtag_out(net0290),
.prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0285),
/*.vssl(vssl_aibcr3aux),*/ /*.vccl(vccl_aibcr3aux),*/ /*.vcc(vccl_aibcr3aux),*/
.por_aib_vccl(vssl_aibcr3aux), .por_aib_vcchssi(vssl_aibcr3aux),
.jtag_clksel(vssl_aibcr3aux), .jtag_intest(vssl_aibcr3aux),
.jtag_rstb_en(vssl_aibcr3aux), .anlg_rstb(vccl_aibcr3aux),
.pd_data_aib(net0115), .oclk_out(net0103), .oclkb_out(net0104),
.odat0_out(net0105), .odat1_out(net0106), .odat_async_out(net0269),
.pd_data_out(net0108), .async_dat_in0(vssl_aibcr3aux),
.async_dat_in1(vssl_aibcr3aux), .iclkin_dist_in0(vssl_aibcr3aux),
.iclkin_dist_in1(vssl_aibcr3aux), .idata0_in0(vssl_aibcr3aux),
.idata0_in1(vssl_aibcr3aux), .idata1_in0(vssl_aibcr3aux),
.idata1_in1(vssl_aibcr3aux), .idataselb_in0(vssl_aibcr3aux),
.idataselb_in1(vssl_aibcr3aux), .iddren_in0(vssl_aibcr3aux),
.iddren_in1(vssl_aibcr3aux), .ilaunch_clk_in0(vssl_aibcr3aux),
.ilaunch_clk_in1(vssl_aibcr3aux), .ilpbk_dat_in0(vssl_aibcr3aux),
.ilpbk_dat_in1(vssl_aibcr3aux), .ilpbk_en_in0(vssl_aibcr3aux),
.ilpbk_en_in1(vssl_aibcr3aux), .indrv_in0({vssl_aibcr3aux,
vssl_aibcr3aux}), .indrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
.ipdrv_in0({vssl_aibcr3aux, vssl_aibcr3aux}),
.ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
.irxen_in0({vssl_aibcr3aux, vssl_aibcr3aux, vssl_aibcr3aux}), .irxen_in1({vssl_aibcr3aux,
vssl_aibcr3aux, vssl_aibcr3aux}), .istrbclk_in0(vssl_aibcr3aux),
.istrbclk_in1(vssl_aibcr3aux), .itxen_in0(vssl_aibcr3aux),
.itxen_in1(vssl_aibcr3aux), .oclk_in1(vssl_aibcr3aux),
.odat_async_aib(dn_por), .oclkb_in1(vssl_aibcr3aux),
.odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
.odat_async_in1(vssl_aibcr3aux), .shift_en(vssl_aibcr3aux),
.pd_data_in1(vssl_aibcr3aux), .dig_rstb(vccl_aibcr3aux),
.jtag_clkdr_out(net073), .odat1_aib(net0113),
.jtag_rx_scan_out(net071), .odat0_aib(net0112),
.oclk_aib(net0110), .last_bs_out(net072), .oclkb_aib(net0111),
.jtag_clkdr_in(vssl_aibcr3aux), .jtag_mode_in(vssl_aibcr3aux),
.jtag_rstb(vssl_aibcr3aux), .jtag_tx_scan_in(vssl_aibcr3aux),
.jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
.iopad(iopad_dn_por), .oclkn(net0109), .iclkn(vssl_aibcr3aux),
// .test_weakpu(vssl_aibcr3aux), .test_weakpd(vccl_aibcr3aux));
.test_weakpu(vccl_aibcr3aux), .test_weakpd(vssl_aibcr3aux)); //Changed from pull down to pull up for Figure 6-16 AIB AUX
//Design Implementation of AIB system spec. JZ 12/30/2019
endmodule |
module aibcr3aux_top_master
(
output wire o_por_vcchssi,
output wire o_por_vccl,
output wire osc_clkout,
inout wire device_detect, //Shrink aux74/75 due to limit microbump/C4 bump pin
inout wire por, //Shrink aux85/87 pin due to limit microbump/C4 bump pin
input m_por_ovrd,
input i_osc_clk
);
`ifdef LEVEL_SHIFTER_TEST
wire vccl_aibcr3aux;
wire vcc_aibcr3aux;
`else
wire vccl_aibcr3aux = 1'b1;
wire vcc_aibcr3aux = 1'b1;
`endif
wire vssl_aibcr3aux =1'b0;
//Changed instantiation to match with the schematic, Jennifer 05/04/18
wire por_out; //After IO buffer
wire por_out_vcc; //After level shifter
aibcr3aux_pasred_baldwin xpasred (
.iopad_crdet(device_detect),
.vssl_aibcr3aux(vssl_aibcr3aux),
.vccl_aibcr3aux(vccl_aibcr3aux),
.iopad_dn_por(por),
.dn_por(por_dummy));
assign o_por_vcc = (m_por_ovrd & por_out_vcc);
assign osc_clkout = i_osc_clk;
assign o_por_vcchssi = o_por_vcc;
assign o_por_vccl = 1'b0;
aibcr3_lvshift_vcc xlvlshf1 (
.vccl_aibcr3aux(vccl_aibcr3aux), .vcc_aibcr3aux(vcc_aibcr3aux),
.out(por_out_vcc), .in(por)); //Output go to AND gate to produce o_por_vccl
endmodule |
module aibcr3_lvshift_vcc ( out, vccl_aibcr3aux, vcc_aibcr3aux, in);
output out;
input vccl_aibcr3aux, vcc_aibcr3aux;
input in;
reg out;
always @ (in, vccl_aibcr3aux, vcc_aibcr3aux)
begin
if (vccl_aibcr3aux == 1'b0 && vcc_aibcr3aux == 1'b0)
begin
out = 1'b0;
end
else if (vccl_aibcr3aux == 1'b0 && vcc_aibcr3aux == 1'b1)
begin
out = 1'b1;
end
else if (vccl_aibcr3aux == 1'b1 && vcc_aibcr3aux == 1'b0)
begin
out = 1'b0;
end
else if (vccl_aibcr3aux == 1'b1 && vcc_aibcr3aux == 1'b1)
begin
out = in;
end
else
begin
out = 1'bx;
end
end
endmodule |
module aibcr3_clktree_mimic
#(
parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps
)
(
input wire clkin, //clock source
output wire lstrbclk_l_0, //buffered clock
output wire lstrbclk_l_1, //buffered clock
output wire lstrbclk_l_2, //buffered clock
output wire lstrbclk_l_3, //buffered clock
output wire lstrbclk_l_4, //buffered clock
output wire lstrbclk_l_5, //buffered clock
output wire lstrbclk_l_6, //buffered clock
output wire lstrbclk_l_7, //buffered clock
output wire lstrbclk_l_8, //buffered clock
output wire lstrbclk_l_9, //buffered clock
output wire lstrbclk_l_10, //buffered clock
output wire lstrbclk_l_11, //buffered clock
output wire lstrbclk_rep, //replica for DLL
output wire lstrbclk_mimic0 //mimic path for load matching
);
`ifdef TIMESCALE_EN
timeunit 1ps;
timeprecision 1ps;
`endif
`ifdef BEHAVIORAL
assign #SKEW_DELAY lstrbclk_l_0 = clkin;
assign #SKEW_DELAY lstrbclk_l_1 = clkin;
assign #SKEW_DELAY lstrbclk_l_2 = clkin;
assign #SKEW_DELAY lstrbclk_l_3 = clkin;
assign #SKEW_DELAY lstrbclk_l_4 = clkin;
assign #SKEW_DELAY lstrbclk_l_5 = clkin;
assign #SKEW_DELAY lstrbclk_l_6 = clkin;
assign #SKEW_DELAY lstrbclk_l_7 = clkin;
assign #SKEW_DELAY lstrbclk_l_8 = clkin;
assign #SKEW_DELAY lstrbclk_l_9 = clkin;
assign #SKEW_DELAY lstrbclk_l_10 = clkin;
assign #SKEW_DELAY lstrbclk_l_11 = clkin;
assign #SKEW_DELAY lstrbclk_rep = clkin;
assign #SKEW_DELAY lstrbclk_mimic0 = clkin;
`else
wire clk_main, clk_l, clk_r;
wire [23:0] dummy_out;
// Process-specific to meet insertion delay
// Insert your process specific buffer cell here
bufclkprocspec1x1 buf_main_0 (.clkout(clk_main), .clk(clkin));
// These mimic buffx1 clock tree loads
// Input cap of each of these should match that of BUFFX1 istrbclk_in0 input (2.6729fF)
// Process-specific for now
bufclkprocspec1x5 dummy_0 (.a(lstrbclk_l_0), .o1(dummy_out[0]));
bufclkprocspec1x5 dummy_1 (.a(lstrbclk_l_1), .o1(dummy_out[1]));
bufclkprocspec1x5 dummy_2 (.a(lstrbclk_l_2), .o1(dummy_out[2]));
bufclkprocspec1x5 dummy_3 (.a(lstrbclk_l_3), .o1(dummy_out[3]));
bufclkprocspec1x5 dummy_4 (.a(lstrbclk_l_4), .o1(dummy_out[4]));
bufclkprocspec1x5 dummy_5 (.a(lstrbclk_l_5), .o1(dummy_out[5]));
bufclkprocspec1x5 dummy_6 (.a(lstrbclk_l_6), .o1(dummy_out[6]));
bufclkprocspec1x5 dummy_7 (.a(lstrbclk_l_7), .o1(dummy_out[7]));
bufclkprocspec1x5 dummy_8 (.a(lstrbclk_l_8), .o1(dummy_out[8]));
bufclkprocspec1x5 dummy_9 (.a(lstrbclk_l_9), .o1(dummy_out[9]));
bufclkprocspec1x5 dummy_10 (.a(lstrbclk_l_10), .o1(dummy_out[10]));
bufclkprocspec1x5 dummy_11 (.a(lstrbclk_l_11), .o1(dummy_out[11]));
bufclkprocspec1x5 dummy_12 (.a(clk_main), .o1(dummy_out[12]));
bufclkprocspec1x5 dummy_13 (.a(clk_main), .o1(dummy_out[13]));
bufclkprocspec1x5 dummy_14 (.a(clk_main), .o1(dummy_out[14]));
bufclkprocspec1x5 dummy_15 (.a(clk_main), .o1(dummy_out[15]));
bufclkprocspec1x5 dummy_16 (.a(clk_main), .o1(dummy_out[16]));
bufclkprocspec1x5 dummy_17 (.a(clk_main), .o1(dummy_out[17]));
bufclkprocspec1x5 dummy_18 (.a(clk_main), .o1(dummy_out[18]));
bufclkprocspec1x5 dummy_19 (.a(clk_main), .o1(dummy_out[19]));
bufclkprocspec1x5 dummy_20 (.a(clk_main), .o1(dummy_out[20]));
bufclkprocspec1x5 dummy_21 (.a(clk_main), .o1(dummy_out[21]));
bufclkprocspec1x5 dummy_22 (.a(clk_main), .o1(dummy_out[22]));
bufclkprocspec1x5 dummy_23 (.a(clk_main), .o1(dummy_out[23]));
assign lstrbclk_l_0 = clk_main;
assign lstrbclk_l_1 = clk_main;
assign lstrbclk_l_2 = clk_main;
assign lstrbclk_l_3 = clk_main;
assign lstrbclk_l_4 = clk_main;
assign lstrbclk_l_5 = clk_main;
assign lstrbclk_l_6 = clk_main;
assign lstrbclk_l_7 = clk_main;
assign lstrbclk_l_8 = clk_main;
assign lstrbclk_l_9 = clk_main;
assign lstrbclk_l_10 = clk_main;
assign lstrbclk_l_11 = clk_main;
assign lstrbclk_rep = clk_main;
assign lstrbclk_mimic0 = clk_main;
`endif
endmodule // aibcr_clktree_mimic |
module aibcr3_clktree
#(
parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps
)
(
input wire clkin, //clock source
output wire lstrbclk_l_0, //buffered clock
output wire lstrbclk_l_1, //buffered clock
output wire lstrbclk_l_2, //buffered clock
output wire lstrbclk_l_3, //buffered clock
output wire lstrbclk_l_4, //buffered clock
output wire lstrbclk_l_5, //buffered clock
output wire lstrbclk_l_6, //buffered clock
output wire lstrbclk_l_7, //buffered clock
output wire lstrbclk_l_8, //buffered clock
output wire lstrbclk_l_9, //buffered clock
output wire lstrbclk_l_10, //buffered clock
output wire lstrbclk_l_11, //buffered clock
output wire lstrbclk_r_0, //buffered clock
output wire lstrbclk_r_1, //buffered clock
output wire lstrbclk_r_2, //buffered clock
output wire lstrbclk_r_3, //buffered clock
output wire lstrbclk_r_4, //buffered clock
output wire lstrbclk_r_5, //buffered clock
output wire lstrbclk_r_6, //buffered clock
output wire lstrbclk_r_7, //buffered clock
output wire lstrbclk_r_8, //buffered clock
output wire lstrbclk_r_9, //buffered clock
output wire lstrbclk_r_10, //buffered clock
output wire lstrbclk_r_11, //buffered clock
output wire lstrbclk_rep, //replica for DLL
output wire lstrbclk_mimic0, //mimic path for load matching
output wire lstrbclk_mimic1, //mimic path for load matching
output wire lstrbclk_mimic2 //mimic path for load matching
);
`ifdef TIMESCALE_EN
timeunit 1ps;
timeprecision 1ps;
`endif
`ifdef BEHAVIORAL
assign #SKEW_DELAY lstrbclk_l_0 = clkin;
assign #SKEW_DELAY lstrbclk_l_1 = clkin;
assign #SKEW_DELAY lstrbclk_l_2 = clkin;
assign #SKEW_DELAY lstrbclk_l_3 = clkin;
assign #SKEW_DELAY lstrbclk_l_4 = clkin;
assign #SKEW_DELAY lstrbclk_l_5 = clkin;
assign #SKEW_DELAY lstrbclk_l_6 = clkin;
assign #SKEW_DELAY lstrbclk_l_7 = clkin;
assign #SKEW_DELAY lstrbclk_l_8 = clkin;
assign #SKEW_DELAY lstrbclk_l_9 = clkin;
assign #SKEW_DELAY lstrbclk_l_10 = clkin;
assign #SKEW_DELAY lstrbclk_l_11 = clkin;
assign #SKEW_DELAY lstrbclk_r_0 = clkin;
assign #SKEW_DELAY lstrbclk_r_1 = clkin;
assign #SKEW_DELAY lstrbclk_r_2 = clkin;
assign #SKEW_DELAY lstrbclk_r_3 = clkin;
assign #SKEW_DELAY lstrbclk_r_4 = clkin;
assign #SKEW_DELAY lstrbclk_r_5 = clkin;
assign #SKEW_DELAY lstrbclk_r_6 = clkin;
assign #SKEW_DELAY lstrbclk_r_7 = clkin;
assign #SKEW_DELAY lstrbclk_r_8 = clkin;
assign #SKEW_DELAY lstrbclk_r_9 = clkin;
assign #SKEW_DELAY lstrbclk_r_10 = clkin;
assign #SKEW_DELAY lstrbclk_r_11 = clkin;
assign #SKEW_DELAY lstrbclk_rep = clkin;
assign #SKEW_DELAY lstrbclk_mimic0 = clkin;
assign #SKEW_DELAY lstrbclk_mimic1 = clkin;
assign #SKEW_DELAY lstrbclk_mimic2 = clkin;
`else
wire clk_main, clk_l, clk_r;
// Process-specific to meet insertion delay
// Insert your process specific buffer cell here
bufclkprocspec1x1 buf_main_0 (.clkout(clk_main), .clk(clkin));
assign lstrbclk_l_0 = clk_main;
assign lstrbclk_l_1 = clk_main;
assign lstrbclk_l_2 = clk_main;
assign lstrbclk_l_3 = clk_main;
assign lstrbclk_l_4 = clk_main;
assign lstrbclk_l_5 = clk_main;
assign lstrbclk_l_6 = clk_main;
assign lstrbclk_l_7 = clk_main;
assign lstrbclk_l_8 = clk_main;
assign lstrbclk_l_9 = clk_main;
assign lstrbclk_l_10 = clk_main;
assign lstrbclk_l_11 = clk_main;
assign lstrbclk_r_0 = clk_main;
assign lstrbclk_r_1 = clk_main;
assign lstrbclk_r_2 = clk_main;
assign lstrbclk_r_3 = clk_main;
assign lstrbclk_r_4 = clk_main;
assign lstrbclk_r_5 = clk_main;
assign lstrbclk_r_6 = clk_main;
assign lstrbclk_r_7 = clk_main;
assign lstrbclk_r_8 = clk_main;
assign lstrbclk_r_9 = clk_main;
assign lstrbclk_r_10 = clk_main;
assign lstrbclk_r_11 = clk_main;
assign lstrbclk_rep = clk_main;
assign lstrbclk_mimic0 = clk_main;
assign lstrbclk_mimic1 = clk_main;
assign lstrbclk_mimic2 = clk_main;
`endif
endmodule // aibcr_clktree |
module aibcr3_rxdig ( clkbuf_en, datbuf_en, odat0, odat1, rx_disable,
rx_idat_buf, sync_datbuf_en0, sync_datbuf_en1,
iclkin_dist, ipadrstb, irstb, irxen, istrbclk, rx_idat );
output clkbuf_en, datbuf_en, odat0, odat1, rx_disable, rx_idat_buf,
sync_datbuf_en0, sync_datbuf_en1;
input iclkin_dist, ipadrstb, irstb, istrbclk, rx_idat;
input [2:0] irxen;
wire pre_databuf_enb;
wire pre_databuf_en_outb;
wire irxen0_b;
wire irxen1;
wire irxen2_b;
wire irxen0;
wire irxen1_b;
wire irxen2;
wire datbuf_enb;
wire syncdat_en0b;
wire gt_sync_datbuf_en1b;
wire gt_sync_datbuf_en0b;
wire idat1_hold_buf1;
wire idat1_sync;
wire idat0_sync;
wire idat0_hold_buf3;
wire idat0_latch;
wire istrbclkb;
wire rx_idatb;
wire odat1_int;
wire odat0_int;
assign tielo = 1'b0;
assign pre_databuf_en = !pre_databuf_enb;
assign pre_databuf_en_out = !pre_databuf_en_outb;
assign rx_disableb = !(irxen0_b & irxen1 & irxen2_b);
assign syncdat_en1b = !(irxen0 & irxen1_b & irxen2_b);
assign clk_modeb = !(irxen0 & irxen1 & irxen2_b);
assign pd_modeb = !(irxen0_b & irxen1_b & irxen2);
assign asyncdat_enb = !(irxen0_b & irxen1_b & irxen2_b);
assign datbuf_en = !datbuf_enb;
assign asyn_data_en = !asyncdat_enb;
assign sdr_mode = !pd_modeb;
assign clkbuf_en = !clk_modeb;
assign sync_datbuf_en0 = !syncdat_en0b;
assign sync_datbuf_en1 = !syncdat_en1b;
assign rx_disable = !rx_disableb;
assign net069 = !ipadrstb;
assign irxen2 = !irxen2_b;
assign irxen1 = !irxen1_b;
assign irxen0 = !irxen0_b;
assign gt_sync_datbuf_en1 = !gt_sync_datbuf_en1b;
assign gt_sync_datbuf_en0 = !gt_sync_datbuf_en0b;
assign pre_databuf_en_outb = !(pre_databuf_en | tielo);
assign datbuf_enb = !(pre_databuf_en_out | sdr_mode);
assign pre_databuf_enb = !(sync_datbuf_en1 | asyn_data_en);
assign syncdat_en0b = !(sync_datbuf_en1 | sdr_mode);
assign irxen0_b = !(irxen[0] & ipadrstb);
assign irxen1_b = !(irxen[1] | net069);
assign irxen2_b = !(irxen[2] & ipadrstb);
assign gt_sync_datbuf_en1b = !(irstb & sync_datbuf_en1);
assign gt_sync_datbuf_en0b = !(irstb & sync_datbuf_en0);
assign idat0_latch_buf1 = idat1_hold_buf1;
assign idat1_hold_buf1 = idat1_sync;
assign idat0_hold_buf1 = idat0_sync;
assign idat0_latch_din = idat0_hold_buf3;
assign idat0_hold_buf4 = idat0_latch;
assign idat0_hold_buf5 = idat0_hold_buf4;
assign idat0_latch_buf0 = idat0_hold_buf5;
assign idat0_hold_buf2 = idat0_hold_buf1;
assign idat0_hold_buf3 = idat0_hold_buf2;
assign istrbclk_buf = !istrbclkb;
assign istrbclkb = !istrbclk;
assign rx_idat_buf_del_inv = !rx_idat_buf;
assign iclkin_distb = !iclkin_dist;
assign iclkin_dist_buf = !iclkin_distb;
assign rx_idat_buf = !rx_idatb;
assign rx_idatb = !rx_idat;
assign odat1 = odat1_int;
assign odat0 = odat0_int;
`ifdef BEHAVIORAL
wire odat1_int_inv;
assign odat1_int = !odat1_int_inv;
aibcr3_ulvt16_dffcdn_cust x56 ( .Q(idat1_sync),
.CDN(gt_sync_datbuf_en1), .CK(istrbclk_buf), .D(rx_idat_buf_del_inv));
aibcr3_ulvt16_dffcdn_cust x49 ( .Q(idat0_sync),
.CDN(gt_sync_datbuf_en0), .CK(istrbclkb), .D(rx_idat_buf));
aibcr3_latch x44 (.Q(idat0_latch), .CDN(gt_sync_datbuf_en0), .E(istrbclk_buf),
.D(idat0_latch_din));
/* changed to latch
aibcr3_ulvt16_dffcdn_cust x44 ( .Q(idat0_latch),
.CDN(gt_sync_datbuf_en0), .CK(istrbclkb), .D(idat0_latch_din));
*/
aibcr3_ulvt16_dffsdn_cust x35 ( .Q(odat1_int_inv),
.CK(iclkin_dist_buf), .D(idat0_latch_buf1), .SDN(gt_sync_datbuf_en1));
aibcr3_ulvt16_dffcdn_cust x36 ( .Q(odat0_int),
.CDN(gt_sync_datbuf_en0), .CK(iclkin_dist_buf), .D(idat0_latch_buf0));
`else
wire rx_idat_del0;
wire rx_idat0_latch, rx_idat0_ff, rx_idat1_ff;
buf_hvt delay_buf (.out(rx_idat_del0), .in(rx_idat));
// Switched the order of latch and flip-flop due to cell availability to avoid need for istrbclkb
//DFFRPQ_X1M_A12TR in0_ff (.Q(idat0_sync), .CK(istrbclkb), .D(rx_idat_buf), .R(~gt_sync_datbuf_en0));
//LATRQ_X1M_A12TR in0_latch (.Q(idat0_latch), .E(istrbclk_buf), .D(idat0_latch_din), .RN(gt_sync_datbuf_en0));
//DFFRPQ_X1M_A12TR in1_ff (.Q(idat1_sync), .CK(istrbclk_buf), .D(rx_idat_buf_del_inv), .R(~gt_sync_datbuf_en1));
// PE: Previous change inverted polarity of data through dat1
// datapath, but forgot to swap out async set flop for async
// reset flop.
latch_rn in0_latch (.q(rx_idat0_latch), .clk(istrbclk), .d(rx_idat_del0), .rn(gt_sync_datbuf_en0));
flop_r in0_ff (.q(rx_idat0_ff), .clk(istrbclk), .d(rx_idat0_latch), .r(~gt_sync_datbuf_en0));
flop_r in1_ff (.q(rx_idat1_ff), .clk(istrbclk), .d(rx_idat_del0), .r(~gt_sync_datbuf_en1));
flop_r out0_ff (.q(odat0_int), .clk(iclkin_dist), .d(rx_idat0_ff), .r(~gt_sync_datbuf_en0));
flop_r out1_ff (.q(odat1_int), .clk(iclkin_dist), .d(rx_idat1_ff), .r(~gt_sync_datbuf_en1));
`endif
endmodule |
module aibcr3_bypmux (
input wire byp,
input wire in0,
input wire in1,
output wire out
);
`ifdef BEHAVIORAL
assign out = (byp) ? in1 : in0;
`else
data_mux_2_1 mx(.sel(byp), .in0(in0), .in1(in1), .out(out));
`endif
endmodule |
module aibcr3_ulvt16_2xarstsyncdff1_b2 (CLR_N, CK, D, SE, SI, Q);
input CLR_N, CK, D, SE, SI;
output logic Q;
wire data;
assign data = SE ? SI : D ;
`ifdef BEHAVIORAL
reg flop_0;
always @(posedge CK or negedge CLR_N)
if (!CLR_N) {Q,flop_0} <= 0;
else if (CLR_N) {Q,flop_0} <= {flop_0,data};
else {Q,flop_0} <= 0;
`else
data_sync_for_aib
# (
.ActiveLow ( 1 ),
.ResetVal ( 1'b0 ),
.SyncRegWidth ( 2 )
)
u_data_sync
(
.clk ( CK ),
.rst_in ( CLR_N ),
.data_in ( data ),
.data_out ( Q )
);
`endif
endmodule |
module aibcr3_dcc_dly_rep ( clkrep, idat, rb_dcc_byp );
output clkrep;
input idat, rb_dcc_byp;
wire tielo;
wire buf_idat;
wire dcc_byp_n;
wire dcc_byp_p;
wire idat_mux0;
wire idat_mux2;
assign tielo = 1'b0;
assign tiehi = 1'b1;
aibcr3_dcc_interpolator x12 (
.intout(idat_mux0),
.a_in(net014),
.sn({tiehi, tiehi, tiehi, tiehi, tiehi, tiehi, tiehi}),
.sp({tielo, tielo, tielo, tielo, tielo, tielo, tielo}));
assign buf_idat = idat;
assign idat_mux2 = idat_mux0;
assign dcc_byp_p = rb_dcc_byp ;
assign clkrep = dcc_byp_p ? buf_idat : idat_mux2;
aibcr3_dlycell_dcc_rep x17 ( net030, net014, tielo, tiehi,
buf_idat);
endmodule |
module aibcr3_dcc_dly ( SOOUT, clk_dly, clk_mindly, PDb,
SE, SI, SMCLK, clk_dcd, dll_lock_reg, gray, launch, measure );
output SOOUT, clk_dly, clk_mindly;
input PDb, SE, SI, SMCLK, clk_dcd, dll_lock_reg, launch, measure;
input [10:0] gray;
// Buses in the design
wire [0:255] net105;
assign tieLO = 1'b0;
assign tieHI = 1'b1;
//assign net102 = tieLO? measure : tieLO;
data_mux_2_1 mindly_mux(.in0(measure), .in1(clk_dcd), .sel(dll_lock_reg), .out(clkin_mindly));
data_mux_2_1 dlyline_mux(.in0(launch), .in1(clk_dcd), .sel(dll_lock_reg), .out(clkin_dlyline));
// Actual delay path
aibcr3_dcc_dlyline I0 ( SO_dlyline, net105[0:255], net029, clk_dly,
clkin_dlyline, PDb, SE, SI, SMCLK, gray[10:0]);
// Intrinsic delay compensation path
aibcr3_dcc_8ph_intp I1 ( SOOUT, clk_mindly, SMCLK, PDb,
net104, {tieLO, tieLO, tieLO}, SE, SO_dlyline);
aibcr3_dlycell_dcc I7 ( .co_p(net103), .out_p(net104), .bk(tieLO), .ci_p(tieHI),
.in_p(clkin_mindly));
endmodule |
module aibcr3_analog ( oclkn, oclkp, odat, odat_async,
iopad, iopad_out, clk_en, data_en, iclkn, indrv_buf, ipdrv_buf,
itx_en_buf, por_aib_vcc1, por_aib_vcchssi, txdin, weak_pulldownen,
weak_pullupenb
);
output wire oclkn, oclkp, odat, odat_async;
inout wire iopad, iopad_out;
input wire clk_en, data_en, iclkn, itx_en_buf, por_aib_vcc1,
por_aib_vcchssi, txdin, weak_pulldownen, weak_pullupenb;
input wire [1:0] indrv_buf;
input wire [1:0] ipdrv_buf;
wire net14;
wire tielo;
wire odat_maxout;
wire odat_mid;
assign tielo = 1'b0;
`ifdef BEHAVIORAL
assign odat_maxout = tielo? tielo : net14;
assign odat = odat_maxout;
`else
// Dummy loading / delays, these need to be preserved
aibcr3_bypmux_x4 delay_mux (.out(odat_maxout), .byp(tielo), .in1(tielo), .in0(net14));
buffer delay_buf (.out(odat_mid), .in(odat_maxout));
// BCA: delay_buf_2 is the additional delay buffer that Ayar put in aibcr3_rxdig on this same
// timing path. We moved it here because we are using Intel's aibcr3_rxdig, but still wanted
// the matching delay of the additional buffer.
buffer delay_buf_2 (.out(odat), .in(odat_mid));
`endif
aibcr3_frontend u_aibcr3_frontend (
.clk_en(clk_en),
.data_en(data_en),
.din(txdin),
.iclkn(iclkn),
.indrv_buf(indrv_buf[1:0]),
.ipdrv_buf(ipdrv_buf[1:0]),
.itx_en_buf(itx_en_buf),
.por(por_aib_vcchssi),
.weak_pulldownen(weak_pulldownen),
.weak_pullupenb(weak_pullupenb),
.iopad_out(iopad_out),
.oclkn(oclkn),
.oclkp(oclkp),
.odat(net14),
.odat_async(odat_async),
.iopad(iopad)
);
endmodule |
module aibcr3_ddrmux (
input wire clk,
input wire in0,
input wire in1,
output wire out
);
`ifdef BEHAVIORAL
assign out = (clk) ? in1 : in0;
`else
data_mux_2_1 mx(.sel(clk), .in0(in0), .in1(in1), .out(out));
`endif
endmodule |
module clk_gate_cel(
output clkout, // Clock gated
input clk, // Clock input
input en, // Clock enable
input te // Test enable
);
wire clk_en;
reg latch;
assign clk_en = te | en;
always @(clk or clk_en)
begin
if(!clk)
latch = clk_en;
end
assign clkout = latch & clk;
endmodule // clk_gate_cel |
module clk_inv_cel(
output clkout, // clock output
input clk // clock input
);
assign clkout = ~clk;
endmodule // clk_inv_cel |
module clk_and2_cel(
output clkout, // AND output
input clk1, // clock 1
input clk2 // clock 2
);
assign clkout = clk1 & clk2;
endmodule // clk_and2_cel |
module clk_resize_cel(
output clkout, // clock output
input clk // clock input
);
assign clkout = clk;
endmodule // clk_resize_cel |
module clk_or3_cel(
output clkout, // OR output
input clk1, // clock 1
input clk2, // clock 2
input clk3 // clock 3
);
wire clkout_1_2;
wire clkout_3;
// First OR level for clk1 and clk2
clk_or2_cel clk_or2_1(
.clkout (clkout_1_2), // OR output
.clk1 (clk1), // clock 1
.clk2 (clk2) // clock 2
);
// First OR level for clk3
clk_or2_cel clk_or2_2(
.clkout (clkout_3), // OR output
.clk1 (clk3), // clock 1
.clk2 (1'b0) // clock 2
);
// Second OR level for clk1, clk2 and clk3
clk_or2_cel clk_or2_3(
.clkout (clkout), // OR output
.clk1 (clkout_1_2), // clock 1
.clk2 (clkout_3) // clock 2
);
endmodule // clk_or3_cel |
module clk_and4_cel(
output clkout, // AND output
input clk1, // clock 1
input clk2, // clock 2
input clk3, // clock 3
input clk4 // clock 3
);
assign clkout = clk1 & clk2 & clk3 & clk4;
endmodule // clk_and4_cel |
module clk_buf_cel(
output clkout, // clock output
input clk // clock input
);
assign clkout = clk;
endmodule // clk_buf_cel |
module clk_mux(
// Inputs
input clk1, // Clock 1 input
input clk2, // Clock 2 input
input s, // Clock selection: 1 - clkout = clk1
// 0 - clkout = clk2
// Outputs
output clkout // Clock output
);
// Clock mux
assign clkout = s ? clk1 : clk2;
endmodule // clk_mux |
module clk_or2_cel(
output clkout, // OR output
input clk1, // clock 1
input clk2 // clock 2
);
assign clkout = clk1 | clk2;
endmodule // clk_or2_cel |
module clk_den_flop(
input clk, // clock
input d, // data input
input den, // data enable
input rb, // Active low reset
output reg o // data output
);
// Flop with data enable
always @(posedge clk or negedge rb)
begin: o_register
if(!rb)
o <= 1'b0;
else if(den)
o <= d;
end // block: o_register
endmodule // clk_den_flop |
module dmux_cell(
output o, // Output
input d1, // Data 1
input d2, // Data 2
input s // Data selection
);
// mux
assign o = s ? d1 : d2;
endmodule // dmux_cell |
module clk_and3_cel(
output clkout, // AND output
input clk1, // clock 1
input clk2, // clock 2
input clk3 // clock 3
);
assign clkout = clk1 & clk2 & clk3;
endmodule // clk_and3_cel |
module aib_bit_sync
#(
parameter DWIDTH = 1'b1, // Sync Data input
parameter [DWIDTH-1:0] RESET_VAL = {DWIDTH{1'b0}} // Reset value
)
(
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
reg [DWIDTH-1:0] dff2;
reg [DWIDTH-1:0] dff1;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dff2 <= RESET_VAL;
dff1 <= RESET_VAL;
end
else begin
dff2 <= dff1;
dff1 <= data_in;
end
assign data_out = dff2;
endmodule // aib_bit_sync |
module aib_clk_div_sys (
// Inputs
input rst_n, // Asynchronous reset
input clk, // Clock
input scan_mode, // Scan mode
input clk_div_ld, // Clock divider enable from avalon interface
input clk_div_1_onehot, // Onehot enable for clock divided by 1
input clk_div_2_onehot, // Onehot enable for clock divided by 2
input clk_div_4_onehot, // Onehot enable for clock divided by 4
input clk_div_8_onehot, // Onehot enable for clock divided by 8
input clk_div_16_onehot, // Onehot enable for clock divided by 16
// Outputs
output clk_out, // Clock divided
output reg clk_div_ld_ack_ff // Clock divider load acknowledge
);
wire clk_div_ld_sync; // Clock divider enable in clk domain
wire clk_div_load; // Loads clock selection control
wire clk_div2; // Clock source divided by 2
wire clk_div4; // Clock source divided by 4
wire clk_div8; // Clock source divided by 8
wire clk_div16; // Clock source divided by 16
wire clk_div2_b; // Clock divided by 2 inverted
wire clk_div4_b; // Clock divided by 4 inverted
wire clk_div8_b; // Clock divided by 8 inverted
wire clk_div16_b; // Clock divided by 16 inverted
wire clk_div1_cg; // Clock divided by 1 after clock gating
wire clk_div2_cg; // Clock divided by 2 after clock gating
wire clk_div4_cg; // Clock divided by 4 after clock gating
wire clk_div8_cg; // Clock divided by 8 after clock gating
wire clk_div16_cg; // Clock divided by 16 after clock gating
wire div1_clk_en; // Clock enable for clock divided by 1
wire div2_clk_en; // Clock enable for clock divided by 2
wire div4_clk_en; // Clock enable for clock divided by 4
wire div8_clk_en; // Clock enable for clock divided by 8
wire div16_clk_en; // Clock enable for clock divided by 16
wire clkout_div1_div2; // First OR level for clock div 1 and clock div 2
wire clkout_div4_div8; // First OR level for clock div 4 and clock div 8
wire clkout_div_16; // First OR level for clock div 16
wire clkout_div_1_8; // Second OR level for clock div1, div 2 and div 8
wire clkout_div_16_2; // Second OR level for clock div16
wire clk_div8_and_en; //den for DIV8 ciruit, AND of DIV2 qb signal and DIV4 qb signal
wire clk_div16_and_en; //den for DIV16 ciruit, AND of DIV2 qb signal, DIV4 qb signal and DIV8 qb signal
reg clk_div_1_sel_ff; // Clock divided by 1 selection
reg clk_div_2_sel_ff; // Clock divided by 2 selection
reg clk_div_4_sel_ff; // Clock divided by 4 selection
reg clk_div_8_sel_ff; // Clock divided by 8 selection
reg clk_div_16_sel_ff; // Clock divided by 16 selection
// phcomp_wren Synchronizer
aib_bit_sync clk_div_load_sync
(
.clk (clk), // Clock of destination domain
.rst_n (rst_n), // Reset of destination domain
.data_in (clk_div_ld), // Input to be synchronized
.data_out (clk_div_ld_sync) // Synchronized output
);
assign clk_div_load = clk_div_ld_ack_ff ^ clk_div_ld_sync;
// Clock division update enable
always @(posedge clk or negedge rst_n)
begin: clk_div_ld_sync_register
if(!rst_n)
clk_div_ld_ack_ff <= 1'b0;
else
clk_div_ld_ack_ff <= clk_div_ld_sync;
end // block: clk_div_ld_sync_register
// Clock divided by 1 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_1_sel_register
if(!rst_n)
clk_div_1_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_1_sel_ff <= clk_div_1_onehot;
end // block: clk_div_1_sel_register
// Clock divided by 2 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_2_sel_register
if(!rst_n)
clk_div_2_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_2_sel_ff <= clk_div_2_onehot;
end // block: clk_div_2_sel_register
// Clock divided by 4 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_4_sel_register
if(!rst_n)
clk_div_4_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_4_sel_ff <= clk_div_4_onehot;
end // block: clk_div_4_sel_register
// Clock divided by 8 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_8_sel_register
if(!rst_n)
clk_div_8_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_8_sel_ff <= clk_div_8_onehot;
end // block: clk_div_8_sel_register
// Clock divided by 16 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_16_sel_register
if(!rst_n)
clk_div_16_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_16_sel_ff <= clk_div_16_onehot;
end // block: clk_div_16_sel_register
// Clock gating for DIV1 clock
clk_gate_cel cg_div_1( .clkout (clk_div1_cg),
.clk (clk),
.en (div1_clk_en),
.te (1'b0) );
assign div1_clk_en = clk_div_1_sel_ff | scan_mode;
assign div2_clk_en = clk_div_2_sel_ff & ~scan_mode;
assign div4_clk_en = clk_div_4_sel_ff & ~scan_mode;
assign div8_clk_en = clk_div_8_sel_ff & ~scan_mode;
assign div16_clk_en = clk_div_16_sel_ff & ~scan_mode;
// Clock gating for DIV2 clock
clk_gate_cel cg_div_2( .clkout (clk_div2_cg),
.clk (clk_div2),
.en (div2_clk_en),
.te (1'b0) );
// Clock gating for DIV4 clock
clk_gate_cel cg_div_4( .clkout (clk_div4_cg),
.clk (clk_div4),
.en (div4_clk_en),
.te (1'b0) );
// Clock gating for DIV8 clock
clk_gate_cel cg_div_8( .clkout (clk_div8_cg),
.clk (clk_div8),
.en (div8_clk_en),
.te (1'b0) );
// Clock gating for DIV16 clock
clk_gate_cel cg_div_16( .clkout (clk_div16_cg),
.clk (clk_div16),
.en (div16_clk_en),
.te (1'b0) );
// Flop to divide clock source by 2
clk_den_flop clk_div2_flop(
.clk (clk),
.d (clk_div2_b),
.den (1'b1),
.rb (rst_n),
.o (clk_div2)
);
// Clock divided by 2 inverted
clk_inv_cel clk_div2_inv(
.clkout (clk_div2_b),
.clk (clk_div2)
);
// Flop to divide clock source by 4
clk_den_flop clk_div4_flop(
.clk (clk),
.d (clk_div4_b),
.den (clk_div2_b),
.rb (rst_n),
.o (clk_div4)
);
// Clock divided by 4 inverted
clk_inv_cel clk_div4_inv(
.clkout (clk_div4_b),
.clk (clk_div4)
);
// Flop to divide clock source by 8
clk_den_flop clk_div8_flop(
.clk (clk),
.d (clk_div8_b),
.den (clk_div8_and_en),
.rb (rst_n),
.o (clk_div8)
);
// Clock divided by 8 inverted
clk_inv_cel clk_div8_inv(
.clkout (clk_div8_b),
.clk (clk_div8)
);
// AND for den signal of div8 circuit
clk_and2_cel clk_and2_div8(
.clkout (clk_div8_and_en), // AND output
.clk1 (clk_div4_b), // clock 1
.clk2 (clk_div2_b) // clock 2
);
// Flop to divide clock source by 16
clk_den_flop clk_div16_flop(
.clk (clk),
.d (clk_div16_b),
.den (clk_div16_and_en),
.rb (rst_n),
.o (clk_div16)
);
// Clock divided by 16 inverted
clk_inv_cel clk_div16_inv(
.clkout (clk_div16_b),
.clk (clk_div16)
);
// AND for den signal of div16 circuit
clk_and3_cel clk_and3_div16(
.clkout (clk_div16_and_en), // AND output
.clk1 (clk_div2_b), // clock 1
.clk2 (clk_div4_b), // clock 2
.clk3 (clk_div8_b) // clock 3
);
// First OR level for clk div 1 and clk div 2
clk_or2_cel clk_or2_div1_div2_1(
.clkout (clkout_div1_div2), // OR output
.clk1 (clk_div1_cg), // clock 1
.clk2 (clk_div2_cg) // clock 2
);
// First OR level for clk div 4 and clk div 8
clk_or2_cel clk_or2_div4_div8_1(
.clkout (clkout_div4_div8), // OR output
.clk1 (clk_div4_cg), // clock 1
.clk2 (clk_div8_cg) // clock 2
);
// First OR level for dclk div 16
clk_or2_cel clk_or2_div16_1(
.clkout (clkout_div_16), // OR output
.clk1 (clk_div16_cg), // clock 1
.clk2 (1'b0) // clock 2
);
// Second OR level 1 for clock div 1, 2 ,4 and 8
clk_or2_cel clk_or2_level2_1(
.clkout (clkout_div_1_8), // OR output
.clk1 (clkout_div1_div2), // clock 1
.clk2 (clkout_div4_div8) // clock 2
);
// Second OR level 2 for clock div 16
clk_or2_cel clk_or2_level2_2(
.clkout (clkout_div_16_2), // OR output
.clk1 (clkout_div_16), // clock 1
.clk2 (1'b0) // clock 2
);
// Level 3 OR
clk_or2_cel clk_or2_level3(
.clkout (clk_out), // OR output
.clk1 (clkout_div_1_8), // clock 1
.clk2 (clkout_div_16_2) // clock 2
);
endmodule // aib_clk_div_sys |
module aib_cdc_data_mux #(
parameter DWIDTH = 'd80 // Data bus width
)
(
// Inputs
input [DWIDTH-1:0] dmux_in0, // Data input for dmux_sel = 1
input [DWIDTH-1:0] dmux_in1, // Data input for dmux_sel = 0
input dmux_sel, // Data selection
// Outputs
output [DWIDTH-1:0] dmux_out // Data mux output
);
genvar i;
generate
for(i = 0; i < DWIDTH; i = i + 1)
begin: dmux_out_gen
dmux_cell dmux_cell(
.d1 (dmux_in0[i]), // Data selected when selection = 1
.d2 (dmux_in1[i]), // Data selected when selection = 0
.s (dmux_sel), // Data selection
.o ( dmux_out[i]) // MUX output data
);
end
endgenerate
endmodule // aib_cdc_data_mux |
module aib_rst_sync
(
input clk, // Destination clock of reset to be synced
input i_rst_n, // Asynchronous reset input
input scan_mode, // Scan bypass for reset
output sync_rst_n // Synchronized reset output
);
wire prescan_sync_rst_n;
aib_bit_sync
#(.DWIDTH(1), .RESET_VAL(0) )
i_sync_rst_n
(
.clk (clk ),
.rst_n (i_rst_n ),
.data_in (1'b1 ),
.data_out (prescan_sync_rst_n)
);
// Scan mux
dmux_cell rst_dmux_out(
.o (sync_rst_n), // Output
.d1 (i_rst_n), // Data 1 (s=1)
.d2 (prescan_sync_rst_n), // Data 2 (s=0)
.s (scan_mode) // Data selection
);
endmodule // aib_rst_sync |
module aib_adapt_fifo_mem #(
parameter DWIDTH = 'd320, // FIFO Input data width
parameter DEPTH = 'd16 // FIFO Depth
)
(
// Inputs
input [DEPTH-1 :0] ff_clk_39_0, // clocks for bits 39-0 of FIFO
input [DEPTH-1 :0] ff_clk_79_40, // clocks for bits 79-40 of FIFO
input [DEPTH-1 :0] ff_clk_119_80, // clocks for bits 119-80 of FIFO
input [DEPTH-1 :0] ff_clk_159_120, // clocks for bits 159-120 of FIFO
input [DEPTH-1 :0] ff_clk_199_160, // clocks for bits 199-160 of FIFO
input [DEPTH-1 :0] ff_clk_239_200, // clocks for bits 239-200 of FIFO
input [DEPTH-1 :0] ff_clk_279_240, // clocks for bits 279-240 of FIFO
input [DEPTH-1 :0] ff_clk_319_280, // clocks for bits 319-280 of FIFO
input ff_rst_n, // FIFO array reset
input [DWIDTH-1:0] wr_data, // FIFO write data bus
// Outputs
output reg [DEPTH-1 :0][DWIDTH-1:0] fifo_data_ff // FIFO data
);
// Bits 39-0
genvar i;
generate
for(i=0;i<DEPTH;i=i+1)
begin:fifo_data_39_0
always @(posedge ff_clk_39_0[i] or negedge ff_rst_n)
begin: fifo_data_39_0_register
if(!ff_rst_n)
fifo_data_ff[i][39:0] <= {40{1'b0}};
else
fifo_data_ff[i][39:0] <= wr_data[39:0];
end // block: fifo_data_39_0_register
end // block: fifo_data_39_0
endgenerate
// Bits 79-40
generate
for(i=0;i<DEPTH;i=i+1)
begin:fifo_data_79_40
always @(posedge ff_clk_79_40[i] or negedge ff_rst_n)
begin: fifo_data_79_40_register
if(!ff_rst_n)
fifo_data_ff[i][79:40] <= {40{1'b0}};
else
fifo_data_ff[i][79:40] <= wr_data[79:40];
end // block: fifo_data_79_40_register
end // block: fifo_data_79_40
endgenerate
// Bits 119-80
generate
for(i=0;i<DEPTH;i=i+1)
begin:fifo_data_119_80
always @(posedge ff_clk_119_80[i] or negedge ff_rst_n)
begin: fifo_data_119_80_register
if(!ff_rst_n)
fifo_data_ff[i][119:80] <= {40{1'b0}};
else
fifo_data_ff[i][119:80] <= wr_data[119:80];
end // block: fifo_data_119_80_register
end // block: fifo_data_119_80
endgenerate
// Bits 159-120
generate
for(i=0;i<DEPTH;i=i+1)
begin:fifo_data_159_120
always @(posedge ff_clk_159_120[i] or negedge ff_rst_n)
begin: fifo_data_159_120_register
if(!ff_rst_n)
fifo_data_ff[i][159:120] <= {40{1'b0}};
else
fifo_data_ff[i][159:120] <= wr_data[159:120];
end // block: fifo_data_159_120_register
end // block: fifo_data_159_120
endgenerate
// Bits 199-160
generate
for(i=0;i<DEPTH;i=i+1)
begin:fifo_data_199_160
always @(posedge ff_clk_199_160[i] or negedge ff_rst_n)
begin: fifo_data_199_160_register
if(!ff_rst_n)
fifo_data_ff[i][199:160] <= {40{1'b0}};
else
fifo_data_ff[i][199:160] <= wr_data[199:160];
end // block: fifo_data_199_160_register
end // block: fifo_data_199_160
endgenerate
// Bits 239-200
generate
for(i=0;i<DEPTH;i=i+1)
begin:fifo_data_239_200
always @(posedge ff_clk_239_200[i] or negedge ff_rst_n)
begin: fifo_data_239_200_register
if(!ff_rst_n)
fifo_data_ff[i][239:200] <= {40{1'b0}};
else
fifo_data_ff[i][239:200] <= wr_data[239:200];
end // block: fifo_data_239_200_register
end // block: fifo_data_239_200
endgenerate
// Bits 279-240
generate
for(i=0;i<DEPTH;i=i+1)
begin:fifo_data_279_240
always @(posedge ff_clk_279_240[i] or negedge ff_rst_n)
begin: fifo_data_279_240_register
if(!ff_rst_n)
fifo_data_ff[i][279:240] <= {40{1'b0}};
else
fifo_data_ff[i][279:240] <= wr_data[279:240];
end // block: fifo_data_279_240_register
end // block: fifo_data_279_240
endgenerate
// Bits 319-280
generate
for(i=0;i<DEPTH;i=i+1)
begin:fifo_data_319_280
always @(posedge ff_clk_319_280[i] or negedge ff_rst_n)
begin: fifo_data_319_280_register
if(!ff_rst_n)
fifo_data_ff[i][319:280] <= {40{1'b0}};
else
fifo_data_ff[i][319:280] <= wr_data[319:280];
end // block: fifo_data_319_280_register
end // block: fifo_data_319_280
endgenerate
endmodule // aib_adapt_fifo_mem |
module aib_clk_div (
// Inputs
input rst_n, // Asynchronous reset
input clk, // Clock
input scan_mode, // Scan mode
input clk_div_ld, // Clock divider enable from avalon interface
input clk_div_1_onehot, // Onehot enable for clock divided by 1
input clk_div_2_onehot, // Onehot enable for clock divided by 2
input clk_div_4_onehot, // Onehot enable for clock divided by 4
// Outputs
output clk_out, // Clock divided
output reg clk_div_ld_ack_ff // Clock divider load acknowledge
);
wire clk_div_ld_sync; // Clock divider enable in clk domain
wire clk_div_load; // Loads clock selection control
wire clk_div2; // Clock source divided by 2
wire clk_div4; // Clock source divided by 4
wire clk_div2_b; // Clock divided by 2 inverted
wire clk_div4_b; // Clock divided by 4 inverted
wire clk_div1_cg; // Clock divided by 1 after clock gating
wire clk_div2_cg; // Clock divided by 2 after clock gating
wire clk_div4_cg; // Clock divided by 4 after clock gating
wire div1_clk_en; // DIV1 clock enable
wire div2_clk_en ; // DIV2 clock enable
wire div4_clk_en; // DIV4 clock enable
reg clk_div_1_sel_ff; // Clock divided by 1 selection
reg clk_div_2_sel_ff; // Clock divided by 2 selection
reg clk_div_4_sel_ff; // Clock divided by 4 selection
// phcomp_wren Synchronizer
aib_bit_sync clk_div_load_sync
(
.clk (clk), // Clock of destination domain
.rst_n (rst_n), // Reset of destination domain
.data_in (clk_div_ld), // Input to be synchronized
.data_out (clk_div_ld_sync) // Synchronized output
);
assign clk_div_load = clk_div_ld_ack_ff ^ clk_div_ld_sync;
// Clock division update enable
always @(posedge clk or negedge rst_n)
begin: clk_div_ld_sync_register
if(!rst_n)
clk_div_ld_ack_ff <= 1'b0;
else
clk_div_ld_ack_ff <= clk_div_ld_sync;
end // block: clk_div_ld_sync_register
// Clock divided by 1 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_1_sel_register
if(!rst_n)
clk_div_1_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_1_sel_ff <= clk_div_1_onehot;
end // block: clk_div_1_sel_register
// Clock divided by 2 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_2_sel_register
if(!rst_n)
clk_div_2_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_2_sel_ff <= clk_div_2_onehot;
end // block: clk_div_2_sel_register
// Clock divided by 4 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_4_sel_register
if(!rst_n)
clk_div_4_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_4_sel_ff <= clk_div_4_onehot;
end // block: clk_div_4_sel_register
// Clock gating for DIV1 clock
clk_gate_cel cg_div_1( .clkout (clk_div1_cg),
.clk (clk),
.en (div1_clk_en),
.te (1'b0) );
assign div1_clk_en = clk_div_1_sel_ff | scan_mode;
assign div2_clk_en = clk_div_2_sel_ff & ~scan_mode;
assign div4_clk_en = clk_div_4_sel_ff & ~scan_mode;
// Clock gating for DIV2 clock
clk_gate_cel cg_div_2( .clkout (clk_div2_cg),
.clk (clk_div2),
.en (div2_clk_en),
.te (1'b0) );
// Clock gating for DIV4 clock
clk_gate_cel cg_div_4( .clkout (clk_div4_cg),
.clk (clk_div4),
.en (div4_clk_en),
.te (1'b0) );
// Flop to divide clock source by 2
clk_den_flop clk_div2_flop(
.clk (clk),
.d (clk_div2_b),
.den (1'b1),
.rb (rst_n),
.o (clk_div2)
);
// Clock divided by 2 inverted
clk_inv_cel clk_div2_inv(
.clkout (clk_div2_b),
.clk (clk_div2)
);
// Flop to divide clock source by 4
clk_den_flop clk_div4_flop(
.clk (clk),
.d (clk_div4_b),
.den (clk_div2_b),
.rb (rst_n),
.o (clk_div4)
);
// Clock divided by 4 inverted
clk_inv_cel clk_div4_inv(
.clkout (clk_div4_b),
.clk (clk_div4)
);
// ORED clock output
clk_or3_cel clk_or3_cel(
.clkout (clk_out),
.clk1 (clk_div1_cg),
.clk2 (clk_div2_cg),
.clk3 (clk_div4_cg)
);
endmodule // aib_clk_div |
module aib_fifo_and_sel #(
parameter DWIDTH = 80
)
(
output [DWIDTH-1:0] fifo_out_sel, // FIFO output ANDed with read enable
input fifo_rd_en, // FIFO read enable
input [DWIDTH-1:0] fifo_rd_in // FIFO data in write domain
);
// AND logic selects the asynchronous bus only when data is stable
assign fifo_out_sel = fifo_rd_in[DWIDTH-1:0] & {DWIDTH{fifo_rd_en}};
endmodule // aib_fifo_and_sel |
module aib_bus_sync
#(
parameter DWIDTH = 1'b1, // Data bus width
parameter [DWIDTH-1:0] RESET_VAL = {DWIDTH{1'h0}} // Reset value
)
(
// Inputs
input src_clk, // source clock
input dest_clk, // destination clock
input src_rst_n, // source async reset
input dest_rst_n, // destination async reset
input [DWIDTH-1:0] src_data, // Source data input
// Outputs
output reg[DWIDTH-1:0] dest_data_ff // destination data output
);
wire src_req_sync; // Data request in destination domain
wire if_ready; // Indicates CDC interface ready
wire dest_ack_sync; // Destination acknowledge
wire dest_sample; // Destination signal to sample source data
reg src_req_ff; // Source data request register
reg [DWIDTH-1:0] src_data_ff; // Source data register
reg dest_ack_ff; // Destination acknowledge register
//------------------------------------------------------------------------------
// Source Domain Logic
//------------------------------------------------------------------------------
// Data sample request
always @(posedge src_clk or negedge src_rst_n)
begin: src_req_register
if(!src_rst_n)
src_req_ff <= 1'b0;
else if(if_ready)
src_req_ff <= ~src_req_ff;
end // block: src_req_register
// Source data register
always @(posedge src_clk or negedge src_rst_n)
begin: src_data_register
if(!src_rst_n)
src_data_ff[DWIDTH-1:0] <= RESET_VAL;
else if(if_ready)
src_data_ff[DWIDTH-1:0] <= src_data[DWIDTH-1:0];
end // block: src_data_register
// Interace ready indication
assign if_ready = ~(src_req_ff ^ dest_ack_sync);
// Destination acknowledge synchronization
aib_bit_sync sync_ack_i(
// Inputs
.clk (src_clk), // clock
.rst_n (src_rst_n), // async reset
.data_in (dest_ack_ff), // data in
// Outputs
.data_out (dest_ack_sync) // data out
);
//------------------------------------------------------------------------------
// Source Domain Logic
//------------------------------------------------------------------------------
// Source request synchronization
aib_bit_sync sync_req_i(
// Inputs
.clk (dest_clk), // clock
.rst_n (dest_rst_n), // async reset
.data_in (src_req_ff), // data in
// Outputs
.data_out (src_req_sync)// data out
);
// Source acknowledge
always @(posedge dest_clk or negedge dest_rst_n)
begin: dest_ack_register
if(!dest_rst_n)
dest_ack_ff <= 1'b0;
else
dest_ack_ff <= src_req_sync;
end // block: dest_ack_register
// samples data in destination domain
assign dest_sample = src_req_sync ^ dest_ack_ff;
// Destination data
always @(posedge dest_clk or negedge dest_rst_n)
begin: dest_data_register
if(!dest_rst_n)
dest_data_ff[DWIDTH-1:0] <= RESET_VAL;
else if(dest_sample)
dest_data_ff[DWIDTH-1:0] <= src_data_ff[DWIDTH-1:0];
end // block: dest_data_register
endmodule // aib_bus_sync |
module aib_bs_clk_gating(
// Inputs
input jtag_clk, // JTAG clock
input jtag_capture_dr, // Capture data register
input jtag_tx_scanen_in, // JTAG TX scan enable
input i_scan_mode, // Scan mode
// Outputs
output tx_jtag_clk_g, // JATG clock gated for transmit shift register
output rx_jtag_clk_g // JATG clock gated for receive shift register
);
wire rx_jtag_clk_en; // RX JTAG clock enable
// RX JTAG clock enable
assign rx_jtag_clk_en = jtag_tx_scanen_in | jtag_capture_dr;
// TX JTAG clock gate
clk_gate_cel clk_gate_tx_jtag(
.clkout (tx_jtag_clk_g), // Clock gated
.clk (jtag_clk), // Clock input
.en (jtag_tx_scanen_in), // Clock enable
.te (i_scan_mode) // Test enable
); // TX JTAG clock gate
// RX JTAG clock gate
clk_gate_cel clk_gate_rx_jtag(
.clkout (rx_jtag_clk_g), // Clock gated
.clk (jtag_clk), // Clock input
.en (rx_jtag_clk_en), // Clock enable
.te (i_scan_mode) // Test enable
); // RX JTAG clock gate
endmodule |
module aib_fifo_rdata_buf #(
parameter DWIDTH = 80 // FIFO Input data width
)
(
// Output
output reg [DWIDTH-1:0] fifo_rdata_ff,
// Input
input [DWIDTH-1:0] fifo_rdata,
input rd_clk,
input rd_rst_n
);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(!rd_rst_n)
fifo_rdata_ff <= {DWIDTH{1'b0}};
else
fifo_rdata_ff <= fifo_rdata;
end
endmodule // aib_fifo_rdata_buf |
module aib_bscan (
input odat_asyn_aib, //async data RX from AIB
input async_data_adap, //async data TX from HSSI Adapter
input tx_async_en_adap, // TX asynchronous enable from Adapter
input jtag_tx_scanen_in, //JTAG shift DR, active high
input tx_jtag_clk_g, // Gated clock for TX shift register
input rx_jtag_clk_g, // Gated clock for RX shift register
input jtag_tx_scan_in, //JTAG TX data scan in
input jtag_mode_in, //JTAG mode select
input jtag_rstb_en, //reset_en from TAP
input jtag_rstb, //reset signal from TAP
input jtag_intest, //intest from TAP
output jtag_rx_scan_out, //JTAG TX scan chain output
output tx_async_en_aib, // TX asynchronous enable to AIB pad
output odat_asyn_adap, //async data RX to HSSI Adapter
output async_data_aib //async data TX to AIB
);
reg [1:0] tx_reg;
reg rx_reg;
reg rx_nreg;
wire [1:0] tx_shift;
wire [1:0] tx_intst;
wire rx_shift;
assign jtag_rx_scan_out = rx_nreg;
clk_mux async_data_aib_ckmux(
// Inputs
.clk1 (tx_reg[1]), // s=1
.clk2 (async_data_adap), // s=0
.s (jtag_mode_in),
// Outputs
.clkout (async_data_aib)
);
assign tx_async_en_aib = jtag_mode_in ? tx_reg[0] : tx_async_en_adap;
clk_mux odat_asyn_adap_ckmux(
// Inputs
.clk1 (rx_reg), // s=1
.clk2 (odat_asyn_aib), // s=0
.s (jtag_intest),
// Outputs
.clkout (odat_asyn_adap)
);
assign tx_shift[0] = (jtag_tx_scanen_in) ? tx_reg[1] : tx_intst[0];
clk_mux tx_shift_4_ckmux(
// Inputs
.clk1 (jtag_tx_scan_in), // s=1
.clk2 (tx_intst[1]), // s=0
.s (jtag_tx_scanen_in),
// Outputs
.clkout (tx_shift[1])
);
assign tx_intst[0] = (jtag_intest) ? tx_async_en_adap : tx_reg[0];
clk_mux tx_intst_4_ckmux(
// Inputs
.clk1 (async_data_adap), // s=1
.clk2 (tx_reg[1]), // s=0
.s (jtag_intest),
// Outputs
.clkout (tx_intst[1])
);
always @(posedge tx_jtag_clk_g)
begin
tx_reg <= tx_shift;
end
clk_mux rx_shift_0_ckmux(
// Inputs
.clk1 (tx_reg[0]), // s=1
.clk2 (odat_asyn_adap), // s=0
.s (jtag_tx_scanen_in),
// Outputs
.clkout (rx_shift)
);
always @(posedge rx_jtag_clk_g)
begin
rx_reg <= rx_shift;
end
always @(negedge rx_jtag_clk_g)
begin
rx_nreg <= rx_reg;
end
endmodule |
module aib_clk_div_dcs (
// Inputs
input rst_n, // Asynchronous reset
input clk, // Clock
input scan_mode, // Scan mode
input clk_div_ld, // Clock divider enable from avalon interface
input clk_div_1_onehot, // Onehot enable for clock divided by 1
input clk_div_2_onehot, // Onehot enable for clock divided by 2
input clk_div_4_onehot, // Onehot enable for clock divided by 4
input clk_div_8_onehot, // Onehot enable for clock divided by 8
input clk_div_16_onehot, // Onehot enable for clock divided by 16
input clk_div_32_onehot, // Onehot enable for clock divided by 32
input clk_div_64_onehot, // Onehot enable for clock divided by 64
input clk_div_128_onehot, // Onehot enable for clock divided by 128
input clk_div_256_onehot, // Onehot enable for clock divided by 256
// Outputs
output clk_out, // Clock divided
output reg clk_div_ld_ack_ff // Clock divider load acknowledge
);
wire clk_div_ld_sync; // Clock divider enable in clk domain
wire clk_div_load; // Loads clock selection control
wire clk_div2; // Clock source divided by 2
wire clk_div4; // Clock source divided by 4
wire clk_div8; // Clock source divided by 8
wire clk_div16; // Clock source divided by 16
wire clk_div32; // Clock source divided by 32
wire clk_div64; // Clock source divided by 64
wire clk_div128; // Clock source divided by 128
wire clk_div256; // Clock source divided by 256
wire clk_div2_b; // Clock divided by 2 inverted
wire clk_div4_b; // Clock divided by 4 inverted
wire clk_div8_b; // Clock divided by 8 inverted
wire clk_div16_b; // Clock divided by 16 inverted
wire clk_div32_b; // Clock divided by 32 inverted
wire clk_div64_b; // Clock divided by 64 inverted
wire clk_div128_b; // Clock divided by 128 inverted
wire clk_div256_b; // Clock divided by 256 inverted
wire clk_div1_cg; // Clock divided by 1 after clock gating
wire clk_div2_cg; // Clock divided by 2 after clock gating
wire clk_div4_cg; // Clock divided by 4 after clock gating
wire clk_div8_cg; // Clock divided by 8 after clock gating
wire clk_div16_cg; // Clock divided by 16 after clock gating
wire clk_div32_cg; // Clock divided by 32 after clock gating
wire clk_div64_cg; // Clock divided by 64 after clock gating
wire clk_div128_cg; // Clock divided by 128 after clock gating
wire clk_div256_cg; // Clock divided by 256 after clock gating
wire div1_clk_en; // Clock enable for clock divided by 1
wire div2_clk_en; // Clock enable for clock divided by 2
wire div4_clk_en; // Clock enable for clock divided by 4
wire div8_clk_en; // Clock enable for clock divided by 8
wire div16_clk_en; // Clock enable for clock divided by 16
wire div32_clk_en; // Clock enable for clock divided by 32
wire div64_clk_en; // Clock enable for clock divided by 64
wire div128_clk_en; // Clock enable for clock divided by 128
wire div256_clk_en; // Clock enable for clock divided by 256
wire clkout_div1_div2; // First OR level for clock div 1 and clock div 2
wire clkout_div4_div8; // First OR level for clock div 4 and clock div 8
wire clkout_div16_div32; // First OR level for clock div 16 and clock div 32
wire clkout_div64_div128; // First OR level for clock div 64 and clock div 128
wire clkout_div16_div128; // Second OR level for clock div 16 and clock div 128
wire clkout_div_1_8; // Second OR level for clock div1, div 2 and div 8
wire clkout_div_16_32; // Second OR level for clock div16
wire clkout_div_16_256; // Third OR level for clock div 16 and clock div 256
wire clk_div8_and_en; //den for DIV8 ciruit, AND of DIV2 qb signal and DIV4 qb signals
wire clk_div16_and_en; //den for DIV16 ciruit, AND of DIV2 qb signal, DIV4 qb signal and DIV8 qb signals
wire clk_div32_and_en; //den for DIV32 ciruit, AND of DIV2,4,8,16 qb signals
wire clk_div64_and_en; //den for DIV64 ciruit, AND of clk_div64_and_en_1, clk_div64_and_en_2
wire clk_div64_and_en_1; //den for DIV64 ciruit, AND of DIV2,4 qb signals
wire clk_div64_and_en_2; //den for DIV64 ciruit, AND of DIV8,16,32 qb signals
wire clk_div128_and_en; //den for DIV128 ciruit, AND of clk_div64_and_en_1,clk_div64_and_en_2
wire clk_div128_and_en_1; //den for DIV128 ciruit, AND of DIV2,4,8 qb signals
wire clk_div128_and_en_2; //den for DIV128 ciruit, AND of DIV16,32,64 qb signals
wire clk_div256_and_en; //den for DIV256 ciruit, AND of clk_div256_and_en_1, clk_div256_and_en_2, 128qb signals
wire clk_div256_and_en_1; //den for DIV256 ciruit, AND of DIV2,4,8 qb signals
wire clk_div256_and_en_2; //den for DIV256 ciruit, AND of DIV16,32,64 qb signals
reg clk_div_1_sel_ff; // Clock divided by 1 selection
reg clk_div_2_sel_ff; // Clock divided by 2 selection
reg clk_div_4_sel_ff; // Clock divided by 4 selection
reg clk_div_8_sel_ff; // Clock divided by 8 selection
reg clk_div_16_sel_ff; // Clock divided by 16 selection
reg clk_div_32_sel_ff; // Clock divided by 32 selection
reg clk_div_64_sel_ff; // Clock divided by 64 selection
reg clk_div_128_sel_ff; // Clock divided by 128 selection
reg clk_div_256_sel_ff; // Clock divided by 256 selection
// phcomp_wren Synchronizer
aib_bit_sync clk_div_load_sync
(
.clk (clk), // Clock of destination domain
.rst_n (rst_n), // Reset of destination domain
.data_in (clk_div_ld), // Input to be synchronized
.data_out (clk_div_ld_sync) // Synchronized output
);
assign clk_div_load = clk_div_ld_ack_ff ^ clk_div_ld_sync;
// Clock division update enable
always @(posedge clk or negedge rst_n)
begin: clk_div_ld_sync_register
if(!rst_n)
clk_div_ld_ack_ff <= 1'b0;
else
clk_div_ld_ack_ff <= clk_div_ld_sync;
end // block: clk_div_ld_sync_register
// Clock divided by 1 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_1_sel_register
if(!rst_n)
clk_div_1_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_1_sel_ff <= clk_div_1_onehot;
end // block: clk_div_1_sel_register
// Clock divided by 2 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_2_sel_register
if(!rst_n)
clk_div_2_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_2_sel_ff <= clk_div_2_onehot;
end // block: clk_div_2_sel_register
// Clock divided by 4 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_4_sel_register
if(!rst_n)
clk_div_4_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_4_sel_ff <= clk_div_4_onehot;
end // block: clk_div_4_sel_register
// Clock divided by 8 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_8_sel_register
if(!rst_n)
clk_div_8_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_8_sel_ff <= clk_div_8_onehot;
end // block: clk_div_8_sel_register
// Clock divided by 16 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_16_sel_register
if(!rst_n)
clk_div_16_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_16_sel_ff <= clk_div_16_onehot;
end // block: clk_div_16_sel_register
// Clock divided by 32 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_32_sel_register
if(!rst_n)
clk_div_32_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_32_sel_ff <= clk_div_32_onehot;
end // block: clk_div_32_sel_register
// Clock divided by 64 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_64_sel_register
if(!rst_n)
clk_div_64_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_64_sel_ff <= clk_div_64_onehot;
end // block: clk_div_64_sel_register
// Clock divided by 128 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_128_sel_register
if(!rst_n)
clk_div_128_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_128_sel_ff <= clk_div_128_onehot;
end // block: clk_div_128_sel_register
// Clock divided by 256 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_256_sel_register
if(!rst_n)
clk_div_256_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_256_sel_ff <= clk_div_256_onehot;
end // block: clk_div_256_sel_register
// Clock gating for DIV1 clock
clk_gate_cel cg_div_1( .clkout (clk_div1_cg),
.clk (clk),
.en (div1_clk_en),
.te (1'b0) );
assign div1_clk_en = clk_div_1_sel_ff | scan_mode;
assign div2_clk_en = clk_div_2_sel_ff & ~scan_mode;
assign div4_clk_en = clk_div_4_sel_ff & ~scan_mode;
assign div8_clk_en = clk_div_8_sel_ff & ~scan_mode;
assign div16_clk_en = clk_div_16_sel_ff & ~scan_mode;
assign div32_clk_en = clk_div_32_sel_ff & ~scan_mode;
assign div64_clk_en = clk_div_64_sel_ff & ~scan_mode;
assign div128_clk_en = clk_div_128_sel_ff & ~scan_mode;
assign div256_clk_en = clk_div_256_sel_ff & ~scan_mode;
// Clock gating for DIV2 clock
clk_gate_cel cg_div_2( .clkout (clk_div2_cg),
.clk (clk_div2),
.en (div2_clk_en),
.te (1'b0) );
// Clock gating for DIV4 clock
clk_gate_cel cg_div_4( .clkout (clk_div4_cg),
.clk (clk_div4),
.en (div4_clk_en),
.te (1'b0) );
// Clock gating for DIV8 clock
clk_gate_cel cg_div_8( .clkout (clk_div8_cg),
.clk (clk_div8),
.en (div8_clk_en),
.te (1'b0) );
// Clock gating for DIV16 clock
clk_gate_cel cg_div_16( .clkout (clk_div16_cg),
.clk (clk_div16),
.en (div16_clk_en),
.te (1'b0) );
// Clock gating for DIV32 clock
clk_gate_cel cg_div_32( .clkout (clk_div32_cg),
.clk (clk_div32),
.en (div32_clk_en),
.te (1'b0) );
// Clock gating for DIV64 clock
clk_gate_cel cg_div_64( .clkout (clk_div64_cg),
.clk (clk_div64),
.en (div64_clk_en),
.te (1'b0) );
// Clock gating for DIV128 clock
clk_gate_cel cg_div_128( .clkout (clk_div128_cg),
.clk (clk_div128),
.en (div128_clk_en),
.te (1'b0) );
// Clock gating for DIV256 clock
clk_gate_cel cg_div_256( .clkout (clk_div256_cg),
.clk (clk_div256),
.en (div256_clk_en),
.te (1'b0) );
// Flop to divide clock source by 2
clk_den_flop clk_div2_flop(
.clk (clk),
.d (clk_div2_b),
.den (1'b1),
.rb (rst_n),
.o (clk_div2)
);
// Clock divided by 2 inverted
clk_inv_cel clk_div2_inv(
.clkout (clk_div2_b),
.clk (clk_div2)
);
// Flop to divide clock source by 4
clk_den_flop clk_div4_flop(
.clk (clk),
.d (clk_div4_b),
.den (clk_div2_b),
.rb (rst_n),
.o (clk_div4)
);
// Clock divided by 4 inverted
clk_inv_cel clk_div4_inv(
.clkout (clk_div4_b),
.clk (clk_div4)
);
// Flop to divide clock source by 8
clk_den_flop clk_div8_flop(
.clk (clk),
.d (clk_div8_b),
.den (clk_div8_and_en),
.rb (rst_n),
.o (clk_div8)
);
// Clock divided by 8 inverted
clk_inv_cel clk_div8_inv(
.clkout (clk_div8_b),
.clk (clk_div8)
);
// AND for den signal of div8 circuit
clk_and2_cel clk_and2_div8(
.clkout (clk_div8_and_en), // AND output
.clk1 (clk_div4_b), // clock 1
.clk2 (clk_div2_b) // clock 2
);
// Flop to divide clock source by 16
clk_den_flop clk_div16_flop(
.clk (clk),
.d (clk_div16_b),
.den (clk_div16_and_en),
.rb (rst_n),
.o (clk_div16)
);
// Clock divided by 16 inverted
clk_inv_cel clk_div16_inv(
.clkout (clk_div16_b),
.clk (clk_div16)
);
// AND for den signal of div16 circuit
clk_and3_cel clk_and3_div16(
.clkout (clk_div16_and_en), // AND output
.clk1 (clk_div2_b), // clock 1
.clk2 (clk_div4_b), // clock 2
.clk3 (clk_div8_b) // clock 3
);
// Flop to divide clock source by 32
clk_den_flop clk_div32_flop(
.clk (clk),
.d (clk_div32_b),
.den (clk_div32_and_en),
.rb (rst_n),
.o (clk_div32)
);
// Clock divided by 32 inverted
clk_inv_cel clk_div32_inv(
.clkout (clk_div32_b),
.clk (clk_div32)
);
// AND for den signal of div32 circuit
clk_and4_cel clk_and4_div32(
.clkout (clk_div32_and_en), // AND output
.clk1 (clk_div2_b), // clock 1
.clk2 (clk_div4_b), // clock 2
.clk3 (clk_div8_b), // clock 3
.clk4 (clk_div16_b) // clock 4
);
// Flop to divide clock source by 64
clk_den_flop clk_div64_flop(
.clk (clk),
.d (clk_div64_b),
.den (clk_div64_and_en),
.rb (rst_n),
.o (clk_div64)
);
// Clock divided by 64 inverted
clk_inv_cel clk_div64_inv(
.clkout (clk_div64_b),
.clk (clk_div64)
);
// AND for den signal of div64 circuit
clk_and2_cel clk_and2_div64_1(
.clkout (clk_div64_and_en_1), // AND output
.clk1 (clk_div2_b), // clock 1
.clk2 (clk_div4_b) // clock 2
);
// AND for den signal of div64 circuit
clk_and3_cel clk_and3_div64_2(
.clkout (clk_div64_and_en_2), // AND output
.clk1 (clk_div8_b), // clock 1
.clk2 (clk_div16_b), // clock 2
.clk3 (clk_div32_b) // clock 3
);
// AND for den signal of div64 circuit
clk_and2_cel clk_and2_div64(
.clkout (clk_div64_and_en), // AND output
.clk1 (clk_div64_and_en_1), // clock 1
.clk2 (clk_div64_and_en_2) // clock 2
);
// Flop to divide clock source by 128
clk_den_flop clk_div128_flop(
.clk (clk),
.d (clk_div128_b),
.den (clk_div128_and_en),
.rb (rst_n),
.o (clk_div128)
);
// Clock divided by 128 inverted
clk_inv_cel clk_div128_inv(
.clkout (clk_div128_b),
.clk (clk_div128)
);
// AND for den signal of div128 circuit
clk_and3_cel clk_and3_div128_1(
.clkout (clk_div128_and_en_1), // AND output
.clk1 (clk_div2_b), // clock 1
.clk2 (clk_div4_b), // clock 2
.clk3 (clk_div8_b) // clock 2
);
// AND for den signal of div128 circuit
clk_and3_cel clk_and3_div128_2(
.clkout (clk_div128_and_en_2), // AND output
.clk1 (clk_div16_b), // clock 1
.clk2 (clk_div32_b), // clock 2
.clk3 (clk_div64_b) // clock 3
);
// AND for den signal of div128 circuit
clk_and2_cel clk_and2_div128(
.clkout (clk_div128_and_en), // AND output
.clk1 (clk_div128_and_en_1), // clock 1
.clk2 (clk_div128_and_en_2) // clock 2
);
// Flop to divide clock source by 256
clk_den_flop clk_div256_flop(
.clk (clk),
.d (clk_div256_b),
.den (clk_div256_and_en),
.rb (rst_n),
.o (clk_div256)
);
// Clock divided by 256 inverted
clk_inv_cel clk_div256_inv(
.clkout (clk_div256_b),
.clk (clk_div256)
);
// AND for den signal of div256 circuit
clk_and3_cel clk_and3_div256_1(
.clkout (clk_div256_and_en_1), // AND output
.clk1 (clk_div2_b), // clock 1
.clk2 (clk_div4_b), // clock 2
.clk3 (clk_div8_b) // clock 3
);
// AND for den signal of div256 circuit
clk_and3_cel clk_and3_div256_2(
.clkout (clk_div256_and_en_2), // AND output
.clk1 (clk_div16_b), // clock 1
.clk2 (clk_div32_b), // clock 2
.clk3 (clk_div64_b) // clock 3
);
// AND for den signal of div256 circuit
clk_and3_cel clk_and3_div256(
.clkout (clk_div256_and_en), // AND output
.clk1 (clk_div256_and_en_1), // clock 1
.clk2 (clk_div256_and_en_2), // clock 2
.clk3 (clk_div128_b) // clock 3
);
// First OR level for clk div 1 and clk div 2
clk_or2_cel clk_or2_div1_div2_1(
.clkout (clkout_div1_div2), // OR output
.clk1 (clk_div1_cg), // clock 1
.clk2 (clk_div2_cg) // clock 2
);
// First OR level for clk div 4 and clk div 8
clk_or2_cel clk_or2_div4_div8_1(
.clkout (clkout_div4_div8), // OR output
.clk1 (clk_div4_cg), // clock 1
.clk2 (clk_div8_cg) // clock 2
);
// First OR level for dclk div 16 and clk div 32
clk_or2_cel clk_or2_div16_div32_1(
.clkout (clkout_div16_div32), // OR output
.clk1 (clk_div16_cg), // clock 1
.clk2 (clk_div32_cg) // clock 2
);
// Second OR level for clock div 1, 2 ,4 and 8
clk_or2_cel clk_or2_level2_1(
.clkout (clkout_div_1_8), // OR output
.clk1 (clkout_div1_div2), // clock 1
.clk2 (clkout_div4_div8) // clock 2
);
// Second OR level 2 for clock div 16 and clock div 32
clk_or2_cel clk_or2_level2_2(
.clkout (clkout_div_16_32), // OR output
.clk1 (clkout_div16_div32), // clock 1
.clk2 (1'b0) // clock 2
);
// Level 4 OR
clk_or2_cel clk_or2_level4(
.clkout (clk_out), // OR output
.clk1 (clkout_div_1_8), // clock 1
.clk2 (clkout_div_16_256) // clock 2
);
// First OR level for dclk div64 and clk div128
clk_or2_cel clk_or2_div64_div128_1(
.clkout (clkout_div64_div128), // OR output
.clk1 (clk_div64_cg), // clock 1
.clk2 (clk_div128_cg) // clock 2
);
// Second OR level for dclk div16 and clk div128
clk_or2_cel clk_or2_div16_div128_2(
.clkout (clkout_div16_div128), // OR output
.clk1 (clkout_div_16_32), // clock 1
.clk2 (clkout_div64_div128) // clock 2
);
//Third OR level 2 for clock div 16 and 256
clk_or2_cel clk_or2_level3(
.clkout (clkout_div_16_256), // OR output
.clk1 (clkout_div16_div128), // clock 1
.clk2 (clk_div256_cg) // clock 2
);
endmodule // aib_clk_div_dcs |
module aib_clk_div_roffcal (
// Inputs
input rst_n, // Asynchronous reset
input clk, // Clock
input scan_mode, // Scan mode
input clk_div_ld, // Clock divider enable from avalon interface
input clk_div_1_onehot, // Onehot enable for clock divided by 1
input clk_div_2_onehot, // Onehot enable for clock divided by 2
input clk_div_4_onehot, // Onehot enable for clock divided by 4
input clk_div_8_onehot, // Onehot enable for clock divided by 8
input clk_div_16_onehot, // Onehot enable for clock divided by 16
input clk_div_32_onehot, // Onehot enable for clock divided by 32
input clk_div_64_onehot, // Onehot enable for clock divided by 64
// Outputs
output clk_out, // Clock divided
output reg clk_div_ld_ack_ff // Clock divider load acknowledge
);
wire clk_div_ld_sync; // Clock divider enable in clk domain
wire clk_div_load; // Loads clock selection control
wire clk_div2; // Clock source divided by 2
wire clk_div4; // Clock source divided by 4
wire clk_div8; // Clock source divided by 8
wire clk_div16; // Clock source divided by 16
wire clk_div32; // Clock source divided by 32
wire clk_div64; // Clock source divided by 64
wire clk_div2_b; // Clock divided by 2 inverted
wire clk_div4_b; // Clock divided by 4 inverted
wire clk_div8_b; // Clock divided by 8 inverted
wire clk_div16_b; // Clock divided by 16 inverted
wire clk_div32_b; // Clock divided by 32 inverted
wire clk_div64_b; // Clock divided by 64 inverted
wire clk_div1_cg; // Clock divided by 1 after clock gating
wire clk_div2_cg; // Clock divided by 2 after clock gating
wire clk_div4_cg; // Clock divided by 4 after clock gating
wire clk_div8_cg; // Clock divided by 8 after clock gating
wire clk_div16_cg; // Clock divided by 16 after clock gating
wire clk_div32_cg; // Clock divided by 32 after clock gating
wire clk_div64_cg; // Clock divided by 64 after clock gating
wire div1_clk_en; // Clock enable for clock divided by 1
wire div2_clk_en; // Clock enable for clock divided by 2
wire div4_clk_en; // Clock enable for clock divided by 4
wire div8_clk_en; // Clock enable for clock divided by 8
wire div16_clk_en; // Clock enable for clock divided by 16
wire div32_clk_en; // Clock enable for clock divided by 32
wire div64_clk_en; // Clock enable for clock divided by 64
wire clkout_div1_div2; // First OR level for clock div 1 and clock div 2
wire clkout_div1_div8; // First OR level for clock div 1 and clock div 2
wire clkout_div4_div8; // First OR level for clock div 4 and clock div 8
wire clkout_div16_div32; // First OR level for clock div 16 and clock div 32
wire clkout_div_16_64; // First OR level for clock div 16 and clock div 64
wire clk_div8_and_en; //den for DIV8 ciruit, AND of DIV2 qb signal and DIV4 qb signal
wire clk_div16_and_en; //den for DIV16 ciruit, AND of DIV2,4,8 qb signal
wire clk_div32_and_en; //den for DIV32 ciruit, AND of DIV2,4,8,16 qb signal
wire clk_div64_and_en; //den for DIV64 ciruit, AND of DIV2,4,8,16,32 qb signal
wire clk_div64_and_en_1; //den for DIV64 ciruit, AND of DIV2,4 qb signal
wire clk_div64_and_en_2; //den for DIV64 ciruit, AND of DIV8,16,32 qb signal
reg clk_div_1_sel_ff; // Clock divided by 1 selection
reg clk_div_2_sel_ff; // Clock divided by 2 selection
reg clk_div_4_sel_ff; // Clock divided by 4 selection
reg clk_div_8_sel_ff; // Clock divided by 8 selection
reg clk_div_16_sel_ff; // Clock divided by 16 selection
reg clk_div_32_sel_ff; // Clock divided by 32 selection
reg clk_div_64_sel_ff; // Clock divided by 64 selection
// phcomp_wren Synchronizer
aib_bit_sync clk_div_load_sync
(
.clk (clk), // Clock of destination domain
.rst_n (rst_n), // Reset of destination domain
.data_in (clk_div_ld), // Input to be synchronized
.data_out (clk_div_ld_sync) // Synchronized output
);
assign clk_div_load = clk_div_ld_ack_ff ^ clk_div_ld_sync;
// Clock division update enable
always @(posedge clk or negedge rst_n)
begin: clk_div_ld_sync_register
if(!rst_n)
clk_div_ld_ack_ff <= 1'b0;
else
clk_div_ld_ack_ff <= clk_div_ld_sync;
end // block: clk_div_ld_sync_register
// Clock divided by 1 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_1_sel_register
if(!rst_n)
clk_div_1_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_1_sel_ff <= clk_div_1_onehot;
end // block: clk_div_1_sel_register
// Clock divided by 2 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_2_sel_register
if(!rst_n)
clk_div_2_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_2_sel_ff <= clk_div_2_onehot;
end // block: clk_div_2_sel_register
// Clock divided by 4 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_4_sel_register
if(!rst_n)
clk_div_4_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_4_sel_ff <= clk_div_4_onehot;
end // block: clk_div_4_sel_register
// Clock divided by 8 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_8_sel_register
if(!rst_n)
clk_div_8_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_8_sel_ff <= clk_div_8_onehot;
end // block: clk_div_8_sel_register
// Clock divided by 16 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_16_sel_register
if(!rst_n)
clk_div_16_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_16_sel_ff <= clk_div_16_onehot;
end // block: clk_div_16_sel_register
// Clock divided by 32 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_32_sel_register
if(!rst_n)
clk_div_32_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_32_sel_ff <= clk_div_32_onehot;
end // block: clk_div_32_sel_register
// Clock divided by 64 selection register
always @(posedge clk or negedge rst_n)
begin: clk_div_64_sel_register
if(!rst_n)
clk_div_64_sel_ff <= 1'b0;
else if(clk_div_load)
clk_div_64_sel_ff <= clk_div_64_onehot;
end // block: clk_div_64_sel_register
// Clock gating for DIV1 clock
clk_gate_cel cg_div_1( .clkout (clk_div1_cg),
.clk (clk),
.en (div1_clk_en),
.te (1'b0) );
assign div1_clk_en = clk_div_1_sel_ff | scan_mode;
assign div2_clk_en = clk_div_2_sel_ff & ~scan_mode;
assign div4_clk_en = clk_div_4_sel_ff & ~scan_mode;
assign div8_clk_en = clk_div_8_sel_ff & ~scan_mode;
assign div16_clk_en = clk_div_16_sel_ff & ~scan_mode;
assign div32_clk_en = clk_div_32_sel_ff & ~scan_mode;
assign div64_clk_en = clk_div_64_sel_ff & ~scan_mode;
// Clock gating for DIV2 clock
clk_gate_cel cg_div_2( .clkout (clk_div2_cg),
.clk (clk_div2),
.en (div2_clk_en),
.te (1'b0) );
// Clock gating for DIV4 clock
clk_gate_cel cg_div_4( .clkout (clk_div4_cg),
.clk (clk_div4),
.en (div4_clk_en),
.te (1'b0) );
// Clock gating for DIV8 clock
clk_gate_cel cg_div_8( .clkout (clk_div8_cg),
.clk (clk_div8),
.en (div8_clk_en),
.te (1'b0) );
// Clock gating for DIV16 clock
clk_gate_cel cg_div_16( .clkout (clk_div16_cg),
.clk (clk_div16),
.en (div16_clk_en),
.te (1'b0) );
// Clock gating for DIV32 clock
clk_gate_cel cg_div_32( .clkout (clk_div32_cg),
.clk (clk_div32),
.en (div32_clk_en),
.te (1'b0) );
// Clock gating for DIV64 clock
clk_gate_cel cg_div_64( .clkout (clk_div64_cg),
.clk (clk_div64),
.en (div64_clk_en),
.te (1'b0) );
// Flop to divide clock source by 2
clk_den_flop clk_div2_flop(
.clk (clk),
.d (clk_div2_b),
.den (1'b1),
.rb (rst_n),
.o (clk_div2)
);
// Clock divided by 2 inverted
clk_inv_cel clk_div2_inv(
.clkout (clk_div2_b),
.clk (clk_div2)
);
// Flop to divide clock source by 4
clk_den_flop clk_div4_flop(
.clk (clk),
.d (clk_div4_b),
.den (clk_div2_b),
.rb (rst_n),
.o (clk_div4)
);
// Clock divided by 4 inverted
clk_inv_cel clk_div4_inv(
.clkout (clk_div4_b),
.clk (clk_div4)
);
// Flop to divide clock source by 8
clk_den_flop clk_div8_flop(
.clk (clk),
.d (clk_div8_b),
.den (clk_div8_and_en),
.rb (rst_n),
.o (clk_div8)
);
// Clock divided by 8 inverted
clk_inv_cel clk_div8_inv(
.clkout (clk_div8_b),
.clk (clk_div8)
);
// AND for den signal of div8 circuit
clk_and2_cel clk_and2_div8(
.clkout (clk_div8_and_en), // AND output
.clk1 (clk_div4_b), // clock 1
.clk2 (clk_div2_b) // clock 2
);
// Flop to divide clock source by 16
clk_den_flop clk_div16_flop(
.clk (clk),
.d (clk_div16_b),
.den (clk_div16_and_en),
.rb (rst_n),
.o (clk_div16)
);
// Clock divided by 16 inverted
clk_inv_cel clk_div16_inv(
.clkout (clk_div16_b),
.clk (clk_div16)
);
// AND for den signal of div32 circuit
clk_and3_cel clk_and3_div16(
.clkout (clk_div16_and_en), // AND output
.clk1 (clk_div4_b), // clock 1
.clk2 (clk_div2_b), // clock 2
.clk3 (clk_div8_b) // clock 3
);
// Flop to divide clock source by 32
clk_den_flop clk_div32_flop(
.clk (clk),
.d (clk_div32_b),
.den (clk_div32_and_en),
.rb (rst_n),
.o (clk_div32)
);
// Clock divided by 16 inverted
clk_inv_cel clk_div32_inv(
.clkout (clk_div32_b),
.clk (clk_div32)
);
// AND for den signal of div32 circuit
clk_and4_cel clk_and4_div32(
.clkout (clk_div32_and_en), // AND output
.clk1 (clk_div4_b), // clock 1
.clk2 (clk_div2_b), // clock 2
.clk3 (clk_div8_b), // clock 3
.clk4 (clk_div16_b) // clock 4
);
// Flop to divide clock source by 64
clk_den_flop clk_div64_flop(
.clk (clk),
.d (clk_div64_b),
.den (clk_div64_and_en),
.rb (rst_n),
.o (clk_div64)
);
// Clock divided by 64 inverted
clk_inv_cel clk_div64_inv(
.clkout (clk_div64_b),
.clk (clk_div64)
);
// AND for den signal of div64 circuit
clk_and2_cel clk_and2_div64_1(
.clkout (clk_div64_and_en_1), // AND output
.clk1 (clk_div2_b), // clock 1
.clk2 (clk_div4_b) // clock 2
);
// AND for den signal of div64 circuit
clk_and3_cel clk_and3_div64_2(
.clkout (clk_div64_and_en_2), // AND output
.clk1 (clk_div8_b), // clock 1
.clk2 (clk_div16_b), // clock 2
.clk3 (clk_div32_b) // clock 3
);
// AND for den signal of div64 circuit
clk_and2_cel clk_and2_div64(
.clkout (clk_div64_and_en), // AND output
.clk1 (clk_div64_and_en_1), // clock 1
.clk2 (clk_div64_and_en_2) // clock 2
);
// First OR level for clk div 1 and clk div 2
clk_or2_cel clk_or2_div1_div2_1(
.clkout (clkout_div1_div2), // OR output
.clk1 (clk_div1_cg), // clock 1
.clk2 (clk_div2_cg) // clock 2
);
// First OR level for clk div 4 and clk div 8
clk_or2_cel clk_or2_div4_div8_1(
.clkout (clkout_div4_div8), // OR output
.clk1 (clk_div4_cg), // clock 1
.clk2 (clk_div8_cg) // clock 2
);
// First OR level for dclk div 16 and clk div 32
clk_or2_cel clk_or2_div16_div32_1(
.clkout (clkout_div16_div32), // OR output
.clk1 (clk_div16_cg), // clock 1
.clk2 (clk_div32_cg) // clock 2
);
// Second OR level 2 for clock div 16 and clock div 64
clk_or2_cel clk_or2_level2_2(
.clkout (clkout_div_16_64), // OR output
.clk1 (clkout_div16_div32), // clock 1
.clk2 (clk_div64_cg) // clock 2
);
// Second OR level 1 for clock div 1, 2 ,4 and 8
clk_or2_cel clk_or2_level2_1(
.clkout (clkout_div1_div8), // OR output
.clk1 (clkout_div1_div2), // clock 1
.clk2 (clkout_div4_div8) // clock 2
);
// Second OR level 1 for clock div 1, 2 ,4 and 8
clk_or2_cel i_clk_out(
.clkout (clk_out), // OR output
.clk1 (clkout_div1_div8), // clock 1
.clk2 (clkout_div_16_64) // clock 2
);
endmodule // aib_clk_div_roffcal |
module rx_offset_cal(
input sys_clk,
input rst_n,
input start_cal,
input cal_data,
output reg cal_done,
output reg [4:0]offs_cal_code
);
parameter START = 3'b000,
UP_COUNT = 3'b001,
COUNT_ROLL = 3'b010,
DOWN_COUNT = 3'b011,
STOP = 3'b100;
`ifdef CAL_CODE_CNT
localparam CAL_CODE_CNT = `CAL_CODE_CNT;
`else
localparam CAL_CODE_CNT = 5'd31;// Calibration count
`endif
//1,2,4,8,(Need to insatntiate clock divider)
//00-DIV1
//01-DIV2
//10-DIV4
//11-DIV8
reg [2:0] offset_curst, offset_nxst;
reg [4:0] edge_detect_up_value, edge_detect_down_value;
reg [1:0] comp_data;
reg [5:0] sum;
wire cal_data_sync;
// Calibration data synchronized
aib_bit_sync cal_data_sync_i
(
.clk (sys_clk), // Clock of destination domain
.rst_n (1'b1), // Reset of destination domain
.data_in (cal_data), // Input to be synchronized
.data_out (cal_data_sync) // Synchronized output
);
always@(posedge sys_clk or negedge rst_n)
begin
if(!rst_n)
offset_curst[2:0] <= 3'b000;
else
offset_curst[2:0] <= offset_nxst[2:0];
end
always@(posedge sys_clk or negedge rst_n)
if(!rst_n)
begin
edge_detect_up_value <= 5'b0_0000;
edge_detect_down_value <= 5'b0_0000;
cal_done <= 1'b0;
offs_cal_code <= 4'b0000;
comp_data <= 2'b00;
sum <= 5'b0_0000;
end
else
begin
case(offset_curst)
START : begin
offs_cal_code <= 5'b0_0000;
comp_data <= 2'b00;
cal_done <= 1'b0;
sum <= 5'b0_0000;
end
UP_COUNT : begin
comp_data <= {comp_data[0], cal_data_sync};
if(comp_data[0] != comp_data[1])
edge_detect_up_value[4:0] <= offs_cal_code[4:0]-1'b1;
else
edge_detect_up_value[4:0] <= edge_detect_up_value[4:0];
offs_cal_code <= offs_cal_code + 1'b1;
end
COUNT_ROLL : begin
offs_cal_code[4:0] <= CAL_CODE_CNT[4:0];
end
DOWN_COUNT : begin
comp_data <= {comp_data[0], cal_data_sync};
if(comp_data[0] != comp_data[1])
edge_detect_down_value[4:0] <= offs_cal_code[4:0]+1'b1;
else
edge_detect_down_value[4:0] <= edge_detect_down_value[4:0];
if(offs_cal_code == 5'b0_0000)
offs_cal_code <= 5'b0_0000;
else
offs_cal_code <= offs_cal_code - 1'b1;
end
STOP : begin
sum <= edge_detect_up_value + edge_detect_down_value;
offs_cal_code <= sum >> 1;
cal_done <= 1'b1;
end
default : begin
offs_cal_code <= 5'b0_0000;
comp_data <= 2'b00;
sum <= 5'b0_0000;
end
endcase
end
always@(*)
begin
offset_nxst = 3'b000;
case(offset_curst)
START : begin
if(start_cal)
offset_nxst = UP_COUNT;
else
offset_nxst = START;
end
UP_COUNT : begin
if(offs_cal_code[4:0] == CAL_CODE_CNT[4:0])
offset_nxst = COUNT_ROLL;
else
offset_nxst = UP_COUNT;
end
COUNT_ROLL : begin
if(offs_cal_code[4:0] == CAL_CODE_CNT[4:0])
offset_nxst = DOWN_COUNT;
else
offset_nxst = COUNT_ROLL;
end
DOWN_COUNT : begin
if(offs_cal_code == 5'd0)
offset_nxst = STOP;
else
offset_nxst = DOWN_COUNT;
end
STOP : begin
if(!start_cal)
offset_nxst = START;
else
offset_nxst = STOP;
end
default : begin
if(start_cal)
offset_nxst = UP_COUNT;
else
offset_nxst = START;
end
endcase
end
endmodule |
module rx_offset_cal_fsm #(parameter DATAWIDTH = 44)
(
input sys_clk,
input rst_n,
input rx_offset_ovrd_sel,
input rx_offset_cal_done_ovrd,
input [4:0]rx_offset_cal_code_ovrd,
input start_cal,
input [(2*DATAWIDTH)-1:0]ana_rxdata,
input scan_mode, // Scan mode
input clk_div_ld, // Clock divider enable from avalon interface
input clk_div_1_onehot, // Onehot enable for clock divided by 1
input clk_div_2_onehot, // Onehot enable for clock divided by 2
input clk_div_4_onehot, // Onehot enable for clock divided by 4
input clk_div_8_onehot, // Onehot enable for clock divided by 8
output wire cal_done,
output wire [(2*DATAWIDTH)-1:0][4:0]offs_cal_code,
output wire rxoffset_clk_div_ld_ack_ff
);
wire [(2*DATAWIDTH)-1:0] cal_done_int;
wire sys_div_clk;
wire [(2*DATAWIDTH)-1:0][4:0] offs_cal_code_intr;
wire [(2*DATAWIDTH)-1:0][4:0] offs_cal_code_pre;
genvar i;
//Data Muxing b/w Register Data and internal logic data
generate
for(i=0;i<(2*DATAWIDTH);i=i+1)
begin: offs_cal_code_pre_gen
assign offs_cal_code_pre[i] = rx_offset_ovrd_sel ? rx_offset_cal_code_ovrd[4:0] : offs_cal_code_intr[i];
end
endgenerate // block: offs_cal_code_pre_gen
generate
for(i=0;i<(2*DATAWIDTH);i=i+1)
begin: offs_cal_code_gen
assign offs_cal_code[i][4:0] = scan_mode ? 5'h0 : offs_cal_code_pre[i];
end // block: offs_cal_code_gen
endgenerate
assign cal_done = rx_offset_ovrd_sel ? rx_offset_cal_done_ovrd : (&cal_done_int);
//==============================
//Clock Divider for Div-1,2,4,8
//==============================
aib_clk_div_roffcal i_aib_clk_div_roffcal(
.rst_n(rst_n),
.clk(sys_clk),
.scan_mode(scan_mode),
.clk_div_ld(clk_div_ld),
.clk_div_1_onehot(clk_div_1_onehot),
.clk_div_2_onehot(clk_div_2_onehot),
.clk_div_4_onehot(clk_div_4_onehot),
.clk_div_8_onehot(clk_div_8_onehot),
.clk_out(sys_div_clk),
.clk_div_ld_ack_ff(rxoffset_clk_div_ld_ack_ff)
);
/*======================================
==========Instantiation of Offset_cal===
========================================*/
generate
for(i=0;i<88;i=i+1)
begin: offset_cal_inst_gen
offset_cal i_offset_cal(
.sys_clk(sys_div_clk),
.rst_n(rst_n),
.start_cal(start_cal),
.cal_data(ana_rxdata[i]),
.cal_done(cal_done_int[i]),
.offs_cal_code(offs_cal_code_intr[i][4:0])
);
end // block: offset_cal_inst_gen
endgenerate
endmodule |
module offset_cal(
input sys_clk,
input rst_n,
input start_cal,
input cal_data,
output reg cal_done,
output reg [4:0]offs_cal_code
);
parameter START = 3'b000,
UP_COUNT = 3'b001,
COUNT_ROLL = 3'b010,
DOWN_COUNT = 3'b011,
STOP = 3'b100;
reg [2:0] offset_curst, offset_nxst;
reg [4:0] edge_detect_up_value, edge_detect_down_value;
reg [1:0] comp_data;
reg [5:0] sum;
always@(posedge sys_clk or negedge rst_n)
begin
if(!rst_n)
offset_curst[2:0] <= 3'b000;
else
offset_curst[2:0] <= offset_nxst[2:0];
end
always@(posedge sys_clk or negedge rst_n)
if(!rst_n)
begin
edge_detect_up_value <= 5'b0_0000;
edge_detect_down_value <= 5'b0_0000;
cal_done <= 1'b0;
offs_cal_code <= 4'b0000;
end
else
begin
case(offset_curst)
START : begin
offs_cal_code <= 5'b0_0000;
comp_data <= 2'b00;
sum <= 5'b0_0000;
end
UP_COUNT : begin
comp_data <= {comp_data[0], cal_data};
if(comp_data[0] != comp_data[1])
edge_detect_up_value[4:0] <= offs_cal_code[4:0]-1'b1;
else
edge_detect_up_value[4:0] <= edge_detect_up_value[4:0];
offs_cal_code <= offs_cal_code + 1'b1;
end
COUNT_ROLL : begin
offs_cal_code <= 5'd31;
end
DOWN_COUNT : begin
comp_data <= {comp_data[0], cal_data};
if(comp_data[0] != comp_data[1])
edge_detect_down_value[4:0] <= offs_cal_code[4:0]+1'b1;
else
edge_detect_down_value[4:0] <= edge_detect_down_value[4:0];
if(offs_cal_code == 5'b0_0000)
offs_cal_code <= 5'b0_0000;
else
offs_cal_code <= offs_cal_code - 1'b1;
end
STOP : begin
sum <= edge_detect_up_value + edge_detect_down_value;
offs_cal_code <= sum >> 1;
cal_done <= 1'b1;
end
default : begin
offs_cal_code <= 5'b0_0000;
comp_data <= 2'b00;
sum <= 5'b0_0000;
end
endcase
end
always@(*)
begin
offset_nxst = 3'b000;
case(offset_curst)
START : begin
if(start_cal)
offset_nxst = UP_COUNT;
else
offset_nxst = START;
end
UP_COUNT : begin
if(offs_cal_code == 5'd31)
offset_nxst = COUNT_ROLL;
else
offset_nxst = UP_COUNT;
end
COUNT_ROLL : begin
if(offs_cal_code == 5'd31)
offset_nxst = DOWN_COUNT;
else
offset_nxst = COUNT_ROLL;
end
DOWN_COUNT : begin
if(offs_cal_code == 5'd0)
offset_nxst = STOP;
else
offset_nxst = DOWN_COUNT;
end
STOP : begin
if(!start_cal)
offset_nxst = START;
else
offset_nxst = STOP;
end
default : begin
if(start_cal)
offset_nxst = UP_COUNT;
else
offset_nxst = START;
end
endcase
end
endmodule |
module phase_adjust_fsm_top(
input m_ns_fwd_clk, //Tx SOC clock
input tx_clk_adapter, //Tx adapter clock
input tx_clk_even, //Tx_even clock
input rx_clk_ana, //piclk_odd(Rx Clock)
input rclk_adapt, //piclk_adapter clock
input fs_fwd_clk, //Rx SOC Clock
input ck_sys, //System clock
input reset_n,
input phase_tx_adapt_ovrd_sel,
input phase_tx_adapt_locked_ovrd,
input [3:0]phase_tx_adapt_code_ovrd,
input phase_tx_soc_ovrd_sel,
input phase_tx_soc_locked_ovrd,
input [3:0]phase_tx_soc_code_ovrd,
input phase_rx_adapt_ovrd_sel,
input phase_rx_adapt_locked_ovrd,
input [3:0]phase_rx_adapt_code_ovrd,
input phase_rx_soc_ovrd_sel,
input phase_rx_soc_locked_ovrd,
input [3:0]phase_rx_soc_code_ovrd,
input tx_adapt_start_phase_lock,
input tx_ana_start_phase_lock,
input rx_adapt_start_phase_lock,
input rx_ana_start_phase_lock,
input tx_en,
input rx_en,
input [1:0]sel_avg,
output wire tx_adapt_phase_locked,
output wire tx_ana_phase_locked,
output wire rx_adapt_phase_locked,
output wire rx_ana_phase_locked,
output wire [3:0]tx_adapt_phase_sel_code, //dll_ckadapter_code
output wire [3:0]tx_ana_phase_sel_code, //dll_cksoc_code
output wire [3:0]rx_adapt_phase_sel_code, //dll_piadapter_code
output wire [3:0]rx_ana_phase_sel_code //dll_pisoc_code
);
//Transmitter Block
phase_adjust_fsm i_tx_adapt(
.ref_clk(m_ns_fwd_clk), //TDB
.rst_n(reset_n),
.phase_adjust_ovrd_sel(phase_tx_adapt_ovrd_sel),
.phase_locked_ovrd(phase_tx_adapt_locked_ovrd),
.phase_sel_code_ovrd(phase_tx_adapt_code_ovrd),
.sample_clk(tx_clk_adapter),
.sys_clk(ck_sys), //System clock
.start_phase_lock(tx_adapt_start_phase_lock),
.enable(tx_en),
.sel_avg(sel_avg), //From AVMM
.phase_locked(tx_adapt_phase_locked),
.phase_sel_code(tx_adapt_phase_sel_code)
);
phase_adjust_fsm i_tx_analog(
.ref_clk(tx_clk_adapter), //Adapter Clock
.rst_n(reset_n),
.phase_adjust_ovrd_sel(phase_tx_soc_ovrd_sel),
.phase_locked_ovrd(phase_tx_soc_locked_ovrd),
.phase_sel_code_ovrd(phase_tx_soc_code_ovrd),
.sample_clk(tx_clk_even), //TXDLL even Clock
.sys_clk(ck_sys), //System clock
.start_phase_lock(tx_ana_start_phase_lock),
.enable(tx_en),
.sel_avg(sel_avg),
.phase_locked(tx_ana_phase_locked),
.phase_sel_code(tx_ana_phase_sel_code)
);
//Receiver Block
phase_adjust_fsm i_rx_analog(
.ref_clk(rx_clk_ana),
.rst_n(reset_n),
.phase_adjust_ovrd_sel(phase_rx_soc_ovrd_sel),
.phase_locked_ovrd(phase_rx_soc_locked_ovrd),
.phase_sel_code_ovrd(phase_rx_soc_code_ovrd),
.sample_clk(rclk_adapt), //piclk_adapt
.sys_clk(ck_sys), //System clock
.start_phase_lock(rx_ana_start_phase_lock),
.enable(rx_en),
.sel_avg(sel_avg),
.phase_locked(rx_ana_phase_locked),
.phase_sel_code(rx_adapt_phase_sel_code)
);
phase_adjust_fsm i_rx_adapt(
.ref_clk(rclk_adapt), //piclk_adapt
.rst_n(reset_n),
.phase_adjust_ovrd_sel(phase_rx_adapt_ovrd_sel),
.phase_locked_ovrd(phase_rx_adapt_locked_ovrd),
.phase_sel_code_ovrd(phase_rx_adapt_code_ovrd),
.sample_clk(fs_fwd_clk), //piclk_soc
.sys_clk(ck_sys),
.start_phase_lock(rx_adapt_start_phase_lock),
.enable(rx_en),
.sel_avg(sel_avg),
.phase_locked(rx_adapt_phase_locked),
.phase_sel_code(rx_ana_phase_sel_code)
);
endmodule |
module rx_offset_cal_fsm_top #(parameter DATAWIDTH = 45)
(
input sys_clk,
input rst_n,
input rx_offset_ovrd_sel,
input rx_offset_cal_done_ovrd,
input [4:0]rx_offset_cal_code_ovrd,
input start_cal,
input [(2*DATAWIDTH)-1:0]ana_rxdata,
input scan_mode, // Scan mode
input clk_div_ld, // Clock divider enable from avalon interface
input clk_div_1_onehot, // Onehot enable for clock divided by 1
input clk_div_2_onehot, // Onehot enable for clock divided by 2
input clk_div_4_onehot, // Onehot enable for clock divided by 4
input clk_div_8_onehot, // Onehot enable for clock divided by 8
input clk_div_16_onehot, // Onehot enable for clock divided by 16
input clk_div_32_onehot, // Onehot enable for clock divided by 32
input clk_div_64_onehot, // Onehot enable for clock divided by 64
output wire rxoffset_cal_done,
output wire rx_offset_cal_run,
output wire [(2*DATAWIDTH)-1:0][4:0]rxoffset_cal_code,
output wire rxoffset_clk_div_ld_ack_ff
);
wire rxoffset_cal_done_int;
wire sys_div_clk;
wire [(2*DATAWIDTH)-1:0][4:0] offs_cal_code_intr;
wire [(2*DATAWIDTH)-1:0][4:0] offs_cal_code_pre;
wire cal_done_single;
wire rx_cal_data;
wire start_cal_intr;
wire [4:0]offs_cal_code;
genvar i;
//Data Muxing b/w Register Data and internal logic data
generate
for(i=0;i<(2*DATAWIDTH);i=i+1)
begin: offs_cal_code_pre_gen
assign offs_cal_code_pre[i] = rx_offset_ovrd_sel ? rx_offset_cal_code_ovrd[4:0] : offs_cal_code_intr[i];
end
endgenerate // block: offs_cal_code_pre_gen
generate
for(i=0;i<(2*DATAWIDTH);i=i+1)
begin: offs_cal_code_gen
assign rxoffset_cal_code[i][4:0] = scan_mode ? 5'h0 : offs_cal_code_pre[i];
end // block: offs_cal_code_gen
endgenerate
assign rxoffset_cal_done = rx_offset_ovrd_sel ? rx_offset_cal_done_ovrd : rxoffset_cal_done_int;
//==============================
//Clock Divider for Div-1,2,4,8
//==============================
aib_clk_div_roffcal i_aib_clk_div_roffcal(
.rst_n(rst_n),
.clk(sys_clk),
.scan_mode(scan_mode),
.clk_div_ld(clk_div_ld),
.clk_div_1_onehot(clk_div_1_onehot),
.clk_div_2_onehot(clk_div_2_onehot),
.clk_div_4_onehot(clk_div_4_onehot),
.clk_div_8_onehot(clk_div_8_onehot),
.clk_div_16_onehot(clk_div_16_onehot),
.clk_div_32_onehot(clk_div_32_onehot),
.clk_div_64_onehot(clk_div_64_onehot),
.clk_out(sys_div_clk),
.clk_div_ld_ack_ff(rxoffset_clk_div_ld_ack_ff)
);
//========================================
//rxoffset calibration for rxdata 88-bits
//========================================
rxoffset_top i_rxoffset_top(.sys_clk(sys_div_clk),
.rst_n(rst_n),
.ana_rxdata(ana_rxdata),
.start_cal(start_cal),
.cal_done(cal_done_single),
.offs_cal_code(offs_cal_code),
.rx_cal_data(rx_cal_data),
.start_cal_sub(start_cal_intr),
.rxoffset_cal_done(rxoffset_cal_done_int),
.rx_offset_cal_run (rx_offset_cal_run),
.rx_offs_cal_code(offs_cal_code_intr)
);
//==========================================
//rxoffset calibration for single bit stage
//==========================================
rx_offset_cal i_rx_offset_cal(.sys_clk(sys_div_clk),
.rst_n(rst_n),
.start_cal(start_cal_intr),
.cal_data(rx_cal_data),
.cal_done(cal_done_single),
.offs_cal_code(offs_cal_code)
);
endmodule |
module aib_cdr_fsm(
input phase_detect, //RxDLL output
input sys_clk, //System CLock,
input rst_n,
input scan_mode,
input rx_en,
input cdr_ovrd_sel,
input cdr_lock_ovrd,
input picode_update_ovrd,
input [6:0]picode_even_ovrd,
input [6:0]picode_odd_ovrd,
input [1:0]clk_sel,//Config Register to decide averaging(2-bits)
output wire picode_update,
output wire cdr_lock, //To indicate the picodes have been locked
output wire [6:0] picode_even, //picode even[6:0] and picode odd[6:0]
output wire [6:0] picode_odd //picode even[6:0] and picode odd[6:0]
);
parameter START = 2'b00,
RUN = 2'b01;
reg [1:0] cdr_lock_curst, cdr_lock_nxst;
reg [6:0] div_sel;
reg [6:0] avg_cnt;
reg [6:0] phase_detect_cnt;
reg [5:0] picode_refp;
reg [4:0] picode_refn;
reg [4:0] lock_count;
reg [31:0][6:0] picode_avg_data;
reg [12:0] picode_average;
reg [4:0] picode_avg_index;
wire max_value;
wire [6:0] picode_avg_divide_value;
wire [6:0] picode_cond_check_0;
wire [6:0] picode_cond_check_p1;
wire [6:0] picode_cond_check_m1;
wire [6:0] picode_cond_check_p2;
wire [6:0] picode_cond_check_m2;
wire [6:0] picode_cond_check;
wire [6:0] div_sel_dec;
reg picode_update_int;
reg [6:0] picode_even_intr;
wire [6:0] picode_odd_intr;
reg picode_update_intr;
reg cdr_lock_intr;
integer i;
wire sync_rst_n;
wire phase_detect_sync;
//Reset Synchronizer
aib_rst_sync cdr_rst_sync
(
.clk (sys_clk), // Destination clock of reset to be synced
.i_rst_n (rst_n), // Asynchronous reset input
.scan_mode (scan_mode), // Scan enable
.sync_rst_n (sync_rst_n) // Synchronized reset output
);
// Phase detect synchronizer
aib_bit_sync bitsync_phase_detect
(
.clk (sys_clk), // Clock of destination domain
.rst_n (sync_rst_n), // Reset of destination domain
.data_in (phase_detect), // Input to be synchronized
.data_out (phase_detect_sync) // Synchronized output
);
//Data Muxing b/w Register Data and internal logic data
assign picode_even = cdr_ovrd_sel ? picode_even_ovrd : picode_even_intr;
assign picode_odd = cdr_ovrd_sel ? picode_odd_ovrd : picode_odd_intr ;
assign picode_update = cdr_ovrd_sel ? picode_update_ovrd : picode_update_intr;
assign cdr_lock = cdr_ovrd_sel ? cdr_lock_ovrd : cdr_lock_intr;
assign picode_avg_divide_value[6:0] = picode_average[11:5];
assign div_sel_dec[6:0] = (div_sel[6:0]-7'h01);
assign max_value = (avg_cnt[6:0] == div_sel_dec[6:0]);
assign picode_cond_check_0 = picode_avg_divide_value ^ picode_even_intr;
assign picode_cond_check_p1 = (picode_avg_divide_value+1) ^ picode_even_intr;
assign picode_cond_check_m1 = (picode_avg_divide_value-1) ^ picode_even_intr;
assign picode_cond_check_p2 = (picode_avg_divide_value+2) ^ picode_even_intr;
assign picode_cond_check_m2 = (picode_avg_divide_value-2) ^ picode_even_intr;
assign picode_cond_check = picode_cond_check_0 & picode_cond_check_p1 & picode_cond_check_m1 & picode_cond_check_p2 & picode_cond_check_m2;
//Need to update
always@(*)
begin
case(clk_sel)
2'b00 : div_sel = 7'b000_1000; //8
2'b01 : div_sel = 7'b001_0000; //16
2'b10 : div_sel = 7'b010_0000; //32
2'b11 : div_sel = 7'b100_0000; //64
endcase
end
always @ (posedge sys_clk or negedge sync_rst_n)
begin
if(!sync_rst_n)
cdr_lock_curst[1:0] <= 2'b00;
else
cdr_lock_curst[1:0] <= cdr_lock_nxst[1:0];
end
always@(posedge sys_clk or negedge sync_rst_n)
if(!sync_rst_n)
begin
picode_refp <= 6'b00_0000;
picode_refn <= 5'b0_0000;
picode_even_intr <= 7'b000_0000;
cdr_lock_intr <= 1'b0;
picode_update_intr <= 1'b0;
picode_update_int <= 1'b0;
lock_count <= 5'b0_0000;
phase_detect_cnt <= 7'b000_0000;
avg_cnt <= 7'b000_0000;
for(i=0; i<32; i=i+1)
begin
picode_avg_data[i] <= 7'b000_0000;
picode_average <= {13{1'b0}};
picode_avg_index <= {5{1'b0}};
end
end
else
begin
case(cdr_lock_nxst)
START : begin
avg_cnt <= 7'b000_0000;
phase_detect_cnt <= 7'b000_0000;
picode_update_intr <= 1'b0;
picode_update_int <= 1'b0;
for(i=0; i<32; i=i+1)
picode_avg_data[i] <= 7'b000_0000;
picode_average <= {13{1'b0}};
picode_avg_index <= {5{1'b0}};
end
RUN : begin
if(max_value)
begin
phase_detect_cnt <= 7'b000_0000;
avg_cnt <= 7'b000_0000;
picode_average <= (picode_even_intr - picode_avg_data[picode_avg_index]) + picode_average;
picode_avg_data[picode_avg_index] <= picode_even_intr;
picode_avg_index <= picode_avg_index + 1'b1;
if(phase_detect_cnt < {1'b0,picode_refp})
begin
picode_even_intr <= picode_even_intr - 1'b1;
picode_update_int <= 1'b1;
end
else if(phase_detect_cnt > {2'b00,picode_refn})
begin
picode_even_intr <= picode_even_intr + 1'b1;
picode_update_int <= 1'b1;
end
else
begin
picode_even_intr <= picode_even_intr ;
picode_update_int <= 1'b0;
end
if(cdr_lock_intr == 1'b0)
begin
if(picode_cond_check!=7'b000_0000)
lock_count <= 5'b0_0000;
else
lock_count <= lock_count + 1'b1;
if(lock_count > 5'b1_0000)
cdr_lock_intr <= 1'b1;
else
cdr_lock_intr <= cdr_lock_intr;
end
end
else if(rx_en)
begin
avg_cnt <= avg_cnt + 1'b1;
if(phase_detect_sync)
phase_detect_cnt <= phase_detect_cnt + 1'b1;
else
phase_detect_cnt <= phase_detect_cnt;
end
else
begin
avg_cnt <= avg_cnt;
phase_detect_cnt <= phase_detect_cnt;
end
if(avg_cnt == 7'b000_0000)
picode_update_intr <= picode_update_int;
else if(avg_cnt == 7'b000_0001)
picode_update_intr <= 1'b0;
else
picode_update_intr <= picode_update_intr;
picode_refp <= 3 * (div_sel>>2);
picode_refn <= div_sel>>2;
end
default : begin
avg_cnt <= 7'b000_0000;
phase_detect_cnt <= 7'b000_0000;
picode_update_intr <= 1'b0;
picode_update_int <= 1'b0;
for(i=0; i<32; i=i+1)
picode_avg_data[i] <= 7'b000_0000;
picode_average <= {13{1'b0}};
picode_avg_index <= {5{1'b0}};
end
endcase
end
always@(*)
begin
cdr_lock_nxst = 2'b00;
case(cdr_lock_curst)
START : begin
if(rx_en)
cdr_lock_nxst = RUN;
else
cdr_lock_nxst = START;
end
RUN : begin
if(!rx_en)
cdr_lock_nxst = START;
else
cdr_lock_nxst = RUN;
end
default : begin
if(rx_en)
cdr_lock_nxst = RUN;
else
cdr_lock_nxst = START;
end
endcase
end
assign picode_odd_intr = picode_even_intr + 7'd64;
endmodule |
module aib_dcs_fsm (
input sys_clk,
input rst_n,
input scan_mode, // Scan mode
input clk_div_ld, // Clock divider enable from avalon interface
input clk_div_1_onehot, // Onehot enable for clock divided by 1
input clk_div_2_onehot, // Onehot enable for clock divided by 2
input clk_div_4_onehot, // Onehot enable for clock divided by 4
input clk_div_8_onehot, // Onehot enable for clock divided by 8
input clk_div_16_onehot, // Onehot enable for clock divided by 16
input clk_div_32_onehot, // Onehot enable for clock divided by 32
input clk_div_64_onehot, // Onehot enable for clock divided by 64
input clk_div_128_onehot, // Onehot enable for clock divided by 128
input clk_div_256_onehot, // Onehot enable for clock divided by 256
input duty_gt_50,
input dcs_en,
input dcs_ovrd_sel,
input dcs_ovrd_lock,
input dcs_ovrd_chopen,
input [4:0] dcs_ovrd_p_pdsel,
input [4:0] dcs_ovrd_p_pusel,
input [4:0] dcs_ovrd_n_pdsel,
input [4:0] dcs_ovrd_n_pusel,
output wire [4:0] dcc_p_pdsel,
output wire [4:0] dcc_p_pusel,
output wire [4:0] dcc_n_pdsel,
output wire [4:0] dcc_n_pusel,
output wire chopen,
output wire dcs_lock,
output wire clk_div_ld_ack_ff // Clock divider load acknowledge
);
reg [1:0] dcs_curst, dcs_nxst;
reg [6:0] dcs_code;
reg [4:0] duty_gt_50_cnt;
reg dcs_lock_int;
reg [1:0]dcs_comp;
reg chopen_intr;
reg [4:0] dcs_lock_cnt;
wire p_pd_chng;
wire n_pu_chng;
wire n_pd_chng;
wire [4:0] dcc_p_pdsel_intr;
wire [4:0] dcc_p_pusel_intr;
wire [4:0] dcc_n_pdsel_intr;
wire [4:0] dcc_n_pusel_intr;
wire sys_div_clk;
wire duty_gt_50_sync;
parameter START = 2'b00,
RUN = 2'b01;
// DCS counter threshold
`ifdef CAL_CODE_CNT
localparam [4:0] DCS_CNT_VAL = `DCS_CNT_VAL;
`else
localparam [4:0] DCS_CNT_VAL = 5'b1_1111;// Calibration count
`endif
//Should keep divider block Div-32,64,128,256 and need to add DCS lock signal
aib_clk_div_dcs aib_clk_div_dcs(
.rst_n(rst_n),
.clk(sys_clk),
.scan_mode(scan_mode),
.clk_div_ld(clk_div_ld),
.clk_div_1_onehot(clk_div_1_onehot),
.clk_div_2_onehot(clk_div_2_onehot),
.clk_div_4_onehot(clk_div_4_onehot),
.clk_div_8_onehot(clk_div_8_onehot),
.clk_div_16_onehot(clk_div_16_onehot),
.clk_div_32_onehot(clk_div_32_onehot),
.clk_div_64_onehot(clk_div_64_onehot), //Default value is 64
.clk_div_128_onehot(clk_div_128_onehot),
.clk_div_256_onehot(clk_div_256_onehot),
.clk_out(sys_div_clk),
.clk_div_ld_ack_ff(clk_div_ld_ack_ff)
);
// Start Phase synchronizer
aib_bit_sync bitsync_duty_gt_50
(
.clk (sys_clk), // Clock of destination domain
.rst_n (rst_n), // Reset of destination domain
.data_in (duty_gt_50), // Input to be synchronized
.data_out (duty_gt_50_sync) // Synchronized output
);
//as output and keep override signal
assign p_pd_chng = ~(dcs_code[1] & dcs_code[0]);
assign n_pu_chng = (dcs_code[1:0] == 2'b00 || dcs_code[1:0] == 2'b01);
assign n_pd_chng = ~(dcs_code[1] | dcs_code[0]);
assign dcc_p_pusel_intr = ~dcs_code[6:2];
assign dcc_p_pdsel_intr = p_pd_chng ? ~dcs_code[6:2] : (~dcs_code[6:2] - 1'b1);
assign dcc_n_pusel_intr = n_pu_chng ? dcs_code[6:2] : (dcs_code[6:2] + 1'b1);
assign dcc_n_pdsel_intr = n_pd_chng ? dcs_code[6:2] : (dcs_code[6:2] + 1'b1);
//Data Muxing b/w Register Data and internal logic data
assign dcc_p_pusel = dcs_ovrd_sel ? dcs_ovrd_p_pusel : dcc_p_pusel_intr;
assign dcc_p_pdsel = dcs_ovrd_sel ? dcs_ovrd_p_pdsel : dcc_p_pdsel_intr;
assign dcc_n_pusel = dcs_ovrd_sel ? dcs_ovrd_n_pusel : dcc_n_pusel_intr;
assign dcc_n_pdsel = dcs_ovrd_sel ? dcs_ovrd_n_pdsel : dcc_n_pdsel_intr;
assign dcs_lock = dcs_ovrd_sel ? dcs_ovrd_lock : dcs_lock_int;
assign chopen = dcs_ovrd_sel ? dcs_ovrd_chopen : chopen_intr;
always@(posedge sys_div_clk or negedge rst_n)
begin
if(!rst_n)
dcs_curst[1:0] <= 2'b00;
else
dcs_curst[1:0] <= dcs_nxst[1:0];
end
always@(posedge sys_div_clk or negedge rst_n)
if(!rst_n)
begin
dcs_code <= 7'b011_1111;
duty_gt_50_cnt <= 5'b0_0000;
chopen_intr <= 1'b0;
dcs_comp <= 2'b00;
dcs_lock_cnt <= 5'b0_0000;
dcs_lock_int <= 1'b0;
end
else
begin
case(dcs_curst)
START : begin
dcs_code <= 7'b011_1111;
duty_gt_50_cnt <= 5'b0_0000;
chopen_intr <= 1'b0;
dcs_comp <= 2'b00;
dcs_lock_cnt <= 5'b0_0000;
dcs_lock_int <= 1'b0;
end
RUN : begin
if(duty_gt_50_cnt == 5'b1_0000)
begin
duty_gt_50_cnt <= 5'b0_0000;
dcs_comp <= 2'b00;
end
else
begin
duty_gt_50_cnt <= duty_gt_50_cnt + 1'b1;
if(duty_gt_50_cnt == 5'b0_0110 || duty_gt_50_cnt == 5'b0_1110)
dcs_comp[duty_gt_50_cnt[3]] <= chopen_intr^duty_gt_50_sync;
else
dcs_comp <= dcs_comp;
if(duty_gt_50_cnt == 5'b0_1000 || duty_gt_50_cnt == 5'b0_0000)
chopen_intr <= ~chopen_intr;
else
chopen_intr <= chopen_intr;
if(duty_gt_50_cnt == 5'b0_1111)
begin
if(dcs_comp == 2'b11)
begin
if(dcs_code == 7'd0)
dcs_code <= dcs_code;
else
dcs_code <= dcs_code - 1'b1;
end
else if(dcs_comp == 2'b00)
begin
if(dcs_code == 7'd123)
dcs_code <= dcs_code;
else
dcs_code <= dcs_code + 1'b1;
end
else
dcs_code <= dcs_code;
if(dcs_lock_cnt == DCS_CNT_VAL)
dcs_lock_int <= 1'b1;
else
begin
dcs_lock_cnt <= dcs_lock_cnt + 1'b1;
dcs_lock_int <= dcs_lock_int;
end
end
end
end
default : begin
dcs_code <= 7'b011_1111;
duty_gt_50_cnt <= 7'b000_0000;
chopen_intr <= 1'b0;
dcs_comp <= 2'b00;
dcs_lock_cnt <= 5'b0_0000;
dcs_lock_int <= 1'b0;
end
endcase
end
always@(*)
begin
dcs_nxst = 2'b00;
case(dcs_curst)
START : begin
if(dcs_en)
dcs_nxst = RUN;
else
dcs_nxst = START;
end
RUN : begin
if(!dcs_en)
dcs_nxst = START;
else
dcs_nxst = RUN;
end
default : begin
if(dcs_en)
dcs_nxst = RUN;
else
dcs_nxst = START;
end
endcase
end
endmodule |
module phase_adjust_fsm(input ref_clk, //2GHz clock freeval_cntuency
input rst_n,
input phase_adjust_ovrd_sel,
input phase_locked_ovrd,
input [3:0]phase_sel_code_ovrd,
input sample_clk, //2GHz Clock freeval_cntuency
input sys_clk, //System clock(250MHz)
input start_phase_lock,
input [1:0]sel_avg,
input enable,
output wire phase_locked,
output wire [3:0]phase_sel_code
);
reg [6:0] div_sel;
reg [6:0] avg_cnt;
reg [15:0][3:0] samp_data;
reg [15:0][3:0] samp_data_diff;
reg [7:0] samp_data_avg;
reg [1:0] phase_adjust_curst;
reg [1:0] phase_adjust_nxst;
wire phase_detect;
wire phase_detect_sync;
wire start_phase_sync;
reg [3:0] max_val;
reg [3:0] eval_cnt;
wire max_value;
wire phase_value;
wire eval_value;
wire [6:0] div_sel_dec;
reg phase_locked_intr;
reg [3:0] phase_sel_code_intr;
reg [3:0] samp_data_in;
reg phase_detect_ff;
integer i;
parameter START = 2'b00,
RUN = 2'b01,
EVALUATE = 2'b10,
STOP = 2'b11;
localparam [1:0] AVG_0 = 2'd0;
localparam [1:0] AVG_1 = 2'd1;
localparam [1:0] AVG_2 = 2'd2;
localparam [1:0] AVG_3 = 2'd3;
// Start Phase synchronizer
aib_bit_sync bitsync_start_phase
(
.clk (sys_clk), // Clock of destination domain
.rst_n (rst_n), // Reset of destination domain
.data_in (start_phase_lock), // Input to be synchronized
.data_out (start_phase_sync) // Synchronized output
);
//Data Muxing b/w Register Data and internal logic data
assign phase_locked = phase_adjust_ovrd_sel ? phase_locked_ovrd : phase_locked_intr;
assign phase_sel_code = phase_adjust_ovrd_sel ? phase_sel_code_ovrd : phase_sel_code_intr;
//getting final count values
assign div_sel_dec[6:0] = div_sel[6:0]-7'h01;
assign max_value = (avg_cnt[6:0] == div_sel_dec[6:0]);
assign phase_value = (phase_sel_code_intr == 4'b1111);
assign eval_value = (eval_cnt == 4'b1111);
always@(*)
begin
case(sel_avg)
2'b00 : div_sel = 7'b000_1000; //8
2'b01 : div_sel = 7'b001_0000; //16
2'b10 : div_sel = 7'b010_0000; //32
2'b11 : div_sel = 7'b100_0000; //64
endcase
end
always @ (posedge sys_clk or negedge rst_n)
begin
if(!rst_n)
phase_adjust_curst[1:0] <= 2'b00;
else
phase_adjust_curst[1:0] <= phase_adjust_nxst[1:0];
end
always @(*)
begin
case(sel_avg[1:0])
AVG_0: samp_data_in[3:0] = samp_data_avg[3:0];
AVG_1: samp_data_in[3:0] = samp_data_avg[4:1];
AVG_2: samp_data_in[3:0] = samp_data_avg[5:2];
AVG_3: samp_data_in[3:0] = samp_data_avg[6:3];
endcase
end
always@(posedge sys_clk or negedge rst_n)
if(!rst_n)
begin
avg_cnt <= 7'b000_0000;
samp_data_avg <= 8'b0000_0000;
phase_sel_code_intr <= 4'b0000;
phase_locked_intr <= 1'b0;
max_val <= 4'b0000;
eval_cnt <= 4'b0000;
for(i=0; i<16; i=i+1)
begin
samp_data[i] <= 4'b0000;
samp_data_diff[i] <= 4'b0000;
end
end
else
begin
case(phase_adjust_curst)
START : begin
avg_cnt <= 7'b000_0000;
phase_sel_code_intr <= 4'b0000;
samp_data_avg <= 8'b0000_0000;
for(i=0; i<16; i=i+1)
begin
samp_data[i] <= 4'b0000;
samp_data_diff[i] <= 4'b0000;
end
end
RUN : begin
if(max_value)
begin
samp_data[phase_sel_code_intr] <= samp_data_in[3:0];
samp_data_avg <= 8'b0000_0000;
avg_cnt <= 7'b000_0000;
phase_sel_code_intr <= phase_sel_code_intr+1'b1;
end
else if(enable)
begin
avg_cnt <= avg_cnt + 1'b1;
if(phase_detect)
samp_data_avg <= samp_data_avg+1'b1;
else
samp_data_avg <= samp_data_avg;
end
else
begin
avg_cnt <= avg_cnt;
samp_data_avg <= samp_data_avg;
end
end
EVALUATE : begin
if(samp_data[0] >= samp_data[15])
begin
samp_data_diff[0] <= samp_data[0] - samp_data[15];
end
else
begin
samp_data_diff[0] <= 4'b0000;
end
for(i=1; i<16; i=i+1)
begin: diff_calculation_register
if(samp_data[i] >= samp_data[i-1])
begin
samp_data_diff[i] <= samp_data[i] - samp_data[i-1];
end
else
begin
samp_data_diff[i] <= 4'b0000;
end
end // block diff_calculation_register
if(eval_cnt == 0)
begin
max_val <= samp_data_diff[0];
end
else if(samp_data_diff[eval_cnt] > max_val)
begin
max_val <= samp_data_diff[eval_cnt];
phase_sel_code_intr <= eval_cnt;
end
else
begin
max_val <= max_val;
phase_sel_code_intr <= phase_sel_code_intr;
end
eval_cnt <= eval_cnt+1'b1;
end
STOP : begin
phase_locked_intr <= 1'b1;
phase_sel_code_intr <= phase_sel_code_intr;
end
endcase
end
always@(*)
begin
phase_adjust_nxst = 2'b00;
case(phase_adjust_curst)
START : begin
if(start_phase_sync)
phase_adjust_nxst = RUN;
else
phase_adjust_nxst = START;
end
RUN : begin
if(phase_value && max_value)
phase_adjust_nxst = EVALUATE;
else
phase_adjust_nxst = RUN;
end
EVALUATE : begin
if(eval_value)
phase_adjust_nxst = STOP;
else
phase_adjust_nxst = EVALUATE;
end
STOP : begin
if(!start_phase_sync)
phase_adjust_nxst = START;
else
phase_adjust_nxst = STOP;
end
endcase
end
// Register to sample adjusted clock wirh respect of reference clock
always@(posedge ref_clk)
begin: phase_detect_register
phase_detect_ff <= sample_clk;
end // block: phase_detect_register
// Phase detect synchronizer
aib_bit_sync bitsync_phase_detect
(
.clk (sys_clk), // Clock of destination domain
.rst_n (1'b1), // Reset of destination domain
.data_in (phase_detect_ff), // Input to be synchronized
.data_out (phase_detect_sync) // Synchronized output
);
assign phase_detect = (phase_adjust_curst == RUN) & phase_detect_sync;
endmodule |
module rcomp_calibration_fsm #(parameter RCOMP_WIDTH = 7)
(
input sys_clk,
input rst_n,
input rcomp_cal_ovrd_sel,
input rcomp_cal_done_ovrd,
input [RCOMP_WIDTH-1:0]rcomp_cal_code_ovrd,
input start_cal,
input pad_data,
input gen1mode_en,
input scan_mode, // Scan mode
input clk_div_ld, // Clock divider enable from avalon interface
input clk_div_1_onehot, // Onehot enable for clock divided by 1
input clk_div_2_onehot, // Onehot enable for clock divided by 2
input clk_div_4_onehot, // Onehot enable for clock divided by 4
input clk_div_8_onehot, // Onehot enable for clock divided by 8
input clk_div_16_onehot, // Onehot enable for clock divided by 16
input clk_div_32_onehot, // Onehot enable for clock divided by 32
output wire rcomp_cal_done,
output reg rcomp_cal_en,
output wire [RCOMP_WIDTH-1:0]rcomp_cal_code, //6-bits for Gen1 and 7-bits for Gen2
output wire rcomp_clk_div_ld_ack_ff
);
parameter START = 2'b00,
COUNT = 2'b01,
STOP = 2'b10;
reg [1:0] rcomp_curst, rcomp_nxst;
reg [RCOMP_WIDTH-1:0] edge_detect_value;
reg [RCOMP_WIDTH-1:0] rcomp_cal_code_cnt;
reg [1:0] comp_data;
wire sys_div_clk;
wire rcomp_max_value;
reg rcomp_cal_done_intr;
wire [RCOMP_WIDTH-1:0]rcomp_cal_code_intr;
wire pad_data_sync;
// PAD data from replica synchronized
aib_bit_sync pad_data_sync_i
(
.clk (sys_clk), // Clock of destination domain
.rst_n (1'b1), // Reset of destination domain
.data_in (pad_data), // Input to be synchronized
.data_out (pad_data_sync) // Synchronized output
);
//===================================
//Clock Divider for Div-1,2,4,8,16,32
//====================================
aib_clk_div_rcomp i_aib_clk_div_rcomp(
.rst_n(rst_n),
.clk(sys_clk),
.scan_mode(scan_mode),
.clk_div_ld(clk_div_ld),
.clk_div_1_onehot(clk_div_1_onehot),
.clk_div_2_onehot(clk_div_2_onehot),
.clk_div_4_onehot(clk_div_4_onehot),
.clk_div_8_onehot(clk_div_8_onehot),
.clk_div_16_onehot(clk_div_16_onehot),
.clk_div_32_onehot(clk_div_32_onehot),
.clk_out(sys_div_clk),
.clk_div_ld_ack_ff(rcomp_clk_div_ld_ack_ff)
);
//Comparing Gen1 or Gen2 Modes
assign rcomp_cal_code_intr = gen1mode_en ? rcomp_cal_code_cnt : ~rcomp_cal_code_cnt;
assign rcomp_max_value = gen1mode_en ? (rcomp_cal_code_cnt == 7'd63) : (rcomp_cal_code_cnt == 7'd127);
//Data Muxing b/w Register Data and internal logic data
assign rcomp_cal_code[RCOMP_WIDTH-1:0] =
scan_mode ?
{RCOMP_WIDTH{1'b0}} :
(rcomp_cal_ovrd_sel ? rcomp_cal_code_ovrd : rcomp_cal_code_intr);
assign rcomp_cal_done = rcomp_cal_ovrd_sel ? rcomp_cal_done_ovrd : rcomp_cal_done_intr;
always@(posedge sys_div_clk or negedge rst_n)
begin
if(!rst_n)
rcomp_curst[1:0] <= 2'b00;
else
rcomp_curst[1:0] <= rcomp_nxst[1:0];
end
always@(posedge sys_div_clk or negedge rst_n)
if(!rst_n)
begin
edge_detect_value <= {RCOMP_WIDTH{1'b0}};
rcomp_cal_code_cnt <= {RCOMP_WIDTH{1'b0}};
rcomp_cal_done_intr <= 1'b0;
rcomp_cal_en <= 1'b0;
comp_data <= 2'b00;
end
else
begin
case(rcomp_curst)
START : begin
rcomp_cal_code_cnt <= {RCOMP_WIDTH{1'b0}};
comp_data <= 2'b00;
rcomp_cal_en <= 1'b1;
end
COUNT : begin
comp_data <= {comp_data[0], pad_data_sync};
rcomp_cal_en <= 1'b1;
if(comp_data[0] != comp_data[1])
begin
edge_detect_value <= rcomp_cal_code_cnt-1'b1; //Previous value
rcomp_cal_code_cnt <= {RCOMP_WIDTH{1'b0}};
end
else
begin
rcomp_cal_code_cnt <= rcomp_cal_code_cnt + 1'b1;
edge_detect_value <= edge_detect_value;
end
end
STOP : begin
rcomp_cal_code_cnt <= edge_detect_value;
rcomp_cal_done_intr <= 1'b1;
rcomp_cal_en <= 1'b0;
end
default : begin
edge_detect_value <= {RCOMP_WIDTH{1'b0}};
comp_data <= 2'b00;
rcomp_cal_en <= 1'b1;
end
endcase
end
always@(*)
begin
rcomp_nxst = 2'b00;
case(rcomp_curst)
START : begin
if(start_cal)
rcomp_nxst = COUNT;
else
rcomp_nxst = START;
end
COUNT : begin
if(comp_data[0] != comp_data[1] || rcomp_max_value)
rcomp_nxst = STOP;
else
rcomp_nxst = COUNT;
end
STOP : begin
if(!start_cal)
rcomp_nxst = START;
else
rcomp_nxst = STOP;
end
default : begin
if(start_cal)
rcomp_nxst = COUNT;
else
rcomp_nxst = START;
end
endcase
end
endmodule |
module aib_dll_ctrl_logic(
input [2:0] freq_range_sel,
output reg [2:0] trim_ctrl_bits
);
always@(*)
begin
case(freq_range_sel)
3'b000 : trim_ctrl_bits = 3'b100;
3'b001 : trim_ctrl_bits = 3'b101;
3'b010 : trim_ctrl_bits = 3'b110;
3'b011 : trim_ctrl_bits = 3'b111;
3'b100 : trim_ctrl_bits = 3'b000;
3'b101 : trim_ctrl_bits = 3'b001;
3'b110 : trim_ctrl_bits = 3'b010;
3'b111 : trim_ctrl_bits = 3'b011;
endcase
end
//========================Frequency LUT======================================
//Freq_range_sel(GHz) Min Max Trim bits(Current trim and cap trim)
// 3'b000 3.2 2.6 3'b100
// 3'b001 2.6 2.1 3'b101
// 3'b010 2.1 1.7 3'b110
// 3'b011 1.7 1.4 3'b111
// 3'b100 1.4 1.1 3'b000
// 3'b101 1.1 0.85 3'b001
// 3'b110 0.85 0.65 3'b010
// 3'b111 0.65 0.50 3'b011
//========================Frequency LUT======================================
endmodule |
module aib_adapter #(
parameter [0:0] BERT_BUF_MODE_EN = 1 // Enables Buffer mode for BERT
)
(
input dual_mode_select, // mode select: 0 follower and 1 leader
input m_gen2_mode, // Indicates generation mode (1: gen 2.0)
input atpg_mode, // Enables ATPG
input adapt_rstn, // Adapt asynchronous reset
input tx_fifo_rstn, // TX FIFO asynchronous reset
input rx_fifo_rstn, // RX FIFO asynchronous reset
input csr_sdr_mode, // SDR mode enable
//MAC data interface
output [319:0] data_out_f, // FIFO read data to mac
output [79:0] data_out, // Register mode data to mac
input [319:0] data_in_f, // FIFO write data from MAC
input [79:0] data_in, // Register mode write data from MAC
input tx_clk_adapter, // TX DLL clock to adapter
input m_wr_clk, // Write domain clock used to store the data
input m_rd_clk, // Read domain clock for data output
input fs_fwd_clk_div, // Divided far side forwarded clock
//AIB IO data interface
output [79:0] aibio_dout, // to IO buffer
input [79:0] aibio_din, // from IO buffer
input rclk_adapt, // RX DLL clock to adapter
//Control and status from MAC interface
input ms_rx_dcc_dll_lock_req, // Leader requests calibration of F2L datapath
input ms_tx_dcc_dll_lock_req, // Leader requests calibration of L2F datapath
input sl_tx_dcc_dll_lock_req, // Follower requests calibration of F2L datapath
input sl_rx_dcc_dll_lock_req, // Follower requests calibration of L2F datapath
input ms_tx_dcc_cal_doneint, // Calibration of leader DCC is complete
input sl_tx_dcc_cal_doneint, // Calibration of follower DCC is complete
input ms_rx_dll_lockint, // Calibration of leader DLL is complete
input sl_rx_dll_lockint, // Calibration of follower DLL is complete
input osc_fsm_ms_rstn, // Oscillator FSM reset for master
input osc_fsm_sl_rstn, // Oscillator FSM reset for slave
input cal_fsm_ms_rstn, // Calibration FSM reset for master
input cal_fsm_sl_rstn, // Calibration FSM reset for slave
output ms_tx_transfer_en, // Calibration of leader TX datapath is complete
output ms_rx_transfer_en, // Calibration of leader RX datapath is complete
output sl_tx_transfer_en, // Calibration of follower TX datapath is complete
output sl_rx_transfer_en, // Calibration of follower RX datapath is complete
output [80:0] ms_sideband, // Leader sideband data
output [72:0] sl_sideband, // Follower sideband data
output m_rx_align_done,
//SR interface with AIB IO
input wire sr_clk_in, // Sideband clock input
input wire srd_in, // Follower serial data input
input wire srl_in, // Follower serial data load input
output sr_clk_out, // Sideband clock output
output std_out, // Follower serial data output
output stl_out, // Follower serial data load output
//From AUX channel
input i_osc_clk, // Oscillator clock from aux channel
//Sideband user interface
input [26:0] sl_external_cntl_26_0, //user defined bits26-0 for slave shift reg
input [2:0] sl_external_cntl_30_28,//user defined bits30-28 for slave shift reg
input [25:0] sl_external_cntl_57_32,//user defined bits57-32 for slave shift reg
input [4:0] ms_external_cntl_4_0, //user defined bits 4:0 for master shift reg
input [57:0] ms_external_cntl_65_8, //user defined bits65-8 for master shift reg
// CSR bits
output fwd_clk_test_sync, // Forwarded clock test enable synchronized
input [1:0] csr_rx_fifo_mode, // RX FIFO mode configuration
input [4:0] rx_align_threshold, // RX FIFO WAM threshold
input [1:0] csr_tx_fifo_mode, // TX FIFO mode configuration
input csr_rx_wa_en, // RX Word alignment enable
input csr_rx_wa_mode, // Rx word alignment mode sticky bit
input csr_tx_wm_en, // TX Word mark insertion enable
input [4:0] csr_rx_mkbit, // Configuration of Rx mark bit position
input [4:0] csr_tx_mkbit, // Configuration of Tx mark bit position
input csr_txswap_en, // TX bit swap enable
input csr_rxswap_en, // RX bit swap enable
input [3:0] csr_tx_phcomp_rd_delay, // TX FIFO phase compensation
input [3:0] csr_rx_phcomp_rd_delay, // RX FIFO phase compensation
input csr_tx_dbi_en, // TX data bit inversion enable
input csr_rx_dbi_en, // RX data bit inversion enable
input [1:0] csr_lpbk_mode, // Loop back mode configuration register
input n_lpbk, // Near side loopback indication
input csr_fwd_clk_test, // Forwarded clock test enable
// BERT access interface
input [ 5:0] bert_acc_addr, // BERT access address
input bert_acc_req, // BERT access request
input bert_acc_rdwr, // BERT access read/write control
input [31:0] bert_wdata_ff, // BERT data to be written
output [31:0] rx_bert_rdata_ff, // Read data from RX BERT interface
output [31:0] tx_bert_rdata_ff, // Read data from TX BERT interface
output bert_acc_rq_pend, // BERT configuration load is pending
// TX BERT control interface
input [3:0] tx_bert_start, // Starts transmitting TX BERT bit sequence
input [3:0] tx_bert_rst, // Resets TX BERT registers
// TX BERT status interface
output bert_seed_good, // Indicates all BPRS seeds are not zero.
output [3:0] txbert_run_ff, // Indicates TX BERT is running
// RX BERT control interface
input [3:0] rxbert_start, // Starts checking input of RX BERT bit sequence
input [3:0] rxbert_rst, // Resets RX BERT registers
input [3:0] rxbert_seed_in, // Enables the self-seeding in RX BERT
// RX BERT status interface
output [ 3:0] rxbert_run_ff, // Indicates RX BERT is running
output [ 3:0] rxbert_biterr_ff, // Error detected in RX BERT checker
// BERT enable
input tx_bert_en, // TX BERT enable
// Avalon clock and asynchronous reset
input i_cfg_avmm_clk,
input i_cfg_avmm_rst_n
);
localparam FARSIDE_LPBK = 2'b01;
localparam NEARSIDE_LPBK = 2'b10;
wire is_master;
wire ms_osc_transfer_en;
wire sl_osc_transfer_en;
wire sr_ms_load_out;
wire rxrd_fifo_rstn;
wire rxwr_rstn;
wire rxwr_fifo_rstn;
wire rxrd_rstn;
wire txwr_rstn;
wire txwr_fifo_rstn;
wire txrd_rstn;
wire txrd_fifo_rstn;
wire sr_ms_data_out;
wire [80:0] ms_data_fr_core, ms_data_to_core;
wire [72:0] sl_data_fr_core, sl_data_to_core;
wire sr_sl_data_out;
wire sr_sl_load_out;
//
wire [319:0] tx_adapt_din;
wire [319:0] rx_adapt_dout;
wire [79:0] tx_adapt_dout;
wire sr_sl_clk_out;
wire ms_tx_transfer_en_m, ms_rx_transfer_en_m;
wire sl_tx_transfer_en_s, sl_rx_transfer_en_s;
wire ms_rx_dll_lock, sl_rx_dll_lock;
wire ms_tx_dcc_cal_done, sl_tx_dcc_cal_done;
reg [79:0] data_in_r, data_out_r;
reg [319:0] data_in_f_r, data_out_f_r;
wire [79:0] data_out_int;
wire [319:0] data_out_f_int;
wire f_lpbk;
wire f_lpbk_int;
wire rxfifo_rd_clk;
wire txfifo_wr_clk;
wire m_rd_clk_g;
wire m_wr_clk_g;
wire csr_rx_wa_en_sync;
wire csr_tx_wm_en_sync;
wire rx_wa_mode_sync;
wire [3:0] rx_rst_pulse;
wire [3:0] rx_start_pulse;
wire [3:0] seed_in_en;
wire [3:0] rx_bertgen_en;
wire [5:0] chk3_lane_sel_ff;
wire [5:0] chk2_lane_sel_ff;
wire [5:0] chk1_lane_sel_ff;
wire [5:0] chk0_lane_sel_ff;
wire [2:0] chk3_ptrn_sel_ff;
wire [2:0] chk2_ptrn_sel_ff;
wire [2:0] chk1_ptrn_sel_ff;
wire [2:0] chk0_ptrn_sel_ff;
wire [48:0] rbert_bit_cnt_ff;
wire [15:0] biterr_cnt_chk3;
wire [15:0] biterr_cnt_chk2;
wire [15:0] biterr_cnt_chk1;
wire [15:0] biterr_cnt_chk0;
wire [127:0] rx_bert3_data;
wire [127:0] rx_bert2_data;
wire [127:0] rx_bert1_data;
wire [127:0] rx_bert0_data;
wire [3:0] tx_start_pulse;
wire [3:0] tx_rst_pulse;
wire [3:0] tx_bertgen_en;
wire [3:0] tx_seed_good;
wire [319:0] tx_bert_data_out;
wire tx_bert_en_sync;
wire [ 2:0] gen0_ptrn_sel_ff;
wire [ 2:0] gen1_ptrn_sel_ff;
wire [ 2:0] gen2_ptrn_sel_ff;
wire [ 2:0] gen3_ptrn_sel_ff;
wire [ 1:0] lane39_gen_sel_ff;
wire [ 1:0] lane38_gen_sel_ff;
wire [ 1:0] lane37_gen_sel_ff;
wire [ 1:0] lane36_gen_sel_ff;
wire [ 1:0] lane35_gen_sel_ff;
wire [ 1:0] lane34_gen_sel_ff;
wire [ 1:0] lane33_gen_sel_ff;
wire [ 1:0] lane32_gen_sel_ff;
wire [ 1:0] lane31_gen_sel_ff;
wire [ 1:0] lane30_gen_sel_ff;
wire [ 1:0] lane29_gen_sel_ff;
wire [ 1:0] lane28_gen_sel_ff;
wire [ 1:0] lane27_gen_sel_ff;
wire [ 1:0] lane26_gen_sel_ff;
wire [ 1:0] lane25_gen_sel_ff;
wire [ 1:0] lane24_gen_sel_ff;
wire [ 1:0] lane23_gen_sel_ff;
wire [ 1:0] lane22_gen_sel_ff;
wire [ 1:0] lane21_gen_sel_ff;
wire [ 1:0] lane20_gen_sel_ff;
wire [ 1:0] lane19_gen_sel_ff;
wire [ 1:0] lane18_gen_sel_ff;
wire [ 1:0] lane17_gen_sel_ff;
wire [ 1:0] lane16_gen_sel_ff;
wire [ 1:0] lane15_gen_sel_ff;
wire [ 1:0] lane14_gen_sel_ff;
wire [ 1:0] lane13_gen_sel_ff;
wire [ 1:0] lane12_gen_sel_ff;
wire [ 1:0] lane11_gen_sel_ff;
wire [ 1:0] lane10_gen_sel_ff;
wire [ 1:0] lane9_gen_sel_ff;
wire [ 1:0] lane8_gen_sel_ff;
wire [ 1:0] lane7_gen_sel_ff;
wire [ 1:0] lane6_gen_sel_ff;
wire [ 1:0] lane5_gen_sel_ff;
wire [ 1:0] lane4_gen_sel_ff;
wire [ 1:0] lane3_gen_sel_ff;
wire [ 1:0] lane2_gen_sel_ff;
wire [ 1:0] lane1_gen_sel_ff;
wire [ 1:0] lane0_gen_sel_ff;
wire [15:0] seed_ld_0;
wire [15:0] seed_ld_1;
wire [15:0] seed_ld_2;
wire [15:0] seed_ld_3;
wire [31:0] txwdata_sync_ff;
//////////////////////////////////////////////////////////////////
// Flop in and Flop out reg mode data and FIFO mode data
//////////////////////////////////////////////////////////////////
assign data_out = data_out_r;
assign data_out_f = data_out_f_r;
clk_gate_cel cg_data_in_f(
.clkout (m_wr_clk_g), // Clock gated
.clk (m_wr_clk), // Clock input
.en (~f_lpbk_int), // Clock enable
.te (atpg_mode) // Test enable
);
// Data Buffer for register mode input
always @(posedge tx_clk_adapter)
begin: data_in_r_register
data_in_r <= data_in;
end // block: data_in_r_register
// Data Buffer for FIFO mode input
always @(posedge m_wr_clk_g)
begin: data_in_f_r_register
data_in_f_r <= data_in_f;
end // block: data_in_f_r_register
// Data Buffer for register mode output
always @(posedge rclk_adapt or negedge rxwr_rstn)
begin: data_out_r_register
if(!rxwr_rstn)
data_out_r[79:0] <= {80{1'b0}};
else
data_out_r[79:0] <= data_out_int[79:0];
end // block: data_out_r_register
clk_gate_cel cg_data_out_f(
.clkout (m_rd_clk_g), // Clock gated
.clk (m_rd_clk), // Clock input
.en (~f_lpbk_int), // Clock enable
.te (atpg_mode) // Test enable
);
// Data Buffer for FIFO mode output
always @(posedge m_rd_clk_g or negedge rxrd_fifo_rstn)
begin: data_out_f_r_register
if(!rxrd_fifo_rstn)
data_out_f_r <= {320{1'b0}};
else
data_out_f_r[319:0] <= data_out_f_int[319:0];
end // data_out_f_r_register
///////////////////////////////////////////////////////////////////
// Control and status relate to calibration state machine
///////////////////////////////////////////////////////////////////
assign ms_tx_transfer_en = dual_mode_select ?
ms_tx_transfer_en_m :
ms_data_to_core[78];
assign ms_rx_transfer_en = dual_mode_select ?
ms_rx_transfer_en_m :
ms_data_to_core[75];
assign sl_tx_transfer_en = dual_mode_select ?
(n_lpbk ? ms_tx_transfer_en_m : sl_data_to_core[64]) :
sl_tx_transfer_en_s;
assign sl_rx_transfer_en = dual_mode_select ?
(n_lpbk ? ms_rx_transfer_en_m : sl_data_to_core[70]) :
sl_rx_transfer_en_s;
assign ms_sideband[80:0] = ms_data_to_core[80:0];
assign sl_sideband[72:0] = sl_data_to_core[72:0];
assign is_master = (dual_mode_select == 1'b1) ? 1'b1 : 1'b0;
clk_mux sr_clk_mux_i(
// Inputs
.clk1 (i_osc_clk), // s=1
.clk2 (sr_sl_clk_out), // s=0
.s (is_master),
// Outputs
.clkout (sr_clk_out)
);
assign std_out = is_master ? sr_ms_data_out : sr_sl_data_out;
assign stl_out = is_master ? sr_ms_load_out : sr_sl_load_out;
assign ms_data_fr_core[80:0] = { ms_osc_transfer_en,
1'b1,
ms_tx_transfer_en_m,
2'b11,
ms_rx_transfer_en_m,
ms_rx_dll_lock,
5'b11111,
ms_tx_dcc_cal_done,
1'b0,
1'b1,
ms_external_cntl_65_8[57:0],
1'b1,
1'b0,
1'b1,
ms_external_cntl_4_0[4:0] };
assign sl_data_fr_core[72:0] = {sl_osc_transfer_en,
1'b0,
sl_rx_transfer_en_s,
sl_rx_dcc_dll_lock_req,
sl_rx_dll_lock,
3'b0,
sl_tx_transfer_en_s,
sl_tx_dcc_dll_lock_req,
1'b0,
1'b0,
1'b1,
1'b0,
1'b1,
sl_external_cntl_57_32[25:0],
sl_tx_dcc_cal_done,
sl_external_cntl_30_28[2:0],
1'b0,
sl_external_cntl_26_0[26:0]};
///////////////////////////////////////////////////////////////////
// Loopback
///////////////////////////////////////////////////////////////////
assign f_lpbk = (csr_lpbk_mode== FARSIDE_LPBK);
assign f_lpbk_int = f_lpbk & ~atpg_mode;
aib_bit_sync tx_berten_sync_i
(
.clk (txfifo_wr_clk), // RX FIFO write clock
.rst_n (txwr_rstn), // RX FIFO write domain reset
.data_in (tx_bert_en), // Input to be synchronized
.data_out (tx_bert_en_sync) // Synchronized output
);
// Farside loopback clock mux of RX FIFO read clock
clk_mux fs_lpb_rd_clk_mux(
// Inputs
.clk1 (fs_fwd_clk_div), // s=1
.clk2 (m_rd_clk), // s=0
.s (f_lpbk_int),
// Outputs
.clkout (rxfifo_rd_clk)
);
// Farside loopback clock mux of RX FIFO read clock
clk_mux fs_lpb_wr_clk_mux(
// Inputs
.clk1 (fs_fwd_clk_div), // s=1
.clk2 (m_wr_clk), // s=0
.s (f_lpbk_int),
// Outputs
.clkout (txfifo_wr_clk)
);
//Farside Loopback: Farside -> AIB IO RX -> AIB Adaptor RX out to TX Adaptor in
assign tx_adapt_din =
f_lpbk_int ?
rx_adapt_dout[319:0] :
(tx_bert_en_sync ? tx_bert_data_out[319:0] : data_in_f_r[319:0]);
// FIFO output data
assign data_out_f_int = rx_adapt_dout;
aib_bit_sync csr_rx_wamen_sync
(
.clk (rclk_adapt), // RX FIFO write clock
.rst_n (rxwr_rstn), // RX FIFO write domain reset
.data_in (csr_rx_wa_en), // Input to be synchronized
.data_out (csr_rx_wa_en_sync) // Synchronized output
);
// Synchronizer for Rx Word alignment mode bit
aib_bit_sync csr_rx_wa_mode_sync
(
.clk (rclk_adapt), // RX FIFO write clock
.rst_n (rxwr_rstn), // RX FIFO write domain reset
.data_in (csr_rx_wa_mode), // Input to be synchronized
.data_out (rx_wa_mode_sync) // Synchronized output
);
// Adapt RX channel
aib_adapter_rxchnl aib_adapt_rxchnl(
// Outputs
.rx_adapt_dout(rx_adapt_dout[319:0]),
.data_out(data_out_int),
.align_done(m_rx_align_done),
// Inputs
.din(aibio_din[79:0]), //from io buffer or near side loopback
.rxfifo_wrclk(rclk_adapt),
.rxfifo_rd_clk(rxfifo_rd_clk),
.atpg_mode(atpg_mode),
.m_gen2_mode(m_gen2_mode),
.rxrd_fifo_rstn (rxrd_fifo_rstn),
.rxwr_rstn (rxwr_rstn),
.rxwr_fifo_rstn (rxwr_fifo_rstn),
.r_rx_fifo_mode(csr_rx_fifo_mode),
.rx_align_threshold (rx_align_threshold[4:0]),
.r_rx_phcomp_rd_delay(csr_rx_phcomp_rd_delay[3:0]),
.r_rx_wa_en(csr_rx_wa_en_sync),
.rx_wa_mode_sync (rx_wa_mode_sync),
.r_rx_mkbit(csr_rx_mkbit[4:0]),
.r_rxswap_en(csr_rxswap_en),
.r_rx_dbi_en(csr_rx_dbi_en)
);
// AIB IO data
assign aibio_dout = tx_adapt_dout;
// Synchronizer Tx Word mark insertion enable
aib_bit_sync csr_tx_wamen_sync
(
.clk (txfifo_wr_clk), // TX FIFO write clock
.rst_n (txwr_rstn), // TX FIFO write domain reset
.data_in (csr_tx_wm_en), // Input to be synchronized
.data_out (csr_tx_wm_en_sync) // Synchronized output
);
// Adapt TX channel
aib_adapter_txchnl aib_adapt_txchnl(
// Outputs
.dout(tx_adapt_dout[79:0]),
// Inputs
.atpg_mode(atpg_mode),
.m_gen2_mode(m_gen2_mode),
.txwr_fifo_rstn (txwr_fifo_rstn),
.txrd_rstn (txrd_rstn),
.txrd_fifo_rstn (txrd_fifo_rstn),
.txfifo_wr_clk(txfifo_wr_clk),
.tx_clk_adapter(tx_clk_adapter), //This includes reg mode clock during loopback.
.tx_adapt_din(tx_adapt_din[319:0]),
.data_in(data_in_r),
.r_tx_fifo_mode(csr_tx_fifo_mode),
.r_tx_phcomp_rd_delay(csr_tx_phcomp_rd_delay[3:0]),
.r_tx_wm_en(csr_tx_wm_en_sync),
.r_tx_mkbit(csr_tx_mkbit[4:0]),
.r_txswap_en(csr_txswap_en),
.r_tx_dbi_en(csr_tx_dbi_en)
);
// Reset and calibration
aib_sr_fsm aib_sm
(
.osc_clk(i_osc_clk), //from aux
.sr_ms_clk_in(sr_clk_in), //input ms clock
.ms_osc_transfer_en(ms_osc_transfer_en),
.ms_rx_transfer_en(ms_rx_transfer_en_m),
.ms_rx_dll_lock(ms_rx_dll_lock),
.ms_tx_dcc_cal_done(ms_tx_dcc_cal_done),
.ms_tx_transfer_en(ms_tx_transfer_en_m),
.ms_rx_dcc_dll_lock_req(ms_rx_dcc_dll_lock_req),
.ms_tx_dcc_dll_lock_req(ms_tx_dcc_dll_lock_req),
.ms_rx_dll_lockint(ms_rx_dll_lockint),
.ms_tx_dcc_cal_doneint(ms_tx_dcc_cal_doneint),
.ms_tx_dcc_cal_donei(ms_data_to_core[68]),
.ms_rx_dll_locki(ms_data_to_core[74]),
.ms_rx_transfer_eni(ms_data_to_core[75]),
.ms_tx_transfer_eni(ms_data_to_core[78]),
.ms_osc_transfer_eni(ms_data_to_core[80]),
.sl_osc_transfer_en(sl_osc_transfer_en),
.sl_rx_transfer_en(sl_rx_transfer_en_s),
.sl_tx_dcc_cal_done(sl_tx_dcc_cal_done),
.sl_tx_transfer_en(sl_tx_transfer_en_s),
.sl_rx_dll_lock(sl_rx_dll_lock),
.sl_tx_dcc_dll_lock_req(sl_data_to_core[63]),
.sl_rx_dcc_dll_lock_req(sl_data_to_core[69]),
.sl_rx_dll_lockint(sl_rx_dll_lockint), //from slave internal
.sl_rx_dll_locki(sl_data_to_core[68]), //from sr interface
.sl_tx_dcc_cal_donei(sl_data_to_core[31]), //from sr interface
.sl_tx_dcc_cal_doneint(sl_tx_dcc_cal_doneint), //from slave internal
.sl_rx_transfer_eni(sl_data_to_core[70]),
.sl_osc_transfer_eni(sl_data_to_core[72]),
.ms_nsl(dual_mode_select),
.n_lpbk (n_lpbk),
.osc_fsm_ms_rstn (osc_fsm_ms_rstn),
.osc_fsm_sl_rstn (osc_fsm_sl_rstn),
.cal_fsm_ms_rstn (cal_fsm_ms_rstn),
.cal_fsm_sl_rstn (cal_fsm_sl_rstn)
);
// Leader sideband chain logic
aib_sr_master #(.MS_LENGTH(7'd81))
aib_sr_ms
(
.osc_clk(i_osc_clk), //free running osc clock
.ms_data_fr_core(ms_data_fr_core[80:0]),
.ms_data_to_core(ms_data_to_core[80:0]),
.sr_ms_data_out(sr_ms_data_out), //master serial data out
.sr_ms_load_out(sr_ms_load_out), //master load out
.sr_ms_data_in(srd_in), //master serial data out
.sr_ms_load_in(srl_in), //master serial data load inupt
.sr_ms_clk_in(sr_clk_in), //from input por
.osc_fsm_ms_rstn (osc_fsm_ms_rstn),
.osc_fsm_sl_rstn (osc_fsm_sl_rstn)
);
// Follower sideband chain logic
aib_sr_slave #(.SL_LENGTH(7'd73))
aib_sr_sl
(
.sr_sl_clk_in(sr_clk_in), //From input
.sr_sl_clk_out(sr_sl_clk_out), //to output
.sl_data_fr_core(sl_data_fr_core[72:0]),
.sl_data_to_core(sl_data_to_core[72:0]),
.sr_sl_data_out(sr_sl_data_out), //slave serial data out
.sr_sl_load_out(sr_sl_load_out), //slave load out
.sr_sl_data_in(srd_in), //slave serial data out
.sr_sl_load_in(srl_in), //slave serial data load inupt
.sr_ms_clk_in(sr_clk_in), //input ms clock
.osc_fsm_sl_rstn(osc_fsm_sl_rstn)
);
aib_bert_cdc #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_bert_cdc(
//------------------------------------------------------------------------------
// Interface with RX BERT
//------------------------------------------------------------------------------
// outputs
.rx_start_pulse (rx_start_pulse[3:0]),
.rx_rst_pulse (rx_rst_pulse[3:0]),
.seed_in_en (seed_in_en[3:0]),
.chk3_lane_sel_ff (chk3_lane_sel_ff[5:0]),
.chk2_lane_sel_ff (chk2_lane_sel_ff[5:0]),
.chk1_lane_sel_ff (chk1_lane_sel_ff[5:0]),
.chk0_lane_sel_ff (chk0_lane_sel_ff[5:0]),
.chk3_ptrn_sel_ff (chk3_ptrn_sel_ff[2:0]),
.chk2_ptrn_sel_ff (chk2_ptrn_sel_ff[2:0]),
.chk1_ptrn_sel_ff (chk1_ptrn_sel_ff[2:0]),
.chk0_ptrn_sel_ff (chk0_ptrn_sel_ff[2:0]),
// inputs
.rxbert_bit_cnt (rbert_bit_cnt_ff[48:0]),
.biterr_cnt_chk3 (biterr_cnt_chk3[15:0]),
.biterr_cnt_chk2 (biterr_cnt_chk2[15:0]),
.biterr_cnt_chk1 (biterr_cnt_chk1[15:0]),
.biterr_cnt_chk0 (biterr_cnt_chk0[15:0]),
.rx_bert3_data (rx_bert3_data[127:0]),
.rx_bert2_data (rx_bert2_data[127:0]),
.rx_bert1_data (rx_bert1_data[127:0]),
.rx_bert0_data (rx_bert0_data[127:0]),
.rx_bertgen_en (rx_bertgen_en[3:0]),
//------------------------------------------------------------------------------
// Interface with TX BERT
//------------------------------------------------------------------------------
//outputs
.lane39_gen_sel_ff (lane39_gen_sel_ff[1:0]),
.lane38_gen_sel_ff (lane38_gen_sel_ff[1:0]),
.lane37_gen_sel_ff (lane37_gen_sel_ff[1:0]),
.lane36_gen_sel_ff (lane36_gen_sel_ff[1:0]),
.lane35_gen_sel_ff (lane35_gen_sel_ff[1:0]),
.lane34_gen_sel_ff (lane34_gen_sel_ff[1:0]),
.lane33_gen_sel_ff (lane33_gen_sel_ff[1:0]),
.lane32_gen_sel_ff (lane32_gen_sel_ff[1:0]),
.lane31_gen_sel_ff (lane31_gen_sel_ff[1:0]),
.lane30_gen_sel_ff (lane30_gen_sel_ff[1:0]),
.lane29_gen_sel_ff (lane29_gen_sel_ff[1:0]),
.lane28_gen_sel_ff (lane28_gen_sel_ff[1:0]),
.lane27_gen_sel_ff (lane27_gen_sel_ff[1:0]),
.lane26_gen_sel_ff (lane26_gen_sel_ff[1:0]),
.lane25_gen_sel_ff (lane25_gen_sel_ff[1:0]),
.lane24_gen_sel_ff (lane24_gen_sel_ff[1:0]),
.lane23_gen_sel_ff (lane23_gen_sel_ff[1:0]),
.lane22_gen_sel_ff (lane22_gen_sel_ff[1:0]),
.lane21_gen_sel_ff (lane21_gen_sel_ff[1:0]),
.lane20_gen_sel_ff (lane20_gen_sel_ff[1:0]),
.lane19_gen_sel_ff (lane19_gen_sel_ff[1:0]),
.lane18_gen_sel_ff (lane18_gen_sel_ff[1:0]),
.lane17_gen_sel_ff (lane17_gen_sel_ff[1:0]),
.lane16_gen_sel_ff (lane16_gen_sel_ff[1:0]),
.lane15_gen_sel_ff (lane15_gen_sel_ff[1:0]),
.lane14_gen_sel_ff (lane14_gen_sel_ff[1:0]),
.lane13_gen_sel_ff (lane13_gen_sel_ff[1:0]),
.lane12_gen_sel_ff (lane12_gen_sel_ff[1:0]),
.lane11_gen_sel_ff (lane11_gen_sel_ff[1:0]),
.lane10_gen_sel_ff (lane10_gen_sel_ff[1:0]),
.lane9_gen_sel_ff (lane9_gen_sel_ff[1:0]),
.lane8_gen_sel_ff (lane8_gen_sel_ff[1:0]),
.lane7_gen_sel_ff (lane7_gen_sel_ff[1:0]),
.lane6_gen_sel_ff (lane6_gen_sel_ff[1:0]),
.lane5_gen_sel_ff (lane5_gen_sel_ff[1:0]),
.lane4_gen_sel_ff (lane4_gen_sel_ff[1:0]),
.lane3_gen_sel_ff (lane3_gen_sel_ff[1:0]),
.lane2_gen_sel_ff (lane2_gen_sel_ff[1:0]),
.lane1_gen_sel_ff (lane1_gen_sel_ff[1:0]),
.lane0_gen_sel_ff (lane0_gen_sel_ff[1:0]),
.gen0_ptrn_sel_ff (gen0_ptrn_sel_ff[2:0]),
.gen1_ptrn_sel_ff (gen1_ptrn_sel_ff[2:0]),
.gen2_ptrn_sel_ff (gen2_ptrn_sel_ff[2:0]),
.gen3_ptrn_sel_ff (gen3_ptrn_sel_ff[2:0]),
.tx_start_pulse (tx_start_pulse[3:0]),
.tx_rst_pulse (tx_rst_pulse[3:0]),
.seed_ld_0 (seed_ld_0[15:0]),
.seed_ld_1 (seed_ld_1[15:0]),
.seed_ld_2 (seed_ld_2[15:0]),
.seed_ld_3 (seed_ld_3[15:0]),
.txwdata_sync_ff (txwdata_sync_ff[31:0]),
//inputs
.tx_seed_good (tx_seed_good[3:0]),
.tx_bertgen_en (tx_bertgen_en[3:0]),
//------------------------------------------------------------------------------
// BERT access interface
//------------------------------------------------------------------------------
// outputs
.rx_bert_rdata_ff (rx_bert_rdata_ff[31:0]), // Read data from RX BERT interface
.tx_bert_rdata_ff (tx_bert_rdata_ff[31:0]), // Read data from TX BERT interface
.bert_acc_rq_pend (bert_acc_rq_pend), // BERT configuration load is pending
// inputs
.bert_acc_addr (bert_acc_addr[5:0]), // BERT access address
.bert_acc_req (bert_acc_req), // BERT access request
.bert_acc_rdwr (bert_acc_rdwr), // BERT access read/write control
.bert_wdata_ff (bert_wdata_ff[31:0]), // BERT data to be written
//------------------------------------------------------------------------------
// TX BERT control interface
//------------------------------------------------------------------------------
// inputs
.tx_bert_start (tx_bert_start[3:0]), // Starts transmitting TX BERT bit sequence
.tx_bert_rst (tx_bert_rst[3:0]), // Resets TX BERT registers
//------------------------------------------------------------------------------
// TX BERT status interface
//------------------------------------------------------------------------------
// outputs
.bert_seed_good (bert_seed_good), // Indicates all BPRS seeds are not zero.
.txbert_run_ff (txbert_run_ff[3:0]), // Indicates TX BERT is running
//------------------------------------------------------------------------------
// RX BERT control interface
//------------------------------------------------------------------------------
// inputs
.rxbert_start (rxbert_start[3:0]), // Starts checking input of RX BERT bit seq
.rxbert_rst (rxbert_rst[3:0]), // Resets RX BERT registers
.rxbert_seed_in (rxbert_seed_in[3:0]), // Enables the self-seeding in RX BERT
//------------------------------------------------------------------------------
// RX BERT status interface
//------------------------------------------------------------------------------
// outputs
.rxbert_run_ff (rxbert_run_ff[3:0]), // Indicates RX BERT is running
.rxbert_biterr_ff (rxbert_biterr_ff[3:0]), // Error detected in RX BERT checker
//------------------------------------------------------------------------------
// clocks and resets
//------------------------------------------------------------------------------
// inputs
.i_cfg_avmm_clk (i_cfg_avmm_clk),
.i_cfg_avmm_rst_n (i_cfg_avmm_rst_n),
.txfifo_wr_clk (txfifo_wr_clk),
.txwr_rstn (txwr_rstn),
.rxfifo_rd_clk (rxfifo_rd_clk),
.rxrd_rstn (rxrd_rstn)
);
aib_rx_bert #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_rx_bert(
// Inputs
.clk (rxfifo_rd_clk), // Rx BERT clock
.rstn (rxrd_fifo_rstn), // Active low asynchronous reset
.rx_rst_pulse (rx_rst_pulse[3:0]), // Resets synchronously RX BERT logic
.rx_start_pulse (rx_start_pulse[3:0]), // Starts data comparison
.seed_in_en (seed_in_en[3:0]), // Seed input mode enable
.chk3_lane_sel_ff (chk3_lane_sel_ff[5:0]), // Lane selection to checker3
.chk2_lane_sel_ff (chk2_lane_sel_ff[5:0]), // Lane selection to checker2
.chk1_lane_sel_ff (chk1_lane_sel_ff[5:0]), // Lane selection to checker1
.chk0_lane_sel_ff (chk0_lane_sel_ff[5:0]), // Lane selection to checker0
.chk3_ptrn_sel_ff (chk3_ptrn_sel_ff[2:0]), // Pattern selection to checker 3
.chk2_ptrn_sel_ff (chk2_ptrn_sel_ff[2:0]), // Pattern selection to checker 2
.chk1_ptrn_sel_ff (chk1_ptrn_sel_ff[2:0]), // Pattern selection to checker 1
.chk0_ptrn_sel_ff (chk0_ptrn_sel_ff[2:0]), // Pattern selection to checker 0
.rx_bert_data_i (rx_adapt_dout[319:0]), // Data bits from RX FIFO
.sdr_mode (csr_sdr_mode), // Single data rate mode
.r_fifo_mode (csr_rx_fifo_mode[1:0]), // RX FIFO mode
.m_gen2_mode (m_gen2_mode), // GEN2 mode selector
// Outputs
.rbert_bit_cnt_ff (rbert_bit_cnt_ff[48:0]),
.biterr_cnt_chk3 (biterr_cnt_chk3[15:0]),
.biterr_cnt_chk2 (biterr_cnt_chk2[15:0]),
.biterr_cnt_chk1 (biterr_cnt_chk1[15:0]),
.biterr_cnt_chk0 (biterr_cnt_chk0[15:0]),
.rx_bert3_data (rx_bert3_data[127:0]),
.rx_bert2_data (rx_bert2_data[127:0]),
.rx_bert1_data (rx_bert1_data[127:0]),
.rx_bert0_data (rx_bert0_data[127:0]),
.rbert_running_ff (rx_bertgen_en[3:0]) // RX BERT checker is running
);
aib_tx_bert #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_tx_bert(
// Inputs
.clk (txfifo_wr_clk), // TX BERT clock
.rstn (txwr_fifo_rstn), // Active low asynchronous reset
.tx_start_pulse (tx_start_pulse[3:0]), // Start pulse
.tx_rst_pulse (tx_rst_pulse[3:0]), // Synchronous reset pulse
.gen0_ptrn_sel_ff (gen0_ptrn_sel_ff[2:0]),
.gen1_ptrn_sel_ff (gen1_ptrn_sel_ff[2:0]),
.gen2_ptrn_sel_ff (gen2_ptrn_sel_ff[2:0]),
.gen3_ptrn_sel_ff (gen3_ptrn_sel_ff[2:0]),
.lane39_gen_sel_ff (lane39_gen_sel_ff[1:0]),
.lane38_gen_sel_ff (lane38_gen_sel_ff[1:0]),
.lane37_gen_sel_ff (lane37_gen_sel_ff[1:0]),
.lane36_gen_sel_ff (lane36_gen_sel_ff[1:0]),
.lane35_gen_sel_ff (lane35_gen_sel_ff[1:0]),
.lane34_gen_sel_ff (lane34_gen_sel_ff[1:0]),
.lane33_gen_sel_ff (lane33_gen_sel_ff[1:0]),
.lane32_gen_sel_ff (lane32_gen_sel_ff[1:0]),
.lane31_gen_sel_ff (lane31_gen_sel_ff[1:0]),
.lane30_gen_sel_ff (lane30_gen_sel_ff[1:0]),
.lane29_gen_sel_ff (lane29_gen_sel_ff[1:0]),
.lane28_gen_sel_ff (lane28_gen_sel_ff[1:0]),
.lane27_gen_sel_ff (lane27_gen_sel_ff[1:0]),
.lane26_gen_sel_ff (lane26_gen_sel_ff[1:0]),
.lane25_gen_sel_ff (lane25_gen_sel_ff[1:0]),
.lane24_gen_sel_ff (lane24_gen_sel_ff[1:0]),
.lane23_gen_sel_ff (lane23_gen_sel_ff[1:0]),
.lane22_gen_sel_ff (lane22_gen_sel_ff[1:0]),
.lane21_gen_sel_ff (lane21_gen_sel_ff[1:0]),
.lane20_gen_sel_ff (lane20_gen_sel_ff[1:0]),
.lane19_gen_sel_ff (lane19_gen_sel_ff[1:0]),
.lane18_gen_sel_ff (lane18_gen_sel_ff[1:0]),
.lane17_gen_sel_ff (lane17_gen_sel_ff[1:0]),
.lane16_gen_sel_ff (lane16_gen_sel_ff[1:0]),
.lane15_gen_sel_ff (lane15_gen_sel_ff[1:0]),
.lane14_gen_sel_ff (lane14_gen_sel_ff[1:0]),
.lane13_gen_sel_ff (lane13_gen_sel_ff[1:0]),
.lane12_gen_sel_ff (lane12_gen_sel_ff[1:0]),
.lane11_gen_sel_ff (lane11_gen_sel_ff[1:0]),
.lane10_gen_sel_ff (lane10_gen_sel_ff[1:0]),
.lane9_gen_sel_ff (lane9_gen_sel_ff[1:0]),
.lane8_gen_sel_ff (lane8_gen_sel_ff[1:0]),
.lane7_gen_sel_ff (lane7_gen_sel_ff[1:0]),
.lane6_gen_sel_ff (lane6_gen_sel_ff[1:0]),
.lane5_gen_sel_ff (lane5_gen_sel_ff[1:0]),
.lane4_gen_sel_ff (lane4_gen_sel_ff[1:0]),
.lane3_gen_sel_ff (lane3_gen_sel_ff[1:0]),
.lane2_gen_sel_ff (lane2_gen_sel_ff[1:0]),
.lane1_gen_sel_ff (lane1_gen_sel_ff[1:0]),
.lane0_gen_sel_ff (lane0_gen_sel_ff[1:0]),
.seed_ld_0 (seed_ld_0[15:0]), // Generator0 seed load
.seed_ld_1 (seed_ld_1[15:0]), // Generator1 seed load
.seed_ld_2 (seed_ld_2[15:0]), // Generator2 seed load
.seed_ld_3 (seed_ld_3[15:0]), // Generator3 seed load
.txwdata_sync_ff (txwdata_sync_ff[31:0]), // Data bus to load seed
.sdr_mode (csr_sdr_mode), // SDR mode enable
.tx_fifo_mode (csr_tx_fifo_mode), // TX FIFO mode field
.m_gen2_mode (m_gen2_mode), // GEN2 mode selector
// Outputs
.tx_seed_good (tx_seed_good[3:0]),
.tx_bertgen_en (tx_bertgen_en[3:0]),
.tx_bert_data_out (tx_bert_data_out[319:0]) // TX Bert output
);
//------------------------------------------------------------------------------
// RX channel reset synchronizers
//------------------------------------------------------------------------------
// RX FIFO read reset synchronizer
aib_rst_sync rxrd_fifo_rstnsync
(
.clk(rxfifo_rd_clk), // Destination clock of reset to be synced
.i_rst_n(rx_fifo_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(rxrd_fifo_rstn) // Synchronized reset output
);
// RX write reset synchronizer
aib_rst_sync rxwr_rstnsync
(
.clk(rclk_adapt), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(rxwr_rstn) // Synchronized reset output
);
// RX FIFO write reset synchronizer
aib_rst_sync rxwr_fifo_rstnsync
(
.clk(rclk_adapt), // Destination clock of reset to be synced
.i_rst_n(rx_fifo_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(rxwr_fifo_rstn) // Synchronized reset output
);
// RX read reset synchronizer
aib_rst_sync rxrd_rstnsync
(
.clk(rxfifo_rd_clk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(rxrd_rstn) // Synchronized reset output
);
//------------------------------------------------------------------------------
// TX channel reset synchronizers
//------------------------------------------------------------------------------
// TX write reset synchronizer
aib_rst_sync txwr_rstnsync
(
.clk(txfifo_wr_clk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(txwr_rstn) // Synchronized reset output
);
// TX FIFO write reset synchronizer
aib_rst_sync txwr_fifo_rstnsync
(
.clk(txfifo_wr_clk), // Destination clock of reset to be synced
.i_rst_n(tx_fifo_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(txwr_fifo_rstn) // Synchronized reset output
);
// TX read reset synchronizer
aib_rst_sync txrd_rstnsync
(
.clk(tx_clk_adapter), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(txrd_rstn) // Synchronized reset output
);
// TX FIFO read reset synchronizer
aib_rst_sync txrd_fifo_rstnsync
(
.clk(tx_clk_adapter), // Destination clock of reset to be synced
.i_rst_n(tx_fifo_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(txrd_fifo_rstn) // Synchronized reset output
);
// Synchronizer for Forwarded clock test
aib_bit_sync #(.DWIDTH (1))
i_fwd_clk_test_sync
(
.clk (tx_clk_adapter),
.rst_n (txrd_rstn),
.data_in (csr_fwd_clk_test),
.data_out (fwd_clk_test_sync)
);
endmodule // aib_adapter |
module aib_redundancy_logic(
input idata_in0_even,
input idata_in1_even,
output wire data_out_even,
input idata_in0_odd,
input idata_in1_odd,
output wire data_out_odd,
input async_in0,
input async_in1,
output wire async_out,
input tx_en0,
input tx_en1,
output wire tx_en_out,
input rx_en0,
input rx_en1,
output wire rx_en_out,
input async_tx_en0,
input async_tx_en1,
output wire async_tx_en_out,
input async_rx_en0,
input async_rx_en1,
output wire async_rx_en_out,
input sdr_mode_en0,
input sdr_mode_en1,
output wire sdr_mode_en_out,
input wkpu_en_in0,
input wkpu_en_in1,
output wkpu_en_out,
input wkpd_en_in0,
input wkpd_en_in1,
output wkpd_en_out,
input shift_en
);
assign data_out_even = shift_en ? idata_in1_even : idata_in0_even;
assign data_out_odd = shift_en ? idata_in1_odd : idata_in0_odd ;
assign async_out = shift_en ? async_in1 : async_in0 ;
assign tx_en_out = shift_en ? tx_en1 : tx_en0 ;
assign rx_en_out = shift_en ? rx_en1 : rx_en0 ;
assign async_tx_en_out = shift_en ? async_tx_en1 : async_tx_en0 ;
assign async_rx_en_out = shift_en ? async_rx_en1 : async_rx_en0 ;
assign sdr_mode_en_out = shift_en ? sdr_mode_en1 : sdr_mode_en0 ;
assign wkpu_en_out = shift_en ? wkpu_en_in1 : wkpu_en_in0;
assign wkpd_en_out = shift_en ? wkpd_en_in1 : wkpd_en_in0;
endmodule |
module aib_redundancy_wrp_top
#(parameter DATAWIDTH = 40) (
input [101:0] shift_en,
input [DATAWIDTH-1:0] tx_data_in_even,
input [DATAWIDTH-1:0] tx_data_in_odd,
input [101:0] data_even_from_pad,
input [101:0] data_odd_from_pad,
input tx_lpbk_mode, //Configure through AVMM registers
input rx_lpbk_mode, //Configure through AVMM registers
input sdr_mode_en, //Configure through AVMM registers
input gen1mode_en, //Configure through AVMM registers
input csr_paden, // PAD enable register
input io_ctrl1_tx_wkpu_ff, // Weak pull-up for TX IOs
input io_ctrl1_tx_wkpd_ff, // Weak pull-down for TX IOs
input io_ctrl1_rx_wkpu_ff, // Weak pull-up for RX IOs
input io_ctrl1_rx_wkpd_ff, // Weak pull-down for RX IOs
input iopad_rstb,
input fwd_clk_test_sync,
//Async Signals
input ns_adapter_rstn,
input ns_mac_rdy ,
input ns_sr_load ,
input ns_sr_data ,
input ns_sr_clk ,
input ns_rcv_clk ,
input [101:0] pad_to_adapter_async_in,
output wire [101:0] async_data_to_pad,
output fs_rcv_clk_out,
output fs_sr_clk_out ,
output fs_sr_data_out ,
output fs_sr_load_out ,
output fs_mac_rdy_out ,
output fs_adapter_rstn_out,
//To Analog block
output wire [101:0] even_data_to_pad,
output wire [101:0] odd_data_to_pad,
output wire [101:0] rx_en_to_pad,
output wire [101:0] tx_en_to_pad,
output wire [101:0] tx_async_en_to_pad,
output wire [101:0] rx_async_en_to_pad,
output wire [101:0] sdr_mode_en_to_pad,
output wire [101:0] wkpu_en_out,
output wire [101:0] wkpd_en_out,
output [101:0] fault_stdby,
//To Adapter
output wire [DATAWIDTH-1:0] rx_data_out_even,
output wire [DATAWIDTH-1:0] rx_data_out_odd
);
wire [101:0] adapter_to_pad_data_even;
wire [101:0] adapter_to_pad_data_odd;
wire [101:0] adapter_to_pad_async;
wire [101:0] async_data_to_adapter;
wire [101:0] pad_to_adapter_dout_even;
wire [101:0] pad_to_adapter_dout_odd;
wire [39:0] rx_even_data;
wire [39:0] rx_odd_data;
wire [39:0] rx_even_data_lpbk;
wire [39:0] rx_odd_data_lpbk;
wire [39:0] tx_even_data_lpbk;
wire [39:0] tx_odd_data_lpbk;
//Enable signals
wire [101:0] rx_en;
wire [101:0] tx_en;
wire [101:0] async_tx_en;
wire [101:0] async_rx_en;
wire [101:0] sdr_mode;
wire [101:0] wkpu_en_in;
wire [101:0] wkpd_en_in;
wire [101:0] tx_en_out;
wire [101:0] rx_en_out;
wire [101:0] async_tx_en_out;
wire [101:0] async_rx_en_out;
wire [101:0] tx_en_out_nc;
wire [101:0] rx_en_out_nc;
wire [101:0] async_tx_en_out_nc;
wire [101:0] async_rx_en_out_nc;
wire [101:0] sdr_mode_en_out_nc;
wire [101:0] wkpu_en_out_nc;
wire [101:0] wkpd_en_out_nc;
wire [101:0] pad_en;
wire bert_clk_test;
// SDR_MODE needs to through redundancy
assign sdr_mode[29:0] = sdr_mode_en ? {30{1'b1}} : {30{1'b0}};
assign sdr_mode[31:30] = {2{1'b0}};
assign sdr_mode[41:32] = sdr_mode_en ? {10{1'b1}} : {10{1'b0}};
assign sdr_mode[49:42] = sdr_mode_en ? {8{1'b1}} : {8{1'b0}};
assign sdr_mode[51:50] = sdr_mode_en ? {2{1'b1}} : {2{1'b0}};
assign sdr_mode[59:52] = sdr_mode_en ? {8{1'b1}} : {8{1'b0}};
assign sdr_mode[69:60] = sdr_mode_en ? {10{1'b1}} : {10{1'b0}};
assign sdr_mode[71:70] = {2{1'b0}};
assign sdr_mode[101:72] = sdr_mode_en ? {30{1'b1}} : {30{1'b0}};
//==================================================
//Data Muxing between loop back data and actual data
//==================================================
assign tx_even_data_lpbk = rx_lpbk_mode ? tx_data_in_even : 40'd0;
assign tx_odd_data_lpbk = rx_lpbk_mode ? tx_data_in_odd : 40'd0;
assign rx_data_out_even[DATAWIDTH-1:4] = tx_lpbk_mode ?
rx_even_data_lpbk[DATAWIDTH-1:4] :
rx_even_data[DATAWIDTH-1:4];
assign rx_data_out_odd[DATAWIDTH-1:4] = tx_lpbk_mode ?
rx_odd_data_lpbk[DATAWIDTH-1:4] :
rx_odd_data[DATAWIDTH-1:4] ;
assign rx_data_out_even[0] =
bert_clk_test ? pad_to_adapter_dout_even[30] :
(tx_lpbk_mode ? rx_even_data_lpbk[0] : rx_even_data[0]);
assign rx_data_out_even[1] =
bert_clk_test ? pad_to_adapter_dout_even[31] :
(tx_lpbk_mode ? rx_even_data_lpbk[1] : rx_even_data[1]);
assign rx_data_out_even[2] =
bert_clk_test ? pad_to_adapter_dout_even[71] :
(tx_lpbk_mode ? rx_even_data_lpbk[2] : rx_even_data[2]);
assign rx_data_out_even[3] =
bert_clk_test ? pad_to_adapter_dout_even[70] :
(tx_lpbk_mode ? rx_even_data_lpbk[3] : rx_even_data[3]);
assign rx_data_out_odd[0] =
bert_clk_test ? pad_to_adapter_dout_odd[30] :
(tx_lpbk_mode ? rx_odd_data_lpbk[0] : rx_odd_data[0]);
assign rx_data_out_odd[1] =
bert_clk_test ? pad_to_adapter_dout_odd[31] :
(tx_lpbk_mode ? rx_odd_data_lpbk[1] : rx_odd_data[1]);
assign rx_data_out_odd[2] =
bert_clk_test ? pad_to_adapter_dout_odd[71] :
(tx_lpbk_mode ? rx_odd_data_lpbk[2] : rx_odd_data[2]);
assign rx_data_out_odd[3] =
bert_clk_test ? pad_to_adapter_dout_odd[70] :
(tx_lpbk_mode ? rx_odd_data_lpbk[3] : rx_odd_data[3]);
//------------------------------------------------------------------------------
// Logic to put pads with fault/unused in standby mode according to redundancy
//------------------------------------------------------------------------------
assign fault_stdby[0] = shift_en[0];
assign fault_stdby[1] = shift_en[0] | (shift_en[1] & ~shift_en[0]);
genvar i;
generate
for(i=2;i<50;i=i+1)
begin: tx_fault_stdby_en_gen
assign fault_stdby[i] = (shift_en[i] & ~shift_en[i-1]) |
(shift_en[i-1] & ~shift_en[i-2]);
end // block: tx_fault_stdby_en_gen
endgenerate
assign fault_stdby[50] = 1'b0;
assign fault_stdby[51] = 1'b0;
generate
for(i=99;i>51;i=i-1)
begin: rx_fault_stdby_en_gen
assign fault_stdby[i] = (shift_en[i] & ~shift_en[i+1]) |
(shift_en[i+1] & ~shift_en[i+2]);
end // block: rx_fault_stdby_en_gen
endgenerate
assign fault_stdby[100] = shift_en[101] | (shift_en[100] & ~shift_en[101]);
assign fault_stdby[101] = shift_en[101];
assign pad_en[101:0] = {102{csr_paden}};
//------------------------------------------------------------------------------
//assign tx_en[29:0] = {30{1'b1}}; Enable signal Should control w.r.to
//conf_done signal
assign tx_en[19:0] = iopad_rstb ? (gen1mode_en ? {20{1'b0}} : pad_en[19:0]) : {20{1'b0}};
assign tx_en[29:20] = iopad_rstb ? pad_en[29:20] : {10{1'b0}}; // for Tx IOs AVMM and Gen1 & Gen2
assign tx_en[31:30] = iopad_rstb ? pad_en[31:30] : {2{1'b0}}; // Near side forwarded clock
assign tx_en[41:32] = iopad_rstb ? pad_en[41:32] : {10{1'b0}}; // for TX IOs
assign tx_en[49:42] = {8{1'b0}};
assign tx_en[51:50] = {2{1'b0}};
assign tx_en[59:52] = {8{1'b0}};
assign tx_en[69:60] = iopad_rstb ? (rx_lpbk_mode ? pad_en[69:60] : {10{1'b0}}) : {10{1'b0}};
assign tx_en[71:70] = iopad_rstb ? {2{bert_clk_test | rx_lpbk_mode | tx_lpbk_mode}} : {2{1'b0}};
assign tx_en[81:72] = iopad_rstb ? (rx_lpbk_mode ? pad_en[81:72] : {10{1'b0}}) : {10{1'b0}}; // for Rx IOs
assign tx_en[101:82] = iopad_rstb ? (gen1mode_en ? {20{1'b0}} : (rx_lpbk_mode ? pad_en[101:82] :
{20{1'b0}})) : {20{1'b0}}; // for Rx IOs
assign async_tx_en[29:0] = {30{1'b0}}; // for Tx IOs
assign async_tx_en[31:30] = {2{1'b0}};
assign async_tx_en[41:32] = {10{1'b0}}; // for TX IOs
assign async_tx_en[42] = (iopad_rstb & gen1mode_en) ? pad_en[42] : 1'b0; // ns_rcv_clk
assign async_tx_en[43] = (iopad_rstb & gen1mode_en) ? pad_en[43] : 1'b0; // ns_rcv_clk_b
assign async_tx_en[44] = iopad_rstb ? pad_en[44] : 1'b0;
assign async_tx_en[45] = (iopad_rstb & gen1mode_en) ? pad_en[45] : 1'b0; // ns_sr_clk_b
assign async_tx_en[49:46] = iopad_rstb ? pad_en[49:46] : {4{1'b0}};
assign async_tx_en[51:50] = {2{1'b0}}; // spares
assign async_tx_en[59:52] = {8{1'b0}};
assign async_tx_en[69:60] = {10{1'b0}}; // for RX IOs
assign async_tx_en[71:70] = {2{1'b0}};
assign async_tx_en[101:72] = {30{1'b0}}; // for Rx IOs
assign async_rx_en[29:0] = {30{1'b0}}; // for Tx IOs
assign async_rx_en[31:30] = {2{1'b0}};
assign async_rx_en[41:32] = {10{1'b0}}; // for TX IOs
assign async_rx_en[49:42] = {8{1'b0}};
assign async_rx_en[51:50] = {2{1'b0}}; // spares
//------------------------------------------------------------------------------
// Rx async enable for signals not used on nearside loopback
//------------------------------------------------------------------------------
assign async_rx_en[55:52] =
iopad_rstb ?
( pad_en[55:52] & {4{(~(rx_lpbk_mode | tx_lpbk_mode))}} ) :
{4{1'b0}};
assign async_rx_en[56] = ( iopad_rstb & gen1mode_en ) ?
( pad_en[56] & (~(rx_lpbk_mode | tx_lpbk_mode)) ) :
1'b0; // fs_sr_clk_b
assign async_rx_en[57] = iopad_rstb ?
( pad_en[57] & (~(rx_lpbk_mode | tx_lpbk_mode)) ) :
1'b0;
assign async_rx_en[58] = ( iopad_rstb & gen1mode_en ) ?
( pad_en[58] & (~(rx_lpbk_mode | tx_lpbk_mode)) ) :
1'b0; // fs_rcv_clk_b
assign async_rx_en[59] = ( iopad_rstb & gen1mode_en ) ?
( pad_en[59] & (~(rx_lpbk_mode | tx_lpbk_mode)) ) :
1'b0; // fs_rcv_clk
//------------------------------------------------------------------------------
assign async_rx_en[69:60] = {10{1'b0}}; // for RX IOs
assign async_rx_en[71:70] = {2{1'b0}};
assign async_rx_en[101:72] = {30{1'b0}}; // for Rx IOs
assign rx_en[19:0] = iopad_rstb ? (gen1mode_en ? {20{1'b0}} : tx_lpbk_mode ? pad_en[19:0] :
{20{1'b0}}) : {20{1'b0}};
assign rx_en[29:20] = iopad_rstb ? (tx_lpbk_mode ? pad_en[29:20] : {10{1'b0}}) : {10{1'b0}};
assign rx_en[31:30] = iopad_rstb ? {2{bert_clk_test | tx_lpbk_mode}} : {2{1'b0}}; // Near side forwarded clock
assign rx_en[41:32] = iopad_rstb ? (tx_lpbk_mode ? pad_en[41:32] : {10{1'b0}}) : {10{1'b0}}; // for TX IOs
assign rx_en[49:42] = {8{1'b0}};
assign rx_en[51:50] = {2{1'b0}}; // spares
//------------------------------------------------------------------------------
// Rx async enable for signals not used on nearside loopback
//------------------------------------------------------------------------------
assign rx_en[55:52] =
iopad_rstb ?
( pad_en[55:52] & {4{(~(rx_lpbk_mode | tx_lpbk_mode))}} ) :
{4{1'b0}};
assign rx_en[56] = ( iopad_rstb & gen1mode_en ) ?
( pad_en[56] & (~(rx_lpbk_mode | tx_lpbk_mode)) ) :
1'b0; // fs_sr_clk_b
assign rx_en[57] = iopad_rstb ?
( pad_en[57] & (~(rx_lpbk_mode | tx_lpbk_mode)) ) :
1'b0;
assign rx_en[58] = ( iopad_rstb & gen1mode_en ) ?
( pad_en[58] & (~(rx_lpbk_mode | tx_lpbk_mode)) ) :
1'b0; // fs_rcv_clk_b
assign rx_en[59] = ( iopad_rstb & gen1mode_en ) ?
( pad_en[59] & (~(rx_lpbk_mode | tx_lpbk_mode)) ) :
1'b0; // fs_rcv_clk
//------------------------------------------------------------------------------
assign rx_en[69:60] = iopad_rstb ? pad_en[69:60] : {10{1'b0}}; // for RX IOs
assign rx_en[71:70] = iopad_rstb ? {2{bert_clk_test}} : {2{1'b0}}; // Far side forwarded clock
assign rx_en[81:72] = iopad_rstb ? pad_en[81:72] : {10{1'b0}}; // for Rx IOs
assign rx_en[101:82] = iopad_rstb ? (gen1mode_en ? {20{1'b0}} : pad_en[101:82]) : {20{1'b0}}; // for Rx IOs
assign wkpu_en_in[101:52] = {50{io_ctrl1_rx_wkpu_ff}};
assign wkpu_en_in[51:50] = {2{1'b0}};
assign wkpu_en_in[49:0] = {50{io_ctrl1_tx_wkpu_ff}};
assign wkpd_en_in[101:60] = {42{io_ctrl1_rx_wkpd_ff | (~iopad_rstb)}};
assign wkpd_en_in[51:50] = 2'b11;
assign wkpd_en_in[41:0] = {42{io_ctrl1_tx_wkpd_ff | (~iopad_rstb)}};
assign wkpd_en_in[42] = io_ctrl1_tx_wkpd_ff | (~gen1mode_en) | (~iopad_rstb); // ns_rcv_clk
assign wkpd_en_in[43] = io_ctrl1_tx_wkpd_ff | (~gen1mode_en) | (~iopad_rstb); // ns_rcv_clk_b
assign wkpd_en_in[44] = io_ctrl1_tx_wkpd_ff | (~iopad_rstb);
assign wkpd_en_in[45] = io_ctrl1_tx_wkpd_ff | (~gen1mode_en) | (~iopad_rstb);// ns_sr_clk_b
assign wkpd_en_in[49:46] = {4{io_ctrl1_tx_wkpd_ff | (~iopad_rstb)}};
assign wkpd_en_in[55:52] = {4{io_ctrl1_rx_wkpd_ff | (~iopad_rstb)}};
assign wkpd_en_in[56] = io_ctrl1_tx_wkpd_ff | (~gen1mode_en) | (~iopad_rstb); // fs_sr_clk_b
assign wkpd_en_in[57] = io_ctrl1_rx_wkpd_ff | (~iopad_rstb);
assign wkpd_en_in[58] = io_ctrl1_tx_wkpd_ff | (~gen1mode_en) | (~iopad_rstb); // fs_rcv_clk_b
assign wkpd_en_in[59] = io_ctrl1_tx_wkpd_ff | (~gen1mode_en) | (~iopad_rstb); // fs_rcv_clk
assign tx_en_to_pad = tx_en_out;
assign tx_async_en_to_pad = async_tx_en_out;
assign rx_en_to_pad = rx_en_out;
assign rx_async_en_to_pad = async_rx_en_out;
//=========================================
//Input Tx Even and Odd Data(From Adapter)
//=========================================
// PAD 0-29 - TX data
generate
for(i=0; i<15; i=i+1)
begin: adapter_to_pad_0_29
assign adapter_to_pad_data_even[2*i] = tx_data_in_even[38-(2*i)];
assign adapter_to_pad_data_even[(2*i)+1] = tx_data_in_even[39-(2*i)];
assign adapter_to_pad_data_odd[2*i] = tx_data_in_odd[38-(2*i)];
assign adapter_to_pad_data_odd[(2*i)+1] = tx_data_in_odd[39-(2*i)];
end
endgenerate
// PAD 32-41 - TX data
generate
for(i=0; i<5; i=i+1)
begin: adapter_to_pad_32_41
assign adapter_to_pad_data_even[32+(2*i)] = tx_data_in_even[8-(2*i)];
assign adapter_to_pad_data_even[32+(2*i)+1] = tx_data_in_even[9-(2*i)];
assign adapter_to_pad_data_odd[32+(2*i)] = tx_data_in_odd[8-(2*i)];
assign adapter_to_pad_data_odd[32+(2*i)+1] = tx_data_in_odd[9-(2*i)];
end
endgenerate
//==============================================
// Loopback data at Transmitter IO Pads
//=============================================
// PAD 60-69 - RX data loop back
generate
for(i=0; i<5; i=i+1)
begin: adapter_to_pad_60_69
assign adapter_to_pad_data_even[60+(2*i)] = tx_even_data_lpbk[1+(2*i)];
assign adapter_to_pad_data_even[60+(2*i)+1] = tx_even_data_lpbk[2*i];
assign adapter_to_pad_data_odd[60+(2*i)] = tx_odd_data_lpbk[1+(2*i)];
assign adapter_to_pad_data_odd[60+(2*i)+1] = tx_odd_data_lpbk[2*i];
end
endgenerate
// PAD 72-101 - RX data loopback
generate
for(i=0; i<15; i=i+1)
begin: adapter_to_pad_72_101
assign adapter_to_pad_data_even[72+(2*i)] = tx_even_data_lpbk[11+(2*i)];
assign adapter_to_pad_data_even[72+(2*i)+1] = tx_even_data_lpbk[10+(2*i)];
assign adapter_to_pad_data_odd[72+(2*i)] = tx_odd_data_lpbk[11+(2*i)];
assign adapter_to_pad_data_odd[72+(2*i)+1] = tx_odd_data_lpbk[10+(2*i)];
end
endgenerate
//Driving constant value(1'b0) to unused bits
generate
for(i=42; i<60; i=i+1)
begin: adapter_to_pad_even_42_58
assign adapter_to_pad_data_even[i] = 1'b0;
assign adapter_to_pad_data_odd[i] = 1'b0;
end
endgenerate
// Selection of clock test logic to observe forward clock from the bumps
// In this mode BERT generators drives the clock pads and BERT checkers
// receive data to check stuck at failures in clock path logic.
assign bert_clk_test = fwd_clk_test_sync &
(rx_lpbk_mode | tx_lpbk_mode);
//Near side Loopback Mode
assign adapter_to_pad_data_even[70] = bert_clk_test ? tx_data_in_even[3] : 1'b1;
assign adapter_to_pad_data_even[71] = bert_clk_test ? tx_data_in_even[2] : 1'b0;
assign adapter_to_pad_data_odd[70] = bert_clk_test ? tx_data_in_odd[3] : 1'b0;
assign adapter_to_pad_data_odd[71] = bert_clk_test ? tx_data_in_odd[2] : 1'b1;
//==============================================
//ns_fwd_clk Even Data
assign adapter_to_pad_data_even[31] = bert_clk_test ? tx_data_in_even[1] : 1'b1;
assign adapter_to_pad_data_even[30] = bert_clk_test ? tx_data_in_even[0] : 1'b0;
//ns_fwd_clk Odd Data
assign adapter_to_pad_data_odd[31] = bert_clk_test ? tx_data_in_odd[1] : 1'b0;
assign adapter_to_pad_data_odd[30] = bert_clk_test ? tx_data_in_odd[0] : 1'b1;
//================================================
//Loop back Data from Transmitter Redundancy ouput
//================================================
//Loopback Data should come from Analog
// PAD 60-69 - RX data
generate
for(i=0; i<5; i=i+1)
begin: rx_pad_to_adapt_lpb_0_9
assign rx_even_data_lpbk[1+(2*i)] = pad_to_adapter_dout_even[40-(2*i)+1];
assign rx_even_data_lpbk[2*i] = pad_to_adapter_dout_even[40-(2*i)];
assign rx_odd_data_lpbk[1+(2*i)] = pad_to_adapter_dout_odd[40-(2*i)+1];
assign rx_odd_data_lpbk[2*i] = pad_to_adapter_dout_odd[40-(2*i)];
end
endgenerate
// PAD 72-101 - RX data
generate
for(i=0; i<15; i=i+1)
begin: rx_pad_to_adapt_lpb_10_39
assign rx_even_data_lpbk[10+(2*i)+1] = pad_to_adapter_dout_even[28-(2*i)+1];
assign rx_even_data_lpbk[10+(2*i)] = pad_to_adapter_dout_even[28-(2*i)];
assign rx_odd_data_lpbk[10+(2*i)+1] = pad_to_adapter_dout_odd[28-(2*i)+1];
assign rx_odd_data_lpbk[10+(2*i)] = pad_to_adapter_dout_odd[28-(2*i)];
end
endgenerate
//============================================
//Output(Rx Even and Odd Data Bits) To Adapter
//============================================
// PAD 60-69 - RX data
generate
for(i=0; i<5; i=i+1)
begin: rx_pad_to_adapt_data_60_69
assign rx_even_data[1+(2*i)] = pad_to_adapter_dout_even[60+(2*i)];
assign rx_even_data[2*i] = pad_to_adapter_dout_even[60+(2*i)+1];
assign rx_odd_data[1+(2*i)] = pad_to_adapter_dout_odd[60+(2*i)];
assign rx_odd_data[2*i] = pad_to_adapter_dout_odd[60+(2*i)+1];
end
endgenerate
// PAD 72-101 - RX data
generate
for(i=0; i<15; i=i+1)
begin: rx_pad_to_adapt_data_72_101
assign rx_even_data[11+(2*i)] = pad_to_adapter_dout_even[72+(2*i)];
assign rx_even_data[10+(2*i)] = pad_to_adapter_dout_even[72+(2*i)+1];
assign rx_odd_data[11+(2*i)] = pad_to_adapter_dout_odd[72+(2*i)];
assign rx_odd_data[10+(2*i)] = pad_to_adapter_dout_odd[72+(2*i)+1];
end
endgenerate
//==========================================
// Async Signals From Adapter
//==========================================
assign adapter_to_pad_async[49] = ns_adapter_rstn;
assign adapter_to_pad_async[48] = ns_mac_rdy ;
assign adapter_to_pad_async[47] = ns_sr_load ;
assign adapter_to_pad_async[46] = ns_sr_data ;
assign adapter_to_pad_async[45] = ~ns_sr_clk ; // FIX ME !!!
assign adapter_to_pad_async[44] = ns_sr_clk ;
assign adapter_to_pad_async[43] = ~ns_rcv_clk; // FIX ME !!!
assign adapter_to_pad_async[42] = ns_rcv_clk;
assign adapter_to_pad_async[31] = 1'b0; // FIX ME !!!
assign adapter_to_pad_async[30] = 1'b0;
assign adapter_to_pad_async[29:0] = {30{1'b0}};
assign adapter_to_pad_async[41:32] = {10{1'b0}};
assign adapter_to_pad_async[101:50] = {52{1'b0}};
//==========================================
//Async signals to Adapter
//==========================================
assign fs_rcv_clk_out = async_data_to_adapter[59];
assign fs_sr_clk_out = async_data_to_adapter[57];
assign fs_sr_data_out = async_data_to_adapter[55];
assign fs_sr_load_out = async_data_to_adapter[54];
assign fs_mac_rdy_out = async_data_to_adapter[53];
assign fs_adapter_rstn_out = async_data_to_adapter[52] |
rx_lpbk_mode |
tx_lpbk_mode;
//=============================================
//Redundancy Module Instantiation
//=============================================
aib_redundancy_wrp
i_aib_redundancy_adapter_to_pad (
.pad_shift (shift_en ),
.pad_even_data_in (adapter_to_pad_data_even ),
.pad_odd_data_in (adapter_to_pad_data_odd ),
.pad_async_in (adapter_to_pad_async ),
.pad_async_out (async_data_to_pad ),
.pad_even_data_out (even_data_to_pad ),
.pad_odd_data_out (odd_data_to_pad ),
.pad_tx_en (tx_en ),
.pad_rx_en (rx_en ),
.pad_async_tx_en (async_tx_en ),
.pad_async_rx_en (async_rx_en ),
.pad_sdr_mode_en (sdr_mode ),
.wkpu_en_in (wkpu_en_in[101:0] ),
.wkpd_en_in (wkpd_en_in[101:0] ),
.pad_tx_en_out (tx_en_out ),
.pad_rx_en_out (rx_en_out ),
.pad_async_tx_en_out(async_tx_en_out ),
.pad_async_rx_en_out(async_rx_en_out ),
.pad_sdr_mode_en_out(sdr_mode_en_to_pad ),
.wkpu_en_out (wkpu_en_out[101:0] ),
.wkpd_en_out (wkpd_en_out[101:0] )
);
aib_redundancy_wrp
i_aib_redundancy_pad_to_adapter (
.pad_shift (shift_en ),
.pad_even_data_in (data_even_from_pad ),
.pad_odd_data_in (data_odd_from_pad ),
.pad_async_in (pad_to_adapter_async_in ),
.pad_async_out (async_data_to_adapter ),
.pad_even_data_out (pad_to_adapter_dout_even ),
.pad_odd_data_out (pad_to_adapter_dout_odd ),
.pad_tx_en ( {102{1'b0}} ), //Drive to constant values(102'b0)
.pad_rx_en ( {102{1'b0}} ),
.pad_async_tx_en ( {102{1'b0}} ),
.pad_async_rx_en ( {102{1'b0}} ),
.pad_sdr_mode_en ( {102{1'b0}} ),
.wkpu_en_in ( {102{1'b0}} ),
.wkpd_en_in ( {102{1'b0}} ),
.pad_tx_en_out (tx_en_out_nc ),
.pad_rx_en_out (rx_en_out_nc ),
.pad_async_tx_en_out(async_tx_en_out_nc ),
.pad_async_rx_en_out(async_rx_en_out_nc ),
.pad_sdr_mode_en_out(sdr_mode_en_out_nc ),
.wkpu_en_out (wkpu_en_out_nc[101:0] ),
.wkpd_en_out (wkpd_en_out_nc[101:0] )
);
endmodule |
module aib_redundancy_wrp (
input [101:0] pad_shift,
input [101:0] pad_even_data_in,
input [101:0] pad_odd_data_in,
input [101:0] pad_async_in,
output wire [101:0] pad_async_out,
output wire [101:0] pad_even_data_out,
output wire [101:0] pad_odd_data_out,
input [101:0] pad_tx_en,
input [101:0] pad_rx_en,
input [101:0] pad_async_tx_en,
input [101:0] pad_async_rx_en,
input [101:0] pad_sdr_mode_en,
input [101:0] wkpu_en_in,
input [101:0] wkpd_en_in,
output wire [101:0] pad_tx_en_out,
output wire [101:0] pad_rx_en_out,
output wire [101:0] pad_async_tx_en_out,
output wire [101:0] pad_async_rx_en_out,
output wire [101:0] pad_sdr_mode_en_out,
output wire [101:0] wkpu_en_out,
output wire [101:0] wkpd_en_out
);
//===========================================
// Microbumps that conect to only one signal
//===========================================
assign pad_even_data_out[0] = pad_even_data_in[0];
assign pad_odd_data_out[0] = pad_odd_data_in[0];
assign pad_even_data_out[1] = pad_even_data_in[1];
assign pad_odd_data_out[1] = pad_odd_data_in[1];
assign pad_even_data_out[100] = (pad_shift[100] == 1'b1) ? pad_even_data_in[98] : pad_even_data_in[100];
assign pad_odd_data_out[100] = (pad_shift[100] == 1'b1) ? pad_odd_data_in[98] : pad_odd_data_in[100];
assign pad_even_data_out[101] = (pad_shift[101] == 1'b1) ? pad_even_data_in[99] : pad_even_data_in[101];
assign pad_odd_data_out[101] = (pad_shift[101] == 1'b1) ? pad_odd_data_in[99] : pad_odd_data_in[101];
assign pad_async_out[0] = pad_async_in[0];
assign pad_async_out[1] = pad_async_in[1];
assign pad_async_out[100] = (pad_shift[100] == 1'b1) ? pad_async_in[98] : pad_async_in[100];
assign pad_async_out[101] = (pad_shift[101] == 1'b1) ? pad_async_in[99] : pad_async_in[101];
assign pad_tx_en_out[0] = pad_tx_en[0];
assign pad_tx_en_out[1] = pad_tx_en[1];
assign pad_tx_en_out[100] = pad_tx_en[100];
assign pad_tx_en_out[101] = pad_tx_en[101];
assign pad_rx_en_out[0] = pad_rx_en[0];
assign pad_rx_en_out[1] = pad_rx_en[1];
assign pad_rx_en_out[100] = pad_rx_en[100];
assign pad_rx_en_out[101] = pad_rx_en[101];
assign pad_async_tx_en_out[0] = pad_async_tx_en[0];
assign pad_async_tx_en_out[1] = pad_async_tx_en[1];
assign pad_async_tx_en_out[100] = pad_async_tx_en[100];
assign pad_async_tx_en_out[101] = pad_async_tx_en[101];
assign pad_async_rx_en_out[0] = pad_async_rx_en[0];
assign pad_async_rx_en_out[1] = pad_async_rx_en[1];
assign pad_async_rx_en_out[100] = pad_async_rx_en[100];
assign pad_async_rx_en_out[101] = pad_async_rx_en[101];
assign pad_sdr_mode_en_out[0] = pad_sdr_mode_en[0];
assign pad_sdr_mode_en_out[1] = pad_sdr_mode_en[1];
assign pad_sdr_mode_en_out[100] = pad_sdr_mode_en[100];
assign pad_sdr_mode_en_out[101] = pad_sdr_mode_en[101];
assign wkpu_en_out[0] = wkpu_en_in[0];
assign wkpu_en_out[1] = wkpu_en_in[1];
assign wkpu_en_out[100] = wkpu_en_in[100];
assign wkpu_en_out[101] = wkpu_en_in[101];
assign wkpd_en_out[0] = wkpd_en_in[0];
assign wkpd_en_out[1] = wkpd_en_in[1];
assign wkpd_en_out[100] = wkpd_en_in[100];
assign wkpd_en_out[101] = wkpd_en_in[101];
//=======================================================
// Microbumps connect to three signals(aib[50] & aib[51])
//=======================================================
assign pad_even_data_out[50] = (pad_shift[48] == 1'b1) ? pad_even_data_in[48] : pad_even_data_in[50];
assign pad_odd_data_out[50] = (pad_shift[48] == 1'b1) ? pad_odd_data_in[48] : pad_odd_data_in[50];
assign pad_even_data_out[51] = (pad_shift[49] == 1'b1) ? pad_even_data_in[49] : pad_even_data_in[51];
assign pad_odd_data_out[51] = (pad_shift[49] == 1'b1) ? pad_odd_data_in[49] : pad_even_data_in[51];
assign pad_async_out[50] = (pad_shift[48] == 1'b1) ? pad_async_in[48] : pad_async_in[50];
assign pad_async_out[51] = (pad_shift[49] == 1'b1) ? pad_async_in[49] : pad_async_in[51];
//Muxing Enable signals
assign pad_tx_en_out[50] = (pad_shift[48] == 1'b1) ? pad_tx_en[48] : (pad_shift[52] == 1'b1) ? pad_tx_en[52] : pad_tx_en[50];
assign pad_tx_en_out[51] = (pad_shift[49] == 1'b1) ? pad_tx_en[49] : (pad_shift[53] == 1'b1) ? pad_tx_en[53] : pad_tx_en[51];
assign pad_rx_en_out[50] = (pad_shift[48] == 1'b1) ? pad_rx_en[48] : (pad_shift[52] == 1'b1) ? pad_rx_en[52] : pad_rx_en[50];
assign pad_rx_en_out[51] = (pad_shift[49] == 1'b1) ? pad_rx_en[49] : (pad_shift[53] == 1'b1) ? pad_rx_en[53] : pad_rx_en[51];
assign pad_async_tx_en_out[50] = (pad_shift[48] == 1'b1) ? pad_async_tx_en[48] : (pad_shift[52] == 1'b1) ? pad_async_tx_en[52] : pad_async_tx_en[50];
assign pad_async_tx_en_out[51] = (pad_shift[49] == 1'b1) ? pad_async_tx_en[49] : (pad_shift[53] == 1'b1) ? pad_async_tx_en[53] : pad_async_tx_en[51];
assign pad_async_rx_en_out[50] = (pad_shift[48] == 1'b1) ? pad_async_rx_en[48] : (pad_shift[52] == 1'b1) ? pad_async_rx_en[52] : pad_async_rx_en[50];
assign pad_async_rx_en_out[51] = (pad_shift[49] == 1'b1) ? pad_async_rx_en[49] : (pad_shift[53] == 1'b1) ? pad_async_rx_en[53] : pad_async_rx_en[51];
assign pad_sdr_mode_en_out[50] = (pad_shift[48] == 1'b1) ? pad_sdr_mode_en[48] : (pad_shift[52] == 1'b1) ? pad_sdr_mode_en[52] : pad_sdr_mode_en[50];
assign pad_sdr_mode_en_out[51] = (pad_shift[49] == 1'b1) ? pad_sdr_mode_en[49] : (pad_shift[53] == 1'b1) ? pad_sdr_mode_en[53] : pad_sdr_mode_en[51];
assign wkpu_en_out[50] = (pad_shift[48] == 1'b1) ? wkpu_en_in[48] :
(pad_shift[52] == 1'b1) ? wkpu_en_in[52] : wkpu_en_in[50];
assign wkpu_en_out[51] = (pad_shift[49] == 1'b1) ? wkpu_en_in[49] :
(pad_shift[53] == 1'b1) ? wkpu_en_in[53] : wkpu_en_in[51];
assign wkpd_en_out[50] = (pad_shift[48] == 1'b1) ? wkpd_en_in[48] :
(pad_shift[52] == 1'b1) ? wkpd_en_in[52] : wkpd_en_in[50];
assign wkpd_en_out[51] = (pad_shift[49] == 1'b1) ? wkpd_en_in[49] :
(pad_shift[53] == 1'b1) ? wkpd_en_in[53] : wkpd_en_in[51];
genvar i;
//===================================================
// Shift up from Lower numbered Microbumps [0 to 49]
//===================================================
generate
for(i=2; i<50; i=i+1)
begin: iopads_0_49
aib_redundancy_logic
i_aib_redundancy (
.idata_in0_even(pad_even_data_in[i]),
.idata_in1_even(pad_even_data_in[i-2]),
.data_out_even (pad_even_data_out[i]),
.idata_in0_odd(pad_odd_data_in[i]),
.idata_in1_odd(pad_odd_data_in[i-2]),
.data_out_odd (pad_odd_data_out[i]),
//Async Signals
.async_in0(pad_async_in[i]),
.async_in1(pad_async_in[i-2]),
.async_out(pad_async_out[i]),
.tx_en0(pad_tx_en[i]),
.tx_en1(pad_tx_en[i-2]),
.tx_en_out(pad_tx_en_out[i]),
.rx_en0(pad_rx_en[i]),
.rx_en1(pad_rx_en[i-2]),
.rx_en_out(pad_rx_en_out[i]),
.async_tx_en0(pad_async_tx_en[i]),
.async_tx_en1(pad_async_tx_en[i-2]),
.async_tx_en_out(pad_async_tx_en_out[i]),
.async_rx_en0(pad_async_rx_en[i]),
.async_rx_en1(pad_async_rx_en[i-2]),
.async_rx_en_out(pad_async_rx_en_out[i]),
.sdr_mode_en0(pad_sdr_mode_en[i]),
.sdr_mode_en1(pad_sdr_mode_en[i-2]),
.sdr_mode_en_out(pad_sdr_mode_en_out[i]),
.wkpu_en_in0 (wkpu_en_in[i]),
.wkpu_en_in1 (wkpu_en_in[i-2]),
.wkpu_en_out (wkpu_en_out[i]),
.wkpd_en_in0 (wkpd_en_in[i]),
.wkpd_en_in1 (wkpd_en_in[i-2]),
.wkpd_en_out (wkpd_en_out[i]),
.shift_en(pad_shift[i])
);
end
endgenerate
//=====================================================
// Shift down from Higher numbered Microbump[99 to 52]
//=====================================================
generate
for(i=99; i>51; i=i-1)
begin: iopads_52_99
aib_redundancy_logic
i_aib_redundancy (
.idata_in0_even(pad_even_data_in[i]),
.idata_in1_even(pad_even_data_in[i-2]),
.data_out_even (pad_even_data_out[i]),
.idata_in0_odd(pad_odd_data_in[i]),
.idata_in1_odd(pad_odd_data_in[i-2]),
.data_out_odd (pad_odd_data_out[i]),
//Async Signals
.async_in0(pad_async_in[i]),
.async_in1(pad_async_in[i-2]),
.async_out(pad_async_out[i]),
.tx_en0(pad_tx_en[i]),
.tx_en1(pad_tx_en[i+2]),
.tx_en_out(pad_tx_en_out[i]),
.rx_en0(pad_rx_en[i]),
.rx_en1(pad_rx_en[i+2]),
.rx_en_out(pad_rx_en_out[i]),
.async_tx_en0(pad_async_tx_en[i]),
.async_tx_en1(pad_async_tx_en[i+2]),
.async_tx_en_out(pad_async_tx_en_out[i]),
.async_rx_en0(pad_async_rx_en[i]),
.async_rx_en1(pad_async_rx_en[i+2]),
.async_rx_en_out(pad_async_rx_en_out[i]),
.sdr_mode_en0(pad_sdr_mode_en[i]),
.sdr_mode_en1(pad_sdr_mode_en[i+2]),
.sdr_mode_en_out(pad_sdr_mode_en_out[i]),
.wkpu_en_in0 (wkpu_en_in[i]),
.wkpu_en_in1 (wkpu_en_in[i+2]),
.wkpu_en_out (wkpu_en_out[i]),
.wkpd_en_in0 (wkpd_en_in[i]),
.wkpd_en_in1 (wkpd_en_in[i+2]),
.wkpd_en_out (wkpd_en_out[i]),
.shift_en(pad_shift[i])
);
end
endgenerate
endmodule |
module aib_rx_dbi (
// Inputs
input wire rst_n, // Asynchronous reset
input wire clk, // Clock
input wire [79:0] data_in, // Data input before DBI logic
input wire dbi_en, // Data inversion enable
// Outputs
output wire [79:0] data_out // Output data after DBI logic
);
wire [3 :0] dbi_calc; // Bits 79, 78, 39 and 38 used on DBI calculation
wire [37:0] dbi_dat_lo; // Low word with DB calculation - bits from 37-0
wire [37:0] dbi_dat_hi; // High word with DB calculation - bits from 77-40
reg [79:0] dbi_data_out; // Register data after DBI calculation
// DBI output mux selects data accoding to DBI enable
assign data_out = dbi_en? dbi_data_out : data_in;
// Data bits 79, 78, 39 and 38 used on DBI calculation
assign dbi_calc = {data_in[79], data_in[78], data_in[39], data_in[38]};
// Calculation of DBI low word and DBI high word
genvar j; // Generate index
generate
for (j=0; j<19; j=j+1)
begin:data_out_gen
assign dbi_dat_lo[2*j] = data_in[2*j] ^dbi_calc[0];
assign dbi_dat_lo[2*j+1] = data_in[2*j+1] ^dbi_calc[1];
assign dbi_dat_hi[2*j] = data_in[2*j+40] ^dbi_calc[2];
assign dbi_dat_hi[2*j+1] = data_in[2*j+1+40]^dbi_calc[3];
end // block data_out_gen
endgenerate
// Output register to latch DBI calculation
always @(posedge clk or negedge rst_n)
begin: dbi_data_out_register
if (!rst_n)
begin
dbi_data_out <= 80'h0;
end
else
begin
dbi_data_out <= {dbi_calc[3:2], dbi_dat_hi, dbi_calc[1:0], dbi_dat_lo};
end
end // block: dbi_data_out_register
endmodule // aib_rx_dbi |
module aib_rxfifo_clk_gating #(
parameter FF_DEPTH = 16,
parameter DEPTH4 = FF_DEPTH * 4,
parameter PNT_S = $clog2(DEPTH4)
)
(
// Outputs
output [FF_DEPTH-1:0] rff_clk_39_0, // Clocks for word 39-0 of RX FIFO
output [FF_DEPTH-1:0] rff_clk_79_40, // Clocks for word 79-40 of RX FIFO
output [FF_DEPTH-1:0] rff_clk_119_80,
output [FF_DEPTH-1:0] rff_clk_159_120,
output [FF_DEPTH-1:0] rff_clk_199_160,
output [FF_DEPTH-1:0] rff_clk_239_200,
output [FF_DEPTH-1:0] rff_clk_279_240,
output [FF_DEPTH-1:0] rff_clk_319_280,
// Inputs
input rxf_wr_clk, // RX FIFO write clock
input rxf_wr_en, // RX FIFO write enable
input [PNT_S-1:0] rxf_pnt_ff, // Indicates RX FIFO element to be written
input m_gen2_mode, // Indicates RX FIFO operates in GEN2 mode
input scan_en // Scan enable
);
localparam [1:0] FIFO1X = 2'b00; // FIFO 1X mode
localparam [1:0] FIFO2X = 2'b01; // FIFO 2X mode
localparam [1:0] FIFO4X = 2'b10; // FIFO 4X mode
localparam [1:0] WD_79_0 = 2'd0;
localparam [1:0] WD_159_80 = 2'd1;
localparam [1:0] WD_239_160 = 2'd2;
localparam [1:0] WD_319_240 = 2'd3;
reg [FF_DEPTH-1:0] rff_clk_39_0_en; // Clocks enable for word 39-0
reg [FF_DEPTH-1:0] rff_clk_79_40_en; // Clocks enable for word 79-40
reg [FF_DEPTH-1:0] rff_clk_119_80_en;
reg [FF_DEPTH-1:0] rff_clk_159_120_en;
reg [FF_DEPTH-1:0] rff_clk_199_160_en;
reg [FF_DEPTH-1:0] rff_clk_239_200_en;
reg [FF_DEPTH-1:0] rff_clk_279_240_en;
reg [FF_DEPTH-1:0] rff_clk_319_280_en;
// RX FIFO clock enable logic
always @(*)
begin: rx_fifo_clk_en_logic
rff_clk_39_0_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
rff_clk_79_40_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
rff_clk_119_80_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
rff_clk_159_120_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
rff_clk_199_160_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
rff_clk_239_200_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
rff_clk_279_240_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
rff_clk_319_280_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
if(m_gen2_mode)// GEN2
begin
case(rxf_pnt_ff[1:0])
WD_79_0:
begin
rff_clk_39_0_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
rff_clk_79_40_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
end
WD_159_80:
begin
rff_clk_119_80_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
rff_clk_159_120_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
end
WD_239_160:
begin
rff_clk_199_160_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
rff_clk_239_200_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
end
WD_319_240:
begin
rff_clk_279_240_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
rff_clk_319_280_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
end
endcase
end // GEN2
else // GEN1
begin
case(rxf_pnt_ff[1:0])
WD_79_0:
begin
rff_clk_39_0_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
end
WD_159_80:
begin
rff_clk_119_80_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
end
WD_239_160:
begin
rff_clk_199_160_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
end
WD_319_240:
begin
rff_clk_279_240_en[rxf_pnt_ff[PNT_S-1:2]] = rxf_wr_en;
end
endcase
end
end // blockk: rx_fifo_clk_en_logic
genvar i;
// Clock gates for FIFO word 39-0
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_39_0_gen
clk_gate_cel clk_gate_cel_39_0(
.clkout (rff_clk_39_0[i]), // Clock gated
.clk (rxf_wr_clk), // Clock input
.en (rff_clk_39_0_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_39_0_gen
endgenerate
// Clock gates for FIFO word 79-40
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_79_40_gen
clk_gate_cel clk_gate_cel_79_40(
.clkout (rff_clk_79_40[i]), // Clock gated
.clk (rxf_wr_clk), // Clock input
.en (rff_clk_79_40_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_79_40_gen
endgenerate
// Clock gates for FIFO word 119-80
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_119_80_gen
clk_gate_cel clk_gate_cel_119_80(
.clkout (rff_clk_119_80[i]), // Clock gated
.clk (rxf_wr_clk), // Clock input
.en (rff_clk_119_80_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_119_80_gen
endgenerate
// Clock gates for FIFO word 159-120
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_159_120_gen
clk_gate_cel clk_gate_cel_159_120(
.clkout (rff_clk_159_120[i]), // Clock gated
.clk (rxf_wr_clk), // Clock input
.en (rff_clk_159_120_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_159_120_gen
endgenerate
// Clock gates for FIFO word 199-160
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_199_160_gen
clk_gate_cel clk_gate_cel_199_160(
.clkout (rff_clk_199_160[i]), // Clock gated
.clk (rxf_wr_clk), // Clock input
.en (rff_clk_199_160_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_199_160_gen
endgenerate
// Clock gates for FIFO word 239-200
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_239_200_gen
clk_gate_cel clk_gate_cel_239_200(
.clkout (rff_clk_239_200[i]), // Clock gated
.clk (rxf_wr_clk), // Clock input
.en (rff_clk_239_200_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_239_200_gen
endgenerate
// Clock gates for FIFO word 279-240
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_279_240_gen
clk_gate_cel clk_gate_cel_279_240(
.clkout (rff_clk_279_240[i]), // Clock gated
.clk (rxf_wr_clk), // Clock input
.en (rff_clk_279_240_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_279_240_gen
endgenerate
// Clock gates for FIFO word 319-280
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_319_280_gen
clk_gate_cel clk_gate_cel_319_280(
.clkout (rff_clk_319_280[i]), // Clock gated
.clk (rxf_wr_clk), // Clock input
.en (rff_clk_319_280_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_319_280_gen
endgenerate
endmodule // aib_rxfifo_clk_gating |
module aib_rx_bert #(
parameter [0:0] BERT_BUF_MODE_EN = 1 // Enables Buffer mode for BERT
)
(
// Inputs
input clk, // Rx BERT clock
input rstn, // Active low asynchronous reset
input [ 3:0] rx_rst_pulse, // Resets synchronously RX BERT logic
input [ 3:0] rx_start_pulse, // Starts data comparison
input [ 3:0] seed_in_en, // Seed input mode enable
input [ 5:0] chk3_lane_sel_ff, // Lane selection to checker3
input [ 5:0] chk2_lane_sel_ff, // Lane selection to checker2
input [ 5:0] chk1_lane_sel_ff, // Lane selection to checker1
input [ 5:0] chk0_lane_sel_ff, // Lane selection to checker0
input [ 2:0] chk3_ptrn_sel_ff, // Pattern selection to checker 3
input [ 2:0] chk2_ptrn_sel_ff, // Pattern selection to checker 2
input [ 2:0] chk1_ptrn_sel_ff, // Pattern selection to checker 1
input [ 2:0] chk0_ptrn_sel_ff, // Pattern selection to checker 0
input [319:0] rx_bert_data_i, // Data bits from RX FIFO
input sdr_mode, // Single data rate mode
input [1:0] r_fifo_mode, // RX FIFO mode
input m_gen2_mode, // GEN2 mode selector
// Outputs
output reg [ 48:0] rbert_bit_cnt_ff, // Bit counter
output [ 15:0] biterr_cnt_chk3, // Bit error counter from checker3
output [ 15:0] biterr_cnt_chk2, // Bit error counter from checker2
output [ 15:0] biterr_cnt_chk1, // Bit error counter from checker1
output [ 15:0] biterr_cnt_chk0, // Bit error counter from checker0
output [127:0] rx_bert3_data, // Receive data in RX BERT3
output [127:0] rx_bert2_data, // Receive data in RX BERT2
output [127:0] rx_bert1_data, // Receive data in RX BERT1
output [127:0] rx_bert0_data, // Receive data in RX BERT0
output [ 3:0] rbert_running_ff // Indicates RX BERT checker is running
);
//------------------------------------------------------------------------------
// Local Parameters
//------------------------------------------------------------------------------
localparam FIFO_1X = 2'b00; //Full rate
localparam FIFO_2X = 2'b01; //Half rate
localparam FIFO_4X = 2'b10; //Quarter Rate
// Defines the number of bits to be considered in RX data:
localparam [1:0] NBIT1 = 2'b00; // 1 bit per clock
localparam [1:0] NBIT2 = 2'b01; // 2 bit per clock
localparam [1:0] NBIT4 = 2'b10; // 4 bit per clock
localparam [1:0] NBIT8 = 2'b11; // 8 bit per clock
integer i; // Integer to attribute bits for each lane
reg [39:0][7:0] rx_bert_lanes; // Bits received in each lane
reg [ 1:0] rx_sft_nb; // Selects the number of valid bits in RX BERT
// checker
reg [ 7:0] rx_bert_data_chk0_ff; // Bits of lane selected to Checker0
reg [ 7:0] rx_bert_data_chk1_ff; // Bits of lane selected to Checker1
reg [ 7:0] rx_bert_data_chk2_ff; // Bits of lane selected to Checker2
reg [ 7:0] rx_bert_data_chk3_ff; // Bits of lane selected to Checker3
reg [48:0] rbert_bit_cnt_in;
reg co1_nc;
wire [7:0] rx_bert_data_chk0; // Bits of lane selected to Checker0
wire [7:0] rx_bert_data_chk1; // Bits of lane selected to Checker1
wire [7:0] rx_bert_data_chk2; // Bits of lane selected to Checker2
wire [7:0] rx_bert_data_chk3; // Bits of lane selected to Checker3
//Logic to select the number of bits per clock
always @(*)
begin: rx_sft_nb_logic
case(r_fifo_mode)
FIFO_1X: // FIFO 1:1 rate
begin
if(sdr_mode)
rx_sft_nb[1:0] = 2'b00; // 1 bits per clock
else
rx_sft_nb[1:0] = 2'b01; // 2 bits per clock
end
FIFO_2X: // FIFO 1:2 rate
begin
if(sdr_mode)
rx_sft_nb[1:0] = 2'b01; // 2 bits per clock
else
rx_sft_nb[1:0] = 2'b10; // 4 bits per clock
end
FIFO_4X: // FIFO 1:4 rate
begin
if(sdr_mode)
rx_sft_nb[1:0] = 2'b10; // 4 bits per clock
else
rx_sft_nb[1:0] = 2'b11; // 8 bits per clock
end
default: // register mode - BERT does not support
begin
if(sdr_mode)
rx_sft_nb[1:0] = 2'b00; // 1 bits per clock
else
rx_sft_nb[1:0] = 2'b01; // 2 bits per clock
end
endcase
end // block: rx_sft_nb_logic
// Grouped 8-bit sequence per each lane
always @(*)
begin: rx_bert_lanes_logic
if(m_gen2_mode) // GEN 2 mode
begin: rx_bert_lanes_gen2
for(i=0;i<40;i=i+1)
begin
rx_bert_lanes[i] = { rx_bert_data_i[(2*i)+241],
rx_bert_data_i[(2*i)+240],
rx_bert_data_i[(2*i)+161],
rx_bert_data_i[(2*i)+160],
rx_bert_data_i[(2*i)+81],
rx_bert_data_i[(2*i)+80],
rx_bert_data_i[(2*i)+1],
rx_bert_data_i[2*i] };
end
end // GEN 2 mode
else // GEN1 mode
begin: rx_bert_lanes_gen1
for(i=0;i<20;i=i+1)
begin
if(sdr_mode) // SDR mode in GEN1 mode
begin
rx_bert_lanes[i] = { rx_bert_data_i[(2*i)+241], // Unused
rx_bert_data_i[(2*i)+240], // Unused
rx_bert_data_i[(2*i)+161], // Unused
rx_bert_data_i[(2*i)+160], // Unused
rx_bert_data_i[(2*i)+81], // Unused
rx_bert_data_i[(2*i)+80], // Unused
rx_bert_data_i[(2*i)+40],
rx_bert_data_i[2*i] };
end // SDR mode
else // DDR mode in GEN1 mode
begin
rx_bert_lanes[i] = { rx_bert_data_i[(2*i)+241], // Unused
rx_bert_data_i[(2*i)+240], // Unused
rx_bert_data_i[(2*i)+161], // Unused
rx_bert_data_i[(2*i)+160], // Unused
rx_bert_data_i[(2*i)+41],
rx_bert_data_i[(2*i)+40],
rx_bert_data_i[(2*i)+1],
rx_bert_data_i[2*i] };
end // DDR mode in GEN1 mode
end
for(i=20;i<40;i=i+1)
begin
rx_bert_lanes[i] = { rx_bert_data_i[(2*i)+241], // Unused in GEN1
rx_bert_data_i[(2*i)+240], // Unused in GEN1
rx_bert_data_i[(2*i)+161], // Unused in GEN1
rx_bert_data_i[(2*i)+160], // Unused in GEN1
rx_bert_data_i[(2*i)+81], // Unused in GEN1
rx_bert_data_i[(2*i)+80], // Unused in GEN1
rx_bert_data_i[(2*i)+1], // Unused in GEN1
rx_bert_data_i[2*i] }; // Unused in GEN1
end
end // // GEN1 mode
end // block: rx_bert_lanes_logic
// Bit selection for each checker
assign rx_bert_data_chk0[7:0] = (chk0_lane_sel_ff[5:0] < 6'd40) ?
rx_bert_lanes[chk0_lane_sel_ff[5:0] ] :
8'h00;
assign rx_bert_data_chk1[7:0] = (chk1_lane_sel_ff[5:0] < 6'd40) ?
rx_bert_lanes[chk1_lane_sel_ff[5:0]] :
8'h00;
assign rx_bert_data_chk2[7:0] = (chk2_lane_sel_ff[5:0] < 6'd40) ?
rx_bert_lanes[chk2_lane_sel_ff[5:0]] :
8'h00;
assign rx_bert_data_chk3[7:0] = (chk3_lane_sel_ff[5:0] < 6'd40) ?
rx_bert_lanes[chk3_lane_sel_ff[5:0]] :
8'h00;
//Input data to LFSRs is registered to meet synthesis timing
always @(posedge clk or negedge rstn)
begin: rx_bert_data_register
if(!rstn)
begin
rx_bert_data_chk0_ff[7:0] <= 8'h0;
rx_bert_data_chk1_ff[7:0] <= 8'h0;
rx_bert_data_chk2_ff[7:0] <= 8'h0;
rx_bert_data_chk3_ff[7:0] <= 8'h0;
end
else
begin
rx_bert_data_chk0_ff[7:0] <= rx_bert_data_chk0[7:0];
rx_bert_data_chk1_ff[7:0] <= rx_bert_data_chk1[7:0];
rx_bert_data_chk2_ff[7:0] <= rx_bert_data_chk2[7:0];
rx_bert_data_chk3_ff[7:0] <= rx_bert_data_chk3[7:0];
end
end // block: rx_bert_data_register
//------------------------------------------------------------------------------
// Rx BERT bit counter implementation
//------------------------------------------------------------------------------
// Logic to increment BERT bit counter
always @(*)
begin: rbert_bit_cnt_in_logic
case(rx_sft_nb[1:0])
NBIT1: // Receives 1 bit per clock
begin
{co1_nc,rbert_bit_cnt_in[48:0]} = rbert_bit_cnt_ff[48:0] + 49'd1;
end
NBIT2: // Receives 2 bit per clock
begin
{co1_nc,rbert_bit_cnt_in[48:0]} = rbert_bit_cnt_ff[48:0] + 49'd2;
end
NBIT4: // Receives 4 bit per clock
begin
{co1_nc,rbert_bit_cnt_in[48:0]} = rbert_bit_cnt_ff[48:0] + 49'd4;
end
NBIT8: // Receives 8 bit per clock
begin
{co1_nc,rbert_bit_cnt_in[48:0]} = rbert_bit_cnt_ff[48:0] + 49'd8;
end
endcase
end // block: rbert_bit_cnt_in_logic
// Linear feedback shift register
always @(posedge clk or negedge rstn)
begin: rbert_bit_cnt_register
if(!rstn) // Async reset
begin
rbert_bit_cnt_ff[48:0] <= {49{1'b0}};
end
else if(rx_rst_pulse[3:0] != 4'h0)
begin
rbert_bit_cnt_ff[48:0] <= {49{1'b0}};
end
else if(rbert_running_ff[3:0] != 4'h0)
begin
rbert_bit_cnt_ff[48:0] <= rbert_bit_cnt_in[48:0];
end
end // block: rbert_bit_cnt_register
//------------------------------------------------------------------------------
// Checker Instances
//------------------------------------------------------------------------------
// Checker 0
aib_bert_chk #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_bert_chk0(
// Inputs
.clk (clk),
.rstn (rstn),
.rx_rst_pulse (rx_rst_pulse[0]),
.rx_start_pulse (rx_start_pulse[0]),
.seed_in_en (seed_in_en[0]),
.rx_sft_nb (rx_sft_nb[1:0]),
.rx_bert_data_in (rx_bert_data_chk0_ff[7:0]),
.rx_ptrn_sel (chk0_ptrn_sel_ff[2:0]),
// Outputs
.rx_bert_data_ff (rx_bert0_data[127:0]),
.rbert_running_ff (rbert_running_ff[0]),
.rbert_biterr_cnt_ff (biterr_cnt_chk0[15:0])
);
// Checker 1
aib_bert_chk #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_bert_chk1(
// Inputs
.clk (clk),
.rstn (rstn),
.rx_rst_pulse (rx_rst_pulse[1]),
.rx_start_pulse (rx_start_pulse[1]),
.seed_in_en (seed_in_en[1]),
.rx_sft_nb (rx_sft_nb[1:0]),
.rx_bert_data_in (rx_bert_data_chk1_ff[7:0]),
.rx_ptrn_sel (chk1_ptrn_sel_ff[2:0]),
// Outputs
.rx_bert_data_ff (rx_bert1_data[127:0]),
.rbert_running_ff (rbert_running_ff[1]),
.rbert_biterr_cnt_ff (biterr_cnt_chk1[15:0])
);
aib_bert_chk #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_bert_chk2(
// Inputs
.clk (clk),
.rstn (rstn),
.rx_rst_pulse (rx_rst_pulse[2]),
.rx_start_pulse (rx_start_pulse[2]),
.seed_in_en (seed_in_en[2]),
.rx_sft_nb (rx_sft_nb[1:0]),
.rx_bert_data_in (rx_bert_data_chk2_ff[7:0]),
.rx_ptrn_sel (chk2_ptrn_sel_ff[2:0]),
// Outputs
.rx_bert_data_ff (rx_bert2_data[127:0]),
.rbert_running_ff (rbert_running_ff[2]),
.rbert_biterr_cnt_ff (biterr_cnt_chk2[15:0])
);
// Checker 3
aib_bert_chk #(.BERT_BUF_MODE_EN (BERT_BUF_MODE_EN))
aib_bert_chk3(
// Inputs
.clk (clk),
.rstn (rstn),
.rx_rst_pulse (rx_rst_pulse[3]),
.rx_start_pulse (rx_start_pulse[3]),
.seed_in_en (seed_in_en[3]),
.rx_sft_nb (rx_sft_nb[1:0]),
.rx_bert_data_in (rx_bert_data_chk3_ff[7:0]),
.rx_ptrn_sel (chk3_ptrn_sel_ff[2:0]),
// Outputs
.rx_bert_data_ff (rx_bert3_data[127:0]),
.rbert_running_ff (rbert_running_ff[3]),
.rbert_biterr_cnt_ff (biterr_cnt_chk3[15:0])
);
endmodule // aib_rx_bert |
module aib_bert_chk #(
parameter [0:0] BERT_BUF_MODE_EN = 1 // Enables Buffer mode for BERT
)
(
input clk, // Rx BERT clock
input rstn, // Active low asynchronous reset
input rx_rst_pulse, // Resets synchronously RX BERT logic
input rx_start_pulse, // Starts data comparison process
input seed_in_en, // Seed input mode enable
input [1:0] rx_sft_nb, // Selects the number of valid data bits
// per clock
input [7:0] rx_bert_data_in, // Data bits from RX FIFO
input [2:0] rx_ptrn_sel, // Pattern selection
output reg [127:0] rx_bert_data_ff, // Last 128 received bits
output reg rbert_running_ff, // Rx BERT checker is running
output reg [15:0] rbert_biterr_cnt_ff // Rx bit error counter
);
// Defines the number of bits to be considered in RX data:
localparam [1:0] NBIT1 = 2'b00; // 1 bit per clock
localparam [1:0] NBIT2 = 2'b01; // 2 bit per clock
localparam [1:0] NBIT4 = 2'b10; // 4 bit per clock
localparam [1:0] NBIT8 = 2'b11; // 8 bit per clock
// Defines pattern check
localparam [2:0] PRBS7 = 3'b000; // PRBS7 selected
localparam [2:0] PRBS15 = 3'b001; // PRBS15 selected
localparam [2:0] PRBS23 = 3'b010; // PRBS23 selected
localparam [2:0] PRBS31 = 3'b011; // PRBS31 selected
localparam [2:0] PTRN127 = 3'b100; // 127-bit pattern selected
localparam [2:0] PTRN128 = 3'b101; // 127-bit pattern selected
integer i; // Integer used on error increment calculation
// Internal Regs
reg [127:0] lfsr_buf_ff; // Linear feedback shift register (LFSR)
reg [127:0] seed_data_in; // Seed data input for self seeding process
reg [127:0] lfsr_buf_next; // Indicate the next value of LFSR
reg [ 7:0] bit_err; // Indicates all the bit error per clock
reg [ 3:0] rxbert_inc_val; // Indicates the increment value of error counter
reg co2_nc; // Unconnected carryout
// Internal wires
wire [15:0] rbert_biterr_cnt_in; // Error counter input
wire [15:0] rbert_biterr_nxt; // Next Error counter value
wire co1_cnt; // Error counter carryout
wire [7:0] lfsr7_sft1; // LSFR7 calculation shifted by 1 bit on the right
wire [7:0] lfsr7_sft2; // LSFR7 calculation shifted by 2 bit on the right
wire [7:0] lfsr7_sft3; // LSFR7 calculation shifted by 3 bit on the right
wire [7:0] lfsr7_sft4; // LSFR7 calculation shifted by 4 bit on the right
wire [7:0] lfsr7_sft5; // LSFR7 calculation shifted by 5 bit on the right
wire [7:0] lfsr7_sft6; // LSFR7 calculation shifted by 6 bit on the right
wire [7:0] lfsr7_sft7; // LSFR7 calculation shifted by 7 bit on the right
wire [7:0] lfsr7_sft8; // LSFR7 calculation shifted by 8 bit on the right
wire [14:0] lfsr15_sft1; // LSFR15 calculation shifted by 1 bit on the right
wire [14:0] lfsr15_sft2; // LSFR15 calculation shifted by 2 bit on the right
wire [14:0] lfsr15_sft3; // LSFR15 calculation shifted by 3 bit on the right
wire [14:0] lfsr15_sft4; // LSFR15 calculation shifted by 4 bit on the right
wire [14:0] lfsr15_sft5; // LSFR15 calculation shifted by 5 bit on the right
wire [14:0] lfsr15_sft6; // LSFR15 calculation shifted by 6 bit on the right
wire [14:0] lfsr15_sft7; // LSFR15 calculation shifted by 7 bit on the right
wire [14:0] lfsr15_sft8; // LSFR15 calculation shifted by 8 bit on the right
wire [22:0] lfsr23_sft1; // LSFR23 calculation shifted by 1 bit on the right
wire [22:0] lfsr23_sft2; // LSFR23 calculation shifted by 2 bit on the right
wire [22:0] lfsr23_sft3; // LSFR23 calculation shifted by 3 bit on the right
wire [22:0] lfsr23_sft4; // LSFR23 calculation shifted by 4 bit on the right
wire [22:0] lfsr23_sft5; // LSFR23 calculation shifted by 5 bit on the right
wire [22:0] lfsr23_sft6; // LSFR23 calculation shifted by 6 bit on the right
wire [22:0] lfsr23_sft7; // LSFR23 calculation shifted by 7 bit on the right
wire [22:0] lfsr23_sft8; // LSFR23 calculation shifted by 8 bit on the right
wire [30:0] lfsr31_sft1; // LSFR31 calculation shifted by 1 bit on the right
wire [30:0] lfsr31_sft2; // LSFR31 calculation shifted by 2 bit on the right
wire [30:0] lfsr31_sft3; // LSFR31 calculation shifted by 3 bit on the right
wire [30:0] lfsr31_sft4; // LSFR31 calculation shifted by 4 bit on the right
wire [30:0] lfsr31_sft5; // LSFR31 calculation shifted by 5 bit on the right
wire [30:0] lfsr31_sft6; // LSFR31 calculation shifted by 6 bit on the right
wire [30:0] lfsr31_sft7; // LSFR31 calculation shifted by 7 bit on the right
wire [30:0] lfsr31_sft8; // LSFR31 calculation shifted by 8 bit on the right
//------------------------------------------------------------------------------
// RX BERT checker enable: received data is compared with expected data
//------------------------------------------------------------------------------
// This register enables data comparison
always @(posedge clk or negedge rstn)
begin: rbert_running_register
if(!rstn) // Async reset
begin
rbert_running_ff <= 1'h0;
end
else if(rx_rst_pulse)
begin
rbert_running_ff <= 1'h0;
end
else if(rx_start_pulse)
begin
rbert_running_ff <= 1'b1;
end
end // block: rbert_running_register
//------------------------------------------------------------------------------
// Seeding value selection according to CRR configuration
//------------------------------------------------------------------------------
// Seeding logic
always @(*)
begin: seed_data_in_logic
case(rx_sft_nb[1:0])
NBIT1: // Receives 1 bit per clock
begin
seed_data_in[127:0] = {rx_bert_data_in[0],
lfsr_buf_ff[127:1]};
end
NBIT2: // Receives 2 bit per clock
begin
seed_data_in[127:0] = {rx_bert_data_in[1:0],
lfsr_buf_ff[127:2]};
end
NBIT4: // Receives 4 bit per clock
begin
seed_data_in[127:0] = {rx_bert_data_in[3:0],
lfsr_buf_ff[127:4]};
end
NBIT8: // Receives 8 bit per clock
begin
seed_data_in[127:0] = {rx_bert_data_in[7:0],
lfsr_buf_ff[127:8]};
end
endcase
end // block: seed_data_in_logic
//------------------------------------------------------------------------------
// Next value of LFSR7 register when operating in check mode
//------------------------------------------------------------------------------
// Polynomial
// x7 + x6 + 1
// One for each configuration: 1bit/clk, 2bit/clk, 4bit/clk and 8bit/clk
assign lfsr7_sft1[7:0] = {(lfsr_buf_ff[121] ^ lfsr_buf_ff[122]),
lfsr_buf_ff[127:121]};
assign lfsr7_sft2[7:0] = {(lfsr7_sft1[1] ^ lfsr7_sft1[2]),lfsr7_sft1[7:1]};
assign lfsr7_sft3[7:0] = {(lfsr7_sft2[1] ^ lfsr7_sft2[2]),lfsr7_sft2[7:1]};
assign lfsr7_sft4[7:0] = {(lfsr7_sft3[1] ^ lfsr7_sft3[2]),lfsr7_sft3[7:1]};
assign lfsr7_sft5[7:0] = {(lfsr7_sft4[1] ^ lfsr7_sft4[2]),lfsr7_sft4[7:1]};
assign lfsr7_sft6[7:0] = {(lfsr7_sft5[1] ^ lfsr7_sft5[2]),lfsr7_sft5[7:1]};
assign lfsr7_sft7[7:0] = {(lfsr7_sft6[1] ^ lfsr7_sft6[2]),lfsr7_sft6[7:1]};
assign lfsr7_sft8[7:0] = {(lfsr7_sft7[1] ^ lfsr7_sft7[2]),lfsr7_sft7[7:1]};
//------------------------------------------------------------------------------
// Next value of LFSR15 register when operating in check mode
//------------------------------------------------------------------------------
// Polynomial
// x15 + x14 + 1
// One for each configuration: 1bit/clk, 2bit/clk, 4bit/clk and 8bit/clk
assign lfsr15_sft1[14:0] = {(lfsr_buf_ff[113] ^ lfsr_buf_ff[114]),
lfsr_buf_ff[127:114]};
assign lfsr15_sft2[14:0] = {(lfsr15_sft1[0] ^ lfsr15_sft1[1]),lfsr15_sft1[14:1]};
assign lfsr15_sft3[14:0] = {(lfsr15_sft2[0] ^ lfsr15_sft2[1]),lfsr15_sft2[14:1]};
assign lfsr15_sft4[14:0] = {(lfsr15_sft3[0] ^ lfsr15_sft3[1]),lfsr15_sft3[14:1]};
assign lfsr15_sft5[14:0] = {(lfsr15_sft4[0] ^ lfsr15_sft4[1]),lfsr15_sft4[14:1]};
assign lfsr15_sft6[14:0] = {(lfsr15_sft5[0] ^ lfsr15_sft5[1]),lfsr15_sft5[14:1]};
assign lfsr15_sft7[14:0] = {(lfsr15_sft6[0] ^ lfsr15_sft6[1]),lfsr15_sft6[14:1]};
assign lfsr15_sft8[14:0] = {(lfsr15_sft7[0] ^ lfsr15_sft7[1]),lfsr15_sft7[14:1]};
//------------------------------------------------------------------------------
// Next value of LFSR23 register when operating in check mode
//------------------------------------------------------------------------------
// Polynomial
// x23 + x18 + 1
// One for each configuration: 1bit/clk, 2bit/clk, 4bit/clk and 8bit/clk
assign lfsr23_sft1[22:0] = {(lfsr_buf_ff[105] ^ lfsr_buf_ff[110]),
lfsr_buf_ff[127:106]};
assign lfsr23_sft2[22:0] = {(lfsr23_sft1[0] ^ lfsr23_sft1[5]),lfsr23_sft1[22:1]};
assign lfsr23_sft3[22:0] = {(lfsr23_sft2[0] ^ lfsr23_sft2[5]),lfsr23_sft2[22:1]};
assign lfsr23_sft4[22:0] = {(lfsr23_sft3[0] ^ lfsr23_sft3[5]),lfsr23_sft3[22:1]};
assign lfsr23_sft5[22:0] = {(lfsr23_sft4[0] ^ lfsr23_sft4[5]),lfsr23_sft4[22:1]};
assign lfsr23_sft6[22:0] = {(lfsr23_sft5[0] ^ lfsr23_sft5[5]),lfsr23_sft5[22:1]};
assign lfsr23_sft7[22:0] = {(lfsr23_sft6[0] ^ lfsr23_sft6[5]),lfsr23_sft6[22:1]};
assign lfsr23_sft8[22:0] = {(lfsr23_sft7[0] ^ lfsr23_sft7[5]),lfsr23_sft7[22:1]};
//------------------------------------------------------------------------------
// Next value of LFSR31 register when operating in check mode
//------------------------------------------------------------------------------
// Polynomial
// x31 + x28 + 1
// One for each configuration: 1bit/clk, 2bit/clk, 4bit/clk and 8bit/clk
assign lfsr31_sft1[30:0] = {(lfsr_buf_ff[97] ^ lfsr_buf_ff[100]),
lfsr_buf_ff[127:98]};
assign lfsr31_sft2[30:0] = {(lfsr31_sft1[0] ^ lfsr31_sft1[3]),lfsr31_sft1[30:1]};
assign lfsr31_sft3[30:0] = {(lfsr31_sft2[0] ^ lfsr31_sft2[3]),lfsr31_sft2[30:1]};
assign lfsr31_sft4[30:0] = {(lfsr31_sft3[0] ^ lfsr31_sft3[3]),lfsr31_sft3[30:1]};
assign lfsr31_sft5[30:0] = {(lfsr31_sft4[0] ^ lfsr31_sft4[3]),lfsr31_sft4[30:1]};
assign lfsr31_sft6[30:0] = {(lfsr31_sft5[0] ^ lfsr31_sft5[3]),lfsr31_sft5[30:1]};
assign lfsr31_sft7[30:0] = {(lfsr31_sft6[0] ^ lfsr31_sft6[3]),lfsr31_sft6[30:1]};
assign lfsr31_sft8[30:0] = {(lfsr31_sft7[0] ^ lfsr31_sft7[3]),lfsr31_sft7[30:1]};
//------------------------------------------------------------------------------
// Logic to calculate next values of bit sequence
//------------------------------------------------------------------------------
// LFSR next value value logic
always @(*)
begin: lfsr_buf_next_logic
lfsr_buf_next[127:0] = lfsr_buf_ff[127:0];
case(rx_ptrn_sel[2:0])
PRBS7: // PRBS7 selected
begin
case(rx_sft_nb[1:0])
NBIT1: // Receives 1 bit per clock
begin
lfsr_buf_next[127:120] = lfsr7_sft1[7:0];
end
NBIT2: // Receives 2 bit per clock
begin
lfsr_buf_next[127:120] = lfsr7_sft2[7:0];
end
NBIT4: // Receives 4 bit per clock
begin
lfsr_buf_next[127:120] = lfsr7_sft4[7:0];
end
NBIT8: // Receives 8 bit per clock
begin
lfsr_buf_next[127:120] = lfsr7_sft8[7:0];
end
endcase
end
PRBS15: // PRBS15 selected
begin
case(rx_sft_nb[1:0])
NBIT1: // Receives 1 bit per clock
begin
lfsr_buf_next[127:113] = lfsr15_sft1[14:0];
end
NBIT2: // Receives 2 bit per clock
begin
lfsr_buf_next[127:113] = lfsr15_sft2[14:0];
end
NBIT4: // Receives 4 bit per clock
begin
lfsr_buf_next[127:113] = lfsr15_sft4[14:0];
end
NBIT8: // Receives 8 bit per clock
begin
lfsr_buf_next[127:113] = lfsr15_sft8[14:0];
end
endcase
end
PRBS23: // PRBS23 selected
begin
case(rx_sft_nb[1:0])
NBIT1: // Receives 1 bit per clock
begin
lfsr_buf_next[127:105] = lfsr23_sft1[22:0];
end
NBIT2: // Receives 2 bit per clock
begin
lfsr_buf_next[127:105] = lfsr23_sft2[22:0];
end
NBIT4: // Receives 4 bit per clock
begin
lfsr_buf_next[127:105] = lfsr23_sft4[22:0];
end
NBIT8: // Receives 8 bit per clock
begin
lfsr_buf_next[127:105] = lfsr23_sft8[22:0];
end
endcase
end
PRBS31: // PRBS31 selected
begin
case(rx_sft_nb[1:0])
NBIT1: // Receives 1 bit per clock
begin
lfsr_buf_next[127:97] = lfsr31_sft1[30:0];
end
NBIT2: // Receives 2 bit per clock
begin
lfsr_buf_next[127:97] = lfsr31_sft2[30:0];
end
NBIT4: // Receives 4 bit per clock
begin
lfsr_buf_next[127:97] = lfsr31_sft4[30:0];
end
NBIT8: // Receives 8 bit per clock
begin
lfsr_buf_next[127:97] = lfsr31_sft8[30:0];
end
endcase
end
PTRN127: // 127-bit pattern selected
begin
case(rx_sft_nb[1:0])
NBIT1: // Receives 1 bit per clock
begin
lfsr_buf_next[127:1] = { lfsr_buf_ff[1],
lfsr_buf_ff[127:2] };
end
NBIT2: // Receives 2 bit per clock
begin
lfsr_buf_next[127:1] = { lfsr_buf_ff[2:1],
lfsr_buf_ff[127:3] };
end
NBIT4: // Receives 4 bit per clock
begin
lfsr_buf_next[127:1] = { lfsr_buf_ff[4:1],
lfsr_buf_ff[127:5] };
end
NBIT8: // Receives 8 bit per clock
begin
lfsr_buf_next[127:1] = { lfsr_buf_ff[8:1],
lfsr_buf_ff[127:9] };
end
endcase
end
PTRN128: // 128-bit pattern selected
begin
case(rx_sft_nb[1:0])
NBIT1: // Receives 1 bit per clock
begin
lfsr_buf_next[127:0] = { lfsr_buf_ff[0],
lfsr_buf_ff[127:1] };
end
NBIT2: // Receives 2 bit per clock
begin
lfsr_buf_next[127:0] = { lfsr_buf_ff[1:0],
lfsr_buf_ff[127:2] };
end
NBIT4: // Receives 4 bit per clock
begin
lfsr_buf_next[127:0] = { lfsr_buf_ff[3:0],
lfsr_buf_ff[127:4] };
end
NBIT8: // Receives 8 bit per clock
begin
lfsr_buf_next[127:0] = { lfsr_buf_ff[7:0],
lfsr_buf_ff[127:8] };
end
endcase
end
default: //Reserved selections keep the register value
begin
lfsr_buf_next[127:0] = lfsr_buf_ff[127:0];
end
endcase
end // block: lfsr_buf_next_logic
//------------------------------------------------------------------------------
// Linear feedback shift register
//------------------------------------------------------------------------------
// Linear feedback shift register
always @(posedge clk or negedge rstn)
begin: lfsr_buf_register
if(!rstn) // Async reset
begin
lfsr_buf_ff[127:0] <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;
end
else if(rx_rst_pulse)
begin
lfsr_buf_ff[127:0] <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;
end
else if(rbert_running_ff | rx_start_pulse)
begin
lfsr_buf_ff[127:0] <= lfsr_buf_next[127:0] &
{31'h7fff_ffff,{97{BERT_BUF_MODE_EN}}};
end
else if(seed_in_en)
begin
lfsr_buf_ff[127:0] <= seed_data_in[127:0] &
{31'h7fff_ffff,{97{BERT_BUF_MODE_EN}}};
end
end // block: lfsr_buf_register
//------------------------------------------------------------------------------
// RX data buffer - stores the last 128 receive bits
//------------------------------------------------------------------------------
// Linear feedback shift register
always @(posedge clk or negedge rstn)
begin: rx_bert_data_register
if(!rstn) // Async reset
begin
rx_bert_data_ff[127:0] <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;
end
else if(rx_rst_pulse)
begin
rx_bert_data_ff[127:0] <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;
end
else if(rbert_running_ff | rx_start_pulse)
begin
rx_bert_data_ff[127:0] <= seed_data_in[127:0];
end
end // block: rx_bert_data_register
//------------------------------------------------------------------------------
// Bit error detection
//------------------------------------------------------------------------------
// Detects bit error according to operation mode
always @(*)
begin: bit_err_logic
bit_err[7:0] = 8'b00;
case(rx_sft_nb[1:0])
NBIT1: // Receives 1 bit per clock
begin
if(rbert_running_ff)
bit_err[0] = lfsr_buf_ff[127] ^ rx_bert_data_ff[127];
end
NBIT2: // Receives 2 bit per clock
begin
if(rbert_running_ff)
bit_err[1:0] = lfsr_buf_ff[127:126] ^ rx_bert_data_ff[127:126];
end
NBIT4: // Receives 4 bit per clock
begin
if(rbert_running_ff)
bit_err[3:0] = lfsr_buf_ff[127:124] ^ rx_bert_data_ff[127:124];
end
NBIT8: // Receives 8 bit per clock
begin
if(rbert_running_ff)
bit_err[7:0] = lfsr_buf_ff[127:120] ^ rx_bert_data_ff[127:120];
end
endcase
end // block: bit_err_logic
//------------------------------------------------------------------------------
// Rx BERT Error counter implementation
//------------------------------------------------------------------------------
// Error counter increment logic
// Calculates the error counter increment based on the total number of bit
// errors in 8-bit word
always @(*)
begin: rxbert_inc_val_logic
rxbert_inc_val[3:0] = 4'h0;
for(i=0;i<8;i=i+1)
begin
rxbert_inc_val[3:0] = rxbert_inc_val[3:0] + {3'h0,bit_err[i]};
end
end // block: rxbert_inc_val_logic
assign {co1_cnt,rbert_biterr_nxt[15:0]} = rbert_biterr_cnt_ff[15:0] +
{12'h0,rxbert_inc_val[3:0]};
// Check saturation of error counter
assign rbert_biterr_cnt_in[15:0] = co1_cnt ? 16'hffff : rbert_biterr_nxt[15:0];
// Linear feedback shift register
always @(posedge clk or negedge rstn)
begin: rbert_biterr_cnt_register
if(!rstn) // Async reset
begin
rbert_biterr_cnt_ff[15:0] <= {16{1'b0}};
end
else if(rx_rst_pulse)
begin
rbert_biterr_cnt_ff[15:0] <= {16{1'b0}};
end
else if(rbert_running_ff)
begin
rbert_biterr_cnt_ff[15:0] <= rbert_biterr_cnt_in[15:0];
end
end // block: rbert_biterr_cnt_register
endmodule // aib_bert_chk |
module aib_adapt_rx_fifo
#(
parameter ODWIDTH = 'd320, // FIFO output data width
parameter IDWIDTH = 'd80, // FIFO Input data width
parameter DEPTH = 'd6, // FIFO Depth
parameter DEPTH4 = DEPTH * 4, // DEPTH MUTIPLIED BY 4
parameter AWIDTH = $clog2(DEPTH4) // FIFO address width
)
(
// Inputs
input wr_rst_n, // Write Domain Active low Reset
input wr_clk, // Write Domain Clock
input [IDWIDTH-1:0] fifo_din, // Write Data In
input rd_rst_n, // Read Domain Active low Reset
input rd_clk, // Read Domain Clock
input scan_en, // Scan enable
input m_gen2_mode, // Generation 2 mode
input [1:0] r_fifo_mode, // FIFO Mode: 4:1 2:1 1:1 Reg mode
input [3:0] r_phcomp_rd_delay, // Programmable phase conpensation
input [4:0] rx_align_threshold, // Rx FIFO alignment threshold
input r_wa_en, // Word-align enable
input [4:0] r_mkbit, // Configurable marker bit
input rx_wa_mode_sync, // Word alignment mode bit
// Outputs
output [ODWIDTH-1:0] fifo_dout, // Read Data Out
output align_done // Word mark alignment done
);
//------------------------------------------------------------------------------
// Local Parameters
//------------------------------------------------------------------------------
localparam FIFO_1X = 2'b00; //Full rate
localparam FIFO_2X = 2'b01; //Half rate
localparam FIFO_4X = 2'b10; //Quarter Rate
localparam REG_MOD = 2'b11; //REG mode
//------------------------------------------------------------------------------
// Define wires and regs
//------------------------------------------------------------------------------
wire phcomp_mode; // Indicates FIFO mode
wire phcomp_wren_sync2; // Wite enable synchronized at read clock domain
wire rd_en_int; // FIFO read enable
wire wam_fifo_wren; // Indicates FIFO can be written
wire phcomp_wren_sync; // Write enable in read clock domain with
// configurable phase
wire phcomp_rden; // Read enable for FIFO mode
wire wam_alig_sync; // Word alignment indication at read clock domain
wire [AWIDTH-1 :0] rxf_wr_pnt_in; // RX FIFO write pointer input
wire [ODWIDTH-1:0] rxf_wr_data; // RX FIFO write data bus
wire [DEPTH4-1 :0] fifo_rd_en; // RX FIFO read enable
wire [DEPTH-1:0] rff_clk_39_0; // Clocks for word 39-0
wire [DEPTH-1:0] rff_clk_79_40; // Clocks for word 79-40
wire [DEPTH-1:0] rff_clk_119_80;
wire [DEPTH-1:0] rff_clk_159_120;
wire [DEPTH-1:0] rff_clk_199_160;
wire [DEPTH-1:0] rff_clk_239_200;
wire [DEPTH-1:0] rff_clk_279_240;
wire [DEPTH-1:0] rff_clk_319_280;
wire [DEPTH-1:0][ODWIDTH-1:0] fifo_data_ff; // Data of FIFO array
wire wr_en_int;
wire co_nc;
reg phcomp_wren_sync3; // Additional delay in the read enable path
reg phcomp_wren_sync4; // Additional delay in the read enable path
reg phcomp_wren_sync5; // Additional delay in the read enable path
reg phcomp_wren_sync6; // Additional delay in the read enable path
reg phcomp_wren_sync7; // Additional delay in the read enable path
reg phcomp_wren_sync8; // Additional delay in the read enable path
reg phcomp_wren_sync9; // Additional delay in the read enable path
reg phcomp_wren_sync10; // Additional delay in the read enable path
reg phcomp_wren_sync11; // Additional delay in the read enable path
reg rd_en_reg; // Read enable registered to be used as align done
// output
reg [AWIDTH-1 :0] rxf_wr_pnt_ff; // RX FIFO write pointer
reg [IDWIDTH-1:0] fifo_din_ff; // Data input register
reg [DEPTH4-1 :0] rxf_rd_pnt_ff; // RX FIFO read pointer
reg [DEPTH4-1 :0] rxf_rd_pnt_in; // RX FIFO read pointer input
// FIFO mode decode
assign phcomp_mode = (r_fifo_mode != REG_MOD); //2'b11 is reg_mod
// Indicates the alignment is done
assign align_done = rd_en_reg;
//********************************************************************
// Read Write logic
//********************************************************************
// FIFO write enable
assign wr_en_int = phcomp_mode & wam_fifo_wren;
// FIFO read enable
assign rd_en_int = phcomp_mode & phcomp_rden;
// Read enable registered to be used as align done output
always @(negedge rd_rst_n or posedge rd_clk)
begin: read_en_register
if (rd_rst_n == 1'b0)
begin
rd_en_reg <= 1'b0;
end // reset
else
begin
rd_en_reg <= rd_en_int & wam_alig_sync;
end // sampled input
end // block: read_en_register
aib_rx_fifo_wam #( .IDWIDTH (IDWIDTH) )
aib_rx_fifo_wam
(
// Inputs
.wr_rst_n (wr_rst_n), // Write Domain Active low Reset
.wr_clk (wr_clk), // Write Domain Clock
.wr_data (fifo_din_ff[IDWIDTH-1:0]), // Write Data In
.rd_rst_n (rd_rst_n), // Read Domain Active low Reset
.rd_clk (rd_clk), // Read Domain Clock
.r_fifo_mode (r_fifo_mode[1:0]), // FIFO double write mode
.rx_wa_mode_sync (rx_wa_mode_sync), // Rx word alignment mode bit
.r_mkbit (r_mkbit[4:0]), // Configurable marker bit
.rx_align_threshold (rx_align_threshold[4:0]), // FIFO word alignment threshold
.r_wa_en (r_wa_en), // Rx word alignment enable
// Outputs
.wam_alig_sync (wam_alig_sync), // Word aligned indication synchronized
.wam_fifo_wren (wam_fifo_wren) // Write in FIFO is enabled
);
// PHCOM_wren synchronization to read clock domain
aib_bit_sync bitsync2_phcomp_wren
(
.clk (rd_clk), // Clock of destination domain
.rst_n (rd_rst_n), // Reset of destination domain
.data_in (wam_fifo_wren), // Input to be synchronized
.data_out (phcomp_wren_sync2) // Synchronized output
);
// Phase compensation for read enable
always @(negedge rd_rst_n or posedge rd_clk)
begin: phcomp_rden_register
if (rd_rst_n == 1'b0)
begin
phcomp_wren_sync3 <= 1'b0;
phcomp_wren_sync4 <= 1'b0;
phcomp_wren_sync5 <= 1'b0;
phcomp_wren_sync6 <= 1'b0;
phcomp_wren_sync7 <= 1'b0;
phcomp_wren_sync8 <= 1'b0;
phcomp_wren_sync9 <= 1'b0;
phcomp_wren_sync10 <= 1'b0;
phcomp_wren_sync11 <= 1'b0;
end
else
begin
phcomp_wren_sync3 <= phcomp_wren_sync2;
phcomp_wren_sync4 <= phcomp_wren_sync3;
phcomp_wren_sync5 <= phcomp_wren_sync4;
phcomp_wren_sync6 <= phcomp_wren_sync5;
phcomp_wren_sync7 <= phcomp_wren_sync6;
phcomp_wren_sync8 <= phcomp_wren_sync7;
phcomp_wren_sync9 <= phcomp_wren_sync8;
phcomp_wren_sync10 <= phcomp_wren_sync9;
phcomp_wren_sync11 <= phcomp_wren_sync10;
end
end // block: phcomp_rden_register
// Read Enable phase control logic
assign phcomp_wren_sync =
(r_phcomp_rd_delay[3:0] == 4'b1011) ? phcomp_wren_sync11 :
(r_phcomp_rd_delay[3:0] == 4'b1010) ? phcomp_wren_sync10 :
(r_phcomp_rd_delay[3:0] == 4'b1001) ? phcomp_wren_sync9 :
(r_phcomp_rd_delay[3:0] == 4'b1000) ? phcomp_wren_sync8 :
(r_phcomp_rd_delay[3:0] == 4'b0111) ? phcomp_wren_sync7 :
(r_phcomp_rd_delay[3:0] == 4'b0110) ? phcomp_wren_sync6 :
(r_phcomp_rd_delay[3:0] == 4'b0101) ? phcomp_wren_sync5 :
(r_phcomp_rd_delay[3:0] == 4'b0100) ? phcomp_wren_sync4 :
(r_phcomp_rd_delay[3:0] == 4'b0011) ? phcomp_wren_sync3 :
phcomp_wren_sync2;
// Read enable is generated using phase compensation configuration
assign phcomp_rden = phcomp_wren_sync;
assign {co_nc,rxf_wr_pnt_in[AWIDTH-1:0]} =
(rxf_wr_pnt_ff[AWIDTH-1:0] == (DEPTH4-1)) ?
{AWIDTH{1'b0}} :
rxf_wr_pnt_ff[AWIDTH-1:0] + {{(AWIDTH-1){1'b0}}, 1'b1};
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(!wr_rst_n)
rxf_wr_pnt_ff[AWIDTH-1:0] <= {AWIDTH{1'b0}};
else if(wr_en_int)
rxf_wr_pnt_ff[AWIDTH-1:0] <= rxf_wr_pnt_in[AWIDTH-1:0];
end
aib_rxfifo_clk_gating #( .FF_DEPTH (DEPTH) )
aib_rxfifo_clk_gating
(
// Outputs
.rff_clk_39_0 (rff_clk_39_0[DEPTH-1:0]), // Clocks for word 39-0
.rff_clk_79_40 (rff_clk_79_40[DEPTH-1:0]), // Clocks for word 79-40
.rff_clk_119_80 (rff_clk_119_80),
.rff_clk_159_120 (rff_clk_159_120),
.rff_clk_199_160 (rff_clk_199_160),
.rff_clk_239_200 (rff_clk_239_200),
.rff_clk_279_240 (rff_clk_279_240),
.rff_clk_319_280 (rff_clk_319_280),
// Inputs
.rxf_wr_clk (wr_clk), // RX FIFO write clock
.rxf_wr_en (wr_en_int), // RX FIFO write enable
.rxf_pnt_ff (rxf_wr_pnt_ff[AWIDTH-1:0]), // Indicates RX FIFO element
.m_gen2_mode (m_gen2_mode), // Indicates RX FIFO operates in GEN2 mode
.scan_en (scan_en) // Scan enable
);
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(!wr_rst_n)
fifo_din_ff[IDWIDTH-1:0] <= {IDWIDTH{1'b0}};
else
fifo_din_ff[IDWIDTH-1:0] <= fifo_din[IDWIDTH-1:0];
end
assign rxf_wr_data[ODWIDTH-1:0] = { fifo_din_ff[IDWIDTH-1:0],
fifo_din_ff[IDWIDTH-1:0],
fifo_din_ff[IDWIDTH-1:0],
fifo_din_ff[IDWIDTH-1:0] };
aib_adapt_fifo_mem #(
.DWIDTH (ODWIDTH), // FIFO Input data width
.DEPTH (DEPTH) // FIFO Depth
)
aib_adapt_rxfifo_mem
(
// Inputs
.ff_clk_39_0 (rff_clk_39_0[DEPTH-1:0]), // clocks for bits 39-0 of FIFO
.ff_clk_79_40 (rff_clk_79_40[DEPTH-1:0]), // clocks for bits 79-40 of FIFO
.ff_clk_119_80 (rff_clk_119_80[DEPTH-1:0]), // clocks for bits 119-80 of FIFO
.ff_clk_159_120 (rff_clk_159_120[DEPTH-1:0]), // clocks for bits 159-120 of FIFO
.ff_clk_199_160 (rff_clk_199_160[DEPTH-1:0]),
.ff_clk_239_200 (rff_clk_239_200[DEPTH-1:0]),
.ff_clk_279_240 (rff_clk_279_240[DEPTH-1:0]),
.ff_clk_319_280 (rff_clk_319_280[DEPTH-1:0]),
.ff_rst_n (wr_rst_n), // FIFO array reset
.wr_data (rxf_wr_data[ODWIDTH-1:0]), // FIFO write data bus
// Outputs
.fifo_data_ff (fifo_data_ff) // FIFO data
);
always @(*)
begin
if(rd_en_int)
begin
case(r_fifo_mode[1:0])
FIFO_4X: rxf_rd_pnt_in = { rxf_rd_pnt_ff[DEPTH4-5:0],
rxf_rd_pnt_ff[DEPTH4-1:DEPTH4-4] };
FIFO_2X: rxf_rd_pnt_in = { rxf_rd_pnt_ff[DEPTH4-3:0],
rxf_rd_pnt_ff[DEPTH4-1:DEPTH4-2] };
default: rxf_rd_pnt_in = { rxf_rd_pnt_ff[DEPTH4-2:0],
rxf_rd_pnt_ff[DEPTH4-1] };
endcase
end
else
begin
case(r_fifo_mode[1:0])
FIFO_4X: rxf_rd_pnt_in = {{(DEPTH4-4){1'b0}},4'b1111};
FIFO_2X: rxf_rd_pnt_in = {{(DEPTH4-2){1'b0}},2'b11};
default: rxf_rd_pnt_in = {{(DEPTH4-1){1'b0}},1'b1};
endcase
end
end
// RX FIFO Read pointer register
always @(posedge rd_clk or negedge rd_rst_n)
begin: rxf_rd_pnt_register
if (!rd_rst_n)
rxf_rd_pnt_ff[DEPTH4-1:0] <= {{(DEPTH4-1){1'b0}},1'b1};
else
rxf_rd_pnt_ff[DEPTH4-1:0] <= rxf_rd_pnt_in[DEPTH4-1:0];
end // block: rxf_rd_pnt_register
// Enables read in RX FIFO
assign fifo_rd_en[DEPTH4-1:0] = rxf_rd_pnt_ff[DEPTH4-1:0] &
{DEPTH4{rd_en_int}};
aib_rxfifo_rd_dpath #(
.DWIDTH (ODWIDTH),
.DEPTH (DEPTH)
)
aib_rxfifo_rd_dpath
(
// Output
.rdata_sync_ff (fifo_dout[ODWIDTH-1:0]), // Read data synchronized
// Inputs
.fifo_rd_en (fifo_rd_en[DEPTH4-1:0]), // FIFO element selector
.r_fifo_mode (r_fifo_mode[1:0]), // FIFO mode
.m_gen2_mode (m_gen2_mode), // GEN2 mode enable
.fifo_data_async (fifo_data_ff), // FIFO data
.rd_clk (rd_clk), // FIFO read clock
.rd_rst_n (rd_rst_n) // FIFO read asynchronous reset
);
endmodule // aib_adapt_rx_fifo |
module aib_adapter_rxchnl(
// Outputs
output wire [319:0] rx_adapt_dout, // FIFO mode data output
output wire [79:0] data_out, // Register mode data output
output wire align_done, // Word Mark alignment done
// Inputs
input atpg_mode, // Scan enabled
input m_gen2_mode, // Generation 2.0 mode
input rxrd_fifo_rstn, // RX FIFO read reset
input rxwr_rstn, // RX write reset
input rxwr_fifo_rstn, // RX FIFO write reset
input [79:0] din, // Data input from io buffer
input rxfifo_rd_clk, // Read clock
input rxfifo_wrclk, // FIFO write clock
input [1:0] r_rx_fifo_mode, // FIFO mode register
input [4:0] rx_align_threshold, // RX FIFO WAM threshold
input [3:0] r_rx_phcomp_rd_delay, // Phase compensation register
input r_rx_wa_en, // RX word aligment enable
input rx_wa_mode_sync, // Rx word alignment mode bit
input r_rxswap_en, // RX swapping enable
input [4:0] r_rx_mkbit, // Selection of Rx word mark bit
input r_rx_dbi_en // Enable for Rx data bus inversion
);
// Wires
wire [79:0] dbi_dout; // Output of data bus inversion
wire [79:0] rx_fifo_data_out_sel; // Swapped data or input data to FIFO
wire [319:0] rx_fifo_data_out; // Output from FIFO registered
// FIFO data output
assign rx_adapt_dout = {rx_fifo_data_out[319:80], rx_fifo_data_out_sel};
// Data output after DBI logic
assign data_out = dbi_dout;
// Data after swapping logic.
// Swapping is used only for FIFO 2x with generation 1
assign rx_fifo_data_out_sel[79:0] =
((r_rx_fifo_mode==2'b01) & r_rxswap_en & ~m_gen2_mode) ?
{rx_fifo_data_out[79],
rx_fifo_data_out[38:0],
rx_fifo_data_out[39],
rx_fifo_data_out[78:40]} :
rx_fifo_data_out[79:0];
// DBI logic
aib_rx_dbi rx_dbi (
// Inputs
.rst_n(rxwr_rstn), // Async reset
.clk(rxfifo_wrclk), // FIFO write clock
.data_in(din), // Data input
.dbi_en(r_rx_dbi_en), // Data bus inversion
// Outputs
.data_out(dbi_dout) // Data bus inversion output
);
// RX FIFO data path logic
aib_adapt_rx_fifo aib_adapt_rx_fifo(
// Outputs
.fifo_dout (rx_fifo_data_out), // FIFO data output registered
.align_done (align_done), // Word mark alignment done
// Inputs
.wr_rst_n (rxwr_fifo_rstn), // Rx FIFO write reset
.wr_clk (rxfifo_wrclk), // Rx FIFO write clock
.fifo_din (dbi_dout), // FIFO input
.rd_rst_n (rxrd_fifo_rstn), // Rx FIFO read reset
.rd_clk (rxfifo_rd_clk), // FIFO Read clock
.scan_en (atpg_mode), // Scan enable
.m_gen2_mode (m_gen2_mode), // Generation mode
.r_fifo_mode (r_rx_fifo_mode[1:0]), // RX FIFO mode configuration
.rx_align_threshold (rx_align_threshold[4:0]), // RX FIFO WAM threshold
.r_phcomp_rd_delay (r_rx_phcomp_rd_delay[3:0]), // RX FIFO phase compensation
.r_mkbit (r_rx_mkbit[4:0]), // RX Mark bits
.rx_wa_mode_sync (rx_wa_mode_sync), // Word alignment mode bit
.r_wa_en (r_rx_wa_en) // Word alignment enable
);
endmodule // aib_adapter_rxchnl |
module aib_rx_fifo_wam #(
parameter IDWIDTH = 'd80 // FIFO Input data width
)
(
// Inputs
input wr_rst_n, // Write Domain Active low Reset
input wr_clk, // Write Domain Clock
input [IDWIDTH-1:0] wr_data, // Write Data In
input rd_rst_n, // Read Domain Active low Reset
input rd_clk, // Read Domain Clock
input [1:0] r_fifo_mode, // FIFO double write mode
input rx_wa_mode_sync, // Rx word alignment mode bit
input [4:0] r_mkbit, // Configurable marker bit (79:76 plus 39)
input [4:0] rx_align_threshold, // Rx FIFO word alignment threshold
input r_wa_en, // Rx word alignment enable
// Outputs
output wam_alig_sync, // Word aligned indication synchronized
output wam_fifo_wren // Write in FIFO is enabled
);
//------------------------------------------------------------------------------
// Local Parameters
//------------------------------------------------------------------------------
localparam FIFO_2X = 2'b01; //Half rate
localparam FIFO_4X = 2'b10; //Quarter Rate
// States of Word alignment mark extraction FSM
localparam [1:0] WAM_RESET = 2'd0; // Reset condition
localparam [1:0] FIND_WAM = 2'd1; // Find alignment condition
localparam [1:0] ALIGNED = 2'd2; // Word mark is aligned
localparam [1:0] ALING_LOST = 2'd3; // Word alignment lost
//------------------------------------------------------------------------------
// Wires and regs
//------------------------------------------------------------------------------
reg wm_bit; // Selects the bit mark according to
// configuration
reg [4:0] wam_cnt_ff; // Counts number of valid mark bits
reg [1:0] wam_extrac_fsm_ff; // Machine to detect the word mark alignment
reg [1:0] wam_extrac_fsm_ns; // Next state of WAM extraction machine
reg wam_cnt_rst; // Resets WAM counter
reg wam_cnt_inc; // Increments WAM counter
reg wam_aligned; // Indicates alignment condiction was detected
reg bit_mark_aligned; // Indicates the current mark is aligned
reg bit_mark_misalign; // Indicates the current mark is not aligned
reg wam_bit_cnt_clr; // Resets WAM bit counter
reg [1:0] wam_bit_cnt_ff; // Index of bit sequence for word alignment
reg wam_aligned_ff; // Word aligned information registered
// Rx mark bit selection logic
always @(*)
begin:_word_mark_bit_logic
case (r_mkbit[4:0])
5'b10000: wm_bit = (wr_data[79] & r_wa_en);
5'b01000: wm_bit = (wr_data[78] & r_wa_en);
5'b00100: wm_bit = (wr_data[77] & r_wa_en);
5'b00010: wm_bit = (wr_data[76] & r_wa_en);
5'b00001: wm_bit = (wr_data[39] & r_wa_en);
default: wm_bit = 1'b0;
endcase
end // block: _word_mark_bit_logic
// Logic to clear WAM bit counter
always @(*)
begin: wam_bit_cnt_clr_logic
case(r_fifo_mode[1:0]) // operation mode
FIFO_4X: wam_bit_cnt_clr = (wam_bit_cnt_ff[1:0] == 3'd3) | wm_bit;
FIFO_2X: wam_bit_cnt_clr = (wam_bit_cnt_ff[1:0] == 3'd1) | wm_bit;
default: wam_bit_cnt_clr = 1'b1; // FIFO 1x or REG mode
endcase // operation mode
end // block: wam_bit_cnt_clr_logic
// This counter detects if bit mark is aligned
always @(posedge wr_clk or negedge wr_rst_n)
begin: wam_bit_cnt_register
if(!wr_rst_n)
wam_bit_cnt_ff[1:0] <= 2'h0;
else if(wam_bit_cnt_clr) // Clear condition
wam_bit_cnt_ff[1:0] <= 2'h0;
else if(!wm_bit) // Waiting for mark bit
wam_bit_cnt_ff[1:0] <= wam_bit_cnt_ff[1:0] + 2'd1;
end // block: wam_bit_cnt_register
// Word alignment mark count
always @(posedge wr_clk or negedge wr_rst_n)
begin: wam_cnt_register
if(!wr_rst_n)
wam_cnt_ff[4:0] <= 5'h0;
else if(wam_cnt_rst) // Word mark counter reset
wam_cnt_ff[4:0] <= 5'h0;
else if(wam_cnt_inc) // Word mark counter increment
wam_cnt_ff[4:0] <= wam_cnt_ff[4:0] + 5'd1;
end // block: wam_cnt_register
// Logic to detect the bit mark is aligned
always @(*)
begin: bit_mark_aligned_logic
case(r_fifo_mode[1:0]) // mode
FIFO_4X: bit_mark_aligned = (wam_bit_cnt_ff[1:0] == 3'd3) & wm_bit;
FIFO_2X: bit_mark_aligned = (wam_bit_cnt_ff[1:0] == 3'd1) & wm_bit;
default: bit_mark_aligned = 1'b0; // FIFO 1x or REG mode
endcase
end // block: bit_mark_aligned_logic
// Logic to detect the bit mark is not aligned
always @(*)
begin: bit_mark_misalign_logic
case(r_fifo_mode[1:0]) // mode
FIFO_4X: bit_mark_misalign = ((wam_bit_cnt_ff[1:0] == 3'd3) & ~wm_bit) |
((wam_bit_cnt_ff[1:0] != 3'd3) & wm_bit);
FIFO_2X: bit_mark_misalign = ((wam_bit_cnt_ff[1:0] == 3'd1) & ~wm_bit) |
((wam_bit_cnt_ff[1:0] == 3'd0) & wm_bit);
default: bit_mark_misalign = 1'b0; // FIFO 1x or REG mode
endcase
end // block: bit_mark_misalign_logic
// Word alignment mark extraction FSM - next state/output logic
always @(*)
begin: wam_ext_fsm_nxt_out_logic
case(wam_extrac_fsm_ff[1:0])
WAM_RESET: // Reset condition
begin
wam_aligned = 1'b0;
wam_cnt_rst = 1'b1;
wam_cnt_inc = 1'b0;
wam_extrac_fsm_ns[1:0] = FIND_WAM;
end // WAM_RESET
FIND_WAM: // Find alignment condition
begin
case(r_fifo_mode[1:0]) // mode
FIFO_4X,FIFO_2X: // FIFO 4x or FIFO 2x
begin
if( ( (wam_cnt_ff == rx_align_threshold) &&
bit_mark_aligned ) || // Threshold met
(!r_wa_en) ) // Alignment disabled
begin
wam_cnt_inc = ~r_wa_en & bit_mark_misalign;
wam_cnt_rst = 1'b0;
wam_aligned = 1'b0;
if(r_wa_en)
begin
wam_extrac_fsm_ns[1:0] = ALIGNED;
end
else if(wam_cnt_ff[4:0] == 5'd2) // Delay to wait reset
begin // propagation to read domain
wam_extrac_fsm_ns[1:0] = ALIGNED;
end
else // Waiting for word alignment or minimum delay
begin
wam_extrac_fsm_ns[1:0] = FIND_WAM;
end
end // Threshold met
else if(bit_mark_misalign) // Mark is not aligned
begin
wam_cnt_inc = 1'b0;
wam_cnt_rst = 1'b1;
wam_aligned = 1'b0;
wam_extrac_fsm_ns[1:0] = FIND_WAM;
end // Mark is not aligned
else // Still detecting mark threshold
begin
wam_cnt_inc = bit_mark_aligned;
wam_cnt_rst = 1'b0;
wam_aligned = 1'b0;
wam_extrac_fsm_ns[1:0] = FIND_WAM;
end // Still detecting mark threshold
end // FIFO_4X,FIFO_2X
default:// FIFO 1X
begin
wam_cnt_inc = 1'b0;
wam_cnt_rst = 1'b0;
wam_aligned = 1'b0;
wam_extrac_fsm_ns[1:0] = ALIGNED;
end // default
endcase // mode
end // FIND_WAM
ALIGNED: // Word mark is aligned
begin
wam_cnt_inc = 1'b0;
wam_aligned = 1'b1;
case(r_fifo_mode[1:0]) // Operation mode
FIFO_4X,FIFO_2X:
begin
if( bit_mark_misalign && // Mark is misssing
!rx_wa_mode_sync ) // Word alignment mode
begin
wam_extrac_fsm_ns[1:0] = ALING_LOST;
wam_cnt_rst = 1'b1;
end
else // Mark is in the corrent position
begin
wam_extrac_fsm_ns[1:0] = ALIGNED;
wam_cnt_rst = 1'b0;
end
end // FIFO_4X or FIFO 2X
default: // FIFO 1x or REG mode
begin
wam_extrac_fsm_ns[1:0] = ALIGNED;
wam_cnt_rst = 1'b0;
end // FIFO 1x or REG mode
endcase // Operation mode
end // ALIGNED
ALING_LOST: // Word alignment lost
begin
if( rx_wa_mode_sync || // Word alignment mode
( (wam_cnt_ff == rx_align_threshold) &&
bit_mark_aligned ) ) // Threshold met
begin
wam_cnt_inc = 1'b0;
wam_cnt_rst = 1'b0;
wam_aligned = 1'b0;
wam_extrac_fsm_ns[1:0] = ALIGNED;
end // Threshold met
else if(bit_mark_misalign) // Mark is not aligned
begin
wam_cnt_inc = 1'b0;
wam_cnt_rst = 1'b1;
wam_aligned = 1'b0;
wam_extrac_fsm_ns[1:0] = ALING_LOST;
end // Mark is not aligned
else // Still detecting mark threshold
begin
wam_cnt_inc = bit_mark_aligned;
wam_cnt_rst = 1'b0;
wam_aligned = 1'b0;
wam_extrac_fsm_ns[1:0] = ALING_LOST;
end // Still detecting mark threshold
end // ALING_LOST
endcase // current state check
end // block: wam_ext_fsm_nxt_out_logic
// Word alignment mark extraction FSM - current state
always @(posedge wr_clk or negedge wr_rst_n)
begin: wam_extrac_fsm_register
if(!wr_rst_n)
wam_extrac_fsm_ff[1:0] <= WAM_RESET;
else
wam_extrac_fsm_ff[1:0] <= wam_extrac_fsm_ns;
end // block: wam_extrac_fsm_register
// Register to indicate RX adapter is aligned
// WAM aligned output needs to be register to avoid
// Glitch in read clock synchronizer
always @(posedge wr_clk or negedge wr_rst_n)
begin: wam_aligned_register
if(!wr_rst_n)
wam_aligned_ff <= 1'b0;
else
wam_aligned_ff <= wam_aligned;
end // block: wam_aligned_register
// Output needs to be register to avoid
// Glitch in read clock synchronizer
// When stats is ALINGNED (10) or ALING_LOST (11),
// FIFO write is enable: state = 1x
assign wam_fifo_wren = wam_extrac_fsm_ff[1];
// wam_aligned synchronized in read clock domain
aib_bit_sync bitsync2_phcomp_wren
(
.clk (rd_clk), // Clock of destination domain
.rst_n (rd_rst_n), // Reset of destination domain
.data_in (wam_aligned_ff), // Input to be synchronized
.data_out (wam_alig_sync) // Synchronized output
);
endmodule // aib_rx_fifo_wam |
module aib_adapter_txchnl(
// Outputs
output wire [79:0] dout, // AIB Data output
// Inputs
input atpg_mode, // Scan enable
input txwr_fifo_rstn, // Tx write fifo reset
input txrd_rstn, // Tx read reset
input txrd_fifo_rstn, // Tx read fifo reset
input m_gen2_mode, // AIB Generation 2.0 indication
input txfifo_wr_clk, // Write clock
input tx_clk_adapter, // TX DLL clock to adapter
input [319:0] tx_adapt_din, // FIFO mode data input
input [79:0] data_in, // Register mode data input
input r_tx_dbi_en, // Enable for tx data bus inversion
input [1:0] r_tx_fifo_mode, // TX FIFO mode register
input [3:0] r_tx_phcomp_rd_delay, // TX phase compensation register
input r_txswap_en, // TX swapping enable
input r_tx_wm_en, // Tx word mark enable
input [4:0] r_tx_mkbit // Selection of word mark bit
);
wire [79:0] fifo_dout; // Output data from FIFO
wire [79:0] merge_dout; // Output slection based on operation mode
wire [79:0] data_in_f_sel; // Swapped data or input data to FIFO
//Mux for bypass mode data and fifo data
assign merge_dout[79:0]= (r_tx_fifo_mode == 2'b11) ?
data_in[79:0] :
fifo_dout[79:0];
//Data bus inversion logic (DBI)
aib_tx_dbi txdbi
(
.rst_n(txrd_rstn), // Async, reset
.clk(tx_clk_adapter), // Near side forwarded clock
.dbi_en(r_tx_dbi_en), // DBI enable
.data_in(merge_dout), // Data to be inverted by DBI logic
.data_out(dout) // Data after DBI logic
);
// Swapping logic used only in Gen 1 mode and 2xFIFO
assign data_in_f_sel[79:0] =
((r_tx_fifo_mode == 2'b01) & r_txswap_en & ~m_gen2_mode) ?
{tx_adapt_din[79],
tx_adapt_din[38:0],
tx_adapt_din[39],
tx_adapt_din[78:40]} :
tx_adapt_din[79:0];
// TX FIFO data path logic
aib_adapt_tx_fifo aib_adapt_tx_fifo (
// Outputs
.fifo_dout (fifo_dout[79:0]), // FIFO data output
// Inputs
.data_in ({tx_adapt_din[319:80], data_in_f_sel[79:0]}), // FIFO data input
.r_fifo_mode (r_tx_fifo_mode[1:0]), // FIFO mode register
.r_phcomp_rd_delay (r_tx_phcomp_rd_delay[3:0]), // Tx phase compensation
.m_gen2_mode (m_gen2_mode), // Generation 2.0 mode
.r_wm_en (r_tx_wm_en), // Tx swapping
.r_mkbit (r_tx_mkbit[4:0]), // Tx Mark bits
.scan_en (atpg_mode), // Scan enable
.wr_clk (txfifo_wr_clk), // Tx write clock
.wr_rst_n (txwr_fifo_rstn), // Tx FIFO write reset
.rd_clk (tx_clk_adapter), // TX DLL clock to adapter
.rd_rst_n (txrd_fifo_rstn) // Tx FIFO read reset
);
endmodule // aib_adapter_txchnl |
module aib_adapt_tx_fifo
#(
parameter ODWIDTH = 'd80, // FIFO output data width
parameter IDWIDTH = 'd320, // FIFO input data width
parameter DEPTH = 'd5, // FIFO Depth
parameter DEPTH4 = (DEPTH * 4), // FIFO Depth x 4
parameter AWIDTH = $clog2(DEPTH4) // FIFO address width
)
(
// Inputs
input wr_rst_n, // Write Domain Active low Reset
input wr_clk, // Write Domain Clock
input m_gen2_mode, // Generation 2 mode
input [IDWIDTH-1:0] data_in, // Write Data In
input rd_rst_n, // Read Domain Active low Reset
input rd_clk, // Read Domain Clock
input scan_en, // Scan enable
input r_wm_en, // mark enable
input [4:0] r_mkbit, // Configurable marker bit
input [1:0] r_fifo_mode, // FIFO Mode: 4:1 2:1 1:1 Reg mode
input [3:0] r_phcomp_rd_delay, // Programmable phase conpensation
// Outputs
output [ODWIDTH-1:0] fifo_dout // Read Data Out
);
//------------------------------------------------------------------------------
// Local Parameters
//------------------------------------------------------------------------------
localparam FIFO_1X = 2'b00; //Full rate
localparam FIFO_2X = 2'b01; //Half rate
localparam FIFO_4X = 2'b10; //Quarter Rate
localparam REG_MOD = 2'b11; //REG mode
// Valid word mark configuration in r_mkbit register
localparam [4:0] MARK_BIT_79 = 5'b10000;// Mark is in bit 79
localparam [4:0] MARK_BIT_78 = 5'b01000;// Mark is in bit 78
localparam [4:0] MARK_BIT_77 = 5'b00100;// Mark is in bit 77
localparam [4:0] MARK_BIT_76 = 5'b00010;// Mark is in bit 76
localparam [4:0] MARK_BIT_39 = 5'b00001;// Mark is in bit 39
//------------------------------------------------------------------------------
// Define wires and regs
//------------------------------------------------------------------------------
wire register_mode; // Register mode indication
wire phcomp_mode; // FIFO mode where phase compensation is used
wire phcomp_rden_int; // Internal read enable to get data from FIFO
wire phcomp_wren; // Write enable synchronized at write clock domain
wire phcomp_wren_sync2; // Write enable synchronized at read clock domain
wire wr_en_int; // FIFO write enable
wire rd_en_int; // FIFO read enable
wire phcomp_wren_sync; // Write enable after compensation of phase
wire [DEPTH-1:0] tff_clk_39_0; // Clocks for word 39-0
wire [DEPTH-1:0] tff_clk_79_40; // Clocks for word 79-40
wire [DEPTH-1:0] tff_clk_119_80; // Clocks for word 119-80
wire [DEPTH-1:0] tff_clk_159_120; // Clocks for word 159-120
wire [DEPTH-1:0] tff_clk_199_160;
wire [DEPTH-1:0] tff_clk_239_200;
wire [DEPTH-1:0] tff_clk_279_240;
wire [DEPTH-1:0] tff_clk_319_280;
wire [DEPTH-1:0][IDWIDTH-1:0] fifo_data_ff; // Data of FIFO array
wire [DEPTH4-1:0] fifo_rd_en; // TX FIFO read enable
wire phcomp_rden;
reg phcomp_wren_d0; // First flop to to sample write enable after reset
reg phcomp_wren_d1; // Second flop to to sample write enable after reset
reg phcomp_wren_d2; // Write enable synchronized at write clock domain
reg phcomp_wren_sync3; // Additional delay after read clock domain sync.
reg phcomp_wren_sync4; // Additional delay after read clock domain sync.
reg phcomp_wren_sync5; // Additional delay after read clock domain sync.
reg phcomp_wren_sync6; // Additional delay after read clock domain sync.
reg phcomp_wren_sync7; // Additional delay after read clock domain sync.
reg phcomp_wren_sync8; // Additional delay after read clock domain sync.
reg phcomp_wren_sync9; // Additional delay after read clock domain sync.
reg phcomp_wren_sync10; // Additional delay after read clock domain sync.
reg phcomp_wren_sync11; // Additional delay after read clock domain sync.
reg [IDWIDTH-1:0] wr_data; // Write data to be written into FIFO
reg [AWIDTH-1 :0]txf_wr_pnt_ff; // TX FIFO write pointer
reg [DEPTH4-1:0] txf_rd_pnt_ff; // TX FIFO read pointer
reg [AWIDTH-1 :0] txf_wr_pnt_in; // Next value of TX FIFO write pointer
reg [319:0] fifo_wr_data;
reg co_nc;
// FIFO mode decode to detect register mode
assign register_mode = (r_fifo_mode == REG_MOD);
// FIFO mode where phase compensation is enabled
assign phcomp_mode = ~ register_mode;
// FIFO write data logic to insert word mark bits
always @(*)
begin: fifo_write_data_logic
if (r_wm_en) // Word Mark insertion is enabled
begin
if (r_fifo_mode == FIFO_4X) // FIFO 4x mode
begin
case(r_mkbit[4:0])
MARK_BIT_79: // Mark is in bit 79
begin
wr_data = { {1'b1, data_in[318:240]},
{1'b0, data_in[238:160]},
{1'b0, data_in[158:80]},
{1'b0, data_in[78:0]} }; //bit 79
end
MARK_BIT_78: // Mark is in bit 78
begin
wr_data = { {data_in[319], 1'b1, data_in[317:240]},
{data_in[239], 1'b0, data_in[237:160]},
{data_in[159], 1'b0, data_in[157:80]},
{data_in[79], 1'b0, data_in[77:0]} }; //bit 78
end
MARK_BIT_77: // Mark is in bit 77
begin
wr_data = { {data_in[319:318], 1'b1, data_in[316:240]},
{data_in[239:238], 1'b0, data_in[236:160]},
{data_in[159:158], 1'b0, data_in[156:80]},
{data_in[79:78], 1'b0, data_in[76:0]} }; //bit 77
end
MARK_BIT_76: // Mark is in bit 76
begin
wr_data = { {data_in[319:317], 1'b1, data_in[315:240]},
{data_in[239:237], 1'b0, data_in[235:160]},
{data_in[159:157], 1'b0, data_in[155:80]},
{data_in[79:77], 1'b0, data_in[75:0]} }; //bit 76
end
MARK_BIT_39: // Mark is in bit 39
begin
wr_data = { {data_in[319:280], 1'b1, data_in[278:240]},
{data_in[239:200], 1'b0, data_in[198:160]},
{data_in[159:120], 1'b0, data_in[118:80]},
{data_in[79:40], 1'b0, data_in[38:0]} }; //bit 39
end
default: // No mark bit enabled - bypass
begin
wr_data = data_in; // No mark bit enabled
end
endcase
end
else if (r_fifo_mode == FIFO_2X) // FIFO 2x mode
begin
case(r_mkbit[4:0])
MARK_BIT_79: // Mark is in bit 79
begin
wr_data = { 160'h0,
{1'b1, data_in[158:80]},
{1'b0, data_in[78:0]} };
end
MARK_BIT_78: // Mark is in bit 78
begin
wr_data = { 160'h0,
{data_in[159], 1'b1, data_in[157:80]},
{data_in[79], 1'b0, data_in[77:0]} };
end
MARK_BIT_77: // Mark is in bit 77
begin
wr_data = { 160'h0,
{data_in[159:158], 1'b1, data_in[156:80]},
{data_in[79:78], 1'b0, data_in[76:0]} };
end
MARK_BIT_76: // Mark is in bit 76
begin
wr_data = { 160'h0,
{data_in[159:157], 1'b1, data_in[155:80]},
{data_in[79:77], 1'b0, data_in[75:0]} };
end
MARK_BIT_39: // Mark is in bit 39
begin
if(m_gen2_mode) // GEN2 mode
begin
wr_data = { 160'h0,
{data_in[159:120], 1'b1, data_in[118:80]},
{data_in[79:40], 1'b0, data_in[38:0]} };
end // GEN2 mode
else // GEN1 mode
begin
wr_data = { 160'h0,
{40'h0, 1'b1, data_in[78:40]},
{40'h0, 1'b0, data_in[38:0]} };
end // GEN1 mode
end
default: // No mark bit enabled - bypass
begin
wr_data = data_in; // No mark bit enabled
end
endcase
end
else // Data bypass
wr_data = data_in;
end // Word Mark insertion is enabled
else
begin // Mark is disabled
if ((r_fifo_mode == FIFO_2X) & ~m_gen2_mode) // FIFO 2x and Gen1
wr_data ={ 160'h0,
{40'h0, data_in[79:40]},
{40'h0, data_in[39:0]}};
else // Data bypass
wr_data = data_in;
end // Mark is disabled
end // block: fifo_write_data_logic
//********************************************************************
// Read Write logic
//********************************************************************
// Write enable
assign wr_en_int = phcomp_mode & phcomp_wren; // Phase Comp Indiviual mode
// Read enable
assign rd_en_int = phcomp_mode & phcomp_rden_int; // Phase Comp Indiviual mode
// Phase Comp FIFO mode Write/Read enable logic generation
// Write Enable
always @(negedge wr_rst_n or posedge wr_clk)
begin: wren_phase_register
if (wr_rst_n == 1'b0)
begin
phcomp_wren_d0 <= 1'b0;
phcomp_wren_d1 <= 1'b0;
phcomp_wren_d2 <= 1'b0;
end
else
begin
phcomp_wren_d0 <= 1'b1; // Indv: 1, Bonding: goes high and stays high
phcomp_wren_d1 <= phcomp_wren_d0;
phcomp_wren_d2 <= phcomp_wren_d1;
end
end // block: wren_phase_register
assign phcomp_wren = phcomp_wren_d2;
// phcomp_wren Synchronizer
aib_bit_sync bitsync2_phcomp_wren
(
.clk (rd_clk), // Clock of destination domain
.rst_n (rd_rst_n), // Reset of destination domain
.data_in (phcomp_wren), // Input to be synchronized
.data_out (phcomp_wren_sync2) // Synchronized output
);
// Write enable delay registers
always @(negedge rd_rst_n or posedge rd_clk)
begin: phcomp_wren_sync_register
if (rd_rst_n == 1'b0)
begin
phcomp_wren_sync3 <= 1'b0;
phcomp_wren_sync4 <= 1'b0;
phcomp_wren_sync5 <= 1'b0;
phcomp_wren_sync6 <= 1'b0;
phcomp_wren_sync7 <= 1'b0;
phcomp_wren_sync8 <= 1'b0;
phcomp_wren_sync9 <= 1'b0;
phcomp_wren_sync10 <= 1'b0;
phcomp_wren_sync11 <= 1'b0;
end // reset
else
begin
phcomp_wren_sync3 <= phcomp_wren_sync2;
phcomp_wren_sync4 <= phcomp_wren_sync3;
phcomp_wren_sync5 <= phcomp_wren_sync4;
phcomp_wren_sync6 <= phcomp_wren_sync5;
phcomp_wren_sync7 <= phcomp_wren_sync6;
phcomp_wren_sync8 <= phcomp_wren_sync7;
phcomp_wren_sync9 <= phcomp_wren_sync8;
phcomp_wren_sync10 <= phcomp_wren_sync9;
phcomp_wren_sync11 <= phcomp_wren_sync10;
end
end // block: phcomp_wren_sync_register
// Read Enable
assign phcomp_wren_sync =
(r_phcomp_rd_delay[3:0] == 4'b1011) ? phcomp_wren_sync11 :
(r_phcomp_rd_delay[3:0] == 4'b1010) ? phcomp_wren_sync10 :
(r_phcomp_rd_delay[3:0] == 4'b1001) ? phcomp_wren_sync9 :
(r_phcomp_rd_delay[3:0] == 4'b1000) ? phcomp_wren_sync8 :
(r_phcomp_rd_delay[3:0] == 4'b0111) ? phcomp_wren_sync7 :
(r_phcomp_rd_delay[3:0] == 4'b0110) ? phcomp_wren_sync6 :
(r_phcomp_rd_delay[3:0] == 4'b0101) ? phcomp_wren_sync5 :
(r_phcomp_rd_delay[3:0] == 4'b0100) ? phcomp_wren_sync4 :
(r_phcomp_rd_delay[3:0] == 4'b0011) ? phcomp_wren_sync3 :
phcomp_wren_sync2;
// Configured delay selected
assign phcomp_rden = phcomp_wren_sync;
// Read enable
assign phcomp_rden_int = phcomp_rden;
always @(*)
begin
case(r_fifo_mode[1:0])
FIFO_2X:
begin
if( txf_wr_pnt_ff[AWIDTH-1:0] == (DEPTH4-2) )
begin
{co_nc,txf_wr_pnt_in[AWIDTH-1:0]} = {(AWIDTH+1){1'b0}};
end
else
begin
{co_nc,txf_wr_pnt_in[AWIDTH-1:0]} = txf_wr_pnt_ff[AWIDTH-1:0] +
{{(AWIDTH-2){1'b0}}, 2'b10};
end
end
FIFO_4X:
begin
if( txf_wr_pnt_ff[AWIDTH-1:0] == (DEPTH4-4) )
begin
{co_nc,txf_wr_pnt_in[AWIDTH-1:0]} = {(AWIDTH+1){1'b0}};
end
else
begin
{co_nc,txf_wr_pnt_in[AWIDTH-1:0]} = txf_wr_pnt_ff[AWIDTH-1:0] +
{{(AWIDTH-3){1'b0}}, 3'b100};
end
end
default:
begin
if(txf_wr_pnt_ff[AWIDTH-1:0] == (DEPTH4-1))
begin
{co_nc,txf_wr_pnt_in[AWIDTH-1:0]} = {(AWIDTH+1){1'b0}};
end
else
begin
{co_nc,txf_wr_pnt_in[AWIDTH-1:0]} = txf_wr_pnt_ff[AWIDTH-1:0] +
{{(AWIDTH-1){1'b0}}, 1'b1};
end
end
endcase
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(!wr_rst_n)
txf_wr_pnt_ff[AWIDTH-1:0] <= {AWIDTH{1'b0}};
else if(wr_en_int)
txf_wr_pnt_ff[AWIDTH-1:0] <= txf_wr_pnt_in[AWIDTH-1:0];
end
aib_txfifo_clk_gating #(.FF_DEPTH (DEPTH))
aib_txfifo_clk_gating
(
// Outputs
.tff_clk_39_0 (tff_clk_39_0[DEPTH-1:0]), // Clocks for word 39-0
.tff_clk_79_40 (tff_clk_79_40[DEPTH-1:0]), // Clocks for word 79-40
.tff_clk_119_80 (tff_clk_119_80[DEPTH-1:0]), // Clocks for word 119-80
.tff_clk_159_120 (tff_clk_159_120[DEPTH-1:0]), // Clocks for word 159-120
.tff_clk_199_160 (tff_clk_199_160[DEPTH-1:0]),
.tff_clk_239_200 (tff_clk_239_200[DEPTH-1:0]),
.tff_clk_279_240 (tff_clk_279_240[DEPTH-1:0]),
.tff_clk_319_280 (tff_clk_319_280[DEPTH-1:0]),
// Inputs
.txf_wr_clk (wr_clk), // TX FIFO write clock
.txf_wr_en (wr_en_int), // TX FIFO write enable
.txf_pnt_ff (txf_wr_pnt_ff[AWIDTH-1:0]), // Indicates TX FIFO element
.tx_fifo_mode (r_fifo_mode[1:0]), // Indicates TX FIFO operation mode
.m_gen2_mode (m_gen2_mode), // Indicates TX FIFO operates in GEN2 mode
.scan_en (scan_en) // Scan enable
);
always @(*)
begin
case(r_fifo_mode[1:0])
FIFO_1X:
begin
fifo_wr_data[319:0] = { wr_data[79:0],
wr_data[79:0],
wr_data[79:0],
wr_data[79:0] };
end
FIFO_2X:
begin
fifo_wr_data[319:0] = {wr_data[159:0],wr_data[159:0]};
end
default:
begin
fifo_wr_data[319:0] = wr_data[319:0];
end
endcase
end
aib_adapt_fifo_mem #(
.DWIDTH (IDWIDTH), // FIFO Input data width
.DEPTH (DEPTH) // FIFO Depth
)
aib_adapt_txfifo_mem
(
// Inputs
.ff_clk_39_0 (tff_clk_39_0[DEPTH-1:0]), // clocks for bits 39-0 of FIFO
.ff_clk_79_40 (tff_clk_79_40[DEPTH-1:0]), // clocks for bits 79-40 of FIFO
.ff_clk_119_80 (tff_clk_119_80[DEPTH-1:0]), // clocks for bits 119-80 of FIFO
.ff_clk_159_120 (tff_clk_159_120[DEPTH-1:0]), // clocks for bits 159-120 of FIFO
.ff_clk_199_160 (tff_clk_199_160[DEPTH-1:0]),
.ff_clk_239_200 (tff_clk_239_200[DEPTH-1:0]),
.ff_clk_279_240 (tff_clk_279_240[DEPTH-1:0]),
.ff_clk_319_280 (tff_clk_319_280[DEPTH-1:0]),
.ff_rst_n (wr_rst_n), // FIFO array reset
.wr_data (fifo_wr_data[IDWIDTH-1:0]), // FIFO write data bus
// Outputs
.fifo_data_ff (fifo_data_ff) // FIFO data
);
// TX FIFO Read pointer register
always @(posedge rd_clk or negedge rd_rst_n)
begin: txf_rd_pnt_register
if (!rd_rst_n)
txf_rd_pnt_ff[DEPTH4-1:0] <= {{(DEPTH4-1){1'b0}},1'b1};
else if (rd_en_int)
txf_rd_pnt_ff[DEPTH4-1:0] <= { txf_rd_pnt_ff[DEPTH4-2:0],
txf_rd_pnt_ff[DEPTH4-1] };
end // block: txf_rd_pnt_register
// Enables read in RX FIFO
assign fifo_rd_en[DEPTH4-1:0] = txf_rd_pnt_ff[DEPTH4-1:0] &
{DEPTH4{rd_en_int}};
aib_txfifo_rd_dpath #(
.DINW (IDWIDTH),
.DOUTW (ODWIDTH),
.DEPTH (DEPTH)
)
aib_txfifo_rd_dpath
(
// Output
.rdata_sync_ff (fifo_dout[ODWIDTH-1:0]), // Read data synchronized
// Inputs
.fifo_rd_en (fifo_rd_en[DEPTH4-1:0]), // FIFO element selector
.fifo_data_async (fifo_data_ff), // FIFO data
.rd_clk (rd_clk), // FIFO read clock
.rd_rst_n (rd_rst_n) // FIFO read asynchronous reset
);
endmodule // aib_adapt_tx_fifo |
module aib_txfifo_clk_gating #(
parameter FF_DEPTH = 16,
parameter DEPTH4 = (FF_DEPTH * 4),
parameter PNT_S = $clog2(DEPTH4)
)
(
// Outputs
output [FF_DEPTH-1:0] tff_clk_39_0, // Clocks for word 39-0 of TX FIFO
output [FF_DEPTH-1:0] tff_clk_79_40, // Clocks for word 79-40 of TX FIFO
output [FF_DEPTH-1:0] tff_clk_119_80, // Clocks for word 119-80 of TX FIFO
output [FF_DEPTH-1:0] tff_clk_159_120, // Clocks for word 159-120 of TX FIFO
output [FF_DEPTH-1:0] tff_clk_199_160,
output [FF_DEPTH-1:0] tff_clk_239_200,
output [FF_DEPTH-1:0] tff_clk_279_240,
output [FF_DEPTH-1:0] tff_clk_319_280,
// Inputs
input txf_wr_clk, // TX FIFO write clock
input txf_wr_en, // TX FIFO write enable
input [PNT_S-1:0] txf_pnt_ff, // Indicates TX FIFO element to be written
input [1:0] tx_fifo_mode, // Indicates TX FIFO operation mode
input m_gen2_mode, // Indicates TX FIFO operates in GEN2 mode
input scan_en // Scan enable
);
localparam [1:0] FIFO1X = 2'b00; // FIFO 1X mode
localparam [1:0] FIFO2X = 2'b01; // FIFO 2X mode
localparam [1:0] FIFO4X = 2'b10; // FIFO 4X mode
localparam [1:0] WD_79_0 = 2'b00;
localparam [1:0] WD_159_80 = 2'b01;
localparam [1:0] WD_239_160 = 2'b10;
localparam [1:0] WD_319_240 = 2'b11;
localparam [0:0] WD_159_0 = 1'b0;
localparam [0:0] WD_319_160 = 1'b1;
reg [FF_DEPTH-1:0] tff_clk_39_0_en; // Clocks enable for word 39-0
reg [FF_DEPTH-1:0] tff_clk_79_40_en; // Clocks enable for word 79-40
reg [FF_DEPTH-1:0] tff_clk_119_80_en; // Clocks enable for word 119-80
reg [FF_DEPTH-1:0] tff_clk_159_120_en; // Clocks enable for word 159-120
reg [FF_DEPTH-1:0] tff_clk_199_160_en;
reg [FF_DEPTH-1:0] tff_clk_239_200_en;
reg [FF_DEPTH-1:0] tff_clk_279_240_en;
reg [FF_DEPTH-1:0] tff_clk_319_280_en;
// TX FIFO clock enable logic
always @(*)
begin: tx_fifo_clk_en_logic
tff_clk_39_0_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_79_40_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_119_80_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_159_120_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_199_160_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_239_200_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_279_240_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_319_280_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
case(tx_fifo_mode[1:0])
FIFO1X: // FIFO 1X mode
begin
case(txf_pnt_ff[1:0])
WD_79_0:
begin
tff_clk_39_0_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
if(m_gen2_mode)
tff_clk_79_40_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
end
WD_159_80:
begin
tff_clk_119_80_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
if(m_gen2_mode)
tff_clk_159_120_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
end
WD_239_160:
begin
tff_clk_199_160_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
if(m_gen2_mode)
tff_clk_239_200_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
end
WD_319_240:
begin
tff_clk_279_240_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
if(m_gen2_mode)
tff_clk_319_280_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
end
endcase
end // FIFO1X
FIFO2X: // FIFO 2X mode
begin
case(txf_pnt_ff[1])
WD_159_0:
begin
tff_clk_39_0_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_119_80_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
if(m_gen2_mode)
begin
tff_clk_79_40_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_159_120_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
end
end
WD_319_160:
begin
tff_clk_199_160_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_279_240_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
if(m_gen2_mode)
begin
tff_clk_239_200_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_319_280_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
end
end
endcase
end
FIFO4X: // FIFO 4X mode
begin
tff_clk_39_0_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_79_40_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_119_80_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_159_120_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_199_160_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_239_200_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_279_240_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
tff_clk_319_280_en[txf_pnt_ff[PNT_S-1:2]] = txf_wr_en;
end // FIFO4X
default: // default - reg mode
begin
tff_clk_39_0_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_79_40_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_119_80_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_159_120_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_199_160_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_239_200_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_279_240_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
tff_clk_319_280_en[FF_DEPTH-1:0] = {FF_DEPTH{1'b0}};
end // default
endcase
end // block: tx_fifo_clk_en_logic
genvar i;
// Clock gates for FIFO word 39-0
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_39_0_gen
clk_gate_cel clk_gate_cel_39_0(
.clkout (tff_clk_39_0[i]), // Clock gated
.clk (txf_wr_clk), // Clock input
.en (tff_clk_39_0_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_39_0_gen
endgenerate
// Clock gates for FIFO word 79-40
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_79_40_gen
clk_gate_cel clk_gate_cel_79_40(
.clkout (tff_clk_79_40[i]), // Clock gated
.clk (txf_wr_clk), // Clock input
.en (tff_clk_79_40_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_79_40_gen
endgenerate
// Clock gates for FIFO word 119-80
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_119_80_gen
clk_gate_cel clk_gate_cel_119_80(
.clkout (tff_clk_119_80[i]), // Clock gated
.clk (txf_wr_clk), // Clock input
.en (tff_clk_119_80_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_119_80_gen
endgenerate
// Clock gates for FIFO word 159-120
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_159_120_gen
clk_gate_cel clk_gate_cel_159_120(
.clkout (tff_clk_159_120[i]), // Clock gated
.clk (txf_wr_clk), // Clock input
.en (tff_clk_159_120_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_159_120_gen
endgenerate
// Clock gates for FIFO word 199-160
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_199_160_gen
clk_gate_cel clk_gate_cel_199_160(
.clkout (tff_clk_199_160[i]), // Clock gated
.clk (txf_wr_clk), // Clock input
.en (tff_clk_199_160_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_199_160_gen
endgenerate
// Clock gates for FIFO word 239-200
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_239_200_gen
clk_gate_cel clk_gate_cel_239_200(
.clkout (tff_clk_239_200[i]), // Clock gated
.clk (txf_wr_clk), // Clock input
.en (tff_clk_239_200_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_239_200_gen
endgenerate
// Clock gates for FIFO word 279-240
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_279_240_gen
clk_gate_cel clk_gate_cel_279_240(
.clkout (tff_clk_279_240[i]), // Clock gated
.clk (txf_wr_clk), // Clock input
.en (tff_clk_279_240_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_279_240_gen
endgenerate
// Clock gates for FIFO word 319-280
generate
for(i=0;i<FF_DEPTH;i = i+1)
begin: clk_gate_cel_319_280_gen
clk_gate_cel clk_gate_cel_319_280(
.clkout (tff_clk_319_280[i]), // Clock gated
.clk (txf_wr_clk), // Clock input
.en (tff_clk_319_280_en[i]), // Clock enable
.te (scan_en) // Test enable
);
end // block: clk_gate_cel_319_280_gen
endgenerate
endmodule // aib_txfifo_clk_gating |
module aib_avalon_adapt_reg (
output [31:0] rx_0, // Rx Adapt configuration register 0
output [31:0] rx_1, // Rx Adapt configuration register 1
output [31:0] tx_0, // Tx Adapt configuration register 0
output [31:0] tx_1, // Tx Adapt configuration register 1
//------------------------------------------------------------------------------
// BERT access interface
//------------------------------------------------------------------------------
output [ 5:0] bert_acc_addr, // BERT access address
output bert_acc_req, // BERT access request
output bert_acc_rdwr, // BERT access read/write control
output reg [31:0] bert_wdata_ff, // BERT data to be written
input [31:0] rx_bert_rdata_ff, // Read data from RX BERT interface
input [31:0] tx_bert_rdata_ff, // Read data from TX BERT interface
input bert_acc_rq_pend, // BERT configuration load is pending
//------------------------------------------------------------------------------
// TX BERT control interface
//------------------------------------------------------------------------------
output [3:0] tx_bert_start, // Starts transmitting TX BERT bit sequence
output [3:0] tx_bert_rst, // Resets TX BERT registers
//------------------------------------------------------------------------------
// TX BERT status interface
//------------------------------------------------------------------------------
input bert_seed_good, // Indicates all BPRS seeds are not zero.
input [3:0] txbert_run_ff, // Indicates TX BERT is running
//------------------------------------------------------------------------------
// RX BERT control interface
//------------------------------------------------------------------------------
output [3:0] rxbert_start, // Starts checking input of RX BERT bit sequence
output [3:0] rxbert_rst, // Resets RX BERT registers
output [3:0] rxbert_seed_in, // Enables the self-seeding in RX BERT
//------------------------------------------------------------------------------
// RX BERT status interface
//------------------------------------------------------------------------------
input [ 3:0] rxbert_run_ff, // Indicates RX BERT is running
input [ 3:0] rxbert_biterr_ff, // Error detected in RX BERT checker
// BERT enable
output tx_bert_en, // TX BERT enable
//------------------------------------------------------------------------------
// Bus Interface
//------------------------------------------------------------------------------
input clk, // Access Clock
input reset, // Asynchronous reset
input [31:0] writedata, // Write data bus
input read, // Read data bus
input write, // Write enable
input [ 3:0] byteenable, // Byte enable
input [ 7:0] address, // Address bus
input tx_clk_div_ld_ack, // TX clock divider load ack
input rx_clk_div_ld_ack, // RX clock divider load ack
output reg [31:0] readdata, // Read data bus
output reg tx_clk_div_ld_ff, // Loads Tx clock divider selection
output reg tx_clk_div_1_ff, // Tx Clock divided by 1 selection
output reg tx_clk_div_2_ff, // Tx Clock divided by 2 selection
output reg tx_clk_div_4_ff, // Tx Clock divided by 4 selection
output reg rx_clk_div_ld_ff, // Loads Rx clock divider selection
output reg rx_clk_div_1_ff, // Rx Clock divided by 1 selection
output reg rx_clk_div_2_ff, // Rx Clock divided by 2 selection
output reg rx_clk_div_4_ff // Rx Clock divided by 4 selection
);
wire reset_n; // Active low reset
wire [ 3:0] we_rx_0; // Rx0 register write enable
wire [ 3:0] we_rx_1; // Tx1 register write enable
wire [ 3:0] we_tx_0; // Rx0 register write enable
wire [ 3:0] we_tx_1; // Tx1 register write enable
wire tx_div_if_busy; // Indicates Tx div CDC interface is busy
wire rx_div_if_busy; // Indicates rx div CDC interface is busy
wire tx_clk_div_ack_sync; // Tx clock divider ack synchronized
wire rx_clk_div_ack_sync; // Rx clock divider ack synchronized
wire txclk_div_update; // Tx clock divided update
wire rxclk_div_update; // Rx clock divided update
wire txclk_div1_sel; // Tx clock divided by 1 selection
wire txclk_div2_sel; // Tx clock divided by 2 selection
wire txclk_div4_sel; // Tx clock divided by 4 selection
wire rxclk_div1_sel; // Tx clock divided by 1 selection
wire rxclk_div2_sel; // Tx clock divided by 2 selection
wire rxclk_div4_sel; // Tx clock divided by 4 selection
reg [31:0] rdata_comb; // combinatorial read data signal declaration
reg [31:0] rx_0_ff; // Rx Adapt configuration register 0
reg [31:0] rx_1_ff; // Rx Adapt configuration register 1
reg [31:0] tx_0_ff; // Tx Adapt configuration register 0
reg [31:0] tx_1_ff; // Tx Adapt configuration register 1
//------------------------------------------------------------------------------
// BERT access request register - ADDR OFF = 0x20
//------------------------------------------------------------------------------
wire bert_acc_rq_sel; // Seed load register selection
wire bert_acc_rq_wbyte_7_0; // Seed load write into byte 7-0
wire bert_acc_rq_wbyte_23_16; // Seed load write into byte 23-16
wire bert_acc_rq_wbyte_31_24; // Seed load write into byte 31-24
wire [31:0] bert_acc_rq_rdata; // Seed load read data
//------------------------------------------------------------------------------
// BERT write data register - ADDR OFF = 0x24
//------------------------------------------------------------------------------
wire bert_wdata_sel; // BERT configuration input register selection
wire bert_wdata_wbyte_7_0; // BERT config input register write into byte 7-0
wire bert_wdata_wbyte_15_8; // BERT config input register write into byte 15-8
wire bert_wdata_wbyte_23_16; // BERT conf. input register write into byte 23-16
wire bert_wdata_wbyte_31_24; // BERT conf. input register write into byte 31-24
//------------------------------------------------------------------------------
// TX BERT control register - ADDR OFF = 0x28
//------------------------------------------------------------------------------
wire txbert_ctrl_sel; // TX BERT control register selection
wire txbert_ctrl_wbyte_7_0; // Write into byte 7-0 of TX BERT control register
wire txbert_ctrl_wbyte_23_16; // Write into byte 23-16 of TX BERT ctrl register
//------------------------------------------------------------------------------
// TX BERT status register - ADDR OFF = 0x2C
//------------------------------------------------------------------------------
wire [31:0] txbert_st_rdata; // TX BERT status data
//------------------------------------------------------------------------------
// RX BERT control register - ADDR OFF = 0x30
//------------------------------------------------------------------------------
wire rxbert_ctrl_sel; // RX BERT control register selection
wire rxbert_ctrl_wbyte_7_0; // Write into byte 7-0 of RX BERT control register
wire rxbert_ctrl_wbyte_23_16; // Write into byte 23-16 of RX BERT ctrl register
wire rxbert_ctrl_wbyte_31_24; // Write into byte 31-24 of RX BERT ctrl register
//------------------------------------------------------------------------------
// RX BERT status register - ADDR OFF = 0x34
//------------------------------------------------------------------------------
wire [31:0] rxbert_st_rdata; // RX BERT status data
// --------------------------------------------------------------------
// Local parameters to enable bits in registers: RX0, RX1, TX0 and TX1
// --------------------------------------------------------------------
localparam [31:0] RX0_PARAM = { 4'h0, // reserved 31-28
4'hf, // rx_phcomp 27-24
20'h0, // Reserved 23-4
2'h3, // rx_clk_div 3-2
1'h1, // rx_dbi_en - bit 1
1'h1 }; // rxswap_en - bit 0
// RX1 register
localparam [31:0] RX1_PARAM ={ 1'h1, // rx_wa_mode
18'h0, // Reserved30-13
5'h1f, // rx_align_threshold
1'h1, // rx_marker_bit79
1'h1, // rx_marker_bit78
1'h1, // rx_marker_bit77
1'h1, // rx_marker_bit76
1'h1, // rx_marker_bit39
2'h3, // rx_fifo_mode1-0
1'h1 }; // rx_wa_en
// TX0 register
localparam [31:0] TX0_PARAM = { 4'hf, // tx_phcomp 30-28
1'h0, // reserved 27
1'h0, // reserved 26
2'h3, // tx_clk_div
1'h1, // tx_wm_en
2'h3, // tx_fifo_mode 1-0
1'h1, // tx_marker_bit79
1'h1, // tx_marker_bit78
1'h1, // tx_marker_bit77
1'h1, // tx_marker_bit76
1'h1, // tx_marker_bit39
14'h0, // Reserved 15-2
1'h1, // tx_dbi_en
1'h1 }; // txswap_en
// TX1 register
localparam [31:0] TX1_PARAM = { 1'h1, // SDR bit
1'h1, // PAD enable bit
14'h0, // Reserved
2'h3, // Loopback_mode 1-0
4'h0, // Reserved
1'h1, // fwd_clk_test
1'h1, // TX BERT enable
8'h0 }; // Reserved
// Reset value of RX_0 register
localparam [31:0] RX0_RST = {5'b0,3'b10,24'b0} & RX0_PARAM;
// Reset value of RX_1 register
localparam [31:0] RX1_RST = {19'b0,5'b10,8'b0} & RX1_PARAM;
// Reset value of TX_0 register
localparam [31:0] TX0_RST = {4'b10,28'b0} & TX0_PARAM;
// Reset value of TX_1 register
localparam [31:0] TX1_RST = {1'b0,1'b1,30'h0} & TX1_PARAM;
// Register address offsets
localparam [7:0] RX0_ADDR_OFF = 8'h08;
localparam [7:0] RX1_ADDR_OFF = 8'h10;
localparam [7:0] TX0_ADDR_OFF = 8'h18;
localparam [7:0] TX1_ADDR_OFF = 8'h1c;
localparam [7:0] BERT_ACC_RQ_ADDR_OFF = 8'h20;
localparam [7:0] BERT_WDATA_ADDR_OFF = 8'h24;
localparam [7:0] TXBERT_CTRL_ADDR_OFF = 8'h28;
localparam [7:0] TXBERT_ST_ADDR_OFF = 8'h2c;
localparam [7:0] TXBERT_RDATA_ADDR_OFF = 8'h30;
localparam [7:0] RXBERT_CTRL_ADDR_OFF = 8'h34;
localparam [7:0] RXBERT_ST_ADDR_OFF = 8'h38;
localparam [7:0] RXBERT_RDATA0_ADDR_OFF = 8'h3c;
// Active low reset
assign reset_n = !reset;
// synchronous process for the read
always @(negedge reset_n or posedge clk)
begin: readdata_register
if (!reset_n) // reset
readdata[31:0] <= 32'h0;
else
readdata[31:0] <= rdata_comb[31:0];
end // block: readdata_register
// ----------------------------------------------------
// A write byte enable for each register
// ----------------------------------------------------
assign we_rx_0[3:0] = write & (address[7:0] == RX0_ADDR_OFF) ?
byteenable[3:0] :
{4{1'b0}};
assign we_rx_1[3:0] = write & (address[7:0] == RX1_ADDR_OFF) ?
byteenable[3:0] :
{4{1'b0}};
assign we_tx_0[3:0] = write & (address[7:0] == TX0_ADDR_OFF) ?
byteenable[3:0] :
{4{1'b0}};
assign we_tx_1[3:0] = write & (address[7:0] == TX1_ADDR_OFF) ?
byteenable[3:0] :
{4{1'b0}};
// RX0 Register - byte 7-0
always @( negedge reset_n or posedge clk)
begin: rx_0_7_0_register
if(!reset_n) // reset
begin
rx_0_ff[7:0] <= RX0_RST[7:0];
end
else if(we_rx_0[0]) // Write enable
begin
rx_0_ff[7:0] <= writedata[7:0] & RX0_PARAM[7:0];
end
else // Keep value
begin
rx_0_ff[7:0] <= rx_0_ff[7:0] & RX0_PARAM[7:0];
end
end // block: rx_0_7_0_register
// RX0 Register - byte 15-8
always @( negedge reset_n or posedge clk)
begin: rx_0_15_8_register
if(!reset_n) // reset
begin
rx_0_ff[15:8] <= RX0_RST[15:8];
end
else if(we_rx_0[1]) // Write enable
begin
rx_0_ff[15:8] <= writedata[15:8] & RX0_PARAM[15:8];
end
else // Keep value
begin
rx_0_ff[15:8] <= rx_0_ff[15:8] & RX0_PARAM[15:8];
end
end // block: rx_0_15_8_register
// RX0 Register - byte 23-16
always @( negedge reset_n or posedge clk)
begin: rx_0_23_16_register
if(!reset_n) // reset
begin
rx_0_ff[23:16] <= RX0_RST[23:16];
end
else if(we_rx_0[2]) // Write enable
begin
rx_0_ff[23:16] <= writedata[23:16] & RX0_PARAM[23:16];
end
else // Keep value
begin
rx_0_ff[23:16] <= rx_0_ff[23:16] & RX0_PARAM[23:16];
end
end // block: rx_0_23_16_register
// RX0 Register - byte 31-24
always @( negedge reset_n or posedge clk)
begin: rx_0_31_24_register
if(!reset_n) // reset
begin
rx_0_ff[31:24] <= RX0_RST[31:24];
end
else if(we_rx_0[3]) // Write enable
begin
rx_0_ff[31:24] <= writedata[31:24] & RX0_PARAM[31:24];
end
else // Keep value
begin
rx_0_ff[31:24] <= rx_0_ff[31:24] & RX0_PARAM[31:24];
end
end // block: rx_0_31_24_register
// RX1 Register - byte 7-0
always @( negedge reset_n or posedge clk)
begin: rx_1_7_0_register
if(!reset_n) // reset
begin
rx_1_ff[7:0] <= RX1_RST[7:0];
end
else if(we_rx_1[0]) // Write enable
begin
rx_1_ff[7:0] <= writedata[7:0] & RX1_PARAM[7:0];
end
else // Keep value
begin
rx_1_ff[7:0] <= rx_1_ff[7:0] & RX1_PARAM[7:0];
end
end // block: rx_1_7_0_register
// RX1 Register - byte 15-8
always @( negedge reset_n or posedge clk)
begin: rx_1_15_8_register
if(!reset_n) // reset
begin
rx_1_ff[15:8] <= RX1_RST[15:8];
end
else if(we_rx_1[1]) // Write enable
begin
rx_1_ff[15:8] <= writedata[15:8] & RX1_PARAM[15:8];
end
else // Keep value
begin
rx_1_ff[15:8] <= rx_1_ff[15:8] & RX1_PARAM[15:8];
end
end // block: rx_1_15_8_register
// RX1 Register - byte 23-16
always @( negedge reset_n or posedge clk)
begin: rx_1_23_16_register
if(!reset_n) // reset
begin
rx_1_ff[23:16] <= RX1_RST[23:16];
end
else if(we_rx_1[2]) // Write enable
begin
rx_1_ff[23:16] <= writedata[23:16] & RX1_PARAM[23:16];
end
else // Keep value
begin
rx_1_ff[23:16] <= rx_1_ff[23:16] & RX1_PARAM[23:16];
end
end // block: rx_1_23_16_register
// RX1 Register - byte 30-24
always @( negedge reset_n or posedge clk)
begin: rx_1_30_24_register
if(!reset_n) // reset
begin
rx_1_ff[30:24] <= RX1_RST[30:24];
end
else if(we_rx_1[3]) // Write enable
begin
rx_1_ff[30:24] <= writedata[30:24] & RX1_PARAM[30:24];
end
else // Keep value
begin
rx_1_ff[30:24] <= rx_1_ff[30:24] & RX1_PARAM[30:24];
end
end // block: rx_1_30_24_register
// RX1 Register - byte 31 - sticky bit rx_wa_mode
always @( negedge reset_n or posedge clk)
begin: rx_1_31_register
if(!reset_n) // reset
begin
rx_1_ff[31] <= RX1_RST[31];
end
else if(we_rx_1[3] && !rx_1_ff[31]) // Write enable
begin
rx_1_ff[31] <= writedata[31] & RX1_PARAM[31];
end
else // Keep value
begin
rx_1_ff[31] <= rx_1_ff[31] & RX1_PARAM[31];
end
end // block: rx_1_31_register
// TX0 Register - byte 7-0
always @( negedge reset_n or posedge clk)
begin: tx_0_7_0_register
if(!reset_n) // reset
begin
tx_0_ff[7:0] <= TX0_RST[7:0];
end
else if(we_tx_0[0]) // Write enable
begin
tx_0_ff[7:0] <= writedata[7:0] & TX0_PARAM[7:0];
end
else // Keep value
begin
tx_0_ff[7:0] <= tx_0_ff[7:0] & TX0_PARAM[7:0];
end
end // block: tx_0_7_0_register
// TX0 Register - byte 15-8
always @( negedge reset_n or posedge clk)
begin: tx_0_15_8_register
if(!reset_n) // reset
begin
tx_0_ff[15:8] <= TX0_RST[15:8];
end
else if(we_tx_0[1]) // Write enable
begin
tx_0_ff[15:8] <= writedata[15:8] & TX0_PARAM[15:8];
end
else // Keep value
begin
tx_0_ff[15:8] <= tx_0_ff[15:8] & TX0_PARAM[15:8];
end
end // block: tx_0_15_8_register
// TX0 Register - byte 23-16
always @( negedge reset_n or posedge clk)
begin: tx_0_23_16_register
if(!reset_n) // reset
begin
tx_0_ff[23:16] <= TX0_RST[23:16];
end
else if(we_tx_0[2]) // Write enable
begin
tx_0_ff[23:16] <= writedata[23:16] & TX0_PARAM[23:16];
end
else // Keep value
begin
tx_0_ff[23:16] <= tx_0_ff[23:16] & TX0_PARAM[23:16];
end
end // block: tx_0_23_16_register
// TX0 Register - byte 31-24
always @( negedge reset_n or posedge clk)
begin: tx_0_31_24_register
if(!reset_n) // reset
begin
tx_0_ff[31:24] <= TX0_RST[31:24];
end
else if(we_tx_0[3]) // Write enable
begin
tx_0_ff[31:24] <= writedata[31:24] & TX0_PARAM[31:24];
end
else // Keep value
begin
tx_0_ff[31:24] <= tx_0_ff[31:24] & TX0_PARAM[31:24];
end
end // block: tx_0_31_24_register
// TX1 Register - byte 7-0
always @( negedge reset_n or posedge clk)
begin: tx_1_7_0_register
if(!reset_n) // reset
begin
tx_1_ff[7:0] <= TX1_RST[7:0];
end
else if(we_tx_1[0]) // Write enable
begin
tx_1_ff[7:0] <= writedata[7:0] & TX1_PARAM[7:0];
end
else // Keep value
begin
tx_1_ff[7:0] <= tx_1_ff[7:0] & TX1_PARAM[7:0];
end
end // block: tx_1_7_0_register
// TX1 Register - byte 15-8
always @( negedge reset_n or posedge clk)
begin: tx_1_15_8_register
if(!reset_n) // reset
begin
tx_1_ff[15:8] <= TX1_RST[15:8];
end
else if(we_tx_1[1]) // Write enable
begin
tx_1_ff[15:8] <= writedata[15:8] & TX1_PARAM[15:8];
end
else // Keep value
begin
tx_1_ff[15:8] <= tx_1_ff[15:8] & TX1_PARAM[15:8];
end
end // block: tx_1_15_8_register
// TX1 Register - byte 23-16
always @( negedge reset_n or posedge clk)
begin: tx_1_23_16_register
if(!reset_n) // reset
begin
tx_1_ff[23:16] <= TX1_RST[23:16];
end
else if(we_tx_1[2]) // Write enable
begin
tx_1_ff[23:16] <= writedata[23:16] & TX1_PARAM[23:16];
end
else // Keep value
begin
tx_1_ff[23:16] <= tx_1_ff[23:16] & TX1_PARAM[23:16];
end
end // block: tx_1_23_16_register
// TX1 Register - byte 31-24
always @( negedge reset_n or posedge clk)
begin: tx_1_31_24_register
if(!reset_n) // reset
begin
tx_1_ff[31:24] <= TX1_RST[31:24];
end
else if(we_tx_1[3]) // Write enable
begin
tx_1_ff[31:24] <= writedata[31:24] & TX1_PARAM[31:24];
end
else // Keep value
begin
tx_1_ff[31:24] <= tx_1_ff[31:24] & TX1_PARAM[31:24];
end
end // block: tx_1_31_24_register
// Register output to optimize logic according to local parameters
// Reserved registers are optimized during synthesis
assign rx_0[31:0] = rx_0_ff[31:0] & RX0_PARAM[31:0];
assign rx_1[31:0] = rx_1_ff[31:0] & RX1_PARAM[31:0];
assign tx_0[31:0] = tx_0_ff[31:0] & TX0_PARAM[31:0];
assign tx_1[31:0] = tx_1_ff[31:0] & TX1_PARAM[31:0];
assign tx_bert_en = tx_1[8];
//------------------------------------------------------------------------------
// BERT access request register - Address offset = 0x20
//------------------------------------------------------------------------------
assign bert_acc_rq_sel = (address[7:0] == BERT_ACC_RQ_ADDR_OFF);
assign bert_acc_rq_wbyte_7_0 = bert_acc_rq_sel & write & byteenable[0];
assign bert_acc_rq_wbyte_23_16 = bert_acc_rq_sel & write & byteenable[2];
assign bert_acc_rq_wbyte_31_24 = bert_acc_rq_sel & write & byteenable[3];
assign bert_acc_addr[5:0] = {6{bert_acc_rq_wbyte_7_0}} & writedata[5:0];
assign bert_acc_req = bert_acc_rq_wbyte_31_24 & writedata[30];
assign bert_acc_rdwr = bert_acc_rq_wbyte_31_24 & writedata[29];
assign bert_acc_rq_rdata[31:0] = {bert_acc_rq_pend,31'h0};
//------------------------------------------------------------------------------
// BERT configuration input register - Address offset = 0x24
//------------------------------------------------------------------------------
assign bert_wdata_sel = (address[7:0] == BERT_WDATA_ADDR_OFF);
assign bert_wdata_wbyte_7_0 = bert_wdata_sel & write & byteenable[0];
assign bert_wdata_wbyte_15_8 = bert_wdata_sel & write & byteenable[1];
assign bert_wdata_wbyte_23_16 = bert_wdata_sel & write & byteenable[2];
assign bert_wdata_wbyte_31_24 = bert_wdata_sel & write & byteenable[3];
always @(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
bert_wdata_ff[7:0] <= 8'h0;
end
else if(!bert_acc_rq_pend && bert_wdata_wbyte_7_0)
begin
bert_wdata_ff[7:0] <= writedata[7:0];
end
end
always @(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
bert_wdata_ff[15:8] <= 8'h0;
end
else if(!bert_acc_rq_pend && bert_wdata_wbyte_15_8)
begin
bert_wdata_ff[15:8] <= writedata[15:8];
end
end
always @(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
bert_wdata_ff[23:16] <= 8'h0;
end
else if(!bert_acc_rq_pend && bert_wdata_wbyte_23_16)
begin
bert_wdata_ff[23:16] <= writedata[23:16];
end
end
always @(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
bert_wdata_ff[31:24] <= 8'h0;
end
else if(!bert_acc_rq_pend && bert_wdata_wbyte_31_24)
begin
bert_wdata_ff[31:24] <= writedata[31:24];
end
end
//------------------------------------------------------------------------------
// TX BERT control register - ADDR OFF = 0x28
//------------------------------------------------------------------------------
assign txbert_ctrl_sel = (address[7:0] == TXBERT_CTRL_ADDR_OFF);
assign txbert_ctrl_wbyte_7_0 = txbert_ctrl_sel & write & byteenable[0];
assign txbert_ctrl_wbyte_23_16 = txbert_ctrl_sel & write & byteenable[2];
assign tx_bert_rst[3:0] = writedata[3:0] & {4{txbert_ctrl_wbyte_7_0}};
assign tx_bert_start[3:0] = writedata[19:16] & {4{txbert_ctrl_wbyte_23_16}};
//------------------------------------------------------------------------------
// TX BERT status register - ADDR OFF = 0x2C
//------------------------------------------------------------------------------
assign txbert_st_rdata[31:0] = { bert_seed_good,
27'h0,
txbert_run_ff[3:0] };
//------------------------------------------------------------------------------
// RX BERT control register - ADDR OFF = 0x34
//------------------------------------------------------------------------------
assign rxbert_ctrl_sel = (address[7:0] == RXBERT_CTRL_ADDR_OFF);
assign rxbert_ctrl_wbyte_7_0 = rxbert_ctrl_sel & write & byteenable[0];
assign rxbert_ctrl_wbyte_23_16 = rxbert_ctrl_sel & write & byteenable[2];
assign rxbert_ctrl_wbyte_31_24 = rxbert_ctrl_sel & write & byteenable[3];
assign rxbert_rst[3:0] = writedata[3:0] & {4{rxbert_ctrl_wbyte_7_0}};
assign rxbert_start[3:0] = writedata[19:16] & {4{rxbert_ctrl_wbyte_23_16}};
assign rxbert_seed_in[3:0] = writedata[27:24] & {4{rxbert_ctrl_wbyte_31_24}};
//------------------------------------------------------------------------------
// RX BERT status register - ADDR OFF = 0x38
//------------------------------------------------------------------------------
// RX BERT status read data
assign rxbert_st_rdata[31:0] = { 12'h0,
rxbert_biterr_ff[3:0],
12'h0,
rxbert_run_ff[3:0] };
//------------------------------------------------------------------------------
// Register read logic
//------------------------------------------------------------------------------
// read process
always @ (*)
begin: rdata_comb_logic
rdata_comb = 32'h0;
if(read) // Read access
begin
case (address[7:0])
RX0_ADDR_OFF: rdata_comb [31:0] = rx_0[31:0];
RX1_ADDR_OFF: rdata_comb [31:0] = rx_1[31:0];
TX0_ADDR_OFF: rdata_comb [31:0] = tx_0[31:0];
TX1_ADDR_OFF: rdata_comb [31:0] = tx_1[31:0];
BERT_ACC_RQ_ADDR_OFF: rdata_comb [31:0] = bert_acc_rq_rdata[31:0];
BERT_WDATA_ADDR_OFF: rdata_comb [31:0] = bert_wdata_ff[31:0];
TXBERT_CTRL_ADDR_OFF: rdata_comb [31:0] = 32'h0;
TXBERT_ST_ADDR_OFF: rdata_comb [31:0] = txbert_st_rdata[31:0];
RXBERT_CTRL_ADDR_OFF: rdata_comb [31:0] = 32'h0;
RXBERT_ST_ADDR_OFF: rdata_comb [31:0] = rxbert_st_rdata[31:0];
RXBERT_RDATA0_ADDR_OFF: rdata_comb [31:0] = rx_bert_rdata_ff[31:0];
TXBERT_RDATA_ADDR_OFF: rdata_comb [31:0] = tx_bert_rdata_ff[31:0];
default : rdata_comb = 32'h00000000;
endcase
end
end // block: rdata_comb_logic
//------------------------------------------------------------------------------
// Tx Clock divider section logic
//------------------------------------------------------------------------------
aib_bit_sync tx_clock_div_ack_sync
(
.clk (clk), // Clock of destination domain
.rst_n (reset_n), // Reset of destination domain
.data_in (tx_clk_div_ld_ack), // Input to be synchronized
.data_out (tx_clk_div_ack_sync) // Synchronized output
);
assign txclk_div1_sel = (tx_0_ff[25:24] == 2'b01);
assign txclk_div2_sel = (tx_0_ff[25:24] == 2'b10);
assign txclk_div4_sel = (tx_0_ff[25:24] == 2'b11);
// Detects if CDC interface is busy
assign tx_div_if_busy = tx_clk_div_ld_ff ^ tx_clk_div_ack_sync;
assign txclk_div_update = (~tx_div_if_busy) &
( (txclk_div1_sel ^ tx_clk_div_1_ff) |
(txclk_div2_sel ^ tx_clk_div_2_ff) |
(txclk_div4_sel ^ tx_clk_div_4_ff) );
// Load register for TX clock divider selection
always @(posedge clk or negedge reset_n)
begin: tx_clk_div_ld_register
if(!reset_n)
tx_clk_div_ld_ff <= 1'b0;
else if(txclk_div_update) // Update selection
tx_clk_div_ld_ff <= ~tx_clk_div_ld_ff;
end // block: tx_clk_div_ld_register
// TX clock divided 1 selection register
always @(posedge clk or negedge reset_n)
begin: tx_clk_div_1_register
if(!reset_n)
tx_clk_div_1_ff <= 1'b0;
else if(txclk_div_update) // Update selection
tx_clk_div_1_ff <= txclk_div1_sel;
end // block: tx_clk_div_1_register
// TX clock divided 2 selection register
always @(posedge clk or negedge reset_n)
begin: tx_clk_div_2_register
if(!reset_n)
tx_clk_div_2_ff <= 1'b0;
else if(txclk_div_update) // Update selection
tx_clk_div_2_ff <= txclk_div2_sel;
end // block: tx_clk_div_2_register
// TX clock divided 4 selection register
always @(posedge clk or negedge reset_n)
begin: tx_clk_div_4_register
if(!reset_n)
tx_clk_div_4_ff <= 1'b0;
else if(txclk_div_update) // Update selection
tx_clk_div_4_ff <= txclk_div4_sel;
end // block: tx_clk_div_4_register
//------------------------------------------------------------------------------
// Rx Clock divider section logic
//------------------------------------------------------------------------------
aib_bit_sync rx_clock_div_ack_sync
(
.clk (clk), // Clock of destination domain
.rst_n (reset_n), // Reset of destination domain
.data_in (rx_clk_div_ld_ack), // Input to be synchronized
.data_out (rx_clk_div_ack_sync) // Synchronized output
);
assign rxclk_div1_sel = (rx_0_ff[3:2] == 2'b01);
assign rxclk_div2_sel = (rx_0_ff[3:2] == 2'b10);
assign rxclk_div4_sel = (rx_0_ff[3:2] == 2'b11);
// Detects if CDC interface is busy
assign rx_div_if_busy = rx_clk_div_ld_ff ^ rx_clk_div_ack_sync;
assign rxclk_div_update = (~rx_div_if_busy) &
( (rxclk_div1_sel ^ rx_clk_div_1_ff) |
(rxclk_div2_sel ^ rx_clk_div_2_ff) |
(rxclk_div4_sel ^ rx_clk_div_4_ff) );
// Load register for RX clock divider selection
always @(posedge clk or negedge reset_n)
begin: rx_clk_div_ld_register
if(!reset_n)
rx_clk_div_ld_ff <= 1'b0;
else if(rxclk_div_update) // Update selection
rx_clk_div_ld_ff <= ~rx_clk_div_ld_ff;
end // block: rx_clk_div_ld_register
// RX clock divided 1 selection register
always @(posedge clk or negedge reset_n)
begin: rx_clk_div_1_register
if(!reset_n)
rx_clk_div_1_ff <= 1'b0;
else if(rxclk_div_update) // Update selection
rx_clk_div_1_ff <= rxclk_div1_sel;
end // block: rx_clk_div_1_register
// RX clock divided 2 selection register
always @(posedge clk or negedge reset_n)
begin: rx_clk_div_2_register
if(!reset_n)
rx_clk_div_2_ff <= 1'b0;
else if(rxclk_div_update) // Update selection
rx_clk_div_2_ff <= rxclk_div2_sel;
end // block: tx_clk_div_2_register
// RX clock divided 4 selection register
always @(posedge clk or negedge reset_n)
begin: rx_clk_div_4_register
if(!reset_n)
rx_clk_div_4_ff <= 1'b0;
else if(rxclk_div_update) // Update selection
rx_clk_div_4_ff <= rxclk_div4_sel;
end // block: rx_clk_div_4_register
endmodule // aib_avalon_adapt_reg |
module aib_avalon (
// Avalon access signals
input [5:0] cfg_avmm_addr_id, // Index of channel based on MSBs of address
input cfg_avmm_clk, // Access clock
input cfg_avmm_rst_n, // Avalon interface async reset
input cfg_avmm_write, // Write enable
input cfg_avmm_read, // Read enable
input [16:0] cfg_avmm_addr, // Address bus
input [31:0] cfg_avmm_wdata, // Write data bus
input [3:0] cfg_avmm_byte_en, // Bytes enable
output [31:0] cfg_avmm_rdata, // Read data bus
output cfg_avmm_rdatavld, // Indicates read data is valid
output cfg_avmm_waitreq, // Forces host to hold access control signals
//Adapt control CSR
output [31:0] rx_adapt_0, // RX0 adapter register
output [31:0] rx_adapt_1, // RX1 adapter register
output [31:0] tx_adapt_0, // TX0 adapter register
output [31:0] tx_adapt_1, // TX1 adapter register
// BERT access interface
output [ 5:0] bert_acc_addr, // BERT access address
output bert_acc_req, // BERT access request
output bert_acc_rdwr, // BERT access read/write control
output [31:0] bert_wdata_ff, // BERT data to be written
input [31:0] rx_bert_rdata_ff, // Read data from RX BERT interface
input [31:0] tx_bert_rdata_ff, // Read data from TX BERT interface
input bert_acc_rq_pend, // BERT configuration load is pending
// TX BERT control interface
output [3:0] tx_bert_start, // Starts transmitting TX BERT bit sequence
output [3:0] tx_bert_rst, // Resets TX BERT registers
// TX BERT status interface
input bert_seed_good, // Indicates all BPRS seeds are not zero.
input [3:0] txbert_run_ff, // Indicates TX BERT is running
// RX BERT control interface
output [3:0] rxbert_start, // Starts checking input of RX BERT bit sequence
output [3:0] rxbert_rst, // Resets RX BERT registers
output [3:0] rxbert_seed_in, // Enables the self-seeding in RX BERT
// RX BERT status interface
input [ 3:0] rxbert_run_ff, // Indicates RX BERT is running
input [ 3:0] rxbert_biterr_ff, // Error detected in RX BERT checker
// BERT enable
output tx_bert_en, // TX BERT enable
//AIB IO control CSR
output [31:0] redund_0, // Redundancy IO register 0
output [31:0] redund_1, // Redundancy IO register 1
output [31:0] redund_2, // Redundancy IO register 2
output [31:0] redund_3, // Redundancy IO register 3
// AIBIO common registers
output [ 2:0] iocmn_pll_freq,
output iocmn_tx_lpbk_en,
output iocmn_rx_lpbk_en,
output iocmn_en_digmon,
output [15:0] iocmn_digmon_sel_code,
output iocmn_en_anamon,
output [ 2:0] iocmn_anamon_sel_code,
output [1:0] dll_sel_avg_ff,
// AIBIO TX/RX registers
output [7:0] iotxrx_tx_drvnpd_code,
output [7:0] iotxrx_tx_drvnpu_code,
output [7:0] iotxrx_tx_drvppu_code,
output io_ctrl1_tx_wkpu_ff,
output io_ctrl1_tx_wkpd_ff,
output io_ctrl1_rx_wkpu_ff,
output io_ctrl1_rx_wkpd_ff,
output [3:0] iotxrx_tx_deskew_ff,
output [3:0] iotxrx_rx_deskew_ff,
output iotxrx_tx_deskew_en_ff,
output iotxrx_tx_deskew_step_ff,
output iotxrx_tx_deskew_ovrd_ff,
output iotxrx_rx_deskew_en_ff,
output iotxrx_rx_deskew_step_ff,
output iotxrx_rx_deskew_ovrd_ff,
// AIBIO VREF registers
output [6:0] vref_p_code_gen1,
output [6:0] vref_n_code_gen1,
output [6:0] vref_p_code_gen2,
output [6:0] vref_n_code_gen2,
output [4:0] vref_calvref_code,
output vref_calcode_ovrd_ff,
output vref_caldone_ovrd_ff,
input vref_cal_done_sync,
// AIBIO RX DLL
output [1:0] rdll_dll_inclk_sel,
output [3:0] rdll_dll_lockthresh_code,
output [1:0] rdll_dll_lockctrl_code,
output [2:0] rdll_cdrctrl_code,
output rdll_ovrd_pi_adpclk_code,
output rddl_adp_lock_ovrd_ff,
output rddl_soc_lock_ovrd_ff,
output [3:0] rdll_pi_adpclk_code,
output rdll_ovrd_pi_socclk_code,
output [3:0] rdll_pi_socclk_code,
output [4:0] rdll_digview_sel,
output cdr_picode_update,
output [6:0] cdr_picode_even_ff,
output [6:0] cdr_picode_odd_ff,
output cdr_ovrd_sel_ff,
output cdr_lock_ovrd_ff,
output [1:0] cdr_clk_sel_ff,
input rx_adp_clk_lock,
input rx_soc_clk_lock,
input [3:0] rx_adp_clkph_code,
input [3:0] rx_soc_clkph_code,
// AIBIO CDR
input aibio_cdr_lock,
// AIBIO TXDLL
output [1:0] tdll_dll_inclk_sel,
output [3:0] tdll_dll_lockthresh_code,
output [1:0] tdll_dll_lockctrl_code,
output tdll_ovrd_pi_adpclk_code,
output tddl_adp_lock_ovrd_ff,
output tddl_soc_lock_ovrd_ff,
output [3:0] tdll_pi_adpclk_code,
output tdll_ovrd_pi_socclk_code,
output [3:0] tdll_pi_socclk_code,
output [4:0] tdll_digview_sel,
input tx_adp_clk_lock,
input tx_soc_clk_lock,
input [3:0] tx_adp_clkph_code,
input [3:0] tx_soc_clkph_code,
// AIBIO RXCLK CBB
output [2:0] iorclk_dcc_bias_code,
output [2:0] iorclk_ibias_ctrl_nored,
output [2:0] iorclk_ibias_ctrl_red,
input rx_dcc_lock,
// AIBIO DCS CBB
output [1:0] dcs1_clkdiv_sel,
output dcs1_sel_clkp,
output dcs1_sel_clkn,
output dcs1_en_single_ended,
output dcs1_sel_ovrd_ff,
output dcs1_lock_ovrd_ff,
output dcs1_chopen_ovrd_ff,
output [4:0] dcs2_npusel_code_ff,
output [4:0] dcs2_npdsel_code_ff,
output [4:0] dcs2_ppusel_code_ff,
output [4:0] dcs2_ppdsel_code_ff,
input dcs1_lock,
// AIBIO RCOMP1 register
output rcomp_calsel_g2_ovrd_ff,
output rcomp_calcode_g2_ovrd_ff,
output [6:0] rcomp_calcode_g2_ff,
output rcomp_calsel_g1_ovrd_ff,
output rcomp_calcode_g1_ovrd_ff,
output [6:0] rcomp_calcode_g1_ff,
input rcomp_cal_done_g2_sync,
input rcomp_cal_done_g1_sync,
// AIBIO RCOMP2 register
input [6:0] rcomp_calcode_g2,
input [6:0] rcomp_calcode_g1,
// AIBIO NTL register
output [15:0] ntl2_count_ff,
output ntl1_done_ovrd_ff,
output ntl1_tx_dodd_ovrd_ff,
output ntl1_tx_deven_ovrd_ff,
output ntl1_rxen_ovrd_ff,
output ntl1_txen_ovrd_ff,
output ntl1_en_ovrd_ff,
output ntl1_en_ff,
output [ 6:0] ntl1_pad_num_ff,
output ntl1_txen_async_ovrd_ff,
output ntl1_rxen_async_ovrd_ff,
input ntl1_done_sync,
input [15:0] ntl2_cnt_val_sync,
// AIB adapter clock divider interface
output tx_clk_div_ld_ff, // Loads Tx clock divider selection
output tx_clk_div_1_ff, // Tx Clock divided by 1 selection
output tx_clk_div_2_ff, // Tx Clock divided by 2 selection
output tx_clk_div_4_ff, // Tx Clock divided by 4 selection
output rx_clk_div_ld_ff, // Loads Rx clock divider selection
output rx_clk_div_1_ff, // Rx Clock divided by 1 selection
output rx_clk_div_2_ff, // Rx Clock divided by 2 selection
output rx_clk_div_4_ff, // Rx Clock divided by 4 selection
input tx_clk_div_ld_ack, // TX clock divider load ack
input rx_clk_div_ld_ack, // RX clock divider load ack
// Analog Interface Clock dividers control signals
output rxoff_cal_div_ld_ff, // Loads RXOFF Cal divider selection
output rxoff_cal_div_1_ff, // RXOFF Cal clock divided by 1
output rxoff_cal_div_2_ff, // RXOFF Cal clock divided by 2
output rxoff_cal_div_4_ff, // RXOFF Cal clock divided by 4
output rxoff_cal_div_8_ff, // RXOFF Cal clock divided by 8
output rxoff_cal_div_16_ff, // RXOFF Cal clock divided by 16
output rxoff_cal_div_32_ff, // RXOFF Cal clock divided by 32
output rxoff_cal_div_64_ff, // RXOFF Cal clock divided by 64
output sysclk_div_ld_ff, // SYS clock divider selection
output sysclk_div_1_ff, // SYS clock divided by 1
output sysclk_div_2_ff, // SYS clock divided by 2
output sysclk_div_4_ff, // SYS clock divided by 4
output sysclk_div_8_ff, // SYS clock divided by 8
output sysclk_div_16_ff, // SYS clock divided by 16
output gen1rcomp_div_ld_ff, // GEN1 RCOMP divider selection
output gen1rcomp_div_1_ff, // GEN1 RCOMP clock divided by 1
output gen1rcomp_div_2_ff, // GEN1 RCOMP clock divided by 2
output gen1rcomp_div_4_ff, // GEN1 RCOMP clock divided by 4
output gen1rcomp_div_8_ff, // GEN1 RCOMP clock divided by 8
output gen1rcomp_div_16_ff, // GEN1 RCOMP clock divided by 16
output gen1rcomp_div_32_ff, // GEN1 RCOMP clock divided by 32
output gen2rcomp_div_ld_ff, // GEN2 RCOMP divider selection
output gen2rcomp_div_1_ff, // GEN2 RCOMP clock divided by 1
output gen2rcomp_div_2_ff, // GEN2 RCOMP clock divided by 2
output gen2rcomp_div_4_ff, // GEN2 RCOMP clock divided by 4
output gen2rcomp_div_8_ff, // GEN2 RCOMP clock divided by 8
output gen2rcomp_div_16_ff, // GEN2 RCOMP clock divided by 16
output gen2rcomp_div_32_ff, // GEN2 RCOMP clock divided by 32
output dcs_div_ld_ff, // DCS divider selection
output dcs_div_1_ff, // DCS clock divided by 1
output dcs_div_2_ff, // DCS clock divided by 2
output dcs_div_4_ff, // DCS clock divided by 4
output dcs_div_8_ff, // DCS clock divided by 8
output dcs_div_16_ff, // DCS clock divided by 16
output dcs_div_32_ff, // DCS clock divided by 32
output dcs_div_64_ff, // DCS clock divided by 32
output dcs_div_128_ff, // DCS clock divided by 32
output dcs_div_256_ff, // DCS clock divided by 32
input rxoff_cal_div_ld_ack, // RXOFF Cal divider load ack
input sysclk_div_ld_ack, // SYS clock divider load ack
input gen1rcomp_div_ld_ack, // GEN1 RCOMP clock divider load ack
input gen2rcomp_div_ld_ack, // GEN2 RCOMP clock divider load ack
input dcs_div_ld_ack, // dcs clock divider load ack
input atpg_mode // ATPG mode
);
wire cfg_csr_clk; // CSR clock
wire cfg_csr_reset; // CSR reset
wire cfg_csr_read; // CSR read enable
wire cfg_csr_write; // CSR write enable
wire [31:0] cfg_csr_wdata; // CSR write data bus
wire [31:0] cfg_csr_rdata; // CSR read data bus
wire [7:0] cfg_csr_addr; // CSR address bus
wire [3:0] cfg_csr_byteen; // CSR byte enables
wire cfg_adapt_addr_match; // Address is in adapter range
wire cfg_io_addr_match; // Address is in IO analog range
wire [31:0] cfg_adapt_rdata; // Adapt read data bus
wire [31:0] cfg_io_rdata; // IO analog read bus
wire cfg_only_id_match;
wire cfg_only_addr_match;
wire cfg_only_write ;
wire cfg_only_read;
// Base addresses
localparam AIB_BASE_BOT = 11'h200;
localparam AIB_BASE_MID = 11'h300;
localparam AIB_BASE_TOP = 11'h400;
// Configuration registers for Adapter and AIBIO
assign cfg_only_id_match = (cfg_avmm_addr_id[5:0] == cfg_avmm_addr[16:11]);
assign cfg_only_addr_match =
(cfg_avmm_addr[10:0] >= AIB_BASE_BOT) &
(cfg_avmm_addr[10:0] < AIB_BASE_TOP) &
cfg_only_id_match;
assign cfg_adapt_addr_match = (cfg_avmm_addr[10:0] >= AIB_BASE_BOT) &
(cfg_avmm_addr[10:0] < AIB_BASE_MID);
assign cfg_io_addr_match = (cfg_avmm_addr[10:0] >= AIB_BASE_MID) &
(cfg_avmm_addr[10:0] < AIB_BASE_TOP);
assign cfg_only_write = cfg_only_addr_match & cfg_avmm_write;
assign cfg_only_read = cfg_only_addr_match & cfg_avmm_read;
assign cfg_csr_rdata = cfg_adapt_rdata | cfg_io_rdata;
aib_avalon_if #( .AVMM_ADDR_WIDTH(8), .RDL_ADDR_WIDTH (8))
adapt_cfg_rdl_intf (
.avmm_clk (cfg_avmm_clk), // AVMM Slave interface
.avmm_rst_n (cfg_avmm_rst_n), // input logic
.i_avmm_write (cfg_only_write), // input logic
.i_avmm_read (cfg_only_read), // input logic
.i_avmm_addr (cfg_avmm_addr[7:0]), // input logic
.i_avmm_wdata (cfg_avmm_wdata), // input logic [31:0]
.i_avmm_byte_en (cfg_avmm_byte_en), // input logic [3:0]
.o_avmm_rdata (cfg_avmm_rdata), // output logic [31:0]
.o_avmm_rdatavalid (cfg_avmm_rdatavld), // output logic
.o_avmm_waitrequest (cfg_avmm_waitreq), // output logic
.clk (cfg_csr_clk), // RDL-generated memory map interface
.reset (cfg_csr_reset), // output logic
.writedata (cfg_csr_wdata), // output logic [31:0]
.read (cfg_csr_read), // output logic
.write (cfg_csr_write), // output logic
.byteenable (cfg_csr_byteen), // output logic [3:0]
.readdata (cfg_csr_rdata), // input logic [31:0]
.address (cfg_csr_addr) // output logic [RDL_ADDR_WIDTH-1:0]
);
aib_avalon_adapt_reg adapt_csr (
.rx_0(rx_adapt_0),
.rx_1(rx_adapt_1),
.tx_0(tx_adapt_0),
.tx_1(tx_adapt_1),
//----------------------------------
// BERT access interface
//----------------------------------
.bert_acc_addr (bert_acc_addr[5:0]), // BERT access address
.bert_acc_req (bert_acc_req), // BERT access request
.bert_acc_rdwr (bert_acc_rdwr), // BERT access read/write control
.bert_wdata_ff (bert_wdata_ff[31:0]), // BERT data to be written
.rx_bert_rdata_ff (rx_bert_rdata_ff[31:0]), // Read data from RX BERT interface
.tx_bert_rdata_ff (tx_bert_rdata_ff[31:0]), // Read data from TX BERT interface
.bert_acc_rq_pend (bert_acc_rq_pend), // BERT configuration load is pending
//-----------------------------------
// TX BERT control interface
//-----------------------------------
.tx_bert_start (tx_bert_start[3:0]), // Starts transmitting TX BERT bit sequence
.tx_bert_rst (tx_bert_rst[3:0]), // Resets TX BERT registers
//-----------------------------------
// TX BERT status interface
//-----------------------------------
.bert_seed_good (bert_seed_good), // Indicates no zero BPRS seeds.
.txbert_run_ff (txbert_run_ff[3:0]), // Indicates TX BERT is running
//------------------------------------
// RX BERT control interface
//------------------------------------
.rxbert_start (rxbert_start[3:0]), // Starts checking RX BERT bit sequence
.rxbert_rst (rxbert_rst[3:0]), // Resets RX BERT registers
.rxbert_seed_in (rxbert_seed_in[3:0]), // Enables the self-seeding in RX BERT
//------------------------------------
// RX BERT status interface
//------------------------------------
.rxbert_run_ff (rxbert_run_ff[3:0]), // Indicates RX BERT is running
.rxbert_biterr_ff (rxbert_biterr_ff[3:0]), // Error detected in RX BERT check.
// BERT enable
.tx_bert_en (tx_bert_en), // TX BERT enable
//--------------------------------------
.clk(cfg_csr_clk),
.reset(cfg_csr_reset),
.writedata(cfg_csr_wdata),
.read((cfg_csr_read & cfg_adapt_addr_match)),
.write((cfg_csr_write &cfg_adapt_addr_match)),
.byteenable(cfg_csr_byteen),
.readdata(cfg_adapt_rdata),
.address(cfg_csr_addr[7:0]),
// Tx clock divider
.tx_clk_div_ld_ff (tx_clk_div_ld_ff),
.tx_clk_div_ld_ack (tx_clk_div_ld_ack),
.tx_clk_div_1_ff (tx_clk_div_1_ff),
.tx_clk_div_2_ff (tx_clk_div_2_ff),
.tx_clk_div_4_ff (tx_clk_div_4_ff),
// Rx clock divider
.rx_clk_div_ld_ff (rx_clk_div_ld_ff),
.rx_clk_div_ld_ack (rx_clk_div_ld_ack),
.rx_clk_div_1_ff (rx_clk_div_1_ff),
.rx_clk_div_2_ff (rx_clk_div_2_ff),
.rx_clk_div_4_ff (rx_clk_div_4_ff)
);
aib_avalon_io_regs io_csr (
.redund_0(redund_0),
.redund_1(redund_1),
.redund_2(redund_2),
.redund_3(redund_3),
// AIBIO common registers
//Outputs
.iocmn_pll_freq (iocmn_pll_freq[2:0]),
.iocmn_tx_lpbk_en (iocmn_tx_lpbk_en),
.iocmn_rx_lpbk_en (iocmn_rx_lpbk_en),
.iocmn_en_digmon (iocmn_en_digmon),
.iocmn_digmon_sel_code (iocmn_digmon_sel_code[15:0]),
.iocmn_en_anamon (iocmn_en_anamon),
.iocmn_anamon_sel_code (iocmn_anamon_sel_code[2:0]),
.dll_sel_avg_ff (dll_sel_avg_ff[1:0]),
// AIBIO TX/RX registers
//Outputs
.iotxrx_tx_drvnpd_code (iotxrx_tx_drvnpd_code[7:0]),
.iotxrx_tx_drvnpu_code (iotxrx_tx_drvnpu_code[7:0]),
.iotxrx_tx_drvppu_code (iotxrx_tx_drvppu_code[7:0]),
.io_ctrl1_tx_wkpu_ff (io_ctrl1_tx_wkpu_ff),
.io_ctrl1_tx_wkpd_ff (io_ctrl1_tx_wkpd_ff),
.io_ctrl1_rx_wkpu_ff (io_ctrl1_rx_wkpu_ff),
.io_ctrl1_rx_wkpd_ff (io_ctrl1_rx_wkpd_ff),
.iotxrx_tx_deskew_ff (iotxrx_tx_deskew_ff[3:0]),
.iotxrx_rx_deskew_ff (iotxrx_rx_deskew_ff[3:0]),
.iotxrx_tx_deskew_en_ff (iotxrx_tx_deskew_en_ff),
.iotxrx_tx_deskew_step_ff (iotxrx_tx_deskew_step_ff),
.iotxrx_tx_deskew_ovrd_ff (iotxrx_tx_deskew_ovrd_ff),
.iotxrx_rx_deskew_en_ff (iotxrx_rx_deskew_en_ff),
.iotxrx_rx_deskew_step_ff (iotxrx_rx_deskew_step_ff),
.iotxrx_rx_deskew_ovrd_ff (iotxrx_rx_deskew_ovrd_ff),
// AIBIO VREF registers
//Outputs
.vref_p_code_gen1 (vref_p_code_gen1[6:0]),
.vref_n_code_gen1 (vref_n_code_gen1[6:0]),
.vref_p_code_gen2 (vref_p_code_gen2[6:0]),
.vref_n_code_gen2 (vref_n_code_gen2[6:0]),
.vref_calvref_code (vref_calvref_code[4:0]),
.vref_calcode_ovrd_ff (vref_calcode_ovrd_ff),
.vref_caldone_ovrd_ff (vref_caldone_ovrd_ff),
// Inputs
.vref_cal_done_sync (vref_cal_done_sync),
// AIBIO RX DLL
//Outputs
.rdll_dll_inclk_sel (rdll_dll_inclk_sel[1:0]),
.rdll_dll_lockthresh_code (rdll_dll_lockthresh_code[3:0]),
.rdll_dll_lockctrl_code (rdll_dll_lockctrl_code[1:0]),
.rdll_cdrctrl_code (rdll_cdrctrl_code[2:0]),
.rdll_ovrd_pi_adpclk_code (rdll_ovrd_pi_adpclk_code),
.rddl_adp_lock_ovrd_ff (rddl_adp_lock_ovrd_ff),
.rddl_soc_lock_ovrd_ff (rddl_soc_lock_ovrd_ff),
.rdll_pi_adpclk_code (rdll_pi_adpclk_code[3:0]),
.rdll_ovrd_pi_socclk_code (rdll_ovrd_pi_socclk_code),
.rdll_pi_socclk_code (rdll_pi_socclk_code[3:0]),
.rdll_digview_sel (rdll_digview_sel[4:0]),
.cdr_picode_update (cdr_picode_update),
.cdr_picode_even_ff (cdr_picode_even_ff[6:0]),
.cdr_picode_odd_ff (cdr_picode_odd_ff[6:0]),
.cdr_ovrd_sel_ff (cdr_ovrd_sel_ff),
.cdr_lock_ovrd_ff (cdr_lock_ovrd_ff),
.cdr_clk_sel_ff (cdr_clk_sel_ff[1:0]),
// Inputs
.rx_adp_clk_lock (rx_adp_clk_lock),
.rx_soc_clk_lock (rx_soc_clk_lock),
.rx_adp_clkph_code (rx_adp_clkph_code[3:0]),
.rx_soc_clkph_code (rx_soc_clkph_code[3:0]),
// AIBIO CDR
// Inputs
.aibio_cdr_lock (aibio_cdr_lock),
// AIBIO TXDLL
// Outputs
.tdll_dll_inclk_sel (tdll_dll_inclk_sel[1:0]),
.tdll_dll_lockthresh_code (tdll_dll_lockthresh_code[3:0]),
.tdll_dll_lockctrl_code (tdll_dll_lockctrl_code[1:0]),
.tdll_ovrd_pi_adpclk_code (tdll_ovrd_pi_adpclk_code),
.tddl_adp_lock_ovrd_ff (tddl_adp_lock_ovrd_ff),
.tddl_soc_lock_ovrd_ff (tddl_soc_lock_ovrd_ff),
.tdll_pi_adpclk_code (tdll_pi_adpclk_code[3:0]),
.tdll_ovrd_pi_socclk_code (tdll_ovrd_pi_socclk_code),
.tdll_pi_socclk_code (tdll_pi_socclk_code[3:0]),
.tdll_digview_sel (tdll_digview_sel[4:0]),
// Inputs
.tx_adp_clk_lock (tx_adp_clk_lock),
.tx_soc_clk_lock (tx_soc_clk_lock),
.tx_adp_clkph_code (tx_adp_clkph_code[3:0]),
.tx_soc_clkph_code (tx_soc_clkph_code[3:0]),
// AIBIO RXCLK CBB
// Outputs
.iorclk_dcc_bias_code (iorclk_dcc_bias_code[2:0]),
.iorclk_ibias_ctrl_nored (iorclk_ibias_ctrl_nored[2:0]),
.iorclk_ibias_ctrl_red (iorclk_ibias_ctrl_red[2:0]),
// Inputs
.rx_dcc_lock (rx_dcc_lock),
// AIBIO DCS CBB
// Outputs
.dcs1_clkdiv_sel (dcs1_clkdiv_sel[1:0]),
.dcs1_sel_clkp (dcs1_sel_clkp),
.dcs1_sel_clkn (dcs1_sel_clkn),
.dcs1_en_single_ended (dcs1_en_single_ended),
.dcs1_sel_ovrd_ff (dcs1_sel_ovrd_ff),
.dcs1_lock_ovrd_ff (dcs1_lock_ovrd_ff),
.dcs1_chopen_ovrd_ff (dcs1_chopen_ovrd_ff),
.dcs2_npusel_code_ff (dcs2_npusel_code_ff[4:0]),
.dcs2_npdsel_code_ff (dcs2_npdsel_code_ff[4:0]),
.dcs2_ppusel_code_ff (dcs2_ppusel_code_ff[4:0]),
.dcs2_ppdsel_code_ff (dcs2_ppdsel_code_ff[4:0]),
// Inputs
.dcs1_lock (dcs1_lock),
// RCOMP register
// outputs
.rcomp_calsel_g2_ovrd_ff (rcomp_calsel_g2_ovrd_ff),
.rcomp_calcode_g2_ovrd_ff (rcomp_calcode_g2_ovrd_ff),
.rcomp_calcode_g2_ff (rcomp_calcode_g2_ff[6:0]),
.rcomp_calsel_g1_ovrd_ff (rcomp_calsel_g1_ovrd_ff),
.rcomp_calcode_g1_ovrd_ff (rcomp_calcode_g1_ovrd_ff),
.rcomp_calcode_g1_ff (rcomp_calcode_g1_ff[6:0]),
// inputs
.rcomp_cal_done_g2_sync (rcomp_cal_done_g2_sync),
.rcomp_cal_done_g1_sync (rcomp_cal_done_g1_sync),
// RCOMP2 register
//Inputs
.rcomp_calcode_g2 (rcomp_calcode_g2),
.rcomp_calcode_g1 (rcomp_calcode_g1),
// AIBIO NTL register
// outputs
.ntl2_count_ff (ntl2_count_ff[15:0]),
.ntl1_done_ovrd_ff (ntl1_done_ovrd_ff),
.ntl1_tx_dodd_ovrd_ff (ntl1_tx_dodd_ovrd_ff),
.ntl1_tx_deven_ovrd_ff (ntl1_tx_deven_ovrd_ff),
.ntl1_rxen_ovrd_ff (ntl1_rxen_ovrd_ff),
.ntl1_txen_ovrd_ff (ntl1_txen_ovrd_ff),
.ntl1_en_ovrd_ff (ntl1_en_ovrd_ff),
.ntl1_en_ff (ntl1_en_ff),
.ntl1_pad_num_ff (ntl1_pad_num_ff[6:0]),
.ntl1_txen_async_ovrd_ff (ntl1_txen_async_ovrd_ff),
.ntl1_rxen_async_ovrd_ff (ntl1_rxen_async_ovrd_ff),
// inputs
.ntl1_done_sync (ntl1_done_sync),
.ntl2_cnt_val_sync (ntl2_cnt_val_sync[15:0]),
// Clock dividers control signals
// Outputs
.rxoff_cal_div_ld_ff (rxoff_cal_div_ld_ff),
.rxoff_cal_div_1_ff (rxoff_cal_div_1_ff),
.rxoff_cal_div_2_ff (rxoff_cal_div_2_ff),
.rxoff_cal_div_4_ff (rxoff_cal_div_4_ff),
.rxoff_cal_div_8_ff (rxoff_cal_div_8_ff),
.rxoff_cal_div_16_ff (rxoff_cal_div_16_ff),
.rxoff_cal_div_32_ff (rxoff_cal_div_32_ff),
.rxoff_cal_div_64_ff (rxoff_cal_div_64_ff),
.sysclk_div_ld_ff (sysclk_div_ld_ff),
.sysclk_div_1_ff (sysclk_div_1_ff),
.sysclk_div_2_ff (sysclk_div_2_ff),
.sysclk_div_4_ff (sysclk_div_4_ff),
.sysclk_div_8_ff (sysclk_div_8_ff),
.sysclk_div_16_ff (sysclk_div_16_ff),
.gen1rcomp_div_ld_ff (gen1rcomp_div_ld_ff),
.gen1rcomp_div_1_ff (gen1rcomp_div_1_ff),
.gen1rcomp_div_2_ff (gen1rcomp_div_2_ff),
.gen1rcomp_div_4_ff (gen1rcomp_div_4_ff),
.gen1rcomp_div_8_ff (gen1rcomp_div_8_ff),
.gen1rcomp_div_16_ff (gen1rcomp_div_16_ff),
.gen1rcomp_div_32_ff (gen1rcomp_div_32_ff),
.gen2rcomp_div_ld_ff (gen2rcomp_div_ld_ff),
.gen2rcomp_div_1_ff (gen2rcomp_div_1_ff),
.gen2rcomp_div_2_ff (gen2rcomp_div_2_ff),
.gen2rcomp_div_4_ff (gen2rcomp_div_4_ff),
.gen2rcomp_div_8_ff (gen2rcomp_div_8_ff),
.gen2rcomp_div_16_ff (gen2rcomp_div_16_ff),
.gen2rcomp_div_32_ff (gen2rcomp_div_32_ff),
.dcs_div_ld_ff (dcs_div_ld_ff),
.dcs_div_1_ff (dcs_div_1_ff),
.dcs_div_2_ff (dcs_div_2_ff),
.dcs_div_4_ff (dcs_div_4_ff),
.dcs_div_8_ff (dcs_div_8_ff),
.dcs_div_16_ff (dcs_div_16_ff),
.dcs_div_32_ff (dcs_div_32_ff),
.dcs_div_64_ff (dcs_div_64_ff),
.dcs_div_128_ff (dcs_div_128_ff),
.dcs_div_256_ff (dcs_div_256_ff),
// Inputs
.rxoff_cal_div_ld_ack (rxoff_cal_div_ld_ack),
.sysclk_div_ld_ack (sysclk_div_ld_ack),
.gen1rcomp_div_ld_ack (gen1rcomp_div_ld_ack),
.gen2rcomp_div_ld_ack (gen2rcomp_div_ld_ack),
.dcs_div_ld_ack (dcs_div_ld_ack),
// Other signals
.clk(cfg_csr_clk),
.reset(cfg_csr_reset),
.writedata(cfg_csr_wdata),
.read((cfg_csr_read & cfg_io_addr_match)),
.write((cfg_csr_write & cfg_io_addr_match)),
.byteenable(cfg_csr_byteen),
.readdata(cfg_io_rdata),
.address(cfg_csr_addr[7:0]),
.atpg_mode (atpg_mode) // ATPG mode
);
endmodule // aib_avalon |
module aib_sr_slave #(
parameter SL_LENGTH = 7'd73
)
(
input sr_sl_clk_in, //From input
output sr_sl_clk_out, //to output
input [SL_LENGTH-1:0] sl_data_fr_core, //Data from Core
output wire [SL_LENGTH-1:0] sl_data_to_core, //Data to Core
output reg sr_sl_data_out, //slave serial data out
output reg sr_sl_load_out, //slave load out
input sr_sl_data_in, //slave serial data out
input sr_sl_load_in, //slave serial data load inupt
input sr_ms_clk_in, //input ms clock
input osc_fsm_sl_rstn // Indicates the configuration is done.
);
localparam [SL_LENGTH-1:0] MS_BUS_RST_VAL = { 1'b0, // sl_osc_transfer_en,
1'b0,
1'b0, // sl_rx_transfer_en_s,
1'b0, // sl_rx_dcc_dll_lock_req,
1'b0, // sl_rx_dll_lock,
3'b0,
1'b0, // sl_tx_transfer_en_s,
1'b0, // sl_tx_dcc_dll_lock_req,
1'b0,
1'b0,
1'b1,
1'b0,
1'b1,
26'b0, // sl_external_cntl_57_32[25:0],
1'b0, // sl_tx_dcc_cal_done,
3'b0, // sl_external_cntl_30_28[2:0],
1'b0,
27'b0 }; // sl_external_cntl_26_0[26:0]
reg [6:0] sl_count;
reg sl_load;
reg [SL_LENGTH-1:0] sl_data_syncr; //master shift output register
reg [SL_LENGTH-1:0] sl_data_revr; //shift receive register
reg [SL_LENGTH-1:0] sl_data_capr; //captured master serial data register
reg sl_shift_en;
wire [SL_LENGTH-1:0] sl_data_sync, sl_data_syncrw, sl_data_revrw, sl_data_caprw;
wire sr_sl_data_outw; //slave serial data out
wire sr_sl_load_outw; //slave load out
assign sl_data_to_core[SL_LENGTH-1:0] = sl_data_capr[SL_LENGTH-1:0];
assign sr_sl_clk_out = sr_ms_clk_in;
aib_bit_sync #(
.DWIDTH (SL_LENGTH),
.RESET_VAL (MS_BUS_RST_VAL)
)
i_ms_data_sync(
.clk (sr_sl_clk_out),
.rst_n (osc_fsm_sl_rstn),
.data_in (sl_data_fr_core[SL_LENGTH-1:0]),
.data_out(sl_data_sync[SL_LENGTH-1:0])
);
always @(posedge sr_sl_clk_out or negedge osc_fsm_sl_rstn) begin
if (!osc_fsm_sl_rstn)
begin
sl_count[6:0] <= 7'h0;
sl_load <= 1'b0;
sl_shift_en <= 1'b0;
end
else
begin
if (sl_count[6:0]==(SL_LENGTH))
begin
sl_count[6:0] <= 7'h0;
sl_load <= 1'b1;
sl_shift_en <= 1'b0;
end
else
begin // increment counter
sl_count[6:0] <= sl_count[6:0] + 7'h01;
sl_load <= 1'b0;
sl_shift_en <= 1'b1;
end
end
end
assign sr_sl_data_outw = sl_data_syncr[SL_LENGTH-1];
assign sr_sl_load_outw = sl_load;
assign sl_data_syncrw[SL_LENGTH-1:0] = sl_load ? sl_data_sync[SL_LENGTH-1:0] :
sl_shift_en ? {sl_data_syncr[SL_LENGTH-2:0], sl_data_syncr[0]} : sl_data_syncr[SL_LENGTH-1:0];
always @(negedge sr_sl_clk_out or negedge osc_fsm_sl_rstn) begin
if (!osc_fsm_sl_rstn)
begin
sr_sl_data_out <= 1'b0;
sr_sl_load_out <= 1'b0;
end
else
begin
sr_sl_data_out <= sr_sl_data_outw;
sr_sl_load_out <= sr_sl_load_outw;
end
end
always @(posedge sr_sl_clk_out or negedge osc_fsm_sl_rstn) begin
if (!osc_fsm_sl_rstn)
begin
sl_data_syncr[SL_LENGTH-1:0] <= 73'h0;
end
else
begin
sl_data_syncr[SL_LENGTH-1:0] <= sl_data_syncrw[SL_LENGTH-1:0];
end
end
assign sl_data_revrw[SL_LENGTH-1:0] = sr_sl_load_in ? sl_data_revr[SL_LENGTH-1:0] : {sl_data_revr[SL_LENGTH-2:0], sr_sl_data_in};
assign sl_data_caprw[SL_LENGTH-1:0] = sr_sl_load_in ? sl_data_revr[SL_LENGTH-1:0] : sl_data_capr[SL_LENGTH-1:0];
always @(posedge sr_sl_clk_in or negedge osc_fsm_sl_rstn) begin
if (!osc_fsm_sl_rstn)
begin
sl_data_revr[SL_LENGTH-1:0] <= 73'h0;
sl_data_capr[SL_LENGTH-1:0] <= 73'h0;
end
else
begin
sl_data_revr[SL_LENGTH-1:0] <= sl_data_revrw[SL_LENGTH-1:0];
sl_data_capr[SL_LENGTH-1:0] <= sl_data_caprw[SL_LENGTH-1:0];
end
end
endmodule // aib_sr_slave |
module aib_sr_fsm
(
input osc_clk, //From Aux
input sr_ms_clk_in, //Input ms clock
output reg ms_osc_transfer_en, //Leader Clock has completed calibration
output reg ms_rx_transfer_en, //Leader receive block has completed calibration
output reg ms_rx_dll_lock, //Leader rx has completed its DLL lock
output reg ms_tx_dcc_cal_done, //Leader has completed its DCC calibration.
output reg ms_tx_transfer_en, //Leader transmit block has completed calibration
input ms_rx_dcc_dll_lock_req, //Leader requests calibration of F2L datapath
input ms_tx_dcc_dll_lock_req, //Leader requests calibration of L2F datapath
input ms_rx_dll_lockint, //Internal DLL Lock is omplete
input ms_tx_dcc_cal_doneint, //Internal DCC calibration is complete
input ms_tx_dcc_cal_donei, //From sr interface
input ms_rx_dll_locki, //From sr interface
input ms_rx_transfer_eni, //From sr interface
input ms_tx_transfer_eni, //From sr interface
input ms_osc_transfer_eni, //From sr interface
output reg sl_osc_transfer_en, //Follower Clock has completed calibration
output reg sl_rx_transfer_en, //Calibration of follower RX datapath is complete
output reg sl_tx_dcc_cal_done, //Follower has completed its DCC calibration.
output reg sl_tx_transfer_en, //Follower receive block has completed calibration
output reg sl_rx_dll_lock, //Follower rx has completed its DLL lock.
input sl_tx_dcc_dll_lock_req, //Follower requests calibration of F2L datapath
input sl_rx_dcc_dll_lock_req, //Follower requests calibration of L2F datapath
input sl_rx_dll_lockint, //From slave internal
input sl_rx_dll_locki, //From sr interface
input sl_tx_dcc_cal_donei, //From sr interface
input sl_tx_dcc_cal_doneint, //From slave internal
input sl_rx_transfer_eni, //From sr interface
input sl_osc_transfer_eni, //From sr interface
input ms_nsl, //"1", this is a Master. "0", this is a Slave
input n_lpbk, // Nearside loopback
input osc_fsm_ms_rstn,
input osc_fsm_sl_rstn,
input cal_fsm_ms_rstn,
input cal_fsm_sl_rstn
);
parameter MS_WAIT_RX_OSC_RDY = 2'd0, //osc sync states
MS_OSC_XFER_EN = 2'd1,
MS_OSC_XFER_ALIVE = 2'd2,
SL_WAIT_RX_OSC_RDY = 1'd0,
SL_OSC_XFER_EN = 1'd1,
MS_WAIT_RX_XFER_REQ = 3'd0, //slave tx to master rx cal states
MS_WAIT_REMT_TX_DCC_CAL_DONE = 3'd1,
MS_SEND_MS_RX_DLL_LOCK_REQ = 3'd2,
MS_RX_DLL_LOCK_ST = 3'd3,
MS_RX_XFER_EN = 3'd4,
SL_WAIT_TX_XFER_REQ = 3'd0,
SL_SEND_TX_DCC_CAL_REQ = 3'd1,
SL_WAIT_REMT_RX_DLL_LOCK = 3'd2,
SL_WAIT_REMT_RX_TRANSFER_EN = 3'd3,
SL_TX_XFER_EN = 3'd4,
MS_WAIT_TX_XFER_REQ = 3'd0, //master tx to slave rx cal states
MS_SEND_TX_DCC_CAL_REQ = 3'd1,
MS_WAIT_REMT_RX_DLL_LOCK = 3'd2,
MS_WAIT_REMT_RX_TRANSFER_EN = 3'd3,
MS_TX_XFER_EN = 3'd4,
SL_WAIT_RX_XFER_REQ = 3'd0,
SL_SEND_RX_DLL_LOCK_REQ = 3'd1,
SL_RX_DLL_LOCK_ST = 3'd2,
SL_RX_XFER_EN = 3'd3,
SL_RX_XFER_ALIVE = 3'd4;
reg [1:0] msosc_curst, msosc_nxst;
reg slosc_curst, slosc_nxst;
reg [2:0] msrxcal_curst, msrxcal_nxst;
reg [2:0] sltxcal_curst, sltxcal_nxst;
reg [2:0] mstxcal_curst, mstxcal_nxst;
reg [2:0] slrxcal_curst, slrxcal_nxst;
reg ms_osc_transfer_alive; //Leader OSC alive
wire is_master, is_slave;
wire ms_rx_dcc_dll_lock_req_sync, ms_rx_dll_lock_sync;
wire ms_tx_dcc_dll_lock_req_sync;
wire sl_rx_dcc_dll_lock_req_sync, sl_rx_transfer_en_sync;
wire sl_osc_transfer_en_sync;
wire sl_tx_dcc_dll_lock_req_sync, sl_tx_dcc_cal_done_slsync;
wire ms_osc_transfer_en_sync, ms_rx_transfer_en_sync, ms_tx_transfer_en_sync;
wire ms_osc_transfer_enw, ms_osc_transfer_alivew;
wire ms_rx_dll_lockw;
wire ms_rx_transfer_enw, ms_tx_dcc_cal_donew;
wire ms_tx_transfer_enw;
wire sl_osc_transfer_enw;
wire sl_tx_dcc_cal_donew, sl_tx_transfer_enw;
wire sl_rx_dll_lockw;
wire sl_rx_transfer_enw;
wire sl_tx_dcc_cal_done_sync;
wire ms_tx_dcc_cal_done_sync;
wire sl_rx_dll_lock_sync;
wire ms_rx_dll_lock_slsync;
wire ms_tx_dcc_cal_done_slsync;
wire sl_rx_dll_lock_slsync;
aib_bit_sync i_sloscxferen_sync
(
.clk(osc_clk),
.rst_n(osc_fsm_ms_rstn),
.data_in(sl_osc_transfer_eni),
.data_out(sl_osc_transfer_en_sync)
);
aib_bit_sync i_sltxdlldcclockreq_sync
(
.clk(osc_clk),
.rst_n(cal_fsm_ms_rstn),
.data_in(sl_tx_dcc_dll_lock_req),
.data_out(sl_tx_dcc_dll_lock_req_sync)
);
aib_bit_sync i_msrxdlldcclockreq
(
.clk(osc_clk),
.rst_n(cal_fsm_ms_rstn),
.data_in(ms_rx_dcc_dll_lock_req),
.data_out(ms_rx_dcc_dll_lock_req_sync)
);
aib_bit_sync i_msrxdlllock
(
.clk(osc_clk),
.rst_n(cal_fsm_ms_rstn),
.data_in(ms_rx_dll_lockint),
.data_out(ms_rx_dll_lock_sync)
);
aib_bit_sync i_sltxdcccaldone
(
.clk(osc_clk),
.rst_n(cal_fsm_ms_rstn),
.data_in(sl_tx_dcc_cal_donei),
.data_out(sl_tx_dcc_cal_done_sync)
);
aib_bit_sync i_slrxdlldcclockreq
(
.clk(osc_clk),
.rst_n(cal_fsm_ms_rstn),
.data_in(sl_rx_dcc_dll_lock_req),
.data_out(sl_rx_dcc_dll_lock_req_sync)
);
aib_bit_sync i_mstxdlldcclockreq
(
.clk(osc_clk),
.rst_n(cal_fsm_ms_rstn),
.data_in(ms_tx_dcc_dll_lock_req),
.data_out(ms_tx_dcc_dll_lock_req_sync)
);
aib_bit_sync i_mstxdcccaldone
(
.clk(osc_clk),
.rst_n(cal_fsm_ms_rstn),
.data_in(ms_tx_dcc_cal_doneint),
.data_out(ms_tx_dcc_cal_done_sync)
);
aib_bit_sync i_slrxdlllock
(
.clk(osc_clk),
.rst_n(cal_fsm_ms_rstn),
.data_in(sl_rx_dll_locki),
.data_out(sl_rx_dll_lock_sync)
);
aib_bit_sync i_slrxtranseren
(
.clk(osc_clk),
.rst_n(cal_fsm_ms_rstn),
.data_in(sl_rx_transfer_eni),
.data_out(sl_rx_transfer_en_sync)
);
aib_bit_sync i_msoscxferen_sync
(
.clk(sr_ms_clk_in),
.rst_n(osc_fsm_sl_rstn),
.data_in(ms_osc_transfer_eni),
.data_out(ms_osc_transfer_en_sync)
);
aib_bit_sync i_slsltxdcccaldone
(
.clk(sr_ms_clk_in),
.rst_n(cal_fsm_sl_rstn),
.data_in(sl_tx_dcc_cal_doneint),
.data_out(sl_tx_dcc_cal_done_slsync)
);
aib_bit_sync i_slmsrxdlllock
(
.clk(sr_ms_clk_in),
.rst_n(cal_fsm_sl_rstn),
.data_in(ms_rx_dll_locki),
.data_out(ms_rx_dll_lock_slsync)
);
aib_bit_sync i_msrxtransferen
(
.clk(sr_ms_clk_in),
.rst_n(cal_fsm_sl_rstn),
.data_in(ms_rx_transfer_eni),
.data_out(ms_rx_transfer_en_sync)
);
aib_bit_sync i_slmstxdcccaldone
(
.clk(sr_ms_clk_in),
.rst_n(cal_fsm_sl_rstn),
.data_in(ms_tx_dcc_cal_donei),
.data_out(ms_tx_dcc_cal_done_slsync)
);
aib_bit_sync i_slslrxdlllock
(
.clk(sr_ms_clk_in),
.rst_n(cal_fsm_sl_rstn),
.data_in(sl_rx_dll_lockint),
.data_out(sl_rx_dll_lock_slsync)
);
aib_bit_sync i_mstxtransferen
(
.clk(sr_ms_clk_in),
.rst_n(cal_fsm_sl_rstn),
.data_in(ms_tx_transfer_eni),
.data_out(ms_tx_transfer_en_sync)
);
assign is_master = (ms_nsl == 1'b1) ? 1'b1 : 1'b0;
assign is_slave = !is_master;
assign ms_osc_transfer_enw = (msosc_curst[1:0]== MS_OSC_XFER_EN) ? 1'b1 :
(msosc_curst[1:0]== MS_WAIT_RX_OSC_RDY) ? 1'b0 : ms_osc_transfer_en;
assign ms_osc_transfer_alivew = (msosc_curst[1:0]== MS_OSC_XFER_ALIVE) ? 1'b1 :
(msosc_curst[1:0]== MS_WAIT_RX_OSC_RDY) ? 1'b0 : ms_osc_transfer_alive;
assign ms_rx_dll_lockw = (msrxcal_curst[2:0] == MS_RX_DLL_LOCK_ST) ? 1'b1 :
(msrxcal_curst[2:0] == MS_WAIT_RX_XFER_REQ) ? 1'b0 : ms_rx_dll_lock;
assign ms_rx_transfer_enw = (msrxcal_curst[2:0] == MS_RX_XFER_EN) ? 1'b1 :
(msrxcal_curst[2:0] == MS_WAIT_RX_XFER_REQ) ? 1'b0 : ms_rx_transfer_en;
assign ms_tx_dcc_cal_donew = (mstxcal_curst[2:0] == MS_WAIT_REMT_RX_DLL_LOCK) ? 1'b1 :
(mstxcal_curst[2:0] == MS_WAIT_TX_XFER_REQ) ? 1'b0 : ms_tx_dcc_cal_done;
assign ms_tx_transfer_enw = (mstxcal_curst[2:0] == MS_TX_XFER_EN) ? 1'b1 :
(mstxcal_curst[2:0] == MS_WAIT_TX_XFER_REQ) ? 1'b0 : ms_tx_transfer_en;
assign sl_osc_transfer_enw = (slosc_curst== SL_OSC_XFER_EN) ? 1'b1 :
(slosc_curst== SL_WAIT_RX_OSC_RDY) ? 1'b0 : sl_osc_transfer_en;
assign sl_tx_dcc_cal_donew = (sltxcal_curst[2:0] == SL_WAIT_REMT_RX_DLL_LOCK) ? 1'b1 :
(sltxcal_curst[2:0] == SL_WAIT_TX_XFER_REQ) ? 1'b0 : sl_tx_dcc_cal_done;
assign sl_tx_transfer_enw = (sltxcal_curst[2:0] == SL_TX_XFER_EN) ? 1'b1 :
(sltxcal_curst[2:0] == SL_WAIT_TX_XFER_REQ) ? 1'b0 : sl_tx_transfer_en;
assign sl_rx_dll_lockw = (slrxcal_curst[2:0] == SL_RX_DLL_LOCK_ST) ? 1'b1 :
(slrxcal_curst[2:0] == SL_WAIT_RX_XFER_REQ) ? 1'b0 : sl_rx_dll_lock;
assign sl_rx_transfer_enw = (slrxcal_curst[2:0] == SL_RX_XFER_EN) ? 1'b1 :
(slrxcal_curst[2:0] == SL_WAIT_RX_XFER_REQ) ? 1'b0 : sl_rx_transfer_en;
always @ (posedge osc_clk or negedge cal_fsm_ms_rstn)
begin
if(!cal_fsm_ms_rstn)
begin
ms_rx_dll_lock <= 1'b0;
ms_rx_transfer_en <= 1'b0;
ms_tx_dcc_cal_done <= 1'b0;
ms_tx_transfer_en <= 1'b0;
end
else
begin
ms_rx_dll_lock <= ms_rx_dll_lockw;
ms_rx_transfer_en <= ms_rx_transfer_enw;
ms_tx_dcc_cal_done <= ms_tx_dcc_cal_donew;
ms_tx_transfer_en <= ms_tx_transfer_enw;
end
end
always @ (posedge sr_ms_clk_in or negedge cal_fsm_sl_rstn)
begin
if(!cal_fsm_sl_rstn)
begin
sl_tx_dcc_cal_done <= 1'b0;
sl_tx_transfer_en <= 1'b0;
sl_rx_dll_lock <= 1'b0;
sl_rx_transfer_en <= 1'b0;
end
else
begin
sl_tx_dcc_cal_done <= sl_tx_dcc_cal_donew;
sl_tx_transfer_en <= sl_tx_transfer_enw;
sl_rx_dll_lock <= sl_rx_dll_lockw;
sl_rx_transfer_en <= sl_rx_transfer_enw;
end
end
//Master oscillator sync. sequence
always @ (posedge osc_clk or negedge osc_fsm_ms_rstn)
begin
if(!osc_fsm_ms_rstn)
begin
msosc_curst[1:0] <= 2'b0;
ms_osc_transfer_en <= 1'b0;
ms_osc_transfer_alive <= 1'b0;
end
else
begin
msosc_curst[1:0] <= msosc_nxst[1:0];
ms_osc_transfer_en <= ms_osc_transfer_enw;
ms_osc_transfer_alive <= ms_osc_transfer_alivew;
end
end
always @(*)
begin
case (msosc_curst)
MS_WAIT_RX_OSC_RDY:
begin
if (is_master )
msosc_nxst = MS_OSC_XFER_EN;
else
msosc_nxst = MS_WAIT_RX_OSC_RDY;
end
MS_OSC_XFER_EN:
begin
if (sl_osc_transfer_en_sync | n_lpbk)
msosc_nxst = MS_OSC_XFER_ALIVE;
else
msosc_nxst = MS_OSC_XFER_EN;
end
MS_OSC_XFER_ALIVE:
begin
msosc_nxst = MS_OSC_XFER_ALIVE;
end
default:
begin
msosc_nxst = MS_WAIT_RX_OSC_RDY;
end
endcase
end
//Slave oscillator sync. sequence
always @ (posedge sr_ms_clk_in or negedge osc_fsm_sl_rstn)
begin
if(!osc_fsm_sl_rstn)
begin
slosc_curst <= 1'b0;
sl_osc_transfer_en <= 1'b0;
end
else
begin
slosc_curst <= slosc_nxst;
sl_osc_transfer_en <= sl_osc_transfer_enw;
end
end
always @(*)
begin
case (slosc_curst)
SL_WAIT_RX_OSC_RDY:
begin
if (is_slave && ms_osc_transfer_en_sync)
slosc_nxst = SL_OSC_XFER_EN;
else
slosc_nxst = SL_WAIT_RX_OSC_RDY;
end
SL_OSC_XFER_EN:
begin
slosc_nxst = SL_OSC_XFER_EN;
end
endcase
end
//Slave_TX to Master_RX calibration sequence
always @ (posedge osc_clk or negedge cal_fsm_ms_rstn)
begin
if(!cal_fsm_ms_rstn)
begin
msrxcal_curst[2:0] <= 3'b0;
end
else
begin
msrxcal_curst[2:0] <= msrxcal_nxst[2:0];
end
end
always @(*)
begin
case (msrxcal_curst)
MS_WAIT_RX_XFER_REQ:
begin
if (is_master && ms_osc_transfer_alive &&
( (sl_tx_dcc_dll_lock_req_sync || n_lpbk) && ms_rx_dcc_dll_lock_req_sync))
msrxcal_nxst = MS_WAIT_REMT_TX_DCC_CAL_DONE;
else
msrxcal_nxst = MS_WAIT_RX_XFER_REQ;
end
MS_WAIT_REMT_TX_DCC_CAL_DONE:
begin
if (!ms_rx_dcc_dll_lock_req_sync || !(sl_tx_dcc_dll_lock_req_sync || n_lpbk))
msrxcal_nxst = MS_WAIT_RX_XFER_REQ;
else if (sl_tx_dcc_cal_done_sync || n_lpbk)
msrxcal_nxst = MS_SEND_MS_RX_DLL_LOCK_REQ;
else
msrxcal_nxst = MS_WAIT_REMT_TX_DCC_CAL_DONE;
end
MS_SEND_MS_RX_DLL_LOCK_REQ:
begin
if (!ms_rx_dcc_dll_lock_req_sync || !(sl_tx_dcc_dll_lock_req_sync || n_lpbk))
msrxcal_nxst = MS_WAIT_RX_XFER_REQ;
else if (ms_rx_dll_lock_sync)
msrxcal_nxst = MS_RX_DLL_LOCK_ST;
else
msrxcal_nxst = MS_SEND_MS_RX_DLL_LOCK_REQ;
end
MS_RX_DLL_LOCK_ST:
begin
if (!ms_rx_dcc_dll_lock_req_sync || !(sl_tx_dcc_dll_lock_req_sync || n_lpbk))
msrxcal_nxst = MS_WAIT_RX_XFER_REQ;
else
msrxcal_nxst = MS_RX_XFER_EN;
end
MS_RX_XFER_EN:
begin
if (!( (sl_tx_dcc_dll_lock_req_sync || n_lpbk) && ms_rx_dcc_dll_lock_req_sync ))
msrxcal_nxst = MS_WAIT_RX_XFER_REQ;
else
msrxcal_nxst = MS_RX_XFER_EN;
end
default:
begin
msrxcal_nxst = MS_WAIT_RX_XFER_REQ;
end
endcase
end
always @ (posedge sr_ms_clk_in or negedge cal_fsm_sl_rstn)
begin
if(!cal_fsm_sl_rstn)
begin
sltxcal_curst[2:0] <= 3'b0;
end
else
begin
sltxcal_curst[2:0] <= sltxcal_nxst[2:0];
end
end
always @(*)
begin
case (sltxcal_curst)
SL_WAIT_TX_XFER_REQ:
begin
if (is_slave && sl_osc_transfer_en && !sl_tx_dcc_cal_done)
sltxcal_nxst = SL_SEND_TX_DCC_CAL_REQ;
else
sltxcal_nxst = SL_WAIT_TX_XFER_REQ;
end
SL_SEND_TX_DCC_CAL_REQ:
begin
if (sl_tx_dcc_cal_done_slsync)
sltxcal_nxst = SL_WAIT_REMT_RX_DLL_LOCK;
else
sltxcal_nxst = SL_SEND_TX_DCC_CAL_REQ;
end
SL_WAIT_REMT_RX_DLL_LOCK:
begin
if (ms_rx_dll_lock_slsync)
sltxcal_nxst = SL_WAIT_REMT_RX_TRANSFER_EN;
else
sltxcal_nxst = SL_WAIT_REMT_RX_DLL_LOCK;
end
SL_WAIT_REMT_RX_TRANSFER_EN:
begin
if (ms_rx_transfer_en_sync)
sltxcal_nxst = SL_TX_XFER_EN;
else
sltxcal_nxst = SL_WAIT_REMT_RX_TRANSFER_EN;
end
SL_TX_XFER_EN:
begin
if (!ms_rx_transfer_en_sync) //??? clarify, fig6-5
sltxcal_nxst = SL_WAIT_TX_XFER_REQ;
else
sltxcal_nxst = SL_TX_XFER_EN;
end
default:
begin
sltxcal_nxst = SL_WAIT_TX_XFER_REQ;
end
endcase
end
//Master_TX to Slave_RX calibration sequence
always @ (posedge osc_clk or negedge cal_fsm_ms_rstn)
begin
if(!cal_fsm_ms_rstn)
begin
mstxcal_curst[2:0] <= 3'b0;
end
else
begin
mstxcal_curst[2:0] <= mstxcal_nxst[2:0];
end
end
always @(*)
begin
case (mstxcal_curst)
MS_WAIT_TX_XFER_REQ:
begin
if (is_master && ms_osc_transfer_alive &&
((sl_rx_dcc_dll_lock_req_sync || n_lpbk) && ms_tx_dcc_dll_lock_req_sync))
mstxcal_nxst = MS_SEND_TX_DCC_CAL_REQ;
else
mstxcal_nxst = MS_WAIT_TX_XFER_REQ;
end
MS_SEND_TX_DCC_CAL_REQ:
begin
if (!ms_tx_dcc_dll_lock_req_sync || !(sl_rx_dcc_dll_lock_req_sync || n_lpbk) )
mstxcal_nxst = MS_WAIT_TX_XFER_REQ;
else if (ms_tx_dcc_cal_done_sync)
mstxcal_nxst = MS_WAIT_REMT_RX_DLL_LOCK;
else
mstxcal_nxst = MS_SEND_TX_DCC_CAL_REQ;
end
MS_WAIT_REMT_RX_DLL_LOCK:
begin
if (!ms_tx_dcc_dll_lock_req_sync || !(sl_rx_dcc_dll_lock_req_sync || n_lpbk) )
mstxcal_nxst = MS_WAIT_TX_XFER_REQ;
else if (sl_rx_dll_lock_sync || n_lpbk)
mstxcal_nxst = MS_WAIT_REMT_RX_TRANSFER_EN;
else
mstxcal_nxst = MS_WAIT_REMT_RX_DLL_LOCK;
end
MS_WAIT_REMT_RX_TRANSFER_EN:
begin
if (!ms_tx_dcc_dll_lock_req_sync || !(sl_rx_dcc_dll_lock_req_sync || n_lpbk) )
mstxcal_nxst = MS_WAIT_TX_XFER_REQ;
else if (sl_rx_transfer_en_sync || n_lpbk)
mstxcal_nxst = MS_TX_XFER_EN;
else
mstxcal_nxst = MS_WAIT_REMT_RX_TRANSFER_EN;
end
MS_TX_XFER_EN:
begin
if (!((sl_rx_dcc_dll_lock_req_sync || n_lpbk) && ms_tx_dcc_dll_lock_req_sync) )
mstxcal_nxst = MS_WAIT_TX_XFER_REQ;
else
mstxcal_nxst = MS_TX_XFER_EN;
end
default:
begin
mstxcal_nxst = MS_WAIT_TX_XFER_REQ;
end
endcase
end
always @ (posedge sr_ms_clk_in or negedge cal_fsm_sl_rstn)
begin
if(!cal_fsm_sl_rstn)
begin
slrxcal_curst[2:0] <= 3'b0;
end
else
begin
slrxcal_curst[2:0] <= slrxcal_nxst[2:0];
end
end
always @(*)
begin
case (slrxcal_curst)
SL_WAIT_RX_XFER_REQ:
begin
if (is_slave && sl_osc_transfer_en && ms_tx_dcc_cal_done_slsync && !sl_rx_dll_lock)
slrxcal_nxst = SL_SEND_RX_DLL_LOCK_REQ;
else
slrxcal_nxst = SL_WAIT_RX_XFER_REQ;
end
SL_SEND_RX_DLL_LOCK_REQ:
begin
if (sl_rx_dll_lock_slsync)
slrxcal_nxst = SL_RX_DLL_LOCK_ST;
else
slrxcal_nxst = SL_SEND_RX_DLL_LOCK_REQ;
end
SL_RX_DLL_LOCK_ST:
begin
slrxcal_nxst = SL_RX_XFER_EN;
end
SL_RX_XFER_EN:
begin
if (ms_tx_transfer_en_sync)
slrxcal_nxst = SL_RX_XFER_ALIVE;
else
slrxcal_nxst = SL_RX_XFER_EN;
end
SL_RX_XFER_ALIVE:
begin
if (!ms_tx_transfer_en_sync)
slrxcal_nxst = SL_WAIT_RX_XFER_REQ;
else
slrxcal_nxst = SL_RX_XFER_ALIVE;
end
default:
begin
slrxcal_nxst = SL_WAIT_RX_XFER_REQ;
end
endcase
end
endmodule // aib_sr_fsm |
module aib_sr_master #(
parameter MS_LENGTH = 7'd81
)
(
// AIB IO Bidirectional
input osc_clk, //free running osc clock
input [MS_LENGTH-1:0] ms_data_fr_core, //Data from Core
output wire [MS_LENGTH-1:0] ms_data_to_core, //Data to Core
output reg sr_ms_data_out, //master serial data out
output reg sr_ms_load_out, //master load out
input sr_ms_data_in, //master serial data out
input sr_ms_load_in, //master serial data load inupt
input sr_ms_clk_in, //from input por
input osc_fsm_ms_rstn,
input osc_fsm_sl_rstn
);
localparam [MS_LENGTH-1:0] MS_BUS_RST_VAL = { 1'b0, // ms_osc_transfer_en
1'b1,
1'b0, // ms_tx_transfer_en_m
2'b11,
1'b0, // ms_rx_transfer_en_m
1'b0, // ms_rx_dll_lock
5'b11111,
1'b0, // ms_tx_dcc_cal_done
1'b0,
1'b1,
58'h0, // ms_external_cntl_65_8[57:0]
1'b1,
1'b0,
1'b1,
5'h0 }; // ms_external_cntl_4_0[4:0]
reg [6:0] ms_count;
reg ms_load;
reg [MS_LENGTH-1:0] ms_data_syncr; //master shift output register
reg [MS_LENGTH-1:0] ms_data_revr; //shift receive register
reg [MS_LENGTH-1:0] ms_data_capr; //captured master serial data register
reg ms_shift_en;
wire [MS_LENGTH-1:0] ms_data_sync, ms_data_syncrw, ms_data_revrw, ms_data_caprw;
wire sr_ms_data_outw; //master serial data out
wire sr_ms_load_outw; //master load out
assign ms_data_to_core[MS_LENGTH-1:0] = ms_data_capr[MS_LENGTH-1:0];
aib_bit_sync #(
.DWIDTH (MS_LENGTH),
.RESET_VAL (MS_BUS_RST_VAL)
)
i_ms_data_sync(
.clk (osc_clk),
.rst_n (osc_fsm_ms_rstn),
.data_in (ms_data_fr_core[MS_LENGTH-1:0]),
.data_out(ms_data_sync[MS_LENGTH-1:0])
);
always @(negedge osc_clk or negedge osc_fsm_ms_rstn) begin
if (!osc_fsm_ms_rstn)
begin
sr_ms_data_out <= 1'b0;
sr_ms_load_out <= 1'b0;
end
else
begin
sr_ms_data_out <= sr_ms_data_outw;
sr_ms_load_out <= sr_ms_load_outw;
end
end
always @(posedge osc_clk or negedge osc_fsm_ms_rstn) begin
if (!osc_fsm_ms_rstn)
begin
ms_count[6:0] <= 7'h0;
ms_load <= 1'b0;
ms_shift_en <= 1'b0;
end
else
begin
if (ms_count[6:0]==(MS_LENGTH))
begin
ms_count[6:0] <= 7'h0;
ms_load <= 1'b1;
ms_shift_en <= 1'b0;
end
else
begin // increment counter
ms_count[6:0] <= ms_count[6:0] + 7'h01;
ms_load <= 1'b0;
ms_shift_en <= 1'b1;
end
end
end
assign sr_ms_data_outw = ms_data_syncr[MS_LENGTH-1];
assign sr_ms_load_outw = ms_load;
assign ms_data_syncrw[MS_LENGTH-1:0] = ms_load ?
ms_data_sync[MS_LENGTH-1:0] :
ms_shift_en ?
{ms_data_syncr[MS_LENGTH-2:0], ms_data_syncr[0]} :
ms_data_syncr[MS_LENGTH-1:0];
always @(posedge osc_clk or negedge osc_fsm_ms_rstn) begin
if (!osc_fsm_ms_rstn)
begin
ms_data_syncr[MS_LENGTH-1:0] <= 81'h0;
end
else
begin
ms_data_syncr[MS_LENGTH-1:0] <= ms_data_syncrw[MS_LENGTH-1:0];
end
end
assign ms_data_revrw[MS_LENGTH-1:0] = sr_ms_load_in ? ms_data_revr[MS_LENGTH-1:0] : {ms_data_revr[MS_LENGTH-2:0], sr_ms_data_in};
assign ms_data_caprw[MS_LENGTH-1:0] = sr_ms_load_in ? ms_data_revr[MS_LENGTH-1:0] : ms_data_capr[MS_LENGTH-1:0];
always @(posedge sr_ms_clk_in or negedge osc_fsm_sl_rstn) begin
if (!osc_fsm_sl_rstn)
begin
ms_data_revr[MS_LENGTH-1:0] <= 81'h0;
ms_data_capr[MS_LENGTH-1:0] <= 81'h0;
end
else
begin
ms_data_revr[MS_LENGTH-1:0] <= ms_data_revrw[MS_LENGTH-1:0];
ms_data_capr[MS_LENGTH-1:0] <= ms_data_caprw[MS_LENGTH-1:0];
end
end
endmodule // aib_sr_master |
module aib_channel
#(
parameter MAX_SCAN_LEN = 200,
parameter DATAWIDTH = 40
)
(
inout wire [101:0] iopad_aib,
input [DATAWIDTH*8-1:0] data_in_f,
output [DATAWIDTH*8-1:0] data_out_f,
input [DATAWIDTH*2-1:0] data_in,
output [DATAWIDTH*2-1:0] data_out,
input m_ns_fwd_clk,
input m_ns_rcv_clk,
output m_fs_rcv_clk,
output m_fs_fwd_clk,
input m_wr_clk,
input m_rd_clk,
output tclk_phy,
input ns_adapter_rstn, //The name is the same as spec, but not consistent
input ns_mac_rdy, //with other m_* name convention.
output fs_mac_rdy, //
input i_conf_done,
input ms_rx_dcc_dll_lock_req,
input ms_tx_dcc_dll_lock_req,
input sl_tx_dcc_dll_lock_req,
input sl_rx_dcc_dll_lock_req,
output ms_tx_transfer_en,
output ms_rx_transfer_en,
output sl_tx_transfer_en,
output sl_rx_transfer_en,
output m_rx_align_done,
output [80:0] sr_ms_tomac,
output [72:0] sr_sl_tomac,
//Sideband user input
input [26:0] sl_external_cntl_26_0, //user defined bits 26:0 for slave shift register
input [2:0] sl_external_cntl_30_28, //user defined bits 30:28 for slave shift register
input [25:0] sl_external_cntl_57_32, //user defined bits 57:32 for slave shift register
input [4:0] ms_external_cntl_4_0, //user defined bits 4:0 for master shift register
input [57:0] ms_external_cntl_65_8, //user defined bits 65:8 for master shift register
input dual_mode_select, //Mater or Slave
input m_gen2_mode, //If 1, it is aib2.0
//Interface with aux channel
input por, //from aux channel
input i_osc_clk, //from aux channel
//JTAG interface
input jtag_clkdr_in,
output wire scan_out,
input jtag_intest,
input jtag_mode_in,
input jtag_rstb,
input jtag_rstb_en,
input jtag_weakpdn,
input jtag_weakpu,
input jtag_tx_scanen_in,
input scan_in,
//Scan IO ports
input i_scan_clk,
input i_scan_clk_500m,
input i_scan_clk_1000m,
input i_scan_en,
input i_scan_mode,
input [MAX_SCAN_LEN-1:0] i_scan_din,
output [MAX_SCAN_LEN-1:0] i_scan_dout,
input [5:0] i_channel_id, // channel ID to program
input i_cfg_avmm_clk,
input i_cfg_avmm_rst_n,
input [16:0] i_cfg_avmm_addr, // address to be programmed
input [3:0] i_cfg_avmm_byte_en, // byte enable
input i_cfg_avmm_read, // Asserted to indicate the Cfg read access
input i_cfg_avmm_write, // Asserted to indicate the Cfg write access
input [31:0] i_cfg_avmm_wdata, // data to be programmed
output o_cfg_avmm_rdatavld,// Assert to indicate data available for Cfg read access
output [31:0] o_cfg_avmm_rdata, // data returned for Cfg read access
output o_cfg_avmm_waitreq // asserted to indicate not ready for Cfg access
);
wire [DATAWIDTH-1:0] iopad_tx;
wire [DATAWIDTH-1:0] iopad_rx;
wire dig_rstb;
wire ms_rx_dll_lock_req;
wire ms_rx_dll_lock;
wire ms_tx_async_rst;
wire ms_tx_dcc_cal_req;
wire ms_tx_dcc_cal_doneint;
wire ms_rx_dll_lockint;
wire sl_osc_transfer_en;
wire sl_fifo_tx_async_rst;
wire sl_tx_dcc_cal_done;
wire sl_tx_dcc_cal_req;
wire sl_rx_async_rst;
wire sl_rx_dll_lock_req;
wire sl_rx_dll_lock;
wire sl_tx_dcc_cal_doneint;
wire sl_rx_dll_lockint;
wire std_out;
wire stl_out;
wire srd_in;
wire srl_in;
wire sr_ms_load_out;
wire sr_clk_in;
wire sr_clk_out;
wire clkp;
wire adpt_rstn;
wire rstn_out, adapter_rstno;
wire sr_ms_data_out;
wire [80:0] ms_data_fr_core, ms_data_to_core;
wire sr_sl_clk_out;
wire [72:0] sl_data_fr_core, sl_data_to_core;
wire sr_sl_data_out;
wire sr_sl_load_out;
wire adapter_rstni;
wire dcc_clk_out;
wire rstn_in;
wire [31:0] rx_adapt_0, rx_adapt_1;
wire [31:0] tx_adapt_0, tx_adapt_1;
wire [31:0] redund_0, redund_1, redund_2, redund_3;
wire [79:0] aibio_din, aibio_dout;
aib_avmm avmm_config (
.cfg_avmm_addr_id(i_channel_id),
.cfg_avmm_clk(i_cfg_avmm_clk),
.cfg_avmm_rst_n(i_cfg_avmm_rst_n),
.cfg_avmm_write(i_cfg_avmm_write),
.cfg_avmm_read(i_cfg_avmm_read),
.cfg_avmm_addr(i_cfg_avmm_addr),
.cfg_avmm_wdata(i_cfg_avmm_wdata),
.cfg_avmm_byte_en(i_cfg_avmm_byte_en),
.cfg_avmm_rdata(o_cfg_avmm_rdata),
.cfg_avmm_rdatavld(o_cfg_avmm_rdatavld),
.cfg_avmm_waitreq(o_cfg_avmm_waitreq),
//Adapt control CSR
.rx_adapt_0(rx_adapt_0),
.rx_adapt_1(rx_adapt_1),
.tx_adapt_0(tx_adapt_0),
.tx_adapt_1(tx_adapt_1),
.redund_0(redund_0),
.redund_1(redund_1),
.redund_2(redund_2),
.redund_3(redund_3)
//AIB IO control CSR
);
wire vccl_aib = 1'b1;
wire vssl_aib = 1'b0;
//////////////////////////////////////////////////////////////////////
//CSR for IO redundancy. See Table 50. Example Bump Table of AIB 2.0
////////////////////////////////////////////////////////////////////////
wire [101:0] AIB = {redund_3[5:0], redund_2[31:0], redund_1[31:0], redund_0[31:0]};
wire [39:0] csr_shift_rxdat = {AIB[100],AIB[101],AIB[98],AIB[99],AIB[96],AIB[97],AIB[94],AIB[95],AIB[92],AIB[93],
AIB[90], AIB[91], AIB[88],AIB[89],AIB[86],AIB[87],AIB[84],AIB[85],AIB[82],AIB[83],
AIB[80], AIB[81], AIB[78],AIB[79],AIB[76],AIB[77],AIB[74],AIB[75],AIB[72],AIB[73],
AIB[68], AIB[69], AIB[66],AIB[67],AIB[64],AIB[65],AIB[62],AIB[63],AIB[60],AIB[61]};
wire csr_shift_fs_fwd_clk = AIB[71];
wire csr_shift_fs_fwd_clkb = AIB[70];
wire csr_shift_fs_rcv_clk = AIB[59];
wire csr_shift_fs_rcv_clkb = AIB[58];
wire csr_shift_fs_sr_clk = AIB[57];
wire csr_shift_fs_sr_clkb = AIB[56];
wire csr_shift_fs_sr_data = AIB[55];
wire csr_shift_fs_sr_load = AIB[54];
wire csr_shift_fs_mac_rdy = AIB[53];
wire csr_shift_fs_adapter_rstn = AIB[52];
wire [1:0] csr_shift_spare = AIB[51:50];
wire csr_shift_ns_adapter_rstn = AIB[49];
wire csr_shift_ns_mac_rdy = AIB[48];
wire csr_shift_ns_sr_load = AIB[47];
wire csr_shift_ns_sr_data = AIB[46];
wire csr_shift_ns_sr_clkb = AIB[45];
wire csr_shift_ns_sr_clk = AIB[44];
wire csr_shift_ns_rcv_clkb = AIB[43];
wire csr_shift_ns_rcv_clk = AIB[42];
wire csr_shift_ns_fwd_clkb = AIB[31];
wire csr_shift_ns_fwd_clk = AIB[30];
wire [39:0] csr_shift_txdat = {AIB[1], AIB[0], AIB[3], AIB[2], AIB[5], AIB[4], AIB[7], AIB[6], AIB[9], AIB[8],
AIB[11],AIB[10],AIB[13],AIB[12],AIB[15],AIB[14],AIB[17],AIB[16],AIB[19],AIB[18],
AIB[21],AIB[20],AIB[23],AIB[22],AIB[25],AIB[24],AIB[27],AIB[26],AIB[29],AIB[28],
AIB[33],AIB[32],AIB[35],AIB[34],AIB[37],AIB[36],AIB[39],AIB[38],AIB[41],AIB[40]};
wire csr_iddren = 1'b1; //csr for turn on DDR bumps
wire csr_idataselb = 1'b0; //csr for turn on async buffer
wire csr_itxen = 1'b1; //csr for turn on transmit buffer
wire [2:0] csr_irxen = 3'b111; //csr for turn on receiver buffer
///////////////////////////////////////////////////////////////////////////////////////////
//CSR for Adapter
///////////////////////////////////////////////////////////////////////////////////////////
wire [1:0] csr_rx_fifo_mode=rx_adapt_1[2:1]; //2'b00 1xfifo, 2'b01 2xfifo, 2'b10 4xfifo, 2'b11 reg mode
wire [1:0] csr_tx_fifo_mode=tx_adapt_0[22:21]; //2'b00 1xfifo, 2'b01 2xfifo, 2'b10 4xfifo, 2'b11 reg mode
wire csr_rx_wa_en=rx_adapt_1[0]; // RX word alignment detection enable
wire csr_tx_wm_en=tx_adapt_0[23]; // TX word marker insertion enable
wire [3:0] csr_tx_phcomp_rd_delay=tx_adapt_0[31:28]; //TX phase compensation FIFO read enable delay
wire [3:0] csr_rx_phcomp_rd_delay={1'b0,rx_adapt_0[26:24]}; //RX phase compensation FIFO read enable delay
wire csr_tx_dbi_en=tx_adapt_0[1]; //TX DBI enable
wire csr_rx_dbi_en=rx_adapt_0[1]; //RX DBI enable
wire [1:0] csr_lpbk_mode=tx_adapt_1[15:14]; //2'b00 no loopback. 2'b01 farside loopback. 2'b10 nearside loopback
wire csr_rxswap_en=rx_adapt_0[0]; //Switch Upper/Lower 39 bit in FIFO2x mode in Gen1 mode
wire csr_txswap_en=tx_adapt_0[0]; //Switch Upper/Lower 39 bit in FIFO2x mode in Gen1 mode
wire [4:0] csr_rx_mkbit=rx_adapt_1[7:3]; //Marker bit position of 79:76
wire [4:0] csr_tx_mkbit=tx_adapt_0[20:16]; //Marker bit position of 79:76
assign adpt_rstn = i_conf_done & adapter_rstni;
assign dig_rstb = i_conf_done & (~por);
wire tx_fifo_rstn = (dual_mode_select) ? ms_tx_transfer_en : sl_tx_transfer_en;
wire rx_fifo_rstn = (dual_mode_select) ? ms_rx_transfer_en : sl_rx_transfer_en;
wire [39:0] idat0, idat1, data_out0, data_out1;
genvar i;
generate
for (i=1; i<(DATAWIDTH+1); i=i+1) begin:data_in_gen
assign idat0[i-1] = aibio_dout[2*i-2];
assign idat1[i-1] = aibio_dout[2*i-1];
end
endgenerate
generate
for (i=1; i<(DATAWIDTH+1); i=i+1) begin:data_out_gen
assign aibio_din[2*i-2] = data_out0[i-1];
assign aibio_din[2*i-1] = data_out1[i-1];
end
endgenerate
aib_adapt_2doto aib_adapt (
.atpg_mode(1'b0),
.dual_mode_select(dual_mode_select),
.m_gen2_mode(m_gen2_mode),
.adapt_rstn(adpt_rstn),
.tx_fifo_rstn(tx_fifo_rstn),
.rx_fifo_rstn(rx_fifo_rstn),
.data_out_f(data_out_f), //to mac
.data_out(data_out), //to mac
.data_in(data_in), //from mac
.data_in_f(data_in_f), //from mac
.aibio_dout(aibio_dout[79:0]), //to IO buffer
.aibio_din(aibio_din[79:0]), //from IO buffer
.m_ns_fwd_clk(m_ns_fwd_clk),
.m_ns_rcv_clk(m_ns_rcv_clk),
.m_wr_clk(m_wr_clk),
.m_rd_clk(m_rd_clk),
.m_fs_fwd_clk(m_fs_fwd_clk),
.m_fs_rcv_clk(m_fs_rcv_clk),
.fs_fwd_clk(fs_fwd_clk_tomac),
.fs_rcv_clk(fs_rvc_clk_tomac),
.ns_fwd_clk(ns_fwd_clk_frmac),
.ns_rcv_clk(ns_rvc_clk_frmac),
.m_ns_adapter_rstn(ns_adapter_rstn), //Name is the same as AIB spec
.m_ns_mac_rdy(ns_mac_rdy), //But not consistent with
.m_fs_mac_rdy(fs_mac_rdy), //Other m_* name convention.
.ns_mac_rdyo(rstn_out),
.fs_mac_rdyi(rstn_in),
.ns_adapter_rstno(adapter_rstno),
.adapter_rstni(adapter_rstni),
.conf_done(i_conf_done),
.ms_rx_dcc_dll_lock_req(ms_rx_dcc_dll_lock_req),
.ms_tx_dcc_dll_lock_req(ms_tx_dcc_dll_lock_req),
.sl_tx_dcc_dll_lock_req(sl_tx_dcc_dll_lock_req),
.sl_rx_dcc_dll_lock_req(sl_rx_dcc_dll_lock_req),
.ms_tx_dcc_cal_doneint(ms_tx_dcc_cal_doneint),
.sl_tx_dcc_cal_doneint(sl_tx_dcc_cal_doneint),
.ms_rx_dll_lockint(ms_rx_dll_lockint),
.sl_rx_dll_lockint(sl_rx_dll_lockint),
.ms_tx_transfer_en(ms_tx_transfer_en),
.ms_rx_transfer_en(ms_rx_transfer_en),
.sl_tx_transfer_en(sl_tx_transfer_en),
.sl_rx_transfer_en(sl_rx_transfer_en),
.ms_sideband(sr_ms_tomac),
.sl_sideband(sr_sl_tomac),
.ms_rx_dll_lock_req(ms_rx_dll_lock_req),
.sl_rx_dll_lock_req(sl_rx_dll_lock_req),
.ms_tx_dcc_cal_req(ms_tx_dcc_cal_req),
.sl_tx_dcc_cal_req(sl_tx_dcc_cal_req),
.m_rx_align_done(m_rx_align_done),
.i_osc_clk(i_osc_clk), //from aux channel
.sl_external_cntl_26_0(sl_external_cntl_26_0), //user defined bits 26:0 for slave shift register
.sl_external_cntl_30_28(sl_external_cntl_30_28), //user defined bits 30:28 for slave shift register
.sl_external_cntl_57_32(sl_external_cntl_57_32), //user defined bits 57:32 for slave shift register
.ms_external_cntl_4_0(ms_external_cntl_4_0), //user defined bits 4:0 for master shift register
.ms_external_cntl_65_8(ms_external_cntl_65_8), //user defined bits 65:8 for master shift register
// AIB
.sr_clk_in(sr_clk_in), //SR clock in for master and slave from AIBIO
.srd_in(srd_in),
.srl_in(srl_in),
.sr_clk_out(sr_clk_out),
.std_out(std_out),
.stl_out(stl_out),
// CSR bit
.csr_rx_fifo_mode(csr_rx_fifo_mode),
.csr_tx_fifo_mode(csr_tx_fifo_mode),
.csr_rx_wa_en(csr_rx_wa_en),
.csr_tx_wm_en(csr_tx_wm_en),
.csr_rx_mkbit(csr_rx_mkbit),
.csr_tx_mkbit(csr_tx_mkbit),
.csr_rxswap_en(csr_rxswap_en),
.csr_txswap_en(csr_txswap_en),
.csr_tx_phcomp_rd_delay(csr_tx_phcomp_rd_delay),
.csr_rx_phcomp_rd_delay(csr_rx_phcomp_rd_delay),
.csr_tx_dbi_en(csr_tx_dbi_en),
.csr_rx_dbi_en(csr_rx_dbi_en),
.csr_lpbk_mode(csr_lpbk_mode)
);
aib_ioring #(.DATAWIDTH(DATAWIDTH)) aib_ioring (
.iopad_txdat({ iopad_aib[1:0], iopad_aib[3:2], iopad_aib[5:4], iopad_aib[7:6], iopad_aib[9:8],
iopad_aib[11:10],iopad_aib[13:12],iopad_aib[15:14],iopad_aib[17:16],iopad_aib[19:18],
iopad_aib[21:20],iopad_aib[23:22],iopad_aib[25:24],iopad_aib[27:26],iopad_aib[29:28],
iopad_aib[33:32],iopad_aib[35:34],iopad_aib[37:36],iopad_aib[39:38],iopad_aib[41:40]}),
// .iopad_txdat(iopad_tx),
// .iopad_rxdat(iopad_rx),
.iopad_rxdat({ iopad_aib[100],iopad_aib[101],iopad_aib[98],iopad_aib[99],iopad_aib[96],iopad_aib[97],
iopad_aib[94], iopad_aib[95], iopad_aib[92],iopad_aib[93],iopad_aib[90],iopad_aib[91],
iopad_aib[88], iopad_aib[89], iopad_aib[86],iopad_aib[87],iopad_aib[84],iopad_aib[85],
iopad_aib[82], iopad_aib[83], iopad_aib[80],iopad_aib[81],iopad_aib[78],iopad_aib[79],
iopad_aib[76], iopad_aib[77], iopad_aib[74],iopad_aib[75],iopad_aib[72],iopad_aib[73],
iopad_aib[68], iopad_aib[69], iopad_aib[66],iopad_aib[67],iopad_aib[64],iopad_aib[65],
iopad_aib[62], iopad_aib[63], iopad_aib[60],iopad_aib[61]}),
.iopad_txclkb(iopad_aib[43]), //iopad_ns_rcv_clkb),
.iopad_txclk(iopad_aib[42]), //iopad_ns_rcv_clk),
.iopad_txfck(iopad_aib[30]), //iopad_ns_fwd_clk),
.iopad_txfckb(iopad_aib[31]), //iopad_ns_fwd_clkb),
.iopad_stck(iopad_aib[44]), //iopad_ns_sr_clk),
.iopad_stckb(iopad_aib[45]), //iopad_ns_sr_clkb),
.iopad_stl(iopad_aib[47]), //iopad_ns_sr_load),
.iopad_std(iopad_aib[46]), //iopad_ns_sr_data),
.iopad_rstno(iopad_aib[48]), //iopad_ns_mac_rdy),
.iopad_arstno(iopad_aib[49]), //iopad_ns_adapter_rstn),
.iopad_spareo(iopad_aib[51]), //iopad_spare1),
.iopad_sparee(iopad_aib[50]), //iopad_spare0),
.iopad_rxclkb(iopad_aib[58]), //iopad_fs_rcv_clkb),
.iopad_rxclk(iopad_aib[59]), //iopad_fs_rcv_clk),
.iopad_rxfckb(iopad_aib[70]), //iopad_fs_fwd_clkb),
.iopad_rxfck(iopad_aib[71]), //iopad_fs_fwd_clk),
.iopad_srckb(iopad_aib[56]), //iopad_fs_sr_clkb),
.iopad_srck(iopad_aib[57]), //iopad_fs_sr_clk),
.iopad_srl(iopad_aib[54]), //iopad_fs_sr_load),
.iopad_srd(iopad_aib[55]), //iopad_fs_sr_data),
.iopad_rstni(iopad_aib[53]), //iopad_fs_mac_rdy),
.iopad_arstni(iopad_aib[52]), //iopad_fs_adapter_rstn),
.tx_launch_clk(dcc_clk_out),
// .tx_launch_div2_clk(tx_launch_div2_clk),
.fs_rvc_clk_tomac(fs_rvc_clk_tomac),
.ns_rvc_clk_frmac(ns_rvc_clk_frmac),
// .ns_rvc_div2_clk_frmac(ns_rvc_div2_clk_frmac),
.dig_rstb(dig_rstb), //reset for io
.iddren(csr_iddren),
.idataselb(csr_idataselb),
.itxen(csr_itxen),
.irxen(csr_irxen),
.idat0(idat0[39:0]),
.idat1(idat1[39:0]),
.data_out0(data_out0[39:0]),
.data_out1(data_out1[39:0]),
.clk_dll_out(clk_dll_out),
.clkp(clkp),
.std_out(std_out),
.stl_out(stl_out),
.srd_in(srd_in),
.srl_in(srl_in),
.sr_clk_in(sr_clk_in),
.sr_clk_out(sr_clk_out),
.adapter_rstno(adapter_rstno),
.rstn_out(rstn_out),
.adapter_rstni(adapter_rstni),
.rstn_in(rstn_in),
.jtag_clkdr_in(jtag_clkdr_in),
.scan_out(scan_out),
.jtag_intest(jtag_intest),
.jtag_mode_in(jtag_mode_in),
.jtag_rstb(jtag_rstb),
.jtag_rstb_en(jtag_rstb_en),
.jtag_weakpdn(jtag_weakpdn),
.jtag_weakpu(jtag_weakpu),
.jtag_tx_scanen_in(jtag_tx_scanen_in),
.scan_in(scan_in),
.tx_shift_en(csr_shift_txdat),
.rx_shift_en(csr_shift_rxdat),
.shift_en_txclkb(csr_shift_ns_rcv_clkb),
.shift_en_txfckb(csr_shift_ns_fwd_clkb),
.shift_en_stckb(csr_shift_ns_sr_clkb),
.shift_en_stl(csr_shift_ns_sr_load),
.shift_en_arstno(csr_shift_ns_adapter_rstn),
.shift_en_txclk(csr_shift_ns_rcv_clk),
.shift_en_std(csr_shift_ns_sr_data),
.shift_en_stck(csr_shift_ns_sr_clk),
.shift_en_txfck(csr_shift_ns_fwd_clk),
.shift_en_rstno(csr_shift_ns_mac_rdy),
.shift_en_rxclkb(csr_shift_fs_rcv_clkb),
.shift_en_rxfckb(csr_shift_fs_fwd_clkb),
.shift_en_srckb(csr_shift_fs_sr_clkb),
.shift_en_srl(csr_shift_fs_sr_load),
.shift_en_arstni(csr_shift_fs_adapter_rstn),
.shift_en_rxclk(csr_shift_fs_rcv_clk),
.shift_en_rxfck(csr_shift_fs_fwd_clk),
.shift_en_srck(csr_shift_fs_sr_clk),
.shift_en_srd(csr_shift_fs_sr_data),
.shift_en_rstni(csr_shift_fs_mac_rdy),
.idataselb_stck(1'b1),
.idataselb_std(1'b1),
.idataselb_stl(1'b1),
.idataselb_arstno(1'b1),
.idataselb_rstno(1'b1),
.vccl_aib(vccl_aib),
.vssl_aib(vssl_aib) );
aib_dcc aib_dcc
(
.clk_in(ns_fwd_clk_frmac),
.ms_dcc_cal_req(ms_tx_dcc_cal_req),
.ms_tx_dcc_dll_lock_req(ms_tx_dcc_dll_lock_req),
.sl_dcc_cal_req(sl_tx_dcc_cal_req),
.sl_rx_dcc_dll_lock_req(sl_rx_dcc_dll_lock_req),
.ms_dcc_cal_done(ms_tx_dcc_cal_doneint),
.sl_dcc_cal_done(sl_tx_dcc_cal_doneint),
.clk_out(dcc_clk_out),
.ms_nsl(dual_mode_select),
.atpg_mode(1'b0),
.reset_n(adpt_rstn)
);
dll u_dll
(
.clkp(clkp),
.clkn(~clkp),
.rstb(adpt_rstn), // Hold DDR in reset if SDR Mode
.rx_clk_tree_in(clk_dll_out),
.ms_rx_dll_lock_req(ms_rx_dll_lock_req),
.ms_rx_dll_lock(ms_rx_dll_lockint),
.sl_rx_dll_lock_req(sl_rx_dll_lock_req),
.sl_rx_dll_lock(sl_rx_dll_lockint),
.ms_nsl(dual_mode_select),
.atpg_mode(1'b0)
);
assign fs_fwd_clk_tomac = clk_dll_out;
endmodule // aib_channel |
module aib_adapt_rxchnl(
// Outputs
output wire [319:0] data_out_f,
output wire [79:0] data_out,
output wire align_done,
// Inputs
input wire atpg_mode,
input wire m_gen2_mode,
input wire adapt_rstn,
input wire rx_fifo_rstn,
input wire [79:0] din, //from io buffer
input wire m_rd_clk,
input wire rxfifo_wrclk,
input wire [1:0] r_rx_fifo_mode,
input wire [3:0] r_rx_phcomp_rd_delay,
input wire r_rx_wa_en,
input wire r_rxswap_en,
input wire [4:0] r_rx_mkbit,
input wire r_rx_dbi_en
);
wire [79:0] dbi_dout, rx_fifo_data_out_sel;
wire [319:0] rx_fifo_data_out;
wire rxwr_rstn, rxrd_rstn;
wire rxwr_fifo_rstn, rxrd_fifo_rstn;
assign data_out_f = {rx_fifo_data_out[319:80], rx_fifo_data_out_sel};
assign data_out = dbi_dout;
assign rx_fifo_data_out_sel[79:0] =((r_rx_fifo_mode==2'b01) & r_rxswap_en & ~m_gen2_mode) ? {rx_fifo_data_out[79], rx_fifo_data_out[38:0], rx_fifo_data_out[39], rx_fifo_data_out[78:40]} : rx_fifo_data_out[79:0];
aib_adaptrxdbi_rxdp rx_dbi (
.rst_n(rxwr_rstn),
.clk(rxfifo_wrclk),
.data_in(din),
.dbi_en(r_rx_dbi_en),
.data_out(dbi_dout)
);
aib_adaptrxdp_fifo rxdp_fifo(
// Outputs
.fifo_dout (rx_fifo_data_out),
.fifo_empty (fifo_empty),
.fifo_pempty (fifo_pempty),
.fifo_pfull (fifo_pfull),
.fifo_full (fifo_full_int),
.align_done (align_done),
// Inputs
.wr_rst_n (rxwr_fifo_rstn),
.wr_clk (rxfifo_wrclk),
.fifo_din (dbi_dout),
.rd_rst_n (rxrd_fifo_rstn),
.rd_clk (m_rd_clk),
.r_pempty (5'b0),
.r_pfull (5'b11111),
.r_empty (5'b0),
.r_full (5'b11111),
.m_gen2_mode (m_gen2_mode),
.r_fifo_mode (r_rx_fifo_mode[1:0]),
.r_phcomp_rd_delay (r_rx_phcomp_rd_delay),
.r_mkbit (r_rx_mkbit),
.r_wa_en (r_rx_wa_en));
aib_rstnsync rxwr_rstnsync
(
.clk(rxfifo_wrclk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(rxwr_rstn) // Synchronized reset output
);
aib_rstnsync rxwr_fifo_rstnsync
(
.clk(rxfifo_wrclk),
.i_rst_n(rx_fifo_rstn),
.scan_mode(atpg_mode),
.sync_rst_n(rxwr_fifo_rstn)
);
aib_rstnsync rxrd_rstnsync
(
.clk(m_rd_clk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(rxrd_rstn) // Synchronized reset output
);
aib_rstnsync rxrd_fifo_rstnsync
(
.clk(m_rd_clk),
.i_rst_n(rx_fifo_rstn),
.scan_mode(atpg_mode),
.sync_rst_n(rxrd_fifo_rstn)
);
endmodule |
module aib_adaptrxdp_async_fifo
#(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter AWIDTH = 'd4 // FIFO Depth (address width)
)
(
input wire wr_rst_n, // Write Domain Active low Reset
input wire wr_clk, // Write Domain Clock
input wire wr_en, // Write Data Enable
input wire [DWIDTH-1:0] wr_data, // Write Data In
input wire rd_rst_n, // Read Domain Active low Reset
input wire rd_clk, // Read Domain Clock
input wire rd_en, // Read Data Enable
input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold
input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold
input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold
input wire [AWIDTH-1:0] r_full, // FIFO full threshold
input wire [1:0] r_fifo_mode, // FIFO double write mode
input wire r_wa_en, // word alignment enable
input wire m_gen2_mode, //AIB2.0 Gen2 or Gen1 mode
input wire [4:0] r_mkbit, //Configurable marker bit (79:76 plus 39)
output wire [DWIDTH*4-1:0] rd_data, // Read Data Out
output reg wa_lock,
output reg wr_empty, // FIFO Empty
output reg wr_pempty, // FIFO Partial Empty
output reg wr_full, // FIFO Full
output reg wr_pfull, // FIFO Parial Full
output reg rd_empty, // FIFO Empty
output reg rd_pempty, // FIFO Partial Empty
output reg rd_full, // FIFO Full
output reg rd_pfull // FIFO Partial Full
);
//********************************************************************
// Define Parameters
//********************************************************************
localparam DEPTH = (1<<AWIDTH);
localparam FIFO_1X = 2'b00; //Full rate
localparam FIFO_2X = 2'b01; //Half rate
localparam FIFO_4X = 2'b10; //Quarter Rate
localparam REG_MOD = 2'b11; //REG mode
//********************************************************************
// Define variables
//********************************************************************
wire [AWIDTH-1:0] rd_numdata; // Number of Data available in Read clock
wire [AWIDTH-1:0] wr_numdata; // Number of Data available in Write clock
reg [11:0] wm_history;
wire full_rd_en;
wire full_rd_empty;
wire full_wr_full;
wire [DEPTH-1:0] full_wr_ptr_one_hot;
wire [DEPTH-1:0] full_rd_ptr_one_hot;
wire [AWIDTH-1:0] full_wr_numdata;
wire [AWIDTH-1:0] full_rd_numdata;
wire [AWIDTH-1:0] full_rd_ptr_bin;
wire [AWIDTH-1:0] full_wr_ptr_bin;
wire [DWIDTH*4-1:0] full_wr_data;
reg [DWIDTH-1:0] wd3, wd2, wd1, wd0;
wire wr_full_comb;
wire wr_pfull_comb;
reg [1:0] wr_cnt;
reg full_wr_en;
reg wm_bit;
wire wa_lock_int;
//********************************************************************
// FIFO RAM
//********************************************************************
aib_adaptrxdp_fifo_ram
# (
.DWIDTH (DWIDTH),
.DEPTH (DEPTH))
ram (
.wr_clk (wr_clk),
.wr_rst_n (wr_rst_n),
.wr_en (full_wr_en),
.wr_ptr (full_wr_ptr_one_hot),
.wr_data (full_wr_data),
.rd_ptr (full_rd_ptr_one_hot),
.rd_data (rd_data)
);
//********************************************************************
// FIFO pointers
//********************************************************************
aib_adaptrxdp_fifo_ptr
# (
.AWIDTH (AWIDTH),
.DEPTH (DEPTH))
full_pointers (
.wr_clk (wr_clk),
.wr_rst_n (wr_rst_n),
.rd_clk (rd_clk),
.rd_rst_n (rd_rst_n),
.wr_en (full_wr_en),
.rd_en (full_rd_en),
.rd_empty (full_rd_empty),
.wr_ptr_one_hot (full_wr_ptr_one_hot),
.rd_ptr_one_hot (full_rd_ptr_one_hot),
.rd_ptr_bin (full_rd_ptr_bin),
.wr_ptr_bin (full_wr_ptr_bin),
.wr_numdata (full_wr_numdata),
.rd_numdata (full_rd_numdata)
);
//********************************************************************
// WRITE CLOCK DOMAIN: Generate Fifo Number of Data Present
// using Write Address and Synchronized Read Address
//********************************************************************
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wr_full <= 1'b0;
wr_pfull <= 1'b0;
wr_empty <= 1'b1;
wr_pempty <= 1'b1;
end
else begin
// Generate FIFO Empty
wr_empty <= (wr_numdata <= r_empty) ? 1'b1 : 1'b0;
// Generate FIFO Almost Empty
wr_pempty <= (wr_numdata <= r_pempty) ? 1'b1 : 1'b0;
// Generate FIFO Full
wr_full <= wr_full_comb;
// Generate FIFO Almost Full
wr_pfull <= wr_pfull_comb;
end
end
assign wr_full_comb = (wr_numdata >= r_full) ? 1'b1 : 1'b0;
assign wr_pfull_comb = (wr_numdata >= r_pfull) ? 1'b1 : 1'b0;
always @* begin
casez (r_mkbit)
5'b10000: wm_bit = wr_data[79];
5'b01000: wm_bit = wr_data[78];
5'b00100: wm_bit = wr_data[77];
5'b00010: wm_bit = wr_data[76];
5'b00001: wm_bit = wr_data[39];
default: wm_bit = 1'b0;
endcase
end
assign wa_lock_int = (r_fifo_mode == FIFO_4X) ? ((wm_history==12'h111) ? 1'b1: 1'b0) :
(r_fifo_mode == FIFO_2X) ? ((wm_history[5:0]==6'h15)? 1'b1: 1'b0):
1'b1;
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wr_cnt <= 2'b00;
wm_history <= 12'h0;
wa_lock <= 1'b0;
end
else begin
if (r_wa_en) begin
wa_lock <= wa_lock_int | wa_lock;
wm_history <= {wm_history[10:0], wm_bit};
if (wr_en) wr_cnt <= wr_cnt + 1'b1;;
end
end
end
always @(posedge wr_clk) begin
case (r_fifo_mode)
FIFO_1X: begin
wd0 <= wr_data;
{wd1,wd2,wd3} <= 240'h0;
end
REG_MOD: begin
wd0 <= wr_data;
{wd1,wd2,wd3} <= 240'h0;
end
FIFO_2X: case (wr_cnt[0])
1'b0: begin
if (m_gen2_mode) wd0 <= wr_data;
else wd0[39:0] <= wr_data[39:0];
end
1'b1: begin
if (m_gen2_mode) wd1 <= wr_data;
else wd0[79:40] <= wr_data[39:0];
end
endcase
FIFO_4X: case(wr_cnt)
2'b00: wd0 <= wr_data;
2'b01: wd1 <= wr_data;
2'b10: wd2 <= wr_data;
2'b11: wd3 <= wr_data;
endcase
endcase
end
assign full_wr_data = {wd3, wd2, wd1, wd0};
always @(posedge wr_clk) begin
if (r_fifo_mode == FIFO_4X) full_wr_en <= wr_en & (wr_cnt == 2'b11);
else if (r_fifo_mode == FIFO_2X) full_wr_en <= wr_en & (wr_cnt[0] == 1'b1);
else full_wr_en <= wr_en;
end
//********************************************************************
// READ CLOCK DOMAIN: Generate Fifo Number of Data Present
// using Read Address and Synchronized Write Address
//********************************************************************
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
rd_empty <= 1'b1;
rd_pempty <= 1'b1;
rd_full <= 1'b0;
rd_pfull <= 1'b0;
end
else begin
// Generate FIFO Empty
rd_empty <= (rd_numdata <= r_empty) ? 1'b1 : 1'b0;
// Generate FIFO Almost Empty
rd_pempty <= (rd_numdata <= r_pempty) ? 1'b1 : 1'b0;
// Generate FIFO Full
rd_full <= (rd_numdata >= r_full) ? 1'b1 : 1'b0;
// Generate FIFO Almost Full
rd_pfull <= (rd_numdata >= r_pfull) ? 1'b1 : 1'b0;
end
end
//********************************************************************
// FIFO Mapping
//********************************************************************
assign full_rd_en = rd_en;
assign full_rd_empty = rd_empty;
assign full_wr_full = wr_full;
assign wr_numdata = full_wr_numdata;
assign rd_numdata = full_rd_numdata;
endmodule // aib_adaptrxdp_async_fifo |
module aib_adapttxdp_fifo
#(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter AWIDTH = 'd5 // FIFO Depth (address width)
)
(
input wire wr_rst_n, // Write Domain Active low Reset
input wire wr_clk, // Write Domain Clock
input wire m_gen2_mode,
input wire [4*DWIDTH-1:0] data_in, // Write Data In
input wire rd_rst_n, // Read Domain Active low Reset
input wire rd_clk, // Read Domain Clock
input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold
input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold
input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold
input wire [AWIDTH-1:0] r_full, // FIFO full threshold
input wire r_wm_en, // mark enable
input wire [4:0] r_mkbit, // Configurable marker bit
input wire [1:0] r_fifo_mode, // FIFO Mode: 4:1 2:1 1:1 Reg mode
input wire [3:0] r_phcomp_rd_delay, // Programmable read and write pointer gap in phase comp mode
output wire [DWIDTH-1:0] fifo_dout, // Read Data Out
output wire fifo_empty, // FIFO empty
output wire fifo_pempty, // FIFO partial empty
output wire fifo_pfull, // FIFO partial full
output wire fifo_full // FIFO full
);
//********************************************************************
// Define Parameters
//********************************************************************
localparam FIFO_DATA_DEFAULT = 320'd0;
localparam ASYNC_FIFO_AWIDTH = 4;
localparam FIFO_1X = 2'b00; //Full rate
localparam FIFO_2X = 2'b01; //Half rate
localparam FIFO_4X = 2'b10; //Quarter Rate
localparam REG_MOD = 2'b11; //REG mode
//********************************************************************
// Define variables
//********************************************************************
wire register_mode;
wire phcomp_mode;
wire phcomp_rden_int;
wire phcomp_wren;
reg phcomp_wren_d0;
wire phcomp_wren_sync2;
reg phcomp_wren_sync3;
reg phcomp_wren_sync4;
reg phcomp_wren_sync5;
reg phcomp_wren_sync6;
wire [DWIDTH-1:0] fifo_out;
reg [DWIDTH-1:0] data_out_int;
reg [DWIDTH*4-1:0] wr_data;
//wire phcomp_mode1x;
wire wr_en_int;
wire rd_en_int;
wire wr_empty;
wire wr_pempty;
wire wr_full;
wire wr_pfull;
wire rd_empty;
wire rd_pempty;
wire rd_full;
wire rd_pfull;
wire wr_addr_msb;
wire rd_addr_msb;
wire phcomp_wren_sync;
reg phcomp_wren_d1;
reg phcomp_wren_d2;
// FIFO mode decode
assign register_mode = (r_fifo_mode == REG_MOD);
assign phcomp_mode = ~ register_mode;
always @ * begin
if (r_wm_en) begin
if (r_fifo_mode == FIFO_4X)
if (r_mkbit[4])
wr_data ={{ 1'b1, data_in[318:240]},
{ 1'b0, data_in[238:160]},
{ 1'b0, data_in[158:80]},
{ 1'b0, data_in[78:0]}}; //bit 79
else if (r_mkbit[3])
wr_data ={{data_in[319], 1'b1, data_in[317:240]},
{data_in[239], 1'b0, data_in[237:160]},
{data_in[159], 1'b0, data_in[157:80]},
{data_in[79], 1'b0, data_in[77:0]}}; //bit 78
else if (r_mkbit[2])
wr_data ={{data_in[319:318], 1'b1, data_in[316:240]},
{data_in[239:238], 1'b0, data_in[236:160]},
{data_in[159:158], 1'b0, data_in[156:80]},
{data_in[79:78], 1'b0, data_in[76:0]}}; //bit 77
else if (r_mkbit[1])
wr_data ={{data_in[319:317], 1'b1, data_in[315:240]},
{data_in[239:237], 1'b0, data_in[235:160]},
{data_in[159:157], 1'b0, data_in[155:80]},
{data_in[79:77], 1'b0, data_in[75:0]}}; //bit 76
else wr_data = data_in;
else if (r_fifo_mode == FIFO_2X)
if (r_mkbit[4])
wr_data ={ 160'h0,
{ 1'b1, data_in[158:80]},
{ 1'b0, data_in[78:0]}};
else if (r_mkbit[3])
wr_data ={ 160'h0,
{data_in[159], 1'b1, data_in[157:80]},
{data_in[79], 1'b0, data_in[77:0]}};
else if (r_mkbit[2])
wr_data ={ 160'h0,
{data_in[159:158], 1'b1, data_in[156:80]},
{data_in[79:78], 1'b0, data_in[76:0]}};
else if (r_mkbit[1])
wr_data ={ 160'h0,
{data_in[159:157], 1'b1, data_in[155:80]},
{data_in[79:77], 1'b0, data_in[75:0]}};
else if (r_mkbit[0] & ~m_gen2_mode)
wr_data ={ 160'h0,
{40'h0, 1'b1, data_in[78:40]},
{40'h0, 1'b0, data_in[38:0]}};
else
wr_data = data_in;
else
wr_data = data_in;
end else begin
if ((r_fifo_mode == FIFO_2X) & ~m_gen2_mode)
wr_data ={ 160'h0,
{40'h0, data_in[79:40]},
{40'h0, data_in[39:0]}};
else
wr_data = data_in;
end
end
//********************************************************************
// Instantiate the Async FIFO
//********************************************************************
aib_adapttxdp_async_fifo
#(
.DWIDTH (DWIDTH), // FIFO Input data width
.AWIDTH (ASYNC_FIFO_AWIDTH)
)
adapt_txdp_async_fifo (
.wr_rst_n (wr_rst_n), // Write Domain Active low Reset
.wr_clk (wr_clk), // Write Domain Clock
.wr_en (wr_en_int), // Write Data Enable
.wr_data (wr_data), // Write Data In
.rd_rst_n (rd_rst_n), // Read Domain Active low Reset
.rd_clk (rd_clk), // Read Domain Clock
.rd_en (rd_en_int), // Read Data Enable
.rd_data (fifo_out), // Read Data Out
.r_pempty (r_pempty[ASYNC_FIFO_AWIDTH-1:0]), // FIFO partially empty threshold
.r_pfull (r_pfull[ASYNC_FIFO_AWIDTH-1:0]), // FIFO partially full threshold
.r_empty (r_empty[ASYNC_FIFO_AWIDTH-1:0]), // FIFO empty threshold
.r_full (r_full[ASYNC_FIFO_AWIDTH-1:0]), // FIFO full threshold
.r_fifo_mode (r_fifo_mode),
.wr_empty (wr_empty), // FIFO Empty
.wr_pempty (wr_pempty), // FIFO Partial Empty
.wr_full (wr_full), // FIFO Full
.wr_pfull (wr_pfull), // FIFO Parial Full
.rd_empty (rd_empty), // FIFO Empty
.rd_pempty (rd_pempty), // FIFO Partial Empty
.rd_full (rd_full), // FIFO Full
.rd_pfull (rd_pfull) // FIFO Partial Full
);
//********************************************************************
// Read Write logic
//********************************************************************
assign wr_en_int = phcomp_mode & phcomp_wren; // Phase Comp Indiviual mode
assign rd_en_int = phcomp_mode & phcomp_rden_int; // Phase Comp Indiviual mode
// Output Register and Bypass Logic
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
data_out_int <= FIFO_DATA_DEFAULT;
end
else if (phcomp_mode && ~rd_en_int) begin
data_out_int <= FIFO_DATA_DEFAULT;
end
else begin
data_out_int <= rd_en_int ? fifo_out: data_out_int;
end
end
assign fifo_dout = data_out_int;
//********************************************************************
// FIFO bonding logic
//********************************************************************
// Phase Comp FIFO mode Write/Read enable logic generation
// Write Enable
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
phcomp_wren_d0 <= 1'b0;
phcomp_wren_d1 <= 1'b0;
phcomp_wren_d2 <= 1'b0;
end
else begin
phcomp_wren_d0 <= 1'b1; // Indv: 1, Bonding: goes high and stays high
phcomp_wren_d1 <= phcomp_wren_d0;
phcomp_wren_d2 <= phcomp_wren_d1;
end
end
assign phcomp_wren = phcomp_wren_d2;
// phcomp_wren Synchronizer
aib_bitsync bitsync2_phcomp_wren
(
.clk (rd_clk),
.rst_n (rd_rst_n),
.data_in (phcomp_wren),
.data_out (phcomp_wren_sync2)
);
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
phcomp_wren_sync3 <= 1'b0;
phcomp_wren_sync4 <= 1'b0;
phcomp_wren_sync5 <= 1'b0;
phcomp_wren_sync6 <= 1'b0;
end
else begin
phcomp_wren_sync3 <= phcomp_wren_sync2;
phcomp_wren_sync4 <= phcomp_wren_sync3;
phcomp_wren_sync5 <= phcomp_wren_sync4;
phcomp_wren_sync6 <= phcomp_wren_sync5;
end
end
// Read Enable
assign phcomp_wren_sync = (r_phcomp_rd_delay == 4'b0110) ? phcomp_wren_sync6 :
(r_phcomp_rd_delay == 4'b0101) ? phcomp_wren_sync5 :
(r_phcomp_rd_delay == 4'b0100) ? phcomp_wren_sync4 :
(r_phcomp_rd_delay == 4'b0011) ? phcomp_wren_sync3 : phcomp_wren_sync2;
assign phcomp_rden = phcomp_wren_sync;
assign phcomp_rden_int = phcomp_rden;
// Sync to write/read clock domain
assign fifo_full = wr_full;
assign fifo_pfull = wr_pfull;
assign fifo_empty = rd_empty;
assign fifo_pempty = rd_pempty;
endmodule |
module aib_adapttxdp_fifo_ram
#(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter DEPTH = 'd16 // FIFO Depth
)
(
input wire wr_clk, // Write Domain Clock
input wire wr_en, // write enable
input wire wr_rst_n, // Write Domain Reset
input wire [DEPTH-1:0] wr_ptr, // Write Pointer
input wire [DWIDTH*4-1:0] wr_data, // Write Data In
input wire [DEPTH-1:0] rd_ptr, // Read Pointer
output reg [DWIDTH*4-1:0] rd_data // Read Data
);
//********************************************************************
// Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
//********************************************************************
integer m;
integer i;
reg [DWIDTH*4-1:0] fifo_mem [DEPTH-1:0];
always @(negedge wr_rst_n or posedge wr_clk) begin
if (~wr_rst_n) begin
for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
fifo_mem[m] <= 'd0;
end
else if (wr_en) begin
for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
if (wr_ptr[m]) begin
fifo_mem[m] <= wr_data;
end
end
end
end
//assign rd_data = fifo_mem[rd_ptr];
always @ *
begin: data_out
rd_data = fifo_mem[0];
for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
if (rd_ptr[i]) begin
rd_data = fifo_mem[i];
end
end
end
endmodule |
module aib_avmm_io_csr (
output reg [31:0] redund_0,
output reg [31:0] redund_1,
output reg [31:0] redund_2,
output reg [31:0] redund_3,
//Bus Interface
input clk,
input reset,
input [31:0] writedata,
input read,
input write,
input [3:0] byteenable,
output reg [31:0] readdata,
output reg readdatavalid,
input [6:0] address
);
wire reset_n = !reset;
// Protocol management
// combinatorial read data signal declaration
reg [31:0] rdata_comb;
// synchronous process for the read
always @(negedge reset_n ,posedge clk)
if (!reset_n) readdata[31:0] <= 32'h0; else readdata[31:0] <= rdata_comb[31:0];
// read data is always returned on the next cycle
always @(negedge reset_n , posedge clk)
if (!reset_n) readdatavalid <= 1'b0; else readdatavalid <= read;
//
// Protocol specific assignment to inside signals
//
wire we = write;
wire re = read;
wire [6:0] addr = address[6:0];
wire [31:0] din = writedata [31:0];
// A write byte enable for each register
wire [3:0] we_redund_0 = we & (addr[6:0] == 7'h20) ? byteenable[3:0] : {4{1'b0}};
wire [3:0] we_redund_1 = we & (addr[6:0] == 7'h24) ? byteenable[3:0] : {4{1'b0}};
wire [3:0] we_redund_2 = we & (addr[6:0] == 7'h28) ? byteenable[3:0] : {4{1'b0}};
wire [3:0] we_redund_3 = we & (addr[6:0] == 7'h1c) ? byteenable[3:0] : {4{1'b0}};
// A read byte enable for each register
always @( negedge reset_n, posedge clk)
if (!reset_n) begin
redund_0[31:0] <= 32'h00000000;
end
else begin
if (we_redund_0[0]) begin
redund_0[7:0] <= din[7:0];
end
if (we_redund_0[1]) begin
redund_0[15:8] <= din[15:8];
end
if (we_redund_0[2]) begin
redund_0[23:16] <= din[23:16];
end
if (we_redund_0[3]) begin
redund_0[31:24] <= din[31:24];
end
end
always @( negedge reset_n, posedge clk)
if (!reset_n) begin
redund_1[31:0]<= 32'h00000000;
end
else begin
if (we_redund_1[0]) begin
redund_1[7:0] <= din[7:0];
end
if (we_redund_1[1]) begin
redund_1[15:8] <= din[15:8];
end
if (we_redund_1[2]) begin
redund_1[23:16] <= din[23:16];
end
if (we_redund_1[3]) begin
redund_1[31:24] <= din[31:24];
end
end
always @( negedge reset_n, posedge clk)
if (!reset_n) begin
redund_2[31:0] <= 32'h00000000;
end
else begin
if (we_redund_2[0]) begin
redund_2[7:0] <= din[7:0];
end
if (we_redund_2[1]) begin
redund_2[15:8] <= din[15:8];
end
if (we_redund_2[2]) begin
redund_2[23:16] <= din[23:16];
end
if (we_redund_2[3]) begin
redund_2[31:24] <= din[31:24];
end
end
always @( negedge reset_n, posedge clk)
if (!reset_n) begin
redund_3[31:0]<= 32'h00000000;
end
else begin
if (we_redund_3[0]) begin
redund_3[7:0] <= din[7:0];
end
if (we_redund_3[1]) begin
redund_3[15:8] <= din[15:8];
end
if (we_redund_3[2]) begin
redund_3[23:16] <= din[23:16];
end
if (we_redund_3[3]) begin
redund_3[31:24] <= din[31:24];
end
end
// read process
always @ (*)
begin
rdata_comb = 32'h0;
if(re) begin
case (addr)
7'h20 : begin
rdata_comb = redund_0;
end
7'h24 : begin
rdata_comb = redund_1;
end
7'h28 : begin
rdata_comb = redund_2;
end
7'h1c : begin
rdata_comb = redund_3;
end
default : begin
rdata_comb = 32'h00000000;
end
endcase
end
end
endmodule |
module aib_adaptrxdp_fifo
#(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter AWIDTH = 'd5 // FIFO Depth (address width)
)
(
input wire wr_rst_n, // Write Domain Active low Reset
input wire wr_clk, // Write Domain Clock
input wire [DWIDTH-1:0] fifo_din, // Write Data In
input wire rd_rst_n, // Read Domain Active low Reset
input wire rd_clk, // Read Domain Clock
input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold
input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold
input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold
input wire [AWIDTH-1:0] r_full, // FIFO full threshold
input wire m_gen2_mode,
input wire [1:0] r_fifo_mode, // FIFO Mode: Phase-comp, BaseR RM, Interlaken, Register Mode
input wire [3:0] r_phcomp_rd_delay, // Programmable read and write pointer gap in phase comp mode
input wire r_wa_en, // Word-align enable
input wire [4:0] r_mkbit, // Configurable marker bit
output wire [4*DWIDTH-1:0] fifo_dout, // Read Data Out
output wire fifo_empty, // FIFO empty
output wire fifo_pempty, // FIFO partial empty
output wire fifo_pfull, // FIFO partial full
output wire fifo_full, // FIFO full
output wire align_done
);
//********************************************************************
// Define Parameters
//********************************************************************
localparam ASYNC_FIFO_AWIDTH = 4;
localparam FIFO_1X = 2'b00; //Full rate
localparam FIFO_2X = 2'b01; //Half rate
localparam FIFO_4X = 2'b10; //Quarter Rate
localparam REG_MOD = 2'b11; //REG mode
//********************************************************************
// Define variables
//********************************************************************
wire phcomp_mode;
wire phcomp_rden_int;
reg phcomp_wren_d0;
wire phcomp_wren_sync2;
wire defult_wren_sync;
reg phcomp_wren_sync3;
reg phcomp_wren_sync4;
reg phcomp_wren_sync5;
reg phcomp_wren_sync6;
reg phcomp_wren_sync7;
reg phcomp_wren_sync8;
wire [4*DWIDTH-1:0] fifo_out;
wire [4*DWIDTH-1:0] data_in;
reg [4*DWIDTH-1:0] data_out;
wire rd_en_int;
wire wr_empty;
wire wr_pempty;
wire wr_full;
wire wr_pfull;
wire rd_empty;
wire rd_pempty;
wire rd_full;
wire rd_pfull;
wire wa_lock;
wire phcomp_wren, phcomp_wren_sync;
reg phcomp_wren_d1;
reg phcomp_wren_d2;
wire phcomp_rden;
reg rd_en_reg;
// FIFO mode decode
assign phcomp_mode = (r_fifo_mode != REG_MOD); //2'b11 is reg_mod
assign align_done = rd_en_reg;
//********************************************************************
// Instantiate the Async FIFO
//********************************************************************
aib_adaptrxdp_async_fifo
#(
.DWIDTH (DWIDTH), // FIFO Input data width
.AWIDTH (ASYNC_FIFO_AWIDTH) // Reduce depth from 32 to 16 to save power
)
rx_datapath_async_fifo
(
.wr_rst_n (wr_rst_n), // Write Domain Active low Reset
.wr_clk (wr_clk), // Write Domain Clock
.wr_en (wr_en_int), // Write Data Enable
.wr_data (fifo_din), // Write Data In
.rd_rst_n (rd_rst_n), // Read Domain Active low Reset
.rd_clk (rd_clk), // Read Domain Clock
.rd_en (rd_en_int), // Read Data Enable
.rd_data (fifo_out), // Read Data Out
.r_wa_en (r_wa_en),
.wa_lock (wa_lock),
.r_pempty (r_pempty[ASYNC_FIFO_AWIDTH-1:0]), // FIFO partially empty threshold
.r_pfull (r_pfull[ASYNC_FIFO_AWIDTH-1:0]), // FIFO partially full threshold
.r_empty (r_empty[ASYNC_FIFO_AWIDTH-1:0]), // FIFO empty threshold
.r_full (r_full[ASYNC_FIFO_AWIDTH-1:0]), // FIFO full threshold
.r_fifo_mode (r_fifo_mode),
.m_gen2_mode (m_gen2_mode),
.r_mkbit (r_mkbit),
.wr_empty (wr_empty), // FIFO Empty
.wr_pempty (wr_pempty), // FIFO Partial Empty
.wr_full (wr_full), // FIFO Full
.wr_pfull (wr_pfull), // FIFO Parial Full
.rd_empty (rd_empty), // FIFO Empty
.rd_pempty (rd_pempty), // FIFO Partial Empty
.rd_full (rd_full), // FIFO Full
.rd_pfull (rd_pfull) // FIFO Partial Full
);
//********************************************************************
// Read Write logic
//********************************************************************
assign wr_en_int = phcomp_mode & phcomp_wren;
assign rd_en_int = phcomp_mode & phcomp_rden_int;
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
data_out <= 320'h0;
end
else if (phcomp_mode && ~rd_en_int) begin
data_out <= 320'h0;
end
else begin
data_out <= rd_en_int ? fifo_out : data_out;
end
end
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
rd_en_reg <= 1'b0;
end
else begin
rd_en_reg <= rd_en_int;
end
end
// Phase Comp FIFO mode Write/Read enable logic generation
// Write Enable
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
phcomp_wren_d0 <= 1'b0;
phcomp_wren_d1 <= 1'b0;
phcomp_wren_d2 <= 1'b0;
end
else begin
phcomp_wren_d0 <= (~r_wa_en || wa_lock) || phcomp_wren_d0;
phcomp_wren_d1 <= phcomp_wren_d0;
phcomp_wren_d2 <= phcomp_wren_d1;
end
end
assign phcomp_wren = phcomp_wren_d2;
// phcomp_wren Synchronizer
aib_bitsync bitsync2_phcomp_wren
(
.clk (rd_clk),
.rst_n (rd_rst_n),
.data_in (phcomp_wren),
.data_out (phcomp_wren_sync2)
);
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
phcomp_wren_sync3 <= 1'b0;
phcomp_wren_sync4 <= 1'b0;
phcomp_wren_sync5 <= 1'b0;
phcomp_wren_sync6 <= 1'b0;
phcomp_wren_sync7 <= 1'b0;
phcomp_wren_sync8 <= 1'b0;
end
else begin
phcomp_wren_sync3 <= phcomp_wren_sync2;
phcomp_wren_sync4 <= phcomp_wren_sync3;
phcomp_wren_sync5 <= phcomp_wren_sync4;
phcomp_wren_sync6 <= phcomp_wren_sync5;
phcomp_wren_sync7 <= phcomp_wren_sync6;
phcomp_wren_sync8 <= phcomp_wren_sync7;
end
end
// Read Enable
// Add safe guard for FIFO_4X mode in case user put wrong configuration value.
wire [3:0] r_phcomp_dly_mod;
assign r_phcomp_dly_mod = ((r_fifo_mode == FIFO_4X) && (r_phcomp_rd_delay < 4'b0110)) ? 4'b0110: r_phcomp_rd_delay;
assign phcomp_wren_sync = (r_phcomp_dly_mod == 4'b0111) ? phcomp_wren_sync7 :
(r_phcomp_dly_mod == 4'b0110) ? phcomp_wren_sync6 :
(r_phcomp_dly_mod == 4'b0101) ? phcomp_wren_sync5 :
(r_phcomp_dly_mod == 4'b0100) ? phcomp_wren_sync4 :
(r_phcomp_dly_mod == 4'b0011) ? phcomp_wren_sync3 : phcomp_wren_sync2;
assign phcomp_rden = phcomp_wren_sync;
// Phase comp mode, FIFO read enable signal asserts when rd_val is high
assign phcomp_rden_int = phcomp_rden;
assign fifo_empty = rd_empty;
assign fifo_pempty = rd_pempty;
assign fifo_full = wr_full;
assign fifo_pfull = wr_pfull;
assign fifo_dout[319:0] = data_out[319:0];
wire [79:0] f3, f2, f1, f0;
assign {f3, f2, f1, f0} = data_out;
endmodule |
module aib_adapt_2doto (
input dual_mode_select,
input m_gen2_mode,
input atpg_mode,
input adapt_rstn,
input tx_fifo_rstn,
input rx_fifo_rstn,
//MAC data interface
output [319:0] data_out_f, //FIFO read data to mac
output [79:0] data_out, //register mode data to mac
input [319:0] data_in_f, //from mac, FIFO write data
input [79:0] data_in,
input m_ns_fwd_clk,
input m_ns_rcv_clk,
input m_wr_clk,
input m_rd_clk,
output m_fs_fwd_clk,
output m_fs_rcv_clk,
//AIB IO data interface
output [79:0] aibio_dout, //to IO buffer
input [79:0] aibio_din, //from IO buffer
input fs_fwd_clk,
input fs_rcv_clk,
output ns_fwd_clk, //send to dcc
output ns_rcv_clk,
//MAC other signal interface
input m_ns_adapter_rstn,
input m_ns_mac_rdy,
output m_fs_mac_rdy,
//AIB IO other signal interface
output ns_mac_rdyo,
input fs_mac_rdyi,
output ns_adapter_rstno,
input adapter_rstni,
//Control and status from MAC interface
input conf_done, // was i_adpt_hard_rst_n
input ms_rx_dcc_dll_lock_req,
input ms_tx_dcc_dll_lock_req,
input sl_tx_dcc_dll_lock_req,
input sl_rx_dcc_dll_lock_req,
input ms_tx_dcc_cal_doneint,
input sl_tx_dcc_cal_doneint,
input ms_rx_dll_lockint,
input sl_rx_dll_lockint,
output ms_tx_transfer_en,
output ms_rx_transfer_en,
output sl_tx_transfer_en,
output sl_rx_transfer_en,
//Interface to DCC and DLL module
output ms_rx_dll_lock_req,
output sl_rx_dll_lock_req,
output ms_tx_dcc_cal_req,
output sl_tx_dcc_cal_req,
output [80:0] ms_sideband,
output [72:0] sl_sideband,
output m_rx_align_done,
//SR interface with AIB IO
input wire sr_clk_in,
input wire srd_in,
input wire srl_in,
output sr_clk_out,
output std_out,
output stl_out,
//From AUX channel
input i_osc_clk, //from aux channel
//Sideband user interface
input [26:0] sl_external_cntl_26_0, //user defined bits 26:0 for slave shift register
input [2:0] sl_external_cntl_30_28, //user defined bits 30:28 for slave shift register
input [25:0] sl_external_cntl_57_32, //user defined bits 57:32 for slave shift register
input [4:0] ms_external_cntl_4_0, //user defined bits 4:0 for master shift register
input [57:0] ms_external_cntl_65_8, //user defined bits 65:8 for master shift register
// CSR bit
input [1:0] csr_rx_fifo_mode,
input [1:0] csr_tx_fifo_mode,
input csr_rx_wa_en,
input csr_tx_wm_en,
input [4:0] csr_rx_mkbit,
input [4:0] csr_tx_mkbit,
input csr_txswap_en,
input csr_rxswap_en,
input [3:0] csr_tx_phcomp_rd_delay,
input [3:0] csr_rx_phcomp_rd_delay,
input csr_tx_dbi_en,
input csr_rx_dbi_en,
input [1:0] csr_lpbk_mode
);
wire is_master, is_slave;
wire dig_rstb;
wire ms_osc_transfer_en;
wire ms_osc_transfer_alive;
wire ms_rx_async_rst;
wire ms_tx_async_rst;
wire sl_osc_transfer_en;
wire sl_rx_async_rst;
wire sr_ms_load_out;
wire adpt_rstn;
wire sr_ms_data_out;
wire [80:0] ms_data_fr_core, ms_data_to_core;
wire [72:0] sl_data_fr_core, sl_data_to_core;
wire sr_sl_data_out;
wire sr_sl_load_out;
wire dcc_clk_out;
//
wire [319:0] tx_adapt_din, rx_adapt_dout;
wire [79:0] tx_adapt_dout, rx_adapt_din;
wire [1:0] r_rx_fifo_mode;
wire [1:0] r_tx_fifo_mode;
wire sr_sl_clk_out;
wire ms_tx_transfer_en_m, ms_rx_transfer_en_m;
wire sl_tx_transfer_en_s, sl_rx_transfer_en_s;
wire ms_rx_dll_lock, sl_rx_dll_lock;
wire ms_tx_dcc_cal_done, sl_tx_dcc_cal_done;
reg [79:0] data_in_r, data_out_r;
reg [319:0] data_in_f_r, data_out_f_r;
wire [79:0] data_out_int;
wire [319:0] data_out_f_int;
//////////////////////////////////////////////////////////////////
// Flop in and Flop out reg mode data and FIFO mode data
//////////////////////////////////////////////////////////////////
assign data_out = data_out_r;
assign data_out_f = data_out_f_r;
always @(posedge m_ns_fwd_clk) data_in_r <= data_in;
always @(posedge m_wr_clk) data_in_f_r <= data_in_f;
always @(posedge m_fs_fwd_clk) data_out_r <= data_out_int;
always @(posedge m_rd_clk) data_out_f_r <= data_out_f_int;
///////////////////////////////////////////////////////////////////
// Control and status relate to calibration state machine
///////////////////////////////////////////////////////////////////
assign ms_tx_transfer_en = dual_mode_select ? ms_tx_transfer_en_m : ms_data_to_core[78];
assign ms_rx_transfer_en = dual_mode_select ? ms_rx_transfer_en_m : ms_data_to_core[75];
assign sl_tx_transfer_en = !dual_mode_select ? sl_tx_transfer_en_s : sl_data_to_core[64];
assign sl_rx_transfer_en = !dual_mode_select ? sl_rx_transfer_en_s : sl_data_to_core[70];
assign m_fs_rcv_clk = fs_rcv_clk;
assign ns_rcv_clk = m_ns_rcv_clk;
assign m_fs_mac_rdy = fs_mac_rdyi;
assign ms_sideband[80:0] = ms_data_to_core[80:0];
assign sl_sideband[72:0] = sl_data_to_core[72:0];
assign is_master = (dual_mode_select == 1'b1) ? 1'b1 : 1'b0;
assign is_slave = !is_master;
assign tx_dcc_cal_req = dual_mode_select ? ms_tx_dcc_cal_req : sl_tx_dcc_cal_req;
assign rx_dll_lock_req = dual_mode_select ? ms_rx_dll_lock_req : sl_rx_dll_lock_req;
assign adpt_rstn = m_ns_adapter_rstn & adapter_rstni;
assign dig_rstb = conf_done;
assign sr_clk_out = is_master ? i_osc_clk : sr_sl_clk_out;
assign std_out = is_master ? sr_ms_data_out : sr_sl_data_out;
assign stl_out = is_master ? sr_ms_load_out : sr_sl_load_out;
assign ns_adapter_rstno = m_ns_adapter_rstn;
assign ns_mac_rdyo = m_ns_mac_rdy;
assign ms_data_fr_core[80:0] = {ms_osc_transfer_en,1'b1,ms_tx_transfer_en_m,2'b11,ms_rx_transfer_en_m,ms_rx_dll_lock, 5'b11111,ms_tx_dcc_cal_done,1'b0,1'b1, ms_external_cntl_65_8[57:0], 1'b1, 1'b0, 1'b1, ms_external_cntl_4_0[4:0]};
assign sl_data_fr_core[72:0] = {sl_osc_transfer_en,1'b0,sl_rx_transfer_en_s,sl_rx_dcc_dll_lock_req, sl_rx_dll_lock,3'b0,sl_tx_transfer_en_s,sl_tx_dcc_dll_lock_req, 1'b0,1'b0,1'b1,1'b0, 1'b1, sl_external_cntl_57_32[25:0], sl_tx_dcc_cal_done, sl_external_cntl_30_28[2:0], 1'b0, sl_external_cntl_26_0[26:0]};
///////////////////////////////////////////////////////////////////
// Loopback
///////////////////////////////////////////////////////////////////
wire f_lpbk, n_lpbk;
localparam FARSIDE_LPBK = 2'b01;
localparam NEARSIDE_LPBK = 2'b10;
assign f_lpbk = (csr_lpbk_mode== FARSIDE_LPBK);
assign n_lpbk = (csr_lpbk_mode== NEARSIDE_LPBK);
//Farside Loopback: Farside -> AIB IO RX -> AIB Adaptor RX out to TX Adaptor in
assign tx_adapt_din = f_lpbk ? rx_adapt_dout : data_in_f_r;
assign tx_wr_clk = f_lpbk ? m_rd_clk : m_wr_clk;
assign tx_rd_clk = f_lpbk ? fs_fwd_clk : m_ns_fwd_clk; //for read clock and register mode forward clock
assign ns_fwd_clk = tx_rd_clk; //Send to dcc block.
//Nearside Loopback: TX MAC -> TX Adapter out -> RX Adapter in -> RX MAC
assign rx_adapt_din = n_lpbk ? tx_adapt_dout : aibio_din;
assign rx_wr_clk = n_lpbk ? m_ns_fwd_clk : fs_fwd_clk;
assign m_fs_fwd_clk = rx_wr_clk;
assign data_out_f_int = rx_adapt_dout;
aib_adapt_rxchnl aib_adapt_rxchnl(
// Outputs
.data_out_f(rx_adapt_dout[319:0]),
.data_out(data_out_int),
.align_done(m_rx_align_done),
// Inputs
.din(rx_adapt_din), //from io buffer or near side loopback
.rxfifo_wrclk(rx_wr_clk),
.m_rd_clk(m_rd_clk),
.atpg_mode(atpg_mode),
.m_gen2_mode(m_gen2_mode),
.adapt_rstn(adapt_rstn),
.rx_fifo_rstn(rx_fifo_rstn),
.r_rx_fifo_mode(csr_rx_fifo_mode),
.r_rx_phcomp_rd_delay(csr_rx_phcomp_rd_delay),
.r_rx_wa_en(csr_rx_wa_en),
.r_rx_mkbit(csr_rx_mkbit),
.r_rxswap_en(csr_rxswap_en),
.r_rx_dbi_en(csr_rx_dbi_en)
);
assign aibio_dout = tx_adapt_dout;
aib_adapt_txchnl aib_adapt_txchnl(
// Outputs
.dout(tx_adapt_dout[79:0]),
//.ns_fwd_clk(ns_fwd_clk),
// Inputs
.atpg_mode(atpg_mode),
.m_gen2_mode(m_gen2_mode),
.adapt_rstn(adpt_rstn),
.tx_fifo_rstn(tx_fifo_rstn),
.m_wr_clk(tx_wr_clk),
.m_ns_fwd_clk(tx_rd_clk), //This includes reg mode clock during loopback.
.data_in_f(tx_adapt_din[319:0]),
.data_in(data_in_r),
.r_tx_fifo_mode(csr_tx_fifo_mode),
.r_tx_phcomp_rd_delay(csr_tx_phcomp_rd_delay),
.r_tx_wm_en(csr_tx_wm_en),
.r_tx_mkbit(csr_tx_mkbit),
.r_txswap_en(csr_txswap_en),
.r_tx_dbi_en(csr_tx_dbi_en)
);
aib_sm aib_sm
(
.osc_clk(i_osc_clk), //from aux
.sr_ms_clk_in(sr_clk_in), //input ms clock
.ms_config_done(conf_done), //master config done
.ms_osc_transfer_en(ms_osc_transfer_en),
.ms_rx_transfer_en(ms_rx_transfer_en_m),
.ms_osc_transfer_alive(ms_osc_transfer_alive),
.ms_rx_async_rst(ms_rx_async_rst),
.ms_rx_dll_lock_req(ms_rx_dll_lock_req),
.ms_rx_dll_lock(ms_rx_dll_lock),
.ms_tx_async_rst(ms_tx_async_rst),
.ms_tx_dcc_cal_req(ms_tx_dcc_cal_req),
.sl_tx_dcc_cal_req(sl_tx_dcc_cal_req),
.ms_tx_dcc_cal_done(ms_tx_dcc_cal_done),
.ms_tx_transfer_en(ms_tx_transfer_en_m),
.ms_rx_dcc_dll_lock_req(ms_rx_dcc_dll_lock_req),
.ms_tx_dcc_dll_lock_req(ms_tx_dcc_dll_lock_req),
.ms_rx_dll_lockint(ms_rx_dll_lockint),
.ms_tx_dcc_cal_doneint(ms_tx_dcc_cal_doneint),
.ms_tx_dcc_cal_donei(ms_data_to_core[68]),
.ms_rx_dll_locki(ms_data_to_core[74]),
.ms_rx_transfer_eni(ms_data_to_core[75]),
.ms_tx_transfer_eni(ms_data_to_core[78]),
.ms_osc_transfer_eni(ms_data_to_core[80]),
.sl_config_done(conf_done), //slave config done
.sl_osc_transfer_en(sl_osc_transfer_en),
.sl_rx_transfer_en(sl_rx_transfer_en_s),
.sl_tx_dcc_cal_done(sl_tx_dcc_cal_done),
.sl_tx_transfer_en(sl_tx_transfer_en_s),
.sl_rx_async_rst(sl_rx_async_rst),
.sl_rx_dll_lock_req(sl_rx_dll_lock_req),
.sl_rx_dll_lock(sl_rx_dll_lock),
.sl_tx_dcc_dll_lock_req(sl_data_to_core[63]),
.sl_rx_dcc_dll_lock_req(sl_data_to_core[69]),
.sl_rx_dll_lockint(sl_rx_dll_lockint), //from slave internal
.sl_rx_dll_locki(sl_data_to_core[68]), //from sr interface
.sl_tx_dcc_cal_donei(sl_data_to_core[31]), //from sr interface
.sl_tx_dcc_cal_doneint(sl_tx_dcc_cal_doneint), //from slave internal
.sl_rx_transfer_eni(sl_data_to_core[70]),
.sl_osc_transfer_eni(sl_data_to_core[72]),
.sl_fifo_tx_async_rst(),
.ms_nsl(dual_mode_select), //
.atpg_mode(atpg_mode),
.reset_n(adpt_rstn) //
);
aib_sr_ms #(
.MS_LENGTH(7'd81))
aib_sr_ms
(
.osc_clk(i_osc_clk), //free running osc clock
.ms_data_fr_core(ms_data_fr_core[80:0]),
.ms_data_to_core(ms_data_to_core[80:0]),
.sr_ms_data_out(sr_ms_data_out), //master serial data out
.sr_ms_load_out(sr_ms_load_out), //master load out
.sr_ms_data_in(srd_in), //master serial data out
.sr_ms_load_in(srl_in), //master serial data load inupt
.sr_ms_clk_in(sr_clk_in), //from input por
.ms_nsl(dual_mode_select),
.atpg_mode(atpg_mode),
.reset_n(conf_done)
);
aib_sr_sl #(
.SL_LENGTH(7'd73))
aib_sr_sl
(
.sr_sl_clk_in(sr_clk_in), //From input
.sr_sl_clk_out(sr_sl_clk_out), //to output
.sl_data_fr_core(sl_data_fr_core[72:0]),
.sl_data_to_core(sl_data_to_core[72:0]),
.sr_sl_data_out(sr_sl_data_out), //slave serial data out
.sr_sl_load_out(sr_sl_load_out), //slave load out
.sr_sl_data_in(srd_in), //slave serial data out
.sr_sl_load_in(srl_in), //slave serial data load inupt
.sr_ms_clk_in(sr_clk_in), //input ms clock
.ms_nsl(dual_mode_select),
.atpg_mode(atpg_mode),
.reset_n(conf_done)
);
endmodule // aib_channel |
module aib_adapt_txchnl(
// Outputs
output wire [79:0] dout,
// output wire ns_fwd_clk,
// Inputs
input atpg_mode,
input adapt_rstn,
input tx_fifo_rstn,
input m_gen2_mode,
input m_wr_clk,
input m_ns_fwd_clk,
input [319:0] data_in_f, //FIFO mode
input [79:0] data_in, //register mode
input r_tx_dbi_en,
input [1:0] r_tx_fifo_mode,
input [3:0] r_tx_phcomp_rd_delay,
input r_txswap_en,
input r_tx_wm_en,
input [4:0] r_tx_mkbit
);
wire fifo_empty, fifo_full;
wire [79:0] fifo_dout, merge_dout, data_in_f_sel;
wire txrd_rstn, txfifo_wrclk, txwr_rstn;
wire txrd_fifo_rstn, txwr_fifo_rstn;
//Mux for bypass mode data and fifo data
assign merge_dout[79:0]= (r_tx_fifo_mode == 2'b11) ? data_in[79:0] : fifo_dout[79:0];
//DBI mux
aib_adapttxdbi_txdp txdbi
(
.rst_n(txrd_rstn),
.clk(m_ns_fwd_clk),
.dbi_en(r_tx_dbi_en),
.data_in(merge_dout),
.data_out(dout)
);
assign data_in_f_sel[79:0] = ((r_tx_fifo_mode == 2'b01) & r_txswap_en & ~m_gen2_mode) ?
{data_in_f[79], data_in_f[38:0], data_in_f[39],data_in_f[78:40]} : data_in_f[79:0];
aib_adapttxdp_fifo txdp_fifo (
// Outputs
.fifo_dout (fifo_dout[79:0]),
.fifo_empty (fifo_empty),
.fifo_full (fifo_full),
.fifo_pfull (),
.fifo_pempty (),
// Inputs
.data_in ({data_in_f[319:80], data_in_f_sel[79:0]}),
.r_empty (5'b0),
.r_fifo_mode (r_tx_fifo_mode[1:0]),
.r_full (5'b11111),
.r_pempty (5'b0),
.r_pfull (5'b11111),
.r_phcomp_rd_delay (r_tx_phcomp_rd_delay),
.m_gen2_mode (m_gen2_mode),
.r_wm_en (r_tx_wm_en),
.r_mkbit (r_tx_mkbit),
.wr_clk (m_wr_clk),
.wr_rst_n (txwr_fifo_rstn),
.rd_clk (m_ns_fwd_clk),
.rd_rst_n (txrd_fifo_rstn)
);
aib_rstnsync txwr_rstnsync
(
.clk(m_wr_clk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(txwr_rstn) // Synchronized reset output
);
aib_rstnsync txwr_fifo_rstnsync
(
.clk(m_wr_clk),
.i_rst_n(tx_fifo_rstn),
.scan_mode(atpg_mode),
.sync_rst_n(txwr_fifo_rstn)
);
aib_rstnsync txrd_rstnsync
(
.clk(m_ns_fwd_clk), // Destination clock of reset to be synced
.i_rst_n(adapt_rstn), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(txrd_rstn) // Synchronized reset output
);
aib_rstnsync txrd_fifo_rstnsync
(
.clk(m_ns_fwd_clk),
.i_rst_n(tx_fifo_rstn),
.scan_mode(atpg_mode),
.sync_rst_n(txrd_fifo_rstn)
);
endmodule |
module aib_adaptrxdbi_rxdp (
input wire rst_n,
input wire clk,
input wire [79:0] data_in,
input wire dbi_en,
output wire [79:0] data_out
);
wire [3:0] dbi_calc;
reg [79:0] last_din, dbi_data_out;
wire [37:0] dbi_dat_lo, dbi_dat_hi;
assign data_out = dbi_en? dbi_data_out : data_in;
assign dbi_calc = {data_in[79], data_in[78], data_in[39], data_in[38]};
genvar j;
generate
for (j=0; j<19; j=j+1) begin:data_out_gen
assign dbi_dat_lo[2*j] = data_in[2*j] ^dbi_calc[0];
assign dbi_dat_lo[2*j+1] = data_in[2*j+1] ^dbi_calc[1];
assign dbi_dat_hi[2*j] = data_in[2*j+40] ^dbi_calc[2];
assign dbi_dat_hi[2*j+1] = data_in[2*j+1+40]^dbi_calc[3];
end
endgenerate
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
dbi_data_out <= 80'h0;
end
else
dbi_data_out <= {dbi_calc[3:2], dbi_dat_hi,
dbi_calc[1:0], dbi_dat_lo};
end
endmodule |
module aib_adapttxdp_async_fifo
#(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter AWIDTH = 'd4 // FIFO Depth (address width)
)
(
input wire wr_rst_n, // Write Domain Active low Reset
input wire wr_clk, // Write Domain Clock
input wire wr_en, // Write Data Enable
input wire [DWIDTH*4-1:0] wr_data, // Write Data In
input wire rd_rst_n, // Read Domain Active low Reset
input wire rd_clk, // Read Domain Clock
input wire rd_en, // Read Data Enable
input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold
input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold
input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold
input wire [AWIDTH-1:0] r_full, // FIFO full threshold
input wire [1:0] r_fifo_mode, // FIFO 2'b00 1:1 FIFO mode
// 2'b01 2:1 FIFO mode
// 2'b10 4:1 FIFO mode.
// 2'b11 reg mode.
output reg [DWIDTH-1:0] rd_data, // Read Data Out
output reg wr_empty, // FIFO Empty
output reg wr_pempty, // FIFO Partial Empty
output reg wr_full, // FIFO Full
output reg wr_pfull, // FIFO Parial Full
output reg rd_empty, // FIFO Empty
output reg rd_pempty, // FIFO Partial Empty
output reg rd_full, // FIFO Full
output reg rd_pfull // FIFO Partial Full
);
//********************************************************************
// Define Parameters
//********************************************************************
localparam DEPTH = (1<<AWIDTH);
localparam FIFO_1X = 2'b00; //Full rate
localparam FIFO_2X = 2'b01; //Half rate
localparam FIFO_4X = 2'b10; //Quarter Rate
localparam REG_MOD = 2'b11; //REG mode
//********************************************************************
// Define variables
//********************************************************************
wire [AWIDTH-1:0] rd_numdata; // Number of Data available in Read clock
wire [AWIDTH-1:0] wr_numdata; // Number of Data available in Write clock
wire wr_full_comb; // FIFO Full
wire wr_pfull_comb; // FIFO Parial Full
wire full_rd_empty;
wire full_wr_full;
wire [DEPTH-1:0] full_wr_ptr_one_hot;
wire [DEPTH-1:0] full_rd_ptr_one_hot;
wire [AWIDTH-1:0] full_wr_numdata;
wire [AWIDTH-1:0] full_rd_numdata;
wire [AWIDTH-1:0] full_rd_ptr_bin;
wire [AWIDTH-1:0] full_wr_ptr_bin;
wire [DWIDTH*4-1:0] full_rd_data;
wire [DWIDTH-1:0] rd3, rd2, rd1, rd0;
wire [DWIDTH-1:0] wd3, wd2, wd1, wd0;
reg [1:0] rd_cnt;
reg full_rd_en;
//********************************************************************
// FIFO RAM
//********************************************************************
aib_adapttxdp_fifo_ram
# (
.DWIDTH (DWIDTH),
.DEPTH (DEPTH))
ram (
.wr_clk (wr_clk),
.wr_rst_n (wr_rst_n),
.wr_en (wr_en),
.wr_ptr (full_wr_ptr_one_hot),
.wr_data (wr_data),
.rd_ptr (full_rd_ptr_one_hot),
.rd_data (full_rd_data)
);
assign {rd3, rd2, rd1, rd0} = full_rd_data;
assign {wd3, wd2, wd1, wd0} = wr_data;
//********************************************************************
// FIFO pointers
//********************************************************************
aib_adapttxdp_fifo_ptr
# (
.AWIDTH (AWIDTH),
.DEPTH (DEPTH))
full_pointers (
.wr_clk (wr_clk),
.wr_rst_n (wr_rst_n),
.rd_clk (rd_clk),
.rd_rst_n (rd_rst_n),
.wr_en (wr_en),
.rd_en (full_rd_en),
.rd_empty (full_rd_empty),
.wr_ptr_one_hot (full_wr_ptr_one_hot),
.rd_ptr_one_hot (full_rd_ptr_one_hot),
.rd_ptr_bin (full_rd_ptr_bin),
.wr_ptr_bin (full_wr_ptr_bin),
.wr_numdata (full_wr_numdata),
.rd_numdata (full_rd_numdata)
);
//********************************************************************
// WRITE CLOCK DOMAIN: Generate Fifo Number of Data Present
// using Write Address and Synchronized Read Address
//********************************************************************
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wr_full <= 1'b0;
wr_pfull <= 1'b0;
wr_empty <= 1'b1;
wr_pempty <= 1'b1;
end
else begin
// Generate FIFO Empty
wr_empty <= (wr_numdata <= r_empty) ? 1'b1 : 1'b0;
// Generate FIFO Almost Empty
wr_pempty <= (wr_numdata <= r_pempty) ? 1'b1 : 1'b0;
// Generate FIFO Full
wr_full <= wr_full_comb;
// Generate FIFO Almost Full
wr_pfull <= wr_pfull_comb;
end
end
assign wr_full_comb = (wr_numdata >= r_full) ? 1'b1 : 1'b0;
assign wr_pfull_comb = (wr_numdata >= r_pfull) ? 1'b1 : 1'b0;
//********************************************************************
// READ CLOCK DOMAIN: Generate Fifo Number of Data Present
// using Read Address and Synchronized Write Address
//********************************************************************
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
rd_empty <= 1'b1;
rd_pempty <= 1'b1;
rd_full <= 1'b0;
rd_pfull <= 1'b0;
end
else begin
// Generate FIFO Empty
rd_empty <= (rd_numdata <= r_empty) ? 1'b1 : 1'b0;
// Generate FIFO Almost Empty
rd_pempty <= (rd_numdata <= r_pempty) ? 1'b1 : 1'b0;
// Generate FIFO Full
rd_full <= (rd_numdata >= r_full) ? 1'b1 : 1'b0;
// Generate FIFO Almost Full
rd_pfull <= (rd_numdata >= r_pfull) ? 1'b1 : 1'b0;
end
end
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
rd_cnt <= 2'b0;
end
else begin
// Generate counter that select rd data for full/half/quard data rate
if (rd_en == 1'b1)
rd_cnt <= rd_cnt + 1'b1;
end
end
always @ * begin
if (r_fifo_mode == FIFO_4X) full_rd_en = rd_en & (rd_cnt == 2'b11);
else if (r_fifo_mode == FIFO_2X) full_rd_en = rd_en & (rd_cnt[0] == 1'b1);
else full_rd_en = rd_en;
end
//********************************************************************
// FIFO Mapping
//********************************************************************
assign wr_numdata = full_wr_numdata;
assign rd_numdata = full_rd_numdata;
// Read data: concatenate data from multiple FIFOs
always @ * begin
case (r_fifo_mode)
REG_MOD: rd_data = rd0;
FIFO_1X: rd_data = rd0;
FIFO_2X: case (rd_cnt[0])
1'b0: rd_data = rd0;
1'b1: rd_data = rd1;
endcase
FIFO_4X: case(rd_cnt)
2'b00: rd_data = rd0;
2'b01: rd_data = rd1;
2'b10: rd_data = rd2;
2'b11: rd_data = rd3;
endcase
endcase
end
endmodule |
module aib_avmm_adapt_csr (
output reg [31:0] rx_0,
output reg [31:0] rx_1,
output reg [31:0] tx_0,
output reg [31:0] tx_1,
//Bus Interface
input clk,
input reset,
input [31:0] writedata,
input read,
input write,
input [3:0] byteenable,
output reg [31:0] readdata,
output reg readdatavalid,
input [6:0] address
);
wire reset_n = !reset;
// Protocol management
// combinatorial read data signal declaration
reg [31:0] rdata_comb;
// synchronous process for the read
always @(negedge reset_n ,posedge clk)
if (!reset_n) readdata[31:0] <= 32'h0; else readdata[31:0] <= rdata_comb[31:0];
// read data is always returned on the next cycle
always @(negedge reset_n , posedge clk)
if (!reset_n) readdatavalid <= 1'b0; else readdatavalid <= read;
//
// Protocol specific assignment to inside signals
//
wire we = write;
wire re = read;
wire [6:0] addr = address[6:0];
wire [31:0] din = writedata [31:0];
// A write byte enable for each register
wire [3:0] we_rx_0 = we & (addr[6:0] == 7'h08) ? byteenable[3:0] : {4{1'b0}};
wire [3:0] we_rx_1 = we & (addr[6:0] == 7'h10) ? byteenable[3:0] : {4{1'b0}};
wire [3:0] we_tx_0 = we & (addr[6:0] == 7'h18) ? byteenable[3:0] : {4{1'b0}};
wire [3:0] we_tx_1 = we & (addr[6:0] == 7'h1c) ? byteenable[3:0] : {4{1'b0}};
// A read byte enable for each register
always @( negedge reset_n, posedge clk)
if (!reset_n) begin
rx_0[31:0] <= 32'h00000000;
end
else begin
if (we_rx_0[0]) begin
rx_0[7:0] <= din[7:0];
end
if (we_rx_0[1]) begin
rx_0[15:8] <= din[15:8];
end
if (we_rx_0[2]) begin
rx_0[23:16] <= din[23:16];
end
if (we_rx_0[3]) begin
rx_0[31:24] <= din[31:24];
end
end
always @( negedge reset_n, posedge clk)
if (!reset_n) begin
rx_1[31:0]<= 32'h00000000;
end
else begin
if (we_rx_1[0]) begin
rx_1[7:0] <= din[7:0];
end
if (we_rx_1[1]) begin
rx_1[15:8] <= din[15:8];
end
if (we_rx_1[2]) begin
rx_1[23:16] <= din[23:16];
end
if (we_rx_1[3]) begin
rx_1[31:24] <= din[31:24];
end
end
always @( negedge reset_n, posedge clk)
if (!reset_n) begin
tx_0[31:0] <= 32'h00000000;
end
else begin
if (we_tx_0[0]) begin
tx_0[7:0] <= din[7:0];
end
if (we_tx_0[1]) begin
tx_0[15:8] <= din[15:8];
end
if (we_tx_0[2]) begin
tx_0[23:16] <= din[23:16];
end
if (we_tx_0[3]) begin
tx_0[31:24] <= din[31:24];
end
end
always @( negedge reset_n, posedge clk)
if (!reset_n) begin
tx_1[31:0]<= 32'h00000000;
end
else begin
if (we_tx_1[0]) begin
tx_1[7:0] <= din[7:0];
end
if (we_tx_1[1]) begin
tx_1[15:8] <= din[15:8];
end
if (we_tx_1[2]) begin
tx_1[23:16] <= din[23:16];
end
if (we_tx_1[3]) begin
tx_1[31:24] <= din[31:24];
end
end
// read process
always @ (*)
begin
rdata_comb = 32'h0;
if(re) begin
case (addr)
7'h08 : begin
rdata_comb [1:0] = rx_0[1:0];
rdata_comb [26:24] = rx_0[26:24] ;
end
7'h10 : begin
rdata_comb [7:0] = rx_1 [7:0] ;
end
7'h18 : begin
rdata_comb [1:0] = tx_0[1:0];
rdata_comb [23:16] = tx_0[23:16];
rdata_comb [31:28] = tx_0[31:28];
end
7'h1c : begin
rdata_comb [15:14]= tx_1[15:14];
end
default : begin
rdata_comb = 32'h00000000;
end
endcase
end
end
endmodule |
module aib_avmm (
input [5:0] cfg_avmm_addr_id,
input cfg_avmm_clk,
input cfg_avmm_rst_n,
input cfg_avmm_write,
input cfg_avmm_read,
input [16:0] cfg_avmm_addr,
input [31:0] cfg_avmm_wdata,
input [3:0] cfg_avmm_byte_en,
output [31:0] cfg_avmm_rdata,
output cfg_avmm_rdatavld,
output cfg_avmm_waitreq,
//Adapt control CSR
output [31:0] rx_adapt_0,
output [31:0] rx_adapt_1,
output [31:0] tx_adapt_0,
output [31:0] tx_adapt_1,
//AIB IO control CSR
output [31:0] redund_0,
output [31:0] redund_1,
output [31:0] redund_2,
output [31:0] redund_3
);
wire cfg_csr_clk, cfg_csr_reset;
wire cfg_csr_read,cfg_csr_write;
wire cfg_csr_rdatavld;
wire [31:0] cfg_csr_wdata, cfg_csr_rdata;
wire [6:0] cfg_csr_addr;
wire [3:0] cfg_csr_byteen;
wire cfg_adapt_addr_match, cfg_io_addr_match;
wire cfg_adapt_rdatavld, cfg_io_rdatavld;
wire [31:0] cfg_adapt_rdata, cfg_io_rdata;
localparam AIB_BASE_BOT = 11'h200;
localparam AIB_BASE_MID = 11'h300;
localparam AIB_BASE_TOP = 11'h400;
// Configuration registers for Adapter and AIBIO
assign cfg_only_id_match = (cfg_avmm_addr_id[5:0] == cfg_avmm_addr[16:11]);
assign cfg_only_addr_match = (cfg_avmm_addr[10:0] >= AIB_BASE_BOT) & (cfg_avmm_addr[10:0] < AIB_BASE_TOP) & cfg_only_id_match;
assign cfg_adapt_addr_match = (cfg_avmm_addr[10:0] >= AIB_BASE_BOT) & (cfg_avmm_addr[10:0] < AIB_BASE_MID);
assign cfg_io_addr_match = (cfg_avmm_addr[10:0] >= AIB_BASE_MID) & (cfg_avmm_addr[10:0] < AIB_BASE_TOP);
assign cfg_only_write = cfg_only_addr_match & cfg_avmm_write;
assign cfg_only_read = cfg_only_addr_match & cfg_avmm_read;
assign cfg_csr_rdatavld = cfg_adapt_rdatavld | cfg_io_rdatavld;
assign cfg_csr_rdata = cfg_adapt_rdata | cfg_io_rdata;
aib_avmm_rdl_intf #( .AVMM_ADDR_WIDTH(8), .RDL_ADDR_WIDTH (7))
adapt_cfg_rdl_intf (
.avmm_clk (cfg_avmm_clk), // input logic // AVMM Slave interface
.avmm_rst_n (cfg_avmm_rst_n), // input logic
.i_avmm_write (cfg_only_write), // input logic
.i_avmm_read (cfg_only_read), // input logic
.i_avmm_addr (cfg_avmm_addr[7:0]), // input logic [AVMM_ADDR_WIDTH-1:0]
.i_avmm_wdata (cfg_avmm_wdata), // input logic [31:0]
.i_avmm_byte_en (cfg_avmm_byte_en), // input logic [3:0]
.o_avmm_rdata (cfg_avmm_rdata), // output logic [31:0]
.o_avmm_rdatavalid (cfg_avmm_rdatavld), // output logic
.o_avmm_waitrequest (cfg_avmm_waitreq), // output logic
.clk (cfg_csr_clk), // output logic // RDL-generated memory map interface
.reset (cfg_csr_reset), // output logic
.writedata (cfg_csr_wdata), // output logic [31:0]
.read (cfg_csr_read), // output logic
.write (cfg_csr_write), // output logic
.byteenable (cfg_csr_byteen), // output logic [3:0]
.readdata (cfg_csr_rdata), // input logic [31:0]
.readdatavalid (cfg_csr_rdatavld), // input logic
.address (cfg_csr_addr) // output logic [RDL_ADDR_WIDTH-1:0]
);
aib_avmm_adapt_csr adapt_csr (
.rx_0(rx_adapt_0),
.rx_1(rx_adapt_1),
.tx_0(tx_adapt_0),
.tx_1(tx_adapt_1),
.clk(cfg_csr_clk),
.reset(cfg_csr_reset),
.writedata(cfg_csr_wdata),
.read((cfg_csr_read & cfg_adapt_addr_match)),
.write((cfg_csr_write &cfg_adapt_addr_match)),
.byteenable(cfg_csr_byteen),
.readdata(cfg_adapt_rdata),
.readdatavalid(cfg_adapt_rdatavld),
.address(cfg_csr_addr)
);
aib_avmm_io_csr io_csr (
.redund_0(redund_0),
.redund_1(redund_1),
.redund_2(redund_2),
.redund_3(redund_3),
.clk(cfg_csr_clk),
.reset(cfg_csr_reset),
.writedata(cfg_csr_wdata),
.read((cfg_csr_read & cfg_io_addr_match)),
.write((cfg_csr_write & cfg_io_addr_match)),
.byteenable(cfg_csr_byteen),
.readdata(cfg_io_rdata),
.readdatavalid(cfg_io_rdatavld),
.address(cfg_csr_addr)
);
endmodule |
module aib_adaptrxdp_fifo_ram
#(
parameter DWIDTH = 'd80, // FIFO Input data width
parameter DEPTH = 'd16 // FIFO Depth
)
(
input wire wr_clk, // Write Domain Clock
input wire wr_rst_n, // Write Domain Reset
input wire wr_en, // Write Data Enable
input wire [DEPTH-1:0] wr_ptr, // Write Pointer
input wire [DWIDTH*4-1:0] wr_data, // Write Data In
input wire [DEPTH-1:0] rd_ptr, // Read Pointer
output reg [DWIDTH*4-1:0] rd_data // Read Data
);
//********************************************************************
// Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
//********************************************************************
wire [DEPTH-1:0] rd_ptr2;
integer m;
integer i, j;
reg [DWIDTH*4-1:0] fifo_mem [DEPTH-1:0];
always @(negedge wr_rst_n or posedge wr_clk) begin
if (~wr_rst_n) begin
for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1)
fifo_mem[m] <= 'd0;
end
else if (wr_en) begin
for (m='d0; m<=(DEPTH-1'b1); m=m+1'b1) begin
if (wr_ptr[m]) begin
fifo_mem[m] <= wr_data;
end
end
end
end
always @ *
begin: data_out
rd_data = fifo_mem[0];
for (i='d0; i<=(DEPTH-1'b1); i=i+1'b1) begin
if (rd_ptr[i]) begin
rd_data = fifo_mem[i];
end
end
end
endmodule |
module ao486_rst_controller
(
input wire clk_sys,
input wire rst,
output reg ao486_rst,
input wire [1:0] address,
input wire write,
input wire [31:0] writedata
);
always @(posedge clk_sys) begin
if(rst) begin
ao486_rst <= 1;
end else begin
if(write && writedata[0] == 1'b0 && address == 4'b0000)
ao486_rst <= 0;
else if(write && writedata[0] == 1'b1 && address == 4'b0000)
ao486_rst <= 1;
end
end
endmodule |
module simple_biclk_bidir_ram
#(parameter width = 1,
parameter widthad = 1)
(
input clk,
input [widthad-1:0] address_a,
input wren_a,
input [width-1:0] data_a,
output reg [width-1:0] q_a,
input clk2,
input [widthad-1:0] address_b,
output reg [width-1:0] q_b
);
reg [width-1:0] mem [(2**widthad)-1:0];
always @(posedge clk) begin
if(wren_a) mem[address_a] <= data_a;
q_a <= mem[address_a];
end
always @(posedge clk2) begin
q_b <= mem[address_b];
end
endmodule |
module to_driver_sd_avs(
input wire clk_sys,
input wire rst,
input wire ao486_rst,
// input hdd_avalon_master
input wire [31:0] hdd_avalon_master_address,
input wire hdd_avalon_master_read,
output wire [31:0] hdd_avalon_master_readdata,
input wire hdd_avalon_master_write,
input wire [31:0] hdd_avalon_master_writedata,
output wire hdd_avalon_master_waitrequest,
output reg hdd_avalon_master_readdatavalid,
// input bios_loader
input wire [31:0] bios_loader_address,
input wire bios_loader_read,
output wire [31:0] bios_loader_readdata,
input wire bios_loader_write,
input wire [31:0] bios_loader_writedata,
output wire bios_loader_waitrequest,
input wire [3:0] bios_loader_byteenable,
// output driver_sd_avs
output wire [1:0] driver_sd_avs_address,
output wire driver_sd_avs_read,
input wire [31:0] driver_sd_avs_readdata,
output wire driver_sd_avs_write,
output wire [31:0] driver_sd_avs_writedata
);
assign driver_sd_avs_address = (~ao486_rst) ? hdd_avalon_master_address[3:2] : bios_loader_address[3:2];
assign driver_sd_avs_read = (~ao486_rst) ? hdd_avalon_master_read : bios_loader_read && bios_loader_address[31:4] == 28'h0;
assign driver_sd_avs_write = (~ao486_rst) ? hdd_avalon_master_write : bios_loader_write && bios_loader_address[31:4] == 28'h0;
assign driver_sd_avs_writedata = (~ao486_rst) ? hdd_avalon_master_writedata : bios_loader_writedata;
assign hdd_avalon_master_readdata = (~ao486_rst) ? driver_sd_avs_readdata : 0;
assign hdd_avalon_master_waitrequest = 0;
always @(posedge clk_sys) hdd_avalon_master_readdatavalid <= (~ao486_rst) ? driver_sd_avs_read : 0;
assign bios_loader_readdata = (~ao486_rst) ? 0 : driver_sd_avs_readdata;
assign bios_loader_waitrequest = 0;
endmodule |
module byteen_converter
#(
parameter IADDR = 32,
parameter OADDR = 32
)
(
input wire clk_sys,
input wire rst,
input wire [IADDR-1:0] addr_in,
input wire write_in,
input wire [31:0] writedata_in,
input wire read_in,
output reg [31:0] readdata_out,
output reg readdatavalid_out,
input wire [3:0] byteenable_in,
output wire waitrequest_out,
output wire [OADDR-1:0] addr_out,
output wire write_out,
output wire [7:0] writedata_out,
output wire read_out,
input wire [7:0] readdata_in,
input wire readdatavalid_in,
input wire waitrequest_in
);
function [2:0] cnt_bit;
input [3:0] data;
integer index;
begin
cnt_bit = 0;
for(index = 0; index < 4; index = index + 1)
if(data[index])
cnt_bit = cnt_bit + 1;
end
endfunction
// data
// data[8] = valid bit
reg [IADDR-1:0] addr0;
reg [8:0] data0; // not used
reg [8:0] data1; // data1
reg [8:0] data2; // data2
reg [8:0] data3; // data3
reg write_mode, read_mode;
assign addr_out = (data1[8]) ? addr0 | 1 :
(data2[8]) ? addr0 | 2 :
(data3[8]) ? addr0 | 3 :
(byteenable_in[0]) ? addr_in :
(byteenable_in[1]) ? addr_in | 1 :
(byteenable_in[2]) ? addr_in | 2 :
(byteenable_in[3]) ? addr_in | 3 : 0;
assign writedata_out = (data1[8] && write_mode) ? data1[7:0] :
(data2[8] && write_mode) ? data2[7:0] :
(data3[8] && write_mode) ? data3[7:0] :
(byteenable_in[0]) ? writedata_in[7:0] :
(byteenable_in[1]) ? writedata_in[15:8] :
(byteenable_in[2]) ? writedata_in[23:16] :
(byteenable_in[3]) ? writedata_in[31:24] : 0;
assign write_out = (!read_mode) && ((write_in && byteenable_in != 0) || write_mode);
assign read_out = (!write_mode) && ((read_in && byteenable_in != 0) || read_mode);
assign waitrequest_out = waitrequest_in || read_mode || write_mode;
always @(posedge clk_sys) begin
if(rst) begin
{data1, data2, data3} <= 0;
{write_mode, read_mode} <= 0;
end else if(data1[8]) begin
data1 <= 0;
write_mode <= write_mode && (data2[8] || data3[8]);
read_mode <= read_mode && (data2[8] || data3[8]);
end else if(data2[8]) begin
data2 <= 0;
write_mode <= write_mode && (data3[8]);
read_mode <= read_mode && (data3[8]);
end else if(data3[8]) begin
data3 <= 0;
write_mode <= 0;
read_mode <= 0;
end else if(cnt_bit(byteenable_in) > 1 && (write_in || read_in)) begin
write_mode <= write_in;
read_mode <= read_in;
addr0 <= addr_in;
data1[8] <= (byteenable_in[0] && byteenable_in[1]) ? 1 : 0;
data2[8] <= (byteenable_in[1:0] && byteenable_in[2]) ? 1 : 0;
data3[8] <= (byteenable_in[2:0] && byteenable_in[3]) ? 1 : 0;
data1[7:0] <= (byteenable_in[0] && byteenable_in[1]) ? writedata_in[15: 8] : 0;
data2[7:0] <= (byteenable_in[1:0] && byteenable_in[2]) ? writedata_in[23:16] : 0;
data3[7:0] <= (byteenable_in[2:0] && byteenable_in[3]) ? writedata_in[31:24] : 0;
end
end
/////////////////////////////////////////////////////////////////////////
reg [3:0] rflag;
always @(posedge clk_sys) begin
if(rst) begin
rflag <= 0;
readdata_out <= 0;
readdatavalid_out <= 0;
end else begin
if(rflag[0] && readdatavalid_in) begin
rflag <= (read_in && !waitrequest_out) ? byteenable_in : {rflag[3:1], 1'b0};
readdata_out <= {readdata_out[31:8], readdata_in};
readdatavalid_out <= !(rflag[3:1]);
end else if(rflag[1] && readdatavalid_in) begin
rflag <= (read_in && !waitrequest_out) ? byteenable_in : {rflag[3:2], 2'b0};
readdata_out <= {readdata_out[31:16], readdata_in, readdata_out[7:0]};
readdatavalid_out <= !(rflag[3:2]);
end else if(rflag[2] && readdatavalid_in) begin
rflag <= (read_in && !waitrequest_out) ? byteenable_in : {rflag[3], 3'b0};
readdata_out <= {readdata_out[31:24], readdata_in[7:0], readdata_out[15:0]};
readdatavalid_out <= !(rflag[3]);
end else if(rflag[3] && readdatavalid_in) begin
rflag <= (read_in && !waitrequest_out) ? byteenable_in : 0;
readdata_out <= {readdata_in[7:0], readdata_out[23:0]};
readdatavalid_out <= 1;
end else if(read_in && !waitrequest_out) begin
rflag <= byteenable_in;
readdatavalid_out <= 0;
end else begin
readdatavalid_out <= 0;
end
end
end
endmodule |
module io_bus
(
input wire clk_sys,
input wire rst,
// input ao486_avalon_io
input wire [15:0] ao486_avalon_io_address,
output wire ao486_avalon_io_waitrequest,
input wire [3:0] ao486_avalon_io_byteenable,
input wire ao486_avalon_io_read,
output wire [31:0] ao486_avalon_io_readdata,
output wire ao486_avalon_io_readdatavalid,
input wire ao486_avalon_io_write,
input wire [31:0] ao486_avalon_io_writedata,
// output vga_io_b, address: 0x3b0~0x3bf
output wire [3:0] vga_io_b_address,
output wire vga_io_b_write,
output wire [7:0] vga_io_b_writedata,
output wire vga_io_b_read,
input wire [7:0] vga_io_b_readdata,
// output vga_io_c, address: 0x3c0~0x3cf
output wire [3:0] vga_io_c_address,
output wire vga_io_c_write,
output wire [7:0] vga_io_c_writedata,
output wire vga_io_c_read,
input wire [7:0] vga_io_c_readdata,
// output vga_io_d, address: 0x3d0~0x3df
output wire [3:0] vga_io_d_address,
output wire vga_io_d_write,
output wire [7:0] vga_io_d_writedata,
output wire vga_io_d_read,
input wire [7:0] vga_io_d_readdata,
// output ps2_io, address: 0x60~0x67
output wire [2:0] ps2_io_address,
output wire ps2_io_write,
output wire [7:0] ps2_io_writedata,
output wire ps2_io_read,
input wire [7:0] ps2_io_readdata,
// output ps2_sysctl, address: 0x90~0x9f
output wire [3:0] ps2_sysctl_address,
output wire ps2_sysctl_write,
output wire [7:0] ps2_sysctl_writedata,
output wire ps2_sysctl_read,
input wire [7:0] ps2_sysctl_readdata,
// output pit_io, address: 0x40~0x43
output wire [1:0] pit_io_address,
output wire pit_io_write,
output wire [7:0] pit_io_writedata,
output wire pit_io_read,
input wire [7:0] pit_io_readdata,
// output rtc_io, address: 0x70~0x71
output wire rtc_io_address,
output wire rtc_io_write,
output wire [7:0] rtc_io_writedata,
output wire rtc_io_read,
input wire [7:0] rtc_io_readdata,
// output pic_master, address: 0x20~0x21
output wire pic_master_address,
output wire pic_master_write,
output wire [7:0] pic_master_writedata,
output wire pic_master_read,
input wire [7:0] pic_master_readdata,
// output pic_slave, address: 0xa0~0xa1
output wire pic_slave_address,
output wire pic_slave_write,
output wire [7:0] pic_slave_writedata,
output wire pic_slave_read,
input wire [7:0] pic_slave_readdata,
// output hdd_io, address: 0x1f0, 0x1f4
output wire hdd_io_address,
output wire hdd_io_write,
output wire [31:0] hdd_io_writedata,
output wire hdd_io_read,
input wire [31:0] hdd_io_readdata,
output wire [3:0] hdd_io_byteenable,
// output ide_3f6, address: 0x3f6
output wire ide_3f6_write,
output wire [7:0] ide_3f6_writedata,
output wire ide_3f6_read,
input wire [7:0] ide_3f6_readdata
);
function [1:0] count_bit;
input [3:0] data;
integer i;
begin
count_bit = 0;
for(i = 0; i <= 3; i = i + 1) begin
if(data[i])
count_bit = count_bit + 1;
end
end
endfunction
//------------------------------------------------------------------------------------
//------------------ ao486 --------------------------------------------------------
//------------------------------------------------------------------------------------
reg vga_io_b_readdatavalid;
always @(posedge clk_sys) vga_io_b_readdatavalid <= vga_io_b_read;
reg vga_io_c_readdatavalid;
always @(posedge clk_sys) vga_io_c_readdatavalid <= vga_io_c_read;
reg vga_io_d_readdatavalid;
always @(posedge clk_sys) vga_io_d_readdatavalid <= vga_io_d_read;
reg ps2_io_readdatavalid;
always @(posedge clk_sys) ps2_io_readdatavalid <= ps2_io_read;
reg ps2_sysctl_readdatavalid;
always @(posedge clk_sys) ps2_sysctl_readdatavalid <= ps2_sysctl_read;
reg pit_io_readdatavalid;
always @(posedge clk_sys) pit_io_readdatavalid <= pit_io_read;
reg rtc_io_readdatavalid;
always @(posedge clk_sys) rtc_io_readdatavalid <= rtc_io_read;
reg pic_master_readdatavalid;
always @(posedge clk_sys) pic_master_readdatavalid <= pic_master_read;
reg pic_slave_readdatavalid;
always @(posedge clk_sys) pic_slave_readdatavalid <= pic_slave_read;
reg ide_3f6_readdatavalid;
always @(posedge clk_sys) ide_3f6_readdatavalid <= ide_3f6_read;
reg hdd_io_readdatavalid;
always @(posedge clk_sys) hdd_io_readdatavalid <= hdd_io_read;
wire [31:0] converted_readdata;
wire converted_readdatavalid;
wire [7:0] readdata_without_hdd;
wire readdatavalid_without_hdd;
reg error_rdvalid;
assign readdatavalid_without_hdd = vga_io_b_readdatavalid || vga_io_c_readdatavalid ||
vga_io_d_readdatavalid || ps2_io_readdatavalid ||
ps2_io_readdatavalid || ps2_sysctl_readdatavalid ||
pit_io_readdatavalid || rtc_io_readdatavalid ||
pic_master_readdatavalid || pic_slave_readdatavalid ||
ide_3f6_readdatavalid || error_rdvalid;
assign readdata_without_hdd = (vga_io_b_readdatavalid) ? vga_io_b_readdata :
(vga_io_c_readdatavalid) ? vga_io_c_readdata :
(vga_io_d_readdatavalid) ? vga_io_d_readdata :
(ps2_io_readdatavalid) ? ps2_io_readdata :
(ps2_sysctl_readdatavalid) ? ps2_sysctl_readdata :
(pit_io_readdatavalid) ? pit_io_readdata :
(rtc_io_readdatavalid) ? rtc_io_readdata :
(pic_master_readdatavalid) ? pic_master_readdata :
(pic_slave_readdatavalid) ? pic_slave_readdata :
(ide_3f6_readdatavalid) ? ide_3f6_readdata : 0;
assign ao486_avalon_io_readdata = (hdd_io_readdatavalid) ? hdd_io_readdata : converted_readdata;
assign ao486_avalon_io_readdatavalid = converted_readdatavalid || hdd_io_readdatavalid;
wire [15:0] converted_address;
wire [7:0] converted_writedata;
wire converted_write, converted_read;
byteen_converter #(.IADDR(16), .OADDR(16))
byteen_converter(.clk_sys(clk_sys), .rst(rst), .addr_in(ao486_avalon_io_address), .write_in(ao486_avalon_io_write && ~hdd_io_write),
.writedata_in(ao486_avalon_io_writedata), .read_in(ao486_avalon_io_read && ~hdd_io_read), .byteenable_in(ao486_avalon_io_byteenable),
.waitrequest_out(ao486_avalon_io_waitrequest), .addr_out(converted_address), .write_out(converted_write),
.writedata_out(converted_writedata), .read_out(converted_read), .waitrequest_in(0), .readdata_in(readdata_without_hdd),
.readdatavalid_in(readdatavalid_without_hdd), .readdata_out(converted_readdata), .readdatavalid_out(converted_readdatavalid));
//------------------------------------------------------------------------------------
//------------------ vga_io_b --------------------------------------------------------
//------------------------------------------------------------------------------------
assign vga_io_b_address = converted_address[3:0];
assign vga_io_b_read = (converted_address[15:4] == 12'h3b) && converted_read;
assign vga_io_b_write = (converted_address[15:4] == 12'h3b) && converted_write;
assign vga_io_b_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ vga_io_c --------------------------------------------------------
//------------------------------------------------------------------------------------
assign vga_io_c_address = converted_address[3:0];
assign vga_io_c_read = (converted_address[15:4] == 12'h3c) && converted_read;
assign vga_io_c_write = (converted_address[15:4] == 12'h3c) && converted_write;
assign vga_io_c_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ vga_io_d --------------------------------------------------------
//------------------------------------------------------------------------------------
assign vga_io_d_address = converted_address[3:0];
assign vga_io_d_read = (converted_address[15:4] == 12'h3d) && converted_read;
assign vga_io_d_write = (converted_address[15:4] == 12'h3d) && converted_write;
assign vga_io_d_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ ps2_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign ps2_io_address = converted_address[2:0];
assign ps2_io_read = (converted_address[15:4] == 12'h6) && converted_read;
assign ps2_io_write = (converted_address[15:4] == 12'h6) && converted_write;
assign ps2_io_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ ps2_sysctl ------------------------------------------------------
//------------------------------------------------------------------------------------
assign ps2_sysctl_address = converted_address[3:0];
assign ps2_sysctl_read = (converted_address[15:4] == 12'h9) && converted_read;
assign ps2_sysctl_write = (converted_address[15:4] == 12'h9) && converted_write;
assign ps2_sysctl_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ pit_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign pit_io_address = converted_address[1:0];
assign pit_io_read = (converted_address[15:4] == 12'h4) && converted_read;
assign pit_io_write = (converted_address[15:4] == 12'h4) && converted_write;
assign pit_io_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ rtc_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign rtc_io_address = converted_address[0];
assign rtc_io_read = (converted_address[15:4] == 12'h7) && converted_read;
assign rtc_io_write = (converted_address[15:4] == 12'h7) && converted_write;
assign rtc_io_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ pic_master ------------------------------------------------------
//------------------------------------------------------------------------------------
assign pic_master_address = converted_address[0];
assign pic_master_read = (converted_address[15:4] == 12'h2) && converted_read;
assign pic_master_write = (converted_address[15:4] == 12'h2) && converted_write;
assign pic_master_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ pic_slave -------------------------------------------------------
//------------------------------------------------------------------------------------
assign pic_slave_address = converted_address[0];
assign pic_slave_read = (converted_address[15:4] == 12'ha) && converted_read;
assign pic_slave_write = (converted_address[15:4] == 12'ha) && converted_write;
assign pic_slave_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ hdd_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign hdd_io_address = ao486_avalon_io_address[2];
assign hdd_io_read = (ao486_avalon_io_address[15:4] == 12'h1f) && ao486_avalon_io_read;
assign hdd_io_write = (ao486_avalon_io_address[15:4] == 12'h1f) && ao486_avalon_io_write;
assign hdd_io_writedata = ao486_avalon_io_writedata;
assign hdd_io_byteenable = ao486_avalon_io_byteenable;
//------------------------------------------------------------------------------------
//------------------ ide_3f6 ---------------------------------------------------------
//------------------------------------------------------------------------------------
assign ide_3f6_read = (converted_address[15:0] == 16'h3f6) && converted_read;
assign ide_3f6_write = (converted_address[15:0] == 16'h3f6) && converted_write;
assign ide_3f6_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ error --------------------------------------------------------
//------------------------------------------------------------------------------------
wire error_read = converted_read &&
~(vga_io_b_read || vga_io_c_read || vga_io_d_read || ps2_io_read || ps2_sysctl_read ||
pit_io_read || rtc_io_read || pic_master_read || pic_slave_read ||
ide_3f6_read);
wire error_write = converted_write &&
~(vga_io_b_write || vga_io_c_write || vga_io_d_write || ps2_io_write || ps2_sysctl_write ||
pit_io_write || rtc_io_write || pic_master_write || pic_slave_write ||
ide_3f6_write);
wire error_cond = error_read || error_write;
always @(posedge clk_sys) error_rdvalid <= error_read;
endmodule |
module bios_loader (
input wire clk,
input wire rst,
output reg [27:0] address,
output reg [3:0] byteenable,
output reg write,
output reg [31:0] writedata,
output reg read,
input wire [31:0] readdata,
input wire waitrequest
);
parameter PIO_OUTPUT_ADDR = 32'h00008860;
parameter DRIVER_SD_ADDR = 32'h00000000;
parameter BIOS_SECTOR = 72;
parameter BIOS_SIZE = (64*1024);
parameter BIOS_ADDR = 32'hF0000 | 32'h8000000;
parameter VBIOS_SECTOR = 8;
parameter VBIOS_SIZE = (32*1024);
parameter VBIOS_ADDR = 32'hC0000 | 32'h8000000;
parameter CTRL_READ = 2;
reg [31:0] state;
always @(posedge clk) begin
if(rst) state <= 1;
else if(state != 0 && (!(waitrequest && write))) state <= state + 1;
end
always @(posedge clk) begin
if(rst) begin
write <= 0;
read <= 0;
writedata <= 0;
address <= 0;
byteenable <= 4'b0000;
end else if(!(waitrequest && write))begin
case(state)
20000000: begin
// set pio_output to 1 (set ao486_reset to low)
address <= PIO_OUTPUT_ADDR;
writedata <= 32'h1;
write <= 1;
end
20001000: begin
// load bios
// bios address
write <= 1;
address <= DRIVER_SD_ADDR;
writedata <= BIOS_ADDR;
end
20002000: begin
// load bios
// SD sector
write <= 1;
address <= DRIVER_SD_ADDR + 4;
writedata <= BIOS_SECTOR;
end
20003000: begin
// load bios
// sector count
write <= 1;
address <= DRIVER_SD_ADDR + 8;
writedata <= BIOS_SIZE / 512;
end
20004000: begin
// load bios
// control READ
write <= 1;
address <= DRIVER_SD_ADDR + 12;
writedata <= CTRL_READ;
end
40004000: begin
// load vbios
// vbios address
write <= 1;
address <= DRIVER_SD_ADDR;
writedata <= VBIOS_ADDR;
end
40005000: begin
// load vbios
// SD sector
write <= 1;
address <= DRIVER_SD_ADDR + 4;
writedata <= VBIOS_SECTOR;
end
40006000: begin
// load vbios
// sector count
write <= 1;
address <= DRIVER_SD_ADDR + 8;
writedata <= VBIOS_SIZE / 512;
end
40007000: begin
// load vbios
// control READ
write <= 1;
address <= DRIVER_SD_ADDR + 12;
writedata <= CTRL_READ;
end
60007000: begin
// set pio_output to 0 (set ao486_reset to high)
address <= PIO_OUTPUT_ADDR;
writedata <= 32'h0;
write <= 1;
end
default: begin
write <= 0;
writedata <= 0;
address <= 0;
end
endcase
end
end
endmodule |
module pc_bus_to_vga
(
input wire clk_sys,
input wire rst,
// input pc_bus_vga
input wire [31:0] pc_bus_vga_address,
input wire [3:0] pc_bus_vga_byteenable,
input wire pc_bus_vga_read,
output wire [31:0] pc_bus_vga_readdata,
input wire pc_bus_vga_write,
input wire [31:0] pc_bus_vga_writedata,
output wire pc_bus_vga_waitrequest,
output wire pc_bus_vga_readdatavalid,
input wire [2:0] pc_bus_vga_burstcount,
// output vga_mem
output wire [16:0] vga_mem_address,
output wire vga_mem_read,
input wire [7:0] vga_mem_readdata,
output wire vga_mem_write,
output wire [7:0] vga_mem_writedata
);
wire [31:0] burst_converted_address;
wire burst_converted_write;
wire [31:0] burst_converted_writedata;
wire burst_converted_read;
wire [31:0] burst_converted_readdata;
wire burst_converted_readdatavalid;
wire [3:0] burst_converted_byteenable;
wire burst_converted_waitrequest;
burst_converter #(.IADDR(32), .OADDR(32))
burst_converter (
.clk_sys (clk_sys),
.rst (rst),
.addr_in (pc_bus_vga_address),
.write_in (pc_bus_vga_write),
.writedata_in (pc_bus_vga_writedata),
.read_in (pc_bus_vga_read),
.readdata_out (pc_bus_vga_readdata),
.readdatavalid_out (pc_bus_vga_readdatavalid),
.byteenable_in (pc_bus_vga_byteenable),
.burstcount_in (pc_bus_vga_burstcount),
.waitrequest_out (pc_bus_vga_waitrequest),
.addr_out (burst_converted_address),
.write_out (burst_converted_write),
.writedata_out (burst_converted_writedata),
.read_out (burst_converted_read),
.readdata_in (burst_converted_readdata),
.readdatavalid_in (burst_converted_readdatavalid),
.byteenable_out (burst_converted_byteenable),
.waitrequest_in (burst_converted_waitrequest)
);
reg vga_mem_readdatavalid;
always @(posedge clk_sys) vga_mem_readdatavalid <= vga_mem_read;
byteen_converter #(.IADDR(32), .OADDR(17))
byteen_converter (
.clk_sys (clk_sys),
.rst (rst),
.addr_in (burst_converted_address),
.write_in (burst_converted_write),
.writedata_in (burst_converted_writedata),
.read_in (burst_converted_read),
.readdata_out (burst_converted_readdata),
.readdatavalid_out (burst_converted_readdatavalid),
.byteenable_in (burst_converted_byteenable),
.waitrequest_out (burst_converted_waitrequest),
.addr_out (vga_mem_address),
.write_out (vga_mem_write),
.writedata_out (vga_mem_writedata),
.read_out (vga_mem_read),
.readdata_in (vga_mem_readdata),
.readdatavalid_in (vga_mem_readdatavalid),
.waitrequest_in (0)
);
endmodule |
module burst_converter
#(
parameter IADDR = 32,
parameter OADDR = 32
)
(
input wire clk_sys,
input wire rst,
input wire [IADDR-1:0] addr_in,
input wire write_in,
input wire [31:0] writedata_in,
input wire read_in,
output wire [31:0] readdata_out,
output wire readdatavalid_out,
input wire [3:0] byteenable_in,
input wire [2:0] burstcount_in,
output wire waitrequest_out,
output wire [OADDR-1:0] addr_out,
output wire write_out,
output wire [31:0] writedata_out,
output wire read_out,
input wire [31:0] readdata_in,
input wire readdatavalid_in,
output wire [3:0] byteenable_out,
input wire waitrequest_in
);
// data
// data[8] = valid bit
reg [IADDR-1:0] raddr, waddr;
reg [3:0] rcount, wcount;
assign addr_out = (rcount[1]) ? raddr + 4 :
(rcount[2]) ? raddr + 8 :
(rcount[3]) ? raddr + 12 :
(wcount[1]) ? waddr + 4 :
(wcount[2]) ? waddr + 8 :
(wcount[3]) ? waddr + 12 : addr_in;
assign writedata_out = writedata_in;
assign byteenable_out = byteenable_in;
assign write_out = write_in;
assign read_out = (read_in && burstcount_in != 0) || rcount;
assign readdata_out = readdata_in;
assign readdatavalid_out = readdatavalid_in;
assign waitrequest_out = waitrequest_in;
/////////////////////////////////////////////////////////////////////////
// burst write
/////////////////////////////////////////////////////////////////////////
always @(posedge clk_sys) begin
if(rst) begin
wcount <= 0;
waddr <= 0;
end else if(wcount[1] && !waitrequest_in) begin
wcount[1] <= 0;
end else if(wcount[2] && !waitrequest_in) begin
wcount[2] <= 0;
end else if(wcount[3] && !waitrequest_in) begin
wcount[3] <= 0;
end else if(burstcount_in > 1 && write_in && !waitrequest_out) begin
waddr <= addr_in;
wcount <= (burstcount_in == 4) ? 4'b1110 :
(burstcount_in == 3) ? 4'b0110 :
(burstcount_in == 2) ? 4'b0010 : 0;
end
end
/////////////////////////////////////////////////////////////////////////
// burst read
/////////////////////////////////////////////////////////////////////////
always @(posedge clk_sys) begin
if(rst) begin
rcount <= 0;
raddr <= 0;
end else if(rcount[1] && !waitrequest_in) begin
rcount[1] <= 0;
end else if(rcount[2] && !waitrequest_in) begin
rcount[2] <= 0;
end else if(rcount[3] && !waitrequest_in) begin
rcount[3] <= 0;
end else if(burstcount_in > 1 && read_in && !waitrequest_out) begin
raddr <= addr_in;
rcount <= (burstcount_in == 4) ? 4'b1110 :
(burstcount_in == 3) ? 4'b0110 :
(burstcount_in == 2) ? 4'b0010 : 0;
end
end
endmodule |
module to_sdram
(
input wire clk_sys,
input wire rst,
input wire ao486_rst,
// input pc_bus_sdram
input wire [31:0] pc_bus_sdram_address,
input wire [3:0] pc_bus_sdram_byteenable,
input wire pc_bus_sdram_read,
output wire [31:0] pc_bus_sdram_readdata,
input wire pc_bus_sdram_write,
input wire [31:0] pc_bus_sdram_writedata,
output wire pc_bus_sdram_waitrequest,
output wire pc_bus_sdram_readdatavalid,
input wire [2:0] pc_bus_sdram_burstcount,
// input driver_sd_avm
input wire [31:0] driver_sd_avm_address,
input wire driver_sd_avm_read,
output wire [31:0] driver_sd_avm_readdata,
input wire driver_sd_avm_write,
input wire [31:0] driver_sd_avm_writedata,
output wire driver_sd_avm_waitrequest,
output wire driver_sd_avm_readdatavalid,
// output sdram_mem
output wire [24:0] sdram_address,
output wire [3:0] sdram_byteenable,
output wire sdram_read,
input wire [31:0] sdram_readdata,
output wire sdram_write,
output wire [31:0] sdram_writedata,
input wire sdram_waitrequest,
input wire sdram_readdatavalid,
input wire sdram_chipselect
);
wire [31:0] burst_converted_address;
wire burst_converted_write;
wire [31:0] burst_converted_writedata;
wire burst_converted_read;
wire [31:0] burst_converted_readdata;
wire burst_converted_readdatavalid;
wire [3:0] burst_converted_byteenable;
wire burst_converted_waitrequest;
burst_converter #(.IADDR(32), .OADDR(27))
burst_converter (
.clk_sys (clk_sys),
.rst (rst),
.addr_in (pc_bus_sdram_address),
.write_in (pc_bus_sdram_write),
.writedata_in (pc_bus_sdram_writedata),
.read_in (pc_bus_sdram_read),
.readdata_out (pc_bus_sdram_readdata),
.readdatavalid_out (pc_bus_sdram_readdatavalid),
.byteenable_in (pc_bus_sdram_byteenable),
.burstcount_in (pc_bus_sdram_burstcount),
.waitrequest_out (pc_bus_sdram_waitrequest),
.addr_out (burst_converted_address),
.write_out (burst_converted_write),
.writedata_out (burst_converted_writedata),
.read_out (burst_converted_read),
.readdata_in (burst_converted_readdata),
.readdatavalid_in (burst_converted_readdatavalid),
.byteenable_out (burst_converted_byteenable),
.waitrequest_in (burst_converted_waitrequest)
);
assign sdram_address = (~ao486_rst) ? burst_converted_address[26:2] : driver_sd_avm_address[26:2];
assign sdram_byteenable = (~ao486_rst) ? burst_converted_byteenable : 4'b1111;
assign sdram_read = (~ao486_rst) ? burst_converted_read : (driver_sd_avm_read && driver_sd_avm_address[27]);
assign sdram_write = (~ao486_rst) ? burst_converted_write : (driver_sd_avm_write && driver_sd_avm_address[27]);
assign sdram_writedata = (~ao486_rst) ? burst_converted_writedata : driver_sd_avm_writedata;
assign burst_converted_readdata = (~ao486_rst) ? sdram_readdata : 0;
assign burst_converted_readdatavalid = (~ao486_rst) ? sdram_readdatavalid : 0;
assign burst_converted_waitrequest = (~ao486_rst) ? sdram_waitrequest : 0;
assign driver_sd_avm_readdata = (ao486_rst) ? sdram_readdata : 0;
assign driver_sd_avm_readdatavalid = (ao486_rst) ? sdram_readdatavalid : 0;
assign driver_sd_avm_waitrequest = (ao486_rst) ? sdram_waitrequest : 0;
endmodule |
module Frix(
input wire CLOCK_100,
input wire RST_IN,
// PSRAM
output wire PSRAM_CLK,
output wire PSRAM_ADV_N,
output wire PSRAM_CE_N,
output wire PSRAM_OE_N,
output wire PSRAM_WE_N,
output wire PSRAM_LB_N,
output wire PSRAM_UB_N,
inout wire [15:0] PSRAM_DATA,
output wire [22:0] PSRAM_ADDR,
//PS2 KEYBOARD
inout wire PS2_CLK,
inout wire PS2_DAT,
//SD
output wire SD_CLK,
inout wire SD_CMD,
inout wire [3:0] SD_DAT,
input wire SD_CD,
output wire SD_RESET,
//VGA
output wire VGA_HS,
output wire VGA_VS,
output wire [3:0] VGA_R,
output wire [3:0] VGA_G,
output wire [3:0] VGA_B,
//LED
output reg [15:0] LED
);
//------------------------------------------------------------------------------
wire clk_sys;
wire clk_vga;
wire clk_sound;
wire rst;
wire rst_n;
assign DRAM_CLK = clk_sys;
GEN gen(
.CLK_IN (CLOCK_100),
.RST_X_IN (~RST_IN),
.CLK_OUT (clk_sys),
.VGA_CLK_OUT (clk_vga),
.RST_X_OUT (rst_n)
);
assign SD_RESET = rst;
assign rst = ~rst_n;
//------------------------------------------------------------------------------
wire ao486_reset;
wire [7:0] VGA_R_8, VGA_G_8, VGA_B_8;
assign VGA_R = VGA_R_8[7:4];
assign VGA_G = VGA_G_8[7:4];
assign VGA_B = VGA_B_8[7:4];
//------------------------------------------------------------------------------
reg [25:0] cnt;
always @(posedge clk_sys) cnt <= cnt + 1;
always @(posedge clk_sys) begin
LED[0] <= cnt[25];
LED[1] <= ~rst;
LED[2] <= ~ao486_reset;
LED[3] <= ~SD_CD;
LED[4] <= ~SD_RESET;
LED[9:5] <= {~SD_CMD, ~SD_DAT};
LED[13:10] <= {~PSRAM_CE_N, ~PSRAM_OE_N, ~PSRAM_WE_N, ~PSRAM_ADV_N};
LED[15:14] <= {~PS2_CLK, ~PS2_DAT};
end
//------------------------------------------------------------------------------
system u0(
.clk_sys (clk_sys),
.reset_sys (rst),
.clk_vga (clk_vga),
.reset_vga (rst),
.vga_clock (VGA_CLK),
.vga_horiz_sync (VGA_HS),
.vga_vert_sync (VGA_VS),
.vga_r (VGA_R_8),
.vga_g (VGA_G_8),
.vga_b (VGA_B_8),
.PSRAM_CLK (PSRAM_CLK),
.PSRAM_ADV_N (PSRAM_ADV_N),
.PSRAM_CE_N (PSRAM_CE_N),
.PSRAM_OE_N (PSRAM_OE_N),
.PSRAM_WE_N (PSRAM_WE_N),
.PSRAM_LB_N (PSRAM_LB_N),
.PSRAM_UB_N (PSRAM_UB_N),
.PSRAM_DATA (PSRAM_DATA),
.PSRAM_ADDR (PSRAM_ADDR),
.sd_clk (SD_CLK),
.sd_dat (SD_DAT),
.sd_cmd (SD_CMD),
.ps2_kbclk (PS2_CLK),
.ps2_kbdat (PS2_DAT),
.reset_only_ao486 (ao486_reset)
);
endmodule |
module system (
input wire clk_sys,
input wire reset_sys,
input wire clk_vga,
input wire reset_vga,
output wire PSRAM_CLK,
output wire PSRAM_ADV_N,
output wire PSRAM_CE_N,
output wire PSRAM_OE_N,
output wire PSRAM_WE_N,
output wire PSRAM_LB_N,
output wire PSRAM_UB_N,
inout wire [15:0] PSRAM_DATA,
output wire [22:0] PSRAM_ADDR,
output wire reset_only_ao486,
output wire vga_clock,
output wire vga_sync_n,
output wire vga_blank_n,
output wire vga_horiz_sync,
output wire vga_vert_sync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b,
inout wire ps2_kbclk,
inout wire ps2_kbdat,
inout wire [3:0] sd_dat,
inout wire sd_cmd,
output wire sd_clk
);
wire [7:0] ide_3f6_writedata;
wire ide_3f6_write;
wire ide_3f6_read;
wire [7:0] ide_3f6_readdata;
wire pic_interrupt_do;
wire [7:0] pic_interrupt_vector;
wire ao486_interrupt_done;
wire bios_loader_waitrequest;
wire [31:0] bios_loader_writedata;
wire [27:0] bios_loader_address;
wire bios_loader_write;
wire bios_loader_read;
wire [31:0] bios_loader_readdata;
wire bios_loader_debugaccess;
wire [3:0] bios_loader_byteenable;
wire hdd_avalon_master_waitrequest;
wire [31:0] hdd_avalon_master_writedata;
wire [31:0] hdd_avalon_master_address;
wire hdd_avalon_master_write;
wire hdd_avalon_master_read;
wire [31:0] hdd_avalon_master_readdata;
wire hdd_avalon_master_readdatavalid;
wire ao486_avalon_memory_waitrequest;
wire [2:0] ao486_avalon_memory_burstcount;
wire [31:0] ao486_avalon_memory_writedata;
wire [31:0] ao486_avalon_memory_address;
wire ao486_avalon_memory_write;
wire ao486_avalon_memory_read;
wire [31:0] ao486_avalon_memory_readdata;
wire ao486_avalon_memory_readdatavalid;
wire [3:0] ao486_avalon_memory_byteenable;
wire ao486_avalon_io_waitrequest;
wire [31:0] ao486_avalon_io_writedata;
wire [15:0] ao486_avalon_io_address;
wire ao486_avalon_io_write;
wire ao486_avalon_io_read;
wire [31:0] ao486_avalon_io_readdata;
wire ao486_avalon_io_readdatavalid;
wire [3:0] ao486_avalon_io_byteenable;
wire [3:0] vga_io_b_address;
wire vga_io_b_write;
wire [7:0] vga_io_b_writedata;
wire vga_io_b_read;
wire [7:0] vga_io_b_readdata;
wire [3:0] vga_io_c_address;
wire vga_io_c_write;
wire [7:0] vga_io_c_writedata;
wire vga_io_c_read;
wire [7:0] vga_io_c_readdata;
wire [3:0] vga_io_d_address;
wire vga_io_d_write;
wire [7:0] vga_io_d_writedata;
wire vga_io_d_read;
wire [7:0] vga_io_d_readdata;
wire [2:0] ps2_io_address;
wire ps2_io_write;
wire [7:0] ps2_io_writedata;
wire ps2_io_read;
wire [7:0] ps2_io_readdata;
wire [3:0] ps2_sysctl_address;
wire ps2_sysctl_write;
wire [7:0] ps2_sysctl_writedata;
wire ps2_sysctl_read;
wire [7:0] ps2_sysctl_readdata;
wire [1:0] pit_io_address;
wire pit_io_write;
wire [7:0] pit_io_writedata;
wire pit_io_read;
wire [7:0] pit_io_readdata;
wire rtc_io_address;
wire rtc_io_write;
wire [7:0] rtc_io_writedata;
wire rtc_io_read;
wire [7:0] rtc_io_readdata;
wire pic_master_address;
wire pic_master_write;
wire [7:0] pic_master_writedata;
wire pic_master_read;
wire [7:0] pic_master_readdata;
wire pic_slave_address;
wire pic_slave_write;
wire [7:0] pic_slave_writedata;
wire pic_slave_read;
wire [7:0] pic_slave_readdata;
wire hdd_io_address;
wire hdd_io_write;
wire [31:0] hdd_io_writedata;
wire hdd_io_read;
wire [31:0] hdd_io_readdata;
wire [3:0] hdd_io_byteenable;
wire pc_bus_mem_waitrequest;
wire [2:0] pc_bus_mem_burstcount;
wire [31:0] pc_bus_mem_writedata;
wire [29:0] pc_bus_mem_address;
wire pc_bus_mem_write;
wire pc_bus_mem_read;
wire [31:0] pc_bus_mem_readdata;
wire pc_bus_mem_readdatavalid;
wire [3:0] pc_bus_mem_byteenable;
wire pc_bus_vga_waitrequest;
wire [2:0] pc_bus_vga_burstcount;
wire [31:0] pc_bus_vga_writedata;
wire [31:0] pc_bus_vga_address;
wire pc_bus_vga_write;
wire pc_bus_vga_read;
wire [31:0] pc_bus_vga_readdata;
wire pc_bus_vga_readdatavalid;
wire [3:0] pc_bus_vga_byteenable;
wire [16:0] vga_mem_address;
wire vga_mem_read;
wire [7:0] vga_mem_readdata;
wire vga_mem_write;
wire [7:0] vga_mem_writedata;
wire [8:0] hdd_sd_slave_address;
wire hdd_sd_slave_read;
wire [31:0] hdd_sd_slave_readdata;
wire hdd_sd_slave_write;
wire [31:0] hdd_sd_slave_writedata;
wire [24:0] sdram_address;
wire [3:0] sdram_byteenable;
wire sdram_read;
wire [31:0] sdram_readdata;
wire sdram_write;
wire [31:0] sdram_writedata;
wire sdram_waitrequest;
wire sdram_readdatavalid;
wire sdram_chipselect;
wire [31:0] pc_bus_sdram_address;
wire pc_bus_sdram_read;
wire [31:0] pc_bus_sdram_readdata;
wire pc_bus_sdram_write;
wire [31:0] pc_bus_sdram_writedata;
wire pc_bus_sdram_waitrequest;
wire pc_bus_sdram_readdatavalid;
wire [2:0] pc_bus_sdram_burstcount;
wire [3:0] pc_bus_sdram_byteenable;
wire [31:0] driver_sd_avm_address;
wire driver_sd_avm_read;
wire [31:0] driver_sd_avm_readdata;
wire driver_sd_avm_write;
wire [31:0] driver_sd_avm_writedata;
wire driver_sd_avm_waitrequest;
wire driver_sd_avm_readdatavalid;
wire [31:0] driver_sd_avm_readdata_from_sdram;
wire driver_sd_avm_readdatavalid_from_sdram;
wire driver_sd_avm_waitrequest_from_sdram;
wire ps2_irq_keyb;
wire ps2_irq_mouse;
wire pit_irq;
wire rtc_irq;
wire floppy_irq;
wire hdd_irq;
wire [15:0] pic_interrupt_input;
wire ao486_rst;
assign reset_only_ao486 = ao486_rst;
wire [1:0] driver_sd_avs_address;
wire driver_sd_avs_read;
wire [31:0] driver_sd_avs_readdata;
wire driver_sd_avs_write;
wire [31:0] driver_sd_avs_writedata;
ao486 ao486 (
.clk (clk_sys),
.rst (ao486_rst),
.avm_address (ao486_avalon_memory_address),
.avm_writedata (ao486_avalon_memory_writedata),
.avm_byteenable (ao486_avalon_memory_byteenable),
.avm_burstcount (ao486_avalon_memory_burstcount),
.avm_write (ao486_avalon_memory_write),
.avm_read (ao486_avalon_memory_read),
.avm_waitrequest (ao486_avalon_memory_waitrequest),
.avm_readdatavalid (ao486_avalon_memory_readdatavalid),
.avm_readdata (ao486_avalon_memory_readdata),
.interrupt_do (pic_interrupt_do),
.interrupt_vector (pic_interrupt_vector),
.interrupt_done (ao486_interrupt_done),
.avalon_io_address (ao486_avalon_io_address),
.avalon_io_byteenable (ao486_avalon_io_byteenable),
.avalon_io_read (ao486_avalon_io_read),
.avalon_io_readdatavalid (ao486_avalon_io_readdatavalid),
.avalon_io_readdata (ao486_avalon_io_readdata),
.avalon_io_write (ao486_avalon_io_write),
.avalon_io_writedata (ao486_avalon_io_writedata),
.avalon_io_waitrequest (ao486_avalon_io_waitrequest)
);
bios_loader bios_loader (
.clk (clk_sys),
.rst (reset_sys),
.address (bios_loader_address),
.byteenable (bios_loader_byteenable),
.read (bios_loader_read),
.readdata (bios_loader_readdata),
.waitrequest (bios_loader_waitrequest),
.write (bios_loader_write),
.writedata (bios_loader_writedata)
);
pc_bus pc_bus (
.clk (clk_sys),
.mem_address (pc_bus_mem_address),
.mem_byteenable (pc_bus_mem_byteenable),
.mem_read (pc_bus_mem_read),
.mem_readdata (pc_bus_mem_readdata),
.mem_write (pc_bus_mem_write),
.mem_writedata (pc_bus_mem_writedata),
.mem_waitrequest (pc_bus_mem_waitrequest),
.mem_readdatavalid (pc_bus_mem_readdatavalid),
.mem_burstcount (pc_bus_mem_burstcount),
.rst (reset_sys),
.vga_address (pc_bus_vga_address),
.vga_byteenable (pc_bus_vga_byteenable),
.vga_read (pc_bus_vga_read),
.vga_readdata (pc_bus_vga_readdata),
.vga_write (pc_bus_vga_write),
.vga_writedata (pc_bus_vga_writedata),
.vga_waitrequest (pc_bus_vga_waitrequest),
.vga_readdatavalid (pc_bus_vga_readdatavalid),
.vga_burstcount (pc_bus_vga_burstcount),
.sdram_address (pc_bus_sdram_address),
.sdram_byteenable (pc_bus_sdram_byteenable),
.sdram_read (pc_bus_sdram_read),
.sdram_readdata (pc_bus_sdram_readdata),
.sdram_write (pc_bus_sdram_write),
.sdram_writedata (pc_bus_sdram_writedata),
.sdram_waitrequest (pc_bus_sdram_waitrequest),
.sdram_readdatavalid (pc_bus_sdram_readdatavalid),
.sdram_burstcount (pc_bus_sdram_burstcount)
);
vga vga (
.io_b_address (vga_io_b_address),
.io_b_read (vga_io_b_read),
.io_b_readdata (vga_io_b_readdata),
.io_b_write (vga_io_b_write),
.io_b_writedata (vga_io_b_writedata),
.io_c_address (vga_io_c_address),
.io_c_read (vga_io_c_read),
.io_c_readdata (vga_io_c_readdata),
.io_c_write (vga_io_c_write),
.io_c_writedata (vga_io_c_writedata),
.io_d_address (vga_io_d_address),
.io_d_read (vga_io_d_read),
.io_d_readdata (vga_io_d_readdata),
.io_d_write (vga_io_d_write),
.io_d_writedata (vga_io_d_writedata),
.mem_address (vga_mem_address),
.mem_read (vga_mem_read),
.mem_readdata (vga_mem_readdata),
.mem_write (vga_mem_write),
.mem_writedata (vga_mem_writedata),
.clk_sys (clk_sys),
.clk_26 (clk_vga),
.rst (reset_vga),
.vga_clock (vga_clock),
.vga_sync_n (vga_sync_n),
.vga_blank_n (vga_blank_n),
.vga_horiz_sync (vga_horiz_sync),
.vga_vert_sync (vga_vert_sync),
.vga_r (vga_r),
.vga_g (vga_g),
.vga_b (vga_b)
);
psramcon psramcon (
.clk (clk_sys),
.reset (reset_sys),
.az_addr (sdram_address),
.az_be_n (~sdram_byteenable),
.az_cs (sdram_chipselect),
.az_data (sdram_writedata),
.az_rd_n (~sdram_read),
.az_wr_n (~sdram_write),
.za_data (sdram_readdata),
.za_valid (sdram_readdatavalid),
.za_waitrequest (sdram_waitrequest),
.PSRAM_CLK (PSRAM_CLK),
.PSRAM_ADV_N (PSRAM_ADV_N),
.PSRAM_CE_N (PSRAM_CE_N),
.PSRAM_OE_N (PSRAM_OE_N),
.PSRAM_WE_N (PSRAM_WE_N),
.PSRAM_LB_N (PSRAM_LB_N),
.PSRAM_UB_N (PSRAM_UB_N),
.PSRAM_DATA (PSRAM_DATA),
.PSRAM_ADDR (PSRAM_ADDR)
);
rtc rtc (
.clk (clk_sys),
.io_address (rtc_io_address),
.io_read (rtc_io_read),
.io_readdata (rtc_io_readdata),
.io_write (rtc_io_write),
.io_writedata (rtc_io_writedata),
.rst (reset_sys),
.irq (rtc_irq)
);
pit pit (
.clk (clk_sys),
.io_address (pit_io_address),
.io_read (pit_io_read),
.io_readdata (pit_io_readdata),
.io_write (pit_io_write),
.io_writedata (pit_io_writedata),
.rst (reset_sys),
.irq (pit_irq)
);
assign pic_interrupt_input = {1'b0, hdd_irq, 1'b0, ps2_irq_mouse, 3'b0, rtc_irq, 6'b0, ps2_irq_keyb, pit_irq};
pic pic (
.clk (clk_sys),
.master_address (pic_master_address),
.master_read (pic_master_read),
.master_readdata (pic_master_readdata),
.master_write (pic_master_write),
.master_writedata (pic_master_writedata),
.slave_address (pic_slave_address),
.slave_read (pic_slave_read),
.slave_readdata (pic_slave_readdata),
.slave_write (pic_slave_write),
.slave_writedata (pic_slave_writedata),
.rst (reset_sys),
.interrupt_vector (pic_interrupt_vector),
.interrupt_done (ao486_interrupt_done),
.interrupt_do (pic_interrupt_do),
.interrupt_input (pic_interrupt_input)
);
hdd hdd (
.clk (clk_sys),
.io_address (hdd_io_address),
.io_byteenable (hdd_io_byteenable),
.io_read (hdd_io_read),
.io_readdata (hdd_io_readdata),
.io_write (hdd_io_write),
.io_writedata (hdd_io_writedata),
.sd_slave_address (hdd_sd_slave_address),
.sd_slave_read (hdd_sd_slave_read),
.sd_slave_readdata (hdd_sd_slave_readdata),
.sd_slave_write (hdd_sd_slave_write),
.sd_slave_writedata (hdd_sd_slave_writedata),
.rst (reset_sys),
.irq (hdd_irq),
.sd_master_address (hdd_avalon_master_address),
.sd_master_waitrequest (hdd_avalon_master_waitrequest),
.sd_master_read (hdd_avalon_master_read),
.sd_master_readdatavalid (hdd_avalon_master_readdatavalid),
.sd_master_readdata (hdd_avalon_master_readdata),
.sd_master_write (hdd_avalon_master_write),
.sd_master_writedata (hdd_avalon_master_writedata),
.ide_3f6_read (ide_3f6_read),
.ide_3f6_readdata (ide_3f6_readdata),
.ide_3f6_write (ide_3f6_write),
.ide_3f6_writedata (ide_3f6_writedata)
);
ao486_rst_controller ao486_rst_controller(
.clk_sys (clk_sys),
.rst (reset_sys),
.ao486_rst (ao486_rst),
.address (bios_loader_address[4:3]),
.write (bios_loader_write && bios_loader_address[15:4] == 12'h886),
.writedata (bios_loader_writedata)
);
ps2 ps2 (
.clk (clk_sys),
.io_address (ps2_io_address),
.io_read (ps2_io_read),
.io_readdata (ps2_io_readdata),
.io_write (ps2_io_write),
.io_writedata (ps2_io_writedata),
.sysctl_address (ps2_sysctl_address),
.sysctl_read (ps2_sysctl_read),
.sysctl_readdata (ps2_sysctl_readdata),
.sysctl_write (ps2_sysctl_write),
.sysctl_writedata (ps2_sysctl_writedata),
.rst (reset_sys),
.irq_mouse (ps2_irq_mouse),
.ps2_kbclk (ps2_kbclk),
.ps2_kbdat (ps2_kbdat),
.irq_keyb (ps2_irq_keyb)
);
driver_sd driver_sd (
.clk (clk_sys),
.avs_address (driver_sd_avs_address),
.avs_read (driver_sd_avs_read),
.avs_readdata (driver_sd_avs_readdata),
.avs_write (driver_sd_avs_write),
.avs_writedata (driver_sd_avs_writedata),
.avm_waitrequest (driver_sd_avm_waitrequest),
.avm_read (driver_sd_avm_read),
.avm_readdata (driver_sd_avm_readdata),
.avm_readdatavalid (driver_sd_avm_readdatavalid),
.avm_write (driver_sd_avm_write),
.avm_writedata (driver_sd_avm_writedata),
.avm_address (driver_sd_avm_address),
.rst (reset_sys),
.sd_cmd (sd_cmd),
.sd_dat (sd_dat),
.sd_clk (sd_clk)
);
assign hdd_sd_slave_address = driver_sd_avm_address[10:2];
assign hdd_sd_slave_read = driver_sd_avm_read && (driver_sd_avm_address[31:11] == 21'h000000);
assign hdd_sd_slave_write = driver_sd_avm_write && (driver_sd_avm_address[31:11] == 21'h000000);
assign hdd_sd_slave_writedata = driver_sd_avm_writedata;
reg hdd_sd_slave_readdatavalid;
always @(posedge clk_sys) hdd_sd_slave_readdatavalid <= hdd_sd_slave_read;
assign driver_sd_avm_readdata = (hdd_sd_slave_readdatavalid) ? hdd_sd_slave_readdata :
driver_sd_avm_readdata_from_sdram;
assign driver_sd_avm_readdatavalid = hdd_sd_slave_readdatavalid || driver_sd_avm_readdatavalid_from_sdram;
assign driver_sd_avm_waitrequest = driver_sd_avm_waitrequest_from_sdram;
to_sdram bus_to_sdram (
.clk_sys (clk_sys),
.rst (reset_sys),
.ao486_rst (ao486_rst),
.pc_bus_sdram_address (pc_bus_sdram_address),
.pc_bus_sdram_write (pc_bus_sdram_write),
.pc_bus_sdram_writedata (pc_bus_sdram_writedata),
.pc_bus_sdram_read (pc_bus_sdram_read),
.pc_bus_sdram_readdata (pc_bus_sdram_readdata),
.pc_bus_sdram_readdatavalid (pc_bus_sdram_readdatavalid),
.pc_bus_sdram_byteenable (pc_bus_sdram_byteenable),
.pc_bus_sdram_burstcount (pc_bus_sdram_burstcount),
.pc_bus_sdram_waitrequest (pc_bus_sdram_waitrequest),
.driver_sd_avm_address (driver_sd_avm_address),
.driver_sd_avm_write (driver_sd_avm_write),
.driver_sd_avm_writedata (driver_sd_avm_writedata),
.driver_sd_avm_read (driver_sd_avm_read),
.driver_sd_avm_readdata (driver_sd_avm_readdata_from_sdram),
.driver_sd_avm_readdatavalid (driver_sd_avm_readdatavalid_from_sdram),
.driver_sd_avm_waitrequest (driver_sd_avm_waitrequest_from_sdram),
.sdram_address (sdram_address),
.sdram_write (sdram_write),
.sdram_writedata (sdram_writedata),
.sdram_read (sdram_read),
.sdram_readdata (sdram_readdata),
.sdram_readdatavalid (sdram_readdatavalid),
.sdram_byteenable (sdram_byteenable),
.sdram_waitrequest (sdram_waitrequest),
.sdram_chipselect (sdram_chipselect)
);
to_driver_sd_avs bus_to_driver_sd_avs (
.clk_sys (clk_sys),
.rst (reset_sys),
.ao486_rst (ao486_rst),
.hdd_avalon_master_address (hdd_avalon_master_address),
.hdd_avalon_master_write (hdd_avalon_master_write),
.hdd_avalon_master_writedata (hdd_avalon_master_writedata),
.hdd_avalon_master_read (hdd_avalon_master_read),
.hdd_avalon_master_readdata (hdd_avalon_master_readdata),
.hdd_avalon_master_readdatavalid (hdd_avalon_master_readdatavalid),
.hdd_avalon_master_waitrequest (hdd_avalon_master_waitrequest),
.bios_loader_address (bios_loader_address),
.bios_loader_write (bios_loader_write),
.bios_loader_writedata (bios_loader_writedata),
.bios_loader_read (bios_loader_read),
.bios_loader_readdata (bios_loader_readdata),
.bios_loader_waitrequest (bios_loader_waitrequest),
.bios_loader_byteenable (bios_loader_byteenable),
.driver_sd_avs_address (driver_sd_avs_address),
.driver_sd_avs_write (driver_sd_avs_write),
.driver_sd_avs_writedata (driver_sd_avs_writedata),
.driver_sd_avs_read (driver_sd_avs_read),
.driver_sd_avs_readdata (driver_sd_avs_readdata)
);
pc_bus_to_vga pc_bus_to_vga (
.clk_sys (clk_sys),
.rst (reset_sys),
.pc_bus_vga_address (pc_bus_vga_address),
.pc_bus_vga_write (pc_bus_vga_write),
.pc_bus_vga_writedata (pc_bus_vga_writedata),
.pc_bus_vga_read (pc_bus_vga_read),
.pc_bus_vga_readdata (pc_bus_vga_readdata),
.pc_bus_vga_readdatavalid (pc_bus_vga_readdatavalid),
.pc_bus_vga_byteenable (pc_bus_vga_byteenable),
.pc_bus_vga_burstcount (pc_bus_vga_burstcount),
.pc_bus_vga_waitrequest (pc_bus_vga_waitrequest),
.vga_mem_address (vga_mem_address),
.vga_mem_write (vga_mem_write),
.vga_mem_writedata (vga_mem_writedata),
.vga_mem_read (vga_mem_read),
.vga_mem_readdata (vga_mem_readdata)
);
assign pc_bus_mem_address = ao486_avalon_memory_address[31:2];
assign pc_bus_mem_write = ao486_avalon_memory_write;
assign pc_bus_mem_read = ao486_avalon_memory_read;
assign pc_bus_mem_writedata = ao486_avalon_memory_writedata;
assign pc_bus_mem_byteenable = ao486_avalon_memory_byteenable;
assign pc_bus_mem_burstcount = ao486_avalon_memory_burstcount;
assign ao486_avalon_memory_readdata = pc_bus_mem_readdata;
assign ao486_avalon_memory_readdatavalid = pc_bus_mem_readdatavalid;
assign ao486_avalon_memory_waitrequest = pc_bus_mem_waitrequest;
io_bus io_bus(
.clk_sys (clk_sys),
.rst (reset_sys),
.ao486_avalon_io_address (ao486_avalon_io_address),
.ao486_avalon_io_waitrequest (ao486_avalon_io_waitrequest),
.ao486_avalon_io_byteenable (ao486_avalon_io_byteenable),
.ao486_avalon_io_read (ao486_avalon_io_read),
.ao486_avalon_io_readdata (ao486_avalon_io_readdata),
.ao486_avalon_io_readdatavalid (ao486_avalon_io_readdatavalid),
.ao486_avalon_io_write (ao486_avalon_io_write),
.ao486_avalon_io_writedata (ao486_avalon_io_writedata),
.vga_io_b_address (vga_io_b_address),
.vga_io_b_write (vga_io_b_write),
.vga_io_b_writedata (vga_io_b_writedata),
.vga_io_b_read (vga_io_b_read),
.vga_io_b_readdata (vga_io_b_readdata),
.vga_io_c_address (vga_io_c_address),
.vga_io_c_write (vga_io_c_write),
.vga_io_c_writedata (vga_io_c_writedata),
.vga_io_c_read (vga_io_c_read),
.vga_io_c_readdata (vga_io_c_readdata),
.vga_io_d_address (vga_io_d_address),
.vga_io_d_write (vga_io_d_write),
.vga_io_d_writedata (vga_io_d_writedata),
.vga_io_d_read (vga_io_d_read),
.vga_io_d_readdata (vga_io_d_readdata),
.ps2_io_address (ps2_io_address),
.ps2_io_write (ps2_io_write),
.ps2_io_writedata (ps2_io_writedata),
.ps2_io_read (ps2_io_read),
.ps2_io_readdata (ps2_io_readdata),
.ps2_sysctl_address (ps2_sysctl_address),
.ps2_sysctl_write (ps2_sysctl_write),
.ps2_sysctl_writedata (ps2_sysctl_writedata),
.ps2_sysctl_read (ps2_sysctl_read),
.ps2_sysctl_readdata (ps2_sysctl_readdata),
.pit_io_address (pit_io_address),
.pit_io_write (pit_io_write),
.pit_io_writedata (pit_io_writedata),
.pit_io_read (pit_io_read),
.pit_io_readdata (pit_io_readdata),
.rtc_io_address (rtc_io_address),
.rtc_io_write (rtc_io_write),
.rtc_io_writedata (rtc_io_writedata),
.rtc_io_read (rtc_io_read),
.rtc_io_readdata (rtc_io_readdata),
.pic_master_address (pic_master_address),
.pic_master_write (pic_master_write),
.pic_master_writedata (pic_master_writedata),
.pic_master_read (pic_master_read),
.pic_master_readdata (pic_master_readdata),
.pic_slave_address (pic_slave_address),
.pic_slave_write (pic_slave_write),
.pic_slave_writedata (pic_slave_writedata),
.pic_slave_read (pic_slave_read),
.pic_slave_readdata (pic_slave_readdata),
.hdd_io_address (hdd_io_address),
.hdd_io_write (hdd_io_write),
.hdd_io_writedata (hdd_io_writedata),
.hdd_io_read (hdd_io_read),
.hdd_io_readdata (hdd_io_readdata),
.hdd_io_byteenable (hdd_io_byteenable),
.ide_3f6_write (ide_3f6_write),
.ide_3f6_writedata (ide_3f6_writedata),
.ide_3f6_read (ide_3f6_read),
.ide_3f6_readdata (ide_3f6_readdata)
);
endmodule |
module GEN( input wire CLK_IN,
input wire RST_X_IN,
output wire CLK_OUT,
output wire VGA_CLK_OUT,
output wire RST_X_OUT
);
wire LOCKED, VLOCKED, CLK_IBUF;
wire RST_X_BUF;
clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED);
RSTGEN rstgen(CLK_OUT, (RST_X_IN & LOCKED), RST_X_OUT);
endmodule |
module RSTGEN(CLK, RST_X_I, RST_X_O);
input CLK, RST_X_I;
output RST_X_O;
reg [23:0] cnt;
assign RST_X_O = cnt[23];
always @(posedge CLK or negedge RST_X_I) begin
if (!RST_X_I) cnt <= 0;
else if (~RST_X_O) cnt <= (cnt + 1'b1);
end
endmodule |
Subsets and Splits