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module mux_tree_tapbuf_size5_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] pReset;
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule |
module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] pReset;
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:16] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[16];
//
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[3]),
.Q(mem_out[4]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[4]),
.Q(mem_out[5]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[5]),
.Q(mem_out[6]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[6]),
.Q(mem_out[7]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[7]),
.Q(mem_out[8]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[8]),
.Q(mem_out[9]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[9]),
.Q(mem_out[10]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[10]),
.Q(mem_out[11]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[11]),
.Q(mem_out[12]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[12]),
.Q(mem_out[13]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[13]),
.Q(mem_out[14]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[14]),
.Q(mem_out[15]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(mem_out[15]),
.Q(mem_out[16]));
endmodule |
module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem(pReset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] pReset;
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:0] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[0];
//
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(pReset[0]),
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
endmodule |
module io_sky130_fd_sc_hd__dfrtp_1_mem
(
ccff_head,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input prog_clk;
input prog_reset;
output ccff_tail;
output mem_out;
wire ccff_head;
wire ccff_tail;
wire mem_out;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out;
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(prog_reset),
.Q(mem_out)
);
endmodule |
module mux_tree_tapbuf_size8_mem
(
ccff_head,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:3]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:3]mem_out;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
endmodule |
module mux_tree_tapbuf_size3_mem
(
ccff_head,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:1]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:1]mem_out;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[1];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
endmodule |
module const0
(
const0
);
output const0;
wire \<const0> ;
wire const0;
assign const0 = \<const0> ;
endmodule |
module sb_1__0_
(
ccff_head,
chanx_left_in,
chanx_right_in,
chany_top_in,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
ccff_tail,
chanx_left_out,
chanx_right_out,
chany_top_out
);
input ccff_head;
input [0:29]chanx_left_in;
input [0:29]chanx_right_in;
input [0:29]chany_top_in;
input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
output ccff_tail;
output [0:29]chanx_left_out;
output [0:29]chanx_right_out;
output [0:29]chany_top_out;
wire ccff_head;
wire ccff_tail;
wire [0:29]chanx_left_in;
wire [0:29]chanx_left_out;
wire [0:29]chanx_right_in;
wire [0:29]chanx_right_out;
wire [0:29]chany_top_in;
wire [0:29]chany_top_out;
wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:2]mux_left_track_11_undriven_sram_inv;
wire [0:2]mux_left_track_13_undriven_sram_inv;
wire [0:2]mux_left_track_1_undriven_sram_inv;
wire [0:2]mux_left_track_21_undriven_sram_inv;
wire [0:2]mux_left_track_29_undriven_sram_inv;
wire [0:2]mux_left_track_37_undriven_sram_inv;
wire [0:2]mux_left_track_3_undriven_sram_inv;
wire [0:2]mux_left_track_45_undriven_sram_inv;
wire [0:2]mux_left_track_53_undriven_sram_inv;
wire [0:2]mux_left_track_5_undriven_sram_inv;
wire [0:2]mux_left_track_7_undriven_sram_inv;
wire [0:2]mux_right_track_0_undriven_sram_inv;
wire [0:2]mux_right_track_10_undriven_sram_inv;
wire [0:2]mux_right_track_12_undriven_sram_inv;
wire [0:2]mux_right_track_20_undriven_sram_inv;
wire [0:2]mux_right_track_28_undriven_sram_inv;
wire [0:2]mux_right_track_2_undriven_sram_inv;
wire [0:2]mux_right_track_36_undriven_sram_inv;
wire [0:1]mux_right_track_44_undriven_sram_inv;
wire [0:2]mux_right_track_4_undriven_sram_inv;
wire [0:1]mux_right_track_52_undriven_sram_inv;
wire [0:2]mux_right_track_6_undriven_sram_inv;
wire [0:2]mux_top_track_0_undriven_sram_inv;
wire [0:2]mux_top_track_10_undriven_sram_inv;
wire [0:2]mux_top_track_12_undriven_sram_inv;
wire [0:2]mux_top_track_14_undriven_sram_inv;
wire [0:2]mux_top_track_16_undriven_sram_inv;
wire [0:2]mux_top_track_18_undriven_sram_inv;
wire [0:1]mux_top_track_20_undriven_sram_inv;
wire [0:1]mux_top_track_22_undriven_sram_inv;
wire [0:1]mux_top_track_24_undriven_sram_inv;
wire [0:1]mux_top_track_26_undriven_sram_inv;
wire [0:1]mux_top_track_28_undriven_sram_inv;
wire [0:2]mux_top_track_2_undriven_sram_inv;
wire [0:1]mux_top_track_30_undriven_sram_inv;
wire [0:1]mux_top_track_32_undriven_sram_inv;
wire [0:1]mux_top_track_34_undriven_sram_inv;
wire [0:1]mux_top_track_36_undriven_sram_inv;
wire [0:1]mux_top_track_40_undriven_sram_inv;
wire [0:1]mux_top_track_42_undriven_sram_inv;
wire [0:1]mux_top_track_44_undriven_sram_inv;
wire [0:1]mux_top_track_46_undriven_sram_inv;
wire [0:1]mux_top_track_48_undriven_sram_inv;
wire [0:2]mux_top_track_4_undriven_sram_inv;
wire [0:1]mux_top_track_50_undriven_sram_inv;
wire [0:1]mux_top_track_58_undriven_sram_inv;
wire [0:2]mux_top_track_6_undriven_sram_inv;
wire [0:2]mux_top_track_8_undriven_sram_inv;
wire [0:1]mux_tree_tapbuf_size2_0_sram;
wire [0:1]mux_tree_tapbuf_size2_10_sram;
wire [0:1]mux_tree_tapbuf_size2_1_sram;
wire [0:1]mux_tree_tapbuf_size2_2_sram;
wire [0:1]mux_tree_tapbuf_size2_3_sram;
wire [0:1]mux_tree_tapbuf_size2_4_sram;
wire [0:1]mux_tree_tapbuf_size2_5_sram;
wire [0:1]mux_tree_tapbuf_size2_6_sram;
wire [0:1]mux_tree_tapbuf_size2_7_sram;
wire [0:1]mux_tree_tapbuf_size2_8_sram;
wire [0:1]mux_tree_tapbuf_size2_9_sram;
wire mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1]mux_tree_tapbuf_size3_0_sram;
wire [0:1]mux_tree_tapbuf_size3_1_sram;
wire [0:1]mux_tree_tapbuf_size3_2_sram;
wire [0:1]mux_tree_tapbuf_size3_3_sram;
wire [0:1]mux_tree_tapbuf_size3_4_sram;
wire [0:1]mux_tree_tapbuf_size3_5_sram;
wire [0:1]mux_tree_tapbuf_size3_6_sram;
wire mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:2]mux_tree_tapbuf_size4_0_sram;
wire [0:2]mux_tree_tapbuf_size4_1_sram;
wire [0:2]mux_tree_tapbuf_size4_2_sram;
wire [0:2]mux_tree_tapbuf_size4_3_sram;
wire [0:2]mux_tree_tapbuf_size4_4_sram;
wire [0:2]mux_tree_tapbuf_size4_5_sram;
wire mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:2]mux_tree_tapbuf_size5_0_sram;
wire [0:2]mux_tree_tapbuf_size5_1_sram;
wire [0:2]mux_tree_tapbuf_size5_2_sram;
wire [0:2]mux_tree_tapbuf_size5_3_sram;
wire [0:2]mux_tree_tapbuf_size5_4_sram;
wire [0:2]mux_tree_tapbuf_size5_5_sram;
wire mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
wire [0:2]mux_tree_tapbuf_size6_0_sram;
wire [0:2]mux_tree_tapbuf_size6_10_sram;
wire [0:2]mux_tree_tapbuf_size6_11_sram;
wire [0:2]mux_tree_tapbuf_size6_12_sram;
wire [0:2]mux_tree_tapbuf_size6_1_sram;
wire [0:2]mux_tree_tapbuf_size6_2_sram;
wire [0:2]mux_tree_tapbuf_size6_3_sram;
wire [0:2]mux_tree_tapbuf_size6_4_sram;
wire [0:2]mux_tree_tapbuf_size6_5_sram;
wire [0:2]mux_tree_tapbuf_size6_6_sram;
wire [0:2]mux_tree_tapbuf_size6_7_sram;
wire [0:2]mux_tree_tapbuf_size6_8_sram;
wire [0:2]mux_tree_tapbuf_size6_9_sram;
wire mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire mux_tree_tapbuf_size6_mem_10_ccff_tail;
wire mux_tree_tapbuf_size6_mem_11_ccff_tail;
wire mux_tree_tapbuf_size6_mem_12_ccff_tail;
wire mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire mux_tree_tapbuf_size6_mem_6_ccff_tail;
wire mux_tree_tapbuf_size6_mem_7_ccff_tail;
wire mux_tree_tapbuf_size6_mem_8_ccff_tail;
wire mux_tree_tapbuf_size6_mem_9_ccff_tail;
wire [0:2]mux_tree_tapbuf_size7_0_sram;
wire [0:2]mux_tree_tapbuf_size7_1_sram;
wire [0:2]mux_tree_tapbuf_size7_2_sram;
wire [0:2]mux_tree_tapbuf_size7_3_sram;
wire [0:2]mux_tree_tapbuf_size7_4_sram;
wire mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
assign chany_top_out[19] = top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
assign chanx_left_out[4] = chanx_right_in[3];
assign chanx_left_out[17] = chanx_right_in[16];
assign chanx_left_out[19] = chanx_right_in[18];
assign chanx_left_out[20] = chanx_right_in[19];
assign chanx_left_out[21] = chanx_right_in[20];
assign chanx_left_out[23] = chanx_right_in[22];
assign chanx_left_out[24] = chanx_right_in[23];
assign chanx_left_out[25] = chanx_right_in[24];
assign chanx_left_out[27] = chanx_right_in[26];
assign chanx_left_out[28] = chanx_right_in[27];
assign chanx_left_out[29] = chanx_right_in[28];
assign chanx_left_out[7] = chanx_right_in[6];
assign chany_top_out[28] = chanx_left_in[2];
assign chanx_right_out[4] = chanx_left_in[3];
assign chany_top_out[27] = chanx_left_in[4];
assign chany_top_out[26] = chanx_left_in[5];
assign chanx_right_out[7] = chanx_left_in[6];
assign chanx_right_out[8] = chanx_left_in[7];
assign chanx_right_out[9] = chanx_left_in[8];
assign chanx_right_out[11] = chanx_left_in[10];
assign chanx_right_out[12] = chanx_left_in[11];
assign chanx_right_out[13] = chanx_left_in[12];
assign chanx_left_out[8] = chanx_right_in[7];
assign chanx_right_out[15] = chanx_left_in[14];
assign chanx_right_out[16] = chanx_left_in[15];
assign chanx_right_out[17] = chanx_left_in[16];
assign chanx_right_out[19] = chanx_left_in[18];
assign chanx_right_out[20] = chanx_left_in[19];
assign chanx_right_out[21] = chanx_left_in[20];
assign chanx_right_out[23] = chanx_left_in[22];
assign chanx_right_out[24] = chanx_left_in[23];
assign chanx_right_out[25] = chanx_left_in[24];
assign chanx_right_out[27] = chanx_left_in[26];
assign chanx_left_out[9] = chanx_right_in[8];
assign chanx_right_out[28] = chanx_left_in[27];
assign chanx_right_out[29] = chanx_left_in[28];
assign chanx_left_out[11] = chanx_right_in[10];
assign chanx_left_out[12] = chanx_right_in[11];
assign chanx_left_out[13] = chanx_right_in[12];
assign chanx_left_out[15] = chanx_right_in[14];
assign chanx_left_out[16] = chanx_right_in[15];
mux_tree_tapbuf_size7_mem mem_left_track_1
(
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_3_sram)
);
mux_tree_tapbuf_size7_mem mem_left_track_11
(
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_4_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_13
(
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_10_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_21
(
.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_11_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_29
(
.ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_12_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_3
(
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_37
(
.ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_5_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_45
(
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_5
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_4_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_53
(
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_7
(
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_9_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_0
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram)
);
mux_tree_tapbuf_size7_mem mem_right_track_10
(
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_2_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_12
(
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_2
(
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_20
(
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_28
(
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_8_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_36
(
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_4
(
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_44
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_52
(
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram)
);
mux_tree_tapbuf_size7_mem mem_right_track_6
(
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_1_sram)
);
mux_tree_tapbuf_size7_mem mem_top_track_0
(
.ccff_head(ccff_head),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_0_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_10
(
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_12
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_14
(
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_16
(
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_18
(
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_2
(
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_20
(
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_22
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_24
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_26
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_28
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_30
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_32
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_34
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_36
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_4
(
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_40
(
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_42
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_46
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_48
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_50
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_58
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_6
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_8
(
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram)
);
mux_tree_tapbuf_size7 mux_left_track_1
(
.in({chany_top_in[0], chany_top_in[11], chany_top_in[22], chanx_right_in[3], chanx_right_in[19], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size7_3_sram),
.sram_inv(mux_left_track_1_undriven_sram_inv),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size7 mux_left_track_11
(
.in({chany_top_in[7], chany_top_in[18], chany_top_in[29], chanx_right_in[10], chanx_right_in[24], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size7_4_sram),
.sram_inv(mux_left_track_11_undriven_sram_inv),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size6 mux_left_track_13
(
.in({chany_top_in[6], chany_top_in[17], chany_top_in[28], chanx_right_in[11], chanx_right_in[26], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size6_10_sram),
.sram_inv(mux_left_track_13_undriven_sram_inv),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size6 mux_left_track_21
(
.in({chany_top_in[5], chany_top_in[16], chany_top_in[27], chanx_right_in[12], chanx_right_in[27], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size6_11_sram),
.sram_inv(mux_left_track_21_undriven_sram_inv),
.out(chanx_left_out[10])
);
mux_tree_tapbuf_size6 mux_left_track_29
(
.in({chany_top_in[4], chany_top_in[15], chany_top_in[26], chanx_right_in[14], chanx_right_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size6_12_sram),
.sram_inv(mux_left_track_29_undriven_sram_inv),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size5 mux_left_track_3
(
.in({chany_top_in[10], chany_top_in[21], chanx_right_in[6], chanx_right_in[20], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size5_3_sram),
.sram_inv(mux_left_track_3_undriven_sram_inv),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size5 mux_left_track_37
(
.in({chany_top_in[3], chany_top_in[14], chany_top_in[25], chanx_right_in[15], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size5_5_sram),
.sram_inv(mux_left_track_37_undriven_sram_inv),
.out(chanx_left_out[18])
);
mux_tree_tapbuf_size4 mux_left_track_45
(
.in({chany_top_in[2], chany_top_in[13], chany_top_in[24], chanx_right_in[16]}),
.sram(mux_tree_tapbuf_size4_4_sram),
.sram_inv(mux_left_track_45_undriven_sram_inv),
.out(chanx_left_out[22])
);
mux_tree_tapbuf_size5 mux_left_track_5
(
.in({chany_top_in[9], chany_top_in[20], chanx_right_in[7], chanx_right_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size5_4_sram),
.sram_inv(mux_left_track_5_undriven_sram_inv),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size4 mux_left_track_53
(
.in({chany_top_in[1], chany_top_in[12], chany_top_in[23], chanx_right_in[18]}),
.sram(mux_tree_tapbuf_size4_5_sram),
.sram_inv(mux_left_track_53_undriven_sram_inv),
.out(chanx_left_out[26])
);
mux_tree_tapbuf_size6 mux_left_track_7
(
.in({chany_top_in[8], chany_top_in[19], chanx_right_in[8], chanx_right_in[23], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size6_9_sram),
.sram_inv(mux_left_track_7_undriven_sram_inv),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size6 mux_right_track_0
(
.in({chany_top_in[10], chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3], chanx_left_in[19]}),
.sram(mux_tree_tapbuf_size6_3_sram),
.sram_inv(mux_right_track_0_undriven_sram_inv),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size7 mux_right_track_10
(
.in({chany_top_in[3], chany_top_in[14], chany_top_in[25], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10], chanx_left_in[24]}),
.sram(mux_tree_tapbuf_size7_2_sram),
.sram_inv(mux_right_track_10_undriven_sram_inv),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size6 mux_right_track_12
(
.in({chany_top_in[4], chany_top_in[15], chany_top_in[26], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[11], chanx_left_in[26]}),
.sram(mux_tree_tapbuf_size6_6_sram),
.sram_inv(mux_right_track_12_undriven_sram_inv),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size6 mux_right_track_2
(
.in({chany_top_in[0], chany_top_in[11], chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[6], chanx_left_in[20]}),
.sram(mux_tree_tapbuf_size6_4_sram),
.sram_inv(mux_right_track_2_undriven_sram_inv),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size6 mux_right_track_20
(
.in({chany_top_in[5], chany_top_in[16], chany_top_in[27], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[12], chanx_left_in[27]}),
.sram(mux_tree_tapbuf_size6_7_sram),
.sram_inv(mux_right_track_20_undriven_sram_inv),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size6 mux_right_track_28
(
.in({chany_top_in[6], chany_top_in[17], chany_top_in[28], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14], chanx_left_in[28]}),
.sram(mux_tree_tapbuf_size6_8_sram),
.sram_inv(mux_right_track_28_undriven_sram_inv),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size5 mux_right_track_36
(
.in({chany_top_in[7], chany_top_in[18], chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[15]}),
.sram(mux_tree_tapbuf_size5_2_sram),
.sram_inv(mux_right_track_36_undriven_sram_inv),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size6 mux_right_track_4
(
.in({chany_top_in[1], chany_top_in[12], chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[7], chanx_left_in[22]}),
.sram(mux_tree_tapbuf_size6_5_sram),
.sram_inv(mux_right_track_4_undriven_sram_inv),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size3 mux_right_track_44
(
.in({chany_top_in[8], chany_top_in[19], chanx_left_in[16]}),
.sram(mux_tree_tapbuf_size3_5_sram),
.sram_inv(mux_right_track_44_undriven_sram_inv),
.out(chanx_right_out[22])
);
mux_tree_tapbuf_size3 mux_right_track_52
(
.in({chany_top_in[9], chany_top_in[20], chanx_left_in[18]}),
.sram(mux_tree_tapbuf_size3_6_sram),
.sram_inv(mux_right_track_52_undriven_sram_inv),
.out(chanx_right_out[26])
);
mux_tree_tapbuf_size7 mux_right_track_6
(
.in({chany_top_in[2], chany_top_in[13], chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[8], chanx_left_in[23]}),
.sram(mux_tree_tapbuf_size7_1_sram),
.sram_inv(mux_right_track_6_undriven_sram_inv),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size7 mux_top_track_0
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[1], chanx_right_in[3], chanx_left_in[0], chanx_left_in[3]}),
.sram(mux_tree_tapbuf_size7_0_sram),
.sram_inv(mux_top_track_0_undriven_sram_inv),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size5 mux_top_track_10
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[11], chanx_right_in[13], chanx_left_in[11]}),
.sram(mux_tree_tapbuf_size5_1_sram),
.sram_inv(mux_top_track_10_undriven_sram_inv),
.out(chany_top_out[5])
);
mux_tree_tapbuf_size4 mux_top_track_12
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[12], chanx_right_in[17], chanx_left_in[12]}),
.sram(mux_tree_tapbuf_size4_0_sram),
.sram_inv(mux_top_track_12_undriven_sram_inv),
.out(chany_top_out[6])
);
mux_tree_tapbuf_size4 mux_top_track_14
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_right_in[14], chanx_right_in[21], chanx_left_in[14]}),
.sram(mux_tree_tapbuf_size4_1_sram),
.sram_inv(mux_top_track_14_undriven_sram_inv),
.out(chany_top_out[7])
);
mux_tree_tapbuf_size4 mux_top_track_16
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_right_in[15], chanx_right_in[25], chanx_left_in[15]}),
.sram(mux_tree_tapbuf_size4_2_sram),
.sram_inv(mux_top_track_16_undriven_sram_inv),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size4 mux_top_track_18
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_right_in[16], chanx_right_in[29], chanx_left_in[16]}),
.sram(mux_tree_tapbuf_size4_3_sram),
.sram_inv(mux_top_track_18_undriven_sram_inv),
.out(chany_top_out[9])
);
mux_tree_tapbuf_size6 mux_top_track_2
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[2], chanx_right_in[6], chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size6_0_sram),
.sram_inv(mux_top_track_2_undriven_sram_inv),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size3 mux_top_track_20
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_right_in[18], chanx_left_in[18]}),
.sram(mux_tree_tapbuf_size3_0_sram),
.sram_inv(mux_top_track_20_undriven_sram_inv),
.out(chany_top_out[10])
);
mux_tree_tapbuf_size3 mux_top_track_22
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[19], chanx_left_in[19]}),
.sram(mux_tree_tapbuf_size3_1_sram),
.sram_inv(mux_top_track_22_undriven_sram_inv),
.out(chany_top_out[11])
);
mux_tree_tapbuf_size3 mux_top_track_24
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[20], chanx_left_in[20]}),
.sram(mux_tree_tapbuf_size3_2_sram),
.sram_inv(mux_top_track_24_undriven_sram_inv),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size3 mux_top_track_26
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[22], chanx_left_in[22]}),
.sram(mux_tree_tapbuf_size3_3_sram),
.sram_inv(mux_top_track_26_undriven_sram_inv),
.out(chany_top_out[13])
);
mux_tree_tapbuf_size2 mux_top_track_28
(
.in({chanx_right_in[23], chanx_left_in[23]}),
.sram(mux_tree_tapbuf_size2_0_sram),
.sram_inv(mux_top_track_28_undriven_sram_inv),
.out(chany_top_out[14])
);
mux_tree_tapbuf_size2 mux_top_track_30
(
.in({chanx_right_in[24], chanx_left_in[24]}),
.sram(mux_tree_tapbuf_size2_1_sram),
.sram_inv(mux_top_track_30_undriven_sram_inv),
.out(chany_top_out[15])
);
mux_tree_tapbuf_size2 mux_top_track_32
(
.in({chanx_right_in[26], chanx_left_in[26]}),
.sram(mux_tree_tapbuf_size2_2_sram),
.sram_inv(mux_top_track_32_undriven_sram_inv),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size2 mux_top_track_34
(
.in({chanx_right_in[27], chanx_left_in[27]}),
.sram(mux_tree_tapbuf_size2_3_sram),
.sram_inv(mux_top_track_34_undriven_sram_inv),
.out(chany_top_out[17])
);
mux_tree_tapbuf_size3 mux_top_track_36
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_right_in[28], chanx_left_in[28]}),
.sram(mux_tree_tapbuf_size3_4_sram),
.sram_inv(mux_top_track_36_undriven_sram_inv),
.out(chany_top_out[18])
);
mux_tree_tapbuf_size5 mux_top_track_4
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_right_in[4], chanx_right_in[7], chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size5_0_sram),
.sram_inv(mux_top_track_4_undriven_sram_inv),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size2 mux_top_track_40
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[29]}),
.sram(mux_tree_tapbuf_size2_4_sram),
.sram_inv(mux_top_track_40_undriven_sram_inv),
.out(chany_top_out[20])
);
mux_tree_tapbuf_size2 mux_top_track_42
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[25]}),
.sram(mux_tree_tapbuf_size2_5_sram),
.sram_inv(mux_top_track_42_undriven_sram_inv),
.out(chany_top_out[21])
);
mux_tree_tapbuf_size2 mux_top_track_44
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[21]}),
.sram(mux_tree_tapbuf_size2_6_sram),
.sram_inv(mux_top_track_44_undriven_sram_inv),
.out(chany_top_out[22])
);
mux_tree_tapbuf_size2 mux_top_track_46
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[17]}),
.sram(mux_tree_tapbuf_size2_7_sram),
.sram_inv(mux_top_track_46_undriven_sram_inv),
.out(chany_top_out[23])
);
mux_tree_tapbuf_size2 mux_top_track_48
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[13]}),
.sram(mux_tree_tapbuf_size2_8_sram),
.sram_inv(mux_top_track_48_undriven_sram_inv),
.out(chany_top_out[24])
);
mux_tree_tapbuf_size2 mux_top_track_50
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size2_9_sram),
.sram_inv(mux_top_track_50_undriven_sram_inv),
.out(chany_top_out[25])
);
mux_tree_tapbuf_size2 mux_top_track_58
(
.in({chanx_right_in[0], chanx_left_in[1]}),
.sram(mux_tree_tapbuf_size2_10_sram),
.sram_inv(mux_top_track_58_undriven_sram_inv),
.out(chany_top_out[29])
);
mux_tree_tapbuf_size6 mux_top_track_6
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_right_in[5], chanx_right_in[8], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size6_1_sram),
.sram_inv(mux_top_track_6_undriven_sram_inv),
.out(chany_top_out[3])
);
mux_tree_tapbuf_size6 mux_top_track_8
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_right_in[9], chanx_right_in[10], chanx_left_in[10]}),
.sram(mux_tree_tapbuf_size6_2_sram),
.sram_inv(mux_top_track_8_undriven_sram_inv),
.out(chany_top_out[4])
);
endmodule |
module const1
(
const1
);
output const1;
wire \<const1> ;
wire const1;
assign const1 = \<const1> ;
endmodule |
module mux_tree_tapbuf_size9_mem
(
ccff_head,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:3]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:3]mem_out;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
endmodule |
module sb_0__8_
(
bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_head,
chanx_right_in,
chany_bottom_in,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail,
chanx_right_out,
chany_bottom_out
);
input bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
input bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
input bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
input bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
input ccff_head;
input [0:29]chanx_right_in;
input [0:29]chany_bottom_in;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
output [0:29]chanx_right_out;
output [0:29]chany_bottom_out;
wire bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
wire bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
wire bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
wire bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
wire ccff_head;
wire ccff_tail;
wire [0:29]chanx_right_in;
wire [0:29]chanx_right_out;
wire [0:29]chany_bottom_in;
wire [0:29]chany_bottom_out;
wire [0:1]mux_bottom_track_11_undriven_sram_inv;
wire [0:1]mux_bottom_track_13_undriven_sram_inv;
wire [0:1]mux_bottom_track_15_undriven_sram_inv;
wire [0:1]mux_bottom_track_17_undriven_sram_inv;
wire [0:1]mux_bottom_track_19_undriven_sram_inv;
wire [0:1]mux_bottom_track_1_undriven_sram_inv;
wire [0:1]mux_bottom_track_29_undriven_sram_inv;
wire [0:1]mux_bottom_track_31_undriven_sram_inv;
wire [0:1]mux_bottom_track_33_undriven_sram_inv;
wire [0:1]mux_bottom_track_35_undriven_sram_inv;
wire [0:1]mux_bottom_track_3_undriven_sram_inv;
wire [0:1]mux_bottom_track_45_undriven_sram_inv;
wire [0:1]mux_bottom_track_47_undriven_sram_inv;
wire [0:1]mux_bottom_track_49_undriven_sram_inv;
wire [0:1]mux_bottom_track_51_undriven_sram_inv;
wire [0:1]mux_bottom_track_5_undriven_sram_inv;
wire [0:1]mux_bottom_track_7_undriven_sram_inv;
wire [0:1]mux_bottom_track_9_undriven_sram_inv;
wire [0:2]mux_right_track_0_undriven_sram_inv;
wire [0:2]mux_right_track_10_undriven_sram_inv;
wire [0:1]mux_right_track_12_undriven_sram_inv;
wire [0:1]mux_right_track_14_undriven_sram_inv;
wire [0:1]mux_right_track_16_undriven_sram_inv;
wire [0:1]mux_right_track_18_undriven_sram_inv;
wire [0:1]mux_right_track_20_undriven_sram_inv;
wire [0:1]mux_right_track_22_undriven_sram_inv;
wire [0:1]mux_right_track_24_undriven_sram_inv;
wire [0:1]mux_right_track_26_undriven_sram_inv;
wire [0:1]mux_right_track_28_undriven_sram_inv;
wire [0:2]mux_right_track_2_undriven_sram_inv;
wire [0:1]mux_right_track_30_undriven_sram_inv;
wire [0:1]mux_right_track_32_undriven_sram_inv;
wire [0:1]mux_right_track_34_undriven_sram_inv;
wire [0:1]mux_right_track_36_undriven_sram_inv;
wire [0:1]mux_right_track_38_undriven_sram_inv;
wire [0:1]mux_right_track_40_undriven_sram_inv;
wire [0:1]mux_right_track_42_undriven_sram_inv;
wire [0:1]mux_right_track_44_undriven_sram_inv;
wire [0:1]mux_right_track_46_undriven_sram_inv;
wire [0:1]mux_right_track_48_undriven_sram_inv;
wire [0:2]mux_right_track_4_undriven_sram_inv;
wire [0:1]mux_right_track_50_undriven_sram_inv;
wire [0:1]mux_right_track_52_undriven_sram_inv;
wire [0:1]mux_right_track_54_undriven_sram_inv;
wire [0:1]mux_right_track_56_undriven_sram_inv;
wire [0:1]mux_right_track_58_undriven_sram_inv;
wire [0:2]mux_right_track_6_undriven_sram_inv;
wire [0:2]mux_right_track_8_undriven_sram_inv;
wire [0:1]mux_tree_tapbuf_size2_0_sram;
wire [0:1]mux_tree_tapbuf_size2_10_sram;
wire [0:1]mux_tree_tapbuf_size2_11_sram;
wire [0:1]mux_tree_tapbuf_size2_12_sram;
wire [0:1]mux_tree_tapbuf_size2_13_sram;
wire [0:1]mux_tree_tapbuf_size2_14_sram;
wire [0:1]mux_tree_tapbuf_size2_15_sram;
wire [0:1]mux_tree_tapbuf_size2_16_sram;
wire [0:1]mux_tree_tapbuf_size2_17_sram;
wire [0:1]mux_tree_tapbuf_size2_18_sram;
wire [0:1]mux_tree_tapbuf_size2_19_sram;
wire [0:1]mux_tree_tapbuf_size2_1_sram;
wire [0:1]mux_tree_tapbuf_size2_20_sram;
wire [0:1]mux_tree_tapbuf_size2_21_sram;
wire [0:1]mux_tree_tapbuf_size2_22_sram;
wire [0:1]mux_tree_tapbuf_size2_23_sram;
wire [0:1]mux_tree_tapbuf_size2_24_sram;
wire [0:1]mux_tree_tapbuf_size2_25_sram;
wire [0:1]mux_tree_tapbuf_size2_26_sram;
wire [0:1]mux_tree_tapbuf_size2_27_sram;
wire [0:1]mux_tree_tapbuf_size2_28_sram;
wire [0:1]mux_tree_tapbuf_size2_2_sram;
wire [0:1]mux_tree_tapbuf_size2_3_sram;
wire [0:1]mux_tree_tapbuf_size2_4_sram;
wire [0:1]mux_tree_tapbuf_size2_5_sram;
wire [0:1]mux_tree_tapbuf_size2_6_sram;
wire [0:1]mux_tree_tapbuf_size2_7_sram;
wire [0:1]mux_tree_tapbuf_size2_8_sram;
wire [0:1]mux_tree_tapbuf_size2_9_sram;
wire mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire mux_tree_tapbuf_size2_mem_19_ccff_tail;
wire mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire mux_tree_tapbuf_size2_mem_20_ccff_tail;
wire mux_tree_tapbuf_size2_mem_21_ccff_tail;
wire mux_tree_tapbuf_size2_mem_22_ccff_tail;
wire mux_tree_tapbuf_size2_mem_23_ccff_tail;
wire mux_tree_tapbuf_size2_mem_24_ccff_tail;
wire mux_tree_tapbuf_size2_mem_25_ccff_tail;
wire mux_tree_tapbuf_size2_mem_26_ccff_tail;
wire mux_tree_tapbuf_size2_mem_27_ccff_tail;
wire mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1]mux_tree_tapbuf_size3_0_sram;
wire [0:1]mux_tree_tapbuf_size3_10_sram;
wire [0:1]mux_tree_tapbuf_size3_11_sram;
wire [0:1]mux_tree_tapbuf_size3_12_sram;
wire [0:1]mux_tree_tapbuf_size3_1_sram;
wire [0:1]mux_tree_tapbuf_size3_2_sram;
wire [0:1]mux_tree_tapbuf_size3_3_sram;
wire [0:1]mux_tree_tapbuf_size3_4_sram;
wire [0:1]mux_tree_tapbuf_size3_5_sram;
wire [0:1]mux_tree_tapbuf_size3_6_sram;
wire [0:1]mux_tree_tapbuf_size3_7_sram;
wire [0:1]mux_tree_tapbuf_size3_8_sram;
wire [0:1]mux_tree_tapbuf_size3_9_sram;
wire mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire mux_tree_tapbuf_size3_mem_10_ccff_tail;
wire mux_tree_tapbuf_size3_mem_11_ccff_tail;
wire mux_tree_tapbuf_size3_mem_12_ccff_tail;
wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire mux_tree_tapbuf_size3_mem_7_ccff_tail;
wire mux_tree_tapbuf_size3_mem_8_ccff_tail;
wire mux_tree_tapbuf_size3_mem_9_ccff_tail;
wire [0:2]mux_tree_tapbuf_size5_0_sram;
wire [0:2]mux_tree_tapbuf_size5_1_sram;
wire [0:2]mux_tree_tapbuf_size5_2_sram;
wire [0:2]mux_tree_tapbuf_size5_3_sram;
wire [0:2]mux_tree_tapbuf_size5_4_sram;
wire [0:2]mux_tree_tapbuf_size5_5_sram;
wire mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
assign chany_bottom_out[28] = chanx_right_in[0];
assign chany_bottom_out[27] = chanx_right_in[1];
assign chany_bottom_out[10] = chanx_right_in[18];
assign chany_bottom_out[29] = chanx_right_in[29];
assign chany_bottom_out[26] = chanx_right_in[2];
assign chany_bottom_out[21] = chanx_right_in[7];
assign chany_bottom_out[20] = chanx_right_in[8];
assign chany_bottom_out[19] = chanx_right_in[9];
assign chany_bottom_out[18] = chanx_right_in[10];
assign chany_bottom_out[13] = chanx_right_in[15];
assign chany_bottom_out[12] = chanx_right_in[16];
assign chany_bottom_out[11] = chanx_right_in[17];
mux_tree_tapbuf_size3_mem mem_bottom_track_1
(
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_11_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_11
(
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_13
(
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_15
(
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_18_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_17
(
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_19_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_19
(
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_20_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_29
(
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_21_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_3
(
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_31
(
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_22_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_33
(
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_23_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_35
(
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_24_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_45
(
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_25_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_47
(
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_26_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_49
(
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_27_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_5
(
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_51
(
.ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_28_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_7
(
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_12_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_9
(
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_0
(
.ccff_head(ccff_head),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_10
(
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_5_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_12
(
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_14
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_16
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_18
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_2
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_20
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_22
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_24
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_26
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_28
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_30
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_32
(
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_34
(
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_36
(
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_38
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_4
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_40
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_42
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_46
(
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_48
(
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_50
(
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_52
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_54
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_56
(
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_58
(
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_10_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_6
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_8
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_4_sram)
);
mux_tree_tapbuf_size3 mux_bottom_track_1
(
.in({chanx_right_in[28], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_11_sram),
.sram_inv(mux_bottom_track_1_undriven_sram_inv),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size2 mux_bottom_track_11
(
.in({chanx_right_in[23], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_16_sram),
.sram_inv(mux_bottom_track_11_undriven_sram_inv),
.out(chany_bottom_out[5])
);
mux_tree_tapbuf_size2 mux_bottom_track_13
(
.in({chanx_right_in[22], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_17_sram),
.sram_inv(mux_bottom_track_13_undriven_sram_inv),
.out(chany_bottom_out[6])
);
mux_tree_tapbuf_size2 mux_bottom_track_15
(
.in({chanx_right_in[21], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_18_sram),
.sram_inv(mux_bottom_track_15_undriven_sram_inv),
.out(chany_bottom_out[7])
);
mux_tree_tapbuf_size2 mux_bottom_track_17
(
.in({chanx_right_in[20], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_19_sram),
.sram_inv(mux_bottom_track_17_undriven_sram_inv),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size2 mux_bottom_track_19
(
.in({chanx_right_in[19], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_20_sram),
.sram_inv(mux_bottom_track_19_undriven_sram_inv),
.out(chany_bottom_out[9])
);
mux_tree_tapbuf_size2 mux_bottom_track_29
(
.in({chanx_right_in[14], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_21_sram),
.sram_inv(mux_bottom_track_29_undriven_sram_inv),
.out(chany_bottom_out[14])
);
mux_tree_tapbuf_size2 mux_bottom_track_3
(
.in({chanx_right_in[27], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_13_sram),
.sram_inv(mux_bottom_track_3_undriven_sram_inv),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size2 mux_bottom_track_31
(
.in({chanx_right_in[13], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_22_sram),
.sram_inv(mux_bottom_track_31_undriven_sram_inv),
.out(chany_bottom_out[15])
);
mux_tree_tapbuf_size2 mux_bottom_track_33
(
.in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_23_sram),
.sram_inv(mux_bottom_track_33_undriven_sram_inv),
.out(chany_bottom_out[16])
);
mux_tree_tapbuf_size2 mux_bottom_track_35
(
.in({chanx_right_in[11], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_24_sram),
.sram_inv(mux_bottom_track_35_undriven_sram_inv),
.out(chany_bottom_out[17])
);
mux_tree_tapbuf_size2 mux_bottom_track_45
(
.in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_25_sram),
.sram_inv(mux_bottom_track_45_undriven_sram_inv),
.out(chany_bottom_out[22])
);
mux_tree_tapbuf_size2 mux_bottom_track_47
(
.in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_26_sram),
.sram_inv(mux_bottom_track_47_undriven_sram_inv),
.out(chany_bottom_out[23])
);
mux_tree_tapbuf_size2 mux_bottom_track_49
(
.in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_27_sram),
.sram_inv(mux_bottom_track_49_undriven_sram_inv),
.out(chany_bottom_out[24])
);
mux_tree_tapbuf_size2 mux_bottom_track_5
(
.in({chanx_right_in[26], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_14_sram),
.sram_inv(mux_bottom_track_5_undriven_sram_inv),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size2 mux_bottom_track_51
(
.in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_28_sram),
.sram_inv(mux_bottom_track_51_undriven_sram_inv),
.out(chany_bottom_out[25])
);
mux_tree_tapbuf_size3 mux_bottom_track_7
(
.in({chanx_right_in[25], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_12_sram),
.sram_inv(mux_bottom_track_7_undriven_sram_inv),
.out(chany_bottom_out[3])
);
mux_tree_tapbuf_size2 mux_bottom_track_9
(
.in({chanx_right_in[24], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_15_sram),
.sram_inv(mux_bottom_track_9_undriven_sram_inv),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size5 mux_right_track_0
(
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[28]}),
.sram(mux_tree_tapbuf_size5_0_sram),
.sram_inv(mux_right_track_0_undriven_sram_inv),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size5 mux_right_track_10
(
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[23]}),
.sram(mux_tree_tapbuf_size5_5_sram),
.sram_inv(mux_right_track_10_undriven_sram_inv),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size3 mux_right_track_12
(
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[22]}),
.sram(mux_tree_tapbuf_size3_0_sram),
.sram_inv(mux_right_track_12_undriven_sram_inv),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size3 mux_right_track_14
(
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[21]}),
.sram(mux_tree_tapbuf_size3_1_sram),
.sram_inv(mux_right_track_14_undriven_sram_inv),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size3 mux_right_track_16
(
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[20]}),
.sram(mux_tree_tapbuf_size3_2_sram),
.sram_inv(mux_right_track_16_undriven_sram_inv),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2 mux_right_track_18
(
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[19]}),
.sram(mux_tree_tapbuf_size2_0_sram),
.sram_inv(mux_right_track_18_undriven_sram_inv),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size5 mux_right_track_2
(
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[27]}),
.sram(mux_tree_tapbuf_size5_1_sram),
.sram_inv(mux_right_track_2_undriven_sram_inv),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size2 mux_right_track_20
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[18]}),
.sram(mux_tree_tapbuf_size2_1_sram),
.sram_inv(mux_right_track_20_undriven_sram_inv),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size2 mux_right_track_22
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[17]}),
.sram(mux_tree_tapbuf_size2_2_sram),
.sram_inv(mux_right_track_22_undriven_sram_inv),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size2 mux_right_track_24
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[16]}),
.sram(mux_tree_tapbuf_size2_3_sram),
.sram_inv(mux_right_track_24_undriven_sram_inv),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size2 mux_right_track_26
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[15]}),
.sram(mux_tree_tapbuf_size2_4_sram),
.sram_inv(mux_right_track_26_undriven_sram_inv),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size3 mux_right_track_28
(
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[14]}),
.sram(mux_tree_tapbuf_size3_3_sram),
.sram_inv(mux_right_track_28_undriven_sram_inv),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size3 mux_right_track_30
(
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[13]}),
.sram(mux_tree_tapbuf_size3_4_sram),
.sram_inv(mux_right_track_30_undriven_sram_inv),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size3 mux_right_track_32
(
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[12]}),
.sram(mux_tree_tapbuf_size3_5_sram),
.sram_inv(mux_right_track_32_undriven_sram_inv),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size3 mux_right_track_34
(
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[11]}),
.sram(mux_tree_tapbuf_size3_6_sram),
.sram_inv(mux_right_track_34_undriven_sram_inv),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2 mux_right_track_36
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[10]}),
.sram(mux_tree_tapbuf_size2_5_sram),
.sram_inv(mux_right_track_36_undriven_sram_inv),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2 mux_right_track_38
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[9]}),
.sram(mux_tree_tapbuf_size2_6_sram),
.sram_inv(mux_right_track_38_undriven_sram_inv),
.out(chanx_right_out[19])
);
mux_tree_tapbuf_size5 mux_right_track_4
(
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[26]}),
.sram(mux_tree_tapbuf_size5_2_sram),
.sram_inv(mux_right_track_4_undriven_sram_inv),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size2 mux_right_track_40
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[8]}),
.sram(mux_tree_tapbuf_size2_7_sram),
.sram_inv(mux_right_track_40_undriven_sram_inv),
.out(chanx_right_out[20])
);
mux_tree_tapbuf_size2 mux_right_track_42
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, chany_bottom_in[7]}),
.sram(mux_tree_tapbuf_size2_8_sram),
.sram_inv(mux_right_track_42_undriven_sram_inv),
.out(chanx_right_out[21])
);
mux_tree_tapbuf_size3 mux_right_track_44
(
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[6]}),
.sram(mux_tree_tapbuf_size3_7_sram),
.sram_inv(mux_right_track_44_undriven_sram_inv),
.out(chanx_right_out[22])
);
mux_tree_tapbuf_size3 mux_right_track_46
(
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[5]}),
.sram(mux_tree_tapbuf_size3_8_sram),
.sram_inv(mux_right_track_46_undriven_sram_inv),
.out(chanx_right_out[23])
);
mux_tree_tapbuf_size3 mux_right_track_48
(
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[4]}),
.sram(mux_tree_tapbuf_size3_9_sram),
.sram_inv(mux_right_track_48_undriven_sram_inv),
.out(chanx_right_out[24])
);
mux_tree_tapbuf_size2 mux_right_track_50
(
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[3]}),
.sram(mux_tree_tapbuf_size2_9_sram),
.sram_inv(mux_right_track_50_undriven_sram_inv),
.out(chanx_right_out[25])
);
mux_tree_tapbuf_size2 mux_right_track_52
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[2]}),
.sram(mux_tree_tapbuf_size2_10_sram),
.sram_inv(mux_right_track_52_undriven_sram_inv),
.out(chanx_right_out[26])
);
mux_tree_tapbuf_size2 mux_right_track_54
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_, chany_bottom_in[1]}),
.sram(mux_tree_tapbuf_size2_11_sram),
.sram_inv(mux_right_track_54_undriven_sram_inv),
.out(chanx_right_out[27])
);
mux_tree_tapbuf_size2 mux_right_track_56
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[0]}),
.sram(mux_tree_tapbuf_size2_12_sram),
.sram_inv(mux_right_track_56_undriven_sram_inv),
.out(chanx_right_out[28])
);
mux_tree_tapbuf_size3 mux_right_track_58
(
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[29]}),
.sram(mux_tree_tapbuf_size3_10_sram),
.sram_inv(mux_right_track_58_undriven_sram_inv),
.out(chanx_right_out[29])
);
mux_tree_tapbuf_size5 mux_right_track_6
(
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[25]}),
.sram(mux_tree_tapbuf_size5_3_sram),
.sram_inv(mux_right_track_6_undriven_sram_inv),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size5 mux_right_track_8
(
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[24]}),
.sram(mux_tree_tapbuf_size5_4_sram),
.sram_inv(mux_right_track_8_undriven_sram_inv),
.out(chanx_right_out[4])
);
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
(
ff_D,
ff_DI,
ff_clk,
ff_reset,
test_enable,
ff_Q
);
input ff_D;
input ff_DI;
input ff_clk;
input ff_reset;
input test_enable;
output ff_Q;
wire ff_D;
wire ff_DI;
wire ff_Q;
wire ff_clk;
wire ff_reset;
wire test_enable;
sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
(
.CLK(ff_clk),
.D(ff_D),
.RESET_B(ff_reset),
.SCD(ff_DI),
.SCE(test_enable),
.Q(ff_Q)
);
endmodule |
module sb_8__0_
(
ccff_head,
chanx_left_in,
chany_top_in,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
prog_clk,
prog_reset,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail,
chanx_left_out,
chany_top_out
);
input ccff_head;
input [0:29]chanx_left_in;
input [0:29]chany_top_in;
input left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
input prog_clk;
input prog_reset;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
output [0:29]chanx_left_out;
output [0:29]chany_top_out;
wire ccff_head;
wire ccff_tail;
wire [0:29]chanx_left_in;
wire [0:29]chanx_left_out;
wire [0:29]chany_top_in;
wire [0:29]chany_top_out;
wire left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
wire left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:1]mux_left_track_11_undriven_sram_inv;
wire [0:1]mux_left_track_13_undriven_sram_inv;
wire [0:1]mux_left_track_15_undriven_sram_inv;
wire [0:1]mux_left_track_17_undriven_sram_inv;
wire [0:1]mux_left_track_19_undriven_sram_inv;
wire [0:1]mux_left_track_1_undriven_sram_inv;
wire [0:1]mux_left_track_29_undriven_sram_inv;
wire [0:1]mux_left_track_31_undriven_sram_inv;
wire [0:1]mux_left_track_33_undriven_sram_inv;
wire [0:1]mux_left_track_35_undriven_sram_inv;
wire [0:1]mux_left_track_3_undriven_sram_inv;
wire [0:1]mux_left_track_45_undriven_sram_inv;
wire [0:1]mux_left_track_47_undriven_sram_inv;
wire [0:1]mux_left_track_49_undriven_sram_inv;
wire [0:1]mux_left_track_51_undriven_sram_inv;
wire [0:1]mux_left_track_5_undriven_sram_inv;
wire [0:1]mux_left_track_7_undriven_sram_inv;
wire [0:1]mux_left_track_9_undriven_sram_inv;
wire [0:2]mux_top_track_0_undriven_sram_inv;
wire [0:2]mux_top_track_10_undriven_sram_inv;
wire [0:1]mux_top_track_12_undriven_sram_inv;
wire [0:1]mux_top_track_14_undriven_sram_inv;
wire [0:1]mux_top_track_16_undriven_sram_inv;
wire [0:1]mux_top_track_18_undriven_sram_inv;
wire [0:1]mux_top_track_20_undriven_sram_inv;
wire [0:1]mux_top_track_22_undriven_sram_inv;
wire [0:1]mux_top_track_24_undriven_sram_inv;
wire [0:1]mux_top_track_26_undriven_sram_inv;
wire [0:1]mux_top_track_28_undriven_sram_inv;
wire [0:2]mux_top_track_2_undriven_sram_inv;
wire [0:1]mux_top_track_30_undriven_sram_inv;
wire [0:1]mux_top_track_32_undriven_sram_inv;
wire [0:1]mux_top_track_34_undriven_sram_inv;
wire [0:1]mux_top_track_36_undriven_sram_inv;
wire [0:1]mux_top_track_38_undriven_sram_inv;
wire [0:1]mux_top_track_40_undriven_sram_inv;
wire [0:1]mux_top_track_42_undriven_sram_inv;
wire [0:1]mux_top_track_44_undriven_sram_inv;
wire [0:1]mux_top_track_46_undriven_sram_inv;
wire [0:1]mux_top_track_48_undriven_sram_inv;
wire [0:2]mux_top_track_4_undriven_sram_inv;
wire [0:1]mux_top_track_50_undriven_sram_inv;
wire [0:2]mux_top_track_6_undriven_sram_inv;
wire [0:2]mux_top_track_8_undriven_sram_inv;
wire [0:1]mux_tree_tapbuf_size2_0_sram;
wire [0:1]mux_tree_tapbuf_size2_10_sram;
wire [0:1]mux_tree_tapbuf_size2_11_sram;
wire [0:1]mux_tree_tapbuf_size2_12_sram;
wire [0:1]mux_tree_tapbuf_size2_13_sram;
wire [0:1]mux_tree_tapbuf_size2_14_sram;
wire [0:1]mux_tree_tapbuf_size2_15_sram;
wire [0:1]mux_tree_tapbuf_size2_16_sram;
wire [0:1]mux_tree_tapbuf_size2_17_sram;
wire [0:1]mux_tree_tapbuf_size2_18_sram;
wire [0:1]mux_tree_tapbuf_size2_19_sram;
wire [0:1]mux_tree_tapbuf_size2_1_sram;
wire [0:1]mux_tree_tapbuf_size2_20_sram;
wire [0:1]mux_tree_tapbuf_size2_21_sram;
wire [0:1]mux_tree_tapbuf_size2_22_sram;
wire [0:1]mux_tree_tapbuf_size2_23_sram;
wire [0:1]mux_tree_tapbuf_size2_24_sram;
wire [0:1]mux_tree_tapbuf_size2_25_sram;
wire [0:1]mux_tree_tapbuf_size2_26_sram;
wire [0:1]mux_tree_tapbuf_size2_27_sram;
wire [0:1]mux_tree_tapbuf_size2_2_sram;
wire [0:1]mux_tree_tapbuf_size2_3_sram;
wire [0:1]mux_tree_tapbuf_size2_4_sram;
wire [0:1]mux_tree_tapbuf_size2_5_sram;
wire [0:1]mux_tree_tapbuf_size2_6_sram;
wire [0:1]mux_tree_tapbuf_size2_7_sram;
wire [0:1]mux_tree_tapbuf_size2_8_sram;
wire [0:1]mux_tree_tapbuf_size2_9_sram;
wire mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire mux_tree_tapbuf_size2_mem_19_ccff_tail;
wire mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire mux_tree_tapbuf_size2_mem_20_ccff_tail;
wire mux_tree_tapbuf_size2_mem_21_ccff_tail;
wire mux_tree_tapbuf_size2_mem_22_ccff_tail;
wire mux_tree_tapbuf_size2_mem_23_ccff_tail;
wire mux_tree_tapbuf_size2_mem_24_ccff_tail;
wire mux_tree_tapbuf_size2_mem_25_ccff_tail;
wire mux_tree_tapbuf_size2_mem_26_ccff_tail;
wire mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1]mux_tree_tapbuf_size3_0_sram;
wire [0:1]mux_tree_tapbuf_size3_1_sram;
wire [0:1]mux_tree_tapbuf_size3_2_sram;
wire [0:1]mux_tree_tapbuf_size3_3_sram;
wire [0:1]mux_tree_tapbuf_size3_4_sram;
wire [0:1]mux_tree_tapbuf_size3_5_sram;
wire [0:1]mux_tree_tapbuf_size3_6_sram;
wire [0:1]mux_tree_tapbuf_size3_7_sram;
wire [0:1]mux_tree_tapbuf_size3_8_sram;
wire [0:1]mux_tree_tapbuf_size3_9_sram;
wire mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire mux_tree_tapbuf_size3_mem_7_ccff_tail;
wire mux_tree_tapbuf_size3_mem_8_ccff_tail;
wire mux_tree_tapbuf_size3_mem_9_ccff_tail;
wire [0:2]mux_tree_tapbuf_size5_0_sram;
wire [0:2]mux_tree_tapbuf_size5_1_sram;
wire [0:2]mux_tree_tapbuf_size5_2_sram;
wire [0:2]mux_tree_tapbuf_size5_3_sram;
wire [0:2]mux_tree_tapbuf_size5_4_sram;
wire [0:2]mux_tree_tapbuf_size5_5_sram;
wire mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
wire prog_clk;
wire prog_reset;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
assign chanx_left_out[29] = chany_top_in[1];
assign chanx_left_out[28] = chany_top_in[2];
assign chanx_left_out[11] = chany_top_in[19];
assign chanx_left_out[10] = chany_top_in[20];
assign chany_top_out[29] = chanx_left_in[1];
assign chany_top_out[28] = chanx_left_in[2];
assign chany_top_out[27] = chanx_left_in[3];
assign chany_top_out[26] = chanx_left_in[4];
assign chanx_left_out[27] = chany_top_in[3];
assign chanx_left_out[26] = chany_top_in[4];
assign chanx_left_out[21] = chany_top_in[9];
assign chanx_left_out[20] = chany_top_in[10];
assign chanx_left_out[19] = chany_top_in[11];
assign chanx_left_out[18] = chany_top_in[12];
assign chanx_left_out[13] = chany_top_in[17];
assign chanx_left_out[12] = chany_top_in[18];
mux_tree_tapbuf_size3_mem mem_left_track_1
(
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_11
(
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_13
(
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_15
(
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_17
(
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_18_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_19
(
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_19_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_29
(
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_20_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_3
(
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_31
(
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_21_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_33
(
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_22_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_35
(
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_23_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_45
(
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_24_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_47
(
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_25_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_49
(
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_26_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_5
(
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_51
(
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_27_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_7
(
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_9
(
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_0
(
.ccff_head(ccff_head),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_10
(
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_5_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_12
(
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_14
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_16
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_18
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_2
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_20
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_22
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_24
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_26
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_28
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_30
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_32
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_34
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_36
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_38
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_4
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_40
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_42
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_46
(
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_48
(
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_50
(
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_6
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_8
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_4_sram)
);
mux_tree_tapbuf_size3 mux_left_track_1
(
.in({chany_top_in[0], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_8_sram),
.sram_inv(mux_left_track_1_undriven_sram_inv),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size2 mux_left_track_11
(
.in({chany_top_in[25], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_15_sram),
.sram_inv(mux_left_track_11_undriven_sram_inv),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size2 mux_left_track_13
(
.in({chany_top_in[24], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_16_sram),
.sram_inv(mux_left_track_13_undriven_sram_inv),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size2 mux_left_track_15
(
.in({chany_top_in[23], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_17_sram),
.sram_inv(mux_left_track_15_undriven_sram_inv),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size2 mux_left_track_17
(
.in({chany_top_in[22], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_18_sram),
.sram_inv(mux_left_track_17_undriven_sram_inv),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size2 mux_left_track_19
(
.in({chany_top_in[21], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_19_sram),
.sram_inv(mux_left_track_19_undriven_sram_inv),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size2 mux_left_track_29
(
.in({chany_top_in[16], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_20_sram),
.sram_inv(mux_left_track_29_undriven_sram_inv),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2 mux_left_track_3
(
.in({chany_top_in[29], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_12_sram),
.sram_inv(mux_left_track_3_undriven_sram_inv),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size2 mux_left_track_31
(
.in({chany_top_in[15], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_21_sram),
.sram_inv(mux_left_track_31_undriven_sram_inv),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2 mux_left_track_33
(
.in({chany_top_in[14], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_22_sram),
.sram_inv(mux_left_track_33_undriven_sram_inv),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2 mux_left_track_35
(
.in({chany_top_in[13], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_23_sram),
.sram_inv(mux_left_track_35_undriven_sram_inv),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2 mux_left_track_45
(
.in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_24_sram),
.sram_inv(mux_left_track_45_undriven_sram_inv),
.out(chanx_left_out[22])
);
mux_tree_tapbuf_size2 mux_left_track_47
(
.in({chany_top_in[7], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_25_sram),
.sram_inv(mux_left_track_47_undriven_sram_inv),
.out(chanx_left_out[23])
);
mux_tree_tapbuf_size2 mux_left_track_49
(
.in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_26_sram),
.sram_inv(mux_left_track_49_undriven_sram_inv),
.out(chanx_left_out[24])
);
mux_tree_tapbuf_size2 mux_left_track_5
(
.in({chany_top_in[28], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_13_sram),
.sram_inv(mux_left_track_5_undriven_sram_inv),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size2 mux_left_track_51
(
.in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_27_sram),
.sram_inv(mux_left_track_51_undriven_sram_inv),
.out(chanx_left_out[25])
);
mux_tree_tapbuf_size3 mux_left_track_7
(
.in({chany_top_in[27], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_9_sram),
.sram_inv(mux_left_track_7_undriven_sram_inv),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size2 mux_left_track_9
(
.in({chany_top_in[26], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_14_sram),
.sram_inv(mux_left_track_9_undriven_sram_inv),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size5 mux_top_track_0
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[0]}),
.sram(mux_tree_tapbuf_size5_0_sram),
.sram_inv(mux_top_track_0_undriven_sram_inv),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size5 mux_top_track_10
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[25]}),
.sram(mux_tree_tapbuf_size5_5_sram),
.sram_inv(mux_top_track_10_undriven_sram_inv),
.out(chany_top_out[5])
);
mux_tree_tapbuf_size3 mux_top_track_12
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[24]}),
.sram(mux_tree_tapbuf_size3_0_sram),
.sram_inv(mux_top_track_12_undriven_sram_inv),
.out(chany_top_out[6])
);
mux_tree_tapbuf_size3 mux_top_track_14
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[23]}),
.sram(mux_tree_tapbuf_size3_1_sram),
.sram_inv(mux_top_track_14_undriven_sram_inv),
.out(chany_top_out[7])
);
mux_tree_tapbuf_size3 mux_top_track_16
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[22]}),
.sram(mux_tree_tapbuf_size3_2_sram),
.sram_inv(mux_top_track_16_undriven_sram_inv),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size3 mux_top_track_18
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[21]}),
.sram(mux_tree_tapbuf_size3_3_sram),
.sram_inv(mux_top_track_18_undriven_sram_inv),
.out(chany_top_out[9])
);
mux_tree_tapbuf_size5 mux_top_track_2
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[29]}),
.sram(mux_tree_tapbuf_size5_1_sram),
.sram_inv(mux_top_track_2_undriven_sram_inv),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size2 mux_top_track_20
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, chanx_left_in[20]}),
.sram(mux_tree_tapbuf_size2_0_sram),
.sram_inv(mux_top_track_20_undriven_sram_inv),
.out(chany_top_out[10])
);
mux_tree_tapbuf_size2 mux_top_track_22
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, chanx_left_in[19]}),
.sram(mux_tree_tapbuf_size2_1_sram),
.sram_inv(mux_top_track_22_undriven_sram_inv),
.out(chany_top_out[11])
);
mux_tree_tapbuf_size2 mux_top_track_24
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, chanx_left_in[18]}),
.sram(mux_tree_tapbuf_size2_2_sram),
.sram_inv(mux_top_track_24_undriven_sram_inv),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size2 mux_top_track_26
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, chanx_left_in[17]}),
.sram(mux_tree_tapbuf_size2_3_sram),
.sram_inv(mux_top_track_26_undriven_sram_inv),
.out(chany_top_out[13])
);
mux_tree_tapbuf_size2 mux_top_track_28
(
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[16]}),
.sram(mux_tree_tapbuf_size2_4_sram),
.sram_inv(mux_top_track_28_undriven_sram_inv),
.out(chany_top_out[14])
);
mux_tree_tapbuf_size2 mux_top_track_30
(
.in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[15]}),
.sram(mux_tree_tapbuf_size2_5_sram),
.sram_inv(mux_top_track_30_undriven_sram_inv),
.out(chany_top_out[15])
);
mux_tree_tapbuf_size2 mux_top_track_32
(
.in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[14]}),
.sram(mux_tree_tapbuf_size2_6_sram),
.sram_inv(mux_top_track_32_undriven_sram_inv),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size2 mux_top_track_34
(
.in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[13]}),
.sram(mux_tree_tapbuf_size2_7_sram),
.sram_inv(mux_top_track_34_undriven_sram_inv),
.out(chany_top_out[17])
);
mux_tree_tapbuf_size2 mux_top_track_36
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, chanx_left_in[12]}),
.sram(mux_tree_tapbuf_size2_8_sram),
.sram_inv(mux_top_track_36_undriven_sram_inv),
.out(chany_top_out[18])
);
mux_tree_tapbuf_size2 mux_top_track_38
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, chanx_left_in[11]}),
.sram(mux_tree_tapbuf_size2_9_sram),
.sram_inv(mux_top_track_38_undriven_sram_inv),
.out(chany_top_out[19])
);
mux_tree_tapbuf_size5 mux_top_track_4
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[28]}),
.sram(mux_tree_tapbuf_size5_2_sram),
.sram_inv(mux_top_track_4_undriven_sram_inv),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size2 mux_top_track_40
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_, chanx_left_in[10]}),
.sram(mux_tree_tapbuf_size2_10_sram),
.sram_inv(mux_top_track_40_undriven_sram_inv),
.out(chany_top_out[20])
);
mux_tree_tapbuf_size2 mux_top_track_42
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size2_11_sram),
.sram_inv(mux_top_track_42_undriven_sram_inv),
.out(chany_top_out[21])
);
mux_tree_tapbuf_size3 mux_top_track_44
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size3_4_sram),
.sram_inv(mux_top_track_44_undriven_sram_inv),
.out(chany_top_out[22])
);
mux_tree_tapbuf_size3 mux_top_track_46
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size3_5_sram),
.sram_inv(mux_top_track_46_undriven_sram_inv),
.out(chany_top_out[23])
);
mux_tree_tapbuf_size3 mux_top_track_48
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size3_6_sram),
.sram_inv(mux_top_track_48_undriven_sram_inv),
.out(chany_top_out[24])
);
mux_tree_tapbuf_size3 mux_top_track_50
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size3_7_sram),
.sram_inv(mux_top_track_50_undriven_sram_inv),
.out(chany_top_out[25])
);
mux_tree_tapbuf_size5 mux_top_track_6
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[27]}),
.sram(mux_tree_tapbuf_size5_3_sram),
.sram_inv(mux_top_track_6_undriven_sram_inv),
.out(chany_top_out[3])
);
mux_tree_tapbuf_size5 mux_top_track_8
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[26]}),
.sram(mux_tree_tapbuf_size5_4_sram),
.sram_inv(mux_top_track_8_undriven_sram_inv),
.out(chany_top_out[4])
);
endmodule |
module mux_tree_size2
(
in,
sram,
sram_inv,
out
);
input [0:1]in;
input [0:1]sram;
input [0:1]sram_inv;
output out;
wire const1_0_const1;
wire [0:1]in;
wire out;
wire sky130_fd_sc_hd__mux2_1_0_X;
wire [0:1]sram;
wire [0:1]sram_inv;
const1 const1_0_
(
.const1(const1_0_const1)
);
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
(
.A0(in[1]),
.A1(in[0]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X)
);
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
(
.A0(const1_0_const1),
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.S(sram[1]),
.X(out)
);
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric
(
ccff_head,
fabric_cin,
fabric_clk,
fabric_in,
fabric_reg_in,
fabric_reset,
fabric_sc_in,
prog_clk,
prog_reset,
test_enable,
ccff_tail,
fabric_cout,
fabric_out,
fabric_reg_out,
fabric_sc_out
);
input ccff_head;
input fabric_cin;
input fabric_clk;
input [0:3]fabric_in;
input fabric_reg_in;
input fabric_reset;
input fabric_sc_in;
input prog_clk;
input prog_reset;
input test_enable;
output ccff_tail;
output fabric_cout;
output [0:1]fabric_out;
output fabric_reg_out;
output fabric_sc_out;
wire ccff_head;
wire ccff_tail;
wire direct_interc_10_out;
wire direct_interc_11_out;
wire direct_interc_12_out;
wire direct_interc_13_out;
wire direct_interc_3_out;
wire direct_interc_4_out;
wire direct_interc_5_out;
wire direct_interc_6_out;
wire direct_interc_7_out;
wire direct_interc_8_out;
wire direct_interc_9_out;
wire fabric_cin;
wire fabric_clk;
wire fabric_cout;
wire [0:3]fabric_in;
wire [0:1]fabric_out;
wire fabric_reg_in;
wire fabric_reg_out;
wire fabric_reset;
wire fabric_sc_in;
wire fabric_sc_out;
wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
wire logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout;
wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
wire [0:1]mux_fabric_out_0_undriven_sram_inv;
wire [0:1]mux_fabric_out_1_undriven_sram_inv;
wire [0:1]mux_ff_0_D_0_undriven_sram_inv;
wire [0:1]mux_ff_1_D_0_undriven_sram_inv;
wire [0:1]mux_tree_size2_0_sram;
wire [0:1]mux_tree_size2_1_sram;
wire mux_tree_size2_2_out;
wire [0:1]mux_tree_size2_2_sram;
wire mux_tree_size2_3_out;
wire [0:1]mux_tree_size2_3_sram;
wire mux_tree_size2_mem_0_ccff_tail;
wire mux_tree_size2_mem_1_ccff_tail;
wire mux_tree_size2_mem_2_ccff_tail;
wire prog_clk;
wire prog_reset;
wire test_enable;
direct_interc direct_interc_0_
(
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q),
.out(fabric_reg_out)
);
direct_interc direct_interc_10_
(
.in(fabric_clk),
.out(direct_interc_10_out)
);
direct_interc direct_interc_11_
(
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q),
.out(direct_interc_11_out)
);
direct_interc direct_interc_12_
(
.in(fabric_reset),
.out(direct_interc_12_out)
);
direct_interc direct_interc_13_
(
.in(fabric_clk),
.out(direct_interc_13_out)
);
direct_interc direct_interc_1_
(
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q),
.out(fabric_sc_out)
);
direct_interc direct_interc_2_
(
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout),
.out(fabric_cout)
);
direct_interc direct_interc_3_
(
.in(fabric_in[0]),
.out(direct_interc_3_out)
);
direct_interc direct_interc_4_
(
.in(fabric_in[1]),
.out(direct_interc_4_out)
);
direct_interc direct_interc_5_
(
.in(fabric_in[2]),
.out(direct_interc_5_out)
);
direct_interc direct_interc_6_
(
.in(fabric_in[3]),
.out(direct_interc_6_out)
);
direct_interc direct_interc_7_
(
.in(fabric_cin),
.out(direct_interc_7_out)
);
direct_interc direct_interc_8_
(
.in(fabric_sc_in),
.out(direct_interc_8_out)
);
direct_interc direct_interc_9_
(
.in(fabric_reset),
.out(direct_interc_9_out)
);
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0
(
.ff_D(mux_tree_size2_2_out),
.ff_DI(direct_interc_8_out),
.ff_clk(direct_interc_10_out),
.ff_reset(direct_interc_9_out),
.test_enable(test_enable),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q)
);
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
(
.ff_D(mux_tree_size2_3_out),
.ff_DI(direct_interc_11_out),
.ff_clk(direct_interc_13_out),
.ff_reset(direct_interc_12_out),
.test_enable(test_enable),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q)
);
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0
(
.ccff_head(ccff_head),
.frac_logic_cin(direct_interc_7_out),
.frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout),
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out)
);
mux_tree_size2_mem mem_fabric_out_0
(
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
.mem_out(mux_tree_size2_0_sram)
);
mux_tree_size2_mem mem_fabric_out_1
(
.ccff_head(mux_tree_size2_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_size2_mem_1_ccff_tail),
.mem_out(mux_tree_size2_1_sram)
);
mux_tree_size2_mem mem_ff_0_D_0
(
.ccff_head(mux_tree_size2_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_size2_mem_2_ccff_tail),
.mem_out(mux_tree_size2_2_sram)
);
mux_tree_size2_mem mem_ff_1_D_0
(
.ccff_head(mux_tree_size2_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_size2_3_sram)
);
mux_tree_size2 mux_fabric_out_0
(
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
.sram(mux_tree_size2_0_sram),
.sram_inv(mux_fabric_out_0_undriven_sram_inv),
.out(fabric_out[0])
);
mux_tree_size2 mux_fabric_out_1
(
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
.sram(mux_tree_size2_1_sram),
.sram_inv(mux_fabric_out_1_undriven_sram_inv),
.out(fabric_out[1])
);
mux_tree_size2 mux_ff_0_D_0
(
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in}),
.sram(mux_tree_size2_2_sram),
.sram_inv(mux_ff_0_D_0_undriven_sram_inv),
.out(mux_tree_size2_2_out)
);
mux_tree_size2 mux_ff_1_D_0
(
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q}),
.sram(mux_tree_size2_3_sram),
.sram_inv(mux_ff_1_D_0_undriven_sram_inv),
.out(mux_tree_size2_3_out)
);
endmodule |
module mux_tree_tapbuf_size10
(
in,
sram,
sram_inv,
out
);
input [0:9]in;
input [0:3]sram;
input [0:3]sram_inv;
output out;
wire const1_0_const1;
wire [0:9]in;
wire out;
wire sky130_fd_sc_hd__mux2_1_0_X;
wire sky130_fd_sc_hd__mux2_1_1_X;
wire sky130_fd_sc_hd__mux2_1_2_X;
wire sky130_fd_sc_hd__mux2_1_3_X;
wire sky130_fd_sc_hd__mux2_1_4_X;
wire sky130_fd_sc_hd__mux2_1_5_X;
wire sky130_fd_sc_hd__mux2_1_6_X;
wire sky130_fd_sc_hd__mux2_1_7_X;
wire sky130_fd_sc_hd__mux2_1_8_X;
wire sky130_fd_sc_hd__mux2_1_9_X;
wire [0:3]sram;
wire [0:3]sram_inv;
const1 const1_0_
(
.const1(const1_0_const1)
);
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
(
.A0(in[1]),
.A1(in[0]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X)
);
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
(
.A0(in[3]),
.A1(in[2]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_1_X)
);
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_
(
.A0(in[5]),
.A1(in[4]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_2_X)
);
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
(
.A0(sky130_fd_sc_hd__mux2_1_1_X),
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_3_X)
);
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_
(
.A0(in[6]),
.A1(sky130_fd_sc_hd__mux2_1_2_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_4_X)
);
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_
(
.A0(in[8]),
.A1(in[7]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_5_X)
);
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_
(
.A0(const1_0_const1),
.A1(in[9]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_6_X)
);
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_
(
.A0(sky130_fd_sc_hd__mux2_1_4_X),
.A1(sky130_fd_sc_hd__mux2_1_3_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_7_X)
);
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_
(
.A0(sky130_fd_sc_hd__mux2_1_6_X),
.A1(sky130_fd_sc_hd__mux2_1_5_X),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_8_X)
);
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_
(
.A0(sky130_fd_sc_hd__mux2_1_8_X),
.A1(sky130_fd_sc_hd__mux2_1_7_X),
.S(sram[3]),
.X(sky130_fd_sc_hd__mux2_1_9_X)
);
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
(
.A(sky130_fd_sc_hd__mux2_1_9_X),
.X(out)
);
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower
(
carry_follower_a,
carry_follower_b,
carry_follower_cin,
carry_follower_cout
);
input carry_follower_a;
input carry_follower_b;
input carry_follower_cin;
output carry_follower_cout;
wire carry_follower_a;
wire carry_follower_b;
wire carry_follower_cin;
wire carry_follower_cout;
sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_
(
.A0(carry_follower_a),
.A1(carry_follower_b),
.S(carry_follower_cin),
.X(carry_follower_cout)
);
endmodule |
module sb_0__0_
(
ccff_head,
chanx_right_in,
chany_top_in,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail,
chanx_right_out,
chany_top_out
);
input ccff_head;
input [0:29]chanx_right_in;
input [0:29]chany_top_in;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
output [0:29]chanx_right_out;
output [0:29]chany_top_out;
wire ccff_head;
wire ccff_tail;
wire [0:29]chanx_right_in;
wire [0:29]chanx_right_out;
wire [0:29]chany_top_in;
wire [0:29]chany_top_out;
wire [0:1]mux_right_track_0_undriven_sram_inv;
wire [0:1]mux_right_track_10_undriven_sram_inv;
wire [0:1]mux_right_track_12_undriven_sram_inv;
wire [0:1]mux_right_track_14_undriven_sram_inv;
wire [0:1]mux_right_track_16_undriven_sram_inv;
wire [0:1]mux_right_track_18_undriven_sram_inv;
wire [0:1]mux_right_track_28_undriven_sram_inv;
wire [0:1]mux_right_track_2_undriven_sram_inv;
wire [0:1]mux_right_track_30_undriven_sram_inv;
wire [0:1]mux_right_track_32_undriven_sram_inv;
wire [0:1]mux_right_track_34_undriven_sram_inv;
wire [0:1]mux_right_track_44_undriven_sram_inv;
wire [0:1]mux_right_track_46_undriven_sram_inv;
wire [0:1]mux_right_track_48_undriven_sram_inv;
wire [0:1]mux_right_track_4_undriven_sram_inv;
wire [0:1]mux_right_track_50_undriven_sram_inv;
wire [0:1]mux_right_track_6_undriven_sram_inv;
wire [0:1]mux_right_track_8_undriven_sram_inv;
wire [0:1]mux_top_track_0_undriven_sram_inv;
wire [0:1]mux_top_track_10_undriven_sram_inv;
wire [0:1]mux_top_track_12_undriven_sram_inv;
wire [0:1]mux_top_track_14_undriven_sram_inv;
wire [0:1]mux_top_track_16_undriven_sram_inv;
wire [0:1]mux_top_track_18_undriven_sram_inv;
wire [0:1]mux_top_track_28_undriven_sram_inv;
wire [0:1]mux_top_track_2_undriven_sram_inv;
wire [0:1]mux_top_track_30_undriven_sram_inv;
wire [0:1]mux_top_track_32_undriven_sram_inv;
wire [0:1]mux_top_track_34_undriven_sram_inv;
wire [0:1]mux_top_track_44_undriven_sram_inv;
wire [0:1]mux_top_track_46_undriven_sram_inv;
wire [0:1]mux_top_track_48_undriven_sram_inv;
wire [0:1]mux_top_track_4_undriven_sram_inv;
wire [0:1]mux_top_track_50_undriven_sram_inv;
wire [0:1]mux_top_track_6_undriven_sram_inv;
wire [0:1]mux_top_track_8_undriven_sram_inv;
wire [0:1]mux_tree_tapbuf_size2_0_sram;
wire [0:1]mux_tree_tapbuf_size2_10_sram;
wire [0:1]mux_tree_tapbuf_size2_11_sram;
wire [0:1]mux_tree_tapbuf_size2_12_sram;
wire [0:1]mux_tree_tapbuf_size2_13_sram;
wire [0:1]mux_tree_tapbuf_size2_14_sram;
wire [0:1]mux_tree_tapbuf_size2_15_sram;
wire [0:1]mux_tree_tapbuf_size2_16_sram;
wire [0:1]mux_tree_tapbuf_size2_17_sram;
wire [0:1]mux_tree_tapbuf_size2_18_sram;
wire [0:1]mux_tree_tapbuf_size2_19_sram;
wire [0:1]mux_tree_tapbuf_size2_1_sram;
wire [0:1]mux_tree_tapbuf_size2_20_sram;
wire [0:1]mux_tree_tapbuf_size2_21_sram;
wire [0:1]mux_tree_tapbuf_size2_22_sram;
wire [0:1]mux_tree_tapbuf_size2_23_sram;
wire [0:1]mux_tree_tapbuf_size2_24_sram;
wire [0:1]mux_tree_tapbuf_size2_25_sram;
wire [0:1]mux_tree_tapbuf_size2_26_sram;
wire [0:1]mux_tree_tapbuf_size2_27_sram;
wire [0:1]mux_tree_tapbuf_size2_28_sram;
wire [0:1]mux_tree_tapbuf_size2_29_sram;
wire [0:1]mux_tree_tapbuf_size2_2_sram;
wire [0:1]mux_tree_tapbuf_size2_30_sram;
wire [0:1]mux_tree_tapbuf_size2_31_sram;
wire [0:1]mux_tree_tapbuf_size2_3_sram;
wire [0:1]mux_tree_tapbuf_size2_4_sram;
wire [0:1]mux_tree_tapbuf_size2_5_sram;
wire [0:1]mux_tree_tapbuf_size2_6_sram;
wire [0:1]mux_tree_tapbuf_size2_7_sram;
wire [0:1]mux_tree_tapbuf_size2_8_sram;
wire [0:1]mux_tree_tapbuf_size2_9_sram;
wire mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire mux_tree_tapbuf_size2_mem_19_ccff_tail;
wire mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire mux_tree_tapbuf_size2_mem_20_ccff_tail;
wire mux_tree_tapbuf_size2_mem_21_ccff_tail;
wire mux_tree_tapbuf_size2_mem_22_ccff_tail;
wire mux_tree_tapbuf_size2_mem_23_ccff_tail;
wire mux_tree_tapbuf_size2_mem_24_ccff_tail;
wire mux_tree_tapbuf_size2_mem_25_ccff_tail;
wire mux_tree_tapbuf_size2_mem_26_ccff_tail;
wire mux_tree_tapbuf_size2_mem_27_ccff_tail;
wire mux_tree_tapbuf_size2_mem_28_ccff_tail;
wire mux_tree_tapbuf_size2_mem_29_ccff_tail;
wire mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire mux_tree_tapbuf_size2_mem_30_ccff_tail;
wire mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1]mux_tree_tapbuf_size3_0_sram;
wire [0:1]mux_tree_tapbuf_size3_1_sram;
wire [0:1]mux_tree_tapbuf_size3_2_sram;
wire [0:1]mux_tree_tapbuf_size3_3_sram;
wire mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
assign chanx_right_out[10] = chany_top_in[9];
assign chanx_right_out[11] = chany_top_in[10];
assign chanx_right_out[28] = chany_top_in[27];
assign chanx_right_out[29] = chany_top_in[28];
assign chany_top_out[29] = chanx_right_in[0];
assign chany_top_out[10] = chanx_right_in[11];
assign chany_top_out[11] = chanx_right_in[12];
assign chany_top_out[12] = chanx_right_in[13];
assign chany_top_out[13] = chanx_right_in[14];
assign chany_top_out[18] = chanx_right_in[19];
assign chany_top_out[19] = chanx_right_in[20];
assign chany_top_out[20] = chanx_right_in[21];
assign chanx_right_out[12] = chany_top_in[11];
assign chany_top_out[21] = chanx_right_in[22];
assign chany_top_out[26] = chanx_right_in[27];
assign chany_top_out[27] = chanx_right_in[28];
assign chany_top_out[28] = chanx_right_in[29];
assign chanx_right_out[13] = chany_top_in[12];
assign chanx_right_out[18] = chany_top_in[17];
assign chanx_right_out[19] = chany_top_in[18];
assign chanx_right_out[20] = chany_top_in[19];
assign chanx_right_out[21] = chany_top_in[20];
assign chanx_right_out[26] = chany_top_in[25];
assign chanx_right_out[27] = chany_top_in[26];
mux_tree_tapbuf_size3_mem mem_right_track_0
(
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_10
(
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_19_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_12
(
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_20_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_14
(
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_21_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_16
(
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_22_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_18
(
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_23_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_2
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_28
(
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_24_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_30
(
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_25_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_32
(
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_26_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_34
(
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_27_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_4
(
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_28_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_46
(
.ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_29_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_48
(
.ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_30_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_50
(
.ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_31_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_6
(
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_8
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_18_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_0
(
.ccff_head(ccff_head),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_10
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_12
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_14
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_16
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_18
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_2
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_28
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_30
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_32
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_34
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_4
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_46
(
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_48
(
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_50
(
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_6
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_8
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size3 mux_right_track_0
(
.in({chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_2_sram),
.sram_inv(mux_right_track_0_undriven_sram_inv),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size2 mux_right_track_10
(
.in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_19_sram),
.sram_inv(mux_right_track_10_undriven_sram_inv),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size2 mux_right_track_12
(
.in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_20_sram),
.sram_inv(mux_right_track_12_undriven_sram_inv),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size2 mux_right_track_14
(
.in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_21_sram),
.sram_inv(mux_right_track_14_undriven_sram_inv),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size2 mux_right_track_16
(
.in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_22_sram),
.sram_inv(mux_right_track_16_undriven_sram_inv),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2 mux_right_track_18
(
.in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_23_sram),
.sram_inv(mux_right_track_18_undriven_sram_inv),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size2 mux_right_track_2
(
.in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_16_sram),
.sram_inv(mux_right_track_2_undriven_sram_inv),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size2 mux_right_track_28
(
.in({chany_top_in[13], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_24_sram),
.sram_inv(mux_right_track_28_undriven_sram_inv),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2 mux_right_track_30
(
.in({chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_25_sram),
.sram_inv(mux_right_track_30_undriven_sram_inv),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2 mux_right_track_32
(
.in({chany_top_in[15], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_26_sram),
.sram_inv(mux_right_track_32_undriven_sram_inv),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2 mux_right_track_34
(
.in({chany_top_in[16], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_27_sram),
.sram_inv(mux_right_track_34_undriven_sram_inv),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2 mux_right_track_4
(
.in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_17_sram),
.sram_inv(mux_right_track_4_undriven_sram_inv),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size2 mux_right_track_44
(
.in({chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_28_sram),
.sram_inv(mux_right_track_44_undriven_sram_inv),
.out(chanx_right_out[22])
);
mux_tree_tapbuf_size2 mux_right_track_46
(
.in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_29_sram),
.sram_inv(mux_right_track_46_undriven_sram_inv),
.out(chanx_right_out[23])
);
mux_tree_tapbuf_size2 mux_right_track_48
(
.in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_30_sram),
.sram_inv(mux_right_track_48_undriven_sram_inv),
.out(chanx_right_out[24])
);
mux_tree_tapbuf_size2 mux_right_track_50
(
.in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_31_sram),
.sram_inv(mux_right_track_50_undriven_sram_inv),
.out(chanx_right_out[25])
);
mux_tree_tapbuf_size3 mux_right_track_6
(
.in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_3_sram),
.sram_inv(mux_right_track_6_undriven_sram_inv),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size2 mux_right_track_8
(
.in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_18_sram),
.sram_inv(mux_right_track_8_undriven_sram_inv),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size3 mux_top_track_0
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1]}),
.sram(mux_tree_tapbuf_size3_0_sram),
.sram_inv(mux_top_track_0_undriven_sram_inv),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size2 mux_top_track_10
(
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[6]}),
.sram(mux_tree_tapbuf_size2_3_sram),
.sram_inv(mux_top_track_10_undriven_sram_inv),
.out(chany_top_out[5])
);
mux_tree_tapbuf_size2 mux_top_track_12
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size2_4_sram),
.sram_inv(mux_top_track_12_undriven_sram_inv),
.out(chany_top_out[6])
);
mux_tree_tapbuf_size2 mux_top_track_14
(
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size2_5_sram),
.sram_inv(mux_top_track_14_undriven_sram_inv),
.out(chany_top_out[7])
);
mux_tree_tapbuf_size2 mux_top_track_16
(
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size2_6_sram),
.sram_inv(mux_top_track_16_undriven_sram_inv),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size2 mux_top_track_18
(
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size2_7_sram),
.sram_inv(mux_top_track_18_undriven_sram_inv),
.out(chany_top_out[9])
);
mux_tree_tapbuf_size2 mux_top_track_2
(
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2]}),
.sram(mux_tree_tapbuf_size2_0_sram),
.sram_inv(mux_top_track_2_undriven_sram_inv),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size2 mux_top_track_28
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[15]}),
.sram(mux_tree_tapbuf_size2_8_sram),
.sram_inv(mux_top_track_28_undriven_sram_inv),
.out(chany_top_out[14])
);
mux_tree_tapbuf_size2 mux_top_track_30
(
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[16]}),
.sram(mux_tree_tapbuf_size2_9_sram),
.sram_inv(mux_top_track_30_undriven_sram_inv),
.out(chany_top_out[15])
);
mux_tree_tapbuf_size2 mux_top_track_32
(
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[17]}),
.sram(mux_tree_tapbuf_size2_10_sram),
.sram_inv(mux_top_track_32_undriven_sram_inv),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size2 mux_top_track_34
(
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[18]}),
.sram(mux_tree_tapbuf_size2_11_sram),
.sram_inv(mux_top_track_34_undriven_sram_inv),
.out(chany_top_out[17])
);
mux_tree_tapbuf_size2 mux_top_track_4
(
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3]}),
.sram(mux_tree_tapbuf_size2_1_sram),
.sram_inv(mux_top_track_4_undriven_sram_inv),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size2 mux_top_track_44
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[23]}),
.sram(mux_tree_tapbuf_size2_12_sram),
.sram_inv(mux_top_track_44_undriven_sram_inv),
.out(chany_top_out[22])
);
mux_tree_tapbuf_size2 mux_top_track_46
(
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[24]}),
.sram(mux_tree_tapbuf_size2_13_sram),
.sram_inv(mux_top_track_46_undriven_sram_inv),
.out(chany_top_out[23])
);
mux_tree_tapbuf_size2 mux_top_track_48
(
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[25]}),
.sram(mux_tree_tapbuf_size2_14_sram),
.sram_inv(mux_top_track_48_undriven_sram_inv),
.out(chany_top_out[24])
);
mux_tree_tapbuf_size2 mux_top_track_50
(
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[26]}),
.sram(mux_tree_tapbuf_size2_15_sram),
.sram_inv(mux_top_track_50_undriven_sram_inv),
.out(chany_top_out[25])
);
mux_tree_tapbuf_size3 mux_top_track_6
(
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[4]}),
.sram(mux_tree_tapbuf_size3_1_sram),
.sram_inv(mux_top_track_6_undriven_sram_inv),
.out(chany_top_out[3])
);
mux_tree_tapbuf_size2 mux_top_track_8
(
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size2_2_sram),
.sram_inv(mux_top_track_8_undriven_sram_inv),
.out(chany_top_out[4])
);
endmodule |
module mux_tree_tapbuf_size10_mem
(
ccff_head,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:3]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:3]mem_out;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
endmodule |
module logical_tile_io_mode_io_
(
ccff_head,
gfpga_pad_io_soc_in,
io_outpad,
isol_n,
prog_clk,
prog_reset,
ccff_tail,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
io_inpad
);
input ccff_head;
input gfpga_pad_io_soc_in;
input io_outpad;
input isol_n;
input prog_clk;
input prog_reset;
output ccff_tail;
output gfpga_pad_io_soc_dir;
output gfpga_pad_io_soc_out;
output io_inpad;
wire ccff_head;
wire ccff_tail;
wire direct_interc_1_out;
wire gfpga_pad_io_soc_dir;
wire gfpga_pad_io_soc_in;
wire gfpga_pad_io_soc_out;
wire io_inpad;
wire io_outpad;
wire isol_n;
wire logical_tile_io_mode_physical__iopad_0_iopad_inpad;
wire prog_clk;
wire prog_reset;
direct_interc direct_interc_0_
(
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
.out(io_inpad)
);
direct_interc direct_interc_1_
(
.in(io_outpad),
.out(direct_interc_1_out)
);
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0
(
.ccff_head(ccff_head),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.iopad_outpad(direct_interc_1_out),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad)
);
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4
(
ccff_head,
frac_lut4_in,
prog_clk,
prog_reset,
ccff_tail,
frac_lut4_lut2_out,
frac_lut4_lut3_out,
frac_lut4_lut4_out
);
input ccff_head;
input [0:3]frac_lut4_in;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:1]frac_lut4_lut2_out;
output [0:1]frac_lut4_lut3_out;
output frac_lut4_lut4_out;
wire ccff_head;
wire ccff_tail;
wire frac_lut4_0__undriven_mode_inv;
wire [0:15]frac_lut4_0__undriven_sram_inv;
wire frac_lut4_0_mode;
wire [0:15]frac_lut4_0_sram;
wire [0:3]frac_lut4_in;
wire [0:1]frac_lut4_lut2_out;
wire [0:1]frac_lut4_lut3_out;
wire frac_lut4_lut4_out;
wire prog_clk;
wire prog_reset;
frac_lut4 frac_lut4_0_
(
.in(frac_lut4_in),
.mode(frac_lut4_0_mode),
.mode_inv(frac_lut4_0__undriven_mode_inv),
.sram(frac_lut4_0_sram),
.sram_inv(frac_lut4_0__undriven_sram_inv),
.lut2_out(frac_lut4_lut2_out),
.lut3_out(frac_lut4_lut3_out),
.lut4_out(frac_lut4_lut4_out)
);
frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
(
.ccff_head(ccff_head),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out({frac_lut4_0_sram[0], frac_lut4_0_sram[1], frac_lut4_0_sram[2], frac_lut4_0_sram[3], frac_lut4_0_sram[4], frac_lut4_0_sram[5], frac_lut4_0_sram[6], frac_lut4_0_sram[7], frac_lut4_0_sram[8], frac_lut4_0_sram[9], frac_lut4_0_sram[10], frac_lut4_0_sram[11], frac_lut4_0_sram[12], frac_lut4_0_sram[13], frac_lut4_0_sram[14], frac_lut4_0_sram[15], frac_lut4_0_mode})
);
endmodule |
module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
(
ccff_head,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:16]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:16]mem_out;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[16];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_
(
.CLK(prog_clk),
.D(mem_out[9]),
.RESET_B(prog_reset),
.Q(mem_out[10])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_
(
.CLK(prog_clk),
.D(mem_out[10]),
.RESET_B(prog_reset),
.Q(mem_out[11])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_
(
.CLK(prog_clk),
.D(mem_out[11]),
.RESET_B(prog_reset),
.Q(mem_out[12])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_
(
.CLK(prog_clk),
.D(mem_out[12]),
.RESET_B(prog_reset),
.Q(mem_out[13])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_
(
.CLK(prog_clk),
.D(mem_out[13]),
.RESET_B(prog_reset),
.Q(mem_out[14])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_
(
.CLK(prog_clk),
.D(mem_out[14]),
.RESET_B(prog_reset),
.Q(mem_out[15])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_
(
.CLK(prog_clk),
.D(mem_out[15]),
.RESET_B(prog_reset),
.Q(mem_out[16])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_
(
.CLK(prog_clk),
.D(mem_out[3]),
.RESET_B(prog_reset),
.Q(mem_out[4])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_
(
.CLK(prog_clk),
.D(mem_out[4]),
.RESET_B(prog_reset),
.Q(mem_out[5])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_
(
.CLK(prog_clk),
.D(mem_out[5]),
.RESET_B(prog_reset),
.Q(mem_out[6])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_
(
.CLK(prog_clk),
.D(mem_out[6]),
.RESET_B(prog_reset),
.Q(mem_out[7])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_
(
.CLK(prog_clk),
.D(mem_out[7]),
.RESET_B(prog_reset),
.Q(mem_out[8])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_
(
.CLK(prog_clk),
.D(mem_out[8]),
.RESET_B(prog_reset),
.Q(mem_out[9])
);
endmodule |
module logical_tile_io_mode_physical__iopad
(
ccff_head,
gfpga_pad_io_soc_in,
iopad_outpad,
isol_n,
prog_clk,
prog_reset,
ccff_tail,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
iopad_inpad
);
input ccff_head;
input gfpga_pad_io_soc_in;
input iopad_outpad;
input isol_n;
input prog_clk;
input prog_reset;
output ccff_tail;
output gfpga_pad_io_soc_dir;
output gfpga_pad_io_soc_out;
output iopad_inpad;
wire ccff_head;
wire ccff_tail;
wire gfpga_pad_io_soc_dir;
wire gfpga_pad_io_soc_in;
wire gfpga_pad_io_soc_out;
wire io_0_en;
wire iopad_inpad;
wire iopad_outpad;
wire isol_n;
wire prog_clk;
wire prog_reset;
io io_0_
(
.FPGA_DIR(io_0_en),
.FPGA_OUT(iopad_outpad),
.IO_ISOL_N(isol_n),
.SOC_IN(gfpga_pad_io_soc_in),
.FPGA_IN(iopad_inpad),
.SOC_DIR(gfpga_pad_io_soc_dir),
.SOC_OUT(gfpga_pad_io_soc_out)
);
io_sky130_fd_sc_hd__dfrtp_1_mem io_sky130_fd_sc_hd__dfrtp_1_mem
(
.ccff_head(ccff_head),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(io_0_en)
);
endmodule |
module mux_tree_tapbuf_size3
(
in,
sram,
sram_inv,
out
);
input [0:2]in;
input [0:1]sram;
input [0:1]sram_inv;
output out;
wire const1_0_const1;
wire [0:2]in;
wire out;
wire sky130_fd_sc_hd__mux2_1_0_X;
wire sky130_fd_sc_hd__mux2_1_1_X;
wire sky130_fd_sc_hd__mux2_1_2_X;
wire [0:1]sram;
wire [0:1]sram_inv;
const1 const1_0_
(
.const1(const1_0_const1)
);
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
(
.A0(in[1]),
.A1(in[0]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X)
);
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_
(
.A0(const1_0_const1),
.A1(in[2]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_1_X)
);
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
(
.A0(sky130_fd_sc_hd__mux2_1_1_X),
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_2_X)
);
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
(
.A(sky130_fd_sc_hd__mux2_1_2_X),
.X(out)
);
endmodule |
module mux_tree_tapbuf_size2
(
in,
sram,
sram_inv,
out
);
input [0:1]in;
input [0:1]sram;
input [0:1]sram_inv;
output out;
wire const1_0_const1;
wire [0:1]in;
wire out;
wire sky130_fd_sc_hd__mux2_1_0_X;
wire sky130_fd_sc_hd__mux2_1_1_X;
wire [0:1]sram;
wire [0:1]sram_inv;
const1 const1_0_
(
.const1(const1_0_const1)
);
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_
(
.A0(in[1]),
.A1(in[0]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X)
);
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_
(
.A0(const1_0_const1),
.A1(sky130_fd_sc_hd__mux2_1_0_X),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_1_X)
);
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_
(
.A(sky130_fd_sc_hd__mux2_1_1_X),
.X(out)
);
endmodule |
module bottom_tile
(
ccff_head,
ccff_head_1,
chanx_left_in,
chanx_right_in_0,
chany_top_in,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset_top_in,
reset_top_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
test_enable_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
ccff_tail,
ccff_tail_0,
chanx_left_out,
chanx_right_out_0,
chany_top_out,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_
);
input ccff_head;
input ccff_head_1;
input [29:0]chanx_left_in;
input [29:0]chanx_right_in_0;
input [29:0]chany_top_in;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset_top_in;
input reset_top_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
input test_enable_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
output ccff_tail;
output ccff_tail_0;
output [29:0]chanx_left_out;
output [29:0]chanx_right_out_0;
output [29:0]chany_top_out;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output top_width_0_height_0_subtile_0__pin_inpad_0_;
output top_width_0_height_0_subtile_1__pin_inpad_0_;
output top_width_0_height_0_subtile_2__pin_inpad_0_;
output top_width_0_height_0_subtile_3__pin_inpad_0_;
wire ccff_head;
wire ccff_head_1;
wire ccff_tail;
wire ccff_tail_0;
wire ccff_tail_1;
wire [29:0]chanx_left_in;
wire [29:0]chanx_left_out;
wire [29:0]chanx_left_out_0;
wire [29:0]chanx_right_in_0;
wire [29:0]chanx_right_out;
wire [29:0]chanx_right_out_0;
wire [29:0]chany_top_in;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire prog_reset_top_in;
wire reset_top_in;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
wire test_enable_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
wire top_width_0_height_0_subtile_0__pin_inpad_0_;
wire top_width_0_height_0_subtile_1__pin_inpad_0_;
wire top_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_width_0_height_0_subtile_3__pin_inpad_0_;
assign prog_reset = prog_reset_top_in;
cbx_1__0_ cbx_1__0_
(
.ccff_head(ccff_head),
.ccff_head_0(ccff_tail_1),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_left_out_0),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.ccff_tail_0(ccff_tail_0),
.chanx_left_out(chanx_left_out),
.chanx_right_out(chanx_right_out),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
.top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_)
);
sb_1__0_ sb_1__0_
(
.ccff_head(ccff_head_1),
.chanx_left_in(chanx_right_out),
.chanx_right_in(chanx_right_in_0),
.chany_top_in(chany_top_in),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_),
.ccff_tail(ccff_tail_1),
.chanx_left_out(chanx_left_out_0),
.chanx_right_out(chanx_right_out_0),
.chany_top_out(chany_top_out)
);
endmodule |
module bottom_right_tile
(
ccff_head,
ccff_head_1,
chanx_left_in,
chany_top_in,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset_top_in,
reset_top_in,
test_enable_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail,
ccff_tail_0,
chanx_left_out,
chany_top_out,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_
);
input ccff_head;
input ccff_head_1;
input [29:0]chanx_left_in;
input [29:0]chany_top_in;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset_top_in;
input reset_top_in;
input test_enable_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
input top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
input top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
input top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
output ccff_tail_0;
output [29:0]chanx_left_out;
output [29:0]chany_top_out;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output top_width_0_height_0_subtile_0__pin_inpad_0_;
output top_width_0_height_0_subtile_1__pin_inpad_0_;
output top_width_0_height_0_subtile_2__pin_inpad_0_;
output top_width_0_height_0_subtile_3__pin_inpad_0_;
wire ccff_head;
wire ccff_head_1;
wire ccff_tail;
wire ccff_tail_0;
wire ccff_tail_1;
wire [29:0]chanx_left_in;
wire [29:0]chanx_left_out;
wire [29:0]chanx_left_out_0;
wire [29:0]chanx_right_out;
wire [29:0]chany_top_in;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire prog_reset_top_in;
wire reset_top_in;
wire test_enable_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
wire top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
wire top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
wire top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
wire top_width_0_height_0_subtile_0__pin_inpad_0_;
wire top_width_0_height_0_subtile_1__pin_inpad_0_;
wire top_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_width_0_height_0_subtile_3__pin_inpad_0_;
assign prog_reset = prog_reset_top_in;
cbx_1__0_ cbx_8__0_
(
.ccff_head(ccff_head),
.ccff_head_0(ccff_tail_1),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_left_out_0),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.ccff_tail_0(ccff_tail_0),
.chanx_left_out(chanx_left_out),
.chanx_right_out(chanx_right_out),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
.top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_)
);
sb_8__0_ sb_8__0_
(
.ccff_head(ccff_head_1),
.chanx_left_in(chanx_right_out),
.chany_top_in(chany_top_in),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_),
.top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(ccff_tail_1),
.chanx_left_out(chanx_left_out_0),
.chany_top_out(chany_top_out)
);
endmodule |
module bottom_left_tile
(
ccff_head,
chanx_right_in,
chany_top_in,
prog_clk,
prog_reset_top_in,
reset_top_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
test_enable_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail,
chanx_right_out,
chany_top_out
);
input ccff_head;
input [29:0]chanx_right_in;
input [29:0]chany_top_in;
input prog_clk;
input prog_reset_top_in;
input reset_top_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
input test_enable_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
output [29:0]chanx_right_out;
output [29:0]chany_top_out;
wire ccff_head;
wire ccff_tail;
wire [29:0]chanx_right_in;
wire [29:0]chanx_right_out;
wire [29:0]chany_top_in;
wire [29:0]chany_top_out;
wire prog_clk;
wire prog_reset;
wire prog_reset_top_in;
wire reset_top_in;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
wire test_enable_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
assign prog_reset = prog_reset_top_in;
sb_0__0_ sb_0__0_
(
.ccff_head(ccff_head),
.chanx_right_in(chanx_right_in),
.chany_top_in(chany_top_in),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(ccff_tail),
.chanx_right_out(chanx_right_out),
.chany_top_out(chany_top_out)
);
endmodule |
module top_left_tile
(
ccff_head,
ccff_head_0,
chanx_right_in,
chany_bottom_in_0,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset_bottom_in,
reset_bottom_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
test_enable_bottom_in,
ccff_tail,
ccff_tail_0,
chanx_right_out,
chany_bottom_out_0,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
right_width_0_height_0_subtile_3__pin_inpad_0_
);
input ccff_head;
input ccff_head_0;
input [29:0]chanx_right_in;
input [29:0]chany_bottom_in_0;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset_bottom_in;
input reset_bottom_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
input test_enable_bottom_in;
output ccff_tail;
output ccff_tail_0;
output [29:0]chanx_right_out;
output [29:0]chany_bottom_out_0;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output right_width_0_height_0_subtile_0__pin_inpad_0_;
output right_width_0_height_0_subtile_1__pin_inpad_0_;
output right_width_0_height_0_subtile_2__pin_inpad_0_;
output right_width_0_height_0_subtile_3__pin_inpad_0_;
wire ccff_head;
wire ccff_head_0;
wire ccff_tail;
wire ccff_tail_0;
wire [29:0]chanx_right_in;
wire [29:0]chanx_right_out;
wire [29:0]chany_bottom_in_0;
wire [29:0]chany_bottom_out;
wire [29:0]chany_bottom_out_0;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire prog_reset_bottom_in;
wire reset_bottom_in;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
wire right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
wire right_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_width_0_height_0_subtile_2__pin_inpad_0_;
wire right_width_0_height_0_subtile_3__pin_inpad_0_;
wire test_enable_bottom_in;
assign prog_reset = prog_reset_bottom_in;
cby_0__1_ cby_0__8_
(
.ccff_head_0(ccff_head_0),
.chany_bottom_in(chany_bottom_in_0),
.chany_top_in(chany_bottom_out),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_0),
.chany_bottom_out(chany_bottom_out_0),
.chany_top_out(chany_top_out),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
.right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
.right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
.right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_)
);
sb_0__8_ sb_0__8_
(
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_head(ccff_head),
.chanx_right_in(chanx_right_in),
.chany_bottom_in(chany_top_out),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_),
.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(ccff_tail),
.chanx_right_out(chanx_right_out),
.chany_bottom_out(chany_bottom_out)
);
endmodule |
module left_tile
(
ccff_head,
ccff_head_0,
chanx_right_in,
chany_bottom_in,
chany_top_in_0,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset_bottom_in,
prog_reset_left_in,
prog_reset_top_in,
reset_bottom_in,
reset_right_in,
reset_top_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
test_enable_bottom_in,
test_enable_right_in,
test_enable_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail,
ccff_tail_0,
chanx_right_out,
chany_bottom_out,
chany_top_out_0,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
prog_reset_bottom_out,
prog_reset_right_out,
prog_reset_top_out,
reset_bottom_out,
reset_top_out,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
right_width_0_height_0_subtile_3__pin_inpad_0_,
test_enable_bottom_out,
test_enable_top_out
);
input ccff_head;
input ccff_head_0;
input [29:0]chanx_right_in;
input [29:0]chany_bottom_in;
input [29:0]chany_top_in_0;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset_bottom_in;
input prog_reset_left_in;
input prog_reset_top_in;
input reset_bottom_in;
input reset_right_in;
input reset_top_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
input test_enable_bottom_in;
input test_enable_right_in;
input test_enable_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
input top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
output ccff_tail_0;
output [29:0]chanx_right_out;
output [29:0]chany_bottom_out;
output [29:0]chany_top_out_0;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output prog_reset_bottom_out;
output prog_reset_right_out;
output prog_reset_top_out;
output reset_bottom_out;
output reset_top_out;
output right_width_0_height_0_subtile_0__pin_inpad_0_;
output right_width_0_height_0_subtile_1__pin_inpad_0_;
output right_width_0_height_0_subtile_2__pin_inpad_0_;
output right_width_0_height_0_subtile_3__pin_inpad_0_;
output test_enable_bottom_out;
output test_enable_top_out;
wire ccff_head;
wire ccff_head_0;
wire ccff_tail;
wire ccff_tail_0;
wire [29:0]chanx_right_in;
wire [29:0]chanx_right_out;
wire [29:0]chany_bottom_in;
wire [29:0]chany_bottom_out;
wire [29:0]chany_bottom_out_0;
wire [29:0]chany_top_in_0;
wire [29:0]chany_top_out;
wire [29:0]chany_top_out_0;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire prog_reset_bottom_in;
wire prog_reset_bottom_out;
wire prog_reset_left_in;
wire prog_reset_right_out;
wire prog_reset_top_in;
wire prog_reset_top_out;
wire reset_bottom_in;
wire reset_bottom_out;
wire reset_right_in;
wire reset_top_in;
wire reset_top_out;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
wire right_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_width_0_height_0_subtile_2__pin_inpad_0_;
wire right_width_0_height_0_subtile_3__pin_inpad_0_;
wire test_enable_bottom_in;
wire test_enable_bottom_out;
wire test_enable_right_in;
wire test_enable_top_in;
wire test_enable_top_out;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
wire top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
assign prog_reset = prog_reset_bottom_in;
assign prog_reset_top_in = prog_reset_left_in;
assign prog_reset_right_out = prog_reset;
assign prog_reset_top_out = prog_reset_right_out;
assign prog_reset_bottom_in = prog_reset_top_in;
assign prog_reset_bottom_out = prog_reset_top_out;
assign reset_top_out = reset_bottom_in;
assign reset_top_in = reset_right_in;
assign reset_bottom_in = reset_top_in;
assign reset_bottom_out = reset_top_out;
assign test_enable_top_out = test_enable_bottom_in;
assign test_enable_top_in = test_enable_right_in;
assign test_enable_bottom_in = test_enable_top_in;
assign test_enable_bottom_out = test_enable_top_out;
cby_0__1_ cby_0__1_
(
.ccff_head_0(ccff_head_0),
.chany_bottom_in(chany_bottom_in),
.chany_top_in(chany_bottom_out_0),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.chany_bottom_out(chany_bottom_out),
.chany_top_out(chany_top_out),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
.right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
.right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
.right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_)
);
sb_0__1_ sb_0__1_
(
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(right_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_head(ccff_head),
.chanx_right_in(chanx_right_in),
.chany_bottom_in(chany_top_out),
.chany_top_in(chany_top_in_0),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(ccff_tail_0),
.chanx_right_out(chanx_right_out),
.chany_bottom_out(chany_bottom_out_0),
.chany_top_out(chany_top_out_0)
);
endmodule |
module tile
(
ccff_head_1,
ccff_head_2,
chanx_left_in,
chanx_right_in_0,
chany_bottom_in,
chany_top_in_0,
clk0,
prog_clk,
prog_reset_bottom_in,
prog_reset_left_in,
prog_reset_top_in,
reset_bottom_in,
reset_right_in,
reset_top_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
sc_in,
test_enable_bottom_in,
test_enable_right_in,
test_enable_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
top_width_0_height_0_subtile_0__pin_cin_0_,
top_width_0_height_0_subtile_0__pin_reg_in_0_,
bottom_width_0_height_0_subtile_0__pin_cout_0_,
bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
ccff_tail,
ccff_tail_0,
chanx_left_out,
chanx_right_out_0,
chany_bottom_out,
chany_top_out_0,
prog_reset_bottom_out,
prog_reset_right_out,
prog_reset_top_out,
reset_bottom_out,
reset_left_out,
reset_top_out,
right_width_0_height_0_subtile_0__pin_O_10_,
right_width_0_height_0_subtile_0__pin_O_11_,
right_width_0_height_0_subtile_0__pin_O_12_,
right_width_0_height_0_subtile_0__pin_O_13_,
right_width_0_height_0_subtile_0__pin_O_14_,
right_width_0_height_0_subtile_0__pin_O_15_,
right_width_0_height_0_subtile_0__pin_O_8_,
right_width_0_height_0_subtile_0__pin_O_9_,
sc_out,
test_enable_bottom_out,
test_enable_left_out,
test_enable_top_out,
top_width_0_height_0_subtile_0__pin_O_0_,
top_width_0_height_0_subtile_0__pin_O_1_,
top_width_0_height_0_subtile_0__pin_O_2_,
top_width_0_height_0_subtile_0__pin_O_3_,
top_width_0_height_0_subtile_0__pin_O_4_,
top_width_0_height_0_subtile_0__pin_O_5_,
top_width_0_height_0_subtile_0__pin_O_6_,
top_width_0_height_0_subtile_0__pin_O_7_
);
input ccff_head_1;
input ccff_head_2;
input [29:0]chanx_left_in;
input [29:0]chanx_right_in_0;
input [29:0]chany_bottom_in;
input [29:0]chany_top_in_0;
input clk0;
input prog_clk;
input prog_reset_bottom_in;
input prog_reset_left_in;
input prog_reset_top_in;
input reset_bottom_in;
input reset_right_in;
input reset_top_in;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
input sc_in;
input test_enable_bottom_in;
input test_enable_right_in;
input test_enable_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
input top_width_0_height_0_subtile_0__pin_cin_0_;
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
output bottom_width_0_height_0_subtile_0__pin_cout_0_;
output bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
output ccff_tail;
output ccff_tail_0;
output [29:0]chanx_left_out;
output [29:0]chanx_right_out_0;
output [29:0]chany_bottom_out;
output [29:0]chany_top_out_0;
output prog_reset_bottom_out;
output prog_reset_right_out;
output prog_reset_top_out;
output reset_bottom_out;
output reset_left_out;
output reset_top_out;
output right_width_0_height_0_subtile_0__pin_O_10_;
output right_width_0_height_0_subtile_0__pin_O_11_;
output right_width_0_height_0_subtile_0__pin_O_12_;
output right_width_0_height_0_subtile_0__pin_O_13_;
output right_width_0_height_0_subtile_0__pin_O_14_;
output right_width_0_height_0_subtile_0__pin_O_15_;
output right_width_0_height_0_subtile_0__pin_O_8_;
output right_width_0_height_0_subtile_0__pin_O_9_;
output sc_out;
output test_enable_bottom_out;
output test_enable_left_out;
output test_enable_top_out;
output top_width_0_height_0_subtile_0__pin_O_0_;
output top_width_0_height_0_subtile_0__pin_O_1_;
output top_width_0_height_0_subtile_0__pin_O_2_;
output top_width_0_height_0_subtile_0__pin_O_3_;
output top_width_0_height_0_subtile_0__pin_O_4_;
output top_width_0_height_0_subtile_0__pin_O_5_;
output top_width_0_height_0_subtile_0__pin_O_6_;
output top_width_0_height_0_subtile_0__pin_O_7_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
wire ccff_head_1;
wire ccff_head_2;
wire ccff_tail;
wire ccff_tail_0;
wire ccff_tail_1;
wire ccff_tail_2;
wire [29:0]chanx_left_in;
wire [29:0]chanx_left_out;
wire [29:0]chanx_left_out_0;
wire [29:0]chanx_right_in_0;
wire [29:0]chanx_right_out;
wire [29:0]chanx_right_out_0;
wire [29:0]chany_bottom_in;
wire [29:0]chany_bottom_out;
wire [29:0]chany_bottom_out_0;
wire [29:0]chany_top_in_0;
wire [29:0]chany_top_out;
wire [29:0]chany_top_out_0;
wire clk0;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire prog_clk;
wire prog_reset;
wire prog_reset_bottom_in;
wire prog_reset_bottom_out;
wire prog_reset_left_in;
wire prog_reset_right_out;
wire prog_reset_top_in;
wire prog_reset_top_out;
wire reset;
wire reset_bottom_in;
wire reset_bottom_out;
wire reset_left_out;
wire reset_right_in;
wire reset_top_in;
wire reset_top_out;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
wire right_width_0_height_0_subtile_0__pin_O_10_;
wire right_width_0_height_0_subtile_0__pin_O_11_;
wire right_width_0_height_0_subtile_0__pin_O_12_;
wire right_width_0_height_0_subtile_0__pin_O_13_;
wire right_width_0_height_0_subtile_0__pin_O_14_;
wire right_width_0_height_0_subtile_0__pin_O_15_;
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire sc_in;
wire sc_out;
wire test_enable;
wire test_enable_bottom_in;
wire test_enable_bottom_out;
wire test_enable_left_out;
wire test_enable_right_in;
wire test_enable_top_in;
wire test_enable_top_out;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
wire top_width_0_height_0_subtile_0__pin_O_0_;
wire top_width_0_height_0_subtile_0__pin_O_1_;
wire top_width_0_height_0_subtile_0__pin_O_2_;
wire top_width_0_height_0_subtile_0__pin_O_3_;
wire top_width_0_height_0_subtile_0__pin_O_4_;
wire top_width_0_height_0_subtile_0__pin_O_5_;
wire top_width_0_height_0_subtile_0__pin_O_6_;
wire top_width_0_height_0_subtile_0__pin_O_7_;
wire top_width_0_height_0_subtile_0__pin_cin_0_;
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
assign prog_reset = prog_reset_bottom_in;
assign prog_reset_top_in = prog_reset_left_in;
assign prog_reset_right_out = prog_reset;
assign prog_reset_top_out = prog_reset_right_out;
assign prog_reset_bottom_in = prog_reset_top_in;
assign prog_reset_bottom_out = prog_reset_top_out;
assign reset = reset_bottom_in;
assign reset_top_out = reset_left_out;
assign reset_left_out = reset;
assign reset_top_in = reset_right_in;
assign reset_bottom_in = reset_top_in;
assign reset_bottom_out = reset_top_out;
assign test_enable = test_enable_bottom_in;
assign test_enable_top_out = test_enable_left_out;
assign test_enable_top_in = test_enable_right_in;
assign test_enable_left_out = test_enable;
assign test_enable_bottom_in = test_enable_top_in;
assign test_enable_bottom_out = test_enable_top_out;
cbx_1__1_ cbx_1__1_
(
.ccff_head(ccff_tail_2),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_left_out_0),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
.ccff_tail(ccff_tail_0),
.chanx_left_out(chanx_left_out),
.chanx_right_out(chanx_right_out)
);
cby_1__1_ cby_1__1_
(
.ccff_head(ccff_head_1),
.chany_bottom_in(chany_bottom_in),
.chany_top_in(chany_bottom_out_0),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_1),
.chany_bottom_out(chany_bottom_out),
.chany_top_out(chany_top_out),
.left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_)
);
grid_clb grid_clb_1__1_
(
.ccff_head(ccff_tail_1),
.clk0(clk0),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.reset(reset),
.right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
.right_width_0_height_0_subtile_0__pin_I4i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_),
.right_width_0_height_0_subtile_0__pin_I5_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_),
.right_width_0_height_0_subtile_0__pin_I5_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_),
.right_width_0_height_0_subtile_0__pin_I5i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_),
.right_width_0_height_0_subtile_0__pin_I5i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_),
.right_width_0_height_0_subtile_0__pin_I6_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_),
.right_width_0_height_0_subtile_0__pin_I6_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_),
.right_width_0_height_0_subtile_0__pin_I6i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_),
.right_width_0_height_0_subtile_0__pin_I6i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_),
.right_width_0_height_0_subtile_0__pin_I7_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_),
.right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
.right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
.right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
.sc_in(sc_in),
.test_enable(test_enable),
.top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
.top_width_0_height_0_subtile_0__pin_I0i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_),
.top_width_0_height_0_subtile_0__pin_I1_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_),
.top_width_0_height_0_subtile_0__pin_I1_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_),
.top_width_0_height_0_subtile_0__pin_I1i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_),
.top_width_0_height_0_subtile_0__pin_I1i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_),
.top_width_0_height_0_subtile_0__pin_I2_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_),
.top_width_0_height_0_subtile_0__pin_I2_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_),
.top_width_0_height_0_subtile_0__pin_I2i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_),
.top_width_0_height_0_subtile_0__pin_I2i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_),
.top_width_0_height_0_subtile_0__pin_I3_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_),
.top_width_0_height_0_subtile_0__pin_I3_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_),
.top_width_0_height_0_subtile_0__pin_I3i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_),
.top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
.top_width_0_height_0_subtile_0__pin_cin_0_(top_width_0_height_0_subtile_0__pin_cin_0_),
.top_width_0_height_0_subtile_0__pin_reg_in_0_(top_width_0_height_0_subtile_0__pin_reg_in_0_),
.bottom_width_0_height_0_subtile_0__pin_cout_0_(bottom_width_0_height_0_subtile_0__pin_cout_0_),
.bottom_width_0_height_0_subtile_0__pin_reg_out_0_(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
.ccff_tail(ccff_tail),
.right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_),
.right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_),
.right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_),
.right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_),
.right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_),
.right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_),
.right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_),
.right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_),
.sc_out(sc_out),
.top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_),
.top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_),
.top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_),
.top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_),
.top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_),
.top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_),
.top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_),
.top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_)
);
sb_1__1_ sb_1__1_
(
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(right_width_0_height_0_subtile_0__pin_O_12_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(right_width_0_height_0_subtile_0__pin_O_13_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(right_width_0_height_0_subtile_0__pin_O_14_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_),
.ccff_head(ccff_head_2),
.chanx_left_in(chanx_right_out),
.chanx_right_in(chanx_right_in_0),
.chany_bottom_in(chany_top_out),
.chany_top_in(chany_top_in_0),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(top_width_0_height_0_subtile_0__pin_O_3_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(top_width_0_height_0_subtile_0__pin_O_4_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_3_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_4_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_13_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_14_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_15_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_),
.ccff_tail(ccff_tail_2),
.chanx_left_out(chanx_left_out_0),
.chanx_right_out(chanx_right_out_0),
.chany_bottom_out(chany_bottom_out_0),
.chany_top_out(chany_top_out_0)
);
endmodule |
module cby_1__1_
(
prog_reset,
prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
left_grid_right_width_0_height_0_subtile_0__pin_I4_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I4_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I5_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I5_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I6_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I6_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I7_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I7_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_,
ccff_tail
);
input prog_reset;
input prog_clk;
input [0:29]chany_bottom_in;
input [0:29]chany_top_in;
input ccff_head;
output [0:29]chany_bottom_out;
output [0:29]chany_top_out;
output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
output left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
output left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
output left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
output left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
output left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
output left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
output left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
output left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
output left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
output left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
output left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
output left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
output ccff_tail;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_bottom_in;
wire [0:29]chany_top_in;
wire ccff_head;
wire [0:29]chany_bottom_out;
wire [0:29]chany_top_out;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire ccff_tail;
wire [0:3]mux_right_ipin_0_undriven_sram_inv;
wire [0:3]mux_right_ipin_10_undriven_sram_inv;
wire [0:3]mux_right_ipin_11_undriven_sram_inv;
wire [0:3]mux_right_ipin_12_undriven_sram_inv;
wire [0:3]mux_right_ipin_13_undriven_sram_inv;
wire [0:3]mux_right_ipin_14_undriven_sram_inv;
wire [0:3]mux_right_ipin_15_undriven_sram_inv;
wire [0:3]mux_right_ipin_1_undriven_sram_inv;
wire [0:3]mux_right_ipin_2_undriven_sram_inv;
wire [0:3]mux_right_ipin_3_undriven_sram_inv;
wire [0:3]mux_right_ipin_4_undriven_sram_inv;
wire [0:3]mux_right_ipin_5_undriven_sram_inv;
wire [0:3]mux_right_ipin_6_undriven_sram_inv;
wire [0:3]mux_right_ipin_7_undriven_sram_inv;
wire [0:3]mux_right_ipin_8_undriven_sram_inv;
wire [0:3]mux_right_ipin_9_undriven_sram_inv;
wire [0:3]mux_tree_tapbuf_size10_0_sram;
wire [0:3]mux_tree_tapbuf_size10_1_sram;
wire [0:3]mux_tree_tapbuf_size10_2_sram;
wire [0:3]mux_tree_tapbuf_size10_3_sram;
wire [0:3]mux_tree_tapbuf_size10_4_sram;
wire [0:3]mux_tree_tapbuf_size10_5_sram;
wire [0:3]mux_tree_tapbuf_size10_6_sram;
wire [0:3]mux_tree_tapbuf_size10_7_sram;
wire mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3]mux_tree_tapbuf_size12_0_sram;
wire [0:3]mux_tree_tapbuf_size12_1_sram;
wire [0:3]mux_tree_tapbuf_size12_2_sram;
wire [0:3]mux_tree_tapbuf_size12_3_sram;
wire [0:3]mux_tree_tapbuf_size12_4_sram;
wire [0:3]mux_tree_tapbuf_size12_5_sram;
wire [0:3]mux_tree_tapbuf_size12_6_sram;
wire [0:3]mux_tree_tapbuf_size12_7_sram;
wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
wire mux_tree_tapbuf_size12_mem_3_ccff_tail;
wire mux_tree_tapbuf_size12_mem_4_ccff_tail;
wire mux_tree_tapbuf_size12_mem_5_ccff_tail;
wire mux_tree_tapbuf_size12_mem_6_ccff_tail;
wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_top_out[20] = chany_bottom_in[20];
assign chany_top_out[21] = chany_bottom_in[21];
assign chany_top_out[22] = chany_bottom_in[22];
assign chany_top_out[23] = chany_bottom_in[23];
assign chany_top_out[24] = chany_bottom_in[24];
assign chany_top_out[25] = chany_bottom_in[25];
assign chany_top_out[26] = chany_bottom_in[26];
assign chany_top_out[27] = chany_bottom_in[27];
assign chany_top_out[28] = chany_bottom_in[28];
assign chany_top_out[29] = chany_bottom_in[29];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign chany_bottom_out[20] = chany_top_in[20];
assign chany_bottom_out[21] = chany_top_in[21];
assign chany_bottom_out[22] = chany_top_in[22];
assign chany_bottom_out[23] = chany_top_in[23];
assign chany_bottom_out[24] = chany_top_in[24];
assign chany_bottom_out[25] = chany_top_in[25];
assign chany_bottom_out[26] = chany_top_in[26];
assign chany_bottom_out[27] = chany_top_in[27];
assign chany_bottom_out[28] = chany_top_in[28];
assign chany_bottom_out[29] = chany_top_in[29];
mux_tree_tapbuf_size12 mux_right_ipin_0
(
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size12_0_sram),
.sram_inv(mux_right_ipin_0_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_)
);
mux_tree_tapbuf_size12 mux_right_ipin_2
(
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
.sram(mux_tree_tapbuf_size12_1_sram),
.sram_inv(mux_right_ipin_2_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_)
);
mux_tree_tapbuf_size12 mux_right_ipin_4
(
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
.sram(mux_tree_tapbuf_size12_2_sram),
.sram_inv(mux_right_ipin_4_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_)
);
mux_tree_tapbuf_size12 mux_right_ipin_6
(
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size12_3_sram),
.sram_inv(mux_right_ipin_6_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_)
);
mux_tree_tapbuf_size12 mux_right_ipin_8
(
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
.sram(mux_tree_tapbuf_size12_4_sram),
.sram_inv(mux_right_ipin_8_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_)
);
mux_tree_tapbuf_size12 mux_right_ipin_10
(
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
.sram(mux_tree_tapbuf_size12_5_sram),
.sram_inv(mux_right_ipin_10_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_)
);
mux_tree_tapbuf_size12 mux_right_ipin_12
(
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size12_6_sram),
.sram_inv(mux_right_ipin_12_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_)
);
mux_tree_tapbuf_size12 mux_right_ipin_14
(
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
.sram(mux_tree_tapbuf_size12_7_sram),
.sram_inv(mux_right_ipin_14_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_0
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_2
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_4
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_6
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_8
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_4_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_10
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_5_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_12
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_6_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_14
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_7_sram)
);
mux_tree_tapbuf_size10 mux_right_ipin_1
(
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[25], chany_top_in[25]}),
.sram(mux_tree_tapbuf_size10_0_sram),
.sram_inv(mux_right_ipin_1_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_)
);
mux_tree_tapbuf_size10 mux_right_ipin_3
(
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[27], chany_top_in[27]}),
.sram(mux_tree_tapbuf_size10_1_sram),
.sram_inv(mux_right_ipin_3_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_)
);
mux_tree_tapbuf_size10 mux_right_ipin_5
(
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}),
.sram(mux_tree_tapbuf_size10_2_sram),
.sram_inv(mux_right_ipin_5_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_)
);
mux_tree_tapbuf_size10 mux_right_ipin_7
(
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}),
.sram(mux_tree_tapbuf_size10_3_sram),
.sram_inv(mux_right_ipin_7_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_)
);
mux_tree_tapbuf_size10 mux_right_ipin_9
(
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size10_4_sram),
.sram_inv(mux_right_ipin_9_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_)
);
mux_tree_tapbuf_size10 mux_right_ipin_11
(
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}),
.sram(mux_tree_tapbuf_size10_5_sram),
.sram_inv(mux_right_ipin_11_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_)
);
mux_tree_tapbuf_size10 mux_right_ipin_13
(
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}),
.sram(mux_tree_tapbuf_size10_6_sram),
.sram_inv(mux_right_ipin_13_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_)
);
mux_tree_tapbuf_size10 mux_right_ipin_15
(
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}),
.sram(mux_tree_tapbuf_size10_7_sram),
.sram_inv(mux_right_ipin_15_undriven_sram_inv),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_1
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_3
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_5
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_7
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_9
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_11
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_13
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_15
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram)
);
endmodule |
module logical_tile_clb_mode_default__fle
(
prog_reset,
prog_clk,
test_enable,
fle_in,
fle_reg_in,
fle_sc_in,
fle_cin,
fle_reset,
fle_clk,
ccff_head,
fle_out,
fle_reg_out,
fle_sc_out,
fle_cout,
ccff_tail
);
input prog_reset;
input prog_clk;
input test_enable;
input [0:3]fle_in;
input fle_reg_in;
input fle_sc_in;
input fle_cin;
input fle_reset;
input fle_clk;
input ccff_head;
output [0:1]fle_out;
output fle_reg_out;
output fle_sc_out;
output fle_cout;
output ccff_tail;
wire prog_reset;
wire prog_clk;
wire test_enable;
wire [0:3]fle_in;
wire fle_reg_in;
wire fle_sc_in;
wire fle_cin;
wire fle_reset;
wire fle_clk;
wire ccff_head;
wire [0:1]fle_out;
wire fle_reg_out;
wire fle_sc_out;
wire fle_cout;
wire ccff_tail;
wire direct_interc_10_out;
wire direct_interc_11_out;
wire direct_interc_12_out;
wire direct_interc_13_out;
wire direct_interc_5_out;
wire direct_interc_6_out;
wire direct_interc_7_out;
wire direct_interc_8_out;
wire direct_interc_9_out;
wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout;
wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out;
wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.test_enable(test_enable),
.fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
.fabric_reg_in(direct_interc_9_out),
.fabric_sc_in(direct_interc_10_out),
.fabric_cin(direct_interc_11_out),
.fabric_reset(direct_interc_12_out),
.fabric_clk(direct_interc_13_out),
.ccff_head(ccff_head),
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out),
.fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out),
.fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out),
.fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
.ccff_tail(ccff_tail)
);
direct_interc direct_interc_0_
(
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
.out(fle_out[0])
);
direct_interc direct_interc_1_
(
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
.out(fle_out[1])
);
direct_interc direct_interc_2_
(
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out),
.out(fle_reg_out)
);
direct_interc direct_interc_3_
(
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out),
.out(fle_sc_out)
);
direct_interc direct_interc_4_
(
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
.out(fle_cout)
);
direct_interc direct_interc_5_
(
.in(fle_in[0]),
.out(direct_interc_5_out)
);
direct_interc direct_interc_6_
(
.in(fle_in[1]),
.out(direct_interc_6_out)
);
direct_interc direct_interc_7_
(
.in(fle_in[2]),
.out(direct_interc_7_out)
);
direct_interc direct_interc_8_
(
.in(fle_in[3]),
.out(direct_interc_8_out)
);
direct_interc direct_interc_9_
(
.in(fle_reg_in),
.out(direct_interc_9_out)
);
direct_interc direct_interc_10_
(
.in(fle_sc_in),
.out(direct_interc_10_out)
);
direct_interc direct_interc_11_
(
.in(fle_cin),
.out(direct_interc_11_out)
);
direct_interc direct_interc_12_
(
.in(fle_reset),
.out(direct_interc_12_out)
);
direct_interc direct_interc_13_
(
.in(fle_clk),
.out(direct_interc_13_out)
);
endmodule |
module grid_clb
(
prog_reset,
prog_clk,
test_enable,
top_width_0_height_0_subtile_0__pin_I0_0_,
top_width_0_height_0_subtile_0__pin_I0_1_,
top_width_0_height_0_subtile_0__pin_I0i_0_,
top_width_0_height_0_subtile_0__pin_I0i_1_,
top_width_0_height_0_subtile_0__pin_I1_0_,
top_width_0_height_0_subtile_0__pin_I1_1_,
top_width_0_height_0_subtile_0__pin_I1i_0_,
top_width_0_height_0_subtile_0__pin_I1i_1_,
top_width_0_height_0_subtile_0__pin_I2_0_,
top_width_0_height_0_subtile_0__pin_I2_1_,
top_width_0_height_0_subtile_0__pin_I2i_0_,
top_width_0_height_0_subtile_0__pin_I2i_1_,
top_width_0_height_0_subtile_0__pin_I3_0_,
top_width_0_height_0_subtile_0__pin_I3_1_,
top_width_0_height_0_subtile_0__pin_I3i_0_,
top_width_0_height_0_subtile_0__pin_I3i_1_,
top_width_0_height_0_subtile_0__pin_reg_in_0_,
top_width_0_height_0_subtile_0__pin_sc_in_0_,
top_width_0_height_0_subtile_0__pin_cin_0_,
right_width_0_height_0_subtile_0__pin_I4_0_,
right_width_0_height_0_subtile_0__pin_I4_1_,
right_width_0_height_0_subtile_0__pin_I4i_0_,
right_width_0_height_0_subtile_0__pin_I4i_1_,
right_width_0_height_0_subtile_0__pin_I5_0_,
right_width_0_height_0_subtile_0__pin_I5_1_,
right_width_0_height_0_subtile_0__pin_I5i_0_,
right_width_0_height_0_subtile_0__pin_I5i_1_,
right_width_0_height_0_subtile_0__pin_I6_0_,
right_width_0_height_0_subtile_0__pin_I6_1_,
right_width_0_height_0_subtile_0__pin_I6i_0_,
right_width_0_height_0_subtile_0__pin_I6i_1_,
right_width_0_height_0_subtile_0__pin_I7_0_,
right_width_0_height_0_subtile_0__pin_I7_1_,
right_width_0_height_0_subtile_0__pin_I7i_0_,
right_width_0_height_0_subtile_0__pin_I7i_1_,
left_width_0_height_0_subtile_0__pin_reset_0_,
left_width_0_height_0_subtile_0__pin_clk_0_,
ccff_head,
top_width_0_height_0_subtile_0__pin_O_0_,
top_width_0_height_0_subtile_0__pin_O_1_,
top_width_0_height_0_subtile_0__pin_O_2_,
top_width_0_height_0_subtile_0__pin_O_3_,
top_width_0_height_0_subtile_0__pin_O_4_,
top_width_0_height_0_subtile_0__pin_O_5_,
top_width_0_height_0_subtile_0__pin_O_6_,
top_width_0_height_0_subtile_0__pin_O_7_,
right_width_0_height_0_subtile_0__pin_O_8_,
right_width_0_height_0_subtile_0__pin_O_9_,
right_width_0_height_0_subtile_0__pin_O_10_,
right_width_0_height_0_subtile_0__pin_O_11_,
right_width_0_height_0_subtile_0__pin_O_12_,
right_width_0_height_0_subtile_0__pin_O_13_,
right_width_0_height_0_subtile_0__pin_O_14_,
right_width_0_height_0_subtile_0__pin_O_15_,
bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
bottom_width_0_height_0_subtile_0__pin_sc_out_0_,
bottom_width_0_height_0_subtile_0__pin_cout_0_,
ccff_tail
);
input prog_reset;
input prog_clk;
input test_enable;
input top_width_0_height_0_subtile_0__pin_I0_0_;
input top_width_0_height_0_subtile_0__pin_I0_1_;
input top_width_0_height_0_subtile_0__pin_I0i_0_;
input top_width_0_height_0_subtile_0__pin_I0i_1_;
input top_width_0_height_0_subtile_0__pin_I1_0_;
input top_width_0_height_0_subtile_0__pin_I1_1_;
input top_width_0_height_0_subtile_0__pin_I1i_0_;
input top_width_0_height_0_subtile_0__pin_I1i_1_;
input top_width_0_height_0_subtile_0__pin_I2_0_;
input top_width_0_height_0_subtile_0__pin_I2_1_;
input top_width_0_height_0_subtile_0__pin_I2i_0_;
input top_width_0_height_0_subtile_0__pin_I2i_1_;
input top_width_0_height_0_subtile_0__pin_I3_0_;
input top_width_0_height_0_subtile_0__pin_I3_1_;
input top_width_0_height_0_subtile_0__pin_I3i_0_;
input top_width_0_height_0_subtile_0__pin_I3i_1_;
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
input top_width_0_height_0_subtile_0__pin_cin_0_;
input right_width_0_height_0_subtile_0__pin_I4_0_;
input right_width_0_height_0_subtile_0__pin_I4_1_;
input right_width_0_height_0_subtile_0__pin_I4i_0_;
input right_width_0_height_0_subtile_0__pin_I4i_1_;
input right_width_0_height_0_subtile_0__pin_I5_0_;
input right_width_0_height_0_subtile_0__pin_I5_1_;
input right_width_0_height_0_subtile_0__pin_I5i_0_;
input right_width_0_height_0_subtile_0__pin_I5i_1_;
input right_width_0_height_0_subtile_0__pin_I6_0_;
input right_width_0_height_0_subtile_0__pin_I6_1_;
input right_width_0_height_0_subtile_0__pin_I6i_0_;
input right_width_0_height_0_subtile_0__pin_I6i_1_;
input right_width_0_height_0_subtile_0__pin_I7_0_;
input right_width_0_height_0_subtile_0__pin_I7_1_;
input right_width_0_height_0_subtile_0__pin_I7i_0_;
input right_width_0_height_0_subtile_0__pin_I7i_1_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input ccff_head;
output top_width_0_height_0_subtile_0__pin_O_0_;
output top_width_0_height_0_subtile_0__pin_O_1_;
output top_width_0_height_0_subtile_0__pin_O_2_;
output top_width_0_height_0_subtile_0__pin_O_3_;
output top_width_0_height_0_subtile_0__pin_O_4_;
output top_width_0_height_0_subtile_0__pin_O_5_;
output top_width_0_height_0_subtile_0__pin_O_6_;
output top_width_0_height_0_subtile_0__pin_O_7_;
output right_width_0_height_0_subtile_0__pin_O_8_;
output right_width_0_height_0_subtile_0__pin_O_9_;
output right_width_0_height_0_subtile_0__pin_O_10_;
output right_width_0_height_0_subtile_0__pin_O_11_;
output right_width_0_height_0_subtile_0__pin_O_12_;
output right_width_0_height_0_subtile_0__pin_O_13_;
output right_width_0_height_0_subtile_0__pin_O_14_;
output right_width_0_height_0_subtile_0__pin_O_15_;
output bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
output bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
output bottom_width_0_height_0_subtile_0__pin_cout_0_;
output ccff_tail;
wire prog_reset;
wire prog_clk;
wire test_enable;
wire top_width_0_height_0_subtile_0__pin_I0_0_;
wire top_width_0_height_0_subtile_0__pin_I0_1_;
wire top_width_0_height_0_subtile_0__pin_I0i_0_;
wire top_width_0_height_0_subtile_0__pin_I0i_1_;
wire top_width_0_height_0_subtile_0__pin_I1_0_;
wire top_width_0_height_0_subtile_0__pin_I1_1_;
wire top_width_0_height_0_subtile_0__pin_I1i_0_;
wire top_width_0_height_0_subtile_0__pin_I1i_1_;
wire top_width_0_height_0_subtile_0__pin_I2_0_;
wire top_width_0_height_0_subtile_0__pin_I2_1_;
wire top_width_0_height_0_subtile_0__pin_I2i_0_;
wire top_width_0_height_0_subtile_0__pin_I2i_1_;
wire top_width_0_height_0_subtile_0__pin_I3_0_;
wire top_width_0_height_0_subtile_0__pin_I3_1_;
wire top_width_0_height_0_subtile_0__pin_I3i_0_;
wire top_width_0_height_0_subtile_0__pin_I3i_1_;
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
wire top_width_0_height_0_subtile_0__pin_cin_0_;
wire right_width_0_height_0_subtile_0__pin_I4_0_;
wire right_width_0_height_0_subtile_0__pin_I4_1_;
wire right_width_0_height_0_subtile_0__pin_I4i_0_;
wire right_width_0_height_0_subtile_0__pin_I4i_1_;
wire right_width_0_height_0_subtile_0__pin_I5_0_;
wire right_width_0_height_0_subtile_0__pin_I5_1_;
wire right_width_0_height_0_subtile_0__pin_I5i_0_;
wire right_width_0_height_0_subtile_0__pin_I5i_1_;
wire right_width_0_height_0_subtile_0__pin_I6_0_;
wire right_width_0_height_0_subtile_0__pin_I6_1_;
wire right_width_0_height_0_subtile_0__pin_I6i_0_;
wire right_width_0_height_0_subtile_0__pin_I6i_1_;
wire right_width_0_height_0_subtile_0__pin_I7_0_;
wire right_width_0_height_0_subtile_0__pin_I7_1_;
wire right_width_0_height_0_subtile_0__pin_I7i_0_;
wire right_width_0_height_0_subtile_0__pin_I7i_1_;
wire left_width_0_height_0_subtile_0__pin_reset_0_;
wire left_width_0_height_0_subtile_0__pin_clk_0_;
wire ccff_head;
wire top_width_0_height_0_subtile_0__pin_O_0_;
wire top_width_0_height_0_subtile_0__pin_O_1_;
wire top_width_0_height_0_subtile_0__pin_O_2_;
wire top_width_0_height_0_subtile_0__pin_O_3_;
wire top_width_0_height_0_subtile_0__pin_O_4_;
wire top_width_0_height_0_subtile_0__pin_O_5_;
wire top_width_0_height_0_subtile_0__pin_O_6_;
wire top_width_0_height_0_subtile_0__pin_O_7_;
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire right_width_0_height_0_subtile_0__pin_O_10_;
wire right_width_0_height_0_subtile_0__pin_O_11_;
wire right_width_0_height_0_subtile_0__pin_O_12_;
wire right_width_0_height_0_subtile_0__pin_O_13_;
wire right_width_0_height_0_subtile_0__pin_O_14_;
wire right_width_0_height_0_subtile_0__pin_O_15_;
wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
wire ccff_tail;
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0
(
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.test_enable(test_enable),
.clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
.clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
.clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),
.clb_I1i({top_width_0_height_0_subtile_0__pin_I1i_0_, top_width_0_height_0_subtile_0__pin_I1i_1_}),
.clb_I2({top_width_0_height_0_subtile_0__pin_I2_0_, top_width_0_height_0_subtile_0__pin_I2_1_}),
.clb_I2i({top_width_0_height_0_subtile_0__pin_I2i_0_, top_width_0_height_0_subtile_0__pin_I2i_1_}),
.clb_I3({top_width_0_height_0_subtile_0__pin_I3_0_, top_width_0_height_0_subtile_0__pin_I3_1_}),
.clb_I3i({top_width_0_height_0_subtile_0__pin_I3i_0_, top_width_0_height_0_subtile_0__pin_I3i_1_}),
.clb_I4({right_width_0_height_0_subtile_0__pin_I4_0_, right_width_0_height_0_subtile_0__pin_I4_1_}),
.clb_I4i({right_width_0_height_0_subtile_0__pin_I4i_0_, right_width_0_height_0_subtile_0__pin_I4i_1_}),
.clb_I5({right_width_0_height_0_subtile_0__pin_I5_0_, right_width_0_height_0_subtile_0__pin_I5_1_}),
.clb_I5i({right_width_0_height_0_subtile_0__pin_I5i_0_, right_width_0_height_0_subtile_0__pin_I5i_1_}),
.clb_I6({right_width_0_height_0_subtile_0__pin_I6_0_, right_width_0_height_0_subtile_0__pin_I6_1_}),
.clb_I6i({right_width_0_height_0_subtile_0__pin_I6i_0_, right_width_0_height_0_subtile_0__pin_I6i_1_}),
.clb_I7({right_width_0_height_0_subtile_0__pin_I7_0_, right_width_0_height_0_subtile_0__pin_I7_1_}),
.clb_I7i({right_width_0_height_0_subtile_0__pin_I7i_0_, right_width_0_height_0_subtile_0__pin_I7i_1_}),
.clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_),
.clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_),
.clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_),
.clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_),
.clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_),
.ccff_head(ccff_head),
.clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}),
.clb_reg_out(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
.clb_sc_out(bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
.clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),
.ccff_tail(ccff_tail)
);
endmodule |
module mux_tree_tapbuf_size7_mem
(
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:2]mem_out;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
wire [0:2]mem_out;
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
);
endmodule |
module mux_tree_tapbuf_size5_mem
(
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:2]mem_out;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
wire [0:2]mem_out;
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
);
endmodule |
module frac_lut4
(
in,
sram,
sram_inv,
mode,
mode_inv,
lut2_out,
lut3_out,
lut4_out
);
input [0:3]in;
input [0:15]sram;
input [0:15]sram_inv;
input mode;
input mode_inv;
output [0:1]lut2_out;
output [0:1]lut3_out;
output lut4_out;
wire [0:3]in;
wire [0:15]sram;
wire [0:15]sram_inv;
wire mode;
wire mode_inv;
wire [0:1]lut2_out;
wire [0:1]lut3_out;
wire lut4_out;
wire sky130_fd_sc_hd__buf_2_0_X;
wire sky130_fd_sc_hd__buf_2_1_X;
wire sky130_fd_sc_hd__buf_2_2_X;
wire sky130_fd_sc_hd__buf_2_3_X;
wire sky130_fd_sc_hd__inv_1_0_Y;
wire sky130_fd_sc_hd__inv_1_1_Y;
wire sky130_fd_sc_hd__inv_1_2_Y;
wire sky130_fd_sc_hd__inv_1_3_Y;
wire sky130_fd_sc_hd__or2_1_0_X;
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_
(
.A(mode),
.B(in[3]),
.X(sky130_fd_sc_hd__or2_1_0_X)
);
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_
(
.A(in[0]),
.Y(sky130_fd_sc_hd__inv_1_0_Y)
);
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_
(
.A(in[1]),
.Y(sky130_fd_sc_hd__inv_1_1_Y)
);
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_
(
.A(in[2]),
.Y(sky130_fd_sc_hd__inv_1_2_Y)
);
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_
(
.A(sky130_fd_sc_hd__or2_1_0_X),
.Y(sky130_fd_sc_hd__inv_1_3_Y)
);
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_
(
.A(in[0]),
.X(sky130_fd_sc_hd__buf_2_0_X)
);
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_
(
.A(in[1]),
.X(sky130_fd_sc_hd__buf_2_1_X)
);
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_
(
.A(in[2]),
.X(sky130_fd_sc_hd__buf_2_2_X)
);
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_
(
.A(sky130_fd_sc_hd__or2_1_0_X),
.X(sky130_fd_sc_hd__buf_2_3_X)
);
frac_lut4_mux frac_lut4_mux_0_
(
.in(sram),
.sram({sky130_fd_sc_hd__buf_2_0_X, sky130_fd_sc_hd__buf_2_1_X, sky130_fd_sc_hd__buf_2_2_X, sky130_fd_sc_hd__buf_2_3_X}),
.sram_inv({sky130_fd_sc_hd__inv_1_0_Y, sky130_fd_sc_hd__inv_1_1_Y, sky130_fd_sc_hd__inv_1_2_Y, sky130_fd_sc_hd__inv_1_3_Y}),
.lut2_out(lut2_out),
.lut3_out(lut3_out),
.lut4_out(lut4_out)
);
endmodule |
module io
(
IO_ISOL_N,
SOC_IN,
SOC_OUT,
SOC_DIR,
FPGA_OUT,
FPGA_DIR,
FPGA_IN
);
input IO_ISOL_N;
input SOC_IN;
output SOC_OUT;
output SOC_DIR;
input FPGA_OUT;
input FPGA_DIR;
output FPGA_IN;
wire IO_ISOL_N;
wire SOC_IN;
wire SOC_OUT;
wire SOC_DIR;
wire FPGA_OUT;
wire FPGA_DIR;
wire FPGA_IN;
endmodule |
module cby_8__1_(prog_reset,
prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I4_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I4_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I5_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I5_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I6_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I6_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I7_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I7_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:29] chany_bottom_in;
//----- INPUT PORTS -----
input [0:29] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:29] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:29] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_left_ipin_0_undriven_sram_inv;
wire [0:3] mux_left_ipin_1_undriven_sram_inv;
wire [0:3] mux_left_ipin_2_undriven_sram_inv;
wire [0:3] mux_left_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size12_0_sram;
wire [0:3] mux_tree_tapbuf_size12_10_sram;
wire [0:3] mux_tree_tapbuf_size12_11_sram;
wire [0:3] mux_tree_tapbuf_size12_1_sram;
wire [0:3] mux_tree_tapbuf_size12_2_sram;
wire [0:3] mux_tree_tapbuf_size12_3_sram;
wire [0:3] mux_tree_tapbuf_size12_4_sram;
wire [0:3] mux_tree_tapbuf_size12_5_sram;
wire [0:3] mux_tree_tapbuf_size12_6_sram;
wire [0:3] mux_tree_tapbuf_size12_7_sram;
wire [0:3] mux_tree_tapbuf_size12_8_sram;
wire [0:3] mux_tree_tapbuf_size12_9_sram;
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[10] = chany_bottom_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[11] = chany_bottom_in[11];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[12] = chany_bottom_in[12];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[13] = chany_bottom_in[13];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[14] = chany_bottom_in[14];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[15] = chany_bottom_in[15];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[16] = chany_bottom_in[16];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[17] = chany_bottom_in[17];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[18] = chany_bottom_in[18];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[19] = chany_bottom_in[19];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[20] = chany_bottom_in[20];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[21] = chany_bottom_in[21];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[22] = chany_bottom_in[22];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[23] = chany_bottom_in[23];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[24] = chany_bottom_in[24];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[25] = chany_bottom_in[25];
// ----- Local connection due to Wire 26 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[26] = chany_bottom_in[26];
// ----- Local connection due to Wire 27 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[27] = chany_bottom_in[27];
// ----- Local connection due to Wire 28 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[28] = chany_bottom_in[28];
// ----- Local connection due to Wire 29 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[29] = chany_bottom_in[29];
// ----- Local connection due to Wire 30 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 31 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 34 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 35 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 38 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 39 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- Local connection due to Wire 40 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[10] = chany_top_in[10];
// ----- Local connection due to Wire 41 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[11] = chany_top_in[11];
// ----- Local connection due to Wire 42 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[12] = chany_top_in[12];
// ----- Local connection due to Wire 43 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[13] = chany_top_in[13];
// ----- Local connection due to Wire 44 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[14] = chany_top_in[14];
// ----- Local connection due to Wire 45 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[15] = chany_top_in[15];
// ----- Local connection due to Wire 46 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[16] = chany_top_in[16];
// ----- Local connection due to Wire 47 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[17] = chany_top_in[17];
// ----- Local connection due to Wire 48 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[18] = chany_top_in[18];
// ----- Local connection due to Wire 49 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[19] = chany_top_in[19];
// ----- Local connection due to Wire 50 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[20] = chany_top_in[20];
// ----- Local connection due to Wire 51 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[21] = chany_top_in[21];
// ----- Local connection due to Wire 52 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[22] = chany_top_in[22];
// ----- Local connection due to Wire 53 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[23] = chany_top_in[23];
// ----- Local connection due to Wire 54 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[24] = chany_top_in[24];
// ----- Local connection due to Wire 55 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[25] = chany_top_in[25];
// ----- Local connection due to Wire 56 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[26] = chany_top_in[26];
// ----- Local connection due to Wire 57 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[27] = chany_top_in[27];
// ----- Local connection due to Wire 58 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[28] = chany_top_in[28];
// ----- Local connection due to Wire 59 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[29] = chany_top_in[29];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size12 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size12_0_sram[0:3]),
.sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_left_ipin_1 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}),
.sram(mux_tree_tapbuf_size12_1_sram[0:3]),
.sram_inv(mux_left_ipin_1_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_left_ipin_2 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
.sram(mux_tree_tapbuf_size12_2_sram[0:3]),
.sram_inv(mux_left_ipin_2_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_left_ipin_3 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}),
.sram(mux_tree_tapbuf_size12_3_sram[0:3]),
.sram_inv(mux_left_ipin_3_undriven_sram_inv[0:3]),
.out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_right_ipin_0 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
.sram(mux_tree_tapbuf_size12_4_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_));
mux_tree_tapbuf_size12 mux_right_ipin_2 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size12_5_sram[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_));
mux_tree_tapbuf_size12 mux_right_ipin_4 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
.sram(mux_tree_tapbuf_size12_6_sram[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5_0_));
mux_tree_tapbuf_size12 mux_right_ipin_6 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
.sram(mux_tree_tapbuf_size12_7_sram[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_0_));
mux_tree_tapbuf_size12 mux_right_ipin_8 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size12_8_sram[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6_0_));
mux_tree_tapbuf_size12 mux_right_ipin_10 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
.sram(mux_tree_tapbuf_size12_9_sram[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_0_));
mux_tree_tapbuf_size12 mux_right_ipin_12 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28]}),
.sram(mux_tree_tapbuf_size12_10_sram[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7_0_));
mux_tree_tapbuf_size12 mux_right_ipin_14 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size12_11_sram[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_));
mux_tree_tapbuf_size12_mem mem_left_ipin_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_left_ipin_1 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_left_ipin_2 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_left_ipin_3 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_4_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_2 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_5_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_4 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_6_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_6 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_7_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_8 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_8_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_10 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_9_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_12 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_10_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_14 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_11_sram[0:3]));
mux_tree_tapbuf_size10 mux_right_ipin_1 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29]}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_));
mux_tree_tapbuf_size10 mux_right_ipin_3 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I4i_1_));
mux_tree_tapbuf_size10 mux_right_ipin_5 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5_1_));
mux_tree_tapbuf_size10 mux_right_ipin_7 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26]}),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I5i_1_));
mux_tree_tapbuf_size10 mux_right_ipin_9 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28]}),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6_1_));
mux_tree_tapbuf_size10 mux_right_ipin_11 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21]}),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I6i_1_));
mux_tree_tapbuf_size10 mux_right_ipin_13 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[23], chany_top_in[23]}),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_));
mux_tree_tapbuf_size10 mux_right_ipin_15 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_));
mux_tree_tapbuf_size10_mem mem_right_ipin_1 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_3 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_5 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_7 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_9 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_11 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_13 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_right_ipin_15 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]));
endmodule |
module cby_0__1_(prog_reset,
prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:29] chany_bottom_in;
//----- INPUT PORTS -----
input [0:29] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:29] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:29] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size12_0_sram;
wire [0:3] mux_tree_tapbuf_size12_1_sram;
wire [0:3] mux_tree_tapbuf_size12_2_sram;
wire [0:3] mux_tree_tapbuf_size12_3_sram;
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[10] = chany_bottom_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[11] = chany_bottom_in[11];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[12] = chany_bottom_in[12];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[13] = chany_bottom_in[13];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[14] = chany_bottom_in[14];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[15] = chany_bottom_in[15];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[16] = chany_bottom_in[16];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[17] = chany_bottom_in[17];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[18] = chany_bottom_in[18];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[19] = chany_bottom_in[19];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[20] = chany_bottom_in[20];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[21] = chany_bottom_in[21];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[22] = chany_bottom_in[22];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[23] = chany_bottom_in[23];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[24] = chany_bottom_in[24];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[25] = chany_bottom_in[25];
// ----- Local connection due to Wire 26 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[26] = chany_bottom_in[26];
// ----- Local connection due to Wire 27 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[27] = chany_bottom_in[27];
// ----- Local connection due to Wire 28 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[28] = chany_bottom_in[28];
// ----- Local connection due to Wire 29 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[29] = chany_bottom_in[29];
// ----- Local connection due to Wire 30 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 31 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 34 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 35 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 38 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 39 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- Local connection due to Wire 40 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[10] = chany_top_in[10];
// ----- Local connection due to Wire 41 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[11] = chany_top_in[11];
// ----- Local connection due to Wire 42 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[12] = chany_top_in[12];
// ----- Local connection due to Wire 43 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[13] = chany_top_in[13];
// ----- Local connection due to Wire 44 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[14] = chany_top_in[14];
// ----- Local connection due to Wire 45 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[15] = chany_top_in[15];
// ----- Local connection due to Wire 46 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[16] = chany_top_in[16];
// ----- Local connection due to Wire 47 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[17] = chany_top_in[17];
// ----- Local connection due to Wire 48 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[18] = chany_top_in[18];
// ----- Local connection due to Wire 49 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[19] = chany_top_in[19];
// ----- Local connection due to Wire 50 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[20] = chany_top_in[20];
// ----- Local connection due to Wire 51 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[21] = chany_top_in[21];
// ----- Local connection due to Wire 52 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[22] = chany_top_in[22];
// ----- Local connection due to Wire 53 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[23] = chany_top_in[23];
// ----- Local connection due to Wire 54 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[24] = chany_top_in[24];
// ----- Local connection due to Wire 55 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[25] = chany_top_in[25];
// ----- Local connection due to Wire 56 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[26] = chany_top_in[26];
// ----- Local connection due to Wire 57 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[27] = chany_top_in[27];
// ----- Local connection due to Wire 58 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[28] = chany_top_in[28];
// ----- Local connection due to Wire 59 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[29] = chany_top_in[29];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size12 mux_right_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24]}),
.sram(mux_tree_tapbuf_size12_0_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_right_ipin_1 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25]}),
.sram(mux_tree_tapbuf_size12_1_sram[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_right_ipin_2 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26]}),
.sram(mux_tree_tapbuf_size12_2_sram[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_right_ipin_3 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27]}),
.sram(mux_tree_tapbuf_size12_3_sram[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size12_mem mem_right_ipin_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_1 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_2 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_right_ipin_3 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]));
endmodule |
module cbx_1__0_(prog_reset,
prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:29] chanx_left_in;
//----- INPUT PORTS -----
input [0:29] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:29] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:29] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size12_0_sram;
wire [0:3] mux_tree_tapbuf_size12_1_sram;
wire [0:3] mux_tree_tapbuf_size12_2_sram;
wire [0:3] mux_tree_tapbuf_size12_3_sram;
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[10] = chanx_left_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[11] = chanx_left_in[11];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[12] = chanx_left_in[12];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[13] = chanx_left_in[13];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[14] = chanx_left_in[14];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[15] = chanx_left_in[15];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[16] = chanx_left_in[16];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[17] = chanx_left_in[17];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[18] = chanx_left_in[18];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[19] = chanx_left_in[19];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[20] = chanx_left_in[20];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[21] = chanx_left_in[21];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[22] = chanx_left_in[22];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[23] = chanx_left_in[23];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[24] = chanx_left_in[24];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[25] = chanx_left_in[25];
// ----- Local connection due to Wire 26 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[26] = chanx_left_in[26];
// ----- Local connection due to Wire 27 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[27] = chanx_left_in[27];
// ----- Local connection due to Wire 28 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[28] = chanx_left_in[28];
// ----- Local connection due to Wire 29 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[29] = chanx_left_in[29];
// ----- Local connection due to Wire 30 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 31 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 34 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 35 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 38 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 39 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- Local connection due to Wire 40 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[10] = chanx_right_in[10];
// ----- Local connection due to Wire 41 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[11] = chanx_right_in[11];
// ----- Local connection due to Wire 42 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[12] = chanx_right_in[12];
// ----- Local connection due to Wire 43 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[13] = chanx_right_in[13];
// ----- Local connection due to Wire 44 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[14] = chanx_right_in[14];
// ----- Local connection due to Wire 45 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[15] = chanx_right_in[15];
// ----- Local connection due to Wire 46 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[16] = chanx_right_in[16];
// ----- Local connection due to Wire 47 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[17] = chanx_right_in[17];
// ----- Local connection due to Wire 48 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[18] = chanx_right_in[18];
// ----- Local connection due to Wire 49 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[19] = chanx_right_in[19];
// ----- Local connection due to Wire 50 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[20] = chanx_right_in[20];
// ----- Local connection due to Wire 51 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[21] = chanx_right_in[21];
// ----- Local connection due to Wire 52 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[22] = chanx_right_in[22];
// ----- Local connection due to Wire 53 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[23] = chanx_right_in[23];
// ----- Local connection due to Wire 54 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[24] = chanx_right_in[24];
// ----- Local connection due to Wire 55 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[25] = chanx_right_in[25];
// ----- Local connection due to Wire 56 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[26] = chanx_right_in[26];
// ----- Local connection due to Wire 57 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[27] = chanx_right_in[27];
// ----- Local connection due to Wire 58 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[28] = chanx_right_in[28];
// ----- Local connection due to Wire 59 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[29] = chanx_right_in[29];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size12 mux_top_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
.sram(mux_tree_tapbuf_size12_0_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_top_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25]}),
.sram(mux_tree_tapbuf_size12_1_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_top_ipin_2 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
.sram(mux_tree_tapbuf_size12_2_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size12 mux_top_ipin_3 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27]}),
.sram(mux_tree_tapbuf_size12_3_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size12_mem mem_top_ipin_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_1 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_2 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_3 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]));
endmodule |
module sb_0__0_(prog_reset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
chanx_right_in,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_right_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:29] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:29] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:29] chany_top_out;
//----- OUTPUT PORTS -----
output [0:29] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:1] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_44_undriven_sram_inv;
wire [0:1] mux_right_track_46_undriven_sram_inv;
wire [0:1] mux_right_track_48_undriven_sram_inv;
wire [0:1] mux_right_track_4_undriven_sram_inv;
wire [0:1] mux_right_track_50_undriven_sram_inv;
wire [0:1] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_28_undriven_sram_inv;
wire [0:1] mux_top_track_2_undriven_sram_inv;
wire [0:1] mux_top_track_30_undriven_sram_inv;
wire [0:1] mux_top_track_32_undriven_sram_inv;
wire [0:1] mux_top_track_34_undriven_sram_inv;
wire [0:1] mux_top_track_44_undriven_sram_inv;
wire [0:1] mux_top_track_46_undriven_sram_inv;
wire [0:1] mux_top_track_48_undriven_sram_inv;
wire [0:1] mux_top_track_4_undriven_sram_inv;
wire [0:1] mux_top_track_50_undriven_sram_inv;
wire [0:1] mux_top_track_6_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_18_sram;
wire [0:1] mux_tree_tapbuf_size2_19_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_20_sram;
wire [0:1] mux_tree_tapbuf_size2_21_sram;
wire [0:1] mux_tree_tapbuf_size2_22_sram;
wire [0:1] mux_tree_tapbuf_size2_23_sram;
wire [0:1] mux_tree_tapbuf_size2_24_sram;
wire [0:1] mux_tree_tapbuf_size2_25_sram;
wire [0:1] mux_tree_tapbuf_size2_26_sram;
wire [0:1] mux_tree_tapbuf_size2_27_sram;
wire [0:1] mux_tree_tapbuf_size2_28_sram;
wire [0:1] mux_tree_tapbuf_size2_29_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_30_sram;
wire [0:1] mux_tree_tapbuf_size2_31_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[10] = chany_top_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[11] = chany_top_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[12] = chany_top_in[11];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[13] = chany_top_in[12];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[18] = chany_top_in[17];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[19] = chany_top_in[18];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[20] = chany_top_in[19];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[21] = chany_top_in[20];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[26] = chany_top_in[25];
// ----- Local connection due to Wire 26 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[27] = chany_top_in[26];
// ----- Local connection due to Wire 27 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[28] = chany_top_in[27];
// ----- Local connection due to Wire 28 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[29] = chany_top_in[28];
// ----- Local connection due to Wire 34 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[29] = chanx_right_in[0];
// ----- Local connection due to Wire 45 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[10] = chanx_right_in[11];
// ----- Local connection due to Wire 46 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[11] = chanx_right_in[12];
// ----- Local connection due to Wire 47 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[12] = chanx_right_in[13];
// ----- Local connection due to Wire 48 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[13] = chanx_right_in[14];
// ----- Local connection due to Wire 53 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[18] = chanx_right_in[19];
// ----- Local connection due to Wire 54 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[19] = chanx_right_in[20];
// ----- Local connection due to Wire 55 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[20] = chanx_right_in[21];
// ----- Local connection due to Wire 56 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[21] = chanx_right_in[22];
// ----- Local connection due to Wire 61 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[26] = chanx_right_in[27];
// ----- Local connection due to Wire 62 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[27] = chanx_right_in[28];
// ----- Local connection due to Wire 63 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[28] = chanx_right_in[29];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size3 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[1]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:1]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size3 mux_top_track_6 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[4]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:1]),
.out(chany_top_out[3]));
mux_tree_tapbuf_size3 mux_right_track_0 (
.in({chany_top_in[29], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:1]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size3 mux_right_track_6 (
.in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_tree_tapbuf_size3_mem mem_top_track_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_6 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_6 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
mux_tree_tapbuf_size2 mux_top_track_2 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:1]),
.out(chany_top_out[1]));
mux_tree_tapbuf_size2 mux_top_track_4 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_tree_tapbuf_size2 mux_top_track_8 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size2 mux_top_track_10 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[6]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_tree_tapbuf_size2 mux_top_track_12 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6]));
mux_tree_tapbuf_size2 mux_top_track_14 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7]));
mux_tree_tapbuf_size2 mux_top_track_16 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size2 mux_top_track_18 (
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9]));
mux_tree_tapbuf_size2 mux_top_track_28 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[15]}),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_top_track_28_undriven_sram_inv[0:1]),
.out(chany_top_out[14]));
mux_tree_tapbuf_size2 mux_top_track_30 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[16]}),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_top_track_30_undriven_sram_inv[0:1]),
.out(chany_top_out[15]));
mux_tree_tapbuf_size2 mux_top_track_32 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[17]}),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:1]),
.out(chany_top_out[16]));
mux_tree_tapbuf_size2 mux_top_track_34 (
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[18]}),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_top_track_34_undriven_sram_inv[0:1]),
.out(chany_top_out[17]));
mux_tree_tapbuf_size2 mux_top_track_44 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[23]}),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_top_track_44_undriven_sram_inv[0:1]),
.out(chany_top_out[22]));
mux_tree_tapbuf_size2 mux_top_track_46 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[24]}),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_top_track_46_undriven_sram_inv[0:1]),
.out(chany_top_out[23]));
mux_tree_tapbuf_size2 mux_top_track_48 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[25]}),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_top_track_48_undriven_sram_inv[0:1]),
.out(chany_top_out[24]));
mux_tree_tapbuf_size2 mux_top_track_50 (
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[26]}),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_top_track_50_undriven_sram_inv[0:1]),
.out(chany_top_out[25]));
mux_tree_tapbuf_size2 mux_right_track_2 (
.in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:1]),
.out(chanx_right_out[1]));
mux_tree_tapbuf_size2 mux_right_track_4 (
.in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size2 mux_right_track_8 (
.in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_18_sram[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size2 mux_right_track_10 (
.in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_19_sram[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_tree_tapbuf_size2 mux_right_track_12 (
.in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_20_sram[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_tree_tapbuf_size2 mux_right_track_14 (
.in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_21_sram[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7]));
mux_tree_tapbuf_size2 mux_right_track_16 (
.in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_22_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size2 mux_right_track_18 (
.in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_23_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9]));
mux_tree_tapbuf_size2 mux_right_track_28 (
.in({chany_top_in[13], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_24_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14]));
mux_tree_tapbuf_size2 mux_right_track_30 (
.in({chany_top_in[14], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_25_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15]));
mux_tree_tapbuf_size2 mux_right_track_32 (
.in({chany_top_in[15], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_26_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16]));
mux_tree_tapbuf_size2 mux_right_track_34 (
.in({chany_top_in[16], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_27_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17]));
mux_tree_tapbuf_size2 mux_right_track_44 (
.in({chany_top_in[21], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_28_sram[0:1]),
.sram_inv(mux_right_track_44_undriven_sram_inv[0:1]),
.out(chanx_right_out[22]));
mux_tree_tapbuf_size2 mux_right_track_46 (
.in({chany_top_in[22], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_29_sram[0:1]),
.sram_inv(mux_right_track_46_undriven_sram_inv[0:1]),
.out(chanx_right_out[23]));
mux_tree_tapbuf_size2 mux_right_track_48 (
.in({chany_top_in[23], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_30_sram[0:1]),
.sram_inv(mux_right_track_48_undriven_sram_inv[0:1]),
.out(chanx_right_out[24]));
mux_tree_tapbuf_size2 mux_right_track_50 (
.in({chany_top_in[24], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_31_sram[0:1]),
.sram_inv(mux_right_track_50_undriven_sram_inv[0:1]),
.out(chanx_right_out[25]));
mux_tree_tapbuf_size2_mem mem_top_track_2 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_4 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_8 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_10 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_12 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_14 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_16 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_18 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_28 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_30 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_32 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_34 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_44 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_46 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_48 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_50 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_2 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_4 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_8 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_10 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_12 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_20_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_14 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_21_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_16 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_22_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_18 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_23_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_28 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_24_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_30 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_25_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_32 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_26_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_34 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_27_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_44 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_28_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_46 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_29_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_48 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_30_sram[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_50 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_31_sram[0:1]));
endmodule |
module cbx_1__1_(prog_reset,
prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:29] chanx_left_in;
//----- INPUT PORTS -----
input [0:29] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:29] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:29] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size12_0_sram;
wire [0:3] mux_tree_tapbuf_size12_1_sram;
wire [0:3] mux_tree_tapbuf_size12_2_sram;
wire [0:3] mux_tree_tapbuf_size12_3_sram;
wire [0:3] mux_tree_tapbuf_size12_4_sram;
wire [0:3] mux_tree_tapbuf_size12_5_sram;
wire [0:3] mux_tree_tapbuf_size12_6_sram;
wire [0:3] mux_tree_tapbuf_size12_7_sram;
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[10] = chanx_left_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[11] = chanx_left_in[11];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[12] = chanx_left_in[12];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[13] = chanx_left_in[13];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[14] = chanx_left_in[14];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[15] = chanx_left_in[15];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[16] = chanx_left_in[16];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[17] = chanx_left_in[17];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[18] = chanx_left_in[18];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[19] = chanx_left_in[19];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[20] = chanx_left_in[20];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[21] = chanx_left_in[21];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[22] = chanx_left_in[22];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[23] = chanx_left_in[23];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[24] = chanx_left_in[24];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[25] = chanx_left_in[25];
// ----- Local connection due to Wire 26 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[26] = chanx_left_in[26];
// ----- Local connection due to Wire 27 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[27] = chanx_left_in[27];
// ----- Local connection due to Wire 28 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[28] = chanx_left_in[28];
// ----- Local connection due to Wire 29 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[29] = chanx_left_in[29];
// ----- Local connection due to Wire 30 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 31 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 34 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 35 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 38 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 39 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- Local connection due to Wire 40 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[10] = chanx_right_in[10];
// ----- Local connection due to Wire 41 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[11] = chanx_right_in[11];
// ----- Local connection due to Wire 42 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[12] = chanx_right_in[12];
// ----- Local connection due to Wire 43 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[13] = chanx_right_in[13];
// ----- Local connection due to Wire 44 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[14] = chanx_right_in[14];
// ----- Local connection due to Wire 45 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[15] = chanx_right_in[15];
// ----- Local connection due to Wire 46 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[16] = chanx_right_in[16];
// ----- Local connection due to Wire 47 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[17] = chanx_right_in[17];
// ----- Local connection due to Wire 48 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[18] = chanx_right_in[18];
// ----- Local connection due to Wire 49 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[19] = chanx_right_in[19];
// ----- Local connection due to Wire 50 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[20] = chanx_right_in[20];
// ----- Local connection due to Wire 51 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[21] = chanx_right_in[21];
// ----- Local connection due to Wire 52 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[22] = chanx_right_in[22];
// ----- Local connection due to Wire 53 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[23] = chanx_right_in[23];
// ----- Local connection due to Wire 54 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[24] = chanx_right_in[24];
// ----- Local connection due to Wire 55 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[25] = chanx_right_in[25];
// ----- Local connection due to Wire 56 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[26] = chanx_right_in[26];
// ----- Local connection due to Wire 57 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[27] = chanx_right_in[27];
// ----- Local connection due to Wire 58 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[28] = chanx_right_in[28];
// ----- Local connection due to Wire 59 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[29] = chanx_right_in[29];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size12 mux_top_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
.sram(mux_tree_tapbuf_size12_0_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_));
mux_tree_tapbuf_size12 mux_top_ipin_2 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
.sram(mux_tree_tapbuf_size12_1_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_));
mux_tree_tapbuf_size12 mux_top_ipin_4 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}),
.sram(mux_tree_tapbuf_size12_2_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_0_));
mux_tree_tapbuf_size12 mux_top_ipin_6 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
.sram(mux_tree_tapbuf_size12_3_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_0_));
mux_tree_tapbuf_size12 mux_top_ipin_8 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
.sram(mux_tree_tapbuf_size12_4_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_0_));
mux_tree_tapbuf_size12 mux_top_ipin_10 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28]}),
.sram(mux_tree_tapbuf_size12_5_sram[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_0_));
mux_tree_tapbuf_size12 mux_top_ipin_12 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24]}),
.sram(mux_tree_tapbuf_size12_6_sram[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_0_));
mux_tree_tapbuf_size12 mux_top_ipin_14 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26]}),
.sram(mux_tree_tapbuf_size12_7_sram[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_));
mux_tree_tapbuf_size12_mem mem_top_ipin_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_2 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_4 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_6 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_8 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_4_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_10 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_5_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_12 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_6_sram[0:3]));
mux_tree_tapbuf_size12_mem mem_top_ipin_14 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_7_sram[0:3]));
mux_tree_tapbuf_size10 mux_top_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[16], chanx_right_in[16], chanx_left_in[25], chanx_right_in[25]}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_));
mux_tree_tapbuf_size10 mux_top_ipin_3 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[18], chanx_right_in[18], chanx_left_in[27], chanx_right_in[27]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_1_));
mux_tree_tapbuf_size10 mux_top_ipin_5 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29]}),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1_1_));
mux_tree_tapbuf_size10 mux_top_ipin_7 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22]}),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I1i_1_));
mux_tree_tapbuf_size10 mux_top_ipin_9 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24]}),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2_1_));
mux_tree_tapbuf_size10 mux_top_ipin_11 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26]}),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I2i_1_));
mux_tree_tapbuf_size10 mux_top_ipin_13 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28]}),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3_1_));
mux_tree_tapbuf_size10 mux_top_ipin_15 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21]}),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_));
mux_tree_tapbuf_size10_mem mem_top_ipin_1 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_3 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_5 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_7 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_9 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_11 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_13 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
mux_tree_tapbuf_size10_mem mem_top_ipin_15 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]));
endmodule |
module logical_tile_clb_mode_default__fle(prog_reset,
prog_clk,
test_enable,
fle_in,
fle_reg_in,
fle_sc_in,
fle_cin,
fle_reset,
fle_clk,
ccff_head,
fle_out,
fle_reg_out,
fle_sc_out,
fle_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] test_enable;
//----- INPUT PORTS -----
input [0:3] fle_in;
//----- INPUT PORTS -----
input [0:0] fle_reg_in;
//----- INPUT PORTS -----
input [0:0] fle_sc_in;
//----- INPUT PORTS -----
input [0:0] fle_cin;
//----- INPUT PORTS -----
input [0:0] fle_reset;
//----- INPUT PORTS -----
input [0:0] fle_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] fle_out;
//----- OUTPUT PORTS -----
output [0:0] fle_reg_out;
//----- OUTPUT PORTS -----
output [0:0] fle_sc_out;
//----- OUTPUT PORTS -----
output [0:0] fle_cout;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] fle_in;
wire [0:0] fle_reg_in;
wire [0:0] fle_sc_in;
wire [0:0] fle_cin;
wire [0:0] fle_reset;
wire [0:0] fle_clk;
wire [0:1] fle_out;
wire [0:0] fle_reg_out;
wire [0:0] fle_sc_out;
wire [0:0] fle_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_11_out;
wire [0:0] direct_interc_12_out;
wire [0:0] direct_interc_13_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.test_enable(test_enable),
.fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
.fabric_reg_in(direct_interc_9_out),
.fabric_sc_in(direct_interc_10_out),
.fabric_cin(direct_interc_11_out),
.fabric_reset(direct_interc_12_out),
.fabric_clk(direct_interc_13_out),
.ccff_head(ccff_head),
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]),
.fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out),
.fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out),
.fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
.ccff_tail(ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
.out(fle_out[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
.out(fle_out[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out),
.out(fle_reg_out));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out),
.out(fle_sc_out));
direct_interc direct_interc_4_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
.out(fle_cout));
direct_interc direct_interc_5_ (
.in(fle_in[0]),
.out(direct_interc_5_out));
direct_interc direct_interc_6_ (
.in(fle_in[1]),
.out(direct_interc_6_out));
direct_interc direct_interc_7_ (
.in(fle_in[2]),
.out(direct_interc_7_out));
direct_interc direct_interc_8_ (
.in(fle_in[3]),
.out(direct_interc_8_out));
direct_interc direct_interc_9_ (
.in(fle_reg_in),
.out(direct_interc_9_out));
direct_interc direct_interc_10_ (
.in(fle_sc_in),
.out(direct_interc_10_out));
direct_interc direct_interc_11_ (
.in(fle_cin),
.out(direct_interc_11_out));
direct_interc direct_interc_12_ (
.in(fle_reset),
.out(direct_interc_12_out));
direct_interc direct_interc_13_ (
.in(fle_clk),
.out(direct_interc_13_out));
endmodule |
module grid_io_bottom_bottom(isol_n,
prog_reset,
prog_clk,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
top_width_0_height_0_subtile_0__pin_outpad_0_,
top_width_0_height_0_subtile_1__pin_outpad_0_,
top_width_0_height_0_subtile_2__pin_outpad_0_,
top_width_0_height_0_subtile_3__pin_outpad_0_,
ccff_head,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:3] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(test_enable,
ff_D,
ff_DI,
ff_reset,
ff_Q,
ff_clk);
//----- GLOBAL PORTS -----
input [0:0] test_enable;
//----- INPUT PORTS -----
input [0:0] ff_D;
//----- INPUT PORTS -----
input [0:0] ff_DI;
//----- INPUT PORTS -----
input [0:0] ff_reset;
//----- OUTPUT PORTS -----
output [0:0] ff_Q;
//----- CLOCK PORTS -----
input [0:0] ff_clk;
//----- BEGIN wire-connection ports -----
wire [0:0] ff_D;
wire [0:0] ff_DI;
wire [0:0] ff_reset;
wire [0:0] ff_Q;
wire [0:0] ff_clk;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ (
.SCE(test_enable),
.D(ff_D),
.SCD(ff_DI),
.RESET_B(ff_reset),
.CLK(ff_clk),
.Q(ff_Q));
endmodule |
module grid_io_right_right(isol_n,
prog_reset,
prog_clk,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
left_width_0_height_0_subtile_0__pin_outpad_0_,
left_width_0_height_0_subtile_1__pin_outpad_0_,
left_width_0_height_0_subtile_2__pin_outpad_0_,
left_width_0_height_0_subtile_3__pin_outpad_0_,
ccff_head,
left_width_0_height_0_subtile_0__pin_inpad_0_,
left_width_0_height_0_subtile_1__pin_inpad_0_,
left_width_0_height_0_subtile_2__pin_inpad_0_,
left_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:3] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower(carry_follower_a,
carry_follower_b,
carry_follower_cin,
carry_follower_cout);
//----- INPUT PORTS -----
input [0:0] carry_follower_a;
//----- INPUT PORTS -----
input [0:0] carry_follower_b;
//----- INPUT PORTS -----
input [0:0] carry_follower_cin;
//----- OUTPUT PORTS -----
output [0:0] carry_follower_cout;
//----- BEGIN wire-connection ports -----
wire [0:0] carry_follower_a;
wire [0:0] carry_follower_b;
wire [0:0] carry_follower_cin;
wire [0:0] carry_follower_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ (
.A0(carry_follower_a),
.A1(carry_follower_b),
.S(carry_follower_cin),
.X(carry_follower_cout));
endmodule |
module grid_io_top_top(isol_n,
prog_reset,
prog_clk,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
bottom_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_width_0_height_0_subtile_3__pin_outpad_0_,
ccff_head,
bottom_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:3] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule |
module grid_io_left_left(isol_n,
prog_reset,
prog_clk,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
right_width_0_height_0_subtile_0__pin_outpad_0_,
right_width_0_height_0_subtile_1__pin_outpad_0_,
right_width_0_height_0_subtile_2__pin_outpad_0_,
right_width_0_height_0_subtile_3__pin_outpad_0_,
ccff_head,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
right_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:3] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule |
module logical_tile_io_mode_io_(isol_n,
prog_reset,
prog_clk,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
io_outpad,
ccff_head,
io_inpad,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:0] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] io_outpad;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] io_inpad;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:0] io_outpad;
wire [0:0] io_inpad;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_1_out;
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.iopad_outpad(direct_interc_1_out),
.ccff_head(ccff_head),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
.ccff_tail(ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
.out(io_inpad));
direct_interc direct_interc_1_ (
.in(io_outpad),
.out(direct_interc_1_out));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(prog_reset,
prog_clk,
frac_lut4_in,
ccff_head,
frac_lut4_lut2_out,
frac_lut4_lut3_out,
frac_lut4_lut4_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:3] frac_lut4_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] frac_lut4_lut2_out;
//----- OUTPUT PORTS -----
output [0:1] frac_lut4_lut3_out;
//----- OUTPUT PORTS -----
output [0:0] frac_lut4_lut4_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] frac_lut4_in;
wire [0:1] frac_lut4_lut2_out;
wire [0:1] frac_lut4_lut3_out;
wire [0:0] frac_lut4_lut4_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] frac_lut4_0__undriven_mode_inv;
wire [0:15] frac_lut4_0__undriven_sram_inv;
wire [0:0] frac_lut4_0_mode;
wire [0:15] frac_lut4_0_sram;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
frac_lut4 frac_lut4_0_ (
.in(frac_lut4_in[0:3]),
.sram(frac_lut4_0_sram[0:15]),
.sram_inv(frac_lut4_0__undriven_sram_inv[0:15]),
.mode(frac_lut4_0_mode),
.mode_inv(frac_lut4_0__undriven_mode_inv),
.lut2_out(frac_lut4_lut2_out[0:1]),
.lut3_out(frac_lut4_lut3_out[0:1]),
.lut4_out(frac_lut4_lut4_out));
frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode}));
endmodule |
module logical_tile_io_mode_physical__iopad(isol_n,
prog_reset,
prog_clk,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
iopad_outpad,
ccff_head,
iopad_inpad,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:0] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] iopad_outpad;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] iopad_inpad;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:0] iopad_outpad;
wire [0:0] iopad_inpad;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] io_0_en;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
io io_0_ (
.IO_ISOL_N(isol_n),
.SOC_IN(gfpga_pad_io_soc_in),
.SOC_OUT(gfpga_pad_io_soc_out),
.SOC_DIR(gfpga_pad_io_soc_dir),
.FPGA_OUT(iopad_outpad),
.FPGA_DIR(io_0_en),
.FPGA_IN(iopad_inpad));
io_sky130_fd_sc_hd__dfrtp_1_mem io_sky130_fd_sc_hd__dfrtp_1_mem (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.mem_out(io_0_en));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(prog_reset,
prog_clk,
frac_logic_in,
frac_logic_cin,
ccff_head,
frac_logic_out,
frac_logic_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:3] frac_logic_in;
//----- INPUT PORTS -----
input [0:0] frac_logic_cin;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] frac_logic_out;
//----- OUTPUT PORTS -----
output [0:0] frac_logic_cout;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] frac_logic_in;
wire [0:0] frac_logic_cin;
wire [0:1] frac_logic_out;
wire [0:0] frac_logic_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv;
wire [0:1] mux_frac_lut4_0_in_2_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
wire [0:0] mux_tree_size2_1_out;
wire [0:1] mux_tree_size2_1_sram;
wire [0:0] mux_tree_size2_mem_0_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}),
.ccff_head(ccff_head),
.frac_lut4_lut2_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0:1]),
.frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]),
.frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
.carry_follower_a(direct_interc_5_out),
.carry_follower_b(direct_interc_6_out),
.carry_follower_cin(direct_interc_7_out),
.carry_follower_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout));
mux_tree_size2 mux_frac_logic_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_frac_logic_out_0_undriven_sram_inv[0:1]),
.out(frac_logic_out[0]));
mux_tree_size2 mux_frac_lut4_0_in_2 (
.in({frac_logic_cin, frac_logic_in[2]}),
.sram(mux_tree_size2_1_sram[0:1]),
.sram_inv(mux_frac_lut4_0_in_2_undriven_sram_inv[0:1]),
.out(mux_tree_size2_1_out));
mux_tree_size2_mem mem_frac_logic_out_0 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
.mem_out(mux_tree_size2_0_sram[0:1]));
mux_tree_size2_mem mem_frac_lut4_0_in_2 (
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_size2_mem_0_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_size2_1_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),
.out(frac_logic_out[1]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout),
.out(frac_logic_cout));
direct_interc direct_interc_2_ (
.in(frac_logic_in[0]),
.out(direct_interc_2_out));
direct_interc direct_interc_3_ (
.in(frac_logic_in[1]),
.out(direct_interc_3_out));
direct_interc direct_interc_4_ (
.in(frac_logic_in[3]),
.out(direct_interc_4_out));
direct_interc direct_interc_5_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[1]),
.out(direct_interc_5_out));
direct_interc direct_interc_6_ (
.in(frac_logic_cin),
.out(direct_interc_6_out));
direct_interc direct_interc_7_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0]),
.out(direct_interc_7_out));
endmodule |
module mux_tree_tapbuf_size12_mem(prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:3] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[3];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule |
module mux_tree_tapbuf_size3_mem(prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:1] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[1];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule |
module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem(prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out);
//----- GLOBAL PORTS -----
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:16] mem_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[16];
// ----- END Local output short connections -----
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[3]),
.Q(mem_out[4]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[4]),
.Q(mem_out[5]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[5]),
.Q(mem_out[6]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[6]),
.Q(mem_out[7]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[7]),
.Q(mem_out[8]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[8]),
.Q(mem_out[9]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[9]),
.Q(mem_out[10]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[10]),
.Q(mem_out[11]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[11]),
.Q(mem_out[12]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[12]),
.Q(mem_out[13]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[13]),
.Q(mem_out[14]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[14]),
.Q(mem_out[15]));
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ (
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[15]),
.Q(mem_out[16]));
endmodule |
module frac_lut4(in,
sram,
sram_inv,
mode,
mode_inv,
lut2_out,
lut3_out,
lut4_out);
//----- INPUT PORTS -----
input [0:3] in;
//----- INPUT PORTS -----
input [0:15] sram;
//----- INPUT PORTS -----
input [0:15] sram_inv;
//----- INPUT PORTS -----
input [0:0] mode;
//----- INPUT PORTS -----
input [0:0] mode_inv;
//----- OUTPUT PORTS -----
output [0:1] lut2_out;
//----- OUTPUT PORTS -----
output [0:1] lut3_out;
//----- OUTPUT PORTS -----
output [0:0] lut4_out;
//----- BEGIN wire-connection ports -----
wire [0:3] in;
wire [0:1] lut2_out;
wire [0:1] lut3_out;
wire [0:0] lut4_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] sky130_fd_sc_hd__buf_2_0_X;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ (
.A(mode),
.B(in[3]),
.X(sky130_fd_sc_hd__or2_1_0_X));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
.A(in[0]),
.Y(sky130_fd_sc_hd__inv_1_0_Y));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ (
.A(in[1]),
.Y(sky130_fd_sc_hd__inv_1_1_Y));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ (
.A(in[2]),
.Y(sky130_fd_sc_hd__inv_1_2_Y));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X),
.Y(sky130_fd_sc_hd__inv_1_3_Y));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
.A(in[0]),
.X(sky130_fd_sc_hd__buf_2_0_X));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
.A(in[1]),
.X(sky130_fd_sc_hd__buf_2_1_X));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
.A(in[2]),
.X(sky130_fd_sc_hd__buf_2_2_X));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X),
.X(sky130_fd_sc_hd__buf_2_3_X));
frac_lut4_mux frac_lut4_mux_0_ (
.in(sram[0:15]),
.sram({sky130_fd_sc_hd__buf_2_0_X, sky130_fd_sc_hd__buf_2_1_X, sky130_fd_sc_hd__buf_2_2_X, sky130_fd_sc_hd__buf_2_3_X}),
.sram_inv({sky130_fd_sc_hd__inv_1_0_Y, sky130_fd_sc_hd__inv_1_1_Y, sky130_fd_sc_hd__inv_1_2_Y, sky130_fd_sc_hd__inv_1_3_Y}),
.lut2_out(lut2_out[0:1]),
.lut3_out(lut3_out[0:1]),
.lut4_out(lut4_out));
endmodule |
module sky130_fd_sc_hd__inv_1(A,
Y);
//----- INPUT PORTS -----
input [0:0] A;
//----- OUTPUT PORTS -----
output [0:0] Y;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module sky130_fd_sc_hd__buf_2(A,
X);
//----- INPUT PORTS -----
input [0:0] A;
//----- OUTPUT PORTS -----
output [0:0] X;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module sky130_fd_sc_hd__or2_1(A,
B,
X);
//----- INPUT PORTS -----
input [0:0] A;
//----- INPUT PORTS -----
input [0:0] B;
//----- OUTPUT PORTS -----
output [0:0] X;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module sky130_fd_sc_hd__dfrtp_1(RESET_B,
CLK,
D,
Q);
//----- GLOBAL PORTS -----
input [0:0] RESET_B;
//----- GLOBAL PORTS -----
input [0:0] CLK;
//----- INPUT PORTS -----
input [0:0] D;
//----- OUTPUT PORTS -----
output [0:0] Q;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module io(IO_ISOL_N,
SOC_IN,
SOC_OUT,
SOC_DIR,
FPGA_OUT,
FPGA_DIR,
FPGA_IN);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
//----- GPIN PORTS -----
input [0:0] SOC_IN;
//----- GPOUT PORTS -----
output [0:0] SOC_OUT;
//----- GPOUT PORTS -----
output [0:0] SOC_DIR;
//----- INPUT PORTS -----
input [0:0] FPGA_OUT;
//----- INPUT PORTS -----
input [0:0] FPGA_DIR;
//----- OUTPUT PORTS -----
output [0:0] FPGA_IN;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module sky130_fd_sc_hd__mux2_1_wrapper(A0,
A1,
S,
X);
//----- INPUT PORTS -----
input [0:0] A0;
//----- INPUT PORTS -----
input [0:0] A1;
//----- INPUT PORTS -----
input [0:0] S;
//----- OUTPUT PORTS -----
output [0:0] X;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module mult_9(
input [0:8] A,
input [0:8] B,
output [0:17] Y
);
assign Y = A * B;
endmodule |
module mult_18(
input [0:17] A,
input [0:17] B,
output [0:35] Y
);
assign Y = A * B;
endmodule |
module mult_9x9 (
input [0:8] A,
input [0:8] B,
output [0:17] Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
mult_9 #() _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.Y (Y) );
endmodule |
module mult_18x18 (
input [0:17] A,
input [0:17] B,
output [0:35] Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
mult_18 #() _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.Y (Y) );
endmodule |
module digital_io_hd_test;
// Local clock to
// - synchronize stimulus generation
// - trigger checkout point
reg [0:0] clock;
// Local wires for Design Under Test (DUT)
reg [0:0] IO_ISOL_N;
reg [0:0] FPGA_DIR;
reg [0:0] SOC_IN;
reg [0:0] FPGA_OUT;
wire [0:0] SOC_DIR;
wire [0:0] FPGA_IN;
wire [0:0] SOC_OUT;
// ----- Counters for error checking -----
integer num_clock_cycles = 0;
integer num_errors = 0;
integer num_checked_points = 0;
// Clock pulse generation
initial
begin
clock[0] = 1'b0;
end
always
begin
#`CLOCK_PERIOD clock[0] = ~clock[0];
end
// IO_ISOL_N stimuli:
// - enabled for two clock cycles
// - disabled then
initial
begin
IO_ISOL_N[0] = 1'b0;
#(`CLOCK_PERIOD*4) IO_ISOL_N[0] = 1'b1;
end
// FPGA_DIR stimuli: swing between 0 and 1
// - Test if DIR works when IO_ISOL_N is enabled
// - Test if DIR works when IO_ISOL_N is disabled
initial
begin
FPGA_DIR[0] = 1'b0;
#(`CLOCK_PERIOD) FPGA_DIR[0] = 1'b1;
forever #(`CLOCK_PERIOD*4) FPGA_DIR[0] = ~FPGA_DIR[0];
end
// SOC_IN stimuli: swing in the frequency of double clock period
initial
begin
SOC_IN[0] = 1'b0;
end
always
begin
#(`CLOCK_PERIOD*2) SOC_IN[0] = ~SOC_IN[0];
end
// FPGA_OUTPUT stimuli: swing in the frequency of double clock period
initial
begin
FPGA_OUT[0] = 1'b0;
end
always
begin
#(`CLOCK_PERIOD*2) FPGA_OUT[0] = ~FPGA_OUT[0];
end
// Instanciate the digital I/O cell
EMBEDDED_IO_HD IO_DUT (
.IO_ISOL_N(IO_ISOL_N),
.FPGA_DIR(FPGA_DIR),
.FPGA_IN(FPGA_IN),
.FPGA_OUT(FPGA_OUT),
.SOC_DIR(SOC_DIR),
.SOC_IN(SOC_IN),
.SOC_OUT(SOC_OUT)
);
// Count number of clock cycles
always @(posedge clock[0]) begin
num_clock_cycles = num_clock_cycles + 1;
end
// Check expected values at SOC_DIR port
always @(posedge clock[0]) begin
// SOC DIR should stay at logic '1' when IO_ISOL_N is enabled
if (1'b0 == IO_ISOL_N) begin
if (1'b1 !== SOC_DIR) begin
$display("Error: SOC_DIR = %b (expect =%b)", SOC_DIR, 1'b1);
num_errors = num_errors + 1;
end
end else if (1'b1 == IO_ISOL_N) begin
if (FPGA_DIR !== SOC_DIR) begin
$display("Error: SOC_DIR = %b (expect =%b)", SOC_DIR, FPGA_DIR);
num_errors = num_errors + 1;
end
end
num_checked_points = num_checked_points + 1;
end
// Check expected values at FPGA_IN port
always @(posedge clock[0]) begin
// FPGA_IN should be same as SOC_IN when IO_ISOL_N is enabled
if (1'b0 == IO_ISOL_N) begin
if (SOC_IN !== FPGA_IN) begin
$display("Error: FPGA_IN = %b (expect =%b)", FPGA_IN, SOC_IN);
num_errors = num_errors + 1;
end
end else if (1'b1 == IO_ISOL_N) begin
if (1'b1 == FPGA_DIR) begin
if (SOC_IN !== FPGA_IN) begin
$display("Error: FPGA_IN = %b (expect =%b)", FPGA_IN, SOC_IN);
num_errors = num_errors + 1;
end
end else if (1'b0 == FPGA_DIR) begin
if (1'bz !== FPGA_IN) begin
$display("Error: FPGA_IN = %b (expect =%b)", FPGA_IN, 1'bz);
num_errors = num_errors + 1;
end
end
end
num_checked_points = num_checked_points + 1;
end
// Check expected values at SOC_OUT port
always @(posedge clock[0]) begin
// SOC_OUT should be 'z' when IO_ISOL_N is enabled
if (1'b0 == IO_ISOL_N) begin
if (1'bz !== SOC_OUT) begin
$display("Error: SOC_OUT = %b (expect =%b)", SOC_OUT, 1'bz);
num_errors = num_errors + 1;
end
end else if (1'b1 == IO_ISOL_N) begin
if (1'b1 == FPGA_DIR) begin
if (1'bz !== SOC_OUT) begin
$display("Error: SOC_OUT = %b (expect =%b)", SOC_OUT, 1'bz);
num_errors = num_errors + 1;
end
end else if (1'b0 == FPGA_DIR) begin
if (FPGA_OUT !== SOC_OUT) begin
$display("Error: SOC_OUT = %b (expect =%b)", SOC_OUT, FPGA_OUT);
num_errors = num_errors + 1;
end
end
end
num_checked_points = num_checked_points + 1;
end
// Finish after a number of clock cycles
always @(posedge clock[0]) begin
if (`NUM_TEST_CLOCK_CYCLES < num_clock_cycles) begin
$display("Simulation finish with %d errors / %d checkpoints", num_errors, num_checked_points);
$finish;
end
end
endmodule |
module pre_pnr_ccff_test;
// ----- Local wires for global ports of FPGA fabric -----
wire [0:0] prog_clk;
wire [0:0] Test_en;
wire [0:0] clk;
// ----- Local wires for I/Os of FPGA fabric -----
wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [0:0] prog_clock;
reg [0:0] prog_clock_reg;
wire [0:0] op_clock;
reg [0:0] op_clock_reg;
reg [0:0] prog_reset;
reg [0:0] prog_set;
reg [0:0] greset;
reg [0:0] gset;
// ---- Configuration-chain head -----
reg [0:0] ccff_head;
// ---- Configuration-chain tail -----
wire [0:0] ccff_tail;
// ---- Scan-chain head -----
wire [0:0] sc_head;
// ---- Scan-chain tail -----
wire [0:0] sc_tail;
wire [0:0] IO_ISOL_N;
// ----- Counters for error checking -----
integer num_prog_cycles = 0;
integer num_errors = 0;
// Indicate when configuration should be finished
reg config_done = 0;
initial
begin
config_done = 1'b0;
end
// ----- Begin raw programming clock signal generation -----
initial
begin
prog_clock_reg[0] = 1'b0;
end
always
begin
#5 prog_clock_reg[0] = ~prog_clock_reg[0];
end
// ----- End raw programming clock signal generation -----
// ----- Actual programming clock is triggered only when config_done and prog_reset are disabled -----
assign prog_clock[0] = prog_clock_reg[0] & (~prog_reset[0]);
// ----- Begin raw operating clock signal generation -----
initial
begin
op_clock_reg[0] = 1'b0;
end
// ----- End raw operating clock signal generation -----
// ----- Actual operating clock is triggered only when config_done is enabled -----
assign op_clock[0] = op_clock_reg[0];
// ----- Begin programming reset signal generation -----
initial
begin
prog_reset[0] = 1'b1;
#10 prog_reset[0] = 1'b0;
end
// ----- End programming reset signal generation -----
// ----- Begin programming set signal generation -----
initial
begin
prog_set[0] = 1'b1;
#10 prog_set[0] = 1'b0;
end
// ----- End programming set signal generation -----
// ----- Begin operating reset signal generation -----
// ----- Reset signal is disabled always -----
initial
begin
greset[0] = 1'b1;
end
// ----- End operating reset signal generation -----
// ----- Begin operating set signal generation: always disabled -----
initial
begin
gset[0] = 1'b0;
end
// ----- End operating set signal generation: always disabled -----
// ----- Begin connecting global ports of FPGA fabric to stimuli -----
assign clk[0] = op_clock[0];
assign prog_clk[0] = prog_clock[0];
assign Test_en[0] = 1'b0;
assign sc_head[0] = 1'b0;
assign IO_ISOL_N[0] = 1'b0;
// ----- End connecting global ports of FPGA fabric to stimuli -----
// ----- FPGA top-level module to be capsulated -----
fpga_top FPGA_DUT (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.IO_ISOL_N(IO_ISOL_N)
);
// ----- Force constant '0' to FPGA I/O as this testbench only check
// programming phase -----
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
// Generate a pulse after programming reset is disabled (in the 2nd clock
// cycle). Then the head of configuration chain should be always zero
always @(negedge prog_clock[0]) begin
ccff_head = 1'b1;
if (0 != num_prog_cycles) begin
ccff_head = 1'b0;
end
end
// ----- Count the number of programming cycles -------
always @(posedge prog_clock[0]) begin
num_prog_cycles = num_prog_cycles + 1;
// Indicate when configuration is suppose to end
if (`FPGA_BITSTREAM_SIZE + 1 == num_prog_cycles) begin
config_done = 1'b1;
end
// Check the ccff_tail when configuration is done
if (1'b1 == config_done) begin
if (sc_tail != 1'b1) begin
$display("Error: sc_tail = %b", sc_tail);
num_errors = num_errors + 1;
end
$display("Simulation finish with %d errors", num_errors);
// End simulation
$finish;
end
end
endmodule |
module ccff_test_post_pnr_caravel_autocheck_top_tb;
reg clock;
reg RSTB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
// ----- Local wires for control ports of FPGA fabric -----
wire [0:0] pReset;
reg [0:0] prog_clock_reg;
wire [0:0] prog_clk;
wire [0:0] prog_clock;
wire [0:0] Test_en;
wire [0:0] Reset;
reg [0:0] op_clock_reg;
wire [0:0] op_clk;
wire [0:0] op_clock;
reg [0:0] prog_reset;
reg [0:0] greset;
// ---- Configuration-chain head -----
reg [0:0] ccff_head;
// ---- Configuration-chain tail -----
wire [0:0] ccff_tail;
// ---- Scan-chain head -----
wire [0:0] sc_head;
// ---- Scan-chain tail -----
wire [0:0] sc_tail;
wire [0:0] IO_ISOL_N;
// ----- Counters for error checking -----
integer num_prog_cycles = 0;
integer num_errors = 0;
integer num_checked_points = 0;
// Indicate when SoC setup phase should be finished
reg soc_setup_done = 0;
// Indicate when configuration should be finished
reg config_done = 0;
initial
begin
config_done = 1'b0;
soc_setup_done = 1'b0;
end
// ----- Begin raw programming clock signal generation -----
initial
begin
prog_clock_reg[0] = 1'b0;
end
always
begin
#(`FPGA_PROG_CLOCK_PERIOD) prog_clock_reg[0] = ~prog_clock_reg[0];
end
// ----- End raw programming clock signal generation -----
// ----- Begin raw operating clock signal generation -----
initial
begin
op_clock_reg[0] = 1'b0;
end
// ----- End raw operating clock signal generation -----
// ----- Actual operating clock is triggered only when config_done is enabled -----
assign prog_clock[0] = prog_clock_reg[0] & (~prog_reset[0]);
assign op_clock[0] = op_clock_reg[0];
// ----- Begin programming reset signal generation -----
initial
begin
prog_reset[0] = 1'b1;
#(`SOC_SETUP_TIME_PERIOD + 2 * `FPGA_PROG_CLOCK_PERIOD) prog_reset[0] = 1'b0;
end
// ----- End programming reset signal generation -----
// ----- Begin operating reset signal generation -----
// ----- Reset signal is disabled always -----
initial
begin
greset[0] = 1'b1;
end
// ----- End operating reset signal generation -----
// ----- Begin connecting global ports of FPGA fabric to stimuli -----
assign op_clk[0] = op_clock[0];
assign prog_clk[0] = prog_clock[0];
assign pReset[0] = ~prog_reset[0];
assign Reset[0] = ~greset[0];
assign Test_en[0] = 1'b0;
assign sc_head[0] = 1'b0;
assign IO_ISOL_N[0] = ~greset;
// ----- End connecting global ports of FPGA fabric to stimuli -----
assign mprj_io[0] = Test_en;
assign mprj_io[1] = IO_ISOL_N;
assign mprj_io[2] = Reset;
assign mprj_io[3] = pReset;
assign mprj_io[12] = ccff_head;
assign mprj_io[25] = 1'b0; // Set FPGA to interface logic analyzer by default
assign mprj_io[26] = sc_head;
assign mprj_io[36] = op_clk;
assign mprj_io[37] = prog_clk;
assign sc_tail = mprj_io[11];
assign ccff_tail = mprj_io[35];
assign mprj_io[10:4] = {7{1'b0}};
assign mprj_io[24:13] = {12{1'b0}};
assign mprj_io[34:27] = {8{1'b0}};
// Generate a pulse after programming reset is disabled (in the 2nd clock
// cycle). Then the head of configuration chain should be always zero
always @(negedge prog_clock[0]) begin
ccff_head = 1'b1;
if (0 != num_prog_cycles) begin
ccff_head = 1'b0;
end
end
// ----- Count the number of programming cycles -------
always @(posedge prog_clock[0]) begin
num_prog_cycles = num_prog_cycles + 1;
// Indicate when configuration is suppose to end
if (`FPGA_BITSTREAM_SIZE + 1 == num_prog_cycles) begin
config_done = 1'b1;
end
// Check the ccff_tail when configuration is done
if (1'b1 == config_done) begin
// The tail should spit a pulse after configuration is done
// So it should be at logic '1' and then pulled down to logic '0'
if (0 == num_checked_points) begin
if (ccff_tail !== 1'b1) begin
$display("Error: ccff_tail = %b", sc_tail);
num_errors = num_errors + 1;
end
end
if (1 <= num_checked_points) begin
if (ccff_tail !== 1'b0) begin
$display("Error: ccff_tail = %b", sc_tail);
num_errors = num_errors + 1;
end
end
num_checked_points = num_checked_points + 1;
end
if (2 < num_checked_points) begin
$display("Simulation finish with %d errors", num_errors);
// End simulation
$finish;
end
end
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #(`SOC_CLOCK_PERIOD) clock <= (clock === 1'b0);
initial begin
clock = 0;
end
initial begin
RSTB <= 1'b0;
soc_setup_done <= 1'b1;
#(`SOC_RESET_TIME_PERIOD);
RSTB <= 1'b1; // Release reset
soc_setup_done <= 1'b1; // We can start scff test
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
power3 <= 1'b0;
power4 <= 1'b0;
#(`POWER_UP_TIME_PERIOD);
power1 <= 1'b1;
#(`POWER_UP_TIME_PERIOD);
power2 <= 1'b1;
#(`POWER_UP_TIME_PERIOD);
power3 <= 1'b1;
#(`POWER_UP_TIME_PERIOD);
power4 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3 = power1;
wire VDD1V8 = power2;
wire USER_VDD3V3 = power3;
wire USER_VDD1V8 = power4;
wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (USER_VDD3V3),
.vdda2 (USER_VDD3V3),
.vssa1 (VSS),
.vssa2 (VSS),
.vccd1 (USER_VDD1V8),
.vccd2 (USER_VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule |
module EMBEDDED_IO_HD (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_IO_DIR,
input CFG_DONE
);
wire cfg_done_b;
sky130_fd_sc_hd__inv_1 INV (
.A(CFG_DONE),
.Y(cfg_done_b)
);
sky130_fd_sc_hd__or3_1 OR3 (
.A(FPGA_IO_DIR),
.B(FPGA_OUT),
.C(cfg_done_b),
.X(SOC_OUT)
);
sky130_fd_sc_hd__and2_1 AND2 (
.A(FPGA_IO_DIR),
.B(SOC_IN),
.X(FPGA_IN)
);
endmodule |
module fpga_top (
// Fixed I/O interface from Caravel SoC definition
// DO NOT CHANGE!!!
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oen,
// IOs
input [37:0] io_in,
output [37:0] io_out,
output [37:0] io_oeb
);
// Modelsim does NOT like redefining wires that already in the
// input/output ports. The follow lines may be needed when
// `default_nettype none
// is enabled
//wire [`MPRJ_IO_PADS-1:0] io_in;
//wire [`MPRJ_IO_PADS-1:0] io_out;
//wire [`MPRJ_IO_PADS-1:0] io_oeb;
// FPGA wires
wire prog_clk;
wire Test_en;
wire IO_ISOL_N;
wire clk;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire ccff_head;
wire ccff_tail;
wire sc_head;
wire sc_tail;
// Switch between wishbone and logic analyzer
wire wb_la_switch;
wire wb_la_switch_b;
// Inverted switch signal to drive tri-state buffers
// Use drive strength 8 as we will have 33 output pins which is driven by
// the buffers
sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(wb_la_switch), .Y(wb_la_switch_b));
// Autogenerate code start
// Autogenerate code end
// I/O[25] is reserved for a switch between wishbone interface
// and logic analyzer
assign wb_la_switch = io_in[25];
assign io_out[25] = 1'b0;
assign io_oeb[25] = 1'b1;
// TODO: Connect spypad from FPGA to logic analyzer ports
fpga_core fpga_core_uut(.prog_clk(prog_clk),
.Test_en(Test_en),
.clk(clk),
.IO_ISOL_N(IO_ISOL_N),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.sc_head(sc_head),
.sc_tail(sc_tail)
);
endmodule |
module IO (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_IO_DIR,
input CFG_DONE,
input IO_ISOL_N
);
wire cfg_done_b;
wire io_isol;
wire f2a_o_gate;
wire f2a_o_int;
sky130_fd_sc_hd__inv_1 INV_CFG_DONE (
.A(CFG_DONE),
.Y(cfg_done_b)
);
sky130_fd_sc_hd__inv_1 INV_ISOL_N (
.A(IO_ISOL_N),
.Y(io_isol)
);
// output path
sky130_fd_sc_hd__nor2_1 NOR2 (
.A(FPGA_IO_DIR),
.B(cfg_done_b),
.Y(f2a_o_gate)
);
sky130_fd_sc_hd__nand2_1 NAND2 (
.A(FPGA_OUT),
.B(f2a_o_gate),
.Y(f2a_o_int)
);
sky130_fd_sc_hd__einvn_4 EINVN_OUT (
.A(f2a_o_int),
.TE_B(io_isol),
.Z(SOC_OUT)
);
// input path
sky130_fd_sc_hd__and3_1 AND3 (
.A(SOC_IN),
.B(FPGA_IO_DIR),
.C(IO_ISOL_N),
.X(FPGA_IN)
);
endmodule |
module sky130_uuopenfpga_cc_hd_invmux2_1 (Z, Q1, Q2, S0, S0B, S1, S1B);
output Z;
input Q1, Q2, S0, S0B, S1, S1B;
wire Q1__bar, Q2__bar;
not (Q2__bar, Q2);
not (Q1__bar, Q1);
bufif1 (Z, Q1__bar, S0);
bufif1 (Z, Q2__bar, S1);
`ifdef ENABLE_SIGNAL_INITIALIZATION
initial begin
$deposit(Q1, 1'b0);
$deposit(Q2, 1'b0);
end
`endif
specify
(Q1 => Z) = 0.01;
(Q2 => Z) = 0.01;
(S0 => Z) = 0.01;
(S0B => Z) = 0.01;
(S1 => Z) = 0.01;
(S1B => Z) = 0.01;
endspecify
endmodule |
module sky130_uuopenfpga_cc_hd_invmux3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B);
output Z;
input Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B;
wire Q1__bar, Q2__bar, Q3__bar;
not (Q3__bar, Q3);
not (Q2__bar, Q2);
not (Q1__bar, Q1);
bufif1 (Z, Q1__bar, S0);
bufif1 (Z, Q2__bar, S1);
bufif1 (Z, Q3__bar, S2);
`ifdef ENABLE_SIGNAL_INITIALIZATION
initial begin
$deposit(Q1, 1'b0);
$deposit(Q2, 1'b0);
$deposit(Q3, 1'b0);
end
`endif
// Timing
specify
(Q1 => Z) = 0.01;
(Q3 => Z) = 0.01;
(S0 => Z) = 0.01;
(S0B => Z) = 0.01;
(S2 => Z) = 0.01;
(S2B => Z) = 0.01;
endspecify
endmodule |
module QL_CCFF (
input RESET_B,
input SE,
input CFGE,
input D,
input SI,
output Q,
output CFGQN,
output CFGQ,
input CLK
);
sky130_fd_sc_hd__nand2_1 NAND2_CFGQN (
.A(Q),
.B(CFGE),
.X(CFGQN)
);
sky130_fd_sc_hd__inv_1 INV_CFGQN (
.A(CFGQN),
.Y(CFGQ)
);
sky130_fd_sc_hd__sdfrtp_1 SDFRTP (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SI),
.SCE(SE),
.RESET_B(RESET_B)
);
endmodule |
module EMBEDDED_IO_HD (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output SOC_DIR, // Output the directionality
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_DIR, // direction control
input IO_ISOL_N // Isolation enable signal
);
wire SOC_DIR_N;
// Use drive-strength 4 for a high fan-out from SoC components
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
.A(FPGA_DIR),
.X(SOC_DIR)
);
// Use drive-strength 4 for a high fan-out from global routing architecture
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
.A(SOC_IN),
.Z(FPGA_IN)
);
// Use drive-strength 4 for a potential high fan-out from SoC components
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
.A(FPGA_OUT),
.Z(SOC_OUT)
);
endmodule |
module sb_0__2_ ( chanx_right_in , right_top_grid_pin_1_ ,
right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ ,
right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in ,
bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out ,
ccff_tail , SC_IN_TOP , SC_OUT_BOT , prog_clk_0_E_in ) ;
input [0:19] chanx_right_in ;
input [0:0] right_top_grid_pin_1_ ;
input [0:0] right_bottom_grid_pin_34_ ;
input [0:0] right_bottom_grid_pin_35_ ;
input [0:0] right_bottom_grid_pin_36_ ;
input [0:0] right_bottom_grid_pin_37_ ;
input [0:0] right_bottom_grid_pin_38_ ;
input [0:0] right_bottom_grid_pin_39_ ;
input [0:0] right_bottom_grid_pin_40_ ;
input [0:0] right_bottom_grid_pin_41_ ;
input [0:19] chany_bottom_in ;
input [0:0] bottom_left_grid_pin_1_ ;
input [0:0] ccff_head ;
output [0:19] chanx_right_out ;
output [0:19] chany_bottom_out ;
output [0:0] ccff_tail ;
input SC_IN_TOP ;
output SC_OUT_BOT ;
input prog_clk_0_E_in ;
wire ropt_net_88 ;
wire ropt_net_87 ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 (
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] ,
right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] ,
right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) ,
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 } ) ,
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_60 ) ) ;
sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 (
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] ,
right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] ,
right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
SYNOPSYS_UNCONNECTED_6 } ) ,
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_62 ) ) ;
sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 (
.in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
chany_bottom_in[17] } ) ,
.sram ( mux_tree_tapbuf_size5_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
SYNOPSYS_UNCONNECTED_9 } ) ,
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_60 ) ) ;
sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 (
.in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
chany_bottom_in[15] } ) ,
.sram ( mux_tree_tapbuf_size5_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( chanx_right_out[3] ) , .p0 ( optlc_net_60 ) ) ;
sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_8 (
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] ,
chany_bottom_in[14] } ) ,
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
.out ( chanx_right_out[4] ) , .p0 ( optlc_net_60 ) ) ;
sb_0__2__mux_tree_tapbuf_size3 mux_right_track_24 (
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] ,
chany_bottom_in[6] } ) ,
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( chanx_right_out[12] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_10 (
.in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) ,
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
.out ( chanx_right_out[5] ) , .p0 ( optlc_net_62 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_12 (
.in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) ,
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( chanx_right_out[6] ) , .p0 ( optlc_net_62 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_14 (
.in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
.out ( chanx_right_out[7] ) , .p0 ( optlc_net_62 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_16 (
.in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) ,
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( chanx_right_out[8] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_18 (
.in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) ,
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
.out ( chanx_right_out[9] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_20 (
.in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) ,
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( chanx_right_out[10] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_22 (
.in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) ,
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
.out ( chanx_right_out[11] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 (
.in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) ,
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( chanx_right_out[13] ) , .p0 ( optlc_net_60 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_28 (
.in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) ,
.sram ( mux_tree_tapbuf_size2_8_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
.out ( chanx_right_out[14] ) , .p0 ( optlc_net_62 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_30 (
.in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) ,
.sram ( mux_tree_tapbuf_size2_9_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( chanx_right_out[15] ) , .p0 ( optlc_net_62 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_32 (
.in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) ,
.sram ( mux_tree_tapbuf_size2_10_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
.out ( chanx_right_out[16] ) , .p0 ( optlc_net_62 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_34 (
.in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) ,
.sram ( mux_tree_tapbuf_size2_11_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
.out ( chanx_right_out[17] ) , .p0 ( optlc_net_62 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_36 (
.in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) ,
.sram ( mux_tree_tapbuf_size2_12_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
.out ( chanx_right_out[18] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_38 (
.in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) ,
.sram ( mux_tree_tapbuf_size2_13_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
.out ( chanx_right_out[19] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_14 mux_bottom_track_1 (
.in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_14_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
.out ( chany_bottom_out[0] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_15 mux_bottom_track_5 (
.in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_15_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
.out ( chany_bottom_out[2] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_16 mux_bottom_track_9 (
.in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_16_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
.out ( chany_bottom_out[4] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_25 (
.in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_17_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( chany_bottom_out[12] ) , .p0 ( optlc_net_61 ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_20 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_22 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_28 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_30 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_32 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_34 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_36 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_38 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_bottom_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_bottom_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_right_in[0] ) ,
.X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_right_in[1] ) ,
.X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_right_in[2] ) ,
.X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[3] ) ,
.X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chanx_right_in[4] ) ,
.X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[5] ) ,
.X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[7] ) ,
.X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[8] ) ,
.X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[9] ) ,
.X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[10] ) ,
.X ( chany_bottom_out[8] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chanx_right_in[11] ) ,
.X ( ropt_net_88 ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[12] ) ,
.X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[13] ) ,
.X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[15] ) ,
.X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[17] ) ,
.X ( chany_bottom_out[1] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) ,
.X ( ropt_net_87 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) ,
.HI ( optlc_net_60 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) ,
.HI ( optlc_net_61 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) ,
.HI ( optlc_net_62 ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1252 ( .A ( ropt_net_87 ) ,
.X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1253 ( .A ( ropt_net_88 ) ,
.X ( chany_bottom_out[7] ) ) ;
endmodule |
module cbx_1__2_ ( chanx_left_in , chanx_right_in , ccff_head ,
chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ ,
bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper ,
bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT ,
SC_IN_BOT , SC_OUT_TOP , prog_clk_0_S_in , prog_clk_0_W_out ) ;
input [0:19] chanx_left_in ;
input [0:19] chanx_right_in ;
input [0:0] ccff_head ;
output [0:19] chanx_left_out ;
output [0:19] chanx_right_out ;
output [0:0] top_grid_pin_0_ ;
output [0:0] bottom_grid_pin_0_ ;
output [0:0] bottom_grid_pin_1_ ;
output [0:0] bottom_grid_pin_2_ ;
output [0:0] bottom_grid_pin_3_ ;
output [0:0] bottom_grid_pin_4_ ;
output [0:0] bottom_grid_pin_5_ ;
output [0:0] bottom_grid_pin_6_ ;
output [0:0] bottom_grid_pin_7_ ;
output [0:0] bottom_grid_pin_8_ ;
output [0:0] bottom_grid_pin_9_ ;
output [0:0] bottom_grid_pin_10_ ;
output [0:0] bottom_grid_pin_11_ ;
output [0:0] bottom_grid_pin_12_ ;
output [0:0] bottom_grid_pin_13_ ;
output [0:0] bottom_grid_pin_14_ ;
output [0:0] bottom_grid_pin_15_ ;
output [0:0] ccff_tail ;
input [0:0] IO_ISOL_N ;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
input [0:0] bottom_width_0_height_0__pin_0_ ;
output [0:0] bottom_width_0_height_0__pin_1_upper ;
output [0:0] bottom_width_0_height_0__pin_1_lower ;
input SC_IN_TOP ;
output SC_OUT_BOT ;
input SC_IN_BOT ;
output SC_OUT_TOP ;
input prog_clk_0_S_in ;
output prog_clk_0_W_out ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:3] mux_tree_tapbuf_size10_8_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:3] mux_tree_tapbuf_size8_3_sram ;
wire [0:3] mux_tree_tapbuf_size8_4_sram ;
wire [0:3] mux_tree_tapbuf_size8_5_sram ;
wire [0:3] mux_tree_tapbuf_size8_6_sram ;
wire [0:3] mux_tree_tapbuf_size8_7_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
chanx_left_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( top_grid_pin_0_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] ,
chanx_left_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] ,
chanx_left_out[14] } ) ,
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] ,
chanx_left_out[15] } ) ,
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] ,
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
chanx_left_out[18] } ) ,
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
chanx_left_out[19] } ) ,
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] ,
chanx_left_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[17] ,
chanx_left_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
chanx_left_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_8_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_7 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_11 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_12 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
.ccff_tail ( { ccff_tail_mid } ) ,
.mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
chanx_right_out[14] , chanx_left_out[14] } ) ,
.sram ( mux_tree_tapbuf_size8_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
.out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
chanx_right_out[15] , chanx_left_out[15] } ) ,
.sram ( mux_tree_tapbuf_size8_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
.out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] ,
chanx_right_out[18] , chanx_left_out[18] } ) ,
.sram ( mux_tree_tapbuf_size8_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
.out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] ,
chanx_right_out[19] , chanx_left_out[19] } ) ,
.sram ( mux_tree_tapbuf_size8_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
chanx_right_out[14] , chanx_left_out[14] } ) ,
.sram ( mux_tree_tapbuf_size8_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
.out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
chanx_right_out[15] , chanx_left_out[15] } ) ,
.sram ( mux_tree_tapbuf_size8_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
.out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] ,
chanx_right_out[18] , chanx_left_out[18] } ) ,
.sram ( mux_tree_tapbuf_size8_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
.out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] ,
chanx_right_out[19] , chanx_left_out[19] } ) ,
.sram ( mux_tree_tapbuf_size8_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
.out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
.io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
.ccff_head ( { ccff_tail_mid } ) ,
.io_inpad ( bottom_width_0_height_0__pin_1_lower ) ,
.ccff_tail ( ccff_tail ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) ,
.X ( ctsbuf_net_174 ) ) ;
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
.X ( chanx_right_out[0] ) ) ;
sky130_fd_sc_hd__buf_12 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
.X ( chanx_right_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
.X ( chanx_right_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
.X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
.X ( chanx_right_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
.X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
.X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
.X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
.X ( chanx_right_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
.X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
.X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
.X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
.X ( chanx_right_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
.X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
.X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
.X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
.X ( chanx_right_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
.X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
.X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
.X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) ,
.X ( chanx_left_out[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) ,
.X ( chanx_left_out[1] ) ) ;
sky130_fd_sc_hd__buf_12 FTB_41__40 ( .A ( chanx_right_in[2] ) ,
.X ( chanx_left_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) ,
.X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) ,
.X ( chanx_left_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) ,
.X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) ,
.X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) ,
.X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) ,
.X ( chanx_left_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) ,
.X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) ,
.X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) ,
.X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) ,
.X ( chanx_left_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) ,
.X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) ,
.X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) ,
.X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) ,
.X ( chanx_left_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) ,
.X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) ,
.X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) ,
.X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_59__58 (
.A ( bottom_width_0_height_0__pin_1_lower[0] ) ,
.X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
.HI ( optlc_net_72 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
.HI ( optlc_net_73 ) ) ;
sky130_fd_sc_hd__buf_6 cts_buf_3521203 ( .A ( ctsbuf_net_174 ) ,
.X ( prog_clk_0_W_out ) ) ;
endmodule |
module sb_2__1_ ( chany_top_in , top_left_grid_pin_42_ ,
top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ ,
top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ ,
top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in ,
bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ ,
bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ ,
bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ ,
bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ ,
bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ ,
left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ ,
left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out ,
chanx_left_out , ccff_tail , prog_clk_0_N_in ) ;
input [0:19] chany_top_in ;
input [0:0] top_left_grid_pin_42_ ;
input [0:0] top_left_grid_pin_43_ ;
input [0:0] top_left_grid_pin_44_ ;
input [0:0] top_left_grid_pin_45_ ;
input [0:0] top_left_grid_pin_46_ ;
input [0:0] top_left_grid_pin_47_ ;
input [0:0] top_left_grid_pin_48_ ;
input [0:0] top_left_grid_pin_49_ ;
input [0:0] top_right_grid_pin_1_ ;
input [0:19] chany_bottom_in ;
input [0:0] bottom_right_grid_pin_1_ ;
input [0:0] bottom_left_grid_pin_42_ ;
input [0:0] bottom_left_grid_pin_43_ ;
input [0:0] bottom_left_grid_pin_44_ ;
input [0:0] bottom_left_grid_pin_45_ ;
input [0:0] bottom_left_grid_pin_46_ ;
input [0:0] bottom_left_grid_pin_47_ ;
input [0:0] bottom_left_grid_pin_48_ ;
input [0:0] bottom_left_grid_pin_49_ ;
input [0:19] chanx_left_in ;
input [0:0] left_bottom_grid_pin_34_ ;
input [0:0] left_bottom_grid_pin_35_ ;
input [0:0] left_bottom_grid_pin_36_ ;
input [0:0] left_bottom_grid_pin_37_ ;
input [0:0] left_bottom_grid_pin_38_ ;
input [0:0] left_bottom_grid_pin_39_ ;
input [0:0] left_bottom_grid_pin_40_ ;
input [0:0] left_bottom_grid_pin_41_ ;
input [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chany_bottom_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input prog_clk_0_N_in ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size14_0_sram ;
wire [0:3] mux_tree_tapbuf_size14_1_sram ;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
wire [0:2] mux_tree_tapbuf_size7_4_sram ;
wire [0:2] mux_tree_tapbuf_size7_5_sram ;
wire [0:2] mux_tree_tapbuf_size7_6_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size9_0_sram ;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
sb_2__1__mux_tree_tapbuf_size10_0 mux_top_track_0 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
top_right_grid_pin_1_[0] , chany_top_out[3] , chany_top_out[13] ,
chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( chany_top_out[0] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_1 (
.in ( { chany_bottom_out[3] , chany_bottom_out[13] ,
bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] ,
bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] ,
chanx_left_in[15] } ) ,
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( chany_bottom_out[0] ) , .p0 ( optlc_net_101 ) ) ;
sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_2 (
.in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] ,
top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
chany_top_out[5] , chany_top_out[14] , chanx_left_in[6] ,
chanx_left_in[13] } ) ,
.sram ( mux_tree_tapbuf_size8_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_8 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] ,
top_right_grid_pin_1_[0] , chany_top_out[7] , chany_top_out[17] ,
chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) ,
.sram ( mux_tree_tapbuf_size8_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( chany_top_out[4] ) , .p0 ( optlc_net_101 ) ) ;
sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_9 (
.in ( { chany_bottom_out[7] , chany_bottom_out[17] ,
bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] ,
bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] ,
chanx_left_in[18] } ) ,
.sram ( mux_tree_tapbuf_size8_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ;
sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size14_0 mux_top_track_4 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] ,
top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] ,
top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] ,
top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] ,
top_right_grid_pin_1_[0] , chany_top_out[6] , chany_top_out[15] ,
chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
.sram ( mux_tree_tapbuf_size14_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( chany_top_out[2] ) , .p0 ( optlc_net_101 ) ) ;
sb_2__1__mux_tree_tapbuf_size14 mux_bottom_track_5 (
.in ( { chany_bottom_out[6] , chany_bottom_out[15] ,
bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] ,
bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] ,
bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] ,
bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] ,
bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] ,
chanx_left_in[17] } ) ,
.sram ( mux_tree_tapbuf_size14_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ;
sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_top_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size14_mem mem_bottom_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_16 (
.in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] ,
chany_top_out[9] , chany_top_out[18] , chanx_left_in[3] ,
chanx_left_in[10] , chanx_left_in[17] } ) ,
.sram ( mux_tree_tapbuf_size7_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
SYNOPSYS_UNCONNECTED_31 } ) ,
.out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_24 (
.in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] ,
chany_top_out[10] , chany_top_out[19] , chanx_left_in[2] ,
chanx_left_in[9] , chanx_left_in[16] } ) ,
.sram ( mux_tree_tapbuf_size7_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 ,
SYNOPSYS_UNCONNECTED_34 } ) ,
.out ( chany_top_out[12] ) , .p0 ( optlc_net_101 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_2 mux_bottom_track_17 (
.in ( { chany_bottom_out[9] , chany_bottom_out[18] ,
bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] ,
chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) ,
.sram ( mux_tree_tapbuf_size7_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 ,
SYNOPSYS_UNCONNECTED_37 } ) ,
.out ( chany_bottom_out[8] ) , .p0 ( optlc_net_101 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_1 (
.in ( { chany_top_in[0] , chany_bottom_out[3] , chany_top_out[3] ,
left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] ,
left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size7_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 ,
SYNOPSYS_UNCONNECTED_40 } ) ,
.out ( chanx_left_out[0] ) , .p0 ( optlc_net_99 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_3 (
.in ( { chany_bottom_out[5] , chany_bottom_in[0] , chany_top_out[5] ,
chanx_left_out[13] , left_bottom_grid_pin_37_[0] ,
left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size7_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
SYNOPSYS_UNCONNECTED_43 } ) ,
.out ( chanx_left_out[1] ) , .p0 ( optlc_net_99 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_5 mux_left_track_5 (
.in ( { chany_bottom_out[6] , chany_bottom_in[1] , chany_top_out[6] ,
left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] ,
left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size7_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 ,
SYNOPSYS_UNCONNECTED_46 } ) ,
.out ( chanx_left_out[2] ) , .p0 ( optlc_net_99 ) ) ;
sb_2__1__mux_tree_tapbuf_size7 mux_left_track_7 (
.in ( { chany_bottom_out[7] , chany_bottom_in[3] , chany_top_out[7] ,
chanx_left_out[13] , left_bottom_grid_pin_37_[0] ,
left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size7_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 ,
SYNOPSYS_UNCONNECTED_49 } ) ,
.out ( chanx_left_out[3] ) , .p0 ( optlc_net_98 ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_left_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size7_mem mem_left_track_7 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size6_0 mux_top_track_32 (
.in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] ,
chany_top_out[11] , chanx_left_in[1] , chanx_left_in[8] ,
chanx_left_in[15] } ) ,
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 ,
SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( chany_top_out[16] ) , .p0 ( optlc_net_101 ) ) ;
sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_25 (
.in ( { chany_bottom_out[10] , chany_bottom_out[19] ,
bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] ,
chanx_left_in[6] , chanx_left_in[13] } ) ,
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
SYNOPSYS_UNCONNECTED_55 } ) ,
.out ( chany_bottom_out[12] ) , .p0 ( optlc_net_98 ) ) ;
sb_2__1__mux_tree_tapbuf_size6 mux_bottom_track_33 (
.in ( { chany_bottom_out[11] , bottom_left_grid_pin_44_[0] ,
bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] ,
chanx_left_in[14] } ) ,
.sram ( mux_tree_tapbuf_size6_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 ,
SYNOPSYS_UNCONNECTED_58 } ) ,
.out ( chany_bottom_out[16] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_32 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size6_mem mem_bottom_track_33 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 (
.in ( { chany_bottom_out[5] , chany_bottom_out[14] ,
bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] ,
bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] ,
chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) ,
.sram ( mux_tree_tapbuf_size9_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 ,
SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
.out ( chany_bottom_out[1] ) , .p0 ( optlc_net_101 ) ) ;
sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_9 (
.in ( { chany_bottom_out[9] , chany_bottom_in[7] , chany_top_out[9] ,
left_bottom_grid_pin_34_[0] } ) ,
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 ,
SYNOPSYS_UNCONNECTED_65 } ) ,
.out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ;
sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_11 (
.in ( { chany_bottom_out[10] , chany_top_out[10] , chany_bottom_in[11] ,
chanx_left_out[13] } ) ,
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 ,
SYNOPSYS_UNCONNECTED_68 } ) ,
.out ( chanx_left_out[5] ) , .p0 ( optlc_net_98 ) ) ;
sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 (
.in ( { chany_bottom_out[11] , chany_top_out[11] , chany_bottom_in[15] ,
left_bottom_grid_pin_36_[0] } ) ,
.sram ( mux_tree_tapbuf_size4_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
SYNOPSYS_UNCONNECTED_71 } ) ,
.out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ;
sb_2__1__mux_tree_tapbuf_size4 mux_left_track_15 (
.in ( { chany_bottom_out[13] , chany_top_out[13] , chany_bottom_in[19] ,
left_bottom_grid_pin_37_[0] } ) ,
.sram ( mux_tree_tapbuf_size4_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 ,
SYNOPSYS_UNCONNECTED_74 } ) ,
.out ( chanx_left_out[7] ) , .p0 ( optlc_net_99 ) ) ;
sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_11 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_15 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 (
.in ( { chany_bottom_out[14] , chany_top_out[14] ,
left_bottom_grid_pin_38_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
.out ( chanx_left_out[8] ) , .p0 ( optlc_net_99 ) ) ;
sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 (
.in ( { chany_bottom_out[15] , chany_top_out[15] ,
left_bottom_grid_pin_39_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
.out ( chanx_left_out[9] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 (
.in ( { chany_bottom_out[17] , chany_top_out[17] ,
left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
.out ( chanx_left_out[10] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 (
.in ( { chany_bottom_out[18] , chany_top_out[18] ,
left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
.out ( chanx_left_out[11] ) , .p0 ( optlc_net_99 ) ) ;
sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 (
.in ( { chany_bottom_out[19] , chany_top_out[19] ,
left_bottom_grid_pin_34_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
.out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 (
.in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
.out ( chanx_left_out[14] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 (
.in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
.out ( chanx_left_out[15] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 (
.in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
.out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 (
.in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
.out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 (
.in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
.out ( chanx_left_out[18] ) , .p0 ( optlc_net_100 ) ) ;
sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 (
.in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
.out ( chanx_left_out[19] ) , .p0 ( optlc_net_98 ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) ,
.X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) ,
.X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) ,
.X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) ,
.X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) ,
.X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) ,
.X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) ,
.X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) ,
.X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) ,
.X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) ,
.X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) ,
.X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) ,
.X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) ,
.X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[2] ) ,
.X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[4] ) ,
.X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[5] ) ,
.X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[6] ) ,
.X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[8] ) ,
.X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[9] ) ,
.X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[10] ) ,
.X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[12] ) ,
.X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[13] ) ,
.X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[14] ) ,
.X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[16] ) ,
.X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[17] ) ,
.X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[18] ) ,
.X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( left_bottom_grid_pin_35_[0] ) ,
.X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_97 ) ,
.HI ( optlc_net_98 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_98 ) ,
.HI ( optlc_net_99 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_99 ) ,
.HI ( optlc_net_100 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_100 ) ,
.HI ( optlc_net_101 ) ) ;
endmodule |
module sb_2__2_ ( chany_bottom_in , bottom_right_grid_pin_1_ ,
bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ ,
bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ ,
bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ ,
bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in ,
left_top_grid_pin_1_ , left_bottom_grid_pin_34_ ,
left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ ,
left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out ,
ccff_tail , SC_IN_BOT , SC_OUT_BOT , prog_clk_0_S_in ) ;
input [0:19] chany_bottom_in ;
input [0:0] bottom_right_grid_pin_1_ ;
input [0:0] bottom_left_grid_pin_42_ ;
input [0:0] bottom_left_grid_pin_43_ ;
input [0:0] bottom_left_grid_pin_44_ ;
input [0:0] bottom_left_grid_pin_45_ ;
input [0:0] bottom_left_grid_pin_46_ ;
input [0:0] bottom_left_grid_pin_47_ ;
input [0:0] bottom_left_grid_pin_48_ ;
input [0:0] bottom_left_grid_pin_49_ ;
input [0:19] chanx_left_in ;
input [0:0] left_top_grid_pin_1_ ;
input [0:0] left_bottom_grid_pin_34_ ;
input [0:0] left_bottom_grid_pin_35_ ;
input [0:0] left_bottom_grid_pin_36_ ;
input [0:0] left_bottom_grid_pin_37_ ;
input [0:0] left_bottom_grid_pin_38_ ;
input [0:0] left_bottom_grid_pin_39_ ;
input [0:0] left_bottom_grid_pin_40_ ;
input [0:0] left_bottom_grid_pin_41_ ;
input [0:0] ccff_head ;
output [0:19] chany_bottom_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input SC_IN_BOT ;
output SC_OUT_BOT ;
input prog_clk_0_S_in ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
wire [0:1] mux_tree_tapbuf_size2_18_sram ;
wire [0:1] mux_tree_tapbuf_size2_19_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_20_sram ;
wire [0:1] mux_tree_tapbuf_size2_21_sram ;
wire [0:1] mux_tree_tapbuf_size2_22_sram ;
wire [0:1] mux_tree_tapbuf_size2_23_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:2] mux_tree_tapbuf_size5_2_sram ;
wire [0:2] mux_tree_tapbuf_size5_3_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
wire [0:2] mux_tree_tapbuf_size6_3_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
.in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] ,
bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) ,
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 } ) ,
.out ( chany_bottom_out[0] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 (
.in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] ,
bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) ,
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
SYNOPSYS_UNCONNECTED_6 } ) ,
.out ( chany_bottom_out[2] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 (
.in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] ,
left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] ,
left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
SYNOPSYS_UNCONNECTED_9 } ) ,
.out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 (
.in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] ,
left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] ,
left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 (
.in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] ,
bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] ,
chanx_left_in[2] } ) ,
.sram ( mux_tree_tapbuf_size5_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 } ) ,
.out ( chany_bottom_out[1] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 (
.in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] ,
bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] ,
chanx_left_in[4] } ) ,
.sram ( mux_tree_tapbuf_size5_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
SYNOPSYS_UNCONNECTED_18 } ) ,
.out ( chany_bottom_out[3] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 (
.in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] ,
left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] ,
left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size5_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
SYNOPSYS_UNCONNECTED_21 } ) ,
.out ( chanx_left_out[1] ) , .p0 ( optlc_net_87 ) ) ;
sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 (
.in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] ,
left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] ,
left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size5_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( chanx_left_out[3] ) , .p0 ( optlc_net_87 ) ) ;
sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_9 (
.in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) ,
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
.out ( chany_bottom_out[4] ) , .p0 ( optlc_net_87 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_11 (
.in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) ,
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( chany_bottom_out[5] ) , .p0 ( optlc_net_87 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_13 (
.in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
.out ( chany_bottom_out[6] ) , .p0 ( optlc_net_87 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_15 (
.in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( chany_bottom_out[7] ) , .p0 ( optlc_net_87 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_17 (
.in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
.out ( chany_bottom_out[8] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_19 (
.in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( chany_bottom_out[9] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_21 (
.in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
.out ( chany_bottom_out[10] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_23 (
.in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
.out ( chany_bottom_out[11] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_27 (
.in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) ,
.sram ( mux_tree_tapbuf_size2_8_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
.out ( chany_bottom_out[13] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_29 (
.in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
.sram ( mux_tree_tapbuf_size2_9_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
.out ( chany_bottom_out[14] ) , .p0 ( optlc_net_87 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 (
.in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_10_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
.out ( chanx_left_out[5] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 (
.in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_11_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
.out ( chanx_left_out[6] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 (
.in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_12_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
.out ( chanx_left_out[7] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 (
.in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_13_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( chanx_left_out[8] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 (
.in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_14_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
.out ( chanx_left_out[9] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 (
.in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_15_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
.out ( chanx_left_out[10] ) , .p0 ( optlc_net_87 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 (
.in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_16_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
.out ( chanx_left_out[11] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 (
.in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_17_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
.out ( chanx_left_out[13] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 (
.in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_18_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
.out ( chanx_left_out[14] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 (
.in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_19_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
.out ( chanx_left_out[15] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 (
.in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_20_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
.out ( chanx_left_out[16] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 (
.in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_21_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
.out ( chanx_left_out[17] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 (
.in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_22_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
.out ( chanx_left_out[18] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 (
.in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_23_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
.out ( chanx_left_out[19] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_11 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_13 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_15 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_19 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_21 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_23 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_27 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_29 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 (
.in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] ,
chanx_left_in[13] } ) ,
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
.out ( chany_bottom_out[12] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_9 (
.in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] ,
left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
.out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__2__mux_tree_tapbuf_size3 mux_left_track_25 (
.in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] ,
left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
.out ( chanx_left_out[12] ) , .p0 ( optlc_net_88 ) ) ;
sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[0] ) ,
.X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[16] ) ,
.X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[17] ) ,
.X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[18] ) ,
.X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[19] ) ,
.X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) ,
.HI ( optlc_net_87 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) ,
.HI ( optlc_net_88 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) ,
.HI ( optlc_net_89 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_82 ) ,
.HI ( optlc_net_90 ) ) ;
endmodule |
module sb_0__0_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in ,
right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ ,
right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ ,
right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ ,
right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ ,
right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
ccff_tail , prog_clk_0_E_in ) ;
input [0:19] chany_top_in ;
input [0:0] top_left_grid_pin_1_ ;
input [0:19] chanx_right_in ;
input [0:0] right_bottom_grid_pin_1_ ;
input [0:0] right_bottom_grid_pin_3_ ;
input [0:0] right_bottom_grid_pin_5_ ;
input [0:0] right_bottom_grid_pin_7_ ;
input [0:0] right_bottom_grid_pin_9_ ;
input [0:0] right_bottom_grid_pin_11_ ;
input [0:0] right_bottom_grid_pin_13_ ;
input [0:0] right_bottom_grid_pin_15_ ;
input [0:0] right_bottom_grid_pin_17_ ;
input [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_right_out ;
output [0:0] ccff_tail ;
input prog_clk_0_E_in ;
wire ropt_net_107 ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 (
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
.out ( chany_top_out[0] ) , .p0 ( optlc_net_79 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_4 (
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) ,
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( chany_top_out[2] ) , .p0 ( optlc_net_79 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_8 (
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) ,
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
.out ( chany_top_out[4] ) , .p0 ( optlc_net_79 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_24 (
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) ,
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( chany_top_out[12] ) , .p0 ( optlc_net_80 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_10 (
.in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
.out ( chanx_right_out[5] ) , .p0 ( optlc_net_77 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_12 (
.in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( chanx_right_out[6] ) , .p0 ( optlc_net_80 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_14 (
.in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
.out ( chanx_right_out[7] ) , .p0 ( optlc_net_80 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_16 (
.in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( chanx_right_out[8] ) , .p0 ( optlc_net_77 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_18 (
.in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_8_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
.out ( chanx_right_out[9] ) , .p0 ( optlc_net_77 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_20 (
.in ( { chany_top_in[9] , right_bottom_grid_pin_13_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_9_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( chanx_right_out[10] ) , .p0 ( optlc_net_77 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_22 (
.in ( { chany_top_in[10] , right_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_10_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
.out ( chanx_right_out[11] ) , .p0 ( optlc_net_78 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 (
.in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_11_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_28 (
.in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_12_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
.out ( chanx_right_out[14] ) , .p0 ( optlc_net_80 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_30 (
.in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_13_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( chanx_right_out[15] ) , .p0 ( optlc_net_80 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_32 (
.in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_14_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
.out ( chanx_right_out[16] ) , .p0 ( optlc_net_77 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_34 (
.in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_15_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( chanx_right_out[17] ) , .p0 ( optlc_net_77 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_36 (
.in ( { chany_top_in[17] , right_bottom_grid_pin_13_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_16_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
.out ( chanx_right_out[18] ) , .p0 ( optlc_net_78 ) ) ;
sb_0__0__mux_tree_tapbuf_size2 mux_right_track_38 (
.in ( { chany_top_in[18] , right_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_17_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( chanx_right_out[19] ) , .p0 ( optlc_net_78 ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_38 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size6_0 mux_right_track_0 (
.in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] ,
right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] ,
right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
SYNOPSYS_UNCONNECTED_39 } ) ,
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_79 ) ) ;
sb_0__0__mux_tree_tapbuf_size6 mux_right_track_4 (
.in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] ,
right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] ,
right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
SYNOPSYS_UNCONNECTED_42 } ) ,
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_78 ) ) ;
sb_0__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size6_mem mem_right_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size5_0 mux_right_track_2 (
.in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] ,
right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] ,
right_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size5_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
SYNOPSYS_UNCONNECTED_45 } ) ,
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_78 ) ) ;
sb_0__0__mux_tree_tapbuf_size5 mux_right_track_6 (
.in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] ,
right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] ,
right_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size5_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 ,
SYNOPSYS_UNCONNECTED_48 } ) ,
.out ( chanx_right_out[3] ) , .p0 ( optlc_net_78 ) ) ;
sb_0__0__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size5_mem mem_right_track_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_8 (
.in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] ,
right_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
.out ( chanx_right_out[4] ) , .p0 ( optlc_net_78 ) ) ;
sb_0__0__mux_tree_tapbuf_size3 mux_right_track_24 (
.in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] ,
right_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( chanx_right_out[12] ) , .p0 ( optlc_net_78 ) ) ;
sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chanx_right_in[0] ) ,
.X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_right_in[2] ) ,
.X ( chany_top_out[1] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_27__26 ( .A ( chanx_right_in[4] ) ,
.X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_right_in[6] ) ,
.X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[7] ) ,
.X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[8] ) ,
.X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[9] ) ,
.X ( chany_top_out[8] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chanx_right_in[10] ) ,
.X ( ropt_net_107 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( chanx_right_in[11] ) ,
.X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[12] ) ,
.X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[14] ) ,
.X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[15] ) ,
.X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[16] ) ,
.X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[17] ) ,
.X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[18] ) ,
.X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[19] ) ,
.X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_53 ) ,
.HI ( optlc_net_77 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_54 ) ,
.HI ( optlc_net_78 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_55 ) ,
.HI ( optlc_net_79 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( SYNOPSYS_UNCONNECTED_56 ) ,
.HI ( optlc_net_80 ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_107 ) ,
.X ( chany_top_out[9] ) ) ;
endmodule |
module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head ,
chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail ,
IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper ,
right_width_0_height_0__pin_1_lower , prog_clk_0_E_in ) ;
input [0:19] chany_bottom_in ;
input [0:19] chany_top_in ;
input [0:0] ccff_head ;
output [0:19] chany_bottom_out ;
output [0:19] chany_top_out ;
output [0:0] left_grid_pin_0_ ;
output [0:0] ccff_tail ;
input [0:0] IO_ISOL_N ;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
input [0:0] right_width_0_height_0__pin_0_ ;
output [0:0] right_width_0_height_0__pin_1_upper ;
output [0:0] right_width_0_height_0__pin_1_lower ;
input prog_clk_0_E_in ;
wire ropt_net_67 ;
wire ropt_net_68 ;
wire ropt_net_66 ;
wire ropt_net_65 ;
wire ropt_net_63 ;
wire ropt_net_69 ;
wire ropt_net_64 ;
wire ropt_net_62 ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
assign prog_clk_0 = prog_clk[0] ;
cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] ,
chany_bottom_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( left_grid_pin_0_ ) , .p0 ( optlc_net_48 ) ) ;
cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( { ccff_tail_mid } ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
.io_outpad ( right_width_0_height_0__pin_0_ ) ,
.ccff_head ( { ccff_tail_mid } ) ,
.io_inpad ( right_width_0_height_0__pin_1_lower ) ,
.ccff_tail ( ccff_tail ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) ,
.X ( chany_top_out[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) ,
.X ( chany_top_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) ,
.X ( chany_top_out[2] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) ,
.X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) ,
.X ( chany_top_out[4] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) ,
.X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_9__8 ( .A ( chany_bottom_in[6] ) ,
.X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) ,
.X ( ropt_net_67 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) ,
.X ( ropt_net_68 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) ,
.X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) ,
.X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) ,
.X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) ,
.X ( ropt_net_66 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) ,
.X ( ropt_net_65 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) ,
.X ( ropt_net_63 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) ,
.X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) ,
.X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) ,
.X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_21__20 ( .A ( chany_bottom_in[18] ) ,
.X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) ,
.X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) ,
.X ( chany_bottom_out[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) ,
.X ( chany_bottom_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) ,
.X ( chany_bottom_out[2] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) ,
.X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) ,
.X ( chany_bottom_out[4] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) ,
.X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) ,
.X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) ,
.X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) ,
.X ( chany_bottom_out[8] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) ,
.X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) ,
.X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) ,
.X ( ropt_net_69 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[12] ) ,
.X ( ropt_net_64 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chany_top_in[13] ) ,
.X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) ,
.X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) ,
.X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) ,
.X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) ,
.X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) ,
.X ( ropt_net_62 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) ,
.X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_43__42 (
.A ( right_width_0_height_0__pin_1_lower[0] ) ,
.X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
.HI ( optlc_net_48 ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1194 ( .A ( ropt_net_62 ) ,
.X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1195 ( .A ( ropt_net_63 ) ,
.X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1196 ( .A ( ropt_net_64 ) ,
.X ( chany_bottom_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1197 ( .A ( ropt_net_65 ) ,
.X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1198 ( .A ( ropt_net_66 ) ,
.X ( chany_top_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1199 ( .A ( ropt_net_67 ) ,
.X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1200 ( .A ( ropt_net_68 ) ,
.X ( chany_top_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1201 ( .A ( ropt_net_69 ) ,
.X ( chany_bottom_out[11] ) ) ;
endmodule |
module cbx_1__0_ ( chanx_left_in , chanx_right_in , ccff_head ,
chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ ,
bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ ,
bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N ,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ ,
top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ ,
top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ ,
top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ ,
top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ ,
top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower ,
top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower ,
top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower ,
top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower ,
top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower ,
top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower ,
top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower ,
top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower ,
top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower ,
SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , prog_clk_0_N_in ,
prog_clk_0_W_out ) ;
input [0:19] chanx_left_in ;
input [0:19] chanx_right_in ;
input [0:0] ccff_head ;
output [0:19] chanx_left_out ;
output [0:19] chanx_right_out ;
output [0:0] bottom_grid_pin_0_ ;
output [0:0] bottom_grid_pin_2_ ;
output [0:0] bottom_grid_pin_4_ ;
output [0:0] bottom_grid_pin_6_ ;
output [0:0] bottom_grid_pin_8_ ;
output [0:0] bottom_grid_pin_10_ ;
output [0:0] bottom_grid_pin_12_ ;
output [0:0] bottom_grid_pin_14_ ;
output [0:0] bottom_grid_pin_16_ ;
output [0:0] ccff_tail ;
input [0:0] IO_ISOL_N ;
input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
input [0:0] top_width_0_height_0__pin_0_ ;
input [0:0] top_width_0_height_0__pin_2_ ;
input [0:0] top_width_0_height_0__pin_4_ ;
input [0:0] top_width_0_height_0__pin_6_ ;
input [0:0] top_width_0_height_0__pin_8_ ;
input [0:0] top_width_0_height_0__pin_10_ ;
input [0:0] top_width_0_height_0__pin_12_ ;
input [0:0] top_width_0_height_0__pin_14_ ;
input [0:0] top_width_0_height_0__pin_16_ ;
output [0:0] top_width_0_height_0__pin_1_upper ;
output [0:0] top_width_0_height_0__pin_1_lower ;
output [0:0] top_width_0_height_0__pin_3_upper ;
output [0:0] top_width_0_height_0__pin_3_lower ;
output [0:0] top_width_0_height_0__pin_5_upper ;
output [0:0] top_width_0_height_0__pin_5_lower ;
output [0:0] top_width_0_height_0__pin_7_upper ;
output [0:0] top_width_0_height_0__pin_7_lower ;
output [0:0] top_width_0_height_0__pin_9_upper ;
output [0:0] top_width_0_height_0__pin_9_lower ;
output [0:0] top_width_0_height_0__pin_11_upper ;
output [0:0] top_width_0_height_0__pin_11_lower ;
output [0:0] top_width_0_height_0__pin_13_upper ;
output [0:0] top_width_0_height_0__pin_13_lower ;
output [0:0] top_width_0_height_0__pin_15_upper ;
output [0:0] top_width_0_height_0__pin_15_lower ;
output [0:0] top_width_0_height_0__pin_17_upper ;
output [0:0] top_width_0_height_0__pin_17_lower ;
input SC_IN_TOP ;
output SC_OUT_BOT ;
input SC_IN_BOT ;
output SC_OUT_TOP ;
input prog_clk_0_N_in ;
output prog_clk_0_W_out ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:3] mux_tree_tapbuf_size10_8_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
chanx_left_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_112 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] ,
chanx_left_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_112 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
chanx_left_out[18] } ) ,
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_113 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
chanx_left_out[19] } ) ,
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_114 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] ,
chanx_left_out[14] } ) ,
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_114 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] ,
chanx_left_out[15] } ) ,
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_114 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
chanx_left_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_112 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] ,
chanx_left_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_112 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] ,
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
chanx_left_out[18] } ) ,
.sram ( mux_tree_tapbuf_size10_8_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_113 ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
.ccff_tail ( { ccff_tail_mid } ) ,
.mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
.io_outpad ( top_width_0_height_0__pin_0_ ) ,
.ccff_head ( { ccff_tail_mid } ) ,
.io_inpad ( top_width_0_height_0__pin_1_lower ) ,
.ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) ,
.io_outpad ( top_width_0_height_0__pin_2_ ) ,
.ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) ,
.io_inpad ( top_width_0_height_0__pin_3_lower ) ,
.ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_511_ } ) ,
.io_outpad ( top_width_0_height_0__pin_4_ ) ,
.ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) ,
.io_inpad ( top_width_0_height_0__pin_5_lower ) ,
.ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ,
.ZBUF_211_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) ,
.io_outpad ( top_width_0_height_0__pin_6_ ) ,
.ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) ,
.io_inpad ( top_width_0_height_0__pin_7_lower ) ,
.ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ,
.io_outpad ( top_width_0_height_0__pin_8_ ) ,
.ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) ,
.io_inpad ( top_width_0_height_0__pin_9_lower ) ,
.ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ;
cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ,
.io_outpad ( top_width_0_height_0__pin_10_ ) ,
.ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) ,
.io_inpad ( top_width_0_height_0__pin_11_lower ) ,
.ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ) ;
cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) ,
.io_outpad ( top_width_0_height_0__pin_12_ ) ,
.ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) ,
.io_inpad ( top_width_0_height_0__pin_13_lower ) ,
.ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ,
.io_outpad ( top_width_0_height_0__pin_14_ ) ,
.ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) ,
.io_inpad ( top_width_0_height_0__pin_15_lower ) ,
.ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ) ;
cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ,
.io_outpad ( top_width_0_height_0__pin_16_ ) ,
.ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) ,
.io_inpad ( top_width_0_height_0__pin_17_lower ) ,
.ccff_tail ( ccff_tail ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
.X ( ctsbuf_net_1115 ) ) ;
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
.X ( chanx_right_out[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
.X ( chanx_right_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
.X ( chanx_right_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
.X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
.X ( chanx_right_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
.X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
.X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
.X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
.X ( chanx_right_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
.X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
.X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
.X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
.X ( chanx_right_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
.X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
.X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
.X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
.X ( chanx_right_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
.X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
.X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
.X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) ,
.X ( chanx_left_out[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) ,
.X ( chanx_left_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) ,
.X ( chanx_left_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) ,
.X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) ,
.X ( chanx_left_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) ,
.X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) ,
.X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) ,
.X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) ,
.X ( chanx_left_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) ,
.X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) ,
.X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) ,
.X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) ,
.X ( chanx_left_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) ,
.X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) ,
.X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) ,
.X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) ,
.X ( chanx_left_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) ,
.X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) ,
.X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) ,
.X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_59__58 (
.A ( top_width_0_height_0__pin_1_lower[0] ) ,
.X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_60__59 (
.A ( top_width_0_height_0__pin_3_lower[0] ) ,
.X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_61__60 (
.A ( top_width_0_height_0__pin_5_lower[0] ) ,
.X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_62__61 (
.A ( top_width_0_height_0__pin_7_lower[0] ) ,
.X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_63__62 (
.A ( top_width_0_height_0__pin_9_lower[0] ) ,
.X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_64__63 (
.A ( top_width_0_height_0__pin_11_lower[0] ) ,
.X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_65__64 (
.A ( top_width_0_height_0__pin_13_lower[0] ) ,
.X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_66__65 (
.A ( top_width_0_height_0__pin_15_lower[0] ) ,
.X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_67__66 (
.A ( top_width_0_height_0__pin_17_lower[0] ) ,
.X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) ,
.HI ( optlc_net_112 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) ,
.HI ( optlc_net_113 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) ,
.HI ( optlc_net_114 ) ) ;
sky130_fd_sc_hd__buf_6 ZBUF_211_inst_119 ( .A ( aps_rename_511_ ) ,
.X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
sky130_fd_sc_hd__clkbuf_8 cts_buf_3521246 ( .A ( ctsbuf_net_1115 ) ,
.X ( prog_clk_0_W_out ) ) ;
endmodule |
module sb_2__0_ ( chany_top_in , top_left_grid_pin_42_ ,
top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ ,
top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ ,
top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in ,
left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out ,
ccff_tail , prog_clk_0_N_in ) ;
input [0:19] chany_top_in ;
input [0:0] top_left_grid_pin_42_ ;
input [0:0] top_left_grid_pin_43_ ;
input [0:0] top_left_grid_pin_44_ ;
input [0:0] top_left_grid_pin_45_ ;
input [0:0] top_left_grid_pin_46_ ;
input [0:0] top_left_grid_pin_47_ ;
input [0:0] top_left_grid_pin_48_ ;
input [0:0] top_left_grid_pin_49_ ;
input [0:0] top_right_grid_pin_1_ ;
input [0:19] chanx_left_in ;
input [0:0] left_bottom_grid_pin_1_ ;
input [0:0] left_bottom_grid_pin_3_ ;
input [0:0] left_bottom_grid_pin_5_ ;
input [0:0] left_bottom_grid_pin_7_ ;
input [0:0] left_bottom_grid_pin_9_ ;
input [0:0] left_bottom_grid_pin_11_ ;
input [0:0] left_bottom_grid_pin_13_ ;
input [0:0] left_bottom_grid_pin_15_ ;
input [0:0] left_bottom_grid_pin_17_ ;
input [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input prog_clk_0_N_in ;
wire ropt_net_110 ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
wire [0:1] mux_tree_tapbuf_size2_18_sram ;
wire [0:1] mux_tree_tapbuf_size2_19_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_20_sram ;
wire [0:1] mux_tree_tapbuf_size2_21_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:2] mux_tree_tapbuf_size5_2_sram ;
wire [0:2] mux_tree_tapbuf_size5_3_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
wire [0:2] mux_tree_tapbuf_size6_3_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
top_right_grid_pin_1_[0] , chanx_left_in[0] } ) ,
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 } ) ,
.out ( chany_top_out[0] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size6_1 mux_top_track_4 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
top_right_grid_pin_1_[0] , chanx_left_in[18] } ) ,
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
SYNOPSYS_UNCONNECTED_6 } ) ,
.out ( chany_top_out[2] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size6_2 mux_left_track_1 (
.in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] ,
left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] ,
left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
SYNOPSYS_UNCONNECTED_9 } ) ,
.out ( chanx_left_out[0] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__0__mux_tree_tapbuf_size6 mux_left_track_5 (
.in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] ,
left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] ,
left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( chanx_left_out[2] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 (
.in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] ,
top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
chanx_left_in[19] } ) ,
.sram ( mux_tree_tapbuf_size5_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 } ) ,
.out ( chany_top_out[1] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size5_1 mux_top_track_6 (
.in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] ,
top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
chanx_left_in[17] } ) ,
.sram ( mux_tree_tapbuf_size5_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
SYNOPSYS_UNCONNECTED_18 } ) ,
.out ( chany_top_out[3] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size5_2 mux_left_track_3 (
.in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] ,
left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] ,
left_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size5_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
SYNOPSYS_UNCONNECTED_21 } ) ,
.out ( chanx_left_out[1] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__0__mux_tree_tapbuf_size5 mux_left_track_7 (
.in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] ,
left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] ,
left_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size5_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( chanx_left_out[3] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_8 (
.in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] ,
chanx_left_in[16] } ) ,
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
.out ( chany_top_out[4] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_24 (
.in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] ,
chanx_left_in[8] } ) ,
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( chany_top_out[12] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_9 (
.in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] ,
left_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
.out ( chanx_left_out[4] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__0__mux_tree_tapbuf_size3 mux_left_track_25 (
.in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] ,
left_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size3_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( chanx_left_out[12] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_10 (
.in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) ,
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
.out ( chany_top_out[5] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_12 (
.in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) ,
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( chany_top_out[6] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_14 (
.in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) ,
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
.out ( chany_top_out[7] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_16 (
.in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) ,
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
.out ( chany_top_out[8] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_18 (
.in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
.out ( chany_top_out[9] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_20 (
.in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) ,
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
.out ( chany_top_out[10] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_22 (
.in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) ,
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
.out ( chany_top_out[11] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_26 (
.in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) ,
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
.out ( chany_top_out[13] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_11 (
.in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_8_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
.out ( chanx_left_out[5] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_13 (
.in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_9_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( chanx_left_out[6] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_15 (
.in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_10_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
.out ( chanx_left_out[7] ) , .p0 ( optlc_net_92 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_17 (
.in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_11_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
.out ( chanx_left_out[8] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_12 mux_left_track_19 (
.in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_12_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
.out ( chanx_left_out[9] ) , .p0 ( optlc_net_92 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_13 mux_left_track_21 (
.in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_13_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
.out ( chanx_left_out[10] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_14 mux_left_track_23 (
.in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_14_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
.out ( chanx_left_out[11] ) , .p0 ( optlc_net_89 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_27 (
.in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_15_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
.out ( chanx_left_out[13] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_29 (
.in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_16_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
.out ( chanx_left_out[14] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_31 (
.in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_17_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
.out ( chanx_left_out[15] ) , .p0 ( optlc_net_92 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_33 (
.in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_18_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
.out ( chanx_left_out[16] ) , .p0 ( optlc_net_93 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_35 (
.in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_19_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
.out ( chanx_left_out[17] ) , .p0 ( optlc_net_93 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_37 (
.in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_20_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
.out ( chanx_left_out[18] ) , .p0 ( optlc_net_91 ) ) ;
sb_2__0__mux_tree_tapbuf_size2 mux_left_track_39 (
.in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_21_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
.out ( chanx_left_out[19] ) , .p0 ( optlc_net_90 ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_10 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_12 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_14 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_18 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_20 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_22 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_26 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_11 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_13 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_15 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_left_track_19 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_left_track_21 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_left_track_23 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_27 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_29 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_31 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_33 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_35 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_37 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_39 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[1] ) ,
.X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_left_in[2] ) ,
.X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_left_in[3] ) ,
.X ( ropt_net_110 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chanx_left_in[4] ) ,
.X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_left_in[5] ) ,
.X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[6] ) ,
.X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) ,
.HI ( optlc_net_89 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) ,
.HI ( optlc_net_90 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) ,
.HI ( optlc_net_91 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) ,
.HI ( optlc_net_92 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) ,
.HI ( optlc_net_93 ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_110 ) ,
.X ( chany_top_out[17] ) ) ;
endmodule |
module sb_1__1_ ( chany_top_in , top_left_grid_pin_42_ ,
top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ ,
top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ ,
top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ ,
right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ ,
right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ ,
right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ ,
right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ ,
bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ ,
bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ ,
bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ ,
bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ ,
left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ ,
left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out ,
chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in ,
Test_en_N_out , prog_clk_0_N_in , prog_clk_1_N_in , prog_clk_1_S_in ,
prog_clk_1_E_out , prog_clk_1_W_out , prog_clk_2_N_in , prog_clk_2_E_in ,
prog_clk_2_S_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_S_out ,
prog_clk_2_N_out , prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in ,
prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out ,
prog_clk_3_N_out , prog_clk_3_S_out , clk_1_N_in , clk_1_S_in ,
clk_1_E_out , clk_1_W_out , clk_2_N_in , clk_2_E_in , clk_2_S_in ,
clk_2_W_in , clk_2_W_out , clk_2_S_out , clk_2_N_out , clk_2_E_out ,
clk_3_W_in , clk_3_E_in , clk_3_S_in , clk_3_N_in , clk_3_E_out ,
clk_3_W_out , clk_3_N_out , clk_3_S_out ) ;
input [0:19] chany_top_in ;
input [0:0] top_left_grid_pin_42_ ;
input [0:0] top_left_grid_pin_43_ ;
input [0:0] top_left_grid_pin_44_ ;
input [0:0] top_left_grid_pin_45_ ;
input [0:0] top_left_grid_pin_46_ ;
input [0:0] top_left_grid_pin_47_ ;
input [0:0] top_left_grid_pin_48_ ;
input [0:0] top_left_grid_pin_49_ ;
input [0:19] chanx_right_in ;
input [0:0] right_bottom_grid_pin_34_ ;
input [0:0] right_bottom_grid_pin_35_ ;
input [0:0] right_bottom_grid_pin_36_ ;
input [0:0] right_bottom_grid_pin_37_ ;
input [0:0] right_bottom_grid_pin_38_ ;
input [0:0] right_bottom_grid_pin_39_ ;
input [0:0] right_bottom_grid_pin_40_ ;
input [0:0] right_bottom_grid_pin_41_ ;
input [0:19] chany_bottom_in ;
input [0:0] bottom_left_grid_pin_42_ ;
input [0:0] bottom_left_grid_pin_43_ ;
input [0:0] bottom_left_grid_pin_44_ ;
input [0:0] bottom_left_grid_pin_45_ ;
input [0:0] bottom_left_grid_pin_46_ ;
input [0:0] bottom_left_grid_pin_47_ ;
input [0:0] bottom_left_grid_pin_48_ ;
input [0:0] bottom_left_grid_pin_49_ ;
input [0:19] chanx_left_in ;
input [0:0] left_bottom_grid_pin_34_ ;
input [0:0] left_bottom_grid_pin_35_ ;
input [0:0] left_bottom_grid_pin_36_ ;
input [0:0] left_bottom_grid_pin_37_ ;
input [0:0] left_bottom_grid_pin_38_ ;
input [0:0] left_bottom_grid_pin_39_ ;
input [0:0] left_bottom_grid_pin_40_ ;
input [0:0] left_bottom_grid_pin_41_ ;
input [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_right_out ;
output [0:19] chany_bottom_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input Test_en_S_in ;
output Test_en_N_out ;
input prog_clk_0_N_in ;
input prog_clk_1_N_in ;
input prog_clk_1_S_in ;
output prog_clk_1_E_out ;
output prog_clk_1_W_out ;
input prog_clk_2_N_in ;
input prog_clk_2_E_in ;
input prog_clk_2_S_in ;
input prog_clk_2_W_in ;
output prog_clk_2_W_out ;
output prog_clk_2_S_out ;
output prog_clk_2_N_out ;
output prog_clk_2_E_out ;
input prog_clk_3_W_in ;
input prog_clk_3_E_in ;
input prog_clk_3_S_in ;
input prog_clk_3_N_in ;
output prog_clk_3_E_out ;
output prog_clk_3_W_out ;
output prog_clk_3_N_out ;
output prog_clk_3_S_out ;
input clk_1_N_in ;
input clk_1_S_in ;
output clk_1_E_out ;
output clk_1_W_out ;
input clk_2_N_in ;
input clk_2_E_in ;
input clk_2_S_in ;
input clk_2_W_in ;
output clk_2_W_out ;
output clk_2_S_out ;
output clk_2_N_out ;
output clk_2_E_out ;
input clk_3_W_in ;
input clk_3_E_in ;
input clk_3_S_in ;
input clk_3_N_in ;
output clk_3_E_out ;
output clk_3_W_out ;
output clk_3_N_out ;
output clk_3_S_out ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_10_sram ;
wire [0:3] mux_tree_tapbuf_size10_11_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:3] mux_tree_tapbuf_size10_8_sram ;
wire [0:3] mux_tree_tapbuf_size10_9_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
wire [0:3] mux_tree_tapbuf_size12_1_sram ;
wire [0:3] mux_tree_tapbuf_size12_2_sram ;
wire [0:3] mux_tree_tapbuf_size12_3_sram ;
wire [0:3] mux_tree_tapbuf_size12_4_sram ;
wire [0:3] mux_tree_tapbuf_size12_5_sram ;
wire [0:3] mux_tree_tapbuf_size12_6_sram ;
wire [0:3] mux_tree_tapbuf_size12_7_sram ;
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
wire [0:4] mux_tree_tapbuf_size16_0_sram ;
wire [0:4] mux_tree_tapbuf_size16_1_sram ;
wire [0:4] mux_tree_tapbuf_size16_2_sram ;
wire [0:4] mux_tree_tapbuf_size16_3_sram ;
wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
assign prog_clk_1_E_out = prog_clk_1_S_in ;
assign prog_clk_1_W_out = prog_clk_1_S_in ;
assign prog_clk_2_W_out = prog_clk_2_W_in ;
assign prog_clk_2_S_out = prog_clk_2_W_in ;
assign prog_clk_2_N_out = prog_clk_2_W_in ;
assign prog_clk_2_E_out = prog_clk_2_W_in ;
assign prog_clk_3_E_out = prog_clk_3_N_in ;
assign prog_clk_3_W_out = prog_clk_3_N_in ;
assign prog_clk_3_N_out = prog_clk_3_N_in ;
assign prog_clk_3_S_out = prog_clk_3_N_in ;
assign clk_1_E_out = clk_1_S_in ;
assign clk_1_W_out = clk_1_S_in ;
assign clk_2_W_out = clk_2_W_in ;
assign clk_2_S_out = clk_2_W_in ;
assign clk_2_N_out = clk_2_W_in ;
assign clk_2_E_out = clk_2_W_in ;
assign clk_3_E_out = clk_3_N_in ;
assign clk_3_W_out = clk_3_N_in ;
assign clk_3_N_out = clk_3_N_in ;
assign clk_3_S_out = clk_3_N_in ;
assign prog_clk_0 = prog_clk[0] ;
assign prog_clk_1_S_in = prog_clk_1_N_in ;
assign prog_clk_2_N_in = prog_clk_2_W_in ;
assign prog_clk_2_S_in = prog_clk_2_W_in ;
assign prog_clk_3_W_in = prog_clk_3_N_in ;
assign prog_clk_3_S_in = prog_clk_3_N_in ;
assign clk_1_S_in = clk_1_N_in ;
assign clk_2_N_in = clk_2_W_in ;
assign clk_2_S_in = clk_2_W_in ;
assign clk_3_W_in = clk_3_N_in ;
assign clk_3_S_in = clk_3_N_in ;
assign prog_clk_2_E_in = prog_clk_2_W_in ;
assign prog_clk_3_E_in = prog_clk_3_N_in ;
assign clk_2_E_in = clk_2_W_in ;
assign clk_3_E_in = clk_3_N_in ;
sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_0 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
chanx_right_in[1] , chanx_left_out[3] , chanx_left_out[13] ,
chany_top_out[3] , chany_top_out[13] , chanx_left_in[0] ,
chanx_right_out[3] , chanx_right_out[13] } ) ,
.sram ( mux_tree_tapbuf_size12_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( chany_top_out[0] ) , .p0 ( optlc_net_106 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_2 (
.in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] ,
top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
chanx_right_in[3] , chanx_left_out[5] , chanx_left_out[14] ,
chany_top_out[5] , chany_top_out[14] , chanx_right_out[5] ,
chanx_right_out[14] , chanx_left_in[19] } ) ,
.sram ( mux_tree_tapbuf_size12_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( chany_top_out[1] ) , .p0 ( optlc_net_102 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_0 (
.in ( { chany_bottom_out[3] , chany_bottom_out[13] , chany_top_in[19] ,
right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
chany_top_out[3] , chany_top_out[13] , chany_bottom_in[15] ,
chanx_right_out[3] , chanx_right_out[13] } ) ,
.sram ( mux_tree_tapbuf_size12_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_2 (
.in ( { chany_top_in[0] , chany_bottom_out[5] , chany_bottom_out[14] ,
right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] ,
right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] ,
chany_top_out[5] , chany_bottom_in[11] , chany_top_out[14] ,
chanx_right_out[5] , chanx_right_out[14] } ) ,
.sram ( mux_tree_tapbuf_size12_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_103 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_1 (
.in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_left_out[3] ,
chanx_left_out[13] , chanx_right_in[15] ,
bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] ,
bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] ,
chanx_left_in[1] , chanx_right_out[3] , chanx_right_out[13] } ) ,
.sram ( mux_tree_tapbuf_size12_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( chany_bottom_out[0] ) , .p0 ( optlc_net_103 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_3 (
.in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_left_out[5] ,
chanx_right_in[11] , chanx_left_out[14] ,
bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] ,
bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] ,
chanx_left_in[3] , chanx_right_out[5] , chanx_right_out[14] } ) ,
.sram ( mux_tree_tapbuf_size12_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( chany_bottom_out[1] ) , .p0 ( optlc_net_102 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_1 (
.in ( { chany_top_in[0] , chany_bottom_out[3] , chany_bottom_out[13] ,
chanx_left_out[3] , chanx_left_out[13] , chany_top_out[3] ,
chany_top_out[13] , chany_bottom_in[19] ,
left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] ,
left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size12_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ;
sb_1__1__mux_tree_tapbuf_size12 mux_left_track_3 (
.in ( { chany_bottom_out[5] , chany_bottom_out[14] , chany_top_in[19] ,
chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] ,
chany_top_out[5] , chany_top_out[14] , left_bottom_grid_pin_35_[0] ,
left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] ,
left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size12_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( chanx_left_out[1] ) , .p0 ( optlc_net_104 ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_0 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size16_0 mux_top_track_4 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] ,
top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] ,
top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] ,
top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] ,
chanx_left_out[6] , chanx_right_in[7] , chanx_left_out[15] ,
chany_top_out[6] , chany_top_out[15] , chanx_right_out[6] ,
chanx_right_out[15] , chanx_left_in[15] } ) ,
.sram ( mux_tree_tapbuf_size16_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 ,
SYNOPSYS_UNCONNECTED_37 } ) ,
.out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ;
sb_1__1__mux_tree_tapbuf_size16_1 mux_right_track_4 (
.in ( { chany_top_in[1] , chany_bottom_out[6] , chany_bottom_out[15] ,
right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] ,
right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] ,
right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] ,
right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] ,
chany_top_out[6] , chany_bottom_in[7] , chany_top_out[15] ,
chanx_right_out[6] , chanx_right_out[15] } ) ,
.sram ( mux_tree_tapbuf_size16_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 ,
SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
SYNOPSYS_UNCONNECTED_42 } ) ,
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_103 ) ) ;
sb_1__1__mux_tree_tapbuf_size16_2 mux_bottom_track_5 (
.in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_left_out[6] ,
chanx_right_in[7] , chanx_left_out[15] , bottom_left_grid_pin_42_[0] ,
bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] ,
bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] ,
bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] ,
bottom_left_grid_pin_49_[0] , chanx_right_out[6] , chanx_left_in[7] ,
chanx_right_out[15] } ) ,
.sram ( mux_tree_tapbuf_size16_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
SYNOPSYS_UNCONNECTED_47 } ) ,
.out ( chany_bottom_out[2] ) , .p0 ( optlc_net_102 ) ) ;
sb_1__1__mux_tree_tapbuf_size16 mux_left_track_5 (
.in ( { chany_bottom_out[6] , chany_bottom_out[15] , chany_top_in[15] ,
chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] ,
chany_top_out[6] , chany_top_out[15] , left_bottom_grid_pin_34_[0] ,
left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_36_[0] ,
left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_38_[0] ,
left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] ,
left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size16_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 ,
SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 ,
SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( chanx_left_out[2] ) , .p0 ( optlc_net_104 ) ) ;
sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_top_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_right_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_bottom_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size16_mem mem_left_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_8 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] ,
chanx_left_out[7] , chanx_right_in[11] , chanx_left_out[17] ,
chany_top_out[7] , chany_top_out[17] , chanx_right_out[7] ,
chanx_left_in[11] , chanx_right_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
.out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_16 (
.in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] ,
chanx_left_out[9] , chanx_right_in[15] , chanx_left_out[18] ,
chany_top_out[9] , chany_top_out[18] , chanx_left_in[7] ,
chanx_right_out[9] , chanx_right_out[18] } ) ,
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
.out ( chany_top_out[8] ) , .p0 ( optlc_net_107 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_24 (
.in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] ,
chanx_left_out[10] , chanx_left_out[19] , chanx_right_in[19] ,
chany_top_out[10] , chany_top_out[19] , chanx_left_in[3] ,
chanx_right_out[10] , chanx_right_out[19] } ) ,
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
.out ( chany_top_out[12] ) , .p0 ( optlc_net_107 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_8 (
.in ( { chany_top_in[3] , chany_bottom_out[7] , chany_bottom_out[17] ,
right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] ,
chany_bottom_in[3] , chany_top_out[7] , chany_top_out[17] ,
chanx_right_out[7] , chanx_right_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
.out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_16 (
.in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] ,
right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] ,
chany_bottom_in[1] , chany_top_out[9] , chany_top_out[18] ,
chanx_right_out[9] , chanx_right_out[18] } ) ,
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 ,
SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
.out ( chanx_right_out[8] ) , .p0 ( optlc_net_108 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_24 (
.in ( { chany_bottom_out[10] , chany_top_in[11] , chany_bottom_out[19] ,
right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] ,
chany_bottom_in[0] , chany_top_out[10] , chany_top_out[19] ,
chanx_right_out[10] , chanx_right_out[19] } ) ,
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
.out ( chanx_right_out[12] ) , .p0 ( optlc_net_108 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_9 (
.in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[3] ,
chanx_left_out[7] , chanx_left_out[17] , bottom_left_grid_pin_42_[0] ,
bottom_left_grid_pin_46_[0] , chanx_right_out[7] , chanx_left_in[11] ,
chanx_right_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
.out ( chany_bottom_out[4] ) , .p0 ( optlc_net_102 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_17 (
.in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] ,
chanx_left_out[9] , chanx_left_out[18] , bottom_left_grid_pin_43_[0] ,
bottom_left_grid_pin_47_[0] , chanx_right_out[9] , chanx_left_in[15] ,
chanx_right_out[18] } ) ,
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 ,
SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
.out ( chany_bottom_out[8] ) , .p0 ( optlc_net_102 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_25 (
.in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] ,
chanx_left_out[10] , chanx_left_out[19] ,
bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] ,
chanx_right_out[10] , chanx_right_out[19] , chanx_left_in[19] } ) ,
.sram ( mux_tree_tapbuf_size10_8_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
.out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_9 (
.in ( { chany_bottom_out[7] , chany_top_in[11] , chany_bottom_out[17] ,
chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[3] ,
chany_top_out[7] , chany_top_out[17] , left_bottom_grid_pin_34_[0] ,
left_bottom_grid_pin_38_[0] } ) ,
.sram ( mux_tree_tapbuf_size10_9_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
.out ( chanx_left_out[4] ) , .p0 ( optlc_net_102 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_17 (
.in ( { chany_top_in[7] , chany_bottom_out[9] , chany_bottom_out[18] ,
chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[7] ,
chany_top_out[9] , chany_top_out[18] , left_bottom_grid_pin_35_[0] ,
left_bottom_grid_pin_39_[0] } ) ,
.sram ( mux_tree_tapbuf_size10_10_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 ,
SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
.out ( chanx_left_out[8] ) , .p0 ( optlc_net_105 ) ) ;
sb_1__1__mux_tree_tapbuf_size10 mux_left_track_25 (
.in ( { chany_top_in[3] , chany_bottom_out[10] , chany_bottom_out[19] ,
chanx_left_out[10] , chanx_left_out[19] , chany_top_out[10] ,
chany_bottom_in[11] , chany_top_out[19] ,
left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size10_11_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 ,
SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
.out ( chanx_left_out[12] ) , .p0 ( optlc_net_105 ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size7_0 mux_top_track_32 (
.in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] ,
chanx_right_in[0] , chanx_left_out[11] , chany_top_out[11] ,
chanx_left_in[1] , chanx_right_out[11] } ) ,
.sram ( mux_tree_tapbuf_size7_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 ,
SYNOPSYS_UNCONNECTED_103 } ) ,
.out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ;
sb_1__1__mux_tree_tapbuf_size7_1 mux_right_track_32 (
.in ( { chany_bottom_out[11] , chany_top_in[15] ,
right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] ,
chany_top_out[11] , chany_bottom_in[19] , chanx_right_out[11] } ) ,
.sram ( mux_tree_tapbuf_size7_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 ,
SYNOPSYS_UNCONNECTED_106 } ) ,
.out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ;
sb_1__1__mux_tree_tapbuf_size7_2 mux_bottom_track_33 (
.in ( { chany_bottom_out[11] , chanx_left_out[11] , chanx_right_in[19] ,
bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] ,
chanx_left_in[0] , chanx_right_out[11] } ) ,
.sram ( mux_tree_tapbuf_size7_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 ,
SYNOPSYS_UNCONNECTED_109 } ) ,
.out ( chany_bottom_out[16] ) , .p0 ( optlc_net_103 ) ) ;
sb_1__1__mux_tree_tapbuf_size7 mux_left_track_33 (
.in ( { chany_top_in[1] , chany_bottom_out[11] , chanx_left_out[11] ,
chany_top_out[11] , chany_bottom_in[15] ,
left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size7_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 ,
SYNOPSYS_UNCONNECTED_112 } ) ,
.out ( chanx_left_out[16] ) , .p0 ( optlc_net_104 ) ) ;
sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_32 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_32 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_33 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_1__1__mux_tree_tapbuf_size7_mem mem_left_track_33 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_113 ) ,
.HI ( optlc_net_102 ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_top_in[2] ) ,
.X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_top_in[4] ) ,
.X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_top_in[5] ) ,
.X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_top_in[6] ) ,
.X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[8] ) ,
.X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[9] ) ,
.X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[10] ) ,
.X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[12] ) ,
.X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[13] ) ,
.X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[14] ) ,
.X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) ,
.X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[17] ) ,
.X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[18] ) ,
.X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[2] ) ,
.X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) ,
.X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) ,
.X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) ,
.X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[8] ) ,
.X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[9] ) ,
.X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[10] ) ,
.X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) ,
.X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) ,
.X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) ,
.X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[16] ) ,
.X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[17] ) ,
.X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[18] ) ,
.X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[2] ) ,
.X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[4] ) ,
.X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[5] ) ,
.X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[6] ) ,
.X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[8] ) ,
.X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[9] ) ,
.X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_bottom_in[10] ) ,
.X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_bottom_in[12] ) ,
.X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_bottom_in[13] ) ,
.X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_bottom_in[14] ) ,
.X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_bottom_in[16] ) ,
.X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_bottom_in[17] ) ,
.X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_bottom_in[18] ) ,
.X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_left_in[2] ) ,
.X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[4] ) ,
.X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[5] ) ,
.X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[6] ) ,
.X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[8] ) ,
.X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[9] ) ,
.X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[10] ) ,
.X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[12] ) ,
.X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[13] ) ,
.X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[14] ) ,
.X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[16] ) ,
.X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[17] ) ,
.X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[18] ) ,
.X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( Test_en_S_in ) ,
.X ( Test_en_N_out ) ) ;
sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_114 ) ,
.HI ( optlc_net_103 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_115 ) ,
.HI ( optlc_net_104 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_116 ) ,
.HI ( optlc_net_105 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_117 ) ,
.HI ( optlc_net_106 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_118 ) ,
.HI ( optlc_net_107 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) ,
.HI ( optlc_net_108 ) ) ;
endmodule |
module sb_0__1_ ( chany_top_in , top_left_grid_pin_1_ , chanx_right_in ,
right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ ,
right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in ,
bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out ,
chany_bottom_out , ccff_tail , prog_clk_0_E_in ) ;
input [0:19] chany_top_in ;
input [0:0] top_left_grid_pin_1_ ;
input [0:19] chanx_right_in ;
input [0:0] right_bottom_grid_pin_34_ ;
input [0:0] right_bottom_grid_pin_35_ ;
input [0:0] right_bottom_grid_pin_36_ ;
input [0:0] right_bottom_grid_pin_37_ ;
input [0:0] right_bottom_grid_pin_38_ ;
input [0:0] right_bottom_grid_pin_39_ ;
input [0:0] right_bottom_grid_pin_40_ ;
input [0:0] right_bottom_grid_pin_41_ ;
input [0:19] chany_bottom_in ;
input [0:0] bottom_left_grid_pin_1_ ;
input [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_right_out ;
output [0:19] chany_bottom_out ;
output [0:0] ccff_tail ;
input prog_clk_0_E_in ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
wire [0:2] mux_tree_tapbuf_size4_4_sram ;
wire [0:2] mux_tree_tapbuf_size4_5_sram ;
wire [0:2] mux_tree_tapbuf_size4_6_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
wire [0:2] mux_tree_tapbuf_size5_2_sram ;
wire [0:2] mux_tree_tapbuf_size5_3_sram ;
wire [0:2] mux_tree_tapbuf_size5_4_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
wire [0:2] mux_tree_tapbuf_size6_3_sram ;
wire [0:2] mux_tree_tapbuf_size6_4_sram ;
wire [0:2] mux_tree_tapbuf_size6_5_sram ;
wire [0:2] mux_tree_tapbuf_size6_6_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 (
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] ,
chanx_right_in[15] , chany_top_out[3] , chany_top_out[13] } ) ,
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 } ) ,
.out ( chany_top_out[0] ) , .p0 ( optlc_net_114 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_4 (
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] ,
chanx_right_in[17] , chany_top_out[6] , chany_top_out[15] } ) ,
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
SYNOPSYS_UNCONNECTED_6 } ) ,
.out ( chany_top_out[2] ) , .p0 ( optlc_net_114 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_8 (
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] ,
chanx_right_in[18] , chany_top_out[7] , chany_top_out[17] } ) ,
.sram ( mux_tree_tapbuf_size6_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
SYNOPSYS_UNCONNECTED_9 } ) ,
.out ( chany_top_out[4] ) , .p0 ( optlc_net_114 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 (
.in ( { chany_bottom_out[3] , right_bottom_grid_pin_34_[0] ,
right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] ,
right_bottom_grid_pin_40_[0] , chany_top_out[3] } ) ,
.sram ( mux_tree_tapbuf_size6_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_115 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_4 mux_bottom_track_1 (
.in ( { chany_bottom_out[3] , chany_bottom_out[13] , chanx_right_in[5] ,
chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 } ) ,
.out ( chany_bottom_out[0] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_5 mux_bottom_track_5 (
.in ( { chany_bottom_out[6] , chany_bottom_out[15] , chanx_right_in[3] ,
chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
SYNOPSYS_UNCONNECTED_18 } ) ,
.out ( chany_bottom_out[2] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_9 (
.in ( { chany_bottom_out[7] , chany_bottom_out[17] , chanx_right_in[2] ,
chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
SYNOPSYS_UNCONNECTED_21 } ) ,
.out ( chany_bottom_out[4] ) , .p0 ( optlc_net_116 ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_bottom_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_bottom_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 (
.in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] ,
chany_top_out[5] , chany_top_out[14] } ) ,
.sram ( mux_tree_tapbuf_size5_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( chany_top_out[1] ) , .p0 ( optlc_net_115 ) ) ;
sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_16 (
.in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] ,
chany_top_out[9] , chany_top_out[18] } ) ,
.sram ( mux_tree_tapbuf_size5_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
SYNOPSYS_UNCONNECTED_27 } ) ,
.out ( chany_top_out[8] ) , .p0 ( optlc_net_116 ) ) ;
sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 (
.in ( { chany_bottom_out[5] , chany_bottom_out[14] , chanx_right_in[4] ,
chanx_right_in[11] , chanx_right_in[18] } ) ,
.sram ( mux_tree_tapbuf_size5_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
SYNOPSYS_UNCONNECTED_30 } ) ,
.out ( chany_bottom_out[1] ) , .p0 ( optlc_net_114 ) ) ;
sb_0__1__mux_tree_tapbuf_size5_3 mux_bottom_track_17 (
.in ( { chany_bottom_out[9] , chany_bottom_out[18] , chanx_right_in[1] ,
chanx_right_in[8] , chanx_right_in[15] } ) ,
.sram ( mux_tree_tapbuf_size5_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 ,
SYNOPSYS_UNCONNECTED_33 } ) ,
.out ( chany_bottom_out[8] ) , .p0 ( optlc_net_116 ) ) ;
sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_25 (
.in ( { chany_bottom_out[10] , chany_bottom_out[19] , chanx_right_in[0] ,
chanx_right_in[7] , chanx_right_in[14] } ) ,
.sram ( mux_tree_tapbuf_size5_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 ,
SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( chany_bottom_out[12] ) , .p0 ( optlc_net_117 ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_24 (
.in ( { chanx_right_in[6] , chanx_right_in[13] , chany_top_out[10] ,
chany_top_out[19] } ) ,
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
SYNOPSYS_UNCONNECTED_39 } ) ,
.out ( chany_top_out[12] ) , .p0 ( optlc_net_116 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_32 (
.in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] ,
chany_top_out[11] } ) ,
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
SYNOPSYS_UNCONNECTED_42 } ) ,
.out ( chany_top_out[16] ) , .p0 ( optlc_net_115 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_8 (
.in ( { chany_top_in[7] , chany_bottom_out[9] ,
right_bottom_grid_pin_34_[0] , chany_top_out[9] } ) ,
.sram ( mux_tree_tapbuf_size4_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
SYNOPSYS_UNCONNECTED_45 } ) ,
.out ( chanx_right_out[4] ) , .p0 ( optlc_net_115 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_10 (
.in ( { chany_bottom_out[10] , chany_top_in[11] ,
right_bottom_grid_pin_35_[0] , chany_top_out[10] } ) ,
.sram ( mux_tree_tapbuf_size4_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 ,
SYNOPSYS_UNCONNECTED_48 } ) ,
.out ( chanx_right_out[5] ) , .p0 ( optlc_net_115 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_12 (
.in ( { chany_bottom_out[11] , chany_top_in[15] ,
right_bottom_grid_pin_36_[0] , chany_top_out[11] } ) ,
.sram ( mux_tree_tapbuf_size4_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
SYNOPSYS_UNCONNECTED_51 } ) ,
.out ( chanx_right_out[6] ) , .p0 ( optlc_net_115 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_14 (
.in ( { chany_bottom_out[13] , chany_top_in[19] ,
right_bottom_grid_pin_37_[0] , chany_top_out[13] } ) ,
.sram ( mux_tree_tapbuf_size4_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 ,
SYNOPSYS_UNCONNECTED_54 } ) ,
.out ( chanx_right_out[7] ) , .p0 ( optlc_net_114 ) ) ;
sb_0__1__mux_tree_tapbuf_size4 mux_right_track_24 (
.in ( { chany_bottom_out[19] , right_bottom_grid_pin_34_[0] ,
chany_top_out[19] , chany_bottom_in[19] } ) ,
.sram ( mux_tree_tapbuf_size4_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 ,
SYNOPSYS_UNCONNECTED_57 } ) ,
.out ( chanx_right_out[12] ) , .p0 ( optlc_net_117 ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_32 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_10 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_12 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_14 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size4_mem mem_right_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 (
.in ( { chany_top_in[0] , chany_bottom_out[5] ,
right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] ,
right_bottom_grid_pin_39_[0] , chanx_right_out[19] ,
chany_top_out[5] } ) ,
.sram ( mux_tree_tapbuf_size7_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 ,
SYNOPSYS_UNCONNECTED_60 } ) ,
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_115 ) ) ;
sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 (
.in ( { chany_top_in[1] , chany_bottom_out[6] ,
right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
chany_top_out[6] } ) ,
.sram ( mux_tree_tapbuf_size7_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
SYNOPSYS_UNCONNECTED_63 } ) ,
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ;
sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 (
.in ( { chany_top_in[3] , chany_bottom_out[7] ,
right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] ,
right_bottom_grid_pin_39_[0] , chanx_right_out[19] ,
chany_top_out[7] } ) ,
.sram ( mux_tree_tapbuf_size7_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 ,
SYNOPSYS_UNCONNECTED_66 } ) ,
.out ( chanx_right_out[3] ) , .p0 ( optlc_net_115 ) ) ;
sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_0 mux_right_track_16 (
.in ( { chany_bottom_out[14] , right_bottom_grid_pin_38_[0] ,
chany_top_out[14] } ) ,
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
.out ( chanx_right_out[8] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_18 (
.in ( { chany_bottom_out[15] , right_bottom_grid_pin_39_[0] ,
chany_top_out[15] } ) ,
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
.out ( chanx_right_out[9] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_20 (
.in ( { chany_bottom_out[17] , right_bottom_grid_pin_40_[0] ,
chany_top_out[17] } ) ,
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
.out ( chanx_right_out[10] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_22 (
.in ( { chany_bottom_out[18] , chanx_right_out[19] , chany_top_out[18] } ) ,
.sram ( mux_tree_tapbuf_size3_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
.out ( chanx_right_out[11] ) , .p0 ( optlc_net_117 ) ) ;
sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_33 (
.in ( { chany_bottom_out[11] , chanx_right_in[6] , chanx_right_in[13] } ) ,
.sram ( mux_tree_tapbuf_size3_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
.out ( chany_bottom_out[16] ) , .p0 ( optlc_net_117 ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_right_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_18 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_20 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_22 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_33 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 (
.in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) ,
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
.out ( chanx_right_out[13] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 (
.in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) ,
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
.out ( chanx_right_out[14] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 (
.in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) ,
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
.out ( chanx_right_out[15] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 (
.in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
.out ( chanx_right_out[16] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 (
.in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) ,
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
.out ( chanx_right_out[17] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 (
.in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) ,
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
.out ( chanx_right_out[18] ) , .p0 ( optlc_net_113 ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[2] ) ,
.X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[4] ) ,
.X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[5] ) ,
.X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[6] ) ,
.X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[8] ) ,
.X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[9] ) ,
.X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[10] ) ,
.X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[12] ) ,
.X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[13] ) ,
.X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[14] ) ,
.X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[16] ) ,
.X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[17] ) ,
.X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[18] ) ,
.X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( right_bottom_grid_pin_41_[0] ) ,
.X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[2] ) ,
.X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_bottom_in[4] ) ,
.X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_bottom_in[5] ) ,
.X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_bottom_in[6] ) ,
.X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_bottom_in[8] ) ,
.X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_bottom_in[9] ) ,
.X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_bottom_in[10] ) ,
.X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_bottom_in[12] ) ,
.X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_bottom_in[13] ) ,
.X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_bottom_in[14] ) ,
.X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_bottom_in[16] ) ,
.X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_bottom_in[17] ) ,
.X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_bottom_in[18] ) ,
.X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) ,
.HI ( optlc_net_113 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) ,
.HI ( optlc_net_114 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) ,
.HI ( optlc_net_115 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_92 ) ,
.HI ( optlc_net_116 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_93 ) ,
.HI ( optlc_net_117 ) ) ;
endmodule |
module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk ,
ccff_head , ccff_tail , mem_out ) ;
input [0:0] prog_clk ;
input [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;
wire copt_net_60 ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
.CLK ( prog_clk[0] ) , .Q ( copt_net_60 ) ) ;
sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_60 ) ,
.X ( copt_net_55 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( copt_net_55 ) ,
.X ( copt_net_56 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_56 ) ,
.X ( copt_net_57 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) ,
.X ( copt_net_58 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_61 ) ,
.X ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1193 ( .A ( copt_net_58 ) ,
.X ( copt_net_61 ) ) ;
endmodule |
module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
input SOC_IN ;
output SOC_OUT ;
output SOC_DIR ;
output FPGA_IN ;
input FPGA_OUT ;
input FPGA_DIR ;
input IO_ISOL_N ;
sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
.B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_43 ) , .Y ( SOC_DIR_N ) ) ;
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
.TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
.TE_B ( BUF_net_43 ) , .Z ( SOC_OUT ) ) ;
sky130_fd_sc_hd__inv_4 BINV_R_43 ( .A ( BUF_net_45 ) , .Y ( BUF_net_43 ) ) ;
sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( SOC_DIR ) ) ;
sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( aps_rename_505_ ) ,
.Y ( BUF_net_45 ) ) ;
endmodule |
module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk ,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head ,
iopad_inpad , ccff_tail ) ;
input [0:0] IO_ISOL_N ;
input [0:0] prog_clk ;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
input [0:0] iopad_outpad ;
input [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
wire [0:0] EMBEDDED_IO_HD_0_en ;
cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
.SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
.SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
.SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
.FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
.FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
endmodule |
module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk ,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
ccff_tail ) ;
input [0:0] IO_ISOL_N ;
input [0:0] prog_clk ;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
input [0:0] io_outpad ;
input [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
.iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
.iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
endmodule |
module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
ccff_tail , mem_out ) ;
input [0:0] prog_clk ;
input [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_54 ) ,
.CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
.CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
.CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
.CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( ccff_head[0] ) ,
.X ( copt_net_49 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_49 ) ,
.X ( copt_net_50 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_50 ) ,
.X ( copt_net_51 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( copt_net_51 ) ,
.X ( copt_net_52 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_52 ) ,
.X ( copt_net_53 ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_53 ) ,
.X ( copt_net_54 ) ) ;
endmodule |
module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
input [0:9] in ;
input [0:3] sram ;
input [0:3] sram_inv ;
output [0:0] out ;
input p0 ;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
.A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
.X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) ,
.A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
.X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) ,
.S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) ,
.S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
.A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ,
.A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) ,
.X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
.A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
.A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
.X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
.A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
.A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
.X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ;
sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ,
.Y ( BUF_net_47 ) ) ;
endmodule |
module cby_1__1_ ( chany_bottom_in , chany_top_in , ccff_head ,
chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ ,
left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ ,
left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ ,
left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ ,
left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ ,
left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in ,
Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out ,
Test_en_E_out , prog_clk_0_W_in , prog_clk_0_S_out , prog_clk_0_N_out ,
prog_clk_2_N_in , prog_clk_2_S_in , prog_clk_2_S_out , prog_clk_2_N_out ,
prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_N_out , prog_clk_3_S_out ,
clk_2_N_in , clk_2_S_in , clk_2_S_out , clk_2_N_out , clk_3_S_in ,
clk_3_N_in , clk_3_N_out , clk_3_S_out ) ;
input [0:19] chany_bottom_in ;
input [0:19] chany_top_in ;
input [0:0] ccff_head ;
output [0:19] chany_bottom_out ;
output [0:19] chany_top_out ;
output [0:0] left_grid_pin_16_ ;
output [0:0] left_grid_pin_17_ ;
output [0:0] left_grid_pin_18_ ;
output [0:0] left_grid_pin_19_ ;
output [0:0] left_grid_pin_20_ ;
output [0:0] left_grid_pin_21_ ;
output [0:0] left_grid_pin_22_ ;
output [0:0] left_grid_pin_23_ ;
output [0:0] left_grid_pin_24_ ;
output [0:0] left_grid_pin_25_ ;
output [0:0] left_grid_pin_26_ ;
output [0:0] left_grid_pin_27_ ;
output [0:0] left_grid_pin_28_ ;
output [0:0] left_grid_pin_29_ ;
output [0:0] left_grid_pin_30_ ;
output [0:0] left_grid_pin_31_ ;
output [0:0] ccff_tail ;
input Test_en_S_in ;
input Test_en_E_in ;
input Test_en_W_in ;
output Test_en_N_out ;
output Test_en_W_out ;
output Test_en_E_out ;
input prog_clk_0_W_in ;
output prog_clk_0_S_out ;
output prog_clk_0_N_out ;
input prog_clk_2_N_in ;
input prog_clk_2_S_in ;
output prog_clk_2_S_out ;
output prog_clk_2_N_out ;
input prog_clk_3_S_in ;
input prog_clk_3_N_in ;
output prog_clk_3_N_out ;
output prog_clk_3_S_out ;
input clk_2_N_in ;
input clk_2_S_in ;
output clk_2_S_out ;
output clk_2_N_out ;
input clk_3_S_in ;
input clk_3_N_in ;
output clk_3_N_out ;
output clk_3_S_out ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:3] mux_tree_tapbuf_size8_3_sram ;
wire [0:3] mux_tree_tapbuf_size8_4_sram ;
wire [0:3] mux_tree_tapbuf_size8_5_sram ;
wire [0:3] mux_tree_tapbuf_size8_6_sram ;
wire [0:3] mux_tree_tapbuf_size8_7_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
assign Test_en_E_in = Test_en_S_in ;
assign Test_en_E_in = Test_en_W_in ;
assign prog_clk_0 = prog_clk[0] ;
assign prog_clk_2_S_in = prog_clk_2_N_in ;
assign prog_clk_3_N_in = prog_clk_3_S_in ;
assign clk_2_S_in = clk_2_N_in ;
assign clk_3_N_in = clk_3_S_in ;
cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] ,
chany_bottom_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( left_grid_pin_16_ ) , .p0 ( optlc_net_76 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
chany_bottom_out[19] } ) ,
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] ,
chany_bottom_out[14] } ) ,
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] ,
chany_bottom_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( left_grid_pin_23_ ) , .p0 ( optlc_net_75 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] ,
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
chany_bottom_out[18] } ) ,
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
chany_top_out[11] , chany_bottom_out[11] , chany_top_out[15] ,
chany_bottom_out[15] } ) ,
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_12 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] ,
chany_bottom_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( left_grid_pin_28_ ) , .p0 ( optlc_net_76 ) ) ;
cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
chany_top_out[15] , chany_bottom_out[15] , chany_top_out[19] ,
chany_bottom_out[19] } ) ,
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
chany_top_out[13] , chany_bottom_out[13] } ) ,
.sram ( mux_tree_tapbuf_size8_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
chany_top_out[14] , chany_bottom_out[14] } ) ,
.sram ( mux_tree_tapbuf_size8_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
.out ( left_grid_pin_18_ ) , .p0 ( optlc_net_76 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
chany_top_out[17] , chany_bottom_out[17] } ) ,
.sram ( mux_tree_tapbuf_size8_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
.out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] ,
chany_top_out[18] , chany_bottom_out[18] } ) ,
.sram ( mux_tree_tapbuf_size8_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
.out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
chany_top_out[13] , chany_bottom_out[13] } ) ,
.sram ( mux_tree_tapbuf_size8_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
chany_top_out[14] , chany_bottom_out[14] } ) ,
.sram ( mux_tree_tapbuf_size8_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
.out ( left_grid_pin_26_ ) , .p0 ( optlc_net_76 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
chany_top_out[17] , chany_bottom_out[17] } ) ,
.sram ( mux_tree_tapbuf_size8_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
.out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] ,
chany_top_out[18] , chany_bottom_out[18] } ) ,
.sram ( mux_tree_tapbuf_size8_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
.out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) ,
.X ( aps_rename_505_ ) ) ;
sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) ,
.X ( Test_en_W_out ) ) ;
sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) ,
.X ( net_net_68 ) ) ;
sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
.X ( ctsbuf_net_177 ) ) ;
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
.X ( ctsbuf_net_278 ) ) ;
sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) ,
.X ( ropt_net_87 ) ) ;
sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) ,
.X ( aps_rename_506_ ) ) ;
sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) ,
.X ( aps_rename_507_ ) ) ;
sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) ,
.X ( prog_clk_3_S_out ) ) ;
sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) ,
.X ( clk_2_S_out ) ) ;
sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) ,
.X ( aps_rename_508_ ) ) ;
sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) ,
.X ( aps_rename_509_ ) ) ;
sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) ,
.X ( aps_rename_510_ ) ) ;
sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) ,
.X ( chany_top_out[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) ,
.X ( chany_top_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) ,
.X ( chany_top_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) ,
.X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) ,
.X ( chany_top_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) ,
.X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) ,
.X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) ,
.X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) ,
.X ( chany_top_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) ,
.X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) ,
.X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) ,
.X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) ,
.X ( chany_top_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) ,
.X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) ,
.X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) ,
.X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) ,
.X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) ,
.X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) ,
.X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) ,
.X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[0] ) ,
.X ( chany_bottom_out[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[1] ) ,
.X ( chany_bottom_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[2] ) ,
.X ( chany_bottom_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[3] ) ,
.X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[4] ) ,
.X ( chany_bottom_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[5] ) ,
.X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[6] ) ,
.X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[7] ) ,
.X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[8] ) ,
.X ( chany_bottom_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[9] ) ,
.X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[10] ) ,
.X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[11] ) ,
.X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[12] ) ,
.X ( chany_bottom_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[13] ) ,
.X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[14] ) ,
.X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[15] ) ,
.X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[16] ) ,
.X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[17] ) ,
.X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) ,
.X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) ,
.X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( Test_en_N_out ) ) ;
sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) ,
.Y ( BUF_net_67 ) ) ;
sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( Test_en_E_out ) ) ;
sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( clk_3_S_out ) ) ;
sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( aps_rename_510_ ) ,
.Y ( BUF_net_70 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
.HI ( optlc_net_75 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
.HI ( optlc_net_76 ) ) ;
sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_509_ ) ,
.X ( clk_3_N_out ) ) ;
sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_585 ( .A ( aps_rename_508_ ) ,
.X ( clk_2_N_out ) ) ;
sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_586 ( .A ( aps_rename_507_ ) ,
.X ( prog_clk_3_N_out ) ) ;
sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_587 ( .A ( aps_rename_506_ ) ,
.X ( prog_clk_2_N_out ) ) ;
sky130_fd_sc_hd__buf_6 ropt_mt_inst_1358 ( .A ( ropt_net_87 ) ,
.X ( prog_clk_2_S_out ) ) ;
sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_177 ) ,
.X ( prog_clk_0_S_out ) ) ;
sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_278 ) ,
.X ( prog_clk_0_N_out ) ) ;
endmodule |
module sb_1__2_ ( chanx_right_in , right_top_grid_pin_1_ ,
right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ ,
right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in ,
bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ ,
bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ ,
bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ ,
bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in ,
left_top_grid_pin_1_ , left_bottom_grid_pin_34_ ,
left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ ,
left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
left_bottom_grid_pin_41_ , ccff_head , chanx_right_out ,
chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT ,
prog_clk_0_S_in ) ;
input [0:19] chanx_right_in ;
input [0:0] right_top_grid_pin_1_ ;
input [0:0] right_bottom_grid_pin_34_ ;
input [0:0] right_bottom_grid_pin_35_ ;
input [0:0] right_bottom_grid_pin_36_ ;
input [0:0] right_bottom_grid_pin_37_ ;
input [0:0] right_bottom_grid_pin_38_ ;
input [0:0] right_bottom_grid_pin_39_ ;
input [0:0] right_bottom_grid_pin_40_ ;
input [0:0] right_bottom_grid_pin_41_ ;
input [0:19] chany_bottom_in ;
input [0:0] bottom_left_grid_pin_42_ ;
input [0:0] bottom_left_grid_pin_43_ ;
input [0:0] bottom_left_grid_pin_44_ ;
input [0:0] bottom_left_grid_pin_45_ ;
input [0:0] bottom_left_grid_pin_46_ ;
input [0:0] bottom_left_grid_pin_47_ ;
input [0:0] bottom_left_grid_pin_48_ ;
input [0:0] bottom_left_grid_pin_49_ ;
input [0:19] chanx_left_in ;
input [0:0] left_top_grid_pin_1_ ;
input [0:0] left_bottom_grid_pin_34_ ;
input [0:0] left_bottom_grid_pin_35_ ;
input [0:0] left_bottom_grid_pin_36_ ;
input [0:0] left_bottom_grid_pin_37_ ;
input [0:0] left_bottom_grid_pin_38_ ;
input [0:0] left_bottom_grid_pin_39_ ;
input [0:0] left_bottom_grid_pin_40_ ;
input [0:0] left_bottom_grid_pin_41_ ;
input [0:0] ccff_head ;
output [0:19] chanx_right_out ;
output [0:19] chany_bottom_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input SC_IN_BOT ;
output SC_OUT_BOT ;
input prog_clk_0_S_in ;
wire ropt_net_118 ;
wire ropt_net_119 ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size14_0_sram ;
wire [0:3] mux_tree_tapbuf_size14_1_sram ;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
wire [0:1] mux_tree_tapbuf_size3_5_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
wire [0:2] mux_tree_tapbuf_size7_4_sram ;
wire [0:2] mux_tree_tapbuf_size7_5_sram ;
wire [0:2] mux_tree_tapbuf_size7_6_sram ;
wire [0:2] mux_tree_tapbuf_size7_7_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size9_0_sram ;
wire [0:3] mux_tree_tapbuf_size9_1_sram ;
wire [0:3] mux_tree_tapbuf_size9_2_sram ;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 (
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] ,
right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] ,
right_bottom_grid_pin_41_[0] , chany_bottom_in[5] ,
chany_bottom_in[12] , chany_bottom_in[19] , chanx_right_out[3] ,
chanx_right_out[13] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ;
sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_2 (
.in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] ,
right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] ,
chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] ,
chanx_right_out[5] , chanx_right_out[14] } ) ,
.sram ( mux_tree_tapbuf_size9_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ;
sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_1 (
.in ( { chanx_left_out[3] , chanx_left_out[13] , chany_bottom_in[6] ,
chany_bottom_in[13] , left_top_grid_pin_1_[0] ,
left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] ,
left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size9_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( chanx_left_out[0] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__2__mux_tree_tapbuf_size9 mux_left_track_3 (
.in ( { chanx_left_out[5] , chanx_left_out[14] , chany_bottom_in[0] ,
chany_bottom_in[7] , chany_bottom_in[14] ,
left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] ,
left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size9_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( chanx_left_out[1] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_3 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size14_0 mux_right_track_4 (
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] ,
right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] ,
right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] ,
right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] ,
right_bottom_grid_pin_41_[0] , chany_bottom_in[3] ,
chany_bottom_in[10] , chany_bottom_in[17] , chanx_right_out[6] ,
chanx_right_out[15] } ) ,
.sram ( mux_tree_tapbuf_size14_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_96 ) ) ;
sb_1__2__mux_tree_tapbuf_size14 mux_left_track_5 (
.in ( { chanx_left_out[6] , chanx_left_out[15] , chany_bottom_in[1] ,
chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] ,
left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] ,
left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] ,
left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] ,
left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size14_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( chanx_left_out[2] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size14_mem mem_left_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_8 (
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] ,
right_bottom_grid_pin_41_[0] , chany_bottom_in[2] ,
chany_bottom_in[9] , chany_bottom_in[16] , chanx_right_out[7] ,
chanx_right_out[17] } ) ,
.sram ( mux_tree_tapbuf_size8_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ;
sb_1__2__mux_tree_tapbuf_size8 mux_left_track_9 (
.in ( { chanx_left_out[7] , chanx_left_out[17] , chany_bottom_in[2] ,
chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] ,
left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) ,
.sram ( mux_tree_tapbuf_size8_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( chanx_left_out[4] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_16 (
.in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] ,
chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] ,
chanx_right_out[9] , chanx_right_out[18] } ) ,
.sram ( mux_tree_tapbuf_size7_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
SYNOPSYS_UNCONNECTED_35 } ) ,
.out ( chanx_right_out[8] ) , .p0 ( optlc_net_96 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_24 (
.in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] ,
chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] ,
chanx_right_out[10] , chanx_right_out[19] } ) ,
.sram ( mux_tree_tapbuf_size7_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 ,
SYNOPSYS_UNCONNECTED_38 } ) ,
.out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_1 (
.in ( { chanx_left_out[3] , bottom_left_grid_pin_42_[0] ,
bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] ,
bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_right_out[3] } ) ,
.sram ( mux_tree_tapbuf_size7_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 ,
SYNOPSYS_UNCONNECTED_41 } ) ,
.out ( chany_bottom_out[0] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_3 (
.in ( { chanx_left_out[5] , bottom_left_grid_pin_43_[0] ,
bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_right_out[5] } ) ,
.sram ( mux_tree_tapbuf_size7_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 ,
SYNOPSYS_UNCONNECTED_44 } ) ,
.out ( chany_bottom_out[1] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_4 mux_bottom_track_5 (
.in ( { chanx_left_out[6] , bottom_left_grid_pin_42_[0] ,
bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] ,
bottom_left_grid_pin_48_[0] , chanx_right_out[6] , chanx_left_in[7] } ) ,
.sram ( mux_tree_tapbuf_size7_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
SYNOPSYS_UNCONNECTED_47 } ) ,
.out ( chany_bottom_out[2] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_5 mux_bottom_track_7 (
.in ( { chanx_left_out[7] , bottom_left_grid_pin_43_[0] ,
bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] ,
bottom_left_grid_pin_49_[0] , chanx_right_out[7] , chanx_left_in[11] } ) ,
.sram ( mux_tree_tapbuf_size7_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 ,
SYNOPSYS_UNCONNECTED_50 } ) ,
.out ( chany_bottom_out[3] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_17 (
.in ( { chanx_left_out[9] , chanx_left_out[18] , chany_bottom_in[3] ,
chany_bottom_in[10] , chany_bottom_in[17] ,
left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) ,
.sram ( mux_tree_tapbuf_size7_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 ,
SYNOPSYS_UNCONNECTED_53 } ) ,
.out ( chanx_left_out[8] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size7 mux_left_track_25 (
.in ( { chanx_left_out[10] , chanx_left_out[19] , chany_bottom_in[4] ,
chany_bottom_in[11] , chany_bottom_in[18] ,
left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) ,
.sram ( mux_tree_tapbuf_size7_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 ,
SYNOPSYS_UNCONNECTED_56 } ) ,
.out ( chanx_left_out[12] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_bottom_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_7 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 (
.in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] ,
chany_bottom_in[6] , chany_bottom_in[13] , chanx_right_out[11] } ) ,
.sram ( mux_tree_tapbuf_size5_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
SYNOPSYS_UNCONNECTED_59 } ) ,
.out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ;
sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_9 (
.in ( { chanx_left_out[9] , bottom_left_grid_pin_42_[0] ,
chanx_right_out[9] , chanx_left_in[15] } ) ,
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 ,
SYNOPSYS_UNCONNECTED_62 } ) ,
.out ( chany_bottom_out[4] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_11 (
.in ( { chanx_left_out[10] , bottom_left_grid_pin_43_[0] ,
chanx_right_out[10] , chanx_left_in[19] } ) ,
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 ,
SYNOPSYS_UNCONNECTED_65 } ) ,
.out ( chany_bottom_out[5] ) , .p0 ( optlc_net_99 ) ) ;
sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_25 (
.in ( { chanx_left_out[19] , chanx_right_in[19] ,
bottom_left_grid_pin_42_[0] , chanx_right_out[19] } ) ,
.sram ( mux_tree_tapbuf_size4_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 ,
SYNOPSYS_UNCONNECTED_68 } ) ,
.out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_11 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 (
.in ( { chanx_left_out[11] , bottom_left_grid_pin_44_[0] ,
chanx_right_out[11] } ) ,
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
.out ( chany_bottom_out[6] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 (
.in ( { chanx_left_out[13] , bottom_left_grid_pin_45_[0] ,
chanx_right_out[13] } ) ,
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
.out ( chany_bottom_out[7] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 (
.in ( { chanx_left_out[14] , bottom_left_grid_pin_46_[0] ,
chanx_right_out[14] } ) ,
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
.out ( chany_bottom_out[8] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 (
.in ( { chanx_left_out[15] , bottom_left_grid_pin_47_[0] ,
chanx_right_out[15] } ) ,
.sram ( mux_tree_tapbuf_size3_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
.out ( chany_bottom_out[9] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 (
.in ( { chanx_left_out[17] , bottom_left_grid_pin_48_[0] ,
chanx_right_out[17] } ) ,
.sram ( mux_tree_tapbuf_size3_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
.out ( chany_bottom_out[10] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 (
.in ( { chanx_left_out[18] , bottom_left_grid_pin_49_[0] ,
chanx_right_out[18] } ) ,
.sram ( mux_tree_tapbuf_size3_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
.out ( chany_bottom_out[11] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 (
.in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) ,
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
.out ( chany_bottom_out[13] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 (
.in ( { chanx_left_out[11] , chany_bottom_in[5] , chany_bottom_in[12] ,
chany_bottom_in[19] , left_bottom_grid_pin_36_[0] ,
left_bottom_grid_pin_40_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 ,
SYNOPSYS_UNCONNECTED_85 } ) ,
.out ( chanx_left_out[16] ) , .p0 ( optlc_net_94 ) ) ;
sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_right_in[0] ) ,
.X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chanx_right_in[1] ) ,
.X ( ropt_net_118 ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[2] ) ,
.X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[3] ) ,
.X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[4] ) ,
.X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[5] ) ,
.X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[6] ) ,
.X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[7] ) ,
.X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[8] ) ,
.X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[9] ) ,
.X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[10] ) ,
.X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[11] ) ,
.X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[12] ) ,
.X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[13] ) ,
.X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[14] ) ,
.X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[16] ) ,
.X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[17] ) ,
.X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[18] ) ,
.X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[0] ) ,
.X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[2] ) ,
.X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[4] ) ,
.X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[5] ) ,
.X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[6] ) ,
.X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[8] ) ,
.X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[9] ) ,
.X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[10] ) ,
.X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[12] ) ,
.X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[13] ) ,
.X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[14] ) ,
.X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[16] ) ,
.X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[17] ) ,
.X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[18] ) ,
.X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) ,
.HI ( optlc_net_94 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) ,
.HI ( optlc_net_95 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) ,
.HI ( optlc_net_96 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) ,
.HI ( optlc_net_97 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) ,
.HI ( optlc_net_98 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_91 ) ,
.HI ( optlc_net_99 ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_118 ) ,
.X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_119 ) ,
.X ( SC_OUT_BOT ) ) ;
endmodule |
module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk ,
ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
input [0:0] prog_clk ;
input [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:0] mem_out ;
input VDD ;
input VSS ;
wire copt_net_60 ;
supply1 VDD ;
supply0 VSS ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) ,
.CLK ( prog_clk[0] ) , .Q ( copt_net_60 ) , .VPWR ( VDD ) ,
.VGND ( VSS ) ) ;
sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ,
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_60 ) ,
.X ( copt_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( copt_net_55 ) ,
.X ( copt_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_56 ) ,
.X ( copt_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) ,
.X ( copt_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_61 ) ,
.X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1193 ( .A ( copt_net_58 ) ,
.X ( copt_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
endmodule |
module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk ,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head ,
iopad_inpad , ccff_tail , VDD , VSS ) ;
input [0:0] IO_ISOL_N ;
input [0:0] prog_clk ;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
input [0:0] iopad_outpad ;
input [0:0] ccff_head ;
output [0:0] iopad_inpad ;
output [0:0] ccff_tail ;
input VDD ;
input VSS ;
wire [0:0] EMBEDDED_IO_HD_0_en ;
supply1 VDD ;
supply0 VSS ;
cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
.SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
.SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
.SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
.FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
.FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ,
.VDD ( VDD ) , .VSS ( VSS ) ) ;
cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ,
.VDD ( VDD ) , .VSS ( VSS ) ) ;
endmodule |
module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk ,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
ccff_tail , VDD , VSS ) ;
input [0:0] IO_ISOL_N ;
input [0:0] prog_clk ;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
input [0:0] io_outpad ;
input [0:0] ccff_head ;
output [0:0] io_inpad ;
output [0:0] ccff_tail ;
input VDD ;
input VSS ;
supply1 VDD ;
supply0 VSS ;
cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
.iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
.iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) ,
.VSS ( VSS ) ) ;
endmodule |
module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
ccff_tail , mem_out , VDD , VSS ) ;
input [0:0] prog_clk ;
input [0:0] ccff_head ;
output [0:0] ccff_tail ;
output [0:3] mem_out ;
input VDD ;
input VSS ;
supply1 VDD ;
supply0 VSS ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_54 ) ,
.CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) ,
.CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) ,
.CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) ,
.CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ,
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( ccff_head[0] ) ,
.X ( copt_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_49 ) ,
.X ( copt_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_50 ) ,
.X ( copt_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( copt_net_51 ) ,
.X ( copt_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_52 ) ,
.X ( copt_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_53 ) ,
.X ( copt_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
endmodule |
Subsets and Splits