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module cby_2__1_ ( chany_bottom_in , chany_top_in , ccff_head ,
chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ ,
left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ ,
left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ ,
left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ ,
left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ ,
left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ,
IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper ,
left_width_0_height_0__pin_1_lower , prog_clk_0_W_in , prog_clk_0_S_out ,
prog_clk_0_N_out ) ;
input [0:19] chany_bottom_in ;
input [0:19] chany_top_in ;
input [0:0] ccff_head ;
output [0:19] chany_bottom_out ;
output [0:19] chany_top_out ;
output [0:0] right_grid_pin_0_ ;
output [0:0] left_grid_pin_16_ ;
output [0:0] left_grid_pin_17_ ;
output [0:0] left_grid_pin_18_ ;
output [0:0] left_grid_pin_19_ ;
output [0:0] left_grid_pin_20_ ;
output [0:0] left_grid_pin_21_ ;
output [0:0] left_grid_pin_22_ ;
output [0:0] left_grid_pin_23_ ;
output [0:0] left_grid_pin_24_ ;
output [0:0] left_grid_pin_25_ ;
output [0:0] left_grid_pin_26_ ;
output [0:0] left_grid_pin_27_ ;
output [0:0] left_grid_pin_28_ ;
output [0:0] left_grid_pin_29_ ;
output [0:0] left_grid_pin_30_ ;
output [0:0] left_grid_pin_31_ ;
output [0:0] ccff_tail ;
input [0:0] IO_ISOL_N ;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
input [0:0] left_width_0_height_0__pin_0_ ;
output [0:0] left_width_0_height_0__pin_1_upper ;
output [0:0] left_width_0_height_0__pin_1_lower ;
input prog_clk_0_W_in ;
output prog_clk_0_S_out ;
output prog_clk_0_N_out ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:3] mux_tree_tapbuf_size10_8_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:3] mux_tree_tapbuf_size8_3_sram ;
wire [0:3] mux_tree_tapbuf_size8_4_sram ;
wire [0:3] mux_tree_tapbuf_size8_5_sram ;
wire [0:3] mux_tree_tapbuf_size8_6_sram ;
wire [0:3] mux_tree_tapbuf_size8_7_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] ,
chany_bottom_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( right_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] ,
chany_bottom_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( left_grid_pin_16_ ) , .p0 ( optlc_net_75 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] ,
chany_bottom_out[14] } ) ,
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( left_grid_pin_19_ ) , .p0 ( optlc_net_73 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] ,
chany_top_out[9] , chany_bottom_out[9] , chany_top_out[15] ,
chany_bottom_out[15] } ) ,
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( left_grid_pin_20_ ) , .p0 ( optlc_net_73 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] ,
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
chany_bottom_out[18] } ) ,
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( left_grid_pin_23_ ) , .p0 ( optlc_net_76 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
chany_bottom_out[19] } ) ,
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( left_grid_pin_24_ ) , .p0 ( optlc_net_73 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] ,
chany_bottom_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( left_grid_pin_27_ ) , .p0 ( optlc_net_74 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
chany_top_out[13] , chany_bottom_out[13] , chany_top_out[17] ,
chany_bottom_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( left_grid_pin_28_ ) , .p0 ( optlc_net_75 ) ) ;
cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] ,
chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] ,
chany_bottom_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_8_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( left_grid_pin_31_ ) , .p0 ( optlc_net_73 ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_7 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_11 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_12 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
.ccff_tail ( { ccff_tail_mid } ) ,
.mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
chany_top_out[14] , chany_bottom_out[14] } ) ,
.sram ( mux_tree_tapbuf_size8_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
.out ( left_grid_pin_17_ ) , .p0 ( optlc_net_74 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
chany_top_out[15] , chany_bottom_out[15] } ) ,
.sram ( mux_tree_tapbuf_size8_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
.out ( left_grid_pin_18_ ) , .p0 ( optlc_net_73 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] ,
chany_top_out[18] , chany_bottom_out[18] } ) ,
.sram ( mux_tree_tapbuf_size8_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
.out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] ,
chany_top_out[19] , chany_bottom_out[19] } ) ,
.sram ( mux_tree_tapbuf_size8_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( left_grid_pin_22_ ) , .p0 ( optlc_net_73 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] ,
chany_top_out[14] , chany_bottom_out[14] } ) ,
.sram ( mux_tree_tapbuf_size8_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
.out ( left_grid_pin_25_ ) , .p0 ( optlc_net_73 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] ,
chany_top_out[15] , chany_bottom_out[15] } ) ,
.sram ( mux_tree_tapbuf_size8_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
.out ( left_grid_pin_26_ ) , .p0 ( optlc_net_74 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] ,
chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] ,
chany_top_out[18] , chany_bottom_out[18] } ) ,
.sram ( mux_tree_tapbuf_size8_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
.out ( left_grid_pin_29_ ) , .p0 ( optlc_net_74 ) ) ;
cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] ,
chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] ,
chany_top_out[19] , chany_bottom_out[19] } ) ,
.sram ( mux_tree_tapbuf_size8_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
.out ( left_grid_pin_30_ ) , .p0 ( optlc_net_73 ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
.io_outpad ( left_width_0_height_0__pin_0_ ) ,
.ccff_head ( { ccff_tail_mid } ) ,
.io_inpad ( left_width_0_height_0__pin_1_lower ) ,
.ccff_tail ( ccff_tail ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
.X ( ctsbuf_net_177 ) ) ;
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
.X ( ctsbuf_net_278 ) ) ;
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) ,
.X ( chany_top_out[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) ,
.X ( chany_top_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) ,
.X ( chany_top_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) ,
.X ( chany_top_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) ,
.X ( chany_top_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) ,
.X ( chany_top_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) ,
.X ( chany_top_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) ,
.X ( chany_top_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) ,
.X ( chany_top_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) ,
.X ( chany_top_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) ,
.X ( chany_top_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) ,
.X ( chany_top_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) ,
.X ( chany_top_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) ,
.X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) ,
.X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) ,
.X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) ,
.X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) ,
.X ( chany_top_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) ,
.X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) ,
.X ( chany_top_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[0] ) ,
.X ( chany_bottom_out[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[1] ) ,
.X ( chany_bottom_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[2] ) ,
.X ( chany_bottom_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[3] ) ,
.X ( chany_bottom_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[4] ) ,
.X ( chany_bottom_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[5] ) ,
.X ( chany_bottom_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[6] ) ,
.X ( chany_bottom_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[7] ) ,
.X ( chany_bottom_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[8] ) ,
.X ( chany_bottom_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[9] ) ,
.X ( chany_bottom_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) ,
.X ( chany_bottom_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) ,
.X ( chany_bottom_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) ,
.X ( chany_bottom_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[13] ) ,
.X ( chany_bottom_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[14] ) ,
.X ( chany_bottom_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[15] ) ,
.X ( chany_bottom_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[16] ) ,
.X ( chany_bottom_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[17] ) ,
.X ( chany_bottom_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[18] ) ,
.X ( chany_bottom_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) ,
.X ( chany_bottom_out[19] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_59__58 (
.A ( left_width_0_height_0__pin_1_lower[0] ) ,
.X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
.HI ( optlc_net_73 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
.HI ( optlc_net_74 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) ,
.HI ( optlc_net_75 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) ,
.HI ( optlc_net_76 ) ) ;
sky130_fd_sc_hd__buf_6 cts_buf_3471203 ( .A ( ctsbuf_net_177 ) ,
.X ( prog_clk_0_S_out ) ) ;
sky130_fd_sc_hd__buf_6 cts_buf_3521208 ( .A ( ctsbuf_net_278 ) ,
.X ( prog_clk_0_N_out ) ) ;
endmodule |
module sb_1__0_ ( chany_top_in , top_left_grid_pin_42_ ,
top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ ,
top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ ,
top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ ,
right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ ,
right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ ,
right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ ,
right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in ,
left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in ,
Test_en_N_out , prog_clk_0_N_in , prog_clk_3_S_in , prog_clk_3_N_out ,
clk_3_S_in , clk_3_N_out ) ;
input [0:19] chany_top_in ;
input [0:0] top_left_grid_pin_42_ ;
input [0:0] top_left_grid_pin_43_ ;
input [0:0] top_left_grid_pin_44_ ;
input [0:0] top_left_grid_pin_45_ ;
input [0:0] top_left_grid_pin_46_ ;
input [0:0] top_left_grid_pin_47_ ;
input [0:0] top_left_grid_pin_48_ ;
input [0:0] top_left_grid_pin_49_ ;
input [0:19] chanx_right_in ;
input [0:0] right_bottom_grid_pin_1_ ;
input [0:0] right_bottom_grid_pin_3_ ;
input [0:0] right_bottom_grid_pin_5_ ;
input [0:0] right_bottom_grid_pin_7_ ;
input [0:0] right_bottom_grid_pin_9_ ;
input [0:0] right_bottom_grid_pin_11_ ;
input [0:0] right_bottom_grid_pin_13_ ;
input [0:0] right_bottom_grid_pin_15_ ;
input [0:0] right_bottom_grid_pin_17_ ;
input [0:19] chanx_left_in ;
input [0:0] left_bottom_grid_pin_1_ ;
input [0:0] left_bottom_grid_pin_3_ ;
input [0:0] left_bottom_grid_pin_5_ ;
input [0:0] left_bottom_grid_pin_7_ ;
input [0:0] left_bottom_grid_pin_9_ ;
input [0:0] left_bottom_grid_pin_11_ ;
input [0:0] left_bottom_grid_pin_13_ ;
input [0:0] left_bottom_grid_pin_15_ ;
input [0:0] left_bottom_grid_pin_17_ ;
input [0:0] ccff_head ;
output [0:19] chany_top_out ;
output [0:19] chanx_right_out ;
output [0:19] chanx_left_out ;
output [0:0] ccff_tail ;
input SC_IN_TOP ;
output SC_OUT_TOP ;
input Test_en_S_in ;
output Test_en_N_out ;
input prog_clk_0_N_in ;
input prog_clk_3_S_in ;
output prog_clk_3_N_out ;
input clk_3_S_in ;
output clk_3_N_out ;
wire ropt_net_119 ;
wire ropt_net_118 ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size14_0_sram ;
wire [0:3] mux_tree_tapbuf_size14_1_sram ;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
wire [0:1] mux_tree_tapbuf_size3_5_sram ;
wire [0:1] mux_tree_tapbuf_size3_6_sram ;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
wire [0:2] mux_tree_tapbuf_size7_4_sram ;
wire [0:2] mux_tree_tapbuf_size7_5_sram ;
wire [0:2] mux_tree_tapbuf_size7_6_sram ;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:3] mux_tree_tapbuf_size8_3_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size9_0_sram ;
wire [0:3] mux_tree_tapbuf_size9_1_sram ;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
sb_1__0__mux_tree_tapbuf_size8_0 mux_top_track_0 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
chanx_right_in[1] , chanx_left_out[3] , chanx_left_in[0] ,
chanx_right_out[3] } ) ,
.sram ( mux_tree_tapbuf_size8_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_8 (
.in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] ,
right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] ,
right_bottom_grid_pin_17_[0] , chanx_right_out[7] ,
chanx_right_out[17] } ) ,
.sram ( mux_tree_tapbuf_size8_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ;
sb_1__0__mux_tree_tapbuf_size8_2 mux_left_track_3 (
.in ( { chany_top_in[6] , chany_top_in[13] , chanx_left_out[5] ,
chanx_left_out[14] , left_bottom_grid_pin_3_[0] ,
left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] ,
left_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size8_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( chanx_left_out[1] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__0__mux_tree_tapbuf_size8 mux_left_track_9 (
.in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] ,
chanx_left_out[7] , chanx_left_out[17] , left_bottom_grid_pin_1_[0] ,
left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size8_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( chanx_left_out[4] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size8_mem_2 mem_left_track_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_9 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_2 (
.in ( { chany_top_out[13] , top_left_grid_pin_45_[0] ,
top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
chanx_right_in[3] , chanx_left_out[5] , chanx_right_out[5] } ) ,
.sram ( mux_tree_tapbuf_size7_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
SYNOPSYS_UNCONNECTED_19 } ) ,
.out ( chany_top_out[1] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_1 mux_top_track_4 (
.in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] ,
top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] ,
chanx_left_out[6] , chanx_right_in[7] , chanx_right_out[6] } ) ,
.sram ( mux_tree_tapbuf_size7_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 ,
SYNOPSYS_UNCONNECTED_22 } ) ,
.out ( chany_top_out[2] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_2 mux_top_track_6 (
.in ( { chany_top_out[13] , top_left_grid_pin_45_[0] ,
top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] ,
chanx_left_out[7] , chanx_right_in[11] , chanx_right_out[7] } ) ,
.sram ( mux_tree_tapbuf_size7_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 ,
SYNOPSYS_UNCONNECTED_25 } ) ,
.out ( chany_top_out[3] ) , .p0 ( optlc_net_99 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_16 (
.in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] ,
right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] ,
chanx_right_out[9] , chanx_right_out[18] } ) ,
.sram ( mux_tree_tapbuf_size7_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 ,
SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( chanx_right_out[8] ) , .p0 ( optlc_net_99 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_24 (
.in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] ,
right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_13_[0] ,
chanx_right_out[10] , chanx_right_out[19] } ) ,
.sram ( mux_tree_tapbuf_size7_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
SYNOPSYS_UNCONNECTED_31 } ) ,
.out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_17 (
.in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] ,
chanx_left_out[9] , chanx_left_out[18] , left_bottom_grid_pin_3_[0] ,
left_bottom_grid_pin_11_[0] } ) ,
.sram ( mux_tree_tapbuf_size7_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 ,
SYNOPSYS_UNCONNECTED_34 } ) ,
.out ( chanx_left_out[8] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__0__mux_tree_tapbuf_size7 mux_left_track_25 (
.in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] ,
chanx_left_out[10] , chanx_left_out[19] , left_bottom_grid_pin_5_[0] ,
left_bottom_grid_pin_13_[0] } ) ,
.sram ( mux_tree_tapbuf_size7_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 ,
SYNOPSYS_UNCONNECTED_37 } ) ,
.out ( chanx_left_out[12] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_top_track_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_24 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_17 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_25 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_8 (
.in ( { top_left_grid_pin_42_[0] , chanx_left_out[9] ,
chanx_right_in[15] , chanx_right_out[9] } ) ,
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 ,
SYNOPSYS_UNCONNECTED_40 } ) ,
.out ( chany_top_out[4] ) , .p0 ( optlc_net_99 ) ) ;
sb_1__0__mux_tree_tapbuf_size4 mux_top_track_10 (
.in ( { chany_top_out[13] , chanx_left_out[10] , chanx_right_in[19] ,
chanx_right_out[10] } ) ,
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
SYNOPSYS_UNCONNECTED_43 } ) ,
.out ( chany_top_out[5] ) , .p0 ( optlc_net_96 ) ) ;
sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_10 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 (
.in ( { top_left_grid_pin_44_[0] , chanx_left_out[11] ,
chanx_right_out[11] } ) ,
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) ,
.out ( chany_top_out[6] ) , .p0 ( optlc_net_96 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 (
.in ( { top_left_grid_pin_45_[0] , chanx_left_out[13] ,
chanx_right_out[13] } ) ,
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) ,
.out ( chany_top_out[7] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 (
.in ( { top_left_grid_pin_46_[0] , chanx_left_out[14] ,
chanx_right_out[14] } ) ,
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) ,
.out ( chany_top_out[8] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 (
.in ( { top_left_grid_pin_47_[0] , chanx_left_out[15] ,
chanx_right_out[15] } ) ,
.sram ( mux_tree_tapbuf_size3_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) ,
.out ( chany_top_out[9] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 (
.in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] ,
chanx_right_out[17] } ) ,
.sram ( mux_tree_tapbuf_size3_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 } ) ,
.out ( chany_top_out[10] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 (
.in ( { top_left_grid_pin_49_[0] , chanx_left_out[18] ,
chanx_right_out[18] } ) ,
.sram ( mux_tree_tapbuf_size3_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) ,
.out ( chany_top_out[11] ) , .p0 ( optlc_net_95 ) ) ;
sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 (
.in ( { top_left_grid_pin_42_[0] , chanx_left_out[19] ,
chanx_right_out[19] } ) ,
.sram ( mux_tree_tapbuf_size3_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) ,
.out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 (
.in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 } ) ,
.out ( chany_top_out[19] ) , .p0 ( optlc_net_99 ) ) ;
sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_0 (
.in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] ,
right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] ,
right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_17_[0] ,
chanx_right_out[3] , chanx_right_out[13] } ) ,
.sram ( mux_tree_tapbuf_size9_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 ,
SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) ,
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ;
sb_1__0__mux_tree_tapbuf_size9 mux_right_track_2 (
.in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] ,
right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] ,
right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] ,
chanx_right_out[5] , chanx_right_out[14] } ) ,
.sram ( mux_tree_tapbuf_size9_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 ,
SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) ,
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ;
sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_0 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size9_mem mem_right_track_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size14_0 mux_right_track_4 (
.in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] ,
right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] ,
right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] ,
right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] ,
right_bottom_grid_pin_13_[0] , right_bottom_grid_pin_15_[0] ,
right_bottom_grid_pin_17_[0] , chanx_right_out[6] ,
chanx_right_out[15] } ) ,
.sram ( mux_tree_tapbuf_size14_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 ,
SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) ,
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ;
sb_1__0__mux_tree_tapbuf_size14 mux_left_track_5 (
.in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] ,
chanx_left_out[6] , chanx_left_out[15] , left_bottom_grid_pin_1_[0] ,
left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] ,
left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] ,
left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_13_[0] ,
left_bottom_grid_pin_15_[0] , left_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size14_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 ,
SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) ,
.out ( chanx_left_out[2] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__0__mux_tree_tapbuf_size14_mem_0 mem_right_track_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size14_mem mem_left_track_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size6_0 mux_right_track_32 (
.in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] ,
right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_15_[0] ,
chanx_right_out[11] } ) ,
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 ,
SYNOPSYS_UNCONNECTED_78 } ) ,
.out ( chanx_right_out[16] ) , .p0 ( optlc_net_96 ) ) ;
sb_1__0__mux_tree_tapbuf_size6 mux_left_track_33 (
.in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] ,
chanx_left_out[11] , left_bottom_grid_pin_7_[0] ,
left_bottom_grid_pin_15_[0] } ) ,
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 ,
SYNOPSYS_UNCONNECTED_81 } ) ,
.out ( chanx_left_out[16] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_right_track_32 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size6_mem mem_left_track_33 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
sb_1__0__mux_tree_tapbuf_size10 mux_left_track_1 (
.in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] ,
chanx_left_out[3] , chanx_left_out[13] , left_bottom_grid_pin_1_[0] ,
left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] ,
left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 ,
SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) ,
.out ( chanx_left_out[0] ) , .p0 ( optlc_net_98 ) ) ;
sb_1__0__mux_tree_tapbuf_size10_mem mem_left_track_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) ,
.HI ( optlc_net_95 ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) ,
.X ( aps_rename_505_ ) ) ;
sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) ,
.X ( aps_rename_506_ ) ) ;
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( top_left_grid_pin_43_[0] ) ,
.X ( chany_top_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_right_in[2] ) ,
.X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_right_in[4] ) ,
.X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_right_in[5] ) ,
.X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_right_in[6] ) ,
.X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_right_in[8] ) ,
.X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_right_in[9] ) ,
.X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[10] ) ,
.X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[12] ) ,
.X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[13] ) ,
.X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[14] ) ,
.X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[16] ) ,
.X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[17] ) ,
.X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[18] ) ,
.X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[2] ) ,
.X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[3] ) ,
.X ( chany_top_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[4] ) ,
.X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[5] ) ,
.X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[6] ) ,
.X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chanx_left_in[7] ) ,
.X ( ropt_net_119 ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_left_in[8] ) ,
.X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_left_in[9] ) ,
.X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_left_in[10] ) ,
.X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_left_in[11] ) ,
.X ( chany_top_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_left_in[12] ) ,
.X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[13] ) ,
.X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[14] ) ,
.X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[15] ) ,
.X ( chany_top_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[16] ) ,
.X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[17] ) ,
.X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[18] ) ,
.X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chanx_left_in[19] ) ,
.X ( chany_top_out[14] ) ) ;
sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( ropt_net_118 ) ) ;
sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( Test_en_N_out ) ) ;
sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( Test_en_S_in ) , .Y ( BUF_net_90 ) ) ;
sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) ,
.Y ( prog_clk_3_N_out ) ) ;
sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_505_ ) ,
.Y ( BUF_net_92 ) ) ;
sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( clk_3_N_out ) ) ;
sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_506_ ) ,
.Y ( BUF_net_94 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) ,
.HI ( optlc_net_96 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) ,
.HI ( optlc_net_97 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_89 ) ,
.HI ( optlc_net_98 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_90 ) ,
.HI ( optlc_net_99 ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_118 ) ,
.X ( SC_OUT_TOP ) ) ;
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_119 ) ,
.X ( chany_top_out[17] ) ) ;
endmodule |
module cbx_1__1_ ( chanx_left_in , chanx_right_in , ccff_head ,
chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP ,
REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , prog_clk_0_N_in ,
prog_clk_0_W_out , prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out ,
prog_clk_1_S_out , prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out ,
prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out ,
prog_clk_3_W_out , clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out ,
clk_2_E_in , clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in ,
clk_3_E_in , clk_3_E_out , clk_3_W_out ) ;
input [0:19] chanx_left_in ;
input [0:19] chanx_right_in ;
input [0:0] ccff_head ;
output [0:19] chanx_left_out ;
output [0:19] chanx_right_out ;
output [0:0] bottom_grid_pin_0_ ;
output [0:0] bottom_grid_pin_1_ ;
output [0:0] bottom_grid_pin_2_ ;
output [0:0] bottom_grid_pin_3_ ;
output [0:0] bottom_grid_pin_4_ ;
output [0:0] bottom_grid_pin_5_ ;
output [0:0] bottom_grid_pin_6_ ;
output [0:0] bottom_grid_pin_7_ ;
output [0:0] bottom_grid_pin_8_ ;
output [0:0] bottom_grid_pin_9_ ;
output [0:0] bottom_grid_pin_10_ ;
output [0:0] bottom_grid_pin_11_ ;
output [0:0] bottom_grid_pin_12_ ;
output [0:0] bottom_grid_pin_13_ ;
output [0:0] bottom_grid_pin_14_ ;
output [0:0] bottom_grid_pin_15_ ;
output [0:0] ccff_tail ;
input SC_IN_TOP ;
output SC_OUT_BOT ;
input SC_IN_BOT ;
output SC_OUT_TOP ;
input REGIN_FEEDTHROUGH ;
output REGOUT_FEEDTHROUGH ;
input prog_clk_0_N_in ;
output prog_clk_0_W_out ;
input prog_clk_1_W_in ;
input prog_clk_1_E_in ;
output prog_clk_1_N_out ;
output prog_clk_1_S_out ;
input prog_clk_2_E_in ;
input prog_clk_2_W_in ;
output prog_clk_2_W_out ;
output prog_clk_2_E_out ;
input prog_clk_3_W_in ;
input prog_clk_3_E_in ;
output prog_clk_3_E_out ;
output prog_clk_3_W_out ;
input clk_1_W_in ;
input clk_1_E_in ;
output clk_1_N_out ;
output clk_1_S_out ;
input clk_2_E_in ;
input clk_2_W_in ;
output clk_2_W_out ;
output clk_2_E_out ;
input clk_3_W_in ;
input clk_3_E_in ;
output clk_3_E_out ;
output clk_3_W_out ;
wire [0:0] prog_clk ;
wire prog_clk_0 ;
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
wire [0:3] mux_tree_tapbuf_size8_3_sram ;
wire [0:3] mux_tree_tapbuf_size8_4_sram ;
wire [0:3] mux_tree_tapbuf_size8_5_sram ;
wire [0:3] mux_tree_tapbuf_size8_6_sram ;
wire [0:3] mux_tree_tapbuf_size8_7_sram ;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
assign prog_clk_0 = prog_clk[0] ;
assign prog_clk_1_E_in = prog_clk_1_W_in ;
assign prog_clk_2_W_in = prog_clk_2_E_in ;
assign prog_clk_3_E_in = prog_clk_3_W_in ;
assign clk_1_E_in = clk_1_W_in ;
assign clk_2_W_in = clk_2_E_in ;
assign clk_3_E_in = clk_3_W_in ;
cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] ,
chanx_left_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
.out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
chanx_left_out[19] } ) ,
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
.out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_74 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] ,
chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] ,
chanx_left_out[14] } ) ,
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
.out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] ,
chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] ,
chanx_left_out[17] } ) ,
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
.out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_74 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] ,
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
chanx_left_out[18] } ) ,
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
.out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[15] ,
chanx_left_out[15] } ) ,
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
.out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] ,
chanx_left_out[16] } ) ,
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
.out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[19] ,
chanx_left_out[19] } ) ,
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
.out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 (
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_4 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_8 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
chanx_right_out[13] , chanx_left_out[13] } ) ,
.sram ( mux_tree_tapbuf_size8_0_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
.out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
chanx_right_out[14] , chanx_left_out[14] } ) ,
.sram ( mux_tree_tapbuf_size8_1_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
.out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
chanx_right_out[17] , chanx_left_out[17] } ) ,
.sram ( mux_tree_tapbuf_size8_2_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
.out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] ,
chanx_right_out[18] , chanx_left_out[18] } ) ,
.sram ( mux_tree_tapbuf_size8_3_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
.out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] ,
chanx_right_out[13] , chanx_left_out[13] } ) ,
.sram ( mux_tree_tapbuf_size8_4_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
.out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] ,
chanx_right_out[14] , chanx_left_out[14] } ) ,
.sram ( mux_tree_tapbuf_size8_5_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
.out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] ,
chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
chanx_right_out[17] , chanx_left_out[17] } ) ,
.sram ( mux_tree_tapbuf_size8_6_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
.out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 (
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] ,
chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] ,
chanx_right_out[18] , chanx_left_out[18] } ) ,
.sram ( mux_tree_tapbuf_size8_7_sram ) ,
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
.out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 (
.prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) ,
.ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) ,
.ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
.mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
.X ( prog_clk[0] ) ) ;
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
.X ( ctsbuf_net_175 ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) ,
.X ( aps_rename_505_ ) ) ;
sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) ,
.X ( prog_clk_1_S_out ) ) ;
sky130_fd_sc_hd__buf_1 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) ,
.X ( net_net_69 ) ) ;
sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) ,
.X ( prog_clk_2_E_out ) ) ;
sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) ,
.X ( prog_clk_3_E_out ) ) ;
sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) ,
.X ( prog_clk_3_W_out ) ) ;
sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_70 ) ) ;
sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) ,
.X ( aps_rename_506_ ) ) ;
sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) ,
.X ( clk_2_W_out ) ) ;
sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_71 ) ) ;
sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) ,
.X ( aps_rename_507_ ) ) ;
sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) ,
.X ( clk_3_W_out ) ) ;
sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) ,
.X ( chanx_right_out[0] ) ) ;
sky130_fd_sc_hd__buf_12 FTB_18__17 ( .A ( chanx_left_in[1] ) ,
.X ( chanx_right_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) ,
.X ( chanx_right_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) ,
.X ( chanx_right_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) ,
.X ( chanx_right_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) ,
.X ( chanx_right_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) ,
.X ( chanx_right_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) ,
.X ( chanx_right_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) ,
.X ( chanx_right_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) ,
.X ( chanx_right_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) ,
.X ( chanx_right_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) ,
.X ( chanx_right_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) ,
.X ( chanx_right_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) ,
.X ( chanx_right_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) ,
.X ( chanx_right_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) ,
.X ( chanx_right_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) ,
.X ( chanx_right_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) ,
.X ( chanx_right_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) ,
.X ( chanx_right_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) ,
.X ( chanx_right_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[0] ) ,
.X ( chanx_left_out[0] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[1] ) ,
.X ( chanx_left_out[1] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[2] ) ,
.X ( chanx_left_out[2] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[3] ) ,
.X ( chanx_left_out[3] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[4] ) ,
.X ( chanx_left_out[4] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[5] ) ,
.X ( chanx_left_out[5] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[6] ) ,
.X ( chanx_left_out[6] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[7] ) ,
.X ( chanx_left_out[7] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[8] ) ,
.X ( chanx_left_out[8] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[9] ) ,
.X ( chanx_left_out[9] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[10] ) ,
.X ( chanx_left_out[10] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[11] ) ,
.X ( chanx_left_out[11] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) ,
.X ( chanx_left_out[12] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) ,
.X ( chanx_left_out[13] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) ,
.X ( chanx_left_out[14] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[15] ) ,
.X ( chanx_left_out[15] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[16] ) ,
.X ( chanx_left_out[16] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[17] ) ,
.X ( chanx_left_out[17] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) ,
.X ( chanx_left_out[18] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) ,
.X ( chanx_left_out[19] ) ) ;
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) ,
.X ( REGOUT_FEEDTHROUGH ) ) ;
sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) ,
.Y ( prog_clk_1_N_out ) ) ;
sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( aps_rename_505_ ) ,
.Y ( BUF_net_68 ) ) ;
sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( net_net_69 ) ,
.X ( prog_clk_2_W_out ) ) ;
sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( net_net_70 ) , .X ( clk_1_N_out ) ) ;
sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( net_net_71 ) , .X ( clk_2_E_out ) ) ;
sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
.HI ( optlc_net_72 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
.HI ( optlc_net_73 ) ) ;
sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) ,
.HI ( optlc_net_74 ) ) ;
sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_79 ( .A ( aps_rename_507_ ) ,
.X ( clk_3_E_out ) ) ;
sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_80 ( .A ( aps_rename_506_ ) ,
.X ( clk_1_S_out ) ) ;
sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_175 ) ,
.X ( prog_clk_0_W_out ) ) ;
endmodule |
module sb_1__2_
( chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_BOT, SC_OUT_BOT, prog_clk_0_S_in );
input [0:19] chanx_right_in;
input [0:0] right_top_grid_pin_1_;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_top_grid_pin_1_;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_BOT;
output SC_OUT_BOT;
input prog_clk_0_S_in;
wire [0:2] mux_bottom_track_11_undriven_sram_inv;
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
wire [0:1] mux_bottom_track_15_undriven_sram_inv;
wire [0:1] mux_bottom_track_17_undriven_sram_inv;
wire [0:1] mux_bottom_track_19_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_21_undriven_sram_inv;
wire [0:1] mux_bottom_track_23_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_27_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_7_undriven_sram_inv;
wire [0:2] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:2] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:3] mux_left_track_5_undriven_sram_inv;
wire [0:3] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_16_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:3] mux_right_track_4_undriven_sram_inv;
wire [0:3] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:2] mux_tree_tapbuf_size7_7_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:3] mux_tree_tapbuf_size9_2_sram;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[18] = chanx_right_in[0];
assign chany_bottom_out[17] = chanx_right_in[1];
assign chanx_left_out[3] = chanx_right_in[2];
assign chany_bottom_out[16] = chanx_right_in[3];
assign chanx_left_out[5] = chanx_right_in[4];
assign chanx_left_out[6] = chanx_right_in[5];
assign chanx_left_out[7] = chanx_right_in[6];
assign chany_bottom_out[15] = chanx_right_in[7];
assign chanx_left_out[9] = chanx_right_in[8];
assign chanx_left_out[10] = chanx_right_in[9];
assign chanx_left_out[11] = chanx_right_in[10];
assign chany_bottom_out[14] = chanx_right_in[11];
assign chanx_left_out[13] = chanx_right_in[12];
assign chanx_left_out[14] = chanx_right_in[13];
assign chanx_left_out[15] = chanx_right_in[14];
assign chanx_left_out[17] = chanx_right_in[16];
assign chanx_left_out[18] = chanx_right_in[17];
assign chanx_left_out[19] = chanx_right_in[18];
assign chany_bottom_out[19] = chanx_left_in[0];
assign chanx_right_out[3] = chanx_left_in[2];
assign chanx_right_out[5] = chanx_left_in[4];
assign chanx_right_out[6] = chanx_left_in[5];
assign chanx_right_out[7] = chanx_left_in[6];
assign chanx_right_out[9] = chanx_left_in[8];
assign chanx_right_out[10] = chanx_left_in[9];
assign chanx_right_out[11] = chanx_left_in[10];
assign chanx_right_out[13] = chanx_left_in[12];
assign chanx_right_out[14] = chanx_left_in[13];
assign chanx_right_out[15] = chanx_left_in[14];
assign chanx_right_out[17] = chanx_left_in[16];
assign chanx_right_out[18] = chanx_left_in[17];
assign chanx_right_out[19] = chanx_left_in[18];
assign SC_OUT_BOT = SC_IN_BOT;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_right_track_0
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size10_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size9
mux_right_track_2
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size9
mux_left_track_1
(
.in({ chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size9
mux_left_track_3
(
.in({ chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size9_2_sram[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size9_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
mux_tree_tapbuf_size9_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3])
);
mux_tree_tapbuf_size9_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_2_sram[0:3])
);
mux_tree_tapbuf_size14
mux_right_track_4
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size14
mux_left_track_5
(
.in({ chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:3]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size14_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
mux_tree_tapbuf_size14_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
mux_tree_tapbuf_size8
mux_right_track_8
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size8
mux_left_track_9
(
.in({ chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:3]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size8_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size7
mux_right_track_16
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:2]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size7
mux_right_track_24
(
.in({ right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size7
mux_bottom_track_1
(
.in({ chanx_right_in[2], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size7
mux_bottom_track_3
(
.in({ chanx_right_in[4], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size7
mux_bottom_track_5
(
.in({ chanx_right_in[5], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[5], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size7
mux_bottom_track_7
(
.in({ chanx_right_in[6], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[6], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]),
.out(chany_bottom_out[3])
);
mux_tree_tapbuf_size7
mux_left_track_17
(
.in({ chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:2]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size7
mux_left_track_25
(
.in({ chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size7_7_sram[0:2]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:2]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size7_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_7_sram[0:2])
);
mux_tree_tapbuf_size5
mux_right_track_32
(
.in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size5_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size4
mux_bottom_track_9
(
.in({ chanx_right_in[8], bottom_left_grid_pin_42_[0], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size4
mux_bottom_track_11
(
.in({ chanx_right_in[9], bottom_left_grid_pin_43_[0], chanx_left_in[9], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_bottom_track_11_undriven_sram_inv[0:2]),
.out(chany_bottom_out[5])
);
mux_tree_tapbuf_size4
mux_bottom_track_25
(
.in({ chanx_right_in[18:19], bottom_left_grid_pin_42_[0], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size4_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_bottom_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size3
mux_bottom_track_13
(
.in({ chanx_right_in[10], bottom_left_grid_pin_44_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
.out(chany_bottom_out[6])
);
mux_tree_tapbuf_size3
mux_bottom_track_15
(
.in({ chanx_right_in[12], bottom_left_grid_pin_45_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]),
.out(chany_bottom_out[7])
);
mux_tree_tapbuf_size3
mux_bottom_track_17
(
.in({ chanx_right_in[13], bottom_left_grid_pin_46_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size3
mux_bottom_track_19
(
.in({ chanx_right_in[14], bottom_left_grid_pin_47_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]),
.out(chany_bottom_out[9])
);
mux_tree_tapbuf_size3
mux_bottom_track_21
(
.in({ chanx_right_in[16], bottom_left_grid_pin_48_[0], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]),
.out(chany_bottom_out[10])
);
mux_tree_tapbuf_size3
mux_bottom_track_23
(
.in({ chanx_right_in[17], bottom_left_grid_pin_49_[0], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]),
.out(chany_bottom_out[11])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1])
);
mux_tree_tapbuf_size2
mux_bottom_track_27
(
.in({ chanx_right_in[15], bottom_left_grid_pin_43_[0] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]),
.out(chany_bottom_out[13])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size6
mux_left_track_33
(
.in({ chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size6_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_S_in),
.X(prog_clk_0)
);
endmodule |
module sb_1__0_
( chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, right_bottom_grid_pin_13_, right_bottom_grid_pin_15_, right_bottom_grid_pin_17_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, left_bottom_grid_pin_13_, left_bottom_grid_pin_15_, left_bottom_grid_pin_17_, ccff_head, chany_top_out, chanx_right_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_OUT_TOP, Test_en_S_in, Test_en_N_out, prog_clk_0_N_in, prog_clk_3_S_in, prog_clk_3_N_out, clk_3_S_in, clk_3_N_out );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_1_;
input [0:0] right_bottom_grid_pin_3_;
input [0:0] right_bottom_grid_pin_5_;
input [0:0] right_bottom_grid_pin_7_;
input [0:0] right_bottom_grid_pin_9_;
input [0:0] right_bottom_grid_pin_11_;
input [0:0] right_bottom_grid_pin_13_;
input [0:0] right_bottom_grid_pin_15_;
input [0:0] right_bottom_grid_pin_17_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_1_;
input [0:0] left_bottom_grid_pin_3_;
input [0:0] left_bottom_grid_pin_5_;
input [0:0] left_bottom_grid_pin_7_;
input [0:0] left_bottom_grid_pin_9_;
input [0:0] left_bottom_grid_pin_11_;
input [0:0] left_bottom_grid_pin_13_;
input [0:0] left_bottom_grid_pin_15_;
input [0:0] left_bottom_grid_pin_17_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
output SC_OUT_TOP;
input Test_en_S_in;
output Test_en_N_out;
input prog_clk_0_N_in;
input prog_clk_3_S_in;
output prog_clk_3_N_out;
input clk_3_S_in;
output clk_3_N_out;
wire [0:2] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:2] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:3] mux_left_track_5_undriven_sram_inv;
wire [0:3] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_16_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:3] mux_right_track_4_undriven_sram_inv;
wire [0:3] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_20_undriven_sram_inv;
wire [0:1] mux_top_track_22_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:1] mux_top_track_38_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_6_undriven_sram_inv;
wire [0:2] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[13] = top_left_grid_pin_43_[0];
assign chanx_left_out[3] = chanx_right_in[2];
assign chanx_left_out[5] = chanx_right_in[4];
assign chanx_left_out[6] = chanx_right_in[5];
assign chanx_left_out[7] = chanx_right_in[6];
assign chanx_left_out[9] = chanx_right_in[8];
assign chanx_left_out[10] = chanx_right_in[9];
assign chanx_left_out[11] = chanx_right_in[10];
assign chanx_left_out[13] = chanx_right_in[12];
assign chanx_left_out[14] = chanx_right_in[13];
assign chanx_left_out[15] = chanx_right_in[14];
assign chanx_left_out[17] = chanx_right_in[16];
assign chanx_left_out[18] = chanx_right_in[17];
assign chanx_left_out[19] = chanx_right_in[18];
assign chanx_right_out[3] = chanx_left_in[2];
assign chany_top_out[18] = chanx_left_in[3];
assign chanx_right_out[5] = chanx_left_in[4];
assign chanx_right_out[6] = chanx_left_in[5];
assign chanx_right_out[7] = chanx_left_in[6];
assign chany_top_out[17] = chanx_left_in[7];
assign chanx_right_out[9] = chanx_left_in[8];
assign chanx_right_out[10] = chanx_left_in[9];
assign chanx_right_out[11] = chanx_left_in[10];
assign chany_top_out[16] = chanx_left_in[11];
assign chanx_right_out[13] = chanx_left_in[12];
assign chanx_right_out[14] = chanx_left_in[13];
assign chanx_right_out[15] = chanx_left_in[14];
assign chany_top_out[15] = chanx_left_in[15];
assign chanx_right_out[17] = chanx_left_in[16];
assign chanx_right_out[18] = chanx_left_in[17];
assign chanx_right_out[19] = chanx_left_in[18];
assign chany_top_out[14] = chanx_left_in[19];
assign SC_OUT_TOP = SC_IN_TOP;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size8
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size8
mux_right_track_8
(
.in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_17_[0], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size8
mux_left_track_3
(
.in({ chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size8
mux_left_track_9
(
.in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:3]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size8_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size7
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_left_in[4] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size7
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size7
mux_top_track_6
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:2]),
.out(chany_top_out[3])
);
mux_tree_tapbuf_size7
mux_right_track_16
(
.in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_11_[0], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:2]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size7
mux_right_track_24
(
.in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_13_[0], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size7
mux_left_track_17
(
.in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:2]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size7
mux_left_track_25
(
.in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:2]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size7_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_top_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
mux_tree_tapbuf_size4
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:2]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size4
mux_top_track_10
(
.in({ top_left_grid_pin_43_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:2]),
.out(chany_top_out[5])
);
mux_tree_tapbuf_size4_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_top_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size3
mux_top_track_12
(
.in({ top_left_grid_pin_44_[0], chanx_right_in[10], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6])
);
mux_tree_tapbuf_size3
mux_top_track_14
(
.in({ top_left_grid_pin_45_[0], chanx_right_in[12], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7])
);
mux_tree_tapbuf_size3
mux_top_track_16
(
.in({ top_left_grid_pin_46_[0], chanx_right_in[13], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size3
mux_top_track_18
(
.in({ top_left_grid_pin_47_[0], chanx_right_in[14], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9])
);
mux_tree_tapbuf_size3
mux_top_track_20
(
.in({ top_left_grid_pin_48_[0], chanx_right_in[16], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_top_track_20_undriven_sram_inv[0:1]),
.out(chany_top_out[10])
);
mux_tree_tapbuf_size3
mux_top_track_22
(
.in({ top_left_grid_pin_49_[0], chanx_right_in[17], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_top_track_22_undriven_sram_inv[0:1]),
.out(chany_top_out[11])
);
mux_tree_tapbuf_size3
mux_top_track_24
(
.in({ top_left_grid_pin_42_[0], chanx_right_in[18], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size3_mem
mem_top_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1])
);
mux_tree_tapbuf_size2
mux_top_track_38
(
.in({ chanx_right_in[0], chanx_left_in[1] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_38_undriven_sram_inv[0:1]),
.out(chany_top_out[19])
);
mux_tree_tapbuf_size2_mem
mem_top_track_38
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size9
mux_right_track_0
(
.in({ chany_top_in[6], chany_top_in[13], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_13_[0], right_bottom_grid_pin_17_[0], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size9
mux_right_track_2
(
.in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_15_[0], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size9_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
mux_tree_tapbuf_size9_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3])
);
mux_tree_tapbuf_size14
mux_right_track_4
(
.in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_13_[0], right_bottom_grid_pin_15_[0], right_bottom_grid_pin_17_[0], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size14
mux_left_track_5
(
.in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_11_[0], left_bottom_grid_pin_13_[0], left_bottom_grid_pin_15_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:3]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size14_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
mux_tree_tapbuf_size14_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
mux_tree_tapbuf_size6
mux_right_track_32
(
.in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_15_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size6
mux_left_track_33
(
.in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size6_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size10
mux_left_track_1
(
.in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_13_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size10_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
sky130_fd_sc_hd__buf_4
Test_en_N_FTB01
(
.A(Test_en_S_in),
.X(Test_en_N_out)
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_N_FTB01
(
.A(prog_clk_3_S_in),
.X(prog_clk_3_N_out)
);
sky130_fd_sc_hd__buf_4
clk_3_N_FTB01
(
.A(clk_3_S_in),
.X(clk_3_N_out)
);
endmodule |
module cby_2__1_
( chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, right_grid_pin_0_, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, left_width_0_height_0__pin_0_, left_width_0_height_0__pin_1_upper, left_width_0_height_0__pin_1_lower, prog_clk_0_W_in, prog_clk_0_S_out, prog_clk_0_N_out );
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] right_grid_pin_0_;
output [0:0] left_grid_pin_16_;
output [0:0] left_grid_pin_17_;
output [0:0] left_grid_pin_18_;
output [0:0] left_grid_pin_19_;
output [0:0] left_grid_pin_20_;
output [0:0] left_grid_pin_21_;
output [0:0] left_grid_pin_22_;
output [0:0] left_grid_pin_23_;
output [0:0] left_grid_pin_24_;
output [0:0] left_grid_pin_25_;
output [0:0] left_grid_pin_26_;
output [0:0] left_grid_pin_27_;
output [0:0] left_grid_pin_28_;
output [0:0] left_grid_pin_29_;
output [0:0] left_grid_pin_30_;
output [0:0] left_grid_pin_31_;
output [0:0] ccff_tail;
input [0:0] IO_ISOL_N;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:0] left_width_0_height_0__pin_0_;
output [0:0] left_width_0_height_0__pin_1_upper;
output [0:0] left_width_0_height_0__pin_1_lower;
input prog_clk_0_W_in;
output prog_clk_0_S_out;
output prog_clk_0_N_out;
wire [0:3] mux_left_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire ccff_tail_mid;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_left_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]),
.out(right_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_3
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_pin_19_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_4
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_7
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_8
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_11
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_12
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_15
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
mux_tree_tapbuf_size10_mem
mem_left_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
mux_tree_tapbuf_size8
mux_right_ipin_1
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_2
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_5
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_6
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_9
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_10
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_13
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_14
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(left_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(left_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_W_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_S_FTB01
(
.A(prog_clk_0_W_in),
.X(prog_clk_0_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_N_FTB01
(
.A(prog_clk_0_W_in),
.X(prog_clk_0_N_out)
);
endmodule |
module sb_0__2_
( chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_OUT_BOT, prog_clk_0_E_in );
input [0:19] chanx_right_in;
input [0:0] right_top_grid_pin_1_;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_1_;
input [0:0] ccff_head;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
output SC_OUT_BOT;
input prog_clk_0_E_in;
wire [0:1] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_5_undriven_sram_inv;
wire [0:1] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:1] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:1] mux_right_track_38_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[18] = chanx_right_in[0];
assign chany_bottom_out[17] = chanx_right_in[1];
assign chany_bottom_out[16] = chanx_right_in[2];
assign chany_bottom_out[15] = chanx_right_in[3];
assign chany_bottom_out[14] = chanx_right_in[4];
assign chany_bottom_out[13] = chanx_right_in[5];
assign chany_bottom_out[11] = chanx_right_in[7];
assign chany_bottom_out[10] = chanx_right_in[8];
assign chany_bottom_out[9] = chanx_right_in[9];
assign chany_bottom_out[8] = chanx_right_in[10];
assign chany_bottom_out[7] = chanx_right_in[11];
assign chany_bottom_out[6] = chanx_right_in[12];
assign chany_bottom_out[5] = chanx_right_in[13];
assign chany_bottom_out[3] = chanx_right_in[15];
assign chany_bottom_out[1] = chanx_right_in[17];
assign chany_bottom_out[19] = chanx_right_in[19];
assign SC_OUT_BOT = SC_IN_TOP;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6
mux_right_track_0
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[18] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size6
mux_right_track_4
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size5
mux_right_track_2
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size5
mux_right_track_6
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[15] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size5_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size3
mux_right_track_8
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size3
mux_right_track_24
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size3_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size2
mux_right_track_10
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size2
mux_right_track_12
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size2
mux_right_track_14
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size2
mux_right_track_16
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2
mux_right_track_18
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[9] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size2
mux_right_track_20
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[8] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size2
mux_right_track_22
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[7] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[5] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[4] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[3] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[2] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[1] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2
mux_right_track_36
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2
mux_right_track_38
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[19] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_right_track_38_undriven_sram_inv[0:1]),
.out(chanx_right_out[19])
);
mux_tree_tapbuf_size2
mux_bottom_track_1
(
.in({ chanx_right_in[18], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size2
mux_bottom_track_5
(
.in({ chanx_right_in[16], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size2
mux_bottom_track_9
(
.in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size2
mux_bottom_track_25
(
.in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size2_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_36
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_38
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_E_in),
.X(prog_clk_0)
);
endmodule |
module cby_0__1_
( chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_0_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, right_width_0_height_0__pin_0_, right_width_0_height_0__pin_1_upper, right_width_0_height_0__pin_1_lower, prog_clk_0_E_in );
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] left_grid_pin_0_;
output [0:0] ccff_tail;
input [0:0] IO_ISOL_N;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:0] right_width_0_height_0__pin_0_;
output [0:0] right_width_0_height_0__pin_1_upper;
output [0:0] right_width_0_height_0__pin_1_lower;
input prog_clk_0_E_in;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire ccff_tail_mid;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_0_[0])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(right_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(right_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_E_in),
.X(prog_clk_0)
);
endmodule |
module cbx_1__2_
( chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, top_grid_pin_0_, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, bottom_width_0_height_0__pin_0_, bottom_width_0_height_0__pin_1_upper, bottom_width_0_height_0__pin_1_lower, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, prog_clk_0_S_in, prog_clk_0_W_out );
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] top_grid_pin_0_;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_1_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_3_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_5_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_7_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_9_;
output [0:0] bottom_grid_pin_10_;
output [0:0] bottom_grid_pin_11_;
output [0:0] bottom_grid_pin_12_;
output [0:0] bottom_grid_pin_13_;
output [0:0] bottom_grid_pin_14_;
output [0:0] bottom_grid_pin_15_;
output [0:0] ccff_tail;
input [0:0] IO_ISOL_N;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:0] bottom_width_0_height_0__pin_0_;
output [0:0] bottom_width_0_height_0__pin_1_upper;
output [0:0] bottom_width_0_height_0__pin_1_lower;
input SC_IN_TOP;
output SC_OUT_BOT;
input SC_IN_BOT;
output SC_OUT_TOP;
input prog_clk_0_S_in;
output prog_clk_0_W_out;
wire [0:3] mux_bottom_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire ccff_tail_mid;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0];
assign SC_OUT_BOT = SC_IN_TOP;
assign SC_OUT_TOP = SC_IN_BOT;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_bottom_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]),
.out(top_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_3
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_3_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_4
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_7
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_8
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_11
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_12
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_15
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
mux_tree_tapbuf_size10_mem
mem_bottom_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
mux_tree_tapbuf_size8
mux_top_ipin_1
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_2
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_5
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_6
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_9
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_10
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_13
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_14
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(bottom_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(bottom_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_S_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_W_FTB01
(
.A(prog_clk_0_S_in),
.X(prog_clk_0_W_out)
);
endmodule |
module sb_2__1_
( chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chany_bottom_out, chanx_left_out, ccff_tail, prog_clk_0_N_in );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:0] top_right_grid_pin_1_;
input [0:19] chany_bottom_in;
input [0:0] bottom_right_grid_pin_1_;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input prog_clk_0_N_in;
wire [0:2] mux_bottom_track_17_undriven_sram_inv;
wire [0:3] mux_bottom_track_1_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:2] mux_bottom_track_33_undriven_sram_inv;
wire [0:3] mux_bottom_track_3_undriven_sram_inv;
wire [0:3] mux_bottom_track_5_undriven_sram_inv;
wire [0:3] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_left_track_11_undriven_sram_inv;
wire [0:2] mux_left_track_13_undriven_sram_inv;
wire [0:2] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:2] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_16_undriven_sram_inv;
wire [0:2] mux_top_track_24_undriven_sram_inv;
wire [0:3] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:3] mux_top_track_4_undriven_sram_inv;
wire [0:3] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[3] = chany_top_in[2];
assign chany_bottom_out[5] = chany_top_in[4];
assign chany_bottom_out[6] = chany_top_in[5];
assign chany_bottom_out[7] = chany_top_in[6];
assign chany_bottom_out[9] = chany_top_in[8];
assign chany_bottom_out[10] = chany_top_in[9];
assign chany_bottom_out[11] = chany_top_in[10];
assign chany_bottom_out[13] = chany_top_in[12];
assign chany_bottom_out[14] = chany_top_in[13];
assign chany_bottom_out[15] = chany_top_in[14];
assign chany_bottom_out[17] = chany_top_in[16];
assign chany_bottom_out[18] = chany_top_in[17];
assign chany_bottom_out[19] = chany_top_in[18];
assign chany_top_out[3] = chany_bottom_in[2];
assign chany_top_out[5] = chany_bottom_in[4];
assign chany_top_out[6] = chany_bottom_in[5];
assign chany_top_out[7] = chany_bottom_in[6];
assign chany_top_out[9] = chany_bottom_in[8];
assign chany_top_out[10] = chany_bottom_in[9];
assign chany_top_out[11] = chany_bottom_in[10];
assign chany_top_out[13] = chany_bottom_in[12];
assign chany_top_out[14] = chany_bottom_in[13];
assign chany_top_out[15] = chany_bottom_in[14];
assign chany_top_out[17] = chany_bottom_in[16];
assign chany_top_out[18] = chany_bottom_in[17];
assign chany_top_out[19] = chany_bottom_in[18];
assign chanx_left_out[13] = left_bottom_grid_pin_35_[0];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size10
mux_bottom_track_1
(
.in({ chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size10_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size8
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:3]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size8
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:3]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size8
mux_bottom_track_9
(
.in({ chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size8_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size14
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:3]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size14
mux_bottom_track_5
(
.in({ chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:3]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size14_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
mux_tree_tapbuf_size14_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
mux_tree_tapbuf_size7
mux_top_track_16
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:2]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size7
mux_top_track_24
(
.in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:2]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size7
mux_bottom_track_17
(
.in({ chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size7
mux_left_track_1
(
.in({ chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size7
mux_left_track_3
(
.in({ chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size7
mux_left_track_5
(
.in({ chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size7
mux_left_track_7
(
.in({ chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size7_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
mux_tree_tapbuf_size6
mux_top_track_32
(
.in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size6
mux_bottom_track_25
(
.in({ chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[6], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size6
mux_bottom_track_33
(
.in({ chany_top_in[10], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]),
.out(chany_bottom_out[16])
);
mux_tree_tapbuf_size6_mem
mem_top_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size9
mux_bottom_track_3
(
.in({ chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size9_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
mux_tree_tapbuf_size4
mux_left_track_9
(
.in({ chany_top_in[8], chany_bottom_in[7:8], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:2]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size4
mux_left_track_11
(
.in({ chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:2]),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size4
mux_left_track_13
(
.in({ chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:2]),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size4
mux_left_track_15
(
.in({ chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:2]),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size4_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
mux_tree_tapbuf_size3
mux_left_track_17
(
.in({ chany_top_in[13], chany_bottom_in[13], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size3
mux_left_track_19
(
.in({ chany_top_in[14], chany_bottom_in[14], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size3
mux_left_track_21
(
.in({ chany_top_in[16], chany_bottom_in[16], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
mux_tree_tapbuf_size3
mux_left_track_23
(
.in({ chany_top_in[17], chany_bottom_in[17], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
mux_tree_tapbuf_size3
mux_left_track_25
(
.in({ chany_top_in[18], chany_bottom_in[18], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size3_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size2
mux_left_track_29
(
.in({ chany_top_in[19], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_31
(
.in({ chany_top_in[15], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2
mux_left_track_33
(
.in({ chany_top_in[11], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2
mux_left_track_35
(
.in({ chany_top_in[7], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2
mux_left_track_37
(
.in({ chany_top_in[3], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
mux_tree_tapbuf_size2
mux_left_track_39
(
.in({ chany_top_in[1], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
mux_tree_tapbuf_size2_mem
mem_left_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_31
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_35
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_37
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_39
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
endmodule |
module sb_2__2_
( chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_BOT, SC_OUT_BOT, prog_clk_0_S_in );
input [0:19] chany_bottom_in;
input [0:0] bottom_right_grid_pin_1_;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_top_grid_pin_1_;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_BOT;
output SC_OUT_BOT;
input prog_clk_0_S_in;
wire [0:1] mux_bottom_track_11_undriven_sram_inv;
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
wire [0:1] mux_bottom_track_15_undriven_sram_inv;
wire [0:1] mux_bottom_track_17_undriven_sram_inv;
wire [0:1] mux_bottom_track_19_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_21_undriven_sram_inv;
wire [0:1] mux_bottom_track_23_undriven_sram_inv;
wire [0:1] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_27_undriven_sram_inv;
wire [0:1] mux_bottom_track_29_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_7_undriven_sram_inv;
wire [0:1] mux_bottom_track_9_undriven_sram_inv;
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_27_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_18_sram;
wire [0:1] mux_tree_tapbuf_size2_19_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_20_sram;
wire [0:1] mux_tree_tapbuf_size2_21_sram;
wire [0:1] mux_tree_tapbuf_size2_22_sram;
wire [0:1] mux_tree_tapbuf_size2_23_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[19] = chanx_left_in[0];
assign chany_bottom_out[15] = chanx_left_in[16];
assign chany_bottom_out[16] = chanx_left_in[17];
assign chany_bottom_out[17] = chanx_left_in[18];
assign chany_bottom_out[18] = chanx_left_in[19];
assign SC_OUT_BOT = SC_IN_BOT;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6
mux_bottom_track_1
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size6
mux_bottom_track_5
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size6
mux_left_track_1
(
.in({ chany_bottom_in[19], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size6
mux_left_track_5
(
.in({ chany_bottom_in[1], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
mux_tree_tapbuf_size5
mux_bottom_track_3
(
.in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size5
mux_bottom_track_7
(
.in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[4] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]),
.out(chany_bottom_out[3])
);
mux_tree_tapbuf_size5
mux_left_track_3
(
.in({ chany_bottom_in[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size5
mux_left_track_7
(
.in({ chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
mux_tree_tapbuf_size2
mux_bottom_track_9
(
.in({ bottom_right_grid_pin_1_[0], chanx_left_in[5] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size2
mux_bottom_track_11
(
.in({ bottom_left_grid_pin_42_[0], chanx_left_in[6] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_bottom_track_11_undriven_sram_inv[0:1]),
.out(chany_bottom_out[5])
);
mux_tree_tapbuf_size2
mux_bottom_track_13
(
.in({ bottom_left_grid_pin_43_[0], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
.out(chany_bottom_out[6])
);
mux_tree_tapbuf_size2
mux_bottom_track_15
(
.in({ bottom_left_grid_pin_44_[0], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]),
.out(chany_bottom_out[7])
);
mux_tree_tapbuf_size2
mux_bottom_track_17
(
.in({ bottom_left_grid_pin_45_[0], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size2
mux_bottom_track_19
(
.in({ bottom_left_grid_pin_46_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]),
.out(chany_bottom_out[9])
);
mux_tree_tapbuf_size2
mux_bottom_track_21
(
.in({ bottom_left_grid_pin_47_[0], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]),
.out(chany_bottom_out[10])
);
mux_tree_tapbuf_size2
mux_bottom_track_23
(
.in({ bottom_left_grid_pin_48_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]),
.out(chany_bottom_out[11])
);
mux_tree_tapbuf_size2
mux_bottom_track_27
(
.in({ bottom_left_grid_pin_42_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]),
.out(chany_bottom_out[13])
);
mux_tree_tapbuf_size2
mux_bottom_track_29
(
.in({ bottom_left_grid_pin_43_[0], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]),
.out(chany_bottom_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_11
(
.in({ chany_bottom_in[4], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size2
mux_left_track_13
(
.in({ chany_bottom_in[5], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size2
mux_left_track_15
(
.in({ chany_bottom_in[6], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size2
mux_left_track_17
(
.in({ chany_bottom_in[7], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size2
mux_left_track_19
(
.in({ chany_bottom_in[8], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size2
mux_left_track_21
(
.in({ chany_bottom_in[9], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
mux_tree_tapbuf_size2
mux_left_track_23
(
.in({ chany_bottom_in[10], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
mux_tree_tapbuf_size2
mux_left_track_27
(
.in({ chany_bottom_in[12], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_left_track_27_undriven_sram_inv[0:1]),
.out(chanx_left_out[13])
);
mux_tree_tapbuf_size2
mux_left_track_29
(
.in({ chany_bottom_in[13], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size2_18_sram[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_31
(
.in({ chany_bottom_in[14], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_19_sram[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2
mux_left_track_33
(
.in({ chany_bottom_in[15], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_20_sram[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2
mux_left_track_35
(
.in({ chany_bottom_in[16], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_21_sram[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2
mux_left_track_37
(
.in({ chany_bottom_in[17], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_22_sram[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
mux_tree_tapbuf_size2
mux_left_track_39
(
.in({ chany_bottom_in[18], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_23_sram[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_31
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_20_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_35
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_21_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_37
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_22_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_39
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_23_sram[0:1])
);
mux_tree_tapbuf_size3
mux_bottom_track_25
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_49_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size3
mux_left_track_9
(
.in({ chany_bottom_in[3], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size3
mux_left_track_25
(
.in({ chany_bottom_in[11], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_S_in),
.X(prog_clk_0)
);
endmodule |
module sb_0__0_
( chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, right_bottom_grid_pin_13_, right_bottom_grid_pin_15_, right_bottom_grid_pin_17_, ccff_head, chany_top_out, chanx_right_out, ccff_tail, prog_clk_0_E_in );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_1_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_1_;
input [0:0] right_bottom_grid_pin_3_;
input [0:0] right_bottom_grid_pin_5_;
input [0:0] right_bottom_grid_pin_7_;
input [0:0] right_bottom_grid_pin_9_;
input [0:0] right_bottom_grid_pin_11_;
input [0:0] right_bottom_grid_pin_13_;
input [0:0] right_bottom_grid_pin_15_;
input [0:0] right_bottom_grid_pin_17_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:0] ccff_tail;
input prog_clk_0_E_in;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:1] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:1] mux_right_track_38_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:1] mux_top_track_4_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[19] = chanx_right_in[0];
assign chany_top_out[1] = chanx_right_in[2];
assign chany_top_out[3] = chanx_right_in[4];
assign chany_top_out[5] = chanx_right_in[6];
assign chany_top_out[6] = chanx_right_in[7];
assign chany_top_out[7] = chanx_right_in[8];
assign chany_top_out[8] = chanx_right_in[9];
assign chany_top_out[9] = chanx_right_in[10];
assign chany_top_out[10] = chanx_right_in[11];
assign chany_top_out[11] = chanx_right_in[12];
assign chany_top_out[13] = chanx_right_in[14];
assign chany_top_out[14] = chanx_right_in[15];
assign chany_top_out[15] = chanx_right_in[16];
assign chany_top_out[16] = chanx_right_in[17];
assign chany_top_out[17] = chanx_right_in[18];
assign chany_top_out[18] = chanx_right_in[19];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size2
mux_top_track_0
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[1] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:1]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size2
mux_top_track_4
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[3] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:1]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size2
mux_top_track_8
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[5] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size2
mux_top_track_24
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size2
mux_right_track_10
(
.in({ chany_top_in[4], right_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size2
mux_right_track_12
(
.in({ chany_top_in[5], right_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size2
mux_right_track_14
(
.in({ chany_top_in[6], right_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size2
mux_right_track_16
(
.in({ chany_top_in[7], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2
mux_right_track_18
(
.in({ chany_top_in[8], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size2
mux_right_track_20
(
.in({ chany_top_in[9], right_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size2
mux_right_track_22
(
.in({ chany_top_in[10], right_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ chany_top_in[12], right_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ chany_top_in[13], right_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ chany_top_in[14], right_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ chany_top_in[15], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ chany_top_in[16], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2
mux_right_track_36
(
.in({ chany_top_in[17], right_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2
mux_right_track_38
(
.in({ chany_top_in[18], right_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_right_track_38_undriven_sram_inv[0:1]),
.out(chanx_right_out[19])
);
mux_tree_tapbuf_size2_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_36
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_38
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
mux_tree_tapbuf_size6
mux_right_track_0
(
.in({ chany_top_in[19], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_13_[0], right_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size6
mux_right_track_4
(
.in({ chany_top_in[1], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_13_[0], right_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size5
mux_right_track_2
(
.in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size5
mux_right_track_6
(
.in({ chany_top_in[2], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size5_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size3
mux_right_track_8
(
.in({ chany_top_in[3], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size3
mux_right_track_24
(
.in({ chany_top_in[11], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size3_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_E_in),
.X(prog_clk_0)
);
endmodule |
module sb_2__0_
( chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, left_bottom_grid_pin_13_, left_bottom_grid_pin_15_, left_bottom_grid_pin_17_, ccff_head, chany_top_out, chanx_left_out, ccff_tail, prog_clk_0_N_in );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:0] top_right_grid_pin_1_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_1_;
input [0:0] left_bottom_grid_pin_3_;
input [0:0] left_bottom_grid_pin_5_;
input [0:0] left_bottom_grid_pin_7_;
input [0:0] left_bottom_grid_pin_9_;
input [0:0] left_bottom_grid_pin_11_;
input [0:0] left_bottom_grid_pin_13_;
input [0:0] left_bottom_grid_pin_15_;
input [0:0] left_bottom_grid_pin_17_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input prog_clk_0_N_in;
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_27_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:2] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_20_undriven_sram_inv;
wire [0:1] mux_top_track_22_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:1] mux_top_track_26_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_6_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_18_sram;
wire [0:1] mux_tree_tapbuf_size2_19_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_20_sram;
wire [0:1] mux_tree_tapbuf_size2_21_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[19] = chanx_left_in[1];
assign chany_top_out[18] = chanx_left_in[2];
assign chany_top_out[17] = chanx_left_in[3];
assign chany_top_out[16] = chanx_left_in[4];
assign chany_top_out[15] = chanx_left_in[5];
assign chany_top_out[14] = chanx_left_in[6];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:2]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size6
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size6
mux_left_track_1
(
.in({ chany_top_in[0], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_13_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size6
mux_left_track_5
(
.in({ chany_top_in[18], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_13_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
mux_tree_tapbuf_size5
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size5
mux_top_track_6
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:2]),
.out(chany_top_out[3])
);
mux_tree_tapbuf_size5
mux_left_track_3
(
.in({ chany_top_in[19], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size5
mux_left_track_7
(
.in({ chany_top_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size5_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_top_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
mux_tree_tapbuf_size3
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size3
mux_top_track_24
(
.in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size3
mux_left_track_9
(
.in({ chany_top_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size3
mux_left_track_25
(
.in({ chany_top_in[8], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size3_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size2
mux_top_track_10
(
.in({ top_left_grid_pin_43_[0], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:1]),
.out(chany_top_out[5])
);
mux_tree_tapbuf_size2
mux_top_track_12
(
.in({ top_left_grid_pin_44_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6])
);
mux_tree_tapbuf_size2
mux_top_track_14
(
.in({ top_left_grid_pin_45_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7])
);
mux_tree_tapbuf_size2
mux_top_track_16
(
.in({ top_left_grid_pin_46_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size2
mux_top_track_18
(
.in({ top_left_grid_pin_47_[0], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9])
);
mux_tree_tapbuf_size2
mux_top_track_20
(
.in({ top_left_grid_pin_48_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_top_track_20_undriven_sram_inv[0:1]),
.out(chany_top_out[10])
);
mux_tree_tapbuf_size2
mux_top_track_22
(
.in({ top_left_grid_pin_49_[0], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_top_track_22_undriven_sram_inv[0:1]),
.out(chany_top_out[11])
);
mux_tree_tapbuf_size2
mux_top_track_26
(
.in({ top_left_grid_pin_43_[0], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_top_track_26_undriven_sram_inv[0:1]),
.out(chany_top_out[13])
);
mux_tree_tapbuf_size2
mux_left_track_11
(
.in({ chany_top_in[15], left_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size2
mux_left_track_13
(
.in({ chany_top_in[14], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size2
mux_left_track_15
(
.in({ chany_top_in[13], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size2
mux_left_track_17
(
.in({ chany_top_in[12], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size2
mux_left_track_19
(
.in({ chany_top_in[11], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size2
mux_left_track_21
(
.in({ chany_top_in[10], left_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
mux_tree_tapbuf_size2
mux_left_track_23
(
.in({ chany_top_in[9], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
mux_tree_tapbuf_size2
mux_left_track_27
(
.in({ chany_top_in[7], left_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_left_track_27_undriven_sram_inv[0:1]),
.out(chanx_left_out[13])
);
mux_tree_tapbuf_size2
mux_left_track_29
(
.in({ chany_top_in[6], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_31
(
.in({ chany_top_in[5], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2
mux_left_track_33
(
.in({ chany_top_in[4], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_18_sram[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2
mux_left_track_35
(
.in({ chany_top_in[3], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_19_sram[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2
mux_left_track_37
(
.in({ chany_top_in[2], left_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size2_20_sram[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
mux_tree_tapbuf_size2
mux_left_track_39
(
.in({ chany_top_in[1], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size2_21_sram[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
mux_tree_tapbuf_size2_mem
mem_top_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_31
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_35
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_37
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_20_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_39
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_21_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
endmodule |
module cbx_1__1_
( chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, REGIN_FEEDTHROUGH, REGOUT_FEEDTHROUGH, prog_clk_0_N_in, prog_clk_0_W_out, prog_clk_1_W_in, prog_clk_1_E_in, prog_clk_1_N_out, prog_clk_1_S_out, prog_clk_2_E_in, prog_clk_2_W_in, prog_clk_2_W_out, prog_clk_2_E_out, prog_clk_3_W_in, prog_clk_3_E_in, prog_clk_3_E_out, prog_clk_3_W_out, clk_1_W_in, clk_1_E_in, clk_1_N_out, clk_1_S_out, clk_2_E_in, clk_2_W_in, clk_2_W_out, clk_2_E_out, clk_3_W_in, clk_3_E_in, clk_3_E_out, clk_3_W_out );
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_1_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_3_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_5_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_7_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_9_;
output [0:0] bottom_grid_pin_10_;
output [0:0] bottom_grid_pin_11_;
output [0:0] bottom_grid_pin_12_;
output [0:0] bottom_grid_pin_13_;
output [0:0] bottom_grid_pin_14_;
output [0:0] bottom_grid_pin_15_;
output [0:0] ccff_tail;
input SC_IN_TOP;
output SC_OUT_BOT;
input SC_IN_BOT;
output SC_OUT_TOP;
input REGIN_FEEDTHROUGH;
output REGOUT_FEEDTHROUGH;
input prog_clk_0_N_in;
output prog_clk_0_W_out;
input prog_clk_1_W_in;
input prog_clk_1_E_in;
output prog_clk_1_N_out;
output prog_clk_1_S_out;
input prog_clk_2_E_in;
input prog_clk_2_W_in;
output prog_clk_2_W_out;
output prog_clk_2_E_out;
input prog_clk_3_W_in;
input prog_clk_3_E_in;
output prog_clk_3_E_out;
output prog_clk_3_W_out;
input clk_1_W_in;
input clk_1_E_in;
output clk_1_N_out;
output clk_1_S_out;
input clk_2_E_in;
input clk_2_W_in;
output clk_2_W_out;
output clk_2_E_out;
input clk_3_W_in;
input clk_3_E_in;
output clk_3_E_out;
output clk_3_W_out;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign SC_OUT_BOT = SC_IN_TOP;
assign SC_OUT_TOP = SC_IN_BOT;
assign REGOUT_FEEDTHROUGH = REGIN_FEEDTHROUGH;
assign prog_clk_0 = prog_clk;
assign prog_clk_1_W_in = prog_clk_1_E_in;
assign prog_clk_2_E_in = prog_clk_2_W_in;
assign prog_clk_3_W_in = prog_clk_3_E_in;
assign clk_1_W_in = clk_1_E_in;
assign clk_2_E_in = clk_2_W_in;
assign clk_3_W_in = clk_3_E_in;
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_3
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_3_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_4
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_7
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_8
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_11
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_12
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_15
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size8
mux_top_ipin_1
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_2
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_5
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_6
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_9
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_10
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_13
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_14
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_W_FTB01
(
.A(prog_clk_0_N_in),
.X(prog_clk_0_W_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_1_N_FTB01
(
.A(prog_clk_1_W_in),
.X(prog_clk_1_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_1_S_FTB01
(
.A(prog_clk_1_W_in),
.X(prog_clk_1_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_W_FTB01
(
.A(prog_clk_2_E_in),
.X(prog_clk_2_W_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_E_FTB01
(
.A(prog_clk_2_E_in),
.X(prog_clk_2_E_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_E_FTB01
(
.A(prog_clk_3_W_in),
.X(prog_clk_3_E_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_W_FTB01
(
.A(prog_clk_3_W_in),
.X(prog_clk_3_W_out)
);
sky130_fd_sc_hd__buf_4
clk_1_N_FTB01
(
.A(clk_1_W_in),
.X(clk_1_N_out)
);
sky130_fd_sc_hd__buf_4
clk_1_S_FTB01
(
.A(clk_1_W_in),
.X(clk_1_S_out)
);
sky130_fd_sc_hd__buf_4
clk_2_W_FTB01
(
.A(clk_2_E_in),
.X(clk_2_W_out)
);
sky130_fd_sc_hd__buf_4
clk_2_E_FTB01
(
.A(clk_2_E_in),
.X(clk_2_E_out)
);
sky130_fd_sc_hd__buf_4
clk_3_E_FTB01
(
.A(clk_3_W_in),
.X(clk_3_E_out)
);
sky130_fd_sc_hd__buf_4
clk_3_W_FTB01
(
.A(clk_3_W_in),
.X(clk_3_W_out)
);
endmodule |
module cby_1__1_
( chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, Test_en_S_in, Test_en_E_in, Test_en_W_in, Test_en_N_out, Test_en_W_out, Test_en_E_out, prog_clk_0_W_in, prog_clk_0_S_out, prog_clk_0_N_out, prog_clk_2_N_in, prog_clk_2_S_in, prog_clk_2_S_out, prog_clk_2_N_out, prog_clk_3_S_in, prog_clk_3_N_in, prog_clk_3_N_out, prog_clk_3_S_out, clk_2_N_in, clk_2_S_in, clk_2_S_out, clk_2_N_out, clk_3_S_in, clk_3_N_in, clk_3_N_out, clk_3_S_out );
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] left_grid_pin_16_;
output [0:0] left_grid_pin_17_;
output [0:0] left_grid_pin_18_;
output [0:0] left_grid_pin_19_;
output [0:0] left_grid_pin_20_;
output [0:0] left_grid_pin_21_;
output [0:0] left_grid_pin_22_;
output [0:0] left_grid_pin_23_;
output [0:0] left_grid_pin_24_;
output [0:0] left_grid_pin_25_;
output [0:0] left_grid_pin_26_;
output [0:0] left_grid_pin_27_;
output [0:0] left_grid_pin_28_;
output [0:0] left_grid_pin_29_;
output [0:0] left_grid_pin_30_;
output [0:0] left_grid_pin_31_;
output [0:0] ccff_tail;
input Test_en_S_in;
input Test_en_E_in;
input Test_en_W_in;
output Test_en_N_out;
output Test_en_W_out;
output Test_en_E_out;
input prog_clk_0_W_in;
output prog_clk_0_S_out;
output prog_clk_0_N_out;
input prog_clk_2_N_in;
input prog_clk_2_S_in;
output prog_clk_2_S_out;
output prog_clk_2_N_out;
input prog_clk_3_S_in;
input prog_clk_3_N_in;
output prog_clk_3_N_out;
output prog_clk_3_S_out;
input clk_2_N_in;
input clk_2_S_in;
output clk_2_S_out;
output clk_2_N_out;
input clk_3_S_in;
input clk_3_N_in;
output clk_3_N_out;
output clk_3_S_out;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign Test_en_S_in = Test_en_E_in;
assign Test_en_E_in = Test_en_W_in;
assign prog_clk_0 = prog_clk;
assign prog_clk_2_N_in = prog_clk_2_S_in;
assign prog_clk_3_S_in = prog_clk_3_N_in;
assign clk_2_N_in = clk_2_S_in;
assign clk_3_S_in = clk_3_N_in;
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_3
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_pin_19_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_4
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_7
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_8
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_11
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_12
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_15
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size8
mux_right_ipin_1
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_2
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_5
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_6
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_9
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_10
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_13
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_14
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
sky130_fd_sc_hd__buf_4
Test_en_N_FTB01
(
.A(Test_en_S_in),
.X(Test_en_N_out)
);
sky130_fd_sc_hd__buf_4
Test_en_W_FTB01
(
.A(Test_en_S_in),
.X(Test_en_W_out)
);
sky130_fd_sc_hd__buf_4
Test_en_E_FTB01
(
.A(Test_en_S_in),
.X(Test_en_E_out)
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_W_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_S_FTB01
(
.A(prog_clk_0_W_in),
.X(prog_clk_0_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_N_FTB01
(
.A(prog_clk_0_W_in),
.X(prog_clk_0_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_S_FTB01
(
.A(prog_clk_2_N_in),
.X(prog_clk_2_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_N_FTB01
(
.A(prog_clk_2_N_in),
.X(prog_clk_2_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_N_FTB01
(
.A(prog_clk_3_S_in),
.X(prog_clk_3_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_S_FTB01
(
.A(prog_clk_3_S_in),
.X(prog_clk_3_S_out)
);
sky130_fd_sc_hd__buf_4
clk_2_S_FTB01
(
.A(clk_2_N_in),
.X(clk_2_S_out)
);
sky130_fd_sc_hd__buf_4
clk_2_N_FTB01
(
.A(clk_2_N_in),
.X(clk_2_N_out)
);
sky130_fd_sc_hd__buf_4
clk_3_N_FTB01
(
.A(clk_3_S_in),
.X(clk_3_N_out)
);
sky130_fd_sc_hd__buf_4
clk_3_S_FTB01
(
.A(clk_3_S_in),
.X(clk_3_S_out)
);
endmodule |
module sb_0__1_
( chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, ccff_tail, prog_clk_0_E_in );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_1_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_1_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:0] ccff_tail;
input prog_clk_0_E_in;
wire [0:2] mux_bottom_track_17_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_33_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_10_undriven_sram_inv;
wire [0:2] mux_right_track_12_undriven_sram_inv;
wire [0:2] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:2] mux_right_track_8_undriven_sram_inv;
wire [0:2] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_16_undriven_sram_inv;
wire [0:2] mux_top_track_24_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_6_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:2] mux_tree_tapbuf_size5_4_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[3] = chany_top_in[2];
assign chany_bottom_out[5] = chany_top_in[4];
assign chany_bottom_out[6] = chany_top_in[5];
assign chany_bottom_out[7] = chany_top_in[6];
assign chany_bottom_out[9] = chany_top_in[8];
assign chany_bottom_out[10] = chany_top_in[9];
assign chany_bottom_out[11] = chany_top_in[10];
assign chany_bottom_out[13] = chany_top_in[12];
assign chany_bottom_out[14] = chany_top_in[13];
assign chany_bottom_out[15] = chany_top_in[14];
assign chany_bottom_out[17] = chany_top_in[16];
assign chany_bottom_out[18] = chany_top_in[17];
assign chany_bottom_out[19] = chany_top_in[18];
assign chanx_right_out[19] = right_bottom_grid_pin_41_[0];
assign chany_top_out[3] = chany_bottom_in[2];
assign chany_top_out[5] = chany_bottom_in[4];
assign chany_top_out[6] = chany_bottom_in[5];
assign chany_top_out[7] = chany_bottom_in[6];
assign chany_top_out[9] = chany_bottom_in[8];
assign chany_top_out[10] = chany_bottom_in[9];
assign chany_top_out[11] = chany_bottom_in[10];
assign chany_top_out[13] = chany_bottom_in[12];
assign chany_top_out[14] = chany_bottom_in[13];
assign chany_top_out[15] = chany_bottom_in[14];
assign chany_top_out[17] = chany_bottom_in[16];
assign chany_top_out[18] = chany_bottom_in[17];
assign chany_top_out[19] = chany_bottom_in[18];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6
mux_top_track_0
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:2]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size6
mux_top_track_4
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size6
mux_top_track_8
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:2]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size6
mux_right_track_0
(
.in({ chany_top_in[2], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size6
mux_bottom_track_1
(
.in({ chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size6
mux_bottom_track_5
(
.in({ chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size6
mux_bottom_track_9
(
.in({ chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size6_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2])
);
mux_tree_tapbuf_size5
mux_top_track_2
(
.in({ chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size5
mux_top_track_16
(
.in({ chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:2]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size5
mux_bottom_track_3
(
.in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size5
mux_bottom_track_17
(
.in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size5
mux_bottom_track_25
(
.in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size5_4_sram[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size5_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_4_sram[0:2])
);
mux_tree_tapbuf_size4
mux_top_track_24
(
.in({ chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:2]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size4
mux_top_track_32
(
.in({ chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size4
mux_right_track_8
(
.in({ chany_top_in[7:8], right_bottom_grid_pin_34_[0], chany_bottom_in[8] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:2]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size4
mux_right_track_10
(
.in({ chany_top_in[9], chany_top_in[11], right_bottom_grid_pin_35_[0], chany_bottom_in[9] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:2]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size4
mux_right_track_12
(
.in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_36_[0], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:2]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size4
mux_right_track_14
(
.in({ chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_37_[0], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:2]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size4
mux_right_track_24
(
.in({ chany_top_in[18], right_bottom_grid_pin_34_[0], chany_bottom_in[18:19] }),
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size4_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_top_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2])
);
mux_tree_tapbuf_size7
mux_right_track_2
(
.in({ chany_top_in[0], chany_top_in[4], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size7
mux_right_track_4
(
.in({ chany_top_in[1], chany_top_in[5], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[5] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size7
mux_right_track_6
(
.in({ chany_top_in[3], chany_top_in[6], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size7_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size3
mux_right_track_16
(
.in({ chany_top_in[13], right_bottom_grid_pin_38_[0], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size3
mux_right_track_18
(
.in({ chany_top_in[14], right_bottom_grid_pin_39_[0], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size3
mux_right_track_20
(
.in({ chany_top_in[16], right_bottom_grid_pin_40_[0], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size3
mux_right_track_22
(
.in({ chany_top_in[17], right_bottom_grid_pin_41_[0], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size3
mux_bottom_track_33
(
.in({ chany_top_in[10], chanx_right_in[6], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:1]),
.out(chany_bottom_out[16])
);
mux_tree_tapbuf_size3_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[15] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[7] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[3] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[1] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2
mux_right_track_36
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_36
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_E_in),
.X(prog_clk_0)
);
endmodule |
module logical_tile_clb_mode_default__fle(prog_clk,
Test_en,
fle_in,
fle_reg_in,
fle_sc_in,
fle_clk,
ccff_head,
fle_out,
fle_reg_out,
fle_sc_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:3] fle_in;
//
input [0:0] fle_reg_in;
//
input [0:0] fle_sc_in;
//
input [0:0] fle_clk;
//
input [0:0] ccff_head;
//
output [0:1] fle_out;
//
output [0:0] fle_reg_out;
//
output [0:0] fle_sc_out;
//
output [0:0] ccff_tail;
//
wire [0:3] fle_in;
wire [0:0] fle_reg_in;
wire [0:0] fle_sc_in;
wire [0:0] fle_clk;
wire [0:1] fle_out;
wire [0:0] fle_reg_out;
wire [0:0] fle_sc_out;
//
//
//
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
//
//
//
//
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fabric_in({direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0]}),
.fabric_reg_in(direct_interc_8_out[0]),
.fabric_sc_in(direct_interc_9_out[0]),
.fabric_clk(direct_interc_10_out[0]),
.ccff_head(ccff_head[0]),
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]),
.fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out[0]),
.fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
.ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
.out(fle_out[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
.out(fle_out[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out[0]),
.out(fle_reg_out[0]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
.out(fle_sc_out[0]));
direct_interc direct_interc_4_ (
.in(fle_in[0]),
.out(direct_interc_4_out[0]));
direct_interc direct_interc_5_ (
.in(fle_in[1]),
.out(direct_interc_5_out[0]));
direct_interc direct_interc_6_ (
.in(fle_in[2]),
.out(direct_interc_6_out[0]));
direct_interc direct_interc_7_ (
.in(fle_in[3]),
.out(direct_interc_7_out[0]));
direct_interc direct_interc_8_ (
.in(fle_reg_in[0]),
.out(direct_interc_8_out[0]));
direct_interc direct_interc_9_ (
.in(fle_sc_in[0]),
.out(direct_interc_9_out[0]));
direct_interc direct_interc_10_ (
.in(fle_clk[0]),
.out(direct_interc_10_out[0]));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(Test_en,
ff_D,
ff_DI,
ff_Q,
ff_clk);
//
input [0:0] Test_en;
//
input [0:0] ff_D;
//
input [0:0] ff_DI;
//
output [0:0] ff_Q;
//
input [0:0] ff_clk;
//
wire [0:0] ff_D;
wire [0:0] ff_DI;
wire [0:0] ff_Q;
wire [0:0] ff_clk;
//
//
//
//
//
//
//
sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ (
.SCE(Test_en[0]),
.D(ff_D[0]),
.SCD(ff_DI[0]),
.CLK(ff_clk[0]),
.Q(ff_Q[0]));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_clk,
Test_en,
fabric_in,
fabric_reg_in,
fabric_sc_in,
fabric_clk,
ccff_head,
fabric_out,
fabric_reg_out,
fabric_sc_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:3] fabric_in;
//
input [0:0] fabric_reg_in;
//
input [0:0] fabric_sc_in;
//
input [0:0] fabric_clk;
//
input [0:0] ccff_head;
//
output [0:1] fabric_out;
//
output [0:0] fabric_reg_out;
//
output [0:0] fabric_sc_out;
//
output [0:0] ccff_tail;
//
wire [0:3] fabric_in;
wire [0:0] fabric_reg_in;
wire [0:0] fabric_sc_in;
wire [0:0] fabric_clk;
wire [0:1] fabric_out;
wire [0:0] fabric_reg_out;
wire [0:0] fabric_sc_out;
//
//
//
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
wire [0:1] mux_fabric_out_0_undriven_sram_inv;
wire [0:1] mux_fabric_out_1_undriven_sram_inv;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv;
wire [0:1] mux_ff_1_D_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
wire [0:1] mux_tree_size2_1_sram;
wire [0:0] mux_tree_size2_2_out;
wire [0:1] mux_tree_size2_2_sram;
wire [0:0] mux_tree_size2_3_out;
wire [0:1] mux_tree_size2_3_sram;
wire [0:0] mux_tree_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_size2_mem_2_ccff_tail;
//
//
//
//
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
.prog_clk(prog_clk[0]),
.frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}),
.ccff_head(ccff_head[0]),
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
.Test_en(Test_en[0]),
.ff_D(mux_tree_size2_2_out[0]),
.ff_DI(direct_interc_6_out[0]),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.ff_clk(direct_interc_7_out[0]));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
.Test_en(Test_en[0]),
.ff_D(mux_tree_size2_3_out[0]),
.ff_DI(direct_interc_8_out[0]),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.ff_clk(direct_interc_9_out[0]));
mux_tree_size2 mux_fabric_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_fabric_out_0_undriven_sram_inv[0:1]),
.out(fabric_out[0]));
mux_tree_size2 mux_fabric_out_1 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
.sram(mux_tree_size2_1_sram[0:1]),
.sram_inv(mux_fabric_out_1_undriven_sram_inv[0:1]),
.out(fabric_out[1]));
mux_tree_size2 mux_ff_0_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in[0]}),
.sram(mux_tree_size2_2_sram[0:1]),
.sram_inv(mux_ff_0_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_2_out[0]));
mux_tree_size2 mux_ff_1_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]}),
.sram(mux_tree_size2_3_sram[0:1]),
.sram_inv(mux_ff_1_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_3_out[0]));
mux_tree_size2_mem mem_fabric_out_0 (
.prog_clk(prog_clk[0]),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_size2_0_sram[0:1]));
mux_tree_size2_mem mem_fabric_out_1 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_size2_1_sram[0:1]));
mux_tree_size2_mem mem_ff_0_D_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_size2_2_sram[0:1]));
mux_tree_size2_mem mem_ff_1_D_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_size2_3_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.out(fabric_reg_out[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.out(fabric_sc_out[0]));
direct_interc direct_interc_2_ (
.in(fabric_in[0]),
.out(direct_interc_2_out[0]));
direct_interc direct_interc_3_ (
.in(fabric_in[1]),
.out(direct_interc_3_out[0]));
direct_interc direct_interc_4_ (
.in(fabric_in[2]),
.out(direct_interc_4_out[0]));
direct_interc direct_interc_5_ (
.in(fabric_in[3]),
.out(direct_interc_5_out[0]));
direct_interc direct_interc_6_ (
.in(fabric_sc_in[0]),
.out(direct_interc_6_out[0]));
direct_interc direct_interc_7_ (
.in(fabric_clk[0]),
.out(direct_interc_7_out[0]));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.out(direct_interc_8_out[0]));
direct_interc direct_interc_9_ (
.in(fabric_clk[0]),
.out(direct_interc_9_out[0]));
endmodule |
module logical_tile_clb_mode_clb_(prog_clk,
Test_en,
clb_I0,
clb_I0i,
clb_I1,
clb_I1i,
clb_I2,
clb_I2i,
clb_I3,
clb_I3i,
clb_I4,
clb_I4i,
clb_I5,
clb_I5i,
clb_I6,
clb_I6i,
clb_I7,
clb_I7i,
clb_reg_in,
clb_sc_in,
clb_clk,
ccff_head,
clb_O,
clb_reg_out,
clb_sc_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:2] clb_I0;
//
input [0:0] clb_I0i;
//
input [0:2] clb_I1;
//
input [0:0] clb_I1i;
//
input [0:2] clb_I2;
//
input [0:0] clb_I2i;
//
input [0:2] clb_I3;
//
input [0:0] clb_I3i;
//
input [0:2] clb_I4;
//
input [0:0] clb_I4i;
//
input [0:2] clb_I5;
//
input [0:0] clb_I5i;
//
input [0:2] clb_I6;
//
input [0:0] clb_I6i;
//
input [0:2] clb_I7;
//
input [0:0] clb_I7i;
//
input [0:0] clb_reg_in;
//
input [0:0] clb_sc_in;
//
input [0:0] clb_clk;
//
input [0:0] ccff_head;
//
output [0:15] clb_O;
//
output [0:0] clb_reg_out;
//
output [0:0] clb_sc_out;
//
output [0:0] ccff_tail;
//
wire [0:2] clb_I0;
wire [0:0] clb_I0i;
wire [0:2] clb_I1;
wire [0:0] clb_I1i;
wire [0:2] clb_I2;
wire [0:0] clb_I2i;
wire [0:2] clb_I3;
wire [0:0] clb_I3i;
wire [0:2] clb_I4;
wire [0:0] clb_I4i;
wire [0:2] clb_I5;
wire [0:0] clb_I5i;
wire [0:2] clb_I6;
wire [0:0] clb_I6i;
wire [0:2] clb_I7;
wire [0:0] clb_I7i;
wire [0:0] clb_reg_in;
wire [0:0] clb_sc_in;
wire [0:0] clb_clk;
wire [0:15] clb_O;
wire [0:0] clb_reg_out;
wire [0:0] clb_sc_out;
//
//
//
wire [0:0] direct_interc_18_out;
wire [0:0] direct_interc_19_out;
wire [0:0] direct_interc_20_out;
wire [0:0] direct_interc_21_out;
wire [0:0] direct_interc_22_out;
wire [0:0] direct_interc_23_out;
wire [0:0] direct_interc_24_out;
wire [0:0] direct_interc_25_out;
wire [0:0] direct_interc_26_out;
wire [0:0] direct_interc_27_out;
wire [0:0] direct_interc_28_out;
wire [0:0] direct_interc_29_out;
wire [0:0] direct_interc_30_out;
wire [0:0] direct_interc_31_out;
wire [0:0] direct_interc_32_out;
wire [0:0] direct_interc_33_out;
wire [0:0] direct_interc_34_out;
wire [0:0] direct_interc_35_out;
wire [0:0] direct_interc_36_out;
wire [0:0] direct_interc_37_out;
wire [0:0] direct_interc_38_out;
wire [0:0] direct_interc_39_out;
wire [0:0] direct_interc_40_out;
wire [0:0] direct_interc_41_out;
wire [0:0] direct_interc_42_out;
wire [0:0] direct_interc_43_out;
wire [0:0] direct_interc_44_out;
wire [0:0] direct_interc_45_out;
wire [0:0] direct_interc_46_out;
wire [0:0] direct_interc_47_out;
wire [0:0] direct_interc_48_out;
wire [0:0] direct_interc_49_out;
wire [0:0] direct_interc_50_out;
wire [0:0] direct_interc_51_out;
wire [0:0] direct_interc_52_out;
wire [0:0] direct_interc_53_out;
wire [0:0] direct_interc_54_out;
wire [0:0] direct_interc_55_out;
wire [0:0] direct_interc_56_out;
wire [0:0] direct_interc_57_out;
wire [0:0] direct_interc_58_out;
wire [0:0] direct_interc_59_out;
wire [0:0] direct_interc_60_out;
wire [0:0] direct_interc_61_out;
wire [0:0] direct_interc_62_out;
wire [0:0] direct_interc_63_out;
wire [0:0] direct_interc_64_out;
wire [0:0] direct_interc_65_out;
wire [0:0] direct_interc_66_out;
wire [0:0] direct_interc_67_out;
wire [0:0] direct_interc_68_out;
wire [0:0] direct_interc_69_out;
wire [0:0] direct_interc_70_out;
wire [0:0] direct_interc_71_out;
wire [0:0] direct_interc_72_out;
wire [0:0] direct_interc_73_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out;
wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
//
//
//
//
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_18_out[0], direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0]}),
.fle_reg_in(direct_interc_22_out[0]),
.fle_sc_in(direct_interc_23_out[0]),
.fle_clk(direct_interc_24_out[0]),
.ccff_head(ccff_head[0]),
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_0_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_25_out[0], direct_interc_26_out[0], direct_interc_27_out[0], direct_interc_28_out[0]}),
.fle_reg_in(direct_interc_29_out[0]),
.fle_sc_in(direct_interc_30_out[0]),
.fle_clk(direct_interc_31_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_1_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_32_out[0], direct_interc_33_out[0], direct_interc_34_out[0], direct_interc_35_out[0]}),
.fle_reg_in(direct_interc_36_out[0]),
.fle_sc_in(direct_interc_37_out[0]),
.fle_clk(direct_interc_38_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_2_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_39_out[0], direct_interc_40_out[0], direct_interc_41_out[0], direct_interc_42_out[0]}),
.fle_reg_in(direct_interc_43_out[0]),
.fle_sc_in(direct_interc_44_out[0]),
.fle_clk(direct_interc_45_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_3_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}),
.fle_reg_in(direct_interc_50_out[0]),
.fle_sc_in(direct_interc_51_out[0]),
.fle_clk(direct_interc_52_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_4_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_53_out[0], direct_interc_54_out[0], direct_interc_55_out[0], direct_interc_56_out[0]}),
.fle_reg_in(direct_interc_57_out[0]),
.fle_sc_in(direct_interc_58_out[0]),
.fle_clk(direct_interc_59_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_5_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_60_out[0], direct_interc_61_out[0], direct_interc_62_out[0], direct_interc_63_out[0]}),
.fle_reg_in(direct_interc_64_out[0]),
.fle_sc_in(direct_interc_65_out[0]),
.fle_clk(direct_interc_66_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_6_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_67_out[0], direct_interc_68_out[0], direct_interc_69_out[0], direct_interc_70_out[0]}),
.fle_reg_in(direct_interc_71_out[0]),
.fle_sc_in(direct_interc_72_out[0]),
.fle_clk(direct_interc_73_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_7_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
.ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[1]),
.out(clb_O[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[0]),
.out(clb_O[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[1]),
.out(clb_O[2]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[0]),
.out(clb_O[3]));
direct_interc direct_interc_4_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[1]),
.out(clb_O[4]));
direct_interc direct_interc_5_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[0]),
.out(clb_O[5]));
direct_interc direct_interc_6_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[1]),
.out(clb_O[6]));
direct_interc direct_interc_7_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[0]),
.out(clb_O[7]));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_4_fle_out[1]),
.out(clb_O[8]));
direct_interc direct_interc_9_ (
.in(logical_tile_clb_mode_default__fle_4_fle_out[0]),
.out(clb_O[9]));
direct_interc direct_interc_10_ (
.in(logical_tile_clb_mode_default__fle_5_fle_out[1]),
.out(clb_O[10]));
direct_interc direct_interc_11_ (
.in(logical_tile_clb_mode_default__fle_5_fle_out[0]),
.out(clb_O[11]));
direct_interc direct_interc_12_ (
.in(logical_tile_clb_mode_default__fle_6_fle_out[1]),
.out(clb_O[12]));
direct_interc direct_interc_13_ (
.in(logical_tile_clb_mode_default__fle_6_fle_out[0]),
.out(clb_O[13]));
direct_interc direct_interc_14_ (
.in(logical_tile_clb_mode_default__fle_7_fle_out[1]),
.out(clb_O[14]));
direct_interc direct_interc_15_ (
.in(logical_tile_clb_mode_default__fle_7_fle_out[0]),
.out(clb_O[15]));
direct_interc direct_interc_16_ (
.in(logical_tile_clb_mode_default__fle_7_fle_reg_out[0]),
.out(clb_reg_out[0]));
direct_interc direct_interc_17_ (
.in(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
.out(clb_sc_out[0]));
direct_interc direct_interc_18_ (
.in(clb_I0[0]),
.out(direct_interc_18_out[0]));
direct_interc direct_interc_19_ (
.in(clb_I0[1]),
.out(direct_interc_19_out[0]));
direct_interc direct_interc_20_ (
.in(clb_I0[2]),
.out(direct_interc_20_out[0]));
direct_interc direct_interc_21_ (
.in(clb_I0i[0]),
.out(direct_interc_21_out[0]));
direct_interc direct_interc_22_ (
.in(clb_reg_in[0]),
.out(direct_interc_22_out[0]));
direct_interc direct_interc_23_ (
.in(clb_sc_in[0]),
.out(direct_interc_23_out[0]));
direct_interc direct_interc_24_ (
.in(clb_clk[0]),
.out(direct_interc_24_out[0]));
direct_interc direct_interc_25_ (
.in(clb_I1[0]),
.out(direct_interc_25_out[0]));
direct_interc direct_interc_26_ (
.in(clb_I1[1]),
.out(direct_interc_26_out[0]));
direct_interc direct_interc_27_ (
.in(clb_I1[2]),
.out(direct_interc_27_out[0]));
direct_interc direct_interc_28_ (
.in(clb_I1i[0]),
.out(direct_interc_28_out[0]));
direct_interc direct_interc_29_ (
.in(logical_tile_clb_mode_default__fle_0_fle_reg_out[0]),
.out(direct_interc_29_out[0]));
direct_interc direct_interc_30_ (
.in(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
.out(direct_interc_30_out[0]));
direct_interc direct_interc_31_ (
.in(clb_clk[0]),
.out(direct_interc_31_out[0]));
direct_interc direct_interc_32_ (
.in(clb_I2[0]),
.out(direct_interc_32_out[0]));
direct_interc direct_interc_33_ (
.in(clb_I2[1]),
.out(direct_interc_33_out[0]));
direct_interc direct_interc_34_ (
.in(clb_I2[2]),
.out(direct_interc_34_out[0]));
direct_interc direct_interc_35_ (
.in(clb_I2i[0]),
.out(direct_interc_35_out[0]));
direct_interc direct_interc_36_ (
.in(logical_tile_clb_mode_default__fle_1_fle_reg_out[0]),
.out(direct_interc_36_out[0]));
direct_interc direct_interc_37_ (
.in(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
.out(direct_interc_37_out[0]));
direct_interc direct_interc_38_ (
.in(clb_clk[0]),
.out(direct_interc_38_out[0]));
direct_interc direct_interc_39_ (
.in(clb_I3[0]),
.out(direct_interc_39_out[0]));
direct_interc direct_interc_40_ (
.in(clb_I3[1]),
.out(direct_interc_40_out[0]));
direct_interc direct_interc_41_ (
.in(clb_I3[2]),
.out(direct_interc_41_out[0]));
direct_interc direct_interc_42_ (
.in(clb_I3i[0]),
.out(direct_interc_42_out[0]));
direct_interc direct_interc_43_ (
.in(logical_tile_clb_mode_default__fle_2_fle_reg_out[0]),
.out(direct_interc_43_out[0]));
direct_interc direct_interc_44_ (
.in(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
.out(direct_interc_44_out[0]));
direct_interc direct_interc_45_ (
.in(clb_clk[0]),
.out(direct_interc_45_out[0]));
direct_interc direct_interc_46_ (
.in(clb_I4[0]),
.out(direct_interc_46_out[0]));
direct_interc direct_interc_47_ (
.in(clb_I4[1]),
.out(direct_interc_47_out[0]));
direct_interc direct_interc_48_ (
.in(clb_I4[2]),
.out(direct_interc_48_out[0]));
direct_interc direct_interc_49_ (
.in(clb_I4i[0]),
.out(direct_interc_49_out[0]));
direct_interc direct_interc_50_ (
.in(logical_tile_clb_mode_default__fle_3_fle_reg_out[0]),
.out(direct_interc_50_out[0]));
direct_interc direct_interc_51_ (
.in(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
.out(direct_interc_51_out[0]));
direct_interc direct_interc_52_ (
.in(clb_clk[0]),
.out(direct_interc_52_out[0]));
direct_interc direct_interc_53_ (
.in(clb_I5[0]),
.out(direct_interc_53_out[0]));
direct_interc direct_interc_54_ (
.in(clb_I5[1]),
.out(direct_interc_54_out[0]));
direct_interc direct_interc_55_ (
.in(clb_I5[2]),
.out(direct_interc_55_out[0]));
direct_interc direct_interc_56_ (
.in(clb_I5i[0]),
.out(direct_interc_56_out[0]));
direct_interc direct_interc_57_ (
.in(logical_tile_clb_mode_default__fle_4_fle_reg_out[0]),
.out(direct_interc_57_out[0]));
direct_interc direct_interc_58_ (
.in(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
.out(direct_interc_58_out[0]));
direct_interc direct_interc_59_ (
.in(clb_clk[0]),
.out(direct_interc_59_out[0]));
direct_interc direct_interc_60_ (
.in(clb_I6[0]),
.out(direct_interc_60_out[0]));
direct_interc direct_interc_61_ (
.in(clb_I6[1]),
.out(direct_interc_61_out[0]));
direct_interc direct_interc_62_ (
.in(clb_I6[2]),
.out(direct_interc_62_out[0]));
direct_interc direct_interc_63_ (
.in(clb_I6i[0]),
.out(direct_interc_63_out[0]));
direct_interc direct_interc_64_ (
.in(logical_tile_clb_mode_default__fle_5_fle_reg_out[0]),
.out(direct_interc_64_out[0]));
direct_interc direct_interc_65_ (
.in(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
.out(direct_interc_65_out[0]));
direct_interc direct_interc_66_ (
.in(clb_clk[0]),
.out(direct_interc_66_out[0]));
direct_interc direct_interc_67_ (
.in(clb_I7[0]),
.out(direct_interc_67_out[0]));
direct_interc direct_interc_68_ (
.in(clb_I7[1]),
.out(direct_interc_68_out[0]));
direct_interc direct_interc_69_ (
.in(clb_I7[2]),
.out(direct_interc_69_out[0]));
direct_interc direct_interc_70_ (
.in(clb_I7i[0]),
.out(direct_interc_70_out[0]));
direct_interc direct_interc_71_ (
.in(logical_tile_clb_mode_default__fle_6_fle_reg_out[0]),
.out(direct_interc_71_out[0]));
direct_interc direct_interc_72_ (
.in(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
.out(direct_interc_72_out[0]));
direct_interc direct_interc_73_ (
.in(clb_clk[0]),
.out(direct_interc_73_out[0]));
endmodule |
module logical_tile_io_mode_io_(IO_ISOL_N,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
io_outpad,
ccff_head,
io_inpad,
ccff_tail);
//
input [0:0] IO_ISOL_N;
//
input [0:0] prog_clk;
//
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//
input [0:0] io_outpad;
//
input [0:0] ccff_head;
//
output [0:0] io_inpad;
//
output [0:0] ccff_tail;
//
wire [0:0] io_outpad;
wire [0:0] io_inpad;
//
//
//
wire [0:0] direct_interc_1_out;
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
//
//
//
//
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.iopad_outpad(direct_interc_1_out[0]),
.ccff_head(ccff_head[0]),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]),
.ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ (
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]),
.out(io_inpad[0]));
direct_interc direct_interc_1_ (
.in(io_outpad[0]),
.out(direct_interc_1_out[0]));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(prog_clk,
frac_lut4_in,
ccff_head,
frac_lut4_lut3_out,
frac_lut4_lut4_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:3] frac_lut4_in;
//
input [0:0] ccff_head;
//
output [0:1] frac_lut4_lut3_out;
//
output [0:0] frac_lut4_lut4_out;
//
output [0:0] ccff_tail;
//
wire [0:3] frac_lut4_in;
wire [0:1] frac_lut4_lut3_out;
wire [0:0] frac_lut4_lut4_out;
//
//
//
wire [0:0] frac_lut4_0__undriven_mode_inv;
wire [0:15] frac_lut4_0__undriven_sram_inv;
wire [0:0] frac_lut4_0_mode;
wire [0:15] frac_lut4_0_sram;
//
//
//
//
frac_lut4 frac_lut4_0_ (
.in(frac_lut4_in[0:3]),
.sram(frac_lut4_0_sram[0:15]),
.sram_inv(frac_lut4_0__undriven_sram_inv[0:15]),
.mode(frac_lut4_0_mode[0]),
.mode_inv(frac_lut4_0__undriven_mode_inv[0]),
.lut3_out(frac_lut4_lut3_out[0:1]),
.lut4_out(frac_lut4_lut4_out[0]));
frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]}));
endmodule |
module logical_tile_io_mode_physical__iopad(IO_ISOL_N,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
iopad_outpad,
ccff_head,
iopad_inpad,
ccff_tail);
//
input [0:0] IO_ISOL_N;
//
input [0:0] prog_clk;
//
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//
input [0:0] iopad_outpad;
//
input [0:0] ccff_head;
//
output [0:0] iopad_inpad;
//
output [0:0] ccff_tail;
//
wire [0:0] iopad_outpad;
wire [0:0] iopad_inpad;
//
//
//
wire [0:0] EMBEDDED_IO_HD_0_en;
//
//
//
//
EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
.IO_ISOL_N(IO_ISOL_N[0]),
.SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.FPGA_OUT(iopad_outpad[0]),
.FPGA_DIR(EMBEDDED_IO_HD_0_en[0]),
.FPGA_IN(iopad_inpad[0]));
EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(EMBEDDED_IO_HD_0_en[0]));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(prog_clk,
frac_logic_in,
ccff_head,
frac_logic_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:3] frac_logic_in;
//
input [0:0] ccff_head;
//
output [0:1] frac_logic_out;
//
output [0:0] ccff_tail;
//
wire [0:3] frac_logic_in;
wire [0:1] frac_logic_out;
//
//
//
wire [0:0] direct_interc_1_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
//
//
//
//
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
.prog_clk(prog_clk[0]),
.frac_lut4_in({direct_interc_1_out[0], direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0]}),
.ccff_head(ccff_head[0]),
.frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]),
.frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]));
mux_tree_size2 mux_frac_logic_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_frac_logic_out_0_undriven_sram_inv[0:1]),
.out(frac_logic_out[0]));
mux_tree_size2_mem mem_frac_logic_out_0 (
.prog_clk(prog_clk[0]),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_size2_0_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),
.out(frac_logic_out[1]));
direct_interc direct_interc_1_ (
.in(frac_logic_in[0]),
.out(direct_interc_1_out[0]));
direct_interc direct_interc_2_ (
.in(frac_logic_in[1]),
.out(direct_interc_2_out[0]));
direct_interc direct_interc_3_ (
.in(frac_logic_in[2]),
.out(direct_interc_3_out[0]));
direct_interc direct_interc_4_ (
.in(frac_logic_in[3]),
.out(direct_interc_4_out[0]));
endmodule |
module mux_tree_tapbuf_size10_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule |
module mux_tree_tapbuf_size5_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule |
module mux_tree_tapbuf_size3_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule |
module mux_tree_tapbuf_size9_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule |
module mux_tree_tapbuf_size16_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:4] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[4];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ (
.CLK(prog_clk[0]),
.D(mem_out[3]),
.Q(mem_out[4]));
endmodule |
module frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:16] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[16];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ (
.CLK(prog_clk[0]),
.D(mem_out[3]),
.Q(mem_out[4]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ (
.CLK(prog_clk[0]),
.D(mem_out[4]),
.Q(mem_out[5]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ (
.CLK(prog_clk[0]),
.D(mem_out[5]),
.Q(mem_out[6]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ (
.CLK(prog_clk[0]),
.D(mem_out[6]),
.Q(mem_out[7]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ (
.CLK(prog_clk[0]),
.D(mem_out[7]),
.Q(mem_out[8]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ (
.CLK(prog_clk[0]),
.D(mem_out[8]),
.Q(mem_out[9]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ (
.CLK(prog_clk[0]),
.D(mem_out[9]),
.Q(mem_out[10]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ (
.CLK(prog_clk[0]),
.D(mem_out[10]),
.Q(mem_out[11]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ (
.CLK(prog_clk[0]),
.D(mem_out[11]),
.Q(mem_out[12]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ (
.CLK(prog_clk[0]),
.D(mem_out[12]),
.Q(mem_out[13]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ (
.CLK(prog_clk[0]),
.D(mem_out[13]),
.Q(mem_out[14]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ (
.CLK(prog_clk[0]),
.D(mem_out[14]),
.Q(mem_out[15]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ (
.CLK(prog_clk[0]),
.D(mem_out[15]),
.Q(mem_out[16]));
endmodule |
module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:0] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[0];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
endmodule |
module fpga_top (
//
//
inout vdda1, //
inout vdda2, //
inout vssa1, //
inout vssa2, //
inout vccd1, //
inout vccd2, //
inout vssd1, //
inout vssd2, //
//
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
//
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oen,
//
input [37:0] io_in,
output [37:0] io_out,
output [37:0] io_oeb
);
//
//
//
//
//
//
//
//
wire prog_clk;
wire Test_en;
wire io_isol_n;
wire clk;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire ccff_head;
wire ccff_tail;
wire sc_head;
wire sc_tail;
//
wire wb_la_switch;
wire wb_la_switch_b;
//
//
//
//
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];
assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0];
assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0];
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1:9] = io_in[23:15];
assign io_out[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1:9];
assign io_oeb[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1:9];
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10:11] = io_in[14:13];
assign io_out[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10:11];
assign io_oeb[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10:11];
//
assign ccff_head = io_in[12];
assign io_out[12] = 1'b0;
assign io_oeb[12] = 1'b1;
assign io_out[11] = sc_tail;
assign io_oeb[11] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:20] = io_in[10:2];
assign io_out[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:20];
assign io_oeb[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:20];
assign io_isol_n = io_in[1];
assign io_out[1] = 1'b0;
assign io_oeb[1] = 1'b1;
assign Test_en = io_in[0];
assign io_out[0] = 1'b0;
assign io_oeb[0] = 1'b1;
//
//
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[13]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
assign la_data_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134]));
assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[15];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[15]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[85]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
assign la_data_out[85] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[86]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62]));
assign la_data_out[86] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[87];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[0]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[87]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[88];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[1]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[88]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[89];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[2]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[89]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[90];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[3]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[90]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[91];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[4]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[91]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[92];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[5]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[92]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[93];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[6]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[93]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[94];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[7]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[94]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[95];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[8]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[95]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[96];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[9]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[96]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[97];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[10]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[97]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[98];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[11]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[98]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[99];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[12]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[99]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[100];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[13]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[100]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[101];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[14]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[101]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[102];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[15]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[102]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[103];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[16]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[103]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[104];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[17]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[104]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[105];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[18]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[105]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[106];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[19]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[106]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[107];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[20]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[107]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[108];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[21]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[108]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[109];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[22]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[109]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[110];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[23]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[110]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[111];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[24]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[111]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[112];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[25]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[112]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[113];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[26]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[113]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[114];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[27]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[114]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[115];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[28]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[115]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[116];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[29]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[116]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[117];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[30]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[117]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[118];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[31]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[118]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[119];
assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[120];
assign la_data_out[120] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[121];
assign la_data_out[121] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[122];
assign la_data_out[122] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[123];
assign la_data_out[123] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[124];
assign la_data_out[124] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[125];
assign la_data_out[125] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[126];
assign la_data_out[126] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[127];
assign la_data_out[127] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21];
//
//
assign prog_clk = io_in[37];
assign io_out[37] = 1'b0;
assign io_oeb[37] = 1'b1;
//
assign clk = io_in[36];
assign io_out[36] = 1'b0;
assign io_oeb[36] = 1'b1;
assign io_out[35] = ccff_tail;
assign io_oeb[35] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136:143] = io_in[34:27];
assign io_out[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136:143];
assign io_oeb[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136:143];
assign sc_head = io_in[26];
assign io_out[26] = 1'b0;
assign io_oeb[26] = 1'b1;
//
//
assign wb_la_switch = io_in[25];
assign io_out[25] = 1'b0;
assign io_oeb[25] = 1'b1;
//
fpga_core fpga_core_uut(.prog_clk(prog_clk),
.Test_en(Test_en),
.clk(clk),
.IO_ISOL_N(io_isol_n),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.sc_head(sc_head),
.sc_tail(sc_tail)
);
endmodule |
module sky130_fd_sc_hvl__dlclkp_1 (
input GATE,
input CLK,
output GCLK);
endmodule |
module sky130_fd_sc_hs__dlclkp_1 (
input GATE,
input CLK,
output GCLK);
endmodule |
module sky130_fd_sc_hs__dlclkp_2 (
input GATE,
input CLK,
output GCLK);
endmodule |
module sky130_fd_sc_hs__dlclkp_4 (
input GATE,
input CLK,
output GCLK);
endmodule |
module sky130_fd_sc_ms__dlclkp_1 (
input GATE,
input CLK,
output GCLK);
endmodule |
module sky130_fd_sc_ms__dlclkp_2 (
input GATE,
input CLK,
output GCLK);
endmodule |
module sky130_fd_sc_ms__dlclkp_4 (
input GATE,
input CLK,
output GCLK);
endmodule |
module blake2s_m_select(
input wire clk,
input wire reset_n,
input wire load,
input wire [511 : 0] m,
input wire [3 : 0] round,
input wire mode,
output wire [31 : 0] G0_m0,
output wire [31 : 0] G0_m1,
output wire [31 : 0] G1_m0,
output wire [31 : 0] G1_m1,
output wire [31 : 0] G2_m0,
output wire [31 : 0] G2_m1,
output wire [31 : 0] G3_m0,
output wire [31 : 0] G3_m1
);
//----------------------------------------------------------------
// regs.
//----------------------------------------------------------------
reg [31 : 0] m_mem [0 : 15];
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [3 : 0] i_G0_m0;
reg [3 : 0] i_G0_m1;
reg [3 : 0] i_G1_m0;
reg [3 : 0] i_G1_m1;
reg [3 : 0] i_G2_m0;
reg [3 : 0] i_G2_m1;
reg [3 : 0] i_G3_m0;
reg [3 : 0] i_G3_m1;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
// Eight parallel, muxes that extract the message block words.
assign G0_m0 = m_mem[i_G0_m0];
assign G0_m1 = m_mem[i_G0_m1];
assign G1_m0 = m_mem[i_G1_m0];
assign G1_m1 = m_mem[i_G1_m1];
assign G2_m0 = m_mem[i_G2_m0];
assign G2_m1 = m_mem[i_G2_m1];
assign G3_m0 = m_mem[i_G3_m0];
assign G3_m1 = m_mem[i_G3_m1];
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous,
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 16 ; i = i + 1)
m_mem[i] <= 32'h0;
end
else
begin
if (load)
begin
// Big to little endian conversion during register load.
m_mem[00] <= {m[0487 : 0480], m[0495 : 0488], m[0503 : 0496], m[0511 : 0504]};
m_mem[01] <= {m[0455 : 0448], m[0463 : 0456], m[0471 : 0464], m[0479 : 0472]};
m_mem[02] <= {m[0423 : 0416], m[0431 : 0424], m[0439 : 0432], m[0447 : 0440]};
m_mem[03] <= {m[0391 : 0384], m[0399 : 0392], m[0407 : 0400], m[0415 : 0408]};
m_mem[04] <= {m[0359 : 0352], m[0367 : 0360], m[0375 : 0368], m[0383 : 0376]};
m_mem[05] <= {m[0327 : 0320], m[0335 : 0328], m[0343 : 0336], m[0351 : 0344]};
m_mem[06] <= {m[0295 : 0288], m[0303 : 0296], m[0311 : 0304], m[0319 : 0312]};
m_mem[07] <= {m[0263 : 0256], m[0271 : 0264], m[0279 : 0272], m[0287 : 0280]};
m_mem[08] <= {m[0231 : 0224], m[0239 : 0232], m[0247 : 0240], m[0255 : 0248]};
m_mem[09] <= {m[0199 : 0192], m[0207 : 0200], m[0215 : 0208], m[0223 : 0216]};
m_mem[10] <= {m[0167 : 0160], m[0175 : 0168], m[0183 : 0176], m[0191 : 0184]};
m_mem[11] <= {m[0135 : 0128], m[0143 : 0136], m[0151 : 0144], m[0159 : 0152]};
m_mem[12] <= {m[0103 : 0096], m[0111 : 0104], m[0119 : 0112], m[0127 : 0120]};
m_mem[13] <= {m[0071 : 0064], m[0079 : 0072], m[0087 : 0080], m[0095 : 0088]};
m_mem[14] <= {m[0039 : 0032], m[0047 : 0040], m[0055 : 0048], m[0063 : 0056]};
m_mem[15] <= {m[0007 : 0000], m[0015 : 0008], m[0023 : 0016], m[0031 : 0024]};
end
end
end // reg_update
//----------------------------------------------------------------
// get_indices
//
// Get the indices from the permutation table given the
// round and the G function mode. This is the SIGMA table.
//----------------------------------------------------------------
always @*
begin : get_indices
i_G0_m0 = 4'd0;
i_G0_m1 = 4'd0;
i_G1_m0 = 4'd0;
i_G1_m1 = 4'd0;
i_G2_m0 = 4'd0;
i_G2_m1 = 4'd0;
i_G3_m0 = 4'd0;
i_G3_m1 = 4'd0;
case ({round, mode})
0: begin
i_G0_m0 = 4'd00;
i_G0_m1 = 4'd01;
i_G1_m0 = 4'd02;
i_G1_m1 = 4'd03;
i_G2_m0 = 4'd04;
i_G2_m1 = 4'd05;
i_G3_m0 = 4'd06;
i_G3_m1 = 4'd07;
end
1: begin
i_G0_m0 = 4'd08;
i_G0_m1 = 4'd09;
i_G1_m0 = 4'd10;
i_G1_m1 = 4'd11;
i_G2_m0 = 4'd12;
i_G2_m1 = 4'd13;
i_G3_m0 = 4'd14;
i_G3_m1 = 4'd15;
end
2: begin
i_G0_m0 = 4'd14;
i_G0_m1 = 4'd10;
i_G1_m0 = 4'd04;
i_G1_m1 = 4'd08;
i_G2_m0 = 4'd09;
i_G2_m1 = 4'd15;
i_G3_m0 = 4'd13;
i_G3_m1 = 4'd06;
end
3: begin
i_G0_m0 = 4'd01;
i_G0_m1 = 4'd12;
i_G1_m0 = 4'd00;
i_G1_m1 = 4'd02;
i_G2_m0 = 4'd11;
i_G2_m1 = 4'd07;
i_G3_m0 = 4'd05;
i_G3_m1 = 4'd03;
end
4: begin
i_G0_m0 = 4'd11;
i_G0_m1 = 4'd08;
i_G1_m0 = 4'd12;
i_G1_m1 = 4'd00;
i_G2_m0 = 4'd05;
i_G2_m1 = 4'd02;
i_G3_m0 = 4'd15;
i_G3_m1 = 4'd13;
end
5: begin
i_G0_m0 = 4'd10;
i_G0_m1 = 4'd14;
i_G1_m0 = 4'd03;
i_G1_m1 = 4'd06;
i_G2_m0 = 4'd07;
i_G2_m1 = 4'd01;
i_G3_m0 = 4'd09;
i_G3_m1 = 4'd04;
end
6: begin
i_G0_m0 = 4'd07;
i_G0_m1 = 4'd09;
i_G1_m0 = 4'd03;
i_G1_m1 = 4'd01;
i_G2_m0 = 4'd13;
i_G2_m1 = 4'd12;
i_G3_m0 = 4'd11;
i_G3_m1 = 4'd14;
end
7: begin
i_G0_m0 = 4'd02;
i_G0_m1 = 4'd06;
i_G1_m0 = 4'd05;
i_G1_m1 = 4'd10;
i_G2_m0 = 4'd04;
i_G2_m1 = 4'd00;
i_G3_m0 = 4'd15;
i_G3_m1 = 4'd08;
end
8: begin
i_G0_m0 = 4'd09;
i_G0_m1 = 4'd00;
i_G1_m0 = 4'd05;
i_G1_m1 = 4'd07;
i_G2_m0 = 4'd02;
i_G2_m1 = 4'd04;
i_G3_m0 = 4'd10;
i_G3_m1 = 4'd15;
end
9: begin
i_G0_m0 = 4'd14;
i_G0_m1 = 4'd01;
i_G1_m0 = 4'd11;
i_G1_m1 = 4'd12;
i_G2_m0 = 4'd06;
i_G2_m1 = 4'd08;
i_G3_m0 = 4'd03;
i_G3_m1 = 4'd13;
end
10: begin
i_G0_m0 = 4'd02;
i_G0_m1 = 4'd12;
i_G1_m0 = 4'd06;
i_G1_m1 = 4'd10;
i_G2_m0 = 4'd00;
i_G2_m1 = 4'd11;
i_G3_m0 = 4'd08;
i_G3_m1 = 4'd03;
end
11: begin
i_G0_m0 = 4'd04;
i_G0_m1 = 4'd13;
i_G1_m0 = 4'd07;
i_G1_m1 = 4'd05;
i_G2_m0 = 4'd15;
i_G2_m1 = 4'd14;
i_G3_m0 = 4'd01;
i_G3_m1 = 4'd09;
end
12: begin
i_G0_m0 = 4'd12;
i_G0_m1 = 4'd05;
i_G1_m0 = 4'd01;
i_G1_m1 = 4'd15;
i_G2_m0 = 4'd14;
i_G2_m1 = 4'd13;
i_G3_m0 = 4'd04;
i_G3_m1 = 4'd10;
end
13: begin
i_G0_m0 = 4'd00;
i_G0_m1 = 4'd07;
i_G1_m0 = 4'd06;
i_G1_m1 = 4'd03;
i_G2_m0 = 4'd09;
i_G2_m1 = 4'd02;
i_G3_m0 = 4'd08;
i_G3_m1 = 4'd11;
end
14: begin
i_G0_m0 = 4'd13;
i_G0_m1 = 4'd11;
i_G1_m0 = 4'd07;
i_G1_m1 = 4'd14;
i_G2_m0 = 4'd12;
i_G2_m1 = 4'd01;
i_G3_m0 = 4'd03;
i_G3_m1 = 4'd09;
end
15: begin
i_G0_m0 = 4'd05;
i_G0_m1 = 4'd00;
i_G1_m0 = 4'd15;
i_G1_m1 = 4'd04;
i_G2_m0 = 4'd08;
i_G2_m1 = 4'd06;
i_G3_m0 = 4'd02;
i_G3_m1 = 4'd10;
end
16: begin
i_G0_m0 = 4'd06;
i_G0_m1 = 4'd15;
i_G1_m0 = 4'd14;
i_G1_m1 = 4'd09;
i_G2_m0 = 4'd11;
i_G2_m1 = 4'd03;
i_G3_m0 = 4'd00;
i_G3_m1 = 4'd08;
end
17: begin
i_G0_m0 = 4'd12;
i_G0_m1 = 4'd02;
i_G1_m0 = 4'd13;
i_G1_m1 = 4'd07;
i_G2_m0 = 4'd01;
i_G2_m1 = 4'd04;
i_G3_m0 = 4'd10;
i_G3_m1 = 4'd05;
end
18: begin
i_G0_m0 = 4'd10;
i_G0_m1 = 4'd02;
i_G1_m0 = 4'd08;
i_G1_m1 = 4'd04;
i_G2_m0 = 4'd07;
i_G2_m1 = 4'd06;
i_G3_m0 = 4'd01;
i_G3_m1 = 4'd05;
end
19: begin
i_G0_m0 = 4'd15;
i_G0_m1 = 4'd11;
i_G1_m0 = 4'd09;
i_G1_m1 = 4'd14;
i_G2_m0 = 4'd03;
i_G2_m1 = 4'd12;
i_G3_m0 = 4'd13;
i_G3_m1 = 4'd00;
end
default: begin end
endcase // case ({round, mode})
end
endmodule // blake2s_m_select |
module rf_64x64 (
input HCLK, // System clock
input WR,
input [ 5:0] RA,
input [ 5:0] RB,
input [ 5:0] RW,
input [63:0] DW,
output [63:0] DA,
output [63:0] DB
);
reg [63:0] RF [63:0];
assign DA = RF[RA] & {64{~(RA==6'd0)}};
assign DB = RF[RB] & {64{~(RB==6'd0)}};
always @ (posedge HCLK)
if(WR)
if(RW!=6'd0) begin
RF[RW] <= DW;
//#1 $display("Write: RF[%d]=0x%X []", RW, RF[RW]);
end
endmodule |
module NfiVe32_RF (
input HCLK, // System clock
input WR,
input [ 4:0] RA,
input [ 4:0] RB,
input [ 4:0] RW,
input [31:0] DW,
output [31:0] DA,
output [31:0] DB
);
reg [31:0] RF [31:0];
assign DA = RF[RA] & {32{~(RA==5'd0)}};
assign DB = RF[RB] & {32{~(RB==5'd0)}};
always @ (posedge HCLK)
if(WR)
if(RW!=5'd0) begin
RF[RW] <= DW;
//#1 $display("Write: RF[%d]=0x%X []", RW, RF[RW]);
end
endmodule |
module blake2s_core(
input wire clk,
input wire reset_n,
input wire init,
input wire update,
input wire finish,
input wire [511 : 0] block,
input wire [6 : 0] blocklen,
output wire [255 : 0] digest,
output wire ready
);
//----------------------------------------------------------------
// Parameter block.
// See BLAKE2 paper and RFC 7693 for definition.
// Chapter 2.8 in https://blake2.net/blake2.pdf
// Section 2.5 in https://tools.ietf.org/html/rfc7693
//----------------------------------------------------------------
// The digest length in bytes. Minimum: 1, Maximum: 32
localparam [7 : 0] DIGEST_LENGTH = 8'd32;
localparam [7 : 0] KEY_LENGTH = 8'd0;
localparam [7 : 0] FANOUT = 8'd1;
localparam [7 : 0] DEPTH = 8'd01;
localparam [31 : 0] LEAF_LENGTH = 32'd0;
localparam [47 : 0] NODE_OFFSET = 48'd0;
localparam [7 : 0] NODE_DEPTH = 8'd0;
localparam [7 : 0] INNER_LENGTH = 8'd0;
localparam [63 : 0] SALT = 64'h0;
localparam [63 : 0] PERSONALIZATION = 64'h0;
wire [255 : 0] parameter_block = {PERSONALIZATION, SALT, INNER_LENGTH,
NODE_DEPTH, NODE_OFFSET, LEAF_LENGTH,
DEPTH, FANOUT, KEY_LENGTH, DIGEST_LENGTH};
//----------------------------------------------------------------
// Internal constant definitions.
//----------------------------------------------------------------
localparam NUM_ROUNDS = 10;
localparam BLOCK_BYTES = 7'd64;
// G function modes.
localparam G_ROW = 1'h0;
localparam G_DIAGONAL = 1'h1;
// Initial vectors.
localparam IV0 = 32'h6a09e667;
localparam IV1 = 32'hbb67ae85;
localparam IV2 = 32'h3c6ef372;
localparam IV3 = 32'ha54ff53a;
localparam IV4 = 32'h510e527f;
localparam IV5 = 32'h9b05688c;
localparam IV6 = 32'h1f83d9ab;
localparam IV7 = 32'h5be0cd19;
// Control FSM state names.
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT_ROUND = 3'h1;
localparam CTRL_G_ROW = 3'h2;
localparam CTRL_G_DIAGONAL = 3'h3;
localparam CTRL_COMP_DONE = 3'h4;
localparam CTRL_FINISH = 3'h5;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] h_reg [0 : 7];
reg [31 : 0] h_new [0 : 7];
reg h_we;
reg [31 : 0] v_reg [0 : 15];
reg [31 : 0] v_new [0 : 15];
reg v_we;
reg init_v;
reg update_v;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_inc;
reg round_ctr_rst;
reg [31 : 0] t0_reg;
reg [31 : 0] t0_new;
reg t0_we;
reg [31 : 0] t1_reg;
reg [31 : 0] t1_new;
reg t1_we;
reg t_ctr_inc;
reg t_ctr_rst;
reg last_reg;
reg last_new;
reg last_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [2 : 0] blake2s_ctrl_reg;
reg [2 : 0] blake2s_ctrl_new;
reg blake2s_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg init_state;
reg update_state;
reg load_m;
reg G_mode;
reg [31 : 0] G0_a;
reg [31 : 0] G0_b;
reg [31 : 0] G0_c;
reg [31 : 0] G0_d;
wire [31 : 0] G0_m0;
wire [31 : 0] G0_m1;
wire [31 : 0] G0_a_prim;
wire [31 : 0] G0_b_prim;
wire [31 : 0] G0_c_prim;
wire [31 : 0] G0_d_prim;
reg [31 : 0] G1_a;
reg [31 : 0] G1_b;
reg [31 : 0] G1_c;
reg [31 : 0] G1_d;
wire [31 : 0] G1_m0;
wire [31 : 0] G1_m1;
wire [31 : 0] G1_a_prim;
wire [31 : 0] G1_b_prim;
wire [31 : 0] G1_c_prim;
wire [31 : 0] G1_d_prim;
reg [31 : 0] G2_a;
reg [31 : 0] G2_b;
reg [31 : 0] G2_c;
reg [31 : 0] G2_d;
wire [31 : 0] G2_m0;
wire [31 : 0] G2_m1;
wire [31 : 0] G2_a_prim;
wire [31 : 0] G2_b_prim;
wire [31 : 0] G2_c_prim;
wire [31 : 0] G2_d_prim;
reg [31 : 0] G3_a;
reg [31 : 0] G3_b;
reg [31 : 0] G3_c;
reg [31 : 0] G3_d;
wire [31 : 0] G3_m0;
wire [31 : 0] G3_m1;
wire [31 : 0] G3_a_prim;
wire [31 : 0] G3_b_prim;
wire [31 : 0] G3_c_prim;
wire [31 : 0] G3_d_prim;
//----------------------------------------------------------------
// Module instantations.
//----------------------------------------------------------------
blake2s_m_select mselect(
.clk(clk),
.reset_n(reset_n),
.load(load_m),
.m(block),
.round(round_ctr_reg),
.mode(G_mode),
.G0_m0(G0_m0),
.G0_m1(G0_m1),
.G1_m0(G1_m0),
.G1_m1(G1_m1),
.G2_m0(G2_m0),
.G2_m1(G2_m1),
.G3_m0(G3_m0),
.G3_m1(G3_m1)
);
blake2s_G G0(
.a(G0_a),
.b(G0_b),
.c(G0_c),
.d(G0_d),
.m0(G0_m0),
.m1(G0_m1),
.a_prim(G0_a_prim),
.b_prim(G0_b_prim),
.c_prim(G0_c_prim),
.d_prim(G0_d_prim)
);
blake2s_G G1(
.a(G1_a),
.b(G1_b),
.c(G1_c),
.d(G1_d),
.m0(G1_m0),
.m1(G1_m1),
.a_prim(G1_a_prim),
.b_prim(G1_b_prim),
.c_prim(G1_c_prim),
.d_prim(G1_d_prim)
);
blake2s_G G2(
.a(G2_a),
.b(G2_b),
.c(G2_c),
.d(G2_d),
.m0(G2_m0),
.m1(G2_m1),
.a_prim(G2_a_prim),
.b_prim(G2_b_prim),
.c_prim(G2_c_prim),
.d_prim(G2_d_prim)
);
blake2s_G G3(
.a(G3_a),
.b(G3_b),
.c(G3_c),
.d(G3_d),
.m0(G3_m0),
.m1(G3_m1),
.a_prim(G3_a_prim),
.b_prim(G3_b_prim),
.c_prim(G3_c_prim),
.d_prim(G3_d_prim)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
// Note little to big endian conversion.
assign digest = {h_reg[0][7 : 0], h_reg[0][15 : 8], h_reg[0][23 : 16], h_reg[0][31 : 24],
h_reg[1][7 : 0], h_reg[1][15 : 8], h_reg[1][23 : 16], h_reg[1][31 : 24],
h_reg[2][7 : 0], h_reg[2][15 : 8], h_reg[2][23 : 16], h_reg[2][31 : 24],
h_reg[3][7 : 0], h_reg[3][15 : 8], h_reg[3][23 : 16], h_reg[3][31 : 24],
h_reg[4][7 : 0], h_reg[4][15 : 8], h_reg[4][23 : 16], h_reg[4][31 : 24],
h_reg[5][7 : 0], h_reg[5][15 : 8], h_reg[5][23 : 16], h_reg[5][31 : 24],
h_reg[6][7 : 0], h_reg[6][15 : 8], h_reg[6][23 : 16], h_reg[6][31 : 24],
h_reg[7][7 : 0], h_reg[7][15 : 8], h_reg[7][23 : 16], h_reg[7][31 : 24]};
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n) begin
for (i = 0; i < 8; i = i + 1) begin
h_reg[i] <= 32'h0;
end
for (i = 0; i < 16; i = i + 1) begin
v_reg[i] <= 32'h0;
end
t0_reg <= 32'h0;
t1_reg <= 32'h0;
last_reg <= 1'h0;
ready_reg <= 1'h1;
round_ctr_reg <= 4'h0;
blake2s_ctrl_reg <= CTRL_IDLE;
end
else begin
if (h_we) begin
for (i = 0; i < 8; i = i + 1) begin
h_reg[i] <= h_new[i];
end
end
if (v_we) begin
for (i = 0; i < 16; i = i + 1) begin
v_reg[i] <= v_new[i];
end
end
if (t0_we) begin
t0_reg <= t0_new;
end
if (t1_we) begin
t1_reg <= t1_new;
end
if (last_we) begin
last_reg <= last_new;
end
if (ready_we) begin
ready_reg <= ready_new;
end
if (round_ctr_we) begin
round_ctr_reg <= round_ctr_new;
end
if (blake2s_ctrl_we) begin
blake2s_ctrl_reg <= blake2s_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// state_logic
//
// Logic for updating the hash state.
//----------------------------------------------------------------
always @*
begin : state_logic
integer i;
for (i = 0; i < 8; i = i + 1) begin
h_new[i] = 32'h0;
end
h_we = 1'h0;
if (init_state) begin
h_new[0] = IV0 ^ parameter_block[31 : 0];
h_new[1] = IV1 ^ parameter_block[63 : 32];
h_new[2] = IV2 ^ parameter_block[95 : 64];
h_new[3] = IV3 ^ parameter_block[127 : 96];
h_new[4] = IV4 ^ parameter_block[159 : 128];
h_new[5] = IV5 ^ parameter_block[191 : 160];
h_new[6] = IV6 ^ parameter_block[223 : 192];
h_new[7] = IV7 ^ parameter_block[255 : 224];
h_we = 1;
end
if (update_state) begin
h_new[0] = h_reg[0] ^ v_reg[0] ^ v_reg[8];
h_new[1] = h_reg[1] ^ v_reg[1] ^ v_reg[9];
h_new[2] = h_reg[2] ^ v_reg[2] ^ v_reg[10];
h_new[3] = h_reg[3] ^ v_reg[3] ^ v_reg[11];
h_new[4] = h_reg[4] ^ v_reg[4] ^ v_reg[12];
h_new[5] = h_reg[5] ^ v_reg[5] ^ v_reg[13];
h_new[6] = h_reg[6] ^ v_reg[6] ^ v_reg[14];
h_new[7] = h_reg[7] ^ v_reg[7] ^ v_reg[15];
h_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// compress_logic
//----------------------------------------------------------------
always @*
begin : compress_logic
integer i;
for (i = 0; i < 16; i = i + 1) begin
v_new[i] = 32'h0;
end
v_we = 1'h0;
G0_a = 32'h0;
G0_b = 32'h0;
G0_c = 32'h0;
G0_d = 32'h0;
G1_a = 32'h0;
G1_b = 32'h0;
G1_c = 32'h0;
G1_d = 32'h0;
G2_a = 32'h0;
G2_b = 32'h0;
G2_c = 32'h0;
G2_d = 32'h0;
G3_a = 32'h0;
G3_b = 32'h0;
G3_c = 32'h0;
G3_d = 32'h0;
if (init_v)
begin
v_new[0] = h_reg[0];
v_new[1] = h_reg[1];
v_new[2] = h_reg[2];
v_new[3] = h_reg[3];
v_new[4] = h_reg[4];
v_new[5] = h_reg[5];
v_new[6] = h_reg[6];
v_new[7] = h_reg[7];
v_new[8] = IV0;
v_new[9] = IV1;
v_new[10] = IV2;
v_new[11] = IV3;
v_new[12] = t0_reg ^ IV4;
v_new[13] = t1_reg ^ IV5;
if (last_reg) begin
v_new[14] = ~IV6;
end else begin
v_new[14] = IV6;
end
v_new[15] = IV7;
v_we = 1;
end
if (update_v)
begin
v_we = 1;
if (G_mode == G_ROW) begin
// Row updates.
G0_a = v_reg[0];
G0_b = v_reg[4];
G0_c = v_reg[8];
G0_d = v_reg[12];
v_new[0] = G0_a_prim;
v_new[4] = G0_b_prim;
v_new[8] = G0_c_prim;
v_new[12] = G0_d_prim;
G1_a = v_reg[1];
G1_b = v_reg[5];
G1_c = v_reg[9];
G1_d = v_reg[13];
v_new[1] = G1_a_prim;
v_new[5] = G1_b_prim;
v_new[9] = G1_c_prim;
v_new[13] = G1_d_prim;
G2_a = v_reg[2];
G2_b = v_reg[6];
G2_c = v_reg[10];
G2_d = v_reg[14];
v_new[2] = G2_a_prim;
v_new[6] = G2_b_prim;
v_new[10] = G2_c_prim;
v_new[14] = G2_d_prim;
G3_a = v_reg[3];
G3_b = v_reg[7];
G3_c = v_reg[11];
G3_d = v_reg[15];
v_new[3] = G3_a_prim;
v_new[7] = G3_b_prim;
v_new[11] = G3_c_prim;
v_new[15] = G3_d_prim;
end
else begin
// Diagonal updates.
G0_a = v_reg[0];
G0_b = v_reg[5];
G0_c = v_reg[10];
G0_d = v_reg[15];
v_new[0] = G0_a_prim;
v_new[5] = G0_b_prim;
v_new[10] = G0_c_prim;
v_new[15] = G0_d_prim;
G1_a = v_reg[1];
G1_b = v_reg[6];
G1_c = v_reg[11];
G1_d = v_reg[12];
v_new[1] = G1_a_prim;
v_new[6] = G1_b_prim;
v_new[11] = G1_c_prim;
v_new[12] = G1_d_prim;
G2_a = v_reg[2];
G2_b = v_reg[7];
G2_c = v_reg[8];
G2_d = v_reg[13];
v_new[2] = G2_a_prim;
v_new[7] = G2_b_prim;
v_new[8] = G2_c_prim;
v_new[13] = G2_d_prim;
G3_a = v_reg[3];
G3_b = v_reg[4];
G3_c = v_reg[9];
G3_d = v_reg[14];
v_new[3] = G3_a_prim;
v_new[4] = G3_b_prim;
v_new[9] = G3_c_prim;
v_new[14] = G3_d_prim;
end
end // if (update_v)
end // compress_logic
//----------------------------------------------------------------
// t_ctr
// Update logic for the length counter t, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : t_ctr
t0_new = 32'h0;
t0_we = 1'h0;
t1_new = 32'h0;
t1_we = 1'h0;
if (t_ctr_rst) begin
t0_new = 32'h0;
t0_we = 1'h1;
t1_new = 32'h0;
t1_we = 1'h1;
end
if (t_ctr_inc) begin
t0_we = 1'h1;
if (last_new) begin
t0_new = t0_reg + {25'h0, blocklen};
end else begin
t0_new = t0_reg + {25'h0, BLOCK_BYTES};
end
if (t0_new < t0_reg) begin
t1_new = t1_reg + 1'h1;
t1_we = 1'h1;
end
end
end // t_ctr
//----------------------------------------------------------------
// round_ctr
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'h0;
if (round_ctr_rst)
begin
round_ctr_new = 4'h0;
round_ctr_we = 1'h1;
end
if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1'h1;
end
end // round_ctr
//----------------------------------------------------------------
// blake2s_ctrl
//----------------------------------------------------------------
always @*
begin : blake2s_ctrl
init_state = 1'h0;
update_state = 1'h0;
init_v = 1'h0;
update_v = 1'h0;
load_m = 1'h0;
G_mode = G_ROW;
round_ctr_inc = 1'h0;
round_ctr_rst = 1'h0;
t_ctr_inc = 1'h0;
t_ctr_rst = 1'h0;
last_new = 1'h0;
last_we = 1'h0;
ready_new = 1'h0;
ready_we = 1'h0;
blake2s_ctrl_new = CTRL_IDLE;
blake2s_ctrl_we = 1'h0;
case (blake2s_ctrl_reg)
CTRL_IDLE: begin
if (init) begin
last_new = 1'h0;
last_we = 1'h1;
init_state = 1'h1;
t_ctr_rst = 1'h1;
ready_new = 1'h0;
ready_we = 1'h1;
blake2s_ctrl_new = CTRL_FINISH;
blake2s_ctrl_we = 1'h1;
end
if (update) begin
if (blocklen == BLOCK_BYTES) begin
load_m = 1'h1;
t_ctr_inc = 1'h1;
ready_new = 1'h0;
ready_we = 1'h1;
blake2s_ctrl_new = CTRL_INIT_ROUND;
blake2s_ctrl_we = 1'h1;
end
end
if (finish) begin
load_m = 1'h1;
t_ctr_inc = 1'h1;
last_new = 1'h1;
last_we = 1'h1;
ready_new = 1'h0;
ready_we = 1'h1;
blake2s_ctrl_new = CTRL_INIT_ROUND;
blake2s_ctrl_we = 1'h1;
end
end
CTRL_INIT_ROUND: begin
init_v = 1'h1;
round_ctr_rst = 1'h1;
blake2s_ctrl_new = CTRL_G_ROW;
blake2s_ctrl_we = 1'h1;
end
CTRL_G_ROW: begin
G_mode = G_ROW;
update_v = 1'h1;
blake2s_ctrl_new = CTRL_G_DIAGONAL;
blake2s_ctrl_we = 1'h1;
end
CTRL_G_DIAGONAL: begin
G_mode = G_DIAGONAL;
update_v = 1'h1;
round_ctr_inc = 1'h1;
if (round_ctr_reg == (NUM_ROUNDS - 1)) begin
blake2s_ctrl_new = CTRL_COMP_DONE;
blake2s_ctrl_we = 1'h1;
end
else begin
blake2s_ctrl_new = CTRL_G_ROW;
blake2s_ctrl_we = 1'h1;
end
end
CTRL_COMP_DONE: begin
last_new = 1'h0;
last_we = 1'h1;
update_state = 1'h1;
blake2s_ctrl_new = CTRL_FINISH;
blake2s_ctrl_we = 1'h1;
end
CTRL_FINISH: begin
ready_new = 1'h1;
ready_we = 1'h1;
blake2s_ctrl_new = CTRL_IDLE;
blake2s_ctrl_we = 1'h1;
end
default: begin end
endcase // case (blake2s_ctrl_reg)
end // blake2s_ctrl
endmodule // blake2s_core |
module y_dct(clk, rst, enable, data_in,
Z11_final, Z12_final, Z13_final, Z14_final, Z15_final, Z16_final, Z17_final, Z18_final,
Z21_final, Z22_final, Z23_final, Z24_final, Z25_final, Z26_final, Z27_final, Z28_final,
Z31_final, Z32_final, Z33_final, Z34_final, Z35_final, Z36_final, Z37_final, Z38_final,
Z41_final, Z42_final, Z43_final, Z44_final, Z45_final, Z46_final, Z47_final, Z48_final,
Z51_final, Z52_final, Z53_final, Z54_final, Z55_final, Z56_final, Z57_final, Z58_final,
Z61_final, Z62_final, Z63_final, Z64_final, Z65_final, Z66_final, Z67_final, Z68_final,
Z71_final, Z72_final, Z73_final, Z74_final, Z75_final, Z76_final, Z77_final, Z78_final,
Z81_final, Z82_final, Z83_final, Z84_final, Z85_final, Z86_final, Z87_final, Z88_final,
output_enable);
input clk;
input rst;
input enable;
input [7:0] data_in;
output [10:0] Z11_final, Z12_final, Z13_final, Z14_final;
output [10:0] Z15_final, Z16_final, Z17_final, Z18_final;
output [10:0] Z21_final, Z22_final, Z23_final, Z24_final;
output [10:0] Z25_final, Z26_final, Z27_final, Z28_final;
output [10:0] Z31_final, Z32_final, Z33_final, Z34_final;
output [10:0] Z35_final, Z36_final, Z37_final, Z38_final;
output [10:0] Z41_final, Z42_final, Z43_final, Z44_final;
output [10:0] Z45_final, Z46_final, Z47_final, Z48_final;
output [10:0] Z51_final, Z52_final, Z53_final, Z54_final;
output [10:0] Z55_final, Z56_final, Z57_final, Z58_final;
output [10:0] Z61_final, Z62_final, Z63_final, Z64_final;
output [10:0] Z65_final, Z66_final, Z67_final, Z68_final;
output [10:0] Z71_final, Z72_final, Z73_final, Z74_final;
output [10:0] Z75_final, Z76_final, Z77_final, Z78_final;
output [10:0] Z81_final, Z82_final, Z83_final, Z84_final;
output [10:0] Z85_final, Z86_final, Z87_final, Z88_final;
output output_enable;
integer T1, T21, T22, T23, T24, T25, T26, T27, T28, T31, T32, T33, T34, T52;
integer Ti1, Ti21, Ti22, Ti23, Ti24, Ti25, Ti26, Ti27, Ti28, Ti31, Ti32, Ti33, Ti34, Ti52;
reg [24:0] Y_temp_11;
reg [24:0] Y11, Y21, Y31, Y41, Y51, Y61, Y71, Y81, Y11_final;
reg [31:0] Y_temp_21, Y_temp_31, Y_temp_41, Y_temp_51;
reg [31:0] Y_temp_61, Y_temp_71, Y_temp_81;
reg [31:0] Z_temp_11, Z_temp_12, Z_temp_13, Z_temp_14;
reg [31:0] Z_temp_15, Z_temp_16, Z_temp_17, Z_temp_18;
reg [31:0] Z_temp_21, Z_temp_22, Z_temp_23, Z_temp_24;
reg [31:0] Z_temp_25, Z_temp_26, Z_temp_27, Z_temp_28;
reg [31:0] Z_temp_31, Z_temp_32, Z_temp_33, Z_temp_34;
reg [31:0] Z_temp_35, Z_temp_36, Z_temp_37, Z_temp_38;
reg [31:0] Z_temp_41, Z_temp_42, Z_temp_43, Z_temp_44;
reg [31:0] Z_temp_45, Z_temp_46, Z_temp_47, Z_temp_48;
reg [31:0] Z_temp_51, Z_temp_52, Z_temp_53, Z_temp_54;
reg [31:0] Z_temp_55, Z_temp_56, Z_temp_57, Z_temp_58;
reg [31:0] Z_temp_61, Z_temp_62, Z_temp_63, Z_temp_64;
reg [31:0] Z_temp_65, Z_temp_66, Z_temp_67, Z_temp_68;
reg [31:0] Z_temp_71, Z_temp_72, Z_temp_73, Z_temp_74;
reg [31:0] Z_temp_75, Z_temp_76, Z_temp_77, Z_temp_78;
reg [31:0] Z_temp_81, Z_temp_82, Z_temp_83, Z_temp_84;
reg [31:0] Z_temp_85, Z_temp_86, Z_temp_87, Z_temp_88;
reg [26:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18;
reg [26:0] Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28;
reg [26:0] Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38;
reg [26:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48;
reg [26:0] Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58;
reg [26:0] Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68;
reg [26:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78;
reg [26:0] Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88;
reg [31:0] Y11_final_2, Y21_final_2, Y11_final_3, Y11_final_4, Y31_final_2, Y41_final_2;
reg [31:0] Y51_final_2, Y61_final_2, Y71_final_2, Y81_final_2;
reg [12:0] Y11_final_1, Y21_final_1, Y31_final_1, Y41_final_1;
reg [12:0] Y51_final_1, Y61_final_1, Y71_final_1, Y81_final_1;
reg [24:0] Y21_final, Y31_final, Y41_final, Y51_final;
reg [24:0] Y61_final, Y71_final, Y81_final;
reg [24:0] Y21_final_prev, Y21_final_diff;
reg [24:0] Y31_final_prev, Y31_final_diff;
reg [24:0] Y41_final_prev, Y41_final_diff;
reg [24:0] Y51_final_prev, Y51_final_diff;
reg [24:0] Y61_final_prev, Y61_final_diff;
reg [24:0] Y71_final_prev, Y71_final_diff;
reg [24:0] Y81_final_prev, Y81_final_diff;
reg [10:0] Z11_final, Z12_final, Z13_final, Z14_final;
reg [10:0] Z15_final, Z16_final, Z17_final, Z18_final;
reg [10:0] Z21_final, Z22_final, Z23_final, Z24_final;
reg [10:0] Z25_final, Z26_final, Z27_final, Z28_final;
reg [10:0] Z31_final, Z32_final, Z33_final, Z34_final;
reg [10:0] Z35_final, Z36_final, Z37_final, Z38_final;
reg [10:0] Z41_final, Z42_final, Z43_final, Z44_final;
reg [10:0] Z45_final, Z46_final, Z47_final, Z48_final;
reg [10:0] Z51_final, Z52_final, Z53_final, Z54_final;
reg [10:0] Z55_final, Z56_final, Z57_final, Z58_final;
reg [10:0] Z61_final, Z62_final, Z63_final, Z64_final;
reg [10:0] Z65_final, Z66_final, Z67_final, Z68_final;
reg [10:0] Z71_final, Z72_final, Z73_final, Z74_final;
reg [10:0] Z75_final, Z76_final, Z77_final, Z78_final;
reg [10:0] Z81_final, Z82_final, Z83_final, Z84_final;
reg [10:0] Z85_final, Z86_final, Z87_final, Z88_final;
reg [2:0] count;
reg [2:0] count_of, count_of_copy;
reg count_1, count_3, count_4, count_5, count_6, count_7, count_8, enable_1, output_enable;
reg count_9, count_10;
reg [7:0] data_1;
integer Y2_mul_input, Y3_mul_input, Y4_mul_input, Y5_mul_input;
integer Y6_mul_input, Y7_mul_input, Y8_mul_input;
integer Ti2_mul_input, Ti3_mul_input, Ti4_mul_input, Ti5_mul_input;
integer Ti6_mul_input, Ti7_mul_input, Ti8_mul_input;
always @(posedge clk)
begin // DCT matrix entries
T1 = 5793; // .3536
T21 = 8035; // .4904
T22 = 6811; // .4157
T23 = 4551; // .2778
T24 = 1598; // .0975
T25 = -1598; // -.0975
T26 = -4551; // -.2778
T27 = -6811; // -.4157
T28 = -8035; // -.4904
T31 = 7568; // .4619
T32 = 3135; // .1913
T33 = -3135; // -.1913
T34 = -7568; // -.4619
T52 = -5793; // -.3536
end
always @(posedge clk)
begin // The inverse DCT matrix entries
Ti1 = 5793; // .3536
Ti21 = 8035; // .4904
Ti22 = 6811; // .4157
Ti23 = 4551; // .2778
Ti24 = 1598; // .0975
Ti25 = -1598; // -.0975
Ti26 = -4551; // -.2778
Ti27 = -6811; // -.4157
Ti28 = -8035; // -.4904
Ti31 = 7568; // .4619
Ti32 = 3135; // .1913
Ti33 = -3135; // -.1913
Ti34 = -7568; // -.4619
Ti52 = -5793; // -.3536
end
always @(posedge clk)
begin
if (rst) begin
Z_temp_11 <= 0; Z_temp_12 <= 0; Z_temp_13 <= 0; Z_temp_14 <= 0;
Z_temp_15 <= 0; Z_temp_16 <= 0; Z_temp_17 <= 0; Z_temp_18 <= 0;
Z_temp_21 <= 0; Z_temp_22 <= 0; Z_temp_23 <= 0; Z_temp_24 <= 0;
Z_temp_25 <= 0; Z_temp_26 <= 0; Z_temp_27 <= 0; Z_temp_28 <= 0;
Z_temp_31 <= 0; Z_temp_32 <= 0; Z_temp_33 <= 0; Z_temp_34 <= 0;
Z_temp_35 <= 0; Z_temp_36 <= 0; Z_temp_37 <= 0; Z_temp_38 <= 0;
Z_temp_41 <= 0; Z_temp_42 <= 0; Z_temp_43 <= 0; Z_temp_44 <= 0;
Z_temp_45 <= 0; Z_temp_46 <= 0; Z_temp_47 <= 0; Z_temp_48 <= 0;
Z_temp_51 <= 0; Z_temp_52 <= 0; Z_temp_53 <= 0; Z_temp_54 <= 0;
Z_temp_55 <= 0; Z_temp_56 <= 0; Z_temp_57 <= 0; Z_temp_58 <= 0;
Z_temp_61 <= 0; Z_temp_62 <= 0; Z_temp_63 <= 0; Z_temp_64 <= 0;
Z_temp_65 <= 0; Z_temp_66 <= 0; Z_temp_67 <= 0; Z_temp_68 <= 0;
Z_temp_71 <= 0; Z_temp_72 <= 0; Z_temp_73 <= 0; Z_temp_74 <= 0;
Z_temp_75 <= 0; Z_temp_76 <= 0; Z_temp_77 <= 0; Z_temp_78 <= 0;
Z_temp_81 <= 0; Z_temp_82 <= 0; Z_temp_83 <= 0; Z_temp_84 <= 0;
Z_temp_85 <= 0; Z_temp_86 <= 0; Z_temp_87 <= 0; Z_temp_88 <= 0;
end
else if (enable_1 & count_8) begin
Z_temp_11 <= Y11_final_4 * Ti1; Z_temp_12 <= Y11_final_4 * Ti2_mul_input;
Z_temp_13 <= Y11_final_4 * Ti3_mul_input; Z_temp_14 <= Y11_final_4 * Ti4_mul_input;
Z_temp_15 <= Y11_final_4 * Ti5_mul_input; Z_temp_16 <= Y11_final_4 * Ti6_mul_input;
Z_temp_17 <= Y11_final_4 * Ti7_mul_input; Z_temp_18 <= Y11_final_4 * Ti8_mul_input;
Z_temp_21 <= Y21_final_2 * Ti1; Z_temp_22 <= Y21_final_2 * Ti2_mul_input;
Z_temp_23 <= Y21_final_2 * Ti3_mul_input; Z_temp_24 <= Y21_final_2 * Ti4_mul_input;
Z_temp_25 <= Y21_final_2 * Ti5_mul_input; Z_temp_26 <= Y21_final_2 * Ti6_mul_input;
Z_temp_27 <= Y21_final_2 * Ti7_mul_input; Z_temp_28 <= Y21_final_2 * Ti8_mul_input;
Z_temp_31 <= Y31_final_2 * Ti1; Z_temp_32 <= Y31_final_2 * Ti2_mul_input;
Z_temp_33 <= Y31_final_2 * Ti3_mul_input; Z_temp_34 <= Y31_final_2 * Ti4_mul_input;
Z_temp_35 <= Y31_final_2 * Ti5_mul_input; Z_temp_36 <= Y31_final_2 * Ti6_mul_input;
Z_temp_37 <= Y31_final_2 * Ti7_mul_input; Z_temp_38 <= Y31_final_2 * Ti8_mul_input;
Z_temp_41 <= Y41_final_2 * Ti1; Z_temp_42 <= Y41_final_2 * Ti2_mul_input;
Z_temp_43 <= Y41_final_2 * Ti3_mul_input; Z_temp_44 <= Y41_final_2 * Ti4_mul_input;
Z_temp_45 <= Y41_final_2 * Ti5_mul_input; Z_temp_46 <= Y41_final_2 * Ti6_mul_input;
Z_temp_47 <= Y41_final_2 * Ti7_mul_input; Z_temp_48 <= Y41_final_2 * Ti8_mul_input;
Z_temp_51 <= Y51_final_2 * Ti1; Z_temp_52 <= Y51_final_2 * Ti2_mul_input;
Z_temp_53 <= Y51_final_2 * Ti3_mul_input; Z_temp_54 <= Y51_final_2 * Ti4_mul_input;
Z_temp_55 <= Y51_final_2 * Ti5_mul_input; Z_temp_56 <= Y51_final_2 * Ti6_mul_input;
Z_temp_57 <= Y51_final_2 * Ti7_mul_input; Z_temp_58 <= Y51_final_2 * Ti8_mul_input;
Z_temp_61 <= Y61_final_2 * Ti1; Z_temp_62 <= Y61_final_2 * Ti2_mul_input;
Z_temp_63 <= Y61_final_2 * Ti3_mul_input; Z_temp_64 <= Y61_final_2 * Ti4_mul_input;
Z_temp_65 <= Y61_final_2 * Ti5_mul_input; Z_temp_66 <= Y61_final_2 * Ti6_mul_input;
Z_temp_67 <= Y61_final_2 * Ti7_mul_input; Z_temp_68 <= Y61_final_2 * Ti8_mul_input;
Z_temp_71 <= Y71_final_2 * Ti1; Z_temp_72 <= Y71_final_2 * Ti2_mul_input;
Z_temp_73 <= Y71_final_2 * Ti3_mul_input; Z_temp_74 <= Y71_final_2 * Ti4_mul_input;
Z_temp_75 <= Y71_final_2 * Ti5_mul_input; Z_temp_76 <= Y71_final_2 * Ti6_mul_input;
Z_temp_77 <= Y71_final_2 * Ti7_mul_input; Z_temp_78 <= Y71_final_2 * Ti8_mul_input;
Z_temp_81 <= Y81_final_2 * Ti1; Z_temp_82 <= Y81_final_2 * Ti2_mul_input;
Z_temp_83 <= Y81_final_2 * Ti3_mul_input; Z_temp_84 <= Y81_final_2 * Ti4_mul_input;
Z_temp_85 <= Y81_final_2 * Ti5_mul_input; Z_temp_86 <= Y81_final_2 * Ti6_mul_input;
Z_temp_87 <= Y81_final_2 * Ti7_mul_input; Z_temp_88 <= Y81_final_2 * Ti8_mul_input;
end
end
always @(posedge clk)
begin
if (rst) begin
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
end
else if (count_8 & count_of == 1) begin
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0;
Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0;
Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0;
Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0;
Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0;
Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0;
Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0;
Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0;
Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
end
else if (enable & count_9) begin
Z11 <= Z_temp_11 + Z11; Z12 <= Z_temp_12 + Z12; Z13 <= Z_temp_13 + Z13; Z14 <= Z_temp_14 + Z14;
Z15 <= Z_temp_15 + Z15; Z16 <= Z_temp_16 + Z16; Z17 <= Z_temp_17 + Z17; Z18 <= Z_temp_18 + Z18;
Z21 <= Z_temp_21 + Z21; Z22 <= Z_temp_22 + Z22; Z23 <= Z_temp_23 + Z23; Z24 <= Z_temp_24 + Z24;
Z25 <= Z_temp_25 + Z25; Z26 <= Z_temp_26 + Z26; Z27 <= Z_temp_27 + Z27; Z28 <= Z_temp_28 + Z28;
Z31 <= Z_temp_31 + Z31; Z32 <= Z_temp_32 + Z32; Z33 <= Z_temp_33 + Z33; Z34 <= Z_temp_34 + Z34;
Z35 <= Z_temp_35 + Z35; Z36 <= Z_temp_36 + Z36; Z37 <= Z_temp_37 + Z37; Z38 <= Z_temp_38 + Z38;
Z41 <= Z_temp_41 + Z41; Z42 <= Z_temp_42 + Z42; Z43 <= Z_temp_43 + Z43; Z44 <= Z_temp_44 + Z44;
Z45 <= Z_temp_45 + Z45; Z46 <= Z_temp_46 + Z46; Z47 <= Z_temp_47 + Z47; Z48 <= Z_temp_48 + Z48;
Z51 <= Z_temp_51 + Z51; Z52 <= Z_temp_52 + Z52; Z53 <= Z_temp_53 + Z53; Z54 <= Z_temp_54 + Z54;
Z55 <= Z_temp_55 + Z55; Z56 <= Z_temp_56 + Z56; Z57 <= Z_temp_57 + Z57; Z58 <= Z_temp_58 + Z58;
Z61 <= Z_temp_61 + Z61; Z62 <= Z_temp_62 + Z62; Z63 <= Z_temp_63 + Z63; Z64 <= Z_temp_64 + Z64;
Z65 <= Z_temp_65 + Z65; Z66 <= Z_temp_66 + Z66; Z67 <= Z_temp_67 + Z67; Z68 <= Z_temp_68 + Z68;
Z71 <= Z_temp_71 + Z71; Z72 <= Z_temp_72 + Z72; Z73 <= Z_temp_73 + Z73; Z74 <= Z_temp_74 + Z74;
Z75 <= Z_temp_75 + Z75; Z76 <= Z_temp_76 + Z76; Z77 <= Z_temp_77 + Z77; Z78 <= Z_temp_78 + Z78;
Z81 <= Z_temp_81 + Z81; Z82 <= Z_temp_82 + Z82; Z83 <= Z_temp_83 + Z83; Z84 <= Z_temp_84 + Z84;
Z85 <= Z_temp_85 + Z85; Z86 <= Z_temp_86 + Z86; Z87 <= Z_temp_87 + Z87; Z88 <= Z_temp_88 + Z88;
end
end
always @(posedge clk)
begin
if (rst) begin
Z11_final <= 0; Z12_final <= 0; Z13_final <= 0; Z14_final <= 0;
Z15_final <= 0; Z16_final <= 0; Z17_final <= 0; Z18_final <= 0;
Z21_final <= 0; Z22_final <= 0; Z23_final <= 0; Z24_final <= 0;
Z25_final <= 0; Z26_final <= 0; Z27_final <= 0; Z28_final <= 0;
Z31_final <= 0; Z32_final <= 0; Z33_final <= 0; Z34_final <= 0;
Z35_final <= 0; Z36_final <= 0; Z37_final <= 0; Z38_final <= 0;
Z41_final <= 0; Z42_final <= 0; Z43_final <= 0; Z44_final <= 0;
Z45_final <= 0; Z46_final <= 0; Z47_final <= 0; Z48_final <= 0;
Z51_final <= 0; Z52_final <= 0; Z53_final <= 0; Z54_final <= 0;
Z55_final <= 0; Z56_final <= 0; Z57_final <= 0; Z58_final <= 0;
Z61_final <= 0; Z62_final <= 0; Z63_final <= 0; Z64_final <= 0;
Z65_final <= 0; Z66_final <= 0; Z67_final <= 0; Z68_final <= 0;
Z71_final <= 0; Z72_final <= 0; Z73_final <= 0; Z74_final <= 0;
Z75_final <= 0; Z76_final <= 0; Z77_final <= 0; Z78_final <= 0;
Z81_final <= 0; Z82_final <= 0; Z83_final <= 0; Z84_final <= 0;
Z85_final <= 0; Z86_final <= 0; Z87_final <= 0; Z88_final <= 0;
end
else if (count_10 & count_of == 0) begin
Z11_final <= Z11[15] ? Z11[26:16] + 1 : Z11[26:16];
Z12_final <= Z12[15] ? Z12[26:16] + 1 : Z12[26:16];
Z13_final <= Z13[15] ? Z13[26:16] + 1 : Z13[26:16];
Z14_final <= Z14[15] ? Z14[26:16] + 1 : Z14[26:16];
Z15_final <= Z15[15] ? Z15[26:16] + 1 : Z15[26:16];
Z16_final <= Z16[15] ? Z16[26:16] + 1 : Z16[26:16];
Z17_final <= Z17[15] ? Z17[26:16] + 1 : Z17[26:16];
Z18_final <= Z18[15] ? Z18[26:16] + 1 : Z18[26:16];
Z21_final <= Z21[15] ? Z21[26:16] + 1 : Z21[26:16];
Z22_final <= Z22[15] ? Z22[26:16] + 1 : Z22[26:16];
Z23_final <= Z23[15] ? Z23[26:16] + 1 : Z23[26:16];
Z24_final <= Z24[15] ? Z24[26:16] + 1 : Z24[26:16];
Z25_final <= Z25[15] ? Z25[26:16] + 1 : Z25[26:16];
Z26_final <= Z26[15] ? Z26[26:16] + 1 : Z26[26:16];
Z27_final <= Z27[15] ? Z27[26:16] + 1 : Z27[26:16];
Z28_final <= Z28[15] ? Z28[26:16] + 1 : Z28[26:16];
Z31_final <= Z31[15] ? Z31[26:16] + 1 : Z31[26:16];
Z32_final <= Z32[15] ? Z32[26:16] + 1 : Z32[26:16];
Z33_final <= Z33[15] ? Z33[26:16] + 1 : Z33[26:16];
Z34_final <= Z34[15] ? Z34[26:16] + 1 : Z34[26:16];
Z35_final <= Z35[15] ? Z35[26:16] + 1 : Z35[26:16];
Z36_final <= Z36[15] ? Z36[26:16] + 1 : Z36[26:16];
Z37_final <= Z37[15] ? Z37[26:16] + 1 : Z37[26:16];
Z38_final <= Z38[15] ? Z38[26:16] + 1 : Z38[26:16];
Z41_final <= Z41[15] ? Z41[26:16] + 1 : Z41[26:16];
Z42_final <= Z42[15] ? Z42[26:16] + 1 : Z42[26:16];
Z43_final <= Z43[15] ? Z43[26:16] + 1 : Z43[26:16];
Z44_final <= Z44[15] ? Z44[26:16] + 1 : Z44[26:16];
Z45_final <= Z45[15] ? Z45[26:16] + 1 : Z45[26:16];
Z46_final <= Z46[15] ? Z46[26:16] + 1 : Z46[26:16];
Z47_final <= Z47[15] ? Z47[26:16] + 1 : Z47[26:16];
Z48_final <= Z48[15] ? Z48[26:16] + 1 : Z48[26:16];
Z51_final <= Z51[15] ? Z51[26:16] + 1 : Z51[26:16];
Z52_final <= Z52[15] ? Z52[26:16] + 1 : Z52[26:16];
Z53_final <= Z53[15] ? Z53[26:16] + 1 : Z53[26:16];
Z54_final <= Z54[15] ? Z54[26:16] + 1 : Z54[26:16];
Z55_final <= Z55[15] ? Z55[26:16] + 1 : Z55[26:16];
Z56_final <= Z56[15] ? Z56[26:16] + 1 : Z56[26:16];
Z57_final <= Z57[15] ? Z57[26:16] + 1 : Z57[26:16];
Z58_final <= Z58[15] ? Z58[26:16] + 1 : Z58[26:16];
Z61_final <= Z61[15] ? Z61[26:16] + 1 : Z61[26:16];
Z62_final <= Z62[15] ? Z62[26:16] + 1 : Z62[26:16];
Z63_final <= Z63[15] ? Z63[26:16] + 1 : Z63[26:16];
Z64_final <= Z64[15] ? Z64[26:16] + 1 : Z64[26:16];
Z65_final <= Z65[15] ? Z65[26:16] + 1 : Z65[26:16];
Z66_final <= Z66[15] ? Z66[26:16] + 1 : Z66[26:16];
Z67_final <= Z67[15] ? Z67[26:16] + 1 : Z67[26:16];
Z68_final <= Z68[15] ? Z68[26:16] + 1 : Z68[26:16];
Z71_final <= Z71[15] ? Z71[26:16] + 1 : Z71[26:16];
Z72_final <= Z72[15] ? Z72[26:16] + 1 : Z72[26:16];
Z73_final <= Z73[15] ? Z73[26:16] + 1 : Z73[26:16];
Z74_final <= Z74[15] ? Z74[26:16] + 1 : Z74[26:16];
Z75_final <= Z75[15] ? Z75[26:16] + 1 : Z75[26:16];
Z76_final <= Z76[15] ? Z76[26:16] + 1 : Z76[26:16];
Z77_final <= Z77[15] ? Z77[26:16] + 1 : Z77[26:16];
Z78_final <= Z78[15] ? Z78[26:16] + 1 : Z78[26:16];
Z81_final <= Z81[15] ? Z81[26:16] + 1 : Z81[26:16];
Z82_final <= Z82[15] ? Z82[26:16] + 1 : Z82[26:16];
Z83_final <= Z83[15] ? Z83[26:16] + 1 : Z83[26:16];
Z84_final <= Z84[15] ? Z84[26:16] + 1 : Z84[26:16];
Z85_final <= Z85[15] ? Z85[26:16] + 1 : Z85[26:16];
Z86_final <= Z86[15] ? Z86[26:16] + 1 : Z86[26:16];
Z87_final <= Z87[15] ? Z87[26:16] + 1 : Z87[26:16];
Z88_final <= Z88[15] ? Z88[26:16] + 1 : Z88[26:16];
end
end
// output_enable signals the next block, the quantizer, that the input data is ready
always @(posedge clk)
begin
if (rst)
output_enable <= 0;
else if (!enable_1)
output_enable <= 0;
else if (count_10 == 0 | count_of)
output_enable <= 0;
else if (count_10 & count_of == 0)
output_enable <= 1;
end
always @(posedge clk)
begin
if (rst)
Y_temp_11 <= 0;
else if (enable)
Y_temp_11 <= data_in * T1;
end
always @(posedge clk)
begin
if (rst)
Y11 <= 0;
else if (count == 1 & enable == 1)
Y11 <= Y_temp_11;
else if (enable)
Y11 <= Y_temp_11 + Y11;
end
always @(posedge clk)
begin
if (rst) begin
Y_temp_21 <= 0;
Y_temp_31 <= 0;
Y_temp_41 <= 0;
Y_temp_51 <= 0;
Y_temp_61 <= 0;
Y_temp_71 <= 0;
Y_temp_81 <= 0;
end
else if (!enable_1) begin
Y_temp_21 <= 0;
Y_temp_31 <= 0;
Y_temp_41 <= 0;
Y_temp_51 <= 0;
Y_temp_61 <= 0;
Y_temp_71 <= 0;
Y_temp_81 <= 0;
end
else if (enable_1) begin
Y_temp_21 <= data_1 * Y2_mul_input;
Y_temp_31 <= data_1 * Y3_mul_input;
Y_temp_41 <= data_1 * Y4_mul_input;
Y_temp_51 <= data_1 * Y5_mul_input;
Y_temp_61 <= data_1 * Y6_mul_input;
Y_temp_71 <= data_1 * Y7_mul_input;
Y_temp_81 <= data_1 * Y8_mul_input;
end
end
always @(posedge clk)
begin
if (rst) begin
Y21 <= 0;
Y31 <= 0;
Y41 <= 0;
Y51 <= 0;
Y61 <= 0;
Y71 <= 0;
Y81 <= 0;
end
else if (!enable_1) begin
Y21 <= 0;
Y31 <= 0;
Y41 <= 0;
Y51 <= 0;
Y61 <= 0;
Y71 <= 0;
Y81 <= 0;
end
else if (enable_1) begin
Y21 <= Y_temp_21 + Y21;
Y31 <= Y_temp_31 + Y31;
Y41 <= Y_temp_41 + Y41;
Y51 <= Y_temp_51 + Y51;
Y61 <= Y_temp_61 + Y61;
Y71 <= Y_temp_71 + Y71;
Y81 <= Y_temp_81 + Y81;
end
end
always @(posedge clk)
begin
if (rst) begin
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
count_10 <= 0;
end
else if (!enable) begin
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
count_10 <= 0;
end
else if (enable) begin
count <= count + 1; count_3 <= count_1; count_4 <= count_3;
count_5 <= count_4; count_6 <= count_5; count_7 <= count_6;
count_8 <= count_7; count_9 <= count_8; count_10 <= count_9;
end
end
always @(posedge clk)
begin
if (rst) begin
count_1 <= 0;
end
else if (count != 7 | !enable) begin
count_1 <= 0;
end
else if (count == 7) begin
count_1 <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
count_of <= 0;
count_of_copy <= 0;
end
else if (!enable) begin
count_of <= 0;
count_of_copy <= 0;
end
else if (count_1 == 1) begin
count_of <= count_of + 1;
count_of_copy <= count_of_copy + 1;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_final <= 0;
end
else if (count_3 & enable_1) begin
Y11_final <= Y11 - 25'd5932032;
/* The Y values weren't centered on 0 before doing the DCT
128 needs to be subtracted from each Y value before, or in this
case, 362 is subtracted from the total, because this is the
total obtained by subtracting 128 from each element
and then multiplying by the weight
assigned by the DCT matrix : 128*8*5793 = 5932032
This is only needed for the first row, the values in the rest of
the rows add up to 0 */
end
end
always @(posedge clk)
begin
if (rst) begin
Y21_final <= 0; Y21_final_prev <= 0;
Y31_final <= 0; Y31_final_prev <= 0;
Y41_final <= 0; Y41_final_prev <= 0;
Y51_final <= 0; Y51_final_prev <= 0;
Y61_final <= 0; Y61_final_prev <= 0;
Y71_final <= 0; Y71_final_prev <= 0;
Y81_final <= 0; Y81_final_prev <= 0;
end
else if (!enable_1) begin
Y21_final <= 0; Y21_final_prev <= 0;
Y31_final <= 0; Y31_final_prev <= 0;
Y41_final <= 0; Y41_final_prev <= 0;
Y51_final <= 0; Y51_final_prev <= 0;
Y61_final <= 0; Y61_final_prev <= 0;
Y71_final <= 0; Y71_final_prev <= 0;
Y81_final <= 0; Y81_final_prev <= 0;
end
else if (count_4 & enable_1) begin
Y21_final <= Y21; Y21_final_prev <= Y21_final;
Y31_final <= Y31; Y31_final_prev <= Y31_final;
Y41_final <= Y41; Y41_final_prev <= Y41_final;
Y51_final <= Y51; Y51_final_prev <= Y51_final;
Y61_final <= Y61; Y61_final_prev <= Y61_final;
Y71_final <= Y71; Y71_final_prev <= Y71_final;
Y81_final <= Y81; Y81_final_prev <= Y81_final;
end
end
always @(posedge clk)
begin
if (rst) begin
Y21_final_diff <= 0; Y31_final_diff <= 0;
Y41_final_diff <= 0; Y51_final_diff <= 0;
Y61_final_diff <= 0; Y71_final_diff <= 0;
Y81_final_diff <= 0;
end
else if (count_5 & enable_1) begin
Y21_final_diff <= Y21_final - Y21_final_prev;
Y31_final_diff <= Y31_final - Y31_final_prev;
Y41_final_diff <= Y41_final - Y41_final_prev;
Y51_final_diff <= Y51_final - Y51_final_prev;
Y61_final_diff <= Y61_final - Y61_final_prev;
Y71_final_diff <= Y71_final - Y71_final_prev;
Y81_final_diff <= Y81_final - Y81_final_prev;
end
end
always @(posedge clk)
begin
case (count)
3'b000: Y2_mul_input <= T21;
3'b001: Y2_mul_input <= T22;
3'b010: Y2_mul_input <= T23;
3'b011: Y2_mul_input <= T24;
3'b100: Y2_mul_input <= T25;
3'b101: Y2_mul_input <= T26;
3'b110: Y2_mul_input <= T27;
3'b111: Y2_mul_input <= T28;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y3_mul_input <= T31;
3'b001: Y3_mul_input <= T32;
3'b010: Y3_mul_input <= T33;
3'b011: Y3_mul_input <= T34;
3'b100: Y3_mul_input <= T34;
3'b101: Y3_mul_input <= T33;
3'b110: Y3_mul_input <= T32;
3'b111: Y3_mul_input <= T31;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y4_mul_input <= T22;
3'b001: Y4_mul_input <= T25;
3'b010: Y4_mul_input <= T28;
3'b011: Y4_mul_input <= T26;
3'b100: Y4_mul_input <= T23;
3'b101: Y4_mul_input <= T21;
3'b110: Y4_mul_input <= T24;
3'b111: Y4_mul_input <= T27;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y5_mul_input <= T1;
3'b001: Y5_mul_input <= T52;
3'b010: Y5_mul_input <= T52;
3'b011: Y5_mul_input <= T1;
3'b100: Y5_mul_input <= T1;
3'b101: Y5_mul_input <= T52;
3'b110: Y5_mul_input <= T52;
3'b111: Y5_mul_input <= T1;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y6_mul_input <= T23;
3'b001: Y6_mul_input <= T28;
3'b010: Y6_mul_input <= T24;
3'b011: Y6_mul_input <= T22;
3'b100: Y6_mul_input <= T27;
3'b101: Y6_mul_input <= T25;
3'b110: Y6_mul_input <= T21;
3'b111: Y6_mul_input <= T26;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y7_mul_input <= T32;
3'b001: Y7_mul_input <= T34;
3'b010: Y7_mul_input <= T31;
3'b011: Y7_mul_input <= T33;
3'b100: Y7_mul_input <= T33;
3'b101: Y7_mul_input <= T31;
3'b110: Y7_mul_input <= T34;
3'b111: Y7_mul_input <= T32;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y8_mul_input <= T24;
3'b001: Y8_mul_input <= T26;
3'b010: Y8_mul_input <= T22;
3'b011: Y8_mul_input <= T28;
3'b100: Y8_mul_input <= T21;
3'b101: Y8_mul_input <= T27;
3'b110: Y8_mul_input <= T23;
3'b111: Y8_mul_input <= T25;
endcase
end
// Inverse DCT matrix entries
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti2_mul_input <= Ti28;
3'b001: Ti2_mul_input <= Ti21;
3'b010: Ti2_mul_input <= Ti22;
3'b011: Ti2_mul_input <= Ti23;
3'b100: Ti2_mul_input <= Ti24;
3'b101: Ti2_mul_input <= Ti25;
3'b110: Ti2_mul_input <= Ti26;
3'b111: Ti2_mul_input <= Ti27;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti3_mul_input <= Ti31;
3'b001: Ti3_mul_input <= Ti31;
3'b010: Ti3_mul_input <= Ti32;
3'b011: Ti3_mul_input <= Ti33;
3'b100: Ti3_mul_input <= Ti34;
3'b101: Ti3_mul_input <= Ti34;
3'b110: Ti3_mul_input <= Ti33;
3'b111: Ti3_mul_input <= Ti32;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti4_mul_input <= Ti27;
3'b001: Ti4_mul_input <= Ti22;
3'b010: Ti4_mul_input <= Ti25;
3'b011: Ti4_mul_input <= Ti28;
3'b100: Ti4_mul_input <= Ti26;
3'b101: Ti4_mul_input <= Ti23;
3'b110: Ti4_mul_input <= Ti21;
3'b111: Ti4_mul_input <= Ti24;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti5_mul_input <= Ti1;
3'b001: Ti5_mul_input <= Ti1;
3'b010: Ti5_mul_input <= Ti52;
3'b011: Ti5_mul_input <= Ti52;
3'b100: Ti5_mul_input <= Ti1;
3'b101: Ti5_mul_input <= Ti1;
3'b110: Ti5_mul_input <= Ti52;
3'b111: Ti5_mul_input <= Ti52;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti6_mul_input <= Ti26;
3'b001: Ti6_mul_input <= Ti23;
3'b010: Ti6_mul_input <= Ti28;
3'b011: Ti6_mul_input <= Ti24;
3'b100: Ti6_mul_input <= Ti22;
3'b101: Ti6_mul_input <= Ti27;
3'b110: Ti6_mul_input <= Ti25;
3'b111: Ti6_mul_input <= Ti21;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti7_mul_input <= Ti32;
3'b001: Ti7_mul_input <= Ti32;
3'b010: Ti7_mul_input <= Ti34;
3'b011: Ti7_mul_input <= Ti31;
3'b100: Ti7_mul_input <= Ti33;
3'b101: Ti7_mul_input <= Ti33;
3'b110: Ti7_mul_input <= Ti31;
3'b111: Ti7_mul_input <= Ti34;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti8_mul_input <= Ti25;
3'b001: Ti8_mul_input <= Ti24;
3'b010: Ti8_mul_input <= Ti26;
3'b011: Ti8_mul_input <= Ti22;
3'b100: Ti8_mul_input <= Ti28;
3'b101: Ti8_mul_input <= Ti21;
3'b110: Ti8_mul_input <= Ti27;
3'b111: Ti8_mul_input <= Ti23;
endcase
end
// Rounding stage
always @(posedge clk)
begin
if (rst) begin
data_1 <= 0;
Y11_final_1 <= 0; Y21_final_1 <= 0; Y31_final_1 <= 0; Y41_final_1 <= 0;
Y51_final_1 <= 0; Y61_final_1 <= 0; Y71_final_1 <= 0; Y81_final_1 <= 0;
Y11_final_2 <= 0; Y21_final_2 <= 0; Y31_final_2 <= 0; Y41_final_2 <= 0;
Y51_final_2 <= 0; Y61_final_2 <= 0; Y71_final_2 <= 0; Y81_final_2 <= 0;
Y11_final_3 <= 0; Y11_final_4 <= 0;
end
else if (enable) begin
data_1 <= data_in;
Y11_final_1 <= Y11_final[11] ? Y11_final[24:12] + 1 : Y11_final[24:12];
Y11_final_2[31:13] <= Y11_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y11_final_2[12:0] <= Y11_final_1;
// Need to sign extend Y11_final_1 and the other registers to store a negative
// number as a twos complement number. If you don't sign extend, then a negative number
// will be stored incorrectly as a positive number. For example, -215 would be stored
// as 1833 without sign extending
Y11_final_3 <= Y11_final_2;
Y11_final_4 <= Y11_final_3;
Y21_final_1 <= Y21_final_diff[11] ? Y21_final_diff[24:12] + 1 : Y21_final_diff[24:12];
Y21_final_2[31:13] <= Y21_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y21_final_2[12:0] <= Y21_final_1;
Y31_final_1 <= Y31_final_diff[11] ? Y31_final_diff[24:12] + 1 : Y31_final_diff[24:12];
Y31_final_2[31:13] <= Y31_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y31_final_2[12:0] <= Y31_final_1;
Y41_final_1 <= Y41_final_diff[11] ? Y41_final_diff[24:12] + 1 : Y41_final_diff[24:12];
Y41_final_2[31:13] <= Y41_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y41_final_2[12:0] <= Y41_final_1;
Y51_final_1 <= Y51_final_diff[11] ? Y51_final_diff[24:12] + 1 : Y51_final_diff[24:12];
Y51_final_2[31:13] <= Y51_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y51_final_2[12:0] <= Y51_final_1;
Y61_final_1 <= Y61_final_diff[11] ? Y61_final_diff[24:12] + 1 : Y61_final_diff[24:12];
Y61_final_2[31:13] <= Y61_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y61_final_2[12:0] <= Y61_final_1;
Y71_final_1 <= Y71_final_diff[11] ? Y71_final_diff[24:12] + 1 : Y71_final_diff[24:12];
Y71_final_2[31:13] <= Y71_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y71_final_2[12:0] <= Y71_final_1;
Y81_final_1 <= Y81_final_diff[11] ? Y81_final_diff[24:12] + 1 : Y81_final_diff[24:12];
Y81_final_2[31:13] <= Y81_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y81_final_2[12:0] <= Y81_final_1;
// The bit in place 11 is the fraction part, for rounding purposes
// if it is 1, then you need to add 1 to the bits in 24-12,
// if bit 11 is 0, then the bits in 24-12 won't change
end
end
always @(posedge clk)
begin
if (rst) begin
enable_1 <= 0;
end
else begin
enable_1 <= enable;
end
end
endmodule |
module blake2s(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_UPDATE_BIT = 1;
localparam CTRL_FINISH_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_BLOCKLEN = 8'h0a;
localparam ADDR_BLOCK0 = 8'h10;
localparam ADDR_BLOCK15 = 8'h1f;
localparam ADDR_DIGEST0 = 8'h40;
localparam ADDR_DIGEST7 = 8'h47;
localparam CORE_NAME0 = 32'h626c616b; // "blak"
localparam CORE_NAME1 = 32'h65327320; // "e2s "
localparam CORE_VERSION = 32'h302e3830; // "0.80"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg update_reg;
reg update_new;
reg finish_reg;
reg finish_new;
reg [6 : 0] blocklen_reg;
reg blocklen_we;
reg [31 : 0] block_mem [0 : 15];
reg block_mem_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire core_ready;
wire [511 : 0] core_block;
wire [255 : 0] core_digest;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_block = {block_mem[0], block_mem[1], block_mem[2], block_mem[3],
block_mem[4], block_mem[5], block_mem[6], block_mem[7],
block_mem[8], block_mem[9], block_mem[10], block_mem[11],
block_mem[12], block_mem[13], block_mem[14], block_mem[15]};
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
blake2s_core core(
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.update(update_reg),
.finish(finish_reg),
.block(core_block),
.blocklen(blocklen_reg),
.digest(core_digest),
.ready(core_ready)
);
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 16 ; i = i + 1)
block_mem[i] <= 32'h0;
init_reg <= 1'h0;
update_reg <= 1'h0;
finish_reg <= 1'h0;
blocklen_reg <= 7'h0;
end
else
begin
init_reg <= init_new;
update_reg <= update_new;
finish_reg <= finish_new;
if (blocklen_we) begin
blocklen_reg <= write_data[6 : 0];
end
if (block_mem_we) begin
block_mem[address[3 : 0]] <= write_data;
end
end
end // reg_update
//----------------------------------------------------------------
// api
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 1'h0;
update_new = 1'h0;
finish_new = 1'h0;
block_mem_we = 1'h0;
blocklen_we = 1'h0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if (address == ADDR_CTRL) begin
init_new = write_data[CTRL_INIT_BIT];
update_new = write_data[CTRL_UPDATE_BIT];
finish_new = write_data[CTRL_FINISH_BIT];
end
if (address == ADDR_BLOCKLEN) begin
blocklen_we = 1;
end
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15)) begin
block_mem_we = 1;
end
end
else
begin
if (address == ADDR_NAME0) begin
tmp_read_data = CORE_NAME0;
end
if (address == ADDR_NAME1) begin
tmp_read_data = CORE_NAME1;
end
if (address == ADDR_VERSION) begin
tmp_read_data = CORE_VERSION;
end
if (address == ADDR_STATUS) begin
tmp_read_data = {31'h0, core_ready};
end
if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST7)) begin
tmp_read_data = core_digest[(7 - (address - ADDR_DIGEST0)) * 32 +: 32];
end
end
end
end // api
endmodule // blake2s |
module AHB_SRAM #( parameter AW = 12) // Address width
(
input HCLK,
input HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire HREADY,
input wire [31:0] HWDATA,
input wire [2:0] HSIZE,
output wire HREADYOUT,
output wire [31:0] HRDATA,
input wire [31:0] SRAMRDATA, // SRAM Read Data
output wire [3:0] SRAMWEN, // SRAM write enable (active high)
output wire [31:0] SRAMWDATA, // SRAM write data
output wire SRAMCS, // SRAM Chip Select (active high)
output wire [AW-3:0] SRAMADDR // SRAM address
);
reg [(AW-3):0] buf_addr; // Write address buffer
reg [ 3:0] buf_we; // Write enable buffer (data phase)
reg buf_hit; // High when reading a wrote-pending data
reg [31:0] buf_data; // AHB write bus buffered
reg buf_pend; // Buffer write data valid
reg buf_data_en; // Data buffer write enable (data phase)
wire ahb_wr = HTRANS[1] & HSEL & HREADY & HWRITE;
wire ahb_rd = HTRANS[1] & HSEL & HREADY & ~HWRITE;
/*
SRAM read involves address and data phases which matches that of an AHB
transactions. However, SRAM write requires both data and address to be present
concurrently. This causes an issue for a read operation after a write operation.
The solution is to delay the write to be done after the read and provide a mean
to short circuit the data if you read from the location to be written.
*/
// Stored write data in pending state if new transfer is read
// buf_data_en indicate new write (data phase)
// ahb_rd indicate new read (address phase)
// buf_pend is registered version of buf_pend_nxt
wire buf_pend_nxt = (buf_pend | buf_data_en) & ahb_rd;
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn)
buf_pend <= 1'b0;
else
buf_pend <= buf_pend_nxt;
// RAM write happens when
// - write pending (buf_pend), or
// - new AHB write seen (buf_data_en) at data phase,
// - and not reading (address phase)
wire ram_write = (buf_pend | buf_data_en) & (~ahb_rd);
// RAM WE is the buffered WE
assign SRAMWEN = {4{ram_write}} & buf_we[3:0];
// RAM address is the buffered address for RAM write otherwise HADDR
assign SRAMADDR = ahb_rd ? HADDR[AW-1:2] : buf_addr;
// RAM chip select during read or write
assign SRAMCS = ahb_rd | ram_write;
// ----------------------------------------------------------
// Byte lane decoder and next state logic
// ----------------------------------------------------------
wire is_byte = (HSIZE == 3'b000);
wire is_half = (HSIZE == 3'b001);
wire is_word = (HSIZE == 3'b010);
wire byte_0 = is_byte & (HADDR[1:0] == 2'b00);
wire byte_1 = is_byte & (HADDR[1:0] == 2'b01);
wire byte_2 = is_byte & (HADDR[1:0] == 2'b10);
wire byte_3 = is_byte & (HADDR[1:0] == 2'b11);
wire half_0 = is_half & ~HADDR[1];
wire half_2 = is_half & HADDR[1];
wire byte_we_0 = is_word | half_0 | byte_0;
wire byte_we_1 = is_word | half_0 | byte_1;
wire byte_we_2 = is_word | half_2 | byte_2;
wire byte_we_3 = is_word | half_2 | byte_3;
// Address phase byte lane strobe
wire [3:0] buf_we_nxt = {4{ahb_wr}} & {byte_we_3, byte_we_2, byte_we_1, byte_we_0};
// buf_we keep the valid status of each byte (data phase)
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn)
buf_we <= 4'b0000;
else if(ahb_wr)
buf_we <= buf_we_nxt;
// buf_data_en is data phase write control
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn)
buf_data_en <= 1'b0;
else
buf_data_en <= ahb_wr;
always @(posedge HCLK) begin
if(buf_data_en) begin
if(buf_we[3]) buf_data[31:24] <= HWDATA[31:24];
if(buf_we[2]) buf_data[23:16] <= HWDATA[23:16];
if(buf_we[1]) buf_data[15: 8] <= HWDATA[15: 8];
if(buf_we[0]) buf_data[ 7: 0] <= HWDATA[ 7: 0];
end
end
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn)
buf_addr <= {(AW-2){1'b0}};
else if (ahb_wr)
buf_addr <= HADDR[(AW-1):2];
end
// Do we have a matching Address (hit)?
wire buf_hit_nxt = (HADDR[AW-1:2] == buf_addr[AW-3 - 0:0]);
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn)
buf_hit <= 1'b0;
else if(ahb_rd)
buf_hit <= buf_hit_nxt;
/*
Handle the short circuit scenario, a read from a location
which has a write-pending operation. In this case return
the pending data
*/
wire [ 3:0] short = {4{buf_hit}} & buf_we;
assign HRDATA = {
short[3] ? buf_data[31:24] : SRAMRDATA[31:24],
short[2] ? buf_data[23:16] : SRAMRDATA[23:16],
short[1] ? buf_data[15: 8] : SRAMRDATA[15: 8],
short[0] ? buf_data[ 7: 0] : SRAMRDATA[ 7: 0]
};
/*
SRAMWDATA comes from the pending write data if any; otherwise it
comes from HWDATA
*/
assign SRAMWDATA = (buf_pend) ? buf_data : HWDATA[31:0];
// No Delay cycles; always ready
assign HREADYOUT = 1'b1;
endmodule |
module y_quantizer(clk, rst, enable,
Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28,
Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48,
Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68,
Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88,
Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28,
Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48,
Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68,
Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88,
out_enable);
input clk;
input rst;
input enable;
input [10:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24;
input [10:0] Z25, Z26, Z27, Z28, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38;
input [10:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z51, Z52, Z53, Z54;
input [10:0] Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68;
input [10:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84;
input [10:0] Z85, Z86, Z87, Z88;
output [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24;
output [10:0] Q25, Q26, Q27, Q28, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38;
output [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q51, Q52, Q53, Q54;
output [10:0] Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68;
output [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84;
output [10:0] Q85, Q86, Q87, Q88;
output out_enable;
/* Below are the quantization values, these can be changed for different
quantization levels. */
parameter Q1_1 = 1;
parameter Q1_2 = 1;
parameter Q1_3 = 1;
parameter Q1_4 = 1;
parameter Q1_5 = 1;
parameter Q1_6 = 1;
parameter Q1_7 = 1;
parameter Q1_8 = 1;
parameter Q2_1 = 1;
parameter Q2_2 = 1;
parameter Q2_3 = 1;
parameter Q2_4 = 1;
parameter Q2_5 = 1;
parameter Q2_6 = 1;
parameter Q2_7 = 1;
parameter Q2_8 = 1;
parameter Q3_1 = 1;
parameter Q3_2 = 1;
parameter Q3_3 = 1;
parameter Q3_4 = 1;
parameter Q3_5 = 1;
parameter Q3_6 = 1;
parameter Q3_7 = 1;
parameter Q3_8 = 1;
parameter Q4_1 = 1;
parameter Q4_2 = 1;
parameter Q4_3 = 1;
parameter Q4_4 = 1;
parameter Q4_5 = 1;
parameter Q4_6 = 1;
parameter Q4_7 = 1;
parameter Q4_8 = 1;
parameter Q5_1 = 1;
parameter Q5_2 = 1;
parameter Q5_3 = 1;
parameter Q5_4 = 1;
parameter Q5_5 = 1;
parameter Q5_6 = 1;
parameter Q5_7 = 1;
parameter Q5_8 = 1;
parameter Q6_1 = 1;
parameter Q6_2 = 1;
parameter Q6_3 = 1;
parameter Q6_4 = 1;
parameter Q6_5 = 1;
parameter Q6_6 = 1;
parameter Q6_7 = 1;
parameter Q6_8 = 1;
parameter Q7_1 = 1;
parameter Q7_2 = 1;
parameter Q7_3 = 1;
parameter Q7_4 = 1;
parameter Q7_5 = 1;
parameter Q7_6 = 1;
parameter Q7_7 = 1;
parameter Q7_8 = 1;
parameter Q8_1 = 1;
parameter Q8_2 = 1;
parameter Q8_3 = 1;
parameter Q8_4 = 1;
parameter Q8_5 = 1;
parameter Q8_6 = 1;
parameter Q8_7 = 1;
parameter Q8_8 = 1;
// End of Quantization Values
/* The following parameters hold the values of 4096 divided by the corresponding
individual quantization values. These values are needed to get around
actually dividing the Y, Cb, and Cr values by the quantization values.
Instead, you can multiply by the values below, and then divide by 4096
to get the same result. And 4096 = 2^12, so instead of dividing, you can
just shift the bottom 12 bits out. This is a lossy process, as 4096/Q divided
by 4096 doesn't always equal the same value as if you were just dividing by Q. But
the quantization process is also lossy, so the additional loss of precision is
negligible. To decrease the loss, you could use a larger number than 4096 to
get around the actual use of division. Like take 8192/Q and then divide by 8192.*/
parameter QQ1_1 = 4096/Q1_1;
parameter QQ1_2 = 4096/Q1_2;
parameter QQ1_3 = 4096/Q1_3;
parameter QQ1_4 = 4096/Q1_4;
parameter QQ1_5 = 4096/Q1_5;
parameter QQ1_6 = 4096/Q1_6;
parameter QQ1_7 = 4096/Q1_7;
parameter QQ1_8 = 4096/Q1_8;
parameter QQ2_1 = 4096/Q2_1;
parameter QQ2_2 = 4096/Q2_2;
parameter QQ2_3 = 4096/Q2_3;
parameter QQ2_4 = 4096/Q2_4;
parameter QQ2_5 = 4096/Q2_5;
parameter QQ2_6 = 4096/Q2_6;
parameter QQ2_7 = 4096/Q2_7;
parameter QQ2_8 = 4096/Q2_8;
parameter QQ3_1 = 4096/Q3_1;
parameter QQ3_2 = 4096/Q3_2;
parameter QQ3_3 = 4096/Q3_3;
parameter QQ3_4 = 4096/Q3_4;
parameter QQ3_5 = 4096/Q3_5;
parameter QQ3_6 = 4096/Q3_6;
parameter QQ3_7 = 4096/Q3_7;
parameter QQ3_8 = 4096/Q3_8;
parameter QQ4_1 = 4096/Q4_1;
parameter QQ4_2 = 4096/Q4_2;
parameter QQ4_3 = 4096/Q4_3;
parameter QQ4_4 = 4096/Q4_4;
parameter QQ4_5 = 4096/Q4_5;
parameter QQ4_6 = 4096/Q4_6;
parameter QQ4_7 = 4096/Q4_7;
parameter QQ4_8 = 4096/Q4_8;
parameter QQ5_1 = 4096/Q5_1;
parameter QQ5_2 = 4096/Q5_2;
parameter QQ5_3 = 4096/Q5_3;
parameter QQ5_4 = 4096/Q5_4;
parameter QQ5_5 = 4096/Q5_5;
parameter QQ5_6 = 4096/Q5_6;
parameter QQ5_7 = 4096/Q5_7;
parameter QQ5_8 = 4096/Q5_8;
parameter QQ6_1 = 4096/Q6_1;
parameter QQ6_2 = 4096/Q6_2;
parameter QQ6_3 = 4096/Q6_3;
parameter QQ6_4 = 4096/Q6_4;
parameter QQ6_5 = 4096/Q6_5;
parameter QQ6_6 = 4096/Q6_6;
parameter QQ6_7 = 4096/Q6_7;
parameter QQ6_8 = 4096/Q6_8;
parameter QQ7_1 = 4096/Q7_1;
parameter QQ7_2 = 4096/Q7_2;
parameter QQ7_3 = 4096/Q7_3;
parameter QQ7_4 = 4096/Q7_4;
parameter QQ7_5 = 4096/Q7_5;
parameter QQ7_6 = 4096/Q7_6;
parameter QQ7_7 = 4096/Q7_7;
parameter QQ7_8 = 4096/Q7_8;
parameter QQ8_1 = 4096/Q8_1;
parameter QQ8_2 = 4096/Q8_2;
parameter QQ8_3 = 4096/Q8_3;
parameter QQ8_4 = 4096/Q8_4;
parameter QQ8_5 = 4096/Q8_5;
parameter QQ8_6 = 4096/Q8_6;
parameter QQ8_7 = 4096/Q8_7;
parameter QQ8_8 = 4096/Q8_8;
wire [12:0] QM1_1 = QQ1_1;
wire [12:0] QM1_2 = QQ1_2;
wire [12:0] QM1_3 = QQ1_3;
wire [12:0] QM1_4 = QQ1_4;
wire [12:0] QM1_5 = QQ1_5;
wire [12:0] QM1_6 = QQ1_6;
wire [12:0] QM1_7 = QQ1_7;
wire [12:0] QM1_8 = QQ1_8;
wire [12:0] QM2_1 = QQ2_1;
wire [12:0] QM2_2 = QQ2_2;
wire [12:0] QM2_3 = QQ2_3;
wire [12:0] QM2_4 = QQ2_4;
wire [12:0] QM2_5 = QQ2_5;
wire [12:0] QM2_6 = QQ2_6;
wire [12:0] QM2_7 = QQ2_7;
wire [12:0] QM2_8 = QQ2_8;
wire [12:0] QM3_1 = QQ3_1;
wire [12:0] QM3_2 = QQ3_2;
wire [12:0] QM3_3 = QQ3_3;
wire [12:0] QM3_4 = QQ3_4;
wire [12:0] QM3_5 = QQ3_5;
wire [12:0] QM3_6 = QQ3_6;
wire [12:0] QM3_7 = QQ3_7;
wire [12:0] QM3_8 = QQ3_8;
wire [12:0] QM4_1 = QQ4_1;
wire [12:0] QM4_2 = QQ4_2;
wire [12:0] QM4_3 = QQ4_3;
wire [12:0] QM4_4 = QQ4_4;
wire [12:0] QM4_5 = QQ4_5;
wire [12:0] QM4_6 = QQ4_6;
wire [12:0] QM4_7 = QQ4_7;
wire [12:0] QM4_8 = QQ4_8;
wire [12:0] QM5_1 = QQ5_1;
wire [12:0] QM5_2 = QQ5_2;
wire [12:0] QM5_3 = QQ5_3;
wire [12:0] QM5_4 = QQ5_4;
wire [12:0] QM5_5 = QQ5_5;
wire [12:0] QM5_6 = QQ5_6;
wire [12:0] QM5_7 = QQ5_7;
wire [12:0] QM5_8 = QQ5_8;
wire [12:0] QM6_1 = QQ6_1;
wire [12:0] QM6_2 = QQ6_2;
wire [12:0] QM6_3 = QQ6_3;
wire [12:0] QM6_4 = QQ6_4;
wire [12:0] QM6_5 = QQ6_5;
wire [12:0] QM6_6 = QQ6_6;
wire [12:0] QM6_7 = QQ6_7;
wire [12:0] QM6_8 = QQ6_8;
wire [12:0] QM7_1 = QQ7_1;
wire [12:0] QM7_2 = QQ7_2;
wire [12:0] QM7_3 = QQ7_3;
wire [12:0] QM7_4 = QQ7_4;
wire [12:0] QM7_5 = QQ7_5;
wire [12:0] QM7_6 = QQ7_6;
wire [12:0] QM7_7 = QQ7_7;
wire [12:0] QM7_8 = QQ7_8;
wire [12:0] QM8_1 = QQ8_1;
wire [12:0] QM8_2 = QQ8_2;
wire [12:0] QM8_3 = QQ8_3;
wire [12:0] QM8_4 = QQ8_4;
wire [12:0] QM8_5 = QQ8_5;
wire [12:0] QM8_6 = QQ8_6;
wire [12:0] QM8_7 = QQ8_7;
wire [12:0] QM8_8 = QQ8_8;
reg [22:0] Z11_temp, Z12_temp, Z13_temp, Z14_temp, Z15_temp, Z16_temp, Z17_temp, Z18_temp;
reg [22:0] Z21_temp, Z22_temp, Z23_temp, Z24_temp, Z25_temp, Z26_temp, Z27_temp, Z28_temp;
reg [22:0] Z31_temp, Z32_temp, Z33_temp, Z34_temp, Z35_temp, Z36_temp, Z37_temp, Z38_temp;
reg [22:0] Z41_temp, Z42_temp, Z43_temp, Z44_temp, Z45_temp, Z46_temp, Z47_temp, Z48_temp;
reg [22:0] Z51_temp, Z52_temp, Z53_temp, Z54_temp, Z55_temp, Z56_temp, Z57_temp, Z58_temp;
reg [22:0] Z61_temp, Z62_temp, Z63_temp, Z64_temp, Z65_temp, Z66_temp, Z67_temp, Z68_temp;
reg [22:0] Z71_temp, Z72_temp, Z73_temp, Z74_temp, Z75_temp, Z76_temp, Z77_temp, Z78_temp;
reg [22:0] Z81_temp, Z82_temp, Z83_temp, Z84_temp, Z85_temp, Z86_temp, Z87_temp, Z88_temp;
reg [22:0] Z11_temp_1, Z12_temp_1, Z13_temp_1, Z14_temp_1, Z15_temp_1, Z16_temp_1, Z17_temp_1, Z18_temp_1;
reg [22:0] Z21_temp_1, Z22_temp_1, Z23_temp_1, Z24_temp_1, Z25_temp_1, Z26_temp_1, Z27_temp_1, Z28_temp_1;
reg [22:0] Z31_temp_1, Z32_temp_1, Z33_temp_1, Z34_temp_1, Z35_temp_1, Z36_temp_1, Z37_temp_1, Z38_temp_1;
reg [22:0] Z41_temp_1, Z42_temp_1, Z43_temp_1, Z44_temp_1, Z45_temp_1, Z46_temp_1, Z47_temp_1, Z48_temp_1;
reg [22:0] Z51_temp_1, Z52_temp_1, Z53_temp_1, Z54_temp_1, Z55_temp_1, Z56_temp_1, Z57_temp_1, Z58_temp_1;
reg [22:0] Z61_temp_1, Z62_temp_1, Z63_temp_1, Z64_temp_1, Z65_temp_1, Z66_temp_1, Z67_temp_1, Z68_temp_1;
reg [22:0] Z71_temp_1, Z72_temp_1, Z73_temp_1, Z74_temp_1, Z75_temp_1, Z76_temp_1, Z77_temp_1, Z78_temp_1;
reg [22:0] Z81_temp_1, Z82_temp_1, Z83_temp_1, Z84_temp_1, Z85_temp_1, Z86_temp_1, Z87_temp_1, Z88_temp_1;
reg [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18;
reg [10:0] Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28;
reg [10:0] Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38;
reg [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48;
reg [10:0] Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58;
reg [10:0] Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68;
reg [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78;
reg [10:0] Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88;
reg out_enable, enable_1, enable_2, enable_3;
integer Z11_int, Z12_int, Z13_int, Z14_int, Z15_int, Z16_int, Z17_int, Z18_int;
integer Z21_int, Z22_int, Z23_int, Z24_int, Z25_int, Z26_int, Z27_int, Z28_int;
integer Z31_int, Z32_int, Z33_int, Z34_int, Z35_int, Z36_int, Z37_int, Z38_int;
integer Z41_int, Z42_int, Z43_int, Z44_int, Z45_int, Z46_int, Z47_int, Z48_int;
integer Z51_int, Z52_int, Z53_int, Z54_int, Z55_int, Z56_int, Z57_int, Z58_int;
integer Z61_int, Z62_int, Z63_int, Z64_int, Z65_int, Z66_int, Z67_int, Z68_int;
integer Z71_int, Z72_int, Z73_int, Z74_int, Z75_int, Z76_int, Z77_int, Z78_int;
integer Z81_int, Z82_int, Z83_int, Z84_int, Z85_int, Z86_int, Z87_int, Z88_int;
always @(posedge clk)
begin
if (rst) begin
Z11_int <= 0; Z12_int <= 0; Z13_int <= 0; Z14_int <= 0;
Z15_int <= 0; Z16_int <= 0; Z17_int <= 0; Z18_int <= 0;
Z21_int <= 0; Z22_int <= 0; Z23_int <= 0; Z24_int <= 0;
Z25_int <= 0; Z26_int <= 0; Z27_int <= 0; Z28_int <= 0;
Z31_int <= 0; Z32_int <= 0; Z33_int <= 0; Z34_int <= 0;
Z35_int <= 0; Z36_int <= 0; Z37_int <= 0; Z38_int <= 0;
Z41_int <= 0; Z42_int <= 0; Z43_int <= 0; Z44_int <= 0;
Z45_int <= 0; Z46_int <= 0; Z47_int <= 0; Z48_int <= 0;
Z51_int <= 0; Z52_int <= 0; Z53_int <= 0; Z54_int <= 0;
Z55_int <= 0; Z56_int <= 0; Z57_int <= 0; Z58_int <= 0;
Z61_int <= 0; Z62_int <= 0; Z63_int <= 0; Z64_int <= 0;
Z65_int <= 0; Z66_int <= 0; Z67_int <= 0; Z68_int <= 0;
Z71_int <= 0; Z72_int <= 0; Z73_int <= 0; Z74_int <= 0;
Z75_int <= 0; Z76_int <= 0; Z77_int <= 0; Z78_int <= 0;
Z81_int <= 0; Z82_int <= 0; Z83_int <= 0; Z84_int <= 0;
Z85_int <= 0; Z86_int <= 0; Z87_int <= 0; Z88_int <= 0;
end
else if (enable) begin
Z11_int[10:0] <= Z11; Z12_int[10:0] <= Z12; Z13_int[10:0] <= Z13; Z14_int[10:0] <= Z14;
Z15_int[10:0] <= Z15; Z16_int[10:0] <= Z16; Z17_int[10:0] <= Z17; Z18_int[10:0] <= Z18;
Z21_int[10:0] <= Z21; Z22_int[10:0] <= Z22; Z23_int[10:0] <= Z23; Z24_int[10:0] <= Z24;
Z25_int[10:0] <= Z25; Z26_int[10:0] <= Z26; Z27_int[10:0] <= Z27; Z28_int[10:0] <= Z28;
Z31_int[10:0] <= Z31; Z32_int[10:0] <= Z32; Z33_int[10:0] <= Z33; Z34_int[10:0] <= Z34;
Z35_int[10:0] <= Z35; Z36_int[10:0] <= Z36; Z37_int[10:0] <= Z37; Z38_int[10:0] <= Z38;
Z41_int[10:0] <= Z41; Z42_int[10:0] <= Z42; Z43_int[10:0] <= Z43; Z44_int[10:0] <= Z44;
Z45_int[10:0] <= Z45; Z46_int[10:0] <= Z46; Z47_int[10:0] <= Z47; Z48_int[10:0] <= Z48;
Z51_int[10:0] <= Z51; Z52_int[10:0] <= Z52; Z53_int[10:0] <= Z53; Z54_int[10:0] <= Z54;
Z55_int[10:0] <= Z55; Z56_int[10:0] <= Z56; Z57_int[10:0] <= Z57; Z58_int[10:0] <= Z58;
Z61_int[10:0] <= Z61; Z62_int[10:0] <= Z62; Z63_int[10:0] <= Z63; Z64_int[10:0] <= Z64;
Z65_int[10:0] <= Z65; Z66_int[10:0] <= Z66; Z67_int[10:0] <= Z67; Z68_int[10:0] <= Z68;
Z71_int[10:0] <= Z71; Z72_int[10:0] <= Z72; Z73_int[10:0] <= Z73; Z74_int[10:0] <= Z74;
Z75_int[10:0] <= Z75; Z76_int[10:0] <= Z76; Z77_int[10:0] <= Z77; Z78_int[10:0] <= Z78;
Z81_int[10:0] <= Z81; Z82_int[10:0] <= Z82; Z83_int[10:0] <= Z83; Z84_int[10:0] <= Z84;
Z85_int[10:0] <= Z85; Z86_int[10:0] <= Z86; Z87_int[10:0] <= Z87; Z88_int[10:0] <= Z88;
// sign extend to make Z11_int a twos complement representation of Z11
Z11_int[31:11] <= Z11[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z12_int[31:11] <= Z12[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z13_int[31:11] <= Z13[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z14_int[31:11] <= Z14[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z15_int[31:11] <= Z15[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z16_int[31:11] <= Z16[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z17_int[31:11] <= Z17[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z18_int[31:11] <= Z18[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z21_int[31:11] <= Z21[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z22_int[31:11] <= Z22[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z23_int[31:11] <= Z23[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z24_int[31:11] <= Z24[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z25_int[31:11] <= Z25[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z26_int[31:11] <= Z26[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z27_int[31:11] <= Z27[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z28_int[31:11] <= Z28[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z31_int[31:11] <= Z31[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z32_int[31:11] <= Z32[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z33_int[31:11] <= Z33[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z34_int[31:11] <= Z34[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z35_int[31:11] <= Z35[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z36_int[31:11] <= Z36[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z37_int[31:11] <= Z37[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z38_int[31:11] <= Z38[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z41_int[31:11] <= Z41[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z42_int[31:11] <= Z42[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z43_int[31:11] <= Z43[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z44_int[31:11] <= Z44[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z45_int[31:11] <= Z45[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z46_int[31:11] <= Z46[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z47_int[31:11] <= Z47[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z48_int[31:11] <= Z48[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z51_int[31:11] <= Z51[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z52_int[31:11] <= Z52[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z53_int[31:11] <= Z53[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z54_int[31:11] <= Z54[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z55_int[31:11] <= Z55[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z56_int[31:11] <= Z56[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z57_int[31:11] <= Z57[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z58_int[31:11] <= Z58[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z61_int[31:11] <= Z61[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z62_int[31:11] <= Z62[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z63_int[31:11] <= Z63[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z64_int[31:11] <= Z64[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z65_int[31:11] <= Z65[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z66_int[31:11] <= Z66[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z67_int[31:11] <= Z67[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z68_int[31:11] <= Z68[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z71_int[31:11] <= Z71[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z72_int[31:11] <= Z72[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z73_int[31:11] <= Z73[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z74_int[31:11] <= Z74[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z75_int[31:11] <= Z75[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z76_int[31:11] <= Z76[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z77_int[31:11] <= Z77[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z78_int[31:11] <= Z78[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z81_int[31:11] <= Z81[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z82_int[31:11] <= Z82[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z83_int[31:11] <= Z83[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z84_int[31:11] <= Z84[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z85_int[31:11] <= Z85[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z86_int[31:11] <= Z86[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z87_int[31:11] <= Z87[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Z88_int[31:11] <= Z88[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
end
end
always @(posedge clk)
begin
if (rst) begin
Z11_temp <= 0; Z12_temp <= 0; Z13_temp <= 0; Z14_temp <= 0;
Z12_temp <= 0; Z16_temp <= 0; Z17_temp <= 0; Z18_temp <= 0;
Z21_temp <= 0; Z22_temp <= 0; Z23_temp <= 0; Z24_temp <= 0;
Z22_temp <= 0; Z26_temp <= 0; Z27_temp <= 0; Z28_temp <= 0;
Z31_temp <= 0; Z32_temp <= 0; Z33_temp <= 0; Z34_temp <= 0;
Z32_temp <= 0; Z36_temp <= 0; Z37_temp <= 0; Z38_temp <= 0;
Z41_temp <= 0; Z42_temp <= 0; Z43_temp <= 0; Z44_temp <= 0;
Z42_temp <= 0; Z46_temp <= 0; Z47_temp <= 0; Z48_temp <= 0;
Z51_temp <= 0; Z52_temp <= 0; Z53_temp <= 0; Z54_temp <= 0;
Z52_temp <= 0; Z56_temp <= 0; Z57_temp <= 0; Z58_temp <= 0;
Z61_temp <= 0; Z62_temp <= 0; Z63_temp <= 0; Z64_temp <= 0;
Z62_temp <= 0; Z66_temp <= 0; Z67_temp <= 0; Z68_temp <= 0;
Z71_temp <= 0; Z72_temp <= 0; Z73_temp <= 0; Z74_temp <= 0;
Z72_temp <= 0; Z76_temp <= 0; Z77_temp <= 0; Z78_temp <= 0;
Z81_temp <= 0; Z82_temp <= 0; Z83_temp <= 0; Z84_temp <= 0;
Z82_temp <= 0; Z86_temp <= 0; Z87_temp <= 0; Z88_temp <= 0;
end
else if (enable_1) begin
Z11_temp <= Z11_int * QM1_1; Z12_temp <= Z12_int * QM1_2;
Z13_temp <= Z13_int * QM1_3; Z14_temp <= Z14_int * QM1_4;
Z15_temp <= Z15_int * QM1_5; Z16_temp <= Z16_int * QM1_6;
Z17_temp <= Z17_int * QM1_7; Z18_temp <= Z18_int * QM1_8;
Z21_temp <= Z21_int * QM2_1; Z22_temp <= Z22_int * QM2_2;
Z23_temp <= Z23_int * QM2_3; Z24_temp <= Z24_int * QM2_4;
Z25_temp <= Z25_int * QM2_5; Z26_temp <= Z26_int * QM2_6;
Z27_temp <= Z27_int * QM2_7; Z28_temp <= Z28_int * QM2_8;
Z31_temp <= Z31_int * QM3_1; Z32_temp <= Z32_int * QM3_2;
Z33_temp <= Z33_int * QM3_3; Z34_temp <= Z34_int * QM3_4;
Z35_temp <= Z35_int * QM3_5; Z36_temp <= Z36_int * QM3_6;
Z37_temp <= Z37_int * QM3_7; Z38_temp <= Z38_int * QM3_8;
Z41_temp <= Z41_int * QM4_1; Z42_temp <= Z42_int * QM4_2;
Z43_temp <= Z43_int * QM4_3; Z44_temp <= Z44_int * QM4_4;
Z45_temp <= Z45_int * QM4_5; Z46_temp <= Z46_int * QM4_6;
Z47_temp <= Z47_int * QM4_7; Z48_temp <= Z48_int * QM4_8;
Z51_temp <= Z51_int * QM5_1; Z52_temp <= Z52_int * QM5_2;
Z53_temp <= Z53_int * QM5_3; Z54_temp <= Z54_int * QM5_4;
Z55_temp <= Z55_int * QM5_5; Z56_temp <= Z56_int * QM5_6;
Z57_temp <= Z57_int * QM5_7; Z58_temp <= Z58_int * QM5_8;
Z61_temp <= Z61_int * QM6_1; Z62_temp <= Z62_int * QM6_2;
Z63_temp <= Z63_int * QM6_3; Z64_temp <= Z64_int * QM6_4;
Z65_temp <= Z65_int * QM6_5; Z66_temp <= Z66_int * QM6_6;
Z67_temp <= Z67_int * QM6_7; Z68_temp <= Z68_int * QM6_8;
Z71_temp <= Z71_int * QM7_1; Z72_temp <= Z72_int * QM7_2;
Z73_temp <= Z73_int * QM7_3; Z74_temp <= Z74_int * QM7_4;
Z75_temp <= Z75_int * QM7_5; Z76_temp <= Z76_int * QM7_6;
Z77_temp <= Z77_int * QM7_7; Z78_temp <= Z78_int * QM7_8;
Z81_temp <= Z81_int * QM8_1; Z82_temp <= Z82_int * QM8_2;
Z83_temp <= Z83_int * QM8_3; Z84_temp <= Z84_int * QM8_4;
Z85_temp <= Z85_int * QM8_5; Z86_temp <= Z86_int * QM8_6;
Z87_temp <= Z87_int * QM8_7; Z88_temp <= Z88_int * QM8_8;
end
end
always @(posedge clk)
begin
if (rst) begin
Z11_temp_1 <= 0; Z12_temp_1 <= 0; Z13_temp_1 <= 0; Z14_temp_1 <= 0;
Z12_temp_1 <= 0; Z16_temp_1 <= 0; Z17_temp_1 <= 0; Z18_temp_1 <= 0;
Z21_temp_1 <= 0; Z22_temp_1 <= 0; Z23_temp_1 <= 0; Z24_temp_1 <= 0;
Z22_temp_1 <= 0; Z26_temp_1 <= 0; Z27_temp_1 <= 0; Z28_temp_1 <= 0;
Z31_temp_1 <= 0; Z32_temp_1 <= 0; Z33_temp_1 <= 0; Z34_temp_1 <= 0;
Z32_temp_1 <= 0; Z36_temp_1 <= 0; Z37_temp_1 <= 0; Z38_temp_1 <= 0;
Z41_temp_1 <= 0; Z42_temp_1 <= 0; Z43_temp_1 <= 0; Z44_temp_1 <= 0;
Z42_temp_1 <= 0; Z46_temp_1 <= 0; Z47_temp_1 <= 0; Z48_temp_1 <= 0;
Z51_temp_1 <= 0; Z52_temp_1 <= 0; Z53_temp_1 <= 0; Z54_temp_1 <= 0;
Z52_temp_1 <= 0; Z56_temp_1 <= 0; Z57_temp_1 <= 0; Z58_temp_1 <= 0;
Z61_temp_1 <= 0; Z62_temp_1 <= 0; Z63_temp_1 <= 0; Z64_temp_1 <= 0;
Z62_temp_1 <= 0; Z66_temp_1 <= 0; Z67_temp_1 <= 0; Z68_temp_1 <= 0;
Z71_temp_1 <= 0; Z72_temp_1 <= 0; Z73_temp_1 <= 0; Z74_temp_1 <= 0;
Z72_temp_1 <= 0; Z76_temp_1 <= 0; Z77_temp_1 <= 0; Z78_temp_1 <= 0;
Z81_temp_1 <= 0; Z82_temp_1 <= 0; Z83_temp_1 <= 0; Z84_temp_1 <= 0;
Z82_temp_1 <= 0; Z86_temp_1 <= 0; Z87_temp_1 <= 0; Z88_temp_1 <= 0;
end
else if (enable_2) begin
Z11_temp_1 <= Z11_temp; Z12_temp_1 <= Z12_temp;
Z13_temp_1 <= Z13_temp; Z14_temp_1 <= Z14_temp;
Z15_temp_1 <= Z15_temp; Z16_temp_1 <= Z16_temp;
Z17_temp_1 <= Z17_temp; Z18_temp_1 <= Z18_temp;
Z21_temp_1 <= Z21_temp; Z22_temp_1 <= Z22_temp;
Z23_temp_1 <= Z23_temp; Z24_temp_1 <= Z24_temp;
Z25_temp_1 <= Z25_temp; Z26_temp_1 <= Z26_temp;
Z27_temp_1 <= Z27_temp; Z28_temp_1 <= Z28_temp;
Z31_temp_1 <= Z31_temp; Z32_temp_1 <= Z32_temp;
Z33_temp_1 <= Z33_temp; Z34_temp_1 <= Z34_temp;
Z35_temp_1 <= Z35_temp; Z36_temp_1 <= Z36_temp;
Z37_temp_1 <= Z37_temp; Z38_temp_1 <= Z38_temp;
Z41_temp_1 <= Z41_temp; Z42_temp_1 <= Z42_temp;
Z43_temp_1 <= Z43_temp; Z44_temp_1 <= Z44_temp;
Z45_temp_1 <= Z45_temp; Z46_temp_1 <= Z46_temp;
Z47_temp_1 <= Z47_temp; Z48_temp_1 <= Z48_temp;
Z51_temp_1 <= Z51_temp; Z52_temp_1 <= Z52_temp;
Z53_temp_1 <= Z53_temp; Z54_temp_1 <= Z54_temp;
Z55_temp_1 <= Z55_temp; Z56_temp_1 <= Z56_temp;
Z57_temp_1 <= Z57_temp; Z58_temp_1 <= Z58_temp;
Z61_temp_1 <= Z61_temp; Z62_temp_1 <= Z62_temp;
Z63_temp_1 <= Z63_temp; Z64_temp_1 <= Z64_temp;
Z65_temp_1 <= Z65_temp; Z66_temp_1 <= Z66_temp;
Z67_temp_1 <= Z67_temp; Z68_temp_1 <= Z68_temp;
Z71_temp_1 <= Z71_temp; Z72_temp_1 <= Z72_temp;
Z73_temp_1 <= Z73_temp; Z74_temp_1 <= Z74_temp;
Z75_temp_1 <= Z75_temp; Z76_temp_1 <= Z76_temp;
Z77_temp_1 <= Z77_temp; Z78_temp_1 <= Z78_temp;
Z81_temp_1 <= Z81_temp; Z82_temp_1 <= Z82_temp;
Z83_temp_1 <= Z83_temp; Z84_temp_1 <= Z84_temp;
Z85_temp_1 <= Z85_temp; Z86_temp_1 <= Z86_temp;
Z87_temp_1 <= Z87_temp; Z88_temp_1 <= Z88_temp;
end
end
always @(posedge clk)
begin
if (rst) begin
Q11 <= 0; Q12 <= 0; Q13 <= 0; Q14 <= 0; Q15 <= 0; Q16 <= 0; Q17 <= 0; Q18 <= 0;
Q21 <= 0; Q22 <= 0; Q23 <= 0; Q24 <= 0; Q25 <= 0; Q26 <= 0; Q27 <= 0; Q28 <= 0;
Q31 <= 0; Q32 <= 0; Q33 <= 0; Q34 <= 0; Q35 <= 0; Q36 <= 0; Q37 <= 0; Q38 <= 0;
Q41 <= 0; Q42 <= 0; Q43 <= 0; Q44 <= 0; Q45 <= 0; Q46 <= 0; Q47 <= 0; Q48 <= 0;
Q51 <= 0; Q52 <= 0; Q53 <= 0; Q54 <= 0; Q55 <= 0; Q56 <= 0; Q57 <= 0; Q58 <= 0;
Q61 <= 0; Q62 <= 0; Q63 <= 0; Q64 <= 0; Q65 <= 0; Q66 <= 0; Q67 <= 0; Q68 <= 0;
Q71 <= 0; Q72 <= 0; Q73 <= 0; Q74 <= 0; Q75 <= 0; Q76 <= 0; Q77 <= 0; Q78 <= 0;
Q81 <= 0; Q82 <= 0; Q83 <= 0; Q84 <= 0; Q85 <= 0; Q86 <= 0; Q87 <= 0; Q88 <= 0;
end
else if (enable_3) begin
// rounding Q11 based on the bit in the 11th place of Z11_temp
Q11 <= Z11_temp_1[11] ? Z11_temp_1[22:12] + 1 : Z11_temp_1[22:12];
Q12 <= Z12_temp_1[11] ? Z12_temp_1[22:12] + 1 : Z12_temp_1[22:12];
Q13 <= Z13_temp_1[11] ? Z13_temp_1[22:12] + 1 : Z13_temp_1[22:12];
Q14 <= Z14_temp_1[11] ? Z14_temp_1[22:12] + 1 : Z14_temp_1[22:12];
Q15 <= Z15_temp_1[11] ? Z15_temp_1[22:12] + 1 : Z15_temp_1[22:12];
Q16 <= Z16_temp_1[11] ? Z16_temp_1[22:12] + 1 : Z16_temp_1[22:12];
Q17 <= Z17_temp_1[11] ? Z17_temp_1[22:12] + 1 : Z17_temp_1[22:12];
Q18 <= Z18_temp_1[11] ? Z18_temp_1[22:12] + 1 : Z18_temp_1[22:12];
Q21 <= Z21_temp_1[11] ? Z21_temp_1[22:12] + 1 : Z21_temp_1[22:12];
Q22 <= Z22_temp_1[11] ? Z22_temp_1[22:12] + 1 : Z22_temp_1[22:12];
Q23 <= Z23_temp_1[11] ? Z23_temp_1[22:12] + 1 : Z23_temp_1[22:12];
Q24 <= Z24_temp_1[11] ? Z24_temp_1[22:12] + 1 : Z24_temp_1[22:12];
Q25 <= Z25_temp_1[11] ? Z25_temp_1[22:12] + 1 : Z25_temp_1[22:12];
Q26 <= Z26_temp_1[11] ? Z26_temp_1[22:12] + 1 : Z26_temp_1[22:12];
Q27 <= Z27_temp_1[11] ? Z27_temp_1[22:12] + 1 : Z27_temp_1[22:12];
Q28 <= Z28_temp_1[11] ? Z28_temp_1[22:12] + 1 : Z28_temp_1[22:12];
Q31 <= Z31_temp_1[11] ? Z31_temp_1[22:12] + 1 : Z31_temp_1[22:12];
Q32 <= Z32_temp_1[11] ? Z32_temp_1[22:12] + 1 : Z32_temp_1[22:12];
Q33 <= Z33_temp_1[11] ? Z33_temp_1[22:12] + 1 : Z33_temp_1[22:12];
Q34 <= Z34_temp_1[11] ? Z34_temp_1[22:12] + 1 : Z34_temp_1[22:12];
Q35 <= Z35_temp_1[11] ? Z35_temp_1[22:12] + 1 : Z35_temp_1[22:12];
Q36 <= Z36_temp_1[11] ? Z36_temp_1[22:12] + 1 : Z36_temp_1[22:12];
Q37 <= Z37_temp_1[11] ? Z37_temp_1[22:12] + 1 : Z37_temp_1[22:12];
Q38 <= Z38_temp_1[11] ? Z38_temp_1[22:12] + 1 : Z38_temp_1[22:12];
Q41 <= Z41_temp_1[11] ? Z41_temp_1[22:12] + 1 : Z41_temp_1[22:12];
Q42 <= Z42_temp_1[11] ? Z42_temp_1[22:12] + 1 : Z42_temp_1[22:12];
Q43 <= Z43_temp_1[11] ? Z43_temp_1[22:12] + 1 : Z43_temp_1[22:12];
Q44 <= Z44_temp_1[11] ? Z44_temp_1[22:12] + 1 : Z44_temp_1[22:12];
Q45 <= Z45_temp_1[11] ? Z45_temp_1[22:12] + 1 : Z45_temp_1[22:12];
Q46 <= Z46_temp_1[11] ? Z46_temp_1[22:12] + 1 : Z46_temp_1[22:12];
Q47 <= Z47_temp_1[11] ? Z47_temp_1[22:12] + 1 : Z47_temp_1[22:12];
Q48 <= Z48_temp_1[11] ? Z48_temp_1[22:12] + 1 : Z48_temp_1[22:12];
Q51 <= Z51_temp_1[11] ? Z51_temp_1[22:12] + 1 : Z51_temp_1[22:12];
Q52 <= Z52_temp_1[11] ? Z52_temp_1[22:12] + 1 : Z52_temp_1[22:12];
Q53 <= Z53_temp_1[11] ? Z53_temp_1[22:12] + 1 : Z53_temp_1[22:12];
Q54 <= Z54_temp_1[11] ? Z54_temp_1[22:12] + 1 : Z54_temp_1[22:12];
Q55 <= Z55_temp_1[11] ? Z55_temp_1[22:12] + 1 : Z55_temp_1[22:12];
Q56 <= Z56_temp_1[11] ? Z56_temp_1[22:12] + 1 : Z56_temp_1[22:12];
Q57 <= Z57_temp_1[11] ? Z57_temp_1[22:12] + 1 : Z57_temp_1[22:12];
Q58 <= Z58_temp_1[11] ? Z58_temp_1[22:12] + 1 : Z58_temp_1[22:12];
Q61 <= Z61_temp_1[11] ? Z61_temp_1[22:12] + 1 : Z61_temp_1[22:12];
Q62 <= Z62_temp_1[11] ? Z62_temp_1[22:12] + 1 : Z62_temp_1[22:12];
Q63 <= Z63_temp_1[11] ? Z63_temp_1[22:12] + 1 : Z63_temp_1[22:12];
Q64 <= Z64_temp_1[11] ? Z64_temp_1[22:12] + 1 : Z64_temp_1[22:12];
Q65 <= Z65_temp_1[11] ? Z65_temp_1[22:12] + 1 : Z65_temp_1[22:12];
Q66 <= Z66_temp_1[11] ? Z66_temp_1[22:12] + 1 : Z66_temp_1[22:12];
Q67 <= Z67_temp_1[11] ? Z67_temp_1[22:12] + 1 : Z67_temp_1[22:12];
Q68 <= Z68_temp_1[11] ? Z68_temp_1[22:12] + 1 : Z68_temp_1[22:12];
Q71 <= Z71_temp_1[11] ? Z71_temp_1[22:12] + 1 : Z71_temp_1[22:12];
Q72 <= Z72_temp_1[11] ? Z72_temp_1[22:12] + 1 : Z72_temp_1[22:12];
Q73 <= Z73_temp_1[11] ? Z73_temp_1[22:12] + 1 : Z73_temp_1[22:12];
Q74 <= Z74_temp_1[11] ? Z74_temp_1[22:12] + 1 : Z74_temp_1[22:12];
Q75 <= Z75_temp_1[11] ? Z75_temp_1[22:12] + 1 : Z75_temp_1[22:12];
Q76 <= Z76_temp_1[11] ? Z76_temp_1[22:12] + 1 : Z76_temp_1[22:12];
Q77 <= Z77_temp_1[11] ? Z77_temp_1[22:12] + 1 : Z77_temp_1[22:12];
Q78 <= Z78_temp_1[11] ? Z78_temp_1[22:12] + 1 : Z78_temp_1[22:12];
Q81 <= Z81_temp_1[11] ? Z81_temp_1[22:12] + 1 : Z81_temp_1[22:12];
Q82 <= Z82_temp_1[11] ? Z82_temp_1[22:12] + 1 : Z82_temp_1[22:12];
Q83 <= Z83_temp_1[11] ? Z83_temp_1[22:12] + 1 : Z83_temp_1[22:12];
Q84 <= Z84_temp_1[11] ? Z84_temp_1[22:12] + 1 : Z84_temp_1[22:12];
Q85 <= Z85_temp_1[11] ? Z85_temp_1[22:12] + 1 : Z85_temp_1[22:12];
Q86 <= Z86_temp_1[11] ? Z86_temp_1[22:12] + 1 : Z86_temp_1[22:12];
Q87 <= Z87_temp_1[11] ? Z87_temp_1[22:12] + 1 : Z87_temp_1[22:12];
Q88 <= Z88_temp_1[11] ? Z88_temp_1[22:12] + 1 : Z88_temp_1[22:12];
end
end
/* enable_1 is delayed one clock cycle from enable, and it's used to
enable the logic that needs to execute on the clock cycle after enable goes high
enable_2 is delayed two clock cycles, and out_enable signals the next module
that its input data is ready*/
always @(posedge clk)
begin
if (rst) begin
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0;
out_enable <= 0;
end
else begin
enable_1 <= enable; enable_2 <= enable_1;
enable_3 <= enable_2;
out_enable <= enable_3;
end
end
endmodule |
module blake2s_G(
input wire [31 : 0] a,
input wire [31 : 0] b,
input wire [31 : 0] c,
input wire [31 : 0] d,
input wire [31 : 0] m0,
input wire [31 : 0] m1,
output wire [31 : 0] a_prim,
output wire [31 : 0] b_prim,
output wire [31 : 0] c_prim,
output wire [31 : 0] d_prim
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] a1;
reg [31 : 0] a2;
reg [31 : 0] b1;
reg [31 : 0] b2;
reg [31 : 0] b3;
reg [31 : 0] b4;
reg [31 : 0] c1;
reg [31 : 0] c2;
reg [31 : 0] d1;
reg [31 : 0] d2;
reg [31 : 0] d3;
reg [31 : 0] d4;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = a2;
assign b_prim = b4;
assign c_prim = c2;
assign d_prim = d4;
//----------------------------------------------------------------
// G_function
//----------------------------------------------------------------
always @*
begin : G_function
a1 = a + b + m0;
d1 = d ^ a1;
d2 = {d1[15 : 0], d1[31 : 16]};
c1 = c + d2;
b1 = b ^ c1;
b2 = {b1[11 : 0], b1[31 : 12]};
a2 = a1 + b2 + m1;
d3 = d2 ^ a2;
d4 = {d3[7 : 0], d3[31 : 8]};
c2 = c1 + d4;
b3 = b2 ^ c2;
b4 = {b3[6 : 0], b3[31 : 7]};
end // G_function
endmodule // blake2s_G |
module FF(input clk,input d, output q );
sky130_fd_sc_hd__dfxtp_4 x (
.Q(qw) ,
.CLK(clk),
.D(d)
);
sky130_fd_sc_hd__inv_1 inv(
.Y(q),
.A(qw)
);
endmodule |
module spi_master
#(parameter DATA_WIDTH=16,
NUM_PORTS=1,
CLK_DIVIDER_WIDTH=8,
SAMPLE_PHASE=0
)
(input clk,
input resetb,
input CPOL,
input CPHA,
input [CLK_DIVIDER_WIDTH-1:0] clk_divider,
input go,
input [(NUM_PORTS*DATA_WIDTH)-1:0] datai,
output [(NUM_PORTS*DATA_WIDTH)-1:0] datao,
output reg busy,
output reg done,
input [NUM_PORTS-1:0] dout,
output [NUM_PORTS-1:0] din,
output reg csb,
output reg sclk
);
reg [CLK_DIVIDER_WIDTH-1:0] clk_count;
wire [CLK_DIVIDER_WIDTH-1:0] next_clk_count = clk_count + 1;
wire pulse = next_clk_count == (clk_divider >> 1);
reg state;
`ifdef verilator
localparam LOG2_DATA_WIDTH = $clog2(DATA_WIDTH+1);
`else
function integer log2;
input integer value;
integer count;
begin
value = value-1;
for (count=0; value>0; count=count+1)
value = value>>1;
log2=count;
end
endfunction
localparam LOG2_DATA_WIDTH = log2(DATA_WIDTH+1);
`endif
reg [LOG2_DATA_WIDTH:0] shift_count;
wire start = shift_count == 0;
/* verilator lint_off WIDTH */
wire stop = shift_count >= 2*DATA_WIDTH-1;
/* verilator lint_on WIDTH */
reg stop_s;
localparam IDLE_STATE = 0,
RUN_STATE = 1;
sro #(.DATA_WIDTH(DATA_WIDTH)) sro[NUM_PORTS-1:0]
(.clk(clk),
.resetb(resetb),
.shift(pulse && !csb && (shift_count[0] == SAMPLE_PHASE) && !stop_s),
.dout(dout),
.datao(datao));
sri #(.DATA_WIDTH(DATA_WIDTH)) sri[NUM_PORTS-1:0]
(.clk(clk),
.resetb(resetb),
.datai(datai),
.sample(go && (state == IDLE_STATE)), // we condition on state so that if the user holds 'go' high, this will sample only at the start of the transfer
.shift(pulse && !csb && (shift_count[0] == 1) && !stop),
.din(din));
`ifdef SYNC_RESET
always @(posedge clk) begin
`else
always @(posedge clk or negedge resetb) begin
`endif
if(!resetb) begin
clk_count <= 0;
shift_count <= 0;
sclk <= 1;
csb <= 1;
state <= IDLE_STATE;
busy <= 0;
done <= 0;
stop_s <= 0;
end else begin
// generate the pulse train
if(pulse) begin
clk_count <= 0;
stop_s <= stop;
end else begin
clk_count <= next_clk_count;
end
// generate csb
if(state == IDLE_STATE) begin
csb <= 1;
shift_count <= 0;
done <= 0;
if(go && !busy) begin // the !busy condition here allows the user to hold go high and this will then run transactions back-to-back at maximum speed where busy drops at for at least one clock cycle but we stay in this idle state for two clock cycles. Staying in idle state for two cycles probably isn't a big deal since the serial clock is running slower anyway.
state <= RUN_STATE;
busy <= 1;
end else begin
busy <= 0;
end
end else begin
if(pulse) begin
if(stop) begin
//csb <= 1;
if(done) begin
state <= IDLE_STATE;
done <= 0;
busy <= 0;
end else begin
done <= 1;
end
end else begin
csb <= 0;
if(!csb) begin
shift_count <= shift_count + 1;
end
end
end
end
// generate sclk
if(pulse) begin
if((CPHA==1 && state==RUN_STATE && !stop) ||
(CPHA==0 && !csb && !stop)) begin
sclk <= !sclk;
end else begin
sclk <= CPOL;
end
end
end
end
endmodule // spi_master |
module sri
// This is a shift register that sends data out to the di lines of
// spi slaves.
#(parameter DATA_WIDTH=16)
(input clk,
input resetb,
input [DATA_WIDTH-1:0] datai,
input sample,
input shift,
output din
);
reg [DATA_WIDTH-1:0] sr_reg;
assign din = sr_reg[DATA_WIDTH-1];
`ifdef SYNC_RESET
always @(posedge clk) begin
`else
always @(posedge clk or negedge resetb) begin
`endif
if(!resetb) begin
sr_reg <= 0;
end else begin
if(sample) begin
sr_reg <= datai;
end else if(shift) begin
sr_reg <= sr_reg << 1;
end
end
end
endmodule |
module sro
// This is a shift register that receives data on the dout lines
// from spi slaves.
#(parameter DATA_WIDTH=16)
(input clk,
input resetb,
input shift,
input dout,
output reg [DATA_WIDTH-1:0] datao
);
reg dout_s;
`ifdef SYNC_RESET
always @(posedge clk) begin
`else
always @(posedge clk or negedge resetb) begin
`endif
if(!resetb) begin
dout_s <= 0;
datao <= 0;
end else begin
dout_s <= dout;
if(shift) begin
datao <= { datao[DATA_WIDTH-2:0], dout_s };
end
end
end
endmodule |
module i2c_master #(
parameter base_addr = 6'h0
)
(
//
input wire sys_clk,
input wire sys_rst,
//
input wire [5:3] io_a,
input wire [7:0] io_di,
output reg [7:0] io_do,
input wire io_re,
input wire io_we,
//
output reg i2c_irq,
//
input wire scl_i, // SCL-line input
output wire scl_o, // SCL-line output (always 1'b0)
output wire scl_oen_o, // SCL-line output enable (active low)
input wire sda_i, // SDA-line input
output wire sda_o, // SDA-line output (always 1'b0)
output wire sda_oen_o // SDA-line output enable (active low)
);
// register address
parameter [2:0] PRE_LO_ADDR = 3'h0;
parameter [2:0] PRE_HI_ADDR = 3'h1;
parameter [2:0] CTRL_ADDR = 3'h2;
parameter [2:0] TXR_ADDR = 3'h3;
parameter [2:0] RXR_ADDR = 3'h4;
parameter [2:0] CR_ADDR = 3'h5;
parameter [2:0] SR_ADDR = 3'h6;
wire csr_selected = (io_a == PRE_LO_ADDR) | (io_a == PRE_HI_ADDR) |
(io_a == CTRL_ADDR) | (io_a == RXR_ADDR) |
(io_a == SR_ADDR) | (io_a == TXR_ADDR) |
(io_a == CR_ADDR);
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// assign io_do
always @*
begin
io_do = 8'd00;
if(io_re & csr_selected)
case (io_a)
PRE_LO_ADDR: io_do = #1 prer[ 7:0];
PRE_HI_ADDR: io_do = #1 prer[15:8];
CTRL_ADDR: io_do = #1 ctr;
RXR_ADDR: io_do = #1 rxr;
SR_ADDR: io_do = #1 sr;
TXR_ADDR: io_do = #1 txr;
CR_ADDR: io_do = #1 cr;
default: io_do = 8'hff; // reserved
endcase
end
/*
always @(posedge sys_clk)
begin
//io_do <= 8'd00;
if(io_re & csr_selected)
case (io_a)
prer_low_addr: io_do <= #1 prer[ 7:0];
prer_high_addr: io_do <= #1 prer[15:8];
ctr_addr: io_do <= #1 ctr;
rxr_addr: io_do <= #1 rxr;
sr_addr: io_do <= #1 sr;
txr_addr: io_do <= #1 txr;
cr_addr: io_do <= #1 cr;
default: ; // reserved
endcase
end
*/
// generate registers
always @(posedge sys_clk or posedge sys_rst)
if (sys_rst)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (io_we & csr_selected)
case (io_a)
PRE_LO_ADDR : prer [ 7:0] <= #1 io_di;
PRE_HI_ADDR : prer [15:8] <= #1 io_di;
CTRL_ADDR : ctr <= #1 io_di;
TXR_ADDR : txr <= #1 io_di;
default: ;
endcase
// generate command register (special case)
always @(posedge sys_clk or posedge sys_rst)
if (sys_rst)
cr <= #1 8'h0;
else if (io_we & (io_a == CR_ADDR))
begin
if (core_en)
cr <= #1 io_di;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 1'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( sys_clk ),
.rst ( sys_rst ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen_o ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen_o )
);
// status register block + interrupt request signal
always @(posedge sys_clk or posedge sys_rst)
if (sys_rst)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al /*| irq_flag*/) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge sys_clk or posedge sys_rst)
if (sys_rst)
i2c_irq <= #1 1'b0;
else
i2c_irq <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule |
module tb_blake2s_m_select();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter VERBOSE = 1;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_load;
reg [511 : 0] tb_m;
reg [3 : 0] tb_round;
reg tb_mode;
wire [31 : 0] tb_G0_m0;
wire [31 : 0] tb_G0_m1;
wire [31 : 0] tb_G1_m0;
wire [31 : 0] tb_G1_m1;
wire [31 : 0] tb_G2_m0;
wire [31 : 0] tb_G2_m1;
wire [31 : 0] tb_G3_m0;
wire [31 : 0] tb_G3_m1;
reg display_cycle_ctr;
//----------------------------------------------------------------
// blake2_G device under test.
//----------------------------------------------------------------
blake2s_m_select dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.load(tb_load),
.m(tb_m),
.round(tb_round),
.mode(tb_mode),
.G0_m0(tb_G0_m0),
.G0_m1(tb_G0_m1),
.G1_m0(tb_G1_m0),
.G1_m1(tb_G1_m1),
.G2_m0(tb_G2_m0),
.G2_m1(tb_G2_m1),
.G3_m0(tb_G3_m0),
.G3_m1(tb_G3_m1)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end // dut_monitor
//----------------------------------------------------------------
// dump_dut_state
//
// Dump the internal state of the dut to std out.
//----------------------------------------------------------------
task dump_dut_state;
begin
if (VERBOSE)
begin
// $display("");
// $display("DUT internal state");
// $display("------------------");
// $display("contents of m:");
// $display("0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x ",
// dut.\m_mem[0] , dut.\m_mem[1] , dut.\m_mem[2] , dut.\m_mem[3] ,
// dut.\m_mem[4] , dut.\m_mem[5] , dut.\m_mem[6] , dut.\m_mem[7] );
// $display("0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x ",
// dut.\m_mem[8] , dut.\m_mem[9] , dut.\m_mem[10] , dut.\m_mem[11] ,
// dut.\m_mem[12] , dut.\m_mem[13] , dut.\m_mem[14] , dut.\m_mem[15] );
// $display("");
end
end
endtask // dump_dut_state
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
$display("--- %02d test cases executed ---", tc_ctr);
if (error_ctr == 0)
begin
$display("--- All %02d test cases completed successfully ---", tc_ctr);
end
else
begin
$display("--- %02d test cases FAILED . ---", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// init_dut()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_dut;
begin
cycle_ctr = 0;
error_ctr = 0;
display_cycle_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_load = 0;
tb_m = 512'h0;
tb_round = 0;
tb_mode = 0;
end
endtask // init_dut
//----------------------------------------------------------------
// test_reset
//
// Check that the m_memory registers cleared by dropping reset.
//----------------------------------------------------------------
task test_reset;
begin : tc_reset
tc_ctr = tc_ctr + 1;
$display("--- Testing that reset clears the m memory");
$display("--- Memory before reset:");
dump_dut_state();
tb_reset_n = 0;
#(CLK_PERIOD);
$display("--- Pulling reset");
tb_reset_n = 1;
#(CLK_PERIOD);
$display("--- Memory after reset:");
dump_dut_state();
$display("");
end
endtask // test_reset
//----------------------------------------------------------------
// test_case1
//
// Check that we can load a known block into m and get the
// big to little endian conversion performed during load.
//----------------------------------------------------------------
task test_case1;
begin : tc1
tc_ctr = tc_ctr + 1;
tb_round = 0;
tb_mode = 0;
tb_load = 0;
tb_m = {32'h00010203, 32'h04050607, 32'h08090a0b, 32'h0c0d0e0f,
32'h10111213, 32'h14151617, 32'h18191a1b, 32'h1c1d1e1f,
32'h20212223, 32'h24252627, 32'h28292a2b, 32'h2c2d2e2f,
32'h30313233, 32'h34353637, 32'h38393a3b, 32'h3c3d3e3f};
$display("--- TC1: Test case 1 started. Loading the m with a known block");
$display("--- TC1: Before loading:");
dump_dut_state();
tb_load = 1;
#(CLK_PERIOD);
tb_load = 0;
$display("--- TC1: After loading:");
dump_dut_state();
$display("");
end
endtask // test_case1
//----------------------------------------------------------------
// test_case2
//
// Check that we can get expected words based on rounds and mode.
//----------------------------------------------------------------
task test_case2;
begin : tc2
integer i;
tc_ctr = tc_ctr + 1;
tb_round = 0;
tb_mode = 0;
tb_load = 0;
tb_m = {32'h00010203, 32'h04050607, 32'h08090a0b, 32'h0c0d0e0f,
32'h10111213, 32'h14151617, 32'h18191a1b, 32'h1c1d1e1f,
32'h20212223, 32'h24252627, 32'h28292a2b, 32'h2c2d2e2f,
32'h30313233, 32'h34353637, 32'h38393a3b, 32'h3c3d3e3f};
$display("--- TC2: Test case 2 started. Loading the m with a known block");
tb_load = 1;
#(CLK_PERIOD);
tb_load = 0;
$display("--- TC2: Looping over all rounds and modes.");
for (i = 0 ; i < 16 ; i = i + 1) begin
tb_round = i[3 : 0];
tb_mode = 0;
#(CLK_PERIOD);
$display("--- TC2: round %2d, mode: %1x:", tb_round, tb_mode);
$display("--- G0_m0: 0x%08x, G0_m1: 0x%08x, G1_m0: 0x%08x, G1_m1: 0x%08x",
tb_G0_m0, tb_G0_m1, tb_G1_m0, tb_G1_m1);
$display("--- G2_m0: 0x%08x, G2_m1: 0x%08x, G3_m0: 0x%08x, G3_m1: 0x%08x",
tb_G2_m0, tb_G2_m1, tb_G3_m0, tb_G3_m1);
#(CLK_PERIOD);
tb_mode = 1;
#(CLK_PERIOD);
$display("--- TC2: round %2d, mode: %1x:", tb_round, tb_mode);
$display("--- G0_m0: 0x%08x, G0_m1: 0x%08x, G1_m0: 0x%08x, G1_m1: 0x%08x",
tb_G0_m0, tb_G0_m1, tb_G1_m0, tb_G1_m1);
$display("--- G2_m0: 0x%08x, G2_m1: 0x%08x, G3_m0: 0x%08x, G3_m1: 0x%08x",
tb_G2_m0, tb_G2_m1, tb_G3_m0, tb_G3_m1);
#(CLK_PERIOD);
end
$display("--- TC2: Test case 2 completed");
tb_load = 1;
$display("");
end
endtask // test_case1
//----------------------------------------------------------------
// testrunner
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : testrunner
$display("--- Testbench for BLAKE2 m select module started ---");
$display("----------------------------------------------------");
$display("");
init_dut();
test_reset();
test_case1();
test_case2();
display_test_result();
$display("--- Testbench for BLAKE2 m select module completed ---");
$display("------------------------------------------------------");
$finish_and_return(error_ctr);
end // testrunner
endmodule // tb_blake2s_m_select |
module tb_blake2s();
initial begin
$display("*******in here*******");
$display("*******in here*******");
$display("*******in here*******");
$display("*******in here*******");
end
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter DUMP_WAIT = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_UPDATE_BIT = 1;
localparam CTRL_FINISH_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_BLOCKLEN = 8'h0a;
localparam ADDR_BLOCK0 = 8'h10;
localparam ADDR_BLOCK15 = 8'h1f;
localparam ADDR_DIGEST0 = 8'h40;
localparam ADDR_DIGEST7 = 8'h47;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_monitor;
reg display_dut_state;
reg display_core_state;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
reg [31 : 0] read_data;
reg [255 : 0] digest;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
blake2s dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
initial begin
//$display("*******in here*******");
//$display("*******in here*******");
//$monitor("A=0x%0h, B=0x%0h, C=0x%0h",dut.core._0950_, dut.core._0951_, dut.core._0952_);
////$monitor("tb_write_data=0x%0h",tb_write_data );
////$monitor("tb_we=0x%0h",tb_we );
//$display("*******in here*******");
// $display("*******in here*******");
end
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (tb_monitor)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state
//
// Dump the internal state of the dut to std out.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("-------------------------------------------------------------------------------------");
$display("-------------------------------------------------------------------------------------");
$display("DUT internal state at cycle: %08d", cycle_ctr);
$display("-------------------------------------");
if (display_dut_state) begin
//$display("block 0 ... 3: 0x%08x 0x%08x 0x%08x 0x%08x",
// dut.\block_mem[0] ,
// dut.\block_mem[1] , dut.\block_mem[2] , dut.\block_mem[3] );
//$display("block 4 ... 7: 0x%08x 0x%08x 0x%08x 0x%08x",
// dut.\block_mem[4] , dut.\block_mem[5] , dut.\block_mem[6] , dut.\block_mem[7] );
//$display("block 8 ... 11: 0x%08x 0x%08x 0x%08x 0x%08x",
// dut.\block_mem[8] , dut.\block_mem[9] , dut.\block_mem[10] , dut.\block_mem[11] );
//$display("block 12 ... 15: 0x%08x 0x%08x 0x%08x 0x%08x",
// dut.\block_mem[12] , dut.\block_mem[13] , dut.\block_mem[14] , dut.\block_mem[15] );
//$display("");
end
if (display_core_state) begin
//$display("Core internal state");
//$display("-------------------");
//$display("init: 0x%01x, update: 0x%01x, finish: 0x%01x", dut.core.init, dut.core.update, dut.core.finish);
//$display("block M: 0x%064x", dut.core.block[511 : 256]);
//$display("block L: 0x%064x", dut.core.block[255 : 000]);
//$display("blocklen: 0x%02x", dut.core.blocklen);
//$display("digest: 0x%064x", dut.core.digest);
//$display("ready: 0x%01x", dut.core.ready);
//$display("");
//$display("blake2s_ctrl_reg: 0x%02x, blake2s_ctrl_new: 0x%02x, blake2s_ctrl_we: 0x%01x",
// dut.core.blake2s_ctrl_reg, dut.core.blake2s_ctrl_new, dut.core.blake2s_ctrl_we);
//$display("");
//$display("h0: 0x%08x, h1: 0x%08x, h2: 0x%08x, h3: 0x%08x",
// dut.core.h_reg[0], dut.core.h_reg[1], dut.core.h_reg[2], dut.core.h_reg[3]);
//$display("h4: 0x%08x, h5: 0x%08x, h6: 0x%08x, h7: 0x%08x",
// dut.core.h_reg[4], dut.core.h_reg[5], dut.core.h_reg[6], dut.core.h_reg[7]);
//$display("");
//$display("v0: 0x%08x, v1: 0x%08x, v2: 0x%08x, v3: 0x%08x",
// dut.core.\v_reg[0] , dut.core.\v_reg[1] , dut.core.\v_reg[2] , dut.core.\v_reg[3] );
//$display("v4: 0x%08x, v5: 0x%08x, v6: 0x%08x, v7: 0x%08x",
// dut.core.\v_reg[4] , dut.core.\v_reg[5] , dut.core.\v_reg[6] , dut.core.\v_reg[7] );
//$display("v8: 0x%08x, v9: 0x%08x, v10: 0x%08x, v11: 0x%08x",
// dut.core.\v_reg[8] , dut.core.\v_reg[9] , dut.core.\v_reg[10] , dut.core.\v_reg[11] );
//$display("v12: 0x%08x, v13: 0x%08x, v14: 0x%08x, v15: 0x%08x",
// dut.core.\v_reg[12] , dut.core.\v_reg[13] , dut.core.\v_reg[14] , dut.core.\v_reg[15] );
//$display("init_v: 0x%1x, update_v: 0x%1x, v_we: 0x%1x", dut.core.init_v, dut.core.update_v, dut.core.v_we);
//$display("");
//$display("t0_reg: 0x%08x, t0_new: 0x%08x", dut.core.t0_reg, dut.core.t0_new);
//$display("t1_reg: 0x%08x, t1_new: 0x%08x", dut.core.t1_reg, dut.core.t1_new);
//$display("t_ctr_rst: 0x%1x, t_ctr_inc: 0x%1x", dut.core.t_ctr_rst, dut.core.t_ctr_inc);
//$display("last_reg: 0x%1x, last_new: 0x%1x, last_we: 0x%1x",
// dut.core.last_reg, dut.core.last_new, dut.core.last_we);
//$display("");
//$display("v0_new: 0x%08x, v1_new: 0x%08x, v2_new: 0x%08x, v3_new: 0x%08x",
// dut.core.v_new[0], dut.core.v_new[1], dut.core.v_new[2], dut.core.v_new[3]);
//$display("v4_new: 0x%08x, v5_new: 0x%08x, v6_new: 0x%08x, v7_new: 0x%08x",
// dut.core.v_new[4], dut.core.v_new[5], dut.core.v_new[6], dut.core.v_new[7]);
//$display("v8_new: 0x%08x, v9_new: 0x%08x, v10_new: 0x%08x, v11_new: 0x%08x",
// dut.core.v_new[8], dut.core.v_new[9], dut.core.v_new[10], dut.core.v_new[11]);
//$display("v12_new: 0x%08x, v13_new: 0x%08x, v14_new: 0x%08x, v15_new: 0x%08x",
// dut.core.v_new[12], dut.core.v_new[13], dut.core.v_new[14], dut.core.v_new[15]);
//$display("");
//$display("G_mode: 0x%1x, ", dut.core.G_mode);
//$display("G0_m0: 0x%08x, G0_m1: 0x%08x, G1_m0: 0x%08x, G1_m1: 0x%08x",
// dut.core.G0_m0, dut.core.G0_m1, dut.core.G1_m0, dut.core.G1_m1);
//$display("G2_m0: 0x%08x, G2_m1: 0x%08x, G3_m0: 0x%08x, G3_m1: 0x%08x",
// dut.core.G2_m0, dut.core.G2_m1, dut.core.G3_m0, dut.core.G3_m1);
//$display("round_ctr_reg: 0x%02x, round_ctr_new: 0x%02x", dut.core.round_ctr_reg, dut.core.round_ctr_reg);
//$display("round_ctr_rst: 0x%1x, round_ctr_inc: 0x%1x, round_ctr_we: 0x%1x",
// dut.core.round_ctr_rst, dut.core.round_ctr_inc, dut.core.round_ctr_we);
end // if (display_core_state)
$display("-------------------------------------------------------------------------------------");
$display("-------------------------------------------------------------------------------------");
$display("");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("--- Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
$display("");
if (error_ctr == 0) begin
$display("--- All %02d test cases completed successfully", tc_ctr);
end else begin
$display("--- %02d tests completed - %02d test cases FAILED .",
tc_ctr, error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_monitor = 0;
display_dut_state = 0;
display_core_state = 0;
tb_clk = 1'h0;
tb_reset_n = 1'h1;
tb_cs = 1'h0;
tb_we = 1'h0;
tb_address = 8'h0;
tb_write_data = 32'h0;
end
endtask // init_sim
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("--- Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(2 * CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag to be set in dut.
//----------------------------------------------------------------
task wait_ready;
begin : wready
read_word(ADDR_STATUS);
while (read_data == 0)
read_word(ADDR_STATUS);
end
endtask // wait_ready
//----------------------------------------------------------------
// get_digest()
//----------------------------------------------------------------
task get_digest;
begin
read_word(ADDR_DIGEST0);
digest[255 : 224] = read_data;
read_word(ADDR_DIGEST0 + 8'h1);
digest[223 : 192] = read_data;
read_word(ADDR_DIGEST0 + 8'h2);
digest[191 : 160] = read_data;
read_word(ADDR_DIGEST0 + 8'h3);
digest[159 : 128] = read_data;
read_word(ADDR_DIGEST0 + 8'h4);
digest[127 : 96] = read_data;
read_word(ADDR_DIGEST0 + 8'h5);
digest[95 : 64] = read_data;
read_word(ADDR_DIGEST0 + 8'h6);
digest[63 : 32] = read_data;
read_word(ADDR_DIGEST0 + 8'h7);
digest[31 : 0] = read_data;
end
endtask // get_digest
//----------------------------------------------------------------
// clean_block()
//----------------------------------------------------------------
task clean_block;
begin: clean_block
integer i;
for (i = 0 ; i < 16 ; i = i + 1) begin
write_word(ADDR_BLOCK0 + i, 32'h0);
end
end
endtask // clean_block
//----------------------------------------------------------------
// test_name_version
//----------------------------------------------------------------
task test_name_version;
begin: test_name_version
reg [31 : 0] name0;
reg [31 : 0] name1;
reg [31 : 0] version;
$display("");
$display("--- test_name_version: Started.");
read_word(ADDR_NAME0);
name0 = read_data;
read_word(ADDR_NAME1);
name1 = read_data;
read_word(ADDR_VERSION);
version = read_data;
$display("--- test_name_version: Name: %c%c%c%c%c%c%c%c",
name0[31 : 24], name0[23 : 16], name0[15 : 8], name0[7 : 0],
name1[31 : 24], name1[23 : 16], name1[15 : 8], name1[7 : 0]);
$display("--- test_name_version: Version: %c%c%c%c",
version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]);
$display("--- test_name_version: Completed.");
$display("");
end
endtask // test_name_version
//----------------------------------------------------------------
// test_empty_message
//----------------------------------------------------------------
task test_empty_message;
begin : test_rfc_7693
tc_ctr = tc_ctr + 1;
tb_monitor = 0;
display_dut_state = 0;
display_core_state = 0;
$display("");
$display("--- test_empty_message: Started.");
$display("--- test_empty_message: Asserting init.");
write_word(ADDR_CTRL, 32'h1);
wait_ready();
$display("--- test_empty_message: Init should be completed.");
$display("--- test_empty_message: Asserting finish.");
write_word(ADDR_BLOCKLEN, 32'h0);
write_word(ADDR_CTRL, 32'h4);
wait_ready();
$display("--- test_empty_message: Finish should be completed.");
get_digest();
$display("--- test_empty_message: Checking generated digest.");
if (digest == 256'h69217a3079908094e11121d042354a7c1f55b6482ca1a51e1b250dfd1ed0eef9) begin
$display("--- test_empty_message: Correct digest generated.");
$display("--- test_empty_message: Got: 0x%064x", digest);
end else begin
$display("--- test_empty_message: Error. Incorrect digest generated.");
$display("--- test_empty_message: Expected: 0x69217a3079908094e11121d042354a7c1f55b6482ca1a51e1b250dfd1ed0eef9");
$display("--- test_empty_message: Got: 0x%064x", digest);
error_ctr = error_ctr + 1;
end
tb_monitor = 0;
display_dut_state = 0;
display_core_state = 0;
$display("--- test_empty_message: Completed.\n");
end
endtask // test_empty_message
//----------------------------------------------------------------
// test_rfc_7693
//----------------------------------------------------------------
task test_rfc_7693;
begin : test_rfc_7693
tc_ctr = tc_ctr + 1;
tb_monitor = 0;
display_dut_state = 0;
display_core_state = 0;
clean_block();
$display("");
$display("--- ttest_rfc_7693: Started.");
$display("--- test_rfc_7693: Asserting init.");
write_word(ADDR_CTRL, 32'h1);
wait_ready();
$display("--- test_rfc_7693: Init should be completed.");
$display("--- test_rfc_7693: Writing message and message length.");
write_word(ADDR_BLOCK0, 32'h61626300);
write_word(ADDR_BLOCKLEN, 32'h3);
$display("--- test_rfc_7693: Asserting finish.");
write_word(ADDR_CTRL, 32'h4);
wait_ready();
$display("--- test_rfc_7693: Finish should be completed.");
get_digest();
$display("--- test_rfc_7693: Checking generated digest.");
if (digest == 256'h508c5e8c327c14e2_e1a72ba34eeb452f_37458b209ed63a29_4d999b4c86675982) begin
$display("--- test_rfc_7693: Correct digest generated.");
$display("--- test_rfc_7693: Got: 0x%064x", digest);
end else begin
$display("--- test_rfc_7693: Error. Incorrect digest generated.");
$display("--- test_rfc_7693: Expected: 0x508c5e8c327c14e2_e1a72ba34eeb452f_37458b209ed63a29_4d999b4c86675982");
$display("--- test_rfc_7693: Got: 0x%064x", digest);
error_ctr = error_ctr + 1;
end
tb_monitor = 0;
display_dut_state = 0;
display_core_state = 0;
$display("--- test_rfc_7693: Completed.\n");
end
endtask // test_rfc_7693
//----------------------------------------------------------------
// test_one_block_message
//----------------------------------------------------------------
task test_one_block_message;
begin : test_one_block_message
tc_ctr = tc_ctr + 1;
tb_monitor = 0;
display_dut_state = 0;
display_core_state = 0;
clean_block();
$display("");
$display("--- test_one_block_message: Started.");
$display("--- test_one_block_message: Asserting init.");
write_word(ADDR_CTRL, 32'h1);
wait_ready();
$display("--- test_one_block_message: Init should be completed.");
$display("--- test_one_block_message: Writing message and message length.");
write_word(ADDR_BLOCK0 + 0, 32'h00010203);
write_word(ADDR_BLOCK0 + 1, 32'h04050607);
write_word(ADDR_BLOCK0 + 2, 32'h08090a0b);
write_word(ADDR_BLOCK0 + 3, 32'h0c0d0e0f);
write_word(ADDR_BLOCK0 + 4, 32'h10111213);
write_word(ADDR_BLOCK0 + 5, 32'h14151617);
write_word(ADDR_BLOCK0 + 6, 32'h18191a1b);
write_word(ADDR_BLOCK0 + 7, 32'h1c1d1e1f);
write_word(ADDR_BLOCK0 + 8, 32'h20212223);
write_word(ADDR_BLOCK0 + 9, 32'h24252627);
write_word(ADDR_BLOCK0 + 10, 32'h28292a2b);
write_word(ADDR_BLOCK0 + 11, 32'h2c2d2e2f);
write_word(ADDR_BLOCK0 + 12, 32'h30313233);
write_word(ADDR_BLOCK0 + 13, 32'h34353637);
write_word(ADDR_BLOCK0 + 14, 32'h38393a3b);
write_word(ADDR_BLOCK0 + 15, 32'h3c3d3e3f);
write_word(ADDR_BLOCKLEN, 32'h40);
$display("--- test_one_block_message: Asserting finish.");
write_word(ADDR_CTRL, 32'h4);
wait_ready();
$display("--- test_one_block_message: Finish should be completed.");
get_digest();
$display("--- test_one_block_message: Checking generated digest.");
if (digest == 256'h56f34e8b96557e90c1f24b52d0c89d51086acf1b00f634cf1dde9233b8eaaa3e) begin
$display("--- test_one_block_message: Correct digest generated.");
$display("--- test_one_block_message: Got: 0x%064x", digest);
end else begin
$display("--- test_one_block_message: Error. Incorrect digest generated.");
$display("--- test_one_block_message: Expected: 0x56f34e8b96557e90c1f24b52d0c89d51086acf1b00f634cf1dde9233b8eaaa3e");
$display("--- test_one_block_message: Got: 0x%064x", digest);
error_ctr = error_ctr + 1;
end
tb_monitor = 0;
display_dut_state = 0;
display_core_state = 0;
$display("--- test_one_block_message: Completed.\n");
end
endtask // test_one_block_message
//----------------------------------------------------------------
// test_one_block_one_byte_message
//----------------------------------------------------------------
task test_one_block_one_byte_message;
begin : test_one_block_one_byte_message
tc_ctr = tc_ctr + 1;
tb_monitor = 0;
display_dut_state = 0;
display_core_state = 0;
clean_block();
$display("");
$display("--- test_one_block_one_byte_message: Started.");
$display("--- test_one_block_one_byte_message: Asserting init.");
write_word(ADDR_CTRL, 32'h1);
wait_ready();
$display("--- test_one_block_one_byte_message: Init should be completed.");
$display("--- test_one_block_one_byte_message: Writing message and message length.");
write_word(ADDR_BLOCK0 + 0, 32'h00010203);
write_word(ADDR_BLOCK0 + 1, 32'h04050607);
write_word(ADDR_BLOCK0 + 2, 32'h08090a0b);
write_word(ADDR_BLOCK0 + 3, 32'h0c0d0e0f);
write_word(ADDR_BLOCK0 + 4, 32'h10111213);
write_word(ADDR_BLOCK0 + 5, 32'h14151617);
write_word(ADDR_BLOCK0 + 6, 32'h18191a1b);
write_word(ADDR_BLOCK0 + 7, 32'h1c1d1e1f);
write_word(ADDR_BLOCK0 + 8, 32'h20212223);
write_word(ADDR_BLOCK0 + 9, 32'h24252627);
write_word(ADDR_BLOCK0 + 10, 32'h28292a2b);
write_word(ADDR_BLOCK0 + 11, 32'h2c2d2e2f);
write_word(ADDR_BLOCK0 + 12, 32'h30313233);
write_word(ADDR_BLOCK0 + 13, 32'h34353637);
write_word(ADDR_BLOCK0 + 14, 32'h38393a3b);
write_word(ADDR_BLOCK0 + 15, 32'h3c3d3e3f);
write_word(ADDR_BLOCKLEN, 32'h40);
$display("--- test_one_block_one_byte_message: Asserting next.");
write_word(ADDR_CTRL, 32'h2);
wait_ready();
$display("--- test_one_block_one_byte_message: Next should be completed.");
get_digest();
$display("--- test_one_block_one_byte_message: Writing message and message length.");
clean_block();
write_word(ADDR_BLOCK0 + 0, 32'h40000000);
write_word(ADDR_BLOCKLEN, 32'h01);
$display("--- test_one_block_one_byte_message: Asserting finish.");
write_word(ADDR_CTRL, 32'h4);
wait_ready();
$display("--- test_one_block_one_byte_message: Finish should be completed.");
get_digest();
$display("--- test_one_block_one_byte_message: Checking generated digest.");
if (digest == 256'h1b53ee94aaf34e4b159d48de352c7f0661d0a40edff95a0b1639b4090e974472) begin
$display("--- test_one_block_one_byte_message: Correct digest generated.");
$display("--- test_one_block_one_byte_message: Got: 0x%064x", digest);
end else begin
$display("--- test_one_block_one_byte_message: Error. Incorrect digest generated.");
$display("--- test_one_block_one_byte_message: Expected: 0x1b53ee94aaf34e4b159d48de352c7f0661d0a40edff95a0b1639b4090e974472");
$display("--- test_one_block_one_byte_message: Got: 0x%064x", digest);
error_ctr = error_ctr + 1;
end
tb_monitor = 0;
display_dut_state = 0;
display_core_state = 0;
$display("--- test_one_block_one_byte_message: Completed.\n");
end
endtask // test_one_block_one_byte_message
//----------------------------------------------------------------
// blake2s_test
//----------------------------------------------------------------
initial
begin : blake2s_test
$display(" -= Testbench for blake2s started =-");
$display(" =================================");
$display("");
init_sim();
reset_dut();
test_name_version();
test_empty_message();
test_rfc_7693();
test_one_block_message();
test_one_block_one_byte_message();
display_test_result();
$display("");
$display(" -= Testbench for blake2s completed =-");
$display(" =================================");
$display("");
$finish;
end // blake2s_test
endmodule // tb_blake2s |
module AHB_SRAM_TB;
localparam SRAM_AW = 10;
reg HCLK;
reg HRESETn;
wire HREADY;
reg HWRITE;
reg [2:0] HSIZE;
reg [1:0] HTRANS;
reg [31:0] HADDR, HWDATA;
wire [31:0] HRDATA;
wire [31:0] SRAMRDATA; // SRAM Read Data
wire [3:0] SRAMWEN; // SRAM write enable (active high)
wire [31:0] SRAMWDATA; // SRAM write data
wire SRAMCS; // SRAM Chip Select (active high)
wire [SRAM_AW-1:0] SRAMADDR; // SRAM address
always #5 HCLK = !HCLK;
initial begin
$dumpfile("ahb_srm_tb.vcd");
$dumpvars;
//$monitor("rdata=0x%0h",rdata);
# 45_000_000 $finish;
end
// RESET
initial begin
HCLK = 0;
HRESETn = 1;
#10;
@(posedge HCLK);
HRESETn = 0;
#100;
@(posedge HCLK);
HRESETn = 1;
end
AHB_SRAM #( .AW(SRAM_AW+2) ) MUV (
.HCLK(HCLK),
.HRESETn(HRESETn),
// AHB-Lite Slave Interface
.HSEL(1'b1),
.HREADYOUT(HREADY),
.HREADY(HREADY),
.HWDATA(HWDATA),
.HRDATA(HRDATA),
.HSIZE(HSIZE),
.HWRITE(HWRITE),
.HTRANS(HTRANS),
.HADDR(HADDR),
.SRAMRDATA(SRAMRDATA),
.SRAMWEN(SRAMWEN),
.SRAMWDATA(SRAMWDATA),
.SRAMCS(SRAMCS),
.SRAMADDR(SRAMADDR)
);
sram32 #( .AW(SRAM_AW), .VERBOSE(0) ) SRAM (
.clk(HCLK),
.cs(SRAMCS),
.we(SRAMWEN),
.A(SRAMADDR),
.Di(SRAMWDATA),
.Do(SRAMRDATA)
);
`include "includes/AHB_tasks.vh"
// test case
reg [31:0] rdata;
initial begin
@(posedge HRESETn);
#200;
AHB_WRITE_WORD(32'h0000_0000, 32'h44_33_22_11);
#25;
AHB_READ_WORD(32'h0000_0000, rdata);
#25;
`CHECK_W(32'h44_33_22_11, 1);
#25;
AHB_READ_HALF(32'h0000_0000, rdata);
#25;
`CHECK_H(16'h22_11, 2);
#25;
AHB_READ_BYTE(32'h0000_0000, rdata);
#25;
`CHECK_B(8'h11, 3);
#25;
AHB_WRITE_WORD(32'h000F_FFF0, 32'hABCD_1234);
#25;
AHB_READ_WORD(32'h000F_FFF0, rdata);
#25;
`CHECK_W(32'hABCD_1234, 4);
#100;
// Read after write
AHB_WRITE_READ_WORD(32'h0000_0A00, 32'h0000_0000, 32'hDEADBEEF, rdata);
#100;
AHB_READ_WORD(32'h0000_0A00, rdata);
#25;
`CHECK_W(32'hDEADBEEF, 5);
$finish;
end
endmodule |
module tb_blake2s_G();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter VERBOSE = 0;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg [31 : 0] tb_a;
reg [31 : 0] tb_b;
reg [31 : 0] tb_c;
reg [31 : 0] tb_d;
reg [31 : 0] tb_m0;
reg [31 : 0] tb_m1;
wire [31 : 0] tb_a_prim;
wire [31 : 0] tb_b_prim;
wire [31 : 0] tb_c_prim;
wire [31 : 0] tb_d_prim;
reg display_cycle_ctr;
//----------------------------------------------------------------
// blake2_G device under test.
//----------------------------------------------------------------
blake2s_G dut(
.a(tb_a),
.b(tb_b),
.c(tb_c),
.d(tb_d),
.m0(tb_m0),
.m1(tb_m1),
.a_prim(tb_a_prim),
.b_prim(tb_b_prim),
.c_prim(tb_c_prim),
.d_prim(tb_d_prim)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end // dut_monitor
//----------------------------------------------------------------
// dump_dut_state
//
// Dump the internal state of the dut to std out.
//----------------------------------------------------------------
task dump_dut_state;
begin
if (VERBOSE)
begin
$display("");
$display("DUT internal state");
$display("------------------");
$display("a1: 0x%08x, a2: 0x%08x", dut.a1, dut.a2);
$display("b1: 0x%08x, b2: 0x%08x, b3: 0x%08x, b4: 0x%08x", dut.b1, dut.b2, dut.b3, dut.b4);
$display("c1: 0x%08x, c2: 0x%08x", dut.c1, dut.c2);
$display("d1: 0x%08x, d2: 0x%08x, d3: 0x%08x, d4: 0x%08x", dut.d1, dut.d2, dut.d3, dut.d4);
$display("");
end
end
endtask // dump_dut_state
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
$display("*** %02d test cases executed ****", tc_ctr);
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully ****", tc_ctr);
end
else
begin
$display("*** %02d test cases FAILED . ***", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// init_dut()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_dut;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_a = 32'h0;
tb_b = 32'h0;
tb_c = 32'h0;
tb_d = 32'h0;
tb_m0 = 32'h0;
tb_m1 = 32'h0;
end
endtask // init_dut
//----------------------------------------------------------------
// task1
//
// First task with vectors captured from the blake2s reference
// while running.
//----------------------------------------------------------------
task test1;
begin : tc1
integer tc1_error;
reg [31 : 0] expected_a;
reg [31 : 0] expected_b;
reg [31 : 0] expected_c;
reg [31 : 0] expected_d;
tc1_error = 0;
tc_ctr = tc_ctr + 1;
tb_a = 32'h6b08c647;
tb_b = 32'h510e527f;
tb_c = 32'h6a09e667;
tb_d = 32'h510e523f;
tb_m0 = 32'h03020100;
tb_m1 = 32'h07060504;
expected_a = 32'h263d8fa2;
expected_b = 32'h0e16dfd0;
expected_c = 32'h6b7198df;
expected_d = 32'hb56dc461;
$display("*** Running test case 1 ****");
dump_dut_state();
#(CLK_PERIOD);
dump_dut_state();
if (tb_a_prim != expected_a)
begin
$display("Error in a. Expected 0x%08x. Got 0x%08x", expected_a, tb_a_prim);
tc1_error = 1;
end
if (tb_b_prim != expected_b)
begin
$display("Error in b. Expected 0x%08x. Got 0x%08x", expected_b, tb_b_prim);
tc1_error = 1;
end
if (tb_c_prim != expected_c)
begin
$display("Error in c. Expected 0x%08x. Got 0x%08x", expected_c, tb_c_prim);
tc1_error = 1;
end
if (tb_d_prim != expected_d)
begin
$display("Error in d. Expected 0x%08x. Got 0x%08x", expected_d, tb_d_prim);
tc1_error = 1;
end
if (tc1_error)
error_ctr = error_ctr + 1;
$display("");
end
endtask // test1
//----------------------------------------------------------------
// testrunner
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : testrunner
$display("*** Testbench for BLAKE2 G function test started ***");
$display("----------------------------------------------------");
$display("");
init_dut();
test1();
display_test_result();
$display("*** BLAKE2 G functions simulation done ****");
$finish_and_return(error_ctr);
end // testrunner
endmodule // tb_blake2s_G |
module regfile_tb;
// Declarations
reg HCLK;
reg WR;
reg [4:0] RA;
reg [4:0] RB;
reg [4:0] RW;
reg [31:0] DW;
wire [31:0] DA;
wire [31:0] DB;
// Instantiation of Unit Under Test
regfile uut (
.HCLK(HCLK),
.WR(WR),
.RA(RA),
.RB(RB),
.RW(RW),
.DW(DW),
.DA(DA),
.DB(DB)
);
initial begin
$dumpfile("out2.vcd");
// vcd dump file
$dumpvars;
// dump everything
end
initial begin
HCLK =0;
//Inputs init:ialization
forever begin: block1
if (HCLK> 400)begin
disable block1;
end
else #(5) HCLK<=~HCLK;
end
end
initial begin
// Input Initialization
WR = 1'b0;
RA = 5'b00101;
RB = 5'b01010;
RW = 5'b00000;
DW = 32'b0000000000000000000000000000000000000;
#10;
WR = 1'b1;
RA = 5'b00101;
RB = 5'b01010;
RW =5'b00101;
DW = 32'b00000000000000000000000001100100;
#10;
`CHECK_DA(32'b00000000000000000000000001100100, 1);
//`CHECK_DB(5'b01010, 1);
WR = 1'b1;
RA = 5'b00101;
RB = 5'b01010;
RW = 5'b01010;
DW = 32'b00000000000000000000000011001000;
#10;
`CHECK_DA(32'b00000000000000000000000001100100, 2);
`CHECK_DB(32'b00000000000000000000000011001000, 3);
WR = 1'b1;
RA = 5'b10100;
RB = 5'b01010;
RW = 5'b10100;
DW = 32'b11111111111110110110101111000010;
#100;
`CHECK_DA(32'b11111111111110110110101111000010, 4);
`CHECK_DB(32'b00000000000000000000000011001000, 5);
WR = 1'b1;
RA = 5'b10100;
RB = 5'b01010;
RW = 5'b10100;
DW = 32'b00000000000000000000001110000011;
#10;
`CHECK_DA(32'b00000000000000000000001110000011, 6);
`CHECK_DB(32'b00000000000000000000000011001000, 7);
// Reset
#100;
WR = 1'b0;
RA = 5'b10100;
RB = 5'b01010;
RW = 5'b10100;
DW = 32'b10000000011100000000001110000011;
#10;
`CHECK_DA(32'b00000000000000000000001110000011, 8);
`CHECK_DB(32'b00000000000000000000000011001000, 9);
// Reset
#100;
$finish;
end
endmodule |
module regfile (
input HCLK, // System clock
input WR,
input [ 4:0] RA,
input [ 4:0] RB,
input [ 4:0] RW,
input [31:0] DW,
output [31:0] DA,
output [31:0] DB
);
reg [31:0] RF [31:0];
assign DA = RF[RA] & {32{~(RA==5'd0)}};
assign DB = RF[RB] & {32{~(RB==5'd0)}};
always @ (posedge HCLK)
if(WR)
if(RW!=5'd0) begin
RF[RW] <= DW;
//#1 $display("Write: RF[%d]=0x%X []", RW, RF[RW]);
end
endmodule |
module sha1_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire [511 : 0] block,
output wire ready,
output wire [159 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter H0_0 = 32'h67452301;
parameter H0_1 = 32'hefcdab89;
parameter H0_2 = 32'h98badcfe;
parameter H0_3 = 32'h10325476;
parameter H0_4 = 32'hc3d2e1f0;
parameter SHA1_ROUNDS = 79;
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] a_reg;
reg [31 : 0] a_new;
reg [31 : 0] b_reg;
reg [31 : 0] b_new;
reg [31 : 0] c_reg;
reg [31 : 0] c_new;
reg [31 : 0] d_reg;
reg [31 : 0] d_new;
reg [31 : 0] e_reg;
reg [31 : 0] e_new;
reg a_e_we;
reg [31 : 0] H0_reg;
reg [31 : 0] H0_new;
reg [31 : 0] H1_reg;
reg [31 : 0] H1_new;
reg [31 : 0] H2_reg;
reg [31 : 0] H2_new;
reg [31 : 0] H3_reg;
reg [31 : 0] H3_new;
reg [31 : 0] H4_reg;
reg [31 : 0] H4_new;
reg H_we;
reg [6 : 0] round_ctr_reg;
reg [6 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_inc;
reg round_ctr_rst;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha1_ctrl_reg;
reg [1 : 0] sha1_ctrl_new;
reg sha1_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg ready_flag;
reg w_init;
reg w_next;
wire [31 : 0] w;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
sha1_w_mem w_mem_inst(
.clk(clk),
.reset_n(reset_n),
.block(block),
.init(w_init),
.next(w_next),
.w(w)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// asynchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
a_reg <= 32'h0;
b_reg <= 32'h0;
c_reg <= 32'h0;
d_reg <= 32'h0;
e_reg <= 32'h0;
H0_reg <= 32'h0;
H1_reg <= 32'h0;
H2_reg <= 32'h0;
H3_reg <= 32'h0;
H4_reg <= 32'h0;
digest_valid_reg <= 1'h0;
round_ctr_reg <= 7'h0;
sha1_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (a_e_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
end
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (digest_valid_we)
digest_valid_reg <= digest_valid_new;
if (sha1_ctrl_we)
sha1_ctrl_reg <= sha1_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 32'h0;
H1_new = 32'h0;
H2_new = 32'h0;
H3_new = 32'h0;
H4_new = 32'h0;
H_we = 0;
if (digest_init)
begin
H0_new = H0_0;
H1_new = H0_1;
H2_new = H0_2;
H3_new = H0_3;
H4_new = H0_4;
H_we = 1;
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
reg [31 : 0] a5;
reg [31 : 0] f;
reg [31 : 0] k;
reg [31 : 0] t;
a5 = 32'h0;
f = 32'h0;
k = 32'h0;
t = 32'h0;
a_new = 32'h0;
b_new = 32'h0;
c_new = 32'h0;
d_new = 32'h0;
e_new = 32'h0;
a_e_we = 1'h0;
if (state_init)
begin
if (first_block)
begin
a_new = H0_0;
b_new = H0_1;
c_new = H0_2;
d_new = H0_3;
e_new = H0_4;
a_e_we = 1;
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
a_e_we = 1;
end
end
if (state_update)
begin
if (round_ctr_reg <= 19)
begin
k = 32'h5a827999;
f = ((b_reg & c_reg) ^ (~b_reg & d_reg));
end
else if ((round_ctr_reg >= 20) && (round_ctr_reg <= 39))
begin
k = 32'h6ed9eba1;
f = b_reg ^ c_reg ^ d_reg;
end
else if ((round_ctr_reg >= 40) && (round_ctr_reg <= 59))
begin
k = 32'h8f1bbcdc;
f = ((b_reg | c_reg) ^ (b_reg | d_reg) ^ (c_reg | d_reg));
end
else if (round_ctr_reg >= 60)
begin
k = 32'hca62c1d6;
f = b_reg ^ c_reg ^ d_reg;
end
a5 = {a_reg[26 : 0], a_reg[31 : 27]};
t = a5 + e_reg + f + k + w;
a_new = t;
b_new = a_reg;
c_new = {b_reg[1 : 0], b_reg[31 : 2]};
d_new = c_reg;
e_new = d_reg;
a_e_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// round_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 7'h0;
round_ctr_we = 1'h0;
if (round_ctr_rst)
begin
round_ctr_new = 7'h0;
round_ctr_we = 1'h1;
end
if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'h1;
round_ctr_we = 1;
end
end // round_ctr
//----------------------------------------------------------------
// sha1_ctrl_fsm
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha1_ctrl_fsm
digest_init = 1'h0;
digest_update = 1'h0;
state_init = 1'h0;
state_update = 1'h0;
first_block = 1'h0;
ready_flag = 1'h0;
w_init = 1'h0;
w_next = 1'h0;
round_ctr_inc = 1'h0;
round_ctr_rst = 1'h0;
digest_valid_new = 1'h0;
digest_valid_we = 1'h0;
sha1_ctrl_new = CTRL_IDLE;
sha1_ctrl_we = 1'h0;
case (sha1_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
if (init)
begin
digest_init = 1'h1;
w_init = 1'h1;
state_init = 1'h1;
first_block = 1'h1;
round_ctr_rst = 1'h1;
digest_valid_new = 1'h0;
digest_valid_we = 1'h1;
sha1_ctrl_new = CTRL_ROUNDS;
sha1_ctrl_we = 1'h1;
end
if (next)
begin
w_init = 1'h1;
state_init = 1'h1;
round_ctr_rst = 1'h1;
digest_valid_new = 1'h0;
digest_valid_we = 1'h1;
sha1_ctrl_new = CTRL_ROUNDS;
sha1_ctrl_we = 1'h1;
end
end
CTRL_ROUNDS:
begin
state_update = 1'h1;
round_ctr_inc = 1'h1;
w_next = 1'h1;
if (round_ctr_reg == SHA1_ROUNDS)
begin
sha1_ctrl_new = CTRL_DONE;
sha1_ctrl_we = 1'h1;
end
end
CTRL_DONE:
begin
digest_update = 1'h1;
digest_valid_new = 1'h1;
digest_valid_we = 1'h1;
sha1_ctrl_new = CTRL_IDLE;
sha1_ctrl_we = 1'h1;
end
endcase // case (sha1_ctrl_reg)
end // sha1_ctrl_fsm
endmodule // sha1_core |
module sha1(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_BLOCK0 = 8'h10;
localparam ADDR_BLOCK15 = 8'h1f;
localparam ADDR_DIGEST0 = 8'h20;
localparam ADDR_DIGEST4 = 8'h24;
localparam CORE_NAME0 = 32'h73686131; // "sha1"
localparam CORE_NAME1 = 32'h20202020; // " "
localparam CORE_VERSION = 32'h302e3630; // "0.60"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg ready_reg;
reg [31 : 0] block_reg [0 : 15];
reg block_we;
reg [159 : 0] digest_reg;
reg digest_valid_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire core_ready;
wire [511 : 0] core_block;
wire [159 : 0] core_digest;
wire core_digest_valid;
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
block_reg[04], block_reg[05], block_reg[06], block_reg[07],
block_reg[08], block_reg[09], block_reg[10], block_reg[11],
block_reg[12], block_reg[13], block_reg[14], block_reg[15]};
assign read_data = tmp_read_data;
assign error = tmp_error;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
sha1_core core(
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next(next_reg),
.block(core_block),
.ready(core_ready),
.digest(core_digest),
.digest_valid(core_digest_valid)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// asynchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
init_reg <= 1'h0;
next_reg <= 1'h0;
ready_reg <= 1'h0;
digest_reg <= 160'h0;
digest_valid_reg <= 1'h0;
for (i = 0 ; i < 16 ; i = i + 1)
block_reg[i] <= 32'h0;
end
else
begin
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
init_reg <= init_new;
next_reg <= next_new;
if (block_we)
block_reg[address[3 : 0]] <= write_data;
if (core_digest_valid)
digest_reg <= core_digest;
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 1'h0;
next_new = 1'h0;
block_we = 1'h0;
tmp_read_data = 32'h0;
tmp_error = 1'h0;
if (cs)
begin
if (we)
begin
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
block_we = 1'h1;
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
end
end // if (write_read)
else
begin
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
tmp_read_data = block_reg[address[3 : 0]];
if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4))
tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32];
case (address)
// Read operations.
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {30'h0, next_reg, init_reg};
ADDR_STATUS:
tmp_read_data = {30'h0, digest_valid_reg, ready_reg};
default:
begin
tmp_error = 1'h1;
end
endcase // case (addr)
end
end
end // addr_decoder
endmodule // sha1 |
module sha1_w_mem(
input wire clk,
input wire reset_n,
input wire [511 : 0] block,
input wire init,
input wire next,
output wire [31 : 0] w
);
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
reg [31 : 0] w_mem00_new;
reg [31 : 0] w_mem01_new;
reg [31 : 0] w_mem02_new;
reg [31 : 0] w_mem03_new;
reg [31 : 0] w_mem04_new;
reg [31 : 0] w_mem05_new;
reg [31 : 0] w_mem06_new;
reg [31 : 0] w_mem07_new;
reg [31 : 0] w_mem08_new;
reg [31 : 0] w_mem09_new;
reg [31 : 0] w_mem10_new;
reg [31 : 0] w_mem11_new;
reg [31 : 0] w_mem12_new;
reg [31 : 0] w_mem13_new;
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
reg [6 : 0] w_ctr_reg;
reg [6 : 0] w_ctr_new;
reg w_ctr_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp;
reg [31 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// asynchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 16 ; i = i + 1)
w_mem[i] <= 32'h0;
w_ctr_reg <= 7'h0;
end
else
begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// W word selection logic. Returns either directly from the
// memory or the next w value calculated.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16)
w_tmp = w_mem[w_ctr_reg[3 : 0]];
else
w_tmp = w_new;
end // select_w
//----------------------------------------------------------------
// w_mem_update_logic
//
// Update logic for the W memory. This is where the scheduling
// based on a sliding window is implemented.
//----------------------------------------------------------------
always @*
begin : w_mem_update_logic
reg [31 : 0] w_0;
reg [31 : 0] w_2;
reg [31 : 0] w_8;
reg [31 : 0] w_13;
reg [31 : 0] w_16;
w_mem00_new = 32'h0;
w_mem01_new = 32'h0;
w_mem02_new = 32'h0;
w_mem03_new = 32'h0;
w_mem04_new = 32'h0;
w_mem05_new = 32'h0;
w_mem06_new = 32'h0;
w_mem07_new = 32'h0;
w_mem08_new = 32'h0;
w_mem09_new = 32'h0;
w_mem10_new = 32'h0;
w_mem11_new = 32'h0;
w_mem12_new = 32'h0;
w_mem13_new = 32'h0;
w_mem14_new = 32'h0;
w_mem15_new = 32'h0;
w_mem_we = 1'h0;
w_0 = w_mem[0];
w_2 = w_mem[2];
w_8 = w_mem[8];
w_13 = w_mem[13];
w_16 = w_13 ^ w_8 ^ w_2 ^ w_0;
w_new = {w_16[30 : 0], w_16[31]};
if (init)
begin
w_mem00_new = block[511 : 480];
w_mem01_new = block[479 : 448];
w_mem02_new = block[447 : 416];
w_mem03_new = block[415 : 384];
w_mem04_new = block[383 : 352];
w_mem05_new = block[351 : 320];
w_mem06_new = block[319 : 288];
w_mem07_new = block[287 : 256];
w_mem08_new = block[255 : 224];
w_mem09_new = block[223 : 192];
w_mem10_new = block[191 : 160];
w_mem11_new = block[159 : 128];
w_mem12_new = block[127 : 96];
w_mem13_new = block[95 : 64];
w_mem14_new = block[63 : 32];
w_mem15_new = block[31 : 0];
w_mem_we = 1'h1;
end
if (next && (w_ctr_reg > 15))
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1'h1;
end
end // w_mem_update_logic
//----------------------------------------------------------------
// w_ctr
//
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 7'h0;
w_ctr_we = 1'h0;
if (init)
begin
w_ctr_new = 7'h0;
w_ctr_we = 1'h1;
end
if (next)
begin
w_ctr_new = w_ctr_reg + 7'h01;
w_ctr_we = 1'h1;
end
end // w_ctr
endmodule // sha1_w_mem |
module apple1 #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input clk25, // 25 MHz master clock
input rst_n, // active low synchronous reset (needed for simulation)
// I/O interface to computer
input uart_rx, // asynchronous serial data input from computer
output uart_tx, // asynchronous serial data output to computer
output uart_cts, // clear to send flag to computer
// I/O interface to keyboard
input ps2_clk, // PS/2 keyboard serial clock input
input ps2_din, // PS/2 keyboard serial data input
input ps2_select, // Input to select the PS/2 keyboard instead of the UART
// Outputs to VGA display
output vga_h_sync, // hozizontal VGA sync pulse
output vga_v_sync, // vertical VGA sync pulse
output vga_red, // red VGA signal
output vga_grn, // green VGA signal
output vga_blu, // blue VGA signal
input vga_cls, // clear screen button
// Debugging ports
output [15:0] pc_monitor // spy for program counter / debugging
);
//////////////////////////////////////////////////////////////////////////
// Registers and Wires
wire [15:0] ab;
wire [7:0] dbi;
wire [7:0] dbo;
wire we;
//////////////////////////////////////////////////////////////////////////
// Clocks
wire cpu_clken;
clock my_clock(
.clk25(clk25),
.rst_n(rst_n),
.cpu_clken(cpu_clken)
);
//////////////////////////////////////////////////////////////////////////
// Reset
wire rst;
pwr_reset my_reset(
.clk25(clk25),
.rst_n(rst_n),
.enable(cpu_clken),
.rst(rst)
);
//////////////////////////////////////////////////////////////////////////
// 6502
arlet_6502 my_cpu(
.clk (clk25),
.enable (cpu_clken),
.rst (rst),
.ab (ab),
.dbi (dbi),
.dbo (dbo),
.we (we),
.irq_n (1'b1),
.nmi_n (1'b1),
.ready (cpu_clken),
.pc_monitor (pc_monitor)
);
//////////////////////////////////////////////////////////////////////////
// Address Decoding
wire ram_cs = (ab[15:13] == 3'b000); // 0x0000 -> 0x1FFF
// font mode, background and foreground colour
wire vga_mode_cs = (ab[15:2] == 14'b11000000000000); // 0xC000 -> 0xC003
// RX: Either keyboard or UART input
// TX: Always VGA and UART output
wire rx_cs = (ab[15:1] == 15'b110100000001000); // 0xD010 -> 0xD011
wire tx_cs = (ab[15:1] == 15'b110100000001001); // 0xD012 -> 0xD013
// select UART on transmit but only receive when PS/2 is not selected.
wire uart_cs = tx_cs | ((~ps2_select) & rx_cs);
// select PS/2 keyboard input when selected.
wire ps2kb_cs = ps2_select & rx_cs;
// VGA always get characters when they are sent.
wire vga_cs = tx_cs;
wire basic_cs = (ab[15:12] == 4'b1110); // 0xE000 -> 0xEFFF
wire rom_cs = (ab[15:8] == 8'b11111111); // 0xFF00 -> 0xFFFF
//////////////////////////////////////////////////////////////////////////
// RAM and ROM
// RAM
wire [7:0] ram_dout;
ram #(
.RAM_FILENAME (RAM_FILENAME)
) my_ram(
.clk(clk25),
.address(ab[12:0]),
.w_en(we & ram_cs),
.din(dbo),
.dout(ram_dout)
);
// WozMon ROM
wire [7:0] rom_dout;
rom_wozmon #(
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) my_rom_wozmon(
.clk(clk25),
.address(ab[7:0]),
.dout(rom_dout)
);
// Basic ROM
wire [7:0] basic_dout;
rom_basic #(
.BASIC_FILENAME (BASIC_FILENAME)
) my_rom_basic(
.clk(clk25),
.address(ab[11:0]),
.dout(basic_dout)
);
//////////////////////////////////////////////////////////////////////////
// Peripherals
// UART
wire [7:0] uart_dout;
uart #(
`ifdef SIM
100, 10, 2 // for simulation don't need real baud rates
`else
25000000, 115200, 8 // 25MHz, 115200 baud, 8 times RX oversampling
`endif
) my_uart(
.clk(clk25),
.enable(uart_cs & cpu_clken),
.rst(rst),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts),
.address(ab[1:0]), // for uart
.w_en(we & uart_cs),
.din(dbo),
.dout(uart_dout)
);
// PS/2 keyboard interface
wire [7:0] ps2_dout;
ps2keyboard keyboard(
.clk25(clk25),
.rst(rst),
.key_clk(ps2_clk),
.key_din(ps2_din),
.cs(ps2kb_cs),
.address(ab[0]),
.dout(ps2_dout)
);
// VGA Display interface
reg [2:0] fg_colour;
reg [2:0] bg_colour;
reg [1:0] font_mode;
reg [7:0] vga_mode_dout;
vga #(
.VRAM_FILENAME (VRAM_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME)
) my_vga(
.clk25(clk25),
.enable(vga_cs & cpu_clken),
.rst(rst),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),
.vga_grn(vga_grn),
.vga_blu(vga_blu),
.address(ab[0]),
.w_en(we & vga_cs),
.din(dbo),
.mode(font_mode),
.fg_colour(fg_colour),
.bg_colour(bg_colour),
.clr_screen(vga_cls)
);
// Handle font mode and foreground and background
// colours. This so isn't Apple One authentic, but
// it can't hurt to have some fun. :D
always @(posedge clk25 or posedge rst)
begin
if (rst)
begin
font_mode <= 2'b0;
fg_colour <= 3'd7;
bg_colour <= 3'd0;
end
else
begin
case (ab[1:0])
2'b00:
begin
vga_mode_dout = {6'b0, font_mode};
if (vga_mode_cs & we & cpu_clken)
font_mode <= dbo[1:0];
end
2'b01:
begin
vga_mode_dout = {5'b0, fg_colour};
if (vga_mode_cs & we & cpu_clken)
fg_colour <= dbo[2:0];
end
2'b10:
begin
vga_mode_dout = {5'b0, bg_colour};
if (vga_mode_cs & we & cpu_clken)
bg_colour <= dbo[2:0];
end
default:
vga_mode_dout = 8'b0;
endcase
end
end
//////////////////////////////////////////////////////////////////////////
// CPU Data In MUX
// link up chip selected device to cpu input
assign dbi = ram_cs ? ram_dout :
rom_cs ? rom_dout :
basic_cs ? basic_dout :
uart_cs ? uart_dout :
ps2kb_cs ? ps2_dout :
vga_mode_cs ? vga_mode_dout :
8'hFF;
endmodule |
module ram #(
parameter RAM_FILENAME = "../../../roms/ram.hex"
) (
input clk, // clock signal
input [12:0] address, // address bus
input w_en, // active high write enable strobe
input [7:0] din, // 8-bit data bus (input)
output reg [7:0] dout // 8-bit data bus (output)
);
reg [7:0] ram_data[0:8191];
initial
$readmemh(RAM_FILENAME, ram_data, 0, 8191);
always @(posedge clk)
begin
dout <= ram_data[address];
if (w_en) ram_data[address] <= din;
end
endmodule |
module clock(
input clk25, // 25MHz clock master clock
input rst_n, // active low synchronous reset
// Clock enables
output reg cpu_clken // 1MHz clock enable for the CPU and devices
);
// generate clock enable once every
// 25 clocks. This will (hopefully) make
// the 6502 run at 1 MHz or 1Hz
//
// the clock division counter is synchronously
// reset using rst_n to avoid undefined signals
// in simulation
//
//`define SLOWCPU
`ifdef SLOWCPU
reg [25:0] clk_div;
always @(posedge clk25)
begin
// note: clk_div should be compared to
// N-1, where N is the clock divisor
if ((clk_div == 24999999) || (rst_n == 1'b0))
clk_div <= 0;
else
clk_div <= clk_div + 1'b1;
cpu_clken <= (clk_div[25:0] == 0);
end
`else
reg [4:0] clk_div;
always @(posedge clk25)
begin
// note: clk_div should be compared to
// N-1, where N is the clock divisor
if ((clk_div == 24) || (rst_n == 1'b0))
clk_div <= 0;
else
clk_div <= clk_div + 1'b1;
cpu_clken <= (clk_div[4:0] == 0);
end
`endif
endmodule |
module rom_basic #(
parameter BASIC_FILENAME = "../../../roms/basic.hex"
) (
input clk, // clock signal
input [11:0] address, // address bus
output reg [7:0] dout // 8-bit data bus (output)
);
reg [7:0] rom_data[0:4095];
initial
$readmemh(BASIC_FILENAME, rom_data, 0, 4095);
always @(posedge clk)
dout <= rom_data[address];
endmodule |
module pwr_reset(
input clk25, // 25Mhz master clock
input rst_n, // active low synchronous reset
input enable, // clock enable
output rst // active high synchronous system reset
);
reg hard_reset;
reg [5:0] reset_cnt;
wire pwr_up_flag = &reset_cnt;
always @(posedge clk25)
begin
if (rst_n == 1'b0)
begin
reset_cnt <= 6'b0;
hard_reset <= 1'b0;
end
else if (enable)
begin
if (!pwr_up_flag)
reset_cnt <= reset_cnt + 6'b1;
hard_reset <= pwr_up_flag;
end
end
assign rst = ~hard_reset;
endmodule |
module rom_wozmon #(
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input clk, // clock signal
input [7:0] address, // address bus
output reg [7:0] dout // 8-bit data bus (output)
);
reg [7:0] rom_data[0:255];
initial
$readmemh(WOZMON_ROM_FILENAME, rom_data, 0, 255);
always @(posedge clk)
dout <= rom_data[address];
endmodule |
module vga_tb;
reg clk25, rst, address, w_en, blink_clken;
reg [7:0] din;
wire vga_h_sync, vga_v_sync, vga_red, vga_grn, vga_blu;
//////////////////////////////////////////////////////////////////////////
// Setup dumping of data for inspection
initial begin
clk25 = 1'b0;
rst = 1'b0;
address = 1'b0;
w_en = 1'b0;
blink_clken = 1'b0;
din = 8'd0;
#5
rst = 1'b1;
#5
rst = 1'b0;
$display("Starting...");
$dumpfile("vga_tb.vcd");
$dumpvars;
//#180000
//uart_rx = 1'b0;
//#400
//uart_rx = 1'b1;
//#400
//uart_rx = 1'b0;
//#400
//uart_rx = 1'b1;
//#800
//uart_rx = 1'b0;
//#1600
//uart_rx = 1'b1;
#50000000 $display("Stopping...");
$finish;
end
//////////////////////////////////////////////////////////////////////////
// Clock
always
#20 clk25 = !clk25;
//////////////////////////////////////////////////////////////////////////
// Core of system
vga my_vga (
.clk25(clk25),
.enable(1'b1),
.rst(rst),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),
.vga_grn(vga_grn),
.vga_blu(vga_blu),
.address(address),
.w_en(w_en),
.din(din)
);
endmodule |
module uart_tb;
reg clk25, enable, rst, w_en, uart_rx;
reg [2:0] state;
reg [1:0] address;
reg [7:0] din;
wire [7:0] dout;
wire uart_tx, uart_cts;
//////////////////////////////////////////////////////////////////////////
// Setup dumping of data for inspection
initial begin
state = 3'd0;
clk25 = 1'b0;
rst = 1'b1;
enable = 1'b0;
w_en = 1'b0;
uart_rx = 1'b1;
address = 2'b11;
din = 8'b0;
$display("Starting...");
$dumpfile("uart_tb.vcd");
$dumpvars;
#40
rst = 1'b0; // reset release
state = 3'd1;
#1 // TX first byte - ignored
address = 2'b10;
din = 8'b00101010;
enable = 1'b1;
w_en = 1'b1;
state = 3'd3;
#2
w_en = 1'b0;
enable = 1'b0;
state = 3'd4;
#40 // TX second byte
address = 2'b10;
din = 8'b00101010;
enable = 1'b1;
w_en = 1'b1;
state = 3'd3;
#2
w_en = 1'b0;
enable = 1'b0;
state = 3'd4;
#6000
state = 3'd5;
uart_rx = 1'b1;
#434 uart_rx = 1'b0; // start
#434 uart_rx = 1'b0; // 1
#434 uart_rx = 1'b1; // 2
#434 uart_rx = 1'b0; // 3
#434 uart_rx = 1'b1; // 4
#434 uart_rx = 1'b0; // 5
#434 uart_rx = 1'b1; // 6
#434 uart_rx = 1'b0; // 7
#434 uart_rx = 1'b1; // 8
#434 uart_rx = 1'b1; // stop bit 1
#434 uart_rx = 1'b1; // stop bit 2
state = 3'd6;
#6000
address = 2'b00;
enable = 1'b1;
state = 3'd7;
#20
enable = 1'b0;
#10000 $display("Stopping...");
$finish;
end
//////////////////////////////////////////////////////////////////////////
// Clock
always
#1 clk25 = !clk25;
//////////////////////////////////////////////////////////////////////////
// Core of system
uart #(
.ClkFrequency(25000000),
.Baud(115200),
.Oversampling(8)
) my_uart (
.clk(clk25),
.enable(1'b1),
.rst(rst),
.address(address),
.w_en(w_en),
.din(din),
.dout(dout),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts)
);
endmodule |
module apple1_tb #(
parameter BASIC_FILENAME = "../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../roms/ram.hex",
parameter VRAM_FILENAME = "../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../roms/wozmon.hex"
);
reg clk25, uart_rx, rst_n;
wire uart_tx, uart_cts;
//////////////////////////////////////////////////////////////////////////
// Setup dumping of data for inspection
initial begin
clk25 = 1'b0;
uart_rx = 1'b1;
rst_n = 1'b0;
#40 rst_n = 1'b1;
$display("Starting...");
$dumpfile("apple1_top_tb.vcd");
$dumpvars;
#180000
uart_rx = 1'b0;
#400
uart_rx = 1'b1;
#400
uart_rx = 1'b0;
#400
uart_rx = 1'b1;
#800
uart_rx = 1'b0;
#1600
uart_rx = 1'b1;
#1000000 $display("Stopping...");
$finish;
end
//////////////////////////////////////////////////////////////////////////
// Clock
always
#20 clk25 = !clk25;
//////////////////////////////////////////////////////////////////////////
// Core of system
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) core_top (
.clk25(clk25),
.rst_n(rst_n),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts)
);
endmodule |
module async_transmitter(
input clk,
input rst,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
////////////////////////////////
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .rst(rst), .enable(TxD_busy), .tick(BitTick));
reg [3:0] TxD_state;
reg [7:0] TxD_shift;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
TxD_state <= 0;
TxD_shift <= 0;
end
else
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);
endmodule |
module uart(
input clk, // clock signal
input enable, // clock enable strobe
input rst, // active high reset signal
input [1:0] address, // address bus
input w_en, // active high write enable strobe
input [7:0] din, // 8-bit data bus (input)
output reg [7:0] dout, // 8-bit data bus (output)
input uart_rx, // asynchronous serial data input from computer
output uart_tx, // asynchronous serial data output to computer
output uart_cts // clear to send flag to computer
);
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
parameter Oversampling = 16;
reg uart_tx_stb, uart_tx_init;
reg [7:0] uart_tx_byte;
wire uart_tx_status;
async_transmitter #(ClkFrequency, Baud) my_tx (
.clk(clk),
.rst(rst),
.TxD_start(uart_tx_stb),
.TxD_data(uart_tx_byte),
.TxD(uart_tx),
.TxD_busy(uart_tx_status)
);
wire uart_rx_stb, rx_idle, rx_end;
wire [7:0] rx_data;
reg uart_rx_status, uart_rx_ack;
reg [7:0] uart_rx_byte;
async_receiver #(ClkFrequency, Baud, Oversampling) my_rx(
.clk(clk),
.rst(rst),
.RxD(uart_rx),
.RxD_data_ready(uart_rx_stb),
.RxD_data(rx_data),
.RxD_idle(rx_idle),
.RxD_endofpacket(rx_end)
);
always @(posedge clk or posedge rst)
begin
if (rst)
begin
uart_rx_status <= 'b0;
uart_rx_byte <= 8'd0;
end
else
begin
// new byte from RX, check register is clear and CPU has seen
// previous byte, otherwise we ignore the new data
if (uart_rx_stb && ~uart_rx_status)
begin
uart_rx_status <= 'b1;
uart_rx_byte <= rx_data;
end
// clear the rx status flag on ack from CPU
if (uart_rx_ack)
uart_rx_status <= 'b0;
end
end
assign uart_cts = ~rx_idle || uart_rx_status;
localparam UART_RX = 2'b00;
localparam UART_RXCR = 2'b01;
localparam UART_TX = 2'b10;
localparam UART_TXCR = 2'b11;
// Handle Register
always @(posedge clk or posedge rst)
begin
if (rst)
begin
dout <= 8'd0;
uart_tx_init <= 0; // flag to ignore the DDR setup from Wozmon PIA call
uart_tx_stb <= 0;
uart_tx_byte <= 8'd0;
uart_rx_ack <= 0;
end
else
begin
uart_tx_stb <= 0;
uart_rx_ack <= 0;
case (address)
UART_RX:
begin
// UART RX - 0xD010
// Bit b7 of KBD is permanently tied to high
dout <= {1'b1, uart_rx_byte[6:0]};
if (~w_en && ~uart_rx_ack && uart_rx_status && enable)
uart_rx_ack <= 1'b1;
end
UART_RXCR:
begin
// UART RX CR - 0xD011
dout <= {uart_rx_status, 7'b0};
end
UART_TX:
begin
// UART TX - 0xD012
dout <= {uart_tx_status, 7'd0};
if (w_en)
begin
// Apple 1 terminal only uses 7 bits, MSB indicates
// terminal has ack'd RX
//
// uart_tx_init is a flag to stop the first character
// sent to the UART from being sent. Wozmon initializes
// the PIA which normally isn't sent to the terminal.
// This causes the UART to ignore the very first byte sent.
if (~uart_tx_status && uart_tx_init)
begin
uart_tx_byte <= {1'b0, din[6:0]};
uart_tx_stb <= 1;
end
else if (~uart_tx_init)
uart_tx_init <= 1 && enable;
end
end
UART_TXCR:
begin
// UART TX CR - 0xD013
// Ignore the TX control register
dout <= 8'b0;
end
endcase
end
end
endmodule |
module ledAndKey(
input clk,
input clk_en,
input rst,
input [3:0] display,
input [7:0] digit1,
input [7:0] digit2,
input [7:0] digit3,
input [7:0] digit4,
input [7:0] digit5,
input [7:0] digit6,
input [7:0] digit7,
input [7:0] digit8,
input [7:0] leds,
output reg [7:0] keys,
output reg tm_cs,
output tm_clk,
inout tm_dio
);
localparam
HIGH = 1'b1,
LOW = 1'b0;
localparam [7:0]
C_READ = 8'b01000010,
C_WRITE = 8'b01000000,
C_DISP = 8'b10001111,
C_ADDR = 8'b11000000;
reg counter;
reg [5:0] instruction_step;
// set up tristate IO pin for display
// tm_dio is physical pin
// dio_in for reading from display
// dio_out for sending to display
// tm_rw selects input or output
reg tm_rw;
wire dio_in, dio_out;
SB_IO #(
.PIN_TYPE(6'b101001),
.PULLUP(1'b1)
) tm_dio_io (
.PACKAGE_PIN(tm_dio),
.OUTPUT_ENABLE(tm_rw),
.D_IN_0(dio_in),
.D_OUT_0(dio_out)
);
// setup tm1638 module with it's tristate IO
// tm_in is read from module
// tm_out is written to module
// tm_latch triggers the module to read/write display
// tm_rw selects read or write mode to display
// busy indicates when module is busy
// (another latch will interrupt)
// tm_clk is the data clk
// dio_in for reading from display
// dio_out for sending to display
//
// tm_data the tristate io pin to module
reg tm_latch;
wire busy;
wire [7:0] tm_data, tm_in;
reg [7:0] tm_out;
assign tm_in = tm_data;
assign tm_data = tm_rw ? tm_out : 8'hZZ;
tm1638 u_tm1638 (
.clk(clk),
.clk_en(clk_en),
.rst(rst),
.data_latch(tm_latch),
.data(tm_data),
.rw(tm_rw),
.busy(busy),
.sclk(tm_clk),
.dio_in(dio_in),
.dio_out(dio_out)
);
always @(posedge clk) begin
if (clk_en) begin
if (rst) begin
instruction_step <= 6'b0;
tm_cs <= HIGH;
tm_rw <= HIGH;
counter <= 1'b0;
keys <= 8'b0;
end else begin
if (counter && ~busy) begin
case (instruction_step)
// *** KEYS ***
1: {tm_cs, tm_rw} <= {LOW, HIGH};
2: {tm_latch, tm_out} <= {HIGH, C_READ}; // read mode
3: {tm_latch, tm_rw} <= {HIGH, LOW};
// read back keys S1 - S8
4: {keys[7], keys[3]} <= {tm_in[0], tm_in[4]};
5: {tm_latch} <= {HIGH};
6: {keys[6], keys[2]} <= {tm_in[0], tm_in[4]};
7: {tm_latch} <= {HIGH};
8: {keys[5], keys[1]} <= {tm_in[0], tm_in[4]};
9: {tm_latch} <= {HIGH};
10: {keys[4], keys[0]} <= {tm_in[0], tm_in[4]};
11: {tm_cs} <= {HIGH};
// *** DISPLAY ***
12: {tm_cs, tm_rw} <= {LOW, HIGH};
13: {tm_latch, tm_out} <= {HIGH, C_WRITE}; // write mode
14: {tm_cs} <= {HIGH};
15: {tm_cs, tm_rw} <= {LOW, HIGH};
16: {tm_latch, tm_out} <= {HIGH, C_ADDR}; // set addr 0 pos
17: {tm_latch, tm_out} <= {HIGH, digit1}; // Digit 1
18: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[7]}}; // LED 1
19: {tm_latch, tm_out} <= {HIGH, digit2}; // Digit 2
20: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[6]}}; // LED 2
21: {tm_latch, tm_out} <= {HIGH, digit3}; // Digit 3
22: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[5]}}; // LED 3
23: {tm_latch, tm_out} <= {HIGH, digit4}; // Digit 4
24: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[4]}}; // LED 4
25: {tm_latch, tm_out} <= {HIGH, digit5}; // Digit 5
26: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[3]}}; // LED 5
27: {tm_latch, tm_out} <= {HIGH, digit6}; // Digit 6
28: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[2]}}; // LED 6
29: {tm_latch, tm_out} <= {HIGH, digit7}; // Digit 7
30: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[1]}}; // LED 7
31: {tm_latch, tm_out} <= {HIGH, digit8}; // Digit 8
32: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[0]}}; // LED 8
33: {tm_cs} <= {HIGH};
34: {tm_cs, tm_rw} <= {LOW, HIGH};
35: {tm_latch, tm_out} <= {HIGH, {4'b1000, display}}; // display
36: {tm_cs, instruction_step} <= {HIGH, 6'b0};
endcase
instruction_step <= instruction_step + 1;
end else if (busy) begin
// pull latch low next clock cycle after module has been
// latched
tm_latch <= LOW;
end
counter <= ~counter;
end
end
end
endmodule |
module tm1638(
input clk,
input clk_en,
input rst,
input data_latch,
inout [7:0] data,
input rw,
output busy,
output sclk,
input dio_in,
output reg dio_out
);
localparam CLK_DIV = 3; // seems happy at 12MHz with 3
localparam CLK_DIV1 = CLK_DIV - 1;
localparam [1:0]
S_IDLE = 2'h0,
S_WAIT = 2'h1,
S_TRANSFER = 2'h2;
reg [1:0] cur_state, next_state;
reg [CLK_DIV1:0] sclk_d, sclk_q;
reg [7:0] data_d, data_q, data_out_d, data_out_q;
reg dio_out_d;
reg [2:0] ctr_d, ctr_q;
// output read data if we're reading
assign data = rw ? 8'hZZ : data_out_q;
// we're busy if we're not idle
assign busy = cur_state != S_IDLE;
// tick the clock if we're transfering data
assign sclk = ~((~sclk_q[CLK_DIV1]) & (cur_state == S_TRANSFER));
always @(*)
begin
sclk_d = sclk_q;
data_d = data_q;
dio_out_d = dio_out;
ctr_d = ctr_q;
data_out_d = data_out_q;
next_state = cur_state;
case(cur_state)
S_IDLE: begin
sclk_d = 0;
if (data_latch) begin
// if we're reading, set to zero, otherwise latch in
// data to send
data_d = rw ? data : 8'b0;
next_state = S_WAIT;
end
end
S_WAIT: begin
sclk_d = sclk_q + 1;
// wait till we're halfway into clock pulse
if (sclk_q == {1'b0, {CLK_DIV1{1'b1}}}) begin
sclk_d = 0;
next_state = S_TRANSFER;
end
end
S_TRANSFER: begin
sclk_d = sclk_q + 1;
if (sclk_q == 0) begin
// start of clock pulse, output MSB
dio_out_d = data_q[0];
end else if (sclk_q == {1'b0, {CLK_DIV1{1'b1}}}) begin
// halfway through pulse, read from device
data_d = {dio_in, data_q[7:1]};
end else if (&sclk_q) begin
// end of pulse, tick the counter
ctr_d = ctr_q + 1;
if (&ctr_q) begin
// last bit sent, switch back to idle
// and output any data recieved
next_state = S_IDLE;
data_out_d = data_q;
dio_out_d = 0;
end
end
end
default:
next_state = S_IDLE;
endcase
end
always @(posedge clk)
begin
if (clk_en)
begin
if (rst)
begin
cur_state <= S_IDLE;
sclk_q <= 0;
ctr_q <= 0;
dio_out <= 0;
data_q <= 0;
data_out_q <= 0;
end
else
begin
cur_state <= next_state;
sclk_q <= sclk_d;
ctr_q <= ctr_d;
dio_out <= dio_out_d;
data_q <= data_d;
data_out_q <= data_out_d;
end
end
end
endmodule |
module debounce(
input clk25, // 25MHz clock
input rst, // active high reset
input sig_in, // input signal
output reg sig_out // debounced output signal
);
wire clk_enb; // enable triggering at clk25 divided by 64
reg [5:0] clk_div; // clock divider counter
reg sig_ff1; // first input signal synchronizer
reg sig_ff2; // second input signal synchronizer
assign clk_enb = (clk_div == 6'd0);
// clock divider
always @(posedge clk25 or posedge rst)
begin
if (rst)
clk_div <= 6'd0;
else
clk_div <= clk_div + 6'd1;
end
// debounce timer
always @(posedge clk25 or posedge rst)
begin
if (rst)
begin
sig_out <= 1'b0;
sig_ff1 <= 1'b0;
sig_ff2 <= 1'b0;
end
else if (clk_enb)
begin
// this runs ar approximately 391k Hz
// giving a debounce time of around 2.5us
sig_ff1 <= sig_in;
sig_ff2 <= sig_ff1;
if ((sig_ff1 ^ sig_ff2) == 1'd0)
begin
sig_out <= sig_ff2;
end
end
end
endmodule |
module ps2keyboard (
input clk25, // 25MHz clock
input rst, // active high reset
// I/O interface to keyboard
input key_clk, // clock input from keyboard / device
input key_din, // data input from keyboard / device
// I/O interface to computer
input cs, // chip select, active high
input address, // =0 RX buffer, =1 RX status
output reg [7:0] dout // 8-bit output bus.
);
reg [3:0] rxcnt; // count how many bits have been shift into rxshiftbuf
reg [10:0] rxshiftbuf; // 11 bit shift receive register
reg rx_flag = 0; // this flag is 1 when
// valid data is available in rxshiftbuf
reg [7:0] rx; // scancode receive buffer
wire ps2_clkdb; // debounced PS/2 clock signal
reg prev_ps2_clkdb; // previous clock state (in clk25 domain)
// keyboard translation signals
reg [7:0] ascii; // ASCII code of received character
reg ascii_rdy; // new ASCII character received
reg shift; // state of the shift key
reg [2:0] cur_state;
reg [2:0] next_state;
debounce ps2clk_debounce
(
.clk25(clk25),
.rst(rst),
.sig_in(key_clk),
.sig_out(ps2_clkdb)
);
always @(posedge clk25 or posedge rst)
begin
if (rst)
begin
prev_ps2_clkdb <= 1'b0;
rx_flag <= 1'b0;
end
else
begin
rx_flag <= 1'b0; // reset the new data flag register
// check for negative edge of PS/2 clock
// and sample the state of the PS/2 data line
if ((prev_ps2_clkdb == 1'b1) && (ps2_clkdb == 1'b0))
begin
rxshiftbuf <= {key_din, rxshiftbuf[10:1]};
rxcnt <= rxcnt + 4'b1;
if (rxcnt == 4'd10)
begin
// 10 bits have been shifted in
// we should have a complete
// scan code here, including
// start, parity and stop bits.
rxcnt <= 0;
// signal new data is present
// note: this signal will only remain high for one
// clock cycle!
//
// TODO: check parity here?
rx_flag <= 1'b1;
end
end
// update previous clock state
prev_ps2_clkdb <= ps2_clkdb;
end
end
//
// IBM Keyboard code page translation
// state machine for US keyboard layout
//
// http://www.computer-engineering.org/ps2keyboard/scancodes2.html
//
localparam S_KEYNORMAL = 3'b000;
localparam S_KEYF0 = 3'b001; // regular key release state
localparam S_KEYE0 = 3'b010; // extended key state
localparam S_KEYE0F0 = 3'b011; // extended release state
always @(posedge clk25 or posedge rst)
begin
if (rst)
begin
rx <= 0;
ascii_rdy <= 0;
shift <= 0;
cur_state <= S_KEYNORMAL;
end
else
begin
// handle I/O from CPU
if (cs == 1'b1)
begin
if (address == 1'b0)
begin
// RX buffer address
dout <= {1'b1, ascii[6:0]};
ascii_rdy <= 1'b0;
end
else
begin
// RX status register
dout <= {ascii_rdy, 7'b0};
end
end
// keyboard translation state machine
if (rx_flag == 1'b1)
begin
// latch data from the serial buffer into
// the rx scancode buffer.
rx <= rxshiftbuf[8:1];
case(cur_state)
S_KEYNORMAL:
begin
if (rx == 8'hF0)
next_state = S_KEYF0;
else if (rx == 8'hE0)
next_state = S_KEYE0;
else
begin
// check the debounce timer, if this is
// not zero, a new key arrived too quickly
// and we simply discard it. For better
// debouncing, we should check if the key
// is actually the same as the previous received/
// key, but let's try this first to see if it works
// ok...
//if (debounce_timer == 16'd0)
//begin
ascii_rdy <= 1'b1; // new key has arrived!
//debounce_timer <= 16'hFFFF; // reset the debounce timer
//end
// check for a SHIFT key
if ((rx == 8'h59) || (rx == 8'h12))
begin
shift <= 1'b1;
ascii_rdy <= 1'b0; // shift is not a key!
end
else begin
if (!shift)
case(rx)
8'h1C: ascii <= "A";
8'h32: ascii <= "B";
8'h21: ascii <= "C";
8'h23: ascii <= "D";
8'h24: ascii <= "E";
8'h2B: ascii <= "F";
8'h34: ascii <= "G";
8'h33: ascii <= "H";
8'h43: ascii <= "I";
8'h3B: ascii <= "J";
8'h42: ascii <= "K";
8'h4B: ascii <= "L";
8'h3A: ascii <= "M";
8'h31: ascii <= "N";
8'h44: ascii <= "O";
8'h4D: ascii <= "P";
8'h15: ascii <= "Q";
8'h2D: ascii <= "R";
8'h1B: ascii <= "S";
8'h2C: ascii <= "T";
8'h3C: ascii <= "U";
8'h2A: ascii <= "V";
8'h1D: ascii <= "W";
8'h22: ascii <= "X";
8'h35: ascii <= "Y";
8'h1A: ascii <= "Z";
8'h45: ascii <= "0";
8'h16: ascii <= "1";
8'h1E: ascii <= "2";
8'h26: ascii <= "3";
8'h25: ascii <= "4";
8'h2E: ascii <= "5";
8'h36: ascii <= "6";
8'h3D: ascii <= "7";
8'h3E: ascii <= "8";
8'h46: ascii <= "9";
8'h4E: ascii <= "-";
8'h55: ascii <= "=";
8'h5D: ascii <= 8'h34; // backslash
8'h66: ascii <= "_"; // backspace
8'h29: ascii <= " ";
8'h5A: ascii <= 8'd13; // enter
8'h54: ascii <= "[";
8'h5B: ascii <= "]";
8'h4C: ascii <= ";";
8'h52: ascii <= "'";
8'h41: ascii <= ",";
8'h49: ascii <= ".";
8'h4A: ascii <= "/";
default:
// unsupported key!
begin
ascii_rdy <= 1'b0; // shift is not a key!
ascii <= " ";
end
endcase
else
// Here, we're in a shifted state
case(rx)
8'h1C: ascii <= "A";
8'h32: ascii <= "B";
8'h21: ascii <= "C";
8'h23: ascii <= "D";
8'h24: ascii <= "E";
8'h2B: ascii <= "F";
8'h34: ascii <= "G";
8'h33: ascii <= "H";
8'h43: ascii <= "I";
8'h3B: ascii <= "J";
8'h42: ascii <= "K";
8'h4B: ascii <= "L";
8'h3A: ascii <= "M";
8'h31: ascii <= "N";
8'h44: ascii <= "O";
8'h4D: ascii <= "P";
8'h15: ascii <= "Q";
8'h2D: ascii <= "R";
8'h1B: ascii <= "S";
8'h2C: ascii <= "T";
8'h3C: ascii <= "U";
8'h2A: ascii <= "V";
8'h1D: ascii <= "W";
8'h22: ascii <= "X";
8'h35: ascii <= "Y";
8'h1A: ascii <= "Z";
8'h45: ascii <= ")";
8'h16: ascii <= "!";
8'h1E: ascii <= "@";
8'h26: ascii <= "#";
8'h25: ascii <= "$";
8'h2E: ascii <= "%";
8'h36: ascii <= "^";
8'h3D: ascii <= "&";
8'h3E: ascii <= "*";
8'h46: ascii <= "(";
8'h4E: ascii <= "_";
8'h55: ascii <= "+";
8'h5D: ascii <= "|";
8'h66: ascii <= "_"; // backspace, normally ASCII 0x08 but '_' for Apple 1
8'h29: ascii <= " ";
8'h5A: ascii <= 8'd13; // enter
8'h54: ascii <= "{";
8'h5B: ascii <= "}";
8'h4C: ascii <= ":";
8'h52: ascii <= "\"";
8'h41: ascii <= "<";
8'h49: ascii <= ">";
8'h4A: ascii <= "?";
default:
// unsupported key!
begin
ascii_rdy <= 1'b0; // shift is not a key!
ascii <= " ";
end
endcase
end
end
end
S_KEYF0:
// when we end up here, a 0xF0 byte was received
// which usually means a key release event
begin
if ((rx == 8'h59) || (rx == 8'h12))
shift <= 1'b0;
next_state = S_KEYNORMAL;
end
S_KEYE0:
begin
if (rx == 8'hF0)
next_state = S_KEYE0F0;
else
next_state = S_KEYNORMAL;
end
S_KEYE0F0:
begin
next_state = S_KEYNORMAL;
end
default:
begin
next_state = S_KEYNORMAL;
end
endcase
end
else
begin
next_state = cur_state; // deliberate blocking assingment!
end
cur_state <= next_state;
end
end
endmodule |
module arlet_6502(
input clk, // clock signal
input enable, // clock enable strobe
input rst, // active high reset signal
output reg [15:0] ab, // address bus
input [7:0] dbi, // 8-bit data bus (input)
output reg [7:0] dbo, // 8-bit data bus (output)
output reg we, // active high write enable strobe
input irq_n, // active low interrupt request
input nmi_n, // active low non-maskable interrupt
input ready, // CPU updates when ready = 1
output [15:0] pc_monitor // program counter monitor signal for debugging
);
wire [7:0] dbo_c;
wire [15:0] ab_c;
wire we_c;
cpu arlet_cpu(
.clk(clk),
.reset(rst),
.AB(ab_c),
.DI(dbi),
.DO(dbo_c),
.WE(we_c),
.IRQ(~irq_n),
.NMI(~nmi_n),
.RDY(ready),
.PC_MONITOR(pc_monitor)
);
always @(posedge clk or posedge rst)
begin
if (rst)
begin
ab <= 16'd0;
dbo <= 8'd0;
we <= 1'b0;
end
else
if (enable)
begin
ab <= ab_c;
dbo <= dbo_c;
we <= we_c;
end
end
endmodule |
module aholme_6502(
input clk,
input enable,
input reset,
output [15:0] ab,
input [7:0] dbi,
output [7:0] dbo,
output we,
input irq,
input nmi,
input ready
);
wire we_c;
chip_6502 aholme_cpu (
.clk(clk),
.phi(clk & enable),
.res(~reset),
.so(1'b0),
.rdy(ready),
.nmi(nmi_n),
.irq(irq_n),
.rw(we_c),
.dbi(dbi),
.dbo(dbo),
.ab(ab)
);
assign we = ~we_c;
endmodule |
module vram #(
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin"
) (
input clk, // clock signal
input [10:0] read_addr, // read address bus
input [10:0] write_addr, // write address bus
input r_en, // active high read enable strobe
input w_en, // active high write enable strobe
input [5:0] din, // 6-bit data bus (input)
output reg [5:0] dout // 6-bit data bus (output)
);
reg [5:0] ram_data[0:2047];
initial
$readmemb(VRAM_FILENAME, ram_data, 0, 2047);
always @(posedge clk)
begin
if (r_en) dout <= ram_data[read_addr];
if (w_en) ram_data[write_addr] <= din;
end
endmodule |
module vga #(
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex"
) (
input clk25, // clock signal
input enable, // clock enable strobe,
input rst, // active high reset signal
output vga_h_sync, // horizontal VGA sync pulse
output vga_v_sync, // vertical VGA sync pulse
output vga_red, // red VGA signal
output vga_grn, // green VGA signal
output vga_blu, // blue VGA signal
input address, // address bus
input w_en, // active high write enable strobe
input [7:0] din, // 8-bit data bus (input)
input [1:0] mode, // 2-bit mode setting for pixel doubling
input [2:0] bg_colour, // 3 bit background colour
input [2:0] fg_colour, // 3 bit foreground colour
input clr_screen // clear screen button
);
//////////////////////////////////////////////////////////////////////////
// Registers and Parameters
// video structure constants
parameter h_pixels = 799; // horizontal pixels per line
parameter v_lines = 520; // vertical lines per frame
parameter h_pulse = 96; // hsync pulse length
parameter v_pulse = 2; // vsync pulse length
parameter hbp = 144; // end of horizontal back porch
parameter hfp = 784; // beginning of horizontal front porch
parameter vbp = 31; // end of vertical back porch
parameter vfp = 511; // beginning of vertical front porch
// registers for storing the horizontal & vertical counters
reg [9:0] h_cnt;
reg [9:0] v_cnt;
wire [3:0] h_dot;
reg [4:0] v_dot;
// hardware cursor registers
wire [10:0] cursor;
reg [5:0] h_cursor;
reg [4:0] v_cursor;
// vram indexing registers
reg [5:0] vram_h_addr;
reg [4:0] vram_v_addr;
reg [4:0] vram_start_addr;
reg [4:0] vram_end_addr;
wire [4:0] vram_clr_addr;
// vram registers
wire [10:0] vram_r_addr;
reg [10:0] vram_w_addr;
reg vram_w_en;
reg [5:0] vram_din;
wire [5:0] vram_dout;
// font rom registers
wire [5:0] font_char;
wire [3:0] font_pixel;
wire [4:0] font_line;
wire font_out;
// cpu control registers
reg char_seen;
// active region strobes
wire h_active;
wire v_active;
assign h_active = (h_cnt >= hbp && h_cnt < hfp);
assign v_active = (v_cnt >= vbp && v_cnt < vfp);
//////////////////////////////////////////////////////////////////////////
// VGA Sync Generation
//
always @(posedge clk25 or posedge rst)
begin
if (rst)
begin
h_cnt <= 10'd0;
v_cnt <= 10'd0;
v_dot <= 5'd0;
end
else
begin
if (h_cnt < h_pixels)
h_cnt <= h_cnt + 1;
else
begin
// reset horizontal counters
h_cnt <= 0;
if (v_cnt < v_lines)
begin
v_cnt <= v_cnt + 1;
// count 20 rows, so 480px / 20 = 24 rows
if (v_active)
begin
v_dot <= v_dot + 1;
if (v_dot == 5'd19)
v_dot <= 0;
end
end
else
begin
// reset vertical counters
v_cnt <= 0;
v_dot <= 0;
end
end
end
end
// count 16 pixels, so 640px / 16 = 40 characters
assign h_dot = h_active ? h_cnt[3:0] : 4'd0;
//////////////////////////////////////////////////////////////////////////
// Character ROM
font_rom #(
.FONT_ROM_FILENAME (FONT_ROM_FILENAME)
) my_font_rom(
.clk(clk25),
.mode(mode),
.character(font_char),
.pixel(font_pixel),
.line(font_line),
.out(font_out)
);
//////////////////////////////////////////////////////////////////////////
// Video RAM
vram #(
.VRAM_FILENAME (VRAM_FILENAME)
) my_vram(
.clk(clk25),
.read_addr(vram_r_addr),
.write_addr(vram_w_addr),
.r_en(h_active),
.w_en(vram_w_en),
.din(vram_din),
.dout(vram_dout)
);
//////////////////////////////////////////////////////////////////////////
// Video Signal Generation
always @(posedge clk25 or posedge rst) begin
if (rst) begin
vram_h_addr <= 'd0;
vram_v_addr <= 'd0;
end else begin
// start the pipeline for reading vram and font details
// 3 pixel clock cycles early
if (h_dot == 4'hC)
vram_h_addr <= vram_h_addr + 'd1;
// advance to next row when last display line is reached for row
if (v_dot == 5'd19 && h_cnt == 10'd0)
vram_v_addr <= vram_v_addr + 'd1;
// clear the address registers if we're not in visible area
if (~h_active)
vram_h_addr <= 'd0;
if (~v_active)
vram_v_addr <= vram_start_addr;
end
end
//////////////////////////////////////////////////////////////////////////
// Cursor blink
reg blink;
reg [22:0] blink_div;
always @(posedge clk25 or posedge rst)
begin
if (rst)
blink_div <= 0;
else
begin
blink_div <= blink_div + 1;
if (blink_div == 23'd0)
blink <= ~blink;
end
end
//////////////////////////////////////////////////////////////////////////
// Pipeline and VGA signals
// vram to font rom to display pipeline assignments
assign cursor = {v_cursor, h_cursor};
assign vram_r_addr = {vram_v_addr, vram_h_addr};
assign font_char = (vram_r_addr != cursor) ? vram_dout : (blink) ? 6'd0 : 6'd32;
assign font_pixel = h_dot + 1; // offset by one to get pixel into right cycle,
// font output one pixel clk behind
assign font_line = v_dot;
// vga signals out to monitor
assign vga_red = (h_active & v_active) ? (font_out ? fg_colour[2] : bg_colour[2]) : 1'b0;
assign vga_grn = (h_active & v_active) ? (font_out ? fg_colour[1] : bg_colour[1]) : 1'b0;
assign vga_blu = (h_active & v_active) ? (font_out ? fg_colour[0] : bg_colour[0]) : 1'b0;
assign vga_h_sync = (h_cnt < h_pulse) ? 0 : 1;
assign vga_v_sync = (v_cnt < v_pulse) ? 0 : 1;
//////////////////////////////////////////////////////////////////////////
// CPU control and hardware cursor
assign vram_clr_addr = vram_end_addr + {3'd0, vram_v_addr[1:0]};
always @(posedge clk25 or posedge rst)
begin
if (rst)
begin
h_cursor <= 6'd0;
v_cursor <= 5'd0;
char_seen <= 'b0;
vram_start_addr <= 5'd0;
vram_end_addr <= 5'd24;
end
else
begin
vram_w_en <= 0;
if (clr_screen)
begin
// return to top of screen
h_cursor <= 6'd0;
v_cursor <= 5'd0;
vram_start_addr <= 5'd0;
vram_end_addr <= 5'd24;
// clear the screen
vram_w_addr <= {vram_v_addr, vram_h_addr};
vram_din <= 6'd32;
vram_w_en <= 1;
end
else
begin
// cursor overflow handling
if (h_cursor == 6'd40)
begin
h_cursor <= 6'd0;
v_cursor <= v_cursor + 'd1;
end
if (v_cursor == vram_end_addr)
begin
vram_start_addr <= vram_start_addr + 'd1;
vram_end_addr <= vram_end_addr + 'd1;
end
if (address == 1'b0) // address low == TX register
begin
if (enable & w_en & ~char_seen)
begin
// incoming character
char_seen <= 1;
case(din)
8'h0D,
8'h8D: begin
// handle carriage return
h_cursor <= 0;
v_cursor <= v_cursor + 'd1;
end
8'h00,
8'h0A,
8'h9B,
8'h7F: begin
// ignore the escape key
h_cursor <= 0;
end
default: begin
vram_w_addr <= cursor;
vram_din <= {~din[6], din[4:0]};
vram_w_en <= 1;
h_cursor <= h_cursor + 1;
end
endcase
end
else if(~enable & ~w_en)
char_seen <= 0;
end
else
begin
vram_w_addr <= {vram_clr_addr, vram_h_addr};
vram_din <= 6'd32;
vram_w_en <= 1;
end
end
end
end
endmodule |
module font_rom #(
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex"
) (
input clk, // clock signal
input [1:0] mode, // character mode
input [5:0] character, // address bus
input [3:0] pixel, // address of the pixel to output
input [4:0] line, // address of the line to output
output reg out // single pixel from address and pixel pos
);
reg [7:0] rom[0:1023];
initial
$readmemh(FONT_ROM_FILENAME, rom, 0, 1023);
// double height of pixel by ignoring bit 0
wire [3:0] line_ptr = line[4:1];
// Note: Quartus II reverses the pixels when we do:
//
// rom[address][bitindex]
//
// directly, so we use an intermediate
// signal, romout, to work around this
// problem.
//
// IceCube2 and Yosys don't seem to have this problem.
//
reg [7:0] romout;
always @(posedge clk)
begin
// mode
// 00 - normal
// 01 - vertical scanlines
// 10 - horizontal scanlines
// 11 - dotty mode
romout = rom[(character * 10) + {2'd0, line_ptr}];
out <= (mode[1] & line[0]) ? 1'b0 :
(mode[0] & pixel[0]) ? 1'b0 :
romout[pixel[3:1]];
end
endmodule |
module MUX #(
parameter N=1
) (
output wire o,
input wire i,
input wire [N-1:0] s,
input wire [N-1:0] d);
assign o = (|s) ? &(d|(~s)) : i;
endmodule |
module LOGIC (
input [`NUM_NODES-1:0] i,
output [`NUM_NODES-1:0] o);
`include "../rtl/cpu/aholme/chip_6502_logic.inc"
endmodule |
module chip_6502 (
input clk, // FPGA clock
input phi, // 6502 clock
input res,
input so,
input rdy,
input nmi,
input irq,
input [7:0] dbi,
output [7:0] dbo,
output rw,
output sync,
output [15:0] ab);
// Node states
wire [`NUM_NODES-1:0] no;
reg [`NUM_NODES-1:0] ni;
reg [`NUM_NODES-1:0] q = 0;
LOGIC logic_00 (.i(ni), .o(no));
always @ (posedge clk)
q <= no;
always @* begin
ni = q;
ni[`NODE_vcc ] = 1'b1;
ni[`NODE_vss ] = 1'b0;
ni[`NODE_res ] = res;
ni[`NODE_clk0] = phi;
ni[`NODE_so ] = so;
ni[`NODE_rdy ] = rdy;
ni[`NODE_nmi ] = nmi;
ni[`NODE_irq ] = irq;
{ni[`NODE_db7],ni[`NODE_db6],ni[`NODE_db5],ni[`NODE_db4],
ni[`NODE_db3],ni[`NODE_db2],ni[`NODE_db1],ni[`NODE_db0]} = dbi[7:0];
end
assign dbo[7:0] = {
no[`NODE_db7],no[`NODE_db6],no[`NODE_db5],no[`NODE_db4],
no[`NODE_db3],no[`NODE_db2],no[`NODE_db1],no[`NODE_db0]
};
assign ab[15:0] = {
no[`NODE_ab15], no[`NODE_ab14], no[`NODE_ab13], no[`NODE_ab12],
no[`NODE_ab11], no[`NODE_ab10], no[`NODE_ab9], no[`NODE_ab8],
no[`NODE_ab7], no[`NODE_ab6], no[`NODE_ab5], no[`NODE_ab4],
no[`NODE_ab3], no[`NODE_ab2], no[`NODE_ab1], no[`NODE_ab0]
};
assign rw = no[`NODE_rw];
assign sync = no[`NODE_sync];
endmodule |
module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
input clk;
input right;
input [3:0] op; // operation
input [7:0] AI;
input [7:0] BI;
input CI;
input BCD; // BCD style carry
output [7:0] OUT;
output CO;
output V;
output Z;
output N;
output HC;
input RDY;
reg [7:0] OUT;
reg CO;
wire V;
wire Z;
reg N;
reg HC;
reg AI7;
reg BI7;
reg [8:0] temp_logic;
reg [7:0] temp_BI;
reg [4:0] temp_l;
reg [4:0] temp_h;
wire [8:0] temp = { temp_h, temp_l[3:0] };
wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
// calculate the logic operations. The 'case' can be done in 1 LUT per
// bit. The 'right' shift is a simple mux that can be implemented by
// F5MUX.
always @* begin
case( op[1:0] )
2'b00: temp_logic = AI | BI;
2'b01: temp_logic = AI & BI;
2'b10: temp_logic = AI ^ BI;
2'b11: temp_logic = AI;
endcase
if( right )
temp_logic = { AI[0], CI, AI[7:1] };
end
// Add logic result to BI input. This only makes sense when logic = AI.
// This stage can be done in 1 LUT per bit, using carry chain logic.
always @* begin
case( op[3:2] )
2'b00: temp_BI = BI; // A+B
2'b01: temp_BI = ~BI; // A-B
2'b10: temp_BI = temp_logic; // A+A
2'b11: temp_BI = 0; // A+0
endcase
end
// HC9 is the half carry bit when doing BCD add
wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
// CO9 is the carry-out bit when doing BCD add
wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
// combined half carry bit
wire temp_HC = temp_l[4] | HC9;
// perform the addition as 2 separate nibble, so we get
// access to the half carry flag
always @* begin
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
end
// calculate the flags
always @(posedge clk)
if( RDY ) begin
AI7 <= AI[7];
BI7 <= temp_BI[7];
OUT <= temp[7:0];
CO <= temp[8] | CO9;
N <= temp[7];
HC <= temp_HC;
end
assign V = AI7 ^ BI7 ^ CO ^ N;
assign Z = ~|OUT;
endmodule |
module pll(
input clock_in,
output clock_out,
output locked
);
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0000111), // DIVF = 7
.DIVQ(3'b101), // DIVQ = 5
.FILTER_RANGE(3'b101) // FILTER_RANGE = 5
) uut (
.LOCK(locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clock_in),
.PLLOUTCORE(clock_out)
);
endmodule |
module clock_pll(REFERENCECLK,
PLLOUTCORE,
PLLOUTGLOBAL,
RESET);
input REFERENCECLK;
input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
output PLLOUTCORE;
output PLLOUTGLOBAL;
SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
.PLLOUTCORE(PLLOUTCORE),
.PLLOUTGLOBAL(PLLOUTGLOBAL),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(RESET),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(),
.SDI(),
.SDO(),
.SCLK());
//\\ Fin=16, Fout=25;
defparam clock_pll_inst.DIVR = 4'b0000;
defparam clock_pll_inst.DIVF = 7'b0110001;
defparam clock_pll_inst.DIVQ = 3'b101;
defparam clock_pll_inst.FILTER_RANGE = 3'b001;
defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
endmodule |
module apple1_s3e_starterkit_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input CLK_50MHZ, // the 50 MHz master clock
// UART I/O signals
output UART_TXD, // UART transmit pin on board
input UART_RXD, // UART receive pin on board
input PS2_KBCLK,
input PS2_KBDAT,
input BUTTON, // Button for RESET
input SWITCH, // Switch between PS/2 input and UART
output VGA_R,
output VGA_G,
output VGA_B,
output VGA_HS,
output VGA_VS
);
//////////////////////////////////////////////////////////////////////////
// Registers and Wires
reg clk25;
wire [15:0] pc_monitor;
wire rst_n;
assign rst_n = ~BUTTON;
// generate 25MHz clock from 50MHz master clock
always @(posedge CLK_50MHZ)
begin
clk25 <= ~clk25;
end
//////////////////////////////////////////////////////////////////////////
// Core of system
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) apple1_top(
.clk25(clk25),
.rst_n(rst_n), // we don't have any reset pulse..
.uart_rx(UART_RXD),
.uart_tx(UART_TXD),
//.uart_cts(UART_CTS), // there is no CTS on the board :(
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.ps2_select(SWITCH),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(VGA_R),
.vga_grn(VGA_G),
.vga_blu(VGA_B),
.vga_cls(~rst_n),
.pc_monitor(pc_monitor)
);
endmodule |
module segmentdisplay (
clk,
latch,
hexdigit_in,
display_out
);
input clk,latch;
input [3:0] hexdigit_in;
output reg [0:6] display_out;
always @(posedge clk)
begin
if (latch == 1)
begin
case (hexdigit_in)
4'b0000:
display_out <= 7'b1000000;
4'b0001:
display_out <= 7'b1111001;
4'b0010:
display_out <= 7'b0100100;
4'b0011:
display_out <= 7'b0110000;
4'b0100:
display_out <= 7'b0011001;
4'b0101:
display_out <= 7'b0010010;
4'b0110:
display_out <= 7'b0000010;
4'b0111:
display_out <= 7'b1111000;
4'b1000:
display_out <= 7'b0000000;
4'b1001:
display_out <= 7'b0011000;
4'b1010:
display_out <= 7'b0001000;
4'b1011:
display_out <= 7'b0000011;
4'b1100:
display_out <= 7'b1000110;
4'b1101:
display_out <= 7'b0100001;
4'b1110:
display_out <= 7'b0000110;
4'b1111:
display_out <= 7'b0001110;
endcase
end
end
endmodule |
module apple1_de0_top #(
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input CLOCK_50, // the 50 MHz DE0 master clock
// UART I/O signals
output UART_TXD, // UART transmit pin on DE0 board
input UART_RXD, // UART receive pin on DE0 board
output UART_CTS, // UART clear-to-send pin on DE0 board
output [7:0] LEDG, // monitoring for lower 8 address bits
input [2:0] BUTTON, // BUTTON[0] for reset
output [6:0] HEX0_D,
output [6:0] HEX1_D,
output [6:0] HEX2_D,
output [6:0] HEX3_D,
input PS2_KBCLK,
input PS2_KBDAT,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS
);
//////////////////////////////////////////////////////////////////////////
// Registers and Wires
reg clk25;
wire [15:0] pc_monitor;
// generate 25MHz clock from 50MHz master clock
always @(posedge CLOCK_50)
begin
clk25 <= ~clk25;
end
wire r_bit, g_bit, b_bit;
//////////////////////////////////////////////////////////////////////////
// Core of system
apple1 #(
.BASIC_FILENAME (BASIC_FILENAME),
.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) apple1_top(
.clk25(clk25),
.rst_n(BUTTON[0]), // we don't have any reset pulse..
.uart_rx(UART_RXD),
.uart_tx(UART_TXD),
.uart_cts(UART_CTS),
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.ps2_select(1'b1),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(r_bit),
.vga_grn(g_bit),
.vga_blu(b_bit),
.pc_monitor(pc_monitor)
);
// set the monochrome base colour here..
assign VGA_R[3:0] = {4{r_bit}};
assign VGA_G[3:0] = {4{g_bit}};
assign VGA_B[3:0] = {4{b_bit}};
//////////////////////////////////////////////////////////////////////////
// Display 6502 address on 7-segment displays
segmentdisplay seg1(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[3:0]),
.display_out(HEX0_D)
);
segmentdisplay seg2(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[7:4]),
.display_out(HEX1_D)
);
segmentdisplay seg3(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[11:8]),
.display_out(HEX2_D)
);
segmentdisplay seg4(
.clk(clk25),
.latch(1'b1),
.hexdigit_in(pc_monitor[15:12]),
.display_out(HEX3_D)
);
assign LEDG = 0;
endmodule |
module Max2AudioDac(clk, mute, din, bclk, wclk, lout, rout);
output [23:0] lout;
output [23:0] rout;
input clk;
input din;
input bclk;
input wclk;
input mute;
reg [23:0] leftReg;
reg [23:0] rightReg;
reg [0:23] shift;
reg [1:0] bclkState;
reg [4:0] counter;
reg wsd = 0;
reg wsdEdge = 0;
wire bclkRise = (bclkState == 2'b01);
wire bclkFall = (bclkState == 2'b10);
wire wsp = wsd ^ wsdEdge;
assign lout = leftReg;
assign rout = rightReg;
initial leftReg = 0;
initial rightReg = 0;
always @(posedge clk)
begin
bclkState <= {bclkState, bclk};
end
always @(posedge clk)
begin
if (bclkRise)
begin
wsd <= wclk;
end
end
always @(posedge clk)
begin
if (bclkRise)
begin
wsdEdge <= wsd;
end
end
always @(posedge clk)
begin
if (bclkFall)
begin
if (wsp)
begin
counter <= 0;
end
else if (counter < 24)
begin
counter <= counter + 1;
end
end
end
always @(posedge clk)
begin
if (bclkRise)
begin
if (wsp)
begin
shift <= 0;
end
if (counter < 24)
begin
shift[counter] <= din;
end
end
end
always @(posedge clk)
begin
if (mute)
begin
leftReg <= 0;
end
else
begin
if (bclkRise)
begin
if (wsd && wsp)
begin
leftReg <= {~shift[0], shift[1:23]};
end
end
end
end
always @(posedge clk)
begin
if (mute)
begin
rightReg <= 0;
end
else
begin
if (bclkRise)
begin
if (!wsd && wsp)
begin
rightReg <= {~shift[0], shift[1:23]};
end
end
end
end
endmodule |
module top(
input CLOCK_50,
input [9:0] SW,
///////// PS2 /////////
inout PS2_CLK,
inout PS2_DAT,
///////// VGA /////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N, // not used (?)
output VGA_VS
);
logic vga_clk;
pll pll(
.refclk ( CLOCK_50 ),
.rst ( 1'b0 ),
.outclk_0 ( ),
.outclk_1 ( vga_clk )
);
assign VGA_CLK = vga_clk;
logic main_reset;
logic sw_0_d1;
logic sw_0_d2;
logic sw_0_d3;
always_ff @( posedge CLOCK_50 )
begin
sw_0_d1 <= SW[0];
sw_0_d2 <= sw_0_d1;
sw_0_d3 <= sw_0_d2;
end
assign main_reset = sw_0_d3;
logic [7:0] ps2_received_data_w;
logic ps2_received_data_en_w;
PS2_Controller ps2(
.CLOCK_50 ( CLOCK_50 ),
.reset ( main_reset ),
// Bidirectionals
.PS2_CLK ( PS2_CLK ),
.PS2_DAT ( PS2_DAT ),
.received_data ( ps2_received_data_w ),
.received_data_en ( ps2_received_data_en_w )
);
logic user_event_rd_req_w;
user_event_t user_event_w;
logic user_event_ready_w;
user_input user_input(
.rst_i ( main_reset ),
.ps2_clk_i ( CLOCK_50 ),
.ps2_key_data_i ( ps2_received_data_w ),
.ps2_key_data_en_i ( ps2_received_data_en_w ),
.main_logic_clk_i ( vga_clk ),
.user_event_rd_req_i ( user_event_rd_req_w ),
.user_event_o ( user_event_w ),
.user_event_ready_o ( user_event_ready_w )
);
game_data_t game_data_w;
main_game_logic main_logic(
.clk_i ( vga_clk ),
.rst_i ( main_reset ),
.user_event_i ( user_event_w ),
.user_event_ready_i ( user_event_ready_w ),
.user_event_rd_req_o ( user_event_rd_req_w ),
.game_data_o ( game_data_w )
);
draw_tetris draw_tetris(
.clk_vga_i ( vga_clk ),
.game_data_i ( game_data_w ),
// VGA interface
.vga_hs_o ( VGA_HS ),
.vga_vs_o ( VGA_VS ),
.vga_de_o ( VGA_BLANK_N ),
.vga_r_o ( VGA_R ),
.vga_g_o ( VGA_G ),
.vga_b_o ( VGA_B )
);
endmodule |
module multiplier_tb();
reg clk;
reg rst;
reg [31:0] input_a;
reg [31:0] input_b;
reg input_a_stb;
reg input_b_stb;
reg output_z_ack;
wire input_a_ack;
wire input_b_ack;
wire output_z_stb;
wire [31:0] output_z;
initial begin
clk = 1;
rst = 1;
input_a_stb = 0;
input_b_stb = 0;
output_z_ack = 0;
#10
rst = 0;
////////////////////////////
input_a_stb = 1;
input_b_stb = 1;
output_z_ack = 1;
// #5
input_a = 32'h3f000000;
input_b = 32'h00000000;
#80
// input_a_stb = 0;
// input_b_stb = 0;
// output_z_ack = 0;
// #10
////////////////////////////
// input_a_stb = 1;
// input_b_stb = 1;
// output_z_ack = 1;
// #5
input_a = 32'h3f000000;
input_b = 32'hbf000000;
#80
// input_a_stb = 0;
// input_b_stb = 0;
// output_z_ack = 0;
// ////////////////////////////
// #10
// input_a_stb = 1;
// input_b_stb = 1;
// output_z_ack = 1;
// #5
input_a = 32'h3f000000;
input_b = 32'h3f800000;
end
multiplier DUT (
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
always
#5 clk = ~clk;
endmodule // multiplier_tb |
module Neg #(
parameter WIDTH = 32
) (
input wire logic signed [WIDTH-1:0] in,
output wire logic signed [WIDTH-1:0] out
);
assign out = -in;
endmodule |
module IEEE_SP_FP_ADDER_NOPIPE (
input _go,
input clk,
input reset,
input [31:0] Number1,
input [31:0] Number2,
output [31:0] Result
);
reg [31:0] Num_shift_80;
reg [7:0] Larger_exp_80, Final_expo_80;
reg [22:0] Small_exp_mantissa_80, S_mantissa_80, L_mantissa_80, Large_mantissa_80, Final_mant_80;
reg [23:0] Add_mant_80, Add1_mant_80;
reg [7:0] e1_80, e2_80;
reg [22:0] m1_80, m2_80;
reg s1_80, s2_80, Final_sign_80;
reg [3:0] renorm_shift_80;
integer signed renorm_exp_80;
reg [31:0] Result_80;
assign Result = Result_80;
always @(*) begin
//stage 1
e1_80 = Number1[30:23];
e2_80 = Number2[30:23];
m1_80 = Number1[22:0];
m2_80 = Number2[22:0];
s1_80 = Number1[31];
s2_80 = Number2[31];
if (e1_80 > e2_80) begin
Num_shift_80 = e1_80 - e2_80; // number of mantissa shift
Larger_exp_80 = e1_80; // store lower exponent
Small_exp_mantissa_80 = m2_80;
Large_mantissa_80 = m1_80;
end else begin
Num_shift_80 = e2_80 - e1_80;
Larger_exp_80 = e2_80;
Small_exp_mantissa_80 = m1_80;
Large_mantissa_80 = m2_80;
end
if (e1_80 == 0 | e2_80 == 0) begin
Num_shift_80 = 0;
end else begin
Num_shift_80 = Num_shift_80;
end
//stage 2
//if check both for normalization then append 1 and shift
if (e1_80 != 0) begin
Small_exp_mantissa_80 = {1'b1, Small_exp_mantissa_80[22:1]};
Small_exp_mantissa_80 = (Small_exp_mantissa_80 >> Num_shift_80);
end else begin
Small_exp_mantissa_80 = Small_exp_mantissa_80;
end
if (e2_80 != 0) begin
Large_mantissa_80 = {1'b1, Large_mantissa_80[22:1]};
end else begin
Large_mantissa_80 = Large_mantissa_80;
end
//else do what to do for denorm field
//stage 3
//check if exponent are equal
if (Small_exp_mantissa_80 < Large_mantissa_80) begin
//Small_exp_mantissa_80 = ((~ Small_exp_mantissa_80 ) + 1'b1);
//$display("what small_exp:%b",Small_exp_mantissa_80);
S_mantissa_80 = Small_exp_mantissa_80;
L_mantissa_80 = Large_mantissa_80;
end else begin
//Large_mantissa_80 = ((~ Large_mantissa_80 ) + 1'b1);
//$display("what large_exp:%b",Large_mantissa_80);
S_mantissa_80 = Large_mantissa_80;
L_mantissa_80 = Small_exp_mantissa_80;
end
//stage 4
//add the two mantissa's
if (e1_80 != 0 & e2_80 != 0) begin
if (s1_80 == s2_80) begin
Add_mant_80 = S_mantissa_80 + L_mantissa_80;
end else begin
Add_mant_80 = L_mantissa_80 - S_mantissa_80;
end
end else begin
Add_mant_80 = L_mantissa_80;
end
//renormalization for mantissa and exponent
if (Add_mant_80[23]) begin
renorm_shift_80 = 4'd1;
renorm_exp_80 = 4'd1;
end else if (Add_mant_80[22]) begin
renorm_shift_80 = 4'd2;
renorm_exp_80 = 0;
end else if (Add_mant_80[21]) begin
renorm_shift_80 = 4'd3;
renorm_exp_80 = -1;
end else if (Add_mant_80[20]) begin
renorm_shift_80 = 4'd4;
renorm_exp_80 = -2;
end else if (Add_mant_80[19]) begin
renorm_shift_80 = 4'd5;
renorm_exp_80 = -3;
end else begin
renorm_shift_80 = 0;
renorm_exp_80 = -Larger_exp_80;
end
//stage 5
// if e1==e2, no shift for exp
Final_expo_80 = Larger_exp_80 + renorm_exp_80;
if (renorm_shift_80 != 0) begin
Add1_mant_80 = Add_mant_80 << renorm_shift_80;
end else begin
Add1_mant_80 = Add_mant_80;
end
Final_mant_80 = Add1_mant_80[23:1];
if (s1_80 == s2_80) begin
Final_sign_80 = s1_80;
end else if (e1_80 > e2_80) begin
Final_sign_80 = s1_80;
end else if (e2_80 > e1_80) begin
Final_sign_80 = s2_80;
end else if (m1_80 > m2_80) begin
Final_sign_80 = s1_80;
end else begin
Final_sign_80 = s2_80;
end
Result_80 = {Final_sign_80, Final_expo_80, Final_mant_80};
end
endmodule |
module IEEE_SP_FP_ADDER (
input _go,
input clk,
input reset,
input [31:0] Number1,
input [31:0] Number2,
output [31:0] Result
);
reg [31:0] Num_shift_80, Num_shift_pipe2_80;
reg [7:0]
Larger_exp_80,
Larger_exp_pipe1_80,
Larger_exp_pipe2_80,
Larger_exp_pipe3_80,
Larger_exp_pipe4_80,
Larger_exp_pipe5_80,
Final_expo_80;
reg [22:0]
Small_exp_mantissa_80,
Small_exp_mantissa_pipe2_80,
S_exp_mantissa_pipe2_80,
S_exp_mantissa_pipe3_80,
Small_exp_mantissa_pipe3_80;
reg [22:0] S_mantissa_80, L_mantissa_80;
reg [22:0] L1_mantissa_pipe2_80, L1_mantissa_pipe3_80, Large_mantissa_80, Final_mant_80;
reg [22:0]
Large_mantissa_pipe2_80, Large_mantissa_pipe3_80, S_mantissa_pipe4_80, L_mantissa_pipe4_80;
reg [23:0] Add_mant_80, Add1_mant_80, Add_mant_pipe5_80;
reg [7:0] e1_80, e1_pipe1_80, e1_pipe2_80, e1_pipe3_80, e1_pipe4_80, e1_pipe5_80;
reg [7:0] e2_80, e2_pipe1_80, e2_pipe2_80, e2_pipe3_80, e2_pipe4_80, e2_pipe5_80;
reg [22:0] m1_80, m1_pipe1_80, m1_pipe2_80, m1_pipe3_80, m1_pipe4_80, m1_pipe5_80;
reg [22:0] m2_80, m2_pipe1_80, m2_pipe2_80, m2_pipe3_80, m2_pipe4_80, m2_pipe5_80;
reg s1_80, s2_80, Final_sign_80, s1_pipe1_80, s1_pipe2_80, s1_pipe3_80, s1_pipe4_80, s1_pipe5_80;
reg s2_pipe1_80, s2_pipe2_80, s2_pipe3_80, s2_pipe4_80, s2_pipe5_80;
reg [3:0] renorm_shift_80, renorm_shift_pipe5_80;
integer signed renorm_exp_80, renorm_exp_pipe5_80;
//reg [3:0] renorm_exp_80,renorm_exp_pipe5_80;
reg [31:0] Result_80;
assign Result = Result_80;
always @(*) begin
///////////////////////// Combinational stage1 ///////////////////////////
e1_80 = Number1[30:23];
e2_80 = Number2[30:23];
m1_80 = Number1[22:0];
m2_80 = Number2[22:0];
s1_80 = Number1[31];
s2_80 = Number2[31];
if (e1_80 > e2_80) begin
Num_shift_80 = e1_80 - e2_80; // determine number of mantissa shift
Larger_exp_80 = e1_80; // store higher exponent
Small_exp_mantissa_80 = m2_80;
Large_mantissa_80 = m1_80;
end else begin
Num_shift_80 = e2_80 - e1_80;
Larger_exp_80 = e2_80;
Small_exp_mantissa_80 = m1_80;
Large_mantissa_80 = m2_80;
end
if (e1_80 == 0 | e2_80 == 0) begin
Num_shift_80 = 0;
end else begin
Num_shift_80 = Num_shift_80;
end
//////// Combinational stage2 /////////
//right shift mantissa of smaller exponent
if (e1_pipe2_80 != 0) begin
S_exp_mantissa_pipe2_80 = {1'b1, Small_exp_mantissa_pipe2_80[22:1]};
S_exp_mantissa_pipe2_80 = (S_exp_mantissa_pipe2_80 >> Num_shift_pipe2_80);
end else begin
S_exp_mantissa_pipe2_80 = Small_exp_mantissa_pipe2_80;
end
// BUG: Uses value from previous stage.
// CONFIRMED: Differs from no_pipe version
// if (e2_80 != 0) begin
if (e2_pipe2_80 != 0) begin
L1_mantissa_pipe2_80 = {1'b1, Large_mantissa_pipe2_80[22:1]};
end else begin
L1_mantissa_pipe2_80 = Large_mantissa_pipe2_80;
end
////////// Combinational stage3 //////
//compare which is smaller mantissa
if (S_exp_mantissa_pipe3_80 < L1_mantissa_pipe3_80) begin
S_mantissa_80 = S_exp_mantissa_pipe3_80;
L_mantissa_80 = L1_mantissa_pipe3_80;
end else begin
S_mantissa_80 = L1_mantissa_pipe3_80;
L_mantissa_80 = S_exp_mantissa_pipe3_80;
end
//////// Combinational stage4 ////////
//add the two mantissa's
if (e1_pipe4_80 != 0 & e2_pipe4_80 != 0) begin
if (s1_pipe4_80 == s2_pipe4_80) begin
Add_mant_80 = S_mantissa_pipe4_80 + L_mantissa_pipe4_80;
end else begin
Add_mant_80 = L_mantissa_pipe4_80 - S_mantissa_pipe4_80;
end
end else begin
Add_mant_80 = L_mantissa_pipe4_80;
end
//determine shifts for renormalization for mantissa and exponent
if (Add_mant_80[23]) begin
renorm_shift_80 = 4'd1;
renorm_exp_80 = 4'd1;
end else if (Add_mant_80[22]) begin
renorm_shift_80 = 4'd2;
renorm_exp_80 = 0;
end else if (Add_mant_80[21]) begin
renorm_shift_80 = 4'd3;
renorm_exp_80 = -1;
end else if (Add_mant_80[20]) begin
renorm_shift_80 = 4'd4;
renorm_exp_80 = -2;
end else if (Add_mant_80[19]) begin
renorm_shift_80 = 4'd5;
renorm_exp_80 = -3;
end else begin
renorm_shift_80 = 0;
// BUG: if the first 1 bit is after the 5th bit, normalization isn't performed.
// BUG: if there are no zeros in the mantissa, the exponent should be set to zero.
// CONFIRMED: left=3212836864, right=1065353216
renorm_exp_80 = -Larger_exp_pipe4_80;
end
////// Combinational stage5 //////
//Shift the mantissa as required; re-normalize exp; determine sign
// BUG: uses value from the previous stage.
// CONFIRMED: left=1197990852, right=1203616721
// Final_expo_80 = Larger_exp_pipe5_80 + renorm_exp_80;
Final_expo_80 = Larger_exp_pipe5_80 + renorm_exp_pipe5_80;
if (renorm_shift_pipe5_80 != 0) begin
Add1_mant_80 = Add_mant_pipe5_80 << renorm_shift_pipe5_80;
end else begin
Add1_mant_80 = Add_mant_pipe5_80;
end
Final_mant_80 = Add1_mant_80[23:1];
if (s1_pipe5_80 == s2_pipe5_80) begin
Final_sign_80 = s1_pipe5_80;
end else if (e1_pipe5_80 > e2_pipe5_80) begin
Final_sign_80 = s1_pipe5_80;
// BUG: uses value from the first pipeline stage.
// CONFIRMED: left=3348281187, right=1203616721
// end else if (e2_80 > e1_80) begin
end else if (e2_pipe5_80 > e1_pipe5_80) begin
Final_sign_80 = s2_pipe5_80;
end else if (m1_pipe5_80 > m2_pipe5_80) begin
Final_sign_80 = s1_pipe5_80;
end else begin
Final_sign_80 = s2_pipe5_80;
end
Result_80 = {Final_sign_80, Final_expo_80, Final_mant_80};
end
always @(posedge clk) begin
if (reset) begin //reset all reg at reset signal
s1_pipe2_80 <= 0;
s2_pipe2_80 <= 0;
e1_pipe2_80 <= 0;
e2_pipe2_80 <= 0;
m1_pipe2_80 <= 0;
m2_pipe2_80 <= 0;
Larger_exp_pipe2_80 <= 0;
//stage2
Small_exp_mantissa_pipe2_80 <= 0;
Large_mantissa_pipe2_80 <= 0;
Num_shift_pipe2_80 <= 0;
s1_pipe3_80 <= 0;
s2_pipe3_80 <= 0;
e1_pipe3_80 <= 0;
e2_pipe3_80 <= 0;
m1_pipe3_80 <= 0;
m2_pipe3_80 <= 0;
Larger_exp_pipe3_80 <= 0;
s1_pipe4_80 <= 0;
s2_pipe4_80 <= 0;
e1_pipe4_80 <= 0;
e2_pipe4_80 <= 0;
m1_pipe4_80 <= 0;
m2_pipe4_80 <= 0;
Larger_exp_pipe4_80 <= 0;
s1_pipe5_80 <= 0;
s2_pipe5_80 <= 0;
e1_pipe5_80 <= 0;
e2_pipe5_80 <= 0;
m1_pipe5_80 <= 0;
m2_pipe5_80 <= 0;
Larger_exp_pipe5_80 <= 0;
//stage3
S_exp_mantissa_pipe3_80 <= 0;
L1_mantissa_pipe3_80 <= 0;
//stage4
S_mantissa_pipe4_80 <= 0;
L_mantissa_pipe4_80 <= 0;
//stage5
Add_mant_pipe5_80 <= 0;
renorm_shift_pipe5_80 <= 0;
end else begin
///////////////////////////////PIPELINE STAGES and VARIABLES/////////////////
//propogate pipelined variables to next stages
s1_pipe2_80 <= s1_80;
s2_pipe2_80 <= s2_80;
e1_pipe2_80 <= e1_80;
e2_pipe2_80 <= e2_80;
m1_pipe2_80 <= m1_80;
m2_pipe2_80 <= m2_80;
Larger_exp_pipe2_80 <= Larger_exp_80;
//stage2
Small_exp_mantissa_pipe2_80 <= Small_exp_mantissa_80;
Large_mantissa_pipe2_80 <= Large_mantissa_80;
Num_shift_pipe2_80 <= Num_shift_80;
s1_pipe3_80 <= s1_pipe2_80;
s2_pipe3_80 <= s2_pipe2_80;
e1_pipe3_80 <= e1_pipe2_80;
e2_pipe3_80 <= e2_pipe2_80;
m1_pipe3_80 <= m1_pipe2_80;
m2_pipe3_80 <= m2_pipe2_80;
Larger_exp_pipe3_80 <= Larger_exp_pipe2_80;
s1_pipe4_80 <= s1_pipe3_80;
s2_pipe4_80 <= s2_pipe3_80;
e1_pipe4_80 <= e1_pipe3_80;
e2_pipe4_80 <= e2_pipe3_80;
m1_pipe4_80 <= m1_pipe3_80;
m2_pipe4_80 <= m2_pipe3_80;
Larger_exp_pipe4_80 <= Larger_exp_pipe3_80;
s1_pipe5_80 <= s1_pipe4_80;
s2_pipe5_80 <= s2_pipe4_80;
e1_pipe5_80 <= e1_pipe4_80;
e2_pipe5_80 <= e2_pipe4_80;
m1_pipe5_80 <= m1_pipe4_80;
m2_pipe5_80 <= m2_pipe4_80;
Larger_exp_pipe5_80 <= Larger_exp_pipe4_80;
//stage3
S_exp_mantissa_pipe3_80 <= S_exp_mantissa_pipe2_80;
L1_mantissa_pipe3_80 <= L1_mantissa_pipe2_80;
//stage4
S_mantissa_pipe4_80 <= S_mantissa_80;
L_mantissa_pipe4_80 <= L_mantissa_80;
//stage5
Add_mant_pipe5_80 <= Add_mant_80;
renorm_shift_pipe5_80 <= renorm_shift_80;
renorm_exp_pipe5_80 <= renorm_exp_80;
end
end
endmodule |
module FP_Mult_NoPipe (
input [31:0] a,
input [31:0] b,
output exception,
output overflow,
output underflow,
output [31:0] res
);
wire sign, round, normalised, zero;
wire [8:0] exponent, sum_exponent, exp_norm;
wire [22:0] product_mantissa;
wire [23:0] op_a, op_b;
wire [47:0] product, product_normalised;
assign sign = a[31] ^ b[31]; // XOR of 32nd bit
assign exception = (&a[30:23]) | (&b[30:23]); // Execption sets to 1 when exponent of any a or b is 255
// If exponent is 0, hidden bit is 0
assign op_a = (|a[30:23]) ? {1'b1, a[22:0]} : {1'b0, a[22:0]};
assign op_b = (|b[30:23]) ? {1'b1, b[22:0]} : {1'b0, b[22:0]};
assign product = op_a * op_b; // Product
assign normalised = product[47] ? 1'b1 : 1'b0;
assign product_normalised = normalised ? product : product << 1; // Normalized value based on 48th bit
assign round = |product_normalised[22:0]; // Last 22 bits are ORed for rounding off purpose
assign product_mantissa = product_normalised[46:24] + (product_normalised[23] & round); // Mantissa
assign sum_exponent = a[30:23] + b[30:23];
assign exp_norm = sum_exponent - 8'd127;
assign exponent = exp_norm + normalised;
assign overflow = (exponent[8] & !exception & !exponent[7]) ; // Overall exponent is greater than 255 then Overflow
assign underflow = (exponent[8] & !exception & exponent[7]) ; // Sum of exponents is less than 255 then Underflow
assign res = exception ? {sign,31'd0} :
overflow ? {sign,8'hFF,23'd0} :
underflow ? {sign,31'd0} :
{sign,exponent[7:0],product_mantissa};
endmodule |
module aib_osc_clk (
output logic osc_clk
);
initial osc_clk = 1'b0;
always #(500) osc_clk = ~osc_clk;
endmodule // aib_osc_clk |
module dll
(
input clkp, clkn,
input rstb,
output wire rx_clk_tree_in,
input ms_rx_dll_lock_req,
output wire ms_rx_dll_lock,
input sl_rx_dll_lock_req,
output wire sl_rx_dll_lock,
input ms_nsl,
input atpg_mode
);
wire rstb_sync;
reg ms_rx_dll_lock_r, sl_rx_dll_lock_r;
wire ms_rx_dll_lock_w, sl_rx_dll_lock_w;
wire ms_rx_dll_lock_req_sync, sl_rx_dll_lock_req_sync;
assign ms_rx_dll_lock = ms_rx_dll_lock_r;
assign sl_rx_dll_lock = sl_rx_dll_lock_r;
assign ms_rx_dll_lock_w = !ms_rx_dll_lock_req_sync ? 1'b0 :
(ms_nsl & ms_rx_dll_lock_req_sync ) ? 1'b1 : ms_rx_dll_lock_r;
assign sl_rx_dll_lock_w = !sl_rx_dll_lock_req_sync ? 1'b0 :
(!ms_nsl & sl_rx_dll_lock_req_sync ) ? 1'b1 : sl_rx_dll_lock_r;
aib_rstnsync aib_rstnsync
(
.clk(clkp), // Destination clock of reset to be synced
.i_rst_n(rstb), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(rstb_sync) // Synchronized reset output
);
aib_bitsync i_msrxdlllockreq
(
.clk(clkp),
.rst_n(rstb_sync),
.data_in(ms_rx_dll_lock_req),
.data_out(ms_rx_dll_lock_req_sync)
);
aib_bitsync i_slrxdlllockreq
(
.clk(clkp),
.rst_n(rstb_sync),
.data_in(sl_rx_dll_lock_req),
.data_out(sl_rx_dll_lock_req_sync)
);
always @(posedge clkp or negedge rstb_sync) begin
if (~rstb_sync)
begin
ms_rx_dll_lock_r <= 1'b0;
sl_rx_dll_lock_r <= 1'b0;
end
else
begin
ms_rx_dll_lock_r <= ms_rx_dll_lock_w;
sl_rx_dll_lock_r <= sl_rx_dll_lock_w;
end
end
assign #(100) rx_clk_tree_in = clkp;
endmodule // dll |
Subsets and Splits