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module aib_io_buffer
(
// Tx Path
input ilaunch_clk, // Clock for transmit SDR/DDR data
input irstb, // io buffer reset
input idat0, // sync data from MAC to iopad
input idat1, // sync data from MAC to iopad
input async_data, // Async data from MAC to iopad
output wire oclkn, // clock output
// Rx Path
input inclk, // Rx clock input
input inclk_dist, // Rx clock input
input iclkn, // clock input
output wire oclk, // clock output
output wire oclk_b, // clock output
output wire odat0, // Data to MAC
output wire odat1, // Data to MAC
output wire odat_async, // Async data out
// Bidirectional Data
inout wire io_pad,
// I/O configuration
input async, // 0 = Sample input data with ilaunch_clk
// 1 = Async path from async_data to iopad
input ddren, // 0 = SDR data idat0 delayed 1.0 ilaunch_clk
// 1 = DDR data idat0 delayed 1.5 ilaunch_clk
// idat1 delayed 2.0 ilaunch_clk
input txen, // 0 = output path disabled
// 1 = output path enabled
input rxen, // 0 = input path disabled
// 1 = input path enabled
input weaken, // 0 = No weak driver on iopad
// 1 = Enable weak driver on iopad
input weakdir // 0 = Pull-down enable when weaken = 1
// 1 = Pull-up enable when weaken = 1
);
reg idat0_preg; // idat0 sampled with pos edge of ilaunch_clk
reg idat1_preg; // idat1 sampled with pos edge of ilaunch_clk
reg idat_nreg; // Selected data sampled with neg edge of ilaunch_clk
wire idatsync_sel; // Synchronized inputdata
wire idat_iopad; // Data value driven to output iopad
reg iopad_preg; // iopad sampled with positive edge of clock
reg iopad_nreg; // iopad sampled with negative edge of clock
reg odat0_i; // latch Rx data
reg odat1_i; // latch Rx data
reg odat0_r; // Rx data to MAC
reg odat1_r; // Rx data to MAC
// Output tri-state buffr
assign io_pad = (~irstb && txen) ? 1'b0 :
(irstb && txen) ? idat_iopad : 1'bz;
// pull-up
bufif1 (weak1, weak0) (io_pad, 1'b1, weaken && (weakdir == 1'b1));
// pull-down
bufif1 (weak1, weak0) (io_pad, 1'b0, weaken && (weakdir == 1'b0));
//---------------------------------------------------------------------------
// Receive Data
//---------------------------------------------------------------------------
// Rx data sampled on positive edge of clock
always @(posedge inclk)
if (rxen)
begin
iopad_preg <= io_pad;
end
// Latch when clock is low
always @(irstb or inclk or rxen or iopad_preg)
if (~irstb)
begin
odat1_i = 1'b0;
end
else if (~inclk && rxen)
begin
odat1_i = iopad_preg;
end
// Rx data sampled on negative edge of clock
always @(negedge inclk)
if (rxen)
begin
iopad_nreg <= io_pad;
end
// Latch when clock is high
always @(irstb or inclk or rxen or iopad_nreg)
if (~irstb)
begin
odat0_i = 1'b0;
end
else if (inclk && rxen)
begin
odat0_i = iopad_nreg;
end
wire odat0_i_tmp;
assign #1 odat0_i_tmp = odat0_i;
// Data to MAC
always @(posedge inclk_dist)
if(rxen)
begin
// odat0_r <= odat0_i;
odat0_r <= odat0_i_tmp;
odat1_r <= odat1_i;
end
//assign odat0 = odat0_r && rxen && irstb;
assign odat0 = ddren ? odat0_r && rxen && irstb : iopad_nreg && rxen && irstb;
assign odat1 = odat1_r && rxen && irstb;
// Asynchronous Rx data outputs
assign odat_async = io_pad && rxen;
//---------------------------------------------------------------------------
// Transmit Data
//---------------------------------------------------------------------------
// Tx data sampled on positive edge of clock
always @(posedge ilaunch_clk)
if(txen)
begin
idat0_preg <= idat0;
idat1_preg <= idat1;
end
// Latch when clock is low
always @(ilaunch_clk or txen or ddren or idat1_preg or idat0_preg)
if(!ilaunch_clk && txen)
begin
idat_nreg = ddren ? idat1_preg : idat0_preg;
end
// SDR/DDR mux
//assign idatsync_sel = ((ilaunch_clk == 1'b0) ? idat0_preg : idat_nreg) && txen;
assign idatsync_sel = (((ilaunch_clk == 1'b1) & !ddren) ? idat0_preg :
((ilaunch_clk == 1'b0) & ddren) ? idat0_preg : idat_nreg) && txen;
// Async/Sync mux
assign idat_iopad = async ? async_data && txen : idatsync_sel;
//---------------------------------------------------------------------------
// Differential Clock
//---------------------------------------------------------------------------
assign oclkn = io_pad;
assign oclk = io_pad;
assign oclk_b = iclkn;
endmodule // aib_io_buffer |
module c3lib_or2_lcell(
// Functional IOs
input logic in0,
input logic in1,
output logic out
);
c3lib_or2_svt_2x u_c3lib_or2_svt_2x(
.in0 ( in0 ),
.in1 ( in1 ),
.out ( out )
);
endmodule |
module c3lib_and2_lcell(
// Functional IOs
input logic in0,
input logic in1,
output logic out
);
c3lib_and2_svt_4x u_c3lib_and2_svt_4x(
.in0 ( in0 ),
.in1 ( in1 ),
.out ( out )
);
endmodule |
module c3lib_tiel_lcell(
output logic out
);
c3lib_tie0_svt_1x c3lib_tie0_svt_1x(
.out ( out )
);
endmodule |
module c3lib_tieh_lcell(
output logic out
);
c3lib_tie1_svt_1x c3lib_tie1_svt_1x(
.out ( out )
);
endmodule |
module c3lib_mtiel_lcell(
output logic out
);
c3lib_mtie0_ds u_c3lib_mtie0_ds(
.out ( out )
);
endmodule |
module c3lib_nand2_lcell(
// Functional IOs
input logic in0,
input logic in1,
output logic out
);
c3lib_nand2_svt_2x u_c3lib_nand2_svt_2x(
.in0 ( in0 ),
.in1 ( in1 ),
.out ( out )
);
endmodule |
module c3lib_buf_lcell(
input logic in,
output logic out
);
c3lib_buf_svt_4x u_c3lib_buf_svt_4x(
.in ( in ),
.out ( out )
);
endmodule |
module c3lib_dff_scan_lcell(
clk,
rst_n,
data_in,
data_out,
scan_in,
scan_en
);
input clk;
input rst_n;
input data_in;
output data_out;
input scan_in;
input scan_en;
c3lib_dff0_scan_reset_svt_2x u_c3lib_dff0_scan_reset_svt_2x(
.data_in ( data_in ),
.clk ( clk ),
.data_out ( data_out ),
.rst_n ( rst_n ),
.scan_en ( scan_en ),
.scan_in ( scan_in )
);
endmodule |
module c3lib_mtieh_lcell(
output logic out
);
c3lib_mtie1_ds u_c3lib_mtie1_ds(
.out ( out )
);
endmodule |
module c3lib_mux2_lcell(
input logic in0,
input logic in1,
input logic sel,
output logic out
);
c3lib_mux2_svt_2x u_c3lib_mux2_svt_2x(
.in0 ( in0 ),
.in1 ( in1 ),
.sel ( sel ),
.out ( out )
);
endmodule |
module c3lib_sync3_reset_ulvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
c3lib_sync_metastable_behav_gate #(
.RESET_VAL ( 0 ),
.SYNC_STAGES( 3 )
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_n ( rst_n ),
.data_in ( data_in ),
.data_out ( data_out )
);
`endif
endmodule |
module c3lib_sync2_set_lvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
c3lib_sync_metastable_behav_gate #(
.RESET_VAL ( 1 ),
.SYNC_STAGES( 2 )
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_n ( rst_n ),
.data_in ( data_in ),
.data_out ( data_out )
);
`endif
endmodule |
module c3lib_ckinv_lvt_12x(
in,
out
);
input in;
output out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
assign out = ~in;
`endif
endmodule |
module c3lib_or2_svt_2x(
in0,
in1,
out
);
input in0;
input in1;
output out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
assign out = in0 | in1;
`endif
endmodule |
module c3lib_buf_svt_4x(
in,
out
);
input in;
output out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
assign out = in;
`endif
endmodule |
module c3lib_and2_svt_4x(
in0,
in1,
out
);
input in0;
input in1;
output out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
assign out = in0 & in1;
`endif
endmodule |
module c3lib_sync2_reset_lvt_gate(
clk,
rst_n,
data_in,
data_out
);
input clk;
input rst_n;
input data_in;
output data_out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
c3lib_sync_metastable_behav_gate #(
.RESET_VAL ( 0 ),
.SYNC_STAGES( 2 )
) u_c3lib_sync2_reset_lvt_gate (
.clk ( clk ),
.rst_n ( rst_n ),
.data_in ( data_in ),
.data_out ( data_out )
);
`endif
endmodule |
module c3lib_mtie1_ds(
out
);
output out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
assign out = 1'b1;
`endif
endmodule |
module c3lib_tie0_svt_1x(
out
);
output out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
assign out = 1'b0;
`endif
endmodule |
module c3lib_mtie0_ds(
out
);
output out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
assign out = 1'b0;
`endif
endmodule |
module c3lib_ckbuf_lvt_4x(
in,
out
);
input in;
output out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
assign out = in;
`endif
endmodule |
module c3lib_nand2_svt_2x(
in0,
in1,
out
);
input in0;
input in1;
output out;
`ifdef USER_MACROS_ON
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
`else
assign out = ~(in0 & in1);
`endif
endmodule |
module c3lib_lvlsync #(
parameter EN_PULSE_MODE = 0, // Enable Pulse mode i.e O/P data pulses for change in I/P
parameter DWIDTH = 1, // Sync Data input
parameter ACTIVE_LEVEL = 1, // 1: Active high; 0: Active low
parameter DST_CLK_FREQ_MHZ= 500, // Clock frequency for destination domain in MHz
parameter SRC_CLK_FREQ_MHZ= 500 // Clock frequency for source domain in MHz
) (
// Inputs
input wire wr_clk, // write clock
input wire rd_clk, // read clock
input wire wr_rst_n, // async reset for write clock domain
input wire rd_rst_n, // async reset for read clock domain
input wire [DWIDTH-1:0] data_in, // data in
// Outputs
output reg [DWIDTH-1:0] data_out // data out
);
localparam DATA_RATE = ( DST_CLK_FREQ_MHZ * SRC_CLK_FREQ_MHZ ) / ( 2*DST_CLK_FREQ_MHZ + 2*SRC_CLK_FREQ_MHZ );
//******************************************************************************
// Define regs
//******************************************************************************
reg [DWIDTH-1:0] data_in_d0;
reg [DWIDTH-1:0] req_wr_clk;
wire [DWIDTH-1:0] req_rd_clk;
wire [DWIDTH-1:0] ack_wr_clk;
wire [DWIDTH-1:0] ack_rd_clk;
reg [DWIDTH-1:0] req_rd_clk_d0;
//******************************************************************************
// Generate for multi bits
//******************************************************************************
genvar i;
generate
for (i=0; i < DWIDTH; i=i+1) begin : LVLSYNC
//******************************************************************************
// WRITE CLOCK DOMAIN: Generate req & Store data when synchroniztion is not
// already in progress
//******************************************************************************
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
if (ACTIVE_LEVEL == 1)
begin
data_in_d0[i] <= 1'b0;
end
else // ACTIVE_LEVEL==0
begin
data_in_d0[i] <= 1'b1;
end
req_wr_clk[i] <= 1'b0;
end
else begin
// Store data when Write Req equals Write Ack
if (req_wr_clk[i] == ack_wr_clk[i]) begin
data_in_d0[i] <= data_in[i];
end
// Generate a Req when there is change in data
if (EN_PULSE_MODE == 0) begin
if ((req_wr_clk[i] == ack_wr_clk[i]) & (data_in_d0[i] != data_in[i])) begin
req_wr_clk[i] <= ~req_wr_clk[i];
end
end
else begin
if (ACTIVE_LEVEL == 1) begin
if ((req_wr_clk[i] == ack_wr_clk[i]) & (data_in_d0[i] != data_in[i]) & data_in[i] == 1'b1) begin
req_wr_clk[i] <= ~req_wr_clk[i];
end
end
else begin
if ((req_wr_clk[i] == ack_wr_clk[i]) & (data_in_d0[i] != data_in[i]) & data_in[i] == 1'b0) begin
req_wr_clk[i] <= ~req_wr_clk[i];
end
end
end
end
end
//******************************************************************************
// WRITE CLOCK DOMAIN:
//******************************************************************************
c3lib_bitsync #(
.DWIDTH ( 1 ),
.RESET_VAL ( 0 ),
.DST_CLK_FREQ_MHZ ( SRC_CLK_FREQ_MHZ ),
.SRC_DATA_FREQ_MHZ ( DATA_RATE )
) bitsync_u_ack_wr_clk (
.clk (wr_clk),
.rst_n (wr_rst_n),
.data_in (ack_rd_clk[i]),
.data_out (ack_wr_clk[i])
);
//******************************************************************************
// READ CLOCK DOMAIN:
//******************************************************************************
c3lib_bitsync #(
.DWIDTH ( 1 ),
.RESET_VAL ( 0 ),
.DST_CLK_FREQ_MHZ ( DST_CLK_FREQ_MHZ ),
.SRC_DATA_FREQ_MHZ ( DATA_RATE )
) bitsync_u_req_rd_clk (
.clk (rd_clk),
.rst_n (rd_rst_n),
.data_in (req_wr_clk[i]),
.data_out (req_rd_clk[i])
);
//******************************************************************************
// READ CLOCK DOMAIN:
//******************************************************************************
assign ack_rd_clk[i] = req_rd_clk_d0[i];
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
if (ACTIVE_LEVEL == 1)
begin
data_out[i] <= 1'b0;
end
else
begin
data_out[i] <= 1'b1;
end
req_rd_clk_d0[i] <= 1'b0;
end
else begin
req_rd_clk_d0[i] <= req_rd_clk[i];
if (EN_PULSE_MODE == 0) begin
if (req_rd_clk_d0[i] != req_rd_clk[i]) begin
data_out[i] <= ~data_out[i];
end
end
else if (EN_PULSE_MODE == 1) begin
if (req_rd_clk_d0[i] != req_rd_clk[i]) begin
if (ACTIVE_LEVEL == 1)
begin
data_out[i] <= 1'b1;
end
else // ACTIVE_LEVEL==0
begin
data_out[i] <= 1'b0;
end
end
else begin // EN_PULSE_MODE==0
if (ACTIVE_LEVEL == 1)
begin
data_out[i] <= 1'b0;
end
else // ACTIVE_LEVEL==0
begin
data_out[i] <= 1'b1;
end
end
end
end
end
end
endgenerate
endmodule // cdclib_lvlsync |
module c3lib_bintogray #(
parameter WIDTH = 2 // Data width
) (
// Inputs
input wire [WIDTH-1:0] data_in,
// Outputs
output wire [WIDTH-1:0] data_out
);
assign data_out = (data_in>>1) ^ data_in;
endmodule |
module c3lib_graytobin #(
parameter WIDTH = 2 // Data width
) (
// Inputs
input wire [WIDTH-1:0] data_in,
// Outputs
output wire [WIDTH-1:0] data_out
);
genvar i;
generate
for (i = 0; i <= WIDTH-1; i = i+1) begin: GRAY_TO_BIN
assign data_out[i] = ^(data_in >> i);
end
endgenerate
endmodule |
module c3lib_sync2_lvt_bitsync #(
parameter DWIDTH = 1, // Width of bus to be sync'ed
parameter RESET_VAL = 0 // Reset value is LOW if set to 0, otherwise HIGH
) (
input logic clk,
input logic rst_n,
input logic[ (DWIDTH-1) : 0 ] data_in,
output logic[ (DWIDTH-1) : 0 ] data_out
);
generate
if (RESET_VAL == 0)
c3lib_sync2_reset_lvt_gate u_c3lib_sync2_reset_lvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n ), .data_in( data_in ), .data_out( data_out ) );
else
c3lib_sync2_set_lvt_gate u_c3lib_sync2_set_lvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n ), .data_in( data_in ), .data_out( data_out ) );
endgenerate
endmodule |
module c3lib_sync2_ulvt_bitsync #(
parameter DWIDTH = 1, // Width of bus to be sync'ed
parameter RESET_VAL = 0 // Reset value is LOW if set to 0, otherwise HIGH
) (
input logic clk,
input logic rst_n,
input logic[ (DWIDTH-1) : 0 ] data_in,
output logic[ (DWIDTH-1) : 0 ] data_out
);
generate
if (RESET_VAL == 0)
c3lib_sync2_reset_ulvt_gate u_c3lib_sync2_reset_ulvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n ), .data_in( data_in ), .data_out( data_out ) );
else
c3lib_sync2_set_ulvt_gate u_c3lib_sync2_set_ulvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n ), .data_in( data_in ), .data_out( data_out ) );
endgenerate
endmodule |
module c3lib_bitsync #(
parameter DWIDTH = 1, // Width of bus to be sync'ed
parameter RESET_VAL = 0, // Reset value is LOW if set to 0, otherwise HIGH
parameter DST_CLK_FREQ_MHZ = 500, // Clock frequency for destination domain in MHz
parameter SRC_DATA_FREQ_MHZ = 100 // Average source data 'frequency' in MHz
) (
input logic clk,
input logic rst_n,
input logic[ (DWIDTH-1) : 0 ] data_in,
output logic[ (DWIDTH-1) : 0 ] data_out
);
generate
if (DST_CLK_FREQ_MHZ > 500) begin : DST_CLK_GREATER_THAN_500MHZ
if (RESET_VAL == 0) begin : ULVT_RESET
c3lib_sync2_reset_ulvt_gate u_c3lib_sync2_reset_ulvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n), .data_in( data_in), .data_out( data_out ) );
end
else begin : ULVT_SET
c3lib_sync2_set_ulvt_gate u_c3lib_sync2_set_ulvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n ), .data_in( data_in), .data_out( data_out ) );
end
end
else begin : DST_CLK_LESS_THAN_OR_EQUAL_TO_500MHZ
if (RESET_VAL == 0) begin : LVT_RESET
c3lib_sync2_reset_lvt_gate u_c3lib_sync2_reset_lvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n ), .data_in( data_in ), .data_out( data_out ) );
end
else begin : LVT_SET
c3lib_sync2_set_lvt_gate u_c3lib_sync2_set_lvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n ), .data_in( data_in ), .data_out( data_out ) );
end
end
endgenerate
endmodule |
module c3lib_sync3_ulvt_bitsync #(
parameter DWIDTH = 1, // Width of bus to be sync'ed
parameter RESET_VAL = 0 // Reset value is LOW if set to 0, otherwise HIGH
) (
input logic clk,
input logic rst_n,
input logic[ (DWIDTH-1) : 0 ] data_in,
output logic[ (DWIDTH-1) : 0 ] data_out
);
generate
if (RESET_VAL == 0)
c3lib_sync3_reset_ulvt_gate u_c3lib_sync3_reset_ulvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n ), .data_in( data_in ), .data_out( data_out ) );
else
c3lib_sync3_set_ulvt_gate u_c3lib_sync3_set_ulvt_gate[ (DWIDTH-1) : 0 ] ( .clk( clk ), .rst_n( rst_n ), .data_in( data_in ), .data_out( data_out ) );
endgenerate
endmodule |
module c3lib_async_fifo #(
parameter DWIDTH = 8, // FIFO Input data width
parameter AWIDTH = 4, // FIFO Depth (address width)
parameter DST_CLK_FREQ_MHZ = 500, // Clock frequency for destination domain in MHz
parameter SRC_CLK_FREQ_MHZ = 500 // Clock frequency for source domain in MHz
) (
input wire wr_rst_n, // Write Domain Active low Reset
input wire wr_clk, // Write Domain Clock
input wire wr_en, // Write Data Enable
input wire [DWIDTH-1:0] wr_data, // Write Data In
input wire rd_rst_n, // Read Domain Active low Reset
input wire rd_clk, // Read Domain Clock
input wire rd_en, // Read Data Enable
input wire [AWIDTH-1:0] r_pempty, // FIFO partially empty threshold
input wire [AWIDTH-1:0] r_pfull, // FIFO partially full threshold
input wire [AWIDTH-1:0] r_empty, // FIFO empty threshold
input wire [AWIDTH-1:0] r_full, // FIFO full threshold
output wire [DWIDTH-1:0] rd_data, // Read Data Out
output wire [AWIDTH-1:0] rd_numdata, // Number of Data available in Read clock
output wire [AWIDTH-1:0] wr_numdata, // Number of Data available in Write clock
output reg wr_empty, // FIFO Empty
output reg wr_pempty, // FIFO Partial Empty
output reg wr_full, // FIFO Full
output reg wr_pfull, // FIFO Parial Full
output reg rd_empty, // FIFO Empty
output reg rd_pempty, // FIFO Partial Empty
output reg rd_full, // FIFO Full
output reg rd_pfull // FIFO Partial Full
);
//********************************************************************
// Define variables
//********************************************************************
integer m;
// Regs
reg [DWIDTH-1:0] fifo_mem [((1<<AWIDTH)-1):0];
reg [AWIDTH:0] wr_addr_bin;
reg [AWIDTH:0] rd_addr_bin;
// reg [AWIDTH:0] rd_addr_bin_next_item;
reg [AWIDTH:0] wr_addr_gry;
reg [AWIDTH:0] rd_addr_gry;
// Wires
wire [AWIDTH-1:0] wr_addr_mem;
wire [AWIDTH-1:0] rd_addr_mem;
// wire [AWIDTH-1:0] rd_addr_mem_next;
wire [AWIDTH:0] wr_addr_bin_nxt;
wire [AWIDTH:0] rd_addr_bin_nxt;
wire [AWIDTH:0] wr_addr_gry_nxt;
wire [AWIDTH:0] rd_addr_gry_nxt;
wire [AWIDTH:0] wr_addr_bin_sync;
wire [AWIDTH:0] rd_addr_bin_sync;
wire [AWIDTH:0] wr_addr_gry_sync;
wire [AWIDTH:0] rd_addr_gry_sync;
//********************************************************************
// Infer Memory or use Dual Port Memory from Quartus/ASIC Memory
//********************************************************************
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
for (m='d0; m<=((1<<AWIDTH)-1'b1); m=m+1'b1) begin
fifo_mem[m] <= 'd0;
end
end
// else if (wr_srst_n == 1'b0) begin
// for (m='d0; m<=((1<<AWIDTH)-1'b1); m=m+1'b1) begin
// fifo_mem[m] <= 'd0;
// end
// end
// Add option to allow write when full
else if (wr_en && ~wr_full) begin
fifo_mem[wr_addr_mem] <= wr_data;
end
end
assign rd_data = fifo_mem[rd_addr_mem];
//********************************************************************
// WRITE CLOCK DOMAIN: Generate WRITE Address & WRITE Address GREY
//********************************************************************
// Memory write-address pointer
assign wr_addr_mem = wr_addr_bin[AWIDTH-1:0];
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wr_addr_bin <= {(AWIDTH+1){1'b0}};
wr_addr_gry <= {(AWIDTH+1){1'b0}};
end
else begin
wr_addr_bin <= wr_addr_bin_nxt;
wr_addr_gry <= wr_addr_gry_nxt;
end
end
// Binary Next Write Address
assign wr_addr_bin_nxt = wr_addr_bin + (wr_en & ~wr_full);
// Grey Next Write Address
// assign wr_addr_gry_nxt = ((wr_addr_bin_nxt>>1) ^ wr_addr_bin_nxt);
c3lib_bintogray #(
.WIDTH ( AWIDTH+1 )
) wr_addr_nxt_bintogray (
.data_in ( wr_addr_bin_nxt ),
.data_out ( wr_addr_gry_nxt )
);
//********************************************************************
// WRITE CLOCK DOMAIN: Synchronize Read Address to Write Clock
//********************************************************************
c3lib_bitsync #(
.DWIDTH ( AWIDTH+1 ),
.RESET_VAL ( 0 ),
.DST_CLK_FREQ_MHZ ( SRC_CLK_FREQ_MHZ ),
.SRC_DATA_FREQ_MHZ( DST_CLK_FREQ_MHZ/4 )
) rd_addr_bitsync (
.clk (wr_clk),
.rst_n (wr_rst_n),
.data_in (rd_addr_gry),
.data_out (rd_addr_gry_sync)
);
// assign rd_addr_bin_sync = greytobin(rd_addr_gry_sync);
c3lib_graytobin #(
.WIDTH ( AWIDTH+1 )
) rd_addr_graytobin (
.data_in ( rd_addr_gry_sync ),
.data_out ( rd_addr_bin_sync )
);
assign wr_numdata = (wr_addr_bin_nxt - rd_addr_bin_sync);
//********************************************************************
// WRITE CLOCK DOMAIN: Generate Fifo Number of Data Present
// using Write Address and Synchronized Read Address
//********************************************************************
always @(negedge wr_rst_n or posedge wr_clk) begin
if (wr_rst_n == 1'b0) begin
wr_full <= 1'b0;
wr_pfull <= 1'b0;
wr_empty <= 1'b1;
wr_pempty<= 1'b1;
end
else begin
// Generate FIFO Empty
wr_empty <= (wr_numdata <= r_empty) ? 1'b1 : 1'b0;
// Generate FIFO Almost Empty
wr_pempty <= (wr_numdata <= r_pempty) ? 1'b1 : 1'b0;
// Generate FIFO Full
wr_full <= (wr_numdata >= r_full) ? 1'b1 : 1'b0;
// Generate FIFO Almost Full
wr_pfull <= (wr_numdata >= r_pfull) ? 1'b1 : 1'b0;
end
end
//********************************************************************
// READ CLOCK DOMAIN: Generate READ Address & READ Address GREY
//********************************************************************
// Memory read-address pointer
assign rd_addr_mem = rd_addr_bin[AWIDTH-1:0];
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
rd_addr_bin <= {(AWIDTH+1){1'b0}};
rd_addr_gry <= {(AWIDTH+1){1'b0}};
end
else begin
rd_addr_bin <= rd_addr_bin_nxt;
rd_addr_gry <= rd_addr_gry_nxt;
end
end
// Binary Next Read Address
assign rd_addr_bin_nxt = rd_addr_bin + (rd_en & ~rd_empty);
// Grey Next Read Address
c3lib_bintogray #(
.WIDTH ( AWIDTH+1 )
) rd_addr_nxt_bintogray (
.data_in ( rd_addr_bin_nxt ),
.data_out ( rd_addr_gry_nxt )
);
//********************************************************************
// READ CLOCK DOMAIN: Synchronize Write Address to Read Clock
//********************************************************************
c3lib_bitsync #(
.DWIDTH ( AWIDTH+1 ),
.RESET_VAL ( 0 ),
.DST_CLK_FREQ_MHZ ( DST_CLK_FREQ_MHZ ),
.SRC_DATA_FREQ_MHZ( SRC_CLK_FREQ_MHZ/4 )
) wr_addr_bitsync (
.clk (rd_clk),
.rst_n (rd_rst_n),
.data_in (wr_addr_gry),
.data_out (wr_addr_gry_sync)
);
c3lib_graytobin #(
.WIDTH ( AWIDTH+1 )
) wr_addr_graytobin (
.data_in ( wr_addr_gry_sync ),
.data_out ( wr_addr_bin_sync )
);
assign rd_numdata = (wr_addr_bin_sync - rd_addr_bin_nxt);
//********************************************************************
// READ CLOCK DOMAIN: Generate Fifo Number of Data Present
// using Read Address and Synchronized Write Address
//********************************************************************
always @(negedge rd_rst_n or posedge rd_clk) begin
if (rd_rst_n == 1'b0) begin
rd_empty <= 1'b1;
rd_pempty <= 1'b1;
rd_full <= 1'b0;
rd_pfull <= 1'b0;
end
else begin
// Generate FIFO Empty
rd_empty <= (rd_numdata <= r_empty) ? 1'b1 : 1'b0;
// Generate FIFO Almost Empty
rd_pempty <= (rd_numdata <= r_pempty) ? 1'b1 : 1'b0;
// Generate FIFO Full
rd_full <= (rd_numdata >= r_full) ? 1'b1 : 1'b0;
// Generate FIFO Almost Full
rd_pfull <= (rd_numdata >= r_pfull) ? 1'b1 : 1'b0;
end
end
endmodule // c3lib_async_fifo |
module c3lib_mux4_ctn(
input logic ck0,
input logic ck1,
input logic ck2,
input logic ck3,
input logic s0,
input logic s1,
output logic ck_out
);
c3lib_ckmux4_lvt_gate c3lib_ckmux4_gate(
// Functional IOs
.ck0 ( ck0 ),
.ck1 ( ck1 ),
.ck2 ( ck2 ),
.ck3 ( ck3 ),
.s0 ( s0 ),
.s1 ( s1 ),
.ck_out ( ck_out ),
// Scan IOs
.tst_override ( 1'b0 ),
.tst_s0 ( 1'b0 ),
.tst_s1 ( 1'b0 )
);
endmodule |
module c3lib_ckinv_ctn(
input logic in,
output logic out
);
c3lib_ckinv_svt_8x u_c3lib_ckinv_svt_8x(
.in ( in ),
.out ( out )
);
endmodule |
module c3lib_ckand2_ctn(
input logic clk_in0,
input logic clk_in1,
output logic clk_out
);
c3lib_and2_svt_4x u_c3lib_and2_svt_4x(
.in0 ( clk_in0 ),
.in1 ( clk_in1 ),
.out ( clk_out )
);
endmodule |
module c3lib_ckbuf_ctn(
input logic in,
output logic out
);
c3lib_buf_svt_4x u_c3lib_buf_svt_4x(
.in ( in ),
.out ( out )
);
endmodule |
module c3lib_ckg_posedge_ctn(
input logic tst_en,
input logic clk_en,
input logic clk,
output logic gated_clk
);
c3lib_ckg_lvt_8x c3lib_ckg_lvt_8x(
.tst_en ( tst_en ),
.clk_en ( clk_en ),
.clk ( clk ),
.gated_clk ( gated_clk )
);
endmodule |
module c3routing_chnl_aib(
// right edge
input i_clk,
input i_rst_n,
input [16:0] i_addr,
input [3:0] i_byte_en,
input i_read,
input i_write,
input [31:0] i_wdata,
output [31:0]o_rdata,
output o_rdatavalid,
output o_waitreq,
input i_adpt_hard_rst_n,
input i_red_idataselb_chain1,
input i_red_idataselb_chain2,
input i_red_shift_en_chain1,
input i_red_shift_en_chain2,
input i_txen_chain1,
input i_txen_chain2,
input i_osc_clk,
input [12:0] i_aibdftdll2adjch,
input i_vccl,
input i_vcchssi,
// left edge
output o_clk,
output o_rst_n,
output [16:0]o_addr,
output [3:0] o_byte_en,
output o_read,
output o_write,
output [31:0]o_wdata,
input [31:0] i_rdata,
input i_rdatavalid,
input i_waitreq,
output o_adpt_hard_rst_n,
output o_red_idataselb_chain1,
output o_red_idataselb_chain2,
output o_red_shift_en_chain1,
output o_red_shift_en_chain2,
output o_txen_chain1,
output o_txen_chain2,
output o_osc_clk,
output [12:0]o_aibdftdll2adjch,
output o_vccl,
output o_vcchssi,
input i_jtag_last_bs_chain_in,
output o_jtag_last_bs_chain_out,
input i_directout_data_chain1_in,
output o_directout_data_chain1_out,
input i_directout_data_chain2_in,
output o_directout_data_chain2_out,
input i_jtag_bs_chain_in,
output o_jtag_bs_chain_out,
input i_jtag_bs_scanen_in,
output o_jtag_bs_scanen_out,
input i_jtag_clkdr_in,
output o_jtag_clkdr_out,
input i_jtag_clksel_in,
output o_jtag_clksel_out,
input i_jtag_intest_in,
output o_jtag_intest_out,
input i_jtag_mode_in,
output o_jtag_mode_out,
input i_jtag_rstb_en_in,
output o_jtag_rstb_en_out,
input i_jtag_rstb_in,
output o_jtag_rstb_out,
input i_jtag_weakpdn_in,
output o_jtag_weakpdn_out,
input i_jtag_weakpu_in,
output o_jtag_weakpu_out
);
`ifndef CRETE3_STUB
assign o_clk = i_clk;
assign o_rst_n = i_rst_n;
assign o_addr = i_addr;
assign o_byte_en = i_byte_en;
assign o_read = i_read;
assign o_write = i_write;
assign o_wdata = i_wdata;
assign o_rdata = i_rdata;
assign o_rdatavalid = i_rdatavalid;
assign o_waitreq = i_waitreq;
assign o_adpt_hard_rst_n = i_adpt_hard_rst_n;
assign o_red_idataselb_chain1 = i_red_idataselb_chain1;
assign o_red_idataselb_chain2 = i_red_idataselb_chain2;
assign o_txen_chain1 = i_txen_chain1;
assign o_txen_chain2 = i_txen_chain2;
assign o_osc_clk = i_osc_clk;
assign o_aibdftdll2adjch = i_aibdftdll2adjch;
assign o_red_shift_en_chain1 = i_red_shift_en_chain1;
assign o_red_shift_en_chain2 = i_red_shift_en_chain2;
assign o_vccl = i_vccl;
assign o_vcchssi = i_vcchssi;
assign o_jtag_last_bs_chain_out = i_jtag_last_bs_chain_in;
assign o_directout_data_chain1_out = i_directout_data_chain1_in;
assign o_directout_data_chain2_out = i_directout_data_chain2_in;
assign o_jtag_bs_chain_out = i_jtag_bs_chain_in;
assign o_jtag_bs_scanen_out = i_jtag_bs_scanen_in;
assign o_jtag_clkdr_out = i_jtag_clkdr_in;
assign o_jtag_clksel_out = i_jtag_clksel_in;
assign o_jtag_intest_out = i_jtag_intest_in;
assign o_jtag_mode_out = i_jtag_mode_in;
assign o_jtag_rstb_en_out = i_jtag_rstb_en_in;
assign o_jtag_rstb_out = i_jtag_rstb_in;
assign o_jtag_weakpdn_out = i_jtag_weakpdn_in;
assign o_jtag_weakpu_out = i_jtag_weakpu_in;
`endif
endmodule |
module c3routing_chnl_edge(
// right edge
output [31:0]o_rdata,
output o_rdatavalid,
output o_waitreq,
output [12:0]o_aibdftdll2adjch,
output o_red_idataselb_chain1,
output o_red_idataselb_chain2,
output o_txen_chain1,
output o_txen_chain2,
output o_red_shift_en_out_chain1,
output o_red_shift_en_out_chain2,
input i_jtag_last_bs_chain_in,
output o_jtag_last_bs_chain_out,
output o_directout_data_chain1_out,
output o_directout_data_chain2_out,
input i_jtag_bs_scanen_in,
input i_jtag_clkdr_in,
input i_jtag_clksel_in,
input i_jtag_intest_in,
input i_jtag_mode_in,
input i_jtag_rstb_en_in,
input i_jtag_rstb_in,
input i_jtag_weakpdn_in,
input i_jtag_weakpu_in
// left edge
);
`ifndef CRETE3_STUB
//Static tie cells to terminate the AVMM chain
assign o_rdata = 32'd0;
assign o_rdatavalid = 1'b0;
assign o_waitreq = 1'b1;
assign o_aibdftdll2adjch = 13'd0;
assign o_red_idataselb_chain1 = 1'b0;
assign o_red_idataselb_chain2 = 1'b0;
assign o_txen_chain1 = 1'b1;
assign o_txen_chain2 = 1'b1;
assign o_red_shift_en_out_chain1 = 1'b0;
assign o_red_shift_en_out_chain2 = 1'b0;
assign o_jtag_last_bs_chain_out = i_jtag_last_bs_chain_in;
assign o_directout_data_chain1_out = '0;
assign o_directout_data_chain2_out = '0;
`endif
endmodule |
module tb_top;
parameter debug = 0;
logic clk = 1'b0;
logic rst, rst_in;
logic led_blue;
logic led_green;
logic led_red;
logic [2:0] gpio;
top #(/*AUTOINSTPARAM*/)
dut
(/*AUTOINST*/
// Outputs
.gpio (gpio[2:0]),
.led_red (led_red),
.led_green (led_green),
.led_blue (led_blue)
);
// Stimulus
always #10 clk = ~clk;
initial begin
$display("Starting simulation");
$dumpfile("tb_top.vcd");
$dumpvars;
// Log the memories
//for (int i=0; i<32; i++) $dumpvars(0, dut.image_mem[i]);
#50000000;
$display("Finishing simulation");
$finish;
end
endmodule // tb_spi_slave |
module servo
#(
// Declare the clock frequency to get the 50Hz update rate
parameter CLK_FREQUENCY = 12000000
)
(
input logic clk,
input logic rst,
input logic [7:0] pos,
output logic pwm
);
localparam CLK_COUNT = CLK_FREQUENCY/(256*1000);
// Design consists of a 256*50Hz generator followed by a simple comparator
logic [7:0] clk_ctr;
logic tick;
// Generate pulses every 1/(256) of a ms for sufficient resolution
always @(posedge clk) tick <= (clk_ctr == CLK_COUNT-2);
always @(posedge clk)
if (rst | tick)
clk_ctr <= '0;
else
clk_ctr <= clk_ctr + 'd1;
// PWM counter
logic [11:0] pwm_ctr;
always @(posedge clk)
if (rst)
pwm_ctr <= '0;
else if (tick)
pwm_ctr <= pwm_ctr + 'd1;
// Generate PWM output
always @(posedge clk)
pwm <= (pwm_ctr < {4'b0001, pos});
endmodule |
module wb_spi_slave (
input logic clk,
input logic rst,
// SPI lines
input logic sck,
input logic ssn,
input logic mosi,
output logic miso,
// Bus interface
output logic o_wb_cyc,
//output logic o_wb_sel,
output logic o_wb_stb,
output logic [23:0] o_wb_adr,
output logic [31:0] o_wb_dat,
output logic o_wb_we,
input logic i_wb_ack,
input logic [31:0] i_wb_dat,
// Control/status to/from SPI slave
output logic reset_out,
input logic [7:0] spi_id,
input logic [7:0] spi_status,
output logic spi_start,
output logic spi_busy,
output logic tx_overrun
);
logic rx_vld, rx_vld_1d;
logic [31:0] wb_rd_data;
logic [23:0] rx_adr;
logic wb_rd_data_vld, wb_rd_data_rdy;
// Clock domain and ser/deser shift registers
spi_slave u_spi_slave(
.o_vld(rx_vld), .o_we(o_wb_we), .o_adr(rx_adr), .o_dat(o_wb_dat),
.i_vld(wb_rd_data_vld), .i_rdy(wb_rd_data_rdy), .i_dat(wb_rd_data),
.*);
// State machine to handle the Wishbone master
enum {WB_IDLE='d0, WB_REQ='d1, WB_WAIT='d2, WB_XXX='d3} wb_curr, wb_next;
// Wishbone master state machine
always @* begin
wb_next = WB_XXX;
o_wb_cyc = '0;
o_wb_stb = '0;
case (wb_curr)
WB_IDLE: begin
if ( rx_vld_1d) begin // (rx_vld_1d & o_wb_we) | (rx_vld & wb_rd_data_rdy & ~o_wb_we) ) begin
// @TODO: Add a WB_PENDING state if wb_rd_data_rdy isnt ready. This should never happen!
wb_next = WB_REQ;
o_wb_cyc = '1;
o_wb_stb = '1;
end else
wb_next = WB_IDLE;
end
WB_REQ: begin
o_wb_cyc = '1;
o_wb_stb = '1;
if (i_wb_ack) begin
wb_next = WB_IDLE;
end
else begin
wb_next = WB_WAIT;
end
end
WB_WAIT: begin
if (i_wb_ack) begin
wb_next = WB_IDLE;
end
else begin
o_wb_cyc = '1;
wb_next = WB_WAIT;
end
end
endcase
// Override reset of the SM
if (rst) begin
wb_next = WB_IDLE;
end
end
// Wishbone SM
always @(posedge clk) begin
if (rst) wb_curr <= WB_IDLE;
else wb_curr <= wb_next;
end
// Capture the WB read xaction
always @(posedge clk) begin
if (rst) begin
o_wb_adr <= '0;
wb_rd_data <= '0;
wb_rd_data_vld <= '0;
rx_vld_1d <= '0;
end else begin
rx_vld_1d <= rx_vld;
if (rx_vld)
o_wb_adr <= rx_adr;
if (i_wb_ack & ~o_wb_we & o_wb_cyc) begin
wb_rd_data <= i_wb_dat;
end
wb_rd_data_vld <= i_wb_ack & ~o_wb_we & o_wb_cyc;
end
end
endmodule |
module tb;
parameter logic debug = 0;
logic clk = 1'b0; // To dut of wb_spi_slave.v
logic rst, rst_dut; // To dut of wb_spi_slave.v
logic i_wb_ack; // To dut of wb_spi_slave.v
logic [31:0] i_wb_dat; // To dut of wb_spi_slave.v
logic [23:0] o_wb_adr; // From dut of wb_spi_slave.v
logic o_wb_cyc; // From dut of wb_spi_slave.v
logic [31:0] o_wb_dat; // From dut of wb_spi_slave.v
logic o_wb_stb; // From dut of wb_spi_slave.v
logic o_wb_we; // From dut of wb_spi_slave.v
logic spi_mosi; // To dut of wb_spi_slave.v
logic spi_miso; // From dut of wb_spi_slave.v
logic spi_clk; // To dut of wb_spi_slave.v
logic spi_ss; // To dut of wb_spi_slave.v
logic tx_overrun;
logic spi_busy;
logic [7:0] spi_id, spi_status;
logic spi_start;
logic reset_out;
logic [31:0] recvWord;
int i;
`include "tb_spi_helpers.sv"
assign #100 rst_dut = reset_out | rst;
wb_spi_slave
dut
(
.rst( rst_dut ),
.sck (spi_clk),
.ssn (spi_ss),
.mosi (spi_mosi),
.miso (spi_miso),
.*
);
// Implement a memory for testing
logic [31:0] mem[10000:0];
logic i_ack;
assign i_wb_ack = i_ack & o_wb_stb;
always @(posedge clk) begin
i_ack <= o_wb_stb & o_wb_cyc;
if (o_wb_cyc & o_wb_stb) begin
if (o_wb_we) begin
mem[o_wb_adr] <= o_wb_dat;
if (i_wb_ack)
$display("%t:: WB Write: addr: 0x%x, data: 0x%x", $time, o_wb_adr, o_wb_dat);
end else begin
i_wb_dat <= mem[o_wb_adr];
if (i_wb_ack)
$display("%t:: WB Read: addr: 0x%x, data: 0x%x", $time, o_wb_adr, mem[o_wb_adr]);
end
end
end
always @(posedge reset_out)
$display("%t::: Got a reset!", $time);
// Stimulus
always #10 clk = ~clk;
logic [23:0] exp_addr;
logic [31:0] temp, temp1, temp2;
initial begin
$display("Starting simulation");
$dumpfile("tb_wb_spi_slave.vcd");
$dumpvars;
// Log the memories
//for (int i=0; i<2; i++) $dumpvars(0, dut.tx_buffer[i]);
spi_ss = '1;
spi_mosi = '0;
spi_clk = '0;
spi_id = 'hde;
spi_status = 'had;
#100 rst = '1;
#100 rst = '0;
#100;
spiWriteReg('hdeadbabe, 'hfeedf00d);
# 1000;
// Burst write
spiWriteStart('hff);
for (int i=0; i<10; i++)
spiWriteWord('hdeadbeef+i);
spiWriteEnd();
#1000;
// Write then read
spiWriteReg('h7fe, 'hfeedf00d);
spiReadReg('h7fe, temp);
$display("Read back: 0x%x", temp);
// Many write then many read
for (int i=0; i<4; i++)
spiWriteReg('h100+i, 'h12345678+4*i);
#5000;
for (int i=0; i<4; i++) begin
spiReadReg('h100+i, temp);
$display("Read back: 0x%x", temp);
end
// Streaming write then Read
spiWriteStart('hfe);
for (int i=0; i<10; i++)
spiWriteWord('h12345678+i);
spiWriteEnd();
#1000;
spiReadStart('hfe); // Address
for (int i=0; i<4; i++) begin
spiReadWord(temp);
$display("Read back: 0x%x", temp);
end
spiReadEnd();
// Get SPI ID
for (int i=0; i<10; i++) begin
spiGetStatus(temp);
$display("Status: 0x%x", temp);
spi_id = spi_id + 'd1;
spi_status = spi_status - 'd1;
end
// Reset the chip
$display("Expect a reset now");
spiSendReset();
/*
spiGetID(temp1, temp2);
`expect_h("SPI ID: ", spi_id, temp1);
`expect_h("SPI Status: ", spi_status, temp2);
exp_addr = $random();
$display("Starting streaming write from address: 0x%x", exp_addr);
spiWriteStart(exp_addr);
for (int i=0; i<16; i++) begin
temp = $random();
spiWriteWord(temp);
`expect_h("SPI_write_addr: ", exp_addr, address);
`expect_h("SPI_write_data: ", temp, rx_data);
exp_addr++;
end
spiWriteEnd();
exp_addr = $random();
$display("Starting streaming write from address: 0x%x", exp_addr);
spiWriteStart(exp_addr);
for (int i=0; i<16; i++) begin
temp = $random();
spiWriteNext(temp);
`expect_h("SPI_write_addr: ", exp_addr, address);
`expect_h("SPI_write_data: ", temp, rx_data);
exp_addr++;
end
spiWriteEnd();
#100;
spiReadStart(15'h10);
for (int i=0; i<16; i++) begin
spiReadNext(recvWord);
`expect_h("SPI read: ", i, recvWord);
end
spiReadEnd();
*/
#10000;
$display("Finishing simulation");
$finish;
end
endmodule // tb_spi_slave |
module spi_slave (
input logic clk,
input logic rst,
// SPI lines
input logic sck,
input logic ssn,
input logic mosi,
output logic miso,
// Data bus
output logic o_vld,
output logic o_we,
output logic [23:0] o_adr,
output logic [31:0] o_dat,
input logic i_vld,
output logic i_rdy,
input logic [31:0] i_dat,
// Control/status to/from SPI slave
output logic reset_out,
input logic [7:0] spi_id,
input logic [7:0] spi_status,
output logic spi_busy,
output logic spi_start,
output logic tx_overrun
);
// SPI protocol
parameter
//SPI_READ_ID = 8'h90,
SPI_READ_STATUS = 8'h05,
//SPI_WRITE_STATUS = 8'h01,
SPI_READ = 8'h0B,
SPI_WRITE = 8'h02,
//SPI_POWERDOWN = 8'hB9,
//SPI_EXIT_POWERDOWN = 8'hAB,
SPI_ARM_RESET = 8'h66,
SPI_FIRE_RESET = 8'h99
;
// SPI serializer & deserializer and clock domain crossing
logic rx_vld, rx_vld_1d, tx_vld, tx_rdy;
logic [7:0] rx_byte, tx_byte;
spi_shifter
u_spi_shifter
(
.sck (sck),
.ssn (ssn),
.mosi (mosi),
.miso (miso),
.clk (clk),
.rst (rst),
.rx_dat(rx_byte),
.rx_vld(rx_vld),
.tx_dat(tx_byte),
.tx_vld(tx_vld),
.tx_rdy(tx_rdy),
.tx_overrun(tx_overrun),
.busy(spi_busy),
.start(spi_start)
);
// Rx processing state machine
// State machine to handle the SPI protocol
enum {
S_IDLE='d0,
S_CMD='d1,
S_ADR_0='d2,
S_ADR_1='d3,
S_ADR_2='d4,
S_GET_RDDATA='d5,
S_DAT_0='d6,
S_DAT_1='d7,
S_DAT_2='d8,
S_DAT_3='d9,
S_INCR_ADR = 'd10,
S_STATUS='d14,
S_XXX='d15
} sm;
logic [7:0] command;
logic [2:0] rx_cnt;
logic reset_armed;
assign tx_ack = '1;
// Next state for SM
always @(posedge clk) begin
if (rst) begin
sm <= S_IDLE;
o_we <= '0;
o_adr <= '0;
reset_armed <= '0;
reset_out <= '0;
end else begin
// Default values:
o_vld <= '0;
tx_vld <= '0;
case (sm)
S_IDLE: if (spi_start) begin
sm <= S_CMD;
tx_vld <= '1;
tx_byte <= spi_id;
end
S_CMD: begin
if (rx_vld) begin
// Command xaction
command <= rx_byte;
case (rx_byte)
SPI_READ, SPI_WRITE: begin
sm <= S_ADR_0;
reset_armed <= '0;
end
SPI_READ_STATUS: begin
sm <= S_STATUS;
tx_vld <= tx_rdy;
tx_byte <= spi_status;
reset_armed <= '0;
end
SPI_ARM_RESET: begin
reset_armed <= '1;
end
SPI_FIRE_RESET: begin
reset_out <= reset_armed;
end
default: sm <= S_IDLE;
endcase
end
end
S_ADR_0: if (rx_vld) begin
sm <= S_ADR_1;
o_adr[23:16] <= rx_byte;
end
S_ADR_1: if (rx_vld) begin
sm <= S_ADR_2;
o_adr[15:8] <= rx_byte;
end
S_ADR_2: if (rx_vld) begin
case (command)
SPI_READ: begin
sm <= S_GET_RDDATA;
o_vld <= '1;
o_we <= '0;
end
SPI_WRITE: begin
sm <= S_DAT_0;
o_we <= '1;
end
endcase
o_adr[7:0] <= rx_byte;
end
S_GET_RDDATA: if (i_vld) begin
sm <= S_DAT_0;
tx_vld <= '1;
tx_byte <= i_dat[31:24];
end
S_DAT_0: if (rx_vld) begin
sm <= S_DAT_1;
if (command == SPI_WRITE)
o_dat[31:24] <= rx_byte;
else begin
tx_byte <= i_dat[23:16];
tx_vld <= '1;
end
end
S_DAT_1: if (rx_vld) begin
sm <= S_DAT_2;
if (command == SPI_WRITE)
o_dat[23:16] <= rx_byte;
else begin
tx_byte <= i_dat[15:8];
tx_vld <= '1;
end
end
S_DAT_2: if (rx_vld) begin
sm <= S_DAT_3;
if (command == SPI_WRITE)
o_dat[15:8] <= rx_byte;
else begin
tx_byte <= i_dat[7:0];
tx_vld <= '1;
end
end
S_DAT_3: if (rx_vld) begin
sm <= S_INCR_ADR;
if (command == SPI_WRITE) begin
o_dat[7:0] <= rx_byte;
o_vld <= '1;
end
end
S_INCR_ADR: begin
o_adr <= o_adr + 'd1;
if (command == SPI_WRITE)
sm <= S_DAT_0;
else begin
o_vld <= '1;
sm <= S_GET_RDDATA;
end
end
S_STATUS: begin
if (rx_vld)
tx_vld <= '1;
tx_byte <= spi_status;
end
endcase
end
// Higher priority for ssn:
if (ssn) begin
sm <= S_IDLE;
o_we <= '0;
o_adr <= '0;
o_vld <= '0;
tx_vld <= '0;
end
end
logic [2:0] tx_cnt;
logic tx_ack;
// Capture incoming data: assumes that the incoming data is held steady till ack'ed
always @(posedge clk)
if (rst) i_rdy <= '1;
else if (i_vld & i_rdy) // Flow control input
i_rdy <= '0;
else if (tx_ack) // Good to go!
i_rdy <= '1;
endmodule |
module top (
// SPI lines
input logic spi_sck,
input logic gpio_23,
output logic spi_mosi,
input logic spi_miso,
output logic led_red,
output logic led_blue,
output logic led_green
);
logic clk, rst_n, rst;
logic spi_reset_out;
logic [22:0] counter;
// Internal oscillator
SB_HFOSC #(.CLKHF_DIV("0b01")) SB_HFOSC_inst(.CLKHFEN(1'b1), .CLKHFPU(1'b1), .CLKHF(clk) );
// Reset
ice40_resetn u_reset_n (.clk(clk), .resetn(rst_n));
assign rst = ~rst_n; // | spi_reset_out;
// Wishbone signals
logic wb_cyc, wb_stb, wb_we, wb_ack;
logic [23:0] wb_adr;
logic [31:0] wb_dat_m2s, wb_dat_s2m;
// SPI Slave
wb_spi_slave u_wb_spi_slave (
.sck(spi_sck),
.ssn(gpio_23),
.mosi(spi_miso),
.miso(spi_mosi),
.o_wb_cyc(wb_cyc),
.o_wb_stb(wb_stb),
.o_wb_adr(wb_adr),
.o_wb_dat(wb_dat_m2s),
.o_wb_we(wb_we),
.i_wb_ack(wb_ack),
.i_wb_dat(wb_dat_s2m),
.reset_out(spi_reset_out),
.spi_id(counter[22:15]),
.spi_status(counter[15:8]),
.spi_start(),
.spi_busy(),
.tx_overrun(),
.*);
// Wishbone peripheral
logic [31:0] mem[255:0];
logic [31:0] my_reg;
logic i_ack;
assign wb_ack = i_ack & wb_stb;
always @(posedge clk) begin
i_ack <= wb_stb & wb_cyc;
if (wb_cyc & wb_stb) begin
if (wb_we) begin
if (wb_adr == 'h0)
my_reg <= wb_dat_m2s;
else
mem[wb_adr[7:0]] <= wb_dat_m2s;
end else begin
if (wb_adr == 'h0)
wb_dat_s2m <= my_reg;
else
wb_dat_s2m <= mem[wb_adr[7:0]];
end
end
end
// Drive some LED's for fun!
logic toggle;
always @(posedge clk) begin
counter <= counter + 'd1;
end
assign toggle = counter[22];
logic duty_cycle;
assign duty_cycle = ~& counter[3:0];
SB_RGBA_DRV u_led_driver(
.CURREN(1'b1),
.RGBLEDEN(1'b1),
.RGB0PWM(my_reg[0] & toggle),
.RGB1PWM(my_reg[1] & toggle),
.RGB2PWM(my_reg[2] & toggle),
.RGB0(led_red),
.RGB1(led_green),
.RGB2(led_blue)
);
defparam u_led_driver.CURRENT_MODE = "0b0" ;
defparam u_led_driver.RGB0_CURRENT = "0b000001";
defparam u_led_driver.RGB1_CURRENT = "0b000001";
defparam u_led_driver.RGB2_CURRENT = "0b000001";
endmodule |
module pipeline_stomach
# (
parameter width = 8
)
(
input clock,
input reset_n,
input [width - 1:0] up_data,
input up_valid,
output up_ready,
output [width - 1:0] down_data,
output down_valid,
input down_ready
);
wire stomach_load, dataout_load, dataout_unload;
reg mux_select;
wire [width - 1:0] data_in;
reg [width - 1:0] stomach_out, mux_out, data_out;
reg data_in_dataout, data_in_stomach;
assign data_in = up_data;
assign down_valid = data_in_dataout;
assign dataout_unload = down_valid & down_ready;
assign dataout_load =
(up_valid & (! data_in_dataout | dataout_unload))
| (data_in_stomach & dataout_unload);
assign stomach_load =
up_valid
& ! data_in_stomach
& (data_in_dataout & ! dataout_unload);
assign up_ready = ! data_in_stomach;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
begin
data_in_stomach <= 1'b0;
data_in_dataout <= 1'b0;
end
else
begin
data_in_stomach <= stomach_load
| (data_in_stomach & ! dataout_unload);
data_in_dataout <= dataout_load
| data_in_stomach
| (data_in_dataout & ! dataout_unload);
end
always @ (posedge clock or negedge reset_n)
if (! reset_n)
mux_select <= 1'b0;
else
mux_select <= stomach_load | (mux_select & ! dataout_load);
always @ (posedge clock or negedge reset_n)
if (! reset_n)
stomach_out <= { width { 1'b0 } };
else if (stomach_load)
stomach_out <= data_in;
always @*
mux_out = mux_select ? stomach_out : data_in;
always @ (posedge clock or negedge reset_n)
if (! reset_n)
data_out <= { width { 1'b0 } };
else if (dataout_load)
data_out <= mux_out;
assign down_data = data_out;
endmodule |
module top
# (
parameter width = 8
)
(
input clock,
input reset_n,
input [width - 1:0] up_data,
input up_valid,
output up_ready,
output [width - 1:0] down_data,
output down_valid,
input down_ready
);
pipeline_stomach # (.width (width))
pipeline_stomach_inst (.*);
/*
clock,
reset_n,
up_data,
up_valid,
up_ready,
down_data,
down_valid,
down_ready
*/
endmodule |
module top
# (
parameter width = 8
)
(
input clock,
input reset_n,
input [width - 1:0] up_data,
input up_valid,
output up_ready,
output [width - 1:0] down_data,
output down_valid,
input down_ready
);
wire [width - 1:0] i12_data;
wire i12_valid;
wire i12_ready;
pipeline_stomach # (.width (width))
pipeline_stomach_inst_1
(
.down_data ( i12_data ),
.down_valid ( i12_valid ),
.down_ready ( i12_ready ),
.*
);
pipeline_stomach # (.width (width))
pipeline_stomach_inst_2
(
.up_data ( i12_data ),
.up_valid ( i12_valid ),
.up_ready ( i12_ready ),
.*
);
endmodule |
module opl3_fpga_v2_0_tb();
xil_axi_uint error_cnt = 0;
xil_axi_uint comparison_cnt = 0;
axi_transaction wr_transaction;
axi_transaction rd_transaction;
axi_monitor_transaction mst_monitor_transaction;
axi_monitor_transaction master_moniter_transaction_queue[$];
xil_axi_uint master_moniter_transaction_queue_size =0;
axi_monitor_transaction mst_scb_transaction;
axi_monitor_transaction passthrough_monitor_transaction;
axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
axi_monitor_transaction passthrough_mst_scb_transaction;
axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
axi_monitor_transaction passthrough_slv_scb_transaction;
axi_monitor_transaction slv_monitor_transaction;
axi_monitor_transaction slave_moniter_transaction_queue[$];
xil_axi_uint slave_moniter_transaction_queue_size =0;
axi_monitor_transaction slv_scb_transaction;
xil_axi_uint mst_agent_verbosity = 0;
xil_axi_uint slv_agent_verbosity = 0;
xil_axi_uint passthrough_agent_verbosity = 0;
bit clock;
bit reset;
integer result_slave;
bit [31:0] S00_AXI_test_data[3:0];
localparam LC_AXI_BURST_LENGTH = 8;
localparam LC_AXI_DATA_WIDTH = 32;
task automatic COMPARE_DATA;
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected;
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave = 0; $stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual);
result_slave = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
" expected = 0x%h",expected, " actual = 0x%h",actual);
end
end
endtask
integer i;
integer j;
xil_axi_uint trans_cnt_before_switch = 48;
xil_axi_uint passthrough_cmd_switch_cnt = 0;
event passthrough_mastermode_start_event;
event passthrough_mastermode_end_event;
event passthrough_slavemode_end_event;
xil_axi_uint mtestID;
xil_axi_ulong mtestADDR;
xil_axi_len_t mtestBurstLength;
xil_axi_size_t mtestDataSize;
xil_axi_burst_t mtestBurstType;
xil_axi_lock_t mtestLOCK;
xil_axi_cache_t mtestCacheType = 0;
xil_axi_prot_t mtestProtectionType = 3'b000;
xil_axi_region_t mtestRegion = 4'b000;
xil_axi_qos_t mtestQOS = 4'b000;
xil_axi_data_beat dbeat;
xil_axi_data_beat [255:0] mtestWUSER;
xil_axi_data_beat mtestAWUSER = 'h0;
xil_axi_data_beat mtestARUSER = 0;
xil_axi_data_beat [255:0] mtestRUSER;
xil_axi_uint mtestBUSER = 0;
xil_axi_resp_t mtestBresp;
xil_axi_resp_t[255:0] mtestRresp;
bit [63:0] mtestWDataL;
bit [63:0] mtestRDataL;
axi_transaction pss_wr_transaction;
axi_transaction pss_rd_transaction;
axi_transaction reactive_transaction;
axi_transaction rd_payload_transaction;
axi_transaction wr_rand;
axi_transaction rd_rand;
axi_transaction wr_reactive;
axi_transaction rd_reactive;
axi_transaction wr_reactive2;
axi_transaction rd_reactive2;
axi_ready_gen bready_gen;
axi_ready_gen rready_gen;
axi_ready_gen awready_gen;
axi_ready_gen wready_gen;
axi_ready_gen arready_gen;
axi_ready_gen bready_gen2;
axi_ready_gen rready_gen2;
axi_ready_gen awready_gen2;
axi_ready_gen wready_gen2;
axi_ready_gen arready_gen2;
xil_axi_payload_byte data_mem[xil_axi_ulong];
opl3_fpga_v2_0_bfm_1_master_0_0_mst_t mst_agent_0;
`BD_WRAPPER DUT(
.ARESETN(reset),
.ACLK(clock)
);
initial begin
mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms
mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
mst_agent_0.set_agent_tag("Master VIP");
mst_agent_0.set_verbosity(mst_agent_verbosity);
mst_agent_0.start_master();
$timeformat (-12, 1, " ps", 1);
end
initial begin
reset <= 1'b0;
#200ns;
reset <= 1'b1;
repeat (5) @(negedge clock);
end
always #5 clock <= ~clock;
initial begin
S_AXI_TEST ( );
#1ns;
$finish;
end
task automatic S_AXI_TEST;
begin
#1;
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts");
mtestID = 0;
mtestADDR = 64'h00000000;
mtestBurstLength = 0;
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
mtestCacheType = 0;
mtestProtectionType = 0;
mtestRegion = 0;
mtestQOS = 0;
result_slave = 1;
mtestWDataL[31:0] = 32'h00000001;
for(int i = 0; i < 4;i++) begin
S00_AXI_test_data[i] <= mtestWDataL[31:0];
mst_agent_0.AXI4LITE_WRITE_BURST(
mtestADDR,
mtestProtectionType,
mtestWDataL,
mtestBresp
);
mtestWDataL[31:0] = mtestWDataL[31:0] + 1;
mtestADDR = mtestADDR + 64'h4;
end
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes");
$display("Sequential read transfers example similar to AXI BFM READ_BURST method starts");
mtestID = 0;
mtestADDR = 64'h00000000;
mtestBurstLength = 0;
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
mtestCacheType = 0;
mtestProtectionType = 0;
mtestRegion = 0;
mtestQOS = 0;
for(int i = 0; i < 4;i++) begin
mst_agent_0.AXI4LITE_READ_BURST(
mtestADDR,
mtestProtectionType,
mtestRDataL,
mtestRresp
);
mtestADDR = mtestADDR + 64'h4;
COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL);
end
$display("Sequential read transfers example similar to AXI BFM READ_BURST method completes");
$display("Sequential read transfers example similar to AXI VIP READ_BURST method completes");
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
endmodule |
module dummy_tb;
initial begin
$display("Hello, Verilator!");
$finish;
end
endmodule |
module i2s_tb;
localparam CLK_HALF_PERIOD = 1/real'(CLK_FREQ)*1000e6/2;
localparam GATE_DELAY = 2; // in ns
bit clk;
wire sample_clk_en;
bit [DAC_OUTPUT_WIDTH-1:0] left_channel = 0;
bit [DAC_OUTPUT_WIDTH-1:0] right_channel = 2**16/2;
wire i2s_sclk;
wire i2s_ws;
wire i2s_sd;
always begin
#CLK_HALF_PERIOD clk = 0;
#CLK_HALF_PERIOD clk = 1;
end
clk_div #(
.INPUT_CLK_FREQ(CLK_FREQ),
.OUTPUT_CLK_EN_FREQ(ACTUAL_SAMPLE_FREQ)
) sample_clk_gen_inst (
.clk_en(sample_clk_en),
.*
);
i2s i2s_inst (
.*
);
always_ff @(posedge clk)
if (sample_clk_en) begin
left_channel <= left_channel + 1;
right_channel <= right_channel + 1;
end
endmodule |
module ibex_controller #(
parameter bit WritebackStage = 0,
parameter bit BranchPredictor = 0
) (
input logic clk_i,
input logic rst_ni,
output logic ctrl_busy_o, // core is busy processing instrs
// decoder related signals
input logic illegal_insn_i, // decoder has an invalid instr
input logic ecall_insn_i, // decoder has ECALL instr
input logic mret_insn_i, // decoder has MRET instr
input logic dret_insn_i, // decoder has DRET instr
input logic wfi_insn_i, // decoder has WFI instr
input logic ebrk_insn_i, // decoder has EBREAK instr
input logic csr_pipe_flush_i, // do CSR-related pipeline flush
// instr from IF-ID pipeline stage
input logic instr_valid_i, // instr is valid
input logic [31:0] instr_i, // uncompressed instr data for mtval
input logic [15:0] instr_compressed_i, // instr compressed data for mtval
input logic instr_is_compressed_i, // instr is compressed
input logic instr_bp_taken_i, // instr was predicted taken branch
input logic instr_fetch_err_i, // instr has error
input logic instr_fetch_err_plus2_i, // instr error is x32
input logic [31:0] pc_id_i, // instr address
// to IF-ID pipeline stage
output logic instr_valid_clear_o, // kill instr in IF-ID reg
output logic id_in_ready_o, // ID stage is ready for new instr
output logic controller_run_o, // Controller is in standard instruction
// run mode
// to prefetcher
output logic instr_req_o, // start fetching instructions
output logic pc_set_o, // jump to address set by pc_mux
output logic pc_set_spec_o, // speculative branch
output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector
// (boot, normal, exception...)
output logic nt_branch_mispredict_o, // Not-taken branch in ID/EX was
// mispredicted (predicted taken)
output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
output ibex_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs
// LSU
input logic [31:0] lsu_addr_last_i, // for mtval
input logic load_err_i,
input logic store_err_i,
output logic wb_exception_o, // Instruction in WB taking an exception
output logic id_exception_o, // Instruction in ID taking an exception
// jump/branch signals
input logic branch_set_i, // branch set signal (branch definitely
// taken)
input logic branch_set_spec_i, // speculative branch signal (branch
// may be taken)
input logic branch_not_set_i, // branch is definitely not taken
input logic jump_set_i, // jump taken set signal
// interrupt signals
input logic csr_mstatus_mie_i, // M-mode interrupt enable bit
input logic irq_pending_i, // interrupt request pending
input ibex_pkg::irqs_t irqs_i, // interrupt requests qualified with
// mie CSR
input logic irq_nm_i, // non-maskeable interrupt
output logic nmi_mode_o, // core executing NMI handler
// debug signals
input logic debug_req_i,
output ibex_pkg::dbg_cause_e debug_cause_o,
output logic debug_csr_save_o,
output logic debug_mode_o,
input logic debug_single_step_i,
input logic debug_ebreakm_i,
input logic debug_ebreaku_i,
input logic trigger_match_i,
output logic csr_save_if_o,
output logic csr_save_id_o,
output logic csr_save_wb_o,
output logic csr_restore_mret_id_o,
output logic csr_restore_dret_id_o,
output logic csr_save_cause_o,
output logic [31:0] csr_mtval_o,
input ibex_pkg::priv_lvl_e priv_mode_i,
input logic csr_mstatus_tw_i,
// stall & flush signals
input logic stall_id_i,
input logic stall_wb_i,
output logic flush_id_o,
input logic ready_wb_i,
// performance monitors
output logic perf_jump_o, // we are executing a jump
// instruction (j, jr, jal, jalr)
output logic perf_tbranch_o // we are executing a taken branch
// instruction
);
import ibex_pkg::*;
// FSM state encoding
typedef enum logic [3:0] {
RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH,
IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID
} ctrl_fsm_e;
ctrl_fsm_e ctrl_fsm_cs, ctrl_fsm_ns;
logic nmi_mode_q, nmi_mode_d;
logic debug_mode_q, debug_mode_d;
logic load_err_q, load_err_d;
logic store_err_q, store_err_d;
logic exc_req_q, exc_req_d;
logic illegal_insn_q, illegal_insn_d;
// Of the various exception/fault signals, which one takes priority in FLUSH and hence controls
// what happens next (setting exc_cause, csr_mtval etc)
logic instr_fetch_err_prio;
logic illegal_insn_prio;
logic ecall_insn_prio;
logic ebrk_insn_prio;
logic store_err_prio;
logic load_err_prio;
logic stall;
logic halt_if;
logic retain_id;
logic flush_id;
logic illegal_dret;
logic illegal_umode;
logic exc_req_lsu;
logic special_req;
logic special_req_pc_change;
logic special_req_flush_only;
logic do_single_step_d;
logic do_single_step_q;
logic enter_debug_mode_prio_d;
logic enter_debug_mode_prio_q;
logic enter_debug_mode;
logic ebreak_into_debug;
logic handle_irq;
logic id_wb_pending;
logic [3:0] mfip_id;
logic unused_irq_timer;
logic ecall_insn;
logic mret_insn;
logic dret_insn;
logic wfi_insn;
logic ebrk_insn;
logic csr_pipe_flush;
logic instr_fetch_err;
`ifndef SYNTHESIS
// synopsys translate_off
// make sure we are called later so that we do not generate messages for
// glitches
always_ff @(negedge clk_i) begin
// print warning in case of decoding errors
if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin
$display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, ibex_core.hart_id_i,
ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);
end
end
// synopsys translate_on
`endif
////////////////
// Exceptions //
////////////////
assign load_err_d = load_err_i;
assign store_err_d = store_err_i;
// Decoder doesn't take instr_valid into account, factor it in here.
assign ecall_insn = ecall_insn_i & instr_valid_i;
assign mret_insn = mret_insn_i & instr_valid_i;
assign dret_insn = dret_insn_i & instr_valid_i;
assign wfi_insn = wfi_insn_i & instr_valid_i;
assign ebrk_insn = ebrk_insn_i & instr_valid_i;
assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i;
assign instr_fetch_err = instr_fetch_err_i & instr_valid_i;
// "Executing DRET outside of Debug Mode causes an illegal instruction exception."
// [Debug Spec v0.13.2, p.41]
assign illegal_dret = dret_insn & ~debug_mode_q;
// Some instructions can only be executed in M-Mode
assign illegal_umode = (priv_mode_i != PRIV_LVL_M) &
// MRET must be in M-Mode. TW means trap WFI to M-Mode.
(mret_insn | (csr_mstatus_tw_i & wfi_insn));
// This is recorded in the illegal_insn_q flop to help timing. Specifically
// it is needed to break the path from ibex_cs_registers/illegal_csr_insn_o
// to pc_set_o. Clear when controller is in FLUSH so it won't remain set
// once illegal instruction is handled.
// All terms in this expression are qualified by instr_valid_i
assign illegal_insn_d = (illegal_insn_i | illegal_dret | illegal_umode) & (ctrl_fsm_cs != FLUSH);
// exception requests
// requests are flopped in exc_req_q. This is cleared when controller is in
// the FLUSH state so the cycle following exc_req_q won't remain set for an
// exception request that has just been handled.
// All terms in this expression are qualified by instr_valid_i
assign exc_req_d = (ecall_insn | ebrk_insn | illegal_insn_d | instr_fetch_err) &
(ctrl_fsm_cs != FLUSH);
// LSU exception requests
assign exc_req_lsu = store_err_i | load_err_i;
assign id_exception_o = exc_req_d;
// special requests: special instructions, pipeline flushes, exceptions...
// All terms in these expressions are qualified by instr_valid_i except exc_req_lsu which can come
// from the Writeback stage with no instr_valid_i from the ID stage
// These special requests only cause a pipeline flush and in particular don't cause a PC change
// that is outside the normal execution flow
assign special_req_flush_only = wfi_insn | csr_pipe_flush;
// These special requests cause a change in PC
assign special_req_pc_change = mret_insn | dret_insn | exc_req_d | exc_req_lsu;
// generic special request signal, applies to all instructions
assign special_req = special_req_pc_change | special_req_flush_only;
// Is there an instruction in ID or WB that has yet to complete?
assign id_wb_pending = instr_valid_i | ~ready_wb_i;
// Exception/fault prioritisation is taken from Table 3.7 of Priviledged Spec v1.11
if (WritebackStage) begin : g_wb_exceptions
always_comb begin
instr_fetch_err_prio = 0;
illegal_insn_prio = 0;
ecall_insn_prio = 0;
ebrk_insn_prio = 0;
store_err_prio = 0;
load_err_prio = 0;
// Note that with the writeback stage store/load errors occur on the instruction in writeback,
// all other exception/faults occur on the instruction in ID/EX. The faults from writeback
// must take priority as that instruction is architecurally ordered before the one in ID/EX.
if (store_err_q) begin
store_err_prio = 1'b1;
end else if (load_err_q) begin
load_err_prio = 1'b1;
end else if (instr_fetch_err) begin
instr_fetch_err_prio = 1'b1;
end else if (illegal_insn_q) begin
illegal_insn_prio = 1'b1;
end else if (ecall_insn) begin
ecall_insn_prio = 1'b1;
end else if (ebrk_insn) begin
ebrk_insn_prio = 1'b1;
end
end
// Instruction in writeback is generating an exception so instruction in ID must not execute
assign wb_exception_o = load_err_q | store_err_q | load_err_i | store_err_i;
end else begin : g_no_wb_exceptions
always_comb begin
instr_fetch_err_prio = 0;
illegal_insn_prio = 0;
ecall_insn_prio = 0;
ebrk_insn_prio = 0;
store_err_prio = 0;
load_err_prio = 0;
if (instr_fetch_err) begin
instr_fetch_err_prio = 1'b1;
end else if (illegal_insn_q) begin
illegal_insn_prio = 1'b1;
end else if (ecall_insn) begin
ecall_insn_prio = 1'b1;
end else if (ebrk_insn) begin
ebrk_insn_prio = 1'b1;
end else if (store_err_q) begin
store_err_prio = 1'b1;
end else if (load_err_q) begin
load_err_prio = 1'b1;
end
end
assign wb_exception_o = 1'b0;
end
`ASSERT_IF(IbexExceptionPrioOnehot,
$onehot({instr_fetch_err_prio,
illegal_insn_prio,
ecall_insn_prio,
ebrk_insn_prio,
store_err_prio,
load_err_prio}),
(ctrl_fsm_cs == FLUSH) & exc_req_q)
////////////////
// Interrupts //
////////////////
// Enter debug mode due to an external debug_req_i or because the core is in
// single step mode (dcsr.step == 1). Single step must be qualified with
// instruction valid otherwise the core will immediately enter debug mode
// due to a recently flushed IF (or a delay in an instruction returning from
// memory) before it has had anything to single step.
// Also enter debug mode on a trigger match (hardware breakpoint)
// Set `do_single_step_q` when a valid instruction is seen outside of debug mode and core is in
// single step mode. The first valid instruction on debug mode entry will clear it. Hold its value
// when there is no valid instruction so `do_single_step_d` remains asserted until debug mode is
// entered.
assign do_single_step_d = instr_valid_i ? ~debug_mode_q & debug_single_step_i : do_single_step_q;
// Enter debug mode due to:
// * external `debug_req_i`
// * core in single step mode (dcsr.step == 1).
// * trigger match (hardware breakpoint)
//
// `debug_req_i` and `do_single_step_d` request debug mode with priority. This results in a debug
// mode entry even if the controller goes to `FLUSH` in preparation for handling an exception or
// interrupt. `trigger_match_i` is not a priority entry into debug mode as it must be ignored
// where control flow changes such that the instruction causing the trigger is no longer being
// executed.
assign enter_debug_mode_prio_d = (debug_req_i | do_single_step_d) & ~debug_mode_q;
assign enter_debug_mode = enter_debug_mode_prio_d | (trigger_match_i & ~debug_mode_q);
// Set when an ebreak should enter debug mode rather than jump to exception
// handler
assign ebreak_into_debug = priv_mode_i == PRIV_LVL_M ? debug_ebreakm_i :
priv_mode_i == PRIV_LVL_U ? debug_ebreaku_i :
1'b0;
// Interrupts including NMI are ignored,
// - while in debug mode [Debug Spec v0.13.2, p.39],
// - while in NMI mode (nested NMIs are not supported, NMI has highest priority and
// cannot be interrupted by regular interrupts).
assign handle_irq = ~debug_mode_q & ~nmi_mode_q &
(irq_nm_i | (irq_pending_i & csr_mstatus_mie_i));
// generate ID of fast interrupts, highest priority to lowest ID
always_comb begin : gen_mfip_id
mfip_id = 4'd0;
for (int i = 14; i >= 0; i--) begin
if (irqs_i.irq_fast[i]) begin
mfip_id = i[3:0];
end
end
end
assign unused_irq_timer = irqs_i.irq_timer;
/////////////////////
// Core controller //
/////////////////////
always_comb begin
// Default values
instr_req_o = 1'b1;
csr_save_if_o = 1'b0;
csr_save_id_o = 1'b0;
csr_save_wb_o = 1'b0;
csr_restore_mret_id_o = 1'b0;
csr_restore_dret_id_o = 1'b0;
csr_save_cause_o = 1'b0;
csr_mtval_o = '0;
// The values of pc_mux and exc_pc_mux are only relevant if pc_set is set. Some of the states
// below always set pc_mux and exc_pc_mux but only set pc_set if certain conditions are met.
// This avoid having to factor those conditions into the pc_mux and exc_pc_mux select signals
// helping timing.
pc_mux_o = PC_BOOT;
pc_set_o = 1'b0;
pc_set_spec_o = 1'b0;
nt_branch_mispredict_o = 1'b0;
exc_pc_mux_o = EXC_PC_IRQ;
exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00
ctrl_fsm_ns = ctrl_fsm_cs;
ctrl_busy_o = 1'b1;
halt_if = 1'b0;
retain_id = 1'b0;
flush_id = 1'b0;
debug_csr_save_o = 1'b0;
debug_cause_o = DBG_CAUSE_EBREAK;
debug_mode_d = debug_mode_q;
nmi_mode_d = nmi_mode_q;
perf_tbranch_o = 1'b0;
perf_jump_o = 1'b0;
controller_run_o = 1'b0;
unique case (ctrl_fsm_cs)
RESET: begin
instr_req_o = 1'b0;
pc_mux_o = PC_BOOT;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
ctrl_fsm_ns = BOOT_SET;
end
BOOT_SET: begin
// copy boot address to instr fetch address
instr_req_o = 1'b1;
pc_mux_o = PC_BOOT;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
ctrl_fsm_ns = FIRST_FETCH;
end
WAIT_SLEEP: begin
ctrl_busy_o = 1'b0;
instr_req_o = 1'b0;
halt_if = 1'b1;
flush_id = 1'b1;
ctrl_fsm_ns = SLEEP;
end
SLEEP: begin
// instruction in IF stage is already valid
// we begin execution when an interrupt has arrived
instr_req_o = 1'b0;
halt_if = 1'b1;
flush_id = 1'b1;
// normal execution flow
// in debug mode or single step mode we leave immediately (wfi=nop)
if (irq_nm_i || irq_pending_i || debug_req_i || debug_mode_q || debug_single_step_i) begin
ctrl_fsm_ns = FIRST_FETCH;
end else begin
// Make sure clock remains disabled.
ctrl_busy_o = 1'b0;
end
end
FIRST_FETCH: begin
// Stall because of IF miss
if (id_in_ready_o) begin
ctrl_fsm_ns = DECODE;
end
// handle interrupts
if (handle_irq) begin
// We are handling an interrupt. Set halt_if to tell IF not to give
// us any more instructions before it redirects to the handler, but
// don't set flush_id: we must allow this instruction to complete
// (since it might have outstanding loads or stores).
ctrl_fsm_ns = IRQ_TAKEN;
halt_if = 1'b1;
end
// enter debug mode
if (enter_debug_mode) begin
ctrl_fsm_ns = DBG_TAKEN_IF;
// Halt IF only for now, ID will be flushed in DBG_TAKEN_IF as the
// ID state is needed for correct debug mode entry
halt_if = 1'b1;
end
end
DECODE: begin
// normal operating mode of the ID stage, in case of debug and interrupt requests,
// priorities are as follows (lower number == higher priority)
// 1. currently running (multicycle) instructions and exceptions caused by these
// 2. debug requests
// 3. interrupt requests
controller_run_o = 1'b1;
// Set PC mux for branch and jump here to ease timing. Value is only relevant if pc_set_o is
// also set. Setting the mux value here avoids factoring in special_req and instr_valid_i
// which helps timing.
pc_mux_o = PC_JUMP;
// Get ready for special instructions, exceptions, pipeline flushes
if (special_req) begin
// Halt IF but don't flush ID. This leaves a valid instruction in
// ID so controller can determine appropriate action in the
// FLUSH state.
retain_id = 1'b1;
// Wait for the writeback stage to either be ready for a new instruction or raise its own
// exception before going to FLUSH. If the instruction in writeback raises an exception it
// must take priority over any exception from an instruction in ID/EX. Only once the
// writeback stage is ready can we be certain that won't happen. Without a writeback
// stage ready_wb_i == 1 so the FSM will always go directly to FLUSH.
if (ready_wb_i | wb_exception_o) begin
ctrl_fsm_ns = FLUSH;
end
end
if (branch_set_i || jump_set_i) begin
// Only set the PC if the branch predictor hasn't already done the branch for us
pc_set_o = BranchPredictor ? ~instr_bp_taken_i : 1'b1;
perf_tbranch_o = branch_set_i;
perf_jump_o = jump_set_i;
end
if (BranchPredictor) begin
if (instr_bp_taken_i & branch_not_set_i) begin
// If the instruction is a branch that was predicted to be taken but was not taken
// signal a mispredict.
nt_branch_mispredict_o = 1'b1;
end
end
// pc_set signal excluding branch taken condition
if (branch_set_spec_i || jump_set_i) begin
// Only speculatively set the PC if the branch predictor hasn't already done the branch
// for us
pc_set_spec_o = BranchPredictor ? ~instr_bp_taken_i : 1'b1;
end
// If entering debug mode or handling an IRQ the core needs to wait until any instruction in
// ID or WB has finished executing. Stall IF during that time.
if ((enter_debug_mode || handle_irq) && (stall || id_wb_pending)) begin
halt_if = 1'b1;
end
if (!stall && !special_req && !id_wb_pending) begin
if (enter_debug_mode) begin
// enter debug mode
ctrl_fsm_ns = DBG_TAKEN_IF;
// Halt IF only for now, ID will be flushed in DBG_TAKEN_IF as the
// ID state is needed for correct debug mode entry
halt_if = 1'b1;
end else if (handle_irq) begin
// handle interrupt (not in debug mode)
ctrl_fsm_ns = IRQ_TAKEN;
// We are handling an interrupt (not in debug mode). Set halt_if to
// tell IF not to give us any more instructions before it redirects
// to the handler, but don't set flush_id: we must allow this
// instruction to complete (since it might have outstanding loads
// or stores).
halt_if = 1'b1;
end
end
end // DECODE
IRQ_TAKEN: begin
pc_mux_o = PC_EXC;
exc_pc_mux_o = EXC_PC_IRQ;
if (handle_irq) begin
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
csr_save_if_o = 1'b1;
csr_save_cause_o = 1'b1;
// interrupt priorities according to Privileged Spec v1.11 p.31
if (irq_nm_i && !nmi_mode_q) begin
exc_cause_o = EXC_CAUSE_IRQ_NM;
nmi_mode_d = 1'b1; // enter NMI mode
end else if (irqs_i.irq_fast != 15'b0) begin
// generate exception cause ID from fast interrupt ID:
// - first bit distinguishes interrupts from exceptions,
// - second bit adds 16 to fast interrupt ID
// for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16}
exc_cause_o = exc_cause_e'({2'b11, mfip_id});
end else if (irqs_i.irq_external) begin
exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M;
end else if (irqs_i.irq_software) begin
exc_cause_o = EXC_CAUSE_IRQ_SOFTWARE_M;
end else begin // irqs_i.irq_timer
exc_cause_o = EXC_CAUSE_IRQ_TIMER_M;
end
end
ctrl_fsm_ns = DECODE;
end
DBG_TAKEN_IF: begin
pc_mux_o = PC_EXC;
exc_pc_mux_o = EXC_PC_DBD;
// enter debug mode and save PC in IF to dpc
// jump to debug exception handler in debug memory
flush_id = 1'b1;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
csr_save_if_o = 1'b1;
debug_csr_save_o = 1'b1;
csr_save_cause_o = 1'b1;
if (trigger_match_i) begin
debug_cause_o = DBG_CAUSE_TRIGGER;
end else if (debug_single_step_i) begin
debug_cause_o = DBG_CAUSE_STEP;
end else begin
debug_cause_o = DBG_CAUSE_HALTREQ;
end
// enter debug mode
debug_mode_d = 1'b1;
ctrl_fsm_ns = DECODE;
end
DBG_TAKEN_ID: begin
// enter debug mode and save PC in ID to dpc, used when encountering
// 1. EBREAK during debug mode
// 2. EBREAK with forced entry into debug mode (ebreakm or ebreaku set).
// regular ebreak's go through FLUSH.
//
// for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39]
// jump to debug exception handler in debug memory
flush_id = 1'b1;
pc_mux_o = PC_EXC;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
exc_pc_mux_o = EXC_PC_DBD;
// update dcsr and dpc
if (ebreak_into_debug && !debug_mode_q) begin // ebreak with forced entry
// dpc (set to the address of the EBREAK, i.e. set to PC in ID stage)
csr_save_cause_o = 1'b1;
csr_save_id_o = 1'b1;
// dcsr
debug_csr_save_o = 1'b1;
debug_cause_o = DBG_CAUSE_EBREAK;
end
// enter debug mode
debug_mode_d = 1'b1;
ctrl_fsm_ns = DECODE;
end
FLUSH: begin
// flush the pipeline
halt_if = 1'b1;
flush_id = 1'b1;
ctrl_fsm_ns = DECODE;
// As pc_mux and exc_pc_mux can take various values in this state they aren't set early
// here.
// exceptions: set exception PC, save PC and exception cause
// exc_req_lsu is high for one clock cycle only (in DECODE)
if (exc_req_q || store_err_q || load_err_q) begin
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
pc_mux_o = PC_EXC;
exc_pc_mux_o = debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC;
if (WritebackStage) begin : g_writeback_mepc_save
// With the writeback stage present whether an instruction accessing memory will cause
// an exception is only known when it is in writeback. So when taking such an exception
// epc must come from writeback.
csr_save_id_o = ~(store_err_q | load_err_q);
csr_save_wb_o = store_err_q | load_err_q;
end else begin : g_no_writeback_mepc_save
csr_save_id_o = 1'b0;
end
csr_save_cause_o = 1'b1;
// Exception/fault prioritisation logic will have set exactly 1 X_prio signal
unique case (1'b1)
instr_fetch_err_prio: begin
exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT;
csr_mtval_o = instr_fetch_err_plus2_i ? (pc_id_i + 32'd2) : pc_id_i;
end
illegal_insn_prio: begin
exc_cause_o = EXC_CAUSE_ILLEGAL_INSN;
csr_mtval_o = instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i;
end
ecall_insn_prio: begin
exc_cause_o = (priv_mode_i == PRIV_LVL_M) ? EXC_CAUSE_ECALL_MMODE :
EXC_CAUSE_ECALL_UMODE;
end
ebrk_insn_prio: begin
if (debug_mode_q | ebreak_into_debug) begin
/*
* EBREAK in debug mode re-enters debug mode
*
* "The only exception is EBREAK. When that is executed in Debug
* Mode, it halts the hart again but without updating dpc or
* dcsr." [Debug Spec v0.13.2, p.39]
*/
/*
* dcsr.ebreakm == 1:
* "EBREAK instructions in M-mode enter Debug Mode."
* [Debug Spec v0.13.2, p.42]
*/
pc_set_o = 1'b0;
pc_set_spec_o = 1'b0;
csr_save_id_o = 1'b0;
csr_save_cause_o = 1'b0;
ctrl_fsm_ns = DBG_TAKEN_ID;
flush_id = 1'b0;
end else begin
/*
* "The EBREAK instruction is used by debuggers to cause control
* to be transferred back to a debugging environment. It
* generates a breakpoint exception and performs no other
* operation. [...] ECALL and EBREAK cause the receiving
* privilege mode's epc register to be set to the address of the
* ECALL or EBREAK instruction itself, not the address of the
* following instruction." [Privileged Spec v1.11, p.40]
*/
exc_cause_o = EXC_CAUSE_BREAKPOINT;
end
end
store_err_prio: begin
exc_cause_o = EXC_CAUSE_STORE_ACCESS_FAULT;
csr_mtval_o = lsu_addr_last_i;
end
load_err_prio: begin
exc_cause_o = EXC_CAUSE_LOAD_ACCESS_FAULT;
csr_mtval_o = lsu_addr_last_i;
end
default: ;
endcase
end else begin
// special instructions and pipeline flushes
if (mret_insn) begin
pc_mux_o = PC_ERET;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
csr_restore_mret_id_o = 1'b1;
if (nmi_mode_q) begin
nmi_mode_d = 1'b0; // exit NMI mode
end
end else if (dret_insn) begin
pc_mux_o = PC_DRET;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
debug_mode_d = 1'b0;
csr_restore_dret_id_o = 1'b1;
end else if (wfi_insn) begin
ctrl_fsm_ns = WAIT_SLEEP;
end else if (csr_pipe_flush && handle_irq) begin
// start handling IRQs when doing CSR-related pipeline flushes
ctrl_fsm_ns = IRQ_TAKEN;
end
end // exc_req_q
// Entering debug mode due to either single step or debug_req. Ensure
// registers are set for exception but then enter debug handler rather
// than exception handler [Debug Spec v0.13.2, p.44]
// Leave all other signals as is to ensure CSRs and PC get set as if
// core was entering exception handler, entry to debug mode will then
// see the appropriate state and setup dpc correctly.
// If an EBREAK instruction is causing us to enter debug mode on the
// same cycle as a debug_req or single step, honor the EBREAK and
// proceed to DBG_TAKEN_ID.
if (enter_debug_mode_prio_q && !(ebrk_insn_prio && ebreak_into_debug)) begin
ctrl_fsm_ns = DBG_TAKEN_IF;
end
end // FLUSH
default: begin
instr_req_o = 1'b0;
ctrl_fsm_ns = RESET;
end
endcase
end
assign flush_id_o = flush_id;
// signal to CSR when in debug mode
assign debug_mode_o = debug_mode_q;
// signal to CSR when in an NMI handler (for nested exception handling)
assign nmi_mode_o = nmi_mode_q;
///////////////////
// Stall control //
///////////////////
// If high current instruction cannot complete this cycle. Either because it needs more cycles to
// finish (stall_id_i) or because the writeback stage cannot accept it yet (stall_wb_i). If there
// is no writeback stage stall_wb_i is a constant 0.
assign stall = stall_id_i | stall_wb_i;
// signal to IF stage that ID stage is ready for next instr
assign id_in_ready_o = ~stall & ~halt_if & ~retain_id;
// kill instr in IF-ID pipeline reg that are done, or if a
// multicycle instr causes an exception for example
// retain_id is another kind of stall, where the instr_valid bit must remain
// set (unless flush_id is set also). It cannot be factored directly into
// stall as this causes a combinational loop.
assign instr_valid_clear_o = ~(stall | retain_id) | flush_id;
// update registers
always_ff @(posedge clk_i or negedge rst_ni) begin : update_regs
if (!rst_ni) begin
ctrl_fsm_cs <= RESET;
nmi_mode_q <= 1'b0;
do_single_step_q <= 1'b0;
debug_mode_q <= 1'b0;
enter_debug_mode_prio_q <= 1'b0;
load_err_q <= 1'b0;
store_err_q <= 1'b0;
exc_req_q <= 1'b0;
illegal_insn_q <= 1'b0;
end else begin
ctrl_fsm_cs <= ctrl_fsm_ns;
nmi_mode_q <= nmi_mode_d;
do_single_step_q <= do_single_step_d;
debug_mode_q <= debug_mode_d;
enter_debug_mode_prio_q <= enter_debug_mode_prio_d;
load_err_q <= load_err_d;
store_err_q <= store_err_d;
exc_req_q <= exc_req_d;
illegal_insn_q <= illegal_insn_d;
end
end
//////////
// FCOV //
//////////
`DV_FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN))
`DV_FCOV_SIGNAL(logic, debug_entry_if,
(ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF))
`DV_FCOV_SIGNAL(logic, debug_entry_id,
(ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID))
`DV_FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH))
`DV_FCOV_SIGNAL(logic, debug_req, debug_req_i & ~debug_mode_q)
////////////////
// Assertions //
////////////////
`ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o |-> instr_valid_clear_o)
// Selectors must be known/valid.
`ASSERT(IbexCtrlStateValid, ctrl_fsm_cs inside {
RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH,
IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID})
// The speculative branch signal should be set whenever the actual branch signal is set
`ASSERT(IbexSpecImpliesSetPC, pc_set_o |-> pc_set_spec_o)
`ifdef INC_ASSERT
// If something that causes a jump into an exception handler is seen that jump must occur before
// the next instruction executes. The logic tracks whether a jump into an exception handler is
// expected. Assertions check the jump occurs.
logic exception_req, exception_req_pending, exception_req_accepted, exception_req_done;
logic exception_pc_set, seen_exception_pc_set, expect_exception_pc_set;
logic exception_req_needs_pc_set;
assign exception_req = (special_req | enter_debug_mode | handle_irq);
// Any exception rquest will cause a transition out of DECODE, once the controller transitions
// back into DECODE we're done handling the request.
assign exception_req_done =
exception_req_pending & (ctrl_fsm_cs != DECODE) & (ctrl_fsm_ns == DECODE);
assign exception_req_needs_pc_set = enter_debug_mode | handle_irq | special_req_pc_change;
// An exception PC set uses specific PC types
assign exception_pc_set =
exception_req_pending & (pc_set_o & (pc_mux_o inside {PC_EXC, PC_ERET, PC_DRET}));
always @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
exception_req_pending <= 1'b0;
exception_req_accepted <= 1'b0;
expect_exception_pc_set <= 1'b0;
seen_exception_pc_set <= 1'b0;
end else begin
// Keep `exception_req_pending` asserted once an exception_req is seen until it is done
exception_req_pending <= (exception_req_pending | exception_req) & ~exception_req_done;
// The exception req has been accepted once the controller transitions out of decode
exception_req_accepted <= (exception_req_accepted & ~exception_req_done) |
(exception_req & ctrl_fsm_ns != DECODE);
// Set `expect_exception_pc_set` if exception req needs one and keep it asserted until
// exception req is done
expect_exception_pc_set <= (expect_exception_pc_set | exception_req_needs_pc_set) &
~exception_req_done;
// Keep `seen_exception_pc_set` asserted once an exception PC set is seen until the
// exception req is done
seen_exception_pc_set <= (seen_exception_pc_set | exception_pc_set) & ~exception_req_done;
end
end
// Once an exception request has been accepted it must be handled before controller goes back to
// DECODE
`ASSERT(IbexNoDoubleExceptionReq, exception_req_accepted |-> ctrl_fsm_cs != DECODE)
// Only signal ready, allowing a new instruction into ID, if there is no exception request
// pending or it is done this cycle.
`ASSERT(IbexDontSkipExceptionReq,
id_in_ready_o |-> !exception_req_pending || exception_req_done)
// Once a PC set has been performed for an exception request there must not be any other
// excepting those to move into debug mode.
`ASSERT(IbexNoDoubleSpecialReqPCSet,
seen_exception_pc_set &&
!((ctrl_fsm_cs inside {DBG_TAKEN_IF, DBG_TAKEN_ID}) &&
(pc_mux_o == PC_EXC) && (exc_pc_mux_o == EXC_PC_DBD))
|-> !pc_set_o)
// When an exception request is done there must have been an appropriate PC set (either this
// cycle or a previous one).
`ASSERT(IbexSetExceptionPCOnSpecialReqIfExpected,
exception_req_pending && expect_exception_pc_set && exception_req_done |->
seen_exception_pc_set || exception_pc_set)
// If there's a pending exception req that doesn't need a PC set we must not see one
`ASSERT(IbexNoPCSetOnSpecialReqIfNotExpected,
exception_req_pending && !expect_exception_pc_set |-> ~pc_set_o)
`endif
`ifdef RVFI
// Workaround for internal verilator error when using hierarchical refers to calcuate this
// directly in ibex_core
logic rvfi_flush_next;
assign rvfi_flush_next = ctrl_fsm_ns == FLUSH;
`endif
endmodule |
module ibex_load_store_unit
(
input logic clk_i,
input logic rst_ni,
// data interface
output logic data_req_o,
input logic data_gnt_i,
input logic data_rvalid_i,
input logic data_err_i,
input logic data_pmp_err_i,
output logic [31:0] data_addr_o,
output logic data_we_o,
output logic [3:0] data_be_o,
output logic [31:0] data_wdata_o,
input logic [31:0] data_rdata_i,
// signals to/from ID/EX stage
input logic lsu_we_i, // write enable -> from ID/EX
input logic [1:0] lsu_type_i, // data type: word, half word, byte -> from ID/EX
input logic [31:0] lsu_wdata_i, // data to write to memory -> from ID/EX
input logic lsu_sign_ext_i, // sign extension -> from ID/EX
output logic [31:0] lsu_rdata_o, // requested data -> to ID/EX
output logic lsu_rdata_valid_o,
input logic lsu_req_i, // data request -> from ID/EX
input logic [31:0] adder_result_ex_i, // address computed in ALU -> from ID/EX
output logic addr_incr_req_o, // request address increment for
// misaligned accesses -> to ID/EX
output logic [31:0] addr_last_o, // address of last transaction -> to controller
// -> mtval
// -> AGU for misaligned accesses
output logic lsu_req_done_o, // Signals that data request is complete
// (only need to await final data
// response) -> to ID/EX
output logic lsu_resp_valid_o, // LSU has response from transaction -> to ID/EX
// exception signals
output logic load_err_o,
output logic store_err_o,
output logic busy_o,
output logic perf_load_o,
output logic perf_store_o
);
logic [31:0] data_addr;
logic [31:0] data_addr_w_aligned;
logic [31:0] addr_last_q, addr_last_d;
logic addr_update;
logic ctrl_update;
logic rdata_update;
logic [31:8] rdata_q;
logic [1:0] rdata_offset_q;
logic [1:0] data_type_q;
logic data_sign_ext_q;
logic data_we_q;
logic [1:0] data_offset; // mux control for data to be written to memory
logic [3:0] data_be;
logic [31:0] data_wdata;
logic [31:0] data_rdata_ext;
logic [31:0] rdata_w_ext; // word realignment for misaligned loads
logic [31:0] rdata_h_ext; // sign extension for half words
logic [31:0] rdata_b_ext; // sign extension for bytes
logic split_misaligned_access;
logic handle_misaligned_q, handle_misaligned_d; // high after receiving grant for first
// part of a misaligned access
logic pmp_err_q, pmp_err_d;
logic lsu_err_q, lsu_err_d;
logic data_or_pmp_err;
typedef enum logic [2:0] {
IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT,
WAIT_RVALID_MIS_GNTS_DONE
} ls_fsm_e;
ls_fsm_e ls_fsm_cs, ls_fsm_ns;
assign data_addr = adder_result_ex_i;
assign data_offset = data_addr[1:0];
///////////////////
// BE generation //
///////////////////
always_comb begin
unique case (lsu_type_i) // Data type 00 Word, 01 Half word, 11,10 byte
2'b00: begin // Writing a word
if (!handle_misaligned_q) begin // first part of potentially misaligned transaction
unique case (data_offset)
2'b00: data_be = 4'b1111;
2'b01: data_be = 4'b1110;
2'b10: data_be = 4'b1100;
2'b11: data_be = 4'b1000;
default: data_be = 4'b1111;
endcase // case (data_offset)
end else begin // second part of misaligned transaction
unique case (data_offset)
2'b00: data_be = 4'b0000; // this is not used, but included for completeness
2'b01: data_be = 4'b0001;
2'b10: data_be = 4'b0011;
2'b11: data_be = 4'b0111;
default: data_be = 4'b1111;
endcase // case (data_offset)
end
end
2'b01: begin // Writing a half word
if (!handle_misaligned_q) begin // first part of potentially misaligned transaction
unique case (data_offset)
2'b00: data_be = 4'b0011;
2'b01: data_be = 4'b0110;
2'b10: data_be = 4'b1100;
2'b11: data_be = 4'b1000;
default: data_be = 4'b1111;
endcase // case (data_offset)
end else begin // second part of misaligned transaction
data_be = 4'b0001;
end
end
2'b10,
2'b11: begin // Writing a byte
unique case (data_offset)
2'b00: data_be = 4'b0001;
2'b01: data_be = 4'b0010;
2'b10: data_be = 4'b0100;
2'b11: data_be = 4'b1000;
default: data_be = 4'b1111;
endcase // case (data_offset)
end
default: data_be = 4'b1111;
endcase // case (lsu_type_i)
end
/////////////////////
// WData alignment //
/////////////////////
// prepare data to be written to the memory
// we handle misaligned accesses, half word and byte accesses here
always_comb begin
unique case (data_offset)
2'b00: data_wdata = lsu_wdata_i[31:0];
2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]};
2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]};
2'b11: data_wdata = {lsu_wdata_i[ 7:0], lsu_wdata_i[31: 8]};
default: data_wdata = lsu_wdata_i[31:0];
endcase // case (data_offset)
end
/////////////////////
// RData alignment //
/////////////////////
// register for unaligned rdata
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rdata_q <= '0;
end else if (rdata_update) begin
rdata_q <= data_rdata_i[31:8];
end
end
// registers for transaction control
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rdata_offset_q <= 2'h0;
data_type_q <= 2'h0;
data_sign_ext_q <= 1'b0;
data_we_q <= 1'b0;
end else if (ctrl_update) begin
rdata_offset_q <= data_offset;
data_type_q <= lsu_type_i;
data_sign_ext_q <= lsu_sign_ext_i;
data_we_q <= lsu_we_i;
end
end
// Store last address for mtval + AGU for misaligned transactions. Do not update in case of
// errors, mtval needs the (first) failing address. Where an aligned access or the first half of
// a misaligned access sees an error provide the calculated access address. For the second half of
// a misaligned access provide the word aligned address of the second half.
assign addr_last_d = addr_incr_req_o ? data_addr_w_aligned : data_addr;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
addr_last_q <= '0;
end else if (addr_update) begin
addr_last_q <= addr_last_d;
end
end
// take care of misaligned words
always_comb begin
unique case (rdata_offset_q)
2'b00: rdata_w_ext = data_rdata_i[31:0];
2'b01: rdata_w_ext = {data_rdata_i[ 7:0], rdata_q[31:8]};
2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]};
2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]};
default: rdata_w_ext = data_rdata_i[31:0];
endcase
end
////////////////////
// Sign extension //
////////////////////
// sign extension for half words
always_comb begin
unique case (rdata_offset_q)
2'b00: begin
if (!data_sign_ext_q) begin
rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
end else begin
rdata_h_ext = {{16{data_rdata_i[15]}}, data_rdata_i[15:0]};
end
end
2'b01: begin
if (!data_sign_ext_q) begin
rdata_h_ext = {16'h0000, data_rdata_i[23:8]};
end else begin
rdata_h_ext = {{16{data_rdata_i[23]}}, data_rdata_i[23:8]};
end
end
2'b10: begin
if (!data_sign_ext_q) begin
rdata_h_ext = {16'h0000, data_rdata_i[31:16]};
end else begin
rdata_h_ext = {{16{data_rdata_i[31]}}, data_rdata_i[31:16]};
end
end
2'b11: begin
if (!data_sign_ext_q) begin
rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]};
end else begin
rdata_h_ext = {{16{data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]};
end
end
default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
endcase // case (rdata_offset_q)
end
// sign extension for bytes
always_comb begin
unique case (rdata_offset_q)
2'b00: begin
if (!data_sign_ext_q) begin
rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]};
end else begin
rdata_b_ext = {{24{data_rdata_i[7]}}, data_rdata_i[7:0]};
end
end
2'b01: begin
if (!data_sign_ext_q) begin
rdata_b_ext = {24'h00_0000, data_rdata_i[15:8]};
end else begin
rdata_b_ext = {{24{data_rdata_i[15]}}, data_rdata_i[15:8]};
end
end
2'b10: begin
if (!data_sign_ext_q) begin
rdata_b_ext = {24'h00_0000, data_rdata_i[23:16]};
end else begin
rdata_b_ext = {{24{data_rdata_i[23]}}, data_rdata_i[23:16]};
end
end
2'b11: begin
if (!data_sign_ext_q) begin
rdata_b_ext = {24'h00_0000, data_rdata_i[31:24]};
end else begin
rdata_b_ext = {{24{data_rdata_i[31]}}, data_rdata_i[31:24]};
end
end
default: rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]};
endcase // case (rdata_offset_q)
end
// select word, half word or byte sign extended version
always_comb begin
unique case (data_type_q)
2'b00: data_rdata_ext = rdata_w_ext;
2'b01: data_rdata_ext = rdata_h_ext;
2'b10,2'b11: data_rdata_ext = rdata_b_ext;
default: data_rdata_ext = rdata_w_ext;
endcase // case (data_type_q)
end
/////////////
// LSU FSM //
/////////////
// check for misaligned accesses that need to be split into two word-aligned accesses
assign split_misaligned_access =
((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access
((lsu_type_i == 2'b01) && (data_offset == 2'b11)); // misaligned half-word access
// FSM
always_comb begin
ls_fsm_ns = ls_fsm_cs;
data_req_o = 1'b0;
addr_incr_req_o = 1'b0;
handle_misaligned_d = handle_misaligned_q;
pmp_err_d = pmp_err_q;
lsu_err_d = lsu_err_q;
addr_update = 1'b0;
ctrl_update = 1'b0;
rdata_update = 1'b0;
perf_load_o = 1'b0;
perf_store_o = 1'b0;
unique case (ls_fsm_cs)
IDLE: begin
pmp_err_d = 1'b0;
if (lsu_req_i) begin
data_req_o = 1'b1;
pmp_err_d = data_pmp_err_i;
lsu_err_d = 1'b0;
perf_load_o = ~lsu_we_i;
perf_store_o = lsu_we_i;
if (data_gnt_i) begin
ctrl_update = 1'b1;
addr_update = 1'b1;
handle_misaligned_d = split_misaligned_access;
ls_fsm_ns = split_misaligned_access ? WAIT_RVALID_MIS : IDLE;
end else begin
ls_fsm_ns = split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT;
end
end
end
WAIT_GNT_MIS: begin
data_req_o = 1'b1;
// data_pmp_err_i is valid during the address phase of a request. An error will block the
// external request and so a data_gnt_i might never be signalled. The registered version
// pmp_err_q is only updated for new address phases and so can be used in WAIT_GNT* and
// WAIT_RVALID* states
if (data_gnt_i || pmp_err_q) begin
addr_update = 1'b1;
ctrl_update = 1'b1;
handle_misaligned_d = 1'b1;
ls_fsm_ns = WAIT_RVALID_MIS;
end
end
WAIT_RVALID_MIS: begin
// push out second request
data_req_o = 1'b1;
// tell ID/EX stage to update the address
addr_incr_req_o = 1'b1;
// first part rvalid is received, or gets a PMP error
if (data_rvalid_i || pmp_err_q) begin
// Update the PMP error for the second part
pmp_err_d = data_pmp_err_i;
// Record the error status of the first part
lsu_err_d = data_err_i | pmp_err_q;
// Capture the first rdata for loads
rdata_update = ~data_we_q;
// If already granted, wait for second rvalid
ls_fsm_ns = data_gnt_i ? IDLE : WAIT_GNT;
// Update the address for the second part, if no error
addr_update = data_gnt_i & ~(data_err_i | pmp_err_q);
// clear handle_misaligned if second request is granted
handle_misaligned_d = ~data_gnt_i;
end else begin
// first part rvalid is NOT received
if (data_gnt_i) begin
// second grant is received
ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE;
handle_misaligned_d = 1'b0;
end
end
end
WAIT_GNT: begin
// tell ID/EX stage to update the address
addr_incr_req_o = handle_misaligned_q;
data_req_o = 1'b1;
if (data_gnt_i || pmp_err_q) begin
ctrl_update = 1'b1;
// Update the address, unless there was an error
addr_update = ~lsu_err_q;
ls_fsm_ns = IDLE;
handle_misaligned_d = 1'b0;
end
end
WAIT_RVALID_MIS_GNTS_DONE: begin
// tell ID/EX stage to update the address (to make sure the
// second address can be captured correctly for mtval and PMP checking)
addr_incr_req_o = 1'b1;
// Wait for the first rvalid, second request is already granted
if (data_rvalid_i) begin
// Update the pmp error for the second part
pmp_err_d = data_pmp_err_i;
// The first part cannot see a PMP error in this state
lsu_err_d = data_err_i;
// Now we can update the address for the second part if no error
addr_update = ~data_err_i;
// Capture the first rdata for loads
rdata_update = ~data_we_q;
// Wait for second rvalid
ls_fsm_ns = IDLE;
end
end
default: begin
ls_fsm_ns = IDLE;
end
endcase
end
assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE);
// registers for FSM
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
ls_fsm_cs <= IDLE;
handle_misaligned_q <= '0;
pmp_err_q <= '0;
lsu_err_q <= '0;
end else begin
ls_fsm_cs <= ls_fsm_ns;
handle_misaligned_q <= handle_misaligned_d;
pmp_err_q <= pmp_err_d;
lsu_err_q <= lsu_err_d;
end
end
/////////////
// Outputs //
/////////////
assign data_or_pmp_err = lsu_err_q | data_err_i | pmp_err_q;
assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE);
assign lsu_rdata_valid_o = (ls_fsm_cs == IDLE) & data_rvalid_i & ~data_or_pmp_err & ~data_we_q;
// output to register file
assign lsu_rdata_o = data_rdata_ext;
// output data address must be word aligned
assign data_addr_w_aligned = {data_addr[31:2], 2'b00};
// output to data interface
assign data_addr_o = data_addr_w_aligned;
assign data_wdata_o = data_wdata;
assign data_we_o = lsu_we_i;
assign data_be_o = data_be;
// output to ID stage: mtval + AGU for misaligned transactions
assign addr_last_o = addr_last_q;
// Signal a load or store error depending on the transaction type outstanding
assign load_err_o = data_or_pmp_err & ~data_we_q & lsu_resp_valid_o;
assign store_err_o = data_or_pmp_err & data_we_q & lsu_resp_valid_o;
assign busy_o = (ls_fsm_cs != IDLE);
//////////
// FCOV //
//////////
`DV_FCOV_SIGNAL(logic, ls_error_exception, (load_err_o | store_err_o) & ~pmp_err_q)
`DV_FCOV_SIGNAL(logic, ls_pmp_exception, (load_err_o | store_err_o) & pmp_err_q)
////////////////
// Assertions //
////////////////
// Selectors must be known/valid.
`ASSERT(IbexDataTypeKnown, (lsu_req_i | busy_o) |-> !$isunknown(lsu_type_i))
`ASSERT(IbexDataOffsetKnown, (lsu_req_i | busy_o) |-> !$isunknown(data_offset))
`ASSERT_KNOWN(IbexRDataOffsetQKnown, rdata_offset_q)
`ASSERT_KNOWN(IbexDataTypeQKnown, data_type_q)
`ASSERT(IbexLsuStateValid, ls_fsm_cs inside {
IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT,
WAIT_RVALID_MIS_GNTS_DONE})
// Address must not contain X when request is sent.
`ASSERT(IbexDataAddrUnknown, data_req_o |-> !$isunknown(data_addr_o))
// Address must be word aligned when request is sent.
`ASSERT(IbexDataAddrUnaligned, data_req_o |-> (data_addr_o[1:0] == 2'b00))
endmodule |
module ibex_if_stage import ibex_pkg::*; #(
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808,
parameter bit DummyInstructions = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
parameter int unsigned BusSizeECC = BUS_SIZE,
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
parameter bit PCIncrCheck = 1'b0,
parameter bit ResetAll = 1'b0,
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
parameter bit BranchPredictor = 1'b0
) (
input logic clk_i,
input logic rst_ni,
input logic [31:0] boot_addr_i, // also used for mtvec
input logic req_i, // instruction request control
// instruction cache interface
output logic instr_req_o,
output logic [31:0] instr_addr_o,
input logic instr_gnt_i,
input logic instr_rvalid_i,
input logic [31:0] instr_rdata_i,
input logic instr_err_i,
input logic instr_pmp_err_i,
// ICache RAM IO
output logic [IC_NUM_WAYS-1:0] ic_tag_req_o,
output logic ic_tag_write_o,
output logic [IC_INDEX_W-1:0] ic_tag_addr_o,
output logic [TagSizeECC-1:0] ic_tag_wdata_o,
input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
output logic [IC_NUM_WAYS-1:0] ic_data_req_o,
output logic ic_data_write_o,
output logic [IC_INDEX_W-1:0] ic_data_addr_o,
output logic [LineSizeECC-1:0] ic_data_wdata_o,
input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
// output of ID stage
output logic instr_valid_id_o, // instr in IF-ID is valid
output logic instr_new_id_o, // instr in IF-ID is new
output logic [31:0] instr_rdata_id_o, // instr for ID stage
output logic [31:0] instr_rdata_alu_id_o, // replicated instr for ID stage
// to reduce fan-out
output logic [15:0] instr_rdata_c_id_o, // compressed instr for ID stage
// (mtval), meaningful only if
// instr_is_compressed_id_o = 1'b1
output logic instr_is_compressed_id_o, // compressed decoder thinks this
// is a compressed instr
output logic instr_bp_taken_o, // instruction was predicted to be
// a taken branch
output logic instr_fetch_err_o, // bus error on fetch
output logic instr_fetch_err_plus2_o, // bus error misaligned
output logic illegal_c_insn_id_o, // compressed decoder thinks this
// is an invalid instr
output logic dummy_instr_id_o, // Instruction is a dummy
output logic [31:0] pc_if_o,
output logic [31:0] pc_id_o,
// control signals
input logic instr_valid_clear_i, // clear instr valid bit in IF-ID
input logic pc_set_i, // set the PC to a new value
input logic pc_set_spec_i,
input pc_sel_e pc_mux_i, // selector for PC multiplexer
input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was
// mispredicted (predicted taken)
input exc_pc_sel_e exc_pc_mux_i, // selects ISR address
input exc_cause_e exc_cause, // selects ISR address for
// vectorized interrupt lines
input logic dummy_instr_en_i,
input logic [2:0] dummy_instr_mask_i,
input logic dummy_instr_seed_en_i,
input logic [31:0] dummy_instr_seed_i,
input logic icache_enable_i,
input logic icache_inval_i,
// jump and branch target
input logic [31:0] branch_target_ex_i, // branch/jump target address
// CSRs
input logic [31:0] csr_mepc_i, // PC to restore after handling
// the interrupt/exception
input logic [31:0] csr_depc_i, // PC to restore after handling
// the debug request
input logic [31:0] csr_mtvec_i, // base PC to jump to on exception
output logic csr_mtvec_init_o, // tell CS regfile to init mtvec
// pipeline stall
input logic id_in_ready_i, // ID stage is ready for new instr
// misc signals
output logic pc_mismatch_alert_o,
output logic if_busy_o // IF stage is busy fetching instr
);
logic instr_valid_id_d, instr_valid_id_q;
logic instr_new_id_d, instr_new_id_q;
// prefetch buffer related signals
logic prefetch_busy;
logic branch_req;
logic branch_spec;
logic predicted_branch;
logic [31:0] fetch_addr_n;
logic unused_fetch_addr_n0;
logic fetch_valid;
logic fetch_ready;
logic [31:0] fetch_rdata;
logic [31:0] fetch_addr;
logic fetch_err;
logic fetch_err_plus2;
logic if_instr_valid;
logic [31:0] if_instr_rdata;
logic [31:0] if_instr_addr;
logic if_instr_err;
logic [31:0] exc_pc;
logic [5:0] irq_id;
logic unused_irq_bit;
logic if_id_pipe_reg_we; // IF-ID pipeline reg write enable
// Dummy instruction signals
logic stall_dummy_instr;
logic [31:0] instr_out;
logic instr_is_compressed_out;
logic illegal_c_instr_out;
logic instr_err_out;
logic predict_branch_taken;
logic [31:0] predict_branch_pc;
ibex_pkg::pc_sel_e pc_mux_internal;
logic [7:0] unused_boot_addr;
logic [7:0] unused_csr_mtvec;
assign unused_boot_addr = boot_addr_i[7:0];
assign unused_csr_mtvec = csr_mtvec_i[7:0];
// extract interrupt ID from exception cause
assign irq_id = {exc_cause};
assign unused_irq_bit = irq_id[5]; // MSB distinguishes interrupts from exceptions
// exception PC selection mux
always_comb begin : exc_pc_mux
unique case (exc_pc_mux_i)
EXC_PC_EXC: exc_pc = { csr_mtvec_i[31:8], 8'h00 };
EXC_PC_IRQ: exc_pc = { csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00 };
EXC_PC_DBD: exc_pc = DmHaltAddr;
EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr;
default: exc_pc = { csr_mtvec_i[31:8], 8'h00 };
endcase
end
// The Branch predictor can provide a new PC which is internal to if_stage. Only override the mux
// select to choose this if the core isn't already trying to set a PC.
assign pc_mux_internal =
(BranchPredictor && predict_branch_taken && !pc_set_i) ? PC_BP : pc_mux_i;
// fetch address selection mux
always_comb begin : fetch_addr_mux
unique case (pc_mux_internal)
PC_BOOT: fetch_addr_n = { boot_addr_i[31:8], 8'h80 };
PC_JUMP: fetch_addr_n = branch_target_ex_i;
PC_EXC: fetch_addr_n = exc_pc; // set PC to exception handler
PC_ERET: fetch_addr_n = csr_mepc_i; // restore PC when returning from EXC
PC_DRET: fetch_addr_n = csr_depc_i;
// Without branch predictor will never get pc_mux_internal == PC_BP. We still handle no branch
// predictor case here to ensure redundant mux logic isn't synthesised.
PC_BP: fetch_addr_n = BranchPredictor ? predict_branch_pc : { boot_addr_i[31:8], 8'h80 };
default: fetch_addr_n = { boot_addr_i[31:8], 8'h80 };
endcase
end
// tell CS register file to initialize mtvec on boot
assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i;
if (ICache) begin : gen_icache
// Full I-Cache option
ibex_icache #(
.BranchPredictor (BranchPredictor),
.ICacheECC (ICacheECC),
.ResetAll (ResetAll),
.BusSizeECC (BusSizeECC),
.TagSizeECC (TagSizeECC),
.LineSizeECC (LineSizeECC)
) icache_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req_i ),
.branch_i ( branch_req ),
.branch_spec_i ( branch_spec ),
.predicted_branch_i ( predicted_branch ),
.branch_mispredict_i ( nt_branch_mispredict_i ),
.addr_i ( {fetch_addr_n[31:1], 1'b0} ),
.ready_i ( fetch_ready ),
.valid_o ( fetch_valid ),
.rdata_o ( fetch_rdata ),
.addr_o ( fetch_addr ),
.err_o ( fetch_err ),
.err_plus2_o ( fetch_err_plus2 ),
.instr_req_o ( instr_req_o ),
.instr_addr_o ( instr_addr_o ),
.instr_gnt_i ( instr_gnt_i ),
.instr_rvalid_i ( instr_rvalid_i ),
.instr_rdata_i ( instr_rdata_i ),
.instr_err_i ( instr_err_i ),
.instr_pmp_err_i ( instr_pmp_err_i ),
.ic_tag_req_o ( ic_tag_req_o ),
.ic_tag_write_o ( ic_tag_write_o ),
.ic_tag_addr_o ( ic_tag_addr_o ),
.ic_tag_wdata_o ( ic_tag_wdata_o ),
.ic_tag_rdata_i ( ic_tag_rdata_i ),
.ic_data_req_o ( ic_data_req_o ),
.ic_data_write_o ( ic_data_write_o ),
.ic_data_addr_o ( ic_data_addr_o ),
.ic_data_wdata_o ( ic_data_wdata_o ),
.ic_data_rdata_i ( ic_data_rdata_i ),
.icache_enable_i ( icache_enable_i ),
.icache_inval_i ( icache_inval_i ),
.busy_o ( prefetch_busy )
);
end else begin : gen_prefetch_buffer
// prefetch buffer, caches a fixed number of instructions
ibex_prefetch_buffer #(
.BranchPredictor (BranchPredictor),
.ResetAll (ResetAll)
) prefetch_buffer_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req_i ),
.branch_i ( branch_req ),
.branch_spec_i ( branch_spec ),
.predicted_branch_i ( predicted_branch ),
.branch_mispredict_i ( nt_branch_mispredict_i ),
.addr_i ( {fetch_addr_n[31:1], 1'b0} ),
.ready_i ( fetch_ready ),
.valid_o ( fetch_valid ),
.rdata_o ( fetch_rdata ),
.addr_o ( fetch_addr ),
.err_o ( fetch_err ),
.err_plus2_o ( fetch_err_plus2 ),
.instr_req_o ( instr_req_o ),
.instr_addr_o ( instr_addr_o ),
.instr_gnt_i ( instr_gnt_i ),
.instr_rvalid_i ( instr_rvalid_i ),
.instr_rdata_i ( instr_rdata_i ),
.instr_err_i ( instr_err_i ),
.instr_pmp_err_i ( instr_pmp_err_i ),
.busy_o ( prefetch_busy )
);
// ICache tieoffs
logic unused_icen, unused_icinv;
logic [TagSizeECC-1:0] unused_tag_ram_input [IC_NUM_WAYS];
logic [LineSizeECC-1:0] unused_data_ram_input [IC_NUM_WAYS];
assign unused_icen = icache_enable_i;
assign unused_icinv = icache_inval_i;
assign unused_tag_ram_input = ic_tag_rdata_i;
assign unused_data_ram_input = ic_data_rdata_i;
assign ic_tag_req_o = 'b0;
assign ic_tag_write_o = 'b0;
assign ic_tag_addr_o = 'b0;
assign ic_tag_wdata_o = 'b0;
assign ic_data_req_o = 'b0;
assign ic_data_write_o = 'b0;
assign ic_data_addr_o = 'b0;
assign ic_data_wdata_o = 'b0;
end
assign unused_fetch_addr_n0 = fetch_addr_n[0];
assign branch_req = pc_set_i | predict_branch_taken;
assign branch_spec = pc_set_spec_i | predict_branch_taken;
assign pc_if_o = if_instr_addr;
assign if_busy_o = prefetch_busy;
// compressed instruction decoding, or more precisely compressed instruction
// expander
//
// since it does not matter where we decompress instructions, we do it here
// to ease timing closure
logic [31:0] instr_decompressed;
logic illegal_c_insn;
logic instr_is_compressed;
ibex_compressed_decoder compressed_decoder_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.valid_i (fetch_valid & ~fetch_err),
.instr_i (if_instr_rdata),
.instr_o (instr_decompressed),
.is_compressed_o(instr_is_compressed),
.illegal_instr_o(illegal_c_insn)
);
// Dummy instruction insertion
if (DummyInstructions) begin : gen_dummy_instr
logic insert_dummy_instr;
logic [31:0] dummy_instr_data;
ibex_dummy_instr #(
.RndCnstLfsrSeed (RndCnstLfsrSeed),
.RndCnstLfsrPerm (RndCnstLfsrPerm)
) dummy_instr_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.dummy_instr_en_i (dummy_instr_en_i),
.dummy_instr_mask_i (dummy_instr_mask_i),
.dummy_instr_seed_en_i(dummy_instr_seed_en_i),
.dummy_instr_seed_i (dummy_instr_seed_i),
.fetch_valid_i (fetch_valid),
.id_in_ready_i (id_in_ready_i),
.insert_dummy_instr_o (insert_dummy_instr),
.dummy_instr_data_o (dummy_instr_data)
);
// Mux between actual instructions and dummy instructions
assign instr_out = insert_dummy_instr ? dummy_instr_data : instr_decompressed;
assign instr_is_compressed_out = insert_dummy_instr ? 1'b0 : instr_is_compressed;
assign illegal_c_instr_out = insert_dummy_instr ? 1'b0 : illegal_c_insn;
assign instr_err_out = insert_dummy_instr ? 1'b0 : if_instr_err;
// Stall the IF stage if we insert a dummy instruction. The dummy will execute between whatever
// is currently in the ID stage and whatever is valid from the prefetch buffer this cycle. The
// PC of the dummy instruction will match whatever is next from the prefetch buffer.
assign stall_dummy_instr = insert_dummy_instr;
// Register the dummy instruction indication into the ID stage
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
dummy_instr_id_o <= 1'b0;
end else if (if_id_pipe_reg_we) begin
dummy_instr_id_o <= insert_dummy_instr;
end
end
end else begin : gen_no_dummy_instr
logic unused_dummy_en;
logic [2:0] unused_dummy_mask;
logic unused_dummy_seed_en;
logic [31:0] unused_dummy_seed;
assign unused_dummy_en = dummy_instr_en_i;
assign unused_dummy_mask = dummy_instr_mask_i;
assign unused_dummy_seed_en = dummy_instr_seed_en_i;
assign unused_dummy_seed = dummy_instr_seed_i;
assign instr_out = instr_decompressed;
assign instr_is_compressed_out = instr_is_compressed;
assign illegal_c_instr_out = illegal_c_insn;
assign instr_err_out = if_instr_err;
assign stall_dummy_instr = 1'b0;
assign dummy_instr_id_o = 1'b0;
end
// The ID stage becomes valid as soon as any instruction is registered in the ID stage flops.
// Note that the current instruction is squashed by the incoming pc_set_i signal.
// Valid is held until it is explicitly cleared (due to an instruction completing or an exception)
assign instr_valid_id_d = (if_instr_valid & id_in_ready_i & ~pc_set_i) |
(instr_valid_id_q & ~instr_valid_clear_i);
assign instr_new_id_d = if_instr_valid & id_in_ready_i;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
instr_valid_id_q <= 1'b0;
instr_new_id_q <= 1'b0;
end else begin
instr_valid_id_q <= instr_valid_id_d;
instr_new_id_q <= instr_new_id_d;
end
end
assign instr_valid_id_o = instr_valid_id_q;
// Signal when a new instruction enters the ID stage (only used for RVFI signalling).
assign instr_new_id_o = instr_new_id_q;
// IF-ID pipeline registers, frozen when the ID stage is stalled
assign if_id_pipe_reg_we = instr_new_id_d;
if (ResetAll) begin : g_instr_rdata_ra
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
instr_rdata_id_o <= '0;
instr_rdata_alu_id_o <= '0;
instr_fetch_err_o <= '0;
instr_fetch_err_plus2_o <= '0;
instr_rdata_c_id_o <= '0;
instr_is_compressed_id_o <= '0;
illegal_c_insn_id_o <= '0;
pc_id_o <= '0;
end else if (if_id_pipe_reg_we) begin
instr_rdata_id_o <= instr_out;
// To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
instr_rdata_alu_id_o <= instr_out;
instr_fetch_err_o <= instr_err_out;
instr_fetch_err_plus2_o <= fetch_err_plus2;
instr_rdata_c_id_o <= if_instr_rdata[15:0];
instr_is_compressed_id_o <= instr_is_compressed_out;
illegal_c_insn_id_o <= illegal_c_instr_out;
pc_id_o <= pc_if_o;
end
end
end else begin : g_instr_rdata_nr
always_ff @(posedge clk_i) begin
if (if_id_pipe_reg_we) begin
instr_rdata_id_o <= instr_out;
// To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
instr_rdata_alu_id_o <= instr_out;
instr_fetch_err_o <= instr_err_out;
instr_fetch_err_plus2_o <= fetch_err_plus2;
instr_rdata_c_id_o <= if_instr_rdata[15:0];
instr_is_compressed_id_o <= instr_is_compressed_out;
illegal_c_insn_id_o <= illegal_c_instr_out;
pc_id_o <= pc_if_o;
end
end
end
// Check for expected increments of the PC when security hardening enabled
if (PCIncrCheck) begin : g_secure_pc
logic [31:0] prev_instr_addr_incr;
logic prev_instr_seq_q, prev_instr_seq_d;
// Do not check for sequential increase after a branch, jump, exception, interrupt or debug
// request, all of which will set branch_req. Also do not check after reset or for dummys.
assign prev_instr_seq_d = (prev_instr_seq_q | instr_new_id_d) &
~branch_req & ~stall_dummy_instr;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
prev_instr_seq_q <= 1'b0;
end else begin
prev_instr_seq_q <= prev_instr_seq_d;
end
end
assign prev_instr_addr_incr = pc_id_o + ((instr_is_compressed_id_o && !instr_fetch_err_o) ?
32'd2 : 32'd4);
// Check that the address equals the previous address +2/+4
assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr);
end else begin : g_no_secure_pc
assign pc_mismatch_alert_o = 1'b0;
end
if (BranchPredictor) begin : g_branch_predictor
logic [31:0] instr_skid_data_q;
logic [31:0] instr_skid_addr_q;
logic instr_skid_bp_taken_q;
logic instr_skid_valid_q, instr_skid_valid_d;
logic instr_skid_en;
logic instr_bp_taken_q, instr_bp_taken_d;
logic predict_branch_taken_raw;
// ID stages needs to know if branch was predicted taken so it can signal mispredicts
if (ResetAll) begin : g_bp_taken_ra
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
instr_bp_taken_q <= '0;
end else if (if_id_pipe_reg_we) begin
instr_bp_taken_q <= instr_bp_taken_d;
end
end
end else begin : g_bp_taken_nr
always_ff @(posedge clk_i) begin
if (if_id_pipe_reg_we) begin
instr_bp_taken_q <= instr_bp_taken_d;
end
end
end
// When branch prediction is enabled a skid buffer between the IF and ID/EX stage is introduced.
// If an instruction in IF is predicted to be a taken branch and ID/EX is not ready the
// instruction in IF is moved to the skid buffer which becomes the output of the IF stage until
// the ID/EX stage accepts the instruction. The skid buffer is required as otherwise the ID/EX
// ready signal is coupled to the instr_req_o output which produces a feedthrough path from
// data_gnt_i -> instr_req_o (which needs to be avoided as for some interconnects this will
// result in a combinational loop).
assign instr_skid_en = predicted_branch & ~id_in_ready_i & ~instr_skid_valid_q;
assign instr_skid_valid_d = (instr_skid_valid_q & ~id_in_ready_i & ~stall_dummy_instr) |
instr_skid_en;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
instr_skid_valid_q <= 1'b0;
end else begin
instr_skid_valid_q <= instr_skid_valid_d;
end
end
if (ResetAll) begin : g_instr_skid_ra
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
instr_skid_bp_taken_q <= '0;
instr_skid_data_q <= '0;
instr_skid_addr_q <= '0;
end else if (instr_skid_en) begin
instr_skid_bp_taken_q <= predict_branch_taken;
instr_skid_data_q <= fetch_rdata;
instr_skid_addr_q <= fetch_addr;
end
end
end else begin : g_instr_skid_nr
always_ff @(posedge clk_i) begin
if (instr_skid_en) begin
instr_skid_bp_taken_q <= predict_branch_taken;
instr_skid_data_q <= fetch_rdata;
instr_skid_addr_q <= fetch_addr;
end
end
end
ibex_branch_predict branch_predict_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.fetch_rdata_i(fetch_rdata),
.fetch_pc_i (fetch_addr),
.fetch_valid_i(fetch_valid),
.predict_branch_taken_o(predict_branch_taken_raw),
.predict_branch_pc_o (predict_branch_pc)
);
// If there is an instruction in the skid buffer there must be no branch prediction.
// Instructions are only placed in the skid after they have been predicted to be a taken branch
// so with the skid valid any prediction has already occurred.
// Do not branch predict on instruction errors.
assign predict_branch_taken = predict_branch_taken_raw & ~instr_skid_valid_q & ~fetch_err;
// pc_set_i takes precendence over branch prediction
assign predicted_branch = predict_branch_taken & ~pc_set_i;
assign if_instr_valid = fetch_valid | instr_skid_valid_q;
assign if_instr_rdata = instr_skid_valid_q ? instr_skid_data_q : fetch_rdata;
assign if_instr_addr = instr_skid_valid_q ? instr_skid_addr_q : fetch_addr;
// Don't branch predict on instruction error so only instructions without errors end up in the
// skid buffer.
assign if_instr_err = ~instr_skid_valid_q & fetch_err;
assign instr_bp_taken_d = instr_skid_valid_q ? instr_skid_bp_taken_q : predict_branch_taken;
assign fetch_ready = id_in_ready_i & ~stall_dummy_instr & ~instr_skid_valid_q;
assign instr_bp_taken_o = instr_bp_taken_q;
`ASSERT(NoPredictSkid, instr_skid_valid_q |-> ~predict_branch_taken)
`ASSERT(NoPredictIllegal, predict_branch_taken |-> ~illegal_c_insn)
end else begin : g_no_branch_predictor
assign instr_bp_taken_o = 1'b0;
assign predict_branch_taken = 1'b0;
assign predicted_branch = 1'b0;
assign predict_branch_pc = 32'b0;
assign if_instr_valid = fetch_valid;
assign if_instr_rdata = fetch_rdata;
assign if_instr_addr = fetch_addr;
assign if_instr_err = fetch_err;
assign fetch_ready = id_in_ready_i & ~stall_dummy_instr;
end
////////////////
// Assertions //
////////////////
// Selectors must be known/valid.
`ASSERT_KNOWN(IbexExcPcMuxKnown, exc_pc_mux_i)
if (BranchPredictor) begin : g_branch_predictor_asserts
`ASSERT_IF(IbexPcMuxValid, pc_mux_internal inside {
PC_BOOT,
PC_JUMP,
PC_EXC,
PC_ERET,
PC_DRET,
PC_BP},
pc_set_i)
`ifdef INC_ASSERT
/**
* Checks for branch prediction interface to fetch_fifo/icache
*
* The interface has two signals:
* - predicted_branch_i: When set with a branch (branch_i) indicates the branch is a predicted
* one, it should be ignored when a branch_i isn't set.
* - branch_mispredict_i: Indicates the previously predicted branch was mis-predicted and
* execution should resume with the not-taken side of the branch (i.e. continue with the PC
* that followed the predicted branch). This must be raised before the instruction that is
* made available following a predicted branch is accepted (Following a cycle with branch_i
* & predicted_branch_i, branch_mispredict_i can only be asserted before or on the same cycle
* as seeing fetch_valid & fetch_ready). When branch_mispredict_i is asserted, fetch_valid may
* be asserted in response. If fetch_valid is asserted on the same cycle as
* branch_mispredict_i this indicates the fetch_fifo/icache has the not-taken side of the
* branch immediately ready for use
*/
logic predicted_branch_live_q, predicted_branch_live_d;
logic [31:0] predicted_branch_nt_pc_q, predicted_branch_nt_pc_d;
logic [31:0] awaiting_instr_after_mispredict_q, awaiting_instr_after_mispredict_d;
logic [31:0] next_pc;
logic mispredicted, mispredicted_d, mispredicted_q;
assign next_pc = fetch_addr + (instr_is_compressed_out ? 32'd2 : 32'd4);
always_comb begin
predicted_branch_live_d = predicted_branch_live_q;
mispredicted_d = mispredicted_q;
if (branch_req & predicted_branch) begin
predicted_branch_live_d = 1'b1;
mispredicted_d = 1'b0;
end else if (predicted_branch_live_q) begin
if (fetch_valid & fetch_ready) begin
predicted_branch_live_d = 1'b0;
end else if (nt_branch_mispredict_i) begin
mispredicted_d = 1'b1;
end
end
end
always @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
predicted_branch_live_q <= 1'b0;
mispredicted_q <= 1'b0;
end else begin
predicted_branch_live_q <= predicted_branch_live_d;
mispredicted_q <= mispredicted_d;
end
end
always @(posedge clk_i) begin
if (branch_req & predicted_branch) begin
predicted_branch_nt_pc_q <= next_pc;
end
end
// Must only see mispredict after we've performed a predicted branch but before we've accepted
// any instruction (with fetch_ready & fetch_valid) that follows that predicted branch.
`ASSERT(MispredictOnlyImmediatelyAfterPredictedBranch,
nt_branch_mispredict_i |-> predicted_branch_live_q)
// Check that on mispredict we get the correct PC for the non-taken side of the branch when
// prefetch buffer/icache makes that PC available.
`ASSERT(CorrectPCOnMispredict,
predicted_branch_live_q & mispredicted_d & fetch_valid |->
fetch_addr == predicted_branch_nt_pc_q)
// Must not signal mispredict over multiple cycles but it's possible to have back to back
// mispredicts for different branches (core signals mispredict, prefetch buffer/icache immediate
// has not-taken side of the mispredicted branch ready, which itself is a predicted branch,
// following cycle core signal that that branch has mispredicted).
`ASSERT(MispredictSingleCycle,
nt_branch_mispredict_i & ~(fetch_valid & fetch_ready) |=> ~nt_branch_mispredict_i)
// Note that we should never see a mispredict and an incoming branch on the same cycle.
// The mispredict also cancels any predicted branch so overall branch_req must be low.
`ASSERT(NoMispredBranch, nt_branch_mispredict_i |-> ~branch_req)
`endif
end else begin : g_no_branch_predictor_asserts
`ASSERT_IF(IbexPcMuxValid, pc_mux_internal inside {
PC_BOOT,
PC_JUMP,
PC_EXC,
PC_ERET,
PC_DRET},
pc_set_i)
end
// Boot address must be aligned to 256 bytes.
`ASSERT(IbexBootAddrUnaligned, boot_addr_i[7:0] == 8'h00)
// Address must not contain X when request is sent.
`ASSERT(IbexInstrAddrUnknown, instr_req_o |-> !$isunknown(instr_addr_o))
// Address must be word aligned when request is sent.
`ASSERT(IbexInstrAddrUnaligned, instr_req_o |-> (instr_addr_o[1:0] == 2'b00))
endmodule |
module ibex_multdiv_slow
(
input logic clk_i,
input logic rst_ni,
input logic mult_en_i, // dynamic enable signal, for FSM control
input logic div_en_i, // dynamic enable signal, for FSM control
input logic mult_sel_i, // static decoder output, for data muxes
input logic div_sel_i, // static decoder output, for data muxes
input ibex_pkg::md_op_e operator_i,
input logic [1:0] signed_mode_i,
input logic [31:0] op_a_i,
input logic [31:0] op_b_i,
input logic [33:0] alu_adder_ext_i,
input logic [31:0] alu_adder_i,
input logic equal_to_zero_i,
input logic data_ind_timing_i,
output logic [32:0] alu_operand_a_o,
output logic [32:0] alu_operand_b_o,
input logic [33:0] imd_val_q_i[2],
output logic [33:0] imd_val_d_o[2],
output logic [1:0] imd_val_we_o,
input logic multdiv_ready_id_i,
output logic [31:0] multdiv_result_o,
output logic valid_o
);
import ibex_pkg::*;
typedef enum logic [2:0] {
MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
} md_fsm_e;
md_fsm_e md_state_q, md_state_d;
logic [32:0] accum_window_q, accum_window_d;
logic unused_imd_val0;
logic [ 1:0] unused_imd_val1;
logic [32:0] res_adder_l;
logic [32:0] res_adder_h;
logic [ 4:0] multdiv_count_q, multdiv_count_d;
logic [32:0] op_b_shift_q, op_b_shift_d;
logic [32:0] op_a_shift_q, op_a_shift_d;
logic [32:0] op_a_ext, op_b_ext;
logic [32:0] one_shift;
logic [32:0] op_a_bw_pp, op_a_bw_last_pp;
logic [31:0] b_0;
logic sign_a, sign_b;
logic [32:0] next_quotient;
logic [31:0] next_remainder;
logic [31:0] op_numerator_q, op_numerator_d;
logic is_greater_equal;
logic div_change_sign, rem_change_sign;
logic div_by_zero_d, div_by_zero_q;
logic multdiv_hold;
logic multdiv_en;
// (accum_window_q + op_a_shift_q)
assign res_adder_l = alu_adder_ext_i[32:0];
// (accum_window_q + op_a_shift_q)>>1
assign res_adder_h = alu_adder_ext_i[33:1];
/////////////////////
// ALU Operand MUX //
/////////////////////
// Intermediate value register shared with ALU
assign imd_val_d_o[0] = {1'b0,accum_window_d};
assign imd_val_we_o[0] = ~multdiv_hold;
assign accum_window_q = imd_val_q_i[0][32:0];
assign unused_imd_val0 = imd_val_q_i[0][33];
assign imd_val_d_o[1] = {2'b00, op_numerator_d};
assign imd_val_we_o[1] = multdiv_en;
assign op_numerator_q = imd_val_q_i[1][31:0];
assign unused_imd_val1 = imd_val_q_i[1][33:32];
always_comb begin
alu_operand_a_o = accum_window_q;
unique case (operator_i)
MD_OP_MULL: begin
alu_operand_b_o = op_a_bw_pp;
end
MD_OP_MULH: begin
alu_operand_b_o = (md_state_q == MD_LAST) ? op_a_bw_last_pp : op_a_bw_pp;
end
MD_OP_DIV,
MD_OP_REM: begin
unique case (md_state_q)
MD_IDLE: begin
// 0 - B = 0 iff B == 0
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~op_b_i, 1'b1};
end
MD_ABS_A: begin
// ABS(A) = 0 - A
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~op_a_i, 1'b1};
end
MD_ABS_B: begin
// ABS(B) = 0 - B
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~op_b_i, 1'b1};
end
MD_CHANGE_SIGN: begin
// ABS(Quotient) = 0 - Quotient (or Reminder)
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~accum_window_q[31:0], 1'b1};
end
default: begin
// Division
alu_operand_a_o = {accum_window_q[31:0], 1'b1}; // it contains the remainder
alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; // -denominator two's compliment
end
endcase
end
default: begin
alu_operand_a_o = accum_window_q;
alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1};
end
endcase
end
// Multiplier partial product calculation
assign b_0 = {32{op_b_shift_q[0]}};
assign op_a_bw_pp = { ~(op_a_shift_q[32] & op_b_shift_q[0]), (op_a_shift_q[31:0] & b_0) };
assign op_a_bw_last_pp = { (op_a_shift_q[32] & op_b_shift_q[0]), ~(op_a_shift_q[31:0] & b_0) };
// Sign extend the input operands
assign sign_a = op_a_i[31] & signed_mode_i[0];
assign sign_b = op_b_i[31] & signed_mode_i[1];
assign op_a_ext = {sign_a, op_a_i};
assign op_b_ext = {sign_b, op_b_i};
// Divider calculations
// The adder in the ALU computes Remainder - Divisor. If Remainder - Divisor >= 0,
// is_greater_equal is true, the next Remainder is the subtraction result and the Quotient
// multdiv_count_q-th bit is set to 1.
assign is_greater_equal = (accum_window_q[31] == op_b_shift_q[31]) ?
~res_adder_h[31] : accum_window_q[31];
assign one_shift = {32'b0, 1'b1} << multdiv_count_q;
assign next_remainder = is_greater_equal ? res_adder_h[31:0] : accum_window_q[31:0];
assign next_quotient = is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q;
assign div_change_sign = (sign_a ^ sign_b) & ~div_by_zero_q;
assign rem_change_sign = sign_a;
always_comb begin
multdiv_count_d = multdiv_count_q;
accum_window_d = accum_window_q;
op_b_shift_d = op_b_shift_q;
op_a_shift_d = op_a_shift_q;
op_numerator_d = op_numerator_q;
md_state_d = md_state_q;
multdiv_hold = 1'b0;
div_by_zero_d = div_by_zero_q;
if (mult_sel_i || div_sel_i) begin
unique case (md_state_q)
MD_IDLE: begin
unique case (operator_i)
MD_OP_MULL: begin
op_a_shift_d = op_a_ext << 1;
accum_window_d = { ~(op_a_ext[32] & op_b_i[0]),
op_a_ext[31:0] & {32{op_b_i[0]}} };
op_b_shift_d = op_b_ext >> 1;
// Proceed with multiplication by 0/1 in data-independent time mode
md_state_d = (!data_ind_timing_i && ((op_b_ext >> 1) == 0)) ? MD_LAST : MD_COMP;
end
MD_OP_MULH: begin
op_a_shift_d = op_a_ext;
accum_window_d = { 1'b1, ~(op_a_ext[32] & op_b_i[0]),
op_a_ext[31:1] & {31{op_b_i[0]}} };
op_b_shift_d = op_b_ext >> 1;
md_state_d = MD_COMP;
end
MD_OP_DIV: begin
// Check if the denominator is 0
// quotient for division by 0 is specified to be -1
// Note with data-independent time option, the full divide operation will proceed as
// normal and will naturally return -1
accum_window_d = {33{1'b1}};
md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
// Record that this is a div by zero to stop the sign change at the end of the
// division (in data_ind_timing mode).
div_by_zero_d = equal_to_zero_i;
end
MD_OP_REM: begin
// Check if the denominator is 0
// remainder for division by 0 is specified to be the numerator (operand a)
// Note with data-independent time option, the full divide operation will proceed as
// normal and will naturally return operand a
accum_window_d = op_a_ext;
md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
end
default:;
endcase
multdiv_count_d = 5'd31;
end
MD_ABS_A: begin
// quotient
op_a_shift_d = '0;
// A abs value
op_numerator_d = sign_a ? alu_adder_i : op_a_i;
md_state_d = MD_ABS_B;
end
MD_ABS_B: begin
// remainder
accum_window_d = {32'h0, op_numerator_q[31]};
// B abs value
op_b_shift_d = sign_b ? {1'b0, alu_adder_i} : {1'b0, op_b_i};
md_state_d = MD_COMP;
end
MD_COMP: begin
multdiv_count_d = multdiv_count_q - 5'h1;
unique case (operator_i)
MD_OP_MULL: begin
accum_window_d = res_adder_l;
op_a_shift_d = op_a_shift_q << 1;
op_b_shift_d = op_b_shift_q >> 1;
// Multiplication is complete once op_b is zero, unless in data_ind_timing mode where
// the maximum possible shift-add operations will be completed regardless of op_b
md_state_d = ((!data_ind_timing_i && (op_b_shift_d == 0)) ||
(multdiv_count_q == 5'd1)) ? MD_LAST : MD_COMP;
end
MD_OP_MULH: begin
accum_window_d = res_adder_h;
op_a_shift_d = op_a_shift_q;
op_b_shift_d = op_b_shift_q >> 1;
md_state_d = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP;
end
MD_OP_DIV,
MD_OP_REM: begin
accum_window_d = {next_remainder[31:0], op_numerator_q[multdiv_count_d]};
op_a_shift_d = next_quotient;
md_state_d = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP;
end
default: ;
endcase
end
MD_LAST: begin
unique case (operator_i)
MD_OP_MULL: begin
accum_window_d = res_adder_l;
// Note no state transition will occur if multdiv_hold is set
md_state_d = MD_IDLE;
multdiv_hold = ~multdiv_ready_id_i;
end
MD_OP_MULH: begin
accum_window_d = res_adder_l;
md_state_d = MD_IDLE;
// Note no state transition will occur if multdiv_hold is set
md_state_d = MD_IDLE;
multdiv_hold = ~multdiv_ready_id_i;
end
MD_OP_DIV: begin
// this time we save the quotient in accum_window_q since we do not need anymore the
// remainder
accum_window_d = next_quotient;
md_state_d = MD_CHANGE_SIGN;
end
MD_OP_REM: begin
// this time we do not save the quotient anymore since we need only the remainder
accum_window_d = {1'b0, next_remainder[31:0]};
md_state_d = MD_CHANGE_SIGN;
end
default: ;
endcase
end
MD_CHANGE_SIGN: begin
md_state_d = MD_FINISH;
unique case (operator_i)
MD_OP_DIV:
accum_window_d = div_change_sign ? {1'b0,alu_adder_i} : accum_window_q;
MD_OP_REM:
accum_window_d = rem_change_sign ? {1'b0,alu_adder_i} : accum_window_q;
default: ;
endcase
end
MD_FINISH: begin
// Note no state transition will occur if multdiv_hold is set
md_state_d = MD_IDLE;
multdiv_hold = ~multdiv_ready_id_i;
end
default: begin
md_state_d = MD_IDLE;
end
endcase // md_state_q
end // (mult_sel_i || div_sel_i)
end
//////////////////////////////////////////
// Mutliplier / Divider state registers //
//////////////////////////////////////////
assign multdiv_en = (mult_en_i | div_en_i) & ~multdiv_hold;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
multdiv_count_q <= 5'h0;
op_b_shift_q <= 33'h0;
op_a_shift_q <= 33'h0;
md_state_q <= MD_IDLE;
div_by_zero_q <= 1'b0;
end else if (multdiv_en) begin
multdiv_count_q <= multdiv_count_d;
op_b_shift_q <= op_b_shift_d;
op_a_shift_q <= op_a_shift_d;
md_state_q <= md_state_d;
div_by_zero_q <= div_by_zero_d;
end
end
/////////////
// Outputs //
/////////////
assign valid_o = (md_state_q == MD_FINISH) |
(md_state_q == MD_LAST &
(operator_i == MD_OP_MULL |
operator_i == MD_OP_MULH));
assign multdiv_result_o = div_en_i ? accum_window_q[31:0] : res_adder_l[31:0];
////////////////
// Assertions //
////////////////
// State must be valid.
`ASSERT(IbexMultDivStateValid, md_state_q inside {
MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
}, clk_i, !rst_ni)
`ifdef FORMAL
`ifdef YOSYS
`include "formal_tb_frag.svh"
`endif
`endif
endmodule |
module ibex_wb_stage #(
parameter bit ResetAll = 1'b0,
parameter bit WritebackStage = 1'b0
) (
input logic clk_i,
input logic rst_ni,
input logic en_wb_i,
input ibex_pkg::wb_instr_type_e instr_type_wb_i,
input logic [31:0] pc_id_i,
input logic instr_is_compressed_id_i,
input logic instr_perf_count_id_i,
output logic ready_wb_o,
output logic rf_write_wb_o,
output logic outstanding_load_wb_o,
output logic outstanding_store_wb_o,
output logic [31:0] pc_wb_o,
output logic perf_instr_ret_wb_o,
output logic perf_instr_ret_compressed_wb_o,
output logic perf_instr_ret_wb_spec_o,
output logic perf_instr_ret_compressed_wb_spec_o,
input logic [4:0] rf_waddr_id_i,
input logic [31:0] rf_wdata_id_i,
input logic rf_we_id_i,
input logic [31:0] rf_wdata_lsu_i,
input logic rf_we_lsu_i,
output logic [31:0] rf_wdata_fwd_wb_o,
output logic [4:0] rf_waddr_wb_o,
output logic [31:0] rf_wdata_wb_o,
output logic rf_we_wb_o,
input logic lsu_resp_valid_i,
input logic lsu_resp_err_i,
output logic instr_done_wb_o
);
import ibex_pkg::*;
// 0 == RF write from ID
// 1 == RF write from LSU
logic [31:0] rf_wdata_wb_mux [2];
logic [1:0] rf_wdata_wb_mux_we;
if (WritebackStage) begin : g_writeback_stage
logic [31:0] rf_wdata_wb_q;
logic rf_we_wb_q;
logic [4:0] rf_waddr_wb_q;
logic wb_done;
logic wb_valid_q;
logic [31:0] wb_pc_q;
logic wb_compressed_q;
logic wb_count_q;
wb_instr_type_e wb_instr_type_q;
logic wb_valid_d;
// Stage becomes valid if an instruction enters for ID/EX and valid is cleared when instruction
// is done
assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done);
// Writeback for non load/store instructions always completes in a cycle (so instantly done)
// Writeback for load/store must wait for response to be received by the LSU
// Signal only relevant if wb_valid_q set
assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_resp_valid_i;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
wb_valid_q <= 1'b0;
end else begin
wb_valid_q <= wb_valid_d;
end
end
if (ResetAll) begin : g_wb_regs_ra
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rf_we_wb_q <= '0;
rf_waddr_wb_q <= '0;
rf_wdata_wb_q <= '0;
wb_instr_type_q <= wb_instr_type_e'(0);
wb_pc_q <= '0;
wb_compressed_q <= '0;
wb_count_q <= '0;
end else if (en_wb_i) begin
rf_we_wb_q <= rf_we_id_i;
rf_waddr_wb_q <= rf_waddr_id_i;
rf_wdata_wb_q <= rf_wdata_id_i;
wb_instr_type_q <= instr_type_wb_i;
wb_pc_q <= pc_id_i;
wb_compressed_q <= instr_is_compressed_id_i;
wb_count_q <= instr_perf_count_id_i;
end
end
end else begin : g_wb_regs_nr
always_ff @(posedge clk_i) begin
if (en_wb_i) begin
rf_we_wb_q <= rf_we_id_i;
rf_waddr_wb_q <= rf_waddr_id_i;
rf_wdata_wb_q <= rf_wdata_id_i;
wb_instr_type_q <= instr_type_wb_i;
wb_pc_q <= pc_id_i;
wb_compressed_q <= instr_is_compressed_id_i;
wb_count_q <= instr_perf_count_id_i;
end
end
end
assign rf_waddr_wb_o = rf_waddr_wb_q;
assign rf_wdata_wb_mux[0] = rf_wdata_wb_q;
assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q;
assign ready_wb_o = ~wb_valid_q | wb_done;
// Instruction in writeback will be writing to register file if either rf_we is set or writeback
// is awaiting load data. This is used for determining RF read hazards in ID/EX
assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == WB_INSTR_LOAD));
assign outstanding_load_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_LOAD);
assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_STORE);
assign pc_wb_o = wb_pc_q;
assign instr_done_wb_o = wb_valid_q & wb_done;
// Increment instruction retire counters for valid instructions which are not lsu errors.
// Speculative versions of the signals do not factor in exceptions and whether the instruction
// is done yet. These are used to get correct values for instructions reading the relevant
// performance counters in the ID stage.
assign perf_instr_ret_wb_spec_o = wb_count_q;
assign perf_instr_ret_compressed_wb_spec_o = perf_instr_ret_wb_spec_o & wb_compressed_q;
assign perf_instr_ret_wb_o = instr_done_wb_o & wb_count_q &
~(lsu_resp_valid_i & lsu_resp_err_i);
assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & wb_compressed_q;
// Forward data that will be written to the RF back to ID to resolve data hazards. The flopped
// rf_wdata_wb_q is used rather than rf_wdata_wb_o as the latter includes read data from memory
// that returns too late to be used on the forwarding path.
assign rf_wdata_fwd_wb_o = rf_wdata_wb_q;
end else begin : g_bypass_wb
// without writeback stage just pass through register write signals
assign rf_waddr_wb_o = rf_waddr_id_i;
assign rf_wdata_wb_mux[0] = rf_wdata_id_i;
assign rf_wdata_wb_mux_we[0] = rf_we_id_i;
// Increment instruction retire counters for valid instructions which are not lsu errors.
// The speculative signals are always 0 when no writeback stage is present as the raw counter
// values will be correct.
assign perf_instr_ret_wb_spec_o = 1'b0;
assign perf_instr_ret_compressed_wb_spec_o = 1'b0;
assign perf_instr_ret_wb_o = instr_perf_count_id_i & en_wb_i &
~(lsu_resp_valid_i & lsu_resp_err_i);
assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & instr_is_compressed_id_i;
// ready needs to be constant 1 without writeback stage (otherwise ID/EX stage will stall)
assign ready_wb_o = 1'b1;
// Unused Writeback stage only IO & wiring
// Assign inputs and internal wiring to unused signals to satisfy lint checks
// Tie-off outputs to constant values
logic unused_clk;
logic unused_rst;
wb_instr_type_e unused_instr_type_wb;
logic [31:0] unused_pc_id;
assign unused_clk = clk_i;
assign unused_rst = rst_ni;
assign unused_instr_type_wb = instr_type_wb_i;
assign unused_pc_id = pc_id_i;
assign outstanding_load_wb_o = 1'b0;
assign outstanding_store_wb_o = 1'b0;
assign pc_wb_o = '0;
assign rf_write_wb_o = 1'b0;
assign rf_wdata_fwd_wb_o = 32'b0;
assign instr_done_wb_o = 1'b0;
end
assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i;
assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;
// RF write data can come from ID results (all RF writes that aren't because of loads will come
// from here) or the LSU (RF writes for load data)
assign rf_wdata_wb_o = ({32{rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) |
({32{rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
assign rf_we_wb_o = |rf_wdata_wb_mux_we;
`DV_FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, WritebackStage)
`ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
endmodule |
module ibex_fetch_fifo #(
parameter int unsigned NUM_REQS = 2,
parameter bit ResetAll = 1'b0
) (
input logic clk_i,
input logic rst_ni,
// control signals
input logic clear_i, // clears the contents of the FIFO
output logic [NUM_REQS-1:0] busy_o,
// input port
input logic in_valid_i,
input logic [31:0] in_addr_i,
input logic [31:0] in_rdata_i,
input logic in_err_i,
// output port
output logic out_valid_o,
input logic out_ready_i,
output logic [31:0] out_addr_o,
output logic [31:0] out_addr_next_o,
output logic [31:0] out_rdata_o,
output logic out_err_o,
output logic out_err_plus2_o
);
localparam int unsigned DEPTH = NUM_REQS+1;
// index 0 is used for output
logic [DEPTH-1:0] [31:0] rdata_d, rdata_q;
logic [DEPTH-1:0] err_d, err_q;
logic [DEPTH-1:0] valid_d, valid_q;
logic [DEPTH-1:0] lowest_free_entry;
logic [DEPTH-1:0] valid_pushed, valid_popped;
logic [DEPTH-1:0] entry_en;
logic pop_fifo;
logic [31:0] rdata, rdata_unaligned;
logic err, err_unaligned, err_plus2;
logic valid, valid_unaligned;
logic aligned_is_compressed, unaligned_is_compressed;
logic addr_incr_two;
logic [31:1] instr_addr_next;
logic [31:1] instr_addr_d, instr_addr_q;
logic instr_addr_en;
logic unused_addr_in;
/////////////////
// Output port //
/////////////////
assign rdata = valid_q[0] ? rdata_q[0] : in_rdata_i;
assign err = valid_q[0] ? err_q[0] : in_err_i;
assign valid = valid_q[0] | in_valid_i;
// The FIFO contains word aligned memory fetches, but the instructions contained in each entry
// might be half-word aligned (due to compressed instructions)
// e.g.
// | 31 16 | 15 0 |
// FIFO entry 0 | Instr 1 [15:0] | Instr 0 [15:0] |
// FIFO entry 1 | Instr 2 [15:0] | Instr 1 [31:16] |
//
// The FIFO also has a direct bypass path, so a complete instruction might be made up of data
// from the FIFO and new incoming data.
//
// Construct the output data for an unaligned instruction
assign rdata_unaligned = valid_q[1] ? {rdata_q[1][15:0], rdata[31:16]} :
{in_rdata_i[15:0], rdata[31:16]};
// If entry[1] is valid, an error can come from entry[0] or entry[1], unless the
// instruction in entry[0] is compressed (entry[1] is a new instruction)
// If entry[1] is not valid, and entry[0] is, an error can come from entry[0] or the incoming
// data, unless the instruction in entry[0] is compressed
// If entry[0] is not valid, the error must come from the incoming data
assign err_unaligned = valid_q[1] ? ((err_q[1] & ~unaligned_is_compressed) | err_q[0]) :
((valid_q[0] & err_q[0]) |
(in_err_i & (~valid_q[0] | ~unaligned_is_compressed)));
// Record when an error is caused by the second half of an unaligned 32bit instruction.
// Only needs to be correct when unaligned and if err_unaligned is set
assign err_plus2 = valid_q[1] ? (err_q[1] & ~err_q[0]) :
(in_err_i & valid_q[0] & ~err_q[0]);
// An uncompressed unaligned instruction is only valid if both parts are available
assign valid_unaligned = valid_q[1] ? 1'b1 :
(valid_q[0] & in_valid_i);
// If there is an error, rdata is unknown
assign unaligned_is_compressed = (rdata[17:16] != 2'b11) & ~err;
assign aligned_is_compressed = (rdata[ 1: 0] != 2'b11) & ~err;
////////////////////////////////////////
// Instruction aligner (if unaligned) //
////////////////////////////////////////
always_comb begin
if (out_addr_o[1]) begin
// unaligned case
out_rdata_o = rdata_unaligned;
out_err_o = err_unaligned;
out_err_plus2_o = err_plus2;
if (unaligned_is_compressed) begin
out_valid_o = valid;
end else begin
out_valid_o = valid_unaligned;
end
end else begin
// aligned case
out_rdata_o = rdata;
out_err_o = err;
out_err_plus2_o = 1'b0;
out_valid_o = valid;
end
end
/////////////////////////
// Instruction address //
/////////////////////////
// Update the address on branches and every time an instruction is driven
assign instr_addr_en = clear_i | (out_ready_i & out_valid_o);
// Increment the address by two every time a compressed instruction is popped
assign addr_incr_two = instr_addr_q[1] ? unaligned_is_compressed :
aligned_is_compressed;
assign instr_addr_next = (instr_addr_q[31:1] +
// Increment address by 4 or 2
{29'd0,~addr_incr_two,addr_incr_two});
assign instr_addr_d = clear_i ? in_addr_i[31:1] :
instr_addr_next;
if (ResetAll) begin : g_instr_addr_ra
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
instr_addr_q <= '0;
end else if (instr_addr_en) begin
instr_addr_q <= instr_addr_d;
end
end
end else begin : g_instr_addr_nr
always_ff @(posedge clk_i) begin
if (instr_addr_en) begin
instr_addr_q <= instr_addr_d;
end
end
end
// Output both PC of current instruction and instruction following. PC of instruction following is
// required for the branch predictor. It's used to fetch the instruction following a branch that
// was not-taken but (mis)predicted taken.
assign out_addr_next_o = {instr_addr_next, 1'b0};
assign out_addr_o = {instr_addr_q, 1'b0};
// The LSB of the address is unused, since all addresses are halfword aligned
assign unused_addr_in = in_addr_i[0];
/////////////////
// FIFO status //
/////////////////
// Indicate the fill level of fifo-entries. This is used to determine when a new request can be
// made on the bus. The prefetch buffer only needs to know about the upper entries which overlap
// with NUM_REQS.
assign busy_o = valid_q[DEPTH-1:DEPTH-NUM_REQS];
/////////////////////
// FIFO management //
/////////////////////
// Since an entry can contain unaligned instructions, popping an entry can leave the entry valid
assign pop_fifo = out_ready_i & out_valid_o & (~aligned_is_compressed | out_addr_o[1]);
for (genvar i = 0; i < (DEPTH - 1); i++) begin : g_fifo_next
// Calculate lowest free entry (write pointer)
if (i == 0) begin : g_ent0
assign lowest_free_entry[i] = ~valid_q[i];
end else begin : g_ent_others
assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i-1];
end
// An entry is set when an incoming request chooses the lowest available entry
assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) |
valid_q[i];
// Popping the FIFO shifts all entries down
assign valid_popped[i] = pop_fifo ? valid_pushed[i+1] : valid_pushed[i];
// All entries are wiped out on a clear
assign valid_d[i] = valid_popped[i] & ~clear_i;
// data flops are enabled if there is new data to shift into it, or
assign entry_en[i] = (valid_pushed[i+1] & pop_fifo) |
// a new request is incoming and this is the lowest free entry
(in_valid_i & lowest_free_entry[i] & ~pop_fifo);
// take the next entry or the incoming data
assign rdata_d[i] = valid_q[i+1] ? rdata_q[i+1] : in_rdata_i;
assign err_d [i] = valid_q[i+1] ? err_q [i+1] : in_err_i;
end
// The top entry is similar but with simpler muxing
assign lowest_free_entry[DEPTH-1] = ~valid_q[DEPTH-1] & valid_q[DEPTH-2];
assign valid_pushed [DEPTH-1] = valid_q[DEPTH-1] | (in_valid_i & lowest_free_entry[DEPTH-1]);
assign valid_popped [DEPTH-1] = pop_fifo ? 1'b0 : valid_pushed[DEPTH-1];
assign valid_d [DEPTH-1] = valid_popped[DEPTH-1] & ~clear_i;
assign entry_en[DEPTH-1] = in_valid_i & lowest_free_entry[DEPTH-1];
assign rdata_d [DEPTH-1] = in_rdata_i;
assign err_d [DEPTH-1] = in_err_i;
////////////////////
// FIFO registers //
////////////////////
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
valid_q <= '0;
end else begin
valid_q <= valid_d;
end
end
for (genvar i = 0; i < DEPTH; i++) begin : g_fifo_regs
if (ResetAll) begin : g_rdata_ra
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rdata_q[i] <= '0;
err_q[i] <= '0;
end else if (entry_en[i]) begin
rdata_q[i] <= rdata_d[i];
err_q[i] <= err_d[i];
end
end
end else begin : g_rdata_nr
always_ff @(posedge clk_i) begin
if (entry_en[i]) begin
rdata_q[i] <= rdata_d[i];
err_q[i] <= err_d[i];
end
end
end
end
////////////////
// Assertions //
////////////////
// Must not push and pop simultaneously when FIFO full.
`ASSERT(IbexFetchFifoPushPopFull,
(in_valid_i && pop_fifo) |-> (!valid_q[DEPTH-1] || clear_i))
// Must not push to FIFO when full.
`ASSERT(IbexFetchFifoPushFull,
(in_valid_i) |-> (!valid_q[DEPTH-1] || clear_i))
endmodule |
module ibex_compressed_decoder (
input logic clk_i,
input logic rst_ni,
input logic valid_i,
input logic [31:0] instr_i,
output logic [31:0] instr_o,
output logic is_compressed_o,
output logic illegal_instr_o
);
import ibex_pkg::*;
// valid_i indicates if instr_i is valid and is used for assertions only.
// The following signal is used to avoid possible lint errors.
logic unused_valid;
assign unused_valid = valid_i;
////////////////////////
// Compressed decoder //
////////////////////////
always_comb begin
// By default, forward incoming instruction, mark it as legal.
instr_o = instr_i;
illegal_instr_o = 1'b0;
// Check if incoming instruction is compressed.
unique case (instr_i[1:0])
// C0
2'b00: begin
unique case (instr_i[15:13])
3'b000: begin
// c.addi4spn -> addi rd', x2, imm
instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5],
instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], {OPCODE_OP_IMM}};
if (instr_i[12:5] == 8'b0) illegal_instr_o = 1'b1;
end
3'b010: begin
// c.lw -> lw rd', imm(rs1')
instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6],
2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {OPCODE_LOAD}};
end
3'b110: begin
// c.sw -> sw rs2', imm(rs1')
instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2],
2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6],
2'b00, {OPCODE_STORE}};
end
3'b001,
3'b011,
3'b100,
3'b101,
3'b111: begin
illegal_instr_o = 1'b1;
end
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
// C1
//
// Register address checks for RV32E are performed in the regular instruction decoder.
// If this check fails, an illegal instruction exception is triggered and the controller
// writes the actual faulting instruction to mtval.
2'b01: begin
unique case (instr_i[15:13])
3'b000: begin
// c.addi -> addi rd, rd, nzimm
// c.nop
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2],
instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP_IMM}};
end
3'b001, 3'b101: begin
// 001: c.jal -> jal x1, imm
// 101: c.j -> jal x0, imm
instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6],
instr_i[7], instr_i[2], instr_i[11], instr_i[5:3],
{9 {instr_i[12]}}, 4'b0, ~instr_i[15], {OPCODE_JAL}};
end
3'b010: begin
// c.li -> addi rd, x0, nzimm
// (c.li hints are translated into an addi hint)
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0,
3'b0, instr_i[11:7], {OPCODE_OP_IMM}};
end
3'b011: begin
// c.lui -> lui rd, imm
// (c.lui hints are translated into a lui hint)
instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {OPCODE_LUI}};
if (instr_i[11:7] == 5'h02) begin
// c.addi16sp -> addi x2, x2, nzimm
instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2],
instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OP_IMM}};
end
if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;
end
3'b100: begin
unique case (instr_i[11:10])
2'b00,
2'b01: begin
// 00: c.srli -> srli rd, rd, shamt
// 01: c.srai -> srai rd, rd, shamt
// (c.srli/c.srai hints are translated into a srli/srai hint)
instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7],
3'b101, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}};
if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1;
end
2'b10: begin
// c.andi -> andi rd, rd, imm
instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7],
3'b111, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}};
end
2'b11: begin
unique case ({instr_i[12], instr_i[6:5]})
3'b000: begin
// c.sub -> sub rd', rd', rs2'
instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7],
3'b000, 2'b01, instr_i[9:7], {OPCODE_OP}};
end
3'b001: begin
// c.xor -> xor rd', rd', rs2'
instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100,
2'b01, instr_i[9:7], {OPCODE_OP}};
end
3'b010: begin
// c.or -> or rd', rd', rs2'
instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110,
2'b01, instr_i[9:7], {OPCODE_OP}};
end
3'b011: begin
// c.and -> and rd', rd', rs2'
instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111,
2'b01, instr_i[9:7], {OPCODE_OP}};
end
3'b100,
3'b101,
3'b110,
3'b111: begin
// 100: c.subw
// 101: c.addw
illegal_instr_o = 1'b1;
end
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
3'b110, 3'b111: begin
// 0: c.beqz -> beq rs1', x0, imm
// 1: c.bnez -> bne rs1', x0, imm
instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01,
instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3],
instr_i[12], {OPCODE_BRANCH}};
end
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
// C2
//
// Register address checks for RV32E are performed in the regular instruction decoder.
// If this check fails, an illegal instruction exception is triggered and the controller
// writes the actual faulting instruction to mtval.
2'b10: begin
unique case (instr_i[15:13])
3'b000: begin
// c.slli -> slli rd, rd, shamt
// (c.ssli hints are translated into a slli hint)
instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {OPCODE_OP_IMM}};
if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1; // reserved for custom extensions
end
3'b010: begin
// c.lwsp -> lw rd, imm(x2)
instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02,
3'b010, instr_i[11:7], OPCODE_LOAD};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
end
3'b100: begin
if (instr_i[12] == 1'b0) begin
if (instr_i[6:2] != 5'b0) begin
// c.mv -> add rd/rs1, x0, rs2
// (c.mv hints are translated into an add hint)
instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], {OPCODE_OP}};
end else begin
// c.jr -> jalr x0, rd/rs1, 0
instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, {OPCODE_JALR}};
if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
end
end else begin
if (instr_i[6:2] != 5'b0) begin
// c.add -> add rd, rd, rs2
// (c.add hints are translated into an add hint)
instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP}};
end else begin
if (instr_i[11:7] == 5'b0) begin
// c.ebreak -> ebreak
instr_o = {32'h00_10_00_73};
end else begin
// c.jalr -> jalr x1, rs1, 0
instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, {OPCODE_JALR}};
end
end
end
end
3'b110: begin
// c.swsp -> sw rs2, imm(x2)
instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010,
instr_i[11:9], 2'b00, {OPCODE_STORE}};
end
3'b001,
3'b011,
3'b101,
3'b111: begin
illegal_instr_o = 1'b1;
end
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
// Incoming instruction is not compressed.
2'b11:;
default: begin
illegal_instr_o = 1'b1;
end
endcase
end
assign is_compressed_o = (instr_i[1:0] != 2'b11);
////////////////
// Assertions //
////////////////
// The valid_i signal used to gate below assertions must be known.
`ASSERT_KNOWN(IbexInstrValidKnown, valid_i)
// Selectors must be known/valid.
`ASSERT(IbexInstrLSBsKnown, valid_i |->
!$isunknown(instr_i[1:0]))
`ASSERT(IbexC0Known1, (valid_i && (instr_i[1:0] == 2'b00)) |->
!$isunknown(instr_i[15:13]))
`ASSERT(IbexC1Known1, (valid_i && (instr_i[1:0] == 2'b01)) |->
!$isunknown(instr_i[15:13]))
`ASSERT(IbexC1Known2, (valid_i && (instr_i[1:0] == 2'b01) && (instr_i[15:13] == 3'b100)) |->
!$isunknown(instr_i[11:10]))
`ASSERT(IbexC1Known3, (valid_i &&
(instr_i[1:0] == 2'b01) && (instr_i[15:13] == 3'b100) && (instr_i[11:10] == 2'b11)) |->
!$isunknown({instr_i[12], instr_i[6:5]}))
`ASSERT(IbexC2Known1, (valid_i && (instr_i[1:0] == 2'b10)) |->
!$isunknown(instr_i[15:13]))
endmodule |
module ibex_multdiv_fast #(
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast
) (
input logic clk_i,
input logic rst_ni,
input logic mult_en_i, // dynamic enable signal, for FSM control
input logic div_en_i, // dynamic enable signal, for FSM control
input logic mult_sel_i, // static decoder output, for data muxes
input logic div_sel_i, // static decoder output, for data muxes
input ibex_pkg::md_op_e operator_i,
input logic [1:0] signed_mode_i,
input logic [31:0] op_a_i,
input logic [31:0] op_b_i,
input logic [33:0] alu_adder_ext_i,
input logic [31:0] alu_adder_i,
input logic equal_to_zero_i,
input logic data_ind_timing_i,
output logic [32:0] alu_operand_a_o,
output logic [32:0] alu_operand_b_o,
input logic [33:0] imd_val_q_i[2],
output logic [33:0] imd_val_d_o[2],
output logic [1:0] imd_val_we_o,
input logic multdiv_ready_id_i,
output logic [31:0] multdiv_result_o,
output logic valid_o
);
import ibex_pkg::*;
// Both multiplier variants
logic signed [34:0] mac_res_signed;
logic [34:0] mac_res_ext;
logic [33:0] accum;
logic sign_a, sign_b;
logic mult_valid;
logic signed_mult;
// Results that become intermediate value depending on whether mul or div is being calculated
logic [33:0] mac_res_d, op_remainder_d;
// Raw output of MAC calculation
logic [33:0] mac_res;
// Divider signals
logic div_sign_a, div_sign_b;
logic is_greater_equal;
logic div_change_sign, rem_change_sign;
logic [31:0] one_shift;
logic [31:0] op_denominator_q;
logic [31:0] op_numerator_q;
logic [31:0] op_quotient_q;
logic [31:0] op_denominator_d;
logic [31:0] op_numerator_d;
logic [31:0] op_quotient_d;
logic [31:0] next_remainder;
logic [32:0] next_quotient;
logic [31:0] res_adder_h;
logic div_valid;
logic [ 4:0] div_counter_q, div_counter_d;
logic multdiv_en;
logic mult_hold;
logic div_hold;
logic div_by_zero_d, div_by_zero_q;
logic mult_en_internal;
logic div_en_internal;
typedef enum logic [2:0] {
MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
} md_fsm_e;
md_fsm_e md_state_q, md_state_d;
logic unused_mult_sel_i;
assign unused_mult_sel_i = mult_sel_i;
assign mult_en_internal = mult_en_i & ~mult_hold;
assign div_en_internal = div_en_i & ~div_hold;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
div_counter_q <= '0;
md_state_q <= MD_IDLE;
op_numerator_q <= '0;
op_quotient_q <= '0;
div_by_zero_q <= '0;
end else if (div_en_internal) begin
div_counter_q <= div_counter_d;
op_numerator_q <= op_numerator_d;
op_quotient_q <= op_quotient_d;
md_state_q <= md_state_d;
div_by_zero_q <= div_by_zero_d;
end
end
`ASSERT_KNOWN(DivEnKnown, div_en_internal)
`ASSERT_KNOWN(MultEnKnown, mult_en_internal)
`ASSERT_KNOWN(MultDivEnKnown, multdiv_en)
assign multdiv_en = mult_en_internal | div_en_internal;
// Intermediate value register shared with ALU
assign imd_val_d_o[0] = div_sel_i ? op_remainder_d : mac_res_d;
assign imd_val_we_o[0] = multdiv_en;
assign imd_val_d_o[1] = {2'b0, op_denominator_d};
assign imd_val_we_o[1] = div_en_internal;
assign op_denominator_q = imd_val_q_i[1][31:0];
logic [1:0] unused_imd_val;
assign unused_imd_val = imd_val_q_i[1][33:32];
logic unused_mac_res_ext;
assign unused_mac_res_ext = mac_res_ext[34];
assign signed_mult = (signed_mode_i != 2'b00);
assign multdiv_result_o = div_sel_i ? imd_val_q_i[0][31:0] : mac_res_d[31:0];
// The single cycle multiplier uses three 17 bit multipliers to compute MUL instructions in a
// single cycle and MULH instructions in two cycles.
if (RV32M == RV32MSingleCycle) begin : gen_mult_single_cycle
typedef enum logic {
MULL, MULH
} mult_fsm_e;
mult_fsm_e mult_state_q, mult_state_d;
logic signed [33:0] mult1_res, mult2_res, mult3_res;
logic [33:0] mult1_res_uns;
logic [33:32] unused_mult1_res_uns;
logic [15:0] mult1_op_a, mult1_op_b;
logic [15:0] mult2_op_a, mult2_op_b;
logic [15:0] mult3_op_a, mult3_op_b;
logic mult1_sign_a, mult1_sign_b;
logic mult2_sign_a, mult2_sign_b;
logic mult3_sign_a, mult3_sign_b;
logic [33:0] summand1, summand2, summand3;
assign mult1_res = $signed({mult1_sign_a, mult1_op_a}) * $signed({mult1_sign_b, mult1_op_b});
assign mult2_res = $signed({mult2_sign_a, mult2_op_a}) * $signed({mult2_sign_b, mult2_op_b});
assign mult3_res = $signed({mult3_sign_a, mult3_op_a}) * $signed({mult3_sign_b, mult3_op_b});
assign mac_res_signed = $signed(summand1) + $signed(summand2) + $signed(summand3);
assign mult1_res_uns = $unsigned(mult1_res);
assign mac_res_ext = $unsigned(mac_res_signed);
assign mac_res = mac_res_ext[33:0];
assign sign_a = signed_mode_i[0] & op_a_i[31];
assign sign_b = signed_mode_i[1] & op_b_i[31];
// The first two multipliers are only used in state 1 (MULL). We can assign them statically.
// al*bl
assign mult1_sign_a = 1'b0;
assign mult1_sign_b = 1'b0;
assign mult1_op_a = op_a_i[`OP_L];
assign mult1_op_b = op_b_i[`OP_L];
// al*bh
assign mult2_sign_a = 1'b0;
assign mult2_sign_b = sign_b;
assign mult2_op_a = op_a_i[`OP_L];
assign mult2_op_b = op_b_i[`OP_H];
// used in MULH
assign accum[17:0] = imd_val_q_i[0][33:16];
assign accum[33:18] = {16{signed_mult & imd_val_q_i[0][33]}};
always_comb begin
// Default values == MULL
// ah*bl
mult3_sign_a = sign_a;
mult3_sign_b = 1'b0;
mult3_op_a = op_a_i[`OP_H];
mult3_op_b = op_b_i[`OP_L];
summand1 = {18'h0, mult1_res_uns[`OP_H]};
summand2 = $unsigned(mult2_res);
summand3 = $unsigned(mult3_res);
// mac_res = A*B[47:16], mult1_res = A*B[15:0]
mac_res_d = {2'b0, mac_res[`OP_L], mult1_res_uns[`OP_L]};
mult_valid = mult_en_i;
mult_state_d = MULL;
mult_hold = 1'b0;
unique case (mult_state_q)
MULL: begin
if (operator_i != MD_OP_MULL) begin
mac_res_d = mac_res;
mult_valid = 1'b0;
mult_state_d = MULH;
end else begin
mult_hold = ~multdiv_ready_id_i;
end
end
MULH: begin
// ah*bh
mult3_sign_a = sign_a;
mult3_sign_b = sign_b;
mult3_op_a = op_a_i[`OP_H];
mult3_op_b = op_b_i[`OP_H];
mac_res_d = mac_res;
summand1 = '0;
summand2 = accum;
summand3 = $unsigned(mult3_res);
mult_state_d = MULL;
mult_valid = 1'b1;
mult_hold = ~multdiv_ready_id_i;
end
default: begin
mult_state_d = MULL;
end
endcase // mult_state_q
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
mult_state_q <= MULL;
end else begin
if (mult_en_internal) begin
mult_state_q <= mult_state_d;
end
end
end
assign unused_mult1_res_uns = mult1_res_uns[33:32];
// States must be knwon/valid.
`ASSERT_KNOWN(IbexMultStateKnown, mult_state_q)
// The fast multiplier uses one 17 bit multiplier to compute MUL instructions in 3 cycles
// and MULH instructions in 4 cycles.
end else begin : gen_mult_fast
logic [15:0] mult_op_a;
logic [15:0] mult_op_b;
typedef enum logic [1:0] {
ALBL, ALBH, AHBL, AHBH
} mult_fsm_e;
mult_fsm_e mult_state_q, mult_state_d;
// The 2 MSBs of mac_res_ext (mac_res_ext[34:33]) are always equal since:
// 1. The 2 MSBs of the multiplicants are always equal, and
// 2. The 16 MSBs of the addend (accum[33:18]) are always equal.
// Thus, it is safe to ignore mac_res_ext[34].
assign mac_res_signed =
$signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b}) + $signed(accum);
assign mac_res_ext = $unsigned(mac_res_signed);
assign mac_res = mac_res_ext[33:0];
always_comb begin
mult_op_a = op_a_i[`OP_L];
mult_op_b = op_b_i[`OP_L];
sign_a = 1'b0;
sign_b = 1'b0;
accum = imd_val_q_i[0];
mac_res_d = mac_res;
mult_state_d = mult_state_q;
mult_valid = 1'b0;
mult_hold = 1'b0;
unique case (mult_state_q)
ALBL: begin
// al*bl
mult_op_a = op_a_i[`OP_L];
mult_op_b = op_b_i[`OP_L];
sign_a = 1'b0;
sign_b = 1'b0;
accum = '0;
mac_res_d = mac_res;
mult_state_d = ALBH;
end
ALBH: begin
// al*bh<<16
mult_op_a = op_a_i[`OP_L];
mult_op_b = op_b_i[`OP_H];
sign_a = 1'b0;
sign_b = signed_mode_i[1] & op_b_i[31];
// result of AL*BL (in imd_val_q_i[0]) always unsigned with no carry
accum = {18'b0, imd_val_q_i[0][31:16]};
if (operator_i == MD_OP_MULL) begin
mac_res_d = {2'b0, mac_res[`OP_L], imd_val_q_i[0][`OP_L]};
end else begin
// MD_OP_MULH
mac_res_d = mac_res;
end
mult_state_d = AHBL;
end
AHBL: begin
// ah*bl<<16
mult_op_a = op_a_i[`OP_H];
mult_op_b = op_b_i[`OP_L];
sign_a = signed_mode_i[0] & op_a_i[31];
sign_b = 1'b0;
if (operator_i == MD_OP_MULL) begin
accum = {18'b0, imd_val_q_i[0][31:16]};
mac_res_d = {2'b0, mac_res[15:0], imd_val_q_i[0][15:0]};
mult_valid = 1'b1;
// Note no state transition will occur if mult_hold is set
mult_state_d = ALBL;
mult_hold = ~multdiv_ready_id_i;
end else begin
accum = imd_val_q_i[0];
mac_res_d = mac_res;
mult_state_d = AHBH;
end
end
AHBH: begin
// only MD_OP_MULH here
// ah*bh
mult_op_a = op_a_i[`OP_H];
mult_op_b = op_b_i[`OP_H];
sign_a = signed_mode_i[0] & op_a_i[31];
sign_b = signed_mode_i[1] & op_b_i[31];
accum[17: 0] = imd_val_q_i[0][33:16];
accum[33:18] = {16{signed_mult & imd_val_q_i[0][33]}};
// result of AH*BL is not signed only if signed_mode_i == 2'b00
mac_res_d = mac_res;
mult_valid = 1'b1;
// Note no state transition will occur if mult_hold is set
mult_state_d = ALBL;
mult_hold = ~multdiv_ready_id_i;
end
default: begin
mult_state_d = ALBL;
end
endcase // mult_state_q
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
mult_state_q <= ALBL;
end else begin
if (mult_en_internal) begin
mult_state_q <= mult_state_d;
end
end
end
// States must be knwon/valid.
`ASSERT_KNOWN(IbexMultStateKnown, mult_state_q)
end // gen_mult_fast
// Divider
assign res_adder_h = alu_adder_ext_i[32:1];
logic [1:0] unused_alu_adder_ext;
assign unused_alu_adder_ext = {alu_adder_ext_i[33],alu_adder_ext_i[0]};
assign next_remainder = is_greater_equal ? res_adder_h[31:0] : imd_val_q_i[0][31:0];
assign next_quotient = is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} :
{1'b0, op_quotient_q};
assign one_shift = {31'b0, 1'b1} << div_counter_q;
// The adder in the ALU computes alu_operand_a_o + alu_operand_b_o which means
// Remainder - Divisor. If Remainder - Divisor >= 0, is_greater_equal is equal to 1,
// the next Remainder is Remainder - Divisor contained in res_adder_h and the
always_comb begin
if ((imd_val_q_i[0][31] ^ op_denominator_q[31]) == 1'b0) begin
is_greater_equal = (res_adder_h[31] == 1'b0);
end else begin
is_greater_equal = imd_val_q_i[0][31];
end
end
assign div_sign_a = op_a_i[31] & signed_mode_i[0];
assign div_sign_b = op_b_i[31] & signed_mode_i[1];
assign div_change_sign = (div_sign_a ^ div_sign_b) & ~div_by_zero_q;
assign rem_change_sign = div_sign_a;
always_comb begin
div_counter_d = div_counter_q - 5'h1;
op_remainder_d = imd_val_q_i[0];
op_quotient_d = op_quotient_q;
md_state_d = md_state_q;
op_numerator_d = op_numerator_q;
op_denominator_d = op_denominator_q;
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~op_b_i, 1'b1};
div_valid = 1'b0;
div_hold = 1'b0;
div_by_zero_d = div_by_zero_q;
unique case (md_state_q)
MD_IDLE: begin
if (operator_i == MD_OP_DIV) begin
// Check if the Denominator is 0
// quotient for division by 0 is specified to be -1
// Note with data-independent time option, the full divide operation will proceed as
// normal and will naturally return -1
op_remainder_d = '1;
md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
// Record that this is a div by zero to stop the sign change at the end of the
// division (in data_ind_timing mode).
div_by_zero_d = equal_to_zero_i;
end else begin
// Check if the Denominator is 0
// remainder for division by 0 is specified to be the numerator (operand a)
// Note with data-independent time option, the full divide operation will proceed as
// normal and will naturally return operand a
op_remainder_d = {2'b0, op_a_i};
md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
end
// 0 - B = 0 iff B == 0
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~op_b_i, 1'b1};
div_counter_d = 5'd31;
end
MD_ABS_A: begin
// quotient
op_quotient_d = '0;
// A abs value
op_numerator_d = div_sign_a ? alu_adder_i : op_a_i;
md_state_d = MD_ABS_B;
div_counter_d = 5'd31;
// ABS(A) = 0 - A
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~op_a_i, 1'b1};
end
MD_ABS_B: begin
// remainder
op_remainder_d = { 33'h0, op_numerator_q[31]};
// B abs value
op_denominator_d = div_sign_b ? alu_adder_i : op_b_i;
md_state_d = MD_COMP;
div_counter_d = 5'd31;
// ABS(B) = 0 - B
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~op_b_i, 1'b1};
end
MD_COMP: begin
op_remainder_d = {1'b0, next_remainder[31:0], op_numerator_q[div_counter_d]};
op_quotient_d = next_quotient[31:0];
md_state_d = (div_counter_q == 5'd1) ? MD_LAST : MD_COMP;
// Division
alu_operand_a_o = {imd_val_q_i[0][31:0], 1'b1}; // it contains the remainder
alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; // -denominator two's compliment
end
MD_LAST: begin
if (operator_i == MD_OP_DIV) begin
// this time we save the quotient in op_remainder_d (i.e. imd_val_q_i[0]) since
// we do not need anymore the remainder
op_remainder_d = {1'b0, next_quotient};
end else begin
// this time we do not save the quotient anymore since we need only the remainder
op_remainder_d = {2'b0, next_remainder[31:0]};
end
// Division
alu_operand_a_o = {imd_val_q_i[0][31:0], 1'b1}; // it contains the remainder
alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; // -denominator two's compliment
md_state_d = MD_CHANGE_SIGN;
end
MD_CHANGE_SIGN: begin
md_state_d = MD_FINISH;
if (operator_i == MD_OP_DIV) begin
op_remainder_d = (div_change_sign) ? {2'h0, alu_adder_i} : imd_val_q_i[0];
end else begin
op_remainder_d = (rem_change_sign) ? {2'h0, alu_adder_i} : imd_val_q_i[0];
end
// ABS(Quotient) = 0 - Quotient (or Remainder)
alu_operand_a_o = {32'h0 , 1'b1};
alu_operand_b_o = {~imd_val_q_i[0][31:0], 1'b1};
end
MD_FINISH: begin
// Hold result until ID stage is ready to accept it
// Note no state transition will occur if div_hold is set
md_state_d = MD_IDLE;
div_hold = ~multdiv_ready_id_i;
div_valid = 1'b1;
end
default: begin
md_state_d = MD_IDLE;
end
endcase // md_state_q
end
assign valid_o = mult_valid | div_valid;
// States must be knwon/valid.
`ASSERT(IbexMultDivStateValid, md_state_q inside {
MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH})
`ifdef FORMAL
`ifdef YOSYS
`include "formal_tb_frag.svh"
`endif
`endif
endmodule // ibex_mult |
module ibex_csr #(
parameter int unsigned Width = 32,
parameter bit ShadowCopy = 1'b0,
parameter bit [Width-1:0] ResetValue = '0
) (
input logic clk_i,
input logic rst_ni,
input logic [Width-1:0] wr_data_i,
input logic wr_en_i,
output logic [Width-1:0] rd_data_o,
output logic rd_error_o
);
logic [Width-1:0] rdata_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rdata_q <= ResetValue;
end else if (wr_en_i) begin
rdata_q <= wr_data_i;
end
end
assign rd_data_o = rdata_q;
if (ShadowCopy) begin : gen_shadow
logic [Width-1:0] shadow_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
shadow_q <= ~ResetValue;
end else if (wr_en_i) begin
shadow_q <= ~wr_data_i;
end
end
assign rd_error_o = rdata_q != ~shadow_q;
end else begin : gen_no_shadow
assign rd_error_o = 1'b0;
end
`ASSERT_KNOWN(IbexCSREnValid, wr_en_i)
endmodule |
module sound_i2s #(
parameter CHANNEL_WIDTH = 16,
parameter SIGNED_INPUT = 0
) (
// input wire clk_74a,
// input wire clk_audio,
input wire audio_sclk,
// Left and right audio channels. ~~Can be in an arbitrary `clk_audio` domain~~
input wire [CHANNEL_WIDTH - 1:0] audio_l,
input wire [CHANNEL_WIDTH - 1:0] audio_r,
// output reg audio_mclk,
output reg audio_lrck,
output reg audio_dac
);
//
// audio i2s generator
//
reg audgen_nextsamp;
// generate MCLK = 12.288mhz with fractional accumulator
// reg [21:0] audgen_accum = 0;
// localparam [20:0] CYCLE_48KHZ = 21'd122880 * 2;
// always @(posedge clk_74a) begin
// audgen_accum <= audgen_accum + CYCLE_48KHZ;
// if (audgen_accum >= 21'd742500) begin
// audio_mclk <= ~audio_mclk;
// audgen_accum <= audgen_accum - 21'd742500 + CYCLE_48KHZ;
// end
// end
// // generate SCLK = 3.072mhz by dividing MCLK by 4
// reg [1:0] aud_mclk_divider;
// reg prev_audio_mclk;
// wire audgen_sclk = aud_mclk_divider[1] /* synthesis keep*/;
// always @(posedge clk_74a) begin
// if (audio_mclk && ~prev_audio_mclk) begin
// aud_mclk_divider <= aud_mclk_divider + 1'b1;
// end
// prev_audio_mclk <= audio_mclk;
// end
// shift out audio data as I2S
// 32 total bits per channel, but only 16 active bits at the start and then 16 dummy bits
//
// synchronize audio samples coming from the core
localparam CHANNEL_LEFT_HIGH = 16;
localparam CHANNEL_RIGHT_HIGH = 16 + CHANNEL_LEFT_HIGH;
// Width of channel with signed component
localparam SIGNED_CHANNEL_WIDTH = SIGNED_INPUT ? CHANNEL_WIDTH : CHANNEL_WIDTH + 1;
// Can center unsigned in signed interval by flipping high bit
wire [CHANNEL_WIDTH - 1:0] sign_converted_audio_l = {
audio_l[CHANNEL_WIDTH-1:CHANNEL_WIDTH-1], audio_l[CHANNEL_WIDTH-2:0]
};
wire [CHANNEL_WIDTH - 1:0] sign_converted_audio_r = {
audio_r[CHANNEL_WIDTH-1:CHANNEL_WIDTH-1], audio_r[CHANNEL_WIDTH-2:0]
};
wire [31:0] audgen_sampdata;
assign audgen_sampdata[CHANNEL_LEFT_HIGH-1:CHANNEL_LEFT_HIGH-CHANNEL_WIDTH] = SIGNED_INPUT ? audio_l : sign_converted_audio_l;
assign audgen_sampdata[CHANNEL_RIGHT_HIGH-1:CHANNEL_RIGHT_HIGH-CHANNEL_WIDTH] = SIGNED_INPUT ? audio_r : sign_converted_audio_r;
generate
if (15 - SIGNED_CHANNEL_WIDTH > 0) begin
assign audgen_sampdata[31-SIGNED_CHANNEL_WIDTH:16] = 0;
assign audgen_sampdata[15-SIGNED_CHANNEL_WIDTH:0] = 0;
end
endgenerate
// sync_fifo #(
// .WIDTH(32)
// ) sync_fifo (
// .clk_write(clk_audio),
// .clk_read (audio_sclk),
// .write_en(write_en),
// .data(audgen_sampdata),
// .data_s(audgen_sampdata_s)
// );
// reg write_en = 0;
// reg [CHANNEL_WIDTH - 1:0] prev_left;
// reg [CHANNEL_WIDTH - 1:0] prev_right;
// // Mark write when necessary
// always @(posedge clk_audio) begin
// prev_left <= audio_l;
// prev_right <= audio_r;
// write_en <= 0;
// if (audio_l != prev_left || audio_r != prev_right) begin
// write_en <= 1;
// end
// end
// wire [31:0] audgen_sampdata_s;
reg [31:0] audgen_sampshift;
reg [ 4:0] audio_lrck_cnt;
always @(posedge audio_sclk) begin
// output the next bit
audio_dac <= audgen_sampshift[31];
// 48khz * 64
audio_lrck_cnt <= audio_lrck_cnt + 1'b1;
if (audio_lrck_cnt == 31) begin
// switch channels
audio_lrck <= ~audio_lrck;
// Reload sample shifter
if (~audio_lrck) begin
audgen_sampshift <= audgen_sampdata;
end
end else if (audio_lrck_cnt < 16) begin
// only shift for 16 clocks per channel
audgen_sampshift <= {audgen_sampshift[30:0], 1'b0};
end
end
initial begin
// Verify parameters
if (CHANNEL_WIDTH > 16) begin
$error("CHANNEL_WIDTH must be <= 16. Received %d", CHANNEL_WIDTH);
end
if (SIGNED_INPUT != 0 && SIGNED_INPUT != 1) begin
$error("SIGNED_INPUT must be 0 or 1. Received %d", SIGNED_INPUT);
end
end
endmodule |
module wishbone (
input wire clk_74a,
input wire clk,
input wire reset,
input wire [29:0] addr,
// Wishbone registered feedback flags
// Burst style extension. Specifies the type of burst
input wire [1:0] bte,
// Cycle type identifier. Indicates what kind of burst cycle is being used
input wire [2:0] cti,
// Cycle. High during the duration of the bus operations
input wire cyc,
input wire [31:0] data_write,
// Which bytes are active in read/write
input wire [3:0] sel,
// Strobe. Need to assert ack or err after this
input wire stb,
// Write enable
input wire we,
output reg ack = 0,
output reg [31:0] data_read = 0,
// output wire [31:0] data_read,
output reg err = 0
);
reg [31:0] ram[16];
// = '{
// 32'h102938,
// 32'h02832,
// 32'h89493,
// 32'h09472,
// 32'h29083,
// 32'h09848,
// 32'h8282,
// 32'h9480,
// 32'h1234,
// 32'h9876,
// 32'h9628,
// 32'h1,
// 32'h2,
// 32'h3,
// 32'h4,
// 32'h5
// };
reg initialized = 0;
reg [3:0] init_addr = 0;
always @(posedge clk) begin
if (reset) begin
initialized <= 0;
init_addr <= 0;
end else begin
if (~initialized) begin
ram[init_addr] <= {28'h0, init_addr};
init_addr <= init_addr + 4'h1;
if (init_addr == 4'hF) begin
initialized <= 1;
end
end
end
end
// assign data_read = 32'hDEADBEEF;
always @(posedge clk) begin
ack <= 0;
if (stb && cyc) begin
// Strobe
if (we) begin
// Write
ram[addr[3:0]] <= data_write;
end else begin
data_read <= ram[addr[3:0]];
end
ack <= 1;
end
end
endmodule |
module audio (
input wire clk_74b,
input wire clk_sys,
input wire reset,
input wire [31:0] audio_bus_in,
input wire audio_bus_wr,
input wire audio_playback_en,
input wire audio_flush,
output wire [11:0] audio_buffer_fill,
output wire audio_mclk, //! Serial Master Clock
output wire audio_lrck, //! Left/Right clock
output wire audio_dac //! Serialized data
);
////////////////////////////////////////////////////////////////////////////////////////
// Audio PLL
wire audio_sclk;
mf_audio_pll audio_pll (
.refclk (clk_74b),
.rst (0),
.outclk_0(audio_mclk),
.outclk_1(audio_sclk)
);
////////////////////////////////////////////////////////////////////////////////////////
// FIFO
wire audio_playback_en_s;
synch_3 settings_synch (
audio_playback_en,
audio_playback_en_s,
audio_mclk
);
wire [15:0] audio_l;
wire [15:0] audio_r;
wire empty;
dcfifo dcfifo_component (
.wrclk(clk_sys),
.rdclk(audio_mclk),
.data (audio_bus_in),
.wrreq(audio_bus_wr),
.q({audio_l, audio_r}),
.rdreq(audio_req && audio_playback_en_s),
.rdempty(empty),
.wrusedw(audio_buffer_fill),
.aclr(reset || audio_flush)
// .eccstatus(),
// .rdfull(),
// .rdusedw(),
// .wrempty(),
// .wrfull()
);
defparam dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 4096, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 12, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5, dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON", dcfifo_component.wrsync_delaypipe = 5;
reg audio_req = 0;
reg [7:0] mclk_div = 8'hFF;
always @(posedge audio_mclk) begin
// MClk is 12.288 MHz, we want 48kHz
audio_req <= 0;
if (mclk_div > 0) begin
mclk_div <= mclk_div - 8'h1;
end else begin
mclk_div <= 8'hFF;
audio_req <= 1;
end
end
////////////////////////////////////////////////////////////////////////////////////////
// i2s Generation
sound_i2s #(
.SIGNED_INPUT(1)
) sound_i2s (
.audio_sclk(audio_sclk),
.audio_l(audio_playback_en_s && ~empty ? audio_l : 16'h0),
.audio_r(audio_playback_en_s && ~empty ? audio_r : 16'h0),
.audio_lrck(audio_lrck),
.audio_dac (audio_dac)
);
endmodule |
module data_loader #(
// Upper 4 bits of address
parameter ADDRESS_MASK_UPPER_4 = 0,
parameter ADDRESS_SIZE = 28
) (
input wire clk_74a,
input wire clk_memory,
input wire bridge_wr,
input wire bridge_endian_little,
input wire [31:0] bridge_addr,
input wire [31:0] bridge_wr_data,
// These outputs are synced to the memory clock
output reg write_en = 0,
output wire [ADDRESS_SIZE-1:0] write_addr,
output wire [31:0] write_data
);
wire mem_empty;
wire [59:0] fifo_out;
assign {write_addr, write_data} = fifo_out;
dcfifo dcfifo_component (
.wrclk(clk_74a),
.rdclk(clk_memory),
.wrreq(wrreq),
.data ({bridge_addr[27:0], bridge_wr_data}),
.rdreq(~mem_empty),
.q(fifo_out),
.rdempty(mem_empty)
// .wrempty(),
// .aclr(),
// .eccstatus(),
// .rdfull(),
// .rdusedw(),
// .wrfull(),
// .wrusedw()
);
defparam dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone V", dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 60, dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "OFF", dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "OFF", dcfifo_component.use_eab = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
reg prev_bridge_wr = 0;
wire wrreq = ~prev_bridge_wr && bridge_wr && bridge_addr[31:28] == ADDRESS_MASK_UPPER_4;
// Receive APF writes and write to FIFO
always @(posedge clk_74a) begin
prev_bridge_wr <= bridge_wr;
end
always @(posedge clk_memory) begin
// Delay write_en by one cycle so FIFO read finishes
write_en <= ~mem_empty;
end
endmodule |
module sync_fifo #(
parameter WIDTH = 2
) (
input wire clk_write,
input wire clk_read,
input wire write_en,
input wire [WIDTH - 1:0] data,
output reg [WIDTH - 1:0] data_s = 0,
output reg write_en_s = 0
);
reg read_req = 0;
wire empty;
wire [WIDTH - 1:0] fifo_out;
dcfifo dcfifo_component (
.data(data),
.rdclk(clk_read),
.rdreq(read_req),
.wrclk(clk_write),
.wrreq(write_en),
.q(fifo_out),
.rdempty(empty),
.aclr(),
.eccstatus(),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrfull(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Cyclone V", dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WIDTH, dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 5;
reg [1:0] read_state = 0;
localparam READ_DELAY = 1;
localparam READ_WRITE = 2;
always @(posedge clk_read) begin
read_req <= 0;
write_en_s <= 0;
if (~empty) begin
read_state <= READ_DELAY;
read_req <= 1;
end
case (read_state)
READ_DELAY: begin
read_state <= READ_WRITE;
end
READ_WRITE: begin
read_state <= 0;
data_s <= fifo_out;
write_en_s <= 1;
end
endcase
end
endmodule |
module rgb565_to_rgb888 (
input wire [15:0] rgb565,
output wire [23:0] rgb888
);
// Constants taken from https://stackoverflow.com/a/9069480
wire [13:0] red = {2'b0, rgb565[15:11]} * 10'd527 + 14'd23;
wire [13:0] green = {1'b0, rgb565[10:5]} * 10'd259 + 14'd33;
wire [13:0] blue = {2'b0, rgb565[4:0]} * 10'd527 + 14'd23;
assign rgb888[23:16] = red[13:6];
assign rgb888[15:8] = green[13:6];
assign rgb888[7:0] = blue[13:6];
endmodule |
module Mem_Accessor (
input user_clk,
input user_reset,
// memory port - upstream
output reg up_read, // upstream completion request
output reg up_write,
output reg [4:0] up_txtag,
input up_wait,
output [63:0] up_address,
output reg [63:0] up_writedata,
input [4:0] up_rxtag, // upstream completion responses
input [63:0] up_readdata,
input up_ack,
input [2:0] up_err,
// memory port - downstream
input down_read,
input down_write,
input [7:0] down_bar,
input [11:0] down_len,
input [4:0] down_rxtag,
input [63:0] down_address,
input [63:0] down_writedata,
output reg [4:0] down_compl_tag,
output reg [11:0] down_compl_len,
output reg down_compl_ack,
output reg down_compl_err,
output reg [63:0] down_readdata,
output reg cfg_interrupt,
input cfg_interrupt_rdy,
output reg [7:0] cfg_interrupt_di
);
initial up_read = 0;
initial up_write = 0;
initial up_txtag = 0;
initial up_writedata = 64'h0;
initial down_compl_tag = 0;
initial down_compl_len = 0;
initial down_compl_ack = 0;
initial down_compl_err = 0;
initial down_readdata = 64'h0;
reg [63:0] up_addr = 0;
reg [4:0] up_rxtag_r = 0;
reg [2:0] up_err_r = 0;
wire up_sent;
reg [63:0] up_readdata_r = 64'h0;
reg [63:0] SCRATCH = 0;
reg [63:0] VER_REG = 64'h00c0fefe_00000001;
reg in_progress=0;
always @(posedge user_clk) begin
down_compl_ack <= 1'b0;
down_compl_err <= 1'b0;
up_txtag <= 0;
up_read <= 0;
up_write <= 0;
if (down_read) begin
// synthesis translate_off
//$display("RTL READ ADDR: 0x%x - BAR: 0x%x - LEN: %d - TAG: 0x%x",down_address,down_bar,down_len,down_rxtag);
// synthesis translate_on
down_compl_len <= down_len;
down_compl_tag <= down_rxtag;
down_compl_ack <= 1'b1;
case (down_address[11:0])
'h0: down_readdata <= VER_REG;
'h4: down_readdata <= {32'h0,VER_REG[63:32]};
'h8: down_readdata <= SCRATCH;
'hC: down_readdata <= {32'b0,SCRATCH[63:32]};
'h10: down_readdata <= up_addr;
'h14: down_readdata <= {32'b0,up_addr[63:32]};
'h18: down_readdata <= up_writedata;
'h1c: down_readdata <= {32'b0,up_writedata[63:32]};
'h20: down_readdata <= up_readdata_r;
'h24: down_readdata <= {32'b0,up_readdata_r[63:32]};
'h30: down_readdata <= {48'h0,7'b0,up_rxtag_r,in_progress,up_err_r};
'h34: down_readdata <= 64'b0;
'h40: down_readdata <= {32'h0,16'h0,4'h0,cfg_interrupt_di,3'h0,cfg_interrupt};
default: begin
down_readdata <= 64'hFFFFFFFFFFFFFFFF;
down_compl_err <= 1'b0;
end
endcase
if (down_len > 2) down_compl_err <= 1;
end
else if (down_write) begin
// synthesis translate_off
//$display("RTL WRITE ADDR: 0x%x - BAR: 0x%x - LEN: %d - TAG: 0x%x - WRITEDATA: 0x%x",down_address,down_bar,down_len,down_rxtag,down_writedata);
// synthesis translate_on
case (down_address[11:0])
'h8: SCRATCH <= (down_len == 2) ? down_writedata : {SCRATCH[63:32],down_writedata[31:0]};
'hC: SCRATCH[63:32] <= down_writedata[31:0];
'h10: up_addr <= (down_len == 2) ? down_writedata : {up_addr[63:32],down_writedata[31:0]};
'h14: up_addr[63:32] <= down_writedata[31:0];
'h18: up_writedata <= (down_len == 2) ? down_writedata : {up_writedata[63:32],down_writedata[31:0]};
'h1C: up_writedata[63:32] <= down_writedata[31:0];
'h28: begin {up_txtag,up_read,up_write} <= {down_writedata[8:4],down_writedata[1:0]}; in_progress <= down_writedata[1]; end
'h2c: up_writedata[63:32] <= down_writedata[31:0];
'h40: begin cfg_interrupt <= down_writedata[0]; cfg_interrupt_di <= down_writedata[11:4]; end
endcase
end
if (cfg_interrupt_rdy) begin
cfg_interrupt <= 0;
end
if (up_ack) begin
up_readdata_r <= up_readdata;
up_rxtag_r <= up_rxtag;
up_err_r <= up_err;
in_progress <= 0;
cfg_interrupt <= 1'b1;
cfg_interrupt_di <= 0;
end
if (user_reset) begin
down_compl_ack <= 1'b0;
down_compl_err <= 1'b0;
SCRATCH <= 64'h0;
in_progress <= 0;
cfg_interrupt <= 0;
cfg_interrupt_di <= 8'h0;
end
end
assign up_address = up_addr;
endmodule |
module TLP_Processor (
input pcie_clk,
input pcie_rst,
input [12:0] pcie_busdev,
input [7:0] rx_bar,
input [0:0] rx_tlast,
input [0:0] rx_tvalid,
output rx_tready,
input [63:0] rx_tdata,
output [0:0] tx_tlast,
output [0:0] tx_tvalid,
input tx_tready,
output [63:0] tx_tdata,
output reg [7:0] tx_tkeep,
// memory port - upstream
input up_read, // upstream completion request
input up_write,
input [4:0] up_txtag,
output up_wait,
input [63:0] up_address,
input [63:0] up_writedata,
output reg [4:0] up_rxtag, // upstream completion responses
output reg [63:0] up_readdata,
output reg up_ack,
output reg [2:0] up_err,
// memory port - downstream
output reg down_read,
output reg down_write,
output reg [7:0] down_bar,
output reg [11:0] down_len,
output reg [4:0] down_rxtag,
output reg [63:0] down_address,
output reg [63:0] down_writedata,
input [4:0] down_compl_tag,
input [11:0] down_compl_len,
input down_compl_ack,
input down_compl_err,
input [63:0] down_readdata
);
function [31:0] byteswap32(input [31:0] data);
byteswap32 = { data[7:0],
data[15:8],
data[23:16],
data[31:24]};
endfunction
`define TX_IDLE 4'h0
`define TX_MEMREAD_3DW 4'h1
`define TX_MEMREAD_4DW 4'h2
`define TX_MEMWRITE_3DW_0 4'h3
`define TX_MEMWRITE_3DW_1 4'h4
`define TX_MEMWRITE_4DW_0 4'h5
`define TX_MEMWRITE_4DW_1 4'h6
`define TX_COMPLERR_3DW 4'h7
`define TX_RCOMPL64_3DW_0 4'h8
`define TX_RCOMPL64_3DW_1 4'h9
`define TX_RCOMPL32_3DW_0 4'hB
`define TX_RCOMPL32_3DW_1 4'hC
wire rx_eop;
wire rx_val;
reg rx_ready;
wire [63:0] rx_data;
reg tx_sop;
reg tx_eop;
reg tx_val;
wire tx_ready;
reg [63:0] tx_data;
assign rx_eop = rx_tlast[0];
assign rx_val = rx_tvalid[0];
assign rx_tready = rx_ready;
assign rx_data = rx_tdata;
assign tx_tlast = tx_eop;
assign tx_tvalid = tx_val;
assign tx_ready = tx_tready;
assign tx_tdata = tx_data;
reg rx_sop = 1'b1;
always @(posedge pcie_clk) begin
if (rx_tvalid && rx_tready && rx_tlast) rx_sop <= 1'b1;
else if (rx_tvalid && rx_tready) rx_sop <= 1'b0;
if (pcie_rst) rx_sop <= 1'b1;
end
`define UPSTREAM_DECODE if (compl_ready) begin \
tx_sop <= 1'b1; \
tx_eop <= 1'b0; \
tx_val <= 1'b1; \
compl_grab <= 1'b1; \
compl_reqidtag_r <= {reqid_ram[compl_tag],3'b000,compl_tag}; \
compl_readdata_r <= compl_readdata; \
laddr_bits <= laddr_ram[compl_tag]; \
if (compl_err || (down_compl_len > 2)) begin \
tx_data[31:0] <= {3'b000 ,5'b01010 ,1'b0, 3'b000, 4'b0000, 1'b0,1'b0,2'b00,2'b00,10'd0}; \
tx_data[63:32] <= {{pcie_busdev,3'b0},3'b001,1'b0,12'h008}; \
tx_state <= `TX_COMPLERR_3DW; \
end \
else if (down_compl_len == 2) begin \
tx_data[31:0] <= {3'b010 ,5'b01010 ,1'b0, 3'b000, 4'b0000, 1'b0,1'b0,2'b00,2'b00,10'd2}; \
tx_data[63:32] <= {{pcie_busdev,3'b0},3'b000,1'b0,12'h008}; \
tx_state <= `TX_RCOMPL64_3DW_0; \
end \
else begin \
tx_data[31:0] <= {3'b010 ,5'b01010 ,1'b0, 3'b000, 4'b0000, 1'b0,1'b0,2'b00,2'b00,10'd1}; \
tx_data[63:32] <= {{pcie_busdev,3'b0},3'b000,1'b0,12'h004}; \
tx_state <= `TX_RCOMPL32_3DW_0; \
end \
end \
else if (upp_read & upp_ready) begin \
tx_sop <= 1'b1; \
tx_eop <= 1'b0; \
tx_val <= 1'b1; \
upp_grab <= 1'b1; \
uppp_address <= upp_address; \
if (~|upp_address[63:32]) begin \
tx_data[31:0] <= {1'b0 ,2'b00 ,5'b00000 ,1'b0, 3'b000, 4'b0000, 1'b0,1'b0,2'b00,2'b00,10'd2}; \
tx_data[63:32] <= {{pcie_busdev,3'b0},3'b0,upp_txtag,4'hF,4'hF}; \
tx_state <= `TX_MEMREAD_3DW; \
end else begin \
tx_data[31:0] <= {1'b0 ,2'b01 ,5'b00000 ,1'b0, 3'b000, 4'b0000, 1'b0,1'b0,2'b00,2'b00,10'd2}; \
tx_data[63:32] <= {{pcie_busdev,3'b0},3'b0,upp_txtag,4'hF,4'hF}; \
tx_state <= `TX_MEMREAD_4DW; \
end \
end \
else if (upp_write & upp_ready) begin \
tx_sop <= 1'b1; \
tx_eop <= 1'b0; \
tx_val <= 1'b1; \
upp_grab <= 1'b1; \
uppp_address <= upp_address; \
uppp_writedata <= upp_writedata; \
if (~|upp_address[63:32]) begin \
tx_data[31:0] <= {1'b0 ,2'b10 ,5'b00000 ,1'b0, 3'b000, 4'b0000, 1'b0,1'b0,2'b00,2'b00,10'd2}; \
tx_data[63:32] <= {{pcie_busdev,3'b0},3'b0,upp_txtag,4'hF,4'hF}; \
tx_state <= `TX_MEMWRITE_3DW_0; \
end else begin \
tx_data[31:0] <= {1'b0 ,2'b11 ,5'b00000 ,1'b0, 3'b000, 4'b0000, 1'b0,1'b0,2'b00,2'b00,10'd2}; \
tx_data[63:32] <= {{pcie_busdev,3'b0},3'b0,upp_txtag,4'hF,4'hF}; \
tx_state <= `TX_MEMWRITE_4DW_0; \
end \
end \
else begin \
tx_sop <= 1'b0; \
tx_eop <= 1'b0; \
tx_val <= 1'b0; \
tx_state <= `TX_IDLE; \
end
reg [3:0] tx_state;
initial tx_data = 64'h0;
initial up_readdata = 64'h0;
wire upp_read; // upstream completion request
wire upp_write;
wire [4:0] upp_txtag;
wire [63:0] upp_address;
wire [63:0] upp_writedata;
wire upp_ready;
wire rdempty_0,rdempty_1;
reg upp_grab;
reg [63:0] uppp_writedata;
reg [63:0] uppp_address;
wire [23:0] compl_reqidtag;
wire [11:0] compl_len;
wire compl_err;
wire [63:0] compl_readdata;
reg compl_grab;
wire compl_ready;
reg [23:0] compl_reqidtag_r;
reg [63:0] compl_readdata_r;
wire [4:0] compl_tag;
compl_fifo cfifo (
.clk(pcie_clk),
.srst(pcie_rst),
.din({down_compl_tag,down_compl_len,down_compl_err,down_readdata}),
.wr_en(down_compl_ack),
.rd_en(compl_grab),
.dout({compl_tag,compl_len,compl_err,compl_readdata}),
.full(),
.empty(rdempty_1)
);
assign compl_ready = ~rdempty_1;
up_fifo ufifo (
.clk(pcie_clk),
.srst(pcie_rst),
.din({up_read, up_write, up_txtag, up_address, up_writedata}),
.wr_en(up_read | up_write),
.rd_en(upp_grab),
.dout({upp_read, upp_write, upp_txtag, upp_address, upp_writedata}),
.full(up_wait),
.empty(rdempty_0)
);
assign upp_ready = ~rdempty_0;
reg [4:0] laddr_ram[0:31];
reg [15:0] reqid_ram[0:31];
reg [4:0] laddr_bits;
always @(posedge pcie_clk or posedge pcie_rst) begin
if (pcie_rst) begin
tx_state <= `TX_IDLE;
tx_sop <= 1'b0;
tx_eop <= 1'b0;
tx_val <= 1'b0;
upp_grab <= 1'b0;
compl_grab <= 1'b0;
tx_tkeep <= 8'hFF;
end else begin
tx_tkeep <= 8'hFF;
upp_grab <= 1'b0;
compl_grab <= 1'b0;
case (tx_state)
`TX_IDLE: begin
if (tx_ready) begin
`UPSTREAM_DECODE
end
end
`TX_RCOMPL32_3DW_0: begin
if (tx_ready) begin
tx_sop <= 1'b0;
tx_eop <= 1'b1;
tx_val <= 1'b1;
tx_data <= {byteswap32(compl_readdata_r[31:0]),{compl_reqidtag_r,1'b0,laddr_bits,2'b00}};
tx_state <= `TX_IDLE;
end
end
`TX_RCOMPL64_3DW_0: begin
if (tx_ready) begin
tx_sop <= 1'b0;
tx_eop <= 1'b0;
tx_val <= 1'b1;
tx_data[31:0] <= {compl_reqidtag_r,1'b0,laddr_bits,2'b00};
tx_data[63:32] <= byteswap32(compl_readdata_r[31:0]);
tx_state <= `TX_RCOMPL64_3DW_1;
end
end
`TX_RCOMPL64_3DW_1: begin
if (tx_ready) begin
tx_sop <= 1'b0;
tx_eop <= 1'b1;
tx_val <= 1'b1;
tx_tkeep <= 8'h0F;
tx_data[31:0] <= byteswap32(compl_readdata_r[63:32]);
tx_state <= `TX_IDLE;
end
end
`TX_COMPLERR_3DW: begin
if (tx_ready) begin
tx_sop <= 1'b0;
tx_eop <= 1'b1;
tx_val <= 1'b1;
tx_tkeep <= 8'h0F;
tx_data[31:0] <= {compl_reqidtag_r,1'b0,laddr_bits,2'b00};
tx_state <= `TX_IDLE;
end
end
`TX_MEMREAD_3DW: begin
if (tx_ready) begin
tx_data[31:0] <= {uppp_address[31:2],2'b0};
tx_sop <= 1'b0;
tx_eop <= 1'b1;
tx_val <= 1'b1;
tx_tkeep <= 8'h0F;
tx_state <= `TX_IDLE;
end
end
`TX_MEMREAD_4DW: begin
if (tx_ready) begin
tx_data[63:32] <= {uppp_address[31:2],2'b0};
tx_data[31:0] <= uppp_address[63:32];
tx_sop <= 1'b0;
tx_eop <= 1'b1;
tx_val <= 1'b1;
tx_state <= `TX_IDLE;
end
end
`TX_MEMWRITE_3DW_0: begin
if (tx_ready) begin
tx_data[31:0] <= {uppp_address[31:2],2'b0};
tx_data[63:32] <= byteswap32(uppp_writedata[31:0]);
tx_sop <= 1'b0;
tx_eop <= 1'b0;
tx_val <= 1'b1;
tx_state <= `TX_MEMWRITE_3DW_1;
end
end
`TX_MEMWRITE_3DW_1: begin
if (tx_ready) begin
tx_data[31:0] <= byteswap32(uppp_writedata[63:32]);
tx_sop <= 1'b0;
tx_eop <= 1'b1;
tx_val <= 1'b1;
tx_tkeep <= 8'h0F;
tx_state <= `TX_IDLE;
end
end
`TX_MEMWRITE_4DW_0: begin
if (tx_ready) begin
tx_data[31:0] <= uppp_address[63:32];
tx_data[63:32] <= {uppp_address[31:2],2'b0};
tx_sop <= 1'b0;
tx_eop <= 1'b0;
tx_val <= 1'b1;
tx_state <= `TX_MEMWRITE_4DW_1;
end
end
`TX_MEMWRITE_4DW_1: begin
if (tx_ready) begin
tx_data <= {byteswap32(uppp_writedata[63:32]),byteswap32(uppp_writedata[31:0])};
tx_sop <= 1'b0;
tx_eop <= 1'b1;
tx_val <= 1'b1;
tx_state <= `TX_IDLE;
end
end
default: tx_state <= `TX_IDLE;
endcase
end
end
`define RX_IDLE 4'h0
`define RX_COMPID_HEADER 4'h1
`define RX_COMPID_DATA 4'h2
`define RX_MEMREAD_3DW 4'h3
`define RX_MEMREAD_4DW 4'h4
`define RX_MEMWRITE_3DW_0 4'h5
`define RX_MEMWRITE_3DW_1 4'h6
`define RX_MEMWRITE_4DW_0 4'h7
`define RX_MEMWRITE_4DW_1 4'h8
reg [3:0] rx_state;
`define DOWNSTREAM_DECODE if (rx_val & rx_ready & rx_sop) begin \
case (rx_data[31:24]) \
{3'b010,5'b01010}: /* Completion w/data */ \
begin \
if (rx_data[9:0] != 10'd2) begin /* only 64-bit accesses at this time */ \
up_ack <= 1'b1; \
up_err <= 3'b111; /* set error bits */ \
rx_state <= `RX_IDLE; \
end \
else rx_state <= `RX_COMPID_HEADER; \
end \
{3'b000,5'b01010}: /* Completion wo/data (Most likely completion error) */ \
begin \
up_err <= rx_data[15+32:13+32]; /* set error bits */ \
up_ack <= 1'b1; \
rx_state <= `RX_IDLE; \
end \
{3'b010,5'b00000}: /* Memory Write Request 3DW (32-bit) */ \
begin \
down_bar <= rx_bar; \
down_len <= rx_data[11:0]; \
down_rxtag <= rx_data[44:40]; \
rx_state <= `RX_MEMWRITE_3DW_0; \
end \
{3'b000,5'b00000}: /* Memory Read Request 3DW (32-bit) */ \
begin \
down_bar <= rx_bar; \
down_len <= rx_data[11:0]; \
down_rxtag <= rx_data[44:40]; \
reqid_ram[rx_data[44:40]] <= rx_data[63:48]; \
rx_state <= `RX_MEMREAD_3DW; \
end \
{3'b011,5'b00000}: /* Memory Write Request 4DW (64-bit) */ \
begin \
down_bar <= rx_bar; \
down_len <= rx_data[11:0]; \
down_rxtag <= rx_data[44:40]; \
rx_state <= `RX_MEMWRITE_4DW_0; \
end \
{3'b001,5'b00000}: /* Memory Read Request 4DW (64-bit) */ \
begin \
down_bar <= rx_bar; \
down_len <= rx_data[11:0]; \
down_rxtag <= rx_data[44:40]; \
reqid_ram[rx_data[44:40]] <= rx_data[63:48]; \
rx_state <= `RX_MEMREAD_4DW; \
end \
default: \
begin \
/* All others unsupported, may need to send unsupported request completion */ \
/* However, hoping unlikely to get other TLP types, otherwise TLP timeout */ \
rx_state <= `RX_IDLE; \
end \
endcase \
end else rx_state <= `RX_IDLE;
always @(posedge pcie_clk or posedge pcie_rst) begin
if (pcie_rst) begin
rx_state <= `RX_IDLE;
rx_ready <= 1'b1;
up_err <= 0;
up_ack <= 1'b0;
up_rxtag <= 0;
down_bar <= 8'h00;
down_len <= 12'h000;
down_rxtag <= 5'h0;
down_read <= 1'b0;
down_write <= 1'b0;
down_address <= 32'h0;
down_writedata <= 32'h0;
end else begin
up_ack <= 1'b0;
down_read <= 1'b0;
down_write <= 1'b0;
case (rx_state)
`RX_IDLE: begin
rx_ready <= 1'b1;
up_err <= 0;
`DOWNSTREAM_DECODE
end
`RX_MEMREAD_3DW: begin
if (rx_val & rx_ready) begin
down_read <= 1'b1;
down_address <= {32'h0000_0000,rx_data[31:2],2'b00};
`DOWNSTREAM_DECODE
end
end
`RX_MEMREAD_4DW: begin
if (rx_val & rx_ready) begin
down_read <= 1'b1;
down_address <= {rx_data[31:0],rx_data[63:34],2'b00};
`DOWNSTREAM_DECODE
end
end
`RX_MEMWRITE_3DW_0: begin
if (rx_val & rx_ready) begin
down_address <= {32'h0000_0000,rx_data[31:2],2'b00};
down_writedata[31:0] <= byteswap32(rx_data[63:32]);
if (down_len == 2) begin
rx_state <= `RX_MEMWRITE_3DW_1;
end
else if (down_len == 1) begin
down_write <= 1'b1;
`DOWNSTREAM_DECODE
end
else rx_state <= `RX_IDLE;
end
end
`RX_MEMWRITE_3DW_1: begin
if (rx_val & rx_ready) begin
down_write <= 1'b1;
down_writedata[63:32] <= byteswap32(rx_data[31:0]);
`DOWNSTREAM_DECODE
end
end
`RX_MEMWRITE_4DW_0: begin
if (rx_val & rx_ready) begin
down_address <= {rx_data[31:0],rx_data[63:34],2'b00};
rx_state <= `RX_MEMWRITE_4DW_1;
end
end
`RX_MEMWRITE_4DW_1: begin
if (rx_val & rx_ready) begin
down_write <= 1'b1;
if (down_len == 2) begin
down_writedata <= {byteswap32(rx_data[63:32]),byteswap32(rx_data[31:0])};
end
else if (down_len == 1) begin
down_writedata[31:0] <= byteswap32(rx_data[31:0]);
end
`DOWNSTREAM_DECODE
end
end
`RX_COMPID_HEADER: begin
if (rx_val & rx_ready) begin
up_rxtag <= rx_data[12:8];
up_readdata[31:0] <= byteswap32(rx_data[63:32]);
rx_state <= `RX_COMPID_DATA;
end
end
`RX_COMPID_DATA: begin
if (rx_val & rx_ready) begin
up_readdata[63:32] <= byteswap32(rx_data[31:0]);
up_ack <= 1'b1;
`DOWNSTREAM_DECODE
end
end
default: `DOWNSTREAM_DECODE
endcase
if (down_read) laddr_ram[down_rxtag] <= down_address[6:2];
end
end
endmodule |
module VX_fpu_fpnew
import VX_fpu_pkg::*;
import fpnew_pkg::*;
import cf_math_pkg::*;
import defs_div_sqrt_mvp::*;
#(
parameter NUM_LANES = 1,
parameter TAG_WIDTH = 1,
parameter OUT_BUF = 0
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
input wire [NUM_LANES-1:0] mask_in,
input wire [TAG_WIDTH-1:0] tag_in,
input wire [`INST_FPU_BITS-1:0] op_type,
input wire [`INST_FMT_BITS-1:0] fmt,
input wire [`INST_FRM_BITS-1:0] frm,
input wire [NUM_LANES-1:0][`XLEN-1:0] dataa,
input wire [NUM_LANES-1:0][`XLEN-1:0] datab,
input wire [NUM_LANES-1:0][`XLEN-1:0] datac,
output wire [NUM_LANES-1:0][`XLEN-1:0] result,
output wire has_fflags,
output wire [`FP_FLAGS_BITS-1:0] fflags,
output wire [TAG_WIDTH-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
localparam LATENCY_FDIVSQRT = `MAX(`LATENCY_FDIV, `LATENCY_FSQRT);
localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAG_WIDTH;
localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
Width: unsigned'(`XLEN),
EnableVectors: 1'b0,
`ifdef XLEN_64
EnableNanBox: 1'b1,
`ifdef FLEN_64
FpFmtMask: 5'b11000,
`else
FpFmtMask: 5'b11000, // TODO: adding FP64 to fix CVT bug in FpNew
`endif
IntFmtMask: 4'b0011
`else
EnableNanBox: 1'b0,
FpFmtMask: 5'b10000,
IntFmtMask: 4'b0010
`endif
};
localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
PipeRegs:'{'{`LATENCY_FMA, 0, 0, 0, 0}, // ADDMUL
'{default: unsigned'(LATENCY_FDIVSQRT)}, // DIVSQRT
'{default: `LATENCY_FNCP}, // NONCOMP
'{default: `LATENCY_FCVT}}, // CONV
UnitTypes:'{'{default: fpnew_pkg::PARALLEL}, // ADDMUL
'{default: fpnew_pkg::MERGED}, // DIVSQRT
'{default: fpnew_pkg::PARALLEL}, // NONCOMP
'{default: fpnew_pkg::MERGED}}, // CONV
PipeConfig: fpnew_pkg::DISTRIBUTED
};
wire fpu_ready_in, fpu_valid_in;
wire fpu_ready_out, fpu_valid_out;
reg [TAG_WIDTH-1:0] fpu_tag_in, fpu_tag_out;
reg [2:0][NUM_LANES-1:0][`XLEN-1:0] fpu_operands;
wire [NUM_LANES-1:0][`XLEN-1:0] fpu_result;
fpnew_pkg::status_t fpu_status;
fpnew_pkg::operation_e fpu_op;
reg [`INST_FRM_BITS-1:0] fpu_rnd;
reg fpu_op_mod;
reg fpu_has_fflags, fpu_has_fflags_out;
fpnew_pkg::fp_format_e fpu_src_fmt, fpu_dst_fmt;
fpnew_pkg::int_format_e fpu_int_fmt;
`UNUSED_VAR (fmt)
always @(*) begin
fpu_op = 'x;
fpu_rnd = frm;
fpu_op_mod = 0;
fpu_has_fflags = 1;
fpu_operands[0] = dataa;
fpu_operands[1] = datab;
fpu_operands[2] = datac;
fpu_dst_fmt = fpnew_pkg::FP32;
fpu_int_fmt = fpnew_pkg::INT32;
`ifdef FLEN_64
if (fmt[0]) begin
fpu_dst_fmt = fpnew_pkg::FP64;
end
`endif
`ifdef XLEN_64
if (fmt[1]) begin
fpu_int_fmt = fpnew_pkg::INT64;
end
`endif
fpu_src_fmt = fpu_dst_fmt;
case (op_type)
`INST_FPU_ADD: begin
fpu_op = fpnew_pkg::ADD;
fpu_operands[1] = dataa;
fpu_operands[2] = datab;
end
`INST_FPU_SUB: begin
fpu_op = fpnew_pkg::ADD;
fpu_operands[1] = dataa;
fpu_operands[2] = datab;
fpu_op_mod = 1;
end
`INST_FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end
`INST_FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end
`INST_FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end
`INST_FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end
`INST_FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end
`INST_FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end
`INST_FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end
`ifdef FLEN_64
`INST_FPU_F2F: begin fpu_op = fpnew_pkg::F2F; fpu_src_fmt = fmt[0] ? fpnew_pkg::FP32 : fpnew_pkg::FP64; end
`endif
`INST_FPU_F2I,
`INST_FPU_F2U: begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = op_type[0]; end
`INST_FPU_I2F,
`INST_FPU_U2F: begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = op_type[0]; end
`INST_FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end
`INST_FPU_MISC:begin
case (frm)
0,1,2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = {1'b0, frm[1:0]}; fpu_has_fflags = 0; end // FSGNJ
3: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end // CLASS
4,5: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = 3'b011; fpu_op_mod = ~frm[0]; fpu_has_fflags = 0; end // FMV.X.W, FMV.W.X
6,7: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = {2'b00, frm[0]}; end // MIN, MAX
endcase
end
default:;
endcase
end
`UNUSED_VAR (mask_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin
wire [(TAG_WIDTH+1)-1:0] fpu_tag;
wire fpu_valid_out_uq;
wire fpu_ready_in_uq;
fpnew_pkg::status_t fpu_status_uq;
`UNUSED_VAR (fpu_tag)
`UNUSED_VAR (fpu_valid_out_uq)
`UNUSED_VAR (fpu_ready_in_uq)
`UNUSED_VAR (fpu_status_uq)
fpnew_top #(
.Features (FPU_FEATURES),
.Implementation (FPU_IMPLEMENTATION),
.TagType (logic[(TAG_WIDTH+1)-1:0]),
.TrueSIMDClass (1),
.EnableSIMDMask (1)
) fpnew_core (
.clk_i (clk),
.rst_ni (~reset),
.operands_i ({fpu_operands[2][i], fpu_operands[1][i], fpu_operands[0][i]}),
.rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)),
.op_i (fpu_op),
.op_mod_i (fpu_op_mod),
.src_fmt_i (fpu_src_fmt),
.dst_fmt_i (fpu_dst_fmt),
.int_fmt_i (fpu_int_fmt),
.vectorial_op_i (1'b0),
.simd_mask_i (mask_in[i]),
.tag_i ({fpu_tag_in, fpu_has_fflags}),
.in_valid_i (fpu_valid_in),
.in_ready_o (fpu_ready_in_uq),
.flush_i (reset),
.result_o (fpu_result[i]),
.status_o (fpu_status_uq),
.tag_o (fpu_tag),
.out_valid_o (fpu_valid_out_uq),
.out_ready_i (fpu_ready_out),
`UNUSED_PIN (busy_o)
);
if (i == 0) begin
assign {fpu_tag_out, fpu_has_fflags_out} = fpu_tag;
assign fpu_valid_out = fpu_valid_out_uq;
assign fpu_ready_in = fpu_ready_in_uq;
assign fpu_status = fpu_status_uq;
end
end
assign fpu_valid_in = valid_in;
assign ready_in = fpu_ready_in;
assign fpu_tag_in = tag_in;
VX_elastic_buffer #(
.DATAW (RSP_DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) rsp_buf (
.clk (clk),
.reset (reset),
.valid_in (fpu_valid_out),
.ready_in (fpu_ready_out),
.data_in ({fpu_result, fpu_has_fflags_out, fpu_status, fpu_tag_out}),
.data_out ({result, has_fflags, fflags, tag_out}),
.valid_out (valid_out),
.ready_out (ready_out)
);
endmodule |
module VX_fpu_dpi import VX_fpu_pkg::*; #(
parameter NUM_LANES = 1,
parameter TAG_WIDTH = 1,
parameter OUT_BUF = 0
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
input wire [NUM_LANES-1:0] mask_in,
input wire [TAG_WIDTH-1:0] tag_in,
input wire [`INST_FPU_BITS-1:0] op_type,
input wire [`INST_FMT_BITS-1:0] fmt,
input wire [`INST_FRM_BITS-1:0] frm,
input wire [NUM_LANES-1:0][`XLEN-1:0] dataa,
input wire [NUM_LANES-1:0][`XLEN-1:0] datab,
input wire [NUM_LANES-1:0][`XLEN-1:0] datac,
output wire [NUM_LANES-1:0][`XLEN-1:0] result,
output wire has_fflags,
output wire [`FP_FLAGS_BITS-1:0] fflags,
output wire [TAG_WIDTH-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
localparam FPU_FMA = 0;
localparam FPU_DIVSQRT = 1;
localparam FPU_CVT = 2;
localparam FPU_NCP = 3;
localparam NUM_FPC = 4;
localparam FPC_BITS = `LOG2UP(NUM_FPC);
localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAG_WIDTH;
wire [NUM_FPC-1:0] per_core_ready_in;
wire [NUM_FPC-1:0][NUM_LANES-1:0][`XLEN-1:0] per_core_result;
wire [NUM_FPC-1:0][TAG_WIDTH-1:0] per_core_tag_out;
reg [NUM_FPC-1:0] per_core_ready_out;
wire [NUM_FPC-1:0] per_core_valid_out;
wire [NUM_FPC-1:0] per_core_has_fflags;
fflags_t [NUM_FPC-1:0] per_core_fflags;
wire div_ready_in, sqrt_ready_in;
wire [NUM_LANES-1:0][`XLEN-1:0] div_result, sqrt_result;
wire [TAG_WIDTH-1:0] div_tag_out, sqrt_tag_out;
wire div_ready_out, sqrt_ready_out;
wire div_valid_out, sqrt_valid_out;
wire div_has_fflags, sqrt_has_fflags;
fflags_t div_fflags, sqrt_fflags;
reg [FPC_BITS-1:0] core_select;
reg is_fadd, is_fsub, is_fmul, is_fmadd, is_fmsub, is_fnmadd, is_fnmsub;
reg is_div, is_fcmp, is_itof, is_utof, is_ftoi, is_ftou, is_f2f;
reg dst_fmt, int_fmt;
reg [NUM_LANES-1:0][63:0] operands [3];
always @(*) begin
for (integer i = 0; i < NUM_LANES; ++i) begin
operands[0][i] = 64'(dataa[i]);
operands[1][i] = 64'(datab[i]);
operands[2][i] = 64'(datac[i]);
end
end
`UNUSED_VAR (fmt)
always @(*) begin
is_fadd = 0;
is_fsub = 0;
is_fmul = 0;
is_fmadd = 0;
is_fmsub = 0;
is_fnmadd = 0;
is_fnmsub = 0;
is_div = 0;
is_fcmp = 0;
is_itof = 0;
is_utof = 0;
is_ftoi = 0;
is_ftou = 0;
is_f2f = 0;
dst_fmt = 0;
int_fmt = 0;
`ifdef FLEN_64
dst_fmt = fmt[0];
`endif
`ifdef XLEN_64
int_fmt = fmt[1];
`endif
case (op_type)
`INST_FPU_ADD: begin core_select = FPU_FMA; is_fadd = 1; end
`INST_FPU_SUB: begin core_select = FPU_FMA; is_fsub = 1; end
`INST_FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end
`INST_FPU_MADD: begin core_select = FPU_FMA; is_fmadd = 1; end
`INST_FPU_MSUB: begin core_select = FPU_FMA; is_fmsub = 1; end
`INST_FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = 1; end
`INST_FPU_NMSUB: begin core_select = FPU_FMA; is_fnmsub = 1; end
`INST_FPU_DIV: begin core_select = FPU_DIVSQRT; is_div = 1; end
`INST_FPU_SQRT: begin core_select = FPU_DIVSQRT; end
`INST_FPU_CMP: begin core_select = FPU_NCP; is_fcmp = 1; end
`INST_FPU_F2I: begin core_select = FPU_CVT; is_ftoi = 1; end
`INST_FPU_F2U: begin core_select = FPU_CVT; is_ftou = 1; end
`INST_FPU_I2F: begin core_select = FPU_CVT; is_itof = 1; end
`INST_FPU_U2F: begin core_select = FPU_CVT; is_utof = 1; end
`INST_FPU_F2F: begin core_select = FPU_CVT; is_f2f = 1; end
default: begin core_select = FPU_NCP; end
endcase
end
generate
begin : fma
reg [NUM_LANES-1:0][`XLEN-1:0] result_fma;
wire [NUM_LANES-1:0][63:0] result_fadd;
wire [NUM_LANES-1:0][63:0] result_fsub;
wire [NUM_LANES-1:0][63:0] result_fmul;
wire [NUM_LANES-1:0][63:0] result_fmadd;
wire [NUM_LANES-1:0][63:0] result_fmsub;
wire [NUM_LANES-1:0][63:0] result_fnmadd;
wire [NUM_LANES-1:0][63:0] result_fnmsub;
fflags_t [NUM_LANES-1:0] fflags_fma;
fflags_t [NUM_LANES-1:0] fflags_fadd;
fflags_t [NUM_LANES-1:0] fflags_fsub;
fflags_t [NUM_LANES-1:0] fflags_fmul;
fflags_t [NUM_LANES-1:0] fflags_fmadd;
fflags_t [NUM_LANES-1:0] fflags_fmsub;
fflags_t [NUM_LANES-1:0] fflags_fnmadd;
fflags_t [NUM_LANES-1:0] fflags_fnmsub;
wire fma_valid = (valid_in && core_select == FPU_FMA);
wire fma_ready = per_core_ready_out[FPU_FMA] || ~per_core_valid_out[FPU_FMA];
wire fma_fire = fma_valid && fma_ready;
always @(*) begin
for (integer i = 0; i < NUM_LANES; ++i) begin
dpi_fadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fadd[i], fflags_fadd[i]);
dpi_fsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fsub[i], fflags_fsub[i]);
dpi_fmul (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fmul[i], fflags_fmul[i]);
dpi_fmadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmadd[i], fflags_fmadd[i]);
dpi_fmsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmsub[i], fflags_fmsub[i]);
dpi_fnmadd (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmadd[i], fflags_fnmadd[i]);
dpi_fnmsub (fma_fire, int'(dst_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmsub[i], fflags_fnmsub[i]);
result_fma[i] = is_fadd ? result_fadd[i][`XLEN-1:0] :
is_fsub ? result_fsub[i][`XLEN-1:0] :
is_fmul ? result_fmul[i][`XLEN-1:0] :
is_fmadd ? result_fmadd[i][`XLEN-1:0] :
is_fmsub ? result_fmsub[i][`XLEN-1:0] :
is_fnmadd ? result_fnmadd[i][`XLEN-1:0] :
is_fnmsub ? result_fnmsub[i][`XLEN-1:0] :
'0;
fflags_fma[i] = is_fadd ? fflags_fadd[i] :
is_fsub ? fflags_fsub[i] :
is_fmul ? fflags_fmul[i] :
is_fmadd ? fflags_fmadd[i] :
is_fmsub ? fflags_fmsub[i] :
is_fnmadd ? fflags_fnmadd[i] :
is_fnmsub ? fflags_fnmsub[i] :
'0;
end
end
fflags_t fflags_merged;
`FPU_MERGE_FFLAGS(fflags_merged, fflags_fma, mask_in, NUM_LANES);
VX_shift_register #(
.DATAW (1 + TAG_WIDTH + NUM_LANES * `XLEN + $bits(fflags_t)),
.DEPTH (`LATENCY_FMA),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (fma_ready),
.data_in ({fma_valid, tag_in, result_fma, fflags_merged}),
.data_out ({per_core_valid_out[FPU_FMA], per_core_tag_out[FPU_FMA], per_core_result[FPU_FMA], per_core_fflags[FPU_FMA]})
);
assign per_core_has_fflags[FPU_FMA] = 1;
assign per_core_ready_in[FPU_FMA] = fma_ready;
end
endgenerate
generate
begin : fdiv
reg [NUM_LANES-1:0][`XLEN-1:0] result_fdiv_r;
wire [NUM_LANES-1:0][63:0] result_fdiv;
fflags_t [NUM_LANES-1:0] fflags_fdiv;
wire fdiv_valid = (valid_in && core_select == FPU_DIVSQRT) && is_div;
wire fdiv_ready = div_ready_out || ~div_valid_out;
wire fdiv_fire = fdiv_valid && fdiv_ready;
always @(*) begin
for (integer i = 0; i < NUM_LANES; ++i) begin
dpi_fdiv (fdiv_fire, int'(dst_fmt), operands[0][i], operands[1][i], frm, result_fdiv[i], fflags_fdiv[i]);
result_fdiv_r[i] = result_fdiv[i][`XLEN-1:0];
end
end
fflags_t fflags_merged;
`FPU_MERGE_FFLAGS(fflags_merged, fflags_fdiv, mask_in, NUM_LANES);
VX_shift_register #(
.DATAW (1 + TAG_WIDTH + NUM_LANES * `XLEN + $bits(fflags_t)),
.DEPTH (`LATENCY_FDIV),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (fdiv_ready),
.data_in ({fdiv_valid, tag_in, result_fdiv_r, fflags_merged}),
.data_out ({div_valid_out, div_tag_out, div_result, div_fflags})
);
assign div_has_fflags = 1;
assign div_ready_in = fdiv_ready;
end
endgenerate
generate
begin : fsqrt
reg [NUM_LANES-1:0][`XLEN-1:0] result_fsqrt_r;
wire [NUM_LANES-1:0][63:0] result_fsqrt;
fflags_t [NUM_LANES-1:0] fflags_fsqrt;
wire fsqrt_valid = (valid_in && core_select == FPU_DIVSQRT) && ~is_div;
wire fsqrt_ready = sqrt_ready_out || ~sqrt_valid_out;
wire fsqrt_fire = fsqrt_valid && fsqrt_ready;
always @(*) begin
for (integer i = 0; i < NUM_LANES; ++i) begin
dpi_fsqrt (fsqrt_fire, int'(dst_fmt), operands[0][i], frm, result_fsqrt[i], fflags_fsqrt[i]);
result_fsqrt_r[i] = result_fsqrt[i][`XLEN-1:0];
end
end
fflags_t fflags_merged;
`FPU_MERGE_FFLAGS(fflags_merged, fflags_fsqrt, mask_in, NUM_LANES);
VX_shift_register #(
.DATAW (1 + TAG_WIDTH + NUM_LANES * `XLEN + $bits(fflags_t)),
.DEPTH (`LATENCY_FSQRT),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (fsqrt_ready),
.data_in ({fsqrt_valid, tag_in, result_fsqrt_r, fflags_merged}),
.data_out ({sqrt_valid_out, sqrt_tag_out, sqrt_result, sqrt_fflags})
);
assign sqrt_has_fflags = 1;
assign sqrt_ready_in = fsqrt_ready;
end
endgenerate
generate
begin : fcvt
reg [NUM_LANES-1:0][`XLEN-1:0] result_fcvt;
wire [NUM_LANES-1:0][63:0] result_itof;
wire [NUM_LANES-1:0][63:0] result_utof;
wire [NUM_LANES-1:0][63:0] result_ftoi;
wire [NUM_LANES-1:0][63:0] result_ftou;
wire [NUM_LANES-1:0][63:0] result_f2f;
fflags_t [NUM_LANES-1:0] fflags_fcvt;
fflags_t [NUM_LANES-1:0] fflags_itof;
fflags_t [NUM_LANES-1:0] fflags_utof;
fflags_t [NUM_LANES-1:0] fflags_ftoi;
fflags_t [NUM_LANES-1:0] fflags_ftou;
wire fcvt_valid = (valid_in && core_select == FPU_CVT);
wire fcvt_ready = per_core_ready_out[FPU_CVT] || ~per_core_valid_out[FPU_CVT];
wire fcvt_fire = fcvt_valid && fcvt_ready;
always @(*) begin
for (integer i = 0; i < NUM_LANES; ++i) begin
dpi_itof (fcvt_fire, int'(dst_fmt), int'(int_fmt), operands[0][i], frm, result_itof[i], fflags_itof[i]);
dpi_utof (fcvt_fire, int'(dst_fmt), int'(int_fmt), operands[0][i], frm, result_utof[i], fflags_utof[i]);
dpi_ftoi (fcvt_fire, int'(int_fmt), int'(dst_fmt), operands[0][i], frm, result_ftoi[i], fflags_ftoi[i]);
dpi_ftou (fcvt_fire, int'(int_fmt), int'(dst_fmt), operands[0][i], frm, result_ftou[i], fflags_ftou[i]);
dpi_f2f (fcvt_fire, int'(dst_fmt), operands[0][i], result_f2f[i]);
result_fcvt[i] = is_itof ? result_itof[i][`XLEN-1:0] :
is_utof ? result_utof[i][`XLEN-1:0] :
is_ftoi ? result_ftoi[i][`XLEN-1:0] :
is_ftou ? result_ftou[i][`XLEN-1:0] :
is_f2f ? result_f2f[i][`XLEN-1:0] :
'0;
fflags_fcvt[i] = is_itof ? fflags_itof[i] :
is_utof ? fflags_utof[i] :
is_ftoi ? fflags_ftoi[i] :
is_ftou ? fflags_ftou[i] :
'0;
end
end
fflags_t fflags_merged;
`FPU_MERGE_FFLAGS(fflags_merged, fflags_fcvt, mask_in, NUM_LANES);
VX_shift_register #(
.DATAW (1 + TAG_WIDTH + NUM_LANES * `XLEN + $bits(fflags_t)),
.DEPTH (`LATENCY_FCVT),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (fcvt_ready),
.data_in ({fcvt_valid, tag_in, result_fcvt, fflags_merged}),
.data_out ({per_core_valid_out[FPU_CVT], per_core_tag_out[FPU_CVT], per_core_result[FPU_CVT], per_core_fflags[FPU_CVT]})
);
assign per_core_has_fflags[FPU_CVT] = 1;
assign per_core_ready_in[FPU_CVT] = fcvt_ready;
end
endgenerate
generate
begin : fncp
reg [NUM_LANES-1:0][`XLEN-1:0] result_fncp;
wire [NUM_LANES-1:0][63:0] result_fclss;
wire [NUM_LANES-1:0][63:0] result_flt;
wire [NUM_LANES-1:0][63:0] result_fle;
wire [NUM_LANES-1:0][63:0] result_feq;
wire [NUM_LANES-1:0][63:0] result_fmin;
wire [NUM_LANES-1:0][63:0] result_fmax;
wire [NUM_LANES-1:0][63:0] result_fsgnj;
wire [NUM_LANES-1:0][63:0] result_fsgnjn;
wire [NUM_LANES-1:0][63:0] result_fsgnjx;
reg [NUM_LANES-1:0][63:0] result_fmvx;
reg [NUM_LANES-1:0][63:0] result_fmvf;
fflags_t [NUM_LANES-1:0] fflags_fncp;
fflags_t [NUM_LANES-1:0] fflags_flt;
fflags_t [NUM_LANES-1:0] fflags_fle;
fflags_t [NUM_LANES-1:0] fflags_feq;
fflags_t [NUM_LANES-1:0] fflags_fmin;
fflags_t [NUM_LANES-1:0] fflags_fmax;
wire fncp_valid = (valid_in && core_select == FPU_NCP);
wire fncp_ready = per_core_ready_out[FPU_NCP] || ~per_core_valid_out[FPU_NCP];
wire fncp_fire = fncp_valid && fncp_ready;
always @(*) begin
for (integer i = 0; i < NUM_LANES; ++i) begin
dpi_fclss (fncp_fire, int'(dst_fmt), operands[0][i], result_fclss[i]);
dpi_fle (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fle[i], fflags_fle[i]);
dpi_flt (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_flt[i], fflags_flt[i]);
dpi_feq (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_feq[i], fflags_feq[i]);
dpi_fmin (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fmin[i], fflags_fmin[i]);
dpi_fmax (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fmax[i], fflags_fmax[i]);
dpi_fsgnj (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnj[i]);
dpi_fsgnjn (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnjn[i]);
dpi_fsgnjx (fncp_fire, int'(dst_fmt), operands[0][i], operands[1][i], result_fsgnjx[i]);
result_fmvx[i] = dst_fmt ? operands[0][i] : 64'($signed(operands[0][i][31:0])); // sign-extension
result_fmvf[i] = dst_fmt ? operands[0][i] : (operands[0][i] | 64'hffffffff00000000); // nan-boxing
end
end
always @(*) begin
result_fncp = 'x;
fflags_fncp = 'x;
for (integer i = 0; i < NUM_LANES; ++i) begin
case (frm)
0: begin result_fncp[i] = is_fcmp ? result_fle[i][`XLEN-1:0] : result_fsgnj[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fle[i]; end
1: begin result_fncp[i] = is_fcmp ? result_flt[i][`XLEN-1:0] : result_fsgnjn[i][`XLEN-1:0]; fflags_fncp[i] = fflags_flt[i]; end
2: begin result_fncp[i] = is_fcmp ? result_feq[i][`XLEN-1:0] : result_fsgnjx[i][`XLEN-1:0]; fflags_fncp[i] = fflags_feq[i]; end
3: begin result_fncp[i] = result_fclss[i][`XLEN-1:0]; end
4: begin result_fncp[i] = result_fmvx[i][`XLEN-1:0]; end
5: begin result_fncp[i] = result_fmvf[i][`XLEN-1:0]; end
6: begin result_fncp[i] = result_fmin[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmin[i]; end
7: begin result_fncp[i] = result_fmax[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmax[i]; end
endcase
end
end
fflags_t fflags_merged;
`FPU_MERGE_FFLAGS(fflags_merged, fflags_fncp, mask_in, NUM_LANES);
wire has_fflags_fncp = (frm >= 6) || is_fcmp;
VX_shift_register #(
.DATAW (1 + TAG_WIDTH + 1 + NUM_LANES * `XLEN + $bits(fflags_t)),
.DEPTH (`LATENCY_FNCP),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (fncp_ready),
.data_in ({fncp_valid, tag_in, has_fflags_fncp, result_fncp, fflags_merged}),
.data_out ({per_core_valid_out[FPU_NCP], per_core_tag_out[FPU_NCP], per_core_has_fflags[FPU_NCP], per_core_result[FPU_NCP], per_core_fflags[FPU_NCP]})
);
assign per_core_ready_in[FPU_NCP] = fncp_ready;
end
endgenerate
///////////////////////////////////////////////////////////////////////////
assign per_core_ready_in[FPU_DIVSQRT] = is_div ? div_ready_in : sqrt_ready_in;
VX_stream_arb #(
.NUM_INPUTS (2),
.DATAW (RSP_DATAW),
.ARBITER ("R"),
.OUT_BUF (0)
) div_sqrt_arb (
.clk (clk),
.reset (reset),
.valid_in ({sqrt_valid_out, div_valid_out}),
.ready_in ({sqrt_ready_out, div_ready_out}),
.data_in ({{sqrt_result, sqrt_has_fflags, sqrt_fflags, sqrt_tag_out},
{div_result, div_has_fflags, div_fflags, div_tag_out}}),
.data_out ({per_core_result[FPU_DIVSQRT], per_core_has_fflags[FPU_DIVSQRT], per_core_fflags[FPU_DIVSQRT], per_core_tag_out[FPU_DIVSQRT]}),
.valid_out (per_core_valid_out[FPU_DIVSQRT]),
.ready_out (per_core_ready_out[FPU_DIVSQRT]),
`UNUSED_PIN (sel_out)
);
///////////////////////////////////////////////////////////////////////////
wire [NUM_FPC-1:0][RSP_DATAW-1:0] per_core_data_out;
for (genvar i = 0; i < NUM_FPC; ++i) begin
assign per_core_data_out[i] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]};
end
VX_stream_arb #(
.NUM_INPUTS (NUM_FPC),
.DATAW (RSP_DATAW),
.ARBITER ("F"),
.OUT_BUF (OUT_BUF)
) rsp_arb (
.clk (clk),
.reset (reset),
.valid_in (per_core_valid_out),
.ready_in (per_core_ready_out),
.data_in (per_core_data_out),
.data_out ({result, has_fflags, fflags, tag_out}),
.valid_out (valid_out),
.ready_out (ready_out),
`UNUSED_PIN (sel_out)
);
assign ready_in = per_core_ready_in[core_select];
endmodule |
module VX_elastic_adapter (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
input wire ready_out,
output wire valid_out,
input wire busy,
output wire strobe
);
wire push = valid_in && ready_in;
wire pop = valid_out && ready_out;
reg loaded;
always @(posedge clk) begin
if (reset) begin
loaded <= 0;
end else begin
if (push) begin
loaded <= 1;
end
if (pop) begin
loaded <= 0;
end
end
end
assign ready_in = ~loaded;
assign valid_out = loaded && ~busy;
assign strobe = push;
endmodule |
module VX_priority_arbiter #(
parameter NUM_REQS = 1,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
);
if (NUM_REQS == 1) begin
assign grant_index = '0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
VX_priority_encoder #(
.N (NUM_REQS)
) priority_encoder (
.data_in (requests),
.index (grant_index),
.onehot (grant_onehot),
.valid_out (grant_valid)
);
end
endmodule |
module VX_sp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter ADDR_MIN = 0,
parameter WRENW = 1,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter LUTRAM = 0,
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire read,
input wire write,
input wire [WRENW-1:0] wren,
input wire [ADDRW-1:0] addr,
input wire [DATAW-1:0] wdata,
output wire [DATAW-1:0] rdata
);
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.ADDR_MIN (ADDR_MIN),
.WRENW (WRENW),
.OUT_REG (OUT_REG),
.NO_RWCHECK (NO_RWCHECK),
.LUTRAM (LUTRAM),
.INIT_ENABLE (INIT_ENABLE),
.INIT_FILE (INIT_FILE),
.INIT_VALUE (INIT_VALUE),
.ADDRW (ADDRW)
) dp_ram (
.clk (clk),
.read (read),
.write (write),
.wren (wren),
.waddr (addr),
.wdata (wdata),
.raddr (addr),
.rdata (rdata)
);
endmodule |
module VX_om_compare #(
parameter DATAW = 24
) (
// Inputs
input wire [`VX_OM_DEPTH_FUNC_BITS-1:0] func,
input wire [DATAW-1:0] a,
input wire [DATAW-1:0] b,
// Outputs
output wire result
);
wire [DATAW:0] sub = (a - b);
wire equal = (0 == sub);
wire less = sub[DATAW];
reg result_r;
always @(*) begin
case (func)
`VX_OM_DEPTH_FUNC_NEVER : result_r = 0;
`VX_OM_DEPTH_FUNC_LESS : result_r = less;
`VX_OM_DEPTH_FUNC_EQUAL : result_r = equal;
`VX_OM_DEPTH_FUNC_LEQUAL : result_r = less || equal;
`VX_OM_DEPTH_FUNC_GREATER : result_r = ~(less || equal);
`VX_OM_DEPTH_FUNC_NOTEQUAL : result_r = ~equal;
`VX_OM_DEPTH_FUNC_GEQUAL : result_r = ~less;
`VX_OM_DEPTH_FUNC_ALWAYS : result_r = 1;
default : result_r = 'x;
endcase
end
assign result = result_r;
endmodule |
module ccip_std_afu #(
parameter NUM_LOCAL_MEM_BANKS = 2
) (
// CCI-P Clocks and Resets
input logic pClk, // Primary CCI-P interface clock.
input logic pClkDiv2, // Aligned, pClk divided by 2.
input logic pClkDiv4, // Aligned, pClk divided by 4.
input logic uClk_usr, // User clock domain. Refer to clock programming guide.
input logic uClk_usrDiv2, // Aligned, user clock divided by 2.
input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset
input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State
input logic pck_cp2af_error, // CCI-P Protocol Error Detected
// CCI-P structures
input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port
output t_if_ccip_Tx pck_af2cp_sTx, // CCI-P Tx Port
// Local memory interface
avalon_mem_if.to_fiu local_mem[NUM_LOCAL_MEM_BANKS]
);
// ====================================================================
// Pick the proper clk and reset, as chosen by the AFU's JSON file
// ====================================================================
// The platform may transform the CCI-P clock from pClk to a clock
// chosen in the AFU's JSON file.
logic clk;
assign clk = `PLATFORM_PARAM_CCI_P_CLOCK;
logic reset;
assign reset = `PLATFORM_PARAM_CCI_P_RESET;
// ====================================================================
// Register signals at interface before consuming them
// ====================================================================
(* noprune *) logic [1:0] cp2af_pwrState_T1;
(* noprune *) logic cp2af_error_T1;
logic reset_T1;
t_if_ccip_Rx cp2af_sRx_T1;
t_if_ccip_Tx af2cp_sTx_T0;
ccip_interface_reg inst_green_ccip_interface_reg
(
.pClk (clk),
.pck_cp2af_softReset_T0 (reset),
.pck_cp2af_pwrState_T0 (pck_cp2af_pwrState),
.pck_cp2af_error_T0 (pck_cp2af_error),
.pck_cp2af_sRx_T0 (pck_cp2af_sRx),
.pck_af2cp_sTx_T0 (af2cp_sTx_T0),
.pck_cp2af_softReset_T1 (reset_T1),
.pck_cp2af_pwrState_T1 (cp2af_pwrState_T1),
.pck_cp2af_error_T1 (cp2af_error_T1),
.pck_cp2af_sRx_T1 (cp2af_sRx_T1),
.pck_af2cp_sTx_T1 (pck_af2cp_sTx)
);
// ====================================================================
// User AFU goes here
// ====================================================================
t_local_mem_byte_mask avs_byteenable [NUM_LOCAL_MEM_BANKS];
logic avs_waitrequest [NUM_LOCAL_MEM_BANKS];
t_local_mem_data avs_readdata [NUM_LOCAL_MEM_BANKS];
logic avs_readdatavalid [NUM_LOCAL_MEM_BANKS];
t_local_mem_burst_cnt avs_burstcount [NUM_LOCAL_MEM_BANKS];
t_local_mem_data avs_writedata [NUM_LOCAL_MEM_BANKS];
t_local_mem_addr avs_address [NUM_LOCAL_MEM_BANKS];
logic avs_write [NUM_LOCAL_MEM_BANKS];
logic avs_read [NUM_LOCAL_MEM_BANKS];
for (genvar b = 0; b < NUM_LOCAL_MEM_BANKS; b++) begin
assign local_mem[b].burstcount = avs_burstcount[b];
assign local_mem[b].writedata = avs_writedata[b];
assign local_mem[b].address = avs_address[b];
assign local_mem[b].byteenable = avs_byteenable[b];
assign local_mem[b].write = avs_write[b];
assign local_mem[b].read = avs_read[b];
assign avs_waitrequest[b] = local_mem[b].waitrequest;
assign avs_readdata[b] = local_mem[b].readdata;
assign avs_readdatavalid[b] = local_mem[b].readdatavalid;
end
vortex_afu #(
.NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS)
) afu (
.clk (clk),
.reset (reset_T1),
.cp2af_sRxPort (cp2af_sRx_T1),
.af2cp_sTxPort (af2cp_sTx_T0),
.avs_writedata (avs_writedata),
.avs_readdata (avs_readdata),
.avs_address (avs_address),
.avs_waitrequest (avs_waitrequest),
.avs_write (avs_write),
.avs_read (avs_read),
.avs_byteenable (avs_byteenable),
.avs_burstcount (avs_burstcount),
.avs_readdatavalid (avs_readdatavalid)
);
endmodule |
module cd_sys(
input nRESET,
//input CLK_68KCLK,
input CLK_68KCLK_EN,
input [23:1] M68K_ADDR,
inout [15:0] M68K_DATA,
input A22Z, A23Z,
input nLDS, nUDS,
input M68K_RW, nAS, nDTACK,
input SYSTEM_CDx,
input [1:0] CD_REGION,
input [1:0] CD_SPEED,
output reg CD_VIDEO_EN,
output reg CD_FIX_EN,
output reg CD_SPR_EN,
output reg CD_nRESET_Z80,
output CD_TR_WR_SPR,
output CD_TR_WR_PCM,
output CD_TR_WR_Z80,
output CD_TR_WR_FIX,
output CD_TR_RD_FIX,
output CD_TR_RD_SPR,
output CD_TR_RD_Z80,
output CD_TR_RD_PCM,
output reg CD_USE_FIX,
output reg CD_USE_SPR,
output reg CD_USE_Z80,
output reg CD_USE_PCM,
output reg [2:0] CD_TR_AREA,
output reg [1:0] CD_BANK_SPR,
output reg CD_BANK_PCM,
output reg [15:0] CD_TR_WR_DATA,
output reg [19:1] CD_TR_WR_ADDR,
output reg CD_UPLOAD_EN, // The bios writes to Z80 RAM without CD_UPLOAD_EN enabled. Maybe this is only watchdog disable?
output CD_VBLANK_IRQ_EN,
output CD_TIMER_IRQ_EN,
input IACK,
output reg CD_IRQ,
input clk_sys,
input [39:0] CDD_STATUS_IN,
input CDD_STATUS_LATCH,
output [39:0] CDD_COMMAND_DATA,
output CDD_COMMAND_SEND,
input CD_DATA_DOWNLOAD,
input CD_DATA_WR,
input [15:0] CD_DATA_DIN,
input [11:1] CD_DATA_ADDR, // word address
output CD_DATA_WR_READY, // Ready to receive sector
input CDDA_RD,
input CDDA_WR,
output [15:0] CD_AUDIO_L,
output [15:0] CD_AUDIO_R,
output CDDA_WR_READY,
input CD_LID, // DEBUG
// For DMA
output reg nBR,
input nBG,
output reg nBGACK,
output reg DMA_RUNNING,
output reg [15:0] DMA_DATA_OUT,
input [15:0] DMA_DATA_IN,
output reg DMA_WR_OUT,
output reg DMA_RD_OUT,
output reg [23:0] DMA_ADDR_IN, // Used for reading
output reg [23:0] DMA_ADDR_OUT, // Used for writing
input DMA_SDRAM_BUSY
);
parameter MCLK = 96671316;
reg CD_nRESET_DRIVE;
reg [15:0] REG_FF0002;
reg [11:0] REG_FF0004;
reg [2:0] CD_IRQ_FLAGS;
reg [23:0] DMA_ADDR_A;
reg [23:0] DMA_ADDR_B;
reg [31:0] DMA_VALUE;
reg [31:0] DMA_COUNT; // TODO: This can probably be 23:0
reg [15:0] DMA_MICROCODE [9];
reg CDD_nIRQ_PREV, CDC_nIRQ_PREV;
reg nLDS_PREV, nUDS_PREV;
reg [3:0] CDD_DIN;
wire [3:0] CDD_DOUT;
reg HOCK;
wire CDCK, CDD_nIRQ;
cd_drive DRIVE(
.clk_sys(clk_sys),
.nRESET(nRESET & CD_nRESET_DRIVE),
.HOCK(HOCK), .CDCK(CDCK),
.CDD_DIN(CDD_DIN), .CDD_DOUT(CDD_DOUT),
.CDD_nIRQ(CDD_nIRQ),
.STATUS_IN(CDD_STATUS_IN),
.STATUS_LATCH(CDD_STATUS_LATCH),
.COMMAND_DATA(CDD_COMMAND_DATA),
.COMMAND_SEND(CDD_COMMAND_SEND)
);
wire [7:0] LC8951_DOUT;
wire CDC_nIRQ;
wire [31:0] HEADER_DIN;
lc8951 LC8951(
.nRESET(nRESET),
.clk_sys(clk_sys),
//.CLK_12M(CLK_68KCLK),
.CLK_68KCLK_EN(CLK_68KCLK_EN),
.nWR(~LC8951_WR), .nRD(~LC8951_RD),
.RS(M68K_ADDR[1]),
.DIN(M68K_DATA[7:0]),
.DOUT(LC8951_DOUT),
.HEADER_DIN(HEADER_DIN),
.SECTOR_READY(SECTOR_READY),
.DMA_RUNNING(DMA_RUNNING),
.CDC_nIRQ(CDC_nIRQ)
);
cdda CDDA(
.CLK(clk_sys),
.nRESET(nRESET),
.READ(CDDA_RD),
.WRITE(CDDA_WR),
.DIN(CD_DATA_DIN),
.AUDIO_L(CD_AUDIO_L),
.AUDIO_R(CD_AUDIO_R),
.WRITE_READY(CDDA_WR_READY)
);
localparam SECTOR_TIME_1X = MCLK / 75;
localparam SECTOR_TIME_2X = MCLK / 150;
localparam SECTOR_TIME_3X = MCLK / 225;
localparam SECTOR_TIME_4X = MCLK / 300;
reg [20:0] SECTOR_TIME;
wire [20:0] SECTOR_TIME_SEL = (CD_SPEED == 2'd0) ? SECTOR_TIME_1X[20:0] :
(CD_SPEED == 2'd1) ? SECTOR_TIME_2X[20:0] :
(CD_SPEED == 2'd2) ? SECTOR_TIME_3X[20:0] :
SECTOR_TIME_4X[20:0];
reg SECTOR_READY; // For decoder interrupt
reg SECTOR_FILLED[2];
reg [23:0] SECTOR_TIME_CNT;
reg FORCE_WR;
reg [2:0] LOADING_STATE;
reg [10:0] CACHE_RD_ADDR, CACHE_WR_ADDR; // 0~2047
reg CACHE_RD_BANK, CACHE_WR_BANK;
reg CACHE_WR_EN;
assign CD_DATA_WR_READY = ~SECTOR_FILLED[~CACHE_RD_BANK];
reg [7:0] HEAD_0[2];
reg [7:0] HEAD_1[2];
reg [7:0] HEAD_2[2];
reg [7:0] HEAD_3[2];
assign HEADER_DIN = { HEAD_3[CACHE_RD_BANK], HEAD_2[CACHE_RD_BANK], HEAD_1[CACHE_RD_BANK], HEAD_0[CACHE_RD_BANK] };
wire [7:0] CACHE_DIN = CACHE_WR_ADDR[0] ? CD_DATA_DIN[15:8] : CD_DATA_DIN[7:0];
wire CACHE_WR = CACHE_WR_EN & (CD_DATA_WR_START | FORCE_WR);
wire [7:0] CACHE_DOUT;
dpram #(12,8) CACHE(
.clock_a(clk_sys),
.address_a( {CACHE_WR_BANK, CACHE_WR_ADDR} ),
.data_a(CACHE_DIN),
.wren_a(CACHE_WR),
.clock_b(clk_sys),
.address_b( {CACHE_RD_BANK, CACHE_RD_ADDR} ),
.wren_b(0),
.q_b(CACHE_DOUT)
);
localparam DMA_STATE_IDLE = 4'd0, DMA_STATE_BR = 4'd1, DMA_STATE_WAIT_BG = 4'd2,
DMA_STATE_WAIT_AS = 4'd3, DMA_STATE_START = 4'd4,
DMA_STATE_CACHE_RD = 4'd5, DMA_STATE_CACHE_RD_L = 4'd6,
DMA_STATE_INIT_RD = 4'd7, DMA_STATE_RD = 4'd8, DMA_STATE_RD_DONE = 4'd9,
DMA_STATE_INIT_WR = 4'd10, DMA_STATE_WR = 4'd11, DMA_STATE_WR_DONE = 4'd12,
DMA_STATE_DONE = 4'd13;
localparam DMA_COPY_CD_WORD = 3'd0, DMA_COPY_CD_BYTE = 3'd1, DMA_COPY_WORD = 3'd2,
DMA_COPY_BYTE = 3'd3, DMA_FILL_VALUE = 3'd4;
reg DMA_START_PREV, DMA_START;
reg [2:0] DMA_MODE;
reg [3:0] DMA_STATE;
reg [3:0] DMA_IO_CNT;
reg [7:0] DMA_TIMER;
reg [15:0] DMA_RD_DATA;
reg [31:0] DMA_COUNT_RUN;
localparam DMA_RW_CYCLES = MCLK / 4800000; // TODO: Tune this
reg CD_DATA_WR_PREV;
wire CD_DATA_WR_START = CD_DATA_WR & ~CD_DATA_WR_PREV;
wire CD_DATA_WR_END = ~CD_DATA_WR & CD_DATA_WR_PREV;
always @(posedge clk_sys)
begin
if (!nRESET)
begin
FORCE_WR <= 0;
SECTOR_READY <= 0;
SECTOR_FILLED[0] <= 0;
SECTOR_FILLED[1] <= 0;
SECTOR_TIME_CNT <= 0;
SECTOR_TIME <= SECTOR_TIME_1X[20:0];
LOADING_STATE <= 3'd0; // Idle, waiting for request
DMA_STATE <= 4'd0;
nBR <= 1;
nBGACK <= 1;
DMA_RUNNING <= 0;
DMA_TIMER <= 8'd0;
CACHE_WR_EN <= 0;
CACHE_RD_BANK <= 0;
CACHE_WR_BANK <= 0;
CD_DATA_WR_PREV <= 0;
end
else
begin
if (SECTOR_TIME_CNT == {1'b0, SECTOR_TIME[20:1]}) begin
SECTOR_READY <= 0;
end
if (SECTOR_TIME_CNT < SECTOR_TIME) begin
SECTOR_TIME_CNT <= SECTOR_TIME_CNT + 1'b1;
end else begin
if (SECTOR_FILLED[~CACHE_RD_BANK]) begin
SECTOR_FILLED[CACHE_RD_BANK] <= 0;
SECTOR_READY <= 1;
CACHE_RD_BANK <= ~CACHE_RD_BANK;
SECTOR_TIME_CNT <= 0;
SECTOR_TIME <= SECTOR_TIME_SEL;
end
end
CD_DATA_WR_PREV <= CD_DATA_WR;
if (LOADING_STATE == 3'd0) begin
if (CD_DATA_WR_READY) begin
if (CD_DATA_DOWNLOAD & CD_DATA_WR_END & (CD_DATA_ADDR == 11'd6)) begin
// Bytes 12-13 (Header 0-1)
CACHE_WR_BANK <= ~CACHE_RD_BANK;
HEAD_0[~CACHE_RD_BANK] <= CD_DATA_DIN[7:0];
HEAD_1[~CACHE_RD_BANK] <= CD_DATA_DIN[15:8];
LOADING_STATE <= 3'd1;
end
end
end
if (LOADING_STATE == 3'd1) begin
if (CD_DATA_DOWNLOAD & CD_DATA_WR_END & (CD_DATA_ADDR == 11'd7)) begin
// Bytes 14-15 (Header 2-3)
HEAD_2[CACHE_WR_BANK] <= CD_DATA_DIN[7:0];
HEAD_3[CACHE_WR_BANK] <= CD_DATA_DIN[15:8];
CACHE_WR_ADDR <= 11'h000;
CACHE_WR_EN <= 1;
LOADING_STATE <= 3'd2;
end
end
if (LOADING_STATE == 3'd2) begin
if (CD_DATA_WR_START) begin
// First byte of pair was written by CD_DATA_WR
CACHE_WR_ADDR <= CACHE_WR_ADDR + 1'b1;
LOADING_STATE <= 3'd3;
FORCE_WR <= 1;
end
if (~CD_DATA_DOWNLOAD) begin // Incomplete data, should not happen.
LOADING_STATE <= 3'd4;
end
end
if (LOADING_STATE == 3'd3) begin
// Second byte of pair was written by FORCE_WR
FORCE_WR <= 0;
CACHE_WR_ADDR <= CACHE_WR_ADDR + 1'b1;
if (CACHE_WR_ADDR == 11'd2047) begin
LOADING_STATE <= 3'd4;
end else begin
LOADING_STATE <= 3'd2;
end
end
if (LOADING_STATE == 3'd4) begin
// Sector load done
CACHE_WR_EN <= 0;
SECTOR_FILLED[CACHE_WR_BANK] <= 1;
LOADING_STATE <= 3'd0;
end
DMA_START_PREV <= DMA_START;
// Rising edge of DMA_START
if (~DMA_START_PREV & DMA_START)
begin
DMA_STATE <= 4'd1;
DMA_IO_CNT <= 4'd0;
DMA_COUNT_RUN <= DMA_COUNT;
case (DMA_MODE)
DMA_COPY_CD_WORD, DMA_COPY_CD_BYTE:
begin
// Init byte copy LC8951 cache -> DMA_ADDR_A
DMA_ADDR_OUT <= DMA_ADDR_A;
CACHE_RD_ADDR <= 11'h000;
end
DMA_COPY_WORD, DMA_COPY_BYTE:
begin
// Init copy DMA_ADDR_A -> DMA_ADDR_B
DMA_ADDR_IN <= DMA_ADDR_A;
DMA_ADDR_OUT <= DMA_ADDR_B;
end
DMA_FILL_VALUE:
begin
// Init word fill from DMA_ADDR_A
DMA_ADDR_OUT <= DMA_ADDR_A;
DMA_DATA_OUT <= DMA_VALUE[31:16]; // Is [15:0] ever used ?
end
default: ;
endcase
end
// DMA logic
// DMA_TIMER is a minimum wait, so tick it even when DMA_SDRAM_BUSY
if (DMA_TIMER)
DMA_TIMER <= DMA_TIMER - 1'b1;
if (!DMA_SDRAM_BUSY)
begin
if (!DMA_TIMER)
begin
if (DMA_STATE == DMA_STATE_BR)
begin
// Init: Do 68k bus request
nBR <= 0;
DMA_STATE <= DMA_STATE_WAIT_BG;
end
if (DMA_STATE == DMA_STATE_WAIT_BG)
begin
// Init: Wait for nBG low
if (~nBG)
DMA_STATE <= DMA_STATE_WAIT_AS;
end
if (DMA_STATE == DMA_STATE_WAIT_AS)
begin
// Init: Wait for nAS and nDTACK high
if (nAS & nDTACK)
begin
nBR <= 1;
nBGACK <= 0;
DMA_RUNNING <= 1;
DMA_STATE <= DMA_STATE_START;
end
end
if (DMA_STATE == DMA_STATE_START)
begin
// Base state for DMA loop
// FX68K doesn't tri-state its outputs when it releases the bus (good !)
// So use separate busses and signals when doing DMA and switch them according to DMA_RUNNING
if (!DMA_COUNT_RUN)
begin
// DMA done !
DMA_STATE <= DMA_STATE_IDLE; // Go back to idle
nBGACK <= 1; // Release bus
DMA_RUNNING <= 0; // Inform CDC that the transfer is finished
end
else
begin
// Working...
case (DMA_MODE)
DMA_COPY_CD_WORD:
begin
// Word copy LC8951 cache -> DMA_ADDR_A
case(DMA_IO_CNT)
4'd0: DMA_STATE <= DMA_STATE_CACHE_RD; // Read word from Cache
4'd1: begin
DMA_DATA_OUT <= DMA_RD_DATA;
DMA_STATE <= DMA_STATE_WR; // Write word
end
default: DMA_STATE <= DMA_STATE_DONE;
endcase
end
DMA_COPY_CD_BYTE:
begin
// Copy LC8951 cache -> DMA_ADDR_A odd bytes
case(DMA_IO_CNT)
4'd0: DMA_STATE <= DMA_STATE_CACHE_RD; // Read word from Cache
4'd1: begin
DMA_DATA_OUT <= {DMA_RD_DATA[7:0], DMA_RD_DATA[15:8]};
DMA_STATE <= DMA_STATE_WR; // Write low byte
end
4'd2: begin
DMA_DATA_OUT <= DMA_RD_DATA;
DMA_STATE <= DMA_STATE_WR; // Write high byte
end
default: DMA_STATE <= DMA_STATE_DONE;
endcase
end
DMA_COPY_WORD:
begin
// Word copy DMA_ADDR_A -> DMA_ADDR_B
case(DMA_IO_CNT)
4'd0: DMA_STATE <= DMA_STATE_RD; // Read word
4'd1: begin
DMA_DATA_OUT <= DMA_RD_DATA;
DMA_STATE <= DMA_STATE_WR; // Write word
end
default: DMA_STATE <= DMA_STATE_DONE;
endcase
end
DMA_COPY_BYTE:
begin
// Byte copy DMA_ADDR_A -> DMA_ADDR_B odd bytes
case(DMA_IO_CNT)
4'd0: DMA_STATE <= DMA_STATE_RD; // Read word
4'd1: begin
DMA_DATA_OUT <= {DMA_RD_DATA[7:0], DMA_RD_DATA[15:8]};
DMA_STATE <= DMA_STATE_WR; // Write low byte
end
4'd2: begin
DMA_DATA_OUT <= DMA_RD_DATA;
DMA_STATE <= DMA_STATE_WR; // Write high byte
end
default: DMA_STATE <= DMA_STATE_DONE;
endcase
end
DMA_FILL_VALUE:
begin
// Word fill from DMA_ADDR_A
case(DMA_IO_CNT)
4'd0: DMA_STATE <= DMA_STATE_WR;
default: DMA_STATE <= DMA_STATE_DONE;
endcase
end
default: ;
endcase
end
end
if (DMA_STATE == DMA_STATE_CACHE_RD)
begin
DMA_RD_DATA[15:8] <= CACHE_DOUT; // Got upper byte
CACHE_RD_ADDR <= CACHE_RD_ADDR + 1'b1;
DMA_TIMER <= DMA_RW_CYCLES[7:0] >> 1; // TODO: Tune this
DMA_STATE <= DMA_STATE_CACHE_RD_L;
end
if (DMA_STATE == DMA_STATE_CACHE_RD_L)
begin
DMA_RD_DATA[7:0] <= CACHE_DOUT; // Got lower byte
CACHE_RD_ADDR <= CACHE_RD_ADDR + 1'b1;
DMA_IO_CNT <= DMA_IO_CNT + 1'b1;
DMA_STATE <= DMA_STATE_START;
end
if (DMA_STATE == DMA_STATE_WR)
begin
DMA_WR_OUT <= 1;
DMA_TIMER <= DMA_RW_CYCLES[7:0]; // TODO: Tune this
DMA_STATE <= DMA_STATE_WR_DONE;
end
if (DMA_STATE == DMA_STATE_WR_DONE)
begin
// Write done
DMA_WR_OUT <= 0;
DMA_ADDR_OUT <= DMA_ADDR_OUT + 2'd2;
DMA_IO_CNT <= DMA_IO_CNT + 1'b1;
DMA_STATE <= DMA_STATE_START;
end
if (DMA_STATE == DMA_STATE_RD)
begin
DMA_RD_OUT <= 1;
DMA_TIMER <= DMA_RW_CYCLES[7:0]; // TODO: Tune this
DMA_STATE <= DMA_STATE_RD_DONE;
end
if (DMA_STATE == DMA_STATE_RD_DONE)
begin
DMA_RD_OUT <= 0;
DMA_RD_DATA <= DMA_DATA_IN;
DMA_ADDR_IN <= DMA_ADDR_IN + 2'd2;
DMA_IO_CNT <= DMA_IO_CNT + 1'b1;
DMA_STATE <= DMA_STATE_START;
end
if (DMA_STATE == DMA_STATE_DONE)
begin
DMA_COUNT_RUN <= DMA_COUNT_RUN - 1'b1;
DMA_STATE <= DMA_STATE_START;
DMA_IO_CNT <= 4'd0;
end
end
end
end
end
wire READING = ~nAS & M68K_RW & (M68K_ADDR[23:12] == 12'hFF0) & SYSTEM_CDx;
wire WRITING = ~nAS & ~M68K_RW & (M68K_ADDR[23:12] == 12'hFF0) & SYSTEM_CDx;
wire LC8951_RD = (READING & (M68K_ADDR[11:2] == 10'b0001_000000)); // FF0101, FF0103
wire LC8951_WR = (WRITING & (M68K_ADDR[11:2] == 10'b0001_000000)); // FF0101, FF0103
// nAS used ?
wire TR_ZONE = (DMA_RUNNING ? (DMA_ADDR_OUT[23:20] == 4'hE) : (M68K_ADDR[23:20] == 4'hE)) & SYSTEM_CDx;
wire TR_ZONE_RD = TR_ZONE & (DMA_RUNNING ? DMA_RD_OUT : M68K_RW & ~(nLDS & nUDS));
wire TR_ZONE_WR = TR_ZONE & (DMA_RUNNING ? DMA_WR_OUT : ~M68K_RW & ~(nLDS & nUDS));
wire CD_TR_SPR = (CD_TR_AREA == 3'd0) & CD_USE_SPR;
wire CD_TR_PCM = (CD_TR_AREA == 3'd1) & CD_USE_PCM;
wire CD_TR_Z80 = (CD_TR_AREA == 3'd4) & CD_USE_Z80;
wire CD_TR_FIX = (CD_TR_AREA == 3'd5) & CD_USE_FIX;
// Allow writes only if the "allow write" flag of the corresponding region is set
assign CD_TR_WR_SPR = TR_ZONE_WR & CD_TR_SPR;
assign CD_TR_WR_PCM = TR_ZONE_WR & CD_TR_PCM;
assign CD_TR_WR_Z80 = TR_ZONE_WR & CD_TR_Z80;
assign CD_TR_WR_FIX = TR_ZONE_WR & CD_TR_FIX;
assign CD_TR_RD_FIX = TR_ZONE_RD & CD_TR_FIX;
assign CD_TR_RD_SPR = TR_ZONE_RD & CD_TR_SPR;
assign CD_TR_RD_Z80 = TR_ZONE_RD & CD_TR_Z80;
assign CD_TR_RD_PCM = TR_ZONE_RD & CD_TR_PCM;
reg [1:0] CDD_nIRQ_SR;
always @(posedge clk_sys)
begin
if (!nRESET)
begin
CD_USE_SPR <= 0;
CD_USE_PCM <= 0;
CD_USE_Z80 <= 0;
CD_USE_FIX <= 0;
CD_SPR_EN <= 1; // ?
CD_FIX_EN <= 1; // ?
CD_VIDEO_EN <= 1; // ?
CD_UPLOAD_EN <= 0;
CD_nRESET_Z80 <= 0; // ?
CD_nRESET_DRIVE <= 0; // ?
HOCK <= 1;
REG_FF0002 <= 16'h0; // ?
REG_FF0004 <= 0; // ?
nLDS_PREV <= 1;
nUDS_PREV <= 1;
CD_IRQ <= 1;
CD_IRQ_FLAGS <= 3'b111;
DMA_START <= 0;
CDD_nIRQ_SR <= 2'b11;
end
else if (CLK_68KCLK_EN) begin
nLDS_PREV <= nLDS;
nUDS_PREV <= nUDS;
CDD_nIRQ_SR <= {CDD_nIRQ_SR[0], CDD_nIRQ};
CDC_nIRQ_PREV <= CDC_nIRQ;
// Falling edge of CDD_nIRQ
//if (CDD_nIRQ_PREV & ~CDD_nIRQ)
if (CDD_nIRQ_SR == 2'b10)
begin
// Trigger CD comm. interrupt
if (REG_FF0002[6] & REG_FF0002[4])
CD_IRQ_FLAGS[1] <= 0;
// REG_FF0002:
// C = CD comm. interrupt
// S = Sector ready interrupt ?
// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
// S S C C
end
// Falling edge of CDC_nIRQ
if (CDC_nIRQ_PREV & ~CDC_nIRQ)
begin
// Trigger CDC interrupt (decoder or transfer end)
if (REG_FF0002[10] & REG_FF0002[8])
CD_IRQ_FLAGS[2] <= 0;
end
CD_IRQ <= ~&{CD_IRQ_FLAGS};
// Trigger
if (DMA_START)
DMA_START <= 0;
if (SYSTEM_CDx & ((nLDS_PREV & ~nLDS) | (nUDS_PREV & ~nUDS))) // & PREV_nAS & ~nAS
begin
// Writes
if ((M68K_ADDR[23:9] == 15'b11111111_0000000) & ~M68K_RW)
begin
casez ({M68K_ADDR[8:1], nUDS, nLDS})
// FF00xx
10'b0_0000001_00: REG_FF0002 <= M68K_DATA; // FF0002
10'b0_0000010_00: REG_FF0004 <= M68K_DATA[11:0]; // FF0004
10'b0_0000111_?0: CD_IRQ_FLAGS <= CD_IRQ_FLAGS | M68K_DATA[5:3]; // FF000E
10'b0_0110000_10: // FF0061
begin
if (M68K_DATA[6])
begin
// DMA start
DMA_START <= 1;
case (DMA_MICROCODE[0])
16'hFF89, 16'hFFC5:
begin
// Copy LC8951 cache -> DMA_ADDR_A
// Count in words even it's really a byte copy
// TOP-SP1 @ C119F4
// $FF89 $FCF5 $D8A6 $F627 $03FD $FFFF
DMA_MODE <= DMA_COPY_CD_WORD;
end
16'hFC2D:
begin
// Copy LC8951 cache -> DMA_ADDR_A odd bytes
// FC2D
DMA_MODE <= DMA_COPY_CD_BYTE;
end
16'hFE6D, 16'hFE3D:
begin
// Word copy DMA_ADDR_A -> DMA_ADDR_B
// Count in words
// TOP-SP1 @ C119D4
// $FE6D $FCF5 $82BF $F693 $BF29 $02FD $FFFF $C515 $FCF5
// Word copy DMA_ADDR_A -> DMA_ADDR_B
// Different microcode, same operation ?
// Used by UploadPRGDMAWords, UploadPalDMAWords
// TOP-SP1 @ C0C07C
// $FE6D $FCF5 $82BF $F693 $BF29 $02FD $FFFF $F97D $FCF5
DMA_MODE <= DMA_COPY_WORD;
end
16'hF2DD, 16'hE2DD:
begin
// Byte copy DMA_ADDR_A -> odd bytes DMA_ADDR_B ?
// Used by UploadFIXDMABytes, UploadPCMDMABytes, UploadZ80DMABytes
// Count in words
// TOP-SP1 @ C0C09A
// $F2DD $82F6 $93DA $BE93 $DABE $2C02 $FDFF
DMA_MODE <= DMA_COPY_BYTE;
end
16'hFFCD, 16'hFFDD:
begin
// Word fill starting at DMA_ADDR_A
// Used by DMAClearPalettes, DMAClearPCMDRAM?
// Count in words
// TOP-SP1 @ C0C09A
// $FFCD $FCF5 $92F6 $2602 $FDFF
DMA_MODE <= DMA_FILL_VALUE;
end
default: ;
endcase
// Other microcodes are used but only for the test mode, those can wait
// See TOP-SP1 @ C0AB26, TOP-SP1 @ C0AB3E, TOP-SP1 @ C0AB5A
end
end
10'b0_0110010_00: DMA_ADDR_A[23:16] <= M68K_DATA[7:0]; // FF0064~FF0065
10'b0_0110011_00: DMA_ADDR_A[15:0] <= M68K_DATA; // FF0066~FF0067
10'b0_0110100_00: DMA_ADDR_B[23:16] <= M68K_DATA[7:0]; // FF0068~FF0069
10'b0_0110101_00: DMA_ADDR_B[15:0] <= M68K_DATA; // FF006A~FF006B
10'b0_0110110_00: DMA_VALUE[31:16] <= M68K_DATA; // FF006C~FF006D
10'b0_0110111_00: DMA_VALUE[15:0] <= M68K_DATA; // FF006E~FF006F
10'b0_0111000_00: DMA_COUNT[31:16] <= M68K_DATA; // FF0070~FF0071
10'b0_0111001_00: DMA_COUNT[15:0] <= M68K_DATA; // FF0072~FF0073
10'b0_0111111_00: DMA_MICROCODE[0] <= M68K_DATA; // FF007E M68K_ADDR[4:1]
10'b0_1000000_00: DMA_MICROCODE[1] <= M68K_DATA; // FF0080 M68K_ADDR[4:1]
10'b0_1000001_00: DMA_MICROCODE[2] <= M68K_DATA; // FF0082 M68K_ADDR[4:1]
10'b0_1000010_00: DMA_MICROCODE[3] <= M68K_DATA; // FF0084 M68K_ADDR[4:1]
10'b0_1000011_00: DMA_MICROCODE[4] <= M68K_DATA; // FF0086 M68K_ADDR[4:1]
10'b0_1000100_00: DMA_MICROCODE[5] <= M68K_DATA; // FF0088 M68K_ADDR[4:1]
10'b0_1000101_00: DMA_MICROCODE[6] <= M68K_DATA; // FF008A M68K_ADDR[4:1]
10'b0_1000110_00: DMA_MICROCODE[7] <= M68K_DATA; // FF008C M68K_ADDR[4:1]
10'b0_1000111_00: DMA_MICROCODE[8] <= M68K_DATA; // FF008E M68K_ADDR[4:1]
// FF01xx
10'b1_0000010_?0: CD_TR_AREA <= M68K_DATA[2:0]; // FF0105 Upload area select
10'b1_0001000_?0: CD_SPR_EN <= ~M68K_DATA[0]; // FF0111 REG_DISBLSPR
10'b1_0001010_?0: CD_FIX_EN <= ~M68K_DATA[0]; // FF0115 REG_DISBLFIX
10'b1_0001100_?0: CD_VIDEO_EN <= M68K_DATA[0]; // FF0119 REG_ENVIDEO
10'b1_0010000_?0: CD_USE_SPR <= 1; // FF0121 REG_UPMAPSPR
10'b1_0010001_?0: CD_USE_PCM <= 1; // FF0123 REG_UPMAPPCM
10'b1_0010011_?0: CD_USE_Z80 <= 1; // FF0127 REG_UPMAPZ80
10'b1_0010100_?0: CD_USE_FIX <= 1; // FF0129 REG_UPMAPFIX
10'b1_0100000_?0: CD_USE_SPR <= 0; // FF0141 REG_UPUNMAPSPR
10'b1_0100001_?0: CD_USE_PCM <= 0; // FF0143 REG_UPUNMAPSPR
10'b1_0100011_?0: CD_USE_Z80 <= 0; // FF0147 REG_UPUNMAPSPR
10'b1_0100100_?0: CD_USE_FIX <= 0; // FF0149 REG_UPUNMAPSPR
10'b1_0110001_10: CDD_DIN <= M68K_DATA[3:0]; // FF0163 REG_CDDOUTPUT
10'b1_0110010_10: HOCK <= M68K_DATA[0]; // FF0165 REG_CDDCTRL
10'b1_0110111_?0: CD_UPLOAD_EN <= M68K_DATA[0]; // FF016F
10'b1_1000000_?0: CD_nRESET_DRIVE <= M68K_DATA[0]; // FF0181
10'b1_1000001_?0: CD_nRESET_Z80 <= M68K_DATA[0]; // FF0183
10'b1_1010000_?0: CD_BANK_SPR <= M68K_DATA[1:0]; // FF01A1 REG_SPRBANK
10'b1_1010001_?0: CD_BANK_PCM <= M68K_DATA[0]; // FF01A3 REG_PCMBANK
default:;
endcase
end
else if ((M68K_ADDR[23:20] == 4'hE) & ~M68K_RW)
begin
// Upload zone
// Is this buffered or is the write directy forwarded to memory ?
CD_TR_WR_DATA <= M68K_DATA;
CD_TR_WR_ADDR <= M68K_ADDR[19:1];
end
end
end
end
// 1111:JP, 1110:US, 1101: EU
wire [3:0] CD_JUMPERS = {2'b11, CD_REGION};
wire [7:0] CD_IRQ_VECTOR = (M68K_ADDR[2:1] == 2'd3) ? 8'd25 : // Timer $64
(M68K_ADDR[2:1] == 2'd2) & ~CD_IRQ_FLAGS[0] ? 8'd23 :
(M68K_ADDR[2:1] == 2'd2) & ~CD_IRQ_FLAGS[1] ? 8'd22 : // CD comm. $58
(M68K_ADDR[2:1] == 2'd2) & ~CD_IRQ_FLAGS[2] ? 8'd21 : // CD decoder $54
(M68K_ADDR[2:1] == 2'd1) ? 8'd26 : // VBlank $68
8'd24; // Spurious interrupt, should not happen
function [15:0] bit_reverse;
input [15:0] a;
begin
bit_reverse = { a[0],a[1],a[2],a[3],a[4],a[5],a[6],a[7],a[8],a[9],a[10],a[11],a[12],a[13],a[14],a[15] };
end
endfunction
assign CD_VBLANK_IRQ_EN = &{REG_FF0004[5:4]};
assign CD_TIMER_IRQ_EN = &{REG_FF0004[9:8]};
assign M68K_DATA = (SYSTEM_CDx & ~nAS & M68K_RW & IACK) ? {8'h00, CD_IRQ_VECTOR} : // Vectored interrupt handler
(READING & {M68K_ADDR[11:1], 1'b0} == 12'h004) ? {4'h0, REG_FF0004} :
(READING & {M68K_ADDR[11:1], 1'b0} == 12'h11C) ? {3'b110, CD_LID, CD_JUMPERS, 8'h00} : // Top mech
(READING & {M68K_ADDR[11:1], 1'b0} == 12'h160) ? {11'b00000000_000, CDCK, CDD_DOUT} : // REG_CDDINPUT
(READING & {M68K_ADDR[11:1], 1'b0} == 12'h166) ? {16'd0} : // Bit 5 needs to be clear for VU meters in CD player to work
(READING & {M68K_ADDR[11:1], 1'b0} == 12'h188) ? bit_reverse(CD_AUDIO_L) : // CDDA L
(READING & {M68K_ADDR[11:1], 1'b0} == 12'h18A) ? bit_reverse(CD_AUDIO_R) : // CDDA R
(LC8951_RD) ? {8'h00, LC8951_DOUT} :
16'bzzzzzzzz_zzzzzzzz;
endmodule |
module MSU
(
input CLK,
input RST_N,
input ENABLE,
input RD_N,
input WR_N,
input SYSCLKF_CE,
input [23:0] ADDR,
input [7:0] DIN,
output reg [7:0] DOUT,
output MSU_SEL,
output reg [15:0] track_num,
output reg track_request,
input track_mounting,
// Audio player control
output reg [7:0] volume,
input status_track_missing,
output reg status_audio_repeat,
output reg status_audio_playing,
input audio_stop,
// Data track read
output reg [31:0] data_addr,
input [7:0] data,
input data_ack,
output reg data_seek,
output reg data_req
);
// Read 'registers'
// MSU_STATUS - $2000
// Status bits
localparam [2:0] status_revision = 3'b001;
wire [7:0] MSU_STATUS = {
status_data_busy,
status_audio_busy,
status_audio_repeat,
status_audio_playing,
status_track_missing,
status_revision
};
// Write registers
reg [31:0] MSU_SEEK; // $2000 - $2003
reg [15:0] MSU_TRACK; // $2004 - $2005
// banks 00-3F and 80-BF, address 2000-2007
assign MSU_SEL = ENABLE && !ADDR[22] && (ADDR[15:4] == 'h200) && !ADDR[3];
wire status_audio_busy = track_request;
reg data_ack_1 = 1'b0;
reg status_data_busy = 1'b0;
reg track_mounting_old = 0;
reg data_rd_old;
wire data_rd = MSU_SEL && !RD_N && ADDR[2:0] == 1 && !status_data_busy;
always @(posedge CLK) begin
if (~RST_N) begin
MSU_SEEK <= 0;
data_addr <= 0;
MSU_TRACK <= 0;
track_num <= 0;
track_request <= 0;
volume <= 0;
status_audio_playing <= 0;
status_audio_repeat <= 0;
status_data_busy <= 0;
track_mounting_old <= 0;
data_req <= 0;
data_seek <= 0;
end
else begin
// Reset our request trigger for pulsing
data_req <= 0;
// Falling edge of data busy
data_ack_1 <= data_ack;
if (!data_ack_1 && data_ack) begin
status_data_busy <= 0;
data_seek <= 0;
end
// Falling edge of track mounting
track_mounting_old <= track_mounting;
if (track_mounting_old && !track_mounting) track_request <= 0;
if (audio_stop) status_audio_playing <= 0;
// Register writes
if (MSU_SEL & SYSCLKF_CE & ~WR_N) begin
case (ADDR[2:0])
0: MSU_SEEK[7:0] <= DIN; // Data seek address. MSU_SEEK, LSB byte
1: MSU_SEEK[15:8] <= DIN; // Data seek address. MSU_SEEK.
2: MSU_SEEK[23:16] <= DIN; // Data seek address. MSU_SEEK.
3: begin
MSU_SEEK[31:24] <= DIN; // Data seek address. MSU_SEEK, MSB byte
data_addr <= {DIN, MSU_SEEK[23:0]};
data_seek <= 1;
status_data_busy <= 1;
end
4: MSU_TRACK[7:0] <= DIN; // MSU_Track LSB
5: begin
MSU_TRACK[15:8] <= DIN; // MSU_Track MSB
track_num <= {DIN, MSU_TRACK[7:0]};
track_request <= 1;
end
6: volume <= DIN; // MSU Audio Volume
// MSU Audio state control
7: begin
status_audio_repeat <= DIN[1];
status_audio_playing <= DIN[0];
end
endcase
end
// Advance data pointer after read
data_rd_old <= data_rd;
if (data_rd_old & ~data_rd) begin
data_addr <= data_addr + 1;
data_req <= 1'b1;
end
case (ADDR[2:0])
0: DOUT <= MSU_STATUS;
1: DOUT <= data;
2: DOUT <= "S";
3: DOUT <= "-";
4: DOUT <= "M";
5: DOUT <= "S";
6: DOUT <= "U";
7: DOUT <= "1";
endcase
end
end
endmodule |
module Sachen8259(
input clk, // System clock
input ce, // M2 ~cpu_clk
input enable, // Mapper enabled
input [31:0] flags, // Cart flags
input [15:0] prg_ain, // prg address
inout [21:0] prg_aout_b, // prg address out
input prg_read, // prg read
input prg_write, // prg write
input [7:0] prg_din, // prg data in
inout [7:0] prg_dout_b, // prg data out
inout prg_allow_b, // Enable access to memory for the specified operation.
input [13:0] chr_ain, // chr address in
inout [21:0] chr_aout_b, // chr address out
input chr_read, // chr ram read
inout chr_allow_b, // chr allow write
inout vram_a10_b, // Value for A10 address line
inout vram_ce_b, // True if the address should be routed to the internal 2kB VRAM.
inout irq_b, // IRQ
input [15:0] audio_in, // Inverted audio from APU
inout [15:0] audio_b, // Mixed audio output
inout [15:0] flags_out_b, // flags {0, 0, 0, 0, has_savestate, prg_conflict, prg_bus_write, has_chr_dout}
// savestates
input [63:0] SaveStateBus_Din,
input [ 9:0] SaveStateBus_Adr,
input SaveStateBus_wren,
input SaveStateBus_rst,
input SaveStateBus_load,
output [63:0] SaveStateBus_Dout
);
assign prg_aout_b = enable ? prg_aout : 22'hZ;
assign prg_dout_b = enable ? prg_dout : 8'hZ;
assign prg_allow_b = enable ? prg_allow : 1'hZ;
assign chr_aout_b = enable ? chr_aout : 22'hZ;
assign chr_allow_b = enable ? chr_allow : 1'hZ;
assign vram_a10_b = enable ? vram_a10 : 1'hZ;
assign vram_ce_b = enable ? vram_ce : 1'hZ;
assign irq_b = enable ? 1'b0 : 1'hZ;
assign flags_out_b = enable ? flags_out : 16'hZ;
assign audio_b = enable ? {1'b0, audio_in[15:1]} : 16'hZ;
wire [21:0] prg_aout, chr_aout;
wire prg_allow;
wire chr_allow;
reg vram_a10;
wire vram_ce;
wire [15:0] flags_out = {12'd0, 1'b1, 1'b0, prg_bus_write, 1'b0};
// 0x4100
wire [7:0] prg_dout = {5'b00111, (~register)}; // ^ (counter & 0x1)
wire prg_bus_write = ({prg_ain[15:14], prg_ain[8], prg_ain[0]} == 4'b0110);
wire mapper137 = (flags[7:0] == 137);
wire mapper138 = (flags[7:0] == 138);
wire mapper139 = (flags[7:0] == 139);
wire mapper141 = (flags[7:0] == 141);
wire mapper150 = (flags[7:0] == 150);
wire mapper243 = (flags[7:0] == 243);
reg [2:0] register;
reg [2:0] prg_bank;
reg [2:0] chr_bank_0, chr_bank_1, chr_bank_2, chr_bank_3, chr_bank_o, chr_bank_p;
reg [2:0] mirroring;
always @(posedge clk)
if (~enable) begin
//any resets?
end else if (SaveStateBus_load) begin
register <= SS_MAP1[ 2: 0];
prg_bank <= SS_MAP1[ 5: 3];
chr_bank_0 <= SS_MAP1[ 8: 6];
chr_bank_1 <= SS_MAP1[11: 9];
chr_bank_2 <= SS_MAP1[14:12];
chr_bank_3 <= SS_MAP1[17:15];
chr_bank_o <= SS_MAP1[20:18];
chr_bank_p <= SS_MAP1[23:21];
mirroring <= SS_MAP1[26:24];
end else if (ce && prg_write) begin
if ({prg_ain[15:14], prg_ain[8], prg_ain[0]} == 4'b0110) begin
register <= prg_din[2:0];
end else if ({prg_ain[15:14], prg_ain[8], prg_ain[0]} == 4'b0111) begin
case (register)
0: begin
chr_bank_0 <= prg_din[2:0]; // Select 2 KB CHR bank at PPU $0000-$07FF;
if (mapper243) {prg_bank, chr_bank_2[0], chr_bank_p[1:0], chr_bank_o[0]} = 7'b000_0011;
end
1: chr_bank_1 <= prg_din[2:0]; // Select 2 KB CHR bank at PPU $0800-$0FFF;
2: begin
chr_bank_2 <= prg_din[2:0]; // Select 2 KB CHR bank at PPU $1000-$17FF;
if (mapper150) prg_bank = {2'b00, prg_din[0]};
end
3: chr_bank_3 <= prg_din[2:0]; // Select 2 KB CHR bank at PPU $1800-$1FFF;
4: chr_bank_o <= prg_din[2:0]; // Outer CHR bank
5: prg_bank <= prg_din[2:0]; // Select 32 KB PRG ROM bank at $8000-$FFFF;
6: chr_bank_p <= prg_din[2:0]; // Outer CHR bank
7: mirroring <= prg_din[2:0]; // Select Mirroring
endcase
end
end
assign SS_MAP1_BACK[ 2: 0] = register;
assign SS_MAP1_BACK[ 5: 3] = prg_bank;
assign SS_MAP1_BACK[ 8: 6] = chr_bank_0;
assign SS_MAP1_BACK[11: 9] = chr_bank_1;
assign SS_MAP1_BACK[14:12] = chr_bank_2;
assign SS_MAP1_BACK[17:15] = chr_bank_3;
assign SS_MAP1_BACK[20:18] = chr_bank_o;
assign SS_MAP1_BACK[23:21] = chr_bank_p;
assign SS_MAP1_BACK[26:24] = mirroring;
assign SS_MAP1_BACK[63:27] = 37'b0; // free to be used
// The CHR bank to load. Each increment here is 1kb. So valid values are 0..255.
reg [2:0] chr_bank;
reg [2:0] chr_banko;
reg [8:0] chrsel;
always @* begin
casez({mirroring[0], mapper137 ? chr_ain[11:10] : chr_ain[12:11]})
3'b000: chr_bank = chr_bank_0;
3'b001: chr_bank = chr_bank_1;
3'b010: chr_bank = chr_bank_2;
3'b011: chr_bank = chr_bank_3;
3'b1??: chr_bank = chr_bank_0;
endcase
casez({mapper137, chr_ain[11:10]})
3'b0??: chr_banko = chr_bank_o;
3'b100: chr_banko = 3'b000;
3'b101: chr_banko = {1'b0, chr_bank_o[0], 1'b0};
3'b110: chr_banko = {1'b0, chr_bank_o[1], 1'b0};
3'b111: chr_banko = {1'b0, chr_bank_o[2], chr_bank_p[0]};
endcase
if (mapper137)
chrsel = chr_ain[12] ? {7'h7F, chr_ain[11:10]} : {3'b111, chr_banko, chr_bank};
else if (mapper138)
chrsel = {2'b11, chr_banko, chr_bank, chr_ain[10]};
else if (mapper141)
chrsel = {1'b1, chr_banko, chr_bank, chr_ain[11:10]};
else if (mapper139)
chrsel = {chr_banko, chr_bank, chr_ain[12:10]};
else if (mapper150)
chrsel = {2'b00, chr_bank_2[0], chr_bank_o[0], chr_bank_p[1:0], chr_ain[12:10]};
else if (mapper243)
chrsel = {2'b00, chr_bank_2[0], chr_bank_p[1:0], chr_bank_o[0], chr_ain[12:10]};
else
chrsel = 9'h000;
end
always @* begin
casez(mapper150 ? {mirroring[2:1], 1'b0} : mapper243 ? {1'b0, mirroring[0], 1'b0} : mirroring)
3'b??1: vram_a10 = chr_ain[10];
3'b000: vram_a10 = chr_ain[10];
3'b010: vram_a10 = chr_ain[11];
3'b100: vram_a10 = chr_ain[10] | chr_ain[11];
3'b110: vram_a10 = 1'b0;
endcase
end
assign prg_aout = {4'b00_00, prg_bank, prg_ain[14:0]};
assign chr_allow = flags[15];
assign chr_aout = {3'b10_0, chrsel, chr_ain[9:0]};
assign vram_ce = chr_ain[13];
//assign vram_a10 = ; //done above
assign prg_allow = prg_ain[15] && !prg_write;
// savestate
wire [63:0] SS_MAP1;
wire [63:0] SS_MAP1_BACK;
wire [63:0] SaveStateBus_Dout_active;
eReg_SavestateV #(SSREG_INDEX_MAP1, 64'h0000000000000000) iREG_SAVESTATE_MAP1 (clk, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_Dout_active, SS_MAP1_BACK, SS_MAP1);
assign SaveStateBus_Dout = enable ? SaveStateBus_Dout_active : 64'h0000000000000000;
endmodule |
module SachenJV001(
input clk, // System clock
input ce, // M2 ~cpu_clk
input enable, // Mapper enabled
input [31:0] flags, // Cart flags
input [15:0] prg_ain, // prg address
inout [21:0] prg_aout_b, // prg address out
input prg_read, // prg read
input prg_write, // prg write
input [7:0] prg_din, // prg data in
inout [7:0] prg_dout_b, // prg data out
inout prg_allow_b, // Enable access to memory for the specified operation.
input [13:0] chr_ain, // chr address in
inout [21:0] chr_aout_b, // chr address out
input chr_read, // chr ram read
inout chr_allow_b, // chr allow write
inout vram_a10_b, // Value for A10 address line
inout vram_ce_b, // True if the address should be routed to the internal 2kB VRAM.
inout irq_b, // IRQ
input [15:0] audio_in, // Inverted audio from APU
inout [15:0] audio_b, // Mixed audio output
inout [15:0] flags_out_b, // flags {0, 0, 0, 0, has_savestate, prg_conflict, prg_bus_write, has_chr_dout}
// savestates
input [63:0] SaveStateBus_Din,
input [ 9:0] SaveStateBus_Adr,
input SaveStateBus_wren,
input SaveStateBus_rst,
input SaveStateBus_load,
output [63:0] SaveStateBus_Dout
);
assign prg_aout_b = enable ? prg_aout : 22'hZ;
assign prg_dout_b = enable ? prg_dout : 8'hZ;
assign prg_allow_b = enable ? prg_allow : 1'hZ;
assign chr_aout_b = enable ? chr_aout : 22'hZ;
assign chr_allow_b = enable ? chr_allow : 1'hZ;
assign vram_a10_b = enable ? vram_a10 : 1'hZ;
assign vram_ce_b = enable ? vram_ce : 1'hZ;
assign irq_b = enable ? 1'b0 : 1'hZ;
assign flags_out_b = enable ? flags_out : 16'hZ;
assign audio_b = enable ? {1'b0, audio_in[15:1]} : 16'hZ;
wire [21:0] prg_aout, chr_aout;
wire prg_allow;
wire chr_allow;
wire vram_a10;
wire vram_ce;
wire [15:0] flags_out = {12'd0, 1'b1, 1'b0, prg_bus_write, 1'b0};
reg [5:0] input_reg; //s_reg = input_reg[3]
reg [5:0] output_reg;
reg [5:0] register_reg;
reg inc_reg;
reg invert_reg;
reg [3:0] alt_chr;
reg mirroring;
//wire mapper136 = (flags[7:0] == 136); //default
wire mapper132 = (flags[7:0] == 132);
wire mapper147 = (flags[7:0] == 147);
wire mapper173 = (flags[7:0] == 173);
wire mapper172 = (flags[7:0] == 172);
wire mapper36 = (flags[7:0] == 36);
wire [7:0] prg_din_adj = mapper147 ? {2'b00, prg_din[7:2]} :
mapper36 ? {4'b0000, prg_din[7:4]} :
mapper172 ? {2'b00, prg_din[0], prg_din[1], prg_din[2], prg_din[3], prg_din[4], prg_din[5]} :
prg_din;
wire prg_bus_write = (prg_ain[15:13] == 3'b010 && prg_ain[8]); //0x4100-3
always @(posedge clk)
if (~enable) begin
//
end else if (SaveStateBus_load) begin
input_reg <= SS_MAP1[ 5: 0];
output_reg <= SS_MAP1[11: 6];
register_reg<= SS_MAP1[17:12];
inc_reg <= SS_MAP1[ 18];
invert_reg <= SS_MAP1[ 19];
alt_chr <= SS_MAP1[23:20];
mirroring <= SS_MAP1[ 24];
end else if (ce) begin
if (prg_ain[15:13] == 3'b010 && prg_ain[8] && prg_write) //0x4100-3
case (prg_ain[1:0])
0: begin
if (inc_reg)
register_reg[3:0] <= register_reg[3:0] + 4'b1;
else
register_reg <= invert_reg ? {input_reg[5:4], ~input_reg[3:0]} : input_reg;
end
1: invert_reg <= prg_din_adj[0];
2: input_reg <= prg_din_adj[5:0];
3: inc_reg <= prg_din_adj[0];
endcase
if (prg_ain[15:13] == 3'b010 && prg_ain[9] && prg_write) //0x4200
alt_chr <= prg_din[3:0];
if (prg_ain[15] == 1'b1 && prg_write) begin
output_reg <= register_reg;
mirroring <= invert_reg;
end
end
assign SS_MAP1_BACK[ 5: 0] = input_reg;
assign SS_MAP1_BACK[11: 6] = output_reg;
assign SS_MAP1_BACK[17:12] = register_reg;
assign SS_MAP1_BACK[ 18] = inc_reg;
assign SS_MAP1_BACK[ 19] = invert_reg;
assign SS_MAP1_BACK[23:20] = alt_chr;
assign SS_MAP1_BACK[ 24] = mirroring;
assign SS_MAP1_BACK[63:25] = 39'b0; // free to be used
// 0x4100-3
wire use_s = mapper132 | mapper173;
wire [5:0] V001_val = (use_s ? {2'b00, input_reg[3], register_reg[2:0]} : register_reg) ^ (invert_reg ? (use_s ? 6'h08 : 6'h30) : 6'h00);
wire [7:0] prg_dout = mapper172 ? {chr_ain[7:6], V001_val[0], V001_val[1], V001_val[2], V001_val[3], V001_val[4], V001_val[5]} :
mapper147 ? {V001_val, chr_ain[1:0]} :
{chr_ain[7:6], V001_val}; // two bits are open bus
wire [3:0] chr_sel = mapper36 ? alt_chr :
mapper173 ? {2'b00, ~invert_reg, output_reg[0]} :
mapper147 ? {output_reg[4:1]} :
mapper172 ? {2'b00, output_reg[1:0]} :
{2'b00, output_reg[1:0]};
wire [1:0] prg_sel = mapper147 ? {output_reg[5], output_reg[0]} :
mapper132 ? {1'b0, output_reg[2]} :
mapper36 ? {output_reg[1:0]} :
2'b00;
assign prg_aout = {5'b00_000, prg_sel, prg_ain[14:0]};
assign prg_allow = prg_ain[15] && !prg_write;
assign chr_allow = flags[15];
assign chr_aout = {5'b10_000, chr_sel, chr_ain[12:0]};
assign vram_ce = chr_ain[13];
assign vram_a10 = (mapper172 ? mirroring : flags[14]) ? chr_ain[10] : chr_ain[11]; // 0: horiz, 1: vert
// savestate
wire [63:0] SS_MAP1;
wire [63:0] SS_MAP1_BACK;
wire [63:0] SaveStateBus_Dout_active;
eReg_SavestateV #(SSREG_INDEX_MAP1, 64'h0000000000000000) iREG_SAVESTATE_MAP1 (clk, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_Dout_active, SS_MAP1_BACK, SS_MAP1);
assign SaveStateBus_Dout = enable ? SaveStateBus_Dout_active : 64'h0000000000000000;
endmodule |
module SachenNROM(
input clk, // System clock
input ce, // M2 ~cpu_clk
input enable, // Mapper enabled
input [31:0] flags, // Cart flags
input [15:0] prg_ain, // prg address
inout [21:0] prg_aout_b, // prg address out
input prg_read, // prg read
input prg_write, // prg write
input [7:0] prg_din, // prg data in
inout [7:0] prg_dout_b, // prg data out
inout prg_allow_b, // Enable access to memory for the specified operation.
input [13:0] chr_ain, // chr address in
inout [21:0] chr_aout_b, // chr address out
input chr_read, // chr ram read
inout chr_allow_b, // chr allow write
inout vram_a10_b, // Value for A10 address line
inout vram_ce_b, // True if the address should be routed to the internal 2kB VRAM.
inout irq_b, // IRQ
input [15:0] audio_in, // Inverted audio from APU
inout [15:0] audio_b, // Mixed audio output
inout [15:0] flags_out_b // flags {0, 0, 0, 0, has_savestate, prg_conflict, prg_bus_write, has_chr_dout}
// savestates
// savestates support - but no state in mapper needs saving
);
assign prg_aout_b = enable ? prg_aout : 22'hZ;
assign prg_dout_b = enable ? prg_dout : 8'hZ;
assign prg_allow_b = enable ? prg_allow : 1'hZ;
assign chr_aout_b = enable ? chr_aout : 22'hZ;
assign chr_allow_b = enable ? chr_allow : 1'hZ;
assign vram_a10_b = enable ? vram_a10 : 1'hZ;
assign vram_ce_b = enable ? vram_ce : 1'hZ;
assign irq_b = enable ? 1'b0 : 1'hZ;
assign flags_out_b = enable ? flags_out : 16'hZ;
assign audio_b = enable ? {1'b0, audio_in[15:1]} : 16'hZ;
wire [21:0] prg_aout, chr_aout;
wire prg_allow;
wire chr_allow;
wire vram_a10;
wire vram_ce;
wire prg_bus_write;
wire [15:0] flags_out = {12'h0, 1'b1, 1'b0, prg_bus_write, 1'b0};
// 0x4100
wire [7:0] prg_dout = {2'b01, ~prg_ain[5:0]}; // top 2 bits are actually open bus
assign prg_bus_write = ((prg_ain[15:13] == 3'b010) && prg_ain[8]);
assign prg_aout = {7'b00_0000_0, prg_ain[14:0]};
assign prg_allow = prg_ain[15] && !prg_write;
assign chr_allow = flags[15];
assign chr_aout = {9'b10_0000_000, chr_ain[12:0]};
assign vram_ce = chr_ain[13];
assign vram_a10 = flags[14] ? chr_ain[10] : chr_ain[11]; // 0: horiz, 1: vert
endmodule |
module N163(
input clk, // System clock
input ce, // M2 ~cpu_clk
input enable, // Mapper enabled
input [31:0] flags, // Cart flags
input [15:0] prg_ain, // prg address
inout [21:0] prg_aout_b, // prg address out
input prg_read, // prg read
input prg_write, // prg write
input [7:0] prg_din, // prg data in
inout [7:0] prg_dout_b, // prg data out
inout prg_allow_b, // Enable access to memory for the specified operation.
input [13:0] chr_ain, // chr address in
inout [21:0] chr_aout_b, // chr address out
input chr_read, // chr ram read
inout chr_allow_b, // chr allow write
inout vram_a10_b, // Value for A10 address line
inout vram_ce_b, // True if the address should be routed to the internal 2kB VRAM.
inout irq_b, // IRQ
input [15:0] audio_in, // Inverted audio from APU
inout [15:0] audio_b, // Mixed audio output
inout [15:0] flags_out_b, // flags {0, 0, 0, 0, has_savestate, prg_conflict, prg_bus_write, has_chr_dout}
// Special ports
input [7:0] audio_dout,
// savestates
input [63:0] SaveStateBus_Din,
input [ 9:0] SaveStateBus_Adr,
input SaveStateBus_wren,
input SaveStateBus_rst,
input SaveStateBus_load,
output [63:0] SaveStateBus_Dout
);
assign prg_aout_b = enable ? prg_aout : 22'hZ;
assign prg_dout_b = enable ? prg_dout : 8'hZ;
assign prg_allow_b = enable ? prg_allow : 1'hZ;
assign chr_aout_b = enable ? chr_aout : 22'hZ;
assign chr_allow_b = enable ? chr_allow : 1'hZ;
assign vram_a10_b = enable ? vram_a10 : 1'hZ;
assign vram_ce_b = enable ? vram_ce : 1'hZ;
assign irq_b = enable ? irq : 1'hZ;
assign flags_out_b = enable ? flags_out : 16'hZ;
assign audio_b = enable ? audio[15:0] : 16'hZ;
wire [21:0] prg_aout, chr_aout;
wire prg_allow;
wire chr_allow;
wire vram_a10;
wire vram_ce;
wire irq;
wire [15:0] flags_out = {12'h0, 1'b1, 1'b0, prg_bus_write, 1'b0};
wire prg_bus_write = nesprg_oe;
wire [7:0] prg_dout;
wire [15:0] audio = audio_in;
wire nesprg_oe;
wire [7:0] neschrdout;
wire neschr_oe;
wire wram_oe;
wire wram_we;
wire prgram_we;
wire chrram_oe;
wire prgram_oe;
wire [18:13] ramprgaout;
wire exp6;
reg [7:0] m2;
wire m2_n = 1;//~ce; //m2_n not used as clk. Invert m2 (ce).
wire [18:10] chr_aoutm;
always @(posedge clk) begin
if (SaveStateBus_load) begin
m2 <= 8'd0;
end else begin
m2[7:1] <= m2[6:0];
m2[0] <= ce;
end
end
MAPN163 n163
(
m2[7], m2_n, clk, ~enable, prg_write, nesprg_oe, 0,
1, prg_ain, chr_ain, prg_din, 8'b0, prg_dout,
neschrdout, neschr_oe, chr_allow, chrram_oe, wram_oe, wram_we, prgram_we,
prgram_oe, chr_aoutm, ramprgaout, irq, vram_ce, exp6,
0, 7'b1111111, 6'b111111, flags[14], flags[16], flags[15],
ce, (flags[7:0]==210), flags[24:21], audio_dout,
// savestates
SaveStateBus_Din,
SaveStateBus_Adr,
SaveStateBus_wren,
SaveStateBus_rst,
SaveStateBus_load,
SaveStateBus_Dout
);
assign chr_aout[21:18] = {4'b1000};
assign chr_aout[17:10] = chr_aoutm[17:10];
assign chr_aout[9:0] = chr_ain[9:0];
assign vram_a10 = chr_aout[10];
wire [21:13] prg_aout_tmp = {3'b00_0, ramprgaout};
wire [21:13] prg_ram = {9'b11_1100_000};
wire prg_is_ram = prg_ain >= 'h6000 && prg_ain < 'h8000;
assign prg_aout[21:13] = prg_is_ram ? prg_ram : prg_aout_tmp;
assign prg_aout[12:0] = prg_ain[12:0];
assign prg_allow = (prg_ain[15] && !prg_write) || prg_is_ram;
endmodule |
module MAPN163( //signal descriptions in powerpak.v
input m2,
input m2_n,
input clk20,
input reset,
input nesprg_we,
output nesprg_oe,
input neschr_rd,
input neschr_wr,
input [15:0] prgain,
input [13:0] chrain,
input [7:0] nesprgdin,
input [7:0] ramprgdin,
output reg [7:0] nesprgdout,
output [7:0] neschrdout,
output neschr_oe,
output reg chrram_we,
output reg chrram_oe,
output wram_oe,
output wram_we,
output prgram_we,
output prgram_oe,
output reg [18:10] ramchraout,
output [18:13] ramprgaout,
output irq,
output reg ciram_ce,
output exp6,
input cfg_boot,
input [18:12] cfg_chrmask,
input [18:13] cfg_prgmask,
input cfg_vertical,
input cfg_fourscreen,
input cfg_chrram,
input ce,// add
input mapper210,
input [3:0] submapper,
//output [15:0] snd_level,
input [7:0] audio_dout,
// savestates
input [63:0] SaveStateBus_Din,
input [ 9:0] SaveStateBus_Adr,
input SaveStateBus_wren,
input SaveStateBus_rst,
input SaveStateBus_load,
output [63:0] SaveStateBus_Dout
);
assign exp6 = 0;
reg [1:0] chr_en;
reg [5:0] prg89,prgAB,prgCD;
reg [7:0] chr0,chr1,chr2,chr3,chr4,chr5,chr6,chr7,chr10,chr11,chr12,chr13;
reg [1:0] mirror;
wire submapper1 = (submapper == 1);
always@(posedge clk20) begin
if (reset) begin
mirror <= cfg_vertical ? 2'b01 : 2'b10;
end else if (SaveStateBus_load) begin
chr0 <= SS_MAP1[ 7: 0];
chr1 <= SS_MAP1[15: 8];
chr2 <= SS_MAP1[23:16];
chr3 <= SS_MAP1[31:24];
chr4 <= SS_MAP1[39:32];
chr5 <= SS_MAP1[47:40];
chr6 <= SS_MAP1[55:48];
chr7 <= SS_MAP1[63:56];
chr10 <= SS_MAP2[23:16];
chr11 <= SS_MAP2[31:24];
chr12 <= SS_MAP2[39:32];
chr13 <= SS_MAP2[47:40];
chr_en <= SS_MAP2[49:48];
prg89 <= SS_MAP2[55:50];
prgAB <= SS_MAP2[61:56];
prgCD <= SS_MAP3[ 5: 0];
mirror <= SS_MAP3[ 7: 6];
end else if(ce && nesprg_we)
case(prgain[15:11])
5'b10000: chr0<=nesprgdin; //8000
5'b10001: chr1<=nesprgdin;
5'b10010: chr2<=nesprgdin; //9000
5'b10011: chr3<=nesprgdin;
5'b10100: chr4<=nesprgdin; //A000
5'b10101: chr5<=nesprgdin;
5'b10110: chr6<=nesprgdin; //B000
5'b10111: chr7<=nesprgdin;
5'b11000: chr10<=nesprgdin; //C000
5'b11001: chr11<=nesprgdin;
5'b11010: chr12<=nesprgdin; //D000
5'b11011: chr13<=nesprgdin;
5'b11100: {mirror,prg89}<=nesprgdin; //E000
5'b11101: {chr_en,prgAB}<=nesprgdin; //E800
5'b11110: prgCD<=nesprgdin[5:0]; //F000
//5'b11111: //F800 (sound)
endcase
end
//IRQ
reg [15:0] count;
wire [15:0] count_next=count+1'd1;
wire countup=count[15] & ~&count[14:0];
reg timeout;
assign irq=timeout;
always@(posedge clk20) begin
if (SaveStateBus_load) begin
count <= SS_MAP3[23: 8];
timeout <= SS_MAP3[ 24];
end else if (ce) begin
if(prgain[15:12]==4'b0101)
timeout<=0;
else if(count==16'hFFFF)
timeout<=1;
if(nesprg_we & prgain[15:11]==5'b01010)
count[7:0]<=nesprgdin;
else if(countup)
count[7:0]<=count_next[7:0];
if(nesprg_we & prgain[15:11]==5'b01011)
count[15:8]<=nesprgdin;
else if(countup)
count[15:8]<=count_next[15:8];
end
end
assign SS_MAP1_BACK[ 7: 0] = chr0;
assign SS_MAP1_BACK[15: 8] = chr1;
assign SS_MAP1_BACK[23:16] = chr2;
assign SS_MAP1_BACK[31:24] = chr3;
assign SS_MAP1_BACK[39:32] = chr4;
assign SS_MAP1_BACK[47:40] = chr5;
assign SS_MAP1_BACK[55:48] = chr6;
assign SS_MAP1_BACK[63:56] = chr7;
assign SS_MAP2_BACK[15: 0] = 16'b0; // free to be used
assign SS_MAP2_BACK[23:16] = chr10;
assign SS_MAP2_BACK[31:24] = chr11;
assign SS_MAP2_BACK[39:32] = chr12;
assign SS_MAP2_BACK[47:40] = chr13;
assign SS_MAP2_BACK[49:48] = chr_en;
assign SS_MAP2_BACK[55:50] = prg89;
assign SS_MAP2_BACK[61:56] = prgAB;
assign SS_MAP2_BACK[63:62] = 2'b0; // free to be used
assign SS_MAP3_BACK[ 5: 0] = prgCD;
assign SS_MAP3_BACK[ 7: 6] = mirror;
assign SS_MAP3_BACK[23: 8] = count;
assign SS_MAP3_BACK[ 24] = timeout;
assign SS_MAP3_BACK[63:25] = 39'b0; // free to be used
//PRG bank
reg [18:13] prgbankin;
always@* begin
case(prgain[14:13])
0:prgbankin=prg89;
1:prgbankin=prgAB;
2:prgbankin=prgCD;
3:prgbankin=6'b111111;
endcase
end
assign ramprgaout[18:13]=prgbankin[18:13] & cfg_prgmask & {4'b1111,{2{prgain[15]}}};
//CHR control
reg chrram;
reg [17:10] chrbank;
always@* begin
case(chrain[13:10])
0:chrbank=chr0;
1:chrbank=chr1;
2:chrbank=chr2;
3:chrbank=chr3;
4:chrbank=chr4;
5:chrbank=chr5;
6:chrbank=chr6;
7:chrbank=chr7;
8,12:chrbank=chr10;
9,13:chrbank=chr11;
10,14:chrbank=chr12;
11,15:chrbank=chr13;
endcase
chrram=(~(chrain[12]?chr_en[1]:chr_en[0]))&(&chrbank[17:15]); //ram/rom select
if(!chrain[13]) begin
ciram_ce=chrram && ~mapper210;
chrram_oe=neschr_rd;
chrram_we=neschr_wr & chrram;
ramchraout[10]=chrbank[10];
end else begin
ciram_ce=(&chrbank[17:15]) | mapper210;
chrram_oe=~ciram_ce & neschr_rd;
chrram_we=~ciram_ce & neschr_wr & chrram;
casez({mapper210,submapper1,mirror,cfg_vertical})
5'b0?_??_?: ramchraout[10] = chrbank[10];
//5'b0?_?1_?: ramchraout[10] = chrain[10];
5'b10_00_?: ramchraout[10] = 1'b0;
5'b10_01_?: ramchraout[10] = chrain[10];
5'b10_10_?: ramchraout[10] = chrain[11];
5'b10_11_?: ramchraout[10] = 1'b1;
5'b11_??_0: ramchraout[10] = chrain[11];
5'b11_??_1: ramchraout[10] = chrain[10];
endcase
end
ramchraout[11]=chrbank[11];
ramchraout[17:12]=chrbank[17:12] & cfg_chrmask[17:12];
ramchraout[18]=ciram_ce;
end
assign wram_oe=m2_n & ~nesprg_we & prgain[15:13]==3'b011;
assign wram_we=m2_n & nesprg_we & prgain[15:13]==3'b011;
assign prgram_we=0;
assign prgram_oe= ~cfg_boot & m2_n & ~nesprg_we & prgain[15];
wire config_rd = 0;
//wire [7:0] gg_out;
//gamegenie gg(m2, reset, nesprg_we, prgain, nesprgdin, ramprgdin, gg_out, config_rd);
//PRG data out
wire mapper_oe = m2_n & ~nesprg_we & ((prgain[15:12]=='b0101) || (prgain[15:11]=='b01001));
always @* begin
case(prgain[15:11])
5'b01001: nesprgdout=audio_dout;
5'b01010: nesprgdout=count[7:0];
5'b01011: nesprgdout=count[15:8];
default: nesprgdout=nesprgdin;
endcase
end
assign nesprg_oe=wram_oe | prgram_oe | mapper_oe | config_rd;
assign neschr_oe=0;
assign neschrdout=0;
// savestate
localparam SAVESTATE_MODULES = 3;
wire [63:0] SaveStateBus_wired_or[0:SAVESTATE_MODULES-1];
wire [63:0] SS_MAP1, SS_MAP2, SS_MAP3;
wire [63:0] SS_MAP1_BACK, SS_MAP2_BACK, SS_MAP3_BACK;
wire [63:0] SaveStateBus_Dout_active = SaveStateBus_wired_or[0] | SaveStateBus_wired_or[1] | SaveStateBus_wired_or[2];
eReg_SavestateV #(SSREG_INDEX_MAP1, 64'h0000000000000000) iREG_SAVESTATE_MAP1 (clk20, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[0], SS_MAP1_BACK, SS_MAP1);
eReg_SavestateV #(SSREG_INDEX_MAP2, 64'h0000000000000000) iREG_SAVESTATE_MAP2 (clk20, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[1], SS_MAP2_BACK, SS_MAP2);
eReg_SavestateV #(SSREG_INDEX_MAP3, 64'h0000000000000000) iREG_SAVESTATE_MAP3 (clk20, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[2], SS_MAP3_BACK, SS_MAP3);
assign SaveStateBus_Dout = ~reset ? SaveStateBus_Dout_active : 64'h0000000000000000;
endmodule |
module namco163_mixed (
input clk,
input ce,
input [3:0] submapper,
input enable,
input wren,
input [15:0] addr_in,
input [7:0] data_in,
output [7:0] data_out,
input [15:0] audio_in,
output [15:0] audio_out,
// savestates
input [63:0] SaveStateBus_Din,
input [ 9:0] SaveStateBus_Adr,
input SaveStateBus_wren,
input SaveStateBus_rst,
input SaveStateBus_load,
output [63:0] SaveStateBus_Dout,
input Savestate_MAPRAMactive,
input [6:0] Savestate_MAPRAMAddr,
input Savestate_MAPRAMRdEn,
input Savestate_MAPRAMWrEn,
input [7:0] Savestate_MAPRAMWriteData,
output [7:0] Savestate_MAPRAMReadData
);
reg disabled;
always@(posedge clk) begin
if (!enable) begin
disabled <= 1'b0;
end else if (SaveStateBus_load) begin
disabled <= SS_MAP1[0];
end else if (ce) begin
if(wren & addr_in[15:11]==5'b11100) //E000..E7FF
disabled<=data_in[6];
end
end
assign SS_MAP1_BACK[0] = disabled;
assign SS_MAP1_BACK[63:1] = 63'b0; // free to be used
//sound
wire [10:0] n163_out;
namco163_sound n163
(
clk, ce, enable, wren, addr_in, data_in, data_out, n163_out,
// savestates
SaveStateBus_Din,
SaveStateBus_Adr,
SaveStateBus_wren,
SaveStateBus_rst,
SaveStateBus_load,
SaveStateBus_wired_or[1],
Savestate_MAPRAMactive,
Savestate_MAPRAMAddr,
Savestate_MAPRAMRdEn,
Savestate_MAPRAMWrEn,
Savestate_MAPRAMWriteData,
Savestate_MAPRAMReadData
);
//pdm #(10) pdm_mod(clk20, saturated, exp6);
wire [9:0] saturated=n163_out[9:0] | {10{n163_out[10]}}; //this is still too quiet for the suggested 47k resistor, but more clipping will make some games sound bad
wire [15:0] audio = {1'b0, saturated, 5'b0};
wire [16:0] audio_mix = (!enable | disabled) ? {audio_in, 1'b0} : (submapper==5) ? (audio_in>>>2) + audio : (submapper==4) ? (audio_in>>>1) + audio : audio_in + audio;
assign audio_out = audio_mix[16:1];
// savestates
localparam SAVESTATE_MODULES = 2;
wire [63:0] SaveStateBus_wired_or[0:SAVESTATE_MODULES-1];
wire [63:0] SS_MAP1;
wire [63:0] SS_MAP1_BACK;
wire [63:0] SaveStateBus_Dout_active = SaveStateBus_wired_or[0] | SaveStateBus_wired_or[1];
eReg_SavestateV #(SSREG_INDEX_SNDMAP5, 64'h0000000000000000) iREG_SAVESTATE_MAP1 (clk, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[0], SS_MAP1_BACK, SS_MAP1);
assign SaveStateBus_Dout = enable ? SaveStateBus_Dout_active : 64'h0000000000000000;
endmodule |
module namco163_sound(
input clk20,
input m2,
input enable,
input wr,
input [15:0] ain,
input [7:0] din,
output [7:0] dout,
output reg [10:0] out, //range is 0..0x708
// savestates
input [63:0] SaveStateBus_Din,
input [ 9:0] SaveStateBus_Adr,
input SaveStateBus_wren,
input SaveStateBus_rst,
input SaveStateBus_load,
output [63:0] SaveStateBus_Dout,
input Savestate_MAPRAMactive,
input [6:0] Savestate_MAPRAMAddr,
input Savestate_MAPRAMRdEn,
input Savestate_MAPRAMWrEn,
input [7:0] Savestate_MAPRAMWriteData,
output reg [7:0] Savestate_MAPRAMReadData
);
reg carry;
reg autoinc;
reg [6:0] ram_ain;
reg [6:0] ram_aout;
wire [7:0] ram_dout;
reg [2:0] ch;
reg [7:0] cnt_L[7:0];
reg [7:0] cnt_M[7:0];
reg [1:0] cnt_H[7:0];
wire [2:0] sum_H=cnt_H[ch]+ram_dout[1:0]+carry;
reg [4:0] sample_pos[7:0];
reg [2:0] cycle;
reg [3:0] sample;
wire [7:0] chan_out=sample*ram_dout[3:0]; //sample*vol
reg [10:0] out_acc;
wire [10:0] sum=out_acc+chan_out;
reg addr_lsb;
wire [7:0] sample_addr=ram_dout+sample_pos[ch];
reg do_inc;
//ram in
always@(posedge clk20) begin
if (SaveStateBus_load) begin
do_inc <= SS_MAP1[ 0];
ram_ain <= SS_MAP1[ 7: 1];
autoinc <= SS_MAP1[ 8];
end else if (m2) begin
do_inc<= 0;
if (do_inc)
ram_ain<=ram_ain+1'd1;
if(wr & ain[15:11]==5'b11111) //F800..FFFF
{autoinc,ram_ain}<=din;
else if(ain[15:11]==5'b01001 & autoinc) //4800..4FFF
do_inc<=1;
end
end
//mixer FSM
always @* begin
case(cycle)
0: ram_aout={1'b1,ch,3'd0}; //freq[7:0]
1: ram_aout={1'b1,ch,3'd2}; //freq[15:8]
2: ram_aout={1'b1,ch,3'd4}; //length, freq[17:16]
3: ram_aout={1'b1,ch,3'd6}; //address
4: ram_aout=sample_addr[7:1]; //sample address
5: ram_aout={1'b1,ch,3'd7}; //volume
default: ram_aout=7'bXXXXXXX;
endcase
end
reg [3:0] count45,cnt45;
always@(posedge clk20) begin
if (SaveStateBus_load) begin
count45 <= SS_MAP1[12: 9];
end else if (m2) begin
count45<=(count45==14)?4'd0:count45+1'd1;
end
end
always@(posedge clk20) begin
if (SaveStateBus_load) begin
cnt45 <= SS_MAP1[16:13];
cycle <= SS_MAP1[19:17];
carry <= SS_MAP1[ 20];
addr_lsb <= SS_MAP1[ 21];
sample <= SS_MAP1[25:22];
ch <= SS_MAP1[28:26];
out_acc <= SS_MAP1[39:29];
cnt_L[0] <= SS_MAP2[ 7: 0];
cnt_L[1] <= SS_MAP2[15: 8];
cnt_L[2] <= SS_MAP2[23:16];
cnt_L[3] <= SS_MAP2[31:24];
cnt_L[4] <= SS_MAP2[39:32];
cnt_L[5] <= SS_MAP2[47:40];
cnt_L[6] <= SS_MAP2[55:48];
cnt_L[7] <= SS_MAP2[63:56];
cnt_M[0] <= SS_MAP3[ 7: 0];
cnt_M[1] <= SS_MAP3[15: 8];
cnt_M[2] <= SS_MAP3[23:16];
cnt_M[3] <= SS_MAP3[31:24];
cnt_M[4] <= SS_MAP3[39:32];
cnt_M[5] <= SS_MAP3[47:40];
cnt_M[6] <= SS_MAP3[55:48];
cnt_M[7] <= SS_MAP3[63:56];
cnt_H[0] <= SS_MAP4[ 1: 0];
cnt_H[1] <= SS_MAP4[ 3: 2];
cnt_H[2] <= SS_MAP4[ 5: 4];
cnt_H[3] <= SS_MAP4[ 7: 6];
cnt_H[4] <= SS_MAP4[ 9: 8];
cnt_H[5] <= SS_MAP4[11:10];
cnt_H[6] <= SS_MAP4[13:12];
cnt_H[7] <= SS_MAP4[15:14];
sample_pos[0] <= SS_MAP4[20:16];
sample_pos[1] <= SS_MAP4[25:21];
sample_pos[2] <= SS_MAP4[30:26];
sample_pos[3] <= SS_MAP4[35:31];
sample_pos[4] <= SS_MAP4[40:36];
sample_pos[5] <= SS_MAP4[45:41];
sample_pos[6] <= SS_MAP4[50:46];
sample_pos[7] <= SS_MAP4[55:51];
end else begin
cnt45<=count45;
if(cnt45[1:0]==0) cycle<=0; // this gives 45 21.4M clocks per channel
else if(cycle!=7) cycle<=cycle+1'd1;
case(cycle)
1: {carry, cnt_L[ch]}<=cnt_L[ch][7:0]+ram_dout;
2: {carry, cnt_M[ch]}<=cnt_M[ch][7:0]+ram_dout+carry;
3: begin
cnt_H[ch]<=sum_H[1:0];
if(sum_H[2])
sample_pos[ch]<=(sample_pos[ch]=={ram_dout[4:2]^3'b111,2'b11})?5'd0:(sample_pos[ch]+1'd1);
end
4: addr_lsb<=sample_addr[0];
5: sample<=addr_lsb?ram_dout[7:4]:ram_dout[3:0];
6: begin
if(ch==7) begin
ch<=~ram_dout[6:4];
out_acc<=0;
out<=sum;
end else begin
ch<=ch+1'd1;
out_acc<=sum;
end
end
endcase
end
end
wire [6:0] ram_addrB = Savestate_MAPRAMactive ? Savestate_MAPRAMAddr : ram_aout;
wire ram_wrenB = Savestate_MAPRAMactive ? Savestate_MAPRAMWrEn : 1'b0;
wire [7:0] ram_dataB = Savestate_MAPRAMactive ? Savestate_MAPRAMWriteData : 8'b0;
dpram #(.widthad_a(7)) modtable
(
.clock_a (clk20),
.address_a (ram_ain),
.wren_a (wr & ain[15:11]==5'b01001),
.byteena_a (1),
.data_a (din),
.q_a (dout),
.clock_b (clk20),
.address_b (ram_addrB),
.wren_b (ram_wrenB),
.byteena_b (1),
.data_b (ram_dataB),
.q_b (ram_dout)
);
// savestate
always@(posedge clk20) begin
if (enable) begin
if (Savestate_MAPRAMRdEn) begin
Savestate_MAPRAMReadData <= ram_dout;
end
end else begin
Savestate_MAPRAMReadData <= 8'd0;
end
end
assign SS_MAP1_BACK[16:13] = cnt45;
assign SS_MAP1_BACK[19:17] = cycle;
assign SS_MAP1_BACK[ 20] = carry;
assign SS_MAP1_BACK[ 21] = addr_lsb;
assign SS_MAP1_BACK[25:22] = sample;
assign SS_MAP1_BACK[28:26] = ch;
assign SS_MAP1_BACK[39:29] = out_acc;
assign SS_MAP1_BACK[63:40] = 24'b0; // free to be used
assign SS_MAP2_BACK[ 7: 0] = cnt_L[0];
assign SS_MAP2_BACK[15: 8] = cnt_L[1];
assign SS_MAP2_BACK[23:16] = cnt_L[2];
assign SS_MAP2_BACK[31:24] = cnt_L[3];
assign SS_MAP2_BACK[39:32] = cnt_L[4];
assign SS_MAP2_BACK[47:40] = cnt_L[5];
assign SS_MAP2_BACK[55:48] = cnt_L[6];
assign SS_MAP2_BACK[63:56] = cnt_L[7];
assign SS_MAP3_BACK[ 7: 0] = cnt_M[0];
assign SS_MAP3_BACK[15: 8] = cnt_M[1];
assign SS_MAP3_BACK[23:16] = cnt_M[2];
assign SS_MAP3_BACK[31:24] = cnt_M[3];
assign SS_MAP3_BACK[39:32] = cnt_M[4];
assign SS_MAP3_BACK[47:40] = cnt_M[5];
assign SS_MAP3_BACK[55:48] = cnt_M[6];
assign SS_MAP3_BACK[63:56] = cnt_M[7];
assign SS_MAP4_BACK[ 1: 0] = cnt_H[0];
assign SS_MAP4_BACK[ 3: 2] = cnt_H[1];
assign SS_MAP4_BACK[ 5: 4] = cnt_H[2];
assign SS_MAP4_BACK[ 7: 6] = cnt_H[3];
assign SS_MAP4_BACK[ 9: 8] = cnt_H[4];
assign SS_MAP4_BACK[11:10] = cnt_H[5];
assign SS_MAP4_BACK[13:12] = cnt_H[6];
assign SS_MAP4_BACK[15:14] = cnt_H[7];
assign SS_MAP4_BACK[20:16] = sample_pos[0];
assign SS_MAP4_BACK[25:21] = sample_pos[1];
assign SS_MAP4_BACK[30:26] = sample_pos[2];
assign SS_MAP4_BACK[35:31] = sample_pos[3];
assign SS_MAP4_BACK[40:36] = sample_pos[4];
assign SS_MAP4_BACK[45:41] = sample_pos[5];
assign SS_MAP4_BACK[50:46] = sample_pos[6];
assign SS_MAP4_BACK[55:51] = sample_pos[7];
assign SS_MAP4_BACK[63:56] = 8'b0; // free to be used
localparam SAVESTATE_MODULES = 4;
wire [63:0] SaveStateBus_wired_or[0:SAVESTATE_MODULES-1];
wire [63:0] SS_MAP1, SS_MAP2, SS_MAP3, SS_MAP4;
wire [63:0] SS_MAP1_BACK, SS_MAP2_BACK, SS_MAP3_BACK, SS_MAP4_BACK;
wire [63:0] SaveStateBus_Dout_active = SaveStateBus_wired_or[0] | SaveStateBus_wired_or[1] | SaveStateBus_wired_or[2] | SaveStateBus_wired_or[3];
eReg_SavestateV #(SSREG_INDEX_SNDMAP1, 64'h0000000000000000) iREG_SAVESTATE_MAP1 (clk20, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[0], SS_MAP1_BACK, SS_MAP1);
eReg_SavestateV #(SSREG_INDEX_SNDMAP2, 64'h0000000000000000) iREG_SAVESTATE_MAP2 (clk20, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[1], SS_MAP2_BACK, SS_MAP2);
eReg_SavestateV #(SSREG_INDEX_SNDMAP3, 64'h0000000000000000) iREG_SAVESTATE_MAP3 (clk20, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[2], SS_MAP3_BACK, SS_MAP3);
eReg_SavestateV #(SSREG_INDEX_SNDMAP4, 64'h0000000000000000) iREG_SAVESTATE_MAP4 (clk20, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[3], SS_MAP4_BACK, SS_MAP4);
assign SaveStateBus_Dout = enable ? SaveStateBus_Dout_active : 64'h0000000000000000;
endmodule |
module MMC5(
input clk, // System clock
input ce, // M2 ~cpu_clk
input enable, // Mapper enabled
input [31:0] flags, // Cart flags
input [15:0] prg_ain, // prg address
inout [21:0] prg_aout_b, // prg address out
input prg_read, // prg read
input prg_write, // prg write
input [7:0] prg_din, // prg data in
inout [7:0] prg_dout_b, // prg data out
inout prg_allow_b, // Enable access to memory for the specified operation.
input [13:0] chr_ain, // chr address in
inout [21:0] chr_aout_b, // chr address out
input chr_read, // chr ram read
inout chr_allow_b, // chr allow write
inout vram_a10_b, // Value for A10 address line
inout vram_ce_b, // True if the address should be routed to the internal 2kB VRAM.
inout irq_b, // IRQ
input [15:0] audio_in, // Inverted audio from APU
inout [15:0] audio_b, // Mixed audio output
inout [15:0] flags_out_b, // flags {0, 0, 0, 0, has_savestate, prg_conflict, prg_bus_write, has_chr_dout}
// Special ports
input [7:0] audio_dout,
input [13:0] chr_ain_o,
input chr_ex, // Extra sprites fetch active
input [7:0] chr_din, // CHR Data in
input chr_write, // CHR Write
inout [7:0] chr_dout_b, // chr data (non standard)
input paused,
// savestates
input [63:0] SaveStateBus_Din,
input [ 9:0] SaveStateBus_Adr,
input SaveStateBus_wren,
input SaveStateBus_rst,
input SaveStateBus_load,
output [63:0] SaveStateBus_Dout,
input Savestate_MAPRAMactive,
input [9:0] Savestate_MAPRAMAddr,
input Savestate_MAPRAMRdEn,
input Savestate_MAPRAMWrEn,
input [7:0] Savestate_MAPRAMWriteData,
output reg [7:0] Savestate_MAPRAMReadData
);
assign prg_aout_b = enable ? prg_aout : 22'hZ;
assign prg_dout_b = enable ? prg_dout : 8'hZ;
assign prg_allow_b = enable ? prg_allow : 1'hZ;
assign chr_aout_b = enable ? chr_aout : 22'hZ;
assign chr_dout_b = enable ? chr_dout : 8'hZ;
assign chr_allow_b = enable ? chr_allow : 1'hZ;
assign vram_a10_b = enable ? vram_a10 : 1'hZ;
assign vram_ce_b = enable ? vram_ce : 1'hZ;
assign irq_b = enable ? irq : 1'hZ;
assign flags_out_b = enable ? flags_out : 16'hZ;
assign audio_b = enable ? audio : 16'hZ;
wire [21:0] prg_aout;
reg [21:0] chr_aout;
wire prg_allow;
wire chr_allow;
wire vram_a10;
reg [7:0] chr_dout, prg_dout;
wire vram_ce;
wire [15:0] flags_out = {12'h0, 1'b1, 1'b0, prg_bus_write, has_chr_dout};
wire irq;
reg prg_bus_write;
wire has_chr_dout;
wire [15:0] audio = audio_in;
reg [1:0] prg_mode, chr_mode;
reg prg_protect_1, prg_protect_2;
reg [1:0] extended_ram_mode;
reg [7:0] mirroring;
reg [7:0] fill_tile;
reg [1:0] fill_attr;
reg [2:0] prg_ram_bank;
reg [7:0] prg_bank_0, prg_bank_1, prg_bank_2;
reg [6:0] prg_bank_3;
reg [9:0] chr_bank_0, chr_bank_1, chr_bank_2, chr_bank_3,
chr_bank_4, chr_bank_5, chr_bank_6, chr_bank_7,
chr_bank_8, chr_bank_9, chr_bank_a, chr_bank_b;
reg [1:0] upper_chr_bank_bits;
reg chr_last; // Which CHR set was written to last?
reg [4:0] vsplit_startstop;
reg vsplit_enable, vsplit_side;
reg [7:0] vsplit_scroll, vsplit_bank;
reg [7:0] irq_scanline;
reg irq_enable;
reg irq_pending, irq_pending_clear;
reg [7:0] multiplier_1;
reg [7:0] multiplier_2;
wire [15:0] multiply_result = multiplier_1 * multiplier_2;
reg [7:0] last_read_exattr;
reg [7:0] last_read_vram;
reg last_chr_read;
reg [7:0] vscroll; // Current y scroll for the split region
reg in_split_area;
reg rendering_en;
reg ppu_sprite16_r;
wire sprite8x16_mode = ppu_sprite16_r & rendering_en;
reg ppu_in_frame, last_ppu_in_frame;
reg [7:0] ppu_scanline;
reg [11:0] ppu_last_nt_addr;
reg [1:0] ppu_nt_read_cnt, ppu_no_rd_read_cnt;
reg [5:0] ppu_tile_cnt;
reg last_chr_a13;
reg is_sprite_fetch;
// is_sprite_fetch goes high during the unused NT fetches of the first sprite.
// That is too late for the first extra sprite so also use chr_ex here.
wire is_bg_fetch = ~(is_sprite_fetch | chr_ex);
// On an original NES these PPU addresses should be latched because the lower 8 bits
// are overwritten with the read data on the 2nd cycle when PPU_/RD goes low.
// In the core the address is not changed so latching is not needed.
wire ppu_is_tile_addr = (~chr_ain[13]);
wire ppu_is_at_addr = (chr_ain[13:12] == 2'b10) & (&chr_ain[9:6]);
wire ppu_is_nt_addr = (chr_ain[13:12] == 2'b10) & (~&chr_ain[9:6]);
// Block RAM, otherwise we need to time multiplex..
reg [9:0] ram_addrA;
reg ram_wrenA;
reg [7:0] ram_dataA;
wire [9:0] ram_addrB = Savestate_MAPRAMactive ? Savestate_MAPRAMAddr : exram_read_addr;
wire ram_wrenB = Savestate_MAPRAMactive ? Savestate_MAPRAMWrEn : 1'b0;
wire [7:0] ram_dataB = Savestate_MAPRAMactive ? Savestate_MAPRAMWriteData : 8'b0;
wire [7:0] last_read_ram;
dpram #(.widthad_a(10)) expansion_ram
(
.clock_a (clk),
.address_a (ram_addrA),
.wren_a (ram_wrenA),
.byteena_a (1),
.data_a (ram_dataA),
.clock_b (clk),
.address_b (ram_addrB),
.wren_b (ram_wrenB),
.byteena_b (1),
.data_b (ram_dataB),
.q_b (last_read_ram)
);
// Handle IO register writes
always @(posedge clk) begin
ram_wrenA <= 1'b0;
if (ce) begin
if (prg_write && prg_ain[15:10] == 6'b010100) begin // $5000-$53FF
//if (prg_ain <= 16'h5113) $write("%X <= %X (%d)\n", prg_ain, prg_din, ppu_scanline);
casez(prg_ain[9:0])
10'h100: prg_mode <= prg_din[1:0];
10'h101: chr_mode <= prg_din[1:0];
10'h102: prg_protect_1 <= (prg_din[1:0] == 2'b10);
10'h103: prg_protect_2 <= (prg_din[1:0] == 2'b01);
10'h104: extended_ram_mode <= prg_din[1:0];
10'h105: mirroring <= prg_din;
10'h106: fill_tile <= prg_din;
10'h107: fill_attr <= prg_din[1:0];
10'h113: prg_ram_bank <= prg_din[2:0];
10'h114: prg_bank_0 <= prg_din;
10'h115: prg_bank_1 <= prg_din;
10'h116: prg_bank_2 <= prg_din;
10'h117: prg_bank_3 <= prg_din[6:0];
10'h120: chr_bank_0 <= {upper_chr_bank_bits, prg_din};
10'h121: chr_bank_1 <= {upper_chr_bank_bits, prg_din};
10'h122: chr_bank_2 <= {upper_chr_bank_bits, prg_din};
10'h123: chr_bank_3 <= {upper_chr_bank_bits, prg_din};
10'h124: chr_bank_4 <= {upper_chr_bank_bits, prg_din};
10'h125: chr_bank_5 <= {upper_chr_bank_bits, prg_din};
10'h126: chr_bank_6 <= {upper_chr_bank_bits, prg_din};
10'h127: chr_bank_7 <= {upper_chr_bank_bits, prg_din};
10'h128: chr_bank_8 <= {upper_chr_bank_bits, prg_din};
10'h129: chr_bank_9 <= {upper_chr_bank_bits, prg_din};
10'h12a: chr_bank_a <= {upper_chr_bank_bits, prg_din};
10'h12b: chr_bank_b <= {upper_chr_bank_bits, prg_din};
10'h130: upper_chr_bank_bits <= prg_din[1:0];
10'h200: {vsplit_enable, vsplit_side, vsplit_startstop} <= {prg_din[7:6], prg_din[4:0]};
10'h201: vsplit_scroll <= prg_din;
10'h202: vsplit_bank <= prg_din;
10'h203: irq_scanline <= prg_din;
10'h204: irq_enable <= prg_din[7];
10'h205: multiplier_1 <= prg_din;
10'h206: multiplier_2 <= prg_din;
default: begin end
endcase
// Remember which set of CHR was written to last.
// chr_last is set to 0 when changing bank with sprites set to 8x8
if (prg_ain[9:4] == 6'b010010) //(prg_ain[9:0] >= 10'h120 && prg_ain[9:0] < 10'h130)
chr_last <= prg_ain[3] & ppu_sprite16_r;
end
if (prg_write && prg_ain == 16'h2000) begin // $2000
ppu_sprite16_r <= prg_din[5];
if (~prg_din[5]) // chr_last is set to 0 when changing sprite size to 8x8
chr_last <= 0;
end
if (prg_write && prg_ain == 16'h2001) begin // $2001
rendering_en <= |prg_din[4:3];
end
end
// Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)
// Mode 2 - Readable and writable
// Mode 3 - Read-only
if (extended_ram_mode != 3) begin
if (~paused && !ppu_in_frame && !extended_ram_mode[1] && chr_write && (mirrbits == 2) && chr_ain[13]) begin
ram_addrA <= chr_ain[9:0];
ram_dataA <= chr_din;
ram_wrenA <= 1'b1;
end else if (ce && prg_write && prg_ain[15:10] == 6'b010111) begin // $5C00-$5FFF
ram_addrA <= prg_ain[9:0];
ram_dataA <= (extended_ram_mode[1] || ppu_in_frame) ? prg_din : 8'd0;
ram_wrenA <= 1'b1;
end
end
if (~enable) begin
prg_bank_3 <= 7'h7F;
prg_mode <= 3;
end
if (SaveStateBus_load) begin
prg_mode <= SS_MAP1[ 1: 0];
chr_mode <= SS_MAP1[ 3: 2];
prg_protect_1 <= SS_MAP1[ 4];
prg_protect_2 <= SS_MAP1[ 5];
extended_ram_mode <= SS_MAP1[ 7: 6];
mirroring <= SS_MAP1[15: 8];
fill_tile <= SS_MAP1[23:16];
fill_attr <= SS_MAP1[25:24];
prg_ram_bank <= SS_MAP1[28:26];
prg_bank_0 <= SS_MAP1[36:29];
prg_bank_1 <= SS_MAP1[44:37];
prg_bank_2 <= SS_MAP1[52:45];
prg_bank_3 <= SS_MAP1[59:53];
chr_bank_0 <= SS_MAP2[ 9: 0];
chr_bank_1 <= SS_MAP2[19:10];
chr_bank_2 <= SS_MAP2[29:20];
chr_bank_3 <= SS_MAP2[39:30];
chr_bank_4 <= SS_MAP2[49:40];
chr_bank_5 <= SS_MAP2[59:50];
chr_bank_6 <= SS_MAP3[ 9: 0];
chr_bank_7 <= SS_MAP3[19:10];
chr_bank_8 <= SS_MAP3[29:20];
chr_bank_9 <= SS_MAP3[39:30];
chr_bank_a <= SS_MAP3[49:40];
chr_bank_b <= SS_MAP3[59:50];
upper_chr_bank_bits <= SS_MAP4[ 1: 0];
vsplit_enable <= SS_MAP4[ 2];
vsplit_side <= SS_MAP4[ 3];
vsplit_startstop <= SS_MAP4[ 8: 4];
vsplit_scroll <= SS_MAP4[16: 9];
vsplit_bank <= SS_MAP4[24:17];
irq_scanline <= SS_MAP4[32:25];
irq_enable <= SS_MAP4[ 33];
multiplier_1 <= SS_MAP4[41:34];
multiplier_2 <= SS_MAP4[49:42];
chr_last <= SS_MAP4[ 50];
ppu_sprite16_r <= SS_MAP4[ 51];
end
end
assign SS_MAP1_BACK[ 1: 0] = prg_mode;
assign SS_MAP1_BACK[ 3: 2] = chr_mode;
assign SS_MAP1_BACK[ 4] = prg_protect_1;
assign SS_MAP1_BACK[ 5] = prg_protect_2;
assign SS_MAP1_BACK[ 7: 6] = extended_ram_mode;
assign SS_MAP1_BACK[15: 8] = mirroring;
assign SS_MAP1_BACK[23:16] = fill_tile;
assign SS_MAP1_BACK[25:24] = fill_attr;
assign SS_MAP1_BACK[28:26] = prg_ram_bank;
assign SS_MAP1_BACK[36:29] = prg_bank_0;
assign SS_MAP1_BACK[44:37] = prg_bank_1;
assign SS_MAP1_BACK[52:45] = prg_bank_2;
assign SS_MAP1_BACK[59:53] = prg_bank_3;
assign SS_MAP1_BACK[63:60] = 4'b0; // free to be used
assign SS_MAP2_BACK[ 9: 0] = chr_bank_0;
assign SS_MAP2_BACK[19:10] = chr_bank_1;
assign SS_MAP2_BACK[29:20] = chr_bank_2;
assign SS_MAP2_BACK[39:30] = chr_bank_3;
assign SS_MAP2_BACK[49:40] = chr_bank_4;
assign SS_MAP2_BACK[59:50] = chr_bank_5;
assign SS_MAP2_BACK[63:60] = 4'b0; // free to be used
assign SS_MAP3_BACK[ 9: 0] = chr_bank_6;
assign SS_MAP3_BACK[19:10] = chr_bank_7;
assign SS_MAP3_BACK[29:20] = chr_bank_8;
assign SS_MAP3_BACK[39:30] = chr_bank_9;
assign SS_MAP3_BACK[49:40] = chr_bank_a;
assign SS_MAP3_BACK[59:50] = chr_bank_b;
assign SS_MAP3_BACK[63:60] = 4'b0; // free to be used
assign SS_MAP4_BACK[ 1: 0] = upper_chr_bank_bits;
assign SS_MAP4_BACK[ 2] = vsplit_enable;
assign SS_MAP4_BACK[ 3] = vsplit_side;
assign SS_MAP4_BACK[ 8: 4] = vsplit_startstop;
assign SS_MAP4_BACK[16: 9] = vsplit_scroll;
assign SS_MAP4_BACK[24:17] = vsplit_bank;
assign SS_MAP4_BACK[32:25] = irq_scanline;
assign SS_MAP4_BACK[ 33] = irq_enable;
assign SS_MAP4_BACK[41:34] = multiplier_1;
assign SS_MAP4_BACK[49:42] = multiplier_2;
assign SS_MAP4_BACK[ 50] = chr_last;
assign SS_MAP4_BACK[ 51] = ppu_sprite16_r;
assign SS_MAP4_BACK[63:52] = 12'b0; // free to be used
// Read from MMC5
always @* begin
prg_bus_write = 1'b1;
if (prg_ain[15:10] == 6'b010111 && extended_ram_mode[1]) begin
prg_dout = last_read_ram;
end else if (prg_ain == 16'h5204) begin
prg_dout = {irq_pending, ppu_in_frame, 6'b111111};
end else if (prg_ain == 16'h5205) begin
prg_dout = multiply_result[7:0];
end else if (prg_ain == 16'h5206) begin
prg_dout = multiply_result[15:8];
end else if (prg_ain == 16'h5015) begin
prg_dout = {6'h00, audio_dout[1:0]};
// TODO: 5010
end else begin
prg_dout = 8'hFF; // By default open bus.
prg_bus_write = 0;
end
end
// Scanline detection
always @(posedge clk) begin
if (SaveStateBus_load) begin
ppu_in_frame <= SS_MAP5[ 0];
irq_pending <= SS_MAP5[ 1];
in_split_area <= SS_MAP5[ 2];
ppu_tile_cnt <= SS_MAP5[ 8: 3];
vscroll <= SS_MAP5[16: 9];
last_ppu_in_frame <= SS_MAP5[ 34];
ppu_scanline <= SS_MAP5[42:35];
ppu_nt_read_cnt <= SS_MAP5[44:43];
ppu_no_rd_read_cnt <= SS_MAP5[46:45];
ppu_last_nt_addr <= SS_MAP5[58:47];
irq_pending_clear <= SS_MAP5[ 59];
is_sprite_fetch <= SS_MAP5[ 60];
last_chr_a13 <= SS_MAP5[ 61];
end else begin
if (~paused & ~last_chr_read & chr_read) begin
ppu_last_nt_addr <= chr_ain_o[11:0];
// Detect 3 PPU NT reads ($2xxx) from the same address
// In_frame and IRQ will be asserted at the 4th read (address does not matter)
// If the 4th and following reads are from the same NT address then
// every read will increment the scanline counter.
if (~&ppu_nt_read_cnt)
ppu_nt_read_cnt <= ppu_nt_read_cnt + 1'b1;
else begin
if (~ppu_in_frame) begin
ppu_in_frame <= 1;
ppu_scanline <= 0;
ppu_tile_cnt <= 6'd2;
vscroll <= vsplit_scroll;
end else begin
// Testing shows the MMC5 goes out of frame when scanline 240 is detected.
// Normally this should not happen because the PPU is idle on that line
// but it could happen if the scanline counter is incremented more than
// once per line which is what the MMC5 scanline glitch test does.
if (ppu_scanline == 8'd239) begin
ppu_in_frame <= 0;
end else begin
ppu_scanline <= ppu_scanline + 1'b1;
if (ppu_scanline + 1'b1 == irq_scanline) begin
irq_pending <= 1;
end
end
end
end
if (chr_ain_o[13:12] != 2'b10 || (|ppu_nt_read_cnt && ppu_last_nt_addr != chr_ain_o[11:0])) begin
ppu_nt_read_cnt <= 0;
end
last_chr_a13 <= chr_ain_o[13];
if (ppu_in_frame) begin
if (last_chr_a13 & ~chr_ain_o[13]) begin
if (ppu_tile_cnt == 41) begin // Last sprite tile fetch
ppu_tile_cnt <= 0; // First 2 background fetches for the next scanline
vscroll <= (vscroll == 239) ? 8'd0 : (vscroll + 1'b1);
end else begin
ppu_tile_cnt <= ppu_tile_cnt + 1'b1;
end
end
if (~last_chr_a13 & chr_ain_o[13]) begin
if (ppu_tile_cnt == 34)
is_sprite_fetch <= 1;
if (ppu_tile_cnt == 0)
is_sprite_fetch <= 0;
if (ppu_tile_cnt == 0)
in_split_area <= !vsplit_side;
else if (ppu_tile_cnt == {1'b0, vsplit_startstop})
in_split_area <= vsplit_side;
else if (ppu_tile_cnt == 34)
in_split_area <= 0;
end
end
end
// The "in-frame" flag is cleared when 3 CPU cycles pass without a PPU read having occurred
if (~paused) begin
if (chr_read) begin
ppu_no_rd_read_cnt <= 0;
end else if (ce & ppu_in_frame) begin
ppu_no_rd_read_cnt <= ppu_no_rd_read_cnt + 1'b1;
if (ppu_no_rd_read_cnt == 2'd2) begin
ppu_in_frame <= 0;
end
end
end
if (ce) begin
if (prg_read) begin
if ({prg_ain[15:1], 1'b0} == 16'hFFFA) begin // $FFFA/FFFB
ppu_in_frame <= 0;
end
if (prg_ain == 16'h5204) begin
// MMC5 scanline glitch test expects irq_pending to be cleared after the read.
irq_pending_clear <= 1;
end
end
if (irq_pending_clear) begin
if (irq_pending) irq_pending <= 0;
irq_pending_clear <= 0;
end
end
if (~paused) begin
last_ppu_in_frame <= ppu_in_frame;
if (last_ppu_in_frame & ~ppu_in_frame) begin
ppu_nt_read_cnt <= 0;
ppu_no_rd_read_cnt <= 0;
irq_pending <= 0;
in_split_area <= 0;
is_sprite_fetch <= 0;
end
end
end
end
assign irq = irq_pending && irq_enable;
// Mirroring bits
// %00 = NES internal NTA
// %01 = NES internal NTB
// %10 = use ExRAM as NT
// %11 = Fill Mode
wire [1:0] mirrbits = (chr_ain[11:10] == 0) ? mirroring[1:0] :
(chr_ain[11:10] == 1) ? mirroring[3:2] :
(chr_ain[11:10] == 2) ? mirroring[5:4] :
mirroring[7:6];
// Compute the new overriden nametable/attr address the split will read from instead
// when the VSplit is active.
// Cycle 0, 1 = nametable
// Cycle 2, 3 = attribute
// Named it loopy so I can copypaste from PPU code :)
wire [9:0] loopy = {vscroll[7:3], ppu_tile_cnt[4:0]};
wire [9:0] split_addr = (ppu_is_nt_addr) ? loopy : // name table
{4'b1111, loopy[9:7], loopy[4:2]}; // attribute table
// Selects 2 out of the attr bits read from exram.
wire [1:0] split_attr = (!loopy[1] && !loopy[6]) ? last_read_ram[1:0] :
( loopy[1] && !loopy[6]) ? last_read_ram[3:2] :
(!loopy[1] && loopy[6]) ? last_read_ram[5:4] :
last_read_ram[7:6];
// If splitting is active or not
wire insplit = in_split_area && vsplit_enable && ~chr_ex;
// Currently reading the attribute byte?
wire exattr_read = (extended_ram_mode == 1) && ppu_is_at_addr && ppu_in_frame;
// If the current chr read should be redirected from |chr_dout| instead.
assign has_chr_dout = chr_ain[13] && (mirrbits[1] || insplit || exattr_read);
wire [1:0] override_attr = insplit ? split_attr : (extended_ram_mode == 1) ? last_read_exattr[7:6] : fill_attr;
always @* begin
if (ppu_in_frame) begin
if (ppu_is_nt_addr) begin
// Name table fetch
if (insplit || mirrbits[0] == 0)
chr_dout = (extended_ram_mode[1] ? 8'b0 : last_read_ram);
else begin
// Inserting Filltile
chr_dout = fill_tile;
end
end else begin
// Attribute table fetch
if (!insplit && !exattr_read && mirrbits[0] == 0)
chr_dout = (extended_ram_mode[1] ? 8'b0 : last_read_ram);
else
chr_dout = {override_attr, override_attr, override_attr, override_attr};
end
end else begin
chr_dout = last_read_vram;
end
end
// Handle reading from the expansion ram.
// 0 - Use as extra nametable (possibly for split mode)
// 1 - Use as extended attribute data OR an extra nametable
// 2 - Use as ordinary RAM
// 3 - Use as ordinary RAM, write protected
wire [9:0] exram_read_addr = extended_ram_mode[1] ? prg_ain[9:0] : insplit ? split_addr : chr_ain[9:0];
always @(posedge clk) begin
if (SaveStateBus_load) begin
last_read_exattr <= SS_MAP5[24:17];
last_read_vram <= SS_MAP5[32:25];
last_chr_read <= SS_MAP5[ 33];
end else if (~paused) begin
last_chr_read <= chr_read;
if (~last_chr_read & chr_read) begin
last_read_vram <= extended_ram_mode[1] ? 8'b0 : last_read_ram;
if (ppu_is_nt_addr & ppu_in_frame) begin
last_read_exattr <= last_read_ram;
end
end
end
end
assign SS_MAP5_BACK[ 0] = ppu_in_frame;
assign SS_MAP5_BACK[ 1] = irq_pending;
assign SS_MAP5_BACK[ 2] = in_split_area;
assign SS_MAP5_BACK[ 8: 3] = ppu_tile_cnt;
assign SS_MAP5_BACK[16: 9] = vscroll;
assign SS_MAP5_BACK[24:17] = last_read_exattr;
assign SS_MAP5_BACK[32:25] = last_read_vram;
assign SS_MAP5_BACK[ 33] = last_chr_read;
assign SS_MAP5_BACK[ 34] = last_ppu_in_frame;
assign SS_MAP5_BACK[42:35] = ppu_scanline;
assign SS_MAP5_BACK[44:43] = ppu_nt_read_cnt;
assign SS_MAP5_BACK[46:45] = ppu_no_rd_read_cnt;
assign SS_MAP5_BACK[58:47] = ppu_last_nt_addr;
assign SS_MAP5_BACK[ 59] = irq_pending_clear;
assign SS_MAP5_BACK[ 60] = is_sprite_fetch;
assign SS_MAP5_BACK[ 61] = last_chr_a13;
assign SS_MAP5_BACK[63:62] = 0; // free to be used
// Compute PRG address to read from.
reg [7:0] prgsel;
always @* begin
casez({prg_mode, prg_ain[15:13]})
5'b??_0??: prgsel = {5'b0xxxx, prg_ram_bank}; // $6000-$7FFF all modes
5'b00_1??: prgsel = {1'b1, prg_bank_3[6:2], prg_ain[14:13]}; // $8000-$FFFF mode 0, 32kB (prg_bank_3, skip 2 bits)
5'b01_10?: prgsel = { prg_bank_1[7:1], prg_ain[13]}; // $8000-$BFFF mode 1, 16kB (prg_bank_1, skip 1 bit)
5'b01_11?: prgsel = {1'b1, prg_bank_3[6:1], prg_ain[13]}; // $C000-$FFFF mode 1, 16kB (prg_bank_3, skip 1 bit)
5'b10_10?: prgsel = { prg_bank_1[7:1], prg_ain[13]}; // $8000-$BFFF mode 2, 16kB (prg_bank_1, skip 1 bit)
5'b10_110: prgsel = { prg_bank_2}; // $C000-$DFFF mode 2, 8kB (prg_bank_2)
5'b10_111: prgsel = {1'b1, prg_bank_3}; // $E000-$FFFF mode 2, 8kB (prg_bank_3)
5'b11_100: prgsel = { prg_bank_0}; // $8000-$9FFF mode 3, 8kB (prg_bank_0)
5'b11_101: prgsel = { prg_bank_1}; // $A000-$BFFF mode 3, 8kB (prg_bank_1)
5'b11_110: prgsel = { prg_bank_2}; // $C000-$DFFF mode 3, 8kB (prg_bank_2)
5'b11_111: prgsel = {1'b1, prg_bank_3}; // $E000-$FFFF mode 3, 8kB (prg_bank_3)
endcase
//Original
//prgsel[7] = !prgsel[7]; // 0 means RAM, doh.
//Done below
//if (prgsel[7])
// prgsel[7] = 0; //ROM
//else
// // Limit to 64k RAM.
// prgsel[7:3] = 5'b1_1100; //RAM location for saves
end
assign prg_aout = {prgsel[7] ? {2'b00, prgsel[6:0]} : {6'b11_1100, prgsel[2:0]}, prg_ain[12:0]}; // 8kB banks
// Registers $5120-$5127 apply to sprite graphics and $5128-$512B for background graphics, but ONLY when 8x16 sprites are enabled.
// Otherwise, the last set of registers written to (either $5120-$5127 or $5128-$512B) will be used for all graphics.
// 0 if using $5120-$5127, 1 if using $5128-$512F
wire chrset = (~sprite8x16_mode) ? 1'd0 : (ppu_in_frame) ? is_bg_fetch : chr_last;
reg [9:0] chrsel;
always @* begin
casez({chr_mode, chr_ain[12:10], chrset})
6'b00_???_0: chrsel = {chr_bank_7[6:0], chr_ain[12:10]}; // $0000-$1FFF mode 0, 8 kB
6'b00_???_1: chrsel = {chr_bank_b[6:0], chr_ain[12:10]}; // $0000-$1FFF mode 0, 8 kB
6'b01_0??_0: chrsel = {chr_bank_3[7:0], chr_ain[11:10]}; // $0000-$0FFF mode 1, 4 kB
6'b01_1??_0: chrsel = {chr_bank_7[7:0], chr_ain[11:10]}; // $1000-$1FFF mode 1, 4 kB
6'b01_???_1: chrsel = {chr_bank_b[7:0], chr_ain[11:10]}; // $0000-$0FFF mode 1, 4 kB
6'b10_00?_0: chrsel = {chr_bank_1[8:0], chr_ain[10]}; // $0000-$07FF mode 2, 2 kB
6'b10_01?_0: chrsel = {chr_bank_3[8:0], chr_ain[10]}; // $0800-$0FFF mode 2, 2 kB
6'b10_10?_0: chrsel = {chr_bank_5[8:0], chr_ain[10]}; // $1000-$17FF mode 2, 2 kB
6'b10_11?_0: chrsel = {chr_bank_7[8:0], chr_ain[10]}; // $1800-$1FFF mode 2, 2 kB
6'b10_?0?_1: chrsel = {chr_bank_9[8:0], chr_ain[10]}; // $0000-$07FF mode 2, 2 kB
6'b10_?1?_1: chrsel = {chr_bank_b[8:0], chr_ain[10]}; // $0800-$0FFF mode 2, 2 kB
6'b11_000_0: chrsel = chr_bank_0; // $0000-$03FF mode 3, 1 kB
6'b11_001_0: chrsel = chr_bank_1; // $0400-$07FF mode 3, 1 kB
6'b11_010_0: chrsel = chr_bank_2; // $0800-$0BFF mode 3, 1 kB
6'b11_011_0: chrsel = chr_bank_3; // $0C00-$0FFF mode 3, 1 kB
6'b11_100_0: chrsel = chr_bank_4; // $1000-$13FF mode 3, 1 kB
6'b11_101_0: chrsel = chr_bank_5; // $1400-$17FF mode 3, 1 kB
6'b11_110_0: chrsel = chr_bank_6; // $1800-$1BFF mode 3, 1 kB
6'b11_111_0: chrsel = chr_bank_7; // $1C00-$1FFF mode 3, 1 kB
6'b11_?00_1: chrsel = chr_bank_8; // $0000-$03FF mode 3, 1 kB
6'b11_?01_1: chrsel = chr_bank_9; // $0400-$07FF mode 3, 1 kB
6'b11_?10_1: chrsel = chr_bank_a; // $0800-$0BFF mode 3, 1 kB
6'b11_?11_1: chrsel = chr_bank_b; // $0C00-$0FFF mode 3, 1 kB
endcase
chr_aout = {2'b10, chrsel, chr_ain[9:0]}; // 1kB banks
// Override |chr_aout| if we're in a vertical split.
if (ppu_in_frame && insplit) begin
//$write("In vertical split!\n");
// chr_aout = {2'b10, vsplit_bank, chr_ain[11:3], vscroll[2:0]}; // SL
chr_aout = {2'b10, vsplit_bank, chr_ain[11:3], chr_ain[2:0]}; // CL
end else if (ppu_in_frame && extended_ram_mode == 1 && is_bg_fetch && ppu_is_tile_addr) begin
//$write("In exram thingy!\n");
// Extended attribute mode. Replace the page with the page from exram.
chr_aout = {2'b10, upper_chr_bank_bits, last_read_exattr[5:0], chr_ain[11:0]};
end
end
// The a10 VRAM address line. (Used for mirroring)
assign vram_a10 = mirrbits[0];
assign vram_ce = chr_ain[13] && !mirrbits[1];
// Writing to RAM is enabled only when the protect bits say so.
wire prg_ram_we = prg_protect_1 && prg_protect_2;
assign prg_allow = (prg_ain >= 16'h6000) && (!prg_write || ((!prgsel[7]) && prg_ram_we));
// MMC5 boards typically have no CHR RAM.
assign chr_allow = flags[15];
// savestate
always@(posedge clk) begin
if (enable) begin
if (Savestate_MAPRAMRdEn) begin
Savestate_MAPRAMReadData <= last_read_ram;
end
end else begin
Savestate_MAPRAMReadData <= 8'd0;
end
end
localparam SAVESTATE_MODULES = 5;
wire [63:0] SaveStateBus_wired_or[0:SAVESTATE_MODULES-1];
wire [63:0] SS_MAP1, SS_MAP2, SS_MAP3, SS_MAP4, SS_MAP5;
wire [63:0] SS_MAP1_BACK, SS_MAP2_BACK, SS_MAP3_BACK, SS_MAP4_BACK, SS_MAP5_BACK;
wire [63:0] SaveStateBus_Dout_active = SaveStateBus_wired_or[0] | SaveStateBus_wired_or[1] | SaveStateBus_wired_or[2] | SaveStateBus_wired_or[3] | SaveStateBus_wired_or[4];
eReg_SavestateV #(SSREG_INDEX_MAP1, 64'h0000000000000000) iREG_SAVESTATE_MAP1 (clk, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[0], SS_MAP1_BACK, SS_MAP1);
eReg_SavestateV #(SSREG_INDEX_MAP2, 64'h0000000000000000) iREG_SAVESTATE_MAP2 (clk, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[1], SS_MAP2_BACK, SS_MAP2);
eReg_SavestateV #(SSREG_INDEX_MAP3, 64'h0000000000000000) iREG_SAVESTATE_MAP3 (clk, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[2], SS_MAP3_BACK, SS_MAP3);
eReg_SavestateV #(SSREG_INDEX_MAP4, 64'h0000000000000000) iREG_SAVESTATE_MAP4 (clk, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[3], SS_MAP4_BACK, SS_MAP4);
eReg_SavestateV #(SSREG_INDEX_MAP5, 64'h0000000000000000) iREG_SAVESTATE_MAP5 (clk, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[4], SS_MAP5_BACK, SS_MAP5);
assign SaveStateBus_Dout = enable ? SaveStateBus_Dout_active : 64'h0000000000000000;
endmodule |
module mmc5_mixed (
input clk,
input ce, // Negedge M2 (aka CPU ce)
input enable,
input wren,
input rden,
input [15:0] addr_in,
input [7:0] data_in,
output [7:0] data_out,
input [15:0] audio_in, // Inverted audio from APU
output [15:0] audio_out,
// savestates
input [63:0] SaveStateBus_Din,
input [ 9:0] SaveStateBus_Adr,
input SaveStateBus_wren,
input SaveStateBus_rst,
input SaveStateBus_load,
output [63:0] SaveStateBus_Dout
);
// NOTE: The apu volume is 100% of MMC5 and the polarity is reversed.
wire [16:0] audio_o = audio + audio_in;
wire [15:0] audio;
assign audio_out = audio_o[16:1];
wire apu_cs = (addr_in[15:5]==11'b0101_0000_000) && (addr_in[3]==0);
wire DmaReq; // 1 when DMC wants DMA
wire [15:0] DmaAddr; // Address DMC wants to read
reg odd_or_even;
wire apu_irq; // TODO: IRQ asserted
reg phi2;
always @(posedge clk) begin
phi2 <= ce;
if (~enable)
odd_or_even <= 0;
else if (ce)
odd_or_even <= ~odd_or_even;
if (SaveStateBus_load) begin
odd_or_even <= SS_MAP1[0];
end
end
assign SS_MAP1_BACK[ 0] = odd_or_even;
assign SS_MAP1_BACK[63: 1] = 63'b0; // free to be used
APU mmc5apu(
.MMC5 (1),
.clk (clk),
.ce (ce),
.PHI2 (phi2),
.CS (apu_cs),
.reset (~enable | SaveStateBus_load),
.ADDR (addr_in[4:0]),
.DIN (data_in),
.DOUT (data_out),
.RW (~wren),
.audio_channels (5'b10011),
.Sample (audio),
.DmaReq (DmaReq),
.DmaAck (1),
.DmaAddr (DmaAddr),
.DmaData (0),
.odd_or_even (odd_or_even),
.IRQ (apu_irq),
// savestates
.SaveStateBus_Din (SaveStateBus_Din ),
.SaveStateBus_Adr (SaveStateBus_Adr ),
.SaveStateBus_wren (SaveStateBus_wren),
.SaveStateBus_rst (SaveStateBus_rst ),
.SaveStateBus_load (SaveStateBus_load ),
.SaveStateBus_Dout (SaveStateBus_wired_or[1])
);
defparam mmc5apu.SSREG_INDEX_TOP = SSREG_INDEX_SNDMAP1;
defparam mmc5apu.SSREG_INDEX_DMC1 = SSREG_INDEX_SNDMAP2;
defparam mmc5apu.SSREG_INDEX_DMC2 = SSREG_INDEX_SNDMAP3;
defparam mmc5apu.SSREG_INDEX_FCT = SSREG_INDEX_SNDMAP4;
// savestates
localparam SAVESTATE_MODULES = 2;
wire [63:0] SaveStateBus_wired_or[0:SAVESTATE_MODULES-1];
wire [63:0] SS_MAP1;
wire [63:0] SS_MAP1_BACK;
wire [63:0] SaveStateBus_Dout_active = SaveStateBus_wired_or[0] | SaveStateBus_wired_or[1];
eReg_SavestateV #(SSREG_INDEX_SNDMAP5, 64'h0000000000000000) iREG_SAVESTATE_MAP1 (clk, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_wired_or[0], SS_MAP1_BACK, SS_MAP1);
assign SaveStateBus_Dout = enable ? SaveStateBus_Dout_active : 64'h0000000000000000;
endmodule |
module ddr3_p0_memphy_m10(
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
pll_locked,
afi_addr,
afi_cke,
afi_cs_n,
afi_ba,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_odt,
afi_rst_n,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_valid,
afi_cal_debug_info,
afi_cal_success,
afi_cal_fail,
mem_a,
mem_ba,
mem_odt,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_reset_n,
mem_ck,
mem_ck_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqs_n,
phy_read_latency_counter,
phy_read_increment_vfifo_hr,
phy_cal_debug_info,
phy_read_fifo_reset,
phy_vfifo_rd_en_override,
calib_skip_steps,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
pll_capture0_clk,
pll_capture1_clk,
phy_clk,
phy_reset_n,
pd_reset_n,
pd_ack,
pd_up,
pd_down
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DEBUG_INFO_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter AFI_RATE_RATIO = "";
// Write Datapath
//The sequencer uses this value to control write latency during calibration
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
parameter NUM_WRITE_FR_CYCLE_SHIFTS = "";
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
parameter CALIB_REG_WIDTH = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Read Datapath parameters
parameter MEM_T_RL = "";
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam MAX_READ_LATENCY = MEM_T_RL/2 + 12;
localparam INVERT_HR_CLOCK = MEM_T_RL % 2;
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; //Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n;
input pll_locked;
output ctl_reset_export_n;
output ctl_reset_n;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [AFI_ADDRESS_WIDTH-1:0] afi_addr;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_BANK_WIDTH-1:0] afi_ba;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
input [MEM_CK_WIDTH-1:0] afi_mem_clk_disable;
input [AFI_DQS_WIDTH-1:0] afi_dqs_burst;
// Write data interface
input [AFI_DATA_WIDTH-1:0] afi_wdata; //write data
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
// Read data interface
output [AFI_DATA_WIDTH-1:0] afi_rdata; //read data
input [AFI_RATE_RATIO-1:0] afi_rdata_en;
output [AFI_RATE_RATIO-1:0] afi_rdata_valid;
// Status interface
input afi_cal_success; //calibration success
input afi_cal_fail;
output [AFI_DEBUG_INFO_WIDTH - 1:0] afi_cal_debug_info;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output mem_reset_n;
inout [MEM_CK_WIDTH-1:0] mem_ck;
inout [MEM_CK_WIDTH-1:0] mem_ck_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_CHIP_SELECT_WIDTH-1:0] mem_cs_n;
output [MEM_DM_WIDTH-1:0] mem_dm;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [MAX_LATENCY_COUNT_WIDTH-1:0] phy_read_latency_counter;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_hr;
input [AFI_DEBUG_INFO_WIDTH - 1:0] phy_cal_debug_info;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_fifo_reset;
input [MEM_READ_DQS_WIDTH-1:0] phy_vfifo_rd_en_override;
output [CALIB_REG_WIDTH-1:0] calib_skip_steps;
// PLL Interface
input pll_afi_clk; //clocks AFI interface logic
input pll_mem_clk;
input pll_write_clk;
input pll_capture0_clk;
input pll_capture1_clk;
// output to sequencer
output phy_clk;
output phy_reset_n;
input pd_reset_n;
input pd_ack;
output pd_up;
output pd_down;
// END PORT SECTION
// ********************************************************************************************************************************
// PHY clock tree buffered clock driving to DDIO
wire pll_mem_clk_ddio;
wire pll_write_clk_ddio;
wire pll_capture0_clk_ddio;
wire pll_capture1_clk_ddio;
wire [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
wire [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
wire [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
wire [AFI_DATA_WIDTH-1:0] ddio_phy_dq;
wire [MEM_READ_DQS_WIDTH-1:0] read_capture_clk_hr_dq;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_resync_clk;
wire invert_hr_clock;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / NUM_OF_DQDQS;
localparam DQDQS_DDIO_PHY_DQ_WIDTH = AFI_DATA_WIDTH / NUM_OF_DQDQS;
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifndef SYNTH_FOR_SIM
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifndef SYNTH_FOR_SIM
`endif
`ifndef SYNTH_FOR_SIM
`endif
// ********************************************************************************************************************************
// Instantiate PHYCLK buffer for fitter
// ********************************************************************************************************************************
fiftyfivenm_phy_clkbuf uphy_clkbuf(
.inclk ({pll_capture1_clk, pll_capture0_clk, pll_write_clk, pll_mem_clk}),
.outclk ({pll_capture1_clk_ddio, pll_capture0_clk_ddio, pll_write_clk_ddio, pll_mem_clk_ddio})
);
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
ddr3_p0_reset_m10 ureset(
.pll_afi_clk (pll_afi_clk),
.pll_write_clk (pll_write_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.ctl_reset_n (ctl_reset_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
assign calib_skip_steps = seq_calib_init_reg;
assign afi_cal_debug_info = phy_cal_debug_info;
assign phy_clk = pll_afi_clk;
assign phy_reset_n = reset_n_afi_clk[0];
// ********************************************************************************************************************************
// The address and command datapath is responsible for adding any flop stages/extra logic that may be required between the AFI
// interface and the output DDIOs.
// ********************************************************************************************************************************
ddr3_p0_addr_cmd_datapath uaddr_cmd_datapath(
.clk (pll_afi_clk),
.reset_n (reset_n_afi_clk[1]),
.afi_address (afi_addr),
.afi_cke (afi_cke),
.afi_cs_n (afi_cs_n),
.afi_bank (afi_ba),
.afi_odt (afi_odt),
.afi_ras_n (afi_ras_n),
.afi_cas_n (afi_cas_n),
.afi_we_n (afi_we_n),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.afi_rst_n (afi_rst_n),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_cs_n (phy_ddio_cs_n)
);
defparam uaddr_cmd_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_datapath.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_datapath.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_datapath.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_datapath.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uaddr_cmd_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uaddr_cmd_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uaddr_cmd_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uaddr_cmd_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_datapath.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_datapath.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_datapath.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_datapath.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uaddr_cmd_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uaddr_cmd_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uaddr_cmd_datapath.NUM_AC_FR_CYCLE_SHIFTS = NUM_AC_FR_CYCLE_SHIFTS;
// ********************************************************************************************************************************
// The write datapath is responsible for adding any flop stages/extra logic that may be required between the AFI interface
// and the output DDIOs.
// ********************************************************************************************************************************
ddr3_p0_write_datapath_m10 uwrite_datapath(
.pll_afi_clk (pll_afi_clk),
.reset_n (reset_n_afi_clk[2]),
.afi_dqs_en (afi_dqs_burst),
.afi_wdata (afi_wdata),
.afi_wdata_valid (afi_wdata_valid),
.afi_dm (afi_dm),
.phy_ddio_dq (phy_ddio_dq),
.phy_ddio_dqs_en (phy_ddio_dqs_en),
.phy_ddio_wrdata_en (phy_ddio_wrdata_en),
.phy_ddio_wrdata_mask (phy_ddio_wrdata_mask)
);
defparam uwrite_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uwrite_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uwrite_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uwrite_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uwrite_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uwrite_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uwrite_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uwrite_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uwrite_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uwrite_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uwrite_datapath.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uwrite_datapath.NUM_WRITE_PATH_FLOP_STAGES = NUM_WRITE_PATH_FLOP_STAGES;
defparam uwrite_datapath.NUM_WRITE_FR_CYCLE_SHIFTS = NUM_WRITE_FR_CYCLE_SHIFTS;
// ********************************************************************************************************************************
// The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
// It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
// ********************************************************************************************************************************
ddr3_p0_read_datapath_m10 uread_datapath(
.reset_n_afi_clk (reset_n_afi_clk[3]),
.pll_afi_clk (pll_afi_clk),
.read_capture_clk_hr_dq (read_capture_clk_hr_dq),
.rdata_hr (ddio_phy_dq),
.seq_read_increment_vfifo (phy_read_increment_vfifo_hr),
.seq_read_fifo_reset (phy_read_fifo_reset),
.seq_read_latency_counter (phy_read_latency_counter),
.afi_rdata_en (afi_rdata_en),
.afi_rdata (afi_rdata),
.afi_rdata_valid (afi_rdata_valid)
);
defparam uread_datapath.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uread_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uread_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uread_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uread_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uread_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uread_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uread_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uread_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uread_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uread_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uread_datapath.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uread_datapath.AFI_RATE_RATIO = AFI_RATE_RATIO;
defparam uread_datapath.NUM_OF_DQDQS = NUM_OF_DQDQS;
defparam uread_datapath.DQDQS_DATA_WIDTH = DQDQS_DATA_WIDTH;
defparam uread_datapath.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
defparam uread_datapath.MAX_READ_LATENCY = MAX_READ_LATENCY;
defparam uread_datapath.MEM_T_RL = MEM_T_RL;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
wire addr_cmd_clk;
wire mimic_clock;
assign addr_cmd_clk = pll_mem_clk_ddio;
localparam INVERT_OUTPUT_CLOCK = "true";
ddr3_p0_addr_cmd_pads_m10 uaddr_cmd_pads(
.reset_n (reset_n_afi_clk[3]),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk_ddio (pll_mem_clk_ddio),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (addr_cmd_clk),
.enable_mem_clk (~afi_mem_clk_disable),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mimic_clock (mimic_clock)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_pads.INVERT_OUTPUT_CLOCK = INVERT_OUTPUT_CLOCK;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
generate
if (INVERT_HR_CLOCK == 1)
assign invert_hr_clock = 1'b1;
else
assign invert_hr_clock = 1'b0;
endgenerate
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
wire dqs_busout;
// The phy_ddio_dq bus is the write data for all DQS groups in one
// AFI cycle. The bus is ordered by time slot and subordered by DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
// Extract the write data targeting the current DQS group
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t0 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t1 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t2 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t3 = phy_ddio_dq [DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)];
// Extract the OE signal targeting the current DQS group
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_wrdata_en_t0 = {DQDQS_DATA_WIDTH{phy_ddio_dqs_en[i]}};
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_wrdata_en_t1 = {DQDQS_DATA_WIDTH{phy_ddio_dqs_en[i+NUM_OF_DQDQS]}};
// Extract the write data mask signal targeting the current DQS group
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t0;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t1;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t2;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t3;
assign phy_ddio_wrdata_mask_t0 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+0*NUM_OF_DQDQS)];
assign phy_ddio_wrdata_mask_t1 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+1*NUM_OF_DQDQS)];
assign phy_ddio_wrdata_mask_t2 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+2*NUM_OF_DQDQS)];
assign phy_ddio_wrdata_mask_t3 = phy_ddio_wrdata_mask [DQDQS_DM_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DM_WIDTH*(i+3*NUM_OF_DQDQS)];
wire pll_capture_clk;
assign pll_capture_clk = pll_capture0_clk_ddio;
ddr3_p0_dqdqs_pads_m10 ubidir_dq_dqs (
.reset_n_afi_clk (reset_n_afi_clk[3]),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk_ddio (pll_mem_clk_ddio),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (pll_write_clk_ddio),
.enable_mem_clk (~afi_mem_clk_disable),
.dq_capture_clk (pll_capture_clk), // calibrated capture clock
.read_capture_clk_hr_dq (read_capture_clk_hr_dq[i]), // to read datapath
.invert_hr_clock (invert_hr_clock),
.phy_mem_dq (mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.mem_dqs (mem_dqs[i]),
.mem_dqs_n (mem_dqs_n[i]),
.extra_write_data_in ({phy_ddio_wrdata_mask_t3, phy_ddio_wrdata_mask_t2, phy_ddio_wrdata_mask_t1, phy_ddio_wrdata_mask_t0}),
.extra_write_data_out (mem_dm[i]),
.rdata_hr (ddio_phy_dq[(DQDQS_DDIO_PHY_DQ_WIDTH*(i+1)-1) : DQDQS_DDIO_PHY_DQ_WIDTH*i]),
.write_oe_in ({phy_ddio_wrdata_en_t1, phy_ddio_wrdata_en_t0}),
.write_data_in ({phy_ddio_dq_t3, phy_ddio_dq_t2, phy_ddio_dq_t1, phy_ddio_dq_t0}),
.output_strobe_ena ({phy_ddio_dqs_en[i+NUM_OF_DQDQS], phy_ddio_dqs_en[i]})
);
defparam ubidir_dq_dqs.MEM_CK_WIDTH = MEM_CK_WIDTH;
end
endgenerate
// ********************************************************************************************************************************
// Instantiate phase detector
// ********************************************************************************************************************************
fiftyfivenm_phase_detector phase_detector_inst
(
.reset (~pd_reset_n),
.phasedone (pd_ack),
.clk ({mimic_clock,pll_capture1_clk,pll_afi_clk}),
.up (pd_up),
.down (pd_down)
);
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule |
module ddr3_p0 (
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
pll_mem_clk,
pll_write_clk,
pll_capture0_clk,
pll_capture1_clk,
pll_locked,
afi_reset_n,
afi_reset_export_n,
afi_clk,
afi_half_clk,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_cal_success,
afi_cal_fail,
afi_wlat,
afi_rlat,
afi_mem_clk_disable,
mem_a,
mem_ba,
mem_ck,
mem_ck_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dq,
mem_dqs,
mem_dqs_n,
mem_reset_n,
mem_odt,
avl_clk,
avl_reset_n,
pd_reset_n,
pd_ack,
pd_up,
pd_down,
phy_clk,
phy_reset_n,
phy_read_latency_counter,
phy_afi_wlat,
phy_afi_rlat,
phy_read_increment_vfifo_fr,
phy_read_increment_vfifo_hr,
phy_read_increment_vfifo_qr,
phy_reset_mem_stable,
phy_write_fr_cycle_shifts,
phy_cal_debug_info,
phy_read_fifo_reset,
phy_vfifo_rd_en_override,
phy_cal_success,
phy_cal_fail,
phy_read_fifo_q,
calib_skip_steps
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver.
parameter DEVICE_FAMILY = "MAX 10";
// choose between abstract (fast) and regular model
`ifndef ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL
`define ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL 0
`endif
parameter ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL = `ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
localparam FAST_SIM_MODEL = ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
// On-chip termination
parameter OCT_TERM_CONTROL_WIDTH = 14;
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec.
parameter MEM_IF_ADDR_WIDTH = 15;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CK_WIDTH = 1;
parameter MEM_IF_CLK_EN_WIDTH = 1;
parameter MEM_IF_CS_WIDTH = 1;
parameter MEM_IF_DM_WIDTH = 2;
parameter MEM_IF_CONTROL_WIDTH = 1;
parameter MEM_IF_DQ_WIDTH = 16;
parameter MEM_IF_DQS_WIDTH = 2;
parameter MEM_IF_READ_DQS_WIDTH = 2;
parameter MEM_IF_WRITE_DQS_WIDTH = 2;
parameter MEM_IF_ODT_WIDTH = 1;
parameter MEM_IF_NUMBER_OF_RANKS = 1;
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations.
// The calculations are done on higher level wrapper.
parameter AFI_ADDR_WIDTH = 30;
parameter AFI_DM_WIDTH = 8;
parameter AFI_BANKADDR_WIDTH = 6;
parameter AFI_CS_WIDTH = 2;
parameter AFI_CLK_EN_WIDTH = 2;
parameter AFI_CONTROL_WIDTH = 2;
parameter AFI_ODT_WIDTH = 2;
parameter AFI_DQ_WIDTH = 64;
parameter AFI_WRITE_DQS_WIDTH = 4;
parameter AFI_RATE_RATIO = 2;
parameter AFI_WLAT_WIDTH = 6;
parameter AFI_RLAT_WIDTH = 6;
parameter AFI_RRANK_WIDTH = 4;
parameter AFI_WRANK_WIDTH = 4;
// DLL Interface
parameter DLL_DELAY_CTRL_WIDTH = 6;
parameter SCC_DATA_WIDTH = 1;
parameter NUM_SUBGROUP_PER_READ_DQS = 1;
parameter QVLD_EXTRA_FLOP_STAGES = 0;
parameter QVLD_WR_ADDRESS_OFFSET = 6;
// Read Datapath parameters, the values should not be changed unless the intention is to change the architecture.
// Read valid prediction FIFO
parameter READ_VALID_FIFO_SIZE = 16;
// Data resynchronization FIFO
parameter READ_FIFO_SIZE = 8;
// Latency calibration parameters
parameter MAX_LATENCY_COUNT_WIDTH = 5; // calibration finds the best latency by reducing the maximum latency
localparam MAX_READ_LATENCY = 2**MAX_LATENCY_COUNT_WIDTH;
// Write Datapath
// The sequencer uses this value to control write latency during calibration
parameter MAX_WRITE_LATENCY_COUNT_WIDTH = 4;
parameter NUM_WRITE_PATH_FLOP_STAGES = 1;
parameter NUM_WRITE_FR_CYCLE_SHIFTS = 0;
// Add additional FF stage between core and periphery
parameter REGISTER_C2P = "false";
// Address/Command Datapath
parameter NUM_AC_FR_CYCLE_SHIFTS = 0;
parameter MR1_ODS = 1;
parameter MR1_RTT = 3;
parameter MR2_RTT_WR = 1;
parameter MEM_T_WL = 6;
localparam MEM_T_RL = 7;
// The sequencer issues back-to-back reads during calibration, NOPs may need to be inserted depending on the burst length
parameter SEQ_BURST_COUNT_WIDTH = 1;
// The DLL offset control width
parameter DLL_OFFSET_CTRL_WIDTH = 6;
parameter MEM_CLK_FREQ = 300.0;
parameter DELAY_BUFFER_MODE = "HIGH";
parameter DQS_DELAY_CHAIN_PHASE_SETTING = 2;
parameter DQS_PHASE_SHIFT = 9000;
parameter DELAYED_CLOCK_PHASE_SETTING = 2;
parameter AFI_DEBUG_INFO_WIDTH = 32;
parameter CALIB_REG_WIDTH = 8;
parameter TB_PROTOCOL = "DDR3";
parameter TB_MEM_CLK_FREQ = "300.0";
parameter TB_RATE = "HALF";
parameter TB_MEM_DQ_WIDTH = "16";
parameter TB_MEM_DQS_WIDTH = "2";
parameter TB_PLL_DLL_MASTER = "true";
parameter FAST_SIM_CALIBRATION = "false";
parameter EXTRA_VFIFO_SHIFT = 0;
localparam SIM_FILESET = ("false" == "true");
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// When the PHY is selected to be a PLL/DLL SLAVE, the PLL and DLL are instantied at the top level of the example design
input pll_mem_clk;
input pll_write_clk;
input pll_capture0_clk;
input pll_capture1_clk;
input pll_locked;
// Reset Interface, AFI 2.0
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
output afi_reset_export_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
// should be used to reset system level afi_clk domain logic
input csr_soft_reset_req; // Reset request (active_high) being driven by external debug master
// OCT termination control signals
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [AFI_ADDR_WIDTH-1:0] afi_addr; // address
input [AFI_BANKADDR_WIDTH-1:0] afi_ba; // bank
input [AFI_CLK_EN_WIDTH-1:0] afi_cke; // clock enable
input [AFI_CS_WIDTH-1:0] afi_cs_n; // chip select
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
// Write data interface
input [AFI_WRITE_DQS_WIDTH-1:0] afi_dqs_burst;
input [AFI_DQ_WIDTH-1:0] afi_wdata; // write data
input [AFI_WRITE_DQS_WIDTH-1:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [AFI_DM_WIDTH-1:0] afi_dm; // write data mask
// Read data interface
output [AFI_DQ_WIDTH-1:0] afi_rdata; // read data
input [AFI_RATE_RATIO-1:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [AFI_RATE_RATIO-1:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [AFI_RATE_RATIO-1:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
output [AFI_WLAT_WIDTH-1:0] afi_wlat;
output [AFI_RLAT_WIDTH-1:0] afi_rlat;
input [MEM_IF_CK_WIDTH-1:0] afi_mem_clk_disable;
// Ping Pong PHY signals
// PHY-Memory Interface
output [MEM_IF_ADDR_WIDTH-1:0] mem_a; // address
output [MEM_IF_BANKADDR_WIDTH-1:0] mem_ba; // bank
inout [MEM_IF_CK_WIDTH-1:0] mem_ck; // differential address and command clock
inout [MEM_IF_CK_WIDTH-1:0] mem_ck_n;
output [MEM_IF_CLK_EN_WIDTH-1:0] mem_cke; // clock enable
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n; // chip select
output [MEM_IF_DM_WIDTH-1:0] mem_dm; // data mask
output [MEM_IF_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_IF_CONTROL_WIDTH-1:0] mem_cas_n;
output [MEM_IF_CONTROL_WIDTH-1:0] mem_we_n;
inout [MEM_IF_DQ_WIDTH-1:0] mem_dq; // bidirectional data bus
inout [MEM_IF_DQS_WIDTH-1:0] mem_dqs; // bidirectional data strobe
inout [MEM_IF_DQS_WIDTH-1:0] mem_dqs_n; // differential bidirectional data strobe
output [MEM_IF_ODT_WIDTH-1:0] mem_odt;
output mem_reset_n;
// PLL Interface
input afi_clk;
input afi_half_clk;
output avl_clk;
output avl_reset_n;
input pd_reset_n;
input pd_ack;
output pd_up;
output pd_down;
output phy_clk;
output phy_reset_n;
input [MAX_LATENCY_COUNT_WIDTH-1:0] phy_read_latency_counter;
input [AFI_WLAT_WIDTH-1:0] phy_afi_wlat;
input [AFI_RLAT_WIDTH-1:0] phy_afi_rlat;
input [MEM_IF_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_fr;
input [MEM_IF_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_hr;
input [MEM_IF_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_qr;
input phy_reset_mem_stable;
input [MEM_IF_WRITE_DQS_WIDTH*2-1:0] phy_write_fr_cycle_shifts;
input [AFI_DEBUG_INFO_WIDTH - 1:0] phy_cal_debug_info;
input [MEM_IF_READ_DQS_WIDTH-1:0] phy_read_fifo_reset;
input [MEM_IF_READ_DQS_WIDTH-1:0] phy_vfifo_rd_en_override;
input phy_cal_success; // calibration success
input phy_cal_fail; // calibration failure
output [AFI_DQ_WIDTH-1:0] phy_read_fifo_q;
output [CALIB_REG_WIDTH-1:0] calib_skip_steps;
// END PORT SECTION
initial $display("Using %0s core emif simulation models", FAST_SIM_MODEL ? "Fast" : "Regular");
assign afi_cal_success = phy_cal_success;
assign afi_cal_fail = phy_cal_fail;
assign avl_clk = afi_clk;
assign avl_reset_n = afi_reset_n;
integer MEM_T_WL_int = (MEM_T_WL/2);
assign afi_wlat = MEM_T_WL_int[AFI_WLAT_WIDTH-1:0];
// Exporting read latency is currently not supported
assign afi_rlat = 0;
ddr3_p0_memphy_m10 #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.MEM_ADDRESS_WIDTH(MEM_IF_ADDR_WIDTH),
.MEM_BANK_WIDTH(MEM_IF_BANKADDR_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_IF_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_IF_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_IF_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_IF_DQS_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_DM_WIDTH(MEM_IF_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_IF_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_IF_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_IF_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_IF_WRITE_DQS_WIDTH),
.AFI_ADDRESS_WIDTH(AFI_ADDR_WIDTH),
.AFI_BANK_WIDTH(AFI_BANKADDR_WIDTH),
.AFI_CHIP_SELECT_WIDTH(AFI_CS_WIDTH),
.AFI_CLK_EN_WIDTH(AFI_CLK_EN_WIDTH),
.AFI_ODT_WIDTH(AFI_ODT_WIDTH),
.AFI_DATA_MASK_WIDTH(AFI_DM_WIDTH),
.AFI_DQS_WIDTH(AFI_WRITE_DQS_WIDTH),
.AFI_CONTROL_WIDTH(AFI_CONTROL_WIDTH),
.AFI_DATA_WIDTH(AFI_DQ_WIDTH),
.AFI_RATE_RATIO(AFI_RATE_RATIO),
.MEM_T_RL(MEM_T_RL),
.MAX_LATENCY_COUNT_WIDTH(MAX_LATENCY_COUNT_WIDTH),
.NUM_WRITE_PATH_FLOP_STAGES(NUM_WRITE_PATH_FLOP_STAGES),
.NUM_WRITE_FR_CYCLE_SHIFTS(NUM_WRITE_FR_CYCLE_SHIFTS),
.NUM_AC_FR_CYCLE_SHIFTS(NUM_AC_FR_CYCLE_SHIFTS),
.CALIB_REG_WIDTH(CALIB_REG_WIDTH),
.AFI_DEBUG_INFO_WIDTH(AFI_DEBUG_INFO_WIDTH)
) umemphy (
.global_reset_n(global_reset_n),
.soft_reset_n(soft_reset_n & ~csr_soft_reset_req),
.ctl_reset_n(afi_reset_n),
.ctl_reset_export_n(afi_reset_export_n),
.pll_locked(pll_locked),
.afi_addr(afi_addr),
.afi_ba(afi_ba),
.afi_cke(afi_cke),
.afi_cs_n(afi_cs_n),
.afi_ras_n(afi_ras_n),
.afi_we_n(afi_we_n),
.afi_cas_n(afi_cas_n),
.afi_rst_n(afi_rst_n),
.afi_mem_clk_disable(afi_mem_clk_disable),
.afi_odt(afi_odt),
.afi_dqs_burst(afi_dqs_burst),
.afi_wdata(afi_wdata),
.afi_wdata_valid(afi_wdata_valid),
.afi_dm(afi_dm),
.afi_rdata(afi_rdata),
.afi_rdata_en(afi_rdata_en),
.afi_rdata_valid(afi_rdata_valid),
.afi_cal_success(afi_cal_success),
.afi_cal_fail(afi_cal_fail),
.mem_a(mem_a),
.mem_ba(mem_ba),
.mem_ck(mem_ck),
.mem_ck_n(mem_ck_n),
.mem_cke(mem_cke),
.mem_cs_n(mem_cs_n),
.mem_dm(mem_dm),
.mem_ras_n(mem_ras_n),
.mem_cas_n(mem_cas_n),
.mem_we_n(mem_we_n),
.mem_reset_n(mem_reset_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqs_n(mem_dqs_n),
.mem_odt(mem_odt),
.pll_afi_clk(afi_clk),
.pll_mem_clk(pll_mem_clk),
.pll_write_clk(pll_write_clk),
.pll_capture0_clk(pll_capture0_clk),
.pll_capture1_clk(pll_capture1_clk),
.phy_read_latency_counter(phy_read_latency_counter),
.phy_read_increment_vfifo_hr(phy_read_increment_vfifo_hr),
.phy_cal_debug_info(phy_cal_debug_info),
.phy_read_fifo_reset(phy_read_fifo_reset),
.phy_vfifo_rd_en_override(phy_vfifo_rd_en_override),
.calib_skip_steps(calib_skip_steps),
.phy_clk(phy_clk),
.phy_reset_n(phy_reset_n),
.pd_reset_n(pd_reset_n),
.pd_ack(pd_ack),
.pd_up(pd_up),
.pd_down(pd_down)
);
endmodule |
module ddr3_s0_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [92-1 : 0] sink0_data,
input [3-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [92-1 : 0] src_data,
output [3-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 92 + 3 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 3;
localparam PKT_TRANS_LOCK = 60;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module alt_mem_if_nextgen_ddr3_controller_core (
afi_clk,
afi_reset_n,
afi_half_clk,
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
afi_rst_n,
afi_cs_n,
afi_cke,
afi_odt,
afi_addr,
afi_ba,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_rdata_en,
afi_rdata_en_full,
afi_rrank,
afi_wrank,
afi_rdata,
afi_rdata_valid,
afi_rlat,
afi_cal_success,
afi_cal_fail,
afi_cal_req,
afi_init_req,
afi_mem_clk_disable,
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
local_refresh_ack,
local_powerdn_ack,
local_self_rfsh_ack,
local_deep_powerdn_ack,
local_refresh_req,
local_refresh_chip,
local_self_rfsh_req,
local_self_rfsh_chip,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_zqcal_req,
local_zqcal_chip,
local_multicast,
local_priority,
local_init_done,
local_cal_success,
local_cal_fail,
ecc_interrupt,
csr_read_req,
csr_write_req,
csr_addr,
csr_wdata,
csr_rdata,
csr_be,
csr_rdata_valid,
csr_waitrequest,
tbp_empty,
cmd_gen_busy,
sideband_in_refresh
);
parameter AVL_SIZE_WIDTH = 0;
parameter AVL_ADDR_WIDTH = 0;
parameter AVL_DATA_WIDTH = 0;
parameter LOCAL_ID_WIDTH = 0;
parameter AVL_BE_WIDTH = 0;
parameter LOCAL_CS_WIDTH = 0;
parameter MEM_IF_ADDR_WIDTH = 0;
parameter MEM_IF_CLK_PAIR_COUNT = 0;
parameter LOCAL_IF_TYPE = "AVALON";
parameter DWIDTH_RATIO = 0;
parameter CTL_ODT_ENABLED = 0;
parameter CTL_OUTPUT_REGD = 0;
parameter CTL_TBP_NUM = 0;
parameter WRBUFFER_ADDR_WIDTH = 0;
parameter RDBUFFER_ADDR_WIDTH = 0;
parameter MAX_PENDING_RD_CMD = 0;
parameter MAX_PENDING_WR_CMD = 0;
parameter MEM_IF_CS_WIDTH = 0;
parameter MEM_IF_CHIP_BITS = 0;
parameter MEM_IF_BANKADDR_WIDTH = 0;
parameter MEM_IF_ROW_ADDR_WIDTH = 0;
parameter MEM_IF_COL_ADDR_WIDTH = 0;
parameter MEM_IF_ODT_WIDTH = 0;
parameter MEM_IF_CLK_EN_WIDTH = 0;
parameter MEM_IF_DQS_WIDTH = 0;
parameter MEM_IF_DQ_WIDTH = 0;
parameter MEM_IF_DM_WIDTH = 0;
parameter MAX_MEM_IF_CS_WIDTH = 30;
parameter MAX_MEM_IF_CHIP = 4;
parameter MAX_MEM_IF_BANKADDR_WIDTH = 3;
parameter MAX_MEM_IF_ROWADDR_WIDTH = 16;
parameter MAX_MEM_IF_COLADDR_WIDTH = 12;
parameter MAX_MEM_IF_ODT_WIDTH = 1;
parameter MAX_MEM_IF_DQS_WIDTH = 5;
parameter MAX_MEM_IF_DQ_WIDTH = 40;
parameter MAX_MEM_IF_MASK_WIDTH = 5;
parameter MAX_LOCAL_DATA_WIDTH = 80;
parameter CFG_TYPE = 0;
parameter CFG_INTERFACE_WIDTH = 0;
parameter CFG_BURST_LENGTH = 0;
parameter CFG_REORDER_DATA = 0;
parameter CFG_DATA_REORDERING_TYPE = "INTER_ROW";
parameter CFG_STARVE_LIMIT = 0;
parameter CFG_ADDR_ORDER = 0;
parameter MEM_WTCL_INT = 0;
parameter MEM_ADD_LAT = 0;
parameter MEM_TCL = 0;
parameter MEM_TRRD = 0;
parameter MEM_TFAW = 0;
parameter MEM_TRFC = 0;
parameter MEM_TREFI = 0;
parameter MEM_TRCD = 0;
parameter MEM_TRP = 0;
parameter MEM_TWR = 0;
parameter MEM_TWTR = 0;
parameter MEM_TRTP = 0;
parameter MEM_TRAS = 0;
parameter MEM_TRC = 0;
parameter CFG_TCCD = 2;
parameter MEM_AUTO_PD_CYCLES = 0;
parameter MEM_IF_RD_TO_WR_TURNAROUND_OCT = 0;
parameter MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0;
parameter CTL_RD_TO_PCH_EXTRA_CLK = 0;
parameter CTL_RD_TO_RD_EXTRA_CLK = 0;
parameter CTL_WR_TO_WR_EXTRA_CLK = 0;
parameter CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK = 0;
parameter CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK = 0;
parameter AFI_ADDR_WIDTH = 0;
parameter AFI_BANKADDR_WIDTH = 0;
parameter AFI_CONTROL_WIDTH = 0;
parameter AFI_CS_WIDTH = 0;
parameter AFI_CLK_EN_WIDTH = 0;
parameter AFI_ODT_WIDTH = 0;
parameter AFI_DM_WIDTH = 0;
parameter AFI_DQ_WIDTH = 0;
parameter AFI_WRITE_DQS_WIDTH = 0;
parameter AFI_RATE_RATIO = 0;
parameter AFI_WLAT_WIDTH = 0;
parameter AFI_RLAT_WIDTH = 0;
parameter AFI_RRANK_WIDTH = 0;
parameter AFI_WRANK_WIDTH = 0;
parameter USE_SHADOW_REGS = 0;
parameter CFG_SELF_RFSH_EXIT_CYCLES = 0;
parameter CFG_PDN_EXIT_CYCLES = 0;
parameter CFG_POWER_SAVING_EXIT_CYCLES = 0;
parameter CFG_MEM_CLK_ENTRY_CYCLES = 0;
parameter MEM_TMRD_CK = 0;
parameter CTL_ECC_ENABLED = 0;
parameter CTL_ECC_AUTO_CORRECTION_ENABLED = 0;
parameter CTL_ECC_MULTIPLES_16_24_40_72 = 1;
parameter CTL_ENABLE_BURST_INTERRUPT_INT = 0;
parameter CTL_ENABLE_BURST_TERMINATE_INT = 0;
parameter CTL_ENABLE_WDATA_PATH_LATENCY = 0;
parameter CFG_GEN_SBE = 0;
parameter CFG_GEN_DBE = 0;
parameter CFG_ENABLE_INTR = 0;
parameter CFG_MASK_SBE_INTR = 0;
parameter CFG_MASK_DBE_INTR = 0;
parameter CFG_MASK_CORRDROP_INTR = 0;
parameter CFG_CLR_INTR = 0;
parameter CTL_USR_REFRESH = 0;
parameter CTL_REGDIMM_ENABLED = 0;
parameter CFG_WRITE_ODT_CHIP = 0;
parameter CFG_READ_ODT_CHIP = 0;
parameter CFG_PORT_WIDTH_WRITE_ODT_CHIP = 0;
parameter CFG_PORT_WIDTH_READ_ODT_CHIP = 0;
parameter MEM_IF_CKE_WIDTH = 0;
parameter CFG_ENABLE_NO_DM = 0;
parameter CSR_BE_WIDTH = 4;
parameter CTL_CSR_ENABLED = 0;
parameter CSR_ADDR_WIDTH = 8;
parameter CSR_DATA_WIDTH = 32;
parameter CFG_ERRCMD_FIFO_REG = 0;
parameter CFG_ECC_DECODER_REG = 0;
parameter CTL_CS_WIDTH = 0;
parameter USE_DQS_TRACKING = 0;
parameter ENABLE_BURST_MERGE = 0;
parameter CONTINUE_AFTER_CAL_FAIL = 0;
parameter MAX10_CFG = 0;
localparam AFI_RDATA_EN_WIDTH = (MEM_IF_DQS_WIDTH * (DWIDTH_RATIO / 2));
input afi_clk;
input afi_reset_n;
input afi_half_clk;
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [AVL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [AVL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
output itf_wr_data_ready;
input itf_wr_data_valid;
input [AVL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [AVL_BE_WIDTH - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
input itf_rd_data_ready;
output itf_rd_data_valid;
output [AVL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
output [AFI_CONTROL_WIDTH - 1 : 0] afi_rst_n;
output [AFI_CS_WIDTH - 1 : 0] afi_cs_n;
output [AFI_CLK_EN_WIDTH - 1 : 0] afi_cke;
output [AFI_ODT_WIDTH - 1 : 0] afi_odt;
output [AFI_ADDR_WIDTH - 1 : 0] afi_addr;
output [AFI_BANKADDR_WIDTH - 1 : 0] afi_ba;
output [AFI_CONTROL_WIDTH - 1 : 0] afi_ras_n;
output [AFI_CONTROL_WIDTH - 1 : 0] afi_cas_n;
output [AFI_CONTROL_WIDTH - 1 : 0] afi_we_n;
output [AFI_WRITE_DQS_WIDTH - 1 : 0] afi_dqs_burst;
output [AFI_WRITE_DQS_WIDTH - 1 : 0] afi_wdata_valid;
output [AFI_DQ_WIDTH - 1 : 0] afi_wdata;
output [AFI_DM_WIDTH - 1 : 0] afi_dm;
input [AFI_WLAT_WIDTH - 1 : 0] afi_wlat;
output [AFI_RATE_RATIO - 1 : 0] afi_rdata_en;
wire [AFI_RDATA_EN_WIDTH - 1 : 0] int_afi_rdata_en;
output [AFI_RATE_RATIO - 1 : 0] afi_rdata_en_full;
wire [AFI_RDATA_EN_WIDTH - 1 : 0] int_afi_rdata_en_full;
output [AFI_RRANK_WIDTH - 1 : 0] afi_rrank;
output [AFI_WRANK_WIDTH - 1 : 0] afi_wrank;
input [AFI_DQ_WIDTH - 1 : 0] afi_rdata;
input [AFI_RATE_RATIO - 1 : 0] afi_rdata_valid;
input [AFI_RLAT_WIDTH - 1 : 0] afi_rlat;
input afi_cal_success;
input afi_cal_fail;
output afi_cal_req;
output afi_init_req;
output [MEM_IF_CLK_PAIR_COUNT - 1 : 0] afi_mem_clk_disable;
wire [(MEM_IF_DQS_WIDTH*CTL_CS_WIDTH) - 1 : 0] afi_cal_byte_lane_sel_n;
output [MEM_IF_CS_WIDTH - 1 : 0] afi_ctl_refresh_done;
input [MEM_IF_CS_WIDTH - 1 : 0] afi_seq_busy;
output [MEM_IF_CS_WIDTH - 1 : 0] afi_ctl_long_idle;
output local_refresh_ack;
output local_powerdn_ack;
output local_self_rfsh_ack;
output local_deep_powerdn_ack;
input local_refresh_req;
input [CTL_CS_WIDTH - 1 : 0] local_refresh_chip;
input local_self_rfsh_req;
input [CTL_CS_WIDTH - 1 : 0] local_self_rfsh_chip;
input local_deep_powerdn_req;
input [CTL_CS_WIDTH - 1 : 0] local_deep_powerdn_chip;
input local_zqcal_req;
input [CTL_CS_WIDTH - 1 : 0] local_zqcal_chip;
input local_multicast;
input local_priority;
output local_init_done;
output local_cal_success;
output local_cal_fail;
output ecc_interrupt;
input csr_read_req;
input csr_write_req;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
input [CSR_BE_WIDTH - 1 : 0] csr_be;
output csr_rdata_valid;
output csr_waitrequest;
output tbp_empty;
output cmd_gen_busy;
output sideband_in_refresh;
alt_mem_ddrx_controller_st_top # (
.LOCAL_SIZE_WIDTH ( AVL_SIZE_WIDTH ),
.LOCAL_ADDR_WIDTH ( AVL_ADDR_WIDTH ),
.LOCAL_DATA_WIDTH ( AVL_DATA_WIDTH ),
.LOCAL_BE_WIDTH ( AVL_BE_WIDTH ),
.LOCAL_ID_WIDTH ( LOCAL_ID_WIDTH ),
.LOCAL_CS_WIDTH ( LOCAL_CS_WIDTH ),
.MEM_IF_ADDR_WIDTH ( MEM_IF_ADDR_WIDTH ),
.MEM_IF_CLK_PAIR_COUNT ( MEM_IF_CLK_PAIR_COUNT ),
.LOCAL_IF_TYPE ( LOCAL_IF_TYPE ),
.DWIDTH_RATIO ( DWIDTH_RATIO ),
.CTL_ODT_ENABLED ( CTL_ODT_ENABLED ),
.CTL_OUTPUT_REGD ( CTL_OUTPUT_REGD ),
.CTL_TBP_NUM ( CTL_TBP_NUM ),
.WRBUFFER_ADDR_WIDTH ( WRBUFFER_ADDR_WIDTH ),
.RDBUFFER_ADDR_WIDTH ( RDBUFFER_ADDR_WIDTH ),
.MAX_PENDING_RD_CMD ( MAX10_CFG ? 16 : MAX_PENDING_RD_CMD ),
.MAX_PENDING_WR_CMD ( MAX10_CFG ? 8 : MAX_PENDING_WR_CMD ),
.MEM_IF_CS_WIDTH ( MEM_IF_CHIP_BITS ),
.MEM_IF_CHIP ( CTL_CS_WIDTH ),
.MEM_IF_BANKADDR_WIDTH ( MEM_IF_BANKADDR_WIDTH ),
.MEM_IF_ROW_WIDTH ( MEM_IF_ROW_ADDR_WIDTH ),
.MEM_IF_COL_WIDTH ( MEM_IF_COL_ADDR_WIDTH ),
.MEM_IF_ODT_WIDTH ( MEM_IF_ODT_WIDTH ),
.MEM_IF_DQS_WIDTH ( MEM_IF_DQS_WIDTH ),
.MEM_IF_DWIDTH ( MEM_IF_DQ_WIDTH ),
.MEM_IF_DM_WIDTH ( MEM_IF_DM_WIDTH ),
.MAX_MEM_IF_CS_WIDTH ( MAX_MEM_IF_CS_WIDTH ),
.MAX_MEM_IF_CHIP ( MAX_MEM_IF_CHIP ),
.MAX_MEM_IF_BANKADDR_WIDTH ( MAX_MEM_IF_BANKADDR_WIDTH ),
.MAX_MEM_IF_ROWADDR_WIDTH ( MAX_MEM_IF_ROWADDR_WIDTH ),
.MAX_MEM_IF_COLADDR_WIDTH ( MAX_MEM_IF_COLADDR_WIDTH ),
.MAX_MEM_IF_ODT_WIDTH ( MAX_MEM_IF_ODT_WIDTH ),
.MAX_MEM_IF_DQS_WIDTH ( MAX_MEM_IF_DQS_WIDTH ),
.MAX_MEM_IF_DQ_WIDTH ( MAX_MEM_IF_DQ_WIDTH ),
.MAX_MEM_IF_MASK_WIDTH ( MAX_MEM_IF_MASK_WIDTH ),
.MAX_LOCAL_DATA_WIDTH ( MAX_LOCAL_DATA_WIDTH ),
.CFG_TYPE ( CFG_TYPE ),
.CFG_INTERFACE_WIDTH ( CFG_INTERFACE_WIDTH ),
.CFG_BURST_LENGTH ( CFG_BURST_LENGTH ),
.CFG_DEVICE_WIDTH ( MEM_IF_DQS_WIDTH ),
.CFG_REORDER_DATA ( CFG_REORDER_DATA ),
.CFG_DATA_REORDERING_TYPE ( CFG_DATA_REORDERING_TYPE ),
.CFG_STARVE_LIMIT ( CFG_STARVE_LIMIT ),
.CFG_ADDR_ORDER ( CFG_ADDR_ORDER ),
.MEM_CAS_WR_LAT ( MEM_WTCL_INT ),
.MEM_ADD_LAT ( MEM_ADD_LAT ),
.MEM_TCL ( MEM_TCL ),
.MEM_TRRD ( MEM_TRRD ),
.MEM_TFAW ( MEM_TFAW ),
.MEM_TRFC ( MEM_TRFC ),
.MEM_TREFI ( MEM_TREFI ),
.MEM_TRCD ( MEM_TRCD ),
.MEM_TRP ( MEM_TRP ),
.MEM_TWR ( MEM_TWR ),
.MEM_TWTR ( MEM_TWTR ),
.MEM_TRTP ( MEM_TRTP ),
.MEM_TRAS ( MEM_TRAS ),
.MEM_TRC ( MEM_TRC ),
.CFG_TCCD ( CFG_TCCD ),
.MEM_AUTO_PD_CYCLES ( MEM_AUTO_PD_CYCLES ),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT ( MEM_IF_RD_TO_WR_TURNAROUND_OCT ),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT ( MEM_IF_WR_TO_RD_TURNAROUND_OCT ),
.CTL_RD_TO_PCH_EXTRA_CLK ( CTL_RD_TO_PCH_EXTRA_CLK ),
.CTL_RD_TO_RD_EXTRA_CLK ( CTL_RD_TO_RD_EXTRA_CLK ),
.CTL_WR_TO_WR_EXTRA_CLK ( CTL_WR_TO_WR_EXTRA_CLK ),
.CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK ( CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK ),
.CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK ( CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK ),
.CFG_SELF_RFSH_EXIT_CYCLES ( CFG_SELF_RFSH_EXIT_CYCLES ),
.CFG_PDN_EXIT_CYCLES ( CFG_PDN_EXIT_CYCLES ),
.CFG_POWER_SAVING_EXIT_CYCLES ( CFG_POWER_SAVING_EXIT_CYCLES ),
.CFG_MEM_CLK_ENTRY_CYCLES ( CFG_MEM_CLK_ENTRY_CYCLES ),
.MEM_TMRD_CK ( MEM_TMRD_CK ),
.CTL_ECC_ENABLED ( CTL_ECC_ENABLED ),
.CTL_ECC_RMW_ENABLED ( CTL_ECC_AUTO_CORRECTION_ENABLED ),
.CTL_ECC_MULTIPLES_16_24_40_72 ( CTL_ECC_MULTIPLES_16_24_40_72 ),
.CTL_ENABLE_BURST_INTERRUPT ( CTL_ENABLE_BURST_INTERRUPT_INT ),
.CTL_ENABLE_BURST_TERMINATE ( CTL_ENABLE_BURST_TERMINATE_INT ),
.CTL_ENABLE_WDATA_PATH_LATENCY ( CTL_ENABLE_WDATA_PATH_LATENCY ),
.ENABLE_BURST_MERGE ( ENABLE_BURST_MERGE ),
.CFG_GEN_SBE ( CFG_GEN_SBE ),
.CFG_GEN_DBE ( CFG_GEN_DBE ),
.CFG_ENABLE_INTR ( CFG_ENABLE_INTR ),
.CFG_MASK_SBE_INTR ( CFG_MASK_SBE_INTR ),
.CFG_MASK_DBE_INTR ( CFG_MASK_DBE_INTR ),
.CFG_MASK_CORRDROP_INTR ( CFG_MASK_CORRDROP_INTR ),
.CFG_CLR_INTR ( CFG_CLR_INTR ),
.CTL_USR_REFRESH ( CTL_USR_REFRESH ),
.CTL_REGDIMM_ENABLED ( CTL_REGDIMM_ENABLED ),
.CFG_WRITE_ODT_CHIP ( CFG_WRITE_ODT_CHIP ),
.CFG_READ_ODT_CHIP ( CFG_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP ( CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP ( CFG_PORT_WIDTH_READ_ODT_CHIP ),
.MEM_IF_CKE_WIDTH ( MEM_IF_CLK_EN_WIDTH ),
.CFG_ENABLE_NO_DM ( CFG_ENABLE_NO_DM ),
.CTL_CSR_ENABLED ( MAX10_CFG ? 0 : CTL_CSR_ENABLED),
.CSR_ADDR_WIDTH ( CSR_ADDR_WIDTH ),
.CSR_DATA_WIDTH ( CSR_DATA_WIDTH ),
.CSR_BE_WIDTH ( CSR_BE_WIDTH ),
.CFG_ENABLE_DQS_TRACKING ( USE_DQS_TRACKING ),
.CFG_WLAT_BUS_WIDTH ( AFI_WLAT_WIDTH ),
.CFG_RLAT_BUS_WIDTH ( AFI_RLAT_WIDTH ),
.CFG_RRANK_BUS_WIDTH ( AFI_RRANK_WIDTH ),
.CFG_WRANK_BUS_WIDTH ( AFI_WRANK_WIDTH ),
.CFG_USE_SHADOW_REGS ( USE_SHADOW_REGS ),
.CFG_ECC_DECODER_REG ( CFG_ECC_DECODER_REG ),
.CFG_ERRCMD_FIFO_REG ( CFG_ERRCMD_FIFO_REG )
) alt_mem_ddrx_controller_top_inst (
.clk ( afi_clk ),
.half_clk ( afi_half_clk ),
.reset_n ( afi_reset_n ),
.itf_cmd_ready ( itf_cmd_ready ),
.itf_cmd_valid ( itf_cmd_valid ),
.itf_cmd ( itf_cmd ),
.itf_cmd_address ( itf_cmd_address ),
.itf_cmd_burstlen ( itf_cmd_burstlen ),
.itf_cmd_id ( itf_cmd_id ),
.itf_cmd_priority ( itf_cmd_priority ),
.itf_cmd_autopercharge ( itf_cmd_autopercharge ),
.itf_cmd_multicast ( itf_cmd_multicast ),
.itf_wr_data_ready ( itf_wr_data_ready ),
.itf_wr_data_valid ( itf_wr_data_valid ),
.itf_wr_data ( itf_wr_data ),
.itf_wr_data_byte_en ( itf_wr_data_byte_en ),
.itf_wr_data_begin ( itf_wr_data_begin ),
.itf_wr_data_last ( itf_wr_data_last ),
.itf_wr_data_id ( itf_wr_data_id ),
.itf_rd_data_ready ( itf_rd_data_ready ),
.itf_rd_data_valid ( itf_rd_data_valid ),
.itf_rd_data ( itf_rd_data ),
.itf_rd_data_error ( itf_rd_data_error ),
.itf_rd_data_begin ( itf_rd_data_begin ),
.itf_rd_data_last ( itf_rd_data_last ),
.itf_rd_data_id ( itf_rd_data_id ),
.afi_rst_n ( afi_rst_n ),
.afi_cs_n ( afi_cs_n ),
.afi_cke ( afi_cke ),
.afi_odt ( afi_odt ),
.afi_addr ( afi_addr ),
.afi_ba ( afi_ba ),
.afi_ras_n ( afi_ras_n ),
.afi_cas_n ( afi_cas_n ),
.afi_we_n ( afi_we_n ),
.afi_dqs_burst ( afi_dqs_burst ),
.afi_wdata_valid ( afi_wdata_valid ),
.afi_wdata ( afi_wdata ),
.afi_dm ( afi_dm ),
.afi_wlat ( afi_wlat ),
.afi_rdata_en ( int_afi_rdata_en ),
.afi_rdata_en_full ( int_afi_rdata_en_full ),
.afi_rrank ( afi_rrank ),
.afi_wrank ( afi_wrank ),
.afi_rdata ( afi_rdata ),
.afi_rdata_valid ( afi_rdata_valid ),
.afi_rlat ( afi_rlat ),
.afi_cal_success ( CONTINUE_AFTER_CAL_FAIL ? (afi_cal_success | afi_cal_fail) : afi_cal_success ),
.afi_cal_fail ( CONTINUE_AFTER_CAL_FAIL ? 1'b0 : afi_cal_fail ),
.afi_cal_req ( afi_cal_req ),
.afi_init_req ( afi_init_req ),
.afi_mem_clk_disable ( afi_mem_clk_disable ),
.afi_cal_byte_lane_sel_n ( afi_cal_byte_lane_sel_n ),
.afi_ctl_refresh_done ( afi_ctl_refresh_done ),
.afi_seq_busy ( afi_seq_busy ),
.afi_ctl_long_idle ( afi_ctl_long_idle ),
.local_init_done ( local_init_done ),
.local_refresh_ack ( local_refresh_ack ),
.local_powerdn_ack ( local_powerdn_ack ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.local_deep_powerdn_ack ( local_deep_powerdn_ack ),
.local_refresh_req ( local_refresh_req ),
.local_refresh_chip ( local_refresh_chip ),
.local_powerdn_req ( ),
.local_self_rfsh_req ( local_self_rfsh_req ),
.local_self_rfsh_chip ( local_self_rfsh_chip ),
.local_deep_powerdn_req ( local_deep_powerdn_req ),
.local_deep_powerdn_chip ( local_deep_powerdn_chip ),
.local_zqcal_req ( local_zqcal_req ),
.local_zqcal_chip ( local_zqcal_chip ),
.local_multicast ( local_multicast ),
.local_priority ( local_priority ),
.ecc_interrupt ( ecc_interrupt ),
.csr_read_req ( csr_read_req ),
.csr_write_req ( csr_write_req ),
.csr_burst_count ( 1'b1 ),
.csr_beginbursttransfer ( ),
.csr_addr ( csr_addr ),
.csr_wdata ( csr_wdata ),
.csr_rdata ( csr_rdata ),
.csr_be ( csr_be ),
.csr_rdata_valid ( csr_rdata_valid ),
.csr_waitrequest ( csr_waitrequest ),
.tbp_empty ( tbp_empty ),
.cmd_gen_busy ( cmd_gen_busy ),
.sideband_in_refresh ( sideband_in_refresh )
);
assign afi_rdata_en = int_afi_rdata_en[AFI_RATE_RATIO-1:0];
assign afi_rdata_en_full = int_afi_rdata_en_full[AFI_RATE_RATIO-1:0];
assign local_cal_success = afi_cal_success;
assign local_cal_fail = afi_cal_fail;
endmodule |
module ddr3_s0_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [78 - 77 : 0] default_destination_id,
output [3-1 : 0] default_wr_channel,
output [3-1 : 0] default_rd_channel,
output [3-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[78 - 77 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 3'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 3'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 3'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module ddr3_s0_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [92-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [92-1 : 0] src_data,
output reg [3-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 55;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 77;
localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 3;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 58;
localparam PKT_TRANS_READ = 59;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h50000 - 64'h48000);
localparam PAD1 = log2ceil(64'h58000 - 64'h50000);
localparam PAD2 = log2ceil(64'h60000 - 64'h58000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h60000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [3-1 : 0] default_src_channel;
ddr3_s0_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x48000 .. 0x50000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h48000 ) begin
src_channel = 3'b001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x50000 .. 0x58000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h50000 ) begin
src_channel = 3'b010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x58000 .. 0x60000 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h58000 ) begin
src_channel = 3'b100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module ddr3_pll0 (
global_reset_n,
pll_ref_clk,
pll_locked,
afi_clk,
afi_half_clk,
pll_mem_clk,
pll_write_clk,
pll_capture0_clk,
pll_capture1_clk,
scanclk,
phasecounterselect,
phasestep,
phaseupdown,
phasedone
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver.
parameter DEVICE_FAMILY = "MAX 10";
// Clock settings
parameter REF_CLK_PERIOD_PS = 20000;
parameter PLL_AFI_CLK_DIV = 1;
parameter PLL_MEM_CLK_DIV = 1;
parameter PLL_WRITE_CLK_DIV = 1;
parameter PLL_CAP0_CLK_DIV = 1;
parameter PLL_CAP1_CLK_DIV = 1;
parameter PLL_AFI_CLK_MULT = 3;
parameter PLL_MEM_CLK_MULT = 6;
parameter PLL_WRITE_CLK_MULT = 6;
parameter PLL_CAP0_CLK_MULT = 6;
parameter PLL_CAP1_CLK_MULT = 6;
parameter PLL_AFI_CLK_PHASE_PS = "0";
parameter PLL_MEM_CLK_PHASE_PS = "0";
parameter PLL_WRITE_CLK_PHASE_PS = "2500";
parameter PLL_CAP0_CLK_PHASE_PS = "0";
parameter PLL_CAP1_CLK_PHASE_PS = "2500";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input pll_ref_clk; // PLL reference clock
output pll_locked; // When 0, PLL is out of lock
// When the PHY is selected to be a PLL/DLL MASTER, the PLL and DLL are instantied on this top level
output afi_clk; // See pll_memphy instantiation below for detailed description of each clock
output afi_half_clk;
output pll_mem_clk;
output pll_write_clk;
output pll_capture0_clk;
output pll_capture1_clk;
input [2:0] phasecounterselect;
input phasestep;
input phaseupdown;
output phasedone;
input scanclk;
assign afi_half_clk = 1'b0;
// END PORT SECTION
// ********************************************************************************************************************************
wire [4:0] sub_wire;
wire afi_clk = sub_wire[4];
wire pll_mem_clk = sub_wire[0];
wire pll_write_clk = sub_wire[1];
wire pll_capture0_clk = sub_wire[2];
wire pll_capture1_clk = sub_wire[3];
altpll upll_memphy (
.areset (~global_reset_n),
.inclk ({1'h0, pll_ref_clk}),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.scanclk (scanclk),
.phaseupdown (phaseupdown),
.clk (sub_wire),
.locked (pll_locked),
.phasedone (phasedone),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
upll_memphy.bandwidth_type = "AUTO",
upll_memphy.clk4_divide_by = PLL_AFI_CLK_DIV,
upll_memphy.clk4_duty_cycle = 50,
upll_memphy.clk4_multiply_by = PLL_AFI_CLK_MULT,
upll_memphy.clk4_phase_shift = PLL_AFI_CLK_PHASE_PS,
upll_memphy.clk0_divide_by = PLL_MEM_CLK_DIV,
upll_memphy.clk0_duty_cycle = 50,
upll_memphy.clk0_multiply_by = PLL_MEM_CLK_MULT,
upll_memphy.clk0_phase_shift = PLL_MEM_CLK_PHASE_PS,
upll_memphy.clk1_divide_by = PLL_WRITE_CLK_DIV,
upll_memphy.clk1_duty_cycle = 50,
upll_memphy.clk1_multiply_by = PLL_WRITE_CLK_MULT,
upll_memphy.clk1_phase_shift = PLL_WRITE_CLK_PHASE_PS,
upll_memphy.clk2_divide_by = PLL_CAP0_CLK_DIV,
upll_memphy.clk2_duty_cycle = 50,
upll_memphy.clk2_multiply_by = PLL_CAP0_CLK_MULT,
upll_memphy.clk2_phase_shift = PLL_CAP0_CLK_PHASE_PS,
upll_memphy.clk3_divide_by = PLL_CAP1_CLK_DIV,
upll_memphy.clk3_duty_cycle = 50,
upll_memphy.clk3_multiply_by = PLL_CAP1_CLK_MULT,
upll_memphy.clk3_phase_shift = PLL_CAP1_CLK_PHASE_PS,
upll_memphy.compensate_clock = "CLK1",
upll_memphy.inclk0_input_frequency = REF_CLK_PERIOD_PS,
upll_memphy.intended_device_family = DEVICE_FAMILY,
upll_memphy.lpm_type = "altpll",
upll_memphy.operation_mode = "NORMAL",
upll_memphy.pll_type = "AUTO",
upll_memphy.port_activeclock = "PORT_UNUSED",
upll_memphy.port_areset = "PORT_USED",
upll_memphy.port_clkbad0 = "PORT_UNUSED",
upll_memphy.port_clkbad1 = "PORT_UNUSED",
upll_memphy.port_clkloss = "PORT_UNUSED",
upll_memphy.port_clkswitch = "PORT_UNUSED",
upll_memphy.port_configupdate = "PORT_UNUSED",
upll_memphy.port_fbin = "PORT_UNUSED",
upll_memphy.port_inclk0 = "PORT_USED",
upll_memphy.port_inclk1 = "PORT_UNUSED",
upll_memphy.port_locked = "PORT_USED",
upll_memphy.port_pfdena = "PORT_UNUSED",
upll_memphy.port_phasecounterselect = "PORT_USED",
upll_memphy.port_phasedone = "PORT_USED",
upll_memphy.port_phasestep = "PORT_USED",
upll_memphy.port_phaseupdown = "PORT_USED",
upll_memphy.port_pllena = "PORT_UNUSED",
upll_memphy.port_scanaclr = "PORT_UNUSED",
upll_memphy.port_scanclk = "PORT_USED",
upll_memphy.port_scanclkena = "PORT_UNUSED",
upll_memphy.port_scandata = "PORT_UNUSED",
upll_memphy.port_scandataout = "PORT_UNUSED",
upll_memphy.port_scandone = "PORT_UNUSED",
upll_memphy.port_scanread = "PORT_UNUSED",
upll_memphy.port_scanwrite = "PORT_UNUSED",
upll_memphy.port_clk0 = "PORT_USED",
upll_memphy.port_clk1 = "PORT_USED",
upll_memphy.port_clk2 = "PORT_USED",
upll_memphy.port_clk3 = "PORT_USED",
upll_memphy.port_clk4 = "PORT_USED",
upll_memphy.port_clk5 = "PORT_UNUSED",
upll_memphy.port_clkena0 = "PORT_UNUSED",
upll_memphy.port_clkena1 = "PORT_UNUSED",
upll_memphy.port_clkena2 = "PORT_UNUSED",
upll_memphy.port_clkena3 = "PORT_UNUSED",
upll_memphy.port_clkena4 = "PORT_UNUSED",
upll_memphy.port_clkena5 = "PORT_UNUSED",
upll_memphy.port_extclk0 = "PORT_UNUSED",
upll_memphy.port_extclk1 = "PORT_UNUSED",
upll_memphy.port_extclk2 = "PORT_UNUSED",
upll_memphy.port_extclk3 = "PORT_UNUSED",
upll_memphy.self_reset_on_loss_lock = "OFF",
upll_memphy.vco_frequency_control = "MANUAL_PHASE",
upll_memphy.vco_phase_shift_step = 104,
upll_memphy.width_clock = 5,
upll_memphy.width_phasecounterselect = 3;
endmodule |
module axi_slice
#(
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_DATA_WIDTH = 64,
parameter AXI_USER_WIDTH = 6,
parameter AXI_ID_WIDTH = 3,
parameter SLICE_DEPTH = 2,
parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8
)
(
input logic clk_i,
input logic rst_ni,
input logic test_en_i,
// AXI4 SLAVE
//***************************************
// WRITE ADDRESS CHANNEL
input logic axi_slave_aw_valid_i,
input logic [AXI_ADDR_WIDTH-1:0] axi_slave_aw_addr_i,
input logic [2:0] axi_slave_aw_prot_i,
input logic [3:0] axi_slave_aw_region_i,
input logic [7:0] axi_slave_aw_len_i,
input logic [2:0] axi_slave_aw_size_i,
input logic [1:0] axi_slave_aw_burst_i,
input logic axi_slave_aw_lock_i,
input logic [3:0] axi_slave_aw_cache_i,
input logic [3:0] axi_slave_aw_qos_i,
input logic [AXI_ID_WIDTH-1:0] axi_slave_aw_id_i,
input logic [AXI_USER_WIDTH-1:0] axi_slave_aw_user_i,
output logic axi_slave_aw_ready_o,
// READ ADDRESS CHANNEL
input logic axi_slave_ar_valid_i,
input logic [AXI_ADDR_WIDTH-1:0] axi_slave_ar_addr_i,
input logic [2:0] axi_slave_ar_prot_i,
input logic [3:0] axi_slave_ar_region_i,
input logic [7:0] axi_slave_ar_len_i,
input logic [2:0] axi_slave_ar_size_i,
input logic [1:0] axi_slave_ar_burst_i,
input logic axi_slave_ar_lock_i,
input logic [3:0] axi_slave_ar_cache_i,
input logic [3:0] axi_slave_ar_qos_i,
input logic [AXI_ID_WIDTH-1:0] axi_slave_ar_id_i,
input logic [AXI_USER_WIDTH-1:0] axi_slave_ar_user_i,
output logic axi_slave_ar_ready_o,
// WRITE DATA CHANNEL
input logic axi_slave_w_valid_i,
input logic [AXI_DATA_WIDTH-1:0] axi_slave_w_data_i,
input logic [AXI_STRB_WIDTH-1:0] axi_slave_w_strb_i,
input logic [AXI_USER_WIDTH-1:0] axi_slave_w_user_i,
input logic axi_slave_w_last_i,
output logic axi_slave_w_ready_o,
// READ DATA CHANNEL
output logic axi_slave_r_valid_o,
output logic [AXI_DATA_WIDTH-1:0] axi_slave_r_data_o,
output logic [1:0] axi_slave_r_resp_o,
output logic axi_slave_r_last_o,
output logic [AXI_ID_WIDTH-1:0] axi_slave_r_id_o,
output logic [AXI_USER_WIDTH-1:0] axi_slave_r_user_o,
input logic axi_slave_r_ready_i,
// WRITE RESPONSE CHANNEL
output logic axi_slave_b_valid_o,
output logic [1:0] axi_slave_b_resp_o,
output logic [AXI_ID_WIDTH-1:0] axi_slave_b_id_o,
output logic [AXI_USER_WIDTH-1:0] axi_slave_b_user_o,
input logic axi_slave_b_ready_i,
// AXI4 MASTER
//***************************************
// WRITE ADDRESS CHANNEL
output logic axi_master_aw_valid_o,
output logic [AXI_ADDR_WIDTH-1:0] axi_master_aw_addr_o,
output logic [2:0] axi_master_aw_prot_o,
output logic [3:0] axi_master_aw_region_o,
output logic [7:0] axi_master_aw_len_o,
output logic [2:0] axi_master_aw_size_o,
output logic [1:0] axi_master_aw_burst_o,
output logic axi_master_aw_lock_o,
output logic [3:0] axi_master_aw_cache_o,
output logic [3:0] axi_master_aw_qos_o,
output logic [AXI_ID_WIDTH-1:0] axi_master_aw_id_o,
output logic [AXI_USER_WIDTH-1:0] axi_master_aw_user_o,
input logic axi_master_aw_ready_i,
// READ ADDRESS CHANNEL
output logic axi_master_ar_valid_o,
output logic [AXI_ADDR_WIDTH-1:0] axi_master_ar_addr_o,
output logic [2:0] axi_master_ar_prot_o,
output logic [3:0] axi_master_ar_region_o,
output logic [7:0] axi_master_ar_len_o,
output logic [2:0] axi_master_ar_size_o,
output logic [1:0] axi_master_ar_burst_o,
output logic axi_master_ar_lock_o,
output logic [3:0] axi_master_ar_cache_o,
output logic [3:0] axi_master_ar_qos_o,
output logic [AXI_ID_WIDTH-1:0] axi_master_ar_id_o,
output logic [AXI_USER_WIDTH-1:0] axi_master_ar_user_o,
input logic axi_master_ar_ready_i,
// WRITE DATA CHANNEL
output logic axi_master_w_valid_o,
output logic [AXI_DATA_WIDTH-1:0] axi_master_w_data_o,
output logic [AXI_STRB_WIDTH-1:0] axi_master_w_strb_o,
output logic [AXI_USER_WIDTH-1:0] axi_master_w_user_o,
output logic axi_master_w_last_o,
input logic axi_master_w_ready_i,
// READ DATA CHANNEL
input logic axi_master_r_valid_i,
input logic [AXI_DATA_WIDTH-1:0] axi_master_r_data_i,
input logic [1:0] axi_master_r_resp_i,
input logic axi_master_r_last_i,
input logic [AXI_ID_WIDTH-1:0] axi_master_r_id_i,
input logic [AXI_USER_WIDTH-1:0] axi_master_r_user_i,
output logic axi_master_r_ready_o,
// WRITE RESPONSE CHANNEL
input logic axi_master_b_valid_i,
input logic [1:0] axi_master_b_resp_i,
input logic [AXI_ID_WIDTH-1:0] axi_master_b_id_i,
input logic [AXI_USER_WIDTH-1:0] axi_master_b_user_i,
output logic axi_master_b_ready_o
);
// AXI WRITE ADDRESS CHANNEL BUFFER
axi_aw_buffer
#(
.ID_WIDTH (AXI_ID_WIDTH),
.ADDR_WIDTH (AXI_ADDR_WIDTH),
.USER_WIDTH (AXI_USER_WIDTH),
.BUFFER_DEPTH (SLICE_DEPTH)
)
aw_buffer_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.test_en_i ( test_en_i ),
.slave_valid_i ( axi_slave_aw_valid_i ),
.slave_addr_i ( axi_slave_aw_addr_i ),
.slave_prot_i ( axi_slave_aw_prot_i ),
.slave_region_i ( axi_slave_aw_region_i ),
.slave_len_i ( axi_slave_aw_len_i ),
.slave_size_i ( axi_slave_aw_size_i ),
.slave_burst_i ( axi_slave_aw_burst_i ),
.slave_lock_i ( axi_slave_aw_lock_i ),
.slave_cache_i ( axi_slave_aw_cache_i ),
.slave_qos_i ( axi_slave_aw_qos_i ),
.slave_id_i ( axi_slave_aw_id_i ),
.slave_user_i ( axi_slave_aw_user_i ),
.slave_ready_o ( axi_slave_aw_ready_o ),
.master_valid_o ( axi_master_aw_valid_o ),
.master_addr_o ( axi_master_aw_addr_o ),
.master_prot_o ( axi_master_aw_prot_o ),
.master_region_o ( axi_master_aw_region_o ),
.master_len_o ( axi_master_aw_len_o ),
.master_size_o ( axi_master_aw_size_o ),
.master_burst_o ( axi_master_aw_burst_o ),
.master_lock_o ( axi_master_aw_lock_o ),
.master_cache_o ( axi_master_aw_cache_o ),
.master_qos_o ( axi_master_aw_qos_o ),
.master_id_o ( axi_master_aw_id_o ),
.master_user_o ( axi_master_aw_user_o ),
.master_ready_i ( axi_master_aw_ready_i )
);
// AXI READ ADDRESS CHANNEL BUFFER
axi_ar_buffer
#(
.ID_WIDTH (AXI_ID_WIDTH),
.ADDR_WIDTH (AXI_ADDR_WIDTH),
.USER_WIDTH (AXI_USER_WIDTH),
.BUFFER_DEPTH (SLICE_DEPTH)
)
ar_buffer_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.test_en_i ( test_en_i ),
.slave_valid_i ( axi_slave_ar_valid_i ),
.slave_addr_i ( axi_slave_ar_addr_i ),
.slave_prot_i ( axi_slave_ar_prot_i ),
.slave_region_i ( axi_slave_ar_region_i ),
.slave_len_i ( axi_slave_ar_len_i ),
.slave_size_i ( axi_slave_ar_size_i ),
.slave_burst_i ( axi_slave_ar_burst_i ),
.slave_lock_i ( axi_slave_ar_lock_i ),
.slave_cache_i ( axi_slave_ar_cache_i ),
.slave_qos_i ( axi_slave_ar_qos_i ),
.slave_id_i ( axi_slave_ar_id_i ),
.slave_user_i ( axi_slave_ar_user_i ),
.slave_ready_o ( axi_slave_ar_ready_o ),
.master_valid_o ( axi_master_ar_valid_o ),
.master_addr_o ( axi_master_ar_addr_o ),
.master_prot_o ( axi_master_ar_prot_o ),
.master_region_o ( axi_master_ar_region_o ),
.master_len_o ( axi_master_ar_len_o ),
.master_size_o ( axi_master_ar_size_o ),
.master_burst_o ( axi_master_ar_burst_o ),
.master_lock_o ( axi_master_ar_lock_o ),
.master_cache_o ( axi_master_ar_cache_o ),
.master_qos_o ( axi_master_ar_qos_o ),
.master_id_o ( axi_master_ar_id_o ),
.master_user_o ( axi_master_ar_user_o ),
.master_ready_i ( axi_master_ar_ready_i )
);
// WRITE DATA CHANNEL BUFFER
axi_w_buffer
#(
.DATA_WIDTH (AXI_DATA_WIDTH),
.USER_WIDTH (AXI_USER_WIDTH),
.BUFFER_DEPTH (SLICE_DEPTH)
)
w_buffer_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.test_en_i ( test_en_i ),
.slave_valid_i ( axi_slave_w_valid_i ),
.slave_data_i ( axi_slave_w_data_i ),
.slave_strb_i ( axi_slave_w_strb_i ),
.slave_user_i ( axi_slave_w_user_i ),
.slave_last_i ( axi_slave_w_last_i ),
.slave_ready_o ( axi_slave_w_ready_o ),
.master_valid_o ( axi_master_w_valid_o ),
.master_data_o ( axi_master_w_data_o ),
.master_strb_o ( axi_master_w_strb_o ),
.master_user_o ( axi_master_w_user_o ),
.master_last_o ( axi_master_w_last_o ),
.master_ready_i ( axi_master_w_ready_i )
);
// READ DATA CHANNEL BUFFER
axi_r_buffer
#(
.ID_WIDTH (AXI_ID_WIDTH),
.DATA_WIDTH (AXI_DATA_WIDTH),
.USER_WIDTH (AXI_USER_WIDTH),
.BUFFER_DEPTH (SLICE_DEPTH)
)
r_buffer_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.test_en_i ( test_en_i ),
.slave_valid_i ( axi_master_r_valid_i ),
.slave_data_i ( axi_master_r_data_i ),
.slave_resp_i ( axi_master_r_resp_i ),
.slave_user_i ( axi_master_r_user_i ),
.slave_id_i ( axi_master_r_id_i ),
.slave_last_i ( axi_master_r_last_i ),
.slave_ready_o ( axi_master_r_ready_o ),
.master_valid_o ( axi_slave_r_valid_o ),
.master_data_o ( axi_slave_r_data_o ),
.master_resp_o ( axi_slave_r_resp_o ),
.master_user_o ( axi_slave_r_user_o ),
.master_id_o ( axi_slave_r_id_o ),
.master_last_o ( axi_slave_r_last_o ),
.master_ready_i ( axi_slave_r_ready_i )
);
// WRITE RESPONSE CHANNEL BUFFER
axi_b_buffer
#(
.ID_WIDTH (AXI_ID_WIDTH),
.USER_WIDTH (AXI_USER_WIDTH),
.BUFFER_DEPTH (SLICE_DEPTH)
)
b_buffer_i
(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.test_en_i ( test_en_i ),
.slave_valid_i ( axi_master_b_valid_i ),
.slave_resp_i ( axi_master_b_resp_i ),
.slave_id_i ( axi_master_b_id_i ),
.slave_user_i ( axi_master_b_user_i ),
.slave_ready_o ( axi_master_b_ready_o ),
.master_valid_o ( axi_slave_b_valid_o ),
.master_resp_o ( axi_slave_b_resp_o ),
.master_id_o ( axi_slave_b_id_o ),
.master_user_o ( axi_slave_b_user_o ),
.master_ready_i ( axi_slave_b_ready_i )
);
endmodule |
module synth_bench (
input logic clk_i,
input logic rst_ni,
input logic src_rst_ni,
input logic src_clk_i,
input logic [31:0] src_data_i,
input logic src_valid_i,
output logic src_ready_o,
input logic dst_rst_ni,
input logic dst_clk_i,
output logic [31:0] dst_data_o,
output logic dst_valid_o,
input logic dst_ready_i
);
cdc_2phase_synth i_cdc_2phase (
.src_rst_ni (src_rst_ni),
.src_clk_i (src_clk_i),
.src_data_i (src_data_i),
.src_valid_i (src_valid_i),
.src_ready_o (src_ready_o),
.dst_rst_ni (dst_rst_ni),
.dst_clk_i (dst_clk_i),
.dst_data_o (dst_data_o),
.dst_valid_o (dst_valid_o),
.dst_ready_i (dst_ready_i)
);
id_queue_synth i_id_queue (
.clk_i (clk_i),
.rst_ni (rst_ni)
);
stream_arbiter_synth i_stream_arbiter (
.clk_i,
.rst_ni
);
ecc_synth i_ecc ();
endmodule |
module unread (
input logic d_i
);
endmodule |
module edge_propagator_rx (
input logic clk_i,
input logic rstn_i,
input logic valid_i,
output logic ack_o,
output logic valid_o
);
pulp_sync_wedge i_sync_clkb (
.clk_i ( clk_i ),
.rstn_i ( rstn_i ),
.en_i ( 1'b1 ),
.serial_i ( valid_i ),
.r_edge_o ( valid_o ),
.f_edge_o ( ),
.serial_o ( ack_o )
);
endmodule |
module edge_detect (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic d_i, // data stream in
output logic re_o, // rising edge detected
output logic fe_o // falling edge detected
);
sync_wedge i_sync_wedge (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.en_i ( 1'b1 ),
.serial_i ( d_i ),
.r_edge_o ( re_o ),
.f_edge_o ( fe_o ),
.serial_o ( )
);
endmodule |
module rstgen (
input logic clk_i,
input logic rst_ni,
input logic test_mode_i,
output logic rst_no,
output logic init_no
);
rstgen_bypass i_rstgen_bypass (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.rst_test_mode_ni ( rst_ni ),
.test_mode_i ( test_mode_i ),
.rst_no ( rst_no ),
.init_no ( init_no )
);
endmodule |
module reg_mux #(
parameter int unsigned NoPorts = 32'd0,
parameter int unsigned AW = 0,
parameter int unsigned DW = 0,
parameter type req_t = logic,
parameter type rsp_t = logic
) (
input logic clk_i,
input logic rst_ni,
input req_t [NoPorts-1:0] in_req_i,
output rsp_t [NoPorts-1:0] in_rsp_o,
output req_t out_req_o,
input rsp_t out_rsp_i
);
logic [NoPorts-1:0] in_valid, in_ready;
`REG_BUS_TYPEDEF_REQ(req_payload_t, logic [AW-1:0], logic [DW-1:0], logic [DW/8-1:0])
req_payload_t [NoPorts-1:0] in_payload;
req_payload_t out_payload;
for (genvar i = 0; i < NoPorts; i++) begin : gen_unpack
// Request
assign in_valid[i] = in_req_i[i].valid;
assign in_payload[i].addr = in_req_i[i].addr;
assign in_payload[i].write = in_req_i[i].write;
assign in_payload[i].wdata = in_req_i[i].wdata;
assign in_payload[i].wstrb = in_req_i[i].wstrb;
assign in_payload[i].valid = in_req_i[i].valid;
// Response
assign in_rsp_o[i].ready = in_ready[i];
assign in_rsp_o[i].rdata = out_rsp_i.rdata;
assign in_rsp_o[i].error = out_rsp_i.error;
end
stream_arbiter #(
.DATA_T (req_payload_t),
.N_INP (NoPorts)
) i_stream_arbiter (
.clk_i,
.rst_ni,
.inp_data_i (in_payload),
.inp_valid_i (in_valid),
.inp_ready_o (in_ready),
.oup_data_o (out_payload),
.oup_valid_o (out_req_o.valid),
.oup_ready_i (out_rsp_i.ready)
);
assign out_req_o.addr = out_payload.addr;
assign out_req_o.write = out_payload.write;
assign out_req_o.wdata = out_payload.wdata;
assign out_req_o.wstrb = out_payload.wstrb;
assign out_req_o.valid = out_payload.valid;
endmodule |
module cluster_clock_and2 (
input logic clk0_i,
input logic clk1_i,
output logic clk_o
);
tc_clk_and2 i_tc_clk_and2 (
.clk0_i,
.clk1_i,
.clk_o
);
endmodule |
Subsets and Splits