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module top;
initial begin
$display("Hex number ab should be printed: %h", 8'hAB);
end
endmodule |
module top(input a, output b);
assign b = a;
endmodule |
module top(output logic a, b, c, d, e, f, g, h, i, j, k, l);
initial begin
a = 1;
a -= 1;
b = 4;
b /= 2;
c = 5;
c %= 2;
d = 1;
d <<= 1;
e = 8;
e >>= 1;
f = 1;
f += 1;
g = 2;
g *= 3;
h = 3;
h &= 1;
i = 6;
i |= 4;
j = 1;
j ^= 0;
k = 5;
k <<<= 1;
l = 5;
l >>>= 1;
end
endmodule |
module top ();
wire a = 0;
wire b = 0;
wire c = 0;
wire d = 0;
reg out;
always @(*)
out = (a | b) & (c | d);
endmodule |
module top ();
wire a = 1;
reg b = 0;
always @* begin
if(a) b = 1;
else b = 0;
end
endmodule |
module top
(
input [0:3] in, // verilog_lint: waive packed-dimensions-range-ordering
output out_1, out_2, out_3, out_4, out_5, out_6, out_7, out_8, out_9, out_10,
out_11, out_12, out_13, out_14, out_15, out_16, out_17, out_18
);
assign out_1 = in[0] & in[1];
assign out_2 = in[0] | in[1];
assign out_3 = in[0] ~& in[1];
assign out_4 = in[0] ~| in[1];
assign out_5 = in[0] ^ in[1];
assign out_6 = in[0] ~^ in[1];
assign out_7 = in[0] ^~ in[1];
assign out_8 = ~in[0];
assign out_9 = in[0];
assign out_10 = &in[0];
assign out_11 = |in[0];
assign out_12 = ~&in[0];
assign out_13 = ~|in[0];
assign out_14 = ^in[0];
assign out_15 = ~^in[0];
assign out_16 = ^~in[0];
assign out_17 = in[0:1] && in [2:3];
assign out_18 = in[0:1] || in [2:3];
endmodule |
module top (i, index_o);
input [31:0] i;
output [1:2] index_o; // verilog_lint: waive packed-dimensions-range-ordering
wire [1:2] index_o; // verilog_lint: waive packed-dimensions-range-ordering
assign index_o[1] = i[1];
assign index_o[2] = i[0];
endmodule |
module top;
endmodule |
module prim_secded_top (
input logic [21:0] in_22,
output logic [21:0] d_o_28,
output logic [5:0] syndrome_o_28,
output logic [1:0] err_o_28,
input logic [31:0] in_32,
output logic [31:0] d_o_32,
output logic [6:0] syndrome_o_32,
output logic [1:0] err_o_32,
input logic [63:0] in_64,
output logic [63:0] d_o_72,
output logic [7:0] syndrome_o_64,
output logic [1:0] err_o_64
);
logic [27:0] enc_28;
prim_secded_28_22_enc enc1 (
.in ( in_22 ),
.out ( enc_28)
);
prim_secded_28_22_dec dec1 (
.in ( enc_28),
.d_o ( d_o_28),
.syndrome_o ( syndrome_o_28),
.err_o ( err_o_28)
);
logic [38:0] enc_39;
prim_secded_39_32_enc enc2 (
.in ( in_32),
.out ( enc_39)
);
prim_secded_39_32_dec dec2 (
.in ( enc_39),
.d_o ( d_o_32),
.syndrome_o ( syndrome_o_32),
.err_o ( err_o_32)
);
logic [71:0] enc_72;
prim_secded_72_64_enc enc3 (
.in ( in_64),
.out ( enc_72)
);
prim_secded_72_64_dec dec3 (
.in ( enc_72),
.d_o ( d_o_72),
.syndrome_o ( syndrome_o_64),
.err_o ( err_o_64)
);
endmodule |
module tft_ili9341_spi(
input spiClk, input[8:0] data, input dataAvailable,
output wire tft_sck, output reg tft_sdi, output reg tft_dc, output wire tft_cs,
output reg idle
);
// Registers
reg[0:2] counter = 3'b0;
reg[8:0] internalData;
reg internalSck;
reg cs;
initial internalSck <= 1'b1;
initial idle <= 1'b1;
initial cs <= 1'b0;
// Combinational Assignments
wire dataDc = internalData[8];
wire[0:7] dataShift = internalData[7:0]; // MSB first
assign tft_sck = internalSck & cs; // only drive sck with an active CS
assign tft_cs = !cs; // active low
// Update SPI CLK + Output data
always @ (posedge spiClk) begin
// Store new data in internal register
if (dataAvailable) begin
internalData <= data;
idle <= 1'b0;
end
// Change data if we're actively sending
if (!idle) begin
// Toggle Clock on every active tick
internalSck <= !internalSck;
// Check if SCK will be low next
if (internalSck) begin
// Update pins
tft_dc <= dataDc;
tft_sdi <= dataShift[counter];
cs <= 1'b1;
// Advance counter
counter <= counter + 1'b1;
idle <= &counter; // we're just sending the last bit
end
end
else begin
internalSck <= 1'b1; // idle mode (also: sent last bit)
if (internalSck) cs <= 1'b0; // idle for two bits in a row -> deactivate CS
end
end
endmodule |
module axis_dram_fifo_single
#(
parameter USE_SRAM_MEMORY = 0,
parameter USE_BD_INTERCON = 0,
parameter SR_BASE = 0
) (
input bus_clk,
input bus_rst,
input sys_clk,
input sys_rst,
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [63:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
output [31:0] rb_data,
input [63:0] forced_bit_err,
output init_calib_complete
);
// Misc declarations
axi4_rd_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_rd(.clk(sys_clk));
axi4_wr_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_wr(.clk(sys_clk));
axi4_rd_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(1)) mig_axi_rd(.clk(sys_clk));
axi4_wr_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(1)) mig_axi_wr(.clk(sys_clk));
wire [31:0] ddr3_dq; // Data pins. Input for Reads; Output for Writes.
wire [3:0] ddr3_dqs_n; // Data Strobes. Input for Reads; Output for Writes.
wire [3:0] ddr3_dqs_p;
wire [14:0] ddr3_addr; // Address
wire [2:0] ddr3_ba; // Bank Address
wire ddr3_ras_n; // Row Address Strobe.
wire ddr3_cas_n; // Column address select
wire ddr3_we_n; // Write Enable
wire ddr3_reset_n; // SDRAM reset pin.
wire [0:0] ddr3_ck_p; // Differential clock
wire [0:0] ddr3_ck_n;
wire [0:0] ddr3_cke; // Clock Enable
wire [0:0] ddr3_cs_n; // Chip Select
wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26; [2] = LDM.U26; ...
wire [0:0] ddr3_odt; // On-Die termination enable.
wire ddr3_axi_clk; // 1/4 DDR external clock rate (250MHz)
wire ddr3_axi_rst; // Synchronized to ddr_sys_clk
reg ddr3_axi_rst_reg_n; // Synchronized to ddr_sys_clk
wire ddr3_axi_clk_x2;
always @(posedge ddr3_axi_clk)
ddr3_axi_rst_reg_n <= ~ddr3_axi_rst;
axi_dma_fifo #(
.DEFAULT_BASE(30'h00010000),
.DEFAULT_MASK(30'hFFFF0000),
.DEFAULT_TIMEOUT(280),
.SR_BASE(SR_BASE),
.EXT_BIST(1),
.SIMULATION(1)
) axi_dma_fifo_i0 (
//
// Clocks and reset
.bus_clk (bus_clk),
.bus_reset (bus_rst),
.dram_clk (ddr3_axi_clk_x2),
.dram_reset (ddr3_axi_rst),
//
// AXI Write address channel
.m_axi_awid (dma_axi_wr.addr.id),
.m_axi_awaddr (dma_axi_wr.addr.addr),
.m_axi_awlen (dma_axi_wr.addr.len),
.m_axi_awsize (dma_axi_wr.addr.size),
.m_axi_awburst (dma_axi_wr.addr.burst),
.m_axi_awlock (dma_axi_wr.addr.lock),
.m_axi_awcache (dma_axi_wr.addr.cache),
.m_axi_awprot (dma_axi_wr.addr.prot),
.m_axi_awqos (dma_axi_wr.addr.qos),
.m_axi_awregion (dma_axi_wr.addr.region),
.m_axi_awuser (dma_axi_wr.addr.user),
.m_axi_awvalid (dma_axi_wr.addr.valid),
.m_axi_awready (dma_axi_wr.addr.ready),
//
// AXI Write data channel.
.m_axi_wdata (dma_axi_wr.data.data),
.m_axi_wstrb (dma_axi_wr.data.strb),
.m_axi_wlast (dma_axi_wr.data.last),
.m_axi_wuser (dma_axi_wr.data.user),
.m_axi_wvalid (dma_axi_wr.data.valid),
.m_axi_wready (dma_axi_wr.data.ready),
//
// AXI Write response channel signals
.m_axi_bid (dma_axi_wr.resp.id),
.m_axi_bresp (dma_axi_wr.resp.resp),
.m_axi_buser (dma_axi_wr.resp.user),
.m_axi_bvalid (dma_axi_wr.resp.valid),
.m_axi_bready (dma_axi_wr.resp.ready),
//
// AXI Read address channel
.m_axi_arid (dma_axi_rd.addr.id),
.m_axi_araddr (dma_axi_rd.addr.addr),
.m_axi_arlen (dma_axi_rd.addr.len),
.m_axi_arsize (dma_axi_rd.addr.size),
.m_axi_arburst (dma_axi_rd.addr.burst),
.m_axi_arlock (dma_axi_rd.addr.lock),
.m_axi_arcache (dma_axi_rd.addr.cache),
.m_axi_arprot (dma_axi_rd.addr.prot),
.m_axi_arqos (dma_axi_rd.addr.qos),
.m_axi_arregion (dma_axi_rd.addr.region),
.m_axi_aruser (dma_axi_rd.addr.user),
.m_axi_arvalid (dma_axi_rd.addr.valid),
.m_axi_arready (dma_axi_rd.addr.ready),
//
// AXI Read data channel
.m_axi_rid (dma_axi_rd.data.id),
.m_axi_rdata (dma_axi_rd.data.data),
.m_axi_rresp (dma_axi_rd.data.resp),
.m_axi_rlast (dma_axi_rd.data.last),
.m_axi_ruser (dma_axi_rd.data.user),
.m_axi_rvalid (dma_axi_rd.data.valid),
.m_axi_rready (dma_axi_rd.data.ready),
//
// CHDR friendly AXI stream input
.i_tdata (i_tdata),
.i_tlast (i_tlast),
.i_tvalid (i_tvalid),
.i_tready (i_tready),
//
// CHDR friendly AXI Stream output
.o_tdata (o_tdata),
.o_tlast (o_tlast),
.o_tvalid (o_tvalid),
.o_tready (o_tready),
//
// Settings
.set_stb (set_stb),
.set_addr (set_addr),
.set_data (set_data),
.rb_data (rb_data),
.debug()
);
generate if (USE_SRAM_MEMORY) begin
assign init_calib_complete = 1;
assign ddr3_axi_clk = bus_clk;
assign ddr3_axi_clk_x2 = bus_clk;
assign ddr3_axi_rst = bus_rst;
axi4_dualport_sram axi4_dualport_sram_i1 (
.s_aclk (ddr3_axi_clk_x2), // input s_aclk
.s_aresetn (~ddr3_axi_rst), // input s_aresetn
.s_axi_awid (dma_axi_wr.addr.id), // input [0 : 0] s_axi_awid
.s_axi_awaddr (dma_axi_wr.addr.addr), // input [31 : 0] s_axi_awaddr
.s_axi_awlen (dma_axi_wr.addr.len), // input [7 : 0] s_axi_awlen
.s_axi_awsize (dma_axi_wr.addr.size), // input [2 : 0] s_axi_awsize
.s_axi_awburst (dma_axi_wr.addr.burst), // input [1 : 0] s_axi_awburst
.s_axi_awvalid (dma_axi_wr.addr.valid), // input s_axi_awvalid
.s_axi_awready (dma_axi_wr.addr.ready), // output s_axi_awready
.s_axi_wdata (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] s_axi_wdata
.s_axi_wstrb (dma_axi_wr.data.strb), // input [7 : 0] s_axi_wstrb
.s_axi_wlast (dma_axi_wr.data.last), // input s_axi_wlast
.s_axi_wvalid (dma_axi_wr.data.valid), // input s_axi_wvalid
.s_axi_wready (dma_axi_wr.data.ready), // output s_axi_wready
.s_axi_bid (dma_axi_wr.resp.id), // output [0 : 0] s_axi_bid
.s_axi_bresp (dma_axi_wr.resp.resp), // output [1 : 0] s_axi_bresp
.s_axi_bvalid (dma_axi_wr.resp.valid), // output s_axi_bvalid
.s_axi_bready (dma_axi_wr.resp.ready), // input s_axi_bready
.s_axi_arid (dma_axi_rd.addr.id), // input [0 : 0] s_axi_arid
.s_axi_araddr (dma_axi_rd.addr.addr), // input [31 : 0] s_axi_araddr
.s_axi_arlen (dma_axi_rd.addr.len), // input [7 : 0] s_axi_arlen
.s_axi_arsize (dma_axi_rd.addr.size), // input [2 : 0] s_axi_arsize
.s_axi_arburst (dma_axi_rd.addr.burst), // input [1 : 0] s_axi_arburst
.s_axi_arvalid (dma_axi_rd.addr.valid), // input s_axi_arvalid
.s_axi_arready (dma_axi_rd.addr.ready), // output s_axi_arready
.s_axi_rid (dma_axi_rd.data.id), // output [0 : 0] s_axi_rid
.s_axi_rdata (dma_axi_rd.data.data), // output [63 : 0] s_axi_rdata
.s_axi_rresp (dma_axi_rd.data.resp), // output [1 : 0] s_axi_rresp
.s_axi_rlast (dma_axi_rd.data.last), // output s_axi_rlast
.s_axi_rvalid (dma_axi_rd.data.valid), // output s_axi_rvalid
.s_axi_rready (dma_axi_rd.data.ready) // input s_axi_rready
);
end else begin //generate if (USE_SRAM_MEMORY) begin
//---------------------------------------------------
// We use an interconnect to connect to FIFOs.
//---------------------------------------------------
if (USE_BD_INTERCON) begin
// Vivado Block Diagram interconnect.
axi_intercon_2x64_128_bd_wrapper axi_intercon_2x64_128_i (
.S00_AXI_ACLK (ddr3_axi_clk_x2), // input S00_AXI_ACLK
.S00_AXI_ARESETN (~ddr3_axi_rst), // input S00_AXI_ARESETN
.S00_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID
.S00_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR
.S00_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN
.S00_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE
.S00_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST
.S00_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK
.S00_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE
.S00_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT
.S00_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS
.S00_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID
.S00_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY
.S00_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA
.S00_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB
.S00_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST
.S00_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID
.S00_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY
.S00_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID
.S00_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP
.S00_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID
.S00_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY
.S00_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID
.S00_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR
.S00_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN
.S00_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE
.S00_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST
.S00_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK
.S00_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE
.S00_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT
.S00_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS
.S00_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID
.S00_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY
.S00_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID
.S00_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA
.S00_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP
.S00_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST
.S00_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID
.S00_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY
//
//.S01_AXI_ARESET_OUT_N (), // output S01_AXI_ARESET_OUT_N
.S01_AXI_ACLK (ddr3_axi_clk_x2), // input S01_AXI_ACLK
.S01_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN
.S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S01_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S01_AXI_AWREADY (), // output S01_AXI_AWREADY
.S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S01_AXI_WLAST (0), // input S01_AXI_WLAST
.S01_AXI_WVALID (0), // input S01_AXI_WVALID
.S01_AXI_WREADY (), // output S01_AXI_WREADY
.S01_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S01_AXI_BVALID (), // output S01_AXI_BVALID
.S01_AXI_BREADY (0), // input S01_AXI_BREADY
.S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S01_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S01_AXI_ARREADY (), // output S01_AXI_ARREADY
.S01_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S01_AXI_RLAST (), // output S01_AXI_RLAST
.S01_AXI_RVALID (), // output S01_AXI_RVALID
.S01_AXI_RREADY (0), // input S01_AXI_RREADY
//
//.M00_AXI_ARESET_OUT_N (), // output M00_AXI_ARESET_OUT_N
.M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK
.M00_AXI_ARESETN (~ddr3_axi_rst), // input M00_AXI_ARESETN
.M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID
.M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR
.M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN
.M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE
.M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST
.M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK
.M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE
.M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT
.M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS
.M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID
.M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY
.M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA
.M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB
.M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST
.M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID
.M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY
.M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID
.M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP
.M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID
.M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY
.M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID
.M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR
.M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN
.M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE
.M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST
.M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK
.M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE
.M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT
.M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS
.M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID
.M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY
.M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID
.M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA
.M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP
.M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST
.M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID
.M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY
);
end else begin
//Original IP interconnect
axi_intercon_2x64_128 axi_intercon_2x64_128_i (
.INTERCONNECT_ACLK(ddr3_axi_clk_x2), // input INTERCONNECT_ACLK
.INTERCONNECT_ARESETN(~ddr3_axi_rst), // input INTERCONNECT_ARESETN
//
.S00_AXI_ARESET_OUT_N (), // output S00_AXI_ARESET_OUT_N
.S00_AXI_ACLK (ddr3_axi_clk_x2), // input S00_AXI_ACLK
.S00_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID
.S00_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR
.S00_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN
.S00_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE
.S00_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST
.S00_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK
.S00_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE
.S00_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT
.S00_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS
.S00_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID
.S00_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY
.S00_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA
.S00_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB
.S00_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST
.S00_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID
.S00_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY
.S00_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID
.S00_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP
.S00_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID
.S00_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY
.S00_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID
.S00_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR
.S00_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN
.S00_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE
.S00_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST
.S00_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK
.S00_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE
.S00_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT
.S00_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS
.S00_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID
.S00_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY
.S00_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID
.S00_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA
.S00_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP
.S00_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST
.S00_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID
.S00_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY
//
.S01_AXI_ARESET_OUT_N (), // output S01_AXI_ARESET_OUT_N
.S01_AXI_ACLK (ddr3_axi_clk_x2), // input S01_AXI_ACLK
.S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S01_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S01_AXI_AWREADY (), // output S01_AXI_AWREADY
.S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S01_AXI_WLAST (0), // input S01_AXI_WLAST
.S01_AXI_WVALID (0), // input S01_AXI_WVALID
.S01_AXI_WREADY (), // output S01_AXI_WREADY
.S01_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S01_AXI_BVALID (), // output S01_AXI_BVALID
.S01_AXI_BREADY (0), // input S01_AXI_BREADY
.S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S01_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S01_AXI_ARREADY (), // output S01_AXI_ARREADY
.S01_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S01_AXI_RLAST (), // output S01_AXI_RLAST
.S01_AXI_RVALID (), // output S01_AXI_RVALID
.S01_AXI_RREADY (0), // input S01_AXI_RREADY
//
.M00_AXI_ARESET_OUT_N (), // output M00_AXI_ARESET_OUT_N
.M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK
.M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID
.M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR
.M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN
.M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE
.M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST
.M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK
.M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE
.M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT
.M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS
.M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID
.M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY
.M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA
.M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB
.M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST
.M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID
.M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY
.M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID
.M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP
.M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID
.M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY
.M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID
.M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR
.M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN
.M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE
.M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST
.M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK
.M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE
.M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT
.M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS
.M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID
.M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY
.M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID
.M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA
.M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP
.M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST
.M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID
.M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY
);
end
//---------------------------------------------------
// MIG
//---------------------------------------------------
wire ddr3_idelay_refclk;
ddr3_32bit ddr_mig_i (
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.ui_clk (ddr3_axi_clk), // 150MHz clock out
.ui_addn_clk_0 (ddr3_axi_clk_x2), // 300MHz clock out
.ui_addn_clk_1 (ddr3_idelay_refclk),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.clk_ref_i (ddr3_idelay_refclk),
.ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 150MHz
.aresetn (ddr3_axi_rst_reg_n),
.app_sr_req (1'b0),
.app_sr_active (),
.app_ref_req (1'b0),
.app_ref_ack (),
.app_zq_req (1'b0),
.app_zq_ack (),
.device_temp_i (12'd0),
// Slave Interface Write Address Ports
.s_axi_awid (mig_axi_wr.addr.id),
.s_axi_awaddr (mig_axi_wr.addr.addr),
.s_axi_awlen (mig_axi_wr.addr.len),
.s_axi_awsize (mig_axi_wr.addr.size),
.s_axi_awburst (mig_axi_wr.addr.burst),
.s_axi_awlock (mig_axi_wr.addr.lock),
.s_axi_awcache (mig_axi_wr.addr.cache),
.s_axi_awprot (mig_axi_wr.addr.prot),
.s_axi_awqos (mig_axi_wr.addr.qos),
.s_axi_awvalid (mig_axi_wr.addr.valid),
.s_axi_awready (mig_axi_wr.addr.ready),
// Slave Interface Write Data Ports
.s_axi_wdata (mig_axi_wr.data.data),
.s_axi_wstrb (mig_axi_wr.data.strb),
.s_axi_wlast (mig_axi_wr.data.last),
.s_axi_wvalid (mig_axi_wr.data.valid),
.s_axi_wready (mig_axi_wr.data.ready),
// Slave Interface Write Response Ports
.s_axi_bid (mig_axi_wr.resp.id),
.s_axi_bresp (mig_axi_wr.resp.resp),
.s_axi_bvalid (mig_axi_wr.resp.valid),
.s_axi_bready (mig_axi_wr.resp.ready),
// Slave Interface Read Address Ports
.s_axi_arid (mig_axi_rd.addr.id),
.s_axi_araddr (mig_axi_rd.addr.addr),
.s_axi_arlen (mig_axi_rd.addr.len),
.s_axi_arsize (mig_axi_rd.addr.size),
.s_axi_arburst (mig_axi_rd.addr.burst),
.s_axi_arlock (mig_axi_rd.addr.lock),
.s_axi_arcache (mig_axi_rd.addr.cache),
.s_axi_arprot (mig_axi_rd.addr.prot),
.s_axi_arqos (mig_axi_rd.addr.qos),
.s_axi_arvalid (mig_axi_rd.addr.valid),
.s_axi_arready (mig_axi_rd.addr.ready),
// Slave Interface Read Data Ports
.s_axi_rid (mig_axi_rd.data.id),
.s_axi_rdata (mig_axi_rd.data.data),
.s_axi_rresp (mig_axi_rd.data.resp),
.s_axi_rlast (mig_axi_rd.data.last),
.s_axi_rvalid (mig_axi_rd.data.valid),
.s_axi_rready (mig_axi_rd.data.ready),
// System Clock Ports
.sys_clk_i (sys_clk), // From external 100MHz source.
.sys_rst (sys_rst)
);
//---------------------------------------------------
// DDR3 SDRAM Models
//---------------------------------------------------
ddr3_model #(
.DEBUG(0) //Disable verbose prints
) sdram_i0 (
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke),
.cs_n (ddr3_cs_n),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm[1:0]),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq[15:0]),
.dqs (ddr3_dqs_p[1:0]),
.dqs_n (ddr3_dqs_n[1:0]),
.tdqs_n (), // Unused on x16
.odt (ddr3_odt)
);
ddr3_model #(
.DEBUG(0) //Disable verbose prints
) sdram_i1 (
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke),
.cs_n (ddr3_cs_n),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm[3:2]),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq[31:16]),
.dqs (ddr3_dqs_p[3:2]),
.dqs_n (ddr3_dqs_n[3:2]),
.tdqs_n (), // Unused on x16
.odt (ddr3_odt)
);
end endgenerate
endmodule |
module axis_dram_fifo_single
#(
parameter DIFF_CLK = 0,
parameter SR_BASE = 0
) (
input bus_clk,
input bus_rst,
input sys_clk_p,
input sys_clk_n,
input sys_rst_n,
input dma_engine_clk,
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [63:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
output [31:0] rb_data,
input [63:0] forced_bit_err,
output init_calib_complete
);
wire ddr3_axi_clk; // 1/4 DDR external clock rate (250MHz)
wire ddr3_axi_rst; // Synchronized to ddr_sys_clk
reg ddr3_axi_rst_reg_n; // Synchronized to ddr_sys_clk
// Misc declarations
axi4_rd_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_rd(.clk(dma_engine_clk));
axi4_wr_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_wr(.clk(dma_engine_clk));
axi4_rd_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(4)) mig_axi_rd(.clk(ddr3_axi_clk));
axi4_wr_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(4)) mig_axi_wr(.clk(ddr3_axi_clk));
wire [31:0] ddr3_dq; // Data pins. Input for Reads; Output for Writes.
wire [3:0] ddr3_dqs_n; // Data Strobes. Input for Reads; Output for Writes.
wire [3:0] ddr3_dqs_p;
wire [15:0] ddr3_addr; // Address
wire [2:0] ddr3_ba; // Bank Address
wire ddr3_ras_n; // Row Address Strobe.
wire ddr3_cas_n; // Column address select
wire ddr3_we_n; // Write Enable
wire ddr3_reset_n; // SDRAM reset pin.
wire [0:0] ddr3_ck_p; // Differential clock
wire [0:0] ddr3_ck_n;
wire [0:0] ddr3_cke; // Clock Enable
wire [0:0] ddr3_cs_n; // Chip Select
wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26; [2] = LDM.U26; ...
wire [0:0] ddr3_odt; // On-Die termination enable.
always @(posedge ddr3_axi_clk)
ddr3_axi_rst_reg_n <= ~ddr3_axi_rst;
axi_dma_fifo #(
.DEFAULT_BASE(30'h02000000),
.DEFAULT_MASK(30'hFF000000),
.DEFAULT_TIMEOUT(280),
.SR_BASE(SR_BASE),
.EXT_BIST(1),
.SIMULATION(1)
) axi_dma_fifo_i0 (
//
// Clocks and reset
.bus_clk (bus_clk),
.bus_reset (bus_rst),
.dram_clk (dma_engine_clk),
.dram_reset (ddr3_axi_rst),
//
// AXI Write address channel
.m_axi_awid (dma_axi_wr.addr.id),
.m_axi_awaddr (dma_axi_wr.addr.addr),
.m_axi_awlen (dma_axi_wr.addr.len),
.m_axi_awsize (dma_axi_wr.addr.size),
.m_axi_awburst (dma_axi_wr.addr.burst),
.m_axi_awlock (dma_axi_wr.addr.lock),
.m_axi_awcache (dma_axi_wr.addr.cache),
.m_axi_awprot (dma_axi_wr.addr.prot),
.m_axi_awqos (dma_axi_wr.addr.qos),
.m_axi_awregion (dma_axi_wr.addr.region),
.m_axi_awuser (dma_axi_wr.addr.user),
.m_axi_awvalid (dma_axi_wr.addr.valid),
.m_axi_awready (dma_axi_wr.addr.ready),
//
// AXI Write data channel.
.m_axi_wdata (dma_axi_wr.data.data),
.m_axi_wstrb (dma_axi_wr.data.strb),
.m_axi_wlast (dma_axi_wr.data.last),
.m_axi_wuser (dma_axi_wr.data.user),
.m_axi_wvalid (dma_axi_wr.data.valid),
.m_axi_wready (dma_axi_wr.data.ready),
//
// AXI Write response channel signals
.m_axi_bid (dma_axi_wr.resp.id),
.m_axi_bresp (dma_axi_wr.resp.resp),
.m_axi_buser (dma_axi_wr.resp.user),
.m_axi_bvalid (dma_axi_wr.resp.valid),
.m_axi_bready (dma_axi_wr.resp.ready),
//
// AXI Read address channel
.m_axi_arid (dma_axi_rd.addr.id),
.m_axi_araddr (dma_axi_rd.addr.addr),
.m_axi_arlen (dma_axi_rd.addr.len),
.m_axi_arsize (dma_axi_rd.addr.size),
.m_axi_arburst (dma_axi_rd.addr.burst),
.m_axi_arlock (dma_axi_rd.addr.lock),
.m_axi_arcache (dma_axi_rd.addr.cache),
.m_axi_arprot (dma_axi_rd.addr.prot),
.m_axi_arqos (dma_axi_rd.addr.qos),
.m_axi_arregion (dma_axi_rd.addr.region),
.m_axi_aruser (dma_axi_rd.addr.user),
.m_axi_arvalid (dma_axi_rd.addr.valid),
.m_axi_arready (dma_axi_rd.addr.ready),
//
// AXI Read data channel
.m_axi_rid (dma_axi_rd.data.id),
.m_axi_rdata (dma_axi_rd.data.data),
.m_axi_rresp (dma_axi_rd.data.resp),
.m_axi_rlast (dma_axi_rd.data.last),
.m_axi_ruser (dma_axi_rd.data.user),
.m_axi_rvalid (dma_axi_rd.data.valid),
.m_axi_rready (dma_axi_rd.data.ready),
//
// CHDR friendly AXI stream input
.i_tdata (i_tdata),
.i_tlast (i_tlast),
.i_tvalid (i_tvalid),
.i_tready (i_tready),
//
// CHDR friendly AXI Stream output
.o_tdata (o_tdata),
.o_tlast (o_tlast),
.o_tvalid (o_tvalid),
.o_tready (o_tready),
//
// Settings
.set_stb (set_stb),
.set_addr (set_addr),
.set_data (set_data),
.rb_data (rb_data),
.debug()
);
//---------------------------------------------------
// We use an interconnect to connect to FIFOs.
//---------------------------------------------------
// Attach to third slave just to validate proper ID handling in interconnect
axi_intercon_4x64_256_bd_wrapper axi_intercon_i (
//
.S00_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK
.S00_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN
.S00_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S00_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S00_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S00_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S00_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S00_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S00_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S00_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S00_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S00_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S00_AXI_AWREADY (), // output S01_AXI_AWREADY
.S00_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S00_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S00_AXI_WLAST (0), // input S01_AXI_WLAST
.S00_AXI_WVALID (0), // input S01_AXI_WVALID
.S00_AXI_WREADY (), // output S01_AXI_WREADY
.S00_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S00_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S00_AXI_BVALID (), // output S01_AXI_BVALID
.S00_AXI_BREADY (1), // input S01_AXI_BREADY
.S00_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S00_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S00_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S00_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S00_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S00_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S00_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S00_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S00_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S00_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S00_AXI_ARREADY (), // output S01_AXI_ARREADY
.S00_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S00_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S00_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S00_AXI_RLAST (), // output S01_AXI_RLAST
.S00_AXI_RVALID (), // output S01_AXI_RVALID
.S00_AXI_RREADY (1), // input S01_AXI_RREADY
//
.S01_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK
.S01_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN
.S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S01_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S01_AXI_AWREADY (), // output S01_AXI_AWREADY
.S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S01_AXI_WLAST (0), // input S01_AXI_WLAST
.S01_AXI_WVALID (0), // input S01_AXI_WVALID
.S01_AXI_WREADY (), // output S01_AXI_WREADY
.S01_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S01_AXI_BVALID (), // output S01_AXI_BVALID
.S01_AXI_BREADY (1), // input S01_AXI_BREADY
.S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S01_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S01_AXI_ARREADY (), // output S01_AXI_ARREADY
.S01_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S01_AXI_RLAST (), // output S01_AXI_RLAST
.S01_AXI_RVALID (), // output S01_AXI_RVALID
.S01_AXI_RREADY (1), // input S01_AXI_RREADY
//
.S02_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK
.S02_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN
.S02_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S02_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S02_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S02_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S02_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S02_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S02_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S02_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S02_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S02_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S02_AXI_AWREADY (), // output S01_AXI_AWREADY
.S02_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S02_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S02_AXI_WLAST (0), // input S01_AXI_WLAST
.S02_AXI_WVALID (0), // input S01_AXI_WVALID
.S02_AXI_WREADY (), // output S01_AXI_WREADY
.S02_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S02_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S02_AXI_BVALID (), // output S01_AXI_BVALID
.S02_AXI_BREADY (1), // input S01_AXI_BREADY
.S02_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S02_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S02_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S02_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S02_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S02_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S02_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S02_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S02_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S02_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S02_AXI_ARREADY (), // output S01_AXI_ARREADY
.S02_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S02_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S02_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S02_AXI_RLAST (), // output S01_AXI_RLAST
.S02_AXI_RVALID (), // output S01_AXI_RVALID
.S02_AXI_RREADY (1), // input S01_AXI_RREADY
//
.S03_AXI_ACLK (dma_engine_clk), // input S00_AXI_ACLK
.S03_AXI_ARESETN (~ddr3_axi_rst), // input S00_AXI_ARESETN
.S03_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID
.S03_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR
.S03_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN
.S03_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE
.S03_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST
.S03_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK
.S03_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE
.S03_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT
.S03_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS
.S03_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID
.S03_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY
.S03_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA
.S03_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB
.S03_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST
.S03_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID
.S03_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY
.S03_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID
.S03_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP
.S03_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID
.S03_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY
.S03_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID
.S03_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR
.S03_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN
.S03_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE
.S03_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST
.S03_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK
.S03_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE
.S03_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT
.S03_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS
.S03_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID
.S03_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY
.S03_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID
.S03_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA
.S03_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP
.S03_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST
.S03_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID
.S03_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY
//
.M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK
.M00_AXI_ARESETN (~ddr3_axi_rst), // input M00_AXI_ARESETN
.M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID
.M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR
.M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN
.M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE
.M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST
.M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK
.M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE
.M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT
.M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS
.M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID
.M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY
.M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA
.M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB
.M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST
.M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID
.M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY
.M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID
.M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP
.M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID
.M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY
.M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID
.M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR
.M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN
.M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE
.M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST
.M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK
.M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE
.M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT
.M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS
.M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID
.M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY
.M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID
.M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA
.M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP
.M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST
.M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID
.M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY
);
//---------------------------------------------------
// MIG
//---------------------------------------------------
ddr3_32bit ddr_mig_i (
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.ui_clk (ddr3_axi_clk), // 150MHz clock out
.ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 150MHz
.aresetn (ddr3_axi_rst_reg_n),
.app_sr_req (1'b0),
.app_sr_active (),
.app_ref_req (1'b0),
.app_ref_ack (),
.app_zq_req (1'b0),
.app_zq_ack (),
// Slave Interface Write Address Ports
.s_axi_awid (mig_axi_wr.addr.id),
.s_axi_awaddr (mig_axi_wr.addr.addr),
.s_axi_awlen (mig_axi_wr.addr.len),
.s_axi_awsize (mig_axi_wr.addr.size),
.s_axi_awburst (mig_axi_wr.addr.burst),
.s_axi_awlock (mig_axi_wr.addr.lock),
.s_axi_awcache (mig_axi_wr.addr.cache),
.s_axi_awprot (mig_axi_wr.addr.prot),
.s_axi_awqos (mig_axi_wr.addr.qos),
.s_axi_awvalid (mig_axi_wr.addr.valid),
.s_axi_awready (mig_axi_wr.addr.ready),
// Slave Interface Write Data Ports
.s_axi_wdata (mig_axi_wr.data.data),
.s_axi_wstrb (mig_axi_wr.data.strb),
.s_axi_wlast (mig_axi_wr.data.last),
.s_axi_wvalid (mig_axi_wr.data.valid),
.s_axi_wready (mig_axi_wr.data.ready),
// Slave Interface Write Response Ports
.s_axi_bid (mig_axi_wr.resp.id),
.s_axi_bresp (mig_axi_wr.resp.resp),
.s_axi_bvalid (mig_axi_wr.resp.valid),
.s_axi_bready (mig_axi_wr.resp.ready),
// Slave Interface Read Address Ports
.s_axi_arid (mig_axi_rd.addr.id),
.s_axi_araddr (mig_axi_rd.addr.addr),
.s_axi_arlen (mig_axi_rd.addr.len),
.s_axi_arsize (mig_axi_rd.addr.size),
.s_axi_arburst (mig_axi_rd.addr.burst),
.s_axi_arlock (mig_axi_rd.addr.lock),
.s_axi_arcache (mig_axi_rd.addr.cache),
.s_axi_arprot (mig_axi_rd.addr.prot),
.s_axi_arqos (mig_axi_rd.addr.qos),
.s_axi_arvalid (mig_axi_rd.addr.valid),
.s_axi_arready (mig_axi_rd.addr.ready),
// Slave Interface Read Data Ports
.s_axi_rid (mig_axi_rd.data.id),
.s_axi_rdata (mig_axi_rd.data.data),
.s_axi_rresp (mig_axi_rd.data.resp),
.s_axi_rlast (mig_axi_rd.data.last),
.s_axi_rvalid (mig_axi_rd.data.valid),
.s_axi_rready (mig_axi_rd.data.ready),
// System Clock Ports
.sys_clk_p (sys_clk_p), // From external 100MHz source.
.sys_clk_n (sys_clk_n), // From external 100MHz source.
.clk_ref_i (bus_clk),
.sys_rst (sys_rst_n) // IJB. Poorly named active low. Should change RST_ACT_LOW.
);
//---------------------------------------------------
// DDR3 SDRAM Models
//---------------------------------------------------
ddr3_model #(
.DEBUG(0) //Disable verbose prints
) sdram_i0 (
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke),
.cs_n (ddr3_cs_n),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm[1:0]),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq[15:0]),
.dqs (ddr3_dqs_p[1:0]),
.dqs_n (ddr3_dqs_n[1:0]),
.tdqs_n (), // Unused on x16
.odt (ddr3_odt)
);
ddr3_model #(
.DEBUG(0) //Disable verbose prints
) sdram_i1 (
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke),
.cs_n (ddr3_cs_n),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm[3:2]),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq[31:16]),
.dqs (ddr3_dqs_p[3:2]),
.dqs_n (ddr3_dqs_n[3:2]),
.tdqs_n (), // Unused on x16
.odt (ddr3_odt)
);
endmodule |
module noc_block_eq_tb;
`TEST_BENCH_INIT("noc_block_eq_tb", `NUM_TEST_CASES, `NS_PER_TICK);
`RFNOC_SIM_INIT(1, 166.67, 200);
`RFNOC_ADD_BLOCK(noc_block_eq, 0);
localparam PACKET_SIZE = 64;
//----------------------------------------------------------------------------
// Stimulus
//----------------------------------------------------------------------------
shortint long_preamble[PACKET_SIZE] = '{0, 0, 0, 0, 0, 0, 1, 1, -1, -1,
1, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1, -1, -1, 1, 1, -1, 1, -1, 1, 1, 1, 1, 0,
1, -1, -1, 1, 1, -1, 1, -1, 1, -1, -1, -1, -1, -1, 1, 1, -1, -1, 1, -1, 1,
-1, 1, 1, 1, 1, 0, 0, 0, 0, 0};
initial begin
logic [63:0] header;
cvita_pkt_t packet;
reg [63:0] mem [0:65535];
int file;
int file_length;
// Prepare preamble: Scale to full range
foreach(long_preamble[i]) begin
if(long_preamble[i] == 1)
long_preamble[i] = 32767;
else if(long_preamble[i] == -1)
long_preamble[i] = -32768;
end
while(bus_rst) @(posedge bus_clk);
while(ce_rst) @(posedge ce_clk);
repeat(10) @(posedge bus_clk);
// Test bench -> Equalizer -> Test bench
`RFNOC_CONNECT_BLOCK_PORT(noc_block_tb, 1, noc_block_eq, 0, PACKET_SIZE*4);
`RFNOC_CONNECT_BLOCK_PORT(noc_block_eq, 0, noc_block_tb, 1, PACKET_SIZE*4);
// Setup equalizer
tb_next_dst = sid_noc_block_eq;
repeat(10) @(posedge bus_clk);
//-------------------------------------------------------------------------
// Setup header
header = flatten_chdr_no_ts('{pkt_type: DATA, has_time: 0, eob: 1,
seqno: 12'h0, length: 8, src_sid: sid_noc_block_tb,
dst_sid: sid_noc_block_eq, timestamp: 64'h0});
packet.push_back(header);
// Add preamble
for(int i = 0; i < PACKET_SIZE - 1; i = i + 2) begin
logic [63:0] preamble;
preamble = {shortint'(long_preamble[i]), shortint'(0),
shortint'(long_preamble[i + 1]), shortint'(0)};
packet.push_back(preamble);
end
// Send preamble
tb_cvita_data.push_pkt(packet);
packet = {};
//-------------------------------------------------------------------------
// Change header
header[60] = 0; // EOB
packet.push_back(header);
// Add data
for(int i = 0; i < PACKET_SIZE / 2; ++i) begin
logic [63:0] data;
shortint pos;
shortint neg;
pos = 32767;
neg = -32768;
data = {pos, neg, neg, pos};
packet.push_back(data);
end
// Send data
tb_cvita_data.push_pkt(packet);
packet = {};
//-------------------------------------------------------------------------
#100000;
// Read file
file = $fopen("../../../../test-int16.bin", "r");
file_length = $fread(mem, file);
$display("Read %d lines", file_length);
$fclose(file);
// Change header
header[60] = 1; // EOB
packet.push_back(header);
// Add preamble
for(int i = 0; i < PACKET_SIZE / 2; ++i) begin
packet.push_back(mem[i]);
end
// Send preamble
tb_cvita_data.push_pkt(packet);
packet = {};
//-------------------------------------------------------------------------
// Change header
header[60] = 0; // EOB
packet.push_back(header);
// Add data
for (int i = PACKET_SIZE / 2; i < PACKET_SIZE; ++i) begin
packet.push_back(mem[i]);
end
// Send data
tb_cvita_data.push_pkt(packet);
packet = {};
//-------------------------------------------------------------------------
#100000;
$finish;
end
//----------------------------------------------------------------------------
// Verification
//----------------------------------------------------------------------------
initial begin : tb_main
logic [63:0] data;
cvita_pkt_t packet;
reg [63:0] comp [0:65535];
int file;
int file_length;
// Read file
file = $fopen("../../../../comp-int16.bin", "r");
file_length = $fread(comp, file);
$display("Read %d lines", file_length);
$fclose(file);
`TEST_CASE_START("Wait for reset");
while (bus_rst) @(posedge bus_clk);
while (ce_rst) @(posedge ce_clk);
`TEST_CASE_DONE(~bus_rst & ~ce_rst);
#70000;
packet = {};
`TEST_CASE_START("Receive data");
tb_cvita_data.pull_pkt(packet);
$display("Header: %H", packet.pop_front());
foreach(packet[i]) begin
data = packet[i];
$display("Received[%d]: %d, %d | %d, %d (%h)", shortint'(i),
shortint'(data[63:48]), shortint'(data[47:32]), shortint'(data[31:16]),
shortint'(data[15:0]), data);
end
`TEST_CASE_DONE(1);
packet = {};
`TEST_CASE_START("Receive file data");
tb_cvita_data.pull_pkt(packet);
$display("Header: %H", packet.pop_front());
foreach(packet[i]) begin
data = packet[i];
$display("Received[%d]: %d, %d | %d, %d (%h)", shortint'(i),
shortint'(data[63:48]), shortint'(data[47:32]), shortint'(data[31:16]),
shortint'(data[15:0]), data);
end
`TEST_CASE_DONE(1);
// End simulation
#1000;
$finish;
end
endmodule |
module Hq2x_optimized
#(
parameter LENGTH = 858,
parameter HALF_DEPTH = 0
)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input hblank,
output [DWIDTH:0] outpixel /*verilator public*/
);
localparam AWIDTH = $clog2(LENGTH)-1;
localparam DWIDTH = HALF_DEPTH ? 11 : 23;
localparam DWIDTH1 = DWIDTH+1;
localparam EXACT_BUFFER = 1;
`HQ_TABLE_TYPE [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
reg [23:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] cyc;
reg curbuf;
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(
clk,
Curr1,
(cyc == 0) ? Prev0 :
(cyc == 1) ? Curr0 :
(cyc == 2) ? Prev2 : Next1,
diff0
);
DiffCheck diffcheck1(
clk,
Curr1,
(cyc == 0) ? Prev1 :
(cyc == 1) ? Next0 :
(cyc == 2) ? Curr2 : Next2,
diff1
);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
wire [23:0] blend_result_pre;
Blend blender(clk, hqTable[nextpatt], disable_hq2x, Curr0_d, X_d, B_d, D_d, F_d, H_d, blend_result_pre);
reg [23:0] Curr0_d, X_d, B_d, D_d, F_d, H_d;
delayline #(
.WIDTH(6*24),
.CYCLES(4)
) blender_queue (
.clock(clk),
.in({ Curr0, X, B, D, F, H }),
.out({ Curr0_d, X_d, B_d, D_d, F_d, H_d })
);
wire [DWIDTH:0] Curr20tmp;
wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
wire [DWIDTH:0] Curr21tmp;
wire [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
reg wrin_en;
function [23:0] h2rgb;
input [11:0] v;
begin
h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]};
end
endfunction
function [11:0] rgb2h;
input [23:0] v;
begin
rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]};
end
endfunction
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(offs),
.rdbuf0(prevbuf),
.rdbuf1(curbuf),
.q0(Curr20tmp),
.q1(Curr21tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
.data(wrpix),
.wren(wrin_en)
);
reg [AWIDTH+1:0] read_x /*verilator public*/;
reg [AWIDTH+1:0] wrout_addr, wrout_addr_delayed;
reg wrout_en, wrout_en_delayed;
reg [DWIDTH1*4-1:0] wrdata, wrdata_pre;
wire [DWIDTH1*4-1:0] outpixel_x4;
reg [DWIDTH1*2-1:0] outpixel_x2;
delayline #(
.WIDTH(AWIDTH+1+1+1),
.CYCLES(22)
) wrdl (
.clock(clk),
.in({ wrout_en, wrout_addr }),
.out({ wrout_en_delayed, wrout_addr_delayed })
);
assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
hq2x_buf #(.NUMWORDS(EXACT_BUFFER ? LENGTH : LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
(
.clock(clk),
.rdaddress(EXACT_BUFFER ? read_x[AWIDTH+1:1] : {read_x[AWIDTH+1:1],read_y[1]}),
.q(outpixel_x4),
.data(wrdata),
.wraddress(wrout_addr_delayed),
.wren(wrout_en_delayed)
);
wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
reg [AWIDTH:0] offs /*verilator public*/;
always @(posedge clk) begin
reg old_reset_line;
reg old_reset_frame;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
if(~&offs) begin
if (cyc == 1) begin
Prev2 <= Curr20;
Curr2 <= Curr21;
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
case({cyc[1],^cyc})
0: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
1: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
2: wrdata[DWIDTH:0] <= blend_result;
3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
endcase
if(cyc==3) begin
offs <= offs + 1'd1;
wrout_addr <= EXACT_BUFFER ? offs : {offs, curbuf};
wrout_en <= 1;
end
end
if(cyc==0) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
end else begin
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
end
if(cyc==3) begin
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
{Prev0, Prev1} <= {Prev1, Prev2};
{Curr0, Curr1} <= {Curr1, Curr2};
{Next0, Next1} <= {Next1, Next2};
end else begin
{B, F, H, D} <= {F, H, D, B};
end
cyc <= cyc + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
cyc <= 0;
curbuf <= ~curbuf;
prevbuf <= curbuf;
{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
if(old_reset_frame & ~reset_frame) begin
curbuf <= 0;
prevbuf <= 0;
end
end
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
if(hblank) read_x <= 0;
old_reset_line <= reset_line;
end
end
endmodule |
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf0, rdbuf1,
output[DWIDTH:0] q0,q1,
input [AWIDTH:0] wraddr,
input wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = $clog2(LENGTH)-1;
wire [DWIDTH:0] out[2];
assign q0 = out[rdbuf0];
assign q1 = out[rdbuf1];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule |
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data /*verilator public*/,
input [AWIDTH:0] rdaddress /*verilator public*/,
input [AWIDTH:0] wraddress /*verilator public*/,
input wren /*verilator public*/,
output logic [DWIDTH:0] q /*verilator public*/
);
(* max_depth = 1024 *) (* ramstyle = "no_rw_check" *) logic [DWIDTH:0] ram[0:NUMWORDS-1];
always_ff@(posedge clock) begin
if(wren) ram[wraddress] <= data;
q <= ram[rdaddress];
end
endmodule |
module DiffCheck
(
input clock,
input [23:0] rgb1,
input [23:0] rgb2,
output reg result
);
reg [7:0] r, g, b, r_q, g_q, b_q;
reg [8:0] t, gx, u, t_q, gx_q;
reg [9:0] y, v;
// if y is inside (-96..96)
reg y_inside, u_inside, v_inside;
always_ff @(posedge clock) begin
// stage 1
r <= rgb1[7:1] - rgb2[7:1];
g <= rgb1[15:9] - rgb2[15:9];
b <= rgb1[23:17] - rgb2[23:17];
// stage 2
t <= $signed(r) + $signed(b);
gx <= { g[7], g };
{ r_q, g_q, b_q } <= { r, g, b };
// stage 3
y <= $signed(t) + $signed(gx);
u <= $signed(r_q) - $signed(b_q);
v <= $signed({g_q, 1'b0}) - $signed(t);
// stage 4
// if y is inside (-96..96)
y_inside <= (y < 10'h60 || y >= 10'h3a0);
// if u is inside (-16, 16)
u_inside <= (u < 9'h10 || u >= 9'h1f0);
// if v is inside (-24, 24)
v_inside <= (v < 10'h18 || v >= 10'h3e8);
// stage 5
result <= !(y_inside && u_inside && v_inside);
end
endmodule |
module InnerBlend
(
input clock,
input [8:0] Op,
input [7:0] A,
input [7:0] B,
input [7:0] C,
output reg [7:0] O
);
function [10:0] mul8x3;
input [7:0] op1;
input [2:0] op2;
begin
mul8x3 = 11'd0;
if(op2[0]) mul8x3 = mul8x3 + op1;
if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
end
endfunction
reg OpOnes;
reg [10:0] Amul, Bmul, Cmul;
reg [10:0] At, Bt, Ct;
reg [11:0] Res;
reg [8:0] Op_q, Op_q_q, Op_q_q_q, Op_q_q_q_q;
reg [7:0] A_q, A_q_q, A_q_q_q, A_q_q_q_q, B_q, B_q_q, C_q, C_q_q;
always_ff @(posedge clock) begin
// stage 1
{ Op_q, A_q, B_q, C_q } <= { Op, A, B, C };
// stage 2
OpOnes <= Op_q[4];
Amul <= mul8x3(A_q, Op_q[7:5]);
Bmul <= mul8x3(B_q, {Op_q[3:2], 1'b0});
Cmul <= mul8x3(C_q, {Op_q[1:0], 1'b0});
{ Op_q_q, A_q_q, B_q_q, C_q_q } <= { Op_q, A_q, B_q, C_q };
// stage 3
At <= Amul;
Bt <= (OpOnes == 0) ? Bmul : {3'b0, B_q_q};
Ct <= (OpOnes == 0) ? Cmul : {3'b0, C_q_q};
{ Op_q_q_q, A_q_q_q } <= { Op_q_q, A_q_q };
// stage 4
Res <= {At, 1'b0} + Bt + Ct;
{ Op_q_q_q_q, A_q_q_q_q } <= { Op_q_q_q, A_q_q_q };
// stage 5
O <= Op_q_q_q_q[8] ? A_q_q_q_q : Res[11:4];
end
endmodule |
module Blend
(
input clock,
input [5:0] rule,
input disable_hq2x,
input [23:0] E,
input [23:0] A,
input [23:0] B,
input [23:0] D,
input [23:0] F,
input [23:0] H,
output reg [23:0] Result
);
reg [23:0] E_reg, A_reg, B_reg, D_reg, F_reg, H_reg;
reg [23:0] E_reg_d, A_reg_d, B_reg_d, D_reg_d, F_reg_q, H_reg_d;
reg [23:0] Input1, Input2, Input3;
reg [23:0] res_out, res_out_q, res_out_q_q, res_out_q_q_q, res_out_q_q_q_q;
reg [1:0] input_ctrl;
reg [8:0] op, op_q;
reg [5:0] rule_reg, rule_1, rule_2, rule_3, rule_d;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(clock, rule_reg[1] ? B_reg : H_reg, rule_reg[0] ? D_reg : F_reg, is_diff);
delayline #(
.WIDTH(6*24),
.CYCLES(5)
) delay1 (
.clock(clock),
.in({ E_reg, A_reg, B_reg, D_reg, F_reg, H_reg }),
.out({ E_reg_d, A_reg_d, B_reg_d, D_reg_d, F_reg_q, H_reg_d })
);
delayline #(
.WIDTH(6),
.CYCLES(4)
) delay2 (
.clock(clock),
.in(rule_reg),
.out(rule_d)
);
always_ff @(posedge clock) begin
{ rule_reg, E_reg, A_reg, B_reg, D_reg, F_reg, H_reg } <= { rule, E, A, B, D, F, H };
case({!is_diff, rule_d[5:2]})
1,17: {op, input_ctrl} <= {BLEND1, AB};
2,18: {op, input_ctrl} <= {BLEND1, DB};
3,19: {op, input_ctrl} <= {BLEND1, BD};
4,20: {op, input_ctrl} <= {BLEND2, DB};
5,21: {op, input_ctrl} <= {BLEND2, AB};
6,22: {op, input_ctrl} <= {BLEND2, AD};
8: {op, input_ctrl} <= {BLEND0, 2'bxx};
9: {op, input_ctrl} <= {BLEND0, 2'bxx};
10: {op, input_ctrl} <= {BLEND0, 2'bxx};
11: {op, input_ctrl} <= {BLEND1, AB};
12: {op, input_ctrl} <= {BLEND1, AB};
13: {op, input_ctrl} <= {BLEND1, AB};
14: {op, input_ctrl} <= {BLEND1, DB};
15: {op, input_ctrl} <= {BLEND1, BD};
24: {op, input_ctrl} <= {BLEND2, DB};
25: {op, input_ctrl} <= {BLEND5, DB};
26: {op, input_ctrl} <= {BLEND6, DB};
27: {op, input_ctrl} <= {BLEND2, DB};
28: {op, input_ctrl} <= {BLEND4, DB};
29: {op, input_ctrl} <= {BLEND5, DB};
30: {op, input_ctrl} <= {BLEND3, BD};
31: {op, input_ctrl} <= {BLEND3, DB};
default: {op, input_ctrl} <= {11{1'bx}};
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] <= 1;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
InnerBlend inner_blend1(clock, op_q, Input1[7:0], Input2[7:0], Input3[7:0], res_out[7:0]);
InnerBlend inner_blend2(clock, op_q, Input1[15:8], Input2[15:8], Input3[15:8], res_out[15:8]);
InnerBlend inner_blend3(clock, op_q, Input1[23:16], Input2[23:16], Input3[23:16], res_out[23:16]);
always_ff @(posedge clock) begin
op_q <= op;
Input1 <= E_reg_d;
Input2 <= !input_ctrl[1] ? A_reg_d :
!input_ctrl[0] ? D_reg_d : B_reg_d;
Input3 <= !input_ctrl[0] ? B_reg_d : D_reg_d;
{ Result, res_out_q_q_q_q, res_out_q_q_q, res_out_q_q, res_out_q } <= { res_out_q_q_q_q, res_out_q_q_q, res_out_q_q, res_out_q, res_out };
end
endmodule |
module testbench();
supply0 vss;
supply1 vdd;
// Skeleton
initial
begin
$dumpfile("waveform.vcd");
$dumpvars(0, testbench);
#(1000)
$finish;
end
// Stimulus
reg a,b;
initial
begin
#100 a = 0; b = 0 ;
#100 a = 0; b = 1 ;
#100 a = 1; b = 0 ;
#100 a = 1; b = 1 ;
end
// DUT
defparam dut.NMODEL = "nmos";
defparam dut.PMODEL = "pmos";
defparam dut.W = {0,1,2,3};
defparam dut.L = {0,1,2,3};
defparam dut.M = {0,1,2,3};
defparam dut.NF = {0,1,2,3};
oh_nor2 dut (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.vdd (vdd),
.vss (vss),
.a (a),
.b (b));
endmodule // top |
module testbench();
supply0 vss;
supply1 vdd;
// Skeleton
initial
begin
$dumpfile("waveform.vcd");
$dumpvars(0, testbench);
#(1000)
$finish;
end
// Stimulus
reg a,b;
initial
begin
#100 a = 0; b = 0 ;
#100 a = 0; b = 1 ;
#100 a = 1; b = 0 ;
#100 a = 1; b = 1 ;
end
// DUT
oh_nand2 #(.SIM("switch"),
.NMODEL("nmos"),
.PMODEL("pmos"),
.W({0,1,2,3}),
.L({4,5,6,7}),
.M({8,9,10,11}),
.NF({12,13,14,15}))
dut (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.vdd (vdd),
.vss (vss),
.a (a),
.b (b));
endmodule // top |
module oh_pmos #(parameter MODEL = "pmos",
parameter W = "0",
parameter L = "0",
parameter M = "0",
parameter NF = "0"
)
(
input bulk,
input g,
input s,
inout d
);
//out,in,ctrlr
pmos p (d,s,g);
// Debug information
`ifdef OH_DEBUG
initial
begin
$display("inst=%m model=%s w=%0d l=%0d m=%0d nf=%0d",
MODEL,W,L,M,NF);
end
`endif
endmodule |
module oh_nmos #(parameter MODEL = "nmos",
parameter W = "0",
parameter L = "0",
parameter M = "0",
parameter NF = "0"
)
(
input bulk,
input g,
input s,
inout d
);
// Primitive Device
nmos n (d, s, g);
// Debug information
`ifdef OH_DEBUG
initial
begin
$display("inst=%m model=%s w=%0d l=%0d m=%0d nf=%0d",
MODEL,W,L,M,NF);
end
`endif
endmodule |
module vector_muladd(
clk,
rst,
op_din_en,
op_din_eop,
op_din,
op_weight,
op_bias,
op_dout
);
//========================================
//parameter define
//========================================
parameter CPF = 4;
parameter RELU = 0;
parameter Q = 8;
parameter DIN_Q = 6;
parameter DOUT_Q = 6;
parameter ACC_WIDTH = 40;
parameter BIAS_DW = 16;
parameter BN = 0;
parameter BN_SCALE_Q = 13;
parameter BN_BIAS_Q = 13;
parameter MID_Q = 13;
parameter DIN_DW = 16;
parameter DOUT_DW = 8; //bit-width of output
parameter WW = 16; //bit-width of weight
parameter MAT_DW = 32;
parameter DELTA_DELAY = 0;
parameter DATA_CHANNEL = 1; // when using 8bit, set to 2
//========================================
//input/output declare
//========================================
input clk;
input rst;
input op_din_en;
input op_din_eop;
input [DIN_DW*CPF-1:0] op_din;
input [WW*DATA_CHANNEL*CPF-1:0] op_weight;
input [BIAS_DW*DATA_CHANNEL-1:0] op_bias;
output [DOUT_DW*DATA_CHANNEL-1:0] op_dout;
wire [MAT_DW-1:0] mul[CPF-1:0];
//========================================
// Multiplier for 1bit/2bit/8bit/16bit
//========================================
genvar gv_i;
generate
for ( gv_i = 0; gv_i < CPF; gv_i = gv_i +1 ) begin: gen_multiplier
multiplier #(.C_WIDTH(DATA_CHANNEL),.D_WIDTH(DIN_DW),.W_WIDTH(WW*DATA_CHANNEL),.M_WIDTH(MAT_DW)) u_mult(
.clk(clk),
.d_i(op_din[DIN_DW*(gv_i+1)-1:DIN_DW*gv_i]),
.w_i(op_weight[WW*DATA_CHANNEL*(gv_i+1)-1:WW*DATA_CHANNEL*gv_i]),
.m_o(mul[gv_i])
);
end
endgenerate
//reg the bais in the end.
reg [BIAS_DW*DATA_CHANNEL-1:0] op_bias_d1;
always @ (posedge clk)
begin
if(rst)
op_bias_d1 <= {(BIAS_DW*DATA_CHANNEL){1'b0}};
else if (op_din_eop)
op_bias_d1 <= op_bias;
else
op_bias_d1 <= op_bias_d1;
end
//========================================
//delay op_din_en N clock
//========================================
wire op_din_en_d1;
delay #((CPF <2)?1:((CPF < 8)?2:((CPF < 32)?3:4)))u_delay_1(
.clk(clk),
.rst(rst),
.in(op_din_en),
.out(op_din_en_d1)
);
//========================================
//delay op_din_eop N+1 clock
//========================================
wire op_din_eop_d2;
delay #((CPF <2)?2:((CPF < 8)?3:((CPF < 32)?4:5)))u_delay_2(
.clk(clk),
.rst(rst),
.in(op_din_eop),
.out(op_din_eop_d2)
);
wire [ACC_WIDTH-1:0] a2_tmp;
wire [BIAS_DW-1:0] bias_tmp;
//========================================
// accumulator
//========================================
generate
if (DIN_DW == 8 && WW == 8) begin: gen_adder_8b
wire [MAT_DW/2-1:0] mul0[CPF-1:0];
wire [MAT_DW/2-1:0] mul1[CPF-1:0];
wire [ACC_WIDTH-1:0] a2_tmp_0;
wire [ACC_WIDTH-1:0] a2_tmp_1;
for ( gv_i = 0; gv_i < CPF; gv_i = gv_i +1 ) begin: gen_mul_8
assign mul0[gv_i] = mul[gv_i][MAT_DW/2-1:0];
assign mul1[gv_i] = mul[gv_i][MAT_DW-1:MAT_DW/2];
end
acc_addr #(.CPF(CPF),.M_DW(MAT_DW/2),.ACC_WIDTH(ACC_WIDTH)) u_acc_addr0(
.clk(clk),
.rst(rst),
.mul(mul0),
.op_din_eop_d2(op_din_eop_d2),
.op_din_en_d1(op_din_en_d1),
.a_o(a2_tmp_0));
acc_addr #(.CPF(CPF),.M_DW(MAT_DW/2),.ACC_WIDTH(ACC_WIDTH)) u_acc_addr1(
.clk(clk),
.rst(rst),
.mul(mul1),
.op_din_eop_d2(op_din_eop_d2),
.op_din_en_d1(op_din_en_d1),
.a_o(a2_tmp_1));
//reg the last accumulated data for multiplexing
reg[2*ACC_WIDTH-1:0] a2_tmp_reg;
always @ (posedge clk)
begin
if(rst)
a2_tmp_reg <= {(2*ACC_WIDTH){1'b0}};
else if (op_din_eop_d2 == 1'b1)
a2_tmp_reg <= {a2_tmp_1, a2_tmp_0};
end
reg a2_tmp_sel;
always @ (posedge clk)
begin
if(rst)
a2_tmp_sel <= 1'b0;
else if (op_din_eop_d2 == 1'b1)
a2_tmp_sel <= 1'b0;
else
a2_tmp_sel <= ~a2_tmp_sel;
end
assign a2_tmp = a2_tmp_sel ? a2_tmp_reg[2*ACC_WIDTH-1:ACC_WIDTH] : a2_tmp_reg[ACC_WIDTH-1:0];
assign bias_tmp = a2_tmp_sel ? op_bias_d1[2*BIAS_DW-1:BIAS_DW] : op_bias_d1[BIAS_DW-1:0];
end
else begin: gen_adder_16b // 16 bit
acc_addr #(.CPF(CPF),.M_DW(MAT_DW),.ACC_WIDTH(ACC_WIDTH)) u_acc_addr0(
.clk(clk),
.rst(rst),
.mul(mul),
.op_din_eop_d2(op_din_eop_d2),
.op_din_en_d1(op_din_en_d1),
.a_o(a2_tmp));
assign bias_tmp = op_bias_d1;
end
endgenerate
wire [DOUT_DW-1:0] op_dout_tmp;
bn_bias_relu #(
.RELU(RELU),
.Q(Q),
.DIN_Q(DIN_Q),
.DOUT_DW(DOUT_DW),
.DOUT_Q(DOUT_Q),
.ACC_WIDTH(ACC_WIDTH),
.BIAS_DW(BIAS_DW),
.BN(BN),
.BN_SCALE_Q(BN_SCALE_Q),
.BN_BIAS_Q(BN_BIAS_Q),
.MID_Q(MID_Q)
) u_bn_bias_relu (
.clk(clk),
.rst(rst),
.acc_in(a2_tmp),
.op_bias(bias_tmp),
.op_dout(op_dout_tmp)
);
generate
if (DIN_DW == 8 && WW == 8) begin: gen_out_8bits
reg [DOUT_DW-1:0] op_dout_reg;
always @ (posedge clk)
begin
if(rst)
op_dout_reg <= {(DOUT_DW){1'b0}};
else
op_dout_reg <= op_dout_tmp;
end
assign op_dout = {op_dout_tmp, op_dout_reg};
end
else begin:gen_out
assign op_dout = op_dout_tmp;
end
endgenerate
endmodule |
module SysPLL_inferred(
// Clock in ports
input CLK_IN,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED
);
assign CLK_OUT1 = CLK_IN;
assign CLK_OUT2 = CLK_IN;
assign LOCKED = ~RESET;
endmodule |
module SysPLL_kc705
(
input i_clk_tcxo,
output o_clk_sys,
output o_clk_ddr,
input i_reset,
output o_locked
);
// Input buffering
//------------------------------------
wire i_clk_tcxo_clk_wiz_0;
wire clk_in2_clk_wiz_0;
assign i_clk_tcxo_clk_wiz_0 = i_clk_tcxo;
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire o_clk_sys_clk_wiz_0;
wire o_clk_ddr_clk_wiz_0;
wire clk_out3_clk_wiz_0;
wire clk_out4_clk_wiz_0;
wire clk_out5_clk_wiz_0;
wire clk_out6_clk_wiz_0;
wire clk_out7_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (5.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (25.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (5),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.000))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (o_clk_sys_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (o_clk_ddr_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (i_clk_tcxo_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = i_reset;
assign o_locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (o_clk_sys),
.I (o_clk_sys_clk_wiz_0));
BUFG clkout2_buf
(.O (o_clk_ddr),
.I (o_clk_ddr_clk_wiz_0));
endmodule |
module tb_sim();
// -----------------------------
// simulation setting
// -----------------------------
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#20000
$finish();
end
localparam RATE = 1000.0/300.0;
// localparam RATE = 1000.0/250.0;
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#1000000
$finish;
end
// ---------------------------------
// clock & reset
// ---------------------------------
localparam RATE = 1000.0/100.00;
logic reset = 1;
initial #100 reset = 0;
logic clk = 1'b1;
always #(RATE/2.0) clk <= ~clk;
// ---------------------------------
// main
// ---------------------------------
tb_main
i_tb_main
(
.reset,
.clk
);
endmodule |
module tb_sim();
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(1, tb_sim);
#10000
$finish;
end
// ---------------------------------
// clock & reset
// ---------------------------------
localparam CLK_RATE = 1000.0/100.00;
reg reset = 1;
initial #100 reset = 0;
reg clk = 1'b1;
always #(CLK_RATE/2.0) clk <= ~clk;
// ---------------------------------
// main
// ---------------------------------
tb_main
i_tb_main
(
.reset,
.clk
);
endmodule |
module tb_top();
initial begin
$dumpfile("tb_top.vcd");
$dumpvars(0, tb_top);
#100000;
$finish;
end
localparam RATE = 1000.0/200.0;
logic clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
logic reset = 1'b1;
initial #(RATE*100) reset = 1'b0;
tb_main
u_tb_main
(
.reset ,
.clk
);
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#(RATE*100);
#(20000*100)
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_main
#(
.DEVICE ("ULTRASCALE")
)
i_main
(
.reset,
.clk
);
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#1000000
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_main
i_main
(
.reset,
.clk
);
/*
logic [1:0] a;
logic [1:0] b;
logic [1:0] c;
logic [1:0] d0;
logic [1:0] d1;
logic msb_carry;
logic carry;
logic overflow;
logic zero;
logic negative;
logic my_eq ;
logic my_ne ;
logic my_lt ;
logic my_ge ;
logic my_ltu;
logic my_geu;
logic exp_eq ;
logic exp_ne ;
logic exp_lt ;
logic exp_ge ;
logic exp_ltu;
logic exp_geu;
initial begin
for (int i = 0; i < 4; ++i ) begin
for (int j = 0; j < 4; ++j ) begin
a = i[1:0];
b = j[1:0];
d0 = a;
d1 = ~b;
{msb_carry, c[0:0]} = {1'b0, d0[0:0]} + {1'b0, d1[0:0]} + 1'b1;
{carry, c[1]} = {1'b0, d0[1]} + {1'b0, d1[1]} + msb_carry;
overflow = (msb_carry != carry);
zero = (c == '0);
negative = c[1];
my_eq = zero;
my_ne = !zero;
my_lt = (overflow != negative);
my_ge = (overflow == negative);
my_ltu = !carry;
my_geu = carry;
exp_eq = ( $signed(a) == $signed(b));
exp_ne = ( $signed(a) != $signed(b));
exp_lt = ( $signed(a) < $signed(b));
exp_ge = ( $signed(a) >= $signed(b));
exp_ltu = ($unsigned(a) < $unsigned(b));
exp_geu = ($unsigned(a) >= $unsigned(b));
$display("%b-%b=%b carry=%b overflow=%b zero=%b, negative=%b", i[1:0], j[1:0], c, carry, overflow, zero, negative);
$display(" eq = %b %b", exp_eq , my_eq );
$display(" ne = %b %b", exp_ne , my_ne );
$display(" lt = %b %b", exp_lt , my_lt );
$display(" ge = %b %b", exp_ge , my_ge );
$display(" ltu = %b %b", exp_ltu, my_ltu );
$display(" geu = %b %b", exp_geu, my_geu );
end
end
$finish;
end
*/
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#2000000
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_sim_main
i_sim_main
(
.reset,
.clk
);
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#10000
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
localparam RATE = 1000.0 / 100.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
// $dumpvars(3, tb_sim);
#1000000;
$finish;
end
reg reset = 1'b1;
initial #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------------------
// main
// -----------------------------------------
tb_main
i_tb_main
(
.reset,
.clk
);
endmodule |
module tb_sim();
localparam RATE = 1000.0/250.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#10000000;
$finish;
end
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE*100.5) reset = 1'b0;
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_main
(
input wire reset,
input wire clk
);
parameter USER_WIDTH = 0;
parameter DATA_WIDTH = 8;
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1;
logic cke = 1'b1;
logic s_img_row_first;
logic s_img_row_last;
logic s_img_col_first;
logic s_img_col_last;
logic s_img_de;
logic [USER_BITS-1:0] s_img_user;
logic [DATA_WIDTH-1:0] s_img_r;
logic [DATA_WIDTH-1:0] s_img_g;
logic [DATA_WIDTH-1:0] s_img_b;
logic s_img_valid;
logic m_img_row_first;
logic m_img_row_last;
logic m_img_col_first;
logic m_img_col_last;
logic m_img_de;
logic [USER_BITS-1:0] m_img_user;
logic [DATA_WIDTH-1:0] m_img_h;
logic [DATA_WIDTH-1:0] m_img_s;
logic [DATA_WIDTH-1:0] m_img_v;
logic m_img_valid;
jelly2_img_rgb2hsv
#(
.USER_WIDTH (USER_WIDTH),
.DATA_WIDTH (DATA_WIDTH)
)
i_img_rgb2hsv
(
.reset,
.clk,
.cke,
.s_img_row_first,
.s_img_row_last,
.s_img_col_first,
.s_img_col_last,
.s_img_de,
.s_img_user,
.s_img_r,
.s_img_g,
.s_img_b,
.s_img_valid,
.m_img_row_first,
.m_img_row_last,
.m_img_col_first,
.m_img_col_last,
.m_img_de,
.m_img_user,
.m_img_h,
.m_img_s,
.m_img_v,
.m_img_valid
);
jelly2_img_master_model
#(
.COMPONENTS (3),
.DATA_WIDTH (8),
.X_NUM (256),
.Y_NUM (256),
.X_BLANK (0), // 基本ゼロ
.Y_BLANK (0), // 末尾にde落ちラインを追加
.X_WIDTH (32),
.Y_WIDTH (32),
.F_WIDTH (32),
// .FILE_NAME ("../../../../data/color/Parrots.ppm"),
.FILE_NAME ("../../../../data/col_ptn.ppm"),
.FILE_EXT (""),
.SEQUENTIAL_FILE (0),
.ENDIAN (0)
)
i_img_master_model
(
.reset,
.clk,
.cke,
.enable (1'b1),
.busy (),
.m_img_row_first (s_img_row_first),
.m_img_row_last (s_img_row_last),
.m_img_col_first (s_img_col_first),
.m_img_col_last (s_img_col_last),
.m_img_de (s_img_de),
.m_img_data ({s_img_r, s_img_g, s_img_b}),
.m_img_x (),
.m_img_y (),
.m_img_f (),
.m_img_valid (s_img_valid)
);
jelly2_img_slave_model
#(
.COMPONENTS (3),
.DATA_WIDTH (8),
.INIT_FRAME_NUM (0),
.X_WIDTH (32),
.Y_WIDTH (32),
.F_WIDTH (32),
.FORMAT ("P3"),
.FILE_NAME ("img_"),
.FILE_EXT (".ppm"),
.SEQUENTIAL_FILE (1),
.ENDIAN (0)
)
i_img_slave_model
(
.reset,
.clk,
.cke,
.param_width (256),
.param_height (256),
.frame_num (),
.s_img_row_first (m_img_row_first),
.s_img_row_last (m_img_row_last),
.s_img_col_first (m_img_col_first),
.s_img_col_last (m_img_col_last),
.s_img_de (m_img_de),
.s_img_data ({m_img_h, m_img_s, m_img_v}),
.s_img_valid (m_img_valid)
);
endmodule |
module tb_sim();
// -----------------------------
// simulation setting
// -----------------------------
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#2000000
$finish();
end
localparam RATE = 10.0;
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
tb_main
i_tb_main
(
.aresetn (~reset),
.aclk (clk)
);
endmodule |
module tb_sim();
localparam RATE = 1000.0/200.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#1000000
$finish;
end
logic reset = 1'b1;
initial #(RATE*10) reset <= 1'b0;
logic clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// ----------------------------------
// main
// ----------------------------------
tb_sim_main
i_sim_main
(
.*
);
/*
// ----------------------------------
// WISHBONE master
// ----------------------------------
localparam WB_DAT_SIZE = 3;
localparam WB_ADR_WIDTH = 40 - WB_DAT_SIZE;
localparam WB_DAT_WIDTH = (8 << WB_DAT_SIZE);
localparam WB_SEL_WIDTH = (1 << WB_DAT_SIZE);
// force connect to top-net
wire wb_rst_i = i_top.wb_peri_rst_i;
wire wb_clk_i = i_top.wb_peri_clk_i;
reg [WB_ADR_WIDTH-1:0] wb_adr_o;
wire [WB_DAT_WIDTH-1:0] wb_dat_i = i_top.wb_peri_dat_o;
reg [WB_DAT_WIDTH-1:0] wb_dat_o;
reg wb_we_o;
reg [WB_SEL_WIDTH-1:0] wb_sel_o;
reg wb_stb_o = 0;
wire wb_ack_i = i_top.wb_peri_ack_o;
initial begin
force i_top.wb_peri_adr_i = wb_adr_o;
force i_top.wb_peri_dat_i = wb_dat_o;
force i_top.wb_peri_we_i = wb_we_o;
force i_top.wb_peri_sel_i = wb_sel_o;
force i_top.wb_peri_stb_i = wb_stb_o;
end
reg [WB_DAT_WIDTH-1:0] reg_wb_dat;
reg reg_wb_ack;
always_ff @(posedge wb_clk_i) begin
if ( ~wb_we_o & wb_stb_o & wb_ack_i ) begin
reg_wb_dat <= wb_dat_i;
end
reg_wb_ack <= wb_ack_i;
end
task wb_write(
input [WB_ADR_WIDTH-1:0] adr,
input [WB_DAT_WIDTH-1:0] dat,
input [WB_SEL_WIDTH-1:0] sel
);
begin
$display("WISHBONE_WRITE(adr:%h dat:%h sel:%b)", adr, dat, sel);
@(negedge wb_clk_i);
wb_adr_o = adr;
wb_dat_o = dat;
wb_sel_o = sel;
wb_we_o = 1'b1;
wb_stb_o = 1'b1;
@(negedge wb_clk_i);
while ( reg_wb_ack == 1'b0 ) begin
@(negedge wb_clk_i);
end
wb_adr_o = {WB_ADR_WIDTH{1'bx}};
wb_dat_o = {WB_DAT_WIDTH{1'bx}};
wb_sel_o = {WB_SEL_WIDTH{1'bx}};
wb_we_o = 1'bx;
wb_stb_o = 1'b0;
end
endtask
task wb_read(
input [WB_ADR_WIDTH-1:0] adr
);
begin
@(negedge wb_clk_i);
wb_adr_o = adr;
wb_dat_o = {WB_DAT_WIDTH{1'bx}};
wb_sel_o = {WB_SEL_WIDTH{1'b1}};
wb_we_o = 1'b0;
wb_stb_o = 1'b1;
@(negedge wb_clk_i);
while ( reg_wb_ack == 1'b0 ) begin
@(negedge wb_clk_i);
end
wb_adr_o = {WB_ADR_WIDTH{1'bx}};
wb_dat_o = {WB_DAT_WIDTH{1'bx}};
wb_sel_o = {WB_SEL_WIDTH{1'bx}};
wb_we_o = 1'bx;
wb_stb_o = 1'b0;
$display("WISHBONE_READ(adr:%h dat:%h)", adr, reg_wb_dat);
end
endtask
// ----------------------------------
// Simulation
// ----------------------------------
localparam ADR_DMA0 = 32'h000000;
localparam ADR_DMA1 = 32'h000100;
localparam ADR_LED = 32'h001000;
localparam ADR_TIM = 32'h002000;
localparam REG_DMA_STATUS = 0;
localparam REG_DMA_WSTART = 1;
localparam REG_DMA_RSTART = 2;
localparam REG_DMA_ADDR = 3;
localparam REG_DMA_WDATA0 = 4;
localparam REG_DMA_WDATA1 = 5;
localparam REG_DMA_RDATA0 = 6;
localparam REG_DMA_RDATA1 = 7;
localparam REG_DMA_ID = 8;
localparam REG_TIM_CONTROL = 2'b00;
localparam REG_TIM_COMPARE = 2'b01;
localparam REG_TIM_COUNTER = 2'b11;
initial begin
@(negedge wb_rst_i);
#10000;
$display(" --- dma0 --- ");
wb_read (ADR_DMA0 + REG_DMA_ID); // CORE_ID
$display(" --- dma1 --- ");
wb_read (ADR_DMA1 + REG_DMA_ID); // CORE_ID
wb_read (ADR_DMA1 + REG_DMA_WDATA0);
wb_write(ADR_DMA1 + REG_DMA_WDATA0, 64'h0123456789abcdef, 8'h0f);
wb_read (ADR_DMA1 + REG_DMA_WDATA0);
wb_write(ADR_DMA1 + REG_DMA_WDATA0, 64'h01234567FFFFFFFF, 8'hf0);
wb_read (ADR_DMA1 + REG_DMA_WDATA0);
$display("write start");
wb_write(ADR_DMA1 + REG_DMA_WDATA0, 64'h0123456789abcdef, 8'hff);
wb_write(ADR_DMA1 + REG_DMA_WDATA1, 64'hfedcba9876543210, 8'hff);
wb_write(ADR_DMA1 + REG_DMA_ADDR, 64'h0000_0100, 8'hff);
wb_write(ADR_DMA1 + REG_DMA_WSTART, 64'h0000_0001, 8'hff);
#10000;
wb_write(ADR_DMA0 + REG_DMA_ADDR, 64'h0000_0100, 8'hff);
wb_write(ADR_DMA0 + REG_DMA_RSTART, 64'h0000_0001, 8'hff);
wb_read (ADR_DMA0 + REG_DMA_STATUS);
#10000;
wb_read (ADR_DMA0 + REG_DMA_STATUS);
wb_read (ADR_DMA0 + REG_DMA_RDATA0);
wb_read (ADR_DMA0 + REG_DMA_RDATA1);
#10000;
$display(" --- led --- ");
wb_read (ADR_LED);
wb_write(ADR_LED, 1, 8'hff);
#10000;
wb_write(ADR_LED, 0, 8'hff);
#10000;
$display(" --- timer --- ");
wb_write(ADR_TIM + REG_TIM_COMPARE, 1000-1, 8'hff);
wb_write(ADR_TIM + REG_TIM_CONTROL, 1000-1, 8'hff);
#11000;
wb_read (ADR_TIM + REG_TIM_CONTROL); // clear
#10000;
wb_read (ADR_TIM + REG_TIM_CONTROL); // clear
#10000;
$finish();
end
*/
endmodule |
module tb_sim();
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#1000000
$finish;
end
// ---------------------------------
// clock & reset
// ---------------------------------
localparam RATE27 = 27.0/100.00;
localparam RATE126 = 126.0/200.00;
localparam RATE25 = 5*126.0/250.00;
reg in_reset_n = 1'b0;
initial #100 in_reset_n = 1'b1;
reg in_clk = 1'b1;
always #(RATE27/2.0) in_clk <= ~in_clk;
reg clk = 1'b1;
always #(RATE25/2.0) clk <= ~clk;
reg clk_x5 = 1'b1;
always #(RATE126/2.0) clk_x5 <= ~clk_x5;
// ---------------------------------
// main
// ---------------------------------
tb_main
i_tb_main
(
.in_reset_n,
.in_clk,
.clk,
.clk_x5
);
endmodule |
module image_processing
#(
parameter WB_ADR_WIDTH = 17,
parameter WB_DAT_WIDTH = 32,
parameter WB_SEL_WIDTH = (WB_DAT_WIDTH / 8),
parameter AXI4_ID_WIDTH = 6,
parameter AXI4_ADDR_WIDTH = 32,
parameter AXI4_DATA_SIZE = 3, // 0:8bit, 1:16bit, 2:32bit ...
parameter AXI4_DATA_WIDTH = (8 << AXI4_DATA_SIZE),
parameter AXI4_STRB_WIDTH = AXI4_DATA_WIDTH / 8,
parameter AXI4_LEN_WIDTH = 8,
parameter AXI4_QOS_WIDTH = 4,
parameter S_DATA_WIDTH = 10,
parameter M_DATA_WIDTH = 8,
parameter MAX_X_NUM = 4096,
parameter IMG_Y_NUM = 480,
parameter IMG_Y_WIDTH = 14,
parameter TUSER_WIDTH = 1,
parameter S_TDATA_WIDTH = 1*S_DATA_WIDTH,
parameter M_TDATA_WIDTH = 4*M_DATA_WIDTH
)
(
input wire aresetn,
input wire aclk,
input wire in_update_req,
input wire s_wb_rst_i,
input wire s_wb_clk_i,
input wire [WB_ADR_WIDTH-1:0] s_wb_adr_i,
input wire [WB_DAT_WIDTH-1:0] s_wb_dat_i,
output wire [WB_DAT_WIDTH-1:0] s_wb_dat_o,
input wire s_wb_we_i,
input wire [WB_SEL_WIDTH-1:0] s_wb_sel_i,
input wire s_wb_stb_i,
output wire s_wb_ack_o,
input wire [TUSER_WIDTH-1:0] s_axi4s_tuser,
input wire s_axi4s_tlast,
input wire [S_TDATA_WIDTH-1:0] s_axi4s_tdata,
input wire s_axi4s_tvalid,
output wire s_axi4s_tready,
output wire [TUSER_WIDTH-1:0] m_axi4s_tuser,
output wire m_axi4s_tlast,
output wire [M_TDATA_WIDTH-1:0] m_axi4s_tdata,
output wire m_axi4s_tvalid,
input wire m_axi4s_tready,
input wire m_axi4_aresetn,
input wire m_axi4_aclk,
output wire [AXI4_ID_WIDTH-1:0] m_axi4_awid,
output wire [AXI4_ADDR_WIDTH-1:0] m_axi4_awaddr,
output wire [AXI4_LEN_WIDTH-1:0] m_axi4_awlen,
output wire [2:0] m_axi4_awsize,
output wire [1:0] m_axi4_awburst,
output wire [0:0] m_axi4_awlock,
output wire [3:0] m_axi4_awcache,
output wire [2:0] m_axi4_awprot,
output wire [AXI4_QOS_WIDTH-1:0] m_axi4_awqos,
output wire [3:0] m_axi4_awregion,
output wire m_axi4_awvalid,
input wire m_axi4_awready,
output wire [AXI4_DATA_WIDTH-1:0] m_axi4_wdata,
output wire [AXI4_STRB_WIDTH-1:0] m_axi4_wstrb,
output wire m_axi4_wlast,
output wire m_axi4_wvalid,
input wire m_axi4_wready,
input wire [AXI4_ID_WIDTH-1:0] m_axi4_bid,
input wire [1:0] m_axi4_bresp,
input wire m_axi4_bvalid,
output wire m_axi4_bready,
output wire [AXI4_ID_WIDTH-1:0] m_axi4_arid,
output wire [AXI4_ADDR_WIDTH-1:0] m_axi4_araddr,
output wire [AXI4_LEN_WIDTH-1:0] m_axi4_arlen,
output wire [2:0] m_axi4_arsize,
output wire [1:0] m_axi4_arburst,
output wire [0:0] m_axi4_arlock,
output wire [3:0] m_axi4_arcache,
output wire [2:0] m_axi4_arprot,
output wire [AXI4_QOS_WIDTH-1:0] m_axi4_arqos,
output wire [3:0] m_axi4_arregion,
output wire m_axi4_arvalid,
input wire m_axi4_arready,
input wire [AXI4_ID_WIDTH-1:0] m_axi4_rid,
input wire [AXI4_DATA_WIDTH-1:0] m_axi4_rdata,
input wire [1:0] m_axi4_rresp,
input wire m_axi4_rlast,
input wire m_axi4_rvalid,
output wire m_axi4_rready
);
localparam USE_VALID = 0;
localparam USER_WIDTH = (TUSER_WIDTH - 1) >= 0 ? (TUSER_WIDTH - 1) : 0;
localparam USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1;
wire reset = ~aresetn;
wire clk = aclk;
wire cke;
wire img_src_line_first;
wire img_src_line_last;
wire img_src_pixel_first;
wire img_src_pixel_last;
wire img_src_de;
wire [USER_BITS-1:0] img_src_user;
wire [S_TDATA_WIDTH-1:0] img_src_data;
wire img_src_valid;
wire img_sink_line_first;
wire img_sink_line_last;
wire img_sink_pixel_first;
wire img_sink_pixel_last;
wire img_sink_de;
wire [USER_BITS-1:0] img_sink_user;
wire [M_TDATA_WIDTH-1:0] img_sink_data;
wire img_sink_valid;
// axi4s<->img
jelly_axi4s_img
#(
.TUSER_WIDTH (TUSER_WIDTH),
.S_TDATA_WIDTH (S_TDATA_WIDTH),
.M_TDATA_WIDTH (M_TDATA_WIDTH),
.IMG_Y_NUM (IMG_Y_NUM),
.IMG_Y_WIDTH (IMG_Y_WIDTH),
.BLANK_Y_WIDTH (8),
.IMG_CKE_BUFG (0)
)
jelly_axi4s_img
(
.reset (reset),
.clk (clk),
.param_blank_num (8'h0f),
.s_axi4s_tdata (s_axi4s_tdata),
.s_axi4s_tlast (s_axi4s_tlast),
.s_axi4s_tuser (s_axi4s_tuser),
.s_axi4s_tvalid (s_axi4s_tvalid),
.s_axi4s_tready (s_axi4s_tready),
.m_axi4s_tdata (m_axi4s_tdata),
.m_axi4s_tlast (m_axi4s_tlast),
.m_axi4s_tuser (m_axi4s_tuser),
.m_axi4s_tvalid (m_axi4s_tvalid),
.m_axi4s_tready (m_axi4s_tready),
.img_cke (cke),
.src_img_line_first (img_src_line_first),
.src_img_line_last (img_src_line_last),
.src_img_pixel_first (img_src_pixel_first),
.src_img_pixel_last (img_src_pixel_last),
.src_img_de (img_src_de),
.src_img_user (img_src_user),
.src_img_data (img_src_data),
.src_img_valid (img_src_valid),
.sink_img_line_first (img_sink_line_first),
.sink_img_line_last (img_sink_line_last),
.sink_img_pixel_first (img_sink_pixel_first),
.sink_img_pixel_last (img_sink_pixel_last),
.sink_img_user (img_sink_user),
.sink_img_de (img_sink_de),
.sink_img_data (img_sink_data),
.sink_img_valid (img_sink_valid)
);
// demosaic
wire img_demos_line_first;
wire img_demos_line_last;
wire img_demos_pixel_first;
wire img_demos_pixel_last;
wire img_demos_de;
wire [USER_BITS-1:0] img_demos_user;
wire [S_DATA_WIDTH-1:0] img_demos_raw;
wire [S_DATA_WIDTH-1:0] img_demos_r;
wire [S_DATA_WIDTH-1:0] img_demos_g;
wire [S_DATA_WIDTH-1:0] img_demos_b;
wire img_demos_valid;
wire [WB_DAT_WIDTH-1:0] wb_demos_dat_o;
wire wb_demos_stb_i;
wire wb_demos_ack_o;
jelly_img_demosaic_acpi
#(
.USER_WIDTH (USER_BITS),
.DATA_WIDTH (S_DATA_WIDTH),
.MAX_X_NUM (4096),
.RAM_TYPE ("block"),
.USE_VALID (USE_VALID),
.WB_ADR_WIDTH (6),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_PARAM_PHASE (2'b11)
)
i_img_demosaic_acpi
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_update_req (in_update_req),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[5:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_demos_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_demos_stb_i),
.s_wb_ack_o (wb_demos_ack_o),
.s_img_line_first (img_src_line_first),
.s_img_line_last (img_src_line_last),
.s_img_pixel_first (img_src_pixel_first),
.s_img_pixel_last (img_src_pixel_last),
.s_img_de (img_src_de),
.s_img_user (img_src_user),
.s_img_raw (img_src_data),
.s_img_valid (img_src_valid),
.m_img_line_first (img_demos_line_first),
.m_img_line_last (img_demos_line_last),
.m_img_pixel_first (img_demos_pixel_first),
.m_img_pixel_last (img_demos_pixel_last),
.m_img_de (img_demos_de),
.m_img_user (img_demos_user),
.m_img_raw (img_demos_raw),
.m_img_r (img_demos_r),
.m_img_g (img_demos_g),
.m_img_b (img_demos_b),
.m_img_valid (img_demos_valid)
);
// color matrix
wire img_colmat_line_first;
wire img_colmat_line_last;
wire img_colmat_pixel_first;
wire img_colmat_pixel_last;
wire img_colmat_de;
wire [USER_BITS-1:0] img_colmat_user;
wire [S_DATA_WIDTH-1:0] img_colmat_raw;
wire [S_DATA_WIDTH-1:0] img_colmat_r;
wire [S_DATA_WIDTH-1:0] img_colmat_g;
wire [S_DATA_WIDTH-1:0] img_colmat_b;
wire img_colmat_valid;
wire [WB_DAT_WIDTH-1:0] wb_colmat_dat_o;
wire wb_colmat_stb_i;
wire wb_colmat_ack_o;
jelly_img_color_matrix
#(
.USER_WIDTH (USER_BITS + S_DATA_WIDTH),
.DATA_WIDTH (S_DATA_WIDTH),
.INTERNAL_WIDTH (S_DATA_WIDTH+2),
.COEFF_INT_WIDTH (9),
.COEFF_FRAC_WIDTH (16),
.COEFF3_INT_WIDTH (9),
.COEFF3_FRAC_WIDTH (16),
.STATIC_COEFF (1),
.DEVICE ("RTL"),
.WB_ADR_WIDTH (6),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_PARAM_MATRIX00 (1 << 16),
.INIT_PARAM_MATRIX01 (0),
.INIT_PARAM_MATRIX02 (0),
.INIT_PARAM_MATRIX03 (0),
.INIT_PARAM_MATRIX10 (0),
.INIT_PARAM_MATRIX11 (1 << 16),
.INIT_PARAM_MATRIX12 (0),
.INIT_PARAM_MATRIX13 (0),
.INIT_PARAM_MATRIX20 (0),
.INIT_PARAM_MATRIX21 (0),
.INIT_PARAM_MATRIX22 (1 << 16),
.INIT_PARAM_MATRIX23 (0),
.INIT_PARAM_CLIP_MIN0 ({S_DATA_WIDTH{1'b0}}),
.INIT_PARAM_CLIP_MAX0 ({S_DATA_WIDTH{1'b1}}),
.INIT_PARAM_CLIP_MIN1 ({S_DATA_WIDTH{1'b0}}),
.INIT_PARAM_CLIP_MAX1 ({S_DATA_WIDTH{1'b1}}),
.INIT_PARAM_CLIP_MIN2 ({S_DATA_WIDTH{1'b0}}),
.INIT_PARAM_CLIP_MAX2 ({S_DATA_WIDTH{1'b1}})
)
i_img_color_matrix
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_update_req (in_update_req),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[5:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_colmat_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_colmat_stb_i),
.s_wb_ack_o (wb_colmat_ack_o),
.s_img_line_first (img_demos_line_first),
.s_img_line_last (img_demos_line_last),
.s_img_pixel_first (img_demos_pixel_first),
.s_img_pixel_last (img_demos_pixel_last),
.s_img_de (img_demos_de),
.s_img_user ({img_demos_user, img_demos_raw}),
.s_img_color0 (img_demos_r),
.s_img_color1 (img_demos_g),
.s_img_color2 (img_demos_b),
.s_img_valid (img_demos_valid),
.m_img_line_first (img_colmat_line_first),
.m_img_line_last (img_colmat_line_last),
.m_img_pixel_first (img_colmat_pixel_first),
.m_img_pixel_last (img_colmat_pixel_last),
.m_img_de (img_colmat_de),
.m_img_user ({img_colmat_user, img_colmat_raw}),
.m_img_color0 (img_colmat_r),
.m_img_color1 (img_colmat_g),
.m_img_color2 (img_colmat_b),
.m_img_valid (img_colmat_valid)
);
// gamma correction
wire img_gamma_line_first;
wire img_gamma_line_last;
wire img_gamma_pixel_first;
wire img_gamma_pixel_last;
wire img_gamma_de;
wire [USER_BITS-1:0] img_gamma_user;
wire [S_DATA_WIDTH-1:0] img_gamma_raw;
wire [3*M_DATA_WIDTH-1:0] img_gamma_data;
wire img_gamma_valid;
wire [WB_DAT_WIDTH-1:0] wb_gamma_dat_o;
wire wb_gamma_stb_i;
wire wb_gamma_ack_o;
jelly_img_gamma_correction
#(
.COMPONENTS (3),
.USER_WIDTH (USER_BITS+S_DATA_WIDTH),
.S_DATA_WIDTH (S_DATA_WIDTH),
.M_DATA_WIDTH (M_DATA_WIDTH),
.USE_VALID (USE_VALID),
.RAM_TYPE ("block"),
.WB_ADR_WIDTH (12),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_CTL_CONTROL (2'b00),
.INIT_PARAM_ENABLE (3'b000)
)
i_img_gamma_correction
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_update_req (in_update_req),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[11:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_gamma_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_gamma_stb_i),
.s_wb_ack_o (wb_gamma_ack_o),
.s_img_line_first (img_colmat_line_first),
.s_img_line_last (img_colmat_line_last),
.s_img_pixel_first (img_colmat_pixel_first),
.s_img_pixel_last (img_colmat_pixel_last),
.s_img_de (img_colmat_de),
.s_img_user ({img_colmat_user, img_colmat_raw}),
.s_img_data ({img_colmat_r, img_colmat_g, img_colmat_b}),
.s_img_valid (img_colmat_valid),
.m_img_line_first (img_gamma_line_first),
.m_img_line_last (img_gamma_line_last),
.m_img_pixel_first (img_gamma_pixel_first),
.m_img_pixel_last (img_gamma_pixel_last),
.m_img_de (img_gamma_de),
.m_img_user ({img_gamma_user, img_gamma_raw}),
.m_img_data (img_gamma_data),
.m_img_valid (img_gamma_valid)
);
// gaussian
wire img_gauss_line_first;
wire img_gauss_line_last;
wire img_gauss_pixel_first;
wire img_gauss_pixel_last;
wire img_gauss_de;
wire [USER_BITS-1:0] img_gauss_user;
wire [S_DATA_WIDTH-1:0] img_gauss_raw;
wire [3*M_DATA_WIDTH-1:0] img_gauss_data;
wire img_gauss_valid;
wire [WB_DAT_WIDTH-1:0] wb_gauss_dat_o;
wire wb_gauss_stb_i;
wire wb_gauss_ack_o;
jelly_img_gaussian_3x3
#(
.NUM (3),
.USER_WIDTH (USER_BITS+S_DATA_WIDTH),
.COMPONENTS (3),
.DATA_WIDTH (M_DATA_WIDTH),
.MAX_X_NUM (MAX_X_NUM),
.RAM_TYPE ("block"),
.USE_VALID (USE_VALID),
.WB_ADR_WIDTH (8),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_CTL_CONTROL (3'b000),
.INIT_PARAM_ENABLE (3'b000)
)
i_img_gaussian_3x3
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_update_req (in_update_req),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[7:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_gauss_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_gauss_stb_i),
.s_wb_ack_o (wb_gauss_ack_o),
.s_img_line_first (img_gamma_line_first),
.s_img_line_last (img_gamma_line_last),
.s_img_pixel_first (img_gamma_pixel_first),
.s_img_pixel_last (img_gamma_pixel_last),
.s_img_de (img_gamma_de),
.s_img_user ({img_gamma_user, img_gamma_raw}),
.s_img_data (img_gamma_data),
.s_img_valid (img_gamma_valid),
.m_img_line_first (img_gauss_line_first),
.m_img_line_last (img_gauss_line_last),
.m_img_pixel_first (img_gauss_pixel_first),
.m_img_pixel_last (img_gauss_pixel_last),
.m_img_de (img_gauss_de),
.m_img_user ({img_gauss_user, img_gauss_raw}),
.m_img_data (img_gauss_data),
.m_img_valid (img_gauss_valid)
);
// selector
localparam SEL_N = 2;
localparam SEL_U = USER_BITS;
localparam SEL_D = M_TDATA_WIDTH;
wire [SEL_N-1:0] img_sel_line_first;
wire [SEL_N-1:0] img_sel_line_last;
wire [SEL_N-1:0] img_sel_pixel_first;
wire [SEL_N-1:0] img_sel_pixel_last;
wire [SEL_N-1:0] img_sel_de;
wire [SEL_N*SEL_U-1:0] img_sel_user;
wire [SEL_N*SEL_D-1:0] img_sel_data;
wire [SEL_N-1:0] img_sel_valid;
assign img_sel_line_first [0] = img_gauss_line_first;
assign img_sel_line_last [0] = img_gauss_line_last;
assign img_sel_pixel_first[0] = img_gauss_pixel_first;
assign img_sel_pixel_last [0] = img_gauss_pixel_last;
assign img_sel_de [0] = img_gauss_de;
assign img_sel_user [0*SEL_U +: SEL_U] = img_gauss_user;
assign img_sel_data [0*SEL_D +: SEL_D] = {img_gauss_raw[S_DATA_WIDTH-1 -: M_DATA_WIDTH], img_gauss_data};
assign img_sel_valid [0] = img_gauss_valid;
assign img_sel_line_first [1] = img_src_line_first;
assign img_sel_line_last [1] = img_src_line_last;
assign img_sel_pixel_first[1] = img_src_pixel_first;
assign img_sel_pixel_last [1] = img_src_pixel_last;
assign img_sel_de [1] = img_src_de;
assign img_sel_user [1*SEL_U +: SEL_U] = img_src_user;
assign img_sel_data [1*SEL_D +: SEL_D] = {4{img_src_data[S_DATA_WIDTH-1 -: M_DATA_WIDTH]}};
assign img_sel_valid [1] = img_src_valid;
wire [WB_DAT_WIDTH-1:0] wb_sel_dat_o;
wire wb_sel_stb_i;
wire wb_sel_ack_o;
jelly_img_selector
#(
.NUM (SEL_N),
.USER_WIDTH (SEL_U),
.DATA_WIDTH (SEL_D),
.WB_ADR_WIDTH (8),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_CTL_SELECT (0)
)
i_img_selector
(
.reset (reset),
.clk (clk),
.cke (cke),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[7:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_sel_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_sel_stb_i),
.s_wb_ack_o (wb_sel_ack_o),
.s_img_line_first (img_sel_line_first),
.s_img_line_last (img_sel_line_last),
.s_img_pixel_first (img_sel_pixel_first),
.s_img_pixel_last (img_sel_pixel_last),
.s_img_de (img_sel_de),
.s_img_user (img_sel_user),
.s_img_data (img_sel_data),
.s_img_valid (img_sel_valid),
.m_img_line_first (img_sink_line_first),
.m_img_line_last (img_sink_line_last),
.m_img_pixel_first (img_sink_pixel_first),
.m_img_pixel_last (img_sink_pixel_last),
.m_img_de (img_sink_de),
.m_img_user (img_sink_user),
.m_img_data (img_sink_data),
.m_img_valid (img_sink_valid)
);
// 外部メモリは利用しない
assign m_axi4_awid = '0;
assign m_axi4_awaddr = '0;
assign m_axi4_awlen = '0;
assign m_axi4_awsize = '0;
assign m_axi4_awburst = '0;
assign m_axi4_awlock = '0;
assign m_axi4_awcache = '0;
assign m_axi4_awprot = '0;
assign m_axi4_awqos = '0;
assign m_axi4_awregion = '0;
assign m_axi4_awvalid = '0;
assign m_axi4_wdata = '0;
assign m_axi4_wstrb = '0;
assign m_axi4_wlast = '0;
assign m_axi4_wvalid = '0;
assign m_axi4_bready = '0;
assign m_axi4_arid = '0;
assign m_axi4_araddr = '0;
assign m_axi4_arlen = '0;
assign m_axi4_arsize = '0;
assign m_axi4_arburst = '0;
assign m_axi4_arlock = '0;
assign m_axi4_arcache = '0;
assign m_axi4_arprot = '0;
assign m_axi4_arqos = '0;
assign m_axi4_arregion = '0;
assign m_axi4_arvalid = '0;
assign m_axi4_rready = '0;
// WISHBONE
assign wb_demos_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'h0);
assign wb_colmat_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'h1);
assign wb_gamma_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'h2);
assign wb_gauss_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'h4);
assign wb_sel_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'hf);
assign s_wb_dat_o = wb_demos_stb_i ? wb_demos_dat_o :
wb_colmat_stb_i ? wb_colmat_dat_o :
wb_gamma_stb_i ? wb_gamma_dat_o :
wb_gauss_stb_i ? wb_gauss_dat_o :
wb_sel_stb_i ? wb_sel_dat_o :
{WB_DAT_WIDTH{1'b0}};
assign s_wb_ack_o = wb_demos_stb_i ? wb_demos_ack_o :
wb_colmat_stb_i ? wb_colmat_ack_o :
wb_gamma_stb_i ? wb_gamma_ack_o :
wb_gauss_stb_i ? wb_gauss_ack_o :
wb_sel_stb_i ? wb_sel_ack_o :
s_wb_stb_i;
endmodule |
module tb_sim_main();
wire [1:0] led;
wire imu_sck;
wire imu_sda;
ultra96v2_mpu9250
i_top
(
.led (led),
.imu_sck (imu_sck),
.imu_sda (imu_sda)
);
endmodule |
module tb_sim_main();
logic [1:0] led;
ultra96v2_rtos
i_top
(
.*
);
endmodule |
module tb_sim_main();
wire [1:0] led;
ultra96v2_hls_test
i_top
(
.led (led)
);
endmodule |
module rmii_to_pmod
(
output wire [3:0] rmii_refclk,
input wire [3:0] rmii_txen,
input wire [3:0][1:0] rmii_tx,
output wire [3:0][1:0] rmii_rx,
output wire [3:0] rmii_crs,
output wire [3:0] rmii_mdc,
input wire [3:0] rmii_mdio_t,
input wire [3:0] rmii_mdio_o,
output wire [3:0] rmii_mdio_i,
inout wire [7:0] pmod_a,
inout wire [7:0] pmod_b,
inout wire [7:0] pmod_c,
inout wire [7:0] pmod_d,
inout wire [7:0] pmod_e
);
IOBUF i_iobuf_pmod_a0 (.IO(pmod_a[0]), .I(rmii_tx [0][0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_a1 (.IO(pmod_a[1]), .I(1'b0), .O(rmii_rx [0][1]), .T(1'b1));
IOBUF i_iobuf_pmod_a2 (.IO(pmod_a[2]), .I(1'b0), .O(rmii_crs [0] ), .T(1'b1));
IOBUF i_iobuf_pmod_a3 (.IO(pmod_a[3]), .I(1'b1), .O(rmii_mdc [0] ), .T(1'b0));
IOBUF i_iobuf_pmod_a4 (.IO(pmod_a[4]), .I(rmii_txen [0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_a5 (.IO(pmod_a[5]), .I(1'b0), .O(rmii_rx [0][0]), .T(1'b1));
IOBUF i_iobuf_pmod_a6 (.IO(pmod_a[6]), .I(1'b0), .O(rmii_refclk[0]), .T(1'b1));
IOBUF i_iobuf_pmod_a7 (.IO(pmod_a[7]), .I(rmii_mdio_o[0]), .O(rmii_mdio_i[0]), .T(rmii_mdio_t[0]));
IOBUF i_iobuf_pmod_c0 (.IO(pmod_c[0]), .I(rmii_tx [0][1]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_b0 (.IO(pmod_b[0]), .I(rmii_tx [1][0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_b1 (.IO(pmod_b[1]), .I(1'b0), .O(rmii_rx [1][1]), .T(1'b1));
IOBUF i_iobuf_pmod_b2 (.IO(pmod_b[2]), .I(1'b0), .O(rmii_crs [1] ), .T(1'b1));
IOBUF i_iobuf_pmod_b3 (.IO(pmod_b[3]), .I(1'b1), .O(rmii_mdc [1] ), .T(1'b0));
IOBUF i_iobuf_pmod_b4 (.IO(pmod_b[4]), .I(rmii_txen [1]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_b5 (.IO(pmod_b[5]), .I(1'b0), .O(rmii_rx [1][0]), .T(1'b1));
IOBUF i_iobuf_pmod_b6 (.IO(pmod_b[6]), .I(1'b0), .O(rmii_refclk[1]), .T(1'b1));
IOBUF i_iobuf_pmod_b7 (.IO(pmod_b[7]), .I(rmii_mdio_o[1]), .O(rmii_mdio_i[1]), .T(rmii_mdio_t[1]));
IOBUF i_iobuf_pmod_c1 (.IO(pmod_c[1]), .I(rmii_tx [1][1]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_d0 (.IO(pmod_d[0]), .I(rmii_tx [2][0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_d1 (.IO(pmod_d[1]), .I(1'b0), .O(rmii_rx [2][1]), .T(1'b1));
IOBUF i_iobuf_pmod_d2 (.IO(pmod_d[2]), .I(1'b0), .O(rmii_crs [2] ), .T(1'b1));
IOBUF i_iobuf_pmod_d3 (.IO(pmod_d[3]), .I(1'b1), .O(rmii_mdc [2] ), .T(1'b0));
IOBUF i_iobuf_pmod_d4 (.IO(pmod_d[4]), .I(rmii_txen [2]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_d5 (.IO(pmod_d[5]), .I(1'b0), .O(rmii_rx [2][0]), .T(1'b1));
IOBUF i_iobuf_pmod_d6 (.IO(pmod_d[6]), .I(1'b0), .O(rmii_refclk[2]), .T(1'b1));
IOBUF i_iobuf_pmod_d7 (.IO(pmod_d[7]), .I(rmii_mdio_o[2]), .O(rmii_mdio_i[2]), .T(rmii_mdio_t[2]));
IOBUF i_iobuf_pmod_c2 (.IO(pmod_c[2]), .I(rmii_tx [2][1]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_e0 (.IO(pmod_e[0]), .I(rmii_tx [3][0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_e1 (.IO(pmod_e[1]), .I(1'b0), .O(rmii_rx [3][1]), .T(1'b1));
IOBUF i_iobuf_pmod_e2 (.IO(pmod_e[2]), .I(1'b0), .O(rmii_crs [3] ), .T(1'b1));
IOBUF i_iobuf_pmod_e3 (.IO(pmod_e[3]), .I(1'b1), .O(rmii_mdc [3] ), .T(1'b0));
IOBUF i_iobuf_pmod_e4 (.IO(pmod_e[4]), .I(rmii_txen [3]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_e5 (.IO(pmod_e[5]), .I(1'b0), .O(rmii_rx [3][0]), .T(1'b1));
IOBUF i_iobuf_pmod_e6 (.IO(pmod_e[6]), .I(1'b0), .O(rmii_refclk[3]), .T(1'b1));
IOBUF i_iobuf_pmod_e7 (.IO(pmod_e[7]), .I(rmii_mdio_o[3]), .O(rmii_mdio_i[3]), .T(rmii_mdio_t[3]));
IOBUF i_iobuf_pmod_c3 (.IO(pmod_c[3]), .I(rmii_tx [3][1]), .O(), .T(1'b0));
endmodule |
module jelly2_img_rgb2hsv
#(
parameter USER_WIDTH = 0,
parameter DATA_WIDTH = 8,
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1
)
(
input wire reset,
input wire clk,
input wire cke,
input wire s_img_row_first,
input wire s_img_row_last,
input wire s_img_col_first,
input wire s_img_col_last,
input wire s_img_de,
input wire [USER_BITS-1:0] s_img_user,
input wire [DATA_WIDTH-1:0] s_img_r,
input wire [DATA_WIDTH-1:0] s_img_g,
input wire [DATA_WIDTH-1:0] s_img_b,
input wire s_img_valid,
output wire m_img_row_first,
output wire m_img_row_last,
output wire m_img_col_first,
output wire m_img_col_last,
output wire m_img_de,
output wire [USER_BITS-1:0] m_img_user,
output wire [DATA_WIDTH-1:0] m_img_h,
output wire [DATA_WIDTH-1:0] m_img_s,
output wire [DATA_WIDTH-1:0] m_img_v,
output wire m_img_valid
);
logic m_row_first;
logic m_row_last;
logic m_col_first;
logic m_col_last;
logic m_de;
logic [USER_BITS-1:0] m_user;
logic [DATA_WIDTH-1:0] m_h;
logic [DATA_WIDTH-1:0] m_s;
logic [DATA_WIDTH-1:0] m_v;
logic m_valid;
jelly2_rgb2hsv
#(
.USER_WIDTH (USER_BITS+5),
.DATA_WIDTH (DATA_WIDTH)
)
i_rgb2hsv
(
.reset,
.clk,
.cke,
.s_user ({
s_img_user,
s_img_row_first,
s_img_row_last,
s_img_col_first,
s_img_col_last,
s_img_de
}),
.s_r (s_img_r),
.s_g (s_img_g),
.s_b (s_img_b),
.s_valid (s_img_valid),
.m_user ({
m_user,
m_row_first,
m_row_last,
m_col_first,
m_col_last,
m_de
}),
.m_h (m_h),
.m_s (m_s),
.m_v (m_v),
.m_valid (m_valid)
);
assign m_img_row_first = m_row_first & m_valid;
assign m_img_row_last = m_row_last & m_valid;
assign m_img_col_first = m_col_first & m_valid;
assign m_img_col_last = m_col_last & m_valid;
assign m_img_de = m_de & m_valid;
assign m_img_user = m_user;
assign m_img_h = m_h;
assign m_img_s = m_s;
assign m_img_v = m_v;
assign m_img_valid = m_valid;
endmodule |
module jelly2_img_delay
#(
parameter USER_WIDTH = 0,
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1,
parameter LATENCY = 1,
parameter USE_VALID = 0,
parameter INIT_USER = {USER_BITS{1'bx}}
)
(
input wire reset,
input wire clk,
input wire cke,
input wire s_img_col_first,
input wire s_img_col_last,
input wire s_img_row_first,
input wire s_img_row_last,
input wire s_img_de,
input wire [USER_BITS-1:0] s_img_user,
input wire s_img_valid,
output wire m_img_col_first,
output wire m_img_col_last,
output wire m_img_row_first,
output wire m_img_row_last,
output wire m_img_de,
output wire [USER_BITS-1:0] m_img_user,
output wire m_img_valid
);
wire [USER_BITS-1:0] delay_user;
wire delay_row_first;
wire delay_row_last;
wire delay_col_first;
wire delay_col_last;
wire delay_de;
wire delay_valid;
jelly_data_delay
#(
.LATENCY (LATENCY),
.DATA_WIDTH (USER_BITS + 6),
.DATA_INIT ({INIT_USER, 6'bxxxxx0})
)
i_data_delay
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_data ({
s_img_user,
s_img_row_first,
s_img_row_last,
s_img_col_first,
s_img_col_last,
s_img_de,
s_img_valid
}),
.out_data ({
delay_user,
delay_row_first,
delay_row_last,
delay_col_first,
delay_col_last,
delay_de,
delay_valid
})
);
generate
if ( USE_VALID ) begin : blk_use_valid
assign m_img_row_first = delay_row_first;
assign m_img_row_last = delay_row_last;
assign m_img_col_first = delay_col_first;
assign m_img_col_last = delay_col_last;
assign m_img_de = delay_de;
assign m_img_user = delay_user;
assign m_img_valid = delay_valid;
end
else begin
assign m_img_row_first = delay_valid & delay_row_first;
assign m_img_row_last = delay_valid & delay_row_last;
assign m_img_col_first = delay_valid & delay_col_first;
assign m_img_col_last = delay_valid & delay_col_last;
assign m_img_de = delay_valid & delay_de;
assign m_img_user = delay_user;
assign m_img_valid = delay_valid;
end
endgenerate
endmodule |
module VerilatorWrapper(
input IP_CLK,
input IP_ARESET_N,
input [31:0] SAXI0_ARADDR,
input [2:0] SAXI0_ARPROT,
input [3:0] SAXI0_ARCACHE,
input [7:0] SAXI0_ARLEN,
input [3:0] SAXI0_ARQOS,
input [0:0] SAXI0_ARLOCK,
input [5:0] SAXI0_ARUSER,
input [3:0] SAXI0_ARREGION,
input [11:0] SAXI0_ARID,
input [2:0] SAXI0_ARSIZE,
input [1:0] SAXI0_ARBURST,
input SAXI0_ARVALID,
output SAXI0_ARREADY,
output [1:0] SAXI0_RRESP,
output [0:0] SAXI0_RLAST,
output [31:0] SAXI0_RDATA,
output [5:0] SAXI0_RUSER,
output [11:0] SAXI0_RID,
output SAXI0_RVALID,
input SAXI0_RREADY,
input [1:0] SAXI0_AWBURST,
input [0:0] SAXI0_AWLOCK,
input [3:0] SAXI0_AWCACHE,
input [2:0] SAXI0_AWSIZE,
input [3:0] SAXI0_AWQOS,
input [31:0] SAXI0_AWADDR,
input [7:0] SAXI0_AWLEN,
input [5:0] SAXI0_AWUSER,
input [11:0] SAXI0_AWID,
input [2:0] SAXI0_AWPROT,
input [3:0] SAXI0_AWREGION,
output SAXI0_AWREADY,
input SAXI0_AWVALID,
input [31:0] SAXI0_WDATA,
input [3:0] SAXI0_WSTRB,
input [0:0] SAXI0_WLAST,
input [5:0] SAXI0_WUSER,
output SAXI0_WREADY,
input SAXI0_WVALID,
output [11:0] SAXI0_BID,
output [5:0] SAXI0_BUSER,
output [1:0] SAXI0_BRESP,
input SAXI0_BREADY,
output SAXI0_BVALID,
output [31:0] MAXI0_ARADDR,
output [2:0] MAXI0_ARPROT,
output [3:0] MAXI0_ARCACHE,
output [7:0] MAXI0_ARLEN,
output [3:0] MAXI0_ARQOS,
output [0:0] MAXI0_ARLOCK,
output [5:0] MAXI0_ARUSER,
output [3:0] MAXI0_ARREGION,
output [11:0] MAXI0_ARID,
output [2:0] MAXI0_ARSIZE,
output [1:0] MAXI0_ARBURST,
output MAXI0_ARVALID,
input MAXI0_ARREADY,
input [1:0] MAXI0_RRESP,
input [0:0] MAXI0_RLAST,
input [63:0] MAXI0_RDATA,
input [5:0] MAXI0_RUSER,
input [11:0] MAXI0_RID,
input MAXI0_RVALID,
output MAXI0_RREADY,
output [1:0] MAXI0_AWBURST,
output [0:0] MAXI0_AWLOCK,
output [3:0] MAXI0_AWCACHE,
output [2:0] MAXI0_AWSIZE,
output [3:0] MAXI0_AWQOS,
output [31:0] MAXI0_AWADDR,
output [7:0] MAXI0_AWLEN,
output [5:0] MAXI0_AWUSER,
output [11:0] MAXI0_AWID,
output [2:0] MAXI0_AWPROT,
output [3:0] MAXI0_AWREGION,
input MAXI0_AWREADY,
output MAXI0_AWVALID,
output [63:0] MAXI0_WDATA,
output [7:0] MAXI0_WSTRB,
output [0:0] MAXI0_WLAST,
output [5:0] MAXI0_WUSER,
input MAXI0_WREADY,
output MAXI0_WVALID,
input [11:0] MAXI0_BID,
input [5:0] MAXI0_BUSER,
input [1:0] MAXI0_BRESP,
output MAXI0_BREADY,
input MAXI0_BVALID,
output [31:0] MAXI1_ARADDR,
output [2:0] MAXI1_ARPROT,
output [3:0] MAXI1_ARCACHE,
output [7:0] MAXI1_ARLEN,
output [3:0] MAXI1_ARQOS,
output [0:0] MAXI1_ARLOCK,
output [5:0] MAXI1_ARUSER,
output [3:0] MAXI1_ARREGION,
output [11:0] MAXI1_ARID,
output [2:0] MAXI1_ARSIZE,
output [1:0] MAXI1_ARBURST,
output MAXI1_ARVALID,
input MAXI1_ARREADY,
input [1:0] MAXI1_RRESP,
input [0:0] MAXI1_RLAST,
input [63:0] MAXI1_RDATA,
input [5:0] MAXI1_RUSER,
input [11:0] MAXI1_RID,
input MAXI1_RVALID,
output MAXI1_RREADY,
output [1:0] MAXI1_AWBURST,
output [0:0] MAXI1_AWLOCK,
output [3:0] MAXI1_AWCACHE,
output [2:0] MAXI1_AWSIZE,
output [3:0] MAXI1_AWQOS,
output [31:0] MAXI1_AWADDR,
output [7:0] MAXI1_AWLEN,
output [5:0] MAXI1_AWUSER,
output [11:0] MAXI1_AWID,
output [2:0] MAXI1_AWPROT,
output [3:0] MAXI1_AWREGION,
input MAXI1_AWREADY,
output MAXI1_AWVALID,
output [63:0] MAXI1_WDATA,
output [7:0] MAXI1_WSTRB,
output [0:0] MAXI1_WLAST,
output [5:0] MAXI1_WUSER,
input MAXI1_WREADY,
output MAXI1_WVALID,
input [11:0] MAXI1_BID,
input [5:0] MAXI1_BUSER,
input [1:0] MAXI1_BRESP,
output MAXI1_BREADY,
input MAXI1_BVALID);
wire [159:0] ZynqNOC_write_input; // write issue
assign MAXI0_WUSER = ZynqNOC_write_input[158:153];
assign MAXI0_AWQOS = ZynqNOC_write_input[77:74];
assign MAXI0_WLAST = ZynqNOC_write_input[152:152];
assign MAXI0_AWCACHE = ZynqNOC_write_input[60:57];
assign MAXI0_AWLOCK = ZynqNOC_write_input[78:78];
assign MAXI0_AWUSER = ZynqNOC_write_input[73:68];
assign MAXI0_WDATA = ZynqNOC_write_input[143:80];
assign MAXI0_WSTRB = ZynqNOC_write_input[151:144];
assign MAXI0_AWID = ZynqNOC_write_input[56:45];
assign MAXI0_AWREGION = ZynqNOC_write_input[67:64];
assign MAXI0_AWSIZE = ZynqNOC_write_input[44:42];
assign MAXI0_AWADDR = ZynqNOC_write_input[31:0];
assign MAXI0_AWVALID = ZynqNOC_write_input[79];
assign MAXI0_AWLEN = ZynqNOC_write_input[39:32];
assign MAXI0_AWBURST = ZynqNOC_write_input[41:40];
assign MAXI0_WVALID = ZynqNOC_write_input[159];
assign MAXI0_AWPROT = ZynqNOC_write_input[63:61];
wire [20:0] ZynqNOC_write_output; // write response
assign ZynqNOC_write_output = {MAXI0_BVALID,MAXI0_BUSER,MAXI0_BID,MAXI0_BRESP};
wire ZynqNOC_write_ready_downstream;
assign MAXI0_BREADY = ZynqNOC_write_ready_downstream;
wire [1:0] ZynqNOC_write_ready;
assign ZynqNOC_write_ready = {MAXI0_WREADY,MAXI0_AWREADY};
////////////////
wire regs_read_ready_downstream;
assign regs_read_ready_downstream = SAXI0_RREADY;
wire regs_read_ready;
assign SAXI0_ARREADY = regs_read_ready;
wire [79:0] regs_read_input; // issue read to slave
assign regs_read_input = {SAXI0_ARVALID,SAXI0_ARQOS,SAXI0_ARUSER,SAXI0_ARREGION,SAXI0_ARLOCK,SAXI0_ARCACHE,SAXI0_ARPROT,SAXI0_ARID,SAXI0_ARBURST,SAXI0_ARSIZE,SAXI0_ARLEN,SAXI0_ARADDR};
wire [53:0] regs_read_output; // slave read response
assign SAXI0_RVALID = regs_read_output[53];
assign SAXI0_RLAST = regs_read_output[32:32];
assign SAXI0_RID = regs_read_output[46:35];
assign SAXI0_RDATA = regs_read_output[31:0];
assign SAXI0_RUSER = regs_read_output[52:47];
assign SAXI0_RRESP = regs_read_output[34:33];
wire regs_write_ready_downstream;
assign regs_write_ready_downstream = SAXI0_BREADY;
wire [1:0] regs_write_ready;
assign SAXI0_AWREADY = regs_write_ready[0];
assign SAXI0_WREADY = regs_write_ready[1];
wire [123:0] regs_write_input; // issue write to slave
assign regs_write_input[79:0] = {SAXI0_AWVALID,SAXI0_AWLOCK,SAXI0_AWQOS,SAXI0_AWUSER,SAXI0_AWREGION,SAXI0_AWPROT,SAXI0_AWCACHE,SAXI0_AWID,SAXI0_AWSIZE,SAXI0_AWBURST,SAXI0_AWLEN,SAXI0_AWADDR};
assign regs_write_input[123:80] = {SAXI0_WVALID,SAXI0_WUSER,SAXI0_WLAST,SAXI0_WSTRB,SAXI0_WDATA};
wire [20:0] regs_write_output; // return write result from slave
assign SAXI0_BVALID = regs_write_output[20];
assign SAXI0_BID = regs_write_output[13:2];
assign SAXI0_BUSER = regs_write_output[19:14];
assign SAXI0_BRESP = regs_write_output[1:0];
/////////////////////
wire ZynqNOC_read_ready_downstream;
assign MAXI0_RREADY = ZynqNOC_read_ready_downstream;
wire ZynqNOC_read_ready;
assign ZynqNOC_read_ready = MAXI0_ARREADY;
wire [79:0] ZynqNOC_read_input; // read request
assign MAXI0_ARADDR = ZynqNOC_read_input[31:0];
assign MAXI0_ARPROT = ZynqNOC_read_input[59:57];
assign MAXI0_ARCACHE = ZynqNOC_read_input[63:60];
assign MAXI0_ARBURST = ZynqNOC_read_input[44:43];
assign MAXI0_ARLEN = ZynqNOC_read_input[39:32];
assign MAXI0_ARSIZE = ZynqNOC_read_input[42:40];
assign MAXI0_ARLOCK = ZynqNOC_read_input[64:64];
assign MAXI0_ARVALID = ZynqNOC_read_input[79];
assign MAXI0_ARREGION = ZynqNOC_read_input[68:65];
assign MAXI0_ARID = ZynqNOC_read_input[56:45];
assign MAXI0_ARQOS = ZynqNOC_read_input[78:75];
assign MAXI0_ARUSER = ZynqNOC_read_input[74:69];
wire [85:0] ZynqNOC_read_output; // read response
assign ZynqNOC_read_output = {MAXI0_RVALID,MAXI0_RUSER,MAXI0_RID,MAXI0_RRESP,MAXI0_RLAST,MAXI0_RDATA};
wire ZynqNOC_read1_ready_downstream;
assign MAXI1_RREADY = ZynqNOC_read1_ready_downstream;
wire ZynqNOC_read1_ready;
assign ZynqNOC_read1_ready = MAXI1_ARREADY;
wire [79:0] ZynqNOC_read1_input; // read request
assign MAXI1_ARADDR = ZynqNOC_read1_input[31:0];
assign MAXI1_ARPROT = ZynqNOC_read1_input[59:57];
assign MAXI1_ARCACHE = ZynqNOC_read1_input[63:60];
assign MAXI1_ARBURST = ZynqNOC_read1_input[44:43];
assign MAXI1_ARLEN = ZynqNOC_read1_input[39:32];
assign MAXI1_ARSIZE = ZynqNOC_read1_input[42:40];
assign MAXI1_ARLOCK = ZynqNOC_read1_input[64:64];
assign MAXI1_ARVALID = ZynqNOC_read1_input[79];
assign MAXI1_ARREGION = ZynqNOC_read1_input[68:65];
assign MAXI1_ARID = ZynqNOC_read1_input[56:45];
assign MAXI1_ARQOS = ZynqNOC_read1_input[78:75];
assign MAXI1_ARUSER = ZynqNOC_read1_input[74:69];
wire [85:0] ZynqNOC_read1_output; // read response
assign ZynqNOC_read1_output = {MAXI1_RVALID,MAXI1_RUSER,MAXI1_RID,MAXI1_RRESP,MAXI1_RLAST,MAXI1_RDATA};
Top top(.CLK(IP_CLK), .reset(~IP_ARESET_N), .*);
endmodule |
module HPS(
output wire [1 - 1 : 0 ] h2f_rst_n
,output wire [1 - 1 : 0 ] h2f_user0_clk
);
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_warm_rst_req_n({
1'b1 // 0:0
})
,.f2h_dbg_rst_req_n({
1'b1 // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
1'b1 // 0:0
})
,.h2f_user0_clk({
h2f_user0_clk[0:0] // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cfg_cport_rfifo_map({
18'b000000000000000000 // 17:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
,.cfg_wfifo_cport_map({
16'b0000000000000000 // 15:0
})
,.cfg_cport_type({
12'b000000000000 // 11:0
})
,.cfg_rfifo_cport_map({
16'b0000000000000000 // 15:0
})
,.cfg_port_width({
12'b000000000000 // 11:0
})
,.cfg_cport_wfifo_map({
18'b000000000000000000 // 17:0
})
);
endmodule |
module lms_ctr_mm_interconnect_0_router_007_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [89 - 86 : 0] default_destination_id,
output [15-1 : 0] default_wr_channel,
output [15-1 : 0] default_rd_channel,
output [15-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[89 - 86 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_007
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [103-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [103-1 : 0] src_data,
output reg [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 57;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 89;
localparam PKT_DEST_ID_L = 86;
localparam PKT_PROTECTION_H = 93;
localparam PKT_PROTECTION_L = 91;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 60;
localparam PKT_TRANS_READ = 61;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [15-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_007_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 15'b01;
end
if (destid == 1 && read_transaction) begin
src_channel = 15'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module altera_customins_slave_translator
#(
parameter N_WIDTH = 8,
USE_DONE = 1,
NUM_FIXED_CYCLES = 2
)
(
// --------------------------------------
// Slave
// --------------------------------------
input wire [31:0] ci_slave_dataa,
input wire [31:0] ci_slave_datab,
output wire [31:0] ci_slave_result,
input wire [7:0] ci_slave_n,
input wire ci_slave_readra,
input wire ci_slave_readrb,
input wire ci_slave_writerc,
input wire [4:0] ci_slave_a,
input wire [4:0] ci_slave_b,
input wire [4:0] ci_slave_c,
input wire [31:0] ci_slave_ipending,
input wire ci_slave_estatus,
input wire ci_slave_clk,
input wire ci_slave_clken,
input wire ci_slave_reset,
input wire ci_slave_reset_req,
input wire ci_slave_start,
output wire ci_slave_done,
// --------------------------------------
// Master
// --------------------------------------
output wire [31:0] ci_master_dataa,
output wire [31:0] ci_master_datab,
input wire [31:0] ci_master_result,
output wire [N_WIDTH-1:0] ci_master_n,
output wire ci_master_readra,
output wire ci_master_readrb,
output wire ci_master_writerc,
output wire [4:0] ci_master_a,
output wire [4:0] ci_master_b,
output wire [4:0] ci_master_c,
output wire [31:0] ci_master_ipending,
output wire ci_master_estatus,
output wire ci_master_clk,
output wire ci_master_clken,
output wire ci_master_reset,
output wire ci_master_reset_req,
output wire ci_master_start,
input wire ci_master_done
);
localparam COUNTER_WIDTH = $clog2(NUM_FIXED_CYCLES);
wire gen_done;
reg [COUNTER_WIDTH-1:0] count;
reg running;
reg reg_start;
assign ci_slave_result = ci_master_result;
assign ci_master_writerc = ci_slave_writerc;
assign ci_master_dataa = ci_slave_dataa;
assign ci_master_readra = ci_slave_readra;
assign ci_master_datab = ci_slave_datab;
assign ci_master_readrb = ci_slave_readrb;
assign ci_master_b = ci_slave_b;
assign ci_master_c = ci_slave_c;
assign ci_master_a = ci_slave_a;
assign ci_master_ipending = ci_slave_ipending;
assign ci_master_estatus = ci_slave_estatus;
assign ci_master_clk = ci_slave_clk;
assign ci_master_clken = ci_slave_clken;
assign ci_master_reset = ci_slave_reset;
assign ci_master_reset_req = ci_slave_reset_req;
// --------------------------------------
// Is there something we need to do if the master does not
// have start?
// --------------------------------------
assign ci_master_start = ci_slave_start;
// --------------------------------------
// Create the done signal if the slave does not drive it.
//
// For num_cycles = 2, this is just the registered start.
// Anything larger and we use a down-counter.
// --------------------------------------
assign ci_slave_done = (USE_DONE == 1) ? ci_master_done : gen_done;
assign gen_done = (NUM_FIXED_CYCLES == 2) ? reg_start : (count == 0);
always @(posedge ci_slave_clk, posedge ci_slave_reset) begin
if (ci_slave_reset)
reg_start <= 0;
else if (ci_slave_clken)
reg_start <= ci_slave_start;
end
always @(posedge ci_slave_clk, posedge ci_slave_reset) begin
if (ci_slave_reset) begin
running <= 0;
count <= NUM_FIXED_CYCLES - 2;
end
else if (ci_slave_clken) begin
if (ci_slave_start)
running <= 1;
if (running)
count <= count - 1;
if (ci_slave_done) begin
running <= 0;
count <= NUM_FIXED_CYCLES - 2;
end
end
end
// --------------------------------------
// Opcode base addresses must be a multiple of their span,
// just like base addresses. This simplifies the following
// assignment (just drop the high order bits)
// --------------------------------------
assign ci_master_n = ci_slave_n[N_WIDTH-1:0];
endmodule |
module lms_ctr_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [103-1 : 0] sink0_data,
input [15-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [103-1 : 0] src_data,
output [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 103 + 15 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam PKT_TRANS_LOCK = 62;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module lms_ctr_mm_interconnect_0_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 10
)
(output [89 - 86 : 0] default_destination_id,
output [15-1 : 0] default_wr_channel,
output [15-1 : 0] default_rd_channel,
output [15-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[89 - 86 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [103-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [103-1 : 0] src_data,
output reg [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 57;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 89;
localparam PKT_DEST_ID_L = 86;
localparam PKT_PROTECTION_H = 93;
localparam PKT_PROTECTION_L = 91;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 60;
localparam PKT_TRANS_READ = 61;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h200000 - 64'h100000);
localparam PAD1 = log2ceil(64'h202000 - 64'h201800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h202000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [15-1 : 0] default_src_channel;
lms_ctr_mm_interconnect_0_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x100000 .. 0x200000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 22'h100000 ) begin
src_channel = 15'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
end
// ( 0x201800 .. 0x202000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 22'h201800 ) begin
src_channel = 15'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [103-1 : 0] sink0_data,
input [15-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [103-1 : 0] sink1_data,
input [15-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [103-1 : 0] sink2_data,
input [15-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [103-1 : 0] sink3_data,
input [15-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [103-1 : 0] sink4_data,
input [15-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [103-1 : 0] sink5_data,
input [15-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
input sink6_valid,
input [103-1 : 0] sink6_data,
input [15-1: 0] sink6_channel,
input sink6_startofpacket,
input sink6_endofpacket,
output sink6_ready,
input sink7_valid,
input [103-1 : 0] sink7_data,
input [15-1: 0] sink7_channel,
input sink7_startofpacket,
input sink7_endofpacket,
output sink7_ready,
input sink8_valid,
input [103-1 : 0] sink8_data,
input [15-1: 0] sink8_channel,
input sink8_startofpacket,
input sink8_endofpacket,
output sink8_ready,
input sink9_valid,
input [103-1 : 0] sink9_data,
input [15-1: 0] sink9_channel,
input sink9_startofpacket,
input sink9_endofpacket,
output sink9_ready,
input sink10_valid,
input [103-1 : 0] sink10_data,
input [15-1: 0] sink10_channel,
input sink10_startofpacket,
input sink10_endofpacket,
output sink10_ready,
input sink11_valid,
input [103-1 : 0] sink11_data,
input [15-1: 0] sink11_channel,
input sink11_startofpacket,
input sink11_endofpacket,
output sink11_ready,
input sink12_valid,
input [103-1 : 0] sink12_data,
input [15-1: 0] sink12_channel,
input sink12_startofpacket,
input sink12_endofpacket,
output sink12_ready,
input sink13_valid,
input [103-1 : 0] sink13_data,
input [15-1: 0] sink13_channel,
input sink13_startofpacket,
input sink13_endofpacket,
output sink13_ready,
input sink14_valid,
input [103-1 : 0] sink14_data,
input [15-1: 0] sink14_channel,
input sink14_startofpacket,
input sink14_endofpacket,
output sink14_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [103-1 : 0] src_data,
output [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 103 + 15 + 2;
localparam NUM_INPUTS = 15;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam PKT_TRANS_LOCK = 62;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
wire [PAYLOAD_W - 1 : 0] sink6_payload;
wire [PAYLOAD_W - 1 : 0] sink7_payload;
wire [PAYLOAD_W - 1 : 0] sink8_payload;
wire [PAYLOAD_W - 1 : 0] sink9_payload;
wire [PAYLOAD_W - 1 : 0] sink10_payload;
wire [PAYLOAD_W - 1 : 0] sink11_payload;
wire [PAYLOAD_W - 1 : 0] sink12_payload;
wire [PAYLOAD_W - 1 : 0] sink13_payload;
wire [PAYLOAD_W - 1 : 0] sink14_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
assign valid[6] = sink6_valid;
assign valid[7] = sink7_valid;
assign valid[8] = sink8_valid;
assign valid[9] = sink9_valid;
assign valid[10] = sink10_valid;
assign valid[11] = sink11_valid;
assign valid[12] = sink12_valid;
assign valid[13] = sink13_valid;
assign valid[14] = sink14_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[62];
lock[1] = sink1_data[62];
lock[2] = sink2_data[62];
lock[3] = sink3_data[62];
lock[4] = sink4_data[62];
lock[5] = sink5_data[62];
lock[6] = sink6_data[62];
lock[7] = sink7_data[62];
lock[8] = sink8_data[62];
lock[9] = sink9_data[62];
lock[10] = sink10_data[62];
lock[11] = sink11_data[62];
lock[12] = sink12_data[62];
lock[13] = sink13_data[62];
lock[14] = sink14_data[62];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
// 6 | 1 | 0
// 7 | 1 | 0
// 8 | 1 | 0
// 9 | 1 | 0
// 10 | 1 | 0
// 11 | 1 | 0
// 12 | 1 | 0
// 13 | 1 | 0
// 14 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
share_6 & { SHARE_COUNTER_W {next_grant[6]} } |
share_7 & { SHARE_COUNTER_W {next_grant[7]} } |
share_8 & { SHARE_COUNTER_W {next_grant[8]} } |
share_9 & { SHARE_COUNTER_W {next_grant[9]} } |
share_10 & { SHARE_COUNTER_W {next_grant[10]} } |
share_11 & { SHARE_COUNTER_W {next_grant[11]} } |
share_12 & { SHARE_COUNTER_W {next_grant[12]} } |
share_13 & { SHARE_COUNTER_W {next_grant[13]} } |
share_14 & { SHARE_COUNTER_W {next_grant[14]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
wire final_packet_6 = 1'b1;
wire final_packet_7 = 1'b1;
wire final_packet_8 = 1'b1;
wire final_packet_9 = 1'b1;
wire final_packet_10 = 1'b1;
wire final_packet_11 = 1'b1;
wire final_packet_12 = 1'b1;
wire final_packet_13 = 1'b1;
wire final_packet_14 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_14,
final_packet_13,
final_packet_12,
final_packet_11,
final_packet_10,
final_packet_9,
final_packet_8,
final_packet_7,
final_packet_6,
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign sink6_ready = src_ready && grant[6];
assign sink7_ready = src_ready && grant[7];
assign sink8_ready = src_ready && grant[8];
assign sink9_ready = src_ready && grant[9];
assign sink10_ready = src_ready && grant[10];
assign sink11_ready = src_ready && grant[11];
assign sink12_ready = src_ready && grant[12];
assign sink13_ready = src_ready && grant[13];
assign sink14_ready = src_ready && grant[14];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} } |
sink6_payload & {PAYLOAD_W {grant[6]} } |
sink7_payload & {PAYLOAD_W {grant[7]} } |
sink8_payload & {PAYLOAD_W {grant[8]} } |
sink9_payload & {PAYLOAD_W {grant[9]} } |
sink10_payload & {PAYLOAD_W {grant[10]} } |
sink11_payload & {PAYLOAD_W {grant[11]} } |
sink12_payload & {PAYLOAD_W {grant[12]} } |
sink13_payload & {PAYLOAD_W {grant[13]} } |
sink14_payload & {PAYLOAD_W {grant[14]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign sink6_payload = {sink6_channel,sink6_data,
sink6_startofpacket,sink6_endofpacket};
assign sink7_payload = {sink7_channel,sink7_data,
sink7_startofpacket,sink7_endofpacket};
assign sink8_payload = {sink8_channel,sink8_data,
sink8_startofpacket,sink8_endofpacket};
assign sink9_payload = {sink9_channel,sink9_data,
sink9_startofpacket,sink9_endofpacket};
assign sink10_payload = {sink10_channel,sink10_data,
sink10_startofpacket,sink10_endofpacket};
assign sink11_payload = {sink11_channel,sink11_data,
sink11_startofpacket,sink11_endofpacket};
assign sink12_payload = {sink12_channel,sink12_data,
sink12_startofpacket,sink12_endofpacket};
assign sink13_payload = {sink13_channel,sink13_data,
sink13_startofpacket,sink13_endofpacket};
assign sink14_payload = {sink14_channel,sink14_data,
sink14_startofpacket,sink14_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module lms_ctr_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [103-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [103-1 : 0] src_data,
output reg [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 57;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 89;
localparam PKT_DEST_ID_L = 86;
localparam PKT_PROTECTION_H = 93;
localparam PKT_PROTECTION_L = 91;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 60;
localparam PKT_TRANS_READ = 61;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h200000 - 64'h100000);
localparam PAD1 = log2ceil(64'h201000 - 64'h200000);
localparam PAD2 = log2ceil(64'h202000 - 64'h201800);
localparam PAD3 = log2ceil(64'h202020 - 64'h202000);
localparam PAD4 = log2ceil(64'h202040 - 64'h202020);
localparam PAD5 = log2ceil(64'h202060 - 64'h202040);
localparam PAD6 = log2ceil(64'h202080 - 64'h202060);
localparam PAD7 = log2ceil(64'h2020a0 - 64'h202080);
localparam PAD8 = log2ceil(64'h2020c0 - 64'h2020a0);
localparam PAD9 = log2ceil(64'h2020e0 - 64'h2020c0);
localparam PAD10 = log2ceil(64'h2020f0 - 64'h2020e0);
localparam PAD11 = log2ceil(64'h202100 - 64'h2020f0);
localparam PAD12 = log2ceil(64'h202110 - 64'h202100);
localparam PAD13 = log2ceil(64'h202118 - 64'h202110);
localparam PAD14 = log2ceil(64'h202120 - 64'h202118);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h202120;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [15-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x100000 .. 0x200000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 22'h100000 ) begin
src_channel = 15'b000000000100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
end
// ( 0x200000 .. 0x201000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 22'h200000 ) begin
src_channel = 15'b000100000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11;
end
// ( 0x201800 .. 0x202000 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 22'h201800 ) begin
src_channel = 15'b000000001000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
end
// ( 0x202000 .. 0x202020 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 22'h202000 ) begin
src_channel = 15'b100000000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x202020 .. 0x202040 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 22'h202020 ) begin
src_channel = 15'b010000000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x202040 .. 0x202060 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 22'h202040 ) begin
src_channel = 15'b001000000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x202060 .. 0x202080 )
if ( {address[RG:PAD6],{PAD6{1'b0}}} == 22'h202060 ) begin
src_channel = 15'b000010000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
end
// ( 0x202080 .. 0x2020a0 )
if ( {address[RG:PAD7],{PAD7{1'b0}}} == 22'h202080 ) begin
src_channel = 15'b000001000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14;
end
// ( 0x2020a0 .. 0x2020c0 )
if ( {address[RG:PAD8],{PAD8{1'b0}}} == 22'h2020a0 ) begin
src_channel = 15'b000000000000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x2020c0 .. 0x2020e0 )
if ( {address[RG:PAD9],{PAD9{1'b0}}} == 22'h2020c0 ) begin
src_channel = 15'b000000000000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x2020e0 .. 0x2020f0 )
if ( {address[RG:PAD10],{PAD10{1'b0}}} == 22'h2020e0 ) begin
src_channel = 15'b000000100000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x2020f0 .. 0x202100 )
if ( {address[RG:PAD11],{PAD11{1'b0}}} == 22'h2020f0 && read_transaction ) begin
src_channel = 15'b000000010000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12;
end
// ( 0x202100 .. 0x202110 )
if ( {address[RG:PAD12],{PAD12{1'b0}}} == 22'h202100 ) begin
src_channel = 15'b000000000000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x202110 .. 0x202118 )
if ( {address[RG:PAD13],{PAD13{1'b0}}} == 22'h202110 ) begin
src_channel = 15'b000000000010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
end
// ( 0x202118 .. 0x202120 )
if ( {address[RG:PAD14],{PAD14{1'b0}}} == 22'h202118 && read_transaction ) begin
src_channel = 15'b000000000001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [103-1 : 0] sink_data, // ST_DATA_W=103
input [15-1 : 0] sink_channel, // ST_CHANNEL_W=15
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [103-1 : 0] src0_data, // ST_DATA_W=103
output reg [15-1 : 0] src0_channel, // ST_CHANNEL_W=15
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{14{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module lms_ctr_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
input receiver2_irq,
input receiver3_irq,
input receiver4_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[0] = receiver0_irq;
sender_irq[1] = receiver1_irq;
sender_irq[2] = receiver2_irq;
sender_irq[3] = receiver3_irq;
sender_irq[4] = receiver4_irq;
end
endmodule |
module lms_ctr_mm_interconnect_0_cmd_demux_001
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [103-1 : 0] sink_data, // ST_DATA_W=103
input [15-1 : 0] sink_channel, // ST_CHANNEL_W=15
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [103-1 : 0] src0_data, // ST_DATA_W=103
output reg [15-1 : 0] src0_channel, // ST_CHANNEL_W=15
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [103-1 : 0] src1_data, // ST_DATA_W=103
output reg [15-1 : 0] src1_channel, // ST_CHANNEL_W=15
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{13{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module lms_ctr_mm_interconnect_0_rsp_mux_001
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [103-1 : 0] sink0_data,
input [15-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [103-1 : 0] sink1_data,
input [15-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [103-1 : 0] src_data,
output [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 103 + 15 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam PKT_TRANS_LOCK = 62;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[62];
lock[1] = sink1_data[62];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module lms_ctr_nios2_cpu_custom_instruction_master_comb_xconnect
(
// -------------------
// Custom instruction masters
// -------------------
output [31 : 0] ci_master0_dataa,
output [31 : 0] ci_master0_datab,
input [31 : 0] ci_master0_result,
output [ 7 : 0] ci_master0_n,
output ci_master0_readra,
output ci_master0_readrb,
output ci_master0_writerc,
output [ 4 : 0] ci_master0_a,
output [ 4 : 0] ci_master0_b,
output [ 4 : 0] ci_master0_c,
output [31 : 0] ci_master0_ipending,
output ci_master0_estatus,
// -------------------
// Custom instruction slave
// -------------------
input [31 : 0] ci_slave_dataa,
input [31 : 0] ci_slave_datab,
output [31 : 0] ci_slave_result,
input [ 7 : 0] ci_slave_n,
input ci_slave_readra,
input ci_slave_readrb,
input ci_slave_writerc,
input [ 4 : 0] ci_slave_a,
input [ 4 : 0] ci_slave_b,
input [ 4 : 0] ci_slave_c,
input [31 : 0] ci_slave_ipending,
input ci_slave_estatus
);
wire select0;
// -------------------------------------------------------
// Wire non-control signals through to each master
// -------------------------------------------------------
assign ci_master0_dataa = ci_slave_dataa;
assign ci_master0_datab = ci_slave_datab;
assign ci_master0_n = ci_slave_n;
assign ci_master0_a = ci_slave_a;
assign ci_master0_b = ci_slave_b;
assign ci_master0_c = ci_slave_c;
assign ci_master0_ipending = ci_slave_ipending;
assign ci_master0_estatus = ci_slave_estatus;
// -------------------------------------------------------
// Figure out which output is selected, and use that to
// gate control signals
// -------------------------------------------------------
assign select0 = ci_slave_n >= 0 && ci_slave_n < 1;
assign ci_master0_readra = (select0 && ci_slave_readra);
assign ci_master0_readrb = (select0 && ci_slave_readrb);
assign ci_master0_writerc = (select0 && ci_slave_writerc);
// -------------------------------------------------------
// Use the select signal to figure out which result to mux
// back
// -------------------------------------------------------
assign ci_slave_result = {32{ select0 }} & ci_master0_result
;
endmodule |
module factory_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [98-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [98-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 98 + 6 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 98;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 61;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module factory_mm_interconnect_0_cmd_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [98-1 : 0] sink_data, // ST_DATA_W=98
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [98-1 : 0] src0_data, // ST_DATA_W=98
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [98-1 : 0] src1_data, // ST_DATA_W=98
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [98-1 : 0] src2_data, // ST_DATA_W=98
output reg [6-1 : 0] src2_channel, // ST_CHANNEL_W=6
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [98-1 : 0] src3_data, // ST_DATA_W=98
output reg [6-1 : 0] src3_channel, // ST_CHANNEL_W=6
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [98-1 : 0] src4_data, // ST_DATA_W=98
output reg [6-1 : 0] src4_channel, // ST_CHANNEL_W=6
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [98-1 : 0] src5_data, // ST_DATA_W=98
output reg [6-1 : 0] src5_channel, // ST_CHANNEL_W=6
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 6;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid;
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid;
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule |
module factory_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 4,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 4
)
(output [84 - 82 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[84 - 82 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module factory_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [98-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [98-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 56;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 84;
localparam PKT_DEST_ID_L = 82;
localparam PKT_PROTECTION_H = 88;
localparam PKT_PROTECTION_L = 86;
localparam ST_DATA_W = 98;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 59;
localparam PKT_TRANS_READ = 60;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20 - 64'h0);
localparam PAD1 = log2ceil(64'h40 - 64'h20);
localparam PAD2 = log2ceil(64'h48 - 64'h40);
localparam PAD3 = log2ceil(64'h80 - 64'h60);
localparam PAD4 = log2ceil(64'h800 - 64'h400);
localparam PAD5 = log2ceil(64'h200000 - 64'h100000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h200000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [6-1 : 0] default_src_channel;
factory_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x20 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 21'h0 ) begin
src_channel = 6'b100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x20 .. 0x40 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 21'h20 ) begin
src_channel = 6'b000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x40 .. 0x48 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 21'h40 ) begin
src_channel = 6'b001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x60 .. 0x80 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 21'h60 ) begin
src_channel = 6'b000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x400 .. 0x800 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 21'h400 ) begin
src_channel = 6'b000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x100000 .. 0x200000 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 21'h100000 ) begin
src_channel = 6'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module factory_mm_interconnect_0_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [98-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [98-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 56;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 84;
localparam PKT_DEST_ID_L = 82;
localparam PKT_PROTECTION_H = 88;
localparam PKT_PROTECTION_L = 86;
localparam ST_DATA_W = 98;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 59;
localparam PKT_TRANS_READ = 60;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [6-1 : 0] default_src_channel;
factory_mm_interconnect_0_router_001_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 6'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module button_debouncer
#(parameter CNT_WIDTH = 16)
( input clk,
input reset,
input key,
output reg key_state_o,
output reg key_down_o,
output reg key_up_o
);
// Синхронизируем вход с текущим тактовым доменом.
reg [1:0] key_reg;
always @ (posedge clk)
begin
if (reset)
key_reg <= 2'b00;
else
key_reg <= {key_reg[0], ~key};
end
reg [CNT_WIDTH - 1:0] key_count;
wire key_change_f = (key_state_o != key_reg[1]);
wire key_cnt_max = &key_count;
always @(posedge clk)
begin
if (reset)
begin
key_count <= 0;
key_state_o <= 0;
end
else if(key_change_f)
begin
key_count <= key_count + 'd1;
if(key_cnt_max)
key_state_o <= ~key_state_o;
end
else
key_count <= 0;
end
always @(posedge clk)
begin
key_down_o <= key_change_f & key_cnt_max & ~key_state_o;
key_up_o <= key_change_f & key_cnt_max & key_state_o;
end
endmodule |
module sys_array_cell
#(parameter DATA_WIDTH = 8)
( input clk,
input reset_n,
input param_load,
input signed [DATA_WIDTH - 1:0] input_data,
input signed [2 * DATA_WIDTH - 1:0] prop_data,
input signed [DATA_WIDTH - 1:0] param_data,
output reg signed [2 * DATA_WIDTH - 1:0] out_data,
output reg signed [DATA_WIDTH - 1:0] prop_param
);
reg signed [DATA_WIDTH - 1:0] par;
always @(posedge clk)
begin
if (~reset_n) begin // Сброс
out_data <= {2 * DATA_WIDTH{1'b0}};
par <= {DATA_WIDTH{1'b0}};
end
else if (param_load) begin // Загрузка параметра
par <= param_data;
end
else begin // Вычисление данных
// Задание 1. Реализуйте основные вычисления модуля.
end
end
endmodule |
module seven_segment_4_digits
(
input clock,
input reset,
input [15:0] number,
output reg [ 7:0] abcdefgh,
output reg [ 3:0] digit
);
function [7:0] bcd_to_seg (input [3:0] bcd);
case (bcd)
'h0: bcd_to_seg = 'b11000000;
'h1: bcd_to_seg = 'b11111001;
'h2: bcd_to_seg = 'b10100100;
'h3: bcd_to_seg = 'b10110000;
'h4: bcd_to_seg = 'b10011001;
'h5: bcd_to_seg = 'b10010010;
'h6: bcd_to_seg = 'b10000010;
'h7: bcd_to_seg = 'b11111000;
'h8: bcd_to_seg = 'b10000000;
'h9: bcd_to_seg = 'b10010000;
'ha: bcd_to_seg = 'b10001000;
'hb: bcd_to_seg = 'b10000011;
'hc: bcd_to_seg = 'b11000110;
'hd: bcd_to_seg = 'b10100001;
'he: bcd_to_seg = 'b10000110;
'hf: bcd_to_seg = 'b10001110;
endcase
endfunction
reg [15:0] cnt;
always @ (posedge clock)
if (reset)
cnt <= 16'd0;
else
cnt <= cnt + 16'd1;
reg [1:0] i;
always @ (posedge clock)
begin
if (reset)
begin
abcdefgh <= bcd_to_seg(0);
digit <= ~ 4'b1;
i <= 0;
end
else if (cnt == 16'b0)
begin
abcdefgh <= bcd_to_seg(number [i * 4 +: 4]);
digit <= ~ (4'b1 << i);
i <= i + 1;
end
end
endmodule |
module read_data
#(parameter DATA_WIDTH=8)(
input clk,
input reset_n,
input change,
output [2:0] code,
output [DATA_WIDTH-1:0] inp,
output [DATA_WIDTH-1:0] par,
output [2*DATA_WIDTH-1:0] prop,
output [2*DATA_WIDTH-1:0] result
);
reg [0:7] [DATA_WIDTH-1:0] data_inp;
reg [0:7] [DATA_WIDTH-1:0] data_param;
reg [0:7] [2*DATA_WIDTH-1:0] data_prop;
reg [0:7] [2*DATA_WIDTH-1:0] data_result;
reg [2:0] code_b;
always @(posedge clk)
begin
if (~reset_n)
begin
code_b = 'd0;
// Индексация 0 1 2 3 4 5 6 7
data_inp = {8'hf1, 8'hf7, 8'hc8, 8'h4c, 8'h50, 8'hd9, 8'h32, 8'h85};
data_param = {8'hc8, 8'h6d, 8'h83, 8'hd1, 8'hd7, 8'h4b, 8'h17, 8'h82};
// Индексация 0 1 2 3 4 5 6 7
data_prop = {16'h001b, 16'h0031, 16'h00de, 16'h0032, 16'h00b9, 16'h0057, 16'h00d7, 16'h00e6};
data_result = {16'hbc63, 16'h695c, 16'h6736, 16'h3e3e, 16'h43e9, 16'h3fea, 16'h0555, 16'h4470};
end
else
if (change)
code_b = code_b + 1;
end
assign inp = data_inp[code_b];
assign par = data_param[code_b];
assign prop = data_prop[code_b];
assign result = data_result[code_b];
// Для RZRD
assign code = ~{code_b[0], code_b[1], code_b[2]};
// Для omdazz
//assign code = ~code_b;
endmodule |
module shift_reg
#(parameter DATA_WIDTH=8,
parameter LENGTH=4)
(
input clk,
input reset_n,
input [1:0] ctrl_code,
input [0:LENGTH-1] [DATA_WIDTH-1:0] data_in,
input [DATA_WIDTH-1:0] data_write,
output reg [DATA_WIDTH-1:0] data_read,
output reg [0:LENGTH-1] [DATA_WIDTH-1:0] data_out
);
localparam REG_UPLOAD = 0,
REG_LOAD = 1,
REG_WRITE = 2,
REG_READ = 3;
reg en;
reg [0:LENGTH - 1] [DATA_WIDTH - 1:0] contents;
integer i;
always @(posedge clk)
begin
if (~reset_n)
begin
for(i = 0; i < LENGTH; i = i + 1) begin : for_reset_n
contents[i] <= {DATA_WIDTH{1'b0}};
end
en <= 1'b1;
end
else
begin
if (en)
begin
case (ctrl_code)
REG_UPLOAD: data_out <= contents;
REG_LOAD: contents <= data_in;
REG_READ:
begin
data_read <= contents[0];
for (i = 0; i < LENGTH - 1; i = i + 1) begin : for_REG_READ
contents[i] <= contents[i+1];
end
contents[LENGTH-1] <= contents[0];
end
REG_WRITE:
begin
for (i = 0; i < LENGTH - 1; i = i + 1) begin : for_REG_WRITE
contents[i] <= contents[i+1];
end
contents[LENGTH-1] <= data_write;
end
endcase
end
end
end
endmodule |
module sys_array_fetcher
#( parameter DATA_WIDTH = 8,
parameter ARRAY_W_W = 2, //Строк в массиве весов
parameter ARRAY_W_L = 5, //Столбцов в массиве весов
parameter ARRAY_A_W = 5, //Строк в массиве данных
parameter ARRAY_A_L = 2) //Столбцов в массиве данных
( input clk,
input reset_n,
input load_params,
input start_comp,
input [0:ARRAY_A_W - 1] [0:ARRAY_A_L - 1] [DATA_WIDTH - 1:0] input_data_b,
input [0:ARRAY_W_W - 1] [0:ARRAY_W_L - 1] [DATA_WIDTH - 1:0] input_data_w,
output reg ready,
output reg [0:ARRAY_W_W - 1] [0:ARRAY_A_L - 1] [2 * DATA_WIDTH - 1:0] out_data
);
// Необходимое количество циклов clk для выполнения выборки и возврата результатов
localparam FETCH_LENGTH = ARRAY_A_L + ARRAY_A_W + ARRAY_W_W + 1;
reg [15:0] cnt; // Счетчик
reg [ARRAY_A_W-1:0] [1:0] control_sr_read; // Контрольные сигналы регистра чтения
reg [ARRAY_W_W-1:0] [1:0] control_sr_write; // Контрольные сигналы регистра записи
wire [0:ARRAY_A_W-1] [DATA_WIDTH-1:0] input_sys_array;
wire [0:ARRAY_A_W-1] [DATA_WIDTH-1:0] empty_wire_reads;
wire [0:ARRAY_A_W-1] [0:ARRAY_A_L-1] [DATA_WIDTH-1:0] empty_wire2_reads;
wire [0:ARRAY_W_W-1] [0:ARRAY_A_L-1] [2*DATA_WIDTH-1:0] empty_wire_writes;
wire [0:ARRAY_W_W-1] [2*DATA_WIDTH-1:0] empty_wire2_writes;
wire [0:ARRAY_W_W-1] [2*DATA_WIDTH-1:0] output_sys_array;
wire [0:ARRAY_W_W - 1] [0:ARRAY_A_L - 1] [2 * DATA_WIDTH - 1:0] output_wire;
genvar i,j;
generate
for (i=0;i<ARRAY_A_W; i=i+1) begin: generate_reads_shift_reg
shift_reg #(.DATA_WIDTH(DATA_WIDTH), .LENGTH(ARRAY_A_L)) reads
( .clk(clk),
.reset_n(reset_n),
.ctrl_code(control_sr_read[i]),
.data_in(input_data_b[i]),
.data_write(empty_wire_reads[i]),
.data_read(input_sys_array[i]),
.data_out(empty_wire2_reads[i])
);
end
endgenerate
generate
for (i=0;i<ARRAY_W_W;i=i+1) begin: generate_writes_shift_reg
shift_reg #(.DATA_WIDTH(2*DATA_WIDTH), .LENGTH(ARRAY_A_L)) writes
( .clk(clk),
.reset_n(reset_n),
.ctrl_code(control_sr_write[i]),
.data_in(empty_wire_writes[i]),
.data_write(output_sys_array[i]),
.data_read(empty_wire2_writes[i]),
.data_out(output_wire[i])
);
end
endgenerate
sys_array_basic #(.DATA_WIDTH(DATA_WIDTH),
.ARRAY_W_W(ARRAY_W_W), .ARRAY_W_L(ARRAY_W_L),
.ARRAY_A_W(ARRAY_A_W), .ARRAY_A_L(ARRAY_A_L))
systolic_array
(
.clk(clk),
.reset_n(reset_n),
.weights_load(load_params),
.weight_data(input_data_w),
.input_data(input_sys_array),
.output_data(output_sys_array)
);
always @(posedge clk)
begin
if (~reset_n) begin // Сброс
cnt <= 15'd0;
control_sr_read <= {ARRAY_A_W * 2{1'b0}};
control_sr_write <= {ARRAY_W_W * 2{1'b0}};
out_data <= 'b0;
ready <= 1'b0;
end
else if(start_comp) begin // Начало вычислений
cnt <= 15'd1;
control_sr_read <= {ARRAY_A_W{2'b01}}; //initiate loading read registers
end
else
if (cnt > 0) begin // Основные вычисления
if (cnt == 1) begin // Задание сигналова на первом такте вычислений
control_sr_read[ARRAY_A_W - 1:1] <= {2 * (ARRAY_A_W - 1){1'b0}};
control_sr_read[0] <= 2'b11;
cnt <= cnt + 1'b1; end
else
begin // Задание логических сигналов
if (cnt < ARRAY_W_L + 1) // Включение регистров чтения
control_sr_read[cnt-1] <= 2'b11;
if ((cnt > ARRAY_A_L) && (cnt < ARRAY_A_L + ARRAY_W_L + 1)) // Старт отключения регистров чтения
control_sr_read[cnt - ARRAY_A_L - 1] <= 2'b00;
if ((cnt > ARRAY_W_L + 1) && (cnt < ARRAY_W_L + ARRAY_W_W + 2)) // Включение регистров записи
control_sr_write[cnt - ARRAY_W_L - 2] <= 2'b10;
if ((cnt > ARRAY_W_L + ARRAY_A_L + 1) && (cnt <= FETCH_LENGTH)) // Старт отключения регистров записи
control_sr_write[cnt - (ARRAY_W_L + ARRAY_A_L) - 2] <= 2'b00;
if (cnt <= FETCH_LENGTH+1)
cnt <= cnt + 1'b1;
else begin // Выдача итогового результата
cnt <= 15'd0;
out_data <= output_wire;
ready <= 1'b1;
end
end
end
end
endmodule |
module sys_array_basic
#(
parameter DATA_WIDTH = 8,
parameter ARRAY_W_W = 4, //Строк в массиве весов
parameter ARRAY_W_L = 4, //Столбцов в массиве весов
parameter ARRAY_A_W = 4, //Строк в массиве данных
parameter ARRAY_A_L = 4) //Столбцов в массиве данных
( input clk,
input reset_n,
input weights_load,
input [0:ARRAY_A_W-1] [DATA_WIDTH-1:0] input_data,
input [0:ARRAY_W_W-1] [0:ARRAY_W_L-1] [DATA_WIDTH-1:0] weight_data,
output [0:ARRAY_W_W-1] [2*DATA_WIDTH-1:0] output_data
);
wire [0:ARRAY_W_W-1] [0:ARRAY_W_L-1] [2*DATA_WIDTH-1:0] temp_output_data;
wire [0:ARRAY_W_W-1] [0:ARRAY_W_L-1] [DATA_WIDTH-1:0] propagate_module;
genvar i;
genvar j;
genvar t;
// Генерация массива вычислительных ячеек
// Задание 2. Допишите необходимые входные и выходные сигналы.
generate
for(i = 0; i < ARRAY_W_W; i = i + 1) begin : generate_array_proc
for (j = 0; j < ARRAY_W_L; j = j + 1) begin : generate_array_proc2
if ((i == 0) && (j == 0)) // i - строка, j - столбец
begin
sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
.clk(clk),
.reset_n(reset_n),
.param_load(weights_load),
.input_data(input_data[0]),
.prop_data({2*DATA_WIDTH{1'b0}}),
.param_data(weight_data[0][0]),
.out_data(temp_output_data[0][0]),
.prop_param(propagate_module[0][0])
);
end
else if (i == 0) // Первая строка
begin
sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
.clk(),
.reset_n(),
.param_load(),
.input_data(),
.prop_data(),
.param_data(),
.out_data(),
.prop_param()
);
end
else if (j == 0) // Первый столбец
begin
sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
.clk(),
.reset_n(),
.param_load(),
.input_data(),
.prop_data(),
.param_data(),
.out_data(),
.prop_param()
);
end
else
begin // Остальные элементы
sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
.clk(),
.reset_n(),
.param_load(),
.input_data(),
.prop_data(),
.param_data(),
.out_data(),
.prop_param()
);
end
end
end
endgenerate
// Генерация связей для выходных данных
generate
for (t=0;t<ARRAY_W_W;t=t+1) begin: output_prop
assign output_data[t] = temp_output_data[t][ARRAY_W_L-1];
end
endgenerate
endmodule |
module upsizing
# (
parameter n = 5, nb = n * 8
)
(
input wire aclk,
input wire aresetn,
input wire [nb - 1:0] in_tdata,
input wire in_tvalid,
output wire in_tready,
output wire [nb*2- 1:0] out_tdata,
output wire out_tvalid,
input wire out_tready
);
logic flag_hf;
logic [nb-1:0] reg_hf;
always @(posedge aclk)
if( ~aresetn )
flag_hf <= #1 '0;
else if( in_tvalid & in_tready )
flag_hf <= #1 ~flag_hf;
always @(posedge aclk)
if( in_tvalid & in_tready & ~flag_hf )
reg_hf <= #1 in_tdata;
assign out_tdata = { reg_hf, in_tdata };
assign in_tready = ~flag_hf | out_tready;
assign out_tvalid = flag_hf & in_tvalid;
endmodule |
module top(
input wire aclk,
input wire aresetn,
input wire [255:0] in_tdata,
input wire in_tvalid,
output wire in_tready,
output wire [255:0] out_tdata,
output wire out_tvalid,
input wire out_tready
);
logic [255:0] c0_tdata;
logic c0_tvalid;
logic c0_tready;
logic [511:0] c1_tdata;
logic c1_tvalid;
logic c1_tready;
logic [255:0] c2_tdata;
logic c2_tvalid;
logic c2_tready;
logic [511:0] c3_tdata;
logic c3_tvalid;
logic c3_tready;
logic [255:0] c4_tdata;
logic c4_tvalid;
logic c4_tready;
logic [511:0] c1s_tdata;
logic c1s_tvalid;
logic c1s_tready;
logic [255:0] c2s_tdata;
logic c2s_tvalid;
logic c2s_tready;
logic [511:0] c3s_tdata;
logic c3s_tvalid;
logic c3s_tready;
axis_register_slice_32 reg_i (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( in_tvalid ),
.s_axis_tready ( in_tready ),
.s_axis_tdata ( in_tdata ),
.m_axis_tvalid ( c0_tvalid ),
.m_axis_tready ( c0_tready ),
.m_axis_tdata ( c0_tdata )
);
upsizing
#(
.n ( 32 )
)
upsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c0_tdata ),
.in_tvalid ( c0_tvalid ),
.in_tready ( c0_tready ),
.out_tdata ( c1_tdata ),
.out_tvalid ( c1_tvalid ),
.out_tready ( c1_tready )
);
skid_crd
#(
.n ( 64 )
)
skid_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1_tdata ),
.in_tvalid ( c1_tvalid ),
.in_tready ( c1_tready ),
.out_tdata ( c1s_tdata ),
.out_tvalid ( c1s_tvalid ),
.out_tready ( c1s_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1s_tdata ),
.in_tvalid ( c1s_tvalid ),
.in_tready ( c1s_tready ),
.out_tdata ( c2_tdata ),
.out_tvalid ( c2_tvalid ),
.out_tready ( c2_tready )
);
skid_crd
#(
.n ( 32 )
)
skid_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2_tdata ),
.in_tvalid ( c2_tvalid ),
.in_tready ( c2_tready ),
.out_tdata ( c2s_tdata ),
.out_tvalid ( c2s_tvalid ),
.out_tready ( c2s_tready )
);
upsizing
#(
.n ( 32 )
)
upsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2s_tdata ),
.in_tvalid ( c2s_tvalid ),
.in_tready ( c2s_tready ),
.out_tdata ( c3_tdata ),
.out_tvalid ( c3_tvalid ),
.out_tready ( c3_tready )
);
skid_crd
#(
.n ( 64 )
)
skid_2
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3_tdata ),
.in_tvalid ( c3_tvalid ),
.in_tready ( c3_tready ),
.out_tdata ( c3s_tdata ),
.out_tvalid ( c3s_tvalid ),
.out_tready ( c3s_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3s_tdata ),
.in_tvalid ( c3s_tvalid ),
.in_tready ( c3s_tready ),
.out_tdata ( c4_tdata ),
.out_tvalid ( c4_tvalid ),
.out_tready ( c4_tready )
);
axis_register_slice_32 reg_0 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( c4_tvalid ),
.s_axis_tready ( c4_tready ),
.s_axis_tdata ( c4_tdata ),
.m_axis_tvalid ( out_tvalid ),
.m_axis_tready ( out_tready ),
.m_axis_tdata ( out_tdata )
);
endmodule |
module user();
endmodule |
module fifo_w8
#(
parameter WIDTH = 16
)
(
input wire reset_p, //! 1 - reset
input wire clk, //! clock
input wire [WIDTH-1:0] data_i,
input wire data_we,
output wire [WIDTH-1:0] data_o,
input wire data_rd,
output wire full,
output wire empty
);
logic [WIDTH-1:0] mem[8];
logic [3:0] cnt_wr;
logic [3:0] cnt_rd;
logic rstp;
always @(posedge clk) begin
rstp <= #1 reset_p;
if( ~full & data_we ) begin
mem[cnt_wr[2:0]] <= #1 data_i;
cnt_wr <= #1 cnt_wr + 1;
end
if( ~empty & data_rd ) begin
cnt_rd <= #1 cnt_rd + 1;
end
if( rstp ) begin
cnt_wr <= # 2'b0000;
cnt_rd <= # 2'b0000;
end
end
//assign full = (cnt_wr_next==cnt_rd) ? 1 : 0;
assign full = (cnt_rd[2:0]==cnt_wr[2:0] && cnt_rd[3]!=cnt_wr[3]) ? 1 : 0;
assign empty = (cnt_wr==cnt_rd) ? 1 : 0;
assign data_o = mem[cnt_rd[2:0]];
endmodule |
module user_axis
# (
parameter n = 5, //! Number of bytes
parameter nb = n * 8 //! Number of bits
)
(
input wire clk, //! clok
input wire reset_n, //! 0 - reset
input wire [nb*2 - 1:0] in_tdata, //! input data
input wire in_tvalid, //! 1 - input data is valid
output wire in_tready, //! 1 - ready for get data
output wire [nb - 1:0] out_tdata, //! output data
output wire out_tvalid, //! 1 - output data is valid
input wire out_tready //! 1 - ready for get data
);
assign out_tdata = in_tdata;
assign out_tvalid = in_tvalid & reset_n;
assign in_tready = out_tready & reset_n;
endmodule |
module top(
input wire aclk,
input wire aresetn,
input wire [255:0] in_tdata,
input wire in_tvalid,
output wire in_tready,
output wire [255:0] out_tdata,
output wire out_tvalid,
input wire out_tready
);
logic [255:0] c0_tdata;
logic c0_tvalid;
logic c0_tready;
logic [511:0] c1_tdata;
logic c1_tvalid;
logic c1_tready;
logic [255:0] c2_tdata;
logic c2_tvalid;
logic c2_tready;
logic [511:0] c3_tdata;
logic c3_tvalid;
logic c3_tready;
logic [255:0] c4_tdata;
logic c4_tvalid;
logic c4_tready;
axis_register_slice_32 reg_i (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( in_tvalid ),
.s_axis_tready ( in_tready ),
.s_axis_tdata ( in_tdata ),
.m_axis_tvalid ( c0_tvalid ),
.m_axis_tready ( c0_tready ),
.m_axis_tdata ( c0_tdata )
);
upsizing
#(
.n ( 32 )
)
upsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c0_tdata ),
.in_tvalid ( c0_tvalid ),
.in_tready ( c0_tready ),
.out_tdata ( c1_tdata ),
.out_tvalid ( c1_tvalid ),
.out_tready ( c1_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1_tdata ),
.in_tvalid ( c1_tvalid ),
.in_tready ( c1_tready ),
.out_tdata ( c2_tdata ),
.out_tvalid ( c2_tvalid ),
.out_tready ( c2_tready )
);
upsizing
#(
.n ( 32 )
)
upsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2_tdata ),
.in_tvalid ( c2_tvalid ),
.in_tready ( c2_tready ),
.out_tdata ( c3_tdata ),
.out_tvalid ( c3_tvalid ),
.out_tready ( c3_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3_tdata ),
.in_tvalid ( c3_tvalid ),
.in_tready ( c3_tready ),
.out_tdata ( c4_tdata ),
.out_tvalid ( c4_tvalid ),
.out_tready ( c4_tready )
);
axis_register_slice_32 reg_0 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( c4_tvalid ),
.s_axis_tready ( c4_tready ),
.s_axis_tdata ( c4_tdata ),
.m_axis_tvalid ( out_tvalid ),
.m_axis_tready ( out_tready ),
.m_axis_tdata ( out_tdata )
);
endmodule |
module other_single_port_ram21
#( parameter RAMLENGTH=800, //RAMLENGTH*DATAWIDTH = 4800 = 80x60 RAM RESOLUTION
RAM_INITIAL_VALUE=6'b111111, //default value for memreset
DATA_WIDTH=6,
ADDR_WIDTH=10
)
(
input [DATA_WIDTH-1:0]data, //RAM words' write input
input [ADDR_WIDTH-1:0] addr, //ln(RAMLENGTH)/ln(2)
input we, clk, memenable,
input [ADDR_WIDTH:0] resetcnt,
output [DATA_WIDTH-1:0]q //RAM words' read input
);
//memreset variable
//integer i;
// Declare the RAM variable
(* ramstyle = "M9K" *) reg [DATA_WIDTH-1:0]ramblock[3*RAMLENGTH-1:0] ;
//(* ramstyle = "M9K" *) - synthesis attribute for making ramblocks of Altera M9K memory blocks
// !!! Not sure in its usefullness
// Variable to hold the registered read address, write data, and we
reg [ADDR_WIDTH-1:0] addr_reg;
reg [DATA_WIDTH-1:0] data_reg;
reg we_reg;
wire [ADDR_WIDTH-1:0] addr_x;
wire [DATA_WIDTH-1:0] data_x;
wire we_x;
// always @ (posedge clk)begin
// //memory reset
// if(memreset) counter<='d800;
// else if(counter!=0)
// begin
// counter<=counter-1;
// ramblock[counter-1]<=RAM_INITIAL_VALUE;
// end
// //R/W operations
// else if(enable) begin
// addr_reg <= addr;
// data_reg <= data;
// we_reg<=we;
// // Write
// if (we_reg) begin
// ramblock[addr_reg]<=data_reg;
// end
// end
// end
assign addr_x = (memenable) ? addr : resetcnt;
assign data_x = (memenable) ? data : '0;
assign we_x = (memenable) ? we : 1;
always @ (posedge clk)begin
addr_reg <= addr_x;
we_reg<=we_x;
data_reg <= data_x;
if (we_reg) begin ramblock[addr_reg]<=data_reg;
end
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ramblock[addr_reg];
endmodule |
module TestBench();
parameter RAMLENGTH = 800,
DATA_WIDTH=6,
ADDR_WIDTH=10,
V_BOTTOM = 1,
V_SYNC = 3,
V_TOP = 30,
H_FRONT = 80,
H_SYNC = 136,
H_BACK = 216,
RESOLUTION_H = 640,
RESOLUTION_V = 480,
X_WIRE_WIDTH = $clog2 (RESOLUTION_H+H_FRONT+H_SYNC+H_BACK),
Y_WIRE_WIDTH = $clog2 (RESOLUTION_V+V_BOTTOM+V_SYNC+V_TOP);
reg display_on, clk, memreset,reset_n,fifoempty;
reg [ADDR_WIDTH-1:0] resetcnt;
reg [X_WIRE_WIDTH-1:0] hpos;
reg [Y_WIRE_WIDTH-1:0] vpos;
reg [2:0] RGBin,RGB;
int hpos_check[10];
int vpos_check[10];
int RGB_check[10];
RGBMemory_top
#(
.RAMLENGTH(RAMLENGTH), //RAMLENGTH*DATAWIDTH = 4800 = 80x60 RAM RESOLUTION
.DATA_WIDTH(DATA_WIDTH),
.X_WIRE_WIDTH(X_WIRE_WIDTH),
.Y_WIRE_WIDTH(Y_WIRE_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.RESOLUTION_H(RESOLUTION_H),
.RESOLUTION_V(RESOLUTION_V)
)
FrameBuffer
(
.display_on(display_on),
.clk(clk),
.memreset(memreset),
.reset_n(~reset_n),
.resetcnt(resetcnt),
.RGBin(RGBin),
.hpos(hpos),
.vpos(vpos),
.RGB(RGB),
.fifoempty(fifoempty)
);
always #5 clk=~clk;
initial begin
fifoempty=0;
clk=0;
display_on=1;
RGBin=0;
resetcnt=0;
memreset=0;
hpos=0;
vpos=0;
RGB=0;
reset_n=0;
#20;
reset_n=1;
for(integer i=0; i<800; i++) begin
resetcnt<=i;
#10;
end
#15;
memreset=1;
#100
display_on=0;
vpos=0;
for(integer i=0; i<5; i++) begin
hpos=i;
if((i%2)==0) RGBin=3'b111;
else RGBin=3'b000;
#50;
end
#120;
display_on=1;
RGBin=0;
vpos=0;
for(integer i=0;i<31;i++) begin
hpos=i; #10;
end
#120
display_on=0;
vpos=1;
for(integer i=0; i<5; i++) begin
hpos=i;
if((i%2)==0) RGBin=3'b111;
else RGBin=3'b000;
#50;
end
#120
display_on=1;
RGBin=0;
vpos=0;
for(integer i=0;i<31;i++) begin
hpos=i; #10;
end
#120
display_on=0;
vpos=2;
for(integer i=0; i<5; i++) begin
hpos=i;
if((i%2)==0) RGBin=3'b111;
else RGBin=3'b000;
#50;
end
#120
display_on=1;
RGBin=0;
vpos=0;
for(integer i=0;i<31;i++) begin
hpos=i; #10;
end
#120
hpos=0;
vpos=0;
/*#100
display_on=0;
for(integer i=0; i<10; i++)begin
hpos=$urandom_range(0,79);
vpos=$urandom_range(0,59);
RGBin=$urandom_range(0,7);
hpos_check[i]=hpos;
vpos_check[i]=vpos;
RGB_check[i]=RGBin;
#50;
end
#10
display_on=1;
for(integer i=0; i<10; i++)begin
hpos=hpos_check[i]*8;
vpos=vpos_check[i]*8;
#10;
if(RGB!=RGB_check[i]) $display("Wrong data on the coordinates hpos=%d, vpos=%d. Supposed to be %d ",hpos,vpos, RGB_check[i]);
end
#10*/
$stop;
end
endmodule |
module Top_FB_TestBench();
reg clk, reset_n;
top DUT (
.clk(clk),
.reset_n(reset_n)
);
always #5 clk=~clk;
initial begin
clk=1;
reset_n=0;
#20;
reset_n=1;
end
endmodule |
module FIFOTestBench();
parameter RESOLUTION_H = 1280,
RESOLUTION_V = 960,
V_BOTTOM = 1,
V_SYNC = 3,
V_TOP = 30,
H_FRONT = 80,
H_SYNC = 136,
H_BACK = 216,
X_WIRE_WIDTH = $clog2 (RESOLUTION_H+H_FRONT+H_SYNC+H_BACK),
Y_WIRE_WIDTH = $clog2 (RESOLUTION_V+V_BOTTOM+V_SYNC+V_TOP),
FIFODEPTH=10;
reg clk,reset_n,push,pop,empty,full;
reg [X_WIRE_WIDTH-1:0] hpos,hpos_read;
reg [Y_WIRE_WIDTH-1:0] vpos,vpos_read;
reg [2:0] RGBin,RGB;
//int hpos_check[10];
//int vpos_check[10];
//int RGB_check[10];
FIFO_top
#(
.RESOLUTION_H(RESOLUTION_H),
.RESOLUTION_V(RESOLUTION_V),
.V_BOTTOM(V_BOTTOM),
.V_SYNC(V_SYNC),
.V_TOP(V_TOP),
.H_FRONT(H_FRONT),
.H_SYNC(H_SYNC),
.H_BACK(H_BACK),
.FIFODEPTH(FIFODEPTH)
)
DUT (
.clk(clk),
.rst(~reset_n),
.push(push),
.toppop(pop),
.hpos_write(hpos),
.vpos_write(vpos),
.RGB_write(RGBin),
.hpos_read(hpos_read),
.vpos_read(vpos_read),
.RGB_read(RGB),
.empty(empty),
.full(full)
);
always #5 clk=~clk;
initial begin
clk=0;
push=0;
pop=0;
hpos=0;
vpos=0;
hpos_read=0;
vpos_read=0;
RGBin=0;
reset_n=0;
#20;
reset_n=1;
#10
push=1;
for(integer i=0; i<10; i++) begin
hpos=$urandom_range(0,1279);
vpos=$urandom_range(0,959);
RGBin=$urandom_range(0,7);
#10;
end
push=0;
#10;
pop=1;
#550;
pop=0;
push=1;
for(integer i=0; i<7; i++) begin
hpos=$urandom_range(0,1279);
vpos=$urandom_range(0,959);
RGBin=$urandom_range(0,7);
#10;
end
push=0;
#10;
pop=1;
#120;
$stop;
end
endmodule |
module sm_rom_p1
#(
parameter SIZE = 64
)
(
input [31:0] a,
output [31:0] rd
);
reg [31:0] rom [SIZE - 1:0];
assign rd = rom [a];
initial begin
$readmemh ("p1_program.hex", rom);
end
endmodule |
module sm_rom_p0
#(
parameter SIZE = 64
)
(
input [31:0] a,
output [31:0] rd
);
reg [31:0] rom [SIZE - 1:0];
assign rd = rom [a];
initial begin
$readmemh ("p0_program.hex", rom);
end
endmodule |
module arbiter
#(
parameter N = 5 // Number of requesters
)(
input wire rst,
input wire clk,
input wire [N-1:0] req,
output wire [N-1:0] grant
);
reg [N-1:0] pointer_req;
//reg [N-1:0] next_grant;
wire [2*N-1:0] double_req = {req,req};
wire [2*N-1:0] double_grant = double_req & ~(double_req - pointer_req);
//Asynchronous grant update
// assign grant = (rst)? {N{1'b0}} : double_grant[N-1:0] | double_grant[2*N-1:N];
assign grant = double_grant[N-1:0] | double_grant[2*N-1:N];
//Update the rotate pointer
wire [N-1:0] new_req = req ^ grant;
wire [2*N-1:0] new_double_req = {new_req,new_req};
wire [2*N-1:0] new_double_grant = new_double_req & ~(new_double_req - pointer_req);
wire [N-1:0] async_pointer_req = new_double_grant[N-1:0] | new_double_grant[2*N-1:N];
always @ (posedge clk)
if (rst || async_pointer_req == 0)
pointer_req <= #1 1;
else
pointer_req <= #1 async_pointer_req;
endmodule |
module mfp_uart_receiver (
input clock,
input reset_n,
input rx,
output reg [7:0] byte_data,
output byte_ready
);
parameter clock_frequency = 50000000;
parameter baud_rate = 9600;
parameter clock_cycles_in_symbol = clock_frequency / baud_rate;
// Synchronize rx input to clock
reg rx_sync1, rx_sync;
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
rx_sync1 <= 1'b1;
rx_sync <= 1'b1;
end else begin
rx_sync1 <= rx;
rx_sync <= rx_sync1;
end
end
// Finding edge for start bit
reg prev_rx_sync;
always @(posedge clock or negedge reset_n) begin
if (!reset_n) prev_rx_sync <= 1'b1;
else prev_rx_sync <= rx_sync;
end
wire start_bit_edge = prev_rx_sync & !rx_sync;
// Counter to measure distance between symbols
reg [31:0] counter;
reg load_counter;
reg [31:0] load_counter_value;
always @(posedge clock or negedge reset_n) begin
if (!reset_n) counter <= 32'b0;
else if (load_counter) counter <= load_counter_value;
else if (counter != 0) counter <= counter - 1;
end
wire counter_done = counter == 1;
// Shift register to accumulate data
reg shift;
reg [7:0] shifted_1;
assign byte_ready = shifted_1[0];
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
shifted_1 <= 8'b0;
end else if (shift) begin
if (shifted_1 == 0) shifted_1 <= 8'b10000000;
else shifted_1 <= shifted_1 >> 1;
byte_data <= {rx, byte_data[7:1]};
end else if (byte_ready) begin
shifted_1 <= 8'b0;
end
end
reg idle, idle_r;
always @* begin
idle = idle_r;
shift = 1'b0;
load_counter = 32'b0;
load_counter_value = 32'b0;
if (idle) begin
if (start_bit_edge) begin
load_counter = 1;
load_counter_value = clock_cycles_in_symbol * 3 / 2;
idle = 1'b0;
end
end else if (counter_done) begin
shift = 1'b1;
load_counter = 1;
load_counter_value = clock_cycles_in_symbol;
end else if (byte_ready) begin
idle = 1'b1;
end
end
always @(posedge clock or negedge reset_n) begin
if (!reset_n) idle_r <= 1'b1;
else idle_r <= idle;
end
endmodule |
module data_aggregator (
input clock,
input reset,
input enter,
input add,
input multiply,
input separator,
input [3:0] data,
output reg [7:0] number,
output reg enter_occured
);
always @(posedge clock) begin
if (reset) begin
number <= 8'b0;
enter_occured <= 1'b0;
end else if (enter) begin
number <= {number[3:0], data};
enter_occured <= 1'b1;
end else if (add || multiply) begin
enter_occured <= 1'b0;
end else if (separator) begin
number <= 8'b0;
end
end
endmodule |
module two_bytes_uart_tx (
input clock,
input start,
input reset,
input [15:0] data,
output reg q,
output busy
);
reg [12:0] cnt;
reg [3:0] bit_num;
wire bit_start = (cnt == 5208);
wire idle = (bit_num == 4'hF);
assign busy = ~idle;
reg byte_state;
wire [7:0] word = byte_state ? data[7:0] : data[15:8];
always @(posedge clock) begin
if (reset) cnt <= 13'b0;
else if (start && idle) cnt <= 13'b0;
else if (bit_start) cnt <= 13'b0;
else cnt <= cnt + 13'b1;
end
always @(posedge clock) begin
if (reset) begin
bit_num <= 4'hf;
byte_state <= 1'b0;
q <= 1'b1;
end else if (start && idle) begin
bit_num <= 4'h0;
byte_state <= 1'b0;
q <= 1'b1;
end else if (bit_start) begin
case (bit_num)
4'h0: begin bit_num <= 4'h1; q <= 1'b0; end // start
4'h1: begin bit_num <= 4'h2; q <= word[0]; end
4'h2: begin bit_num <= 4'h3; q <= word[1]; end
4'h3: begin bit_num <= 4'h4; q <= word[2]; end
4'h4: begin bit_num <= 4'h5; q <= word[3]; end
4'h5: begin bit_num <= 4'h6; q <= word[4]; end
4'h6: begin bit_num <= 4'h7; q <= word[5]; end
4'h7: begin bit_num <= 4'h8; q <= word[6]; end
4'h8: begin bit_num <= 4'h9; q <= word[7]; end
4'h9: begin bit_num <= 4'ha; q <= 1'b1; // finish
if (!byte_state) begin
byte_state <= 1'b1;
bit_num <= 4'h0;
end
end
default: begin bit_num <= 4'hF; end // Stop
endcase
end
end
endmodule |
module uart_transmitter (
input clock,
input start,
input reset,
input [15:0] data,
output reg q,
output busy
);
parameter clock_frequency = 50000000;
parameter baud_rate = 9600;
parameter clock_cycles_in_bit = clock_frequency / baud_rate;
reg [12:0] cnt;
reg [3:0] bit_num;
wire bit_start = (cnt == clock_cycles_in_bit);
wire idle = (bit_num == 4'hF);
assign busy = ~idle;
reg byte_state;
wire [7:0] word = byte_state ? data[7:0] : data[15:8];
always @(posedge clock) begin
if (reset) cnt <= 13'b0;
else if (start && idle) cnt <= 13'b0;
else if (bit_start) cnt <= 13'b0;
else cnt <= cnt + 13'b1;
end
always @(posedge clock) begin
if (reset) begin
bit_num <= 4'hF;
byte_state <= 1'b0;
q <= 1'b1;
end else if (start && idle) begin
bit_num <= 4'h0;
byte_state <= 1'b0;
q <= 1'b1;
end else if (bit_start) begin
case (bit_num)
4'h0: begin bit_num <= 4'h1; q <= 1'b0; end // start
4'h1: begin bit_num <= 4'h2; q <= word[0]; end
4'h2: begin bit_num <= 4'h3; q <= word[1]; end
4'h3: begin bit_num <= 4'h4; q <= word[2]; end
4'h4: begin bit_num <= 4'h5; q <= word[3]; end
4'h5: begin bit_num <= 4'h6; q <= word[4]; end
4'h6: begin bit_num <= 4'h7; q <= word[5]; end
4'h7: begin bit_num <= 4'h8; q <= word[6]; end
4'h8: begin bit_num <= 4'h9; q <= word[7]; end
4'h9: begin bit_num <= 4'ha; q <= 1'b1; // finish
if (!byte_state) begin
byte_state <= 1'b1;
bit_num <= 4'h0;
end
end
default: begin bit_num <= 4'hF; end // Stop
endcase
end
end
endmodule |
module top (
input clock,
input reset_n,
input rx,
output reg tx,
output reg [7:0] abcdefgh,
output reg [3:0] nx_digit
);
wire byte_ready;
wire [7:0] ascii_data;
uart_receiver listener (
.clock (clock),
.reset_n(reset_n),
.rx (rx),
.byte_data (ascii_data),
.byte_ready(byte_ready)
);
wire separator, add, multiply, enter, clear, error_ascii;
wire [3:0] digit;
ascii_to_action translator (
.clock(clock),
.start(byte_ready),
.reset(~reset_n),
.data (ascii_data),
.separator(separator),
.add (add),
.multiply (multiply),
.digit (digit),
.enter (enter),
.clear (clear),
.error (error_ascii)
);
// Prepare and accumulate data
logic [7:0] number;
logic enter_occured;
data_aggregator aggregator (
.clock (clock),
.reset (~reset_n),
.enter (enter),
.add (add),
.multiply (multiply),
.separator(separator),
.data (digit),
.number (number),
.enter_occured(enter_occured)
);
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire [15:0] result;
wire overflow, newresult;
wire [3:0] error_calculator;
wire is_tx_busy;
calculator calculator (
.clock (clock),
.reset (~reset_n || clear),
.enter (separator & enter_occured),
.add (add),
.multiply(multiply),
.data (number),
.newresult(newresult),
.result (result),
.overflow (overflow),
.error (error_calculator)
);
seven_segment_4_digits display (
.clock (clock),
.reset (~reset_n),
.number(result),
.digit (nx_digit),
.abcdefgh(abcdefgh)
);
uart_transmitter loader (
.clock(clock),
.reset(~reset_n),
.start(newresult),
.data (result),
.q (tx),
.busy(is_tx_busy)
);
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [96-1 : 0] sink_data, // ST_DATA_W=96
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [96-1 : 0] src0_data, // ST_DATA_W=96
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [96-1 : 0] src1_data, // ST_DATA_W=96
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module DE0_NANO_SOC_QSYS_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[0] = receiver0_irq;
sender_irq[1] = receiver1_irq;
end
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [96-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [96-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 96 + 6 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 60;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_mux_001
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [96-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [96-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [96-1 : 0] sink2_data,
input [6-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [96-1 : 0] sink3_data,
input [6-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [96-1 : 0] sink4_data,
input [6-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [96-1 : 0] sink5_data,
input [6-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [96-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 96 + 6 + 2;
localparam NUM_INPUTS = 6;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 60;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[60];
lock[1] = sink1_data[60];
lock[2] = sink2_data[60];
lock[3] = sink3_data[60];
lock[4] = sink4_data[60];
lock[5] = sink5_data[60];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 3
)
(output [82 - 80 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[82 - 80 : 0];
generate begin : default_decode
if (DEFAULT_CHANNEL == -1) begin
assign default_src_channel = '0;
end
else begin
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
end
endgenerate
generate begin : default_decode_rw
if (DEFAULT_RD_CHANNEL == -1) begin
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
end
endgenerate
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [96-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [96-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 55;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 82;
localparam PKT_DEST_ID_L = 80;
localparam PKT_PROTECTION_H = 86;
localparam PKT_PROTECTION_L = 84;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 58;
localparam PKT_TRANS_READ = 59;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h80000 - 64'h40000);
localparam PAD1 = log2ceil(64'h81000 - 64'h80800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h81000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [6-1 : 0] default_src_channel;
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x40000 .. 0x80000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h40000 ) begin
src_channel = 6'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x80800 .. 0x81000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h80800 ) begin
src_channel = 6'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [96-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [96-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [96-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 96 + 6 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 60;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[60];
lock[1] = sink1_data[60];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [96-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [96-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 55;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 82;
localparam PKT_DEST_ID_L = 80;
localparam PKT_PROTECTION_H = 86;
localparam PKT_PROTECTION_L = 84;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 58;
localparam PKT_TRANS_READ = 59;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10 - 64'h0);
localparam PAD1 = log2ceil(64'h80000 - 64'h40000);
localparam PAD2 = log2ceil(64'h81000 - 64'h80800);
localparam PAD3 = log2ceil(64'h81008 - 64'h81000);
localparam PAD4 = log2ceil(64'h81010 - 64'h81008);
localparam PAD5 = log2ceil(64'h81018 - 64'h81010);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h81018;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [6-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x10 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h0 ) begin
src_channel = 6'b100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x40000 .. 0x80000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h40000 ) begin
src_channel = 6'b000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x80800 .. 0x81000 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 20'h80800 ) begin
src_channel = 6'b000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x81000 .. 0x81008 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 20'h81000 ) begin
src_channel = 6'b001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x81008 .. 0x81010 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 20'h81008 && read_transaction ) begin
src_channel = 6'b000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x81010 .. 0x81018 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 20'h81010 ) begin
src_channel = 6'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
Subsets and Splits