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module sysmem_HPS_fpga_interfaces
(
// h2f_reset
output wire [1 - 1 : 0 ] h2f_rst_n
// f2h_cold_reset_req
,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
// f2h_warm_reset_req
,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
// h2f_user0_clock
,output wire [1 - 1 : 0 ] h2f_user0_clk
// f2h_sdram0_data
,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram0_READ
,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
// f2h_sdram0_clock
,input wire [1 - 1 : 0 ] f2h_sdram0_clk
// f2h_sdram1_data
,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram1_READ
,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
// f2h_sdram1_clock
,input wire [1 - 1 : 0 ] f2h_sdram1_clk
// f2h_sdram2_data
,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram2_READ
,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
// f2h_sdram2_clock
,input wire [1 - 1 : 0 ] f2h_sdram2_clk
,input uart_cts // uart.cts
,input uart_dsr // .dsr
,input uart_dcd // .dcd
,input uart_ri // .ri
,output uart_dtr // .dtr
,output uart_rts // .rts
,output uart_out1_n // .out1_n
,output uart_out2_n // .out2_n
,input uart_rxd // .rxd
,output uart_txd // .txd
);
wire [29 - 1 : 0] intermediate;
assign intermediate[0:0] = ~intermediate[1:1];
assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
assign intermediate[2:2] = intermediate[9:9];
assign intermediate[3:3] = intermediate[9:9];
assign intermediate[5:5] = intermediate[9:9];
assign intermediate[6:6] = intermediate[9:9];
assign intermediate[10:10] = intermediate[9:9];
assign intermediate[11:11] = ~intermediate[12:12];
assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
assign intermediate[13:13] = intermediate[18:18];
assign intermediate[15:15] = intermediate[18:18];
assign intermediate[19:19] = intermediate[18:18];
assign intermediate[20:20] = ~intermediate[21:21];
assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
assign intermediate[22:22] = intermediate[27:27];
assign intermediate[24:24] = intermediate[27:27];
assign intermediate[28:28] = intermediate[27:27];
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
assign intermediate[4:4] = f2h_sdram0_READ[0:0];
assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
assign intermediate[9:9] = f2h_sdram0_clk[0:0];
assign intermediate[14:14] = f2h_sdram1_READ[0:0];
assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
assign intermediate[18:18] = f2h_sdram1_clk[0:0];
assign intermediate[23:23] = f2h_sdram2_READ[0:0];
assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
assign intermediate[27:27] = f2h_sdram2_clk[0:0];
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_warm_rst_req_n({
f2h_warm_rst_req_n[0:0] // 0:0
})
,.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_dbg_rst_req_n({
1'b1 // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
f2h_cold_rst_req_n[0:0] // 0:0
})
,.h2f_user0_clk({
h2f_user0_clk[0:0] // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cfg_rfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.cfg_wfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.rd_ready_3({
1'b1 // 0:0
})
,.cmd_port_clk_2({
intermediate[28:28] // 0:0
})
,.rd_ready_2({
1'b1 // 0:0
})
,.cmd_port_clk_1({
intermediate[19:19] // 0:0
})
,.rd_ready_1({
1'b1 // 0:0
})
,.cmd_port_clk_0({
intermediate[10:10] // 0:0
})
,.rd_ready_0({
1'b1 // 0:0
})
,.wrack_ready_2({
1'b1 // 0:0
})
,.wrack_ready_1({
1'b1 // 0:0
})
,.wrack_ready_0({
1'b1 // 0:0
})
,.cmd_ready_2({
intermediate[21:21] // 0:0
})
,.cmd_ready_1({
intermediate[12:12] // 0:0
})
,.cmd_ready_0({
intermediate[1:1] // 0:0
})
,.cfg_port_width({
12'b000000010110 // 11:0
})
,.rd_valid_3({
f2h_sdram2_READDATAVALID[0:0] // 0:0
})
,.rd_valid_2({
f2h_sdram1_READDATAVALID[0:0] // 0:0
})
,.rd_valid_1({
f2h_sdram0_READDATAVALID[0:0] // 0:0
})
,.rd_clk_3({
intermediate[22:22] // 0:0
})
,.rd_data_3({
f2h_sdram2_READDATA[63:0] // 63:0
})
,.rd_clk_2({
intermediate[13:13] // 0:0
})
,.rd_data_2({
f2h_sdram1_READDATA[63:0] // 63:0
})
,.rd_clk_1({
intermediate[3:3] // 0:0
})
,.rd_data_1({
f2h_sdram0_READDATA[127:64] // 63:0
})
,.rd_clk_0({
intermediate[2:2] // 0:0
})
,.rd_data_0({
f2h_sdram0_READDATA[63:0] // 63:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
,.cmd_valid_2({
intermediate[26:26] // 0:0
})
,.cmd_valid_1({
intermediate[17:17] // 0:0
})
,.cmd_valid_0({
intermediate[8:8] // 0:0
})
,.cfg_cport_rfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_data_3({
2'b00 // 89:88
,f2h_sdram2_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram2_WRITEDATA[63:0] // 63:0
})
,.wr_data_2({
2'b00 // 89:88
,f2h_sdram1_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram1_WRITEDATA[63:0] // 63:0
})
,.wr_data_1({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[15:8] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[127:64] // 63:0
})
,.cfg_cport_type({
12'b000000111111 // 11:0
})
,.wr_data_0({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[63:0] // 63:0
})
,.cfg_cport_wfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_clk_3({
intermediate[24:24] // 0:0
})
,.wr_clk_2({
intermediate[15:15] // 0:0
})
,.wr_clk_1({
intermediate[6:6] // 0:0
})
,.wr_clk_0({
intermediate[5:5] // 0:0
})
,.cmd_data_2({
18'b000000000000000000 // 59:42
,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram2_ADDRESS[28:0] // 30:2
,intermediate[25:25] // 1:1
,intermediate[23:23] // 0:0
})
,.cmd_data_1({
18'b000000000000000000 // 59:42
,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram1_ADDRESS[28:0] // 30:2
,intermediate[16:16] // 1:1
,intermediate[14:14] // 0:0
})
,.cmd_data_0({
18'b000000000000000000 // 59:42
,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
,4'b0000 // 33:30
,f2h_sdram0_ADDRESS[27:0] // 29:2
,intermediate[7:7] // 1:1
,intermediate[4:4] // 0:0
})
);
cyclonev_hps_interface_peripheral_uart peripheral_uart1
(
.txd(uart_txd)
,.cts(uart_cts)
,.out1_n(uart_out1_n)
,.dtr(uart_dtr)
,.rts(uart_rts)
,.out2_n(uart_out2_n)
,.rxd(uart_rxd)
,.ri(uart_ri)
,.dsr(uart_dsr)
,.dcd(uart_dcd)
);
endmodule |
module uncore_axi_xbar #(
parameter int unsigned AXI_ADDR_WIDTH = 64,
parameter int unsigned AXI_DATA_WIDTH = 32,
parameter int unsigned AXI_ID_WIDTH = 4,
parameter int unsigned AXI_USER_WIDTH = 1
) (
input clk_i,
input rst_ni,
// AXI Interface -- slave 0
/*********************************************************************/
//AW channel
input [AXI_ID_WIDTH-1:0] slv0_aw_awid,
input [AXI_ADDR_WIDTH-1:0] slv0_aw_awaddr,
input [7:0] slv0_aw_awlen,
input [2:0] slv0_aw_awsize,
input [1:0] slv0_aw_awburst,
input slv0_aw_awlock,
input [3:0] slv0_aw_awcache,
input [2:0] slv0_aw_awprot,
input [3:0] slv0_aw_awqos,
input [3:0] slv0_aw_awregion,
input slv0_aw_awuser,//
input slv0_aw_awvalid,
output slv0_aw_awready,
//W channel
input [AXI_DATA_WIDTH-1:0] slv0_w_wdata,
input [AXI_DATA_WIDTH/8-1:0] slv0_w_wstrb,
input slv0_w_wlast,
input slv0_w_wuser,
input slv0_w_wvalid,
output slv0_w_wready,
//AXI4-B channel
output [AXI_ID_WIDTH-1:0] slv0_b_bid,
output [1:0] slv0_b_bresp,
output slv0_b_buser,
output slv0_b_bvalid,
input slv0_b_bready,
//AXI4-AR channel
input [AXI_ID_WIDTH-1:0] slv0_ar_arid,
input [AXI_ADDR_WIDTH-1:0] slv0_ar_araddr,
input [7:0] slv0_ar_arlen,
input [2:0] slv0_ar_arsize,
input [1:0] slv0_ar_arburst,
input slv0_ar_arlock,
input [3:0] slv0_ar_arcache,
input [2:0] slv0_ar_arprot,
input [3:0] slv0_ar_arqos,
input [3:0] slv0_ar_arregion,
input slv0_ar_aruser,
input slv0_ar_arvalid,
output slv0_ar_arready,
//AXI4-R channel
output [AXI_ID_WIDTH-1:0] slv0_r_rid,
output [AXI_DATA_WIDTH-1:0] slv0_r_rdata,
output [1:0] slv0_r_rresp,
output slv0_r_rlast,
output slv0_r_ruser,
output slv0_r_rvalid,
input slv0_r_rready,
/*********************************************************************/
// AXI Interface -- master 0
/*********************************************************************/
//AW channel
output [AXI_ID_WIDTH+0-1:0] mst0_aw_awid,
output [AXI_ADDR_WIDTH-1:0] mst0_aw_awaddr,
output [7:0] mst0_aw_awlen,
output [2:0] mst0_aw_awsize,
output [1:0] mst0_aw_awburst,
output mst0_aw_awlock,
output [3:0] mst0_aw_awcache,
output [2:0] mst0_aw_awprot,
output [3:0] mst0_aw_awqos,
output [3:0] mst0_aw_awregion,
output mst0_aw_awuser,//
output mst0_aw_awvalid,
input mst0_aw_awready,
//W channel
output [AXI_DATA_WIDTH-1:0] mst0_w_wdata,
output [AXI_DATA_WIDTH/8-1:0] mst0_w_wstrb,
output mst0_w_wlast,
output mst0_w_wuser,
output mst0_w_wvalid,
input mst0_w_wready,
//AXI4-B channel
input [AXI_ID_WIDTH+0-1:0] mst0_b_bid,
input [1:0] mst0_b_bresp,
input mst0_b_buser,
input mst0_b_bvalid,
output mst0_b_bready,
//AXI4-AR channel
output [AXI_ID_WIDTH+0-1:0] mst0_ar_arid,
output [AXI_ADDR_WIDTH-1:0] mst0_ar_araddr,
output [7:0] mst0_ar_arlen,
output [2:0] mst0_ar_arsize,
output [1:0] mst0_ar_arburst,
output mst0_ar_arlock,
output [3:0] mst0_ar_arcache,
output [2:0] mst0_ar_arprot,
output [3:0] mst0_ar_arqos,
output [3:0] mst0_ar_arregion,
output mst0_ar_aruser,
output mst0_ar_arvalid,
input mst0_ar_arready,
//AXI4-R channel
input [AXI_ID_WIDTH+0-1:0] mst0_r_rid,
input [AXI_DATA_WIDTH-1:0] mst0_r_rdata,
input [1:0] mst0_r_rresp,
input mst0_r_rlast,
input mst0_r_ruser,
input mst0_r_rvalid,
output mst0_r_rready,
/*********************************************************************/
// AXI Interface -- master 1
/*********************************************************************/
//AW channel
output [AXI_ID_WIDTH+0-1:0] mst1_aw_awid,
output [AXI_ADDR_WIDTH-1:0] mst1_aw_awaddr,
output [7:0] mst1_aw_awlen,
output [2:0] mst1_aw_awsize,
output [1:0] mst1_aw_awburst,
output mst1_aw_awlock,
output [3:0] mst1_aw_awcache,
output [2:0] mst1_aw_awprot,
output [3:0] mst1_aw_awqos,
output [3:0] mst1_aw_awregion,
output mst1_aw_awuser,//
output mst1_aw_awvalid,
input mst1_aw_awready,
//W channel
output [AXI_DATA_WIDTH-1:0] mst1_w_wdata,
output [AXI_DATA_WIDTH/8-1:0] mst1_w_wstrb,
output mst1_w_wlast,
output mst1_w_wuser,
output mst1_w_wvalid,
input mst1_w_wready,
//AXI4-B channel
input [AXI_ID_WIDTH+0-1:0] mst1_b_bid,
input [1:0] mst1_b_bresp,
input mst1_b_buser,
input mst1_b_bvalid,
output mst1_b_bready,
//AXI4-AR channel
output [AXI_ID_WIDTH+0-1:0] mst1_ar_arid,
output [AXI_ADDR_WIDTH-1:0] mst1_ar_araddr,
output [7:0] mst1_ar_arlen,
output [2:0] mst1_ar_arsize,
output [1:0] mst1_ar_arburst,
output mst1_ar_arlock,
output [3:0] mst1_ar_arcache,
output [2:0] mst1_ar_arprot,
output [3:0] mst1_ar_arqos,
output [3:0] mst1_ar_arregion,
output mst1_ar_aruser,
output mst1_ar_arvalid,
input mst1_ar_arready,
//AXI4-R channel
input [AXI_ID_WIDTH+0-1:0] mst1_r_rid,
input [AXI_DATA_WIDTH-1:0] mst1_r_rdata,
input [1:0] mst1_r_rresp,
input mst1_r_rlast,
input mst1_r_ruser,
input mst1_r_rvalid,
output mst1_r_rready,
/*********************************************************************/
// AXI Interface -- master 2
/*********************************************************************/
//AW channel
output [AXI_ID_WIDTH+0-1:0] mst2_aw_awid,
output [AXI_ADDR_WIDTH-1:0] mst2_aw_awaddr,
output [7:0] mst2_aw_awlen,
output [2:0] mst2_aw_awsize,
output [1:0] mst2_aw_awburst,
output mst2_aw_awlock,
output [3:0] mst2_aw_awcache,
output [2:0] mst2_aw_awprot,
output [3:0] mst2_aw_awqos,
output [3:0] mst2_aw_awregion,
output mst2_aw_awuser,//
output mst2_aw_awvalid,
input mst2_aw_awready,
//W channel
output [AXI_DATA_WIDTH-1:0] mst2_w_wdata,
output [AXI_DATA_WIDTH/8-1:0] mst2_w_wstrb,
output mst2_w_wlast,
output mst2_w_wuser,
output mst2_w_wvalid,
input mst2_w_wready,
//AXI4-B channel
input [AXI_ID_WIDTH+0-1:0] mst2_b_bid,
input [1:0] mst2_b_bresp,
input mst2_b_buser,
input mst2_b_bvalid,
output mst2_b_bready,
//AXI4-AR channel
output [AXI_ID_WIDTH+0-1:0] mst2_ar_arid,
output [AXI_ADDR_WIDTH-1:0] mst2_ar_araddr,
output [7:0] mst2_ar_arlen,
output [2:0] mst2_ar_arsize,
output [1:0] mst2_ar_arburst,
output mst2_ar_arlock,
output [3:0] mst2_ar_arcache,
output [2:0] mst2_ar_arprot,
output [3:0] mst2_ar_arqos,
output [3:0] mst2_ar_arregion,
output mst2_ar_aruser,
output mst2_ar_arvalid,
input mst2_ar_arready,
//AXI4-R channel
input [AXI_ID_WIDTH+0-1:0] mst2_r_rid,
input [AXI_DATA_WIDTH-1:0] mst2_r_rdata,
input [1:0] mst2_r_rresp,
input mst2_r_rlast,
input mst2_r_ruser,
input mst2_r_rvalid,
output mst2_r_rready
/*********************************************************************/
);
localparam axi_pkg::xbar_cfg_t XBarCfg = '{
NoSlvPorts : 1,
NoMstPorts : 3,
MaxMstTrans : 4,
MaxSlvTrans : 4,
FallThrough : 1'b0,
LatencyMode : axi_pkg::CUT_MST_PORTS,
AxiIdWidthSlvPorts: AXI_ID_WIDTH,
AxiIdUsedSlvPorts : AXI_ID_WIDTH,
UniqueIds : 1'b0,
AxiAddrWidth : AXI_ADDR_WIDTH,
AxiDataWidth : AXI_DATA_WIDTH,
NoAddrRules : 3
};
axi_pkg::xbar_rule_64_t [3-1:0] routing_rules;
assign routing_rules = '{
'{idx: 0, start_addr: 64'h40300000, end_addr: 64'h4030ffff},
'{idx: 1, start_addr: 64'h40100000, end_addr: 64'h4012ffff},
'{idx: 2, start_addr: 64'h40000000, end_addr: 64'h4001ffff}
};
localparam int unsigned AxiIdWidthMstPorts = XBarCfg.AxiIdWidthSlvPorts + $clog2(XBarCfg.NoSlvPorts);
typedef logic [AxiIdWidthMstPorts -1:0] id_mst_t;
typedef logic [XBarCfg.AxiIdWidthSlvPorts -1:0] id_slv_t;
typedef logic [XBarCfg.AxiAddrWidth -1:0] addr_t;
typedef logic [XBarCfg.AxiDataWidth -1:0] data_t;
typedef logic [XBarCfg.AxiDataWidth/8 -1:0] strb_t;
typedef logic [AXI_USER_WIDTH -1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, id_mst_t, user_t)
`AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, id_slv_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_mst_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_slv_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, id_mst_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_slv_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_mst_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_slv_t, user_t)
`AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t)
`AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t)
`AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t)
`AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t)
mst_req_t [XBarCfg.NoMstPorts-1:0] mst_reqs;
mst_resp_t [XBarCfg.NoMstPorts-1:0] mst_resps;
slv_req_t [XBarCfg.NoSlvPorts-1:0] slv_reqs;
slv_resp_t [XBarCfg.NoSlvPorts-1:0] slv_resps;
//for (genvar i = 0; i < XBarCfg.NoMstPorts; i++) begin : gen_assign_mst
// `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i])
// `AXI_ASSIGN_TO_RESP(mst_resps[i], mst_ports[i])
//end
//for (genvar i = 0; i < XBarCfg.NoSlvPorts; i++) begin : gen_assign_slv
// `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i])
// `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_resps[i])
//end
//AXI slave0 interface connection
/*********************************************************************/
/*request*/
assign slv_reqs[0].aw.id = slv0_aw_awid ;
assign slv_reqs[0].aw.addr = slv0_aw_awaddr ;
assign slv_reqs[0].aw.len = slv0_aw_awlen ;
assign slv_reqs[0].aw.size = slv0_aw_awsize ;
assign slv_reqs[0].aw.burst = slv0_aw_awburst ;
assign slv_reqs[0].aw.lock = slv0_aw_awlock ;
assign slv_reqs[0].aw.cache = slv0_aw_awcache ;
assign slv_reqs[0].aw.prot = slv0_aw_awprot ;
assign slv_reqs[0].aw.region = slv0_aw_awregion ;
assign slv_reqs[0].aw.qos = slv0_aw_awqos ;
assign slv_reqs[0].aw.atop = 6'd0 ;
assign slv_reqs[0].aw.user = slv0_aw_awuser ;
assign slv_reqs[0].aw_valid = slv0_aw_awvalid ;
assign slv_reqs[0].w.data = slv0_w_wdata ;
assign slv_reqs[0].w.strb = slv0_w_wstrb ;
assign slv_reqs[0].w.last = slv0_w_wlast ;
assign slv_reqs[0].w.user = slv0_w_wuser ;
assign slv_reqs[0].w_valid = slv0_w_wvalid ;
assign slv_reqs[0].b_ready = slv0_b_bready ;
assign slv_reqs[0].ar.id = slv0_ar_arid ;
assign slv_reqs[0].ar.addr = slv0_ar_araddr ;
assign slv_reqs[0].ar.len = slv0_ar_arlen ;
assign slv_reqs[0].ar.size = slv0_ar_arsize ;
assign slv_reqs[0].ar.burst = slv0_ar_arburst ;
assign slv_reqs[0].ar.lock = slv0_ar_arlock ;
assign slv_reqs[0].ar.cache = slv0_ar_arcache ;
assign slv_reqs[0].ar.prot = slv0_ar_arprot ;
assign slv_reqs[0].ar.region = slv0_ar_arregion ;
assign slv_reqs[0].ar.qos = slv0_ar_arqos ;
assign slv_reqs[0].ar.user = slv0_ar_aruser ;
assign slv_reqs[0].ar_valid = slv0_ar_arvalid ;
assign slv_reqs[0].r_ready = slv0_r_rready ;
/*response*/
assign slv0_aw_awready = slv_resps[0].aw_ready ;
assign slv0_w_wready = slv_resps[0].w_ready ;
assign slv0_b_bid = slv_resps[0].b.id ;
assign slv0_b_bresp = slv_resps[0].b.resp ;
assign slv0_b_buser = slv_resps[0].b.user ;
assign slv0_b_bvalid = slv_resps[0].b_valid ;
assign slv0_ar_arready = slv_resps[0].ar_ready ;
assign slv0_r_rid = slv_resps[0].r.id ;
assign slv0_r_rdata = slv_resps[0].r.data ;
assign slv0_r_rresp = slv_resps[0].r.resp ;
assign slv0_r_rlast = slv_resps[0].r.last ;
assign slv0_r_ruser = slv_resps[0].r.user ;
assign slv0_r_rvalid = slv_resps[0].r_valid ;
/*********************************************************************/
//AXI Master0 interface connection
/*********************************************************************/
/*request*/
assign mst0_aw_awid = mst_reqs[0].aw.id ;
assign mst0_aw_awaddr = mst_reqs[0].aw.addr ;
assign mst0_aw_awlen = mst_reqs[0].aw.len ;
assign mst0_aw_awsize = mst_reqs[0].aw.size ;
assign mst0_aw_awburst = mst_reqs[0].aw.burst ;
assign mst0_aw_awlock = mst_reqs[0].aw.lock ;
assign mst0_aw_awcache = mst_reqs[0].aw.cache ;
assign mst0_aw_awprot = mst_reqs[0].aw.prot ;
assign mst0_aw_awregion = mst_reqs[0].aw.region ;
assign mst0_aw_awqos = mst_reqs[0].aw.qos ;
assign mst0_aw_awuser = mst_reqs[0].aw.user ;
assign mst0_aw_awvalid = mst_reqs[0].aw_valid ;
assign mst0_w_wdata = mst_reqs[0].w.data ;
assign mst0_w_wstrb = mst_reqs[0].w.strb ;
assign mst0_w_wlast = mst_reqs[0].w.last ;
assign mst0_w_wuser = mst_reqs[0].w.user ;
assign mst0_w_wvalid = mst_reqs[0].w_valid ;
assign mst0_b_bready = mst_reqs[0].b_ready ;
assign mst0_ar_arid = mst_reqs[0].ar.id ;
assign mst0_ar_araddr = mst_reqs[0].ar.addr ;
assign mst0_ar_arlen = mst_reqs[0].ar.len ;
assign mst0_ar_arsize = mst_reqs[0].ar.size ;
assign mst0_ar_arburst = mst_reqs[0].ar.burst ;
assign mst0_ar_arlock = mst_reqs[0].ar.lock ;
assign mst0_ar_arcache = mst_reqs[0].ar.cache ;
assign mst0_ar_arprot = mst_reqs[0].ar.prot ;
assign mst0_ar_arregion = mst_reqs[0].ar.region ;
assign mst0_ar_arqos = mst_reqs[0].ar.qos ;
assign mst0_ar_aruser = mst_reqs[0].ar.user ;
assign mst0_ar_arvalid = mst_reqs[0].ar_valid ;
assign mst0_r_rready = mst_reqs[0].r_ready ;
/*response*/
assign mst_resps[0].aw_ready = mst0_aw_awready ;
assign mst_resps[0].w_ready = mst0_w_wready ;
assign mst_resps[0].b.id = mst0_b_bid ;
assign mst_resps[0].b.resp = mst0_b_bresp ;
assign mst_resps[0].b.user = mst0_b_buser ;
assign mst_resps[0].b_valid = mst0_b_bvalid ;
assign mst_resps[0].ar_ready = mst0_ar_arready ;
assign mst_resps[0].r.id = mst0_r_rid ;
assign mst_resps[0].r.data = mst0_r_rdata ;
assign mst_resps[0].r.resp = mst0_r_rresp ;
assign mst_resps[0].r.last = mst0_r_rlast ;
assign mst_resps[0].r.user = mst0_r_ruser ;
assign mst_resps[0].r_valid = mst0_r_rvalid ;
/*********************************************************************/
//AXI Master1 interface connection
/*********************************************************************/
/*request*/
assign mst1_aw_awid = mst_reqs[1].aw.id ;
assign mst1_aw_awaddr = mst_reqs[1].aw.addr ;
assign mst1_aw_awlen = mst_reqs[1].aw.len ;
assign mst1_aw_awsize = mst_reqs[1].aw.size ;
assign mst1_aw_awburst = mst_reqs[1].aw.burst ;
assign mst1_aw_awlock = mst_reqs[1].aw.lock ;
assign mst1_aw_awcache = mst_reqs[1].aw.cache ;
assign mst1_aw_awprot = mst_reqs[1].aw.prot ;
assign mst1_aw_awregion = mst_reqs[1].aw.region ;
assign mst1_aw_awqos = mst_reqs[1].aw.qos ;
assign mst1_aw_awuser = mst_reqs[1].aw.user ;
assign mst1_aw_awvalid = mst_reqs[1].aw_valid ;
assign mst1_w_wdata = mst_reqs[1].w.data ;
assign mst1_w_wstrb = mst_reqs[1].w.strb ;
assign mst1_w_wlast = mst_reqs[1].w.last ;
assign mst1_w_wuser = mst_reqs[1].w.user ;
assign mst1_w_wvalid = mst_reqs[1].w_valid ;
assign mst1_b_bready = mst_reqs[1].b_ready ;
assign mst1_ar_arid = mst_reqs[1].ar.id ;
assign mst1_ar_araddr = mst_reqs[1].ar.addr ;
assign mst1_ar_arlen = mst_reqs[1].ar.len ;
assign mst1_ar_arsize = mst_reqs[1].ar.size ;
assign mst1_ar_arburst = mst_reqs[1].ar.burst ;
assign mst1_ar_arlock = mst_reqs[1].ar.lock ;
assign mst1_ar_arcache = mst_reqs[1].ar.cache ;
assign mst1_ar_arprot = mst_reqs[1].ar.prot ;
assign mst1_ar_arregion = mst_reqs[1].ar.region ;
assign mst1_ar_arqos = mst_reqs[1].ar.qos ;
assign mst1_ar_aruser = mst_reqs[1].ar.user ;
assign mst1_ar_arvalid = mst_reqs[1].ar_valid ;
assign mst1_r_rready = mst_reqs[1].r_ready ;
/*response*/
assign mst_resps[1].aw_ready = mst1_aw_awready ;
assign mst_resps[1].w_ready = mst1_w_wready ;
assign mst_resps[1].b.id = mst1_b_bid ;
assign mst_resps[1].b.resp = mst1_b_bresp ;
assign mst_resps[1].b.user = mst1_b_buser ;
assign mst_resps[1].b_valid = mst1_b_bvalid ;
assign mst_resps[1].ar_ready = mst1_ar_arready ;
assign mst_resps[1].r.id = mst1_r_rid ;
assign mst_resps[1].r.data = mst1_r_rdata ;
assign mst_resps[1].r.resp = mst1_r_rresp ;
assign mst_resps[1].r.last = mst1_r_rlast ;
assign mst_resps[1].r.user = mst1_r_ruser ;
assign mst_resps[1].r_valid = mst1_r_rvalid ;
/*********************************************************************/
//AXI Master2 interface connection
/*********************************************************************/
/*request*/
assign mst2_aw_awid = mst_reqs[2].aw.id ;
assign mst2_aw_awaddr = mst_reqs[2].aw.addr ;
assign mst2_aw_awlen = mst_reqs[2].aw.len ;
assign mst2_aw_awsize = mst_reqs[2].aw.size ;
assign mst2_aw_awburst = mst_reqs[2].aw.burst ;
assign mst2_aw_awlock = mst_reqs[2].aw.lock ;
assign mst2_aw_awcache = mst_reqs[2].aw.cache ;
assign mst2_aw_awprot = mst_reqs[2].aw.prot ;
assign mst2_aw_awregion = mst_reqs[2].aw.region ;
assign mst2_aw_awqos = mst_reqs[2].aw.qos ;
assign mst2_aw_awuser = mst_reqs[2].aw.user ;
assign mst2_aw_awvalid = mst_reqs[2].aw_valid ;
assign mst2_w_wdata = mst_reqs[2].w.data ;
assign mst2_w_wstrb = mst_reqs[2].w.strb ;
assign mst2_w_wlast = mst_reqs[2].w.last ;
assign mst2_w_wuser = mst_reqs[2].w.user ;
assign mst2_w_wvalid = mst_reqs[2].w_valid ;
assign mst2_b_bready = mst_reqs[2].b_ready ;
assign mst2_ar_arid = mst_reqs[2].ar.id ;
assign mst2_ar_araddr = mst_reqs[2].ar.addr ;
assign mst2_ar_arlen = mst_reqs[2].ar.len ;
assign mst2_ar_arsize = mst_reqs[2].ar.size ;
assign mst2_ar_arburst = mst_reqs[2].ar.burst ;
assign mst2_ar_arlock = mst_reqs[2].ar.lock ;
assign mst2_ar_arcache = mst_reqs[2].ar.cache ;
assign mst2_ar_arprot = mst_reqs[2].ar.prot ;
assign mst2_ar_arregion = mst_reqs[2].ar.region ;
assign mst2_ar_arqos = mst_reqs[2].ar.qos ;
assign mst2_ar_aruser = mst_reqs[2].ar.user ;
assign mst2_ar_arvalid = mst_reqs[2].ar_valid ;
assign mst2_r_rready = mst_reqs[2].r_ready ;
/*response*/
assign mst_resps[2].aw_ready = mst2_aw_awready ;
assign mst_resps[2].w_ready = mst2_w_wready ;
assign mst_resps[2].b.id = mst2_b_bid ;
assign mst_resps[2].b.resp = mst2_b_bresp ;
assign mst_resps[2].b.user = mst2_b_buser ;
assign mst_resps[2].b_valid = mst2_b_bvalid ;
assign mst_resps[2].ar_ready = mst2_ar_arready ;
assign mst_resps[2].r.id = mst2_r_rid ;
assign mst_resps[2].r.data = mst2_r_rdata ;
assign mst_resps[2].r.resp = mst2_r_rresp ;
assign mst_resps[2].r.last = mst2_r_rlast ;
assign mst_resps[2].r.user = mst2_r_ruser ;
assign mst_resps[2].r_valid = mst2_r_rvalid ;
/*********************************************************************/
axi_xbar #(
.Cfg ( XBarCfg ),
.slv_aw_chan_t ( slv_aw_chan_t ),
.mst_aw_chan_t ( mst_aw_chan_t ),
.w_chan_t ( w_chan_t ),
.slv_b_chan_t ( slv_b_chan_t ),
.mst_b_chan_t ( mst_b_chan_t ),
.slv_ar_chan_t ( slv_ar_chan_t ),
.mst_ar_chan_t ( mst_ar_chan_t ),
.slv_r_chan_t ( slv_r_chan_t ),
.mst_r_chan_t ( mst_r_chan_t ),
.slv_req_t ( slv_req_t ),
.slv_resp_t ( slv_resp_t ),
.mst_req_t ( mst_req_t ),
.mst_resp_t ( mst_resp_t ),
.rule_t ( axi_pkg::xbar_rule_64_t),
.slv_aw_chan_width ( 35+XBarCfg.AxiIdWidthSlvPorts+XBarCfg.AxiAddrWidth+AXI_USER_WIDTH),
.slv_ar_chan_width ( 35+XBarCfg.AxiIdWidthSlvPorts+XBarCfg.AxiAddrWidth+AXI_USER_WIDTH)
) i_xbar (
.clk_i,
.rst_ni,
.test_i (1'b0),
.slv_ports_req_i (slv_reqs ),
.slv_ports_resp_o (slv_resps),
.mst_ports_req_o (mst_reqs ),
.mst_ports_resp_i (mst_resps),
.addr_map_i (routing_rules),
.en_default_mst_port_i('0 ),
.default_mst_port_i ('0 )
);
endmodule |
module axi_to_mem #(
/// AXI4+ATOP request type. See `include/axi/typedef.svh`.
parameter type axi_req_t = logic,
/// AXI4+ATOP response type. See `include/axi/typedef.svh`.
parameter type axi_resp_t = logic,
/// Address width, has to be less or equal than the width off the AXI address field.
/// Determines the width of `mem_addr_o`. Has to be wide enough to emit the memory region
/// which should be accessible.
parameter int unsigned AddrWidth = 0,
/// AXI4+ATOP data width.
parameter int unsigned DataWidth = 0,
/// AXI4+ATOP ID width.
parameter int unsigned IdWidth = 0,
/// Number of banks at output, must evenly divide `DataWidth`.
parameter int unsigned NumBanks = 0,
/// Depth of memory response buffer. This should be equal to the memory response latency.
parameter int unsigned BufDepth = 1,
/// Dependent parameter, do not override. Memory address type.
localparam type addr_t = logic [AddrWidth-1:0],
/// Dependent parameter, do not override. Memory data type.
localparam type mem_data_t = logic [DataWidth/NumBanks-1:0],
/// Dependent parameter, do not override. Memory write strobe type.
localparam type mem_strb_t = logic [DataWidth/NumBanks/8-1:0]
) (
/// Clock input.
input logic clk_i,
/// Asynchronous reset, active low.
input logic rst_ni,
/// The unit is busy handling an AXI4+ATOP request.
output logic busy_o,
/// AXI4+ATOP slave port, request input.
input axi_req_t axi_req_i,
/// AXI4+ATOP slave port, response output.
output axi_resp_t axi_resp_o,
/// Memory stream master, request is valid for this bank.
output logic [NumBanks-1:0] mem_req_o,
/// Memory stream master, request can be granted by this bank.
input logic [NumBanks-1:0] mem_gnt_i,
/// Memory stream master, byte address of the request.
output addr_t [NumBanks-1:0] mem_addr_o,
/// Memory stream master, write data for this bank. Valid when `mem_req_o`.
output mem_data_t [NumBanks-1:0] mem_wdata_o,
/// Memory stream master, byte-wise strobe (byte enable).
output mem_strb_t [NumBanks-1:0] mem_strb_o,
/// Memory stream master, `axi_pkg::atop_t` signal associated with this request.
output axi_pkg::atop_t [NumBanks-1:0] mem_atop_o,
/// Memory stream master, write enable. Then asserted store of `mem_w_data` is requested.
output logic [NumBanks-1:0] mem_we_o,
/// Memory stream master, response is valid. This module expects always a response valid for a
/// request regardless if the request was a write or a read.
input logic [NumBanks-1:0] mem_rvalid_i,
/// Memory stream master, read response data.
input mem_data_t [NumBanks-1:0] mem_rdata_i
);
typedef logic [DataWidth-1:0] axi_data_t;
typedef logic [DataWidth/8-1:0] axi_strb_t;
typedef logic [IdWidth-1:0] axi_id_t;
typedef struct packed {
addr_t addr;
axi_pkg::atop_t atop;
axi_strb_t strb;
axi_data_t wdata;
logic we;
} mem_req_t;
typedef struct packed {
addr_t addr;
axi_pkg::atop_t atop;
axi_id_t id;
logic last;
axi_pkg::qos_t qos;
axi_pkg::size_t size;
logic write;
} meta_t;
axi_data_t mem_rdata,
m2s_resp;
axi_pkg::len_t r_cnt_d, r_cnt_q,
w_cnt_d, w_cnt_q;
logic arb_valid, arb_ready,
rd_valid, rd_ready,
wr_valid, wr_ready,
sel_b, sel_buf_b,
sel_r, sel_buf_r,
sel_valid, sel_ready,
sel_buf_valid, sel_buf_ready,
sel_lock_d, sel_lock_q,
meta_valid, meta_ready,
meta_buf_valid, meta_buf_ready,
meta_sel_d, meta_sel_q,
m2s_req_valid, m2s_req_ready,
m2s_resp_valid, m2s_resp_ready,
mem_req_valid, mem_req_ready,
mem_rvalid;
mem_req_t m2s_req,
mem_req;
meta_t rd_meta,
rd_meta_d, rd_meta_q,
wr_meta,
wr_meta_d, wr_meta_q,
meta, meta_buf;
assign busy_o = axi_req_i.aw_valid | axi_req_i.ar_valid | axi_req_i.w_valid |
axi_resp_o.b_valid | axi_resp_o.r_valid |
(r_cnt_q > 0) | (w_cnt_q > 0);
// Handle reads.
always_comb begin
// Default assignments
axi_resp_o.ar_ready = 1'b0;
rd_meta_d = rd_meta_q;
rd_meta = meta_t'{default: '0};
rd_valid = 1'b0;
r_cnt_d = r_cnt_q;
// Handle R burst in progress.
if (r_cnt_q > '0) begin
rd_meta_d.last = (r_cnt_q == 8'd1);
rd_meta = rd_meta_d;
rd_meta.addr = rd_meta_q.addr + axi_pkg::num_bytes(rd_meta_q.size);
rd_valid = 1'b1;
if (rd_ready) begin
r_cnt_d--;
rd_meta_d.addr = rd_meta.addr;
end
// Handle new AR if there is one.
end else if (axi_req_i.ar_valid) begin
rd_meta_d = '{
addr: addr_t'(axi_pkg::aligned_addr(axi_req_i.ar.addr, axi_req_i.ar.size)),
atop: '0,
id: axi_req_i.ar.id,
last: (axi_req_i.ar.len == '0),
qos: axi_req_i.ar.qos,
size: axi_req_i.ar.size,
write: 1'b0
};
rd_meta = rd_meta_d;
rd_meta.addr = addr_t'(axi_req_i.ar.addr);
rd_valid = 1'b1;
if (rd_ready) begin
r_cnt_d = axi_req_i.ar.len;
axi_resp_o.ar_ready = 1'b1;
end
end
end
// Handle writes.
always_comb begin
// Default assignments
axi_resp_o.aw_ready = 1'b0;
axi_resp_o.w_ready = 1'b0;
wr_meta_d = wr_meta_q;
wr_meta = meta_t'{default: '0};
wr_valid = 1'b0;
w_cnt_d = w_cnt_q;
// Handle W bursts in progress.
if (w_cnt_q > '0) begin
wr_meta_d.last = (w_cnt_q == 8'd1);
wr_meta = wr_meta_d;
wr_meta.addr = wr_meta_q.addr + axi_pkg::num_bytes(wr_meta_q.size);
if (axi_req_i.w_valid) begin
wr_valid = 1'b1;
if (wr_ready) begin
axi_resp_o.w_ready = 1'b1;
w_cnt_d--;
wr_meta_d.addr = wr_meta.addr;
end
end
// Handle new AW if there is one.
end else if (axi_req_i.aw_valid && axi_req_i.w_valid) begin
wr_meta_d = '{
addr: addr_t'(axi_pkg::aligned_addr(axi_req_i.aw.addr, axi_req_i.aw.size)),
atop: axi_req_i.aw.atop,
id: axi_req_i.aw.id,
last: (axi_req_i.aw.len == '0),
qos: axi_req_i.aw.qos,
size: axi_req_i.aw.size,
write: 1'b1
};
wr_meta = wr_meta_d;
wr_meta.addr = addr_t'(axi_req_i.aw.addr);
wr_valid = 1'b1;
if (wr_ready) begin
w_cnt_d = axi_req_i.aw.len;
axi_resp_o.aw_ready = 1'b1;
axi_resp_o.w_ready = 1'b1;
end
end
end
// Arbitrate between reads and writes.
stream_mux #(
.DATA_T ( meta_t ),
.N_INP ( 32'd2 )
) i_ax_mux (
.inp_data_i ({wr_meta, rd_meta }),
.inp_valid_i ({wr_valid, rd_valid}),
.inp_ready_o ({wr_ready, rd_ready}),
.inp_sel_i ( meta_sel_d ),
.oup_data_o ( meta ),
.oup_valid_o ( arb_valid ),
.oup_ready_i ( arb_ready )
);
always_comb begin
meta_sel_d = meta_sel_q;
sel_lock_d = sel_lock_q;
if (sel_lock_q) begin
meta_sel_d = meta_sel_q;
if (arb_valid && arb_ready) begin
sel_lock_d = 1'b0;
end
end else begin
if (wr_valid ^ rd_valid) begin
// If either write or read is valid but not both, select the valid one.
meta_sel_d = wr_valid;
end else if (wr_valid && rd_valid) begin
// If both write and read are valid, decide according to QoS then burst properties.
// Prioritize higher QoS.
if (wr_meta.qos > rd_meta.qos) begin
meta_sel_d = 1'b1;
end else if (rd_meta.qos > wr_meta.qos) begin
meta_sel_d = 1'b0;
// Decide requests with identical QoS.
end else if (wr_meta.qos == rd_meta.qos) begin
// 1. Prioritize individual writes over read bursts.
// Rationale: Read bursts can be interleaved on AXI but write bursts cannot.
if (wr_meta.last && !rd_meta.last) begin
meta_sel_d = 1'b1;
// 2. Prioritize ongoing burst.
// Rationale: Stalled bursts create back-pressure or require costly buffers.
end else if (w_cnt_q > '0) begin
meta_sel_d = 1'b1;
end else if (r_cnt_q > '0) begin
meta_sel_d = 1'b0;
// 3. Otherwise arbitrate round robin to prevent starvation.
end else begin
meta_sel_d = ~meta_sel_q;
end
end
end
// Lock arbitration if valid but not yet ready.
if (arb_valid && !arb_ready) begin
sel_lock_d = 1'b1;
end
end
end
// Fork arbitrated stream to meta data, memory requests, and R/B channel selection.
stream_fork #(
.N_OUP ( 32'd3 )
) i_fork (
.clk_i,
.rst_ni,
.valid_i ( arb_valid ),
.ready_o ( arb_ready ),
.valid_o ({sel_valid, meta_valid, m2s_req_valid}),
.ready_i ({sel_ready, meta_ready, m2s_req_ready})
);
assign sel_b = meta.write & meta.last;
assign sel_r = ~meta.write | meta.atop[5];
stream_fifo #(
.FALL_THROUGH ( 1'b1 ),
.DEPTH ( 32'd1 + BufDepth ),
.T ( logic[1:0] )
) i_sel_buf (
.clk_i,
.rst_ni,
.flush_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.data_i ({sel_b, sel_r }),
.valid_i ( sel_valid ),
.ready_o ( sel_ready ),
.data_o ({sel_buf_b, sel_buf_r}),
.valid_o ( sel_buf_valid ),
.ready_i ( sel_buf_ready ),
.usage_o ( /* unused */ )
);
stream_fifo #(
.FALL_THROUGH ( 1'b1 ),
.DEPTH ( 32'd1 + BufDepth ),
.T ( meta_t )
) i_meta_buf (
.clk_i,
.rst_ni,
.flush_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.data_i ( meta ),
.valid_i ( meta_valid ),
.ready_o ( meta_ready ),
.data_o ( meta_buf ),
.valid_o ( meta_buf_valid ),
.ready_i ( meta_buf_ready ),
.usage_o ( /* unused */ )
);
// Assemble the actual memory request from meta information and write data.
assign m2s_req = mem_req_t'{
addr: meta.addr,
atop: meta.atop,
strb: axi_req_i.w.strb,
wdata: axi_req_i.w.data,
we: meta.write
};
// Interface memory as stream.
stream_to_mem #(
.mem_req_t ( mem_req_t ),
.mem_resp_t ( axi_data_t ),
.BufDepth ( BufDepth )
) i_stream_to_mem (
.clk_i,
.rst_ni,
.req_i ( m2s_req ),
.req_valid_i ( m2s_req_valid ),
.req_ready_o ( m2s_req_ready ),
.resp_o ( m2s_resp ),
.resp_valid_o ( m2s_resp_valid ),
.resp_ready_i ( m2s_resp_ready ),
.mem_req_o ( mem_req ),
.mem_req_valid_o ( mem_req_valid ),
.mem_req_ready_i ( mem_req_ready ),
.mem_resp_i ( mem_rdata ),
.mem_resp_valid_i ( mem_rvalid )
);
// Split single memory request to desired number of banks.
mem_to_banks #(
.AddrWidth ( AddrWidth ),
.DataWidth ( DataWidth ),
.NumBanks ( NumBanks )
) i_mem_to_banks (
.clk_i,
.rst_ni,
.req_i ( mem_req_valid ),
.gnt_o ( mem_req_ready ),
.addr_i ( mem_req.addr ),
.wdata_i ( mem_req.wdata ),
.strb_i ( mem_req.strb ),
.atop_i ( mem_req.atop ),
.we_i ( mem_req.we ),
.rvalid_o ( mem_rvalid ),
.rdata_o ( mem_rdata ),
.bank_req_o ( mem_req_o ),
.bank_gnt_i ( mem_gnt_i ),
.bank_addr_o ( mem_addr_o ),
.bank_wdata_o ( mem_wdata_o ),
.bank_strb_o ( mem_strb_o ),
.bank_atop_o ( mem_atop_o ),
.bank_we_o ( mem_we_o ),
.bank_rvalid_i ( mem_rvalid_i ),
.bank_rdata_i ( mem_rdata_i )
);
// Join memory read data and meta data stream.
logic mem_join_valid, mem_join_ready;
stream_join #(
.N_INP ( 32'd2 )
) i_join (
.inp_valid_i ({m2s_resp_valid, meta_buf_valid}),
.inp_ready_o ({m2s_resp_ready, meta_buf_ready}),
.oup_valid_o ( mem_join_valid ),
.oup_ready_i ( mem_join_ready )
);
// Dynamically fork the joined stream to B and R channels.
stream_fork_dynamic #(
.N_OUP ( 32'd2 )
) i_fork_dynamic (
.clk_i,
.rst_ni,
.valid_i ( mem_join_valid ),
.ready_o ( mem_join_ready ),
.sel_i ({sel_buf_b, sel_buf_r }),
.sel_valid_i ( sel_buf_valid ),
.sel_ready_o ( sel_buf_ready ),
.valid_o ({axi_resp_o.b_valid, axi_resp_o.r_valid}),
.ready_i ({axi_req_i.b_ready, axi_req_i.r_ready })
);
// Compose B responses.
assign axi_resp_o.b = '{
id: meta_buf.id,
resp: axi_pkg::RESP_OKAY,
user: '0
};
// Compose R responses.
assign axi_resp_o.r = '{
data: m2s_resp,
id: meta_buf.id,
last: meta_buf.last,
resp: axi_pkg::RESP_OKAY,
user: '0
};
// Registers
`FFARN(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni)
`FFARN(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni)
`FFARN(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni)
`FFARN(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni)
`FFARN(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni)
`FFARN(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni)
// Assertions
// pragma translate_off
`ifndef VERILATOR
default disable iff (!rst_ni);
assume property (@(posedge clk_i)
axi_req_i.ar_valid && !axi_resp_o.ar_ready |=> $stable(axi_req_i.ar))
else $error("AR must remain stable until handshake has happened!");
assert property (@(posedge clk_i)
axi_resp_o.r_valid && !axi_req_i.r_ready |=> $stable(axi_resp_o.r))
else $error("R must remain stable until handshake has happened!");
assume property (@(posedge clk_i)
axi_req_i.aw_valid && !axi_resp_o.aw_ready |=> $stable(axi_req_i.aw))
else $error("AW must remain stable until handshake has happened!");
assume property (@(posedge clk_i)
axi_req_i.w_valid && !axi_resp_o.w_ready |=> $stable(axi_req_i.w))
else $error("W must remain stable until handshake has happened!");
assert property (@(posedge clk_i)
axi_resp_o.b_valid && !axi_req_i.b_ready |=> $stable(axi_resp_o.b))
else $error("B must remain stable until handshake has happened!");
assert property (@(posedge clk_i) axi_req_i.ar_valid && axi_req_i.ar.len > 0 |->
axi_req_i.ar.burst == axi_pkg::BURST_INCR)
else $error("Non-incrementing bursts are not supported!");
assert property (@(posedge clk_i) axi_req_i.aw_valid && axi_req_i.aw.len > 0 |->
axi_req_i.aw.burst == axi_pkg::BURST_INCR)
else $error("Non-incrementing bursts are not supported!");
assert property (@(posedge clk_i) meta_valid && meta.atop != '0 |-> meta.write)
else $warning("Unexpected atomic operation on read.");
`endif
// pragma translate_on
endmodule |
module axi_to_mem_intf #(
/// See `axi_to_mem`, parameter `AddrWidth`.
parameter int unsigned ADDR_WIDTH = 32'd0,
/// See `axi_to_mem`, parameter `DataWidth`.
parameter int unsigned DATA_WIDTH = 32'd0,
/// AXI4+ATOP ID width.
parameter int unsigned ID_WIDTH = 32'd0,
/// AXI4+ATOP user width.
parameter int unsigned USER_WIDTH = 32'd0,
/// See `axi_to_mem`, parameter `NumBanks`.
parameter int unsigned NUM_BANKS = 32'd0,
/// See `axi_to_mem`, parameter `BufDepth`.
parameter int unsigned BUF_DEPTH = 32'd1,
/// Dependent parameter, do not override. See `axi_to_mem`, parameter `addr_t`.
localparam type addr_t = logic [ADDR_WIDTH-1:0],
/// Dependent parameter, do not override. See `axi_to_mem`, parameter `mem_data_t`.
localparam type mem_data_t = logic [DATA_WIDTH/NUM_BANKS-1:0],
/// Dependent parameter, do not override. See `axi_to_mem`, parameter `mem_strb_t`.
localparam type mem_strb_t = logic [DATA_WIDTH/NUM_BANKS/8-1:0]
) (
/// Clock input.
input logic clk_i,
/// Asynchronous reset, active low.
input logic rst_ni,
/// See `axi_to_mem`, port `busy_o`.
output logic busy_o,
/// AXI4+ATOP slave interface port.
AXI_BUS.Slave slv,
/// See `axi_to_mem`, port `mem_req_o`.
output logic [NUM_BANKS-1:0] mem_req_o,
/// See `axi_to_mem`, port `mem_gnt_i`.
input logic [NUM_BANKS-1:0] mem_gnt_i,
/// See `axi_to_mem`, port `mem_addr_o`.
output addr_t [NUM_BANKS-1:0] mem_addr_o,
/// See `axi_to_mem`, port `mem_wdata_o`.
output mem_data_t [NUM_BANKS-1:0] mem_wdata_o,
/// See `axi_to_mem`, port `mem_strb_o`.
output mem_strb_t [NUM_BANKS-1:0] mem_strb_o,
/// See `axi_to_mem`, port `mem_atop_o`.
output axi_pkg::atop_t [NUM_BANKS-1:0] mem_atop_o,
/// See `axi_to_mem`, port `mem_we_o`.
output logic [NUM_BANKS-1:0] mem_we_o,
/// See `axi_to_mem`, port `mem_rvalid_i`.
input logic [NUM_BANKS-1:0] mem_rvalid_i,
/// See `axi_to_mem`, port `mem_rdata_i`.
input mem_data_t [NUM_BANKS-1:0] mem_rdata_i
);
typedef logic [ID_WIDTH-1:0] id_t;
typedef logic [DATA_WIDTH-1:0] data_t;
typedef logic [DATA_WIDTH/8-1:0] strb_t;
typedef logic [USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t req;
resp_t resp;
`AXI_ASSIGN_TO_REQ(req, slv)
`AXI_ASSIGN_FROM_RESP(slv, resp)
axi_to_mem #(
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.AddrWidth ( ADDR_WIDTH ),
.DataWidth ( DATA_WIDTH ),
.IdWidth ( ID_WIDTH ),
.NumBanks ( NUM_BANKS ),
.BufDepth ( BUF_DEPTH )
) i_axi_to_mem (
.clk_i,
.rst_ni,
.busy_o,
.axi_req_i ( req ),
.axi_resp_o ( resp ),
.mem_req_o,
.mem_gnt_i,
.mem_addr_o,
.mem_wdata_o,
.mem_strb_o,
.mem_atop_o,
.mem_we_o,
.mem_rvalid_i,
.mem_rdata_i
);
endmodule |
module mem_to_banks #(
/// Input address width.
parameter int unsigned AddrWidth = 32'd0,
/// Input data width, must be a power of two.
parameter int unsigned DataWidth = 32'd0,
/// Number of banks at output, must evenly divide `DataWidth`.
parameter int unsigned NumBanks = 32'd0,
/// Dependent parameter, do not override! Address type.
localparam type addr_t = logic [AddrWidth-1:0],
/// Dependent parameter, do not override! Input data type.
localparam type inp_data_t = logic [DataWidth-1:0],
/// Dependent parameter, do not override! Input write strobe type.
localparam type inp_strb_t = logic [DataWidth/8-1:0],
/// Dependent parameter, do not override! Output data type.
localparam type oup_data_t = logic [DataWidth/NumBanks-1:0],
/// Dependent parameter, do not override! Output write strobe type.
localparam type oup_strb_t = logic [DataWidth/NumBanks/8-1:0]
) (
/// Clock input.
input logic clk_i,
/// Asynchronous reset, active low.
input logic rst_ni,
/// Memory request to split, request is valid.
input logic req_i,
/// Memory request to split, request can be granted.
output logic gnt_o,
/// Memory request to split, request address, byte-wise.
input addr_t addr_i,
/// Memory request to split, request write data.
input inp_data_t wdata_i,
/// Memory request to split, request write strobe.
input inp_strb_t strb_i,
/// Memory request to split, request Atomic signal from AXI4+ATOP.
input axi_pkg::atop_t atop_i,
/// Memory request to split, request write enable, active high.
input logic we_i,
/// Memory request to split, response is valid. Required for read and write requests
output logic rvalid_o,
/// Memory request to split, response read data.
output inp_data_t rdata_o,
/// Memory bank request, request is valid.
output logic [NumBanks-1:0] bank_req_o,
/// Memory bank request, request can be granted.
input logic [NumBanks-1:0] bank_gnt_i,
/// Memory bank request, request address, byte-wise. Will be different for each bank.
output addr_t [NumBanks-1:0] bank_addr_o,
/// Memory bank request, request write data.
output oup_data_t [NumBanks-1:0] bank_wdata_o,
/// Memory bank request, request write strobe.
output oup_strb_t [NumBanks-1:0] bank_strb_o,
/// Memory bank request, request Atomic signal from AXI4+ATOP.
output axi_pkg::atop_t [NumBanks-1:0] bank_atop_o,
/// Memory bank request, request write enable, active high.
output logic [NumBanks-1:0] bank_we_o,
/// Memory bank request, response is valid. Required for read and write requests
input logic [NumBanks-1:0] bank_rvalid_i,
/// Memory bank request, response read data.
input oup_data_t [NumBanks-1:0] bank_rdata_i
);
localparam DataBytes = $bits(inp_strb_t);
localparam BitsPerBank = $bits(oup_data_t);
localparam BytesPerBank = $bits(oup_strb_t);
typedef struct packed {
addr_t addr;
oup_data_t wdata;
oup_strb_t strb;
axi_pkg::atop_t atop;
logic we;
} req_t;
logic req_valid;
logic [NumBanks-1:0] req_ready,
resp_valid, resp_ready;
req_t [NumBanks-1:0] bank_req,
bank_oup;
function automatic addr_t align_addr(input addr_t addr);
return (addr >> $clog2(DataBytes)) << $clog2(DataBytes);
endfunction
// Handle requests.
assign req_valid = req_i & gnt_o;
for (genvar i = 0; unsigned'(i) < NumBanks; i++) begin : gen_reqs
assign bank_req[i].addr = align_addr(addr_i) + i * BytesPerBank;
assign bank_req[i].wdata = wdata_i[i*BitsPerBank+:BitsPerBank];
assign bank_req[i].strb = strb_i[i*BytesPerBank+:BytesPerBank];
assign bank_req[i].atop = atop_i;
assign bank_req[i].we = we_i;
fall_through_register #(
.T ( req_t )
) i_ft_reg (
.clk_i,
.rst_ni,
.clr_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.valid_i ( req_valid ),
.ready_o ( req_ready[i] ),
.data_i ( bank_req[i] ),
.valid_o ( bank_req_o[i] ),
.ready_i ( bank_gnt_i[i] ),
.data_o ( bank_oup[i] )
);
assign bank_addr_o[i] = bank_oup[i].addr;
assign bank_wdata_o[i] = bank_oup[i].wdata;
assign bank_strb_o[i] = bank_oup[i].strb;
assign bank_atop_o[i] = bank_oup[i].atop;
assign bank_we_o[i] = bank_oup[i].we;
end
// Grant output if all our requests have been granted.
assign gnt_o = (&req_ready) & (&resp_ready);
// Handle responses.
for (genvar i = 0; unsigned'(i) < NumBanks; i++) begin : gen_resp_regs
fall_through_register #(
.T ( oup_data_t )
) i_ft_reg (
.clk_i,
.rst_ni,
.clr_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.valid_i ( bank_rvalid_i[i] ),
.ready_o ( resp_ready[i] ),
.data_i ( bank_rdata_i[i] ),
.data_o ( rdata_o[i*BitsPerBank+:BitsPerBank] ),
.ready_i ( rvalid_o ),
.valid_o ( resp_valid[i] )
);
end
assign rvalid_o = &resp_valid;
// Assertions
// pragma translate_off
`ifndef VERILATOR
initial begin
assume (DataWidth != 0 && (DataWidth & (DataWidth - 1)) == 0)
else $fatal(1, "Data width must be a power of two!");
assume (DataWidth % NumBanks == 0)
else $fatal(1, "Data width must be evenly divisible over banks!");
assume ((DataWidth / NumBanks) % 8 == 0)
else $fatal(1, "Data width of each bank must be divisible into 8-bit bytes!");
end
`endif
// pragma translate_on
endmodule |
module fpnew_noncomp #(
parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0),
parameter int unsigned NumPipeRegs = 0,
parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE,
parameter type TagType = logic,
parameter type AuxType = logic,
localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat) // do not change
) (
input logic clk_i,
input logic rst_ni,
// Input signals
input logic [1:0][WIDTH-1:0] operands_i, // 2 operands
input logic [1:0] is_boxed_i, // 2 operands
input fpnew_pkg::roundmode_e rnd_mode_i,
input fpnew_pkg::operation_e op_i,
input logic op_mod_i,
input TagType tag_i,
input logic mask_i,
input AuxType aux_i,
// Input Handshake
input logic in_valid_i,
output logic in_ready_o,
input logic flush_i,
// Output signals
output logic [WIDTH-1:0] result_o,
output fpnew_pkg::status_t status_o,
output logic extension_bit_o,
output fpnew_pkg::classmask_e class_mask_o,
output logic is_class_o,
output TagType tag_o,
output logic mask_o,
output AuxType aux_o,
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// Indication of valid data in flight
output logic busy_o
);
// ----------
// Constants
// ----------
localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat);
localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat);
// Pipelines
localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE || PipeConfig == fpnew_pkg::INSIDE)
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? ((NumPipeRegs + 1) / 2) // First to get distributed regs
: 0); // no regs here otherwise
localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? (NumPipeRegs / 2) // Last to get distributed regs
: 0); // no regs here otherwise
// ----------------
// Type definition
// ----------------
typedef struct packed {
logic sign;
logic [EXP_BITS-1:0] exponent;
logic [MAN_BITS-1:0] mantissa;
} fp_t;
// ---------------
// Input pipeline
// ---------------
// Input pipeline signals, index i holds signal after i register stages
logic [0:NUM_INP_REGS][1:0][WIDTH-1:0] inp_pipe_operands_q;
logic [0:NUM_INP_REGS][1:0] inp_pipe_is_boxed_q;
fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q;
fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q;
logic [0:NUM_INP_REGS] inp_pipe_op_mod_q;
TagType [0:NUM_INP_REGS] inp_pipe_tag_q;
logic [0:NUM_INP_REGS] inp_pipe_mask_q;
AuxType [0:NUM_INP_REGS] inp_pipe_aux_q;
logic [0:NUM_INP_REGS] inp_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_INP_REGS] inp_pipe_ready;
// Input stage: First element of pipeline is taken from inputs
assign inp_pipe_operands_q[0] = operands_i;
assign inp_pipe_is_boxed_q[0] = is_boxed_i;
assign inp_pipe_rnd_mode_q[0] = rnd_mode_i;
assign inp_pipe_op_q[0] = op_i;
assign inp_pipe_op_mod_q[0] = op_mod_i;
assign inp_pipe_tag_q[0] = tag_i;
assign inp_pipe_mask_q[0] = mask_i;
assign inp_pipe_aux_q[0] = aux_i;
assign inp_pipe_valid_q[0] = in_valid_i;
// Input stage: Propagate pipeline ready signal to updtream circuitry
assign in_ready_o = inp_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0)
`FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0)
`FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
`FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD)
`FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0)
`FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0)
`FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// ---------------------
// Input classification
// ---------------------
fpnew_pkg::fp_info_t [1:0] info_q;
// Classify input
fpnew_classifier #(
.FpFormat ( FpFormat ),
.NumOperands ( 2 )
) i_class_a (
.operands_i ( inp_pipe_operands_q[NUM_INP_REGS] ),
.is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS] ),
.info_o ( info_q )
);
fp_t operand_a, operand_b;
fpnew_pkg::fp_info_t info_a, info_b;
// Packing-order-agnostic assignments
assign operand_a = inp_pipe_operands_q[NUM_INP_REGS][0];
assign operand_b = inp_pipe_operands_q[NUM_INP_REGS][1];
assign info_a = info_q[0];
assign info_b = info_q[1];
logic any_operand_inf;
logic any_operand_nan;
logic signalling_nan;
// Reduction for special case handling
assign any_operand_inf = (| {info_a.is_inf, info_b.is_inf});
assign any_operand_nan = (| {info_a.is_nan, info_b.is_nan});
assign signalling_nan = (| {info_a.is_signalling, info_b.is_signalling});
logic operands_equal, operand_a_smaller;
// Equality checks for zeroes too
assign operands_equal = (operand_a == operand_b) || (info_a.is_zero && info_b.is_zero);
// Invert result if non-zero signs involved (unsigned comparison)
assign operand_a_smaller = (operand_a < operand_b) ^ (operand_a.sign || operand_b.sign);
// ---------------
// Sign Injection
// ---------------
fp_t sgnj_result;
fpnew_pkg::status_t sgnj_status;
logic sgnj_extension_bit;
// Sign Injection - operation is encoded in rnd_mode_q:
// RNE = SGNJ, RTZ = SGNJN, RDN = SGNJX, RUP = Passthrough (no NaN-box check)
always_comb begin : sign_injections
logic sign_a, sign_b; // internal signs
// Default assignment
sgnj_result = operand_a; // result based on operand a
// NaN-boxing check will treat invalid inputs as canonical NaNs
if (!info_a.is_boxed) sgnj_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)};
// Internal signs are treated as positive in case of non-NaN-boxed values
sign_a = operand_a.sign & info_a.is_boxed;
sign_b = operand_b.sign & info_b.is_boxed;
// Do the sign injection based on rm field
unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS])
fpnew_pkg::RNE: sgnj_result.sign = sign_b; // SGNJ
fpnew_pkg::RTZ: sgnj_result.sign = ~sign_b; // SGNJN
fpnew_pkg::RDN: sgnj_result.sign = sign_a ^ sign_b; // SGNJX
fpnew_pkg::RUP: sgnj_result = operand_a; // passthrough
default: sgnj_result = '{default: fpnew_pkg::DONT_CARE}; // don't care
endcase
end
assign sgnj_status = '0; // sign injections never raise exceptions
// op_mod_q enables integer sign-extension of result (for storing to integer regfile)
assign sgnj_extension_bit = inp_pipe_op_mod_q[NUM_INP_REGS] ? sgnj_result.sign : 1'b1;
// ------------------
// Minimum / Maximum
// ------------------
fp_t minmax_result;
fpnew_pkg::status_t minmax_status;
logic minmax_extension_bit;
// Minimum/Maximum - operation is encoded in rnd_mode_q:
// RNE = MIN, RTZ = MAX
always_comb begin : min_max
// Default assignment
minmax_status = '0;
// Min/Max use quiet comparisons - only sNaN are invalid
minmax_status.NV = signalling_nan;
// Both NaN inputs cause a NaN output
if (info_a.is_nan && info_b.is_nan)
minmax_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)}; // canonical qNaN
// If one operand is NaN, the non-NaN operand is returned
else if (info_a.is_nan) minmax_result = operand_b;
else if (info_b.is_nan) minmax_result = operand_a;
// Otherwise decide according to the operation
else begin
unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS])
fpnew_pkg::RNE: minmax_result = operand_a_smaller ? operand_a : operand_b; // MIN
fpnew_pkg::RTZ: minmax_result = operand_a_smaller ? operand_b : operand_a; // MAX
default: minmax_result = '{default: fpnew_pkg::DONT_CARE}; // don't care
endcase
end
end
assign minmax_extension_bit = 1'b1; // NaN-box as result is always a float value
// ------------
// Comparisons
// ------------
fp_t cmp_result;
fpnew_pkg::status_t cmp_status;
logic cmp_extension_bit;
// Comparisons - operation is encoded in rnd_mode_q:
// RNE = LE, RTZ = LT, RDN = EQ
// op_mod_q inverts boolean outputs
always_comb begin : comparisons
// Default assignment
cmp_result = '0; // false
cmp_status = '0; // no flags
// Signalling NaNs always compare as false and are illegal
if (signalling_nan) cmp_status.NV = 1'b1; // invalid operation
// Otherwise do comparisons
else begin
unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS])
fpnew_pkg::RNE: begin // Less than or equal
if (any_operand_nan) cmp_status.NV = 1'b1; // Signalling comparison: NaNs are invalid
else cmp_result = (operand_a_smaller | operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS];
end
fpnew_pkg::RTZ: begin // Less than
if (any_operand_nan) cmp_status.NV = 1'b1; // Signalling comparison: NaNs are invalid
else cmp_result = (operand_a_smaller & ~operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS];
end
fpnew_pkg::RDN: begin // Equal
if (any_operand_nan) cmp_result = inp_pipe_op_mod_q[NUM_INP_REGS]; // NaN always not equal
else cmp_result = operands_equal ^ inp_pipe_op_mod_q[NUM_INP_REGS];
end
default: cmp_result = '{default: fpnew_pkg::DONT_CARE}; // don't care
endcase
end
end
assign cmp_extension_bit = 1'b0; // Comparisons always produce booleans in integer registers
// ---------------
// Classification
// ---------------
fpnew_pkg::status_t class_status;
logic class_extension_bit;
fpnew_pkg::classmask_e class_mask_d; // the result is actually here
// Classification - always return the classification mask on the dedicated port
always_comb begin : classify
if (info_a.is_normal) begin
class_mask_d = operand_a.sign ? fpnew_pkg::NEGNORM : fpnew_pkg::POSNORM;
end else if (info_a.is_subnormal) begin
class_mask_d = operand_a.sign ? fpnew_pkg::NEGSUBNORM : fpnew_pkg::POSSUBNORM;
end else if (info_a.is_zero) begin
class_mask_d = operand_a.sign ? fpnew_pkg::NEGZERO : fpnew_pkg::POSZERO;
end else if (info_a.is_inf) begin
class_mask_d = operand_a.sign ? fpnew_pkg::NEGINF : fpnew_pkg::POSINF;
end else if (info_a.is_nan) begin
class_mask_d = info_a.is_signalling ? fpnew_pkg::SNAN : fpnew_pkg::QNAN;
end else begin
class_mask_d = fpnew_pkg::QNAN; // default value
end
end
assign class_status = '0; // classification does not set flags
assign class_extension_bit = 1'b0; // classification always produces results in integer registers
// -----------------
// Result selection
// -----------------
fp_t result_d;
fpnew_pkg::status_t status_d;
logic extension_bit_d;
logic is_class_d;
// Select result
always_comb begin : select_result
unique case (inp_pipe_op_q[NUM_INP_REGS])
fpnew_pkg::SGNJ: begin
result_d = sgnj_result;
status_d = sgnj_status;
extension_bit_d = sgnj_extension_bit;
end
fpnew_pkg::MINMAX: begin
result_d = minmax_result;
status_d = minmax_status;
extension_bit_d = minmax_extension_bit;
end
fpnew_pkg::CMP: begin
result_d = cmp_result;
status_d = cmp_status;
extension_bit_d = cmp_extension_bit;
end
fpnew_pkg::CLASSIFY: begin
result_d = '{default: fpnew_pkg::DONT_CARE}; // unused
status_d = class_status;
extension_bit_d = class_extension_bit;
end
default: begin
result_d = '{default: fpnew_pkg::DONT_CARE}; // dont care
status_d = '{default: fpnew_pkg::DONT_CARE}; // dont care
extension_bit_d = fpnew_pkg::DONT_CARE; // dont care
end
endcase
end
assign is_class_d = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::CLASSIFY);
// ----------------
// Output Pipeline
// ----------------
// Output pipeline signals, index i holds signal after i register stages
fp_t [0:NUM_OUT_REGS] out_pipe_result_q;
fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q;
logic [0:NUM_OUT_REGS] out_pipe_extension_bit_q;
fpnew_pkg::classmask_e [0:NUM_OUT_REGS] out_pipe_class_mask_q;
logic [0:NUM_OUT_REGS] out_pipe_is_class_q;
TagType [0:NUM_OUT_REGS] out_pipe_tag_q;
logic [0:NUM_OUT_REGS] out_pipe_mask_q;
AuxType [0:NUM_OUT_REGS] out_pipe_aux_q;
logic [0:NUM_OUT_REGS] out_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_OUT_REGS] out_pipe_ready;
// Input stage: First element of pipeline is taken from inputs
assign out_pipe_result_q[0] = result_d;
assign out_pipe_status_q[0] = status_d;
assign out_pipe_extension_bit_q[0] = extension_bit_d;
assign out_pipe_class_mask_q[0] = class_mask_d;
assign out_pipe_is_class_q[0] = is_class_d;
assign out_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS];
assign out_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS];
assign out_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS];
assign out_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS];
// Input stage: Propagate pipeline ready signal to inside pipe
assign inp_pipe_ready[NUM_INP_REGS] = out_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0)
`FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0)
`FFL(out_pipe_extension_bit_q[i+1], out_pipe_extension_bit_q[i], reg_ena, '0)
`FFL(out_pipe_class_mask_q[i+1], out_pipe_class_mask_q[i], reg_ena, fpnew_pkg::QNAN)
`FFL(out_pipe_is_class_q[i+1], out_pipe_is_class_q[i], reg_ena, '0)
`FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0)
`FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// Output stage: Ready travels backwards from output side, driven by downstream circuitry
assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i;
// Output stage: assign module outputs
assign result_o = out_pipe_result_q[NUM_OUT_REGS];
assign status_o = out_pipe_status_q[NUM_OUT_REGS];
assign extension_bit_o = out_pipe_extension_bit_q[NUM_OUT_REGS];
assign class_mask_o = out_pipe_class_mask_q[NUM_OUT_REGS];
assign is_class_o = out_pipe_is_class_q[NUM_OUT_REGS];
assign tag_o = out_pipe_tag_q[NUM_OUT_REGS];
assign mask_o = out_pipe_mask_q[NUM_OUT_REGS];
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, out_pipe_valid_q});
endmodule |
module fpnew_opgroup_multifmt_slice #(
parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::CONV,
parameter int unsigned Width = 64,
// FPU configuration
parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1,
parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = '1,
parameter logic EnableVectors = 1'b1,
parameter int unsigned NumPipeRegs = 0,
parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE,
parameter type TagType = logic,
// Do not change
localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup),
localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS,
localparam int unsigned NUM_SIMD_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, EnableVectors),
localparam type MaskType = logic [NUM_SIMD_LANES-1:0]
) (
input logic clk_i,
input logic rst_ni,
// Input signals
input logic [NUM_OPERANDS-1:0][Width-1:0] operands_i,
input logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed_i,
input fpnew_pkg::roundmode_e rnd_mode_i,
input fpnew_pkg::operation_e op_i,
input logic op_mod_i,
input fpnew_pkg::fp_format_e src_fmt_i,
input fpnew_pkg::fp_format_e dst_fmt_i,
input fpnew_pkg::int_format_e int_fmt_i,
input logic vectorial_op_i,
input TagType tag_i,
input MaskType simd_mask_i,
// Input Handshake
input logic in_valid_i,
output logic in_ready_o,
input logic flush_i,
// Output signals
output logic [Width-1:0] result_o,
output fpnew_pkg::status_t status_o,
output logic extension_bit_o,
output TagType tag_o,
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// Indication of valid data in flight
output logic busy_o
);
localparam int unsigned MAX_FP_WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig);
localparam int unsigned MAX_INT_WIDTH = fpnew_pkg::max_int_width(IntFmtConfig);
localparam int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, 1'b1);
localparam int unsigned NUM_INT_FORMATS = fpnew_pkg::NUM_INT_FORMATS;
// We will send the format information along with the data
localparam int unsigned FMT_BITS =
fpnew_pkg::maximum($clog2(NUM_FORMATS), $clog2(NUM_INT_FORMATS));
localparam int unsigned AUX_BITS = FMT_BITS + 2; // also add vectorial and integer flags
logic [NUM_LANES-1:0] lane_in_ready, lane_out_valid, divsqrt_done, divsqrt_ready; // Handshake signals for the lanes
logic vectorial_op;
logic [FMT_BITS-1:0] dst_fmt; // destination format to pass along with operation
logic [AUX_BITS-1:0] aux_data;
// additional flags for CONV
logic dst_fmt_is_int, dst_is_cpk;
logic [1:0] dst_vec_op; // info for vectorial results (for packing)
logic [2:0] target_aux_d, target_aux_q;
logic is_up_cast, is_down_cast;
logic [NUM_FORMATS-1:0][Width-1:0] fmt_slice_result;
logic [NUM_INT_FORMATS-1:0][Width-1:0] ifmt_slice_result;
logic [Width-1:0] conv_slice_result;
logic [Width-1:0] conv_target_d, conv_target_q; // vectorial conversions update a register
fpnew_pkg::status_t [NUM_LANES-1:0] lane_status;
logic [NUM_LANES-1:0] lane_ext_bit; // only the first one is actually used
TagType [NUM_LANES-1:0] lane_tags; // only the first one is actually used
logic [NUM_LANES-1:0] lane_masks;
logic [NUM_LANES-1:0][AUX_BITS-1:0] lane_aux; // only the first one is actually used
logic [NUM_LANES-1:0] lane_busy; // dito
logic result_is_vector;
logic [FMT_BITS-1:0] result_fmt;
logic result_fmt_is_int, result_is_cpk;
logic [1:0] result_vec_op; // info for vectorial results (for packing)
logic simd_synch_rdy, simd_synch_done;
// -----------
// Input Side
// -----------
assign in_ready_o = lane_in_ready[0]; // Upstream ready is given by first lane
assign vectorial_op = vectorial_op_i & EnableVectors; // only do vectorial stuff if enabled
// Cast-and-Pack ops are encoded in operation and modifier
assign dst_fmt_is_int = (OpGroup == fpnew_pkg::CONV) & (op_i == fpnew_pkg::F2I);
assign dst_is_cpk = (OpGroup == fpnew_pkg::CONV) & (op_i == fpnew_pkg::CPKAB ||
op_i == fpnew_pkg::CPKCD);
assign dst_vec_op = (OpGroup == fpnew_pkg::CONV) & {(op_i == fpnew_pkg::CPKCD), op_mod_i};
assign is_up_cast = (fpnew_pkg::fp_width(dst_fmt_i) > fpnew_pkg::fp_width(src_fmt_i));
assign is_down_cast = (fpnew_pkg::fp_width(dst_fmt_i) < fpnew_pkg::fp_width(src_fmt_i));
// The destination format is the int format for F2I casts
assign dst_fmt = dst_fmt_is_int ? int_fmt_i : dst_fmt_i;
// The data sent along consists of the vectorial flag and format bits
assign aux_data = {dst_fmt_is_int, vectorial_op, dst_fmt};
assign target_aux_d = {dst_vec_op, dst_is_cpk};
// CONV passes one operand for assembly after the unit: opC for cpk, opB for others
if (OpGroup == fpnew_pkg::CONV) begin : conv_target
assign conv_target_d = dst_is_cpk ? operands_i[2] : operands_i[1];
end
// For 2-operand units, prepare boxing info
logic [NUM_FORMATS-1:0] is_boxed_1op;
logic [NUM_FORMATS-1:0][1:0] is_boxed_2op;
always_comb begin : boxed_2op
for (int fmt = 0; fmt < NUM_FORMATS; fmt++) begin
is_boxed_1op[fmt] = is_boxed_i[fmt][0];
is_boxed_2op[fmt] = is_boxed_i[fmt][1:0];
end
end
// ---------------
// Generate Lanes
// ---------------
for (genvar lane = 0; lane < int'(NUM_LANES); lane++) begin : gen_num_lanes
localparam int unsigned LANE = unsigned'(lane); // unsigned to please the linter
// Get a mask of active formats for this lane
localparam fpnew_pkg::fmt_logic_t ACTIVE_FORMATS =
fpnew_pkg::get_lane_formats(Width, FpFmtConfig, LANE);
localparam fpnew_pkg::ifmt_logic_t ACTIVE_INT_FORMATS =
fpnew_pkg::get_lane_int_formats(Width, FpFmtConfig, IntFmtConfig, LANE);
localparam int unsigned MAX_WIDTH = fpnew_pkg::max_fp_width(ACTIVE_FORMATS);
// Cast-specific parameters
localparam fpnew_pkg::fmt_logic_t CONV_FORMATS =
fpnew_pkg::get_conv_lane_formats(Width, FpFmtConfig, LANE);
localparam fpnew_pkg::ifmt_logic_t CONV_INT_FORMATS =
fpnew_pkg::get_conv_lane_int_formats(Width, FpFmtConfig, IntFmtConfig, LANE);
localparam int unsigned CONV_WIDTH = fpnew_pkg::max_fp_width(CONV_FORMATS);
// Lane parameters from Opgroup
localparam fpnew_pkg::fmt_logic_t LANE_FORMATS = (OpGroup == fpnew_pkg::CONV)
? CONV_FORMATS : ACTIVE_FORMATS;
localparam int unsigned LANE_WIDTH = (OpGroup == fpnew_pkg::CONV) ? CONV_WIDTH : MAX_WIDTH;
logic [LANE_WIDTH-1:0] local_result; // lane-local results
// Generate instances only if needed, lane 0 always generated
if ((lane == 0) || EnableVectors) begin : active_lane
logic in_valid, out_valid, out_ready; // lane-local handshake
logic [NUM_OPERANDS-1:0][LANE_WIDTH-1:0] local_operands; // lane-local oprands
logic [LANE_WIDTH-1:0] op_result; // lane-local results
fpnew_pkg::status_t op_status;
assign in_valid = in_valid_i & ((lane == 0) | vectorial_op); // upper lanes only for vectors
// Slice out the operands for this lane, upper bits are ignored in the unit
always_comb begin : prepare_input
for (int unsigned i = 0; i < NUM_OPERANDS; i++) begin
local_operands[i] = operands_i[i] >> LANE*fpnew_pkg::fp_width(src_fmt_i);
end
// override operand 0 for some conversions
if (OpGroup == fpnew_pkg::CONV) begin
// Source is an integer
if (op_i == fpnew_pkg::I2F) begin
local_operands[0] = operands_i[0] >> LANE*fpnew_pkg::int_width(int_fmt_i);
// vectorial F2F up casts
end else if (op_i == fpnew_pkg::F2F) begin
if (vectorial_op && op_mod_i && is_up_cast) begin // up cast with upper half
local_operands[0] = operands_i[0] >> LANE*fpnew_pkg::fp_width(src_fmt_i) +
MAX_FP_WIDTH/2;
end
// CPK
end else if (dst_is_cpk) begin
if (lane == 1) begin
local_operands[0] = operands_i[1][LANE_WIDTH-1:0]; // using opB as second argument
end
end
end
end
// Instantiate the operation from the selected opgroup
if (OpGroup == fpnew_pkg::ADDMUL) begin : lane_instance
fpnew_fma_multi #(
.FpFmtConfig ( LANE_FORMATS ),
.NumPipeRegs ( NumPipeRegs ),
.PipeConfig ( PipeConfig ),
.TagType ( TagType ),
.AuxType ( logic [AUX_BITS-1:0] )
) i_fpnew_fma_multi (
.clk_i,
.rst_ni,
.operands_i ( local_operands ),
.is_boxed_i,
.rnd_mode_i,
.op_i,
.op_mod_i,
.src_fmt_i,
.dst_fmt_i,
.tag_i,
.mask_i ( simd_mask_i[lane] ),
.aux_i ( aux_data ),
.in_valid_i ( in_valid ),
.in_ready_o ( lane_in_ready[lane] ),
.flush_i,
.result_o ( op_result ),
.status_o ( op_status ),
.extension_bit_o ( lane_ext_bit[lane] ),
.tag_o ( lane_tags[lane] ),
.mask_o ( lane_masks[lane] ),
.aux_o ( lane_aux[lane] ),
.out_valid_o ( out_valid ),
.out_ready_i ( out_ready ),
.busy_o ( lane_busy[lane] )
);
end else if (OpGroup == fpnew_pkg::DIVSQRT) begin : lane_instance
fpnew_divsqrt_multi #(
.FpFmtConfig ( LANE_FORMATS ),
.NumPipeRegs ( NumPipeRegs ),
.PipeConfig ( PipeConfig ),
.TagType ( TagType ),
.AuxType ( logic [AUX_BITS-1:0] )
) i_fpnew_divsqrt_multi (
.clk_i,
.rst_ni,
.operands_i ( local_operands[1:0] ), // 2 operands
.is_boxed_i ( is_boxed_2op ), // 2 operands
.rnd_mode_i,
.op_i,
.dst_fmt_i,
.tag_i,
.mask_i ( simd_mask_i[lane] ),
.aux_i ( aux_data ),
.in_valid_i ( in_valid ),
.in_ready_o ( lane_in_ready[lane] ),
.divsqrt_done_o ( divsqrt_done[lane] ),
.simd_synch_done_i( simd_synch_done ),
.divsqrt_ready_o ( divsqrt_ready[lane]),
.simd_synch_rdy_i( simd_synch_rdy ),
.flush_i,
.result_o ( op_result ),
.status_o ( op_status ),
.extension_bit_o ( lane_ext_bit[lane] ),
.tag_o ( lane_tags[lane] ),
.mask_o ( lane_masks[lane] ),
.aux_o ( lane_aux[lane] ),
.out_valid_o ( out_valid ),
.out_ready_i ( out_ready ),
.busy_o ( lane_busy[lane] )
);
end else if (OpGroup == fpnew_pkg::NONCOMP) begin : lane_instance
end else if (OpGroup == fpnew_pkg::CONV) begin : lane_instance
fpnew_cast_multi #(
.FpFmtConfig ( LANE_FORMATS ),
.IntFmtConfig ( CONV_INT_FORMATS ),
.NumPipeRegs ( NumPipeRegs ),
.PipeConfig ( PipeConfig ),
.TagType ( TagType ),
.AuxType ( logic [AUX_BITS-1:0] )
) i_fpnew_cast_multi (
.clk_i,
.rst_ni,
.operands_i ( local_operands[0] ),
.is_boxed_i ( is_boxed_1op ),
.rnd_mode_i,
.op_i,
.op_mod_i,
.src_fmt_i,
.dst_fmt_i,
.int_fmt_i,
.tag_i,
.mask_i ( simd_mask_i[lane] ),
.aux_i ( aux_data ),
.in_valid_i ( in_valid ),
.in_ready_o ( lane_in_ready[lane] ),
.flush_i,
.result_o ( op_result ),
.status_o ( op_status ),
.extension_bit_o ( lane_ext_bit[lane] ),
.tag_o ( lane_tags[lane] ),
.mask_o ( lane_masks[lane] ),
.aux_o ( lane_aux[lane] ),
.out_valid_o ( out_valid ),
.out_ready_i ( out_ready ),
.busy_o ( lane_busy[lane] )
);
end // ADD OTHER OPTIONS HERE
// Handshakes are only done if the lane is actually used
assign out_ready = out_ready_i & ((lane == 0) | result_is_vector);
assign lane_out_valid[lane] = out_valid & ((lane == 0) | result_is_vector);
// Properly NaN-box or sign-extend the slice result if not in use
assign local_result = lane_out_valid[lane] ? op_result : '{default: lane_ext_bit[0]};
assign lane_status[lane] = lane_out_valid[lane] ? op_status : '0;
// Otherwise generate constant sign-extension
end else begin : inactive_lane
assign lane_out_valid[lane] = 1'b0; // unused lane
assign lane_in_ready[lane] = 1'b0; // unused lane
assign local_result = '{default: lane_ext_bit[0]}; // sign-extend/nan box
assign lane_status[lane] = '0;
assign lane_busy[lane] = 1'b0;
end
// Generate result packing depending on float format
for (genvar fmt = 0; fmt < NUM_FORMATS; fmt++) begin : pack_fp_result
// Set up some constants
localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt));
// only for active formats within the lane
if (ACTIVE_FORMATS[fmt])
assign fmt_slice_result[fmt][(LANE+1)*FP_WIDTH-1:LANE*FP_WIDTH] =
local_result[FP_WIDTH-1:0];
end
// Generate result packing depending on integer format
if (OpGroup == fpnew_pkg::CONV) begin : int_results_enabled
for (genvar ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) begin : pack_int_result
// Set up some constants
localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt));
if (ACTIVE_INT_FORMATS[ifmt])
assign ifmt_slice_result[ifmt][(LANE+1)*INT_WIDTH-1:LANE*INT_WIDTH] =
local_result[INT_WIDTH-1:0];
end
end
end
// Extend slice result if needed
for (genvar fmt = 0; fmt < NUM_FORMATS; fmt++) begin : extend_fp_result
// Set up some constants
localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt));
if (NUM_LANES*FP_WIDTH < Width)
assign fmt_slice_result[fmt][Width-1:NUM_LANES*FP_WIDTH] = '{default: lane_ext_bit[0]};
end
// Mute int results if unused
for (genvar ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) begin : int_results_disabled
if (OpGroup != fpnew_pkg::CONV) begin : mute_int_result
assign ifmt_slice_result[ifmt] = '0;
end
end
// Bypass lanes with target operand for vectorial casts
if (OpGroup == fpnew_pkg::CONV) begin : target_regs
// Bypass pipeline signals, index i holds signal after i register stages
logic [0:NumPipeRegs][Width-1:0] byp_pipe_target_q;
logic [0:NumPipeRegs][2:0] byp_pipe_aux_q;
logic [0:NumPipeRegs] byp_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NumPipeRegs] byp_pipe_ready;
// Input stage: First element of pipeline is taken from inputs
assign byp_pipe_target_q[0] = conv_target_d;
assign byp_pipe_aux_q[0] = target_aux_d;
assign byp_pipe_valid_q[0] = in_valid_i & vectorial_op;
// Generate the register stages
for (genvar i = 0; i < NumPipeRegs; i++) begin : gen_bypass_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign byp_pipe_ready[i] = byp_pipe_ready[i+1] | ~byp_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(byp_pipe_valid_q[i+1], byp_pipe_valid_q[i], byp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = byp_pipe_ready[i] & byp_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(byp_pipe_target_q[i+1], byp_pipe_target_q[i], reg_ena, '0)
`FFL(byp_pipe_aux_q[i+1], byp_pipe_aux_q[i], reg_ena, '0)
end
// Output stage: Ready travels backwards from output side, driven by downstream circuitry
assign byp_pipe_ready[NumPipeRegs] = out_ready_i & result_is_vector;
// Output stage: assign module outputs
assign conv_target_q = byp_pipe_target_q[NumPipeRegs];
// decode the aux data
assign {result_vec_op, result_is_cpk} = byp_pipe_aux_q[NumPipeRegs];
end else begin : no_conv
assign {result_vec_op, result_is_cpk} = '0;
end
// Synch lanes if there is more than one
assign simd_synch_rdy = EnableVectors ? &divsqrt_ready : divsqrt_ready[0];
assign simd_synch_done = EnableVectors ? &divsqrt_done : divsqrt_done[0];
// ------------
// Output Side
// ------------
assign {result_fmt_is_int, result_is_vector, result_fmt} = lane_aux[0];
assign result_o = result_fmt_is_int
? ifmt_slice_result[result_fmt]
: fmt_slice_result[result_fmt];
assign extension_bit_o = lane_ext_bit[0]; // don't care about upper ones
assign tag_o = lane_tags[0]; // don't care about upper ones
assign busy_o = (| lane_busy);
assign out_valid_o = lane_out_valid[0]; // don't care about upper ones
// Collapse the status
always_comb begin : output_processing
// Collapse the status
automatic fpnew_pkg::status_t temp_status;
temp_status = '0;
for (int i = 0; i < int'(NUM_LANES); i++)
temp_status |= lane_status[i] & {5{lane_masks[i]}};
status_o = temp_status;
end
endmodule |
module fpnew_cast_multi #(
parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1,
parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = '1,
// FPU configuration
parameter int unsigned NumPipeRegs = 0,
parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE,
parameter type TagType = logic,
parameter type AuxType = logic,
// Do not change
localparam int unsigned WIDTH = fpnew_pkg::maximum(fpnew_pkg::max_fp_width(FpFmtConfig),
fpnew_pkg::max_int_width(IntFmtConfig)),
localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS
) (
input logic clk_i,
input logic rst_ni,
// Input signals
input logic [WIDTH-1:0] operands_i, // 1 operand
input logic [NUM_FORMATS-1:0] is_boxed_i, // 1 operand
input fpnew_pkg::roundmode_e rnd_mode_i,
input fpnew_pkg::operation_e op_i,
input logic op_mod_i,
input fpnew_pkg::fp_format_e src_fmt_i,
input fpnew_pkg::fp_format_e dst_fmt_i,
input fpnew_pkg::int_format_e int_fmt_i,
input TagType tag_i,
input logic mask_i,
input AuxType aux_i,
// Input Handshake
input logic in_valid_i,
output logic in_ready_o,
input logic flush_i,
// Output signals
output logic [WIDTH-1:0] result_o,
output fpnew_pkg::status_t status_o,
output logic extension_bit_o,
output TagType tag_o,
output logic mask_o,
output AuxType aux_o,
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// Indication of valid data in flight
output logic busy_o
);
// ----------
// Constants
// ----------
localparam int unsigned NUM_INT_FORMATS = fpnew_pkg::NUM_INT_FORMATS;
localparam int unsigned MAX_INT_WIDTH = fpnew_pkg::max_int_width(IntFmtConfig);
localparam fpnew_pkg::fp_encoding_t SUPER_FORMAT = fpnew_pkg::super_format(FpFmtConfig);
localparam int unsigned SUPER_EXP_BITS = SUPER_FORMAT.exp_bits;
localparam int unsigned SUPER_MAN_BITS = SUPER_FORMAT.man_bits;
localparam int unsigned SUPER_BIAS = 2**(SUPER_EXP_BITS - 1) - 1;
// The internal mantissa includes normal bit or an entire integer
localparam int unsigned INT_MAN_WIDTH = fpnew_pkg::maximum(SUPER_MAN_BITS + 1, MAX_INT_WIDTH);
// If needed, there will be a LZC for renormalization
localparam int unsigned LZC_RESULT_WIDTH = $clog2(INT_MAN_WIDTH);
// The internal exponent must be able to represent the smallest denormal input value as signed
// or the number of bits in an integer
localparam int unsigned INT_EXP_WIDTH = fpnew_pkg::maximum($clog2(MAX_INT_WIDTH),
fpnew_pkg::maximum(SUPER_EXP_BITS, $clog2(SUPER_BIAS + SUPER_MAN_BITS))) + 1;
// Pipelines
localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? ((NumPipeRegs + 1) / 3) // Second to get distributed regs
: 0); // no regs here otherwise
localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? ((NumPipeRegs + 2) / 3) // First to get distributed regs
: 0); // no regs here otherwise
localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? (NumPipeRegs / 3) // Last to get distributed regs
: 0); // no regs here otherwise
// ---------------
// Input pipeline
// ---------------
// Selected pipeline output signals as non-arrays
logic [WIDTH-1:0] operands_q;
logic [NUM_FORMATS-1:0] is_boxed_q;
logic op_mod_q;
fpnew_pkg::fp_format_e src_fmt_q;
fpnew_pkg::fp_format_e dst_fmt_q;
fpnew_pkg::int_format_e int_fmt_q;
// Input pipeline signals, index i holds signal after i register stages
logic [0:NUM_INP_REGS][WIDTH-1:0] inp_pipe_operands_q;
logic [0:NUM_INP_REGS][NUM_FORMATS-1:0] inp_pipe_is_boxed_q;
fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q;
fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q;
logic [0:NUM_INP_REGS] inp_pipe_op_mod_q;
fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_src_fmt_q;
fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q;
fpnew_pkg::int_format_e [0:NUM_INP_REGS] inp_pipe_int_fmt_q;
TagType [0:NUM_INP_REGS] inp_pipe_tag_q;
logic [0:NUM_INP_REGS] inp_pipe_mask_q;
AuxType [0:NUM_INP_REGS] inp_pipe_aux_q;
logic [0:NUM_INP_REGS] inp_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_INP_REGS] inp_pipe_ready;
// Input stage: First element of pipeline is taken from inputs
assign inp_pipe_operands_q[0] = operands_i;
assign inp_pipe_is_boxed_q[0] = is_boxed_i;
assign inp_pipe_rnd_mode_q[0] = rnd_mode_i;
assign inp_pipe_op_q[0] = op_i;
assign inp_pipe_op_mod_q[0] = op_mod_i;
assign inp_pipe_src_fmt_q[0] = src_fmt_i;
assign inp_pipe_dst_fmt_q[0] = dst_fmt_i;
assign inp_pipe_int_fmt_q[0] = int_fmt_i;
assign inp_pipe_tag_q[0] = tag_i;
assign inp_pipe_mask_q[0] = mask_i;
assign inp_pipe_aux_q[0] = aux_i;
assign inp_pipe_valid_q[0] = in_valid_i;
// Input stage: Propagate pipeline ready signal to updtream circuitry
assign in_ready_o = inp_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0)
`FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0)
`FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
`FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD)
`FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0)
`FFL(inp_pipe_src_fmt_q[i+1], inp_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0))
`FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0))
`FFL(inp_pipe_int_fmt_q[i+1], inp_pipe_int_fmt_q[i], reg_ena, fpnew_pkg::int_format_e'(0))
`FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0)
`FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// Output stage: assign selected pipe outputs to signals for later use
assign operands_q = inp_pipe_operands_q[NUM_INP_REGS];
assign is_boxed_q = inp_pipe_is_boxed_q[NUM_INP_REGS];
assign op_mod_q = inp_pipe_op_mod_q[NUM_INP_REGS];
assign src_fmt_q = inp_pipe_src_fmt_q[NUM_INP_REGS];
assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS];
assign int_fmt_q = inp_pipe_int_fmt_q[NUM_INP_REGS];
// -----------------
// Input processing
// -----------------
logic src_is_int, dst_is_int; // if 0, it's a float
assign src_is_int = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::I2F);
assign dst_is_int = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::F2I);
logic [INT_MAN_WIDTH-1:0] encoded_mant; // input mantissa with implicit bit
logic [NUM_FORMATS-1:0] fmt_sign;
logic signed [NUM_FORMATS-1:0][INT_EXP_WIDTH-1:0] fmt_exponent;
logic [NUM_FORMATS-1:0][INT_MAN_WIDTH-1:0] fmt_mantissa;
logic signed [NUM_FORMATS-1:0][INT_EXP_WIDTH-1:0] fmt_shift_compensation; // for LZC
fpnew_pkg::fp_info_t [NUM_FORMATS-1:0] info;
logic [NUM_INT_FORMATS-1:0][INT_MAN_WIDTH-1:0] ifmt_input_val;
logic int_sign;
logic [INT_MAN_WIDTH-1:0] int_value, int_mantissa;
// FP Input initialization
for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : fmt_init_inputs
// Set up some constants
localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt));
if (FpFmtConfig[fmt]) begin : active_format
// Classify input
fpnew_classifier #(
.FpFormat ( fpnew_pkg::fp_format_e'(fmt) ),
.NumOperands ( 1 )
) i_fpnew_classifier (
.operands_i ( operands_q[FP_WIDTH-1:0] ),
.is_boxed_i ( is_boxed_q[fmt] ),
.info_o ( info[fmt] )
);
assign fmt_sign[fmt] = operands_q[FP_WIDTH-1];
assign fmt_exponent[fmt] = signed'({1'b0, operands_q[MAN_BITS+:EXP_BITS]});
assign fmt_mantissa[fmt] = {info[fmt].is_normal, operands_q[MAN_BITS-1:0]}; // zero pad
// Compensation for the difference in mantissa widths used for leading-zero count
assign fmt_shift_compensation[fmt] = signed'(INT_MAN_WIDTH - 1 - MAN_BITS);
end else begin : inactive_format
assign info[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled
assign fmt_sign[fmt] = fpnew_pkg::DONT_CARE; // format disabled
assign fmt_exponent[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled
assign fmt_mantissa[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled
assign fmt_shift_compensation[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled
end
end
// Sign-extend INT input
for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_sign_extend_int
// Set up some constants
localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt));
if (IntFmtConfig[ifmt]) begin : active_format // only active formats
always_comb begin : sign_ext_input
// sign-extend value only if it's signed
ifmt_input_val[ifmt] = '{default: operands_q[INT_WIDTH-1] & ~op_mod_q};
ifmt_input_val[ifmt][INT_WIDTH-1:0] = operands_q[INT_WIDTH-1:0];
end
end else begin : inactive_format
assign ifmt_input_val[ifmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled
end
end
// Construct input mantissa from integer
assign int_value = ifmt_input_val[int_fmt_q];
assign int_sign = int_value[INT_MAN_WIDTH-1] & ~op_mod_q; // only signed ints are negative
assign int_mantissa = int_sign ? unsigned'(-int_value) : int_value; // get magnitude of negative
// select mantissa with source format
assign encoded_mant = src_is_int ? int_mantissa : fmt_mantissa[src_fmt_q];
// --------------
// Normalization
// --------------
logic signed [INT_EXP_WIDTH-1:0] src_bias; // src format bias
logic signed [INT_EXP_WIDTH-1:0] src_exp; // src format exponent (biased)
logic signed [INT_EXP_WIDTH-1:0] src_subnormal; // src is subnormal
logic signed [INT_EXP_WIDTH-1:0] src_offset; // src offset within mantissa
assign src_bias = signed'(fpnew_pkg::bias(src_fmt_q));
assign src_exp = fmt_exponent[src_fmt_q];
assign src_subnormal = signed'({1'b0, info[src_fmt_q].is_subnormal});
assign src_offset = fmt_shift_compensation[src_fmt_q];
logic input_sign; // input sign
logic signed [INT_EXP_WIDTH-1:0] input_exp; // unbiased true exponent
logic [INT_MAN_WIDTH-1:0] input_mant; // normalized input mantissa
logic mant_is_zero; // for integer zeroes
logic signed [INT_EXP_WIDTH-1:0] fp_input_exp;
logic signed [INT_EXP_WIDTH-1:0] int_input_exp;
// Input mantissa needs to be normalized
logic [LZC_RESULT_WIDTH-1:0] renorm_shamt; // renormalization shift amount
logic [LZC_RESULT_WIDTH:0] renorm_shamt_sgn; // signed form for calculations
// Leading-zero counter is needed for renormalization
lzc #(
.WIDTH ( INT_MAN_WIDTH ),
.MODE ( 1 ) // MODE = 1 counts leading zeroes
) i_lzc (
.in_i ( encoded_mant ),
.cnt_o ( renorm_shamt ),
.empty_o ( mant_is_zero )
);
assign renorm_shamt_sgn = signed'({1'b0, renorm_shamt});
// Get the sign from the proper source
assign input_sign = src_is_int ? int_sign : fmt_sign[src_fmt_q];
// Realign input mantissa, append zeroes if destination is wider
assign input_mant = encoded_mant << renorm_shamt;
// Unbias exponent and compensate for shift
assign fp_input_exp = signed'(src_exp + src_subnormal - src_bias -
renorm_shamt_sgn + src_offset); // compensate for shift
assign int_input_exp = signed'(INT_MAN_WIDTH - 1 - renorm_shamt_sgn);
assign input_exp = src_is_int ? int_input_exp : fp_input_exp;
logic signed [INT_EXP_WIDTH-1:0] destination_exp; // re-biased exponent for destination
// Rebias the exponent
assign destination_exp = input_exp + signed'(fpnew_pkg::bias(dst_fmt_q));
// ---------------
// Internal pipeline
// ---------------
// Pipeline output signals as non-arrays
logic input_sign_q;
logic signed [INT_EXP_WIDTH-1:0] input_exp_q;
logic [INT_MAN_WIDTH-1:0] input_mant_q;
logic signed [INT_EXP_WIDTH-1:0] destination_exp_q;
logic src_is_int_q;
logic dst_is_int_q;
fpnew_pkg::fp_info_t info_q;
logic mant_is_zero_q;
logic op_mod_q2;
fpnew_pkg::roundmode_e rnd_mode_q;
fpnew_pkg::fp_format_e src_fmt_q2;
fpnew_pkg::fp_format_e dst_fmt_q2;
fpnew_pkg::int_format_e int_fmt_q2;
// Internal pipeline signals, index i holds signal after i register stages
logic [0:NUM_MID_REGS] mid_pipe_input_sign_q;
logic signed [0:NUM_MID_REGS][INT_EXP_WIDTH-1:0] mid_pipe_input_exp_q;
logic [0:NUM_MID_REGS][INT_MAN_WIDTH-1:0] mid_pipe_input_mant_q;
logic signed [0:NUM_MID_REGS][INT_EXP_WIDTH-1:0] mid_pipe_dest_exp_q;
logic [0:NUM_MID_REGS] mid_pipe_src_is_int_q;
logic [0:NUM_MID_REGS] mid_pipe_dst_is_int_q;
fpnew_pkg::fp_info_t [0:NUM_MID_REGS] mid_pipe_info_q;
logic [0:NUM_MID_REGS] mid_pipe_mant_zero_q;
logic [0:NUM_MID_REGS] mid_pipe_op_mod_q;
fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q;
fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_src_fmt_q;
fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_dst_fmt_q;
fpnew_pkg::int_format_e [0:NUM_MID_REGS] mid_pipe_int_fmt_q;
TagType [0:NUM_MID_REGS] mid_pipe_tag_q;
logic [0:NUM_MID_REGS] mid_pipe_mask_q;
AuxType [0:NUM_MID_REGS] mid_pipe_aux_q;
logic [0:NUM_MID_REGS] mid_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_MID_REGS] mid_pipe_ready;
// Input stage: First element of pipeline is taken from upstream logic
assign mid_pipe_input_sign_q[0] = input_sign;
assign mid_pipe_input_exp_q[0] = input_exp;
assign mid_pipe_input_mant_q[0] = input_mant;
assign mid_pipe_dest_exp_q[0] = destination_exp;
assign mid_pipe_src_is_int_q[0] = src_is_int;
assign mid_pipe_dst_is_int_q[0] = dst_is_int;
assign mid_pipe_info_q[0] = info[src_fmt_q];
assign mid_pipe_mant_zero_q[0] = mant_is_zero;
assign mid_pipe_op_mod_q[0] = op_mod_q;
assign mid_pipe_rnd_mode_q[0] = inp_pipe_rnd_mode_q[NUM_INP_REGS];
assign mid_pipe_src_fmt_q[0] = src_fmt_q;
assign mid_pipe_dst_fmt_q[0] = dst_fmt_q;
assign mid_pipe_int_fmt_q[0] = int_fmt_q;
assign mid_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS];
assign mid_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS];
assign mid_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS];
assign mid_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS];
// Input stage: Propagate pipeline ready signal to input pipe
assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign mid_pipe_ready[i] = mid_pipe_ready[i+1] | ~mid_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(mid_pipe_valid_q[i+1], mid_pipe_valid_q[i], mid_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = mid_pipe_ready[i] & mid_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(mid_pipe_input_sign_q[i+1], mid_pipe_input_sign_q[i], reg_ena, '0)
`FFL(mid_pipe_input_exp_q[i+1], mid_pipe_input_exp_q[i], reg_ena, '0)
`FFL(mid_pipe_input_mant_q[i+1], mid_pipe_input_mant_q[i], reg_ena, '0)
`FFL(mid_pipe_dest_exp_q[i+1], mid_pipe_dest_exp_q[i], reg_ena, '0)
`FFL(mid_pipe_src_is_int_q[i+1], mid_pipe_src_is_int_q[i], reg_ena, '0)
`FFL(mid_pipe_dst_is_int_q[i+1], mid_pipe_dst_is_int_q[i], reg_ena, '0)
`FFL(mid_pipe_info_q[i+1], mid_pipe_info_q[i], reg_ena, '0)
`FFL(mid_pipe_mant_zero_q[i+1], mid_pipe_mant_zero_q[i], reg_ena, '0)
`FFL(mid_pipe_op_mod_q[i+1], mid_pipe_op_mod_q[i], reg_ena, '0)
`FFL(mid_pipe_rnd_mode_q[i+1], mid_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
`FFL(mid_pipe_src_fmt_q[i+1], mid_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0))
`FFL(mid_pipe_dst_fmt_q[i+1], mid_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0))
`FFL(mid_pipe_int_fmt_q[i+1], mid_pipe_int_fmt_q[i], reg_ena, fpnew_pkg::int_format_e'(0))
`FFL(mid_pipe_tag_q[i+1], mid_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(mid_pipe_mask_q[i+1], mid_pipe_mask_q[i], reg_ena, '0)
`FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// Output stage: assign selected pipe outputs to signals for later use
assign input_sign_q = mid_pipe_input_sign_q[NUM_MID_REGS];
assign input_exp_q = mid_pipe_input_exp_q[NUM_MID_REGS];
assign input_mant_q = mid_pipe_input_mant_q[NUM_MID_REGS];
assign destination_exp_q = mid_pipe_dest_exp_q[NUM_MID_REGS];
assign src_is_int_q = mid_pipe_src_is_int_q[NUM_MID_REGS];
assign dst_is_int_q = mid_pipe_dst_is_int_q[NUM_MID_REGS];
assign info_q = mid_pipe_info_q[NUM_MID_REGS];
assign mant_is_zero_q = mid_pipe_mant_zero_q[NUM_MID_REGS];
assign op_mod_q2 = mid_pipe_op_mod_q[NUM_MID_REGS];
assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS];
assign src_fmt_q2 = mid_pipe_src_fmt_q[NUM_MID_REGS];
assign dst_fmt_q2 = mid_pipe_dst_fmt_q[NUM_MID_REGS];
assign int_fmt_q2 = mid_pipe_int_fmt_q[NUM_MID_REGS];
// --------
// Casting
// --------
logic [INT_EXP_WIDTH-1:0] final_exp; // after eventual adjustments
logic [2*INT_MAN_WIDTH:0] preshift_mant; // mantissa before final shift
logic [2*INT_MAN_WIDTH:0] destination_mant; // mantissa from shifter, with rnd bit
logic [SUPER_MAN_BITS-1:0] final_mant; // mantissa after adjustments
logic [MAX_INT_WIDTH-1:0] final_int; // integer shifted in position
logic [$clog2(INT_MAN_WIDTH+1)-1:0] denorm_shamt; // shift amount for denormalization
logic [1:0] fp_round_sticky_bits, int_round_sticky_bits, round_sticky_bits;
logic of_before_round, uf_before_round;
// Perform adjustments to mantissa and exponent
always_comb begin : cast_value
// Default assignment
final_exp = unsigned'(destination_exp_q); // take exponent as is, only look at lower bits
preshift_mant = '0; // initialize mantissa container with zeroes
denorm_shamt = SUPER_MAN_BITS - fpnew_pkg::man_bits(dst_fmt_q2); // right of mantissa
of_before_round = 1'b0;
uf_before_round = 1'b0;
// Place mantissa to the left of the shifter
preshift_mant = input_mant_q << (INT_MAN_WIDTH + 1);
// Handle INT casts
if (dst_is_int_q) begin
// By default right shift mantissa to be an integer
denorm_shamt = unsigned'(MAX_INT_WIDTH - 1 - input_exp_q);
// overflow: when converting to unsigned the range is larger by one
if (input_exp_q >= signed'(fpnew_pkg::int_width(int_fmt_q2) - 1 + op_mod_q2)) begin
denorm_shamt = '0; // prevent shifting
of_before_round = 1'b1;
// underflow
end else if (input_exp_q < -1) begin
denorm_shamt = MAX_INT_WIDTH + 1; // all bits go to the sticky
uf_before_round = 1'b1;
end
// Handle FP over-/underflows
end else begin
// Overflow or infinities (for proper rounding)
if ((destination_exp_q >= signed'(2**fpnew_pkg::exp_bits(dst_fmt_q2))-1) ||
(~src_is_int_q && info_q.is_inf)) begin
final_exp = unsigned'(2**fpnew_pkg::exp_bits(dst_fmt_q2)-2); // largest normal value
preshift_mant = '1; // largest normal value and RS bits set
of_before_round = 1'b1;
// Denormalize underflowing values
end else if (destination_exp_q < 1 &&
destination_exp_q >= -signed'(fpnew_pkg::man_bits(dst_fmt_q2))) begin
final_exp = '0; // denormal result
denorm_shamt = unsigned'(denorm_shamt + 1 - destination_exp_q); // adjust right shifting
uf_before_round = 1'b1;
// Limit the shift to retain sticky bits
end else if (destination_exp_q < -signed'(fpnew_pkg::man_bits(dst_fmt_q2))) begin
final_exp = '0; // denormal result
denorm_shamt = unsigned'(denorm_shamt + 2 + fpnew_pkg::man_bits(dst_fmt_q2)); // to sticky
uf_before_round = 1'b1;
end
end
end
localparam NUM_FP_STICKY = 2 * INT_MAN_WIDTH - SUPER_MAN_BITS - 1; // removed mantissa, 1. and R
localparam NUM_INT_STICKY = 2 * INT_MAN_WIDTH - MAX_INT_WIDTH; // removed int and R
// Mantissa adjustment shift
assign destination_mant = preshift_mant >> denorm_shamt;
// Extract final mantissa and round bit, discard the normal bit (for FP)
assign {final_mant, fp_round_sticky_bits[1]} =
destination_mant[2*INT_MAN_WIDTH-1-:SUPER_MAN_BITS+1];
assign {final_int, int_round_sticky_bits[1]} = destination_mant[2*INT_MAN_WIDTH-:MAX_INT_WIDTH+1];
// Collapse sticky bits
assign fp_round_sticky_bits[0] = (| {destination_mant[NUM_FP_STICKY-1:0]});
assign int_round_sticky_bits[0] = (| {destination_mant[NUM_INT_STICKY-1:0]});
// select RS bits for destination operation
assign round_sticky_bits = dst_is_int_q ? int_round_sticky_bits : fp_round_sticky_bits;
// ----------------------------
// Rounding and classification
// ----------------------------
logic [WIDTH-1:0] pre_round_abs; // absolute value of result before rnd
logic of_after_round; // overflow
logic uf_after_round; // underflow
logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_pre_round_abs; // per format
logic [NUM_FORMATS-1:0] fmt_of_after_round;
logic [NUM_FORMATS-1:0] fmt_uf_after_round;
logic [NUM_INT_FORMATS-1:0][WIDTH-1:0] ifmt_pre_round_abs; // per format
logic rounded_sign;
logic [WIDTH-1:0] rounded_abs; // absolute value of result after rounding
logic result_true_zero;
logic [WIDTH-1:0] rounded_int_res; // after possible inversion
logic rounded_int_res_zero; // after rounding
// Pack exponent and mantissa into proper rounding form
for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_res_assemble
// Set up some constants
localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt));
if (FpFmtConfig[fmt]) begin : active_format
always_comb begin : assemble_result
fmt_pre_round_abs[fmt] = {final_exp[EXP_BITS-1:0], final_mant[MAN_BITS-1:0]}; // 0-extend
end
end else begin : inactive_format
assign fmt_pre_round_abs[fmt] = '{default: fpnew_pkg::DONT_CARE};
end
end
// Sign-extend integer result
for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_int_res_sign_ext
// Set up some constants
localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt));
if (IntFmtConfig[ifmt]) begin : active_format
always_comb begin : assemble_result
// sign-extend reusult
ifmt_pre_round_abs[ifmt] = '{default: final_int[INT_WIDTH-1]};
ifmt_pre_round_abs[ifmt][INT_WIDTH-1:0] = final_int[INT_WIDTH-1:0];
end
end else begin : inactive_format
assign ifmt_pre_round_abs[ifmt] = '{default: fpnew_pkg::DONT_CARE};
end
end
// Select output with destination format and operation
assign pre_round_abs = dst_is_int_q ? ifmt_pre_round_abs[int_fmt_q2] : fmt_pre_round_abs[dst_fmt_q2];
fpnew_rounding #(
.AbsWidth ( WIDTH )
) i_fpnew_rounding (
.abs_value_i ( pre_round_abs ),
.sign_i ( input_sign_q ), // source format
.round_sticky_bits_i ( round_sticky_bits ),
.rnd_mode_i ( rnd_mode_q ),
.effective_subtraction_i ( 1'b0 ), // no operation happened
.abs_rounded_o ( rounded_abs ),
.sign_o ( rounded_sign ),
.exact_zero_o ( result_true_zero )
);
logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_result;
// Detect overflows and inject sign
for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_sign_inject
// Set up some constants
localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt));
if (FpFmtConfig[fmt]) begin : active_format
always_comb begin : post_process
// detect of / uf
fmt_uf_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0; // denormal
fmt_of_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // inf exp.
// Assemble regular result, nan box short ones. Int zeroes need to be detected`
fmt_result[fmt] = '1;
fmt_result[fmt][FP_WIDTH-1:0] = src_is_int_q & mant_is_zero_q
? '0
: {rounded_sign, rounded_abs[EXP_BITS+MAN_BITS-1:0]};
end
end else begin : inactive_format
assign fmt_uf_after_round[fmt] = fpnew_pkg::DONT_CARE;
assign fmt_of_after_round[fmt] = fpnew_pkg::DONT_CARE;
assign fmt_result[fmt] = '{default: fpnew_pkg::DONT_CARE};
end
end
// Classification after rounding select by destination format
assign uf_after_round = fmt_uf_after_round[dst_fmt_q2];
assign of_after_round = fmt_of_after_round[dst_fmt_q2];
// Negative integer result needs to be brought into two's complement
assign rounded_int_res = rounded_sign ? unsigned'(-rounded_abs) : rounded_abs;
assign rounded_int_res_zero = (rounded_int_res == '0);
// -------------------------
// FP Special case handling
// -------------------------
logic [WIDTH-1:0] fp_special_result;
fpnew_pkg::status_t fp_special_status;
logic fp_result_is_special;
logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_special_result;
// Special result construction
for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_special_results
// Set up some constants
localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt));
localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = '1;
localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1);
if (FpFmtConfig[fmt]) begin : active_format
always_comb begin : special_results
logic [FP_WIDTH-1:0] special_res;
special_res = info_q.is_zero
? input_sign_q << FP_WIDTH-1 // signed zero
: {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN
// Initialize special result with ones (NaN-box)
fmt_special_result[fmt] = '1;
fmt_special_result[fmt][FP_WIDTH-1:0] = special_res;
end
end else begin : inactive_format
assign fmt_special_result[fmt] = '{default: fpnew_pkg::DONT_CARE};
end
end
// Detect special case from source format, I2F casts don't produce a special result
assign fp_result_is_special = ~src_is_int_q & (info_q.is_zero |
info_q.is_nan |
~info_q.is_boxed);
// Signalling input NaNs raise invalid flag, otherwise no flags set
assign fp_special_status = '{NV: info_q.is_signalling, default: 1'b0};
// Assemble result according to destination format
assign fp_special_result = fmt_special_result[dst_fmt_q2]; // destination format
// --------------------------
// INT Special case handling
// --------------------------
logic [WIDTH-1:0] int_special_result;
fpnew_pkg::status_t int_special_status;
logic int_result_is_special;
logic [NUM_INT_FORMATS-1:0][WIDTH-1:0] ifmt_special_result;
// Special result construction
for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_special_results_int
// Set up some constants
localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt));
if (IntFmtConfig[ifmt]) begin : active_format
always_comb begin : special_results
automatic logic [INT_WIDTH-1:0] special_res;
// Default is overflow to positive max, which is 2**INT_WIDTH-1 or 2**(INT_WIDTH-1)-1
special_res[INT_WIDTH-2:0] = '1; // alone yields 2**(INT_WIDTH-1)-1
special_res[INT_WIDTH-1] = op_mod_q2; // for unsigned casts yields 2**INT_WIDTH-1
// Negative special case (except for nans) tie to -max or 0
if (input_sign_q && !info_q.is_nan)
special_res = ~special_res;
// Initialize special result with sign-extension
ifmt_special_result[ifmt] = '{default: special_res[INT_WIDTH-1]};
ifmt_special_result[ifmt][INT_WIDTH-1:0] = special_res;
end
end else begin : inactive_format
assign ifmt_special_result[ifmt] = '{default: fpnew_pkg::DONT_CARE};
end
end
// Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned)
assign int_result_is_special = info_q.is_nan | info_q.is_inf |
of_before_round | ~info_q.is_boxed |
(input_sign_q & op_mod_q2 & ~rounded_int_res_zero);
// All integer special cases are invalid
assign int_special_status = '{NV: 1'b1, default: 1'b0};
// Assemble result according to destination format
assign int_special_result = ifmt_special_result[int_fmt_q2]; // destination format
// -----------------
// Result selection
// -----------------
fpnew_pkg::status_t int_regular_status, fp_regular_status;
logic [WIDTH-1:0] fp_result, int_result;
fpnew_pkg::status_t fp_status, int_status;
assign fp_regular_status.NV = src_is_int_q & (of_before_round | of_after_round); // overflow is invalid for I2F casts
assign fp_regular_status.DZ = 1'b0; // no divisions
assign fp_regular_status.OF = ~src_is_int_q & (~info_q.is_inf & (of_before_round | of_after_round)); // inf casts no OF
assign fp_regular_status.UF = uf_after_round & fp_regular_status.NX;
assign fp_regular_status.NX = src_is_int_q ? (| fp_round_sticky_bits) // overflow is invalid in i2f
: (| fp_round_sticky_bits) | (~info_q.is_inf & (of_before_round | of_after_round));
assign int_regular_status = '{NX: (| int_round_sticky_bits), default: 1'b0};
assign fp_result = fp_result_is_special ? fp_special_result : fmt_result[dst_fmt_q2];
assign fp_status = fp_result_is_special ? fp_special_status : fp_regular_status;
assign int_result = int_result_is_special ? int_special_result : rounded_int_res;
assign int_status = int_result_is_special ? int_special_status : int_regular_status;
// Final results for output pipeline
logic [WIDTH-1:0] result_d;
fpnew_pkg::status_t status_d;
logic extension_bit;
// Select output depending on special case detection
assign result_d = dst_is_int_q ? int_result : fp_result;
assign status_d = dst_is_int_q ? int_status : fp_status;
// MSB of int result decides extension, otherwise NaN box
assign extension_bit = dst_is_int_q ? int_result[WIDTH-1] : 1'b1;
// ----------------
// Output Pipeline
// ----------------
// Output pipeline signals, index i holds signal after i register stages
logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q;
fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q;
logic [0:NUM_OUT_REGS] out_pipe_ext_bit_q;
TagType [0:NUM_OUT_REGS] out_pipe_tag_q;
logic [0:NUM_OUT_REGS] out_pipe_mask_q;
AuxType [0:NUM_OUT_REGS] out_pipe_aux_q;
logic [0:NUM_OUT_REGS] out_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_OUT_REGS] out_pipe_ready;
// Input stage: First element of pipeline is taken from inputs
assign out_pipe_result_q[0] = result_d;
assign out_pipe_status_q[0] = status_d;
assign out_pipe_ext_bit_q[0] = extension_bit;
assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS];
assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS];
assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS];
assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS];
// Input stage: Propagate pipeline ready signal to inside pipe
assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0)
`FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0)
`FFL(out_pipe_ext_bit_q[i+1], out_pipe_ext_bit_q[i], reg_ena, '0)
`FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0)
`FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// Output stage: Ready travels backwards from output side, driven by downstream circuitry
assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i;
// Output stage: assign module outputs
assign result_o = out_pipe_result_q[NUM_OUT_REGS];
assign status_o = out_pipe_status_q[NUM_OUT_REGS];
assign extension_bit_o = out_pipe_ext_bit_q[NUM_OUT_REGS];
assign tag_o = out_pipe_tag_q[NUM_OUT_REGS];
assign mask_o = out_pipe_mask_q[NUM_OUT_REGS];
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q});
endmodule |
module fpnew_fma_multi #(
parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1,
parameter int unsigned NumPipeRegs = 0,
parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE,
parameter type TagType = logic,
parameter type AuxType = logic,
// Do not change
localparam int unsigned WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig),
localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS
) (
input logic clk_i,
input logic rst_ni,
// Input signals
input logic [2:0][WIDTH-1:0] operands_i, // 3 operands
input logic [NUM_FORMATS-1:0][2:0] is_boxed_i, // 3 operands
input fpnew_pkg::roundmode_e rnd_mode_i,
input fpnew_pkg::operation_e op_i,
input logic op_mod_i,
input fpnew_pkg::fp_format_e src_fmt_i, // format of the multiplicands
input fpnew_pkg::fp_format_e dst_fmt_i, // format of the addend and result
input TagType tag_i,
input logic mask_i,
input AuxType aux_i,
// Input Handshake
input logic in_valid_i,
output logic in_ready_o,
input logic flush_i,
// Output signals
output logic [WIDTH-1:0] result_o,
output fpnew_pkg::status_t status_o,
output logic extension_bit_o,
output TagType tag_o,
output logic mask_o,
output AuxType aux_o,
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// Indication of valid data in flight
output logic busy_o
);
// ----------
// Constants
// ----------
// The super-format that can hold all formats
localparam fpnew_pkg::fp_encoding_t SUPER_FORMAT = fpnew_pkg::super_format(FpFmtConfig);
localparam int unsigned SUPER_EXP_BITS = SUPER_FORMAT.exp_bits;
localparam int unsigned SUPER_MAN_BITS = SUPER_FORMAT.man_bits;
// Precision bits 'p' include the implicit bit
localparam int unsigned PRECISION_BITS = SUPER_MAN_BITS + 1;
// The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection
localparam int unsigned LOWER_SUM_WIDTH = 2 * PRECISION_BITS + 3;
localparam int unsigned LZC_RESULT_WIDTH = $clog2(LOWER_SUM_WIDTH);
// Internal exponent width of FMA must accomodate all meaningful exponent values in order to avoid
// datapath leakage. This is either given by the exponent bits or the width of the LZC result.
// In most reasonable FP formats the internal exponent will be wider than the LZC result.
localparam int unsigned EXP_WIDTH = fpnew_pkg::maximum(SUPER_EXP_BITS + 2, LZC_RESULT_WIDTH);
// Shift amount width: maximum internal mantissa size is 3p+3 bits
localparam int unsigned SHIFT_AMOUNT_WIDTH = $clog2(3 * PRECISION_BITS + 3);
// Pipelines
localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? ((NumPipeRegs + 1) / 3) // Second to get distributed regs
: 0); // no regs here otherwise
localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? ((NumPipeRegs + 2) / 3) // First to get distributed regs
: 0); // no regs here otherwise
localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? (NumPipeRegs / 3) // Last to get distributed regs
: 0); // no regs here otherwise
// ----------------
// Type definition
// ----------------
typedef struct packed {
logic sign;
logic [SUPER_EXP_BITS-1:0] exponent;
logic [SUPER_MAN_BITS-1:0] mantissa;
} fp_t;
// ---------------
// Input pipeline
// ---------------
// Selected pipeline output signals as non-arrays
logic [2:0][WIDTH-1:0] operands_q;
fpnew_pkg::fp_format_e src_fmt_q;
fpnew_pkg::fp_format_e dst_fmt_q;
// Input pipeline signals, index i holds signal after i register stages
logic [0:NUM_INP_REGS][2:0][WIDTH-1:0] inp_pipe_operands_q;
logic [0:NUM_INP_REGS][NUM_FORMATS-1:0][2:0] inp_pipe_is_boxed_q;
fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q;
fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q;
logic [0:NUM_INP_REGS] inp_pipe_op_mod_q;
fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_src_fmt_q;
fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q;
TagType [0:NUM_INP_REGS] inp_pipe_tag_q;
logic [0:NUM_INP_REGS] inp_pipe_mask_q;
AuxType [0:NUM_INP_REGS] inp_pipe_aux_q;
logic [0:NUM_INP_REGS] inp_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_INP_REGS] inp_pipe_ready;
// Input stage: First element of pipeline is taken from inputs
assign inp_pipe_operands_q[0] = operands_i;
assign inp_pipe_is_boxed_q[0] = is_boxed_i;
assign inp_pipe_rnd_mode_q[0] = rnd_mode_i;
assign inp_pipe_op_q[0] = op_i;
assign inp_pipe_op_mod_q[0] = op_mod_i;
assign inp_pipe_src_fmt_q[0] = src_fmt_i;
assign inp_pipe_dst_fmt_q[0] = dst_fmt_i;
assign inp_pipe_tag_q[0] = tag_i;
assign inp_pipe_mask_q[0] = mask_i;
assign inp_pipe_aux_q[0] = aux_i;
assign inp_pipe_valid_q[0] = in_valid_i;
// Input stage: Propagate pipeline ready signal to updtream circuitry
assign in_ready_o = inp_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0)
`FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0)
`FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
`FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD)
`FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0)
`FFL(inp_pipe_src_fmt_q[i+1], inp_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0))
`FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0))
`FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0)
`FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// Output stage: assign selected pipe outputs to signals for later use
assign operands_q = inp_pipe_operands_q[NUM_INP_REGS];
assign src_fmt_q = inp_pipe_src_fmt_q[NUM_INP_REGS];
assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS];
// -----------------
// Input processing
// -----------------
logic [NUM_FORMATS-1:0][2:0] fmt_sign;
logic signed [NUM_FORMATS-1:0][2:0][SUPER_EXP_BITS-1:0] fmt_exponent;
logic [NUM_FORMATS-1:0][2:0][SUPER_MAN_BITS-1:0] fmt_mantissa;
fpnew_pkg::fp_info_t [NUM_FORMATS-1:0][2:0] info_q;
// FP Input initialization
for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : fmt_init_inputs
// Set up some constants
localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt));
if (FpFmtConfig[fmt]) begin : active_format
logic [2:0][FP_WIDTH-1:0] trimmed_ops;
// Classify input
fpnew_classifier #(
.FpFormat ( fpnew_pkg::fp_format_e'(fmt) ),
.NumOperands ( 3 )
) i_fpnew_classifier (
.operands_i ( trimmed_ops ),
.is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS][fmt] ),
.info_o ( info_q[fmt] )
);
for (genvar op = 0; op < 3; op++) begin : gen_operands
assign trimmed_ops[op] = operands_q[op][FP_WIDTH-1:0];
assign fmt_sign[fmt][op] = operands_q[op][FP_WIDTH-1];
assign fmt_exponent[fmt][op] = signed'({1'b0, operands_q[op][MAN_BITS+:EXP_BITS]});
assign fmt_mantissa[fmt][op] = {info_q[fmt][op].is_normal, operands_q[op][MAN_BITS-1:0]} <<
(SUPER_MAN_BITS - MAN_BITS); // move to left of mantissa
end
end else begin : inactive_format
assign info_q[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled
assign fmt_sign[fmt] = fpnew_pkg::DONT_CARE; // format disabled
assign fmt_exponent[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled
assign fmt_mantissa[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled
end
end
fp_t operand_a, operand_b, operand_c;
fpnew_pkg::fp_info_t info_a, info_b, info_c;
// Operation selection and operand adjustment
// | \c op_q | \c op_mod_q | Operation Adjustment
// |:--------:|:-----------:|---------------------
// | FMADD | \c 0 | FMADD: none
// | FMADD | \c 1 | FMSUB: Invert sign of operand C
// | FNMSUB | \c 0 | FNMSUB: Invert sign of operand A
// | FNMSUB | \c 1 | FNMADD: Invert sign of operands A and C
// | ADD | \c 0 | ADD: Set operand A to +1.0
// | ADD | \c 1 | SUB: Set operand A to +1.0, invert sign of operand C
// | MUL | \c 0 | MUL: Set operand C to +0.0
// | *others* | \c - | *invalid*
// \note \c op_mod_q always inverts the sign of the addend.
always_comb begin : op_select
// Default assignments - packing-order-agnostic
operand_a = {fmt_sign[src_fmt_q][0], fmt_exponent[src_fmt_q][0], fmt_mantissa[src_fmt_q][0]};
operand_b = {fmt_sign[src_fmt_q][1], fmt_exponent[src_fmt_q][1], fmt_mantissa[src_fmt_q][1]};
operand_c = {fmt_sign[dst_fmt_q][2], fmt_exponent[dst_fmt_q][2], fmt_mantissa[dst_fmt_q][2]};
info_a = info_q[src_fmt_q][0];
info_b = info_q[src_fmt_q][1];
info_c = info_q[dst_fmt_q][2];
// op_mod_q inverts sign of operand C
operand_c.sign = operand_c.sign ^ inp_pipe_op_mod_q[NUM_INP_REGS];
unique case (inp_pipe_op_q[NUM_INP_REGS])
fpnew_pkg::FMADD: ; // do nothing
fpnew_pkg::FNMSUB: operand_a.sign = ~operand_a.sign; // invert sign of product
fpnew_pkg::ADD: begin // Set multiplicand to +1
operand_a = '{sign: 1'b0, exponent: fpnew_pkg::bias(src_fmt_q), mantissa: '0};
info_a = '{is_normal: 1'b1, is_boxed: 1'b1, default: 1'b0}; //normal, boxed value.
end
fpnew_pkg::MUL: begin // Set addend to -0 (for proper rounding with RDN)
operand_c = '{sign: 1'b1, exponent: '0, mantissa: '0};
info_c = '{is_zero: 1'b1, is_boxed: 1'b1, default: 1'b0}; //zero, boxed value.
end
default: begin // propagate don't cares
operand_a = '{default: fpnew_pkg::DONT_CARE};
operand_b = '{default: fpnew_pkg::DONT_CARE};
operand_c = '{default: fpnew_pkg::DONT_CARE};
info_a = '{default: fpnew_pkg::DONT_CARE};
info_b = '{default: fpnew_pkg::DONT_CARE};
info_c = '{default: fpnew_pkg::DONT_CARE};
end
endcase
end
// ---------------------
// Input classification
// ---------------------
logic any_operand_inf;
logic any_operand_nan;
logic signalling_nan;
logic effective_subtraction;
logic tentative_sign;
// Reduction for special case handling
assign any_operand_inf = (| {info_a.is_inf, info_b.is_inf, info_c.is_inf});
assign any_operand_nan = (| {info_a.is_nan, info_b.is_nan, info_c.is_nan});
assign signalling_nan = (| {info_a.is_signalling, info_b.is_signalling, info_c.is_signalling});
// Effective subtraction in FMA occurs when product and addend signs differ
assign effective_subtraction = operand_a.sign ^ operand_b.sign ^ operand_c.sign;
// The tentative sign of the FMA shall be the sign of the product
assign tentative_sign = operand_a.sign ^ operand_b.sign;
// ----------------------
// Special case handling
// ----------------------
logic [WIDTH-1:0] special_result;
fpnew_pkg::status_t special_status;
logic result_is_special;
logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_special_result;
fpnew_pkg::status_t [NUM_FORMATS-1:0] fmt_special_status;
logic [NUM_FORMATS-1:0] fmt_result_is_special;
for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_special_results
// Set up some constants
localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt));
localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = '1;
localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1);
localparam logic [MAN_BITS-1:0] ZERO_MANTISSA = '0;
if (FpFmtConfig[fmt]) begin : active_format
always_comb begin : special_results
logic [FP_WIDTH-1:0] special_res;
// Default assignment
special_res = {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN
fmt_special_status[fmt] = '0;
fmt_result_is_special[fmt] = 1'b0;
// Handle potentially mixed nan & infinity input => important for the case where infinity and
// zero are multiplied and added to a qnan.
// RISC-V mandates raising the NV exception in these cases:
// (inf * 0) + c or (0 * inf) + c INVALID, no matter c (even quiet NaNs)
if ((info_a.is_inf && info_b.is_zero) || (info_a.is_zero && info_b.is_inf)) begin
fmt_result_is_special[fmt] = 1'b1; // bypass FMA, output is the canonical qNaN
fmt_special_status[fmt].NV = 1'b1; // invalid operation
// NaN Inputs cause canonical quiet NaN at the output and maybe invalid OP
end else if (any_operand_nan) begin
fmt_result_is_special[fmt] = 1'b1; // bypass FMA, output is the canonical qNaN
fmt_special_status[fmt].NV = signalling_nan; // raise the invalid operation flag if signalling
// Special cases involving infinity
end else if (any_operand_inf) begin
fmt_result_is_special[fmt] = 1'b1; // bypass FMA
// Effective addition of opposite infinities (±inf - ±inf) is invalid!
if ((info_a.is_inf || info_b.is_inf) && info_c.is_inf && effective_subtraction)
fmt_special_status[fmt].NV = 1'b1; // invalid operation
// Handle cases where output will be inf because of inf product input
else if (info_a.is_inf || info_b.is_inf) begin
// Result is infinity with the sign of the product
special_res = {operand_a.sign ^ operand_b.sign, QNAN_EXPONENT, ZERO_MANTISSA};
// Handle cases where the addend is inf
end else if (info_c.is_inf) begin
// Result is inifinity with sign of the addend (= operand_c)
special_res = {operand_c.sign, QNAN_EXPONENT, ZERO_MANTISSA};
end
end
// Initialize special result with ones (NaN-box)
fmt_special_result[fmt] = '1;
fmt_special_result[fmt][FP_WIDTH-1:0] = special_res;
end
end else begin : inactive_format
assign fmt_special_result[fmt] = '{default: fpnew_pkg::DONT_CARE};
end
end
// Detect special case from source format, I2F casts don't produce a special result
assign result_is_special = fmt_result_is_special[dst_fmt_q]; // they're all the same
// Signalling input NaNs raise invalid flag, otherwise no flags set
assign special_status = fmt_special_status[dst_fmt_q];
// Assemble result according to destination format
assign special_result = fmt_special_result[dst_fmt_q]; // destination format
// ---------------------------
// Initial exponent data path
// ---------------------------
logic signed [EXP_WIDTH-1:0] exponent_a, exponent_b, exponent_c;
logic signed [EXP_WIDTH-1:0] exponent_addend, exponent_product, exponent_difference;
logic signed [EXP_WIDTH-1:0] tentative_exponent;
// Zero-extend exponents into signed container - implicit width extension
assign exponent_a = signed'({1'b0, operand_a.exponent});
assign exponent_b = signed'({1'b0, operand_b.exponent});
assign exponent_c = signed'({1'b0, operand_c.exponent});
// Calculate internal exponents from encoded values. Real exponents are (ex = Ex - bias + 1 - nx)
// with Ex the encoded exponent and nx the implicit bit. Internal exponents are biased to dst fmt.
assign exponent_addend = signed'(exponent_c + $signed({1'b0, ~info_c.is_normal})); // 0 as subnorm
// Biased product exponent is the sum of encoded exponents minus the bias.
assign exponent_product = (info_a.is_zero || info_b.is_zero) // in case the product is zero, set minimum exp.
? 2 - signed'(fpnew_pkg::bias(dst_fmt_q))
: signed'(exponent_a + info_a.is_subnormal
+ exponent_b + info_b.is_subnormal
- 2*signed'(fpnew_pkg::bias(src_fmt_q))
+ signed'(fpnew_pkg::bias(dst_fmt_q))); // rebias for dst fmt
// Exponent difference is the addend exponent minus the product exponent
assign exponent_difference = exponent_addend - exponent_product;
// The tentative exponent will be the larger of the product or addend exponent
assign tentative_exponent = (exponent_difference > 0) ? exponent_addend : exponent_product;
// Shift amount for addend based on exponents (unsigned as only right shifts)
logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt;
always_comb begin : addend_shift_amount
// Product-anchored case, saturated shift (addend is only in the sticky bit)
if (exponent_difference <= signed'(-2 * PRECISION_BITS - 1))
addend_shamt = 3 * PRECISION_BITS + 4;
// Addend and product will have mutual bits to add
else if (exponent_difference <= signed'(PRECISION_BITS + 2))
addend_shamt = unsigned'(signed'(PRECISION_BITS) + 3 - exponent_difference);
// Addend-anchored case, saturated shift (product is only in the sticky bit)
else
addend_shamt = 0;
end
// ------------------
// Product data path
// ------------------
logic [PRECISION_BITS-1:0] mantissa_a, mantissa_b, mantissa_c;
logic [2*PRECISION_BITS-1:0] product; // the p*p product is 2p bits wide
logic [3*PRECISION_BITS+3:0] product_shifted; // addends are 3p+4 bit wide (including G/R)
// Add implicit bits to mantissae
assign mantissa_a = {info_a.is_normal, operand_a.mantissa};
assign mantissa_b = {info_b.is_normal, operand_b.mantissa};
assign mantissa_c = {info_c.is_normal, operand_c.mantissa};
// Mantissa multiplier (a*b)
assign product = mantissa_a * mantissa_b;
// Product is placed into a 3p+4 bit wide vector, padded with 2 bits for round and sticky:
// | 000...000 | product | RS |
// <- p+2 -> <- 2p -> < 2>
assign product_shifted = product << 2; // constant shift
// -----------------
// Addend data path
// -----------------
logic [3*PRECISION_BITS+3:0] addend_after_shift; // upper 3p+4 bits are needed to go on
logic [PRECISION_BITS-1:0] addend_sticky_bits; // up to p bit of shifted addend are sticky
logic sticky_before_add; // they are compressed into a single sticky bit
logic [3*PRECISION_BITS+3:0] addend_shifted; // addends are 3p+4 bit wide (including G/R)
logic inject_carry_in; // inject carry for subtractions if needed
// In parallel, the addend is right-shifted according to the exponent difference. Up to p bits are
// shifted out and compressed into a sticky bit.
// BEFORE THE SHIFT:
// | mantissa_c | 000..000 |
// <- p -> <- 3p+4 ->
// AFTER THE SHIFT:
// | 000..........000 | mantissa_c | 000...............0GR | sticky bits |
// <- addend_shamt -> <- p -> <- 2p+4-addend_shamt -> <- up to p ->
assign {addend_after_shift, addend_sticky_bits} =
(mantissa_c << (3 * PRECISION_BITS + 4)) >> addend_shamt;
assign sticky_before_add = (| addend_sticky_bits);
// In case of a subtraction, the addend is inverted
assign addend_shifted = (effective_subtraction) ? ~addend_after_shift : addend_after_shift;
assign inject_carry_in = effective_subtraction & ~sticky_before_add;
// ------
// Adder
// ------
logic [3*PRECISION_BITS+4:0] sum_raw; // added one bit for the carry
logic sum_carry; // observe carry bit from sum for sign fixing
logic [3*PRECISION_BITS+3:0] sum; // discard carry as sum won't overflow
logic final_sign;
//Mantissa adder (ab+c). In normal addition, it cannot overflow.
assign sum_raw = product_shifted + addend_shifted + inject_carry_in;
assign sum_carry = sum_raw[3*PRECISION_BITS+4];
// Complement negative sum (can only happen in subtraction -> overflows for positive results)
assign sum = (effective_subtraction && ~sum_carry) ? -sum_raw : sum_raw;
// In case of a mispredicted subtraction result, do a sign flip
assign final_sign = (effective_subtraction && (sum_carry == tentative_sign))
? 1'b1
: (effective_subtraction ? 1'b0 : tentative_sign);
// ---------------
// Internal pipeline
// ---------------
// Pipeline output signals as non-arrays
logic effective_subtraction_q;
logic signed [EXP_WIDTH-1:0] exponent_product_q;
logic signed [EXP_WIDTH-1:0] exponent_difference_q;
logic signed [EXP_WIDTH-1:0] tentative_exponent_q;
logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt_q;
logic sticky_before_add_q;
logic [3*PRECISION_BITS+3:0] sum_q;
logic final_sign_q;
fpnew_pkg::fp_format_e dst_fmt_q2;
fpnew_pkg::roundmode_e rnd_mode_q;
logic result_is_special_q;
fp_t special_result_q;
fpnew_pkg::status_t special_status_q;
// Internal pipeline signals, index i holds signal after i register stages
logic [0:NUM_MID_REGS] mid_pipe_eff_sub_q;
logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_prod_q;
logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_diff_q;
logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_tent_exp_q;
logic [0:NUM_MID_REGS][SHIFT_AMOUNT_WIDTH-1:0] mid_pipe_add_shamt_q;
logic [0:NUM_MID_REGS] mid_pipe_sticky_q;
logic [0:NUM_MID_REGS][3*PRECISION_BITS+3:0] mid_pipe_sum_q;
logic [0:NUM_MID_REGS] mid_pipe_final_sign_q;
fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q;
fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_dst_fmt_q;
logic [0:NUM_MID_REGS] mid_pipe_res_is_spec_q;
fp_t [0:NUM_MID_REGS] mid_pipe_spec_res_q;
fpnew_pkg::status_t [0:NUM_MID_REGS] mid_pipe_spec_stat_q;
TagType [0:NUM_MID_REGS] mid_pipe_tag_q;
logic [0:NUM_MID_REGS] mid_pipe_mask_q;
AuxType [0:NUM_MID_REGS] mid_pipe_aux_q;
logic [0:NUM_MID_REGS] mid_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_MID_REGS] mid_pipe_ready;
// Input stage: First element of pipeline is taken from upstream logic
assign mid_pipe_eff_sub_q[0] = effective_subtraction;
assign mid_pipe_exp_prod_q[0] = exponent_product;
assign mid_pipe_exp_diff_q[0] = exponent_difference;
assign mid_pipe_tent_exp_q[0] = tentative_exponent;
assign mid_pipe_add_shamt_q[0] = addend_shamt;
assign mid_pipe_sticky_q[0] = sticky_before_add;
assign mid_pipe_sum_q[0] = sum;
assign mid_pipe_final_sign_q[0] = final_sign;
assign mid_pipe_rnd_mode_q[0] = inp_pipe_rnd_mode_q[NUM_INP_REGS];
assign mid_pipe_dst_fmt_q[0] = dst_fmt_q;
assign mid_pipe_res_is_spec_q[0] = result_is_special;
assign mid_pipe_spec_res_q[0] = special_result;
assign mid_pipe_spec_stat_q[0] = special_status;
assign mid_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS];
assign mid_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS];
assign mid_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS];
assign mid_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS];
// Input stage: Propagate pipeline ready signal to input pipe
assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign mid_pipe_ready[i] = mid_pipe_ready[i+1] | ~mid_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(mid_pipe_valid_q[i+1], mid_pipe_valid_q[i], mid_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = mid_pipe_ready[i] & mid_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(mid_pipe_eff_sub_q[i+1], mid_pipe_eff_sub_q[i], reg_ena, '0)
`FFL(mid_pipe_exp_prod_q[i+1], mid_pipe_exp_prod_q[i], reg_ena, '0)
`FFL(mid_pipe_exp_diff_q[i+1], mid_pipe_exp_diff_q[i], reg_ena, '0)
`FFL(mid_pipe_tent_exp_q[i+1], mid_pipe_tent_exp_q[i], reg_ena, '0)
`FFL(mid_pipe_add_shamt_q[i+1], mid_pipe_add_shamt_q[i], reg_ena, '0)
`FFL(mid_pipe_sticky_q[i+1], mid_pipe_sticky_q[i], reg_ena, '0)
`FFL(mid_pipe_sum_q[i+1], mid_pipe_sum_q[i], reg_ena, '0)
`FFL(mid_pipe_final_sign_q[i+1], mid_pipe_final_sign_q[i], reg_ena, '0)
`FFL(mid_pipe_rnd_mode_q[i+1], mid_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
`FFL(mid_pipe_dst_fmt_q[i+1], mid_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0))
`FFL(mid_pipe_res_is_spec_q[i+1], mid_pipe_res_is_spec_q[i], reg_ena, '0)
`FFL(mid_pipe_spec_res_q[i+1], mid_pipe_spec_res_q[i], reg_ena, '0)
`FFL(mid_pipe_spec_stat_q[i+1], mid_pipe_spec_stat_q[i], reg_ena, '0)
`FFL(mid_pipe_tag_q[i+1], mid_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(mid_pipe_mask_q[i+1], mid_pipe_mask_q[i], reg_ena, '0)
`FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// Output stage: assign selected pipe outputs to signals for later use
assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_MID_REGS];
assign exponent_product_q = mid_pipe_exp_prod_q[NUM_MID_REGS];
assign exponent_difference_q = mid_pipe_exp_diff_q[NUM_MID_REGS];
assign tentative_exponent_q = mid_pipe_tent_exp_q[NUM_MID_REGS];
assign addend_shamt_q = mid_pipe_add_shamt_q[NUM_MID_REGS];
assign sticky_before_add_q = mid_pipe_sticky_q[NUM_MID_REGS];
assign sum_q = mid_pipe_sum_q[NUM_MID_REGS];
assign final_sign_q = mid_pipe_final_sign_q[NUM_MID_REGS];
assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS];
assign dst_fmt_q2 = mid_pipe_dst_fmt_q[NUM_MID_REGS];
assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_MID_REGS];
assign special_result_q = mid_pipe_spec_res_q[NUM_MID_REGS];
assign special_status_q = mid_pipe_spec_stat_q[NUM_MID_REGS];
// --------------
// Normalization
// --------------
logic [LOWER_SUM_WIDTH-1:0] sum_lower; // lower 2p+3 bits of sum are searched
logic [LZC_RESULT_WIDTH-1:0] leading_zero_count; // the number of leading zeroes
logic signed [LZC_RESULT_WIDTH:0] leading_zero_count_sgn; // signed leading-zero count
logic lzc_zeroes; // in case only zeroes found
logic [SHIFT_AMOUNT_WIDTH-1:0] norm_shamt; // Normalization shift amount
logic signed [EXP_WIDTH-1:0] normalized_exponent;
logic [3*PRECISION_BITS+4:0] sum_shifted; // result after first normalization shift
logic [PRECISION_BITS:0] final_mantissa; // final mantissa before rounding with round bit
logic [2*PRECISION_BITS+2:0] sum_sticky_bits; // remaining 2p+3 sticky bits after normalization
logic sticky_after_norm; // sticky bit after normalization
logic signed [EXP_WIDTH-1:0] final_exponent;
assign sum_lower = sum_q[LOWER_SUM_WIDTH-1:0];
// Leading zero counter for cancellations
lzc #(
.WIDTH ( LOWER_SUM_WIDTH ),
.MODE ( 1 ) // MODE = 1 counts leading zeroes
) i_lzc (
.in_i ( sum_lower ),
.cnt_o ( leading_zero_count ),
.empty_o ( lzc_zeroes )
);
assign leading_zero_count_sgn = signed'({1'b0, leading_zero_count});
// Normalization shift amount based on exponents and LZC (unsigned as only left shifts)
always_comb begin : norm_shift_amount
// Product-anchored case or cancellations require LZC
if ((exponent_difference_q <= 0) || (effective_subtraction_q && (exponent_difference_q <= 2))) begin
// Normal result (biased exponent > 0 and not a zero)
if ((exponent_product_q - leading_zero_count_sgn + 1 >= 0) && !lzc_zeroes) begin
// Undo initial product shift, remove the counted zeroes
norm_shamt = PRECISION_BITS + 2 + leading_zero_count;
normalized_exponent = exponent_product_q - leading_zero_count_sgn + 1; // account for shift
// Subnormal result
end else begin
// Cap the shift distance to align mantissa with minimum exponent
norm_shamt = unsigned'(signed'(PRECISION_BITS + 2 + exponent_product_q));
normalized_exponent = 0; // subnormals encoded as 0
end
// Addend-anchored case
end else begin
norm_shamt = addend_shamt_q; // Undo the initial shift
normalized_exponent = tentative_exponent_q;
end
end
// Do the large normalization shift
assign sum_shifted = sum_q << norm_shamt;
// The addend-anchored case needs a 1-bit normalization since the leading-one can be to the left
// or right of the (non-carry) MSB of the sum.
always_comb begin : small_norm
// Default assignment, discarding carry bit
{final_mantissa, sum_sticky_bits} = sum_shifted;
final_exponent = normalized_exponent;
// The normalized sum has overflown, align right and fix exponent
if (sum_shifted[3*PRECISION_BITS+4]) begin // check the carry bit
{final_mantissa, sum_sticky_bits} = sum_shifted >> 1;
final_exponent = normalized_exponent + 1;
// The normalized sum is normal, nothing to do
end else if (sum_shifted[3*PRECISION_BITS+3]) begin // check the sum MSB
// do nothing
// The normalized sum is still denormal, align left - unless the result is not already subnormal
end else if (normalized_exponent > 1) begin
{final_mantissa, sum_sticky_bits} = sum_shifted << 1;
final_exponent = normalized_exponent - 1;
// Otherwise we're denormal
end else begin
final_exponent = '0;
end
end
// Update the sticky bit with the shifted-out bits
assign sticky_after_norm = (| {sum_sticky_bits}) | sticky_before_add_q;
// ----------------------------
// Rounding and classification
// ----------------------------
logic pre_round_sign;
logic [SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] pre_round_abs; // absolute value of result before rounding
logic [1:0] round_sticky_bits;
logic of_before_round, of_after_round; // overflow
logic uf_before_round, uf_after_round; // underflow
logic [NUM_FORMATS-1:0][SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] fmt_pre_round_abs; // per format
logic [NUM_FORMATS-1:0][1:0] fmt_round_sticky_bits;
logic [NUM_FORMATS-1:0] fmt_of_after_round;
logic [NUM_FORMATS-1:0] fmt_uf_after_round;
logic rounded_sign;
logic [SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] rounded_abs; // absolute value of result after rounding
logic result_zero;
// Classification before round. RISC-V mandates checking underflow AFTER rounding!
assign of_before_round = final_exponent >= 2**(fpnew_pkg::exp_bits(dst_fmt_q2))-1; // infinity exponent is all ones
assign uf_before_round = final_exponent == 0; // exponent for subnormals capped to 0
// Pack exponent and mantissa into proper rounding form
for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_res_assemble
// Set up some constants
localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt));
logic [EXP_BITS-1:0] pre_round_exponent;
logic [MAN_BITS-1:0] pre_round_mantissa;
if (FpFmtConfig[fmt]) begin : active_format
assign pre_round_exponent = (of_before_round) ? 2**EXP_BITS-2 : final_exponent[EXP_BITS-1:0];
assign pre_round_mantissa = (of_before_round) ? '1 : final_mantissa[SUPER_MAN_BITS-:MAN_BITS];
// Assemble result before rounding. In case of overflow, the largest normal value is set.
assign fmt_pre_round_abs[fmt] = {pre_round_exponent, pre_round_mantissa}; // 0-extend
// Round bit is after mantissa (1 in case of overflow for rounding)
assign fmt_round_sticky_bits[fmt][1] = final_mantissa[SUPER_MAN_BITS-MAN_BITS] |
of_before_round;
// remaining bits in mantissa to sticky (1 in case of overflow for rounding)
if (MAN_BITS < SUPER_MAN_BITS) begin : narrow_sticky
assign fmt_round_sticky_bits[fmt][0] = (| final_mantissa[SUPER_MAN_BITS-MAN_BITS-1:0]) |
sticky_after_norm | of_before_round;
end else begin : normal_sticky
assign fmt_round_sticky_bits[fmt][0] = sticky_after_norm | of_before_round;
end
end else begin : inactive_format
assign fmt_pre_round_abs[fmt] = '{default: fpnew_pkg::DONT_CARE};
assign fmt_round_sticky_bits[fmt] = '{default: fpnew_pkg::DONT_CARE};
end
end
// Assemble result before rounding. In case of overflow, the largest normal value is set.
assign pre_round_sign = final_sign_q;
assign pre_round_abs = fmt_pre_round_abs[dst_fmt_q2];
// In case of overflow, the round and sticky bits are set for proper rounding
assign round_sticky_bits = fmt_round_sticky_bits[dst_fmt_q2];
// Perform the rounding
fpnew_rounding #(
.AbsWidth ( SUPER_EXP_BITS + SUPER_MAN_BITS )
) i_fpnew_rounding (
.abs_value_i ( pre_round_abs ),
.sign_i ( pre_round_sign ),
.round_sticky_bits_i ( round_sticky_bits ),
.rnd_mode_i ( rnd_mode_q ),
.effective_subtraction_i ( effective_subtraction_q ),
.abs_rounded_o ( rounded_abs ),
.sign_o ( rounded_sign ),
.exact_zero_o ( result_zero )
);
logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_result;
for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_sign_inject
// Set up some constants
localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt));
localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt));
if (FpFmtConfig[fmt]) begin : active_format
always_comb begin : post_process
// detect of / uf
fmt_uf_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0; // denormal
fmt_of_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // inf exp.
// Assemble regular result, nan box short ones.
fmt_result[fmt] = '1;
fmt_result[fmt][FP_WIDTH-1:0] = {rounded_sign, rounded_abs[EXP_BITS+MAN_BITS-1:0]};
end
end else begin : inactive_format
assign fmt_uf_after_round[fmt] = fpnew_pkg::DONT_CARE;
assign fmt_of_after_round[fmt] = fpnew_pkg::DONT_CARE;
assign fmt_result[fmt] = '{default: fpnew_pkg::DONT_CARE};
end
end
// Classification after rounding select by destination format
assign uf_after_round = fmt_uf_after_round[dst_fmt_q2];
assign of_after_round = fmt_of_after_round[dst_fmt_q2];
// -----------------
// Result selection
// -----------------
logic [WIDTH-1:0] regular_result;
fpnew_pkg::status_t regular_status;
// Assemble regular result
assign regular_result = fmt_result[dst_fmt_q2];
assign regular_status.NV = 1'b0; // only valid cases are handled in regular path
assign regular_status.DZ = 1'b0; // no divisions
assign regular_status.OF = of_before_round | of_after_round; // rounding can introduce overflow
assign regular_status.UF = uf_after_round & regular_status.NX; // only inexact results raise UF
assign regular_status.NX = (| round_sticky_bits) | of_before_round | of_after_round;
// Final results for output pipeline
logic [WIDTH-1:0] result_d;
fpnew_pkg::status_t status_d;
// Select output depending on special case detection
assign result_d = result_is_special_q ? special_result_q : regular_result;
assign status_d = result_is_special_q ? special_status_q : regular_status;
// ----------------
// Output Pipeline
// ----------------
// Output pipeline signals, index i holds signal after i register stages
logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q;
fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q;
TagType [0:NUM_OUT_REGS] out_pipe_tag_q;
logic [0:NUM_OUT_REGS] out_pipe_mask_q;
AuxType [0:NUM_OUT_REGS] out_pipe_aux_q;
logic [0:NUM_OUT_REGS] out_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_OUT_REGS] out_pipe_ready;
// Input stage: First element of pipeline is taken from inputs
assign out_pipe_result_q[0] = result_d;
assign out_pipe_status_q[0] = status_d;
assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS];
assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS];
assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS];
assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS];
// Input stage: Propagate pipeline ready signal to inside pipe
assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0)
`FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0)
`FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0)
`FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// Output stage: Ready travels backwards from output side, driven by downstream circuitry
assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i;
// Output stage: assign module outputs
assign result_o = out_pipe_result_q[NUM_OUT_REGS];
assign status_o = out_pipe_status_q[NUM_OUT_REGS];
assign extension_bit_o = 1'b1; // always NaN-Box result
assign tag_o = out_pipe_tag_q[NUM_OUT_REGS];
assign mask_o = out_pipe_mask_q[NUM_OUT_REGS];
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q});
endmodule |
module fpnew_divsqrt_multi #(
parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1,
// FPU configuration
parameter int unsigned NumPipeRegs = 0,
parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::AFTER,
parameter type TagType = logic,
parameter type AuxType = logic,
// Do not change
localparam int unsigned WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig),
localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS
) (
input logic clk_i,
input logic rst_ni,
// Input signals
input logic [1:0][WIDTH-1:0] operands_i, // 2 operands
input logic [NUM_FORMATS-1:0][1:0] is_boxed_i, // 2 operands
input fpnew_pkg::roundmode_e rnd_mode_i,
input fpnew_pkg::operation_e op_i,
input fpnew_pkg::fp_format_e dst_fmt_i,
input TagType tag_i,
input logic mask_i,
input AuxType aux_i,
// Input Handshake
input logic in_valid_i,
output logic in_ready_o,
output logic divsqrt_done_o,
input logic simd_synch_done_i,
output logic divsqrt_ready_o,
input logic simd_synch_rdy_i,
input logic flush_i,
// Output signals
output logic [WIDTH-1:0] result_o,
output fpnew_pkg::status_t status_o,
output logic extension_bit_o,
output TagType tag_o,
output logic mask_o,
output AuxType aux_o,
// Output handshake
output logic out_valid_o,
input logic out_ready_i,
// Indication of valid data in flight
output logic busy_o
);
// ----------
// Constants
// ----------
// Pipelines
localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE)
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? (NumPipeRegs / 2) // Last to get distributed regs
: 0); // no regs here otherwise
localparam NUM_OUT_REGS = (PipeConfig == fpnew_pkg::AFTER || PipeConfig == fpnew_pkg::INSIDE)
? NumPipeRegs
: (PipeConfig == fpnew_pkg::DISTRIBUTED
? ((NumPipeRegs + 1) / 2) // First to get distributed regs
: 0); // no regs here otherwise
// ---------------
// Input pipeline
// ---------------
// Selected pipeline output signals as non-arrays
logic [1:0][WIDTH-1:0] operands_q;
fpnew_pkg::roundmode_e rnd_mode_q;
fpnew_pkg::operation_e op_q;
fpnew_pkg::fp_format_e dst_fmt_q;
logic in_valid_q;
// Input pipeline signals, index i holds signal after i register stages
logic [0:NUM_INP_REGS][1:0][WIDTH-1:0] inp_pipe_operands_q;
fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q;
fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q;
fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q;
TagType [0:NUM_INP_REGS] inp_pipe_tag_q;
logic [0:NUM_INP_REGS] inp_pipe_mask_q;
AuxType [0:NUM_INP_REGS] inp_pipe_aux_q;
logic [0:NUM_INP_REGS] inp_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_INP_REGS] inp_pipe_ready;
// Input stage: First element of pipeline is taken from inputs
assign inp_pipe_operands_q[0] = operands_i;
assign inp_pipe_rnd_mode_q[0] = rnd_mode_i;
assign inp_pipe_op_q[0] = op_i;
assign inp_pipe_dst_fmt_q[0] = dst_fmt_i;
assign inp_pipe_tag_q[0] = tag_i;
assign inp_pipe_mask_q[0] = mask_i;
assign inp_pipe_aux_q[0] = aux_i;
assign inp_pipe_valid_q[0] = in_valid_i;
// Input stage: Propagate pipeline ready signal to updtream circuitry
assign in_ready_o = inp_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0)
`FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
`FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD)
`FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0))
`FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0)
`FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// Output stage: assign selected pipe outputs to signals for later use
assign operands_q = inp_pipe_operands_q[NUM_INP_REGS];
assign rnd_mode_q = inp_pipe_rnd_mode_q[NUM_INP_REGS];
assign op_q = inp_pipe_op_q[NUM_INP_REGS];
assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS];
assign in_valid_q = inp_pipe_valid_q[NUM_INP_REGS];
// -----------------
// Input processing
// -----------------
logic [1:0] divsqrt_fmt;
logic [1:0][63:0] divsqrt_operands; // those are fixed to 64bit
logic input_is_fp8;
// Translate fpnew formats into divsqrt formats
always_comb begin : translate_fmt
unique case (dst_fmt_q)
fpnew_pkg::FP32: divsqrt_fmt = 2'b00;
fpnew_pkg::FP64: divsqrt_fmt = 2'b01;
fpnew_pkg::FP16: divsqrt_fmt = 2'b10;
fpnew_pkg::FP16ALT: divsqrt_fmt = 2'b11;
default: divsqrt_fmt = 2'b10; // maps also FP8 to FP16
endcase
// Only if FP8 is enabled
input_is_fp8 = FpFmtConfig[fpnew_pkg::FP8] & (dst_fmt_q == fpnew_pkg::FP8);
// If FP8 is supported, map it to an FP16 value
divsqrt_operands[0] = input_is_fp8 ? operands_q[0] << 8 : operands_q[0];
divsqrt_operands[1] = input_is_fp8 ? operands_q[1] << 8 : operands_q[1];
end
// ------------
// Control FSM
// ------------
logic in_ready; // input handshake with upstream
logic div_valid, sqrt_valid; // input signalling with unit
logic unit_ready, unit_done, unit_done_q; // status signals from unit instance
logic op_starting; // high in the cycle a new operation starts
logic out_valid, out_ready; // output handshake with downstream
logic unit_busy; // valid data in flight
// FSM states
typedef enum logic [1:0] {IDLE, BUSY, HOLD} fsm_state_e;
fsm_state_e state_q, state_d;
// Ready synch with other lanes
// Bring the FSM-generated ready outside the unit, to synchronize it with the other lanes
assign divsqrt_ready_o = in_ready;
// Upstream ready comes from sanitization FSM, and it is synched among all the lanes
assign inp_pipe_ready[NUM_INP_REGS] = simd_synch_rdy_i;
// Valid synch with other lanes
// When one divsqrt unit completes an operation, keep its done high, waiting for the other lanes
// As soon as all the lanes are over, we can clear this FF and start with a new operation
`FFLARNC(unit_done_q, unit_done, unit_done, simd_synch_done_i, 1'b0, clk_i, rst_ni);
// Tell the other units that this unit has finished now or in the past
assign divsqrt_done_o = unit_done_q | unit_done;
// Valids are gated by the FSM ready. Invalid input ops run a sqrt to not lose illegal instr.
assign div_valid = in_valid_q & (op_q == fpnew_pkg::DIV) & in_ready & ~flush_i;
assign sqrt_valid = in_valid_q & (op_q != fpnew_pkg::DIV) & in_ready & ~flush_i;
assign op_starting = div_valid | sqrt_valid;
// FSM to safely apply and receive data from DIVSQRT unit
always_comb begin : flag_fsm
// Default assignments
in_ready = 1'b0;
out_valid = 1'b0;
unit_busy = 1'b0;
state_d = state_q;
unique case (state_q)
// Waiting for work
IDLE: begin
in_ready = 1'b1; // we're ready
if (in_valid_q && unit_ready) begin // New work arrives
state_d = BUSY; // go into processing state
end
end
// Operation in progress
BUSY: begin
unit_busy = 1'b1; // data in flight
// If all the lanes are done with processing
if (simd_synch_done_i) begin
out_valid = 1'b1; // try to commit result downstream
// If downstream accepts our result
if (out_ready) begin
state_d = IDLE; // we anticipate going back to idling..
if (in_valid_q && unit_ready) begin // ..unless new work comes in
in_ready = 1'b1; // we acknowledge the instruction
state_d = BUSY; // and stay busy with it
end
// Otherwise if downstream is not ready for the result
end else begin
state_d = HOLD; // wait for the pipeline to take the data
end
end
end
// Waiting with valid result for downstream
HOLD: begin
unit_busy = 1'b1; // data in flight
out_valid = 1'b1; // try to commit result downstream
// If the result is accepted by downstream
if (out_ready) begin
state_d = IDLE; // go back to idle..
if (in_valid_q && unit_ready) begin // ..unless new work comes in
in_ready = 1'b1; // acknowledge the new transaction
state_d = BUSY; // will be busy with the next instruction
end
end
end
// fall into idle state otherwise
default: state_d = IDLE;
endcase
// Flushing overrides the other actions
if (flush_i) begin
unit_busy = 1'b0; // data is invalidated
out_valid = 1'b0; // cancel any valid data
state_d = IDLE; // go to default state
end
end
// FSM status register (asynch active low reset)
`FF(state_q, state_d, IDLE)
// Hold additional information while the operation is in progress
logic result_is_fp8_q;
TagType result_tag_q;
logic result_mask_q;
AuxType result_aux_q;
// Fill the registers everytime a valid operation arrives (load FF, active low asynch rst)
`FFL(result_is_fp8_q, input_is_fp8, op_starting, '0)
`FFL(result_tag_q, inp_pipe_tag_q[NUM_INP_REGS], op_starting, '0)
`FFL(result_mask_q, inp_pipe_mask_q[NUM_INP_REGS],op_starting, '0)
`FFL(result_aux_q, inp_pipe_aux_q[NUM_INP_REGS], op_starting, '0)
// -----------------
// DIVSQRT instance
// -----------------
logic [63:0] unit_result;
logic [WIDTH-1:0] adjusted_result, held_result_q;
fpnew_pkg::status_t unit_status, held_status_q;
logic hold_en;
div_sqrt_top_mvp i_divsqrt_lei (
.Clk_CI ( clk_i ),
.Rst_RBI ( rst_ni ),
.Div_start_SI ( div_valid ),
.Sqrt_start_SI ( sqrt_valid ),
.Operand_a_DI ( divsqrt_operands[0] ),
.Operand_b_DI ( divsqrt_operands[1] ),
.RM_SI ( rnd_mode_q ),
.Precision_ctl_SI ( '0 ),
.Format_sel_SI ( divsqrt_fmt ),
.Kill_SI ( flush_i ),
.Result_DO ( unit_result ),
.Fflags_SO ( unit_status ),
.Ready_SO ( unit_ready ),
.Done_SO ( unit_done )
);
// Adjust result width and fix FP8
assign adjusted_result = result_is_fp8_q ? unit_result >> 8 : unit_result;
// Hold the result when one lane has finished execution, except when all the lanes finish together
// and the result can be accepted downstream
assign hold_en = unit_done & (~simd_synch_done_i | ~out_ready);
// The Hold register (load, no reset)
`FFLNR(held_result_q, adjusted_result, hold_en, clk_i)
`FFLNR(held_status_q, unit_status, hold_en, clk_i)
// --------------
// Output Select
// --------------
logic [WIDTH-1:0] result_d;
fpnew_pkg::status_t status_d;
// Prioritize hold register data
assign result_d = unit_done_q ? held_result_q : adjusted_result;
assign status_d = unit_done_q ? held_status_q : unit_status;
// ----------------
// Output Pipeline
// ----------------
// Output pipeline signals, index i holds signal after i register stages
logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q;
fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q;
TagType [0:NUM_OUT_REGS] out_pipe_tag_q;
logic [0:NUM_OUT_REGS] out_pipe_mask_q;
AuxType [0:NUM_OUT_REGS] out_pipe_aux_q;
logic [0:NUM_OUT_REGS] out_pipe_valid_q;
// Ready signal is combinatorial for all stages
logic [0:NUM_OUT_REGS] out_pipe_ready;
// Input stage: First element of pipeline is taken from inputs
assign out_pipe_result_q[0] = result_d;
assign out_pipe_status_q[0] = status_d;
assign out_pipe_tag_q[0] = result_tag_q;
assign out_pipe_mask_q[0] = result_mask_q;
assign out_pipe_aux_q[0] = result_aux_q;
assign out_pipe_valid_q[0] = out_valid;
// Input stage: Propagate pipeline ready signal to inside pipe
assign out_ready = out_pipe_ready[0];
// Generate the register stages
for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline
// Internal register enable for this stage
logic reg_ena;
// Determine the ready signal of the current stage - advance the pipeline:
// 1. if the next stage is ready for our data
// 2. if the next stage only holds a bubble (not valid) -> we can pop it
assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1];
// Valid: enabled by ready signal, synchronous clear with the flush signal
`FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)
// Enable register if pipleine ready and a valid data item is present
assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i];
// Generate the pipeline registers within the stages, use enable-registers
`FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0)
`FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0)
`FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0))
`FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0)
`FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0))
end
// Output stage: Ready travels backwards from output side, driven by downstream circuitry
assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i;
// Output stage: assign module outputs
assign result_o = out_pipe_result_q[NUM_OUT_REGS];
assign status_o = out_pipe_status_q[NUM_OUT_REGS];
assign extension_bit_o = 1'b1; // always NaN-Box result
assign tag_o = out_pipe_tag_q[NUM_OUT_REGS];
assign mask_o = out_pipe_mask_q[NUM_OUT_REGS];
assign aux_o = out_pipe_aux_q[NUM_OUT_REGS];
assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS];
assign busy_o = (| {inp_pipe_valid_q, unit_busy, out_pipe_valid_q});
endmodule |
module cdc_fifo_gray #(
/// The width of the default logic type.
parameter WIDTH = 1,
/// The data type of the payload transported by the FIFO.
parameter type T = logic [WIDTH-1:0],
/// The FIFO's depth given as 2**LOG_DEPTH.
parameter int LOG_DEPTH = 3,
/// The number of synchronization registers to insert on the async pointers.
parameter int SYNC_STAGES = 2
) (
input logic src_rst_ni,
input logic src_clk_i,
input T src_data_i,
input logic src_valid_i,
output logic src_ready_o,
input logic dst_rst_ni,
input logic dst_clk_i,
output T dst_data_o,
output logic dst_valid_o,
input logic dst_ready_i
);
T [2**LOG_DEPTH-1:0] async_data;
logic [LOG_DEPTH:0] async_wptr;
logic [LOG_DEPTH:0] async_rptr;
cdc_fifo_gray_src #(
.T ( T ),
.LOG_DEPTH ( LOG_DEPTH )
) i_src (
.src_rst_ni,
.src_clk_i,
.src_data_i,
.src_valid_i,
.src_ready_o,
(* async *) .async_data_o ( async_data ),
(* async *) .async_wptr_o ( async_wptr ),
(* async *) .async_rptr_i ( async_rptr )
);
cdc_fifo_gray_dst #(
.T ( T ),
.LOG_DEPTH ( LOG_DEPTH )
) i_dst (
.dst_rst_ni,
.dst_clk_i,
.dst_data_o,
.dst_valid_o,
.dst_ready_i,
(* async *) .async_data_i ( async_data ),
(* async *) .async_wptr_i ( async_wptr ),
(* async *) .async_rptr_o ( async_rptr )
);
// Check the invariants.
// pragma translate_off
`ifndef VERILATOR
initial assert(LOG_DEPTH > 0);
initial assert(SYNC_STAGES >= 2);
`endif
// pragma translate_on
endmodule |
module cdc_fifo_gray_src #(
parameter type T = logic,
parameter int LOG_DEPTH = 3,
parameter int SYNC_STAGES = 2
)(
input logic src_rst_ni,
input logic src_clk_i,
input T src_data_i,
input logic src_valid_i,
output logic src_ready_o,
output T [2**LOG_DEPTH-1:0] async_data_o,
output logic [LOG_DEPTH:0] async_wptr_o,
input logic [LOG_DEPTH:0] async_rptr_i
);
localparam int PTR_WIDTH = LOG_DEPTH+1;
localparam [PTR_WIDTH-1:0] PTR_FULL = (1 << LOG_DEPTH);
T [2**LOG_DEPTH-1:0] data_q;
logic [PTR_WIDTH-1:0] wptr_q, wptr_d, wptr_bin, wptr_next, rptr, rptr_bin;
// Data FIFO.
assign async_data_o = data_q;
for (genvar i = 0; i < 2**LOG_DEPTH; i++) begin : gen_word
`FFLNR(data_q[i], src_data_i, src_valid_i & src_ready_o & (wptr_bin[LOG_DEPTH-1:0] == i), src_clk_i)
end
// Read pointer.
for (genvar i = 0; i < PTR_WIDTH; i++) begin : gen_sync
sync #(.STAGES(SYNC_STAGES)) i_sync (
.clk_i ( src_clk_i ),
.rst_ni ( src_rst_ni ),
.serial_i ( async_rptr_i[i] ),
.serial_o ( rptr[i] )
);
end
gray_to_binary #(PTR_WIDTH) i_rptr_g2b (.A(rptr), .Z(rptr_bin));
// Write pointer.
assign wptr_next = wptr_bin+1;
gray_to_binary #(PTR_WIDTH) i_wptr_g2b (.A(wptr_q), .Z(wptr_bin));
binary_to_gray #(PTR_WIDTH) i_wptr_b2g (.A(wptr_next), .Z(wptr_d));
`FFLARN(wptr_q, wptr_d, src_valid_i & src_ready_o, '0, src_clk_i, src_rst_ni)
assign async_wptr_o = wptr_q;
// The pointers into the FIFO are one bit wider than the actual address into
// the FIFO. This makes detecting critical states very simple: if all but the
// topmost bit of rptr and wptr agree, the FIFO is in a critical state. If the
// topmost bit is equal, the FIFO is empty, otherwise it is full.
assign src_ready_o = ((wptr_bin ^ rptr_bin) != PTR_FULL);
endmodule |
module cdc_fifo_gray_dst #(
parameter type T = logic,
parameter int LOG_DEPTH = 3,
parameter int SYNC_STAGES = 2
)(
input logic dst_rst_ni,
input logic dst_clk_i,
output T dst_data_o,
output logic dst_valid_o,
input logic dst_ready_i,
input T [2**LOG_DEPTH-1:0] async_data_i,
input logic [LOG_DEPTH:0] async_wptr_i,
output logic [LOG_DEPTH:0] async_rptr_o
);
localparam int PTR_WIDTH = LOG_DEPTH+1;
localparam [PTR_WIDTH-1:0] PTR_EMPTY = '0;
T dst_data;
logic [PTR_WIDTH-1:0] rptr_q, rptr_d, rptr_bin, rptr_bin_d, rptr_next, wptr, wptr_bin;
logic dst_valid, dst_ready;
// Data selector and register.
assign dst_data = async_data_i[rptr_bin[LOG_DEPTH-1:0]];
// Read pointer.
assign rptr_next = rptr_bin+1;
gray_to_binary #(PTR_WIDTH) i_rptr_g2b (.A(rptr_q), .Z(rptr_bin));
binary_to_gray #(PTR_WIDTH) i_rptr_b2g (.A(rptr_next), .Z(rptr_d));
`FFLARN(rptr_q, rptr_d, dst_valid & dst_ready, '0, dst_clk_i, dst_rst_ni)
assign async_rptr_o = rptr_q;
// Write pointer.
for (genvar i = 0; i < PTR_WIDTH; i++) begin : gen_sync
sync #(.STAGES(SYNC_STAGES)) i_sync (
.clk_i ( dst_clk_i ),
.rst_ni ( dst_rst_ni ),
.serial_i ( async_wptr_i[i] ),
.serial_o ( wptr[i] )
);
end
gray_to_binary #(PTR_WIDTH) i_wptr_g2b (.A(wptr), .Z(wptr_bin));
// The pointers into the FIFO are one bit wider than the actual address into
// the FIFO. This makes detecting critical states very simple: if all but the
// topmost bit of rptr and wptr agree, the FIFO is in a critical state. If the
// topmost bit is equal, the FIFO is empty, otherwise it is full.
assign dst_valid = ((wptr_bin ^ rptr_bin) != PTR_EMPTY);
// Cut the combinatorial path with a spill register.
spill_register #(
.T ( T )
) i_spill_register (
.clk_i ( dst_clk_i ),
.rst_ni ( dst_rst_ni ),
.valid_i ( dst_valid ),
.ready_o ( dst_ready ),
.data_i ( dst_data ),
.valid_o ( dst_valid_o ),
.ready_i ( dst_ready_i ),
.data_o ( dst_data_o )
);
endmodule |
module tb_axi_id_remap;
parameter AW = 32;
parameter DW = 32;
parameter IW = 8;
parameter UW = 8;
parameter IWO = 4;
parameter TS = 4;
localparam tCK = 1ns;
logic clk = 0;
logic rst = 1;
logic done = 0;
AXI_BUS_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IWO),
.AXI_USER_WIDTH(UW)
) axi_slave_dv(clk);
AXI_BUS #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IWO),
.AXI_USER_WIDTH(UW)
) axi_slave();
`AXI_ASSIGN(axi_slave_dv, axi_slave);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi_master_dv(clk);
AXI_BUS #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi_master();
`AXI_ASSIGN(axi_master, axi_master_dv);
axi_id_remap #(
.ADDR_WIDTH (AW),
.DATA_WIDTH (DW),
.USER_WIDTH (UW),
.ID_WIDTH_IN (IW),
.ID_WIDTH_OUT (IWO),
.TABLE_SIZE (TS)
) i_dut (
.clk_i ( clk ),
.rst_ni ( rst ),
.in ( axi_master ),
.out ( axi_slave )
);
axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IWO), .UW(UW), .TA(200ps), .TT(700ps)) axi_slave_drv = new(axi_slave_dv);
axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(200ps), .TT(700ps)) axi_master_drv = new(axi_master_dv);
initial begin
#tCK;
rst <= 0;
#tCK;
rst <= 1;
#tCK;
while (!done) begin
clk <= 1;
#(tCK/2);
clk <= 0;
#(tCK/2);
end
end
initial begin
automatic axi_test::axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat = new;
automatic axi_test::axi_w_beat #(.DW(DW), .UW(UW)) w_beat = new;
automatic axi_test::axi_b_beat #(.IW(IW), .UW(UW)) b_beat;
axi_master_drv.reset_master();
@(posedge clk);
repeat (4) begin
@(posedge clk);
void'(randomize(ax_beat));
axi_master_drv.send_aw(ax_beat);
w_beat.w_data = 'hcafebabe;
axi_master_drv.send_w(w_beat);
end
repeat (4) axi_master_drv.recv_b(b_beat);
done = 1;
end
initial begin
automatic axi_test::axi_ax_beat #(.AW(AW), .IW(IWO), .UW(UW)) ax_beat;
automatic axi_test::axi_w_beat #(.DW(DW), .UW(UW)) w_beat;
automatic axi_test::axi_b_beat #(.IW(IWO), .UW(UW)) b_beat = new;
axi_slave_drv.reset_slave();
@(posedge clk);
repeat (4) begin
axi_slave_drv.recv_aw(ax_beat);
$info("AXI AW: addr %h", ax_beat.ax_addr);
axi_slave_drv.recv_w(w_beat);
$info("AXI W: data %h, strb %h", w_beat.w_data, w_beat.w_strb);
end
b_beat.b_id = 2;
axi_slave_drv.send_b(b_beat);
b_beat.b_id = 0;
axi_slave_drv.send_b(b_beat);
b_beat.b_id = 1;
axi_slave_drv.send_b(b_beat);
b_beat.b_id = 3;
axi_slave_drv.send_b(b_beat);
end
// vsim -voptargs=+acc work.tb_axi_id_remap
endmodule |
module tb_axi_to_axi_lite;
parameter AW = 32;
parameter DW = 32;
parameter IW = 8;
parameter UW = 8;
localparam tCK = 1ns;
localparam TA = tCK * 1/4;
localparam TT = tCK * 3/4;
logic clk = 0;
logic rst = 1;
logic done = 0;
AXI_LITE_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) axi_lite_dv(clk);
AXI_LITE #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) axi_lite();
`AXI_LITE_ASSIGN(axi_lite_dv, axi_lite);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi_dv(clk);
AXI_BUS #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi();
`AXI_ASSIGN(axi, axi_dv);
axi_to_axi_lite i_dut (
.clk_i ( clk ),
.rst_ni ( rst ),
.testmode_i ( 1'b0 ),
.in ( axi ),
.out ( axi_lite )
);
typedef axi_test::axi_lite_driver #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)) axi_lite_drv_t;
typedef axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TA), .TT(TT)) axi_drv_t;
axi_lite_drv_t axi_lite_drv = new(axi_lite_dv);
axi_drv_t axi_drv = new(axi_dv);
initial begin
#tCK;
rst <= 0;
#tCK;
rst <= 1;
#tCK;
while (!done) begin
clk <= 1;
#(tCK/2);
clk <= 0;
#(tCK/2);
end
end
initial begin
automatic axi_drv_t::ax_beat_t ax = new;
automatic axi_drv_t::w_beat_t w = new;
automatic axi_drv_t::b_beat_t b = new;
automatic axi_drv_t::r_beat_t r = new;
axi_drv.reset_master();
@(posedge clk);
ax.randomize();
w.randomize();
w.last = 1'b1;
axi_drv.send_aw(ax);
axi_drv.send_w(w);
axi_drv.recv_b(b);
ax.randomize();
axi_drv.send_ar(ax);
axi_drv.recv_r(r);
repeat (4) @(posedge clk);
done = 1;
end
initial begin
automatic logic [AW-1:0] addr;
automatic logic [DW-1:0] data;
automatic logic [DW/8-1:0] strb;
axi_lite_drv.reset_slave();
@(posedge clk);
axi_lite_drv.recv_aw(addr);
axi_lite_drv.recv_w(data, strb);
axi_lite_drv.send_b(axi_pkg::RESP_OKAY);
axi_lite_drv.recv_ar(addr);
axi_lite_drv.send_r('0, axi_pkg::RESP_OKAY);
end
endmodule |
module tb_axi_atop_filter #(
// AXI Parameters
parameter int unsigned AXI_ADDR_WIDTH = 32,
parameter int unsigned AXI_DATA_WIDTH = 64,
parameter int unsigned AXI_ID_WIDTH = 4,
parameter int unsigned AXI_USER_WIDTH = 2,
parameter int unsigned AXI_MAX_READ_TXNS = 10,
parameter int unsigned AXI_MAX_WRITE_TXNS = 12,
// TB Parameters
parameter time TCLK = 10ns,
parameter time TA = TCLK * 1/4,
parameter time TT = TCLK * 3/4,
parameter int unsigned REQ_MIN_WAIT_CYCLES = 0,
parameter int unsigned REQ_MAX_WAIT_CYCLES = 10,
parameter int unsigned RESP_MIN_WAIT_CYCLES = 0,
parameter int unsigned RESP_MAX_WAIT_CYCLES = REQ_MAX_WAIT_CYCLES/2,
parameter int unsigned N_TXNS = 10000
);
timeunit 1ns;
timeprecision 10ps;
localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
localparam int unsigned NUM_AXI_IDS = 2**AXI_ID_WIDTH;
logic clk,
rst_n;
clk_rst_gen #(
.CLK_PERIOD (TCLK),
.RST_CLK_CYCLES (5)
) i_clk_rst_gen (
.clk_o (clk),
.rst_no (rst_n)
);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) upstream_dv (
.clk_i (clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) upstream ();
`AXI_ASSIGN(upstream, upstream_dv);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) downstream_dv (
.clk_i (clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) downstream ();
`AXI_ASSIGN(downstream_dv, downstream);
axi_atop_filter #(
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS)
) dut (
.clk_i (clk),
.rst_ni (rst_n),
.slv (upstream),
.mst (downstream)
);
typedef axi_test::axi_driver #(
.AW (AXI_ADDR_WIDTH),
.DW (AXI_DATA_WIDTH),
.IW (AXI_ID_WIDTH),
.UW (AXI_USER_WIDTH),
.TA (TA),
.TT (TT)
) axi_driver_t;
typedef rand_id_queue #(
.data_t (axi_driver_t::ax_beat_t),
.ID_WIDTH (AXI_ID_WIDTH)
) rand_ax_beat_queue;
typedef logic [AXI_ADDR_WIDTH-1:0] axi_addr_t;
typedef logic [AXI_ID_WIDTH-1:0] axi_id_t;
localparam axi_addr_t PFN_MASK = '{11: 1'b0, 10: 1'b0, 9: 1'b0, 8: 1'b0, 7: 1'b0, 6: 1'b0,
5: 1'b0, 4: 1'b0, 3: 1'b0, 2: 1'b0, 1: 1'b0, 0: 1'b0, default: '1};
task rand_req_wait();
rand_wait(REQ_MIN_WAIT_CYCLES, REQ_MAX_WAIT_CYCLES, clk);
endtask
task rand_resp_wait();
rand_wait(RESP_MIN_WAIT_CYCLES, RESP_MAX_WAIT_CYCLES, clk);
endtask
function axi_driver_t::ax_beat_t new_rand_burst();
automatic int unsigned rand_success = 0;
automatic axi_driver_t::ax_beat_t ax_beat = new;
automatic axi_addr_t addr;
automatic axi_pkg::burst_t burst;
automatic axi_pkg::size_t size;
// Randomly pick FIXED or INCR burst. WRAP is currently not supported.
rand_success = std::randomize(burst) with {
burst <= axi_pkg::BURST_INCR;
}; assert(rand_success);
ax_beat.ax_burst = burst;
// Randomize burst length.
ax_beat.ax_len = $random();
// Randomize beat size.
rand_success = std::randomize(size) with {
2**size <= AXI_STRB_WIDTH;
}; assert(rand_success);
ax_beat.ax_size = size;
// Randomize address. Make sure that the burst does not cross a 4KiB boundary.
if (ax_beat.ax_burst == BURST_FIXED) begin
forever begin
rand_success = std::randomize(addr); assert(rand_success);
if (((addr + 2**ax_beat.ax_size) & PFN_MASK) == (addr & PFN_MASK))
break;
end
ax_beat.ax_addr = addr;
end else begin // BURST_INCR
forever begin
rand_success = std::randomize(addr); assert(rand_success);
if (((addr + 2**ax_beat.ax_size * (ax_beat.ax_len + 1)) & PFN_MASK) == (addr & PFN_MASK))
break;
end
ax_beat.ax_addr = addr;
end
return ax_beat;
endfunction
// AXI Master
logic mst_done = 1'b0;
axi_driver_t axi_master = new(upstream_dv);
// TODO: Is it possible to move such a master driver as class to `axi_test`?
initial begin
static axi_driver_t::ax_beat_t aw_queue[$];
static int unsigned atop_flight_cnt[NUM_AXI_IDS-1:0],
r_flight_cnt[NUM_AXI_IDS-1:0],
w_flight_cnt[NUM_AXI_IDS-1:0],
tot_atop_flight_cnt = 0,
tot_r_flight_cnt = 0,
tot_w_flight_cnt = 0;
static logic ar_done = 1'b0,
aw_done = 1'b0;
static semaphore cnt_sem = new(1);
axi_master.reset_master();
for (int unsigned i = 0; i < NUM_AXI_IDS; i++) begin
atop_flight_cnt[i] = 0;
r_flight_cnt[i] = 0;
w_flight_cnt[i] = 0;
end
wait (rst_n);
fork
// AR
begin
repeat (N_TXNS) begin
automatic axi_driver_t::ax_beat_t ar_beat = new_rand_burst();
static int unsigned rand_success;
automatic axi_id_t id;
while (tot_r_flight_cnt >= AXI_MAX_READ_TXNS) begin
@(posedge clk);
end
// The ID must not be the same as that of any in-flight ATOP.
cnt_sem.get();
do begin
rand_success = std::randomize(id); assert(rand_success);
end while (atop_flight_cnt[id] != 0);
ar_beat.ax_id = id;
r_flight_cnt[ar_beat.ax_id]++;
tot_r_flight_cnt++;
cnt_sem.put();
rand_req_wait();
axi_master.send_ar(ar_beat);
end
ar_done = 1'b1;
end
// R
while (!(ar_done && tot_r_flight_cnt == 0 && aw_done && tot_atop_flight_cnt == 0)) begin
automatic axi_driver_t::r_beat_t r_beat;
rand_resp_wait();
axi_master.recv_r(r_beat);
if (r_beat.r_last) begin
cnt_sem.get();
if (r_beat.r_resp == RESP_OKAY) begin
r_flight_cnt[r_beat.r_id]--;
tot_r_flight_cnt--;
end
cnt_sem.put();
end
end
// AW
begin
repeat (N_TXNS) begin
automatic axi_driver_t::ax_beat_t aw_beat = new_rand_burst();
static int unsigned rand_success = 0;
automatic axi_id_t id;
while (tot_w_flight_cnt >= AXI_MAX_WRITE_TXNS
|| tot_atop_flight_cnt >= AXI_MAX_WRITE_TXNS) begin
@(posedge clk);
end
aw_beat.ax_atop[5:4] = $random();
if (aw_beat.ax_atop[5:4] != 2'b00) begin // ATOP
// Determine `ax_atop`.
if (aw_beat.ax_atop[5:4] == ATOP_ATOMICSTORE ||
aw_beat.ax_atop[5:4] == ATOP_ATOMICLOAD) begin
// Endianness
aw_beat.ax_atop[3] = $random();
// Atomic operation
aw_beat.ax_atop[2:0] = $random();
end else begin // Atomic{Swap,Compare}
aw_beat.ax_atop[3:1] = '0;
aw_beat.ax_atop[0] = $random();
end
// Determine `ax_size` and `ax_len`.
if (2**aw_beat.ax_size < AXI_STRB_WIDTH) begin
// Transaction does *not* occupy full data bus, so we must send just one beat. [E2.1.3]
aw_beat.ax_len = '0;
end else begin
automatic int unsigned bytes;
if (aw_beat.ax_atop == ATOP_ATOMICCMP) begin
// Total data transferred in burst can be 2, 4, 8, 16, or 32 B.
automatic int unsigned log_bytes;
rand_success = std::randomize(log_bytes) with {
log_bytes > 0; 2**log_bytes >= AXI_STRB_WIDTH; 2**log_bytes <= 32;
}; assert(rand_success);
bytes = 2**log_bytes;
end else begin
// Total data transferred in burst can be 1, 2, 4, or 8 B.
if (AXI_STRB_WIDTH >= 8) begin
bytes = AXI_STRB_WIDTH;
end else begin
automatic int unsigned log_bytes;
rand_success = std::randomize(log_bytes); assert(rand_success);
log_bytes = log_bytes % (4 - $clog2(AXI_STRB_WIDTH)) - $clog2(AXI_STRB_WIDTH);
bytes = 2**log_bytes;
end
end
aw_beat.ax_len = bytes / AXI_STRB_WIDTH - 1;
end
// Determine `ax_addr`.
if (aw_beat.ax_atop == ATOP_ATOMICCMP) begin
// The address must be aligned to half the outbound data size. [E2-337]
aw_beat.ax_addr = aw_beat.ax_addr & ~(1<<aw_beat.ax_size - 1);
end else begin
// The address must be aligned to the data size. [E2-337]
aw_beat.ax_addr = aw_beat.ax_addr & ~(1<<(aw_beat.ax_size+1) - 1);
end
// Determine `ax_burst`.
if (aw_beat.ax_atop == ATOP_ATOMICCMP) begin
// If the address is aligned to the total size of outgoing data, the burst type must be
// INCR. Otherwise, it must be WRAP. [E2-338]
aw_beat.ax_burst = (aw_beat.ax_addr % ((aw_beat.ax_len+1) * 2**aw_beat.ax_size) == 0) ?
BURST_INCR : BURST_WRAP;
end else begin
// Only INCR allowed.
aw_beat.ax_burst = BURST_INCR;
end
// Determine `ax_id`, which must not be the same as that of any other in-flight AXI
// transaction.
cnt_sem.get();
do begin
rand_success = std::randomize(id); assert(rand_success);
end while (atop_flight_cnt[id] != 0 || r_flight_cnt[id] != 0 || w_flight_cnt[id] != 0);
end else begin
// Determine `ax_id`, which must not be the same as that of any in-flight ATOP.
cnt_sem.get();
do begin
rand_success = std::randomize(id); assert(rand_success);
end while (atop_flight_cnt[id] != 0);
end
aw_beat.ax_id = id;
// Add AW to queue and put it in flight.
aw_queue.push_back(aw_beat);
if (aw_beat.ax_atop == '0) begin
w_flight_cnt[aw_beat.ax_id]++;
tot_w_flight_cnt++;
end else begin
atop_flight_cnt[aw_beat.ax_id]++;
tot_atop_flight_cnt++;
end
cnt_sem.put();
rand_req_wait();
axi_master.send_aw(aw_beat);
end
aw_done = 1'b1;
end
// W
while (!(aw_done && aw_queue.size() == 0)) begin
automatic axi_driver_t::ax_beat_t aw_beat;
automatic axi_addr_t addr;
static int unsigned rand_success = 0;
wait (aw_queue.size() > 0);
aw_beat = aw_queue.pop_front();
addr = aw_beat.ax_addr;
for (int unsigned i = 0; i < aw_beat.ax_len + 1; i++) begin
automatic axi_driver_t::w_beat_t w_beat = new;
int unsigned begin_byte, n_bytes;
logic [AXI_STRB_WIDTH-1:0] rand_strb, strb_mask;
rand_success = std::randomize(w_beat); assert (rand_success);
// Determine strobe.
w_beat.w_strb = '0;
n_bytes = 2**aw_beat.ax_size;
begin_byte = addr % AXI_STRB_WIDTH;
strb_mask = ((1'b1 << n_bytes) - 1) << begin_byte;
rand_strb = $random();
w_beat.w_strb |= (rand_strb & strb_mask);
// Determine last.
w_beat.w_last = (i == aw_beat.ax_len);
rand_req_wait();
axi_master.send_w(w_beat);
if (aw_beat.ax_burst == BURST_INCR)
addr += n_bytes;
end
end
// B
while (!(aw_done && tot_atop_flight_cnt == 0 && tot_w_flight_cnt == 0)) begin
automatic axi_driver_t::b_beat_t b_beat;
rand_resp_wait();
axi_master.recv_b(b_beat);
cnt_sem.get();
if (b_beat.b_resp == RESP_SLVERR) begin
atop_flight_cnt[b_beat.b_id]--;
tot_atop_flight_cnt--;
end else begin
w_flight_cnt[b_beat.b_id]--;
tot_w_flight_cnt--;
end
cnt_sem.put();
end
join
mst_done = 1'b1;
end
initial begin
wait (mst_done);
$finish();
end
// AXI Slave
axi_driver_t axi_slave = new(downstream_dv);
// TODO: Is it possible to move such a slave driver as class to `axi_test`?
initial begin
static rand_ax_beat_queue ar_queue = new;
static axi_driver_t::ax_beat_t aw_queue[$];
static rand_ax_beat_queue b_queue = new;
axi_slave.reset_slave();
wait (rst_n);
fork
// AR
forever begin
automatic axi_driver_t::ax_beat_t ar_beat;
rand_resp_wait();
axi_slave.recv_ar(ar_beat);
ar_queue.push(ar_beat.ax_id, ar_beat);
end
// R
forever begin
automatic axi_driver_t::ax_beat_t ar_beat;
automatic axi_driver_t::r_beat_t r_beat = new;
wait (!ar_queue.empty());
ar_beat = ar_queue.peek();
void'(std::randomize(r_beat));
r_beat.r_id = ar_beat.ax_id;
rand_resp_wait();
if (ar_beat.ax_len == '0) begin
r_beat.r_last = 1'b1;
void'(ar_queue.pop_id(ar_beat.ax_id));
end else begin
ar_beat.ax_len--;
ar_queue.set(ar_beat.ax_id, ar_beat);
end
axi_slave.send_r(r_beat);
end
// AW
forever begin
automatic axi_driver_t::ax_beat_t aw_beat;
rand_resp_wait();
axi_slave.recv_aw(aw_beat);
aw_queue.push_back(aw_beat);
end
// W
forever begin
automatic axi_driver_t::ax_beat_t aw_beat;
forever begin
automatic axi_driver_t::w_beat_t w_beat;
rand_resp_wait();
axi_slave.recv_w(w_beat);
if (w_beat.w_last)
break;
end
wait (aw_queue.size() > 0);
aw_beat = aw_queue.pop_front();
b_queue.push(aw_beat.ax_id, aw_beat);
end
// B
forever begin
automatic axi_driver_t::ax_beat_t aw_beat;
automatic axi_driver_t::b_beat_t b_beat = new;
wait (!b_queue.empty());
aw_beat = b_queue.pop();
void'(std::randomize(b_beat));
b_beat.b_id = aw_beat.ax_id;
rand_resp_wait();
axi_slave.send_b(b_beat);
end
join
end
typedef struct packed {
axi_id_t id;
logic thru;
} w_cmd_t;
// Monitor and check responses of filter.
initial begin
static axi_driver_t::ax_beat_t ar_xfer_queue[$],
aw_xfer_queue[$];
static axi_driver_t::b_beat_t b_inject_queue[$],
b_xfer_queue[$];
static axi_driver_t::r_beat_t r_inject_queue[$],
r_xfer_queue[$];
static w_cmd_t w_cmd_queue[$];
static axi_driver_t::w_beat_t w_xfer_queue[$];
forever begin
@(posedge clk);
#(TT);
// Ensure that downstream never sees an `aw_atop`.
if (downstream.aw_valid) begin
assert (downstream.aw_atop == '0);
end
// Push upstream ARs into transfer queues.
if (upstream.ar_valid && upstream.ar_ready) begin
automatic axi_driver_t::ax_beat_t ar_beat = new;
ar_beat.ax_id = upstream.ar_id;
ar_beat.ax_addr = upstream.ar_addr;
ar_beat.ax_len = upstream.ar_len;
ar_beat.ax_size = upstream.ar_size;
ar_beat.ax_burst = upstream.ar_burst;
ar_beat.ax_lock = upstream.ar_lock;
ar_beat.ax_cache = upstream.ar_cache;
ar_beat.ax_prot = upstream.ar_prot;
ar_beat.ax_qos = upstream.ar_qos;
ar_beat.ax_region = upstream.ar_region;
ar_beat.ax_user = upstream.ar_user;
ar_xfer_queue.push_back(ar_beat);
end
// Push upstream AWs that must go through into transfer queues, and push to W command queue.
if (upstream.aw_valid && upstream.aw_ready) begin
automatic axi_driver_t::ax_beat_t aw_beat = new;
automatic w_cmd_t w_cmd;
aw_beat.ax_id = upstream.aw_id;
aw_beat.ax_addr = upstream.aw_addr;
aw_beat.ax_len = upstream.aw_len;
aw_beat.ax_size = upstream.aw_size;
aw_beat.ax_burst = upstream.aw_burst;
aw_beat.ax_lock = upstream.aw_lock;
aw_beat.ax_cache = upstream.aw_cache;
aw_beat.ax_prot = upstream.aw_prot;
aw_beat.ax_qos = upstream.aw_qos;
aw_beat.ax_region = upstream.aw_region;
aw_beat.ax_atop = upstream.aw_atop;
aw_beat.ax_user = upstream.aw_user;
w_cmd.id = aw_beat.ax_id;
w_cmd.thru = (aw_beat.ax_atop == '0);
w_cmd_queue.push_back(w_cmd);
if (w_cmd.thru) begin
aw_xfer_queue.push_back(aw_beat);
end else if (aw_beat.ax_atop[5:4] != ATOP_ATOMICSTORE) begin
for (int unsigned i = 0; i < aw_beat.ax_len + 1; i++) begin
automatic axi_driver_t::r_beat_t r_beat = new;
r_beat.r_id = aw_beat.ax_id;
r_beat.r_resp = RESP_SLVERR;
r_beat.r_data = '0;
r_beat.r_user = '0;
r_beat.r_last = (i == aw_beat.ax_len);
r_inject_queue.push_back(r_beat);
end
end
end
// Push upstream Ws that must go through into transfer queue; push to B and R inject queue for
// completed W bursts that must not go through.
if (upstream.w_valid && upstream.w_ready) begin
automatic axi_driver_t::w_beat_t w_beat = new;
automatic w_cmd_t w_cmd;
w_beat.w_data = upstream.w_data;
w_beat.w_strb = upstream.w_strb;
w_beat.w_last = upstream.w_last;
w_beat.w_user = upstream.w_user;
assert (w_cmd_queue.size() > 0) else $fatal("upstream.W: Undecided beat!");
w_cmd = w_cmd_queue[0];
if (w_cmd.thru) begin
w_xfer_queue.push_back(w_beat);
end
if (w_beat.w_last) begin
if (!w_cmd.thru) begin
automatic axi_driver_t::b_beat_t b_beat = new;
b_beat.b_id = w_cmd.id;
b_beat.b_resp = RESP_SLVERR;
b_inject_queue.push_back(b_beat);
end
void'(w_cmd_queue.pop_front());
end
end
// Push downstream Rs into transfer queue.
if (downstream.r_valid && downstream.r_ready) begin
automatic axi_driver_t::r_beat_t r_beat = new;
r_beat.r_id = downstream.r_id;
r_beat.r_data = downstream.r_data;
r_beat.r_resp = downstream.r_resp;
r_beat.r_last = downstream.r_last;
r_beat.r_user = downstream.r_user;
r_xfer_queue.push_back(r_beat);
end
// Push downstream Bs into transfer queue.
if (downstream.b_valid && downstream.b_ready) begin
automatic axi_driver_t::b_beat_t b_beat = new;
b_beat.b_id = downstream.b_id;
b_beat.b_resp = downstream.b_resp;
b_beat.b_user = downstream.b_user;
b_xfer_queue.push_back(b_beat);
end
// Ensure downstream ARs match beats from transfer queue.
if (downstream.ar_valid && downstream.ar_ready) begin
automatic axi_driver_t::ax_beat_t exp_beat;
assert (ar_xfer_queue.size() > 0) else $fatal(1, "downstream.AR: Unknown beat!");
exp_beat = ar_xfer_queue.pop_front();
assert (downstream.ar_id == exp_beat.ax_id);
assert (downstream.ar_addr == exp_beat.ax_addr);
assert (downstream.ar_len == exp_beat.ax_len);
assert (downstream.ar_size == exp_beat.ax_size);
assert (downstream.ar_burst == exp_beat.ax_burst);
assert (downstream.ar_cache == exp_beat.ax_cache);
assert (downstream.ar_prot == exp_beat.ax_prot);
assert (downstream.ar_qos == exp_beat.ax_qos);
assert (downstream.ar_region == exp_beat.ax_region);
assert (downstream.ar_user == exp_beat.ax_user);
end
// Ensure downstream AWs match beats from transfer queue.
if (downstream.aw_valid && downstream.aw_ready) begin
automatic axi_driver_t::ax_beat_t exp_beat;
assert (aw_xfer_queue.size() > 0) else $fatal(1, "downstream.AW: Unknown beat!");
exp_beat = aw_xfer_queue.pop_front();
assert (downstream.aw_id == exp_beat.ax_id);
assert (downstream.aw_addr == exp_beat.ax_addr);
assert (downstream.aw_len == exp_beat.ax_len);
assert (downstream.aw_size == exp_beat.ax_size);
assert (downstream.aw_burst == exp_beat.ax_burst);
assert (downstream.aw_cache == exp_beat.ax_cache);
assert (downstream.aw_prot == exp_beat.ax_prot);
assert (downstream.aw_qos == exp_beat.ax_qos);
assert (downstream.aw_region == exp_beat.ax_region);
assert (downstream.aw_user == exp_beat.ax_user);
end
// Ensure downstream Ws match beats from transfer queue.
if (downstream.w_valid && downstream.w_ready) begin
automatic axi_driver_t::w_beat_t exp_beat;
assert (w_xfer_queue.size() > 0) else $fatal(1, "downstream.W: Unknown beat!");
exp_beat = w_xfer_queue.pop_front();
assert (downstream.w_data == exp_beat.w_data);
assert (downstream.w_strb == exp_beat.w_strb);
assert (downstream.w_last == exp_beat.w_last);
assert (downstream.w_user == exp_beat.w_user);
end
// Ensure upstream Rs match beats from transfer or inject queue.
if (upstream.r_valid && upstream.r_ready) begin
automatic axi_driver_t::r_beat_t exp_beat;
if (r_inject_queue.size() > 0 && r_inject_queue[0].r_id == upstream.r_id) begin
exp_beat = r_inject_queue.pop_front();
end else if (r_xfer_queue.size() > 0 && r_xfer_queue[0].r_id == upstream.r_id) begin
exp_beat = r_xfer_queue.pop_front();
end else begin
$fatal(1, "upstream.R: Unknown beat!");
end
assert (upstream.r_id == exp_beat.r_id);
assert (upstream.r_data == exp_beat.r_data);
assert (upstream.r_resp == exp_beat.r_resp);
assert (upstream.r_last == exp_beat.r_last);
assert (upstream.r_user == exp_beat.r_user);
end
// Ensure upstream Bs match beats from transfer or inject queue.
if (upstream.b_valid && upstream.b_ready) begin
automatic axi_driver_t::b_beat_t exp_beat;
if (b_inject_queue.size() > 0 && b_inject_queue[0].b_id == upstream.b_id) begin
exp_beat = b_inject_queue.pop_front();
end else if (b_xfer_queue.size() > 0 && b_xfer_queue[0].b_id == upstream.b_id) begin
exp_beat = b_xfer_queue.pop_front();
end else begin
$fatal(1, "upstream.B: Unknown beat!");
end
assert (upstream.b_id == exp_beat.b_id);
assert (upstream.b_resp == exp_beat.b_resp);
assert (upstream.b_user == exp_beat.b_user);
end
end
end
endmodule |
module tb_axi_lite_to_axi;
parameter AW = 32;
parameter DW = 32;
parameter IW = 8;
parameter UW = 8;
localparam tCK = 1ns;
logic clk = 0;
logic rst = 1;
logic done = 0;
AXI_LITE_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) axi_lite_dv(clk);
AXI_LITE #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) axi_lite();
`AXI_LITE_ASSIGN(axi_lite, axi_lite_dv);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi_dv(clk);
AXI_BUS #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi();
`AXI_ASSIGN(axi_dv, axi);
axi_lite_to_axi i_dut (
.in ( axi_lite ),
.out ( axi )
);
axi_test::axi_lite_driver #(.AW(AW), .DW(DW)) axi_lite_drv = new(axi_lite_dv);
axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW)) axi_drv = new(axi_dv);
initial begin
#tCK;
rst <= 0;
#tCK;
rst <= 1;
#tCK;
while (!done) begin
clk <= 1;
#(tCK/2);
clk <= 0;
#(tCK/2);
end
end
initial begin
automatic axi_pkg::resp_t resp;
axi_lite_drv.reset_master();
@(posedge clk);
axi_lite_drv.send_aw('hdeadbeef);
axi_lite_drv.send_w('hdeadbeef, '1);
axi_lite_drv.recv_b(resp);
$info("AXI-Lite B: resp %h", resp);
repeat (4) @(posedge clk);
done = 1;
end
initial begin
automatic axi_test::axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat;
automatic axi_test::axi_w_beat #(.DW(DW), .UW(UW)) w_beat;
automatic axi_test::axi_b_beat #(.IW(IW), .UW(UW)) b_beat = new;
axi_drv.reset_slave();
@(posedge clk);
axi_drv.recv_aw(ax_beat);
$info("AXI AW: addr %h", ax_beat.ax_addr);
axi_drv.recv_w(w_beat);
$info("AXI W: data %h, strb %h", w_beat.w_data, w_beat.w_strb);
axi_drv.send_b(b_beat);
end
endmodule |
module tb_axi_lite_xbar;
parameter AW = 32;
parameter DW = 32;
parameter IW = 8;
parameter UW = 8;
parameter NUM_MASTER = 2;
parameter NUM_SLAVE = 2;
parameter NUM_TRANSACTIONS = 1000;
localparam tCK = 1ns;
logic clk = 0;
logic rst = 1;
AXI_LITE_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) master_dv [0:NUM_MASTER-1](clk);
AXI_LITE #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) master [0:NUM_MASTER-1]();
for (genvar i = 0; i < NUM_MASTER; i++) begin: gen_conn_dv_masters
`AXI_LITE_ASSIGN(master[i], master_dv[i]);
end
AXI_LITE_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) slave_dv [0:NUM_SLAVE-1](clk);
AXI_LITE #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) slave [0:NUM_SLAVE-1]();
for (genvar i = 0; i < NUM_SLAVE; i++) begin: gen_conn_dv_slaves
`AXI_LITE_ASSIGN(slave_dv[i], slave[i]);
end
AXI_ROUTING_RULES #(
.AXI_ADDR_WIDTH(AW),
.NUM_SLAVE(NUM_SLAVE),
.NUM_RULES(1)
) routing();
localparam int SLAVE_SHIFT = (AW-$clog2(NUM_SLAVE));
for (genvar i = 0; i < NUM_SLAVE; i++) begin
logic [AW-1:0] addr = i;
assign routing.rules[i][0].enabled = 1;
assign routing.rules[i][0].mask = '1 << SLAVE_SHIFT;
assign routing.rules[i][0].base = addr << SLAVE_SHIFT;
end
axi_lite_xbar #(
.ADDR_WIDTH(AW),
.DATA_WIDTH(DW),
.NUM_MASTER(NUM_MASTER),
.NUM_SLAVE(NUM_SLAVE),
.NUM_RULES(1)
) i_dut (
.clk_i ( clk ),
.rst_ni ( rst ),
.master ( master ),
.slave ( slave ),
.rules ( routing )
);
// Define the transaction queues.
class transaction_t;
rand logic [AW-1:0] addr;
rand logic [DW-1:0] data;
rand logic [DW/8-1:0] strb;
axi_pkg::resp_t resp;
endclass
typedef axi_test::axi_lite_driver #(
.AW(AW),
.DW(DW),
.TA(0.2*tCK),
.TT(0.8*tCK)
) driver_t;
// Randomly block for a few clock cycles.
task random_delay;
automatic int i;
i = $urandom_range(0, 50);
if (i > 5) return;
repeat (i) @(posedge clk);
endtask
// Setup a queue for reads and writes for each slave.
transaction_t queue_rd [NUM_SLAVE][$];
transaction_t queue_wr [NUM_SLAVE][$];
mailbox mailbox_rd [NUM_SLAVE];
mailbox mailbox_wr [NUM_SLAVE];
int tests_total = 0;
int tests_failed = 0;
// Initialize the master driver processes.
logic [NUM_MASTER-1:0] master_done = '0;
assign done = &master_done;
for (genvar i = 0; i < NUM_MASTER; i++) initial begin : g_master
// Initialize and reset the driver.
static driver_t drv = new(master_dv[i]);
drv.reset_master();
repeat(2) @(posedge clk);
// Fork off multiple processes that will issue transactions on the read
// and write paths.
fork
for (int k = 0; k < NUM_TRANSACTIONS; k++) begin : t_read
static transaction_t t;
static logic [DW-1:0] data;
static axi_pkg::resp_t resp;
t = new();
do begin
automatic int rand_success = t.randomize();
assert(rand_success);
end while ((t.addr >> SLAVE_SHIFT) >= NUM_SLAVE);
t.resp = axi_pkg::RESP_OKAY;
random_delay();
drv.send_ar(t.addr);
// queue_rd[t.addr >> SLAVE_SHIFT].push_back(t);
mailbox_rd[t.addr >> SLAVE_SHIFT].put(t);
random_delay();
drv.recv_r(data, resp);
tests_total++;
if (t.data != data || t.resp != resp) begin
tests_failed++;
$info("MISMATCH: master [%0d] read, data exp=%h act=%h, resp exp=%h act=%h",
i, t.data, data, t.resp, resp
);
end
end
for (int k = 0; k < NUM_TRANSACTIONS; k++) begin : t_write
static transaction_t t;
static axi_pkg::resp_t resp;
t = new();
do begin
automatic int rand_success = t.randomize();
assert(rand_success);
end while ((t.addr >> SLAVE_SHIFT) >= NUM_SLAVE);
t.resp = axi_pkg::RESP_OKAY;
random_delay();
drv.send_aw(t.addr);
// queue_wr[t.addr >> SLAVE_SHIFT].push_back(t);
mailbox_wr[t.addr >> SLAVE_SHIFT].put(t);
random_delay();
drv.send_w(t.data, t.strb);
random_delay();
drv.recv_b(resp);
tests_total++;
if (t.resp != resp) begin
tests_failed++;
$info("MISMATCH: master [%0d] write, resp exp=%h act=%h",
i, t.resp, resp
);
end
end
join
repeat(2) @(posedge clk);
master_done[i] = 1;
end
// Initialize the slave driver processes.
for (genvar i = 0; i < NUM_SLAVE; i++) initial begin : g_slave
// Initialize and reset the driver.
static driver_t drv = new(slave_dv[i]);
drv.reset_slave();
mailbox_rd[i] = new();
mailbox_wr[i] = new();
@(posedge clk);
// Fork off mulitple processes that will respond to transactions on the read
// and write paths.
fork
while (!done) begin : t_read
static transaction_t t;
static logic [AW-1:0] addr;
random_delay();
drv.recv_ar(addr);
// t = queue_rd[i].pop_front();
mailbox_rd[i].get(t);
random_delay();
drv.send_r(t.data, t.resp);
tests_total++;
if (t.addr != addr) begin
tests_failed++;
$info("MISMATCH: slave [%0d] read, addr exp=%h act=%h",
i, t.addr, addr
);
end
end
while (!done) begin : t_write
static transaction_t t;
static logic [AW-1:0] addr;
static logic [DW-1:0] data;
static logic [DW/8-1:0] strb;
random_delay();
drv.recv_aw(addr);
// t = queue_wr[i].pop_front();
mailbox_wr[i].get(t);
random_delay();
drv.recv_w(data, strb);
random_delay();
drv.send_b(t.resp);
tests_total++;
if (t.addr != addr || t.data != data || t.strb != strb) begin
tests_failed++;
$info("MISMATCH: slave [%0d] write, addr exp=%h act=%h, data exp=%h act=%h, strb exp=%h act=%h",
i, t.addr, addr, t.data, data, t.strb, strb
);
end
end
join
end
// Clock and reset generator.
initial begin
static int cycle = 0;
#tCK;
rst <= 0;
#tCK;
rst <= 1;
#tCK;
while (!done) begin
clk <= 1;
#(tCK/2);
clk <= 0;
#(tCK/2);
if (cycle >= 1000000)
$fatal(1, "timeout at %t", $time);
cycle++;
end
if (tests_failed == 0)
$info("ALL %0d TESTS PASSED", tests_total);
else
$error("%0d / %0d TESTS FAILED", tests_failed, tests_total);
end
endmodule |
module pulp_clock_mux2
(
input logic clk0_i,
input logic clk1_i,
input logic clk_sel_i,
output logic clk_o
);
BUFGMUX bufgmux_i (
.S(clk_sel_i),
.I0(clk0_i),
.I1(clk1_i),
.O(clk_o)
);
endmodule |
module axi_response_block
#(
parameter AXI_ADDRESS_W = 32,
parameter AXI_DATA_W = 64,
parameter AXI_USER_W = 6,
parameter N_INIT_PORT = 4,
parameter N_TARG_PORT = 8,
parameter FIFO_DEPTH_DW = 8,
parameter AXI_ID_IN = 16,
parameter AXI_ID_OUT = AXI_ID_IN + $clog2(N_TARG_PORT),
parameter N_REGION = 2
)
(
input logic clk,
input logic rst_n,
input logic test_en_i,
//AXI BACKWARD read data bus ----------------------------------------------
input logic [N_INIT_PORT-1:0][AXI_ID_OUT-1:0] rid_i,
input logic [N_INIT_PORT-1:0][AXI_DATA_W-1:0] rdata_i,
input logic [N_INIT_PORT-1:0][ 1:0] rresp_i,
input logic [N_INIT_PORT-1:0] rlast_i, //last transfer in burst
input logic [N_INIT_PORT-1:0][AXI_USER_W-1:0] ruser_i, //last transfer in burst
input logic [N_INIT_PORT-1:0] rvalid_i, //slave data valid
output logic [N_INIT_PORT-1:0] rready_o, //master ready to accept
//AXI BACKWARD WRITE data bus ----------------------------------------------
input logic [N_INIT_PORT-1:0][AXI_ID_OUT-1:0] bid_i,
input logic [N_INIT_PORT-1:0][ 1:0] bresp_i,
input logic [N_INIT_PORT-1:0][AXI_USER_W-1:0] buser_i, //last transfer in burst
input logic [N_INIT_PORT-1:0] bvalid_i, //slave data valid
output logic [N_INIT_PORT-1:0] bready_o, //master ready to accept
//AXI BACKWARD read data bus ----------------------------------------------
output logic [AXI_ID_IN-1:0] rid_o,
output logic [AXI_DATA_W-1:0] rdata_o,
output logic [ 1:0] rresp_o,
output logic rlast_o, //last transfer in burst
output logic [AXI_USER_W-1:0] ruser_o,
output logic rvalid_o, //slave data valid
input logic rready_i, //master ready to accept
//AXI BACKWARD WRITE data bus ----------------------------------------------
output logic [AXI_ID_IN-1:0] bid_o,
output logic [ 1:0] bresp_o,
output logic [AXI_USER_W-1:0] buser_o, //last transfer in burst
output logic bvalid_o, //slave data valid
input logic bready_i, //master ready to accept
// ADDRESS READ DECODER
input logic arvalid_i,
input logic [AXI_ADDRESS_W-1:0] araddr_i,
output logic arready_o,
input logic [AXI_ID_IN-1:0] arid_i,
input logic [ 7:0] arlen_i,
input logic [ AXI_USER_W-1:0] aruser_i,
output logic [N_INIT_PORT-1:0] arvalid_o,
input logic [N_INIT_PORT-1:0] arready_i,
// ADDRESS WRITE DECODER
input logic awvalid_i,
input logic [AXI_ADDRESS_W-1:0] awaddr_i,
output logic awready_o,
input logic [AXI_ID_IN-1:0] awid_i,
input logic [AXI_USER_W-1:0] awuser_i,
output logic [N_INIT_PORT-1:0] awvalid_o,
input logic [N_INIT_PORT-1:0] awready_i,
// DATA WRITE DECODER
input logic wvalid_i,
input logic wlast_i,
output logic wready_o,
output logic [N_INIT_PORT-1:0] wvalid_o,
input logic [N_INIT_PORT-1:0] wready_i,
// FROM CFG REGS
input logic [N_REGION-1:0][N_INIT_PORT-1:0][AXI_ADDRESS_W-1:0] START_ADDR_i,
input logic [N_REGION-1:0][N_INIT_PORT-1:0][AXI_ADDRESS_W-1:0] END_ADDR_i,
input logic [N_REGION-1:0][N_INIT_PORT-1:0] enable_region_i,
input logic [N_INIT_PORT-1:0] connectivity_map_i
);
logic push_DEST_DW;
logic grant_FIFO_DEST_DW;
logic [N_INIT_PORT-1:0] DEST_DW;
logic incr_ar_req;
logic full_counter_ar;
logic outstanding_trans_ar;
logic error_ar_req;
logic error_ar_gnt;
logic incr_aw_req;
logic full_counter_aw;
logic outstanding_trans_aw;
logic handle_error_aw;
logic wdata_error_completed;
logic sample_awdata_info;
logic sample_ardata_info;
logic error_aw_req;
logic error_aw_gnt;
//logic [AXI_USER_W-1:0] error_aw_user;
//logic [AXI_ID_IN-1:0] error_aw_id;
axi_BW_allocator
#(
.AXI_USER_W ( AXI_USER_W ),
.N_INIT_PORT ( N_INIT_PORT ),
.N_TARG_PORT ( N_TARG_PORT ),
.AXI_DATA_W ( AXI_DATA_W ),
.AXI_ID_IN ( AXI_ID_IN )
)
BW_ALLOC
(
.clk ( clk ),
.rst_n ( rst_n ),
//AXI BACKWARD read data bus ----------------------------------------------
.bid_i ( bid_i ),
.bresp_i ( bresp_i ),
.buser_i ( buser_i ), //last transfer in burst
.bvalid_i ( bvalid_i ), //slave data valid
.bready_o ( bready_o ), //master ready to accept
//AXI BACKWARD read data bus ----------------------------------------------
.bid_o ( bid_o ),
.bresp_o ( bresp_o ),
.buser_o ( buser_o ), //last transfer in burst
.bvalid_o ( bvalid_o ), //slave data valid
.bready_i ( bready_i ), //master ready to accept
.incr_req_i ( incr_aw_req ),
.full_counter_o ( full_counter_aw ),
.outstanding_trans_o ( outstanding_trans_aw ),
.sample_awdata_info_i ( sample_awdata_info ),
.error_req_i ( error_aw_req ),
.error_gnt_o ( error_aw_gnt ),
.error_user_i ( awuser_i ),
.error_id_i ( awid_i )
);
axi_BR_allocator
#(
.AXI_USER_W ( AXI_USER_W ),
.N_INIT_PORT ( N_INIT_PORT ),
.N_TARG_PORT ( N_TARG_PORT ),
.AXI_DATA_W ( AXI_DATA_W ),
.AXI_ID_IN ( AXI_ID_IN )
)
BR_ALLOC
(
.clk ( clk ),
.rst_n ( rst_n ),
//AXI BACKWARD read data bus ----------------------------------------------
.rid_i ( rid_i ),
.rdata_i ( rdata_i ),
.rresp_i ( rresp_i ),
.rlast_i ( rlast_i ),
.ruser_i ( ruser_i ), //last transfer in burst
.rvalid_i ( rvalid_i ), //slave data valid
.rready_o ( rready_o ), //master ready to accept
//AXI BACKWARD read data bus ----------------------------------------------
.rid_o ( rid_o ),
.rdata_o ( rdata_o ),
.rresp_o ( rresp_o ),
.rlast_o ( rlast_o ),
.ruser_o ( ruser_o ), //last transfer in burst
.rvalid_o ( rvalid_o ), //slave data valid
.rready_i ( rready_i ), //master ready to accept
.incr_req_i ( incr_ar_req ),
.full_counter_o ( full_counter_ar ),
.outstanding_trans_o ( outstanding_trans_ar ),
.error_req_i ( error_ar_req ),
.error_gnt_o ( error_ar_gnt ),
.error_len_i ( arlen_i ),
.error_user_i ( aruser_i ),
.error_id_i ( arid_i ),
.sample_ardata_info_i ( sample_ardata_info )
);
axi_address_decoder_AR
#(
.ADDR_WIDTH ( AXI_ADDRESS_W ),
.N_INIT_PORT ( N_INIT_PORT ),
.N_REGION ( N_REGION )
)
AR_ADDR_DEC
(
.clk ( clk ),
.rst_n ( rst_n ),
.arvalid_i ( arvalid_i ),
.araddr_i ( araddr_i ),
.arready_o ( arready_o ),
.arvalid_o ( arvalid_o ), // REQUEST VECTOR (one for each INIT --> OH encoding)
.arready_i ( arready_i ), // Grant VECTOR (one for each INIT --> OH encoding)
.START_ADDR_i ( START_ADDR_i ),
.END_ADDR_i ( END_ADDR_i ),
.enable_region_i ( enable_region_i ),
.connectivity_map_i ( connectivity_map_i ),
.incr_req_o ( incr_ar_req ),
.full_counter_i ( full_counter_ar ),
.outstanding_trans_i ( outstanding_trans_ar ),
.error_req_o ( error_ar_req ),
.error_gnt_i ( error_ar_gnt ),
.sample_ardata_info_o ( sample_ardata_info )
);
axi_address_decoder_AW
#(
.ADDR_WIDTH ( AXI_ADDRESS_W ),
.N_INIT_PORT ( N_INIT_PORT ),
.N_REGION ( N_REGION )
)
AW_ADDR_DEC
(
.clk ( clk ),
.rst_n ( rst_n ),
.awvalid_i ( awvalid_i ),
.awaddr_i ( awaddr_i ),
.awready_o ( awready_o ),
.awvalid_o ( awvalid_o ), // REQUEST VECTOR (one for each INIT --> OH encoding)
.awready_i ( awready_i ), // Grant VECTOR (one for each INIT --> OH encoding)
.grant_FIFO_DEST_i ( grant_FIFO_DEST_DW ),
.DEST_o ( DEST_DW ),
.push_DEST_o ( push_DEST_DW ),
.START_ADDR_i ( START_ADDR_i ),
.END_ADDR_i ( END_ADDR_i ),
.enable_region_i ( enable_region_i ),
.connectivity_map_i ( connectivity_map_i ),
.incr_req_o ( incr_aw_req ),
.full_counter_i ( full_counter_aw ),
.outstanding_trans_i ( outstanding_trans_aw ),
.error_req_o ( error_aw_req ),
.error_gnt_i ( error_aw_gnt ),
.handle_error_o ( handle_error_aw ),
.wdata_error_completed_i ( wdata_error_completed ),
.sample_awdata_info_o ( sample_awdata_info )
);
axi_address_decoder_DW
#(
.N_INIT_PORT ( N_INIT_PORT ),
.FIFO_DEPTH ( FIFO_DEPTH_DW )
)
DW_ADDR_DEC
(
.clk ( clk ),
.rst_n ( rst_n ),
.test_en_i ( test_en_i ),
.wvalid_i ( wvalid_i ),
.wlast_i ( wlast_i ),
.wready_o ( wready_o ),
.wvalid_o ( wvalid_o ),
.wready_i ( wready_i ),
.grant_FIFO_DEST_o ( grant_FIFO_DEST_DW ),
.DEST_i ( DEST_DW ),
.push_DEST_i ( push_DEST_DW ),
.handle_error_i ( handle_error_aw ),
.wdata_error_completed_o ( wdata_error_completed )
);
endmodule |
module axi_request_block
#(
parameter AXI_ADDRESS_W = 32,
parameter AXI_DATA_W = 64,
parameter AXI_NUMBYTES = AXI_DATA_W/8,
parameter AXI_USER_W = 6,
parameter N_INIT_PORT = 5,
parameter N_TARG_PORT = 8,
parameter FIFO_DW_DEPTH = 8,
parameter AXI_ID_IN = 16,
parameter LOG_N_TARG = $clog2(N_TARG_PORT),
parameter AXI_ID_OUT = AXI_ID_IN + LOG_N_TARG
)
(
input logic clk,
input logic rst_n,
input logic test_en_i,
// -----------------------------------------------------------------------------------//
// INTERNAL (N_TARGET PORT ) //
// -----------------------------------------------------------------------------------//
//AXI write address bus --------------------------------------------------------------//
input logic [N_TARG_PORT-1:0][AXI_ID_IN-1:0] awid_i, //
input logic [N_TARG_PORT-1:0][AXI_ADDRESS_W-1:0] awaddr_i, //
input logic [N_TARG_PORT-1:0][ 7:0] awlen_i, //burst length is 1 + (0 - 15)
input logic [N_TARG_PORT-1:0][ 2:0] awsize_i, //size of each transfer in burst
input logic [N_TARG_PORT-1:0][ 1:0] awburst_i, //for bursts>1, accept only incr burst=01
input logic [N_TARG_PORT-1:0] awlock_i, //only normal access supported axs_awlock=00
input logic [N_TARG_PORT-1:0][ 3:0] awcache_i, //
input logic [N_TARG_PORT-1:0][ 2:0] awprot_i, //
input logic [N_TARG_PORT-1:0][ 3:0] awregion_i, //
input logic [N_TARG_PORT-1:0][ 5:0] awatop_i, //
input logic [N_TARG_PORT-1:0][ AXI_USER_W-1:0] awuser_i, //
input logic [N_TARG_PORT-1:0][ 3:0] awqos_i, //
input logic [N_TARG_PORT-1:0] awvalid_i, //master addr valid
output logic [N_TARG_PORT-1:0] awready_o, //slave ready to accept
// -----------------------------------------------------------------------------------//
//AXI write data bus -----------------------------------------------------------------//
input logic [N_TARG_PORT-1:0] [AXI_DATA_W-1:0] wdata_i,
input logic [N_TARG_PORT-1:0] [AXI_NUMBYTES-1:0] wstrb_i, //1 strobe per byte
input logic [N_TARG_PORT-1:0] wlast_i, //last transfer in burst
input logic [N_TARG_PORT-1:0] [AXI_USER_W-1:0] wuser_i,
input logic [N_TARG_PORT-1:0] wvalid_i, //master data valid
output logic [N_TARG_PORT-1:0] wready_o, //slave ready to accept
// -----------------------------------------------------------------------------------//
//AXI read address bus ---------------------------------------------------------------//
input logic [N_TARG_PORT-1:0][ AXI_ID_IN-1:0] arid_i,
input logic [N_TARG_PORT-1:0][ AXI_ADDRESS_W-1:0] araddr_i,
input logic [N_TARG_PORT-1:0][ 7:0] arlen_i, //burst length - 1 to 16
input logic [N_TARG_PORT-1:0][ 2:0] arsize_i, //size of each transfer in burst
input logic [N_TARG_PORT-1:0][ 1:0] arburst_i, //for bursts>1, accept only incr burst=01
input logic [N_TARG_PORT-1:0] arlock_i, //only normal access supported axs_awlock=00
input logic [N_TARG_PORT-1:0][ 3:0] arcache_i,
input logic [N_TARG_PORT-1:0][ 2:0] arprot_i,
input logic [N_TARG_PORT-1:0][ 3:0] arregion_i, //
input logic [N_TARG_PORT-1:0][ AXI_USER_W-1:0] aruser_i, //
input logic [N_TARG_PORT-1:0][ 3:0] arqos_i, //
input logic [N_TARG_PORT-1:0] arvalid_i, //master addr valid
output logic [N_TARG_PORT-1:0] arready_o, //slave ready to accept
// -----------------------------------------------------------------------------------//
// ------------------------------------------------------------------------------------//
// SLAVE SIDE (ONE PORT ONLY) //
// ------------------------------------------------------------------------------------//
//AXI BACKWARD write response bus -----------------------------------------------------//
input logic [AXI_ID_OUT-1:0] bid_i,
input logic bvalid_i,
output logic bready_o,
// To BW ALLOC --> FROM BW DECODER
output logic [N_TARG_PORT-1:0] bvalid_o,
input logic [N_TARG_PORT-1:0] bready_i,
//AXI BACKWARD read data bus ----------------------------------------------------------//
input logic [AXI_ID_OUT-1:0] rid_i,
input logic rvalid_i, //slave data valid
output logic rready_o, //master ready to accept
// To BR ALLOC --> FROM BW DECODER
output logic [N_TARG_PORT-1:0] rvalid_o,
input logic [N_TARG_PORT-1:0] rready_i,
//AXI write address bus --------------------------------------------------------------//
output logic [AXI_ID_OUT-1:0] awid_o, //
output logic [AXI_ADDRESS_W-1:0] awaddr_o, //
output logic [ 7:0] awlen_o, //burst length is 1 + (0 - 15)
output logic [ 2:0] awsize_o, //size of each transfer in burst
output logic [ 1:0] awburst_o, //for bursts>1, accept only incr burst=01
output logic awlock_o, //only normal access supported axs_awlock=00
output logic [ 3:0] awcache_o, //
output logic [ 2:0] awprot_o, //
output logic [ 3:0] awregion_o, //
output logic [ 5:0] awatop_o, //
output logic [ AXI_USER_W-1:0] awuser_o, //
output logic [ 3:0] awqos_o, //
output logic awvalid_o, //master addr valid
input logic awready_i, //slave ready to accept
// -----------------------------------------------------------------------------------//
//AXI write data bus -----------------------------------------------------------------//
output logic [AXI_DATA_W-1:0] wdata_o,
output logic [AXI_NUMBYTES-1:0] wstrb_o, //1 strobe per byte
output logic wlast_o, //last transfer in burst
output logic [AXI_USER_W-1:0] wuser_o,
output logic wvalid_o, //master data valid
input logic wready_i, //slave ready to accept
// -----------------------------------------------------------------------------------//
//AXI read address bus ---------------------------------------------------------------//
output logic [ AXI_ID_OUT-1:0] arid_o,
output logic [ AXI_ADDRESS_W-1:0] araddr_o,
output logic [ 7:0] arlen_o, //burst length - 1 to 16
output logic [ 2:0] arsize_o, //size of each transfer in burst
output logic [ 1:0] arburst_o, //for bursts>1, accept only incr burst=01
output logic arlock_o, //only normal access supported axs_awlock=00
output logic [ 3:0] arcache_o,
output logic [ 2:0] arprot_o,
output logic [ 3:0] arregion_o, //
output logic [ AXI_USER_W-1:0] aruser_o, //
output logic [ 3:0] arqos_o, //
output logic arvalid_o, //master addr valid
input logic arready_i //slave ready to accept
// -----------------------------------------------------------------------------------//
);
logic push_ID;
logic [LOG_N_TARG+N_TARG_PORT-1:0] ID;
logic grant_FIFO_ID;
axi_AR_allocator
#(
.AXI_ADDRESS_W ( AXI_ADDRESS_W ),
.AXI_USER_W ( AXI_USER_W ),
.N_TARG_PORT ( N_TARG_PORT ),
.AXI_ID_IN ( AXI_ID_IN )
)
AR_ALLOCATOR
(
.clk ( clk ),
.rst_n ( rst_n ),
//AXI Read address bus ----------------------------------------------------------------
.arid_i ( arid_i ), //
.araddr_i ( araddr_i ), //
.arlen_i ( arlen_i ), //burst length - 1 to 16
.arsize_i ( arsize_i ), //size of each transfer in burst
.arburst_i ( arburst_i ), //for bursts>1(), accept only incr burst=01
.arlock_i ( arlock_i ), //only normal access supported axs_arlock=00
.arcache_i ( arcache_i ), //
.arprot_i ( arprot_i ), //
.arregion_i( arregion_i ), //
.aruser_i ( aruser_i ), //
.arqos_i ( arqos_i ), //
.arvalid_i ( arvalid_i ), //master addr valid
.arready_o ( arready_o ), //slave ready to accept
//AXI Read address bus--> OUT----------------------------------------------------------------
.arid_o ( arid_o ),
.araddr_o ( araddr_o ),
.arlen_o ( arlen_o ), //burst length - 1 to 16
.arsize_o ( arsize_o ), //size of each transfer in burst
.arburst_o ( arburst_o ), //for bursts>1(), accept only incr burst=01
.arlock_o ( arlock_o ), //only normal access supported axs_arlock=00
.arcache_o ( arcache_o ),
.arprot_o ( arprot_o ),
.arregion_o( arregion_o), //
.aruser_o ( aruser_o ), //
.arqos_o ( arqos_o ), //
.arvalid_o ( arvalid_o ), //master addr valid
.arready_i ( arready_i ) //slave ready to accept
);
axi_AW_allocator
#(
.AXI_ADDRESS_W ( AXI_ADDRESS_W ),
.AXI_USER_W ( AXI_USER_W ),
.N_TARG_PORT ( N_TARG_PORT ),
.AXI_ID_IN ( AXI_ID_IN )
)
AW_ALLOCATOR
(
.clk ( clk ),
.rst_n ( rst_n ),
//AXI write address bus ----------------------------------------------------------------
.awid_i ( awid_i ), //
.awaddr_i ( awaddr_i ), //
.awlen_i ( awlen_i ), //burst length is 1 + (0 - 15)
.awsize_i ( awsize_i ), //size of each transfer in burst
.awburst_i ( awburst_i ), //for bursts>1, accept only incr burst=01
.awlock_i ( awlock_i ), //only normal access supported axs_awlock=00
.awcache_i ( awcache_i ), //
.awprot_i ( awprot_i ), //
.awregion_i ( awregion_i ), //
.awatop_i ( awatop_i ), //
.awuser_i ( awuser_i ), //
.awqos_i ( awqos_i ), //
.awvalid_i ( awvalid_i ), //master addr valid
.awready_o ( awready_o ), //slave ready to accept
//AXI write address bus--> OUT----------------------------------------------------------------
.awid_o ( awid_o ), // Append the Master ID on the MSB bit
.awaddr_o ( awaddr_o ), //
.awlen_o ( awlen_o ), //burst length is 1 + (0 - 15)
.awsize_o ( awsize_o ), //size of each transfer in burst
.awburst_o ( awburst_o ), //for bursts>1, accept only incr burst=01
.awlock_o ( awlock_o ), //only normal access supported axs_awlock=00
.awcache_o ( awcache_o ), //
.awprot_o ( awprot_o ), //
.awregion_o ( awregion_o ), //
.awatop_o ( awatop_o ), //
.awuser_o ( awuser_o ), //
.awqos_o ( awqos_o ), //
.awvalid_o ( awvalid_o ), //master addr valid
.awready_i ( awready_i ), //slave ready to accept
// PUSH Interface to DW allocator
.push_ID_o ( push_ID),
.ID_o ( ID ), // {BIN_ID( ), OH_ID};
.grant_FIFO_ID_i ( grant_FIFO_ID )
);
axi_DW_allocator
#(
.AXI_USER_W (AXI_USER_W),
.N_TARG_PORT (N_TARG_PORT),
.FIFO_DEPTH (FIFO_DW_DEPTH),
.AXI_DATA_W (AXI_DATA_W)
)
DW_ALLOC
(
.clk ( clk ),
.rst_n ( rst_n ),
.test_en_i ( test_en_i ),
//AXI write data bus --> Processor Side -----------------------------------------
.wdata_i ( wdata_i ),
.wstrb_i ( wstrb_i ), //1 strobe per byte
.wlast_i ( wlast_i ), //last transfer in burst
.wuser_i ( wuser_i ), // User sideband signal
.wvalid_i ( wvalid_i ), //master data valid
.wready_o ( wready_o ), //slave ready to accept
//AXI write data bus --> Slave Side -----------------------------------------
.wdata_o ( wdata_o ),
.wstrb_o ( wstrb_o ), //1 strobe per byte
.wlast_o ( wlast_o ), //last transfer in burst
.wuser_o ( wuser_o ), // User sideband signal
.wvalid_o ( wvalid_o ), //master data valid
.wready_i ( wready_i ), //slave ready to accept
// PUSH Interface to DW allocator
.push_ID_i ( push_ID ),
.ID_i ( ID ), // {BIN_ID( ), OH_ID};
.grant_FIFO_ID_o ( grant_FIFO_ID )
);
axi_address_decoder_BW
#(
.N_TARG_PORT (N_TARG_PORT ),
.AXI_ID_IN (AXI_ID_IN )
)
BW_DECODER
(
//AXI BACKWARD write response
.bid_i(bid_i),
.bvalid_i(bvalid_i),
.bready_o(bready_o),
// To BW ALLOC --> FROM BW DECODER
.bvalid_o(bvalid_o),
.bready_i(bready_i)
);
axi_address_decoder_BR
#(
.N_TARG_PORT (N_TARG_PORT ),
.AXI_ID_IN (AXI_ID_IN )
)
BR_DECODER
(
//AXI BACKWARD write response
.rid_i(rid_i),
.rvalid_i(rvalid_i),
.rready_o(rready_o),
// To BW ALLOC --> FROM BW DECODER
.rvalid_o(rvalid_o),
.rready_i(rready_i)
);
endmodule |
module eth_mac_1g_rgmii_fifo #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_ADDR_WIDTH = 12,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_ADDR_WIDTH = 12,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
)
(
input wire gtx_clk,
input wire gtx_clk90,
input wire gtx_rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire rx_clk,
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* RGMII interface
*/
input wire rgmii_rx_clk,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
output wire rgmii_tx_clk,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
output wire mac_gmii_tx_en,
/*
* Status
*/
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
output wire [1:0] speed,
output wire [31:0] rx_fcs_reg,
output wire [31:0] tx_fcs_reg,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire tx_clk;
wire tx_rst;
wire rx_rst;
// synchronize MAC status signals into logic clock domain
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1;
reg [1:0] rx_sync_reg_2;
reg [1:0] rx_sync_reg_3;
reg [1:0] rx_sync_reg_4;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_frame_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
wire [1:0] speed_int;
reg [1:0] speed_sync_reg_1;
reg [1:0] speed_sync_reg_2;
assign speed = speed_sync_reg_2;
always @(posedge logic_clk) begin
speed_sync_reg_1 <= speed_int;
speed_sync_reg_2 <= speed_sync_reg_1;
end
eth_mac_1g_rgmii #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.USE_CLK90(USE_CLK90),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_rgmii_inst (
.gtx_clk(gtx_clk),
.gtx_clk90(gtx_clk90),
.gtx_rst(gtx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(rgmii_rx_clk),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.rgmii_tx_clk(rgmii_tx_clk),
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.mac_gmii_tx_en(mac_gmii_tx_en),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.rx_fcs_reg(rx_fcs_reg),
.tx_fcs_reg(tx_fcs_reg),
.speed(speed_int),
.ifg_delay(ifg_delay)
);
endmodule |
module axis_gmii_rx
(
input wire clk,
input wire rst,
/*
* GMII input
*/
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
/*
* AXI output
*/
output wire [7:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Control
*/
input wire clk_enable,
input wire mii_select,
/*
* Status
*/
output wire error_bad_frame,
output wire error_bad_fcs,
/* debug */
output reg [31:0] fcs_reg
);
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_WAIT_LAST = 3'd2,
STATE_CRC = 3'd3;
reg [2:0] state_reg, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg mii_odd;
reg mii_locked;
reg [7:0] gmii_rxd_d0;
reg [7:0] gmii_rxd_d1;
reg [7:0] gmii_rxd_d2;
reg [7:0] gmii_rxd_d3;
reg [7:0] gmii_rxd_d4;
reg gmii_rx_dv_d0;
reg gmii_rx_dv_d1;
reg gmii_rx_dv_d2;
reg gmii_rx_dv_d3;
reg gmii_rx_dv_d4;
reg gmii_rx_er_d0;
reg gmii_rx_er_d1;
reg gmii_rx_er_d2;
reg gmii_rx_er_d3;
reg gmii_rx_er_d4;
reg [7:0] m_axis_tdata_reg, m_axis_tdata_next;
reg m_axis_tvalid_reg, m_axis_tvalid_next;
reg m_axis_tlast_reg, m_axis_tlast_next;
reg m_axis_tuser_reg, m_axis_tuser_next;
reg error_bad_frame_reg, error_bad_frame_next;
reg error_bad_fcs_reg, error_bad_fcs_next;
reg [31:0] fcs_next;
reg [31:0] crc_state;
reg [1:0] crc_cnt, crc_cnt_next;
wire [31:0] crc_next;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
assign error_bad_frame = error_bad_frame_reg;
assign error_bad_fcs = error_bad_fcs_reg;
rgmii_lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(gmii_rxd_d4),
.state_in(crc_state),
.data_out(),
.state_out(crc_next)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
m_axis_tdata_next = 8'd0;
m_axis_tvalid_next = 1'b0;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = 1'b0;
error_bad_frame_next = 1'b0;
error_bad_fcs_next = 1'b0;
fcs_next = fcs_reg;
crc_cnt_next = crc_cnt;
if (!clk_enable) begin
// clock disabled - hold state
state_next = state_reg;
end else if (mii_select && !mii_odd) begin
// MII even cycle - hold state
state_next = state_reg;
end else begin
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD) begin
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// read payload
update_crc = 1'b1;
m_axis_tdata_next = gmii_rxd_d4;
m_axis_tvalid_next = 1'b1;
if (gmii_rx_dv_d4 && gmii_rx_er_d4) begin
// error
m_axis_tlast_next = 1'b1;
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
fcs_next = 32'HDEADBEEF;
state_next = STATE_WAIT_LAST;
end else if (!gmii_rx_dv) begin
// end of packet
if (gmii_rx_er_d0 || gmii_rx_er_d1 || gmii_rx_er_d2 || gmii_rx_er_d3) begin
// error received in FCS bytes
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
end else if ({gmii_rxd_d0, gmii_rxd_d1, gmii_rxd_d2, gmii_rxd_d3} == ~crc_next) begin
// FCS good
m_axis_tuser_next = 1'b0;
end else begin
// FCS bad
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
error_bad_fcs_next = 1'b1;
end
crc_cnt_next = 2'b0;
state_next = STATE_CRC;
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_CRC: begin
// wait for CRC
update_crc = 1'b1;
m_axis_tdata_next = gmii_rxd_d4;
m_axis_tvalid_next = 1'b1;
crc_cnt_next = crc_cnt + 1;
if (&crc_cnt) begin
// end of packet + CRC bytes
fcs_next = crc_next;
m_axis_tlast_next = 1'b1;
state_next = STATE_IDLE;
end else begin
fcs_next = 32'b0;
state_next = STATE_CRC;
end
end
STATE_WAIT_LAST: begin
// wait for end of packet
if (~gmii_rx_dv) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end
default:;
endcase
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
m_axis_tvalid_reg <= 1'b0;
error_bad_frame_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
fcs_reg <= 32'hFFFFFFFF;
crc_state <= 32'hFFFFFFFF;
crc_cnt <= 2'b0;
mii_locked <= 1'b0;
mii_odd <= 1'b0;
gmii_rx_dv_d0 <= 1'b0;
gmii_rx_dv_d1 <= 1'b0;
gmii_rx_dv_d2 <= 1'b0;
gmii_rx_dv_d3 <= 1'b0;
gmii_rx_dv_d4 <= 1'b0;
end else begin
state_reg <= state_next;
m_axis_tvalid_reg <= m_axis_tvalid_next;
error_bad_frame_reg <= error_bad_frame_next;
error_bad_fcs_reg <= error_bad_fcs_next;
fcs_reg <= fcs_next;
crc_cnt <= crc_cnt_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next;
end
if (clk_enable) begin
if (mii_select) begin
mii_odd <= !mii_odd;
if (mii_locked) begin
mii_locked <= gmii_rx_dv;
end else if (gmii_rx_dv && {gmii_rxd[3:0], gmii_rxd_d0[7:4]} == ETH_SFD) begin
mii_locked <= 1'b1;
mii_odd <= 1'b1;
end
if (mii_odd) begin
gmii_rx_dv_d0 <= gmii_rx_dv & gmii_rx_dv_d0;
gmii_rx_dv_d1 <= gmii_rx_dv_d0 & gmii_rx_dv;
gmii_rx_dv_d2 <= gmii_rx_dv_d1 & gmii_rx_dv;
gmii_rx_dv_d3 <= gmii_rx_dv_d2 & gmii_rx_dv;
gmii_rx_dv_d4 <= gmii_rx_dv_d3 & gmii_rx_dv;
end else begin
gmii_rx_dv_d0 <= gmii_rx_dv;
end
end else begin
gmii_rx_dv_d0 <= gmii_rx_dv;
gmii_rx_dv_d1 <= gmii_rx_dv_d0 & gmii_rx_dv;
gmii_rx_dv_d2 <= gmii_rx_dv_d1 & gmii_rx_dv;
gmii_rx_dv_d3 <= gmii_rx_dv_d2 & gmii_rx_dv;
gmii_rx_dv_d4 <= gmii_rx_dv_d3 & gmii_rx_dv;
end
end
end
m_axis_tdata_reg <= m_axis_tdata_next;
m_axis_tlast_reg <= m_axis_tlast_next;
m_axis_tuser_reg <= m_axis_tuser_next;
// delay input
if (clk_enable) begin
if (mii_select) begin
gmii_rxd_d0 <= {gmii_rxd[3:0], gmii_rxd_d0[7:4]};
if (mii_odd) begin
gmii_rxd_d1 <= gmii_rxd_d0;
gmii_rxd_d2 <= gmii_rxd_d1;
gmii_rxd_d3 <= gmii_rxd_d2;
gmii_rxd_d4 <= gmii_rxd_d3;
gmii_rx_er_d0 <= gmii_rx_er | gmii_rx_er_d0;
gmii_rx_er_d1 <= gmii_rx_er_d0;
gmii_rx_er_d2 <= gmii_rx_er_d1;
gmii_rx_er_d3 <= gmii_rx_er_d2;
gmii_rx_er_d4 <= gmii_rx_er_d3;
end else begin
gmii_rx_er_d0 <= gmii_rx_er;
end
end else begin
gmii_rxd_d0 <= gmii_rxd;
gmii_rxd_d1 <= gmii_rxd_d0;
gmii_rxd_d2 <= gmii_rxd_d1;
gmii_rxd_d3 <= gmii_rxd_d2;
gmii_rxd_d4 <= gmii_rxd_d3;
gmii_rx_er_d0 <= gmii_rx_er;
gmii_rx_er_d1 <= gmii_rx_er_d0;
gmii_rx_er_d2 <= gmii_rx_er_d1;
gmii_rx_er_d3 <= gmii_rx_er_d2;
gmii_rx_er_d4 <= gmii_rx_er_d3;
end
end
end
endmodule |
module rgmii_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
output wire mac_gmii_tx_en,
/*
* AXI input
*/
input wire tx_axis_tvalid,
input wire tx_axis_tlast,
input wire [7:0] tx_axis_tdata,
output wire tx_axis_tready,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire rx_clk,
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* Status
*/
output wire [31:0] rx_fcs_reg,
output wire [31:0] tx_fcs_reg
);
assign phy_reset_n = !rst;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.rx_clk(rx_clk),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.mac_gmii_tx_en(mac_gmii_tx_en),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fcs_reg(rx_fcs_reg),
.tx_fcs_reg(tx_fcs_reg),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
endmodule |
module dualmem_widen(clka, clkb, dina, dinb, addra, addrb, wea, web, douta, doutb, ena, enb);
input wire clka, clkb;
input [15:0] dina;
input [63:0] dinb;
input [10:0] addra;
input [8:0] addrb;
input [1:0] wea;
input [1:0] web;
input [0:0] ena, enb;
output [15:0] douta;
output [63:0] doutb;
genvar r;
wire [47:0] dout;
/*
`ifndef verilator
`define RAMB16
`endif
*/
`ifdef KINTEX7
`define RAMB16
`endif
`ifdef RAMB16
generate for (r = 0; r < 2; r=r+1)
RAMB16_S9_S36
RAMB16_S9_S36_inst
(
.CLKA ( clka ), // Port A Clock
.DOA ( douta[r*8 +: 8] ), // Port A 1-bit Data Output
.DOPA ( ),
.ADDRA ( addra ), // Port A 14-bit Address Input
.DIA ( dina[r*8 +: 8] ), // Port A 1-bit Data Input
.DIPA ( 1'b0 ),
.ENA ( ena ), // Port A RAM Enable Input
.SSRA ( 1'b0 ), // Port A Synchronous Set/Reset Input
.WEA ( wea[r] ), // Port A Write Enable Input
.CLKB ( clkb ), // Port B Clock
.DOB ( doutb[r*32 +: 32] ), // Port B 1-bit Data Output
.DOPB ( ),
.ADDRB ( addrb ), // Port B 14-bit Address Input
.DIB ( dinb[r*32 +: 32] ), // Port B 1-bit Data Input
.DIPB ( 4'b0 ),
.ENB ( enb ), // Port B RAM Enable Input
.SSRB ( 1'b0 ), // Port B Synchronous Set/Reset Input
.WEB ( web[r] ) // Port B Write Enable Input
);
endgenerate
`else // !`ifdef RAMB16
// This bit is a placeholder
infer_dpram #(.RAM_SIZE(11), .BYTE_WIDTH(8)) ram1 // RAM_SIZE is in words
(
.ram_clk_a(clka),
.ram_en_a(|ena),
.ram_we_a({wea[1],wea[1],wea[1],wea[1],wea[0],wea[0],wea[0],wea[0]}),
.ram_addr_a(addra),
.ram_wrdata_a({dina,dina,dina,dina}),
.ram_rddata_a({dout,douta}),
.ram_clk_b(clkb),
.ram_en_b(|enb),
.ram_we_b({web[1],web[1],web[1],web[1],web[0],web[0],web[0],web[0]}),
.ram_addr_b({2'b0,addrb}),
.ram_wrdata_b(dinb),
.ram_rddata_b(doutb)
);
`endif
endmodule // dualmem |
module dualmem_widen8(clka, clkb, dina, dinb, addra, addrb, wea, web, douta, doutb, ena, enb);
input wire clka, clkb;
input [15:0] dina;
input [63:0] dinb;
input [12:0] addra;
input [10:0] addrb;
input [1:0] wea;
input [1:0] web;
input [0:0] ena, enb;
output [15:0] douta;
output [63:0] doutb;
genvar r;
wire [63:0] dout0;
wire [255:0] dout1;
wire [7:0] we0, we1, en0, en1;
wire [63:0] din0;
wire [255:0] din1;
reg [12:0] addra_dly;
reg [10:0] addrb_dly;
/*
`ifndef verilator
`define RAMB16
`endif
*/
`ifdef KINTEX7
`define RAMB16
`endif
`ifdef RAMB16
assign douta = dout0 >> {addra_dly[12:11],4'b0000};
assign doutb = dout1 >> {addrb_dly[10:9],6'b000000};
assign we0 = wea << {addra[12:11],1'b0};
assign we1 = web << {addrb[10:9],1'b0};
assign en0 = {ena,ena} << {addra[12:11],1'b0};
assign en1 = {enb,enb} << {addrb[10:9],1'b0};
assign din0 = {dina,dina,dina,dina};
assign din1 = {dinb,dinb,dinb,dinb};
always @(posedge clka)
begin
addra_dly <= addra;
addrb_dly <= addrb;
end
generate for (r = 0; r < 8; r=r+1)
RAMB16_S9_S36
RAMB16_S9_S36_inst
(
.CLKA ( clka ), // Port A Clock
.DOA ( dout0[r*8 +: 8] ), // Port A 1-bit Data Output
.DOPA ( ),
.ADDRA ( addra[10:0] ), // Port A 14-bit Address Input
.DIA ( din0[r*8 +: 8] ), // Port A 1-bit Data Input
.DIPA ( 1'b0 ),
.ENA ( en0[r] ), // Port A RAM Enable Input
.SSRA ( 1'b0 ), // Port A Synchronous Set/Reset Input
.WEA ( we0[r] ), // Port A Write Enable Input
.CLKB ( clkb ), // Port B Clock
.DOB ( dout1[r*32 +: 32] ), // Port B 1-bit Data Output
.DOPB ( ),
.ADDRB ( addrb[8:0] ), // Port B 14-bit Address Input
.DIB ( din1[r*32 +: 32] ), // Port B 1-bit Data Input
.DIPB ( 4'b0 ),
.ENB ( en1[r] ), // Port B RAM Enable Input
.SSRB ( 1'b0 ), // Port B Synchronous Set/Reset Input
.WEB ( we1[r] ) // Port B Write Enable Input
);
endgenerate
`else // !`ifdef RAMB16
// This bit is a placeholder
infer_dpram #(.RAM_SIZE(11), .BYTE_WIDTH(8)) ram1 // RAM_SIZE is in words
(
.ram_clk_a(clka),
.ram_en_a(|ena),
.ram_we_a({wea[1],wea[1],wea[1],wea[1],wea[0],wea[0],wea[0],wea[0]}),
.ram_addr_a(addra),
.ram_wrdata_a({dina,dina,dina,dina}),
.ram_rddata_a({dout,douta}),
.ram_clk_b(clkb),
.ram_en_b(|enb),
.ram_we_b({web[1],web[1],web[1],web[1],web[0],web[0],web[0],web[0]}),
.ram_addr_b({2'b0,addrb}),
.ram_wrdata_b(dinb),
.ram_rddata_b(doutb)
);
`endif
endmodule // dualmem |
module framing_top
(
input wire msoc_clk,
input wire [14:0] core_lsu_addr,
input wire [63:0] core_lsu_wdata,
input wire [7:0] core_lsu_be,
input wire ce_d,
input wire we_d,
input wire framing_sel,
output logic [63:0] framing_rdata,
// Internal 125 MHz clock
input wire clk_int,
input wire rst_int,
input wire clk90_int,
input wire clk_200_int,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
input wire phy_mdio_i,
output reg phy_mdio_o,
output reg phy_mdio_oe,
output wire phy_mdc,
output reg eth_irq
);
// obsolete signals to be removedphy_
//
logic [14:0] core_lsu_addr_dly;
logic tx_enable_i, mac_gmii_tx_en;
logic [47:0] mac_address, rx_dest_mac;
logic [10:0] tx_frame_addr, rx_length_axis[0:7], tx_packet_length;
logic [12:0] axis_tx_frame_size;
logic ce_d_dly, avail;
logic [63:0] framing_rdata_pkt, framing_wdata_pkt;
logic [3:0] tx_enable_dly, firstbuf, nextbuf, lastbuf;
logic [2:0] last;
reg byte_sync, sync, irq_en, tx_busy;
wire [7:0] m_enb = (we_d ? core_lsu_be : 8'hFF);
logic phy_mdclk, cooked, tx_enable_old, loopback, promiscuous;
logic [3:0] spare;
logic [10:0] rx_addr_axis;
/*
* AXI input
*/
reg tx_axis_tvalid;
reg tx_axis_tvalid_dly;
reg tx_axis_tlast;
wire [7:0] tx_axis_tdata;
wire tx_axis_tready;
wire tx_axis_tuser = 1'b0;
/*
* AXI output
*/
wire rx_clk;
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
/*
* AXIS Status
*/
wire [31:0] tx_fcs_reg_rev, rx_fcs_reg_rev;
always @(posedge rx_clk)
if (rst_int == 1'b1)
begin
byte_sync <= 1'b0;
end
else
begin
if (rx_axis_tvalid && (byte_sync == 0) && (nextbuf != (firstbuf+lastbuf)&15))
begin
byte_sync <= 1'b1;
end
if (rx_axis_tlast && byte_sync)
begin
last <= 1'b1;
end
else if ((last > 0) && (last < 7))
begin
byte_sync <= 1'b0;
last <= last + 3'b1;
end
else
begin
last <= 3'b0;
end
end
wire [1:0] rx_wr = rx_axis_tvalid << rx_addr_axis[2];
logic [15:0] douta;
assign tx_axis_tdata = douta >> {tx_frame_addr[2],3'b000};
assign phy_mdc = phy_mdclk;
dualmem_widen8 RAMB16_inst_rx (
.clka(rx_clk), // Port A Clock
.clkb(msoc_clk), // Port A Clock
.douta(), // Port A 8-bit Data Output
.addra({nextbuf[2:0],rx_addr_axis[10:3],rx_addr_axis[1:0]}), // Port A 11-bit Address Input
.dina({rx_axis_tdata,rx_axis_tdata}), // Port A 8-bit Data Input
.ena(rx_axis_tvalid), // Port A RAM Enable Input
.wea(rx_wr), // Port A Write Enable Input
.doutb(framing_rdata_pkt), // Port B 32-bit Data Output
.addrb(core_lsu_addr[13:3]), // Port B 9-bit Address Input
.dinb(core_lsu_wdata), // Port B 32-bit Data Input
.enb(ce_d & framing_sel & core_lsu_addr[14]),
// Port B RAM Enable Input
.web(we_d ? {(|core_lsu_be[7:4]),(|core_lsu_be[3:0])} : 2'b0) // Port B Write Enable Input
);
dualmem_widen RAMB16_inst_tx (
.clka(~clk_int), // Port A Clock
.clkb(msoc_clk), // Port A Clock
.douta(douta), // Port A 8-bit Data Output
.addra({1'b0,tx_frame_addr[10:3],tx_frame_addr[1:0]}), // Port A 11-bit Address Input
.dina(16'b0), // Port A 8-bit Data Input
.ena(tx_axis_tvalid), // Port A RAM Enable Input
.wea(2'b0), // Port A Write Enable Input
.doutb(framing_wdata_pkt), // Port B 32-bit Data Output
.addrb(core_lsu_addr[11:3]), // Port B 9-bit Address Input
.dinb(core_lsu_wdata), // Port B 32-bit Data Input
.enb(ce_d & framing_sel & (core_lsu_addr[14:12]==3'b001)),
// Port B RAM Enable Input
.web(we_d ? {(|core_lsu_be[7:4]),(|core_lsu_be[3:0])} : 2'b0) // Port B Write Enable Input
);
always @(posedge msoc_clk)
if (rst_int)
begin
core_lsu_addr_dly <= 0;
mac_address <= 48'H230100890702;
tx_packet_length <= 0;
tx_enable_dly <= 0;
cooked <= 1'b0;
loopback <= 1'b0;
spare <= 4'b0;
promiscuous <= 1'b0;
phy_mdio_oe <= 1'b0;
phy_mdio_o <= 1'b0;
phy_mdclk <= 1'b0;
sync <= 1'b0;
firstbuf <= 4'b0;
lastbuf <= 4'b0;
nextbuf <= 4'b0;
eth_irq <= 1'b0;
irq_en <= 1'b0;
ce_d_dly <= 1'b0;
tx_busy <= 1'b0;
avail = 1'b0;
end
else
begin
core_lsu_addr_dly <= core_lsu_addr;
ce_d_dly <= ce_d;
avail = nextbuf != firstbuf;
eth_irq <= avail & irq_en; // make eth_irq go away immediately if irq_en is low
if (framing_sel&we_d&(&core_lsu_be[3:0])&(core_lsu_addr[14:11]==4'b0001))
case(core_lsu_addr[6:3])
0: mac_address[31:0] <= core_lsu_wdata;
1: {irq_en,promiscuous,spare,loopback,cooked,mac_address[47:32]} <= core_lsu_wdata;
2: begin tx_enable_dly <= 10; tx_packet_length <= core_lsu_wdata; end /* tx payload size */
3: begin tx_enable_dly <= 0; tx_packet_length <= 0; end
4: begin {phy_mdio_oe,phy_mdio_o,phy_mdclk} <= core_lsu_wdata; end
5: begin lastbuf <= core_lsu_wdata[3:0]; end
6: begin firstbuf <= core_lsu_wdata[3:0]; end
default:;
endcase
if ((last > 0) && ~sync)
begin
// check broadcast/multicast address
sync <= (rx_dest_mac[47:24]==24'h01005E) | (&rx_dest_mac) | (mac_address == rx_dest_mac) | promiscuous;
end
else if (!last)
begin
if (sync) nextbuf <= nextbuf + 1'b1;
sync <= 1'b0;
end
if (mac_gmii_tx_en && tx_enable_i)
begin
tx_enable_dly <= 0;
end
else if (1'b1 == |tx_enable_dly)
begin
tx_busy <= 1'b1;
tx_enable_dly <= tx_enable_dly + !(&tx_enable_dly);
end
else if (~mac_gmii_tx_en)
tx_busy <= 1'b0;
end
always @(posedge clk_int)
if (rst_int)
begin
tx_enable_i <= 1'b0;
end
else
begin
if (mac_gmii_tx_en && tx_axis_tlast)
begin
tx_enable_i <= 1'b0;
end
else if (1'b1 == &tx_enable_dly)
tx_enable_i <= 1'b1;
end
always @* casez({ce_d_dly,core_lsu_addr_dly[14:3]})
13'b10001????0000 : framing_rdata = mac_address[31:0];
13'b10001????0001 : framing_rdata = {irq_en, promiscuous, spare, loopback, cooked, mac_address[47:32]};
13'b1000?????0010 : framing_rdata = {tx_busy, 4'b0, tx_frame_addr, 5'b0, tx_packet_length};
13'b10001????0011 : framing_rdata = tx_fcs_reg_rev;
13'b10001????0100 : framing_rdata = {phy_mdio_i,phy_mdio_oe,phy_mdio_o,phy_mdclk};
13'b10001????0101 : framing_rdata = rx_fcs_reg_rev;
13'b10001????0110 : framing_rdata = {eth_irq, avail, lastbuf, nextbuf, firstbuf};
13'b10001????1??? : framing_rdata = rx_length_axis[core_lsu_addr_dly[5:3]];
13'b10010???????? : framing_rdata = framing_wdata_pkt;
13'b11??????????? : framing_rdata = framing_rdata_pkt;
default: framing_rdata = 'h0;
endcase
parameter dly = 0;
wire [31:0] tx_fcs_reg, rx_fcs_reg;
assign tx_fcs_reg_rev = {tx_fcs_reg[0],tx_fcs_reg[1],tx_fcs_reg[2],tx_fcs_reg[3],
tx_fcs_reg[4],tx_fcs_reg[5],tx_fcs_reg[6],tx_fcs_reg[7],
tx_fcs_reg[8],tx_fcs_reg[9],tx_fcs_reg[10],tx_fcs_reg[11],
tx_fcs_reg[12],tx_fcs_reg[13],tx_fcs_reg[14],tx_fcs_reg[15],
tx_fcs_reg[16],tx_fcs_reg[17],tx_fcs_reg[18],tx_fcs_reg[19],
tx_fcs_reg[20],tx_fcs_reg[21],tx_fcs_reg[22],tx_fcs_reg[23],
tx_fcs_reg[24],tx_fcs_reg[25],tx_fcs_reg[26],tx_fcs_reg[27],
tx_fcs_reg[28],tx_fcs_reg[29],tx_fcs_reg[30],tx_fcs_reg[31]};
assign rx_fcs_reg_rev = {rx_fcs_reg[0],rx_fcs_reg[1],rx_fcs_reg[2],rx_fcs_reg[3],
rx_fcs_reg[4],rx_fcs_reg[5],rx_fcs_reg[6],rx_fcs_reg[7],
rx_fcs_reg[8],rx_fcs_reg[9],rx_fcs_reg[10],rx_fcs_reg[11],
rx_fcs_reg[12],rx_fcs_reg[13],rx_fcs_reg[14],rx_fcs_reg[15],
rx_fcs_reg[16],rx_fcs_reg[17],rx_fcs_reg[18],rx_fcs_reg[19],
rx_fcs_reg[20],rx_fcs_reg[21],rx_fcs_reg[22],rx_fcs_reg[23],
rx_fcs_reg[24],rx_fcs_reg[25],rx_fcs_reg[26],rx_fcs_reg[27],
rx_fcs_reg[28],rx_fcs_reg[29],rx_fcs_reg[30],rx_fcs_reg[31]};
always @(posedge clk_int)
if (rst_int)
begin
tx_axis_tvalid <= 'b0;
tx_axis_tvalid_dly <= 'b0;
tx_frame_addr <= 'b0;
tx_axis_tlast <= 'b0;
end
else
begin
tx_enable_old <= tx_enable_i;
if (tx_enable_i & (tx_enable_old == 0))
begin
tx_frame_addr <= 'b0;
end
if (tx_axis_tready)
begin
tx_frame_addr <= tx_frame_addr + 1;
tx_axis_tlast <= (tx_frame_addr == tx_packet_length-2) & tx_axis_tvalid_dly;
end
tx_axis_tvalid <= tx_axis_tvalid_dly;
if (tx_enable_old)
tx_axis_tvalid_dly <= 1'b1;
else if (~tx_axis_tlast)
tx_axis_tvalid_dly <= 1'b0;
end
always @(posedge rx_clk)
if (rst_int)
begin
rx_addr_axis <= 'b0;
rx_dest_mac <= 'b0;
end
else
begin
if (rx_axis_tvalid)
begin
rx_addr_axis <= rx_addr_axis + 1;
if (rx_addr_axis < 6)
rx_dest_mac <= {rx_dest_mac[39:0],rx_axis_tdata};
end
if (rx_axis_tlast)
begin
rx_length_axis[nextbuf[2:0]] <= rx_addr_axis + 1;
rx_addr_axis <= 'b0;
end
end
rgmii_soc rgmii_soc1
(
.rst_int(rst_int),
.clk_int(clk_int),
.clk90_int(clk90_int),
.clk_200_int(clk_200_int),
.rx_clk(rx_clk),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_ctl(phy_rx_ctl),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_ctl(phy_tx_ctl),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
.phy_pme_n(phy_pme_n),
.mac_gmii_tx_en(mac_gmii_tx_en),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rx_fcs_reg(rx_fcs_reg),
.tx_fcs_reg(tx_fcs_reg)
);
// `define XILINX_ILA_1
// `define XILINX_ILA_2
// `define XILINX_ILA_3
`ifdef XILINX_ILA_1
xlnx_ila_1 eth_ila_clk_rx (
.clk(clk_int), // input wire clk
.probe0(rx_axis_tdata), // input wire [7:0] probe4
.probe1(rx_axis_tvalid), // input wire [0:0] probe5
.probe2(rx_axis_tlast), // input wire [0:0] probe6
.probe3(rx_axis_tuser), // input wire [0:0] probe7
.probe4(byte_sync),
.probe5(last),
.probe6(rx_addr_axis),
.probe7(rx_dest_mac),
.probe8(rx_length_axis[nextbuf[2:0]]),
.probe9(rx_clk)
);
`endif
`ifdef XILINX_ILA_2
xlnx_ila_2 eth_ila_clk_int (
.clk(clk_int), // input wire clk
.probe0(tx_axis_tdata), // input wire [7:0] probe0
.probe1(tx_axis_tvalid), // input wire [0:0] probe1
.probe2(tx_axis_tready), // input wire [0:0] probe2
.probe3(tx_axis_tlast), // input wire [0:0] probe3
.probe4(tx_enable_i),
.probe5(douta),
.probe6(tx_axis_tvalid_dly),
.probe7(tx_frame_addr),
.probe8(mac_gmii_tx_en),
.probe9(tx_enable_old)
);
`endif
`ifdef XILINX_ILA_3
xlnx_ila_3 eth_ila_clk_msoc (
.clk(msoc_clk), // input wire clk
.probe0(sync),
.probe1(avail),
.probe2(nextbuf),
.probe3(tx_enable_dly),
.probe4(tx_busy)
);
`endif
endmodule // framing_top |
module rgmii_soc (
// Internal 125 MHz clock
input clk_int,
input rst_int,
input clk90_int,
input clk_200_int,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
output wire mac_gmii_tx_en,
/*
* AXI input
*/
input wire tx_axis_tvalid,
input wire tx_axis_tlast,
input wire [7:0] tx_axis_tdata,
output wire tx_axis_tready,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire rx_clk,
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output rx_axis_tuser,
/*
* Status
*/
output wire [31:0] rx_fcs_reg,
output wire [31:0] tx_fcs_reg
);
// IODELAY elements for RGMII interface to PHY
wire [3:0] phy_rxd_delay;
wire phy_rx_ctl_delay;
IDELAYCTRL
idelayctrl_inst
(
.REFCLK(clk_200_int),
.RST(rst_int),
.RDY()
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_0
(
.IDATAIN(phy_rxd[0]),
.DATAOUT(phy_rxd_delay[0]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_1
(
.IDATAIN(phy_rxd[1]),
.DATAOUT(phy_rxd_delay[1]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_2
(
.IDATAIN(phy_rxd[2]),
.DATAOUT(phy_rxd_delay[2]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_3
(
.IDATAIN(phy_rxd[3]),
.DATAOUT(phy_rxd_delay[3]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_VALUE(0),
.IDELAY_TYPE("FIXED")
)
phy_rx_ctl_idelay
(
.IDATAIN(phy_rx_ctl),
.DATAOUT(phy_rx_ctl_delay),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
rgmii_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.clk90(clk90_int),
.rx_clk(rx_clk),
.rst(rst_int),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd_delay),
.phy_rx_ctl(phy_rx_ctl_delay),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_ctl(phy_tx_ctl),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
.phy_pme_n(phy_pme_n),
.mac_gmii_tx_en(mac_gmii_tx_en),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rx_fcs_reg(rx_fcs_reg),
.tx_fcs_reg(tx_fcs_reg)
);
endmodule |
module eth_mac_1g #
(
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* GMII interface
*/
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Control
*/
input wire rx_clk_enable,
input wire tx_clk_enable,
input wire rx_mii_select,
input wire tx_mii_select,
/*
* Status
*/
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire [31:0] rx_fcs_reg,
output wire [31:0] tx_fcs_reg,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
axis_gmii_rx
axis_gmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.clk_enable(rx_clk_enable),
.mii_select(rx_mii_select),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs),
.fcs_reg(rx_fcs_reg)
);
axis_gmii_tx #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
axis_gmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.clk_enable(tx_clk_enable),
.mii_select(tx_mii_select),
.ifg_delay(ifg_delay),
.fcs_reg(tx_fcs_reg)
);
endmodule |
module axis_gmii_tx #
(
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [7:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* GMII output
*/
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Control
*/
input wire clk_enable,
input wire mii_select,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
/* debug */
output reg [31:0] fcs_reg
);
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PREAMBLE = 3'd1,
STATE_PAYLOAD = 3'd2,
STATE_LAST = 3'd3,
STATE_PAD = 3'd4,
STATE_FCS = 3'd5,
STATE_WAIT_END = 3'd6,
STATE_IFG = 3'd7;
reg [2:0] state_reg, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg [7:0] s_tdata_reg, s_tdata_next, ifg_reg, ifg_next;
reg mii_odd_reg, mii_odd_next;
reg [3:0] mii_msn_reg, mii_msn_next;
reg [15:0] frame_ptr_reg, frame_ptr_next;
reg [7:0] gmii_txd_reg, gmii_txd_next;
reg gmii_tx_en_reg, gmii_tx_en_next;
reg gmii_tx_er_reg, gmii_tx_er_next;
reg s_axis_tready_reg, s_axis_tready_next;
reg [31:0] crc_state, fcs_next;
wire [31:0] crc_next;
assign s_axis_tready = s_axis_tready_reg;
assign gmii_txd = gmii_txd_reg;
assign gmii_tx_en = gmii_tx_en_reg;
assign gmii_tx_er = gmii_tx_er_reg;
rgmii_lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(s_tdata_reg),
.state_in(crc_state),
.data_out(),
.state_out(crc_next)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
mii_odd_next = mii_odd_reg;
mii_msn_next = mii_msn_reg;
frame_ptr_next = frame_ptr_reg;
fcs_next = fcs_reg;
ifg_next = ifg_reg;
s_axis_tready_next = 1'b0;
s_tdata_next = s_tdata_reg;
gmii_txd_next = 8'd0;
gmii_tx_en_next = 1'b0;
gmii_tx_er_next = 1'b0;
if (!clk_enable) begin
// clock disabled - hold state and outputs
gmii_txd_next = gmii_txd_reg;
gmii_tx_en_next = gmii_tx_en_reg;
gmii_tx_er_next = gmii_tx_er_reg;
state_next = state_reg;
end else if (mii_select && mii_odd_reg) begin
// MII odd cycle - hold state, output MSN
mii_odd_next = 1'b0;
gmii_txd_next = {4'd0, mii_msn_reg};
gmii_tx_en_next = gmii_tx_en_reg;
gmii_tx_er_next = gmii_tx_er_reg;
state_next = state_reg;
end else begin
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
mii_odd_next = 1'b0;
if (s_axis_tvalid) begin
mii_odd_next = 1'b1;
frame_ptr_next = 16'd1;
gmii_txd_next = ETH_PRE;
gmii_tx_en_next = 1'b1;
state_next = STATE_PREAMBLE;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PREAMBLE: begin
// send preamble
reset_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
gmii_txd_next = ETH_PRE;
gmii_tx_en_next = 1'b1;
if (frame_ptr_reg == 16'd6) begin
s_axis_tready_next = 1'b1;
s_tdata_next = s_axis_tdata;
state_next = STATE_PREAMBLE;
end else if (frame_ptr_reg == 16'd7) begin
// end of preamble; start payload
frame_ptr_next = 16'd0;
if (s_axis_tready_reg) begin
s_axis_tready_next = 1'b1;
s_tdata_next = s_axis_tdata;
end
gmii_txd_next = ETH_SFD;
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_PREAMBLE;
end
end
STATE_PAYLOAD: begin
// send payload
update_crc = 1'b1;
s_axis_tready_next = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
gmii_txd_next = s_tdata_reg;
gmii_tx_en_next = 1'b1;
s_tdata_next = s_axis_tdata;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
s_axis_tready_next = !s_axis_tready_reg;
if (s_axis_tuser) begin
gmii_tx_er_next = 1'b1;
frame_ptr_next = 1'b0;
state_next = STATE_IFG;
end else begin
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
// tvalid deassert, fail frame
gmii_tx_er_next = 1'b1;
frame_ptr_next = 16'd0;
state_next = STATE_WAIT_END;
end
end
STATE_LAST: begin
// last payload word
update_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
gmii_txd_next = s_tdata_reg;
gmii_tx_en_next = 1'b1;
if (ENABLE_PADDING && frame_ptr_reg < MIN_FRAME_LENGTH-5) begin
s_tdata_next = 8'd0;
state_next = STATE_PAD;
end else begin
frame_ptr_next = 16'd0;
state_next = STATE_FCS;
end
end
STATE_PAD: begin
// send padding
update_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
gmii_txd_next = 8'd0;
gmii_tx_en_next = 1'b1;
s_tdata_next = 8'd0;
if (frame_ptr_reg < MIN_FRAME_LENGTH-5) begin
state_next = STATE_PAD;
end else begin
frame_ptr_next = 16'd0;
state_next = STATE_FCS;
end
end
STATE_FCS: begin
// send FCS
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
case (frame_ptr_reg)
2'd0: gmii_txd_next = ~crc_state[7:0];
2'd1: gmii_txd_next = ~crc_state[15:8];
2'd2: gmii_txd_next = ~crc_state[23:16];
2'd3: gmii_txd_next = ~crc_state[31:24];
default:;
endcase
gmii_tx_en_next = 1'b1;
if (frame_ptr_reg < 3) begin
state_next = STATE_FCS;
end else begin
frame_ptr_next = 16'd0;
fcs_next = crc_state;
state_next = STATE_IFG;
end
end
STATE_WAIT_END: begin
// wait for end of frame
reset_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
s_axis_tready_next = 1'b1;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
s_axis_tready_next = 1'b0;
ifg_next = 8'b0;
state_next = STATE_IFG;
end else begin
state_next = STATE_WAIT_END;
end
end else begin
state_next = STATE_WAIT_END;
end
end
STATE_IFG: begin
// send IFG
reset_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
if (ifg_reg < ifg_delay-1) begin
ifg_next = ifg_reg + 1;
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
end
end
endcase
if (mii_select) begin
mii_msn_next = gmii_txd_next[7:4];
gmii_txd_next[7:4] = 4'd0;
end
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
s_axis_tready_reg <= 1'b0;
gmii_tx_en_reg <= 1'b0;
gmii_tx_er_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
fcs_reg <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
s_axis_tready_reg <= s_axis_tready_next;
gmii_tx_en_reg <= gmii_tx_en_next;
gmii_tx_er_reg <= gmii_tx_er_next;
fcs_reg <= fcs_next;
ifg_reg <= ifg_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next;
end
end
mii_odd_reg <= mii_odd_next;
mii_msn_reg <= mii_msn_next;
s_tdata_reg <= s_tdata_next;
gmii_txd_reg <= gmii_txd_next;
end
endmodule |
module reg_uart_wrap #(
parameter int unsigned AddrWidth = -1,
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic
) (
input logic clk_i,
input logic rst_ni,
// Regbus
input reg_req_t reg_req_i,
output reg_rsp_t reg_rsp_o,
// Physical interface
output logic intr_o,
output logic out1_no,
output logic out2_no,
output logic rts_no,
output logic dtr_no,
input logic cts_ni,
input logic dsr_ni,
input logic dcd_ni,
input logic rin_ni,
input logic sin_i, // RX
output logic sout_o // TX
);
`APB_TYPEDEF_REQ_T(reg_uart_apb_req_t, logic [AddrWidth-1:0], logic [31:0], logic [3:0])
`APB_TYPEDEF_RESP_T(reg_uart_apb_rsp_t, logic [31:0])
reg_uart_apb_req_t uart_apb_req;
reg_uart_apb_rsp_t uart_apb_rsp;
reg_to_apb #(
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.apb_req_t ( reg_uart_apb_req_t ),
.apb_rsp_t ( reg_uart_apb_rsp_t )
) i_reg_uart_reg_to_apb (
.clk_i,
.rst_ni,
.reg_req_i,
.reg_rsp_o,
.apb_req_o ( uart_apb_req ),
.apb_rsp_i ( uart_apb_rsp )
);
apb_uart i_apb_uart (
.CLK ( clk_i ),
.RSTN ( rst_ni ),
.PSEL ( uart_apb_req.psel ),
.PENABLE ( uart_apb_req.penable ),
.PWRITE ( uart_apb_req.pwrite ),
.PADDR ( uart_apb_req.paddr[4:2] ),
.PWDATA ( uart_apb_req.pwdata ),
.PRDATA ( uart_apb_rsp.prdata ),
.PREADY ( uart_apb_rsp.pready ),
.PSLVERR ( uart_apb_rsp.pslverr ),
.INT ( intr_o ),
.OUT1N ( out1_no ),
.OUT2N ( out2_no ),
.RTSN ( rts_no ),
.DTRN ( dtr_no ),
.CTSN ( cts_ni ),
.DSRN ( dsr_ni ),
.DCDN ( dcd_ni ),
.RIN ( rin_ni ),
.SIN ( sin_i ),
.SOUT ( sout_o )
);
endmodule |
module isochronous_spill_register #(
/// Data type of spill register.
parameter type T = logic,
/// Make this spill register transparent.
parameter bit Bypass = 1'b0
) (
/// Clock of source clock domain.
input logic src_clk_i,
/// Active low async reset in source domain.
input logic src_rst_ni,
/// Source input data is valid.
input logic src_valid_i,
/// Source is ready to accept.
output logic src_ready_o,
/// Source input data.
input T src_data_i,
/// Clock of destination clock domain.
input logic dst_clk_i,
/// Active low async reset in destination domain.
input logic dst_rst_ni,
/// Destination output data is valid.
output logic dst_valid_o,
/// Destination is ready to accept.
input logic dst_ready_i,
/// Destination output data.
output T dst_data_o
);
// Don't generate the spill register.
if (Bypass) begin : gen_bypass
assign dst_valid_o = src_valid_i;
assign src_ready_o = dst_ready_i;
assign dst_data_o = src_data_i;
// Generate the spill register
end else begin : gen_isochronous_spill_register
/// Read/write pointer are one bit wider than necessary.
/// We implicitly capture the full and empty state with the second bit:
/// If all but the topmost bit of `rd_pointer_q` and `wr_pointer_q` agree, the
/// FIFO is in a critical state. If the topmost bit is equal, the FIFO is
/// empty, otherwise it is full.
logic [1:0] rd_pointer_q, wr_pointer_q;
// Advance write pointer if we pushed a new item into the FIFO. (Source clock domain)
`FFLARN(wr_pointer_q, wr_pointer_q+1, (src_valid_i && src_ready_o), '0, src_clk_i, src_rst_ni)
// Advance read pointer if downstream consumed an item. (Destination clock domain)
`FFLARN(rd_pointer_q, rd_pointer_q+1, (dst_valid_o && dst_ready_i), '0, dst_clk_i, dst_rst_ni)
T [1:0] mem_d, mem_q;
`FFLNR(mem_q, mem_d, (src_valid_i && src_ready_o), src_clk_i)
always_comb begin
mem_d = mem_q;
mem_d[wr_pointer_q[0]] = src_data_i;
end
assign src_ready_o = (rd_pointer_q ^ wr_pointer_q) != 2'b10;
assign dst_valid_o = (rd_pointer_q ^ wr_pointer_q) != '0;
assign dst_data_o = mem_q[rd_pointer_q[0]];
end
endmodule |
module stream_to_mem #(
/// Memory request payload type, usually write enable, write data, etc.
parameter type mem_req_t = logic,
/// Memory response payload type, usually read data
parameter type mem_resp_t = logic,
/// Number of buffered responses (fall-through, thus no additional latency). This defines the
/// maximum number of outstanding requests on the memory interface. If the attached memory
/// responds in the same cycle a request is applied, this MUST be 0. If the attached memory
/// responds at least one cycle after a request, this MUST be >= 1 and should be equal to the
/// response latency of the memory to saturate bandwidth.
parameter int unsigned BufDepth = 32'd1
) (
/// Clock
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// Request stream interface, payload
input mem_req_t req_i,
/// Request stream interface, payload is valid for transfer
input logic req_valid_i,
/// Request stream interface, payload can be accepted
output logic req_ready_o,
/// Response stream interface, payload
output mem_resp_t resp_o,
/// Response stream interface, payload is valid for transfer
output logic resp_valid_o,
/// Response stream interface, payload can be accepted
input logic resp_ready_i,
/// Memory request interface, payload
output mem_req_t mem_req_o,
/// Memory request interface, payload is valid for transfer
output logic mem_req_valid_o,
/// Memory request interface, payload can be accepted
input logic mem_req_ready_i,
/// Memory response interface, payload
input mem_resp_t mem_resp_i,
/// Memory response interface, payload is valid
input logic mem_resp_valid_i
);
typedef logic [$clog2(BufDepth+1):0] cnt_t;
cnt_t cnt_d, cnt_q;
logic buf_ready,
req_ready;
if (BufDepth > 0) begin : gen_buf
// Count number of outstanding requests.
always_comb begin
cnt_d = cnt_q;
if (req_valid_i && req_ready_o) begin
cnt_d++;
end
if (resp_valid_o && resp_ready_i) begin
cnt_d--;
end
end
// Can issue another request if the counter is not at its limit or a response is delivered in
// the current cycle.
assign req_ready = (cnt_q < BufDepth) | (resp_valid_o & resp_ready_i);
// Control request and memory request interface handshakes.
assign req_ready_o = mem_req_ready_i & req_ready;
assign mem_req_valid_o = req_valid_i & req_ready;
// Buffer responses.
stream_fifo #(
.FALL_THROUGH ( 1'b1 ),
.DEPTH ( BufDepth ),
.T ( mem_resp_t )
) i_resp_buf (
.clk_i,
.rst_ni,
.flush_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.data_i ( mem_resp_i ),
.valid_i ( mem_resp_valid_i ),
.ready_o ( buf_ready ),
.data_o ( resp_o ),
.valid_o ( resp_valid_o ),
.ready_i ( resp_ready_i ),
.usage_o ( /* unused */ )
);
// Register
`FFARN(cnt_q, cnt_d, '0, clk_i, rst_ni)
end else begin : gen_no_buf
// Control request, memory request, and response interface handshakes.
assign mem_req_valid_o = req_valid_i;
assign resp_valid_o = mem_req_valid_o & mem_req_ready_i & mem_resp_valid_i;
assign req_ready_o = resp_ready_i & resp_valid_o;
// Forward responses.
assign resp_o = mem_resp_i;
end
// Forward requests.
assign mem_req_o = req_i;
// Assertions
// pragma translate_off
`ifndef VERILATOR
if (BufDepth > 0) begin : gen_buf_asserts
assert property (@(posedge clk_i) mem_resp_valid_i |-> buf_ready)
else $error("Memory response lost!");
assert property (@(posedge clk_i) cnt_q == '0 |=> cnt_q != '1)
else $error("Counter underflowed!");
assert property (@(posedge clk_i) cnt_q == BufDepth |=> cnt_q != BufDepth + 1)
else $error("Counter overflowed!");
end else begin : gen_no_buf_asserts
assume property (@(posedge clk_i) mem_req_valid_o & mem_req_ready_i |-> mem_resp_valid_i)
else $error("Without BufDepth = 0, the memory must respond in the same cycle!");
end
`endif
// pragma translate_on
endmodule |
module tb_axi_addr_test #(
/// Number of calculated AX transfers
int unsigned NumTests = 32'd10000,
/// Print each calculated address
bit PrintDbg = 1'b0
);
localparam int unsigned AxiIdWidth = 32'd1;
localparam int unsigned AxiAddrWidth = 32'd16;
localparam int unsigned AxiDataWidth = 32'd1024;
localparam int unsigned AxiUserWidth = 32'd1;
// Sim print config, how many transactions
localparam int unsigned PrintTnx = 1000;
localparam int unsigned NoReads = 0;
localparam int unsigned NoWrites = NumTests;
typedef logic [AxiAddrWidth:0] addr_t;
/// The data transferred on a beat on the AW/AR channels.
class ax_transfer;
rand addr_t addr = '0;
rand axi_pkg::len_t len = '0;
rand axi_pkg::size_t size = '0;
rand axi_pkg::burst_t burst = '0;
endclass
// Random master no Transactions
localparam int unsigned NoPendingDut = 16;
// timing parameters
localparam time CyclTime = 10ns;
localparam time ApplTime = 2ns;
localparam time TestTime = 8ns;
typedef axi_test::axi_rand_master #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
.IW ( AxiIdWidth ),
.UW ( AxiUserWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime ),
// Enable burst types
.AXI_BURST_FIXED ( 1'b1 ),
.AXI_BURST_INCR ( 1'b1 ),
.AXI_BURST_WRAP ( 1'b1 )
) axi_rand_master_t;
typedef axi_test::axi_rand_slave #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
.IW ( AxiIdWidth ),
.UW ( AxiUserWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime )
) axi_rand_slave_t;
// -------------
// DUT signals
// -------------
logic clk;
logic rst_n;
logic end_of_sim;
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master_dv (clk);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave_dv (clk);
`AXI_ASSIGN(slave_dv, master_dv)
//-----------------------------------
// Clock generator
//-----------------------------------
clk_rst_gen #(
.ClkPeriod ( CyclTime ),
.RstClkCycles( 5 )
) i_clk_gen (
.clk_o (clk),
.rst_no(rst_n)
);
initial begin : proc_axi_master
automatic axi_rand_master_t axi_rand_master = new(master_dv);
end_of_sim <= 1'b0;
axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::DEVICE_NONBUFFERABLE);
axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WTHRU_NOALLOCATE);
axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WBACK_RWALLOCATE);
axi_rand_master.reset();
@(posedge rst_n);
axi_rand_master.run(0, NumTests);
end_of_sim <= 1'b1;
repeat (10000) @(posedge clk);
$stop();
end
initial begin : proc_axi_slave
automatic axi_rand_slave_t axi_rand_slave = new(slave_dv);
axi_rand_slave.reset();
@(posedge rst_n);
axi_rand_slave.run();
end
initial begin : proc_sim_progress
automatic int unsigned aw = 0;
automatic int unsigned ar = 0;
automatic bit aw_printed = 1'b0;
automatic bit ar_printed = 1'b0;
@(posedge rst_n);
forever begin
@(posedge clk);
#TestTime;
if (master_dv.aw_valid && master_dv.aw_ready) begin
aw++;
end
if (master_dv.ar_valid && master_dv.ar_ready) begin
ar++;
end
if ((aw % PrintTnx == 0) && ! aw_printed) begin
$display("%t> Transmit AW %d of %d.", $time(), aw, NoWrites);
aw_printed = 1'b1;
end
if ((ar % PrintTnx == 0) && !ar_printed) begin
$display("%t> Transmit AR %d of %d.", $time(), ar, NoReads);
ar_printed = 1'b1;
end
if (aw % PrintTnx == 1) begin
aw_printed = 1'b0;
end
if (ar % PrintTnx == 1) begin
ar_printed = 1'b0;
end
if (end_of_sim) begin
$info("All transactions completed.");
break;
end
end
end
// Test Address queue
ax_transfer ax_queue[$];
addr_t gold_addr[$];
initial begin : generate_tests
automatic logic rand_success;
automatic ax_transfer ax_beat;
forever begin
@(posedge clk);
#TestTime;
if (master_dv.aw_valid && master_dv.aw_ready) begin
ax_beat = new;
ax_beat.addr = master_dv.aw_addr;
ax_beat.len = master_dv.aw_len;
ax_beat.size = master_dv.aw_size;
ax_beat.burst = master_dv.aw_burst;
ax_queue.push_back(ax_beat);
end
end
end
initial begin : proc_test
automatic ax_transfer ax_beat;
automatic addr_t test_addr, exp_addr;
for (int unsigned i = 0; i < NumTests; i++) begin
wait (ax_queue.size());
// get current transfer
ax_beat = ax_queue.pop_front();
if (PrintDbg) begin
print_ax(ax_beat);
end
// golden model derived from pseudocode from A-52
data_transfer(ax_beat.addr, (2**ax_beat.size), (ax_beat.len+1), ax_beat.burst);
// test the calculated addresses
for (int unsigned i = 0; i <= ax_beat.len; i++) begin
test_addr = axi_pkg::beat_addr(ax_beat.addr, ax_beat.size, ax_beat.len, ax_beat.burst, i);
exp_addr = gold_addr.pop_front();
if (PrintDbg) begin
print_addr(test_addr, i);
end
assert (test_addr == exp_addr) else
begin
print_ax(ax_beat);
print_addr(test_addr, i);
$error("Expected ADDR: %0h was ADDR: %0h", exp_addr, test_addr);
end
end
end
end
// golden model derived from pseudocode from A-52
function automatic void data_transfer(addr_t start_addr, int unsigned num_bytes,
int unsigned burst_length, axi_pkg::burst_t mode);
// define boundaries wider than the address, to finf wrapp of addr space
localparam int unsigned large_addr = $bits(addr_t);
typedef logic [large_addr:0] laddr_t;
laddr_t addr;
laddr_t aligned_addr;
bit aligned;
int unsigned dtsize;
laddr_t lower_wrap_boundary;
laddr_t upper_wrap_boundary;
assume (mode inside {axi_pkg::BURST_FIXED, axi_pkg::BURST_INCR, axi_pkg::BURST_WRAP});
addr = laddr_t'(start_addr);
aligned_addr = laddr_t'((addr / num_bytes) * num_bytes);
aligned = (aligned_addr == addr);
dtsize = num_bytes * burst_length;
if (mode == axi_pkg::BURST_WRAP) begin
lower_wrap_boundary = laddr_t'((addr / dtsize) * dtsize);
upper_wrap_boundary = lower_wrap_boundary + dtsize;
end
for (int unsigned n = 1; n <= burst_length; n++) begin
gold_addr.push_back(addr_t'(addr));
// increment address if necessary
if (mode != axi_pkg::BURST_FIXED) begin
if (aligned) begin
addr += num_bytes;
end else begin
addr = aligned_addr + num_bytes;
aligned = 1'b1;
end
if (mode == axi_pkg::BURST_WRAP && (addr >= upper_wrap_boundary)) begin
addr = lower_wrap_boundary;
end
end
end
endfunction : data_transfer
function automatic void print_ax (ax_transfer ax);
$display("####################################################################",);
$display("AX transfer with:");
case (ax.burst)
axi_pkg::BURST_FIXED: $display("TYPE: BURST_FIXED");
axi_pkg::BURST_INCR: $display("TYPE: BURST_INCR");
axi_pkg::BURST_WRAP: $display("TYPE: BURST_WRAP");
default : $error("TYPE: NOT_DEFINED");
endcase
$display("ADDR: %0h", ax.addr);
$display("SIZE: %0h", ax.size);
$display("LEN: %0h", ax.len);
endfunction : print_ax
function automatic void print_addr(addr_t addr, int unsigned i_addr);
$display("i_beat: %0h ADDR: %0h", i_addr, addr);
endfunction : print_addr
endmodule |
module tb_axi_delayer;
parameter AW = 32;
parameter DW = 32;
parameter IW = 8;
parameter UW = 8;
parameter TS = 4;
localparam tCK = 1ns;
logic clk = 0;
logic rst = 1;
logic done = 0;
AXI_BUS_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi_slave_dv(clk), axi_master_dv(clk);
AXI_BUS #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi_slave(), axi_master();
`AXI_ASSIGN(axi_slave_dv, axi_slave)
`AXI_ASSIGN(axi_master, axi_master_dv)
axi_delayer_intf #(
.AXI_ADDR_WIDTH ( AW ),
.AXI_DATA_WIDTH ( DW ),
.AXI_ID_WIDTH ( IW ),
.AXI_USER_WIDTH ( UW ),
.FIXED_DELAY_INPUT ( 0 ),
.STALL_RANDOM_INPUT ( 1 )
) i_axi_delayer (
.clk_i ( clk ),
.rst_ni ( rst ),
.slv ( axi_master ),
.mst ( axi_slave )
);
axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(200ps), .TT(700ps)) axi_slave_drv = new(axi_slave_dv);
axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(200ps), .TT(700ps)) axi_master_drv = new(axi_master_dv);
initial begin
#tCK;
rst <= 0;
#tCK;
rst <= 1;
#tCK;
while (!done) begin
clk <= 1;
#(tCK/2);
clk <= 0;
#(tCK/2);
end
end
initial begin
automatic axi_test::axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat = new;
automatic axi_test::axi_w_beat #(.DW(DW), .UW(UW)) w_beat = new;
automatic axi_test::axi_b_beat #(.IW(IW), .UW(UW)) b_beat;
automatic logic rand_success;
axi_master_drv.reset_master();
@(posedge clk);
repeat (200) begin
@(posedge clk);
rand_success = ax_beat.randomize(); assert(rand_success);
axi_master_drv.send_aw(ax_beat);
w_beat.w_data = 'hcafebabe;
axi_master_drv.send_w(w_beat);
end
repeat (200) axi_master_drv.recv_b(b_beat);
done = 1;
end
initial begin
automatic axi_test::axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat;
automatic axi_test::axi_w_beat #(.DW(DW), .UW(UW)) w_beat;
automatic axi_test::axi_b_beat #(.IW(IW), .UW(UW)) b_beat = new;
automatic int b_id_queue[$];
axi_slave_drv.reset_slave();
@(posedge clk);
repeat (200) begin
axi_slave_drv.recv_aw(ax_beat);
$info("AXI AW: addr %h", ax_beat.ax_addr);
axi_slave_drv.recv_w(w_beat);
$info("AXI W: data %h, strb %h", w_beat.w_data, w_beat.w_strb);
b_id_queue.push_back(ax_beat.ax_id);
end
while (b_id_queue.size() != 0) begin
b_beat.b_id = b_id_queue.pop_front();
axi_slave_drv.send_b(b_beat);
end
end
// vsim -voptargs=+acc work.tb_axi_delayer
endmodule |
module tb_axi_xbar #(
parameter bit TbEnAtop = 1'b1, // enable atomic operations (ATOPs)
parameter bit TbEnExcl = 1'b0, // enable exclusive accesses
parameter bit TbUniqueIds = 1'b0 // restrict to only unique IDs
);
// Dut parameters
localparam int unsigned NoMasters = 6; // How many Axi Masters there are
localparam int unsigned NoSlaves = 8; // How many Axi Slaves there are
// Random master no Transactions
localparam int unsigned NoWrites = 125; // How many writes per master
localparam int unsigned NoReads = 125; // How many reads per master
// timing parameters
localparam time CyclTime = 10ns;
localparam time ApplTime = 2ns;
localparam time TestTime = 8ns;
// axi configuration
localparam int unsigned AxiIdWidthMasters = 4;
localparam int unsigned AxiIdUsed = 3; // Has to be <= AxiIdWidthMasters
localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMasters);
localparam int unsigned AxiAddrWidth = 32; // Axi Address Width
localparam int unsigned AxiDataWidth = 64; // Axi Data Width
localparam int unsigned AxiStrbWidth = AxiDataWidth / 8;
localparam int unsigned AxiUserWidth = 5;
// in the bench can change this variables which are set here freely
localparam axi_pkg::xbar_cfg_t xbar_cfg = '{
NoSlvPorts: NoMasters,
NoMstPorts: NoSlaves,
MaxMstTrans: 10,
MaxSlvTrans: 6,
FallThrough: 1'b0,
LatencyMode: axi_pkg::CUT_ALL_AX,
AxiIdWidthSlvPorts: AxiIdWidthMasters,
AxiIdUsedSlvPorts: AxiIdUsed,
UniqueIds: TbUniqueIds,
AxiAddrWidth: AxiAddrWidth,
AxiDataWidth: AxiDataWidth,
NoAddrRules: 8
};
typedef logic [AxiIdWidthMasters-1:0] id_mst_t;
typedef logic [AxiIdWidthSlaves-1:0] id_slv_t;
typedef logic [AxiAddrWidth-1:0] addr_t;
typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr
typedef logic [AxiDataWidth-1:0] data_t;
typedef logic [AxiStrbWidth-1:0] strb_t;
typedef logic [AxiUserWidth-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_mst_t, addr_t, id_mst_t, user_t)
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_slv_t, addr_t, id_slv_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_mst_t, id_mst_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_slv_t, id_slv_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_mst_t, addr_t, id_mst_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_slv_t, addr_t, id_slv_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_mst_t, data_t, id_mst_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_slv_t, data_t, id_slv_t, user_t)
`AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t)
`AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_mst_t, r_chan_mst_t)
`AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t)
`AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_slv_t, r_chan_slv_t)
localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = '{
'{idx: 32'd7, start_addr: 32'h0001_0000, end_addr: 32'h0001_1000},
'{idx: 32'd6, start_addr: 32'h0000_9000, end_addr: 32'h0001_0000},
'{idx: 32'd5, start_addr: 32'h0000_8000, end_addr: 32'h0000_9000},
'{idx: 32'd4, start_addr: 32'h0000_7000, end_addr: 32'h0000_8000},
'{idx: 32'd3, start_addr: 32'h0000_6300, end_addr: 32'h0000_7000},
'{idx: 32'd2, start_addr: 32'h0000_4000, end_addr: 32'h0000_6300},
'{idx: 32'd1, start_addr: 32'h0000_3000, end_addr: 32'h0000_4000},
'{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000}
};
typedef axi_test::axi_rand_master #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
.IW ( AxiIdWidthMasters ),
.UW ( AxiUserWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime ),
// Maximum number of read and write transactions in flight
.MAX_READ_TXNS ( 20 ),
.MAX_WRITE_TXNS ( 20 ),
.AXI_EXCLS ( TbEnExcl ),
.AXI_ATOPS ( TbEnAtop ),
.UNIQUE_IDS ( TbUniqueIds )
) axi_rand_master_t;
typedef axi_test::axi_rand_slave #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
.IW ( AxiIdWidthSlaves ),
.UW ( AxiUserWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime )
) axi_rand_slave_t;
// -------------
// DUT signals
// -------------
logic clk;
// DUT signals
logic rst_n;
logic [NoMasters-1:0] end_of_sim;
// master structs
mst_req_t [NoMasters-1:0] masters_req;
mst_resp_t [NoMasters-1:0] masters_resp;
// slave structs
slv_req_t [NoSlaves-1:0] slaves_req;
slv_resp_t [NoSlaves-1:0] slaves_resp;
// -------------------------------
// AXI Interfaces
// -------------------------------
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthMasters ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master [NoMasters-1:0] ();
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthMasters ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master_dv [NoMasters-1:0] (clk);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthMasters ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master_monitor_dv [NoMasters-1:0] (clk);
for (genvar i = 0; i < NoMasters; i++) begin : gen_conn_dv_masters
`AXI_ASSIGN (master[i], master_dv[i])
`AXI_ASSIGN_TO_REQ(masters_req[i], master[i])
`AXI_ASSIGN_FROM_RESP(master[i], masters_resp[i])
end
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave [NoSlaves-1:0] ();
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave_dv [NoSlaves-1:0](clk);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave_monitor_dv [NoSlaves-1:0](clk);
for (genvar i = 0; i < NoSlaves; i++) begin : gen_conn_dv_slaves
`AXI_ASSIGN(slave_dv[i], slave[i])
`AXI_ASSIGN_FROM_REQ(slave[i], slaves_req[i])
`AXI_ASSIGN_TO_RESP(slaves_resp[i], slave[i])
end
// -------------------------------
// AXI Rand Masters and Slaves
// -------------------------------
// Masters control simulation run time
for (genvar i = 0; i < NoMasters; i++) begin : gen_rand_master
static axi_rand_master_t axi_rand_master = new ( master_dv[i] );
initial begin
end_of_sim[i] <= 1'b0;
axi_rand_master.add_memory_region(AddrMap[0].start_addr,
AddrMap[xbar_cfg.NoAddrRules-1].end_addr,
axi_pkg::DEVICE_NONBUFFERABLE);
axi_rand_master.reset();
@(posedge rst_n);
axi_rand_master.run(NoReads, NoWrites);
end_of_sim[i] <= 1'b1;
end
end
for (genvar i = 0; i < NoSlaves; i++) begin : gen_rand_slave
static axi_rand_slave_t axi_rand_slave = new( slave_dv[i] );
initial begin
axi_rand_slave.reset();
@(posedge rst_n);
axi_rand_slave.run();
end
end
initial begin : proc_monitor
static tb_axi_xbar_pkg::axi_xbar_monitor #(
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiIdWidthMasters ( AxiIdWidthMasters ),
.AxiIdWidthSlaves ( AxiIdWidthSlaves ),
.AxiUserWidth ( AxiUserWidth ),
.NoMasters ( NoMasters ),
.NoSlaves ( NoSlaves ),
.NoAddrRules ( xbar_cfg.NoAddrRules ),
.rule_t ( rule_t ),
.AddrMap ( AddrMap ),
.TimeTest ( TestTime )
) monitor = new( master_monitor_dv, slave_monitor_dv );
fork
monitor.run();
do begin
#TestTime;
if(end_of_sim == '1) begin
monitor.print_result();
$stop();
end
@(posedge clk);
end while (1'b1);
join
end
//-----------------------------------
// Clock generator
//-----------------------------------
clk_rst_gen #(
.ClkPeriod ( CyclTime ),
.RstClkCycles ( 5 )
) i_clk_gen (
.clk_o (clk),
.rst_no(rst_n)
);
//-----------------------------------
// DUT
//-----------------------------------
axi_xbar #(
.Cfg ( xbar_cfg ),
.slv_aw_chan_t( aw_chan_mst_t ),
.mst_aw_chan_t( aw_chan_slv_t ),
.w_chan_t ( w_chan_t ),
.slv_b_chan_t ( b_chan_mst_t ),
.mst_b_chan_t ( b_chan_slv_t ),
.slv_ar_chan_t( ar_chan_mst_t ),
.mst_ar_chan_t( ar_chan_slv_t ),
.slv_r_chan_t ( r_chan_mst_t ),
.mst_r_chan_t ( r_chan_slv_t ),
.slv_req_t ( mst_req_t ),
.slv_resp_t ( mst_resp_t ),
.mst_req_t ( slv_req_t ),
.mst_resp_t ( slv_resp_t ),
.rule_t (rule_t )
) i_xbar_dut (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_i ( 1'b0 ),
.slv_ports_req_i ( masters_req ),
.slv_ports_resp_o ( masters_resp ),
.mst_ports_req_o ( slaves_req ),
.mst_ports_resp_i ( slaves_resp ),
.addr_map_i ( AddrMap ),
.en_default_mst_port_i ( '0 ),
.default_mst_port_i ( '0 )
);
// logger for master modules
for (genvar i = 0; i < NoMasters; i++) begin : gen_master_logger
axi_chan_logger #(
.TestTime ( TestTime ), // Time after clock, where sampling happens
.LoggerName( $sformatf("axi_logger_master_%0d", i)),
.aw_chan_t ( aw_chan_mst_t ), // axi AW type
.w_chan_t ( w_chan_t ), // axi W type
.b_chan_t ( b_chan_mst_t ), // axi B type
.ar_chan_t ( ar_chan_mst_t ), // axi AR type
.r_chan_t ( r_chan_mst_t ) // axi R type
) i_mst_channel_logger (
.clk_i ( clk ), // Clock
.rst_ni ( rst_n ), // Asynchronous reset active low, when `1'b0` no sampling
.end_sim_i ( &end_of_sim ),
// AW channel
.aw_chan_i ( masters_req[i].aw ),
.aw_valid_i ( masters_req[i].aw_valid ),
.aw_ready_i ( masters_resp[i].aw_ready ),
// W channel
.w_chan_i ( masters_req[i].w ),
.w_valid_i ( masters_req[i].w_valid ),
.w_ready_i ( masters_resp[i].w_ready ),
// B channel
.b_chan_i ( masters_resp[i].b ),
.b_valid_i ( masters_resp[i].b_valid ),
.b_ready_i ( masters_req[i].b_ready ),
// AR channel
.ar_chan_i ( masters_req[i].ar ),
.ar_valid_i ( masters_req[i].ar_valid ),
.ar_ready_i ( masters_resp[i].ar_ready ),
// R channel
.r_chan_i ( masters_resp[i].r ),
.r_valid_i ( masters_resp[i].r_valid ),
.r_ready_i ( masters_req[i].r_ready )
);
end
// logger for slave modules
for (genvar i = 0; i < NoSlaves; i++) begin : gen_slave_logger
axi_chan_logger #(
.TestTime ( TestTime ), // Time after clock, where sampling happens
.LoggerName( $sformatf("axi_logger_slave_%0d",i)),
.aw_chan_t ( aw_chan_slv_t ), // axi AW type
.w_chan_t ( w_chan_t ), // axi W type
.b_chan_t ( b_chan_slv_t ), // axi B type
.ar_chan_t ( ar_chan_slv_t ), // axi AR type
.r_chan_t ( r_chan_slv_t ) // axi R type
) i_slv_channel_logger (
.clk_i ( clk ), // Clock
.rst_ni ( rst_n ), // Asynchronous reset active low, when `1'b0` no sampling
.end_sim_i ( &end_of_sim ),
// AW channel
.aw_chan_i ( slaves_req[i].aw ),
.aw_valid_i ( slaves_req[i].aw_valid ),
.aw_ready_i ( slaves_resp[i].aw_ready ),
// W channel
.w_chan_i ( slaves_req[i].w ),
.w_valid_i ( slaves_req[i].w_valid ),
.w_ready_i ( slaves_resp[i].w_ready ),
// B channel
.b_chan_i ( slaves_resp[i].b ),
.b_valid_i ( slaves_resp[i].b_valid ),
.b_ready_i ( slaves_req[i].b_ready ),
// AR channel
.ar_chan_i ( slaves_req[i].ar ),
.ar_valid_i ( slaves_req[i].ar_valid ),
.ar_ready_i ( slaves_resp[i].ar_ready ),
// R channel
.r_chan_i ( slaves_resp[i].r ),
.r_valid_i ( slaves_resp[i].r_valid ),
.r_ready_i ( slaves_req[i].r_ready )
);
end
for (genvar i = 0; i < NoMasters; i++) begin : gen_connect_master_monitor
assign master_monitor_dv[i].aw_id = master[i].aw_id ;
assign master_monitor_dv[i].aw_addr = master[i].aw_addr ;
assign master_monitor_dv[i].aw_len = master[i].aw_len ;
assign master_monitor_dv[i].aw_size = master[i].aw_size ;
assign master_monitor_dv[i].aw_burst = master[i].aw_burst ;
assign master_monitor_dv[i].aw_lock = master[i].aw_lock ;
assign master_monitor_dv[i].aw_cache = master[i].aw_cache ;
assign master_monitor_dv[i].aw_prot = master[i].aw_prot ;
assign master_monitor_dv[i].aw_qos = master[i].aw_qos ;
assign master_monitor_dv[i].aw_region = master[i].aw_region;
assign master_monitor_dv[i].aw_atop = master[i].aw_atop ;
assign master_monitor_dv[i].aw_user = master[i].aw_user ;
assign master_monitor_dv[i].aw_valid = master[i].aw_valid ;
assign master_monitor_dv[i].aw_ready = master[i].aw_ready ;
assign master_monitor_dv[i].w_data = master[i].w_data ;
assign master_monitor_dv[i].w_strb = master[i].w_strb ;
assign master_monitor_dv[i].w_last = master[i].w_last ;
assign master_monitor_dv[i].w_user = master[i].w_user ;
assign master_monitor_dv[i].w_valid = master[i].w_valid ;
assign master_monitor_dv[i].w_ready = master[i].w_ready ;
assign master_monitor_dv[i].b_id = master[i].b_id ;
assign master_monitor_dv[i].b_resp = master[i].b_resp ;
assign master_monitor_dv[i].b_user = master[i].b_user ;
assign master_monitor_dv[i].b_valid = master[i].b_valid ;
assign master_monitor_dv[i].b_ready = master[i].b_ready ;
assign master_monitor_dv[i].ar_id = master[i].ar_id ;
assign master_monitor_dv[i].ar_addr = master[i].ar_addr ;
assign master_monitor_dv[i].ar_len = master[i].ar_len ;
assign master_monitor_dv[i].ar_size = master[i].ar_size ;
assign master_monitor_dv[i].ar_burst = master[i].ar_burst ;
assign master_monitor_dv[i].ar_lock = master[i].ar_lock ;
assign master_monitor_dv[i].ar_cache = master[i].ar_cache ;
assign master_monitor_dv[i].ar_prot = master[i].ar_prot ;
assign master_monitor_dv[i].ar_qos = master[i].ar_qos ;
assign master_monitor_dv[i].ar_region = master[i].ar_region;
assign master_monitor_dv[i].ar_user = master[i].ar_user ;
assign master_monitor_dv[i].ar_valid = master[i].ar_valid ;
assign master_monitor_dv[i].ar_ready = master[i].ar_ready ;
assign master_monitor_dv[i].r_id = master[i].r_id ;
assign master_monitor_dv[i].r_data = master[i].r_data ;
assign master_monitor_dv[i].r_resp = master[i].r_resp ;
assign master_monitor_dv[i].r_last = master[i].r_last ;
assign master_monitor_dv[i].r_user = master[i].r_user ;
assign master_monitor_dv[i].r_valid = master[i].r_valid ;
assign master_monitor_dv[i].r_ready = master[i].r_ready ;
end
for (genvar i = 0; i < NoSlaves; i++) begin : gen_connect_slave_monitor
assign slave_monitor_dv[i].aw_id = slave[i].aw_id ;
assign slave_monitor_dv[i].aw_addr = slave[i].aw_addr ;
assign slave_monitor_dv[i].aw_len = slave[i].aw_len ;
assign slave_monitor_dv[i].aw_size = slave[i].aw_size ;
assign slave_monitor_dv[i].aw_burst = slave[i].aw_burst ;
assign slave_monitor_dv[i].aw_lock = slave[i].aw_lock ;
assign slave_monitor_dv[i].aw_cache = slave[i].aw_cache ;
assign slave_monitor_dv[i].aw_prot = slave[i].aw_prot ;
assign slave_monitor_dv[i].aw_qos = slave[i].aw_qos ;
assign slave_monitor_dv[i].aw_region = slave[i].aw_region;
assign slave_monitor_dv[i].aw_atop = slave[i].aw_atop ;
assign slave_monitor_dv[i].aw_user = slave[i].aw_user ;
assign slave_monitor_dv[i].aw_valid = slave[i].aw_valid ;
assign slave_monitor_dv[i].aw_ready = slave[i].aw_ready ;
assign slave_monitor_dv[i].w_data = slave[i].w_data ;
assign slave_monitor_dv[i].w_strb = slave[i].w_strb ;
assign slave_monitor_dv[i].w_last = slave[i].w_last ;
assign slave_monitor_dv[i].w_user = slave[i].w_user ;
assign slave_monitor_dv[i].w_valid = slave[i].w_valid ;
assign slave_monitor_dv[i].w_ready = slave[i].w_ready ;
assign slave_monitor_dv[i].b_id = slave[i].b_id ;
assign slave_monitor_dv[i].b_resp = slave[i].b_resp ;
assign slave_monitor_dv[i].b_user = slave[i].b_user ;
assign slave_monitor_dv[i].b_valid = slave[i].b_valid ;
assign slave_monitor_dv[i].b_ready = slave[i].b_ready ;
assign slave_monitor_dv[i].ar_id = slave[i].ar_id ;
assign slave_monitor_dv[i].ar_addr = slave[i].ar_addr ;
assign slave_monitor_dv[i].ar_len = slave[i].ar_len ;
assign slave_monitor_dv[i].ar_size = slave[i].ar_size ;
assign slave_monitor_dv[i].ar_burst = slave[i].ar_burst ;
assign slave_monitor_dv[i].ar_lock = slave[i].ar_lock ;
assign slave_monitor_dv[i].ar_cache = slave[i].ar_cache ;
assign slave_monitor_dv[i].ar_prot = slave[i].ar_prot ;
assign slave_monitor_dv[i].ar_qos = slave[i].ar_qos ;
assign slave_monitor_dv[i].ar_region = slave[i].ar_region;
assign slave_monitor_dv[i].ar_user = slave[i].ar_user ;
assign slave_monitor_dv[i].ar_valid = slave[i].ar_valid ;
assign slave_monitor_dv[i].ar_ready = slave[i].ar_ready ;
assign slave_monitor_dv[i].r_id = slave[i].r_id ;
assign slave_monitor_dv[i].r_data = slave[i].r_data ;
assign slave_monitor_dv[i].r_resp = slave[i].r_resp ;
assign slave_monitor_dv[i].r_last = slave[i].r_last ;
assign slave_monitor_dv[i].r_user = slave[i].r_user ;
assign slave_monitor_dv[i].r_valid = slave[i].r_valid ;
assign slave_monitor_dv[i].r_ready = slave[i].r_ready ;
end
endmodule |
module tb_axi_modify_address #(
// DUT Parameters
parameter int unsigned AXI_SLV_PORT_ADDR_WIDTH = 32,
parameter int unsigned AXI_MST_PORT_ADDR_WIDTH = 48,
parameter int unsigned AXI_DATA_WIDTH = 64,
parameter int unsigned AXI_ID_WIDTH = 3,
parameter int unsigned AXI_USER_WIDTH = 2,
// TB Parameters
parameter time TCLK = 10ns,
parameter time TA = TCLK * 1/4,
parameter time TT = TCLK * 3/4,
parameter int unsigned REQ_MIN_WAIT_CYCLES = 0,
parameter int unsigned REQ_MAX_WAIT_CYCLES = 10,
parameter int unsigned RESP_MIN_WAIT_CYCLES = 0,
parameter int unsigned RESP_MAX_WAIT_CYCLES = REQ_MAX_WAIT_CYCLES/2,
parameter int unsigned N_TXNS = 1000
);
localparam int unsigned N_RD_TXNS = N_TXNS / 2;
localparam int unsigned N_WR_TXNS = N_TXNS / 2;
// Clock and Reset
logic clk,
rst_n;
clk_rst_gen #(
.ClkPeriod (TCLK),
.RstClkCycles (5)
) i_clk_rst_gen (
.clk_o (clk),
.rst_no (rst_n)
);
// AXI Interfaces
AXI_BUS_DV #(
.AXI_ADDR_WIDTH (AXI_SLV_PORT_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) upstream_dv (
.clk_i (clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH (AXI_SLV_PORT_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) upstream ();
`AXI_ASSIGN(upstream, upstream_dv)
AXI_BUS_DV #(
.AXI_ADDR_WIDTH (AXI_MST_PORT_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) downstream_dv (
.clk_i (clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH (AXI_MST_PORT_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) downstream ();
`AXI_ASSIGN(downstream_dv, downstream)
// Types
typedef logic [AXI_MST_PORT_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_MST_PORT_ADDR_WIDTH-13:0] page_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t)
// DUT
addr_t mst_aw_addr,
mst_ar_addr;
axi_modify_address_intf #(
.AXI_SLV_PORT_ADDR_WIDTH (AXI_SLV_PORT_ADDR_WIDTH),
.AXI_MST_PORT_ADDR_WIDTH (AXI_MST_PORT_ADDR_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ID_WIDTH (AXI_ID_WIDTH),
.AXI_USER_WIDTH (AXI_USER_WIDTH)
) i_dut (
.slv (upstream),
.mst_aw_addr_i (mst_aw_addr),
.mst_ar_addr_i (mst_ar_addr),
.mst (downstream)
);
// Test harness master
typedef axi_test::axi_rand_master #(
.AW (AXI_SLV_PORT_ADDR_WIDTH),
.DW (AXI_DATA_WIDTH),
.IW (AXI_ID_WIDTH),
.UW (AXI_USER_WIDTH),
.TA (TA),
.TT (TT),
.MAX_READ_TXNS (N_TXNS),
.MAX_WRITE_TXNS (N_TXNS),
.AX_MIN_WAIT_CYCLES (REQ_MIN_WAIT_CYCLES),
.AX_MAX_WAIT_CYCLES (REQ_MAX_WAIT_CYCLES),
.W_MIN_WAIT_CYCLES (REQ_MIN_WAIT_CYCLES),
.W_MAX_WAIT_CYCLES (REQ_MAX_WAIT_CYCLES),
.RESP_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES),
.RESP_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES),
.AXI_MAX_BURST_LEN (16)
) axi_master_t;
axi_master_t axi_master = new(upstream_dv);
initial begin
wait (rst_n);
axi_master.run(N_RD_TXNS, N_WR_TXNS);
#(10*TCLK);
$finish();
end
// Test harness slave
typedef axi_test::axi_rand_slave #(
.AW (AXI_MST_PORT_ADDR_WIDTH),
.DW (AXI_DATA_WIDTH),
.IW (AXI_ID_WIDTH),
.UW (AXI_USER_WIDTH),
.TA (TA),
.TT (TT),
.AX_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES),
.AX_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES),
.R_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES),
.R_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES),
.RESP_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES),
.RESP_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES)
) axi_slave_t;
axi_slave_t axi_slave = new(downstream_dv);
initial begin
wait (rst_n);
axi_slave.run();
end
// Assign offset within page from upstream.
assign mst_aw_addr[11:0] = upstream.aw_addr[11:0];
assign mst_ar_addr[11:0] = upstream.ar_addr[11:0];
// Randomize page number.
page_t mst_aw_page,
mst_ar_page;
assign mst_aw_addr[AXI_MST_PORT_ADDR_WIDTH-1:12] = mst_aw_page;
assign mst_ar_addr[AXI_MST_PORT_ADDR_WIDTH-1:12] = mst_ar_page;
initial begin
logic rand_success;
mst_aw_page = '0;
mst_ar_page = '0;
wait (rst_n);
forever begin
@(posedge clk);
#TA;
if (!(upstream.aw_valid && !upstream.aw_ready)) begin
rand_success = std::randomize(mst_aw_page);
assert(rand_success);
end
if (!(upstream.ar_valid && !upstream.ar_ready)) begin
rand_success = std::randomize(mst_ar_page);
assert(rand_success);
end
end
end
// Signals for expected and actual responses
aw_t aw_exp, aw_act;
w_t w_exp, w_act;
b_t b_exp, b_act;
ar_t ar_exp, ar_act;
r_t r_exp, r_act;
// Compute expected responses.
always_comb begin
`AXI_SET_TO_AW(aw_exp, upstream)
aw_exp.addr = mst_aw_addr;
`AXI_SET_TO_AR(ar_exp, upstream)
ar_exp.addr = mst_ar_addr;
end
`AXI_ASSIGN_TO_W(w_exp, upstream)
`AXI_ASSIGN_TO_B(b_exp, downstream)
`AXI_ASSIGN_TO_R(r_exp, downstream)
// Determine actual responses.
`AXI_ASSIGN_TO_AW(aw_act, downstream)
`AXI_ASSIGN_TO_W(w_act, downstream)
`AXI_ASSIGN_TO_B(b_act, upstream)
`AXI_ASSIGN_TO_AR(ar_act, downstream)
`AXI_ASSIGN_TO_R(r_act, upstream)
// Assert that actual responses match expected responses.
default disable iff (~rst_n);
aw: assert property(@(posedge clk)
downstream.aw_valid |-> aw_act == aw_exp
) else $error("AW %p != %p!", aw_act, aw_exp);
w: assert property(@(posedge clk)
downstream.w_valid |-> w_act == w_exp
) else $error("W %p != %p!", w_act, w_exp);
b: assert property(@(posedge clk)
upstream.b_valid |-> b_act == b_exp
) else $error("B %p != %p!", b_act, b_exp);
ar: assert property(@(posedge clk)
downstream.ar_valid |-> ar_act == ar_exp
) else $error("AR %p != %p!", ar_act, ar_exp);
r: assert property(@(posedge clk)
upstream.r_valid |-> r_act == r_exp
) else $error("R %p != %p!", r_act, r_exp);
endmodule |
module tb_axi_isolate #(
parameter int unsigned NoWrites = 50000, // How many writes per master
parameter int unsigned NoReads = 30000 // How many reads per master
);
// Random master no Transactions
localparam int unsigned NoPendingDut = 16;
// Random Master Atomics
localparam int unsigned MaxAW = 32'd30;
localparam int unsigned MaxAR = 32'd30;
localparam bit EnAtop = 1'b1;
// timing parameters
localparam time CyclTime = 10ns;
localparam time ApplTime = 2ns;
localparam time TestTime = 8ns;
// AXI configuration
localparam int unsigned AxiIdWidth = 4;
localparam int unsigned AxiAddrWidth = 32; // Axi Address Width
localparam int unsigned AxiDataWidth = 64; // Axi Data Width
localparam int unsigned AxiUserWidth = 5;
// Sim print config, how many transactions
localparam int unsigned PrintTnx = 1000;
typedef axi_test::axi_rand_master #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
.IW ( AxiIdWidth ),
.UW ( AxiUserWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime ),
// Maximum number of read and write transactions in flight
.MAX_READ_TXNS ( MaxAR ),
.MAX_WRITE_TXNS ( MaxAW ),
.AXI_ATOPS ( EnAtop )
) axi_rand_master_t;
typedef axi_test::axi_rand_slave #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
.IW ( AxiIdWidth ),
.UW ( AxiUserWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime )
) axi_rand_slave_t;
// -------------
// DUT signals
// -------------
logic clk;
logic rst_n;
logic end_of_sim;
// DUT signals
logic isolate, isolated;
// interfaces
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master ();
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master_dv (clk);
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave ();
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave_dv (clk);
`AXI_ASSIGN ( master, master_dv )
`AXI_ASSIGN ( slave_dv, slave )
//-----------------------------------
// Clock generator
//-----------------------------------
clk_rst_gen #(
.ClkPeriod ( CyclTime ),
.RstClkCycles ( 5 )
) i_clk_gen (
.clk_o (clk),
.rst_no(rst_n)
);
//-----------------------------------
// DUT
//-----------------------------------
axi_isolate_intf #(
.NUM_PENDING ( NoPendingDut ), // number of pending requests
.AXI_ID_WIDTH ( AxiIdWidth ), // AXI ID width
.AXI_ADDR_WIDTH ( AxiAddrWidth ), // AXI address width
.AXI_DATA_WIDTH ( AxiDataWidth ), // AXI data width
.AXI_USER_WIDTH ( AxiUserWidth ) // AXI user width
) i_dut (
.clk_i ( clk ), // clock
.rst_ni ( rst_n ), // asynchronous reset active low
.slv ( master ), // slave port
.mst ( slave ), // master port
.isolate_i ( isolate ), // isolate master port from slave port
.isolated_o ( isolated ) // master port is isolated from slave port
);
initial begin : proc_axi_master
automatic axi_rand_master_t axi_rand_master = new(master_dv);
end_of_sim <= 1'b0;
axi_rand_master.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE);
axi_rand_master.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE);
axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE);
axi_rand_master.reset();
@(posedge rst_n);
axi_rand_master.run(NoReads, NoWrites);
end_of_sim <= 1'b1;
repeat (10000) @(posedge clk);
$stop();
end
initial begin : proc_axi_slave
automatic axi_rand_slave_t axi_rand_slave = new(slave_dv);
axi_rand_slave.reset();
@(posedge rst_n);
axi_rand_slave.run();
end
initial begin : proc_sim_ctl
forever begin
isolate <= 1'b0;
repeat ($urandom_range(100000,1)) @(posedge clk);
isolate <= 1'b1;
repeat ($urandom_range(100000,1)) @(posedge clk);
end
end
initial begin : proc_sim_progress
automatic int unsigned aw = 0;
automatic int unsigned ar = 0;
automatic bit aw_printed = 1'b0;
automatic bit ar_printed = 1'b0;
@(posedge rst_n);
forever begin
@(posedge clk);
#TestTime;
if (master.aw_valid && master.aw_ready) begin
aw++;
end
if (master.ar_valid && master.ar_ready) begin
ar++;
end
if ((aw % PrintTnx == 0) && ! aw_printed) begin
$display("%t> Transmit AW %d of %d.", $time(), aw, NoWrites);
aw_printed = 1'b1;
end
if ((ar % PrintTnx == 0) && !ar_printed) begin
$display("%t> Transmit AR %d of %d.", $time(), ar, NoReads);
ar_printed = 1'b1;
end
if (aw % PrintTnx == 1) begin
aw_printed = 1'b0;
end
if (ar % PrintTnx == 1) begin
ar_printed = 1'b0;
end
if (end_of_sim) begin
$info("All transactions completed.");
break;
end
end
end
default disable iff (!rst_n);
aw_unstable: assert property (@(posedge clk)
(slave.aw_valid && !slave.aw_ready) |=> $stable(slave.aw_addr)) else
$fatal(1, "AW is unstable.");
w_unstable: assert property (@(posedge clk)
(slave.w_valid && !slave.w_ready) |=> $stable(slave.w_data)) else
$fatal(1, "W is unstable.");
b_unstable: assert property (@(posedge clk)
(master.b_valid && !master.b_ready) |=> $stable(master.b_resp)) else
$fatal(1, "B is unstable.");
ar_unstable: assert property (@(posedge clk)
(slave.ar_valid && !slave.ar_ready) |=> $stable(slave.ar_addr)) else
$fatal(1, "AR is unstable.");
r_unstable: assert property (@(posedge clk)
(master.r_valid && !master.r_ready) |=> $stable(master.r_data)) else
$fatal(1, "R is unstable.");
endmodule |
module tb_axi_to_axi_lite;
parameter AW = 32;
parameter DW = 32;
parameter IW = 8;
parameter UW = 8;
localparam tCK = 1ns;
localparam TA = tCK * 1/4;
localparam TT = tCK * 3/4;
localparam MAX_READ_TXNS = 32'd20;
localparam MAX_WRITE_TXNS = 32'd20;
localparam bit AXI_ATOPS = 1'b1;
logic clk = 0;
logic rst = 1;
logic done = 0;
AXI_LITE_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) axi_lite_dv(clk);
AXI_LITE #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) axi_lite();
`AXI_LITE_ASSIGN(axi_lite_dv, axi_lite)
AXI_BUS_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi_dv(clk);
AXI_BUS #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi();
`AXI_ASSIGN(axi, axi_dv)
axi_to_axi_lite_intf #(
.AXI_ID_WIDTH ( IW ),
.AXI_ADDR_WIDTH ( AW ),
.AXI_DATA_WIDTH ( DW ),
.AXI_USER_WIDTH ( UW ),
.AXI_MAX_WRITE_TXNS ( 32'd10 ),
.AXI_MAX_READ_TXNS ( 32'd10 ),
.FALL_THROUGH ( 1'b1 )
) i_dut (
.clk_i ( clk ),
.rst_ni ( rst ),
.testmode_i ( 1'b0 ),
.slv ( axi ),
.mst ( axi_lite )
);
typedef axi_test::axi_rand_master #(
// AXI interface parameters
.AW ( AW ),
.DW ( DW ),
.IW ( IW ),
.UW ( UW ),
// Stimuli application and test time
.TA ( TA ),
.TT ( TT ),
// Maximum number of read and write transactions in flight
.MAX_READ_TXNS ( MAX_READ_TXNS ),
.MAX_WRITE_TXNS ( MAX_WRITE_TXNS ),
.AXI_ATOPS ( AXI_ATOPS )
) axi_rand_master_t;
typedef axi_test::axi_lite_rand_slave #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)) axi_lite_rand_slv_t;
axi_lite_rand_slv_t axi_lite_drv = new(axi_lite_dv, "axi_lite_rand_slave");
axi_rand_master_t axi_drv = new(axi_dv);
initial begin
#tCK;
rst <= 0;
#tCK;
rst <= 1;
#tCK;
while (!done) begin
clk <= 1;
#(tCK/2);
clk <= 0;
#(tCK/2);
end
end
initial begin
axi_drv.add_memory_region(32'h0000_0000,
32'h1000_0000,
axi_pkg::NORMAL_NONCACHEABLE_NONBUFFERABLE);
axi_drv.add_memory_region(32'h1000_0000,
32'h2000_0000,
axi_pkg::NORMAL_NONCACHEABLE_BUFFERABLE);
axi_drv.add_memory_region(32'h3000_0000,
32'h4000_0000,
axi_pkg::WBACK_RWALLOCATE);
axi_drv.reset();
@(posedge rst);
axi_drv.run(1000, 2000);
repeat (4) @(posedge clk);
done = 1'b1;
$info("All AXI4+ATOP Bursts converted to AXI4-Lite");
repeat (4) @(posedge clk);
$stop();
end
initial begin
axi_lite_drv.reset();
@(posedge clk);
axi_lite_drv.run();
end
initial begin : proc_count_lite_beats
automatic longint aw_cnt = 0;
automatic longint w_cnt = 0;
automatic longint b_cnt = 0;
automatic longint ar_cnt = 0;
automatic longint r_cnt = 0;
@(posedge rst);
while (!done) begin
@(posedge clk);
#TT;
if (axi_lite.aw_valid && axi_lite.aw_ready) begin
aw_cnt++;
end
if (axi_lite.w_valid && axi_lite.w_ready) begin
w_cnt++;
end
if (axi_lite.b_valid && axi_lite.b_ready) begin
b_cnt++;
end
if (axi_lite.ar_valid && axi_lite.ar_ready) begin
ar_cnt++;
end
if (axi_lite.r_valid && axi_lite.r_ready) begin
r_cnt++;
end
end
assert (aw_cnt == w_cnt && w_cnt == b_cnt);
assert (ar_cnt == r_cnt);
$display("AXI4-Lite AW count: %0d", aw_cnt );
$display("AXI4-Lite W count: %0d", w_cnt );
$display("AXI4-Lite B count: %0d", b_cnt );
$display("AXI4-Lite AR count: %0d", ar_cnt );
$display("AXI4-Lite R count: %0d", r_cnt );
end
endmodule |
module tb_axi_dw_downsizer #(
// AXI Parameters
parameter int unsigned TbAxiAddrWidth = 64 ,
parameter int unsigned TbAxiIdWidth = 4 ,
parameter int unsigned TbAxiSlvPortDataWidth = 64 ,
parameter int unsigned TbAxiMstPortDataWidth = 32 ,
parameter int unsigned TbAxiUserWidth = 8 ,
// TB Parameters
parameter time TbCyclTime = 10ns,
parameter time TbApplTime = 2ns ,
parameter time TbTestTime = 8ns
);
/*********************
* CLOCK GENERATOR *
*********************/
logic clk;
logic rst_n;
logic eos;
clk_rst_gen #(
.ClkPeriod (TbCyclTime),
.RstClkCycles (5 )
) i_clk_rst_gen (
.clk_o (clk ),
.rst_no(rst_n)
);
/*********
* AXI *
*********/
// Master port
AXI_BUS_DV #(
.AXI_ADDR_WIDTH(TbAxiAddrWidth ),
.AXI_DATA_WIDTH(TbAxiSlvPortDataWidth),
.AXI_ID_WIDTH (TbAxiIdWidth ),
.AXI_USER_WIDTH(TbAxiUserWidth )
) master_dv (
.clk_i(clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH(TbAxiAddrWidth ),
.AXI_DATA_WIDTH(TbAxiSlvPortDataWidth),
.AXI_ID_WIDTH (TbAxiIdWidth ),
.AXI_USER_WIDTH(TbAxiUserWidth )
) master ();
`AXI_ASSIGN(master, master_dv)
axi_test::axi_rand_master #(
.AW (TbAxiAddrWidth ),
.DW (TbAxiSlvPortDataWidth),
.IW (TbAxiIdWidth ),
.UW (TbAxiUserWidth ),
.TA (TbApplTime ),
.TT (TbTestTime ),
.MAX_READ_TXNS (8 ),
.MAX_WRITE_TXNS (8 ),
.AXI_BURST_FIXED(1'b0 ),
.AXI_ATOPS (1'b1 )
) master_drv = new (master_dv);
// Slave port
AXI_BUS_DV #(
.AXI_ADDR_WIDTH(TbAxiAddrWidth ),
.AXI_DATA_WIDTH(TbAxiMstPortDataWidth),
.AXI_ID_WIDTH (TbAxiIdWidth ),
.AXI_USER_WIDTH(TbAxiUserWidth )
) slave_dv (
.clk_i(clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH(TbAxiAddrWidth ),
.AXI_DATA_WIDTH(TbAxiMstPortDataWidth),
.AXI_ID_WIDTH (TbAxiIdWidth ),
.AXI_USER_WIDTH(TbAxiUserWidth )
) slave ();
axi_test::axi_rand_slave #(
.AW(TbAxiAddrWidth ),
.DW(TbAxiMstPortDataWidth),
.IW(TbAxiIdWidth ),
.UW(TbAxiUserWidth ),
.TA(TbApplTime ),
.TT(TbTestTime )
) slave_drv = new (slave_dv);
`AXI_ASSIGN(slave_dv, slave)
/*********
* DUT *
*********/
axi_dw_converter_intf #(
.AXI_MAX_READS (4 ),
.AXI_ADDR_WIDTH (TbAxiAddrWidth ),
.AXI_ID_WIDTH (TbAxiIdWidth ),
.AXI_SLV_PORT_DATA_WIDTH(TbAxiSlvPortDataWidth),
.AXI_MST_PORT_DATA_WIDTH(TbAxiMstPortDataWidth),
.AXI_USER_WIDTH (TbAxiUserWidth )
) i_dw_converter (
.clk_i (clk ),
.rst_ni(rst_n ),
.slv (master),
.mst (slave )
);
/*************
* DRIVERS *
*************/
initial begin
eos = 1'b0;
// Configuration
slave_drv.reset() ;
master_drv.reset() ;
master_drv.add_memory_region({TbAxiAddrWidth{1'b0}}, {TbAxiAddrWidth{1'b1}}, axi_pkg::WTHRU_NOALLOCATE);
// Wait for the reset before sending requests
@(posedge rst_n);
fork
// Act as a sink
slave_drv.run() ;
master_drv.run(200, 200);
join_any
// Done
repeat (10) @(posedge clk);
eos = 1'b1;
end
/*************
* MONITOR *
*************/
initial begin : proc_monitor
static tb_axi_dw_pkg::axi_dw_downsizer_monitor #(
.AxiAddrWidth (TbAxiAddrWidth ),
.AxiMstPortDataWidth(TbAxiMstPortDataWidth),
.AxiSlvPortDataWidth(TbAxiSlvPortDataWidth),
.AxiIdWidth (TbAxiIdWidth ),
.AxiUserWidth (TbAxiUserWidth ),
.TimeTest (TbTestTime )
) monitor = new (master_dv, slave_dv);
fork
monitor.run();
forever begin
#TbTestTime;
if(eos) begin
monitor.print_result();
$stop() ;
end
@(posedge clk);
end
join
end
// vsim -voptargs=+acc work.tb_axi_dw_downsizer
endmodule : tb_axi_dw_downsizer |
module tb_axi_lite_mailbox;
// timing parameters
localparam time CyclTime = 10ns;
localparam time ApplTime = 2ns;
localparam time TestTime = 8ns;
// axi configuration
localparam int unsigned AxiAddrWidth = 32'd32; // Axi Address Width
localparam int unsigned AxiDataWidth = 32'd64; // Axi Data Width
// mailbox params
localparam int unsigned MailboxDepth = 32'd16;
typedef logic [AxiAddrWidth-1:0] addr_t; // for sign extension
typedef logic [AxiDataWidth-1:0] data_t; // for sign extension
typedef enum addr_t {
MBOXW = addr_t'(0 * AxiDataWidth/8),
MBOXR = addr_t'(1 * AxiDataWidth/8),
STATUS = addr_t'(2 * AxiDataWidth/8),
ERROR = addr_t'(3 * AxiDataWidth/8),
WIRQT = addr_t'(4 * AxiDataWidth/8),
RIRQT = addr_t'(5 * AxiDataWidth/8),
IRQS = addr_t'(6 * AxiDataWidth/8),
IRQEN = addr_t'(7 * AxiDataWidth/8),
IRQP = addr_t'(8 * AxiDataWidth/8),
CTRL = addr_t'(9 * AxiDataWidth/8)
} reg_addr_e;
typedef axi_test::axi_lite_rand_master #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime ),
.MIN_ADDR ( 32'h0000_0000 ),
.MAX_ADDR ( 32'h0001_3000 ),
.MAX_READ_TXNS ( 10 ),
.MAX_WRITE_TXNS ( 10 )
) rand_lite_master_t;
// -------------
// DUT signals
// -------------
logic clk;
// DUT signals
logic rst_n;
logic [1:0] end_of_sim;
logic [1:0] irq;
int unsigned test_failed [1:0];
// -------------------------------
// AXI Interfaces
// -------------------------------
AXI_LITE #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) master [1:0] ();
AXI_LITE_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) master_dv [1:0] (clk);
for (genvar i = 0; i < 2; i++) begin : gen_conn_dv_masters
`AXI_LITE_ASSIGN(master[i], master_dv[i])
end
// Masters control simulation run time
initial begin : proc_master_0
automatic rand_lite_master_t lite_axi_master = new ( master_dv[0], "MST_0");
automatic data_t data = '0;
automatic axi_pkg::resp_t resp = axi_pkg::RESP_SLVERR;
// automatic int unsigned test_failed[0] = 0;
automatic int unsigned loop = 0;
end_of_sim[0] <= 1'b0;
lite_axi_master.reset();
@(posedge rst_n);
// -------------------------------
// Read all registers anf compare their results
// -------------------------------
$info("Initial test by reading each register");
$display("%0t MST_0> Read register MBOXW ", $time());
lite_axi_master.read(MBOXW, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(32'hFEEDC0DE)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register MBOXR, this generates an error ", $time());
lite_axi_master.read(MBOXR, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(32'hFEEDDEAD)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register STATUS", $time());
lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(1)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register ERROR ", $time());
lite_axi_master.read(ERROR, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(1)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register WIRQT ", $time());
lite_axi_master.read(WIRQT, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register RIRQT ", $time());
lite_axi_master.read(RIRQT, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register IRQS ", $time());
lite_axi_master.read(IRQS, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(3'b100)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Acknowledge Error by writing to IRQS", $time());
lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), 64'h4, 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register IRQEN ", $time());
lite_axi_master.read(IRQEN, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register IRQP ", $time());
lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register CTRL ", $time());
lite_axi_master.read(CTRL, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(0)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
// -------------------------------
// Test Read error interrupt on port 0
// -------------------------------
repeat (50) @(posedge clk);
$info("Test error interrupt");
$display("%0t MST_0> Enable Error interrupt ", $time());
lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register MBOXR, this generates an error ", $time());
lite_axi_master.read(MBOXR, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(32'hFEEDDEAD)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read register ERROR ", $time());
lite_axi_master.read(ERROR, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(1)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Acknowledge Error by writing to IRQS", $time());
lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Disable interrupt", $time());
lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
// -------------------------------
// Send data to the other port, and enable interrupt for recieving
// -------------------------------
repeat (50) @(posedge clk);
$info("Test sending data from one to the other slave interface");
$display("%0t MST_0> Set write threshold to 100, truncates to depth ", $time());
lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), 64'd100, 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read out write threshold ", $time());
lite_axi_master.read(WIRQT, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(MailboxDepth - 1)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Set write threshold to 0", $time());
lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), 64'd0, 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Set Read threshold to 100, truncates to depth ", $time());
lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), 64'd100, 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Read out read threshold ", $time());
lite_axi_master.read(RIRQT, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(MailboxDepth - 1)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Set Read threshold to 64'd2 ", $time());
lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), 64'd2, 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Enable Read threshold interrupt ", $time());
lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), 64'h2, 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> Send to slave 1 data ", $time());
lite_axi_master.write(MBOXW, axi_pkg::prot_t'('0), data_t'(32'hFEEDFEED), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
// wait for interrupt
wait (irq[0]);
$display("%0t MST_0> interrupt recieved, test that it is the expected one ", $time());
lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(3'b010)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(4'b1000)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
$display("%0t MST_0> empty data from port ", $time());
while (!data[0]) begin
lite_axi_master.read(MBOXR, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(loop)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
loop ++;
lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp);
end
$display("%0t MST_0> FIFO is now empty, clear interrupt and disable it ", $time());
lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b111), 8'hFF, resp);
lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp);
lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp);
// -------------------------------
// Test Flush
// -------------------------------
repeat (50) @(posedge clk);
$info("%0t MST_0> Test Flush all FIFOs ", $time());
lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'('1), 8'h00, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'('1), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
// -------------------------------
// Fill the write FIFO, until write error interrupt, then flush and clear interrupt
// -------------------------------
repeat (50) @(posedge clk);
$info("%0t MST_0> Test Write error interrupt ", $time());
lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp);
loop = 0;
while (!irq[0]) begin
lite_axi_master.write(MBOXW, axi_pkg::prot_t'('0), data_t'(loop), 8'hFF, resp);
end
lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(3'b100)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.read(ERROR, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(2'b10)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'(2'b01), 8'h01, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b111), 8'h01, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(4'b0001)) else begin test_failed[0]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
// -------------------------------
// Make an unmapped read and write access
// -------------------------------
repeat (50) @(posedge clk);
$info("%0t MST_0> Make an unmapped access read and write ", $time());
lite_axi_master.read(addr_t'(16'hDEAD), axi_pkg::prot_t'('0), data, resp);
assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(addr_t'(16'hDEAD), axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'hFF, resp);
assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(ERROR, axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'hFF, resp);
assert (resp == axi_pkg::RESP_SLVERR) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'h00, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(16'hDEAD), 8'h00, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'h00, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), data_t'('0), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'h00, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), data_t'('1), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), data_t'('0), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end
end_of_sim[0] <= 1'b1;
end
initial begin : proc_master_1
automatic rand_lite_master_t lite_axi_master = new ( master_dv[1], "MST_1");
//automatic int unsigned test_failed = 0;
automatic data_t data = '0;
automatic axi_pkg::resp_t resp = axi_pkg::RESP_SLVERR;
automatic int unsigned loop = 0;
end_of_sim[1] <= 1'b0;
lite_axi_master.reset();
@(posedge rst_n);
// -------------------------------
// Test Flush seperately
// -------------------------------
$display("%0t MST_1> Flush Read MBOX ", $time());
lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'(2'b10), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
$display("%0t MST_1> Flush Write MBOX ", $time());
lite_axi_master.write(CTRL, axi_pkg::prot_t'('0), data_t'(2'b01), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
// -------------------------------
// Set read and write thresholds, wait for reflect some data
// -------------------------------
$display("%0t MST_1> Set Read threshold to 64'd0 ", $time());
lite_axi_master.write(RIRQT, axi_pkg::prot_t'('0), data_t'(0), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
$display("%0t MST_1> Enable Read threshold interrupt ", $time());
lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(2), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
$display("%0t MST_1> Wait for Read threshold interrupt ", $time());
wait (irq[1]);
$display("%0t MST_1> Interrupt Recieved, read pending register and Acknowledge irq ", $time());
lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(2)) else begin test_failed[1]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
lite_axi_master.read(IRQS, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(2)) else begin test_failed[1]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
lite_axi_master.read(MBOXR, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(32'hFEEDFEED)) else begin test_failed[1]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(2), 8'h1, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
$display("%0t MST_1> Enable write threshold interrupt ", $time());
lite_axi_master.write(WIRQT, axi_pkg::prot_t'('0), 32'h8, 8'h1, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(1), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
$display("%0t MST_1> Write back looping answer ", $time());
while (!irq[1]) begin
lite_axi_master.write(MBOXW, axi_pkg::prot_t'('0), data_t'(loop), 8'hFF, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
loop++;
end
$display("%0t MST_1> Stop looping answer and clear interrupt", $time());
lite_axi_master.read(IRQP, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(1)) else begin test_failed[1]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
lite_axi_master.read(IRQS, axi_pkg::prot_t'('0), data, resp);
assert (data == data_t'(1)) else begin test_failed[1]++; $error("Unexpected result"); end
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
// clear the interrupt, if the Write FIFO is status reg is below threshold
lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp);
while (data[3]) begin
repeat (10) @(posedge clk);
lite_axi_master.read(STATUS, axi_pkg::prot_t'('0), data, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
end
lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(2), 8'h1, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(0), 8'h1, resp);
assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[1]++; $error("Unexpected result"); end
end_of_sim[1] <= 1'b1;
end
initial begin : proc_monitor_irq_0
forever begin
@(posedge irq[0]);
$info("Recieved interrupt from slave port 0");
end
end
initial begin : proc_monitor_irq_1
forever begin
@(posedge irq[1]);
$info("Recieved interrupt from slave port 1");
end
end
initial begin : proc_stop_sim
wait (&end_of_sim);
repeat (50) @(posedge clk);
$display("Slave port 0 failed tests: %0d", test_failed[0]);
$display("Slave port 1 failed tests: %0d", test_failed[1]);
if (test_failed[0] > 0 || test_failed[1] > 0) begin
$fatal(1, "Simulation stopped as assertion errors have been encountered, Failure!!!");
end else begin
$info("Simulation stopped as all Masters transferred their data, Success.",);
end
$stop();
end
//-----------------------------------
// Clock generator
//-----------------------------------
clk_rst_gen #(
.ClkPeriod ( CyclTime ),
.RstClkCycles ( 5 )
) i_clk_gen (
.clk_o (clk),
.rst_no(rst_n)
);
//-----------------------------------
// DUT
//-----------------------------------
axi_lite_mailbox_intf #(
.MAILBOX_DEPTH ( MailboxDepth ),
.IRQ_EDGE_TRIG ( 1'b0 ),
.IRQ_ACT_HIGH ( 1'b1 ),
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) i_mailbox_dut (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_i ( 1'b0 ),
.slv ( master ),
.irq_o ( irq ),
.base_addr_i ( '0 ) // set base address to '0
);
endmodule |
module tb_axi_atop_filter #(
// AXI Parameters
parameter int unsigned TB_AXI_ADDR_WIDTH = 32,
parameter int unsigned TB_AXI_DATA_WIDTH = 64,
parameter int unsigned TB_AXI_ID_WIDTH = 4,
parameter int unsigned TB_AXI_USER_WIDTH = 2,
parameter int unsigned TB_AXI_MAX_READ_TXNS = 10,
parameter int unsigned TB_AXI_MAX_WRITE_TXNS = 12,
// TB Parameters
parameter time TB_TCLK = 10ns,
parameter time TB_TA = TB_TCLK * 1/4,
parameter time TB_TT = TB_TCLK * 3/4,
parameter int unsigned TB_REQ_MIN_WAIT_CYCLES = 0,
parameter int unsigned TB_REQ_MAX_WAIT_CYCLES = 10,
parameter int unsigned TB_RESP_MIN_WAIT_CYCLES = 0,
parameter int unsigned TB_RESP_MAX_WAIT_CYCLES = TB_REQ_MAX_WAIT_CYCLES/2,
parameter int unsigned TB_N_TXNS = 1000
);
import axi_pkg::ATOP_ATOMICCMP;
import axi_pkg::ATOP_ATOMICLOAD;
import axi_pkg::ATOP_ATOMICSTORE;
import axi_pkg::BURST_FIXED;
import axi_pkg::BURST_INCR;
import axi_pkg::BURST_WRAP;
import axi_pkg::RESP_OKAY;
import axi_pkg::RESP_SLVERR;
import rand_id_queue_pkg::rand_id_queue;
import rand_verif_pkg::rand_wait;
localparam int unsigned AXI_STRB_WIDTH = TB_AXI_DATA_WIDTH / 8;
localparam int unsigned NUM_AXI_IDS = 2**TB_AXI_ID_WIDTH;
logic clk,
rst_n;
clk_rst_gen #(
.ClkPeriod (TB_TCLK),
.RstClkCycles (5)
) i_clk_rst_gen (
.clk_o (clk),
.rst_no (rst_n)
);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH (TB_AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (TB_AXI_DATA_WIDTH),
.AXI_ID_WIDTH (TB_AXI_ID_WIDTH),
.AXI_USER_WIDTH (TB_AXI_USER_WIDTH)
) upstream_dv (
.clk_i (clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH (TB_AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (TB_AXI_DATA_WIDTH),
.AXI_ID_WIDTH (TB_AXI_ID_WIDTH),
.AXI_USER_WIDTH (TB_AXI_USER_WIDTH)
) upstream ();
`AXI_ASSIGN(upstream, upstream_dv)
AXI_BUS_DV #(
.AXI_ADDR_WIDTH (TB_AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (TB_AXI_DATA_WIDTH),
.AXI_ID_WIDTH (TB_AXI_ID_WIDTH),
.AXI_USER_WIDTH (TB_AXI_USER_WIDTH)
) downstream_dv (
.clk_i (clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH (TB_AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (TB_AXI_DATA_WIDTH),
.AXI_ID_WIDTH (TB_AXI_ID_WIDTH),
.AXI_USER_WIDTH (TB_AXI_USER_WIDTH)
) downstream ();
`AXI_ASSIGN(downstream_dv, downstream)
axi_atop_filter_intf #(
.AXI_ID_WIDTH (TB_AXI_ID_WIDTH),
.AXI_MAX_WRITE_TXNS (TB_AXI_MAX_WRITE_TXNS),
.AXI_ADDR_WIDTH (TB_AXI_ADDR_WIDTH),
.AXI_DATA_WIDTH (TB_AXI_DATA_WIDTH),
.AXI_USER_WIDTH (TB_AXI_USER_WIDTH)
) dut (
.clk_i (clk),
.rst_ni (rst_n),
.slv (upstream),
.mst (downstream)
);
typedef logic [TB_AXI_ID_WIDTH-1:0] axi_id_t;
// AXI Master
logic mst_done = 1'b0;
axi_test::axi_rand_master #(
.AW(TB_AXI_ADDR_WIDTH), .DW(TB_AXI_DATA_WIDTH), .IW(TB_AXI_ID_WIDTH), .UW(TB_AXI_USER_WIDTH),
.TA(TB_TA), .TT(TB_TT),
.MAX_READ_TXNS (TB_AXI_MAX_READ_TXNS),
.MAX_WRITE_TXNS (TB_AXI_MAX_WRITE_TXNS+2), // master is not required to comply
.AX_MIN_WAIT_CYCLES (TB_REQ_MIN_WAIT_CYCLES),
.AX_MAX_WAIT_CYCLES (TB_REQ_MAX_WAIT_CYCLES),
.W_MIN_WAIT_CYCLES (TB_REQ_MIN_WAIT_CYCLES),
.W_MAX_WAIT_CYCLES (TB_REQ_MAX_WAIT_CYCLES),
.RESP_MIN_WAIT_CYCLES (TB_RESP_MIN_WAIT_CYCLES),
.RESP_MAX_WAIT_CYCLES (TB_RESP_MAX_WAIT_CYCLES),
.AXI_ATOPS (1'b1)
) axi_master = new(upstream_dv);
initial begin
axi_master.reset();
wait(rst_n);
axi_master.add_memory_region({TB_AXI_ADDR_WIDTH{1'b0}}, {TB_AXI_ADDR_WIDTH{1'b1}}, axi_pkg::WTHRU_NOALLOCATE);
axi_master.run(TB_N_TXNS, TB_N_TXNS);
mst_done = 1'b1;
end
initial begin
wait (mst_done);
$finish();
end
// AXI Slave
axi_test::axi_rand_slave #(
.AW(TB_AXI_ADDR_WIDTH), .DW(TB_AXI_DATA_WIDTH), .IW(TB_AXI_ID_WIDTH), .UW(TB_AXI_USER_WIDTH),
.TA(TB_TA), .TT(TB_TT),
.AX_MIN_WAIT_CYCLES (TB_RESP_MIN_WAIT_CYCLES),
.AX_MAX_WAIT_CYCLES (TB_RESP_MAX_WAIT_CYCLES),
.R_MIN_WAIT_CYCLES (TB_RESP_MIN_WAIT_CYCLES),
.R_MAX_WAIT_CYCLES (TB_RESP_MAX_WAIT_CYCLES),
.RESP_MIN_WAIT_CYCLES (TB_RESP_MIN_WAIT_CYCLES),
.RESP_MAX_WAIT_CYCLES (TB_RESP_MAX_WAIT_CYCLES)
) axi_slave = new(downstream_dv);
initial begin
axi_slave.reset();
wait (rst_n);
axi_slave.run();
end
typedef struct packed {
axi_id_t id;
logic thru;
} w_cmd_t;
typedef axi_test::axi_ax_beat #(
.AW(TB_AXI_ADDR_WIDTH), .IW(TB_AXI_ID_WIDTH), .UW(TB_AXI_USER_WIDTH)
) ax_beat_t;
typedef axi_test::axi_b_beat #(
.IW(TB_AXI_ID_WIDTH), .UW(TB_AXI_USER_WIDTH)
) b_beat_t;
typedef axi_test::axi_r_beat #(
.DW(TB_AXI_DATA_WIDTH), .IW(TB_AXI_ID_WIDTH), .UW(TB_AXI_USER_WIDTH)
) r_beat_t;
typedef axi_test::axi_w_beat #(
.DW(TB_AXI_DATA_WIDTH), .UW(TB_AXI_USER_WIDTH)
) w_beat_t;
// Put W beats into transfer queue or drop them and inject B responses based on W command.
function automatic void process_w_beat(w_beat_t w_beat, ref w_cmd_t w_cmd_queue[$],
ref w_beat_t w_xfer_queue[$], ref b_beat_t b_inject_queue[$]
);
w_cmd_t w_cmd = w_cmd_queue[0];
if (w_cmd.thru) begin
w_xfer_queue.push_back(w_beat);
end
if (w_beat.w_last) begin
if (!w_cmd.thru) begin
automatic b_beat_t b_beat = new;
b_beat.b_id = w_cmd.id;
b_beat.b_resp = RESP_SLVERR;
b_inject_queue.push_back(b_beat);
end
void'(w_cmd_queue.pop_front());
end
endfunction
// Monitor and check responses of filter.
initial begin
static ax_beat_t ar_xfer_queue[$],
aw_xfer_queue[$];
static b_beat_t b_inject_queue[$],
b_xfer_queue[$];
static r_beat_t r_inject_queue[$],
r_xfer_queue[$];
static w_cmd_t w_cmd_queue[$];
static w_beat_t w_act_queue[$],
w_undecided_queue[$],
w_xfer_queue[$];
forever begin
@(posedge clk);
#(TB_TT);
// Ensure that downstream never sees an `aw_atop`.
if (downstream.aw_valid) begin
assert (downstream.aw_atop == '0);
end
// Push upstream ARs into transfer queues.
if (upstream.ar_valid && upstream.ar_ready) begin
automatic ax_beat_t ar_beat = new;
ar_beat.ax_id = upstream.ar_id;
ar_beat.ax_addr = upstream.ar_addr;
ar_beat.ax_len = upstream.ar_len;
ar_beat.ax_size = upstream.ar_size;
ar_beat.ax_burst = upstream.ar_burst;
ar_beat.ax_lock = upstream.ar_lock;
ar_beat.ax_cache = upstream.ar_cache;
ar_beat.ax_prot = upstream.ar_prot;
ar_beat.ax_qos = upstream.ar_qos;
ar_beat.ax_region = upstream.ar_region;
ar_beat.ax_user = upstream.ar_user;
ar_xfer_queue.push_back(ar_beat);
end
// Push upstream AWs that must go through into transfer queues, and push to W command queue.
if (upstream.aw_valid && upstream.aw_ready) begin
automatic ax_beat_t aw_beat = new;
automatic w_cmd_t w_cmd;
aw_beat.ax_id = upstream.aw_id;
aw_beat.ax_addr = upstream.aw_addr;
aw_beat.ax_len = upstream.aw_len;
aw_beat.ax_size = upstream.aw_size;
aw_beat.ax_burst = upstream.aw_burst;
aw_beat.ax_lock = upstream.aw_lock;
aw_beat.ax_cache = upstream.aw_cache;
aw_beat.ax_prot = upstream.aw_prot;
aw_beat.ax_qos = upstream.aw_qos;
aw_beat.ax_region = upstream.aw_region;
aw_beat.ax_atop = upstream.aw_atop;
aw_beat.ax_user = upstream.aw_user;
w_cmd.id = aw_beat.ax_id;
w_cmd.thru = (aw_beat.ax_atop == '0);
w_cmd_queue.push_back(w_cmd);
if (w_cmd.thru) begin
aw_xfer_queue.push_back(aw_beat);
end else if (aw_beat.ax_atop[5:4] != ATOP_ATOMICSTORE) begin
for (int unsigned i = 0; i < aw_beat.ax_len + 1; i++) begin
automatic r_beat_t r_beat = new;
r_beat.r_id = aw_beat.ax_id;
r_beat.r_resp = RESP_SLVERR;
r_beat.r_data = '0;
r_beat.r_user = '0;
r_beat.r_last = (i == aw_beat.ax_len);
r_inject_queue.push_back(r_beat);
end
end
end
// Handle undecided upstream W beats if possible.
while (w_undecided_queue.size() > 0 && w_cmd_queue.size() > 0) begin
automatic w_beat_t w_beat = w_undecided_queue.pop_front();
process_w_beat(w_beat, w_cmd_queue, w_xfer_queue, b_inject_queue);
end
// Process upstream W beats or put them into queue of undecided W beats.
if (upstream.w_valid && upstream.w_ready) begin
automatic w_beat_t w_beat = new;
w_beat.w_data = upstream.w_data;
w_beat.w_strb = upstream.w_strb;
w_beat.w_last = upstream.w_last;
w_beat.w_user = upstream.w_user;
if (w_cmd_queue.size() > 0) begin
process_w_beat(w_beat, w_cmd_queue, w_xfer_queue, b_inject_queue);
end else begin
w_undecided_queue.push_back(w_beat);
end
end
// Push downstream Rs into transfer queue.
if (downstream.r_valid && downstream.r_ready) begin
automatic r_beat_t r_beat = new;
r_beat.r_id = downstream.r_id;
r_beat.r_data = downstream.r_data;
r_beat.r_resp = downstream.r_resp;
r_beat.r_last = downstream.r_last;
r_beat.r_user = downstream.r_user;
r_xfer_queue.push_back(r_beat);
end
// Push downstream Bs into transfer queue.
if (downstream.b_valid && downstream.b_ready) begin
automatic b_beat_t b_beat = new;
b_beat.b_id = downstream.b_id;
b_beat.b_resp = downstream.b_resp;
b_beat.b_user = downstream.b_user;
b_xfer_queue.push_back(b_beat);
end
// Ensure downstream ARs match beats from transfer queue.
if (downstream.ar_valid && downstream.ar_ready) begin
automatic ax_beat_t exp_beat;
assert (ar_xfer_queue.size() > 0) else $fatal(1, "downstream.AR: Unknown beat!");
exp_beat = ar_xfer_queue.pop_front();
assert (downstream.ar_id == exp_beat.ax_id);
assert (downstream.ar_addr == exp_beat.ax_addr);
assert (downstream.ar_len == exp_beat.ax_len);
assert (downstream.ar_size == exp_beat.ax_size);
assert (downstream.ar_burst == exp_beat.ax_burst);
assert (downstream.ar_cache == exp_beat.ax_cache);
assert (downstream.ar_prot == exp_beat.ax_prot);
assert (downstream.ar_qos == exp_beat.ax_qos);
assert (downstream.ar_region == exp_beat.ax_region);
assert (downstream.ar_user == exp_beat.ax_user);
end
// Ensure downstream AWs match beats from transfer queue.
if (downstream.aw_valid && downstream.aw_ready) begin
automatic ax_beat_t exp_beat;
assert (aw_xfer_queue.size() > 0) else $fatal(1, "downstream.AW: Unknown beat!");
exp_beat = aw_xfer_queue.pop_front();
assert (downstream.aw_id == exp_beat.ax_id);
assert (downstream.aw_addr == exp_beat.ax_addr);
assert (downstream.aw_len == exp_beat.ax_len);
assert (downstream.aw_size == exp_beat.ax_size);
assert (downstream.aw_burst == exp_beat.ax_burst);
assert (downstream.aw_cache == exp_beat.ax_cache);
assert (downstream.aw_prot == exp_beat.ax_prot);
assert (downstream.aw_qos == exp_beat.ax_qos);
assert (downstream.aw_region == exp_beat.ax_region);
assert (downstream.aw_user == exp_beat.ax_user);
end
// Ensure downstream Ws match beats from transfer queue.
while (w_act_queue.size() > 0 && w_xfer_queue.size() > 0) begin
automatic w_beat_t exp_beat = w_xfer_queue.pop_front();
automatic w_beat_t act_beat = w_act_queue.pop_front();
assert (act_beat.w_data == exp_beat.w_data);
assert (act_beat.w_strb == exp_beat.w_strb);
assert (act_beat.w_last == exp_beat.w_last);
assert (act_beat.w_user == exp_beat.w_user);
end
if (downstream.w_valid && downstream.w_ready) begin
if (w_xfer_queue.size() > 0) begin
automatic w_beat_t exp_beat = w_xfer_queue.pop_front();
assert (downstream.w_data == exp_beat.w_data);
assert (downstream.w_strb == exp_beat.w_strb);
assert (downstream.w_last == exp_beat.w_last);
assert (downstream.w_user == exp_beat.w_user);
end else begin
automatic w_beat_t act_beat = new;
act_beat.w_data = downstream.w_data;
act_beat.w_strb = downstream.w_strb;
act_beat.w_last = downstream.w_last;
act_beat.w_user = downstream.w_user;
w_act_queue.push_back(act_beat);
end
end
// Ensure upstream Rs match beats from transfer or inject queue.
if (upstream.r_valid && upstream.r_ready) begin
automatic r_beat_t exp_beat;
if (r_inject_queue.size() > 0 && r_inject_queue[0].r_id == upstream.r_id) begin
exp_beat = r_inject_queue.pop_front();
end else if (r_xfer_queue.size() > 0 && r_xfer_queue[0].r_id == upstream.r_id) begin
exp_beat = r_xfer_queue.pop_front();
end else begin
$fatal(1, "upstream.R: Unknown beat!");
end
assert (upstream.r_id == exp_beat.r_id);
assert (upstream.r_data == exp_beat.r_data);
assert (upstream.r_resp == exp_beat.r_resp);
assert (upstream.r_last == exp_beat.r_last);
assert (upstream.r_user == exp_beat.r_user);
end
// Ensure upstream Bs match beats from transfer or inject queue.
if (upstream.b_valid && upstream.b_ready) begin
automatic b_beat_t exp_beat;
if (b_inject_queue.size() > 0 && b_inject_queue[0].b_id == upstream.b_id) begin
exp_beat = b_inject_queue.pop_front();
end else if (b_xfer_queue.size() > 0 && b_xfer_queue[0].b_id == upstream.b_id) begin
exp_beat = b_xfer_queue.pop_front();
end else begin
$fatal(1, "upstream.B: Unknown beat!");
end
assert (upstream.b_id == exp_beat.b_id);
assert (upstream.b_resp == exp_beat.b_resp);
assert (upstream.b_user == exp_beat.b_user);
end
end
end
endmodule |
module tb_axi_serializer #(
parameter int unsigned NoWrites = 5000, // How many writes per master
parameter int unsigned NoReads = 3000 // How many reads per master
);
// Random master no Transactions
localparam int unsigned NoPendingDut = 4;
// Random Master Atomics
localparam int unsigned MaxAW = 32'd30;
localparam int unsigned MaxAR = 32'd30;
localparam bit EnAtop = 1'b1;
// timing parameters
localparam time CyclTime = 10ns;
localparam time ApplTime = 2ns;
localparam time TestTime = 8ns;
// AXI configuration
localparam int unsigned AxiIdWidth = 4;
localparam int unsigned AxiAddrWidth = 32; // Axi Address Width
localparam int unsigned AxiDataWidth = 64; // Axi Data Width
localparam int unsigned AxiUserWidth = 5;
// Sim print config, how many transactions
localparam int unsigned PrintTxn = 500;
typedef axi_test::axi_rand_master #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
.IW ( AxiIdWidth ),
.UW ( AxiUserWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime ),
// Maximum number of read and write transactions in flight
.MAX_READ_TXNS ( MaxAR ),
.MAX_WRITE_TXNS ( MaxAW ),
.AXI_ATOPS ( EnAtop )
) axi_rand_master_t;
typedef axi_test::axi_rand_slave #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
.IW ( AxiIdWidth ),
.UW ( AxiUserWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime )
) axi_rand_slave_t;
// -------------
// DUT signals
// -------------
logic clk;
logic rst_n;
logic end_of_sim;
// interfaces
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master ();
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) master_dv (clk);
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave ();
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave_dv (clk);
`AXI_ASSIGN(master, master_dv)
`AXI_ASSIGN(slave_dv, slave)
//-----------------------------------
// Clock generator
//-----------------------------------
clk_rst_gen #(
.ClkPeriod ( CyclTime ),
.RstClkCycles ( 5 )
) i_clk_gen (
.clk_o (clk),
.rst_no(rst_n)
);
//-----------------------------------
// DUT
//-----------------------------------
axi_serializer_intf #(
.MAX_READ_TXNS ( NoPendingDut ),
.MAX_WRITE_TXNS ( NoPendingDut ),
.AXI_ID_WIDTH ( AxiIdWidth ), // AXI ID width
.AXI_ADDR_WIDTH ( AxiAddrWidth ), // AXI address width
.AXI_DATA_WIDTH ( AxiDataWidth ), // AXI data width
.AXI_USER_WIDTH ( AxiUserWidth ) // AXI user width
) i_dut (
.clk_i ( clk ), // clock
.rst_ni ( rst_n ), // asynchronous reset active low
.slv ( master ), // slave port
.mst ( slave ) // master port
);
initial begin : proc_axi_master
automatic axi_rand_master_t axi_rand_master = new(master_dv);
end_of_sim <= 1'b0;
axi_rand_master.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE);
axi_rand_master.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE);
axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE);
axi_rand_master.reset();
@(posedge rst_n);
axi_rand_master.run(NoReads, NoWrites);
end_of_sim <= 1'b1;
repeat (100) @(posedge clk);
$stop();
end
initial begin : proc_axi_slave
automatic axi_rand_slave_t axi_rand_slave = new(slave_dv);
axi_rand_slave.reset();
@(posedge rst_n);
axi_rand_slave.run();
end
// Checker
typedef logic [AxiIdWidth-1:0] axi_id_t;
typedef logic [AxiIdWidth-1:0] axi_addr_t;
typedef logic [AxiIdWidth-1:0] axi_data_t;
typedef logic [AxiIdWidth-1:0] axi_strb_t;
typedef logic [AxiIdWidth-1:0] axi_user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, axi_addr_t, axi_id_t, axi_user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, axi_data_t, axi_strb_t, axi_user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, axi_id_t, axi_user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, axi_addr_t, axi_id_t, axi_user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, axi_data_t, axi_id_t, axi_user_t)
axi_id_t aw_queue[$];
axi_id_t ar_queue[$];
aw_chan_t aw_chan[$];
w_chan_t w_chan[$];
b_chan_t b_chan[$];
ar_chan_t ar_chan[$];
r_chan_t r_chan[$];
initial begin : proc_checker
automatic axi_id_t id_exp; // expected ID
automatic aw_chan_t aw_exp; // expected AW
automatic aw_chan_t aw_act; // actual AW
automatic w_chan_t w_exp; // expected W
automatic w_chan_t w_act; // actual W
automatic b_chan_t b_exp; // expected B
automatic b_chan_t b_act; // actual B
automatic ar_chan_t ar_exp; // expected AR
automatic ar_chan_t ar_act; // actual AR
automatic r_chan_t r_exp; // expected R
automatic r_chan_t r_act; // actual R
forever begin
@(posedge clk);
#TestTime;
// All FIFOs get populated if there is something to put in
if (master.aw_valid && master.aw_ready) begin
`AXI_SET_TO_AW(aw_exp, master)
aw_exp.id = '0;
id_exp = master.aw_id;
aw_chan.push_back(aw_exp);
aw_queue.push_back(id_exp);
if (master.aw_atop[axi_pkg::ATOP_R_RESP]) begin
ar_queue.push_back(id_exp);
end
end
if (master.w_valid && master.w_ready) begin
`AXI_SET_TO_W(w_exp, master)
w_chan.push_back(w_exp);
end
if (slave.b_valid && slave.b_ready) begin
id_exp = aw_queue.pop_front();
`AXI_SET_TO_B(b_exp, slave)
b_exp.id = id_exp;
b_chan.push_back(b_exp);
end
if (master.ar_valid && master.ar_ready) begin
`AXI_SET_TO_AR(ar_exp, master)
ar_exp.id = '0;
id_exp = master.ar_id;
ar_chan.push_back(ar_exp);
ar_queue.push_back(id_exp);
end
if (slave.r_valid && slave.r_ready) begin
`AXI_SET_TO_R(r_exp, slave)
if (slave.r_last) begin
id_exp = ar_queue.pop_front();
end else begin
id_exp = ar_queue[0];
end
r_exp.id = id_exp;
r_chan.push_back(r_exp);
end
// Check that all channels match the expected response
if (slave.aw_valid && slave.aw_ready) begin
aw_exp = aw_chan.pop_front();
`AXI_SET_TO_AW(aw_act, slave)
assert(aw_act == aw_exp) else $error("AW Measured: %h Expected: %h", aw_act, aw_exp);
end
if (slave.w_valid && slave.w_ready) begin
w_exp = w_chan.pop_front();
`AXI_SET_TO_W(w_act, slave)
assert(w_act == w_exp) else $error("W Measured: %h Expected: %h", w_act, w_exp);
end
if (master.b_valid && master.b_ready) begin
b_exp = b_chan.pop_front();
`AXI_SET_TO_B(b_act, master)
assert(b_act == b_exp) else $error("B Measured: %h Expected: %h", b_act, b_exp);
end
if (slave.ar_valid && slave.ar_ready) begin
ar_exp = ar_chan.pop_front();
`AXI_SET_TO_AR(ar_act, slave)
assert(ar_act == ar_exp) else $error("AR Measured: %h Expected: %h", ar_act, ar_exp);
end
if (master.r_valid && master.r_ready) begin
r_exp = r_chan.pop_front();
`AXI_SET_TO_R(r_act, master)
assert(r_act == r_exp) else $error("R Measured: %h Expected: %h", r_act, r_exp);
end
end
end
initial begin : proc_sim_progress
automatic int unsigned aw = 0;
automatic int unsigned ar = 0;
automatic bit aw_printed = 1'b0;
automatic bit ar_printed = 1'b0;
@(posedge rst_n);
forever begin
@(posedge clk);
#TestTime;
if (master.aw_valid && master.aw_ready) begin
aw++;
end
if (master.ar_valid && master.ar_ready) begin
ar++;
end
if ((aw % PrintTxn == 0) && ! aw_printed) begin
$display("%t> Transmit AW %d of %d.", $time(), aw, NoWrites);
aw_printed = 1'b1;
end
if ((ar % PrintTxn == 0) && !ar_printed) begin
$display("%t> Transmit AR %d of %d.", $time(), ar, NoReads);
ar_printed = 1'b1;
end
if (aw % PrintTxn == 1) begin
aw_printed = 1'b0;
end
if (ar % PrintTxn == 1) begin
ar_printed = 1'b0;
end
if (end_of_sim) begin
$info("All transactions completed.");
break;
end
end
end
endmodule |
module tb_axi_cdc #(
// AXI Parameters
parameter int unsigned AXI_AW = 32,
parameter int unsigned AXI_DW = 64,
parameter int unsigned AXI_IW = 4,
parameter int unsigned AXI_UW = 2,
parameter int unsigned AXI_MAX_READ_TXNS = 10,
parameter int unsigned AXI_MAX_WRITE_TXNS = 12,
// TB Parameters
parameter time TCLK_UPSTREAM = 10ns,
parameter time TA_UPSTREAM = TCLK_UPSTREAM * 1/4,
parameter time TT_UPSTREAM = TCLK_UPSTREAM * 3/4,
parameter time TCLK_DOWNSTREAM = 3ns,
parameter time TA_DOWNSTREAM = TCLK_DOWNSTREAM * 1/4,
parameter time TT_DOWNSTREAM = TCLK_DOWNSTREAM * 3/4,
parameter int unsigned REQ_MIN_WAIT_CYCLES = 0,
parameter int unsigned REQ_MAX_WAIT_CYCLES = 10,
parameter int unsigned RESP_MIN_WAIT_CYCLES = 0,
parameter int unsigned RESP_MAX_WAIT_CYCLES = REQ_MAX_WAIT_CYCLES/2,
parameter int unsigned N_TXNS = 1000
);
localparam int unsigned N_RD_TXNS = N_TXNS / 2;
localparam int unsigned N_WR_TXNS = N_TXNS / 2;
// Clocks and Resets
logic upstream_clk,
downstream_clk,
upstream_rst_n,
downstream_rst_n;
clk_rst_gen #(
.ClkPeriod (TCLK_UPSTREAM),
.RstClkCycles (5)
) i_clk_rst_gen_upstream (
.clk_o (upstream_clk),
.rst_no (upstream_rst_n)
);
clk_rst_gen #(
.ClkPeriod (TCLK_DOWNSTREAM),
.RstClkCycles (5)
) i_clk_rst_gen_downstream (
.clk_o (downstream_clk),
.rst_no (downstream_rst_n)
);
// AXI Interfaces
AXI_BUS_DV #(
.AXI_ADDR_WIDTH (AXI_AW),
.AXI_DATA_WIDTH (AXI_DW),
.AXI_ID_WIDTH (AXI_IW),
.AXI_USER_WIDTH (AXI_UW)
) upstream_dv (
.clk_i (upstream_clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH (AXI_AW),
.AXI_DATA_WIDTH (AXI_DW),
.AXI_ID_WIDTH (AXI_IW),
.AXI_USER_WIDTH (AXI_UW)
) upstream ();
`AXI_ASSIGN(upstream, upstream_dv)
AXI_BUS_DV #(
.AXI_ADDR_WIDTH (AXI_AW),
.AXI_DATA_WIDTH (AXI_DW),
.AXI_ID_WIDTH (AXI_IW),
.AXI_USER_WIDTH (AXI_UW)
) downstream_dv (
.clk_i (downstream_clk)
);
AXI_BUS #(
.AXI_ADDR_WIDTH (AXI_AW),
.AXI_DATA_WIDTH (AXI_DW),
.AXI_ID_WIDTH (AXI_IW),
.AXI_USER_WIDTH (AXI_UW)
) downstream ();
`AXI_ASSIGN(downstream_dv, downstream)
// AXI Channel Structs
typedef logic [AXI_AW-1:0] addr_t;
typedef logic [AXI_DW-1:0] data_t;
typedef logic [AXI_IW-1:0] id_t;
typedef logic [AXI_DW/8-1:0] strb_t;
typedef logic [AXI_UW-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
axi_cdc_intf #(
.AXI_ADDR_WIDTH (AXI_AW),
.AXI_DATA_WIDTH (AXI_DW),
.AXI_ID_WIDTH (AXI_IW),
.AXI_USER_WIDTH (AXI_UW),
.LOG_DEPTH (2)
) dut (
.src_clk_i (upstream_clk),
.src_rst_ni (upstream_rst_n),
.src (upstream),
.dst_clk_i (downstream_clk),
.dst_rst_ni (downstream_rst_n),
.dst (downstream)
);
typedef axi_test::axi_rand_master #(
.AW (AXI_AW),
.DW (AXI_DW),
.IW (AXI_IW),
.UW (AXI_UW),
.TA (TA_UPSTREAM),
.TT (TT_UPSTREAM),
.MAX_READ_TXNS (AXI_MAX_READ_TXNS),
.MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS),
.AX_MIN_WAIT_CYCLES (REQ_MIN_WAIT_CYCLES),
.AX_MAX_WAIT_CYCLES (REQ_MAX_WAIT_CYCLES),
.W_MIN_WAIT_CYCLES (REQ_MIN_WAIT_CYCLES),
.W_MAX_WAIT_CYCLES (REQ_MAX_WAIT_CYCLES),
.RESP_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES),
.RESP_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES),
.AXI_MAX_BURST_LEN (16)
) axi_master_t;
axi_master_t axi_master = new(upstream_dv);
initial begin
wait (upstream_rst_n);
axi_master.run(N_RD_TXNS, N_WR_TXNS);
end
typedef axi_test::axi_rand_slave #(
.AW (AXI_AW),
.DW (AXI_DW),
.IW (AXI_IW),
.UW (AXI_UW),
.TA (TA_DOWNSTREAM),
.TT (TT_DOWNSTREAM),
.AX_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES),
.AX_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES),
.R_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES),
.R_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES),
.RESP_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES),
.RESP_MAX_WAIT_CYCLES (RESP_MAX_WAIT_CYCLES)
) axi_slave_t;
axi_slave_t axi_slave = new(downstream_dv);
initial begin
wait (downstream_rst_n);
axi_slave.run();
end
ar_chan_t mst_ar, slv_ar, ar_queue[$];
aw_chan_t mst_aw, slv_aw, aw_queue[$];
b_chan_t mst_b, slv_b, b_queue[$];
r_chan_t mst_r, slv_r, r_queue[$];
w_chan_t mst_w, slv_w, w_queue[$];
`AXI_ASSIGN_TO_AR(mst_ar, upstream)
`AXI_ASSIGN_TO_AR(slv_ar, downstream)
`AXI_ASSIGN_TO_AW(mst_aw, upstream)
`AXI_ASSIGN_TO_AW(slv_aw, downstream)
`AXI_ASSIGN_TO_B(mst_b, upstream)
`AXI_ASSIGN_TO_B(slv_b, downstream)
`AXI_ASSIGN_TO_R(mst_r, upstream)
`AXI_ASSIGN_TO_R(slv_r, downstream)
`AXI_ASSIGN_TO_W(mst_w, upstream)
`AXI_ASSIGN_TO_W(slv_w, downstream)
logic mst_done = 1'b0;
// Monitor and check upstream
initial begin
automatic b_chan_t exp_b;
automatic r_chan_t exp_r;
automatic int unsigned rd_cnt = 0, wr_cnt = 0;
forever begin
@(posedge upstream_clk);
#(TT_UPSTREAM);
if (upstream.aw_valid && upstream.aw_ready) begin
aw_queue.push_back(mst_aw);
end
if (upstream.w_valid && upstream.w_ready) begin
w_queue.push_back(mst_w);
end
if (upstream.b_valid && upstream.b_ready) begin
exp_b = b_queue.pop_front();
assert (mst_b == exp_b);
wr_cnt++;
end
if (upstream.ar_valid && upstream.ar_ready) begin
ar_queue.push_back(mst_ar);
end
if (upstream.r_valid && upstream.r_ready) begin
exp_r = r_queue.pop_front();
assert (mst_r == exp_r);
if (upstream.r_last) begin
rd_cnt++;
end
end
if (rd_cnt == N_RD_TXNS && wr_cnt == N_WR_TXNS) begin
mst_done = 1'b1;
end
end
end
// Monitor and check downstream
initial begin
automatic ar_chan_t exp_ar;
automatic aw_chan_t exp_aw;
automatic w_chan_t exp_w;
forever begin
@(posedge downstream_clk);
#(TT_DOWNSTREAM);
if (downstream.aw_valid && downstream.aw_ready) begin
exp_aw = aw_queue.pop_front();
assert (slv_aw == exp_aw);
end
if (downstream.w_valid && downstream.w_ready) begin
exp_w = w_queue.pop_front();
assert (slv_w == exp_w);
end
if (downstream.b_valid && downstream.b_ready) begin
b_queue.push_back(slv_b);
end
if (downstream.ar_valid && downstream.ar_ready) begin
exp_ar = ar_queue.pop_front();
assert (slv_ar == exp_ar);
end
if (downstream.r_valid && downstream.r_ready) begin
r_queue.push_back(slv_r);
end
end
end
// Terminate simulation after all transactions have completed.
initial begin
wait (mst_done);
#(10*TCLK_UPSTREAM);
$finish();
end
endmodule |
module tb_axi_sim_mem #(
// TB Parameters
parameter time TbTclk = 10ns,
// Module Parameters
parameter int unsigned TbAddrWidth = 32'd64,
parameter int unsigned TbDataWidth = 32'd128,
parameter int unsigned TbIdWidth = 32'd6,
parameter int unsigned TbUserWidth = 32'd2,
parameter bit TbWarnUninitialized = 1'b0,
parameter time TbApplDelay = 2ns,
parameter time TbAcqDelay = 8ns
);
logic clk,
rst_n;
clk_rst_gen #(
.ClkPeriod (TbTclk),
.RstClkCycles (5)
) i_clk_rst_gen (
.clk_o (clk),
.rst_no (rst_n)
);
localparam int unsigned StrbWidth = TbDataWidth / 8;
typedef logic [TbAddrWidth-1:0] addr_t;
typedef logic [TbDataWidth-1:0] data_t;
typedef logic [TbIdWidth-1:0] id_t;
typedef logic [StrbWidth-1:0] strb_t;
typedef logic [TbUserWidth-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_t, w_t, ar_t)
`AXI_TYPEDEF_RESP_T(rsp_t, b_t, r_t)
req_t req;
rsp_t rsp;
axi_sim_mem #(
.AddrWidth (TbAddrWidth),
.DataWidth (TbDataWidth),
.IdWidth (TbIdWidth),
.UserWidth (TbUserWidth),
.req_t (req_t),
.rsp_t (rsp_t),
.WarnUninitialized (TbWarnUninitialized),
.ApplDelay (TbApplDelay),
.AcqDelay (TbAcqDelay)
) i_sim_mem (
.clk_i (clk),
.rst_ni (rst_n),
.axi_req_i (req),
.axi_rsp_o (rsp)
);
AXI_BUS_DV #(
.AXI_ADDR_WIDTH (TbAddrWidth),
.AXI_DATA_WIDTH (TbDataWidth),
.AXI_ID_WIDTH (TbIdWidth),
.AXI_USER_WIDTH (TbUserWidth)
) axi_dv (clk);
`AXI_ASSIGN_TO_REQ(req, axi_dv)
`AXI_ASSIGN_FROM_RESP(axi_dv, rsp)
typedef axi_test::axi_driver #(
.AW(TbAddrWidth), .DW(TbDataWidth), .IW(TbIdWidth), .UW(TbUserWidth),
.TA(1ns), .TT(6ns)
) drv_t;
drv_t drv = new(axi_dv);
// Simply read and write a random memory region.
initial begin
automatic logic rand_success;
automatic data_t exp_data[$];
automatic drv_t::ax_beat_t aw_beat = new, ar_beat = new;
automatic drv_t::w_beat_t w_beat = new;
automatic drv_t::b_beat_t b_beat;
automatic drv_t::r_beat_t r_beat;
drv.reset_master();
wait (rst_n);
// AW
rand_success = aw_beat.randomize(); assert(rand_success);
aw_beat.ax_addr >>= $clog2(StrbWidth); // align address with data width
aw_beat.ax_addr <<= $clog2(StrbWidth);
aw_beat.ax_len = $urandom();
aw_beat.ax_size = $clog2(StrbWidth);
aw_beat.ax_burst = axi_pkg::BURST_INCR;
drv.send_aw(aw_beat);
// W beats
for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin
rand_success = w_beat.randomize(); assert(rand_success);
w_beat.w_strb = '1;
if (i == aw_beat.ax_len) begin
w_beat.w_last = 1'b1;
end
drv.send_w(w_beat);
exp_data.push_back(w_beat.w_data);
end
// B
drv.recv_b(b_beat);
assert(b_beat.b_resp == axi_pkg::RESP_OKAY);
// AR
ar_beat.ax_addr = aw_beat.ax_addr;
ar_beat.ax_len = aw_beat.ax_len;
ar_beat.ax_size = aw_beat.ax_size;
ar_beat.ax_burst = aw_beat.ax_burst;
drv.send_ar(ar_beat);
// R beats
for (int unsigned i = 0; i <= ar_beat.ax_len; i++) begin
automatic data_t exp = exp_data.pop_front();
drv.recv_r(r_beat);
assert(r_beat.r_data == exp) else
$error("Received 0x%h != expected 0x%h!", r_beat.r_data, exp);
end
// Done.
#(TbTclk);
$finish();
end
endmodule |
module tb_axi_lite_xbar;
// Dut parameters
localparam int unsigned NoMasters = 32'd6; // How many Axi Masters there are
localparam int unsigned NoSlaves = 32'd8; // How many Axi Slaves there are
// Random master no Transactions
localparam int unsigned NoWrites = 32'd10000; // How many writes per master
localparam int unsigned NoReads = 32'd10000; // How many reads per master
// timing parameters
localparam time CyclTime = 10ns;
localparam time ApplTime = 2ns;
localparam time TestTime = 8ns;
// axi configuration
localparam int unsigned AxiAddrWidth = 32'd32; // Axi Address Width
localparam int unsigned AxiDataWidth = 32'd64; // Axi Data Width
localparam int unsigned AxiStrbWidth = AxiDataWidth / 32'd8;
// in the bench can change this variables which are set here freely
localparam axi_pkg::xbar_cfg_t xbar_cfg = '{
NoSlvPorts: NoMasters,
NoMstPorts: NoSlaves,
MaxMstTrans: 32'd10,
MaxSlvTrans: 32'd6,
FallThrough: 1'b0,
LatencyMode: axi_pkg::CUT_ALL_AX,
AxiAddrWidth: AxiAddrWidth,
AxiDataWidth: AxiDataWidth,
NoAddrRules: 32'd8,
default: '0
};
typedef logic [AxiAddrWidth-1:0] addr_t;
typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr
typedef logic [AxiDataWidth-1:0] data_t;
typedef logic [AxiStrbWidth-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_lite_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t)
localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = '{
'{idx: 32'd7, start_addr: 32'h0001_0000, end_addr: 32'h0001_1000},
'{idx: 32'd6, start_addr: 32'h0000_9000, end_addr: 32'h0001_0000},
'{idx: 32'd5, start_addr: 32'h0000_8000, end_addr: 32'h0000_9000},
'{idx: 32'd4, start_addr: 32'h0000_7000, end_addr: 32'h0000_8000},
'{idx: 32'd3, start_addr: 32'h0000_6300, end_addr: 32'h0000_7000},
'{idx: 32'd2, start_addr: 32'h0000_4000, end_addr: 32'h0000_6300},
'{idx: 32'd1, start_addr: 32'h0000_3000, end_addr: 32'h0000_4000},
'{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000}
};
typedef axi_test::axi_lite_rand_master #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime ),
.MIN_ADDR ( 32'h0000_0000 ),
.MAX_ADDR ( 32'h0001_3000 ),
.MAX_READ_TXNS ( 10 ),
.MAX_WRITE_TXNS ( 10 )
) rand_lite_master_t;
typedef axi_test::axi_lite_rand_slave #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime )
) rand_lite_slave_t;
// -------------
// DUT signals
// -------------
logic clk;
// DUT signals
logic rst_n;
logic [NoMasters-1:0] end_of_sim;
// master structs
req_lite_t [NoMasters-1:0] masters_req;
resp_lite_t [NoMasters-1:0] masters_resp;
// slave structs
req_lite_t [NoSlaves-1:0] slaves_req;
resp_lite_t [NoSlaves-1:0] slaves_resp;
// -------------------------------
// AXI Interfaces
// -------------------------------
AXI_LITE #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) master [NoMasters-1:0] ();
AXI_LITE_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) master_dv [NoMasters-1:0] (clk);
for (genvar i = 0; i < NoMasters; i++) begin : gen_conn_dv_masters
`AXI_LITE_ASSIGN(master[i], master_dv[i])
`AXI_LITE_ASSIGN_TO_REQ(masters_req[i], master[i])
`AXI_LITE_ASSIGN_FROM_RESP(master[i], masters_resp[i])
end
AXI_LITE #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) slave [NoSlaves-1:0] ();
AXI_LITE_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) slave_dv [NoSlaves-1:0](clk);
for (genvar i = 0; i < NoSlaves; i++) begin : gen_conn_dv_slaves
`AXI_LITE_ASSIGN(slave_dv[i], slave[i])
`AXI_LITE_ASSIGN_FROM_REQ(slave[i], slaves_req[i])
`AXI_LITE_ASSIGN_TO_RESP(slaves_resp[i], slave[i])
end
// -------------------------------
// AXI Rand Masters and Slaves
// -------------------------------
// Masters control simulation run time
for (genvar i = 0; i < NoMasters; i++) begin : gen_rand_master
initial begin : proc_generate_traffic
automatic rand_lite_master_t lite_axi_master = new ( master_dv[i], $sformatf("MST_%0d", i));
automatic data_t data = '0;
automatic axi_pkg::resp_t resp = '0;
end_of_sim[i] <= 1'b0;
lite_axi_master.reset();
@(posedge rst_n);
lite_axi_master.write(32'h0000_1100, axi_pkg::prot_t'('0), 64'hDEADBEEFDEADBEEF, 8'hFF, resp);
lite_axi_master.read(32'h0000_e100, axi_pkg::prot_t'('0), data, resp);
lite_axi_master.run(NoReads, NoWrites);
end_of_sim[i] <= 1'b1;
end
end
for (genvar i = 0; i < NoSlaves; i++) begin : gen_rand_slave
initial begin : proc_recieve_traffic
automatic rand_lite_slave_t lite_axi_slave = new( slave_dv[i] , $sformatf("SLV_%0d", i));
lite_axi_slave.reset();
@(posedge rst_n);
lite_axi_slave.run();
end
end
initial begin : proc_stop_sim
wait (&end_of_sim);
repeat (1000) @(posedge clk);
$display("Simulation stopped as all Masters transferred their data, Success.",);
$stop();
end
//-----------------------------------
// Clock generator
//-----------------------------------
clk_rst_gen #(
.ClkPeriod ( CyclTime ),
.RstClkCycles ( 5 )
) i_clk_gen (
.clk_o (clk),
.rst_no(rst_n)
);
//-----------------------------------
// DUT
//-----------------------------------
axi_lite_xbar #(
.Cfg ( xbar_cfg ),
.aw_chan_t ( aw_chan_lite_t ),
.w_chan_t ( w_chan_lite_t ),
.b_chan_t ( b_chan_lite_t ),
.ar_chan_t ( ar_chan_lite_t ),
.r_chan_t ( r_chan_lite_t ),
.req_t ( req_lite_t ),
.resp_t ( resp_lite_t ),
.rule_t ( rule_t )
) i_xbar_dut (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_i ( 1'b0 ),
.slv_ports_req_i ( masters_req ),
.slv_ports_resp_o ( masters_resp ),
.mst_ports_req_o ( slaves_req ),
.mst_ports_resp_i ( slaves_resp ),
.addr_map_i ( AddrMap ),
.en_default_mst_port_i ( '0 ),
.default_mst_port_i ( '0 )
);
endmodule |
module tb_axi_lite_to_apb #(
parameter bit TbPipelineRequest = 1'b0,
parameter bit TbPipelineResponse = 1'b0
);
// Dut parameters
localparam int unsigned NoApbSlaves = 8; // How many APB Slaves there are
localparam int unsigned NoAddrRules = 9; // How many address rules for the APB slaves
// Random master no Transactions
localparam int unsigned NoWrites = 10000; // How many rand writes of the master
localparam int unsigned NoReads = 20000; // How many rand reads of the master
// timing parameters
localparam time CyclTime = 10ns;
localparam time ApplTime = 2ns;
localparam time TestTime = 8ns;
// Type widths
localparam int unsigned AxiAddrWidth = 32;
localparam int unsigned AxiDataWidth = 32;
localparam int unsigned AxiStrbWidth = AxiDataWidth/8;
typedef logic [AxiAddrWidth-1:0] addr_t;
typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr
typedef logic [AxiDataWidth-1:0] data_t;
typedef logic [AxiStrbWidth-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
typedef logic [NoApbSlaves-1:0] sel_t;
typedef struct packed {
addr_t paddr;
axi_pkg::prot_t pprot; // same as AXI, this is allowed
logic psel; // onehot
logic penable;
logic pwrite;
data_t pwdata;
strb_t pstrb;
} apb_req_t;
typedef struct packed {
logic pready;
data_t prdata;
logic pslverr;
} apb_resp_t;
localparam rule_t [NoAddrRules-1:0] AddrMap = '{
'{idx: 32'd7, start_addr: 32'h0001_0000, end_addr: 32'h0001_1000},
'{idx: 32'd6, start_addr: 32'h0000_9000, end_addr: 32'h0001_0000},
'{idx: 32'd5, start_addr: 32'h0000_8000, end_addr: 32'h0000_9000},
'{idx: 32'd4, start_addr: 32'h0002_0000, end_addr: 32'h0002_1000},
'{idx: 32'd4, start_addr: 32'h0000_7000, end_addr: 32'h0000_8000},
'{idx: 32'd3, start_addr: 32'h0000_6300, end_addr: 32'h0000_7000},
'{idx: 32'd2, start_addr: 32'h0000_4000, end_addr: 32'h0000_6300},
'{idx: 32'd1, start_addr: 32'h0000_3000, end_addr: 32'h0000_4000},
'{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000}
};
typedef axi_test::axi_lite_rand_master #(
// AXI interface parameters
.AW ( AxiAddrWidth ),
.DW ( AxiDataWidth ),
// Stimuli application and test time
.TA ( ApplTime ),
.TT ( TestTime ),
.MIN_ADDR ( 32'h0000_0000 ),
.MAX_ADDR ( 32'h0002_2000 ),
// Maximum number of open transactions
.MAX_READ_TXNS ( 32'd10 ),
.MAX_WRITE_TXNS ( 32'd10 ),
// Upper and lower bounds on wait cycles on Ax, W, and resp (R and B) channels
.AX_MIN_WAIT_CYCLES ( 0 ),
.AX_MAX_WAIT_CYCLES ( 10 ),
.W_MIN_WAIT_CYCLES ( 0 ),
.W_MAX_WAIT_CYCLES ( 5 ),
.RESP_MIN_WAIT_CYCLES ( 0 ),
.RESP_MAX_WAIT_CYCLES ( 20 )
) axi_lite_rand_master_t;
// -------------
// DUT signals
// -------------
logic clk;
// DUT signals
logic rst_n;
logic end_of_sim;
// master structs
axi_req_t axi_req;
axi_resp_t axi_resp;
// slave structs
apb_req_t [NoApbSlaves-1:0] apb_req;
apb_resp_t [NoApbSlaves-1:0] apb_resps;
// -------------------------------
// AXI Interfaces
// -------------------------------
AXI_LITE #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) master ();
AXI_LITE_DV #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) master_dv (clk);
`AXI_LITE_ASSIGN(master, master_dv)
`AXI_LITE_ASSIGN_TO_REQ(axi_req, master)
`AXI_LITE_ASSIGN_FROM_RESP(master, axi_resp)
// -------------------------------
// AXI Rand Masters
// -------------------------------
// Master controls simulation run time
initial begin : proc_axi_master
static axi_lite_rand_master_t axi_lite_rand_master = new ( master_dv , "axi_lite_mst");
end_of_sim <= 1'b0;
axi_lite_rand_master.reset();
@(posedge rst_n);
axi_lite_rand_master.run(NoReads, NoWrites);
end_of_sim <= 1'b1;
end
for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_slave
initial begin : proc_apb_slave
apb_resps[i] <= '0;
forever begin
@(posedge clk);
apb_resps[i].pready <= #ApplTime $urandom();
apb_resps[i].prdata <= #ApplTime $urandom();
apb_resps[i].pslverr <= #ApplTime $urandom();
end
end
end
initial begin : proc_sim_stop
@(posedge rst_n);
wait (end_of_sim);
$stop();
end
// pragma translate_off
`ifndef VERILATOR
// Assertions to determine correct APB protocol sequencing
default disable iff (!rst_n);
for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_assertions
// when psel is not asserted, the bus is in the idle state
sequence APB_IDLE;
!apb_req[i].psel;
endsequence
// when psel is set and penable is not, it is the setup state
sequence APB_SETUP;
apb_req[i].psel && !apb_req[i].penable;
endsequence
// when psel and penable are set it is the access state
sequence APB_ACCESS;
apb_req[i].psel && apb_req[i].penable;
endsequence
// APB Transfer is APB state going from setup to access
sequence APB_TRANSFER;
APB_SETUP ##1 APB_ACCESS;
endsequence
apb_complete: assert property ( @(posedge clk)
(APB_SETUP |-> APB_TRANSFER));
apb_penable: assert property ( @(posedge clk)
(apb_req[i].penable && apb_req[i].psel && apb_resps[i].pready |=> (!apb_req[i].penable)));
control_stable: assert property ( @(posedge clk)
(APB_TRANSFER |-> $stable({apb_req[i].pwrite, apb_req[i].paddr})));
apb_valid: assert property ( @(posedge clk)
(APB_TRANSFER |-> ((!{apb_req[i].pwrite, apb_req[i].pstrb, apb_req[i].paddr}) !== 1'bx)));
write_stable: assert property ( @(posedge clk)
((apb_req[i].penable && apb_req[i].pwrite) |-> $stable(apb_req[i].pwdata)));
strb_stable: assert property ( @(posedge clk)
((apb_req[i].penable && apb_req[i].pwrite) |-> $stable(apb_req[i].pstrb)));
end
`endif
// pragma translate_on
//-----------------------------------
// Clock generator
//-----------------------------------
clk_rst_gen #(
.ClkPeriod ( CyclTime ),
.RstClkCycles ( 5 )
) i_clk_gen (
.clk_o ( clk ),
.rst_no ( rst_n )
);
//-----------------------------------
// DUT
//-----------------------------------
axi_lite_to_apb #(
.NoApbSlaves ( NoApbSlaves ),
.NoRules ( NoAddrRules ),
.AddrWidth ( AxiAddrWidth ),
.DataWidth ( AxiDataWidth ),
.PipelineRequest ( TbPipelineRequest ),
.PipelineResponse ( TbPipelineResponse ),
.axi_lite_req_t ( axi_req_t ),
.axi_lite_resp_t ( axi_resp_t ),
.apb_req_t ( apb_req_t ),
.apb_resp_t ( apb_resp_t ),
.rule_t ( rule_t )
) i_axi_lite_to_apb_dut (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.axi_lite_req_i ( axi_req ),
.axi_lite_resp_o ( axi_resp ),
.apb_req_o ( apb_req ),
.apb_resp_i ( apb_resps ),
.addr_map_i ( AddrMap )
);
endmodule |
module axi_lite_xbar #(
parameter axi_pkg::xbar_cfg_t Cfg = '0,
parameter type aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type b_chan_t = logic,
parameter type ar_chan_t = logic,
parameter type r_chan_t = logic,
parameter type req_t = logic,
parameter type resp_t = logic,
parameter type rule_t = axi_pkg::xbar_rule_64_t,
// DEPENDENT PARAMETERS, DO NOT OVERWRITE!
parameter int unsigned MstIdxWidth = (Cfg.NoMstPorts > 32'd1) ? $clog2(Cfg.NoMstPorts) : 32'd1
) (
input logic clk_i,
input logic rst_ni,
input logic test_i,
input req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i,
output resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o,
output req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o,
input resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i,
input rule_t [Cfg.NoAddrRules-1:0] addr_map_i,
input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i,
input logic [Cfg.NoSlvPorts-1:0][MstIdxWidth-1:0] default_mst_port_i
);
typedef logic [Cfg.AxiAddrWidth-1:0] addr_t;
typedef logic [Cfg.AxiDataWidth-1:0] data_t;
typedef logic [Cfg.AxiDataWidth/8-1:0] strb_t;
// to account for the decoding error slave
typedef logic [$clog2(Cfg.NoMstPorts + 1)-1:0] mst_port_idx_t;
// full AXI typedef for the decode error slave, id_t and user_t are logic and will be
// removed during logic optimization as they are stable
`AXI_TYPEDEF_AW_CHAN_T(full_aw_chan_t, addr_t, logic, logic)
`AXI_TYPEDEF_W_CHAN_T(full_w_chan_t, data_t, strb_t, logic)
`AXI_TYPEDEF_B_CHAN_T(full_b_chan_t, logic, logic)
`AXI_TYPEDEF_AR_CHAN_T(full_ar_chan_t, addr_t, logic, logic)
`AXI_TYPEDEF_R_CHAN_T(full_r_chan_t, data_t, logic, logic)
`AXI_TYPEDEF_REQ_T(full_req_t, full_aw_chan_t, full_w_chan_t, full_ar_chan_t)
`AXI_TYPEDEF_RESP_T(full_resp_t, full_b_chan_t, full_r_chan_t)
// signals from the axi_lite_demuxes, one index more for decode error routing
req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs;
resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps;
// signals into the axi_lite_muxes, are of type slave as the multiplexer extends the ID
req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs;
resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps;
for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux
logic [MstIdxWidth-1:0] dec_aw, dec_ar;
mst_port_idx_t slv_aw_select, slv_ar_select;
logic dec_aw_error;
logic dec_ar_error;
full_req_t decerr_req;
full_resp_t decerr_resp;
addr_decode #(
.NoIndices ( Cfg.NoMstPorts ),
.NoRules ( Cfg.NoAddrRules ),
.addr_t ( addr_t ),
.rule_t ( rule_t )
) i_axi_aw_decode (
.addr_i ( slv_ports_req_i[i].aw.addr ),
.addr_map_i ( addr_map_i ),
.idx_o ( dec_aw ),
.dec_valid_o ( /*not used*/ ),
.dec_error_o ( dec_aw_error ),
.en_default_idx_i ( en_default_mst_port_i[i] ),
.default_idx_i ( default_mst_port_i[i] )
);
addr_decode #(
.NoIndices ( Cfg.NoMstPorts ),
.addr_t ( addr_t ),
.NoRules ( Cfg.NoAddrRules ),
.rule_t ( rule_t )
) i_axi_ar_decode (
.addr_i ( slv_ports_req_i[i].ar.addr ),
.addr_map_i ( addr_map_i ),
.idx_o ( dec_ar ),
.dec_valid_o ( /*not used*/ ),
.dec_error_o ( dec_ar_error ),
.en_default_idx_i ( en_default_mst_port_i[i] ),
.default_idx_i ( default_mst_port_i[i] )
);
assign slv_aw_select = (dec_aw_error) ?
mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_aw);
assign slv_ar_select = (dec_ar_error) ?
mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_ar);
// make sure that the default slave does not get changed, if there is an unserved Ax
// pragma translate_off
`ifndef VERILATOR
default disable iff (~rst_ni);
default_aw_mst_port_en: assert property(
@(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready)
|=> $stable(en_default_mst_port_i[i]))
else $fatal (1, $sformatf("It is not allowed to change the default mst port\
enable, when there is an unserved Aw beat. Slave Port: %0d", i));
default_aw_mst_port: assert property(
@(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready)
|=> $stable(default_mst_port_i[i]))
else $fatal (1, $sformatf("It is not allowed to change the default mst port\
when there is an unserved Aw beat. Slave Port: %0d", i));
default_ar_mst_port_en: assert property(
@(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready)
|=> $stable(en_default_mst_port_i[i]))
else $fatal (1, $sformatf("It is not allowed to change the enable, when\
there is an unserved Ar beat. Slave Port: %0d", i));
default_ar_mst_port: assert property(
@(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready)
|=> $stable(default_mst_port_i[i]))
else $fatal (1, $sformatf("It is not allowed to change the default mst port\
when there is an unserved Ar beat. Slave Port: %0d", i));
`endif
// pragma translate_on
axi_lite_demux #(
.aw_chan_t ( aw_chan_t ), // AW Channel Type
.w_chan_t ( w_chan_t ), // W Channel Type
.b_chan_t ( b_chan_t ), // B Channel Type
.ar_chan_t ( ar_chan_t ), // AR Channel Type
.r_chan_t ( r_chan_t ), // R Channel Type
.req_t ( req_t ),
.resp_t ( resp_t ),
.NoMstPorts ( Cfg.NoMstPorts + 1 ),
.MaxTrans ( Cfg.MaxMstTrans ),
.FallThrough ( Cfg.FallThrough ),
.SpillAw ( Cfg.LatencyMode[9] ),
.SpillW ( Cfg.LatencyMode[8] ),
.SpillB ( Cfg.LatencyMode[7] ),
.SpillAr ( Cfg.LatencyMode[6] ),
.SpillR ( Cfg.LatencyMode[5] )
) i_axi_lite_demux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Testmode enable
.slv_req_i ( slv_ports_req_i[i] ),
.slv_aw_select_i ( slv_aw_select ),
.slv_ar_select_i ( slv_ar_select ),
.slv_resp_o ( slv_ports_resp_o[i] ),
.mst_reqs_o ( slv_reqs[i] ),
.mst_resps_i ( slv_resps[i] )
);
// connect the decode error module to the last index of the demux master port
// typedef as the decode error slave uses full axi
axi_lite_to_axi #(
.AxiDataWidth ( Cfg.AxiDataWidth ),
.req_lite_t ( req_t ),
.resp_lite_t ( resp_t ),
.req_t ( full_req_t ),
.resp_t ( full_resp_t )
) i_dec_err_conv (
.slv_req_lite_i ( slv_reqs[i][Cfg.NoMstPorts] ),
.slv_resp_lite_o ( slv_resps[i][Cfg.NoMstPorts] ),
.slv_aw_cache_i ( 4'd0 ),
.slv_ar_cache_i ( 4'd0 ),
.mst_req_o ( decerr_req ),
.mst_resp_i ( decerr_resp )
);
axi_err_slv #(
.AxiIdWidth ( 32'd1 ), // ID width is one as defined as logic above
.req_t ( full_req_t ), // AXI request struct
.resp_t ( full_resp_t ), // AXI response struct
.Resp ( axi_pkg::RESP_DECERR ),
.ATOPs ( 1'b0 ), // no ATOPs in AXI4-Lite
.MaxTrans ( 1 ) // Transactions terminate at this slave, and AXI4-Lite
// transactions have only a single beat.
) i_axi_err_slv (
.clk_i ( clk_i ), // Clock
.rst_ni ( rst_ni ), // Asynchronous reset active low
.test_i ( test_i ), // Testmode enable
// slave port
.slv_req_i ( decerr_req ),
.slv_resp_o ( decerr_resp )
);
end
// cross all channels
for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_xbar_slv_cross
for (genvar j = 0; j < Cfg.NoMstPorts; j++) begin : gen_xbar_mst_cross
assign mst_reqs[j][i] = slv_reqs[i][j];
assign slv_resps[i][j] = mst_resps[j][i];
end
end
for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux
axi_lite_mux #(
.aw_chan_t ( aw_chan_t ), // AW Channel Type
.w_chan_t ( w_chan_t ), // W Channel Type
.b_chan_t ( b_chan_t ), // B Channel Type
.ar_chan_t ( ar_chan_t ), // AR Channel Type
.r_chan_t ( r_chan_t ), // R Channel Type
.req_t ( req_t ),
.resp_t ( resp_t ),
.NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module
.MaxTrans ( Cfg.MaxSlvTrans ),
.FallThrough ( Cfg.FallThrough ),
.SpillAw ( Cfg.LatencyMode[4] ),
.SpillW ( Cfg.LatencyMode[3] ),
.SpillB ( Cfg.LatencyMode[2] ),
.SpillAr ( Cfg.LatencyMode[1] ),
.SpillR ( Cfg.LatencyMode[0] )
) i_axi_lite_mux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Test Mode enable
.slv_reqs_i ( mst_reqs[i] ),
.slv_resps_o ( mst_resps[i] ),
.mst_req_o ( mst_ports_req_o[i] ),
.mst_resp_i ( mst_ports_resp_i[i] )
);
end
endmodule |
module axi_sim_mem #(
/// AXI Address Width
parameter int unsigned AddrWidth = 32'd0,
/// AXI Data Width
parameter int unsigned DataWidth = 32'd0,
/// AXI ID Width
parameter int unsigned IdWidth = 32'd0,
/// AXI User Width.
parameter int unsigned UserWidth = 32'd0,
/// AXI4 request struct definition
parameter type req_t = logic,
/// AXI4 response struct definition
parameter type rsp_t = logic,
/// Warn on accesses to uninitialized bytes
parameter bit WarnUninitialized = 1'b0,
/// Application delay (measured after rising clock edge)
parameter time ApplDelay = 0ps,
/// Acquisition delay (measured after rising clock edge)
parameter time AcqDelay = 0ps
) (
/// Rising-edge clock
input logic clk_i,
/// Active-low reset
input logic rst_ni,
/// AXI4 request struct
input req_t axi_req_i,
/// AXI4 response struct
output rsp_t axi_rsp_o
);
localparam int unsigned StrbWidth = DataWidth / 8;
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [IdWidth-1:0] id_t;
typedef logic [StrbWidth-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_t, data_t, id_t, user_t)
logic [7:0] mem[addr_t];
initial begin
automatic ar_t ar_queue[$];
automatic aw_t aw_queue[$];
automatic b_t b_queue[$];
automatic shortint unsigned r_cnt = 0, w_cnt = 0;
axi_rsp_o = '0;
wait (rst_ni);
fork
// AW
forever begin
@(posedge clk_i);
#(ApplDelay);
axi_rsp_o.aw_ready = 1'b1;
#(AcqDelay - ApplDelay);
if (axi_req_i.aw_valid) begin
automatic aw_t aw = axi_req_i.aw;
aw_queue.push_back(aw);
end
end
// W
forever begin
@(posedge clk_i);
#(ApplDelay);
axi_rsp_o.w_ready = 1'b0;
if (aw_queue.size() != 0) begin
axi_rsp_o.w_ready = 1'b1;
#(AcqDelay - ApplDelay);
if (axi_req_i.w_valid) begin
automatic axi_pkg::burst_t burst = aw_queue[0].burst;
automatic axi_pkg::len_t len = aw_queue[0].len;
automatic axi_pkg::size_t size = aw_queue[0].size;
automatic addr_t addr = axi_pkg::beat_addr(aw_queue[0].addr, size, len, burst,
w_cnt);
for (shortint unsigned
i_byte = axi_pkg::beat_lower_byte(addr, size, len, burst, StrbWidth, w_cnt);
i_byte <= axi_pkg::beat_upper_byte(addr, size, len, burst, StrbWidth, w_cnt);
i_byte++) begin
if (axi_req_i.w.strb[i_byte]) begin
automatic addr_t byte_addr = (addr / StrbWidth) * StrbWidth + i_byte;
mem[byte_addr] = axi_req_i.w.data[i_byte*8+:8];
end
end
if (w_cnt == aw_queue[0].len) begin
automatic b_t b_beat = '0;
assert (axi_req_i.w.last) else $error("Expected last beat of W burst!");
b_beat.id = aw_queue[0].id;
b_beat.resp = axi_pkg::RESP_OKAY;
b_queue.push_back(b_beat);
w_cnt = 0;
void'(aw_queue.pop_front());
end else begin
assert (!axi_req_i.w.last) else $error("Did not expect last beat of W burst!");
w_cnt++;
end
end
end
end
// B
forever begin
@(posedge clk_i);
#(ApplDelay);
axi_rsp_o.b_valid = 1'b0;
if (b_queue.size() != 0) begin
axi_rsp_o.b = b_queue[0];
axi_rsp_o.b_valid = 1'b1;
#(AcqDelay - ApplDelay);
if (axi_req_i.b_ready) begin
void'(b_queue.pop_front());
end
end
end
// AR
forever begin
@(posedge clk_i);
#(ApplDelay);
axi_rsp_o.ar_ready = 1'b1;
#(AcqDelay - ApplDelay);
if (axi_req_i.ar_valid) begin
automatic ar_t ar = axi_req_i.ar;
ar_queue.push_back(ar);
end
end
// R
forever begin
@(posedge clk_i);
#(ApplDelay);
axi_rsp_o.r_valid = 1'b0;
if (ar_queue.size() != 0) begin
automatic axi_pkg::burst_t burst = ar_queue[0].burst;
automatic axi_pkg::len_t len = ar_queue[0].len;
automatic axi_pkg::size_t size = ar_queue[0].size;
automatic addr_t addr = axi_pkg::beat_addr(ar_queue[0].addr, size, len, burst, r_cnt);
automatic r_t r_beat = '0;
r_beat.data = 'x;
r_beat.id = ar_queue[0].id;
r_beat.resp = axi_pkg::RESP_OKAY;
for (shortint unsigned
i_byte = axi_pkg::beat_lower_byte(addr, size, len, burst, StrbWidth, r_cnt);
i_byte <= axi_pkg::beat_upper_byte(addr, size, len, burst, StrbWidth, r_cnt);
i_byte++) begin
automatic addr_t byte_addr = (addr / StrbWidth) * StrbWidth + i_byte;
if (!mem.exists(byte_addr)) begin
if (WarnUninitialized) begin
$warning("Access to non-initialized byte at address 0x%016x by ID 0x%x.", byte_addr,
r_beat.id);
end
r_beat.data[i_byte*8+:8] = 'x;
end else begin
r_beat.data[i_byte*8+:8] = mem[byte_addr];
end
end
if (r_cnt == ar_queue[0].len) begin
r_beat.last = 1'b1;
end
axi_rsp_o.r = r_beat;
axi_rsp_o.r_valid = 1'b1;
#(AcqDelay - ApplDelay);
if (axi_req_i.r_ready) begin
if (r_beat.last) begin
r_cnt = 0;
void'(ar_queue.pop_front());
end else begin
r_cnt++;
end
end
end
end
join
end
// Parameter Assertions
initial begin
assert (AddrWidth != 0) else $fatal("AddrWidth must be non-zero!", 1);
assert (DataWidth != 0) else $fatal("DataWidth must be non-zero!", 1);
assert (IdWidth != 0) else $fatal("IdWidth must be non-zero!", 1);
assert (UserWidth != 0) else $fatal("UserWidth must be non-zero!", 1);
end
endmodule |
module axi_burst_splitter #(
// Maximum number of AXI read bursts outstanding at the same time
parameter int unsigned MaxReadTxns = 32'd0,
// Maximum number of AXI write bursts outstanding at the same time
parameter int unsigned MaxWriteTxns = 32'd0,
// AXI Bus Types
parameter int unsigned AddrWidth = 32'd0,
parameter int unsigned DataWidth = 32'd0,
parameter int unsigned IdWidth = 32'd0,
parameter int unsigned UserWidth = 32'd0,
parameter type req_t = logic,
parameter type resp_t = logic
) (
input logic clk_i,
input logic rst_ni,
// Input / Slave Port
input req_t slv_req_i,
output resp_t slv_resp_o,
// Output / Master Port
output req_t mst_req_o,
input resp_t mst_resp_i
);
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [IdWidth-1:0] id_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
// Demultiplex between supported and unsupported transactions.
req_t act_req, unsupported_req;
resp_t act_resp, unsupported_resp;
logic sel_aw_unsupported, sel_ar_unsupported;
localparam int unsigned MaxTxns = (MaxReadTxns > MaxWriteTxns) ? MaxReadTxns : MaxWriteTxns;
axi_demux #(
.AxiIdWidth ( IdWidth ),
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.req_t ( req_t ),
.resp_t ( resp_t ),
.NoMstPorts ( 2 ),
.MaxTrans ( MaxTxns ),
.AxiLookBits ( IdWidth ),
.FallThrough ( 1'b1 ),
.SpillAw ( 1'b0 ),
.SpillW ( 1'b0 ),
.SpillB ( 1'b0 ),
.SpillAr ( 1'b0 ),
.SpillR ( 1'b0 ),
.aw_chan_width(35+IdWidth+AddrWidth+UserWidth),
.ar_chan_width(35+IdWidth+AddrWidth+UserWidth)
) i_demux_supported_vs_unsupported (
.clk_i,
.rst_ni,
.test_i ( 1'b0 ),
.slv_req_i,
.slv_aw_select_i ( sel_aw_unsupported ),
.slv_ar_select_i ( sel_ar_unsupported ),
.slv_resp_o,
.mst_reqs_o ( {unsupported_req, act_req} ),
.mst_resps_i ( {unsupported_resp, act_resp} )
);
// Define supported transactions.
function bit txn_supported(axi_pkg::atop_t atop, axi_pkg::burst_t burst, axi_pkg::cache_t cache,
axi_pkg::len_t len);
// Single-beat transactions do not need splitting, so all are supported.
if (len == '0) return 1'b1;
// Wrapping bursts are currently not supported.
if (burst == axi_pkg::BURST_WRAP) return 1'b0;
// ATOPs are not supported.
if (atop != '0) return 1'b0;
// The AXI Spec (A3.4.1) only allows splitting non-modifiable transactions ..
if (!axi_pkg::modifiable(cache)) begin
// .. if they are INCR bursts and longer than 16 beats.
return (burst == axi_pkg::BURST_INCR) & (len > 16);
end
// All other transactions are supported.
return 1'b1;
endfunction
assign sel_aw_unsupported = ~txn_supported(slv_req_i.aw.atop, slv_req_i.aw.burst,
slv_req_i.aw.cache, slv_req_i.aw.len);
assign sel_ar_unsupported = ~txn_supported('0, slv_req_i.ar.burst,
slv_req_i.ar.cache, slv_req_i.ar.len);
// Respond to unsupported transactions with slave errors.
axi_err_slv #(
.AxiIdWidth ( IdWidth ),
.req_t ( req_t ),
.resp_t ( resp_t ),
.Resp ( axi_pkg::RESP_SLVERR ),
.ATOPs ( 1'b0 ), // The burst splitter does not support ATOPs.
.MaxTrans ( 1 ) // Splitting bursts implies a low-performance bus.
) i_err_slv (
.clk_i,
.rst_ni,
.test_i ( 1'b0 ),
.slv_req_i ( unsupported_req ),
.slv_resp_o ( unsupported_resp )
);
// --------------------------------------------------
// AW Channel
// --------------------------------------------------
logic w_cnt_dec, w_cnt_req, w_cnt_gnt, w_cnt_err;
axi_pkg::len_t w_cnt_len;
axi_burst_splitter_ax_chan #(
.chan_t ( aw_chan_t ),
.IdWidth ( IdWidth ),
.MaxTxns ( MaxWriteTxns )
) i_axi_burst_splitter_aw_chan (
.clk_i,
.rst_ni,
.ax_i ( act_req.aw ),
.ax_valid_i ( act_req.aw_valid ),
.ax_ready_o ( act_resp.aw_ready ),
.ax_o ( mst_req_o.aw ),
.ax_valid_o ( mst_req_o.aw_valid ),
.ax_ready_i ( mst_resp_i.aw_ready ),
.cnt_id_i ( mst_resp_i.b.id ),
.cnt_len_o ( w_cnt_len ),
.cnt_set_err_i ( mst_resp_i.b.resp[1] ),
.cnt_err_o ( w_cnt_err ),
.cnt_dec_i ( w_cnt_dec ),
.cnt_req_i ( w_cnt_req ),
.cnt_gnt_o ( w_cnt_gnt )
);
// --------------------------------------------------
// W Channel
// --------------------------------------------------
// Feed through, except `last`, which is always set.
always_comb begin
mst_req_o.w = act_req.w;
mst_req_o.w.last = 1'b1; // overwrite last flag
end
assign mst_req_o.w_valid = act_req.w_valid;
assign act_resp.w_ready = mst_resp_i.w_ready;
// --------------------------------------------------
// B Channel
// --------------------------------------------------
// Filter B response, except for the last one
enum logic {BReady, BWait} b_state_d, b_state_q;
logic b_err_d, b_err_q;
always_comb begin
mst_req_o.b_ready = 1'b0;
act_resp.b = '0;
act_resp.b_valid = 1'b0;
w_cnt_dec = 1'b0;
w_cnt_req = 1'b0;
b_err_d = b_err_q;
b_state_d = b_state_q;
unique case (b_state_q)
BReady: begin
if (mst_resp_i.b_valid) begin
w_cnt_req = 1'b1;
if (w_cnt_gnt) begin
if (w_cnt_len == 8'd0) begin
act_resp.b = mst_resp_i.b;
if (w_cnt_err) begin
act_resp.b.resp = axi_pkg::RESP_SLVERR;
end
act_resp.b_valid = 1'b1;
w_cnt_dec = 1'b1;
if (act_req.b_ready) begin
mst_req_o.b_ready = 1'b1;
end else begin
b_state_d = BWait;
b_err_d = w_cnt_err;
end
end else begin
mst_req_o.b_ready = 1'b1;
w_cnt_dec = 1'b1;
end
end
end
end
BWait: begin
act_resp.b = mst_resp_i.b;
if (b_err_q) begin
act_resp.b.resp = axi_pkg::RESP_SLVERR;
end
act_resp.b_valid = 1'b1;
if (mst_resp_i.b_valid && act_req.b_ready) begin
mst_req_o.b_ready = 1'b1;
b_state_d = BReady;
end
end
default: /*do nothing*/;
endcase
end
// --------------------------------------------------
// AR Channel
// --------------------------------------------------
// See description of `ax_chan` module.
logic r_cnt_dec, r_cnt_req, r_cnt_gnt;
axi_pkg::len_t r_cnt_len;
axi_burst_splitter_ax_chan #(
.chan_t ( ar_chan_t ),
.IdWidth ( IdWidth ),
.MaxTxns ( MaxReadTxns )
) i_axi_burst_splitter_ar_chan (
.clk_i,
.rst_ni,
.ax_i ( act_req.ar ),
.ax_valid_i ( act_req.ar_valid ),
.ax_ready_o ( act_resp.ar_ready ),
.ax_o ( mst_req_o.ar ),
.ax_valid_o ( mst_req_o.ar_valid ),
.ax_ready_i ( mst_resp_i.ar_ready ),
.cnt_id_i ( mst_resp_i.r.id ),
.cnt_len_o ( r_cnt_len ),
.cnt_set_err_i ( 1'b0 ),
.cnt_err_o ( ),
.cnt_dec_i ( r_cnt_dec ),
.cnt_req_i ( r_cnt_req ),
.cnt_gnt_o ( r_cnt_gnt )
);
// --------------------------------------------------
// R Channel
// --------------------------------------------------
// Reconstruct `last`, feed rest through.
logic r_last_d, r_last_q;
enum logic {RFeedthrough, RWait} r_state_d, r_state_q;
always_comb begin
r_cnt_dec = 1'b0;
r_cnt_req = 1'b0;
r_last_d = r_last_q;
r_state_d = r_state_q;
mst_req_o.r_ready = 1'b0;
act_resp.r = mst_resp_i.r;
act_resp.r.last = 1'b0;
act_resp.r_valid = 1'b0;
unique case (r_state_q)
RFeedthrough: begin
// If downstream has an R beat and the R counters can give us the remaining length of
// that burst, ...
if (mst_resp_i.r_valid) begin
r_cnt_req = 1'b1;
if (r_cnt_gnt) begin
r_last_d = (r_cnt_len == 8'd0);
act_resp.r.last = r_last_d;
// Decrement the counter.
r_cnt_dec = 1'b1;
// Try to forward the beat upstream.
act_resp.r_valid = 1'b1;
if (act_req.r_ready) begin
// Acknowledge downstream.
mst_req_o.r_ready = 1'b1;
end else begin
// Wait for upstream to become ready.
r_state_d = RWait;
end
end
end
end
RWait: begin
act_resp.r.last = r_last_q;
act_resp.r_valid = mst_resp_i.r_valid;
if (mst_resp_i.r_valid && act_req.r_ready) begin
mst_req_o.r_ready = 1'b1;
r_state_d = RFeedthrough;
end
end
default: /*do nothing*/;
endcase
end
// --------------------------------------------------
// Flip-Flops
// --------------------------------------------------
`FFARN(b_err_q, b_err_d, 1'b0, clk_i, rst_ni)
`FFARN(b_state_q, b_state_d, BReady, clk_i, rst_ni)
`FFARN(r_last_q, r_last_d, 1'b0, clk_i, rst_ni)
`FFARN(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni)
// --------------------------------------------------
// Assumptions and assertions
// --------------------------------------------------
`ifndef VERILATOR
// pragma translate_off
default disable iff (!rst_ni);
// Inputs
assume property (@(posedge clk_i) slv_req_i.aw_valid |->
txn_supported(slv_req_i.aw.atop, slv_req_i.aw.burst, slv_req_i.aw.cache, slv_req_i.aw.len)
) else $warning("Unsupported AW transaction received, returning slave error!");
assume property (@(posedge clk_i) slv_req_i.ar_valid |->
txn_supported('0, slv_req_i.ar.burst, slv_req_i.ar.cache, slv_req_i.ar.len)
) else $warning("Unsupported AR transaction received, returning slave error!");
assume property (@(posedge clk_i) slv_req_i.aw_valid |->
slv_req_i.aw.atop == '0 || slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_ATOMICSTORE
) else $fatal(1, "Unsupported ATOP that gives rise to a R response received,\
cannot respond in protocol-compliant manner!");
// Outputs
assert property (@(posedge clk_i) mst_req_o.aw_valid |-> mst_req_o.aw.len == '0)
else $fatal(1, "AW burst longer than a single beat emitted!");
assert property (@(posedge clk_i) mst_req_o.ar_valid |-> mst_req_o.ar.len == '0)
else $fatal(1, "AR burst longer than a single beat emitted!");
// pragma translate_on
`endif
endmodule |
module axi_burst_splitter_ax_chan #(
parameter type chan_t = logic,
parameter int unsigned IdWidth = 0,
parameter int unsigned MaxTxns = 0,
parameter type id_t = logic[IdWidth-1:0]
) (
input logic clk_i,
input logic rst_ni,
input chan_t ax_i,
input logic ax_valid_i,
output logic ax_ready_o,
output chan_t ax_o,
output logic ax_valid_o,
input logic ax_ready_i,
input id_t cnt_id_i,
output axi_pkg::len_t cnt_len_o,
input logic cnt_set_err_i,
output logic cnt_err_o,
input logic cnt_dec_i,
input logic cnt_req_i,
output logic cnt_gnt_o
);
typedef logic[IdWidth-1:0] cnt_id_t;
logic cnt_alloc_req, cnt_alloc_gnt;
axi_burst_splitter_counters #(
.MaxTxns ( MaxTxns ),
.IdWidth ( IdWidth )
) i_axi_burst_splitter_counters (
.clk_i,
.rst_ni,
.alloc_id_i ( ax_i.id ),
.alloc_len_i ( ax_i.len ),
.alloc_req_i ( cnt_alloc_req ),
.alloc_gnt_o ( cnt_alloc_gnt ),
.cnt_id_i ( cnt_id_i ),
.cnt_len_o ( cnt_len_o ),
.cnt_set_err_i ( cnt_set_err_i ),
.cnt_err_o ( cnt_err_o ),
.cnt_dec_i ( cnt_dec_i ),
.cnt_req_i ( cnt_req_i ),
.cnt_gnt_o ( cnt_gnt_o )
);
chan_t ax_d, ax_q;
enum logic {Idle, Busy} state_d, state_q;
always_comb begin
cnt_alloc_req = 1'b0;
ax_d = ax_q;
state_d = state_q;
ax_o = '0;
ax_valid_o = 1'b0;
ax_ready_o = 1'b0;
unique case (state_q)
Idle: begin
if (ax_valid_i && cnt_alloc_gnt) begin
if (ax_i.len == '0) begin // No splitting required -> feed through.
ax_o = ax_i;
ax_valid_o = 1'b1;
// As soon as downstream is ready, allocate a counter and acknowledge upstream.
if (ax_ready_i) begin
cnt_alloc_req = 1'b1;
ax_ready_o = 1'b1;
end
end else begin // Splitting required.
// Store Ax, allocate a counter, and acknowledge upstream.
ax_d = ax_i;
cnt_alloc_req = 1'b1;
ax_ready_o = 1'b1;
// Try to feed first burst through.
ax_o = ax_d;
ax_o.len = '0;
ax_valid_o = 1'b1;
if (ax_ready_i) begin
// Reduce number of bursts still to be sent by one and increment address.
ax_d.len--;
if (ax_d.burst == axi_pkg::BURST_INCR) begin
ax_d.addr += (1 << ax_d.size);
end
end
state_d = Busy;
end
end
end
Busy: begin
// Sent next burst from split.
ax_o = ax_q;
ax_o.len = '0;
ax_valid_o = 1'b1;
if (ax_ready_i) begin
if (ax_q.len == '0) begin
// If this was the last burst, go back to idle.
state_d = Idle;
end else begin
// Otherwise, continue with the next burst.
ax_d.len--;
if (ax_q.burst == axi_pkg::BURST_INCR) begin
ax_d.addr += (1 << ax_q.size);
end
end
end
end
default: /*do nothing*/;
endcase
end
// registers
`FFARN(ax_q, ax_d, '0, clk_i, rst_ni)
`FFARN(state_q, state_d, Idle, clk_i, rst_ni)
endmodule |
module axi_burst_splitter_counters #(
parameter int unsigned MaxTxns = 0,
parameter int unsigned IdWidth = 0,
parameter type id_t = logic [IdWidth-1:0]
) (
input logic clk_i,
input logic rst_ni,
input id_t alloc_id_i,
input axi_pkg::len_t alloc_len_i,
input logic alloc_req_i,
output logic alloc_gnt_o,
input id_t cnt_id_i,
output axi_pkg::len_t cnt_len_o,
input logic cnt_set_err_i,
output logic cnt_err_o,
input logic cnt_dec_i,
input logic cnt_req_i,
output logic cnt_gnt_o
);
localparam int unsigned CntIdxWidth = (MaxTxns > 1) ? $clog2(MaxTxns) : 32'd1;
typedef logic [CntIdxWidth-1:0] cnt_idx_t;
typedef logic [$bits(axi_pkg::len_t):0] cnt_t;
logic [MaxTxns-1:0] cnt_dec, cnt_free, cnt_set, err_d, err_q;
cnt_t cnt_inp;
cnt_t [MaxTxns-1:0] cnt_oup;
cnt_idx_t cnt_free_idx, cnt_r_idx;
for (genvar i = 0; i < MaxTxns; i++) begin : gen_cnt
counter #(
.WIDTH ( $bits(cnt_t) )
) i_cnt (
.clk_i,
.rst_ni,
.clear_i ( 1'b0 ),
.en_i ( cnt_dec[i] ),
.load_i ( cnt_set[i] ),
.down_i ( 1'b1 ),
.d_i ( cnt_inp ),
.q_o ( cnt_oup[i] ),
.overflow_o ( ) // not used
);
assign cnt_free[i] = (cnt_oup[i] == '0);
end
assign cnt_inp = {1'b0, alloc_len_i} + 1;
lzc #(
.WIDTH ( MaxTxns ),
.MODE ( 1'b0 ) // start counting at index 0
) i_lzc (
.in_i ( cnt_free ),
.cnt_o ( cnt_free_idx ),
.empty_o ( )
);
logic idq_inp_req, idq_inp_gnt,
idq_oup_gnt, idq_oup_valid, idq_oup_pop;
id_queue #(
.ID_WIDTH ( $bits(id_t) ),
.CAPACITY ( MaxTxns ),
.data_t ( cnt_idx_t )
) i_idq (
.clk_i,
.rst_ni,
.inp_id_i ( alloc_id_i ),
.inp_data_i ( cnt_free_idx ),
.inp_req_i ( idq_inp_req ),
.inp_gnt_o ( idq_inp_gnt ),
.exists_data_i ( '0 ),
.exists_mask_i ( '0 ),
.exists_req_i ( 1'b0 ),
.exists_o (/* keep open */),
.exists_gnt_o (/* keep open */),
.oup_id_i ( cnt_id_i ),
.oup_pop_i ( idq_oup_pop ),
.oup_req_i ( cnt_req_i ),
.oup_data_o ( cnt_r_idx ),
.oup_data_valid_o ( idq_oup_valid ),
.oup_gnt_o ( idq_oup_gnt )
);
assign idq_inp_req = alloc_req_i & alloc_gnt_o;
assign alloc_gnt_o = idq_inp_gnt & |(cnt_free);
assign cnt_gnt_o = idq_oup_gnt & idq_oup_valid;
logic [8:0] read_len;
assign read_len = cnt_oup[cnt_r_idx] - 1;
assign cnt_len_o = read_len[7:0];
assign idq_oup_pop = cnt_req_i & cnt_gnt_o & cnt_dec_i & (cnt_len_o == 8'd0);
always_comb begin
cnt_dec = '0;
cnt_dec[cnt_r_idx] = cnt_req_i & cnt_gnt_o & cnt_dec_i;
end
always_comb begin
cnt_set = '0;
cnt_set[cnt_free_idx] = alloc_req_i & alloc_gnt_o;
end
always_comb begin
err_d = err_q;
cnt_err_o = err_q[cnt_r_idx];
if (cnt_req_i && cnt_gnt_o && cnt_set_err_i) begin
err_d[cnt_r_idx] = 1'b1;
cnt_err_o = 1'b1;
end
if (alloc_req_i && alloc_gnt_o) begin
err_d[cnt_free_idx] = 1'b0;
end
end
// registers
`FFARN(err_q, err_d, '0, clk_i, rst_ni)
`ifndef VERILATOR
// pragma translate_off
assume property (@(posedge clk_i) idq_oup_gnt |-> idq_oup_valid)
else $warning("Invalid output at ID queue, read not granted!");
// pragma translate_on
`endif
endmodule |
module axi_join_intf (
AXI_BUS.Slave in,
AXI_BUS.Master out
);
`AXI_ASSIGN(out, in)
// pragma translate_off
`ifndef VERILATOR
initial begin
assert(in.AXI_ADDR_WIDTH == out.AXI_ADDR_WIDTH);
assert(in.AXI_DATA_WIDTH == out.AXI_DATA_WIDTH);
assert(in.AXI_ID_WIDTH <= out.AXI_ID_WIDTH );
assert(in.AXI_USER_WIDTH == out.AXI_USER_WIDTH);
end
`endif
// pragma translate_on
endmodule |
module axi_isolate #(
parameter int unsigned NumPending = 32'd16, // Number of pending requests per channel
parameter type req_t = logic, // AXI request struct definition
parameter type resp_t = logic // AXI response struct definition
) (
input logic clk_i, // clock
input logic rst_ni, // reset
input req_t slv_req_i, // slave port request struct
output resp_t slv_resp_o, // slave port response struct
output req_t mst_req_o, // master port request struct
input resp_t mst_resp_i, // master port response struct
input logic isolate_i, // isolate master port from slave port
output logic isolated_o // master port is isolated from slave port
);
// plus 1 in clog for accouning no open transaction, plus one bit for atomic injection
localparam int unsigned CounterWidth = $clog2(NumPending + 32'd1) + 32'd1;
typedef logic [CounterWidth-1:0] cnt_t;
typedef enum logic [1:0] {
Normal,
Hold,
Drain,
Isolate
} isolate_state_e;
isolate_state_e state_aw_d, state_aw_q, state_ar_d, state_ar_q;
logic update_aw_state, update_ar_state;
cnt_t pending_aw_d, pending_aw_q;
logic update_aw_cnt;
cnt_t pending_w_d, pending_w_q;
logic update_w_cnt, connect_w;
cnt_t pending_ar_d, pending_ar_q;
logic update_ar_cnt;
`FFLARN(pending_aw_q, pending_aw_d, update_aw_cnt, '0, clk_i, rst_ni)
`FFLARN(pending_w_q, pending_w_d, update_w_cnt, '0, clk_i, rst_ni)
`FFLARN(pending_ar_q, pending_ar_d, update_ar_cnt, '0, clk_i, rst_ni)
`FFLARN(state_aw_q, state_aw_d, update_aw_state, Isolate, clk_i, rst_ni)
`FFLARN(state_ar_q, state_ar_d, update_ar_state, Isolate, clk_i, rst_ni)
// Update counters.
always_comb begin
pending_aw_d = pending_aw_q;
update_aw_cnt = 1'b0;
pending_w_d = pending_w_q;
update_w_cnt = 1'b0;
connect_w = 1'b0;
pending_ar_d = pending_ar_q;
update_ar_cnt = 1'b0;
// write counters
if (mst_req_o.aw_valid && (state_aw_q == Normal)) begin
pending_aw_d++;
update_aw_cnt = 1'b1;
pending_w_d++;
update_w_cnt = 1'b1;
connect_w = 1'b1;
if (mst_req_o.aw.atop[axi_pkg::ATOP_R_RESP]) begin
pending_ar_d++; // handle atomic with read response by injecting a count in AR
update_ar_cnt = 1'b1;
end
end
if (mst_req_o.w_valid && mst_resp_i.w_ready && mst_req_o.w.last) begin
pending_w_d--;
update_w_cnt = 1'b1;
end
if (mst_resp_i.b_valid && mst_req_o.b_ready) begin
pending_aw_d--;
update_aw_cnt = 1'b1;
end
// read counters
if (mst_req_o.ar_valid && (state_ar_q == Normal)) begin
pending_ar_d++;
update_ar_cnt = 1'b1;
end
if (mst_resp_i.r_valid && mst_req_o.r_ready && mst_resp_i.r.last) begin
pending_ar_d--;
update_ar_cnt = 1'b1;
end
end
// Perform isolation.
always_comb begin
// Default assignments
state_aw_d = state_aw_q;
update_aw_state = 1'b0;
state_ar_d = state_ar_q;
update_ar_state = 1'b0;
// Connect channel per default
mst_req_o = slv_req_i;
slv_resp_o = mst_resp_i;
/////////////////////////////////////////////////////////////
// Write transaction
/////////////////////////////////////////////////////////////
unique case (state_aw_q)
Normal: begin // Normal operation
// Cut valid handshake if a counter capacity is reached. It has to check AR counter in case
// of atomics. Counters are wide enough to account for injected count in the read response
// counter.
if (pending_aw_q >= cnt_t'(NumPending) || pending_ar_q >= cnt_t'(2*NumPending)
|| (pending_w_q >= cnt_t'(NumPending))) begin
mst_req_o.aw_valid = 1'b0;
slv_resp_o.aw_ready = 1'b0;
if (isolate_i) begin
state_aw_d = Drain;
update_aw_state = 1'b1;
end
end else begin
// here the AW handshake is connected normally
if (slv_req_i.aw_valid && !mst_resp_i.aw_ready) begin
state_aw_d = Hold;
update_aw_state = 1'b1;
end else begin
if (isolate_i) begin
state_aw_d = Drain;
update_aw_state = 1'b1;
end
end
end
end
Hold: begin // Hold the valid signal on 1'b1 if there was no transfer
mst_req_o.aw_valid = 1'b1;
// aw_ready normal connected
if (mst_resp_i.aw_ready) begin
update_aw_state = 1'b1;
state_aw_d = isolate_i ? Drain : Normal;
end
end
Drain: begin // cut the AW channel until counter is zero
mst_req_o.aw = '0;
mst_req_o.aw_valid = 1'b0;
slv_resp_o.aw_ready = 1'b0;
if (pending_aw_q == '0) begin
state_aw_d = Isolate;
update_aw_state = 1'b1;
end
end
Isolate: begin // Cut the signals to the outputs
mst_req_o.aw = '0;
mst_req_o.aw_valid = 1'b0;
slv_resp_o.aw_ready = 1'b0;
slv_resp_o.b = '0;
slv_resp_o.b_valid = 1'b0;
mst_req_o.b_ready = 1'b0;
if (!isolate_i) begin
state_aw_d = Normal;
update_aw_state = 1'b1;
end
end
default: /*do nothing*/;
endcase
// W channel is cut as long the counter is zero and not explicitly unlocked through an AW.
if ((pending_w_q == '0) && !connect_w ) begin
mst_req_o.w = '0;
mst_req_o.w_valid = 1'b0;
slv_resp_o.w_ready = 1'b0;
end
/////////////////////////////////////////////////////////////
// Read transaction
/////////////////////////////////////////////////////////////
unique case (state_ar_q)
Normal: begin
// cut handshake if counter capacity is reached
if (pending_ar_q >= NumPending) begin
mst_req_o.ar_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
if (isolate_i) begin
state_ar_d = Drain;
update_ar_state = 1'b1;
end
end else begin
// here the AR handshake is connected normally
if (slv_req_i.ar_valid && !mst_resp_i.ar_ready) begin
state_ar_d = Hold;
update_ar_state = 1'b1;
end else begin
if (isolate_i) begin
state_ar_d = Drain;
update_ar_state = 1'b1;
end
end
end
end
Hold: begin // Hold the valid signal on 1'b1 if there was no transfer
mst_req_o.ar_valid = 1'b1;
// ar_ready normal connected
if (mst_resp_i.ar_ready) begin
update_ar_state = 1'b1;
state_ar_d = isolate_i ? Drain : Normal;
end
end
Drain: begin
mst_req_o.ar = '0;
mst_req_o.ar_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
if (pending_ar_q == '0) begin
state_ar_d = Isolate;
update_ar_state = 1'b1;
end
end
Isolate: begin
mst_req_o.ar = '0;
mst_req_o.ar_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
slv_resp_o.r = '0;
slv_resp_o.r_valid = 1'b0;
mst_req_o.r_ready = 1'b0;
if (!isolate_i) begin
state_ar_d = Normal;
update_ar_state = 1'b1;
end
end
default: /*do nothing*/;
endcase
end
// the isolated output signal
assign isolated_o = (state_aw_q == Isolate && state_ar_q == Isolate);
// pragma translate_off
`ifndef VERILATOR
initial begin
assume (NumPending > 0) else $fatal(1, "At least one pending transaction required.");
end
default disable iff (!rst_ni);
aw_overflow: assert property (@(posedge clk_i)
(pending_aw_q == '1) |=> (pending_aw_q != '0)) else
$fatal(1, "pending_aw_q overflowed");
ar_overflow: assert property (@(posedge clk_i)
(pending_ar_q == '1) |=> (pending_ar_q != '0)) else
$fatal(1, "pending_ar_q overflowed");
aw_underflow: assert property (@(posedge clk_i)
(pending_aw_q == '0) |=> (pending_aw_q != '1)) else
$fatal(1, "pending_aw_q underflowed");
ar_underflow: assert property (@(posedge clk_i)
(pending_ar_q == '0) |=> (pending_ar_q != '1)) else
$fatal(1, "pending_ar_q underflowed");
`endif
// pragma translate_on
endmodule |
module axi_isolate_intf #(
parameter int unsigned NUM_PENDING = 32'd16, // Number of pending requests
parameter int unsigned AXI_ID_WIDTH = 32'd0, // AXI ID width
parameter int unsigned AXI_ADDR_WIDTH = 32'd0, // AXI address width
parameter int unsigned AXI_DATA_WIDTH = 32'd0, // AXI data width
parameter int unsigned AXI_USER_WIDTH = 32'd0 // AXI user width
) (
input logic clk_i, // clock
input logic rst_ni, // asynchronous reset active low
AXI_BUS.Slave slv, // slave port
AXI_BUS.Master mst, // master port
input logic isolate_i, // isolate master port from slave port
output logic isolated_o // master port is isolated from slave port
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t slv_req, mst_req;
resp_t slv_resp, mst_resp;
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
`AXI_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_ASSIGN_TO_RESP(mst_resp, mst)
axi_isolate #(
.NumPending ( NUM_PENDING ), // Number of pending requests per channel
.req_t ( req_t ), // AXI request struct definition
.resp_t ( resp_t ) // AXI response struct definition
) i_axi_isolate (
.clk_i, // clock
.rst_ni, // reset
.slv_req_i ( slv_req ), // slave port request struct
.slv_resp_o ( slv_resp ), // slave port response struct
.mst_req_o ( mst_req ), // master port request struct
.mst_resp_i ( mst_resp ), // master port response struct
.isolate_i, // isolate master port from slave port
.isolated_o // master port is isolated from slave port
);
// pragma translate_off
`ifndef VERILATOR
initial begin
assume (AXI_ID_WIDTH > 0) else $fatal(1, "AXI_ID_WIDTH has to be > 0.");
assume (AXI_ADDR_WIDTH > 0) else $fatal(1, "AXI_ADDR_WIDTH has to be > 0.");
assume (AXI_DATA_WIDTH > 0) else $fatal(1, "AXI_DATA_WIDTH has to be > 0.");
assume (AXI_USER_WIDTH > 0) else $fatal(1, "AXI_USER_WIDTH has to be > 0.");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_join_intf (
AXI_LITE.Slave in,
AXI_LITE.Master out
);
`AXI_LITE_ASSIGN(out, in)
// pragma translate_off
`ifndef VERILATOR
initial begin
assert(in.AXI_ADDR_WIDTH == out.AXI_ADDR_WIDTH);
assert(in.AXI_DATA_WIDTH == out.AXI_DATA_WIDTH);
end
`endif
// pragma translate_on
endmodule |
module axi_demux #(
parameter int unsigned AxiIdWidth = 32'd0,
parameter type aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type b_chan_t = logic,
parameter type ar_chan_t = logic,
parameter type r_chan_t = logic,
parameter type req_t = logic,
parameter type resp_t = logic,
parameter int unsigned NoMstPorts = 32'd0,
parameter int unsigned MaxTrans = 32'd8,
parameter int unsigned AxiLookBits = 32'd3,
parameter bit UniqueIds = 1'b0,
parameter bit FallThrough = 1'b0,
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0,
parameter int unsigned aw_chan_width = 32'd0,
parameter int unsigned ar_chan_width = 32'd0,
// Dependent parameters, DO NOT OVERRIDE!
parameter int unsigned SelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1,
parameter type select_t = logic [SelectWidth-1:0]
) (
input logic clk_i,
input logic rst_ni,
input logic test_i,
// Slave Port
input req_t slv_req_i,
input select_t slv_aw_select_i,
input select_t slv_ar_select_i,
output resp_t slv_resp_o,
// Master Ports
output req_t [NoMstPorts-1:0] mst_reqs_o,
input resp_t [NoMstPorts-1:0] mst_resps_i
);
localparam int unsigned IdCounterWidth = MaxTrans > 1 ? $clog2(MaxTrans) : 1;
//--------------------------------------
// Typedefs for the FIFOs / Queues
//--------------------------------------
typedef struct packed {
aw_chan_t aw_chan;
select_t aw_select;
} aw_chan_select_t;
typedef struct packed {
ar_chan_t ar_chan;
select_t ar_select;
} ar_chan_select_t;
// pass through if only one master port
if (NoMstPorts == 32'h1) begin : gen_no_demux
assign mst_reqs_o[0] = slv_req_i;
assign slv_resp_o = mst_resps_i;
// other non degenerate cases
end else begin : gen_demux
//--------------------------------------
//--------------------------------------
// Signal Declarations
//--------------------------------------
//--------------------------------------
//--------------------------------------
// Write Transaction
//--------------------------------------
// comes from spill register at input
aw_chan_select_t slv_aw_chan_select;
logic slv_aw_valid, slv_aw_ready;
// AW ID counter
select_t lookup_aw_select;
logic aw_select_occupied, aw_id_cnt_full;
logic aw_push;
// Upon an ATOP load, inject IDs from the AW into the AR channel
logic atop_inject;
// W FIFO: stores the decision to which master W beats should go
logic w_fifo_pop;
logic w_fifo_full, w_fifo_empty;
select_t w_select;
// Register which locks the AW valid signal
logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock;
logic aw_valid, aw_ready;
// W channel from spill reg
w_chan_t slv_w_chan;
logic slv_w_valid, slv_w_ready;
// B channles input into the arbitration
b_chan_t [NoMstPorts-1:0] mst_b_chans;
logic [NoMstPorts-1:0] mst_b_valids, mst_b_readies;
// B channel to spill register
b_chan_t slv_b_chan;
logic slv_b_valid, slv_b_ready;
//--------------------------------------
// Read Transaction
//--------------------------------------
// comes from spill register at input
ar_chan_select_t slv_ar_chan_select;
logic slv_ar_valid, slv_ar_ready;
// AR ID counter
select_t lookup_ar_select;
logic ar_select_occupied, ar_id_cnt_full;
logic ar_push;
// Register which locks the AR valid signel
logic lock_ar_valid_d, lock_ar_valid_q, load_ar_lock;
logic ar_valid, ar_ready;
// R channles input into the arbitration
r_chan_t [NoMstPorts-1:0] mst_r_chans;
logic [NoMstPorts-1:0] mst_r_valids, mst_r_readies;
// R channel to spill register
r_chan_t slv_r_chan;
logic slv_r_valid, slv_r_ready;
//--------------------------------------
//--------------------------------------
// Channel Control
//--------------------------------------
//--------------------------------------
//--------------------------------------
// AW Channel
//--------------------------------------
// spill register at the channel input
// Workaround for bug in Questa 2020.2 and 2021.1: Flatten the struct into a logic vector before
// instantiating `spill_register`.
//typedef logic [$bits(aw_chan_select_t)-1:0] aw_chan_select_flat_t;
typedef logic [aw_chan_width+SelectWidth-1:0] aw_chan_select_flat_t;
aw_chan_select_flat_t slv_aw_chan_select_in_flat,
slv_aw_chan_select_out_flat;
assign slv_aw_chan_select_in_flat = {slv_req_i.aw, slv_aw_select_i};
spill_register #(
.T ( aw_chan_select_flat_t ),
.Bypass ( ~SpillAw ) // because module param indicates if we want a spill reg
) i_aw_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.aw_valid ),
.ready_o ( slv_resp_o.aw_ready ),
.data_i ( slv_aw_chan_select_in_flat ),
.valid_o ( slv_aw_valid ),
.ready_i ( slv_aw_ready ),
.data_o ( slv_aw_chan_select_out_flat )
);
assign slv_aw_chan_select = slv_aw_chan_select_out_flat;
// Control of the AW handshake
always_comb begin
// AXI Handshakes
slv_aw_ready = 1'b0;
aw_valid = 1'b0;
// `lock_aw_valid`, used to be protocol conform as it is not allowed to deassert
// a valid if there was no corresponding ready. As this process has to be able to inject
// an AXI ID into the counter of the AR channel on an ATOP, there could be a case where
// this process waits on `aw_ready` but in the mean time on the AR channel the counter gets
// full.
lock_aw_valid_d = lock_aw_valid_q;
load_aw_lock = 1'b0;
// AW ID counter and W FIFO
aw_push = 1'b0;
// ATOP injection into ar counter
atop_inject = 1'b0;
// we had an arbitration decision, the valid is locked, wait for the transaction
if (lock_aw_valid_q) begin
aw_valid = 1'b1;
// transaction
if (aw_ready) begin
slv_aw_ready = 1'b1;
lock_aw_valid_d = 1'b0;
load_aw_lock = 1'b1;
atop_inject = slv_aw_chan_select.aw_chan.atop[5]; // inject the ATOP if necessary
end
end else begin
// Process can start handling a transaction if its `i_aw_id_counter` and `w_fifo` have
// space in them. Further check if we could inject something on the AR channel.
if (!aw_id_cnt_full && !w_fifo_full && !ar_id_cnt_full) begin
// there is a valid AW vector make the id lookup and go further, if it passes
if (slv_aw_valid && (!aw_select_occupied ||
(slv_aw_chan_select.aw_select == lookup_aw_select))) begin
// connect the handshake
aw_valid = 1'b1;
// push arbitration to the W FIFO regardless, do not wait for the AW transaction
aw_push = 1'b1;
// on AW transaction
if (aw_ready) begin
slv_aw_ready = 1'b1;
atop_inject = slv_aw_chan_select.aw_chan.atop[5];
// no AW transaction this cycle, lock the decision
end else begin
lock_aw_valid_d = 1'b1;
load_aw_lock = 1'b1;
end
end
end
end
end
// lock the valid signal, as the selection gets pushed into the W FIFO on first assertion,
// prevent further pushing
`FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
if (UniqueIds) begin : gen_unique_ids_aw
// If the `UniqueIds` parameter is set, each write transaction has an ID that is unique among
// all in-flight write transactions, or all write transactions with a given ID target the same
// master port as all write transactions with the same ID, or both. This means that the
// signals that are driven by the ID counters if this parameter is not set can instead be
// derived from existing signals. The ID counters can therefore be omitted.
assign lookup_aw_select = slv_aw_chan_select.aw_select;
assign aw_select_occupied = 1'b0;
assign aw_id_cnt_full = 1'b0;
end else begin : gen_aw_id_counter
axi_demux_id_counters #(
.AxiIdBits ( AxiLookBits ),
.CounterWidth ( IdCounterWidth ),
.mst_port_select_t ( select_t )
) i_aw_id_counter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.lookup_axi_id_i ( slv_aw_chan_select.aw_chan.id[0+:AxiLookBits] ),
.lookup_mst_select_o ( lookup_aw_select ),
.lookup_mst_select_occupied_o ( aw_select_occupied ),
.full_o ( aw_id_cnt_full ),
.inject_axi_id_i ( '0 ),
.inject_i ( 1'b0 ),
.push_axi_id_i ( slv_aw_chan_select.aw_chan.id[0+:AxiLookBits] ),
.push_mst_select_i ( slv_aw_chan_select.aw_select ),
.push_i ( aw_push ),
.pop_axi_id_i ( slv_b_chan.id[0+:AxiLookBits] ),
.pop_i ( slv_b_valid & slv_b_ready )
);
// pop from ID counter on outward transaction
end
// FIFO to save W selection
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_w_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( w_fifo_full ),
.empty_o ( w_fifo_empty ),
.usage_o ( ),
.data_i ( slv_aw_chan_select.aw_select ),
.push_i ( aw_push ), // controlled from proc_aw_chan
.data_o ( w_select ), // where the w beat should go
.pop_i ( w_fifo_pop ) // controlled from proc_w_chan
);
//--------------------------------------
// W Channel
//--------------------------------------
spill_register #(
.T ( w_chan_t ),
.Bypass ( ~SpillW )
) i_w_spill_reg(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.w_valid ),
.ready_o ( slv_resp_o.w_ready ),
.data_i ( slv_req_i.w ),
.valid_o ( slv_w_valid ),
.ready_i ( slv_w_ready ),
.data_o ( slv_w_chan )
);
//--------------------------------------
// B Channel
//--------------------------------------
// optional spill register
spill_register #(
.T ( b_chan_t ),
.Bypass ( ~SpillB )
) i_b_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_b_valid ),
.ready_o ( slv_b_ready ),
.data_i ( slv_b_chan ),
.valid_o ( slv_resp_o.b_valid ),
.ready_i ( slv_req_i.b_ready ),
.data_o ( slv_resp_o.b )
);
// Arbitration of the different B responses
rr_arb_tree #(
.NumIn ( NoMstPorts ),
.DataType ( b_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_b_mux (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( mst_b_valids ),
.gnt_o ( mst_b_readies ),
.data_i ( mst_b_chans ),
.gnt_i ( slv_b_ready ),
.req_o ( slv_b_valid ),
.data_o ( slv_b_chan ),
.idx_o ( )
);
//--------------------------------------
// AR Channel
//--------------------------------------
// Workaround for bug in Questa 2020.2 and 2021.1: Flatten the struct into a logic vector before
// instantiating `spill_register`.
//typedef logic [$bits(ar_chan_select_t)-1:0] ar_chan_select_flat_t;
typedef logic [ar_chan_width+SelectWidth-1:0] ar_chan_select_flat_t;
ar_chan_select_flat_t slv_ar_chan_select_in_flat,
slv_ar_chan_select_out_flat;
assign slv_ar_chan_select_in_flat = {slv_req_i.ar, slv_ar_select_i};
spill_register #(
.T ( ar_chan_select_flat_t ),
.Bypass ( ~SpillAr )
) i_ar_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.ar_valid ),
.ready_o ( slv_resp_o.ar_ready ),
.data_i ( slv_ar_chan_select_in_flat ),
.valid_o ( slv_ar_valid ),
.ready_i ( slv_ar_ready ),
.data_o ( slv_ar_chan_select_out_flat )
);
assign slv_ar_chan_select = slv_ar_chan_select_out_flat;
// control of the AR handshake
always_comb begin
// AXI Handshakes
slv_ar_ready = 1'b0;
ar_valid = 1'b0;
// `lock_ar_valid`: Used to be protocol conform as it is not allowed to deassert `ar_valid`
// if there was no corresponding `ar_ready`. There is the possibility that an injection
// of a R response from an `atop` from the AW channel can change the occupied flag of the
// `i_ar_id_counter`, even if it was previously empty. This FF prevents the deassertion.
lock_ar_valid_d = lock_ar_valid_q;
load_ar_lock = 1'b0;
// AR id counter
ar_push = 1'b0;
// The process had an arbitration decision in a previous cycle, the valid is locked,
// wait for the AR transaction.
if (lock_ar_valid_q) begin
ar_valid = 1'b1;
// transaction
if (ar_ready) begin
slv_ar_ready = 1'b1;
ar_push = 1'b1;
lock_ar_valid_d = 1'b0;
load_ar_lock = 1'b1;
end
end else begin
// The process can start handling AR transaction if `i_ar_id_counter` has space.
if (!ar_id_cnt_full) begin
// There is a valid AR, so look the ID up.
if (slv_ar_valid && (!ar_select_occupied ||
(slv_ar_chan_select.ar_select == lookup_ar_select))) begin
// connect the AR handshake
ar_valid = 1'b1;
// on transaction
if (ar_ready) begin
slv_ar_ready = 1'b1;
ar_push = 1'b1;
// no transaction this cycle, lock the valid decision!
end else begin
lock_ar_valid_d = 1'b1;
load_ar_lock = 1'b1;
end
end
end
end
end
// this ff is needed so that ar does not get de-asserted if an atop gets injected
`FFLARN(lock_ar_valid_q, lock_ar_valid_d, load_ar_lock, '0, clk_i, rst_ni)
if (UniqueIds) begin : gen_unique_ids_ar
// If the `UniqueIds` parameter is set, each read transaction has an ID that is unique among
// all in-flight read transactions, or all read transactions with a given ID target the same
// master port as all read transactions with the same ID, or both. This means that the
// signals that are driven by the ID counters if this parameter is not set can instead be
// derived from existing signals. The ID counters can therefore be omitted.
assign lookup_ar_select = slv_ar_chan_select.ar_select;
assign ar_select_occupied = 1'b0;
assign ar_id_cnt_full = 1'b0;
end else begin : gen_ar_id_counter
axi_demux_id_counters #(
.AxiIdBits ( AxiLookBits ),
.CounterWidth ( IdCounterWidth ),
.mst_port_select_t ( select_t )
) i_ar_id_counter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.lookup_axi_id_i ( slv_ar_chan_select.ar_chan.id[0+:AxiLookBits] ),
.lookup_mst_select_o ( lookup_ar_select ),
.lookup_mst_select_occupied_o ( ar_select_occupied ),
.full_o ( ar_id_cnt_full ),
.inject_axi_id_i ( slv_aw_chan_select.aw_chan.id[0+:AxiLookBits] ),
.inject_i ( atop_inject ),
.push_axi_id_i ( slv_ar_chan_select.ar_chan.id[0+:AxiLookBits] ),
.push_mst_select_i ( slv_ar_chan_select.ar_select ),
.push_i ( ar_push ),
.pop_axi_id_i ( slv_r_chan.id[0+:AxiLookBits] ),
.pop_i ( slv_r_valid & slv_r_ready & slv_r_chan.last )
);
end
//--------------------------------------
// R Channel
//--------------------------------------
// optional spill register
spill_register #(
.T ( r_chan_t ),
.Bypass ( ~SpillR )
) i_r_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_r_valid ),
.ready_o ( slv_r_ready ),
.data_i ( slv_r_chan ),
.valid_o ( slv_resp_o.r_valid ),
.ready_i ( slv_req_i.r_ready ),
.data_o ( slv_resp_o.r )
);
// Arbitration of the different r responses
rr_arb_tree #(
.NumIn ( NoMstPorts ),
.DataType ( r_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_r_mux (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( mst_r_valids ),
.gnt_o ( mst_r_readies ),
.data_i ( mst_r_chans ),
.gnt_i ( slv_r_ready ),
.req_o ( slv_r_valid ),
.data_o ( slv_r_chan ),
.idx_o ( )
);
assign ar_ready = ar_valid & mst_resps_i[slv_ar_chan_select.ar_select].ar_ready;
assign aw_ready = aw_valid & mst_resps_i[slv_aw_chan_select.aw_select].aw_ready;
// process that defines the individual demuxes and assignments for the arbitration
// as mst_reqs_o has to be drivem from the same always comb block!
always_comb begin
// default assignments
mst_reqs_o = '0;
slv_w_ready = 1'b0;
w_fifo_pop = 1'b0;
for (int unsigned i = 0; i < NoMstPorts; i++) begin
// AW channel
mst_reqs_o[i].aw = slv_aw_chan_select.aw_chan;
mst_reqs_o[i].aw_valid = 1'b0;
if (aw_valid && (slv_aw_chan_select.aw_select == i)) begin
mst_reqs_o[i].aw_valid = 1'b1;
end
// W channel
mst_reqs_o[i].w = slv_w_chan;
mst_reqs_o[i].w_valid = 1'b0;
if (!w_fifo_empty && (w_select == i)) begin
mst_reqs_o[i].w_valid = slv_w_valid;
slv_w_ready = mst_resps_i[i].w_ready;
w_fifo_pop = slv_w_valid & mst_resps_i[i].w_ready & slv_w_chan.last;
end
// B channel
mst_reqs_o[i].b_ready = mst_b_readies[i];
// AR channel
mst_reqs_o[i].ar = slv_ar_chan_select.ar_chan;
mst_reqs_o[i].ar_valid = 1'b0;
if (ar_valid && (slv_ar_chan_select.ar_select == i)) begin
mst_reqs_o[i].ar_valid = 1'b1;
end
// R channel
mst_reqs_o[i].r_ready = mst_r_readies[i];
end
end
// unpack the response B and R channels for the arbitration
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_b_channels
assign mst_b_chans[i] = mst_resps_i[i].b;
assign mst_b_valids[i] = mst_resps_i[i].b_valid;
assign mst_r_chans[i] = mst_resps_i[i].r;
assign mst_r_valids[i] = mst_resps_i[i].r_valid;
end
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
`ifndef XSIM
initial begin: validate_params
no_mst_ports: assume (NoMstPorts > 0) else
$fatal(1, "The Number of slaves (NoMstPorts) has to be at least 1");
AXI_ID_BITS: assume (AxiIdWidth >= AxiLookBits) else
$fatal(1, "AxiIdBits has to be equal or smaller than AxiIdWidth.");
end
default disable iff (!rst_ni);
aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |->
(slv_aw_select_i < NoMstPorts))) else
$fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\
NoMstPorts: %d", slv_aw_select_i, NoMstPorts);
ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |->
(slv_ar_select_i < NoMstPorts))) else
$fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\
NoMstPorts: %d", slv_ar_select_i, NoMstPorts);
aw_valid_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) |=> aw_valid) else
$fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle.");
ar_valid_stable: assert property( @(posedge clk_i)
(ar_valid && !ar_ready) |=> ar_valid) else
$fatal(1, "ar_valid was deasserted, when ar_ready = 0 in last cycle.");
aw_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready)
|=> $stable(slv_aw_chan_select)) else
$fatal(1, "slv_aw_chan_select unstable with valid set.");
ar_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready)
|=> $stable(slv_ar_chan_select)) else
$fatal(1, "slv_aw_chan_select unstable with valid set.");
internal_ar_select: assert property( @(posedge clk_i)
(ar_valid |-> slv_ar_chan_select.ar_select < NoMstPorts))
else $fatal(1, "slv_ar_chan_select.ar_select illegal while ar_valid.");
internal_aw_select: assert property( @(posedge clk_i)
(aw_valid |-> slv_aw_chan_select.aw_select < NoMstPorts))
else $fatal(1, "slv_aw_chan_select.aw_select illegal while aw_valid.");
`endif
`endif
// pragma translate_on
end
endmodule |
module axi_demux_id_counters #(
// the lower bits of the AXI ID that should be considered, results in 2**AXI_ID_BITS counters
parameter int unsigned AxiIdBits = 2,
parameter int unsigned CounterWidth = 4,
parameter type mst_port_select_t = logic
) (
input clk_i, // Clock
input rst_ni, // Asynchronous reset active low
// lookup
input logic [AxiIdBits-1:0] lookup_axi_id_i,
output mst_port_select_t lookup_mst_select_o,
output logic lookup_mst_select_occupied_o,
// push
output logic full_o,
input logic [AxiIdBits-1:0] push_axi_id_i,
input mst_port_select_t push_mst_select_i,
input logic push_i,
// inject ATOPs in AR channel
input logic [AxiIdBits-1:0] inject_axi_id_i,
input logic inject_i,
// pop
input logic [AxiIdBits-1:0] pop_axi_id_i,
input logic pop_i
);
localparam int unsigned NoCounters = 2**AxiIdBits;
typedef logic [CounterWidth-1:0] cnt_t;
// registers, each gets loaded when push_en[i]
mst_port_select_t [NoCounters-1:0] mst_select_q;
// counter signals
logic [NoCounters-1:0] push_en, inject_en, pop_en, occupied, cnt_full;
//-----------------------------------
// Lookup
//-----------------------------------
assign lookup_mst_select_o = mst_select_q[lookup_axi_id_i];
assign lookup_mst_select_occupied_o = occupied[lookup_axi_id_i];
//-----------------------------------
// Push and Pop
//-----------------------------------
assign push_en = (push_i) ? (1 << push_axi_id_i) : '0;
assign inject_en = (inject_i) ? (1 << inject_axi_id_i) : '0;
assign pop_en = (pop_i) ? (1 << pop_axi_id_i) : '0;
assign full_o = |cnt_full;
// counters
for (genvar i = 0; i < NoCounters; i++) begin : gen_counters
logic cnt_en, cnt_down, overflow;
cnt_t cnt_delta, in_flight;
always_comb begin
unique case ({push_en[i], inject_en[i], pop_en[i]})
3'b001 : begin // pop_i = -1
cnt_en = 1'b1;
cnt_down = 1'b1;
cnt_delta = cnt_t'(1);
end
3'b010 : begin // inject_i = +1
cnt_en = 1'b1;
cnt_down = 1'b0;
cnt_delta = cnt_t'(1);
end
// 3'b011, inject_i & pop_i = 0 --> use default
3'b100 : begin // push_i = +1
cnt_en = 1'b1;
cnt_down = 1'b0;
cnt_delta = cnt_t'(1);
end
// 3'b101, push_i & pop_i = 0 --> use default
3'b110 : begin // push_i & inject_i = +2
cnt_en = 1'b1;
cnt_down = 1'b0;
cnt_delta = cnt_t'(2);
end
3'b111 : begin // push_i & inject_i & pop_i = +1
cnt_en = 1'b1;
cnt_down = 1'b0;
cnt_delta = cnt_t'(1);
end
default : begin // do nothing to the counters
cnt_en = 1'b0;
cnt_down = 1'b0;
cnt_delta = cnt_t'(0);
end
endcase
end
delta_counter #(
.WIDTH ( CounterWidth ),
.STICKY_OVERFLOW ( 1'b0 )
) i_in_flight_cnt (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clear_i ( 1'b0 ),
.en_i ( cnt_en ),
.load_i ( 1'b0 ),
.down_i ( cnt_down ),
.delta_i ( cnt_delta ),
.d_i ( '0 ),
.q_o ( in_flight ),
.overflow_o ( overflow )
);
assign occupied[i] = |in_flight;
assign cnt_full[i] = overflow | (&in_flight);
// holds the selection signal for this id
`FFLARN(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni)
// pragma translate_off
//`ifndef VERILATOR
//`ifndef XSIM
// // Validate parameters.
// cnt_underflow: assert property(
// @(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else
// $fatal(1, "axi_demux_id_counters > Counter: %0d underflowed.\
// The reason is probably a faulty AXI response.", i);
//`endif
//`endif
// pragma translate_on
end
endmodule |
module axi_demux_intf #(
parameter int unsigned AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
parameter int unsigned AXI_USER_WIDTH = 32'd0,
parameter int unsigned NO_MST_PORTS = 32'd3,
parameter int unsigned MAX_TRANS = 32'd8,
parameter int unsigned AXI_LOOK_BITS = 32'd3,
parameter bit UNIQUE_IDS = 1'b0,
parameter bit FALL_THROUGH = 1'b0,
parameter bit SPILL_AW = 1'b1,
parameter bit SPILL_W = 1'b0,
parameter bit SPILL_B = 1'b0,
parameter bit SPILL_AR = 1'b1,
parameter bit SPILL_R = 1'b0,
// Dependent parameters, DO NOT OVERRIDE!
parameter int unsigned SELECT_WIDTH = (NO_MST_PORTS > 32'd1) ? $clog2(NO_MST_PORTS) : 32'd1,
parameter type select_t = logic [SELECT_WIDTH-1:0] // MST port select type
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
input select_t slv_aw_select_i, // has to be stable, when aw_valid
input select_t slv_ar_select_i, // has to be stable, when ar_valid
AXI_BUS.Slave slv, // slave port
AXI_BUS.Master mst [NO_MST_PORTS-1:0] // master ports
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t slv_req;
resp_t slv_resp;
req_t [NO_MST_PORTS-1:0] mst_req;
resp_t [NO_MST_PORTS-1:0] mst_resp;
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
for (genvar i = 0; i < NO_MST_PORTS; i++) begin : gen_assign_mst_ports
`AXI_ASSIGN_FROM_REQ(mst[i], mst_req[i])
`AXI_ASSIGN_TO_RESP(mst_resp[i], mst[i])
end
axi_demux #(
.AxiIdWidth ( AXI_ID_WIDTH ), // ID Width
.aw_chan_t ( aw_chan_t ), // AW Channel Type
.w_chan_t ( w_chan_t ), // W Channel Type
.b_chan_t ( b_chan_t ), // B Channel Type
.ar_chan_t ( ar_chan_t ), // AR Channel Type
.r_chan_t ( r_chan_t ), // R Channel Type
.req_t ( req_t ),
.resp_t ( resp_t ),
.NoMstPorts ( NO_MST_PORTS ),
.MaxTrans ( MAX_TRANS ),
.AxiLookBits ( AXI_LOOK_BITS ),
.UniqueIds ( UNIQUE_IDS ),
.FallThrough ( FALL_THROUGH ),
.SpillAw ( SPILL_AW ),
.SpillW ( SPILL_W ),
.SpillB ( SPILL_B ),
.SpillAr ( SPILL_AR ),
.SpillR ( SPILL_R ),
.aw_chan_width ( 35+AXI_ID_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH),
.ar_chan_width ( 35+AXI_ID_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH)
) i_axi_demux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Testmode enable
// slave port
.slv_req_i ( slv_req ),
.slv_aw_select_i ( slv_aw_select_i ),
.slv_ar_select_i ( slv_ar_select_i ),
.slv_resp_o ( slv_resp ),
// master port
.mst_reqs_o ( mst_req ),
.mst_resps_i ( mst_resp )
);
endmodule |
module axi_lite_demux #(
parameter type aw_chan_t = logic, // AXI4-Lite AW channel
parameter type w_chan_t = logic, // AXI4-Lite W channel
parameter type b_chan_t = logic, // AXI4-Lite B channel
parameter type ar_chan_t = logic, // AXI4-Lite AR channel
parameter type r_chan_t = logic, // AXI4-Lite R channel
parameter type req_t = logic, // AXI4-Lite request struct
parameter type resp_t = logic, // AXI4-Lite response struct
parameter int unsigned NoMstPorts = 32'd0, // Number of instantiated ports
parameter int unsigned MaxTrans = 32'd0, // Maximum number of open transactions per channel
parameter bit FallThrough = 1'b0, // FIFOs are in fall through mode
parameter bit SpillAw = 1'b1, // insert one cycle latency on slave AW
parameter bit SpillW = 1'b0, // insert one cycle latency on slave W
parameter bit SpillB = 1'b0, // insert one cycle latency on slave B
parameter bit SpillAr = 1'b1, // insert one cycle latency on slave AR
parameter bit SpillR = 1'b0, // insert one cycle latency on slave R
// Dependent parameters, DO NOT OVERRIDE!
parameter type select_t = logic [$clog2(NoMstPorts)-1:0]
) (
input logic clk_i,
input logic rst_ni,
input logic test_i,
// slave port (AXI4-Lite input), connect master module here
input req_t slv_req_i,
input select_t slv_aw_select_i,
input select_t slv_ar_select_i,
output resp_t slv_resp_o,
// master ports (AXI4-Lite outputs), connect slave modules here
output req_t [NoMstPorts-1:0] mst_reqs_o,
input resp_t [NoMstPorts-1:0] mst_resps_i
);
//--------------------------------------
// Typedefs for the spill registers
//--------------------------------------
typedef struct packed {
aw_chan_t aw;
select_t select;
} aw_chan_select_t;
typedef struct packed {
ar_chan_t ar;
select_t select;
} ar_chan_select_t;
if (NoMstPorts == 32'd1) begin : gen_no_demux
// degenerate case, connect slave to master port
// AW channel
assign mst_reqs_o[0] = slv_req_i;
assign slv_resp_o = mst_resps_i[0];
end else begin : gen_demux
// normal non degenerate case
//--------------------------------------
//--------------------------------------
// Signal Declarations
//--------------------------------------
//--------------------------------------
//--------------------------------------
// Write Transaction
//--------------------------------------
aw_chan_select_t slv_aw_chan;
logic slv_aw_valid, slv_aw_ready;
logic [NoMstPorts-1:0] mst_aw_valids, mst_aw_readies;
logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock;
logic w_fifo_push, w_fifo_pop;
logic w_fifo_full, w_fifo_empty;
w_chan_t slv_w_chan;
select_t w_select;
logic slv_w_valid, slv_w_ready;
logic /*w_pop*/ b_fifo_pop;
logic b_fifo_full, b_fifo_empty;
b_chan_t slv_b_chan;
select_t b_select;
logic slv_b_valid, slv_b_ready;
//--------------------------------------
// Read Transaction
//--------------------------------------
ar_chan_select_t slv_ar_chan;
logic slv_ar_valid, slv_ar_ready;
logic r_fifo_push, r_fifo_pop;
logic r_fifo_full, r_fifo_empty;
r_chan_t slv_r_chan;
select_t r_select;
logic slv_r_valid, slv_r_ready;
//--------------------------------------
//--------------------------------------
// Channel control
//--------------------------------------
//--------------------------------------
//--------------------------------------
// AW Channel
//--------------------------------------
aw_chan_select_t slv_aw_inp;
assign slv_aw_inp.aw = slv_req_i.aw;
assign slv_aw_inp.select = slv_aw_select_i;
spill_register #(
.T ( aw_chan_select_t ),
.Bypass ( ~SpillAw )
) i_aw_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.aw_valid ),
.ready_o ( slv_resp_o.aw_ready ),
.data_i ( slv_aw_inp ),
.valid_o ( slv_aw_valid ),
.ready_i ( slv_aw_ready ),
.data_o ( slv_aw_chan )
);
// replicate AW channel to the request output
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_aw
assign mst_reqs_o[i].aw = slv_aw_chan.aw;
assign mst_reqs_o[i].aw_valid = mst_aw_valids[i];
assign mst_aw_readies[i] = mst_resps_i[i].aw_ready;
end
// AW channel handshake control
always_comb begin
// default assignments
lock_aw_valid_d = lock_aw_valid_q;
load_aw_lock = 1'b0;
// handshake
slv_aw_ready = 1'b0;
mst_aw_valids = '0;
// W FIFO input control
w_fifo_push = 1'b0;
// control
if (lock_aw_valid_q) begin
// AW channel is locked and has valid output, fifo was pushed, as the new request was issued
mst_aw_valids[slv_aw_chan.select] = 1'b1;
if (mst_aw_readies[slv_aw_chan.select]) begin
// transaction, go back to IDLE
slv_aw_ready = 1'b1;
lock_aw_valid_d = 1'b0;
load_aw_lock = 1'b1;
end
end else begin
if (!w_fifo_full && slv_aw_valid) begin
// new transaction, push select in the FIFO and then look if transaction happened
w_fifo_push = 1'b1;
mst_aw_valids[slv_aw_chan.select] = 1'b1; // only set the valid when FIFO is not full
if (mst_aw_readies[slv_aw_chan.select]) begin
// transaction, notify slave port
slv_aw_ready = 1'b1;
end else begin
// no transaction, lock valid
lock_aw_valid_d = 1'b1;
load_aw_lock = 1'b1;
end
end
end
end
// lock the valid signal, as the selection gets pushed into the W FIFO on first assertion,
// prevent further pushing
`FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
fifo_v3 #(
.FALL_THROUGH( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_w_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemtion rule
.testmode_i ( test_i ),
.full_o ( w_fifo_full ),
.empty_o ( w_fifo_empty ),
.usage_o ( /*not used*/ ),
.data_i ( slv_aw_chan.select ),
.push_i ( w_fifo_push ),
.data_o ( w_select ),
.pop_i ( w_fifo_pop )
);
//--------------------------------------
// W Channel
//--------------------------------------
spill_register #(
.T ( w_chan_t ),
.Bypass ( ~SpillW )
) i_w_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.w_valid ),
.ready_o ( slv_resp_o.w_ready ),
.data_i ( slv_req_i.w ),
.valid_o ( slv_w_valid ),
.ready_i ( slv_w_ready ),
.data_o ( slv_w_chan )
);
// replicate W channel
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_w
assign mst_reqs_o[i].w = slv_w_chan;
assign mst_reqs_o[i].w_valid = ~w_fifo_empty & ~b_fifo_full &
slv_w_valid & (w_select == select_t'(i));
end
assign slv_w_ready = ~w_fifo_empty & ~b_fifo_full & mst_resps_i[w_select].w_ready;
assign w_fifo_pop = slv_w_valid & slv_w_ready;
fifo_v3 #(
.FALL_THROUGH( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_b_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemption
.testmode_i ( test_i ),
.full_o ( b_fifo_full ),
.empty_o ( b_fifo_empty ),
.usage_o ( /*not used*/ ),
.data_i ( w_select ),
.push_i ( w_fifo_pop ), // w beat was transferred, push selection to b channel
.data_o ( b_select ),
.pop_i ( b_fifo_pop )
);
//--------------------------------------
// B Channel
//--------------------------------------
spill_register #(
.T ( b_chan_t ),
.Bypass ( ~SpillB )
) i_b_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_b_valid ),
.ready_o ( slv_b_ready ),
.data_i ( slv_b_chan ),
.valid_o ( slv_resp_o.b_valid ),
.ready_i ( slv_req_i.b_ready ),
.data_o ( slv_resp_o.b )
);
// connect the response if the FIFO has valid data in it
assign slv_b_chan = (!b_fifo_empty) ? mst_resps_i[b_select].b : '0;
assign slv_b_valid = ~b_fifo_empty & mst_resps_i[b_select].b_valid;
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_b
assign mst_reqs_o[i].b_ready = ~b_fifo_empty & slv_b_ready & (b_select == select_t'(i));
end
assign b_fifo_pop = slv_b_valid & slv_b_ready;
//--------------------------------------
// AR Channel
//--------------------------------------
ar_chan_select_t slv_ar_inp;
assign slv_ar_inp.ar = slv_req_i.ar;
assign slv_ar_inp.select = slv_ar_select_i;
spill_register #(
.T ( ar_chan_select_t ),
.Bypass ( ~SpillAr )
) i_ar_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_req_i.ar_valid ),
.ready_o ( slv_resp_o.ar_ready ),
.data_i ( slv_ar_inp ),
.valid_o ( slv_ar_valid ),
.ready_i ( slv_ar_ready ),
.data_o ( slv_ar_chan )
);
// replicate AR channel
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_ar
assign mst_reqs_o[i].ar = slv_ar_chan.ar;
assign mst_reqs_o[i].ar_valid = ~r_fifo_full & slv_ar_valid &
(slv_ar_chan.select == select_t'(i));
end
assign slv_ar_ready = ~r_fifo_full & mst_resps_i[slv_ar_chan.select].ar_ready;
assign r_fifo_push = slv_ar_valid & slv_ar_ready;
fifo_v3 #(
.FALL_THROUGH( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_r_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemption rule
.testmode_i ( test_i ),
.full_o ( r_fifo_full ),
.empty_o ( r_fifo_empty ),
.usage_o ( /*not used*/ ),
.data_i ( slv_ar_chan.select ),
.push_i ( r_fifo_push ),
.data_o ( r_select ),
.pop_i ( r_fifo_pop )
);
//--------------------------------------
// R Channel
//--------------------------------------
spill_register #(
.T ( r_chan_t ),
.Bypass ( ~SpillR )
) i_r_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( slv_r_valid ),
.ready_o ( slv_r_ready ),
.data_i ( slv_r_chan ),
.valid_o ( slv_resp_o.r_valid ),
.ready_i ( slv_req_i.r_ready ),
.data_o ( slv_resp_o.r )
);
// connect the response if the FIFO has valid data in it
assign slv_r_chan = (!r_fifo_empty) ? mst_resps_i[r_select].r : '0;
assign slv_r_valid = ~r_fifo_empty & mst_resps_i[r_select].r_valid;
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_mst_r
assign mst_reqs_o[i].r_ready = ~r_fifo_empty & slv_r_ready & (r_select == select_t'(i));
end
assign r_fifo_pop = slv_r_valid & slv_r_ready;
// pragma translate_off
`ifndef VERILATOR
default disable iff (!rst_ni);
aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |->
(slv_aw_select_i < NoMstPorts))) else
$fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\
NoMstPorts: %d", slv_aw_select_i, NoMstPorts);
ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |->
(slv_ar_select_i < NoMstPorts))) else
$fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\
NoMstPorts: %d", slv_ar_select_i, NoMstPorts);
aw_valid_stable: assert property( @(posedge clk_i) (slv_aw_valid && !slv_aw_ready)
|=> slv_aw_valid) else
$fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle.");
ar_valid_stable: assert property( @(posedge clk_i) (slv_ar_valid && !slv_ar_ready)
|=> slv_ar_valid) else
$fatal(1, "ar_valid was deasserted, when ar_ready = 0 in last cycle.");
aw_stable: assert property( @(posedge clk_i) (slv_aw_valid && !slv_aw_ready)
|=> $stable(slv_aw_chan)) else
$fatal(1, "slv_aw_chan_select unstable with valid set.");
ar_stable: assert property( @(posedge clk_i) (slv_ar_valid && !slv_ar_ready)
|=> $stable(slv_ar_chan)) else
$fatal(1, "slv_aw_chan_select unstable with valid set.");
`endif
// pragma translate_on
end
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
NoPorts: assert (NoMstPorts > 0) else $fatal("Number of master ports must be at least 1!");
MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_demux_intf #(
parameter int unsigned AxiAddrWidth = 32'd0,
parameter int unsigned AxiDataWidth = 32'd0,
parameter int unsigned NoMstPorts = 32'd0,
parameter int unsigned MaxTrans = 32'd0,
parameter bit FallThrough = 1'b0,
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0,
// Dependent parameters, DO NOT OVERRIDE!
parameter type select_t = logic [$clog2(NoMstPorts)-1:0]
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
input select_t slv_aw_select_i, // has to be stable, when aw_valid
input select_t slv_ar_select_i, // has to be stable, when ar_valid
AXI_LITE.Slave slv, // slave port
AXI_LITE.Master mst [NoMstPorts-1:0] // master ports
);
typedef logic [AxiAddrWidth-1:0] addr_t;
typedef logic [AxiDataWidth-1:0] data_t;
typedef logic [AxiDataWidth/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t slv_req;
resp_t slv_resp;
req_t [NoMstPorts-1:0] mst_reqs;
resp_t [NoMstPorts-1:0] mst_resps;
`AXI_LITE_ASSIGN_TO_REQ(slv_req, slv)
`AXI_LITE_ASSIGN_FROM_RESP(slv, slv_resp)
for (genvar i = 0; i < NoMstPorts; i++) begin : gen_assign_mst_ports
`AXI_LITE_ASSIGN_FROM_REQ(mst[i], mst_reqs[i])
`AXI_LITE_ASSIGN_TO_RESP(mst_resps[i], mst[i])
end
axi_lite_demux #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.req_t ( req_t ),
.resp_t ( resp_t ),
.NoMstPorts ( NoMstPorts ),
.MaxTrans ( MaxTrans ),
.FallThrough ( FallThrough ),
.SpillAw ( SpillAw ),
.SpillW ( SpillW ),
.SpillB ( SpillB ),
.SpillAr ( SpillAr ),
.SpillR ( SpillR )
) i_axi_demux (
.clk_i,
.rst_ni,
.test_i,
// slave Port
.slv_req_i ( slv_req ),
.slv_aw_select_i ( slv_aw_select_i ), // must be stable while slv_aw_valid_i
.slv_ar_select_i ( slv_ar_select_i ), // must be stable while slv_ar_valid_i
.slv_resp_o ( slv_resp ),
// mster ports
.mst_reqs_o ( mst_reqs ),
.mst_resps_i ( mst_resps )
);
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
AddrWidth: assert (AxiAddrWidth > 0) else $fatal("Axi Parmeter has to be > 0!");
DataWidth: assert (AxiDataWidth > 0) else $fatal("Axi Parmeter has to be > 0!");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_mux #(
// AXI4-Lite parameter and channel types
parameter type aw_chan_t = logic, // AW LITE Channel Type
parameter type w_chan_t = logic, // W LITE Channel Type
parameter type b_chan_t = logic, // B LITE Channel Type
parameter type ar_chan_t = logic, // AR LITE Channel Type
parameter type r_chan_t = logic, // R LITE Channel Type
parameter type req_t = logic, // AXI4-Lite request type
parameter type resp_t = logic, // AXI4-Lite response type
parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports
// Maximum number of outstanding transactions per write or read
parameter int unsigned MaxTrans = 32'd0,
// If enabled, this multiplexer is purely combinatorial
parameter bit FallThrough = 1'b0,
// add spill register on write master port, adds a cycle latency on write channels
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
// add spill register on read master port, adds a cycle latency on read channels
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Test Mode enable
// slave ports (AXI4-Lite inputs), connect master modules here
input req_t [NoSlvPorts-1:0] slv_reqs_i,
output resp_t [NoSlvPorts-1:0] slv_resps_o,
// master port (AXI4-Lite output), connect slave module here
output req_t mst_req_o,
input resp_t mst_resp_i
);
// pass through if only one slave port
if (NoSlvPorts == 32'h1) begin : gen_no_mux
assign mst_req_o = slv_reqs_i[0];
assign slv_resps_o[0] = mst_resp_i;
// other non degenerate cases
end else begin : gen_mux
// typedef for the FIFO types
typedef logic [$clog2(NoSlvPorts)-1:0] select_t;
// input to the AW arbitration tree, unpacked from request struct
aw_chan_t [NoSlvPorts-1:0] slv_aw_chans;
logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies;
// AW channel arb tree decision
select_t aw_select;
aw_chan_t mst_aw_chan;
logic mst_aw_valid, mst_aw_ready;
// AW master handshake internal, so that we are able to stall, if w_fifo is full
logic aw_valid, aw_ready;
// FF to lock the AW valid signal, when a new arbitration decision is made the decision
// gets pushed into the W FIFO, when it now stalls prevent subsequent pushing
// This FF removes AW to W dependency
logic lock_aw_valid_d, lock_aw_valid_q;
logic load_aw_lock;
// signals for the FIFO that holds the last switching decision of the AW channel
logic w_fifo_full, w_fifo_empty;
logic w_fifo_push, w_fifo_pop;
// W channel spill reg
select_t w_select;
w_chan_t mst_w_chan;
logic mst_w_valid, mst_w_ready;
// switching decision for the B response back routing
select_t b_select;
// signals for the FIFO that holds the last switching decision of the AW channel
logic b_fifo_full, b_fifo_empty;
logic /*w_fifo_pop*/b_fifo_pop;
// B channel spill reg
b_chan_t mst_b_chan;
logic mst_b_valid, mst_b_ready;
// input to the AR arbitration tree, unpacked from request struct
ar_chan_t [NoSlvPorts-1:0] slv_ar_chans;
logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies;
// AR channel for when spill is enabled
select_t ar_select;
ar_chan_t mst_ar_chan;
logic mst_ar_valid, mst_ar_ready;
// AR master handshake internal, so that we are able to stall, if R_fifo is full
logic ar_valid, ar_ready;
// master ID in the r_id
select_t r_select;
// signals for the FIFO that holds the last switching decision of the AR channel
logic r_fifo_full, r_fifo_empty;
logic r_fifo_push, r_fifo_pop;
// R channel spill reg
r_chan_t mst_r_chan;
logic mst_r_valid, mst_r_ready;
//--------------------------------------
// AW Channel
//--------------------------------------
// unpach AW channel from request/response array
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_aw_arb_input
assign slv_aw_chans[i] = slv_reqs_i[i].aw;
assign slv_aw_valids[i] = slv_reqs_i[i].aw_valid;
assign slv_resps_o[i].aw_ready = slv_aw_readies[i];
end
rr_arb_tree #(
.NumIn ( NoSlvPorts ),
.DataType ( aw_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_aw_arbiter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( slv_aw_valids ),
.gnt_o ( slv_aw_readies ),
.data_i ( slv_aw_chans ),
.gnt_i ( aw_ready ),
.req_o ( aw_valid ),
.data_o ( mst_aw_chan ),
.idx_o ( aw_select )
);
// control of the AW channel
always_comb begin
// default assignments
lock_aw_valid_d = lock_aw_valid_q;
load_aw_lock = 1'b0;
w_fifo_push = 1'b0;
mst_aw_valid = 1'b0;
aw_ready = 1'b0;
// had a downstream stall, be valid and send the AW along
if (lock_aw_valid_q) begin
mst_aw_valid = 1'b1;
// transaction
if (mst_aw_ready) begin
aw_ready = 1'b1;
lock_aw_valid_d = 1'b0;
load_aw_lock = 1'b1;
end
end else begin
if (!w_fifo_full && aw_valid) begin
mst_aw_valid = 1'b1;
w_fifo_push = 1'b1;
if (mst_aw_ready) begin
aw_ready = 1'b1;
end else begin
// go to lock if transaction not in this cycle
lock_aw_valid_d = 1'b1;
load_aw_lock = 1'b1;
end
end
end
end
`FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_w_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( w_fifo_full ),
.empty_o ( w_fifo_empty ),
.usage_o ( ),
.data_i ( aw_select ),
.push_i ( w_fifo_push ),
.data_o ( w_select ),
.pop_i ( w_fifo_pop )
);
spill_register #(
.T ( aw_chan_t ),
.Bypass ( ~SpillAw ) // Param indicated that we want a spill reg
) i_aw_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_aw_valid ),
.ready_o ( mst_aw_ready ),
.data_i ( mst_aw_chan ),
.valid_o ( mst_req_o.aw_valid ),
.ready_i ( mst_resp_i.aw_ready ),
.data_o ( mst_req_o.aw )
);
//--------------------------------------
// W Channel
//--------------------------------------
// multiplexer
assign mst_w_chan = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w : '0;
assign mst_w_valid = (!w_fifo_empty && !b_fifo_full) ? slv_reqs_i[w_select].w_valid : 1'b0;
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_slv_w_ready
assign slv_resps_o[i].w_ready = mst_w_ready & ~w_fifo_empty &
~b_fifo_full & (w_select == select_t'(i));
end
assign w_fifo_pop = mst_w_valid & mst_w_ready;
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_b_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( b_fifo_full ),
.empty_o ( b_fifo_empty ),
.usage_o ( ),
.data_i ( w_select ),
.push_i ( w_fifo_pop ), // push the selection for the B channel on W transaction
.data_o ( b_select ),
.pop_i ( b_fifo_pop )
);
spill_register #(
.T ( w_chan_t ),
.Bypass ( ~SpillW )
) i_w_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_w_valid ),
.ready_o ( mst_w_ready ),
.data_i ( mst_w_chan ),
.valid_o ( mst_req_o.w_valid ),
.ready_i ( mst_resp_i.w_ready ),
.data_o ( mst_req_o.w )
);
//--------------------------------------
// B Channel
//--------------------------------------
// replicate B channels
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_slv_resps_b
assign slv_resps_o[i].b = mst_b_chan;
assign slv_resps_o[i].b_valid = mst_b_valid & ~b_fifo_empty & (b_select == select_t'(i));
end
assign mst_b_ready = ~b_fifo_empty & slv_reqs_i[b_select].b_ready;
assign b_fifo_pop = mst_b_valid & mst_b_ready;
spill_register #(
.T ( b_chan_t ),
.Bypass ( ~SpillB )
) i_b_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_resp_i.b_valid ),
.ready_o ( mst_req_o.b_ready ),
.data_i ( mst_resp_i.b ),
.valid_o ( mst_b_valid ),
.ready_i ( mst_b_ready ),
.data_o ( mst_b_chan )
);
//--------------------------------------
// AR Channel
//--------------------------------------
// unpack AR channel from request/response struct
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_ar_arb_input
assign slv_ar_chans[i] = slv_reqs_i[i].ar;
assign slv_ar_valids[i] = slv_reqs_i[i].ar_valid;
assign slv_resps_o[i].ar_ready = slv_ar_readies[i];
end
rr_arb_tree #(
.NumIn ( NoSlvPorts ),
.DataType ( ar_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_ar_arbiter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( slv_ar_valids ),
.gnt_o ( slv_ar_readies ),
.data_i ( slv_ar_chans ),
.gnt_i ( ar_ready ),
.req_o ( ar_valid ),
.data_o ( mst_ar_chan ),
.idx_o ( ar_select )
);
// connect the handshake if there is space in the FIFO, no need for valid locking
// as the R response is only allowed, when AR is transferred
assign mst_ar_valid = (!r_fifo_full) ? ar_valid : 1'b0;
assign ar_ready = (!r_fifo_full) ? mst_ar_ready : 1'b0;
assign r_fifo_push = mst_ar_valid & mst_ar_ready;
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxTrans ),
.dtype ( select_t )
) i_r_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( r_fifo_full ),
.empty_o ( r_fifo_empty ),
.usage_o ( ),
.data_i ( ar_select ),
.push_i ( r_fifo_push ), // push the selection when w transaction happens
.data_o ( r_select ),
.pop_i ( r_fifo_pop )
);
spill_register #(
.T ( ar_chan_t ),
.Bypass ( ~SpillAr )
) i_ar_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_ar_valid ),
.ready_o ( mst_ar_ready ),
.data_i ( mst_ar_chan ),
.valid_o ( mst_req_o.ar_valid ),
.ready_i ( mst_resp_i.ar_ready ),
.data_o ( mst_req_o.ar )
);
//--------------------------------------
// R Channel
//--------------------------------------
// replicate R channels
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_slv_resps_r
assign slv_resps_o[i].r = mst_r_chan;
assign slv_resps_o[i].r_valid = mst_r_valid & ~r_fifo_empty & (r_select == select_t'(i));
end
assign mst_r_ready = ~r_fifo_empty & slv_reqs_i[r_select].r_ready;
assign r_fifo_pop = mst_r_valid & mst_r_ready;
spill_register #(
.T ( r_chan_t ),
.Bypass ( ~SpillR )
) i_r_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_resp_i.r_valid ),
.ready_o ( mst_req_o.r_ready ),
.data_i ( mst_resp_i.r ),
.valid_o ( mst_r_valid ),
.ready_i ( mst_r_ready ),
.data_o ( mst_r_chan )
);
end
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
NoPorts: assert (NoSlvPorts > 0) else $fatal("Number of slave ports must be at least 1!");
MaxTnx: assert (MaxTrans > 0) else $fatal("Number of transactions must be at least 1!");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_mux_intf #(
parameter int unsigned AxiAddrWidth = 32'd0,
parameter int unsigned AxiDataWidth = 32'd0,
parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports
// Maximum number of outstanding transactions per write
parameter int unsigned MaxTrans = 32'd0,
// if enabled, this multiplexer is purely combinatorial
parameter bit FallThrough = 1'b0,
// add spill register on write master ports, adds a cycle latency on write channels
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
// add spill register on read master ports, adds a cycle latency on read channels
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
AXI_BUS.Slave slv [NoSlvPorts-1:0], // slave ports
AXI_BUS.Master mst // master port
);
typedef logic [AxiAddrWidth-1:0] addr_t;
typedef logic [AxiDataWidth-1:0] data_t;
typedef logic [AxiDataWidth/8-1:0] strb_t;
// channels typedef
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t [NoSlvPorts-1:0] slv_reqs;
resp_t [NoSlvPorts-1:0] slv_resps;
req_t mst_req;
resp_t mst_resp;
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_assign_slv_ports
`AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i])
`AXI_LITE_ASSIGN_FROM_RESP(slv[i], slv_resps[i])
end
`AXI_LITE_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_LITE_ASSIGN_TO_RESP(mst_resp, mst)
axi_lite_mux #(
.aw_chan_t ( aw_chan_t ), // AW Channel Type
.w_chan_t ( w_chan_t ), // W Channel Type
.b_chan_t ( b_chan_t ), // B Channel Type
.ar_chan_t ( ar_chan_t ), // AR Channel Type
.r_chan_t ( r_chan_t ), // R Channel Type
.NoSlvPorts ( NoSlvPorts ), // Number of slave ports
.MaxTrans ( MaxTrans ),
.FallThrough ( FallThrough ),
.SpillAw ( SpillAw ),
.SpillW ( SpillW ),
.SpillB ( SpillB ),
.SpillAr ( SpillAr ),
.SpillR ( SpillR )
) i_axi_mux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Test Mode enable
.slv_reqs_i ( slv_reqs ),
.slv_resps_o ( slv_resps ),
.mst_req_o ( mst_req ),
.mst_resp_i ( mst_resp )
);
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
AddrWidth: assert (AxiAddrWidth > 0) else $fatal("Axi Parameter has to be > 0!");
DataWidth: assert (AxiDataWidth > 0) else $fatal("Axi Parameter has to be > 0!");
end
`endif
// pragma translate_on
endmodule |
module axi_mux #(
// AXI parameter and channel types
parameter int unsigned SlvAxiIDWidth = 32'd0, // AXI ID width, slave ports
parameter type slv_aw_chan_t = logic, // AW Channel Type, slave ports
parameter type mst_aw_chan_t = logic, // AW Channel Type, master port
parameter type w_chan_t = logic, // W Channel Type, all ports
parameter type slv_b_chan_t = logic, // B Channel Type, slave ports
parameter type mst_b_chan_t = logic, // B Channel Type, master port
parameter type slv_ar_chan_t = logic, // AR Channel Type, slave ports
parameter type mst_ar_chan_t = logic, // AR Channel Type, master port
parameter type slv_r_chan_t = logic, // R Channel Type, slave ports
parameter type mst_r_chan_t = logic, // R Channel Type, master port
parameter type slv_req_t = logic, // Slave port request type
parameter type slv_resp_t = logic, // Slave port response type
parameter type mst_req_t = logic, // Master ports request type
parameter type mst_resp_t = logic, // Master ports response type
parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports
// Maximum number of outstanding transactions per write
parameter int unsigned MaxWTrans = 32'd8,
// If enabled, this multiplexer is purely combinatorial
parameter bit FallThrough = 1'b0,
// add spill register on write master ports, adds a cycle latency on write channels
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
// add spill register on read master ports, adds a cycle latency on read channels
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Test Mode enable
// slave ports (AXI inputs), connect master modules here
input slv_req_t [NoSlvPorts-1:0] slv_reqs_i,
output slv_resp_t [NoSlvPorts-1:0] slv_resps_o,
// master port (AXI outputs), connect slave modules here
output mst_req_t mst_req_o,
input mst_resp_t mst_resp_i
);
localparam int unsigned MstIdxBits = $clog2(NoSlvPorts);
localparam int unsigned MstAxiIDWidth = SlvAxiIDWidth + MstIdxBits;
// pass through if only one slave port
if (NoSlvPorts == 32'h1) begin : gen_no_mux
assign mst_req_o = slv_reqs_i[0];
assign slv_resps_o[0] = mst_resp_i;
// other non degenerate cases
end else begin : gen_mux
typedef logic [MstIdxBits-1:0] switch_id_t;
// AXI channels between the ID prepend unit and the rest of the multiplexer
mst_aw_chan_t [NoSlvPorts-1:0] slv_aw_chans;
logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies;
w_chan_t [NoSlvPorts-1:0] slv_w_chans;
logic [NoSlvPorts-1:0] slv_w_valids, slv_w_readies;
mst_b_chan_t [NoSlvPorts-1:0] slv_b_chans;
logic [NoSlvPorts-1:0] slv_b_valids, slv_b_readies;
mst_ar_chan_t [NoSlvPorts-1:0] slv_ar_chans;
logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies;
mst_r_chan_t [NoSlvPorts-1:0] slv_r_chans;
logic [NoSlvPorts-1:0] slv_r_valids, slv_r_readies;
// These signals are all ID prepended
// AW channel
mst_aw_chan_t mst_aw_chan;
logic mst_aw_valid, mst_aw_ready;
// AW master handshake internal, so that we are able to stall, if w_fifo is full
logic aw_valid, aw_ready;
// FF to lock the AW valid signal, when a new arbitration decision is made the decision
// gets pushed into the W FIFO, when it now stalls prevent subsequent pushing
// This FF removes AW to W dependency
logic lock_aw_valid_d, lock_aw_valid_q;
logic load_aw_lock;
// signals for the FIFO that holds the last switching decision of the AW channel
logic w_fifo_full, w_fifo_empty;
logic w_fifo_push, w_fifo_pop;
switch_id_t w_fifo_data;
// W channel spill reg
w_chan_t mst_w_chan;
logic mst_w_valid, mst_w_ready;
// master ID in the b_id
switch_id_t switch_b_id;
// B channel spill reg
mst_b_chan_t mst_b_chan;
logic mst_b_valid;
// AR channel for when spill is enabled
mst_ar_chan_t mst_ar_chan;
logic ar_valid, ar_ready;
// master ID in the r_id
switch_id_t switch_r_id;
// R channel spill reg
mst_r_chan_t mst_r_chan;
logic mst_r_valid;
//--------------------------------------
// ID prepend for all slave ports
//--------------------------------------
for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_id_prepend
axi_id_prepend #(
.NoBus ( 32'd1 ), // one AXI bus per slave port
.AxiIdWidthSlvPort( SlvAxiIDWidth ),
.AxiIdWidthMstPort( MstAxiIDWidth ),
.slv_aw_chan_t ( slv_aw_chan_t ),
.slv_w_chan_t ( w_chan_t ),
.slv_b_chan_t ( slv_b_chan_t ),
.slv_ar_chan_t ( slv_ar_chan_t ),
.slv_r_chan_t ( slv_r_chan_t ),
.mst_aw_chan_t ( mst_aw_chan_t ),
.mst_w_chan_t ( w_chan_t ),
.mst_b_chan_t ( mst_b_chan_t ),
.mst_ar_chan_t ( mst_ar_chan_t ),
.mst_r_chan_t ( mst_r_chan_t )
) i_id_prepend (
.pre_id_i ( switch_id_t'(i) ),
.slv_aw_chans_i ( slv_reqs_i[i].aw ),
.slv_aw_valids_i ( slv_reqs_i[i].aw_valid ),
.slv_aw_readies_o ( slv_resps_o[i].aw_ready ),
.slv_w_chans_i ( slv_reqs_i[i].w ),
.slv_w_valids_i ( slv_reqs_i[i].w_valid ),
.slv_w_readies_o ( slv_resps_o[i].w_ready ),
.slv_b_chans_o ( slv_resps_o[i].b ),
.slv_b_valids_o ( slv_resps_o[i].b_valid ),
.slv_b_readies_i ( slv_reqs_i[i].b_ready ),
.slv_ar_chans_i ( slv_reqs_i[i].ar ),
.slv_ar_valids_i ( slv_reqs_i[i].ar_valid ),
.slv_ar_readies_o ( slv_resps_o[i].ar_ready ),
.slv_r_chans_o ( slv_resps_o[i].r ),
.slv_r_valids_o ( slv_resps_o[i].r_valid ),
.slv_r_readies_i ( slv_reqs_i[i].r_ready ),
.mst_aw_chans_o ( slv_aw_chans[i] ),
.mst_aw_valids_o ( slv_aw_valids[i] ),
.mst_aw_readies_i ( slv_aw_readies[i] ),
.mst_w_chans_o ( slv_w_chans[i] ),
.mst_w_valids_o ( slv_w_valids[i] ),
.mst_w_readies_i ( slv_w_readies[i] ),
.mst_b_chans_i ( slv_b_chans[i] ),
.mst_b_valids_i ( slv_b_valids[i] ),
.mst_b_readies_o ( slv_b_readies[i] ),
.mst_ar_chans_o ( slv_ar_chans[i] ),
.mst_ar_valids_o ( slv_ar_valids[i] ),
.mst_ar_readies_i ( slv_ar_readies[i] ),
.mst_r_chans_i ( slv_r_chans[i] ),
.mst_r_valids_i ( slv_r_valids[i] ),
.mst_r_readies_o ( slv_r_readies[i] )
);
end
//--------------------------------------
// AW Channel
//--------------------------------------
rr_arb_tree #(
.NumIn ( NoSlvPorts ),
.DataType ( mst_aw_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_aw_arbiter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( slv_aw_valids ),
.gnt_o ( slv_aw_readies ),
.data_i ( slv_aw_chans ),
.gnt_i ( aw_ready ),
.req_o ( aw_valid ),
.data_o ( mst_aw_chan ),
.idx_o ( )
);
// control of the AW channel
always_comb begin
// default assignments
lock_aw_valid_d = lock_aw_valid_q;
load_aw_lock = 1'b0;
w_fifo_push = 1'b0;
mst_aw_valid = 1'b0;
aw_ready = 1'b0;
// had a downstream stall, be valid and send the AW along
if (lock_aw_valid_q) begin
mst_aw_valid = 1'b1;
// transaction
if (mst_aw_ready) begin
aw_ready = 1'b1;
lock_aw_valid_d = 1'b0;
load_aw_lock = 1'b1;
end
end else begin
if (!w_fifo_full && aw_valid) begin
mst_aw_valid = 1'b1;
w_fifo_push = 1'b1;
if (mst_aw_ready) begin
aw_ready = 1'b1;
end else begin
// go to lock if transaction not in this cycle
lock_aw_valid_d = 1'b1;
load_aw_lock = 1'b1;
end
end
end
end
`FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
fifo_v3 #(
.FALL_THROUGH ( FallThrough ),
.DEPTH ( MaxWTrans ),
.dtype ( switch_id_t )
) i_w_fifo (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( 1'b0 ),
.testmode_i( test_i ),
.full_o ( w_fifo_full ),
.empty_o ( w_fifo_empty ),
.usage_o ( ),
.data_i ( mst_aw_chan.id[SlvAxiIDWidth+:MstIdxBits] ),
.push_i ( w_fifo_push ),
.data_o ( w_fifo_data ),
.pop_i ( w_fifo_pop )
);
spill_register #(
.T ( mst_aw_chan_t ),
.Bypass ( ~SpillAw ) // Param indicated that we want a spill reg
) i_aw_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_aw_valid ),
.ready_o ( mst_aw_ready ),
.data_i ( mst_aw_chan ),
.valid_o ( mst_req_o.aw_valid ),
.ready_i ( mst_resp_i.aw_ready ),
.data_o ( mst_req_o.aw )
);
//--------------------------------------
// W Channel
//--------------------------------------
// multiplexer
assign mst_w_chan = slv_w_chans[w_fifo_data];
always_comb begin
// default assignments
mst_w_valid = 1'b0;
slv_w_readies = '0;
w_fifo_pop = 1'b0;
// control
if (!w_fifo_empty) begin
// connect the handshake
mst_w_valid = slv_w_valids[w_fifo_data];
slv_w_readies[w_fifo_data] = mst_w_ready;
// pop FIFO on a last transaction
w_fifo_pop = slv_w_valids[w_fifo_data] & mst_w_ready & mst_w_chan.last;
end
end
spill_register #(
.T ( w_chan_t ),
.Bypass ( ~SpillW )
) i_w_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_w_valid ),
.ready_o ( mst_w_ready ),
.data_i ( mst_w_chan ),
.valid_o ( mst_req_o.w_valid ),
.ready_i ( mst_resp_i.w_ready ),
.data_o ( mst_req_o.w )
);
//--------------------------------------
// B Channel
//--------------------------------------
// replicate B channels
assign slv_b_chans = {NoSlvPorts{mst_b_chan}};
// control B channel handshake
assign switch_b_id = mst_b_chan.id[SlvAxiIDWidth+:MstIdxBits];
assign slv_b_valids = (mst_b_valid) ? (1 << switch_b_id) : '0;
spill_register #(
.T ( mst_b_chan_t ),
.Bypass ( ~SpillB )
) i_b_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_resp_i.b_valid ),
.ready_o ( mst_req_o.b_ready ),
.data_i ( mst_resp_i.b ),
.valid_o ( mst_b_valid ),
.ready_i ( slv_b_readies[switch_b_id] ),
.data_o ( mst_b_chan )
);
//--------------------------------------
// AR Channel
//--------------------------------------
rr_arb_tree #(
.NumIn ( NoSlvPorts ),
.DataType ( mst_ar_chan_t ),
.AxiVldRdy( 1'b1 ),
.LockIn ( 1'b1 )
) i_ar_arbiter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i( 1'b0 ),
.rr_i ( '0 ),
.req_i ( slv_ar_valids ),
.gnt_o ( slv_ar_readies ),
.data_i ( slv_ar_chans ),
.gnt_i ( ar_ready ),
.req_o ( ar_valid ),
.data_o ( mst_ar_chan ),
.idx_o ( )
);
spill_register #(
.T ( mst_ar_chan_t ),
.Bypass ( ~SpillAr )
) i_ar_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( ar_valid ),
.ready_o ( ar_ready ),
.data_i ( mst_ar_chan ),
.valid_o ( mst_req_o.ar_valid ),
.ready_i ( mst_resp_i.ar_ready ),
.data_o ( mst_req_o.ar )
);
//--------------------------------------
// R Channel
//--------------------------------------
// replicate R channels
assign slv_r_chans = {NoSlvPorts{mst_r_chan}};
// R channel handshake control
assign switch_r_id = mst_r_chan.id[SlvAxiIDWidth+:MstIdxBits];
assign slv_r_valids = (mst_r_valid) ? (1 << switch_r_id) : '0;
spill_register #(
.T ( mst_r_chan_t ),
.Bypass ( ~SpillR )
) i_r_spill_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( mst_resp_i.r_valid ),
.ready_o ( mst_req_o.r_ready ),
.data_i ( mst_resp_i.r ),
.valid_o ( mst_r_valid ),
.ready_i ( slv_r_readies[switch_r_id] ),
.data_o ( mst_r_chan )
);
end
// pragma translate_off
`ifndef VERILATOR
initial begin
assert (SlvAxiIDWidth > 0) else $fatal(1, "AXI ID width of slave ports must be non-zero!");
assert (NoSlvPorts > 0) else $fatal(1, "Number of slave ports must be non-zero!");
assert (MaxWTrans > 0)
else $fatal(1, "Maximum number of outstanding writes must be non-zero!");
assert (MstAxiIDWidth >= SlvAxiIDWidth + $clog2(NoSlvPorts))
else $fatal(1, "AXI ID width of master ports must be wide enough to identify slave ports!");
// Assert ID widths (one slave is sufficient since they all have the same type).
assert ($unsigned($bits(slv_reqs_i[0].aw.id)) == SlvAxiIDWidth)
else $fatal(1, "ID width of AW channel of slave ports does not match parameter!");
assert ($unsigned($bits(slv_reqs_i[0].ar.id)) == SlvAxiIDWidth)
else $fatal(1, "ID width of AR channel of slave ports does not match parameter!");
assert ($unsigned($bits(slv_resps_o[0].b.id)) == SlvAxiIDWidth)
else $fatal(1, "ID width of B channel of slave ports does not match parameter!");
assert ($unsigned($bits(slv_resps_o[0].r.id)) == SlvAxiIDWidth)
else $fatal(1, "ID width of R channel of slave ports does not match parameter!");
assert ($unsigned($bits(mst_req_o.aw.id)) == MstAxiIDWidth)
else $fatal(1, "ID width of AW channel of master port is wrong!");
assert ($unsigned($bits(mst_req_o.ar.id)) == MstAxiIDWidth)
else $fatal(1, "ID width of AR channel of master port is wrong!");
assert ($unsigned($bits(mst_resp_i.b.id)) == MstAxiIDWidth)
else $fatal(1, "ID width of B channel of master port is wrong!");
assert ($unsigned($bits(mst_resp_i.r.id)) == MstAxiIDWidth)
else $fatal(1, "ID width of R channel of master port is wrong!");
end
`endif
// pragma translate_on
endmodule |
module axi_mux_intf #(
parameter int unsigned SLV_AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params
parameter int unsigned MST_AXI_ID_WIDTH = 32'd0,
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
parameter int unsigned AXI_USER_WIDTH = 32'd0,
parameter int unsigned NO_SLV_PORTS = 32'd0, // Number of slave ports
// Maximum number of outstanding transactions per write
parameter int unsigned MAX_W_TRANS = 32'd8,
// if enabled, this multiplexer is purely combinatorial
parameter bit FALL_THROUGH = 1'b0,
// add spill register on write master ports, adds a cycle latency on write channels
parameter bit SPILL_AW = 1'b1,
parameter bit SPILL_W = 1'b0,
parameter bit SPILL_B = 1'b0,
// add spill register on read master ports, adds a cycle latency on read channels
parameter bit SPILL_AR = 1'b1,
parameter bit SPILL_R = 1'b0
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
AXI_BUS.Slave slv [NO_SLV_PORTS-1:0], // slave ports
AXI_BUS.Master mst // master port
);
typedef logic [SLV_AXI_ID_WIDTH-1:0] slv_id_t;
typedef logic [MST_AXI_ID_WIDTH-1:0] mst_id_t;
typedef logic [AXI_ADDR_WIDTH -1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
// channels typedef
`AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, user_t)
`AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t)
`AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t)
`AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t)
`AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t)
`AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t)
slv_req_t [NO_SLV_PORTS-1:0] slv_reqs;
slv_resp_t [NO_SLV_PORTS-1:0] slv_resps;
mst_req_t mst_req;
mst_resp_t mst_resp;
for (genvar i = 0; i < NO_SLV_PORTS; i++) begin : gen_assign_slv_ports
`AXI_ASSIGN_TO_REQ(slv_reqs[i], slv[i])
`AXI_ASSIGN_FROM_RESP(slv[i], slv_resps[i])
end
`AXI_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_ASSIGN_TO_RESP(mst_resp, mst)
axi_mux #(
.SlvAxiIDWidth ( SLV_AXI_ID_WIDTH ),
.slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports
.mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port
.w_chan_t ( w_chan_t ), // W Channel Type, all ports
.slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports
.mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port
.slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports
.mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port
.slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports
.mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port
.slv_req_t ( slv_req_t ),
.slv_resp_t ( slv_resp_t ),
.mst_req_t ( mst_req_t ),
.mst_resp_t ( mst_resp_t ),
.NoSlvPorts ( NO_SLV_PORTS ), // Number of slave ports
.MaxWTrans ( MAX_W_TRANS ),
.FallThrough ( FALL_THROUGH ),
.SpillAw ( SPILL_AW ),
.SpillW ( SPILL_W ),
.SpillB ( SPILL_B ),
.SpillAr ( SPILL_AR ),
.SpillR ( SPILL_R )
) i_axi_mux (
.clk_i ( clk_i ), // Clock
.rst_ni ( rst_ni ), // Asynchronous reset active low
.test_i ( test_i ), // Test Mode enable
.slv_reqs_i ( slv_reqs ),
.slv_resps_o ( slv_resps ),
.mst_req_o ( mst_req ),
.mst_resp_i ( mst_resp )
);
endmodule |
module axi_lite_mailbox #(
parameter int unsigned MailboxDepth = 32'd0,
parameter bit unsigned IrqEdgeTrig = 1'b0,
parameter bit unsigned IrqActHigh = 1'b1,
parameter int unsigned AxiAddrWidth = 32'd0,
parameter int unsigned AxiDataWidth = 32'd0,
parameter type req_lite_t = logic,
parameter type resp_lite_t = logic,
// DEPENDENT PARAMETERS, DO NOT OVERRIDE!
parameter type addr_t = logic [AxiAddrWidth-1:0]
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
// slave ports [1:0]
input req_lite_t [1:0] slv_reqs_i,
output resp_lite_t [1:0] slv_resps_o,
output logic [1:0] irq_o, // interrupt output for each port
input addr_t [1:0] base_addr_i // base address for each port
);
localparam int unsigned FifoUsageWidth = $clog2(MailboxDepth);
typedef logic [AxiDataWidth-1:0] data_t;
// usage type of the mailbox FIFO, also the type of the threshold comparison
// is one bit wider, MSB is the fifo_full flag of the respective fifo
typedef logic [FifoUsageWidth:0] usage_t;
// signal declaration for the mailbox FIFO's, signal index is the port
logic [1:0] mbox_full, mbox_empty; // index is the instantiated mailbox FIFO
logic [1:0] mbox_push, mbox_pop; // index is port
logic [1:0] w_mbox_flush, r_mbox_flush; // index is port
data_t [1:0] mbox_w_data, mbox_r_data; // index is port
usage_t [1:0] mbox_usage; // index is the instantiated mailbox FIFO
// interrupt request from this slave port, level triggered, active high --> convert
logic [1:0] slv_irq;
logic [1:0] clear_irq;
axi_lite_mailbox_slave #(
.MailboxDepth ( MailboxDepth ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.req_lite_t ( req_lite_t ),
.resp_lite_t ( resp_lite_t ),
.addr_t ( addr_t ),
.data_t ( data_t ),
.usage_t ( usage_t ) // fill pointer from MBOX FIFO
) i_slv_port_0 (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
// slave port
.slv_req_i ( slv_reqs_i[0] ),
.slv_resp_o ( slv_resps_o[0] ),
.base_addr_i ( base_addr_i[0] ), // base address for the slave port
// write FIFO port
.mbox_w_data_o ( mbox_w_data[0] ),
.mbox_w_full_i ( mbox_full[0] ),
.mbox_w_push_o ( mbox_push[0] ),
.mbox_w_flush_o ( w_mbox_flush[0] ),
.mbox_w_usage_i ( mbox_usage[0] ),
// read FIFO port
.mbox_r_data_i ( mbox_r_data[0] ),
.mbox_r_empty_i ( mbox_empty[1] ),
.mbox_r_pop_o ( mbox_pop[0] ),
.mbox_r_flush_o ( r_mbox_flush[0] ),
.mbox_r_usage_i ( mbox_usage[1] ),
// interrupt output, level triggered, active high, conversion in top
.irq_o ( slv_irq[0] ),
.clear_irq_o ( clear_irq[0] )
);
axi_lite_mailbox_slave #(
.MailboxDepth ( MailboxDepth ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.req_lite_t ( req_lite_t ),
.resp_lite_t ( resp_lite_t ),
.addr_t ( addr_t ),
.data_t ( data_t ),
.usage_t ( usage_t ) // fill pointer from MBOX FIFO
) i_slv_port_1 (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
// slave port
.slv_req_i ( slv_reqs_i[1] ),
.slv_resp_o ( slv_resps_o[1] ),
.base_addr_i ( base_addr_i[1] ), // base address for the slave port
// write FIFO port
.mbox_w_data_o ( mbox_w_data[1] ),
.mbox_w_full_i ( mbox_full[1] ),
.mbox_w_push_o ( mbox_push[1] ),
.mbox_w_flush_o ( w_mbox_flush[1] ),
.mbox_w_usage_i ( mbox_usage[1] ),
// read FIFO port
.mbox_r_data_i ( mbox_r_data[1] ),
.mbox_r_empty_i ( mbox_empty[0] ),
.mbox_r_pop_o ( mbox_pop[1] ),
.mbox_r_flush_o ( r_mbox_flush[1] ),
.mbox_r_usage_i ( mbox_usage[0] ),
// interrupt output, level triggered, active high, conversion in top
.irq_o ( slv_irq[1] ),
.clear_irq_o ( clear_irq[1] )
);
// the usage gets concatinated with the full flag to have consistent threshold detection
logic [FifoUsageWidth-1:0] mbox_0_to_1_usage, mbox_1_to_0_usage;
fifo_v3 #(
.FALL_THROUGH ( 1'b0 ),
.DEPTH ( MailboxDepth ),
.dtype ( data_t )
) i_mbox_0_to_1 (
.clk_i,
.rst_ni,
.testmode_i( test_i ),
.flush_i ( w_mbox_flush[0] | r_mbox_flush[1] ),
.full_o ( mbox_full[0] ),
.empty_o ( mbox_empty[0] ),
.usage_o ( mbox_0_to_1_usage ),
.data_i ( mbox_w_data[0] ),
.push_i ( mbox_push[0] ),
.data_o ( mbox_r_data[1] ),
.pop_i ( mbox_pop[1] )
);
// assign the MSB of the FIFO to the correct usage signal
assign mbox_usage[0] = {mbox_full[0], mbox_0_to_1_usage};
fifo_v3 #(
.FALL_THROUGH ( 1'b0 ),
.DEPTH ( MailboxDepth ),
.dtype ( data_t )
) i_mbox_1_to_0 (
.clk_i,
.rst_ni,
.testmode_i( test_i ),
.flush_i ( w_mbox_flush[1] | r_mbox_flush[0] ),
.full_o ( mbox_full[1] ),
.empty_o ( mbox_empty[1] ),
.usage_o ( mbox_1_to_0_usage ),
.data_i ( mbox_w_data[1] ),
.push_i ( mbox_push[1] ),
.data_o ( mbox_r_data[0] ),
.pop_i ( mbox_pop[0] )
);
assign mbox_usage[1] = {mbox_full[1], mbox_1_to_0_usage};
for (genvar i = 0; i < 2; i++) begin : gen_irq_conversion
if (IrqEdgeTrig) begin : gen_irq_edge
logic irq_q, irq_d, update_irq;
always_comb begin
// default assignments
irq_d = irq_q;
update_irq = 1'b0;
// init the irq and pulse only on update
irq_o[i] = ~IrqActHigh;
if (clear_irq[i]) begin
irq_d = 1'b0;
update_irq = 1'b1;
end else if (!irq_q && slv_irq[i]) begin
irq_d = 1'b1;
update_irq = 1'b1;
irq_o[i] = IrqActHigh; // on update of the register pulse the irq signal
end
end
`FFLARN(irq_q, irq_d, update_irq, '0, clk_i, rst_ni)
end else begin : gen_irq_level
assign irq_o[i] = (IrqActHigh) ? slv_irq[i] : ~slv_irq[i];
end
end
// pragma translate_off
`ifndef VERILATOR
initial begin : proc_check_params
mailbox_depth: assert (MailboxDepth > 1) else $fatal(1, "MailboxDepth has to be at least 2");
axi_addr_width: assert (AxiAddrWidth > 0) else $fatal(1, "AxiAddrWidth has to be > 0");
axi_data_width: assert (AxiDataWidth > 0) else $fatal(1, "AxiDataWidth has to be > 0");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_mailbox_slave #(
parameter int unsigned MailboxDepth = 32'd16,
parameter int unsigned AxiAddrWidth = 32'd32,
parameter int unsigned AxiDataWidth = 32'd32,
parameter type req_lite_t = logic,
parameter type resp_lite_t = logic,
parameter type addr_t = logic [AxiAddrWidth-1:0],
parameter type data_t = logic [AxiDataWidth-1:0],
parameter type usage_t = logic // fill pointer from MBOX FIFO
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// slave port
input req_lite_t slv_req_i,
output resp_lite_t slv_resp_o,
input addr_t base_addr_i, // base address for the slave port
// write FIFO port
output data_t mbox_w_data_o,
input logic mbox_w_full_i,
output logic mbox_w_push_o,
output logic mbox_w_flush_o,
input usage_t mbox_w_usage_i,
// read FIFO port
input data_t mbox_r_data_i,
input logic mbox_r_empty_i,
output logic mbox_r_pop_o,
output logic mbox_r_flush_o,
input usage_t mbox_r_usage_i,
// interrupt output, level triggered, active high, conversion in top
output logic irq_o,
output logic clear_irq_o // clear the edge trigger irq register in `axi_lite_mailbox`
);
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t)
localparam int unsigned NoRegs = 32'd10;
typedef enum logic [3:0] {
MBOXW = 4'd0, // Mailbox write register
MBOXR = 4'd1, // Mailbox read register
STATUS = 4'd2, // Mailbox status register
ERROR = 4'd3, // Mailbox error register
WIRQT = 4'd4, // Write interrupt request threshold register
RIRQT = 4'd5, // Read interrupt request threshold register
IRQS = 4'd6, // Interrupt request status register
IRQEN = 4'd7, // Interrupt request enable register
IRQP = 4'd8, // Interrupt request pending register
CTRL = 4'd9 // Mailbox control register
} reg_e;
// address map rule struct, as required from `addr_decode` from `common_cells`
typedef struct packed {
int unsigned idx;
addr_t start_addr;
addr_t end_addr;
} rule_t;
// output type of the address decoders, to be casted onto the enum type `reg_e`
typedef logic [$clog2(NoRegs)-1:0] idx_t;
// LITE response signals, go into the output spill registers to prevent combinational response
logic b_valid, b_ready;
b_chan_lite_t b_chan;
logic r_valid, r_ready;
r_chan_lite_t r_chan;
// address map generation
rule_t [NoRegs-1:0] addr_map;
for (genvar i = 0; i < NoRegs; i++) begin : gen_addr_map
assign addr_map[i] = '{
idx: i,
start_addr: base_addr_i + i * (AxiDataWidth / 8),
end_addr: base_addr_i + (i + 1) * (AxiDataWidth / 8),
default: '0
};
end
// address decode flags
idx_t w_reg_idx, r_reg_idx;
logic dec_w_valid, dec_r_valid;
// mailbox register signal declarations, get extended when read, some of these regs
// are build combinationally, indicated by the absence of the `*_d` signal
logic [3:0] status_q; // mailbox status register (read only)
logic [1:0] error_q, error_d; // mailbox error register
data_t wirqt_q, wirqt_d; // write interrupt request threshold register
data_t rirqt_q, rirqt_d; // read interrupt request threshold register
logic [2:0] irqs_q, irqs_d; // interrupt request status register
logic [2:0] irqen_q, irqen_d; // interrupt request enable register
logic [2:0] irqp_q; // interrupt request pending register (read only)
logic [1:0] ctrl_q; // mailbox control register
logic update_regs; // register enable signal
// register instantiation
`FFLARN(error_q, error_d, update_regs, '0, clk_i, rst_ni)
`FFLARN(wirqt_q, wirqt_d, update_regs, '0, clk_i, rst_ni)
`FFLARN(rirqt_q, rirqt_d, update_regs, '0, clk_i, rst_ni)
`FFLARN(irqs_q, irqs_d, update_regs, '0, clk_i, rst_ni)
`FFLARN(irqen_q, irqen_d, update_regs, '0, clk_i, rst_ni)
// Mailbox FIFO data assignments
for (genvar i = 0; i < (AxiDataWidth/8); i++) begin : gen_w_mbox_data
assign mbox_w_data_o[i*8+:8] = slv_req_i.w.strb[i] ? slv_req_i.w.data[i*8+:8] : '0;
end
// combinational mailbox register assignments, for the read only registers
assign status_q = { mbox_r_usage_i > usage_t'(rirqt_q),
mbox_w_usage_i > usage_t'(wirqt_q),
mbox_w_full_i,
mbox_r_empty_i };
assign irqp_q = irqs_q & irqen_q; // interrupt request pending is bit wise and
assign ctrl_q = {mbox_r_flush_o, mbox_w_flush_o}; // read ctrl_q is flush signals
assign irq_o = |irqp_q; // generate an active-high level irq
always_comb begin
// slave port channel outputs for the AW, W and R channel, other driven from spill register
slv_resp_o.aw_ready = 1'b0;
slv_resp_o.w_ready = 1'b0;
b_chan = '{resp: axi_pkg::RESP_SLVERR};
b_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
r_chan = '{data: '0, resp: axi_pkg::RESP_SLVERR};
r_valid = 1'b0;
// Default assignments for the internal registers
error_d = error_q; // mailbox error register
wirqt_d = wirqt_q; // write interrupt request threshold register
rirqt_d = rirqt_q; // read interrupt request threshold register
irqs_d = irqs_q; // interrupt request status register
irqen_d = irqen_q; // interrupt request enable register
update_regs = 1'b0; // register update enable signal
// MBOX FIFO control signals
mbox_w_push_o = 1'b0;
mbox_w_flush_o = 1'b0;
mbox_r_pop_o = 1'b0;
mbox_r_flush_o = 1'b0;
// clear the edge triggered irq register if it is instantiated
clear_irq_o = 1'b0;
// -------------------------------------------
// Set the read and write interrupt FF (irqs), when the threshold triggers
// -------------------------------------------
// strict threshold interrupt these fields get cleared by acknowledge on write onto the register
// read trigger, see status_q above
if (!irqs_q[1] && status_q[3]) begin
irqs_d[1] = 1'b1;
update_regs = 1'b1;
end
// write trigger, see status_q above
if (!irqs_q[0] && status_q[2]) begin
irqs_d[0] = 1'b1;
update_regs = 1'b1;
end
// -------------------------------------------
// Read registers
// -------------------------------------------
// The logic of the read and write channels have to be in the same `always_comb` block.
// The reason is that the error register could be cleared in the same cycle as a read from
// the mailbox FIFO generates a new error. In this case the error is NOT cleared. Instead
// it will generate a new irq when it is edge triggered, or the level will stay at its
// active state.
// Check if there is a pending read request on the slave port.
if (slv_req_i.ar_valid) begin
// set the right read channel output depending on the address decoding
if (dec_r_valid) begin
// when decode not valid, send the default slaveerror
// read the right register when the transfer happens and decode is valid
unique case (reg_e'(r_reg_idx))
MBOXW: r_chan = '{data: data_t'( 32'hFEEDC0DE ), resp: axi_pkg::RESP_OKAY};
MBOXR: begin
if (!mbox_r_empty_i) begin
r_chan = '{data: data_t'( mbox_r_data_i ), resp: axi_pkg::RESP_OKAY};
mbox_r_pop_o = 1'b1;
end else begin
// read mailbox is empty, set the read error Flip flop and respond with error
r_chan = '{data: data_t'( 32'hFEEDDEAD ), resp: axi_pkg::RESP_SLVERR};
error_d[0] = 1'b1;
irqs_d[2] = 1'b1;
update_regs = 1'b1;
end
end
STATUS: r_chan = '{data: data_t'( status_q ), resp: axi_pkg::RESP_OKAY};
ERROR: begin // clear the error register
r_chan = '{data: data_t'( error_q ), resp: axi_pkg::RESP_OKAY};
error_d = '0;
update_regs = 1'b1;
end
WIRQT: r_chan = '{data: data_t'( wirqt_q ), resp: axi_pkg::RESP_OKAY};
RIRQT: r_chan = '{data: data_t'( rirqt_q ), resp: axi_pkg::RESP_OKAY};
IRQS: r_chan = '{data: data_t'( irqs_q ), resp: axi_pkg::RESP_OKAY};
IRQEN: r_chan = '{data: data_t'( irqen_q ), resp: axi_pkg::RESP_OKAY};
IRQP: r_chan = '{data: data_t'( irqp_q ), resp: axi_pkg::RESP_OKAY};
CTRL: r_chan = '{data: data_t'( ctrl_q ), resp: axi_pkg::RESP_OKAY};
default: /*do nothing*/;
endcase
end
r_valid = 1'b1;
if (r_ready) begin
slv_resp_o.ar_ready = 1'b1;
end
end // read register
// -------------------------------------------
// Write registers
// -------------------------------------------
// Wait for control and write data to be valid.
if (slv_req_i.aw_valid && slv_req_i.w_valid) begin
// Can do the handshake here as the b response goes into a spill register with latency one.
// Without the B spill register, the B channel would violate the AXI stable requirement.
b_valid = 1'b1;
if (b_ready) begin
// write to the register if required
if (dec_w_valid) begin
unique case (reg_e'(w_reg_idx))
MBOXW: begin
if (!mbox_w_full_i) begin
mbox_w_push_o = 1'b1;
b_chan = '{resp: axi_pkg::RESP_OKAY};
end else begin
// response with default error and set the error FF
error_d[1] = 1'b1;
irqs_d[2] = 1'b1;
update_regs = 1'b1;
end
end
// MBOXR: read only
// STATUS: read only
// ERROR: read only
WIRQT: begin
for (int unsigned i = 0; i < AxiDataWidth/8; i++) begin
wirqt_d[i*8+:8] = slv_req_i.w.strb[i] ? slv_req_i.w.data[i*8+:8] : 8'b0000_0000;
end
if (wirqt_d >= data_t'(MailboxDepth)) begin
// the `-1` is to have the interrupt fireing when the FIFO is comletely full
wirqt_d = data_t'(MailboxDepth) - data_t'(32'd1); // Threshold to maximal value
end
update_regs = 1'b1;
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
RIRQT: begin
for (int unsigned i = 0; i < AxiDataWidth/8; i++) begin
rirqt_d[i*8+:8] = slv_req_i.w.strb[i] ? slv_req_i.w.data[i*8+:8] : 8'b0000_0000;
end
if (rirqt_d >= data_t'(MailboxDepth)) begin
// Threshold to maximal value, minus two to prevent overflow in usage
rirqt_d = data_t'(MailboxDepth) - data_t'(32'd1);
end
update_regs = 1'b1;
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
IRQS: begin
// Acknowledge and clear the register by asserting the respective one
if (slv_req_i.w.strb[0]) begin
// *_d signal is set in the beginning of this process, prevent accidental
// overwrite of not acknowledged irq
irqs_d[2] = slv_req_i.w.data[2] ? 1'b0 : irqs_d[2]; // Error irq status
irqs_d[1] = slv_req_i.w.data[1] ? 1'b0 : irqs_d[1]; // Read irq status
irqs_d[0] = slv_req_i.w.data[0] ? 1'b0 : irqs_d[0]; // Write irq status
clear_irq_o = 1'b1;
update_regs = 1'b1;
end
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
IRQEN: begin
if (slv_req_i.w.strb[0]) begin
irqen_d[2:0] = slv_req_i.w.data[2:0]; // set the irq enable bits
update_regs = 1'b1;
end
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
// IRQP: read only
CTRL: begin
if (slv_req_i.w.strb[0]) begin
mbox_r_flush_o = slv_req_i.w.data[1]; // Flush read FIFO
mbox_w_flush_o = slv_req_i.w.data[0]; // Flush write FIFO
end
b_chan = '{resp: axi_pkg::RESP_OKAY};
end
default : /* use default b_chan */;
endcase
end
slv_resp_o.aw_ready = 1'b1;
slv_resp_o.w_ready = 1'b1;
end // if (b_ready): Does not violate AXI spec, because the ready comes from an internal
// spill register and does not propagate the ready from the b channel.
end // write register
end
// address decoder and response FIFOs for the LITE channel, the port can take a new transaction if
// these FIFOs are not full, not fall through to prevent combinational paths to the return path
addr_decode #(
.NoIndices( NoRegs ),
.NoRules ( NoRegs ),
.addr_t ( addr_t ),
.rule_t ( rule_t )
) i_waddr_decode (
.addr_i ( slv_req_i.aw.addr ),
.addr_map_i ( addr_map ),
.idx_o ( w_reg_idx ),
.dec_valid_o ( dec_w_valid ),
.dec_error_o ( /*not used*/ ),
.en_default_idx_i ( 1'b0 ),
.default_idx_i ( '0 )
);
spill_register #(
.T ( b_chan_lite_t )
) i_b_chan_outp (
.clk_i,
.rst_ni,
.valid_i ( b_valid ),
.ready_o ( b_ready ),
.data_i ( b_chan ),
.valid_o ( slv_resp_o.b_valid ),
.ready_i ( slv_req_i.b_ready ),
.data_o ( slv_resp_o.b )
);
addr_decode #(
.NoIndices( NoRegs ),
.NoRules ( NoRegs ),
.addr_t ( addr_t ),
.rule_t ( rule_t )
) i_raddr_decode (
.addr_i ( slv_req_i.ar.addr ),
.addr_map_i ( addr_map ),
.idx_o ( r_reg_idx ),
.dec_valid_o ( dec_r_valid ),
.dec_error_o ( /*not used*/ ),
.en_default_idx_i ( 1'b0 ),
.default_idx_i ( '0 )
);
spill_register #(
.T ( r_chan_lite_t )
) i_r_chan_outp (
.clk_i,
.rst_ni,
.valid_i ( r_valid ),
.ready_o ( r_ready ),
.data_i ( r_chan ),
.valid_o ( slv_resp_o.r_valid ),
.ready_i ( slv_req_i.r_ready ),
.data_o ( slv_resp_o.r )
);
// pragma translate_off
`ifndef VERILATOR
initial begin : proc_check_params
assert (AxiAddrWidth == $bits(slv_req_i.aw.addr)) else $fatal(1, "AW AxiAddrWidth mismatch");
assert (AxiDataWidth == $bits(slv_req_i.w.data)) else $fatal(1, " W AxiDataWidth mismatch");
assert (AxiAddrWidth == $bits(slv_req_i.ar.addr)) else $fatal(1, "AR AxiAddrWidth mismatch");
assert (AxiDataWidth == $bits(slv_resp_o.r.data)) else $fatal(1, " R AxiDataWidth mismatch");
end
`endif
// pragma translate_on
endmodule |
module axi_lite_mailbox_intf #(
parameter int unsigned MAILBOX_DEPTH = 32'd0,
parameter bit unsigned IRQ_EDGE_TRIG = 1'b0,
parameter bit unsigned IRQ_ACT_HIGH = 1'b1,
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
// DEPENDENT PARAMETERS, DO NOT OVERRIDE!
parameter type addr_t = logic [AXI_ADDR_WIDTH-1:0]
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
AXI_LITE.Slave slv [1:0], // slave ports [1:0]
output logic [1:0] irq_o, // interrupt output for each port
input addr_t [1:0] base_addr_i // base address for each port
);
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_lite_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t)
req_lite_t [1:0] slv_reqs;
resp_lite_t [1:0] slv_resps;
for (genvar i = 0; i < 2; i++) begin : gen_port_assign
`AXI_LITE_ASSIGN_TO_REQ(slv_reqs[i], slv[i])
`AXI_LITE_ASSIGN_FROM_RESP(slv[i], slv_resps[i])
end
axi_lite_mailbox #(
.MailboxDepth ( MAILBOX_DEPTH ),
.IrqEdgeTrig ( IRQ_EDGE_TRIG ),
.IrqActHigh ( IRQ_ACT_HIGH ),
.AxiAddrWidth ( AXI_ADDR_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.req_lite_t ( req_lite_t ),
.resp_lite_t ( resp_lite_t )
) i_axi_lite_mailbox (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Testmode enable
// slave ports [1:0]
.slv_reqs_i ( slv_reqs ),
.slv_resps_o ( slv_resps ),
.irq_o, // interrupt output for each port
.base_addr_i // base address for each port
);
// pragma translate_off
`ifndef VERILATOR
initial begin
assert (slv[0].AXI_ADDR_WIDTH == AXI_ADDR_WIDTH)
else $fatal(1, "LITE Interface [0] AXI_ADDR_WIDTH missmatch!");
assert (slv[1].AXI_ADDR_WIDTH == AXI_ADDR_WIDTH)
else $fatal(1, "LITE Interface [1] AXI_ADDR_WIDTH missmatch!");
assert (slv[0].AXI_DATA_WIDTH == AXI_DATA_WIDTH)
else $fatal(1, "LITE Interface [0] AXI_DATA_WIDTH missmatch!");
assert (slv[1].AXI_DATA_WIDTH == AXI_DATA_WIDTH)
else $fatal(1, "LITE Interface [1] AXI_DATA_WIDTH missmatch!");
end
`endif
// pragma translate_on
endmodule |
module axi_cdc_src #(
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LogDepth = 1,
parameter type aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type b_chan_t = logic,
parameter type ar_chan_t = logic,
parameter type r_chan_t = logic,
parameter type axi_req_t = logic,
parameter type axi_resp_t = logic
) (
// synchronous slave port - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
input axi_req_t src_req_i,
output axi_resp_t src_resp_o,
// asynchronous master port
output aw_chan_t [2**LogDepth-1:0] async_data_master_aw_data_o,
output logic [LogDepth:0] async_data_master_aw_wptr_o,
input logic [LogDepth:0] async_data_master_aw_rptr_i,
output w_chan_t [2**LogDepth-1:0] async_data_master_w_data_o,
output logic [LogDepth:0] async_data_master_w_wptr_o,
input logic [LogDepth:0] async_data_master_w_rptr_i,
input b_chan_t [2**LogDepth-1:0] async_data_master_b_data_i,
input logic [LogDepth:0] async_data_master_b_wptr_i,
output logic [LogDepth:0] async_data_master_b_rptr_o,
output ar_chan_t [2**LogDepth-1:0] async_data_master_ar_data_o,
output logic [LogDepth:0] async_data_master_ar_wptr_o,
input logic [LogDepth:0] async_data_master_ar_rptr_i,
input r_chan_t [2**LogDepth-1:0] async_data_master_r_data_i,
input logic [LogDepth:0] async_data_master_r_wptr_i,
output logic [LogDepth:0] async_data_master_r_rptr_o
);
cdc_fifo_gray_src #(
.T ( logic [$bits(aw_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_aw (
.src_clk_i,
.src_rst_ni,
.src_data_i ( src_req_i.aw ),
.src_valid_i ( src_req_i.aw_valid ),
.src_ready_o ( src_resp_o.aw_ready ),
.async_data_o ( async_data_master_aw_data_o ),
.async_wptr_o ( async_data_master_aw_wptr_o ),
.async_rptr_i ( async_data_master_aw_rptr_i )
);
cdc_fifo_gray_src #(
.T ( logic [$bits(w_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_w (
.src_clk_i,
.src_rst_ni,
.src_data_i ( src_req_i.w ),
.src_valid_i ( src_req_i.w_valid ),
.src_ready_o ( src_resp_o.w_ready ),
.async_data_o ( async_data_master_w_data_o ),
.async_wptr_o ( async_data_master_w_wptr_o ),
.async_rptr_i ( async_data_master_w_rptr_i )
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(b_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_b (
.dst_clk_i ( src_clk_i ),
.dst_rst_ni ( src_rst_ni ),
.dst_data_o ( src_resp_o.b ),
.dst_valid_o ( src_resp_o.b_valid ),
.dst_ready_i ( src_req_i.b_ready ),
.async_data_i ( async_data_master_b_data_i ),
.async_wptr_i ( async_data_master_b_wptr_i ),
.async_rptr_o ( async_data_master_b_rptr_o )
);
cdc_fifo_gray_src #(
.T ( logic [$bits(ar_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_ar (
.src_clk_i,
.src_rst_ni,
.src_data_i ( src_req_i.ar ),
.src_valid_i ( src_req_i.ar_valid ),
.src_ready_o ( src_resp_o.ar_ready ),
.async_data_o ( async_data_master_ar_data_o ),
.async_wptr_o ( async_data_master_ar_wptr_o ),
.async_rptr_i ( async_data_master_ar_rptr_i )
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(r_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_r (
.dst_clk_i ( src_clk_i ),
.dst_rst_ni ( src_rst_ni ),
.dst_data_o ( src_resp_o.r ),
.dst_valid_o ( src_resp_o.r_valid ),
.dst_ready_i ( src_req_i.r_ready ),
.async_data_i ( async_data_master_r_data_i ),
.async_wptr_i ( async_data_master_r_wptr_i ),
.async_rptr_o ( async_data_master_r_rptr_o )
);
endmodule |
module axi_cdc_src_intf #(
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// synchronous slave port - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
AXI_BUS.Slave src,
// asynchronous master port
AXI_BUS_ASYNC_GRAY.Master dst
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t src_req;
resp_t src_resp;
`AXI_ASSIGN_TO_REQ(src_req, src)
`AXI_ASSIGN_FROM_RESP(src, src_resp)
axi_cdc_src #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc_src (
.src_clk_i,
.src_rst_ni,
.src_req_i ( src_req ),
.src_resp_o ( src_resp ),
.async_data_master_aw_data_o ( dst.aw_data ),
.async_data_master_aw_wptr_o ( dst.aw_wptr ),
.async_data_master_aw_rptr_i ( dst.aw_rptr ),
.async_data_master_w_data_o ( dst.w_data ),
.async_data_master_w_wptr_o ( dst.w_wptr ),
.async_data_master_w_rptr_i ( dst.w_rptr ),
.async_data_master_b_data_i ( dst.b_data ),
.async_data_master_b_wptr_i ( dst.b_wptr ),
.async_data_master_b_rptr_o ( dst.b_rptr ),
.async_data_master_ar_data_o ( dst.ar_data ),
.async_data_master_ar_wptr_o ( dst.ar_wptr ),
.async_data_master_ar_rptr_i ( dst.ar_rptr ),
.async_data_master_r_data_i ( dst.r_data ),
.async_data_master_r_wptr_i ( dst.r_wptr ),
.async_data_master_r_rptr_o ( dst.r_rptr )
);
endmodule |
module axi_lite_cdc_src_intf #(
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// synchronous slave port - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
AXI_BUS.Slave src,
// asynchronous master port
AXI_LITE_ASYNC_GRAY.Master dst
);
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t src_req;
resp_t src_resp;
`AXI_LITE_ASSIGN_TO_REQ(src_req, src)
`AXI_LITE_ASSIGN_FROM_RESP(src, src_resp)
axi_cdc_src #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc_src (
.src_clk_i,
.src_rst_ni,
.src_req_o ( src_req ),
.src_resp_i ( src_resp ),
.async_data_master_aw_data_o ( dst.aw_data ),
.async_data_master_aw_wptr_o ( dst.aw_wptr ),
.async_data_master_aw_rptr_i ( dst.aw_rptr ),
.async_data_master_w_data_o ( dst.w_data ),
.async_data_master_w_wptr_o ( dst.w_wptr ),
.async_data_master_w_rptr_i ( dst.w_rptr ),
.async_data_master_b_data_i ( dst.b_data ),
.async_data_master_b_wptr_i ( dst.b_wptr ),
.async_data_master_b_rptr_o ( dst.b_rptr ),
.async_data_master_ar_data_o ( dst.ar_data ),
.async_data_master_ar_wptr_o ( dst.ar_wptr ),
.async_data_master_ar_rptr_i ( dst.ar_rptr ),
.async_data_master_r_data_i ( dst.r_data ),
.async_data_master_r_wptr_i ( dst.r_wptr ),
.async_data_master_r_rptr_o ( dst.r_rptr )
);
endmodule |
module axi_cdc_dst #(
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LogDepth = 1,
parameter type aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type b_chan_t = logic,
parameter type ar_chan_t = logic,
parameter type r_chan_t = logic,
parameter type axi_req_t = logic,
parameter type axi_resp_t = logic
) (
// asynchronous slave port
input aw_chan_t [2**LogDepth-1:0] async_data_slave_aw_data_i,
input logic [LogDepth:0] async_data_slave_aw_wptr_i,
output logic [LogDepth:0] async_data_slave_aw_rptr_o,
input w_chan_t [2**LogDepth-1:0] async_data_slave_w_data_i,
input logic [LogDepth:0] async_data_slave_w_wptr_i,
output logic [LogDepth:0] async_data_slave_w_rptr_o,
output b_chan_t [2**LogDepth-1:0] async_data_slave_b_data_o,
output logic [LogDepth:0] async_data_slave_b_wptr_o,
input logic [LogDepth:0] async_data_slave_b_rptr_i,
input ar_chan_t [2**LogDepth-1:0] async_data_slave_ar_data_i,
input logic [LogDepth:0] async_data_slave_ar_wptr_i,
output logic [LogDepth:0] async_data_slave_ar_rptr_o,
output r_chan_t [2**LogDepth-1:0] async_data_slave_r_data_o,
output logic [LogDepth:0] async_data_slave_r_wptr_o,
input logic [LogDepth:0] async_data_slave_r_rptr_i,
// synchronous master port - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
output axi_req_t dst_req_o,
input axi_resp_t dst_resp_i
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(aw_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_aw (
.async_data_i ( async_data_slave_aw_data_i ),
.async_wptr_i ( async_data_slave_aw_wptr_i ),
.async_rptr_o ( async_data_slave_aw_rptr_o ),
.dst_clk_i,
.dst_rst_ni,
.dst_data_o ( dst_req_o.aw ),
.dst_valid_o ( dst_req_o.aw_valid ),
.dst_ready_i ( dst_resp_i.aw_ready )
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(w_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_w (
.async_data_i ( async_data_slave_w_data_i ),
.async_wptr_i ( async_data_slave_w_wptr_i ),
.async_rptr_o ( async_data_slave_w_rptr_o ),
.dst_clk_i,
.dst_rst_ni,
.dst_data_o ( dst_req_o.w ),
.dst_valid_o ( dst_req_o.w_valid ),
.dst_ready_i ( dst_resp_i.w_ready )
);
cdc_fifo_gray_src #(
.T ( logic [$bits(b_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_b (
.src_clk_i ( dst_clk_i ),
.src_rst_ni ( dst_rst_ni ),
.src_data_i ( dst_resp_i.b ),
.src_valid_i ( dst_resp_i.b_valid ),
.src_ready_o ( dst_req_o.b_ready ),
.async_data_o ( async_data_slave_b_data_o ),
.async_wptr_o ( async_data_slave_b_wptr_o ),
.async_rptr_i ( async_data_slave_b_rptr_i )
);
cdc_fifo_gray_dst #(
.T ( logic [$bits(ar_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_dst_ar (
.dst_clk_i,
.dst_rst_ni,
.dst_data_o ( dst_req_o.ar ),
.dst_valid_o ( dst_req_o.ar_valid ),
.dst_ready_i ( dst_resp_i.ar_ready ),
.async_data_i ( async_data_slave_ar_data_i ),
.async_wptr_i ( async_data_slave_ar_wptr_i ),
.async_rptr_o ( async_data_slave_ar_rptr_o )
);
cdc_fifo_gray_src #(
.T ( logic [$bits(r_chan_t)-1:0] ),
.LOG_DEPTH ( LogDepth )
) i_cdc_fifo_gray_src_r (
.src_clk_i ( dst_clk_i ),
.src_rst_ni ( dst_rst_ni ),
.src_data_i ( dst_resp_i.r ),
.src_valid_i ( dst_resp_i.r_valid ),
.src_ready_o ( dst_req_o.r_ready ),
.async_data_o ( async_data_slave_r_data_o ),
.async_wptr_o ( async_data_slave_r_wptr_o ),
.async_rptr_i ( async_data_slave_r_rptr_i )
);
endmodule |
module axi_cdc_dst_intf #(
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// asynchronous slave port
AXI_BUS_ASYNC_GRAY.Slave src,
// synchronous master port - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
AXI_BUS.Master dst
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t dst_req;
resp_t dst_resp;
axi_cdc_dst #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc_dst (
.async_data_slave_aw_data_i ( src.aw_data ),
.async_data_slave_aw_wptr_i ( src.aw_wptr ),
.async_data_slave_aw_rptr_o ( src.aw_rptr ),
.async_data_slave_w_data_i ( src.w_data ),
.async_data_slave_w_wptr_i ( src.w_wptr ),
.async_data_slave_w_rptr_o ( src.w_rptr ),
.async_data_slave_b_data_o ( src.b_data ),
.async_data_slave_b_wptr_o ( src.b_wptr ),
.async_data_slave_b_rptr_i ( src.b_rptr ),
.async_data_slave_ar_data_i ( src.ar_data ),
.async_data_slave_ar_wptr_i ( src.ar_wptr ),
.async_data_slave_ar_rptr_o ( src.ar_rptr ),
.async_data_slave_r_data_o ( src.r_data ),
.async_data_slave_r_wptr_o ( src.r_wptr ),
.async_data_slave_r_rptr_i ( src.r_rptr ),
.dst_clk_i,
.dst_rst_ni,
.dst_req_o ( dst_req ),
.dst_resp_i ( dst_resp )
);
`AXI_ASSIGN_FROM_REQ(dst, dst_req)
`AXI_ASSIGN_TO_RESP(dst_resp, dst)
endmodule |
module axi_lite_cdc_dst_intf #(
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// asynchronous slave port
AXI_LITE_ASYNC_GRAY.Slave src,
// synchronous master port - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
AXI_LITE.Master dst
);
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t dst_req;
resp_t dst_resp;
axi_cdc_dst #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc_dst (
.async_data_slave_aw_data_i ( src.aw_data ),
.async_data_slave_aw_wptr_i ( src.aw_wptr ),
.async_data_slave_aw_rptr_o ( src.aw_rptr ),
.async_data_slave_w_data_i ( src.w_data ),
.async_data_slave_w_wptr_i ( src.w_wptr ),
.async_data_slave_w_rptr_o ( src.w_rptr ),
.async_data_slave_b_data_o ( src.b_data ),
.async_data_slave_b_wptr_o ( src.b_wptr ),
.async_data_slave_b_rptr_i ( src.b_rptr ),
.async_data_slave_ar_data_i ( src.ar_data ),
.async_data_slave_ar_wptr_i ( src.ar_wptr ),
.async_data_slave_ar_rptr_o ( src.ar_rptr ),
.async_data_slave_r_data_o ( src.r_data ),
.async_data_slave_r_wptr_o ( src.r_wptr ),
.async_data_slave_r_rptr_i ( src.r_rptr ),
.dst_clk_i,
.dst_rst_ni,
.dst_req_o ( dst_req ),
.dst_resp_i ( dst_resp )
);
`AXI_LITE_ASSIGN_FROM_REQ(dst, dst_req)
`AXI_LITE_ASSIGN_TO_RESP(dst_resp, dst)
endmodule |
module axi_serializer #(
/// Maximum number of in flight read transactions.
parameter int unsigned MaxReadTxns = 32'd0,
/// Maximum number of in flight write transactions.
parameter int unsigned MaxWriteTxns = 32'd0,
/// AXI4+ATOP ID width.
parameter int unsigned AxiIdWidth = 32'd0,
/// AXI4+ATOP request struct definition.
parameter type req_t = logic,
/// AXI4+ATOP response struct definition.
parameter type resp_t = logic
) (
/// Clock
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// Slave port request
input req_t slv_req_i,
/// Slave port response
output resp_t slv_resp_o,
/// Master port request
output req_t mst_req_o,
/// Master port response
input resp_t mst_resp_i
);
typedef logic [AxiIdWidth-1:0] id_t;
typedef enum logic [1:0] {
AtopIdle = 2'b00,
AtopDrain = 2'b01,
AtopExecute = 2'b10
} state_e;
logic rd_fifo_full, rd_fifo_empty, rd_fifo_push, rd_fifo_pop,
wr_fifo_full, wr_fifo_empty, wr_fifo_push, wr_fifo_pop;
id_t b_id,
r_id, ar_id;
state_e state_q, state_d;
always_comb begin
// Default assignments
state_d = state_q;
rd_fifo_push = 1'b0;
wr_fifo_push = 1'b0;
// Default, connect the channels
mst_req_o = slv_req_i;
slv_resp_o = mst_resp_i;
// Serialize transactions -> tie downstream IDs to zero.
mst_req_o.aw.id = '0;
mst_req_o.ar.id = '0;
// Reflect upstream ID in response.
ar_id = slv_req_i.ar.id;
slv_resp_o.b.id = b_id;
slv_resp_o.r.id = r_id;
// Default, cut the AW/AR handshaking
mst_req_o.ar_valid = 1'b0;
slv_resp_o.ar_ready = 1'b0;
mst_req_o.aw_valid = 1'b0;
slv_resp_o.aw_ready = 1'b0;
unique case (state_q)
AtopIdle, AtopExecute: begin
// Wait until the ATOP response(s) have been sent back upstream.
if (state_q == AtopExecute) begin
if ((wr_fifo_empty && rd_fifo_empty) || (wr_fifo_pop && rd_fifo_pop) ||
(wr_fifo_empty && rd_fifo_pop) || (wr_fifo_pop && rd_fifo_empty)) begin
state_d = AtopIdle;
end
end
// This part lets new Transactions through, if no ATOP is underway or the last ATOP
// response has been transmitted.
if ((state_q == AtopIdle) || (state_d == AtopIdle)) begin
// Gate AR handshake with ready output of Read FIFO.
mst_req_o.ar_valid = slv_req_i.ar_valid & ~rd_fifo_full;
slv_resp_o.ar_ready = mst_resp_i.ar_ready & ~rd_fifo_full;
rd_fifo_push = mst_req_o.ar_valid & mst_resp_i.ar_ready;
if (slv_req_i.aw_valid) begin
if (slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin
// Normal operation
// Gate AW handshake with ready output of Write FIFO.
mst_req_o.aw_valid = ~wr_fifo_full;
slv_resp_o.aw_ready = mst_resp_i.aw_ready & ~wr_fifo_full;
wr_fifo_push = mst_req_o.aw_valid & mst_resp_i.aw_ready;
end else begin
// Atomic Operation received, go to drain state, when both channels are ready
// Wait for finished or no AR beat
if (!mst_req_o.ar_valid || (mst_req_o.ar_valid && mst_resp_i.ar_ready)) begin
state_d = AtopDrain;
end
end
end
end
end
AtopDrain: begin
// Send the ATOP AW when the last open transaction terminates
if (wr_fifo_empty && rd_fifo_empty) begin
mst_req_o.aw_valid = 1'b1;
slv_resp_o.aw_ready = mst_resp_i.aw_ready;
wr_fifo_push = mst_resp_i.aw_ready;
if (slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
// Overwrite the read ID with the one from AW
ar_id = slv_req_i.aw.id;
rd_fifo_push = mst_resp_i.aw_ready;
end
if (mst_resp_i.aw_ready) begin
state_d = AtopExecute;
end
end
end
default : /* do nothing */;
endcase
// Gate B handshake with empty flag output of Write FIFO.
slv_resp_o.b_valid = mst_resp_i.b_valid & ~wr_fifo_empty;
mst_req_o.b_ready = slv_req_i.b_ready & ~wr_fifo_empty;
// Gate R handshake with empty flag output of Read FIFO.
slv_resp_o.r_valid = mst_resp_i.r_valid & ~rd_fifo_empty;
mst_req_o.r_ready = slv_req_i.r_ready & ~rd_fifo_empty;
end
fifo_v3 #(
.FALL_THROUGH ( 1'b0 ), // No fall-through as response has to come a cycle later anyway
.DEPTH ( MaxReadTxns ),
.dtype ( id_t )
) i_rd_id_fifo (
.clk_i,
.rst_ni,
.flush_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.data_i ( ar_id ),
.push_i ( rd_fifo_push ),
.full_o ( rd_fifo_full ),
.data_o ( r_id ),
.empty_o ( rd_fifo_empty ),
.pop_i ( rd_fifo_pop ),
.usage_o ( /*not used*/ )
);
// Assign as this condition is needed in FSM
assign rd_fifo_pop = slv_resp_o.r_valid & slv_req_i.r_ready & slv_resp_o.r.last;
fifo_v3 #(
.FALL_THROUGH ( 1'b0 ),
.DEPTH ( MaxWriteTxns ),
.dtype ( id_t )
) i_wr_id_fifo (
.clk_i,
.rst_ni,
.flush_i ( 1'b0 ),
.testmode_i ( 1'b0 ),
.data_i ( slv_req_i.aw.id ),
.push_i ( wr_fifo_push ),
.full_o ( wr_fifo_full ),
.data_o ( b_id ),
.empty_o ( wr_fifo_empty ),
.pop_i ( wr_fifo_pop ),
.usage_o ( /*not used*/ )
);
// Assign as this condition is needed in FSM
assign wr_fifo_pop = slv_resp_o.b_valid & slv_req_i.b_ready;
`FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni)
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
assert (AxiIdWidth >= 1) else $fatal(1, "AXI ID width must be at least 1!");
assert (MaxReadTxns >= 1)
else $fatal(1, "Maximum number of read transactions must be >= 1!");
assert (MaxWriteTxns >= 1)
else $fatal(1, "Maximum number of write transactions must be >= 1!");
end
default disable iff (~rst_ni);
aw_lost : assert property( @(posedge clk_i)
(slv_req_i.aw_valid & slv_resp_o.aw_ready |-> mst_req_o.aw_valid & mst_resp_i.aw_ready))
else $error("AW beat lost.");
w_lost : assert property( @(posedge clk_i)
(slv_req_i.w_valid & slv_resp_o.w_ready |-> mst_req_o.w_valid & mst_resp_i.w_ready))
else $error("W beat lost.");
b_lost : assert property( @(posedge clk_i)
(mst_resp_i.b_valid & mst_req_o.b_ready |-> slv_resp_o.b_valid & slv_req_i.b_ready))
else $error("B beat lost.");
ar_lost : assert property( @(posedge clk_i)
(slv_req_i.ar_valid & slv_resp_o.ar_ready |-> mst_req_o.ar_valid & mst_resp_i.ar_ready))
else $error("AR beat lost.");
r_lost : assert property( @(posedge clk_i)
(mst_resp_i.r_valid & mst_req_o.r_ready |-> slv_resp_o.r_valid & slv_req_i.r_ready))
else $error("R beat lost.");
`endif
// pragma translate_on
endmodule |
module axi_serializer_intf #(
/// AXI4+ATOP ID width.
parameter int unsigned AXI_ID_WIDTH = 32'd0,
/// AXI4+ATOP address width.
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
/// AXI4+ATOP data width.
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
/// AXI4+ATOP user width.
parameter int unsigned AXI_USER_WIDTH = 32'd0,
/// Maximum number of in flight read transactions.
parameter int unsigned MAX_READ_TXNS = 32'd0,
/// Maximum number of in flight write transactions.
parameter int unsigned MAX_WRITE_TXNS = 32'd0
) (
/// Clock
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// AXI4+ATOP Slave modport
AXI_BUS.Slave slv,
/// AXI4+ATOP Master modport
AXI_BUS.Master mst
);
typedef logic [AXI_ID_WIDTH -1:0] id_t;
typedef logic [AXI_ADDR_WIDTH -1:0] addr_t;
typedef logic [AXI_DATA_WIDTH -1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH -1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t slv_req, mst_req;
resp_t slv_resp, mst_resp;
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
`AXI_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_ASSIGN_TO_RESP(mst_resp, mst)
axi_serializer #(
.MaxReadTxns ( MAX_READ_TXNS ),
.MaxWriteTxns ( MAX_WRITE_TXNS ),
.AxiIdWidth ( AXI_ID_WIDTH ),
.req_t ( req_t ),
.resp_t ( resp_t )
) i_axi_serializer (
.clk_i,
.rst_ni,
.slv_req_i ( slv_req ),
.slv_resp_o ( slv_resp ),
.mst_req_o ( mst_req ),
.mst_resp_i ( mst_resp )
);
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
assert (AXI_ADDR_WIDTH >= 1) else $fatal(1, "AXI address width must be at least 1!");
assert (AXI_DATA_WIDTH >= 1) else $fatal(1, "AXI data width must be at least 1!");
assert (AXI_ID_WIDTH >= 1) else $fatal(1, "AXI ID width must be at least 1!");
assert (AXI_USER_WIDTH >= 1) else $fatal(1, "AXI user width must be at least 1!");
assert (MAX_READ_TXNS >= 1)
else $fatal(1, "Maximum number of read transactions must be >= 1!");
assert (MAX_WRITE_TXNS >= 1)
else $fatal(1, "Maximum number of write transactions must be >= 1!");
end
`endif
// pragma translate_on
endmodule |
module axi_cdc #(
parameter type aw_chan_t = logic, // AW Channel Type
parameter type w_chan_t = logic, // W Channel Type
parameter type b_chan_t = logic, // B Channel Type
parameter type ar_chan_t = logic, // AR Channel Type
parameter type r_chan_t = logic, // R Channel Type
parameter type axi_req_t = logic, // encapsulates request channels
parameter type axi_resp_t = logic, // encapsulates request channels
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LogDepth = 1
) (
// slave side - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
input axi_req_t src_req_i,
output axi_resp_t src_resp_o,
// master side - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
output axi_req_t dst_req_o,
input axi_resp_t dst_resp_i
);
aw_chan_t [2**LogDepth-1:0] async_data_aw_data;
w_chan_t [2**LogDepth-1:0] async_data_w_data;
b_chan_t [2**LogDepth-1:0] async_data_b_data;
ar_chan_t [2**LogDepth-1:0] async_data_ar_data;
r_chan_t [2**LogDepth-1:0] async_data_r_data;
logic [LogDepth:0] async_data_aw_wptr, async_data_aw_rptr,
async_data_w_wptr, async_data_w_rptr,
async_data_b_wptr, async_data_b_rptr,
async_data_ar_wptr, async_data_ar_rptr,
async_data_r_wptr, async_data_r_rptr;
axi_cdc_src #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( axi_req_t ),
.axi_resp_t ( axi_resp_t ),
.LogDepth ( LogDepth )
) i_axi_cdc_src (
.src_clk_i,
.src_rst_ni,
.src_req_i,
.src_resp_o,
(* async *) .async_data_master_aw_data_o ( async_data_aw_data ),
(* async *) .async_data_master_aw_wptr_o ( async_data_aw_wptr ),
(* async *) .async_data_master_aw_rptr_i ( async_data_aw_rptr ),
(* async *) .async_data_master_w_data_o ( async_data_w_data ),
(* async *) .async_data_master_w_wptr_o ( async_data_w_wptr ),
(* async *) .async_data_master_w_rptr_i ( async_data_w_rptr ),
(* async *) .async_data_master_b_data_i ( async_data_b_data ),
(* async *) .async_data_master_b_wptr_i ( async_data_b_wptr ),
(* async *) .async_data_master_b_rptr_o ( async_data_b_rptr ),
(* async *) .async_data_master_ar_data_o ( async_data_ar_data ),
(* async *) .async_data_master_ar_wptr_o ( async_data_ar_wptr ),
(* async *) .async_data_master_ar_rptr_i ( async_data_ar_rptr ),
(* async *) .async_data_master_r_data_i ( async_data_r_data ),
(* async *) .async_data_master_r_wptr_i ( async_data_r_wptr ),
(* async *) .async_data_master_r_rptr_o ( async_data_r_rptr )
);
axi_cdc_dst #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( axi_req_t ),
.axi_resp_t ( axi_resp_t ),
.LogDepth ( LogDepth )
) i_axi_cdc_dst (
.dst_clk_i,
.dst_rst_ni,
.dst_req_o,
.dst_resp_i,
(* async *) .async_data_slave_aw_wptr_i ( async_data_aw_wptr ),
(* async *) .async_data_slave_aw_rptr_o ( async_data_aw_rptr ),
(* async *) .async_data_slave_aw_data_i ( async_data_aw_data ),
(* async *) .async_data_slave_w_wptr_i ( async_data_w_wptr ),
(* async *) .async_data_slave_w_rptr_o ( async_data_w_rptr ),
(* async *) .async_data_slave_w_data_i ( async_data_w_data ),
(* async *) .async_data_slave_b_wptr_o ( async_data_b_wptr ),
(* async *) .async_data_slave_b_rptr_i ( async_data_b_rptr ),
(* async *) .async_data_slave_b_data_o ( async_data_b_data ),
(* async *) .async_data_slave_ar_wptr_i ( async_data_ar_wptr ),
(* async *) .async_data_slave_ar_rptr_o ( async_data_ar_rptr ),
(* async *) .async_data_slave_ar_data_i ( async_data_ar_data ),
(* async *) .async_data_slave_r_wptr_o ( async_data_r_wptr ),
(* async *) .async_data_slave_r_rptr_i ( async_data_r_rptr ),
(* async *) .async_data_slave_r_data_o ( async_data_r_data )
);
endmodule |
module axi_cdc_intf #(
parameter int unsigned AXI_ID_WIDTH = 0,
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
parameter int unsigned AXI_USER_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// slave side - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
AXI_BUS.Slave src,
// master side - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
AXI_BUS.Master dst
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t src_req, dst_req;
resp_t src_resp, dst_resp;
`AXI_ASSIGN_TO_REQ(src_req, src)
`AXI_ASSIGN_FROM_RESP(src, src_resp)
`AXI_ASSIGN_FROM_REQ(dst, dst_req)
`AXI_ASSIGN_TO_RESP(dst_resp, dst)
axi_cdc #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc (
.src_clk_i,
.src_rst_ni,
.src_req_i ( src_req ),
.src_resp_o ( src_resp ),
.dst_clk_i,
.dst_rst_ni,
.dst_req_o ( dst_req ),
.dst_resp_i ( dst_resp )
);
endmodule |
module axi_lite_cdc_intf #(
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
/// Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
parameter int unsigned LOG_DEPTH = 1
) (
// slave side - clocked by `src_clk_i`
input logic src_clk_i,
input logic src_rst_ni,
AXI_LITE.Slave src,
// master side - clocked by `dst_clk_i`
input logic dst_clk_i,
input logic dst_rst_ni,
AXI_LITE.Master dst
);
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)
req_t src_req, dst_req;
resp_t src_resp, dst_resp;
`AXI_LITE_ASSIGN_TO_REQ(src_req, src)
`AXI_LITE_ASSIGN_FROM_RESP(src, src_resp)
`AXI_LITE_ASSIGN_FROM_REQ(dst, dst_req)
`AXI_LITE_ASSIGN_TO_RESP(dst_resp, dst)
axi_cdc #(
.aw_chan_t ( aw_chan_t ),
.w_chan_t ( w_chan_t ),
.b_chan_t ( b_chan_t ),
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( req_t ),
.axi_resp_t ( resp_t ),
.LogDepth ( LOG_DEPTH )
) i_axi_cdc (
.src_clk_i,
.src_rst_ni,
.src_req_i ( src_req ),
.src_resp_o ( src_resp ),
.dst_clk_i,
.dst_rst_ni,
.dst_req_o ( dst_req ),
.dst_resp_i ( dst_resp )
);
endmodule |
module axi_lite_regs #(
/// The size of the register field in bytes.
parameter int unsigned RegNumBytes = 32'd0,
/// Address width of the AXI4-Lite port.
///
/// The minimum value of this parameter is `$clog2(RegNumBytes)`.
parameter int unsigned AxiAddrWidth = 32'd0,
/// Data width of the AXI4-Lite port.
parameter int unsigned AxiDataWidth = 32'd0,
/// Only allow *privileged* accesses on the AXI4-Lite port.
///
/// If this parameter is set to `1`, this module only allows reads and writes that have the
/// `AxProt[0]` bit set. If a transaction does not have the `AxProt[0]` bit set, this module
/// replies with `SLVERR` and does not read or write register data.
parameter bit PrivProtOnly = 1'b0,
/// Only allow *secure* accesses on the AXI4-Lite port.
///
/// If this parameter is set to `1`, this module only allows reads and writes that have the
/// `AxProt[1]` bit set. If a transaction does not have the `AxProt[1]` bit set, this module
/// replies with `SLVERR` and does not read or write register data.
parameter bit SecuProtOnly = 1'b0,
/// Define individual bytes as *read-only from the AXI4-Lite port*.
///
/// This parameter is an array with one bit for each byte. If that bit is `0`, the byte can be
/// read and written on the AXI4-Lite port; if that bit is `1`, the byte can only be read on the
/// AXI4-Lite port.
parameter logic [RegNumBytes-1:0] AxiReadOnly = {RegNumBytes{1'b0}},
/// Constant (=**do not overwrite!**); type of a byte is 8 bit.
parameter type byte_t = logic [7:0],
/// Reset value for the whole register array.
///
/// This parameter is an array with one byte value for each byte. At reset, each byte is
/// assigned its value from this array.
parameter byte_t [RegNumBytes-1:0] RegRstVal = {RegNumBytes{8'h00}},
/// Request struct of the AXI4-Lite port.
parameter type req_lite_t = logic,
/// Response struct of the AXI4-Lite port.
parameter type resp_lite_t = logic
) (
/// Rising-edge clock of all ports
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
/// AXI4-Lite slave request
input req_lite_t axi_req_i,
/// AXI4-Lite slave response
output resp_lite_t axi_resp_o,
/// Signals that a byte is being written from the AXI4-Lite port in the current clock cycle. This
/// signal is asserted regardless of the value of `AxiReadOnly` and can therefore be used by
/// surrounding logic to react to write-on-read-only-byte errors.
output logic [RegNumBytes-1:0] wr_active_o,
/// Signals that a byte is being read from the AXI4-Lite port in the current clock cycle.
output logic [RegNumBytes-1:0] rd_active_o,
/// Input value of each byte. If `reg_load_i` is `1` for a byte in the current clock cycle, the
/// byte register in this module is set to the value of the byte in `reg_d_i` at the next clock
/// edge.
input byte_t [RegNumBytes-1:0] reg_d_i,
/// Load enable of each byte.
///
/// If `reg_load_i` is `1` for a byte defined as non-read-only in a clock cycle, an AXI4-Lite
/// write transaction is stalled when it tries to write the same byte. That is, a write
/// transaction is stalled if all of the following conditions are true for the byte at index `i`:
/// - `AxiReadOnly[i]` is `0`,
/// - `reg_load_i[i]` is `1`,
/// - the bit in `axi_req_i.w.strb` that affects the byte is `1`.
///
/// If unused, set this input to `'0`.
input logic [RegNumBytes-1:0] reg_load_i,
/// The registered value of each byte.
output byte_t [RegNumBytes-1:0] reg_q_o
);
// Define the number of register chunks needed to map all `RegNumBytes` to the AXI channel.
// Eg: `AxiDataWidth == 32'd32`
// AXI strb: 3 2 1 0
// | | | |
// *---------*---------* | | |
// | *-------|-*-------|-* | |
// | | *-----|-|-*-----|-|-* |
// | | | *---|-|-|-*---|-|-|-*
// | | | | | | | | | | | |
// Reg byte: B A 9 8 7 6 5 4 3 2 1 0
// | chunk_2 | chunk_1 | chunk_0 |
localparam int unsigned AxiStrbWidth = AxiDataWidth / 32'd8;
localparam int unsigned NumChunks = cf_math_pkg::ceil_div(RegNumBytes, AxiStrbWidth);
localparam int unsigned ChunkIdxWidth = (NumChunks > 32'd1) ? $clog2(NumChunks) : 32'd1;
// Type of the index to identify a specific register chunk.
typedef logic [ChunkIdxWidth-1:0] chunk_idx_t;
// Find out how many bits of the address are applicable for this module.
// Look at the `AddrWidth` number of LSBs to calculate the multiplexer index of the AXI.
localparam int unsigned AddrWidth = (RegNumBytes > 32'd1) ? ($clog2(RegNumBytes)+1) : 32'd2;
typedef logic [AddrWidth-1:0] addr_t;
// Define the address map which maps each register chunk onto an AXI address.
typedef struct packed {
int unsigned idx;
addr_t start_addr;
addr_t end_addr;
} axi_rule_t;
axi_rule_t [NumChunks-1:0] addr_map;
for (genvar i = 0; i < NumChunks; i++) begin : gen_addr_map
assign addr_map[i] = axi_rule_t'{
idx: i,
start_addr: addr_t'( i * AxiStrbWidth),
end_addr: addr_t'((i+1)* AxiStrbWidth)
};
end
// Channel definitions for spill register
typedef logic [AxiDataWidth-1:0] axi_data_t;
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, axi_data_t)
// Register array declarations
byte_t [RegNumBytes-1:0] reg_q, reg_d;
logic [RegNumBytes-1:0] reg_update;
// Write logic
chunk_idx_t aw_chunk_idx;
logic aw_dec_valid;
b_chan_lite_t b_chan;
logic b_valid, b_ready;
logic aw_prot_ok;
logic chunk_loaded, chunk_ro;
// Flag for telling that the protection level is the right one.
assign aw_prot_ok = (PrivProtOnly ? axi_req_i.aw.prot[0] : 1'b1) &
(SecuProtOnly ? axi_req_i.aw.prot[1] : 1'b1);
// Have a flag which is true if any of the bytes inside a chunk are directly loaded.
logic [AxiStrbWidth-1:0] load;
logic [AxiStrbWidth-1:0] read_only;
// Address of the lowest byte byte of a chunk accessed by an AXI write transaction.
addr_t byte_w_addr;
assign byte_w_addr = addr_t'(aw_chunk_idx * AxiStrbWidth);
for (genvar i = 0; i < AxiStrbWidth; i++) begin : gen_load_assign
// Indexed byte address
addr_t reg_w_idx;
assign reg_w_idx = byte_w_addr + addr_t'(i);
// Only assert load flag for non read only bytes.
assign load[i] = (reg_w_idx < RegNumBytes) ?
(reg_load_i[reg_w_idx] && !AxiReadOnly[reg_w_idx]) : 1'b0;
// Flag to find out that all bytes of the chunk are read only.
assign read_only[i] = (reg_w_idx < RegNumBytes) ? AxiReadOnly[reg_w_idx] : 1'b1;
end
// Only assert the loaded flag if there could be a load conflict between a strobe and load
// signal.
assign chunk_loaded = |(load & axi_req_i.w.strb);
assign chunk_ro = &read_only;
// Register write logic.
always_comb begin
automatic addr_t reg_byte_idx = '0;
// default assignments
reg_d = reg_q;
reg_update = '0;
// Channel handshake
axi_resp_o.aw_ready = 1'b0;
axi_resp_o.w_ready = 1'b0;
// Response
b_chan = b_chan_lite_t'{resp: axi_pkg::RESP_SLVERR, default: '0};
b_valid = 1'b0;
// write active flag
wr_active_o = '0;
// Control
// Handle all non AXI register loads.
for (int unsigned i = 0; i < RegNumBytes; i++) begin
if (reg_load_i[i]) begin
reg_d[i] = reg_d_i[i];
reg_update[i] = 1'b1;
end
end
// Handle load from AXI write.
// `b_ready` is allowed to be a condition as it comes from a spill register.
if (axi_req_i.aw_valid && axi_req_i.w_valid && b_ready) begin
// The write can be performed when these conditions are true:
// - AW decode is valid.
// - `axi_req_i.aw.prot` has the right value.
if (aw_dec_valid && aw_prot_ok) begin
// Stall write as long as any direct load is going on in the current chunk.
// Read-only bytes within a chunk have no influence on stalling.
if (!chunk_loaded) begin
// Go through all bytes on the W channel.
for (int unsigned i = 0; i < AxiStrbWidth; i++) begin
reg_byte_idx = byte_w_addr + addr_t'(i);
// Only execute if the byte is mapped onto the register array.
if (reg_byte_idx < RegNumBytes) begin
// Only update the reg from an AXI write if it is not `ReadOnly`.
// Only connect the data and load to the reg, if the byte is written from AXI.
// This allows for simultaneous direct load onto unwritten bytes.
if (!AxiReadOnly[reg_byte_idx] && axi_req_i.w.strb[i]) begin
reg_d[reg_byte_idx] = axi_req_i.w.data[8*i+:8];
reg_update[reg_byte_idx] = 1'b1;
end
wr_active_o[reg_byte_idx] = axi_req_i.w.strb[i];
end
end
b_chan.resp = chunk_ro ? axi_pkg::RESP_SLVERR : axi_pkg::RESP_OKAY;
b_valid = 1'b1;
axi_resp_o.aw_ready = 1'b1;
axi_resp_o.w_ready = 1'b1;
end
end else begin
// Send default B error response on each not allowed write transaction.
b_valid = 1'b1;
axi_resp_o.aw_ready = 1'b1;
axi_resp_o.w_ready = 1'b1;
end
end
end
// Read logic
chunk_idx_t ar_chunk_idx;
logic ar_dec_valid;
r_chan_lite_t r_chan;
logic r_valid, r_ready;
logic ar_prot_ok;
assign ar_prot_ok = (PrivProtOnly ? axi_req_i.ar.prot[0] : 1'b1) &
(SecuProtOnly ? axi_req_i.ar.prot[1] : 1'b1);
// Multiplexer to determine R channel
always_comb begin
automatic int unsigned reg_byte_idx = '0;
// Default R channel throws an error.
r_chan = r_chan_lite_t'{
data: axi_data_t'(32'hBA5E1E55),
resp: axi_pkg::RESP_SLVERR,
default: '0
};
// Default nothing is reading the registers
rd_active_o = '0;
// Read is valid on a chunk
if (ar_dec_valid && ar_prot_ok) begin
// Calculate the corresponding byte index from `ar_chunk_idx`.
for (int unsigned i = 0; i < AxiStrbWidth; i++) begin
reg_byte_idx = unsigned'(ar_chunk_idx) * AxiStrbWidth + i;
// Guard to not index outside the `reg_q_o` array.
if (reg_byte_idx < RegNumBytes) begin
r_chan.data[8*i+:8] = reg_q_o[reg_byte_idx];
rd_active_o[reg_byte_idx] = r_valid & r_ready;
end else begin
r_chan.data[8*i+:8] = 8'h00;
end
end
r_chan.resp = axi_pkg::RESP_OKAY;
end
end
assign r_valid = axi_req_i.ar_valid; // to spill register
assign axi_resp_o.ar_ready = r_ready; // from spill register
// Register array mapping, even read only register can be loaded over `reg_load_i`.
for (genvar i = 0; i < RegNumBytes; i++) begin : gen_rw_regs
`FFLARN(reg_q[i], reg_d[i], reg_update[i], RegRstVal[i], clk_i, rst_ni)
assign reg_q_o[i] = reg_q[i];
end
addr_decode #(
.NoIndices ( NumChunks ),
.NoRules ( NumChunks ),
.addr_t ( addr_t ),
.rule_t ( axi_rule_t )
) i_aw_decode (
.addr_i ( addr_t'(axi_req_i.aw.addr) ), // Only look at the `AddrWidth` LSBs.
.addr_map_i ( addr_map ),
.idx_o ( aw_chunk_idx ),
.dec_valid_o ( aw_dec_valid ),
.dec_error_o ( /*not used*/ ),
.en_default_idx_i ( '0 ),
.default_idx_i ( '0 )
);
addr_decode #(
.NoIndices ( NumChunks ),
.NoRules ( NumChunks ),
.addr_t ( addr_t ),
.rule_t ( axi_rule_t )
) i_ar_decode (
.addr_i ( addr_t'(axi_req_i.ar.addr) ), // Only look at the `AddrWidth` LSBs.
.addr_map_i ( addr_map ),
.idx_o ( ar_chunk_idx ),
.dec_valid_o ( ar_dec_valid ),
.dec_error_o ( /*not used*/ ),
.en_default_idx_i ( '0 ),
.default_idx_i ( '0 )
);
// Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs.
spill_register #(
.T ( b_chan_lite_t ),
.Bypass ( 1'b0 )
) i_b_spill_register (
.clk_i,
.rst_ni,
.valid_i ( b_valid ),
.ready_o ( b_ready ),
.data_i ( b_chan ),
.valid_o ( axi_resp_o.b_valid ),
.ready_i ( axi_req_i.b_ready ),
.data_o ( axi_resp_o.b )
);
// Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs.
spill_register #(
.T ( r_chan_lite_t ),
.Bypass ( 1'b0 )
) i_r_spill_register (
.clk_i,
.rst_ni,
.valid_i ( r_valid ),
.ready_o ( r_ready ),
.data_i ( r_chan ),
.valid_o ( axi_resp_o.r_valid ),
.ready_i ( axi_req_i.r_ready ),
.data_o ( axi_resp_o.r )
);
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
assert (RegNumBytes > 32'd0) else
$fatal(1, "The number of bytes must be at least 1!");
assert (AxiAddrWidth >= AddrWidth) else
$fatal(1, "AxiAddrWidth is not wide enough, has to be at least %0d-bit wide!", AddrWidth);
assert ($bits(axi_req_i.aw.addr) == AxiAddrWidth) else
$fatal(1, "AddrWidth does not match req_i.aw.addr!");
assert ($bits(axi_req_i.ar.addr) == AxiAddrWidth) else
$fatal(1, "AddrWidth does not match req_i.ar.addr!");
assert (AxiDataWidth == $bits(axi_req_i.w.data)) else
$fatal(1, "AxiDataWidth has to be: AxiDataWidth == $bits(axi_req_i.w.data)!");
assert (AxiDataWidth == $bits(axi_resp_o.r.data)) else
$fatal(1, "AxiDataWidth has to be: AxiDataWidth == $bits(axi_resp_o.r.data)!");
assert (RegNumBytes == $bits(AxiReadOnly)) else
$fatal(1, "Each register needs a `ReadOnly` flag!");
end
default disable iff (~rst_ni);
for (genvar i = 0; i < RegNumBytes; i++) begin
assert property (@(posedge clk_i) (!reg_load_i[i] && AxiReadOnly[i] |=> $stable(reg_q_o[i])))
else $fatal(1, "Read-only register at `byte_index: %0d` was changed by AXI!", i);
end
`endif
// pragma translate_on
endmodule |
module axi_lite_regs_intf #(
parameter type byte_t = logic [7:0],
parameter int unsigned REG_NUM_BYTES = 32'd0,
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
parameter bit PRIV_PROT_ONLY = 1'd0,
parameter bit SECU_PROT_ONLY = 1'd0,
parameter logic [REG_NUM_BYTES-1:0] AXI_READ_ONLY = {REG_NUM_BYTES{1'b0}},
parameter byte_t [REG_NUM_BYTES-1:0] REG_RST_VAL = {REG_NUM_BYTES{8'h00}}
) (
input logic clk_i,
input logic rst_ni,
AXI_LITE.Slave slv,
output logic [REG_NUM_BYTES-1:0] wr_active_o,
output logic [REG_NUM_BYTES-1:0] rd_active_o,
input byte_t [REG_NUM_BYTES-1:0] reg_d_i,
input logic [REG_NUM_BYTES-1:0] reg_load_i,
output byte_t [REG_NUM_BYTES-1:0] reg_q_o
);
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_lite_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t)
req_lite_t axi_lite_req;
resp_lite_t axi_lite_resp;
`AXI_LITE_ASSIGN_TO_REQ(axi_lite_req, slv)
`AXI_LITE_ASSIGN_FROM_RESP(slv, axi_lite_resp)
axi_lite_regs #(
.RegNumBytes ( REG_NUM_BYTES ),
.AxiAddrWidth ( AXI_ADDR_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.PrivProtOnly ( PRIV_PROT_ONLY ),
.SecuProtOnly ( SECU_PROT_ONLY ),
.AxiReadOnly ( AXI_READ_ONLY ),
.RegRstVal ( REG_RST_VAL ),
.req_lite_t ( req_lite_t ),
.resp_lite_t ( resp_lite_t )
) i_axi_lite_regs (
.clk_i,
.rst_ni,
.axi_req_i ( axi_lite_req ),
.axi_resp_o ( axi_lite_resp ),
.wr_active_o,
.rd_active_o,
.reg_d_i,
.reg_load_i,
.reg_q_o
);
// Validate parameters.
// pragma translate_off
`ifndef VERILATOR
initial begin: p_assertions
assert (AXI_ADDR_WIDTH == $bits(slv.aw_addr))
else $fatal(1, "AXI_ADDR_WIDTH does not match slv interface!");
assert (AXI_DATA_WIDTH == $bits(slv.w_data))
else $fatal(1, "AXI_DATA_WIDTH does not match slv interface!");
end
`endif
// pragma translate_on
endmodule |
module main_scu_bac_address_decoder
#(
parameter p_bus_address_width = 24,
parameter p_response_width = 3 ,
parameter p_bac_reg_offset_address_width = 10,
parameter p_kernel_reg_offset_address_width = 10
)
(
//clock & reset
input clk_i ,
input resetn_i ,
//Bus access interface
input bus_csb_i ,
input bus_wr_i ,
input[p_bus_address_width-1:0] bus_address_i ,
input[31:0] bus_write_data_i,
input[3:0] bus_byte_en_i ,
output reg [31:0] bus_read_data_o ,
output reg bus_ready_o ,
output reg [p_response_width-1:0] bus_response_o ,
//to BAC register
output bac_csb_o ,
output bac_wr_o ,
output[p_bac_reg_offset_address_width-1:0] bac_address_o ,
output[31:0] bac_write_data_o,
output[3:0] bac_byte_en_o ,
input [31:0] bac_read_data_i ,
input bac_ready_i ,
input[p_response_width-1:0] bac_response_i ,
//to register bank
output reg_csb_o ,
output reg_wr_o ,
output[p_kernel_reg_offset_address_width-1:0] reg_address_o ,
output[31:0] reg_write_data_o,
output[3:0] reg_byte_en_o ,
input [31:0] reg_read_data_i ,
input reg_ready_i ,
input [p_response_width-1:0] reg_response_i
);
//TODO address distribution
//BAC Reg 24'h00_0000
// 24'h00_03FF
//TX fifo 24'h00_0400
// 24'h00_07FC
//RX fifo 24'h00_0800
// 24'h00_0BFC
//BAC Reserved 24'h00_0C00
// 24'h00_0FFF
//Kernel Reg 24'h00_1000
// 24'h01_FFFF
//Memory IF 24'h02_0000
// 24'hFF_FFFF
logic bac_sel_s;
logic reg_sel_s;
logic bac_sel_r;
logic reg_sel_r;
//decoder
always@(*)begin
bac_sel_s=1'b0;
reg_sel_s=1'b0;
if(bus_address_i[23:0] < 24'h00_0040) begin
bac_sel_s= 1'b1;
end
else if(bus_address_i[23:0] >= 24'h00_0040 && bus_address_i[23:0] < 24'hc10 + 24'h00_0040 + 24'h4 ) begin
//TODO Extract the .csv max user offset address
reg_sel_s= 1'b1;
end
end
always@(posedge clk_i or negedge resetn_i)
begin
if(!resetn_i) begin
bac_sel_r<=1'b0;
reg_sel_r<=1'b0;
end
else begin
if(!bus_csb_i && bus_ready_o) begin
bac_sel_r<=bac_sel_s;
reg_sel_r<=reg_sel_s;
end
end
end
//BAC Reg
assign bac_csb_o =(bac_sel_s == 1)? bus_csb_i : 1'b1 ;
assign bac_wr_o =(bac_sel_s == 1)? bus_wr_i : 1'b0 ;
assign bac_address_o =(bac_sel_s == 1)? bus_address_i[p_bac_reg_offset_address_width-1:0] : {p_bac_reg_offset_address_width{1'b0} };
assign bac_write_data_o=(bac_sel_s == 1)? bus_write_data_i : 32'h0 ;
assign bac_byte_en_o =(bac_sel_s == 1)? bus_byte_en_i : 4'h0 ;
//Kernel Reg
////TODO?? need to make the kernel base address auto generated!!!
assign reg_csb_o =(reg_sel_s == 1)? bus_csb_i : 1'b1 ;
assign reg_wr_o =(reg_sel_s == 1)? bus_wr_i : 1'b0 ;
assign reg_address_o =(reg_sel_s == 1)? bus_address_i[p_bus_address_width-8:0]-17'h0040 : {p_kernel_reg_offset_address_width{1'b0} };
assign reg_write_data_o=(reg_sel_s == 1)? bus_write_data_i : 32'h0 ;
assign reg_byte_en_o =(reg_sel_s == 1)? bus_byte_en_i : 4'h0 ;
always@(*)
begin
bus_read_data_o = 'hdead_dead;
bus_response_o = 'h0;
if(bac_sel_r) begin
bus_read_data_o = bac_read_data_i ;
bus_response_o = bac_response_i ;
end
else if(reg_sel_r) begin //TODO Add else to the always block
bus_read_data_o = reg_read_data_i ;
bus_response_o = reg_response_i ;
end
end
always@(*)
begin
bus_ready_o = 'h1;
if(bac_sel_s) begin
bus_ready_o = bac_ready_i ;
end
else if(reg_sel_s) begin //TODO Add else to the alwyas block
bus_ready_o = reg_ready_i ;
end
end
//TODO??
//
//need to verify the request_ready, response_ready behavior ,
//currently for BAC, kernel register, it is tied to "1"
//But in the future, when there is memory, it will need these two ready with
//correct backpressure on request and response
endmodule |
module main_scu_bus_access_control_top
#(
parameter p_num_of_bac_register =16,
parameter p_bus_address_width = 24,
parameter p_response_width = 3,
parameter p_memory_address_width = 24, // memory will give full 24 bits address
parameter p_bac_reg_offset_address_width = 6,
parameter p_kernel_reg_offset_address_width = 12,
parameter p_client_num = 1,
parameter p_func_int0_num = 32,
parameter p_func_int1_num = 32,
parameter p_error_int_num = 32,
parameter p_tx_fifo_common_int_num = 8,
parameter p_rx_fifo_common_int_num = 8
)
(
//clock & reset
input clk_i ,
input resetn_i ,
//DFT port
input dft_scan_en_i , //It will be used to control the clock gate cell
input jtag_rst_sync_bypass_i , //It will be used to control the Reset sync cell
input bus_clk_i , // in case it is async bridge
//synced reset for AHB2ESRAM Async Bridge
output synced_hclk_reset_o ,
//SRAM Bus access interface
input bus_csb_i ,
input bus_wr_i ,
input[p_bus_address_width-1:0] bus_address_i ,
input[31:0] bus_write_data_i ,
input[3:0] bus_byte_en_i ,
output reg [31:0] bus_read_data_o ,
output reg bus_ready_o ,
output reg [p_response_width-1:0] bus_response_o ,
//to register bank
output reg_csb_o ,
output reg_wr_o ,
output[p_kernel_reg_offset_address_width-1:0] reg_address_o ,
output[31:0] reg_write_data_o ,
output[3:0] reg_byte_en_o ,
input [31:0] reg_read_data_i ,
input reg_ready_i ,
input[p_response_width-1:0] reg_response_i ,
//interrupt HW set from Kernel side
input [p_func_int0_num-1 :0] func_int0_hw_set_i ,
output func_int0_interrupt_o ,
//gated clocks
output gated_kernel_clk_o ,
output gated_regbank_clk_o ,
//synced kernel reset
output synced_kernel_reset_o
);
//in this top level, only Wiring(signals & parameters) is allowed!!!!!
//logic definition
//SRAM access interface
logic bac_csb_s ;
logic bac_wr_s ;
logic[p_bac_reg_offset_address_width-1:0] bac_address_s ;
logic[31:0] bac_write_data_s ;
logic[3:0] bac_byte_en_s ;
logic[31:0] bac_read_data_s ;
logic bac_ready_s ;
logic[p_response_width-1:0] bac_response_s ;
//TODO p_chipid_val p_checksum_val p_register_if_version_val p_module_versionid_val p_moduleid_val
logic [31:0] p_chipid_val_s ;
logic [31:0] p_checksum_val_s ;
logic [15:0] p_register_if_version_val_s;
logic [7:0] p_module_versionid_val_s ;
logic [7:0] p_moduleid_val_s ;
//common interrupts
logic [p_func_int0_num-1 :0] func_int0_enable_set_s ;
logic [p_func_int0_num-1 :0] func_int0_enable_clr_s ;
logic [p_func_int0_num-1 :0] func_int0_sw_set_s ;
logic [p_func_int0_num-1 :0] func_int0_sw_clr_s ;
logic [p_func_int0_num-1 :0] func_int0_enable_status_s ;
logic [p_func_int0_num-1 :0] func_int0_enabled_int_status_s ;
logic [p_func_int0_num-1 :0] func_int0_int_status_s ;
//--
logic[p_client_num-1:0] reg_bank_clk_i_en_set_wo_s ;
logic[p_client_num-1:0] reg_bank_clk_i_en_clr_wo_s ;
logic[p_client_num-1:0] reg_bank_clk_i_en_sta_ro_s ;
logic[p_client_num-1:0] kernel_clk_i_en_set_wo_s ;
logic[p_client_num-1:0] kernel_clk_i_en_clr_wo_s ;
logic[p_client_num-1:0] kernel_clk_i_en_sta_ro_s ;
//TODO because delete these ports---
//logic first_access_error_clear_wo_o ;
//logic last_access_error_clear_wo_o ;
//logic[31:0] first_access_error_ro_i ;
//logic[31:0] last_access_error_ro_i ;
//--
logic synced_kernel_reset_s;
//---
main_scu_bac_address_decoder
#(
.p_bus_address_width (p_bus_address_width ),
.p_response_width (p_response_width ),
.p_bac_reg_offset_address_width (p_bac_reg_offset_address_width ),
.p_kernel_reg_offset_address_width(p_kernel_reg_offset_address_width)
) main_scu_bac_address_decoder_inst
(
.clk_i (clk_i ),
.resetn_i (synced_kernel_reset_s ),
.bus_csb_i (bus_csb_i ),
.bus_wr_i (bus_wr_i ),
.bus_address_i (bus_address_i ),
.bus_write_data_i (bus_write_data_i),
.bus_byte_en_i (bus_byte_en_i ),
.bus_read_data_o (bus_read_data_o ),
.bus_ready_o (bus_ready_o ),
.bus_response_o (bus_response_o ),
.bac_csb_o (bac_csb_s ),
.bac_wr_o (bac_wr_s ),
.bac_address_o (bac_address_s ),
.bac_write_data_o (bac_write_data_s),
.bac_byte_en_o (bac_byte_en_s ),
.bac_read_data_i (bac_read_data_s ),
.bac_ready_i (bac_ready_s ),
.bac_response_i (bac_response_s ),
.reg_csb_o (reg_csb_o ),
.reg_wr_o (reg_wr_o ),
.reg_address_o (reg_address_o ),
.reg_write_data_o (reg_write_data_o),
.reg_byte_en_o (reg_byte_en_o ),
.reg_read_data_i (reg_read_data_i ),
.reg_ready_i (reg_ready_i ),
.reg_response_i (reg_response_i )
);
//TODO main_scu_bac_register_block --> main_scu_bac_register_block_wrapper---
main_scu_bac_register_wrapper
#(
.p_bac_reg_offset_address_width(p_bac_reg_offset_address_width),
.p_response_width (p_response_width ),
.p_num_of_bac_register (p_num_of_bac_register ), // 4 TX/RX FIFO is not consider here
.p_tx_fifo_common_int_num (p_tx_fifo_common_int_num ),
.p_rx_fifo_common_int_num (p_rx_fifo_common_int_num )
) main_scu_bac_register_wrapper_inst
(
.clk_i (clk_i ),
.rst_n_i (synced_kernel_reset_s ),
.bac_csb_i (bac_csb_s ),
.bac_wr_i (bac_wr_s ),
.bac_address_i (bac_address_s ),
.bac_write_data_i (bac_write_data_s ),
.bac_byte_en_i (bac_byte_en_s ),
.bac_read_data_o (bac_read_data_s ),
.bac_ready_o (bac_ready_s ),
.bac_response_o (bac_response_s ),
//TODO?? need to connect for real function ..
.register_bank_clock_enable_set_wo_set_o (reg_bank_clk_i_en_set_wo_s ),
.register_bank_clock_enable_clr_wo_clr_o (reg_bank_clk_i_en_clr_wo_s ),
.register_bank_clock_enable_status_ro_status_i (reg_bank_clk_i_en_sta_ro_s ),
.kernel_clock_enable_set_wo_set_o (kernel_clk_i_en_set_wo_s ),
.kernel_clock_enable_clr_wo_clr_o (kernel_clk_i_en_clr_wo_s ),
.kernel_clock_enable_status_ro_status_i (kernel_clk_i_en_sta_ro_s ),
.func_int_0_enable_set_wo_set_o (func_int0_enable_set_s ),
.func_int_0_enable_clear_wo_clear_o (func_int0_enable_clr_s ),
.func_int_0_set_wo_set_o (func_int0_sw_set_s ),
.func_int_0_clr_wo_clear_o (func_int0_sw_clr_s ),
.func_int_0_enable_status_ro_status_i (func_int0_enable_status_s ),
.func_int_0_status_enabled_ro_status_i (func_int0_enabled_int_status_s ),
.func_int_0_status_ro_status_i (func_int0_int_status_s ),
.chipid_ro_chipid_i (p_chipid_val_s ),
.moduleid_ro_module_id_i (p_moduleid_val_s ),
.moduleid_ro_module_version_i (p_module_versionid_val_s ),
.moduleid_ro_reg_if_version_i (p_register_if_version_val_s ),
.checksum_ro_checksum_i (p_checksum_val_s )
);
//---
main_scu_bac_common_interrupt_handle
#(
.p_func_int0_num (p_func_int0_num ),
.p_func_int1_num (p_func_int1_num ),
.p_error_int_num (p_error_int_num ),
.p_tx_fifo_common_int_num (p_tx_fifo_common_int_num ),
.p_rx_fifo_common_int_num (p_rx_fifo_common_int_num )
) main_scu_bac_common_interrupt_handle_inst
(
.func_int0_enable_set_i (func_int0_enable_set_s ),
.func_int0_enable_clr_i (func_int0_enable_clr_s ),
.func_int0_hw_set_i (func_int0_hw_set_i ),
.func_int0_sw_set_i (func_int0_sw_set_s ),
.func_int0_sw_clr_i (func_int0_sw_clr_s ),
.func_int0_enable_status_o (func_int0_enable_status_s ),
.func_int0_enabled_int_status_o (func_int0_enabled_int_status_s ),
.func_int0_int_status_o (func_int0_int_status_s ),
.func_int0_interrupt_o (func_int0_interrupt_o ),
.clk_i (clk_i ),
.resetn_i (synced_kernel_reset_s )
);
//---
main_scu_bac_misc
#(
.p_client_num(p_client_num)
) main_scu_bac_misc_inst
(
.kernel_clk_i (clk_i ),
.resetn_i (resetn_i ),
.dft_scan_en_i (dft_scan_en_i ) ,
.jtag_rst_sync_bypass_i (jtag_rst_sync_bypass_i ) ,
//---
.reg_bank_clk_en_set_i (reg_bank_clk_i_en_set_wo_s ),
.reg_bank_clk_en_clr_i (reg_bank_clk_i_en_clr_wo_s ),
.reg_bank_clk_en_sta_o (reg_bank_clk_i_en_sta_ro_s ),
.kernel_clk_en_set_i (kernel_clk_i_en_set_wo_s ),
.kernel_clk_en_clr_i (kernel_clk_i_en_clr_wo_s ),
.kernel_clk_en_sta_o (kernel_clk_i_en_sta_ro_s ),
//TODO p_chipid_val p_checksum_val p_register_if_version_val p_moduleid_val p_moduleid_val
.p_chipid_val_o (p_chipid_val_s ),
.p_checksum_val_o (p_checksum_val_s ),
.p_register_if_version_val_o (p_register_if_version_val_s ),
.p_module_versionid_val_o (p_module_versionid_val_s ),
.p_moduleid_val_o (p_moduleid_val_s ),
.gated_kernel_clk_o (gated_kernel_clk_o ),
.gated_regbank_clk_o (gated_regbank_clk_o ),
.hclk_i (bus_clk_i ),
.synced_hclk_reset_o (synced_hclk_reset_o ),
.synced_kernel_reset_o (synced_kernel_reset_s )
);
assign synced_kernel_reset_o = synced_kernel_reset_s;
endmodule |
module TestBench ();
parameter CLOCK_FREQ = 100_000_000;
parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;
// setup clock and reset
reg clk, rst;
initial clk = 'b0;
always #(CLOCK_PERIOD/2) clk = ~clk;
Tile dut (
.clock(clk),
.reset(rst),
.io_led()
);
reg clock;
initial begin
// set up logging
// $dumpfile("out.vcd");
// $dumpvars(0, top);
$fsdbDumpfile("out.fsdb");
$fsdbDumpvars("+all");
#0;
rst = 1;
$display("[TEST]\tRESET pulled HIGH.");
repeat(2) @(posedge clk);
@(negedge clk);
rst = 0;
$display("[TEST]\tRESET pulled LOW.");
@(posedge clk);
repeat(100) @(posedge clk);
$display("[TEST]\tDONE.");
$finish;
end
endmodule |
module TB_Tile();
parameter CLOCK_FREQ = 100_000_000;
parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;
// setup clock and reset
reg clk, rst;
initial clk = 'b0;
always #(CLOCK_PERIOD/2) clk = ~clk;
Tile dut (
.clk(clk),
.rst(rst),
.led()
);
initial begin
#0;
rst = 1;
$display("[TEST]\tRESET pulled HIGH.");
repeat(2) @(posedge clk);
@(negedge clk);
rst = 0;
$display("[TEST]\tRESET pulled LOW.");
@(posedge clk);
repeat(10000) @(posedge clk);
$finish();
end
endmodule |
module nvme_buffer_ram
#(
parameter ADDR_BITS = 8,
parameter DEPTH = 2**8
) (
input wire wclk,
input wire [3:0] we,
input wire [ADDR_BITS-1:0] waddr,
input wire [127:0] din,
input wire rclk,
input wire re,
input wire [ADDR_BITS-1:0] raddr,
output logic [127:0] dout
);
reg [31:0] ram0 [0:DEPTH-1];
reg [31:0] ram1 [0:DEPTH-1];
reg [31:0] ram2 [0:DEPTH-1];
reg [31:0] ram3 [0:DEPTH-1];
always @(posedge rclk)
begin : READ_P
if (re) begin
dout <= {ram3[raddr], ram2[raddr], ram1[raddr], ram0[raddr]};
end
end
always @(posedge wclk)
begin : WRITE_P
if (we[0]) begin
ram0[waddr] <= din[31:0];
end
if (we[1]) begin
ram1[waddr] <= din[63:32];
end
if (we[2]) begin
ram2[waddr] <= din[95:64];
end
if (we[3]) begin
ram3[waddr] <= din[127:96];
end
end
endmodule |
module nvme_host
(
input wire axi_aclk,
input wire axi_aresetn,
// Action/MMIO to NMVE Host Slave AXI Lite IF
input wire [`HOST_ADDR_BITS - 1:0] host_s_axi_awaddr,
input wire host_s_axi_awvalid,
output logic host_s_axi_awready,
input wire [31:0] host_s_axi_wdata,
input wire [3:0] host_s_axi_wstrb,
input wire host_s_axi_wvalid,
output logic host_s_axi_wready,
output logic [1:0] host_s_axi_bresp,
output logic host_s_axi_bvalid,
input wire host_s_axi_bready,
input wire [`HOST_ADDR_BITS - 1:0] host_s_axi_araddr,
input wire host_s_axi_arvalid,
output logic host_s_axi_arready,
output logic [31:0] host_s_axi_rdata,
output logic [1:0] host_s_axi_rresp,
output logic host_s_axi_rvalid,
input wire host_s_axi_rready,
// NVMe Host to PCIE Master AXI Lite IF
output logic [`PCIE_M_ADDR_BITS-1:0] pcie_m_axi_awaddr,
output logic [2:0] pcie_m_axi_awprot,
output logic pcie_m_axi_awvalid,
input wire pcie_m_axi_awready,
output logic [31:0] pcie_m_axi_wdata,
output logic [3:0] pcie_m_axi_wstrb,
output logic pcie_m_axi_wvalid,
input wire pcie_m_axi_wready,
input wire [1:0] pcie_m_axi_bresp,
input wire pcie_m_axi_bvalid,
output logic pcie_m_axi_bready,
output logic [`PCIE_M_ADDR_BITS-1:0] pcie_m_axi_araddr,
output logic [2:0] pcie_m_axi_arprot,
output logic pcie_m_axi_arvalid,
input wire pcie_m_axi_arready,
input wire [31:0] pcie_m_axi_rdata,
input wire [1:0] pcie_m_axi_rresp,
input wire pcie_m_axi_rvalid,
output logic pcie_m_axi_rready,
// NVMe Host to PCIE Slave AXI MM IF
input wire [`PCIE_S_ID_BITS-1:0] pcie_s_axi_awid,
input wire [`PCIE_S_ADDR_BITS-1:0] pcie_s_axi_awaddr,
input wire [7:0] pcie_s_axi_awlen,
input wire [2:0] pcie_s_axi_awsize,
input wire [1:0] pcie_s_axi_awburst,
input wire pcie_s_axi_awvalid,
output logic pcie_s_axi_awready,
input wire [127:0] pcie_s_axi_wdata,
input wire [15:0] pcie_s_axi_wstrb,
input wire pcie_s_axi_wlast,
input wire pcie_s_axi_wvalid,
output logic pcie_s_axi_wready,
output logic [`PCIE_S_ID_BITS-1:0] pcie_s_axi_bid,
output logic [1:0] pcie_s_axi_bresp,
output logic pcie_s_axi_bvalid,
input wire pcie_s_axi_bready,
input wire [`PCIE_S_ID_BITS-1:0] pcie_s_axi_arid,
input wire [`PCIE_S_ADDR_BITS-1:0] pcie_s_axi_araddr,
input wire [7:0] pcie_s_axi_arlen,
input wire [2:0] pcie_s_axi_arsize,
input wire [1:0] pcie_s_axi_arburst,
input wire pcie_s_axi_arvalid,
output logic pcie_s_axi_arready,
output logic [`PCIE_S_ID_BITS-1:0] pcie_s_axi_rid,
output logic [127:0] pcie_s_axi_rdata,
output logic [1:0] pcie_s_axi_rresp,
output logic pcie_s_axi_rlast,
output logic pcie_s_axi_rvalid,
input wire pcie_s_axi_rready
);
// Each submission queue entry is 64 bytes, buffer width is 16 bytes
// Each completion queue entry is 16 bytes, buffer width is 16 bytes
// There is a separate Admin and IO queue for each SSD drive
localparam integer TX_DEPTH = (`ADM_SQ_NUM * 2 + `IO_SQ_NUM * 2 + `DATA_SQ_NUM) * 4;
localparam integer RX_DEPTH = (`ADM_CQ_NUM * 2 + `IO_CQ_NUM * 2 + `DATA_CQ_NUM) * 1;
// Buffer initialization done
logic init_done;
// Tx Buffer Signals
localparam TX_ADDR_BITS = $clog2(TX_DEPTH);
logic [3:0] tx_write;
logic [TX_ADDR_BITS-1:0] tx_waddr;
logic [127:0] tx_wdata;
logic tx_read;
logic [TX_ADDR_BITS-1:0] tx_raddr;
logic [127:0] tx_rdata;
// Rx Buffer Signals
localparam RX_ADDR_BITS = $clog2(RX_DEPTH);
logic rx_write_valid;
logic [3:0] rx_write;
logic [RX_ADDR_BITS-1:0] rx_waddr;
logic [127:0] rx_wdata;
logic rx_read;
logic [RX_ADDR_BITS-1:0] rx_raddr;
logic [127:0] rx_rdata;
// PCIE Master Write IF
logic pcie_write;
logic [31:0] pcie_waddr;
logic [31:0] pcie_wdata;
logic pcie_wdone;
logic pcie_werror;
// PCIE Master Read IF
logic pcie_read;
logic [31:0] pcie_raddr;
logic [31:0] pcie_rdata;
logic pcie_rdone;
logic pcie_rerror;
// Action/MMIO AXI Lite Slave
nvme_host_slave #(.TX_ADDR_BITS(TX_ADDR_BITS), .RX_ADDR_BITS(RX_ADDR_BITS)) host_slave_i
(
.*
);
// PCIE AXI Lite Master
nvme_pcie_master pcie_master_i
(
.*
);
// PCIE AXI MM Slave
nvme_pcie_slave #(.TX_ADDR_BITS(TX_ADDR_BITS), .RX_ADDR_BITS(RX_ADDR_BITS)) pcie_slave_i
(
.*
);
// Tx Buffer Instantiation
nvme_buffer_ram #(.ADDR_BITS(TX_ADDR_BITS), .DEPTH(TX_DEPTH)) tx_ram_i
(
.wclk(axi_aclk),
.we(tx_write),
.waddr(tx_waddr),
.din(tx_wdata),
.rclk(axi_aclk),
.re(tx_read),
.raddr(tx_raddr),
.dout(tx_rdata)
);
// Rx Buffer Instantiation
nvme_buffer_ram #(.ADDR_BITS(RX_ADDR_BITS), .DEPTH(RX_DEPTH)) rx_ram_i
(
.wclk(axi_aclk),
.we(rx_write),
.waddr(rx_waddr),
.din(rx_wdata),
.rclk(axi_aclk),
.re(rx_read),
.raddr(rx_raddr),
.dout(rx_rdata)
);
endmodule |
module nvme_top (
/* Action AXI Bus: Here we should see the register reads/writes */
input wire ACT_NVME_ACLK,
input wire ACT_NVME_ARESETN,
input wire [31:0]ACT_NVME_AXI_araddr,
input wire [1:0]ACT_NVME_AXI_arburst,
input wire [3:0]ACT_NVME_AXI_arcache,
input wire [7:0]ACT_NVME_AXI_arlen,
input wire [0:0]ACT_NVME_AXI_arlock,
input wire [2:0]ACT_NVME_AXI_arprot,
input wire [3:0]ACT_NVME_AXI_arqos,
output wire ACT_NVME_AXI_arready,
input wire [3:0]ACT_NVME_AXI_arregion,
input wire [2:0]ACT_NVME_AXI_arsize,
input wire ACT_NVME_AXI_arvalid,
input wire [31:0]ACT_NVME_AXI_awaddr,
input wire [1:0]ACT_NVME_AXI_awburst,
input wire [3:0]ACT_NVME_AXI_awcache,
input wire [7:0]ACT_NVME_AXI_awlen,
input wire [0:0]ACT_NVME_AXI_awlock,
input wire [2:0]ACT_NVME_AXI_awprot,
input wire [3:0]ACT_NVME_AXI_awqos,
output wire ACT_NVME_AXI_awready,
input wire [3:0]ACT_NVME_AXI_awregion,
input wire [2:0]ACT_NVME_AXI_awsize,
input wire ACT_NVME_AXI_awvalid,
input wire ACT_NVME_AXI_bready,
output wire [1:0]ACT_NVME_AXI_bresp,
output wire ACT_NVME_AXI_bvalid,
output wire [31:0]ACT_NVME_AXI_rdata,
output wire ACT_NVME_AXI_rlast,
input wire ACT_NVME_AXI_rready,
output wire [1:0]ACT_NVME_AXI_rresp,
output wire ACT_NVME_AXI_rvalid,
input wire [31:0]ACT_NVME_AXI_wdata,
input wire ACT_NVME_AXI_wlast,
output wire ACT_NVME_AXI_wready,
input wire [3:0]ACT_NVME_AXI_wstrb,
input wire ACT_NVME_AXI_wvalid,
/* SDRAM Access AXI Bus: Here we need to copy data to or from */
output wire [`DDR_M_ADDRBWIDTH-1:0]DDR_M_AXI_araddr,
output wire [1:0]DDR_M_AXI_arburst,
output wire [3:0]DDR_M_AXI_arcache,
output wire [3:0]DDR_M_AXI_arid,
output wire [7:0]DDR_M_AXI_arlen,
output wire [0:0]DDR_M_AXI_arlock,
output wire [2:0]DDR_M_AXI_arprot,
output wire [3:0]DDR_M_AXI_arqos,
input wire [0:0]DDR_M_AXI_arready,
output wire [3:0]DDR_M_AXI_arregion,
output wire [2:0]DDR_M_AXI_arsize,
output wire [0:0]DDR_M_AXI_arvalid,
output wire [`DDR_M_ADDRBWIDTH-1:0]DDR_M_AXI_awaddr,
output wire [1:0]DDR_M_AXI_awburst,
output wire [3:0]DDR_M_AXI_awcache,
output wire [3:0]DDR_M_AXI_awid,
output wire [7:0]DDR_M_AXI_awlen,
output wire [0:0]DDR_M_AXI_awlock,
output wire [2:0]DDR_M_AXI_awprot,
output wire [3:0]DDR_M_AXI_awqos,
input wire [0:0]DDR_M_AXI_awready,
output wire [3:0]DDR_M_AXI_awregion,
output wire [2:0]DDR_M_AXI_awsize,
output wire [0:0]DDR_M_AXI_awvalid,
input wire [3:0]DDR_M_AXI_bid,
output wire [0:0]DDR_M_AXI_bready,
input wire [1:0]DDR_M_AXI_bresp,
input wire [0:0]DDR_M_AXI_bvalid,
input wire [127:0]DDR_M_AXI_rdata,
input wire [3:0]DDR_M_AXI_rid,
input wire [0:0]DDR_M_AXI_rlast,
output wire [0:0]DDR_M_AXI_rready,
input wire [1:0]DDR_M_AXI_rresp,
input wire [15:0]DDR_M_AXI_ruser,
input wire [0:0]DDR_M_AXI_rvalid,
output wire [127:0]DDR_M_AXI_wdata,
output wire [0:0]DDR_M_AXI_wlast,
input wire [0:0]DDR_M_AXI_wready,
output wire [15:0]DDR_M_AXI_wstrb,
output wire [15:0]DDR_M_AXI_wuser,
output wire [0:0]DDR_M_AXI_wvalid,
/* Yet another AXI Bus */
input wire NVME_S_ACLK,
input wire NVME_S_ARESETN,
input wire [31:0]NVME_S_AXI_araddr,
input wire [2:0]NVME_S_AXI_arprot,
output wire [0:0]NVME_S_AXI_arready,
input wire [0:0]NVME_S_AXI_arvalid,
input wire [31:0]NVME_S_AXI_awaddr,
input wire [2:0]NVME_S_AXI_awprot,
output wire [0:0]NVME_S_AXI_awready,
input wire [0:0]NVME_S_AXI_awvalid,
input wire [0:0]NVME_S_AXI_bready,
output wire [1:0]NVME_S_AXI_bresp,
output wire [0:0]NVME_S_AXI_bvalid,
output wire [31:0]NVME_S_AXI_rdata,
input wire [0:0]NVME_S_AXI_rready,
output wire [1:0]NVME_S_AXI_rresp,
output wire [0:0]NVME_S_AXI_rvalid,
input wire [31:0]NVME_S_AXI_wdata,
output wire [0:0]NVME_S_AXI_wready,
input wire [3:0]NVME_S_AXI_wstrb,
input wire [0:0]NVME_S_AXI_wvalid,
/* And some other signals to control the PCIe root complexes in the orignal design */
output wire ddr_aclk,
output wire ddr_aresetn,
input wire nvme_reset_n,
input wire [3:0]pcie_rc0_rxn,
input wire [3:0]pcie_rc0_rxp,
output wire [3:0]pcie_rc0_txn,
output wire [3:0]pcie_rc0_txp,
input wire [3:0]pcie_rc1_rxn,
input wire [3:0]pcie_rc1_rxp,
output wire [3:0]pcie_rc1_txn,
output wire [3:0]pcie_rc1_txp,
input wire refclk_nvme_ch0_n,
input wire refclk_nvme_ch0_p,
input wire refclk_nvme_ch1_n,
input wire refclk_nvme_ch1_p
);
`define CONFIG_DDR_READWRITE_TEST 0 /* Enable test for DDR, write some data, read it back and compare */
/* Local hardware instances go here */
reg ACT_arready;
reg [31:0] ACT_araddr;
reg [31:0] ACT_rdata;
reg [0:0] ACT_awready;
reg [31:0] ACT_awaddr;
reg [31:0] ACT_wdata;
reg [0:0] ACT_wready;
reg [0:0] ACT_bvalid;
reg [1:0] ACT_bresp;
reg [0:0] ACT_rvalid;
reg [0:0] ACT_rlast;
reg [1:0] ACT_rresp;
/* DDR AXI Bus control signals */
reg DDR_aclk;
reg DDR_aresetn;
reg [3:0] DDR_arid;
reg [7:0] DDR_awlen;
reg [2:0] DDR_awsize;
reg [1:0] DDR_awburst;
reg [`DDR_M_ADDRBWIDTH-1:0] DDR_awaddr;
reg [0:0] DDR_arvalid;
reg [0:0] DDR_awvalid;
reg [127:0] DDR_wdata;
reg [15:0] DDR_wstrb;
reg [0:0] DDR_wvalid;
reg [3:0] DDR_awid;
reg [7:0] DDR_arlen;
reg [2:0] DDR_arsize;
reg [`DDR_M_ADDRBWIDTH-1:0] DDR_araddr;
reg [0:0] DDR_rready;
reg [0:0] DDR_arlock;
reg [0:0] DDR_wlast;
reg [0:0] DDR_bready;
reg [0:0] DDR_arburst;
reg [0:0] DDR_awlock;
reg [2:0] DDR_awprot;
reg [2:0] DDR_arprot;
reg [3:0] DDR_awqos;
reg [3:0] DDR_arqos;
reg [3:0] DDR_awcache;
reg [3:0] DDR_arcache;
reg [15:0] DDR_wuser;
reg [3:0] DDR_awregion;
reg [3:0] DDR_arregion;
/* SNAP Action AXI Interface */
assign ACT_NVME_AXI_arready = ACT_arready;
assign ACT_NVME_AXI_rdata = ACT_rdata;
assign ACT_NVME_AXI_awready = ACT_awready;
assign ACT_NVME_AXI_wready = ACT_wready;
assign ACT_NVME_AXI_bvalid = ACT_bvalid;
assign ACT_NVME_AXI_bresp = ACT_bresp;
assign ACT_NVME_AXI_rvalid = ACT_rvalid;
assign ACT_NVME_AXI_rresp = ACT_rresp;
assign ACT_NVME_AXI_rlast = ACT_rlast;
/* Access to Card DDR AXI Interface */
assign ddr_aclk = DDR_aclk;
assign ddr_aresetn = DDR_aresetn;
assign DDR_M_AXI_awid = DDR_awid;
assign DDR_M_AXI_arid = DDR_arid;
assign DDR_M_AXI_awlen = DDR_awlen;
assign DDR_M_AXI_awsize = DDR_awsize;
assign DDR_M_AXI_awburst = DDR_awburst;
assign DDR_M_AXI_awaddr = DDR_awaddr[`DDR_M_ADDRBWIDTH-1:0];
assign DDR_M_AXI_awvalid = DDR_awvalid;
assign DDR_M_AXI_wdata = DDR_wdata;
assign DDR_M_AXI_wstrb = DDR_wstrb;
assign DDR_M_AXI_wvalid = DDR_wvalid;
assign DDR_M_AXI_wlast = DDR_wlast;
assign DDR_M_AXI_arvalid = DDR_arvalid;
assign DDR_M_AXI_arlen = DDR_arlen;
assign DDR_M_AXI_arsize = DDR_arsize;
assign DDR_M_AXI_araddr = DDR_araddr[`DDR_M_ADDRBWIDTH-1:0];
assign DDR_M_AXI_rready = DDR_rready;
assign DDR_M_AXI_bready = DDR_bready;
assign DDR_M_AXI_arburst = DDR_arburst;
assign DDR_M_AXI_awlock = DDR_awlock;
assign DDR_M_AXI_arlock = DDR_arlock;
assign DDR_M_AXI_awprot = DDR_awprot;
assign DDR_M_AXI_arprot = DDR_arprot;
assign DDR_M_AXI_awqos = DDR_awqos;
assign DDR_M_AXI_arqos = DDR_arqos;
assign DDR_M_AXI_awcache = DDR_awcache;
assign DDR_M_AXI_arcache = DDR_arcache;
assign DDR_M_AXI_wuser = DDR_wuser;
assign DDR_M_AXI_awregion = DDR_awregion;
assign DDR_M_AXI_arregion = DDR_arregion;
/* SNAP NVME AXI Interface: FIXME Figure out for what this is really used */
localparam ACTION_W_BITS = $clog2(`ACTION_W_NUM_REGS);
localparam ACTION_R_BITS = $clog2(`ACTION_R_NUM_REGS);
localparam SQ_INDEX_BITS = $clog2(`TOTAL_NUM_QUEUES);
logic [31:0] action_w_regs[`ACTION_W_NUM_REGS];
logic [31:0] action_r_regs[`ACTION_R_NUM_REGS];
logic [ACTION_R_BITS - 1: 0] action_r_index;
assign action_r_index = ACT_araddr[ACTION_R_BITS + 1: 2];
logic [ACTION_W_BITS - 1: 0] action_w_index;
assign action_w_index = ACT_awaddr[ACTION_W_BITS + 1: 2];
/* Tie status information to TRACK_n register bits */
assign action_r_regs[`ACTION_R_STATUS][16] = action_r_regs[`ACTION_R_TRACK_0][0];
assign action_r_regs[`ACTION_R_STATUS][17] = action_r_regs[`ACTION_R_TRACK_0 + 1][0];
assign action_r_regs[`ACTION_R_STATUS][18] = action_r_regs[`ACTION_R_TRACK_0 + 2][0];
assign action_r_regs[`ACTION_R_STATUS][19] = action_r_regs[`ACTION_R_TRACK_0 + 3][0];
assign action_r_regs[`ACTION_R_STATUS][20] = action_r_regs[`ACTION_R_TRACK_0 + 4][0];
assign action_r_regs[`ACTION_R_STATUS][21] = action_r_regs[`ACTION_R_TRACK_0 + 5][0];
assign action_r_regs[`ACTION_R_STATUS][22] = action_r_regs[`ACTION_R_TRACK_0 + 6][0];
assign action_r_regs[`ACTION_R_STATUS][23] = action_r_regs[`ACTION_R_TRACK_0 + 7][0];
assign action_r_regs[`ACTION_R_STATUS][24] = action_r_regs[`ACTION_R_TRACK_0 + 8][0];
assign action_r_regs[`ACTION_R_STATUS][25] = action_r_regs[`ACTION_R_TRACK_0 + 9][0];
assign action_r_regs[`ACTION_R_STATUS][26] = action_r_regs[`ACTION_R_TRACK_0 + 10][0];
assign action_r_regs[`ACTION_R_STATUS][27] = action_r_regs[`ACTION_R_TRACK_0 + 11][0];
assign action_r_regs[`ACTION_R_STATUS][28] = action_r_regs[`ACTION_R_TRACK_0 + 12][0];
assign action_r_regs[`ACTION_R_STATUS][29] = action_r_regs[`ACTION_R_TRACK_0 + 13][0];
assign action_r_regs[`ACTION_R_STATUS][30] = action_r_regs[`ACTION_R_TRACK_0 + 14][0];
assign action_r_regs[`ACTION_R_STATUS][31] = action_r_regs[`ACTION_R_TRACK_15][0];
localparam DDR_AWLEN = 4; /* AXI write burst length on the DDR bus (substract 1 to get awlen) */
localparam DDR_ARLEN = 4; /* AXI read burst length on the DDR bus (substract 1 to get arlen) */
localparam ACTION_ID_MAX = 16;
localparam ACTION_ID_BITS = $clog2(ACTION_ID_MAX);
/* NVME Device STATEMACHINE */
enum { NVME_IDLE, NVME_WRITING, NVME_READING, NVME_COMPLETED } activity_state;
/* Verification helper */
enum { VERIFY_OK, VERIFY_ERROR } verify_state;
initial begin
// Complete reset driving ddr_aresetn
axi_ddr_reset();
// Small reset, just set our output to defined values
//axi_ddr_wreset();
//axi_ddr_rreset();
if (`CONFIG_DDR_READWRITE_TEST) begin
axi_ddr_test();
end
end
/* ACTION REGISTER READ STATEMACHINE */
enum { READ_IDLE, READ_DECODE, READ_BUFFER, READ_ACTION_REGS } read_state;
always @(posedge ACT_NVME_ACLK, negedge ACT_NVME_ARESETN)
begin
if (!ACT_NVME_ARESETN) begin
ACT_arready <= 1'b0;
ACT_araddr <= 'hx;
ACT_rdata <= 'hx; /* data to see if read might work ok */
ACT_rresp <= 2'hx;
ACT_rlast <= 1'b0;
ACT_rvalid <= 1'b0;
action_r_regs[`ACTION_R_STATUS] = 32'h0000fff0;
for (int i = `ACTION_R_TRACK_0; i < `ACTION_R_SQ_LEVEL; i++) begin
action_r_regs[i][31:16] <= 16'h0000;
action_r_regs[i][15:8] <= i;
action_r_regs[i][7:0] <= 8'h0;
end
for (int i = `ACTION_R_SQ_LEVEL; i < `ACTION_R_NUM_REGS; i++) begin
action_r_regs[i] <= 32'haabbcc00 + i;
end
read_state <= READ_IDLE;
end else begin
case (read_state)
READ_IDLE: begin /* Capture read address */
ACT_rvalid <= 1'b0; /* No data available yet */
ACT_arready <= 1'b1; /* Ready to accept next read address */
if (ACT_arready && ACT_NVME_AXI_arvalid) begin
ACT_araddr <= ACT_NVME_AXI_araddr;
ACT_arready <= 1'b0; /* address is not needed anymore */
read_state <= READ_DECODE;
end
end
READ_DECODE: begin
ACT_rresp <= 2'h0; /* read status is OK */
ACT_rdata <= action_r_regs[action_r_index]; /* provide data */
ACT_rvalid <= 1'b1; /* signal that data is valid */
ACT_rlast <= 1'b1; /* last transfer for the given address, no burst read yet */
/* Implement read-clear behavior */
if ((ACT_NVME_AXI_araddr >= `ACTION_R_TRACK_0) &&
(ACT_NVME_AXI_araddr <= `ACTION_R_TRACK_15) &&
(activity_state == NVME_COMPLETED)) begin
action_r_regs[action_r_index][31:30] <= 2'b11; /* Mark ACTION_TRACK_n debug */
action_r_regs[action_r_index][0] <= 0; /* Clear ACTION_TRACK_n[0] */
end
read_state <= READ_BUFFER;
end
READ_BUFFER: begin
if (ACT_rvalid && ACT_NVME_AXI_rready) begin
//ACT_rdata <= 32'hX; /* Mark invalid for debugging */
ACT_rvalid <= 1'b0;
ACT_rlast <= 1'b0;
read_state <= READ_IDLE;
end
end
default: begin
end
endcase
end
end
/* ACTION REGISTER WRITE STATEMACHINE */
enum { WRITE_IDLE, WRITE_DECODE, WRITE_BUFFER, WRITE_BURST } write_state;
logic start_nvme_operation;
always @(posedge ACT_NVME_ACLK, negedge ACT_NVME_ARESETN)
begin
if (!ACT_NVME_ARESETN) begin
ACT_awready <= 1'b0; /* Ready to accept next write address */
ACT_bvalid <= 1'b0; /* write not finished */
ACT_bresp <= 2'hx;
ACT_awaddr <= 'hx;
ACT_wdata <= 'hx;
ACT_wready <= 1'b0; /* must be 0 to indicate that we are not ready for data yet, must not let be undefined */
for (int i = 0; i < `ACTION_W_NUM_REGS; i++) begin
action_w_regs[i] <= 'd0;
end
write_state <= WRITE_IDLE;
end else begin
case (write_state)
WRITE_IDLE: begin /* Capture write address */
ACT_awready <= 1'b1;
ACT_wready <= 1'b0;
start_nvme_operation <= 0;
if (ACT_NVME_AXI_awvalid == 1 && ACT_NVME_AXI_awready == 1) begin
ACT_awaddr <= ACT_NVME_AXI_awaddr; // Save away the desired address
ACT_awready <= 1'b0; // Wait for data now, no addresses anymore
ACT_wready <= 1'b1; // Now we captured the address and can receive the data
//action_w_index = 0;
write_state <= WRITE_DECODE;
end
end
WRITE_DECODE: begin /* Capture write data */
if (ACT_NVME_AXI_wvalid == 1 && ACT_wready == 1) begin
/* Save away the data for the address AXI_awaddr */
/* Addresses are 0x0, 0x4, 0x8, 0xC, ... */
ACT_wdata <= ACT_NVME_AXI_wdata;
action_w_regs[ACT_awaddr[ACTION_W_BITS + 1: 2]] <= ACT_NVME_AXI_wdata;
if (ACT_NVME_AXI_awburst == 2'b01) begin
ACT_awaddr <= ACT_awaddr + 4;
write_state <= WRITE_BURST;
end else begin
write_state <= WRITE_BUFFER;
end
end
end
/* AXI Single Write */
WRITE_BUFFER: begin /* Check if command register was written and try to trigger actity based on that */
if ((ACT_NVME_AXI_wvalid == 1'b1) && (ACT_wready == 1'b1) && (ACT_bvalid == 1'b0)) begin
if (ACT_awaddr[ACTION_W_BITS + 1: 2] == `ACTION_W_COMMAND) begin
void' (nvme_operation());
end
end
ACT_bresp <= 2'h0;
ACT_bvalid <= 1'b1; /* Write transfer completed */
if (ACT_bvalid && ACT_NVME_AXI_bready) begin
ACT_bvalid <= 1'b0; /* Accept next write request */
write_state <= WRITE_IDLE;
end
end
/* AXI Burst Read */
WRITE_BURST: begin
ACT_wready <= 1'b1;
if ((ACT_NVME_AXI_wvalid == 1'b1) && (ACT_wready == 1'b1) && (ACT_bvalid == 1'b0)) begin
if (ACT_awaddr[ACTION_W_BITS + 1: 2] == `ACTION_W_COMMAND) begin
start_nvme_operation <= 1;
end
/* store register content */
action_w_regs[ACT_awaddr[ACTION_W_BITS + 1: 2]] <= ACT_NVME_AXI_wdata;
ACT_wdata <= ACT_NVME_AXI_wdata; /* Take write data every clock */
ACT_awaddr <= ACT_awaddr + 4;
end
/* We need to ack the last transfer with bvalid = 1 if wlast was set to 1,
when the partner has set bready, we can start all over again */
if (ACT_NVME_AXI_wvalid == 1'b1 && ACT_wready == 1'b1 && ACT_NVME_AXI_wlast == 1'b1) begin
ACT_bresp <= 2'b00;
ACT_bvalid <= 1'b1;
end
if (ACT_bvalid && ACT_NVME_AXI_bready) begin
if (start_nvme_operation) begin
void '(nvme_operation());
start_nvme_operation <= 0;
end
ACT_bvalid <= 1'b0;
write_state <= WRITE_IDLE;
end
end
endcase
end
end
function nvme_operation();
logic [63:0] ddr_addr;
logic [63:0] lba_addr;
logic [31:0] lba_num;
logic [63:0] axi_addr;
logic [`CMD_TYPE_BITS-1:0] cmd_type;
logic [`CMD_ACTION_ID_BITS-1:0] cmd_action_id;
//#1; /* Ensure that all required registers are latched */
assign cmd_type = action_w_regs[`ACTION_W_COMMAND][`CMD_TYPE_BITS-1:0];
assign cmd_action_id = action_w_regs[`ACTION_W_COMMAND][11:8];
assign ddr_addr = { action_w_regs[`ACTION_W_DPTR_HIGH], action_w_regs[`ACTION_W_DPTR_LOW] };
assign lba_addr = { action_w_regs[`ACTION_W_LBA_HIGH], action_w_regs[`ACTION_W_LBA_LOW] };
assign lba_num = action_w_regs[`ACTION_W_LBA_NUM] + 1;
$display("nvme_operation: ddr=%h lba=%h num=%h cmd_type=%h cmd_action_id=%h",
ddr_addr, lba_addr, lba_num, cmd_type, cmd_action_id);
if (cmd_type == `CMD_READ) begin
fork
nvme_cmd_read(ddr_addr, lba_addr, lba_num, cmd_action_id);
join_none
end
if (cmd_type == `CMD_WRITE) begin
fork
nvme_cmd_write(ddr_addr, lba_addr, lba_num, cmd_action_id);
join_none
end
return 0;
endfunction
task nvme_cmd_read(input logic [63:0] ddr_addr,
input logic [63:0] lba_addr,
input logic [31:0] lba_num,
input logic [`CMD_ACTION_ID_BITS-1:0] cmd_action_id);
logic [63:0] axi_addr;
logic [15:0] i, j;
logic [127:0] axi_data[512/16]; /* size of one LBA */
//int fd;
activity_state = NVME_READING;
if (action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] == 1) begin
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][1] = 1; /* error, results not read */
end
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][31:30] = 2'b00; /* Mark ACTION_TRACK_n debug */
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] = 0; /* Mark ACTION_TRACK_n busy */
verify_state = VERIFY_OK;
#1;
// read stuff: 128bit DDR access => 16 bytes
$display("nvme_read: ddr=%h lba=%h num=%h", ddr_addr, lba_addr, lba_num);
i = 0;
for (axi_addr = ddr_addr; axi_addr < ddr_addr + lba_num * 512; axi_addr += 16 * DDR_AWLEN) begin
/* Read a block once buffer is empty */
if (i == 0) begin
/* Circumvention for simulator problems we have seen. Xilinx change request was filed */
`ifdef SIM_XSIM
static logic [7:0] fname[128]; /* works only for xsim */
`else
static string fname; /* works for ncsim but not for xsim */
`endif
$sformat(fname, "SNAP_LBA_%h.bin", lba_addr);
$readmemh(fname, axi_data);
// FIXME Bug in xsim sformat, the fname version has problems, the fixed filename seems working OK.
// $readmemh("SNAP_LBA_0000000000000000.bin", axi_data);
lba_addr += 1;
end
/* FIXME ... well well not really generic regarding DDR_AWLEN ... HOWTO FIX THAT? */
axi_ddr_write(axi_addr, { axi_data[i], axi_data[i+1], axi_data[i+2],axi_data[i+3] });
$display(" write: axi_addr=%h axi_data=%h%h%h%h", axi_addr,
axi_data[i], axi_data[i+1], axi_data[i+2], axi_data[i+3]);
i = (i + DDR_AWLEN) % (512/16);
//#1;
end
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][31:30] = 2'b10; /* Mark ACTION_TRACK_n debug */
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] = 1; /* Mark ACTION_TRACK_n ready */
activity_state = NVME_COMPLETED;
#1;
endtask
task nvme_cmd_write(input logic [63:0] ddr_addr,
input logic [63:0] lba_addr,
input logic [31:0] lba_num,
input logic [`CMD_ACTION_ID_BITS-1:0] cmd_action_id);
logic [63:0] axi_addr;
logic [15:0] i, j;
logic [127:0] axi_rdata[DDR_ARLEN];
logic [127:0] axi_data[512/16]; /* size of one LBA */
activity_state = NVME_WRITING;
if (action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] == 1) begin
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][1] = 1; /* error, results not read */
end
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][31:30] = 2'b00; /* Mark ACTION_TRACK_n debug */
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] = 0; /* Mark ACTION_TRACK_n busy */
verify_state = VERIFY_OK; /* No real verification done here, but set to OK such that it looks nice */
#1;
// write stuff: 128bit DDR access => 16 bytes
i = 0;
$display("nvme_write: ddr=%h lba=%h num=%h", ddr_addr, lba_addr, lba_num);
for (axi_addr = ddr_addr; axi_addr < ddr_addr + lba_num * 512; axi_addr += 16 * DDR_ARLEN) begin
axi_ddr_read(axi_addr, axi_rdata);
for (j = 0; j < DDR_ARLEN; j++) begin
axi_data[i + j] = axi_rdata[j];
end
$display(" read: axi_addr=%h axi_data=%h%h%h%h", axi_addr,
axi_data[i], axi_data[i+1], axi_data[i+2], axi_data[i+3]);
i = (i + DDR_ARLEN) % (512/16);
/* Write a block once buffer is full */
if (i == 0) begin
static string fname;
$sformat(fname, "SNAP_LBA_%h.bin", lba_addr);
$display("Writing %s\n", fname);
$writememh(fname, axi_data);
lba_addr += 1;
end
//#1;
end
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][31:30] = 2'b01; /* Mark ACTION_TRACK_n debug */
action_r_regs[`ACTION_R_TRACK_0 + cmd_action_id][0] = 1; /* Mark ACTION_TRACK_n ready */
activity_state = NVME_COMPLETED;
#1;
endtask
/* AXI RAM Clock */
always begin : AXI_DDR_CLOCK
#1 DDR_aclk = 0;
#1 DDR_aclk = 1;
end
enum { DDR_WIDLE, DDR_WRESET, DDR_WADDR, DDR_WDATA, DDR_WACK, DDR_WERROR } ddr_write_state;
enum { DDR_RIDLE, DDR_RRESET, DDR_RADDR, DDR_RDATA, DDR_RERROR } ddr_read_state;
task axi_ddr_reset();
DDR_aclk = 0;
DDR_aresetn = 0;
ddr_write_state = DDR_WRESET;
ddr_read_state = DDR_RRESET;
#5;
DDR_aresetn = 1;
#1;
endtask
// Test AXI DDR access
// NOTE Development only, did not execute that once it started working in the
// larger context. Try out yourself or throw away if it is not useful.
task axi_ddr_test();
int i;
logic [`DDR_M_ADDRBWIDTH-1:0] axi_addr;
logic [127:0] axi_data[DDR_AWLEN];
logic [127:0] cmp_data[DDR_AWLEN];
// AXI Memory Transfers
/* axi_ddr_reset(); */
for (axi_addr = 0; axi_addr < 4 * 1024; axi_addr += 16 * DDR_AWLEN) begin
for (i = 0; i < DDR_AWLEN; i++) begin
axi_data[i] = 128'h0011223344556677_8899aa00000000 + axi_addr + i;
$display("write: axi_addr=%h axi_data=%h", axi_addr + 16 * i, axi_data[i]);
end
axi_ddr_write(axi_addr, axi_data);
end
/* Read back the data and check for correctness. Result is visible in
ddr_state. */
for (axi_addr = 0; axi_addr < 4 * 1024; axi_addr += 16 * DDR_AWLEN) begin
for (i = 0; i < DDR_AWLEN; i++) begin
cmp_data[i] = 128'h0011223344556677_8899aa00000000 + axi_addr + i;
end
axi_ddr_read(axi_addr, axi_data);
if (axi_data != cmp_data) begin
ddr_read_state = DDR_RERROR;
end
$display("read: axi_addr=%h cmp_data=%h%h%h%h axi_data=%h%h%h%h", axi_addr,
cmp_data[i], cmp_data[i+1], cmp_data[i+2], cmp_data[i+3],
axi_data[i], axi_data[i+1], axi_data[i+2], axi_data[i+3]);
end
endtask
/* task or function, what is more appropriate? How to wait best for completion? */
logic [`DDR_M_ADDRBWIDTH-1:0] ddr_write_addr; /* FIXME need one per slot */
logic [7:0] ddr_widx; /* Index into ddr_write_data[] */
logic [127:0] ddr_write_data[DDR_AWLEN]; /* FIXME need one per slot */
/* task or function, what is more appropriate? How to wait best for completion? */
logic [`DDR_M_ADDRBWIDTH-1:0] ddr_read_addr; /* FIXME need one per slot */
logic [7:0] ddr_ridx; /* Index into ddr_read_data[] */
logic [127:0] ddr_read_data[DDR_ARLEN]; /* FIXME need one per slot */
task axi_ddr_write(input logic [`DDR_M_ADDRBWIDTH-1:0] addr, input logic [127:0] data[DDR_AWLEN]);
while (ddr_write_state != DDR_WIDLE) begin
#1;
end
ddr_write_addr = addr;
ddr_write_data = data;
ddr_write_state = DDR_WADDR;
#1;
while (ddr_write_state != DDR_WIDLE) begin
#1;
end
endtask
function axi_ddr_wreset();
DDR_awid <= 0;
DDR_awlen <= 0;
DDR_awsize <= 0;
DDR_wstrb <= 0;
DDR_awburst <= 0;
DDR_awvalid <= 0;
DDR_wstrb <= 0;
DDR_wlast <= 0;
DDR_wvalid <= 0;
DDR_bready <= 0; // 1: Master is ready
DDR_awlock <= 0;
DDR_awprot <= 0;
DDR_awqos <= 0;
DDR_awcache <= 0;
DDR_wuser <= 0;
DDR_awregion <= 0;
ddr_widx <= 0;
ddr_write_state <= DDR_WIDLE;
return 0;
endfunction
/* DDR WRITE Statemachine */
always @(posedge DDR_aclk, negedge ddr_aresetn) begin
if (!ddr_aresetn) begin
void' (axi_ddr_wreset());
end else begin
case (ddr_write_state)
DDR_WADDR: begin
DDR_awburst <= 2'b01; /* 00 FIXED, 01 INCR burst mode */
ddr_widx <= 0;
DDR_awlen <= DDR_AWLEN - 1;
DDR_awcache <= 4'b0011; /* allow merging / bufferable */
DDR_awprot <= 4'b0000; /* no protection bits */
DDR_awsize <= 3'b100; /* 16 bytes */
DDR_wstrb <= 16'hffff; /* all bytes enabled */
DDR_bready <= 1'b0;
DDR_wvalid <= 1'b0;
DDR_awaddr <= ddr_write_addr;
DDR_awvalid <= 1'b1; /* put address on bus */
if (DDR_M_AXI_awready && DDR_M_AXI_awvalid) begin /* address is on bus and slave saw it */
DDR_wdata <= ddr_write_data[ddr_widx]; /* put data on bus */
ddr_widx <= ddr_widx + 1;
DDR_wvalid <= 1'b1; /* and mark it valid */
DDR_awvalid <= 1'b0;
if (ddr_widx == DDR_AWLEN - 1) begin
DDR_wlast <= 1'b1;
end
ddr_write_state <= DDR_WDATA;
end
end
DDR_WDATA: begin
/* not the last one, put new data on the bus */
if (!DDR_wlast && DDR_M_AXI_wvalid && DDR_M_AXI_wready) begin
DDR_wdata <= ddr_write_data[ddr_widx]; /* put data on bus */
ddr_widx <= ddr_widx + 1;
DDR_wvalid <= 1'b1; /* and mark it valid */
if (ddr_widx == DDR_AWLEN - 1) begin
DDR_wlast <= 1'b1;
end
end
/* last one, end transfer and change back to WACK */
if (DDR_wlast && DDR_M_AXI_wvalid && DDR_M_AXI_wready) begin
DDR_wvalid <= 1'b0;
DDR_wlast <= 1'b0;
DDR_bready <= 1'b1; /* Ready to accept answer */
ddr_write_state <= DDR_WACK;
end
end
DDR_WACK: begin
if (DDR_M_AXI_bready && DDR_M_AXI_bvalid) begin
DDR_bready <= 1'b0;
ddr_write_state <= DDR_WIDLE;
end
end
default begin
end
endcase
end
end
task axi_ddr_read(input logic [`DDR_M_ADDRBWIDTH-1:0] addr, output logic [127:0] data[DDR_ARLEN]);
while (ddr_read_state != DDR_RIDLE) begin
#1;
end
ddr_read_addr = addr;
ddr_read_state = DDR_RADDR;
#1;
while (ddr_read_state != DDR_RIDLE) begin
#1;
end
data = ddr_read_data;
#1;
endtask
function axi_ddr_rreset();
DDR_arid <= 0;
DDR_arlock <= 0;
DDR_arlen <= 0;
DDR_arsize <= 0;
DDR_arburst <= 0;
DDR_arcache <= 0;
DDR_arvalid <= 0;
DDR_rready <= 0; // master is ready to receive data
DDR_rready <= 0;
DDR_arqos <= 0;
DDR_arregion <= 0;
ddr_ridx <= 0;
ddr_read_state <= DDR_RIDLE;
return 0;
endfunction
/* DDR READ Statemachine */
always @(posedge DDR_aclk, negedge ddr_aresetn) begin
if (!ddr_aresetn) begin
void' (axi_ddr_rreset());
end else begin
case (ddr_read_state)
DDR_RADDR: begin
DDR_arburst <= 2'b01; /* 00 FIXED, 01 INCR burst mode */
DDR_arlen <= DDR_ARLEN - 1;
ddr_ridx <= 0;
DDR_arcache <= 4'b0011; /* allow merging, bufferable */
DDR_arprot <= 4'b0000; /* no protection bits */
DDR_arsize <= 3'b100; /* 16 bytes */
DDR_araddr <= ddr_read_addr;
DDR_arvalid <= 1'b1; /* put read address on bus */
if (DDR_M_AXI_arready && DDR_arvalid) begin
DDR_arvalid <= 1'b0; /* no address required anymore */
DDR_rready <= 1'b1; /* ready to receive data */
ddr_read_state <= DDR_RDATA;
end
end
DDR_RDATA: begin
if (DDR_M_AXI_rvalid && DDR_rready) begin
ddr_read_data[ddr_ridx] <= DDR_M_AXI_rdata; /* get the data */
ddr_ridx <= ddr_ridx + 1;
if (DDR_M_AXI_rlast == 1'b1) begin
DDR_rready <= 1'b0; /* have all the data now */
ddr_read_state <= DDR_RIDLE;
end
end
end
default begin
end
endcase
end
end
endmodule |
module rvfi_bus_util_fifo_stage #(
parameter WIDTH = 8
) (
input clock,
input reset,
input in_valid,
output in_ready,
input [WIDTH-1:0] in_data,
output out_valid,
input out_ready,
output [WIDTH-1:0] out_data
);
reg [WIDTH-1:0] buffered;
reg buffer_valid;
wire in_txn = in_valid && in_ready;
wire out_txn = out_valid && out_ready;
assign out_data = buffer_valid ? buffered : in_data;
assign in_ready = out_ready || !buffer_valid;
assign out_valid = in_valid || buffer_valid;
always @(posedge clock) begin
if (reset) begin
buffer_valid <= 0;
end else begin
if (in_txn != out_txn)
buffer_valid <= in_txn;
end
if (in_txn)
buffered <= in_data;
end
endmodule |
module rvfi_bus_util_fifo #(
parameter WIDTH = 8,
parameter DEPTH = 3
) (
input clock,
input reset,
input in_valid,
output in_ready,
input [WIDTH-1:0] in_data,
output out_valid,
input out_ready,
output [WIDTH-1:0] out_data
);
wire [WIDTH-1:0] stage_data [0:DEPTH];
wire [DEPTH:0] stage_valid;
wire [DEPTH:0] stage_ready;
genvar i;
generate for (i = 0; i < DEPTH; i = i + 1) begin
rvfi_bus_util_fifo_stage #(.WIDTH(WIDTH)) stage (
.clock(clock),
.reset(reset),
.in_data(stage_data[i]),
.out_data(stage_data[i+1]),
.in_valid(stage_valid[i]),
.out_valid(stage_valid[i+1]),
.in_ready(stage_ready[i]),
.out_ready(stage_ready[i+1])
);
end endgenerate
assign stage_valid[0] = in_valid;
assign stage_data[0] = in_data;
assign in_ready = stage_ready[0];
assign out_valid = stage_valid[DEPTH];
assign stage_ready[DEPTH] = out_ready;
assign out_data = stage_data[DEPTH];
endmodule |
module testbench (
input clk
);
reg reset = 1;
always @(posedge clk)
reset <= 0;
(* keep *) wire iBus_cmd_valid;
(* keep *) wire [31:0] iBus_cmd_payload_pc;
(* keep *) `rvformal_rand_reg iBus_cmd_ready;
(* keep *) `rvformal_rand_reg iBus_rsp_ready;
(* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst;
(* keep *) wire dBus_cmd_valid;
(* keep *) wire dBus_cmd_payload_wr;
(* keep *) wire [31:0] dBus_cmd_payload_address;
(* keep *) wire [31:0] dBus_cmd_payload_data;
(* keep *) wire [1:0] dBus_cmd_payload_size;
(* keep *) `rvformal_rand_reg dBus_cmd_ready;
(* keep *) `rvformal_rand_reg dBus_rsp_ready;
(* keep *) `rvformal_rand_reg [31:0] dBus_rsp_data;
`RVFI_WIRES
(* keep *) wire [31:0] dmem_addr;
(* keep *) reg [31:0] dmem_data;
rvfi_dmem_check checker_inst (
.clock (clk ),
.reset (reset ),
.enable (1'b1 ),
.dmem_addr (dmem_addr),
`RVFI_CONN
);
(* keep *) reg dmem_last_valid;
(* keep *) wire [3:0] dBus_cmd_payload_mask;
assign dBus_cmd_payload_mask = ((1 << (1 << dBus_cmd_payload_size))-1) << dBus_cmd_payload_address[1:0];
always @(posedge clk) begin
if (reset) begin
dmem_last_valid <= 0;
end else begin
if(dmem_last_valid) begin
assume(dBus_rsp_data == dmem_data);
end
if(dBus_rsp_ready) begin
dmem_last_valid <= 0;
end
if(dBus_cmd_valid && dBus_cmd_ready) begin
if((dBus_cmd_payload_address >> 2) == (dmem_addr >> 2)) begin
if(!dBus_cmd_payload_wr) begin
dmem_last_valid <= 1;
end else begin
if (dBus_cmd_payload_mask[0]) dmem_data[ 7: 0] <= dBus_cmd_payload_data[ 7: 0];
if (dBus_cmd_payload_mask[1]) dmem_data[15: 8] <= dBus_cmd_payload_data[15: 8];
if (dBus_cmd_payload_mask[2]) dmem_data[23:16] <= dBus_cmd_payload_data[23:16];
if (dBus_cmd_payload_mask[3]) dmem_data[31:24] <= dBus_cmd_payload_data[31:24];
end
end
end
end
end
VexRiscv uut (
.clk (clk ),
.reset (reset ),
.iBus_cmd_valid (iBus_cmd_valid),
.iBus_cmd_ready (iBus_cmd_ready),
.iBus_cmd_payload_pc (iBus_cmd_payload_pc ),
.iBus_rsp_ready(iBus_rsp_ready),
.iBus_rsp_inst (iBus_rsp_inst),
.iBus_rsp_error(1'b0),
.dBus_cmd_valid(dBus_cmd_valid),
.dBus_cmd_payload_wr(dBus_cmd_payload_wr),
.dBus_cmd_payload_address(dBus_cmd_payload_address),
.dBus_cmd_payload_data(dBus_cmd_payload_data),
.dBus_cmd_payload_size(dBus_cmd_payload_size),
.dBus_cmd_ready(dBus_cmd_ready),
.dBus_rsp_ready(dBus_rsp_ready),
.dBus_rsp_data(dBus_rsp_data),
.dBus_rsp_error(1'b0),
`RVFI_CONN
);
endmodule |
module testbench (
input clk
);
reg reset = 1;
always @(posedge clk)
reset <= 0;
(* keep *) wire iBus_cmd_valid;
(* keep *) wire [31:0] iBus_cmd_payload_pc;
(* keep *) `rvformal_rand_reg iBus_cmd_ready;
(* keep *) `rvformal_rand_reg iBus_rsp_ready;
(* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst;
(* keep *) wire dBus_cmd_valid;
(* keep *) wire dBus_cmd_payload_wr;
(* keep *) wire [31:0] dBus_cmd_payload_address;
(* keep *) wire [31:0] dBus_cmd_payload_data;
(* keep *) wire [1:0] dBus_cmd_payload_size;
(* keep *) `rvformal_rand_reg dBus_cmd_ready;
(* keep *) `rvformal_rand_reg dBus_rsp_ready;
(* keep *) `rvformal_rand_reg [31:0] dBus_rsp_data;
`RVFI_WIRES
(* keep *) wire [31:0] imem_addr;
(* keep *) wire [15:0] imem_data;
rvfi_imem_check checker_inst (
.clock (clk ),
.reset (reset ),
.enable (1'b1 ),
.imem_addr (imem_addr),
.imem_data (imem_data),
`RVFI_CONN
);
(* keep *) wire imem_last_valid;
(* keep *) wire [31:0] imem_last_addr;
always @(posedge clk) begin
if (reset) begin
imem_last_valid <= 0;
end else begin
if(imem_last_valid) begin
if (imem_last_addr == imem_addr)
assume(iBus_rsp_inst[15:0] == imem_data);
if (imem_last_addr+2 == imem_addr)
assume(iBus_rsp_inst[31:16] == imem_data);
end
if(iBus_rsp_ready) begin
imem_last_valid <= 0;
end
if(iBus_cmd_valid && iBus_cmd_ready) begin
imem_last_valid <= 1;
imem_last_addr <= iBus_cmd_payload_pc;
end
end
end
VexRiscv uut (
.clk (clk ),
.reset (reset ),
.iBus_cmd_valid (iBus_cmd_valid),
.iBus_cmd_ready (iBus_cmd_ready),
.iBus_cmd_payload_pc (iBus_cmd_payload_pc ),
.iBus_rsp_ready(iBus_rsp_ready),
.iBus_rsp_inst (iBus_rsp_inst),
.iBus_rsp_error(1'b0),
.dBus_cmd_valid(dBus_cmd_valid),
.dBus_cmd_payload_wr(dBus_cmd_payload_wr),
.dBus_cmd_payload_address(dBus_cmd_payload_address),
.dBus_cmd_payload_data(dBus_cmd_payload_data),
.dBus_cmd_payload_size(dBus_cmd_payload_size),
.dBus_cmd_ready(dBus_cmd_ready),
.dBus_rsp_ready(dBus_rsp_ready),
.dBus_rsp_data(dBus_rsp_data),
.dBus_rsp_error(1'b0),
`RVFI_CONN
);
endmodule |
module SB_RAM40_4K (
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
// MODE 0: 256 x 16
// MODE 1: 512 x 8
// MODE 2: 1024 x 4
// MODE 3: 2048 x 2
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
`ifndef BLACKBOX
wire [15:0] WMASK_I;
wire [15:0] RMASK_I;
reg [15:0] RDATA_I;
wire [15:0] WDATA_I;
generate
case (WRITE_MODE)
0: assign WMASK_I = MASK;
1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
endcase
case (READ_MODE)
0: assign RMASK_I = 16'b 0000_0000_0000_0000;
1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
endcase
case (WRITE_MODE)
0: assign WDATA_I = WDATA;
1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
WDATA[11], WDATA[11], WDATA[11], WDATA[11],
WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
endcase
case (READ_MODE)
0: assign RDATA = RDATA_I;
1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
endcase
endgenerate
integer i;
reg [15:0] memory [0:255];
initial begin
for (i=0; i<16; i=i+1) begin
memory[ 0*16 + i] <= INIT_0[16*i +: 16];
memory[ 1*16 + i] <= INIT_1[16*i +: 16];
memory[ 2*16 + i] <= INIT_2[16*i +: 16];
memory[ 3*16 + i] <= INIT_3[16*i +: 16];
memory[ 4*16 + i] <= INIT_4[16*i +: 16];
memory[ 5*16 + i] <= INIT_5[16*i +: 16];
memory[ 6*16 + i] <= INIT_6[16*i +: 16];
memory[ 7*16 + i] <= INIT_7[16*i +: 16];
memory[ 8*16 + i] <= INIT_8[16*i +: 16];
memory[ 9*16 + i] <= INIT_9[16*i +: 16];
memory[10*16 + i] <= INIT_A[16*i +: 16];
memory[11*16 + i] <= INIT_B[16*i +: 16];
memory[12*16 + i] <= INIT_C[16*i +: 16];
memory[13*16 + i] <= INIT_D[16*i +: 16];
memory[14*16 + i] <= INIT_E[16*i +: 16];
memory[15*16 + i] <= INIT_F[16*i +: 16];
end
end
always @(posedge WCLK) begin
if (WE && WCLKE) begin
if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
end
end
always @(posedge RCLK) begin
if (RE && RCLKE) begin
RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
end
end
`endif
endmodule |
module SB_RAM40_4KNR (
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F )
) RAM (
.RDATA(RDATA),
.RCLK (~RCLKN),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (WCLK ),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
endmodule |
module nervsoc (
input clock,
input reset,
output reg [31:0] leds
);
reg [31:0] imem [0:1023];
reg [31:0] dmem [0:1023];
wire stall = 0;
wire trap;
wire [31:0] imem_addr;
reg [31:0] imem_data;
wire dmem_valid;
wire [31:0] dmem_addr;
wire [3:0] dmem_wstrb;
wire [31:0] dmem_wdata;
reg [31:0] dmem_rdata;
initial begin
$readmemh("firmware.hex", imem);
end
always @(posedge clock)
imem_data <= imem[imem_addr[31:2]];
always @(posedge clock) begin
if (dmem_valid) begin
if (dmem_addr == 32'h 0100_0000) begin
if (dmem_wstrb[0]) leds[ 7: 0] <= dmem_wdata[ 7: 0];
if (dmem_wstrb[1]) leds[15: 8] <= dmem_wdata[15: 8];
if (dmem_wstrb[2]) leds[23:16] <= dmem_wdata[23:16];
if (dmem_wstrb[3]) leds[31:24] <= dmem_wdata[31:24];
end else begin
if (dmem_wstrb[0]) dmem[dmem_addr[31:2]][ 7: 0] <= dmem_wdata[ 7: 0];
if (dmem_wstrb[1]) dmem[dmem_addr[31:2]][15: 8] <= dmem_wdata[15: 8];
if (dmem_wstrb[2]) dmem[dmem_addr[31:2]][23:16] <= dmem_wdata[23:16];
if (dmem_wstrb[3]) dmem[dmem_addr[31:2]][31:24] <= dmem_wdata[31:24];
end
dmem_rdata <= dmem[dmem_addr[31:2]];
end
end
nerv cpu (
.clock (clock ),
.reset (reset ),
.stall (stall ),
.trap (trap ),
.imem_addr (imem_addr ),
.imem_data (imem_data ),
.dmem_valid(dmem_valid),
.dmem_addr (dmem_addr ),
.dmem_wstrb(dmem_wstrb),
.dmem_wdata(dmem_wdata),
.dmem_rdata(dmem_rdata)
);
endmodule |
module testbench;
localparam MEM_ADDR_WIDTH = 16;
localparam TIMEOUT = (1<<10);
reg clock;
reg reset = 1'b1;
reg stall = 1'b0;
wire trap;
wire [31:0] imem_addr;
reg [31:0] imem_data;
wire dmem_valid;
wire [31:0] dmem_addr;
wire [ 3:0] dmem_wstrb;
wire [31:0] dmem_wdata;
reg [31:0] dmem_rdata;
reg [31:0] irq = 'b0;
always #5 clock = clock === 1'b0;
always @(posedge clock) reset <= 0;
reg [7:0] mem [0:(1<<MEM_ADDR_WIDTH)-1];
wire wr_in_mem_range = (dmem_addr[31:2] < (1<<MEM_ADDR_WIDTH));
wire wr_in_output = (dmem_addr == 32'h 02000000);
reg [31:0] out;
reg out_valid;
always @(posedge clock) begin
if (out_valid) begin
$write("%c", out[7:0]);
`ifndef VERILATOR
$fflush();
`endif
end
end
`ifdef STALL
always @(posedge clock) begin
stall <= $random;
end
`endif
always @(posedge clock) begin
if (imem_addr >= (1<<MEM_ADDR_WIDTH)) begin
$display("Memory access out of range: imem_addr = 0x%08x", imem_addr);
end
if (dmem_valid && !(wr_in_mem_range || wr_in_output)) begin
$display("Memory access out of range: dmem_addr = 0x%08x", dmem_addr);
end
end
integer i;
always @(posedge clock) begin
out <= 32'h 0;
out_valid <= 1'b0;
if (!stall && !reset) begin
imem_data <= {
mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b11}],
mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b10}],
mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b01}],
mem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b00}]
};
if (dmem_valid) begin
dmem_rdata <= {
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b11}],
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b10}],
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b01}],
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b00}]
};
for (i=0;i<4;i=i+1) begin
if (dmem_wstrb[i]) begin
if (wr_in_mem_range) begin
mem[{dmem_addr[MEM_ADDR_WIDTH-1:2], i[1:0]}] <= dmem_wdata[(i*8)+: 8];
end
if (wr_in_output) begin
out[(i*8)+: 8] <= dmem_wdata[(i*8)+: 8];
out_valid <= 1'b1;
end
dmem_rdata <= 'hx;
end
end
end else begin
dmem_rdata <= 32'h XXXX_XXXX;
end
end
end
initial begin
$readmemh("firmware.hex", mem);
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
end
nerv dut (
.clock(clock),
.reset(reset),
.stall(stall),
.trap(trap),
.imem_addr(imem_addr),
.imem_data(stall ? 32'bx : imem_data),
.dmem_valid(dmem_valid),
.dmem_addr(dmem_addr),
.dmem_wstrb(dmem_wstrb),
.dmem_wdata(dmem_wdata),
.dmem_rdata(stall ? 32'bx : dmem_rdata),
`ifdef NERV_FAULT
.imem_fault(1'b0),
.dmem_fault(1'b0),
`endif
.irq(irq)
);
reg [31:0] cycles = 0;
always @(posedge clock) begin
cycles <= cycles + 32'h1;
if (trap || (cycles >= TIMEOUT)) begin
$display("Simulated %0d cycles", cycles);
$finish;
end
end
endmodule |
module testbench;
localparam TIMEOUT = (1<<10);
reg clock;
wire LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5;
always #5 clock = clock === 1'b0;
top dut (
.CLK(clock),
.LEDR_N(LEDR_N),
.LEDG_N(LEDG_N),
.LED1(LED1),
.LED2(LED2),
.LED3(LED3),
.LED4(LED4),
.LED5(LED5)
);
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
end
reg [31:0] cycles = 0;
always @(posedge clock) begin
cycles <= cycles + 32'h1;
if (cycles >= TIMEOUT) begin
$display("Simulated %0d cycles", cycles);
$finish;
end
end
endmodule |
module emib_ch (
inout s_aib95,
inout aib95,
inout s_aib94,
inout aib94,
inout s_aib93,
inout aib93,
inout s_aib92,
inout aib92,
inout s_aib91,
inout aib91,
inout s_aib90,
inout aib90,
inout s_aib89,
inout aib89,
inout s_aib88,
inout aib88,
inout s_aib87,
inout aib87,
inout s_aib86,
inout aib86,
inout s_aib85,
inout aib85,
inout s_aib84,
inout aib84,
inout s_aib83,
inout aib83,
inout s_aib82,
inout aib82,
inout s_aib81,
inout aib81,
inout s_aib80,
inout aib80,
inout s_aib79,
inout aib79,
inout s_aib78,
inout aib78,
inout s_aib77,
inout aib77,
inout s_aib76,
inout aib76,
inout s_aib75,
inout aib75,
inout s_aib74,
inout aib74,
inout s_aib73,
inout aib73,
inout s_aib72,
inout aib72,
inout s_aib71,
inout aib71,
inout s_aib70,
inout aib70,
inout s_aib69,
inout aib69,
inout s_aib68,
inout aib68,
inout s_aib67,
inout aib67,
inout s_aib66,
inout aib66,
inout s_aib65,
inout aib65,
inout s_aib64,
inout aib64,
inout s_aib63,
inout aib63,
inout s_aib62,
inout aib62,
inout s_aib61,
inout aib61,
inout s_aib60,
inout aib60,
inout s_aib59,
inout aib59,
inout s_aib58,
inout aib58,
inout s_aib57,
inout aib57,
inout s_aib56,
inout aib56,
inout s_aib55,
inout aib55,
inout s_aib54,
inout aib54,
inout s_aib53,
inout aib53,
inout s_aib52,
inout aib52,
inout s_aib51,
inout aib51,
inout s_aib50,
inout aib50,
inout s_aib49,
inout aib49,
inout s_aib48,
inout aib48,
inout s_aib47,
inout aib47,
inout s_aib46,
inout aib46,
inout s_aib45,
inout aib45,
inout s_aib44,
inout aib44,
inout s_aib43,
inout aib43,
inout s_aib42,
inout aib42,
inout s_aib41,
inout aib41,
inout s_aib40,
inout aib40,
inout s_aib39,
inout aib39,
inout s_aib38,
inout aib38,
inout s_aib37,
inout aib37,
inout s_aib36,
inout aib36,
inout s_aib35,
inout aib35,
inout s_aib34,
inout aib34,
inout s_aib33,
inout aib33,
inout s_aib32,
inout aib32,
inout s_aib31,
inout aib31,
inout s_aib30,
inout aib30,
inout s_aib29,
inout aib29,
inout s_aib28,
inout aib28,
inout s_aib27,
inout aib27,
inout s_aib26,
inout aib26,
inout s_aib25,
inout aib25,
inout s_aib24,
inout aib24,
inout s_aib23,
inout aib23,
inout s_aib22,
inout aib22,
inout s_aib21,
inout aib21,
inout s_aib20,
inout aib20,
inout s_aib19,
inout aib19,
inout s_aib18,
inout aib18,
inout s_aib17,
inout aib17,
inout s_aib16,
inout aib16,
inout s_aib15,
inout aib15,
inout s_aib14,
inout aib14,
inout s_aib13,
inout aib13,
inout s_aib12,
inout aib12,
inout s_aib11,
inout aib11,
inout s_aib10,
inout aib10,
inout s_aib9,
inout aib9,
inout s_aib8,
inout aib8,
inout s_aib7,
inout aib7,
inout s_aib6,
inout aib6,
inout s_aib5,
inout aib5,
inout s_aib4,
inout aib4,
inout s_aib3,
inout aib3,
inout s_aib2,
inout aib2,
inout s_aib1,
inout aib1,
inout s_aib0,
inout aib0
);
aliasv xaliasv95 (
.PLUS(s_aib95),
.MINUS(aib95)
);
aliasv xaliasv94 (
.PLUS(s_aib94),
.MINUS(aib94)
);
aliasv xaliasv93 (
.PLUS(s_aib93),
.MINUS(aib93)
);
aliasv xaliasv92 (
.PLUS(s_aib92),
.MINUS(aib92)
);
aliasv xaliasv91 (
.PLUS(s_aib91),
.MINUS(aib91)
);
aliasv xaliasv90 (
.PLUS(s_aib90),
.MINUS(aib90)
);
aliasv xaliasv89 (
.PLUS(s_aib89),
.MINUS(aib89)
);
aliasv xaliasv88 (
.PLUS(s_aib88),
.MINUS(aib88)
);
aliasv xaliasv87 (
.PLUS(s_aib87),
.MINUS(aib87)
);
aliasv xaliasv86 (
.PLUS(s_aib86),
.MINUS(aib86)
);
aliasv xaliasv85 (
.PLUS(s_aib85),
.MINUS(aib85)
);
aliasv xaliasv84 (
.PLUS(s_aib84),
.MINUS(aib84)
);
aliasv xaliasv83 (
.PLUS(s_aib83),
.MINUS(aib83)
);
aliasv xaliasv82 (
.PLUS(s_aib82),
.MINUS(aib82)
);
aliasv xaliasv81 (
.PLUS(s_aib81),
.MINUS(aib81)
);
aliasv xaliasv80 (
.PLUS(s_aib80),
.MINUS(aib80)
);
aliasv xaliasv79 (
.PLUS(s_aib79),
.MINUS(aib79)
);
aliasv xaliasv78 (
.PLUS(s_aib78),
.MINUS(aib78)
);
aliasv xaliasv77 (
.PLUS(s_aib77),
.MINUS(aib77)
);
aliasv xaliasv76 (
.PLUS(s_aib76),
.MINUS(aib76)
);
aliasv xaliasv75 (
.PLUS(s_aib75),
.MINUS(aib75)
);
aliasv xaliasv74 (
.PLUS(s_aib74),
.MINUS(aib74)
);
aliasv xaliasv73 (
.PLUS(s_aib73),
.MINUS(aib73)
);
aliasv xaliasv72 (
.PLUS(s_aib72),
.MINUS(aib72)
);
aliasv xaliasv71 (
.PLUS(s_aib71),
.MINUS(aib71)
);
aliasv xaliasv70 (
.PLUS(s_aib70),
.MINUS(aib70)
);
aliasv xaliasv69 (
.PLUS(s_aib69),
.MINUS(aib69)
);
aliasv xaliasv68 (
.PLUS(s_aib68),
.MINUS(aib68)
);
aliasv xaliasv67 (
.PLUS(s_aib67),
.MINUS(aib67)
);
aliasv xaliasv66 (
.PLUS(s_aib66),
.MINUS(aib66)
);
aliasv xaliasv65 (
.PLUS(s_aib65),
.MINUS(aib65)
);
aliasv xaliasv64 (
.PLUS(s_aib64),
.MINUS(aib64)
);
aliasv xaliasv63 (
.PLUS(s_aib63),
.MINUS(aib63)
);
aliasv xaliasv62 (
.PLUS(s_aib62),
.MINUS(aib62)
);
aliasv xaliasv61 (
.PLUS(s_aib61),
.MINUS(aib61)
);
aliasv xaliasv60 (
.PLUS(s_aib60),
.MINUS(aib60)
);
aliasv xaliasv59 (
.PLUS(s_aib59),
.MINUS(aib59)
);
aliasv xaliasv58 (
.PLUS(s_aib58),
.MINUS(aib58)
);
aliasv xaliasv57 (
.PLUS(s_aib57),
.MINUS(aib57)
);
aliasv xaliasv56 (
.PLUS(s_aib56),
.MINUS(aib56)
);
aliasv xaliasv55 (
.PLUS(s_aib55),
.MINUS(aib55)
);
aliasv xaliasv54 (
.PLUS(s_aib54),
.MINUS(aib54)
);
aliasv xaliasv53 (
.PLUS(s_aib53),
.MINUS(aib53)
);
aliasv xaliasv52 (
.PLUS(s_aib52),
.MINUS(aib52)
);
aliasv xaliasv51 (
.PLUS(s_aib51),
.MINUS(aib51)
);
aliasv xaliasv50 (
.PLUS(s_aib50),
.MINUS(aib50)
);
aliasv xaliasv49 (
.PLUS(s_aib49),
.MINUS(aib49)
);
aliasv xaliasv48 (
.PLUS(s_aib48),
.MINUS(aib48)
);
aliasv xaliasv47 (
.PLUS(s_aib47),
.MINUS(aib47)
);
aliasv xaliasv46 (
.PLUS(s_aib46),
.MINUS(aib46)
);
aliasv xaliasv45 (
.PLUS(s_aib45),
.MINUS(aib45)
);
aliasv xaliasv44 (
.PLUS(s_aib44),
.MINUS(aib44)
);
aliasv xaliasv43 (
.PLUS(s_aib43),
.MINUS(aib43)
);
aliasv xaliasv42 (
.PLUS(s_aib42),
.MINUS(aib42)
);
aliasv xaliasv41 (
.PLUS(s_aib41),
.MINUS(aib41)
);
aliasv xaliasv40 (
.PLUS(s_aib40),
.MINUS(aib40)
);
aliasv xaliasv39 (
.PLUS(s_aib39),
.MINUS(aib39)
);
aliasv xaliasv38 (
.PLUS(s_aib38),
.MINUS(aib38)
);
aliasv xaliasv37 (
.PLUS(s_aib37),
.MINUS(aib37)
);
aliasv xaliasv36 (
.PLUS(s_aib36),
.MINUS(aib36)
);
aliasv xaliasv35 (
.PLUS(s_aib35),
.MINUS(aib35)
);
aliasv xaliasv34 (
.PLUS(s_aib34),
.MINUS(aib34)
);
aliasv xaliasv33 (
.PLUS(s_aib33),
.MINUS(aib33)
);
aliasv xaliasv32 (
.PLUS(s_aib32),
.MINUS(aib32)
);
aliasv xaliasv31 (
.PLUS(s_aib31),
.MINUS(aib31)
);
aliasv xaliasv30 (
.PLUS(s_aib30),
.MINUS(aib30)
);
aliasv xaliasv29 (
.PLUS(s_aib29),
.MINUS(aib29)
);
aliasv xaliasv28 (
.PLUS(s_aib28),
.MINUS(aib28)
);
aliasv xaliasv27 (
.PLUS(s_aib27),
.MINUS(aib27)
);
aliasv xaliasv26 (
.PLUS(s_aib26),
.MINUS(aib26)
);
aliasv xaliasv25 (
.PLUS(s_aib25),
.MINUS(aib25)
);
aliasv xaliasv24 (
.PLUS(s_aib24),
.MINUS(aib24)
);
aliasv xaliasv23 (
.PLUS(s_aib23),
.MINUS(aib23)
);
aliasv xaliasv22 (
.PLUS(s_aib22),
.MINUS(aib22)
);
aliasv xaliasv21 (
.PLUS(s_aib21),
.MINUS(aib21)
);
aliasv xaliasv20 (
.PLUS(s_aib20),
.MINUS(aib20)
);
aliasv xaliasv19 (
.PLUS(s_aib19),
.MINUS(aib19)
);
aliasv xaliasv18 (
.PLUS(s_aib18),
.MINUS(aib18)
);
aliasv xaliasv17 (
.PLUS(s_aib17),
.MINUS(aib17)
);
aliasv xaliasv16 (
.PLUS(s_aib16),
.MINUS(aib16)
);
aliasv xaliasv15 (
.PLUS(s_aib15),
.MINUS(aib15)
);
aliasv xaliasv14 (
.PLUS(s_aib14),
.MINUS(aib14)
);
aliasv xaliasv13 (
.PLUS(s_aib13),
.MINUS(aib13)
);
aliasv xaliasv12 (
.PLUS(s_aib12),
.MINUS(aib12)
);
aliasv xaliasv11 (
.PLUS(s_aib11),
.MINUS(aib11)
);
aliasv xaliasv10 (
.PLUS(s_aib10),
.MINUS(aib10)
);
aliasv xaliasv9 (
.PLUS(s_aib9),
.MINUS(aib9)
);
aliasv xaliasv8 (
.PLUS(s_aib8),
.MINUS(aib8)
);
aliasv xaliasv7 (
.PLUS(s_aib7),
.MINUS(aib7)
);
aliasv xaliasv6 (
.PLUS(s_aib6),
.MINUS(aib6)
);
aliasv xaliasv5 (
.PLUS(s_aib5),
.MINUS(aib5)
);
aliasv xaliasv4 (
.PLUS(s_aib4),
.MINUS(aib4)
);
aliasv xaliasv3 (
.PLUS(s_aib3),
.MINUS(aib3)
);
aliasv xaliasv2 (
.PLUS(s_aib2),
.MINUS(aib2)
);
aliasv xaliasv1 (
.PLUS(s_aib1),
.MINUS(aib1)
);
aliasv xaliasv0 (
.PLUS(s_aib0),
.MINUS(aib0)
);
endmodule |
module aliasv ( .PLUS(w), .MINUS(w) );
inout w;
wire w;
endmodule |
module aliasv_16 ( .PLUS(w), .MINUS(w) );
inout [15:0] w;
wire [15:0] w;
endmodule |
Subsets and Splits