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module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [96-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [96-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 55;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 82;
localparam PKT_DEST_ID_L = 80;
localparam PKT_PROTECTION_H = 86;
localparam PKT_PROTECTION_L = 84;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 58;
localparam PKT_TRANS_READ = 59;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [6-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 1 && read_transaction) begin
src_channel = 6'b01;
end
if (destid == 0 ) begin
src_channel = 6'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module aes_tb_top;
import uvm_pkg::*;
import aes_pkg::*;
//Interface declaration
aes_if vif();
/*
input [7:0] key_byte, state_byte,
input clk,rst,enable,
output reg [7:0] state_out_byte,
output reg load,ready
*/
//Connects the Interface to the DUT
AES_Encrypt aes(
.key_byte(vif.in_key_byte),
.state_byte(vif.in_state_byte),
.clk(vif.sig_clock),
.rst(vif.sig_rst),
.enable(vif.sig_enable),
.state_out_byte(vif.out_state_byte),
.load(vif.sig_load),
.ready(vif.sig_ready)
);
initial begin
//Registers the Interface in the configuration block so that other
//blocks can use it
uvm_resource_db#(virtual aes_if)::set
(.scope("ifs"), .name("aes_if"), .val(vif));
//Executes the test
run_test();
end
//Variable initialization
initial begin
vif.sig_clock <= 1'b1;
end
//Clock generation
always
#5 vif.sig_clock = ~vif.sig_clock;
endmodule |
module tone_mapping
#(
parameter W = 10
)
(
input wire clk,
input wire reset_n,
input wire sop,
input wire eop,
input wire valid,
input wire [W-1: 0] data,
input wire [7:0] reg_parallax_corr,
output wire [W-3: 0] data_o
);
wire [W-1: 0] min;
wire [W-1: 0] max;
wire [W-1: 0] max_min_diff;
reg [W-1: 0] data_min_diff;
reg [(W-1)*2:0] data_min_diff_mult;
//reg [W-3: 0] data_min_div;
min_max_detector
#(
.W ( W )
)
min_max_detector_inst
(
.clk ( clk ),
.reset_n ( reset_n ),
.sop ( sop ),
.eop ( eop ),
.valid ( valid ),
.data ( data ),
.min ( min ),
.max ( max ),
.max_min_diff ( max_min_diff ),
.reg_parallax_corr (reg_parallax_corr)
);
always @( posedge clk )
begin
data_min_diff <= data - min;
data_min_diff_mult <= data_min_diff*255;
end
tone_mapping_divider tone_mapping_divider_inst
(
.clock ( clk ),
.denom ( max_min_diff ),
.numer ( data_min_diff_mult ),
.quotient ( data_o ),
.remain ( )
);
endmodule |
module parallax_fix
(
input wire clk,
input wire reset_n,
input wire [7 : 0] parallax_corr,
input wire [ 7: 0] raw_data_0,
input wire [ 7: 0] raw_data_1,
input wire raw_data_valid,
input wire raw_data_sop,
input wire raw_data_eop,
output wire [ 7: 0] prlx_fxd_data_0,
output wire [ 7: 0] prlx_fxd_data_1,
output reg prlx_fxd_data_valid,
output reg prlx_fxd_data_sop,
output reg prlx_fxd_data_eop
);
reg [11: 0] cnt_wr;
reg [11: 0] cnt_rd;
wire wr_0;
wire rd_0;
wire wr_1;
wire rd_1;
wire [7 :0] q_0;
wire [7 :0] q_1;
wire w_prlx_fxd_data_valid;
wire w_prlx_fxd_data_sop;
wire w_prlx_fxd_data_eop;
always @( posedge clk or negedge reset_n )
if ( !reset_n )
cnt_wr <= 12'h0;
else
if ( raw_data_valid )
cnt_wr <= cnt_wr + 1'h1;
else
cnt_wr <= 12'h0;
always @( posedge clk or negedge reset_n )
if ( !reset_n )
cnt_rd <= 12'h0;
else
if ( cnt_rd == 12'd1280 )
cnt_rd <= 12'h0;
else if ( cnt_wr == parallax_corr )
cnt_rd <= 1'h1;
else if ( cnt_rd != 12'h0 )
cnt_rd <= cnt_rd + 1'h1;
assign wr_1 = raw_data_valid && ( cnt_wr < (1280-parallax_corr) );
assign wr_0 = raw_data_valid && ( cnt_wr >= parallax_corr );
assign rd_0 = ( cnt_rd > 0 ) ? 1'h1: 1'h0;
fifo_parallax_fix fifo_parallax_fix_0
(
.clock ( clk ),
.data ( raw_data_0 ),
.rdreq ( rd_0 ),
.wrreq ( wr_0 ),
.empty (),
.full (),
.q ( q_0 ),
.usedw ()
);
fifo_parallax_fix fifo_parallax_fix_1
(
.clock ( clk ),
.data ( raw_data_1 ),
.rdreq ( rd_0 ),
.wrreq ( wr_1 ),
.empty (),
.full (),
.q ( q_1 ),
.usedw ()
);
assign prlx_fxd_data_0 = ( cnt_rd < (1280-parallax_corr) ) ? q_0 : 7'h1;
assign prlx_fxd_data_1 = ( cnt_rd < (1280-parallax_corr) ) ? q_1 : 7'h1;
assign w_prlx_fxd_data_valid = ( cnt_rd > 12'h0 ) ? 1'h1 : 7'h0;
assign w_prlx_fxd_data_sop = ( cnt_rd == 12'h1 ) ? 1'h1 : 7'h0;
assign w_prlx_fxd_data_eop = ( cnt_rd == 12'd1280 ) ? 1'h1 : 7'h0;
always @( posedge clk )
begin
prlx_fxd_data_valid <= w_prlx_fxd_data_valid ;
prlx_fxd_data_sop <= w_prlx_fxd_data_sop ;
prlx_fxd_data_eop <= w_prlx_fxd_data_eop ;
end
/*
assign prlx_fxd_data_valid
assign prlx_fxd_data_sop
assign prlx_fxd_data_eop*/
endmodule |
module gamma_correction
(
input wire clk,
input wire reset_n,
input wire [ 7: 0] raw_data_0,
input wire [ 7: 0] raw_data_1,
input wire raw_data_valid,
input wire raw_data_sop,
input wire raw_data_eop,
output wire [ 7: 0] addr_0,
input wire [ 7: 0] data_0,
output wire [ 7: 0] addr_1,
input wire [ 7: 0] data_1,
output wire [ 7: 0] gamma_data_0,
output wire [ 7: 0] gamma_data_1,
output wire gamma_data_valid,
output wire gamma_data_sop,
output wire gamma_data_eop
);
assign addr_0 = raw_data_0;
assign addr_1 = raw_data_1;
assign gamma_data_0 = data_0;
assign gamma_data_1 = data_1;
delay_rg
#(
.W ( 3 ),
.D ( 1 )
)
delay_strobes
(
.clk ( clk ),
.data_in ( { raw_data_sop, raw_data_eop, raw_data_valid } ),
.data_out ( { gamma_data_sop, gamma_data_eop, gamma_data_valid } )
);
endmodule |
module wrp_HDR_algorithm
#(
parameter DATA_WIDTH = 32
)
(
//clocks & reset
input wire clk,
//
input wire asi_snk_0_valid_i,
input wire [DATA_WIDTH-1: 0] asi_snk_0_data_r_i,
input wire [DATA_WIDTH-1: 0] asi_snk_0_data_g_i,
input wire [DATA_WIDTH-1: 0] asi_snk_0_data_b_i,
input wire asi_snk_0_startofpacket_i,
input wire asi_snk_0_endofpacket_i,
input wire [DATA_WIDTH-1: 0] asi_snk_1_data_r_i,
input wire [DATA_WIDTH-1: 0] asi_snk_1_data_g_i,
input wire [DATA_WIDTH-1: 0] asi_snk_1_data_b_i,
output logic aso_src_valid_o,
output logic [DATA_WIDTH+1: 0] aso_src_data_r_o,
output logic [DATA_WIDTH+1: 0] aso_src_data_g_o,
output logic [DATA_WIDTH+1: 0] aso_src_data_b_o,
output logic aso_src_startofpacket_o,
output logic aso_src_endofpacket_o
);
//
HDR_algorithm
#(
.DATA_WIDTH ( DATA_WIDTH )
)
HDR_algorithm_r
(
.clk ( clk ),
.data_i0 ( asi_snk_0_data_r_i ),
.data_i1 ( asi_snk_1_data_r_i ),
.data_o ( aso_src_data_r_o )
);
HDR_algorithm
#(
.DATA_WIDTH ( DATA_WIDTH )
)
HDR_algorithm_g
(
.clk ( clk ),
.data_i0 ( asi_snk_0_data_g_i ),
.data_i1 ( asi_snk_1_data_g_i ),
.data_o ( aso_src_data_g_o )
);
HDR_algorithm
#(
.DATA_WIDTH ( DATA_WIDTH )
)
HDR_algorithm_b
(
.clk ( clk ),
.data_i0 ( asi_snk_0_data_b_i ),
.data_i1 ( asi_snk_1_data_b_i ),
.data_o ( aso_src_data_b_o )
);
delay_rg
#(
.W ( 3 ),
.D ( 21+2-8+5 )
)
delay_weight
(
.clk ( clk ),
.data_in ( {asi_snk_0_endofpacket_i, asi_snk_0_startofpacket_i, asi_snk_0_valid_i } ),
.data_out ( {aso_src_endofpacket_o, aso_src_startofpacket_o, aso_src_valid_o } )
);
endmodule |
module calc_weight_coef
#(
parameter DATA_WIDTH = 32
)
(
//clocks & reset
input wire clk,
// input wire reset_n,
//
input wire [DATA_WIDTH-1: 0] Z,
output wire [DATA_WIDTH-1: 0] weight_coef
);
localparam Zmin = 0;
localparam Zmax = 255;
localparam Zhalf_summ = (Zmax + Zmin)/2;
reg [DATA_WIDTH: 0] Zsumm;
reg [DATA_WIDTH-1: 0] weight_coef_tmp;
always @( posedge clk )
if ( Z <= Zhalf_summ )
weight_coef_tmp = Z - Zmin;
else
weight_coef_tmp = Zmax - Z;
assign weight_coef = ( weight_coef_tmp != 0 ) ? weight_coef_tmp : 1;
endmodule |
module wrp_tone_mapping
#(
parameter W = 10
)
(
input wire clk,
input wire reset_n,
input wire enable,
input wire sop_i,
input wire eop_i,
input wire valid_i,
input wire [W-1: 0] data_r_i,
input wire [W-1: 0] data_g_i,
input wire [W-1: 0] data_b_i,
input wire [7:0] reg_parallax_corr,
output reg [W-3: 0] data_r_o,
output reg [W-3: 0] data_g_o,
output reg [W-3: 0] data_b_o,
output reg sop_o,
output reg eop_o,
output reg valid_o
);
wire sop;
wire eop;
wire valid;
wire [W-3: 0] data_r;
wire [W-3: 0] data_g;
wire [W-3: 0] data_b;
tone_mapping
#(
.W ( W )
)
tone_mapping_r
(
.clk ( clk ),
.reset_n ( reset_n ),
.sop ( sop_i ),
.eop ( eop_i ),
.valid ( valid_i ),
.data ( data_r_i ),
.data_o ( data_r ),
.reg_parallax_corr ( reg_parallax_corr )
);
tone_mapping
#(
.W ( W )
)
tone_mapping_g
(
.clk ( clk ),
.reset_n ( reset_n ),
.sop ( sop_i ),
.eop ( eop_i ),
.valid ( valid_i ),
.data ( data_g_i ),
.data_o ( data_g ),
.reg_parallax_corr ( reg_parallax_corr )
);
tone_mapping
#(
.W ( W )
)
tone_mapping_b
(
.clk ( clk ),
.reset_n ( reset_n ),
.sop ( sop_i ),
.eop ( eop_i ),
.valid ( valid_i ),
.data ( data_b_i ),
.data_o ( data_b ),
.reg_parallax_corr ( reg_parallax_corr )
);
delay_rg
#(
.W ( 3 ),
.D ( 20 )
)
delay_strobes
(
.clk ( clk ),
.data_in ( { sop_i, eop_i, valid_i } ),
.data_out ( { sop, eop, valid } )
);
always @( posedge clk )
if ( enable )
begin
data_r_o <= data_r;
data_g_o <= data_g;
data_b_o <= data_b;
sop_o <= sop;
eop_o <= eop;
valid_o <= valid;
end
else
begin
data_r_o <= data_r_i[8:1];
data_g_o <= data_g_i[8:1];
data_b_o <= data_b_i[8:1];
sop_o <= sop_i;
eop_o <= eop_i;
valid_o <= valid_i ;
end
endmodule |
module HDR_algorithm
#(
parameter DATA_WIDTH = 32
)
(
//clocks & reset
input wire clk,
//
input wire [DATA_WIDTH-1: 0] data_i0,
input wire [DATA_WIDTH-1: 0] data_i1,
output reg [DATA_WIDTH+1: 0] data_o
);
//
wire [DATA_WIDTH-1: 0] weight_coef_0;
wire [DATA_WIDTH-1: 0] weight_coef_1;
reg [DATA_WIDTH: 0] weight_coef_sum;
wire [DATA_WIDTH: 0] weight_coef_sum_delay;
wire [DATA_WIDTH-1: 0] bright_delay_0;
wire [DATA_WIDTH-1: 0] bright_delay_1;
reg [(DATA_WIDTH*2): 0] mult_0;
reg [(DATA_WIDTH*2): 0] mult_1;
reg [(DATA_WIDTH*2)+1: 0] E;
wire [17: 0] quotient;
wire [ 8: 0] remain;
delay_rg
#(
.W ( DATA_WIDTH ),
.D ( 2 )
)
delay_rg_0
(
.clk ( clk ),
.data_in ( data_i0 ),
.data_out ( bright_delay_0)
);
delay_rg
#(
.W ( DATA_WIDTH ),
.D ( 2 )
)
delay_rg_1
(
.clk ( clk ),
.data_in ( data_i1 ),
.data_out ( bright_delay_1)
);
calc_weight_coef
#(
.DATA_WIDTH ( DATA_WIDTH )
)
calc_weight_coef_0
(
.clk ( clk ),
.Z ( data_i0 ),
.weight_coef ( weight_coef_0 )
);
calc_weight_coef
#(
.DATA_WIDTH ( DATA_WIDTH )
)
calc_weight_coef_1
(
.clk ( clk ),
.Z ( data_i1 ),
.weight_coef ( weight_coef_1 )
);
delay_rg
#(
.W ( DATA_WIDTH+1 ),
.D ( 2 )
)
delay_weight
(
.clk ( clk ),
.data_in ( weight_coef_sum ),
.data_out ( weight_coef_sum_delay )
);
always @( posedge clk )
weight_coef_sum <= weight_coef_0 + weight_coef_1;
always @( posedge clk )
begin
mult_0 <= weight_coef_sum*bright_delay_0;
mult_1 <= weight_coef_sum*bright_delay_1;
end
always @( posedge clk )
E = mult_0 + mult_1;
HDR_divider HDR_divider_inst
(
.clock ( clk ),
.denom ( weight_coef_sum_delay ),
.numer ( E ),
.quotient ( quotient ),
.remain ( remain )
);
always @( posedge clk )
if ( remain > 0 )
data_o <= quotient[9:0] + 1'h1;
else
data_o <= quotient[9:0];
endmodule |
module RGB2HSV
(
input wire clk,
input wire rst,
input wire [ 7: 0] r,
input wire [ 7: 0] g,
input wire [ 7: 0] b,
output reg [ 8: 0] H,
output wire [10: 0] S,
output wire [ 7: 0] V
);
localparam DIV_DELAY = 9;
//st0
reg [ 7: 0] max;
reg [ 7: 0] min;
reg [ 7: 0] st1_r;
reg [ 7: 0] st1_g;
reg [ 7: 0] st1_b;
reg [ 4: 0] chz;
wire[ 4: 0] chz_delay;
wire[ 7: 0] max_for_div;
//st1
reg [ 7: 0] max_min_sub_H;
reg signed [18: 0] sub_H;
wire signed [17: 0] div_min_max_S;
reg signed [18: 0] mult_2048_max_V;
wire [7 : 0] remain_S;
//st2
wire signed [17: 0] div_sub_maxmin_H;
wire [ 7: 0] remain_H;
reg [11: 0] sub_1_div_S;
//st3
reg [23: 0] mult60_H;
wire signed [8: 0] mult60_H_round_H;
//st4
// reg [8:0] H;
//st0
//поиск минимума и максимума
always @( posedge clk /*or posedge rst*/ )
if ( ( r >= g ) && ( r >= b ) )
max <= r;
else if ( ( g >= r ) && ( g >= b ) )
max <= g;
else if ( ( b >= r ) && ( b >= g ) )
max <= b;
always @( posedge clk /*or posedge rst*/ )
if ( ( r <= g ) && ( r <= b ) )
min <= r;
else if ( ( g <= r ) && ( g <= b ) )
min <= g;
else if ( ( b <= r ) && ( b <= g ) )
min <= b;
always @( posedge clk )
begin
st1_r <= r;
st1_g <= g;
st1_b <= b;
end
//st1
always @( posedge clk )
max_min_sub_H <= max - min;
always @( posedge clk )
if ( ( max == st1_r ) )
sub_H <= {st1_g,10'd0} - {st1_b,10'd0};
else if ( max == st1_g )
sub_H <= {st1_b,10'd0} - {st1_r,10'd0};
else if ( max == st1_b )
sub_H <= {st1_r,10'd0} - {st1_g,10'd0};
always @( posedge clk )
if ( min == max )
chz <= 5'b10000;
else if ( ( max == st1_r ) && ( st1_g >= st1_b ) )
chz <= 5'b01000;
else if( ( max == st1_r ) && ( st1_g < st1_b ) )
chz <= 5'b00100;
else if ( max == st1_g )
chz <= 5'b00010;
else if ( max == st1_b )
chz <= 5'b00001;
assign max_for_div = ( ( max == 0 ) ? 1 : max );
rgb2hsv_divider_S rgb2hsv_divider_S_inst
(
.clock ( clk ),
.denom ( max_for_div ),
.numer ( { min, 11'h0 } ),
.quotient ( div_min_max_S ),
.remain ( remain_S )
);
/*
always @( posedge clk )
mult_2048_max_V <= { max, 11'h0 };
*/
//st2
delay_rg
#(
.W ( 5 ),
.D ( 6+DIV_DELAY )
)
delay_rg_1
(
.clk ( clk ),
.data_in ( chz ),
.data_out ( chz_delay )
);
rgb2hsv_divider0 rgb2hsv_divider0_inst
(
.clock ( clk ),
.denom ( max_min_sub_H ),
.numer ( sub_H ),
.quotient ( div_sub_maxmin_H ),
.remain ( remain_H )
);
always @( posedge clk )
sub_1_div_S <= ( remain_S[7] == 1 ) ? ( 2047 - div_min_max_S[11:0] ) : ( 2048 - div_min_max_S[11:0] );
//st3
always @( posedge clk )
mult60_H <= ( remain_H[7] == 1 ) ? ( (div_sub_maxmin_H + 1) * 60 ) : ( div_sub_maxmin_H * 60);
rounder
#(
.BEFORE_ROUND ( 24 ),
.LOW_BIT ( 10 ),
.AFTER_ROUND ( 9 )
)
rounder_inst
(
.clk ( clk ),
.reset_b ( !rst ),
.data_in ( mult60_H ),
.data_out ( mult60_H_round_H )
);
//st4
always @( posedge clk )
case ( chz_delay )
5'b10000: H <= '0;
5'b01000: H <= mult60_H_round_H;
5'b00100: H <= mult60_H_round_H + 360;
5'b00010: H <= mult60_H_round_H + 120;
5'b00001: H <= mult60_H_round_H + 240;
default: H <= '0;
endcase
delay_rg
#(
.W ( 11 ),
.D ( 6 )
)
delay_rg_S
(
.clk ( clk ),
.data_in ( ( sub_1_div_S[11]?2047:sub_1_div_S[10:0] ) ),
.data_out ( S )
);
delay_rg
#(
.W ( 8 ),
.D ( 8 + DIV_DELAY )
)
delay_rg_V
(
.clk ( clk ),
.data_in ( max ),
.data_out ( V )
);
endmodule |
module jonpaolo02_async_fifo (
input [7:0] io_in,
output [7:0] io_out
);
async_fifo #(.WIDTH(3), .DEPTH(8)) top
(.rst(io_in[2]),
.wclk(io_in[0]), .we(io_in[3]),
.full(io_out[3]),
.wdata(io_in[7:5]),
.rclk(io_in[1]), .re(io_in[4]),
.empty(io_out[4]),
.rdata(io_out[7:5]));
endmodule |
module lms_ctr_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [95-1 : 0] sink0_data,
input [11-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [95-1 : 0] src_data,
output [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 95 + 11 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam PKT_TRANS_LOCK = 57;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module lms_ctr_mm_interconnect_0_cmd_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [95-1 : 0] sink_data, // ST_DATA_W=95
input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [95-1 : 0] src0_data, // ST_DATA_W=95
output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [95-1 : 0] src1_data, // ST_DATA_W=95
output reg [11-1 : 0] src1_channel, // ST_CHANNEL_W=11
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [95-1 : 0] src2_data, // ST_DATA_W=95
output reg [11-1 : 0] src2_channel, // ST_CHANNEL_W=11
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [95-1 : 0] src3_data, // ST_DATA_W=95
output reg [11-1 : 0] src3_channel, // ST_CHANNEL_W=11
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [95-1 : 0] src4_data, // ST_DATA_W=95
output reg [11-1 : 0] src4_channel, // ST_CHANNEL_W=11
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [95-1 : 0] src5_data, // ST_DATA_W=95
output reg [11-1 : 0] src5_channel, // ST_CHANNEL_W=11
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
output reg src6_valid,
output reg [95-1 : 0] src6_data, // ST_DATA_W=95
output reg [11-1 : 0] src6_channel, // ST_CHANNEL_W=11
output reg src6_startofpacket,
output reg src6_endofpacket,
input src6_ready,
output reg src7_valid,
output reg [95-1 : 0] src7_data, // ST_DATA_W=95
output reg [11-1 : 0] src7_channel, // ST_CHANNEL_W=11
output reg src7_startofpacket,
output reg src7_endofpacket,
input src7_ready,
output reg src8_valid,
output reg [95-1 : 0] src8_data, // ST_DATA_W=95
output reg [11-1 : 0] src8_channel, // ST_CHANNEL_W=11
output reg src8_startofpacket,
output reg src8_endofpacket,
input src8_ready,
output reg src9_valid,
output reg [95-1 : 0] src9_data, // ST_DATA_W=95
output reg [11-1 : 0] src9_channel, // ST_CHANNEL_W=11
output reg src9_startofpacket,
output reg src9_endofpacket,
input src9_ready,
output reg src10_valid,
output reg [95-1 : 0] src10_data, // ST_DATA_W=95
output reg [11-1 : 0] src10_channel, // ST_CHANNEL_W=11
output reg src10_startofpacket,
output reg src10_endofpacket,
input src10_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 11;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid;
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid;
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid;
src6_data = sink_data;
src6_startofpacket = sink_startofpacket;
src6_endofpacket = sink_endofpacket;
src6_channel = sink_channel >> NUM_OUTPUTS;
src6_valid = sink_channel[6] && sink_valid;
src7_data = sink_data;
src7_startofpacket = sink_startofpacket;
src7_endofpacket = sink_endofpacket;
src7_channel = sink_channel >> NUM_OUTPUTS;
src7_valid = sink_channel[7] && sink_valid;
src8_data = sink_data;
src8_startofpacket = sink_startofpacket;
src8_endofpacket = sink_endofpacket;
src8_channel = sink_channel >> NUM_OUTPUTS;
src8_valid = sink_channel[8] && sink_valid;
src9_data = sink_data;
src9_startofpacket = sink_startofpacket;
src9_endofpacket = sink_endofpacket;
src9_channel = sink_channel >> NUM_OUTPUTS;
src9_valid = sink_channel[9] && sink_valid;
src10_data = sink_data;
src10_startofpacket = sink_startofpacket;
src10_endofpacket = sink_endofpacket;
src10_channel = sink_channel >> NUM_OUTPUTS;
src10_valid = sink_channel[10] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign ready_vector[6] = src6_ready;
assign ready_vector[7] = src7_ready;
assign ready_vector[8] = src8_ready;
assign ready_vector[9] = src9_ready;
assign ready_vector[10] = src10_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule |
module lms_ctr_mm_interconnect_0_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 5
)
(output [81 - 78 : 0] default_destination_id,
output [11-1 : 0] default_wr_channel,
output [11-1 : 0] default_rd_channel,
output [11-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[81 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 11'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 11'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 11'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10000 - 64'h8000);
localparam PAD1 = log2ceil(64'h11000 - 64'h10800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h11000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [11-1 : 0] default_src_channel;
lms_ctr_mm_interconnect_0_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x8000 .. 0x10000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 17'h8000 ) begin
src_channel = 11'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x10800 .. 0x11000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 17'h10800 ) begin
src_channel = 11'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_router_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [11-1 : 0] default_src_channel;
lms_ctr_mm_interconnect_0_router_002_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 11'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [95-1 : 0] sink0_data,
input [11-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [95-1 : 0] sink1_data,
input [11-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [95-1 : 0] sink2_data,
input [11-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [95-1 : 0] sink3_data,
input [11-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [95-1 : 0] sink4_data,
input [11-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [95-1 : 0] sink5_data,
input [11-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
input sink6_valid,
input [95-1 : 0] sink6_data,
input [11-1: 0] sink6_channel,
input sink6_startofpacket,
input sink6_endofpacket,
output sink6_ready,
input sink7_valid,
input [95-1 : 0] sink7_data,
input [11-1: 0] sink7_channel,
input sink7_startofpacket,
input sink7_endofpacket,
output sink7_ready,
input sink8_valid,
input [95-1 : 0] sink8_data,
input [11-1: 0] sink8_channel,
input sink8_startofpacket,
input sink8_endofpacket,
output sink8_ready,
input sink9_valid,
input [95-1 : 0] sink9_data,
input [11-1: 0] sink9_channel,
input sink9_startofpacket,
input sink9_endofpacket,
output sink9_ready,
input sink10_valid,
input [95-1 : 0] sink10_data,
input [11-1: 0] sink10_channel,
input sink10_startofpacket,
input sink10_endofpacket,
output sink10_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [95-1 : 0] src_data,
output [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 95 + 11 + 2;
localparam NUM_INPUTS = 11;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam PKT_TRANS_LOCK = 57;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
wire [PAYLOAD_W - 1 : 0] sink6_payload;
wire [PAYLOAD_W - 1 : 0] sink7_payload;
wire [PAYLOAD_W - 1 : 0] sink8_payload;
wire [PAYLOAD_W - 1 : 0] sink9_payload;
wire [PAYLOAD_W - 1 : 0] sink10_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
assign valid[6] = sink6_valid;
assign valid[7] = sink7_valid;
assign valid[8] = sink8_valid;
assign valid[9] = sink9_valid;
assign valid[10] = sink10_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[57];
lock[1] = sink1_data[57];
lock[2] = sink2_data[57];
lock[3] = sink3_data[57];
lock[4] = sink4_data[57];
lock[5] = sink5_data[57];
lock[6] = sink6_data[57];
lock[7] = sink7_data[57];
lock[8] = sink8_data[57];
lock[9] = sink9_data[57];
lock[10] = sink10_data[57];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
// 6 | 1 | 0
// 7 | 1 | 0
// 8 | 1 | 0
// 9 | 1 | 0
// 10 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
share_6 & { SHARE_COUNTER_W {next_grant[6]} } |
share_7 & { SHARE_COUNTER_W {next_grant[7]} } |
share_8 & { SHARE_COUNTER_W {next_grant[8]} } |
share_9 & { SHARE_COUNTER_W {next_grant[9]} } |
share_10 & { SHARE_COUNTER_W {next_grant[10]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
wire final_packet_6 = 1'b1;
wire final_packet_7 = 1'b1;
wire final_packet_8 = 1'b1;
wire final_packet_9 = 1'b1;
wire final_packet_10 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_10,
final_packet_9,
final_packet_8,
final_packet_7,
final_packet_6,
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign sink6_ready = src_ready && grant[6];
assign sink7_ready = src_ready && grant[7];
assign sink8_ready = src_ready && grant[8];
assign sink9_ready = src_ready && grant[9];
assign sink10_ready = src_ready && grant[10];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} } |
sink6_payload & {PAYLOAD_W {grant[6]} } |
sink7_payload & {PAYLOAD_W {grant[7]} } |
sink8_payload & {PAYLOAD_W {grant[8]} } |
sink9_payload & {PAYLOAD_W {grant[9]} } |
sink10_payload & {PAYLOAD_W {grant[10]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign sink6_payload = {sink6_channel,sink6_data,
sink6_startofpacket,sink6_endofpacket};
assign sink7_payload = {sink7_channel,sink7_data,
sink7_startofpacket,sink7_endofpacket};
assign sink8_payload = {sink8_channel,sink8_data,
sink8_startofpacket,sink8_endofpacket};
assign sink9_payload = {sink9_channel,sink9_data,
sink9_startofpacket,sink9_endofpacket};
assign sink10_payload = {sink10_channel,sink10_data,
sink10_startofpacket,sink10_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module lms_ctr_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10000 - 64'h8000);
localparam PAD1 = log2ceil(64'h11000 - 64'h10800);
localparam PAD2 = log2ceil(64'h11020 - 64'h11000);
localparam PAD3 = log2ceil(64'h11040 - 64'h11020);
localparam PAD4 = log2ceil(64'h11060 - 64'h11040);
localparam PAD5 = log2ceil(64'h11080 - 64'h11060);
localparam PAD6 = log2ceil(64'h110a0 - 64'h11080);
localparam PAD7 = log2ceil(64'h110b0 - 64'h110a0);
localparam PAD8 = log2ceil(64'h110c0 - 64'h110b0);
localparam PAD9 = log2ceil(64'h110d0 - 64'h110c0);
localparam PAD10 = log2ceil(64'h110d8 - 64'h110d0);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h110d8;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [11-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x8000 .. 0x10000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 17'h8000 ) begin
src_channel = 11'b00000010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x10800 .. 0x11000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 17'h10800 ) begin
src_channel = 11'b00000001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x11000 .. 0x11020 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 17'h11000 ) begin
src_channel = 11'b10000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x11020 .. 0x11040 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 17'h11020 ) begin
src_channel = 11'b01000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
end
// ( 0x11040 .. 0x11060 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 17'h11040 ) begin
src_channel = 11'b00100000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
end
// ( 0x11060 .. 0x11080 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 17'h11060 ) begin
src_channel = 11'b00010000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x11080 .. 0x110a0 )
if ( {address[RG:PAD6],{PAD6{1'b0}}} == 17'h11080 ) begin
src_channel = 11'b00000000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x110a0 .. 0x110b0 )
if ( {address[RG:PAD7],{PAD7{1'b0}}} == 17'h110a0 ) begin
src_channel = 11'b00001000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x110b0 .. 0x110c0 )
if ( {address[RG:PAD8],{PAD8{1'b0}}} == 17'h110b0 && read_transaction ) begin
src_channel = 11'b00000100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
end
// ( 0x110c0 .. 0x110d0 )
if ( {address[RG:PAD9],{PAD9{1'b0}}} == 17'h110c0 ) begin
src_channel = 11'b00000000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x110d0 .. 0x110d8 )
if ( {address[RG:PAD10],{PAD10{1'b0}}} == 17'h110d0 && read_transaction ) begin
src_channel = 11'b00000000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [95-1 : 0] sink_data, // ST_DATA_W=95
input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [95-1 : 0] src0_data, // ST_DATA_W=95
output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{10{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module lms_ctr_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
input receiver2_irq,
input receiver3_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[0] = receiver0_irq;
sender_irq[1] = receiver1_irq;
sender_irq[2] = receiver2_irq;
sender_irq[3] = receiver3_irq;
end
endmodule |
module lms_ctr_mm_interconnect_0_router_005
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [11-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_005_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 11'b01;
end
if (destid == 1 && read_transaction) begin
src_channel = 11'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_router_004_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [79 - 77 : 0] default_destination_id,
output [8-1 : 0] default_wr_channel,
output [8-1 : 0] default_rd_channel,
output [8-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[79 - 77 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 8'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 8'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 8'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_004
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [93-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [93-1 : 0] src_data,
output reg [8-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 79;
localparam PKT_DEST_ID_L = 77;
localparam PKT_PROTECTION_H = 83;
localparam PKT_PROTECTION_L = 81;
localparam ST_DATA_W = 93;
localparam ST_CHANNEL_W = 8;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [8-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_004_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 8'b01;
end
if (destid == 1 && read_transaction) begin
src_channel = 8'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_rsp_mux_001
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [95-1 : 0] sink0_data,
input [11-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [95-1 : 0] sink1_data,
input [11-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [95-1 : 0] src_data,
output [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 95 + 11 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam PKT_TRANS_LOCK = 57;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[57];
lock[1] = sink1_data[57];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module sgen_nco_tb;
time CLK_PERIOD = 50.0;// 10kHz
reg i_rst_an;
reg i_ena;
reg i_clk;
reg s_clk;
reg [`P_PHASEACCU_WIDTH-1:0] i_fcw;
wire rdy;
wire signed [`P_ROM_WIDTH:0] o_sin_rtl,o_cos_rtl;
reg data_ready;
integer error_count=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_ROM_WIDTH:0] o_sin_mat, o_cos_mat;
// WRITE-OUT RTL RESPONSE FILE
reg [8*64:1] filename_rtl_oup;
integer fid_rtl_oup;
integer status_rtl_oup;
// RTL MATLAB TOLERANCE
integer diff, abs_diff;
// -------------------------------------------------------------------
initial
begin
i_rst_an = 1'b1;
#1 i_rst_an = 1'b0;
#(2*2*CLK_PERIOD+CLK_PERIOD-3) i_rst_an = 1'b1;
end
initial
begin
i_ena = 1'b0;
#(2*2*CLK_PERIOD+CLK_PERIOD-1) i_ena = 1'b1;
end
initial s_clk = 1'b0;
always s_clk = #(CLK_PERIOD) ~s_clk;
//initial s_clk = #5 i_clk;
assign #1 i_clk = s_clk;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of NCO.");
$display("### Testcase %d", `TESTCASE);
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge s_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_fcw);
else
i_fcw = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(posedge i_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d %d\n", o_sin_mat, o_cos_mat);
end
always @(negedge i_clk)
begin: ASSERT_RTL_vs_MATLAB
if (i_rst_an && i_ena)
diff = o_sin_rtl - o_sin_mat;
abs_diff = `ABS(diff);
if ( abs_diff > 1)
begin
$error("### RTL = %d, MAT = %d", o_sin_rtl, o_sin_mat); error_count<= error_count + 1;
end
end
`ifdef RTL
initial
begin: TEXTIO_WRITE_OUT
$sformat(filename_rtl_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_rtl.dat");
fid_rtl_oup = $fopen(filename_rtl_oup, "w");
@(posedge data_ready) $fclose(fid_rtl_oup);
end
always @(posedge i_clk)
begin: RTL_RESPONSE
$fwrite(fid_rtl_oup,"%d\n",o_sin_rtl);
end
`endif
sgen_nco #(
.gp_rom_width (`P_ROM_WIDTH),
.gp_rom_depth (`P_ROM_DEPTH),
.gp_phase_accu_width (`P_PHASEACCU_WIDTH)
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_fcw (i_fcw),
.o_sin (o_sin_rtl),
.o_cos (o_cos_rtl)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","sgen_nco_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,sgen_nco_tb);
end
`endif
endmodule |
module filt_fir_tb;
time CLK_PERIOD = 50;
reg i_rst_an;
reg i_ena;
reg i_clk;
reg [`P_INP_DATA_W-1:0] i_data;
wire rdy;
wire signed [`P_OUP_DATA_W-1:0] oup_data;
reg data_ready;
integer error_count=0;
integer nr_of_samples=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_DATA_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin
i_rst_an = 1'b1;
#170 i_rst_an = 1'b0;
#205 i_rst_an = 1'b1;
end
initial
begin
i_ena = 1'b0;
#410 i_ena = 1'b1;
end
initial i_clk = 1'b0;
always i_clk = #(CLK_PERIOD) ~i_clk;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of FIR Filter.");
$display("### Testcase %d", `TESTCASE);
//$write("### ");$system($sformatf("date"));
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED with %d samples", nr_of_samples);
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena) begin
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
nr_of_samples <= nr_of_samples + 1;
end
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(posedge i_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
end
always @(negedge i_clk)
begin
if (i_rst_an && i_ena)
if (oup_data != o_data_mat)
begin
$error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
end
end
filt_fir #(
.gp_inp_width (`P_INP_DATA_W),
.gp_coeff_length (`P_COEFF_L),
.gp_coeff_width (`P_COEFF_W),
.gp_tf_df (`P_TF_DF),
.gp_symm (`P_SYMM),
.gp_oup_width ()
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (oup_data)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_fir_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_fir_tb);
end
`endif
endmodule |
module filt_ppi_tb;
time CLK_PERIOD = 1000;
//time F_CLK_PERIOD = CLK_PERIOD/`P_INTERPOLATION;
reg i_rst_an;
reg i_ena=1'b0;
reg i_clk;
reg i_fclk;
reg f_clk=1'b0;
reg s_clk;
int r_cnt=`P_INTERPOLATION;
reg [1:0] r_start_chk='d0;
integer error_count=0;
reg data_ready=1'b0;
reg signed [`P_INP_DATA_W-1:0] i_data;
wire signed [`P_OUP_W-1:0] o_data_rtl;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_W-1:0] r_data_mat;
reg signed [`P_OUP_W-1:0] sr_data_mat [0:`P_INTERPOLATION];
reg signed [`P_OUP_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin: RST
i_rst_an = 1'b1;
#2 i_rst_an = 1'b0;
#(0.5*CLK_PERIOD) i_rst_an = 1'b1;
end
always @(posedge s_clk)
begin: EGU
if (i_rst_an)
i_ena = 1'b1;
end
always f_clk = #(CLK_PERIOD/(`P_INTERPOLATION*2)) ~f_clk;
always @(posedge f_clk)
begin: SCLK
if (r_cnt<`P_INTERPOLATION-1)
r_cnt <= r_cnt + 1;
else
r_cnt <= 'd0;
end
assign s_clk = (r_cnt<`P_INTERPOLATION/2) ? 1'b1 : 1'b0;
initial begin
fork
forever #2 i_fclk = f_clk;
forever #2 i_clk = s_clk;
join
end
always @(posedge i_clk)
begin: FLAG_START_CHK
if (r_start_chk < 3)
r_start_chk <= r_start_chk + 1;
end
integer error;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of Polyphase Interpolation FIR Filter.");
$display("### Testcase %d", `TESTCASE);
//$write("### ");$system($sformatf("date"));
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);$display("%s",filename_mat_oup);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(negedge i_fclk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
end
filt_ppi #(
.gp_idata_width (`P_INP_DATA_W ),
.gp_interpolation_factor (`P_INTERPOLATION),
.gp_coeff_length (`P_COEFF_L ),
.gp_coeff_width (`P_COEFF_W ),
.gp_tf_df (`P_TF_DF ),
.gp_comm_ccw (`P_COMM_CCW_CW ),
.gp_mul_ccw (`P_MUL_CCW_CW ),
.gp_comm_phase (`P_COMM_PHA ),
.gp_odata_width (`P_OUP_W )
) dut (
.i_rst_an (i_rst_an ),
.i_ena (i_ena ),
.i_clk (i_clk ),
.i_data (i_data ),
.i_fclk (i_fclk ),
.o_data (o_data_rtl),
.o_sclk ( )
);
always @(posedge i_fclk)
begin: ASSERT_OUP_CHK
if (i_rst_an && i_ena && (r_start_chk == 3))
begin
if (o_data_rtl !== o_data_mat)
begin
$error("### RTL = %d, MAT = %d", o_data_rtl, o_data_mat); error_count<= error_count + 1;
end
end
end
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_ppi_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_ppi_tb);
end
`endif
endmodule |
module filt_ppd_tb;
time CLK_PERIOD = 50;
reg i_rst_an;
reg i_ena=1'b0;
reg i_clk;
reg f_clk=1'b0;
wire s_clk;// = 1'b0;
integer error_count=0;
reg data_ready;
reg signed [`P_INP_DATA_W-1:0] i_data,r_data;
wire signed [`P_OUP_W-1:0] o_data_rtl;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin: RGU
i_rst_an = 1'b1;
#130 i_rst_an = 1'b0;
#205 i_rst_an = 1'b1;
end
always @(posedge f_clk)
begin: EGU
if (i_rst_an&&!s_clk)
i_ena = 1'b1;
end
always
begin: GEN_CLK
f_clk = #(CLK_PERIOD/2) ~f_clk;
end
reg res_clk;
initial begin
fork
forever #2 i_clk = f_clk;
forever #1 res_clk = s_clk;
join
end
initial data_ready = 0;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of Polyphase Decimation FIR Filter.");
$display("### Testcase %d", `TESTCASE);
//$write("### ");$system($sformatf("date"));
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);$display("%s",filename_mat_oup);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", r_data);
else
r_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always i_data = #5 r_data;
always @(posedge res_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup, "%d\n", o_data_mat);
end
filt_ppd #(
.gp_idata_width (`P_INP_DATA_W ),
.gp_decimation_factor (`P_DECIMATION ),
.gp_coeff_length (`P_COEFF_L ),
.gp_coeff_width (`P_COEFF_W ),
.gp_tf_df (`P_TF_DF ),
.gp_comm_reg_oup (`P_COMM_R_OUP ),
.gp_comm_ccw (`P_COMM_CCW_CW),
.gp_mul_ccw (`P_MUL_CCW_CW ),
.gp_comm_phase (`P_COMM_PHA ),
.gp_odata_width ( )
) dut (
.i_rst_an (i_rst_an ),
.i_ena (i_ena ),
.i_clk (i_clk ),
.i_data (i_data ),
.o_data (o_data_rtl),
.o_sclk (s_clk )
);
always @(negedge s_clk)
begin
if (i_rst_an && i_ena)
if (o_data_rtl != o_data_mat)
//else
begin
$error("### RTL = %d, MAT = %d", o_data_rtl, o_data_mat); error_count<= error_count + 1;
end
end
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_ppd_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_ppd_tb);
end
`endif
endmodule |
module filt_mac_tb;
localparam CLK_CYCLES = (`P_SYMM) ? `DIV2(`P_COEFF_L) : `P_COEFF_L;
time F_CLK_PERIOD = 50;
time S_CLK_PERIOD = 50*CLK_CYCLES;
reg i_rst_an;
reg i_ena;
reg i_clk;
reg s_clk;
reg f_clk = 1'b0;
reg [`P_INP_DATA_W-1:0] i_data;
wire rdy;
wire signed [`P_OUP_DATA_W-1:0] oup_data;
wire o_done;
reg data_ready;
reg load_response= 1'b0;
integer error_count=0;
integer count_clk_cycles=127;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_DATA_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin: RGU
i_rst_an = 1'b1;
#17 i_rst_an = 1'b0;
#205 i_rst_an = 1'b1;
end
initial
begin: EGU
i_ena = 1'b0;
#400 i_ena = 1'b1;
end
//initial f_clk = 1'b0;
always
begin: FCGU
f_clk = #(F_CLK_PERIOD) ~f_clk;
end
initial s_clk = 1'b0;
//initial count_clk_cycles = 127;
always @(posedge f_clk)
begin: CLK_DIV
if (i_ena)
begin
if (count_clk_cycles < CLK_CYCLES-1)
count_clk_cycles <= count_clk_cycles + 1'b1;
else
count_clk_cycles = 0;
end
end
always @(*)
begin: SCGU
s_clk = (count_clk_cycles==0) ? 1'b1 : 1'b0;
end
always
begin: CGU
i_clk = #1 f_clk;
end
//initial load_response = 1'b0;
always @(posedge o_done)
begin
if ( (i_rst_an && i_ena) && (load_response < 1) )
load_response <= load_response + 1'b1;
end
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of FIR Filter.");
$display("### Testcase %d", `TESTCASE);
$write("### ");
//$system($sformatf("date"));
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge s_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(posedge s_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena && load_response)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
else
o_data_mat = 'd0;
end
always @(negedge s_clk)
begin: CHK_OUP
if (i_rst_an && i_ena)
if (oup_data != o_data_mat)
begin
$error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
end
end
/*initial
begin
i_data = 'd0;
#(549+300) i_data = 'd1;
#(4*100) i_data = 'd0;
i_data = 'd0;
#(549+300) i_data = 'd1;
i_data = 'd10;
#(549+300) i_data = 'd1;
#(4*100) i_data = 'd2;
#(4*100) i_data = 'd3;
#(4*100) i_data = 'd4;
#(4*100) i_data = 'd5;
#(4*100) i_data = 'd6;
#(4*100) i_data = 'd7;
#(4*100) i_data = 'd8;
#(4*100) i_data = 'd9;
i_data = 'd0;
#(549+1700) i_data = 'd1;
#(17*100) i_data = 'd2;
#(17*100) i_data = 'd3;
#(17*100) i_data = 'd4;
#(17*100) i_data = 'd5;
#(17*100) i_data = 'd6;
#(17*100) i_data = 'd7;
#(17*100) i_data = 'd8;
#(17*100) i_data = 'd9;
end*/
filt_mac #(
.gp_inp_width (`P_INP_DATA_W),
.gp_coeff_length (`P_COEFF_L),
.gp_coeff_width (`P_COEFF_W),
.gp_symm (`P_SYMM),
.gp_oup_width (`P_OUP_DATA_W)
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (oup_data),
.o_done (o_done)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_mac_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_mac_tb);
end
`endif
endmodule |
module filt_cici_tb;
time CLK_PERIOD = 400;
//time F_CLK_PERIOD = CLK_PERIOD/`P_INTERPOLATION;
reg i_rst_an;
reg i_ena=1'b0;
reg i_clk=1'b0;
reg i_fclk=1'b0;
reg f_clk=1'b0;
reg s_clk;
int r_cnt=`P_INTERPOLATION;
reg [`P_INP_DATA_W-1:0] i_data,r_data;
wire rdy;
wire signed [`P_OUP_DATA_W-1:0] oup_data;
reg data_ready=1'b0;
integer error_count=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_DATA_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin: RST
i_rst_an = 1'b1;
#2 i_rst_an = 1'b0;
#(0.5*CLK_PERIOD) i_rst_an = 1'b1;
end
always @(posedge s_clk)
begin: EGU
if (i_rst_an)
i_ena = 1'b1;
end
always f_clk = #(CLK_PERIOD/(`P_INTERPOLATION*2)) ~f_clk;
always @(posedge f_clk)
begin: SCLK
if (r_cnt<`P_INTERPOLATION-1)
r_cnt <= r_cnt + 1;
else
r_cnt <= 'd0;
end
assign s_clk = (r_cnt<`P_INTERPOLATION/2) ? 1'b1 : 1'b0;
initial begin
fork
forever #2 i_fclk = f_clk;
forever #2 i_clk = s_clk;
join
end
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of CIC Interpolation Filter.");
$display("### Testcase %d", `TESTCASE);
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(posedge i_fclk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
end
always @(negedge f_clk)
begin
if (i_rst_an && i_ena)
if (oup_data != o_data_mat)
begin
$error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
end
end
filt_cici #(
.gp_interpolation_factor (`P_INTERPOLATION),
.gp_order (`P_ORDER),
.gp_diff_delay (`P_DIFF_DELAY),
.gp_phase (`P_PHASE),
.gp_inp_width (`P_INP_DATA_W),
.gp_oup_width (`P_OUP_DATA_W)
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (s_clk),
.i_fclk (i_fclk),
.i_data (i_data),
.o_data (oup_data)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_cici_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_cici_tb);
end
`endif
endmodule |
module sgen_cordic_tb;
time F_CLK_PERIOD = 50;
time S_CLK_PERIOD = 50*`P_ITER;
reg i_rst_an;
reg i_ena;
reg i_clk;
wire s_clk;
reg f_clk;
reg data_ready=1'b0;
integer counter;
integer error_count=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_dbg;
integer fid_mat_dbg;
integer status_mat_dbg;
// MATLAB DEBUG OUTPUTS
reg signed [`P_XY_WIDTH+$clog2(`P_ITER)-1:0] o_x_mat;
reg signed [`P_XY_WIDTH+$clog2(`P_ITER)-1:0] o_y_mat;
reg signed [`P_Z_WIDTH +$clog2(`P_ITER)-1:0] o_z_mat;
reg signed [1 :0] o_d_mat;
reg signed [`P_XY_WIDTH-1:0] i_x;
reg signed [`P_XY_WIDTH-1:0] i_y;
reg signed [`P_Z_WIDTH-1 :0] i_z;
reg signed [`P_XY_WIDTH+$clog2(`P_ITER)-1:0] o_x_a_mat;
reg signed [`P_XY_WIDTH-1:0] o_y_r_mat;//???? change width based on mode of operation
// -------------------------------------------------------------------
initial
begin
i_rst_an = 1'b1;
#1 i_rst_an = 1'b0;
#(S_CLK_PERIOD-10) i_rst_an = 1'b1;
end
initial
begin
i_ena = 1'b0;
#(S_CLK_PERIOD-1) i_ena = 1'b1;
end
initial f_clk = 1'b1;
always f_clk = #(F_CLK_PERIOD) ~f_clk;
initial counter = 1024;
always @(posedge f_clk)
begin
if (counter < `P_ITER-1)
counter <= counter + 1;
else
counter <= 0;
end
assign s_clk = (counter < `P_ITER/2) ? 1'b0 : 1'b1;
assign #1 i_clk = (`P_IMPL_U_I) ? s_clk : f_clk;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of FIR Filter.");
$display("### Testcase %d", `TESTCASE);
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_oup_mat.dat");
$sformat(filename_mat_dbg,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_dbg_mat.dat");
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
fid_mat_dbg = $fopen(filename_mat_dbg, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
$fclose(fid_mat_dbg);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge s_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d %d %d\n", i_x, i_y, i_z);
end
always @(negedge s_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d %d\n", o_x_a_mat, o_y_r_mat);
end
always @(negedge f_clk)
begin: MATLAB_DEBUG
if (i_rst_an && i_ena)
status_mat_dbg = $fscanf(fid_mat_dbg,"%d %d %d %d\n", o_x_mat, o_y_mat, o_z_mat, o_d_mat);
if ($feof(fid_mat_dbg)) begin
data_ready = 1'b1;
end
end
wire signed [`P_XY_WIDTH-1:0] x_2_gain;
wire signed [`P_XY_WIDTH-1:0] y_2_gain;
sgen_cordic #(
.gp_mode_rot_vec (`P_MODE_ROT_VEC),
.gp_impl_unrolled_iterative (`P_IMPL_U_I),
.gp_nr_iter (`P_ITER),
.gp_angle_width (`P_ATAN_LUT_WIDTH),
.gp_angle_depth (`P_ATAN_LUT_DEPTH),
.gp_xy_width (`P_XY_WIDTH),
.gp_z_width (`P_Z_WIDTH)
) dut (
.i_rst_an(i_rst_an),
.i_ena(i_ena),
.i_clk(i_clk),
.i_x(i_x),
.i_y(i_y),
.i_z(i_z),
.o_x(x_2_gain),
.o_y(y_2_gain),
.o_z(),
.o_done()
);
cordic_gain #(
.gp_mode_rot_vec (`P_MODE_ROT_VEC),
.gp_gain_width (`P_ATAN_GAIN_WIDTH),
.gp_xy_width (`P_XY_WIDTH),
.gp_xy_owidth ()
) gain_compensation (
.i_cordic_x (x_2_gain),
.i_cordic_y (y_2_gain),
.o_cordic_x (),
.o_cordic_y ()
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","sgen_cordic_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,sgen_cordic_tb);
end
`endif
endmodule |
module filt_cicd_tb;
time CLK_PERIOD = 50;
reg i_rst_an;
reg i_ena;
reg i_clk;
wire s_clk;
reg [`P_INP_DATA_W-1:0] i_data;
wire rdy;
wire signed [`P_OUP_DATA_W-1:0] oup_data;
reg data_ready;
integer error_count=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_DATA_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin
i_rst_an = 1'b1;
#170 i_rst_an = 1'b0;
#205 i_rst_an = 1'b1;
end
initial
begin
i_ena = 1'b0;
#400 i_ena = 1'b1;
end
initial i_clk = 1'b0;
always i_clk = #(CLK_PERIOD) ~i_clk;
assign #1 s_clk = dut.w_sclk;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of FIR Filter.");
$display("### Testcase %d", `TESTCASE);
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(negedge s_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
else
o_data_mat = 'd0;
end
always @(posedge s_clk)
begin
if (i_rst_an && i_ena)
if (oup_data != o_data_mat)
//else
begin
$error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
end
end
filt_cicd #(
.gp_decimation_factor (`P_DECIMATION),
.gp_order (`P_ORDER),
.gp_diff_delay (`P_DIFF_DELAY),
.gp_phase (`P_PHASE),
.gp_inp_width (`P_INP_DATA_W),
.gp_oup_width ()
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (oup_data)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_cicd_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_cicd_tb);
end
`endif
endmodule |
module Top(
input wire logic reset,
input wire logic clk,
output wire logic tx,
input wire logic rx,
output wire logic led);
logic reset_n;
SyncChain #(.DEFAULT(1'b0)) reset_sync_chain(
.reset_n(~reset),
.clk(clk),
.x(1'b1),
.x_sync(reset_n));
logic rx_sync;
SyncChain #(.DEFAULT(1'b1)) rx_sync_chain(
.reset_n(reset_n),
.clk(clk),
.x(rx),
.x_sync(rx_sync));
Uart uart(
.reset_n(reset_n),
.clk(clk),
.tx(tx),
.rx(rx_sync),
.has_errored(led));
endmodule |
module cci_std_afu(
// Link/Protocol (LP) clocks and reset
input /*var*/ logic vl_clk_LPdomain_32ui, // CCI Inteface Clock. 32ui link/protocol clock domain.
input /*var*/ logic vl_clk_LPdomain_16ui, // 2x CCI interface clock. Synchronous.16ui link/protocol clock domain.
input /*var*/ logic ffs_vl_LP32ui_lp2sy_SystemReset_n, // System Reset
input /*var*/ logic ffs_vl_LP32ui_lp2sy_SoftReset_n, // CCI-S soft reset
// Native CCI Interface (cache line interface for back end)
/* Channel 0 can receive READ, WRITE, WRITE CSR responses.*/
input /*var*/ logic [17:0] ffs_vl18_LP32ui_lp2sy_C0RxHdr, // System to LP header
input /*var*/ logic [511:0] ffs_vl512_LP32ui_lp2sy_C0RxData, // System to LP data
input /*var*/ logic ffs_vl_LP32ui_lp2sy_C0RxWrValid, // RxWrHdr valid signal
input /*var*/ logic ffs_vl_LP32ui_lp2sy_C0RxRdValid, // RxRdHdr valid signal
input /*var*/ logic ffs_vl_LP32ui_lp2sy_C0RxCgValid, // RxCgHdr valid signal
input /*var*/ logic ffs_vl_LP32ui_lp2sy_C0RxUgValid, // Rx Umsg Valid signal
input /*var*/ logic ffs_vl_LP32ui_lp2sy_C0RxIrValid, // Rx Interrupt valid signal
/* Channel 1 reserved for WRITE RESPONSE ONLY */
input /*var*/ logic [17:0] ffs_vl18_LP32ui_lp2sy_C1RxHdr, // System to LP header (Channel 1)
input /*var*/ logic ffs_vl_LP32ui_lp2sy_C1RxWrValid, // RxData valid signal (Channel 1)
input /*var*/ logic ffs_vl_LP32ui_lp2sy_C1RxIrValid, // Rx Interrupt valid signal (Channel 1)
/*Channel 0 reserved for READ REQUESTS ONLY */
output /*var*/ logic [60:0] ffs_vl61_LP32ui_sy2lp_C0TxHdr, // System to LP header
output /*var*/ logic ffs_vl_LP32ui_sy2lp_C0TxRdValid, // TxRdHdr valid signals
/*Channel 1 reserved for WRITE REQUESTS ONLY */
output /*var*/ logic [60:0] ffs_vl61_LP32ui_sy2lp_C1TxHdr, // System to LP header
output /*var*/ logic [511:0] ffs_vl512_LP32ui_sy2lp_C1TxData, // System to LP data
output /*var*/ logic ffs_vl_LP32ui_sy2lp_C1TxWrValid, // TxWrHdr valid signal
output /*var*/ logic ffs_vl_LP32ui_sy2lp_C1TxIrValid, // Tx Interrupt valid signal
/* Tx push flow control */
input /*var*/ logic ffs_vl_LP32ui_lp2sy_C0TxAlmFull, // Channel 0 almost full
input /*var*/ logic ffs_vl_LP32ui_lp2sy_C1TxAlmFull, // Channel 1 almost full
input /*var*/ logic ffs_vl_LP32ui_lp2sy_InitDnForSys // System layer is aok to run
);
/* User AFU goes here
*/
fpga_arch fpga_arch(
.clk (vl_clk_LPdomain_32ui),
.Clk_400 (vl_clk_LPdomain_16ui),
.rst_n (ffs_vl_LP32ui_lp2sy_SystemReset_n),
.linkup (ffs_vl_LP32ui_lp2sy_InitDnForSys),
// CCI TX read request
.cci_tx_rd_almostfull (ffs_vl_LP32ui_lp2sy_C0TxAlmFull),
.spl_tx_rd_valid (ffs_vl_LP32ui_sy2lp_C0TxRdValid),
.spl_tx_rd_hdr (ffs_vl61_LP32ui_sy2lp_C0TxHdr),
// CCI TX write request
.cci_tx_wr_almostfull (ffs_vl_LP32ui_lp2sy_C1TxAlmFull),
.spl_tx_wr_valid (ffs_vl_LP32ui_sy2lp_C1TxWrValid),
.spl_tx_intr_valid (ffs_vl_LP32ui_sy2lp_C1TxIrValid),
.spl_tx_wr_hdr (ffs_vl61_LP32ui_sy2lp_C1TxHdr),
.spl_tx_data (ffs_vl512_LP32ui_sy2lp_C1TxData),
// CCI RX read response
.cci_rx_rd_valid (ffs_vl_LP32ui_lp2sy_C0RxRdValid),
.cci_rx_wr_valid0 (ffs_vl_LP32ui_lp2sy_C0RxWrValid),
.cci_rx_cfg_valid (ffs_vl_LP32ui_lp2sy_C0RxCgValid),
.cci_rx_intr_valid0 (ffs_vl_LP32ui_lp2sy_C0RxIrValid),
.cci_rx_umsg_valid (ffs_vl_LP32ui_lp2sy_C0RxUgValid),
.cci_rx_hdr0 (ffs_vl18_LP32ui_lp2sy_C0RxHdr),
.cci_rx_data (ffs_vl512_LP32ui_lp2sy_C0RxData),
// CCI RX write response
.cci_rx_wr_valid1 (ffs_vl_LP32ui_lp2sy_C1RxWrValid),
.cci_rx_intr_valid1 (ffs_vl_LP32ui_lp2sy_C1RxIrValid),
.cci_rx_hdr1 (ffs_vl18_LP32ui_lp2sy_C1RxHdr)
);
endmodule |
module ack_delay_logic (
input wire [31:0] delay_ack_pio,
input wire ack_in,
output wire ack_delay_out,
input wire clk,
input wire reset
);
wire ack_loopback_delay_ver;
reg [1:0] state, next_state;
reg [31:0] ack_delay_counter;
reg start_ack_count;
reg en_ack_loopback;
reg reset_ack_count;
localparam [1:0] IDLE = 2'b00;
localparam [1:0] ACK_DELAY_COUNT = 2'b01;
localparam [1:0] ENABLE_ACK_LOOPBACK = 2'b10;
localparam [1:0] RESET_ACK_DELAY_COUNT = 2'b11;
always @(posedge clk or posedge reset) begin
if (reset) begin
ack_delay_counter <= 32'd0;
end
else begin
if (start_ack_count) begin
ack_delay_counter <= ack_delay_counter + 32'd1;
end
if (reset_ack_count) begin
ack_delay_counter <= 32'd0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
always @* begin
case (state)
IDLE: begin
if (ack_in) begin
if (delay_ack_pio == 0) begin
next_state = ENABLE_ACK_LOOPBACK;
end else begin
next_state = ACK_DELAY_COUNT;
end
end
else begin
next_state = IDLE;
end
end
ACK_DELAY_COUNT: begin
if (ack_delay_counter == delay_ack_pio) begin
next_state = ENABLE_ACK_LOOPBACK;
end
else begin
next_state = ACK_DELAY_COUNT;
end
end
ENABLE_ACK_LOOPBACK: begin
if (~ack_in) begin
next_state = RESET_ACK_DELAY_COUNT;
end
else begin
next_state = ENABLE_ACK_LOOPBACK;
end
end
RESET_ACK_DELAY_COUNT: begin
next_state = IDLE;
end
default: begin
next_state = 2'bxx;
end
endcase
end
always @(next_state) begin
if (next_state == ACK_DELAY_COUNT) begin
start_ack_count <= 1'b1;
end else
start_ack_count <= 1'b0;
end
always @(next_state) begin
if (next_state == ENABLE_ACK_LOOPBACK) begin
en_ack_loopback <= 1'b1;
end else
en_ack_loopback <= 1'b0;
end
always @(next_state) begin
if (next_state == RESET_ACK_DELAY_COUNT || next_state == IDLE) begin
reset_ack_count <= 1'b1;
end else
reset_ack_count <= 1'b0;
end
assign ack_delay_out = (en_ack_loopback) ? ack_in : 1'b0;
endmodule |
module ghrd_10as066n2_pr_region_controller_0_altera_conduit_merger_171_nva7cjy #(
parameter NUM_INTF_BRIDGE = 1
) (
input illegal_request0,
output freeze0,
input illegal_request1,
output freeze1,
output pr_freeze0,
input freeze_in,
output [NUM_INTF_BRIDGE-1:0] illegal_request_out
);
assign illegal_request_out = {
illegal_request1,
illegal_request0
};
assign freeze1 = freeze_in;
assign freeze0 = freeze_in;
assign pr_freeze0 = freeze_in;
endmodule |
module Computer_System_mm_interconnect_1_cmd_demux
(
// -------------------
// Sink
// -------------------
input [9-1 : 0] sink_valid,
input [129-1 : 0] sink_data, // ST_DATA_W=129
input [9-1 : 0] sink_channel, // ST_CHANNEL_W=9
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [129-1 : 0] src0_data, // ST_DATA_W=129
output reg [9-1 : 0] src0_channel, // ST_CHANNEL_W=9
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [129-1 : 0] src1_data, // ST_DATA_W=129
output reg [9-1 : 0] src1_channel, // ST_CHANNEL_W=9
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [129-1 : 0] src2_data, // ST_DATA_W=129
output reg [9-1 : 0] src2_channel, // ST_CHANNEL_W=9
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [129-1 : 0] src3_data, // ST_DATA_W=129
output reg [9-1 : 0] src3_channel, // ST_CHANNEL_W=9
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [129-1 : 0] src4_data, // ST_DATA_W=129
output reg [9-1 : 0] src4_channel, // ST_CHANNEL_W=9
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [129-1 : 0] src5_data, // ST_DATA_W=129
output reg [9-1 : 0] src5_channel, // ST_CHANNEL_W=9
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
output reg src6_valid,
output reg [129-1 : 0] src6_data, // ST_DATA_W=129
output reg [9-1 : 0] src6_channel, // ST_CHANNEL_W=9
output reg src6_startofpacket,
output reg src6_endofpacket,
input src6_ready,
output reg src7_valid,
output reg [129-1 : 0] src7_data, // ST_DATA_W=129
output reg [9-1 : 0] src7_channel, // ST_CHANNEL_W=9
output reg src7_startofpacket,
output reg src7_endofpacket,
input src7_ready,
output reg src8_valid,
output reg [129-1 : 0] src8_data, // ST_DATA_W=129
output reg [9-1 : 0] src8_channel, // ST_CHANNEL_W=9
output reg src8_startofpacket,
output reg src8_endofpacket,
input src8_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 9;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid[0];
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid[1];
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid[2];
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid[3];
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid[4];
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid[5];
src6_data = sink_data;
src6_startofpacket = sink_startofpacket;
src6_endofpacket = sink_endofpacket;
src6_channel = sink_channel >> NUM_OUTPUTS;
src6_valid = sink_channel[6] && sink_valid[6];
src7_data = sink_data;
src7_startofpacket = sink_startofpacket;
src7_endofpacket = sink_endofpacket;
src7_channel = sink_channel >> NUM_OUTPUTS;
src7_valid = sink_channel[7] && sink_valid[7];
src8_data = sink_data;
src8_startofpacket = sink_startofpacket;
src8_endofpacket = sink_endofpacket;
src8_channel = sink_channel >> NUM_OUTPUTS;
src8_valid = sink_channel[8] && sink_valid[8];
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign ready_vector[6] = src6_ready;
assign ready_vector[7] = src7_ready;
assign ready_vector[8] = src8_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule |
module Computer_System_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
input receiver2_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[1] = receiver0_irq;
sender_irq[11] = receiver1_irq;
sender_irq[12] = receiver2_irq;
end
endmodule |
module Computer_System_mm_interconnect_0_rsp_demux_001
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [111-1 : 0] sink_data, // ST_DATA_W=111
input [5-1 : 0] sink_channel, // ST_CHANNEL_W=5
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [111-1 : 0] src0_data, // ST_DATA_W=111
output reg [5-1 : 0] src0_channel, // ST_CHANNEL_W=5
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [111-1 : 0] src1_data, // ST_DATA_W=111
output reg [5-1 : 0] src1_channel, // ST_CHANNEL_W=5
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [111-1 : 0] src2_data, // ST_DATA_W=111
output reg [5-1 : 0] src2_channel, // ST_CHANNEL_W=5
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [111-1 : 0] src3_data, // ST_DATA_W=111
output reg [5-1 : 0] src3_channel, // ST_CHANNEL_W=5
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 4;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module Computer_System_mm_interconnect_1_router_default_decode
#(
parameter DEFAULT_CHANNEL = 8,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 8
)
(output [104 - 101 : 0] default_destination_id,
output [9-1 : 0] default_wr_channel,
output [9-1 : 0] default_rd_channel,
output [9-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 101 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 9'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 9'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 9'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module Computer_System_mm_interconnect_1_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [129-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [129-1 : 0] src_data,
output reg [9-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 104;
localparam PKT_DEST_ID_L = 101;
localparam PKT_PROTECTION_H = 119;
localparam PKT_PROTECTION_L = 117;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 9;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10 - 64'h0);
localparam PAD1 = log2ceil(64'h50 - 64'h40);
localparam PAD2 = log2ceil(64'h60 - 64'h50);
localparam PAD3 = log2ceil(64'h2048 - 64'h2040);
localparam PAD4 = log2ceil(64'h3030 - 64'h3020);
localparam PAD5 = log2ceil(64'h3040 - 64'h3030);
localparam PAD6 = log2ceil(64'h3070 - 64'h3060);
localparam PAD7 = log2ceil(64'h3080 - 64'h3070);
localparam PAD8 = log2ceil(64'h80000 - 64'h40000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h80000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [9-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
Computer_System_mm_interconnect_1_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x10 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin
src_channel = 9'b000001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x40 .. 0x50 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40 && read_transaction ) begin
src_channel = 9'b000010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x50 .. 0x60 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h50 ) begin
src_channel = 9'b000100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x2040 .. 0x2048 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 19'h2040 && read_transaction ) begin
src_channel = 9'b000000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x3020 .. 0x3030 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 19'h3020 ) begin
src_channel = 9'b001000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x3030 .. 0x3040 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 19'h3030 ) begin
src_channel = 9'b000000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x3060 .. 0x3070 )
if ( {address[RG:PAD6],{PAD6{1'b0}}} == 19'h3060 ) begin
src_channel = 9'b010000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x3070 .. 0x3080 )
if ( {address[RG:PAD7],{PAD7{1'b0}}} == 19'h3070 ) begin
src_channel = 9'b000000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
end
// ( 0x40000 .. 0x80000 )
if ( {address[RG:PAD8],{PAD8{1'b0}}} == 19'h40000 ) begin
src_channel = 9'b100000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module Computer_System_mm_interconnect_4_cmd_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [74-1 : 0] sink_data, // ST_DATA_W=74
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [74-1 : 0] src0_data, // ST_DATA_W=74
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module Computer_System_mm_interconnect_0_rsp_mux_002
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [111-1 : 0] sink0_data,
input [5-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [111-1 : 0] src_data,
output [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 111 + 5 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 111;
localparam ST_CHANNEL_W = 5;
localparam PKT_TRANS_LOCK = 54;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module Computer_System_mm_interconnect_1_router_008_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 0
)
(output [104 - 101 : 0] default_destination_id,
output [9-1 : 0] default_wr_channel,
output [9-1 : 0] default_rd_channel,
output [9-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 101 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 9'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 9'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 9'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module Computer_System_mm_interconnect_0_router_007_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 0
)
(output [104 - 103 : 0] default_destination_id,
output [5-1 : 0] default_wr_channel,
output [5-1 : 0] default_rd_channel,
output [5-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 103 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module Computer_System_Video_In_Subsystem_avalon_st_adapter_data_format_adapter_0 (
// Interface: in
output reg in_ready,
input in_valid,
input [16-1 : 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [16-1: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
output reg out_empty,
// Interface: clk
input clk,
// Interface: reset
input reset_n
);
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_empty = 0;
end
endmodule |
module Computer_System_mm_interconnect_0_router_002_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [86 - 85 : 0] default_destination_id,
output [5-1 : 0] default_wr_channel,
output [5-1 : 0] default_rd_channel,
output [5-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[86 - 85 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module Computer_System_mm_interconnect_0_router_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [111-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [111-1 : 0] src_data,
output reg [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 49;
localparam PKT_ADDR_L = 18;
localparam PKT_DEST_ID_H = 86;
localparam PKT_DEST_ID_L = 85;
localparam PKT_PROTECTION_H = 101;
localparam PKT_PROTECTION_L = 99;
localparam ST_DATA_W = 111;
localparam ST_CHANNEL_W = 5;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 52;
localparam PKT_TRANS_READ = 53;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h8040000 - 64'h8000000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h8040000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [5-1 : 0] default_src_channel;
Computer_System_mm_interconnect_0_router_002_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 8000000 .. 8040000 )
src_channel = 5'b1;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module Computer_System_mm_interconnect_0_router_003
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [111-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [111-1 : 0] src_data,
output reg [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 49;
localparam PKT_ADDR_L = 18;
localparam PKT_DEST_ID_H = 86;
localparam PKT_DEST_ID_L = 85;
localparam PKT_PROTECTION_H = 101;
localparam PKT_PROTECTION_L = 99;
localparam ST_DATA_W = 111;
localparam ST_CHANNEL_W = 5;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 52;
localparam PKT_TRANS_READ = 53;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h4000000 - 64'h0);
localparam PAD1 = log2ceil(64'h8040000 - 64'h8000000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h8040000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [5-1 : 0] default_src_channel;
Computer_System_mm_interconnect_0_router_003_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x4000000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 28'h0 ) begin
src_channel = 5'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x8000000 .. 0x8040000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 28'h8000000 ) begin
src_channel = 5'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module Computer_System_mm_interconnect_0_cmd_demux_003
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [111-1 : 0] sink_data, // ST_DATA_W=111
input [5-1 : 0] sink_channel, // ST_CHANNEL_W=5
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [111-1 : 0] src0_data, // ST_DATA_W=111
output reg [5-1 : 0] src0_channel, // ST_CHANNEL_W=5
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [111-1 : 0] src1_data, // ST_DATA_W=111
output reg [5-1 : 0] src1_channel, // ST_CHANNEL_W=5
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{3{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module Computer_System_mm_interconnect_1_router_007_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 0
)
(output [104 - 101 : 0] default_destination_id,
output [9-1 : 0] default_wr_channel,
output [9-1 : 0] default_rd_channel,
output [9-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 101 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 9'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 9'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 9'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module Computer_System_mm_interconnect_1_router_007
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [129-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [129-1 : 0] src_data,
output reg [9-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 104;
localparam PKT_DEST_ID_L = 101;
localparam PKT_PROTECTION_H = 119;
localparam PKT_PROTECTION_L = 117;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 9;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [9-1 : 0] default_rd_channel;
wire [9-1 : 0] default_wr_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
Computer_System_mm_interconnect_1_router_007_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (default_wr_channel),
.default_rd_channel (default_rd_channel),
.default_src_channel ()
);
always @* begin
src_data = sink_data;
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 && write_transaction) begin
src_channel = 9'b001;
end
if (destid == 0 && read_transaction) begin
src_channel = 9'b010;
end
if (destid == 1 && write_transaction) begin
src_channel = 9'b100;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module Computer_System_mm_interconnect_0_router_005_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 0
)
(output [104 - 103 : 0] default_destination_id,
output [5-1 : 0] default_wr_channel,
output [5-1 : 0] default_rd_channel,
output [5-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 103 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module Computer_System_mm_interconnect_0_router_006
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [111-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [111-1 : 0] src_data,
output reg [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 49;
localparam PKT_ADDR_L = 18;
localparam PKT_DEST_ID_H = 86;
localparam PKT_DEST_ID_L = 85;
localparam PKT_PROTECTION_H = 101;
localparam PKT_PROTECTION_L = 99;
localparam ST_DATA_W = 111;
localparam ST_CHANNEL_W = 5;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 52;
localparam PKT_TRANS_READ = 53;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [5-1 : 0] default_rd_channel;
wire [5-1 : 0] default_wr_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
Computer_System_mm_interconnect_0_router_006_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (default_wr_channel),
.default_rd_channel (default_rd_channel),
.default_src_channel ()
);
always @* begin
src_data = sink_data;
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 && write_transaction) begin
src_channel = 5'b0001;
end
if (destid == 0 && read_transaction) begin
src_channel = 5'b0010;
end
if (destid == 3 && write_transaction) begin
src_channel = 5'b0100;
end
if (destid == 1 && read_transaction) begin
src_channel = 5'b1000;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module Computer_System_mm_interconnect_4_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [74-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [74-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 39;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 60;
localparam PKT_DEST_ID_L = 60;
localparam PKT_PROTECTION_H = 64;
localparam PKT_PROTECTION_L = 62;
localparam ST_DATA_W = 74;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 42;
localparam PKT_TRANS_READ = 43;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10 - 64'h0);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h10;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [2-1 : 0] default_src_channel;
Computer_System_mm_interconnect_4_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0 .. 10 )
src_channel = 2'b1;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module Computer_System_mm_interconnect_1_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [129-1 : 0] sink_data, // ST_DATA_W=129
input [9-1 : 0] sink_channel, // ST_CHANNEL_W=9
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [129-1 : 0] src0_data, // ST_DATA_W=129
output reg [9-1 : 0] src0_channel, // ST_CHANNEL_W=9
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [129-1 : 0] src1_data, // ST_DATA_W=129
output reg [9-1 : 0] src1_channel, // ST_CHANNEL_W=9
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{7{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [61 - 61 : 0] default_destination_id,
output [1-1 : 0] default_wr_channel,
output [1-1 : 0] default_rd_channel,
output [1-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[61 - 61 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 1'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 1'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 1'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [75-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [75-1 : 0] src_data,
output reg [1-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 40;
localparam PKT_ADDR_L = 9;
localparam PKT_DEST_ID_H = 61;
localparam PKT_DEST_ID_L = 61;
localparam PKT_PROTECTION_H = 65;
localparam PKT_PROTECTION_L = 63;
localparam ST_DATA_W = 75;
localparam ST_CHANNEL_W = 1;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 43;
localparam PKT_TRANS_READ = 44;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h9002000 - 64'h9000000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h9002000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [1-1 : 0] default_src_channel;
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 9000000 .. 9002000 )
src_channel = 1'b1;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module Computer_System_mm_interconnect_0_rsp_demux_003
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [129-1 : 0] sink_data, // ST_DATA_W=129
input [5-1 : 0] sink_channel, // ST_CHANNEL_W=5
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [129-1 : 0] src0_data, // ST_DATA_W=129
output reg [5-1 : 0] src0_channel, // ST_CHANNEL_W=5
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module Computer_System_mm_interconnect_0_cmd_mux_003
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [129-1 : 0] sink0_data,
input [5-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [129-1 : 0] src_data,
output [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 129 + 5 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 5;
localparam PKT_TRANS_LOCK = 72;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module Computer_System_mm_interconnect_1_cmd_demux_002
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [129-1 : 0] sink_data, // ST_DATA_W=129
input [9-1 : 0] sink_channel, // ST_CHANNEL_W=9
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [129-1 : 0] src0_data, // ST_DATA_W=129
output reg [9-1 : 0] src0_channel, // ST_CHANNEL_W=9
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{8{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module Computer_System_ARM_A9_HPS_fpga_interfaces(
// h2f_reset
output wire [1 - 1 : 0 ] h2f_rst_n
// f2h_axi_clock
,input wire [1 - 1 : 0 ] f2h_axi_clk
// f2h_axi_slave
,input wire [8 - 1 : 0 ] f2h_AWID
,input wire [32 - 1 : 0 ] f2h_AWADDR
,input wire [4 - 1 : 0 ] f2h_AWLEN
,input wire [3 - 1 : 0 ] f2h_AWSIZE
,input wire [2 - 1 : 0 ] f2h_AWBURST
,input wire [2 - 1 : 0 ] f2h_AWLOCK
,input wire [4 - 1 : 0 ] f2h_AWCACHE
,input wire [3 - 1 : 0 ] f2h_AWPROT
,input wire [1 - 1 : 0 ] f2h_AWVALID
,output wire [1 - 1 : 0 ] f2h_AWREADY
,input wire [5 - 1 : 0 ] f2h_AWUSER
,input wire [8 - 1 : 0 ] f2h_WID
,input wire [64 - 1 : 0 ] f2h_WDATA
,input wire [8 - 1 : 0 ] f2h_WSTRB
,input wire [1 - 1 : 0 ] f2h_WLAST
,input wire [1 - 1 : 0 ] f2h_WVALID
,output wire [1 - 1 : 0 ] f2h_WREADY
,output wire [8 - 1 : 0 ] f2h_BID
,output wire [2 - 1 : 0 ] f2h_BRESP
,output wire [1 - 1 : 0 ] f2h_BVALID
,input wire [1 - 1 : 0 ] f2h_BREADY
,input wire [8 - 1 : 0 ] f2h_ARID
,input wire [32 - 1 : 0 ] f2h_ARADDR
,input wire [4 - 1 : 0 ] f2h_ARLEN
,input wire [3 - 1 : 0 ] f2h_ARSIZE
,input wire [2 - 1 : 0 ] f2h_ARBURST
,input wire [2 - 1 : 0 ] f2h_ARLOCK
,input wire [4 - 1 : 0 ] f2h_ARCACHE
,input wire [3 - 1 : 0 ] f2h_ARPROT
,input wire [1 - 1 : 0 ] f2h_ARVALID
,output wire [1 - 1 : 0 ] f2h_ARREADY
,input wire [5 - 1 : 0 ] f2h_ARUSER
,output wire [8 - 1 : 0 ] f2h_RID
,output wire [64 - 1 : 0 ] f2h_RDATA
,output wire [2 - 1 : 0 ] f2h_RRESP
,output wire [1 - 1 : 0 ] f2h_RLAST
,output wire [1 - 1 : 0 ] f2h_RVALID
,input wire [1 - 1 : 0 ] f2h_RREADY
// h2f_lw_axi_clock
,input wire [1 - 1 : 0 ] h2f_lw_axi_clk
// h2f_lw_axi_master
,output wire [12 - 1 : 0 ] h2f_lw_AWID
,output wire [21 - 1 : 0 ] h2f_lw_AWADDR
,output wire [4 - 1 : 0 ] h2f_lw_AWLEN
,output wire [3 - 1 : 0 ] h2f_lw_AWSIZE
,output wire [2 - 1 : 0 ] h2f_lw_AWBURST
,output wire [2 - 1 : 0 ] h2f_lw_AWLOCK
,output wire [4 - 1 : 0 ] h2f_lw_AWCACHE
,output wire [3 - 1 : 0 ] h2f_lw_AWPROT
,output wire [1 - 1 : 0 ] h2f_lw_AWVALID
,input wire [1 - 1 : 0 ] h2f_lw_AWREADY
,output wire [12 - 1 : 0 ] h2f_lw_WID
,output wire [32 - 1 : 0 ] h2f_lw_WDATA
,output wire [4 - 1 : 0 ] h2f_lw_WSTRB
,output wire [1 - 1 : 0 ] h2f_lw_WLAST
,output wire [1 - 1 : 0 ] h2f_lw_WVALID
,input wire [1 - 1 : 0 ] h2f_lw_WREADY
,input wire [12 - 1 : 0 ] h2f_lw_BID
,input wire [2 - 1 : 0 ] h2f_lw_BRESP
,input wire [1 - 1 : 0 ] h2f_lw_BVALID
,output wire [1 - 1 : 0 ] h2f_lw_BREADY
,output wire [12 - 1 : 0 ] h2f_lw_ARID
,output wire [21 - 1 : 0 ] h2f_lw_ARADDR
,output wire [4 - 1 : 0 ] h2f_lw_ARLEN
,output wire [3 - 1 : 0 ] h2f_lw_ARSIZE
,output wire [2 - 1 : 0 ] h2f_lw_ARBURST
,output wire [2 - 1 : 0 ] h2f_lw_ARLOCK
,output wire [4 - 1 : 0 ] h2f_lw_ARCACHE
,output wire [3 - 1 : 0 ] h2f_lw_ARPROT
,output wire [1 - 1 : 0 ] h2f_lw_ARVALID
,input wire [1 - 1 : 0 ] h2f_lw_ARREADY
,input wire [12 - 1 : 0 ] h2f_lw_RID
,input wire [32 - 1 : 0 ] h2f_lw_RDATA
,input wire [2 - 1 : 0 ] h2f_lw_RRESP
,input wire [1 - 1 : 0 ] h2f_lw_RLAST
,input wire [1 - 1 : 0 ] h2f_lw_RVALID
,output wire [1 - 1 : 0 ] h2f_lw_RREADY
// h2f_axi_clock
,input wire [1 - 1 : 0 ] h2f_axi_clk
// h2f_axi_master
,output wire [12 - 1 : 0 ] h2f_AWID
,output wire [30 - 1 : 0 ] h2f_AWADDR
,output wire [4 - 1 : 0 ] h2f_AWLEN
,output wire [3 - 1 : 0 ] h2f_AWSIZE
,output wire [2 - 1 : 0 ] h2f_AWBURST
,output wire [2 - 1 : 0 ] h2f_AWLOCK
,output wire [4 - 1 : 0 ] h2f_AWCACHE
,output wire [3 - 1 : 0 ] h2f_AWPROT
,output wire [1 - 1 : 0 ] h2f_AWVALID
,input wire [1 - 1 : 0 ] h2f_AWREADY
,output wire [12 - 1 : 0 ] h2f_WID
,output wire [128 - 1 : 0 ] h2f_WDATA
,output wire [16 - 1 : 0 ] h2f_WSTRB
,output wire [1 - 1 : 0 ] h2f_WLAST
,output wire [1 - 1 : 0 ] h2f_WVALID
,input wire [1 - 1 : 0 ] h2f_WREADY
,input wire [12 - 1 : 0 ] h2f_BID
,input wire [2 - 1 : 0 ] h2f_BRESP
,input wire [1 - 1 : 0 ] h2f_BVALID
,output wire [1 - 1 : 0 ] h2f_BREADY
,output wire [12 - 1 : 0 ] h2f_ARID
,output wire [30 - 1 : 0 ] h2f_ARADDR
,output wire [4 - 1 : 0 ] h2f_ARLEN
,output wire [3 - 1 : 0 ] h2f_ARSIZE
,output wire [2 - 1 : 0 ] h2f_ARBURST
,output wire [2 - 1 : 0 ] h2f_ARLOCK
,output wire [4 - 1 : 0 ] h2f_ARCACHE
,output wire [3 - 1 : 0 ] h2f_ARPROT
,output wire [1 - 1 : 0 ] h2f_ARVALID
,input wire [1 - 1 : 0 ] h2f_ARREADY
,input wire [12 - 1 : 0 ] h2f_RID
,input wire [128 - 1 : 0 ] h2f_RDATA
,input wire [2 - 1 : 0 ] h2f_RRESP
,input wire [1 - 1 : 0 ] h2f_RLAST
,input wire [1 - 1 : 0 ] h2f_RVALID
,output wire [1 - 1 : 0 ] h2f_RREADY
// f2h_irq0
,input wire [32 - 1 : 0 ] f2h_irq_p0
// f2h_irq1
,input wire [32 - 1 : 0 ] f2h_irq_p1
);
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_warm_rst_req_n({
1'b1 // 0:0
})
,.f2h_dbg_rst_req_n({
1'b1 // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
1'b1 // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b01 // 1:0
})
,.arsize({
f2h_ARSIZE[2:0] // 2:0
})
,.awuser({
f2h_AWUSER[4:0] // 4:0
})
,.wvalid({
f2h_WVALID[0:0] // 0:0
})
,.rlast({
f2h_RLAST[0:0] // 0:0
})
,.clk({
f2h_axi_clk[0:0] // 0:0
})
,.rresp({
f2h_RRESP[1:0] // 1:0
})
,.arready({
f2h_ARREADY[0:0] // 0:0
})
,.arprot({
f2h_ARPROT[2:0] // 2:0
})
,.araddr({
f2h_ARADDR[31:0] // 31:0
})
,.bvalid({
f2h_BVALID[0:0] // 0:0
})
,.arid({
f2h_ARID[7:0] // 7:0
})
,.bid({
f2h_BID[7:0] // 7:0
})
,.arburst({
f2h_ARBURST[1:0] // 1:0
})
,.arcache({
f2h_ARCACHE[3:0] // 3:0
})
,.awvalid({
f2h_AWVALID[0:0] // 0:0
})
,.wdata({
f2h_WDATA[63:0] // 63:0
})
,.aruser({
f2h_ARUSER[4:0] // 4:0
})
,.rid({
f2h_RID[7:0] // 7:0
})
,.rvalid({
f2h_RVALID[0:0] // 0:0
})
,.wready({
f2h_WREADY[0:0] // 0:0
})
,.awlock({
f2h_AWLOCK[1:0] // 1:0
})
,.bresp({
f2h_BRESP[1:0] // 1:0
})
,.arlen({
f2h_ARLEN[3:0] // 3:0
})
,.awsize({
f2h_AWSIZE[2:0] // 2:0
})
,.awlen({
f2h_AWLEN[3:0] // 3:0
})
,.bready({
f2h_BREADY[0:0] // 0:0
})
,.awid({
f2h_AWID[7:0] // 7:0
})
,.rdata({
f2h_RDATA[63:0] // 63:0
})
,.awready({
f2h_AWREADY[0:0] // 0:0
})
,.arvalid({
f2h_ARVALID[0:0] // 0:0
})
,.wlast({
f2h_WLAST[0:0] // 0:0
})
,.awprot({
f2h_AWPROT[2:0] // 2:0
})
,.awaddr({
f2h_AWADDR[31:0] // 31:0
})
,.wid({
f2h_WID[7:0] // 7:0
})
,.awburst({
f2h_AWBURST[1:0] // 1:0
})
,.awcache({
f2h_AWCACHE[3:0] // 3:0
})
,.arlock({
f2h_ARLOCK[1:0] // 1:0
})
,.rready({
f2h_RREADY[0:0] // 0:0
})
,.wstrb({
f2h_WSTRB[7:0] // 7:0
})
);
cyclonev_hps_interface_hps2fpga_light_weight hps2fpga_light_weight(
.arsize({
h2f_lw_ARSIZE[2:0] // 2:0
})
,.wvalid({
h2f_lw_WVALID[0:0] // 0:0
})
,.rlast({
h2f_lw_RLAST[0:0] // 0:0
})
,.clk({
h2f_lw_axi_clk[0:0] // 0:0
})
,.rresp({
h2f_lw_RRESP[1:0] // 1:0
})
,.arready({
h2f_lw_ARREADY[0:0] // 0:0
})
,.arprot({
h2f_lw_ARPROT[2:0] // 2:0
})
,.araddr({
h2f_lw_ARADDR[20:0] // 20:0
})
,.bvalid({
h2f_lw_BVALID[0:0] // 0:0
})
,.arid({
h2f_lw_ARID[11:0] // 11:0
})
,.bid({
h2f_lw_BID[11:0] // 11:0
})
,.arburst({
h2f_lw_ARBURST[1:0] // 1:0
})
,.arcache({
h2f_lw_ARCACHE[3:0] // 3:0
})
,.awvalid({
h2f_lw_AWVALID[0:0] // 0:0
})
,.wdata({
h2f_lw_WDATA[31:0] // 31:0
})
,.rid({
h2f_lw_RID[11:0] // 11:0
})
,.rvalid({
h2f_lw_RVALID[0:0] // 0:0
})
,.wready({
h2f_lw_WREADY[0:0] // 0:0
})
,.awlock({
h2f_lw_AWLOCK[1:0] // 1:0
})
,.bresp({
h2f_lw_BRESP[1:0] // 1:0
})
,.arlen({
h2f_lw_ARLEN[3:0] // 3:0
})
,.awsize({
h2f_lw_AWSIZE[2:0] // 2:0
})
,.awlen({
h2f_lw_AWLEN[3:0] // 3:0
})
,.bready({
h2f_lw_BREADY[0:0] // 0:0
})
,.awid({
h2f_lw_AWID[11:0] // 11:0
})
,.rdata({
h2f_lw_RDATA[31:0] // 31:0
})
,.awready({
h2f_lw_AWREADY[0:0] // 0:0
})
,.arvalid({
h2f_lw_ARVALID[0:0] // 0:0
})
,.wlast({
h2f_lw_WLAST[0:0] // 0:0
})
,.awprot({
h2f_lw_AWPROT[2:0] // 2:0
})
,.awaddr({
h2f_lw_AWADDR[20:0] // 20:0
})
,.wid({
h2f_lw_WID[11:0] // 11:0
})
,.awcache({
h2f_lw_AWCACHE[3:0] // 3:0
})
,.arlock({
h2f_lw_ARLOCK[1:0] // 1:0
})
,.awburst({
h2f_lw_AWBURST[1:0] // 1:0
})
,.rready({
h2f_lw_RREADY[0:0] // 0:0
})
,.wstrb({
h2f_lw_WSTRB[3:0] // 3:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b10 // 1:0
})
,.arsize({
h2f_ARSIZE[2:0] // 2:0
})
,.wvalid({
h2f_WVALID[0:0] // 0:0
})
,.rlast({
h2f_RLAST[0:0] // 0:0
})
,.clk({
h2f_axi_clk[0:0] // 0:0
})
,.rresp({
h2f_RRESP[1:0] // 1:0
})
,.arready({
h2f_ARREADY[0:0] // 0:0
})
,.arprot({
h2f_ARPROT[2:0] // 2:0
})
,.araddr({
h2f_ARADDR[29:0] // 29:0
})
,.bvalid({
h2f_BVALID[0:0] // 0:0
})
,.arid({
h2f_ARID[11:0] // 11:0
})
,.bid({
h2f_BID[11:0] // 11:0
})
,.arburst({
h2f_ARBURST[1:0] // 1:0
})
,.arcache({
h2f_ARCACHE[3:0] // 3:0
})
,.awvalid({
h2f_AWVALID[0:0] // 0:0
})
,.wdata({
h2f_WDATA[127:0] // 127:0
})
,.rid({
h2f_RID[11:0] // 11:0
})
,.rvalid({
h2f_RVALID[0:0] // 0:0
})
,.wready({
h2f_WREADY[0:0] // 0:0
})
,.awlock({
h2f_AWLOCK[1:0] // 1:0
})
,.bresp({
h2f_BRESP[1:0] // 1:0
})
,.arlen({
h2f_ARLEN[3:0] // 3:0
})
,.awsize({
h2f_AWSIZE[2:0] // 2:0
})
,.awlen({
h2f_AWLEN[3:0] // 3:0
})
,.bready({
h2f_BREADY[0:0] // 0:0
})
,.awid({
h2f_AWID[11:0] // 11:0
})
,.rdata({
h2f_RDATA[127:0] // 127:0
})
,.awready({
h2f_AWREADY[0:0] // 0:0
})
,.arvalid({
h2f_ARVALID[0:0] // 0:0
})
,.wlast({
h2f_WLAST[0:0] // 0:0
})
,.awprot({
h2f_AWPROT[2:0] // 2:0
})
,.awaddr({
h2f_AWADDR[29:0] // 29:0
})
,.wid({
h2f_WID[11:0] // 11:0
})
,.awcache({
h2f_AWCACHE[3:0] // 3:0
})
,.arlock({
h2f_ARLOCK[1:0] // 1:0
})
,.awburst({
h2f_AWBURST[1:0] // 1:0
})
,.rready({
h2f_RREADY[0:0] // 0:0
})
,.wstrb({
h2f_WSTRB[15:0] // 15:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cfg_cport_rfifo_map({
18'b000000000000000000 // 17:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
,.cfg_wfifo_cport_map({
16'b0000000000000000 // 15:0
})
,.cfg_cport_type({
12'b000000000000 // 11:0
})
,.cfg_rfifo_cport_map({
16'b0000000000000000 // 15:0
})
,.cfg_port_width({
12'b000000000000 // 11:0
})
,.cfg_cport_wfifo_map({
18'b000000000000000000 // 17:0
})
);
cyclonev_hps_interface_interrupts interrupts(
.irq({
f2h_irq_p1[31:0] // 63:32
,f2h_irq_p0[31:0] // 31:0
})
);
endmodule |
module Computer_System_VGA_Subsystem_avalon_st_adapter_channel_adapter_0
(
// Interface: in
output reg in_ready,
input in_valid,
input [30-1: 0] in_data,
input [2-1: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [30-1: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: clk
input clk,
// Interface: reset
input reset_n
);
reg out_channel;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = in_channel; //TODO delete this to avoid Quartus warnings
end
endmodule |
module Computer_System_ARM_A9_HPS_hps_io_border(
// memory
output wire [15 - 1 : 0 ] mem_a
,output wire [3 - 1 : 0 ] mem_ba
,output wire [1 - 1 : 0 ] mem_ck
,output wire [1 - 1 : 0 ] mem_ck_n
,output wire [1 - 1 : 0 ] mem_cke
,output wire [1 - 1 : 0 ] mem_cs_n
,output wire [1 - 1 : 0 ] mem_ras_n
,output wire [1 - 1 : 0 ] mem_cas_n
,output wire [1 - 1 : 0 ] mem_we_n
,output wire [1 - 1 : 0 ] mem_reset_n
,inout wire [32 - 1 : 0 ] mem_dq
,inout wire [4 - 1 : 0 ] mem_dqs
,inout wire [4 - 1 : 0 ] mem_dqs_n
,output wire [1 - 1 : 0 ] mem_odt
,output wire [4 - 1 : 0 ] mem_dm
,input wire [1 - 1 : 0 ] oct_rzqin
// hps_io
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TX_CLK
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TXD0
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TXD1
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TXD2
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TXD3
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RXD0
,inout wire [1 - 1 : 0 ] hps_io_emac1_inst_MDIO
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_MDC
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RX_CTL
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TX_CTL
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RX_CLK
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RXD1
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RXD2
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RXD3
,inout wire [1 - 1 : 0 ] hps_io_qspi_inst_IO0
,inout wire [1 - 1 : 0 ] hps_io_qspi_inst_IO1
,inout wire [1 - 1 : 0 ] hps_io_qspi_inst_IO2
,inout wire [1 - 1 : 0 ] hps_io_qspi_inst_IO3
,output wire [1 - 1 : 0 ] hps_io_qspi_inst_SS0
,output wire [1 - 1 : 0 ] hps_io_qspi_inst_CLK
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_CMD
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_D0
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_D1
,output wire [1 - 1 : 0 ] hps_io_sdio_inst_CLK
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_D2
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_D3
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D0
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D1
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D2
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D3
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D4
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D5
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D6
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D7
,input wire [1 - 1 : 0 ] hps_io_usb1_inst_CLK
,output wire [1 - 1 : 0 ] hps_io_usb1_inst_STP
,input wire [1 - 1 : 0 ] hps_io_usb1_inst_DIR
,input wire [1 - 1 : 0 ] hps_io_usb1_inst_NXT
,output wire [1 - 1 : 0 ] hps_io_spim1_inst_CLK
,output wire [1 - 1 : 0 ] hps_io_spim1_inst_MOSI
,input wire [1 - 1 : 0 ] hps_io_spim1_inst_MISO
,output wire [1 - 1 : 0 ] hps_io_spim1_inst_SS0
,input wire [1 - 1 : 0 ] hps_io_uart0_inst_RX
,output wire [1 - 1 : 0 ] hps_io_uart0_inst_TX
,inout wire [1 - 1 : 0 ] hps_io_i2c0_inst_SDA
,inout wire [1 - 1 : 0 ] hps_io_i2c0_inst_SCL
,inout wire [1 - 1 : 0 ] hps_io_i2c1_inst_SDA
,inout wire [1 - 1 : 0 ] hps_io_i2c1_inst_SCL
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO09
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO35
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO40
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO41
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO48
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO53
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO54
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO61
);
assign hps_io_emac1_inst_MDIO = intermediate[1] ? intermediate[0] : 'z;
assign hps_io_qspi_inst_IO0 = intermediate[3] ? intermediate[2] : 'z;
assign hps_io_qspi_inst_IO1 = intermediate[5] ? intermediate[4] : 'z;
assign hps_io_qspi_inst_IO2 = intermediate[7] ? intermediate[6] : 'z;
assign hps_io_qspi_inst_IO3 = intermediate[9] ? intermediate[8] : 'z;
assign hps_io_sdio_inst_CMD = intermediate[11] ? intermediate[10] : 'z;
assign hps_io_sdio_inst_D0 = intermediate[13] ? intermediate[12] : 'z;
assign hps_io_sdio_inst_D1 = intermediate[15] ? intermediate[14] : 'z;
assign hps_io_sdio_inst_D2 = intermediate[17] ? intermediate[16] : 'z;
assign hps_io_sdio_inst_D3 = intermediate[19] ? intermediate[18] : 'z;
assign hps_io_usb1_inst_D0 = intermediate[21] ? intermediate[20] : 'z;
assign hps_io_usb1_inst_D1 = intermediate[23] ? intermediate[22] : 'z;
assign hps_io_usb1_inst_D2 = intermediate[25] ? intermediate[24] : 'z;
assign hps_io_usb1_inst_D3 = intermediate[27] ? intermediate[26] : 'z;
assign hps_io_usb1_inst_D4 = intermediate[29] ? intermediate[28] : 'z;
assign hps_io_usb1_inst_D5 = intermediate[31] ? intermediate[30] : 'z;
assign hps_io_usb1_inst_D6 = intermediate[33] ? intermediate[32] : 'z;
assign hps_io_usb1_inst_D7 = intermediate[35] ? intermediate[34] : 'z;
assign hps_io_spim1_inst_MOSI = intermediate[37] ? intermediate[36] : 'z;
assign hps_io_i2c0_inst_SDA = intermediate[38] ? '0 : 'z;
assign hps_io_i2c0_inst_SCL = intermediate[39] ? '0 : 'z;
assign hps_io_i2c1_inst_SDA = intermediate[40] ? '0 : 'z;
assign hps_io_i2c1_inst_SCL = intermediate[41] ? '0 : 'z;
assign hps_io_gpio_inst_GPIO09 = intermediate[43] ? intermediate[42] : 'z;
assign hps_io_gpio_inst_GPIO35 = intermediate[45] ? intermediate[44] : 'z;
assign hps_io_gpio_inst_GPIO40 = intermediate[47] ? intermediate[46] : 'z;
assign hps_io_gpio_inst_GPIO41 = intermediate[49] ? intermediate[48] : 'z;
assign hps_io_gpio_inst_GPIO48 = intermediate[51] ? intermediate[50] : 'z;
assign hps_io_gpio_inst_GPIO53 = intermediate[53] ? intermediate[52] : 'z;
assign hps_io_gpio_inst_GPIO54 = intermediate[55] ? intermediate[54] : 'z;
assign hps_io_gpio_inst_GPIO61 = intermediate[57] ? intermediate[56] : 'z;
wire [58 - 1 : 0] intermediate;
wire [96 - 1 : 0] floating;
cyclonev_hps_peripheral_emac emac1_inst(
.EMAC_GMII_MDO_I({
hps_io_emac1_inst_MDIO[0:0] // 0:0
})
,.EMAC_GMII_MDO_OE({
intermediate[1:1] // 0:0
})
,.EMAC_PHY_TXD({
hps_io_emac1_inst_TXD3[0:0] // 3:3
,hps_io_emac1_inst_TXD2[0:0] // 2:2
,hps_io_emac1_inst_TXD1[0:0] // 1:1
,hps_io_emac1_inst_TXD0[0:0] // 0:0
})
,.EMAC_CLK_TX({
hps_io_emac1_inst_TX_CLK[0:0] // 0:0
})
,.EMAC_PHY_RXDV({
hps_io_emac1_inst_RX_CTL[0:0] // 0:0
})
,.EMAC_PHY_RXD({
hps_io_emac1_inst_RXD3[0:0] // 3:3
,hps_io_emac1_inst_RXD2[0:0] // 2:2
,hps_io_emac1_inst_RXD1[0:0] // 1:1
,hps_io_emac1_inst_RXD0[0:0] // 0:0
})
,.EMAC_GMII_MDO_O({
intermediate[0:0] // 0:0
})
,.EMAC_GMII_MDC({
hps_io_emac1_inst_MDC[0:0] // 0:0
})
,.EMAC_PHY_TX_OE({
hps_io_emac1_inst_TX_CTL[0:0] // 0:0
})
,.EMAC_CLK_RX({
hps_io_emac1_inst_RX_CLK[0:0] // 0:0
})
);
cyclonev_hps_peripheral_qspi qspi_inst(
.QSPI_MO2({
intermediate[6:6] // 0:0
})
,.QSPI_MI3({
hps_io_qspi_inst_IO3[0:0] // 0:0
})
,.QSPI_MO1({
intermediate[4:4] // 0:0
})
,.QSPI_MO0({
intermediate[2:2] // 0:0
})
,.QSPI_MI2({
hps_io_qspi_inst_IO2[0:0] // 0:0
})
,.QSPI_MI1({
hps_io_qspi_inst_IO1[0:0] // 0:0
})
,.QSPI_MI0({
hps_io_qspi_inst_IO0[0:0] // 0:0
})
,.QSPI_MO_EN_N({
intermediate[9:9] // 3:3
,intermediate[7:7] // 2:2
,intermediate[5:5] // 1:1
,intermediate[3:3] // 0:0
})
,.QSPI_SS_N({
hps_io_qspi_inst_SS0[0:0] // 0:0
})
,.QSPI_SCLK({
hps_io_qspi_inst_CLK[0:0] // 0:0
})
,.QSPI_MO3({
intermediate[8:8] // 0:0
})
);
cyclonev_hps_peripheral_sdmmc sdio_inst(
.SDMMC_DATA_I({
hps_io_sdio_inst_D3[0:0] // 3:3
,hps_io_sdio_inst_D2[0:0] // 2:2
,hps_io_sdio_inst_D1[0:0] // 1:1
,hps_io_sdio_inst_D0[0:0] // 0:0
})
,.SDMMC_CMD_O({
intermediate[10:10] // 0:0
})
,.SDMMC_CCLK({
hps_io_sdio_inst_CLK[0:0] // 0:0
})
,.SDMMC_DATA_O({
intermediate[18:18] // 3:3
,intermediate[16:16] // 2:2
,intermediate[14:14] // 1:1
,intermediate[12:12] // 0:0
})
,.SDMMC_CMD_OE({
intermediate[11:11] // 0:0
})
,.SDMMC_CMD_I({
hps_io_sdio_inst_CMD[0:0] // 0:0
})
,.SDMMC_DATA_OE({
intermediate[19:19] // 3:3
,intermediate[17:17] // 2:2
,intermediate[15:15] // 1:1
,intermediate[13:13] // 0:0
})
);
cyclonev_hps_peripheral_usb usb1_inst(
.USB_ULPI_STP({
hps_io_usb1_inst_STP[0:0] // 0:0
})
,.USB_ULPI_DATA_I({
hps_io_usb1_inst_D7[0:0] // 7:7
,hps_io_usb1_inst_D6[0:0] // 6:6
,hps_io_usb1_inst_D5[0:0] // 5:5
,hps_io_usb1_inst_D4[0:0] // 4:4
,hps_io_usb1_inst_D3[0:0] // 3:3
,hps_io_usb1_inst_D2[0:0] // 2:2
,hps_io_usb1_inst_D1[0:0] // 1:1
,hps_io_usb1_inst_D0[0:0] // 0:0
})
,.USB_ULPI_NXT({
hps_io_usb1_inst_NXT[0:0] // 0:0
})
,.USB_ULPI_DIR({
hps_io_usb1_inst_DIR[0:0] // 0:0
})
,.USB_ULPI_DATA_O({
intermediate[34:34] // 7:7
,intermediate[32:32] // 6:6
,intermediate[30:30] // 5:5
,intermediate[28:28] // 4:4
,intermediate[26:26] // 3:3
,intermediate[24:24] // 2:2
,intermediate[22:22] // 1:1
,intermediate[20:20] // 0:0
})
,.USB_ULPI_CLK({
hps_io_usb1_inst_CLK[0:0] // 0:0
})
,.USB_ULPI_DATA_OE({
intermediate[35:35] // 7:7
,intermediate[33:33] // 6:6
,intermediate[31:31] // 5:5
,intermediate[29:29] // 4:4
,intermediate[27:27] // 3:3
,intermediate[25:25] // 2:2
,intermediate[23:23] // 1:1
,intermediate[21:21] // 0:0
})
);
cyclonev_hps_peripheral_spi_master spim1_inst(
.SPI_MASTER_RXD({
hps_io_spim1_inst_MISO[0:0] // 0:0
})
,.SPI_MASTER_TXD({
intermediate[36:36] // 0:0
})
,.SPI_MASTER_SSI_OE_N({
intermediate[37:37] // 0:0
})
,.SPI_MASTER_SCLK({
hps_io_spim1_inst_CLK[0:0] // 0:0
})
,.SPI_MASTER_SS_0_N({
hps_io_spim1_inst_SS0[0:0] // 0:0
})
);
cyclonev_hps_peripheral_uart uart0_inst(
.UART_RXD({
hps_io_uart0_inst_RX[0:0] // 0:0
})
,.UART_TXD({
hps_io_uart0_inst_TX[0:0] // 0:0
})
);
cyclonev_hps_peripheral_i2c i2c0_inst(
.I2C_DATA({
hps_io_i2c0_inst_SDA[0:0] // 0:0
})
,.I2C_CLK({
hps_io_i2c0_inst_SCL[0:0] // 0:0
})
,.I2C_DATA_OE({
intermediate[38:38] // 0:0
})
,.I2C_CLK_OE({
intermediate[39:39] // 0:0
})
);
cyclonev_hps_peripheral_i2c i2c1_inst(
.I2C_DATA({
hps_io_i2c1_inst_SDA[0:0] // 0:0
})
,.I2C_CLK({
hps_io_i2c1_inst_SCL[0:0] // 0:0
})
,.I2C_DATA_OE({
intermediate[40:40] // 0:0
})
,.I2C_CLK_OE({
intermediate[41:41] // 0:0
})
);
cyclonev_hps_peripheral_gpio gpio_inst(
.GPIO1_PORTA_I({
hps_io_gpio_inst_GPIO54[0:0] // 25:25
,hps_io_gpio_inst_GPIO53[0:0] // 24:24
,floating[3:0] // 23:20
,hps_io_gpio_inst_GPIO48[0:0] // 19:19
,floating[9:4] // 18:13
,hps_io_gpio_inst_GPIO41[0:0] // 12:12
,hps_io_gpio_inst_GPIO40[0:0] // 11:11
,floating[13:10] // 10:7
,hps_io_gpio_inst_GPIO35[0:0] // 6:6
,floating[19:14] // 5:0
})
,.GPIO1_PORTA_OE({
intermediate[55:55] // 25:25
,intermediate[53:53] // 24:24
,floating[23:20] // 23:20
,intermediate[51:51] // 19:19
,floating[29:24] // 18:13
,intermediate[49:49] // 12:12
,intermediate[47:47] // 11:11
,floating[33:30] // 10:7
,intermediate[45:45] // 6:6
,floating[39:34] // 5:0
})
,.GPIO2_PORTA_O({
intermediate[56:56] // 3:3
,floating[42:40] // 2:0
})
,.GPIO0_PORTA_O({
intermediate[42:42] // 9:9
,floating[51:43] // 8:0
})
,.GPIO2_PORTA_I({
hps_io_gpio_inst_GPIO61[0:0] // 3:3
,floating[54:52] // 2:0
})
,.GPIO2_PORTA_OE({
intermediate[57:57] // 3:3
,floating[57:55] // 2:0
})
,.GPIO0_PORTA_I({
hps_io_gpio_inst_GPIO09[0:0] // 9:9
,floating[66:58] // 8:0
})
,.GPIO0_PORTA_OE({
intermediate[43:43] // 9:9
,floating[75:67] // 8:0
})
,.GPIO1_PORTA_O({
intermediate[54:54] // 25:25
,intermediate[52:52] // 24:24
,floating[79:76] // 23:20
,intermediate[50:50] // 19:19
,floating[85:80] // 18:13
,intermediate[48:48] // 12:12
,intermediate[46:46] // 11:11
,floating[89:86] // 10:7
,intermediate[44:44] // 6:6
,floating[95:90] // 5:0
})
);
hps_sdram hps_sdram_inst(
.mem_dq({
mem_dq[31:0] // 31:0
})
,.mem_odt({
mem_odt[0:0] // 0:0
})
,.mem_ras_n({
mem_ras_n[0:0] // 0:0
})
,.mem_dqs_n({
mem_dqs_n[3:0] // 3:0
})
,.mem_dqs({
mem_dqs[3:0] // 3:0
})
,.mem_dm({
mem_dm[3:0] // 3:0
})
,.mem_we_n({
mem_we_n[0:0] // 0:0
})
,.mem_cas_n({
mem_cas_n[0:0] // 0:0
})
,.mem_ba({
mem_ba[2:0] // 2:0
})
,.mem_a({
mem_a[14:0] // 14:0
})
,.mem_cs_n({
mem_cs_n[0:0] // 0:0
})
,.mem_ck({
mem_ck[0:0] // 0:0
})
,.mem_cke({
mem_cke[0:0] // 0:0
})
,.oct_rzqin({
oct_rzqin[0:0] // 0:0
})
,.mem_reset_n({
mem_reset_n[0:0] // 0:0
})
,.mem_ck_n({
mem_ck_n[0:0] // 0:0
})
);
endmodule |
module Computer_System_mm_interconnect_1_rsp_demux_003
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [129-1 : 0] sink_data, // ST_DATA_W=129
input [9-1 : 0] sink_channel, // ST_CHANNEL_W=9
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [129-1 : 0] src0_data, // ST_DATA_W=129
output reg [9-1 : 0] src0_channel, // ST_CHANNEL_W=9
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [129-1 : 0] src1_data, // ST_DATA_W=129
output reg [9-1 : 0] src1_channel, // ST_CHANNEL_W=9
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [129-1 : 0] src2_data, // ST_DATA_W=129
output reg [9-1 : 0] src2_channel, // ST_CHANNEL_W=9
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 3;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module Computer_System_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 2
)
(output [212 - 211 : 0] default_destination_id,
output [5-1 : 0] default_wr_channel,
output [5-1 : 0] default_rd_channel,
output [5-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[212 - 211 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module Computer_System_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [237-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [237-1 : 0] src_data,
output reg [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 175;
localparam PKT_ADDR_L = 144;
localparam PKT_DEST_ID_H = 212;
localparam PKT_DEST_ID_L = 211;
localparam PKT_PROTECTION_H = 227;
localparam PKT_PROTECTION_L = 225;
localparam ST_DATA_W = 237;
localparam ST_CHANNEL_W = 5;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 178;
localparam PKT_TRANS_READ = 179;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h4000000 - 64'h0);
localparam PAD1 = log2ceil(64'h8040000 - 64'h8000000);
localparam PAD2 = log2ceil(64'h9002000 - 64'h9000000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h9002000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [5-1 : 0] default_src_channel;
Computer_System_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x4000000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 28'h0 ) begin
src_channel = 5'b010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x8000000 .. 0x8040000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 28'h8000000 ) begin
src_channel = 5'b100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x9000000 .. 0x9002000 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 28'h9000000 ) begin
src_channel = 5'b001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module sv_xcvr_data_adapter #(
parameter lanes = 1, //Number of lanes chosen by user. legal value: 1+
parameter channel_interface = 0, //legal value: (0,1) 1-Enable channel reconfiguration
parameter ser_base_factor = 8, // (8,10)
parameter ser_words = 1, // (1,2,4)
parameter skip_word = 1 // (1,2)
) (
input wire [(channel_interface? 44: ser_base_factor*ser_words)*lanes-1:0] tx_parallel_data,
input wire [ser_words*lanes -1:0] tx_datak,
input tri0 [ser_words*lanes -1:0] tx_forcedisp,
input wire [ser_words*lanes -1:0] tx_dispval,
output tri0 [64*lanes -1:0] tx_datain_from_pld,
input tri0 [64*lanes -1:0] rx_dataout_to_pld,
output wire [(channel_interface? 64: ser_base_factor*ser_words)*lanes-1:0] rx_parallel_data,
output wire [ser_words*lanes -1:0] rx_datak,
output wire [ser_words*lanes -1:0] rx_errdetect,
output wire [ser_words*lanes -1:0] rx_syncstatus,
output wire [ser_words*lanes -1:0] rx_disperr,
output wire [ser_words*lanes -1:0] rx_patterndetect,
output wire [ser_words*lanes -1:0] rx_rmfifodatainserted,
output wire [ser_words*lanes -1:0] rx_rmfifodatadeleted,
output wire [ser_words*lanes -1:0] rx_runningdisp,
output wire [ser_words*lanes -1:0] rx_a1a2sizeout
);
localparam tx_data_bundle_size = 11; // TX PLD to PCS interface groups data and control in 11-bit bundles
localparam rx_data_bundle_size = 16; // RX PCS to PLD interface groups data and status in 16-bit bundles
generate begin
genvar num_ch;
genvar num_word;
for (num_ch=0; num_ch < lanes; num_ch = num_ch + 1) begin:channel
if (channel_interface == 0) begin
for (num_word=0; num_word < ser_words; num_word=num_word+1) begin:word
//***************************************************************
//*********************** TX assignments ************************
//With 8B/10B enabled, Tx datain from PLD to PCS has 8-bit data + 3 controls in 11-bit bundles
//For 1 lane, [7:0] = data
// [8] = k char
// [9] = force disparity
// [10] = disparity value (Tx Elec Idle for PIPE Gen1 & 2)
assign tx_datain_from_pld[64*num_ch+num_word*tx_data_bundle_size*skip_word +: ser_base_factor] = tx_parallel_data[ser_base_factor*ser_words*num_ch+num_word*ser_base_factor +: ser_base_factor];
if (ser_base_factor == 8) begin
assign tx_datain_from_pld[64*num_ch+num_word*tx_data_bundle_size*skip_word + 8] = tx_datak [ser_words*num_ch+num_word];
assign tx_datain_from_pld[64*num_ch+num_word*tx_data_bundle_size*skip_word + 9] = tx_forcedisp [ser_words*num_ch+num_word];
assign tx_datain_from_pld[64*num_ch+num_word*tx_data_bundle_size*skip_word + 10] = tx_dispval [ser_words*num_ch+num_word];
end
//***************************************************************
//*********************** RX assignments ************************
//With 8B/10B enabled, Rx dataout from PCS to PLD has 8-bit data + 8 controls in 16-bit bundles
//For 1 lane, [7:0] = data
// [8] = k char
// [9] = code violation
// [10] = word aligner status
// [11] = disparity error
// [12] = pattern detect
// [14:13] = rate match FIFO status
// [15] = running disparity
assign rx_parallel_data[ser_base_factor*ser_words*num_ch+num_word*ser_base_factor +: ser_base_factor]
= rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word +: ser_base_factor];
assign rx_datak [ser_words*num_ch+num_word] = rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 8];
assign rx_errdetect [ser_words*num_ch+num_word] = rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 9];
assign rx_syncstatus [ser_words*num_ch+num_word] = rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 10];
assign rx_disperr [ser_words*num_ch+num_word] = rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 11];
assign rx_patterndetect[ser_words*num_ch+num_word] = rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 12];
// rate-match FIFO status is encoded as 2 bits at offsets 13,14 within a bundle
// 00: Normal data, 01: Deletion, 10: Insertion (or Underflow with 9'h1FE or 9'h1F7), 11: Overflow
assign rx_rmfifodatainserted[ser_words*num_ch+num_word] = rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 14]
& ~rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 13];
assign rx_rmfifodatadeleted [ser_words*num_ch+num_word] = ~rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 14]
& rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 13];
assign rx_runningdisp [ser_words*num_ch+num_word] = rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 15];
assign rx_a1a2sizeout [ser_words*num_ch+num_word] = rx_dataout_to_pld[64*num_ch+num_word*rx_data_bundle_size*skip_word + 8];
end //for word
end
else begin
assign tx_datain_from_pld [64*num_ch +: 44] = tx_parallel_data [44*num_ch +: 44];
assign tx_datain_from_pld [64*num_ch+44 +: 20] = {20{1'b0}};
assign rx_parallel_data [64*num_ch +: 64] = rx_dataout_to_pld[64*num_ch +: 64];
// Drive unused outputs
assign rx_datak = {(ser_words*lanes){1'b0}};
assign rx_errdetect = {(ser_words*lanes){1'b0}};
assign rx_syncstatus = {(ser_words*lanes){1'b0}};
assign rx_disperr = {(ser_words*lanes){1'b0}};
assign rx_patterndetect = {(ser_words*lanes){1'b0}};
assign rx_rmfifodatainserted = {(ser_words*lanes){1'b0}};
assign rx_rmfifodatadeleted = {(ser_words*lanes){1'b0}};
assign rx_runningdisp = {(ser_words*lanes){1'b0}};
assign rx_a1a2sizeout = {(ser_words*lanes){1'b0}};
end
end //for channel
end
endgenerate
endmodule |
module alt_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming. Must be >1
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0, // See description above
parameter INIT_VALUE = 0
) (
input wire clk,
input wire reset,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 1) ? SYNC_CHAIN_LENGTH : 2;
localparam [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
(* altera_attribute = "disable_da_rule=D103" *)
reg [INT_LEN-1:0] sync_r = L_INIT_VALUE;
assign q[ig] = sync_r[INT_LEN-1]; // Output signal
always @(posedge clk or posedge reset)
if(reset)
sync_r <= L_INIT_VALUE;
else
sync_r <= {sync_r[INT_LEN-2:0],d_in};
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r = L_INIT_VALUE[0];
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule |
module altera_tse_reset_sequencer
#(
parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
)
(
// User inputs and outputs
input wire clock,
input wire reset_all,
input wire reset_tx_digital,
input wire reset_rx_digital,
input wire powerdown_all,
output wire tx_ready,
output wire rx_ready,
// I/O to Stratix IV transceiver control & status
output wire pll_powerdown, // reset TX PLL
output wire tx_digitalreset, // reset TX PCS
output wire rx_analogreset, // reset RX PMA
output wire rx_digitalreset, // reset RX PCS
output wire gxb_powerdown, // powerdown whole quad
input wire pll_is_locked, // TX PLL is locked status
input wire rx_oc_busy, // RX channel offset cancellation status
input wire rx_is_lockedtodata, // RX CDR PLL is locked to data status
input wire manual_mode // 0=Automatically reset RX after loss of rx_is_lockedtodata
);
localparam clk_in_mhz =
`ifdef QUARTUS__SIMGEN
2; // simulation-only value
`elsif ALTERA_RESERVED_QIS
sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
`else
2; // simulation-only value
`endif
localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
wire pll_is_locked_r; // pll_is_locked resynchronized
wire rx_oc_busy_r; // rx_oc_busy resynchronized
wire rx_is_lockedtodata_r; // rx_is_lockedtodata resynchronized
wire manual_mode_r; // manual_mode resynchonized
wire sdone_lego_pll_powerdown; // 'sequence done' output of pll_powerdown lego
wire sdone_lego_tx_digitalreset;// 'sequence done' output of tx_digitalreset lego
wire sdone_lego_rx_digitalreset;// 'sequence done' output of rx_digitalreset lego
wire sdone_lego_rx_analogreset; // 'sequence done' output of rx_analogreset lego
wire wire_tx_digital_only_reset;// reset output for TX digital-only
wire wire_rx_digital_only_reset;// reset output for RX digital-only
wire wire_tx_digitalreset; // TX digital full-reset source
wire wire_rx_digitalreset; // RX digital full-reset source
wire wire_rx_digital_retrigger; // Trigger new RX digital sequence after main sequence completes, and lose lock-to-data
// Resynchronize input signals
altera_tse_xcvr_resync #(
.WIDTH(4)
) altera_tse_xcvr_resync_inst (
.clk (clock),
.d ({pll_is_locked ,rx_oc_busy ,rx_is_lockedtodata ,manual_mode }),
.q ({pll_is_locked_r,rx_oc_busy_r,rx_is_lockedtodata_r,manual_mode_r})
);
// First reset ctrl sequencer lego is for pll_powerdown generation
altera_tse_reset_ctrl_lego #(
.reset_hold_cycles(t_pll_powerdown) // hold pll_powerdown for 1us
) lego_pll_powerdown ( .clock(clock),
.start(reset_all), // Do not use resynched version of reset_all here
.aclr(powerdown_all),
.reset(pll_powerdown),
.rdone(pll_is_locked_r),
.sdone(sdone_lego_pll_powerdown));
// next reset ctrl sequencer lego is for tx_digitalreset generation
altera_tse_reset_ctrl_lego #(
.reset_hold_til_rdone(1) // hold until rdone arrives for this test case
) lego_tx_digitalreset ( .clock(clock),
.start(reset_all),
.aclr(powerdown_all),
.reset(wire_tx_digitalreset),
.rdone(sdone_lego_pll_powerdown),
.sdone(sdone_lego_tx_digitalreset));
// next reset ctrl sequencer lego is for rx_analogreset generation
altera_tse_reset_ctrl_lego #(
.reset_hold_til_rdone(1), // hold until rdone arrives for this test case
.sdone_delay_cycles(2) // hold rx_analogreset 2 parallel_clock cycles after offset cancellation done
) lego_rx_analogreset ( .clock(clock),
.start(reset_all),
.aclr(powerdown_all),
.reset(rx_analogreset),
.rdone(sdone_lego_tx_digitalreset & ~rx_oc_busy_r),
.sdone(sdone_lego_rx_analogreset));
// last reset ctrl sequencer lego is for rx_digitalreset generation
altera_tse_reset_ctrl_lego #(
.reset_hold_til_rdone(1), // hold until rdone arrives for this test case
.sdone_delay_cycles(t_ltd_auto) // hold rx_digitalreset for 4us
) lego_rx_digitalreset ( .clock(clock),
.start(~manual_mode & reset_all | wire_rx_digital_retrigger),
.aclr(powerdown_all),
.reset(wire_rx_digitalreset),
.rdone(sdone_lego_rx_analogreset & rx_is_lockedtodata_r),
.sdone(sdone_lego_rx_digitalreset));
//////////// digital-only reset ////////////
// separate reset ctrl sequencer lego for digital-only reset generation
altera_tse_reset_ctrl_lego #(
.reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
) lego_tx_digitalonly ( .clock(clock),
.start(reset_tx_digital | reset_all),
.aclr(powerdown_all),
.reset(wire_tx_digital_only_reset),
.rdone(sdone_lego_tx_digitalreset),
.sdone(tx_ready)); // TX status indicator for user
altera_tse_reset_ctrl_lego #(
.reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
) lego_rx_digitalonly ( .clock(clock),
.start(reset_rx_digital | (reset_all & ~manual_mode) | wire_rx_digital_retrigger),
.aclr(powerdown_all),
.reset(wire_rx_digital_only_reset),
.rdone(sdone_lego_rx_digitalreset),
.sdone(rx_ready)); // RX status indicator for user
// digital resets have 2 possible sources: full-reset or digital-only
assign tx_digitalreset = wire_tx_digitalreset | wire_tx_digital_only_reset;
assign rx_digitalreset = wire_rx_digitalreset | wire_rx_digital_only_reset;
// re-trigger RX digital sequence when main sequence is complete (indicated by sdone_lego_rx_digitalreset)
// not manual mode, and lose lock-to-data
assign wire_rx_digital_retrigger = ~manual_mode & sdone_lego_rx_digitalreset & ~rx_is_lockedtodata_r;
// Quad power-down
assign gxb_powerdown = powerdown_all;
////////////////////////
// general assertions
//synopsys translate_off
// vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
`ifdef ALTERA_XCVR_ASSERTIONS
always @(posedge clock) begin
// reset_all starts by triggering CMU PLL powerdown
assert property ($rose(reset_all) |=> $rose(pll_powerdown));
// While CMU PLL powerdown is asserted, all other resets must be asserted
assert property (pll_powerdown |-> (tx_digitalreset & rx_analogreset & rx_digitalreset));
// While rx_analogreset is asserted, rx_digitalreset must be asserted
assert property (rx_analogreset |-> rx_digitalreset);
// When pll_is_locked is asserted, tx_digitalreset must be deasserted
assert property ($rose(pll_is_locked_r) |-> ##[0:2] !tx_digitalreset);
// During a reset, rx_digitalreset should remain high for t_ltd_auto after rx_is_lockedtodata rising edge
assert property ($rose(rx_is_lockedtodata_r) |-> rx_digitalreset [*(t_ltd_auto+1)] ##1 !rx_digitalreset);
// reset_tx_digital results in only a brief pulse on tx_digitalreset
assert property ($rose(reset_tx_digital) |=> tx_digitalreset [*3] );
assert property ($rose(reset_tx_digital) & tx_ready |=> tx_digitalreset [*3] ##1 ~tx_digitalreset ##1 $rose(tx_ready) );
// reset_rx_digital results in only a brief pulse on rx_digitalreset
assert property ($rose(reset_rx_digital) |=> rx_digitalreset [*3] );
assert property ($rose(reset_rx_digital) & rx_ready |=> rx_digitalreset [*3] ##1 ~rx_digitalreset ##1 $rose(rx_ready) );
end
`endif
//synopsys translate_on
endmodule |
module alt_xcvr_mgmt2dec (
// user-visible external management interface
input wire mgmt_clk_reset,
input wire mgmt_clk,
input wire [8:0] mgmt_address,
input wire mgmt_read,
output reg [31:0] mgmt_readdata = ~32'd0,
output reg mgmt_waitrequest = 0,
input wire mgmt_write,
// internal interface to 'top' csr block
output wire [7:0] topcsr_address,
output wire topcsr_read,
input wire [31:0] topcsr_readdata,
input wire topcsr_waitrequest,
output wire topcsr_write,
// internal interface to 'top' csr block
output wire [7:0] reconf_address,
output wire reconf_read,
input wire [31:0] reconf_readdata,
input wire reconf_waitrequest,
output wire reconf_write
);
localparam width_swa = 7; // word address width of interface to slaves (2 for top.CSR and 1 for reconfig)
localparam dec_count = 2; // count of the total number of sub-components that can act
// as slaves to the mgmt interface
localparam dec_topcsr = 0; // uses 2 128-word address blocks
localparam dec_reconf = 1; // uses 1 128-word address block
///////////////////////////////////////////////////////////////////////
// Decoder for multiple slaves of reconfig_mgmt interface
///////////////////////////////////////////////////////////////////////
wire [dec_count-1:0] r_decode;
assign r_decode =
(mgmt_address[8:width_swa+1] == dec_topcsr) ? (({dec_count-dec_topcsr{1'b0}} | 1'b1) << dec_topcsr)
: (mgmt_address[8:width_swa] == 2'd2) ? (({dec_count-dec_reconf{1'b0}} | 1'b1) << dec_reconf)
: {dec_count{1'b0}};
// reconfig_mgmt output generation is muxing of decoded slave output
always @(*) begin
if (r_decode[dec_topcsr] == 1'b1) begin
mgmt_readdata = topcsr_readdata;
mgmt_waitrequest = topcsr_waitrequest;
end else if (r_decode[dec_reconf] == 1'b1) begin
mgmt_readdata = reconf_readdata;
mgmt_waitrequest = reconf_waitrequest;
end else begin
mgmt_readdata = -1;
mgmt_waitrequest = 1'b0;
end
end
// internal interface to 'top' csr block
assign topcsr_address = mgmt_address[width_swa:0]; // top.csr uses 2 128-word blocks
assign topcsr_read = mgmt_read & r_decode[dec_topcsr];
assign topcsr_write = mgmt_write & r_decode[dec_topcsr];
// internal interface to 'top' csr block
assign reconf_address = mgmt_address[width_swa-1:0]; // reconfig uses 1 128-word block
assign reconf_read = mgmt_read & r_decode[dec_reconf];
assign reconf_write = mgmt_write & r_decode[dec_reconf];
endmodule |
module altera_tse_reset_ctrl_lego
#(
parameter reset_hold_til_rdone = 0, // 1 means reset stays high until rdone arrives
// 0 means fixed pulse length, defined by reset_hold_cycles
parameter reset_hold_cycles = 1, // reset pulse length in clock cycles
parameter sdone_delay_cycles = 0, // optional delay from rdone received til sdone sent to next block
parameter rdone_is_edge_sensitive = 0 // default is level sensitive rdone
)
(
// clocks and PLLs
input wire clock,
input wire start,
input wire aclr, // active-high asynchronous reset
output wire reset,
input wire rdone, // reset done signal
output reg sdone // sequence done for this lego
);
localparam max_precision = 32; // VCS requires this declaration outside the function
function integer ceil_log2;
input [max_precision-1:0] input_num;
integer i;
reg [max_precision-1:0] try_result;
begin
i = 0;
try_result = 1;
while ((try_result << i) < input_num && i < max_precision)
i = i + 1;
ceil_log2 = i;
end
endfunction
// How many bits are needed for 'reset_hold_cycles' counter?
localparam rhc_bits = ceil_log2(reset_hold_cycles);
localparam rhc_load_constant = (1 << rhc_bits) | (reset_hold_cycles-1);
// How many bits are needed for 'sdone_delay_cycles' counter?
localparam sdc_bits = ceil_log2(sdone_delay_cycles);
localparam sdc_load_constant = (1 << sdc_bits)
| ((rdone_is_edge_sensitive == 1 && sdone_delay_cycles > 1) ? sdone_delay_cycles-2 : sdone_delay_cycles-1);
localparam sdone_stable_cycles = (sdone_delay_cycles > 1 ? sdone_delay_cycles+1 : 0);
wire spulse; // synchronous detection of 'start' 0-to-1 transition
wire rhold;
wire timed_reset_in_progress;
wire rinit_next; // combinatorial input to rinit DFF
wire rdonei; // internal selector between rdone and rdsave (rdone_is_edge_sensitive==1)
wire rdpulse; // synchronous detection of 'rdone' 0-to-1 transition, when rdone_is_edge_sensitive==1
reg zstart; // delayed value of 'start' input, used for detection of 0-to-1 transition
reg rinit; // state bit that indicates sequence is in progress
// 'start' input, detect 0-to-1 transition that triggers sequence
assign spulse = start & ~zstart;
always @(posedge clock or posedge aclr)
if (aclr == 1'b1)
zstart <= 0;
else
zstart <= start;
// rinit state bit, triggered by spulse, waits while rhold = 1
assign rinit_next = spulse | (rinit & (rhold | ~rdonei | rdpulse)) | timed_reset_in_progress;
always @(posedge clock or posedge aclr)
if (aclr == 1'b1)
rinit <= 1;
else
rinit <= rinit_next;
// optional internal 'rdone' generation logic, if rdone_is_edge_sensitive==1
generate
if (rdone_is_edge_sensitive == 0) begin
assign rdpulse = 0;
assign rdonei = rdone;
end
else begin
// instantiate synchronous edge-detection logic for rdone
reg zrdone; // for edge-sensitive rdone, detect 0-to-1 transition synchronously
reg rdsave; // for edge-sensitive rdone, use this as internal rdone
always @(posedge clock or posedge aclr) begin
if (aclr == 1'b1) begin
zrdone <= 0;
rdsave <= 0;
end
else begin
zrdone <= rdone; // previous value of rdone for synchronous edge detection
rdsave <= ~spulse & (rdpulse | rdsave);
end
end
assign rdpulse = rdone & ~zrdone;
assign rdonei = rdsave;
end
endgenerate
// rhold depends on sdone_delay_cycles and rdone_is_edge_sensitive
generate
if (sdone_delay_cycles == 0 || (sdone_delay_cycles == 1 && rdone_is_edge_sensitive == 1))
assign rhold = ~rdonei; // sdone_delay_cycles=0
else begin
// declare only when needed to avoid Quartus synthesis warnings
reg [sdc_bits:0] rhold_reg; // for sdone_delay_cycles > 0
if (sdone_delay_cycles == 1) begin
always @(posedge clock or posedge aclr) begin
if (aclr == 1'b1)
rhold_reg <= 0;
else
rhold_reg <= ~(rinit & rdonei);
end
assign rhold = rhold_reg[0]; // sdone_delay_cycles=1
end
else begin
// need to count cycles to make sure rdone is stable
always @(posedge clock or posedge aclr)
begin
if (aclr == 1'b1)
rhold_reg <= 0;
else if ((rinit & rdonei & ~rdpulse) == 0)
// keep load value until rinit & rdone both high, and no new rdone pulses
rhold_reg <= sdc_load_constant[sdc_bits:0];
else
rhold_reg <= rhold_reg - 1'b1;
end
assign rhold = rhold_reg[sdc_bits]; // sdone_delay_cycles > 1
end
end
endgenerate
// sdone state bit indicates that reset sequence completed. Clear again on 'start'
always @(posedge clock or posedge aclr)
if (aclr == 1'b1)
sdone <= 0;
else
sdone <= ~spulse & (sdone | (rinit & ~rinit_next));
// reset pulse generation logic depends on 2 parameters
generate
if (reset_hold_til_rdone == 1) begin
assign reset = rinit;
assign timed_reset_in_progress = 0;
end
else if (reset_hold_cycles < 1) begin // 0 is legal, but catch negative (illegal) values too
assign reset = spulse;
assign timed_reset_in_progress = 0;
end
else begin
// declare only when needed to avoid Quartus synthesis warnings
reg [rhc_bits:0] zspulse; // bits for reset pulse if fixed length
assign timed_reset_in_progress = zspulse[rhc_bits];
assign reset = zspulse[rhc_bits];
if (reset_hold_cycles == 1)
// a single-cycle reset pulse needs 1 register
always @(posedge clock or posedge aclr)
if (aclr == 1'b1)
zspulse <= 1;
else
zspulse <= spulse;
else begin
// multi-cycle reset pulse needs a counter
always @(posedge clock or posedge aclr)
begin
if (aclr == 1'b1)
zspulse <= {rhc_bits + 1 { 1'b1}};
else if (spulse == 1)
zspulse <= rhc_load_constant[rhc_bits:0];
else if (zspulse[rhc_bits] == 1)
zspulse <= zspulse - 1'b1;
end
end
end
endgenerate
// generate
// case (reset_hold_til_rdone)
// 0 : m1 U1 (a, b, c);
// 2 : m2 U1 (a, b, c);
// default : m3 U1 (a, b, c);
// endcase
// endgenerate
// general assertions
//synopsys translate_off
// vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
`ifdef ALTERA_XCVR_ASSERTIONS
// when rdone is edge sensitive, last rdone +ve edge triggers sdone +ve edge,
// 'sdone_delay_cycles' later. "##1 1" is an always-true cycle to match $rise(sdone)
sequence rdone_last_edge;
@(posedge clock) $rose(rdone) ##1 !$rose(rdone) [*sdone_delay_cycles] ##1 1;
endsequence
// when rdone is level sensitive, stable rdone for 'sdone_delay_cycles' consecutive cycles
// triggers sdone +ve edge. "##1 1" is an always-true cycle to match $rise(sdone)
sequence rdone_stable_level;
@(posedge clock) rdone [*(sdone_delay_cycles+1)] ##1 1;
endsequence
// Most assertions aren't valid when 'aclr' is active
//`define assert_awake(arg) assert property (disable iff (aclr) arg )
always @(aclr)
if (aclr) $assertkill;
else $asserton;
generate
always @(posedge clock) begin
// A rising edge on start will result in reset high within 1 clock cycle
assert property ($rose(start & ~aclr) |-> ##[0:1] reset);
// A rising edge on reset will result in sdone low within 1 clock cycle
assert property ($rose(reset) |-> ##[0:1] !sdone);
// assertions for optional behavior: reset pulse length options
if (reset_hold_til_rdone == 0 && reset_hold_cycles > 1)
// Verify fixed-length reset pulse option
assert property ($rose(reset) |-> reset [*reset_hold_cycles] ##1 !reset)
else $error("Reset pulse length should be %d", reset_hold_cycles);
if (reset_hold_til_rdone == 0 && reset_hold_cycles == 1)
// Verify fixed 1-length reset pulse option
assert property ($rose(reset) |=> !reset);
if (reset_hold_til_rdone == 0 && reset_hold_cycles == 0)
// Verify minimal-length reset pulse option, which mirrors 'start' edge detection
assert property ($rose(start & ~aclr) |-> reset ##1 !reset);
if (reset_hold_til_rdone == 1) begin
// with hold-til-rdone, reset should not deassert until after rdone asserts, then deassert immediately
assert property ($rose(reset) && !rdone |=> $stable(reset) [*0:$] ##1 (reset && rdone) ##1 !reset);
assert property ($rose(reset) && rdone ##1 rdone [*sdone_delay_cycles] |=> !reset); // rdone was already high
//assert property ($rose(reset) && !rdone |-> ##[0:$] rdone ##1 !reset);
end
// assertions for optional behavior: sdone delay options and rdone edge sensitive option
if (rdone_is_edge_sensitive == 1)
// rdone edge-sensitive option only has an effect when sdone_delay_cycles > 0
assert property ($rose(sdone) |-> rdone_last_edge.ended);
if (rdone_is_edge_sensitive == 0)
// rdone defaults to level-sensitive
assert property ($rose(sdone) |-> (rdone_stable_level.ended or $past($fell(reset),1)));
end
endgenerate
`endif // ALTERA_XCVR_ASSERTIONS
//synopsys translate_on
endmodule |
module sv_xcvr_avmm_dcd #(
parameter NUM_OF_SAMPLES = 40,
parameter DIN_WIDTH = 4 // data in A and B
)(
input wire clk,
input wire req,
output reg ack,
input wire [7:0] deserial_data,
output reg [(log2(NUM_OF_SAMPLES * DIN_WIDTH))-1 :0] acc_a,
output reg [(log2(NUM_OF_SAMPLES * DIN_WIDTH))-1 :0] acc_b
);
// control states
localparam [1:0] STATE_IDLE = 2'b00;
localparam [1:0] STATE_RESET = 2'b01;
localparam [1:0] STATE_RUN = 2'b11;
localparam [1:0] STATE_ACK = 2'b10;
function integer log2;
input [31:0] value;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
endfunction
reg [DIN_WIDTH -1 :0] din_a_buf;
reg [DIN_WIDTH -1 :0] din_b_buf;
reg [(log2(DIN_WIDTH))-1 :0] sum_in_a;
reg [(log2(DIN_WIDTH))-1 :0] sum_in_b;
reg [1:0] state;
reg [(log2(NUM_OF_SAMPLES-1)-1):0] counter;
wire counter_tc;
wire acc_rst;
wire acc_ld;
reg [2:0] req_ff;
wire req_sync;
integer i;
// input buffers
always @(posedge clk)
begin
for (i=0; i<4; i=i+1)
begin
din_a_buf[i] <= deserial_data[2*i];
din_b_buf[i] <= deserial_data[(2*i) +1];
end
end
// sum of inputs A
always @(posedge clk)
begin
case (din_a_buf)
4'h0: sum_in_a <= 3'h0;
4'h1: sum_in_a <= 3'h1;
4'h2: sum_in_a <= 3'h1;
4'h3: sum_in_a <= 3'h2;
4'h4: sum_in_a <= 3'h1;
4'h5: sum_in_a <= 3'h2;
4'h6: sum_in_a <= 3'h2;
4'h7: sum_in_a <= 3'h3;
4'h8: sum_in_a <= 3'h1;
4'h9: sum_in_a <= 3'h2;
4'ha: sum_in_a <= 3'h2;
4'hb: sum_in_a <= 3'h3;
4'hc: sum_in_a <= 3'h2;
4'hd: sum_in_a <= 3'h3;
4'he: sum_in_a <= 3'h3;
4'hf: sum_in_a <= 3'h4;
endcase
end
// accumulator A
always @(posedge clk)
begin
if (acc_rst)
acc_a <= 'h0;
else if (acc_ld)
acc_a <= acc_a + sum_in_a;
end
// sum of inputs B
always @(posedge clk)
begin
case (din_b_buf)
4'h0: sum_in_b <= 3'h0;
4'h1: sum_in_b <= 3'h1;
4'h2: sum_in_b <= 3'h1;
4'h3: sum_in_b <= 3'h2;
4'h4: sum_in_b <= 3'h1;
4'h5: sum_in_b <= 3'h2;
4'h6: sum_in_b <= 3'h2;
4'h7: sum_in_b <= 3'h3;
4'h8: sum_in_b <= 3'h1;
4'h9: sum_in_b <= 3'h2;
4'ha: sum_in_b <= 3'h2;
4'hb: sum_in_b <= 3'h3;
4'hc: sum_in_b <= 3'h2;
4'hd: sum_in_b <= 3'h3;
4'he: sum_in_b <= 3'h3;
4'hf: sum_in_b <= 3'h4;
endcase
end
// accumulator B
always @(posedge clk)
begin
if (acc_rst)
acc_b <= 'h0;
else if (acc_ld)
acc_b <= acc_b + sum_in_b;
end
// control
always @(posedge clk)
begin
if (!req_sync)
state <= STATE_IDLE;
else
case (state)
STATE_IDLE: state <= STATE_RESET;
STATE_RESET: state <= STATE_RUN;
STATE_RUN: if (counter_tc)
state <= STATE_ACK;
STATE_ACK: state <= STATE_ACK;
default: state <= STATE_IDLE;
endcase
end
// state machine outputs
assign acc_rst = (state == STATE_RESET);
assign acc_ld = (state == STATE_RUN);
always @(posedge clk)
begin
if (!req_sync)
ack <= 1'b0;
else
ack <= (state == STATE_ACK);
end
// number of samples
always @(posedge clk)
begin
if (!acc_ld)
counter <= 'h0;
else
counter <= counter + 1'b1;
end
assign counter_tc = (counter == NUM_OF_SAMPLES -1);
// synchronize request
always @(posedge clk)
begin
req_ff <= {req_ff[1:0], req};
end
assign req_sync = req_ff[2];
endmodule |
module alt_xcvr_arbiter #(
parameter width = 2
) (
input wire clock,
input wire [width-1:0] req, // req[n] requests for this cycle
output reg [width-1:0] grant // grant[n] means requester n is grantee in this cycle
);
wire idle; // idle when no requests
wire [width-1:0] keep; // keep[n] means requester n is requesting, and already has the grant
// Note: current grantee is always highest priority for next grant
wire [width-1:0] take; // take[n] means requester n is requesting, and there are no higher-priority requests
assign keep = req & grant; // current grantee is always highest priority for next grant
assign idle = ~| req; // idle when no requests
initial begin
grant = 0;
end
// grant next state depends on current grant and take priority
always @(posedge clock) begin
grant <=
// synthesis translate_off
(grant === {width{1'bx}})? {width{1'b0}} :
// synthesis translate_on
keep // if current grantee is requesting, gets to keep grant
| ({width{idle}} & grant) // if no requests, grant state remains unchanged
| take; // take applies only if current grantee is not requesting
end
// 'take' bus encodes priority. Request with lowest bit number wins when current grantee not requesting
assign take[0] = req[0]
& (~| (keep & ({width{1'b1}} << 1))); // no 'keep' from lower-priority inputs
genvar i;
generate
for (i=1; i < width; i = i + 1) begin : arb
assign take[i] = req[i]
& (~| (keep & ({width{1'b1}} << (i+1)))) // no 'keep' from lower-priority inputs
& (~| (req & {i{1'b1}})); // no 'req' from higher-priority inputs
end
endgenerate
endmodule |
module sv_tx_pma_ch #(
parameter mode = 8,
parameter auto_negotiation = "false",
parameter plls = 1,
parameter pll_sel = 0,
parameter ser_loopback = "false",
parameter ht_delay_sel = "false",
parameter tx_pma_type = "SINGLE_CHANNEL",
parameter data_rate = "0 ps",
parameter rx_det_pdb = "true",
parameter tx_clk_div = 1, //(1,2,4,8)
parameter cgb_sync = "normal", //("normal","pcs_sync_rst","sync_rst")
parameter pcie_g3_x8 = "non_pcie_g3_x8", //("non_pcie_g3_x8","pcie_g3_x8")
parameter pll_feedback = "non_pll_feedback", //("non_pll_feedback","pll_feedback")
parameter reset_scheme = "non_reset_bonding_scheme", //("non_reset_bonding_scheme","reset_bonding_scheme")
parameter pcie_rst = "normal_reset", // PCS reset to be used for CGB in PCIe HIP configurations
parameter cal_clk_sel = "pm_aux_iqclk_cal_clk_sel_cal_clk", //Valid values: pm_aux_iqclk_cal_clk_sel_cal_clk|pm_aux_iqclk_cal_clk_sel_iqclk0|pm_aux_iqclk_cal_clk_sel_iqclk1|pm_aux_iqclk_cal_clk_sel_iqclk2|pm_aux_iqclk_cal_clk_sel_iqclk3|pm_aux_iqclk_cal_clk_sel_iqclk4|pm_aux_iqclk_cal_clk_sel_iqclk5|pm_aux_iqclk_cal_clk_sel_iqclk6|pm_aux_iqclk_cal_clk_sel_iqclk7|pm_aux_iqclk_cal_clk_sel_iqclk8|pm_aux_iqclk_cal_clk_sel_iqclk9|pm_aux_iqclk_cal_clk_sel_iqclk10
parameter fir_coeff_ctrl_sel = "ram_ctl", //Valid values: dynamic_ctl|ram_ctl
parameter pma_direct = "false" // ("true","false") PMA_DIRECT parameter
) (
//input port for aux
input calclk,
input [10: 0] refiqclk,
//input port for buf
input [79:0] datain,
input txelecidl,
input rxdetclk,
input txdetrx,
input [17:0] icoeff,
input txqpipulldn, // QPI input port
input txqpipullup, // QPI input port
//output port for buf
output dataout,
output rxdetectvalid,
output rxfound,
//input ports for ser
input rstn,
input pcs_rst_n,
input seriallpbken,
//output ports for ser
output clkdivtx,
output seriallpbkout,
//input ports for cgb
input [plls-1:0] clk,
input [1:0] pciesw,
input txpmasyncp,
// bonding clock inputs from master CGB
input cpulsein,
input hfclkpin,
input lfclkpin,
input [2:0] pclkin,
//output ports for cgb
output [1:0] pcieswdone,
output pcie_fb_clk, // PLL feedback clock for PCIe Gen3 x8
output pll_fb_sw, // PLL feedback clock select
// bonding clock outputs (driven if this CGB is acting as a master)
output hfclkpout,
output lfclkpout,
output cpulseout,
output [2:0] pclkout,
input avmmrstn,
input avmmclk,
input avmmwrite,
input avmmread,
input [1:0 ] avmmbyteen,
input [10:0 ] avmmaddress,
input [15:0 ] avmmwritedata,
output [15:0 ] avmmreaddata_cgb, // CGB readdata
output [15:0 ] avmmreaddata_ser, // SER readdata
output [15:0 ] avmmreaddata_buf, // BUF readdata
output blockselect_cgb, // CGB blockselect
output blockselect_ser, // SER blockselect
output blockselect_buf, // BUF blockselect
input vrlpbkp,
input vrlpbkn
);
localparam MAX_PLLS = 8;
localparam PLL_CNT = (plls < MAX_PLLS) ? plls : MAX_PLLS;
localparam integer is_single_chan = (tx_pma_type == "SINGLE_CHANNEL" ) ? 1 : 0;
localparam integer is_master_only = (tx_pma_type == "MASTER_ONLY" ) ? 1 : 0;
localparam integer is_master_chan = (tx_pma_type == "MASTER_SINGLE_CHANNEL") ? 1 : 0;
localparam integer is_slave_chan = (tx_pma_type == "SLAVE_CHANNEL" ) ? 1 : 0;
localparam integer is_empty_chan = (tx_pma_type == "EMPTY_CHANNEL" ) ? 1 : 0;
localparam integer is_fb_comp = (tx_pma_type == "FB_COMP_CHANNEL" ) ? 1 : 0;
// to support bonding
// Select clock source for g2/g3 and g1 based on auto_negotiation
localparam X1_CLOCK_SOURCE_SEL_AUTONEG =
(auto_negotiation == "true") ? "same_ch_txpll_g2_ch1_txpll_t_g3"
: (is_fb_comp == 1) ? "same_ch_txpll" // 5 - clk_cdr_loc
//: (pll_sel ==11) ? "hfclk_ch1_x6_up"// 9 - hfclkp_x6_up
//: (pll_sel ==10) ? "hfclk_xn_dn" // 8 - hfclkp_xn_dn
//: (pll_sel == 9) ? "hfclk_ch1_x6_dn"// 7 - hfclkp_x6_dn
//: (pll_sel == 8) ? "hfclk_xn_up" // 6 - hfclkp_xn_up
//: (pll_sel == 7) ? "down_segmented" // 1 - clk_dn_seg
//: (pll_sel == 6) ? "up_segmented" // 0 - clk_up_seg
//: (pll_sel == 5) ? "ffpll" // 2 - clk_ffpll
: (pll_sel == 4) ? "lcpll_bottom" // 11 - clk_lc_b
: (pll_sel == 3) ? "lcpll_top" // 10 - clk_lc_t
: (pll_sel == 2) ? "ch1_txpll_b" // 4 - clk_cdr_1b
: (pll_sel == 1) ? "ch1_txpll_t" // 3 - clk_cdr_1t
: (pll_sel == 0) ? "same_ch_txpll" // 5 - clk_cdr_loc
: "same_ch_txpll";
localparam X1_DIV_M_SEL = (tx_clk_div == 2) ? 2 :
(tx_clk_div == 4) ? 4 :
(tx_clk_div == 8) ? 8 :
1;
generate if(is_empty_chan == 0) begin:tx_pma_ch
wire [MAX_PLLS-1:0] wire_clk;
wire [79:0] w_datain;
wire w_txelecidl;
wire w_rxdetclk;
wire w_txdetrx;
wire cpulse_from_cgb;
wire hclk_from_cgb;
wire lfclk_from_cgb;
wire [2:0] pclk_from_cgb;
wire dataout_from_ser;
wire wire_hfclkpin;
wire wire_lfclkpin;
wire wire_cpulsein;
wire [2:0] wire_pclkin;
wire wire_hfclkpout;
wire wire_lfclkpout;
wire wire_cpulseout;
wire [2:0] wire_pclkout;
wire [1:0] w_pciesw;
// for bonding support
wire cpulse_from_cgb_master;
wire hclk_from_cgb_master ;
wire lfclk_from_cgb_master ;
wire [2:0] pclk_from_cgb_master ;
assign w_datain = (is_master_only == 0) ? datain : 80'd0;
assign w_txelecidl = (is_master_only == 0) ? txelecidl : 1'b0;
assign w_rxdetclk = (is_master_only == 0) ? rxdetclk : 1'b0;
assign w_txdetrx = (is_master_only == 0) ? txdetrx : 1'b0;
// Determine what drives the bonding lines input to the CGB
assign wire_hfclkpin = (is_single_chan == 1) ? 1'b0 :
(is_fb_comp == 1) ? wire_hfclkpout :
(is_master_chan == 1) ? wire_hfclkpout :
(is_master_only == 1) ? wire_hfclkpout :
hfclkpin ;
assign wire_lfclkpin = (is_single_chan == 1) ? 1'b0 :
(is_fb_comp == 1) ? wire_lfclkpout :
(is_master_chan == 1) ? wire_lfclkpout :
(is_master_only == 1) ? wire_lfclkpout :
lfclkpin ;
assign wire_cpulsein = (is_single_chan == 1) ? 1'b0 :
(is_fb_comp == 1) ? wire_cpulseout :
(is_master_chan == 1) ? wire_cpulseout :
(is_master_only == 1) ? wire_cpulseout :
cpulsein ;
assign wire_pclkin = (is_single_chan == 1) ? 3'b000 :
(is_fb_comp == 1) ? wire_pclkout :
(is_master_chan == 1) ? wire_pclkout :
(is_master_only == 1) ? wire_pclkout :
pclkin ;
// determine what drives the bonding lines output from this module
assign hfclkpout = (is_single_chan == 1) ? 1'b0 :
(is_slave_chan == 1) ? 1'b0 :
wire_hfclkpout;
assign lfclkpout = (is_single_chan == 1) ? 1'b0 :
(is_slave_chan == 1) ? 1'b0 :
wire_lfclkpout;
assign cpulseout = (is_single_chan == 1) ? 1'b0 :
(is_slave_chan == 1) ? 1'b0 :
wire_cpulseout;
assign pclkout = (is_single_chan == 1) ? 1'b0 :
(is_slave_chan == 1) ? 1'b0 :
wire_pclkout;
// determine what drives the HF clock input into CGB
assign wire_clk = (is_slave_chan == 1) ? {MAX_PLLS{1'b0}} // no clock can be connected in a slave mode
: {{(MAX_PLLS-PLL_CNT){1'b0}},clk}; // otherwise, connect the input clock
assign w_pciesw = (auto_negotiation == "false") ? 2'b00 : pciesw;
wire avmmrstn_master ;
wire avmmclk_master ;
wire avmmwrite_master ;
wire avmmread_master ;
wire [1:0] avmmbyteen_master ;
wire [10:0] avmmaddress_master ;
wire [15:0] avmmwritedata_master;
wire [15:0] avmmreaddata_master ;
wire blockselect_master ;
// Only connect CGB AVMM for non-bonded channels
assign avmmrstn_master = (is_single_chan == 1) ? avmmrstn : 1'd1 ;
assign avmmclk_master = (is_single_chan == 1) ? avmmclk : 1'd0 ;
assign avmmwrite_master = (is_single_chan == 1) ? avmmwrite : 1'd0 ;
assign avmmread_master = (is_single_chan == 1) ? avmmread : 1'd0 ;
assign avmmbyteen_master = (is_single_chan == 1) ? avmmbyteen : 2'd0 ;
assign avmmaddress_master = (is_single_chan == 1) ? avmmaddress : 11'd0 ;
assign avmmwritedata_master = (is_single_chan == 1) ? avmmwritedata : 16'd0 ;
stratixv_hssi_pma_tx_cgb #(
.mode (mode),
.auto_negotiation (auto_negotiation),
.data_rate (data_rate),
.pcie_rst (pcie_rst),
.x1_clock_source_sel (
((is_fb_comp == 1) ||
(is_single_chan == 1) ||
(is_master_chan == 1) ||
(is_master_only == 1)) ? X1_CLOCK_SOURCE_SEL_AUTONEG // corresponds to .clkcdrloc input
: "x1_clk_unused"), // a special setting when the front-end mux of the CGB is not used (SLAVE CHANNEL ONLY)
.xn_clock_source_sel (
((is_fb_comp == 1) ||
(is_master_chan == 1) ||
(is_slave_chan == 1) ||
(is_master_only == 1)) ? "xn_up" : // corresponds to *xnup ports
((is_single_chan == 1) && (ht_delay_sel == "true")) ? "cgb_ht"
: "cgb_x1_m_div"),
.x1_div_m_sel (X1_DIV_M_SEL),
// Attributes for PCIe Gen3
.cgb_sync (cgb_sync),
.clk_mute ("disable_clockmute"),
.pcie_g3_x8 (((is_master_only == 1) || (is_master_chan == 1) || (is_single_chan == 1)) ? pcie_g3_x8 : "non_pcie_g3_x8"),
.pll_feedback (pll_feedback),
.reset_scheme (reset_scheme)
) tx_cgb (
.rstn (rstn ),
`ifdef ALTERA_RESERVED_QIS_ES
.pcs_rst_n ( ), // float connection for ES as this is a production only signal
`else
.pcs_rst_n (pcs_rst_n ),
`endif
.clkcdrloc (wire_clk[0] ),
.clkcdr1t (wire_clk[1] ),
.clkcdr1b (wire_clk[2] ),
.clklct (wire_clk[3] ),
.clklcb (wire_clk[4] ),
.clkffpll (wire_clk[5] ),
.clkupseg (wire_clk[6] ),
.clkdnseg (wire_clk[7] ),
.pciesw (w_pciesw ),
.hfclkpxnup (wire_hfclkpin ),
.lfclkpxnup (wire_lfclkpin ),
.cpulsexnup (wire_cpulsein ),
.pclkxnup (wire_pclkin ),
// to serializer
.cpulse (cpulse_from_cgb_master ),
.hfclkp (hclk_from_cgb_master ),
.lfclkp (lfclk_from_cgb_master ),
.pclk (pclk_from_cgb_master ),
// when used as a CGB master, these are bonding clocks
.cpulseout (wire_cpulseout ),
.hfclkpout (wire_hfclkpout ),
.lfclkpout (wire_lfclkpout ),
.pclkout (wire_pclkout ),
.pcieswdone (pcieswdone ),
.pciefbclk (pcie_fb_clk ),
.pllfbsw (pll_fb_sw ),
.txpmasyncp (txpmasyncp ),
.avmmrstn (avmmrstn_master ),
.avmmclk (avmmclk_master ),
.avmmwrite (avmmwrite_master ),
.avmmread (avmmread_master ),
.avmmbyteen (avmmbyteen_master ),
.avmmaddress (avmmaddress_master ),
.avmmwritedata (avmmwritedata_master),
.avmmreaddata (avmmreaddata_master ),
.blockselect (blockselect_master )
`ifndef ALTERA_RESERVED_QIS
,
.hfclkn ( ),
.hfclknout ( ),
.lfclkn ( ),
.lfclknout ( ),
.rxiqclk ( ),
.fref (1'b0 ),
.rxclk (1'b0 ),
.clkbcdr1t (1'b0 ),
.clkbcdr1b (1'b0 ),
.clkbcdrloc (1'b0 ),
.clkbdnseg (1'b0 ),
.clkbffpll (1'b0 ),
.clkblcb (1'b0 ),
.clkblct (1'b0 ),
.clkbupseg (1'b0 ),
.cpulsex6up (1'b0 ),
.cpulsex6dn (1'b0 ),
.cpulsexndn (1'b0 ),
.hfclknx6up (1'b0 ),
.hfclknx6dn (1'b0 ),
.hfclknxndn (1'b0 ),
.hfclknxnup (1'b0 ),
.hfclkpx6up (1'b0 ),
.hfclkpx6dn (1'b0 ),
.hfclkpxndn (1'b0 ),
.lfclknx6up (1'b0 ),
.lfclknx6dn (1'b0 ),
.lfclknxndn (1'b0 ),
.lfclknxnup (1'b0 ),
.lfclkpx6up (1'b0 ),
.lfclkpx6dn (1'b0 ),
.lfclkpxndn (1'b0 ),
.pciesyncp (/*TODO*/ ),
.pclkx6up (3'b0 ),
.pclkx6dn (3'b0 ),
.pclkxndn (3'b0 )
`endif // ifndef ALTERA_RESERVED_QIS
);
// Outputs to AVMM
// If feedback compensation is not used, signals from CGB connect to/from the AVMM
assign avmmreaddata_cgb = (is_single_chan == 1) ? avmmreaddata_master: 16'd0 ;
assign blockselect_cgb = (is_single_chan == 1) ? blockselect_master : 1'd0 ;
if(is_fb_comp == 0) begin: tx_cgb_master
// Based on the bonding type, either the master or the slave CGB output ports will be connected to the Serializer.
// If the bonding type is not feedback compensation, then the master CGB output ports will be connected to the Serializer
assign cpulse_from_cgb = cpulse_from_cgb_master;
assign hclk_from_cgb = hclk_from_cgb_master ;
assign lfclk_from_cgb = lfclk_from_cgb_master ;
assign pclk_from_cgb = pclk_from_cgb_master ;
end else begin
wire cpulse_from_cgb_slave ;
wire hclk_from_cgb_slave ;
wire lfclk_from_cgb_slave ;
wire [2:0] pclk_from_cgb_slave ;
// slave CGB; This is cascaded to the Master CGB when feedback compensation bonding is used.
// The cpulseout, hfclkpout, lfclkpout, pclkout, pcieswdone, pciefbclk, pllfbsw, txpmasyncp are left unconnected
assign cpulse_from_cgb = cpulse_from_cgb_slave;
assign hclk_from_cgb = hclk_from_cgb_slave ;
assign lfclk_from_cgb = lfclk_from_cgb_slave ;
assign pclk_from_cgb = pclk_from_cgb_slave ;
stratixv_hssi_pma_tx_cgb #(
.mode (mode),
.auto_negotiation (auto_negotiation),
.data_rate (data_rate),
.x1_clock_source_sel ("x1_clk_unused"),
.xn_clock_source_sel ("xn_up"),
.x1_div_m_sel (X1_DIV_M_SEL),
.pcie_rst (pcie_rst),
// Attributes for PCIe Gen3
.cgb_sync (cgb_sync),
.clk_mute ("disable_clockmute"),
.pcie_g3_x8 (pcie_g3_x8),
.pll_feedback (pll_feedback),
.reset_scheme (reset_scheme)
)tx_cgb_slave (
.rstn (rstn ),
`ifdef ALTERA_RESERVED_QIS_ES
.pcs_rst_n ( ), // float connection for ES as this is a production only signal
`else
.pcs_rst_n (pcs_rst_n ),
`endif
.clkcdrloc (1'b0 ),
.clkcdr1t (1'b0 ),
.clkcdr1b (1'b0 ),
.clklct (1'b0 ),
.clklcb (1'b0 ),
.clkffpll (1'b0 ),
.clkupseg (1'b0 ),
.clkdnseg (1'b0 ),
.pciesw (w_pciesw ),
.hfclkpxnup (wire_hfclkpout ),
.lfclkpxnup (wire_lfclkpout ),
.cpulsexnup (wire_cpulseout ),
.pclkxnup (wire_pclkout ),
// to serializer
.cpulse (cpulse_from_cgb_slave ),
.hfclkp (hclk_from_cgb_slave ),
.lfclkp (lfclk_from_cgb_slave ),
.pclk (pclk_from_cgb_slave ),
// when used as a CGB master, these are bonding clocks
.cpulseout ( ),
.hfclkpout ( ),
.lfclkpout ( ),
.pclkout ( ),
.pcieswdone ( ),
.pciefbclk ( ),
.pllfbsw ( ),
.txpmasyncp ( ),
.avmmrstn (1'b1 ),
.avmmclk (1'b0 ),
.avmmwrite (1'b0 ),
.avmmread (1'b0 ),
.avmmbyteen (2'b00 ),
.avmmaddress (11'd0 ),
.avmmwritedata (16'd0 ),
.avmmreaddata (/*unused*/ ),
.blockselect (/*unused*/ )
`ifndef ALTERA_RESERVED_QIS
,
.hfclkn ( ),
.hfclknout ( ),
.lfclkn ( ),
.lfclknout ( ),
.rxiqclk ( ),
.fref (1'b0 ),
.rxclk (1'b0 ),
.clkbcdr1t (1'b0 ),
.clkbcdr1b (1'b0 ),
.clkbcdrloc (1'b0 ),
.clkbdnseg (1'b0 ),
.clkbffpll (1'b0 ),
.clkblcb (1'b0 ),
.clkblct (1'b0 ),
.clkbupseg (1'b0 ),
.cpulsex6up (1'b0 ),
.cpulsex6dn (1'b0 ),
.cpulsexndn (1'b0 ),
.hfclknx6up (1'b0 ),
.hfclknx6dn (1'b0 ),
.hfclknxndn (1'b0 ),
.hfclknxnup (1'b0 ),
.hfclkpx6up (1'b0 ),
.hfclkpx6dn (1'b0 ),
.hfclkpxndn (1'b0 ),
.lfclknx6up (1'b0 ),
.lfclknx6dn (1'b0 ),
.lfclknxndn (1'b0 ),
.lfclknxnup (1'b0 ),
.lfclkpx6up (1'b0 ),
.lfclkpx6dn (1'b0 ),
.lfclkpxndn (1'b0 ),
.pciesyncp (/*TODO*/ ),
.pclkx6up (3'b0 ),
.pclkx6dn (3'b0 ),
.pclkxndn (3'b0 )
`endif // ifndef ALTERA_RESERVED_QIS
);
end
stratixv_hssi_pma_tx_ser #(
.duty_cycle_tune ("duty_cycle4"), // iTrack 80215 - always use static setting of '4' for rser_dc_tune DCD compensation
.pma_direct (pma_direct),
.mode (mode),
.auto_negotiation (auto_negotiation),
.ser_loopback (ser_loopback),
.clk_forward_only_mode ((is_master_only == 1) ? "true" : "false")
) tx_pma_ser (
.cpulse (cpulse_from_cgb ),
.datain (w_datain ),
.hfclk (hclk_from_cgb ),
.lfclk (lfclk_from_cgb ),
.pclk (pclk_from_cgb ),
.pciesw (w_pciesw ),
.rstn (rstn ),
.clkdivtx (clkdivtx ),
.dataout (dataout_from_ser ),
.lbvop (seriallpbkout ),
.slpbk (seriallpbken ),
.hfclkn (1'b0 ),
.lfclkn (1'b0 ),
.lbvon (/*TODO*/ ),
.preenout (/*TODO*/ ),
.pciesyncp (/*TODO*/ ),
.avmmrstn (avmmrstn ),
.avmmclk (avmmclk ),
.avmmwrite (avmmwrite ),
.avmmread (avmmread ),
.avmmbyteen (avmmbyteen ),
.avmmaddress (avmmaddress ),
.avmmwritedata (avmmwritedata ),
.avmmreaddata (avmmreaddata_ser ),
.blockselect (blockselect_ser )
);
if (is_master_only == 0) begin:tx_pma_buf
wire nonuserfrompmaux;
stratixv_hssi_pma_aux #(
.cal_clk_sel (cal_clk_sel),
.continuous_calibration ("true"),
.rx_imp("cal_imp_52_ohm"),
.tx_imp("cal_imp_52_ohm")
) tx_pma_aux (
.calpdb (1'b1 ),
.calclk (calclk ),
.testcntl (/*unused*/ ),
.refiqclk (refiqclk ),
.nonusertoio (nonuserfrompmaux ),
.zrxtx50 (/*unused*/ )
);
stratixv_hssi_pma_tx_buf #(
.rx_det_pdb(rx_det_pdb),
.fir_coeff_ctrl_sel(fir_coeff_ctrl_sel)
) tx_pma_buf (
.nonuserfrompmaux (nonuserfrompmaux ),
.datain (dataout_from_ser ),
.rxdetclk (w_rxdetclk ),
.txdetrx (w_txdetrx ),
.txelecidl (w_txelecidl ),
.rxdetectvalid (rxdetectvalid ),
.dataout (dataout ),
.rxfound (rxfound ),
.txqpipulldn (txqpipulldn ), // QPI input port
.txqpipullup (txqpipullup ), // QPI input port
.fixedclkout (/*TODO*/ ),
.vrlpbkn (vrlpbkn ),
.vrlpbkp (vrlpbkp ),
.vrlpbkp1t (/*TODO*/ ),
.vrlpbkn1t (/*TODO*/ ),
.icoeff (icoeff ),
.avmmrstn (avmmrstn ),
.avmmclk (avmmclk ),
.avmmwrite (avmmwrite ),
.avmmread (avmmread ),
.avmmbyteen (avmmbyteen ),
.avmmaddress (avmmaddress ),
.avmmwritedata (avmmwritedata ),
.avmmreaddata (avmmreaddata_buf ),
.blockselect (blockselect_buf )
);
end // end of if (is_master_only == 0)
end else begin // if dummy_chan
// Warning avoidance
assign dataout = {1'b0,calclk,datain,txelecidl,rxdetclk,txdetrx,
rstn,seriallpbken,clk,pciesw,txpmasyncp,cpulsein,
hfclkpin,lfclkpin,pclkin,avmmrstn,avmmclk,avmmwrite,
avmmread,avmmbyteen,avmmaddress,avmmwritedata,
vrlpbkp,vrlpbkn};
assign rxdetectvalid = 1'b0;
assign rxfound = 1'b0;
assign clkdivtx = 1'b0;
assign seriallpbkout = 1'b0;
assign pcieswdone = 2'b00;
assign pcie_fb_clk = 1'b0;
assign pll_fb_sw = 1'b0;
assign hfclkpout = 1'b0;
assign lfclkpout = 1'b0;
assign cpulseout = 1'b0;
assign pclkout = 3'b000;
assign avmmreaddata_cgb = 16'd0;
assign avmmreaddata_ser = 16'd0;
assign avmmreaddata_buf = 16'd0;
assign blockselect_cgb = 1'b0;
assign blockselect_ser = 1'b0;
assign blockselect_buf = 1'b0;
end
endgenerate
initial begin
if( (tx_clk_div != 1) && (tx_clk_div != 2) && (tx_clk_div != 4) && (tx_clk_div != 8) ) begin
$display("Warning: parameter 'tx_clk_div' of instance '%m' has illegal value '%0d' assigned to it. Valid parameter values are: '1,2,4,8'. Using value '%0d'", tx_clk_div, X1_DIV_M_SEL);
end
end
endmodule |
module alt_xcvr_m2s #(
parameter width_addr = 3,
parameter width_data = 32
) (
input wire clock,
output wire req, // request to arbiter for slave access
input wire grant,
// signals from/to master
input wire m_read,
input wire m_write,
input wire [width_addr-1:0] m_address,
input wire [width_data-1:0] m_writedata,
output wire [width_data-1:0] m_readdata,
output wire m_waitrequest,
// signals from/to slave
output wire s_read,
output wire s_write,
output wire [width_addr-1:0] s_address,
output wire [width_data-1:0] s_writedata,
input wire [width_data-1:0] s_readdata,
input wire s_waitrequest
);
// If master is requesting access, generate waitreq until granted
assign req = m_read | m_write; // master access requests
assign m_waitrequest = grant ? s_waitrequest : req;
// gate outputs to slave with grant signal
assign s_read = m_read & grant;
assign s_write = m_write & grant;
assign s_address = m_address & {width_addr{grant}};
assign s_writedata = m_writedata & {width_data{grant}};
// slave data outputs pass through directly
assign m_readdata = s_readdata;
endmodule |
module csr_mux #(
parameter groups = 2,
parameter grp_size = 1,
parameter sel_size = 1
)
(
input wire [groups*grp_size-1:0] in_wide,
input tri0 [sel_size-1:0] sel,
output wire [grp_size-1:0] out_narrow
);
// lpm_mux #(.lpm_size(groups), .lpm_width(grp_size), .lpm_widths(sel_size))
// mux (.data(in_wide), .sel(sel), .result(out_narrow));
wire [grp_size-1:0] in_groups [groups-1:0];
// a synthesizable mux, with a parameterized number of inputs
genvar i;
assign in_groups[0] = in_wide[grp_size-1:0] & {grp_size{sel == 0}};
generate for (i=1; i<groups; i = i+1) begin: mux
assign in_groups[i] = in_groups[i-1] | in_wide[i*grp_size +: grp_size] & {grp_size{sel == i}};
end
endgenerate
assign out_narrow = in_groups[groups-1];
endmodule |
module csr_indexed_write_mux #(
parameter groups = 2,
parameter grp_size = 1,
parameter sel_size = 1,
parameter init_value = 0
)
(
input wire [grp_size-1:0] in_narrow,
input tri0 [sel_size-1:0] sel,
output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
input wire [groups*grp_size-1:0] in_wide, // full-width control reg state
output wire [groups*grp_size-1:0] out_wide // to write to full-width control reg
);
wire [groups*grp_size-1:0] wire_wide [groups-1:0];
// in_narrow is output in the group position indicated by .sel() input
genvar i;
assign wire_wide[0] = (in_wide & {grp_size{sel != 0}}) | (in_narrow & {grp_size{sel == 0}});
generate for (i=1; i<groups; i = i+1) begin: mux
assign wire_wide[i] = wire_wide[i-1]
| (in_wide & {{grp_size{sel != i}}, {(grp_size*i){1'b0}}})
| ({in_narrow & {grp_size{sel == i}}, {(grp_size*i){1'b0}}});
end
endgenerate
assign out_wide = wire_wide[groups-1];
// generate out_narrow as ordinary mux of in_wide
csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
o_narrow(.in_wide(in_wide), .sel(sel), .out_narrow(out_narrow));
endmodule |
module csr_indexed_read_only_reg #(
parameter groups = 2,
parameter grp_size = 1,
parameter sel_size = 1,
parameter sync_stages = 2
)
(
input wire clk,
input tri0 [sel_size-1:0] sel,
output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
input wire [groups*grp_size-1:0] async_in_wide // full-width async status inputs
);
localparam sync_stages_str = sync_stages[7:0] + 8'd48; // number of sync stages specified as string (for timing constraints)
localparam SYNC_SREG_CONSTRAINT = {"-name SDC_STATEMENT \"set regs [get_registers -nowarn *csr_indexed_read_only_reg*sreg[",sync_stages_str,"]*]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}\""};
localparam SDC_CONSTRAINTS = {SYNC_SREG_CONSTRAINT};
// read-only status registers are synchronized forms of async status signals
// async inputs go to sreg [sync_stages], and come out synchronized at sreg [1]
// Apply false path timing constraints to synchronization registers.
(* altera_attribute = SDC_CONSTRAINTS *)
reg [groups*grp_size-1:0] sreg [sync_stages:1];
integer stage;
always @(posedge clk) begin
sreg[sync_stages] <= async_in_wide;
for (stage=2; stage <= sync_stages; stage = stage + 1) begin
// additional sync stages
sreg[stage-1] <= sreg[stage];
end
end
// generate out_narrow as ordinary mux of out_wide
csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
o_narrow(.in_wide(sreg[1]), .sel(sel), .out_narrow(out_narrow));
endmodule |
module dut(clk, fifo_push, fullness_in);
parameter DEPTH = 4;
parameter DEPTH_BITS = 2; //0 is ilegal
input clk;
input wire fifo_push;
output reg [DEPTH-1:0] fullness_in;
reg [DEPTH_BITS-1:0] ptr_in;
always @(/*AUTOSENSE*/fifo_push or ptr_in)
begin
fullness_in = 4'b0;
fullness_in[ptr_in] = fifo_push;
end
endmodule |
module dut #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
(input wire clk,
input wire [CTRLW-1:0] ctrl,
input wire [DINW-1:0] din,
input wire [SELW-1:0] sel,
output reg [WIDTH-1:0] dout);
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk) begin
dout <= dout + 1;
dout[ctrl*sel+:SLICE] <= din ;
end
endmodule |
module module_scope_Example(o1);
parameter [31:0] v1 = 10;
output wire [31:0] o1;
assign module_scope_Example.o1 = module_scope_Example.v1;
endmodule |
module_scope_Example #(.v1(11)) a (a1);
endmodule |
module dut #(
parameter ENTSEL = 2,
parameter ENTNUM = 4
)
(
input logic clk,
input wire [ENTNUM-1:0] in,
output reg [ENTSEL-1:0] out,
output reg en
);
integer i;
always @ (*) begin
out = 0;
en = 0;
for (i = ENTNUM-1; i >= 0 ; i = i - 1) begin
if (in[i]) begin
out = i;
en = 1;
end
end
end
endmodule // search_from_top |
module I_BUF #(
parameter WEAK_KEEPER = "NONE",
parameter DRIVE = "STRONG"
) (
input logic I,
input logic EN,
output logic O
);
endmodule |
module dut(input logic clk, input logic I,
input logic EN,
output logic O1, O2);
I_BUF ibuf1(I, EN, O1);
I_BUF #(.WEAK_KEEPER("PULLUP")) ibuf2 (I, EN, O2);
endmodule |
module lms_ctr_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [13-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 13;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20 - 64'h0);
localparam PAD1 = log2ceil(64'h10000 - 64'h8000);
localparam PAD2 = log2ceil(64'h11000 - 64'h10800);
localparam PAD3 = log2ceil(64'h11020 - 64'h11000);
localparam PAD4 = log2ceil(64'h11040 - 64'h11020);
localparam PAD5 = log2ceil(64'h11060 - 64'h11040);
localparam PAD6 = log2ceil(64'h11080 - 64'h11060);
localparam PAD7 = log2ceil(64'h110a0 - 64'h11080);
localparam PAD8 = log2ceil(64'h110c0 - 64'h110a0);
localparam PAD9 = log2ceil(64'h110d0 - 64'h110c0);
localparam PAD10 = log2ceil(64'h110e0 - 64'h110d0);
localparam PAD11 = log2ceil(64'h110f0 - 64'h110e0);
localparam PAD12 = log2ceil(64'h110f8 - 64'h110f0);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h110f8;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [13-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x20 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 17'h0 ) begin
src_channel = 13'b1000000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x8000 .. 0x10000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 17'h8000 ) begin
src_channel = 13'b0000000010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x10800 .. 0x11000 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 17'h10800 ) begin
src_channel = 13'b0000000001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x11000 .. 0x11020 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 17'h11000 ) begin
src_channel = 13'b0100000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
end
// ( 0x11020 .. 0x11040 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 17'h11020 ) begin
src_channel = 13'b0010000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
end
// ( 0x11040 .. 0x11060 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 17'h11040 ) begin
src_channel = 13'b0001000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
end
// ( 0x11060 .. 0x11080 )
if ( {address[RG:PAD6],{PAD6{1'b0}}} == 17'h11060 ) begin
src_channel = 13'b0000100000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x11080 .. 0x110a0 )
if ( {address[RG:PAD7],{PAD7{1'b0}}} == 17'h11080 ) begin
src_channel = 13'b0000010000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12;
end
// ( 0x110a0 .. 0x110c0 )
if ( {address[RG:PAD8],{PAD8{1'b0}}} == 17'h110a0 ) begin
src_channel = 13'b0000000000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x110c0 .. 0x110d0 )
if ( {address[RG:PAD9],{PAD9{1'b0}}} == 17'h110c0 ) begin
src_channel = 13'b0000001000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x110d0 .. 0x110e0 )
if ( {address[RG:PAD10],{PAD10{1'b0}}} == 17'h110d0 && read_transaction ) begin
src_channel = 13'b0000000100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
end
// ( 0x110e0 .. 0x110f0 )
if ( {address[RG:PAD11],{PAD11{1'b0}}} == 17'h110e0 ) begin
src_channel = 13'b0000000000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x110f0 .. 0x110f8 )
if ( {address[RG:PAD12],{PAD12{1'b0}}} == 17'h110f0 && read_transaction ) begin
src_channel = 13'b0000000000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_router_005_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [81 - 78 : 0] default_destination_id,
output [13-1 : 0] default_wr_channel,
output [13-1 : 0] default_rd_channel,
output [13-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[81 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 13'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 13'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 13'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_005
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [13-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 13;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [13-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_005_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 13'b01;
end
if (destid == 1 && read_transaction) begin
src_channel = 13'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module read_stim
#(
parameter FILENAME = "output.log",
parameter LENGTH = 29
)
(
input clk,
input rst,
output signed [LENGTH-1:0] data,
output data_valid
);
integer input_file;
integer scan_file;
initial begin
input_file = $fopen(FILENAME, "r");
if (input_file == 0) begin
$display("ERROR opening file!!");
$finish;
end
end
logic [LENGTH-1:0] stim;
logic stim_valid;
initial begin
stim = 0;
stim_valid = 0;
wait(~rst);
while(!$feof(input_file)) begin
scan_file = $fscanf(input_file, "%d\n", stim);
stim_valid = 1;
@(posedge clk);
end
end
assign data = stim;
assign data_valid = stim_valid;
endmodule |
module log_data
#(
parameter FILENAME = "output.log",
parameter LENGTH = 29
)
(
input clk,
input rst,
input signed [LENGTH-1:0] data,
input data_valid
);
integer output_err_file;
initial begin
output_err_file = $fopen(FILENAME, "w");
end
always@(posedge clk) begin
if (rst) begin
end
else begin
if (data_valid) begin
$fwrite(output_err_file,"%d,",data);
end
end
end
endmodule |
module ethernet_tb(
);
// Clock definition
localparam CLK_PERIOD = 10; // 50 Mhz (counter is in ns)
localparam RST_COUNT = 10; //Clock cycles that reset is high
logic clk = 0;
logic rst;
always begin
clk = #(CLK_PERIOD/2) ~clk;
end
// reset definition
initial begin
rst = 1;
#(RST_COUNT*CLK_PERIOD);
@(posedge clk);
rst = 0;
end
logic lsfr_data;
logic lsfr_clk;
/*
// Gen input data
lfsr_8bit lfsr_8bit_i
(
.clk(lsfr_clk),
.rst(1'b0),
.clk_en(1'b1),
.data(lsfr_data)
);*/
read_stim
#(
.FILENAME("../../../../../tb/pdm_stimulus.txt"),
.LENGTH(1)
)
read_stim_i
(
.clk(lsfr_clk),
.rst(~rst),
.data(lsfr_data),
.data_valid()
);
ethernet_top ethernet_top_i
(
.CLK(clk),
.RST_N(~rst),
.M_CLK(lsfr_clk),
.M_DATA(lsfr_data),
.M_LRSEL()
);
log_data
#(
.FILENAME("output_mic_data.log"),
.LENGTH(32)
)
log_data_mic_data
(
.clk(clk),
.rst(rst),
.data(ethernet_tb.ethernet_top_i.mic_data),
.data_valid(ethernet_tb.ethernet_top_i.mic_data_valid)
);
endmodule |
module NexysBaseProject_top
(
input CLK,
input RST_N,
// // Switches
// input [15:0] SW,
input BTNC,
// input BTNU,
// input BTNL,
// input BTNR,
// input BTND,
// // PMOD headers
// // Can be both inputs and outputs
// // Set to input to be safe
// input [10:1] JA,
// input [10:1] JB,
// input [10:1] JC,
// input [10:1] JD,
// input [4:1] XA_N,
// input [4:1] XA_P,
// // LEDs
// output [15:0] LED,
// output LED16_B,
// output LED16_G,
// output LED16_R,
// output LED17_B,
// output LED17_G,
// output LED17_R,
// //7 segment display
// output CA,
// output CB,
// output CC,
// output CD,
// output CE,
// output CF,
// output CG,
// output DP,
// output [7:0] AN,
// // VGA
// output [3:0] VGA_R,
// output [3:0] VGA_G,
// output [3:0] VGA_B,
// output VGA_HS,
// output VGA_VS,
// // SD Card
// output SD_RESET,
// input SD_CD,
// inout SD_SCK,
// inout SD_CMD,
// inout [3:0] SD_DAT,
// // Accelerometer
// input ACL_MISO,
// output ACL_MOSI,
// output ACL_SCLK,
// output ACL_CSN,
// input [2:1] ACL_INT,
// // Temperature Sensor
// output TMP_SCL,
// inout TMP_SDA,
// input TMP_INT,
// input TMP_CT,
// // Microphone
// output M_CLK,
// input M_DATA,
// output M_LRSEL,
// // PWM Audio Amplifier
// output AUD_PWM,
// output AUD_SD,
// // UART
// input UART_TXD_IN,
// input UART_RTS,
// output UART_RXD_OUT,
// output UART_CTS,
// // USB HID
// inout PS2_CLK,
// inout PS2_DATA,
// // Ethernet
// output ETH_MDC,
// inout ETH_MDIO,
output ETH_RSTN,
// inout ETH_CRSDV,
// input ETH_RXERR,
// inout [1:0] ETH_RXD,
// output ETH_TXEN,
// output [1:0] ETH_TXD,
output ETH_REFCLK
// input ETH_INTN
// // QSPI Flash
// output QSPI_CSN,
// inout [3:0] QSPI_DQ
);
// Reset Generate
logic rst;
rst_gen rst_gen_i
(
.clk_in(CLK),
.rst_in(~RST_N),
.rst_out(rst)
);
// Ethernet clk and reset generate
logic eth_clk;
logic eth_rst;
eth_rst_gen eth_rst_gen_i
(
.clk(CLK),
.rst(rst),
.eth_clk_out(eth_clk),
.eth_rst_out(eth_rst),
.ETH_REFCLK(ETH_REFCLK),
.ETH_RSTN(ETH_RSTN)
);
// Debounce on buttons
logic btn_c_debounce;
logic btn_c_i;
logic count_en;
debounce debounce_sw
(
.clk(clk),
.rst(~rst_n),
.sw_in(BTNC),
.sw_out(btn_c_debounce)
);
edge_detect edge_detect_i
(
.clk(clk),
.rst(~rst_n),
.data_in(btn_c_debounce),
.data_out(btn_c_i)
);
endmodule |
module NexysBaseProject_tb
(
);
logic clk = 0;
logic rst = 1;
// Clock definition
localparam CLK_PERIOD = 10; // 100 Mhz (counter is in ns)
localparam RST_COUNT = 10; //Clock cycles that reset is high
always begin
clk = #(CLK_PERIOD/2) ~clk;
end
// reset definition
initial begin
rst = 1;
#(RST_COUNT*CLK_PERIOD);
@(posedge clk);
rst = 0;
end
// UUT
NexysBaseProject_top NexysBaseProject_top_i
(
.CLK(clk),
.RST_N(~rst)
);
endmodule |
module led_flash_tb(
);
logic clk = 0;
logic rst = 1;
// Clock definition
localparam CLK_PERIOD = 10; // 100 Mhz (counter is in ns)
localparam RST_COUNT = 10; //Clock cycles that reset is high
always begin
clk = #(CLK_PERIOD/2) ~clk;
end
// reset definition
initial begin
rst = 1;
#(RST_COUNT*CLK_PERIOD);
@(posedge clk);
rst = 0;
end
led_flash
led_flash_i(
.clk(clk),
.rst_n(~rst),
.led()
);
endmodule |
module ethernet_tb(
);
// Clock definition
localparam CLK_PERIOD = 10; // 50 Mhz (counter is in ns)
localparam RST_COUNT = 10; //Clock cycles that reset is high
logic clk = 0;
logic rst;
always begin
clk = #(CLK_PERIOD/2) ~clk;
end
// reset definition
initial begin
rst = 1;
#(RST_COUNT*CLK_PERIOD);
@(posedge clk);
rst = 0;
end
logic [7:0] lsfr_data;
logic lsfr_clk;
// Gen input data
lfsr_8bit lfsr_8bit_i
(
.clk(lsfr_clk),
.rst(1'b0),
.clk_en(1'b1),
.data(lsfr_data)
);
ethernet_top ethernet_top_i
(
.CLK(clk),
.RST_N(~rst),
.M_CLK(lsfr_clk),
.M_DATA(lsfr_data[0]),
.M_LRSEL()
);
endmodule |
module ethernet_tb(
);
// Clock definition
localparam CLK_PERIOD = 5; // 100 Mhz (counter is in ns)
localparam RST_COUNT = 10; //Clock cycles that reset is high
logic clk = 0;
logic rst;
always begin
clk = #(CLK_PERIOD/2) ~clk;
end
// reset definition
initial begin
rst = 1;
#(RST_COUNT*CLK_PERIOD);
@(posedge clk);
rst = 0;
end
ethernet_top ethernet_top_i(
.CLK(clk),
.RST_N(~rst)
);
endmodule |
module lfsr_4bit_tb(
);
logic clk = 0;
logic rst = 1;
logic led;
// Clock definition
localparam CLK_PERIOD = 20000; // 50 Mhz (counter is in ps)
localparam RST_COUNT = 10; //Clock cycles that reset is high
always begin
clk = #(CLK_PERIOD/2) ~clk;
end
// reset definition
initial begin
rst = 1;
#(RST_COUNT*CLK_PERIOD);
@(posedge clk);
rst = 0;
end
lfsr_4bit_top
lfsr_4bit_top_i
(
.clk(clk),
.rst(rst),
.led(led)
);
endmodule |
module uart
#(
parameter CLKRATE = 100000000,
parameter BAUD = 115200,
parameter WORD_LENGTH = 8
)
(
input clk,
input rst,
input [WORD_LENGTH-1:0] tx_data,
input tx_data_valid,
input tx_data_last,
output tx_data_ready,
output UART_TX
);
logic tx_data_fifo_m_axis_tlast;
logic tx_data_fifo_m_axis_tready;
logic tx_data_fifo_m_axis_tvalid;
logic [WORD_LENGTH-1:0] tx_data_fifo_m_axis_tdata;
tx_fifo
tx_data_fifo_i(
// unused
.wr_rst_busy(), // output wire wr_rst_busy
.rd_rst_busy(), // output wire rd_rst_busy
.s_aclk(clk), // input wire s_aclk
.s_aresetn(~rst), // input wire s_aresetn
// slave
.s_axis_tvalid(tx_data_valid), // input wire s_axis_tvalid
.s_axis_tready(tx_data_ready), // output wire s_axis_tready
.s_axis_tdata(tx_data), // input wire [7 : 0] s_axis_tdata
.s_axis_tlast(tx_data_last), // input wire s_axis_tlast
//master
.m_axis_tvalid(tx_data_fifo_m_axis_tvalid), // output wire m_axis_tvalid
.m_axis_tready(tx_data_fifo_m_axis_tready), // input wire m_axis_tready
.m_axis_tdata(tx_data_fifo_m_axis_tdata), // output wire [7 : 0] m_axis_tdata
.m_axis_tlast(tx_data_fifo_m_axis_tlast) // output wire m_axis_tlast
);
uart_tx
#(
.CLKRATE(CLKRATE),
.BAUD(BAUD),
.WORD_LENGTH(WORD_LENGTH)
)
uart_tx_i
(
.clk(clk),
.rst(rst),
.tx_data(tx_data_fifo_m_axis_tdata),
.tx_data_valid(tx_data_fifo_m_axis_tvalid),
.tx_data_ready(tx_data_fifo_m_axis_tready),
.UART_TX(UART_TX)
);
endmodule |
module sysmem_lite
(
input ramclk1_clk, // ramclk1.clk
input [28:0] ram1_address, // ram1.address
input [7:0] ram1_burstcount, // .burstcount
output ram1_waitrequest, // .waitrequest
output [63:0] ram1_readdata, // .readdata
output ram1_readdatavalid, // .readdatavalid
input ram1_read, // .read
input [63:0] ram1_writedata, // .writedata
input [7:0] ram1_byteenable, // .byteenable
input ram1_write, // .write
input ramclk2_clk, // ramclk2.clk
input [28:0] ram2_address, // ram2.address
input [7:0] ram2_burstcount, // .burstcount
output ram2_waitrequest, // .waitrequest
output [63:0] ram2_readdata, // .readdata
output ram2_readdatavalid, // .readdatavalid
input ram2_read, // .read
input [63:0] ram2_writedata, // .writedata
input [7:0] ram2_byteenable, // .byteenable
input ram2_write, // .write
output ctl_clock,
input reset_cold_req, // reset.cold_req
output reset_reset, // .reset
input reset_reset_req, // .reset_req
input reset_warm_req, // .warm_req
input vbuf_clk, // vbuf.clk
input [27:0] vbuf_address, // vbuf.address
input [7:0] vbuf_burstcount, // .burstcount
output vbuf_waitrequest, // .waitrequest
output [127:0] vbuf_readdata, // .readdata
output vbuf_readdatavalid, // .readdatavalid
input vbuf_read, // .read
input [127:0] vbuf_writedata, // .writedata
input [15:0] vbuf_byteenable, // .byteenable
input vbuf_write, // .write
input uart_cts, // uart.cts
input uart_dsr, // .dsr
input uart_dcd, // .dcd
input uart_ri, // .ri
output uart_dtr, // .dtr
output uart_rts, // .rts
output uart_out1_n, // .out1_n
output uart_out2_n, // .out2_n
input uart_rxd, // .rxd
output uart_txd // .txd
);
assign ctl_clock = clk_vip_clk;
wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps
wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
wire clk_vip_clk;
sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
.f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
.h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (vbuf_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (vbuf_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (vbuf_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (vbuf_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (vbuf_readdata), // .readdata
.f2h_sdram0_READDATAVALID (vbuf_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (vbuf_read), // .read
.f2h_sdram0_WRITEDATA (vbuf_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (vbuf_byteenable), // .byteenable
.f2h_sdram0_WRITE (vbuf_write), // .write
.f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount
.f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest
.f2h_sdram1_READDATA (ram1_readdata), // .readdata
.f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid
.f2h_sdram1_READ (ram1_read), // .read
.f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata
.f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable
.f2h_sdram1_WRITE (ram1_write), // .write
.f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk
.f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount
.f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest
.f2h_sdram2_READDATA (ram2_readdata), // .readdata
.f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid
.f2h_sdram2_READ (ram2_read), // .read
.f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata
.f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable
.f2h_sdram2_WRITE (ram2_write), // .write
.uart_cts (uart_cts),
.uart_dsr (uart_dsr),
.uart_dcd (uart_dcd),
.uart_ri (uart_ri),
.uart_dtr (uart_dtr),
.uart_rts (uart_rts),
.uart_out1_n (uart_out1_n),
.uart_out2_n (uart_out2_n),
.uart_rxd (uart_rxd),
.uart_txd (uart_txd)
);
reset_source reset_source (
.clk (clk_vip_clk), // clock.clk
.reset_hps (~hps_h2f_reset_reset), // reset_hps.reset
.reset_sys (), // reset_sys.reset
.cold_req (reset_cold_req), // reset_ctl.cold_req
.reset (reset_reset), // .reset
.reset_req (reset_reset_req), // .reset_req
.reset_vip (0), // .reset_vip
.warm_req (reset_warm_req), // .warm_req
.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
.reset_cold (reset_source_reset_cold_reset) // reset_cold.reset
);
endmodule |
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